From 1afb013dfe9cff72247a80279ab11925f3562134 Mon Sep 17 00:00:00 2001
From: coolsnowwolf <coolsnowwolf@gmail.com>
Date: Thu, 3 Jan 2019 17:26:06 +0800
Subject: [PATCH] Revert "kernel: bump 4.14 to 4.14.90"

This reverts commit e5d66977f754fd5b2554e7bd373912976809e677.
---
 include/kernel-version.mk                     |     4 +-
 target/linux/brcm2708/Makefile                |     2 +-
 target/linux/brcm2708/bcm2708/config-4.14     |   413 -
 target/linux/brcm2708/bcm2709/config-4.14     |   460 -
 target/linux/brcm2708/bcm2710/config-4.14     |   477 -
 target/linux/brcm2708/image/Makefile          |    25 +-
 target/linux/brcm2708/modules.mk              |   255 +-
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 ...e_resource-against-resources-without.patch |    28 -
 ...ent-spurious-interrupts-and-trap-the.patch |    27 -
 ...cm2836-Avoid-Invalid-trigger-warning.patch |    24 -
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 ...erlays-for-ADV7282M-OV5647-and-TC358.patch |   477 -
 ...-Set-premultiplied-for-alpha-formats.patch |    50 -
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 ...6-drm-vc4-Move-plane-state-to-header.patch |   157 -
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 ...s-Add-addr-parameter-to-i2c-rtc-gpio.patch |   111 -
 ...-dereferencing-DPI-s-connector-since.patch |    78 -
 ...-the-DPI-hardware-to-the-device-tree.patch |    34 -
 ...the-18-bit-DPI-pinmux-to-the-RPI-DTs.patch |    30 -
 ...overlay-for-the-Adafruit-Kippah-with.patch |    85 -
 ...stale-notes-about-vc4-s-CMA-alignmen.patch |    51 -
 ...rtise-supported-modifiers-for-planes.patch |    97 -
 ...ome-missing-HVS-register-definitions.patch |   149 -
 ...ing-formats-to-vc4_format_mod_suppor.patch |    33 -
 ...rm-vc4-Add-support-for-SAND-modifier.patch |   266 -
 ...e-GPIO-CSs-honour-the-SPI_NO_CS-flag.patch |    32 -
 ...rx-handling-before-first-packet-is-s.patch |    30 -
 ...an78xx-Fix-link-status-notifications.patch |    29 -
 ...61-overlays-Fix-vc4-kms-kippah-7inch.patch |    41 -
 ...Q-Fix-bad-mode-in-data-abort-handler.patch |   128 -
 ...-log-messages-in-one-newline-not-two.patch |    54 -
 ...e-log-message-ending-in-two-newlines.patch |    21 -
 .../950-0365-Add-rpi-poe-fan-driver.patch     |   615 -
 ...Pi-CM3-dts-to-arm64-mimic-the-RPi-3B.patch |    30 -
 ...camera-Skip-ISP-pass-to-eliminate-pa.patch |   231 -
 ...camera-Allocate-context-once-per-buf.patch |   192 -
 ...camera-Remove-bulk_mutex-as-it-is-no.patch |   154 -
 ...camera-Match-MMAL-buffer-count-to-V4.patch |   115 -
 ...camera-Remove-V4L2-MMAL-buffer-remap.patch |   239 -
 ...camera-Add-multiple-include-protecti.patch |    39 -
 ...5-camera-Move-struct-vchiq_mmal_rect.patch |    54 -
 ...camera-Replace-BUG_ON-with-return-er.patch |    41 -
 ...ing-bcm2835-camera-Fix-comment-typos.patch |    27 -
 ...835-camera-Fix-indentation-of-tables.patch |   321 -
 ...camera-Fix-warnings-about-string-ops.patch |    61 -
 ...Remove-dead-code-related-to-framerat.patch |    39 -
 ...Fix-mmal_port_parameter_get-signed-u.patch |    45 -
 ...80-staging-bcm2835-Use-BIT_ULL-macro.patch |    31 -
 ...vices-no-need-to-check-debugfs-retur.patch |   217 -
 ...vices-remove-odd-vchiq_debugfs_top-w.patch |   104 -
 ...vices-move-client-dbg-directory-into.patch |    94 -
 ...vices-remove-struct-vchiq_debugfs_in.patch |    63 -
 ...vices-vchiq_debugfs_log_entry-can-be.patch |    51 -
 ...vices-no-need-to-save-the-log-debufs.patch |    83 -
 ...services-Join-multiline-dereferences.patch |    60 -
 ...amera-Fix-timestamp-calculation-prob.patch |    93 -
 ...35-camera-use-ktime_t-for-timestamps.patch |    87 -
 ...ervices-Unsplit-user-visible-strings.patch |    53 -
 ...1-staging-vc04_services-Use-__func__.patch |    30 -
 ...camera-Do-not-bulk-receive-from-serv.patch |   197 -
 ...cm2835-camera-Return-early-on-errors.patch |   192 -
 ...5-camera-Remove-dead-email-addresses.patch |   241 -
 ...-camera-Fix-comment-style-violations.patch |   617 -
 ...-camera-Fix-spacing-around-operators.patch |   145 -
 ...5-camera-Reduce-length-of-enum-names.patch |   771 -
 ...camera-Fix-multiple-line-dereference.patch |   133 -
 ...cm2835-camera-Fix-brace-style-issues.patch |    56 -
 ...camera-Fix-missing-lines-between-ite.patch |    61 -
 ...camera-Fix-logical-continuation-spli.patch |    49 -
 ...camera-Fix-open-parenthesis-alignmen.patch |   137 -
 ...0403-staging-bcm2835-camera-Fix-typo.patch |    23 -
 ...camera-Ensure-all-buffers-are-return.patch |    82 -
 ...iq-Remove-check-of-the-number-of-buf.patch |    39 -
 ...camera-Handle-empty-EOS-buffers-whil.patch |    84 -
 ...camera-Set-sequence-number-correctly.patch |    46 -
 ...camera-Ensure-timestamps-never-go-ba.patch |    38 -
 ...upport-for-ADV7280-M-ADV7281-M-and-A.patch |   134 -
 ...0410-bcm2835-interpolate-audio-delay.patch |    90 -
 ...audioinjector.net-ultra-soundcard.-2.patch |   141 -
 .../950-0412-PoE-HAT-driver-cleanup.patch     |   245 -
 ...oC-cs4265-Add-a-S-PDIF-enable-switch.patch |    26 -
 ...s4265-Add-native-32bit-I2S-transport.patch |    29 -
 ...ET_DTR-quirk-to-the-SIMCOM-shared-de.patch |    45 -
 ...0-0416-configs-Add-SENSOR_GPIO_FAN-m.patch |    55 -
 ...0417-BCM270X_DT-Add-gpio-fan-overlay.patch |   114 -
 ...ays-Correct-DT-handling-camera-GPIOs.patch |    75 -
 ...-ov5647-Use-gpiod_set_value_cansleep.patch |    54 -
 ...fix-incorrect-DMA-register-offset-ca.patch |    63 -
 ...2-configs-Add-CONFIG_HID_BIGBEN_FF-m.patch |    33 -
 ...SoC-cs4265-Add-a-MIC-pre.-route-2696.patch |    34 -
 ...mplement-a-DMA-pool-for-small-bulk-t.patch |   126 -
 ...425-Update-gpio-fan-overlay.dts-2711.patch |    72 -
 ...step_wise-add-support-for-hysteresis.patch |    96 -
 ...step_wise-avoid-throttling-at-hyster.patch |    22 -
 ...just-rpi-poe-fan-overlay-trip-points.patch |    67 -
 ...dd-overrides-for-PoE-HAT-fan-control.patch |    50 -
 ...erlays-Add-gpio-no-bank0-irq-overlay.patch |    60 -
 ...-2017-model-device-tree-overlay-2721.patch |   209 -
 ...50-0432-config-Add-CONFIG_USBIP_VUDC.patch |    31 -
 ...sdhost-Recover-from-MMC_SEND_EXT_CSD.patch |    50 -
 ...cm2835-Recover-from-MMC_SEND_EXT_CSD.patch |    50 -
 ...i3-disable-bt-Clear-out-bt_pins-node.patch |    33 -
 ...23-properly-handle-oscillator-stop-b.patch |    56 -
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 ...is7xx-Don-t-spin-if-no-data-received.patch |    23 -
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 ...0X_DT-Add-new-Ethernet-DT-parameters.patch |    55 -
 ...camera-Fix-stride-on-RGB3-BGR3-forma.patch |    53 -
 ...pm-Make-SECURITYFS-a-weak-dependency.patch |    35 -
 ...PI-support-for-TPM1.2-and-TPM2.0-chi.patch |   106 -
 ...ay-for-SLB9760-Iridium-LetsTrust-TPM.patch |    92 -
 ...driver-for-3Dlab-Nano-soundcard-2758.patch |   505 -
 ...-audio-fix-sgtl5000-compatible-strin.patch |    27 -
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 ...e-link-events-to-minimize-poll-storm.patch |    44 -
 .../960-add-rasbperrypi-compatible.patch      |    51 -
 .../patches-4.14/961-lan78xx-enable-LED.patch |    18 -
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 ...inal-flags-for-every-struct-mtd_info.patch |    58 -
 ...ulating-partition-boundaries-when-ch.patch |    55 -
 ...ddress-assignment-via-ifconfig-ioctl.patch |    79 -
 ...writing-to-wrong-PCI-registers-after.patch |    74 -
 ...hecksum-indirection-to-struct-nf_ipv.patch |     2 +-
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 ...-saveroute-indirection-in-struct-nf_.patch |     4 +-
 ...oute-indirection-to-struct-nf_ipv6_o.patch |     2 +-
 ...eroute-indirection-to-struct-nf_ipv6.patch |     6 +-
 ...-route_key_size-field-in-struct-nf_a.patch |     2 +-
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 ...s-trigger-Introduce-a-NETDEV-trigger.patch |   588 -
 ...linking-of-inodes-correctly-while-re.patch |    89 -
 .../generic/hack-4.14/902-debloat_proc.patch  |     2 +-
 .../pending-4.14/834-ledtrig-libata.patch     |     8 +-
 target/linux/layerscape/Makefile              |     2 +-
 target/linux/layerscape/README                |     4 +-
 .../armv7/{config-4.14 => config-4.9}         |   294 +-
 .../armv8_32b/{config-4.14 => config-4.9}     |   413 +-
 .../armv8_64b/{config-4.14 => config-4.9}     |   380 +-
 target/linux/layerscape/image/armv7.mk        |    16 -
 target/linux/layerscape/image/armv8_32b.mk    |     3 +-
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 target/linux/layerscape/modules.mk            |     3 +-
 .../201-config-support-layerscape.patch       |   301 -
 .../202-core-linux-support-layerscape.patch   |   741 -
 .../301-arch-support-layerscape.patch         |   325 -
 .../302-dts-support-layerscape.patch          |  6848 --
 ...s1021a-Add-LS1021A-IOT-board-support.patch |   289 -
 .../701-dpaa2-dpio-support-layerscape.patch   |  2415 -
 ...02-dpaa2-ethernet-support-layerscape.patch |  8094 --
 ...03-dpaa2-l2switch-support-layerscape.patch |  4040 -
 ...704-dpaa2-mac-phy-support-layerscape.patch |  1888 -
 .../705-dpaa2-rtc-support-layerscape.patch    |  1367 -
 ...aa2-virtualbridge-support-layerscape.patch |  3256 -
 .../711-dpaa-bqman-support-layerscape.patch   |   550 -
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 .../814-ls2-console-support-layerscape.patch  |   316 -
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 .../816-pcie-support-layerscape.patch         |   596 -
 ...platform-security-support-layerscape.patch |  1443 -
 .../818-qspi-support-layerscape.patch         |   774 -
 .../819-sdhc-support-layerscape.patch         |   147 -
 .../820-sec-support-layerscape.patch          | 13093 ----
 .../821-smmu-support-layerscape.patch         |   506 -
 .../822-uart-support-layerscape.patch         |    52 -
 ...hc-add-voltage-switch-support-for-ls.patch |    23 -
 .../201-config-support-layerscape.patch       |   374 +
 .../202-core-linux-support-layerscape.patch   |  1458 +
 .../301-arch-support-layerscape.patch         |   517 +
 .../302-dts-support-layercape.patch           | 10549 +++
 ...-dts-layerscape-add-traverse-ls1043.patch} |    23 +-
 .../401-mtd-spi-nor-support-layerscape.patch  |   993 +
 .../402-mtd-support-layerscape.patch}         |    76 +-
 .../701-sdk_dpaa-support-layerscape.patch}    |  1905 +-
 .../702-pci-support-layerscape.patch          |  2098 +
 .../703-phy-support-layerscape.patch}         |   378 +-
 .../704-fsl-mc-layerscape-support.patch}      | 11947 ++-
 .../705-dpaa2-support-layerscape.patch        | 23038 ++++++
 .../706-fsl_ppfe-support-layercape.patch}     |   304 +-
 .../801-ata-support-layerscape.patch          |   144 +
 .../802-clk-support-layerscape.patch          |   323 +
 .../803-cpufreq-support-layerscape.patch}     |   366 +-
 .../804-crypto-support-layerscape.patch       | 29223 ++++++++
 .../805-dma-support-layerscape.patch}         |  1456 +-
 .../806-flextimer-support-layerscape.patch}   |   103 +-
 .../807-gpu-support-layerscape.patch          |    58 +
 .../808-guts-support-layerscape.patch         |   421 +
 .../809-i2c-support-layerscape.patch}         |    49 +-
 .../810-iommu-support-layerscape.patch        |  1671 +
 .../811-irqchip-support-layerscape.patch      |   182 +
 .../812-mmc-layerscape-support.patch          |   594 +
 .../813-qe-support-layerscape.patch}          |    99 +-
 .../814-rtc-support-layerscape.patch}         |   114 +-
 .../815-spi-support-layerscape.patch          |   427 +
 .../816-tty-serial-support-layerscape.patch   |   162 +
 .../817-usb-support-layerscape.patch}         |   922 +-
 .../818-vfio-support-layerscape.patch}        |   115 +-
 .../819-flexcan-support-layerscape.patch}     |   335 +-
 .../820-kvm-support-layerscape.patch}         |   193 +-
 .../821-add-esdhc-vsel-to-ls1043.patch        |    10 +
 .../822-rgmii-fixed-link.patch}               |     6 +-
 .../oxnas/patches-4.14/999-libata-hacks.patch |     4 +-
 547 files changed, 85992 insertions(+), 208304 deletions(-)
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 delete mode 100644 target/linux/brcm2708/patches-4.14/950-0411-Add-support-for-audioinjector.net-ultra-soundcard.-2.patch
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 delete mode 100644 target/linux/brcm2708/patches-4.14/950-0437-Update-issue-templates-2736.patch
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 mode change 100755 => 100644
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 delete mode 100644 target/linux/layerscape/patches-4.14/824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch
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 create mode 100644 target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch
 create mode 100644 target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch
 rename target/linux/layerscape/{patches-4.14/303-add-DTS-for-Traverse-LS1043-Boards.patch => patches-4.9/303-dts-layerscape-add-traverse-ls1043.patch} (75%)
 create mode 100644 target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
 rename target/linux/layerscape/{patches-4.14/813-ifc-nor-nand-support-layerscape.patch => patches-4.9/402-mtd-support-layerscape.patch} (86%)
 rename target/linux/layerscape/{patches-4.14/707-dpaa-ethernet-support-layerscape.patch => patches-4.9/701-sdk_dpaa-support-layerscape.patch} (99%)
 create mode 100644 target/linux/layerscape/patches-4.9/702-pci-support-layerscape.patch
 rename target/linux/layerscape/{patches-4.14/709-mdio-phy-support-layerscape.patch => patches-4.9/703-phy-support-layerscape.patch} (78%)
 rename target/linux/layerscape/{patches-4.14/708-mc-bus-support-layerscape.patch => patches-4.9/704-fsl-mc-layerscape-support.patch} (52%)
 create mode 100644 target/linux/layerscape/patches-4.9/705-dpaa2-support-layerscape.patch
 rename target/linux/layerscape/{patches-4.14/710-pfe-eth-support-layerscape.patch => patches-4.9/706-fsl_ppfe-support-layercape.patch} (97%)
 create mode 100644 target/linux/layerscape/patches-4.9/801-ata-support-layerscape.patch
 create mode 100644 target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch
 rename target/linux/layerscape/{patches-4.14/823-pm-support-layerscape.patch => patches-4.9/803-cpufreq-support-layerscape.patch} (71%)
 create mode 100644 target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch
 rename target/linux/layerscape/{patches-4.14/802-dma-support-layerscape.patch => patches-4.9/805-dma-support-layerscape.patch} (82%)
 rename target/linux/layerscape/{patches-4.14/803-flextimer-support-layerscape.patch => patches-4.9/806-flextimer-support-layerscape.patch} (72%)
 create mode 100644 target/linux/layerscape/patches-4.9/807-gpu-support-layerscape.patch
 create mode 100644 target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch
 rename target/linux/layerscape/{patches-4.14/804-i2c-support-layerscape.patch => patches-4.9/809-i2c-support-layerscape.patch} (88%)
 create mode 100644 target/linux/layerscape/patches-4.9/810-iommu-support-layerscape.patch
 create mode 100644 target/linux/layerscape/patches-4.9/811-irqchip-support-layerscape.patch
 create mode 100644 target/linux/layerscape/patches-4.9/812-mmc-layerscape-support.patch
 rename target/linux/layerscape/{patches-4.14/805-qe-support-layerscape.patch => patches-4.9/813-qe-support-layerscape.patch} (95%)
 rename target/linux/layerscape/{patches-4.14/806-rtc-support-layerscape.patch => patches-4.9/814-rtc-support-layerscape.patch} (83%)
 create mode 100644 target/linux/layerscape/patches-4.9/815-spi-support-layerscape.patch
 create mode 100644 target/linux/layerscape/patches-4.9/816-tty-serial-support-layerscape.patch
 rename target/linux/layerscape/{patches-4.14/807-usb-support-layerscape.patch => patches-4.9/817-usb-support-layerscape.patch} (62%)
 rename target/linux/layerscape/{patches-4.14/808-vfio-support-layerscape.patch => patches-4.9/818-vfio-support-layerscape.patch} (89%)
 rename target/linux/layerscape/{patches-4.14/809-flexcan-support-layerscape.patch => patches-4.9/819-flexcan-support-layerscape.patch} (63%)
 rename target/linux/layerscape/{patches-4.14/810-kvm-support-layerscape.patch => patches-4.9/820-kvm-support-layerscape.patch} (59%)
 create mode 100644 target/linux/layerscape/patches-4.9/821-add-esdhc-vsel-to-ls1043.patch
 rename target/linux/layerscape/{patches-4.14/712-sdk-dpaa-rgmii-fixed-link.patch => patches-4.9/822-rgmii-fixed-link.patch} (90%)

diff --git a/include/kernel-version.mk b/include/kernel-version.mk
index e80987972..ed740ff1b 100644
--- a/include/kernel-version.mk
+++ b/include/kernel-version.mk
@@ -4,12 +4,12 @@ LINUX_RELEASE?=1
 
 LINUX_VERSION-3.18 = .130
 LINUX_VERSION-4.9 = .146
-LINUX_VERSION-4.14 = .90
+LINUX_VERSION-4.14 = .89
 LINUX_VERSION-4.19 = .9
 
 LINUX_KERNEL_HASH-3.18.130 = d1bf85ed3fd0067b1134178ed5492ae0053cb3fdd5361986fe0b85234fc82723
 LINUX_KERNEL_HASH-4.9.146 = 58195a8be3085d117c83a2ed1caa3b46ea7c1614c75f951b9f13f7adb03f8e59
-LINUX_KERNEL_HASH-4.14.90 = 0c1ed0c93085e44ad89cd279647b0e4617d06ce5a482213b5481b612ffa186ca
+LINUX_KERNEL_HASH-4.14.89 = ce6e16ac44dddd0d6a232bf2ce03e8bf8beca19f9b84503684466d140a1a0b25
 LINUX_KERNEL_HASH-4.19.9 = fc116cc6829c73944215d3b3ac0fc368dde9e8235b456744afffde001269dbf2
 
 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
diff --git a/target/linux/brcm2708/Makefile b/target/linux/brcm2708/Makefile
index 6b1991bce..3032b9ffd 100644
--- a/target/linux/brcm2708/Makefile
+++ b/target/linux/brcm2708/Makefile
@@ -14,7 +14,7 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu squashfs
 MAINTAINER:=Álvaro Fernández Rojas <noltari@gmail.com>
 SUBTARGETS:=bcm2708 bcm2709 bcm2710
 
-KERNEL_PATCHVER:=4.14
+KERNEL_PATCHVER:=4.9
 
 define Target/Description
 	Build firmware image for Broadcom BCM27xx SoC devices.
diff --git a/target/linux/brcm2708/bcm2708/config-4.14 b/target/linux/brcm2708/bcm2708/config-4.14
deleted file mode 100644
index cc563edac..000000000
--- a/target/linux/brcm2708/bcm2708/config-4.14
+++ /dev/null
@@ -1,413 +0,0 @@
-# CONFIG_AIO is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM2835=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_BCM2835_CPUFREQ=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_ERRATA_411920=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_ARM_UNWIND=y
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BCM2708_VCMEM=y
-# CONFIG_BCM2835_DEVGPIOMEM is not set
-CONFIG_BCM2835_FAST_MEMCPY=y
-CONFIG_BCM2835_MBOX=y
-# CONFIG_BCM2835_SMI is not set
-CONFIG_BCM2835_THERMAL=y
-CONFIG_BCM2835_TIMER=y
-CONFIG_BCM2835_VCHIQ=y
-# CONFIG_BCM2835_VCHIQ_SUPPORT_MEMDUMP is not set
-CONFIG_BCM2835_WDT=y
-CONFIG_BCM_VCIO=y
-CONFIG_BCM_VC_SM=y
-CONFIG_BCM_VIDEOCORE=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BRCM_CHAR_DRIVERS=y
-CONFIG_BUILD_BIN2C=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_PM=y
-# CONFIG_CPU_THERMAL is not set
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_BCM2708=y
-CONFIG_DMA_BCM2835=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-CONFIG_F2FS_FS=y
-# CONFIG_F2FS_FS_SECURITY is not set
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_BCM2708=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
-# CONFIG_FB_RPISENSE is not set
-CONFIG_FIQ=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_FPE_NWFPE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-# CONFIG_GPIO_BCM_EXP is not set
-# CONFIG_GPIO_BCM_VIRT is not set
-CONFIG_GPIO_SYSFS=y
-# CONFIG_GRO_CELLS is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-# CONFIG_HAVE_ARCH_BITREVERSE is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-# CONFIG_I2C_BCM2708 is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_INPUT=y
-CONFIG_LIBFDT=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_MAC_PARTITION=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MAX_RAW_DEVS=256
-# CONFIG_MDIO_BUS is not set
-CONFIG_MEMORY_ISOLATION=y
-# CONFIG_MFD_RPISENSE_CORE is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-# CONFIG_MMC_BCM2835 is not set
-CONFIG_MMC_BCM2835_DMA=y
-CONFIG_MMC_BCM2835_MMC=y
-CONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2
-CONFIG_MMC_BCM2835_SDHOST=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NLS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_OABI_COMPAT=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_CONFIGFS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_NET=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PCI_DOMAINS_GENERIC is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_BCM2835=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PWM=y
-CONFIG_PWM_BCM2835=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_RASPBERRYPI_POWER=y
-CONFIG_RATIONAL=y
-CONFIG_RAW_DRIVER=y
-# CONFIG_RCU_NEED_SEGCBLIST is not set
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SCHED_INFO is not set
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SERIAL_8250_BCM2835AUX=y
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=0
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWIOTLB=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_UEVENT_HELPER_PATH=""
-# CONFIG_UID16 is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWCOTG=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_NET_SMSC95XX=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UAS=y
-CONFIG_USB_USBNET=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/target/linux/brcm2708/bcm2709/config-4.14 b/target/linux/brcm2708/bcm2709/config-4.14
deleted file mode 100644
index ef49952eb..000000000
--- a/target/linux/brcm2708/bcm2709/config-4.14
+++ /dev/null
@@ -1,460 +0,0 @@
-# CONFIG_AIO is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM2835=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_BCM2835_CPUFREQ=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_LPAE is not set
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BCM2708_VCMEM=y
-# CONFIG_BCM2835_DEVGPIOMEM is not set
-CONFIG_BCM2835_MBOX=y
-# CONFIG_BCM2835_SMI is not set
-CONFIG_BCM2835_THERMAL=y
-CONFIG_BCM2835_TIMER=y
-CONFIG_BCM2835_VCHIQ=y
-# CONFIG_BCM2835_VCHIQ_SUPPORT_MEMDUMP is not set
-CONFIG_BCM2835_WDT=y
-CONFIG_BCM_VCIO=y
-CONFIG_BCM_VC_SM=y
-CONFIG_BCM_VIDEOCORE=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BRCM_CHAR_DRIVERS=y
-CONFIG_BUILD_BIN2C=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-# CONFIG_CPU_THERMAL is not set
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_BCM2708=y
-CONFIG_DMA_BCM2835=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-CONFIG_F2FS_FS=y
-# CONFIG_F2FS_FS_SECURITY is not set
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_BCM2708=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
-# CONFIG_FB_RPISENSE is not set
-CONFIG_FIQ=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_FPE_NWFPE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FREEZER=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_BCM_EXP=y
-CONFIG_GPIO_BCM_VIRT=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_GRO_CELLS is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARM_ARCH_TIMER=y
-CONFIG_HAVE_ARM_SMCCC=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_OPTPROBES=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_UID16=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-# CONFIG_I2C_BCM2708 is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_INPUT=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_MAC_PARTITION=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEMORY_ISOLATION=y
-# CONFIG_MFD_RPISENSE_CORE is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MICROCHIP_PHY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-# CONFIG_MMC_BCM2835 is not set
-CONFIG_MMC_BCM2835_DMA=y
-CONFIG_MMC_BCM2835_MMC=y
-CONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2
-CONFIG_MMC_BCM2835_SDHOST=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD is not set
-CONFIG_MULTI_IRQ_HANDLER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_OABI_COMPAT=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_CONFIGFS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0x80000000
-# CONFIG_PCI_DOMAINS_GENERIC is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_BCM2835=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PWM=y
-CONFIG_PWM_BCM2835=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_RASPBERRYPI_POWER=y
-CONFIG_RATIONAL=y
-CONFIG_RAW_DRIVER=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SCHED_INFO is not set
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SERIAL_8250_BCM2835AUX=y
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=0
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UEVENT_HELPER_PATH=""
-# CONFIG_UID16 is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWCOTG=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_LAN78XX=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_NET_SMSC95XX=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UAS=y
-CONFIG_USB_USBNET=y
-CONFIG_USE_OF=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VMSPLIT_2G=y
-# CONFIG_VMSPLIT_3G is not set
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/target/linux/brcm2708/bcm2710/config-4.14 b/target/linux/brcm2708/bcm2710/config-4.14
deleted file mode 100644
index 289ec68df..000000000
--- a/target/linux/brcm2708/bcm2710/config-4.14
+++ /dev/null
@@ -1,477 +0,0 @@
-CONFIG_64BIT=y
-# CONFIG_AIO is not set
-CONFIG_ARCH_BCM2835=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
-CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
-CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
-CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
-CONFIG_ARCH_HAS_KCOV=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
-CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
-CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
-CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
-CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
-CONFIG_ARCH_WANT_FRAME_POINTERS=y
-CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
-CONFIG_ARM64=y
-# CONFIG_ARM64_16K_PAGES is not set
-CONFIG_ARM64_4K_PAGES=y
-# CONFIG_ARM64_64K_PAGES is not set
-CONFIG_ARM64_CONT_SHIFT=4
-# CONFIG_ARM64_CRYPTO is not set
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_HW_AFDBM=y
-# CONFIG_ARM64_LSE_ATOMICS is not set
-CONFIG_ARM64_MODULE_CMODEL_LARGE=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-# CONFIG_ARM64_PMEM is not set
-# CONFIG_ARM64_PTDUMP_CORE is not set
-# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
-# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
-CONFIG_ARM64_SSBD=y
-# CONFIG_ARM64_SW_TTBR0_PAN is not set
-CONFIG_ARM64_UAO=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-# CONFIG_ARM64_VA_BITS_48 is not set
-CONFIG_ARM64_VHE=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_BCM2835_CPUFREQ=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_SP805_WATCHDOG is not set
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BCM2708_VCMEM=y
-# CONFIG_BCM2835_DEVGPIOMEM is not set
-CONFIG_BCM2835_MBOX=y
-# CONFIG_BCM2835_SMI is not set
-CONFIG_BCM2835_THERMAL=y
-CONFIG_BCM2835_VCHIQ=y
-# CONFIG_BCM2835_VCHIQ_SUPPORT_MEMDUMP is not set
-CONFIG_BCM2835_WDT=y
-# CONFIG_BCM_FLEXRM_MBOX is not set
-# CONFIG_BCM_VCIO is not set
-# CONFIG_BCM_VC_SM is not set
-CONFIG_BCM_VIDEOCORE=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_SCSI_REQUEST=y
-CONFIG_BOUNCE=y
-CONFIG_BRCM_CHAR_DRIVERS=y
-CONFIG_BUILD_BIN2C=y
-CONFIG_CAVIUM_ERRATUM_22375=y
-CONFIG_CAVIUM_ERRATUM_23154=y
-CONFIG_CAVIUM_ERRATUM_27456=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_XGENE=y
-# CONFIG_COMPAT is not set
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-# CONFIG_CPUFREQ_DT is not set
-# CONFIG_CPU_BIG_ENDIAN is not set
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-# CONFIG_CPU_THERMAL is not set
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-CONFIG_CRYPTO_NULL2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_BCM2708=y
-CONFIG_DMA_BCM2835=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-# CONFIG_F2FS_CHECK_FS is not set
-CONFIG_F2FS_FS=y
-# CONFIG_F2FS_FS_SECURITY is not set
-CONFIG_F2FS_FS_XATTR=y
-CONFIG_F2FS_STAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_BCM2708=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
-# CONFIG_FB_RPISENSE is not set
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FREEZER=y
-CONFIG_FSL_ERRATUM_A008585=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_BCM_EXP=y
-CONFIG_GPIO_BCM_VIRT=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_GRO_CELLS is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
-CONFIG_HAVE_ARCH_AUDITSYSCALL=y
-CONFIG_HAVE_ARCH_BITREVERSE=y
-CONFIG_HAVE_ARCH_HUGE_VMAP=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KASAN=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_PFN_VALID=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
-CONFIG_HAVE_ARM_SMCCC=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CC_STACKPROTECTOR=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CLK_PREPARE=y
-CONFIG_HAVE_CMPXCHG_DOUBLE=y
-CONFIG_HAVE_CMPXCHG_LOCAL=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_BUGVERBOSE=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_EBPF_JIT=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_GUP=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_PATA_PLATFORM=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_PERF_REGS=y
-CONFIG_HAVE_PERF_USER_STACK_DUMP=y
-CONFIG_HAVE_RCU_TABLE_FREE=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_HOTPLUG_CPU=y
-# CONFIG_HUGETLBFS is not set
-CONFIG_HW_CONSOLE=y
-CONFIG_I2C=y
-# CONFIG_I2C_BCM2708 is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_INPUT=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_MAC_PARTITION=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MEMORY_ISOLATION=y
-# CONFIG_MFD_RPISENSE_CORE is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MICROCHIP_PHY=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-# CONFIG_MMC_BCM2835 is not set
-CONFIG_MMC_BCM2835_DMA=y
-CONFIG_MMC_BCM2835_MMC=y
-CONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2
-CONFIG_MMC_BCM2835_SDHOST=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MTD is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NO_BOOTMEM=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-# CONFIG_NUMA is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_CONFIGFS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESERVED_MEM=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PARTITION_PERCPU=y
-# CONFIG_PCI_DOMAINS is not set
-# CONFIG_PCI_DOMAINS_GENERIC is not set
-# CONFIG_PCI_SYSCALL is not set
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_BCM2835=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PWM=y
-CONFIG_PWM_BCM2835=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_RANDOMIZE_BASE is not set
-CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_RASPBERRYPI_POWER=y
-CONFIG_RATIONAL=y
-CONFIG_RAW_DRIVER=y
-CONFIG_RCU_NEED_SEGCBLIST=y
-CONFIG_RCU_STALL_COMMON=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_SCHED_INFO is not set
-CONFIG_SCSI=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SERIAL_8250_BCM2835AUX=y
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=0
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_SUPPORTS_HUGETLBFS=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWCOTG=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_LAN78XX=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_NET_SMSC95XX=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UAS=y
-CONFIG_USB_USBNET=y
-CONFIG_VMAP_STACK=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
diff --git a/target/linux/brcm2708/image/Makefile b/target/linux/brcm2708/image/Makefile
index f2d8cec32..aedea9445 100644
--- a/target/linux/brcm2708/image/Makefile
+++ b/target/linux/brcm2708/image/Makefile
@@ -29,10 +29,8 @@ define Build/boot-img
 	mcopy -i $@.boot $(KDIR)/LICENCE.broadcom ::
 	mcopy -i $@.boot $(KDIR)/start.elf ::
 	mcopy -i $@.boot $(KDIR)/start_cd.elf ::
-	mcopy -i $@.boot $(KDIR)/start_x.elf ::
 	mcopy -i $@.boot $(KDIR)/fixup.dat ::
 	mcopy -i $@.boot $(KDIR)/fixup_cd.dat ::
-	mcopy -i $@.boot $(KDIR)/fixup_x.dat ::
 	mcopy -i $@.boot cmdline.txt ::
 	mcopy -i $@.boot config.txt ::
 	mcopy -i $@.boot $(IMAGE_KERNEL) ::$(KERNEL_IMG)
@@ -59,12 +57,8 @@ endef
 define Device/rpi
   DEVICE_TITLE := Raspberry Pi B/B+/CM/Zero/ZeroW
   DEVICE_DTS := bcm2708-rpi-b bcm2708-rpi-b-plus bcm2708-rpi-cm bcm2708-rpi-0-w
-  SUPPORTED_DEVICES := \
-	rpi-b rpi-b-plus rpi-cm rpi-zero rpi-zero-w \
-	raspberrypi,model-b raspberrypi,model-b-plus raspberrypi,model-b-rev2 \
-	raspberrypi,compute-module raspberrypi,compute-module-1 \
-	raspberrypi,model-zero raspberrypi,model-zero-w
-  DEVICE_PACKAGES := brcmfmac-firmware-43430-sdio brcmfmac-board-rpi2 kmod-brcmfmac wpad-basic
+  SUPPORTED_DEVICES := rpi-b rpi-b-plus rpi-cm rpi-zero rpi-zero-w raspberrypi,model-b raspberrypi,model-b-plus raspberrypi,compute-module-1 raspberrypi,model-b-rev2 raspberrypi,model-zero raspberrypi,model-zero-w
+  DEVICE_PACKAGES := brcmfmac-firmware-43430-sdio brcmfmac-board-rpi2 kmod-brcmfmac wpad-mini
 endef
 ifeq ($(SUBTARGET),bcm2708)
   TARGET_DEVICES += rpi
@@ -73,12 +67,8 @@ endif
 define Device/rpi-2
   DEVICE_TITLE := Raspberry Pi 2B/3B/3B+/3CM
   DEVICE_DTS := bcm2709-rpi-2-b bcm2710-rpi-3-b bcm2710-rpi-3-b-plus bcm2710-rpi-cm3
-  SUPPORTED_DEVICES := \
-	rpi-2-b rpi-3-b rpi-3-b-plus rpi-cm \
-	raspberrypi,2-model-b \
-	raspberrypi,3-model-b raspberrypi,3-model-b-plus \
-	raspberrypi,3-compute-module raspberrypi,compute-module-3
-  DEVICE_PACKAGES := brcmfmac-firmware-43430-sdio brcmfmac-firmware-43455-sdio brcmfmac-board-rpi2 brcmfmac-board-rpi3 kmod-brcmfmac wpad-basic
+  SUPPORTED_DEVICES := rpi-2-b rpi-3-b rpi-3-b-plus rpi-cm raspberrypi,2-model-b raspberrypi,3-model-b raspberrypi,3-model-b-plus raspberrypi,compute-module-3
+  DEVICE_PACKAGES := brcmfmac-firmware-43430-sdio brcmfmac-firmware-43455-sdio brcmfmac-board-rpi2 brcmfmac-board-rpi3 kmod-brcmfmac wpad-mini
 endef
 ifeq ($(SUBTARGET),bcm2709)
   TARGET_DEVICES += rpi-2
@@ -88,11 +78,8 @@ define Device/rpi-3
   KERNEL_IMG := kernel8.img
   DEVICE_TITLE := Raspberry Pi 3B/3B+
   DEVICE_DTS := broadcom/bcm2710-rpi-3-b broadcom/bcm2710-rpi-3-b-plus
-  SUPPORTED_DEVICES := \
-	rpi-3-b rpi-3-b-plus \
-	raspberrypi,3-model-b raspberrypi,3-model-b-plus \
-	raspberrypi,3-compute-module raspberrypi,compute-module-3
-  DEVICE_PACKAGES := brcmfmac-firmware-43430-sdio brcmfmac-board-rpi2 brcmfmac-firmware-43455-sdio brcmfmac-board-rpi3 kmod-brcmfmac wpad-basic
+  SUPPORTED_DEVICES := rpi-3-b rpi-3-b-plus raspberrypi,3-model-b raspberrypi,3-model-b-plus
+  DEVICE_PACKAGES := brcmfmac-firmware-43430-sdio brcmfmac-board-rpi2 brcmfmac-firmware-43455-sdio brcmfmac-board-rpi3 kmod-brcmfmac wpad-mini
 endef
 ifeq ($(SUBTARGET),bcm2710)
   TARGET_DEVICES += rpi-3
diff --git a/target/linux/brcm2708/modules.mk b/target/linux/brcm2708/modules.mk
index 9a5e7c297..47738abd4 100644
--- a/target/linux/brcm2708/modules.mk
+++ b/target/linux/brcm2708/modules.mk
@@ -8,13 +8,8 @@
 define KernelPackage/drm-vc4
   SUBMENU:=$(VIDEO_MENU)
   TITLE:=Broadcom VC4 Graphics
-  DEPENDS:= \
-	@TARGET_brcm2708 +kmod-drm \
-	+LINUX_4_14:kmod-sound-core \
-	+LINUX_4_14:kmod-sound-soc-core
-  KCONFIG:= \
-	CONFIG_DRM_VC4 \
-	CONFIG_DRM_VC4_HDMI_CEC=n
+  DEPENDS:=@TARGET_brcm2708 +kmod-drm
+  KCONFIG:=CONFIG_DRM_VC4
   FILES:= \
 	$(LINUX_DIR)/drivers/gpu/drm/vc4/vc4.ko \
 	$(LINUX_DIR)/drivers/gpu/drm/drm_kms_helper.ko
@@ -28,23 +23,6 @@ endef
 
 $(eval $(call KernelPackage,drm-vc4))
 
-
-define KernelPackage/hwmon-rpi-poe-fan
-  SUBMENU:=$(HWMON_MENU)
-  TITLE:=Raspberry Pi PoE HAT fan
-  DEPENDS:=@TARGET_brcm2708 @LINUX_4_14 +kmod-hwmon-core
-  KCONFIG:=CONFIG_SENSORS_RPI_POE_FAN
-  FILES:=$(LINUX_DIR)/drivers/hwmon/rpi-poe-fan.ko
-  AUTOLOAD:=$(call AutoProbe,rpi-poe-fan)
-endef
-
-define KernelPackage/hwmon-rpi-poe-fan/description
-  Raspberry Pi PoE HAT fan driver
-endef
-
-$(eval $(call KernelPackage,hwmon-rpi-poe-fan))
-
-
 define KernelPackage/sound-arm-bcm2835
   TITLE:=BCM2835 ALSA driver
   KCONFIG:= \
@@ -52,8 +30,7 @@ define KernelPackage/sound-arm-bcm2835
 	CONFIG_SND_BCM2835 \
 	CONFIG_SND_ARMAACI=n
   FILES:= \
-	$(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-audio/snd-bcm2835.ko@ge4.12 \
-	$(LINUX_DIR)/sound/arm/snd-bcm2835.ko@lt4.12
+	$(LINUX_DIR)/sound/arm/snd-bcm2835.ko
   AUTOLOAD:=$(call AutoLoad,68,snd-bcm2835)
   DEPENDS:=@TARGET_brcm2708
   $(call AddDepends/sound)
@@ -85,24 +62,6 @@ endef
 
 $(eval $(call KernelPackage,sound-soc-bcm2835-i2s))
 
-
-define KernelPackage/sound-soc-3dlab-nano-player
-  TITLE:=Support for 3Dlab Nano Player
-  KCONFIG:= CONFIG_SND_BCM2708_SOC_3DLAB_NANO_PLAYER
-  FILES:=$(LINUX_DIR)/sound/soc/bcm/snd-soc-3dlab-nano-player.ko
-  AUTOLOAD:=$(call AutoLoad,68,snd-soc-3dlab-nano-player)
-  DEPENDS:= \
-	@LINUX_4_14 \
-	kmod-sound-soc-bcm2835-i2s
-endef
-
-define KernelPackage/sound-soc-3dlab-nano-player/description
-  This package contains support for 3Dlab Nano Player
-endef
-
-$(eval $(call KernelPackage,sound-soc-3dlab-nano-player))
-
-
 define KernelPackage/sound-soc-adau1977-adc
   TITLE:=Support for ADAU1977 ADC
   KCONFIG:= \
@@ -127,59 +86,6 @@ endef
 
 $(eval $(call KernelPackage,sound-soc-adau1977-adc))
 
-
-define KernelPackage/sound-soc-allo-boss-dac
-  TITLE:=Support for Allo Boss DAC
-  KCONFIG:= \
-	CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC \
-	CONFIG_SND_SOC_PCM512x \
-	CONFIG_SND_SOC_PCM512x_I2C
-  FILES:= \
-	$(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-boss-dac.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko
-  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x-i2c snd-soc-pcm512x \
-	snd-soc-allo-boss-dac)
-  DEPENDS:= \
-	@LINUX_4_14 \
-	+kmod-i2c-bcm2708 \
-	kmod-sound-soc-bcm2835-i2s
-  $(call AddDepends/sound)
-endef
-
-define KernelPackage/sound-soc-allo-boss-dac/description
-  This package contains support for Allo Boss DAC
-endef
-
-$(eval $(call KernelPackage,sound-soc-allo-boss-dac))
-
-
-define KernelPackage/sound-soc-allo-digione
-  TITLE:=Support for Allo Piano DigiOne
-  KCONFIG:= \
-	CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE \
-	CONFIG_SND_SOC_PCM512x \
-	CONFIG_SND_SOC_PCM512x_I2C
-  FILES:= \
-	$(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-digione.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko
-  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x-i2c snd-soc-pcm512x \
-	snd-soc-allo-digione)
-  DEPENDS:= \
-	@LINUX_4_14 \
-	+kmod-i2c-bcm2708 \
-	kmod-sound-soc-bcm2835-i2s
-  $(call AddDepends/sound)
-endef
-
-define KernelPackage/sound-soc-allo-digione/description
-  This package contains support for Allo DigiOne
-endef
-
-$(eval $(call KernelPackage,sound-soc-allo-digione))
-
-
 define KernelPackage/sound-soc-allo-piano-dac
   TITLE:=Support for Allo Piano DAC
   KCONFIG:= \
@@ -204,88 +110,6 @@ endef
 
 $(eval $(call KernelPackage,sound-soc-allo-piano-dac))
 
-
-define KernelPackage/sound-soc-allo-piano-dac-plus
-  TITLE:=Support for Allo Piano DAC Plus
-  KCONFIG:= \
-	CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS \
-	CONFIG_SND_SOC_PCM512x \
-	CONFIG_SND_SOC_PCM512x_I2C
-  FILES:= \
-	$(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-piano-dac-plus.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko
-  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x-i2c snd-soc-pcm512x \
-	snd-soc-allo-piano-dac-plus)
-  DEPENDS:= \
-	@LINUX_4_14 \
-	+kmod-i2c-bcm2708 \
-	kmod-sound-soc-bcm2835-i2s
-  $(call AddDepends/sound)
-endef
-
-define KernelPackage/sound-soc-allo-piano-dac-plus/description
-  This package contains support for Allo Piano DAC Plus
-endef
-
-$(eval $(call KernelPackage,sound-soc-allo-piano-dac-plus))
-
-
-define KernelPackage/sound-soc-allo-katana-codec
-  TITLE:=Support for Allo Katana DAC
-  KCONFIG:= \
-	CONFIG_SND_AUDIO_GRAPH_CARD \
-	CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC \
-	CONFIG_SND_SOC_PCM512x \
-	CONFIG_SND_SOC_PCM512x_I2C \
-	CONFIG_SND_SIMPLE_CARD_UTILS
-  FILES:= \
-	$(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-katana-codec.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko
-  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x-i2c snd-soc-pcm512x \
-	snd-soc-allo-katana-codec)
-  DEPENDS:= \
-	@LINUX_4_14 \
-	+kmod-i2c-bcm2708 \
-	+kmod-regmap \
-	kmod-sound-soc-bcm2835-i2s
-  $(call AddDepends/sound)
-endef
-
-define KernelPackage/sound-soc-allo-katana-codec/description
-  This package contains support for Allo Katana DAC
-endef
-
-$(eval $(call KernelPackage,sound-soc-allo-katana-codec))
-
-
-define KernelPackage/sound-soc-audioinjector-octo-soundcard
-  TITLE:=Support for AudioInjector Octo soundcard
-  KCONFIG:= \
-	CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD \
-	CONFIG_SND_SOC_CS42XX8 \
-	CONFIG_SND_SOC_CS42XX8_I2C
-  FILES:= \
-	$(LINUX_DIR)/sound/soc/bcm/snd-soc-audioinjector-octo-soundcard.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-cs42xx8.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-cs42xx8-i2c.ko
-  AUTOLOAD:=$(call AutoLoad,68,snd-soc- \
-	snd-soc-audioinjector-octo-soundcard)
-  DEPENDS:= \
-	@LINUX_4_14 \
-	+kmod-i2c-bcm2708 \
-	kmod-sound-soc-bcm2835-i2s
-  $(call AddDepends/sound)
-endef
-
-define KernelPackage/sound-soc-audioinjector-octo-soundcard/description
-  This package contains support for AudioInjector Octo soundcard
-endef
-
-$(eval $(call KernelPackage,sound-soc-audioinjector-octo-soundcard))
-
-
 define KernelPackage/sound-soc-audioinjector-pi-soundcard
   TITLE:=Support for AudioInjector Pi soundcard
   KCONFIG:= \
@@ -400,30 +224,6 @@ endef
 
 $(eval $(call KernelPackage,sound-soc-fe-pi))
 
-
-define KernelPackage/sound-soc-googlevoicehat
-  TITLE:=Support for Google VoiceHAT Sound Card
-  KCONFIG:= \
-	CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD \
-	CONFIG_SND_SOC_VOICEHAT
-  FILES:= \
-	$(LINUX_DIR)/sound/soc/bcm/snd-soc-googlevoicehat-codec.ko \
-	$(LINUX_DIR)/sound/soc/bcm/snd-soc-googlevoicehat-soundcard.ko
-  AUTOLOAD:=$(call AutoLoad,68,snd-soc-googlevoicehat-codec \
-	snd-soc-googlevoicehat-soundcard)
-  DEPENDS:= \
-	@LINUX_4_14 \
-	kmod-sound-soc-bcm2835-i2s
-  $(call AddDepends/sound)
-endef
-
-define KernelPackage/sound-soc-googlevoicehat/description
-  This package contains support for Google VoiceHAT Sound Card
-endef
-
-$(eval $(call KernelPackage,sound-soc-googlevoicehat))
-
-
 define KernelPackage/sound-soc-hifiberry-dac
   TITLE:=Support for HifiBerry DAC
   KCONFIG:= \
@@ -635,7 +435,6 @@ define KernelPackage/sound-soc-raspidac3
   AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x snd-soc-pcm512x-i2c \
 	snd-soc-tpa6130a2 snd-soc-raspidac3)
   DEPENDS:= \
-	@LINUX_4_9 \
 	kmod-sound-soc-bcm2835-i2s \
 	+kmod-i2c-bcm2708
   $(call AddDepends/sound)
@@ -647,48 +446,6 @@ endef
 
 $(eval $(call KernelPackage,sound-soc-raspidac3))
 
-
-define KernelPackage/sound-soc-rpi-cirrus
-  TITLE:=Support for Cirrus Logic Audio Card
-  KCONFIG:= \
-	CONFIG_GPIO_ARIZONA \
-	CONFIG_INPUT_ARIZONA_HAPTICS=n \
-	CONFIG_MFD_ARIZONA=y \
-	CONFIG_MFD_ARIZONA_I2C \
-	CONFIG_MFD_CS47L24=n \
-	CONFIG_MFD_WM5102=n \
-	CONFIG_MFD_WM5110=n \
-	CONFIG_MFD_WM8997=n \
-	CONFIG_MFD_WM8998=n \
-	CONFIG_REGULATOR_ARIZONA \
-	CONFIG_REGULATOR_ARIZONA_LDO1 \
-	CONFIG_REGULATOR_ARIZONA_MICSUPP \
-	CONFIG_SND_BCM2708_SOC_RPI_CIRRUS \
-	CONFIG_SND_SOC_ARIZONA \
-	CONFIG_SND_SOC_WM5102 \
-	CONFIG_SND_SOC_WM8804 \
-	CONFIG_SND_SOC_WM_ADSP
-  FILES:= \
-	$(LINUX_DIR)/sound/soc/bcm/snd-soc-rpi-cirrus.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-arizona.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-wm-adsp.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-wm5102.ko \
-	$(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko
-  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm1794a snd-soc-rpi-cirrus)
-  DEPENDS:= \
-	@LINUX_4_14 \
-	+kmod-i2c-bcm2708 \
-	kmod-sound-soc-bcm2835-i2s
-  $(call AddDepends/sound)
-endef
-
-define KernelPackage/sound-soc-rpi-cirrus/description
-  This package contains support for RPi-Cirrus
-endef
-
-$(eval $(call KernelPackage,sound-soc-rpi-cirrus))
-
-
 define KernelPackage/sound-soc-rpi-dac
   TITLE:=Support for RPi-DAC
   KCONFIG:= \
@@ -870,11 +627,9 @@ $(eval $(call KernelPackage,i2c-bcm2835))
 define KernelPackage/video-bcm2835
   TITLE:=Broadcom BCM2835 camera interface driver
   KCONFIG:= \
-	CONFIG_VIDEO_BCM2835$(if $(CONFIG_LINUX_4_9),=y) \
+	CONFIG_VIDEO_BCM2835=y \
 	CONFIG_VIDEO_BCM2835_MMAL
-  FILES:= \
-	$(LINUX_DIR)/drivers/media/platform/bcm2835/bcm2835-v4l2.ko@lt4.12 \
-	$(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-camera/bcm2835-v4l2.ko@ge4.12
+  FILES:= $(LINUX_DIR)/drivers/media/platform/bcm2835/bcm2835-v4l2.ko
   AUTOLOAD:=$(call AutoLoad,65,bcm2835-v4l2)
   $(call AddDepends/video,@TARGET_brcm2708 +kmod-video-videobuf2)
 endef
diff --git a/target/linux/brcm2708/patches-4.14/950-0001-arm-partially-revert-702b94bff3c50542a6e4ab9a4f4cef0.patch b/target/linux/brcm2708/patches-4.14/950-0001-arm-partially-revert-702b94bff3c50542a6e4ab9a4f4cef0.patch
deleted file mode 100644
index 7becfb3d9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0001-arm-partially-revert-702b94bff3c50542a6e4ab9a4f4cef0.patch
+++ /dev/null
@@ -1,99 +0,0 @@
-From a45a0eb188581a6c1f57b7adc4f66f5754927ad3 Mon Sep 17 00:00:00 2001
-From: Dan Pasanen <dan.pasanen@gmail.com>
-Date: Thu, 21 Sep 2017 09:55:42 -0500
-Subject: [PATCH 001/454] arm: partially revert
- 702b94bff3c50542a6e4ab9a4f4cef093262fe65
-
-* Re-expose some dmi APIs for use in VCSM
----
- arch/arm/include/asm/cacheflush.h | 21 +++++++++++++++++++++
- arch/arm/include/asm/glue-cache.h |  2 ++
- arch/arm/mm/proc-macros.S         |  2 ++
- arch/arm/mm/proc-syms.c           |  3 +++
- 4 files changed, 28 insertions(+)
-
---- a/arch/arm/include/asm/cacheflush.h
-+++ b/arch/arm/include/asm/cacheflush.h
-@@ -94,6 +94,21 @@
-  *	DMA Cache Coherency
-  *	===================
-  *
-+ *	dma_inv_range(start, end)
-+ *
-+ *		Invalidate (discard) the specified virtual address range.
-+ *		May not write back any entries.  If 'start' or 'end'
-+ *		are not cache line aligned, those lines must be written
-+ *		back.
-+ *		- start  - virtual start address
-+ *		- end    - virtual end address
-+ *
-+ *	dma_clean_range(start, end)
-+ *
-+ *		Clean (write back) the specified virtual address range.
-+ *		- start  - virtual start address
-+ *		- end    - virtual end address
-+ *
-  *	dma_flush_range(start, end)
-  *
-  *		Clean and invalidate the specified virtual address range.
-@@ -115,6 +130,8 @@ struct cpu_cache_fns {
- 	void (*dma_map_area)(const void *, size_t, int);
- 	void (*dma_unmap_area)(const void *, size_t, int);
- 
-+	void (*dma_inv_range)(const void *, const void *);
-+	void (*dma_clean_range)(const void *, const void *);
- 	void (*dma_flush_range)(const void *, const void *);
- } __no_randomize_layout;
- 
-@@ -140,6 +157,8 @@ extern struct cpu_cache_fns cpu_cache;
-  * is visible to DMA, or data written by DMA to system memory is
-  * visible to the CPU.
-  */
-+#define dmac_inv_range			cpu_cache.dma_inv_range
-+#define dmac_clean_range		cpu_cache.dma_clean_range
- #define dmac_flush_range		cpu_cache.dma_flush_range
- 
- #else
-@@ -159,6 +178,8 @@ extern void __cpuc_flush_dcache_area(voi
-  * is visible to DMA, or data written by DMA to system memory is
-  * visible to the CPU.
-  */
-+extern void dmac_inv_range(const void *, const void *);
-+extern void dmac_clean_range(const void *, const void *);
- extern void dmac_flush_range(const void *, const void *);
- 
- #endif
---- a/arch/arm/include/asm/glue-cache.h
-+++ b/arch/arm/include/asm/glue-cache.h
-@@ -154,6 +154,8 @@ static inline void nop_dma_unmap_area(co
- #define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
- #define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
- 
-+#define dmac_inv_range			__glue(_CACHE,_dma_inv_range)
-+#define dmac_clean_range		__glue(_CACHE,_dma_clean_range)
- #define dmac_flush_range		__glue(_CACHE,_dma_flush_range)
- #endif
- 
---- a/arch/arm/mm/proc-macros.S
-+++ b/arch/arm/mm/proc-macros.S
-@@ -325,6 +325,8 @@ ENTRY(\name\()_cache_fns)
- 	.long	\name\()_flush_kern_dcache_area
- 	.long	\name\()_dma_map_area
- 	.long	\name\()_dma_unmap_area
-+	.long	\name\()_dma_inv_range
-+	.long	\name\()_dma_clean_range
- 	.long	\name\()_dma_flush_range
- 	.size	\name\()_cache_fns, . - \name\()_cache_fns
- .endm
---- a/arch/arm/mm/proc-syms.c
-+++ b/arch/arm/mm/proc-syms.c
-@@ -30,6 +30,9 @@ EXPORT_SYMBOL(__cpuc_flush_user_all);
- EXPORT_SYMBOL(__cpuc_flush_user_range);
- EXPORT_SYMBOL(__cpuc_coherent_kern_range);
- EXPORT_SYMBOL(__cpuc_flush_dcache_area);
-+EXPORT_SYMBOL(dmac_inv_range);
-+EXPORT_SYMBOL(dmac_clean_range);
-+EXPORT_SYMBOL(dmac_flush_range);
- #else
- EXPORT_SYMBOL(cpu_cache);
- #endif
diff --git a/target/linux/brcm2708/patches-4.14/950-0002-smsx95xx-fix-crimes-against-truesize.patch b/target/linux/brcm2708/patches-4.14/950-0002-smsx95xx-fix-crimes-against-truesize.patch
deleted file mode 100644
index 0dd2c7ce3..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0002-smsx95xx-fix-crimes-against-truesize.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 313db26f57beeb201e7c72acb6f0f9772f7d56d8 Mon Sep 17 00:00:00 2001
-From: Steve Glendinning <steve.glendinning@smsc.com>
-Date: Thu, 19 Feb 2015 18:47:12 +0000
-Subject: [PATCH 002/454] smsx95xx: fix crimes against truesize
-
-smsc95xx is adjusting truesize when it shouldn't, and following a recent patch from Eric this is now triggering warnings.
-
-This patch stops smsc95xx from changing truesize.
-
-Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
----
- drivers/net/usb/smsc95xx.c | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
---- a/drivers/net/usb/smsc95xx.c
-+++ b/drivers/net/usb/smsc95xx.c
-@@ -82,6 +82,10 @@ static bool turbo_mode = true;
- module_param(turbo_mode, bool, 0644);
- MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
- 
-+static bool truesize_mode = false;
-+module_param(truesize_mode, bool, 0644);
-+MODULE_PARM_DESC(truesize_mode, "Report larger truesize value");
-+
- static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
- 					    u32 *data, int in_pm)
- {
-@@ -1971,7 +1975,8 @@ static int smsc95xx_rx_fixup(struct usbn
- 				if (dev->net->features & NETIF_F_RXCSUM)
- 					smsc95xx_rx_csum_offload(skb);
- 				skb_trim(skb, skb->len - 4); /* remove fcs */
--				skb->truesize = size + sizeof(struct sk_buff);
-+				if (truesize_mode)
-+					skb->truesize = size + sizeof(struct sk_buff);
- 
- 				return 1;
- 			}
-@@ -1989,7 +1994,8 @@ static int smsc95xx_rx_fixup(struct usbn
- 			if (dev->net->features & NETIF_F_RXCSUM)
- 				smsc95xx_rx_csum_offload(ax_skb);
- 			skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
--			ax_skb->truesize = size + sizeof(struct sk_buff);
-+			if (truesize_mode)
-+				ax_skb->truesize = size + sizeof(struct sk_buff);
- 
- 			usbnet_skb_return(dev, ax_skb);
- 		}
diff --git a/target/linux/brcm2708/patches-4.14/950-0003-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch b/target/linux/brcm2708/patches-4.14/950-0003-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch
deleted file mode 100644
index 5f9a6d396..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0003-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 4e6c055ee7fbbe82449edafce4f1371116e6dcab Mon Sep 17 00:00:00 2001
-From: Sam Nazarko <email@samnazarko.co.uk>
-Date: Fri, 1 Apr 2016 17:27:21 +0100
-Subject: [PATCH 003/454] smsc95xx: Experimental: Enable turbo_mode and
- packetsize=2560 by default
-
-See: http://forum.kodi.tv/showthread.php?tid=285288
----
- drivers/net/usb/smsc95xx.c | 14 +++++++++-----
- 1 file changed, 9 insertions(+), 5 deletions(-)
-
---- a/drivers/net/usb/smsc95xx.c
-+++ b/drivers/net/usb/smsc95xx.c
-@@ -86,6 +86,10 @@ static bool truesize_mode = false;
- module_param(truesize_mode, bool, 0644);
- MODULE_PARM_DESC(truesize_mode, "Report larger truesize value");
- 
-+static int packetsize = 2560;
-+module_param(packetsize, int, 0644);
-+MODULE_PARM_DESC(packetsize, "Override the RX URB packet size");
-+
- static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
- 					    u32 *data, int in_pm)
- {
-@@ -1109,13 +1113,13 @@ static int smsc95xx_reset(struct usbnet
- 
- 	if (!turbo_mode) {
- 		burst_cap = 0;
--		dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
-+		dev->rx_urb_size = packetsize ? packetsize : MAX_SINGLE_PACKET_SIZE;
- 	} else if (dev->udev->speed == USB_SPEED_HIGH) {
--		burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
--		dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
-+		dev->rx_urb_size = packetsize ? packetsize : DEFAULT_HS_BURST_CAP_SIZE;
-+		burst_cap = dev->rx_urb_size / HS_USB_PKT_SIZE;
- 	} else {
--		burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
--		dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
-+		dev->rx_urb_size = packetsize ? packetsize : DEFAULT_FS_BURST_CAP_SIZE;
-+		burst_cap = dev->rx_urb_size / FS_USB_PKT_SIZE;
- 	}
- 
- 	netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
diff --git a/target/linux/brcm2708/patches-4.14/950-0004-Allow-mac-address-to-be-set-in-smsc95xx.patch b/target/linux/brcm2708/patches-4.14/950-0004-Allow-mac-address-to-be-set-in-smsc95xx.patch
deleted file mode 100644
index c7c7b9b5c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0004-Allow-mac-address-to-be-set-in-smsc95xx.patch
+++ /dev/null
@@ -1,96 +0,0 @@
-From e592fc748cfc927a3c6ed098a21ece63b1efa682 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Tue, 26 Mar 2013 17:26:38 +0000
-Subject: [PATCH 004/454] Allow mac address to be set in smsc95xx
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
----
- drivers/net/usb/smsc95xx.c | 56 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 56 insertions(+)
-
---- a/drivers/net/usb/smsc95xx.c
-+++ b/drivers/net/usb/smsc95xx.c
-@@ -60,6 +60,7 @@
- #define SUSPEND_SUSPEND3		(0x08)
- #define SUSPEND_ALLMODES		(SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
- 					 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
-+#define MAC_ADDR_LEN                    (6)
- 
- #define CARRIER_CHECK_DELAY (2 * HZ)
- 
-@@ -90,6 +91,10 @@ static int packetsize = 2560;
- module_param(packetsize, int, 0644);
- MODULE_PARM_DESC(packetsize, "Override the RX URB packet size");
- 
-+static char *macaddr = ":";
-+module_param(macaddr, charp, 0);
-+MODULE_PARM_DESC(macaddr, "MAC address");
-+
- static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
- 					    u32 *data, int in_pm)
- {
-@@ -921,6 +926,53 @@ static int smsc95xx_ioctl(struct net_dev
- 	return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
- }
- 
-+/* Check the macaddr module parameter for a MAC address */
-+static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac)
-+{
-+       int i, j, got_num, num;
-+       u8 mtbl[MAC_ADDR_LEN];
-+
-+       if (macaddr[0] == ':')
-+               return 0;
-+
-+       i = 0;
-+       j = 0;
-+       num = 0;
-+       got_num = 0;
-+       while (j < MAC_ADDR_LEN) {
-+               if (macaddr[i] && macaddr[i] != ':') {
-+                       got_num++;
-+                       if ('0' <= macaddr[i] && macaddr[i] <= '9')
-+                               num = num * 16 + macaddr[i] - '0';
-+                       else if ('A' <= macaddr[i] && macaddr[i] <= 'F')
-+                               num = num * 16 + 10 + macaddr[i] - 'A';
-+                       else if ('a' <= macaddr[i] && macaddr[i] <= 'f')
-+                               num = num * 16 + 10 + macaddr[i] - 'a';
-+                       else
-+                               break;
-+                       i++;
-+               } else if (got_num == 2) {
-+                       mtbl[j++] = (u8) num;
-+                       num = 0;
-+                       got_num = 0;
-+                       i++;
-+               } else {
-+                       break;
-+               }
-+       }
-+
-+       if (j == MAC_ADDR_LEN) {
-+               netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: "
-+               "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2],
-+                                               mtbl[3], mtbl[4], mtbl[5]);
-+               for (i = 0; i < MAC_ADDR_LEN; i++)
-+                       dev_mac[i] = mtbl[i];
-+               return 1;
-+       } else {
-+               return 0;
-+       }
-+}
-+
- static void smsc95xx_init_mac_address(struct usbnet *dev)
- {
- 	const u8 *mac_addr;
-@@ -942,6 +994,10 @@ static void smsc95xx_init_mac_address(st
- 		}
- 	}
- 
-+	/* Check module parameters */
-+	if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr))
-+		return;
-+
- 	/* no useful static MAC address found. generate a random one */
- 	eth_hw_addr_random(dev->net);
- 	netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
diff --git a/target/linux/brcm2708/patches-4.14/950-0005-Protect-__release_resource-against-resources-without.patch b/target/linux/brcm2708/patches-4.14/950-0005-Protect-__release_resource-against-resources-without.patch
deleted file mode 100644
index cd6bd549c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0005-Protect-__release_resource-against-resources-without.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From f641853ee23864c1ea7c36553e6406662b8cd0ba Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 13 Mar 2015 12:43:36 +0000
-Subject: [PATCH 005/454] Protect __release_resource against resources without
- parents
-
-Without this patch, removing a device tree overlay can crash here.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- kernel/resource.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/kernel/resource.c
-+++ b/kernel/resource.c
-@@ -246,6 +246,12 @@ static int __release_resource(struct res
- {
- 	struct resource *tmp, **p, *chd;
- 
-+	if (!old->parent) {
-+		WARN(old->sibling, "sibling but no parent");
-+		if (old->sibling)
-+			return -EINVAL;
-+		return 0;
-+	}
- 	p = &old->parent->child;
- 	for (;;) {
- 		tmp = *p;
diff --git a/target/linux/brcm2708/patches-4.14/950-0006-irq-bcm2836-Prevent-spurious-interrupts-and-trap-the.patch b/target/linux/brcm2708/patches-4.14/950-0006-irq-bcm2836-Prevent-spurious-interrupts-and-trap-the.patch
deleted file mode 100644
index b7ee68450..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0006-irq-bcm2836-Prevent-spurious-interrupts-and-trap-the.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 1d7fd600451fbca94e968f552e5e663e3aa36c61 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 4 Dec 2015 17:41:50 +0000
-Subject: [PATCH 006/454] irq-bcm2836: Prevent spurious interrupts, and trap
- them early
-
-The old arch-specific IRQ macros included a dsb to ensure the
-write to clear the mailbox interrupt completed before returning
-from the interrupt. The BCM2836 irqchip driver needs the same
-precaution to avoid spurious interrupts.
-
-Spurious interrupts are still possible for other reasons,
-though, so trap them early.
----
- drivers/irqchip/irq-bcm2836.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/irqchip/irq-bcm2836.c
-+++ b/drivers/irqchip/irq-bcm2836.c
-@@ -175,6 +175,7 @@ __exception_irq_entry bcm2836_arm_irqchi
- 		u32 ipi = ffs(mbox_val) - 1;
- 
- 		writel(1 << ipi, mailbox0);
-+		dsb(sy);
- 		handle_IPI(ipi, regs);
- #endif
- 	} else if (stat) {
diff --git a/target/linux/brcm2708/patches-4.14/950-0007-irq-bcm2836-Avoid-Invalid-trigger-warning.patch b/target/linux/brcm2708/patches-4.14/950-0007-irq-bcm2836-Avoid-Invalid-trigger-warning.patch
deleted file mode 100644
index cb6f79d2c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0007-irq-bcm2836-Avoid-Invalid-trigger-warning.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From 00931bb3a62ff22372284e8797ed17816beb264a Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 9 Feb 2017 14:33:30 +0000
-Subject: [PATCH 007/454] irq-bcm2836: Avoid "Invalid trigger warning"
-
-Initialise the level for each IRQ to avoid a warning from the
-arm arch timer code.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/irqchip/irq-bcm2836.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/irqchip/irq-bcm2836.c
-+++ b/drivers/irqchip/irq-bcm2836.c
-@@ -157,7 +157,7 @@ static void bcm2836_arm_irqchip_register
- 
- 	irq_set_percpu_devid(irq);
- 	irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
--	irq_set_status_flags(irq, IRQ_NOAUTOEN);
-+	irq_set_status_flags(irq, IRQ_NOAUTOEN | IRQ_TYPE_LEVEL_LOW);
- }
- 
- static void
diff --git a/target/linux/brcm2708/patches-4.14/950-0008-irqchip-bcm2835-Add-FIQ-support.patch b/target/linux/brcm2708/patches-4.14/950-0008-irqchip-bcm2835-Add-FIQ-support.patch
deleted file mode 100644
index dee8c5497..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0008-irqchip-bcm2835-Add-FIQ-support.patch
+++ /dev/null
@@ -1,127 +0,0 @@
-From 3bf3bf7064d688dae7fdf7b49b28073eccd9dd99 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Fri, 12 Jun 2015 19:01:05 +0200
-Subject: [PATCH 008/454] irqchip: bcm2835: Add FIQ support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add a duplicate irq range with an offset on the hwirq's so the
-driver can detect that enable_fiq() is used.
-Tested with downstream dwc_otg USB controller driver.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Acked-by: Stephen Warren <swarren@wwwdotorg.org>
----
- arch/arm/mach-bcm/Kconfig     |  1 +
- drivers/irqchip/irq-bcm2835.c | 51 +++++++++++++++++++++++++++++++----
- 2 files changed, 47 insertions(+), 5 deletions(-)
-
---- a/arch/arm/mach-bcm/Kconfig
-+++ b/arch/arm/mach-bcm/Kconfig
-@@ -155,6 +155,7 @@ config ARCH_BCM2835
- 	select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
- 	select TIMER_OF
- 	select BCM2835_TIMER
-+	select FIQ
- 	select PINCTRL
- 	select PINCTRL_BCM2835
- 	help
---- a/drivers/irqchip/irq-bcm2835.c
-+++ b/drivers/irqchip/irq-bcm2835.c
-@@ -54,7 +54,7 @@
- #include <asm/exception.h>
- 
- /* Put the bank and irq (32 bits) into the hwirq */
--#define MAKE_HWIRQ(b, n)	((b << 5) | (n))
-+#define MAKE_HWIRQ(b, n)	(((b) << 5) | (n))
- #define HWIRQ_BANK(i)		(i >> 5)
- #define HWIRQ_BIT(i)		BIT(i & 0x1f)
- 
-@@ -70,9 +70,13 @@
- 					| SHORTCUT1_MASK | SHORTCUT2_MASK)
- 
- #define REG_FIQ_CONTROL		0x0c
-+#define REG_FIQ_ENABLE		0x80
-+#define REG_FIQ_DISABLE		0
- 
- #define NR_BANKS		3
- #define IRQS_PER_BANK		32
-+#define NUMBER_IRQS		MAKE_HWIRQ(NR_BANKS, 0)
-+#define FIQ_START		(NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))
- 
- static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
- static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
-@@ -97,14 +101,38 @@ static void __exception_irq_entry bcm283
- 	struct pt_regs *regs);
- static void bcm2836_chained_handle_irq(struct irq_desc *desc);
- 
-+static inline unsigned int hwirq_to_fiq(unsigned long hwirq)
-+{
-+	hwirq -= NUMBER_IRQS;
-+	/*
-+	 * The hwirq numbering used in this driver is:
-+	 *   BASE (0-7) GPU1 (32-63) GPU2 (64-95).
-+	 * This differ from the one used in the FIQ register:
-+	 *   GPU1 (0-31) GPU2 (32-63) BASE (64-71)
-+	 */
-+	if (hwirq >= 32)
-+		return hwirq - 32;
-+
-+	return hwirq + 64;
-+}
-+
- static void armctrl_mask_irq(struct irq_data *d)
- {
--	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
-+	if (d->hwirq >= NUMBER_IRQS)
-+		writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
-+	else
-+		writel_relaxed(HWIRQ_BIT(d->hwirq),
-+			       intc.disable[HWIRQ_BANK(d->hwirq)]);
- }
- 
- static void armctrl_unmask_irq(struct irq_data *d)
- {
--	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
-+	if (d->hwirq >= NUMBER_IRQS)
-+		writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
-+			       intc.base + REG_FIQ_CONTROL);
-+	else
-+		writel_relaxed(HWIRQ_BIT(d->hwirq),
-+			       intc.enable[HWIRQ_BANK(d->hwirq)]);
- }
- 
- static struct irq_chip armctrl_chip = {
-@@ -149,8 +177,9 @@ static int __init armctrl_of_init(struct
- 	if (!base)
- 		panic("%pOF: unable to map IC registers\n", node);
- 
--	intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
--			&armctrl_ops, NULL);
-+	intc.base = base;
-+	intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
-+					    &armctrl_ops, NULL);
- 	if (!intc.domain)
- 		panic("%pOF: unable to create IRQ domain\n", node);
- 
-@@ -180,6 +209,18 @@ static int __init armctrl_of_init(struct
- 		set_handle_irq(bcm2835_handle_irq);
- 	}
- 
-+	/* Make a duplicate irq range which is used to enable FIQ */
-+	for (b = 0; b < NR_BANKS; b++) {
-+		for (i = 0; i < bank_irqs[b]; i++) {
-+			irq = irq_create_mapping(intc.domain,
-+					MAKE_HWIRQ(b, i) + NUMBER_IRQS);
-+			BUG_ON(irq <= 0);
-+			irq_set_chip(irq, &armctrl_chip);
-+			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-+		}
-+	}
-+	init_FIQ(FIQ_START);
-+
- 	return 0;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0009-irqchip-irq-bcm2835-Add-2836-FIQ-support.patch b/target/linux/brcm2708/patches-4.14/950-0009-irqchip-irq-bcm2835-Add-2836-FIQ-support.patch
deleted file mode 100644
index 87fd157b4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0009-irqchip-irq-bcm2835-Add-2836-FIQ-support.patch
+++ /dev/null
@@ -1,99 +0,0 @@
-From 1d8af4d16ff95154c134b060900aefac133c50b6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Fri, 23 Oct 2015 16:26:55 +0200
-Subject: [PATCH 009/454] irqchip: irq-bcm2835: Add 2836 FIQ support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/irqchip/irq-bcm2835.c | 43 +++++++++++++++++++++++++++++++++--
- 1 file changed, 41 insertions(+), 2 deletions(-)
-
---- a/drivers/irqchip/irq-bcm2835.c
-+++ b/drivers/irqchip/irq-bcm2835.c
-@@ -50,8 +50,11 @@
- #include <linux/of_irq.h>
- #include <linux/irqchip.h>
- #include <linux/irqdomain.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
- 
- #include <asm/exception.h>
-+#include <asm/mach/irq.h>
- 
- /* Put the bank and irq (32 bits) into the hwirq */
- #define MAKE_HWIRQ(b, n)	(((b) << 5) | (n))
-@@ -69,6 +72,9 @@
- #define BANK0_VALID_MASK	(BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
- 					| SHORTCUT1_MASK | SHORTCUT2_MASK)
- 
-+#undef ARM_LOCAL_GPU_INT_ROUTING
-+#define ARM_LOCAL_GPU_INT_ROUTING 0x0c
-+
- #define REG_FIQ_CONTROL		0x0c
- #define REG_FIQ_ENABLE		0x80
- #define REG_FIQ_DISABLE		0
-@@ -94,6 +100,7 @@ struct armctrl_ic {
- 	void __iomem *enable[NR_BANKS];
- 	void __iomem *disable[NR_BANKS];
- 	struct irq_domain *domain;
-+	struct regmap *local_regmap;
- };
- 
- static struct armctrl_ic intc __read_mostly;
-@@ -127,12 +134,35 @@ static void armctrl_mask_irq(struct irq_
- 
- static void armctrl_unmask_irq(struct irq_data *d)
- {
--	if (d->hwirq >= NUMBER_IRQS)
-+	if (d->hwirq >= NUMBER_IRQS) {
-+		if (num_online_cpus() > 1) {
-+			unsigned int data;
-+			int ret;
-+
-+			if (!intc.local_regmap) {
-+				pr_err("FIQ is disabled due to missing regmap\n");
-+				return;
-+			}
-+
-+			ret = regmap_read(intc.local_regmap,
-+					  ARM_LOCAL_GPU_INT_ROUTING, &data);
-+			if (ret) {
-+				pr_err("Failed to read int routing %d\n", ret);
-+				return;
-+			}
-+
-+			data &= ~0xc;
-+			data |= (1 << 2);
-+			regmap_write(intc.local_regmap,
-+				     ARM_LOCAL_GPU_INT_ROUTING, data);
-+		}
-+
- 		writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
- 			       intc.base + REG_FIQ_CONTROL);
--	else
-+	} else {
- 		writel_relaxed(HWIRQ_BIT(d->hwirq),
- 			       intc.enable[HWIRQ_BANK(d->hwirq)]);
-+	}
- }
- 
- static struct irq_chip armctrl_chip = {
-@@ -209,6 +239,15 @@ static int __init armctrl_of_init(struct
- 		set_handle_irq(bcm2835_handle_irq);
- 	}
- 
-+	if (is_2836) {
-+		intc.local_regmap =
-+			syscon_regmap_lookup_by_compatible("brcm,bcm2836-arm-local");
-+		if (IS_ERR(intc.local_regmap)) {
-+			pr_err("Failed to get local register map. FIQ is disabled for cpus > 1\n");
-+			intc.local_regmap = NULL;
-+		}
-+	}
-+
- 	/* Make a duplicate irq range which is used to enable FIQ */
- 	for (b = 0; b < NR_BANKS; b++) {
- 		for (i = 0; i < bank_irqs[b]; i++) {
diff --git a/target/linux/brcm2708/patches-4.14/950-0010-irq_bcm2836-Send-event-when-onlining-sleeping-cores.patch b/target/linux/brcm2708/patches-4.14/950-0010-irq_bcm2836-Send-event-when-onlining-sleeping-cores.patch
deleted file mode 100644
index 48ccfbfab..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0010-irq_bcm2836-Send-event-when-onlining-sleeping-cores.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 6b8b69ff7c4c25f01535cbe49a80516df6dbcfe8 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 8 May 2017 16:43:40 +0100
-Subject: [PATCH 010/454] irq_bcm2836: Send event when onlining sleeping cores
-
-In order to reduce power consumption and bus traffic, it is sensible
-for secondary cores to enter a low-power idle state when waiting to
-be started. The wfe instruction causes a core to wait until an event
-or interrupt arrives before continuing to the next instruction.
-The sev instruction sends a wakeup event to the other cores, so call
-it from bcm2836_smp_boot_secondary, the function that wakes up the
-waiting cores during booting.
-
-It is harmless to use this patch without the corresponding change
-adding wfe to the ARMv7/ARMv8-32 stubs, but if the stubs are updated
-and this patch is not applied then the other cores will sleep forever.
-
-See: https://github.com/raspberrypi/linux/issues/1989
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/irqchip/irq-bcm2836.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/irqchip/irq-bcm2836.c
-+++ b/drivers/irqchip/irq-bcm2836.c
-@@ -227,6 +227,9 @@ static int __init bcm2836_smp_boot_secon
- 	writel(secondary_startup_phys,
- 	       intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
- 
-+	dsb(sy); /* Ensure write has completed before waking the other CPUs */
-+	sev();
-+
- 	return 0;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0011-spidev-Add-spidev-compatible-string-to-silence-warni.patch b/target/linux/brcm2708/patches-4.14/950-0011-spidev-Add-spidev-compatible-string-to-silence-warni.patch
deleted file mode 100644
index 47550aa89..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0011-spidev-Add-spidev-compatible-string-to-silence-warni.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 5e12841c484176b869a26955fc73730720e52b67 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 14 Jul 2015 10:26:09 +0100
-Subject: [PATCH 011/454] spidev: Add "spidev" compatible string to silence
- warning
-
-See: https://github.com/raspberrypi/linux/issues/1054
----
- drivers/spi/spidev.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/spi/spidev.c
-+++ b/drivers/spi/spidev.c
-@@ -670,6 +670,7 @@ static const struct of_device_id spidev_
- 	{ .compatible = "ge,achc" },
- 	{ .compatible = "semtech,sx1301" },
- 	{ .compatible = "siliconlabs,si3210" },
-+	{ .compatible = "spidev" },
- 	{},
- };
- MODULE_DEVICE_TABLE(of, spidev_dt_ids);
diff --git a/target/linux/brcm2708/patches-4.14/950-0012-spi-bcm2835-Support-pin-groups-other-than-7-11.patch b/target/linux/brcm2708/patches-4.14/950-0012-spi-bcm2835-Support-pin-groups-other-than-7-11.patch
deleted file mode 100644
index edd040455..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0012-spi-bcm2835-Support-pin-groups-other-than-7-11.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From e27613dee9bede1a5d8c86c3cdc5244175651534 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 24 Jun 2015 14:10:44 +0100
-Subject: [PATCH 012/454] spi-bcm2835: Support pin groups other than 7-11
-
-The spi-bcm2835 driver automatically uses GPIO chip-selects due to
-some unreliability of the native ones. In doing so it chooses the
-same pins as the native chip-selects would use, but the existing
-code always uses pins 7 and 8, wherever the SPI function is mapped.
-
-Search the pinctrl group assigned to the driver for pins that
-correspond to native chip-selects, and use those for GPIO chip-
-selects.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/spi/spi-bcm2835.c | 45 ++++++++++++++++++++++++++++++++-------
- 1 file changed, 37 insertions(+), 8 deletions(-)
-
---- a/drivers/spi/spi-bcm2835.c
-+++ b/drivers/spi/spi-bcm2835.c
-@@ -688,6 +688,8 @@ static int bcm2835_spi_setup(struct spi_
- {
- 	int err;
- 	struct gpio_chip *chip;
-+	struct device_node *pins;
-+	u32 pingroup_index;
- 	/*
- 	 * sanity checking the native-chipselects
- 	 */
-@@ -704,15 +706,42 @@ static int bcm2835_spi_setup(struct spi_
- 			"setup: only two native chip-selects are supported\n");
- 		return -EINVAL;
- 	}
--	/* now translate native cs to GPIO */
- 
--	/* get the gpio chip for the base */
--	chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
--	if (!chip)
--		return 0;
-+	/* now translate native cs to GPIO */
-+	/* first look for chip select pins in the devices pin groups */
-+	for (pingroup_index = 0;
-+	     (pins = of_parse_phandle(spi->master->dev.of_node,
-+				     "pinctrl-0",
-+				      pingroup_index)) != 0;
-+	     pingroup_index++) {
-+		u32 pin;
-+		u32 pin_index;
-+		for (pin_index = 0;
-+		     of_property_read_u32_index(pins,
-+						"brcm,pins",
-+						pin_index,
-+						&pin) == 0;
-+		     pin_index++) {
-+			if (((spi->chip_select == 0) &&
-+			     ((pin == 8) || (pin == 36) || (pin == 46))) ||
-+			    ((spi->chip_select == 1) &&
-+			     ((pin == 7) || (pin == 35)))) {
-+				spi->cs_gpio = pin;
-+				break;
-+			}
-+		}
-+		of_node_put(pins);
-+	}
-+	/* if that fails, assume GPIOs 7-11 are used */
-+	if (!gpio_is_valid(spi->cs_gpio) ) {
-+		/* get the gpio chip for the base */
-+		chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
-+		if (!chip)
-+			return 0;
- 
--	/* and calculate the real CS */
--	spi->cs_gpio = chip->base + 8 - spi->chip_select;
-+		/* and calculate the real CS */
-+		spi->cs_gpio = chip->base + 8 - spi->chip_select;
-+	}
- 
- 	/* and set up the "mode" and level */
- 	dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
diff --git a/target/linux/brcm2708/patches-4.14/950-0013-spi-bcm2835-Disable-forced-software-CS.patch b/target/linux/brcm2708/patches-4.14/950-0013-spi-bcm2835-Disable-forced-software-CS.patch
deleted file mode 100644
index e0ab7ecef..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0013-spi-bcm2835-Disable-forced-software-CS.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 6af2125a4aa2bfacda4e7c01ed3214a3a866eab6 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 1 Jul 2016 22:09:24 +0100
-Subject: [PATCH 013/454] spi-bcm2835: Disable forced software CS
-
-Select software CS in bcm2708_common.dtsi, and disable the automatic
-conversion in the driver to allow hardware CS to be re-enabled with an
-overlay.
-
-See: https://github.com/raspberrypi/linux/issues/1547
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/spi/spi-bcm2835.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/spi/spi-bcm2835.c
-+++ b/drivers/spi/spi-bcm2835.c
-@@ -707,6 +707,7 @@ static int bcm2835_spi_setup(struct spi_
- 		return -EINVAL;
- 	}
- 
-+#if 0
- 	/* now translate native cs to GPIO */
- 	/* first look for chip select pins in the devices pin groups */
- 	for (pingroup_index = 0;
-@@ -756,6 +757,7 @@ static int bcm2835_spi_setup(struct spi_
- 			spi->chip_select, spi->cs_gpio, err);
- 		return err;
- 	}
-+#endif
- 
- 	return 0;
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0014-spi-bcm2835-Remove-unused-code.patch b/target/linux/brcm2708/patches-4.14/950-0014-spi-bcm2835-Remove-unused-code.patch
deleted file mode 100644
index 601de428f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0014-spi-bcm2835-Remove-unused-code.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 538bc2e4d22633d87f2e4689edfd1f313baf61ab Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 8 Nov 2016 21:35:38 +0000
-Subject: [PATCH 014/454] spi-bcm2835: Remove unused code
-
----
- drivers/spi/spi-bcm2835.c | 61 ---------------------------------------
- 1 file changed, 61 deletions(-)
-
---- a/drivers/spi/spi-bcm2835.c
-+++ b/drivers/spi/spi-bcm2835.c
-@@ -679,17 +679,8 @@ static void bcm2835_spi_set_cs(struct sp
- 	bcm2835_wr(bs, BCM2835_SPI_CS, cs);
- }
- 
--static int chip_match_name(struct gpio_chip *chip, void *data)
--{
--	return !strcmp(chip->label, data);
--}
--
- static int bcm2835_spi_setup(struct spi_device *spi)
- {
--	int err;
--	struct gpio_chip *chip;
--	struct device_node *pins;
--	u32 pingroup_index;
- 	/*
- 	 * sanity checking the native-chipselects
- 	 */
-@@ -707,58 +698,6 @@ static int bcm2835_spi_setup(struct spi_
- 		return -EINVAL;
- 	}
- 
--#if 0
--	/* now translate native cs to GPIO */
--	/* first look for chip select pins in the devices pin groups */
--	for (pingroup_index = 0;
--	     (pins = of_parse_phandle(spi->master->dev.of_node,
--				     "pinctrl-0",
--				      pingroup_index)) != 0;
--	     pingroup_index++) {
--		u32 pin;
--		u32 pin_index;
--		for (pin_index = 0;
--		     of_property_read_u32_index(pins,
--						"brcm,pins",
--						pin_index,
--						&pin) == 0;
--		     pin_index++) {
--			if (((spi->chip_select == 0) &&
--			     ((pin == 8) || (pin == 36) || (pin == 46))) ||
--			    ((spi->chip_select == 1) &&
--			     ((pin == 7) || (pin == 35)))) {
--				spi->cs_gpio = pin;
--				break;
--			}
--		}
--		of_node_put(pins);
--	}
--	/* if that fails, assume GPIOs 7-11 are used */
--	if (!gpio_is_valid(spi->cs_gpio) ) {
--		/* get the gpio chip for the base */
--		chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
--		if (!chip)
--			return 0;
--
--		/* and calculate the real CS */
--		spi->cs_gpio = chip->base + 8 - spi->chip_select;
--	}
--
--	/* and set up the "mode" and level */
--	dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
--		 spi->chip_select, spi->cs_gpio);
--
--	/* set up GPIO as output and pull to the correct level */
--	err = gpio_direction_output(spi->cs_gpio,
--				    (spi->mode & SPI_CS_HIGH) ? 0 : 1);
--	if (err) {
--		dev_err(&spi->dev,
--			"could not set CS%i gpio %i as output: %i",
--			spi->chip_select, spi->cs_gpio, err);
--		return err;
--	}
--#endif
--
- 	return 0;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0015-ARM-bcm2835-Set-Serial-number-and-Revision.patch b/target/linux/brcm2708/patches-4.14/950-0015-ARM-bcm2835-Set-Serial-number-and-Revision.patch
deleted file mode 100644
index bf93c934b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0015-ARM-bcm2835-Set-Serial-number-and-Revision.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 524b23e8fd0b05840b2eec5686389ead822983ef Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Wed, 3 Jun 2015 12:26:13 +0200
-Subject: [PATCH 015/454] ARM: bcm2835: Set Serial number and Revision
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The VideoCore bootloader passes in Serial number and
-Revision number through Device Tree. Make these available to
-userspace through /proc/cpuinfo.
-
-Mainline status:
-
-There is a commit in linux-next that standardize passing the serial
-number through Device Tree (string: /serial-number):
-ARM: 8355/1: arch: Show the serial number from devicetree in cpuinfo
-
-There was an attempt to do the same with the revision number, but it
-didn't get in:
-[PATCH v2 1/2] arm: devtree: Set system_rev from DT revision
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- arch/arm/mach-bcm/board_bcm2835.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm/mach-bcm/board_bcm2835.c
-+++ b/arch/arm/mach-bcm/board_bcm2835.c
-@@ -16,13 +16,23 @@
- #include <linux/irqchip.h>
- #include <linux/of_address.h>
- #include <linux/clk/bcm2835.h>
-+#include <asm/system_info.h>
- 
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- 
- static void __init bcm2835_init(void)
- {
-+	struct device_node *np = of_find_node_by_path("/system");
-+	u32 val;
-+	u64 val64;
-+
- 	bcm2835_init_clocks();
-+
-+	if (!of_property_read_u32(np, "linux,revision", &val))
-+		system_rev = val;
-+	if (!of_property_read_u64(np, "linux,serial", &val64))
-+		system_serial_low = val64;
- }
- 
- static const char * const bcm2835_compat[] = {
diff --git a/target/linux/brcm2708/patches-4.14/950-0016-dmaengine-bcm2835-Load-driver-early-and-support-lega.patch b/target/linux/brcm2708/patches-4.14/950-0016-dmaengine-bcm2835-Load-driver-early-and-support-lega.patch
deleted file mode 100644
index bb14791ba..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0016-dmaengine-bcm2835-Load-driver-early-and-support-lega.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From 8a9eb6f0ef9e548aaa5ac60e95e4c0c9c99adcab Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Sat, 3 Oct 2015 22:22:55 +0200
-Subject: [PATCH 016/454] dmaengine: bcm2835: Load driver early and support
- legacy API
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Load driver early since at least bcm2708_fb doesn't support deferred
-probing and even if it did, we don't want the video driver deferred.
-Support the legacy DMA API which is needed by bcm2708_fb.
-Don't mask out channel 2.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/dma/Kconfig       |  2 +-
- drivers/dma/bcm2835-dma.c | 26 +++++++++++++++++++++++++-
- 2 files changed, 26 insertions(+), 2 deletions(-)
-
---- a/drivers/dma/Kconfig
-+++ b/drivers/dma/Kconfig
-@@ -131,7 +131,7 @@ config COH901318
- 
- config DMA_BCM2835
- 	tristate "BCM2835 DMA engine support"
--	depends on ARCH_BCM2835
-+	depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
- 	select DMA_ENGINE
- 	select DMA_VIRTUAL_CHANNELS
- 
---- a/drivers/dma/bcm2835-dma.c
-+++ b/drivers/dma/bcm2835-dma.c
-@@ -37,6 +37,7 @@
- #include <linux/interrupt.h>
- #include <linux/list.h>
- #include <linux/module.h>
-+#include <linux/platform_data/dma-bcm2708.h>
- #include <linux/platform_device.h>
- #include <linux/slab.h>
- #include <linux/io.h>
-@@ -48,6 +49,7 @@
- 
- #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
- #define BCM2835_DMA_CHAN_NAME_SIZE 8
-+#define BCM2835_DMA_BULK_MASK  BIT(0)
- 
- struct bcm2835_dmadev {
- 	struct dma_device ddev;
-@@ -925,6 +927,9 @@ static int bcm2835_dma_probe(struct plat
- 	base = devm_ioremap_resource(&pdev->dev, res);
- 	if (IS_ERR(base))
- 		return PTR_ERR(base);
-+	rc = bcm_dmaman_probe(pdev, base, BCM2835_DMA_BULK_MASK);
-+	if (rc)
-+		dev_err(&pdev->dev, "Failed to initialize the legacy API\n");
- 
- 	od->base = base;
- 
-@@ -962,6 +967,9 @@ static int bcm2835_dma_probe(struct plat
- 		goto err_no_dma;
- 	}
- 
-+	/* Channel 0 is used by the legacy API */
-+	chans_available &= ~BCM2835_DMA_BULK_MASK;
-+
- 	/* get irqs for each channel that we support */
- 	for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
- 		/* skip masked out channels */
-@@ -1036,6 +1044,7 @@ static int bcm2835_dma_remove(struct pla
- {
- 	struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
- 
-+	bcm_dmaman_remove(pdev);
- 	dma_async_device_unregister(&od->ddev);
- 	bcm2835_dma_free(od);
- 
-@@ -1051,7 +1060,22 @@ static struct platform_driver bcm2835_dm
- 	},
- };
- 
--module_platform_driver(bcm2835_dma_driver);
-+static int bcm2835_dma_init(void)
-+{
-+	return platform_driver_register(&bcm2835_dma_driver);
-+}
-+
-+static void bcm2835_dma_exit(void)
-+{
-+	platform_driver_unregister(&bcm2835_dma_driver);
-+}
-+
-+/*
-+ * Load after serial driver (arch_initcall) so we see the messages if it fails,
-+ * but before drivers (module_init) that need a DMA channel.
-+ */
-+subsys_initcall(bcm2835_dma_init);
-+module_exit(bcm2835_dma_exit);
- 
- MODULE_ALIAS("platform:bcm2835-dma");
- MODULE_DESCRIPTION("BCM2835 DMA engine driver");
diff --git a/target/linux/brcm2708/patches-4.14/950-0017-firmware-Updated-mailbox-header.patch b/target/linux/brcm2708/patches-4.14/950-0017-firmware-Updated-mailbox-header.patch
deleted file mode 100644
index 7d60bfbee..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0017-firmware-Updated-mailbox-header.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From b9570d562487b4d9ec176838b020b02815356511 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Mon, 25 Jan 2016 17:25:12 +0000
-Subject: [PATCH 017/454] firmware: Updated mailbox header
-
----
- include/soc/bcm2835/raspberrypi-firmware.h | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/include/soc/bcm2835/raspberrypi-firmware.h
-+++ b/include/soc/bcm2835/raspberrypi-firmware.h
-@@ -12,6 +12,8 @@
- #include <linux/types.h>
- #include <linux/of_device.h>
- 
-+#define RPI_FIRMWARE_CHAN_FB		1
-+
- struct rpi_firmware;
- 
- enum rpi_firmware_property_status {
-@@ -63,6 +65,7 @@ enum rpi_firmware_property_tag {
- 	RPI_FIRMWARE_GET_MIN_VOLTAGE =                        0x00030008,
- 	RPI_FIRMWARE_GET_TURBO =                              0x00030009,
- 	RPI_FIRMWARE_GET_MAX_TEMPERATURE =                    0x0003000a,
-+	RPI_FIRMWARE_GET_STC =                                0x0003000b,
- 	RPI_FIRMWARE_ALLOCATE_MEMORY =                        0x0003000c,
- 	RPI_FIRMWARE_LOCK_MEMORY =                            0x0003000d,
- 	RPI_FIRMWARE_UNLOCK_MEMORY =                          0x0003000e,
-@@ -72,12 +75,22 @@ enum rpi_firmware_property_tag {
- 	RPI_FIRMWARE_SET_ENABLE_QPU =                         0x00030012,
- 	RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE =       0x00030014,
- 	RPI_FIRMWARE_GET_EDID_BLOCK =                         0x00030020,
-+	RPI_FIRMWARE_GET_CUSTOMER_OTP =                       0x00030021,
- 	RPI_FIRMWARE_GET_DOMAIN_STATE =                       0x00030030,
- 	RPI_FIRMWARE_SET_CLOCK_STATE =                        0x00038001,
- 	RPI_FIRMWARE_SET_CLOCK_RATE =                         0x00038002,
- 	RPI_FIRMWARE_SET_VOLTAGE =                            0x00038003,
- 	RPI_FIRMWARE_SET_TURBO =                              0x00038009,
-+	RPI_FIRMWARE_SET_CUSTOMER_OTP =                       0x00038021,
- 	RPI_FIRMWARE_SET_DOMAIN_STATE =                       0x00038030,
-+	RPI_FIRMWARE_GET_GPIO_STATE =                         0x00030041,
-+	RPI_FIRMWARE_SET_GPIO_STATE =                         0x00038041,
-+	RPI_FIRMWARE_SET_SDHOST_CLOCK =                       0x00038042,
-+	RPI_FIRMWARE_GET_GPIO_CONFIG =                        0x00030043,
-+	RPI_FIRMWARE_SET_GPIO_CONFIG =                        0x00038043,
-+	RPI_FIRMWARE_GET_PERIPH_REG =                         0x00030045,
-+	RPI_FIRMWARE_SET_PERIPH_REG =                         0x00038045,
-+
- 
- 	/* Dispmanx TAGS */
- 	RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE =                   0x00040001,
-@@ -91,6 +104,8 @@ enum rpi_firmware_property_tag {
- 	RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET =         0x00040009,
- 	RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN =               0x0004000a,
- 	RPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE =                0x0004000b,
-+	RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF =               0x0004000f,
-+	RPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF =            0x00040010,
- 	RPI_FIRMWARE_FRAMEBUFFER_RELEASE =                    0x00048001,
- 	RPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
- 	RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT =  0x00044004,
-@@ -100,6 +115,7 @@ enum rpi_firmware_property_tag {
- 	RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET =        0x00044009,
- 	RPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN =              0x0004400a,
- 	RPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE =               0x0004400b,
-+	RPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC =                 0x0004400e,
- 	RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT =  0x00048003,
- 	RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT =   0x00048004,
- 	RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH =                  0x00048005,
-@@ -108,6 +124,10 @@ enum rpi_firmware_property_tag {
- 	RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET =         0x00048009,
- 	RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN =               0x0004800a,
- 	RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE =                0x0004800b,
-+	RPI_FIRMWARE_FRAMEBUFFER_SET_TOUCHBUF =               0x0004801f,
-+	RPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF =            0x00048020,
-+	RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC =                  0x0004800e,
-+	RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT =              0x0004800f,
- 
- 	RPI_FIRMWARE_VCHIQ_INIT =                             0x00048010,
- 
-@@ -139,5 +159,6 @@ static inline struct rpi_firmware *rpi_f
- 	return NULL;
- }
- #endif
-+int rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data);
- 
- #endif /* __SOC_RASPBERRY_FIRMWARE_H__ */
diff --git a/target/linux/brcm2708/patches-4.14/950-0018-rtc-Add-SPI-alias-for-pcf2123-driver.patch b/target/linux/brcm2708/patches-4.14/950-0018-rtc-Add-SPI-alias-for-pcf2123-driver.patch
deleted file mode 100644
index 9c7e8d14e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0018-rtc-Add-SPI-alias-for-pcf2123-driver.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 2630e731569dd34a084bc14fceb52d114604d84b Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 15 Jun 2016 16:48:41 +0100
-Subject: [PATCH 018/454] rtc: Add SPI alias for pcf2123 driver
-
-Without this alias, Device Tree won't cause the driver
-to be loaded.
-
-See: https://github.com/raspberrypi/linux/pull/1510
----
- drivers/rtc/rtc-pcf2123.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/rtc/rtc-pcf2123.c
-+++ b/drivers/rtc/rtc-pcf2123.c
-@@ -472,3 +472,4 @@ module_spi_driver(pcf2123_driver);
- MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
- MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
- MODULE_LICENSE("GPL");
-+MODULE_ALIAS("spi:rtc-pcf2123");
diff --git a/target/linux/brcm2708/patches-4.14/950-0019-watchdog-bcm2835-Support-setting-reboot-partition.patch b/target/linux/brcm2708/patches-4.14/950-0019-watchdog-bcm2835-Support-setting-reboot-partition.patch
deleted file mode 100644
index 785bae4c9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0019-watchdog-bcm2835-Support-setting-reboot-partition.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From e9ee8ed10620ed2e4474af53cb23058b034a6e56 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Fri, 7 Oct 2016 16:50:59 +0200
-Subject: [PATCH 019/454] watchdog: bcm2835: Support setting reboot partition
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Raspberry Pi firmware looks at the RSTS register to know which
-partition to boot from. The reboot syscall command
-LINUX_REBOOT_CMD_RESTART2 supports passing in a string argument.
-
-Add support for passing in a partition number 0..63 to boot from.
-Partition 63 is a special partiton indicating halt.
-If the partition doesn't exist, the firmware falls back to partition 0.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/watchdog/bcm2835_wdt.c | 49 +++++++++++++++++++---------------
- 1 file changed, 27 insertions(+), 22 deletions(-)
-
---- a/drivers/watchdog/bcm2835_wdt.c
-+++ b/drivers/watchdog/bcm2835_wdt.c
-@@ -34,13 +34,7 @@
- #define PM_RSTC_WRCFG_SET		0x00000030
- #define PM_RSTC_WRCFG_FULL_RESET	0x00000020
- #define PM_RSTC_RESET			0x00000102
--
--/*
-- * The Raspberry Pi firmware uses the RSTS register to know which partition
-- * to boot from. The partition value is spread into bits 0, 2, 4, 6, 8, 10.
-- * Partition 63 is a special partition used by the firmware to indicate halt.
-- */
--#define PM_RSTS_RASPBERRYPI_HALT	0x555
-+#define PM_RSTS_PARTITION_CLR          0xfffffaaa
- 
- #define SECS_TO_WDOG_TICKS(x) ((x) << 16)
- #define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
-@@ -97,9 +91,24 @@ static unsigned int bcm2835_wdt_get_time
- 	return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
- }
- 
--static void __bcm2835_restart(struct bcm2835_wdt *wdt)
-+/*
-+ * The Raspberry Pi firmware uses the RSTS register to know which partiton
-+ * to boot from. The partiton value is spread into bits 0, 2, 4, 6, 8, 10.
-+ * Partiton 63 is a special partition used by the firmware to indicate halt.
-+ */
-+
-+static void __bcm2835_restart(struct bcm2835_wdt *wdt, u8 partition)
- {
--	u32 val;
-+	u32 val, rsts;
-+
-+	rsts = (partition & BIT(0)) | ((partition & BIT(1)) << 1) |
-+	       ((partition & BIT(2)) << 2) | ((partition & BIT(3)) << 3) |
-+	       ((partition & BIT(4)) << 4) | ((partition & BIT(5)) << 5);
-+
-+	val = readl_relaxed(wdt->base + PM_RSTS);
-+	val &= PM_RSTS_PARTITION_CLR;
-+	val |= PM_PASSWORD | rsts;
-+	writel_relaxed(val, wdt->base + PM_RSTS);
- 
- 	/* use a timeout of 10 ticks (~150us) */
- 	writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);
-@@ -117,7 +126,13 @@ static int bcm2835_restart(struct watchd
- {
- 	struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);
- 
--	__bcm2835_restart(wdt);
-+	unsigned long long val;
-+	u8 partition = 0;
-+
-+	if (data && !kstrtoull(data, 0, &val) && val <= 63)
-+		partition = val;
-+
-+	__bcm2835_restart(wdt, partition);
- 
- 	return 0;
- }
-@@ -155,19 +170,9 @@ static void bcm2835_power_off(void)
- 		of_find_compatible_node(NULL, NULL, "brcm,bcm2835-pm-wdt");
- 	struct platform_device *pdev = of_find_device_by_node(np);
- 	struct bcm2835_wdt *wdt = platform_get_drvdata(pdev);
--	u32 val;
--
--	/*
--	 * We set the watchdog hard reset bit here to distinguish this reset
--	 * from the normal (full) reset. bootcode.bin will not reboot after a
--	 * hard reset.
--	 */
--	val = readl_relaxed(wdt->base + PM_RSTS);
--	val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT;
--	writel_relaxed(val, wdt->base + PM_RSTS);
- 
--	/* Continue with normal reset mechanism */
--	__bcm2835_restart(wdt);
-+	/* Partition 63 tells the firmware that this is a halt */
-+	__bcm2835_restart(wdt, 63);
- }
- 
- static int bcm2835_wdt_probe(struct platform_device *pdev)
diff --git a/target/linux/brcm2708/patches-4.14/950-0020-reboot-Use-power-off-rather-than-busy-spinning-when-.patch b/target/linux/brcm2708/patches-4.14/950-0020-reboot-Use-power-off-rather-than-busy-spinning-when-.patch
deleted file mode 100644
index fa3064500..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0020-reboot-Use-power-off-rather-than-busy-spinning-when-.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From ac6e6825886db6760ba756f675e92fcdbd7634d4 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Tue, 5 Apr 2016 19:40:12 +0100
-Subject: [PATCH 020/454] reboot: Use power off rather than busy spinning when
- halt is requested
-
----
- arch/arm/kernel/reboot.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
---- a/arch/arm/kernel/reboot.c
-+++ b/arch/arm/kernel/reboot.c
-@@ -105,9 +105,7 @@ void machine_shutdown(void)
-  */
- void machine_halt(void)
- {
--	local_irq_disable();
--	smp_send_stop();
--	while (1);
-+	machine_power_off();
- }
- 
- /*
diff --git a/target/linux/brcm2708/patches-4.14/950-0021-bcm-Make-RASPBERRYPI_POWER-depend-on-PM.patch b/target/linux/brcm2708/patches-4.14/950-0021-bcm-Make-RASPBERRYPI_POWER-depend-on-PM.patch
deleted file mode 100644
index 828302a32..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0021-bcm-Make-RASPBERRYPI_POWER-depend-on-PM.patch
+++ /dev/null
@@ -1,19 +0,0 @@
-From 9a4491019545e135376214b0014d6a2b4c780d02 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Wed, 9 Nov 2016 13:02:52 +0000
-Subject: [PATCH 021/454] bcm: Make RASPBERRYPI_POWER depend on PM
-
----
- drivers/soc/bcm/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/soc/bcm/Kconfig
-+++ b/drivers/soc/bcm/Kconfig
-@@ -4,6 +4,7 @@ config RASPBERRYPI_POWER
- 	bool "Raspberry Pi power domain driver"
- 	depends on ARCH_BCM2835 || (COMPILE_TEST && OF)
- 	depends on RASPBERRYPI_FIRMWARE=y
-+	depends on PM
- 	select PM_GENERIC_DOMAINS if PM
- 	help
- 	  This enables support for the RPi power domains which can be enabled
diff --git a/target/linux/brcm2708/patches-4.14/950-0022-Register-the-clocks-early-during-the-boot-process-so.patch b/target/linux/brcm2708/patches-4.14/950-0022-Register-the-clocks-early-during-the-boot-process-so.patch
deleted file mode 100644
index fb409b30f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0022-Register-the-clocks-early-during-the-boot-process-so.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 5881d7a1df54ac9b0acf618d970737479b2f6721 Mon Sep 17 00:00:00 2001
-From: Martin Sperl <kernel@martin.sperl.org>
-Date: Fri, 2 Sep 2016 16:45:27 +0100
-Subject: [PATCH 022/454] Register the clocks early during the boot process, so
- that special/critical clocks can get enabled early on in the boot process
- avoiding the risk of disabling a clock, pll_divider or pll when a claiming
- driver fails to install propperly - maybe it needs to defer.
-
-Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
----
- drivers/clk/bcm/clk-bcm2835.c | 15 +++++++++++++--
- 1 file changed, 13 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/bcm/clk-bcm2835.c
-+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -2220,8 +2220,15 @@ static int bcm2835_clk_probe(struct plat
- 	if (ret)
- 		return ret;
- 
--	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
-+	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
- 				      &cprman->onecell);
-+	if (ret)
-+		return ret;
-+
-+	/* note that we have registered all the clocks */
-+	dev_dbg(dev, "registered %d clocks\n", asize);
-+
-+	return 0;
- }
- 
- static const struct of_device_id bcm2835_clk_of_match[] = {
-@@ -2238,7 +2245,11 @@ static struct platform_driver bcm2835_cl
- 	.probe          = bcm2835_clk_probe,
- };
- 
--builtin_platform_driver(bcm2835_clk_driver);
-+static int __init __bcm2835_clk_driver_init(void)
-+{
-+	return platform_driver_register(&bcm2835_clk_driver);
-+}
-+core_initcall(__bcm2835_clk_driver_init);
- 
- MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
- MODULE_DESCRIPTION("BCM2835 clock driver");
diff --git a/target/linux/brcm2708/patches-4.14/950-0023-bcm2835-rng-Avoid-initialising-if-already-enabled.patch b/target/linux/brcm2708/patches-4.14/950-0023-bcm2835-rng-Avoid-initialising-if-already-enabled.patch
deleted file mode 100644
index ca8fe94ee..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0023-bcm2835-rng-Avoid-initialising-if-already-enabled.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 3c343d373b5de2837e9dd827fe9b44f2563186cb Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Tue, 6 Dec 2016 17:05:39 +0000
-Subject: [PATCH 023/454] bcm2835-rng: Avoid initialising if already enabled
-
-Avoids the 0x40000 cycles of warmup again if firmware has already used it
----
- drivers/char/hw_random/bcm2835-rng.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/char/hw_random/bcm2835-rng.c
-+++ b/drivers/char/hw_random/bcm2835-rng.c
-@@ -102,9 +102,10 @@ static int bcm2835_rng_probe(struct plat
- 		rng_setup(rng_base);
- 
- 	/* set warm-up count & enable */
--	__raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS);
--	__raw_writel(RNG_RBGEN, rng_base + RNG_CTRL);
--
-+	if (!(__raw_readl(rng_base + RNG_CTRL) & RNG_RBGEN)) {
-+		__raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS);
-+		__raw_writel(RNG_RBGEN, rng_base + RNG_CTRL);
-+	}
- 	/* register driver */
- 	err = hwrng_register(&bcm2835_rng_ops);
- 	if (err) {
diff --git a/target/linux/brcm2708/patches-4.14/950-0024-kbuild-Ignore-dtco-targets-when-filtering-symbols.patch b/target/linux/brcm2708/patches-4.14/950-0024-kbuild-Ignore-dtco-targets-when-filtering-symbols.patch
deleted file mode 100644
index c1c555b94..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0024-kbuild-Ignore-dtco-targets-when-filtering-symbols.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 4d4ac64c781eb1d565c896d6614feed9c89b1957 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 24 Aug 2016 16:28:44 +0100
-Subject: [PATCH 024/454] kbuild: Ignore dtco targets when filtering symbols
-
----
- scripts/Kbuild.include | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/scripts/Kbuild.include
-+++ b/scripts/Kbuild.include
-@@ -294,7 +294,7 @@ ksym_dep_filter =
- 	    $(CPP) $(call flags_nodeps,c_flags) -D__KSYM_DEPS__ $< ;;        \
- 	  as_*_S|cpp_s_S)                                                    \
- 	    $(CPP) $(call flags_nodeps,a_flags) -D__KSYM_DEPS__ $< ;;        \
--	  boot*|build*|cpp_its_S|*cpp_lds_S|dtc|host*|vdso*) : ;;            \
-+	  boot*|build*|cpp_its_S|*cpp_lds_S|dtc*|host*|vdso*) : ;;            \
- 	  *) echo "Don't know how to preprocess $(1)" >&2; false ;;          \
- 	esac | tr ";" "\n" | sed -rn 's/^.*=== __KSYM_(.*) ===.*$$/KSYM_\1/p'
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0025-BCM2835_DT-Fix-I2S-register-map.patch b/target/linux/brcm2708/patches-4.14/950-0025-BCM2835_DT-Fix-I2S-register-map.patch
deleted file mode 100644
index 45578d5e8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0025-BCM2835_DT-Fix-I2S-register-map.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From ecabc19a9d6a889382771e3126ed413b3a51825a Mon Sep 17 00:00:00 2001
-From: Robert Tiemann <rtie@gmx.de>
-Date: Mon, 20 Jul 2015 11:01:25 +0200
-Subject: [PATCH 025/454] BCM2835_DT: Fix I2S register map
-
----
- Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt   | 4 ++--
- Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
-+++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
-@@ -74,8 +74,8 @@ Example:
- 
- bcm2835_i2s: i2s@7e203000 {
- 	compatible = "brcm,bcm2835-i2s";
--	reg = <	0x7e203000 0x20>,
--	      < 0x7e101098 0x02>;
-+	reg = <	0x7e203000 0x24>,
-+	      < 0x7e101098 0x08>;
- 
- 	dmas = <&dma 2>,
- 	       <&dma 3>;
---- a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
-+++ b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
-@@ -16,8 +16,8 @@ Example:
- 
- bcm2835_i2s: i2s@7e203000 {
- 	compatible = "brcm,bcm2835-i2s";
--	reg = <0x7e203000 0x20>,
--	      <0x7e101098 0x02>;
-+	reg = <0x7e203000 0x24>,
-+	      <0x7e101098 0x08>;
- 
- 	dmas = <&dma 2>,
- 	       <&dma 3>;
diff --git a/target/linux/brcm2708/patches-4.14/950-0026-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch b/target/linux/brcm2708/patches-4.14/950-0026-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch
deleted file mode 100644
index affa877e4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0026-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 39c54b332bfe3cb95221b663d38b5b620e47c912 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 13 Feb 2017 17:20:08 +0000
-Subject: [PATCH 026/454] clk-bcm2835: Mark used PLLs and dividers CRITICAL
-
-The VPU configures and relies on several PLLs and dividers. Mark all
-enabled dividers and their PLLs as CRITICAL to prevent the kernel from
-switching them off.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/clk/bcm/clk-bcm2835.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/clk/bcm/clk-bcm2835.c
-+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -1397,6 +1397,11 @@ bcm2835_register_pll_divider(struct bcm2
- 	divider->div.hw.init = &init;
- 	divider->div.table = NULL;
- 
-+	if (!(cprman_read(cprman, data->cm_reg) & data->hold_mask)) {
-+		init.flags |= CLK_IS_CRITICAL;
-+		divider->div.flags |= CLK_IS_CRITICAL;
-+	}
-+
- 	divider->cprman = cprman;
- 	divider->data = data;
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0027-clk-bcm2835-Add-claim-clocks-property.patch b/target/linux/brcm2708/patches-4.14/950-0027-clk-bcm2835-Add-claim-clocks-property.patch
deleted file mode 100644
index 1e2bddcdb..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0027-clk-bcm2835-Add-claim-clocks-property.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From 7a4c12de72b705c93482f3dd28b230ced588052f Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 13 Feb 2017 17:20:08 +0000
-Subject: [PATCH 027/454] clk-bcm2835: Add claim-clocks property
-
-The claim-clocks property can be used to prevent PLLs and dividers
-from being marked as critical. It contains a vector of clock IDs,
-as defined by dt-bindings/clock/bcm2835.h.
-
-Use this mechanism to claim PLLD_DSI0, PLLD_DSI1, PLLH_AUX and
-PLLH_PIX for the vc4_kms_v3d driver.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/clk/bcm/clk-bcm2835.c | 34 ++++++++++++++++++++++++++++++++--
- 1 file changed, 32 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/bcm/clk-bcm2835.c
-+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -1329,6 +1329,8 @@ static const struct clk_ops bcm2835_vpu_
- 	.debug_init = bcm2835_clock_debug_init,
- };
- 
-+static bool bcm2835_clk_is_claimed(const char *name);
-+
- static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
- 					   const struct bcm2835_pll_data *data)
- {
-@@ -1345,6 +1347,9 @@ static struct clk_hw *bcm2835_register_p
- 	init.ops = &bcm2835_pll_clk_ops;
- 	init.flags = CLK_IGNORE_UNUSED;
- 
-+	if (!bcm2835_clk_is_claimed(data->name))
-+		init.flags |= CLK_IS_CRITICAL;
-+
- 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- 	if (!pll)
- 		return NULL;
-@@ -1398,8 +1403,10 @@ bcm2835_register_pll_divider(struct bcm2
- 	divider->div.table = NULL;
- 
- 	if (!(cprman_read(cprman, data->cm_reg) & data->hold_mask)) {
--		init.flags |= CLK_IS_CRITICAL;
--		divider->div.flags |= CLK_IS_CRITICAL;
-+		if (!bcm2835_clk_is_claimed(data->source_pll))
-+			init.flags |= CLK_IS_CRITICAL;
-+		if (!bcm2835_clk_is_claimed(data->name))
-+			divider->div.flags |= CLK_IS_CRITICAL;
- 	}
- 
- 	divider->cprman = cprman;
-@@ -2152,6 +2159,8 @@ static const struct bcm2835_clk_desc clk
- 		.ctl_reg = CM_PERIICTL),
- };
- 
-+static bool bcm2835_clk_claimed[ARRAY_SIZE(clk_desc_array)];
-+
- /*
-  * Permanently take a reference on the parent of the SDRAM clock.
-  *
-@@ -2171,6 +2180,19 @@ static int bcm2835_mark_sdc_parent_criti
- 	return clk_prepare_enable(parent);
- }
- 
-+static bool bcm2835_clk_is_claimed(const char *name)
-+{
-+	int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) {
-+		const char *clk_name = *(const char **)(clk_desc_array[i].data);
-+		if (!strcmp(name, clk_name))
-+		    return bcm2835_clk_claimed[i];
-+	}
-+
-+	return false;
-+}
-+
- static int bcm2835_clk_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
-@@ -2180,6 +2202,7 @@ static int bcm2835_clk_probe(struct plat
- 	const struct bcm2835_clk_desc *desc;
- 	const size_t asize = ARRAY_SIZE(clk_desc_array);
- 	size_t i;
-+	u32 clk_id;
- 	int ret;
- 
- 	cprman = devm_kzalloc(dev, sizeof(*cprman) +
-@@ -2195,6 +2218,13 @@ static int bcm2835_clk_probe(struct plat
- 	if (IS_ERR(cprman->regs))
- 		return PTR_ERR(cprman->regs);
- 
-+	memset(bcm2835_clk_claimed, 0, sizeof(bcm2835_clk_claimed));
-+	for (i = 0;
-+	     !of_property_read_u32_index(pdev->dev.of_node, "claim-clocks",
-+					 i, &clk_id);
-+	     i++)
-+		bcm2835_clk_claimed[clk_id]= true;
-+
- 	memcpy(cprman->real_parent_names, cprman_parent_names,
- 	       sizeof(cprman_parent_names));
- 	of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
diff --git a/target/linux/brcm2708/patches-4.14/950-0028-clk-bcm2835-Read-max-core-clock-from-firmware.patch b/target/linux/brcm2708/patches-4.14/950-0028-clk-bcm2835-Read-max-core-clock-from-firmware.patch
deleted file mode 100644
index b232c0c13..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0028-clk-bcm2835-Read-max-core-clock-from-firmware.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From a3927566a6d90268423ae58aad12a71b9bf39dd9 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 6 Mar 2017 09:06:18 +0000
-Subject: [PATCH 028/454] clk-bcm2835: Read max core clock from firmware
-
-The VPU is responsible for managing the core clock, usually under
-direction from the bcm2835-cpufreq driver but not via the clk-bcm2835
-driver. Since the core frequency can change without warning, it is
-safer to report the maximum clock rate to users of the core clock -
-I2C, SPI and the mini UART - to err on the safe side when calculating
-clock divisors.
-
-If the DT node for the clock driver includes a reference to the
-firmware node, use the firmware API to query the maximum core clock
-instead of reading the divider registers.
-
-Prior to this patch, a "100KHz" I2C bus was sometimes clocked at about
-160KHz. In particular, switching to the 4.9 kernel was likely to break
-SenseHAT usage on a Pi3.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/clk/bcm/clk-bcm2835.c | 39 ++++++++++++++++++++++++++++++++++-
- 1 file changed, 38 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/bcm/clk-bcm2835.c
-+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -45,6 +45,7 @@
- #include <linux/platform_device.h>
- #include <linux/slab.h>
- #include <dt-bindings/clock/bcm2835.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
- 
- #define CM_PASSWORD		0x5a000000
- 
-@@ -299,6 +300,8 @@
- #define LOCK_TIMEOUT_NS		100000000
- #define BCM2835_MAX_FB_RATE	1750000000u
- 
-+#define VCMSG_ID_CORE_CLOCK     4
-+
- /*
-  * Names of clocks used within the driver that need to be replaced
-  * with an external parent's name.  This array is in the order that
-@@ -317,6 +320,7 @@ static const char *const cprman_parent_n
- struct bcm2835_cprman {
- 	struct device *dev;
- 	void __iomem *regs;
-+	struct rpi_firmware *fw;
- 	spinlock_t regs_lock; /* spinlock for all clocks */
- 
- 	/*
-@@ -1032,6 +1036,30 @@ static unsigned long bcm2835_clock_get_r
- 	return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
- }
- 
-+static unsigned long bcm2835_clock_get_rate_vpu(struct clk_hw *hw,
-+						unsigned long parent_rate)
-+{
-+	struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
-+	struct bcm2835_cprman *cprman = clock->cprman;
-+
-+	if (cprman->fw) {
-+		struct {
-+			u32 id;
-+			u32 val;
-+		} packet;
-+
-+		packet.id = VCMSG_ID_CORE_CLOCK;
-+		packet.val = 0;
-+
-+		if (!rpi_firmware_property(cprman->fw,
-+					   RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
-+					   &packet, sizeof(packet)))
-+			return packet.val;
-+	}
-+
-+	return bcm2835_clock_get_rate(hw, parent_rate);
-+}
-+
- static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
- {
- 	struct bcm2835_cprman *cprman = clock->cprman;
-@@ -1321,7 +1349,7 @@ static int bcm2835_vpu_clock_is_on(struc
-  */
- static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
- 	.is_prepared = bcm2835_vpu_clock_is_on,
--	.recalc_rate = bcm2835_clock_get_rate,
-+	.recalc_rate = bcm2835_clock_get_rate_vpu,
- 	.set_rate = bcm2835_clock_set_rate,
- 	.determine_rate = bcm2835_clock_determine_rate,
- 	.set_parent = bcm2835_clock_set_parent,
-@@ -2201,6 +2229,7 @@ static int bcm2835_clk_probe(struct plat
- 	struct resource *res;
- 	const struct bcm2835_clk_desc *desc;
- 	const size_t asize = ARRAY_SIZE(clk_desc_array);
-+	struct device_node *fw_node;
- 	size_t i;
- 	u32 clk_id;
- 	int ret;
-@@ -2218,6 +2247,14 @@ static int bcm2835_clk_probe(struct plat
- 	if (IS_ERR(cprman->regs))
- 		return PTR_ERR(cprman->regs);
- 
-+	fw_node = of_parse_phandle(dev->of_node, "firmware", 0);
-+	if (fw_node) {
-+		struct rpi_firmware *fw = rpi_firmware_get(NULL);
-+		if (!fw)
-+			return -EPROBE_DEFER;
-+		cprman->fw = fw;
-+	}
-+
- 	memset(bcm2835_clk_claimed, 0, sizeof(bcm2835_clk_claimed));
- 	for (i = 0;
- 	     !of_property_read_u32_index(pdev->dev.of_node, "claim-clocks",
diff --git a/target/linux/brcm2708/patches-4.14/950-0029-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch b/target/linux/brcm2708/patches-4.14/950-0029-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch
deleted file mode 100644
index a1150161f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0029-clk-bcm2835-Mark-GPIO-clocks-enabled-at-boot-as-crit.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 08accfd44328954d33c264402730c1944f1c70fc Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Mon, 9 May 2016 17:28:18 -0700
-Subject: [PATCH 029/454] clk: bcm2835: Mark GPIO clocks enabled at boot as
- critical.
-
-These divide off of PLLD_PER and are used for the ethernet and wifi
-PHYs source PLLs.  Neither of them is currently represented by a phy
-device that would grab the clock for us.
-
-This keeps other drivers from killing the networking PHYs when they
-disable their own clocks and trigger PLLD_PER's refcount going to 0.
-
-v2: Skip marking as critical if they aren't on at boot.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/clk/bcm/clk-bcm2835.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/drivers/clk/bcm/clk-bcm2835.c
-+++ b/drivers/clk/bcm/clk-bcm2835.c
-@@ -1490,6 +1490,15 @@ static struct clk_hw *bcm2835_register_c
- 	init.flags = data->flags | CLK_IGNORE_UNUSED;
- 
- 	/*
-+	 * Some GPIO clocks for ethernet/wifi PLLs are marked as
-+	 * critical (since some platforms use them), but if the
-+	 * firmware didn't have them turned on then they clearly
-+	 * aren't actually critical.
-+	 */
-+	if ((cprman_read(cprman, data->ctl_reg) & CM_ENABLE) == 0)
-+		init.flags &= ~CLK_IS_CRITICAL;
-+
-+	/*
- 	 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
- 	 * rate changes on at least of the parents.
- 	 */
diff --git a/target/linux/brcm2708/patches-4.14/950-0030-sound-Demote-deferral-errors-to-INFO-level.patch b/target/linux/brcm2708/patches-4.14/950-0030-sound-Demote-deferral-errors-to-INFO-level.patch
deleted file mode 100644
index 2efbacd61..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0030-sound-Demote-deferral-errors-to-INFO-level.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 22f73cdb523fbbc9fd20d9e04ade2957f96233d6 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 9 Feb 2017 14:36:44 +0000
-Subject: [PATCH 030/454] sound: Demote deferral errors to INFO level
-
-At present there is no mechanism to specify driver load order,
-which can lead to deferrals and repeated retries until successful.
-Since this situation is expected, reduce the dmesg level to
-INFO and mention that the operation will be retried.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- sound/soc/soc-core.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/sound/soc/soc-core.c
-+++ b/sound/soc/soc-core.c
-@@ -1124,7 +1124,7 @@ static int soc_bind_dai_link(struct snd_
- 	cpu_dai_component.dai_name = dai_link->cpu_dai_name;
- 	rtd->cpu_dai = snd_soc_find_dai(&cpu_dai_component);
- 	if (!rtd->cpu_dai) {
--		dev_err(card->dev, "ASoC: CPU DAI %s not registered\n",
-+		dev_info(card->dev, "ASoC: CPU DAI %s not registered - will retry\n",
- 			dai_link->cpu_dai_name);
- 		goto _err_defer;
- 	}
-@@ -1137,7 +1137,7 @@ static int soc_bind_dai_link(struct snd_
- 	for (i = 0; i < rtd->num_codecs; i++) {
- 		codec_dais[i] = snd_soc_find_dai(&codecs[i]);
- 		if (!codec_dais[i]) {
--			dev_err(card->dev, "ASoC: CODEC DAI %s not registered\n",
-+			dev_info(card->dev, "ASoC: CODEC DAI %s not registered - will retry\n",
- 				codecs[i].dai_name);
- 			goto _err_defer;
- 		}
diff --git a/target/linux/brcm2708/patches-4.14/950-0031-Update-vfpmodule.c.patch b/target/linux/brcm2708/patches-4.14/950-0031-Update-vfpmodule.c.patch
deleted file mode 100644
index 6647e5a4f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0031-Update-vfpmodule.c.patch
+++ /dev/null
@@ -1,138 +0,0 @@
-From 5abe6a0ebe150f320a4ca0ed73b2e15fca1b16fd Mon Sep 17 00:00:00 2001
-From: Claggy3 <stephen.maclagan@hotmail.com>
-Date: Sat, 11 Feb 2017 14:00:30 +0000
-Subject: [PATCH 031/454] Update vfpmodule.c
-
-Christopher Alexander Tobias Schulze - May 2, 2015, 11:57 a.m.
-This patch fixes a problem with VFP state save and restore related
-to exception handling (panic with message "BUG: unsupported FP
-instruction in kernel mode") present on VFP11 floating point units
-(as used with ARM1176JZF-S CPUs, e.g. on first generation Raspberry
-Pi boards). This patch was developed and discussed on
-
-   https://github.com/raspberrypi/linux/issues/859
-
-A precondition to see the crashes is that floating point exception
-traps are enabled. In this case, the VFP11 might determine that a FPU
-operation needs to trap at a point in time when it is not possible to
-signal this to the ARM11 core any more. The VFP11 will then set the
-FPEXC.EX bit and store the trapped opcode in FPINST. (In some cases,
-a second opcode might have been accepted by the VFP11 before the
-exception was detected and could be reported to the ARM11 - in this
-case, the VFP11 also sets FPEXC.FP2V and stores the second opcode in
-FPINST2.)
-
-If FPEXC.EX is set, the VFP11 will "bounce" the next FPU opcode issued
-by the ARM11 CPU, which will be seen by the ARM11 as an undefined opcode
-trap. The VFP support code examines the FPEXC.EX and FPEXC.FP2V bits
-to decide what actions to take, i.e., whether to emulate the opcodes
-found in FPINST and FPINST2, and whether to retry the bounced instruction.
-
-If a user space application has left the VFP11 in this "pending trap"
-state, the next FPU opcode issued to the VFP11 might actually be the
-VSTMIA operation vfp_save_state() uses to store the FPU registers
-to memory (in our test cases, when building the signal stack frame).
-In this case, the kernel crashes as described above.
-
-This patch fixes the problem by making sure that vfp_save_state() is
-always entered with FPEXC.EX cleared. (The current value of FPEXC has
-already been saved, so this does not corrupt the context. Clearing
-FPEXC.EX has no effects on FPINST or FPINST2. Also note that many
-callers already modify FPEXC by setting FPEXC.EN before invoking
-vfp_save_state().)
-
-This patch also addresses a second problem related to FPEXC.EX: After
-returning from signal handling, the kernel reloads the VFP context
-from the user mode stack. However, the current code explicitly clears
-both FPEXC.EX and FPEXC.FP2V during reload. As VFP11 requires these
-bits to be preserved, this patch disables clearing them for VFP
-implementations belonging to architecture 1. There should be no
-negative side effects: the user can set both bits by executing FPU
-opcodes anyway, and while user code may now place arbitrary values
-into FPINST and FPINST2 (e.g., non-VFP ARM opcodes) the VFP support
-code knows which instructions can be emulated, and rejects other
-opcodes with "unhandled bounce" messages, so there should be no
-security impact from allowing reloading FPEXC.EX and FPEXC.FP2V.
-
-Signed-off-by: Christopher Alexander Tobias Schulze <cat.schulze@alice-dsl.net>
----
- arch/arm/vfp/vfpmodule.c | 26 ++++++++++++++++++++------
- 1 file changed, 20 insertions(+), 6 deletions(-)
-
---- a/arch/arm/vfp/vfpmodule.c
-+++ b/arch/arm/vfp/vfpmodule.c
-@@ -179,8 +179,11 @@ static int vfp_notifier(struct notifier_
- 		 * case the thread migrates to a different CPU. The
- 		 * restoring is done lazily.
- 		 */
--		if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu])
-+		if ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) {
-+			/* vfp_save_state oopses on VFP11 if EX bit set */
-+			fmxr(FPEXC, fpexc & ~FPEXC_EX);
- 			vfp_save_state(vfp_current_hw_state[cpu], fpexc);
-+		}
- #endif
- 
- 		/*
-@@ -463,13 +466,16 @@ static int vfp_pm_suspend(void)
- 	/* if vfp is on, then save state for resumption */
- 	if (fpexc & FPEXC_EN) {
- 		pr_debug("%s: saving vfp state\n", __func__);
-+		/* vfp_save_state oopses on VFP11 if EX bit set */
-+		fmxr(FPEXC, fpexc & ~FPEXC_EX);
- 		vfp_save_state(&ti->vfpstate, fpexc);
- 
- 		/* disable, just in case */
- 		fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
- 	} else if (vfp_current_hw_state[ti->cpu]) {
- #ifndef CONFIG_SMP
--		fmxr(FPEXC, fpexc | FPEXC_EN);
-+		/* vfp_save_state oopses on VFP11 if EX bit set */
-+		fmxr(FPEXC, (fpexc & ~FPEXC_EX) | FPEXC_EN);
- 		vfp_save_state(vfp_current_hw_state[ti->cpu], fpexc);
- 		fmxr(FPEXC, fpexc);
- #endif
-@@ -532,7 +538,8 @@ void vfp_sync_hwstate(struct thread_info
- 		/*
- 		 * Save the last VFP state on this CPU.
- 		 */
--		fmxr(FPEXC, fpexc | FPEXC_EN);
-+		/* vfp_save_state oopses on VFP11 if EX bit set */
-+		fmxr(FPEXC, (fpexc & ~FPEXC_EX) | FPEXC_EN);
- 		vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN);
- 		fmxr(FPEXC, fpexc);
- 	}
-@@ -602,6 +609,8 @@ int vfp_restore_user_hwstate(struct user
- 	struct thread_info *thread = current_thread_info();
- 	struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
- 	unsigned long fpexc;
-+	int err = 0;
-+	u32 fpsid = fmrx(FPSID);
- 
- 	/* Disable VFP to avoid corrupting the new thread state. */
- 	vfp_flush_hwstate(thread);
-@@ -624,8 +633,12 @@ int vfp_restore_user_hwstate(struct user
- 	/* Ensure the VFP is enabled. */
- 	fpexc |= FPEXC_EN;
- 
--	/* Ensure FPINST2 is invalid and the exception flag is cleared. */
--	fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
-+	/* Mask FPXEC_EX and FPEXC_FP2V if not required by VFP arch */
-+	if ((fpsid & FPSID_ARCH_MASK) != (1 << FPSID_ARCH_BIT)) {
-+		/* Ensure FPINST2 is invalid and the exception flag is cleared. */
-+		fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
-+	}
-+
- 	hwstate->fpexc = fpexc;
- 
- 	hwstate->fpinst = ufp_exc->fpinst;
-@@ -695,7 +708,8 @@ void kernel_neon_begin(void)
- 	cpu = get_cpu();
- 
- 	fpexc = fmrx(FPEXC) | FPEXC_EN;
--	fmxr(FPEXC, fpexc);
-+	/* vfp_save_state oopses on VFP11 if EX bit set */
-+	fmxr(FPEXC, fpexc & ~FPEXC_EX);
- 
- 	/*
- 	 * Save the userland NEON/VFP state. Under UP,
diff --git a/target/linux/brcm2708/patches-4.14/950-0032-ASoC-bcm2835_i2s.c-relax-the-ch2-register-setting-fo.patch b/target/linux/brcm2708/patches-4.14/950-0032-ASoC-bcm2835_i2s.c-relax-the-ch2-register-setting-fo.patch
deleted file mode 100644
index 74f627dc3..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0032-ASoC-bcm2835_i2s.c-relax-the-ch2-register-setting-fo.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 3221c46961b4dcc88791f4a80dc8bd503c6cfe00 Mon Sep 17 00:00:00 2001
-From: Matt Flax <flatmax@flatmax.org>
-Date: Wed, 8 Mar 2017 21:13:24 +1100
-Subject: [PATCH 032/454] ASoC: bcm2835_i2s.c: relax the ch2 register setting
- for 8 channels
-
-This patch allows ch2 registers to be set for 8 channels of audio.
----
- sound/soc/bcm/bcm2835-i2s.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/sound/soc/bcm/bcm2835-i2s.c
-+++ b/sound/soc/bcm/bcm2835-i2s.c
-@@ -312,6 +312,7 @@ static int bcm2835_i2s_hw_params(struct
- 
- 	switch (params_channels(params)) {
- 	case 2:
-+	case 8:
- 		format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
- 		format |= BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(ch1pos));
- 		format |= BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(ch2pos));
diff --git a/target/linux/brcm2708/patches-4.14/950-0033-i2c-bcm2835-Add-debug-support.patch b/target/linux/brcm2708/patches-4.14/950-0033-i2c-bcm2835-Add-debug-support.patch
deleted file mode 100644
index f740fb587..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0033-i2c-bcm2835-Add-debug-support.patch
+++ /dev/null
@@ -1,189 +0,0 @@
-From 390de19e8520898d19726ffa3d9a420349342442 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Tue, 1 Nov 2016 15:15:41 +0100
-Subject: [PATCH 033/454] i2c: bcm2835: Add debug support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This adds a debug module parameter to aid in debugging transfer issues
-by printing info to the kernel log. When enabled, status values are
-collected in the interrupt routine and msg info in
-bcm2835_i2c_start_transfer(). This is done in a way that tries to avoid
-affecting timing. Having printk in the isr can mask issues.
-
-debug values (additive):
-1: Print info on error
-2: Print info on all transfers
-3: Print messages before transfer is started
-
-The value can be changed at runtime:
-/sys/module/i2c_bcm2835/parameters/debug
-
-Example output, debug=3:
-[  747.114448] bcm2835_i2c_xfer: msg(1/2) write addr=0x54, len=2 flags= [i2c1]
-[  747.114463] bcm2835_i2c_xfer: msg(2/2) read addr=0x54, len=32 flags= [i2c1]
-[  747.117809] start_transfer: msg(1/2) write addr=0x54, len=2 flags= [i2c1]
-[  747.117825] isr: remain=2, status=0x30000055 : TA TXW TXD TXE  [i2c1]
-[  747.117839] start_transfer: msg(2/2) read addr=0x54, len=32 flags= [i2c1]
-[  747.117849] isr: remain=32, status=0xd0000039 : TA RXR TXD RXD  [i2c1]
-[  747.117861] isr: remain=20, status=0xd0000039 : TA RXR TXD RXD  [i2c1]
-[  747.117870] isr: remain=8, status=0x32 : DONE TXD RXD  [i2c1]
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/i2c/busses/i2c-bcm2835.c | 99 +++++++++++++++++++++++++++++++-
- 1 file changed, 98 insertions(+), 1 deletion(-)
-
---- a/drivers/i2c/busses/i2c-bcm2835.c
-+++ b/drivers/i2c/busses/i2c-bcm2835.c
-@@ -56,6 +56,18 @@
- #define BCM2835_I2C_CDIV_MIN	0x0002
- #define BCM2835_I2C_CDIV_MAX	0xFFFE
- 
-+static unsigned int debug;
-+module_param(debug, uint, 0644);
-+MODULE_PARM_DESC(debug, "1=err, 2=isr, 3=xfer");
-+
-+#define BCM2835_DEBUG_MAX	512
-+struct bcm2835_debug {
-+	struct i2c_msg *msg;
-+	int msg_idx;
-+	size_t remain;
-+	u32 status;
-+};
-+
- struct bcm2835_i2c_dev {
- 	struct device *dev;
- 	void __iomem *regs;
-@@ -69,8 +81,78 @@ struct bcm2835_i2c_dev {
- 	u32 msg_err;
- 	u8 *msg_buf;
- 	size_t msg_buf_remaining;
-+	struct bcm2835_debug debug[BCM2835_DEBUG_MAX];
-+	unsigned int debug_num;
-+	unsigned int debug_num_msgs;
- };
- 
-+static inline void bcm2835_debug_add(struct bcm2835_i2c_dev *i2c_dev, u32 s)
-+{
-+	if (!i2c_dev->debug_num_msgs || i2c_dev->debug_num >= BCM2835_DEBUG_MAX)
-+		return;
-+
-+	i2c_dev->debug[i2c_dev->debug_num].msg = i2c_dev->curr_msg;
-+	i2c_dev->debug[i2c_dev->debug_num].msg_idx =
-+				i2c_dev->debug_num_msgs - i2c_dev->num_msgs;
-+	i2c_dev->debug[i2c_dev->debug_num].remain = i2c_dev->msg_buf_remaining;
-+	i2c_dev->debug[i2c_dev->debug_num].status = s;
-+	i2c_dev->debug_num++;
-+}
-+
-+static void bcm2835_debug_print_status(struct bcm2835_i2c_dev *i2c_dev,
-+				       struct bcm2835_debug *d)
-+{
-+	u32 s = d->status;
-+
-+	pr_info("isr: remain=%zu, status=0x%x : %s%s%s%s%s%s%s%s%s%s [i2c%d]\n",
-+		d->remain, s,
-+		s & BCM2835_I2C_S_TA ? "TA " : "",
-+		s & BCM2835_I2C_S_DONE ? "DONE " : "",
-+		s & BCM2835_I2C_S_TXW ? "TXW " : "",
-+		s & BCM2835_I2C_S_RXR ? "RXR " : "",
-+		s & BCM2835_I2C_S_TXD ? "TXD " : "",
-+		s & BCM2835_I2C_S_RXD ? "RXD " : "",
-+		s & BCM2835_I2C_S_TXE ? "TXE " : "",
-+		s & BCM2835_I2C_S_RXF ? "RXF " : "",
-+		s & BCM2835_I2C_S_ERR ? "ERR " : "",
-+		s & BCM2835_I2C_S_CLKT ? "CLKT " : "",
-+		i2c_dev->adapter.nr);
-+}
-+
-+static void bcm2835_debug_print_msg(struct bcm2835_i2c_dev *i2c_dev,
-+				    struct i2c_msg *msg, int i, int total,
-+				    const char *fname)
-+{
-+	pr_info("%s: msg(%d/%d) %s addr=0x%02x, len=%u flags=%s%s%s%s%s%s%s [i2c%d]\n",
-+		fname, i, total,
-+		msg->flags & I2C_M_RD ? "read" : "write", msg->addr, msg->len,
-+		msg->flags & I2C_M_TEN ? "TEN" : "",
-+		msg->flags & I2C_M_RECV_LEN ? "RECV_LEN" : "",
-+		msg->flags & I2C_M_NO_RD_ACK ? "NO_RD_ACK" : "",
-+		msg->flags & I2C_M_IGNORE_NAK ? "IGNORE_NAK" : "",
-+		msg->flags & I2C_M_REV_DIR_ADDR ? "REV_DIR_ADDR" : "",
-+		msg->flags & I2C_M_NOSTART ? "NOSTART" : "",
-+		msg->flags & I2C_M_STOP ? "STOP" : "",
-+		i2c_dev->adapter.nr);
-+}
-+
-+static void bcm2835_debug_print(struct bcm2835_i2c_dev *i2c_dev)
-+{
-+	struct bcm2835_debug *d;
-+	unsigned int i;
-+
-+	for (i = 0; i < i2c_dev->debug_num; i++) {
-+		d = &i2c_dev->debug[i];
-+		if (d->status == ~0)
-+			bcm2835_debug_print_msg(i2c_dev, d->msg, d->msg_idx,
-+				i2c_dev->debug_num_msgs, "start_transfer");
-+		else
-+			bcm2835_debug_print_status(i2c_dev, d);
-+	}
-+	if (i2c_dev->debug_num >= BCM2835_DEBUG_MAX)
-+		pr_info("BCM2835_DEBUG_MAX reached\n");
-+}
-+
- static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,
- 				      u32 reg, u32 val)
- {
-@@ -189,6 +271,7 @@ static void bcm2835_i2c_start_transfer(s
- 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);
- 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);
- 	bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);
-+	bcm2835_debug_add(i2c_dev, ~0);
- }
- 
- /*
-@@ -206,6 +289,7 @@ static irqreturn_t bcm2835_i2c_isr(int t
- 	u32 val, err;
- 
- 	val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
-+	bcm2835_debug_add(i2c_dev, val);
- 
- 	err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
- 	if (err) {
-@@ -272,6 +356,13 @@ static int bcm2835_i2c_xfer(struct i2c_a
- 	unsigned long time_left;
- 	int i, ret;
- 
-+	if (debug)
-+		i2c_dev->debug_num_msgs = num;
-+
-+	if (debug > 2)
-+		for (i = 0; i < num; i++)
-+			bcm2835_debug_print_msg(i2c_dev, &msgs[i], i + 1, num, __func__);
-+
- 	for (i = 0; i < (num - 1); i++)
- 		if (msgs[i].flags & I2C_M_RD) {
- 			dev_warn_once(i2c_dev->dev,
-@@ -291,6 +382,10 @@ static int bcm2835_i2c_xfer(struct i2c_a
- 
- 	time_left = wait_for_completion_timeout(&i2c_dev->completion,
- 						adap->timeout);
-+	if (debug > 1 || (debug && (!time_left || i2c_dev->msg_err)))
-+		bcm2835_debug_print(i2c_dev);
-+	i2c_dev->debug_num_msgs = 0;
-+	i2c_dev->debug_num = 0;
- 	if (!time_left) {
- 		bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,
- 				   BCM2835_I2C_C_CLEAR);
-@@ -301,7 +396,9 @@ static int bcm2835_i2c_xfer(struct i2c_a
- 	if (!i2c_dev->msg_err)
- 		return num;
- 
--	dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err);
-+	if (debug)
-+		dev_err(i2c_dev->dev, "i2c transfer failed: %x\n",
-+			i2c_dev->msg_err);
- 
- 	if (i2c_dev->msg_err & BCM2835_I2C_S_ERR)
- 		return -EREMOTEIO;
diff --git a/target/linux/brcm2708/patches-4.14/950-0034-mm-Remove-the-PFN-busy-warning.patch b/target/linux/brcm2708/patches-4.14/950-0034-mm-Remove-the-PFN-busy-warning.patch
deleted file mode 100644
index 98b6f0174..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0034-mm-Remove-the-PFN-busy-warning.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 311430df64b6d7992d1fbde8dab4995bcb082a9b Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Thu, 18 Dec 2014 16:07:15 -0800
-Subject: [PATCH 034/454] mm: Remove the PFN busy warning
-
-See commit dae803e165a11bc88ca8dbc07a11077caf97bbcb -- the warning is
-expected sometimes when using CMA.  However, that commit still spams
-my kernel log with these warnings.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- mm/page_alloc.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/mm/page_alloc.c
-+++ b/mm/page_alloc.c
-@@ -7618,8 +7618,6 @@ int alloc_contig_range(unsigned long sta
- 
- 	/* Make sure the range is really isolated. */
- 	if (test_pages_isolated(outer_start, end, false)) {
--		pr_info_ratelimited("%s: [%lx, %lx) PFNs busy\n",
--			__func__, outer_start, end);
- 		ret = -EBUSY;
- 		goto done;
- 	}
diff --git a/target/linux/brcm2708/patches-4.14/950-0035-ASoC-Add-prompt-for-ICS43432-codec.patch b/target/linux/brcm2708/patches-4.14/950-0035-ASoC-Add-prompt-for-ICS43432-codec.patch
deleted file mode 100644
index 043d80b71..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0035-ASoC-Add-prompt-for-ICS43432-codec.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 138508ce754d2451be8583fca4484056fe720e97 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 23 Mar 2017 10:06:56 +0000
-Subject: [PATCH 035/454] ASoC: Add prompt for ICS43432 codec
-
-Without a prompt string, a config setting can't be included in a
-defconfig. Give CONFIG_SND_SOC_ICS43432 a prompt so that Pi soundcards
-can use the driver.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- sound/soc/codecs/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/sound/soc/codecs/Kconfig
-+++ b/sound/soc/codecs/Kconfig
-@@ -579,7 +579,7 @@ config SND_SOC_HDAC_HDMI
- 	select HDMI
- 
- config SND_SOC_ICS43432
--	tristate
-+	tristate "InvenSense ICS43432 I2S microphone codec"
- 
- config SND_SOC_INNO_RK3036
- 	tristate "Inno codec driver for RK3036 SoC"
diff --git a/target/linux/brcm2708/patches-4.14/950-0036-Main-bcm2708-bcm2709-linux-port.patch b/target/linux/brcm2708/patches-4.14/950-0036-Main-bcm2708-bcm2709-linux-port.patch
deleted file mode 100644
index 27c92c42e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0036-Main-bcm2708-bcm2709-linux-port.patch
+++ /dev/null
@@ -1,180 +0,0 @@
-From 456ed3c197e8aec439ebeca39060c204d2429896 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Sun, 12 May 2013 12:24:19 +0100
-Subject: [PATCH 036/454] Main bcm2708/bcm2709 linux port
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-bcm2709: Drop platform smp and timer init code
-
-irq-bcm2836 handles this through these functions:
-bcm2835_init_local_timer_frequency()
-bcm2836_arm_irqchip_smp_init()
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-bcm270x: Use watchdog for reboot/poweroff
-
-The watchdog driver already has support for reboot/poweroff.
-Make use of this and remove the code from the platform files.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- arch/arm/mach-bcm/Kconfig         |  1 +
- arch/arm/mach-bcm/board_bcm2835.c |  9 +++++++++
- arch/arm/mm/proc-v6.S             | 15 ++++++++++++---
- drivers/irqchip/irq-bcm2835.c     |  7 ++++++-
- drivers/mailbox/bcm2835-mailbox.c | 18 ++++++++++++++++--
- 5 files changed, 44 insertions(+), 6 deletions(-)
-
---- a/arch/arm/mach-bcm/Kconfig
-+++ b/arch/arm/mach-bcm/Kconfig
-@@ -158,6 +158,7 @@ config ARCH_BCM2835
- 	select FIQ
- 	select PINCTRL
- 	select PINCTRL_BCM2835
-+	select MFD_SYSCON if ARCH_MULTI_V7
- 	help
- 	  This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
- 	  This SoC is used in the Raspberry Pi and Roku 2 devices.
---- a/arch/arm/mach-bcm/board_bcm2835.c
-+++ b/arch/arm/mach-bcm/board_bcm2835.c
-@@ -21,6 +21,8 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- 
-+#include <linux/dma-mapping.h>
-+
- static void __init bcm2835_init(void)
- {
- 	struct device_node *np = of_find_node_by_path("/system");
-@@ -35,6 +37,12 @@ static void __init bcm2835_init(void)
- 		system_serial_low = val64;
- }
- 
-+static void __init bcm2835_init_early(void)
-+{
-+	/* dwc_otg needs this for bounce buffers on non-aligned transfers */
-+	init_dma_coherent_pool_size(SZ_1M);
-+}
-+
- static const char * const bcm2835_compat[] = {
- #ifdef CONFIG_ARCH_MULTI_V6
- 	"brcm,bcm2835",
-@@ -47,5 +55,6 @@ static const char * const bcm2835_compat
- 
- DT_MACHINE_START(BCM2835, "BCM2835")
- 	.init_machine = bcm2835_init,
-+	.init_early = bcm2835_init_early,
- 	.dt_compat = bcm2835_compat
- MACHINE_END
---- a/arch/arm/mm/proc-v6.S
-+++ b/arch/arm/mm/proc-v6.S
-@@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
-  *
-  *	IRQs are already disabled.
-  */
-+
-+/* See jira SW-5991 for details of this workaround */
- ENTRY(cpu_v6_do_idle)
--	mov	r1, #0
--	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
--	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
-+	.align 5
-+	mov     r1, #2
-+1:	subs	r1, #1
-+	nop
-+	mcreq	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
-+	mcreq	p15, 0, r1, c7, c0, 4		@ wait for interrupt
-+	nop
-+	nop
-+	nop
-+	bne 1b
- 	ret	lr
- 
- ENTRY(cpu_v6_dcache_clean_area)
---- a/drivers/irqchip/irq-bcm2835.c
-+++ b/drivers/irqchip/irq-bcm2835.c
-@@ -54,7 +54,9 @@
- #include <linux/regmap.h>
- 
- #include <asm/exception.h>
-+#ifndef CONFIG_ARM64
- #include <asm/mach/irq.h>
-+#endif
- 
- /* Put the bank and irq (32 bits) into the hwirq */
- #define MAKE_HWIRQ(b, n)	(((b) << 5) | (n))
-@@ -82,6 +84,7 @@
- #define NR_BANKS		3
- #define IRQS_PER_BANK		32
- #define NUMBER_IRQS		MAKE_HWIRQ(NR_BANKS, 0)
-+#undef FIQ_START
- #define FIQ_START		(NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))
- 
- static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
-@@ -255,10 +258,12 @@ static int __init armctrl_of_init(struct
- 					MAKE_HWIRQ(b, i) + NUMBER_IRQS);
- 			BUG_ON(irq <= 0);
- 			irq_set_chip(irq, &armctrl_chip);
--			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-+			irq_set_probe(irq);
- 		}
- 	}
-+#ifndef CONFIG_ARM64
- 	init_FIQ(FIQ_START);
-+#endif
- 
- 	return 0;
- }
---- a/drivers/mailbox/bcm2835-mailbox.c
-+++ b/drivers/mailbox/bcm2835-mailbox.c
-@@ -51,12 +51,15 @@
- #define MAIL1_WRT	(ARM_0_MAIL1 + 0x00)
- #define MAIL1_STA	(ARM_0_MAIL1 + 0x18)
- 
-+/* On ARCH_BCM270x these come through <linux/interrupt.h> (arm_control.h ) */
-+#ifndef ARM_MS_FULL
- /* Status register: FIFO state. */
- #define ARM_MS_FULL		BIT(31)
- #define ARM_MS_EMPTY		BIT(30)
- 
- /* Configuration register: Enable interrupts. */
- #define ARM_MC_IHAVEDATAIRQEN	BIT(0)
-+#endif
- 
- struct bcm2835_mbox {
- 	void __iomem *regs;
-@@ -151,7 +154,7 @@ static int bcm2835_mbox_probe(struct pla
- 		return -ENOMEM;
- 	spin_lock_init(&mbox->lock);
- 
--	ret = devm_request_irq(dev, irq_of_parse_and_map(dev->of_node, 0),
-+	ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
- 			       bcm2835_mbox_irq, 0, dev_name(dev), mbox);
- 	if (ret) {
- 		dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n",
-@@ -209,7 +212,18 @@ static struct platform_driver bcm2835_mb
- 	.probe		= bcm2835_mbox_probe,
- 	.remove		= bcm2835_mbox_remove,
- };
--module_platform_driver(bcm2835_mbox_driver);
-+
-+static int __init bcm2835_mbox_init(void)
-+{
-+	return platform_driver_register(&bcm2835_mbox_driver);
-+}
-+arch_initcall(bcm2835_mbox_init);
-+
-+static void __init bcm2835_mbox_exit(void)
-+{
-+	platform_driver_unregister(&bcm2835_mbox_driver);
-+}
-+module_exit(bcm2835_mbox_exit);
- 
- MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
- MODULE_DESCRIPTION("BCM2835 mailbox IPC driver");
diff --git a/target/linux/brcm2708/patches-4.14/950-0037-Add-dwc_otg-driver.patch b/target/linux/brcm2708/patches-4.14/950-0037-Add-dwc_otg-driver.patch
deleted file mode 100644
index 49a291702..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0037-Add-dwc_otg-driver.patch
+++ /dev/null
@@ -1,61098 +0,0 @@
-From 451dab6b675762f8889979b04ee3e529eee915e8 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Wed, 1 May 2013 19:46:17 +0100
-Subject: [PATCH 037/454] Add dwc_otg driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
-
-usb: dwc: fix lockdep false positive
-
-Signed-off-by: Kari Suvanto <karis79@gmail.com>
-
-usb: dwc: fix inconsistent lock state
-
-Signed-off-by: Kari Suvanto <karis79@gmail.com>
-
-Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance.
-Thanks to Gordon and Costas
-
-Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005.
-
-Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh
-
-Make sure we wait for the reset to finish
-
-dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel
-	 memory corruption, escalating to OOPS under high USB load.
-
-dwc_otg: Fix unsafe access of QTD during URB enqueue
-
-In dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the
-transaction could complete almost immediately after the qtd was assigned
-to a host channel during URB enqueue, which meant the qtd pointer was no
-longer valid having been completed and removed. Usually, this resulted in
-an OOPS during URB submission. By predetermining whether transactions
-need to be queued or not, this unsafe pointer access is avoided.
-
-This bug was only evident on the Pi model A where a device was attached
-that had no periodic endpoints (e.g. USB pendrive or some wlan devices).
-
-dwc_otg: Fix incorrect URB allocation error handling
-
-If the memory allocation for a dwc_otg_urb failed, the kernel would OOPS
-because for some reason a member of the *unallocated* struct was set to
-zero. Error handling changed to fail correctly.
-
-dwc_otg: fix potential use-after-free case in interrupt handler
-
-If a transaction had previously aborted, certain interrupts are
-enabled to track error counts and reset where necessary. On IN
-endpoints the host generates an ACK interrupt near-simultaneously
-with completion of transfer. In the case where this transfer had
-previously had an error, this results in a use-after-free on
-the QTD memory space with a 1-byte length being overwritten to
-0x00.
-
-dwc_otg: add handling of SPLIT transaction data toggle errors
-
-Previously a data toggle error on packets from a USB1.1 device behind
-a TT would result in the Pi locking up as the driver never handled
-the associated interrupt. Patch adds basic retry mechanism and
-interrupt acknowledgement to cater for either a chance toggle error or
-for devices that have a broken initial toggle state (FT8U232/FT232BM).
-
-dwc_otg: implement tasklet for returning URBs to usbcore hcd layer
-
-The dwc_otg driver interrupt handler for transfer completion will spend
-a very long time with interrupts disabled when a URB is completed -
-this is because usb_hcd_giveback_urb is called from within the handler
-which for a USB device driver with complicated processing (e.g. webcam)
-will take an exorbitant amount of time to complete. This results in
-missed completion interrupts for other USB packets which lead to them
-being dropped due to microframe overruns.
-
-This patch splits returning the URB to the usb hcd layer into a
-high-priority tasklet. This will have most benefit for isochronous IN
-transfers but will also have incidental benefit where multiple periodic
-devices are active at once.
-
-dwc_otg: fix NAK holdoff and allow on split transactions only
-
-This corrects a bug where if a single active non-periodic endpoint
-had at least one transaction in its qh, on frnum == MAX_FRNUM the qh
-would get skipped and never get queued again. This would result in
-a silent device until error detection (automatic or otherwise) would
-either reset the device or flush and requeue the URBs.
-
-Additionally the NAK holdoff was enabled for all transactions - this
-would potentially stall a HS endpoint for 1ms if a previous error state
-enabled this interrupt and the next response was a NAK. Fix so that
-only split transactions get held off.
-
-dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler
-
-usb_hcd_unlink_urb_from_ep must be called with the HCD lock held.  Calling it
-asynchronously in the tasklet was not safe (regression in
-c4564d4a1a0a9b10d4419e48239f5d99e88d2667).
-
-This change unlinks it from the endpoint prior to queueing it for handling in
-the tasklet, and also adds a check to ensure the urb is OK to be unlinked
-before doing so.
-
-NULL pointer dereference kernel oopses had been observed in usb_hcd_giveback_urb
-when a USB device was unplugged/replugged during data transfer.  This effect
-was reproduced using automated USB port power control, hundreds of replug
-events were performed during active transfers to confirm that the problem was
-eliminated.
-
-USB fix using a FIQ to implement split transactions
-
-This commit adds a FIQ implementaion that schedules
-the split transactions using a FIQ so we don't get
-held off by the interrupt latency of Linux
-
-dwc_otg: fix device attributes and avoid kernel warnings on boot
-
-dcw_otg: avoid logging function that can cause panics
-
-See: https://github.com/raspberrypi/firmware/issues/21
-Thanks to cleverca22 for fix
-
-dwc_otg: mask correct interrupts after transaction error recovery
-
-The dwc_otg driver will unmask certain interrupts on a transaction
-that previously halted in the error state in order to reset the
-QTD error count. The various fine-grained interrupt handlers do not
-consider that other interrupts besides themselves were unmasked.
-
-By disabling the two other interrupts only ever enabled in DMA mode
-for this purpose, we can avoid unnecessary function calls in the
-IRQ handler. This will also prevent an unneccesary FIQ interrupt
-from being generated if the FIQ is enabled.
-
-dwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ
-
-In the case of a transaction to a device that had previously aborted
-due to an error, several interrupts are enabled to reset the error
-count when a device responds. This has the side-effect of making the
-FIQ thrash because the hardware will generate multiple instances of
-a NAK on an IN bulk/interrupt endpoint and multiple instances of ACK
-on an OUT bulk/interrupt endpoint. Make the FIQ mask and clear the
-associated interrupts.
-
-Additionally, on non-split transactions make sure that only unmasked
-interrupts are cleared. This caused a hard-to-trigger but serious
-race condition when you had the combination of an endpoint awaiting
-error recovery and a transaction completed on an endpoint - due to
-the sequencing and timing of interrupts generated by the dwc_otg core,
-it was possible to confuse the IRQ handler.
-
-Fix function tracing
-
-dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue
-
-dwc_otg: prevent OOPSes during device disconnects
-
-The dwc_otg_urb_enqueue function is thread-unsafe. In particular the
-access of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and
-friends does not occur within a critical section and so if a device
-was unplugged during activity there was a high chance that the
-usbcore hub_thread would try to disable the endpoint with partially-
-formed entries in the URB queue. This would result in BUG() or null
-pointer dereferences.
-
-Fix so that access of urb->hcpriv, enqueuing to the hardware and
-adding to usbcore endpoint URB lists is contained within a single
-critical section.
-
-dwc_otg: prevent BUG() in TT allocation if hub address is > 16
-
-A fixed-size array is used to track TT allocation. This was
-previously set to 16 which caused a crash because
-dwc_otg_hcd_allocate_port would read past the end of the array.
-
-This was hit if a hub was plugged in which enumerated as addr > 16,
-due to previous device resets or unplugs.
-
-Also add #ifdef FIQ_DEBUG around hcd->hub_port_alloc[], which grows
-to a large size if 128 hub addresses are supported. This field is
-for debug only for tracking which frame an allocate happened in.
-
-dwc_otg: make channel halts with unknown state less damaging
-
-If the IRQ received a channel halt interrupt through the FIQ
-with no other bits set, the IRQ would not release the host
-channel and never complete the URB.
-
-Add catchall handling to treat as a transaction error and retry.
-
-dwc_otg: fiq_split: use TTs with more granularity
-
-This fixes certain issues with split transaction scheduling.
-
-- Isochronous multi-packet OUT transactions now hog the TT until
-  they are completed - this prevents hubs aborting transactions
-  if they get a periodic start-split out-of-order
-- Don't perform TT allocation on non-periodic endpoints - this
-  allows simultaneous use of the TT's bulk/control and periodic
-  transaction buffers
-
-This commit will mainly affect USB audio playback.
-
-dwc_otg: fix potential sleep while atomic during urb enqueue
-
-Fixes a regression introduced with eb1b482a. Kmalloc called from
-dwc_otg_hcd_qtd_add / dwc_otg_hcd_qtd_create did not always have
-the GPF_ATOMIC flag set. Force this flag when inside the larger
-critical section.
-
-dwc_otg: make fiq_split_enable imply fiq_fix_enable
-
-Failing to set up the FIQ correctly would result in
-"IRQ 32: nobody cared" errors in dmesg.
-
-dwc_otg: prevent crashes on host port disconnects
-
-Fix several issues resulting in crashes or inconsistent state
-if a Model A root port was disconnected.
-
-- Clean up queue heads properly in kill_urbs_in_qh_list by
-  removing the empty QHs from the schedule lists
-- Set the halt status properly to prevent IRQ handlers from
-  using freed memory
-- Add fiq_split related cleanup for saved registers
-- Make microframe scheduling reclaim host channels if
-  active during a disconnect
-- Abort URBs with -ESHUTDOWN status response, informing
-  device drivers so they respond in a more correct fashion
-  and don't try to resubmit URBs
-- Prevent IRQ handlers from attempting to handle channel
-  interrupts if the associated URB was dequeued (and the
-  driver state was cleared)
-
-dwc_otg: prevent leaking URBs during enqueue
-
-A dwc_otg_urb would get leaked if the HCD enqueue function
-failed for any reason. Free the URB at the appropriate points.
-
-dwc_otg: Enable NAK holdoff for control split transactions
-
-Certain low-speed devices take a very long time to complete a
-data or status stage of a control transaction, producing NAK
-responses until they complete internal processing - the USB2.0
-spec limit is up to 500mS. This causes the same type of interrupt
-storm as seen with USB-serial dongles prior to c8edb238.
-
-In certain circumstances, usually while booting, this interrupt
-storm could cause SD card timeouts.
-
-dwc_otg: Fix for occasional lockup on boot when doing a USB reset
-
-dwc_otg: Don't issue traffic to LS devices in FS mode
-
-Issuing low-speed packets when the root port is in full-speed mode
-causes the root port to stop responding. Explicitly fail when
-enqueuing URBs to a LS endpoint on a FS bus.
-
-Fix ARM architecture issue with local_irq_restore()
-
-If local_fiq_enable() is called before a local_irq_restore(flags) where
-the flags variable has the F bit set, the FIQ will be erroneously disabled.
-
-Fixup arch_local_irq_restore to avoid trampling the F bit in CPSR.
-
-Also fix some of the hacks previously implemented for previous dwc_otg
-incarnations.
-
-dwc_otg: fiq_fsm: Base commit for driver rewrite
-
-This commit removes the previous FIQ fixes entirely and adds fiq_fsm.
-
-This rewrite features much more complete support for split transactions
-and takes into account several OTG hardware bugs. High-speed
-isochronous transactions are also capable of being performed by fiq_fsm.
-
-All driver options have been removed and replaced with:
-  - dwc_otg.fiq_enable (bool)
-  - dwc_otg.fiq_fsm_enable (bool)
-  - dwc_otg.fiq_fsm_mask (bitmask)
-  - dwc_otg.nak_holdoff (unsigned int)
-
-Defaults are specified such that fiq_fsm behaves similarly to the
-previously implemented FIQ fixes.
-
-fiq_fsm: Push error recovery into the FIQ when fiq_fsm is used
-
-If the transfer associated with a QTD failed due to a bus error, the HCD
-would retry the transfer up to 3 times (implementing the USB2.0
-three-strikes retry in software).
-
-Due to the masking mechanism used by fiq_fsm, it is only possible to pass
-a single interrupt through to the HCD per-transfer.
-
-In this instance host channels would fall off the radar because the error
-reset would function, but the subsequent channel halt would be lost.
-
-Push the error count reset into the FIQ handler.
-
-fiq_fsm: Implement timeout mechanism
-
-For full-speed endpoints with a large packet size, interrupt latency
-runs the risk of the FIQ starting a transaction too late in a full-speed
-frame. If the device is still transmitting data when EOF2 for the
-downstream frame occurs, the hub will disable the port. This change is
-not reflected in the hub status endpoint and the device becomes
-unresponsive.
-
-Prevent high-bandwidth transactions from being started too late in a
-frame. The mechanism is not guaranteed: a combination of bit stuffing
-and hub latency may still result in a device overrunning.
-
-fiq_fsm: fix bounce buffer utilisation for Isochronous OUT
-
-Multi-packet isochronous OUT transactions were subject to a few bounday
-bugs. Fix them.
-
-Audio playback is now much more robust: however, an issue stands with
-devices that have adaptive sinks - ALSA plays samples too fast.
-
-dwc_otg: Return full-speed frame numbers in HS mode
-
-The frame counter increments on every *microframe* in high-speed mode.
-Most device drivers expect this number to be in full-speed frames - this
-caused considerable confusion to e.g. snd_usb_audio which uses the
-frame counter to estimate the number of samples played.
-
-fiq_fsm: save PID on completion of interrupt OUT transfers
-
-Also add edge case handling for interrupt transports.
-
-Note that for periodic split IN, data toggles are unimplemented in the
-OTG host hardware - it unconditionally accepts any PID.
-
-fiq_fsm: add missing case for fiq_fsm_tt_in_use()
-
-Certain combinations of bitrate and endpoint activity could
-result in a periodic transaction erroneously getting started
-while the previous Isochronous OUT was still active.
-
-fiq_fsm: clear hcintmsk for aborted transactions
-
-Prevents the FIQ from erroneously handling interrupts
-on a timed out channel.
-
-fiq_fsm: enable by default
-
-fiq_fsm: fix dequeues for non-periodic split transactions
-
-If a dequeue happened between the SSPLIT and CSPLIT phases of the
-transaction, the HCD would never receive an interrupt.
-
-fiq_fsm: Disable by default
-
-fiq_fsm: Handle HC babble errors
-
-The HCTSIZ transfer size field raises a babble interrupt if
-the counter wraps. Handle the resulting interrupt in this case.
-
-dwc_otg: fix interrupt registration for fiq_enable=0
-
-Additionally make the module parameter conditional for wherever
-hcd->fiq_state is touched.
-
-fiq_fsm: Enable by default
-
-dwc_otg: Fix various issues with root port and transaction errors
-
-Process the host port interrupts correctly (and don't trample them).
-Root port hotplug now functional again.
-
-Fix a few thinkos with the transaction error passthrough for fiq_fsm.
-
-fiq_fsm: Implement hack for Split Interrupt transactions
-
-Hubs aren't too picky about which endpoint we send Control type split
-transactions to. By treating Interrupt transfers as Control, it is
-possible to use the non-periodic queue in the OTG core as well as the
-non-periodic FIFOs in the hub itself. This massively reduces the
-microframe exclusivity/contention that periodic split transactions
-otherwise have to enforce.
-
-It goes without saying that this is a fairly egregious USB specification
-violation, but it works.
-
-Original idea by Hans Petter Selasky @ FreeBSD.org.
-
-dwc_otg: FIQ support on SMP. Set up FIQ stack and handler on Core 0 only.
-
-dwc_otg: introduce fiq_fsm_spin(un|)lock()
-
-SMP safety for the FIQ relies on register read-modify write cycles being
-completed in the correct order. Several places in the DWC code modify
-registers also touched by the FIQ. Protect these by a bare-bones lock
-mechanism.
-
-This also makes it possible to run the FIQ and IRQ handlers on different
-cores.
-
-fiq_fsm: fix build on bcm2708 and bcm2709 platforms
-
-dwc_otg: put some barriers back where they should be for UP
-
-bcm2709/dwc_otg: Setup FIQ on core 1 if >1 core active
-
-dwc_otg: fixup read-modify-write in critical paths
-
-Be more careful about read-modify-write on registers that the FIQ
-also touches.
-
-Guard fiq_fsm_spin_lock with fiq_enable check
-
-fiq_fsm: Falling out of the state machine isn't fatal
-
-This edge case can be hit if the port is disabled while the FIQ is
-in the middle of a transaction. Make the effects less severe.
-
-Also get rid of the useless return value.
-
-squash: dwc_otg: Allow to build without SMP
-
-usb: core: make overcurrent messages more prominent
-
-Hub overcurrent messages are more serious than "debug". Increase loglevel.
-
-usb: dwc_otg: Don't use dma_to_virt()
-
-Commit 6ce0d20 changes dma_to_virt() which breaks this driver.
-Open code the old dma_to_virt() implementation to work around this.
-
-Limit the use of __bus_to_virt() to cases where transfer_buffer_length
-is set and transfer_buffer is not set. This is done to increase the
-chance that this driver will also work on ARCH_BCM2835.
-
-transfer_buffer should not be NULL if the length is set, but the
-comment in the code indicates that there are situations where this
-might happen. drivers/usb/isp1760/isp1760-hcd.c also has a similar
-comment pointing to a possible: 'usb storage / SCSI bug'.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dwc_otg: Fix crash when fiq_enable=0
-
-dwc_otg: fiq_fsm: Make high-speed isochronous strided transfers work properly
-
-Certain low-bandwidth high-speed USB devices (specialist audio devices,
-compressed-frame webcams) have packet intervals > 1 microframe.
-
-Stride these transfers in the FIQ by using the start-of-frame interrupt
-to restart the channel at the right time.
-
-dwc_otg: Force host mode to fix incorrect compute module boards
-
-dwc_otg: Add ARCH_BCM2835 support
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dwc_otg: Simplify FIQ irq number code
-
-Dropping ATAGS means we can simplify the FIQ irq number code.
-Also add error checking on the returned irq number.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dwc_otg: Remove duplicate gadget probe/unregister function
-
-dwc_otg: Properly set the HFIR
-
-Douglas Anderson reported:
-
-According to the most up to date version of the dwc2 databook, the FRINT
-field of the HFIR register should be programmed to:
-* 125 us * (PHY clock freq for HS) - 1
-* 1000 us * (PHY clock freq for FS/LS) - 1
-
-This is opposed to older versions of the doc that claimed it should be:
-* 125 us * (PHY clock freq for HS)
-* 1000 us * (PHY clock freq for FS/LS)
-
-and reported lower timing jitter on a USB analyser
-
-dcw_otg: trim xfer length when buffer larger than allocated size is received
-
-dwc_otg: Don't free qh align buffers in atomic context
-
-dwc_otg: Enable the hack for Split Interrupt transactions by default
-
-dwc_otg.fiq_fsm_mask=0xF has long been a suggestion for users with audio stutters or other USB bandwidth issues.
-So far we are aware of many success stories but no failure caused by this setting.
-Make it a default to learn more.
-
-See: https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=70437
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
-
-dwc_otg: Use kzalloc when suitable
-
-dwc_otg: Pass struct device to dma_alloc*()
-
-This makes it possible to get the bus address from Device Tree.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dwc_otg: fix summarize urb->actual_length for isochronous transfers
-
-Kernel does not copy input data of ISO transfers to userspace
-if actual_length is set only in ISO transfers and not summarized
-in urb->actual_length. Fixes raspberrypi/linux#903
-
-fiq_fsm: Use correct states when starting isoc OUT transfers
-
-In fiq_fsm_start_next_periodic() if an isochronous OUT transfer
-was selected, no regard was given as to whether this was a single-packet
-transfer or a multi-packet staged transfer.
-
-For single-packet transfers, this had the effect of repeatedly sending
-OUT packets with bogus data and lengths.
-
-Eventually if the channel was repeatedly enabled enough times, this
-would lock up the OTG core and no further bus transfers would happen.
-
-Set the FSM state up properly if we select a single-packet transfer.
-
-Fixes https://github.com/raspberrypi/linux/issues/1842
-
-dwc_otg: make nak_holdoff work as intended with empty queues
-
-If URBs reading from non-periodic split endpoints were dequeued and
-the last transfer from the endpoint was a NAK handshake, the resulting
-qh->nak_frame value was stale which would result in unnecessarily long
-polling intervals for the first subsequent transfer with a fresh URB.
-
-Fixup qh->nak_frame in dwc_otg_hcd_urb_dequeue and also guard against
-a case where a single URB is submitted to the endpoint, a NAK was
-received on the transfer immediately prior to receiving data and the
-device subsequently resubmits another URB past the qh->nak_frame interval.
-
-Fixes https://github.com/raspberrypi/linux/issues/1709
-
-dwc_otg: fix split transaction data toggle handling around dequeues
-
-See https://github.com/raspberrypi/linux/issues/1709
-
-Fix several issues regarding endpoint state when URBs are dequeued
-- If the HCD is disconnected, flush FIQ-enabled channels properly
-- Save the data toggle state for bulk endpoints if the last transfer
-  from an endpoint where URBs were dequeued returned a data packet
-- Reset hc->start_pkt_count properly in assign_and_init_hc()
-
-dwc_otg: fix several potential crash sources
-
-On root port disconnect events, the host driver state is cleared and
-in-progress host channels are forcibly stopped. This doesn't play
-well with the FIQ running in the background, so:
-- Guard the disconnect callback with both the host spinlock and FIQ
-  spinlock
-- Move qtd dereference in dwc_otg_handle_hc_fsm() after the early-out
-  so we don't dereference a qtd that has gone away
-- Turn catch-all BUG()s in dwc_otg_handle_hc_fsm() into warnings.
-
-dwc_otg: delete hcd->channel_lock
-
-The lock serves no purpose as it is only held while the HCD spinlock
-is already being held.
-
-dwc_otg: remove unnecessary dma-mode channel halts on disconnect interrupt
-
-Host channels are already halted in kill_urbs_in_qh_list() with the
-subsequent interrupt processing behaving as if the URB was dequeued
-via HCD callback.
-
-There's no need to clobber the host channel registers a second time
-as this exposes races between the driver and host channel resulting
-in hcd->free_hc_list becoming corrupted.
-
-dwcotg: Allow to build without FIQ on ARM64
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
-
-dwc_otg: make periodic scheduling behave properly for FS buses
-
-If the root port is in full-speed mode, transfer times at 12mbit/s
-would be calculated but matched against high-speed quotas.
-
-Reinitialise hcd->frame_usecs[i] on each port enable event so that
-full-speed bandwidth can be tracked sensibly.
-
-Also, don't bother using the FIQ for transfers when in full-speed
-mode - at the slower bus speed, interrupt frequency is reduced by
-an order of magnitude.
-
-Related issue: https://github.com/raspberrypi/linux/issues/2020
-
-dwc_otg: fiq_fsm: Make isochronous compatibility checks work properly
-
-Get rid of the spammy printk and local pointer mangling.
-Also, there is a nominal benefit for using fiq_fsm for isochronous
-transfers in FS mode (~1.1k IRQs per second vs 2.1k IRQs per second)
-so remove the root port speed check.
-
-dwc_otg: add module parameter int_ep_interval_min
-
-Add a module parameter (defaulting to ignored) that clamps the polling rate
-of high-speed Interrupt endpoints to a minimum microframe interval.
-
-The parameter is modifiable at runtime as it is used when activating new
-endpoints (such as on device connect).
-
-dwc_otg: fiq_fsm: Add non-periodic TT exclusivity constraints
-
-Certain hub types do not discriminate between pipe direction (IN or OUT)
-when considering non-periodic transfers. Therefore these hubs get confused
-if multiple transfers are issued in different directions with the same
-device address and endpoint number.
-
-Constrain queuing non-periodic split transactions so they are performed
-serially in such cases.
-
-Related: https://github.com/raspberrypi/linux/issues/2024
-
-dwc_otg: Fixup change to DRIVER_ATTR interface
-
-dwc_otg: Fix compilation warnings
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-USB_DWCOTG: Disable building dwc_otg as a module (#2265)
-
-When dwc_otg is built as a module, build will fail with the following
-error:
-
-ERROR: "DWC_TASK_HI_SCHEDULE" [drivers/usb/host/dwc_otg/dwc_otg.ko] undefined!
-scripts/Makefile.modpost:91: recipe for target '__modpost' failed
-make[1]: *** [__modpost] Error 1
-Makefile:1199: recipe for target 'modules' failed
-make: *** [modules] Error 2
-
-Even if the error is solved by including the missing
-DWC_TASK_HI_SCHEDULE function, the kernel will panic when loading
-dwc_otg.
-
-As a workaround, simply prevent user from building dwc_otg as a module
-as the current kernel does not support it.
-
-See: https://github.com/raspberrypi/linux/issues/2258
-
-Signed-off-by: Malik Olivier Boussejra <malik@boussejra.com>
----
- arch/arm/include/asm/irqflags.h               |   16 +-
- arch/arm/kernel/fiqasm.S                      |    4 +
- drivers/usb/Makefile                          |    1 +
- drivers/usb/core/generic.c                    |    1 +
- drivers/usb/core/hub.c                        |    2 +-
- drivers/usb/core/message.c                    |   79 +
- drivers/usb/core/otg_whitelist.h              |  114 +-
- drivers/usb/gadget/file_storage.c             | 3676 +++++++++
- drivers/usb/host/Kconfig                      |   10 +
- drivers/usb/host/Makefile                     |    2 +
- drivers/usb/host/dwc_common_port/Makefile     |   58 +
- .../usb/host/dwc_common_port/Makefile.fbsd    |   17 +
- .../usb/host/dwc_common_port/Makefile.linux   |   49 +
- drivers/usb/host/dwc_common_port/changes.txt  |  174 +
- .../usb/host/dwc_common_port/doc/doxygen.cfg  |  270 +
- drivers/usb/host/dwc_common_port/dwc_cc.c     |  532 ++
- drivers/usb/host/dwc_common_port/dwc_cc.h     |  224 +
- .../host/dwc_common_port/dwc_common_fbsd.c    | 1308 +++
- .../host/dwc_common_port/dwc_common_linux.c   | 1418 ++++
- .../host/dwc_common_port/dwc_common_nbsd.c    | 1275 +++
- drivers/usb/host/dwc_common_port/dwc_crypto.c |  308 +
- drivers/usb/host/dwc_common_port/dwc_crypto.h |  111 +
- drivers/usb/host/dwc_common_port/dwc_dh.c     |  291 +
- drivers/usb/host/dwc_common_port/dwc_dh.h     |  106 +
- drivers/usb/host/dwc_common_port/dwc_list.h   |  594 ++
- drivers/usb/host/dwc_common_port/dwc_mem.c    |  245 +
- drivers/usb/host/dwc_common_port/dwc_modpow.c |  636 ++
- drivers/usb/host/dwc_common_port/dwc_modpow.h |   34 +
- .../usb/host/dwc_common_port/dwc_notifier.c   |  319 +
- .../usb/host/dwc_common_port/dwc_notifier.h   |  122 +
- drivers/usb/host/dwc_common_port/dwc_os.h     | 1276 +++
- drivers/usb/host/dwc_common_port/usb.h        |  946 +++
- drivers/usb/host/dwc_otg/Makefile             |   82 +
- drivers/usb/host/dwc_otg/doc/doxygen.cfg      |  224 +
- drivers/usb/host/dwc_otg/dummy_audio.c        | 1574 ++++
- drivers/usb/host/dwc_otg/dwc_cfi_common.h     |  142 +
- drivers/usb/host/dwc_otg/dwc_otg_adp.c        |  854 ++
- drivers/usb/host/dwc_otg/dwc_otg_adp.h        |   80 +
- drivers/usb/host/dwc_otg/dwc_otg_attr.c       | 1212 +++
- drivers/usb/host/dwc_otg/dwc_otg_attr.h       |   89 +
- drivers/usb/host/dwc_otg/dwc_otg_cfi.c        | 1876 +++++
- drivers/usb/host/dwc_otg/dwc_otg_cfi.h        |  320 +
- drivers/usb/host/dwc_otg/dwc_otg_cil.c        | 7141 +++++++++++++++++
- drivers/usb/host/dwc_otg/dwc_otg_cil.h        | 1464 ++++
- drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c   | 1596 ++++
- drivers/usb/host/dwc_otg/dwc_otg_core_if.h    |  705 ++
- drivers/usb/host/dwc_otg/dwc_otg_dbg.h        |  117 +
- drivers/usb/host/dwc_otg/dwc_otg_driver.c     | 1760 ++++
- drivers/usb/host/dwc_otg/dwc_otg_driver.h     |   86 +
- drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c    | 1389 ++++
- drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h    |  372 +
- drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S   |   80 +
- drivers/usb/host/dwc_otg/dwc_otg_hcd.c        | 4283 ++++++++++
- drivers/usb/host/dwc_otg/dwc_otg_hcd.h        |  870 ++
- drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c   | 1134 +++
- drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h     |  417 +
- drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c   | 2752 +++++++
- drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c  | 1007 +++
- drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c  |  971 +++
- drivers/usb/host/dwc_otg/dwc_otg_os_dep.h     |  188 +
- drivers/usb/host/dwc_otg/dwc_otg_pcd.c        | 2725 +++++++
- drivers/usb/host/dwc_otg/dwc_otg_pcd.h        |  273 +
- drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h     |  361 +
- drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c   | 5148 ++++++++++++
- drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c  | 1280 +++
- drivers/usb/host/dwc_otg/dwc_otg_regs.h       | 2550 ++++++
- drivers/usb/host/dwc_otg/test/Makefile        |   16 +
- drivers/usb/host/dwc_otg/test/dwc_otg_test.pm |  337 +
- .../usb/host/dwc_otg/test/test_mod_param.pl   |  133 +
- drivers/usb/host/dwc_otg/test/test_sysfs.pl   |  193 +
- 70 files changed, 60003 insertions(+), 16 deletions(-)
- create mode 100644 drivers/usb/gadget/file_storage.c
- create mode 100644 drivers/usb/host/dwc_common_port/Makefile
- create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd
- create mode 100644 drivers/usb/host/dwc_common_port/Makefile.linux
- create mode 100644 drivers/usb/host/dwc_common_port/changes.txt
- create mode 100644 drivers/usb/host/dwc_common_port/doc/doxygen.cfg
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.h
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_linux.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.h
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.h
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_list.h
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_mem.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.h
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.c
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.h
- create mode 100644 drivers/usb/host/dwc_common_port/dwc_os.h
- create mode 100644 drivers/usb/host/dwc_common_port/usb.h
- create mode 100644 drivers/usb/host/dwc_otg/Makefile
- create mode 100644 drivers/usb/host/dwc_otg/doc/doxygen.cfg
- create mode 100644 drivers/usb/host/dwc_otg/dummy_audio.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_cfi_common.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_core_if.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_dbg.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
- create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_regs.h
- create mode 100644 drivers/usb/host/dwc_otg/test/Makefile
- create mode 100644 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
- create mode 100644 drivers/usb/host/dwc_otg/test/test_mod_param.pl
- create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl
-
---- a/arch/arm/include/asm/irqflags.h
-+++ b/arch/arm/include/asm/irqflags.h
-@@ -163,13 +163,23 @@ static inline unsigned long arch_local_s
- }
- 
- /*
-- * restore saved IRQ & FIQ state
-+ * restore saved IRQ state
-  */
- #define arch_local_irq_restore arch_local_irq_restore
- static inline void arch_local_irq_restore(unsigned long flags)
- {
--	asm volatile(
--		"	msr	" IRQMASK_REG_NAME_W ", %0	@ local_irq_restore"
-+	unsigned long temp = 0;
-+	flags &= ~(1 << 6);
-+	asm volatile (
-+		" mrs %0, cpsr"
-+		: "=r" (temp)
-+		:
-+		: "memory", "cc");
-+		/* Preserve FIQ bit */
-+		temp &= (1 << 6);
-+		flags = flags | temp;
-+	asm volatile (
-+		"    msr    cpsr_c, %0    @ local_irq_restore"
- 		:
- 		: "r" (flags)
- 		: "memory", "cc");
---- a/arch/arm/kernel/fiqasm.S
-+++ b/arch/arm/kernel/fiqasm.S
-@@ -47,3 +47,7 @@ ENTRY(__get_fiq_regs)
- 	mov	r0, r0		@ avoid hazard prior to ARMv4
- 	ret	lr
- ENDPROC(__get_fiq_regs)
-+
-+ENTRY(__FIQ_Branch)
-+	mov pc, r8
-+ENDPROC(__FIQ_Branch)
---- a/drivers/usb/Makefile
-+++ b/drivers/usb/Makefile
-@@ -8,6 +8,7 @@
- obj-$(CONFIG_USB)		+= core/
- obj-$(CONFIG_USB_SUPPORT)	+= phy/
- 
-+obj-$(CONFIG_USB_DWCOTG)	+= host/
- obj-$(CONFIG_USB_DWC3)		+= dwc3/
- obj-$(CONFIG_USB_DWC2)		+= dwc2/
- obj-$(CONFIG_USB_ISP1760)	+= isp1760/
---- a/drivers/usb/core/generic.c
-+++ b/drivers/usb/core/generic.c
-@@ -154,6 +154,7 @@ int usb_choose_configuration(struct usb_
- 		dev_warn(&udev->dev,
- 			"no configuration chosen from %d choice%s\n",
- 			num_configs, plural(num_configs));
-+		dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
- 	}
- 	return i;
- }
---- a/drivers/usb/core/hub.c
-+++ b/drivers/usb/core/hub.c
-@@ -5084,7 +5084,7 @@ static void port_event(struct usb_hub *h
- 	if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
- 		u16 status = 0, unused;
- 
--		dev_dbg(&port_dev->dev, "over-current change\n");
-+		dev_notice(&port_dev->dev, "over-current change\n");
- 		usb_clear_port_feature(hdev, port1,
- 				USB_PORT_FEAT_C_OVER_CURRENT);
- 		msleep(100);	/* Cool down */
---- a/drivers/usb/core/message.c
-+++ b/drivers/usb/core/message.c
-@@ -1924,6 +1924,85 @@ free_interfaces:
- 	if (cp->string == NULL &&
- 			!(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
- 		cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
-+/* Uncomment this define to enable the HS Electrical Test support */
-+#define DWC_HS_ELECT_TST 1
-+#ifdef DWC_HS_ELECT_TST
-+		/* Here we implement the HS Electrical Test support. The
-+		 * tester uses a vendor ID of 0x1A0A to indicate we should
-+		 * run a special test sequence. The product ID tells us
-+		 * which sequence to run. We invoke the test sequence by
-+		 * sending a non-standard SetFeature command to our root
-+		 * hub port. Our dwc_otg_hcd_hub_control() routine will
-+		 * recognize the command and perform the desired test
-+		 * sequence.
-+		 */
-+		if (dev->descriptor.idVendor == 0x1A0A) {
-+			/* HSOTG Electrical Test */
-+			dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
-+
-+			if (dev->bus && dev->bus->root_hub) {
-+				struct usb_device *hdev = dev->bus->root_hub;
-+				dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
-+
-+				switch (dev->descriptor.idProduct) {
-+				case 0x0101:	/* TEST_SE0_NAK */
-+					dev_warn(&dev->dev, "TEST_SE0_NAK\n");
-+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+							USB_REQ_SET_FEATURE, USB_RT_PORT,
-+							USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
-+					break;
-+
-+				case 0x0102:	/* TEST_J */
-+					dev_warn(&dev->dev, "TEST_J\n");
-+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+							USB_REQ_SET_FEATURE, USB_RT_PORT,
-+							USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
-+					break;
-+
-+				case 0x0103:	/* TEST_K */
-+					dev_warn(&dev->dev, "TEST_K\n");
-+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+							USB_REQ_SET_FEATURE, USB_RT_PORT,
-+							USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
-+					break;
-+
-+				case 0x0104:	/* TEST_PACKET */
-+					dev_warn(&dev->dev, "TEST_PACKET\n");
-+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+							USB_REQ_SET_FEATURE, USB_RT_PORT,
-+							USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
-+					break;
-+
-+				case 0x0105:	/* TEST_FORCE_ENABLE */
-+					dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
-+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+							USB_REQ_SET_FEATURE, USB_RT_PORT,
-+							USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
-+					break;
-+
-+				case 0x0106:	/* HS_HOST_PORT_SUSPEND_RESUME */
-+					dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
-+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+							USB_REQ_SET_FEATURE, USB_RT_PORT,
-+							USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
-+					break;
-+
-+				case 0x0107:	/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
-+					dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
-+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+							USB_REQ_SET_FEATURE, USB_RT_PORT,
-+							USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
-+					break;
-+
-+				case 0x0108:	/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
-+					dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
-+					usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
-+							USB_REQ_SET_FEATURE, USB_RT_PORT,
-+							USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
-+				}
-+			}
-+		}
-+#endif /* DWC_HS_ELECT_TST */
- 
- 	/* Now that the interfaces are installed, re-enable LPM. */
- 	usb_unlocked_enable_lpm(dev);
---- a/drivers/usb/core/otg_whitelist.h
-+++ b/drivers/usb/core/otg_whitelist.h
-@@ -19,33 +19,82 @@
- static struct usb_device_id whitelist_table[] = {
- 
- /* hubs are optional in OTG, but very handy ... */
-+#define CERT_WITHOUT_HUBS
-+#if defined(CERT_WITHOUT_HUBS)
-+{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
-+#else
- { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
- { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
-+{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
-+#endif
- 
- #ifdef	CONFIG_USB_PRINTER		/* ignoring nonstatic linkage! */
- /* FIXME actually, printers are NOT supposed to use device classes;
-  * they're supposed to use interface classes...
-  */
--{ USB_DEVICE_INFO(7, 1, 1) },
--{ USB_DEVICE_INFO(7, 1, 2) },
--{ USB_DEVICE_INFO(7, 1, 3) },
-+//{ USB_DEVICE_INFO(7, 1, 1) },
-+//{ USB_DEVICE_INFO(7, 1, 2) },
-+//{ USB_DEVICE_INFO(7, 1, 3) },
- #endif
- 
- #ifdef	CONFIG_USB_NET_CDCETHER
- /* Linux-USB CDC Ethernet gadget */
--{ USB_DEVICE(0x0525, 0xa4a1), },
-+//{ USB_DEVICE(0x0525, 0xa4a1), },
- /* Linux-USB CDC Ethernet + RNDIS gadget */
--{ USB_DEVICE(0x0525, 0xa4a2), },
-+//{ USB_DEVICE(0x0525, 0xa4a2), },
- #endif
- 
- #if	IS_ENABLED(CONFIG_USB_TEST)
- /* gadget zero, for testing */
--{ USB_DEVICE(0x0525, 0xa4a0), },
-+//{ USB_DEVICE(0x0525, 0xa4a0), },
- #endif
- 
-+/* OPT Tester */
-+{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
-+{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
-+{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
-+{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
-+{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
-+{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME  */
-+{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
-+{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
-+
-+/* Sony cameras */
-+{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
-+
-+/* Memory Devices */
-+//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
-+//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
-+//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
-+//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD  */
-+{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
-+//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
-+
-+/* HP Printers */
-+//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
-+//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
-+
-+/* Speakers */
-+//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
-+//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
-+
- { }	/* Terminating entry */
- };
- 
-+static inline void report_errors(struct usb_device *dev)
-+{
-+	/* OTG MESSAGE: report errors here, customize to match your product */
-+	dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
-+		 le16_to_cpu(dev->descriptor.idVendor),
-+		 le16_to_cpu(dev->descriptor.idProduct));
-+        if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
-+                dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
-+        } else {
-+                dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
-+        }
-+}
-+
-+
- static int is_targeted(struct usb_device *dev)
- {
- 	struct usb_device_id	*id = whitelist_table;
-@@ -95,16 +144,57 @@ static int is_targeted(struct usb_device
- 			continue;
- 
- 		return 1;
--	}
-+		/* NOTE: can't use usb_match_id() since interface caches
-+		 * aren't set up yet. this is cut/paste from that code.
-+		 */
-+		for (id = whitelist_table; id->match_flags; id++) {
-+#ifdef DEBUG
-+			dev_dbg(&dev->dev,
-+				"ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
-+				id->idVendor,
-+				id->idProduct,
-+				id->bDeviceClass,
-+				id->bDeviceSubClass,
-+				id->bDeviceProtocol);
-+#endif
- 
--	/* add other match criteria here ... */
-+			if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
-+			    id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
-+				continue;
-+
-+			if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
-+			    id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
-+				continue;
-+
-+			/* No need to test id->bcdDevice_lo != 0, since 0 is never
-+			   greater than any unsigned number. */
-+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
-+			    (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
-+				continue;
-+
-+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
-+			    (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
-+				continue;
-+
-+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
-+			    (id->bDeviceClass != dev->descriptor.bDeviceClass))
-+				continue;
-+
-+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
-+			    (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
-+				continue;
-+
-+			if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
-+			    (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
-+				continue;
- 
-+			return 1;
-+		}
-+	}
- 
--	/* OTG MESSAGE: report errors here, customize to match your product */
--	dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
--		le16_to_cpu(dev->descriptor.idVendor),
--		le16_to_cpu(dev->descriptor.idProduct));
-+	/* add other match criteria here ... */
- 
-+	report_errors(dev);
- 	return 0;
- }
- 
---- /dev/null
-+++ b/drivers/usb/gadget/file_storage.c
-@@ -0,0 +1,3676 @@
-+/*
-+ * file_storage.c -- File-backed USB Storage Gadget, for USB development
-+ *
-+ * Copyright (C) 2003-2008 Alan Stern
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+/*
-+ * The File-backed Storage Gadget acts as a USB Mass Storage device,
-+ * appearing to the host as a disk drive or as a CD-ROM drive.  In addition
-+ * to providing an example of a genuinely useful gadget driver for a USB
-+ * device, it also illustrates a technique of double-buffering for increased
-+ * throughput.  Last but not least, it gives an easy way to probe the
-+ * behavior of the Mass Storage drivers in a USB host.
-+ *
-+ * Backing storage is provided by a regular file or a block device, specified
-+ * by the "file" module parameter.  Access can be limited to read-only by
-+ * setting the optional "ro" module parameter.  (For CD-ROM emulation,
-+ * access is always read-only.)  The gadget will indicate that it has
-+ * removable media if the optional "removable" module parameter is set.
-+ *
-+ * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
-+ * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
-+ * by the optional "transport" module parameter.  It also supports the
-+ * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),
-+ * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by
-+ * the optional "protocol" module parameter.  In addition, the default
-+ * Vendor ID, Product ID, release number and serial number can be overridden.
-+ *
-+ * There is support for multiple logical units (LUNs), each of which has
-+ * its own backing file.  The number of LUNs can be set using the optional
-+ * "luns" module parameter (anywhere from 1 to 8), and the corresponding
-+ * files are specified using comma-separated lists for "file" and "ro".
-+ * The default number of LUNs is taken from the number of "file" elements;
-+ * it is 1 if "file" is not given.  If "removable" is not set then a backing
-+ * file must be specified for each LUN.  If it is set, then an unspecified
-+ * or empty backing filename means the LUN's medium is not loaded.  Ideally
-+ * each LUN would be settable independently as a disk drive or a CD-ROM
-+ * drive, but currently all LUNs have to be the same type.  The CD-ROM
-+ * emulation includes a single data track and no audio tracks; hence there
-+ * need be only one backing file per LUN.
-+ *
-+ * Requirements are modest; only a bulk-in and a bulk-out endpoint are
-+ * needed (an interrupt-out endpoint is also needed for CBI).  The memory
-+ * requirement amounts to two 16K buffers, size configurable by a parameter.
-+ * Support is included for both full-speed and high-speed operation.
-+ *
-+ * Note that the driver is slightly non-portable in that it assumes a
-+ * single memory/DMA buffer will be useable for bulk-in, bulk-out, and
-+ * interrupt-in endpoints.  With most device controllers this isn't an
-+ * issue, but there may be some with hardware restrictions that prevent
-+ * a buffer from being used by more than one endpoint.
-+ *
-+ * Module options:
-+ *
-+ *	file=filename[,filename...]
-+ *				Required if "removable" is not set, names of
-+ *					the files or block devices used for
-+ *					backing storage
-+ *	serial=HHHH...		Required serial number (string of hex chars)
-+ *	ro=b[,b...]		Default false, booleans for read-only access
-+ *	removable		Default false, boolean for removable media
-+ *	luns=N			Default N = number of filenames, number of
-+ *					LUNs to support
-+ *	nofua=b[,b...]		Default false, booleans for ignore FUA flag
-+ *					in SCSI WRITE(10,12) commands
-+ *	stall			Default determined according to the type of
-+ *					USB device controller (usually true),
-+ *					boolean to permit the driver to halt
-+ *					bulk endpoints
-+ *	cdrom			Default false, boolean for whether to emulate
-+ *					a CD-ROM drive
-+ *	transport=XXX		Default BBB, transport name (CB, CBI, or BBB)
-+ *	protocol=YYY		Default SCSI, protocol name (RBC, 8020 or
-+ *					ATAPI, QIC, UFI, 8070, or SCSI;
-+ *					also 1 - 6)
-+ *	vendor=0xVVVV		Default 0x0525 (NetChip), USB Vendor ID
-+ *	product=0xPPPP		Default 0xa4a5 (FSG), USB Product ID
-+ *	release=0xRRRR		Override the USB release number (bcdDevice)
-+ *	buflen=N		Default N=16384, buffer size used (will be
-+ *					rounded down to a multiple of
-+ *					PAGE_CACHE_SIZE)
-+ *
-+ * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro",
-+ * "removable", "luns", "nofua", "stall", and "cdrom" options are available;
-+ * default values are used for everything else.
-+ *
-+ * The pathnames of the backing files and the ro settings are available in
-+ * the attribute files "file", "nofua", and "ro" in the lun<n> subdirectory of
-+ * the gadget's sysfs directory.  If the "removable" option is set, writing to
-+ * these files will simulate ejecting/loading the medium (writing an empty
-+ * line means eject) and adjusting a write-enable tab.  Changes to the ro
-+ * setting are not allowed when the medium is loaded or if CD-ROM emulation
-+ * is being used.
-+ *
-+ * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
-+ * The driver's SCSI command interface was based on the "Information
-+ * technology - Small Computer System Interface - 2" document from
-+ * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at
-+ * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>.  The single exception
-+ * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the
-+ * "Universal Serial Bus Mass Storage Class UFI Command Specification"
-+ * document, Revision 1.0, December 14, 1998, available at
-+ * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.
-+ */
-+
-+
-+/*
-+ *				Driver Design
-+ *
-+ * The FSG driver is fairly straightforward.  There is a main kernel
-+ * thread that handles most of the work.  Interrupt routines field
-+ * callbacks from the controller driver: bulk- and interrupt-request
-+ * completion notifications, endpoint-0 events, and disconnect events.
-+ * Completion events are passed to the main thread by wakeup calls.  Many
-+ * ep0 requests are handled at interrupt time, but SetInterface,
-+ * SetConfiguration, and device reset requests are forwarded to the
-+ * thread in the form of "exceptions" using SIGUSR1 signals (since they
-+ * should interrupt any ongoing file I/O operations).
-+ *
-+ * The thread's main routine implements the standard command/data/status
-+ * parts of a SCSI interaction.  It and its subroutines are full of tests
-+ * for pending signals/exceptions -- all this polling is necessary since
-+ * the kernel has no setjmp/longjmp equivalents.  (Maybe this is an
-+ * indication that the driver really wants to be running in userspace.)
-+ * An important point is that so long as the thread is alive it keeps an
-+ * open reference to the backing file.  This will prevent unmounting
-+ * the backing file's underlying filesystem and could cause problems
-+ * during system shutdown, for example.  To prevent such problems, the
-+ * thread catches INT, TERM, and KILL signals and converts them into
-+ * an EXIT exception.
-+ *
-+ * In normal operation the main thread is started during the gadget's
-+ * fsg_bind() callback and stopped during fsg_unbind().  But it can also
-+ * exit when it receives a signal, and there's no point leaving the
-+ * gadget running when the thread is dead.  So just before the thread
-+ * exits, it deregisters the gadget driver.  This makes things a little
-+ * tricky: The driver is deregistered at two places, and the exiting
-+ * thread can indirectly call fsg_unbind() which in turn can tell the
-+ * thread to exit.  The first problem is resolved through the use of the
-+ * REGISTERED atomic bitflag; the driver will only be deregistered once.
-+ * The second problem is resolved by having fsg_unbind() check
-+ * fsg->state; it won't try to stop the thread if the state is already
-+ * FSG_STATE_TERMINATED.
-+ *
-+ * To provide maximum throughput, the driver uses a circular pipeline of
-+ * buffer heads (struct fsg_buffhd).  In principle the pipeline can be
-+ * arbitrarily long; in practice the benefits don't justify having more
-+ * than 2 stages (i.e., double buffering).  But it helps to think of the
-+ * pipeline as being a long one.  Each buffer head contains a bulk-in and
-+ * a bulk-out request pointer (since the buffer can be used for both
-+ * output and input -- directions always are given from the host's
-+ * point of view) as well as a pointer to the buffer and various state
-+ * variables.
-+ *
-+ * Use of the pipeline follows a simple protocol.  There is a variable
-+ * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.
-+ * At any time that buffer head may still be in use from an earlier
-+ * request, so each buffer head has a state variable indicating whether
-+ * it is EMPTY, FULL, or BUSY.  Typical use involves waiting for the
-+ * buffer head to be EMPTY, filling the buffer either by file I/O or by
-+ * USB I/O (during which the buffer head is BUSY), and marking the buffer
-+ * head FULL when the I/O is complete.  Then the buffer will be emptied
-+ * (again possibly by USB I/O, during which it is marked BUSY) and
-+ * finally marked EMPTY again (possibly by a completion routine).
-+ *
-+ * A module parameter tells the driver to avoid stalling the bulk
-+ * endpoints wherever the transport specification allows.  This is
-+ * necessary for some UDCs like the SuperH, which cannot reliably clear a
-+ * halt on a bulk endpoint.  However, under certain circumstances the
-+ * Bulk-only specification requires a stall.  In such cases the driver
-+ * will halt the endpoint and set a flag indicating that it should clear
-+ * the halt in software during the next device reset.  Hopefully this
-+ * will permit everything to work correctly.  Furthermore, although the
-+ * specification allows the bulk-out endpoint to halt when the host sends
-+ * too much data, implementing this would cause an unavoidable race.
-+ * The driver will always use the "no-stall" approach for OUT transfers.
-+ *
-+ * One subtle point concerns sending status-stage responses for ep0
-+ * requests.  Some of these requests, such as device reset, can involve
-+ * interrupting an ongoing file I/O operation, which might take an
-+ * arbitrarily long time.  During that delay the host might give up on
-+ * the original ep0 request and issue a new one.  When that happens the
-+ * driver should not notify the host about completion of the original
-+ * request, as the host will no longer be waiting for it.  So the driver
-+ * assigns to each ep0 request a unique tag, and it keeps track of the
-+ * tag value of the request associated with a long-running exception
-+ * (device-reset, interface-change, or configuration-change).  When the
-+ * exception handler is finished, the status-stage response is submitted
-+ * only if the current ep0 request tag is equal to the exception request
-+ * tag.  Thus only the most recently received ep0 request will get a
-+ * status-stage response.
-+ *
-+ * Warning: This driver source file is too long.  It ought to be split up
-+ * into a header file plus about 3 separate .c files, to handle the details
-+ * of the Gadget, USB Mass Storage, and SCSI protocols.
-+ */
-+
-+
-+/* #define VERBOSE_DEBUG */
-+/* #define DUMP_MSGS */
-+
-+
-+#include <linux/blkdev.h>
-+#include <linux/completion.h>
-+#include <linux/dcache.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/fcntl.h>
-+#include <linux/file.h>
-+#include <linux/fs.h>
-+#include <linux/kref.h>
-+#include <linux/kthread.h>
-+#include <linux/limits.h>
-+#include <linux/module.h>
-+#include <linux/rwsem.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+#include <linux/string.h>
-+#include <linux/freezer.h>
-+#include <linux/utsname.h>
-+
-+#include <linux/usb/ch9.h>
-+#include <linux/usb/gadget.h>
-+
-+#include "gadget_chips.h"
-+
-+
-+
-+/*
-+ * Kbuild is not very cooperative with respect to linking separately
-+ * compiled library objects into one module.  So for now we won't use
-+ * separate compilation ... ensuring init/exit sections work to shrink
-+ * the runtime footprint, and giving us at least some parts of what
-+ * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
-+ */
-+#include "usbstring.c"
-+#include "config.c"
-+#include "epautoconf.c"
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define DRIVER_DESC		"File-backed Storage Gadget"
-+#define DRIVER_NAME		"g_file_storage"
-+#define DRIVER_VERSION		"1 September 2010"
-+
-+static       char fsg_string_manufacturer[64];
-+static const char fsg_string_product[] = DRIVER_DESC;
-+static const char fsg_string_config[] = "Self-powered";
-+static const char fsg_string_interface[] = "Mass Storage";
-+
-+
-+#include "storage_common.c"
-+
-+
-+MODULE_DESCRIPTION(DRIVER_DESC);
-+MODULE_AUTHOR("Alan Stern");
-+MODULE_LICENSE("Dual BSD/GPL");
-+
-+/*
-+ * This driver assumes self-powered hardware and has no way for users to
-+ * trigger remote wakeup.  It uses autoconfiguration to select endpoints
-+ * and endpoint addresses.
-+ */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/* Encapsulate the module parameter settings */
-+
-+static struct {
-+	char		*file[FSG_MAX_LUNS];
-+	char		*serial;
-+	bool		ro[FSG_MAX_LUNS];
-+	bool		nofua[FSG_MAX_LUNS];
-+	unsigned int	num_filenames;
-+	unsigned int	num_ros;
-+	unsigned int	num_nofuas;
-+	unsigned int	nluns;
-+
-+	bool		removable;
-+	bool		can_stall;
-+	bool		cdrom;
-+
-+	char		*transport_parm;
-+	char		*protocol_parm;
-+	unsigned short	vendor;
-+	unsigned short	product;
-+	unsigned short	release;
-+	unsigned int	buflen;
-+
-+	int		transport_type;
-+	char		*transport_name;
-+	int		protocol_type;
-+	char		*protocol_name;
-+
-+} mod_data = {					// Default values
-+	.transport_parm		= "BBB",
-+	.protocol_parm		= "SCSI",
-+	.removable		= 0,
-+	.can_stall		= 1,
-+	.cdrom			= 0,
-+	.vendor			= FSG_VENDOR_ID,
-+	.product		= FSG_PRODUCT_ID,
-+	.release		= 0xffff,	// Use controller chip type
-+	.buflen			= 16384,
-+	};
-+
-+
-+module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,
-+		S_IRUGO);
-+MODULE_PARM_DESC(file, "names of backing files or devices");
-+
-+module_param_named(serial, mod_data.serial, charp, S_IRUGO);
-+MODULE_PARM_DESC(serial, "USB serial number");
-+
-+module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);
-+MODULE_PARM_DESC(ro, "true to force read-only");
-+
-+module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,
-+		S_IRUGO);
-+MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit");
-+
-+module_param_named(luns, mod_data.nluns, uint, S_IRUGO);
-+MODULE_PARM_DESC(luns, "number of LUNs");
-+
-+module_param_named(removable, mod_data.removable, bool, S_IRUGO);
-+MODULE_PARM_DESC(removable, "true to simulate removable media");
-+
-+module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
-+MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
-+
-+module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
-+MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
-+
-+/* In the non-TEST version, only the module parameters listed above
-+ * are available. */
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+
-+module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);
-+MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)");
-+
-+module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);
-+MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, "
-+		"8070, or SCSI)");
-+
-+module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
-+MODULE_PARM_DESC(vendor, "USB Vendor ID");
-+
-+module_param_named(product, mod_data.product, ushort, S_IRUGO);
-+MODULE_PARM_DESC(product, "USB Product ID");
-+
-+module_param_named(release, mod_data.release, ushort, S_IRUGO);
-+MODULE_PARM_DESC(release, "USB release number");
-+
-+module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);
-+MODULE_PARM_DESC(buflen, "I/O buffer size");
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*
-+ * These definitions will permit the compiler to avoid generating code for
-+ * parts of the driver that aren't used in the non-TEST version.  Even gcc
-+ * can recognize when a test of a constant expression yields a dead code
-+ * path.
-+ */
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+
-+#define transport_is_bbb()	(mod_data.transport_type == USB_PR_BULK)
-+#define transport_is_cbi()	(mod_data.transport_type == USB_PR_CBI)
-+#define protocol_is_scsi()	(mod_data.protocol_type == USB_SC_SCSI)
-+
-+#else
-+
-+#define transport_is_bbb()	1
-+#define transport_is_cbi()	0
-+#define protocol_is_scsi()	1
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+struct fsg_dev {
-+	/* lock protects: state, all the req_busy's, and cbbuf_cmnd */
-+	spinlock_t		lock;
-+	struct usb_gadget	*gadget;
-+
-+	/* filesem protects: backing files in use */
-+	struct rw_semaphore	filesem;
-+
-+	/* reference counting: wait until all LUNs are released */
-+	struct kref		ref;
-+
-+	struct usb_ep		*ep0;		// Handy copy of gadget->ep0
-+	struct usb_request	*ep0req;	// For control responses
-+	unsigned int		ep0_req_tag;
-+	const char		*ep0req_name;
-+
-+	struct usb_request	*intreq;	// For interrupt responses
-+	int			intreq_busy;
-+	struct fsg_buffhd	*intr_buffhd;
-+
-+	unsigned int		bulk_out_maxpacket;
-+	enum fsg_state		state;		// For exception handling
-+	unsigned int		exception_req_tag;
-+
-+	u8			config, new_config;
-+
-+	unsigned int		running : 1;
-+	unsigned int		bulk_in_enabled : 1;
-+	unsigned int		bulk_out_enabled : 1;
-+	unsigned int		intr_in_enabled : 1;
-+	unsigned int		phase_error : 1;
-+	unsigned int		short_packet_received : 1;
-+	unsigned int		bad_lun_okay : 1;
-+
-+	unsigned long		atomic_bitflags;
-+#define REGISTERED		0
-+#define IGNORE_BULK_OUT		1
-+#define SUSPENDED		2
-+
-+	struct usb_ep		*bulk_in;
-+	struct usb_ep		*bulk_out;
-+	struct usb_ep		*intr_in;
-+
-+	struct fsg_buffhd	*next_buffhd_to_fill;
-+	struct fsg_buffhd	*next_buffhd_to_drain;
-+
-+	int			thread_wakeup_needed;
-+	struct completion	thread_notifier;
-+	struct task_struct	*thread_task;
-+
-+	int			cmnd_size;
-+	u8			cmnd[MAX_COMMAND_SIZE];
-+	enum data_direction	data_dir;
-+	u32			data_size;
-+	u32			data_size_from_cmnd;
-+	u32			tag;
-+	unsigned int		lun;
-+	u32			residue;
-+	u32			usb_amount_left;
-+
-+	/* The CB protocol offers no way for a host to know when a command
-+	 * has completed.  As a result the next command may arrive early,
-+	 * and we will still have to handle it.  For that reason we need
-+	 * a buffer to store new commands when using CB (or CBI, which
-+	 * does not oblige a host to wait for command completion either). */
-+	int			cbbuf_cmnd_size;
-+	u8			cbbuf_cmnd[MAX_COMMAND_SIZE];
-+
-+	unsigned int		nluns;
-+	struct fsg_lun		*luns;
-+	struct fsg_lun		*curlun;
-+	/* Must be the last entry */
-+	struct fsg_buffhd	buffhds[];
-+};
-+
-+typedef void (*fsg_routine_t)(struct fsg_dev *);
-+
-+static int exception_in_progress(struct fsg_dev *fsg)
-+{
-+	return (fsg->state > FSG_STATE_IDLE);
-+}
-+
-+/* Make bulk-out requests be divisible by the maxpacket size */
-+static void set_bulk_out_req_length(struct fsg_dev *fsg,
-+		struct fsg_buffhd *bh, unsigned int length)
-+{
-+	unsigned int	rem;
-+
-+	bh->bulk_out_intended_length = length;
-+	rem = length % fsg->bulk_out_maxpacket;
-+	if (rem > 0)
-+		length += fsg->bulk_out_maxpacket - rem;
-+	bh->outreq->length = length;
-+}
-+
-+static struct fsg_dev			*the_fsg;
-+static struct usb_gadget_driver		fsg_driver;
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
-+{
-+	const char	*name;
-+
-+	if (ep == fsg->bulk_in)
-+		name = "bulk-in";
-+	else if (ep == fsg->bulk_out)
-+		name = "bulk-out";
-+	else
-+		name = ep->name;
-+	DBG(fsg, "%s set halt\n", name);
-+	return usb_ep_set_halt(ep);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * DESCRIPTORS ... most are static, but strings and (full) configuration
-+ * descriptors are built on demand.  Also the (static) config and interface
-+ * descriptors are adjusted during fsg_bind().
-+ */
-+
-+/* There is only one configuration. */
-+#define	CONFIG_VALUE		1
-+
-+static struct usb_device_descriptor
-+device_desc = {
-+	.bLength =		sizeof device_desc,
-+	.bDescriptorType =	USB_DT_DEVICE,
-+
-+	.bcdUSB =		cpu_to_le16(0x0200),
-+	.bDeviceClass =		USB_CLASS_PER_INTERFACE,
-+
-+	/* The next three values can be overridden by module parameters */
-+	.idVendor =		cpu_to_le16(FSG_VENDOR_ID),
-+	.idProduct =		cpu_to_le16(FSG_PRODUCT_ID),
-+	.bcdDevice =		cpu_to_le16(0xffff),
-+
-+	.iManufacturer =	FSG_STRING_MANUFACTURER,
-+	.iProduct =		FSG_STRING_PRODUCT,
-+	.iSerialNumber =	FSG_STRING_SERIAL,
-+	.bNumConfigurations =	1,
-+};
-+
-+static struct usb_config_descriptor
-+config_desc = {
-+	.bLength =		sizeof config_desc,
-+	.bDescriptorType =	USB_DT_CONFIG,
-+
-+	/* wTotalLength computed by usb_gadget_config_buf() */
-+	.bNumInterfaces =	1,
-+	.bConfigurationValue =	CONFIG_VALUE,
-+	.iConfiguration =	FSG_STRING_CONFIG,
-+	.bmAttributes =		USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
-+	.bMaxPower =		CONFIG_USB_GADGET_VBUS_DRAW / 2,
-+};
-+
-+
-+static struct usb_qualifier_descriptor
-+dev_qualifier = {
-+	.bLength =		sizeof dev_qualifier,
-+	.bDescriptorType =	USB_DT_DEVICE_QUALIFIER,
-+
-+	.bcdUSB =		cpu_to_le16(0x0200),
-+	.bDeviceClass =		USB_CLASS_PER_INTERFACE,
-+
-+	.bNumConfigurations =	1,
-+};
-+
-+static int populate_bos(struct fsg_dev *fsg, u8 *buf)
-+{
-+	memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);
-+	buf += USB_DT_BOS_SIZE;
-+
-+	memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);
-+	buf += USB_DT_USB_EXT_CAP_SIZE;
-+
-+	memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);
-+
-+	return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE
-+		+ USB_DT_USB_EXT_CAP_SIZE;
-+}
-+
-+/*
-+ * Config descriptors must agree with the code that sets configurations
-+ * and with code managing interfaces and their altsettings.  They must
-+ * also handle different speeds and other-speed requests.
-+ */
-+static int populate_config_buf(struct usb_gadget *gadget,
-+		u8 *buf, u8 type, unsigned index)
-+{
-+	enum usb_device_speed			speed = gadget->speed;
-+	int					len;
-+	const struct usb_descriptor_header	**function;
-+
-+	if (index > 0)
-+		return -EINVAL;
-+
-+	if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)
-+		speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;
-+	function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH
-+		? (const struct usb_descriptor_header **)fsg_hs_function
-+		: (const struct usb_descriptor_header **)fsg_fs_function;
-+
-+	/* for now, don't advertise srp-only devices */
-+	if (!gadget_is_otg(gadget))
-+		function++;
-+
-+	len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);
-+	((struct usb_config_descriptor *) buf)->bDescriptorType = type;
-+	return len;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* These routines may be called in process context or in_irq */
-+
-+/* Caller must hold fsg->lock */
-+static void wakeup_thread(struct fsg_dev *fsg)
-+{
-+	/* Tell the main thread that something has happened */
-+	fsg->thread_wakeup_needed = 1;
-+	if (fsg->thread_task)
-+		wake_up_process(fsg->thread_task);
-+}
-+
-+
-+static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
-+{
-+	unsigned long		flags;
-+
-+	/* Do nothing if a higher-priority exception is already in progress.
-+	 * If a lower-or-equal priority exception is in progress, preempt it
-+	 * and notify the main thread by sending it a signal. */
-+	spin_lock_irqsave(&fsg->lock, flags);
-+	if (fsg->state <= new_state) {
-+		fsg->exception_req_tag = fsg->ep0_req_tag;
-+		fsg->state = new_state;
-+		if (fsg->thread_task)
-+			send_sig_info(SIGUSR1, SEND_SIG_FORCED,
-+					fsg->thread_task);
-+	}
-+	spin_unlock_irqrestore(&fsg->lock, flags);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* The disconnect callback and ep0 routines.  These always run in_irq,
-+ * except that ep0_queue() is called in the main thread to acknowledge
-+ * completion of various requests: set config, set interface, and
-+ * Bulk-only device reset. */
-+
-+static void fsg_disconnect(struct usb_gadget *gadget)
-+{
-+	struct fsg_dev		*fsg = get_gadget_data(gadget);
-+
-+	DBG(fsg, "disconnect or port reset\n");
-+	raise_exception(fsg, FSG_STATE_DISCONNECT);
-+}
-+
-+
-+static int ep0_queue(struct fsg_dev *fsg)
-+{
-+	int	rc;
-+
-+	rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);
-+	if (rc != 0 && rc != -ESHUTDOWN) {
-+
-+		/* We can't do much more than wait for a reset */
-+		WARNING(fsg, "error in submission: %s --> %d\n",
-+				fsg->ep0->name, rc);
-+	}
-+	return rc;
-+}
-+
-+static void ep0_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+	struct fsg_dev		*fsg = ep->driver_data;
-+
-+	if (req->actual > 0)
-+		dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);
-+	if (req->status || req->actual != req->length)
-+		DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+				req->status, req->actual, req->length);
-+	if (req->status == -ECONNRESET)		// Request was cancelled
-+		usb_ep_fifo_flush(ep);
-+
-+	if (req->status == 0 && req->context)
-+		((fsg_routine_t) (req->context))(fsg);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Bulk and interrupt endpoint completion handlers.
-+ * These always run in_irq. */
-+
-+static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+	struct fsg_dev		*fsg = ep->driver_data;
-+	struct fsg_buffhd	*bh = req->context;
-+
-+	if (req->status || req->actual != req->length)
-+		DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+				req->status, req->actual, req->length);
-+	if (req->status == -ECONNRESET)		// Request was cancelled
-+		usb_ep_fifo_flush(ep);
-+
-+	/* Hold the lock while we update the request and buffer states */
-+	smp_wmb();
-+	spin_lock(&fsg->lock);
-+	bh->inreq_busy = 0;
-+	bh->state = BUF_STATE_EMPTY;
-+	wakeup_thread(fsg);
-+	spin_unlock(&fsg->lock);
-+}
-+
-+static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+	struct fsg_dev		*fsg = ep->driver_data;
-+	struct fsg_buffhd	*bh = req->context;
-+
-+	dump_msg(fsg, "bulk-out", req->buf, req->actual);
-+	if (req->status || req->actual != bh->bulk_out_intended_length)
-+		DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+				req->status, req->actual,
-+				bh->bulk_out_intended_length);
-+	if (req->status == -ECONNRESET)		// Request was cancelled
-+		usb_ep_fifo_flush(ep);
-+
-+	/* Hold the lock while we update the request and buffer states */
-+	smp_wmb();
-+	spin_lock(&fsg->lock);
-+	bh->outreq_busy = 0;
-+	bh->state = BUF_STATE_FULL;
-+	wakeup_thread(fsg);
-+	spin_unlock(&fsg->lock);
-+}
-+
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{
-+	struct fsg_dev		*fsg = ep->driver_data;
-+	struct fsg_buffhd	*bh = req->context;
-+
-+	if (req->status || req->actual != req->length)
-+		DBG(fsg, "%s --> %d, %u/%u\n", __func__,
-+				req->status, req->actual, req->length);
-+	if (req->status == -ECONNRESET)		// Request was cancelled
-+		usb_ep_fifo_flush(ep);
-+
-+	/* Hold the lock while we update the request and buffer states */
-+	smp_wmb();
-+	spin_lock(&fsg->lock);
-+	fsg->intreq_busy = 0;
-+	bh->state = BUF_STATE_EMPTY;
-+	wakeup_thread(fsg);
-+	spin_unlock(&fsg->lock);
-+}
-+
-+#else
-+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
-+{}
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Ep0 class-specific handlers.  These always run in_irq. */
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	struct usb_request	*req = fsg->ep0req;
-+	static u8		cbi_reset_cmnd[6] = {
-+			SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};
-+
-+	/* Error in command transfer? */
-+	if (req->status || req->length != req->actual ||
-+			req->actual < 6 || req->actual > MAX_COMMAND_SIZE) {
-+
-+		/* Not all controllers allow a protocol stall after
-+		 * receiving control-out data, but we'll try anyway. */
-+		fsg_set_halt(fsg, fsg->ep0);
-+		return;			// Wait for reset
-+	}
-+
-+	/* Is it the special reset command? */
-+	if (req->actual >= sizeof cbi_reset_cmnd &&
-+			memcmp(req->buf, cbi_reset_cmnd,
-+				sizeof cbi_reset_cmnd) == 0) {
-+
-+		/* Raise an exception to stop the current operation
-+		 * and reinitialize our state. */
-+		DBG(fsg, "cbi reset request\n");
-+		raise_exception(fsg, FSG_STATE_RESET);
-+		return;
-+	}
-+
-+	VDBG(fsg, "CB[I] accept device-specific command\n");
-+	spin_lock(&fsg->lock);
-+
-+	/* Save the command for later */
-+	if (fsg->cbbuf_cmnd_size)
-+		WARNING(fsg, "CB[I] overwriting previous command\n");
-+	fsg->cbbuf_cmnd_size = req->actual;
-+	memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);
-+
-+	wakeup_thread(fsg);
-+	spin_unlock(&fsg->lock);
-+}
-+
-+#else
-+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{}
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+
-+static int class_setup_req(struct fsg_dev *fsg,
-+		const struct usb_ctrlrequest *ctrl)
-+{
-+	struct usb_request	*req = fsg->ep0req;
-+	int			value = -EOPNOTSUPP;
-+	u16			w_index = le16_to_cpu(ctrl->wIndex);
-+	u16                     w_value = le16_to_cpu(ctrl->wValue);
-+	u16			w_length = le16_to_cpu(ctrl->wLength);
-+
-+	if (!fsg->config)
-+		return value;
-+
-+	/* Handle Bulk-only class-specific requests */
-+	if (transport_is_bbb()) {
-+		switch (ctrl->bRequest) {
-+
-+		case US_BULK_RESET_REQUEST:
-+			if (ctrl->bRequestType != (USB_DIR_OUT |
-+					USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+				break;
-+			if (w_index != 0 || w_value != 0 || w_length != 0) {
-+				value = -EDOM;
-+				break;
-+			}
-+
-+			/* Raise an exception to stop the current operation
-+			 * and reinitialize our state. */
-+			DBG(fsg, "bulk reset request\n");
-+			raise_exception(fsg, FSG_STATE_RESET);
-+			value = DELAYED_STATUS;
-+			break;
-+
-+		case US_BULK_GET_MAX_LUN:
-+			if (ctrl->bRequestType != (USB_DIR_IN |
-+					USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+				break;
-+			if (w_index != 0 || w_value != 0 || w_length != 1) {
-+				value = -EDOM;
-+				break;
-+			}
-+			VDBG(fsg, "get max LUN\n");
-+			*(u8 *) req->buf = fsg->nluns - 1;
-+			value = 1;
-+			break;
-+		}
-+	}
-+
-+	/* Handle CBI class-specific requests */
-+	else {
-+		switch (ctrl->bRequest) {
-+
-+		case USB_CBI_ADSC_REQUEST:
-+			if (ctrl->bRequestType != (USB_DIR_OUT |
-+					USB_TYPE_CLASS | USB_RECIP_INTERFACE))
-+				break;
-+			if (w_index != 0 || w_value != 0) {
-+				value = -EDOM;
-+				break;
-+			}
-+			if (w_length > MAX_COMMAND_SIZE) {
-+				value = -EOVERFLOW;
-+				break;
-+			}
-+			value = w_length;
-+			fsg->ep0req->context = received_cbi_adsc;
-+			break;
-+		}
-+	}
-+
-+	if (value == -EOPNOTSUPP)
-+		VDBG(fsg,
-+			"unknown class-specific control req "
-+			"%02x.%02x v%04x i%04x l%u\n",
-+			ctrl->bRequestType, ctrl->bRequest,
-+			le16_to_cpu(ctrl->wValue), w_index, w_length);
-+	return value;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Ep0 standard request handlers.  These always run in_irq. */
-+
-+static int standard_setup_req(struct fsg_dev *fsg,
-+		const struct usb_ctrlrequest *ctrl)
-+{
-+	struct usb_request	*req = fsg->ep0req;
-+	int			value = -EOPNOTSUPP;
-+	u16			w_index = le16_to_cpu(ctrl->wIndex);
-+	u16			w_value = le16_to_cpu(ctrl->wValue);
-+
-+	/* Usually this just stores reply data in the pre-allocated ep0 buffer,
-+	 * but config change events will also reconfigure hardware. */
-+	switch (ctrl->bRequest) {
-+
-+	case USB_REQ_GET_DESCRIPTOR:
-+		if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+				USB_RECIP_DEVICE))
-+			break;
-+		switch (w_value >> 8) {
-+
-+		case USB_DT_DEVICE:
-+			VDBG(fsg, "get device descriptor\n");
-+			device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;
-+			value = sizeof device_desc;
-+			memcpy(req->buf, &device_desc, value);
-+			break;
-+		case USB_DT_DEVICE_QUALIFIER:
-+			VDBG(fsg, "get device qualifier\n");
-+			if (!gadget_is_dualspeed(fsg->gadget) ||
-+					fsg->gadget->speed == USB_SPEED_SUPER)
-+				break;
-+			/*
-+			 * Assume ep0 uses the same maxpacket value for both
-+			 * speeds
-+			 */
-+			dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;
-+			value = sizeof dev_qualifier;
-+			memcpy(req->buf, &dev_qualifier, value);
-+			break;
-+
-+		case USB_DT_OTHER_SPEED_CONFIG:
-+			VDBG(fsg, "get other-speed config descriptor\n");
-+			if (!gadget_is_dualspeed(fsg->gadget) ||
-+					fsg->gadget->speed == USB_SPEED_SUPER)
-+				break;
-+			goto get_config;
-+		case USB_DT_CONFIG:
-+			VDBG(fsg, "get configuration descriptor\n");
-+get_config:
-+			value = populate_config_buf(fsg->gadget,
-+					req->buf,
-+					w_value >> 8,
-+					w_value & 0xff);
-+			break;
-+
-+		case USB_DT_STRING:
-+			VDBG(fsg, "get string descriptor\n");
-+
-+			/* wIndex == language code */
-+			value = usb_gadget_get_string(&fsg_stringtab,
-+					w_value & 0xff, req->buf);
-+			break;
-+
-+		case USB_DT_BOS:
-+			VDBG(fsg, "get bos descriptor\n");
-+
-+			if (gadget_is_superspeed(fsg->gadget))
-+				value = populate_bos(fsg, req->buf);
-+			break;
-+		}
-+
-+		break;
-+
-+	/* One config, two speeds */
-+	case USB_REQ_SET_CONFIGURATION:
-+		if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
-+				USB_RECIP_DEVICE))
-+			break;
-+		VDBG(fsg, "set configuration\n");
-+		if (w_value == CONFIG_VALUE || w_value == 0) {
-+			fsg->new_config = w_value;
-+
-+			/* Raise an exception to wipe out previous transaction
-+			 * state (queued bufs, etc) and set the new config. */
-+			raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
-+			value = DELAYED_STATUS;
-+		}
-+		break;
-+	case USB_REQ_GET_CONFIGURATION:
-+		if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+				USB_RECIP_DEVICE))
-+			break;
-+		VDBG(fsg, "get configuration\n");
-+		*(u8 *) req->buf = fsg->config;
-+		value = 1;
-+		break;
-+
-+	case USB_REQ_SET_INTERFACE:
-+		if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |
-+				USB_RECIP_INTERFACE))
-+			break;
-+		if (fsg->config && w_index == 0) {
-+
-+			/* Raise an exception to wipe out previous transaction
-+			 * state (queued bufs, etc) and install the new
-+			 * interface altsetting. */
-+			raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);
-+			value = DELAYED_STATUS;
-+		}
-+		break;
-+	case USB_REQ_GET_INTERFACE:
-+		if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
-+				USB_RECIP_INTERFACE))
-+			break;
-+		if (!fsg->config)
-+			break;
-+		if (w_index != 0) {
-+			value = -EDOM;
-+			break;
-+		}
-+		VDBG(fsg, "get interface\n");
-+		*(u8 *) req->buf = 0;
-+		value = 1;
-+		break;
-+
-+	default:
-+		VDBG(fsg,
-+			"unknown control req %02x.%02x v%04x i%04x l%u\n",
-+			ctrl->bRequestType, ctrl->bRequest,
-+			w_value, w_index, le16_to_cpu(ctrl->wLength));
-+	}
-+
-+	return value;
-+}
-+
-+
-+static int fsg_setup(struct usb_gadget *gadget,
-+		const struct usb_ctrlrequest *ctrl)
-+{
-+	struct fsg_dev		*fsg = get_gadget_data(gadget);
-+	int			rc;
-+	int			w_length = le16_to_cpu(ctrl->wLength);
-+
-+	++fsg->ep0_req_tag;		// Record arrival of a new request
-+	fsg->ep0req->context = NULL;
-+	fsg->ep0req->length = 0;
-+	dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
-+
-+	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
-+		rc = class_setup_req(fsg, ctrl);
-+	else
-+		rc = standard_setup_req(fsg, ctrl);
-+
-+	/* Respond with data/status or defer until later? */
-+	if (rc >= 0 && rc != DELAYED_STATUS) {
-+		rc = min(rc, w_length);
-+		fsg->ep0req->length = rc;
-+		fsg->ep0req->zero = rc < w_length;
-+		fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?
-+				"ep0-in" : "ep0-out");
-+		rc = ep0_queue(fsg);
-+	}
-+
-+	/* Device either stalls (rc < 0) or reports success */
-+	return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* All the following routines run in process context */
-+
-+
-+/* Use this for bulk or interrupt transfers, not ep0 */
-+static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
-+		struct usb_request *req, int *pbusy,
-+		enum fsg_buffer_state *state)
-+{
-+	int	rc;
-+
-+	if (ep == fsg->bulk_in)
-+		dump_msg(fsg, "bulk-in", req->buf, req->length);
-+	else if (ep == fsg->intr_in)
-+		dump_msg(fsg, "intr-in", req->buf, req->length);
-+
-+	spin_lock_irq(&fsg->lock);
-+	*pbusy = 1;
-+	*state = BUF_STATE_BUSY;
-+	spin_unlock_irq(&fsg->lock);
-+	rc = usb_ep_queue(ep, req, GFP_KERNEL);
-+	if (rc != 0) {
-+		*pbusy = 0;
-+		*state = BUF_STATE_EMPTY;
-+
-+		/* We can't do much more than wait for a reset */
-+
-+		/* Note: currently the net2280 driver fails zero-length
-+		 * submissions if DMA is enabled. */
-+		if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
-+						req->length == 0))
-+			WARNING(fsg, "error in submission: %s --> %d\n",
-+					ep->name, rc);
-+	}
-+}
-+
-+
-+static int sleep_thread(struct fsg_dev *fsg)
-+{
-+	int	rc = 0;
-+
-+	/* Wait until a signal arrives or we are woken up */
-+	for (;;) {
-+		try_to_freeze();
-+		set_current_state(TASK_INTERRUPTIBLE);
-+		if (signal_pending(current)) {
-+			rc = -EINTR;
-+			break;
-+		}
-+		if (fsg->thread_wakeup_needed)
-+			break;
-+		schedule();
-+	}
-+	__set_current_state(TASK_RUNNING);
-+	fsg->thread_wakeup_needed = 0;
-+	return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_read(struct fsg_dev *fsg)
-+{
-+	struct fsg_lun		*curlun = fsg->curlun;
-+	u32			lba;
-+	struct fsg_buffhd	*bh;
-+	int			rc;
-+	u32			amount_left;
-+	loff_t			file_offset, file_offset_tmp;
-+	unsigned int		amount;
-+	ssize_t			nread;
-+
-+	/* Get the starting Logical Block Address and check that it's
-+	 * not too big */
-+	if (fsg->cmnd[0] == READ_6)
-+		lba = get_unaligned_be24(&fsg->cmnd[1]);
-+	else {
-+		lba = get_unaligned_be32(&fsg->cmnd[2]);
-+
-+		/* We allow DPO (Disable Page Out = don't save data in the
-+		 * cache) and FUA (Force Unit Access = don't read from the
-+		 * cache), but we don't implement them. */
-+		if ((fsg->cmnd[1] & ~0x18) != 0) {
-+			curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+			return -EINVAL;
-+		}
-+	}
-+	if (lba >= curlun->num_sectors) {
-+		curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+		return -EINVAL;
-+	}
-+	file_offset = ((loff_t) lba) << curlun->blkbits;
-+
-+	/* Carry out the file reads */
-+	amount_left = fsg->data_size_from_cmnd;
-+	if (unlikely(amount_left == 0))
-+		return -EIO;		// No default reply
-+
-+	for (;;) {
-+
-+		/* Figure out how much we need to read:
-+		 * Try to read the remaining amount.
-+		 * But don't read more than the buffer size.
-+		 * And don't try to read past the end of the file.
-+		 */
-+		amount = min((unsigned int) amount_left, mod_data.buflen);
-+		amount = min((loff_t) amount,
-+				curlun->file_length - file_offset);
-+
-+		/* Wait for the next buffer to become available */
-+		bh = fsg->next_buffhd_to_fill;
-+		while (bh->state != BUF_STATE_EMPTY) {
-+			rc = sleep_thread(fsg);
-+			if (rc)
-+				return rc;
-+		}
-+
-+		/* If we were asked to read past the end of file,
-+		 * end with an empty buffer. */
-+		if (amount == 0) {
-+			curlun->sense_data =
-+					SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+			curlun->sense_data_info = file_offset >> curlun->blkbits;
-+			curlun->info_valid = 1;
-+			bh->inreq->length = 0;
-+			bh->state = BUF_STATE_FULL;
-+			break;
-+		}
-+
-+		/* Perform the read */
-+		file_offset_tmp = file_offset;
-+		nread = vfs_read(curlun->filp,
-+				(char __user *) bh->buf,
-+				amount, &file_offset_tmp);
-+		VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
-+				(unsigned long long) file_offset,
-+				(int) nread);
-+		if (signal_pending(current))
-+			return -EINTR;
-+
-+		if (nread < 0) {
-+			LDBG(curlun, "error in file read: %d\n",
-+					(int) nread);
-+			nread = 0;
-+		} else if (nread < amount) {
-+			LDBG(curlun, "partial file read: %d/%u\n",
-+					(int) nread, amount);
-+			nread = round_down(nread, curlun->blksize);
-+		}
-+		file_offset  += nread;
-+		amount_left  -= nread;
-+		fsg->residue -= nread;
-+
-+		/* Except at the end of the transfer, nread will be
-+		 * equal to the buffer size, which is divisible by the
-+		 * bulk-in maxpacket size.
-+		 */
-+		bh->inreq->length = nread;
-+		bh->state = BUF_STATE_FULL;
-+
-+		/* If an error occurred, report it and its position */
-+		if (nread < amount) {
-+			curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
-+			curlun->sense_data_info = file_offset >> curlun->blkbits;
-+			curlun->info_valid = 1;
-+			break;
-+		}
-+
-+		if (amount_left == 0)
-+			break;		// No more left to read
-+
-+		/* Send this buffer and go read some more */
-+		bh->inreq->zero = 0;
-+		start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+				&bh->inreq_busy, &bh->state);
-+		fsg->next_buffhd_to_fill = bh->next;
-+	}
-+
-+	return -EIO;		// No default reply
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_write(struct fsg_dev *fsg)
-+{
-+	struct fsg_lun		*curlun = fsg->curlun;
-+	u32			lba;
-+	struct fsg_buffhd	*bh;
-+	int			get_some_more;
-+	u32			amount_left_to_req, amount_left_to_write;
-+	loff_t			usb_offset, file_offset, file_offset_tmp;
-+	unsigned int		amount;
-+	ssize_t			nwritten;
-+	int			rc;
-+
-+	if (curlun->ro) {
-+		curlun->sense_data = SS_WRITE_PROTECTED;
-+		return -EINVAL;
-+	}
-+	spin_lock(&curlun->filp->f_lock);
-+	curlun->filp->f_flags &= ~O_SYNC;	// Default is not to wait
-+	spin_unlock(&curlun->filp->f_lock);
-+
-+	/* Get the starting Logical Block Address and check that it's
-+	 * not too big */
-+	if (fsg->cmnd[0] == WRITE_6)
-+		lba = get_unaligned_be24(&fsg->cmnd[1]);
-+	else {
-+		lba = get_unaligned_be32(&fsg->cmnd[2]);
-+
-+		/* We allow DPO (Disable Page Out = don't save data in the
-+		 * cache) and FUA (Force Unit Access = write directly to the
-+		 * medium).  We don't implement DPO; we implement FUA by
-+		 * performing synchronous output. */
-+		if ((fsg->cmnd[1] & ~0x18) != 0) {
-+			curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+			return -EINVAL;
-+		}
-+		/* FUA */
-+		if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {
-+			spin_lock(&curlun->filp->f_lock);
-+			curlun->filp->f_flags |= O_DSYNC;
-+			spin_unlock(&curlun->filp->f_lock);
-+		}
-+	}
-+	if (lba >= curlun->num_sectors) {
-+		curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+		return -EINVAL;
-+	}
-+
-+	/* Carry out the file writes */
-+	get_some_more = 1;
-+	file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;
-+	amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
-+
-+	while (amount_left_to_write > 0) {
-+
-+		/* Queue a request for more data from the host */
-+		bh = fsg->next_buffhd_to_fill;
-+		if (bh->state == BUF_STATE_EMPTY && get_some_more) {
-+
-+			/* Figure out how much we want to get:
-+			 * Try to get the remaining amount,
-+			 * but not more than the buffer size.
-+			 */
-+			amount = min(amount_left_to_req, mod_data.buflen);
-+
-+			/* Beyond the end of the backing file? */
-+			if (usb_offset >= curlun->file_length) {
-+				get_some_more = 0;
-+				curlun->sense_data =
-+					SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+				curlun->sense_data_info = usb_offset >> curlun->blkbits;
-+				curlun->info_valid = 1;
-+				continue;
-+			}
-+
-+			/* Get the next buffer */
-+			usb_offset += amount;
-+			fsg->usb_amount_left -= amount;
-+			amount_left_to_req -= amount;
-+			if (amount_left_to_req == 0)
-+				get_some_more = 0;
-+
-+			/* Except at the end of the transfer, amount will be
-+			 * equal to the buffer size, which is divisible by
-+			 * the bulk-out maxpacket size.
-+			 */
-+			set_bulk_out_req_length(fsg, bh, amount);
-+			start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+					&bh->outreq_busy, &bh->state);
-+			fsg->next_buffhd_to_fill = bh->next;
-+			continue;
-+		}
-+
-+		/* Write the received data to the backing file */
-+		bh = fsg->next_buffhd_to_drain;
-+		if (bh->state == BUF_STATE_EMPTY && !get_some_more)
-+			break;			// We stopped early
-+		if (bh->state == BUF_STATE_FULL) {
-+			smp_rmb();
-+			fsg->next_buffhd_to_drain = bh->next;
-+			bh->state = BUF_STATE_EMPTY;
-+
-+			/* Did something go wrong with the transfer? */
-+			if (bh->outreq->status != 0) {
-+				curlun->sense_data = SS_COMMUNICATION_FAILURE;
-+				curlun->sense_data_info = file_offset >> curlun->blkbits;
-+				curlun->info_valid = 1;
-+				break;
-+			}
-+
-+			amount = bh->outreq->actual;
-+			if (curlun->file_length - file_offset < amount) {
-+				LERROR(curlun,
-+	"write %u @ %llu beyond end %llu\n",
-+	amount, (unsigned long long) file_offset,
-+	(unsigned long long) curlun->file_length);
-+				amount = curlun->file_length - file_offset;
-+			}
-+
-+			/* Don't accept excess data.  The spec doesn't say
-+			 * what to do in this case.  We'll ignore the error.
-+			 */
-+			amount = min(amount, bh->bulk_out_intended_length);
-+
-+			/* Don't write a partial block */
-+			amount = round_down(amount, curlun->blksize);
-+			if (amount == 0)
-+				goto empty_write;
-+
-+			/* Perform the write */
-+			file_offset_tmp = file_offset;
-+			nwritten = vfs_write(curlun->filp,
-+					(char __user *) bh->buf,
-+					amount, &file_offset_tmp);
-+			VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
-+					(unsigned long long) file_offset,
-+					(int) nwritten);
-+			if (signal_pending(current))
-+				return -EINTR;		// Interrupted!
-+
-+			if (nwritten < 0) {
-+				LDBG(curlun, "error in file write: %d\n",
-+						(int) nwritten);
-+				nwritten = 0;
-+			} else if (nwritten < amount) {
-+				LDBG(curlun, "partial file write: %d/%u\n",
-+						(int) nwritten, amount);
-+				nwritten = round_down(nwritten, curlun->blksize);
-+			}
-+			file_offset += nwritten;
-+			amount_left_to_write -= nwritten;
-+			fsg->residue -= nwritten;
-+
-+			/* If an error occurred, report it and its position */
-+			if (nwritten < amount) {
-+				curlun->sense_data = SS_WRITE_ERROR;
-+				curlun->sense_data_info = file_offset >> curlun->blkbits;
-+				curlun->info_valid = 1;
-+				break;
-+			}
-+
-+ empty_write:
-+			/* Did the host decide to stop early? */
-+			if (bh->outreq->actual < bh->bulk_out_intended_length) {
-+				fsg->short_packet_received = 1;
-+				break;
-+			}
-+			continue;
-+		}
-+
-+		/* Wait for something to happen */
-+		rc = sleep_thread(fsg);
-+		if (rc)
-+			return rc;
-+	}
-+
-+	return -EIO;		// No default reply
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_synchronize_cache(struct fsg_dev *fsg)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	int		rc;
-+
-+	/* We ignore the requested LBA and write out all file's
-+	 * dirty data buffers. */
-+	rc = fsg_lun_fsync_sub(curlun);
-+	if (rc)
-+		curlun->sense_data = SS_WRITE_ERROR;
-+	return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void invalidate_sub(struct fsg_lun *curlun)
-+{
-+	struct file	*filp = curlun->filp;
-+	struct inode	*inode = filp->f_path.dentry->d_inode;
-+	unsigned long	rc;
-+
-+	rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
-+	VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc);
-+}
-+
-+static int do_verify(struct fsg_dev *fsg)
-+{
-+	struct fsg_lun		*curlun = fsg->curlun;
-+	u32			lba;
-+	u32			verification_length;
-+	struct fsg_buffhd	*bh = fsg->next_buffhd_to_fill;
-+	loff_t			file_offset, file_offset_tmp;
-+	u32			amount_left;
-+	unsigned int		amount;
-+	ssize_t			nread;
-+
-+	/* Get the starting Logical Block Address and check that it's
-+	 * not too big */
-+	lba = get_unaligned_be32(&fsg->cmnd[2]);
-+	if (lba >= curlun->num_sectors) {
-+		curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+		return -EINVAL;
-+	}
-+
-+	/* We allow DPO (Disable Page Out = don't save data in the
-+	 * cache) but we don't implement it. */
-+	if ((fsg->cmnd[1] & ~0x10) != 0) {
-+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+		return -EINVAL;
-+	}
-+
-+	verification_length = get_unaligned_be16(&fsg->cmnd[7]);
-+	if (unlikely(verification_length == 0))
-+		return -EIO;		// No default reply
-+
-+	/* Prepare to carry out the file verify */
-+	amount_left = verification_length << curlun->blkbits;
-+	file_offset = ((loff_t) lba) << curlun->blkbits;
-+
-+	/* Write out all the dirty buffers before invalidating them */
-+	fsg_lun_fsync_sub(curlun);
-+	if (signal_pending(current))
-+		return -EINTR;
-+
-+	invalidate_sub(curlun);
-+	if (signal_pending(current))
-+		return -EINTR;
-+
-+	/* Just try to read the requested blocks */
-+	while (amount_left > 0) {
-+
-+		/* Figure out how much we need to read:
-+		 * Try to read the remaining amount, but not more than
-+		 * the buffer size.
-+		 * And don't try to read past the end of the file.
-+		 */
-+		amount = min((unsigned int) amount_left, mod_data.buflen);
-+		amount = min((loff_t) amount,
-+				curlun->file_length - file_offset);
-+		if (amount == 0) {
-+			curlun->sense_data =
-+					SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+			curlun->sense_data_info = file_offset >> curlun->blkbits;
-+			curlun->info_valid = 1;
-+			break;
-+		}
-+
-+		/* Perform the read */
-+		file_offset_tmp = file_offset;
-+		nread = vfs_read(curlun->filp,
-+				(char __user *) bh->buf,
-+				amount, &file_offset_tmp);
-+		VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
-+				(unsigned long long) file_offset,
-+				(int) nread);
-+		if (signal_pending(current))
-+			return -EINTR;
-+
-+		if (nread < 0) {
-+			LDBG(curlun, "error in file verify: %d\n",
-+					(int) nread);
-+			nread = 0;
-+		} else if (nread < amount) {
-+			LDBG(curlun, "partial file verify: %d/%u\n",
-+					(int) nread, amount);
-+			nread = round_down(nread, curlun->blksize);
-+		}
-+		if (nread == 0) {
-+			curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
-+			curlun->sense_data_info = file_offset >> curlun->blkbits;
-+			curlun->info_valid = 1;
-+			break;
-+		}
-+		file_offset += nread;
-+		amount_left -= nread;
-+	}
-+	return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	u8	*buf = (u8 *) bh->buf;
-+
-+	static char vendor_id[] = "Linux   ";
-+	static char product_disk_id[] = "File-Stor Gadget";
-+	static char product_cdrom_id[] = "File-CD Gadget  ";
-+
-+	if (!fsg->curlun) {		// Unsupported LUNs are okay
-+		fsg->bad_lun_okay = 1;
-+		memset(buf, 0, 36);
-+		buf[0] = 0x7f;		// Unsupported, no device-type
-+		buf[4] = 31;		// Additional length
-+		return 36;
-+	}
-+
-+	memset(buf, 0, 8);
-+	buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);
-+	if (mod_data.removable)
-+		buf[1] = 0x80;
-+	buf[2] = 2;		// ANSI SCSI level 2
-+	buf[3] = 2;		// SCSI-2 INQUIRY data format
-+	buf[4] = 31;		// Additional length
-+				// No special options
-+	sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
-+			(mod_data.cdrom ? product_cdrom_id :
-+				product_disk_id),
-+			mod_data.release);
-+	return 36;
-+}
-+
-+
-+static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	u8		*buf = (u8 *) bh->buf;
-+	u32		sd, sdinfo;
-+	int		valid;
-+
-+	/*
-+	 * From the SCSI-2 spec., section 7.9 (Unit attention condition):
-+	 *
-+	 * If a REQUEST SENSE command is received from an initiator
-+	 * with a pending unit attention condition (before the target
-+	 * generates the contingent allegiance condition), then the
-+	 * target shall either:
-+	 *   a) report any pending sense data and preserve the unit
-+	 *	attention condition on the logical unit, or,
-+	 *   b) report the unit attention condition, may discard any
-+	 *	pending sense data, and clear the unit attention
-+	 *	condition on the logical unit for that initiator.
-+	 *
-+	 * FSG normally uses option a); enable this code to use option b).
-+	 */
-+#if 0
-+	if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
-+		curlun->sense_data = curlun->unit_attention_data;
-+		curlun->unit_attention_data = SS_NO_SENSE;
-+	}
-+#endif
-+
-+	if (!curlun) {		// Unsupported LUNs are okay
-+		fsg->bad_lun_okay = 1;
-+		sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
-+		sdinfo = 0;
-+		valid = 0;
-+	} else {
-+		sd = curlun->sense_data;
-+		sdinfo = curlun->sense_data_info;
-+		valid = curlun->info_valid << 7;
-+		curlun->sense_data = SS_NO_SENSE;
-+		curlun->sense_data_info = 0;
-+		curlun->info_valid = 0;
-+	}
-+
-+	memset(buf, 0, 18);
-+	buf[0] = valid | 0x70;			// Valid, current error
-+	buf[2] = SK(sd);
-+	put_unaligned_be32(sdinfo, &buf[3]);	/* Sense information */
-+	buf[7] = 18 - 8;			// Additional sense length
-+	buf[12] = ASC(sd);
-+	buf[13] = ASCQ(sd);
-+	return 18;
-+}
-+
-+
-+static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	u32		lba = get_unaligned_be32(&fsg->cmnd[2]);
-+	int		pmi = fsg->cmnd[8];
-+	u8		*buf = (u8 *) bh->buf;
-+
-+	/* Check the PMI and LBA fields */
-+	if (pmi > 1 || (pmi == 0 && lba != 0)) {
-+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+		return -EINVAL;
-+	}
-+
-+	put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
-+						/* Max logical block */
-+	put_unaligned_be32(curlun->blksize, &buf[4]);	/* Block length */
-+	return 8;
-+}
-+
-+
-+static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	int		msf = fsg->cmnd[1] & 0x02;
-+	u32		lba = get_unaligned_be32(&fsg->cmnd[2]);
-+	u8		*buf = (u8 *) bh->buf;
-+
-+	if ((fsg->cmnd[1] & ~0x02) != 0) {		/* Mask away MSF */
-+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+		return -EINVAL;
-+	}
-+	if (lba >= curlun->num_sectors) {
-+		curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
-+		return -EINVAL;
-+	}
-+
-+	memset(buf, 0, 8);
-+	buf[0] = 0x01;		/* 2048 bytes of user data, rest is EC */
-+	store_cdrom_address(&buf[4], msf, lba);
-+	return 8;
-+}
-+
-+
-+static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	int		msf = fsg->cmnd[1] & 0x02;
-+	int		start_track = fsg->cmnd[6];
-+	u8		*buf = (u8 *) bh->buf;
-+
-+	if ((fsg->cmnd[1] & ~0x02) != 0 ||		/* Mask away MSF */
-+			start_track > 1) {
-+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+		return -EINVAL;
-+	}
-+
-+	memset(buf, 0, 20);
-+	buf[1] = (20-2);		/* TOC data length */
-+	buf[2] = 1;			/* First track number */
-+	buf[3] = 1;			/* Last track number */
-+	buf[5] = 0x16;			/* Data track, copying allowed */
-+	buf[6] = 0x01;			/* Only track is number 1 */
-+	store_cdrom_address(&buf[8], msf, 0);
-+
-+	buf[13] = 0x16;			/* Lead-out track is data */
-+	buf[14] = 0xAA;			/* Lead-out track number */
-+	store_cdrom_address(&buf[16], msf, curlun->num_sectors);
-+	return 20;
-+}
-+
-+
-+static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	int		mscmnd = fsg->cmnd[0];
-+	u8		*buf = (u8 *) bh->buf;
-+	u8		*buf0 = buf;
-+	int		pc, page_code;
-+	int		changeable_values, all_pages;
-+	int		valid_page = 0;
-+	int		len, limit;
-+
-+	if ((fsg->cmnd[1] & ~0x08) != 0) {		// Mask away DBD
-+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+		return -EINVAL;
-+	}
-+	pc = fsg->cmnd[2] >> 6;
-+	page_code = fsg->cmnd[2] & 0x3f;
-+	if (pc == 3) {
-+		curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
-+		return -EINVAL;
-+	}
-+	changeable_values = (pc == 1);
-+	all_pages = (page_code == 0x3f);
-+
-+	/* Write the mode parameter header.  Fixed values are: default
-+	 * medium type, no cache control (DPOFUA), and no block descriptors.
-+	 * The only variable value is the WriteProtect bit.  We will fill in
-+	 * the mode data length later. */
-+	memset(buf, 0, 8);
-+	if (mscmnd == MODE_SENSE) {
-+		buf[2] = (curlun->ro ? 0x80 : 0x00);		// WP, DPOFUA
-+		buf += 4;
-+		limit = 255;
-+	} else {			// MODE_SENSE_10
-+		buf[3] = (curlun->ro ? 0x80 : 0x00);		// WP, DPOFUA
-+		buf += 8;
-+		limit = 65535;		// Should really be mod_data.buflen
-+	}
-+
-+	/* No block descriptors */
-+
-+	/* The mode pages, in numerical order.  The only page we support
-+	 * is the Caching page. */
-+	if (page_code == 0x08 || all_pages) {
-+		valid_page = 1;
-+		buf[0] = 0x08;		// Page code
-+		buf[1] = 10;		// Page length
-+		memset(buf+2, 0, 10);	// None of the fields are changeable
-+
-+		if (!changeable_values) {
-+			buf[2] = 0x04;	// Write cache enable,
-+					// Read cache not disabled
-+					// No cache retention priorities
-+			put_unaligned_be16(0xffff, &buf[4]);
-+					/* Don't disable prefetch */
-+					/* Minimum prefetch = 0 */
-+			put_unaligned_be16(0xffff, &buf[8]);
-+					/* Maximum prefetch */
-+			put_unaligned_be16(0xffff, &buf[10]);
-+					/* Maximum prefetch ceiling */
-+		}
-+		buf += 12;
-+	}
-+
-+	/* Check that a valid page was requested and the mode data length
-+	 * isn't too long. */
-+	len = buf - buf0;
-+	if (!valid_page || len > limit) {
-+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+		return -EINVAL;
-+	}
-+
-+	/*  Store the mode data length */
-+	if (mscmnd == MODE_SENSE)
-+		buf0[0] = len - 1;
-+	else
-+		put_unaligned_be16(len - 2, buf0);
-+	return len;
-+}
-+
-+
-+static int do_start_stop(struct fsg_dev *fsg)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	int		loej, start;
-+
-+	if (!mod_data.removable) {
-+		curlun->sense_data = SS_INVALID_COMMAND;
-+		return -EINVAL;
-+	}
-+
-+	// int immed = fsg->cmnd[1] & 0x01;
-+	loej = fsg->cmnd[4] & 0x02;
-+	start = fsg->cmnd[4] & 0x01;
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+	if ((fsg->cmnd[1] & ~0x01) != 0 ||		// Mask away Immed
-+			(fsg->cmnd[4] & ~0x03) != 0) {	// Mask LoEj, Start
-+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+		return -EINVAL;
-+	}
-+
-+	if (!start) {
-+
-+		/* Are we allowed to unload the media? */
-+		if (curlun->prevent_medium_removal) {
-+			LDBG(curlun, "unload attempt prevented\n");
-+			curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;
-+			return -EINVAL;
-+		}
-+		if (loej) {		// Simulate an unload/eject
-+			up_read(&fsg->filesem);
-+			down_write(&fsg->filesem);
-+			fsg_lun_close(curlun);
-+			up_write(&fsg->filesem);
-+			down_read(&fsg->filesem);
-+		}
-+	} else {
-+
-+		/* Our emulation doesn't support mounting; the medium is
-+		 * available for use as soon as it is loaded. */
-+		if (!fsg_lun_is_open(curlun)) {
-+			curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
-+			return -EINVAL;
-+		}
-+	}
-+#endif
-+	return 0;
-+}
-+
-+
-+static int do_prevent_allow(struct fsg_dev *fsg)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	int		prevent;
-+
-+	if (!mod_data.removable) {
-+		curlun->sense_data = SS_INVALID_COMMAND;
-+		return -EINVAL;
-+	}
-+
-+	prevent = fsg->cmnd[4] & 0x01;
-+	if ((fsg->cmnd[4] & ~0x01) != 0) {		// Mask away Prevent
-+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+		return -EINVAL;
-+	}
-+
-+	if (curlun->prevent_medium_removal && !prevent)
-+		fsg_lun_fsync_sub(curlun);
-+	curlun->prevent_medium_removal = prevent;
-+	return 0;
-+}
-+
-+
-+static int do_read_format_capacities(struct fsg_dev *fsg,
-+			struct fsg_buffhd *bh)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+	u8		*buf = (u8 *) bh->buf;
-+
-+	buf[0] = buf[1] = buf[2] = 0;
-+	buf[3] = 8;		// Only the Current/Maximum Capacity Descriptor
-+	buf += 4;
-+
-+	put_unaligned_be32(curlun->num_sectors, &buf[0]);
-+						/* Number of blocks */
-+	put_unaligned_be32(curlun->blksize, &buf[4]);	/* Block length */
-+	buf[4] = 0x02;				/* Current capacity */
-+	return 12;
-+}
-+
-+
-+static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	struct fsg_lun	*curlun = fsg->curlun;
-+
-+	/* We don't support MODE SELECT */
-+	curlun->sense_data = SS_INVALID_COMMAND;
-+	return -EINVAL;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int halt_bulk_in_endpoint(struct fsg_dev *fsg)
-+{
-+	int	rc;
-+
-+	rc = fsg_set_halt(fsg, fsg->bulk_in);
-+	if (rc == -EAGAIN)
-+		VDBG(fsg, "delayed bulk-in endpoint halt\n");
-+	while (rc != 0) {
-+		if (rc != -EAGAIN) {
-+			WARNING(fsg, "usb_ep_set_halt -> %d\n", rc);
-+			rc = 0;
-+			break;
-+		}
-+
-+		/* Wait for a short time and then try again */
-+		if (msleep_interruptible(100) != 0)
-+			return -EINTR;
-+		rc = usb_ep_set_halt(fsg->bulk_in);
-+	}
-+	return rc;
-+}
-+
-+static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
-+{
-+	int	rc;
-+
-+	DBG(fsg, "bulk-in set wedge\n");
-+	rc = usb_ep_set_wedge(fsg->bulk_in);
-+	if (rc == -EAGAIN)
-+		VDBG(fsg, "delayed bulk-in endpoint wedge\n");
-+	while (rc != 0) {
-+		if (rc != -EAGAIN) {
-+			WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc);
-+			rc = 0;
-+			break;
-+		}
-+
-+		/* Wait for a short time and then try again */
-+		if (msleep_interruptible(100) != 0)
-+			return -EINTR;
-+		rc = usb_ep_set_wedge(fsg->bulk_in);
-+	}
-+	return rc;
-+}
-+
-+static int throw_away_data(struct fsg_dev *fsg)
-+{
-+	struct fsg_buffhd	*bh;
-+	u32			amount;
-+	int			rc;
-+
-+	while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
-+			fsg->usb_amount_left > 0) {
-+
-+		/* Throw away the data in a filled buffer */
-+		if (bh->state == BUF_STATE_FULL) {
-+			smp_rmb();
-+			bh->state = BUF_STATE_EMPTY;
-+			fsg->next_buffhd_to_drain = bh->next;
-+
-+			/* A short packet or an error ends everything */
-+			if (bh->outreq->actual < bh->bulk_out_intended_length ||
-+					bh->outreq->status != 0) {
-+				raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+				return -EINTR;
-+			}
-+			continue;
-+		}
-+
-+		/* Try to submit another request if we need one */
-+		bh = fsg->next_buffhd_to_fill;
-+		if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
-+			amount = min(fsg->usb_amount_left,
-+					(u32) mod_data.buflen);
-+
-+			/* Except at the end of the transfer, amount will be
-+			 * equal to the buffer size, which is divisible by
-+			 * the bulk-out maxpacket size.
-+			 */
-+			set_bulk_out_req_length(fsg, bh, amount);
-+			start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+					&bh->outreq_busy, &bh->state);
-+			fsg->next_buffhd_to_fill = bh->next;
-+			fsg->usb_amount_left -= amount;
-+			continue;
-+		}
-+
-+		/* Otherwise wait for something to happen */
-+		rc = sleep_thread(fsg);
-+		if (rc)
-+			return rc;
-+	}
-+	return 0;
-+}
-+
-+
-+static int finish_reply(struct fsg_dev *fsg)
-+{
-+	struct fsg_buffhd	*bh = fsg->next_buffhd_to_fill;
-+	int			rc = 0;
-+
-+	switch (fsg->data_dir) {
-+	case DATA_DIR_NONE:
-+		break;			// Nothing to send
-+
-+	/* If we don't know whether the host wants to read or write,
-+	 * this must be CB or CBI with an unknown command.  We mustn't
-+	 * try to send or receive any data.  So stall both bulk pipes
-+	 * if we can and wait for a reset. */
-+	case DATA_DIR_UNKNOWN:
-+		if (mod_data.can_stall) {
-+			fsg_set_halt(fsg, fsg->bulk_out);
-+			rc = halt_bulk_in_endpoint(fsg);
-+		}
-+		break;
-+
-+	/* All but the last buffer of data must have already been sent */
-+	case DATA_DIR_TO_HOST:
-+		if (fsg->data_size == 0)
-+			;		// Nothing to send
-+
-+		/* If there's no residue, simply send the last buffer */
-+		else if (fsg->residue == 0) {
-+			bh->inreq->zero = 0;
-+			start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+					&bh->inreq_busy, &bh->state);
-+			fsg->next_buffhd_to_fill = bh->next;
-+		}
-+
-+		/* There is a residue.  For CB and CBI, simply mark the end
-+		 * of the data with a short packet.  However, if we are
-+		 * allowed to stall, there was no data at all (residue ==
-+		 * data_size), and the command failed (invalid LUN or
-+		 * sense data is set), then halt the bulk-in endpoint
-+		 * instead. */
-+		else if (!transport_is_bbb()) {
-+			if (mod_data.can_stall &&
-+					fsg->residue == fsg->data_size &&
-+	(!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {
-+				bh->state = BUF_STATE_EMPTY;
-+				rc = halt_bulk_in_endpoint(fsg);
-+			} else {
-+				bh->inreq->zero = 1;
-+				start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+						&bh->inreq_busy, &bh->state);
-+				fsg->next_buffhd_to_fill = bh->next;
-+			}
-+		}
-+
-+		/*
-+		 * For Bulk-only, mark the end of the data with a short
-+		 * packet.  If we are allowed to stall, halt the bulk-in
-+		 * endpoint.  (Note: This violates the Bulk-Only Transport
-+		 * specification, which requires us to pad the data if we
-+		 * don't halt the endpoint.  Presumably nobody will mind.)
-+		 */
-+		else {
-+			bh->inreq->zero = 1;
-+			start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+					&bh->inreq_busy, &bh->state);
-+			fsg->next_buffhd_to_fill = bh->next;
-+			if (mod_data.can_stall)
-+				rc = halt_bulk_in_endpoint(fsg);
-+		}
-+		break;
-+
-+	/* We have processed all we want from the data the host has sent.
-+	 * There may still be outstanding bulk-out requests. */
-+	case DATA_DIR_FROM_HOST:
-+		if (fsg->residue == 0)
-+			;		// Nothing to receive
-+
-+		/* Did the host stop sending unexpectedly early? */
-+		else if (fsg->short_packet_received) {
-+			raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+			rc = -EINTR;
-+		}
-+
-+		/* We haven't processed all the incoming data.  Even though
-+		 * we may be allowed to stall, doing so would cause a race.
-+		 * The controller may already have ACK'ed all the remaining
-+		 * bulk-out packets, in which case the host wouldn't see a
-+		 * STALL.  Not realizing the endpoint was halted, it wouldn't
-+		 * clear the halt -- leading to problems later on. */
-+#if 0
-+		else if (mod_data.can_stall) {
-+			fsg_set_halt(fsg, fsg->bulk_out);
-+			raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
-+			rc = -EINTR;
-+		}
-+#endif
-+
-+		/* We can't stall.  Read in the excess data and throw it
-+		 * all away. */
-+		else
-+			rc = throw_away_data(fsg);
-+		break;
-+	}
-+	return rc;
-+}
-+
-+
-+static int send_status(struct fsg_dev *fsg)
-+{
-+	struct fsg_lun		*curlun = fsg->curlun;
-+	struct fsg_buffhd	*bh;
-+	int			rc;
-+	u8			status = US_BULK_STAT_OK;
-+	u32			sd, sdinfo = 0;
-+
-+	/* Wait for the next buffer to become available */
-+	bh = fsg->next_buffhd_to_fill;
-+	while (bh->state != BUF_STATE_EMPTY) {
-+		rc = sleep_thread(fsg);
-+		if (rc)
-+			return rc;
-+	}
-+
-+	if (curlun) {
-+		sd = curlun->sense_data;
-+		sdinfo = curlun->sense_data_info;
-+	} else if (fsg->bad_lun_okay)
-+		sd = SS_NO_SENSE;
-+	else
-+		sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
-+
-+	if (fsg->phase_error) {
-+		DBG(fsg, "sending phase-error status\n");
-+		status = US_BULK_STAT_PHASE;
-+		sd = SS_INVALID_COMMAND;
-+	} else if (sd != SS_NO_SENSE) {
-+		DBG(fsg, "sending command-failure status\n");
-+		status = US_BULK_STAT_FAIL;
-+		VDBG(fsg, "  sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
-+				"  info x%x\n",
-+				SK(sd), ASC(sd), ASCQ(sd), sdinfo);
-+	}
-+
-+	if (transport_is_bbb()) {
-+		struct bulk_cs_wrap	*csw = bh->buf;
-+
-+		/* Store and send the Bulk-only CSW */
-+		csw->Signature = cpu_to_le32(US_BULK_CS_SIGN);
-+		csw->Tag = fsg->tag;
-+		csw->Residue = cpu_to_le32(fsg->residue);
-+		csw->Status = status;
-+
-+		bh->inreq->length = US_BULK_CS_WRAP_LEN;
-+		bh->inreq->zero = 0;
-+		start_transfer(fsg, fsg->bulk_in, bh->inreq,
-+				&bh->inreq_busy, &bh->state);
-+
-+	} else if (mod_data.transport_type == USB_PR_CB) {
-+
-+		/* Control-Bulk transport has no status phase! */
-+		return 0;
-+
-+	} else {			// USB_PR_CBI
-+		struct interrupt_data	*buf = bh->buf;
-+
-+		/* Store and send the Interrupt data.  UFI sends the ASC
-+		 * and ASCQ bytes.  Everything else sends a Type (which
-+		 * is always 0) and the status Value. */
-+		if (mod_data.protocol_type == USB_SC_UFI) {
-+			buf->bType = ASC(sd);
-+			buf->bValue = ASCQ(sd);
-+		} else {
-+			buf->bType = 0;
-+			buf->bValue = status;
-+		}
-+		fsg->intreq->length = CBI_INTERRUPT_DATA_LEN;
-+
-+		fsg->intr_buffhd = bh;		// Point to the right buffhd
-+		fsg->intreq->buf = bh->inreq->buf;
-+		fsg->intreq->context = bh;
-+		start_transfer(fsg, fsg->intr_in, fsg->intreq,
-+				&fsg->intreq_busy, &bh->state);
-+	}
-+
-+	fsg->next_buffhd_to_fill = bh->next;
-+	return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Check whether the command is properly formed and whether its data size
-+ * and direction agree with the values we already have. */
-+static int check_command(struct fsg_dev *fsg, int cmnd_size,
-+		enum data_direction data_dir, unsigned int mask,
-+		int needs_medium, const char *name)
-+{
-+	int			i;
-+	int			lun = fsg->cmnd[1] >> 5;
-+	static const char	dirletter[4] = {'u', 'o', 'i', 'n'};
-+	char			hdlen[20];
-+	struct fsg_lun		*curlun;
-+
-+	/* Adjust the expected cmnd_size for protocol encapsulation padding.
-+	 * Transparent SCSI doesn't pad. */
-+	if (protocol_is_scsi())
-+		;
-+
-+	/* There's some disagreement as to whether RBC pads commands or not.
-+	 * We'll play it safe and accept either form. */
-+	else if (mod_data.protocol_type == USB_SC_RBC) {
-+		if (fsg->cmnd_size == 12)
-+			cmnd_size = 12;
-+
-+	/* All the other protocols pad to 12 bytes */
-+	} else
-+		cmnd_size = 12;
-+
-+	hdlen[0] = 0;
-+	if (fsg->data_dir != DATA_DIR_UNKNOWN)
-+		sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
-+				fsg->data_size);
-+	VDBG(fsg, "SCSI command: %s;  Dc=%d, D%c=%u;  Hc=%d%s\n",
-+			name, cmnd_size, dirletter[(int) data_dir],
-+			fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
-+
-+	/* We can't reply at all until we know the correct data direction
-+	 * and size. */
-+	if (fsg->data_size_from_cmnd == 0)
-+		data_dir = DATA_DIR_NONE;
-+	if (fsg->data_dir == DATA_DIR_UNKNOWN) {	// CB or CBI
-+		fsg->data_dir = data_dir;
-+		fsg->data_size = fsg->data_size_from_cmnd;
-+
-+	} else {					// Bulk-only
-+		if (fsg->data_size < fsg->data_size_from_cmnd) {
-+
-+			/* Host data size < Device data size is a phase error.
-+			 * Carry out the command, but only transfer as much
-+			 * as we are allowed. */
-+			fsg->data_size_from_cmnd = fsg->data_size;
-+			fsg->phase_error = 1;
-+		}
-+	}
-+	fsg->residue = fsg->usb_amount_left = fsg->data_size;
-+
-+	/* Conflicting data directions is a phase error */
-+	if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
-+		fsg->phase_error = 1;
-+		return -EINVAL;
-+	}
-+
-+	/* Verify the length of the command itself */
-+	if (cmnd_size != fsg->cmnd_size) {
-+
-+		/* Special case workaround: There are plenty of buggy SCSI
-+		 * implementations. Many have issues with cbw->Length
-+		 * field passing a wrong command size. For those cases we
-+		 * always try to work around the problem by using the length
-+		 * sent by the host side provided it is at least as large
-+		 * as the correct command length.
-+		 * Examples of such cases would be MS-Windows, which issues
-+		 * REQUEST SENSE with cbw->Length == 12 where it should
-+		 * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and
-+		 * REQUEST SENSE with cbw->Length == 10 where it should
-+		 * be 6 as well.
-+		 */
-+		if (cmnd_size <= fsg->cmnd_size) {
-+			DBG(fsg, "%s is buggy! Expected length %d "
-+					"but we got %d\n", name,
-+					cmnd_size, fsg->cmnd_size);
-+			cmnd_size = fsg->cmnd_size;
-+		} else {
-+			fsg->phase_error = 1;
-+			return -EINVAL;
-+		}
-+	}
-+
-+	/* Check that the LUN values are consistent */
-+	if (transport_is_bbb()) {
-+		if (fsg->lun != lun)
-+			DBG(fsg, "using LUN %d from CBW, "
-+					"not LUN %d from CDB\n",
-+					fsg->lun, lun);
-+	}
-+
-+	/* Check the LUN */
-+	curlun = fsg->curlun;
-+	if (curlun) {
-+		if (fsg->cmnd[0] != REQUEST_SENSE) {
-+			curlun->sense_data = SS_NO_SENSE;
-+			curlun->sense_data_info = 0;
-+			curlun->info_valid = 0;
-+		}
-+	} else {
-+		fsg->bad_lun_okay = 0;
-+
-+		/* INQUIRY and REQUEST SENSE commands are explicitly allowed
-+		 * to use unsupported LUNs; all others may not. */
-+		if (fsg->cmnd[0] != INQUIRY &&
-+				fsg->cmnd[0] != REQUEST_SENSE) {
-+			DBG(fsg, "unsupported LUN %d\n", fsg->lun);
-+			return -EINVAL;
-+		}
-+	}
-+
-+	/* If a unit attention condition exists, only INQUIRY and
-+	 * REQUEST SENSE commands are allowed; anything else must fail. */
-+	if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
-+			fsg->cmnd[0] != INQUIRY &&
-+			fsg->cmnd[0] != REQUEST_SENSE) {
-+		curlun->sense_data = curlun->unit_attention_data;
-+		curlun->unit_attention_data = SS_NO_SENSE;
-+		return -EINVAL;
-+	}
-+
-+	/* Check that only command bytes listed in the mask are non-zero */
-+	fsg->cmnd[1] &= 0x1f;			// Mask away the LUN
-+	for (i = 1; i < cmnd_size; ++i) {
-+		if (fsg->cmnd[i] && !(mask & (1 << i))) {
-+			if (curlun)
-+				curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
-+			return -EINVAL;
-+		}
-+	}
-+
-+	/* If the medium isn't mounted and the command needs to access
-+	 * it, return an error. */
-+	if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
-+		curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/* wrapper of check_command for data size in blocks handling */
-+static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,
-+		enum data_direction data_dir, unsigned int mask,
-+		int needs_medium, const char *name)
-+{
-+	if (fsg->curlun)
-+		fsg->data_size_from_cmnd <<= fsg->curlun->blkbits;
-+	return check_command(fsg, cmnd_size, data_dir,
-+			mask, needs_medium, name);
-+}
-+
-+static int do_scsi_command(struct fsg_dev *fsg)
-+{
-+	struct fsg_buffhd	*bh;
-+	int			rc;
-+	int			reply = -EINVAL;
-+	int			i;
-+	static char		unknown[16];
-+
-+	dump_cdb(fsg);
-+
-+	/* Wait for the next buffer to become available for data or status */
-+	bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
-+	while (bh->state != BUF_STATE_EMPTY) {
-+		rc = sleep_thread(fsg);
-+		if (rc)
-+			return rc;
-+	}
-+	fsg->phase_error = 0;
-+	fsg->short_packet_received = 0;
-+
-+	down_read(&fsg->filesem);	// We're using the backing file
-+	switch (fsg->cmnd[0]) {
-+
-+	case INQUIRY:
-+		fsg->data_size_from_cmnd = fsg->cmnd[4];
-+		if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+				(1<<4), 0,
-+				"INQUIRY")) == 0)
-+			reply = do_inquiry(fsg, bh);
-+		break;
-+
-+	case MODE_SELECT:
-+		fsg->data_size_from_cmnd = fsg->cmnd[4];
-+		if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
-+				(1<<1) | (1<<4), 0,
-+				"MODE SELECT(6)")) == 0)
-+			reply = do_mode_select(fsg, bh);
-+		break;
-+
-+	case MODE_SELECT_10:
-+		fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+		if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
-+				(1<<1) | (3<<7), 0,
-+				"MODE SELECT(10)")) == 0)
-+			reply = do_mode_select(fsg, bh);
-+		break;
-+
-+	case MODE_SENSE:
-+		fsg->data_size_from_cmnd = fsg->cmnd[4];
-+		if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+				(1<<1) | (1<<2) | (1<<4), 0,
-+				"MODE SENSE(6)")) == 0)
-+			reply = do_mode_sense(fsg, bh);
-+		break;
-+
-+	case MODE_SENSE_10:
-+		fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+				(1<<1) | (1<<2) | (3<<7), 0,
-+				"MODE SENSE(10)")) == 0)
-+			reply = do_mode_sense(fsg, bh);
-+		break;
-+
-+	case ALLOW_MEDIUM_REMOVAL:
-+		fsg->data_size_from_cmnd = 0;
-+		if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
-+				(1<<4), 0,
-+				"PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
-+			reply = do_prevent_allow(fsg);
-+		break;
-+
-+	case READ_6:
-+		i = fsg->cmnd[4];
-+		fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
-+		if ((reply = check_command_size_in_blocks(fsg, 6,
-+				DATA_DIR_TO_HOST,
-+				(7<<1) | (1<<4), 1,
-+				"READ(6)")) == 0)
-+			reply = do_read(fsg);
-+		break;
-+
-+	case READ_10:
-+		fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+		if ((reply = check_command_size_in_blocks(fsg, 10,
-+				DATA_DIR_TO_HOST,
-+				(1<<1) | (0xf<<2) | (3<<7), 1,
-+				"READ(10)")) == 0)
-+			reply = do_read(fsg);
-+		break;
-+
-+	case READ_12:
-+		fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
-+		if ((reply = check_command_size_in_blocks(fsg, 12,
-+				DATA_DIR_TO_HOST,
-+				(1<<1) | (0xf<<2) | (0xf<<6), 1,
-+				"READ(12)")) == 0)
-+			reply = do_read(fsg);
-+		break;
-+
-+	case READ_CAPACITY:
-+		fsg->data_size_from_cmnd = 8;
-+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+				(0xf<<2) | (1<<8), 1,
-+				"READ CAPACITY")) == 0)
-+			reply = do_read_capacity(fsg, bh);
-+		break;
-+
-+	case READ_HEADER:
-+		if (!mod_data.cdrom)
-+			goto unknown_cmnd;
-+		fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+				(3<<7) | (0x1f<<1), 1,
-+				"READ HEADER")) == 0)
-+			reply = do_read_header(fsg, bh);
-+		break;
-+
-+	case READ_TOC:
-+		if (!mod_data.cdrom)
-+			goto unknown_cmnd;
-+		fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+				(7<<6) | (1<<1), 1,
-+				"READ TOC")) == 0)
-+			reply = do_read_toc(fsg, bh);
-+		break;
-+
-+	case READ_FORMAT_CAPACITIES:
-+		fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
-+				(3<<7), 1,
-+				"READ FORMAT CAPACITIES")) == 0)
-+			reply = do_read_format_capacities(fsg, bh);
-+		break;
-+
-+	case REQUEST_SENSE:
-+		fsg->data_size_from_cmnd = fsg->cmnd[4];
-+		if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
-+				(1<<4), 0,
-+				"REQUEST SENSE")) == 0)
-+			reply = do_request_sense(fsg, bh);
-+		break;
-+
-+	case START_STOP:
-+		fsg->data_size_from_cmnd = 0;
-+		if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
-+				(1<<1) | (1<<4), 0,
-+				"START-STOP UNIT")) == 0)
-+			reply = do_start_stop(fsg);
-+		break;
-+
-+	case SYNCHRONIZE_CACHE:
-+		fsg->data_size_from_cmnd = 0;
-+		if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
-+				(0xf<<2) | (3<<7), 1,
-+				"SYNCHRONIZE CACHE")) == 0)
-+			reply = do_synchronize_cache(fsg);
-+		break;
-+
-+	case TEST_UNIT_READY:
-+		fsg->data_size_from_cmnd = 0;
-+		reply = check_command(fsg, 6, DATA_DIR_NONE,
-+				0, 1,
-+				"TEST UNIT READY");
-+		break;
-+
-+	/* Although optional, this command is used by MS-Windows.  We
-+	 * support a minimal version: BytChk must be 0. */
-+	case VERIFY:
-+		fsg->data_size_from_cmnd = 0;
-+		if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
-+				(1<<1) | (0xf<<2) | (3<<7), 1,
-+				"VERIFY")) == 0)
-+			reply = do_verify(fsg);
-+		break;
-+
-+	case WRITE_6:
-+		i = fsg->cmnd[4];
-+		fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
-+		if ((reply = check_command_size_in_blocks(fsg, 6,
-+				DATA_DIR_FROM_HOST,
-+				(7<<1) | (1<<4), 1,
-+				"WRITE(6)")) == 0)
-+			reply = do_write(fsg);
-+		break;
-+
-+	case WRITE_10:
-+		fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
-+		if ((reply = check_command_size_in_blocks(fsg, 10,
-+				DATA_DIR_FROM_HOST,
-+				(1<<1) | (0xf<<2) | (3<<7), 1,
-+				"WRITE(10)")) == 0)
-+			reply = do_write(fsg);
-+		break;
-+
-+	case WRITE_12:
-+		fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
-+		if ((reply = check_command_size_in_blocks(fsg, 12,
-+				DATA_DIR_FROM_HOST,
-+				(1<<1) | (0xf<<2) | (0xf<<6), 1,
-+				"WRITE(12)")) == 0)
-+			reply = do_write(fsg);
-+		break;
-+
-+	/* Some mandatory commands that we recognize but don't implement.
-+	 * They don't mean much in this setting.  It's left as an exercise
-+	 * for anyone interested to implement RESERVE and RELEASE in terms
-+	 * of Posix locks. */
-+	case FORMAT_UNIT:
-+	case RELEASE:
-+	case RESERVE:
-+	case SEND_DIAGNOSTIC:
-+		// Fall through
-+
-+	default:
-+ unknown_cmnd:
-+		fsg->data_size_from_cmnd = 0;
-+		sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
-+		if ((reply = check_command(fsg, fsg->cmnd_size,
-+				DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
-+			fsg->curlun->sense_data = SS_INVALID_COMMAND;
-+			reply = -EINVAL;
-+		}
-+		break;
-+	}
-+	up_read(&fsg->filesem);
-+
-+	if (reply == -EINTR || signal_pending(current))
-+		return -EINTR;
-+
-+	/* Set up the single reply buffer for finish_reply() */
-+	if (reply == -EINVAL)
-+		reply = 0;		// Error reply length
-+	if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
-+		reply = min((u32) reply, fsg->data_size_from_cmnd);
-+		bh->inreq->length = reply;
-+		bh->state = BUF_STATE_FULL;
-+		fsg->residue -= reply;
-+	}				// Otherwise it's already set
-+
-+	return 0;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
-+{
-+	struct usb_request		*req = bh->outreq;
-+	struct bulk_cb_wrap	*cbw = req->buf;
-+
-+	/* Was this a real packet?  Should it be ignored? */
-+	if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
-+		return -EINVAL;
-+
-+	/* Is the CBW valid? */
-+	if (req->actual != US_BULK_CB_WRAP_LEN ||
-+			cbw->Signature != cpu_to_le32(
-+				US_BULK_CB_SIGN)) {
-+		DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
-+				req->actual,
-+				le32_to_cpu(cbw->Signature));
-+
-+		/* The Bulk-only spec says we MUST stall the IN endpoint
-+		 * (6.6.1), so it's unavoidable.  It also says we must
-+		 * retain this state until the next reset, but there's
-+		 * no way to tell the controller driver it should ignore
-+		 * Clear-Feature(HALT) requests.
-+		 *
-+		 * We aren't required to halt the OUT endpoint; instead
-+		 * we can simply accept and discard any data received
-+		 * until the next reset. */
-+		wedge_bulk_in_endpoint(fsg);
-+		set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
-+		return -EINVAL;
-+	}
-+
-+	/* Is the CBW meaningful? */
-+	if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||
-+			cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
-+		DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
-+				"cmdlen %u\n",
-+				cbw->Lun, cbw->Flags, cbw->Length);
-+
-+		/* We can do anything we want here, so let's stall the
-+		 * bulk pipes if we are allowed to. */
-+		if (mod_data.can_stall) {
-+			fsg_set_halt(fsg, fsg->bulk_out);
-+			halt_bulk_in_endpoint(fsg);
-+		}
-+		return -EINVAL;
-+	}
-+
-+	/* Save the command for later */
-+	fsg->cmnd_size = cbw->Length;
-+	memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
-+	if (cbw->Flags & US_BULK_FLAG_IN)
-+		fsg->data_dir = DATA_DIR_TO_HOST;
-+	else
-+		fsg->data_dir = DATA_DIR_FROM_HOST;
-+	fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
-+	if (fsg->data_size == 0)
-+		fsg->data_dir = DATA_DIR_NONE;
-+	fsg->lun = cbw->Lun;
-+	fsg->tag = cbw->Tag;
-+	return 0;
-+}
-+
-+
-+static int get_next_command(struct fsg_dev *fsg)
-+{
-+	struct fsg_buffhd	*bh;
-+	int			rc = 0;
-+
-+	if (transport_is_bbb()) {
-+
-+		/* Wait for the next buffer to become available */
-+		bh = fsg->next_buffhd_to_fill;
-+		while (bh->state != BUF_STATE_EMPTY) {
-+			rc = sleep_thread(fsg);
-+			if (rc)
-+				return rc;
-+		}
-+
-+		/* Queue a request to read a Bulk-only CBW */
-+		set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);
-+		start_transfer(fsg, fsg->bulk_out, bh->outreq,
-+				&bh->outreq_busy, &bh->state);
-+
-+		/* We will drain the buffer in software, which means we
-+		 * can reuse it for the next filling.  No need to advance
-+		 * next_buffhd_to_fill. */
-+
-+		/* Wait for the CBW to arrive */
-+		while (bh->state != BUF_STATE_FULL) {
-+			rc = sleep_thread(fsg);
-+			if (rc)
-+				return rc;
-+		}
-+		smp_rmb();
-+		rc = received_cbw(fsg, bh);
-+		bh->state = BUF_STATE_EMPTY;
-+
-+	} else {		// USB_PR_CB or USB_PR_CBI
-+
-+		/* Wait for the next command to arrive */
-+		while (fsg->cbbuf_cmnd_size == 0) {
-+			rc = sleep_thread(fsg);
-+			if (rc)
-+				return rc;
-+		}
-+
-+		/* Is the previous status interrupt request still busy?
-+		 * The host is allowed to skip reading the status,
-+		 * so we must cancel it. */
-+		if (fsg->intreq_busy)
-+			usb_ep_dequeue(fsg->intr_in, fsg->intreq);
-+
-+		/* Copy the command and mark the buffer empty */
-+		fsg->data_dir = DATA_DIR_UNKNOWN;
-+		spin_lock_irq(&fsg->lock);
-+		fsg->cmnd_size = fsg->cbbuf_cmnd_size;
-+		memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);
-+		fsg->cbbuf_cmnd_size = 0;
-+		spin_unlock_irq(&fsg->lock);
-+
-+		/* Use LUN from the command */
-+		fsg->lun = fsg->cmnd[1] >> 5;
-+	}
-+
-+	/* Update current lun */
-+	if (fsg->lun >= 0 && fsg->lun < fsg->nluns)
-+		fsg->curlun = &fsg->luns[fsg->lun];
-+	else
-+		fsg->curlun = NULL;
-+
-+	return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
-+		const struct usb_endpoint_descriptor *d)
-+{
-+	int	rc;
-+
-+	ep->driver_data = fsg;
-+	ep->desc = d;
-+	rc = usb_ep_enable(ep);
-+	if (rc)
-+		ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
-+	return rc;
-+}
-+
-+static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
-+		struct usb_request **preq)
-+{
-+	*preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
-+	if (*preq)
-+		return 0;
-+	ERROR(fsg, "can't allocate request for %s\n", ep->name);
-+	return -ENOMEM;
-+}
-+
-+/*
-+ * Reset interface setting and re-init endpoint state (toggle etc).
-+ * Call with altsetting < 0 to disable the interface.  The only other
-+ * available altsetting is 0, which enables the interface.
-+ */
-+static int do_set_interface(struct fsg_dev *fsg, int altsetting)
-+{
-+	int	rc = 0;
-+	int	i;
-+	const struct usb_endpoint_descriptor	*d;
-+
-+	if (fsg->running)
-+		DBG(fsg, "reset interface\n");
-+
-+reset:
-+	/* Deallocate the requests */
-+	for (i = 0; i < fsg_num_buffers; ++i) {
-+		struct fsg_buffhd *bh = &fsg->buffhds[i];
-+
-+		if (bh->inreq) {
-+			usb_ep_free_request(fsg->bulk_in, bh->inreq);
-+			bh->inreq = NULL;
-+		}
-+		if (bh->outreq) {
-+			usb_ep_free_request(fsg->bulk_out, bh->outreq);
-+			bh->outreq = NULL;
-+		}
-+	}
-+	if (fsg->intreq) {
-+		usb_ep_free_request(fsg->intr_in, fsg->intreq);
-+		fsg->intreq = NULL;
-+	}
-+
-+	/* Disable the endpoints */
-+	if (fsg->bulk_in_enabled) {
-+		usb_ep_disable(fsg->bulk_in);
-+		fsg->bulk_in_enabled = 0;
-+	}
-+	if (fsg->bulk_out_enabled) {
-+		usb_ep_disable(fsg->bulk_out);
-+		fsg->bulk_out_enabled = 0;
-+	}
-+	if (fsg->intr_in_enabled) {
-+		usb_ep_disable(fsg->intr_in);
-+		fsg->intr_in_enabled = 0;
-+	}
-+
-+	fsg->running = 0;
-+	if (altsetting < 0 || rc != 0)
-+		return rc;
-+
-+	DBG(fsg, "set interface %d\n", altsetting);
-+
-+	/* Enable the endpoints */
-+	d = fsg_ep_desc(fsg->gadget,
-+			&fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,
-+			&fsg_ss_bulk_in_desc);
-+	if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
-+		goto reset;
-+	fsg->bulk_in_enabled = 1;
-+
-+	d = fsg_ep_desc(fsg->gadget,
-+			&fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,
-+			&fsg_ss_bulk_out_desc);
-+	if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
-+		goto reset;
-+	fsg->bulk_out_enabled = 1;
-+	fsg->bulk_out_maxpacket = usb_endpoint_maxp(d);
-+	clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
-+
-+	if (transport_is_cbi()) {
-+		d = fsg_ep_desc(fsg->gadget,
-+				&fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,
-+				&fsg_ss_intr_in_desc);
-+		if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)
-+			goto reset;
-+		fsg->intr_in_enabled = 1;
-+	}
-+
-+	/* Allocate the requests */
-+	for (i = 0; i < fsg_num_buffers; ++i) {
-+		struct fsg_buffhd	*bh = &fsg->buffhds[i];
-+
-+		if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)
-+			goto reset;
-+		if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)
-+			goto reset;
-+		bh->inreq->buf = bh->outreq->buf = bh->buf;
-+		bh->inreq->context = bh->outreq->context = bh;
-+		bh->inreq->complete = bulk_in_complete;
-+		bh->outreq->complete = bulk_out_complete;
-+	}
-+	if (transport_is_cbi()) {
-+		if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)
-+			goto reset;
-+		fsg->intreq->complete = intr_in_complete;
-+	}
-+
-+	fsg->running = 1;
-+	for (i = 0; i < fsg->nluns; ++i)
-+		fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
-+	return rc;
-+}
-+
-+
-+/*
-+ * Change our operational configuration.  This code must agree with the code
-+ * that returns config descriptors, and with interface altsetting code.
-+ *
-+ * It's also responsible for power management interactions.  Some
-+ * configurations might not work with our current power sources.
-+ * For now we just assume the gadget is always self-powered.
-+ */
-+static int do_set_config(struct fsg_dev *fsg, u8 new_config)
-+{
-+	int	rc = 0;
-+
-+	/* Disable the single interface */
-+	if (fsg->config != 0) {
-+		DBG(fsg, "reset config\n");
-+		fsg->config = 0;
-+		rc = do_set_interface(fsg, -1);
-+	}
-+
-+	/* Enable the interface */
-+	if (new_config != 0) {
-+		fsg->config = new_config;
-+		if ((rc = do_set_interface(fsg, 0)) != 0)
-+			fsg->config = 0;	// Reset on errors
-+		else
-+			INFO(fsg, "%s config #%d\n",
-+			     usb_speed_string(fsg->gadget->speed),
-+			     fsg->config);
-+	}
-+	return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void handle_exception(struct fsg_dev *fsg)
-+{
-+	siginfo_t		info;
-+	int			sig;
-+	int			i;
-+	int			num_active;
-+	struct fsg_buffhd	*bh;
-+	enum fsg_state		old_state;
-+	u8			new_config;
-+	struct fsg_lun		*curlun;
-+	unsigned int		exception_req_tag;
-+	int			rc;
-+
-+	/* Clear the existing signals.  Anything but SIGUSR1 is converted
-+	 * into a high-priority EXIT exception. */
-+	for (;;) {
-+		sig = dequeue_signal_lock(current, &current->blocked, &info);
-+		if (!sig)
-+			break;
-+		if (sig != SIGUSR1) {
-+			if (fsg->state < FSG_STATE_EXIT)
-+				DBG(fsg, "Main thread exiting on signal\n");
-+			raise_exception(fsg, FSG_STATE_EXIT);
-+		}
-+	}
-+
-+	/* Cancel all the pending transfers */
-+	if (fsg->intreq_busy)
-+		usb_ep_dequeue(fsg->intr_in, fsg->intreq);
-+	for (i = 0; i < fsg_num_buffers; ++i) {
-+		bh = &fsg->buffhds[i];
-+		if (bh->inreq_busy)
-+			usb_ep_dequeue(fsg->bulk_in, bh->inreq);
-+		if (bh->outreq_busy)
-+			usb_ep_dequeue(fsg->bulk_out, bh->outreq);
-+	}
-+
-+	/* Wait until everything is idle */
-+	for (;;) {
-+		num_active = fsg->intreq_busy;
-+		for (i = 0; i < fsg_num_buffers; ++i) {
-+			bh = &fsg->buffhds[i];
-+			num_active += bh->inreq_busy + bh->outreq_busy;
-+		}
-+		if (num_active == 0)
-+			break;
-+		if (sleep_thread(fsg))
-+			return;
-+	}
-+
-+	/* Clear out the controller's fifos */
-+	if (fsg->bulk_in_enabled)
-+		usb_ep_fifo_flush(fsg->bulk_in);
-+	if (fsg->bulk_out_enabled)
-+		usb_ep_fifo_flush(fsg->bulk_out);
-+	if (fsg->intr_in_enabled)
-+		usb_ep_fifo_flush(fsg->intr_in);
-+
-+	/* Reset the I/O buffer states and pointers, the SCSI
-+	 * state, and the exception.  Then invoke the handler. */
-+	spin_lock_irq(&fsg->lock);
-+
-+	for (i = 0; i < fsg_num_buffers; ++i) {
-+		bh = &fsg->buffhds[i];
-+		bh->state = BUF_STATE_EMPTY;
-+	}
-+	fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
-+			&fsg->buffhds[0];
-+
-+	exception_req_tag = fsg->exception_req_tag;
-+	new_config = fsg->new_config;
-+	old_state = fsg->state;
-+
-+	if (old_state == FSG_STATE_ABORT_BULK_OUT)
-+		fsg->state = FSG_STATE_STATUS_PHASE;
-+	else {
-+		for (i = 0; i < fsg->nluns; ++i) {
-+			curlun = &fsg->luns[i];
-+			curlun->prevent_medium_removal = 0;
-+			curlun->sense_data = curlun->unit_attention_data =
-+					SS_NO_SENSE;
-+			curlun->sense_data_info = 0;
-+			curlun->info_valid = 0;
-+		}
-+		fsg->state = FSG_STATE_IDLE;
-+	}
-+	spin_unlock_irq(&fsg->lock);
-+
-+	/* Carry out any extra actions required for the exception */
-+	switch (old_state) {
-+	default:
-+		break;
-+
-+	case FSG_STATE_ABORT_BULK_OUT:
-+		send_status(fsg);
-+		spin_lock_irq(&fsg->lock);
-+		if (fsg->state == FSG_STATE_STATUS_PHASE)
-+			fsg->state = FSG_STATE_IDLE;
-+		spin_unlock_irq(&fsg->lock);
-+		break;
-+
-+	case FSG_STATE_RESET:
-+		/* In case we were forced against our will to halt a
-+		 * bulk endpoint, clear the halt now.  (The SuperH UDC
-+		 * requires this.) */
-+		if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
-+			usb_ep_clear_halt(fsg->bulk_in);
-+
-+		if (transport_is_bbb()) {
-+			if (fsg->ep0_req_tag == exception_req_tag)
-+				ep0_queue(fsg);	// Complete the status stage
-+
-+		} else if (transport_is_cbi())
-+			send_status(fsg);	// Status by interrupt pipe
-+
-+		/* Technically this should go here, but it would only be
-+		 * a waste of time.  Ditto for the INTERFACE_CHANGE and
-+		 * CONFIG_CHANGE cases. */
-+		// for (i = 0; i < fsg->nluns; ++i)
-+		//	fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
-+		break;
-+
-+	case FSG_STATE_INTERFACE_CHANGE:
-+		rc = do_set_interface(fsg, 0);
-+		if (fsg->ep0_req_tag != exception_req_tag)
-+			break;
-+		if (rc != 0)			// STALL on errors
-+			fsg_set_halt(fsg, fsg->ep0);
-+		else				// Complete the status stage
-+			ep0_queue(fsg);
-+		break;
-+
-+	case FSG_STATE_CONFIG_CHANGE:
-+		rc = do_set_config(fsg, new_config);
-+		if (fsg->ep0_req_tag != exception_req_tag)
-+			break;
-+		if (rc != 0)			// STALL on errors
-+			fsg_set_halt(fsg, fsg->ep0);
-+		else				// Complete the status stage
-+			ep0_queue(fsg);
-+		break;
-+
-+	case FSG_STATE_DISCONNECT:
-+		for (i = 0; i < fsg->nluns; ++i)
-+			fsg_lun_fsync_sub(fsg->luns + i);
-+		do_set_config(fsg, 0);		// Unconfigured state
-+		break;
-+
-+	case FSG_STATE_EXIT:
-+	case FSG_STATE_TERMINATED:
-+		do_set_config(fsg, 0);			// Free resources
-+		spin_lock_irq(&fsg->lock);
-+		fsg->state = FSG_STATE_TERMINATED;	// Stop the thread
-+		spin_unlock_irq(&fsg->lock);
-+		break;
-+	}
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static int fsg_main_thread(void *fsg_)
-+{
-+	struct fsg_dev		*fsg = fsg_;
-+
-+	/* Allow the thread to be killed by a signal, but set the signal mask
-+	 * to block everything but INT, TERM, KILL, and USR1. */
-+	allow_signal(SIGINT);
-+	allow_signal(SIGTERM);
-+	allow_signal(SIGKILL);
-+	allow_signal(SIGUSR1);
-+
-+	/* Allow the thread to be frozen */
-+	set_freezable();
-+
-+	/* Arrange for userspace references to be interpreted as kernel
-+	 * pointers.  That way we can pass a kernel pointer to a routine
-+	 * that expects a __user pointer and it will work okay. */
-+	set_fs(get_ds());
-+
-+	/* The main loop */
-+	while (fsg->state != FSG_STATE_TERMINATED) {
-+		if (exception_in_progress(fsg) || signal_pending(current)) {
-+			handle_exception(fsg);
-+			continue;
-+		}
-+
-+		if (!fsg->running) {
-+			sleep_thread(fsg);
-+			continue;
-+		}
-+
-+		if (get_next_command(fsg))
-+			continue;
-+
-+		spin_lock_irq(&fsg->lock);
-+		if (!exception_in_progress(fsg))
-+			fsg->state = FSG_STATE_DATA_PHASE;
-+		spin_unlock_irq(&fsg->lock);
-+
-+		if (do_scsi_command(fsg) || finish_reply(fsg))
-+			continue;
-+
-+		spin_lock_irq(&fsg->lock);
-+		if (!exception_in_progress(fsg))
-+			fsg->state = FSG_STATE_STATUS_PHASE;
-+		spin_unlock_irq(&fsg->lock);
-+
-+		if (send_status(fsg))
-+			continue;
-+
-+		spin_lock_irq(&fsg->lock);
-+		if (!exception_in_progress(fsg))
-+			fsg->state = FSG_STATE_IDLE;
-+		spin_unlock_irq(&fsg->lock);
-+		}
-+
-+	spin_lock_irq(&fsg->lock);
-+	fsg->thread_task = NULL;
-+	spin_unlock_irq(&fsg->lock);
-+
-+	/* If we are exiting because of a signal, unregister the
-+	 * gadget driver. */
-+	if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
-+		usb_gadget_unregister_driver(&fsg_driver);
-+
-+	/* Let the unbind and cleanup routines know the thread has exited */
-+	complete_and_exit(&fsg->thread_notifier, 0);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/* The write permissions and store_xxx pointers are set in fsg_bind() */
-+static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);
-+static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);
-+static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void fsg_release(struct kref *ref)
-+{
-+	struct fsg_dev	*fsg = container_of(ref, struct fsg_dev, ref);
-+
-+	kfree(fsg->luns);
-+	kfree(fsg);
-+}
-+
-+static void lun_release(struct device *dev)
-+{
-+	struct rw_semaphore	*filesem = dev_get_drvdata(dev);
-+	struct fsg_dev		*fsg =
-+		container_of(filesem, struct fsg_dev, filesem);
-+
-+	kref_put(&fsg->ref, fsg_release);
-+}
-+
-+static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
-+{
-+	struct fsg_dev		*fsg = get_gadget_data(gadget);
-+	int			i;
-+	struct fsg_lun		*curlun;
-+	struct usb_request	*req = fsg->ep0req;
-+
-+	DBG(fsg, "unbind\n");
-+	clear_bit(REGISTERED, &fsg->atomic_bitflags);
-+
-+	/* If the thread isn't already dead, tell it to exit now */
-+	if (fsg->state != FSG_STATE_TERMINATED) {
-+		raise_exception(fsg, FSG_STATE_EXIT);
-+		wait_for_completion(&fsg->thread_notifier);
-+
-+		/* The cleanup routine waits for this completion also */
-+		complete(&fsg->thread_notifier);
-+	}
-+
-+	/* Unregister the sysfs attribute files and the LUNs */
-+	for (i = 0; i < fsg->nluns; ++i) {
-+		curlun = &fsg->luns[i];
-+		if (curlun->registered) {
-+			device_remove_file(&curlun->dev, &dev_attr_nofua);
-+			device_remove_file(&curlun->dev, &dev_attr_ro);
-+			device_remove_file(&curlun->dev, &dev_attr_file);
-+			fsg_lun_close(curlun);
-+			device_unregister(&curlun->dev);
-+			curlun->registered = 0;
-+		}
-+	}
-+
-+	/* Free the data buffers */
-+	for (i = 0; i < fsg_num_buffers; ++i)
-+		kfree(fsg->buffhds[i].buf);
-+
-+	/* Free the request and buffer for endpoint 0 */
-+	if (req) {
-+		kfree(req->buf);
-+		usb_ep_free_request(fsg->ep0, req);
-+	}
-+
-+	set_gadget_data(gadget, NULL);
-+}
-+
-+
-+static int __init check_parameters(struct fsg_dev *fsg)
-+{
-+	int	prot;
-+	int	gcnum;
-+
-+	/* Store the default values */
-+	mod_data.transport_type = USB_PR_BULK;
-+	mod_data.transport_name = "Bulk-only";
-+	mod_data.protocol_type = USB_SC_SCSI;
-+	mod_data.protocol_name = "Transparent SCSI";
-+
-+	/* Some peripheral controllers are known not to be able to
-+	 * halt bulk endpoints correctly.  If one of them is present,
-+	 * disable stalls.
-+	 */
-+	if (gadget_is_at91(fsg->gadget))
-+		mod_data.can_stall = 0;
-+
-+	if (mod_data.release == 0xffff) {	// Parameter wasn't set
-+		gcnum = usb_gadget_controller_number(fsg->gadget);
-+		if (gcnum >= 0)
-+			mod_data.release = 0x0300 + gcnum;
-+		else {
-+			WARNING(fsg, "controller '%s' not recognized\n",
-+				fsg->gadget->name);
-+			mod_data.release = 0x0399;
-+		}
-+	}
-+
-+	prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
-+
-+#ifdef CONFIG_USB_FILE_STORAGE_TEST
-+	if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
-+		;		// Use default setting
-+	} else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) {
-+		mod_data.transport_type = USB_PR_CB;
-+		mod_data.transport_name = "Control-Bulk";
-+	} else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) {
-+		mod_data.transport_type = USB_PR_CBI;
-+		mod_data.transport_name = "Control-Bulk-Interrupt";
-+	} else {
-+		ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm);
-+		return -EINVAL;
-+	}
-+
-+	if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 ||
-+			prot == USB_SC_SCSI) {
-+		;		// Use default setting
-+	} else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 ||
-+			prot == USB_SC_RBC) {
-+		mod_data.protocol_type = USB_SC_RBC;
-+		mod_data.protocol_name = "RBC";
-+	} else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 ||
-+			strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 ||
-+			prot == USB_SC_8020) {
-+		mod_data.protocol_type = USB_SC_8020;
-+		mod_data.protocol_name = "8020i (ATAPI)";
-+	} else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 ||
-+			prot == USB_SC_QIC) {
-+		mod_data.protocol_type = USB_SC_QIC;
-+		mod_data.protocol_name = "QIC-157";
-+	} else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 ||
-+			prot == USB_SC_UFI) {
-+		mod_data.protocol_type = USB_SC_UFI;
-+		mod_data.protocol_name = "UFI";
-+	} else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 ||
-+			prot == USB_SC_8070) {
-+		mod_data.protocol_type = USB_SC_8070;
-+		mod_data.protocol_name = "8070i";
-+	} else {
-+		ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm);
-+		return -EINVAL;
-+	}
-+
-+	mod_data.buflen &= PAGE_CACHE_MASK;
-+	if (mod_data.buflen <= 0) {
-+		ERROR(fsg, "invalid buflen\n");
-+		return -ETOOSMALL;
-+	}
-+
-+#endif /* CONFIG_USB_FILE_STORAGE_TEST */
-+
-+	/* Serial string handling.
-+	 * On a real device, the serial string would be loaded
-+	 * from permanent storage. */
-+	if (mod_data.serial) {
-+		const char *ch;
-+		unsigned len = 0;
-+
-+		/* Sanity check :
-+		 * The CB[I] specification limits the serial string to
-+		 * 12 uppercase hexadecimal characters.
-+		 * BBB need at least 12 uppercase hexadecimal characters,
-+		 * with a maximum of 126. */
-+		for (ch = mod_data.serial; *ch; ++ch) {
-+			++len;
-+			if ((*ch < '0' || *ch > '9') &&
-+			    (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */
-+				WARNING(fsg,
-+					"Invalid serial string character: %c\n",
-+					*ch);
-+				goto no_serial;
-+			}
-+		}
-+		if (len > 126 ||
-+		    (mod_data.transport_type == USB_PR_BULK && len < 12) ||
-+		    (mod_data.transport_type != USB_PR_BULK && len > 12)) {
-+			WARNING(fsg, "Invalid serial string length!\n");
-+			goto no_serial;
-+		}
-+		fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;
-+	} else {
-+		WARNING(fsg, "No serial-number string provided!\n");
-+ no_serial:
-+		device_desc.iSerialNumber = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static int __init fsg_bind(struct usb_gadget *gadget)
-+{
-+	struct fsg_dev		*fsg = the_fsg;
-+	int			rc;
-+	int			i;
-+	struct fsg_lun		*curlun;
-+	struct usb_ep		*ep;
-+	struct usb_request	*req;
-+	char			*pathbuf, *p;
-+
-+	fsg->gadget = gadget;
-+	set_gadget_data(gadget, fsg);
-+	fsg->ep0 = gadget->ep0;
-+	fsg->ep0->driver_data = fsg;
-+
-+	if ((rc = check_parameters(fsg)) != 0)
-+		goto out;
-+
-+	if (mod_data.removable) {	// Enable the store_xxx attributes
-+		dev_attr_file.attr.mode = 0644;
-+		dev_attr_file.store = fsg_store_file;
-+		if (!mod_data.cdrom) {
-+			dev_attr_ro.attr.mode = 0644;
-+			dev_attr_ro.store = fsg_store_ro;
-+		}
-+	}
-+
-+	/* Only for removable media? */
-+	dev_attr_nofua.attr.mode = 0644;
-+	dev_attr_nofua.store = fsg_store_nofua;
-+
-+	/* Find out how many LUNs there should be */
-+	i = mod_data.nluns;
-+	if (i == 0)
-+		i = max(mod_data.num_filenames, 1u);
-+	if (i > FSG_MAX_LUNS) {
-+		ERROR(fsg, "invalid number of LUNs: %d\n", i);
-+		rc = -EINVAL;
-+		goto out;
-+	}
-+
-+	/* Create the LUNs, open their backing files, and register the
-+	 * LUN devices in sysfs. */
-+	fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);
-+	if (!fsg->luns) {
-+		rc = -ENOMEM;
-+		goto out;
-+	}
-+	fsg->nluns = i;
-+
-+	for (i = 0; i < fsg->nluns; ++i) {
-+		curlun = &fsg->luns[i];
-+		curlun->cdrom = !!mod_data.cdrom;
-+		curlun->ro = mod_data.cdrom || mod_data.ro[i];
-+		curlun->initially_ro = curlun->ro;
-+		curlun->removable = mod_data.removable;
-+		curlun->nofua = mod_data.nofua[i];
-+		curlun->dev.release = lun_release;
-+		curlun->dev.parent = &gadget->dev;
-+		curlun->dev.driver = &fsg_driver.driver;
-+		dev_set_drvdata(&curlun->dev, &fsg->filesem);
-+		dev_set_name(&curlun->dev,"%s-lun%d",
-+			     dev_name(&gadget->dev), i);
-+
-+		kref_get(&fsg->ref);
-+		rc = device_register(&curlun->dev);
-+		if (rc) {
-+			INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
-+			put_device(&curlun->dev);
-+			goto out;
-+		}
-+		curlun->registered = 1;
-+
-+		rc = device_create_file(&curlun->dev, &dev_attr_ro);
-+		if (rc)
-+			goto out;
-+		rc = device_create_file(&curlun->dev, &dev_attr_nofua);
-+		if (rc)
-+			goto out;
-+		rc = device_create_file(&curlun->dev, &dev_attr_file);
-+		if (rc)
-+			goto out;
-+
-+		if (mod_data.file[i] && *mod_data.file[i]) {
-+			rc = fsg_lun_open(curlun, mod_data.file[i]);
-+			if (rc)
-+				goto out;
-+		} else if (!mod_data.removable) {
-+			ERROR(fsg, "no file given for LUN%d\n", i);
-+			rc = -EINVAL;
-+			goto out;
-+		}
-+	}
-+
-+	/* Find all the endpoints we will use */
-+	usb_ep_autoconfig_reset(gadget);
-+	ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
-+	if (!ep)
-+		goto autoconf_fail;
-+	ep->driver_data = fsg;		// claim the endpoint
-+	fsg->bulk_in = ep;
-+
-+	ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);
-+	if (!ep)
-+		goto autoconf_fail;
-+	ep->driver_data = fsg;		// claim the endpoint
-+	fsg->bulk_out = ep;
-+
-+	if (transport_is_cbi()) {
-+		ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);
-+		if (!ep)
-+			goto autoconf_fail;
-+		ep->driver_data = fsg;		// claim the endpoint
-+		fsg->intr_in = ep;
-+	}
-+
-+	/* Fix up the descriptors */
-+	device_desc.idVendor = cpu_to_le16(mod_data.vendor);
-+	device_desc.idProduct = cpu_to_le16(mod_data.product);
-+	device_desc.bcdDevice = cpu_to_le16(mod_data.release);
-+
-+	i = (transport_is_cbi() ? 3 : 2);	// Number of endpoints
-+	fsg_intf_desc.bNumEndpoints = i;
-+	fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;
-+	fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;
-+	fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+	if (gadget_is_dualspeed(gadget)) {
-+		fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+		/* Assume endpoint addresses are the same for both speeds */
-+		fsg_hs_bulk_in_desc.bEndpointAddress =
-+			fsg_fs_bulk_in_desc.bEndpointAddress;
-+		fsg_hs_bulk_out_desc.bEndpointAddress =
-+			fsg_fs_bulk_out_desc.bEndpointAddress;
-+		fsg_hs_intr_in_desc.bEndpointAddress =
-+			fsg_fs_intr_in_desc.bEndpointAddress;
-+	}
-+
-+	if (gadget_is_superspeed(gadget)) {
-+		unsigned		max_burst;
-+
-+		fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;
-+
-+		/* Calculate bMaxBurst, we know packet size is 1024 */
-+		max_burst = min_t(unsigned, mod_data.buflen / 1024, 15);
-+
-+		/* Assume endpoint addresses are the same for both speeds */
-+		fsg_ss_bulk_in_desc.bEndpointAddress =
-+			fsg_fs_bulk_in_desc.bEndpointAddress;
-+		fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;
-+
-+		fsg_ss_bulk_out_desc.bEndpointAddress =
-+			fsg_fs_bulk_out_desc.bEndpointAddress;
-+		fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;
-+	}
-+
-+	if (gadget_is_otg(gadget))
-+		fsg_otg_desc.bmAttributes |= USB_OTG_HNP;
-+
-+	rc = -ENOMEM;
-+
-+	/* Allocate the request and buffer for endpoint 0 */
-+	fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
-+	if (!req)
-+		goto out;
-+	req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);
-+	if (!req->buf)
-+		goto out;
-+	req->complete = ep0_complete;
-+
-+	/* Allocate the data buffers */
-+	for (i = 0; i < fsg_num_buffers; ++i) {
-+		struct fsg_buffhd	*bh = &fsg->buffhds[i];
-+
-+		/* Allocate for the bulk-in endpoint.  We assume that
-+		 * the buffer will also work with the bulk-out (and
-+		 * interrupt-in) endpoint. */
-+		bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);
-+		if (!bh->buf)
-+			goto out;
-+		bh->next = bh + 1;
-+	}
-+	fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];
-+
-+	/* This should reflect the actual gadget power source */
-+	usb_gadget_set_selfpowered(gadget);
-+
-+	snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,
-+			"%s %s with %s",
-+			init_utsname()->sysname, init_utsname()->release,
-+			gadget->name);
-+
-+	fsg->thread_task = kthread_create(fsg_main_thread, fsg,
-+			"file-storage-gadget");
-+	if (IS_ERR(fsg->thread_task)) {
-+		rc = PTR_ERR(fsg->thread_task);
-+		goto out;
-+	}
-+
-+	INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n");
-+	INFO(fsg, "NOTE: This driver is deprecated.  "
-+			"Consider using g_mass_storage instead.\n");
-+	INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
-+
-+	pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
-+	for (i = 0; i < fsg->nluns; ++i) {
-+		curlun = &fsg->luns[i];
-+		if (fsg_lun_is_open(curlun)) {
-+			p = NULL;
-+			if (pathbuf) {
-+				p = d_path(&curlun->filp->f_path,
-+					   pathbuf, PATH_MAX);
-+				if (IS_ERR(p))
-+					p = NULL;
-+			}
-+			LINFO(curlun, "ro=%d, nofua=%d, file: %s\n",
-+			      curlun->ro, curlun->nofua, (p ? p : "(error)"));
-+		}
-+	}
-+	kfree(pathbuf);
-+
-+	DBG(fsg, "transport=%s (x%02x)\n",
-+			mod_data.transport_name, mod_data.transport_type);
-+	DBG(fsg, "protocol=%s (x%02x)\n",
-+			mod_data.protocol_name, mod_data.protocol_type);
-+	DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
-+			mod_data.vendor, mod_data.product, mod_data.release);
-+	DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
-+			mod_data.removable, mod_data.can_stall,
-+			mod_data.cdrom, mod_data.buflen);
-+	DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
-+
-+	set_bit(REGISTERED, &fsg->atomic_bitflags);
-+
-+	/* Tell the thread to start working */
-+	wake_up_process(fsg->thread_task);
-+	return 0;
-+
-+autoconf_fail:
-+	ERROR(fsg, "unable to autoconfigure all endpoints\n");
-+	rc = -ENOTSUPP;
-+
-+out:
-+	fsg->state = FSG_STATE_TERMINATED;	// The thread is dead
-+	fsg_unbind(gadget);
-+	complete(&fsg->thread_notifier);
-+	return rc;
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void fsg_suspend(struct usb_gadget *gadget)
-+{
-+	struct fsg_dev		*fsg = get_gadget_data(gadget);
-+
-+	DBG(fsg, "suspend\n");
-+	set_bit(SUSPENDED, &fsg->atomic_bitflags);
-+}
-+
-+static void fsg_resume(struct usb_gadget *gadget)
-+{
-+	struct fsg_dev		*fsg = get_gadget_data(gadget);
-+
-+	DBG(fsg, "resume\n");
-+	clear_bit(SUSPENDED, &fsg->atomic_bitflags);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_gadget_driver		fsg_driver = {
-+	.max_speed	= USB_SPEED_SUPER,
-+	.function	= (char *) fsg_string_product,
-+	.unbind		= fsg_unbind,
-+	.disconnect	= fsg_disconnect,
-+	.setup		= fsg_setup,
-+	.suspend	= fsg_suspend,
-+	.resume		= fsg_resume,
-+
-+	.driver		= {
-+		.name		= DRIVER_NAME,
-+		.owner		= THIS_MODULE,
-+		// .release = ...
-+		// .suspend = ...
-+		// .resume = ...
-+	},
-+};
-+
-+
-+static int __init fsg_alloc(void)
-+{
-+	struct fsg_dev		*fsg;
-+
-+	fsg = kzalloc(sizeof *fsg +
-+		      fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);
-+
-+	if (!fsg)
-+		return -ENOMEM;
-+	spin_lock_init(&fsg->lock);
-+	init_rwsem(&fsg->filesem);
-+	kref_init(&fsg->ref);
-+	init_completion(&fsg->thread_notifier);
-+
-+	the_fsg = fsg;
-+	return 0;
-+}
-+
-+
-+static int __init fsg_init(void)
-+{
-+	int		rc;
-+	struct fsg_dev	*fsg;
-+
-+	rc = fsg_num_buffers_validate();
-+	if (rc != 0)
-+		return rc;
-+
-+	if ((rc = fsg_alloc()) != 0)
-+		return rc;
-+	fsg = the_fsg;
-+	if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)
-+		kref_put(&fsg->ref, fsg_release);
-+	return rc;
-+}
-+module_init(fsg_init);
-+
-+
-+static void __exit fsg_cleanup(void)
-+{
-+	struct fsg_dev	*fsg = the_fsg;
-+
-+	/* Unregister the driver iff the thread hasn't already done so */
-+	if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
-+		usb_gadget_unregister_driver(&fsg_driver);
-+
-+	/* Wait for the thread to finish up */
-+	wait_for_completion(&fsg->thread_notifier);
-+
-+	kref_put(&fsg->ref, fsg_release);
-+}
-+module_exit(fsg_cleanup);
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -763,6 +763,16 @@ config USB_HWA_HCD
- 	  To compile this driver a module, choose M here: the module
- 	  will be called "hwa-hc".
- 
-+config USB_DWCOTG
-+	bool "Synopsis DWC host support"
-+	depends on USB && (FIQ || ARM64)
-+	help
-+	  The Synopsis DWC controller is a dual-role
-+	  host/peripheral/OTG ("On The Go") USB controllers.
-+
-+	  Enable this option to support this IP in host controller mode.
-+	  If unsure, say N.
-+
- config USB_IMX21_HCD
-        tristate "i.MX21 HCD support"
-        depends on ARM && ARCH_MXC
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -73,6 +73,8 @@ obj-$(CONFIG_USB_SL811_CS)	+= sl811_cs.o
- obj-$(CONFIG_USB_U132_HCD)	+= u132-hcd.o
- obj-$(CONFIG_USB_R8A66597_HCD)	+= r8a66597-hcd.o
- obj-$(CONFIG_USB_HWA_HCD)	+= hwa-hc.o
-+
-+obj-$(CONFIG_USB_DWCOTG)        += dwc_otg/ dwc_common_port/
- obj-$(CONFIG_USB_IMX21_HCD)	+= imx21-hcd.o
- obj-$(CONFIG_USB_FSL_USB2)	+= fsl-mph-dr-of.o
- obj-$(CONFIG_USB_EHCI_FSL)	+= fsl-mph-dr-of.o
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/Makefile
-@@ -0,0 +1,58 @@
-+#
-+# Makefile for DWC_common library
-+#
-+
-+ifneq ($(KERNELRELEASE),)
-+
-+ccflags-y	+= -DDWC_LINUX
-+#ccflags-y	+= -DDEBUG
-+#ccflags-y	+= -DDWC_DEBUG_REGS
-+#ccflags-y	+= -DDWC_DEBUG_MEMORY
-+
-+ccflags-y	+= -DDWC_LIBMODULE
-+ccflags-y	+= -DDWC_CCLIB
-+#ccflags-y	+= -DDWC_CRYPTOLIB
-+ccflags-y	+= -DDWC_NOTIFYLIB
-+ccflags-y	+= -DDWC_UTFLIB
-+
-+obj-$(CONFIG_USB_DWCOTG)	+= dwc_common_port_lib.o
-+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
-+			    dwc_crypto.o dwc_notifier.o \
-+			    dwc_common_linux.o dwc_mem.o
-+
-+kernrelwd := $(subst ., ,$(KERNELRELEASE))
-+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
-+
-+ifneq ($(kernrel3),2.6.20)
-+# grayg - I only know that we use ccflags-y in 2.6.31 actually
-+ccflags-y += $(CPPFLAGS)
-+endif
-+
-+else
-+
-+#ifeq ($(KDIR),)
-+#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
-+#endif
-+
-+ifeq ($(ARCH),)
-+$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
-+ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
-+endif
-+
-+ifeq ($(DOXYGEN),)
-+DOXYGEN		:= doxygen
-+endif
-+
-+default:
-+	$(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+docs:	$(wildcard *.[hc]) doc/doxygen.cfg
-+	$(DOXYGEN) doc/doxygen.cfg
-+
-+tags:	$(wildcard *.[hc])
-+	$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+endif
-+
-+clean:
-+	rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/Makefile.fbsd
-@@ -0,0 +1,17 @@
-+CFLAGS	+= -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include
-+CFLAGS	+= -DDWC_FREEBSD
-+CFLAGS	+= -DDEBUG
-+#CFLAGS	+= -DDWC_DEBUG_REGS
-+#CFLAGS	+= -DDWC_DEBUG_MEMORY
-+
-+#CFLAGS	+= -DDWC_LIBMODULE
-+#CFLAGS	+= -DDWC_CCLIB
-+#CFLAGS	+= -DDWC_CRYPTOLIB
-+#CFLAGS	+= -DDWC_NOTIFYLIB
-+#CFLAGS	+= -DDWC_UTFLIB
-+
-+KMOD = dwc_common_port_lib
-+SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \
-+       dwc_common_fbsd.c dwc_mem.c
-+
-+.include <bsd.kmod.mk>
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/Makefile.linux
-@@ -0,0 +1,49 @@
-+#
-+# Makefile for DWC_common library
-+#
-+ifneq ($(KERNELRELEASE),)
-+
-+ccflags-y	+= -DDWC_LINUX
-+#ccflags-y	+= -DDEBUG
-+#ccflags-y	+= -DDWC_DEBUG_REGS
-+#ccflags-y	+= -DDWC_DEBUG_MEMORY
-+
-+ccflags-y	+= -DDWC_LIBMODULE
-+ccflags-y	+= -DDWC_CCLIB
-+ccflags-y	+= -DDWC_CRYPTOLIB
-+ccflags-y	+= -DDWC_NOTIFYLIB
-+ccflags-y	+= -DDWC_UTFLIB
-+
-+obj-m			 := dwc_common_port_lib.o
-+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
-+			    dwc_crypto.o dwc_notifier.o \
-+			    dwc_common_linux.o dwc_mem.o
-+
-+else
-+
-+ifeq ($(KDIR),)
-+$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
-+endif
-+
-+ifeq ($(ARCH),)
-+$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
-+ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
-+endif
-+
-+ifeq ($(DOXYGEN),)
-+DOXYGEN		:= doxygen
-+endif
-+
-+default:
-+	$(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+docs:	$(wildcard *.[hc]) doc/doxygen.cfg
-+	$(DOXYGEN) doc/doxygen.cfg
-+
-+tags:	$(wildcard *.[hc])
-+	$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+endif
-+
-+clean:
-+	rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/changes.txt
-@@ -0,0 +1,174 @@
-+
-+dwc_read_reg32() and friends now take an additional parameter, a pointer to an
-+IO context struct. The IO context struct should live in an os-dependent struct
-+in your driver. As an example, the dwc_usb3 driver has an os-dependent struct
-+named 'os_dep' embedded in the main device struct. So there these calls look
-+like this:
-+
-+	dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);
-+
-+	dwc_write_reg32(&usb3_dev->os_dep.ioctx,
-+			&pcd->dev_global_regs->dcfg, 0);
-+
-+Note that for the existing Linux driver ports, it is not necessary to actually
-+define the 'ioctx' member in the os-dependent struct. Since Linux does not
-+require an IO context, its macros for dwc_read_reg32() and friends do not
-+use the context pointer, so it is optimized away by the compiler. But it is
-+necessary to add the pointer parameter to all of the call sites, to be ready
-+for any future ports (such as FreeBSD) which do require an IO context.
-+
-+
-+Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now
-+take an additional parameter, a pointer to a memory context. Examples:
-+
-+	addr = dwc_alloc(&usb3_dev->os_dep.memctx, size);
-+
-+	dwc_free(&usb3_dev->os_dep.memctx, addr);
-+
-+Again, for the Linux ports, it is not necessary to actually define the memctx
-+member, but it is necessary to add the pointer parameter to all of the call
-+sites.
-+
-+
-+Same for dwc_dma_alloc() and dwc_dma_free(). Examples:
-+
-+	virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);
-+
-+	dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);
-+
-+
-+Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:
-+
-+	mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);
-+
-+	dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);
-+
-+
-+Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:
-+
-+	lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);
-+
-+	dwc_spinlock_free(&usb3_dev->osdep.splctx, lock);
-+
-+
-+Same for dwc_timer_alloc(). Example:
-+
-+	timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1",
-+				cb_func, cb_data);
-+
-+
-+Same for dwc_waitq_alloc(). Example:
-+
-+	waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);
-+
-+
-+Same for dwc_thread_run(). Example:
-+
-+	thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,
-+				"dwc_usb3_thd1", data);
-+
-+
-+Same for dwc_workq_alloc(). Example:
-+
-+	workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1");
-+
-+
-+Same for dwc_task_alloc(). Example:
-+
-+	task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1",
-+			      cb_func, cb_data);
-+
-+
-+In addition to the context pointer additions, a few core functions have had
-+other changes made to their parameters:
-+
-+The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()
-+has been changed from a uint64_t to a dwc_irqflags_t.
-+
-+dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the
-+FreeBSD equivalent of that function requires it.
-+
-+And, in addition to the context pointer, dwc_task_alloc() also adds a
-+'char *name' parameter, to be consistent with dwc_thread_run() and
-+dwc_workq_alloc(), and because the FreeBSD equivalent of that function
-+requires a unique name.
-+
-+
-+Here is a complete list of the core functions that now take a pointer to a
-+context as their first parameter:
-+
-+	dwc_read_reg32
-+	dwc_read_reg64
-+	dwc_write_reg32
-+	dwc_write_reg64
-+	dwc_modify_reg32
-+	dwc_modify_reg64
-+	dwc_alloc
-+	dwc_alloc_atomic
-+	dwc_strdup
-+	dwc_free
-+	dwc_dma_alloc
-+	dwc_dma_free
-+	dwc_mutex_alloc
-+	dwc_mutex_free
-+	dwc_spinlock_alloc
-+	dwc_spinlock_free
-+	dwc_timer_alloc
-+	dwc_waitq_alloc
-+	dwc_thread_run
-+	dwc_workq_alloc
-+	dwc_task_alloc     Also adds a 'char *name' as its 2nd parameter
-+
-+And here are the core functions that have other changes to their parameters:
-+
-+	dwc_spinlock_irqsave      'flags' param is now a 'dwc_irqflags_t *'
-+	dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'
-+	dwc_thread_should_stop    Adds a 'dwc_thread_t *' parameter
-+
-+
-+
-+The changes to the core functions also require some of the other library
-+functions to change:
-+
-+	dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'
-+	(for memory allocation) as the 1st param and a 'void *mtxctx'
-+	(for mutex allocation) as the 2nd param.
-+
-+	dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),
-+	dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a
-+	'void *memctx' as the 1st param.
-+
-+	dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a
-+	'void *memctx' as the 1st param.
-+
-+	dwc_modpow() now takes a 'void *memctx' as the 1st param.
-+
-+	dwc_alloc_notification_manager() now takes a 'void *memctx' as the
-+	1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd
-+	param, and also now returns an integer value that is non-zero if
-+	allocation of its data structures or work queue fails.
-+
-+	dwc_register_notifier() now takes a 'void *memctx' as the 1st param.
-+
-+	dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first
-+	param, and also now returns an integer value that is non-zero if
-+	allocation of its data structures fails.
-+
-+
-+
-+Other miscellaneous changes:
-+
-+The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to
-+DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.
-+
-+The following #define's have been added to allow selectively compiling library
-+features:
-+
-+	DWC_CCLIB
-+	DWC_CRYPTOLIB
-+	DWC_NOTIFYLIB
-+	DWC_UTFLIB
-+
-+A DWC_LIBMODULE #define has also been added. If this is not defined, then the
-+module code in dwc_common_linux.c is not compiled in. This allows linking the
-+library code directly into a driver module, instead of as a standalone module.
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
-@@ -0,0 +1,270 @@
-+# Doxyfile 1.4.5
-+
-+#---------------------------------------------------------------------------
-+# Project related configuration options
-+#---------------------------------------------------------------------------
-+PROJECT_NAME           = "Synopsys DWC Portability and Common Library for UWB"
-+PROJECT_NUMBER         =
-+OUTPUT_DIRECTORY       = doc
-+CREATE_SUBDIRS         = NO
-+OUTPUT_LANGUAGE        = English
-+BRIEF_MEMBER_DESC      = YES
-+REPEAT_BRIEF           = YES
-+ABBREVIATE_BRIEF       = "The $name class" \
-+                         "The $name widget" \
-+                         "The $name file" \
-+                         is \
-+                         provides \
-+                         specifies \
-+                         contains \
-+                         represents \
-+                         a \
-+                         an \
-+                         the
-+ALWAYS_DETAILED_SEC    = YES
-+INLINE_INHERITED_MEMB  = NO
-+FULL_PATH_NAMES        = NO
-+STRIP_FROM_PATH        = ..
-+STRIP_FROM_INC_PATH    =
-+SHORT_NAMES            = NO
-+JAVADOC_AUTOBRIEF      = YES
-+MULTILINE_CPP_IS_BRIEF = NO
-+DETAILS_AT_TOP         = YES
-+INHERIT_DOCS           = YES
-+SEPARATE_MEMBER_PAGES  = NO
-+TAB_SIZE               = 8
-+ALIASES                =
-+OPTIMIZE_OUTPUT_FOR_C  = YES
-+OPTIMIZE_OUTPUT_JAVA   = NO
-+BUILTIN_STL_SUPPORT    = NO
-+DISTRIBUTE_GROUP_DOC   = NO
-+SUBGROUPING            = NO
-+#---------------------------------------------------------------------------
-+# Build related configuration options
-+#---------------------------------------------------------------------------
-+EXTRACT_ALL            = NO
-+EXTRACT_PRIVATE        = NO
-+EXTRACT_STATIC         = YES
-+EXTRACT_LOCAL_CLASSES  = NO
-+EXTRACT_LOCAL_METHODS  = NO
-+HIDE_UNDOC_MEMBERS     = NO
-+HIDE_UNDOC_CLASSES     = NO
-+HIDE_FRIEND_COMPOUNDS  = NO
-+HIDE_IN_BODY_DOCS      = NO
-+INTERNAL_DOCS          = NO
-+CASE_SENSE_NAMES       = YES
-+HIDE_SCOPE_NAMES       = NO
-+SHOW_INCLUDE_FILES     = NO
-+INLINE_INFO            = YES
-+SORT_MEMBER_DOCS       = NO
-+SORT_BRIEF_DOCS        = NO
-+SORT_BY_SCOPE_NAME     = NO
-+GENERATE_TODOLIST      = YES
-+GENERATE_TESTLIST      = YES
-+GENERATE_BUGLIST       = YES
-+GENERATE_DEPRECATEDLIST= YES
-+ENABLED_SECTIONS       =
-+MAX_INITIALIZER_LINES  = 30
-+SHOW_USED_FILES        = YES
-+SHOW_DIRECTORIES       = YES
-+FILE_VERSION_FILTER    =
-+#---------------------------------------------------------------------------
-+# configuration options related to warning and progress messages
-+#---------------------------------------------------------------------------
-+QUIET                  = YES
-+WARNINGS               = YES
-+WARN_IF_UNDOCUMENTED   = NO
-+WARN_IF_DOC_ERROR      = YES
-+WARN_NO_PARAMDOC       = YES
-+WARN_FORMAT            = "$file:$line: $text"
-+WARN_LOGFILE           =
-+#---------------------------------------------------------------------------
-+# configuration options related to the input files
-+#---------------------------------------------------------------------------
-+INPUT                  = .
-+FILE_PATTERNS          = *.c \
-+                         *.cc \
-+                         *.cxx \
-+                         *.cpp \
-+                         *.c++ \
-+                         *.d \
-+                         *.java \
-+                         *.ii \
-+                         *.ixx \
-+                         *.ipp \
-+                         *.i++ \
-+                         *.inl \
-+                         *.h \
-+                         *.hh \
-+                         *.hxx \
-+                         *.hpp \
-+                         *.h++ \
-+                         *.idl \
-+                         *.odl \
-+                         *.cs \
-+                         *.php \
-+                         *.php3 \
-+                         *.inc \
-+                         *.m \
-+                         *.mm \
-+                         *.dox \
-+                         *.py \
-+                         *.C \
-+                         *.CC \
-+                         *.C++ \
-+                         *.II \
-+                         *.I++ \
-+                         *.H \
-+                         *.HH \
-+                         *.H++ \
-+                         *.CS \
-+                         *.PHP \
-+                         *.PHP3 \
-+                         *.M \
-+                         *.MM \
-+                         *.PY
-+RECURSIVE              = NO
-+EXCLUDE                =
-+EXCLUDE_SYMLINKS       = NO
-+EXCLUDE_PATTERNS       =
-+EXAMPLE_PATH           =
-+EXAMPLE_PATTERNS       = *
-+EXAMPLE_RECURSIVE      = NO
-+IMAGE_PATH             =
-+INPUT_FILTER           =
-+FILTER_PATTERNS        =
-+FILTER_SOURCE_FILES    = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to source browsing
-+#---------------------------------------------------------------------------
-+SOURCE_BROWSER         = NO
-+INLINE_SOURCES         = NO
-+STRIP_CODE_COMMENTS    = YES
-+REFERENCED_BY_RELATION = YES
-+REFERENCES_RELATION    = YES
-+USE_HTAGS              = NO
-+VERBATIM_HEADERS       = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the alphabetical class index
-+#---------------------------------------------------------------------------
-+ALPHABETICAL_INDEX     = NO
-+COLS_IN_ALPHA_INDEX    = 5
-+IGNORE_PREFIX          =
-+#---------------------------------------------------------------------------
-+# configuration options related to the HTML output
-+#---------------------------------------------------------------------------
-+GENERATE_HTML          = YES
-+HTML_OUTPUT            = html
-+HTML_FILE_EXTENSION    = .html
-+HTML_HEADER            =
-+HTML_FOOTER            =
-+HTML_STYLESHEET        =
-+HTML_ALIGN_MEMBERS     = YES
-+GENERATE_HTMLHELP      = NO
-+CHM_FILE               =
-+HHC_LOCATION           =
-+GENERATE_CHI           = NO
-+BINARY_TOC             = NO
-+TOC_EXPAND             = NO
-+DISABLE_INDEX          = NO
-+ENUM_VALUES_PER_LINE   = 4
-+GENERATE_TREEVIEW      = YES
-+TREEVIEW_WIDTH         = 250
-+#---------------------------------------------------------------------------
-+# configuration options related to the LaTeX output
-+#---------------------------------------------------------------------------
-+GENERATE_LATEX         = NO
-+LATEX_OUTPUT           = latex
-+LATEX_CMD_NAME         = latex
-+MAKEINDEX_CMD_NAME     = makeindex
-+COMPACT_LATEX          = NO
-+PAPER_TYPE             = a4wide
-+EXTRA_PACKAGES         =
-+LATEX_HEADER           =
-+PDF_HYPERLINKS         = NO
-+USE_PDFLATEX           = NO
-+LATEX_BATCHMODE        = NO
-+LATEX_HIDE_INDICES     = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the RTF output
-+#---------------------------------------------------------------------------
-+GENERATE_RTF           = NO
-+RTF_OUTPUT             = rtf
-+COMPACT_RTF            = NO
-+RTF_HYPERLINKS         = NO
-+RTF_STYLESHEET_FILE    =
-+RTF_EXTENSIONS_FILE    =
-+#---------------------------------------------------------------------------
-+# configuration options related to the man page output
-+#---------------------------------------------------------------------------
-+GENERATE_MAN           = NO
-+MAN_OUTPUT             = man
-+MAN_EXTENSION          = .3
-+MAN_LINKS              = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the XML output
-+#---------------------------------------------------------------------------
-+GENERATE_XML           = NO
-+XML_OUTPUT             = xml
-+XML_SCHEMA             =
-+XML_DTD                =
-+XML_PROGRAMLISTING     = YES
-+#---------------------------------------------------------------------------
-+# configuration options for the AutoGen Definitions output
-+#---------------------------------------------------------------------------
-+GENERATE_AUTOGEN_DEF   = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the Perl module output
-+#---------------------------------------------------------------------------
-+GENERATE_PERLMOD       = NO
-+PERLMOD_LATEX          = NO
-+PERLMOD_PRETTY         = YES
-+PERLMOD_MAKEVAR_PREFIX =
-+#---------------------------------------------------------------------------
-+# Configuration options related to the preprocessor
-+#---------------------------------------------------------------------------
-+ENABLE_PREPROCESSING   = YES
-+MACRO_EXPANSION        = NO
-+EXPAND_ONLY_PREDEF     = NO
-+SEARCH_INCLUDES        = YES
-+INCLUDE_PATH           =
-+INCLUDE_FILE_PATTERNS  =
-+PREDEFINED             = DEBUG DEBUG_MEMORY
-+EXPAND_AS_DEFINED      =
-+SKIP_FUNCTION_MACROS   = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to external references
-+#---------------------------------------------------------------------------
-+TAGFILES               =
-+GENERATE_TAGFILE       =
-+ALLEXTERNALS           = NO
-+EXTERNAL_GROUPS        = YES
-+PERL_PATH              = /usr/bin/perl
-+#---------------------------------------------------------------------------
-+# Configuration options related to the dot tool
-+#---------------------------------------------------------------------------
-+CLASS_DIAGRAMS         = YES
-+HIDE_UNDOC_RELATIONS   = YES
-+HAVE_DOT               = NO
-+CLASS_GRAPH            = YES
-+COLLABORATION_GRAPH    = YES
-+GROUP_GRAPHS           = YES
-+UML_LOOK               = NO
-+TEMPLATE_RELATIONS     = NO
-+INCLUDE_GRAPH          = NO
-+INCLUDED_BY_GRAPH      = YES
-+CALL_GRAPH             = NO
-+GRAPHICAL_HIERARCHY    = YES
-+DIRECTORY_GRAPH        = YES
-+DOT_IMAGE_FORMAT       = png
-+DOT_PATH               =
-+DOTFILE_DIRS           =
-+MAX_DOT_GRAPH_DEPTH    = 1000
-+DOT_TRANSPARENT        = NO
-+DOT_MULTI_TARGETS      = NO
-+GENERATE_LEGEND        = YES
-+DOT_CLEANUP            = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to the search engine
-+#---------------------------------------------------------------------------
-+SEARCHENGINE           = NO
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_cc.c
-@@ -0,0 +1,532 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $
-+ * $Revision: #4 $
-+ * $Date: 2010/11/04 $
-+ * $Change: 1621692 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifdef DWC_CCLIB
-+
-+#include "dwc_cc.h"
-+
-+typedef struct dwc_cc
-+{
-+	uint32_t uid;
-+	uint8_t chid[16];
-+	uint8_t cdid[16];
-+	uint8_t ck[16];
-+	uint8_t *name;
-+	uint8_t length;
-+        DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
-+} dwc_cc_t;
-+
-+DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
-+
-+/** The main structure for CC management.  */
-+struct dwc_cc_if
-+{
-+	dwc_mutex_t *mutex;
-+	char *filename;
-+
-+	unsigned is_host:1;
-+
-+	dwc_notifier_t *notifier;
-+
-+	struct context_list list;
-+};
-+
-+#ifdef DEBUG
-+static inline void dump_bytes(char *name, uint8_t *bytes, int len)
-+{
-+	int i;
-+	DWC_PRINTF("%s: ", name);
-+	for (i=0; i<len; i++) {
-+		DWC_PRINTF("%02x ", bytes[i]);
-+	}
-+	DWC_PRINTF("\n");
-+}
-+#else
-+#define dump_bytes(x...)
-+#endif
-+
-+static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)
-+{
-+	dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));
-+	if (!cc) {
-+		return NULL;
-+	}
-+	DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
-+
-+	if (name) {
-+		cc->length = length;
-+		cc->name = dwc_alloc(mem_ctx, length);
-+		if (!cc->name) {
-+			dwc_free(mem_ctx, cc);
-+			return NULL;
-+		}
-+
-+		DWC_MEMCPY(cc->name, name, length);
-+	}
-+
-+	return cc;
-+}
-+
-+static void free_cc(void *mem_ctx, dwc_cc_t *cc)
-+{
-+	if (cc->name) {
-+		dwc_free(mem_ctx, cc->name);
-+	}
-+	dwc_free(mem_ctx, cc);
-+}
-+
-+static uint32_t next_uid(dwc_cc_if_t *cc_if)
-+{
-+	uint32_t uid = 0;
-+	dwc_cc_t *cc;
-+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+		if (cc->uid > uid) {
-+			uid = cc->uid;
-+		}
-+	}
-+
-+	if (uid == 0) {
-+		uid = 255;
-+	}
-+
-+	return uid + 1;
-+}
-+
-+static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
-+{
-+	dwc_cc_t *cc;
-+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+		if (cc->uid == uid) {
-+			return cc;
-+		}
-+	}
-+	return NULL;
-+}
-+
-+static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
-+{
-+	unsigned int size = 0;
-+	dwc_cc_t *cc;
-+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+		size += (48 + 1);
-+		if (cc->name) {
-+			size += cc->length;
-+		}
-+	}
-+	return size;
-+}
-+
-+static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
-+{
-+	uint32_t uid = 0;
-+	dwc_cc_t *cc;
-+
-+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+		if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
-+			uid = cc->uid;
-+			break;
-+		}
-+	}
-+	return uid;
-+}
-+static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
-+{
-+	uint32_t uid = 0;
-+	dwc_cc_t *cc;
-+
-+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+		if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
-+			uid = cc->uid;
-+			break;
-+		}
-+	}
-+	return uid;
-+}
-+
-+/* Internal cc_add */
-+static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+		      uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+	dwc_cc_t *cc;
-+	uint32_t uid;
-+
-+	if (cc_if->is_host) {
-+		uid = cc_match_cdid(cc_if, cdid);
-+	}
-+	else {
-+		uid = cc_match_chid(cc_if, chid);
-+	}
-+
-+	if (uid) {
-+		DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
-+		cc = cc_find(cc_if, uid);
-+	}
-+	else {
-+		cc = alloc_cc(mem_ctx, name, length);
-+		cc->uid = next_uid(cc_if);
-+		DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
-+	}
-+
-+	DWC_MEMCPY(&(cc->chid[0]), chid, 16);
-+	DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
-+	DWC_MEMCPY(&(cc->ck[0]), ck, 16);
-+
-+	DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
-+	dump_bytes("CHID", cc->chid, 16);
-+	dump_bytes("CDID", cc->cdid, 16);
-+	dump_bytes("CK", cc->ck, 16);
-+	return cc->uid;
-+}
-+
-+/* Internal cc_clear */
-+static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
-+{
-+	while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
-+		dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
-+		DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
-+		free_cc(mem_ctx, cc);
-+	}
-+}
-+
-+dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
-+			     dwc_notifier_t *notifier, unsigned is_host)
-+{
-+	dwc_cc_if_t *cc_if = NULL;
-+
-+	/* Allocate a common_cc_if structure */
-+	cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));
-+
-+	if (!cc_if)
-+		return NULL;
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+	DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
-+#else
-+	cc_if->mutex = dwc_mutex_alloc(mtx_ctx);
-+#endif
-+	if (!cc_if->mutex) {
-+		dwc_free(mem_ctx, cc_if);
-+		return NULL;
-+	}
-+
-+	DWC_CIRCLEQ_INIT(&cc_if->list);
-+	cc_if->is_host = is_host;
-+	cc_if->notifier = notifier;
-+	return cc_if;
-+}
-+
-+void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)
-+{
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+	DWC_MUTEX_FREE(cc_if->mutex);
-+#else
-+	dwc_mutex_free(mtx_ctx, cc_if->mutex);
-+#endif
-+	cc_clear(mem_ctx, cc_if);
-+	dwc_free(mem_ctx, cc_if);
-+}
-+
-+static void cc_changed(dwc_cc_if_t *cc_if)
-+{
-+	if (cc_if->notifier) {
-+		dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
-+	}
-+}
-+
-+void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
-+{
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	cc_clear(mem_ctx, cc_if);
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+	cc_changed(cc_if);
-+}
-+
-+int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+		   uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+	uint32_t uid;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+	cc_changed(cc_if);
-+
-+	return uid;
-+}
-+
-+void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,
-+		   uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
-+{
-+	dwc_cc_t* cc;
-+
-+	DWC_DEBUGC("Change connection context %d", id);
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	cc = cc_find(cc_if, id);
-+	if (!cc) {
-+		DWC_ERROR("Uid %d not found in cc list\n", id);
-+		DWC_MUTEX_UNLOCK(cc_if->mutex);
-+		return;
-+	}
-+
-+	if (chid) {
-+		DWC_MEMCPY(&(cc->chid[0]), chid, 16);
-+	}
-+	if (cdid) {
-+		DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
-+	}
-+	if (ck) {
-+		DWC_MEMCPY(&(cc->ck[0]), ck, 16);
-+	}
-+
-+	if (name) {
-+		if (cc->name) {
-+			dwc_free(mem_ctx, cc->name);
-+		}
-+		cc->name = dwc_alloc(mem_ctx, length);
-+		if (!cc->name) {
-+			DWC_ERROR("Out of memory in dwc_cc_change()\n");
-+			DWC_MUTEX_UNLOCK(cc_if->mutex);
-+			return;
-+		}
-+		cc->length = length;
-+		DWC_MEMCPY(cc->name, name, length);
-+	}
-+
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+	cc_changed(cc_if);
-+
-+	DWC_DEBUGC("Changed connection context id=%d\n", id);
-+	dump_bytes("New CHID", cc->chid, 16);
-+	dump_bytes("New CDID", cc->cdid, 16);
-+	dump_bytes("New CK", cc->ck, 16);
-+}
-+
-+void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)
-+{
-+	dwc_cc_t *cc;
-+
-+	DWC_DEBUGC("Removing connection context %d", id);
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	cc = cc_find(cc_if, id);
-+	if (!cc) {
-+		DWC_ERROR("Uid %d not found in cc list\n", id);
-+		DWC_MUTEX_UNLOCK(cc_if->mutex);
-+		return;
-+	}
-+
-+	DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+	free_cc(mem_ctx, cc);
-+
-+	cc_changed(cc_if);
-+}
-+
-+uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)
-+{
-+	uint8_t *buf, *x;
-+	uint8_t zero = 0;
-+	dwc_cc_t *cc;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	*length = cc_data_size(cc_if);
-+	if (!(*length)) {
-+		DWC_MUTEX_UNLOCK(cc_if->mutex);
-+		return NULL;
-+	}
-+
-+	DWC_DEBUGC("Creating data for saving (length=%d)", *length);
-+
-+	buf = dwc_alloc(mem_ctx, *length);
-+	if (!buf) {
-+		*length = 0;
-+		DWC_MUTEX_UNLOCK(cc_if->mutex);
-+		return NULL;
-+	}
-+
-+	x = buf;
-+	DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
-+		DWC_MEMCPY(x, cc->chid, 16);
-+		x += 16;
-+		DWC_MEMCPY(x, cc->cdid, 16);
-+		x += 16;
-+		DWC_MEMCPY(x, cc->ck, 16);
-+		x += 16;
-+		if (cc->name) {
-+			DWC_MEMCPY(x, &cc->length, 1);
-+			x += 1;
-+			DWC_MEMCPY(x, cc->name, cc->length);
-+			x += cc->length;
-+		}
-+		else {
-+			DWC_MEMCPY(x, &zero, 1);
-+			x += 1;
-+		}
-+	}
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+	return buf;
-+}
-+
-+void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
-+{
-+	uint8_t name_length;
-+	uint8_t *name;
-+	uint8_t *chid;
-+	uint8_t *cdid;
-+	uint8_t *ck;
-+	uint32_t i = 0;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	cc_clear(mem_ctx, cc_if);
-+
-+	while (i < length) {
-+		chid = &data[i];
-+		i += 16;
-+		cdid = &data[i];
-+		i += 16;
-+		ck = &data[i];
-+		i += 16;
-+
-+		name_length = data[i];
-+		i ++;
-+
-+		if (name_length) {
-+			name = &data[i];
-+			i += name_length;
-+		}
-+		else {
-+			name = NULL;
-+		}
-+
-+		/* check to see if we haven't overflown the buffer */
-+		if (i > length) {
-+			DWC_ERROR("Data format error while attempting to load CCs "
-+				  "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length);
-+			break;
-+		}
-+
-+		cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);
-+	}
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+	cc_changed(cc_if);
-+}
-+
-+uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
-+{
-+	uint32_t uid = 0;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	uid = cc_match_chid(cc_if, chid);
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+	return uid;
-+}
-+uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
-+{
-+	uint32_t uid = 0;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	uid = cc_match_cdid(cc_if, cdid);
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+	return uid;
-+}
-+
-+uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+	uint8_t *ck = NULL;
-+	dwc_cc_t *cc;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	cc = cc_find(cc_if, id);
-+	if (cc) {
-+		ck = cc->ck;
-+	}
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+	return ck;
-+
-+}
-+
-+uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+	uint8_t *retval = NULL;
-+	dwc_cc_t *cc;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	cc = cc_find(cc_if, id);
-+	if (cc) {
-+		retval = cc->chid;
-+	}
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+	return retval;
-+}
-+
-+uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
-+{
-+	uint8_t *retval = NULL;
-+	dwc_cc_t *cc;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	cc = cc_find(cc_if, id);
-+	if (cc) {
-+		retval = cc->cdid;
-+	}
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+	return retval;
-+}
-+
-+uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
-+{
-+	uint8_t *retval = NULL;
-+	dwc_cc_t *cc;
-+
-+	DWC_MUTEX_LOCK(cc_if->mutex);
-+	*length = 0;
-+	cc = cc_find(cc_if, id);
-+	if (cc) {
-+		*length = cc->length;
-+		retval = cc->name;
-+	}
-+	DWC_MUTEX_UNLOCK(cc_if->mutex);
-+
-+	return retval;
-+}
-+
-+#endif	/* DWC_CCLIB */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_cc.h
-@@ -0,0 +1,224 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $
-+ * $Revision: #4 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_CC_H_
-+#define _DWC_CC_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file defines the Context Context library.
-+ *
-+ * The main data structure is dwc_cc_if_t which is returned by either the
-+ * dwc_cc_if_alloc function or returned by the module to the user via a provided
-+ * function. The data structure is opaque and should only be manipulated via the
-+ * functions provied in this API.
-+ *
-+ * It manages a list of connection contexts and operations can be performed to
-+ * add, remove, query, search, and change, those contexts.  Additionally,
-+ * a dwc_notifier_t object can be requested from the manager so that
-+ * the user can be notified whenever the context list has changed.
-+ */
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+#include "dwc_notifier.h"
-+
-+
-+/* Notifications */
-+#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
-+
-+struct dwc_cc_if;
-+typedef struct dwc_cc_if dwc_cc_if_t;
-+
-+
-+/** @name Connection Context Operations */
-+/** @{ */
-+
-+/** This function allocates memory for a dwc_cc_if_t structure, initializes
-+ * fields to default values, and returns a pointer to the structure or NULL on
-+ * error. */
-+extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
-+				    dwc_notifier_t *notifier, unsigned is_host);
-+
-+/** Frees the memory for the specified CC structure allocated from
-+ * dwc_cc_if_alloc(). */
-+extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);
-+
-+/** Removes all contexts from the connection context list */
-+extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
-+
-+/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
-+ * If a CHID already exists, the CK and name are overwritten.  Statistics are
-+ * not overwritten.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param chid A pointer to the 16-byte CHID.  This value will be copied.
-+ * @param ck A pointer to the 16-byte CK.  This value will be copied.
-+ * @param cdid A pointer to the 16-byte CDID.  This value will be copied.
-+ * @param name An optional host friendly name as defined in the association model
-+ * spec.  Must be a UTF16-LE unicode string.  Can be NULL to indicated no name.
-+ * @param length The length othe unicode string.
-+ * @return A unique identifier used to refer to this context that is valid for
-+ * as long as this context is still in the list. */
-+extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
-+			  uint8_t *cdid, uint8_t *ck, uint8_t *name,
-+			  uint8_t length);
-+
-+/** Changes the CHID, CK, CDID, or Name values of a connection context in the
-+ * list, preserving any accumulated statistics.  This would typically be called
-+ * if the host decideds to change the context with a SET_CONNECTION request.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @param chid A pointer to the 16-byte CHID.  This value will be copied.  NULL
-+ * indicates no change.
-+ * @param cdid A pointer to the 16-byte CDID.  This value will be copied.  NULL
-+ * indicates no change.
-+ * @param ck A pointer to the 16-byte CK.  This value will be copied.  NULL
-+ * indicates no change.
-+ * @param name Host friendly name UTF16-LE.  NULL indicates no change.
-+ * @param length Length of name. */
-+extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,
-+			  uint8_t *chid, uint8_t *cdid, uint8_t *ck,
-+			  uint8_t *name, uint8_t length);
-+
-+/** Remove the specified connection context.
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context to remove. */
-+extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Get a binary block of data for the connection context list and attributes.
-+ * This data can be used by the OS specific driver to save the connection
-+ * context list into non-volatile memory.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param length Return the length of the data buffer.
-+ * @return A pointer to the data buffer.  The memory for this buffer should be
-+ * freed with DWC_FREE() after use. */
-+extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,
-+				     unsigned int *length);
-+
-+/** Restore the connection context list from the binary data that was previously
-+ * returned from a call to dwc_cc_data_for_save.  This can be used by the OS specific
-+ * driver to load a connection context list from non-volatile memory.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param data The data bytes as returned from dwc_cc_data_for_save.
-+ * @param length The length of the data. */
-+extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,
-+				     uint8_t *data, unsigned int length);
-+
-+/** Find the connection context from the specified CHID.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param chid A pointer to the CHID data.
-+ * @return A non-zero identifier of the connection context if the CHID matches.
-+ * Otherwise returns 0. */
-+extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
-+
-+/** Find the connection context from the specified CDID.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param cdid A pointer to the CDID data.
-+ * @return A non-zero identifier of the connection context if the CHID matches.
-+ * Otherwise returns 0. */
-+extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
-+
-+/** Retrieve the CK from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CK data.  The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Retrieve the CHID from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CHID data.  The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
-+
-+/** Retrieve the CDID from the specified connection context.
-+ *
-+ * @param cc_if The cc_if structure.
-+ * @param id The identifier of the connection context.
-+ * @return A pointer to the CDID data.  The memory does not need to be freed. */
-+extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
-+
-+extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
-+
-+/** Checks a buffer for non-zero.
-+ * @param id A pointer to a 16 byte buffer.
-+ * @return true if the 16 byte value is non-zero. */
-+static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
-+	int i;
-+	for (i=0; i<16; i++) {
-+		if (id[i]) return 1;
-+	}
-+	return 0;
-+}
-+
-+/** Checks a buffer for zero.
-+ * @param id A pointer to a 16 byte buffer.
-+ * @return true if the 16 byte value is zero. */
-+static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
-+	return !dwc_assoc_is_not_zero_id(id);
-+}
-+
-+/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
-+ * buffer. */
-+static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
-+	char *ptr = buffer;
-+	int i;
-+	for (i=0; i<16; i++) {
-+		ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
-+		if (i < 15) {
-+			ptr += DWC_SPRINTF(ptr, " ");
-+		}
-+	}
-+	return ptr - buffer;
-+}
-+
-+/** @} */
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_CC_H_ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
-@@ -0,0 +1,1308 @@
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+	return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+	return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+	bcopy(src, dest, size);
-+	return dest;
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+	return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+	return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+	return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+	return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+	return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+	int len = DWC_STRLEN(str) + 1;
-+	char *new = DWC_ALLOC_ATOMIC(len);
-+
-+	if (!new) {
-+		return NULL;
-+	}
-+
-+	DWC_MEMCPY(new, str, len);
-+	return new;
-+}
-+
-+int DWC_ATOI(char *str, int32_t *value)
-+{
-+	char *end = NULL;
-+
-+	*value = strtol(str, &end, 0);
-+	if (*end == '\0') {
-+		return 0;
-+	}
-+
-+	return -1;
-+}
-+
-+int DWC_ATOUI(char *str, uint32_t *value)
-+{
-+	char *end = NULL;
-+
-+	*value = strtoul(str, &end, 0);
-+	if (*end == '\0') {
-+		return 0;
-+	}
-+
-+	return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+	int	count = 0;
-+	u8	c;
-+	u16	uchar;
-+
-+	/* this insists on correct encodings, though not minimal ones.
-+	 * BUT it currently rejects legit 4-byte UTF-8 code points,
-+	 * which need surrogate pairs.  (Unicode 3.1 can use them.)
-+	 */
-+	while (len != 0 && (c = (u8) *s++) != 0) {
-+		if (unlikely(c & 0x80)) {
-+			// 2-byte sequence:
-+			// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+			if ((c & 0xe0) == 0xc0) {
-+				uchar = (c & 0x1f) << 6;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c;
-+
-+			// 3-byte sequence (most CJKV characters):
-+			// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+			} else if ((c & 0xf0) == 0xe0) {
-+				uchar = (c & 0x0f) << 12;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c << 6;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c;
-+
-+				/* no bogus surrogates */
-+				if (0xd800 <= uchar && uchar <= 0xdfff)
-+					goto fail;
-+
-+			// 4-byte sequence (surrogate pairs, currently rare):
-+			// 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+			//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+			// (uuuuu = wwww + 1)
-+			// FIXME accept the surrogate code points (only)
-+			} else
-+				goto fail;
-+		} else
-+			uchar = c;
-+		put_unaligned (cpu_to_le16 (uchar), cp++);
-+		count++;
-+		len--;
-+	}
-+	return count;
-+fail:
-+	return -1;
-+}
-+
-+#endif	/* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+//	return in_irq();
-+	return 0;
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+//	return in_softirq();
-+	return 0;
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+	vprintf(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+	return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+	int retval;
-+	va_list args;
-+
-+	va_start(args, format);
-+	retval = vsprintf(buffer, format, args);
-+	va_end(args);
-+	return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+	int retval;
-+	va_list args;
-+
-+	va_start(args, format);
-+	retval = vsnprintf(buffer, size, format, args);
-+	va_end(args);
-+	return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+//	BUG_ON(1);	???
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+				uint32_t align,
-+				uint32_t alloc)
-+{
-+	struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+						size, align, alloc);
-+	return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+	dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+//	return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+	return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+	void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+	memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+	dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
-+{
-+	if (error)
-+		return;
-+	*(bus_addr_t *)arg = segs[0].ds_addr;
-+}
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+	dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+	int error;
-+
-+	error = bus_dma_tag_create(
-+#if __FreeBSD_version >= 700000
-+			bus_get_dma_tag(dma->dev),	/* parent */
-+#else
-+			NULL,				/* parent */
-+#endif
-+			4, 0,				/* alignment, bounds */
-+			BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
-+			BUS_SPACE_MAXADDR,		/* highaddr */
-+			NULL, NULL,			/* filter, filterarg */
-+			size,				/* maxsize */
-+			1,				/* nsegments */
-+			size,				/* maxsegsize */
-+			0,				/* flags */
-+			NULL,				/* lockfunc */
-+			NULL,				/* lockarg */
-+			&dma->dma_tag);
-+	if (error) {
-+		device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n",
-+			      __func__, error);
-+		goto fail_0;
-+	}
-+
-+	error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,
-+				 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
-+	if (error) {
-+		device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
-+			      __func__, (uintmax_t)size, error);
-+		goto fail_1;
-+	}
-+
-+	dma->dma_paddr = 0;
-+	error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,
-+				dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
-+	if (error || dma->dma_paddr == 0) {
-+		device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n",
-+			      __func__, error);
-+		goto fail_2;
-+	}
-+
-+	*dma_addr = dma->dma_paddr;
-+	return dma->dma_vaddr;
-+
-+fail_2:
-+	bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+fail_1:
-+	bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
-+	bus_dma_tag_destroy(dma->dma_tag);
-+fail_0:
-+	dma->dma_map = NULL;
-+	dma->dma_tag = NULL;
-+
-+	return NULL;
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+	dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+
-+	if (dma->dma_tag == NULL)
-+		return;
-+	if (dma->dma_map != NULL) {
-+		bus_dmamap_sync(dma->dma_tag, dma->dma_map,
-+				BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-+		bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+		bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
-+		dma->dma_map = NULL;
-+	}
-+
-+	bus_dma_tag_destroy(dma->dma_tag);
-+	dma->dma_tag = NULL;
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+	return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+	return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+	free(addr, M_DEVBUF);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+	get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+	struct crypto_blkcipher *tfm;
-+	struct blkcipher_desc desc;
-+	struct scatterlist sgd;
-+	struct scatterlist sgs;
-+
-+	tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+	if (tfm == NULL) {
-+		printk("failed to load transform for aes CBC\n");
-+		return -1;
-+	}
-+
-+	crypto_blkcipher_setkey(tfm, key, keylen);
-+	crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+	sg_init_one(&sgd, out, messagelen);
-+	sg_init_one(&sgs, message, messagelen);
-+
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+		crypto_free_blkcipher(tfm);
-+		DWC_ERROR("AES CBC encryption failed");
-+		return -1;
-+	}
-+
-+	crypto_free_blkcipher(tfm);
-+	return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+	struct crypto_hash *tfm;
-+	struct hash_desc desc;
-+	struct scatterlist sg;
-+
-+	tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+	if (IS_ERR(tfm)) {
-+		DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
-+		return 0;
-+	}
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	sg_init_one(&sg, message, len);
-+	crypto_hash_digest(&desc, &sg, len, out);
-+	crypto_free_hash(tfm);
-+
-+	return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+		    uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+	struct crypto_hash *tfm;
-+	struct hash_desc desc;
-+	struct scatterlist sg;
-+
-+	tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+	if (IS_ERR(tfm)) {
-+		DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
-+		return 0;
-+	}
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	sg_init_one(&sg, message, messagelen);
-+	crypto_hash_setkey(tfm, key, keylen);
-+	crypto_hash_digest(&desc, &sg, messagelen, out);
-+	crypto_free_hash(tfm);
-+
-+	return 1;
-+}
-+
-+#endif	/* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	return bus_space_read_4(io->iot, io->ioh, ior);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	return bus_space_read_8(io->iot, io->ioh, ior);
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	bus_space_write_4(io->iot, io->ioh, ior, value);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	bus_space_write_8(io->iot, io->ioh, ior, value);
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
-+		      uint32_t set_mask)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	bus_space_write_4(io->iot, io->ioh, ior,
-+			  (bus_space_read_4(io->iot, io->ioh, ior) &
-+			   ~clear_mask) | set_mask);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
-+		      uint64_t set_mask)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	bus_space_write_8(io->iot, io->ioh, ior,
-+			  (bus_space_read_8(io->iot, io->ioh, ior) &
-+			   ~clear_mask) | set_mask);
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+	struct mtx *sl = DWC_ALLOC(sizeof(*sl));
-+
-+	if (!sl) {
-+		DWC_ERROR("Cannot allocate memory for spinlock");
-+		return NULL;
-+	}
-+
-+	mtx_init(sl, "dw3spn", NULL, MTX_SPIN);
-+	return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+	struct mtx *sl = (struct mtx *)lock;
-+
-+	mtx_destroy(sl);
-+	DWC_FREE(sl);
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+	mtx_lock_spin((struct mtx *)lock);	// ???
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+	mtx_unlock_spin((struct mtx *)lock);	// ???
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+	mtx_lock_spin((struct mtx *)lock);
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+	mtx_unlock_spin((struct mtx *)lock);
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+	struct mtx *m;
-+	dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));
-+
-+	if (!mutex) {
-+		DWC_ERROR("Cannot allocate memory for mutex");
-+		return NULL;
-+	}
-+
-+	m = (struct mtx *)mutex;
-+	mtx_init(m, "dw3mtx", NULL, MTX_DEF);
-+	return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+	mtx_destroy((struct mtx *)mutex);
-+	DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+	struct mtx *m = (struct mtx *)mutex;
-+
-+	mtx_lock(m);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+	struct mtx *m = (struct mtx *)mutex;
-+
-+	return mtx_trylock(m);
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+	struct mtx *m = (struct mtx *)mutex;
-+
-+	mtx_unlock(m);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+	DELAY(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+	do {
-+		DELAY(1000);
-+	} while (--msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+	struct timeval tv;
-+
-+	tv.tv_sec = msecs / 1000;
-+	tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+	pause("dw3slp", tvtohz(&tv));
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+	struct timeval tv;
-+
-+	microuptime(&tv);	// or getmicrouptime? (less precise, but faster)
-+	return tv.tv_sec * 1000 + tv.tv_usec / 1000;
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+	struct callout t;
-+	char *name;
-+	dwc_spinlock_t *lock;
-+	dwc_timer_callback_t cb;
-+	void *data;
-+};
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+	dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+	if (!t) {
-+		DWC_ERROR("Cannot allocate memory for timer");
-+		return NULL;
-+	}
-+
-+	callout_init(&t->t, 1);
-+
-+	t->name = DWC_STRDUP(name);
-+	if (!t->name) {
-+		DWC_ERROR("Cannot allocate memory for timer->name");
-+		goto no_name;
-+	}
-+
-+	t->lock = DWC_SPINLOCK_ALLOC();
-+	if (!t->lock) {
-+		DWC_ERROR("Cannot allocate memory for lock");
-+		goto no_lock;
-+	}
-+
-+	t->cb = cb;
-+	t->data = data;
-+
-+	return t;
-+
-+ no_lock:
-+	DWC_FREE(t->name);
-+ no_name:
-+	DWC_FREE(t);
-+
-+	return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+	callout_stop(&timer->t);
-+	DWC_SPINLOCK_FREE(timer->lock);
-+	DWC_FREE(timer->name);
-+	DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+	struct timeval tv;
-+
-+	tv.tv_sec = time / 1000;
-+	tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+	callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+	callout_stop(&timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+	struct mtx lock;
-+	int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+	dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+	if (!wq) {
-+		DWC_ERROR("Cannot allocate memory for waitqueue");
-+		return NULL;
-+	}
-+
-+	mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF);
-+	wq->abort = 0;
-+
-+	return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+	mtx_destroy(&wq->lock);
-+	DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+//	intrmask_t ipl;
-+	int result = 0;
-+
-+	mtx_lock(&wq->lock);
-+//	ipl = splbio();
-+
-+	/* Skip the sleep if already aborted or triggered */
-+	if (!wq->abort && !cond(data)) {
-+//		splx(ipl);
-+		result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout
-+//		ipl = splbio();
-+	}
-+
-+	if (result == ERESTART) {	// signaled - restart
-+		result = -DWC_E_RESTART;
-+
-+	} else if (result == EINTR) {	// signaled - interrupt
-+		result = -DWC_E_ABORT;
-+
-+	} else if (wq->abort) {
-+		result = -DWC_E_ABORT;
-+
-+	} else {
-+		result = 0;
-+	}
-+
-+	wq->abort = 0;
-+//	splx(ipl);
-+	mtx_unlock(&wq->lock);
-+	return result;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+			       void *data, int32_t msecs)
-+{
-+	struct timeval tv, tv1, tv2;
-+//	intrmask_t ipl;
-+	int result = 0;
-+
-+	tv.tv_sec = msecs / 1000;
-+	tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+
-+	mtx_lock(&wq->lock);
-+//	ipl = splbio();
-+
-+	/* Skip the sleep if already aborted or triggered */
-+	if (!wq->abort && !cond(data)) {
-+//		splx(ipl);
-+		getmicrouptime(&tv1);
-+		result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv));
-+		getmicrouptime(&tv2);
-+//		ipl = splbio();
-+	}
-+
-+	if (result == 0) {			// awoken
-+		if (wq->abort) {
-+			result = -DWC_E_ABORT;
-+		} else {
-+			tv2.tv_usec -= tv1.tv_usec;
-+			if (tv2.tv_usec < 0) {
-+				tv2.tv_usec += 1000000;
-+				tv2.tv_sec--;
-+			}
-+
-+			tv2.tv_sec -= tv1.tv_sec;
-+			result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
-+			result = msecs - result;
-+			if (result <= 0)
-+				result = 1;
-+		}
-+	} else if (result == ERESTART) {	// signaled - restart
-+		result = -DWC_E_RESTART;
-+
-+	} else if (result == EINTR) {		// signaled - interrupt
-+		result = -DWC_E_ABORT;
-+
-+	} else {				// timed out
-+		result = -DWC_E_TIMEOUT;
-+	}
-+
-+	wq->abort = 0;
-+//	splx(ipl);
-+	mtx_unlock(&wq->lock);
-+	return result;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+	wakeup(wq);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+//	intrmask_t ipl;
-+
-+	mtx_lock(&wq->lock);
-+//	ipl = splbio();
-+	wq->abort = 1;
-+	wakeup(wq);
-+//	splx(ipl);
-+	mtx_unlock(&wq->lock);
-+}
-+
-+
-+/* Threading */
-+
-+struct dwc_thread {
-+	struct proc *proc;
-+	int abort;
-+};
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+	int retval;
-+	dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
-+
-+	if (!thread) {
-+		return NULL;
-+	}
-+
-+	thread->abort = 0;
-+	retval = kthread_create((void (*)(void *))func, data, &thread->proc,
-+				RFPROC | RFNOWAIT, 0, "%s", name);
-+	if (retval) {
-+		DWC_FREE(thread);
-+		return NULL;
-+	}
-+
-+	return thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+	int retval;
-+
-+	thread->abort = 1;
-+	retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
-+
-+	if (retval == 0) {
-+		/* DWC_THREAD_EXIT() will free the thread struct */
-+		return 0;
-+	}
-+
-+	/* NOTE: We leak the thread struct if thread doesn't die */
-+
-+	if (retval == EWOULDBLOCK) {
-+		return -DWC_E_TIMEOUT;
-+	}
-+
-+	return -DWC_E_UNKNOWN;
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
-+{
-+	return thread->abort;
-+}
-+
-+void DWC_THREAD_EXIT(dwc_thread_t *thread)
-+{
-+	wakeup(&thread->abort);
-+	DWC_FREE(thread);
-+	kthread_exit(0);
-+}
-+
-+
-+/* tasklets
-+ - Runs in interrupt context (cannot sleep)
-+ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]
-+ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]
-+ */
-+struct dwc_tasklet {
-+	struct task t;
-+	dwc_tasklet_callback_t cb;
-+	void *data;
-+};
-+
-+static void tasklet_callback(void *data, int pending)	// what to do with pending ???
-+{
-+	dwc_tasklet_t *task = (dwc_tasklet_t *)data;
-+
-+	task->cb(task->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+	dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
-+
-+	if (task) {
-+		task->cb = cb;
-+		task->data = data;
-+		TASK_INIT(&task->t, 0, tasklet_callback, task);
-+	} else {
-+		DWC_ERROR("Cannot allocate memory for tasklet");
-+	}
-+
-+	return task;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+	taskqueue_drain(taskqueue_fast, &task->t);	// ???
-+	DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+	/* Uses predefined system queue */
-+	taskqueue_enqueue_fast(taskqueue_fast, &task->t);
-+}
-+
-+
-+/* workqueues
-+ - Runs in process context (can sleep)
-+ */
-+typedef struct work_container {
-+	dwc_work_callback_t cb;
-+	void *data;
-+	dwc_workq_t *wq;
-+	char *name;
-+	int hz;
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_ENTRY(work_container) entry;
-+#endif
-+	struct task task;
-+} work_container_t;
-+
-+#ifdef DEBUG
-+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
-+#endif
-+
-+struct dwc_workq {
-+	struct taskqueue *taskq;
-+	dwc_spinlock_t *lock;
-+	dwc_waitq_t *waitq;
-+	int pending;
-+
-+#ifdef DEBUG
-+	struct work_container_queue entries;
-+#endif
-+};
-+
-+static void do_work(void *data, int pending)	// what to do with pending ???
-+{
-+	work_container_t *container = (work_container_t *)data;
-+	dwc_workq_t *wq = container->wq;
-+	dwc_irqflags_t flags;
-+
-+	if (container->hz) {
-+		pause("dw3wrk", container->hz);
-+	}
-+
-+	container->cb(container->data);
-+	DWC_DEBUG("Work done: %s, container=%p", container->name, container);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
-+#endif
-+	if (container->name)
-+		DWC_FREE(container->name);
-+	DWC_FREE(container);
-+	wq->pending--;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+	dwc_workq_t *workq = (dwc_workq_t *)data;
-+
-+	return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+	return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+	dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+	if (!wq) {
-+		DWC_ERROR("Cannot allocate memory for workqueue");
-+		return NULL;
-+	}
-+
-+	wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);
-+	if (!wq->taskq) {
-+		DWC_ERROR("Cannot allocate memory for taskqueue");
-+		goto no_taskq;
-+	}
-+
-+	wq->pending = 0;
-+
-+	wq->lock = DWC_SPINLOCK_ALLOC();
-+	if (!wq->lock) {
-+		DWC_ERROR("Cannot allocate memory for spinlock");
-+		goto no_lock;
-+	}
-+
-+	wq->waitq = DWC_WAITQ_ALLOC();
-+	if (!wq->waitq) {
-+		DWC_ERROR("Cannot allocate memory for waitqueue");
-+		goto no_waitq;
-+	}
-+
-+	taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk");
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_INIT(&wq->entries);
-+#endif
-+	return wq;
-+
-+ no_waitq:
-+	DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+	taskqueue_free(wq->taskq);
-+ no_taskq:
-+	DWC_FREE(wq);
-+
-+	return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+	dwc_irqflags_t flags;
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+	if (wq->pending != 0) {
-+		struct work_container *container;
-+
-+		DWC_ERROR("Destroying work queue with pending work");
-+
-+		DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {
-+			DWC_ERROR("Work %s still pending", container->name);
-+		}
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+#endif
-+	DWC_WAITQ_FREE(wq->waitq);
-+	DWC_SPINLOCK_FREE(wq->lock);
-+	taskqueue_free(wq->taskq);
-+	DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+			char *format, ...)
-+{
-+	dwc_irqflags_t flags;
-+	work_container_t *container;
-+	static char name[128];
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VSNPRINTF(name, 128, format, args);
-+	va_end(args);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+	wq->pending++;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+	container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+	if (!container) {
-+		DWC_ERROR("Cannot allocate memory for container");
-+		return;
-+	}
-+
-+	container->name = DWC_STRDUP(name);
-+	if (!container->name) {
-+		DWC_ERROR("Cannot allocate memory for container->name");
-+		DWC_FREE(container);
-+		return;
-+	}
-+
-+	container->cb = cb;
-+	container->data = data;
-+	container->wq = wq;
-+	container->hz = 0;
-+
-+	DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+
-+	TASK_INIT(&container->task, 0, do_work, container);
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+	taskqueue_enqueue_fast(wq->taskq, &container->task);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+				void *data, uint32_t time, char *format, ...)
-+{
-+	dwc_irqflags_t flags;
-+	work_container_t *container;
-+	static char name[128];
-+	struct timeval tv;
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VSNPRINTF(name, 128, format, args);
-+	va_end(args);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+	wq->pending++;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+	container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+	if (!container) {
-+		DWC_ERROR("Cannot allocate memory for container");
-+		return;
-+	}
-+
-+	container->name = DWC_STRDUP(name);
-+	if (!container->name) {
-+		DWC_ERROR("Cannot allocate memory for container->name");
-+		DWC_FREE(container);
-+		return;
-+	}
-+
-+	container->cb = cb;
-+	container->data = data;
-+	container->wq = wq;
-+
-+	tv.tv_sec = time / 1000;
-+	tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+	container->hz = tvtohz(&tv);
-+
-+	DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+
-+	TASK_INIT(&container->task, 0, do_work, container);
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+	taskqueue_enqueue_fast(wq->taskq, &container->task);
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+	return wq->pending;
-+}
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c
-@@ -0,0 +1,1418 @@
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/kthread.h>
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the Linux kernel implementation of the DWC platform library. */
-+#include <linux/moduleparam.h>
-+#include <linux/ctype.h>
-+#include <linux/crypto.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/cdev.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/jiffies.h>
-+#include <linux/list.h>
-+#include <linux/pci.h>
-+#include <linux/random.h>
-+#include <linux/scatterlist.h>
-+#include <linux/slab.h>
-+#include <linux/stat.h>
-+#include <linux/string.h>
-+#include <linux/timer.h>
-+#include <linux/usb.h>
-+
-+#include <linux/version.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
-+# include <linux/usb/gadget.h>
-+#else
-+# include <linux/usb_gadget.h>
-+#endif
-+
-+#include <asm/io.h>
-+#include <asm/page.h>
-+#include <asm/uaccess.h>
-+#include <asm/unaligned.h>
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+	return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+	return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+	return memmove(dest, src, size);
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+	return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+	return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+	return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+	return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+	return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+	int len = DWC_STRLEN(str) + 1;
-+	char *new = DWC_ALLOC_ATOMIC(len);
-+
-+	if (!new) {
-+		return NULL;
-+	}
-+
-+	DWC_MEMCPY(new, str, len);
-+	return new;
-+}
-+
-+int DWC_ATOI(const char *str, int32_t *value)
-+{
-+	char *end = NULL;
-+
-+	*value = simple_strtol(str, &end, 0);
-+	if (*end == '\0') {
-+		return 0;
-+	}
-+
-+	return -1;
-+}
-+
-+int DWC_ATOUI(const char *str, uint32_t *value)
-+{
-+	char *end = NULL;
-+
-+	*value = simple_strtoul(str, &end, 0);
-+	if (*end == '\0') {
-+		return 0;
-+	}
-+
-+	return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+	int	count = 0;
-+	u8	c;
-+	u16	uchar;
-+
-+	/* this insists on correct encodings, though not minimal ones.
-+	 * BUT it currently rejects legit 4-byte UTF-8 code points,
-+	 * which need surrogate pairs.  (Unicode 3.1 can use them.)
-+	 */
-+	while (len != 0 && (c = (u8) *s++) != 0) {
-+		if (unlikely(c & 0x80)) {
-+			// 2-byte sequence:
-+			// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+			if ((c & 0xe0) == 0xc0) {
-+				uchar = (c & 0x1f) << 6;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c;
-+
-+			// 3-byte sequence (most CJKV characters):
-+			// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+			} else if ((c & 0xf0) == 0xe0) {
-+				uchar = (c & 0x0f) << 12;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c << 6;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c;
-+
-+				/* no bogus surrogates */
-+				if (0xd800 <= uchar && uchar <= 0xdfff)
-+					goto fail;
-+
-+			// 4-byte sequence (surrogate pairs, currently rare):
-+			// 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+			//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+			// (uuuuu = wwww + 1)
-+			// FIXME accept the surrogate code points (only)
-+			} else
-+				goto fail;
-+		} else
-+			uchar = c;
-+		put_unaligned (cpu_to_le16 (uchar), cp++);
-+		count++;
-+		len--;
-+	}
-+	return count;
-+fail:
-+	return -1;
-+}
-+#endif	/* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+	return in_irq();
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+	return in_softirq();
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+	vprintk(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+	return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+	int retval;
-+	va_list args;
-+
-+	va_start(args, format);
-+	retval = vsprintf(buffer, format, args);
-+	va_end(args);
-+	return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+	int retval;
-+	va_list args;
-+
-+	va_start(args, format);
-+	retval = vsnprintf(buffer, size, format, args);
-+	va_end(args);
-+	return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_PRINTF(KERN_WARNING);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_PRINTF(KERN_ERR);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_PRINTF(KERN_ERR);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+	BUG_ON(1);
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_PRINTF(KERN_DEBUG);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+				uint32_t align,
-+				uint32_t alloc)
-+{
-+	struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+						size, align, alloc);
-+	return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+	dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+	return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+	void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+	memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+	dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+	return dma_zalloc_coherent(dma_ctx, size, dma_addr, GFP_KERNEL | GFP_DMA32);
-+}
-+
-+void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+	return dma_zalloc_coherent(dma_ctx, size, dma_addr, GFP_ATOMIC);
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+	dma_free_coherent(dma_ctx, size, virt_addr, dma_addr);
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+	return kzalloc(size, GFP_KERNEL);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+	return kzalloc(size, GFP_ATOMIC);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+	kfree(addr);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+	get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+	struct crypto_blkcipher *tfm;
-+	struct blkcipher_desc desc;
-+	struct scatterlist sgd;
-+	struct scatterlist sgs;
-+
-+	tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+	if (tfm == NULL) {
-+		printk("failed to load transform for aes CBC\n");
-+		return -1;
-+	}
-+
-+	crypto_blkcipher_setkey(tfm, key, keylen);
-+	crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+	sg_init_one(&sgd, out, messagelen);
-+	sg_init_one(&sgs, message, messagelen);
-+
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+		crypto_free_blkcipher(tfm);
-+		DWC_ERROR("AES CBC encryption failed");
-+		return -1;
-+	}
-+
-+	crypto_free_blkcipher(tfm);
-+	return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+	struct crypto_hash *tfm;
-+	struct hash_desc desc;
-+	struct scatterlist sg;
-+
-+	tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+	if (IS_ERR(tfm)) {
-+		DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
-+		return 0;
-+	}
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	sg_init_one(&sg, message, len);
-+	crypto_hash_digest(&desc, &sg, len, out);
-+	crypto_free_hash(tfm);
-+
-+	return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+		    uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+	struct crypto_hash *tfm;
-+	struct hash_desc desc;
-+	struct scatterlist sg;
-+
-+	tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+	if (IS_ERR(tfm)) {
-+		DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
-+		return 0;
-+	}
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	sg_init_one(&sg, message, messagelen);
-+	crypto_hash_setkey(tfm, key, keylen);
-+	crypto_hash_digest(&desc, &sg, messagelen, out);
-+	crypto_free_hash(tfm);
-+
-+	return 1;
-+}
-+#endif	/* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(uint32_t volatile *reg)
-+{
-+	return readl(reg);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(uint64_t volatile *reg)
-+{
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
-+{
-+	writel(value, reg);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
-+{
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
-+{
-+	writel((readl(reg) & ~clear_mask) | set_mask, reg);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)
-+{
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+	spinlock_t *sl = (spinlock_t *)1;
-+
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+	sl = DWC_ALLOC(sizeof(*sl));
-+	if (!sl) {
-+		DWC_ERROR("Cannot allocate memory for spinlock\n");
-+		return NULL;
-+	}
-+
-+	spin_lock_init(sl);
-+#endif
-+	return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+	DWC_FREE(lock);
-+#endif
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+	spin_lock((spinlock_t *)lock);
-+#endif
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+	spin_unlock((spinlock_t *)lock);
-+#endif
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+	dwc_irqflags_t f;
-+
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+	spin_lock_irqsave((spinlock_t *)lock, f);
-+#else
-+	local_irq_save(f);
-+#endif
-+	*flags = f;
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
-+	spin_unlock_irqrestore((spinlock_t *)lock, flags);
-+#else
-+	local_irq_restore(flags);
-+#endif
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+	struct mutex *m;
-+	dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));
-+
-+	if (!mutex) {
-+		DWC_ERROR("Cannot allocate memory for mutex\n");
-+		return NULL;
-+	}
-+
-+	m = (struct mutex *)mutex;
-+	mutex_init(m);
-+	return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+	mutex_destroy((struct mutex *)mutex);
-+	DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+	struct mutex *m = (struct mutex *)mutex;
-+	mutex_lock(m);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+	struct mutex *m = (struct mutex *)mutex;
-+	return mutex_trylock(m);
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+	struct mutex *m = (struct mutex *)mutex;
-+	mutex_unlock(m);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+	udelay(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+	mdelay(msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+	msleep(msecs);
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+	return jiffies_to_msecs(jiffies);
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+	struct timer_list *t;
-+	char *name;
-+	dwc_timer_callback_t cb;
-+	void *data;
-+	uint8_t scheduled;
-+	dwc_spinlock_t *lock;
-+};
-+
-+static void timer_callback(unsigned long data)
-+{
-+	dwc_timer_t *timer = (dwc_timer_t *)data;
-+	dwc_irqflags_t flags;
-+
-+	DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+	timer->scheduled = 0;
-+	DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+	DWC_DEBUGC("Timer %s callback", timer->name);
-+	timer->cb(timer->data);
-+}
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+	dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+	if (!t) {
-+		DWC_ERROR("Cannot allocate memory for timer");
-+		return NULL;
-+	}
-+
-+	t->t = DWC_ALLOC(sizeof(*t->t));
-+	if (!t->t) {
-+		DWC_ERROR("Cannot allocate memory for timer->t");
-+		goto no_timer;
-+	}
-+
-+	t->name = DWC_STRDUP(name);
-+	if (!t->name) {
-+		DWC_ERROR("Cannot allocate memory for timer->name");
-+		goto no_name;
-+	}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
-+	DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock);
-+#else
-+	t->lock = DWC_SPINLOCK_ALLOC();
-+#endif
-+	if (!t->lock) {
-+		DWC_ERROR("Cannot allocate memory for lock");
-+		goto no_lock;
-+	}
-+
-+	t->scheduled = 0;
-+	t->t->expires = jiffies;
-+	setup_timer(t->t, timer_callback, (unsigned long)t);
-+
-+	t->cb = cb;
-+	t->data = data;
-+
-+	return t;
-+
-+ no_lock:
-+	DWC_FREE(t->name);
-+ no_name:
-+	DWC_FREE(t->t);
-+ no_timer:
-+	DWC_FREE(t);
-+	return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+	dwc_irqflags_t flags;
-+
-+	DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+
-+	if (timer->scheduled) {
-+		del_timer(timer->t);
-+		timer->scheduled = 0;
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+	DWC_SPINLOCK_FREE(timer->lock);
-+	DWC_FREE(timer->t);
-+	DWC_FREE(timer->name);
-+	DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+	dwc_irqflags_t flags;
-+
-+	DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
-+
-+	if (!timer->scheduled) {
-+		timer->scheduled = 1;
-+		DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time);
-+		timer->t->expires = jiffies + msecs_to_jiffies(time);
-+		add_timer(timer->t);
-+	} else {
-+		DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time);
-+		mod_timer(timer->t, jiffies + msecs_to_jiffies(time));
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+	del_timer(timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+	wait_queue_head_t queue;
-+	int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+	dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+	if (!wq) {
-+		DWC_ERROR("Cannot allocate memory for waitqueue\n");
-+		return NULL;
-+	}
-+
-+	init_waitqueue_head(&wq->queue);
-+	wq->abort = 0;
-+	return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+	DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+	int result = wait_event_interruptible(wq->queue,
-+					      cond(data) || wq->abort);
-+	if (result == -ERESTARTSYS) {
-+		wq->abort = 0;
-+		return -DWC_E_RESTART;
-+	}
-+
-+	if (wq->abort == 1) {
-+		wq->abort = 0;
-+		return -DWC_E_ABORT;
-+	}
-+
-+	wq->abort = 0;
-+
-+	if (result == 0) {
-+		return 0;
-+	}
-+
-+	return -DWC_E_UNKNOWN;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+			       void *data, int32_t msecs)
-+{
-+	int32_t tmsecs;
-+	int result = wait_event_interruptible_timeout(wq->queue,
-+						      cond(data) || wq->abort,
-+						      msecs_to_jiffies(msecs));
-+	if (result == -ERESTARTSYS) {
-+		wq->abort = 0;
-+		return -DWC_E_RESTART;
-+	}
-+
-+	if (wq->abort == 1) {
-+		wq->abort = 0;
-+		return -DWC_E_ABORT;
-+	}
-+
-+	wq->abort = 0;
-+
-+	if (result > 0) {
-+		tmsecs = jiffies_to_msecs(result);
-+		if (!tmsecs) {
-+			return 1;
-+		}
-+
-+		return tmsecs;
-+	}
-+
-+	if (result == 0) {
-+		return -DWC_E_TIMEOUT;
-+	}
-+
-+	return -DWC_E_UNKNOWN;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+	wq->abort = 0;
-+	wake_up_interruptible(&wq->queue);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+	wq->abort = 1;
-+	wake_up_interruptible(&wq->queue);
-+}
-+
-+
-+/* Threading */
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+	struct task_struct *thread = kthread_run(func, data, name);
-+
-+	if (thread == ERR_PTR(-ENOMEM)) {
-+		return NULL;
-+	}
-+
-+	return (dwc_thread_t *)thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+	return kthread_stop((struct task_struct *)thread);
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(void)
-+{
-+	return kthread_should_stop();
-+}
-+
-+
-+/* tasklets
-+ - run in interrupt context (cannot sleep)
-+ - each tasklet runs on a single CPU
-+ - different tasklets can be running simultaneously on different CPUs
-+ */
-+struct dwc_tasklet {
-+	struct tasklet_struct t;
-+	dwc_tasklet_callback_t cb;
-+	void *data;
-+};
-+
-+static void tasklet_callback(unsigned long data)
-+{
-+	dwc_tasklet_t *t = (dwc_tasklet_t *)data;
-+	t->cb(t->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+	dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
-+
-+	if (t) {
-+		t->cb = cb;
-+		t->data = data;
-+		tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
-+	} else {
-+		DWC_ERROR("Cannot allocate memory for tasklet\n");
-+	}
-+
-+	return t;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+	DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+	tasklet_schedule(&task->t);
-+}
-+
-+void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task)
-+{
-+	tasklet_hi_schedule(&task->t);
-+}
-+
-+
-+/* workqueues
-+ - run in process context (can sleep)
-+ */
-+typedef struct work_container {
-+	dwc_work_callback_t cb;
-+	void *data;
-+	dwc_workq_t *wq;
-+	char *name;
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_ENTRY(work_container) entry;
-+#endif
-+	struct delayed_work work;
-+} work_container_t;
-+
-+#ifdef DEBUG
-+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
-+#endif
-+
-+struct dwc_workq {
-+	struct workqueue_struct *wq;
-+	dwc_spinlock_t *lock;
-+	dwc_waitq_t *waitq;
-+	int pending;
-+
-+#ifdef DEBUG
-+	struct work_container_queue entries;
-+#endif
-+};
-+
-+static void do_work(struct work_struct *work)
-+{
-+	dwc_irqflags_t flags;
-+	struct delayed_work *dw = container_of(work, struct delayed_work, work);
-+	work_container_t *container = container_of(dw, struct work_container, work);
-+	dwc_workq_t *wq = container->wq;
-+
-+	container->cb(container->data);
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
-+#endif
-+	DWC_DEBUGC("Work done: %s, container=%p", container->name, container);
-+	if (container->name) {
-+		DWC_FREE(container->name);
-+	}
-+	DWC_FREE(container);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+	wq->pending--;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+	dwc_workq_t *workq = (dwc_workq_t *)data;
-+	return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+	return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+	dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+	if (!wq) {
-+		return NULL;
-+	}
-+
-+	wq->wq = create_singlethread_workqueue(name);
-+	if (!wq->wq) {
-+		goto no_wq;
-+	}
-+
-+	wq->pending = 0;
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
-+	DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock);
-+#else
-+	wq->lock = DWC_SPINLOCK_ALLOC();
-+#endif
-+	if (!wq->lock) {
-+		goto no_lock;
-+	}
-+
-+	wq->waitq = DWC_WAITQ_ALLOC();
-+	if (!wq->waitq) {
-+		goto no_waitq;
-+	}
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_INIT(&wq->entries);
-+#endif
-+	return wq;
-+
-+ no_waitq:
-+	DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+	destroy_workqueue(wq->wq);
-+ no_wq:
-+	DWC_FREE(wq);
-+
-+	return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+	if (wq->pending != 0) {
-+		struct work_container *wc;
-+		DWC_ERROR("Destroying work queue with pending work");
-+		DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
-+			DWC_ERROR("Work %s still pending", wc->name);
-+		}
-+	}
-+#endif
-+	destroy_workqueue(wq->wq);
-+	DWC_SPINLOCK_FREE(wq->lock);
-+	DWC_WAITQ_FREE(wq->waitq);
-+	DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+			char *format, ...)
-+{
-+	dwc_irqflags_t flags;
-+	work_container_t *container;
-+	static char name[128];
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VSNPRINTF(name, 128, format, args);
-+	va_end(args);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+	wq->pending++;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+	container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+	if (!container) {
-+		DWC_ERROR("Cannot allocate memory for container\n");
-+		return;
-+	}
-+
-+	container->name = DWC_STRDUP(name);
-+	if (!container->name) {
-+		DWC_ERROR("Cannot allocate memory for container->name\n");
-+		DWC_FREE(container);
-+		return;
-+	}
-+
-+	container->cb = cb;
-+	container->data = data;
-+	container->wq = wq;
-+	DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
-+	INIT_WORK(&container->work.work, do_work);
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+	queue_work(wq->wq, &container->work.work);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+				void *data, uint32_t time, char *format, ...)
-+{
-+	dwc_irqflags_t flags;
-+	work_container_t *container;
-+	static char name[128];
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VSNPRINTF(name, 128, format, args);
-+	va_end(args);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+	wq->pending++;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+	container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+	if (!container) {
-+		DWC_ERROR("Cannot allocate memory for container\n");
-+		return;
-+	}
-+
-+	container->name = DWC_STRDUP(name);
-+	if (!container->name) {
-+		DWC_ERROR("Cannot allocate memory for container->name\n");
-+		DWC_FREE(container);
-+		return;
-+	}
-+
-+	container->cb = cb;
-+	container->data = data;
-+	container->wq = wq;
-+	DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
-+	INIT_DELAYED_WORK(&container->work, do_work);
-+
-+#ifdef DEBUG
-+	DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
-+#endif
-+	queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+	return wq->pending;
-+}
-+
-+
-+#ifdef DWC_LIBMODULE
-+
-+#ifdef DWC_CCLIB
-+/* CC */
-+EXPORT_SYMBOL(dwc_cc_if_alloc);
-+EXPORT_SYMBOL(dwc_cc_if_free);
-+EXPORT_SYMBOL(dwc_cc_clear);
-+EXPORT_SYMBOL(dwc_cc_add);
-+EXPORT_SYMBOL(dwc_cc_remove);
-+EXPORT_SYMBOL(dwc_cc_change);
-+EXPORT_SYMBOL(dwc_cc_data_for_save);
-+EXPORT_SYMBOL(dwc_cc_restore_from_data);
-+EXPORT_SYMBOL(dwc_cc_match_chid);
-+EXPORT_SYMBOL(dwc_cc_match_cdid);
-+EXPORT_SYMBOL(dwc_cc_ck);
-+EXPORT_SYMBOL(dwc_cc_chid);
-+EXPORT_SYMBOL(dwc_cc_cdid);
-+EXPORT_SYMBOL(dwc_cc_name);
-+#endif	/* DWC_CCLIB */
-+
-+#ifdef DWC_CRYPTOLIB
-+# ifndef CONFIG_MACH_IPMATE
-+/* Modpow */
-+EXPORT_SYMBOL(dwc_modpow);
-+
-+/* DH */
-+EXPORT_SYMBOL(dwc_dh_modpow);
-+EXPORT_SYMBOL(dwc_dh_derive_keys);
-+EXPORT_SYMBOL(dwc_dh_pk);
-+# endif	/* CONFIG_MACH_IPMATE */
-+
-+/* Crypto */
-+EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
-+EXPORT_SYMBOL(dwc_wusb_cmf);
-+EXPORT_SYMBOL(dwc_wusb_prf);
-+EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
-+EXPORT_SYMBOL(dwc_wusb_gen_nonce);
-+EXPORT_SYMBOL(dwc_wusb_gen_key);
-+EXPORT_SYMBOL(dwc_wusb_gen_mic);
-+#endif	/* DWC_CRYPTOLIB */
-+
-+/* Notification */
-+#ifdef DWC_NOTIFYLIB
-+EXPORT_SYMBOL(dwc_alloc_notification_manager);
-+EXPORT_SYMBOL(dwc_free_notification_manager);
-+EXPORT_SYMBOL(dwc_register_notifier);
-+EXPORT_SYMBOL(dwc_unregister_notifier);
-+EXPORT_SYMBOL(dwc_add_observer);
-+EXPORT_SYMBOL(dwc_remove_observer);
-+EXPORT_SYMBOL(dwc_notify);
-+#endif
-+
-+/* Memory Debugging Routines */
-+#ifdef DWC_DEBUG_MEMORY
-+EXPORT_SYMBOL(dwc_alloc_debug);
-+EXPORT_SYMBOL(dwc_alloc_atomic_debug);
-+EXPORT_SYMBOL(dwc_free_debug);
-+EXPORT_SYMBOL(dwc_dma_alloc_debug);
-+EXPORT_SYMBOL(dwc_dma_free_debug);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_MEMSET);
-+EXPORT_SYMBOL(DWC_MEMCPY);
-+EXPORT_SYMBOL(DWC_MEMMOVE);
-+EXPORT_SYMBOL(DWC_MEMCMP);
-+EXPORT_SYMBOL(DWC_STRNCMP);
-+EXPORT_SYMBOL(DWC_STRCMP);
-+EXPORT_SYMBOL(DWC_STRLEN);
-+EXPORT_SYMBOL(DWC_STRCPY);
-+EXPORT_SYMBOL(DWC_STRDUP);
-+EXPORT_SYMBOL(DWC_ATOI);
-+EXPORT_SYMBOL(DWC_ATOUI);
-+
-+#ifdef DWC_UTFLIB
-+EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
-+#endif	/* DWC_UTFLIB */
-+
-+EXPORT_SYMBOL(DWC_IN_IRQ);
-+EXPORT_SYMBOL(DWC_IN_BH);
-+EXPORT_SYMBOL(DWC_VPRINTF);
-+EXPORT_SYMBOL(DWC_VSNPRINTF);
-+EXPORT_SYMBOL(DWC_PRINTF);
-+EXPORT_SYMBOL(DWC_SPRINTF);
-+EXPORT_SYMBOL(DWC_SNPRINTF);
-+EXPORT_SYMBOL(__DWC_WARN);
-+EXPORT_SYMBOL(__DWC_ERROR);
-+EXPORT_SYMBOL(DWC_EXCEPTION);
-+
-+#ifdef DEBUG
-+EXPORT_SYMBOL(__DWC_DEBUG);
-+#endif
-+
-+EXPORT_SYMBOL(__DWC_DMA_ALLOC);
-+EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
-+EXPORT_SYMBOL(__DWC_DMA_FREE);
-+EXPORT_SYMBOL(__DWC_ALLOC);
-+EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
-+EXPORT_SYMBOL(__DWC_FREE);
-+
-+#ifdef DWC_CRYPTOLIB
-+EXPORT_SYMBOL(DWC_RANDOM_BYTES);
-+EXPORT_SYMBOL(DWC_AES_CBC);
-+EXPORT_SYMBOL(DWC_SHA256);
-+EXPORT_SYMBOL(DWC_HMAC_SHA256);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_CPU_TO_LE32);
-+EXPORT_SYMBOL(DWC_CPU_TO_BE32);
-+EXPORT_SYMBOL(DWC_LE32_TO_CPU);
-+EXPORT_SYMBOL(DWC_BE32_TO_CPU);
-+EXPORT_SYMBOL(DWC_CPU_TO_LE16);
-+EXPORT_SYMBOL(DWC_CPU_TO_BE16);
-+EXPORT_SYMBOL(DWC_LE16_TO_CPU);
-+EXPORT_SYMBOL(DWC_BE16_TO_CPU);
-+EXPORT_SYMBOL(DWC_READ_REG32);
-+EXPORT_SYMBOL(DWC_WRITE_REG32);
-+EXPORT_SYMBOL(DWC_MODIFY_REG32);
-+
-+#if 0
-+EXPORT_SYMBOL(DWC_READ_REG64);
-+EXPORT_SYMBOL(DWC_WRITE_REG64);
-+EXPORT_SYMBOL(DWC_MODIFY_REG64);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
-+EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
-+EXPORT_SYMBOL(DWC_SPINLOCK);
-+EXPORT_SYMBOL(DWC_SPINUNLOCK);
-+EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
-+EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
-+EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
-+
-+#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))
-+EXPORT_SYMBOL(DWC_MUTEX_FREE);
-+#endif
-+
-+EXPORT_SYMBOL(DWC_MUTEX_LOCK);
-+EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
-+EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
-+EXPORT_SYMBOL(DWC_UDELAY);
-+EXPORT_SYMBOL(DWC_MDELAY);
-+EXPORT_SYMBOL(DWC_MSLEEP);
-+EXPORT_SYMBOL(DWC_TIME);
-+EXPORT_SYMBOL(DWC_TIMER_ALLOC);
-+EXPORT_SYMBOL(DWC_TIMER_FREE);
-+EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
-+EXPORT_SYMBOL(DWC_TIMER_CANCEL);
-+EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
-+EXPORT_SYMBOL(DWC_WAITQ_FREE);
-+EXPORT_SYMBOL(DWC_WAITQ_WAIT);
-+EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
-+EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
-+EXPORT_SYMBOL(DWC_WAITQ_ABORT);
-+EXPORT_SYMBOL(DWC_THREAD_RUN);
-+EXPORT_SYMBOL(DWC_THREAD_STOP);
-+EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
-+EXPORT_SYMBOL(DWC_TASK_ALLOC);
-+EXPORT_SYMBOL(DWC_TASK_FREE);
-+EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
-+EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
-+EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
-+EXPORT_SYMBOL(DWC_WORKQ_FREE);
-+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
-+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
-+EXPORT_SYMBOL(DWC_WORKQ_PENDING);
-+
-+static int dwc_common_port_init_module(void)
-+{
-+	int result = 0;
-+
-+	printk(KERN_DEBUG "Module dwc_common_port init\n" );
-+
-+#ifdef DWC_DEBUG_MEMORY
-+	result = dwc_memory_debug_start(NULL);
-+	if (result) {
-+		printk(KERN_ERR
-+		       "dwc_memory_debug_start() failed with error %d\n",
-+		       result);
-+		return result;
-+	}
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+	result = dwc_alloc_notification_manager(NULL, NULL);
-+	if (result) {
-+		printk(KERN_ERR
-+		       "dwc_alloc_notification_manager() failed with error %d\n",
-+		       result);
-+		return result;
-+	}
-+#endif
-+	return result;
-+}
-+
-+static void dwc_common_port_exit_module(void)
-+{
-+	printk(KERN_DEBUG "Module dwc_common_port exit\n" );
-+
-+#ifdef DWC_NOTIFYLIB
-+	dwc_free_notification_manager();
-+#endif
-+
-+#ifdef DWC_DEBUG_MEMORY
-+	dwc_memory_debug_stop();
-+#endif
-+}
-+
-+module_init(dwc_common_port_init_module);
-+module_exit(dwc_common_port_exit_module);
-+
-+MODULE_DESCRIPTION("DWC Common Library - Portable version");
-+MODULE_AUTHOR("Synopsys Inc.");
-+MODULE_LICENSE ("GPL");
-+
-+#endif	/* DWC_LIBMODULE */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
-@@ -0,0 +1,1275 @@
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+#ifdef DWC_CCLIB
-+# include "dwc_cc.h"
-+#endif
-+
-+#ifdef DWC_CRYPTOLIB
-+# include "dwc_modpow.h"
-+# include "dwc_dh.h"
-+# include "dwc_crypto.h"
-+#endif
-+
-+#ifdef DWC_NOTIFYLIB
-+# include "dwc_notifier.h"
-+#endif
-+
-+/* OS-Level Implementations */
-+
-+/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */
-+
-+
-+/* MISC */
-+
-+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
-+{
-+	return memset(dest, byte, size);
-+}
-+
-+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
-+{
-+	return memcpy(dest, src, size);
-+}
-+
-+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
-+{
-+	bcopy(src, dest, size);
-+	return dest;
-+}
-+
-+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
-+{
-+	return memcmp(m1, m2, size);
-+}
-+
-+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
-+{
-+	return strncmp(s1, s2, size);
-+}
-+
-+int DWC_STRCMP(void *s1, void *s2)
-+{
-+	return strcmp(s1, s2);
-+}
-+
-+int DWC_STRLEN(char const *str)
-+{
-+	return strlen(str);
-+}
-+
-+char *DWC_STRCPY(char *to, char const *from)
-+{
-+	return strcpy(to, from);
-+}
-+
-+char *DWC_STRDUP(char const *str)
-+{
-+	int len = DWC_STRLEN(str) + 1;
-+	char *new = DWC_ALLOC_ATOMIC(len);
-+
-+	if (!new) {
-+		return NULL;
-+	}
-+
-+	DWC_MEMCPY(new, str, len);
-+	return new;
-+}
-+
-+int DWC_ATOI(char *str, int32_t *value)
-+{
-+	char *end = NULL;
-+
-+	/* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'
-+	 * should be equivalent on 2's complement machines
-+	 */
-+	*value = strtoul(str, &end, 0);
-+	if (*end == '\0') {
-+		return 0;
-+	}
-+
-+	return -1;
-+}
-+
-+int DWC_ATOUI(char *str, uint32_t *value)
-+{
-+	char *end = NULL;
-+
-+	*value = strtoul(str, &end, 0);
-+	if (*end == '\0') {
-+		return 0;
-+	}
-+
-+	return -1;
-+}
-+
-+
-+#ifdef DWC_UTFLIB
-+/* From usbstring.c */
-+
-+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
-+{
-+	int	count = 0;
-+	u8	c;
-+	u16	uchar;
-+
-+	/* this insists on correct encodings, though not minimal ones.
-+	 * BUT it currently rejects legit 4-byte UTF-8 code points,
-+	 * which need surrogate pairs.  (Unicode 3.1 can use them.)
-+	 */
-+	while (len != 0 && (c = (u8) *s++) != 0) {
-+		if (unlikely(c & 0x80)) {
-+			// 2-byte sequence:
-+			// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+			if ((c & 0xe0) == 0xc0) {
-+				uchar = (c & 0x1f) << 6;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c;
-+
-+			// 3-byte sequence (most CJKV characters):
-+			// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+			} else if ((c & 0xf0) == 0xe0) {
-+				uchar = (c & 0x0f) << 12;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c << 6;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c;
-+
-+				/* no bogus surrogates */
-+				if (0xd800 <= uchar && uchar <= 0xdfff)
-+					goto fail;
-+
-+			// 4-byte sequence (surrogate pairs, currently rare):
-+			// 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+			//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+			// (uuuuu = wwww + 1)
-+			// FIXME accept the surrogate code points (only)
-+			} else
-+				goto fail;
-+		} else
-+			uchar = c;
-+		put_unaligned (cpu_to_le16 (uchar), cp++);
-+		count++;
-+		len--;
-+	}
-+	return count;
-+fail:
-+	return -1;
-+}
-+
-+#endif	/* DWC_UTFLIB */
-+
-+
-+/* dwc_debug.h */
-+
-+dwc_bool_t DWC_IN_IRQ(void)
-+{
-+//	return in_irq();
-+	return 0;
-+}
-+
-+dwc_bool_t DWC_IN_BH(void)
-+{
-+//	return in_softirq();
-+	return 0;
-+}
-+
-+void DWC_VPRINTF(char *format, va_list args)
-+{
-+	vprintf(format, args);
-+}
-+
-+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
-+{
-+	return vsnprintf(str, size, format, args);
-+}
-+
-+void DWC_PRINTF(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+int DWC_SPRINTF(char *buffer, char *format, ...)
-+{
-+	int retval;
-+	va_list args;
-+
-+	va_start(args, format);
-+	retval = vsprintf(buffer, format, args);
-+	va_end(args);
-+	return retval;
-+}
-+
-+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
-+{
-+	int retval;
-+	va_list args;
-+
-+	va_start(args, format);
-+	retval = vsnprintf(buffer, size, format, args);
-+	va_end(args);
-+	return retval;
-+}
-+
-+void __DWC_WARN(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+void __DWC_ERROR(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+
-+void DWC_EXCEPTION(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+//	BUG_ON(1);	???
-+}
-+
-+#ifdef DEBUG
-+void __DWC_DEBUG(char *format, ...)
-+{
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VPRINTF(format, args);
-+	va_end(args);
-+}
-+#endif
-+
-+
-+/* dwc_mem.h */
-+
-+#if 0
-+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
-+				uint32_t align,
-+				uint32_t alloc)
-+{
-+	struct dma_pool *pool = dma_pool_create("Pool", NULL,
-+						size, align, alloc);
-+	return (dwc_pool_t *)pool;
-+}
-+
-+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
-+{
-+	dma_pool_destroy((struct dma_pool *)pool);
-+}
-+
-+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+//	return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
-+	return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
-+}
-+
-+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
-+{
-+	void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
-+	memset(..);
-+}
-+
-+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
-+{
-+	dma_pool_free(pool, vaddr, daddr);
-+}
-+#endif
-+
-+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
-+{
-+	dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+	int error;
-+
-+	error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,
-+				 sizeof(dma->segs) / sizeof(dma->segs[0]),
-+				 &dma->nsegs, BUS_DMA_NOWAIT);
-+	if (error) {
-+		printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__,
-+		       (uintmax_t)size, error);
-+		goto fail_0;
-+	}
-+
-+	error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,
-+			       (caddr_t *)&dma->dma_vaddr,
-+			       BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
-+	if (error) {
-+		printf("%s: bus_dmamem_map failed: %d\n", __func__, error);
-+		goto fail_1;
-+	}
-+
-+	error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,
-+				  BUS_DMA_NOWAIT, &dma->dma_map);
-+	if (error) {
-+		printf("%s: bus_dmamap_create failed: %d\n", __func__, error);
-+		goto fail_2;
-+	}
-+
-+	error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
-+				size, NULL, BUS_DMA_NOWAIT);
-+	if (error) {
-+		printf("%s: bus_dmamap_load failed: %d\n", __func__, error);
-+		goto fail_3;
-+	}
-+
-+	dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;
-+	*dma_addr = dma->dma_paddr;
-+	return dma->dma_vaddr;
-+
-+fail_3:
-+	bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
-+fail_2:
-+	bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
-+fail_1:
-+	bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
-+fail_0:
-+	dma->dma_map = NULL;
-+	dma->dma_vaddr = NULL;
-+	dma->nsegs = 0;
-+
-+	return NULL;
-+}
-+
-+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
-+{
-+	dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
-+
-+	if (dma->dma_map != NULL) {
-+		bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,
-+				BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-+		bus_dmamap_unload(dma->dma_tag, dma->dma_map);
-+		bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
-+		bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
-+		bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
-+		dma->dma_paddr = 0;
-+		dma->dma_map = NULL;
-+		dma->dma_vaddr = NULL;
-+		dma->nsegs = 0;
-+	}
-+}
-+
-+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
-+{
-+	return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
-+}
-+
-+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
-+{
-+	return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
-+}
-+
-+void __DWC_FREE(void *mem_ctx, void *addr)
-+{
-+	free(addr, M_DEVBUF);
-+}
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/* dwc_crypto.h */
-+
-+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
-+{
-+	get_random_bytes(buffer, length);
-+}
-+
-+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
-+{
-+	struct crypto_blkcipher *tfm;
-+	struct blkcipher_desc desc;
-+	struct scatterlist sgd;
-+	struct scatterlist sgs;
-+
-+	tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
-+	if (tfm == NULL) {
-+		printk("failed to load transform for aes CBC\n");
-+		return -1;
-+	}
-+
-+	crypto_blkcipher_setkey(tfm, key, keylen);
-+	crypto_blkcipher_set_iv(tfm, iv, 16);
-+
-+	sg_init_one(&sgd, out, messagelen);
-+	sg_init_one(&sgs, message, messagelen);
-+
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
-+		crypto_free_blkcipher(tfm);
-+		DWC_ERROR("AES CBC encryption failed");
-+		return -1;
-+	}
-+
-+	crypto_free_blkcipher(tfm);
-+	return 0;
-+}
-+
-+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
-+{
-+	struct crypto_hash *tfm;
-+	struct hash_desc desc;
-+	struct scatterlist sg;
-+
-+	tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
-+	if (IS_ERR(tfm)) {
-+		DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
-+		return 0;
-+	}
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	sg_init_one(&sg, message, len);
-+	crypto_hash_digest(&desc, &sg, len, out);
-+	crypto_free_hash(tfm);
-+
-+	return 1;
-+}
-+
-+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
-+		    uint8_t *key, uint32_t keylen, uint8_t *out)
-+{
-+	struct crypto_hash *tfm;
-+	struct hash_desc desc;
-+	struct scatterlist sg;
-+
-+	tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
-+	if (IS_ERR(tfm)) {
-+		DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
-+		return 0;
-+	}
-+	desc.tfm = tfm;
-+	desc.flags = 0;
-+
-+	sg_init_one(&sg, message, messagelen);
-+	crypto_hash_setkey(tfm, key, keylen);
-+	crypto_hash_digest(&desc, &sg, messagelen, out);
-+	crypto_free_hash(tfm);
-+
-+	return 1;
-+}
-+
-+#endif	/* DWC_CRYPTOLIB */
-+
-+
-+/* Byte Ordering Conversions */
-+
-+uint32_t DWC_CPU_TO_LE32(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_CPU_TO_BE32(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_LE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint32_t DWC_BE32_TO_CPU(uint32_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+
-+	return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_LE16(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_CPU_TO_BE16(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_LE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __LITTLE_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+uint16_t DWC_BE16_TO_CPU(uint16_t *p)
-+{
-+#ifdef __BIG_ENDIAN
-+	return *p;
-+#else
-+	uint8_t *u_p = (uint8_t *)p;
-+	return (u_p[1] | (u_p[0] << 8));
-+#endif
-+}
-+
-+
-+/* Registers */
-+
-+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	return bus_space_read_4(io->iot, io->ioh, ior);
-+}
-+
-+#if 0
-+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	return bus_space_read_8(io->iot, io->ioh, ior);
-+}
-+#endif
-+
-+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	bus_space_write_4(io->iot, io->ioh, ior, value);
-+}
-+
-+#if 0
-+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	bus_space_write_8(io->iot, io->ioh, ior, value);
-+}
-+#endif
-+
-+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
-+		      uint32_t set_mask)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	bus_space_write_4(io->iot, io->ioh, ior,
-+			  (bus_space_read_4(io->iot, io->ioh, ior) &
-+			   ~clear_mask) | set_mask);
-+}
-+
-+#if 0
-+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
-+		      uint64_t set_mask)
-+{
-+	dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
-+	bus_size_t ior = (bus_size_t)reg;
-+
-+	bus_space_write_8(io->iot, io->ioh, ior,
-+			  (bus_space_read_8(io->iot, io->ioh, ior) &
-+			   ~clear_mask) | set_mask);
-+}
-+#endif
-+
-+
-+/* Locking */
-+
-+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
-+{
-+	struct simplelock *sl = DWC_ALLOC(sizeof(*sl));
-+
-+	if (!sl) {
-+		DWC_ERROR("Cannot allocate memory for spinlock");
-+		return NULL;
-+	}
-+
-+	simple_lock_init(sl);
-+	return (dwc_spinlock_t *)sl;
-+}
-+
-+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
-+{
-+	struct simplelock *sl = (struct simplelock *)lock;
-+
-+	DWC_FREE(sl);
-+}
-+
-+void DWC_SPINLOCK(dwc_spinlock_t *lock)
-+{
-+	simple_lock((struct simplelock *)lock);
-+}
-+
-+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
-+{
-+	simple_unlock((struct simplelock *)lock);
-+}
-+
-+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
-+{
-+	simple_lock((struct simplelock *)lock);
-+	*flags = splbio();
-+}
-+
-+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
-+{
-+	splx(flags);
-+	simple_unlock((struct simplelock *)lock);
-+}
-+
-+dwc_mutex_t *DWC_MUTEX_ALLOC(void)
-+{
-+	dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));
-+
-+	if (!mutex) {
-+		DWC_ERROR("Cannot allocate memory for mutex");
-+		return NULL;
-+	}
-+
-+	lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0);
-+	return mutex;
-+}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
-+#else
-+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
-+{
-+	DWC_FREE(mutex);
-+}
-+#endif
-+
-+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
-+{
-+	lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);
-+}
-+
-+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
-+{
-+	int status;
-+
-+	status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);
-+	return status == 0;
-+}
-+
-+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
-+{
-+	lockmgr((struct lock *)mutex, LK_RELEASE, NULL);
-+}
-+
-+
-+/* Timing */
-+
-+void DWC_UDELAY(uint32_t usecs)
-+{
-+	DELAY(usecs);
-+}
-+
-+void DWC_MDELAY(uint32_t msecs)
-+{
-+	do {
-+		DELAY(1000);
-+	} while (--msecs);
-+}
-+
-+void DWC_MSLEEP(uint32_t msecs)
-+{
-+	struct timeval tv;
-+
-+	tv.tv_sec = msecs / 1000;
-+	tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+	tsleep(&tv, 0, "dw3slp", tvtohz(&tv));
-+}
-+
-+uint32_t DWC_TIME(void)
-+{
-+	struct timeval tv;
-+
-+	microuptime(&tv);	// or getmicrouptime? (less precise, but faster)
-+	return tv.tv_sec * 1000 + tv.tv_usec / 1000;
-+}
-+
-+
-+/* Timers */
-+
-+struct dwc_timer {
-+	struct callout t;
-+	char *name;
-+	dwc_spinlock_t *lock;
-+	dwc_timer_callback_t cb;
-+	void *data;
-+};
-+
-+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
-+{
-+	dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
-+
-+	if (!t) {
-+		DWC_ERROR("Cannot allocate memory for timer");
-+		return NULL;
-+	}
-+
-+	callout_init(&t->t);
-+
-+	t->name = DWC_STRDUP(name);
-+	if (!t->name) {
-+		DWC_ERROR("Cannot allocate memory for timer->name");
-+		goto no_name;
-+	}
-+
-+	t->lock = DWC_SPINLOCK_ALLOC();
-+	if (!t->lock) {
-+		DWC_ERROR("Cannot allocate memory for timer->lock");
-+		goto no_lock;
-+	}
-+
-+	t->cb = cb;
-+	t->data = data;
-+
-+	return t;
-+
-+ no_lock:
-+	DWC_FREE(t->name);
-+ no_name:
-+	DWC_FREE(t);
-+
-+	return NULL;
-+}
-+
-+void DWC_TIMER_FREE(dwc_timer_t *timer)
-+{
-+	callout_stop(&timer->t);
-+	DWC_SPINLOCK_FREE(timer->lock);
-+	DWC_FREE(timer->name);
-+	DWC_FREE(timer);
-+}
-+
-+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
-+{
-+	struct timeval tv;
-+
-+	tv.tv_sec = time / 1000;
-+	tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+	callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
-+}
-+
-+void DWC_TIMER_CANCEL(dwc_timer_t *timer)
-+{
-+	callout_stop(&timer->t);
-+}
-+
-+
-+/* Wait Queues */
-+
-+struct dwc_waitq {
-+	struct simplelock lock;
-+	int abort;
-+};
-+
-+dwc_waitq_t *DWC_WAITQ_ALLOC(void)
-+{
-+	dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+	if (!wq) {
-+		DWC_ERROR("Cannot allocate memory for waitqueue");
-+		return NULL;
-+	}
-+
-+	simple_lock_init(&wq->lock);
-+	wq->abort = 0;
-+
-+	return wq;
-+}
-+
-+void DWC_WAITQ_FREE(dwc_waitq_t *wq)
-+{
-+	DWC_FREE(wq);
-+}
-+
-+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
-+{
-+	int ipl;
-+	int result = 0;
-+
-+	simple_lock(&wq->lock);
-+	ipl = splbio();
-+
-+	/* Skip the sleep if already aborted or triggered */
-+	if (!wq->abort && !cond(data)) {
-+		splx(ipl);
-+		result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout
-+		ipl = splbio();
-+	}
-+
-+	if (result == 0) {			// awoken
-+		if (wq->abort) {
-+			wq->abort = 0;
-+			result = -DWC_E_ABORT;
-+		} else {
-+			result = 0;
-+		}
-+
-+		splx(ipl);
-+		simple_unlock(&wq->lock);
-+	} else {
-+		wq->abort = 0;
-+		splx(ipl);
-+		simple_unlock(&wq->lock);
-+
-+		if (result == ERESTART) {	// signaled - restart
-+			result = -DWC_E_RESTART;
-+		} else {			// signaled - must be EINTR
-+			result = -DWC_E_ABORT;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+			       void *data, int32_t msecs)
-+{
-+	struct timeval tv, tv1, tv2;
-+	int ipl;
-+	int result = 0;
-+
-+	tv.tv_sec = msecs / 1000;
-+	tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
-+
-+	simple_lock(&wq->lock);
-+	ipl = splbio();
-+
-+	/* Skip the sleep if already aborted or triggered */
-+	if (!wq->abort && !cond(data)) {
-+		splx(ipl);
-+		getmicrouptime(&tv1);
-+		result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock);
-+		getmicrouptime(&tv2);
-+		ipl = splbio();
-+	}
-+
-+	if (result == 0) {			// awoken
-+		if (wq->abort) {
-+			wq->abort = 0;
-+			splx(ipl);
-+			simple_unlock(&wq->lock);
-+			result = -DWC_E_ABORT;
-+		} else {
-+			splx(ipl);
-+			simple_unlock(&wq->lock);
-+
-+			tv2.tv_usec -= tv1.tv_usec;
-+			if (tv2.tv_usec < 0) {
-+				tv2.tv_usec += 1000000;
-+				tv2.tv_sec--;
-+			}
-+
-+			tv2.tv_sec -= tv1.tv_sec;
-+			result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
-+			result = msecs - result;
-+			if (result <= 0)
-+				result = 1;
-+		}
-+	} else {
-+		wq->abort = 0;
-+		splx(ipl);
-+		simple_unlock(&wq->lock);
-+
-+		if (result == ERESTART) {	// signaled - restart
-+			result = -DWC_E_RESTART;
-+
-+		} else if (result == EINTR) {		// signaled - interrupt
-+			result = -DWC_E_ABORT;
-+
-+		} else {				// timed out
-+			result = -DWC_E_TIMEOUT;
-+		}
-+	}
-+
-+	return result;
-+}
-+
-+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
-+{
-+	wakeup(wq);
-+}
-+
-+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
-+{
-+	int ipl;
-+
-+	simple_lock(&wq->lock);
-+	ipl = splbio();
-+	wq->abort = 1;
-+	wakeup(wq);
-+	splx(ipl);
-+	simple_unlock(&wq->lock);
-+}
-+
-+
-+/* Threading */
-+
-+struct dwc_thread {
-+	struct proc *proc;
-+	int abort;
-+};
-+
-+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
-+{
-+	int retval;
-+	dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
-+
-+	if (!thread) {
-+		return NULL;
-+	}
-+
-+	thread->abort = 0;
-+	retval = kthread_create1((void (*)(void *))func, data, &thread->proc,
-+				 "%s", name);
-+	if (retval) {
-+		DWC_FREE(thread);
-+		return NULL;
-+	}
-+
-+	return thread;
-+}
-+
-+int DWC_THREAD_STOP(dwc_thread_t *thread)
-+{
-+	int retval;
-+
-+	thread->abort = 1;
-+	retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
-+
-+	if (retval == 0) {
-+		/* DWC_THREAD_EXIT() will free the thread struct */
-+		return 0;
-+	}
-+
-+	/* NOTE: We leak the thread struct if thread doesn't die */
-+
-+	if (retval == EWOULDBLOCK) {
-+		return -DWC_E_TIMEOUT;
-+	}
-+
-+	return -DWC_E_UNKNOWN;
-+}
-+
-+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
-+{
-+	return thread->abort;
-+}
-+
-+void DWC_THREAD_EXIT(dwc_thread_t *thread)
-+{
-+	wakeup(&thread->abort);
-+	DWC_FREE(thread);
-+	kthread_exit(0);
-+}
-+
-+/* tasklets
-+ - Runs in interrupt context (cannot sleep)
-+ - Each tasklet runs on a single CPU
-+ - Different tasklets can be running simultaneously on different CPUs
-+ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-
-+   halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]
-+ */
-+struct dwc_tasklet {
-+	dwc_tasklet_callback_t cb;
-+	void *data;
-+};
-+
-+static void tasklet_callback(void *data)
-+{
-+	dwc_tasklet_t *task = (dwc_tasklet_t *)data;
-+
-+	task->cb(task->data);
-+}
-+
-+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
-+{
-+	dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
-+
-+	if (task) {
-+		task->cb = cb;
-+		task->data = data;
-+	} else {
-+		DWC_ERROR("Cannot allocate memory for tasklet");
-+	}
-+
-+	return task;
-+}
-+
-+void DWC_TASK_FREE(dwc_tasklet_t *task)
-+{
-+	DWC_FREE(task);
-+}
-+
-+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
-+{
-+	tasklet_callback(task);
-+}
-+
-+
-+/* workqueues
-+ - Runs in process context (can sleep)
-+ */
-+typedef struct work_container {
-+	dwc_work_callback_t cb;
-+	void *data;
-+	dwc_workq_t *wq;
-+	char *name;
-+	int hz;
-+	struct work task;
-+} work_container_t;
-+
-+struct dwc_workq {
-+	struct workqueue *taskq;
-+	dwc_spinlock_t *lock;
-+	dwc_waitq_t *waitq;
-+	int pending;
-+	struct work_container *container;
-+};
-+
-+static void do_work(struct work *task, void *data)
-+{
-+	dwc_workq_t *wq = (dwc_workq_t *)data;
-+	work_container_t *container = wq->container;
-+	dwc_irqflags_t flags;
-+
-+	if (container->hz) {
-+		tsleep(container, 0, "dw3wrk", container->hz);
-+	}
-+
-+	container->cb(container->data);
-+	DWC_DEBUG("Work done: %s, container=%p", container->name, container);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+	if (container->name)
-+		DWC_FREE(container->name);
-+	DWC_FREE(container);
-+	wq->pending--;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+}
-+
-+static int work_done(void *data)
-+{
-+	dwc_workq_t *workq = (dwc_workq_t *)data;
-+
-+	return workq->pending == 0;
-+}
-+
-+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
-+{
-+	return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
-+}
-+
-+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
-+{
-+	int result;
-+	dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
-+
-+	if (!wq) {
-+		DWC_ERROR("Cannot allocate memory for workqueue");
-+		return NULL;
-+	}
-+
-+	result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,
-+				  IPL_BIO, 0);
-+	if (result) {
-+		DWC_ERROR("Cannot create workqueue");
-+		goto no_taskq;
-+	}
-+
-+	wq->pending = 0;
-+
-+	wq->lock = DWC_SPINLOCK_ALLOC();
-+	if (!wq->lock) {
-+		DWC_ERROR("Cannot allocate memory for spinlock");
-+		goto no_lock;
-+	}
-+
-+	wq->waitq = DWC_WAITQ_ALLOC();
-+	if (!wq->waitq) {
-+		DWC_ERROR("Cannot allocate memory for waitqueue");
-+		goto no_waitq;
-+	}
-+
-+	return wq;
-+
-+ no_waitq:
-+	DWC_SPINLOCK_FREE(wq->lock);
-+ no_lock:
-+	workqueue_destroy(wq->taskq);
-+ no_taskq:
-+	DWC_FREE(wq);
-+
-+	return NULL;
-+}
-+
-+void DWC_WORKQ_FREE(dwc_workq_t *wq)
-+{
-+#ifdef DEBUG
-+	dwc_irqflags_t flags;
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+
-+	if (wq->pending != 0) {
-+		struct work_container *container = wq->container;
-+
-+		DWC_ERROR("Destroying work queue with pending work");
-+
-+		if (container && container->name) {
-+			DWC_ERROR("Work %s still pending", container->name);
-+		}
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+#endif
-+	DWC_WAITQ_FREE(wq->waitq);
-+	DWC_SPINLOCK_FREE(wq->lock);
-+	workqueue_destroy(wq->taskq);
-+	DWC_FREE(wq);
-+}
-+
-+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
-+			char *format, ...)
-+{
-+	dwc_irqflags_t flags;
-+	work_container_t *container;
-+	static char name[128];
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VSNPRINTF(name, 128, format, args);
-+	va_end(args);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+	wq->pending++;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+	container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+	if (!container) {
-+		DWC_ERROR("Cannot allocate memory for container");
-+		return;
-+	}
-+
-+	container->name = DWC_STRDUP(name);
-+	if (!container->name) {
-+		DWC_ERROR("Cannot allocate memory for container->name");
-+		DWC_FREE(container);
-+		return;
-+	}
-+
-+	container->cb = cb;
-+	container->data = data;
-+	container->wq = wq;
-+	container->hz = 0;
-+	wq->container = container;
-+
-+	DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+	workqueue_enqueue(wq->taskq, &container->task);
-+}
-+
-+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
-+				void *data, uint32_t time, char *format, ...)
-+{
-+	dwc_irqflags_t flags;
-+	work_container_t *container;
-+	static char name[128];
-+	struct timeval tv;
-+	va_list args;
-+
-+	va_start(args, format);
-+	DWC_VSNPRINTF(name, 128, format, args);
-+	va_end(args);
-+
-+	DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
-+	wq->pending++;
-+	DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
-+	DWC_WAITQ_TRIGGER(wq->waitq);
-+
-+	container = DWC_ALLOC_ATOMIC(sizeof(*container));
-+	if (!container) {
-+		DWC_ERROR("Cannot allocate memory for container");
-+		return;
-+	}
-+
-+	container->name = DWC_STRDUP(name);
-+	if (!container->name) {
-+		DWC_ERROR("Cannot allocate memory for container->name");
-+		DWC_FREE(container);
-+		return;
-+	}
-+
-+	container->cb = cb;
-+	container->data = data;
-+	container->wq = wq;
-+	tv.tv_sec = time / 1000;
-+	tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
-+	container->hz = tvtohz(&tv);
-+	wq->container = container;
-+
-+	DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
-+	workqueue_enqueue(wq->taskq, &container->task);
-+}
-+
-+int DWC_WORKQ_PENDING(dwc_workq_t *wq)
-+{
-+	return wq->pending;
-+}
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_crypto.c
-@@ -0,0 +1,308 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $
-+ * $Revision: #5 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+
-+/** @file
-+ * This file contains the WUSB cryptographic routines.
-+ */
-+
-+#ifdef DWC_CRYPTOLIB
-+
-+#include "dwc_crypto.h"
-+#include "usb.h"
-+
-+#ifdef DEBUG
-+static inline void dump_bytes(char *name, uint8_t *bytes, int len)
-+{
-+	int i;
-+	DWC_PRINTF("%s: ", name);
-+	for (i=0; i<len; i++) {
-+		DWC_PRINTF("%02x ", bytes[i]);
-+	}
-+	DWC_PRINTF("\n");
-+}
-+#else
-+#define dump_bytes(x...)
-+#endif
-+
-+/* Display a block */
-+void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
-+{
-+#ifdef DWC_DEBUG_CRYPTO
-+	int i, blksize = 16;
-+
-+	DWC_DEBUG("%s", prefix);
-+
-+	if (suffix == NULL) {
-+		suffix = "\n";
-+		blksize = a;
-+	}
-+
-+	for (i = 0; i < blksize; i++)
-+		DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? "  " : " ");
-+	DWC_PRINT(suffix);
-+#endif
-+}
-+
-+/**
-+ * Encrypts an array of bytes using the AES encryption engine.
-+ * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
-+ * in-place.
-+ *
-+ * @return  0 on success, negative error code on error.
-+ */
-+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
-+{
-+	u8 block_t[16];
-+	DWC_MEMSET(block_t, 0, 16);
-+
-+	return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
-+}
-+
-+/**
-+ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
-+ * This function takes a data string and returns the encrypted CBC
-+ * Counter-mode MIC.
-+ *
-+ * @param key     The 128-bit symmetric key.
-+ * @param nonce   The CCM nonce.
-+ * @param label   The unique 14-byte ASCII text label.
-+ * @param bytes   The byte array to be encrypted.
-+ * @param len     Length of the byte array.
-+ * @param result  Byte array to receive the 8-byte encrypted MIC.
-+ */
-+void dwc_wusb_cmf(u8 *key, u8 *nonce,
-+		  char *label, u8 *bytes, int len, u8 *result)
-+{
-+	u8 block_m[16];
-+	u8 block_x[16];
-+	u8 block_t[8];
-+	int idx, blkNum;
-+	u16 la = (u16)(len + 14);
-+
-+	/* Set the AES-128 key */
-+	//dwc_aes_setkey(tfm, key, 16);
-+
-+	/* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
-+	block_m[0] = 0x59;
-+	for (idx = 0; idx < 13; idx++)
-+		block_m[idx + 1] = nonce[idx];
-+	block_m[14] = 0;
-+	block_m[15] = 0;
-+
-+	/* Produce the CBC IV */
-+	dwc_wusb_aes_encrypt(block_m, key, block_x);
-+	show_block(block_m, "CBC IV in: ", "\n", 0);
-+	show_block(block_x, "CBC IV out:", "\n", 0);
-+
-+	/* Fill block B1 from l(a) = Blen + 14, and A */
-+	block_x[0] ^= (u8)(la >> 8);
-+	block_x[1] ^= (u8)la;
-+	for (idx = 0; idx < 14; idx++)
-+		block_x[idx + 2] ^= label[idx];
-+	show_block(block_x, "After xor: ", "b1\n", 16);
-+
-+	dwc_wusb_aes_encrypt(block_x, key, block_x);
-+	show_block(block_x, "After AES: ", "b1\n", 16);
-+
-+	idx = 0;
-+	blkNum = 0;
-+
-+	/* Fill remaining blocks with B */
-+	while (len-- > 0) {
-+		block_x[idx] ^= *bytes++;
-+		if (++idx >= 16) {
-+			idx = 0;
-+			show_block(block_x, "After xor: ", "\n", blkNum);
-+			dwc_wusb_aes_encrypt(block_x, key, block_x);
-+			show_block(block_x, "After AES: ", "\n", blkNum);
-+			blkNum++;
-+		}
-+	}
-+
-+	/* Handle partial last block */
-+	if (idx > 0) {
-+		show_block(block_x, "After xor: ", "\n", blkNum);
-+		dwc_wusb_aes_encrypt(block_x, key, block_x);
-+		show_block(block_x, "After AES: ", "\n", blkNum);
-+	}
-+
-+	/* Save the MIC tag */
-+	DWC_MEMCPY(block_t, block_x, 8);
-+	show_block(block_t, "MIC tag  : ", NULL, 8);
-+
-+	/* Fill block A0 from flags = 0x01, N, and counter = 0 */
-+	block_m[0] = 0x01;
-+	block_m[14] = 0;
-+	block_m[15] = 0;
-+
-+	/* Encrypt the counter */
-+	dwc_wusb_aes_encrypt(block_m, key, block_x);
-+	show_block(block_x, "CTR[MIC] : ", NULL, 8);
-+
-+	/* XOR with MIC tag */
-+	for (idx = 0; idx < 8; idx++) {
-+		block_t[idx] ^= block_x[idx];
-+	}
-+
-+	/* Return result to caller */
-+	DWC_MEMCPY(result, block_t, 8);
-+	show_block(result, "CCM-MIC  : ", NULL, 8);
-+
-+}
-+
-+/**
-+ * The PRF function described in section 6.5 of the WUSB spec. This function
-+ * concatenates MIC values returned from dwc_cmf() to create a value of
-+ * the requested length.
-+ *
-+ * @param prf_len  Length of the PRF function in bits (64, 128, or 256).
-+ * @param key, nonce, label, bytes, len  Same as for dwc_cmf().
-+ * @param result   Byte array to receive the result.
-+ */
-+void dwc_wusb_prf(int prf_len, u8 *key,
-+		  u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
-+{
-+	int i;
-+
-+	nonce[0] = 0;
-+	for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
-+		dwc_wusb_cmf(key, nonce, label, bytes, len, result);
-+		result += 8;
-+	}
-+}
-+
-+/**
-+ * Fills in CCM Nonce per the WUSB spec.
-+ *
-+ * @param[in] haddr Host address.
-+ * @param[in] daddr Device address.
-+ * @param[in] tkid Session Key(PTK) identifier.
-+ * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
-+ */
-+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
-+			     uint8_t *nonce)
-+{
-+
-+	DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
-+
-+	DWC_MEMSET(&nonce[0], 0, 16);
-+
-+	DWC_MEMCPY(&nonce[6], tkid, 3);
-+	nonce[9] = daddr & 0xFF;
-+	nonce[10] = (daddr >> 8) & 0xFF;
-+	nonce[11] = haddr & 0xFF;
-+	nonce[12] = (haddr >> 8) & 0xFF;
-+
-+	dump_bytes("CCM nonce", nonce, 16);
-+}
-+
-+/**
-+ * Generates a 16-byte cryptographic-grade random number for the Host/Device
-+ * Nonce.
-+ */
-+void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
-+{
-+	uint8_t inonce[16];
-+	uint32_t temp[4];
-+
-+	/* Fill in the Nonce */
-+	DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
-+	inonce[9] = addr & 0xFF;
-+	inonce[10] = (addr >> 8) & 0xFF;
-+	inonce[11] = inonce[9];
-+	inonce[12] = inonce[10];
-+
-+	/* Collect "randomness samples" */
-+	DWC_RANDOM_BYTES((uint8_t *)temp, 16);
-+
-+	dwc_wusb_prf_128((uint8_t *)temp, nonce,
-+			 "Random Numbers", (uint8_t *)temp, sizeof(temp),
-+			 nonce);
-+}
-+
-+/**
-+ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
-+ * WUSB spec.
-+ *
-+ * @param[in] ccm_nonce Pointer to CCM Nonce.
-+ * @param[in] mk Master Key to derive the session from
-+ * @param[in] hnonce Pointer to Host Nonce.
-+ * @param[in] dnonce Pointer to Device Nonce.
-+ * @param[out] kck Pointer to where the KCK output is to be written.
-+ * @param[out] ptk Pointer to where the PTK output is to be written.
-+ */
-+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
-+		      uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
-+{
-+	uint8_t idata[32];
-+	uint8_t odata[32];
-+
-+	dump_bytes("ck", mk, 16);
-+	dump_bytes("hnonce", hnonce, 16);
-+	dump_bytes("dnonce", dnonce, 16);
-+
-+	/* The data is the HNonce and DNonce concatenated */
-+	DWC_MEMCPY(&idata[0], hnonce, 16);
-+	DWC_MEMCPY(&idata[16], dnonce, 16);
-+
-+	dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
-+
-+	/* Low 16 bytes of the result is the KCK, high 16 is the PTK */
-+	DWC_MEMCPY(kck, &odata[0], 16);
-+	DWC_MEMCPY(ptk, &odata[16], 16);
-+
-+	dump_bytes("kck", kck, 16);
-+	dump_bytes("ptk", ptk, 16);
-+}
-+
-+/**
-+ * Generates the Message Integrity Code over the Handshake data per the
-+ * WUSB spec.
-+ *
-+ * @param ccm_nonce Pointer to CCM Nonce.
-+ * @param kck   Pointer to Key Confirmation Key.
-+ * @param data  Pointer to Handshake data to be checked.
-+ * @param mic   Pointer to where the MIC output is to be written.
-+ */
-+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
-+		      uint8_t *data, uint8_t *mic)
-+{
-+
-+	dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
-+			data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
-+}
-+
-+#endif	/* DWC_CRYPTOLIB */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_crypto.h
-@@ -0,0 +1,111 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $
-+ * $Revision: #3 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+
-+#ifndef _DWC_CRYPTO_H_
-+#define _DWC_CRYPTO_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file contains declarations for the WUSB Cryptographic routines as
-+ * defined in the WUSB spec.  They are only to be used internally by the DWC UWB
-+ * modules.
-+ */
-+
-+#include "dwc_os.h"
-+
-+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
-+
-+void dwc_wusb_cmf(u8 *key, u8 *nonce,
-+		  char *label, u8 *bytes, int len, u8 *result);
-+void dwc_wusb_prf(int prf_len, u8 *key,
-+		  u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
-+
-+/**
-+ * The PRF-64 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
-+				   char *label, u8 *bytes, int len, u8 *result)
-+{
-+	dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
-+}
-+
-+/**
-+ * The PRF-128 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
-+				    char *label, u8 *bytes, int len, u8 *result)
-+{
-+	dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
-+}
-+
-+/**
-+ * The PRF-256 function described in section 6.5 of the WUSB spec.
-+ *
-+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
-+ */
-+static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
-+				    char *label, u8 *bytes, int len, u8 *result)
-+{
-+	dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
-+}
-+
-+
-+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
-+			       uint8_t *nonce);
-+void dwc_wusb_gen_nonce(uint16_t addr,
-+			  uint8_t *nonce);
-+
-+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
-+			uint8_t *hnonce, uint8_t *dnonce,
-+			uint8_t *kck, uint8_t *ptk);
-+
-+
-+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
-+			*kck, uint8_t *data, uint8_t *mic);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_CRYPTO_H_ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_dh.c
-@@ -0,0 +1,291 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $
-+ * $Revision: #3 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifdef DWC_CRYPTOLIB
-+
-+#ifndef CONFIG_MACH_IPMATE
-+
-+#include "dwc_dh.h"
-+#include "dwc_modpow.h"
-+
-+#ifdef DEBUG
-+/* This function prints out a buffer in the format described in the Association
-+ * Model specification. */
-+static void dh_dump(char *str, void *_num, int len)
-+{
-+	uint8_t *num = _num;
-+	int i;
-+	DWC_PRINTF("%s\n", str);
-+	for (i = 0; i < len; i ++) {
-+		DWC_PRINTF("%02x", num[i]);
-+		if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
-+		if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
-+	}
-+
-+	DWC_PRINTF("\n");
-+}
-+#else
-+#define dh_dump(_x...) do {; } while(0)
-+#endif
-+
-+/* Constant g value */
-+static __u32 dh_g[] = {
-+	0x02000000,
-+};
-+
-+/* Constant p value */
-+static __u32 dh_p[] = {
-+	0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
-+	0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
-+	0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
-+	0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
-+	0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
-+	0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
-+	0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
-+	0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
-+	0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
-+	0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
-+	0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
-+	0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
-+};
-+
-+static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
-+{
-+	uint8_t *in = _in;
-+	uint8_t *out = _out;
-+	int i;
-+	for (i=0; i<len; i++) {
-+		out[i] = in[len-1-i];
-+	}
-+}
-+
-+/* Computes the modular exponentiation (num^exp % mod).  num, exp, and mod are
-+ * big endian numbers of size len, in bytes.  Each len value must be a multiple
-+ * of 4. */
-+int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
-+		  void *exp, uint32_t exp_len,
-+		  void *mod, uint32_t mod_len,
-+		  void *out)
-+{
-+	/* modpow() takes little endian numbers.  AM uses big-endian.  This
-+	 * function swaps bytes of numbers before passing onto modpow. */
-+
-+	int retval = 0;
-+	uint32_t *result;
-+
-+	uint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);
-+	uint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);
-+	uint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);
-+
-+	dh_swap_bytes(num, &bignum_num[1], num_len);
-+	bignum_num[0] = num_len / 4;
-+
-+	dh_swap_bytes(exp, &bignum_exp[1], exp_len);
-+	bignum_exp[0] = exp_len / 4;
-+
-+	dh_swap_bytes(mod, &bignum_mod[1], mod_len);
-+	bignum_mod[0] = mod_len / 4;
-+
-+	result = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);
-+	if (!result) {
-+		retval = -1;
-+		goto dh_modpow_nomem;
-+	}
-+
-+	dh_swap_bytes(&result[1], out, result[0] * 4);
-+	dwc_free(mem_ctx, result);
-+
-+ dh_modpow_nomem:
-+	dwc_free(mem_ctx, bignum_num);
-+	dwc_free(mem_ctx, bignum_exp);
-+	dwc_free(mem_ctx, bignum_mod);
-+	return retval;
-+}
-+
-+
-+int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
-+{
-+	int retval;
-+	uint8_t m3[385];
-+
-+#ifndef DH_TEST_VECTORS
-+	DWC_RANDOM_BYTES(exp, 32);
-+#endif
-+
-+	/* Compute the pkd */
-+	if ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,
-+				    exp, 32,
-+				    dh_p, 384, pk))) {
-+		return retval;
-+	}
-+
-+	m3[384] = nd;
-+	DWC_MEMCPY(&m3[0], pk, 384);
-+	DWC_SHA256(m3, 385, hash);
-+
-+	dh_dump("PK", pk, 384);
-+	dh_dump("SHA-256(M3)", hash, 32);
-+	return 0;
-+}
-+
-+int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
-+		       uint8_t *exp, int is_host,
-+		       char *dd, uint8_t *ck, uint8_t *kdk)
-+{
-+	int retval;
-+	uint8_t mv[784];
-+	uint8_t sha_result[32];
-+	uint8_t dhkey[384];
-+	uint8_t shared_secret[384];
-+	char *message;
-+	uint32_t vd;
-+
-+	uint8_t *pk;
-+
-+	if (is_host) {
-+		pk = pkd;
-+	}
-+	else {
-+		pk = pkh;
-+	}
-+
-+	if ((retval = dwc_dh_modpow(mem_ctx, pk, 384,
-+				    exp, 32,
-+				    dh_p, 384, shared_secret))) {
-+		return retval;
-+	}
-+	dh_dump("Shared Secret", shared_secret, 384);
-+
-+	DWC_SHA256(shared_secret, 384, dhkey);
-+	dh_dump("DHKEY", dhkey, 384);
-+
-+	DWC_MEMCPY(&mv[0], pkd, 384);
-+	DWC_MEMCPY(&mv[384], pkh, 384);
-+	DWC_MEMCPY(&mv[768], "displayed digest", 16);
-+	dh_dump("MV", mv, 784);
-+
-+	DWC_SHA256(mv, 784, sha_result);
-+	dh_dump("SHA-256(MV)", sha_result, 32);
-+	dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
-+
-+	dh_swap_bytes(sha_result, &vd, 4);
-+#ifdef DEBUG
-+	DWC_PRINTF("Vd (decimal) = %d\n", vd);
-+#endif
-+
-+	switch (nd) {
-+	case 2:
-+		vd = vd % 100;
-+		DWC_SPRINTF(dd, "%02d", vd);
-+		break;
-+	case 3:
-+		vd = vd % 1000;
-+		DWC_SPRINTF(dd, "%03d", vd);
-+		break;
-+	case 4:
-+		vd = vd % 10000;
-+		DWC_SPRINTF(dd, "%04d", vd);
-+		break;
-+	}
-+#ifdef DEBUG
-+	DWC_PRINTF("Display Digits: %s\n", dd);
-+#endif
-+
-+	message = "connection key";
-+	DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
-+	dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
-+	DWC_MEMCPY(ck, sha_result, 16);
-+
-+	message = "key derivation key";
-+	DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
-+	dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
-+	DWC_MEMCPY(kdk, sha_result, 32);
-+
-+	return 0;
-+}
-+
-+
-+#ifdef DH_TEST_VECTORS
-+
-+static __u8 dh_a[] = {
-+	0x44, 0x00, 0x51, 0xd6,
-+	0xf0, 0xb5, 0x5e, 0xa9,
-+	0x67, 0xab, 0x31, 0xc6,
-+	0x8a, 0x8b, 0x5e, 0x37,
-+	0xd9, 0x10, 0xda, 0xe0,
-+	0xe2, 0xd4, 0x59, 0xa4,
-+	0x86, 0x45, 0x9c, 0xaa,
-+	0xdf, 0x36, 0x75, 0x16,
-+};
-+
-+static __u8 dh_b[] = {
-+	0x5d, 0xae, 0xc7, 0x86,
-+	0x79, 0x80, 0xa3, 0x24,
-+	0x8c, 0xe3, 0x57, 0x8f,
-+	0xc7, 0x5f, 0x1b, 0x0f,
-+	0x2d, 0xf8, 0x9d, 0x30,
-+	0x6f, 0xa4, 0x52, 0xcd,
-+	0xe0, 0x7a, 0x04, 0x8a,
-+	0xde, 0xd9, 0x26, 0x56,
-+};
-+
-+void dwc_run_dh_test_vectors(void *mem_ctx)
-+{
-+	uint8_t pkd[384];
-+	uint8_t pkh[384];
-+	uint8_t hashd[32];
-+	uint8_t hashh[32];
-+	uint8_t ck[16];
-+	uint8_t kdk[32];
-+	char dd[5];
-+
-+	DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
-+
-+	/* compute the PKd and SHA-256(PKd || Nd) */
-+	DWC_PRINTF("Computing PKd\n");
-+	dwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);
-+
-+	/* compute the PKd and SHA-256(PKh || Nd) */
-+	DWC_PRINTF("Computing PKh\n");
-+	dwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);
-+
-+	/* compute the dhkey */
-+	dwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);
-+}
-+#endif /* DH_TEST_VECTORS */
-+
-+#endif /* !CONFIG_MACH_IPMATE */
-+
-+#endif /* DWC_CRYPTOLIB */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_dh.h
-@@ -0,0 +1,106 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $
-+ * $Revision: #4 $
-+ * $Date: 2010/09/28 $
-+ * $Change: 1596182 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_DH_H_
-+#define _DWC_DH_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * This file defines the common functions on device and host for performing
-+ * numeric association as defined in the WUSB spec.  They are only to be
-+ * used internally by the DWC UWB modules. */
-+
-+extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
-+extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
-+			      uint8_t *key, uint32_t keylen,
-+			      uint8_t *out);
-+extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
-+			 void *exp, uint32_t exp_len,
-+			 void *mod, uint32_t mod_len,
-+			 void *out);
-+
-+/** Computes PKD or PKH, and SHA-256(PKd || Nd)
-+ *
-+ * PK = g^exp mod p.
-+ *
-+ * Input:
-+ * Nd = Number of digits on the device.
-+ *
-+ * Output:
-+ * exp = A 32-byte buffer to be filled with a randomly generated number.
-+ *       used as either A or B.
-+ * pk = A 384-byte buffer to be filled with the PKH or PKD.
-+ * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
-+ */
-+extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
-+
-+/** Computes the DHKEY, and VD.
-+ *
-+ * If called from host, then it will comput DHKEY=PKD^exp % p.
-+ * If called from device, then it will comput DHKEY=PKH^exp % p.
-+ *
-+ * Input:
-+ * pkd = The PKD value.
-+ * pkh = The PKH value.
-+ * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
-+ * is_host = Set to non zero if a WUSB host is calling this function.
-+ *
-+ * Output:
-+
-+ * dd = A pointer to an buffer to be set to the displayed digits string to be shown
-+ *      to the user.  This buffer should be at 5 bytes long to hold 4 digits plus a
-+ *      null termination character.  This buffer can be used directly for display.
-+ * ck = A 16-byte buffer to be filled with the CK.
-+ * kdk = A 32-byte buffer to be filled with the KDK.
-+ */
-+extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
-+			      uint8_t *exp, int is_host,
-+			      char *dd, uint8_t *ck, uint8_t *kdk);
-+
-+#ifdef DH_TEST_VECTORS
-+extern void dwc_run_dh_test_vectors(void);
-+#endif
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_DH_H_ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_list.h
-@@ -0,0 +1,594 @@
-+/*	$OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $	*/
-+/*	$NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $	*/
-+
-+/*
-+ * Copyright (c) 1991, 1993
-+ *	The Regents of the University of California.  All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions and the following disclaimer.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. Neither the name of the University nor the names of its contributors
-+ *    may be used to endorse or promote products derived from this software
-+ *    without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
-+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-+ * SUCH DAMAGE.
-+ *
-+ *	@(#)queue.h	8.5 (Berkeley) 8/20/94
-+ */
-+
-+#ifndef _DWC_LIST_H_
-+#define _DWC_LIST_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * This file defines linked list operations.  It is derived from BSD with
-+ * only the MACRO names being prefixed with DWC_.  This is because a few of
-+ * these names conflict with those on Linux.  For documentation on use, see the
-+ * inline comments in the source code.  The original license for this source
-+ * code applies and is preserved in the dwc_list.h source file.
-+ */
-+
-+/*
-+ * This file defines five types of data structures: singly-linked lists,
-+ * lists, simple queues, tail queues, and circular queues.
-+ *
-+ *
-+ * A singly-linked list is headed by a single forward pointer. The elements
-+ * are singly linked for minimum space and pointer manipulation overhead at
-+ * the expense of O(n) removal for arbitrary elements. New elements can be
-+ * added to the list after an existing element or at the head of the list.
-+ * Elements being removed from the head of the list should use the explicit
-+ * macro for this purpose for optimum efficiency. A singly-linked list may
-+ * only be traversed in the forward direction.  Singly-linked lists are ideal
-+ * for applications with large datasets and few or no removals or for
-+ * implementing a LIFO queue.
-+ *
-+ * A list is headed by a single forward pointer (or an array of forward
-+ * pointers for a hash table header). The elements are doubly linked
-+ * so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before
-+ * or after an existing element or at the head of the list. A list
-+ * may only be traversed in the forward direction.
-+ *
-+ * A simple queue is headed by a pair of pointers, one the head of the
-+ * list and the other to the tail of the list. The elements are singly
-+ * linked to save space, so elements can only be removed from the
-+ * head of the list. New elements can be added to the list before or after
-+ * an existing element, at the head of the list, or at the end of the
-+ * list. A simple queue may only be traversed in the forward direction.
-+ *
-+ * A tail queue is headed by a pair of pointers, one to the head of the
-+ * list and the other to the tail of the list. The elements are doubly
-+ * linked so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before or
-+ * after an existing element, at the head of the list, or at the end of
-+ * the list. A tail queue may be traversed in either direction.
-+ *
-+ * A circle queue is headed by a pair of pointers, one to the head of the
-+ * list and the other to the tail of the list. The elements are doubly
-+ * linked so that an arbitrary element can be removed without a need to
-+ * traverse the list. New elements can be added to the list before or after
-+ * an existing element, at the head of the list, or at the end of the list.
-+ * A circle queue may be traversed in either direction, but has a more
-+ * complex end of list detection.
-+ *
-+ * For details on the use of these macros, see the queue(3) manual page.
-+ */
-+
-+/*
-+ * Double-linked List.
-+ */
-+
-+typedef struct dwc_list_link {
-+	struct dwc_list_link *next;
-+	struct dwc_list_link *prev;
-+} dwc_list_link_t;
-+
-+#define DWC_LIST_INIT(link) do {	\
-+	(link)->next = (link);		\
-+	(link)->prev = (link);		\
-+} while (0)
-+
-+#define DWC_LIST_FIRST(link)	((link)->next)
-+#define DWC_LIST_LAST(link)	((link)->prev)
-+#define DWC_LIST_END(link)	(link)
-+#define DWC_LIST_NEXT(link)	((link)->next)
-+#define DWC_LIST_PREV(link)	((link)->prev)
-+#define DWC_LIST_EMPTY(link)	\
-+	(DWC_LIST_FIRST(link) == DWC_LIST_END(link))
-+#define DWC_LIST_ENTRY(link, type, field)			\
-+	(type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
-+
-+#if 0
-+#define DWC_LIST_INSERT_HEAD(list, link) do {			\
-+	(link)->next = (list)->next;				\
-+	(link)->prev = (list);					\
-+	(list)->next->prev = (link);				\
-+	(list)->next = (link);					\
-+} while (0)
-+
-+#define DWC_LIST_INSERT_TAIL(list, link) do {			\
-+	(link)->next = (list);					\
-+	(link)->prev = (list)->prev;				\
-+	(list)->prev->next = (link);				\
-+	(list)->prev = (link);					\
-+} while (0)
-+#else
-+#define DWC_LIST_INSERT_HEAD(list, link) do {			\
-+	dwc_list_link_t *__next__ = (list)->next;		\
-+	__next__->prev = (link);				\
-+	(link)->next = __next__;				\
-+	(link)->prev = (list);					\
-+	(list)->next = (link);					\
-+} while (0)
-+
-+#define DWC_LIST_INSERT_TAIL(list, link) do {			\
-+	dwc_list_link_t *__prev__ = (list)->prev;		\
-+	(list)->prev = (link);					\
-+	(link)->next = (list);					\
-+	(link)->prev = __prev__;				\
-+	__prev__->next = (link);				\
-+} while (0)
-+#endif
-+
-+#if 0
-+static inline void __list_add(struct list_head *new,
-+                              struct list_head *prev,
-+                              struct list_head *next)
-+{
-+        next->prev = new;
-+        new->next = next;
-+        new->prev = prev;
-+        prev->next = new;
-+}
-+
-+static inline void list_add(struct list_head *new, struct list_head *head)
-+{
-+        __list_add(new, head, head->next);
-+}
-+
-+static inline void list_add_tail(struct list_head *new, struct list_head *head)
-+{
-+        __list_add(new, head->prev, head);
-+}
-+
-+static inline void __list_del(struct list_head * prev, struct list_head * next)
-+{
-+        next->prev = prev;
-+        prev->next = next;
-+}
-+
-+static inline void list_del(struct list_head *entry)
-+{
-+        __list_del(entry->prev, entry->next);
-+        entry->next = LIST_POISON1;
-+        entry->prev = LIST_POISON2;
-+}
-+#endif
-+
-+#define DWC_LIST_REMOVE(link) do {				\
-+	(link)->next->prev = (link)->prev;			\
-+	(link)->prev->next = (link)->next;			\
-+} while (0)
-+
-+#define DWC_LIST_REMOVE_INIT(link) do {				\
-+	DWC_LIST_REMOVE(link);					\
-+	DWC_LIST_INIT(link);					\
-+} while (0)
-+
-+#define DWC_LIST_MOVE_HEAD(list, link) do {			\
-+	DWC_LIST_REMOVE(link);					\
-+	DWC_LIST_INSERT_HEAD(list, link);			\
-+} while (0)
-+
-+#define DWC_LIST_MOVE_TAIL(list, link) do {			\
-+	DWC_LIST_REMOVE(link);					\
-+	DWC_LIST_INSERT_TAIL(list, link);			\
-+} while (0)
-+
-+#define DWC_LIST_FOREACH(var, list)				\
-+	for((var) = DWC_LIST_FIRST(list);			\
-+	    (var) != DWC_LIST_END(list);			\
-+	    (var) = DWC_LIST_NEXT(var))
-+
-+#define DWC_LIST_FOREACH_SAFE(var, var2, list)			\
-+	for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var);	\
-+	    (var) != DWC_LIST_END(list);			\
-+	    (var) = (var2), (var2) = DWC_LIST_NEXT(var2))
-+
-+#define DWC_LIST_FOREACH_REVERSE(var, list)			\
-+	for((var) = DWC_LIST_LAST(list);			\
-+	    (var) != DWC_LIST_END(list);			\
-+	    (var) = DWC_LIST_PREV(var))
-+
-+/*
-+ * Singly-linked List definitions.
-+ */
-+#define DWC_SLIST_HEAD(name, type)					\
-+struct name {								\
-+	struct type *slh_first;	/* first element */			\
-+}
-+
-+#define DWC_SLIST_HEAD_INITIALIZER(head)				\
-+	{ NULL }
-+
-+#define DWC_SLIST_ENTRY(type)						\
-+struct {								\
-+	struct type *sle_next;	/* next element */			\
-+}
-+
-+/*
-+ * Singly-linked List access methods.
-+ */
-+#define DWC_SLIST_FIRST(head)	((head)->slh_first)
-+#define DWC_SLIST_END(head)		NULL
-+#define DWC_SLIST_EMPTY(head)	(SLIST_FIRST(head) == SLIST_END(head))
-+#define DWC_SLIST_NEXT(elm, field)	((elm)->field.sle_next)
-+
-+#define DWC_SLIST_FOREACH(var, head, field)				\
-+	for((var) = SLIST_FIRST(head);					\
-+	    (var) != SLIST_END(head);					\
-+	    (var) = SLIST_NEXT(var, field))
-+
-+#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field)		\
-+	for((varp) = &SLIST_FIRST((head));				\
-+	    ((var) = *(varp)) != SLIST_END(head);			\
-+	    (varp) = &SLIST_NEXT((var), field))
-+
-+/*
-+ * Singly-linked List functions.
-+ */
-+#define DWC_SLIST_INIT(head) {						\
-+	SLIST_FIRST(head) = SLIST_END(head);				\
-+}
-+
-+#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do {		\
-+	(elm)->field.sle_next = (slistelm)->field.sle_next;		\
-+	(slistelm)->field.sle_next = (elm);				\
-+} while (0)
-+
-+#define DWC_SLIST_INSERT_HEAD(head, elm, field) do {			\
-+	(elm)->field.sle_next = (head)->slh_first;			\
-+	(head)->slh_first = (elm);					\
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do {			\
-+	(elm)->field.sle_next = (elm)->field.sle_next->field.sle_next;	\
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE_HEAD(head, field) do {				\
-+	(head)->slh_first = (head)->slh_first->field.sle_next;		\
-+} while (0)
-+
-+#define DWC_SLIST_REMOVE(head, elm, type, field) do {			\
-+	if ((head)->slh_first == (elm)) {				\
-+		SLIST_REMOVE_HEAD((head), field);			\
-+	}								\
-+	else {								\
-+		struct type *curelm = (head)->slh_first;		\
-+		while( curelm->field.sle_next != (elm) )		\
-+			curelm = curelm->field.sle_next;		\
-+		curelm->field.sle_next =				\
-+		    curelm->field.sle_next->field.sle_next;		\
-+	}								\
-+} while (0)
-+
-+/*
-+ * Simple queue definitions.
-+ */
-+#define DWC_SIMPLEQ_HEAD(name, type)					\
-+struct name {								\
-+	struct type *sqh_first;	/* first element */			\
-+	struct type **sqh_last;	/* addr of last next element */		\
-+}
-+
-+#define DWC_SIMPLEQ_HEAD_INITIALIZER(head)				\
-+	{ NULL, &(head).sqh_first }
-+
-+#define DWC_SIMPLEQ_ENTRY(type)						\
-+struct {								\
-+	struct type *sqe_next;	/* next element */			\
-+}
-+
-+/*
-+ * Simple queue access methods.
-+ */
-+#define DWC_SIMPLEQ_FIRST(head)	    ((head)->sqh_first)
-+#define DWC_SIMPLEQ_END(head)	    NULL
-+#define DWC_SIMPLEQ_EMPTY(head)	    (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
-+#define DWC_SIMPLEQ_NEXT(elm, field)    ((elm)->field.sqe_next)
-+
-+#define DWC_SIMPLEQ_FOREACH(var, head, field)				\
-+	for((var) = SIMPLEQ_FIRST(head);				\
-+	    (var) != SIMPLEQ_END(head);					\
-+	    (var) = SIMPLEQ_NEXT(var, field))
-+
-+/*
-+ * Simple queue functions.
-+ */
-+#define DWC_SIMPLEQ_INIT(head) do {					\
-+	(head)->sqh_first = NULL;					\
-+	(head)->sqh_last = &(head)->sqh_first;				\
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do {			\
-+	if (((elm)->field.sqe_next = (head)->sqh_first) == NULL)	\
-+		(head)->sqh_last = &(elm)->field.sqe_next;		\
-+	(head)->sqh_first = (elm);					\
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do {			\
-+	(elm)->field.sqe_next = NULL;					\
-+	*(head)->sqh_last = (elm);					\
-+	(head)->sqh_last = &(elm)->field.sqe_next;			\
-+} while (0)
-+
-+#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do {	\
-+	if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
-+		(head)->sqh_last = &(elm)->field.sqe_next;		\
-+	(listelm)->field.sqe_next = (elm);				\
-+} while (0)
-+
-+#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do {			\
-+	if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
-+		(head)->sqh_last = &(head)->sqh_first;			\
-+} while (0)
-+
-+/*
-+ * Tail queue definitions.
-+ */
-+#define DWC_TAILQ_HEAD(name, type)					\
-+struct name {								\
-+	struct type *tqh_first;	/* first element */			\
-+	struct type **tqh_last;	/* addr of last next element */		\
-+}
-+
-+#define DWC_TAILQ_HEAD_INITIALIZER(head)				\
-+	{ NULL, &(head).tqh_first }
-+
-+#define DWC_TAILQ_ENTRY(type)						\
-+struct {								\
-+	struct type *tqe_next;	/* next element */			\
-+	struct type **tqe_prev;	/* address of previous next element */	\
-+}
-+
-+/*
-+ * tail queue access methods
-+ */
-+#define DWC_TAILQ_FIRST(head)		((head)->tqh_first)
-+#define DWC_TAILQ_END(head)		NULL
-+#define DWC_TAILQ_NEXT(elm, field)	((elm)->field.tqe_next)
-+#define DWC_TAILQ_LAST(head, headname)					\
-+	(*(((struct headname *)((head)->tqh_last))->tqh_last))
-+/* XXX */
-+#define DWC_TAILQ_PREV(elm, headname, field)				\
-+	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-+#define DWC_TAILQ_EMPTY(head)						\
-+	(DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head))
-+
-+#define DWC_TAILQ_FOREACH(var, head, field)				\
-+	for ((var) = DWC_TAILQ_FIRST(head);				\
-+	    (var) != DWC_TAILQ_END(head);				\
-+	    (var) = DWC_TAILQ_NEXT(var, field))
-+
-+#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
-+	for ((var) = DWC_TAILQ_LAST(head, headname);			\
-+	    (var) != DWC_TAILQ_END(head);				\
-+	    (var) = DWC_TAILQ_PREV(var, headname, field))
-+
-+/*
-+ * Tail queue functions.
-+ */
-+#define DWC_TAILQ_INIT(head) do {					\
-+	(head)->tqh_first = NULL;					\
-+	(head)->tqh_last = &(head)->tqh_first;				\
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do {			\
-+	if (((elm)->field.tqe_next = (head)->tqh_first) != NULL)	\
-+		(head)->tqh_first->field.tqe_prev =			\
-+		    &(elm)->field.tqe_next;				\
-+	else								\
-+		(head)->tqh_last = &(elm)->field.tqe_next;		\
-+	(head)->tqh_first = (elm);					\
-+	(elm)->field.tqe_prev = &(head)->tqh_first;			\
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do {			\
-+	(elm)->field.tqe_next = NULL;					\
-+	(elm)->field.tqe_prev = (head)->tqh_last;			\
-+	*(head)->tqh_last = (elm);					\
-+	(head)->tqh_last = &(elm)->field.tqe_next;			\
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
-+	if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
-+		(elm)->field.tqe_next->field.tqe_prev =			\
-+		    &(elm)->field.tqe_next;				\
-+	else								\
-+		(head)->tqh_last = &(elm)->field.tqe_next;		\
-+	(listelm)->field.tqe_next = (elm);				\
-+	(elm)->field.tqe_prev = &(listelm)->field.tqe_next;		\
-+} while (0)
-+
-+#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do {		\
-+	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
-+	(elm)->field.tqe_next = (listelm);				\
-+	*(listelm)->field.tqe_prev = (elm);				\
-+	(listelm)->field.tqe_prev = &(elm)->field.tqe_next;		\
-+} while (0)
-+
-+#define DWC_TAILQ_REMOVE(head, elm, field) do {				\
-+	if (((elm)->field.tqe_next) != NULL)				\
-+		(elm)->field.tqe_next->field.tqe_prev =			\
-+		    (elm)->field.tqe_prev;				\
-+	else								\
-+		(head)->tqh_last = (elm)->field.tqe_prev;		\
-+	*(elm)->field.tqe_prev = (elm)->field.tqe_next;			\
-+} while (0)
-+
-+#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do {			\
-+	if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL)	\
-+		(elm2)->field.tqe_next->field.tqe_prev =		\
-+		    &(elm2)->field.tqe_next;				\
-+	else								\
-+		(head)->tqh_last = &(elm2)->field.tqe_next;		\
-+	(elm2)->field.tqe_prev = (elm)->field.tqe_prev;			\
-+	*(elm2)->field.tqe_prev = (elm2);				\
-+} while (0)
-+
-+/*
-+ * Circular queue definitions.
-+ */
-+#define DWC_CIRCLEQ_HEAD(name, type)					\
-+struct name {								\
-+	struct type *cqh_first;		/* first element */		\
-+	struct type *cqh_last;		/* last element */		\
-+}
-+
-+#define DWC_CIRCLEQ_HEAD_INITIALIZER(head)				\
-+	{ DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
-+
-+#define DWC_CIRCLEQ_ENTRY(type)						\
-+struct {								\
-+	struct type *cqe_next;		/* next element */		\
-+	struct type *cqe_prev;		/* previous element */		\
-+}
-+
-+/*
-+ * Circular queue access methods
-+ */
-+#define DWC_CIRCLEQ_FIRST(head)		((head)->cqh_first)
-+#define DWC_CIRCLEQ_LAST(head)		((head)->cqh_last)
-+#define DWC_CIRCLEQ_END(head)		((void *)(head))
-+#define DWC_CIRCLEQ_NEXT(elm, field)	((elm)->field.cqe_next)
-+#define DWC_CIRCLEQ_PREV(elm, field)	((elm)->field.cqe_prev)
-+#define DWC_CIRCLEQ_EMPTY(head)						\
-+	(DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
-+
-+#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
-+
-+#define DWC_CIRCLEQ_FOREACH(var, head, field)				\
-+	for((var) = DWC_CIRCLEQ_FIRST(head);				\
-+	    (var) != DWC_CIRCLEQ_END(head);				\
-+	    (var) = DWC_CIRCLEQ_NEXT(var, field))
-+
-+#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field)			\
-+	for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
-+	    (var) != DWC_CIRCLEQ_END(head);					\
-+	    (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
-+
-+#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field)			\
-+	for((var) = DWC_CIRCLEQ_LAST(head);				\
-+	    (var) != DWC_CIRCLEQ_END(head);				\
-+	    (var) = DWC_CIRCLEQ_PREV(var, field))
-+
-+/*
-+ * Circular queue functions.
-+ */
-+#define DWC_CIRCLEQ_INIT(head) do {					\
-+	(head)->cqh_first = DWC_CIRCLEQ_END(head);			\
-+	(head)->cqh_last = DWC_CIRCLEQ_END(head);			\
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do {				\
-+	(elm)->field.cqe_next = NULL;					\
-+	(elm)->field.cqe_prev = NULL;					\
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do {	\
-+	(elm)->field.cqe_next = (listelm)->field.cqe_next;		\
-+	(elm)->field.cqe_prev = (listelm);				\
-+	if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head))		\
-+		(head)->cqh_last = (elm);				\
-+	else								\
-+		(listelm)->field.cqe_next->field.cqe_prev = (elm);	\
-+	(listelm)->field.cqe_next = (elm);				\
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do {	\
-+	(elm)->field.cqe_next = (listelm);				\
-+	(elm)->field.cqe_prev = (listelm)->field.cqe_prev;		\
-+	if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head))		\
-+		(head)->cqh_first = (elm);				\
-+	else								\
-+		(listelm)->field.cqe_prev->field.cqe_next = (elm);	\
-+	(listelm)->field.cqe_prev = (elm);				\
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do {			\
-+	(elm)->field.cqe_next = (head)->cqh_first;			\
-+	(elm)->field.cqe_prev = DWC_CIRCLEQ_END(head);			\
-+	if ((head)->cqh_last == DWC_CIRCLEQ_END(head))			\
-+		(head)->cqh_last = (elm);				\
-+	else								\
-+		(head)->cqh_first->field.cqe_prev = (elm);		\
-+	(head)->cqh_first = (elm);					\
-+} while (0)
-+
-+#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do {			\
-+	(elm)->field.cqe_next = DWC_CIRCLEQ_END(head);			\
-+	(elm)->field.cqe_prev = (head)->cqh_last;			\
-+	if ((head)->cqh_first == DWC_CIRCLEQ_END(head))			\
-+		(head)->cqh_first = (elm);				\
-+	else								\
-+		(head)->cqh_last->field.cqe_next = (elm);		\
-+	(head)->cqh_last = (elm);					\
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REMOVE(head, elm, field) do {			\
-+	if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head))		\
-+		(head)->cqh_last = (elm)->field.cqe_prev;		\
-+	else								\
-+		(elm)->field.cqe_next->field.cqe_prev =			\
-+		    (elm)->field.cqe_prev;				\
-+	if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head))		\
-+		(head)->cqh_first = (elm)->field.cqe_next;		\
-+	else								\
-+		(elm)->field.cqe_prev->field.cqe_next =			\
-+		    (elm)->field.cqe_next;				\
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do {			\
-+	DWC_CIRCLEQ_REMOVE(head, elm, field);				\
-+	DWC_CIRCLEQ_INIT_ENTRY(elm, field);				\
-+} while (0)
-+
-+#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do {		\
-+	if (((elm2)->field.cqe_next = (elm)->field.cqe_next) ==		\
-+	    DWC_CIRCLEQ_END(head))					\
-+		(head).cqh_last = (elm2);				\
-+	else								\
-+		(elm2)->field.cqe_next->field.cqe_prev = (elm2);	\
-+	if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) ==		\
-+	    DWC_CIRCLEQ_END(head))					\
-+		(head).cqh_first = (elm2);				\
-+	else								\
-+		(elm2)->field.cqe_prev->field.cqe_next = (elm2);	\
-+} while (0)
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_LIST_H_ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_mem.c
-@@ -0,0 +1,245 @@
-+/* Memory Debugging */
-+#ifdef DWC_DEBUG_MEMORY
-+
-+#include "dwc_os.h"
-+#include "dwc_list.h"
-+
-+struct allocation {
-+	void *addr;
-+	void *ctx;
-+	char *func;
-+	int line;
-+	uint32_t size;
-+	int dma;
-+	DWC_CIRCLEQ_ENTRY(allocation) entry;
-+};
-+
-+DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
-+
-+struct allocation_manager {
-+	void *mem_ctx;
-+	struct allocation_queue allocations;
-+
-+	/* statistics */
-+	int num;
-+	int num_freed;
-+	int num_active;
-+	uint32_t total;
-+	uint32_t cur;
-+	uint32_t max;
-+};
-+
-+static struct allocation_manager *manager = NULL;
-+
-+static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,
-+			  int dma)
-+{
-+	struct allocation *a;
-+
-+	DWC_ASSERT(manager != NULL, "manager not allocated");
-+
-+	a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));
-+	if (!a) {
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);
-+	if (!a->func) {
-+		__DWC_FREE(manager->mem_ctx, a);
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);
-+	a->addr = addr;
-+	a->ctx = ctx;
-+	a->line = line;
-+	a->size = size;
-+	a->dma = dma;
-+	DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
-+
-+	/* Update stats */
-+	manager->num++;
-+	manager->num_active++;
-+	manager->total += size;
-+	manager->cur += size;
-+
-+	if (manager->max < manager->cur) {
-+		manager->max = manager->cur;
-+	}
-+
-+	return 0;
-+}
-+
-+static struct allocation *find_allocation(void *ctx, void *addr)
-+{
-+	struct allocation *a;
-+
-+	DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+		if (a->ctx == ctx && a->addr == addr) {
-+			return a;
-+		}
-+	}
-+
-+	return NULL;
-+}
-+
-+static void free_allocation(void *ctx, void *addr, char const *func, int line)
-+{
-+	struct allocation *a = find_allocation(ctx, addr);
-+
-+	if (!a) {
-+		DWC_ASSERT(0,
-+			   "Free of address %p that was never allocated or already freed %s:%d",
-+			   addr, func, line);
-+		return;
-+	}
-+
-+	DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
-+
-+	manager->num_active--;
-+	manager->num_freed++;
-+	manager->cur -= a->size;
-+	__DWC_FREE(manager->mem_ctx, a->func);
-+	__DWC_FREE(manager->mem_ctx, a);
-+}
-+
-+int dwc_memory_debug_start(void *mem_ctx)
-+{
-+	DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
-+
-+	if (manager) {
-+		return -DWC_E_BUSY;
-+	}
-+
-+	manager = __DWC_ALLOC(mem_ctx, sizeof(*manager));
-+	if (!manager) {
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	DWC_CIRCLEQ_INIT(&manager->allocations);
-+	manager->mem_ctx = mem_ctx;
-+	manager->num = 0;
-+	manager->num_freed = 0;
-+	manager->num_active = 0;
-+	manager->total = 0;
-+	manager->cur = 0;
-+	manager->max = 0;
-+
-+	return 0;
-+}
-+
-+void dwc_memory_debug_stop(void)
-+{
-+	struct allocation *a;
-+
-+	dwc_memory_debug_report();
-+
-+	DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+		DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
-+		free_allocation(a->ctx, a->addr, NULL, -1);
-+	}
-+
-+	__DWC_FREE(manager->mem_ctx, manager);
-+}
-+
-+void dwc_memory_debug_report(void)
-+{
-+	struct allocation *a;
-+
-+	DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
-+	DWC_PRINTF("Num Allocations = %d\n", manager->num);
-+	DWC_PRINTF("Freed = %d\n", manager->num_freed);
-+	DWC_PRINTF("Active = %d\n", manager->num_active);
-+	DWC_PRINTF("Current Memory Used = %d\n", manager->cur);
-+	DWC_PRINTF("Total Memory Used = %d\n", manager->total);
-+	DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
-+	DWC_PRINTF("Unfreed allocations:\n");
-+
-+	DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
-+		DWC_PRINTF("    addr=%p, size=%d from %s:%d, DMA=%d\n",
-+			   a->addr, a->size, a->func, a->line, a->dma);
-+	}
-+}
-+
-+/* The replacement functions */
-+void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)
-+{
-+	void *addr = __DWC_ALLOC(mem_ctx, size);
-+
-+	if (!addr) {
-+		return NULL;
-+	}
-+
-+	if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
-+		__DWC_FREE(mem_ctx, addr);
-+		return NULL;
-+	}
-+
-+	return addr;
-+}
-+
-+void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,
-+			     int line)
-+{
-+	void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);
-+
-+	if (!addr) {
-+		return NULL;
-+	}
-+
-+	if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
-+		__DWC_FREE(mem_ctx, addr);
-+		return NULL;
-+	}
-+
-+	return addr;
-+}
-+
-+void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)
-+{
-+	free_allocation(mem_ctx, addr, func, line);
-+	__DWC_FREE(mem_ctx, addr);
-+}
-+
-+void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+			  char const *func, int line)
-+{
-+	void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);
-+
-+	if (!addr) {
-+		return NULL;
-+	}
-+
-+	if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
-+		__DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
-+		return NULL;
-+	}
-+
-+	return addr;
-+}
-+
-+void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,
-+				 dwc_dma_t *dma_addr, char const *func, int line)
-+{
-+	void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);
-+
-+	if (!addr) {
-+		return NULL;
-+	}
-+
-+	if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
-+		__DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
-+		return NULL;
-+	}
-+
-+	return addr;
-+}
-+
-+void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
-+			dwc_dma_t dma_addr, char const *func, int line)
-+{
-+	free_allocation(dma_ctx, virt_addr, func, line);
-+	__DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);
-+}
-+
-+#endif /* DWC_DEBUG_MEMORY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_modpow.c
-@@ -0,0 +1,636 @@
-+/* Bignum routines adapted from PUTTY sources.  PuTTY copyright notice follows.
-+ *
-+ * PuTTY is copyright 1997-2007 Simon Tatham.
-+ *
-+ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
-+ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
-+ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
-+ * Kuhn, and CORE SDI S.A.
-+ *
-+ * Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation files
-+ * (the "Software"), to deal in the Software without restriction,
-+ * including without limitation the rights to use, copy, modify, merge,
-+ * publish, distribute, sublicense, and/or sell copies of the Software,
-+ * and to permit persons to whom the Software is furnished to do so,
-+ * subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT.  IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
-+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
-+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-+ *
-+ */
-+#ifdef DWC_CRYPTOLIB
-+
-+#ifndef CONFIG_MACH_IPMATE
-+
-+#include "dwc_modpow.h"
-+
-+#define BIGNUM_INT_MASK  0xFFFFFFFFUL
-+#define BIGNUM_TOP_BIT   0x80000000UL
-+#define BIGNUM_INT_BITS  32
-+
-+
-+static void *snmalloc(void *mem_ctx, size_t n, size_t size)
-+{
-+    void *p;
-+    size *= n;
-+    if (size == 0) size = 1;
-+    p = dwc_alloc(mem_ctx, size);
-+    return p;
-+}
-+
-+#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))
-+#define sfree dwc_free
-+
-+/*
-+ * Usage notes:
-+ *  * Do not call the DIVMOD_WORD macro with expressions such as array
-+ *    subscripts, as some implementations object to this (see below).
-+ *  * Note that none of the division methods below will cope if the
-+ *    quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
-+ *    to avoid this case.
-+ *    If this condition occurs, in the case of the x86 DIV instruction,
-+ *    an overflow exception will occur, which (according to a correspondent)
-+ *    will manifest on Windows as something like
-+ *      0xC0000095: Integer overflow
-+ *    The C variant won't give the right answer, either.
-+ */
-+
-+#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
-+
-+#if defined __GNUC__ && defined __i386__
-+#define DIVMOD_WORD(q, r, hi, lo, w) \
-+    __asm__("div %2" : \
-+	    "=d" (r), "=a" (q) : \
-+	    "r" (w), "d" (hi), "a" (lo))
-+#else
-+#define DIVMOD_WORD(q, r, hi, lo, w) do { \
-+    BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
-+    q = n / w; \
-+    r = n % w; \
-+} while (0)
-+#endif
-+
-+//    q = n / w;
-+//    r = n % w;
-+
-+#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
-+
-+#define BIGNUM_INTERNAL
-+
-+static Bignum newbn(void *mem_ctx, int length)
-+{
-+    Bignum b = snewn(mem_ctx, length + 1, BignumInt);
-+    //if (!b)
-+    //abort();		       /* FIXME */
-+    DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
-+    b[0] = length;
-+    return b;
-+}
-+
-+void freebn(void *mem_ctx, Bignum b)
-+{
-+    /*
-+     * Burn the evidence, just in case.
-+     */
-+    DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
-+    sfree(mem_ctx, b);
-+}
-+
-+/*
-+ * Compute c = a * b.
-+ * Input is in the first len words of a and b.
-+ * Result is returned in the first 2*len words of c.
-+ */
-+static void internal_mul(BignumInt *a, BignumInt *b,
-+			 BignumInt *c, int len)
-+{
-+    int i, j;
-+    BignumDblInt t;
-+
-+    for (j = 0; j < 2 * len; j++)
-+	c[j] = 0;
-+
-+    for (i = len - 1; i >= 0; i--) {
-+	t = 0;
-+	for (j = len - 1; j >= 0; j--) {
-+	    t += MUL_WORD(a[i], (BignumDblInt) b[j]);
-+	    t += (BignumDblInt) c[i + j + 1];
-+	    c[i + j + 1] = (BignumInt) t;
-+	    t = t >> BIGNUM_INT_BITS;
-+	}
-+	c[i] = (BignumInt) t;
-+    }
-+}
-+
-+static void internal_add_shifted(BignumInt *number,
-+				 unsigned n, int shift)
-+{
-+    int word = 1 + (shift / BIGNUM_INT_BITS);
-+    int bshift = shift % BIGNUM_INT_BITS;
-+    BignumDblInt addend;
-+
-+    addend = (BignumDblInt)n << bshift;
-+
-+    while (addend) {
-+	addend += number[word];
-+	number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
-+	addend >>= BIGNUM_INT_BITS;
-+	word++;
-+    }
-+}
-+
-+/*
-+ * Compute a = a % m.
-+ * Input in first alen words of a and first mlen words of m.
-+ * Output in first alen words of a
-+ * (of which first alen-mlen words will be zero).
-+ * The MSW of m MUST have its high bit set.
-+ * Quotient is accumulated in the `quotient' array, which is a Bignum
-+ * rather than the internal bigendian format. Quotient parts are shifted
-+ * left by `qshift' before adding into quot.
-+ */
-+static void internal_mod(BignumInt *a, int alen,
-+			 BignumInt *m, int mlen,
-+			 BignumInt *quot, int qshift)
-+{
-+    BignumInt m0, m1;
-+    unsigned int h;
-+    int i, k;
-+
-+    m0 = m[0];
-+    if (mlen > 1)
-+	m1 = m[1];
-+    else
-+	m1 = 0;
-+
-+    for (i = 0; i <= alen - mlen; i++) {
-+	BignumDblInt t;
-+	unsigned int q, r, c, ai1;
-+
-+	if (i == 0) {
-+	    h = 0;
-+	} else {
-+	    h = a[i - 1];
-+	    a[i - 1] = 0;
-+	}
-+
-+	if (i == alen - 1)
-+	    ai1 = 0;
-+	else
-+	    ai1 = a[i + 1];
-+
-+	/* Find q = h:a[i] / m0 */
-+	if (h >= m0) {
-+	    /*
-+	     * Special case.
-+	     *
-+	     * To illustrate it, suppose a BignumInt is 8 bits, and
-+	     * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
-+	     * our initial division will be 0xA123 / 0xA1, which
-+	     * will give a quotient of 0x100 and a divide overflow.
-+	     * However, the invariants in this division algorithm
-+	     * are not violated, since the full number A1:23:... is
-+	     * _less_ than the quotient prefix A1:B2:... and so the
-+	     * following correction loop would have sorted it out.
-+	     *
-+	     * In this situation we set q to be the largest
-+	     * quotient we _can_ stomach (0xFF, of course).
-+	     */
-+	    q = BIGNUM_INT_MASK;
-+	} else {
-+	    /* Macro doesn't want an array subscript expression passed
-+	     * into it (see definition), so use a temporary. */
-+	    BignumInt tmplo = a[i];
-+	    DIVMOD_WORD(q, r, h, tmplo, m0);
-+
-+	    /* Refine our estimate of q by looking at
-+	     h:a[i]:a[i+1] / m0:m1 */
-+	    t = MUL_WORD(m1, q);
-+	    if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
-+		q--;
-+		t -= m1;
-+		r = (r + m0) & BIGNUM_INT_MASK;     /* overflow? */
-+		if (r >= (BignumDblInt) m0 &&
-+		    t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
-+	    }
-+	}
-+
-+	/* Subtract q * m from a[i...] */
-+	c = 0;
-+	for (k = mlen - 1; k >= 0; k--) {
-+	    t = MUL_WORD(q, m[k]);
-+	    t += c;
-+	    c = (unsigned)(t >> BIGNUM_INT_BITS);
-+	    if ((BignumInt) t > a[i + k])
-+		c++;
-+	    a[i + k] -= (BignumInt) t;
-+	}
-+
-+	/* Add back m in case of borrow */
-+	if (c != h) {
-+	    t = 0;
-+	    for (k = mlen - 1; k >= 0; k--) {
-+		t += m[k];
-+		t += a[i + k];
-+		a[i + k] = (BignumInt) t;
-+		t = t >> BIGNUM_INT_BITS;
-+	    }
-+	    q--;
-+	}
-+	if (quot)
-+	    internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
-+    }
-+}
-+
-+/*
-+ * Compute p % mod.
-+ * The most significant word of mod MUST be non-zero.
-+ * We assume that the result array is the same size as the mod array.
-+ * We optionally write out a quotient if `quotient' is non-NULL.
-+ * We can avoid writing out the result if `result' is NULL.
-+ */
-+void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)
-+{
-+    BignumInt *n, *m;
-+    int mshift;
-+    int plen, mlen, i, j;
-+
-+    /* Allocate m of size mlen, copy mod to m */
-+    /* We use big endian internally */
-+    mlen = mod[0];
-+    m = snewn(mem_ctx, mlen, BignumInt);
-+    //if (!m)
-+    //abort();		       /* FIXME */
-+    for (j = 0; j < mlen; j++)
-+	m[j] = mod[mod[0] - j];
-+
-+    /* Shift m left to make msb bit set */
-+    for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
-+	if ((m[0] << mshift) & BIGNUM_TOP_BIT)
-+	    break;
-+    if (mshift) {
-+	for (i = 0; i < mlen - 1; i++)
-+	    m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
-+	m[mlen - 1] = m[mlen - 1] << mshift;
-+    }
-+
-+    plen = p[0];
-+    /* Ensure plen > mlen */
-+    if (plen <= mlen)
-+	plen = mlen + 1;
-+
-+    /* Allocate n of size plen, copy p to n */
-+    n = snewn(mem_ctx, plen, BignumInt);
-+    //if (!n)
-+    //abort();		       /* FIXME */
-+    for (j = 0; j < plen; j++)
-+	n[j] = 0;
-+    for (j = 1; j <= (int)p[0]; j++)
-+	n[plen - j] = p[j];
-+
-+    /* Main computation */
-+    internal_mod(n, plen, m, mlen, quotient, mshift);
-+
-+    /* Fixup result in case the modulus was shifted */
-+    if (mshift) {
-+	for (i = plen - mlen - 1; i < plen - 1; i++)
-+	    n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
-+	n[plen - 1] = n[plen - 1] << mshift;
-+	internal_mod(n, plen, m, mlen, quotient, 0);
-+	for (i = plen - 1; i >= plen - mlen; i--)
-+	    n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
-+    }
-+
-+    /* Copy result to buffer */
-+    if (result) {
-+	for (i = 1; i <= (int)result[0]; i++) {
-+	    int j = plen - i;
-+	    result[i] = j >= 0 ? n[j] : 0;
-+	}
-+    }
-+
-+    /* Free temporary arrays */
-+    for (i = 0; i < mlen; i++)
-+	m[i] = 0;
-+    sfree(mem_ctx, m);
-+    for (i = 0; i < plen; i++)
-+	n[i] = 0;
-+    sfree(mem_ctx, n);
-+}
-+
-+/*
-+ * Simple remainder.
-+ */
-+Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)
-+{
-+    Bignum r = newbn(mem_ctx, b[0]);
-+    bigdivmod(mem_ctx, a, b, r, NULL);
-+    return r;
-+}
-+
-+/*
-+ * Compute (base ^ exp) % mod.
-+ */
-+Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)
-+{
-+    BignumInt *a, *b, *n, *m;
-+    int mshift;
-+    int mlen, i, j;
-+    Bignum base, result;
-+
-+    /*
-+     * The most significant word of mod needs to be non-zero. It
-+     * should already be, but let's make sure.
-+     */
-+    //assert(mod[mod[0]] != 0);
-+
-+    /*
-+     * Make sure the base is smaller than the modulus, by reducing
-+     * it modulo the modulus if not.
-+     */
-+    base = bigmod(mem_ctx, base_in, mod);
-+
-+    /* Allocate m of size mlen, copy mod to m */
-+    /* We use big endian internally */
-+    mlen = mod[0];
-+    m = snewn(mem_ctx, mlen, BignumInt);
-+    //if (!m)
-+    //abort();		       /* FIXME */
-+    for (j = 0; j < mlen; j++)
-+	m[j] = mod[mod[0] - j];
-+
-+    /* Shift m left to make msb bit set */
-+    for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
-+	if ((m[0] << mshift) & BIGNUM_TOP_BIT)
-+	    break;
-+    if (mshift) {
-+	for (i = 0; i < mlen - 1; i++)
-+	    m[i] =
-+		(m[i] << mshift) | (m[i + 1] >>
-+				    (BIGNUM_INT_BITS - mshift));
-+	m[mlen - 1] = m[mlen - 1] << mshift;
-+    }
-+
-+    /* Allocate n of size mlen, copy base to n */
-+    n = snewn(mem_ctx, mlen, BignumInt);
-+    //if (!n)
-+    //abort();		       /* FIXME */
-+    i = mlen - base[0];
-+    for (j = 0; j < i; j++)
-+	n[j] = 0;
-+    for (j = 0; j < base[0]; j++)
-+	n[i + j] = base[base[0] - j];
-+
-+    /* Allocate a and b of size 2*mlen. Set a = 1 */
-+    a = snewn(mem_ctx, 2 * mlen, BignumInt);
-+    //if (!a)
-+    //abort();		       /* FIXME */
-+    b = snewn(mem_ctx, 2 * mlen, BignumInt);
-+    //if (!b)
-+    //abort();		       /* FIXME */
-+    for (i = 0; i < 2 * mlen; i++)
-+	a[i] = 0;
-+    a[2 * mlen - 1] = 1;
-+
-+    /* Skip leading zero bits of exp. */
-+    i = 0;
-+    j = BIGNUM_INT_BITS - 1;
-+    while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
-+	j--;
-+	if (j < 0) {
-+	    i++;
-+	    j = BIGNUM_INT_BITS - 1;
-+	}
-+    }
-+
-+    /* Main computation */
-+    while (i < exp[0]) {
-+	while (j >= 0) {
-+	    internal_mul(a + mlen, a + mlen, b, mlen);
-+	    internal_mod(b, mlen * 2, m, mlen, NULL, 0);
-+	    if ((exp[exp[0] - i] & (1 << j)) != 0) {
-+		internal_mul(b + mlen, n, a, mlen);
-+		internal_mod(a, mlen * 2, m, mlen, NULL, 0);
-+	    } else {
-+		BignumInt *t;
-+		t = a;
-+		a = b;
-+		b = t;
-+	    }
-+	    j--;
-+	}
-+	i++;
-+	j = BIGNUM_INT_BITS - 1;
-+    }
-+
-+    /* Fixup result in case the modulus was shifted */
-+    if (mshift) {
-+	for (i = mlen - 1; i < 2 * mlen - 1; i++)
-+	    a[i] =
-+		(a[i] << mshift) | (a[i + 1] >>
-+				    (BIGNUM_INT_BITS - mshift));
-+	a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
-+	internal_mod(a, mlen * 2, m, mlen, NULL, 0);
-+	for (i = 2 * mlen - 1; i >= mlen; i--)
-+	    a[i] =
-+		(a[i] >> mshift) | (a[i - 1] <<
-+				    (BIGNUM_INT_BITS - mshift));
-+    }
-+
-+    /* Copy result to buffer */
-+    result = newbn(mem_ctx, mod[0]);
-+    for (i = 0; i < mlen; i++)
-+	result[result[0] - i] = a[i + mlen];
-+    while (result[0] > 1 && result[result[0]] == 0)
-+	result[0]--;
-+
-+    /* Free temporary arrays */
-+    for (i = 0; i < 2 * mlen; i++)
-+	a[i] = 0;
-+    sfree(mem_ctx, a);
-+    for (i = 0; i < 2 * mlen; i++)
-+	b[i] = 0;
-+    sfree(mem_ctx, b);
-+    for (i = 0; i < mlen; i++)
-+	m[i] = 0;
-+    sfree(mem_ctx, m);
-+    for (i = 0; i < mlen; i++)
-+	n[i] = 0;
-+    sfree(mem_ctx, n);
-+
-+    freebn(mem_ctx, base);
-+
-+    return result;
-+}
-+
-+
-+#ifdef UNITTEST
-+
-+static __u32 dh_p[] = {
-+	96,
-+	0xFFFFFFFF,
-+	0xFFFFFFFF,
-+	0xA93AD2CA,
-+	0x4B82D120,
-+	0xE0FD108E,
-+	0x43DB5BFC,
-+	0x74E5AB31,
-+	0x08E24FA0,
-+	0xBAD946E2,
-+	0x770988C0,
-+	0x7A615D6C,
-+	0xBBE11757,
-+	0x177B200C,
-+	0x521F2B18,
-+	0x3EC86A64,
-+	0xD8760273,
-+	0xD98A0864,
-+	0xF12FFA06,
-+	0x1AD2EE6B,
-+	0xCEE3D226,
-+	0x4A25619D,
-+	0x1E8C94E0,
-+	0xDB0933D7,
-+	0xABF5AE8C,
-+	0xA6E1E4C7,
-+	0xB3970F85,
-+	0x5D060C7D,
-+	0x8AEA7157,
-+	0x58DBEF0A,
-+	0xECFB8504,
-+	0xDF1CBA64,
-+	0xA85521AB,
-+	0x04507A33,
-+	0xAD33170D,
-+	0x8AAAC42D,
-+	0x15728E5A,
-+	0x98FA0510,
-+	0x15D22618,
-+	0xEA956AE5,
-+	0x3995497C,
-+	0x95581718,
-+	0xDE2BCBF6,
-+	0x6F4C52C9,
-+	0xB5C55DF0,
-+	0xEC07A28F,
-+	0x9B2783A2,
-+	0x180E8603,
-+	0xE39E772C,
-+	0x2E36CE3B,
-+	0x32905E46,
-+	0xCA18217C,
-+	0xF1746C08,
-+	0x4ABC9804,
-+	0x670C354E,
-+	0x7096966D,
-+	0x9ED52907,
-+	0x208552BB,
-+	0x1C62F356,
-+	0xDCA3AD96,
-+	0x83655D23,
-+	0xFD24CF5F,
-+	0x69163FA8,
-+	0x1C55D39A,
-+	0x98DA4836,
-+	0xA163BF05,
-+	0xC2007CB8,
-+	0xECE45B3D,
-+	0x49286651,
-+	0x7C4B1FE6,
-+	0xAE9F2411,
-+	0x5A899FA5,
-+	0xEE386BFB,
-+	0xF406B7ED,
-+	0x0BFF5CB6,
-+	0xA637ED6B,
-+	0xF44C42E9,
-+	0x625E7EC6,
-+	0xE485B576,
-+	0x6D51C245,
-+	0x4FE1356D,
-+	0xF25F1437,
-+	0x302B0A6D,
-+	0xCD3A431B,
-+	0xEF9519B3,
-+	0x8E3404DD,
-+	0x514A0879,
-+	0x3B139B22,
-+	0x020BBEA6,
-+	0x8A67CC74,
-+	0x29024E08,
-+	0x80DC1CD1,
-+	0xC4C6628B,
-+	0x2168C234,
-+	0xC90FDAA2,
-+	0xFFFFFFFF,
-+	0xFFFFFFFF,
-+};
-+
-+static __u32 dh_a[] = {
-+	8,
-+	0xdf367516,
-+	0x86459caa,
-+	0xe2d459a4,
-+	0xd910dae0,
-+	0x8a8b5e37,
-+	0x67ab31c6,
-+	0xf0b55ea9,
-+	0x440051d6,
-+};
-+
-+static __u32 dh_b[] = {
-+	8,
-+	0xded92656,
-+	0xe07a048a,
-+	0x6fa452cd,
-+	0x2df89d30,
-+	0xc75f1b0f,
-+	0x8ce3578f,
-+	0x7980a324,
-+	0x5daec786,
-+};
-+
-+static __u32 dh_g[] = {
-+	1,
-+	2,
-+};
-+
-+int main(void)
-+{
-+	int i;
-+	__u32 *k;
-+	k = dwc_modpow(NULL, dh_g, dh_a, dh_p);
-+
-+	printf("\n\n");
-+	for (i=0; i<k[0]; i++) {
-+		__u32 word32 = k[k[0] - i];
-+		__u16 l = word32 & 0xffff;
-+		__u16 m = (word32 & 0xffff0000) >> 16;
-+		printf("%04x %04x ", m, l);
-+		if (!((i + 1)%13)) printf("\n");
-+	}
-+	printf("\n\n");
-+
-+	if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
-+		printf("PASS\n\n");
-+	}
-+	else {
-+		printf("FAIL\n\n");
-+	}
-+
-+}
-+
-+#endif /* UNITTEST */
-+
-+#endif /* CONFIG_MACH_IPMATE */
-+
-+#endif /*DWC_CRYPTOLIB */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_modpow.h
-@@ -0,0 +1,34 @@
-+/*
-+ * dwc_modpow.h
-+ * See dwc_modpow.c for license and changes
-+ */
-+#ifndef _DWC_MODPOW_H
-+#define _DWC_MODPOW_H
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * This file defines the module exponentiation function which is only used
-+ * internally by the DWC UWB modules for calculation of PKs during numeric
-+ * association.  The routine is taken from the PUTTY, an open source terminal
-+ * emulator.  The PUTTY License is preserved in the dwc_modpow.c file.
-+ *
-+ */
-+
-+typedef uint32_t BignumInt;
-+typedef uint64_t BignumDblInt;
-+typedef BignumInt *Bignum;
-+
-+/* Compute modular exponentiaion */
-+extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _LINUX_BIGNUM_H */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_notifier.c
-@@ -0,0 +1,319 @@
-+#ifdef DWC_NOTIFYLIB
-+
-+#include "dwc_notifier.h"
-+#include "dwc_list.h"
-+
-+typedef struct dwc_observer {
-+	void *observer;
-+	dwc_notifier_callback_t callback;
-+	void *data;
-+	char *notification;
-+	DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
-+} observer_t;
-+
-+DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
-+
-+typedef struct dwc_notifier {
-+	void *mem_ctx;
-+	void *object;
-+	struct observer_queue observers;
-+	DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
-+} notifier_t;
-+
-+DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
-+
-+typedef struct manager {
-+	void *mem_ctx;
-+	void *wkq_ctx;
-+	dwc_workq_t *wq;
-+//	dwc_mutex_t *mutex;
-+	struct notifier_queue notifiers;
-+} manager_t;
-+
-+static manager_t *manager = NULL;
-+
-+static int create_manager(void *mem_ctx, void *wkq_ctx)
-+{
-+	manager = dwc_alloc(mem_ctx, sizeof(manager_t));
-+	if (!manager) {
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	DWC_CIRCLEQ_INIT(&manager->notifiers);
-+
-+	manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ");
-+	if (!manager->wq) {
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	return 0;
-+}
-+
-+static void free_manager(void)
-+{
-+	dwc_workq_free(manager->wq);
-+
-+	/* All notifiers must have unregistered themselves before this module
-+	 * can be removed.  Hitting this assertion indicates a programmer
-+	 * error. */
-+	DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),
-+		   "Notification manager being freed before all notifiers have been removed");
-+	dwc_free(manager->mem_ctx, manager);
-+}
-+
-+#ifdef DEBUG
-+static void dump_manager(void)
-+{
-+	notifier_t *n;
-+	observer_t *o;
-+
-+	DWC_ASSERT(manager, "Notification manager not found");
-+
-+	DWC_DEBUG("List of all notifiers and observers:\n");
-+	DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
-+		DWC_DEBUG("Notifier %p has observers:\n", n->object);
-+		DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
-+			DWC_DEBUG("    %p watching %s\n", o->observer, o->notification);
-+		}
-+	}
-+}
-+#else
-+#define dump_manager(...)
-+#endif
-+
-+static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,
-+				  dwc_notifier_callback_t callback, void *data)
-+{
-+	observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));
-+
-+	if (!new_observer) {
-+		return NULL;
-+	}
-+
-+	DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
-+	new_observer->observer = observer;
-+	new_observer->notification = notification;
-+	new_observer->callback = callback;
-+	new_observer->data = data;
-+	return new_observer;
-+}
-+
-+static void free_observer(void *mem_ctx, observer_t *observer)
-+{
-+	dwc_free(mem_ctx, observer);
-+}
-+
-+static notifier_t *alloc_notifier(void *mem_ctx, void *object)
-+{
-+	notifier_t *notifier;
-+
-+	if (!object) {
-+		return NULL;
-+	}
-+
-+	notifier = dwc_alloc(mem_ctx, sizeof(notifier_t));
-+	if (!notifier) {
-+		return NULL;
-+	}
-+
-+	DWC_CIRCLEQ_INIT(&notifier->observers);
-+	DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
-+
-+	notifier->mem_ctx = mem_ctx;
-+	notifier->object = object;
-+	return notifier;
-+}
-+
-+static void free_notifier(notifier_t *notifier)
-+{
-+	observer_t *observer;
-+
-+	DWC_CIRCLEQ_FOREACH(observer, &notifier->observers, list_entry) {
-+		free_observer(notifier->mem_ctx, observer);
-+	}
-+
-+	dwc_free(notifier->mem_ctx, notifier);
-+}
-+
-+static notifier_t *find_notifier(void *object)
-+{
-+	notifier_t *notifier;
-+
-+	DWC_ASSERT(manager, "Notification manager not found");
-+
-+	if (!object) {
-+		return NULL;
-+	}
-+
-+	DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
-+		if (notifier->object == object) {
-+			return notifier;
-+		}
-+	}
-+
-+	return NULL;
-+}
-+
-+int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)
-+{
-+	return create_manager(mem_ctx, wkq_ctx);
-+}
-+
-+void dwc_free_notification_manager(void)
-+{
-+	free_manager();
-+}
-+
-+dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)
-+{
-+	notifier_t *notifier;
-+
-+	DWC_ASSERT(manager, "Notification manager not found");
-+
-+	notifier = find_notifier(object);
-+	if (notifier) {
-+		DWC_ERROR("Notifier %p is already registered\n", object);
-+		return NULL;
-+	}
-+
-+	notifier = alloc_notifier(mem_ctx, object);
-+	if (!notifier) {
-+		return NULL;
-+	}
-+
-+	DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
-+
-+	DWC_INFO("Notifier %p registered", object);
-+	dump_manager();
-+
-+	return notifier;
-+}
-+
-+void dwc_unregister_notifier(dwc_notifier_t *notifier)
-+{
-+	DWC_ASSERT(manager, "Notification manager not found");
-+
-+	if (!DWC_CIRCLEQ_EMPTY(&notifier->observers)) {
-+		observer_t *o;
-+
-+		DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object);
-+		DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
-+			DWC_DEBUGC("    %p watching %s\n", o->observer, o->notification);
-+		}
-+
-+		DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&notifier->observers),
-+			   "Notifier %p has active observers when removing", notifier);
-+	}
-+
-+	DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
-+	free_notifier(notifier);
-+
-+	DWC_INFO("Notifier unregistered");
-+	dump_manager();
-+}
-+
-+/* Add an observer to observe the notifier for a particular state, event, or notification. */
-+int dwc_add_observer(void *observer, void *object, char *notification,
-+		     dwc_notifier_callback_t callback, void *data)
-+{
-+	notifier_t *notifier = find_notifier(object);
-+	observer_t *new_observer;
-+
-+	if (!notifier) {
-+		DWC_ERROR("Notifier %p is not found when adding observer\n", object);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);
-+	if (!new_observer) {
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	DWC_CIRCLEQ_INSERT_TAIL(&notifier->observers, new_observer, list_entry);
-+
-+	DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
-+		 observer, object, notification, callback, data);
-+
-+	dump_manager();
-+	return 0;
-+}
-+
-+int dwc_remove_observer(void *observer)
-+{
-+	notifier_t *n;
-+
-+	DWC_ASSERT(manager, "Notification manager not found");
-+
-+	DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
-+		observer_t *o;
-+		observer_t *o2;
-+
-+		DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
-+			if (o->observer == observer) {
-+				DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
-+				DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
-+					 o->observer, n->object, o->notification);
-+				free_observer(n->mem_ctx, o);
-+			}
-+		}
-+	}
-+
-+	dump_manager();
-+	return 0;
-+}
-+
-+typedef struct callback_data {
-+	void *mem_ctx;
-+	dwc_notifier_callback_t cb;
-+	void *observer;
-+	void *data;
-+	void *object;
-+	char *notification;
-+	void *notification_data;
-+} cb_data_t;
-+
-+static void cb_task(void *data)
-+{
-+	cb_data_t *cb = (cb_data_t *)data;
-+
-+	cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
-+	dwc_free(cb->mem_ctx, cb);
-+}
-+
-+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
-+{
-+	observer_t *o;
-+
-+	DWC_ASSERT(manager, "Notification manager not found");
-+
-+	DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
-+		int len = DWC_STRLEN(notification);
-+
-+		if (DWC_STRLEN(o->notification) != len) {
-+			continue;
-+		}
-+
-+		if (DWC_STRNCMP(o->notification, notification, len) == 0) {
-+			cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));
-+
-+			if (!cb_data) {
-+				DWC_ERROR("Failed to allocate callback data\n");
-+				return;
-+			}
-+
-+			cb_data->mem_ctx = notifier->mem_ctx;
-+			cb_data->cb = o->callback;
-+			cb_data->observer = o->observer;
-+			cb_data->data = o->data;
-+			cb_data->object = notifier->object;
-+			cb_data->notification = notification;
-+			cb_data->notification_data = notification_data;
-+			DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification);
-+			DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
-+					   "Notify callback from %p for Notification %s, to observer %p",
-+					   cb_data->object, notification, cb_data->observer);
-+		}
-+	}
-+}
-+
-+#endif	/* DWC_NOTIFYLIB */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_notifier.h
-@@ -0,0 +1,122 @@
-+
-+#ifndef __DWC_NOTIFIER_H__
-+#define __DWC_NOTIFIER_H__
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ *
-+ * A simple implementation of the Observer pattern.  Any "module" can
-+ * register as an observer or notifier.  The notion of "module" is abstract and
-+ * can mean anything used to identify either an observer or notifier.  Usually
-+ * it will be a pointer to a data structure which contains some state, ie an
-+ * object.
-+ *
-+ * Before any notifiers can be added, the global notification manager must be
-+ * brought up with dwc_alloc_notification_manager().
-+ * dwc_free_notification_manager() will bring it down and free all resources.
-+ * These would typically be called upon module load and unload.  The
-+ * notification manager is a single global instance that handles all registered
-+ * observable modules and observers so this should be done only once.
-+ *
-+ * A module can be observable by using Notifications to publicize some general
-+ * information about it's state or operation.  It does not care who listens, or
-+ * even if anyone listens, or what they do with the information.  The observable
-+ * modules do not need to know any information about it's observers or their
-+ * interface, or their state or data.
-+ *
-+ * Any module can register to emit Notifications.  It should publish a list of
-+ * notifications that it can emit and their behavior, such as when they will get
-+ * triggered, and what information will be provided to the observer.  Then it
-+ * should register itself as an observable module. See dwc_register_notifier().
-+ *
-+ * Any module can observe any observable, registered module, provided it has a
-+ * handle to the other module and knows what notifications to observe.  See
-+ * dwc_add_observer().
-+ *
-+ * A function of type dwc_notifier_callback_t is called whenever a notification
-+ * is triggered with one or more observers observing it.  This function is
-+ * called in it's own process so it may sleep or block if needed.  It is
-+ * guaranteed to be called sometime after the notification has occurred and will
-+ * be called once per each time the notification is triggered.  It will NOT be
-+ * called in the same process context used to trigger the notification.
-+ *
-+ * @section Limitiations
-+ *
-+ * Keep in mind that Notifications that can be triggered in rapid sucession may
-+ * schedule too many processes too handle.  Be aware of this limitation when
-+ * designing to use notifications, and only add notifications for appropriate
-+ * observable information.
-+ *
-+ * Also Notification callbacks are not synchronous.  If you need to synchronize
-+ * the behavior between module/observer you must use other means.  And perhaps
-+ * that will mean Notifications are not the proper solution.
-+ */
-+
-+struct dwc_notifier;
-+typedef struct dwc_notifier dwc_notifier_t;
-+
-+/** The callback function must be of this type.
-+ *
-+ * @param object This is the object that is being observed.
-+ * @param notification This is the notification that was triggered.
-+ * @param observer This is the observer
-+ * @param notification_data This is notification-specific data that the notifier
-+ * has included in this notification.  The value of this should be published in
-+ * the documentation of the observable module with the notifications.
-+ * @param user_data This is any custom data that the observer provided when
-+ * adding itself as an observer to the notification. */
-+typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,
-+					void *notification_data, void *user_data);
-+
-+/** Brings up the notification manager. */
-+extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);
-+/** Brings down the notification manager. */
-+extern void dwc_free_notification_manager(void);
-+
-+/** This function registers an observable module.  A dwc_notifier_t object is
-+ * returned to the observable module.  This is an opaque object that is used by
-+ * the observable module to trigger notifications.  This object should only be
-+ * accessible to functions that are authorized to trigger notifications for this
-+ * module.  Observers do not need this object. */
-+extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);
-+
-+/** This function unregisters an observable module.  All observers have to be
-+ * removed prior to unregistration. */
-+extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
-+
-+/** Add a module as an observer to the observable module.  The observable module
-+ * needs to have previously registered with the notification manager.
-+ *
-+ * @param observer The observer module
-+ * @param object The module to observe
-+ * @param notification The notification to observe
-+ * @param callback The callback function to call
-+ * @param user_data Any additional user data to pass into the callback function */
-+extern int dwc_add_observer(void *observer, void *object, char *notification,
-+			    dwc_notifier_callback_t callback, void *user_data);
-+
-+/** Removes the specified observer from all notifications that it is currently
-+ * observing. */
-+extern int dwc_remove_observer(void *observer);
-+
-+/** This function triggers a Notification.  It should be called by the
-+ * observable module, or any module or library which the observable module
-+ * allows to trigger notification on it's behalf.  Such as the dwc_cc_t.
-+ *
-+ * dwc_notify is a non-blocking function.  Callbacks are scheduled called in
-+ * their own process context for each trigger.  Callbacks can be blocking.
-+ * dwc_notify can be called from interrupt context if needed.
-+ *
-+ */
-+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* __DWC_NOTIFIER_H__ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/dwc_os.h
-@@ -0,0 +1,1276 @@
-+/* =========================================================================
-+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
-+ * $Revision: #14 $
-+ * $Date: 2010/11/04 $
-+ * $Change: 1621695 $
-+ *
-+ * Synopsys Portability Library Software and documentation
-+ * (hereinafter, "Software") is an Unsupported proprietary work of
-+ * Synopsys, Inc. unless otherwise expressly agreed to in writing
-+ * between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product
-+ * under any End User Software License Agreement or Agreement for
-+ * Licensed Product with Synopsys or any supplement thereto. You are
-+ * permitted to use and redistribute this Software in source and binary
-+ * forms, with or without modification, provided that redistributions
-+ * of source code must retain this notice. You may not view, use,
-+ * disclose, copy or distribute this file or any information contained
-+ * herein except pursuant to this license grant from Synopsys. If you
-+ * do not agree with this notice, including the disclaimer below, then
-+ * you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
-+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
-+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================= */
-+#ifndef _DWC_OS_H_
-+#define _DWC_OS_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/** @file
-+ *
-+ * DWC portability library, low level os-wrapper functions
-+ *
-+ */
-+
-+/* These basic types need to be defined by some OS header file or custom header
-+ * file for your specific target architecture.
-+ *
-+ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
-+ *
-+ * Any custom or alternate header file must be added and enabled here.
-+ */
-+
-+#ifdef DWC_LINUX
-+# include <linux/types.h>
-+# ifdef CONFIG_DEBUG_MUTEXES
-+#  include <linux/mutex.h>
-+# endif
-+# include <linux/spinlock.h>
-+# include <linux/errno.h>
-+# include <stdarg.h>
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+# include <os_dep.h>
-+#endif
-+
-+
-+/** @name Primitive Types and Values */
-+
-+/** We define a boolean type for consistency.  Can be either YES or NO */
-+typedef uint8_t dwc_bool_t;
-+#define YES  1
-+#define NO   0
-+
-+#ifdef DWC_LINUX
-+
-+/** @name Error Codes */
-+#define DWC_E_INVALID		EINVAL
-+#define DWC_E_NO_MEMORY		ENOMEM
-+#define DWC_E_NO_DEVICE		ENODEV
-+#define DWC_E_NOT_SUPPORTED	EOPNOTSUPP
-+#define DWC_E_TIMEOUT		ETIMEDOUT
-+#define DWC_E_BUSY		EBUSY
-+#define DWC_E_AGAIN		EAGAIN
-+#define DWC_E_RESTART		ERESTART
-+#define DWC_E_ABORT		ECONNABORTED
-+#define DWC_E_SHUTDOWN		ESHUTDOWN
-+#define DWC_E_NO_DATA		ENODATA
-+#define DWC_E_DISCONNECT	ECONNRESET
-+#define DWC_E_UNKNOWN		EINVAL
-+#define DWC_E_NO_STREAM_RES	ENOSR
-+#define DWC_E_COMMUNICATION	ECOMM
-+#define DWC_E_OVERFLOW		EOVERFLOW
-+#define DWC_E_PROTOCOL		EPROTO
-+#define DWC_E_IN_PROGRESS	EINPROGRESS
-+#define DWC_E_PIPE		EPIPE
-+#define DWC_E_IO		EIO
-+#define DWC_E_NO_SPACE		ENOSPC
-+
-+#else
-+
-+/** @name Error Codes */
-+#define DWC_E_INVALID		1001
-+#define DWC_E_NO_MEMORY		1002
-+#define DWC_E_NO_DEVICE		1003
-+#define DWC_E_NOT_SUPPORTED	1004
-+#define DWC_E_TIMEOUT		1005
-+#define DWC_E_BUSY		1006
-+#define DWC_E_AGAIN		1007
-+#define DWC_E_RESTART		1008
-+#define DWC_E_ABORT		1009
-+#define DWC_E_SHUTDOWN		1010
-+#define DWC_E_NO_DATA		1011
-+#define DWC_E_DISCONNECT	2000
-+#define DWC_E_UNKNOWN		3000
-+#define DWC_E_NO_STREAM_RES	4001
-+#define DWC_E_COMMUNICATION	4002
-+#define DWC_E_OVERFLOW		4003
-+#define DWC_E_PROTOCOL		4004
-+#define DWC_E_IN_PROGRESS	4005
-+#define DWC_E_PIPE		4006
-+#define DWC_E_IO		4007
-+#define DWC_E_NO_SPACE		4008
-+
-+#endif
-+
-+
-+/** @name Tracing/Logging Functions
-+ *
-+ * These function provide the capability to add tracing, debugging, and error
-+ * messages, as well exceptions as assertions.  The WUDEV uses these
-+ * extensively.  These could be logged to the main console, the serial port, an
-+ * internal buffer, etc.  These functions could also be no-op if they are too
-+ * expensive on your system.  By default undefining the DEBUG macro already
-+ * no-ops some of these functions. */
-+
-+/** Returns non-zero if in interrupt context. */
-+extern dwc_bool_t DWC_IN_IRQ(void);
-+#define dwc_in_irq DWC_IN_IRQ
-+
-+/** Returns "IRQ" if DWC_IN_IRQ is true. */
-+static inline char *dwc_irq(void) {
-+	return DWC_IN_IRQ() ? "IRQ" : "";
-+}
-+
-+/** Returns non-zero if in bottom-half context. */
-+extern dwc_bool_t DWC_IN_BH(void);
-+#define dwc_in_bh DWC_IN_BH
-+
-+/** Returns "BH" if DWC_IN_BH is true. */
-+static inline char *dwc_bh(void) {
-+	return DWC_IN_BH() ? "BH" : "";
-+}
-+
-+/**
-+ * A vprintf() clone.  Just call vprintf if you've got it.
-+ */
-+extern void DWC_VPRINTF(char *format, va_list args);
-+#define dwc_vprintf DWC_VPRINTF
-+
-+/**
-+ * A vsnprintf() clone.  Just call vprintf if you've got it.
-+ */
-+extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
-+#define dwc_vsnprintf DWC_VSNPRINTF
-+
-+/**
-+ * printf() clone.  Just call printf if you've go it.
-+ */
-+extern void DWC_PRINTF(char *format, ...)
-+/* This provides compiler level static checking of the parameters if you're
-+ * using GCC. */
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 1, 2)));
-+#else
-+	;
-+#endif
-+#define dwc_printf DWC_PRINTF
-+
-+/**
-+ * sprintf() clone.  Just call sprintf if you've got it.
-+ */
-+extern int DWC_SPRINTF(char *string, char *format, ...)
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 2, 3)));
-+#else
-+	;
-+#endif
-+#define dwc_sprintf DWC_SPRINTF
-+
-+/**
-+ * snprintf() clone.  Just call snprintf if you've got it.
-+ */
-+extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 3, 4)));
-+#else
-+	;
-+#endif
-+#define dwc_snprintf DWC_SNPRINTF
-+
-+/**
-+ * Prints a WARNING message.  On systems that don't differentiate between
-+ * warnings and regular log messages, just print it.  Indicates that something
-+ * may be wrong with the driver.  Works like printf().
-+ *
-+ * Use the DWC_WARN macro to call this function.
-+ */
-+extern void __DWC_WARN(char *format, ...)
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 1, 2)));
-+#else
-+	;
-+#endif
-+
-+/**
-+ * Prints an error message.  On systems that don't differentiate between errors
-+ * and regular log messages, just print it.  Indicates that something went wrong
-+ * with the driver.  Works like printf().
-+ *
-+ * Use the DWC_ERROR macro to call this function.
-+ */
-+extern void __DWC_ERROR(char *format, ...)
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 1, 2)));
-+#else
-+	;
-+#endif
-+
-+/**
-+ * Prints an exception error message and takes some user-defined action such as
-+ * print out a backtrace or trigger a breakpoint.  Indicates that something went
-+ * abnormally wrong with the driver such as programmer error, or other
-+ * exceptional condition.  It should not be ignored so even on systems without
-+ * printing capability, some action should be taken to notify the developer of
-+ * it.  Works like printf().
-+ */
-+extern void DWC_EXCEPTION(char *format, ...)
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 1, 2)));
-+#else
-+	;
-+#endif
-+#define dwc_exception DWC_EXCEPTION
-+
-+#ifndef DWC_OTG_DEBUG_LEV
-+#define DWC_OTG_DEBUG_LEV 0
-+#endif
-+
-+#ifdef DEBUG
-+/**
-+ * Prints out a debug message.  Used for logging/trace messages.
-+ *
-+ * Use the DWC_DEBUG macro to call this function
-+ */
-+extern void __DWC_DEBUG(char *format, ...)
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 1, 2)));
-+#else
-+	;
-+#endif
-+#else
-+#define __DWC_DEBUG printk
-+#endif
-+
-+/**
-+ * Prints out a Debug message.
-+ */
-+#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
-+						 __func__, dwc_irq(), ## _args)
-+#define dwc_debug DWC_DEBUG
-+/**
-+ * Prints out a Debug message if enabled at compile time.
-+ */
-+#if DWC_OTG_DEBUG_LEV > 0
-+#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
-+#else
-+#define DWC_DEBUGC(_format, _args...)
-+#endif
-+#define dwc_debugc DWC_DEBUGC
-+/**
-+ * Prints out an informative message.
-+ */
-+#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
-+					       dwc_irq(), ## _args)
-+#define dwc_info DWC_INFO
-+/**
-+ * Prints out an informative message if enabled at compile time.
-+ */
-+#if DWC_OTG_DEBUG_LEV > 1
-+#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
-+#else
-+#define DWC_INFOC(_format, _args...)
-+#endif
-+#define dwc_infoc DWC_INFOC
-+/**
-+ * Prints out a warning message.
-+ */
-+#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
-+					dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_warn DWC_WARN
-+/**
-+ * Prints out an error message.
-+ */
-+#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
-+					dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_error DWC_ERROR
-+
-+#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
-+						dwc_irq(), __func__, __LINE__, ## _args)
-+#define dwc_proto_error DWC_PROTO_ERROR
-+
-+#ifdef DEBUG
-+/** Prints out a exception error message if the _expr expression fails.  Disabled
-+ * if DEBUG is not enabled. */
-+#define DWC_ASSERT(_expr, _format, _args...) do { \
-+	if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
-+				      __FILE__, __LINE__, ## _args); } \
-+	} while (0)
-+#else
-+#define DWC_ASSERT(_x...)
-+#endif
-+#define dwc_assert DWC_ASSERT
-+
-+
-+/** @name Byte Ordering
-+ * The following functions are for conversions between processor's byte ordering
-+ * and specific ordering you want.
-+ */
-+
-+/** Converts 32 bit data in CPU byte ordering to little endian. */
-+extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
-+#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
-+
-+/** Converts 32 bit data in CPU byte orderint to big endian. */
-+extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
-+#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
-+
-+/** Converts 32 bit little endian data to CPU byte ordering. */
-+extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
-+#define dwc_le32_to_cpu DWC_LE32_TO_CPU
-+
-+/** Converts 32 bit big endian data to CPU byte ordering. */
-+extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
-+#define dwc_be32_to_cpu DWC_BE32_TO_CPU
-+
-+/** Converts 16 bit data in CPU byte ordering to little endian. */
-+extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
-+#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
-+
-+/** Converts 16 bit data in CPU byte orderint to big endian. */
-+extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
-+#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
-+
-+/** Converts 16 bit little endian data to CPU byte ordering. */
-+extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
-+#define dwc_le16_to_cpu DWC_LE16_TO_CPU
-+
-+/** Converts 16 bit bi endian data to CPU byte ordering. */
-+extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
-+#define dwc_be16_to_cpu DWC_BE16_TO_CPU
-+
-+
-+/** @name Register Read/Write
-+ *
-+ * The following six functions should be implemented to read/write registers of
-+ * 32-bit and 64-bit sizes.  All modules use this to read/write register values.
-+ * The reg value is a pointer to the register calculated from the void *base
-+ * variable passed into the driver when it is started.  */
-+
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any extra parameters for register read/write, so we
-+ * just throw away the IO context parameter.
-+ */
-+/** Reads the content of a 32-bit register. */
-+extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
-+#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
-+
-+/** Reads the content of a 64-bit register. */
-+extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
-+#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
-+
-+/** Writes to a 32-bit register. */
-+extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
-+#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
-+
-+/** Writes to a 64-bit register. */
-+extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
-+#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
-+
-+/**
-+ * Modify bit values in a register.  Using the
-+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
-+ */
-+extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
-+#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
-+extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
-+#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
-+
-+#endif	/* DWC_LINUX */
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+typedef struct dwc_ioctx {
-+	struct device *dev;
-+	bus_space_tag_t iot;
-+	bus_space_handle_t ioh;
-+} dwc_ioctx_t;
-+
-+/** BSD needs two extra parameters for register read/write, so we pass
-+ * them in using the IO context parameter.
-+ */
-+/** Reads the content of a 32-bit register. */
-+extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
-+#define dwc_read_reg32 DWC_READ_REG32
-+
-+/** Reads the content of a 64-bit register. */
-+extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
-+#define dwc_read_reg64 DWC_READ_REG64
-+
-+/** Writes to a 32-bit register. */
-+extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
-+#define dwc_write_reg32 DWC_WRITE_REG32
-+
-+/** Writes to a 64-bit register. */
-+extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
-+#define dwc_write_reg64 DWC_WRITE_REG64
-+
-+/**
-+ * Modify bit values in a register.  Using the
-+ * algorithm: (reg_contents & ~clear_mask) | set_mask.
-+ */
-+extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
-+#define dwc_modify_reg32 DWC_MODIFY_REG32
-+extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
-+#define dwc_modify_reg64 DWC_MODIFY_REG64
-+
-+#endif	/* DWC_FREEBSD || DWC_NETBSD */
-+
-+/** @cond */
-+
-+/** @name Some convenience MACROS used internally.  Define DWC_DEBUG_REGS to log the
-+ * register writes. */
-+
-+#ifdef DWC_LINUX
-+
-+# ifdef DWC_DEBUG_REGS
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
-+	return DWC_READ_REG32(&container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
-+	DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
-+		  &(((uint32_t*)container->regs->_reg)[num]), data); \
-+	DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(_container_type *container) { \
-+	return DWC_READ_REG32(&container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
-+	DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
-+	DWC_WRITE_REG32(&container->regs->_reg, data); \
-+}
-+
-+# else	/* DWC_DEBUG_REGS */
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
-+	return DWC_READ_REG32(&container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
-+	DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(_container_type *container) { \
-+	return DWC_READ_REG32(&container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
-+	DWC_WRITE_REG32(&container->regs->_reg, data); \
-+}
-+
-+# endif	/* DWC_DEBUG_REGS */
-+
-+#endif	/* DWC_LINUX */
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+
-+# ifdef DWC_DEBUG_REGS
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
-+	return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
-+	DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
-+		  &(((uint32_t*)container->regs->_reg)[num]), data); \
-+	DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
-+	return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
-+	DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
-+	DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
-+}
-+
-+# else	/* DWC_DEBUG_REGS */
-+
-+#define dwc_define_read_write_reg_n(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
-+	return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
-+} \
-+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
-+	DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
-+}
-+
-+#define dwc_define_read_write_reg(_reg,_container_type) \
-+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
-+	return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
-+} \
-+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
-+	DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
-+}
-+
-+# endif	/* DWC_DEBUG_REGS */
-+
-+#endif	/* DWC_FREEBSD || DWC_NETBSD */
-+
-+/** @endcond */
-+
-+
-+#ifdef DWC_CRYPTOLIB
-+/** @name Crypto Functions
-+ *
-+ * These are the low-level cryptographic functions used by the driver. */
-+
-+/** Perform AES CBC */
-+extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
-+#define dwc_aes_cbc DWC_AES_CBC
-+
-+/** Fill the provided buffer with random bytes.  These should be cryptographic grade random numbers. */
-+extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
-+#define dwc_random_bytes DWC_RANDOM_BYTES
-+
-+/** Perform the SHA-256 hash function */
-+extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
-+#define dwc_sha256 DWC_SHA256
-+
-+/** Calculated the HMAC-SHA256 */
-+extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
-+#define dwc_hmac_sha256 DWC_HMAC_SHA256
-+
-+#endif	/* DWC_CRYPTOLIB */
-+
-+
-+/** @name Memory Allocation
-+ *
-+ * These function provide access to memory allocation.  There are only 2 DMA
-+ * functions and 3 Regular memory functions that need to be implemented.  None
-+ * of the memory debugging routines need to be implemented.  The allocation
-+ * routines all ZERO the contents of the memory.
-+ *
-+ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
-+ * This checks for memory leaks, keeping track of alloc/free pairs.  It also
-+ * keeps track of how much memory the driver is using at any given time. */
-+
-+#define DWC_PAGE_SIZE 4096
-+#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
-+#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
-+
-+#define DWC_INVALID_DMA_ADDR 0x0
-+
-+#ifdef DWC_LINUX
-+/** Type for a DMA address */
-+typedef dma_addr_t dwc_dma_t;
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+typedef bus_addr_t dwc_dma_t;
-+#endif
-+
-+#ifdef DWC_FREEBSD
-+typedef struct dwc_dmactx {
-+	struct device *dev;
-+	bus_dma_tag_t dma_tag;
-+	bus_dmamap_t dma_map;
-+	bus_addr_t dma_paddr;
-+	void *dma_vaddr;
-+} dwc_dmactx_t;
-+#endif
-+
-+#ifdef DWC_NETBSD
-+typedef struct dwc_dmactx {
-+	struct device *dev;
-+	bus_dma_tag_t dma_tag;
-+	bus_dmamap_t dma_map;
-+	bus_dma_segment_t segs[1];
-+	int nsegs;
-+	bus_addr_t dma_paddr;
-+	void *dma_vaddr;
-+} dwc_dmactx_t;
-+#endif
-+
-+/* @todo these functions will be added in the future */
-+#if 0
-+/**
-+ * Creates a DMA pool from which you can allocate DMA buffers.  Buffers
-+ * allocated from this pool will be guaranteed to meet the size, alignment, and
-+ * boundary requirements specified.
-+ *
-+ * @param[in] size Specifies the size of the buffers that will be allocated from
-+ * this pool.
-+ * @param[in] align Specifies the byte alignment requirements of the buffers
-+ * allocated from this pool.  Must be a power of 2.
-+ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
-+ * this pool must not cross.
-+ *
-+ * @returns A pointer to an internal opaque structure which is not to be
-+ * accessed outside of these library functions.  Use this handle to specify
-+ * which pools to allocate/free DMA buffers from and also to destroy the pool,
-+ * when you are done with it.
-+ */
-+extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
-+
-+/**
-+ * Destroy a DMA pool.  All buffers allocated from that pool must be freed first.
-+ */
-+extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
-+
-+/**
-+ * Allocate a buffer from the specified DMA pool and zeros its contents.
-+ */
-+extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
-+
-+/**
-+ * Free a previously allocated buffer from the DMA pool.
-+ */
-+extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
-+#endif
-+
-+/** Allocates a DMA capable buffer and zeroes its contents. */
-+extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
-+
-+/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
-+extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
-+
-+/** Frees a previously allocated buffer. */
-+extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
-+
-+/** Allocates a block of memory and zeroes its contents. */
-+extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
-+
-+/** Allocates a block of memory and zeroes its contents, in an atomic manner
-+ * which can be used inside interrupt context.  The size should be sufficiently
-+ * small, a few KB at most, such that failures are not likely to occur.  Can just call
-+ * __DWC_ALLOC if it is atomic. */
-+extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
-+
-+/** Frees a previously allocated buffer. */
-+extern void __DWC_FREE(void *mem_ctx, void *addr);
-+
-+#ifndef DWC_DEBUG_MEMORY
-+
-+#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
-+#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
-+#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
-+
-+# ifdef DWC_LINUX
-+#define DWC_DMA_ALLOC(_dev, _size_, _dma_) __DWC_DMA_ALLOC(_dev, _size_, _dma_)
-+#define DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_) __DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_)
-+#define DWC_DMA_FREE(_dev, _size_,_virt_, _dma_) __DWC_DMA_FREE(_dev, _size_, _virt_, _dma_)
-+# endif
-+
-+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
-+#define DWC_DMA_FREE __DWC_DMA_FREE
-+# endif
-+extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
-+
-+#else	/* DWC_DEBUG_MEMORY */
-+
-+extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
-+extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
-+extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
-+extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+				 char const *func, int line);
-+extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
-+				char const *func, int line);
-+extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
-+			       dwc_dma_t dma_addr, char const *func, int line);
-+
-+extern int dwc_memory_debug_start(void *mem_ctx);
-+extern void dwc_memory_debug_stop(void);
-+extern void dwc_memory_debug_report(void);
-+
-+#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
-+#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
-+							__func__, __LINE__)
-+#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
-+
-+# ifdef DWC_LINUX
-+#define DWC_DMA_ALLOC(_dev, _size_, _dma_) \
-+	dwc_dma_alloc_debug(_dev, _size_, _dma_, __func__, __LINE__)
-+#define DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_) \
-+	dwc_dma_alloc_atomic_debug(_dev, _size_, _dma_, __func__, __LINE__)
-+#define DWC_DMA_FREE(_dev, _size_, _virt_, _dma_) \
-+	dwc_dma_free_debug(_dev, _size_, _virt_, _dma_, __func__, __LINE__)
-+# endif
-+
-+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
-+						_dma_, __func__, __LINE__)
-+#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
-+						 _virt_, _dma_, __func__, __LINE__)
-+# endif
-+
-+#endif /* DWC_DEBUG_MEMORY */
-+
-+#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
-+#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
-+#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
-+
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
-+ * just throw away the DMA context parameter.
-+ */
-+#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
-+#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
-+#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+/** BSD needs several extra parameters for DMA buffer allocation, so we pass
-+ * them in using the DMA context parameter.
-+ */
-+#define dwc_dma_alloc DWC_DMA_ALLOC
-+#define dwc_dma_free DWC_DMA_FREE
-+#endif
-+
-+
-+/** @name Memory and String Processing */
-+
-+/** memset() clone */
-+extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
-+#define dwc_memset DWC_MEMSET
-+
-+/** memcpy() clone */
-+extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
-+#define dwc_memcpy DWC_MEMCPY
-+
-+/** memmove() clone */
-+extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
-+#define dwc_memmove DWC_MEMMOVE
-+
-+/** memcmp() clone */
-+extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
-+#define dwc_memcmp DWC_MEMCMP
-+
-+/** strcmp() clone */
-+extern int DWC_STRCMP(void *s1, void *s2);
-+#define dwc_strcmp DWC_STRCMP
-+
-+/** strncmp() clone */
-+extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
-+#define dwc_strncmp DWC_STRNCMP
-+
-+/** strlen() clone, for NULL terminated ASCII strings */
-+extern int DWC_STRLEN(char const *str);
-+#define dwc_strlen DWC_STRLEN
-+
-+/** strcpy() clone, for NULL terminated ASCII strings */
-+extern char *DWC_STRCPY(char *to, const char *from);
-+#define dwc_strcpy DWC_STRCPY
-+
-+/** strdup() clone.  If you wish to use memory allocation debugging, this
-+ * implementation of strdup should use the DWC_* memory routines instead of
-+ * calling a predefined strdup.  Otherwise the memory allocated by this routine
-+ * will not be seen by the debugging routines. */
-+extern char *DWC_STRDUP(char const *str);
-+#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
-+
-+/** NOT an atoi() clone.  Read the description carefully.  Returns an integer
-+ * converted from the string str in base 10 unless the string begins with a "0x"
-+ * in which case it is base 16.  String must be a NULL terminated sequence of
-+ * ASCII characters and may optionally begin with whitespace, a + or -, and a
-+ * "0x" prefix if base 16.  The remaining characters must be valid digits for
-+ * the number and end with a NULL character.  If any invalid characters are
-+ * encountered or it returns with a negative error code and the results of the
-+ * conversion are undefined.  On sucess it returns 0.  Overflow conditions are
-+ * undefined.  An example implementation using atoi() can be referenced from the
-+ * Linux implementation. */
-+extern int DWC_ATOI(const char *str, int32_t *value);
-+#define dwc_atoi DWC_ATOI
-+
-+/** Same as above but for unsigned. */
-+extern int DWC_ATOUI(const char *str, uint32_t *value);
-+#define dwc_atoui DWC_ATOUI
-+
-+#ifdef DWC_UTFLIB
-+/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
-+extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
-+#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
-+#endif
-+
-+
-+/** @name Wait queues
-+ *
-+ * Wait queues provide a means of synchronizing between threads or processes.  A
-+ * process can block on a waitq if some condition is not true, waiting for it to
-+ * become true.  When the waitq is triggered all waiting process will get
-+ * unblocked and the condition will be check again.  Waitqs should be triggered
-+ * every time a condition can potentially change.*/
-+struct dwc_waitq;
-+
-+/** Type for a waitq */
-+typedef struct dwc_waitq dwc_waitq_t;
-+
-+/** The type of waitq condition callback function.  This is called every time
-+ * condition is evaluated. */
-+typedef int (*dwc_waitq_condition_t)(void *data);
-+
-+/** Allocate a waitq */
-+extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
-+#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
-+
-+/** Free a waitq */
-+extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
-+#define dwc_waitq_free DWC_WAITQ_FREE
-+
-+/** Check the condition and if it is false, block on the waitq.  When unblocked, check the
-+ * condition again.  The function returns when the condition becomes true.  The return value
-+ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
-+extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
-+#define dwc_waitq_wait DWC_WAITQ_WAIT
-+
-+/** Check the condition and if it is false, block on the waitq.  When unblocked,
-+ * check the condition again.  The function returns when the condition become
-+ * true or the timeout has passed.  The return value is 0 on condition true or
-+ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
-+ * error. */
-+extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
-+				      void *data, int32_t msecs);
-+#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
-+
-+/** Trigger a waitq, unblocking all processes.  This should be called whenever a condition
-+ * has potentially changed. */
-+extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
-+#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
-+
-+/** Unblock all processes waiting on the waitq with an ABORTED result. */
-+extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
-+#define dwc_waitq_abort DWC_WAITQ_ABORT
-+
-+
-+/** @name Threads
-+ *
-+ * A thread must be explicitly stopped.  It must check DWC_THREAD_SHOULD_STOP
-+ * whenever it is woken up, and then return.  The DWC_THREAD_STOP function
-+ * returns the value from the thread.
-+ */
-+
-+struct dwc_thread;
-+
-+/** Type for a thread */
-+typedef struct dwc_thread dwc_thread_t;
-+
-+/** The thread function */
-+typedef int (*dwc_thread_function_t)(void *data);
-+
-+/** Create a thread and start it running the thread_function.  Returns a handle
-+ * to the thread */
-+extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
-+#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
-+
-+/** Stops a thread.  Return the value returned by the thread.  Or will return
-+ * DWC_ABORT if the thread never started. */
-+extern int DWC_THREAD_STOP(dwc_thread_t *thread);
-+#define dwc_thread_stop DWC_THREAD_STOP
-+
-+/** Signifies to the thread that it must stop. */
-+#ifdef DWC_LINUX
-+/* Linux doesn't need any parameters for kthread_should_stop() */
-+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
-+#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
-+
-+/* No thread_exit function in Linux */
-+#define dwc_thread_exit(_thrd_)
-+#endif
-+
-+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
-+/** BSD needs the thread pointer for kthread_suspend_check() */
-+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
-+#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
-+
-+/** The thread must call this to exit. */
-+extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
-+#define dwc_thread_exit DWC_THREAD_EXIT
-+#endif
-+
-+
-+/** @name Work queues
-+ *
-+ * Workqs are used to queue a callback function to be called at some later time,
-+ * in another thread. */
-+struct dwc_workq;
-+
-+/** Type for a workq */
-+typedef struct dwc_workq dwc_workq_t;
-+
-+/** The type of the callback function to be called. */
-+typedef void (*dwc_work_callback_t)(void *data);
-+
-+/** Allocate a workq */
-+extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
-+#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
-+
-+/** Free a workq.  All work must be completed before being freed. */
-+extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
-+#define dwc_workq_free DWC_WORKQ_FREE
-+
-+/** Schedule a callback on the workq, passing in data.  The function will be
-+ * scheduled at some later time. */
-+extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
-+			       void *data, char *format, ...)
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 4, 5)));
-+#else
-+	;
-+#endif
-+#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
-+
-+/** Schedule a callback on the workq, that will be called until at least
-+ * given number miliseconds have passed. */
-+extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
-+				       void *data, uint32_t time, char *format, ...)
-+#ifdef __GNUC__
-+	__attribute__ ((format(printf, 5, 6)));
-+#else
-+	;
-+#endif
-+#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
-+
-+/** The number of processes in the workq */
-+extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
-+#define dwc_workq_pending DWC_WORKQ_PENDING
-+
-+/** Blocks until all the work in the workq is complete or timed out.  Returns <
-+ * 0 on timeout. */
-+extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
-+#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
-+
-+
-+/** @name Tasklets
-+ *
-+ */
-+struct dwc_tasklet;
-+
-+/** Type for a tasklet */
-+typedef struct dwc_tasklet dwc_tasklet_t;
-+
-+/** The type of the callback function to be called */
-+typedef void (*dwc_tasklet_callback_t)(void *data);
-+
-+/** Allocates a tasklet */
-+extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
-+#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
-+
-+/** Frees a tasklet */
-+extern void DWC_TASK_FREE(dwc_tasklet_t *task);
-+#define dwc_task_free DWC_TASK_FREE
-+
-+/** Schedules a tasklet to run */
-+extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
-+#define dwc_task_schedule DWC_TASK_SCHEDULE
-+
-+extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);
-+#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE
-+
-+/** @name Timer
-+ *
-+ * Callbacks must be small and atomic.
-+ */
-+struct dwc_timer;
-+
-+/** Type for a timer */
-+typedef struct dwc_timer dwc_timer_t;
-+
-+/** The type of the callback function to be called */
-+typedef void (*dwc_timer_callback_t)(void *data);
-+
-+/** Allocates a timer */
-+extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
-+#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
-+
-+/** Frees a timer */
-+extern void DWC_TIMER_FREE(dwc_timer_t *timer);
-+#define dwc_timer_free DWC_TIMER_FREE
-+
-+/** Schedules the timer to run at time ms from now.  And will repeat at every
-+ * repeat_interval msec therafter
-+ *
-+ * Modifies a timer that is still awaiting execution to a new expiration time.
-+ * The mod_time is added to the old time.  */
-+extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
-+#define dwc_timer_schedule DWC_TIMER_SCHEDULE
-+
-+/** Disables the timer from execution. */
-+extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
-+#define dwc_timer_cancel DWC_TIMER_CANCEL
-+
-+
-+/** @name Spinlocks
-+ *
-+ * These locks are used when the work between the lock/unlock is atomic and
-+ * short.  Interrupts are also disabled during the lock/unlock and thus they are
-+ * suitable to lock between interrupt/non-interrupt context.  They also lock
-+ * between processes if you have multiple CPUs or Preemption.  If you don't have
-+ * multiple CPUS or Preemption, then the you can simply implement the
-+ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts.  Because
-+ * the work between the lock/unlock is atomic, the process context will never
-+ * change, and so you never have to lock between processes.  */
-+
-+struct dwc_spinlock;
-+
-+/** Type for a spinlock */
-+typedef struct dwc_spinlock dwc_spinlock_t;
-+
-+/** Type for the 'flags' argument to spinlock funtions */
-+typedef unsigned long dwc_irqflags_t;
-+
-+/** Returns an initialized lock variable.  This function should allocate and
-+ * initialize the OS-specific data structure used for locking.  This data
-+ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
-+ * be freed by the DWC_FREE_LOCK when it is no longer used.
-+ *
-+ * For Linux Spinlock Debugging make it macro because the debugging routines use
-+ * the symbol name to determine recursive locking. Using a wrapper function
-+ * makes it falsely think recursive locking occurs. */
-+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)
-+#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \
-+	lock = DWC_ALLOC(sizeof(spinlock_t)); \
-+	if (lock) { \
-+		spin_lock_init((spinlock_t *)lock); \
-+	} \
-+})
-+#else
-+extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
-+#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
-+#endif
-+
-+/** Frees an initialized lock variable. */
-+extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
-+#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
-+
-+/** Disables interrupts and blocks until it acquires the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ * @param flags Unsigned long for irq flags storage.
-+ */
-+extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
-+#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
-+
-+/** Re-enables the interrupt and releases the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ * @param flags Unsigned long for irq flags storage.  Must be the same as was
-+ * passed into DWC_LOCK.
-+ */
-+extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
-+#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
-+
-+/** Blocks until it acquires the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ */
-+extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
-+#define dwc_spinlock DWC_SPINLOCK
-+
-+/** Releases the lock.
-+ *
-+ * @param lock Pointer to the spinlock.
-+ */
-+extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
-+#define dwc_spinunlock DWC_SPINUNLOCK
-+
-+
-+/** @name Mutexes
-+ *
-+ * Unlike spinlocks Mutexes lock only between processes and the work between the
-+ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
-+ */
-+
-+struct dwc_mutex;
-+
-+/** Type for a mutex */
-+typedef struct dwc_mutex dwc_mutex_t;
-+
-+/* For Linux Mutex Debugging make it inline because the debugging routines use
-+ * the symbol to determine recursive locking.  This makes it falsely think
-+ * recursive locking occurs. */
-+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
-+#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
-+	__mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
-+	mutex_init((struct mutex *)__mutexp); \
-+})
-+#endif
-+
-+/** Allocate a mutex */
-+extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
-+#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
-+
-+/* For memory leak debugging when using Linux Mutex Debugging */
-+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
-+#define DWC_MUTEX_FREE(__mutexp) do { \
-+	mutex_destroy((struct mutex *)__mutexp); \
-+	DWC_FREE(__mutexp); \
-+} while(0)
-+#else
-+/** Free a mutex */
-+extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
-+#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
-+#endif
-+
-+/** Lock a mutex */
-+extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_lock DWC_MUTEX_LOCK
-+
-+/** Non-blocking lock returns 1 on successful lock. */
-+extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
-+
-+/** Unlock a mutex */
-+extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
-+#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
-+
-+
-+/** @name Time */
-+
-+/** Microsecond delay.
-+ *
-+ * @param usecs  Microseconds to delay.
-+ */
-+extern void DWC_UDELAY(uint32_t usecs);
-+#define dwc_udelay DWC_UDELAY
-+
-+/** Millisecond delay.
-+ *
-+ * @param msecs  Milliseconds to delay.
-+ */
-+extern void DWC_MDELAY(uint32_t msecs);
-+#define dwc_mdelay DWC_MDELAY
-+
-+/** Non-busy waiting.
-+ * Sleeps for specified number of milliseconds.
-+ *
-+ * @param msecs Milliseconds to sleep.
-+ */
-+extern void DWC_MSLEEP(uint32_t msecs);
-+#define dwc_msleep DWC_MSLEEP
-+
-+/**
-+ * Returns number of milliseconds since boot.
-+ */
-+extern uint32_t DWC_TIME(void);
-+#define dwc_time DWC_TIME
-+
-+
-+
-+
-+/* @mainpage DWC Portability and Common Library
-+ *
-+ * This is the documentation for the DWC Portability and Common Library.
-+ *
-+ * @section intro Introduction
-+ *
-+ * The DWC Portability library consists of wrapper calls and data structures to
-+ * all low-level functions which are typically provided by the OS.  The WUDEV
-+ * driver uses only these functions.  In order to port the WUDEV driver, only
-+ * the functions in this library need to be re-implemented, with the same
-+ * behavior as documented here.
-+ *
-+ * The Common library consists of higher level functions, which rely only on
-+ * calling the functions from the DWC Portability library.  These common
-+ * routines are shared across modules.  Some of the common libraries need to be
-+ * used directly by the driver programmer when porting WUDEV.  Such as the
-+ * parameter and notification libraries.
-+ *
-+ * @section low Portability Library OS Wrapper Functions
-+ *
-+ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
-+ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC().  All of
-+ * these functions are included in the dwc_os.h file.
-+ *
-+ * There are many functions here covering a wide array of OS services.  Please
-+ * see dwc_os.h for details, and implementation notes for each function.
-+ *
-+ * @section common Common Library Functions
-+ *
-+ * Any function starting with dwc and in all lowercase is a common library
-+ * routine.  These functions have a portable implementation and do not need to
-+ * be reimplemented when porting.  The common routines can be used by any
-+ * driver, and some must be used by the end user to control the drivers.  For
-+ * example, you must use the Parameter common library in order to set the
-+ * parameters in the WUDEV module.
-+ *
-+ * The common libraries consist of the following:
-+ *
-+ * - Connection Contexts - Used internally and can be used by end-user.  See dwc_cc.h
-+ * - Parameters - Used internally and can be used by end-user.  See dwc_params.h
-+ * - Notifications - Used internally and can be used by end-user.  See dwc_notifier.h
-+ * - Lists - Used internally and can be used by end-user.  See dwc_list.h
-+ * - Memory Debugging - Used internally and can be used by end-user.  See dwc_os.h
-+ * - Modpow - Used internally only.  See dwc_modpow.h
-+ * - DH - Used internally only.  See dwc_dh.h
-+ * - Crypto - Used internally only.  See dwc_crypto.h
-+ *
-+ *
-+ * @section prereq Prerequistes For dwc_os.h
-+ * @subsection types Data Types
-+ *
-+ * The dwc_os.h file assumes that several low-level data types are pre defined for the
-+ * compilation environment.  These data types are:
-+ *
-+ * - uint8_t - unsigned 8-bit data type
-+ * - int8_t - signed 8-bit data type
-+ * - uint16_t - unsigned 16-bit data type
-+ * - int16_t - signed 16-bit data type
-+ * - uint32_t - unsigned 32-bit data type
-+ * - int32_t - signed 32-bit data type
-+ * - uint64_t - unsigned 64-bit data type
-+ * - int64_t - signed 64-bit data type
-+ *
-+ * Ensure that these are defined before using dwc_os.h.  The easiest way to do
-+ * that is to modify the top of the file to include the appropriate header.
-+ * This is already done for the Linux environment.  If the DWC_LINUX macro is
-+ * defined, the correct header will be added.  A standard header <stdint.h> is
-+ * also used for environments where standard C headers are available.
-+ *
-+ * @subsection stdarg Variable Arguments
-+ *
-+ * Variable arguments are provided by a standard C header <stdarg.h>.  it is
-+ * available in Both the Linux and ANSI C enviornment.  An equivalent must be
-+ * provided in your enviornment in order to use dwc_os.h with the debug and
-+ * tracing message functionality.
-+ *
-+ * @subsection thread Threading
-+ *
-+ * WUDEV Core must be run on an operating system that provides for multiple
-+ * threads/processes.  Threading can be implemented in many ways, even in
-+ * embedded systems without an operating system.  At the bare minimum, the
-+ * system should be able to start any number of processes at any time to handle
-+ * special work.  It need not be a pre-emptive system.  Process context can
-+ * change upon a call to a blocking function.  The hardware interrupt context
-+ * that calls the module's ISR() function must be differentiable from process
-+ * context, even if your processes are impemented via a hardware interrupt.
-+ * Further locking mechanism between process must exist (or be implemented), and
-+ * process context must have a way to disable interrupts for a period of time to
-+ * lock them out.  If all of this exists, the functions in dwc_os.h related to
-+ * threading should be able to be implemented with the defined behavior.
-+ *
-+ */
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _DWC_OS_H_ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_common_port/usb.h
-@@ -0,0 +1,946 @@
-+/*
-+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
-+ * All rights reserved.
-+ *
-+ * This code is derived from software contributed to The NetBSD Foundation
-+ * by Lennart Augustsson (lennart@augustsson.net) at
-+ * Carlstedt Research & Technology.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions and the following disclaimer.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. All advertising materials mentioning features or use of this software
-+ *    must display the following acknowledgement:
-+ *        This product includes software developed by the NetBSD
-+ *        Foundation, Inc. and its contributors.
-+ * 4. Neither the name of The NetBSD Foundation nor the names of its
-+ *    contributors may be used to endorse or promote products derived
-+ *    from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
-+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
-+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+/* Modified by Synopsys, Inc, 12/12/2007 */
-+
-+
-+#ifndef _USB_H_
-+#define _USB_H_
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+/*
-+ * The USB records contain some unaligned little-endian word
-+ * components.  The U[SG]ETW macros take care of both the alignment
-+ * and endian problem and should always be used to access non-byte
-+ * values.
-+ */
-+typedef u_int8_t uByte;
-+typedef u_int8_t uWord[2];
-+typedef u_int8_t uDWord[4];
-+
-+#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
-+#define UCONSTW(x)	{ (x) & 0xff, ((x) >> 8) & 0xff }
-+#define UCONSTDW(x)	{ (x) & 0xff, ((x) >> 8) & 0xff, \
-+			  ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }
-+
-+#if 1
-+#define UGETW(w) ((w)[0] | ((w)[1] << 8))
-+#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
-+#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
-+#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
-+		     (w)[1] = (u_int8_t)((v) >> 8), \
-+		     (w)[2] = (u_int8_t)((v) >> 16), \
-+		     (w)[3] = (u_int8_t)((v) >> 24))
-+#else
-+/*
-+ * On little-endian machines that can handle unanliged accesses
-+ * (e.g. i386) these macros can be replaced by the following.
-+ */
-+#define UGETW(w) (*(u_int16_t *)(w))
-+#define USETW(w,v) (*(u_int16_t *)(w) = (v))
-+#define UGETDW(w) (*(u_int32_t *)(w))
-+#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
-+#endif
-+
-+/*
-+ * Macros for accessing UAS IU fields, which are big-endian
-+ */
-+#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))
-+#define IUCONSTW(x)	{ ((x) >> 8) & 0xff, (x) & 0xff }
-+#define IUCONSTDW(x)	{ ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
-+			((x) >> 8) & 0xff, (x) & 0xff }
-+#define IUGETW(w) (((w)[0] << 8) | (w)[1])
-+#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))
-+#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])
-+#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \
-+		      (w)[1] = (u_int8_t)((v) >> 16), \
-+		      (w)[2] = (u_int8_t)((v) >> 8), \
-+		      (w)[3] = (u_int8_t)(v))
-+
-+#define UPACKED __attribute__((__packed__))
-+
-+typedef struct {
-+	uByte		bmRequestType;
-+	uByte		bRequest;
-+	uWord		wValue;
-+	uWord		wIndex;
-+	uWord		wLength;
-+} UPACKED usb_device_request_t;
-+
-+#define UT_GET_DIR(a) ((a) & 0x80)
-+#define UT_WRITE		0x00
-+#define UT_READ			0x80
-+
-+#define UT_GET_TYPE(a) ((a) & 0x60)
-+#define UT_STANDARD		0x00
-+#define UT_CLASS		0x20
-+#define UT_VENDOR		0x40
-+
-+#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
-+#define UT_DEVICE		0x00
-+#define UT_INTERFACE		0x01
-+#define UT_ENDPOINT		0x02
-+#define UT_OTHER		0x03
-+
-+#define UT_READ_DEVICE		(UT_READ  | UT_STANDARD | UT_DEVICE)
-+#define UT_READ_INTERFACE	(UT_READ  | UT_STANDARD | UT_INTERFACE)
-+#define UT_READ_ENDPOINT	(UT_READ  | UT_STANDARD | UT_ENDPOINT)
-+#define UT_WRITE_DEVICE		(UT_WRITE | UT_STANDARD | UT_DEVICE)
-+#define UT_WRITE_INTERFACE	(UT_WRITE | UT_STANDARD | UT_INTERFACE)
-+#define UT_WRITE_ENDPOINT	(UT_WRITE | UT_STANDARD | UT_ENDPOINT)
-+#define UT_READ_CLASS_DEVICE	(UT_READ  | UT_CLASS | UT_DEVICE)
-+#define UT_READ_CLASS_INTERFACE	(UT_READ  | UT_CLASS | UT_INTERFACE)
-+#define UT_READ_CLASS_OTHER	(UT_READ  | UT_CLASS | UT_OTHER)
-+#define UT_READ_CLASS_ENDPOINT	(UT_READ  | UT_CLASS | UT_ENDPOINT)
-+#define UT_WRITE_CLASS_DEVICE	(UT_WRITE | UT_CLASS | UT_DEVICE)
-+#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
-+#define UT_WRITE_CLASS_OTHER	(UT_WRITE | UT_CLASS | UT_OTHER)
-+#define UT_WRITE_CLASS_ENDPOINT	(UT_WRITE | UT_CLASS | UT_ENDPOINT)
-+#define UT_READ_VENDOR_DEVICE	(UT_READ  | UT_VENDOR | UT_DEVICE)
-+#define UT_READ_VENDOR_INTERFACE (UT_READ  | UT_VENDOR | UT_INTERFACE)
-+#define UT_READ_VENDOR_OTHER	(UT_READ  | UT_VENDOR | UT_OTHER)
-+#define UT_READ_VENDOR_ENDPOINT	(UT_READ  | UT_VENDOR | UT_ENDPOINT)
-+#define UT_WRITE_VENDOR_DEVICE	(UT_WRITE | UT_VENDOR | UT_DEVICE)
-+#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
-+#define UT_WRITE_VENDOR_OTHER	(UT_WRITE | UT_VENDOR | UT_OTHER)
-+#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
-+
-+/* Requests */
-+#define UR_GET_STATUS		0x00
-+#define  USTAT_STANDARD_STATUS  0x00
-+#define  WUSTAT_WUSB_FEATURE    0x01
-+#define  WUSTAT_CHANNEL_INFO    0x02
-+#define  WUSTAT_RECEIVED_DATA   0x03
-+#define  WUSTAT_MAS_AVAILABILITY 0x04
-+#define  WUSTAT_CURRENT_TRANSMIT_POWER 0x05
-+#define UR_CLEAR_FEATURE	0x01
-+#define UR_SET_FEATURE		0x03
-+#define UR_SET_AND_TEST_FEATURE 0x0c
-+#define UR_SET_ADDRESS		0x05
-+#define UR_GET_DESCRIPTOR	0x06
-+#define  UDESC_DEVICE		0x01
-+#define  UDESC_CONFIG		0x02
-+#define  UDESC_STRING		0x03
-+#define  UDESC_INTERFACE	0x04
-+#define  UDESC_ENDPOINT		0x05
-+#define  UDESC_SS_USB_COMPANION	0x30
-+#define  UDESC_DEVICE_QUALIFIER	0x06
-+#define  UDESC_OTHER_SPEED_CONFIGURATION 0x07
-+#define  UDESC_INTERFACE_POWER	0x08
-+#define  UDESC_OTG		0x09
-+#define  WUDESC_SECURITY	0x0c
-+#define  WUDESC_KEY		0x0d
-+#define   WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
-+#define   WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
-+#define    WUD_KEY_TYPE_ASSOC    0x01
-+#define    WUD_KEY_TYPE_GTK      0x02
-+#define   WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
-+#define    WUD_KEY_ORIGIN_HOST   0x00
-+#define    WUD_KEY_ORIGIN_DEVICE 0x01
-+#define  WUDESC_ENCRYPTION_TYPE	0x0e
-+#define  WUDESC_BOS		0x0f
-+#define  WUDESC_DEVICE_CAPABILITY 0x10
-+#define  WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
-+#define  UDESC_BOS		0x0f
-+#define  UDESC_DEVICE_CAPABILITY 0x10
-+#define  UDESC_CS_DEVICE	0x21	/* class specific */
-+#define  UDESC_CS_CONFIG	0x22
-+#define  UDESC_CS_STRING	0x23
-+#define  UDESC_CS_INTERFACE	0x24
-+#define  UDESC_CS_ENDPOINT	0x25
-+#define  UDESC_HUB		0x29
-+#define UR_SET_DESCRIPTOR	0x07
-+#define UR_GET_CONFIG		0x08
-+#define UR_SET_CONFIG		0x09
-+#define UR_GET_INTERFACE	0x0a
-+#define UR_SET_INTERFACE	0x0b
-+#define UR_SYNCH_FRAME		0x0c
-+#define WUR_SET_ENCRYPTION      0x0d
-+#define WUR_GET_ENCRYPTION	0x0e
-+#define WUR_SET_HANDSHAKE	0x0f
-+#define WUR_GET_HANDSHAKE	0x10
-+#define WUR_SET_CONNECTION	0x11
-+#define WUR_SET_SECURITY_DATA	0x12
-+#define WUR_GET_SECURITY_DATA	0x13
-+#define WUR_SET_WUSB_DATA	0x14
-+#define  WUDATA_DRPIE_INFO	0x01
-+#define  WUDATA_TRANSMIT_DATA	0x02
-+#define  WUDATA_TRANSMIT_PARAMS	0x03
-+#define  WUDATA_RECEIVE_PARAMS	0x04
-+#define  WUDATA_TRANSMIT_POWER	0x05
-+#define WUR_LOOPBACK_DATA_WRITE	0x15
-+#define WUR_LOOPBACK_DATA_READ	0x16
-+#define WUR_SET_INTERFACE_DS	0x17
-+
-+/* Feature numbers */
-+#define UF_ENDPOINT_HALT	0
-+#define UF_DEVICE_REMOTE_WAKEUP	1
-+#define UF_TEST_MODE		2
-+#define UF_DEVICE_B_HNP_ENABLE	3
-+#define UF_DEVICE_A_HNP_SUPPORT	4
-+#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
-+#define WUF_WUSB		3
-+#define  WUF_TX_DRPIE		0x0
-+#define  WUF_DEV_XMIT_PACKET	0x1
-+#define  WUF_COUNT_PACKETS	0x2
-+#define  WUF_CAPTURE_PACKETS	0x3
-+#define UF_FUNCTION_SUSPEND	0
-+#define UF_U1_ENABLE		48
-+#define UF_U2_ENABLE		49
-+#define UF_LTM_ENABLE		50
-+
-+/* Class requests from the USB 2.0 hub spec, table 11-15 */
-+#define UCR_CLEAR_HUB_FEATURE		(0x2000 | UR_CLEAR_FEATURE)
-+#define UCR_CLEAR_PORT_FEATURE		(0x2300 | UR_CLEAR_FEATURE)
-+#define UCR_GET_HUB_DESCRIPTOR		(0xa000 | UR_GET_DESCRIPTOR)
-+#define UCR_GET_HUB_STATUS		(0xa000 | UR_GET_STATUS)
-+#define UCR_GET_PORT_STATUS		(0xa300 | UR_GET_STATUS)
-+#define UCR_SET_HUB_FEATURE		(0x2000 | UR_SET_FEATURE)
-+#define UCR_SET_PORT_FEATURE		(0x2300 | UR_SET_FEATURE)
-+#define UCR_SET_AND_TEST_PORT_FEATURE	(0xa300 | UR_SET_AND_TEST_FEATURE)
-+
-+#ifdef _MSC_VER
-+#include <pshpack1.h>
-+#endif
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+	uByte		bDescriptorSubtype;
-+} UPACKED usb_descriptor_t;
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+} UPACKED usb_descriptor_header_t;
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+	uWord		bcdUSB;
-+#define UD_USB_2_0		0x0200
-+#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
-+	uByte		bDeviceClass;
-+	uByte		bDeviceSubClass;
-+	uByte		bDeviceProtocol;
-+	uByte		bMaxPacketSize;
-+	/* The fields below are not part of the initial descriptor. */
-+	uWord		idVendor;
-+	uWord		idProduct;
-+	uWord		bcdDevice;
-+	uByte		iManufacturer;
-+	uByte		iProduct;
-+	uByte		iSerialNumber;
-+	uByte		bNumConfigurations;
-+} UPACKED usb_device_descriptor_t;
-+#define USB_DEVICE_DESCRIPTOR_SIZE 18
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+	uWord		wTotalLength;
-+	uByte		bNumInterface;
-+	uByte		bConfigurationValue;
-+	uByte		iConfiguration;
-+#define UC_ATT_ONE		(1 << 7)	/* must be set */
-+#define UC_ATT_SELFPOWER	(1 << 6)	/* self powered */
-+#define UC_ATT_WAKEUP		(1 << 5)	/* can wakeup */
-+#define UC_ATT_BATTERY		(1 << 4)	/* battery powered */
-+	uByte		bmAttributes;
-+#define UC_BUS_POWERED		0x80
-+#define UC_SELF_POWERED		0x40
-+#define UC_REMOTE_WAKEUP	0x20
-+	uByte		bMaxPower; /* max current in 2 mA units */
-+#define UC_POWER_FACTOR 2
-+} UPACKED usb_config_descriptor_t;
-+#define USB_CONFIG_DESCRIPTOR_SIZE 9
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+	uByte		bInterfaceNumber;
-+	uByte		bAlternateSetting;
-+	uByte		bNumEndpoints;
-+	uByte		bInterfaceClass;
-+	uByte		bInterfaceSubClass;
-+	uByte		bInterfaceProtocol;
-+	uByte		iInterface;
-+} UPACKED usb_interface_descriptor_t;
-+#define USB_INTERFACE_DESCRIPTOR_SIZE 9
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+	uByte		bEndpointAddress;
-+#define UE_GET_DIR(a)	((a) & 0x80)
-+#define UE_SET_DIR(a,d)	((a) | (((d)&1) << 7))
-+#define UE_DIR_IN	0x80
-+#define UE_DIR_OUT	0x00
-+#define UE_ADDR		0x0f
-+#define UE_GET_ADDR(a)	((a) & UE_ADDR)
-+	uByte		bmAttributes;
-+#define UE_XFERTYPE	0x03
-+#define  UE_CONTROL	0x00
-+#define  UE_ISOCHRONOUS	0x01
-+#define  UE_BULK	0x02
-+#define  UE_INTERRUPT	0x03
-+#define UE_GET_XFERTYPE(a)	((a) & UE_XFERTYPE)
-+#define UE_ISO_TYPE	0x0c
-+#define  UE_ISO_ASYNC	0x04
-+#define  UE_ISO_ADAPT	0x08
-+#define  UE_ISO_SYNC	0x0c
-+#define UE_GET_ISO_TYPE(a)	((a) & UE_ISO_TYPE)
-+	uWord		wMaxPacketSize;
-+	uByte		bInterval;
-+} UPACKED usb_endpoint_descriptor_t;
-+#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
-+
-+typedef struct ss_endpoint_companion_descriptor {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uByte bMaxBurst;
-+#define USSE_GET_MAX_STREAMS(a)		((a) & 0x1f)
-+#define USSE_SET_MAX_STREAMS(a, b)	((a) | ((b) & 0x1f))
-+#define USSE_GET_MAX_PACKET_NUM(a)	((a) & 0x03)
-+#define USSE_SET_MAX_PACKET_NUM(a, b)	((a) | ((b) & 0x03))
-+	uByte bmAttributes;
-+	uWord wBytesPerInterval;
-+} UPACKED ss_endpoint_companion_descriptor_t;
-+#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+	uWord		bString[127];
-+} UPACKED usb_string_descriptor_t;
-+#define USB_MAX_STRING_LEN 128
-+#define USB_LANGUAGE_TABLE 0	/* # of the string language id table */
-+
-+/* Hub specific request */
-+#define UR_GET_BUS_STATE	0x02
-+#define UR_CLEAR_TT_BUFFER	0x08
-+#define UR_RESET_TT		0x09
-+#define UR_GET_TT_STATE		0x0a
-+#define UR_STOP_TT		0x0b
-+
-+/* Hub features */
-+#define UHF_C_HUB_LOCAL_POWER	0
-+#define UHF_C_HUB_OVER_CURRENT	1
-+#define UHF_PORT_CONNECTION	0
-+#define UHF_PORT_ENABLE		1
-+#define UHF_PORT_SUSPEND	2
-+#define UHF_PORT_OVER_CURRENT	3
-+#define UHF_PORT_RESET		4
-+#define UHF_PORT_L1		5
-+#define UHF_PORT_POWER		8
-+#define UHF_PORT_LOW_SPEED	9
-+#define UHF_PORT_HIGH_SPEED	10
-+#define UHF_C_PORT_CONNECTION	16
-+#define UHF_C_PORT_ENABLE	17
-+#define UHF_C_PORT_SUSPEND	18
-+#define UHF_C_PORT_OVER_CURRENT	19
-+#define UHF_C_PORT_RESET	20
-+#define UHF_C_PORT_L1		23
-+#define UHF_PORT_TEST		21
-+#define UHF_PORT_INDICATOR	22
-+
-+typedef struct {
-+	uByte		bDescLength;
-+	uByte		bDescriptorType;
-+	uByte		bNbrPorts;
-+	uWord		wHubCharacteristics;
-+#define UHD_PWR			0x0003
-+#define  UHD_PWR_GANGED		0x0000
-+#define  UHD_PWR_INDIVIDUAL	0x0001
-+#define  UHD_PWR_NO_SWITCH	0x0002
-+#define UHD_COMPOUND		0x0004
-+#define UHD_OC			0x0018
-+#define  UHD_OC_GLOBAL		0x0000
-+#define  UHD_OC_INDIVIDUAL	0x0008
-+#define  UHD_OC_NONE		0x0010
-+#define UHD_TT_THINK		0x0060
-+#define  UHD_TT_THINK_8		0x0000
-+#define  UHD_TT_THINK_16	0x0020
-+#define  UHD_TT_THINK_24	0x0040
-+#define  UHD_TT_THINK_32	0x0060
-+#define UHD_PORT_IND		0x0080
-+	uByte		bPwrOn2PwrGood;	/* delay in 2 ms units */
-+#define UHD_PWRON_FACTOR 2
-+	uByte		bHubContrCurrent;
-+	uByte		DeviceRemovable[32]; /* max 255 ports */
-+#define UHD_NOT_REMOV(desc, i) \
-+    (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
-+	/* deprecated */ uByte		PortPowerCtrlMask[1];
-+} UPACKED usb_hub_descriptor_t;
-+#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+	uWord		bcdUSB;
-+	uByte		bDeviceClass;
-+	uByte		bDeviceSubClass;
-+	uByte		bDeviceProtocol;
-+	uByte		bMaxPacketSize0;
-+	uByte		bNumConfigurations;
-+	uByte		bReserved;
-+} UPACKED usb_device_qualifier_t;
-+#define USB_DEVICE_QUALIFIER_SIZE 10
-+
-+typedef struct {
-+	uByte		bLength;
-+	uByte		bDescriptorType;
-+	uByte		bmAttributes;
-+#define UOTG_SRP	0x01
-+#define UOTG_HNP	0x02
-+} UPACKED usb_otg_descriptor_t;
-+
-+/* OTG feature selectors */
-+#define UOTG_B_HNP_ENABLE	3
-+#define UOTG_A_HNP_SUPPORT	4
-+#define UOTG_A_ALT_HNP_SUPPORT	5
-+
-+typedef struct {
-+	uWord		wStatus;
-+/* Device status flags */
-+#define UDS_SELF_POWERED		0x0001
-+#define UDS_REMOTE_WAKEUP		0x0002
-+/* Endpoint status flags */
-+#define UES_HALT			0x0001
-+} UPACKED usb_status_t;
-+
-+typedef struct {
-+	uWord		wHubStatus;
-+#define UHS_LOCAL_POWER			0x0001
-+#define UHS_OVER_CURRENT		0x0002
-+	uWord		wHubChange;
-+} UPACKED usb_hub_status_t;
-+
-+typedef struct {
-+	uWord		wPortStatus;
-+#define UPS_CURRENT_CONNECT_STATUS	0x0001
-+#define UPS_PORT_ENABLED		0x0002
-+#define UPS_SUSPEND			0x0004
-+#define UPS_OVERCURRENT_INDICATOR	0x0008
-+#define UPS_RESET			0x0010
-+#define UPS_PORT_POWER			0x0100
-+#define UPS_LOW_SPEED			0x0200
-+#define UPS_HIGH_SPEED			0x0400
-+#define UPS_PORT_TEST			0x0800
-+#define UPS_PORT_INDICATOR		0x1000
-+	uWord		wPortChange;
-+#define UPS_C_CONNECT_STATUS		0x0001
-+#define UPS_C_PORT_ENABLED		0x0002
-+#define UPS_C_SUSPEND			0x0004
-+#define UPS_C_OVERCURRENT_INDICATOR	0x0008
-+#define UPS_C_PORT_RESET		0x0010
-+} UPACKED usb_port_status_t;
-+
-+#ifdef _MSC_VER
-+#include <poppack.h>
-+#endif
-+
-+/* Device class codes */
-+#define UDCLASS_IN_INTERFACE	0x00
-+#define UDCLASS_COMM		0x02
-+#define UDCLASS_HUB		0x09
-+#define  UDSUBCLASS_HUB		0x00
-+#define  UDPROTO_FSHUB		0x00
-+#define  UDPROTO_HSHUBSTT	0x01
-+#define  UDPROTO_HSHUBMTT	0x02
-+#define UDCLASS_DIAGNOSTIC	0xdc
-+#define UDCLASS_WIRELESS	0xe0
-+#define  UDSUBCLASS_RF		0x01
-+#define   UDPROTO_BLUETOOTH	0x01
-+#define UDCLASS_VENDOR		0xff
-+
-+/* Interface class codes */
-+#define UICLASS_UNSPEC		0x00
-+
-+#define UICLASS_AUDIO		0x01
-+#define  UISUBCLASS_AUDIOCONTROL	1
-+#define  UISUBCLASS_AUDIOSTREAM		2
-+#define  UISUBCLASS_MIDISTREAM		3
-+
-+#define UICLASS_CDC		0x02 /* communication */
-+#define  UISUBCLASS_DIRECT_LINE_CONTROL_MODEL	1
-+#define  UISUBCLASS_ABSTRACT_CONTROL_MODEL	2
-+#define  UISUBCLASS_TELEPHONE_CONTROL_MODEL	3
-+#define  UISUBCLASS_MULTICHANNEL_CONTROL_MODEL	4
-+#define  UISUBCLASS_CAPI_CONTROLMODEL		5
-+#define  UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
-+#define  UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
-+#define   UIPROTO_CDC_AT			1
-+
-+#define UICLASS_HID		0x03
-+#define  UISUBCLASS_BOOT	1
-+#define  UIPROTO_BOOT_KEYBOARD	1
-+
-+#define UICLASS_PHYSICAL	0x05
-+
-+#define UICLASS_IMAGE		0x06
-+
-+#define UICLASS_PRINTER		0x07
-+#define  UISUBCLASS_PRINTER	1
-+#define  UIPROTO_PRINTER_UNI	1
-+#define  UIPROTO_PRINTER_BI	2
-+#define  UIPROTO_PRINTER_1284	3
-+
-+#define UICLASS_MASS		0x08
-+#define  UISUBCLASS_RBC		1
-+#define  UISUBCLASS_SFF8020I	2
-+#define  UISUBCLASS_QIC157	3
-+#define  UISUBCLASS_UFI		4
-+#define  UISUBCLASS_SFF8070I	5
-+#define  UISUBCLASS_SCSI	6
-+#define  UIPROTO_MASS_CBI_I	0
-+#define  UIPROTO_MASS_CBI	1
-+#define  UIPROTO_MASS_BBB_OLD	2	/* Not in the spec anymore */
-+#define  UIPROTO_MASS_BBB	80	/* 'P' for the Iomega Zip drive */
-+
-+#define UICLASS_HUB		0x09
-+#define  UISUBCLASS_HUB		0
-+#define  UIPROTO_FSHUB		0
-+#define  UIPROTO_HSHUBSTT	0 /* Yes, same as previous */
-+#define  UIPROTO_HSHUBMTT	1
-+
-+#define UICLASS_CDC_DATA	0x0a
-+#define  UISUBCLASS_DATA		0
-+#define   UIPROTO_DATA_ISDNBRI		0x30    /* Physical iface */
-+#define   UIPROTO_DATA_HDLC		0x31    /* HDLC */
-+#define   UIPROTO_DATA_TRANSPARENT	0x32    /* Transparent */
-+#define   UIPROTO_DATA_Q921M		0x50    /* Management for Q921 */
-+#define   UIPROTO_DATA_Q921		0x51    /* Data for Q921 */
-+#define   UIPROTO_DATA_Q921TM		0x52    /* TEI multiplexer for Q921 */
-+#define   UIPROTO_DATA_V42BIS		0x90    /* Data compression */
-+#define   UIPROTO_DATA_Q931		0x91    /* Euro-ISDN */
-+#define   UIPROTO_DATA_V120		0x92    /* V.24 rate adaption */
-+#define   UIPROTO_DATA_CAPI		0x93    /* CAPI 2.0 commands */
-+#define   UIPROTO_DATA_HOST_BASED	0xfd    /* Host based driver */
-+#define   UIPROTO_DATA_PUF		0xfe    /* see Prot. Unit Func. Desc.*/
-+#define   UIPROTO_DATA_VENDOR		0xff    /* Vendor specific */
-+
-+#define UICLASS_SMARTCARD	0x0b
-+
-+/*#define UICLASS_FIRM_UPD	0x0c*/
-+
-+#define UICLASS_SECURITY	0x0d
-+
-+#define UICLASS_DIAGNOSTIC	0xdc
-+
-+#define UICLASS_WIRELESS	0xe0
-+#define  UISUBCLASS_RF			0x01
-+#define   UIPROTO_BLUETOOTH		0x01
-+
-+#define UICLASS_APPL_SPEC	0xfe
-+#define  UISUBCLASS_FIRMWARE_DOWNLOAD	1
-+#define  UISUBCLASS_IRDA		2
-+#define  UIPROTO_IRDA			0
-+
-+#define UICLASS_VENDOR		0xff
-+
-+#define USB_HUB_MAX_DEPTH 5
-+
-+/*
-+ * Minimum time a device needs to be powered down to go through
-+ * a power cycle.  XXX Are these time in the spec?
-+ */
-+#define USB_POWER_DOWN_TIME	200 /* ms */
-+#define USB_PORT_POWER_DOWN_TIME	100 /* ms */
-+
-+#if 0
-+/* These are the values from the spec. */
-+#define USB_PORT_RESET_DELAY	10  /* ms */
-+#define USB_PORT_ROOT_RESET_DELAY 50  /* ms */
-+#define USB_PORT_RESET_RECOVERY	10  /* ms */
-+#define USB_PORT_POWERUP_DELAY	100 /* ms */
-+#define USB_SET_ADDRESS_SETTLE	2   /* ms */
-+#define USB_RESUME_DELAY	(20*5)  /* ms */
-+#define USB_RESUME_WAIT		10  /* ms */
-+#define USB_RESUME_RECOVERY	10  /* ms */
-+#define USB_EXTRA_POWER_UP_TIME	0   /* ms */
-+#else
-+/* Allow for marginal (i.e. non-conforming) devices. */
-+#define USB_PORT_RESET_DELAY	50  /* ms */
-+#define USB_PORT_ROOT_RESET_DELAY 250  /* ms */
-+#define USB_PORT_RESET_RECOVERY	250  /* ms */
-+#define USB_PORT_POWERUP_DELAY	300 /* ms */
-+#define USB_SET_ADDRESS_SETTLE	10  /* ms */
-+#define USB_RESUME_DELAY	(50*5)  /* ms */
-+#define USB_RESUME_WAIT		50  /* ms */
-+#define USB_RESUME_RECOVERY	50  /* ms */
-+#define USB_EXTRA_POWER_UP_TIME	20  /* ms */
-+#endif
-+
-+#define USB_MIN_POWER		100 /* mA */
-+#define USB_MAX_POWER		500 /* mA */
-+
-+#define USB_BUS_RESET_DELAY	100 /* ms XXX?*/
-+
-+#define USB_UNCONFIG_NO 0
-+#define USB_UNCONFIG_INDEX (-1)
-+
-+/*** ioctl() related stuff ***/
-+
-+struct usb_ctl_request {
-+	int	ucr_addr;
-+	usb_device_request_t ucr_request;
-+	void	*ucr_data;
-+	int	ucr_flags;
-+#define USBD_SHORT_XFER_OK	0x04	/* allow short reads */
-+	int	ucr_actlen;		/* actual length transferred */
-+};
-+
-+struct usb_alt_interface {
-+	int	uai_config_index;
-+	int	uai_interface_index;
-+	int	uai_alt_no;
-+};
-+
-+#define USB_CURRENT_CONFIG_INDEX (-1)
-+#define USB_CURRENT_ALT_INDEX (-1)
-+
-+struct usb_config_desc {
-+	int	ucd_config_index;
-+	usb_config_descriptor_t ucd_desc;
-+};
-+
-+struct usb_interface_desc {
-+	int	uid_config_index;
-+	int	uid_interface_index;
-+	int	uid_alt_index;
-+	usb_interface_descriptor_t uid_desc;
-+};
-+
-+struct usb_endpoint_desc {
-+	int	ued_config_index;
-+	int	ued_interface_index;
-+	int	ued_alt_index;
-+	int	ued_endpoint_index;
-+	usb_endpoint_descriptor_t ued_desc;
-+};
-+
-+struct usb_full_desc {
-+	int	ufd_config_index;
-+	u_int	ufd_size;
-+	u_char	*ufd_data;
-+};
-+
-+struct usb_string_desc {
-+	int	usd_string_index;
-+	int	usd_language_id;
-+	usb_string_descriptor_t usd_desc;
-+};
-+
-+struct usb_ctl_report_desc {
-+	int	ucrd_size;
-+	u_char	ucrd_data[1024];	/* filled data size will vary */
-+};
-+
-+typedef struct { u_int32_t cookie; } usb_event_cookie_t;
-+
-+#define USB_MAX_DEVNAMES 4
-+#define USB_MAX_DEVNAMELEN 16
-+struct usb_device_info {
-+	u_int8_t	udi_bus;
-+	u_int8_t	udi_addr;	/* device address */
-+	usb_event_cookie_t udi_cookie;
-+	char		udi_product[USB_MAX_STRING_LEN];
-+	char		udi_vendor[USB_MAX_STRING_LEN];
-+	char		udi_release[8];
-+	u_int16_t	udi_productNo;
-+	u_int16_t	udi_vendorNo;
-+	u_int16_t	udi_releaseNo;
-+	u_int8_t	udi_class;
-+	u_int8_t	udi_subclass;
-+	u_int8_t	udi_protocol;
-+	u_int8_t	udi_config;
-+	u_int8_t	udi_speed;
-+#define USB_SPEED_UNKNOWN	0
-+#define USB_SPEED_LOW		1
-+#define USB_SPEED_FULL		2
-+#define USB_SPEED_HIGH		3
-+#define USB_SPEED_VARIABLE	4
-+#define USB_SPEED_SUPER		5
-+	int		udi_power;	/* power consumption in mA, 0 if selfpowered */
-+	int		udi_nports;
-+	char		udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
-+	u_int8_t	udi_ports[16];/* hub only: addresses of devices on ports */
-+#define USB_PORT_ENABLED 0xff
-+#define USB_PORT_SUSPENDED 0xfe
-+#define USB_PORT_POWERED 0xfd
-+#define USB_PORT_DISABLED 0xfc
-+};
-+
-+struct usb_ctl_report {
-+	int	ucr_report;
-+	u_char	ucr_data[1024];	/* filled data size will vary */
-+};
-+
-+struct usb_device_stats {
-+	u_long	uds_requests[4];	/* indexed by transfer type UE_* */
-+};
-+
-+#define WUSB_MIN_IE			0x80
-+#define WUSB_WCTA_IE			0x80
-+#define WUSB_WCONNECTACK_IE		0x81
-+#define WUSB_WHOSTINFO_IE		0x82
-+#define  WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
-+#define   WUHI_CA_RECONN		0x00
-+#define   WUHI_CA_LIMITED		0x01
-+#define   WUHI_CA_ALL			0x03
-+#define  WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
-+#define WUSB_WCHCHANGEANNOUNCE_IE	0x83
-+#define WUSB_WDEV_DISCONNECT_IE		0x84
-+#define WUSB_WHOST_DISCONNECT_IE	0x85
-+#define WUSB_WRELEASE_CHANNEL_IE	0x86
-+#define WUSB_WWORK_IE			0x87
-+#define WUSB_WCHANNEL_STOP_IE		0x88
-+#define WUSB_WDEV_KEEPALIVE_IE		0x89
-+#define WUSB_WISOCH_DISCARD_IE		0x8A
-+#define WUSB_WRESETDEVICE_IE		0x8B
-+#define WUSB_WXMIT_PACKET_ADJUST_IE	0x8C
-+#define WUSB_MAX_IE			0x8C
-+
-+/* Device Notification Types */
-+
-+#define WUSB_DN_MIN			0x01
-+#define WUSB_DN_CONNECT			0x01
-+# define WUSB_DA_OLDCONN	0x00
-+# define WUSB_DA_NEWCONN	0x01
-+# define WUSB_DA_SELF_BEACON	0x02
-+# define WUSB_DA_DIR_BEACON	0x04
-+# define WUSB_DA_NO_BEACON	0x06
-+#define WUSB_DN_DISCONNECT		0x02
-+#define WUSB_DN_EPRDY			0x03
-+#define WUSB_DN_MASAVAILCHANGED		0x04
-+#define WUSB_DN_REMOTEWAKEUP		0x05
-+#define WUSB_DN_SLEEP			0x06
-+#define WUSB_DN_ALIVE			0x07
-+#define WUSB_DN_MAX			0x07
-+
-+#ifdef _MSC_VER
-+#include <pshpack1.h>
-+#endif
-+
-+/* WUSB Handshake Data.  Used during the SET/GET HANDSHAKE requests */
-+typedef struct wusb_hndshk_data {
-+	uByte bMessageNumber;
-+	uByte bStatus;
-+	uByte tTKID[3];
-+	uByte bReserved;
-+	uByte CDID[16];
-+	uByte Nonce[16];
-+	uByte MIC[8];
-+} UPACKED wusb_hndshk_data_t;
-+#define WUSB_HANDSHAKE_LEN_FOR_MIC	38
-+
-+/* WUSB Connection Context */
-+typedef struct wusb_conn_context {
-+	uByte CHID [16];
-+	uByte CDID [16];
-+	uByte CK [16];
-+} UPACKED wusb_conn_context_t;
-+
-+/* WUSB Security Descriptor */
-+typedef struct wusb_security_desc {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uWord wTotalLength;
-+	uByte bNumEncryptionTypes;
-+} UPACKED wusb_security_desc_t;
-+
-+/* WUSB Encryption Type Descriptor */
-+typedef struct wusb_encrypt_type_desc {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+
-+	uByte bEncryptionType;
-+#define WUETD_UNSECURE		0
-+#define WUETD_WIRED		1
-+#define WUETD_CCM_1		2
-+#define WUETD_RSA_1		3
-+
-+	uByte bEncryptionValue;
-+	uByte bAuthKeyIndex;
-+} UPACKED wusb_encrypt_type_desc_t;
-+
-+/* WUSB Key Descriptor */
-+typedef struct wusb_key_desc {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uByte tTKID[3];
-+	uByte bReserved;
-+	uByte KeyData[1];	/* variable length */
-+} UPACKED wusb_key_desc_t;
-+
-+/* WUSB BOS Descriptor (Binary device Object Store) */
-+typedef struct wusb_bos_desc {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uWord wTotalLength;
-+	uByte bNumDeviceCaps;
-+} UPACKED wusb_bos_desc_t;
-+
-+#define USB_DEVICE_CAPABILITY_20_EXTENSION	0x02
-+typedef struct usb_dev_cap_20_ext_desc {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uByte bDevCapabilityType;
-+#define USB_20_EXT_LPM				0x02
-+	uDWord bmAttributes;
-+} UPACKED usb_dev_cap_20_ext_desc_t;
-+
-+#define USB_DEVICE_CAPABILITY_SS_USB		0x03
-+typedef struct usb_dev_cap_ss_usb {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uByte bDevCapabilityType;
-+#define USB_DC_SS_USB_LTM_CAPABLE		0x02
-+	uByte bmAttributes;
-+#define USB_DC_SS_USB_SPEED_SUPPORT_LOW		0x01
-+#define USB_DC_SS_USB_SPEED_SUPPORT_FULL	0x02
-+#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH	0x04
-+#define USB_DC_SS_USB_SPEED_SUPPORT_SS		0x08
-+	uWord wSpeedsSupported;
-+	uByte bFunctionalitySupport;
-+	uByte bU1DevExitLat;
-+	uWord wU2DevExitLat;
-+} UPACKED usb_dev_cap_ss_usb_t;
-+
-+#define USB_DEVICE_CAPABILITY_CONTAINER_ID	0x04
-+typedef struct usb_dev_cap_container_id {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uByte bDevCapabilityType;
-+	uByte bReserved;
-+	uByte containerID[16];
-+} UPACKED usb_dev_cap_container_id_t;
-+
-+/* Device Capability Type Codes */
-+#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
-+
-+/* Device Capability Descriptor */
-+typedef struct wusb_dev_cap_desc {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uByte bDevCapabilityType;
-+	uByte caps[1];	/* Variable length */
-+} UPACKED wusb_dev_cap_desc_t;
-+
-+/* Device Capability Descriptor */
-+typedef struct wusb_dev_cap_uwb_desc {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uByte bDevCapabilityType;
-+	uByte bmAttributes;
-+	uWord wPHYRates;	/* Bitmap */
-+	uByte bmTFITXPowerInfo;
-+	uByte bmFFITXPowerInfo;
-+	uWord bmBandGroup;
-+	uByte bReserved;
-+} UPACKED wusb_dev_cap_uwb_desc_t;
-+
-+/* Wireless USB Endpoint Companion Descriptor */
-+typedef struct wusb_endpoint_companion_desc {
-+	uByte bLength;
-+	uByte bDescriptorType;
-+	uByte bMaxBurst;
-+	uByte bMaxSequence;
-+	uWord wMaxStreamDelay;
-+	uWord wOverTheAirPacketSize;
-+	uByte bOverTheAirInterval;
-+	uByte bmCompAttributes;
-+} UPACKED wusb_endpoint_companion_desc_t;
-+
-+/* Wireless USB Numeric Association M1 Data Structure */
-+typedef struct wusb_m1_data {
-+	uByte version;
-+	uWord langId;
-+	uByte deviceFriendlyNameLength;
-+	uByte sha_256_m3[32];
-+	uByte deviceFriendlyName[256];
-+} UPACKED wusb_m1_data_t;
-+
-+typedef struct wusb_m2_data {
-+	uByte version;
-+	uWord langId;
-+	uByte hostFriendlyNameLength;
-+	uByte pkh[384];
-+	uByte hostFriendlyName[256];
-+} UPACKED wusb_m2_data_t;
-+
-+typedef struct wusb_m3_data {
-+	uByte pkd[384];
-+	uByte nd;
-+} UPACKED wusb_m3_data_t;
-+
-+typedef struct wusb_m4_data {
-+	uDWord _attributeTypeIdAndLength_1;
-+	uWord  associationTypeId;
-+
-+	uDWord _attributeTypeIdAndLength_2;
-+	uWord  associationSubTypeId;
-+
-+	uDWord _attributeTypeIdAndLength_3;
-+	uDWord length;
-+
-+	uDWord _attributeTypeIdAndLength_4;
-+	uDWord associationStatus;
-+
-+	uDWord _attributeTypeIdAndLength_5;
-+	uByte  chid[16];
-+
-+	uDWord _attributeTypeIdAndLength_6;
-+	uByte  cdid[16];
-+
-+	uDWord _attributeTypeIdAndLength_7;
-+	uByte  bandGroups[2];
-+} UPACKED wusb_m4_data_t;
-+
-+#ifdef _MSC_VER
-+#include <poppack.h>
-+#endif
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+#endif /* _USB_H_ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/Makefile
-@@ -0,0 +1,82 @@
-+#
-+# Makefile for DWC_otg Highspeed USB controller driver
-+#
-+
-+ifneq ($(KERNELRELEASE),)
-+
-+# Use the BUS_INTERFACE variable to compile the software for either
-+# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.
-+ifeq ($(BUS_INTERFACE),)
-+#	BUS_INTERFACE = -DPCI_INTERFACE
-+#	BUS_INTERFACE = -DLM_INTERFACE
-+        BUS_INTERFACE = -DPLATFORM_INTERFACE
-+endif
-+
-+#ccflags-y	+= -DDEBUG
-+#ccflags-y	+= -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs
-+
-+# Use one of the following flags to compile the software in host-only or
-+# device-only mode.
-+#ccflags-y        += -DDWC_HOST_ONLY
-+#ccflags-y        += -DDWC_DEVICE_ONLY
-+
-+ccflags-y	+= -Dlinux -DDWC_HS_ELECT_TST
-+#ccflags-y	+= -DDWC_EN_ISOC
-+ccflags-y   	+= -I$(obj)/../dwc_common_port
-+#ccflags-y   	+= -I$(PORTLIB)
-+ccflags-y   	+= -DDWC_LINUX
-+ccflags-y   	+= $(CFI)
-+ccflags-y	+= $(BUS_INTERFACE)
-+#ccflags-y	+= -DDWC_DEV_SRPCAP
-+
-+obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
-+
-+dwc_otg-objs	:= dwc_otg_driver.o dwc_otg_attr.o
-+dwc_otg-objs	+= dwc_otg_cil.o dwc_otg_cil_intr.o
-+dwc_otg-objs	+= dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
-+dwc_otg-objs	+= dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
-+dwc_otg-objs	+= dwc_otg_adp.o
-+dwc_otg-objs	+= dwc_otg_fiq_fsm.o
-+dwc_otg-objs	+= dwc_otg_fiq_stub.o
-+ifneq ($(CFI),)
-+dwc_otg-objs	+= dwc_otg_cfi.o
-+endif
-+
-+kernrelwd := $(subst ., ,$(KERNELRELEASE))
-+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
-+
-+ifneq ($(kernrel3),2.6.20)
-+ccflags-y += $(CPPFLAGS)
-+endif
-+
-+else
-+
-+PWD		:= $(shell pwd)
-+PORTLIB		:= $(PWD)/../dwc_common_port
-+
-+# Command paths
-+CTAGS		:= $(CTAGS)
-+DOXYGEN		:= $(DOXYGEN)
-+
-+default: portlib
-+	$(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+
-+install: default
-+	$(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
-+	$(MAKE) -C$(KDIR) M=$(PWD) modules_install
-+
-+portlib:
-+	$(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
-+	cp $(PORTLIB)/Module.symvers $(PWD)/
-+
-+docs:	$(wildcard *.[hc]) doc/doxygen.cfg
-+	$(DOXYGEN) doc/doxygen.cfg
-+
-+tags:	$(wildcard *.[hc])
-+	$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
-+
-+
-+clean:
-+	rm -rf   *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
-+
-+endif
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/doc/doxygen.cfg
-@@ -0,0 +1,224 @@
-+# Doxyfile 1.3.9.1
-+
-+#---------------------------------------------------------------------------
-+# Project related configuration options
-+#---------------------------------------------------------------------------
-+PROJECT_NAME           = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
-+PROJECT_NUMBER         = v3.00a
-+OUTPUT_DIRECTORY       = ./doc/
-+CREATE_SUBDIRS         = NO
-+OUTPUT_LANGUAGE        = English
-+BRIEF_MEMBER_DESC      = YES
-+REPEAT_BRIEF           = YES
-+ABBREVIATE_BRIEF       = "The $name class" \
-+                         "The $name widget" \
-+                         "The $name file" \
-+                         is \
-+                         provides \
-+                         specifies \
-+                         contains \
-+                         represents \
-+                         a \
-+                         an \
-+                         the
-+ALWAYS_DETAILED_SEC    = NO
-+INLINE_INHERITED_MEMB  = NO
-+FULL_PATH_NAMES        = NO
-+STRIP_FROM_PATH        =
-+STRIP_FROM_INC_PATH    =
-+SHORT_NAMES            = NO
-+JAVADOC_AUTOBRIEF      = YES
-+MULTILINE_CPP_IS_BRIEF = NO
-+INHERIT_DOCS           = YES
-+DISTRIBUTE_GROUP_DOC   = NO
-+TAB_SIZE               = 8
-+ALIASES                =
-+OPTIMIZE_OUTPUT_FOR_C  = YES
-+OPTIMIZE_OUTPUT_JAVA   = NO
-+SUBGROUPING            = YES
-+#---------------------------------------------------------------------------
-+# Build related configuration options
-+#---------------------------------------------------------------------------
-+EXTRACT_ALL            = NO
-+EXTRACT_PRIVATE        = YES
-+EXTRACT_STATIC         = YES
-+EXTRACT_LOCAL_CLASSES  = YES
-+EXTRACT_LOCAL_METHODS  = NO
-+HIDE_UNDOC_MEMBERS     = NO
-+HIDE_UNDOC_CLASSES     = NO
-+HIDE_FRIEND_COMPOUNDS  = NO
-+HIDE_IN_BODY_DOCS      = NO
-+INTERNAL_DOCS          = NO
-+CASE_SENSE_NAMES       = NO
-+HIDE_SCOPE_NAMES       = NO
-+SHOW_INCLUDE_FILES     = YES
-+INLINE_INFO            = YES
-+SORT_MEMBER_DOCS       = NO
-+SORT_BRIEF_DOCS        = NO
-+SORT_BY_SCOPE_NAME     = NO
-+GENERATE_TODOLIST      = YES
-+GENERATE_TESTLIST      = YES
-+GENERATE_BUGLIST       = YES
-+GENERATE_DEPRECATEDLIST= YES
-+ENABLED_SECTIONS       =
-+MAX_INITIALIZER_LINES  = 30
-+SHOW_USED_FILES        = YES
-+SHOW_DIRECTORIES       = YES
-+#---------------------------------------------------------------------------
-+# configuration options related to warning and progress messages
-+#---------------------------------------------------------------------------
-+QUIET                  = YES
-+WARNINGS               = YES
-+WARN_IF_UNDOCUMENTED   = NO
-+WARN_IF_DOC_ERROR      = YES
-+WARN_FORMAT            = "$file:$line: $text"
-+WARN_LOGFILE           =
-+#---------------------------------------------------------------------------
-+# configuration options related to the input files
-+#---------------------------------------------------------------------------
-+INPUT                  = .
-+FILE_PATTERNS          = *.c \
-+                         *.h \
-+                         ./linux/*.c \
-+                         ./linux/*.h
-+RECURSIVE              = NO
-+EXCLUDE                = ./test/ \
-+                         ./dwc_otg/.AppleDouble/
-+EXCLUDE_SYMLINKS       = YES
-+EXCLUDE_PATTERNS       = *.mod.*
-+EXAMPLE_PATH           =
-+EXAMPLE_PATTERNS       = *
-+EXAMPLE_RECURSIVE      = NO
-+IMAGE_PATH             =
-+INPUT_FILTER           =
-+FILTER_PATTERNS        =
-+FILTER_SOURCE_FILES    = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to source browsing
-+#---------------------------------------------------------------------------
-+SOURCE_BROWSER         = YES
-+INLINE_SOURCES         = NO
-+STRIP_CODE_COMMENTS    = YES
-+REFERENCED_BY_RELATION = NO
-+REFERENCES_RELATION    = NO
-+VERBATIM_HEADERS       = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the alphabetical class index
-+#---------------------------------------------------------------------------
-+ALPHABETICAL_INDEX     = NO
-+COLS_IN_ALPHA_INDEX    = 5
-+IGNORE_PREFIX          =
-+#---------------------------------------------------------------------------
-+# configuration options related to the HTML output
-+#---------------------------------------------------------------------------
-+GENERATE_HTML          = YES
-+HTML_OUTPUT            = html
-+HTML_FILE_EXTENSION    = .html
-+HTML_HEADER            =
-+HTML_FOOTER            =
-+HTML_STYLESHEET        =
-+HTML_ALIGN_MEMBERS     = YES
-+GENERATE_HTMLHELP      = NO
-+CHM_FILE               =
-+HHC_LOCATION           =
-+GENERATE_CHI           = NO
-+BINARY_TOC             = NO
-+TOC_EXPAND             = NO
-+DISABLE_INDEX          = NO
-+ENUM_VALUES_PER_LINE   = 4
-+GENERATE_TREEVIEW      = YES
-+TREEVIEW_WIDTH         = 250
-+#---------------------------------------------------------------------------
-+# configuration options related to the LaTeX output
-+#---------------------------------------------------------------------------
-+GENERATE_LATEX         = NO
-+LATEX_OUTPUT           = latex
-+LATEX_CMD_NAME         = latex
-+MAKEINDEX_CMD_NAME     = makeindex
-+COMPACT_LATEX          = NO
-+PAPER_TYPE             = a4wide
-+EXTRA_PACKAGES         =
-+LATEX_HEADER           =
-+PDF_HYPERLINKS         = NO
-+USE_PDFLATEX           = NO
-+LATEX_BATCHMODE        = NO
-+LATEX_HIDE_INDICES     = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the RTF output
-+#---------------------------------------------------------------------------
-+GENERATE_RTF           = NO
-+RTF_OUTPUT             = rtf
-+COMPACT_RTF            = NO
-+RTF_HYPERLINKS         = NO
-+RTF_STYLESHEET_FILE    =
-+RTF_EXTENSIONS_FILE    =
-+#---------------------------------------------------------------------------
-+# configuration options related to the man page output
-+#---------------------------------------------------------------------------
-+GENERATE_MAN           = NO
-+MAN_OUTPUT             = man
-+MAN_EXTENSION          = .3
-+MAN_LINKS              = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the XML output
-+#---------------------------------------------------------------------------
-+GENERATE_XML           = NO
-+XML_OUTPUT             = xml
-+XML_SCHEMA             =
-+XML_DTD                =
-+XML_PROGRAMLISTING     = YES
-+#---------------------------------------------------------------------------
-+# configuration options for the AutoGen Definitions output
-+#---------------------------------------------------------------------------
-+GENERATE_AUTOGEN_DEF   = NO
-+#---------------------------------------------------------------------------
-+# configuration options related to the Perl module output
-+#---------------------------------------------------------------------------
-+GENERATE_PERLMOD       = NO
-+PERLMOD_LATEX          = NO
-+PERLMOD_PRETTY         = YES
-+PERLMOD_MAKEVAR_PREFIX =
-+#---------------------------------------------------------------------------
-+# Configuration options related to the preprocessor
-+#---------------------------------------------------------------------------
-+ENABLE_PREPROCESSING   = YES
-+MACRO_EXPANSION        = YES
-+EXPAND_ONLY_PREDEF     = YES
-+SEARCH_INCLUDES        = YES
-+INCLUDE_PATH           =
-+INCLUDE_FILE_PATTERNS  =
-+PREDEFINED             = DEVICE_ATTR DWC_EN_ISOC
-+EXPAND_AS_DEFINED      = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
-+SKIP_FUNCTION_MACROS   = NO
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to external references
-+#---------------------------------------------------------------------------
-+TAGFILES               =
-+GENERATE_TAGFILE       =
-+ALLEXTERNALS           = NO
-+EXTERNAL_GROUPS        = YES
-+PERL_PATH              = /usr/bin/perl
-+#---------------------------------------------------------------------------
-+# Configuration options related to the dot tool
-+#---------------------------------------------------------------------------
-+CLASS_DIAGRAMS         = YES
-+HIDE_UNDOC_RELATIONS   = YES
-+HAVE_DOT               = NO
-+CLASS_GRAPH            = YES
-+COLLABORATION_GRAPH    = YES
-+UML_LOOK               = NO
-+TEMPLATE_RELATIONS     = NO
-+INCLUDE_GRAPH          = YES
-+INCLUDED_BY_GRAPH      = YES
-+CALL_GRAPH             = NO
-+GRAPHICAL_HIERARCHY    = YES
-+DOT_IMAGE_FORMAT       = png
-+DOT_PATH               =
-+DOTFILE_DIRS           =
-+MAX_DOT_GRAPH_DEPTH    = 1000
-+GENERATE_LEGEND        = YES
-+DOT_CLEANUP            = YES
-+#---------------------------------------------------------------------------
-+# Configuration::additions related to the search engine
-+#---------------------------------------------------------------------------
-+SEARCHENGINE           = NO
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dummy_audio.c
-@@ -0,0 +1,1574 @@
-+/*
-+ * zero.c -- Gadget Zero, for USB development
-+ *
-+ * Copyright (C) 2003-2004 David Brownell
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+/*
-+ * Gadget Zero only needs two bulk endpoints, and is an example of how you
-+ * can write a hardware-agnostic gadget driver running inside a USB device.
-+ *
-+ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
-+ * affect most of the driver.
-+ *
-+ * Use it with the Linux host/master side "usbtest" driver to get a basic
-+ * functional test of your device-side usb stack, or with "usb-skeleton".
-+ *
-+ * It supports two similar configurations.  One sinks whatever the usb host
-+ * writes, and in return sources zeroes.  The other loops whatever the host
-+ * writes back, so the host can read it.  Module options include:
-+ *
-+ *   buflen=N		default N=4096, buffer size used
-+ *   qlen=N		default N=32, how many buffers in the loopback queue
-+ *   loopdefault	default false, list loopback config first
-+ *
-+ * Many drivers will only have one configuration, letting them be much
-+ * simpler if they also don't support high speed operation (like this
-+ * driver does).
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/delay.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/slab.h>
-+#include <linux/smp_lock.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/timer.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/uts.h>
-+#include <linux/version.h>
-+#include <linux/device.h>
-+#include <linux/moduleparam.h>
-+#include <linux/proc_fs.h>
-+
-+#include <asm/byteorder.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/system.h>
-+#include <asm/unaligned.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
-+# include <linux/usb/ch9.h>
-+#else
-+# include <linux/usb_ch9.h>
-+#endif
-+
-+#include <linux/usb_gadget.h>
-+
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
-+{
-+	int	count = 0;
-+	u8	c;
-+	u16	uchar;
-+
-+	/* this insists on correct encodings, though not minimal ones.
-+	 * BUT it currently rejects legit 4-byte UTF-8 code points,
-+	 * which need surrogate pairs.  (Unicode 3.1 can use them.)
-+	 */
-+	while (len != 0 && (c = (u8) *s++) != 0) {
-+		if (unlikely(c & 0x80)) {
-+			// 2-byte sequence:
-+			// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
-+			if ((c & 0xe0) == 0xc0) {
-+				uchar = (c & 0x1f) << 6;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c;
-+
-+			// 3-byte sequence (most CJKV characters):
-+			// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
-+			} else if ((c & 0xf0) == 0xe0) {
-+				uchar = (c & 0x0f) << 12;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c << 6;
-+
-+				c = (u8) *s++;
-+				if ((c & 0xc0) != 0xc0)
-+					goto fail;
-+				c &= 0x3f;
-+				uchar |= c;
-+
-+				/* no bogus surrogates */
-+				if (0xd800 <= uchar && uchar <= 0xdfff)
-+					goto fail;
-+
-+			// 4-byte sequence (surrogate pairs, currently rare):
-+			// 11101110wwwwzzzzyy + 110111yyyyxxxxxx
-+			//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
-+			// (uuuuu = wwww + 1)
-+			// FIXME accept the surrogate code points (only)
-+
-+			} else
-+				goto fail;
-+		} else
-+			uchar = c;
-+		put_unaligned (cpu_to_le16 (uchar), cp++);
-+		count++;
-+		len--;
-+	}
-+	return count;
-+fail:
-+	return -1;
-+}
-+
-+
-+/**
-+ * usb_gadget_get_string - fill out a string descriptor
-+ * @table: of c strings encoded using UTF-8
-+ * @id: string id, from low byte of wValue in get string descriptor
-+ * @buf: at least 256 bytes
-+ *
-+ * Finds the UTF-8 string matching the ID, and converts it into a
-+ * string descriptor in utf16-le.
-+ * Returns length of descriptor (always even) or negative errno
-+ *
-+ * If your driver needs stings in multiple languages, you'll probably
-+ * "switch (wIndex) { ... }"  in your ep0 string descriptor logic,
-+ * using this routine after choosing which set of UTF-8 strings to use.
-+ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
-+ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
-+ * characters (which are also widely used in C strings).
-+ */
-+int
-+usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
-+{
-+	struct usb_string	*s;
-+	int			len;
-+
-+	/* descriptor 0 has the language id */
-+	if (id == 0) {
-+		buf [0] = 4;
-+		buf [1] = USB_DT_STRING;
-+		buf [2] = (u8) table->language;
-+		buf [3] = (u8) (table->language >> 8);
-+		return 4;
-+	}
-+	for (s = table->strings; s && s->s; s++)
-+		if (s->id == id)
-+			break;
-+
-+	/* unrecognized: stall. */
-+	if (!s || !s->s)
-+		return -EINVAL;
-+
-+	/* string descriptors have length, tag, then UTF16-LE text */
-+	len = min ((size_t) 126, strlen (s->s));
-+	memset (buf + 2, 0, 2 * len);	/* zero all the bytes */
-+	len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
-+	if (len < 0)
-+		return -EINVAL;
-+	buf [0] = (len + 1) * 2;
-+	buf [1] = USB_DT_STRING;
-+	return buf [0];
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+/**
-+ * usb_descriptor_fillbuf - fill buffer with descriptors
-+ * @buf: Buffer to be filled
-+ * @buflen: Size of buf
-+ * @src: Array of descriptor pointers, terminated by null pointer.
-+ *
-+ * Copies descriptors into the buffer, returning the length or a
-+ * negative error code if they can't all be copied.  Useful when
-+ * assembling descriptors for an associated set of interfaces used
-+ * as part of configuring a composite device; or in other cases where
-+ * sets of descriptors need to be marshaled.
-+ */
-+int
-+usb_descriptor_fillbuf(void *buf, unsigned buflen,
-+		const struct usb_descriptor_header **src)
-+{
-+	u8	*dest = buf;
-+
-+	if (!src)
-+		return -EINVAL;
-+
-+	/* fill buffer from src[] until null descriptor ptr */
-+	for (; 0 != *src; src++) {
-+		unsigned		len = (*src)->bLength;
-+
-+		if (len > buflen)
-+			return -EINVAL;
-+		memcpy(dest, *src, len);
-+		buflen -= len;
-+		dest += len;
-+	}
-+	return dest - (u8 *)buf;
-+}
-+
-+
-+/**
-+ * usb_gadget_config_buf - builts a complete configuration descriptor
-+ * @config: Header for the descriptor, including characteristics such
-+ *	as power requirements and number of interfaces.
-+ * @desc: Null-terminated vector of pointers to the descriptors (interface,
-+ *	endpoint, etc) defining all functions in this device configuration.
-+ * @buf: Buffer for the resulting configuration descriptor.
-+ * @length: Length of buffer.  If this is not big enough to hold the
-+ *	entire configuration descriptor, an error code will be returned.
-+ *
-+ * This copies descriptors into the response buffer, building a descriptor
-+ * for that configuration.  It returns the buffer length or a negative
-+ * status code.  The config.wTotalLength field is set to match the length
-+ * of the result, but other descriptor fields (including power usage and
-+ * interface count) must be set by the caller.
-+ *
-+ * Gadget drivers could use this when constructing a config descriptor
-+ * in response to USB_REQ_GET_DESCRIPTOR.  They will need to patch the
-+ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
-+ */
-+int usb_gadget_config_buf(
-+	const struct usb_config_descriptor	*config,
-+	void					*buf,
-+	unsigned				length,
-+	const struct usb_descriptor_header	**desc
-+)
-+{
-+	struct usb_config_descriptor		*cp = buf;
-+	int					len;
-+
-+	/* config descriptor first */
-+	if (length < USB_DT_CONFIG_SIZE || !desc)
-+		return -EINVAL;
-+	*cp = *config;
-+
-+	/* then interface/endpoint/class/vendor/... */
-+	len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
-+			length - USB_DT_CONFIG_SIZE, desc);
-+	if (len < 0)
-+		return len;
-+	len += USB_DT_CONFIG_SIZE;
-+	if (len > 0xffff)
-+		return -EINVAL;
-+
-+	/* patch up the config descriptor */
-+	cp->bLength = USB_DT_CONFIG_SIZE;
-+	cp->bDescriptorType = USB_DT_CONFIG;
-+	cp->wTotalLength = cpu_to_le16(len);
-+	cp->bmAttributes |= USB_CONFIG_ATT_ONE;
-+	return len;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+/*-------------------------------------------------------------------------*/
-+
-+
-+#define RBUF_LEN (1024*1024)
-+static int rbuf_start;
-+static int rbuf_len;
-+static __u8 rbuf[RBUF_LEN];
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define DRIVER_VERSION		"St Patrick's Day 2004"
-+
-+static const char shortname [] = "zero";
-+static const char longname [] = "YAMAHA YST-MS35D USB Speaker  ";
-+
-+static const char source_sink [] = "source and sink data";
-+static const char loopback [] = "loop input to output";
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * driver assumes self-powered hardware, and
-+ * has no way for users to trigger remote wakeup.
-+ *
-+ * this version autoconfigures as much as possible,
-+ * which is reasonable for most "bulk-only" drivers.
-+ */
-+static const char *EP_IN_NAME;		/* source */
-+static const char *EP_OUT_NAME;		/* sink */
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* big enough to hold our biggest descriptor */
-+#define USB_BUFSIZ	512
-+
-+struct zero_dev {
-+	spinlock_t		lock;
-+	struct usb_gadget	*gadget;
-+	struct usb_request	*req;		/* for control responses */
-+
-+	/* when configured, we have one of two configs:
-+	 * - source data (in to host) and sink it (out from host)
-+	 * - or loop it back (out from host back in to host)
-+	 */
-+	u8			config;
-+	struct usb_ep		*in_ep, *out_ep;
-+
-+	/* autoresume timer */
-+	struct timer_list	resume;
-+};
-+
-+#define xprintk(d,level,fmt,args...) \
-+	dev_printk(level , &(d)->gadget->dev , fmt , ## args)
-+
-+#ifdef DEBUG
-+#define DBG(dev,fmt,args...) \
-+	xprintk(dev , KERN_DEBUG , fmt , ## args)
-+#else
-+#define DBG(dev,fmt,args...) \
-+	do { } while (0)
-+#endif /* DEBUG */
-+
-+#ifdef VERBOSE
-+#define VDBG	DBG
-+#else
-+#define VDBG(dev,fmt,args...) \
-+	do { } while (0)
-+#endif /* VERBOSE */
-+
-+#define ERROR(dev,fmt,args...) \
-+	xprintk(dev , KERN_ERR , fmt , ## args)
-+#define WARN(dev,fmt,args...) \
-+	xprintk(dev , KERN_WARNING , fmt , ## args)
-+#define INFO(dev,fmt,args...) \
-+	xprintk(dev , KERN_INFO , fmt , ## args)
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static unsigned buflen = 4096;
-+static unsigned qlen = 32;
-+static unsigned pattern = 0;
-+
-+module_param (buflen, uint, S_IRUGO|S_IWUSR);
-+module_param (qlen, uint, S_IRUGO|S_IWUSR);
-+module_param (pattern, uint, S_IRUGO|S_IWUSR);
-+
-+/*
-+ * if it's nonzero, autoresume says how many seconds to wait
-+ * before trying to wake up the host after suspend.
-+ */
-+static unsigned autoresume = 0;
-+module_param (autoresume, uint, 0);
-+
-+/*
-+ * Normally the "loopback" configuration is second (index 1) so
-+ * it's not the default.  Here's where to change that order, to
-+ * work better with hosts where config changes are problematic.
-+ * Or controllers (like superh) that only support one config.
-+ */
-+static int loopdefault = 0;
-+
-+module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Thanks to NetChip Technologies for donating this product ID.
-+ *
-+ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!
-+ * Instead:  allocate your own, using normal USB-IF procedures.
-+ */
-+#ifndef	CONFIG_USB_ZERO_HNPTEST
-+#define DRIVER_VENDOR_NUM	0x0525		/* NetChip */
-+#define DRIVER_PRODUCT_NUM	0xa4a0		/* Linux-USB "Gadget Zero" */
-+#else
-+#define DRIVER_VENDOR_NUM	0x1a0a		/* OTG test device IDs */
-+#define DRIVER_PRODUCT_NUM	0xbadd
-+#endif
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * DESCRIPTORS ... most are static, but strings and (full)
-+ * configuration descriptors are built on demand.
-+ */
-+
-+/*
-+#define STRING_MANUFACTURER		25
-+#define STRING_PRODUCT			42
-+#define STRING_SERIAL			101
-+*/
-+#define STRING_MANUFACTURER		1
-+#define STRING_PRODUCT			2
-+#define STRING_SERIAL			3
-+
-+#define STRING_SOURCE_SINK		250
-+#define STRING_LOOPBACK			251
-+
-+/*
-+ * This device advertises two configurations; these numbers work
-+ * on a pxa250 as well as more flexible hardware.
-+ */
-+#define	CONFIG_SOURCE_SINK	3
-+#define	CONFIG_LOOPBACK		2
-+
-+/*
-+static struct usb_device_descriptor
-+device_desc = {
-+	.bLength =		sizeof device_desc,
-+	.bDescriptorType =	USB_DT_DEVICE,
-+
-+	.bcdUSB =		__constant_cpu_to_le16 (0x0200),
-+	.bDeviceClass =		USB_CLASS_VENDOR_SPEC,
-+
-+	.idVendor =		__constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
-+	.idProduct =		__constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
-+	.iManufacturer =	STRING_MANUFACTURER,
-+	.iProduct =		STRING_PRODUCT,
-+	.iSerialNumber =	STRING_SERIAL,
-+	.bNumConfigurations =	2,
-+};
-+*/
-+static struct usb_device_descriptor
-+device_desc = {
-+	.bLength =		sizeof device_desc,
-+	.bDescriptorType =	USB_DT_DEVICE,
-+	.bcdUSB =		__constant_cpu_to_le16 (0x0100),
-+	.bDeviceClass =		USB_CLASS_PER_INTERFACE,
-+	.bDeviceSubClass =      0,
-+	.bDeviceProtocol =      0,
-+	.bMaxPacketSize0 =      64,
-+	.bcdDevice =            __constant_cpu_to_le16 (0x0100),
-+	.idVendor =		__constant_cpu_to_le16 (0x0499),
-+	.idProduct =		__constant_cpu_to_le16 (0x3002),
-+	.iManufacturer =	STRING_MANUFACTURER,
-+	.iProduct =		STRING_PRODUCT,
-+	.iSerialNumber =	STRING_SERIAL,
-+	.bNumConfigurations =	1,
-+};
-+
-+static struct usb_config_descriptor
-+z_config = {
-+	.bLength =		sizeof z_config,
-+	.bDescriptorType =	USB_DT_CONFIG,
-+
-+	/* compute wTotalLength on the fly */
-+	.bNumInterfaces =	2,
-+	.bConfigurationValue =	1,
-+	.iConfiguration =	0,
-+	.bmAttributes =		0x40,
-+	.bMaxPower =		0,	/* self-powered */
-+};
-+
-+
-+static struct usb_otg_descriptor
-+otg_descriptor = {
-+	.bLength =		sizeof otg_descriptor,
-+	.bDescriptorType =	USB_DT_OTG,
-+
-+	.bmAttributes =		USB_OTG_SRP,
-+};
-+
-+/* one interface in each configuration */
-+#ifdef	CONFIG_USB_GADGET_DUALSPEED
-+
-+/*
-+ * usb 2.0 devices need to expose both high speed and full speed
-+ * descriptors, unless they only run at full speed.
-+ *
-+ * that means alternate endpoint descriptors (bigger packets)
-+ * and a "device qualifier" ... plus more construction options
-+ * for the config descriptor.
-+ */
-+
-+static struct usb_qualifier_descriptor
-+dev_qualifier = {
-+	.bLength =		sizeof dev_qualifier,
-+	.bDescriptorType =	USB_DT_DEVICE_QUALIFIER,
-+
-+	.bcdUSB =		__constant_cpu_to_le16 (0x0200),
-+	.bDeviceClass =		USB_CLASS_VENDOR_SPEC,
-+
-+	.bNumConfigurations =	2,
-+};
-+
-+
-+struct usb_cs_as_general_descriptor {
-+	__u8  bLength;
-+	__u8  bDescriptorType;
-+
-+	__u8  bDescriptorSubType;
-+	__u8  bTerminalLink;
-+	__u8  bDelay;
-+	__u16  wFormatTag;
-+} __attribute__ ((packed));
-+
-+struct usb_cs_as_format_descriptor {
-+	__u8  bLength;
-+	__u8  bDescriptorType;
-+
-+	__u8  bDescriptorSubType;
-+	__u8  bFormatType;
-+	__u8  bNrChannels;
-+	__u8  bSubframeSize;
-+	__u8  bBitResolution;
-+	__u8  bSamfreqType;
-+	__u8  tLowerSamFreq[3];
-+	__u8  tUpperSamFreq[3];
-+} __attribute__ ((packed));
-+
-+static const struct usb_interface_descriptor
-+z_audio_control_if_desc = {
-+	.bLength =		sizeof z_audio_control_if_desc,
-+	.bDescriptorType =	USB_DT_INTERFACE,
-+	.bInterfaceNumber = 0,
-+	.bAlternateSetting = 0,
-+	.bNumEndpoints = 0,
-+	.bInterfaceClass = USB_CLASS_AUDIO,
-+	.bInterfaceSubClass = 0x1,
-+	.bInterfaceProtocol = 0,
-+	.iInterface = 0,
-+};
-+
-+static const struct usb_interface_descriptor
-+z_audio_if_desc = {
-+	.bLength =		sizeof z_audio_if_desc,
-+	.bDescriptorType =	USB_DT_INTERFACE,
-+	.bInterfaceNumber = 1,
-+	.bAlternateSetting = 0,
-+	.bNumEndpoints = 0,
-+	.bInterfaceClass = USB_CLASS_AUDIO,
-+	.bInterfaceSubClass = 0x2,
-+	.bInterfaceProtocol = 0,
-+	.iInterface = 0,
-+};
-+
-+static const struct usb_interface_descriptor
-+z_audio_if_desc2 = {
-+	.bLength =		sizeof z_audio_if_desc,
-+	.bDescriptorType =	USB_DT_INTERFACE,
-+	.bInterfaceNumber = 1,
-+	.bAlternateSetting = 1,
-+	.bNumEndpoints = 1,
-+	.bInterfaceClass = USB_CLASS_AUDIO,
-+	.bInterfaceSubClass = 0x2,
-+	.bInterfaceProtocol = 0,
-+	.iInterface = 0,
-+};
-+
-+static const struct usb_cs_as_general_descriptor
-+z_audio_cs_as_if_desc = {
-+	.bLength = 7,
-+	.bDescriptorType = 0x24,
-+
-+	.bDescriptorSubType = 0x01,
-+	.bTerminalLink = 0x01,
-+	.bDelay = 0x0,
-+	.wFormatTag = __constant_cpu_to_le16 (0x0001)
-+};
-+
-+
-+static const struct usb_cs_as_format_descriptor
-+z_audio_cs_as_format_desc = {
-+	.bLength = 0xe,
-+	.bDescriptorType = 0x24,
-+
-+	.bDescriptorSubType = 2,
-+	.bFormatType = 1,
-+	.bNrChannels = 1,
-+	.bSubframeSize = 1,
-+	.bBitResolution = 8,
-+	.bSamfreqType = 0,
-+	.tLowerSamFreq = {0x7e, 0x13, 0x00},
-+	.tUpperSamFreq = {0xe2, 0xd6, 0x00},
-+};
-+
-+static const struct usb_endpoint_descriptor
-+z_iso_ep = {
-+	.bLength = 0x09,
-+	.bDescriptorType = 0x05,
-+	.bEndpointAddress = 0x04,
-+	.bmAttributes = 0x09,
-+	.wMaxPacketSize = 0x0038,
-+	.bInterval = 0x01,
-+	.bRefresh = 0x00,
-+	.bSynchAddress = 0x00,
-+};
-+
-+static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+// 9 bytes
-+static char z_ac_interface_header_desc[] =
-+{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
-+
-+// 12 bytes
-+static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
-+		     0x03, 0x00, 0x00, 0x00};
-+// 13 bytes
-+static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
-+		     0x02, 0x00, 0x02, 0x00, 0x00};
-+// 9 bytes
-+static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
-+		     0x00};
-+
-+static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
-+		      0x00};
-+
-+static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
-+		      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
-+		      0x00};
-+
-+static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
-+		      0x00};
-+
-+static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
-+		      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
-+		      0x00};
-+
-+static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
-+		       0x00};
-+
-+static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
-+		       0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
-+		       0x00};
-+
-+static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
-+		       0x00};
-+
-+static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
-+		       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
-+		       0x00};
-+
-+static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
-+		       0x00};
-+
-+static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
-+
-+static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
-+		       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
-+
-+static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
-+		       0x00};
-+
-+static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
-+
-+
-+
-+static const struct usb_descriptor_header *z_function [] = {
-+	(struct usb_descriptor_header *) &z_audio_control_if_desc,
-+	(struct usb_descriptor_header *) &z_ac_interface_header_desc,
-+	(struct usb_descriptor_header *) &z_0,
-+	(struct usb_descriptor_header *) &z_1,
-+	(struct usb_descriptor_header *) &z_2,
-+	(struct usb_descriptor_header *) &z_audio_if_desc,
-+	(struct usb_descriptor_header *) &z_audio_if_desc2,
-+	(struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
-+	(struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
-+	(struct usb_descriptor_header *) &z_iso_ep,
-+	(struct usb_descriptor_header *) &z_iso_ep2,
-+	(struct usb_descriptor_header *) &za_0,
-+	(struct usb_descriptor_header *) &za_1,
-+	(struct usb_descriptor_header *) &za_2,
-+	(struct usb_descriptor_header *) &za_3,
-+	(struct usb_descriptor_header *) &za_4,
-+	(struct usb_descriptor_header *) &za_5,
-+	(struct usb_descriptor_header *) &za_6,
-+	(struct usb_descriptor_header *) &za_7,
-+	(struct usb_descriptor_header *) &za_8,
-+	(struct usb_descriptor_header *) &za_9,
-+	(struct usb_descriptor_header *) &za_10,
-+	(struct usb_descriptor_header *) &za_11,
-+	(struct usb_descriptor_header *) &za_12,
-+	(struct usb_descriptor_header *) &za_13,
-+	(struct usb_descriptor_header *) &za_14,
-+	(struct usb_descriptor_header *) &za_15,
-+	(struct usb_descriptor_header *) &za_16,
-+	(struct usb_descriptor_header *) &za_17,
-+	(struct usb_descriptor_header *) &za_18,
-+	(struct usb_descriptor_header *) &za_19,
-+	(struct usb_descriptor_header *) &za_20,
-+	(struct usb_descriptor_header *) &za_21,
-+	(struct usb_descriptor_header *) &za_22,
-+	(struct usb_descriptor_header *) &za_23,
-+	(struct usb_descriptor_header *) &za_24,
-+	NULL,
-+};
-+
-+/* maxpacket and other transfer characteristics vary by speed. */
-+#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
-+
-+#else
-+
-+/* if there's no high speed support, maxpacket doesn't change. */
-+#define ep_desc(g,hs,fs) fs
-+
-+#endif	/* !CONFIG_USB_GADGET_DUALSPEED */
-+
-+static char				manufacturer [40];
-+//static char				serial [40];
-+static char				serial [] = "Ser 00 em";
-+
-+/* static strings, in UTF-8 */
-+static struct usb_string		strings [] = {
-+	{ STRING_MANUFACTURER, manufacturer, },
-+	{ STRING_PRODUCT, longname, },
-+	{ STRING_SERIAL, serial, },
-+	{ STRING_LOOPBACK, loopback, },
-+	{ STRING_SOURCE_SINK, source_sink, },
-+	{  }			/* end of list */
-+};
-+
-+static struct usb_gadget_strings	stringtab = {
-+	.language	= 0x0409,	/* en-us */
-+	.strings	= strings,
-+};
-+
-+/*
-+ * config descriptors are also handcrafted.  these must agree with code
-+ * that sets configurations, and with code managing interfaces and their
-+ * altsettings.  other complexity may come from:
-+ *
-+ *  - high speed support, including "other speed config" rules
-+ *  - multiple configurations
-+ *  - interfaces with alternate settings
-+ *  - embedded class or vendor-specific descriptors
-+ *
-+ * this handles high speed, and has a second config that could as easily
-+ * have been an alternate interface setting (on most hardware).
-+ *
-+ * NOTE:  to demonstrate (and test) more USB capabilities, this driver
-+ * should include an altsetting to test interrupt transfers, including
-+ * high bandwidth modes at high speed.  (Maybe work like Intel's test
-+ * device?)
-+ */
-+static int
-+config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
-+{
-+	int len;
-+	const struct usb_descriptor_header **function;
-+
-+	function = z_function;
-+	len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
-+	if (len < 0)
-+		return len;
-+	((struct usb_config_descriptor *) buf)->bDescriptorType = type;
-+	return len;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_request *
-+alloc_ep_req (struct usb_ep *ep, unsigned length)
-+{
-+	struct usb_request	*req;
-+
-+	req = usb_ep_alloc_request (ep, GFP_ATOMIC);
-+	if (req) {
-+		req->length = length;
-+		req->buf = usb_ep_alloc_buffer (ep, length,
-+				&req->dma, GFP_ATOMIC);
-+		if (!req->buf) {
-+			usb_ep_free_request (ep, req);
-+			req = NULL;
-+		}
-+	}
-+	return req;
-+}
-+
-+static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
-+{
-+	if (req->buf)
-+		usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
-+	usb_ep_free_request (ep, req);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* optionally require specific source/sink data patterns  */
-+
-+static int
-+check_read_data (
-+	struct zero_dev		*dev,
-+	struct usb_ep		*ep,
-+	struct usb_request	*req
-+)
-+{
-+	unsigned	i;
-+	u8		*buf = req->buf;
-+
-+	for (i = 0; i < req->actual; i++, buf++) {
-+		switch (pattern) {
-+		/* all-zeroes has no synchronization issues */
-+		case 0:
-+			if (*buf == 0)
-+				continue;
-+			break;
-+		/* mod63 stays in sync with short-terminated transfers,
-+		 * or otherwise when host and gadget agree on how large
-+		 * each usb transfer request should be.  resync is done
-+		 * with set_interface or set_config.
-+		 */
-+		case 1:
-+			if (*buf == (u8)(i % 63))
-+				continue;
-+			break;
-+		}
-+		ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
-+		usb_ep_set_halt (ep);
-+		return -EINVAL;
-+	}
-+	return 0;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void zero_reset_config (struct zero_dev *dev)
-+{
-+	if (dev->config == 0)
-+		return;
-+
-+	DBG (dev, "reset config\n");
-+
-+	/* just disable endpoints, forcing completion of pending i/o.
-+	 * all our completion handlers free their requests in this case.
-+	 */
-+	if (dev->in_ep) {
-+		usb_ep_disable (dev->in_ep);
-+		dev->in_ep = NULL;
-+	}
-+	if (dev->out_ep) {
-+		usb_ep_disable (dev->out_ep);
-+		dev->out_ep = NULL;
-+	}
-+	dev->config = 0;
-+	del_timer (&dev->resume);
-+}
-+
-+#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
-+
-+static void
-+zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
-+{
-+	struct zero_dev	*dev = ep->driver_data;
-+	int		status = req->status;
-+	int i, j;
-+
-+	switch (status) {
-+
-+	case 0: 			/* normal completion? */
-+		//printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
-+		for (i=0, j=rbuf_start; i<req->actual; i++) {
-+			//printk ("%02x ", ((__u8*)req->buf)[i]);
-+			rbuf[j] = ((__u8*)req->buf)[i];
-+			j++;
-+			if (j >= RBUF_LEN) j=0;
-+		}
-+		rbuf_start = j;
-+		//printk ("\n\n");
-+
-+		if (rbuf_len < RBUF_LEN) {
-+			rbuf_len += req->actual;
-+			if (rbuf_len > RBUF_LEN) {
-+				rbuf_len = RBUF_LEN;
-+			}
-+		}
-+
-+		break;
-+
-+	/* this endpoint is normally active while we're configured */
-+	case -ECONNABORTED: 		/* hardware forced ep reset */
-+	case -ECONNRESET:		/* request dequeued */
-+	case -ESHUTDOWN:		/* disconnect from host */
-+		VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
-+				req->actual, req->length);
-+		if (ep == dev->out_ep)
-+			check_read_data (dev, ep, req);
-+		free_ep_req (ep, req);
-+		return;
-+
-+	case -EOVERFLOW:		/* buffer overrun on read means that
-+					 * we didn't provide a big enough
-+					 * buffer.
-+					 */
-+	default:
-+#if 1
-+		DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
-+				status, req->actual, req->length);
-+#endif
-+	case -EREMOTEIO:		/* short read */
-+		break;
-+	}
-+
-+	status = usb_ep_queue (ep, req, GFP_ATOMIC);
-+	if (status) {
-+		ERROR (dev, "kill %s:  resubmit %d bytes --> %d\n",
-+				ep->name, req->length, status);
-+		usb_ep_set_halt (ep);
-+		/* FIXME recover later ... somehow */
-+	}
-+}
-+
-+static struct usb_request *
-+zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
-+{
-+	struct usb_request	*req;
-+	int			status;
-+
-+	req = alloc_ep_req (ep, 512);
-+	if (!req)
-+		return NULL;
-+
-+	req->complete = zero_isoc_complete;
-+
-+	status = usb_ep_queue (ep, req, gfp_flags);
-+	if (status) {
-+		struct zero_dev	*dev = ep->driver_data;
-+
-+		ERROR (dev, "start %s --> %d\n", ep->name, status);
-+		free_ep_req (ep, req);
-+		req = NULL;
-+	}
-+
-+	return req;
-+}
-+
-+/* change our operational config.  this code must agree with the code
-+ * that returns config descriptors, and altsetting code.
-+ *
-+ * it's also responsible for power management interactions. some
-+ * configurations might not work with our current power sources.
-+ *
-+ * note that some device controller hardware will constrain what this
-+ * code can do, perhaps by disallowing more than one configuration or
-+ * by limiting configuration choices (like the pxa2xx).
-+ */
-+static int
-+zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
-+{
-+	int			result = 0;
-+	struct usb_gadget	*gadget = dev->gadget;
-+	const struct usb_endpoint_descriptor	*d;
-+	struct usb_ep		*ep;
-+
-+	if (number == dev->config)
-+		return 0;
-+
-+	zero_reset_config (dev);
-+
-+	gadget_for_each_ep (ep, gadget) {
-+
-+		if (strcmp (ep->name, "ep4") == 0) {
-+
-+			d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
-+			result = usb_ep_enable (ep, d);
-+
-+			if (result == 0) {
-+				ep->driver_data = dev;
-+				dev->in_ep = ep;
-+
-+				if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
-+
-+					dev->in_ep = ep;
-+					continue;
-+				}
-+
-+				usb_ep_disable (ep);
-+				result = -EIO;
-+			}
-+		}
-+
-+	}
-+
-+	dev->config = number;
-+	return result;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
-+{
-+	if (req->status || req->actual != req->length)
-+		DBG ((struct zero_dev *) ep->driver_data,
-+				"setup complete --> %d, %d/%d\n",
-+				req->status, req->actual, req->length);
-+}
-+
-+/*
-+ * The setup() callback implements all the ep0 functionality that's
-+ * not handled lower down, in hardware or the hardware driver (like
-+ * device and endpoint feature flags, and their status).  It's all
-+ * housekeeping for the gadget function we're implementing.  Most of
-+ * the work is in config-specific setup.
-+ */
-+static int
-+zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
-+{
-+	struct zero_dev		*dev = get_gadget_data (gadget);
-+	struct usb_request	*req = dev->req;
-+	int			value = -EOPNOTSUPP;
-+
-+	/* usually this stores reply data in the pre-allocated ep0 buffer,
-+	 * but config change events will reconfigure hardware.
-+	 */
-+	req->zero = 0;
-+	switch (ctrl->bRequest) {
-+
-+	case USB_REQ_GET_DESCRIPTOR:
-+
-+		switch (ctrl->wValue >> 8) {
-+
-+		case USB_DT_DEVICE:
-+			value = min (ctrl->wLength, (u16) sizeof device_desc);
-+			memcpy (req->buf, &device_desc, value);
-+			break;
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+		case USB_DT_DEVICE_QUALIFIER:
-+			if (!gadget->is_dualspeed)
-+				break;
-+			value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
-+			memcpy (req->buf, &dev_qualifier, value);
-+			break;
-+
-+		case USB_DT_OTHER_SPEED_CONFIG:
-+			if (!gadget->is_dualspeed)
-+				break;
-+			// FALLTHROUGH
-+#endif /* CONFIG_USB_GADGET_DUALSPEED */
-+		case USB_DT_CONFIG:
-+			value = config_buf (gadget, req->buf,
-+					ctrl->wValue >> 8,
-+					ctrl->wValue & 0xff);
-+			if (value >= 0)
-+				value = min (ctrl->wLength, (u16) value);
-+			break;
-+
-+		case USB_DT_STRING:
-+			/* wIndex == language code.
-+			 * this driver only handles one language, you can
-+			 * add string tables for other languages, using
-+			 * any UTF-8 characters
-+			 */
-+			value = usb_gadget_get_string (&stringtab,
-+					ctrl->wValue & 0xff, req->buf);
-+			if (value >= 0) {
-+				value = min (ctrl->wLength, (u16) value);
-+			}
-+			break;
-+		}
-+		break;
-+
-+	/* currently two configs, two speeds */
-+	case USB_REQ_SET_CONFIGURATION:
-+		if (ctrl->bRequestType != 0)
-+			goto unknown;
-+
-+		spin_lock (&dev->lock);
-+		value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
-+		spin_unlock (&dev->lock);
-+		break;
-+	case USB_REQ_GET_CONFIGURATION:
-+		if (ctrl->bRequestType != USB_DIR_IN)
-+			goto unknown;
-+		*(u8 *)req->buf = dev->config;
-+		value = min (ctrl->wLength, (u16) 1);
-+		break;
-+
-+	/* until we add altsetting support, or other interfaces,
-+	 * only 0/0 are possible.  pxa2xx only supports 0/0 (poorly)
-+	 * and already killed pending endpoint I/O.
-+	 */
-+	case USB_REQ_SET_INTERFACE:
-+
-+		if (ctrl->bRequestType != USB_RECIP_INTERFACE)
-+			goto unknown;
-+		spin_lock (&dev->lock);
-+		if (dev->config) {
-+			u8		config = dev->config;
-+
-+			/* resets interface configuration, forgets about
-+			 * previous transaction state (queued bufs, etc)
-+			 * and re-inits endpoint state (toggle etc)
-+			 * no response queued, just zero status == success.
-+			 * if we had more than one interface we couldn't
-+			 * use this "reset the config" shortcut.
-+			 */
-+			zero_reset_config (dev);
-+			zero_set_config (dev, config, GFP_ATOMIC);
-+			value = 0;
-+		}
-+		spin_unlock (&dev->lock);
-+		break;
-+	case USB_REQ_GET_INTERFACE:
-+		if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
-+			value = ctrl->wLength;
-+			break;
-+		}
-+		else {
-+			if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
-+				goto unknown;
-+			if (!dev->config)
-+				break;
-+			if (ctrl->wIndex != 0) {
-+				value = -EDOM;
-+				break;
-+			}
-+			*(u8 *)req->buf = 0;
-+			value = min (ctrl->wLength, (u16) 1);
-+		}
-+		break;
-+
-+	/*
-+	 * These are the same vendor-specific requests supported by
-+	 * Intel's USB 2.0 compliance test devices.  We exceed that
-+	 * device spec by allowing multiple-packet requests.
-+	 */
-+	case 0x5b:	/* control WRITE test -- fill the buffer */
-+		if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
-+			goto unknown;
-+		if (ctrl->wValue || ctrl->wIndex)
-+			break;
-+		/* just read that many bytes into the buffer */
-+		if (ctrl->wLength > USB_BUFSIZ)
-+			break;
-+		value = ctrl->wLength;
-+		break;
-+	case 0x5c:	/* control READ test -- return the buffer */
-+		if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
-+			goto unknown;
-+		if (ctrl->wValue || ctrl->wIndex)
-+			break;
-+		/* expect those bytes are still in the buffer; send back */
-+		if (ctrl->wLength > USB_BUFSIZ
-+				|| ctrl->wLength != req->length)
-+			break;
-+		value = ctrl->wLength;
-+		break;
-+
-+	case 0x01: // SET_CUR
-+	case 0x02:
-+	case 0x03:
-+	case 0x04:
-+	case 0x05:
-+		value = ctrl->wLength;
-+		break;
-+	case 0x81:
-+		switch (ctrl->wValue) {
-+		case 0x0201:
-+		case 0x0202:
-+			((u8*)req->buf)[0] = 0x00;
-+			((u8*)req->buf)[1] = 0xe3;
-+			break;
-+		case 0x0300:
-+		case 0x0500:
-+			((u8*)req->buf)[0] = 0x00;
-+			break;
-+		}
-+		//((u8*)req->buf)[0] = 0x81;
-+		//((u8*)req->buf)[1] = 0x81;
-+		value = ctrl->wLength;
-+		break;
-+	case 0x82:
-+		switch (ctrl->wValue) {
-+		case 0x0201:
-+		case 0x0202:
-+			((u8*)req->buf)[0] = 0x00;
-+			((u8*)req->buf)[1] = 0xc3;
-+			break;
-+		case 0x0300:
-+		case 0x0500:
-+			((u8*)req->buf)[0] = 0x00;
-+			break;
-+		}
-+		//((u8*)req->buf)[0] = 0x82;
-+		//((u8*)req->buf)[1] = 0x82;
-+		value = ctrl->wLength;
-+		break;
-+	case 0x83:
-+		switch (ctrl->wValue) {
-+		case 0x0201:
-+		case 0x0202:
-+			((u8*)req->buf)[0] = 0x00;
-+			((u8*)req->buf)[1] = 0x00;
-+			break;
-+		case 0x0300:
-+			((u8*)req->buf)[0] = 0x60;
-+			break;
-+		case 0x0500:
-+			((u8*)req->buf)[0] = 0x18;
-+			break;
-+		}
-+		//((u8*)req->buf)[0] = 0x83;
-+		//((u8*)req->buf)[1] = 0x83;
-+		value = ctrl->wLength;
-+		break;
-+	case 0x84:
-+		switch (ctrl->wValue) {
-+		case 0x0201:
-+		case 0x0202:
-+			((u8*)req->buf)[0] = 0x00;
-+			((u8*)req->buf)[1] = 0x01;
-+			break;
-+		case 0x0300:
-+		case 0x0500:
-+			((u8*)req->buf)[0] = 0x08;
-+			break;
-+		}
-+		//((u8*)req->buf)[0] = 0x84;
-+		//((u8*)req->buf)[1] = 0x84;
-+		value = ctrl->wLength;
-+		break;
-+	case 0x85:
-+		((u8*)req->buf)[0] = 0x85;
-+		((u8*)req->buf)[1] = 0x85;
-+		value = ctrl->wLength;
-+		break;
-+
-+
-+	default:
-+unknown:
-+		printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
-+			ctrl->bRequestType, ctrl->bRequest,
-+			ctrl->wValue, ctrl->wIndex, ctrl->wLength);
-+	}
-+
-+	/* respond with data transfer before status phase? */
-+	if (value >= 0) {
-+		req->length = value;
-+		req->zero = value < ctrl->wLength
-+				&& (value % gadget->ep0->maxpacket) == 0;
-+		value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
-+		if (value < 0) {
-+			DBG (dev, "ep_queue < 0 --> %d\n", value);
-+			req->status = 0;
-+			zero_setup_complete (gadget->ep0, req);
-+		}
-+	}
-+
-+	/* device either stalls (value < 0) or reports success */
-+	return value;
-+}
-+
-+static void
-+zero_disconnect (struct usb_gadget *gadget)
-+{
-+	struct zero_dev		*dev = get_gadget_data (gadget);
-+	unsigned long		flags;
-+
-+	spin_lock_irqsave (&dev->lock, flags);
-+	zero_reset_config (dev);
-+
-+	/* a more significant application might have some non-usb
-+	 * activities to quiesce here, saving resources like power
-+	 * or pushing the notification up a network stack.
-+	 */
-+	spin_unlock_irqrestore (&dev->lock, flags);
-+
-+	/* next we may get setup() calls to enumerate new connections;
-+	 * or an unbind() during shutdown (including removing module).
-+	 */
-+}
-+
-+static void
-+zero_autoresume (unsigned long _dev)
-+{
-+	struct zero_dev	*dev = (struct zero_dev *) _dev;
-+	int		status;
-+
-+	/* normally the host would be woken up for something
-+	 * more significant than just a timer firing...
-+	 */
-+	if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
-+		status = usb_gadget_wakeup (dev->gadget);
-+		DBG (dev, "wakeup --> %d\n", status);
-+	}
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void
-+zero_unbind (struct usb_gadget *gadget)
-+{
-+	struct zero_dev		*dev = get_gadget_data (gadget);
-+
-+	DBG (dev, "unbind\n");
-+
-+	/* we've already been disconnected ... no i/o is active */
-+	if (dev->req)
-+		free_ep_req (gadget->ep0, dev->req);
-+	del_timer_sync (&dev->resume);
-+	kfree (dev);
-+	set_gadget_data (gadget, NULL);
-+}
-+
-+static int
-+zero_bind (struct usb_gadget *gadget)
-+{
-+	struct zero_dev		*dev;
-+	//struct usb_ep		*ep;
-+
-+	printk("binding\n");
-+	/*
-+	 * DRIVER POLICY CHOICE:  you may want to do this differently.
-+	 * One thing to avoid is reusing a bcdDevice revision code
-+	 * with different host-visible configurations or behavior
-+	 * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
-+	 */
-+	//device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
-+
-+
-+	/* ok, we made sense of the hardware ... */
-+	dev = kzalloc (sizeof *dev, SLAB_KERNEL);
-+	if (!dev)
-+		return -ENOMEM;
-+	spin_lock_init (&dev->lock);
-+	dev->gadget = gadget;
-+	set_gadget_data (gadget, dev);
-+
-+	/* preallocate control response and buffer */
-+	dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
-+	if (!dev->req)
-+		goto enomem;
-+	dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
-+				&dev->req->dma, GFP_KERNEL);
-+	if (!dev->req->buf)
-+		goto enomem;
-+
-+	dev->req->complete = zero_setup_complete;
-+
-+	device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
-+
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+	/* assume ep0 uses the same value for both speeds ... */
-+	dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
-+
-+	/* and that all endpoints are dual-speed */
-+	//hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
-+	//hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
-+#endif
-+
-+	usb_gadget_set_selfpowered (gadget);
-+
-+	init_timer (&dev->resume);
-+	dev->resume.function = zero_autoresume;
-+	dev->resume.data = (unsigned long) dev;
-+
-+	gadget->ep0->driver_data = dev;
-+
-+	INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
-+	INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
-+		EP_OUT_NAME, EP_IN_NAME);
-+
-+	snprintf (manufacturer, sizeof manufacturer,
-+		UTS_SYSNAME " " UTS_RELEASE " with %s",
-+		gadget->name);
-+
-+	return 0;
-+
-+enomem:
-+	zero_unbind (gadget);
-+	return -ENOMEM;
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static void
-+zero_suspend (struct usb_gadget *gadget)
-+{
-+	struct zero_dev		*dev = get_gadget_data (gadget);
-+
-+	if (gadget->speed == USB_SPEED_UNKNOWN)
-+		return;
-+
-+	if (autoresume) {
-+		mod_timer (&dev->resume, jiffies + (HZ * autoresume));
-+		DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
-+	} else
-+		DBG (dev, "suspend\n");
-+}
-+
-+static void
-+zero_resume (struct usb_gadget *gadget)
-+{
-+	struct zero_dev		*dev = get_gadget_data (gadget);
-+
-+	DBG (dev, "resume\n");
-+	del_timer (&dev->resume);
-+}
-+
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static struct usb_gadget_driver zero_driver = {
-+#ifdef CONFIG_USB_GADGET_DUALSPEED
-+	.speed		= USB_SPEED_HIGH,
-+#else
-+	.speed		= USB_SPEED_FULL,
-+#endif
-+	.function	= (char *) longname,
-+	.bind		= zero_bind,
-+	.unbind		= zero_unbind,
-+
-+	.setup		= zero_setup,
-+	.disconnect	= zero_disconnect,
-+
-+	.suspend	= zero_suspend,
-+	.resume		= zero_resume,
-+
-+	.driver 	= {
-+		.name		= (char *) shortname,
-+		// .shutdown = ...
-+		// .suspend = ...
-+		// .resume = ...
-+	},
-+};
-+
-+MODULE_AUTHOR ("David Brownell");
-+MODULE_LICENSE ("Dual BSD/GPL");
-+
-+static struct proc_dir_entry *pdir, *pfile;
-+
-+static int isoc_read_data (char *page, char **start,
-+			   off_t off, int count,
-+			   int *eof, void *data)
-+{
-+	int i;
-+	static int c = 0;
-+	static int done = 0;
-+	static int s = 0;
-+
-+/*
-+	printk ("\ncount: %d\n", count);
-+	printk ("rbuf_start: %d\n", rbuf_start);
-+	printk ("rbuf_len: %d\n", rbuf_len);
-+	printk ("off: %d\n", off);
-+	printk ("start: %p\n\n", *start);
-+*/
-+	if (done) {
-+		c = 0;
-+		done = 0;
-+		*eof = 1;
-+		return 0;
-+	}
-+
-+	if (c == 0) {
-+		if (rbuf_len == RBUF_LEN)
-+			s = rbuf_start;
-+		else s = 0;
-+	}
-+
-+	for (i=0; i<count && c<rbuf_len; i++, c++) {
-+		page[i] = rbuf[(c+s) % RBUF_LEN];
-+	}
-+	*start = page;
-+
-+	if (c >= rbuf_len) {
-+		*eof = 1;
-+		done = 1;
-+	}
-+
-+
-+	return i;
-+}
-+
-+static int __init init (void)
-+{
-+
-+	int retval = 0;
-+
-+	pdir = proc_mkdir("isoc_test", NULL);
-+	if(pdir == NULL) {
-+		retval = -ENOMEM;
-+		printk("Error creating dir\n");
-+		goto done;
-+	}
-+	pdir->owner = THIS_MODULE;
-+
-+	pfile = create_proc_read_entry("isoc_data",
-+				       0444, pdir,
-+				       isoc_read_data,
-+				       NULL);
-+	if (pfile == NULL) {
-+		retval = -ENOMEM;
-+		printk("Error creating file\n");
-+		goto no_file;
-+	}
-+	pfile->owner = THIS_MODULE;
-+
-+	return usb_gadget_register_driver (&zero_driver);
-+
-+ no_file:
-+	remove_proc_entry("isoc_data", NULL);
-+ done:
-+	return retval;
-+}
-+module_init (init);
-+
-+static void __exit cleanup (void)
-+{
-+
-+	usb_gadget_unregister_driver (&zero_driver);
-+
-+	remove_proc_entry("isoc_data", pdir);
-+	remove_proc_entry("isoc_test", NULL);
-+}
-+module_exit (cleanup);
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_cfi_common.h
-@@ -0,0 +1,142 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_CFI_COMMON_H__)
-+#define __DWC_CFI_COMMON_H__
-+
-+//#include <linux/types.h>
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the CFI specific common constants, interfaces
-+ * (functions and macros) and structures for Linux. No PCD specific
-+ * data structure or definition is to be included in this file.
-+ *
-+ */
-+
-+/** This is a request for all Core Features */
-+#define VEN_CORE_GET_FEATURES		0xB1
-+
-+/** This is a request to get the value of a specific Core Feature */
-+#define VEN_CORE_GET_FEATURE		0xB2
-+
-+/** This command allows the host to set the value of a specific Core Feature */
-+#define VEN_CORE_SET_FEATURE		0xB3
-+
-+/** This command allows the host to set the default values of
-+ * either all or any specific Core Feature
-+ */
-+#define VEN_CORE_RESET_FEATURES		0xB4
-+
-+/** This command forces the PCD to write the deferred values of a Core Features */
-+#define VEN_CORE_ACTIVATE_FEATURES	0xB5
-+
-+/** This request reads a DWORD value from a register at the specified offset */
-+#define VEN_CORE_READ_REGISTER		0xB6
-+
-+/** This request writes a DWORD value into a register at the specified offset */
-+#define VEN_CORE_WRITE_REGISTER		0xB7
-+
-+/** This structure is the header of the Core Features dataset returned to
-+ *  the Host
-+ */
-+struct cfi_all_features_header {
-+/** The features header structure length is */
-+#define CFI_ALL_FEATURES_HDR_LEN		8
-+	/**
-+	 * The total length of the features dataset returned to the Host
-+	 */
-+	uint16_t wTotalLen;
-+
-+	/**
-+	 * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
-+	 * This field identifies the version of the CFI Specification with which
-+	 * the device is compliant.
-+	 */
-+	uint16_t wVersion;
-+
-+	/** The ID of the Core */
-+	uint16_t wCoreID;
-+#define CFI_CORE_ID_UDC		1
-+#define CFI_CORE_ID_OTG		2
-+#define CFI_CORE_ID_WUDEV	3
-+
-+	/** Number of features returned by VEN_CORE_GET_FEATURES request */
-+	uint16_t wNumFeatures;
-+} UPACKED;
-+
-+typedef struct cfi_all_features_header cfi_all_features_header_t;
-+
-+/** This structure is a header of the Core Feature descriptor dataset returned to
-+ *  the Host after the VEN_CORE_GET_FEATURES request
-+ */
-+struct cfi_feature_desc_header {
-+#define CFI_FEATURE_DESC_HDR_LEN	8
-+
-+	/** The feature ID */
-+	uint16_t wFeatureID;
-+
-+	/** Length of this feature descriptor in bytes - including the
-+	 * length of the feature name string
-+	 */
-+	uint16_t wLength;
-+
-+	/** The data length of this feature in bytes */
-+	uint16_t wDataLength;
-+
-+	/**
-+	 * Attributes of this features
-+	 * D0: Access rights
-+	 * 0 - Read/Write
-+	 * 1 - Read only
-+	 */
-+	uint8_t bmAttributes;
-+#define CFI_FEATURE_ATTR_RO		1
-+#define CFI_FEATURE_ATTR_RW		0
-+
-+	/** Length of the feature name in bytes */
-+	uint8_t bNameLen;
-+
-+	/** The feature name buffer */
-+	//uint8_t *name;
-+} UPACKED;
-+
-+typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
-+
-+/**
-+ * This structure describes a NULL terminated string referenced by its id field.
-+ * It is very similar to usb_string structure but has the id field type set to 16-bit.
-+ */
-+struct cfi_string {
-+	uint16_t id;
-+	const uint8_t *s;
-+};
-+typedef struct cfi_string cfi_string_t;
-+
-+#endif
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.c
-@@ -0,0 +1,854 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
-+ * $Revision: #12 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_adp.h"
-+
-+/** @file
-+ *
-+ * This file contains the most of the Attach Detect Protocol implementation for
-+ * the driver to support OTG Rev2.0.
-+ *
-+ */
-+
-+void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
-+{
-+	adpctl_data_t adpctl;
-+
-+	adpctl.d32 = value;
-+	adpctl.b.ar = 0x2;
-+
-+	DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
-+
-+	while (adpctl.b.ar) {
-+		adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
-+	}
-+
-+}
-+
-+/**
-+ * Function is called to read ADP registers
-+ */
-+uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
-+{
-+	adpctl_data_t adpctl;
-+
-+	adpctl.d32 = 0;
-+	adpctl.b.ar = 0x1;
-+
-+	DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
-+
-+	while (adpctl.b.ar) {
-+		adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
-+	}
-+
-+	return adpctl.d32;
-+}
-+
-+/**
-+ * Function is called to read ADPCTL register and filter Write-clear bits
-+ */
-+uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
-+{
-+	adpctl_data_t adpctl;
-+
-+	adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+	adpctl.b.adp_tmout_int = 0;
-+	adpctl.b.adp_prb_int = 0;
-+	adpctl.b.adp_tmout_int = 0;
-+
-+	return adpctl.d32;
-+}
-+
-+/**
-+ * Function is called to write ADP registers
-+ */
-+void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
-+			    uint32_t set)
-+{
-+	dwc_otg_adp_write_reg(core_if,
-+			      (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
-+}
-+
-+static void adp_sense_timeout(void *ptr)
-+{
-+	dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+	core_if->adp.sense_timer_started = 0;
-+	DWC_PRINTF("ADP SENSE TIMEOUT\n");
-+	if (core_if->adp_enable) {
-+		dwc_otg_adp_sense_stop(core_if);
-+		dwc_otg_adp_probe_start(core_if);
-+	}
-+}
-+
-+/**
-+ * This function is called when the ADP vbus timer expires. Timeout is 1.1s.
-+ */
-+static void adp_vbuson_timeout(void *ptr)
-+{
-+	gpwrdn_data_t gpwrdn;
-+	dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+	hprt0_data_t hprt0 = {.d32 = 0 };
-+	pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+	DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
-+	if (core_if) {
-+		core_if->adp.vbuson_timer_started = 0;
-+		/* Turn off vbus */
-+		hprt0.b.prtpwr = 1;
-+		DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
-+		gpwrdn.d32 = 0;
-+
-+		/* Power off the core */
-+		if (core_if->power_down == 2) {
-+			/* Enable Wakeup Logic */
-+//                      gpwrdn.b.wkupactiv = 1;
-+			gpwrdn.b.pmuactv = 0;
-+			gpwrdn.b.pwrdnrstn = 1;
-+			gpwrdn.b.pwrdnclmp = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+					 gpwrdn.d32);
-+
-+			/* Suspend the Phy Clock */
-+			pcgcctl.b.stoppclk = 1;
-+			DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+			/* Switch on VDD */
-+//                      gpwrdn.b.wkupactiv = 1;
-+			gpwrdn.b.pmuactv = 1;
-+			gpwrdn.b.pwrdnrstn = 1;
-+			gpwrdn.b.pwrdnclmp = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+					 gpwrdn.d32);
-+		} else {
-+			/* Enable Power Down Logic */
-+			gpwrdn.b.pmuintsel = 1;
-+			gpwrdn.b.pmuactv = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+		}
-+
-+		/* Power off the core */
-+		if (core_if->power_down == 2) {
-+			gpwrdn.d32 = 0;
-+			gpwrdn.b.pwrdnswtch = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
-+					 gpwrdn.d32, 0);
-+		}
-+
-+		/* Unmask SRP detected interrupt from Power Down Logic */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.srp_det_msk = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+
-+		dwc_otg_adp_probe_start(core_if);
-+		dwc_otg_dump_global_registers(core_if);
-+		dwc_otg_dump_host_registers(core_if);
-+	}
-+
-+}
-+
-+/**
-+ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
-+ * not asserted within 1.1 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
-+{
-+	core_if->adp.vbuson_timer_started = 1;
-+	if (core_if->adp.vbuson_timer)
-+	{
-+		DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
-+		/* 1.1 secs + 60ms necessary for cil_hcd_start*/
-+		DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
-+	} else {
-+		DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
-+	}
-+}
-+
-+#if 0
-+/**
-+ * Masks all DWC OTG core interrupts
-+ *
-+ */
-+static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+	int i;
-+	gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+
-+	/* Mask Host Interrupts */
-+
-+	/* Clear and disable HCINTs */
-+	for (i = 0; i < core_if->core_params->host_channels; i++) {
-+		DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
-+		DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
-+
-+	}
-+
-+	/* Clear and disable HAINT */
-+	DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
-+	DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
-+
-+	/* Mask Device Interrupts */
-+	if (!core_if->multiproc_int_enable) {
-+		/* Clear and disable IN Endpoint interrupts */
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
-+		for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+			DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
-+					diepint, 0xFFFFFFFF);
-+		}
-+
-+		/* Clear and disable OUT Endpoint interrupts */
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
-+		for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+			DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
-+					doepint, 0xFFFFFFFF);
-+		}
-+
-+		/* Clear and disable DAINT */
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
-+				0xFFFFFFFF);
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
-+	} else {
-+		for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+			DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+					diepeachintmsk[i], 0);
-+			DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
-+					diepint, 0xFFFFFFFF);
-+		}
-+
-+		for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+			DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+					doepeachintmsk[i], 0);
-+			DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
-+					doepint, 0xFFFFFFFF);
-+		}
-+
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
-+				0);
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
-+				0xFFFFFFFF);
-+
-+	}
-+
-+	/* Disable interrupts */
-+	ahbcfg.b.glblintrmsk = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
-+
-+	/* Disable all interrupts. */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
-+
-+	/* Clear any pending interrupts */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/* Clear any pending OTG Interrupts */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
-+}
-+
-+/**
-+ * Unmask Port Connection Detected interrupt
-+ *
-+ */
-+static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
-+{
-+	gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
-+
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
-+}
-+#endif
-+
-+/**
-+ * Starts the ADP Probing
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ */
-+uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
-+{
-+
-+	adpctl_data_t adpctl = {.d32 = 0};
-+	gpwrdn_data_t gpwrdn;
-+#if 0
-+	adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
-+								.b.adp_sns_int = 1, b.adp_tmout_int};
-+#endif
-+	dwc_otg_disable_global_interrupts(core_if);
-+	DWC_PRINTF("ADP Probe Start\n");
-+	core_if->adp.probe_enabled = 1;
-+
-+	adpctl.b.adpres = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+	while (adpctl.b.adpres) {
-+		adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+	}
-+
-+	adpctl.d32 = 0;
-+	gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+	/* In Host mode unmask SRP detected interrupt */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.sts_chngint_msk = 1;
-+	if (!gpwrdn.b.idsts) {
-+		gpwrdn.b.srp_det_msk = 1;
-+	}
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+
-+	adpctl.b.adp_tmout_int_msk = 1;
-+	adpctl.b.adp_prb_int_msk = 1;
-+	adpctl.b.prb_dschg = 1;
-+	adpctl.b.prb_delta = 1;
-+	adpctl.b.prb_per = 1;
-+	adpctl.b.adpen = 1;
-+	adpctl.b.enaprb = 1;
-+
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+	DWC_PRINTF("ADP Probe Finish\n");
-+	return 0;
-+}
-+
-+/**
-+ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
-+ * within 3 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
-+{
-+	core_if->adp.sense_timer_started = 1;
-+	DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
-+}
-+
-+/**
-+ * Starts the ADP Sense
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
-+{
-+	adpctl_data_t adpctl;
-+
-+	DWC_PRINTF("ADP Sense Start\n");
-+
-+	/* Unmask ADP sense interrupt and mask all other from the core */
-+	adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+	adpctl.b.adp_sns_int_msk = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+	dwc_otg_disable_global_interrupts(core_if); // vahrama
-+
-+	/* Set ADP reset bit*/
-+	adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+	adpctl.b.adpres = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+	while (adpctl.b.adpres) {
-+		adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+	}
-+
-+	adpctl.b.adpres = 0;
-+	adpctl.b.adpen = 1;
-+	adpctl.b.enasns = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+	dwc_otg_adp_sense_timer_start(core_if);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Stops the ADP Probing
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
-+{
-+
-+	adpctl_data_t adpctl;
-+	DWC_PRINTF("Stop ADP probe\n");
-+	core_if->adp.probe_enabled = 0;
-+	core_if->adp.probe_counter = 0;
-+	adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+
-+	adpctl.b.adpen = 0;
-+	adpctl.b.adp_prb_int = 1;
-+	adpctl.b.adp_tmout_int = 1;
-+	adpctl.b.adp_sns_int = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Stops the ADP Sensing
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
-+{
-+	adpctl_data_t adpctl;
-+
-+	core_if->adp.sense_enabled = 0;
-+
-+	adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
-+	adpctl.b.enasns = 0;
-+	adpctl.b.adp_sns_int = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+	return 0;
-+}
-+
-+/**
-+ * Called to turn on the VBUS after initial ADP probe in host mode.
-+ * If port power was already enabled in cil_hcd_start function then
-+ * only schedule a timer.
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ */
-+void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
-+{
-+	hprt0_data_t hprt0 = {.d32 = 0 };
-+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+	DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
-+
-+	if (hprt0.b.prtpwr == 0) {
-+		hprt0.b.prtpwr = 1;
-+		//DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+	}
-+
-+	dwc_otg_adp_vbuson_timer_start(core_if);
-+}
-+
-+/**
-+ * Called right after driver is loaded
-+ * to perform initial actions for ADP
-+ *
-+ * @param core_if the pointer to core_if structure.
-+ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN
-+ */
-+void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
-+{
-+	gpwrdn_data_t gpwrdn;
-+
-+	DWC_PRINTF("ADP Initial Start\n");
-+	core_if->adp.adp_started = 1;
-+
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+	dwc_otg_disable_global_interrupts(core_if);
-+	if (is_host) {
-+		DWC_PRINTF("HOST MODE\n");
-+		/* Enable Power Down Logic Interrupt*/
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pmuintsel = 1;
-+		gpwrdn.b.pmuactv = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+		/* Initialize first ADP probe to obtain Ramp Time value */
-+		core_if->adp.initial_probe = 1;
-+		dwc_otg_adp_probe_start(core_if);
-+	} else {
-+		gotgctl_data_t gotgctl;
-+		gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+		DWC_PRINTF("DEVICE MODE\n");
-+		if (gotgctl.b.bsesvld == 0) {
-+			/* Enable Power Down Logic Interrupt*/
-+			gpwrdn.d32 = 0;
-+			DWC_PRINTF("VBUS is not valid - start ADP probe\n");
-+			gpwrdn.b.pmuintsel = 1;
-+			gpwrdn.b.pmuactv = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+			core_if->adp.initial_probe = 1;
-+			dwc_otg_adp_probe_start(core_if);
-+		} else {
-+			DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
-+			core_if->op_state = B_PERIPHERAL;
-+			dwc_otg_core_init(core_if);
-+			dwc_otg_enable_global_interrupts(core_if);
-+			cil_pcd_start(core_if);
-+			dwc_otg_dump_global_registers(core_if);
-+			dwc_otg_dump_dev_registers(core_if);
-+		}
-+	}
-+}
-+
-+void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
-+{
-+	core_if->adp.adp_started = 0;
-+	core_if->adp.initial_probe = 0;
-+	core_if->adp.probe_timer_values[0] = -1;
-+	core_if->adp.probe_timer_values[1] = -1;
-+	core_if->adp.probe_enabled = 0;
-+	core_if->adp.sense_enabled = 0;
-+	core_if->adp.sense_timer_started = 0;
-+	core_if->adp.vbuson_timer_started = 0;
-+	core_if->adp.probe_counter = 0;
-+	core_if->adp.gpwrdn = 0;
-+	core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
-+	/* Initialize timers */
-+	core_if->adp.sense_timer =
-+	    DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
-+	core_if->adp.vbuson_timer =
-+	    DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
-+	if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
-+	{
-+		DWC_ERROR("Could not allocate memory for ADP timers\n");
-+	}
-+}
-+
-+void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
-+{
-+	gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+	gpwrdn.b.pmuintsel = 1;
-+	gpwrdn.b.pmuactv = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	if (core_if->adp.probe_enabled)
-+		dwc_otg_adp_probe_stop(core_if);
-+	if (core_if->adp.sense_enabled)
-+		dwc_otg_adp_sense_stop(core_if);
-+	if (core_if->adp.sense_timer_started)
-+		DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+	if (core_if->adp.vbuson_timer_started)
-+		DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
-+	DWC_TIMER_FREE(core_if->adp.sense_timer);
-+	DWC_TIMER_FREE(core_if->adp.vbuson_timer);
-+}
-+
-+/////////////////////////////////////////////////////////////////////
-+////////////// ADP Interrupt Handlers ///////////////////////////////
-+/////////////////////////////////////////////////////////////////////
-+/**
-+ * This function sets Ramp Timer values
-+ */
-+static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	if (core_if->adp.probe_timer_values[0] == -1) {
-+		core_if->adp.probe_timer_values[0] = val;
-+		core_if->adp.probe_timer_values[1] = -1;
-+		return 1;
-+	} else {
-+		core_if->adp.probe_timer_values[1] =
-+		    core_if->adp.probe_timer_values[0];
-+		core_if->adp.probe_timer_values[0] = val;
-+		return 0;
-+	}
-+}
-+
-+/**
-+ * This function compares Ramp Timer values
-+ */
-+static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
-+{
-+	uint32_t diff;
-+	if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
-+			diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
-+	else
-+			diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];
-+	if(diff < 2) {
-+		return 0;
-+	} else {
-+		return 1;
-+	}
-+}
-+
-+/**
-+ * This function handles ADP Probe Interrupts
-+ */
-+static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
-+						 uint32_t val)
-+{
-+	adpctl_data_t adpctl = {.d32 = 0 };
-+	gpwrdn_data_t gpwrdn, temp;
-+	adpctl.d32 = val;
-+
-+	temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+	core_if->adp.probe_counter++;
-+	core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+	if (adpctl.b.rtim == 0 && !temp.b.idsts){
-+		DWC_PRINTF("RTIM value is 0\n");
-+		goto exit;
-+	}
-+	if (set_timer_value(core_if, adpctl.b.rtim) &&
-+	    core_if->adp.initial_probe) {
-+		core_if->adp.initial_probe = 0;
-+		dwc_otg_adp_probe_stop(core_if);
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pmuactv = 1;
-+		gpwrdn.b.pmuintsel = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+		/* check which value is for device mode and which for Host mode */
-+		if (!temp.b.idsts) {	/* considered host mode value is 0 */
-+			/*
-+			 * Turn on VBUS after initial ADP probe.
-+			 */
-+			core_if->op_state = A_HOST;
-+			dwc_otg_enable_global_interrupts(core_if);
-+			DWC_SPINUNLOCK(core_if->lock);
-+			cil_hcd_start(core_if);
-+			dwc_otg_adp_turnon_vbus(core_if);
-+			DWC_SPINLOCK(core_if->lock);
-+		} else {
-+			/*
-+			 * Initiate SRP after initial ADP probe.
-+			 */
-+			dwc_otg_enable_global_interrupts(core_if);
-+			dwc_otg_initiate_srp(core_if);
-+		}
-+	} else if (core_if->adp.probe_counter > 2){
-+		gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+		if (compare_timer_values(core_if)) {
-+			DWC_PRINTF("Difference in timer values !!! \n");
-+//                      core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
-+			dwc_otg_adp_probe_stop(core_if);
-+
-+			/* Power on the core */
-+			if (core_if->power_down == 2) {
-+				gpwrdn.b.pwrdnswtch = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+			}
-+
-+			/* check which value is for device mode and which for Host mode */
-+			if (!temp.b.idsts) {	/* considered host mode value is 0 */
-+				/* Disable Interrupt from Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pmuintsel = 1;
-+				gpwrdn.b.pmuactv = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, gpwrdn.d32, 0);
-+
-+				/*
-+				 * Initialize the Core for Host mode.
-+				 */
-+				core_if->op_state = A_HOST;
-+				dwc_otg_core_init(core_if);
-+				dwc_otg_enable_global_interrupts(core_if);
-+				cil_hcd_start(core_if);
-+			} else {
-+				gotgctl_data_t gotgctl;
-+				/* Mask SRP detected interrupt from Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.srp_det_msk = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, gpwrdn.d32, 0);
-+
-+				/* Disable Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pmuintsel = 1;
-+				gpwrdn.b.pmuactv = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, gpwrdn.d32, 0);
-+
-+				/*
-+				 * Initialize the Core for Device mode.
-+				 */
-+				core_if->op_state = B_PERIPHERAL;
-+				dwc_otg_core_init(core_if);
-+				dwc_otg_enable_global_interrupts(core_if);
-+				cil_pcd_start(core_if);
-+
-+				gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+				if (!gotgctl.b.bsesvld) {
-+					dwc_otg_initiate_srp(core_if);
-+				}
-+			}
-+		}
-+		if (core_if->power_down == 2) {
-+			if (gpwrdn.b.bsessvld) {
-+				/* Mask SRP detected interrupt from Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.srp_det_msk = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+				/* Disable Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pmuactv = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+				/*
-+				 * Initialize the Core for Device mode.
-+				 */
-+				core_if->op_state = B_PERIPHERAL;
-+				dwc_otg_core_init(core_if);
-+				dwc_otg_enable_global_interrupts(core_if);
-+				cil_pcd_start(core_if);
-+			}
-+		}
-+	}
-+exit:
-+	/* Clear interrupt */
-+	adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+	adpctl.b.adp_prb_int = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+	return 0;
-+}
-+
-+/**
-+ * This function hadles ADP Sense Interrupt
-+ */
-+static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
-+{
-+	adpctl_data_t adpctl;
-+	/* Stop ADP Sense timer */
-+	DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+
-+	/* Restart ADP Sense timer */
-+	dwc_otg_adp_sense_timer_start(core_if);
-+
-+	/* Clear interrupt */
-+	adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+	adpctl.b.adp_sns_int = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+	return 0;
-+}
-+
-+/**
-+ * This function handles ADP Probe Interrupts
-+ */
-+static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
-+						 uint32_t val)
-+{
-+	adpctl_data_t adpctl = {.d32 = 0 };
-+	adpctl.d32 = val;
-+	set_timer_value(core_if, adpctl.b.rtim);
-+
-+	/* Clear interrupt */
-+	adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+	adpctl.b.adp_tmout_int = 1;
-+	dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+
-+	return 0;
-+}
-+
-+/**
-+ * ADP Interrupt handler.
-+ *
-+ */
-+int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
-+{
-+	int retval = 0;
-+	adpctl_data_t adpctl = {.d32 = 0};
-+
-+	adpctl.d32 = dwc_otg_adp_read_reg(core_if);
-+	DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
-+
-+	if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
-+		DWC_PRINTF("ADP Sense interrupt\n");
-+		retval |= dwc_otg_adp_handle_sns_intr(core_if);
-+	}
-+	if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
-+		DWC_PRINTF("ADP timeout interrupt\n");
-+		retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
-+	}
-+	if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
-+		DWC_PRINTF("ADP Probe interrupt\n");
-+		adpctl.b.adp_prb_int = 1;
-+		retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
-+	}
-+
-+//	dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
-+	//dwc_otg_adp_write_reg(core_if, adpctl.d32);
-+	DWC_PRINTF("RETURN FROM ADP ISR\n");
-+
-+	return retval;
-+}
-+
-+/**
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
-+{
-+
-+#ifndef DWC_HOST_ONLY
-+	hprt0_data_t hprt0;
-+	gpwrdn_data_t gpwrdn;
-+	DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
-+
-+	gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+	/* check which value is for device mode and which for Host mode */
-+	if (!gpwrdn.b.idsts) {	/* considered host mode value is 0 */
-+		DWC_PRINTF("SRP: Host mode\n");
-+
-+		if (core_if->adp_enable) {
-+			dwc_otg_adp_probe_stop(core_if);
-+
-+			/* Power on the core */
-+			if (core_if->power_down == 2) {
-+				gpwrdn.b.pwrdnswtch = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+			}
-+
-+			core_if->op_state = A_HOST;
-+			dwc_otg_core_init(core_if);
-+			dwc_otg_enable_global_interrupts(core_if);
-+			cil_hcd_start(core_if);
-+		}
-+
-+		/* Turn on the port power bit. */
-+		hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+		hprt0.b.prtpwr = 1;
-+		DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+		/* Start the Connection timer. So a message can be displayed
-+		 * if connect does not occur within 10 seconds. */
-+		cil_hcd_session_start(core_if);
-+	} else {
-+		DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
-+		if (core_if->adp_enable) {
-+			dwc_otg_adp_probe_stop(core_if);
-+
-+			/* Power on the core */
-+			if (core_if->power_down == 2) {
-+				gpwrdn.b.pwrdnswtch = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+			}
-+
-+			gpwrdn.d32 = 0;
-+			gpwrdn.b.pmuactv = 0;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+					 gpwrdn.d32);
-+
-+			core_if->op_state = B_PERIPHERAL;
-+			dwc_otg_core_init(core_if);
-+			dwc_otg_enable_global_interrupts(core_if);
-+			cil_pcd_start(core_if);
-+		}
-+	}
-+#endif
-+	return 1;
-+}
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.h
-@@ -0,0 +1,80 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
-+ * $Revision: #7 $
-+ * $Date: 2011/10/24 $
-+ * $Change: 1871159 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_ADP_H__
-+#define __DWC_OTG_ADP_H__
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the Attach Detect Protocol interfaces and defines
-+ * (functions) and structures for Linux.
-+ *
-+ */
-+
-+#define DWC_OTG_ADP_UNATTACHED	0
-+#define DWC_OTG_ADP_ATTACHED	1
-+#define DWC_OTG_ADP_UNKOWN	2
-+
-+typedef struct dwc_otg_adp {
-+	uint32_t adp_started;
-+	uint32_t initial_probe;
-+	int32_t probe_timer_values[2];
-+	uint32_t probe_enabled;
-+	uint32_t sense_enabled;
-+	dwc_timer_t *sense_timer;
-+	uint32_t sense_timer_started;
-+	dwc_timer_t *vbuson_timer;
-+	uint32_t vbuson_timer_started;
-+	uint32_t attached;
-+	uint32_t probe_counter;
-+	uint32_t gpwrdn;
-+} dwc_otg_adp_t;
-+
-+/**
-+ * Attach Detect Protocol functions
-+ */
-+
-+extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
-+extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
-+extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
-+extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
-+extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
-+extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
-+
-+#endif //__DWC_OTG_ADP_H__
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.c
-@@ -0,0 +1,1212 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
-+ * $Revision: #44 $
-+ * $Date: 2010/11/29 $
-+ * $Change: 1636033 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The diagnostic interface will provide access to the controller for
-+ * bringing up the hardware and testing.  The Linux driver attributes
-+ * feature will be used to provide the Linux Diagnostic
-+ * Interface. These attributes are accessed through sysfs.
-+ */
-+
-+/** @page "Linux Module Attributes"
-+ *
-+ * The Linux module attributes feature is used to provide the Linux
-+ * Diagnostic Interface.  These attributes are accessed through sysfs.
-+ * The diagnostic interface will provide access to the controller for
-+ * bringing up the hardware and testing.
-+
-+ The following table shows the attributes.
-+ <table>
-+ <tr>
-+ <td><b> Name</b></td>
-+ <td><b> Description</b></td>
-+ <td><b> Access</b></td>
-+ </tr>
-+
-+ <tr>
-+ <td> mode </td>
-+ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hnpcapable </td>
-+ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> srpcapable </td>
-+ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hsic_connect </td>
-+ <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> inv_sel_hsic </td>
-+ <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
-+ Read returns the current value.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hnp </td>
-+ <td> Initiates the Host Negotiation Protocol.  Read returns the status.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> srp </td>
-+ <td> Initiates the Session Request Protocol.  Read returns the status.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> buspower </td>
-+ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> bussuspend </td>
-+ <td> Suspends the USB bus.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> busconnected </td>
-+ <td> Gets the connection status of the bus</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gotgctl </td>
-+ <td> Gets or sets the Core Control Status Register.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gusbcfg </td>
-+ <td> Gets or sets the Core USB Configuration Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> grxfsiz </td>
-+ <td> Gets or sets the Receive FIFO Size Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gnptxfsiz </td>
-+ <td> Gets or sets the non-periodic Transmit Size Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gpvndctl </td>
-+ <td> Gets or sets the PHY Vendor Control Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> ggpio </td>
-+ <td> Gets the value in the lower 16-bits of the General Purpose IO Register
-+ or sets the upper 16 bits.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> guid </td>
-+ <td> Gets or sets the value of the User ID Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> gsnpsid </td>
-+ <td> Gets the value of the Synopsys ID Regester</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> devspeed </td>
-+ <td> Gets or sets the device speed setting in the DCFG register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> enumspeed </td>
-+ <td> Gets the device enumeration Speed.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hptxfsiz </td>
-+ <td> Gets the value of the Host Periodic Transmit FIFO</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hprt0 </td>
-+ <td> Gets or sets the value in the Host Port Control and Status Register</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regoffset </td>
-+ <td> Sets the register offset for the next Register Access</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regvalue </td>
-+ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> remote_wakeup </td>
-+ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
-+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
-+ Wakeup signalling bit in the Device Control Register is set for 1
-+ milli-second.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> rem_wakeup_pwrdn </td>
-+ <td> On read, shows the status core - hibernated or not. On write, initiates
-+ a remote wakeup of the device from Hibernation. </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> mode_ch_tim_en </td>
-+ <td> This bit is used to enable or disable the host core to wait for 200 PHY
-+ clock cycles at the end of Resume to change the opmode signal to the PHY to 00
-+ after Suspend or LPM. </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> fr_interval </td>
-+ <td> On read, shows the value of HFIR Frame Interval. On write, dynamically
-+ reload HFIR register during runtime. The application can write a value to this
-+ register only after the Port Enable bit of the Host Port Control and Status
-+ register (HPRT.PrtEnaPort) has been set </td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> disconnect_us </td>
-+ <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us
-+ which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>
-+ <td> Read/Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> regdump </td>
-+ <td> Dumps the contents of core registers.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> spramdump </td>
-+ <td> Dumps the contents of core registers.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hcddump </td>
-+ <td> Dumps the current HCD state.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> hcd_frrem </td>
-+ <td> Shows the average value of the Frame Remaining
-+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt
-+ occurs. This can be used to determine the average interrupt latency. Also
-+ shows the average Frame Remaining value for start_transfer and the "a" and
-+ "b" sample points. The "a" and "b" sample points may be used during debugging
-+ bto determine how long it takes to execute a section of the HCD code.</td>
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> rd_reg_test </td>
-+ <td> Displays the time required to read the GNPTXFSIZ register many times
-+ (the output shows the number of times the register is read).
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> wr_reg_test </td>
-+ <td> Displays the time required to write the GNPTXFSIZ register many times
-+ (the output shows the number of times the register is written).
-+ <td> Read</td>
-+ </tr>
-+
-+ <tr>
-+ <td> lpm_response </td>
-+ <td> Gets or sets lpm_response mode. Applicable only in device mode.
-+ <td> Write</td>
-+ </tr>
-+
-+ <tr>
-+ <td> sleep_status </td>
-+ <td> Shows sleep status of device.
-+ <td> Read</td>
-+ </tr>
-+
-+ </table>
-+
-+ Example usage:
-+ To get the current mode:
-+ cat /sys/devices/lm0/mode
-+
-+ To power down the USB:
-+ echo 0 > /sys/devices/lm0/buspower
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_os.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_attr.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_hcd_if.h"
-+
-+/*
-+ * MACROs for defining sysfs attribute
-+ */
-+#ifdef LM_INTERFACE
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);		\
-+	uint32_t val; \
-+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+	return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+					const char *buf, size_t count) \
-+{ \
-+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+	uint32_t set = simple_strtoul(buf, NULL, 16); \
-+	dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+	return count; \
-+}
-+
-+#elif defined(PCI_INTERFACE)
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);	\
-+	uint32_t val; \
-+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+	return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+					const char *buf, size_t count) \
-+{ \
-+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
-+	uint32_t set = simple_strtoul(buf, NULL, 16); \
-+	dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+	return count; \
-+}
-+
-+#elif defined(PLATFORM_INTERFACE)
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+        struct platform_device *platform_dev = \
-+                container_of(_dev, struct platform_device, dev); \
-+        dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);  \
-+	uint32_t val; \
-+	DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
-+                    __func__, _dev, platform_dev, otg_dev); \
-+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+	return sprintf (buf, "%s = 0x%x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+					const char *buf, size_t count) \
-+{ \
-+        struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+        dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+	uint32_t set = simple_strtoul(buf, NULL, 16); \
-+	dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
-+	return count; \
-+}
-+#endif
-+
-+/*
-+ * MACROs for defining sysfs attribute for 32-bit registers
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+	uint32_t val; \
-+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+	return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+					const char *buf, size_t count) \
-+{ \
-+	struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
-+	dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
-+	uint32_t val = simple_strtoul(buf, NULL, 16); \
-+	dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+	return count; \
-+}
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
-+	uint32_t val; \
-+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+	return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+					const char *buf, size_t count) \
-+{ \
-+	dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
-+	uint32_t val = simple_strtoul(buf, NULL, 16); \
-+	dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+	return count; \
-+}
-+
-+#elif defined(PLATFORM_INTERFACE)
-+#include "dwc_otg_dbg.h"
-+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
-+{ \
-+	struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+	uint32_t val; \
-+	DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
-+                    __func__, _dev, platform_dev, otg_dev); \
-+	val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
-+	return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
-+}
-+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
-+					const char *buf, size_t count) \
-+{ \
-+	struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
-+	dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
-+	uint32_t val = simple_strtoul(buf, NULL, 16); \
-+	dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
-+	return count; \
-+}
-+
-+#endif
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
-+
-+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-+
-+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
-+
-+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
-+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
-+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
-+
-+/** @name Functions for Show/Store of Attributes */
-+/**@{*/
-+
-+/**
-+ * Helper function returning the otg_device structure of the given device
-+ */
-+static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
-+{
-+        dwc_otg_device_t *otg_dev;
-+        DWC_OTG_GETDRVDEV(otg_dev, _dev);
-+        return otg_dev;
-+}
-+
-+/**
-+ * Show the register offset of the Register Access.
-+ */
-+static ssize_t regoffset_show(struct device *_dev,
-+			      struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
-+			otg_dev->os_dep.reg_offset);
-+}
-+
-+/**
-+ * Set the register offset for the next Register Access 	Read/Write
-+ */
-+static ssize_t regoffset_store(struct device *_dev,
-+			       struct device_attribute *attr,
-+			       const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t offset = simple_strtoul(buf, NULL, 16);
-+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+	if (offset < SZ_256K) {
-+#elif  defined(PCI_INTERFACE)
-+	if (offset < 0x00040000) {
-+#endif
-+		otg_dev->os_dep.reg_offset = offset;
-+	} else {
-+		dev_err(_dev, "invalid offset\n");
-+	}
-+
-+	return count;
-+}
-+
-+DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
-+
-+/**
-+ * Show the value of the register at the offset in the reg_offset
-+ * attribute.
-+ */
-+static ssize_t regvalue_show(struct device *_dev,
-+			     struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t val;
-+	volatile uint32_t *addr;
-+
-+	if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
-+		/* Calculate the address */
-+		addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
-+				     (uint8_t *) otg_dev->os_dep.base);
-+		val = DWC_READ_REG32(addr);
-+		return snprintf(buf,
-+				sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
-+				"Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
-+				val);
-+	} else {
-+		dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
-+		return sprintf(buf, "invalid offset\n");
-+	}
-+}
-+
-+/**
-+ * Store the value in the register at the offset in the reg_offset
-+ * attribute.
-+ *
-+ */
-+static ssize_t regvalue_store(struct device *_dev,
-+			      struct device_attribute *attr,
-+			      const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	volatile uint32_t *addr;
-+	uint32_t val = simple_strtoul(buf, NULL, 16);
-+	//dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
-+	if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
-+		/* Calculate the address */
-+		addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
-+				     (uint8_t *) otg_dev->os_dep.base);
-+		DWC_WRITE_REG32(addr, val);
-+	} else {
-+		dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
-+			otg_dev->os_dep.reg_offset);
-+	}
-+	return count;
-+}
-+
-+DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
-+
-+/*
-+ * Attributes
-+ */
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
-+
-+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
-+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
-+
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
-+			     &(otg_dev->core_if->core_global_regs->gusbcfg),
-+			     "GUSBCFG");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
-+			     &(otg_dev->core_if->core_global_regs->grxfsiz),
-+			     "GRXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
-+			     &(otg_dev->core_if->core_global_regs->gnptxfsiz),
-+			     "GNPTXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
-+			     &(otg_dev->core_if->core_global_regs->gpvndctl),
-+			     "GPVNDCTL");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
-+			     &(otg_dev->core_if->core_global_regs->ggpio),
-+			     "GGPIO");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
-+			     "GUID");
-+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
-+			     &(otg_dev->core_if->core_global_regs->gsnpsid),
-+			     "GSNPSID");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
-+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
-+
-+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
-+			     &(otg_dev->core_if->core_global_regs->hptxfsiz),
-+			     "HPTXFSIZ");
-+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
-+
-+/**
-+ * @todo Add code to initiate the HNP.
-+ */
-+/**
-+ * Show the HNP status bit
-+ */
-+static ssize_t hnp_show(struct device *_dev,
-+			struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	return sprintf(buf, "HstNegScs = 0x%x\n",
-+		       dwc_otg_get_hnpstatus(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the HNP Request bit
-+ */
-+static ssize_t hnp_store(struct device *_dev,
-+			 struct device_attribute *attr,
-+			 const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t in = simple_strtoul(buf, NULL, 16);
-+	dwc_otg_set_hnpreq(otg_dev->core_if, in);
-+	return count;
-+}
-+
-+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
-+
-+/**
-+ * @todo Add code to initiate the SRP.
-+ */
-+/**
-+ * Show the SRP status bit
-+ */
-+static ssize_t srp_show(struct device *_dev,
-+			struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	return sprintf(buf, "SesReqScs = 0x%x\n",
-+		       dwc_otg_get_srpstatus(otg_dev->core_if));
-+#else
-+	return sprintf(buf, "Host Only Mode!\n");
-+#endif
-+}
-+
-+/**
-+ * Set the SRP Request bit
-+ */
-+static ssize_t srp_store(struct device *_dev,
-+			 struct device_attribute *attr,
-+			 const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	dwc_otg_pcd_initiate_srp(otg_dev->pcd);
-+#endif
-+	return count;
-+}
-+
-+DEVICE_ATTR(srp, 0644, srp_show, srp_store);
-+
-+/**
-+ * @todo Need to do more for power on/off?
-+ */
-+/**
-+ * Show the Bus Power status
-+ */
-+static ssize_t buspower_show(struct device *_dev,
-+			     struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	return sprintf(buf, "Bus Power = 0x%x\n",
-+		       dwc_otg_get_prtpower(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Bus Power status
-+ */
-+static ssize_t buspower_store(struct device *_dev,
-+			      struct device_attribute *attr,
-+			      const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t on = simple_strtoul(buf, NULL, 16);
-+	dwc_otg_set_prtpower(otg_dev->core_if, on);
-+	return count;
-+}
-+
-+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
-+
-+/**
-+ * @todo Need to do more for suspend?
-+ */
-+/**
-+ * Show the Bus Suspend status
-+ */
-+static ssize_t bussuspend_show(struct device *_dev,
-+			       struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	return sprintf(buf, "Bus Suspend = 0x%x\n",
-+		       dwc_otg_get_prtsuspend(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Bus Suspend status
-+ */
-+static ssize_t bussuspend_store(struct device *_dev,
-+				struct device_attribute *attr,
-+				const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t in = simple_strtoul(buf, NULL, 16);
-+	dwc_otg_set_prtsuspend(otg_dev->core_if, in);
-+	return count;
-+}
-+
-+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
-+
-+/**
-+ * Show the Mode Change Ready Timer status
-+ */
-+static ssize_t mode_ch_tim_en_show(struct device *_dev,
-+				   struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
-+		       dwc_otg_get_mode_ch_tim(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the Mode Change Ready Timer status
-+ */
-+static ssize_t mode_ch_tim_en_store(struct device *_dev,
-+				    struct device_attribute *attr,
-+				    const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t in = simple_strtoul(buf, NULL, 16);
-+	dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
-+	return count;
-+}
-+
-+DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
-+
-+/**
-+ * Show the value of HFIR Frame Interval bitfield
-+ */
-+static ssize_t fr_interval_show(struct device *_dev,
-+				struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	return sprintf(buf, "Frame Interval = 0x%x\n",
-+		       dwc_otg_get_fr_interval(otg_dev->core_if));
-+}
-+
-+/**
-+ * Set the HFIR Frame Interval value
-+ */
-+static ssize_t fr_interval_store(struct device *_dev,
-+				 struct device_attribute *attr,
-+				 const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t in = simple_strtoul(buf, NULL, 10);
-+	dwc_otg_set_fr_interval(otg_dev->core_if, in);
-+	return count;
-+}
-+
-+DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
-+
-+/**
-+ * Show the status of Remote Wakeup.
-+ */
-+static ssize_t remote_wakeup_show(struct device *_dev,
-+				  struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+	return sprintf(buf,
-+		       "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
-+		       dwc_otg_get_remotewakesig(otg_dev->core_if),
-+		       dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
-+		       dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
-+#else
-+	return sprintf(buf, "Host Only Mode!\n");
-+#endif /* DWC_HOST_ONLY */
-+}
-+
-+/**
-+ * Initiate a remote wakeup of the host.  The Device control register
-+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
-+ * flag is set.
-+ *
-+ */
-+static ssize_t remote_wakeup_store(struct device *_dev,
-+				   struct device_attribute *attr,
-+				   const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t val = simple_strtoul(buf, NULL, 16);
-+
-+	if (val & 1) {
-+		dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
-+	} else {
-+		dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
-+	}
-+#endif /* DWC_HOST_ONLY */
-+	return count;
-+}
-+
-+DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
-+	    remote_wakeup_store);
-+
-+/**
-+ * Show the whether core is hibernated or not.
-+ */
-+static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
-+				     struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_HOST_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+	if (dwc_otg_get_core_state(otg_dev->core_if)) {
-+		DWC_PRINTF("Core is in hibernation\n");
-+	} else {
-+		DWC_PRINTF("Core is not in hibernation\n");
-+	}
-+#endif /* DWC_HOST_ONLY */
-+	return 0;
-+}
-+
-+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+					      int rem_wakeup, int reset);
-+
-+/**
-+ * Initiate a remote wakeup of the device to exit from hibernation.
-+ */
-+static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
-+				      struct device_attribute *attr,
-+				      const char *buf, size_t count)
-+{
-+#ifndef DWC_HOST_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
-+#endif
-+	return count;
-+}
-+
-+DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
-+	    rem_wakeup_pwrdn_store);
-+
-+static ssize_t disconnect_us(struct device *_dev,
-+			     struct device_attribute *attr,
-+			     const char *buf, size_t count)
-+{
-+
-+#ifndef DWC_HOST_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t val = simple_strtoul(buf, NULL, 16);
-+	DWC_PRINTF("The Passed value is %04x\n", val);
-+
-+	dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
-+
-+#endif /* DWC_HOST_ONLY */
-+	return count;
-+}
-+
-+DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
-+
-+/**
-+ * Dump global registers and either host or device registers (depending on the
-+ * current mode of the core).
-+ */
-+static ssize_t regdump_show(struct device *_dev,
-+			    struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+	dwc_otg_dump_global_registers(otg_dev->core_if);
-+	if (dwc_otg_is_host_mode(otg_dev->core_if)) {
-+		dwc_otg_dump_host_registers(otg_dev->core_if);
-+	} else {
-+		dwc_otg_dump_dev_registers(otg_dev->core_if);
-+
-+	}
-+	return sprintf(buf, "Register Dump\n");
-+}
-+
-+DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
-+
-+/**
-+ * Dump global registers and either host or device registers (depending on the
-+ * current mode of the core).
-+ */
-+static ssize_t spramdump_show(struct device *_dev,
-+			      struct device_attribute *attr, char *buf)
-+{
-+#if 0
-+	dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+	dwc_otg_dump_spram(otg_dev->core_if);
-+#endif
-+
-+	return sprintf(buf, "SPRAM Dump\n");
-+}
-+
-+DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
-+
-+/**
-+ * Dump the current hcd state.
-+ */
-+static ssize_t hcddump_show(struct device *_dev,
-+			    struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_DEVICE_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	dwc_otg_hcd_dump_state(otg_dev->hcd);
-+#endif /* DWC_DEVICE_ONLY */
-+	return sprintf(buf, "HCD Dump\n");
-+}
-+
-+DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
-+
-+/**
-+ * Dump the average frame remaining at SOF. This can be used to
-+ * determine average interrupt latency. Frame remaining is also shown for
-+ * start transfer and two additional sample points.
-+ */
-+static ssize_t hcd_frrem_show(struct device *_dev,
-+			      struct device_attribute *attr, char *buf)
-+{
-+#ifndef DWC_DEVICE_ONLY
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+	dwc_otg_hcd_dump_frrem(otg_dev->hcd);
-+#endif /* DWC_DEVICE_ONLY */
-+	return sprintf(buf, "HCD Dump Frame Remaining\n");
-+}
-+
-+DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
-+
-+/**
-+ * Displays the time required to read the GNPTXFSIZ register many times (the
-+ * output shows the number of times the register is read).
-+ */
-+#define RW_REG_COUNT 10000000
-+#define MSEC_PER_JIFFIE 1000/HZ
-+static ssize_t rd_reg_test_show(struct device *_dev,
-+				struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	int i;
-+	int time;
-+	int start_jiffies;
-+
-+	printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
-+	       HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
-+	start_jiffies = jiffies;
-+	for (i = 0; i < RW_REG_COUNT; i++) {
-+		dwc_otg_get_gnptxfsiz(otg_dev->core_if);
-+	}
-+	time = jiffies - start_jiffies;
-+	return sprintf(buf,
-+		       "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
-+		       RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
-+}
-+
-+DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
-+
-+/**
-+ * Displays the time required to write the GNPTXFSIZ register many times (the
-+ * output shows the number of times the register is written).
-+ */
-+static ssize_t wr_reg_test_show(struct device *_dev,
-+				struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t reg_val;
-+	int i;
-+	int time;
-+	int start_jiffies;
-+
-+	printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
-+	       HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
-+	reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
-+	start_jiffies = jiffies;
-+	for (i = 0; i < RW_REG_COUNT; i++) {
-+		dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
-+	}
-+	time = jiffies - start_jiffies;
-+	return sprintf(buf,
-+		       "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
-+		       RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
-+}
-+
-+DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+
-+/**
-+* Show the lpm_response attribute.
-+*/
-+static ssize_t lpmresp_show(struct device *_dev,
-+			    struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+
-+	if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
-+		return sprintf(buf, "** LPM is DISABLED **\n");
-+
-+	if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
-+		return sprintf(buf, "** Current mode is not device mode\n");
-+	}
-+	return sprintf(buf, "lpm_response = %d\n",
-+		       dwc_otg_get_lpmresponse(otg_dev->core_if));
-+}
-+
-+/**
-+* Store the lpm_response attribute.
-+*/
-+static ssize_t lpmresp_store(struct device *_dev,
-+			     struct device_attribute *attr,
-+			     const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	uint32_t val = simple_strtoul(buf, NULL, 16);
-+
-+	if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
-+		return 0;
-+	}
-+
-+	if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
-+		return 0;
-+	}
-+
-+	dwc_otg_set_lpmresponse(otg_dev->core_if, val);
-+	return count;
-+}
-+
-+DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
-+
-+/**
-+* Show the sleep_status attribute.
-+*/
-+static ssize_t sleepstatus_show(struct device *_dev,
-+				struct device_attribute *attr, char *buf)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	return sprintf(buf, "Sleep Status = %d\n",
-+		       dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
-+}
-+
-+/**
-+ * Store the sleep_status attribure.
-+ */
-+static ssize_t sleepstatus_store(struct device *_dev,
-+				 struct device_attribute *attr,
-+				 const char *buf, size_t count)
-+{
-+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
-+	dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+	if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
-+		if (dwc_otg_is_host_mode(core_if)) {
-+
-+			DWC_PRINTF("Host initiated resume\n");
-+			dwc_otg_set_prtresume(otg_dev->core_if, 1);
-+		}
-+	}
-+
-+	return count;
-+}
-+
-+DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
-+	    sleepstatus_store);
-+
-+#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
-+
-+/**@}*/
-+
-+/**
-+ * Create the device files
-+ */
-+void dwc_otg_attr_create(
-+#ifdef LM_INTERFACE
-+	struct lm_device *dev
-+#elif  defined(PCI_INTERFACE)
-+	struct pci_dev *dev
-+#elif  defined(PLATFORM_INTERFACE)
-+        struct platform_device *dev
-+#endif
-+    )
-+{
-+	int error;
-+
-+	error = device_create_file(&dev->dev, &dev_attr_regoffset);
-+	error = device_create_file(&dev->dev, &dev_attr_regvalue);
-+	error = device_create_file(&dev->dev, &dev_attr_mode);
-+	error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
-+	error = device_create_file(&dev->dev, &dev_attr_srpcapable);
-+	error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
-+	error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
-+	error = device_create_file(&dev->dev, &dev_attr_hnp);
-+	error = device_create_file(&dev->dev, &dev_attr_srp);
-+	error = device_create_file(&dev->dev, &dev_attr_buspower);
-+	error = device_create_file(&dev->dev, &dev_attr_bussuspend);
-+	error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
-+	error = device_create_file(&dev->dev, &dev_attr_fr_interval);
-+	error = device_create_file(&dev->dev, &dev_attr_busconnected);
-+	error = device_create_file(&dev->dev, &dev_attr_gotgctl);
-+	error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
-+	error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
-+	error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
-+	error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
-+	error = device_create_file(&dev->dev, &dev_attr_ggpio);
-+	error = device_create_file(&dev->dev, &dev_attr_guid);
-+	error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
-+	error = device_create_file(&dev->dev, &dev_attr_devspeed);
-+	error = device_create_file(&dev->dev, &dev_attr_enumspeed);
-+	error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
-+	error = device_create_file(&dev->dev, &dev_attr_hprt0);
-+	error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
-+	error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
-+	error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
-+	error = device_create_file(&dev->dev, &dev_attr_regdump);
-+	error = device_create_file(&dev->dev, &dev_attr_spramdump);
-+	error = device_create_file(&dev->dev, &dev_attr_hcddump);
-+	error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
-+	error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
-+	error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	error = device_create_file(&dev->dev, &dev_attr_lpm_response);
-+	error = device_create_file(&dev->dev, &dev_attr_sleep_status);
-+#endif
-+}
-+
-+/**
-+ * Remove the device files
-+ */
-+void dwc_otg_attr_remove(
-+#ifdef LM_INTERFACE
-+	struct lm_device *dev
-+#elif  defined(PCI_INTERFACE)
-+	struct pci_dev *dev
-+#elif  defined(PLATFORM_INTERFACE)
-+	struct platform_device *dev
-+#endif
-+    )
-+{
-+	device_remove_file(&dev->dev, &dev_attr_regoffset);
-+	device_remove_file(&dev->dev, &dev_attr_regvalue);
-+	device_remove_file(&dev->dev, &dev_attr_mode);
-+	device_remove_file(&dev->dev, &dev_attr_hnpcapable);
-+	device_remove_file(&dev->dev, &dev_attr_srpcapable);
-+	device_remove_file(&dev->dev, &dev_attr_hsic_connect);
-+	device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
-+	device_remove_file(&dev->dev, &dev_attr_hnp);
-+	device_remove_file(&dev->dev, &dev_attr_srp);
-+	device_remove_file(&dev->dev, &dev_attr_buspower);
-+	device_remove_file(&dev->dev, &dev_attr_bussuspend);
-+	device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
-+	device_remove_file(&dev->dev, &dev_attr_fr_interval);
-+	device_remove_file(&dev->dev, &dev_attr_busconnected);
-+	device_remove_file(&dev->dev, &dev_attr_gotgctl);
-+	device_remove_file(&dev->dev, &dev_attr_gusbcfg);
-+	device_remove_file(&dev->dev, &dev_attr_grxfsiz);
-+	device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
-+	device_remove_file(&dev->dev, &dev_attr_gpvndctl);
-+	device_remove_file(&dev->dev, &dev_attr_ggpio);
-+	device_remove_file(&dev->dev, &dev_attr_guid);
-+	device_remove_file(&dev->dev, &dev_attr_gsnpsid);
-+	device_remove_file(&dev->dev, &dev_attr_devspeed);
-+	device_remove_file(&dev->dev, &dev_attr_enumspeed);
-+	device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
-+	device_remove_file(&dev->dev, &dev_attr_hprt0);
-+	device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
-+	device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
-+	device_remove_file(&dev->dev, &dev_attr_disconnect_us);
-+	device_remove_file(&dev->dev, &dev_attr_regdump);
-+	device_remove_file(&dev->dev, &dev_attr_spramdump);
-+	device_remove_file(&dev->dev, &dev_attr_hcddump);
-+	device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
-+	device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
-+	device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	device_remove_file(&dev->dev, &dev_attr_lpm_response);
-+	device_remove_file(&dev->dev, &dev_attr_sleep_status);
-+#endif
-+}
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.h
-@@ -0,0 +1,89 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
-+ * $Revision: #13 $
-+ * $Date: 2010/06/21 $
-+ * $Change: 1532021 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_OTG_ATTR_H__)
-+#define __DWC_OTG_ATTR_H__
-+
-+/** @file
-+ * This file contains the interface to the Linux device attributes.
-+ */
-+extern struct device_attribute dev_attr_regoffset;
-+extern struct device_attribute dev_attr_regvalue;
-+
-+extern struct device_attribute dev_attr_mode;
-+extern struct device_attribute dev_attr_hnpcapable;
-+extern struct device_attribute dev_attr_srpcapable;
-+extern struct device_attribute dev_attr_hnp;
-+extern struct device_attribute dev_attr_srp;
-+extern struct device_attribute dev_attr_buspower;
-+extern struct device_attribute dev_attr_bussuspend;
-+extern struct device_attribute dev_attr_mode_ch_tim_en;
-+extern struct device_attribute dev_attr_fr_interval;
-+extern struct device_attribute dev_attr_busconnected;
-+extern struct device_attribute dev_attr_gotgctl;
-+extern struct device_attribute dev_attr_gusbcfg;
-+extern struct device_attribute dev_attr_grxfsiz;
-+extern struct device_attribute dev_attr_gnptxfsiz;
-+extern struct device_attribute dev_attr_gpvndctl;
-+extern struct device_attribute dev_attr_ggpio;
-+extern struct device_attribute dev_attr_guid;
-+extern struct device_attribute dev_attr_gsnpsid;
-+extern struct device_attribute dev_attr_devspeed;
-+extern struct device_attribute dev_attr_enumspeed;
-+extern struct device_attribute dev_attr_hptxfsiz;
-+extern struct device_attribute dev_attr_hprt0;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+extern struct device_attribute dev_attr_lpm_response;
-+extern struct device_attribute devi_attr_sleep_status;
-+#endif
-+
-+void dwc_otg_attr_create(
-+#ifdef LM_INTERFACE
-+				struct lm_device *dev
-+#elif  defined(PCI_INTERFACE)
-+				struct pci_dev *dev
-+#elif  defined(PLATFORM_INTERFACE)
-+	struct platform_device *dev
-+#endif
-+    );
-+
-+void dwc_otg_attr_remove(
-+#ifdef LM_INTERFACE
-+				struct lm_device *dev
-+#elif  defined(PCI_INTERFACE)
-+				struct pci_dev *dev
-+#elif  defined(PLATFORM_INTERFACE)
-+	struct platform_device *dev
-+#endif
-+    );
-+#endif
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
-@@ -0,0 +1,1876 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * This file contains the most of the CFI(Core Feature Interface)
-+ * implementation for the OTG.
-+ */
-+
-+#ifdef DWC_UTE_CFI
-+
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_cfi.h"
-+
-+/** This definition should actually migrate to the Portability Library */
-+#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
-+
-+extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
-+
-+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
-+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
-+				 struct dwc_otg_pcd *pcd,
-+				 struct cfi_usb_ctrlrequest *ctrl_req);
-+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
-+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+			     struct cfi_usb_ctrlrequest *req);
-+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+				 struct cfi_usb_ctrlrequest *req);
-+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+				struct cfi_usb_ctrlrequest *req);
-+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
-+			     struct cfi_usb_ctrlrequest *req);
-+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
-+
-+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
-+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
-+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
-+
-+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
-+
-+/** This is the header of the all features descriptor */
-+static cfi_all_features_header_t all_props_desc_header = {
-+	.wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
-+	.wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
-+	.wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
-+};
-+
-+/** This is an array of statically allocated feature descriptors */
-+static cfi_feature_desc_header_t prop_descs[] = {
-+
-+	/* FT_ID_DMA_MODE */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
-+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
-+	 },
-+
-+	/* FT_ID_DMA_BUFFER_SETUP */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
-+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+	 },
-+
-+	/* FT_ID_DMA_BUFF_ALIGN */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
-+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+	 },
-+
-+	/* FT_ID_DMA_CONCAT_SETUP */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
-+	 //.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),
-+	 },
-+
-+	/* FT_ID_DMA_CIRCULAR */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
-+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+	 },
-+
-+	/* FT_ID_THRESHOLD_SETUP */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
-+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
-+	 },
-+
-+	/* FT_ID_DFIFO_DEPTH */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RO,
-+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+	 },
-+
-+	/* FT_ID_TX_FIFO_DEPTH */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
-+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+	 },
-+
-+	/* FT_ID_RX_FIFO_DEPTH */
-+	{
-+	 .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
-+	 .bmAttributes = CFI_FEATURE_ATTR_RW,
-+	 .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
-+	 }
-+};
-+
-+/** The table of feature names */
-+cfi_string_t prop_name_table[] = {
-+	{FT_ID_DMA_MODE, "dma_mode"},
-+	{FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
-+	{FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
-+	{FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
-+	{FT_ID_DMA_CIRCULAR, "buffer_circular"},
-+	{FT_ID_THRESHOLD_SETUP, "threshold_setup"},
-+	{FT_ID_DFIFO_DEPTH, "dfifo_depth"},
-+	{FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
-+	{FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
-+	{}
-+};
-+
-+/************************************************************************/
-+
-+/**
-+ * Returns the name of the feature by its ID
-+ * or NULL if no featute ID matches.
-+ *
-+ */
-+const uint8_t *get_prop_name(uint16_t prop_id, int *len)
-+{
-+	cfi_string_t *pstr;
-+	*len = 0;
-+
-+	for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
-+		if (pstr->id == prop_id) {
-+			*len = DWC_STRLEN(pstr->s);
-+			return pstr->s;
-+		}
-+	}
-+	return NULL;
-+}
-+
-+/**
-+ * This function handles all CFI specific control requests.
-+ *
-+ * Return a negative value to stall the DCE.
-+ */
-+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
-+{
-+	int retval = 0;
-+	dwc_otg_pcd_ep_t *ep = NULL;
-+	cfiobject_t *cfi = pcd->cfi;
-+	struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
-+	uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
-+	uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
-+	uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
-+	uint32_t regaddr = 0;
-+	uint32_t regval = 0;
-+
-+	/* Save this Control Request in the CFI object.
-+	 * The data field will be assigned in the data stage completion CB function.
-+	 */
-+	cfi->ctrl_req = *ctrl;
-+	cfi->ctrl_req.data = NULL;
-+
-+	cfi->need_gadget_att = 0;
-+	cfi->need_status_in_complete = 0;
-+
-+	switch (ctrl->bRequest) {
-+	case VEN_CORE_GET_FEATURES:
-+		retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
-+		if (retval >= 0) {
-+			//dump_msg(cfi->buf_in.buf, retval);
-+			ep = &pcd->ep0;
-+
-+			retval = min((uint16_t) retval, wLen);
-+			/* Transfer this buffer to the host through the EP0-IN EP */
-+			ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+			ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+			ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+			ep->dwc_ep.xfer_len = retval;
-+			ep->dwc_ep.xfer_count = 0;
-+			ep->dwc_ep.sent_zlp = 0;
-+			ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+			pcd->ep0_pending = 1;
-+			dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+		}
-+		retval = 0;
-+		break;
-+
-+	case VEN_CORE_GET_FEATURE:
-+		CFI_INFO("VEN_CORE_GET_FEATURE\n");
-+		retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
-+					       pcd, ctrl);
-+		if (retval >= 0) {
-+			ep = &pcd->ep0;
-+
-+			retval = min((uint16_t) retval, wLen);
-+			/* Transfer this buffer to the host through the EP0-IN EP */
-+			ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+			ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+			ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+			ep->dwc_ep.xfer_len = retval;
-+			ep->dwc_ep.xfer_count = 0;
-+			ep->dwc_ep.sent_zlp = 0;
-+			ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+			pcd->ep0_pending = 1;
-+			dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+		}
-+		CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
-+		dump_msg(cfi->buf_in.buf, retval);
-+		break;
-+
-+	case VEN_CORE_SET_FEATURE:
-+		CFI_INFO("VEN_CORE_SET_FEATURE\n");
-+		/* Set up an XFER to get the data stage of the control request,
-+		 * which is the new value of the feature to be modified.
-+		 */
-+		ep = &pcd->ep0;
-+		ep->dwc_ep.is_in = 0;
-+		ep->dwc_ep.dma_addr = cfi->buf_out.addr;
-+		ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
-+		ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
-+		ep->dwc_ep.xfer_len = wLen;
-+		ep->dwc_ep.xfer_count = 0;
-+		ep->dwc_ep.sent_zlp = 0;
-+		ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+		pcd->ep0_pending = 1;
-+		/* Read the control write's data stage */
-+		dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+		retval = 0;
-+		break;
-+
-+	case VEN_CORE_RESET_FEATURES:
-+		CFI_INFO("VEN_CORE_RESET_FEATURES\n");
-+		cfi->need_gadget_att = 1;
-+		cfi->need_status_in_complete = 1;
-+		retval = cfi_preproc_reset(pcd, ctrl);
-+		CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
-+		break;
-+
-+	case VEN_CORE_ACTIVATE_FEATURES:
-+		CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
-+		break;
-+
-+	case VEN_CORE_READ_REGISTER:
-+		CFI_INFO("VEN_CORE_READ_REGISTER\n");
-+		/* wValue optionally contains the HI WORD of the register offset and
-+		 * wIndex contains the LOW WORD of the register offset
-+		 */
-+		if (wValue == 0) {
-+			/* @TODO - MAS - fix the access to the base field */
-+			regaddr = 0;
-+			//regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
-+			//GET_CORE_IF(pcd)->co
-+			regaddr |= wIndex;
-+		} else {
-+			regaddr = (wValue << 16) | wIndex;
-+		}
-+
-+		/* Read a 32-bit value of the memory at the regaddr */
-+		regval = DWC_READ_REG32((uint32_t *) regaddr);
-+
-+		ep = &pcd->ep0;
-+		dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
-+		ep->dwc_ep.is_in = 1;
-+		ep->dwc_ep.dma_addr = cfi->buf_in.addr;
-+		ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
-+		ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
-+		ep->dwc_ep.xfer_len = wLen;
-+		ep->dwc_ep.xfer_count = 0;
-+		ep->dwc_ep.sent_zlp = 0;
-+		ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+		pcd->ep0_pending = 1;
-+		dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+		cfi->need_gadget_att = 0;
-+		retval = 0;
-+		break;
-+
-+	case VEN_CORE_WRITE_REGISTER:
-+		CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
-+		/* Set up an XFER to get the data stage of the control request,
-+		 * which is the new value of the register to be modified.
-+		 */
-+		ep = &pcd->ep0;
-+		ep->dwc_ep.is_in = 0;
-+		ep->dwc_ep.dma_addr = cfi->buf_out.addr;
-+		ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
-+		ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
-+		ep->dwc_ep.xfer_len = wLen;
-+		ep->dwc_ep.xfer_count = 0;
-+		ep->dwc_ep.sent_zlp = 0;
-+		ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+		pcd->ep0_pending = 1;
-+		/* Read the control write's data stage */
-+		dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
-+		retval = 0;
-+		break;
-+
-+	default:
-+		retval = -DWC_E_NOT_SUPPORTED;
-+		break;
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function prepares the core features descriptors and copies its
-+ * raw representation into the buffer <buf>.
-+ *
-+ * The buffer structure is as follows:
-+ *	all_features_header (8 bytes)
-+ *	features_#1 (8 bytes + feature name string length)
-+ *	features_#2 (8 bytes + feature name string length)
-+ *	.....
-+ *	features_#n - where n=the total count of feature descriptors
-+ */
-+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
-+{
-+	cfi_feature_desc_header_t *prop_hdr = prop_descs;
-+	cfi_feature_desc_header_t *prop;
-+	cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
-+	cfi_all_features_header_t *tmp;
-+	uint8_t *tmpbuf = buf;
-+	const uint8_t *pname = NULL;
-+	int i, j, namelen = 0, totlen;
-+
-+	/* Prepare and copy the core features into the buffer */
-+	CFI_INFO("%s:\n", __func__);
-+
-+	tmp = (cfi_all_features_header_t *) tmpbuf;
-+	*tmp = *all_props_hdr;
-+	tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
-+
-+	j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
-+	for (i = 0; i < j; i++, prop_hdr++) {
-+		pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
-+		prop = (cfi_feature_desc_header_t *) tmpbuf;
-+		*prop = *prop_hdr;
-+
-+		prop->bNameLen = namelen;
-+		prop->wLength =
-+		    DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
-+					     namelen);
-+
-+		tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
-+		dwc_memcpy(tmpbuf, pname, namelen);
-+		tmpbuf += namelen;
-+	}
-+
-+	totlen = tmpbuf - buf;
-+
-+	if (totlen > 0) {
-+		tmp = (cfi_all_features_header_t *) buf;
-+		tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
-+	}
-+
-+	return totlen;
-+}
-+
-+/**
-+ * This function releases all the dynamic memory in the CFI object.
-+ */
-+static void cfi_release(cfiobject_t * cfiobj)
-+{
-+	cfi_ep_t *cfiep;
-+	dwc_list_link_t *tmp;
-+
-+	CFI_INFO("%s\n", __func__);
-+
-+	if (cfiobj->buf_in.buf) {
-+		DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
-+			     cfiobj->buf_in.addr);
-+		cfiobj->buf_in.buf = NULL;
-+	}
-+
-+	if (cfiobj->buf_out.buf) {
-+		DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
-+			     cfiobj->buf_out.addr);
-+		cfiobj->buf_out.buf = NULL;
-+	}
-+
-+	/* Free the Buffer Setup values for each EP */
-+	//list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
-+	DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
-+		cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+		cfi_free_ep_bs_dyn_data(cfiep);
-+	}
-+}
-+
-+/**
-+ * This function frees the dynamically allocated EP buffer setup data.
-+ */
-+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
-+{
-+	if (cfiep->bm_sg) {
-+		DWC_FREE(cfiep->bm_sg);
-+		cfiep->bm_sg = NULL;
-+	}
-+
-+	if (cfiep->bm_align) {
-+		DWC_FREE(cfiep->bm_align);
-+		cfiep->bm_align = NULL;
-+	}
-+
-+	if (cfiep->bm_concat) {
-+		if (NULL != cfiep->bm_concat->wTxBytes) {
-+			DWC_FREE(cfiep->bm_concat->wTxBytes);
-+			cfiep->bm_concat->wTxBytes = NULL;
-+		}
-+		DWC_FREE(cfiep->bm_concat);
-+		cfiep->bm_concat = NULL;
-+	}
-+}
-+
-+/**
-+ * This function initializes the default values of the features
-+ * for a specific endpoint and should be called only once when
-+ * the EP is enabled first time.
-+ */
-+static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
-+{
-+	int retval = 0;
-+
-+	cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
-+	if (NULL == cfiep->bm_sg) {
-+		CFI_INFO("Failed to allocate memory for SG feature value\n");
-+		return -DWC_E_NO_MEMORY;
-+	}
-+	dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+
-+	/* For the Concatenation feature's default value we do not allocate
-+	 * memory for the wTxBytes field - it will be done in the set_feature_value
-+	 * request handler.
-+	 */
-+	cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
-+	if (NULL == cfiep->bm_concat) {
-+		CFI_INFO
-+		    ("Failed to allocate memory for CONCATENATION feature value\n");
-+		DWC_FREE(cfiep->bm_sg);
-+		return -DWC_E_NO_MEMORY;
-+	}
-+	dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
-+
-+	cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
-+	if (NULL == cfiep->bm_align) {
-+		CFI_INFO
-+		    ("Failed to allocate memory for Alignment feature value\n");
-+		DWC_FREE(cfiep->bm_sg);
-+		DWC_FREE(cfiep->bm_concat);
-+		return -DWC_E_NO_MEMORY;
-+	}
-+	dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
-+
-+	return retval;
-+}
-+
-+/**
-+ * The callback function that notifies the CFI on the activation of
-+ * an endpoint in the PCD. The following steps are done in this function:
-+ *
-+ *	Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's
-+ *		active endpoint)
-+ *	Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
-+ *	Set the Buffer Mode to standard
-+ *	Initialize the default values for all EP modes (SG, Circular, Concat, Align)
-+ *	Add the cfi_ep_t object to the list of active endpoints in the CFI object
-+ */
-+static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
-+			 struct dwc_otg_pcd_ep *ep)
-+{
-+	cfi_ep_t *cfiep;
-+	int retval = -DWC_E_NOT_SUPPORTED;
-+
-+	CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
-+		 "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
-+	/* MAS - Check whether this endpoint already is in the list */
-+	cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
-+
-+	if (NULL == cfiep) {
-+		/* Allocate a cfi_ep_t object */
-+		cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
-+		if (NULL == cfiep) {
-+			CFI_INFO
-+			    ("Unable to allocate memory for <cfiep> in function %s\n",
-+			     __func__);
-+			return -DWC_E_NO_MEMORY;
-+		}
-+		dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
-+
-+		/* Save the dwc_otg_pcd_ep pointer in the cfiep object */
-+		cfiep->ep = ep;
-+
-+		/* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
-+		ep->dwc_ep.descs =
-+		    DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
-+				  sizeof(dwc_otg_dma_desc_t),
-+				  &ep->dwc_ep.descs_dma_addr);
-+
-+		if (NULL == ep->dwc_ep.descs) {
-+			DWC_FREE(cfiep);
-+			return -DWC_E_NO_MEMORY;
-+		}
-+
-+		DWC_LIST_INIT(&cfiep->lh);
-+
-+		/* Set the buffer mode to BM_STANDARD. It will be modified
-+		 * when building descriptors for a specific buffer mode */
-+		ep->dwc_ep.buff_mode = BM_STANDARD;
-+
-+		/* Create and initialize the default values for this EP's Buffer modes */
-+		if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
-+			return retval;
-+
-+		/* Add the cfi_ep_t object to the CFI object's list of active endpoints */
-+		DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
-+		retval = 0;
-+	} else {		/* The sought EP already is in the list */
-+		CFI_INFO("%s: The sought EP already is in the list\n",
-+			 __func__);
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function is called when the data stage of a 3-stage Control Write request
-+ * is complete.
-+ *
-+ */
-+static int cfi_ctrl_write_complete(struct cfiobject *cfi,
-+				   struct dwc_otg_pcd *pcd)
-+{
-+	uint32_t addr, reg_value;
-+	uint16_t wIndex, wValue;
-+	uint8_t bRequest;
-+	uint8_t *buf = cfi->buf_out.buf;
-+	//struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
-+	struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
-+	int retval = -DWC_E_NOT_SUPPORTED;
-+
-+	CFI_INFO("%s\n", __func__);
-+
-+	bRequest = ctrl_req->bRequest;
-+	wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
-+	wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
-+
-+	/*
-+	 * Save the pointer to the data stage in the ctrl_req's <data> field.
-+	 * The request should be already saved in the command stage by now.
-+	 */
-+	ctrl_req->data = cfi->buf_out.buf;
-+	cfi->need_status_in_complete = 0;
-+	cfi->need_gadget_att = 0;
-+
-+	switch (bRequest) {
-+	case VEN_CORE_WRITE_REGISTER:
-+		/* The buffer contains raw data of the new value for the register */
-+		reg_value = *((uint32_t *) buf);
-+		if (wValue == 0) {
-+			addr = 0;
-+			//addr = (uint32_t) pcd->otg_dev->os_dep.base;
-+			addr += wIndex;
-+		} else {
-+			addr = (wValue << 16) | wIndex;
-+		}
-+
-+		//writel(reg_value, addr);
-+
-+		retval = 0;
-+		cfi->need_status_in_complete = 1;
-+		break;
-+
-+	case VEN_CORE_SET_FEATURE:
-+		/* The buffer contains raw data of the new value of the feature */
-+		retval = cfi_set_feature_value(pcd);
-+		if (retval < 0)
-+			return retval;
-+
-+		cfi->need_status_in_complete = 1;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the SG buffer mode.
-+ */
-+static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+			       dwc_otg_pcd_request_t * req)
-+{
-+	struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+	ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
-+	struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+	struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
-+	dma_addr_t buff_addr = req->dma;
-+	int i;
-+	uint32_t txsize, off;
-+
-+	txsize = sgval->wSize;
-+	off = sgval->bOffset;
-+
-+//      CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n",
-+//              __func__, cfiep->ep->ep.name, txsize, off);
-+
-+	for (i = 0; i < sgval->bCount; i++) {
-+		desc->status.b.bs = BS_HOST_BUSY;
-+		desc->buf = buff_addr;
-+		desc->status.b.l = 0;
-+		desc->status.b.ioc = 0;
-+		desc->status.b.sp = 0;
-+		desc->status.b.bytes = txsize;
-+		desc->status.b.bs = BS_HOST_READY;
-+
-+		/* Set the next address of the buffer */
-+		buff_addr += txsize + off;
-+		desc_last = desc;
-+		desc++;
-+	}
-+
-+	/* Set the last, ioc and sp bits on the Last DMA Descriptor */
-+	desc_last->status.b.l = 1;
-+	desc_last->status.b.ioc = 1;
-+	desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
-+	/* Save the last DMA descriptor pointer */
-+	cfiep->dma_desc_last = desc_last;
-+	cfiep->desc_count = sgval->bCount;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Concatenation buffer mode.
-+ */
-+static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+				   dwc_otg_pcd_request_t * req)
-+{
-+	struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+	ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
-+	struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+	struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
-+	dma_addr_t buff_addr = req->dma;
-+	int i;
-+	uint16_t *txsize;
-+
-+	txsize = concatval->wTxBytes;
-+
-+	for (i = 0; i < concatval->hdr.bDescCount; i++) {
-+		desc->buf = buff_addr;
-+		desc->status.b.bs = BS_HOST_BUSY;
-+		desc->status.b.l = 0;
-+		desc->status.b.ioc = 0;
-+		desc->status.b.sp = 0;
-+		desc->status.b.bytes = *txsize;
-+		desc->status.b.bs = BS_HOST_READY;
-+
-+		txsize++;
-+		/* Set the next address of the buffer */
-+		buff_addr += UGETW(ep->desc->wMaxPacketSize);
-+		desc_last = desc;
-+		desc++;
-+	}
-+
-+	/* Set the last, ioc and sp bits on the Last DMA Descriptor */
-+	desc_last->status.b.l = 1;
-+	desc_last->status.b.ioc = 1;
-+	desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
-+	cfiep->dma_desc_last = desc_last;
-+	cfiep->desc_count = concatval->hdr.bDescCount;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Circular buffer mode
-+ */
-+static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+				 dwc_otg_pcd_request_t * req)
-+{
-+	/* @todo: MAS - add implementation when this feature needs to be tested */
-+}
-+
-+/**
-+ * This function builds the DMA descriptors for the Alignment buffer mode
-+ */
-+static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
-+				  dwc_otg_pcd_request_t * req)
-+{
-+	struct dwc_otg_pcd_ep *ep = cfiep->ep;
-+	ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
-+	struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
-+	dma_addr_t buff_addr = req->dma;
-+
-+	desc->status.b.bs = BS_HOST_BUSY;
-+	desc->status.b.l = 1;
-+	desc->status.b.ioc = 1;
-+	desc->status.b.sp = ep->dwc_ep.sent_zlp;
-+	desc->status.b.bytes = req->length;
-+	/* Adjust the buffer alignment */
-+	desc->buf = (buff_addr + alignval->bAlign);
-+	desc->status.b.bs = BS_HOST_READY;
-+	cfiep->dma_desc_last = desc;
-+	cfiep->desc_count = 1;
-+}
-+
-+/**
-+ * This function builds the DMA descriptors chain for different modes of the
-+ * buffer setup of an endpoint.
-+ */
-+static void cfi_build_descriptors(struct cfiobject *cfi,
-+				  struct dwc_otg_pcd *pcd,
-+				  struct dwc_otg_pcd_ep *ep,
-+				  dwc_otg_pcd_request_t * req)
-+{
-+	cfi_ep_t *cfiep;
-+
-+	/* Get the cfiep by the dwc_otg_pcd_ep */
-+	cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
-+	if (NULL == cfiep) {
-+		CFI_INFO("%s: Unable to find a matching active endpoint\n",
-+			 __func__);
-+		return;
-+	}
-+
-+	cfiep->xfer_len = req->length;
-+
-+	/* Iterate through all the DMA descriptors */
-+	switch (cfiep->ep->dwc_ep.buff_mode) {
-+	case BM_SG:
-+		cfi_build_sg_descs(cfi, cfiep, req);
-+		break;
-+
-+	case BM_CONCAT:
-+		cfi_build_concat_descs(cfi, cfiep, req);
-+		break;
-+
-+	case BM_CIRCULAR:
-+		cfi_build_circ_descs(cfi, cfiep, req);
-+		break;
-+
-+	case BM_ALIGN:
-+		cfi_build_align_descs(cfi, cfiep, req);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+/**
-+ * Allocate DMA buffer for different Buffer modes.
-+ */
-+static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
-+			      struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
-+			      unsigned size, gfp_t flags)
-+{
-+	return DWC_DMA_ALLOC(size, dma);
-+}
-+
-+/**
-+ * This function initializes the CFI object.
-+ */
-+int init_cfi(cfiobject_t * cfiobj)
-+{
-+	CFI_INFO("%s\n", __func__);
-+
-+	/* Allocate a buffer for IN XFERs */
-+	cfiobj->buf_in.buf =
-+	    DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
-+	if (NULL == cfiobj->buf_in.buf) {
-+		CFI_INFO("Unable to allocate buffer for INs\n");
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	/* Allocate a buffer for OUT XFERs */
-+	cfiobj->buf_out.buf =
-+	    DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
-+	if (NULL == cfiobj->buf_out.buf) {
-+		CFI_INFO("Unable to allocate buffer for OUT\n");
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	/* Initialize the callback function pointers */
-+	cfiobj->ops.release = cfi_release;
-+	cfiobj->ops.ep_enable = cfi_ep_enable;
-+	cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
-+	cfiobj->ops.build_descriptors = cfi_build_descriptors;
-+	cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
-+
-+	/* Initialize the list of active endpoints in the CFI object */
-+	DWC_LIST_INIT(&cfiobj->active_eps);
-+
-+	return 0;
-+}
-+
-+/**
-+ * This function reads the required feature's current value into the buffer
-+ *
-+ * @retval: Returns negative as error, or the data length of the feature
-+ */
-+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
-+				 struct dwc_otg_pcd *pcd,
-+				 struct cfi_usb_ctrlrequest *ctrl_req)
-+{
-+	int retval = -DWC_E_NOT_SUPPORTED;
-+	struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
-+	uint16_t dfifo, rxfifo, txfifo;
-+
-+	switch (ctrl_req->wIndex) {
-+		/* Whether the DDMA is enabled or not */
-+	case FT_ID_DMA_MODE:
-+		*buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
-+		retval = 1;
-+		break;
-+
-+	case FT_ID_DMA_BUFFER_SETUP:
-+		retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
-+		break;
-+
-+	case FT_ID_DMA_BUFF_ALIGN:
-+		retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
-+		break;
-+
-+	case FT_ID_DMA_CONCAT_SETUP:
-+		retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
-+		break;
-+
-+	case FT_ID_DMA_CIRCULAR:
-+		CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
-+		break;
-+
-+	case FT_ID_THRESHOLD_SETUP:
-+		CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
-+		break;
-+
-+	case FT_ID_DFIFO_DEPTH:
-+		dfifo = get_dfifo_size(coreif);
-+		*((uint16_t *) buf) = dfifo;
-+		retval = sizeof(uint16_t);
-+		break;
-+
-+	case FT_ID_TX_FIFO_DEPTH:
-+		retval = get_txfifo_size(pcd, ctrl_req->wValue);
-+		if (retval >= 0) {
-+			txfifo = retval;
-+			*((uint16_t *) buf) = txfifo;
-+			retval = sizeof(uint16_t);
-+		}
-+		break;
-+
-+	case FT_ID_RX_FIFO_DEPTH:
-+		retval = get_rxfifo_size(coreif, ctrl_req->wValue);
-+		if (retval >= 0) {
-+			rxfifo = retval;
-+			*((uint16_t *) buf) = rxfifo;
-+			retval = sizeof(uint16_t);
-+		}
-+		break;
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function resets the SG for the specified EP to its default value
-+ */
-+static int cfi_reset_sg_val(cfi_ep_t * cfiep)
-+{
-+	dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+	return 0;
-+}
-+
-+/**
-+ * This function resets the Alignment for the specified EP to its default value
-+ */
-+static int cfi_reset_align_val(cfi_ep_t * cfiep)
-+{
-+	dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
-+	return 0;
-+}
-+
-+/**
-+ * This function resets the Concatenation for the specified EP to its default value
-+ * This function will also set the value of the wTxBytes field to NULL after
-+ * freeing the memory previously allocated for this field.
-+ */
-+static int cfi_reset_concat_val(cfi_ep_t * cfiep)
-+{
-+	/* First we need to free the wTxBytes field */
-+	if (cfiep->bm_concat->wTxBytes) {
-+		DWC_FREE(cfiep->bm_concat->wTxBytes);
-+		cfiep->bm_concat->wTxBytes = NULL;
-+	}
-+
-+	dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
-+	return 0;
-+}
-+
-+/**
-+ * This function resets all the buffer setups of the specified endpoint
-+ */
-+static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
-+{
-+	cfi_reset_sg_val(cfiep);
-+	cfi_reset_align_val(cfiep);
-+	cfi_reset_concat_val(cfiep);
-+	return 0;
-+}
-+
-+static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
-+				     uint8_t rx_rst, uint8_t tx_rst)
-+{
-+	int retval = -DWC_E_INVALID;
-+	uint16_t tx_siz[15];
-+	uint16_t rx_siz = 0;
-+	dwc_otg_pcd_ep_t *ep = NULL;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+
-+	if (rx_rst) {
-+		rx_siz = params->dev_rx_fifo_size;
-+		params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
-+	}
-+
-+	if (tx_rst) {
-+		if (ep_addr == 0) {
-+			int i;
-+
-+			for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+				tx_siz[i] =
-+				    core_if->core_params->dev_tx_fifo_size[i];
-+				core_if->core_params->dev_tx_fifo_size[i] =
-+				    core_if->init_txfsiz[i];
-+			}
-+		} else {
-+
-+			ep = get_ep_by_addr(pcd, ep_addr);
-+
-+			if (NULL == ep) {
-+				CFI_INFO
-+				    ("%s: Unable to get the endpoint addr=0x%02x\n",
-+				     __func__, ep_addr);
-+				return -DWC_E_INVALID;
-+			}
-+
-+			tx_siz[0] =
-+			    params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
-+						     1];
-+			params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
-+			    GET_CORE_IF(pcd)->init_txfsiz[ep->
-+							  dwc_ep.tx_fifo_num -
-+							  1];
-+		}
-+	}
-+
-+	if (resize_fifos(GET_CORE_IF(pcd))) {
-+		retval = 0;
-+	} else {
-+		CFI_INFO
-+		    ("%s: Error resetting the feature Reset All(FIFO size)\n",
-+		     __func__);
-+		if (rx_rst) {
-+			params->dev_rx_fifo_size = rx_siz;
-+		}
-+
-+		if (tx_rst) {
-+			if (ep_addr == 0) {
-+				int i;
-+				for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
-+				     i++) {
-+					core_if->
-+					    core_params->dev_tx_fifo_size[i] =
-+					    tx_siz[i];
-+				}
-+			} else {
-+				params->dev_tx_fifo_size[ep->
-+							 dwc_ep.tx_fifo_num -
-+							 1] = tx_siz[0];
-+			}
-+		}
-+		retval = -DWC_E_INVALID;
-+	}
-+	return retval;
-+}
-+
-+static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+	int retval = 0;
-+	cfi_ep_t *cfiep;
-+	cfiobject_t *cfi = pcd->cfi;
-+	dwc_list_link_t *tmp;
-+
-+	retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
-+	if (retval < 0) {
-+		return retval;
-+	}
-+
-+	/* If the EP address is known then reset the features for only that EP */
-+	if (addr) {
-+		cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+		if (NULL == cfiep) {
-+			CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+				 __func__, addr);
-+			return -DWC_E_INVALID;
-+		}
-+		retval = cfi_ep_reset_all_setup_vals(cfiep);
-+		cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
-+	}
-+	/* Otherwise (wValue == 0), reset all features of all EP's */
-+	else {
-+		/* Traverse all the active EP's and reset the feature(s) value(s) */
-+		//list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+		DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+			cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+			retval = cfi_ep_reset_all_setup_vals(cfiep);
-+			cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
-+			if (retval < 0) {
-+				CFI_INFO
-+				    ("%s: Error resetting the feature Reset All\n",
-+				     __func__);
-+				return retval;
-+			}
-+		}
-+	}
-+	return retval;
-+}
-+
-+static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
-+					   uint8_t addr)
-+{
-+	int retval = 0;
-+	cfi_ep_t *cfiep;
-+	cfiobject_t *cfi = pcd->cfi;
-+	dwc_list_link_t *tmp;
-+
-+	/* If the EP address is known then reset the features for only that EP */
-+	if (addr) {
-+		cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+		if (NULL == cfiep) {
-+			CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+				 __func__, addr);
-+			return -DWC_E_INVALID;
-+		}
-+		retval = cfi_reset_sg_val(cfiep);
-+	}
-+	/* Otherwise (wValue == 0), reset all features of all EP's */
-+	else {
-+		/* Traverse all the active EP's and reset the feature(s) value(s) */
-+		//list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+		DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+			cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+			retval = cfi_reset_sg_val(cfiep);
-+			if (retval < 0) {
-+				CFI_INFO
-+				    ("%s: Error resetting the feature Buffer Setup\n",
-+				     __func__);
-+				return retval;
-+			}
-+		}
-+	}
-+	return retval;
-+}
-+
-+static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+	int retval = 0;
-+	cfi_ep_t *cfiep;
-+	cfiobject_t *cfi = pcd->cfi;
-+	dwc_list_link_t *tmp;
-+
-+	/* If the EP address is known then reset the features for only that EP */
-+	if (addr) {
-+		cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+		if (NULL == cfiep) {
-+			CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+				 __func__, addr);
-+			return -DWC_E_INVALID;
-+		}
-+		retval = cfi_reset_concat_val(cfiep);
-+	}
-+	/* Otherwise (wValue == 0), reset all features of all EP's */
-+	else {
-+		/* Traverse all the active EP's and reset the feature(s) value(s) */
-+		//list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+		DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+			cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+			retval = cfi_reset_concat_val(cfiep);
-+			if (retval < 0) {
-+				CFI_INFO
-+				    ("%s: Error resetting the feature Concatenation Value\n",
-+				     __func__);
-+				return retval;
-+			}
-+		}
-+	}
-+	return retval;
-+}
-+
-+static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
-+{
-+	int retval = 0;
-+	cfi_ep_t *cfiep;
-+	cfiobject_t *cfi = pcd->cfi;
-+	dwc_list_link_t *tmp;
-+
-+	/* If the EP address is known then reset the features for only that EP */
-+	if (addr) {
-+		cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+		if (NULL == cfiep) {
-+			CFI_INFO("%s: Error getting the EP address 0x%02x\n",
-+				 __func__, addr);
-+			return -DWC_E_INVALID;
-+		}
-+		retval = cfi_reset_align_val(cfiep);
-+	}
-+	/* Otherwise (wValue == 0), reset all features of all EP's */
-+	else {
-+		/* Traverse all the active EP's and reset the feature(s) value(s) */
-+		//list_for_each_entry(cfiep, &cfi->active_eps, lh) {
-+		DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+			cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+			retval = cfi_reset_align_val(cfiep);
-+			if (retval < 0) {
-+				CFI_INFO
-+				    ("%s: Error resetting the feature Aliignment Value\n",
-+				     __func__);
-+				return retval;
-+			}
-+		}
-+	}
-+	return retval;
-+
-+}
-+
-+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
-+			     struct cfi_usb_ctrlrequest *req)
-+{
-+	int retval = 0;
-+
-+	switch (req->wIndex) {
-+	case 0:
-+		/* Reset all features */
-+		retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
-+		break;
-+
-+	case FT_ID_DMA_BUFFER_SETUP:
-+		/* Reset the SG buffer setup */
-+		retval =
-+		    cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
-+		break;
-+
-+	case FT_ID_DMA_CONCAT_SETUP:
-+		/* Reset the Concatenation buffer setup */
-+		retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
-+		break;
-+
-+	case FT_ID_DMA_BUFF_ALIGN:
-+		/* Reset the Alignment buffer setup */
-+		retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
-+		break;
-+
-+	case FT_ID_TX_FIFO_DEPTH:
-+		retval =
-+		    cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
-+		pcd->cfi->need_gadget_att = 0;
-+		break;
-+
-+	case FT_ID_RX_FIFO_DEPTH:
-+		retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
-+		pcd->cfi->need_gadget_att = 0;
-+		break;
-+	default:
-+		break;
-+	}
-+	return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the SG buffer setup.
-+ */
-+static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+	uint8_t inaddr, outaddr;
-+	cfi_ep_t *epin, *epout;
-+	ddma_sg_buffer_setup_t *psgval;
-+	uint32_t desccount, size;
-+
-+	CFI_INFO("%s\n", __func__);
-+
-+	psgval = (ddma_sg_buffer_setup_t *) buf;
-+	desccount = (uint32_t) psgval->bCount;
-+	size = (uint32_t) psgval->wSize;
-+
-+	/* Check the DMA descriptor count */
-+	if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
-+		CFI_INFO
-+		    ("%s: The count of DMA Descriptors should be between 1 and %d\n",
-+		     __func__, MAX_DMA_DESCS_PER_EP);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	/* Check the DMA descriptor count */
-+
-+	if (size == 0) {
-+
-+		CFI_INFO("%s: The transfer size should be at least 1 byte\n",
-+			 __func__);
-+
-+		return -DWC_E_INVALID;
-+
-+	}
-+
-+	inaddr = psgval->bInEndpointAddress;
-+	outaddr = psgval->bOutEndpointAddress;
-+
-+	epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
-+	epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
-+
-+	if (NULL == epin || NULL == epout) {
-+		CFI_INFO
-+		    ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
-+		     __func__, inaddr, outaddr);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	epin->ep->dwc_ep.buff_mode = BM_SG;
-+	dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
-+
-+	epout->ep->dwc_ep.buff_mode = BM_SG;
-+	dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
-+
-+	return 0;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+	cfi_ep_t *ep;
-+	uint8_t addr;
-+	ddma_align_buffer_setup_t *palignval;
-+
-+	palignval = (ddma_align_buffer_setup_t *) buf;
-+	addr = palignval->bEndpointAddress;
-+
-+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+
-+	if (NULL == ep) {
-+		CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+			 __func__, addr);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	ep->ep->dwc_ep.buff_mode = BM_ALIGN;
-+	dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
-+
-+	return 0;
-+}
-+
-+/**
-+ * This function sets a new value for the Concatenation buffer setup.
-+ */
-+static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
-+{
-+	uint8_t addr;
-+	cfi_ep_t *ep;
-+	struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
-+	uint16_t *pVals;
-+	uint32_t desccount;
-+	int i;
-+	uint16_t mps;
-+
-+	pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
-+	desccount = (uint32_t) pConcatValHdr->bDescCount;
-+	pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
-+
-+	/* Check the DMA descriptor count */
-+	if (desccount > MAX_DMA_DESCS_PER_EP) {
-+		CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
-+			 __func__, MAX_DMA_DESCS_PER_EP);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	addr = pConcatValHdr->bEndpointAddress;
-+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+	if (NULL == ep) {
-+		CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+			 __func__, addr);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	mps = UGETW(ep->ep->desc->wMaxPacketSize);
-+
-+#if 0
-+	for (i = 0; i < desccount; i++) {
-+		CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
-+	}
-+	CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
-+#endif
-+
-+	/* Check the wTxSizes to be less than or equal to the mps */
-+	for (i = 0; i < desccount; i++) {
-+		if (pVals[i] > mps) {
-+			CFI_INFO
-+			    ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
-+			     __func__, i, pVals[i]);
-+			return -DWC_E_INVALID;
-+		}
-+	}
-+
-+	ep->ep->dwc_ep.buff_mode = BM_CONCAT;
-+	dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
-+
-+	/* Free the previously allocated storage for the wTxBytes */
-+	if (ep->bm_concat->wTxBytes) {
-+		DWC_FREE(ep->bm_concat->wTxBytes);
-+	}
-+
-+	/* Allocate a new storage for the wTxBytes field */
-+	ep->bm_concat->wTxBytes =
-+	    DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
-+	if (NULL == ep->bm_concat->wTxBytes) {
-+		CFI_INFO("%s: Unable to allocate memory\n", __func__);
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	/* Copy the new values into the wTxBytes filed */
-+	dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
-+		   sizeof(uint16_t) * pConcatValHdr->bDescCount);
-+
-+	return 0;
-+}
-+
-+/**
-+ * This function calculates the total of all FIFO sizes
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_core_params_t *params = core_if->core_params;
-+	uint16_t dfifo_total = 0;
-+	int i;
-+
-+	/* The shared RxFIFO size */
-+	dfifo_total =
-+	    params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
-+
-+	/* Add up each TxFIFO size to the total */
-+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+		dfifo_total += params->dev_tx_fifo_size[i];
-+	}
-+
-+	return dfifo_total;
-+}
-+
-+/**
-+ * This function returns Rx FIFO size
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
-+{
-+	switch (wValue >> 8) {
-+	case 0:
-+		return (core_if->pwron_rxfsiz <
-+			32768) ? core_if->pwron_rxfsiz : 32768;
-+		break;
-+	case 1:
-+		return core_if->core_params->dev_rx_fifo_size;
-+		break;
-+	default:
-+		return -DWC_E_INVALID;
-+		break;
-+	}
-+}
-+
-+/**
-+ * This function returns Tx FIFO size for IN EP
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return The total of data FIFO sizes.
-+ *
-+ */
-+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+
-+	ep = get_ep_by_addr(pcd, wValue & 0xff);
-+
-+	if (NULL == ep) {
-+		CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+			 __func__, wValue & 0xff);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (!ep->dwc_ep.is_in) {
-+		CFI_INFO
-+		    ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
-+		     __func__, wValue & 0xff);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	switch (wValue >> 8) {
-+	case 0:
-+		return (GET_CORE_IF(pcd)->pwron_txfsiz
-+			[ep->dwc_ep.tx_fifo_num - 1] <
-+			768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
-+							      dwc_ep.tx_fifo_num
-+							      - 1] : 32768;
-+		break;
-+	case 1:
-+		return GET_CORE_IF(pcd)->core_params->
-+		    dev_tx_fifo_size[ep->dwc_ep.num - 1];
-+		break;
-+	default:
-+		return -DWC_E_INVALID;
-+		break;
-+	}
-+}
-+
-+/**
-+ * This function checks if the submitted combination of
-+ * device mode FIFO sizes is possible or not.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return 1 if possible, 0 otherwise.
-+ *
-+ */
-+static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
-+{
-+	uint16_t dfifo_actual = 0;
-+	dwc_otg_core_params_t *params = core_if->core_params;
-+	uint16_t start_addr = 0;
-+	int i;
-+
-+	dfifo_actual =
-+	    params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
-+
-+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+		dfifo_actual += params->dev_tx_fifo_size[i];
-+	}
-+
-+	if (dfifo_actual > core_if->total_fifo_size) {
-+		return 0;
-+	}
-+
-+	if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
-+		return 0;
-+
-+	if (params->dev_nperio_tx_fifo_size > 32768
-+	    || params->dev_nperio_tx_fifo_size < 16)
-+		return 0;
-+
-+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+		if (params->dev_tx_fifo_size[i] > 768
-+		    || params->dev_tx_fifo_size[i] < 4)
-+			return 0;
-+	}
-+
-+	if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
-+		return 0;
-+	start_addr = params->dev_rx_fifo_size;
-+
-+	if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
-+		return 0;
-+	start_addr += params->dev_nperio_tx_fifo_size;
-+
-+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+		if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
-+			return 0;
-+		start_addr += params->dev_tx_fifo_size[i];
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * This function resizes Device mode FIFOs
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ * @return 1 if successful, 0 otherwise
-+ *
-+ */
-+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
-+{
-+	int i = 0;
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	dwc_otg_core_params_t *params = core_if->core_params;
-+	uint32_t rx_fifo_size;
-+	fifosize_data_t nptxfifosize;
-+	fifosize_data_t txfifosize[15];
-+
-+	uint32_t rx_fsz_bak;
-+	uint32_t nptxfsz_bak;
-+	uint32_t txfsz_bak[15];
-+
-+	uint16_t start_address;
-+	uint8_t retval = 1;
-+
-+	if (!check_fifo_sizes(core_if)) {
-+		return 0;
-+	}
-+
-+	/* Configure data FIFO sizes */
-+	if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+		rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
-+		rx_fifo_size = params->dev_rx_fifo_size;
-+		DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
-+
-+		/*
-+		 * Tx FIFOs These FIFOs are numbered from 1 to 15.
-+		 * Indexes of the FIFO size module parameters in the
-+		 * dev_tx_fifo_size array and the FIFO size registers in
-+		 * the dtxfsiz array run from 0 to 14.
-+		 */
-+
-+		/* Non-periodic Tx FIFO */
-+		nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
-+		nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+		start_address = params->dev_rx_fifo_size;
-+		nptxfifosize.b.startaddr = start_address;
-+
-+		DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+
-+		start_address += nptxfifosize.b.depth;
-+
-+		for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+			txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
-+
-+			txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
-+			txfifosize[i].b.startaddr = start_address;
-+			DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+					txfifosize[i].d32);
-+
-+			start_address += txfifosize[i].b.depth;
-+		}
-+
-+		/** Check if register values are set correctly */
-+		if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
-+			retval = 0;
-+		}
-+
-+		if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
-+			retval = 0;
-+		}
-+
-+		for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+			if (txfifosize[i].d32 !=
-+			    DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
-+				retval = 0;
-+			}
-+		}
-+
-+		/** If register values are not set correctly, reset old values */
-+		if (retval == 0) {
-+			DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
-+
-+			/* Non-periodic Tx FIFO */
-+			DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
-+
-+			for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+				DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+						txfsz_bak[i]);
-+			}
-+		}
-+	} else {
-+		return 0;
-+	}
-+
-+	/* Flush the FIFOs */
-+	dwc_otg_flush_tx_fifo(core_if, 0x10);	/* all Tx FIFOs */
-+	dwc_otg_flush_rx_fifo(core_if);
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
-+{
-+	int retval;
-+	uint32_t fsiz;
-+	uint16_t size;
-+	uint16_t ep_addr;
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+	tx_fifo_size_setup_t *ptxfifoval;
-+
-+	ptxfifoval = (tx_fifo_size_setup_t *) buf;
-+	ep_addr = ptxfifoval->bEndpointAddress;
-+	size = ptxfifoval->wDepth;
-+
-+	ep = get_ep_by_addr(pcd, ep_addr);
-+
-+	CFI_INFO
-+	    ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
-+	     __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
-+
-+	if (NULL == ep) {
-+		CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
-+			 __func__, ep_addr);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
-+	params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
-+
-+	if (resize_fifos(GET_CORE_IF(pcd))) {
-+		retval = 0;
-+	} else {
-+		CFI_INFO
-+		    ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
-+		     __func__, ep_addr);
-+		params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the buffer Alignment setup.
-+ */
-+static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
-+{
-+	int retval;
-+	uint32_t fsiz;
-+	uint16_t size;
-+	dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
-+	rx_fifo_size_setup_t *prxfifoval;
-+
-+	prxfifoval = (rx_fifo_size_setup_t *) buf;
-+	size = prxfifoval->wDepth;
-+
-+	fsiz = params->dev_rx_fifo_size;
-+	params->dev_rx_fifo_size = size;
-+
-+	if (resize_fifos(GET_CORE_IF(pcd))) {
-+		retval = 0;
-+	} else {
-+		CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
-+			 __func__);
-+		params->dev_rx_fifo_size = fsiz;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function reads the SG of an EP's buffer setup into the buffer buf
-+ */
-+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+			     struct cfi_usb_ctrlrequest *req)
-+{
-+	int retval = -DWC_E_INVALID;
-+	uint8_t addr;
-+	cfi_ep_t *ep;
-+
-+	/* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+	addr = req->wValue & 0xFF;
-+	if (addr == 0)		/* The address should be non-zero */
-+		return retval;
-+
-+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+	if (NULL == ep) {
-+		CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+			 __func__, addr);
-+		return retval;
-+	}
-+
-+	dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
-+	retval = BS_SG_VAL_DESC_LEN;
-+	return retval;
-+}
-+
-+/**
-+ * This function reads the Concatenation value of an EP's buffer mode into
-+ * the buffer buf
-+ */
-+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+				 struct cfi_usb_ctrlrequest *req)
-+{
-+	int retval = -DWC_E_INVALID;
-+	uint8_t addr;
-+	cfi_ep_t *ep;
-+	uint8_t desc_count;
-+
-+	/* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+	addr = req->wValue & 0xFF;
-+	if (addr == 0)		/* The address should be non-zero */
-+		return retval;
-+
-+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+	if (NULL == ep) {
-+		CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+			 __func__, addr);
-+		return retval;
-+	}
-+
-+	/* Copy the header to the buffer */
-+	dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
-+	/* Advance the buffer pointer by the header size */
-+	buf += BS_CONCAT_VAL_HDR_LEN;
-+
-+	desc_count = ep->bm_concat->hdr.bDescCount;
-+	/* Copy alll the wTxBytes to the buffer */
-+	dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
-+
-+	retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
-+	return retval;
-+}
-+
-+/**
-+ * This function reads the buffer Alignment value of an EP's buffer mode into
-+ * the buffer buf
-+ *
-+ * @return The total number of bytes copied to the buffer or negative error code.
-+ */
-+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
-+				struct cfi_usb_ctrlrequest *req)
-+{
-+	int retval = -DWC_E_INVALID;
-+	uint8_t addr;
-+	cfi_ep_t *ep;
-+
-+	/* The Low Byte of the wValue contains a non-zero address of the endpoint */
-+	addr = req->wValue & 0xFF;
-+	if (addr == 0)		/* The address should be non-zero */
-+		return retval;
-+
-+	ep = get_cfi_ep_by_addr(pcd->cfi, addr);
-+	if (NULL == ep) {
-+		CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
-+			 __func__, addr);
-+		return retval;
-+	}
-+
-+	dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
-+	retval = BS_ALIGN_VAL_HDR_LEN;
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function sets a new value for the specified feature
-+ *
-+ * @param	pcd	A pointer to the PCD object
-+ *
-+ * @return 0 if successful, negative error code otherwise to stall the DCE.
-+ */
-+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
-+{
-+	int retval = -DWC_E_NOT_SUPPORTED;
-+	uint16_t wIndex, wValue;
-+	uint8_t bRequest;
-+	struct dwc_otg_core_if *coreif;
-+	cfiobject_t *cfi = pcd->cfi;
-+	struct cfi_usb_ctrlrequest *ctrl_req;
-+	uint8_t *buf;
-+	ctrl_req = &cfi->ctrl_req;
-+
-+	buf = pcd->cfi->ctrl_req.data;
-+
-+	coreif = GET_CORE_IF(pcd);
-+	bRequest = ctrl_req->bRequest;
-+	wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
-+	wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
-+
-+	/* See which feature is to be modified */
-+	switch (wIndex) {
-+	case FT_ID_DMA_BUFFER_SETUP:
-+		/* Modify the feature */
-+		if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
-+			return retval;
-+
-+		/* And send this request to the gadget */
-+		cfi->need_gadget_att = 1;
-+		break;
-+
-+	case FT_ID_DMA_BUFF_ALIGN:
-+		if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
-+			return retval;
-+		cfi->need_gadget_att = 1;
-+		break;
-+
-+	case FT_ID_DMA_CONCAT_SETUP:
-+		/* Modify the feature */
-+		if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
-+			return retval;
-+		cfi->need_gadget_att = 1;
-+		break;
-+
-+	case FT_ID_DMA_CIRCULAR:
-+		CFI_INFO("FT_ID_DMA_CIRCULAR\n");
-+		break;
-+
-+	case FT_ID_THRESHOLD_SETUP:
-+		CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
-+		break;
-+
-+	case FT_ID_DFIFO_DEPTH:
-+		CFI_INFO("FT_ID_DFIFO_DEPTH\n");
-+		break;
-+
-+	case FT_ID_TX_FIFO_DEPTH:
-+		CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
-+		if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
-+			return retval;
-+		cfi->need_gadget_att = 0;
-+		break;
-+
-+	case FT_ID_RX_FIFO_DEPTH:
-+		CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
-+		if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
-+			return retval;
-+		cfi->need_gadget_att = 0;
-+		break;
-+	}
-+
-+	return retval;
-+}
-+
-+#endif //DWC_UTE_CFI
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
-@@ -0,0 +1,320 @@
-+/* ==========================================================================
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_OTG_CFI_H__)
-+#define __DWC_OTG_CFI_H__
-+
-+#include "dwc_otg_pcd.h"
-+#include "dwc_cfi_common.h"
-+
-+/**
-+ * @file
-+ * This file contains the CFI related OTG PCD specific common constants,
-+ * interfaces(functions and macros) and data structures.The CFI Protocol is an
-+ * optional interface for internal testing purposes that a DUT may implement to
-+ * support testing of configurable features.
-+ *
-+ */
-+
-+struct dwc_otg_pcd;
-+struct dwc_otg_pcd_ep;
-+
-+/** OTG CFI Features (properties) ID constants */
-+/** This is a request for all Core Features */
-+#define FT_ID_DMA_MODE					0x0001
-+#define FT_ID_DMA_BUFFER_SETUP			0x0002
-+#define FT_ID_DMA_BUFF_ALIGN			0x0003
-+#define FT_ID_DMA_CONCAT_SETUP			0x0004
-+#define FT_ID_DMA_CIRCULAR				0x0005
-+#define FT_ID_THRESHOLD_SETUP			0x0006
-+#define FT_ID_DFIFO_DEPTH				0x0007
-+#define FT_ID_TX_FIFO_DEPTH				0x0008
-+#define FT_ID_RX_FIFO_DEPTH				0x0009
-+
-+/**********************************************************/
-+#define CFI_INFO_DEF
-+
-+#ifdef CFI_INFO_DEF
-+#define CFI_INFO(fmt...)	DWC_PRINTF("CFI: " fmt);
-+#else
-+#define CFI_INFO(fmt...)
-+#endif
-+
-+#define min(x,y) ({ \
-+	x < y ? x : y; })
-+
-+#define max(x,y) ({ \
-+	x > y ? x : y; })
-+
-+/**
-+ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
-+ * also used for setting up a buffer for Circular DDMA.
-+ */
-+struct _ddma_sg_buffer_setup {
-+#define BS_SG_VAL_DESC_LEN	6
-+	/* The OUT EP address */
-+	uint8_t bOutEndpointAddress;
-+	/* The IN EP address */
-+	uint8_t bInEndpointAddress;
-+	/* Number of bytes to put between transfer segments (must be DWORD boundaries) */
-+	uint8_t bOffset;
-+	/* The number of transfer segments (a DMA descriptors per each segment) */
-+	uint8_t bCount;
-+	/* Size (in byte) of each transfer segment */
-+	uint16_t wSize;
-+} __attribute__ ((packed));
-+typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
-+
-+/** Descriptor DMA Concatenation Buffer setup structure */
-+struct _ddma_concat_buffer_setup_hdr {
-+#define BS_CONCAT_VAL_HDR_LEN	4
-+	/* The endpoint for which the buffer is to be set up */
-+	uint8_t bEndpointAddress;
-+	/* The count of descriptors to be used */
-+	uint8_t bDescCount;
-+	/* The total size of the transfer */
-+	uint16_t wSize;
-+} __attribute__ ((packed));
-+typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
-+
-+/** Descriptor DMA Concatenation Buffer setup structure */
-+struct _ddma_concat_buffer_setup {
-+	/* The SG header */
-+	ddma_concat_buffer_setup_hdr_t hdr;
-+
-+	/* The XFER sizes pointer (allocated dynamically) */
-+	uint16_t *wTxBytes;
-+} __attribute__ ((packed));
-+typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
-+
-+/** Descriptor DMA Alignment Buffer setup structure */
-+struct _ddma_align_buffer_setup {
-+#define BS_ALIGN_VAL_HDR_LEN	2
-+	uint8_t bEndpointAddress;
-+	uint8_t bAlign;
-+} __attribute__ ((packed));
-+typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
-+
-+/** Transmit FIFO Size setup structure */
-+struct _tx_fifo_size_setup {
-+	uint8_t bEndpointAddress;
-+	uint16_t wDepth;
-+} __attribute__ ((packed));
-+typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
-+
-+/** Transmit FIFO Size setup structure */
-+struct _rx_fifo_size_setup {
-+	uint16_t wDepth;
-+} __attribute__ ((packed));
-+typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
-+
-+/**
-+ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
-+ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer
-+ * to the data returned in the data stage of a 3-stage Control Write requests.
-+ */
-+struct cfi_usb_ctrlrequest {
-+	uint8_t bRequestType;
-+	uint8_t bRequest;
-+	uint16_t wValue;
-+	uint16_t wIndex;
-+	uint16_t wLength;
-+	uint8_t *data;
-+} UPACKED;
-+
-+/*---------------------------------------------------------------------------*/
-+
-+/**
-+ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
-+ * This structure is used to store the buffer setup data for any
-+ * enabled endpoint in the PCD.
-+ */
-+struct cfi_ep {
-+	/* Entry for the list container */
-+	dwc_list_link_t lh;
-+	/* Pointer to the active PCD endpoint structure */
-+	struct dwc_otg_pcd_ep *ep;
-+	/* The last descriptor in the chain of DMA descriptors of the endpoint */
-+	struct dwc_otg_dma_desc *dma_desc_last;
-+	/* The SG feature value */
-+	ddma_sg_buffer_setup_t *bm_sg;
-+	/* The Circular feature value */
-+	ddma_sg_buffer_setup_t *bm_circ;
-+	/* The Concatenation feature value */
-+	ddma_concat_buffer_setup_t *bm_concat;
-+	/* The Alignment feature value */
-+	ddma_align_buffer_setup_t *bm_align;
-+	/* XFER length */
-+	uint32_t xfer_len;
-+	/*
-+	 * Count of DMA descriptors currently used.
-+	 * The total should not exceed the MAX_DMA_DESCS_PER_EP value
-+	 * defined in the dwc_otg_cil.h
-+	 */
-+	uint32_t desc_count;
-+};
-+typedef struct cfi_ep cfi_ep_t;
-+
-+typedef struct cfi_dma_buff {
-+#define CFI_IN_BUF_LEN	1024
-+#define CFI_OUT_BUF_LEN	1024
-+	dma_addr_t addr;
-+	uint8_t *buf;
-+} cfi_dma_buff_t;
-+
-+struct cfiobject;
-+
-+/**
-+ * This is the interface for the CFI operations.
-+ *
-+ * @param	ep_enable			Called when any endpoint is enabled and activated.
-+ * @param	release				Called when the CFI object is released and it needs to correctly
-+ *								deallocate the dynamic memory
-+ * @param	ctrl_write_complete	Called when the data stage of the request is complete
-+ */
-+typedef struct cfi_ops {
-+	int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
-+			  struct dwc_otg_pcd_ep * ep);
-+	void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
-+			       struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
-+			       unsigned size, gfp_t flags);
-+	void (*release) (struct cfiobject * cfi);
-+	int (*ctrl_write_complete) (struct cfiobject * cfi,
-+				    struct dwc_otg_pcd * pcd);
-+	void (*build_descriptors) (struct cfiobject * cfi,
-+				   struct dwc_otg_pcd * pcd,
-+				   struct dwc_otg_pcd_ep * ep,
-+				   dwc_otg_pcd_request_t * req);
-+} cfi_ops_t;
-+
-+struct cfiobject {
-+	cfi_ops_t ops;
-+	struct dwc_otg_pcd *pcd;
-+	struct usb_gadget *gadget;
-+
-+	/* Buffers used to send/receive CFI-related request data */
-+	cfi_dma_buff_t buf_in;
-+	cfi_dma_buff_t buf_out;
-+
-+	/* CFI specific Control request wrapper */
-+	struct cfi_usb_ctrlrequest ctrl_req;
-+
-+	/* The list of active EP's in the PCD of type cfi_ep_t */
-+	dwc_list_link_t active_eps;
-+
-+	/* This flag shall control the propagation of a specific request
-+	 * to the gadget's processing routines.
-+	 * 0 - no gadget handling
-+	 * 1 - the gadget needs to know about this request (w/o completing a status
-+	 * phase - just return a 0 to the _setup callback)
-+	 */
-+	uint8_t need_gadget_att;
-+
-+	/* Flag indicating whether the status IN phase needs to be
-+	 * completed by the PCD
-+	 */
-+	uint8_t need_status_in_complete;
-+};
-+typedef struct cfiobject cfiobject_t;
-+
-+#define DUMP_MSG
-+
-+#if defined(DUMP_MSG)
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+	unsigned int start, num, i;
-+	char line[52], *p;
-+
-+	if (length >= 512)
-+		return;
-+
-+	start = 0;
-+	while (length > 0) {
-+		num = min(length, 16u);
-+		p = line;
-+		for (i = 0; i < num; ++i) {
-+			if (i == 8)
-+				*p++ = ' ';
-+			DWC_SPRINTF(p, " %02x", buf[i]);
-+			p += 3;
-+		}
-+		*p = 0;
-+		DWC_DEBUG("%6x: %s\n", start, line);
-+		buf += num;
-+		start += num;
-+		length -= num;
-+	}
-+}
-+#else
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+}
-+#endif
-+
-+/**
-+ * This function returns a pointer to cfi_ep_t object with the addr address.
-+ */
-+static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
-+						uint8_t addr)
-+{
-+	struct cfi_ep *pcfiep;
-+	dwc_list_link_t *tmp;
-+
-+	DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+		pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+
-+		if (pcfiep->ep->desc->bEndpointAddress == addr) {
-+			return pcfiep;
-+		}
-+	}
-+
-+	return NULL;
-+}
-+
-+/**
-+ * This function returns a pointer to cfi_ep_t object that matches
-+ * the dwc_otg_pcd_ep object.
-+ */
-+static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
-+						  struct dwc_otg_pcd_ep *ep)
-+{
-+	struct cfi_ep *pcfiep = NULL;
-+	dwc_list_link_t *tmp;
-+
-+	DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
-+		pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
-+		if (pcfiep->ep == ep) {
-+			return pcfiep;
-+		}
-+	}
-+	return NULL;
-+}
-+
-+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
-+
-+#endif /* (__DWC_OTG_CFI_H__) */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c
-@@ -0,0 +1,7141 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
-+ * $Revision: #191 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The Core Interface Layer provides basic services for accessing and
-+ * managing the DWC_otg hardware. These services are used by both the
-+ * Host Controller Driver and the Peripheral Controller Driver.
-+ *
-+ * The CIL manages the memory map for the core so that the HCD and PCD
-+ * don't have to do this separately. It also handles basic tasks like
-+ * reading/writing the registers and data FIFOs in the controller.
-+ * Some of the data access functions provide encapsulation of several
-+ * operations required to perform a task, such as writing multiple
-+ * registers to start a transfer. Finally, the CIL performs basic
-+ * services that are not specific to either the host or device modes
-+ * of operation. These services include management of the OTG Host
-+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
-+ * Diagnostic API is also provided to allow testing of the controller
-+ * hardware.
-+ *
-+ * The Core Interface Layer has the following requirements:
-+ * - Provides basic controller operations.
-+ * - Minimal use of OS services.
-+ * - The OS services used will be abstracted by using inline functions
-+ *	 or macros.
-+ *
-+ */
-+
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+
-+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * This function is called to initialize the DWC_otg CSR data
-+ * structures. The register addresses in the device and host
-+ * structures are initialized from the base address supplied by the
-+ * caller. The calling function must make the OS calls to get the
-+ * base address of the DWC_otg controller registers. The core_params
-+ * argument holds the parameters that specify how the core should be
-+ * configured.
-+ *
-+ * @param reg_base_addr Base address of DWC_otg core registers
-+ *
-+ */
-+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
-+{
-+	dwc_otg_core_if_t *core_if = 0;
-+	dwc_otg_dev_if_t *dev_if = 0;
-+	dwc_otg_host_if_t *host_if = 0;
-+	uint8_t *reg_base = (uint8_t *) reg_base_addr;
-+	int i = 0;
-+
-+	DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
-+
-+	core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
-+
-+	if (core_if == NULL) {
-+		DWC_DEBUGPL(DBG_CIL,
-+			    "Allocation of dwc_otg_core_if_t failed\n");
-+		return 0;
-+	}
-+	core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
-+
-+	/*
-+	 * Allocate the Device Mode structures.
-+	 */
-+	dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
-+
-+	if (dev_if == NULL) {
-+		DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
-+		DWC_FREE(core_if);
-+		return 0;
-+	}
-+
-+	dev_if->dev_global_regs =
-+	    (dwc_otg_device_global_regs_t *) (reg_base +
-+					      DWC_DEV_GLOBAL_REG_OFFSET);
-+
-+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+		dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
-+		    (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
-+		     (i * DWC_EP_REG_OFFSET));
-+
-+		dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
-+		    (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
-+		     (i * DWC_EP_REG_OFFSET));
-+		DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
-+			    i, &dev_if->in_ep_regs[i]->diepctl);
-+		DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
-+			    i, &dev_if->out_ep_regs[i]->doepctl);
-+	}
-+
-+	dev_if->speed = 0;	// unknown
-+
-+	core_if->dev_if = dev_if;
-+
-+	/*
-+	 * Allocate the Host Mode structures.
-+	 */
-+	host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
-+
-+	if (host_if == NULL) {
-+		DWC_DEBUGPL(DBG_CIL,
-+			    "Allocation of dwc_otg_host_if_t failed\n");
-+		DWC_FREE(dev_if);
-+		DWC_FREE(core_if);
-+		return 0;
-+	}
-+
-+	host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
-+	    (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
-+
-+	host_if->hprt0 =
-+	    (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
-+
-+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+		host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
-+		    (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
-+		     (i * DWC_OTG_CHAN_REGS_OFFSET));
-+		DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
-+			    i, &host_if->hc_regs[i]->hcchar);
-+	}
-+
-+	host_if->num_host_channels = MAX_EPS_CHANNELS;
-+	core_if->host_if = host_if;
-+
-+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+		core_if->data_fifo[i] =
-+		    (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
-+				  (i * DWC_OTG_DATA_FIFO_SIZE));
-+		DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
-+			    i, (unsigned long)core_if->data_fifo[i]);
-+	}
-+
-+	core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
-+
-+	/* Initiate lx_state to L3 disconnected state */
-+	core_if->lx_state = DWC_OTG_L3;
-+	/*
-+	 * Store the contents of the hardware configuration registers here for
-+	 * easy access later.
-+	 */
-+	core_if->hwcfg1.d32 =
-+	    DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
-+	core_if->hwcfg2.d32 =
-+	    DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
-+	core_if->hwcfg3.d32 =
-+	    DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
-+	core_if->hwcfg4.d32 =
-+	    DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
-+
-+	/* Force host mode to get HPTXFSIZ exact power on value */
-+	{
-+		gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+		gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+		gusbcfg.b.force_host_mode = 1;
-+		DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+		dwc_mdelay(100);
-+		core_if->hptxfsiz.d32 =
-+		DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+		gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+		gusbcfg.b.force_host_mode = 1;
-+		DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+		dwc_mdelay(100);
-+	}
-+
-+	DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
-+	DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
-+	DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
-+	DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
-+
-+	core_if->hcfg.d32 =
-+	    DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+	core_if->dcfg.d32 =
-+	    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+
-+	DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
-+	DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
-+
-+	DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
-+	DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
-+	DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
-+	DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
-+		    core_if->hwcfg2.b.num_host_chan);
-+	DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
-+		    core_if->hwcfg2.b.nonperio_tx_q_depth);
-+	DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
-+		    core_if->hwcfg2.b.host_perio_tx_q_depth);
-+	DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
-+		    core_if->hwcfg2.b.dev_token_q_depth);
-+
-+	DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
-+		    core_if->hwcfg3.b.dfifo_depth);
-+	DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
-+		    core_if->hwcfg3.b.xfer_size_cntr_width);
-+
-+	/*
-+	 * Set the SRP sucess bit for FS-I2c
-+	 */
-+	core_if->srp_success = 0;
-+	core_if->srp_timer_started = 0;
-+
-+	/*
-+	 * Create new workqueue and init works
-+	 */
-+	core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
-+	if (core_if->wq_otg == 0) {
-+		DWC_WARN("DWC_WORKQ_ALLOC failed\n");
-+		DWC_FREE(host_if);
-+		DWC_FREE(dev_if);
-+		DWC_FREE(core_if);
-+		return 0;
-+	}
-+
-+	core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
-+
-+	DWC_PRINTF("Core Release: %x.%x%x%x\n",
-+		   (core_if->snpsid >> 12 & 0xF),
-+		   (core_if->snpsid >> 8 & 0xF),
-+		   (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
-+
-+	core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
-+					     w_wakeup_detected, core_if);
-+	if (core_if->wkp_timer == 0) {
-+		DWC_WARN("DWC_TIMER_ALLOC failed\n");
-+		DWC_FREE(host_if);
-+		DWC_FREE(dev_if);
-+		DWC_WORKQ_FREE(core_if->wq_otg);
-+		DWC_FREE(core_if);
-+		return 0;
-+	}
-+
-+	if (dwc_otg_setup_params(core_if)) {
-+		DWC_WARN("Error while setting core params\n");
-+	}
-+
-+	core_if->hibernation_suspend = 0;
-+
-+	/** ADP initialization */
-+	dwc_otg_adp_init(core_if);
-+
-+	return core_if;
-+}
-+
-+/**
-+ * This function frees the structures allocated by dwc_otg_cil_init().
-+ *
-+ * @param core_if The core interface pointer returned from
-+ * 		  dwc_otg_cil_init().
-+ *
-+ */
-+void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
-+{
-+	dctl_data_t dctl = {.d32 = 0 };
-+	DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
-+
-+	/* Disable all interrupts */
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
-+
-+	dctl.b.sftdiscon = 1;
-+	if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
-+				 dctl.d32);
-+	}
-+
-+	if (core_if->wq_otg) {
-+		DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
-+		DWC_WORKQ_FREE(core_if->wq_otg);
-+	}
-+	if (core_if->dev_if) {
-+		DWC_FREE(core_if->dev_if);
-+	}
-+	if (core_if->host_if) {
-+		DWC_FREE(core_if->host_if);
-+	}
-+
-+	/** Remove ADP Stuff  */
-+	dwc_otg_adp_remove(core_if);
-+	if (core_if->core_params) {
-+		DWC_FREE(core_if->core_params);
-+	}
-+	if (core_if->wkp_timer) {
-+		DWC_TIMER_FREE(core_if->wkp_timer);
-+	}
-+	if (core_if->srp_timer) {
-+		DWC_TIMER_FREE(core_if->srp_timer);
-+	}
-+	DWC_FREE(core_if);
-+}
-+
-+/**
-+ * This function enables the controller's Global Interrupt in the AHB Config
-+ * register.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+	gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+	ahbcfg.b.glblintrmsk = 1;	/* Enable interrupts */
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
-+}
-+
-+/**
-+ * This function disables the controller's Global Interrupt in the AHB Config
-+ * register.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+	gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+	ahbcfg.b.glblintrmsk = 1;	/* Disable interrupts */
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
-+}
-+
-+/**
-+ * This function initializes the commmon interrupts, used in both
-+ * device and host modes.
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ *
-+ */
-+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	/* Clear any pending OTG Interrupts */
-+	DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
-+
-+	/* Clear any pending interrupts */
-+	DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/*
-+	 * Enable the interrupts in the GINTMSK.
-+	 */
-+	intr_mask.b.modemismatch = 1;
-+	intr_mask.b.otgintr = 1;
-+
-+	if (!core_if->dma_enable) {
-+		intr_mask.b.rxstsqlvl = 1;
-+	}
-+
-+	intr_mask.b.conidstschng = 1;
-+	intr_mask.b.wkupintr = 1;
-+	intr_mask.b.disconnect = 0;
-+	intr_mask.b.usbsuspend = 1;
-+	intr_mask.b.sessreqintr = 1;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	if (core_if->core_params->lpm_enable) {
-+		intr_mask.b.lpmtranrcvd = 1;
-+	}
-+#endif
-+	DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
-+}
-+
-+/*
-+ * The restore operation is modified to support Synopsys Emulated Powerdown and
-+ * Hibernation. This function is for exiting from Device mode hibernation by
-+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
-+ * @param reset - indicates whether resume is initiated by Reset.
-+ */
-+int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+				       int rem_wakeup, int reset)
-+{
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+	dctl_data_t dctl = {.d32 = 0 };
-+
-+	int timeout = 2000;
-+
-+	if (!core_if->hibernation_suspend) {
-+		DWC_PRINTF("Already exited from Hibernation\n");
-+		return 1;
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
-+	/* Switch-on voltage to the core */
-+	gpwrdn.b.pwrdnswtch = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Reset core */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Assert Restore signal */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.restore = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+	dwc_udelay(10);
-+
-+	/* Disable power clamps */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnclmp = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	if (rem_wakeup) {
-+		dwc_udelay(70);
-+	}
-+
-+	/* Deassert Reset core */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+	dwc_udelay(10);
-+
-+	/* Disable PMU interrupt */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuintsel = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	/* Mask interrupts from gpwrdn */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.connect_det_msk = 1;
-+	gpwrdn.b.srp_det_msk = 1;
-+	gpwrdn.b.disconn_det_msk = 1;
-+	gpwrdn.b.rst_det_msk = 1;
-+	gpwrdn.b.lnstchng_msk = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	/* Indicates that we are going out from hibernation */
-+	core_if->hibernation_suspend = 0;
-+
-+	/*
-+	 * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
-+	 * indicates restore from remote_wakeup
-+	 */
-+	restore_essential_regs(core_if, rem_wakeup, 0);
-+
-+	/*
-+	 * Wait a little for seeing new value of variable hibernation_suspend if
-+	 * Restore done interrupt received before polling
-+	 */
-+	dwc_udelay(10);
-+
-+	if (core_if->hibernation_suspend == 0) {
-+		/*
-+		 * Wait For Restore_done Interrupt. This mechanism of polling the
-+		 * interrupt is introduced to avoid any possible race conditions
-+		 */
-+		do {
-+			gintsts_data_t gintsts;
-+			gintsts.d32 =
-+			    DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+			if (gintsts.b.restoredone) {
-+				gintsts.d32 = 0;
-+				gintsts.b.restoredone = 1;
-+				DWC_WRITE_REG32(&core_if->core_global_regs->
-+						gintsts, gintsts.d32);
-+				DWC_PRINTF("Restore Done Interrupt seen\n");
-+				break;
-+			}
-+			dwc_udelay(10);
-+		} while (--timeout);
-+		if (!timeout) {
-+			DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
-+		}
-+	}
-+	/* Clear all pending interupts */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/* De-assert Restore */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.restore = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	if (!rem_wakeup) {
-+		pcgcctl.d32 = 0;
-+		pcgcctl.b.rstpdwnmodule = 1;
-+		DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+	}
-+
-+	/* Restore GUSBCFG and DCFG */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+			core_if->gr_backup->gusbcfg_local);
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+			core_if->dr_backup->dcfg);
-+
-+	/* De-assert Wakeup Logic */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuactv = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	if (!rem_wakeup) {
-+		/* Set Device programming done bit */
-+		dctl.b.pwronprgdone = 1;
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+	} else {
-+		/* Start Remote Wakeup Signaling */
-+		dctl.d32 = core_if->dr_backup->dctl;
-+		dctl.b.rmtwkupsig = 1;
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+	}
-+
-+	dwc_mdelay(2);
-+	/* Clear all pending interupts */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/* Restore global registers */
-+	dwc_otg_restore_global_regs(core_if);
-+	/* Restore device global registers */
-+	dwc_otg_restore_dev_regs(core_if, rem_wakeup);
-+
-+	if (rem_wakeup) {
-+		dwc_mdelay(7);
-+		dctl.d32 = 0;
-+		dctl.b.rmtwkupsig = 1;
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+	}
-+
-+	core_if->hibernation_suspend = 0;
-+	/* The core will be in ON STATE */
-+	core_if->lx_state = DWC_OTG_L0;
-+	DWC_PRINTF("Hibernation recovery completes here\n");
-+
-+	return 1;
-+}
-+
-+/*
-+ * The restore operation is modified to support Synopsys Emulated Powerdown and
-+ * Hibernation. This function is for exiting from Host mode hibernation by
-+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
-+ * @param reset - indicates whether resume is initiated by Reset.
-+ */
-+int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
-+				     int rem_wakeup, int reset)
-+{
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+	int timeout = 2000;
-+
-+	DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
-+	/* Switch-on voltage to the core */
-+	gpwrdn.b.pwrdnswtch = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Reset core */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Assert Restore signal */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.restore = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+	dwc_udelay(10);
-+
-+	/* Disable power clamps */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnclmp = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	if (!rem_wakeup) {
-+		dwc_udelay(50);
-+	}
-+
-+	/* Deassert Reset core */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+	dwc_udelay(10);
-+
-+	/* Disable PMU interrupt */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuintsel = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.connect_det_msk = 1;
-+	gpwrdn.b.srp_det_msk = 1;
-+	gpwrdn.b.disconn_det_msk = 1;
-+	gpwrdn.b.rst_det_msk = 1;
-+	gpwrdn.b.lnstchng_msk = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	/* Indicates that we are going out from hibernation */
-+	core_if->hibernation_suspend = 0;
-+
-+	/* Set Restore Essential Regs bit in PCGCCTL register */
-+	restore_essential_regs(core_if, rem_wakeup, 1);
-+
-+	/* Wait a little for seeing new value of variable hibernation_suspend if
-+	 * Restore done interrupt received before polling */
-+	dwc_udelay(10);
-+
-+	if (core_if->hibernation_suspend == 0) {
-+		/* Wait For Restore_done Interrupt. This mechanism of polling the
-+		 * interrupt is introduced to avoid any possible race conditions
-+		 */
-+		do {
-+			gintsts_data_t gintsts;
-+			gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+			if (gintsts.b.restoredone) {
-+				gintsts.d32 = 0;
-+				gintsts.b.restoredone = 1;
-+			DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+				DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
-+				break;
-+			}
-+			dwc_udelay(10);
-+		} while (--timeout);
-+		if (!timeout) {
-+			DWC_WARN("Restore Done interrupt wasn't generated\n");
-+		}
-+	}
-+
-+	/* Set the flag's value to 0 again after receiving restore done interrupt */
-+	core_if->hibernation_suspend = 0;
-+
-+	/* This step is not described in functional spec but if not wait for this
-+	 * delay, mismatch interrupts occurred because just after restore core is
-+	 * in Device mode(gintsts.curmode == 0) */
-+	dwc_mdelay(100);
-+
-+	/* Clear all pending interrupts */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/* De-assert Restore */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.restore = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Restore GUSBCFG and HCFG */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+			core_if->gr_backup->gusbcfg_local);
-+	DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
-+			core_if->hr_backup->hcfg_local);
-+
-+	/* De-assert Wakeup Logic */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuactv = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Start the Resume operation by programming HPRT0 */
-+	hprt0.d32 = core_if->hr_backup->hprt0_local;
-+	hprt0.b.prtpwr = 1;
-+	hprt0.b.prtena = 0;
-+	hprt0.b.prtsusp = 0;
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+	DWC_PRINTF("Resume Starts Now\n");
-+	if (!reset) {		// Indicates it is Resume Operation
-+		hprt0.d32 = core_if->hr_backup->hprt0_local;
-+		hprt0.b.prtres = 1;
-+		hprt0.b.prtpwr = 1;
-+		hprt0.b.prtena = 0;
-+		hprt0.b.prtsusp = 0;
-+		DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+		if (!rem_wakeup)
-+			hprt0.b.prtres = 0;
-+		/* Wait for Resume time and then program HPRT again */
-+		dwc_mdelay(100);
-+		DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+	} else {		// Indicates it is Reset Operation
-+		hprt0.d32 = core_if->hr_backup->hprt0_local;
-+		hprt0.b.prtrst = 1;
-+		hprt0.b.prtpwr = 1;
-+		hprt0.b.prtena = 0;
-+		hprt0.b.prtsusp = 0;
-+		DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+		/* Wait for Reset time and then program HPRT again */
-+		dwc_mdelay(60);
-+		hprt0.b.prtrst = 0;
-+		DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+	}
-+	/* Clear all interrupt status */
-+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+	hprt0.b.prtconndet = 1;
-+	hprt0.b.prtenchng = 1;
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+	/* Clear all pending interupts */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/* Restore global registers */
-+	dwc_otg_restore_global_regs(core_if);
-+	/* Restore host global registers */
-+	dwc_otg_restore_host_regs(core_if, reset);
-+
-+	/* The core will be in ON STATE */
-+	core_if->lx_state = DWC_OTG_L0;
-+	DWC_PRINTF("Hibernation recovery is complete here\n");
-+	return 0;
-+}
-+
-+/** Saves some register values into system memory. */
-+int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
-+{
-+	struct dwc_otg_global_regs_backup *gr;
-+	int i;
-+
-+	gr = core_if->gr_backup;
-+	if (!gr) {
-+		gr = DWC_ALLOC(sizeof(*gr));
-+		if (!gr) {
-+			return -DWC_E_NO_MEMORY;
-+		}
-+		core_if->gr_backup = gr;
-+	}
-+
-+	gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+	gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+	gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
-+	gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+	gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+	gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
-+	gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+#endif
-+	gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
-+	gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
-+	gr->gdfifocfg_local =
-+	    DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
-+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+		gr->dtxfsiz_local[i] =
-+		    DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
-+	}
-+
-+	DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
-+	DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl   = %08x\n", gr->gotgctl_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg   = %08x\n", gr->gahbcfg_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg   = %08x\n", gr->gusbcfg_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz   = %08x\n", gr->grxfsiz_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
-+		    gr->gnptxfsiz_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz  = %08x\n",
-+		    gr->hptxfsiz_local);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg   = %08x\n", gr->glpmcfg_local);
-+#endif
-+	DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl   = %08x\n", gr->gi2cctl_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl   = %08x\n", gr->pcgcctl_local);
-+	DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg   = %08x\n",gr->gdfifocfg_local);
-+
-+	return 0;
-+}
-+
-+/** Saves GINTMSK register before setting the msk bits. */
-+int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
-+{
-+	struct dwc_otg_global_regs_backup *gr;
-+
-+	gr = core_if->gr_backup;
-+	if (!gr) {
-+		gr = DWC_ALLOC(sizeof(*gr));
-+		if (!gr) {
-+			return -DWC_E_NO_MEMORY;
-+		}
-+		core_if->gr_backup = gr;
-+	}
-+
-+	gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+	DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
-+	DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
-+
-+	return 0;
-+}
-+
-+int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
-+{
-+	struct dwc_otg_dev_regs_backup *dr;
-+	int i;
-+
-+	dr = core_if->dr_backup;
-+	if (!dr) {
-+		dr = DWC_ALLOC(sizeof(*dr));
-+		if (!dr) {
-+			return -DWC_E_NO_MEMORY;
-+		}
-+		core_if->dr_backup = dr;
-+	}
-+
-+	dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+	dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+	dr->daintmsk =
-+	    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+	dr->diepmsk =
-+	    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
-+	dr->doepmsk =
-+	    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
-+
-+	for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+		dr->diepctl[i] =
-+		    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
-+		dr->dieptsiz[i] =
-+		    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
-+		dr->diepdma[i] =
-+		    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
-+	}
-+
-+	DWC_DEBUGPL(DBG_ANY,
-+		    "=============Backing Host registers==============\n");
-+	DWC_DEBUGPL(DBG_ANY, "Backed up dcfg            = %08x\n", dr->dcfg);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up dctl        = %08x\n", dr->dctl);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk            = %08x\n",
-+		    dr->daintmsk);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk        = %08x\n", dr->diepmsk);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk        = %08x\n", dr->doepmsk);
-+	for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+		DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d]        = %08x\n", i,
-+			    dr->diepctl[i]);
-+		DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d]        = %08x\n",
-+			    i, dr->dieptsiz[i]);
-+		DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d]        = %08x\n", i,
-+			    dr->diepdma[i]);
-+	}
-+
-+	return 0;
-+}
-+
-+int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
-+{
-+	struct dwc_otg_host_regs_backup *hr;
-+	int i;
-+
-+	hr = core_if->hr_backup;
-+	if (!hr) {
-+		hr = DWC_ALLOC(sizeof(*hr));
-+		if (!hr) {
-+			return -DWC_E_NO_MEMORY;
-+		}
-+		core_if->hr_backup = hr;
-+	}
-+
-+	hr->hcfg_local =
-+	    DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+	hr->haintmsk_local =
-+	    DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
-+	for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+		hr->hcintmsk_local[i] =
-+		    DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
-+	}
-+	hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
-+	hr->hfir_local =
-+	    DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+
-+	DWC_DEBUGPL(DBG_ANY,
-+		    "=============Backing Host registers===============\n");
-+	DWC_DEBUGPL(DBG_ANY, "Backed up hcfg		= %08x\n",
-+		    hr->hcfg_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
-+	for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+		DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
-+			    hr->hcintmsk_local[i]);
-+	}
-+	DWC_DEBUGPL(DBG_ANY, "Backed up hprt0           = %08x\n",
-+		    hr->hprt0_local);
-+	DWC_DEBUGPL(DBG_ANY, "Backed up hfir           = %08x\n",
-+		    hr->hfir_local);
-+
-+	return 0;
-+}
-+
-+int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
-+{
-+	struct dwc_otg_global_regs_backup *gr;
-+	int i;
-+
-+	gr = core_if->gr_backup;
-+	if (!gr) {
-+		return -DWC_E_INVALID;
-+	}
-+
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
-+			gr->gnptxfsiz_local);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
-+			gr->hptxfsiz_local);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
-+			gr->gdfifocfg_local);
-+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+		DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
-+				gr->dtxfsiz_local[i]);
-+	}
-+
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
-+			(gr->gahbcfg_local));
-+	return 0;
-+}
-+
-+int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
-+{
-+	struct dwc_otg_dev_regs_backup *dr;
-+	int i;
-+
-+	dr = core_if->dr_backup;
-+
-+	if (!dr) {
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (!rem_wakeup) {
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+				dr->dctl);
-+	}
-+
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
-+
-+	for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+		DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
-+		DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
-+		DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
-+	}
-+
-+	return 0;
-+}
-+
-+int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
-+{
-+	struct dwc_otg_host_regs_backup *hr;
-+	int i;
-+	hr = core_if->hr_backup;
-+
-+	if (!hr) {
-+		return -DWC_E_INVALID;
-+	}
-+
-+	DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
-+	//if (!reset)
-+	//{
-+	//      DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
-+	//}
-+
-+	DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
-+			hr->haintmsk_local);
-+	for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
-+		DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
-+				hr->hcintmsk_local[i]);
-+	}
-+
-+	return 0;
-+}
-+
-+int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
-+{
-+	struct dwc_otg_global_regs_backup *gr;
-+
-+	gr = core_if->gr_backup;
-+
-+	/* Restore values for LPM and I2C */
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
-+#endif
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
-+
-+	return 0;
-+}
-+
-+int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
-+{
-+	struct dwc_otg_global_regs_backup *gr;
-+	pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+	gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+	gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+	gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+	/* Restore LPM and I2C registers */
-+	restore_lpm_i2c_regs(core_if);
-+
-+	/* Set PCGCCTL to 0 */
-+	DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
-+
-+	gr = core_if->gr_backup;
-+	/* Load restore values for [31:14] bits */
-+	DWC_WRITE_REG32(core_if->pcgcctl,
-+			((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
-+
-+	/* Umnask global Interrupt in GAHBCFG and restore it */
-+	gahbcfg.d32 = gr->gahbcfg_local;
-+	gahbcfg.b.glblintrmsk = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
-+
-+	/* Clear all pending interupts */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/* Unmask restore done interrupt */
-+	gintmsk.b.restoredone = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
-+
-+	/* Restore GUSBCFG and HCFG/DCFG */
-+	gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
-+
-+	if (is_host) {
-+		hcfg_data_t hcfg = {.d32 = 0 };
-+		hcfg.d32 = core_if->hr_backup->hcfg_local;
-+		DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
-+				hcfg.d32);
-+
-+		/* Load restore values for [31:14] bits */
-+		pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+		pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+
-+		if (rmode)
-+			pcgcctl.b.restoremode = 1;
-+		DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+		dwc_udelay(10);
-+
-+		/* Load restore values for [31:14] bits and set EssRegRestored bit */
-+		pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
-+		pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+		pcgcctl.b.ess_reg_restored = 1;
-+		if (rmode)
-+			pcgcctl.b.restoremode = 1;
-+		DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+	} else {
-+		dcfg_data_t dcfg = {.d32 = 0 };
-+		dcfg.d32 = core_if->dr_backup->dcfg;
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+		/* Load restore values for [31:14] bits */
-+		pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+		pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+		if (!rmode) {
-+			pcgcctl.d32 |= 0x208;
-+		}
-+		DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+		dwc_udelay(10);
-+
-+		/* Load restore values for [31:14] bits */
-+		pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
-+		pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
-+		pcgcctl.b.ess_reg_restored = 1;
-+		if (!rmode)
-+			pcgcctl.d32 |= 0x208;
-+		DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
-+ * type.
-+ */
-+static void init_fslspclksel(dwc_otg_core_if_t * core_if)
-+{
-+	uint32_t val;
-+	hcfg_data_t hcfg;
-+
-+	if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+	     (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+	     (core_if->core_params->ulpi_fs_ls)) ||
-+	    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+		/* Full speed PHY */
-+		val = DWC_HCFG_48_MHZ;
-+	} else {
-+		/* High speed PHY running at full speed or high speed */
-+		val = DWC_HCFG_30_60_MHZ;
-+	}
-+
-+	DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
-+	hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+	hcfg.b.fslspclksel = val;
-+	DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+/**
-+ * Initializes the DevSpd field of the DCFG register depending on the PHY type
-+ * and the enumeration speed of the device.
-+ */
-+static void init_devspd(dwc_otg_core_if_t * core_if)
-+{
-+	uint32_t val;
-+	dcfg_data_t dcfg;
-+
-+	if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+	     (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+	     (core_if->core_params->ulpi_fs_ls)) ||
-+	    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+		/* Full speed PHY */
-+		val = 0x3;
-+	} else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
-+		/* High speed PHY running at full speed */
-+		val = 0x1;
-+	} else {
-+		/* High speed PHY running at high speed */
-+		val = 0x0;
-+	}
-+
-+	DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
-+
-+	dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+	dcfg.b.devspd = val;
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+}
-+
-+/**
-+ * This function calculates the number of IN EPS
-+ * using GHWCFG1 and GHWCFG2 registers values
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ */
-+static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
-+{
-+	uint32_t num_in_eps = 0;
-+	uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
-+	uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
-+	uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
-+	int i;
-+
-+	for (i = 0; i < num_eps; ++i) {
-+		if (!(hwcfg1 & 0x1))
-+			num_in_eps++;
-+
-+		hwcfg1 >>= 2;
-+	}
-+
-+	if (core_if->hwcfg4.b.ded_fifo_en) {
-+		num_in_eps =
-+		    (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
-+	}
-+
-+	return num_in_eps;
-+}
-+
-+/**
-+ * This function calculates the number of OUT EPS
-+ * using GHWCFG1 and GHWCFG2 registers values
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ */
-+static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
-+{
-+	uint32_t num_out_eps = 0;
-+	uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
-+	uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
-+	int i;
-+
-+	for (i = 0; i < num_eps; ++i) {
-+		if (!(hwcfg1 & 0x1))
-+			num_out_eps++;
-+
-+		hwcfg1 >>= 2;
-+	}
-+	return num_out_eps;
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers and
-+ * prepares the core for device mode or host mode operation.
-+ *
-+ * @param core_if Programming view of the DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
-+{
-+	int i = 0;
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	gahbcfg_data_t ahbcfg = {.d32 = 0 };
-+	gusbcfg_data_t usbcfg = {.d32 = 0 };
-+	gi2cctl_data_t i2cctl = {.d32 = 0 };
-+
-+	DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
-+                    core_if, global_regs);
-+
-+	/* Common Initialization */
-+	usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+	/* Program the ULPI External VBUS bit if needed */
-+	usbcfg.b.ulpi_ext_vbus_drv =
-+	    (core_if->core_params->phy_ulpi_ext_vbus ==
-+	     DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
-+
-+	/* Set external TS Dline pulsing */
-+	usbcfg.b.term_sel_dl_pulse =
-+	    (core_if->core_params->ts_dline == 1) ? 1 : 0;
-+	DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+	/* Reset the Controller */
-+	dwc_otg_core_reset(core_if);
-+
-+	core_if->adp_enable = core_if->core_params->adp_supp_enable;
-+	core_if->power_down = core_if->core_params->power_down;
-+	core_if->otg_sts = 0;
-+
-+	/* Initialize parameters from Hardware configuration registers. */
-+	dev_if->num_in_eps = calc_num_in_eps(core_if);
-+	dev_if->num_out_eps = calc_num_out_eps(core_if);
-+
-+	DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
-+		    core_if->hwcfg4.b.num_dev_perio_in_ep);
-+
-+	for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
-+		dev_if->perio_tx_fifo_size[i] =
-+		    DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
-+		DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
-+			    i, dev_if->perio_tx_fifo_size[i]);
-+	}
-+
-+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+		dev_if->tx_fifo_size[i] =
-+		    DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
-+		DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
-+			    i, dev_if->tx_fifo_size[i]);
-+	}
-+
-+	core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
-+	core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
-+	core_if->nperio_tx_fifo_size =
-+	    DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
-+
-+	DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
-+	DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
-+	DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
-+		    core_if->nperio_tx_fifo_size);
-+
-+	/* This programming sequence needs to happen in FS mode before any other
-+	 * programming occurs */
-+	if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
-+	    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
-+		/* If FS mode with FS PHY */
-+
-+		/* core_init() is now called on every switch so only call the
-+		 * following for the first time through. */
-+		if (!core_if->phy_init_done) {
-+			core_if->phy_init_done = 1;
-+			DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
-+			usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+			usbcfg.b.physel = 1;
-+			DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+			/* Reset after a PHY select */
-+			dwc_otg_core_reset(core_if);
-+		}
-+
-+		/* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
-+		 * do this on HNP Dev/Host mode switches (done in dev_init and
-+		 * host_init). */
-+		if (dwc_otg_is_host_mode(core_if)) {
-+			init_fslspclksel(core_if);
-+		} else {
-+			init_devspd(core_if);
-+		}
-+
-+		if (core_if->core_params->i2c_enable) {
-+			DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
-+			/* Program GUSBCFG.OtgUtmifsSel to I2C */
-+			usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+			usbcfg.b.otgutmifssel = 1;
-+			DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+			/* Program GI2CCTL.I2CEn */
-+			i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
-+			i2cctl.b.i2cdevaddr = 1;
-+			i2cctl.b.i2cen = 0;
-+			DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
-+			i2cctl.b.i2cen = 1;
-+			DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
-+		}
-+
-+	} /* endif speed == DWC_SPEED_PARAM_FULL */
-+	else {
-+		/* High speed PHY. */
-+		if (!core_if->phy_init_done) {
-+			core_if->phy_init_done = 1;
-+			/* HS PHY parameters.  These parameters are preserved
-+			 * during soft reset so only program the first time.  Do
-+			 * a soft reset immediately after setting phyif.  */
-+
-+			if (core_if->core_params->phy_type == 2) {
-+				/* ULPI interface */
-+				usbcfg.b.ulpi_utmi_sel = 1;
-+				usbcfg.b.phyif = 0;
-+				usbcfg.b.ddrsel =
-+				    core_if->core_params->phy_ulpi_ddr;
-+			} else if (core_if->core_params->phy_type == 1) {
-+				/* UTMI+ interface */
-+				usbcfg.b.ulpi_utmi_sel = 0;
-+				if (core_if->core_params->phy_utmi_width == 16) {
-+					usbcfg.b.phyif = 1;
-+
-+				} else {
-+					usbcfg.b.phyif = 0;
-+				}
-+			} else {
-+				DWC_ERROR("FS PHY TYPE\n");
-+			}
-+			DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+			/* Reset after setting the PHY parameters */
-+			dwc_otg_core_reset(core_if);
-+		}
-+	}
-+
-+	if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+	    (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+	    (core_if->core_params->ulpi_fs_ls)) {
-+		DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
-+		usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+		usbcfg.b.ulpi_fsls = 1;
-+		usbcfg.b.ulpi_clk_sus_m = 1;
-+		DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+	} else {
-+		usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+		usbcfg.b.ulpi_fsls = 0;
-+		usbcfg.b.ulpi_clk_sus_m = 0;
-+		DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+	}
-+
-+	/* Program the GAHBCFG Register. */
-+	switch (core_if->hwcfg2.b.architecture) {
-+
-+	case DWC_SLAVE_ONLY_ARCH:
-+		DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
-+		ahbcfg.b.nptxfemplvl_txfemplvl =
-+		    DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-+		ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
-+		core_if->dma_enable = 0;
-+		core_if->dma_desc_enable = 0;
-+		break;
-+
-+	case DWC_EXT_DMA_ARCH:
-+		DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
-+		{
-+			uint8_t brst_sz = core_if->core_params->dma_burst_size;
-+			ahbcfg.b.hburstlen = 0;
-+			while (brst_sz > 1) {
-+				ahbcfg.b.hburstlen++;
-+				brst_sz >>= 1;
-+			}
-+		}
-+		core_if->dma_enable = (core_if->core_params->dma_enable != 0);
-+		core_if->dma_desc_enable =
-+		    (core_if->core_params->dma_desc_enable != 0);
-+		break;
-+
-+	case DWC_INT_DMA_ARCH:
-+		DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
-+		/* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
-+		  Host mode ISOC in issue fix - vahrama */
-+		/* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */
-+		ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;
-+		core_if->dma_enable = (core_if->core_params->dma_enable != 0);
-+		core_if->dma_desc_enable =
-+		    (core_if->core_params->dma_desc_enable != 0);
-+		break;
-+
-+	}
-+	if (core_if->dma_enable) {
-+		if (core_if->dma_desc_enable) {
-+			DWC_PRINTF("Using Descriptor DMA mode\n");
-+		} else {
-+			DWC_PRINTF("Using Buffer DMA mode\n");
-+
-+		}
-+	} else {
-+		DWC_PRINTF("Using Slave mode\n");
-+		core_if->dma_desc_enable = 0;
-+	}
-+
-+	if (core_if->core_params->ahb_single) {
-+		ahbcfg.b.ahbsingle = 1;
-+	}
-+
-+	ahbcfg.b.dmaenable = core_if->dma_enable;
-+	DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
-+
-+	core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
-+
-+	core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
-+	core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
-+	DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
-+		   ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
-+	DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
-+		   ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
-+
-+	/*
-+	 * Program the GUSBCFG register.
-+	 */
-+	usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+	switch (core_if->hwcfg2.b.op_mode) {
-+	case DWC_MODE_HNP_SRP_CAPABLE:
-+		usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
-+				   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
-+		usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+				   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+		break;
-+
-+	case DWC_MODE_SRP_ONLY_CAPABLE:
-+		usbcfg.b.hnpcap = 0;
-+		usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+				   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+		break;
-+
-+	case DWC_MODE_NO_HNP_SRP_CAPABLE:
-+		usbcfg.b.hnpcap = 0;
-+		usbcfg.b.srpcap = 0;
-+		break;
-+
-+	case DWC_MODE_SRP_CAPABLE_DEVICE:
-+		usbcfg.b.hnpcap = 0;
-+		usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+				   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+		break;
-+
-+	case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
-+		usbcfg.b.hnpcap = 0;
-+		usbcfg.b.srpcap = 0;
-+		break;
-+
-+	case DWC_MODE_SRP_CAPABLE_HOST:
-+		usbcfg.b.hnpcap = 0;
-+		usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
-+				   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+		break;
-+
-+	case DWC_MODE_NO_SRP_CAPABLE_HOST:
-+		usbcfg.b.hnpcap = 0;
-+		usbcfg.b.srpcap = 0;
-+		break;
-+	}
-+
-+	DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	if (core_if->core_params->lpm_enable) {
-+		glpmcfg_data_t lpmcfg = {.d32 = 0 };
-+
-+		/* To enable LPM support set lpm_cap_en bit */
-+		lpmcfg.b.lpm_cap_en = 1;
-+
-+		/* Make AppL1Res ACK */
-+		lpmcfg.b.appl_resp = 1;
-+
-+		/* Retry 3 times */
-+		lpmcfg.b.retry_count = 3;
-+
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
-+				 0, lpmcfg.d32);
-+
-+	}
-+#endif
-+	if (core_if->core_params->ic_usb_cap) {
-+		gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+		gusbcfg.b.ic_usb_cap = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
-+				 0, gusbcfg.d32);
-+	}
-+	{
-+		gotgctl_data_t gotgctl = {.d32 = 0 };
-+		gotgctl.b.otgver = core_if->core_params->otg_ver;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
-+				 gotgctl.d32);
-+		/* Set OTG version supported */
-+		core_if->otg_ver = core_if->core_params->otg_ver;
-+		DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
-+			   core_if->core_params->otg_ver, core_if->otg_ver);
-+	}
-+
-+
-+	/* Enable common interrupts */
-+	dwc_otg_enable_common_interrupts(core_if);
-+
-+	/* Do device or host intialization based on mode during PCD
-+	 * and HCD initialization  */
-+	if (dwc_otg_is_host_mode(core_if)) {
-+		DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
-+		core_if->op_state = A_HOST;
-+	} else {
-+		DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
-+		core_if->op_state = B_PERIPHERAL;
-+#ifdef DWC_DEVICE_ONLY
-+		dwc_otg_core_dev_init(core_if);
-+#endif
-+	}
-+}
-+
-+/**
-+ * This function enables the Device mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+
-+	DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
-+
-+	/* Disable all interrupts. */
-+	DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+	/* Clear any pending interrupts */
-+	DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/* Enable the common interrupts */
-+	dwc_otg_enable_common_interrupts(core_if);
-+
-+	/* Enable interrupts */
-+	intr_mask.b.usbreset = 1;
-+	intr_mask.b.enumdone = 1;
-+	/* Disable Disconnect interrupt in Device mode */
-+	intr_mask.b.disconnect = 0;
-+
-+	if (!core_if->multiproc_int_enable) {
-+		intr_mask.b.inepintr = 1;
-+		intr_mask.b.outepintr = 1;
-+	}
-+
-+	intr_mask.b.erlysuspend = 1;
-+
-+	if (core_if->en_multiple_tx_fifo == 0) {
-+		intr_mask.b.epmismatch = 1;
-+	}
-+
-+	//intr_mask.b.incomplisoout = 1;
-+	intr_mask.b.incomplisoin = 1;
-+
-+/* Enable the ignore frame number for ISOC xfers - MAS */
-+/* Disable to support high bandwith ISOC transfers - manukz */
-+#if 0
-+#ifdef DWC_UTE_PER_IO
-+	if (core_if->dma_enable) {
-+		if (core_if->dma_desc_enable) {
-+			dctl_data_t dctl1 = {.d32 = 0 };
-+			dctl1.b.ifrmnum = 1;
-+			DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+					 dctl, 0, dctl1.d32);
-+			DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
-+				  DWC_READ_REG32(&core_if->dev_if->
-+						 dev_global_regs->dctl));
-+		}
-+	}
-+#endif
-+#endif
-+#ifdef DWC_EN_ISOC
-+	if (core_if->dma_enable) {
-+		if (core_if->dma_desc_enable == 0) {
-+			if (core_if->pti_enh_enable) {
-+				dctl_data_t dctl = {.d32 = 0 };
-+				dctl.b.ifrmnum = 1;
-+				DWC_MODIFY_REG32(&core_if->
-+						 dev_if->dev_global_regs->dctl,
-+						 0, dctl.d32);
-+			} else {
-+				intr_mask.b.incomplisoin = 1;
-+				intr_mask.b.incomplisoout = 1;
-+			}
-+		}
-+	} else {
-+		intr_mask.b.incomplisoin = 1;
-+		intr_mask.b.incomplisoout = 1;
-+	}
-+#endif /* DWC_EN_ISOC */
-+
-+	/** @todo NGS: Should this be a module parameter? */
-+#ifdef USE_PERIODIC_EP
-+	intr_mask.b.isooutdrop = 1;
-+	intr_mask.b.eopframe = 1;
-+	intr_mask.b.incomplisoin = 1;
-+	intr_mask.b.incomplisoout = 1;
-+#endif
-+
-+	DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+
-+	DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
-+		    DWC_READ_REG32(&global_regs->gintmsk));
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers for
-+ * device mode.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
-+{
-+	int i;
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	dwc_otg_core_params_t *params = core_if->core_params;
-+	dcfg_data_t dcfg = {.d32 = 0 };
-+	depctl_data_t diepctl = {.d32 = 0 };
-+	grstctl_t resetctl = {.d32 = 0 };
-+	uint32_t rx_fifo_size;
-+	fifosize_data_t nptxfifosize;
-+	fifosize_data_t txfifosize;
-+	dthrctl_data_t dthrctl;
-+	fifosize_data_t ptxfifosize;
-+	uint16_t rxfsiz, nptxfsiz;
-+	gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+	hwcfg3_data_t hwcfg3 = {.d32 = 0 };
-+
-+	/* Restart the Phy Clock */
-+	DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+
-+	/* Device configuration register */
-+	init_devspd(core_if);
-+	dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+	dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
-+	dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
-+	/* Enable Device OUT NAK in case of DDMA mode*/
-+	if (core_if->core_params->dev_out_nak) {
-+		dcfg.b.endevoutnak = 1;
-+	}
-+
-+	if (core_if->core_params->cont_on_bna) {
-+		dctl_data_t dctl = {.d32 = 0 };
-+		dctl.b.encontonbna = 1;
-+		DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+	}
-+
-+
-+	DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+	/* Configure data FIFO sizes */
-+	if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+		DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
-+			    core_if->total_fifo_size);
-+		DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
-+			    params->dev_rx_fifo_size);
-+		DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
-+			    params->dev_nperio_tx_fifo_size);
-+
-+		/* Rx FIFO */
-+		DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
-+			    DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+#ifdef DWC_UTE_CFI
-+		core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
-+		core_if->init_rxfsiz = params->dev_rx_fifo_size;
-+#endif
-+		rx_fifo_size = params->dev_rx_fifo_size;
-+		DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
-+
-+		DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
-+			    DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+		/** Set Periodic Tx FIFO Mask all bits 0 */
-+		core_if->p_tx_msk = 0;
-+
-+		/** Set Tx FIFO Mask all bits 0 */
-+		core_if->tx_msk = 0;
-+
-+		if (core_if->en_multiple_tx_fifo == 0) {
-+			/* Non-periodic Tx FIFO */
-+			DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+				    DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+			nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+			nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-+
-+			DWC_WRITE_REG32(&global_regs->gnptxfsiz,
-+					nptxfifosize.d32);
-+
-+			DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+				    DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+			/**@todo NGS: Fix Periodic FIFO Sizing! */
-+			/*
-+			 * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
-+			 * Indexes of the FIFO size module parameters in the
-+			 * dev_perio_tx_fifo_size array and the FIFO size registers in
-+			 * the dptxfsiz array run from 0 to 14.
-+			 */
-+			/** @todo Finish debug of this */
-+			ptxfifosize.b.startaddr =
-+			    nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+			for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
-+				ptxfifosize.b.depth =
-+				    params->dev_perio_tx_fifo_size[i];
-+				DWC_DEBUGPL(DBG_CIL,
-+					    "initial dtxfsiz[%d]=%08x\n", i,
-+					    DWC_READ_REG32(&global_regs->dtxfsiz
-+							   [i]));
-+				DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+						ptxfifosize.d32);
-+				DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
-+					    i,
-+					    DWC_READ_REG32(&global_regs->dtxfsiz
-+							   [i]));
-+				ptxfifosize.b.startaddr += ptxfifosize.b.depth;
-+			}
-+		} else {
-+			/*
-+			 * Tx FIFOs These FIFOs are numbered from 1 to 15.
-+			 * Indexes of the FIFO size module parameters in the
-+			 * dev_tx_fifo_size array and the FIFO size registers in
-+			 * the dtxfsiz array run from 0 to 14.
-+			 */
-+
-+			/* Non-periodic Tx FIFO */
-+			DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+				    DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+#ifdef DWC_UTE_CFI
-+			core_if->pwron_gnptxfsiz =
-+			    (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+			core_if->init_gnptxfsiz =
-+			    params->dev_nperio_tx_fifo_size;
-+#endif
-+			nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
-+			nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
-+
-+			DWC_WRITE_REG32(&global_regs->gnptxfsiz,
-+					nptxfifosize.d32);
-+
-+			DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+				    DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+			txfifosize.b.startaddr =
-+			    nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+
-+			for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
-+
-+				txfifosize.b.depth =
-+				    params->dev_tx_fifo_size[i];
-+
-+				DWC_DEBUGPL(DBG_CIL,
-+					    "initial dtxfsiz[%d]=%08x\n",
-+					    i,
-+					    DWC_READ_REG32(&global_regs->dtxfsiz
-+							   [i]));
-+
-+#ifdef DWC_UTE_CFI
-+				core_if->pwron_txfsiz[i] =
-+				    (DWC_READ_REG32
-+				     (&global_regs->dtxfsiz[i]) >> 16);
-+				core_if->init_txfsiz[i] =
-+				    params->dev_tx_fifo_size[i];
-+#endif
-+				DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
-+						txfifosize.d32);
-+
-+				DWC_DEBUGPL(DBG_CIL,
-+					    "new dtxfsiz[%d]=%08x\n",
-+					    i,
-+					    DWC_READ_REG32(&global_regs->dtxfsiz
-+							   [i]));
-+
-+				txfifosize.b.startaddr += txfifosize.b.depth;
-+			}
-+			if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+				/* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
-+				gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
-+				hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
-+				gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
-+				DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+				rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
-+				nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+				gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
-+				DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+			}
-+		}
-+
-+		/* Flush the FIFOs */
-+		dwc_otg_flush_tx_fifo(core_if, 0x10);	/* all Tx FIFOs */
-+		dwc_otg_flush_rx_fifo(core_if);
-+
-+		/* Flush the Learning Queue. */
-+		resetctl.b.intknqflsh = 1;
-+		DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+		if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
-+			core_if->start_predict = 0;
-+			for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
-+				core_if->nextep_seq[i] = 0xff;	// 0xff - EP not active
-+			}
-+			core_if->nextep_seq[0] = 0;
-+			core_if->first_in_nextep_seq = 0;
-+			diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+			diepctl.b.nextep = 0;
-+			DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+			/* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
-+			dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+			dcfg.b.epmscnt = 2;
-+			DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+			DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+				__func__, core_if->first_in_nextep_seq);
-+			for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+				DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
-+			}
-+			DWC_DEBUGPL(DBG_CILV,"\n");
-+		}
-+
-+		/* Clear all pending Device Interrupts */
-+		/** @todo - if the condition needed to be checked
-+		 *  or in any case all pending interrutps should be cleared?
-+	     */
-+		if (core_if->multiproc_int_enable) {
-+			for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
-+				DWC_WRITE_REG32(&dev_if->
-+						dev_global_regs->diepeachintmsk[i], 0);
-+			}
-+		}
-+
-+		for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+			DWC_WRITE_REG32(&dev_if->
-+					dev_global_regs->doepeachintmsk[i], 0);
-+		}
-+
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
-+	} else {
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
-+	}
-+
-+	for (i = 0; i <= dev_if->num_in_eps; i++) {
-+		depctl_data_t depctl;
-+		depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+		if (depctl.b.epena) {
-+			depctl.d32 = 0;
-+			depctl.b.epdis = 1;
-+			depctl.b.snak = 1;
-+		} else {
-+			depctl.d32 = 0;
-+		}
-+
-+		DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+
-+		DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
-+		DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
-+		DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
-+	}
-+
-+	for (i = 0; i <= dev_if->num_out_eps; i++) {
-+		depctl_data_t depctl;
-+		depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+		if (depctl.b.epena) {
-+			dctl_data_t dctl = {.d32 = 0 };
-+			gintmsk_data_t gintsts = {.d32 = 0 };
-+			doepint_data_t doepint = {.d32 = 0 };
-+			dctl.b.sgoutnak = 1;
-+			DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+			do {
-+				dwc_udelay(10);
-+				gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+			} while (!gintsts.b.goutnakeff);
-+			gintsts.d32 = 0;
-+			gintsts.b.goutnakeff = 1;
-+			DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+			depctl.d32 = 0;
-+			depctl.b.epdis = 1;
-+			depctl.b.snak = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
-+			do {
-+				dwc_udelay(10);
-+				doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+					out_ep_regs[i]->doepint);
-+			} while (!doepint.b.epdisabled);
-+
-+			doepint.b.epdisabled = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
-+
-+			dctl.d32 = 0;
-+			dctl.b.cgoutnak = 1;
-+			DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+		} else {
-+			depctl.d32 = 0;
-+		}
-+
-+		DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
-+
-+		DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
-+		DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
-+		DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
-+	}
-+
-+	if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
-+		dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
-+		dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
-+		dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
-+
-+		dev_if->rx_thr_length = params->rx_thr_length;
-+		dev_if->tx_thr_length = params->tx_thr_length;
-+
-+		dev_if->setup_desc_index = 0;
-+
-+		dthrctl.d32 = 0;
-+		dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
-+		dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
-+		dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
-+		dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
-+		dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
-+		dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
-+
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
-+				dthrctl.d32);
-+
-+		DWC_DEBUGPL(DBG_CIL,
-+			    "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
-+			    dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
-+			    dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
-+			    dthrctl.b.rx_thr_len);
-+
-+	}
-+
-+	dwc_otg_enable_device_interrupts(core_if);
-+
-+	{
-+		diepmsk_data_t msk = {.d32 = 0 };
-+		msk.b.txfifoundrn = 1;
-+		if (core_if->multiproc_int_enable) {
-+			DWC_MODIFY_REG32(&dev_if->dev_global_regs->
-+					 diepeachintmsk[0], msk.d32, msk.d32);
-+		} else {
-+			DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
-+					 msk.d32, msk.d32);
-+		}
-+	}
-+
-+	if (core_if->multiproc_int_enable) {
-+		/* Set NAK on Babble */
-+		dctl_data_t dctl = {.d32 = 0 };
-+		dctl.b.nakonbble = 1;
-+		DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+	}
-+
-+	if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
-+		dctl_data_t dctl = {.d32 = 0 };
-+		dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
-+		dctl.b.sftdiscon = 0;
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
-+	}
-+}
-+
-+/**
-+ * This function enables the Host mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
-+
-+	/* Disable all interrupts. */
-+	DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+	/* Clear any pending interrupts. */
-+	DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
-+
-+	/* Enable the common interrupts */
-+	dwc_otg_enable_common_interrupts(core_if);
-+
-+	/*
-+	 * Enable host mode interrupts without disturbing common
-+	 * interrupts.
-+	 */
-+
-+	intr_mask.b.disconnect = 1;
-+	intr_mask.b.portintr = 1;
-+	intr_mask.b.hcintr = 1;
-+
-+	DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+}
-+
-+/**
-+ * This function disables the Host Mode interrupts.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
-+
-+	/*
-+	 * Disable host mode interrupts without disturbing common
-+	 * interrupts.
-+	 */
-+	intr_mask.b.sofintr = 1;
-+	intr_mask.b.portintr = 1;
-+	intr_mask.b.hcintr = 1;
-+	intr_mask.b.ptxfempty = 1;
-+	intr_mask.b.nptxfempty = 1;
-+
-+	DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
-+}
-+
-+/**
-+ * This function initializes the DWC_otg controller registers for
-+ * host mode.
-+ *
-+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
-+ * request queues. Host channels are reset to ensure that they are ready for
-+ * performing transfers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ *
-+ */
-+void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	dwc_otg_host_if_t *host_if = core_if->host_if;
-+	dwc_otg_core_params_t *params = core_if->core_params;
-+	hprt0_data_t hprt0 = {.d32 = 0 };
-+	fifosize_data_t nptxfifosize;
-+	fifosize_data_t ptxfifosize;
-+	uint16_t rxfsiz, nptxfsiz, hptxfsiz;
-+	gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+	int i;
-+	hcchar_data_t hcchar;
-+	hcfg_data_t hcfg;
-+	hfir_data_t hfir;
-+	dwc_otg_hc_regs_t *hc_regs;
-+	int num_channels;
-+	gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+	DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
-+
-+	/* Restart the Phy Clock */
-+	DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+
-+	/* Initialize Host Configuration Register */
-+	init_fslspclksel(core_if);
-+	if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
-+		hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
-+		hcfg.b.fslssupp = 1;
-+		DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
-+
-+	}
-+
-+	/* This bit allows dynamic reloading of the HFIR register
-+	 * during runtime. This bit needs to be programmed during
-+	 * initial configuration and its value must not be changed
-+	 * during runtime.*/
-+	if (core_if->core_params->reload_ctl == 1) {
-+		hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
-+		hfir.b.hfirrldctrl = 1;
-+		DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
-+	}
-+
-+	if (core_if->core_params->dma_desc_enable) {
-+		uint8_t op_mode = core_if->hwcfg2.b.op_mode;
-+		if (!
-+		    (core_if->hwcfg4.b.desc_dma
-+		     && (core_if->snpsid >= OTG_CORE_REV_2_90a)
-+		     && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+			 || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+			 || (op_mode ==
-+			     DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
-+			 || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
-+			 || (op_mode ==
-+			     DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
-+
-+			DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
-+				  "Either core version is below 2.90a or "
-+				  "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
-+				  "To run the driver in Buffer DMA host mode set dma_desc_enable "
-+				  "module parameter to 0.\n");
-+			return;
-+		}
-+		hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
-+		hcfg.b.descdma = 1;
-+		DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
-+	}
-+
-+	/* Configure data FIFO sizes */
-+	if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
-+		DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
-+			    core_if->total_fifo_size);
-+		DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
-+			    params->host_rx_fifo_size);
-+		DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
-+			    params->host_nperio_tx_fifo_size);
-+		DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
-+			    params->host_perio_tx_fifo_size);
-+
-+		/* Rx FIFO */
-+		DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
-+			    DWC_READ_REG32(&global_regs->grxfsiz));
-+		DWC_WRITE_REG32(&global_regs->grxfsiz,
-+				params->host_rx_fifo_size);
-+		DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
-+			    DWC_READ_REG32(&global_regs->grxfsiz));
-+
-+		/* Non-periodic Tx FIFO */
-+		DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
-+			    DWC_READ_REG32(&global_regs->gnptxfsiz));
-+		nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
-+		nptxfifosize.b.startaddr = params->host_rx_fifo_size;
-+		DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
-+		DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
-+			    DWC_READ_REG32(&global_regs->gnptxfsiz));
-+
-+		/* Periodic Tx FIFO */
-+		DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
-+			    DWC_READ_REG32(&global_regs->hptxfsiz));
-+		ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
-+		ptxfifosize.b.startaddr =
-+		    nptxfifosize.b.startaddr + nptxfifosize.b.depth;
-+		DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
-+		DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
-+			    DWC_READ_REG32(&global_regs->hptxfsiz));
-+
-+		if (core_if->en_multiple_tx_fifo
-+		    && core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+			/* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
-+			gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
-+			rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
-+			nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
-+			hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
-+			gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
-+			DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
-+		}
-+	}
-+
-+	/* TODO - check this */
-+	/* Clear Host Set HNP Enable in the OTG Control Register */
-+	gotgctl.b.hstsethnpen = 1;
-+	DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+	/* Make sure the FIFOs are flushed. */
-+	dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
-+	dwc_otg_flush_rx_fifo(core_if);
-+
-+	/* Clear Host Set HNP Enable in the OTG Control Register */
-+	gotgctl.b.hstsethnpen = 1;
-+	DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+
-+	if (!core_if->core_params->dma_desc_enable) {
-+		/* Flush out any leftover queued requests. */
-+		num_channels = core_if->core_params->host_channels;
-+
-+		for (i = 0; i < num_channels; i++) {
-+			hc_regs = core_if->host_if->hc_regs[i];
-+			hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+			hcchar.b.chen = 0;
-+			hcchar.b.chdis = 1;
-+			hcchar.b.epdir = 0;
-+			DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+		}
-+
-+		/* Halt all channels to put them into a known state. */
-+		for (i = 0; i < num_channels; i++) {
-+			int count = 0;
-+			hc_regs = core_if->host_if->hc_regs[i];
-+			hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+			hcchar.b.chen = 1;
-+			hcchar.b.chdis = 1;
-+			hcchar.b.epdir = 0;
-+			DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+			DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
-+			do {
-+				hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+				if (++count > 1000) {
-+					DWC_ERROR
-+					    ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
-+					     __func__, i, hcchar.d32, &hc_regs->hcchar);
-+					break;
-+				}
-+				dwc_udelay(1);
-+			} while (hcchar.b.chen);
-+		}
-+	}
-+
-+	/* Turn on the vbus power. */
-+	DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
-+	if (core_if->op_state == A_HOST) {
-+		hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+		DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
-+		if (hprt0.b.prtpwr == 0) {
-+			hprt0.b.prtpwr = 1;
-+			DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
-+		}
-+	}
-+
-+	dwc_otg_enable_host_interrupts(core_if);
-+}
-+
-+/**
-+ * Prepares a host channel for transferring packets to/from a specific
-+ * endpoint. The HCCHARn register is set up with the characteristics specified
-+ * in _hc. Host channel interrupts that may need to be serviced while this
-+ * transfer is in progress are enabled.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ * @param hc Information needed to initialize the host channel
-+ */
-+void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+	hcintmsk_data_t hc_intr_mask;
-+	hcchar_data_t hcchar;
-+	hcsplt_data_t hcsplt;
-+
-+	uint8_t hc_num = hc->hc_num;
-+	dwc_otg_host_if_t *host_if = core_if->host_if;
-+	dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
-+
-+	/* Clear old interrupt conditions for this host channel. */
-+	hc_intr_mask.d32 = 0xFFFFFFFF;
-+	hc_intr_mask.b.reserved14_31 = 0;
-+	DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
-+
-+	/* Enable channel interrupts required for this transfer. */
-+	hc_intr_mask.d32 = 0;
-+	hc_intr_mask.b.chhltd = 1;
-+	if (core_if->dma_enable) {
-+		/* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
-+		if (!core_if->dma_desc_enable)
-+			hc_intr_mask.b.ahberr = 1;
-+		else {
-+			if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+				hc_intr_mask.b.xfercompl = 1;
-+		}
-+
-+		if (hc->error_state && !hc->do_split &&
-+		    hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+			hc_intr_mask.b.ack = 1;
-+			if (hc->ep_is_in) {
-+				hc_intr_mask.b.datatglerr = 1;
-+				if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
-+					hc_intr_mask.b.nak = 1;
-+				}
-+			}
-+		}
-+	} else {
-+		switch (hc->ep_type) {
-+		case DWC_OTG_EP_TYPE_CONTROL:
-+		case DWC_OTG_EP_TYPE_BULK:
-+			hc_intr_mask.b.xfercompl = 1;
-+			hc_intr_mask.b.stall = 1;
-+			hc_intr_mask.b.xacterr = 1;
-+			hc_intr_mask.b.datatglerr = 1;
-+			if (hc->ep_is_in) {
-+				hc_intr_mask.b.bblerr = 1;
-+			} else {
-+				hc_intr_mask.b.nak = 1;
-+				hc_intr_mask.b.nyet = 1;
-+				if (hc->do_ping) {
-+					hc_intr_mask.b.ack = 1;
-+				}
-+			}
-+
-+			if (hc->do_split) {
-+				hc_intr_mask.b.nak = 1;
-+				if (hc->complete_split) {
-+					hc_intr_mask.b.nyet = 1;
-+				} else {
-+					hc_intr_mask.b.ack = 1;
-+				}
-+			}
-+
-+			if (hc->error_state) {
-+				hc_intr_mask.b.ack = 1;
-+			}
-+			break;
-+		case DWC_OTG_EP_TYPE_INTR:
-+			hc_intr_mask.b.xfercompl = 1;
-+			hc_intr_mask.b.nak = 1;
-+			hc_intr_mask.b.stall = 1;
-+			hc_intr_mask.b.xacterr = 1;
-+			hc_intr_mask.b.datatglerr = 1;
-+			hc_intr_mask.b.frmovrun = 1;
-+
-+			if (hc->ep_is_in) {
-+				hc_intr_mask.b.bblerr = 1;
-+			}
-+			if (hc->error_state) {
-+				hc_intr_mask.b.ack = 1;
-+			}
-+			if (hc->do_split) {
-+				if (hc->complete_split) {
-+					hc_intr_mask.b.nyet = 1;
-+				} else {
-+					hc_intr_mask.b.ack = 1;
-+				}
-+			}
-+			break;
-+		case DWC_OTG_EP_TYPE_ISOC:
-+			hc_intr_mask.b.xfercompl = 1;
-+			hc_intr_mask.b.frmovrun = 1;
-+			hc_intr_mask.b.ack = 1;
-+
-+			if (hc->ep_is_in) {
-+				hc_intr_mask.b.xacterr = 1;
-+				hc_intr_mask.b.bblerr = 1;
-+			}
-+			break;
-+		}
-+	}
-+	DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
-+
-+	/*
-+	 * Program the HCCHARn register with the endpoint characteristics for
-+	 * the current transfer.
-+	 */
-+	hcchar.d32 = 0;
-+	hcchar.b.devaddr = hc->dev_addr;
-+	hcchar.b.epnum = hc->ep_num;
-+	hcchar.b.epdir = hc->ep_is_in;
-+	hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
-+	hcchar.b.eptype = hc->ep_type;
-+	hcchar.b.mps = hc->max_packet;
-+
-+	DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
-+
-+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n",
-+                    __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);
-+	DWC_DEBUGPL(DBG_HCDV, "	 Is In %d, Is Low Speed %d, EP Type %d, "
-+                                "Max Pkt %d, Multi Cnt %d\n",
-+                    hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,
-+                    hcchar.b.mps, hcchar.b.multicnt);
-+
-+	/*
-+	 * Program the HCSPLIT register for SPLITs
-+	 */
-+	hcsplt.d32 = 0;
-+	if (hc->do_split) {
-+		DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
-+			    hc->hc_num,
-+			    hc->complete_split ? "CSPLIT" : "SSPLIT");
-+		hcsplt.b.compsplt = hc->complete_split;
-+		hcsplt.b.xactpos = hc->xact_pos;
-+		hcsplt.b.hubaddr = hc->hub_addr;
-+		hcsplt.b.prtaddr = hc->port_addr;
-+		DWC_DEBUGPL(DBG_HCDV, "\t  comp split %d\n", hc->complete_split);
-+		DWC_DEBUGPL(DBG_HCDV, "\t  xact pos %d\n", hc->xact_pos);
-+		DWC_DEBUGPL(DBG_HCDV, "\t  hub addr %d\n", hc->hub_addr);
-+		DWC_DEBUGPL(DBG_HCDV, "\t  port addr %d\n", hc->port_addr);
-+		DWC_DEBUGPL(DBG_HCDV, "\t  is_in %d\n", hc->ep_is_in);
-+		DWC_DEBUGPL(DBG_HCDV, "\t  Max Pkt: %d\n", hcchar.b.mps);
-+		DWC_DEBUGPL(DBG_HCDV, "\t  xferlen: %d\n", hc->xfer_len);
-+	}
-+	DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
-+
-+}
-+
-+/**
-+ * Attempts to halt a host channel. This function should only be called in
-+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
-+ * normal circumstances in DMA mode, the controller halts the channel when the
-+ * transfer is complete or a condition occurs that requires application
-+ * intervention.
-+ *
-+ * In slave mode, checks for a free request queue entry, then sets the Channel
-+ * Enable and Channel Disable bits of the Host Channel Characteristics
-+ * register of the specified channel to intiate the halt. If there is no free
-+ * request queue entry, sets only the Channel Disable bit of the HCCHARn
-+ * register to flush requests for this channel. In the latter case, sets a
-+ * flag to indicate that the host channel needs to be halted when a request
-+ * queue slot is open.
-+ *
-+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
-+ * HCCHARn register. The controller ensures there is space in the request
-+ * queue before submitting the halt request.
-+ *
-+ * Some time may elapse before the core flushes any posted requests for this
-+ * host channel and halts. The Channel Halted interrupt handler completes the
-+ * deactivation of the host channel.
-+ *
-+ * @param core_if Controller register interface.
-+ * @param hc Host channel to halt.
-+ * @param halt_status Reason for halting the channel.
-+ */
-+void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
-+		     dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
-+{
-+	gnptxsts_data_t nptxsts;
-+	hptxsts_data_t hptxsts;
-+	hcchar_data_t hcchar;
-+	dwc_otg_hc_regs_t *hc_regs;
-+	dwc_otg_core_global_regs_t *global_regs;
-+	dwc_otg_host_global_regs_t *host_global_regs;
-+
-+	hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+	global_regs = core_if->core_global_regs;
-+	host_global_regs = core_if->host_if->host_global_regs;
-+
-+	DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
-+		   "halt_status = %d\n", halt_status);
-+
-+	if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
-+	    halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
-+		/*
-+		 * Disable all channel interrupts except Ch Halted. The QTD
-+		 * and QH state associated with this transfer has been cleared
-+		 * (in the case of URB_DEQUEUE), so the channel needs to be
-+		 * shut down carefully to prevent crashes.
-+		 */
-+		hcintmsk_data_t hcintmsk;
-+		hcintmsk.d32 = 0;
-+		hcintmsk.b.chhltd = 1;
-+		DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
-+
-+		/*
-+		 * Make sure no other interrupts besides halt are currently
-+		 * pending. Handling another interrupt could cause a crash due
-+		 * to the QTD and QH state.
-+		 */
-+		DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
-+
-+		/*
-+		 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
-+		 * even if the channel was already halted for some other
-+		 * reason.
-+		 */
-+		hc->halt_status = halt_status;
-+
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+		if (hcchar.b.chen == 0) {
-+			/*
-+			 * The channel is either already halted or it hasn't
-+			 * started yet. In DMA mode, the transfer may halt if
-+			 * it finishes normally or a condition occurs that
-+			 * requires driver intervention. Don't want to halt
-+			 * the channel again. In either Slave or DMA mode,
-+			 * it's possible that the transfer has been assigned
-+			 * to a channel, but not started yet when an URB is
-+			 * dequeued. Don't want to halt a channel that hasn't
-+			 * started yet.
-+			 */
-+			return;
-+		}
-+	}
-+	if (hc->halt_pending) {
-+		/*
-+		 * A halt has already been issued for this channel. This might
-+		 * happen when a transfer is aborted by a higher level in
-+		 * the stack.
-+		 */
-+#ifdef DEBUG
-+		DWC_PRINTF
-+		    ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
-+		     __func__, hc->hc_num);
-+
-+#endif
-+		return;
-+	}
-+
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+	/* No need to set the bit in DDMA for disabling the channel */
-+	//TODO check it everywhere channel is disabled
-+	if (!core_if->core_params->dma_desc_enable)
-+		hcchar.b.chen = 1;
-+	hcchar.b.chdis = 1;
-+
-+	if (!core_if->dma_enable) {
-+		/* Check for space in the request queue to issue the halt. */
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+		    hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
-+			nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+			if (nptxsts.b.nptxqspcavail == 0) {
-+				hcchar.b.chen = 0;
-+			}
-+		} else {
-+			hptxsts.d32 =
-+			    DWC_READ_REG32(&host_global_regs->hptxsts);
-+			if ((hptxsts.b.ptxqspcavail == 0)
-+			    || (core_if->queuing_high_bandwidth)) {
-+				hcchar.b.chen = 0;
-+			}
-+		}
-+	}
-+	DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+	hc->halt_status = halt_status;
-+
-+	if (hcchar.b.chen) {
-+		hc->halt_pending = 1;
-+		hc->halt_on_queue = 0;
-+	} else {
-+		hc->halt_on_queue = 1;
-+	}
-+
-+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+	DWC_DEBUGPL(DBG_HCDV, "	 hcchar: 0x%08x\n", hcchar.d32);
-+	DWC_DEBUGPL(DBG_HCDV, "	 halt_pending: %d\n", hc->halt_pending);
-+	DWC_DEBUGPL(DBG_HCDV, "	 halt_on_queue: %d\n", hc->halt_on_queue);
-+	DWC_DEBUGPL(DBG_HCDV, "	 halt_status: %d\n", hc->halt_status);
-+
-+	return;
-+}
-+
-+/**
-+ * Clears the transfer state for a host channel. This function is normally
-+ * called after a transfer is done and the host channel is being released.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Identifies the host channel to clean up.
-+ */
-+void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+	dwc_otg_hc_regs_t *hc_regs;
-+
-+	hc->xfer_started = 0;
-+
-+	/*
-+	 * Clear channel interrupt enables and any unhandled channel interrupt
-+	 * conditions.
-+	 */
-+	hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+	DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
-+	DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
-+#ifdef DEBUG
-+	DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
-+#endif
-+}
-+
-+/**
-+ * Sets the channel property that indicates in which frame a periodic transfer
-+ * should occur. This is always set to the _next_ frame. This function has no
-+ * effect on non-periodic transfers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Identifies the host channel to set up and its properties.
-+ * @param hcchar Current value of the HCCHAR register for the specified host
-+ * channel.
-+ */
-+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
-+					 dwc_hc_t * hc, hcchar_data_t * hcchar)
-+{
-+	if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+	    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+		hfnum_data_t hfnum;
-+		hfnum.d32 =
-+		    DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
-+
-+		/* 1 if _next_ frame is odd, 0 if it's even */
-+		hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
-+#ifdef DEBUG
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
-+		    && !hc->complete_split) {
-+			switch (hfnum.b.frnum & 0x7) {
-+			case 7:
-+				core_if->hfnum_7_samples++;
-+				core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
-+				break;
-+			case 0:
-+				core_if->hfnum_0_samples++;
-+				core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
-+				break;
-+			default:
-+				core_if->hfnum_other_samples++;
-+				core_if->hfnum_other_frrem_accum +=
-+				    hfnum.b.frrem;
-+				break;
-+			}
-+		}
-+#endif
-+	}
-+}
-+
-+#ifdef DEBUG
-+void hc_xfer_timeout(void *ptr)
-+{
-+	hc_xfer_info_t *xfer_info = NULL;
-+	int hc_num = 0;
-+
-+	if (ptr)
-+		xfer_info = (hc_xfer_info_t *) ptr;
-+
-+	if (!xfer_info->hc) {
-+		DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
-+		return;
-+	}
-+
-+	hc_num = xfer_info->hc->hc_num;
-+	DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
-+	DWC_WARN("	start_hcchar_val 0x%08x\n",
-+		 xfer_info->core_if->start_hcchar_val[hc_num]);
-+}
-+#endif
-+
-+void ep_xfer_timeout(void *ptr)
-+{
-+	ep_xfer_info_t *xfer_info = NULL;
-+	int ep_num = 0;
-+	dctl_data_t dctl = {.d32 = 0 };
-+	gintsts_data_t gintsts = {.d32 = 0 };
-+	gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+	if (ptr)
-+		xfer_info = (ep_xfer_info_t *) ptr;
-+
-+	if (!xfer_info->ep) {
-+		DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
-+		return;
-+	}
-+
-+	ep_num = xfer_info->ep->num;
-+	DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
-+	/* Put the sate to 2 as it was time outed */
-+	xfer_info->state = 2;
-+
-+	dctl.d32 =
-+	    DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
-+	gintsts.d32 =
-+	    DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
-+	gintmsk.d32 =
-+	    DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
-+
-+	if (!gintmsk.b.goutnakeff) {
-+		/* Unmask it */
-+		gintmsk.b.goutnakeff = 1;
-+		DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
-+				gintmsk.d32);
-+
-+	}
-+
-+	if (!gintsts.b.goutnakeff) {
-+		dctl.b.sgoutnak = 1;
-+	}
-+	DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
-+			dctl.d32);
-+
-+}
-+
-+void set_pid_isoc(dwc_hc_t * hc)
-+{
-+	/* Set up the initial PID for the transfer. */
-+	if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
-+		if (hc->ep_is_in) {
-+			if (hc->multi_count == 1) {
-+				hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+			} else if (hc->multi_count == 2) {
-+				hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
-+			} else {
-+				hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
-+			}
-+		} else {
-+			if (hc->multi_count == 1) {
-+				hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+			} else {
-+				hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
-+			}
-+		}
-+	} else {
-+		hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
-+	}
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for a host channel and
-+ * starts the transfer. May be called in either Slave mode or DMA mode. In
-+ * Slave mode, the caller must ensure that there is sufficient space in the
-+ * request queue and Tx Data FIFO.
-+ *
-+ * For an OUT transfer in Slave mode, it loads a data packet into the
-+ * appropriate FIFO. If necessary, additional data packets will be loaded in
-+ * the Host ISR.
-+ *
-+ * For an IN transfer in Slave mode, a data packet is requested. The data
-+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
-+ * additional data packets are requested in the Host ISR.
-+ *
-+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
-+ * register along with a packet count of 1 and the channel is enabled. This
-+ * causes a single PING transaction to occur. Other fields in HCTSIZ are
-+ * simply set to 0 since no data transfer occurs in this case.
-+ *
-+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
-+ * all the information required to perform the subsequent data transfer. In
-+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
-+ * controller performs the entire PING protocol, then starts the data
-+ * transfer.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Information needed to initialize the host channel. The xfer_len
-+ * value may be reduced to accommodate the max widths of the XferSize and
-+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
-+ * to reflect the final xfer_len value.
-+ */
-+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+	hcchar_data_t hcchar;
-+	hctsiz_data_t hctsiz;
-+	uint16_t num_packets;
-+	uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
-+	uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
-+	dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+	hctsiz.d32 = 0;
-+
-+	if (hc->do_ping) {
-+		if (!core_if->dma_enable) {
-+			dwc_otg_hc_do_ping(core_if, hc);
-+			hc->xfer_started = 1;
-+			return;
-+		} else {
-+			hctsiz.b.dopng = 1;
-+		}
-+	}
-+
-+	if (hc->do_split) {
-+		num_packets = 1;
-+
-+		if (hc->complete_split && !hc->ep_is_in) {
-+			/* For CSPLIT OUT Transfer, set the size to 0 so the
-+			 * core doesn't expect any data written to the FIFO */
-+			hc->xfer_len = 0;
-+		} else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
-+			hc->xfer_len = hc->max_packet;
-+		} else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
-+			hc->xfer_len = 188;
-+		}
-+
-+		hctsiz.b.xfersize = hc->xfer_len;
-+	} else {
-+		/*
-+		 * Ensure that the transfer length and packet count will fit
-+		 * in the widths allocated for them in the HCTSIZn register.
-+		 */
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+		    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+			/*
-+			 * Make sure the transfer size is no larger than one
-+			 * (micro)frame's worth of data. (A check was done
-+			 * when the periodic transfer was accepted to ensure
-+			 * that a (micro)frame's worth of data can be
-+			 * programmed into a channel.)
-+			 */
-+			uint32_t max_periodic_len =
-+			    hc->multi_count * hc->max_packet;
-+			if (hc->xfer_len > max_periodic_len) {
-+				hc->xfer_len = max_periodic_len;
-+			} else {
-+			}
-+		} else if (hc->xfer_len > max_hc_xfer_size) {
-+			/* Make sure that xfer_len is a multiple of max packet size. */
-+			hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
-+		}
-+
-+		if (hc->xfer_len > 0) {
-+			num_packets =
-+			    (hc->xfer_len + hc->max_packet -
-+			     1) / hc->max_packet;
-+			if (num_packets > max_hc_pkt_count) {
-+				num_packets = max_hc_pkt_count;
-+				hc->xfer_len = num_packets * hc->max_packet;
-+			}
-+		} else {
-+			/* Need 1 packet for transfer length of 0. */
-+			num_packets = 1;
-+		}
-+
-+		if (hc->ep_is_in) {
-+			/* Always program an integral # of max packets for IN transfers. */
-+			hc->xfer_len = num_packets * hc->max_packet;
-+		}
-+
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+		    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+			/*
-+			 * Make sure that the multi_count field matches the
-+			 * actual transfer length.
-+			 */
-+			hc->multi_count = num_packets;
-+		}
-+
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+			set_pid_isoc(hc);
-+
-+		hctsiz.b.xfersize = hc->xfer_len;
-+	}
-+
-+	hc->start_pkt_count = num_packets;
-+	hctsiz.b.pktcnt = num_packets;
-+	hctsiz.b.pid = hc->data_pid_start;
-+	DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+	DWC_DEBUGPL(DBG_HCDV, "	 Xfer Size: %d\n", hctsiz.b.xfersize);
-+	DWC_DEBUGPL(DBG_HCDV, "	 Num Pkts: %d\n", hctsiz.b.pktcnt);
-+	DWC_DEBUGPL(DBG_HCDV, "	 Start PID: %d\n", hctsiz.b.pid);
-+
-+	if (core_if->dma_enable) {
-+		dwc_dma_t dma_addr;
-+		if (hc->align_buff) {
-+			dma_addr = hc->align_buff;
-+		} else {
-+			dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
-+		}
-+		DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
-+	}
-+
-+	/* Start the split */
-+	if (hc->do_split) {
-+		hcsplt_data_t hcsplt;
-+		hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+		hcsplt.b.spltena = 1;
-+		DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
-+	}
-+
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	hcchar.b.multicnt = hc->multi_count;
-+	hc_set_even_odd_frame(core_if, hc, &hcchar);
-+#ifdef DEBUG
-+	core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
-+	if (hcchar.b.chdis) {
-+		DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-+			 __func__, hc->hc_num, hcchar.d32);
-+	}
-+#endif
-+
-+	/* Set host channel enable after all other setup is complete. */
-+	hcchar.b.chen = 1;
-+	hcchar.b.chdis = 0;
-+	DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+	hc->xfer_started = 1;
-+	hc->requests++;
-+
-+	if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
-+		/* Load OUT packet into the appropriate Tx FIFO. */
-+		dwc_otg_hc_write_packet(core_if, hc);
-+	}
-+#ifdef DEBUG
-+	if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
-+                DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
-+                            hc->hc_num, core_if);//GRAYG
-+		core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
-+		core_if->hc_xfer_info[hc->hc_num].hc = hc;
-+
-+		/* Start a timer for this transfer. */
-+		DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
-+	}
-+#endif
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for a host channel
-+ * and starts the transfer in Descriptor DMA mode.
-+ *
-+ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
-+ * Sets PID and NTD values. For periodic transfers
-+ * initializes SCHED_INFO field with micro-frame bitmap.
-+ *
-+ * Initializes HCDMA register with descriptor list address and CTD value
-+ * then starts the transfer via enabling the channel.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param hc Information needed to initialize the host channel.
-+ */
-+void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+	dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+	hcchar_data_t hcchar;
-+	hctsiz_data_t hctsiz;
-+	hcdma_data_t hcdma;
-+
-+	hctsiz.d32 = 0;
-+
-+	if (hc->do_ping)
-+		hctsiz.b_ddma.dopng = 1;
-+
-+	if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+		set_pid_isoc(hc);
-+
-+	/* Packet Count and Xfer Size are not used in Descriptor DMA mode */
-+	hctsiz.b_ddma.pid = hc->data_pid_start;
-+	hctsiz.b_ddma.ntd = hc->ntd - 1;	/* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
-+	hctsiz.b_ddma.schinfo = hc->schinfo;	/* Non-zero only for high-speed interrupt endpoints */
-+
-+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+	DWC_DEBUGPL(DBG_HCDV, "	 Start PID: %d\n", hctsiz.b.pid);
-+	DWC_DEBUGPL(DBG_HCDV, "	 NTD: %d\n", hctsiz.b_ddma.ntd);
-+
-+	DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+	hcdma.d32 = 0;
-+	hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
-+
-+	/* Always start from first descriptor. */
-+	hcdma.b.ctd = 0;
-+	DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
-+
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	hcchar.b.multicnt = hc->multi_count;
-+
-+#ifdef DEBUG
-+	core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
-+	if (hcchar.b.chdis) {
-+		DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
-+			 __func__, hc->hc_num, hcchar.d32);
-+	}
-+#endif
-+
-+	/* Set host channel enable after all other setup is complete. */
-+	hcchar.b.chen = 1;
-+	hcchar.b.chdis = 0;
-+
-+	DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+	hc->xfer_started = 1;
-+	hc->requests++;
-+
-+#ifdef DEBUG
-+	if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
-+	    && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
-+                DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
-+                            hc->hc_num, core_if);//GRAYG
-+		core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
-+		core_if->hc_xfer_info[hc->hc_num].hc = hc;
-+		/* Start a timer for this transfer. */
-+		DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
-+	}
-+#endif
-+
-+}
-+
-+/**
-+ * This function continues a data transfer that was started by previous call
-+ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
-+ * sufficient space in the request queue and Tx Data FIFO. This function
-+ * should only be called in Slave mode. In DMA mode, the controller acts
-+ * autonomously to complete transfers programmed to a host channel.
-+ *
-+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
-+ * if there is any data remaining to be queued. For an IN transfer, another
-+ * data packet is always requested. For the SETUP phase of a control transfer,
-+ * this function does nothing.
-+ *
-+ * @return 1 if a new request is queued, 0 if no more requests are required
-+ * for this transfer.
-+ */
-+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+
-+	if (hc->do_split) {
-+		/* SPLITs always queue just once per channel */
-+		return 0;
-+	} else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
-+		/* SETUPs are queued only once since they can't be NAKed. */
-+		return 0;
-+	} else if (hc->ep_is_in) {
-+		/*
-+		 * Always queue another request for other IN transfers. If
-+		 * back-to-back INs are issued and NAKs are received for both,
-+		 * the driver may still be processing the first NAK when the
-+		 * second NAK is received. When the interrupt handler clears
-+		 * the NAK interrupt for the first NAK, the second NAK will
-+		 * not be seen. So we can't depend on the NAK interrupt
-+		 * handler to requeue a NAKed request. Instead, IN requests
-+		 * are issued each time this function is called. When the
-+		 * transfer completes, the extra requests for the channel will
-+		 * be flushed.
-+		 */
-+		hcchar_data_t hcchar;
-+		dwc_otg_hc_regs_t *hc_regs =
-+		    core_if->host_if->hc_regs[hc->hc_num];
-+
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+		hc_set_even_odd_frame(core_if, hc, &hcchar);
-+		hcchar.b.chen = 1;
-+		hcchar.b.chdis = 0;
-+		DWC_DEBUGPL(DBG_HCDV, "	 IN xfer: hcchar = 0x%08x\n",
-+			    hcchar.d32);
-+		DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+		hc->requests++;
-+		return 1;
-+	} else {
-+		/* OUT transfers. */
-+		if (hc->xfer_count < hc->xfer_len) {
-+			if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+			    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+				hcchar_data_t hcchar;
-+				dwc_otg_hc_regs_t *hc_regs;
-+				hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+				hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+				hc_set_even_odd_frame(core_if, hc, &hcchar);
-+			}
-+
-+			/* Load OUT packet into the appropriate Tx FIFO. */
-+			dwc_otg_hc_write_packet(core_if, hc);
-+			hc->requests++;
-+			return 1;
-+		} else {
-+			return 0;
-+		}
-+	}
-+}
-+
-+/**
-+ * Starts a PING transfer. This function should only be called in Slave mode.
-+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
-+ */
-+void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+	hcchar_data_t hcchar;
-+	hctsiz_data_t hctsiz;
-+	dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
-+
-+	DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
-+
-+	hctsiz.d32 = 0;
-+	hctsiz.b.dopng = 1;
-+	hctsiz.b.pktcnt = 1;
-+	DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	hcchar.b.chen = 1;
-+	hcchar.b.chdis = 0;
-+	DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+}
-+
-+/*
-+ * This function writes a packet into the Tx FIFO associated with the Host
-+ * Channel. For a channel associated with a non-periodic EP, the non-periodic
-+ * Tx FIFO is written. For a channel associated with a periodic EP, the
-+ * periodic Tx FIFO is written. This function should only be called in Slave
-+ * mode.
-+ *
-+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
-+ * then number of bytes written to the Tx FIFO.
-+ */
-+void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
-+{
-+	uint32_t i;
-+	uint32_t remaining_count;
-+	uint32_t byte_count;
-+	uint32_t dword_count;
-+
-+	uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
-+	uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
-+
-+	remaining_count = hc->xfer_len - hc->xfer_count;
-+	if (remaining_count > hc->max_packet) {
-+		byte_count = hc->max_packet;
-+	} else {
-+		byte_count = remaining_count;
-+	}
-+
-+	dword_count = (byte_count + 3) / 4;
-+
-+	if ((((unsigned long)data_buff) & 0x3) == 0) {
-+		/* xfer_buff is DWORD aligned. */
-+		for (i = 0; i < dword_count; i++, data_buff++) {
-+			DWC_WRITE_REG32(data_fifo, *data_buff);
-+		}
-+	} else {
-+		/* xfer_buff is not DWORD aligned. */
-+		for (i = 0; i < dword_count; i++, data_buff++) {
-+			uint32_t data;
-+			data =
-+			    (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
-+			     16 | data_buff[3] << 24);
-+			DWC_WRITE_REG32(data_fifo, data);
-+		}
-+	}
-+
-+	hc->xfer_count += byte_count;
-+	hc->xfer_buff += byte_count;
-+}
-+
-+/**
-+ * Gets the current USB frame number. This is the frame number from the last
-+ * SOF packet.
-+ */
-+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
-+{
-+	dsts_data_t dsts;
-+	dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+	/* read current frame/microframe number from DSTS register */
-+	return dsts.b.soffn;
-+}
-+
-+/**
-+ * Calculates and gets the frame Interval value of HFIR register according PHY
-+ * type and speed.The application can modify a value of HFIR register only after
-+ * the Port Enable bit of the Host Port Control and Status register
-+ * (HPRT.PrtEnaPort) has been set.
-+*/
-+
-+uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
-+{
-+	gusbcfg_data_t usbcfg;
-+	hwcfg2_data_t hwcfg2;
-+	hprt0_data_t hprt0;
-+	int clock = 60;		// default value
-+	usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+	hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
-+	hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+	if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
-+		clock = 60;
-+	if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
-+		clock = 48;
-+	if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+	    !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
-+		clock = 30;
-+	if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+	    !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
-+		clock = 60;
-+	if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
-+	    !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
-+		clock = 48;
-+	if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
-+		clock = 48;
-+	if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
-+		clock = 48;
-+	if (hprt0.b.prtspd == 0)
-+		/* High speed case */
-+		return 125 * clock - 1;
-+	else
-+		/* FS/LS case */
-+		return 1000 * clock - 1;
-+}
-+
-+/**
-+ * This function reads a setup packet from the Rx FIFO into the destination
-+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
-+ * Interrupt routine when a SETUP packet has been received in Slave mode.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dest Destination buffer for packet data.
-+ */
-+void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
-+{
-+	device_grxsts_data_t status;
-+	/* Get the 8 bytes of a setup transaction data */
-+
-+	/* Pop 2 DWORDS off the receive data FIFO into memory */
-+	dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
-+	dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
-+	if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+		status.d32 =
-+		    DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
-+		DWC_DEBUGPL(DBG_ANY,
-+			    "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
-+			    status.b.epnum, status.b.bcnt, status.b.pktsts,
-+			    status.b.fn, status.b.fn);
-+	}
-+}
-+
-+/**
-+ * This function enables EP0 OUT to receive SETUP packets and configures EP0
-+ * IN for transmitting packets. It is normally called when the
-+ * "Enumeration Done" interrupt occurs.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	dsts_data_t dsts;
-+	depctl_data_t diepctl;
-+	depctl_data_t doepctl;
-+	dctl_data_t dctl = {.d32 = 0 };
-+
-+	ep->stp_rollover = 0;
-+	/* Read the Device Status and Endpoint 0 Control registers */
-+	dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
-+	diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+	doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
-+
-+	/* Set the MPS of the IN EP based on the enumeration speed */
-+	switch (dsts.b.enumspd) {
-+	case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
-+	case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
-+	case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
-+		diepctl.b.mps = DWC_DEP0CTL_MPS_64;
-+		break;
-+	case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
-+		diepctl.b.mps = DWC_DEP0CTL_MPS_8;
-+		break;
-+	}
-+
-+	DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+	/* Enable OUT EP for receive */
-+	if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+	doepctl.b.epena = 1;
-+	DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
-+	}
-+#ifdef VERBOSE
-+	DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
-+		    DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+	DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
-+		    DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
-+#endif
-+	dctl.b.cgnpinnak = 1;
-+
-+	DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+	DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
-+		    DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
-+
-+}
-+
-+/**
-+ * This function activates an EP.  The Device EP control register for
-+ * the EP is configured as defined in the ep structure. Note: This
-+ * function is not used for EP0.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to activate.
-+ */
-+void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	depctl_data_t depctl;
-+	volatile uint32_t *addr;
-+	daint_data_t daintmsk = {.d32 = 0 };
-+	dcfg_data_t dcfg;
-+	uint8_t i;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
-+		    (ep->is_in ? "IN" : "OUT"));
-+
-+#ifdef DWC_UTE_PER_IO
-+	ep->xiso_frame_num = 0xFFFFFFFF;
-+	ep->xiso_active_xfers = 0;
-+	ep->xiso_queued_xfers = 0;
-+#endif
-+	/* Read DEPCTLn register */
-+	if (ep->is_in == 1) {
-+		addr = &dev_if->in_ep_regs[ep->num]->diepctl;
-+		daintmsk.ep.in = 1 << ep->num;
-+	} else {
-+		addr = &dev_if->out_ep_regs[ep->num]->doepctl;
-+		daintmsk.ep.out = 1 << ep->num;
-+	}
-+
-+	/* If the EP is already active don't change the EP Control
-+	 * register. */
-+	depctl.d32 = DWC_READ_REG32(addr);
-+	if (!depctl.b.usbactep) {
-+		depctl.b.mps = ep->maxpacket;
-+		depctl.b.eptype = ep->type;
-+		depctl.b.txfnum = ep->tx_fifo_num;
-+
-+		if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+			depctl.b.setd0pid = 1;	// ???
-+		} else {
-+			depctl.b.setd0pid = 1;
-+		}
-+		depctl.b.usbactep = 1;
-+
-+		/* Update nextep_seq array and EPMSCNT in DCFG*/
-+		if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {	// NP IN EP
-+			for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+				if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
-+				break;
-+			}
-+			core_if->nextep_seq[i] = ep->num;
-+			core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
-+			depctl.b.nextep = core_if->nextep_seq[ep->num];
-+			dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+			dcfg.b.epmscnt++;
-+			DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+			DWC_DEBUGPL(DBG_PCDV,
-+				    "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+				__func__, core_if->first_in_nextep_seq);
-+			for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+				DWC_DEBUGPL(DBG_PCDV, "%2d\n",
-+					    core_if->nextep_seq[i]);
-+			}
-+
-+		}
-+
-+
-+		DWC_WRITE_REG32(addr, depctl.d32);
-+		DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
-+	}
-+
-+	/* Enable the Interrupt for this EP */
-+	if (core_if->multiproc_int_enable) {
-+		if (ep->is_in == 1) {
-+			diepmsk_data_t diepmsk = {.d32 = 0 };
-+			diepmsk.b.xfercompl = 1;
-+			diepmsk.b.timeout = 1;
-+			diepmsk.b.epdisabled = 1;
-+			diepmsk.b.ahberr = 1;
-+			diepmsk.b.intknepmis = 1;
-+			if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+				diepmsk.b.intknepmis = 0;
-+			diepmsk.b.txfifoundrn = 1;	//?????
-+			if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+				diepmsk.b.nak = 1;
-+			}
-+
-+
-+
-+/*
-+			if (core_if->dma_desc_enable) {
-+				diepmsk.b.bna = 1;
-+			}
-+*/
-+/*
-+			if (core_if->dma_enable) {
-+				doepmsk.b.nak = 1;
-+			}
-+*/
-+			DWC_WRITE_REG32(&dev_if->dev_global_regs->
-+					diepeachintmsk[ep->num], diepmsk.d32);
-+
-+		} else {
-+			doepmsk_data_t doepmsk = {.d32 = 0 };
-+			doepmsk.b.xfercompl = 1;
-+			doepmsk.b.ahberr = 1;
-+			doepmsk.b.epdisabled = 1;
-+			if (ep->type == DWC_OTG_EP_TYPE_ISOC)
-+				doepmsk.b.outtknepdis = 1;
-+
-+/*
-+
-+			if (core_if->dma_desc_enable) {
-+				doepmsk.b.bna = 1;
-+			}
-+*/
-+/*
-+			doepmsk.b.babble = 1;
-+			doepmsk.b.nyet = 1;
-+			doepmsk.b.nak = 1;
-+*/
-+			DWC_WRITE_REG32(&dev_if->dev_global_regs->
-+					doepeachintmsk[ep->num], doepmsk.d32);
-+		}
-+		DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
-+				 0, daintmsk.d32);
-+	} else {
-+		if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+			if (ep->is_in) {
-+				diepmsk_data_t diepmsk = {.d32 = 0 };
-+				diepmsk.b.nak = 1;
-+				DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
-+			} else {
-+				doepmsk_data_t doepmsk = {.d32 = 0 };
-+				doepmsk.b.outtknepdis = 1;
-+				DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
-+			}
-+		}
-+		DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
-+				 0, daintmsk.d32);
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
-+		    DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
-+
-+	ep->stall_clear_flag = 0;
-+
-+	return;
-+}
-+
-+/**
-+ * This function deactivates an EP. This is done by clearing the USB Active
-+ * EP bit in the Device EP control register. Note: This function is not used
-+ * for EP0. EP0 cannot be deactivated.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to deactivate.
-+ */
-+void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	depctl_data_t depctl = {.d32 = 0 };
-+	volatile uint32_t *addr;
-+	daint_data_t daintmsk = {.d32 = 0 };
-+	dcfg_data_t dcfg;
-+	uint8_t i = 0;
-+
-+#ifdef DWC_UTE_PER_IO
-+	ep->xiso_frame_num = 0xFFFFFFFF;
-+	ep->xiso_active_xfers = 0;
-+	ep->xiso_queued_xfers = 0;
-+#endif
-+
-+	/* Read DEPCTLn register */
-+	if (ep->is_in == 1) {
-+		addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+		daintmsk.ep.in = 1 << ep->num;
-+	} else {
-+		addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+		daintmsk.ep.out = 1 << ep->num;
-+	}
-+
-+	depctl.d32 = DWC_READ_REG32(addr);
-+
-+	depctl.b.usbactep = 0;
-+
-+	/* Update nextep_seq array and EPMSCNT in DCFG*/
-+	if (!(depctl.b.eptype & 1) && ep->is_in == 1) {	// NP EP IN
-+		for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+			if (core_if->nextep_seq[i] == ep->num)
-+			break;
-+		}
-+		core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
-+		if (core_if->first_in_nextep_seq == ep->num)
-+			core_if->first_in_nextep_seq = i;
-+		core_if->nextep_seq[ep->num] = 0xff;
-+		depctl.b.nextep = 0;
-+		dcfg.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+		dcfg.b.epmscnt--;
-+		DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+				dcfg.d32);
-+
-+		DWC_DEBUGPL(DBG_PCDV,
-+			    "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+				__func__, core_if->first_in_nextep_seq);
-+			for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+				DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
-+			}
-+	}
-+
-+	if (ep->is_in == 1)
-+		depctl.b.txfnum = 0;
-+
-+	if (core_if->dma_desc_enable)
-+		depctl.b.epdis = 1;
-+
-+	DWC_WRITE_REG32(addr, depctl.d32);
-+	depctl.d32 = DWC_READ_REG32(addr);
-+	if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
-+	    && depctl.b.epena) {
-+		depctl_data_t depctl = {.d32 = 0};
-+		if (ep->is_in) {
-+			diepint_data_t diepint = {.d32 = 0};
-+
-+			depctl.b.snak = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+					diepctl, depctl.d32);
-+			do {
-+				dwc_udelay(10);
-+				diepint.d32 =
-+				    DWC_READ_REG32(&core_if->
-+						   dev_if->in_ep_regs[ep->num]->
-+						   diepint);
-+			} while (!diepint.b.inepnakeff);
-+			diepint.b.inepnakeff = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+					diepint, diepint.d32);
-+			depctl.d32 = 0;
-+			depctl.b.epdis = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+					diepctl, depctl.d32);
-+			do {
-+				dwc_udelay(10);
-+				diepint.d32 =
-+				    DWC_READ_REG32(&core_if->
-+						   dev_if->in_ep_regs[ep->num]->
-+						   diepint);
-+			} while (!diepint.b.epdisabled);
-+			diepint.b.epdisabled = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+					diepint, diepint.d32);
-+		} else {
-+			dctl_data_t dctl = {.d32 = 0};
-+			gintmsk_data_t gintsts = {.d32 = 0};
-+			doepint_data_t doepint = {.d32 = 0};
-+			dctl.b.sgoutnak = 1;
-+			DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+					 dctl, 0, dctl.d32);
-+			do {
-+				dwc_udelay(10);
-+				gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+			} while (!gintsts.b.goutnakeff);
-+			gintsts.d32 = 0;
-+			gintsts.b.goutnakeff = 1;
-+			DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+			depctl.d32 = 0;
-+			depctl.b.epdis = 1;
-+			depctl.b.snak = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
-+			do
-+			{
-+				dwc_udelay(10);
-+				doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+											out_ep_regs[ep->num]->doepint);
-+			} while (!doepint.b.epdisabled);
-+
-+			doepint.b.epdisabled = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
-+
-+			dctl.d32 = 0;
-+			dctl.b.cgoutnak = 1;
-+			DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+		}
-+	}
-+
-+	/* Disable the Interrupt for this EP */
-+	if (core_if->multiproc_int_enable) {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
-+				 daintmsk.d32, 0);
-+
-+		if (ep->is_in == 1) {
-+			DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+					diepeachintmsk[ep->num], 0);
-+		} else {
-+			DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
-+					doepeachintmsk[ep->num], 0);
-+		}
-+	} else {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
-+				 daintmsk.d32, 0);
-+	}
-+
-+}
-+
-+/**
-+ * This function initializes dma descriptor chain.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+	uint32_t offset;
-+	uint32_t xfer_est;
-+	int i;
-+	unsigned maxxfer_local, total_len;
-+
-+	if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
-+					(ep->maxpacket%4)) {
-+		maxxfer_local = ep->maxpacket;
-+		total_len = ep->xfer_len;
-+	} else {
-+		maxxfer_local = ep->maxxfer;
-+		total_len = ep->total_len;
-+	}
-+
-+	ep->desc_cnt = (total_len / maxxfer_local) +
-+            ((total_len % maxxfer_local) ? 1 : 0);
-+
-+	if (!ep->desc_cnt)
-+		ep->desc_cnt = 1;
-+
-+	if (ep->desc_cnt > MAX_DMA_DESC_CNT)
-+		ep->desc_cnt = MAX_DMA_DESC_CNT;
-+
-+	dma_desc = ep->desc_addr;
-+	if (maxxfer_local == ep->maxpacket) {
-+		if ((total_len % maxxfer_local) &&
-+				(total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
-+			xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
-+					(total_len % maxxfer_local);
-+		} else
-+			xfer_est = ep->desc_cnt * maxxfer_local;
-+	} else
-+		xfer_est = total_len;
-+	offset = 0;
-+	for (i = 0; i < ep->desc_cnt; ++i) {
-+		/** DMA Descriptor Setup */
-+		if (xfer_est > maxxfer_local) {
-+			dma_desc->status.b.bs = BS_HOST_BUSY;
-+			dma_desc->status.b.l = 0;
-+			dma_desc->status.b.ioc = 0;
-+			dma_desc->status.b.sp = 0;
-+			dma_desc->status.b.bytes = maxxfer_local;
-+			dma_desc->buf = ep->dma_addr + offset;
-+			dma_desc->status.b.sts = 0;
-+			dma_desc->status.b.bs = BS_HOST_READY;
-+
-+			xfer_est -= maxxfer_local;
-+			offset += maxxfer_local;
-+		} else {
-+			dma_desc->status.b.bs = BS_HOST_BUSY;
-+			dma_desc->status.b.l = 1;
-+			dma_desc->status.b.ioc = 1;
-+			if (ep->is_in) {
-+				dma_desc->status.b.sp =
-+				    (xfer_est %
-+				     ep->maxpacket) ? 1 : ((ep->
-+							    sent_zlp) ? 1 : 0);
-+				dma_desc->status.b.bytes = xfer_est;
-+			} else {
-+				if (maxxfer_local == ep->maxpacket)
-+					dma_desc->status.b.bytes = xfer_est;
-+				else
-+					dma_desc->status.b.bytes =
-+						xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
-+			}
-+
-+			dma_desc->buf = ep->dma_addr + offset;
-+			dma_desc->status.b.sts = 0;
-+			dma_desc->status.b.bs = BS_HOST_READY;
-+		}
-+		dma_desc++;
-+	}
-+}
-+/**
-+ * This function is called when to write ISOC data into appropriate dedicated
-+ * periodic FIFO.
-+ */
-+static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
-+{
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	dwc_otg_dev_in_ep_regs_t *ep_regs;
-+	dtxfsts_data_t txstatus = {.d32 = 0 };
-+	uint32_t len = 0;
-+	int epnum = dwc_ep->num;
-+	int dwords;
-+
-+	DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
-+
-+	ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+	len = dwc_ep->xfer_len - dwc_ep->xfer_count;
-+
-+	if (len > dwc_ep->maxpacket) {
-+		len = dwc_ep->maxpacket;
-+	}
-+
-+	dwords = (len + 3) / 4;
-+
-+	/* While there is space in the queue and space in the FIFO and
-+	 * More data to tranfer, Write packets to the Tx FIFO */
-+	txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+	DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
-+
-+	while (txstatus.b.txfspcavail > dwords &&
-+	       dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
-+		/* Write the FIFO */
-+		dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
-+
-+		len = dwc_ep->xfer_len - dwc_ep->xfer_count;
-+		if (len > dwc_ep->maxpacket) {
-+			len = dwc_ep->maxpacket;
-+		}
-+
-+		dwords = (len + 3) / 4;
-+		txstatus.d32 =
-+		    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+		DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
-+			    txstatus.d32);
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
-+		    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
-+
-+	return 1;
-+}
-+/**
-+ * This function does the setup for a data transfer for an EP and
-+ * starts the transfer. For an IN transfer, the packets will be
-+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
-+ * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	depctl_data_t depctl;
-+	deptsiz_data_t deptsiz;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
-+	DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
-+		    "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
-+		    ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
-+		    ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
-+		    ep->total_len);
-+	/* IN endpoint */
-+	if (ep->is_in == 1) {
-+		dwc_otg_dev_in_ep_regs_t *in_regs =
-+		    core_if->dev_if->in_ep_regs[ep->num];
-+
-+		gnptxsts_data_t gtxstatus;
-+
-+		gtxstatus.d32 =
-+		    DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+
-+		if (core_if->en_multiple_tx_fifo == 0
-+		    && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
-+#ifdef DEBUG
-+			DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
-+#endif
-+			return;
-+		}
-+
-+		depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
-+		deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
-+
-+		if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
-+			ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
-+				ep->maxxfer : (ep->total_len - ep->xfer_len);
-+		else
-+			ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
-+				 MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
-+
-+
-+		/* Zero Length Packet? */
-+		if ((ep->xfer_len - ep->xfer_count) == 0) {
-+			deptsiz.b.xfersize = 0;
-+			deptsiz.b.pktcnt = 1;
-+		} else {
-+			/* Program the transfer size and packet count
-+			 *      as follows: xfersize = N * maxpacket +
-+			 *      short_packet pktcnt = N + (short_packet
-+			 *      exist ? 1 : 0)
-+			 */
-+			deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
-+			deptsiz.b.pktcnt =
-+			    (ep->xfer_len - ep->xfer_count - 1 +
-+			     ep->maxpacket) / ep->maxpacket;
-+			if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
-+				deptsiz.b.pktcnt = MAX_PKT_CNT;
-+				deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+			}
-+			if (ep->type == DWC_OTG_EP_TYPE_ISOC)
-+				deptsiz.b.mc = deptsiz.b.pktcnt;
-+		}
-+
-+		/* Write the DMA register */
-+		if (core_if->dma_enable) {
-+			if (core_if->dma_desc_enable == 0) {
-+				if (ep->type != DWC_OTG_EP_TYPE_ISOC)
-+					deptsiz.b.mc = 1;
-+				DWC_WRITE_REG32(&in_regs->dieptsiz,
-+						deptsiz.d32);
-+				DWC_WRITE_REG32(&(in_regs->diepdma),
-+						(uint32_t) ep->dma_addr);
-+			} else {
-+#ifdef DWC_UTE_CFI
-+				/* The descriptor chain should be already initialized by now */
-+				if (ep->buff_mode != BM_STANDARD) {
-+					DWC_WRITE_REG32(&in_regs->diepdma,
-+							ep->descs_dma_addr);
-+				} else {
-+#endif
-+					init_dma_desc_chain(core_if, ep);
-+				/** DIEPDMAn Register write */
-+					DWC_WRITE_REG32(&in_regs->diepdma,
-+							ep->dma_desc_addr);
-+#ifdef DWC_UTE_CFI
-+				}
-+#endif
-+			}
-+		} else {
-+			DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+			if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
-+				/**
-+				 * Enable the Non-Periodic Tx FIFO empty interrupt,
-+				 * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
-+				 * the data will be written into the fifo by the ISR.
-+				 */
-+				if (core_if->en_multiple_tx_fifo == 0) {
-+					intr_mask.b.nptxfempty = 1;
-+					DWC_MODIFY_REG32
-+					    (&core_if->core_global_regs->gintmsk,
-+					     intr_mask.d32, intr_mask.d32);
-+				} else {
-+					/* Enable the Tx FIFO Empty Interrupt for this EP */
-+					if (ep->xfer_len > 0) {
-+						uint32_t fifoemptymsk = 0;
-+						fifoemptymsk = 1 << ep->num;
-+						DWC_MODIFY_REG32
-+						    (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+						     0, fifoemptymsk);
-+
-+					}
-+				}
-+			}  else {
-+					 write_isoc_tx_fifo(core_if, ep);
-+			}
-+		}
-+		if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+			depctl.b.nextep = core_if->nextep_seq[ep->num];
-+
-+		if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+			dsts_data_t dsts = {.d32 = 0};
-+			if (ep->bInterval == 1) {
-+				dsts.d32 =
-+				    DWC_READ_REG32(&core_if->dev_if->
-+						   dev_global_regs->dsts);
-+				ep->frame_num = dsts.b.soffn + ep->bInterval;
-+				if (ep->frame_num > 0x3FFF) {
-+					ep->frm_overrun = 1;
-+					ep->frame_num &= 0x3FFF;
-+				} else
-+					ep->frm_overrun = 0;
-+				if (ep->frame_num & 0x1) {
-+					depctl.b.setd1pid = 1;
-+				} else {
-+					depctl.b.setd0pid = 1;
-+				}
-+			}
-+		}
-+		/* EP enable, IN data in FIFO */
-+		depctl.b.cnak = 1;
-+		depctl.b.epena = 1;
-+		DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+	} else {
-+		/* OUT endpoint */
-+		dwc_otg_dev_out_ep_regs_t *out_regs =
-+		    core_if->dev_if->out_ep_regs[ep->num];
-+
-+		depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
-+		deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
-+
-+		if (!core_if->dma_desc_enable) {
-+			if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
-+				ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
-+				ep->maxxfer : (ep->total_len - ep->xfer_len);
-+                else
-+					ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
-+					- ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
-+		}
-+
-+		/* Program the transfer size and packet count as follows:
-+		 *
-+		 *      pktcnt = N
-+		 *      xfersize = N * maxpacket
-+		 */
-+		if ((ep->xfer_len - ep->xfer_count) == 0) {
-+			/* Zero Length Packet */
-+			deptsiz.b.xfersize = ep->maxpacket;
-+			deptsiz.b.pktcnt = 1;
-+		} else {
-+			deptsiz.b.pktcnt =
-+			    (ep->xfer_len - ep->xfer_count +
-+			     (ep->maxpacket - 1)) / ep->maxpacket;
-+			if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
-+				deptsiz.b.pktcnt = MAX_PKT_CNT;
-+			}
-+			if (!core_if->dma_desc_enable) {
-+				ep->xfer_len =
-+					deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
-+			}
-+			deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
-+		}
-+
-+		DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
-+			    ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+
-+		if (core_if->dma_enable) {
-+			if (!core_if->dma_desc_enable) {
-+				DWC_WRITE_REG32(&out_regs->doeptsiz,
-+						deptsiz.d32);
-+
-+				DWC_WRITE_REG32(&(out_regs->doepdma),
-+						(uint32_t) ep->dma_addr);
-+			} else {
-+#ifdef DWC_UTE_CFI
-+				/* The descriptor chain should be already initialized by now */
-+				if (ep->buff_mode != BM_STANDARD) {
-+					DWC_WRITE_REG32(&out_regs->doepdma,
-+							ep->descs_dma_addr);
-+				} else {
-+#endif
-+					/** This is used for interrupt out transfers*/
-+					if (!ep->xfer_len)
-+						ep->xfer_len = ep->total_len;
-+					init_dma_desc_chain(core_if, ep);
-+
-+					if (core_if->core_params->dev_out_nak) {
-+						if (ep->type == DWC_OTG_EP_TYPE_BULK) {
-+							deptsiz.b.pktcnt = (ep->total_len +
-+								(ep->maxpacket - 1)) / ep->maxpacket;
-+							deptsiz.b.xfersize = ep->total_len;
-+							/* Remember initial value of doeptsiz */
-+							core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
-+							DWC_WRITE_REG32(&out_regs->doeptsiz,
-+								deptsiz.d32);
-+						}
-+					}
-+				/** DOEPDMAn Register write */
-+					DWC_WRITE_REG32(&out_regs->doepdma,
-+							ep->dma_desc_addr);
-+#ifdef DWC_UTE_CFI
-+				}
-+#endif
-+			}
-+		} else {
-+			DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+		}
-+
-+		if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+			dsts_data_t dsts = {.d32 = 0};
-+			if (ep->bInterval == 1) {
-+				dsts.d32 =
-+				    DWC_READ_REG32(&core_if->dev_if->
-+						   dev_global_regs->dsts);
-+				ep->frame_num = dsts.b.soffn + ep->bInterval;
-+				if (ep->frame_num > 0x3FFF) {
-+					ep->frm_overrun = 1;
-+					ep->frame_num &= 0x3FFF;
-+				} else
-+					ep->frm_overrun = 0;
-+
-+				if (ep->frame_num & 0x1) {
-+					depctl.b.setd1pid = 1;
-+				} else {
-+					depctl.b.setd0pid = 1;
-+				}
-+			}
-+		}
-+
-+		/* EP enable */
-+		depctl.b.cnak = 1;
-+		depctl.b.epena = 1;
-+
-+		DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+		DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
-+			    DWC_READ_REG32(&out_regs->doepctl),
-+			    DWC_READ_REG32(&out_regs->doeptsiz));
-+		DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
-+			    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
-+					   daintmsk),
-+			    DWC_READ_REG32(&core_if->core_global_regs->
-+					   gintmsk));
-+
-+		/* Timer is scheduling only for out bulk transfers for
-+		 * "Device DDMA OUT NAK Enhancement" feature to inform user
-+		 * about received data payload in case of timeout
-+		 */
-+		if (core_if->core_params->dev_out_nak) {
-+			if (ep->type == DWC_OTG_EP_TYPE_BULK) {
-+				core_if->ep_xfer_info[ep->num].core_if = core_if;
-+				core_if->ep_xfer_info[ep->num].ep = ep;
-+				core_if->ep_xfer_info[ep->num].state = 1;
-+
-+				/* Start a timer for this transfer. */
-+				DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
-+			}
-+		}
-+	}
-+}
-+
-+/**
-+ * This function setup a zero length transfer in Buffer DMA and
-+ * Slave modes for usb requests with zero field set
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+
-+	depctl_data_t depctl;
-+	deptsiz_data_t deptsiz;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
-+	DWC_PRINTF("zero length transfer is called\n");
-+
-+	/* IN endpoint */
-+	if (ep->is_in == 1) {
-+		dwc_otg_dev_in_ep_regs_t *in_regs =
-+		    core_if->dev_if->in_ep_regs[ep->num];
-+
-+		depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
-+		deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
-+
-+		deptsiz.b.xfersize = 0;
-+		deptsiz.b.pktcnt = 1;
-+
-+		/* Write the DMA register */
-+		if (core_if->dma_enable) {
-+			if (core_if->dma_desc_enable == 0) {
-+				deptsiz.b.mc = 1;
-+				DWC_WRITE_REG32(&in_regs->dieptsiz,
-+						deptsiz.d32);
-+				DWC_WRITE_REG32(&(in_regs->diepdma),
-+						(uint32_t) ep->dma_addr);
-+			}
-+		} else {
-+			DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+			/**
-+			 * Enable the Non-Periodic Tx FIFO empty interrupt,
-+			 * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
-+			 * the data will be written into the fifo by the ISR.
-+			 */
-+			if (core_if->en_multiple_tx_fifo == 0) {
-+				intr_mask.b.nptxfempty = 1;
-+				DWC_MODIFY_REG32(&core_if->
-+						 core_global_regs->gintmsk,
-+						 intr_mask.d32, intr_mask.d32);
-+			} else {
-+				/* Enable the Tx FIFO Empty Interrupt for this EP */
-+				if (ep->xfer_len > 0) {
-+					uint32_t fifoemptymsk = 0;
-+					fifoemptymsk = 1 << ep->num;
-+					DWC_MODIFY_REG32(&core_if->
-+							 dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+							 0, fifoemptymsk);
-+				}
-+			}
-+		}
-+
-+		if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+			depctl.b.nextep = core_if->nextep_seq[ep->num];
-+		/* EP enable, IN data in FIFO */
-+		depctl.b.cnak = 1;
-+		depctl.b.epena = 1;
-+		DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+	} else {
-+		/* OUT endpoint */
-+		dwc_otg_dev_out_ep_regs_t *out_regs =
-+		    core_if->dev_if->out_ep_regs[ep->num];
-+
-+		depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
-+		deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
-+
-+		/* Zero Length Packet */
-+		deptsiz.b.xfersize = ep->maxpacket;
-+		deptsiz.b.pktcnt = 1;
-+
-+		if (core_if->dma_enable) {
-+			if (!core_if->dma_desc_enable) {
-+				DWC_WRITE_REG32(&out_regs->doeptsiz,
-+						deptsiz.d32);
-+
-+				DWC_WRITE_REG32(&(out_regs->doepdma),
-+						(uint32_t) ep->dma_addr);
-+			}
-+		} else {
-+			DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+		}
-+
-+		/* EP enable */
-+		depctl.b.cnak = 1;
-+		depctl.b.epena = 1;
-+
-+		DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+	}
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for EP0 and starts
-+ * the transfer.  For an IN transfer, the packets will be loaded into
-+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
-+ * unloaded from the Rx FIFO in the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	depctl_data_t depctl;
-+	deptsiz0_data_t deptsiz;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+
-+	DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
-+		    "xfer_buff=%p start_xfer_buff=%p \n",
-+		    ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
-+		    ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
-+
-+	ep->total_len = ep->xfer_len;
-+
-+	/* IN endpoint */
-+	if (ep->is_in == 1) {
-+		dwc_otg_dev_in_ep_regs_t *in_regs =
-+		    core_if->dev_if->in_ep_regs[0];
-+
-+		gnptxsts_data_t gtxstatus;
-+
-+		if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+			depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+			if (depctl.b.epena)
-+				return;
-+		}
-+
-+		gtxstatus.d32 =
-+		    DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+
-+		/* If dedicated FIFO every time flush fifo before enable ep*/
-+		if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
-+			dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
-+
-+		if (core_if->en_multiple_tx_fifo == 0
-+		    && gtxstatus.b.nptxqspcavail == 0
-+		    && !core_if->dma_enable) {
-+#ifdef DEBUG
-+			deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+			DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
-+				    DWC_READ_REG32(&in_regs->diepctl));
-+			DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
-+				    deptsiz.d32,
-+				    deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+			DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
-+				   gtxstatus.d32);
-+#endif
-+			return;
-+		}
-+
-+		depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+		deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+
-+		/* Zero Length Packet? */
-+		if (ep->xfer_len == 0) {
-+			deptsiz.b.xfersize = 0;
-+			deptsiz.b.pktcnt = 1;
-+		} else {
-+			/* Program the transfer size and packet count
-+			 *      as follows: xfersize = N * maxpacket +
-+			 *      short_packet pktcnt = N + (short_packet
-+			 *      exist ? 1 : 0)
-+			 */
-+			if (ep->xfer_len > ep->maxpacket) {
-+				ep->xfer_len = ep->maxpacket;
-+				deptsiz.b.xfersize = ep->maxpacket;
-+			} else {
-+				deptsiz.b.xfersize = ep->xfer_len;
-+			}
-+			deptsiz.b.pktcnt = 1;
-+
-+		}
-+		DWC_DEBUGPL(DBG_PCDV,
-+			    "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
-+			    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+			    deptsiz.d32);
-+
-+		/* Write the DMA register */
-+		if (core_if->dma_enable) {
-+			if (core_if->dma_desc_enable == 0) {
-+				DWC_WRITE_REG32(&in_regs->dieptsiz,
-+						deptsiz.d32);
-+
-+				DWC_WRITE_REG32(&(in_regs->diepdma),
-+						(uint32_t) ep->dma_addr);
-+			} else {
-+				dma_desc = core_if->dev_if->in_desc_addr;
-+
-+				/** DMA Descriptor Setup */
-+				dma_desc->status.b.bs = BS_HOST_BUSY;
-+				dma_desc->status.b.l = 1;
-+				dma_desc->status.b.ioc = 1;
-+				dma_desc->status.b.sp =
-+				    (ep->xfer_len == ep->maxpacket) ? 0 : 1;
-+				dma_desc->status.b.bytes = ep->xfer_len;
-+				dma_desc->buf = ep->dma_addr;
-+				dma_desc->status.b.sts = 0;
-+				dma_desc->status.b.bs = BS_HOST_READY;
-+
-+				/** DIEPDMA0 Register write */
-+				DWC_WRITE_REG32(&in_regs->diepdma,
-+						core_if->
-+						dev_if->dma_in_desc_addr);
-+			}
-+		} else {
-+			DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+		}
-+
-+		if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+			depctl.b.nextep = core_if->nextep_seq[ep->num];
-+		/* EP enable, IN data in FIFO */
-+		depctl.b.cnak = 1;
-+		depctl.b.epena = 1;
-+		DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+		/**
-+		 * Enable the Non-Periodic Tx FIFO empty interrupt, the
-+		 * data will be written into the fifo by the ISR.
-+		 */
-+		if (!core_if->dma_enable) {
-+			if (core_if->en_multiple_tx_fifo == 0) {
-+				intr_mask.b.nptxfempty = 1;
-+				DWC_MODIFY_REG32(&core_if->
-+						 core_global_regs->gintmsk,
-+						 intr_mask.d32, intr_mask.d32);
-+			} else {
-+				/* Enable the Tx FIFO Empty Interrupt for this EP */
-+				if (ep->xfer_len > 0) {
-+					uint32_t fifoemptymsk = 0;
-+					fifoemptymsk |= 1 << ep->num;
-+					DWC_MODIFY_REG32(&core_if->
-+							 dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+							 0, fifoemptymsk);
-+				}
-+			}
-+		}
-+	} else {
-+		/* OUT endpoint */
-+		dwc_otg_dev_out_ep_regs_t *out_regs =
-+		    core_if->dev_if->out_ep_regs[0];
-+
-+		depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
-+		deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
-+
-+		/* Program the transfer size and packet count as follows:
-+		 *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
-+		 *      pktcnt = N                                                                                      */
-+		/* Zero Length Packet */
-+		deptsiz.b.xfersize = ep->maxpacket;
-+		deptsiz.b.pktcnt = 1;
-+		if (core_if->snpsid >= OTG_CORE_REV_3_00a)
-+			deptsiz.b.supcnt = 3;
-+
-+		DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
-+			    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+
-+		if (core_if->dma_enable) {
-+			if (!core_if->dma_desc_enable) {
-+				DWC_WRITE_REG32(&out_regs->doeptsiz,
-+						deptsiz.d32);
-+
-+				DWC_WRITE_REG32(&(out_regs->doepdma),
-+						(uint32_t) ep->dma_addr);
-+			} else {
-+				dma_desc = core_if->dev_if->out_desc_addr;
-+
-+				/** DMA Descriptor Setup */
-+				dma_desc->status.b.bs = BS_HOST_BUSY;
-+				if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+					dma_desc->status.b.mtrf = 0;
-+					dma_desc->status.b.sr = 0;
-+				}
-+				dma_desc->status.b.l = 1;
-+				dma_desc->status.b.ioc = 1;
-+				dma_desc->status.b.bytes = ep->maxpacket;
-+				dma_desc->buf = ep->dma_addr;
-+				dma_desc->status.b.sts = 0;
-+				dma_desc->status.b.bs = BS_HOST_READY;
-+
-+				/** DOEPDMA0 Register write */
-+				DWC_WRITE_REG32(&out_regs->doepdma,
-+						core_if->dev_if->
-+						dma_out_desc_addr);
-+			}
-+		} else {
-+			DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+		}
-+
-+		/* EP enable */
-+		depctl.b.cnak = 1;
-+		depctl.b.epena = 1;
-+		DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
-+	}
-+}
-+
-+/**
-+ * This function continues control IN transfers started by
-+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
-+ * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
-+ * bit for the packet count.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP0 data.
-+ */
-+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	depctl_data_t depctl;
-+	deptsiz0_data_t deptsiz;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+
-+	if (ep->is_in == 1) {
-+		dwc_otg_dev_in_ep_regs_t *in_regs =
-+		    core_if->dev_if->in_ep_regs[0];
-+		gnptxsts_data_t tx_status = {.d32 = 0 };
-+
-+		tx_status.d32 =
-+		    DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
-+		/** @todo Should there be check for room in the Tx
-+		 * Status Queue.  If not remove the code above this comment. */
-+
-+		depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
-+		deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
-+
-+		/* Program the transfer size and packet count
-+		 *      as follows: xfersize = N * maxpacket +
-+		 *      short_packet pktcnt = N + (short_packet
-+		 *      exist ? 1 : 0)
-+		 */
-+
-+		if (core_if->dma_desc_enable == 0) {
-+			deptsiz.b.xfersize =
-+			    (ep->total_len - ep->xfer_count) >
-+			    ep->maxpacket ? ep->maxpacket : (ep->total_len -
-+							     ep->xfer_count);
-+			deptsiz.b.pktcnt = 1;
-+			if (core_if->dma_enable == 0) {
-+				ep->xfer_len += deptsiz.b.xfersize;
-+			} else {
-+				ep->xfer_len = deptsiz.b.xfersize;
-+			}
-+			DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
-+		} else {
-+			ep->xfer_len =
-+			    (ep->total_len - ep->xfer_count) >
-+			    ep->maxpacket ? ep->maxpacket : (ep->total_len -
-+							     ep->xfer_count);
-+
-+			dma_desc = core_if->dev_if->in_desc_addr;
-+
-+			/** DMA Descriptor Setup */
-+			dma_desc->status.b.bs = BS_HOST_BUSY;
-+			dma_desc->status.b.l = 1;
-+			dma_desc->status.b.ioc = 1;
-+			dma_desc->status.b.sp =
-+			    (ep->xfer_len == ep->maxpacket) ? 0 : 1;
-+			dma_desc->status.b.bytes = ep->xfer_len;
-+			dma_desc->buf = ep->dma_addr;
-+			dma_desc->status.b.sts = 0;
-+			dma_desc->status.b.bs = BS_HOST_READY;
-+
-+			/** DIEPDMA0 Register write */
-+			DWC_WRITE_REG32(&in_regs->diepdma,
-+					core_if->dev_if->dma_in_desc_addr);
-+		}
-+
-+		DWC_DEBUGPL(DBG_PCDV,
-+			    "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
-+			    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+			    deptsiz.d32);
-+
-+		/* Write the DMA register */
-+		if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
-+			if (core_if->dma_desc_enable == 0)
-+				DWC_WRITE_REG32(&(in_regs->diepdma),
-+						(uint32_t) ep->dma_addr);
-+		}
-+		if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
-+			depctl.b.nextep = core_if->nextep_seq[ep->num];
-+		/* EP enable, IN data in FIFO */
-+		depctl.b.cnak = 1;
-+		depctl.b.epena = 1;
-+		DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
-+
-+		/**
-+		 * Enable the Non-Periodic Tx FIFO empty interrupt, the
-+		 * data will be written into the fifo by the ISR.
-+		 */
-+		if (!core_if->dma_enable) {
-+			if (core_if->en_multiple_tx_fifo == 0) {
-+				/* First clear it from GINTSTS */
-+				intr_mask.b.nptxfempty = 1;
-+				DWC_MODIFY_REG32(&core_if->
-+						 core_global_regs->gintmsk,
-+						 intr_mask.d32, intr_mask.d32);
-+
-+			} else {
-+				/* Enable the Tx FIFO Empty Interrupt for this EP */
-+				if (ep->xfer_len > 0) {
-+					uint32_t fifoemptymsk = 0;
-+					fifoemptymsk |= 1 << ep->num;
-+					DWC_MODIFY_REG32(&core_if->
-+							 dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+							 0, fifoemptymsk);
-+				}
-+			}
-+		}
-+	} else {
-+		dwc_otg_dev_out_ep_regs_t *out_regs =
-+		    core_if->dev_if->out_ep_regs[0];
-+
-+		depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
-+		deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
-+
-+		/* Program the transfer size and packet count
-+		 *      as follows: xfersize = N * maxpacket +
-+		 *      short_packet pktcnt = N + (short_packet
-+		 *      exist ? 1 : 0)
-+		 */
-+		deptsiz.b.xfersize = ep->maxpacket;
-+		deptsiz.b.pktcnt = 1;
-+
-+		if (core_if->dma_desc_enable == 0) {
-+			DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
-+		} else {
-+			dma_desc = core_if->dev_if->out_desc_addr;
-+
-+			/** DMA Descriptor Setup */
-+			dma_desc->status.b.bs = BS_HOST_BUSY;
-+			dma_desc->status.b.l = 1;
-+			dma_desc->status.b.ioc = 1;
-+			dma_desc->status.b.bytes = ep->maxpacket;
-+			dma_desc->buf = ep->dma_addr;
-+			dma_desc->status.b.sts = 0;
-+			dma_desc->status.b.bs = BS_HOST_READY;
-+
-+			/** DOEPDMA0 Register write */
-+			DWC_WRITE_REG32(&out_regs->doepdma,
-+					core_if->dev_if->dma_out_desc_addr);
-+		}
-+
-+		DWC_DEBUGPL(DBG_PCDV,
-+			    "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
-+			    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
-+			    deptsiz.d32);
-+
-+		/* Write the DMA register */
-+		if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
-+			if (core_if->dma_desc_enable == 0)
-+				DWC_WRITE_REG32(&(out_regs->doepdma),
-+						(uint32_t) ep->dma_addr);
-+
-+		}
-+
-+		/* EP enable, IN data in FIFO */
-+		depctl.b.cnak = 1;
-+		depctl.b.epena = 1;
-+		DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
-+
-+	}
-+}
-+
-+#ifdef DEBUG
-+void dump_msg(const u8 * buf, unsigned int length)
-+{
-+	unsigned int start, num, i;
-+	char line[52], *p;
-+
-+	if (length >= 512)
-+		return;
-+	start = 0;
-+	while (length > 0) {
-+		num = length < 16u ? length : 16u;
-+		p = line;
-+		for (i = 0; i < num; ++i) {
-+			if (i == 8)
-+				*p++ = ' ';
-+			DWC_SPRINTF(p, " %02x", buf[i]);
-+			p += 3;
-+		}
-+		*p = 0;
-+		DWC_PRINTF("%6x: %s\n", start, line);
-+		buf += num;
-+		start += num;
-+		length -= num;
-+	}
-+}
-+#else
-+static inline void dump_msg(const u8 * buf, unsigned int length)
-+{
-+}
-+#endif
-+
-+/**
-+ * This function writes a packet into the Tx FIFO associated with the
-+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written.  For
-+ * periodic EPs the periodic Tx FIFO associated with the EP is written
-+ * with all packets for the next micro-frame.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to write packet for.
-+ * @param dma Indicates if DMA is being used.
-+ */
-+void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
-+			     int dma)
-+{
-+	/**
-+	 * The buffer is padded to DWORD on a per packet basis in
-+	 * slave/dma mode if the MPS is not DWORD aligned. The last
-+	 * packet, if short, is also padded to a multiple of DWORD.
-+	 *
-+	 * ep->xfer_buff always starts DWORD aligned in memory and is a
-+	 * multiple of DWORD in length
-+	 *
-+	 * ep->xfer_len can be any number of bytes
-+	 *
-+	 * ep->xfer_count is a multiple of ep->maxpacket until the last
-+	 *	packet
-+	 *
-+	 * FIFO access is DWORD */
-+
-+	uint32_t i;
-+	uint32_t byte_count;
-+	uint32_t dword_count;
-+	uint32_t *fifo;
-+	uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
-+
-+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
-+		    ep);
-+	if (ep->xfer_count >= ep->xfer_len) {
-+		DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
-+		return;
-+	}
-+
-+	/* Find the byte length of the packet either short packet or MPS */
-+	if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
-+		byte_count = ep->xfer_len - ep->xfer_count;
-+	} else {
-+		byte_count = ep->maxpacket;
-+	}
-+
-+	/* Find the DWORD length, padded by extra bytes as neccessary if MPS
-+	 * is not a multiple of DWORD */
-+	dword_count = (byte_count + 3) / 4;
-+
-+#ifdef VERBOSE
-+	dump_msg(ep->xfer_buff, byte_count);
-+#endif
-+
-+	/**@todo NGS Where are the Periodic Tx FIFO addresses
-+	 * intialized?	What should this be? */
-+
-+	fifo = core_if->data_fifo[ep->num];
-+
-+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
-+		    fifo, data_buff, *data_buff, byte_count);
-+
-+	if (!dma) {
-+		for (i = 0; i < dword_count; i++, data_buff++) {
-+			DWC_WRITE_REG32(fifo, *data_buff);
-+		}
-+	}
-+
-+	ep->xfer_count += byte_count;
-+	ep->xfer_buff += byte_count;
-+	ep->dma_addr += byte_count;
-+}
-+
-+/**
-+ * Set the EP STALL.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to set the stall on.
-+ */
-+void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	depctl_data_t depctl;
-+	volatile uint32_t *depctl_addr;
-+
-+	DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
-+		    (ep->is_in ? "IN" : "OUT"));
-+
-+	if (ep->is_in == 1) {
-+		depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
-+		depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+		/* set the disable and stall bits */
-+		if (depctl.b.epena) {
-+			depctl.b.epdis = 1;
-+		}
-+		depctl.b.stall = 1;
-+		DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+	} else {
-+		depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
-+		depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+		/* set the stall bit */
-+		depctl.b.stall = 1;
-+		DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
-+
-+	return;
-+}
-+
-+/**
-+ * Clear the EP STALL.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to clear stall from.
-+ */
-+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	depctl_data_t depctl;
-+	volatile uint32_t *depctl_addr;
-+
-+	DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
-+		    (ep->is_in ? "IN" : "OUT"));
-+
-+	if (ep->is_in == 1) {
-+		depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
-+	} else {
-+		depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
-+	}
-+
-+	depctl.d32 = DWC_READ_REG32(depctl_addr);
-+
-+	/* clear the stall bits */
-+	depctl.b.stall = 0;
-+
-+	/*
-+	 * USB Spec 9.4.5: For endpoints using data toggle, regardless
-+	 * of whether an endpoint has the Halt feature set, a
-+	 * ClearFeature(ENDPOINT_HALT) request always results in the
-+	 * data toggle being reinitialized to DATA0.
-+	 */
-+	if (ep->type == DWC_OTG_EP_TYPE_INTR ||
-+	    ep->type == DWC_OTG_EP_TYPE_BULK) {
-+		depctl.b.setd0pid = 1;	/* DATA0 */
-+	}
-+
-+	DWC_WRITE_REG32(depctl_addr, depctl.d32);
-+	DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
-+	return;
-+}
-+
-+/**
-+ * This function reads a packet from the Rx FIFO into the destination
-+ * buffer. To read SETUP data use dwc_otg_read_setup_packet.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dest	  Destination buffer for the packet.
-+ * @param bytes  Number of bytes to copy to the destination.
-+ */
-+void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
-+			 uint8_t * dest, uint16_t bytes)
-+{
-+	int i;
-+	int word_count = (bytes + 3) / 4;
-+
-+	volatile uint32_t *fifo = core_if->data_fifo[0];
-+	uint32_t *data_buff = (uint32_t *) dest;
-+
-+	/**
-+	 * @todo Account for the case where _dest is not dword aligned. This
-+	 * requires reading data from the FIFO into a uint32_t temp buffer,
-+	 * then moving it into the data buffer.
-+	 */
-+
-+	DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
-+		    core_if, dest, bytes);
-+
-+	for (i = 0; i < word_count; i++, data_buff++) {
-+		*data_buff = DWC_READ_REG32(fifo);
-+	}
-+
-+	return;
-+}
-+
-+/**
-+ * This functions reads the device registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
-+{
-+	int i;
-+	volatile uint32_t *addr;
-+
-+	DWC_PRINTF("Device Global Registers\n");
-+	addr = &core_if->dev_if->dev_global_regs->dcfg;
-+	DWC_PRINTF("DCFG		 @0x%08lX : 0x%08X\n",
-+		   (unsigned long)addr, DWC_READ_REG32(addr));
-+	addr = &core_if->dev_if->dev_global_regs->dctl;
-+	DWC_PRINTF("DCTL		 @0x%08lX : 0x%08X\n",
-+		   (unsigned long)addr, DWC_READ_REG32(addr));
-+	addr = &core_if->dev_if->dev_global_regs->dsts;
-+	DWC_PRINTF("DSTS		 @0x%08lX : 0x%08X\n",
-+		   (unsigned long)addr, DWC_READ_REG32(addr));
-+	addr = &core_if->dev_if->dev_global_regs->diepmsk;
-+	DWC_PRINTF("DIEPMSK	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->dev_if->dev_global_regs->doepmsk;
-+	DWC_PRINTF("DOEPMSK	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->dev_if->dev_global_regs->daint;
-+	DWC_PRINTF("DAINT	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->dev_if->dev_global_regs->daintmsk;
-+	DWC_PRINTF("DAINTMSK	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->dev_if->dev_global_regs->dtknqr1;
-+	DWC_PRINTF("DTKNQR1	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
-+		addr = &core_if->dev_if->dev_global_regs->dtknqr2;
-+		DWC_PRINTF("DTKNQR2	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+	}
-+
-+	addr = &core_if->dev_if->dev_global_regs->dvbusdis;
-+	DWC_PRINTF("DVBUSID	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+
-+	addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
-+	DWC_PRINTF("DVBUSPULSE	@0x%08lX : 0x%08X\n",
-+		   (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+	addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
-+	DWC_PRINTF("DTKNQR3_DTHRCTL	 @0x%08lX : 0x%08X\n",
-+		   (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+	if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
-+		addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
-+		DWC_PRINTF("DTKNQR4	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+	}
-+
-+	addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
-+	DWC_PRINTF("FIFOEMPMSK	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+
-+	if (core_if->hwcfg2.b.multi_proc_int) {
-+
-+		addr = &core_if->dev_if->dev_global_regs->deachint;
-+		DWC_PRINTF("DEACHINT	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->dev_global_regs->deachintmsk;
-+		DWC_PRINTF("DEACHINTMSK	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+
-+		for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+			addr =
-+			    &core_if->dev_if->
-+			    dev_global_regs->diepeachintmsk[i];
-+			DWC_PRINTF("DIEPEACHINTMSK[%d]	 @0x%08lX : 0x%08X\n",
-+				   i, (unsigned long)addr,
-+				   DWC_READ_REG32(addr));
-+		}
-+
-+		for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+			addr =
-+			    &core_if->dev_if->
-+			    dev_global_regs->doepeachintmsk[i];
-+			DWC_PRINTF("DOEPEACHINTMSK[%d]	 @0x%08lX : 0x%08X\n",
-+				   i, (unsigned long)addr,
-+				   DWC_READ_REG32(addr));
-+		}
-+	}
-+
-+	for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+		DWC_PRINTF("Device IN EP %d Registers\n", i);
-+		addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
-+		DWC_PRINTF("DIEPCTL	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->in_ep_regs[i]->diepint;
-+		DWC_PRINTF("DIEPINT	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
-+		DWC_PRINTF("DIETSIZ	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
-+		DWC_PRINTF("DIEPDMA	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
-+		DWC_PRINTF("DTXFSTS	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
-+		DWC_PRINTF("DIEPDMAB	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
-+	}
-+
-+	for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
-+		DWC_PRINTF("Device OUT EP %d Registers\n", i);
-+		addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
-+		DWC_PRINTF("DOEPCTL	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->out_ep_regs[i]->doepint;
-+		DWC_PRINTF("DOEPINT	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
-+		DWC_PRINTF("DOETSIZ	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
-+		DWC_PRINTF("DOEPDMA	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		if (core_if->dma_enable) {	/* Don't access this register in SLAVE mode */
-+			addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
-+			DWC_PRINTF("DOEPDMAB	 @0x%08lX : 0x%08X\n",
-+				   (unsigned long)addr, DWC_READ_REG32(addr));
-+		}
-+
-+	}
-+}
-+
-+/**
-+ * This functions reads the SPRAM and prints its content
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
-+{
-+	volatile uint8_t *addr, *start_addr, *end_addr;
-+
-+	DWC_PRINTF("SPRAM Data:\n");
-+	start_addr = (void *)core_if->core_global_regs;
-+	DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
-+	start_addr += 0x00028000;
-+	end_addr = (void *)core_if->core_global_regs;
-+	end_addr += 0x000280e0;
-+
-+	for (addr = start_addr; addr < end_addr; addr += 16) {
-+		DWC_PRINTF
-+		    ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
-+		     (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
-+		     addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
-+		     addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
-+		    );
-+	}
-+
-+	return;
-+}
-+
-+/**
-+ * This function reads the host registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
-+{
-+	int i;
-+	volatile uint32_t *addr;
-+
-+	DWC_PRINTF("Host Global Registers\n");
-+	addr = &core_if->host_if->host_global_regs->hcfg;
-+	DWC_PRINTF("HCFG		 @0x%08lX : 0x%08X\n",
-+		   (unsigned long)addr, DWC_READ_REG32(addr));
-+	addr = &core_if->host_if->host_global_regs->hfir;
-+	DWC_PRINTF("HFIR		 @0x%08lX : 0x%08X\n",
-+		   (unsigned long)addr, DWC_READ_REG32(addr));
-+	addr = &core_if->host_if->host_global_regs->hfnum;
-+	DWC_PRINTF("HFNUM	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->host_if->host_global_regs->hptxsts;
-+	DWC_PRINTF("HPTXSTS	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->host_if->host_global_regs->haint;
-+	DWC_PRINTF("HAINT	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->host_if->host_global_regs->haintmsk;
-+	DWC_PRINTF("HAINTMSK	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	if (core_if->dma_desc_enable) {
-+		addr = &core_if->host_if->host_global_regs->hflbaddr;
-+		DWC_PRINTF("HFLBADDR	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+	}
-+
-+	addr = core_if->host_if->hprt0;
-+	DWC_PRINTF("HPRT0	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+
-+	for (i = 0; i < core_if->core_params->host_channels; i++) {
-+		DWC_PRINTF("Host Channel %d Specific Registers\n", i);
-+		addr = &core_if->host_if->hc_regs[i]->hcchar;
-+		DWC_PRINTF("HCCHAR	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->host_if->hc_regs[i]->hcsplt;
-+		DWC_PRINTF("HCSPLT	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->host_if->hc_regs[i]->hcint;
-+		DWC_PRINTF("HCINT	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->host_if->hc_regs[i]->hcintmsk;
-+		DWC_PRINTF("HCINTMSK	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->host_if->hc_regs[i]->hctsiz;
-+		DWC_PRINTF("HCTSIZ	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		addr = &core_if->host_if->hc_regs[i]->hcdma;
-+		DWC_PRINTF("HCDMA	 @0x%08lX : 0x%08X\n",
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+		if (core_if->dma_desc_enable) {
-+			addr = &core_if->host_if->hc_regs[i]->hcdmab;
-+			DWC_PRINTF("HCDMAB	 @0x%08lX : 0x%08X\n",
-+				   (unsigned long)addr, DWC_READ_REG32(addr));
-+		}
-+
-+	}
-+	return;
-+}
-+
-+/**
-+ * This function reads the core global registers and prints them
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
-+{
-+	int i, ep_num;
-+	volatile uint32_t *addr;
-+	char *txfsiz;
-+
-+	DWC_PRINTF("Core Global Registers\n");
-+	addr = &core_if->core_global_regs->gotgctl;
-+	DWC_PRINTF("GOTGCTL	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gotgint;
-+	DWC_PRINTF("GOTGINT	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gahbcfg;
-+	DWC_PRINTF("GAHBCFG	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gusbcfg;
-+	DWC_PRINTF("GUSBCFG	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->grstctl;
-+	DWC_PRINTF("GRSTCTL	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gintsts;
-+	DWC_PRINTF("GINTSTS	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gintmsk;
-+	DWC_PRINTF("GINTMSK	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->grxstsr;
-+	DWC_PRINTF("GRXSTSR	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->grxfsiz;
-+	DWC_PRINTF("GRXFSIZ	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gnptxfsiz;
-+	DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gnptxsts;
-+	DWC_PRINTF("GNPTXSTS	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gi2cctl;
-+	DWC_PRINTF("GI2CCTL	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gpvndctl;
-+	DWC_PRINTF("GPVNDCTL	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->ggpio;
-+	DWC_PRINTF("GGPIO	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->guid;
-+	DWC_PRINTF("GUID		 @0x%08lX : 0x%08X\n",
-+		   (unsigned long)addr, DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gsnpsid;
-+	DWC_PRINTF("GSNPSID	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->ghwcfg1;
-+	DWC_PRINTF("GHWCFG1	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->ghwcfg2;
-+	DWC_PRINTF("GHWCFG2	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->ghwcfg3;
-+	DWC_PRINTF("GHWCFG3	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->ghwcfg4;
-+	DWC_PRINTF("GHWCFG4	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->glpmcfg;
-+	DWC_PRINTF("GLPMCFG	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gpwrdn;
-+	DWC_PRINTF("GPWRDN	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->gdfifocfg;
-+	DWC_PRINTF("GDFIFOCFG	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+	addr = &core_if->core_global_regs->adpctl;
-+	DWC_PRINTF("ADPCTL	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   dwc_otg_adp_read_reg(core_if));
-+	addr = &core_if->core_global_regs->hptxfsiz;
-+	DWC_PRINTF("HPTXFSIZ	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+
-+	if (core_if->en_multiple_tx_fifo == 0) {
-+		ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
-+		txfsiz = "DPTXFSIZ";
-+	} else {
-+		ep_num = core_if->hwcfg4.b.num_in_eps;
-+		txfsiz = "DIENPTXF";
-+	}
-+	for (i = 0; i < ep_num; i++) {
-+		addr = &core_if->core_global_regs->dtxfsiz[i];
-+		DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
-+			   (unsigned long)addr, DWC_READ_REG32(addr));
-+	}
-+	addr = core_if->pcgcctl;
-+	DWC_PRINTF("PCGCCTL	 @0x%08lX : 0x%08X\n", (unsigned long)addr,
-+		   DWC_READ_REG32(addr));
-+}
-+
-+/**
-+ * Flush a Tx FIFO.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param num Tx FIFO to flush.
-+ */
-+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
-+{
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	volatile grstctl_t greset = {.d32 = 0 };
-+	int count = 0;
-+
-+	DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
-+
-+	greset.b.txfflsh = 1;
-+	greset.b.txfnum = num;
-+	DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+
-+	do {
-+		greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+		if (++count > 10000) {
-+			DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
-+				 __func__, greset.d32,
-+				 DWC_READ_REG32(&global_regs->gnptxsts));
-+			break;
-+		}
-+		dwc_udelay(1);
-+	} while (greset.b.txfflsh == 1);
-+
-+	/* Wait for 3 PHY Clocks */
-+	dwc_udelay(1);
-+}
-+
-+/**
-+ * Flush Rx FIFO.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	volatile grstctl_t greset = {.d32 = 0 };
-+	int count = 0;
-+
-+	DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
-+	/*
-+	 *
-+	 */
-+	greset.b.rxfflsh = 1;
-+	DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+
-+	do {
-+		greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+		if (++count > 10000) {
-+			DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
-+				 greset.d32);
-+			break;
-+		}
-+		dwc_udelay(1);
-+	} while (greset.b.rxfflsh == 1);
-+
-+	/* Wait for 3 PHY Clocks */
-+	dwc_udelay(1);
-+}
-+
-+/**
-+ * Do core a soft reset of the core.  Be careful with this because it
-+ * resets all the internal state machines of the core.
-+ */
-+void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	volatile grstctl_t greset = {.d32 = 0 };
-+	int count = 0;
-+
-+	DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
-+	/* Wait for AHB master IDLE state. */
-+	do {
-+		dwc_udelay(10);
-+		greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+		if (++count > 100000) {
-+			DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
-+				 greset.d32);
-+			return;
-+		}
-+	}
-+	while (greset.b.ahbidle == 0);
-+
-+	/* Core Soft Reset */
-+	count = 0;
-+	greset.b.csftrst = 1;
-+	DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
-+	do {
-+		greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
-+		if (++count > 10000) {
-+			DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
-+				 __func__, greset.d32);
-+			break;
-+		}
-+		dwc_udelay(1);
-+	}
-+	while (greset.b.csftrst == 1);
-+
-+	/* Wait for 3 PHY Clocks */
-+	dwc_mdelay(100);
-+}
-+
-+uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
-+{
-+	return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
-+}
-+
-+uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
-+{
-+	return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
-+}
-+
-+/**
-+ * Register HCD callbacks. The callbacks are used to start and stop
-+ * the HCD for interrupt processing.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param cb the HCD callback structure.
-+ * @param p pointer to be passed to callback function (usb_hcd*).
-+ */
-+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
-+					dwc_otg_cil_callbacks_t * cb, void *p)
-+{
-+	core_if->hcd_cb = cb;
-+	cb->p = p;
-+}
-+
-+/**
-+ * Register PCD callbacks. The callbacks are used to start and stop
-+ * the PCD for interrupt processing.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param cb the PCD callback structure.
-+ * @param p pointer to be passed to callback function (pcd*).
-+ */
-+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
-+					dwc_otg_cil_callbacks_t * cb, void *p)
-+{
-+	core_if->pcd_cb = cb;
-+	cb->p = p;
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function writes isoc data per 1 (micro)frame into tx fifo
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	dwc_otg_dev_in_ep_regs_t *ep_regs;
-+	dtxfsts_data_t txstatus = {.d32 = 0 };
-+	uint32_t len = 0;
-+	uint32_t dwords;
-+
-+	ep->xfer_len = ep->data_per_frame;
-+	ep->xfer_count = 0;
-+
-+	ep_regs = core_if->dev_if->in_ep_regs[ep->num];
-+
-+	len = ep->xfer_len - ep->xfer_count;
-+
-+	if (len > ep->maxpacket) {
-+		len = ep->maxpacket;
-+	}
-+
-+	dwords = (len + 3) / 4;
-+
-+	/* While there is space in the queue and space in the FIFO and
-+	 * More data to tranfer, Write packets to the Tx FIFO */
-+	txstatus.d32 =
-+	    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
-+	DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
-+
-+	while (txstatus.b.txfspcavail > dwords &&
-+	       ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
-+		/* Write the FIFO */
-+		dwc_otg_ep_write_packet(core_if, ep, 0);
-+
-+		len = ep->xfer_len - ep->xfer_count;
-+		if (len > ep->maxpacket) {
-+			len = ep->maxpacket;
-+		}
-+
-+		dwords = (len + 3) / 4;
-+		txstatus.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+				   dtxfsts);
-+		DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
-+			    txstatus.d32);
-+	}
-+}
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
-+				       dwc_ep_t * ep)
-+{
-+	deptsiz_data_t deptsiz = {.d32 = 0 };
-+	depctl_data_t depctl = {.d32 = 0 };
-+	dsts_data_t dsts = {.d32 = 0 };
-+	volatile uint32_t *addr;
-+
-+	if (ep->is_in) {
-+		addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+	} else {
-+		addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+	}
-+
-+	ep->xfer_len = ep->data_per_frame;
-+	ep->xfer_count = 0;
-+	ep->xfer_buff = ep->cur_pkt_addr;
-+	ep->dma_addr = ep->cur_pkt_dma_addr;
-+
-+	if (ep->is_in) {
-+		/* Program the transfer size and packet count
-+		 *      as follows: xfersize = N * maxpacket +
-+		 *      short_packet pktcnt = N + (short_packet
-+		 *      exist ? 1 : 0)
-+		 */
-+		deptsiz.b.xfersize = ep->xfer_len;
-+		deptsiz.b.pktcnt =
-+		    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+		deptsiz.b.mc = deptsiz.b.pktcnt;
-+		DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
-+				deptsiz.d32);
-+
-+		/* Write the DMA register */
-+		if (core_if->dma_enable) {
-+			DWC_WRITE_REG32(&
-+					(core_if->dev_if->in_ep_regs[ep->num]->
-+					 diepdma), (uint32_t) ep->dma_addr);
-+		}
-+	} else {
-+		deptsiz.b.pktcnt =
-+		    (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
-+		deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+
-+		DWC_WRITE_REG32(&core_if->dev_if->
-+				out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
-+
-+		if (core_if->dma_enable) {
-+			DWC_WRITE_REG32(&
-+					(core_if->dev_if->
-+					 out_ep_regs[ep->num]->doepdma),
-+					(uint32_t) ep->dma_addr);
-+		}
-+	}
-+
-+	/** Enable endpoint, clear nak  */
-+
-+	depctl.d32 = 0;
-+	if (ep->bInterval == 1) {
-+		dsts.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+		ep->next_frame = dsts.b.soffn + ep->bInterval;
-+
-+		if (ep->next_frame & 0x1) {
-+			depctl.b.setd1pid = 1;
-+		} else {
-+			depctl.b.setd0pid = 1;
-+		}
-+	} else {
-+		ep->next_frame += ep->bInterval;
-+
-+		if (ep->next_frame & 0x1) {
-+			depctl.b.setd1pid = 1;
-+		} else {
-+			depctl.b.setd0pid = 1;
-+		}
-+	}
-+	depctl.b.epena = 1;
-+	depctl.b.cnak = 1;
-+
-+	DWC_MODIFY_REG32(addr, 0, depctl.d32);
-+	depctl.d32 = DWC_READ_REG32(addr);
-+
-+	if (ep->is_in && core_if->dma_enable == 0) {
-+		write_isoc_frame_data(core_if, ep);
-+	}
-+
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+static void dwc_otg_set_uninitialized(int32_t * p, int size)
-+{
-+	int i;
-+	for (i = 0; i < size; i++) {
-+		p[i] = -1;
-+	}
-+}
-+
-+static int dwc_otg_param_initialized(int32_t val)
-+{
-+	return val != -1;
-+}
-+
-+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
-+{
-+	int i;
-+	core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
-+	if (!core_if->core_params) {
-+		return -DWC_E_NO_MEMORY;
-+	}
-+	dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
-+				  sizeof(*core_if->core_params) /
-+				  sizeof(int32_t));
-+	DWC_PRINTF("Setting default values for core params\n");
-+	dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
-+	dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
-+	dwc_otg_set_param_dma_desc_enable(core_if,
-+					  dwc_param_dma_desc_enable_default);
-+	dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
-+	dwc_otg_set_param_dma_burst_size(core_if,
-+					 dwc_param_dma_burst_size_default);
-+	dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
-+						       dwc_param_host_support_fs_ls_low_power_default);
-+	dwc_otg_set_param_enable_dynamic_fifo(core_if,
-+					      dwc_param_enable_dynamic_fifo_default);
-+	dwc_otg_set_param_data_fifo_size(core_if,
-+					 dwc_param_data_fifo_size_default);
-+	dwc_otg_set_param_dev_rx_fifo_size(core_if,
-+					   dwc_param_dev_rx_fifo_size_default);
-+	dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
-+						  dwc_param_dev_nperio_tx_fifo_size_default);
-+	dwc_otg_set_param_host_rx_fifo_size(core_if,
-+					    dwc_param_host_rx_fifo_size_default);
-+	dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
-+						   dwc_param_host_nperio_tx_fifo_size_default);
-+	dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
-+						  dwc_param_host_perio_tx_fifo_size_default);
-+	dwc_otg_set_param_max_transfer_size(core_if,
-+					    dwc_param_max_transfer_size_default);
-+	dwc_otg_set_param_max_packet_count(core_if,
-+					   dwc_param_max_packet_count_default);
-+	dwc_otg_set_param_host_channels(core_if,
-+					dwc_param_host_channels_default);
-+	dwc_otg_set_param_dev_endpoints(core_if,
-+					dwc_param_dev_endpoints_default);
-+	dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
-+	dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
-+	dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
-+						    dwc_param_host_ls_low_power_phy_clk_default);
-+	dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
-+	dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
-+					    dwc_param_phy_ulpi_ext_vbus_default);
-+	dwc_otg_set_param_phy_utmi_width(core_if,
-+					 dwc_param_phy_utmi_width_default);
-+	dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
-+	dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
-+	dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
-+	dwc_otg_set_param_en_multiple_tx_fifo(core_if,
-+					      dwc_param_en_multiple_tx_fifo_default);
-+	for (i = 0; i < 15; i++) {
-+		dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
-+							 dwc_param_dev_perio_tx_fifo_size_default,
-+							 i);
-+	}
-+
-+	for (i = 0; i < 15; i++) {
-+		dwc_otg_set_param_dev_tx_fifo_size(core_if,
-+						   dwc_param_dev_tx_fifo_size_default,
-+						   i);
-+	}
-+	dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
-+	dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
-+	dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
-+	dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
-+	dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
-+	dwc_otg_set_param_tx_thr_length(core_if,
-+					dwc_param_tx_thr_length_default);
-+	dwc_otg_set_param_rx_thr_length(core_if,
-+					dwc_param_rx_thr_length_default);
-+	dwc_otg_set_param_ahb_thr_ratio(core_if,
-+					dwc_param_ahb_thr_ratio_default);
-+	dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
-+	dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
-+	dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
-+	dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
-+	dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
-+	dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
-+	dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
-+	DWC_PRINTF("Finished setting default values for core params\n");
-+
-+	return 0;
-+}
-+
-+uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->dma_enable;
-+}
-+
-+/* Checks if the parameter is outside of its valid range of values */
-+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
-+		(((_param_) < (_low_)) || \
-+		((_param_) > (_high_)))
-+
-+/* Parameter access functions */
-+int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int valid;
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
-+		DWC_WARN("Wrong value for otg_cap parameter\n");
-+		DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
-+		retval = -DWC_E_INVALID;
-+		goto out;
-+	}
-+
-+	valid = 1;
-+	switch (val) {
-+	case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
-+		if (core_if->hwcfg2.b.op_mode !=
-+		    DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+			valid = 0;
-+		break;
-+	case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
-+		if ((core_if->hwcfg2.b.op_mode !=
-+		     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+		    && (core_if->hwcfg2.b.op_mode !=
-+			DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+		    && (core_if->hwcfg2.b.op_mode !=
-+			DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
-+		    && (core_if->hwcfg2.b.op_mode !=
-+			DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
-+			valid = 0;
-+		}
-+		break;
-+	case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
-+		/* always valid */
-+		break;
-+	}
-+	if (!valid) {
-+		if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
-+			DWC_ERROR
-+			    ("%d invalid for otg_cap paremter. Check HW configuration.\n",
-+			     val);
-+		}
-+		val =
-+		    (((core_if->hwcfg2.b.op_mode ==
-+		       DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
-+		      || (core_if->hwcfg2.b.op_mode ==
-+			  DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
-+		      || (core_if->hwcfg2.b.op_mode ==
-+			  DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
-+		      || (core_if->hwcfg2.b.op_mode ==
-+			  DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
-+		     DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
-+		     DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->otg_cap = val;
-+out:
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->otg_cap;
-+}
-+
-+int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong value for opt parameter\n");
-+		return -DWC_E_INVALID;
-+	}
-+	core_if->core_params->opt = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->opt;
-+}
-+
-+int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong value for dma enable\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
-+		if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
-+			DWC_ERROR
-+			    ("%d invalid for dma_enable paremter. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = 0;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->dma_enable = val;
-+	if (val == 0) {
-+		dwc_otg_set_param_dma_desc_enable(core_if, 0);
-+	}
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->dma_enable;
-+}
-+
-+int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong value for dma_enable\n");
-+		DWC_WARN("dma_desc_enable must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == 1)
-+	    && ((dwc_otg_get_param_dma_enable(core_if) == 0)
-+		|| (core_if->hwcfg4.b.desc_dma == 0))) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->dma_desc_enable)) {
-+			DWC_ERROR
-+			    ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = 0;
-+		retval = -DWC_E_INVALID;
-+	}
-+	core_if->core_params->dma_desc_enable = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->dma_desc_enable;
-+}
-+
-+int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
-+						   int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong value for host_support_fs_low_power\n");
-+		DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+	core_if->core_params->host_support_fs_ls_low_power = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
-+						       core_if)
-+{
-+	return core_if->core_params->host_support_fs_ls_low_power;
-+}
-+
-+int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
-+					  int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong value for enable_dynamic_fifo\n");
-+		DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->enable_dynamic_fifo)) {
-+			DWC_ERROR
-+			    ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = 0;
-+		retval = -DWC_E_INVALID;
-+	}
-+	core_if->core_params->enable_dynamic_fifo = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->enable_dynamic_fifo;
-+}
-+
-+int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
-+		DWC_WARN("Wrong value for data_fifo_size\n");
-+		DWC_WARN("data_fifo_size must be 32-32768\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > core_if->hwcfg3.b.dfifo_depth) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->data_fifo_size)) {
-+			DWC_ERROR
-+			    ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = core_if->hwcfg3.b.dfifo_depth;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->data_fifo_size = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->data_fifo_size;
-+}
-+
-+int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+		DWC_WARN("Wrong value for dev_rx_fifo_size\n");
-+		DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
-+		if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
-+		DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
-+		}
-+		val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->dev_rx_fifo_size = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->dev_rx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+					      int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+		DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
-+		DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->dev_nperio_tx_fifo_size)) {
-+			DWC_ERROR
-+			    ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
-+			     val);
-+		}
-+		val =
-+		    (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
-+		     16);
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->dev_nperio_tx_fifo_size = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->dev_nperio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+					int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+		DWC_WARN("Wrong value for host_rx_fifo_size\n");
-+		DWC_WARN("host_rx_fifo_size must be 16-32768\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->host_rx_fifo_size)) {
-+			DWC_ERROR
-+			    ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->host_rx_fifo_size = val;
-+	return retval;
-+
-+}
-+
-+int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->host_rx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+					       int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+		DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
-+		DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->host_nperio_tx_fifo_size)) {
-+			DWC_ERROR
-+			    ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
-+			     val);
-+		}
-+		val =
-+		    (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
-+		     16);
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->host_nperio_tx_fifo_size = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->host_nperio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+					      int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
-+		DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
-+		DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > ((core_if->hptxfsiz.d32) >> 16)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->host_perio_tx_fifo_size)) {
-+			DWC_ERROR
-+			    ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = (core_if->hptxfsiz.d32) >> 16;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->host_perio_tx_fifo_size = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->host_perio_tx_fifo_size;
-+}
-+
-+int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
-+					int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
-+		DWC_WARN("Wrong value for max_transfer_size\n");
-+		DWC_WARN("max_transfer_size must be 2047-524288\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->max_transfer_size)) {
-+			DWC_ERROR
-+			    ("%d invalid for max_transfer_size. Check HW configuration.\n",
-+			     val);
-+		}
-+		val =
-+		    ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
-+		     1);
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->max_transfer_size = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->max_transfer_size;
-+}
-+
-+int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
-+		DWC_WARN("Wrong value for max_packet_count\n");
-+		DWC_WARN("max_packet_count must be 15-511\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->max_packet_count)) {
-+			DWC_ERROR
-+			    ("%d invalid for max_packet_count. Check HW configuration.\n",
-+			     val);
-+		}
-+		val =
-+		    ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->max_packet_count = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->max_packet_count;
-+}
-+
-+int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
-+		DWC_WARN("Wrong value for host_channels\n");
-+		DWC_WARN("host_channels must be 1-16\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->host_channels)) {
-+			DWC_ERROR
-+			    ("%d invalid for host_channels. Check HW configurations.\n",
-+			     val);
-+		}
-+		val = (core_if->hwcfg2.b.num_host_chan + 1);
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->host_channels = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->host_channels;
-+}
-+
-+int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
-+		DWC_WARN("Wrong value for dev_endpoints\n");
-+		DWC_WARN("dev_endpoints must be 1-15\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val > (core_if->hwcfg2.b.num_dev_ep)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->dev_endpoints)) {
-+			DWC_ERROR
-+			    ("%d invalid for dev_endpoints. Check HW configurations.\n",
-+			     val);
-+		}
-+		val = core_if->hwcfg2.b.num_dev_ep;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->dev_endpoints = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->dev_endpoints;
-+}
-+
-+int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	int valid = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
-+		DWC_WARN("Wrong value for phy_type\n");
-+		DWC_WARN("phy_type must be 0,1 or 2\n");
-+		return -DWC_E_INVALID;
-+	}
-+#ifndef NO_FS_PHY_HW_CHECKS
-+	if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
-+	    ((core_if->hwcfg2.b.hs_phy_type == 1) ||
-+	     (core_if->hwcfg2.b.hs_phy_type == 3))) {
-+		valid = 1;
-+	} else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
-+		   ((core_if->hwcfg2.b.hs_phy_type == 2) ||
-+		    (core_if->hwcfg2.b.hs_phy_type == 3))) {
-+		valid = 1;
-+	} else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
-+		   (core_if->hwcfg2.b.fs_phy_type == 1)) {
-+		valid = 1;
-+	}
-+	if (!valid) {
-+		if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
-+			DWC_ERROR
-+			    ("%d invalid for phy_type. Check HW configurations.\n",
-+			     val);
-+		}
-+		if (core_if->hwcfg2.b.hs_phy_type) {
-+			if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
-+			    (core_if->hwcfg2.b.hs_phy_type == 1)) {
-+				val = DWC_PHY_TYPE_PARAM_UTMI;
-+			} else {
-+				val = DWC_PHY_TYPE_PARAM_ULPI;
-+			}
-+		}
-+		retval = -DWC_E_INVALID;
-+	}
-+#endif
-+	core_if->core_params->phy_type = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->phy_type;
-+}
-+
-+int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong value for speed parameter\n");
-+		DWC_WARN("max_speed parameter must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+	if ((val == 0)
-+	    && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
-+		if (dwc_otg_param_initialized(core_if->core_params->speed)) {
-+			DWC_ERROR
-+			    ("%d invalid for speed paremter. Check HW configuration.\n",
-+			     val);
-+		}
-+		val =
-+		    (dwc_otg_get_param_phy_type(core_if) ==
-+		     DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
-+		retval = -DWC_E_INVALID;
-+	}
-+	core_if->core_params->speed = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->speed;
-+}
-+
-+int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
-+						int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN
-+		    ("Wrong value for host_ls_low_power_phy_clk parameter\n");
-+		DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
-+	    && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->host_ls_low_power_phy_clk)) {
-+			DWC_ERROR
-+			    ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
-+			     val);
-+		}
-+		val =
-+		    (dwc_otg_get_param_phy_type(core_if) ==
-+		     DWC_PHY_TYPE_PARAM_FS) ?
-+		    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
-+		    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->host_ls_low_power_phy_clk = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->host_ls_low_power_phy_clk;
-+}
-+
-+int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong value for phy_ulpi_ddr\n");
-+		DWC_WARN("phy_upli_ddr must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->phy_ulpi_ddr = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->phy_ulpi_ddr;
-+}
-+
-+int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
-+					int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
-+		DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->phy_ulpi_ext_vbus = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->phy_ulpi_ext_vbus;
-+}
-+
-+int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
-+		DWC_WARN("Wrong valaue for phy_utmi_width\n");
-+		DWC_WARN("phy_utmi_width must be 8 or 16\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->phy_utmi_width = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->phy_utmi_width;
-+}
-+
-+int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
-+		DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->ulpi_fs_ls = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->ulpi_fs_ls;
-+}
-+
-+int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong valaue for ts_dline\n");
-+		DWC_WARN("ts_dline must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->ts_dline = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->ts_dline;
-+}
-+
-+int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong valaue for i2c_enable\n");
-+		DWC_WARN("i2c_enable must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+#ifndef NO_FS_PHY_HW_CHECK
-+	if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
-+		if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
-+			DWC_ERROR
-+			    ("%d invalid for i2c_enable. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = 0;
-+		retval = -DWC_E_INVALID;
-+	}
-+#endif
-+
-+	core_if->core_params->i2c_enable = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->i2c_enable;
-+}
-+
-+int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+					     int32_t val, int fifo_num)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
-+		DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
-+		DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val >
-+	    (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
-+			DWC_ERROR
-+			    ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
-+			     val, fifo_num);
-+		}
-+		val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+						 int fifo_num)
-+{
-+	return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
-+}
-+
-+int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
-+					  int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
-+		DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->en_multiple_tx_fifo)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = 0;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->en_multiple_tx_fifo = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->en_multiple_tx_fifo;
-+}
-+
-+int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
-+				       int fifo_num)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
-+		DWC_WARN("Wrong value for dev_tx_fifo_size\n");
-+		DWC_WARN("dev_tx_fifo_size must be 4-768\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val >
-+	    (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
-+			DWC_ERROR
-+			    ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
-+			     val, fifo_num);
-+		}
-+		val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+					   int fifo_num)
-+{
-+	return core_if->core_params->dev_tx_fifo_size[fifo_num];
-+}
-+
-+int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
-+		DWC_WARN("Wrong value for thr_ctl\n");
-+		DWC_WARN("thr_ctl must be 0-7\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val != 0) &&
-+	    (!dwc_otg_get_param_dma_enable(core_if) ||
-+	     !core_if->hwcfg4.b.ded_fifo_en)) {
-+		if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = 0;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->thr_ctl = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->thr_ctl;
-+}
-+
-+int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("Wrong value for lpm_enable\n");
-+		DWC_WARN("lpm_enable must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val && !core_if->hwcfg3.b.otg_lpm_en) {
-+		if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
-+			     val);
-+		}
-+		val = 0;
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->lpm_enable = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->lpm_enable;
-+}
-+
-+int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
-+		DWC_WARN("Wrong valaue for tx_thr_length\n");
-+		DWC_WARN("tx_thr_length must be 8 - 128\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->tx_thr_length = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->tx_thr_length;
-+}
-+
-+int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
-+		DWC_WARN("Wrong valaue for rx_thr_length\n");
-+		DWC_WARN("rx_thr_length must be 8 - 128\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->rx_thr_length = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->rx_thr_length;
-+}
-+
-+int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
-+	    DWC_OTG_PARAM_TEST(val, 4, 4) &&
-+	    DWC_OTG_PARAM_TEST(val, 8, 8) &&
-+	    DWC_OTG_PARAM_TEST(val, 16, 16) &&
-+	    DWC_OTG_PARAM_TEST(val, 32, 32) &&
-+	    DWC_OTG_PARAM_TEST(val, 64, 64) &&
-+	    DWC_OTG_PARAM_TEST(val, 128, 128) &&
-+	    DWC_OTG_PARAM_TEST(val, 256, 256)) {
-+		DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
-+		return -DWC_E_INVALID;
-+	}
-+	core_if->core_params->dma_burst_size = val;
-+	return 0;
-+}
-+
-+int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->dma_burst_size;
-+}
-+
-+int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
-+		return -DWC_E_INVALID;
-+	}
-+	if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
-+		if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter pti_enable. Check HW configuration.\n",
-+			     val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->pti_enable = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->pti_enable;
-+}
-+
-+int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
-+		return -DWC_E_INVALID;
-+	}
-+	if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
-+		if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
-+			     val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->mpi_enable = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->mpi_enable;
-+}
-+
-+int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
-+		return -DWC_E_INVALID;
-+	}
-+	if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->adp_supp_enable)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter adp_enable. Check HW configuration.\n",
-+			     val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->adp_supp_enable = val;
-+	/*Set OTG version 2.0 in case of enabling ADP*/
-+	if (val)
-+		dwc_otg_set_param_otg_ver(core_if, 1);
-+
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->adp_supp_enable;
-+}
-+
-+int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
-+		DWC_WARN("ic_usb_cap must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
-+		if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
-+			     val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->ic_usb_cap = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->ic_usb_cap;
-+}
-+
-+int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	int valid = 1;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
-+		DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
-+		DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (val
-+	    && (core_if->snpsid < OTG_CORE_REV_2_81a
-+		|| !dwc_otg_get_param_thr_ctl(core_if))) {
-+		valid = 0;
-+	} else if (val
-+		   && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
-+		       4)) {
-+		valid = 0;
-+	}
-+	if (valid == 0) {
-+		if (dwc_otg_param_initialized
-+		    (core_if->core_params->ahb_thr_ratio)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
-+			     val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+
-+	core_if->core_params->ahb_thr_ratio = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->ahb_thr_ratio;
-+}
-+
-+int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	int valid = 1;
-+	hwcfg4_data_t hwcfg4 = {.d32 = 0 };
-+	hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
-+		DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
-+		DWC_WARN("power_down must be 0 - 2\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
-+		valid = 0;
-+	}
-+	if ((val == 3)
-+	    && ((core_if->snpsid < OTG_CORE_REV_3_00a)
-+		|| (hwcfg4.b.xhiber == 0))) {
-+		valid = 0;
-+	}
-+	if (valid == 0) {
-+		if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
-+			DWC_ERROR
-+			    ("%d invalid for parameter power_down. Check HW configuration.\n",
-+			     val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->power_down = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->power_down;
-+}
-+
-+int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	int valid = 1;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
-+		DWC_WARN("reload_ctl must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
-+		valid = 0;
-+	}
-+	if (valid == 0) {
-+		if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
-+			DWC_ERROR("%d invalid for parameter reload_ctl."
-+				  "Check HW configuration.\n", val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->reload_ctl = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->reload_ctl;
-+}
-+
-+int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	int valid = 1;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
-+		DWC_WARN("dev_out_nak must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
-+		!(core_if->core_params->dma_desc_enable))) {
-+		valid = 0;
-+	}
-+	if (valid == 0) {
-+		if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
-+			DWC_ERROR("%d invalid for parameter dev_out_nak."
-+				"Check HW configuration.\n", val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->dev_out_nak = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->dev_out_nak;
-+}
-+
-+int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	int valid = 1;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
-+		DWC_WARN("cont_on_bna must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
-+		!(core_if->core_params->dma_desc_enable))) {
-+			valid = 0;
-+	}
-+	if (valid == 0) {
-+		if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
-+			DWC_ERROR("%d invalid for parameter cont_on_bna."
-+				"Check HW configuration.\n", val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->cont_on_bna = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->cont_on_bna;
-+}
-+
-+int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+	int valid = 1;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
-+		DWC_WARN("ahb_single must be 0 or 1\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
-+			valid = 0;
-+	}
-+	if (valid == 0) {
-+		if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
-+			DWC_ERROR("%d invalid for parameter ahb_single."
-+				"Check HW configuration.\n", val);
-+		}
-+		retval = -DWC_E_INVALID;
-+		val = 0;
-+	}
-+	core_if->core_params->ahb_single = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->ahb_single;
-+}
-+
-+int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
-+{
-+	int retval = 0;
-+
-+	if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
-+		DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
-+		DWC_WARN
-+		    ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	core_if->core_params->otg_ver = val;
-+	return retval;
-+}
-+
-+int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->core_params->otg_ver;
-+}
-+
-+uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
-+{
-+	gotgctl_data_t otgctl;
-+	otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+	return otgctl.b.hstnegscs;
-+}
-+
-+uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
-+{
-+	gotgctl_data_t otgctl;
-+	otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+	return otgctl.b.sesreqscs;
-+}
-+
-+void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	if(core_if->otg_ver == 0) {
-+		gotgctl_data_t otgctl;
-+		otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+		otgctl.b.hnpreq = val;
-+		DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
-+	} else {
-+		core_if->otg_sts = val;
-+	}
-+}
-+
-+uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->snpsid;
-+}
-+
-+uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
-+{
-+	gintsts_data_t gintsts;
-+	gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+	return gintsts.b.curmode;
-+}
-+
-+uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
-+{
-+	gusbcfg_data_t usbcfg;
-+	usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+	return usbcfg.b.hnpcap;
-+}
-+
-+void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	gusbcfg_data_t usbcfg;
-+	usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+	usbcfg.b.hnpcap = val;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
-+{
-+	gusbcfg_data_t usbcfg;
-+	usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+	return usbcfg.b.srpcap;
-+}
-+
-+void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	gusbcfg_data_t usbcfg;
-+	usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+	usbcfg.b.srpcap = val;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
-+{
-+	dcfg_data_t dcfg;
-+	/* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */
-+
-+        dcfg.d32 = -1; //GRAYG
-+        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
-+        if (NULL == core_if)
-+                DWC_ERROR("reg request with NULL core_if\n");
-+        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
-+                    core_if, core_if->dev_if);
-+        if (NULL == core_if->dev_if)
-+                DWC_ERROR("reg request with NULL dev_if\n");
-+        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
-+                    "dev_global_regs(%p)\n", __func__,
-+                    core_if, core_if->dev_if,
-+                    core_if->dev_if->dev_global_regs);
-+        if (NULL == core_if->dev_if->dev_global_regs)
-+                DWC_ERROR("reg request with NULL dev_global_regs\n");
-+        else {
-+                DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
-+                            "dev_global_regs(%p)->dcfg = %p\n", __func__,
-+                            core_if, core_if->dev_if,
-+                            core_if->dev_if->dev_global_regs,
-+                            &core_if->dev_if->dev_global_regs->dcfg);
-+		dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+        }
-+	return dcfg.b.devspd;
-+}
-+
-+void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	dcfg_data_t dcfg;
-+	dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+	dcfg.b.devspd = val;
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
-+{
-+	hprt0_data_t hprt0;
-+	hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+	return hprt0.b.prtconnsts;
-+}
-+
-+uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
-+{
-+	dsts_data_t dsts;
-+	dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+	return dsts.b.enumspd;
-+}
-+
-+uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
-+{
-+	hprt0_data_t hprt0;
-+	hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+	return hprt0.b.prtpwr;
-+
-+}
-+
-+uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
-+{
-+	return core_if->hibernation_suspend;
-+}
-+
-+void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	hprt0_data_t hprt0;
-+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+	hprt0.b.prtpwr = val;
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
-+{
-+	hprt0_data_t hprt0;
-+	hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+	return hprt0.b.prtsusp;
-+
-+}
-+
-+void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	hprt0_data_t hprt0;
-+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+	hprt0.b.prtsusp = val;
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
-+{
-+	hfir_data_t hfir;
-+	hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+	return hfir.b.frint;
-+
-+}
-+
-+void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	hfir_data_t hfir;
-+	uint32_t fram_int;
-+	fram_int = calc_frame_interval(core_if);
-+	hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
-+	if (!core_if->core_params->reload_ctl) {
-+		DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
-+			 "not set to 1.\nShould load driver with reload_ctl=1"
-+			 " module parameter\n");
-+		return;
-+	}
-+	switch (fram_int) {
-+	case 3750:
-+		if ((val < 3350) || (val > 4150)) {
-+			DWC_WARN("HFIR interval for HS core and 30 MHz"
-+				 "clock freq should be from 3350 to 4150\n");
-+			return;
-+		}
-+		break;
-+	case 30000:
-+		if ((val < 26820) || (val > 33180)) {
-+			DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
-+				 "clock freq should be from 26820 to 33180\n");
-+			return;
-+		}
-+		break;
-+	case 6000:
-+		if ((val < 5360) || (val > 6640)) {
-+			DWC_WARN("HFIR interval for HS core and 48 MHz"
-+				 "clock freq should be from 5360 to 6640\n");
-+			return;
-+		}
-+		break;
-+	case 48000:
-+		if ((val < 42912) || (val > 53088)) {
-+			DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
-+				 "clock freq should be from 42912 to 53088\n");
-+			return;
-+		}
-+		break;
-+	case 7500:
-+		if ((val < 6700) || (val > 8300)) {
-+			DWC_WARN("HFIR interval for HS core and 60 MHz"
-+				 "clock freq should be from 6700 to 8300\n");
-+			return;
-+		}
-+		break;
-+	case 60000:
-+		if ((val < 53640) || (val > 65536)) {
-+			DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
-+				 "clock freq should be from 53640 to 65536\n");
-+			return;
-+		}
-+		break;
-+	default:
-+		DWC_WARN("Unknown frame interval\n");
-+		return;
-+		break;
-+
-+	}
-+	hfir.b.frint = val;
-+	DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
-+}
-+
-+uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
-+{
-+	hcfg_data_t hcfg;
-+	hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+	return hcfg.b.modechtimen;
-+
-+}
-+
-+void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	hcfg_data_t hcfg;
-+	hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
-+	hcfg.b.modechtimen = val;
-+	DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	hprt0_data_t hprt0;
-+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+	hprt0.b.prtres = val;
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+}
-+
-+uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
-+{
-+	dctl_data_t dctl;
-+	dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+	return dctl.b.rmtwkupsig;
-+}
-+
-+uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+
-+	DWC_ASSERT(!
-+		   ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
-+		   "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
-+		   core_if->lx_state, lpmcfg.b.prt_sleep_sts);
-+
-+	return lpmcfg.b.prt_sleep_sts;
-+}
-+
-+uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	return lpmcfg.b.rem_wkup_en;
-+}
-+
-+uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	return lpmcfg.b.appl_resp;
-+}
-+
-+void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	lpmcfg.b.appl_resp = val;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	return lpmcfg.b.hsic_connect;
-+}
-+
-+void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	lpmcfg.b.hsic_connect = val;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	return lpmcfg.b.inv_sel_hsic;
-+
-+}
-+
-+void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	lpmcfg.b.inv_sel_hsic = val;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+}
-+
-+uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+}
-+
-+void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
-+}
-+
-+uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+}
-+
-+void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
-+}
-+
-+uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+}
-+
-+void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
-+}
-+
-+uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
-+}
-+
-+void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
-+}
-+
-+uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
-+}
-+
-+void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
-+}
-+
-+uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
-+}
-+
-+void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
-+}
-+
-+uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(core_if->host_if->hprt0);
-+
-+}
-+
-+void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, val);
-+}
-+
-+uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(&core_if->core_global_regs->guid);
-+}
-+
-+void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
-+{
-+	DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
-+}
-+
-+uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
-+{
-+	return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
-+}
-+
-+uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
-+{
-+	return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
-+}
-+
-+/**
-+ * Start the SRP timer to detect when the SRP does not complete within
-+ * 6 seconds.
-+ *
-+ * @param core_if the pointer to core_if strucure.
-+ */
-+void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
-+{
-+	core_if->srp_timer_started = 1;
-+	DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
-+}
-+
-+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
-+{
-+	uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
-+	gotgctl_data_t mem;
-+	gotgctl_data_t val;
-+
-+	val.d32 = DWC_READ_REG32(addr);
-+	if (val.b.sesreq) {
-+		DWC_ERROR("Session Request Already active!\n");
-+		return;
-+	}
-+
-+	DWC_INFO("Session Request Initated\n");	//NOTICE
-+	mem.d32 = DWC_READ_REG32(addr);
-+	mem.b.sesreq = 1;
-+	DWC_WRITE_REG32(addr, mem.d32);
-+
-+	/* Start the SRP timer */
-+	dwc_otg_pcd_start_srp_timer(core_if);
-+	return;
-+}
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.h
-@@ -0,0 +1,1464 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
-+ * $Revision: #123 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#if !defined(__DWC_CIL_H__)
-+#define __DWC_CIL_H__
-+
-+#include "dwc_list.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_regs.h"
-+
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_adp.h"
-+
-+/**
-+ * @file
-+ * This file contains the interface to the Core Interface Layer.
-+ */
-+
-+#ifdef DWC_UTE_CFI
-+
-+#define MAX_DMA_DESCS_PER_EP	256
-+
-+/**
-+ * Enumeration for the data buffer mode
-+ */
-+typedef enum _data_buffer_mode {
-+	BM_STANDARD = 0,	/* data buffer is in normal mode */
-+	BM_SG = 1,		/* data buffer uses the scatter/gather mode */
-+	BM_CONCAT = 2,		/* data buffer uses the concatenation mode */
-+	BM_CIRCULAR = 3,	/* data buffer uses the circular DMA mode */
-+	BM_ALIGN = 4		/* data buffer is in buffer alignment mode */
-+} data_buffer_mode_e;
-+#endif //DWC_UTE_CFI
-+
-+/** Macros defined for DWC OTG HW Release version */
-+
-+#define OTG_CORE_REV_2_60a	0x4F54260A
-+#define OTG_CORE_REV_2_71a	0x4F54271A
-+#define OTG_CORE_REV_2_72a	0x4F54272A
-+#define OTG_CORE_REV_2_80a	0x4F54280A
-+#define OTG_CORE_REV_2_81a	0x4F54281A
-+#define OTG_CORE_REV_2_90a	0x4F54290A
-+#define OTG_CORE_REV_2_91a	0x4F54291A
-+#define OTG_CORE_REV_2_92a	0x4F54292A
-+#define OTG_CORE_REV_2_93a	0x4F54293A
-+#define OTG_CORE_REV_2_94a	0x4F54294A
-+#define OTG_CORE_REV_3_00a	0x4F54300A
-+
-+/**
-+ * Information for each ISOC packet.
-+ */
-+typedef struct iso_pkt_info {
-+	uint32_t offset;
-+	uint32_t length;
-+	int32_t status;
-+} iso_pkt_info_t;
-+
-+/**
-+ * The <code>dwc_ep</code> structure represents the state of a single
-+ * endpoint when acting in device mode. It contains the data items
-+ * needed for an endpoint to be activated and transfer packets.
-+ */
-+typedef struct dwc_ep {
-+	/** EP number used for register address lookup */
-+	uint8_t num;
-+	/** EP direction 0 = OUT */
-+	unsigned is_in:1;
-+	/** EP active. */
-+	unsigned active:1;
-+
-+	/**
-+	 * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
-+	 * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
-+	unsigned tx_fifo_num:4;
-+	/** EP type: 0 - Control, 1 - ISOC,	 2 - BULK,	3 - INTR */
-+	unsigned type:2;
-+#define DWC_OTG_EP_TYPE_CONTROL	   0
-+#define DWC_OTG_EP_TYPE_ISOC	   1
-+#define DWC_OTG_EP_TYPE_BULK	   2
-+#define DWC_OTG_EP_TYPE_INTR	   3
-+
-+	/** DATA start PID for INTR and BULK EP */
-+	unsigned data_pid_start:1;
-+	/** Frame (even/odd) for ISOC EP */
-+	unsigned even_odd_frame:1;
-+	/** Max Packet bytes */
-+	unsigned maxpacket:11;
-+
-+	/** Max Transfer size */
-+	uint32_t maxxfer;
-+
-+	/** @name Transfer state */
-+	/** @{ */
-+
-+	/**
-+	 * Pointer to the beginning of the transfer buffer -- do not modify
-+	 * during transfer.
-+	 */
-+
-+	dwc_dma_t dma_addr;
-+
-+	dwc_dma_t dma_desc_addr;
-+	dwc_otg_dev_dma_desc_t *desc_addr;
-+
-+	uint8_t *start_xfer_buff;
-+	/** pointer to the transfer buffer */
-+	uint8_t *xfer_buff;
-+	/** Number of bytes to transfer */
-+	unsigned xfer_len:19;
-+	/** Number of bytes transferred. */
-+	unsigned xfer_count:19;
-+	/** Sent ZLP */
-+	unsigned sent_zlp:1;
-+	/** Total len for control transfer */
-+	unsigned total_len:19;
-+
-+	/** stall clear flag */
-+	unsigned stall_clear_flag:1;
-+
-+	/** SETUP pkt cnt rollover flag for EP0 out*/
-+	unsigned stp_rollover;
-+
-+#ifdef DWC_UTE_CFI
-+	/* The buffer mode */
-+	data_buffer_mode_e buff_mode;
-+
-+	/* The chain of DMA descriptors.
-+	 * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
-+	 */
-+	dwc_otg_dma_desc_t *descs;
-+
-+	/* The DMA address of the descriptors chain start */
-+	dma_addr_t descs_dma_addr;
-+	/** This variable stores the length of the last enqueued request */
-+	uint32_t cfi_req_len;
-+#endif				//DWC_UTE_CFI
-+
-+/** Max DMA Descriptor count for any EP */
-+#define MAX_DMA_DESC_CNT 256
-+	/** Allocated DMA Desc count */
-+	uint32_t desc_cnt;
-+
-+	/** bInterval */
-+	uint32_t bInterval;
-+	/** Next frame num to setup next ISOC transfer */
-+	uint32_t frame_num;
-+	/** Indicates SOF number overrun in DSTS */
-+	uint8_t frm_overrun;
-+
-+#ifdef DWC_UTE_PER_IO
-+	/** Next frame num for which will be setup DMA Desc */
-+	uint32_t xiso_frame_num;
-+	/** bInterval */
-+	uint32_t xiso_bInterval;
-+	/** Count of currently active transfers - shall be either 0 or 1 */
-+	int xiso_active_xfers;
-+	int xiso_queued_xfers;
-+#endif
-+#ifdef DWC_EN_ISOC
-+	/**
-+	 * Variables specific for ISOC EPs
-+	 *
-+	 */
-+	/** DMA addresses of ISOC buffers */
-+	dwc_dma_t dma_addr0;
-+	dwc_dma_t dma_addr1;
-+
-+	dwc_dma_t iso_dma_desc_addr;
-+	dwc_otg_dev_dma_desc_t *iso_desc_addr;
-+
-+	/** pointer to the transfer buffers */
-+	uint8_t *xfer_buff0;
-+	uint8_t *xfer_buff1;
-+
-+	/** number of ISOC Buffer is processing */
-+	uint32_t proc_buf_num;
-+	/** Interval of ISOC Buffer processing */
-+	uint32_t buf_proc_intrvl;
-+	/** Data size for regular frame */
-+	uint32_t data_per_frame;
-+
-+	/* todo - pattern data support is to be implemented in the future */
-+	/** Data size for pattern frame */
-+	uint32_t data_pattern_frame;
-+	/** Frame number of pattern data */
-+	uint32_t sync_frame;
-+
-+	/** bInterval */
-+	uint32_t bInterval;
-+	/** ISO Packet number per frame */
-+	uint32_t pkt_per_frm;
-+	/** Next frame num for which will be setup DMA Desc */
-+	uint32_t next_frame;
-+	/** Number of packets per buffer processing */
-+	uint32_t pkt_cnt;
-+	/** Info for all isoc packets */
-+	iso_pkt_info_t *pkt_info;
-+	/** current pkt number */
-+	uint32_t cur_pkt;
-+	/** current pkt number */
-+	uint8_t *cur_pkt_addr;
-+	/** current pkt number */
-+	uint32_t cur_pkt_dma_addr;
-+#endif				/* DWC_EN_ISOC */
-+
-+/** @} */
-+} dwc_ep_t;
-+
-+/*
-+ * Reasons for halting a host channel.
-+ */
-+typedef enum dwc_otg_halt_status {
-+	DWC_OTG_HC_XFER_NO_HALT_STATUS,
-+	DWC_OTG_HC_XFER_COMPLETE,
-+	DWC_OTG_HC_XFER_URB_COMPLETE,
-+	DWC_OTG_HC_XFER_ACK,
-+	DWC_OTG_HC_XFER_NAK,
-+	DWC_OTG_HC_XFER_NYET,
-+	DWC_OTG_HC_XFER_STALL,
-+	DWC_OTG_HC_XFER_XACT_ERR,
-+	DWC_OTG_HC_XFER_FRAME_OVERRUN,
-+	DWC_OTG_HC_XFER_BABBLE_ERR,
-+	DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
-+	DWC_OTG_HC_XFER_AHB_ERR,
-+	DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
-+	DWC_OTG_HC_XFER_URB_DEQUEUE
-+} dwc_otg_halt_status_e;
-+
-+/**
-+ * Host channel descriptor. This structure represents the state of a single
-+ * host channel when acting in host mode. It contains the data items needed to
-+ * transfer packets to an endpoint via a host channel.
-+ */
-+typedef struct dwc_hc {
-+	/** Host channel number used for register address lookup */
-+	uint8_t hc_num;
-+
-+	/** Device to access */
-+	unsigned dev_addr:7;
-+
-+	/** EP to access */
-+	unsigned ep_num:4;
-+
-+	/** EP direction. 0: OUT, 1: IN */
-+	unsigned ep_is_in:1;
-+
-+	/**
-+	 * EP speed.
-+	 * One of the following values:
-+	 *	- DWC_OTG_EP_SPEED_LOW
-+	 *	- DWC_OTG_EP_SPEED_FULL
-+	 *	- DWC_OTG_EP_SPEED_HIGH
-+	 */
-+	unsigned speed:2;
-+#define DWC_OTG_EP_SPEED_LOW	0
-+#define DWC_OTG_EP_SPEED_FULL	1
-+#define DWC_OTG_EP_SPEED_HIGH	2
-+
-+	/**
-+	 * Endpoint type.
-+	 * One of the following values:
-+	 *	- DWC_OTG_EP_TYPE_CONTROL: 0
-+	 *	- DWC_OTG_EP_TYPE_ISOC: 1
-+	 *	- DWC_OTG_EP_TYPE_BULK: 2
-+	 *	- DWC_OTG_EP_TYPE_INTR: 3
-+	 */
-+	unsigned ep_type:2;
-+
-+	/** Max packet size in bytes */
-+	unsigned max_packet:11;
-+
-+	/**
-+	 * PID for initial transaction.
-+	 * 0: DATA0,<br>
-+	 * 1: DATA2,<br>
-+	 * 2: DATA1,<br>
-+	 * 3: MDATA (non-Control EP),
-+	 *	  SETUP (Control EP)
-+	 */
-+	unsigned data_pid_start:2;
-+#define DWC_OTG_HC_PID_DATA0 0
-+#define DWC_OTG_HC_PID_DATA2 1
-+#define DWC_OTG_HC_PID_DATA1 2
-+#define DWC_OTG_HC_PID_MDATA 3
-+#define DWC_OTG_HC_PID_SETUP 3
-+
-+	/** Number of periodic transactions per (micro)frame */
-+	unsigned multi_count:2;
-+
-+	/** @name Transfer State */
-+	/** @{ */
-+
-+	/** Pointer to the current transfer buffer position. */
-+	uint8_t *xfer_buff;
-+	/**
-+	 * In Buffer DMA mode this buffer will be used
-+	 * if xfer_buff is not DWORD aligned.
-+	 */
-+	dwc_dma_t align_buff;
-+	/** Total number of bytes to transfer. */
-+	uint32_t xfer_len;
-+	/** Number of bytes transferred so far. */
-+	uint32_t xfer_count;
-+	/** Packet count at start of transfer.*/
-+	uint16_t start_pkt_count;
-+
-+	/**
-+	 * Flag to indicate whether the transfer has been started. Set to 1 if
-+	 * it has been started, 0 otherwise.
-+	 */
-+	uint8_t xfer_started;
-+
-+	/**
-+	 * Set to 1 to indicate that a PING request should be issued on this
-+	 * channel. If 0, process normally.
-+	 */
-+	uint8_t do_ping;
-+
-+	/**
-+	 * Set to 1 to indicate that the error count for this transaction is
-+	 * non-zero. Set to 0 if the error count is 0.
-+	 */
-+	uint8_t error_state;
-+
-+	/**
-+	 * Set to 1 to indicate that this channel should be halted the next
-+	 * time a request is queued for the channel. This is necessary in
-+	 * slave mode if no request queue space is available when an attempt
-+	 * is made to halt the channel.
-+	 */
-+	uint8_t halt_on_queue;
-+
-+	/**
-+	 * Set to 1 if the host channel has been halted, but the core is not
-+	 * finished flushing queued requests. Otherwise 0.
-+	 */
-+	uint8_t halt_pending;
-+
-+	/**
-+	 * Reason for halting the host channel.
-+	 */
-+	dwc_otg_halt_status_e halt_status;
-+
-+	/*
-+	 * Split settings for the host channel
-+	 */
-+	uint8_t do_split;		   /**< Enable split for the channel */
-+	uint8_t complete_split;	   /**< Enable complete split */
-+	uint8_t hub_addr;		   /**< Address of high speed hub */
-+
-+	uint8_t port_addr;		   /**< Port of the low/full speed device */
-+	/** Split transaction position
-+	 * One of the following values:
-+	 *	  - DWC_HCSPLIT_XACTPOS_MID
-+	 *	  - DWC_HCSPLIT_XACTPOS_BEGIN
-+	 *	  - DWC_HCSPLIT_XACTPOS_END
-+	 *	  - DWC_HCSPLIT_XACTPOS_ALL */
-+	uint8_t xact_pos;
-+
-+	/** Set when the host channel does a short read. */
-+	uint8_t short_read;
-+
-+	/**
-+	 * Number of requests issued for this channel since it was assigned to
-+	 * the current transfer (not counting PINGs).
-+	 */
-+	uint8_t requests;
-+
-+	/**
-+	 * Queue Head for the transfer being processed by this channel.
-+	 */
-+	struct dwc_otg_qh *qh;
-+
-+	/** @} */
-+
-+	/** Entry in list of host channels. */
-+	 DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
-+
-+	/** @name Descriptor DMA support */
-+	/** @{ */
-+
-+	/** Number of Transfer Descriptors */
-+	uint16_t ntd;
-+
-+	/** Descriptor List DMA address */
-+	dwc_dma_t desc_list_addr;
-+
-+	/** Scheduling micro-frame bitmap. */
-+	uint8_t schinfo;
-+
-+	/** @} */
-+} dwc_hc_t;
-+
-+/**
-+ * The following parameters may be specified when starting the module. These
-+ * parameters define how the DWC_otg controller should be configured.
-+ */
-+typedef struct dwc_otg_core_params {
-+	int32_t opt;
-+
-+	/**
-+	 * Specifies the OTG capabilities. The driver will automatically
-+	 * detect the value for this parameter if none is specified.
-+	 * 0 - HNP and SRP capable (default)
-+	 * 1 - SRP Only capable
-+	 * 2 - No HNP/SRP capable
-+	 */
-+	int32_t otg_cap;
-+
-+	/**
-+	 * Specifies whether to use slave or DMA mode for accessing the data
-+	 * FIFOs. The driver will automatically detect the value for this
-+	 * parameter if none is specified.
-+	 * 0 - Slave
-+	 * 1 - DMA (default, if available)
-+	 */
-+	int32_t dma_enable;
-+
-+	/**
-+	 * When DMA mode is enabled specifies whether to use address DMA or DMA
-+	 * Descriptor mode for accessing the data FIFOs in device mode. The driver
-+	 * will automatically detect the value for this if none is specified.
-+	 * 0 - address DMA
-+	 * 1 - DMA Descriptor(default, if available)
-+	 */
-+	int32_t dma_desc_enable;
-+	/** The DMA Burst size (applicable only for External DMA
-+	 * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+	 */
-+	int32_t dma_burst_size;	/* Translate this to GAHBCFG values */
-+
-+	/**
-+	 * Specifies the maximum speed of operation in host and device mode.
-+	 * The actual speed depends on the speed of the attached device and
-+	 * the value of phy_type. The actual speed depends on the speed of the
-+	 * attached device.
-+	 * 0 - High Speed (default)
-+	 * 1 - Full Speed
-+	 */
-+	int32_t speed;
-+	/** Specifies whether low power mode is supported when attached
-+	 *	to a Full Speed or Low Speed device in host mode.
-+	 * 0 - Don't support low power mode (default)
-+	 * 1 - Support low power mode
-+	 */
-+	int32_t host_support_fs_ls_low_power;
-+
-+	/** Specifies the PHY clock rate in low power mode when connected to a
-+	 * Low Speed device in host mode. This parameter is applicable only if
-+	 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
-+	 * then defaults to 6 MHZ otherwise 48 MHZ.
-+	 *
-+	 * 0 - 48 MHz
-+	 * 1 - 6 MHz
-+	 */
-+	int32_t host_ls_low_power_phy_clk;
-+
-+	/**
-+	 * 0 - Use cC FIFO size parameters
-+	 * 1 - Allow dynamic FIFO sizing (default)
-+	 */
-+	int32_t enable_dynamic_fifo;
-+
-+	/** Total number of 4-byte words in the data FIFO memory. This
-+	 * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
-+	 * Tx FIFOs.
-+	 * 32 to 32768 (default 8192)
-+	 * Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+	 */
-+	int32_t data_fifo_size;
-+
-+	/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+	 * FIFO sizing is enabled.
-+	 * 16 to 32768 (default 1064)
-+	 */
-+	int32_t dev_rx_fifo_size;
-+
-+	/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
-+	 * when dynamic FIFO sizing is enabled.
-+	 * 16 to 32768 (default 1024)
-+	 */
-+	int32_t dev_nperio_tx_fifo_size;
-+
-+	/** Number of 4-byte words in each of the periodic Tx FIFOs in device
-+	 * mode when dynamic FIFO sizing is enabled.
-+	 * 4 to 768 (default 256)
-+	 */
-+	uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+
-+	/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
-+	 * FIFO sizing is enabled.
-+	 * 16 to 32768 (default 1024)
-+	 */
-+	int32_t host_rx_fifo_size;
-+
-+	/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
-+	 * when Dynamic FIFO sizing is enabled in the core.
-+	 * 16 to 32768 (default 1024)
-+	 */
-+	int32_t host_nperio_tx_fifo_size;
-+
-+	/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
-+	 * FIFO sizing is enabled.
-+	 * 16 to 32768 (default 1024)
-+	 */
-+	int32_t host_perio_tx_fifo_size;
-+
-+	/** The maximum transfer size supported in bytes.
-+	 * 2047 to 65,535  (default 65,535)
-+	 */
-+	int32_t max_transfer_size;
-+
-+	/** The maximum number of packets in a transfer.
-+	 * 15 to 511  (default 511)
-+	 */
-+	int32_t max_packet_count;
-+
-+	/** The number of host channel registers to use.
-+	 * 1 to 16 (default 12)
-+	 * Note: The FPGA configuration supports a maximum of 12 host channels.
-+	 */
-+	int32_t host_channels;
-+
-+	/** The number of endpoints in addition to EP0 available for device
-+	 * mode operations.
-+	 * 1 to 15 (default 6 IN and OUT)
-+	 * Note: The FPGA configuration supports a maximum of 6 IN and OUT
-+	 * endpoints in addition to EP0.
-+	 */
-+	int32_t dev_endpoints;
-+
-+		/**
-+		 * Specifies the type of PHY interface to use. By default, the driver
-+		 * will automatically detect the phy_type.
-+		 *
-+		 * 0 - Full Speed PHY
-+		 * 1 - UTMI+ (default)
-+		 * 2 - ULPI
-+		 */
-+	int32_t phy_type;
-+
-+	/**
-+	 * Specifies the UTMI+ Data Width. This parameter is
-+	 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
-+	 * PHY_TYPE, this parameter indicates the data width between
-+	 * the MAC and the ULPI Wrapper.) Also, this parameter is
-+	 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
-+	 * to "8 and 16 bits", meaning that the core has been
-+	 * configured to work at either data path width.
-+	 *
-+	 * 8 or 16 bits (default 16)
-+	 */
-+	int32_t phy_utmi_width;
-+
-+	/**
-+	 * Specifies whether the ULPI operates at double or single
-+	 * data rate. This parameter is only applicable if PHY_TYPE is
-+	 * ULPI.
-+	 *
-+	 * 0 - single data rate ULPI interface with 8 bit wide data
-+	 * bus (default)
-+	 * 1 - double data rate ULPI interface with 4 bit wide data
-+	 * bus
-+	 */
-+	int32_t phy_ulpi_ddr;
-+
-+	/**
-+	 * Specifies whether to use the internal or external supply to
-+	 * drive the vbus with a ULPI phy.
-+	 */
-+	int32_t phy_ulpi_ext_vbus;
-+
-+	/**
-+	 * Specifies whether to use the I2Cinterface for full speed PHY. This
-+	 * parameter is only applicable if PHY_TYPE is FS.
-+	 * 0 - No (default)
-+	 * 1 - Yes
-+	 */
-+	int32_t i2c_enable;
-+
-+	int32_t ulpi_fs_ls;
-+
-+	int32_t ts_dline;
-+
-+	/**
-+	 * Specifies whether dedicated transmit FIFOs are
-+	 * enabled for non periodic IN endpoints in device mode
-+	 * 0 - No
-+	 * 1 - Yes
-+	 */
-+	int32_t en_multiple_tx_fifo;
-+
-+	/** Number of 4-byte words in each of the Tx FIFOs in device
-+	 * mode when dynamic FIFO sizing is enabled.
-+	 * 4 to 768 (default 256)
-+	 */
-+	uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
-+
-+	/** Thresholding enable flag-
-+	 * bit 0 - enable non-ISO Tx thresholding
-+	 * bit 1 - enable ISO Tx thresholding
-+	 * bit 2 - enable Rx thresholding
-+	 */
-+	uint32_t thr_ctl;
-+
-+	/** Thresholding length for Tx
-+	 *	FIFOs in 32 bit DWORDs
-+	 */
-+	uint32_t tx_thr_length;
-+
-+	/** Thresholding length for Rx
-+	 *	FIFOs in 32 bit DWORDs
-+	 */
-+	uint32_t rx_thr_length;
-+
-+	/**
-+	 * Specifies whether LPM (Link Power Management) support is enabled
-+	 */
-+	int32_t lpm_enable;
-+
-+	/** Per Transfer Interrupt
-+	 *	mode enable flag
-+	 * 1 - Enabled
-+	 * 0 - Disabled
-+	 */
-+	int32_t pti_enable;
-+
-+	/** Multi Processor Interrupt
-+	 *	mode enable flag
-+	 * 1 - Enabled
-+	 * 0 - Disabled
-+	 */
-+	int32_t mpi_enable;
-+
-+	/** IS_USB Capability
-+	 * 1 - Enabled
-+	 * 0 - Disabled
-+	 */
-+	int32_t ic_usb_cap;
-+
-+	/** AHB Threshold Ratio
-+	 * 2'b00 AHB Threshold = 	MAC Threshold
-+	 * 2'b01 AHB Threshold = 1/2 	MAC Threshold
-+	 * 2'b10 AHB Threshold = 1/4	MAC Threshold
-+	 * 2'b11 AHB Threshold = 1/8	MAC Threshold
-+	 */
-+	int32_t ahb_thr_ratio;
-+
-+	/** ADP Support
-+	 * 1 - Enabled
-+	 * 0 - Disabled
-+	 */
-+	int32_t adp_supp_enable;
-+
-+	/** HFIR Reload Control
-+	 * 0 - The HFIR cannot be reloaded dynamically.
-+	 * 1 - Allow dynamic reloading of the HFIR register during runtime.
-+	 */
-+	int32_t reload_ctl;
-+
-+	/** DCFG: Enable device Out NAK
-+	 * 0 - The core does not set NAK after Bulk Out transfer complete.
-+	 * 1 - The core sets NAK after Bulk OUT transfer complete.
-+	 */
-+	int32_t dev_out_nak;
-+
-+	/** DCFG: Enable Continue on BNA
-+	 * After receiving BNA interrupt the core disables the endpoint,when the
-+	 * endpoint is re-enabled by the application the core starts processing
-+	 * 0 - from the DOEPDMA descriptor
-+	 * 1 - from the descriptor which received the BNA.
-+	 */
-+	int32_t cont_on_bna;
-+
-+	/** GAHBCFG: AHB Single Support
-+	 * This bit when programmed supports SINGLE transfers for remainder
-+	 * data in a transfer for DMA mode of operation.
-+	 * 0 - in this case the remainder data will be sent using INCR burst size.
-+	 * 1 - in this case the remainder data will be sent using SINGLE burst size.
-+	 */
-+	int32_t ahb_single;
-+
-+	/** Core Power down mode
-+	 * 0 - No Power Down is enabled
-+	 * 1 - Reserved
-+	 * 2 - Complete Power Down (Hibernation)
-+	 */
-+	int32_t power_down;
-+
-+	/** OTG revision supported
-+	 * 0 - OTG 1.3 revision
-+	 * 1 - OTG 2.0 revision
-+	 */
-+	int32_t otg_ver;
-+
-+} dwc_otg_core_params_t;
-+
-+#ifdef DEBUG
-+struct dwc_otg_core_if;
-+typedef struct hc_xfer_info {
-+	struct dwc_otg_core_if *core_if;
-+	dwc_hc_t *hc;
-+} hc_xfer_info_t;
-+#endif
-+
-+typedef struct ep_xfer_info {
-+	struct dwc_otg_core_if *core_if;
-+	dwc_ep_t *ep;
-+	uint8_t state;
-+} ep_xfer_info_t;
-+/*
-+ * Device States
-+ */
-+typedef enum dwc_otg_lx_state {
-+	/** On state */
-+	DWC_OTG_L0,
-+	/** LPM sleep state*/
-+	DWC_OTG_L1,
-+	/** USB suspend state*/
-+	DWC_OTG_L2,
-+	/** Off state*/
-+	DWC_OTG_L3
-+} dwc_otg_lx_state_e;
-+
-+struct dwc_otg_global_regs_backup {
-+	uint32_t gotgctl_local;
-+	uint32_t gintmsk_local;
-+	uint32_t gahbcfg_local;
-+	uint32_t gusbcfg_local;
-+	uint32_t grxfsiz_local;
-+	uint32_t gnptxfsiz_local;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	uint32_t glpmcfg_local;
-+#endif
-+	uint32_t gi2cctl_local;
-+	uint32_t hptxfsiz_local;
-+	uint32_t pcgcctl_local;
-+	uint32_t gdfifocfg_local;
-+	uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
-+	uint32_t gpwrdn_local;
-+	uint32_t xhib_pcgcctl;
-+	uint32_t xhib_gpwrdn;
-+};
-+
-+struct dwc_otg_host_regs_backup {
-+	uint32_t hcfg_local;
-+	uint32_t haintmsk_local;
-+	uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
-+	uint32_t hprt0_local;
-+	uint32_t hfir_local;
-+};
-+
-+struct dwc_otg_dev_regs_backup {
-+	uint32_t dcfg;
-+	uint32_t dctl;
-+	uint32_t daintmsk;
-+	uint32_t diepmsk;
-+	uint32_t doepmsk;
-+	uint32_t diepctl[MAX_EPS_CHANNELS];
-+	uint32_t dieptsiz[MAX_EPS_CHANNELS];
-+	uint32_t diepdma[MAX_EPS_CHANNELS];
-+};
-+/**
-+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage
-+ * the DWC_otg controller acting in either host or device mode. It
-+ * represents the programming view of the controller as a whole.
-+ */
-+struct dwc_otg_core_if {
-+	/** Parameters that define how the core should be configured.*/
-+	dwc_otg_core_params_t *core_params;
-+
-+	/** Core Global registers starting at offset 000h. */
-+	dwc_otg_core_global_regs_t *core_global_regs;
-+
-+	/** Device-specific information */
-+	dwc_otg_dev_if_t *dev_if;
-+	/** Host-specific information */
-+	dwc_otg_host_if_t *host_if;
-+
-+	/** Value from SNPSID register */
-+	uint32_t snpsid;
-+
-+	/*
-+	 * Set to 1 if the core PHY interface bits in USBCFG have been
-+	 * initialized.
-+	 */
-+	uint8_t phy_init_done;
-+
-+	/*
-+	 * SRP Success flag, set by srp success interrupt in FS I2C mode
-+	 */
-+	uint8_t srp_success;
-+	uint8_t srp_timer_started;
-+	/** Timer for SRP. If it expires before SRP is successful
-+	 * clear the SRP. */
-+	dwc_timer_t *srp_timer;
-+
-+#ifdef DWC_DEV_SRPCAP
-+	/* This timer is needed to power on the hibernated host core if SRP is not
-+	 * initiated on connected SRP capable device for limited period of time
-+	 */
-+	uint8_t pwron_timer_started;
-+	dwc_timer_t *pwron_timer;
-+#endif
-+	/* Common configuration information */
-+	/** Power and Clock Gating Control Register */
-+	volatile uint32_t *pcgcctl;
-+#define DWC_OTG_PCGCCTL_OFFSET 0xE00
-+
-+	/** Push/pop addresses for endpoints or host channels.*/
-+	uint32_t *data_fifo[MAX_EPS_CHANNELS];
-+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
-+#define DWC_OTG_DATA_FIFO_SIZE 0x1000
-+
-+	/** Total RAM for FIFOs (Bytes) */
-+	uint16_t total_fifo_size;
-+	/** Size of Rx FIFO (Bytes) */
-+	uint16_t rx_fifo_size;
-+	/** Size of Non-periodic Tx FIFO (Bytes) */
-+	uint16_t nperio_tx_fifo_size;
-+
-+	/** 1 if DMA is enabled, 0 otherwise. */
-+	uint8_t dma_enable;
-+
-+	/** 1 if DMA descriptor is enabled, 0 otherwise. */
-+	uint8_t dma_desc_enable;
-+
-+	/** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
-+	uint8_t pti_enh_enable;
-+
-+	/** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
-+	uint8_t multiproc_int_enable;
-+
-+	/** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
-+	uint8_t en_multiple_tx_fifo;
-+
-+	/** Set to 1 if multiple packets of a high-bandwidth transfer is in
-+	 * process of being queued */
-+	uint8_t queuing_high_bandwidth;
-+
-+	/** Hardware Configuration -- stored here for convenience.*/
-+	hwcfg1_data_t hwcfg1;
-+	hwcfg2_data_t hwcfg2;
-+	hwcfg3_data_t hwcfg3;
-+	hwcfg4_data_t hwcfg4;
-+	fifosize_data_t hptxfsiz;
-+
-+	/** Host and Device Configuration -- stored here for convenience.*/
-+	hcfg_data_t hcfg;
-+	dcfg_data_t dcfg;
-+
-+	/** The operational State, during transations
-+	 * (a_host>>a_peripherial and b_device=>b_host) this may not
-+	 * match the core but allows the software to determine
-+	 * transitions.
-+	 */
-+	uint8_t op_state;
-+
-+	/**
-+	 * Set to 1 if the HCD needs to be restarted on a session request
-+	 * interrupt. This is required if no connector ID status change has
-+	 * occurred since the HCD was last disconnected.
-+	 */
-+	uint8_t restart_hcd_on_session_req;
-+
-+	/** HCD callbacks */
-+	/** A-Device is a_host */
-+#define A_HOST		(1)
-+	/** A-Device is a_suspend */
-+#define A_SUSPEND	(2)
-+	/** A-Device is a_peripherial */
-+#define A_PERIPHERAL	(3)
-+	/** B-Device is operating as a Peripheral. */
-+#define B_PERIPHERAL	(4)
-+	/** B-Device is operating as a Host. */
-+#define B_HOST		(5)
-+
-+	/** HCD callbacks */
-+	struct dwc_otg_cil_callbacks *hcd_cb;
-+	/** PCD callbacks */
-+	struct dwc_otg_cil_callbacks *pcd_cb;
-+
-+	/** Device mode Periodic Tx FIFO Mask */
-+	uint32_t p_tx_msk;
-+	/** Device mode Periodic Tx FIFO Mask */
-+	uint32_t tx_msk;
-+
-+	/** Workqueue object used for handling several interrupts */
-+	dwc_workq_t *wq_otg;
-+
-+	/** Timer object used for handling "Wakeup Detected" Interrupt */
-+	dwc_timer_t *wkp_timer;
-+	/** This arrays used for debug purposes for DEV OUT NAK enhancement */
-+	uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
-+	ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
-+	dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
-+#ifdef DEBUG
-+	uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
-+
-+	hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
-+	dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
-+
-+	uint32_t hfnum_7_samples;
-+	uint64_t hfnum_7_frrem_accum;
-+	uint32_t hfnum_0_samples;
-+	uint64_t hfnum_0_frrem_accum;
-+	uint32_t hfnum_other_samples;
-+	uint64_t hfnum_other_frrem_accum;
-+#endif
-+
-+#ifdef DWC_UTE_CFI
-+	uint16_t pwron_rxfsiz;
-+	uint16_t pwron_gnptxfsiz;
-+	uint16_t pwron_txfsiz[15];
-+
-+	uint16_t init_rxfsiz;
-+	uint16_t init_gnptxfsiz;
-+	uint16_t init_txfsiz[15];
-+#endif
-+
-+	/** Lx state of device */
-+	dwc_otg_lx_state_e lx_state;
-+
-+	/** Saved Core Global registers */
-+	struct dwc_otg_global_regs_backup *gr_backup;
-+	/** Saved Host registers */
-+	struct dwc_otg_host_regs_backup *hr_backup;
-+	/** Saved Device registers */
-+	struct dwc_otg_dev_regs_backup *dr_backup;
-+
-+	/** Power Down Enable */
-+	uint32_t power_down;
-+
-+	/** ADP support Enable */
-+	uint32_t adp_enable;
-+
-+	/** ADP structure object */
-+	dwc_otg_adp_t adp;
-+
-+	/** hibernation/suspend flag */
-+	int hibernation_suspend;
-+
-+	/** Device mode extended hibernation flag */
-+	int xhib;
-+
-+	/** OTG revision supported */
-+	uint32_t otg_ver;
-+
-+	/** OTG status flag used for HNP polling */
-+	uint8_t otg_sts;
-+
-+	/** Pointer to either hcd->lock or pcd->lock */
-+	dwc_spinlock_t *lock;
-+
-+	/** Start predict NextEP based on Learning Queue if equal 1,
-+	 * also used as counter of disabled NP IN EP's */
-+	uint8_t start_predict;
-+
-+	/** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
-+	 * active, 0xff otherwise */
-+	uint8_t nextep_seq[MAX_EPS_CHANNELS];
-+
-+	/** Index of fisrt EP in nextep_seq array which should be re-enabled **/
-+	uint8_t first_in_nextep_seq;
-+
-+	/** Frame number while entering to ISR - needed for ISOCs **/
-+	uint32_t frame_num;
-+
-+};
-+
-+#ifdef DEBUG
-+/*
-+ * This function is called when transfer is timed out.
-+ */
-+extern void hc_xfer_timeout(void *ptr);
-+#endif
-+
-+/*
-+ * This function is called when transfer is timed out on endpoint.
-+ */
-+extern void ep_xfer_timeout(void *ptr);
-+
-+/*
-+ * The following functions are functions for works
-+ * using during handling some interrupts
-+ */
-+extern void w_conn_id_status_change(void *p);
-+
-+extern void w_wakeup_detected(void *p);
-+
-+/** Saves global register values into system memory. */
-+extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
-+/** Saves device register values into system memory. */
-+extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
-+/** Saves host register values into system memory. */
-+extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
-+/** Restore global register values. */
-+extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
-+/** Restore host register values. */
-+extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
-+/** Restore device register values. */
-+extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
-+				    int rem_wakeup);
-+extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
-+extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
-+				  int is_host);
-+
-+extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
-+					    int restore_mode, int reset);
-+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
-+					      int rem_wakeup, int reset);
-+
-+/*
-+ * The following functions support initialization of the CIL driver component
-+ * and the DWC_otg controller.
-+ */
-+extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
-+
-+/** @name Device CIL Functions
-+ * The following functions support managing the DWC_otg controller in device
-+ * mode.
-+ */
-+/**@{*/
-+extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
-+				      uint32_t * _dest);
-+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
-+				      dwc_ep_t * _ep);
-+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
-+					 dwc_ep_t * _ep);
-+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
-+				       dwc_ep_t * _ep);
-+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
-+					  dwc_ep_t * _ep);
-+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
-+				    dwc_ep_t * _ep, int _dma);
-+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
-+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
-+				   dwc_ep_t * _ep);
-+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+#ifdef DWC_EN_ISOC
-+extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
-+					      dwc_ep_t * ep);
-+extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
-+					      dwc_ep_t * ep);
-+#endif /* DWC_EN_ISOC */
-+/**@}*/
-+
-+/** @name Host CIL Functions
-+ * The following functions support managing the DWC_otg controller in host
-+ * mode.
-+ */
-+/**@{*/
-+extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
-+			    dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
-+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
-+				      dwc_hc_t * _hc);
-+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
-+					dwc_hc_t * _hc);
-+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
-+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
-+				    dwc_hc_t * _hc);
-+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
-+					   dwc_hc_t * hc);
-+
-+extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
-+
-+/* Macro used to clear one channel interrupt */
-+#define clear_hc_int(_hc_regs_, _intr_) \
-+do { \
-+	hcint_data_t hcint_clear = {.d32 = 0}; \
-+	hcint_clear.b._intr_ = 1; \
-+	DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
-+} while (0)
-+
-+/*
-+ * Macro used to disable one channel interrupt. Channel interrupts are
-+ * disabled when the channel is halted or released by the interrupt handler.
-+ * There is no need to handle further interrupts of that type until the
-+ * channel is re-assigned. In fact, subsequent handling may cause crashes
-+ * because the channel structures are cleaned up when the channel is released.
-+ */
-+#define disable_hc_int(_hc_regs_, _intr_) \
-+do { \
-+	hcintmsk_data_t hcintmsk = {.d32 = 0}; \
-+	hcintmsk.b._intr_ = 1; \
-+	DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
-+} while (0)
-+
-+/**
-+ * This function Reads HPRT0 in preparation to modify. It keeps the
-+ * WC bits 0 so that if they are read as 1, they won't clear when you
-+ * write it back
-+ */
-+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
-+{
-+	hprt0_data_t hprt0;
-+	hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
-+	hprt0.b.prtena = 0;
-+	hprt0.b.prtconndet = 0;
-+	hprt0.b.prtenchng = 0;
-+	hprt0.b.prtovrcurrchng = 0;
-+	return hprt0.d32;
-+}
-+
-+/**@}*/
-+
-+/** @name Common CIL Functions
-+ * The following functions support managing the DWC_otg controller in either
-+ * device or host mode.
-+ */
-+/**@{*/
-+
-+extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
-+				uint8_t * dest, uint16_t bytes);
-+
-+extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
-+extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
-+
-+/**
-+ * This function returns the Core Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
-+{
-+	return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
-+		DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
-+}
-+
-+/**
-+ * This function returns the OTG Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
-+{
-+	return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
-+}
-+
-+/**
-+ * This function reads the Device All Endpoints Interrupt register and
-+ * returns the IN endpoint interrupt bits.
-+ */
-+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
-+						       core_if)
-+{
-+
-+	uint32_t v;
-+
-+	if (core_if->multiproc_int_enable) {
-+		v = DWC_READ_REG32(&core_if->dev_if->
-+				   dev_global_regs->deachint) &
-+		    DWC_READ_REG32(&core_if->
-+				   dev_if->dev_global_regs->deachintmsk);
-+	} else {
-+		v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
-+		    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+	}
-+	return (v & 0xffff);
-+}
-+
-+/**
-+ * This function reads the Device All Endpoints Interrupt register and
-+ * returns the OUT endpoint interrupt bits.
-+ */
-+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
-+							core_if)
-+{
-+	uint32_t v;
-+
-+	if (core_if->multiproc_int_enable) {
-+		v = DWC_READ_REG32(&core_if->dev_if->
-+				   dev_global_regs->deachint) &
-+		    DWC_READ_REG32(&core_if->
-+				   dev_if->dev_global_regs->deachintmsk);
-+	} else {
-+		v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
-+		    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
-+	}
-+
-+	return ((v & 0xffff0000) >> 16);
-+}
-+
-+/**
-+ * This function returns the Device IN EP Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
-+						   dwc_ep_t * ep)
-+{
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	uint32_t v, msk, emp;
-+
-+	if (core_if->multiproc_int_enable) {
-+		msk =
-+		    DWC_READ_REG32(&dev_if->
-+				   dev_global_regs->diepeachintmsk[ep->num]);
-+		emp =
-+		    DWC_READ_REG32(&dev_if->
-+				   dev_global_regs->dtknqr4_fifoemptymsk);
-+		msk |= ((emp >> ep->num) & 0x1) << 7;
-+		v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
-+	} else {
-+		msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
-+		emp =
-+		    DWC_READ_REG32(&dev_if->
-+				   dev_global_regs->dtknqr4_fifoemptymsk);
-+		msk |= ((emp >> ep->num) & 0x1) << 7;
-+		v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
-+	}
-+
-+	return v;
-+}
-+
-+/**
-+ * This function returns the Device OUT EP Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
-+						    _core_if, dwc_ep_t * _ep)
-+{
-+	dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
-+	uint32_t v;
-+	doepmsk_data_t msk = {.d32 = 0 };
-+
-+	if (_core_if->multiproc_int_enable) {
-+		msk.d32 =
-+		    DWC_READ_REG32(&dev_if->
-+				   dev_global_regs->doepeachintmsk[_ep->num]);
-+		if (_core_if->pti_enh_enable) {
-+			msk.b.pktdrpsts = 1;
-+		}
-+		v = DWC_READ_REG32(&dev_if->
-+				   out_ep_regs[_ep->num]->doepint) & msk.d32;
-+	} else {
-+		msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
-+		if (_core_if->pti_enh_enable) {
-+			msk.b.pktdrpsts = 1;
-+		}
-+		v = DWC_READ_REG32(&dev_if->
-+				   out_ep_regs[_ep->num]->doepint) & msk.d32;
-+	}
-+	return v;
-+}
-+
-+/**
-+ * This function returns the Host All Channel Interrupt register
-+ */
-+static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
-+							   _core_if)
-+{
-+	return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
-+}
-+
-+static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
-+						      _core_if, dwc_hc_t * _hc)
-+{
-+	return (DWC_READ_REG32
-+		(&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
-+}
-+
-+/**
-+ * This function returns the mode of the operation, host or device.
-+ *
-+ * @return 0 - Device Mode, 1 - Host Mode
-+ */
-+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
-+{
-+	return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
-+}
-+
-+/**@}*/
-+
-+/**
-+ * DWC_otg CIL callback structure. This structure allows the HCD and
-+ * PCD to register functions used for starting and stopping the PCD
-+ * and HCD for role change on for a DRD.
-+ */
-+typedef struct dwc_otg_cil_callbacks {
-+	/** Start function for role change */
-+	int (*start) (void *_p);
-+	/** Stop Function for role change */
-+	int (*stop) (void *_p);
-+	/** Disconnect Function for role change */
-+	int (*disconnect) (void *_p);
-+	/** Resume/Remote wakeup Function */
-+	int (*resume_wakeup) (void *_p);
-+	/** Suspend function */
-+	int (*suspend) (void *_p);
-+	/** Session Start (SRP) */
-+	int (*session_start) (void *_p);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	/** Sleep (switch to L0 state) */
-+	int (*sleep) (void *_p);
-+#endif
-+	/** Pointer passed to start() and stop() */
-+	void *p;
-+} dwc_otg_cil_callbacks_t;
-+
-+extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
-+					       dwc_otg_cil_callbacks_t * _cb,
-+					       void *_p);
-+extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
-+					       dwc_otg_cil_callbacks_t * _cb,
-+					       void *_p);
-+
-+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
-+
-+//////////////////////////////////////////////////////////////////////
-+/** Start the HCD.  Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->hcd_cb && core_if->hcd_cb->start) {
-+		core_if->hcd_cb->start(core_if->hcd_cb->p);
-+	}
-+}
-+
-+/** Stop the HCD.  Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->hcd_cb && core_if->hcd_cb->stop) {
-+		core_if->hcd_cb->stop(core_if->hcd_cb->p);
-+	}
-+}
-+
-+/** Disconnect the HCD.  Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
-+		core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
-+	}
-+}
-+
-+/** Inform the HCD the a New Session has begun.  Helper function for
-+ * using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
-+		core_if->hcd_cb->session_start(core_if->hcd_cb->p);
-+	}
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * Inform the HCD about LPM sleep.
-+ * Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
-+		core_if->hcd_cb->sleep(core_if->hcd_cb->p);
-+	}
-+}
-+#endif
-+
-+/** Resume the HCD.  Helper function for using the HCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
-+		core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
-+	}
-+}
-+
-+/** Start the PCD.  Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->pcd_cb && core_if->pcd_cb->start) {
-+		core_if->pcd_cb->start(core_if->pcd_cb->p);
-+	}
-+}
-+
-+/** Stop the PCD.  Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->pcd_cb && core_if->pcd_cb->stop) {
-+		core_if->pcd_cb->stop(core_if->pcd_cb->p);
-+	}
-+}
-+
-+/** Suspend the PCD.  Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
-+		core_if->pcd_cb->suspend(core_if->pcd_cb->p);
-+	}
-+}
-+
-+/** Resume the PCD.  Helper function for using the PCD callbacks.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
-+{
-+	if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+		core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+	}
-+}
-+
-+//////////////////////////////////////////////////////////////////////
-+
-+#endif
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
-@@ -0,0 +1,1596 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
-+ * $Revision: #32 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ *
-+ * The Core Interface Layer provides basic services for accessing and
-+ * managing the DWC_otg hardware. These services are used by both the
-+ * Host Controller Driver and the Peripheral Controller Driver.
-+ *
-+ * This file contains the Common Interrupt handlers.
-+ */
-+#include "dwc_os.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_hcd.h"
-+
-+#ifdef DEBUG
-+inline const char *op_state_str(dwc_otg_core_if_t * core_if)
-+{
-+	return (core_if->op_state == A_HOST ? "a_host" :
-+		(core_if->op_state == A_SUSPEND ? "a_suspend" :
-+		 (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
-+		  (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
-+		   (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
-+}
-+#endif
-+
-+/** This function will log a debug message
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
-+{
-+	gintsts_data_t gintsts;
-+	DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
-+		 dwc_otg_mode(core_if) ? "Host" : "Device");
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.modemismatch = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+	return 1;
-+}
-+
-+/**
-+ * This function handles the OTG Interrupts. It reads the OTG
-+ * Interrupt Register (GOTGINT) to determine what interrupt has
-+ * occurred.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	gotgint_data_t gotgint;
-+	gotgctl_data_t gotgctl;
-+	gintmsk_data_t gintmsk;
-+	gpwrdn_data_t gpwrdn;
-+
-+	gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
-+	gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+	DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
-+		    op_state_str(core_if));
-+
-+	if (gotgint.b.sesenddet) {
-+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+			    "Session End Detected++ (%s)\n",
-+			    op_state_str(core_if));
-+		gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+
-+		if (core_if->op_state == B_HOST) {
-+			cil_pcd_start(core_if);
-+			core_if->op_state = B_PERIPHERAL;
-+		} else {
-+			/* If not B_HOST and Device HNP still set. HNP
-+			 * Did not succeed!*/
-+			if (gotgctl.b.devhnpen) {
-+				DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
-+				__DWC_ERROR("Device Not Connected/Responding!\n");
-+			}
-+
-+			/* If Session End Detected the B-Cable has
-+			 * been disconnected. */
-+			/* Reset PCD and Gadget driver to a
-+			 * clean state. */
-+			core_if->lx_state = DWC_OTG_L0;
-+			DWC_SPINUNLOCK(core_if->lock);
-+			cil_pcd_stop(core_if);
-+			DWC_SPINLOCK(core_if->lock);
-+
-+			if (core_if->adp_enable) {
-+				if (core_if->power_down == 2) {
-+					gpwrdn.d32 = 0;
-+					gpwrdn.b.pwrdnswtch = 1;
-+					DWC_MODIFY_REG32(&core_if->
-+							 core_global_regs->
-+							 gpwrdn, gpwrdn.d32, 0);
-+				}
-+
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pmuintsel = 1;
-+				gpwrdn.b.pmuactv = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+
-+				dwc_otg_adp_sense_start(core_if);
-+			}
-+		}
-+
-+		gotgctl.d32 = 0;
-+		gotgctl.b.devhnpen = 1;
-+		DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+	}
-+	if (gotgint.b.sesreqsucstschng) {
-+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+			    "Session Reqeust Success Status Change++\n");
-+		gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+		if (gotgctl.b.sesreqscs) {
-+
-+			if ((core_if->core_params->phy_type ==
-+			     DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
-+				core_if->srp_success = 1;
-+			} else {
-+				DWC_SPINUNLOCK(core_if->lock);
-+				cil_pcd_resume(core_if);
-+				DWC_SPINLOCK(core_if->lock);
-+				/* Clear Session Request */
-+				gotgctl.d32 = 0;
-+				gotgctl.b.sesreq = 1;
-+				DWC_MODIFY_REG32(&global_regs->gotgctl,
-+						 gotgctl.d32, 0);
-+			}
-+		}
-+	}
-+	if (gotgint.b.hstnegsucstschng) {
-+		/* Print statements during the HNP interrupt handling
-+		 * can cause it to fail.*/
-+		gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
-+		/* WA for 3.00a- HW is not setting cur_mode, even sometimes
-+		 * this does not help*/
-+		if (core_if->snpsid >= OTG_CORE_REV_3_00a)
-+			dwc_udelay(100);
-+		if (gotgctl.b.hstnegscs) {
-+			if (dwc_otg_is_host_mode(core_if)) {
-+				core_if->op_state = B_HOST;
-+				/*
-+				 * Need to disable SOF interrupt immediately.
-+				 * When switching from device to host, the PCD
-+				 * interrupt handler won't handle the
-+				 * interrupt if host mode is already set. The
-+				 * HCD interrupt handler won't get called if
-+				 * the HCD state is HALT. This means that the
-+				 * interrupt does not get handled and Linux
-+				 * complains loudly.
-+				 */
-+				gintmsk.d32 = 0;
-+				gintmsk.b.sofintr = 1;
-+				DWC_MODIFY_REG32(&global_regs->gintmsk,
-+						 gintmsk.d32, 0);
-+				/* Call callback function with spin lock released */
-+				DWC_SPINUNLOCK(core_if->lock);
-+				cil_pcd_stop(core_if);
-+				/*
-+				 * Initialize the Core for Host mode.
-+				 */
-+				cil_hcd_start(core_if);
-+				DWC_SPINLOCK(core_if->lock);
-+				core_if->op_state = B_HOST;
-+			}
-+		} else {
-+			gotgctl.d32 = 0;
-+			gotgctl.b.hnpreq = 1;
-+			gotgctl.b.devhnpen = 1;
-+			DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
-+			DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
-+			__DWC_ERROR("Device Not Connected/Responding\n");
-+		}
-+	}
-+	if (gotgint.b.hstnegdet) {
-+		/* The disconnect interrupt is set at the same time as
-+		 * Host Negotiation Detected.  During the mode
-+		 * switch all interrupts are cleared so the disconnect
-+		 * interrupt handler will not get executed.
-+		 */
-+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+			    "Host Negotiation Detected++ (%s)\n",
-+			    (dwc_otg_is_host_mode(core_if) ? "Host" :
-+			     "Device"));
-+		if (dwc_otg_is_device_mode(core_if)) {
-+			DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
-+				    core_if->op_state);
-+			DWC_SPINUNLOCK(core_if->lock);
-+			cil_hcd_disconnect(core_if);
-+			cil_pcd_start(core_if);
-+			DWC_SPINLOCK(core_if->lock);
-+			core_if->op_state = A_PERIPHERAL;
-+		} else {
-+			/*
-+			 * Need to disable SOF interrupt immediately. When
-+			 * switching from device to host, the PCD interrupt
-+			 * handler won't handle the interrupt if host mode is
-+			 * already set. The HCD interrupt handler won't get
-+			 * called if the HCD state is HALT. This means that
-+			 * the interrupt does not get handled and Linux
-+			 * complains loudly.
-+			 */
-+			gintmsk.d32 = 0;
-+			gintmsk.b.sofintr = 1;
-+			DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
-+			DWC_SPINUNLOCK(core_if->lock);
-+			cil_pcd_stop(core_if);
-+			cil_hcd_start(core_if);
-+			DWC_SPINLOCK(core_if->lock);
-+			core_if->op_state = A_HOST;
-+		}
-+	}
-+	if (gotgint.b.adevtoutchng) {
-+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
-+			    "A-Device Timeout Change++\n");
-+	}
-+	if (gotgint.b.debdone) {
-+		DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
-+	}
-+
-+	/* Clear GOTGINT */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
-+
-+	return 1;
-+}
-+
-+void w_conn_id_status_change(void *p)
-+{
-+	dwc_otg_core_if_t *core_if = p;
-+	uint32_t count = 0;
-+	gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+	gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+	DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
-+	DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
-+
-+	/* B-Device connector (Device Mode) */
-+	if (gotgctl.b.conidsts) {
-+		/* Wait for switch to device mode. */
-+		while (!dwc_otg_is_device_mode(core_if)) {
-+			DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
-+				   (dwc_otg_is_host_mode(core_if) ? "Host" :
-+				    "Peripheral"));
-+			dwc_mdelay(100);
-+			if (++count > 10000)
-+				break;
-+		}
-+		DWC_ASSERT(++count < 10000,
-+			   "Connection id status change timed out");
-+		core_if->op_state = B_PERIPHERAL;
-+		dwc_otg_core_init(core_if);
-+		dwc_otg_enable_global_interrupts(core_if);
-+		cil_pcd_start(core_if);
-+	} else {
-+		/* A-Device connector (Host Mode) */
-+		while (!dwc_otg_is_host_mode(core_if)) {
-+			DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
-+				   (dwc_otg_is_host_mode(core_if) ? "Host" :
-+				    "Peripheral"));
-+			dwc_mdelay(100);
-+			if (++count > 10000)
-+				break;
-+		}
-+		DWC_ASSERT(++count < 10000,
-+			   "Connection id status change timed out");
-+		core_if->op_state = A_HOST;
-+		/*
-+		 * Initialize the Core for Host mode.
-+		 */
-+		dwc_otg_core_init(core_if);
-+		dwc_otg_enable_global_interrupts(core_if);
-+		cil_hcd_start(core_if);
-+	}
-+}
-+
-+/**
-+ * This function handles the Connector ID Status Change Interrupt.  It
-+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this
-+ * is a Device to Host Mode transition or a Host Mode to Device
-+ * Transition.
-+ *
-+ * This only occurs when the cable is connected/removed from the PHY
-+ * connector.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
-+{
-+
-+	/*
-+	 * Need to disable SOF interrupt immediately. If switching from device
-+	 * to host, the PCD interrupt handler won't handle the interrupt if
-+	 * host mode is already set. The HCD interrupt handler won't get
-+	 * called if the HCD state is HALT. This means that the interrupt does
-+	 * not get handled and Linux complains loudly.
-+	 */
-+	gintmsk_data_t gintmsk = {.d32 = 0 };
-+	gintsts_data_t gintsts = {.d32 = 0 };
-+
-+	gintmsk.b.sofintr = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+
-+	DWC_DEBUGPL(DBG_CIL,
-+		    " ++Connector ID Status Change Interrupt++  (%s)\n",
-+		    (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
-+
-+	DWC_SPINUNLOCK(core_if->lock);
-+
-+	/*
-+	 * Need to schedule a work, as there are possible DELAY function calls
-+	 * Release lock before scheduling workq as it holds spinlock during scheduling
-+	 */
-+
-+	DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
-+			   core_if, "connection id status change");
-+	DWC_SPINLOCK(core_if->lock);
-+
-+	/* Set flag and clear interrupt */
-+	gintsts.b.conidstschng = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that a device is initiating the Session
-+ * Request Protocol to request the host to turn on bus power so a new
-+ * session can begin. The handler responds by turning on bus power. If
-+ * the DWC_otg controller is in low power mode, the handler brings the
-+ * controller out of low power mode before turning on bus power.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
-+{
-+	gintsts_data_t gintsts;
-+
-+#ifndef DWC_HOST_ONLY
-+	DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
-+
-+	if (dwc_otg_is_device_mode(core_if)) {
-+		DWC_PRINTF("SRP: Device mode\n");
-+	} else {
-+		hprt0_data_t hprt0;
-+		DWC_PRINTF("SRP: Host mode\n");
-+
-+		/* Turn on the port power bit. */
-+		hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+		hprt0.b.prtpwr = 1;
-+		DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+		/* Start the Connection timer. So a message can be displayed
-+		 * if connect does not occur within 10 seconds. */
-+		cil_hcd_session_start(core_if);
-+	}
-+#endif
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.sessreqintr = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+
-+void w_wakeup_detected(void *p)
-+{
-+	dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
-+	/*
-+	 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
-+	 * so that OPT tests pass with all PHYs).
-+	 */
-+	hprt0_data_t hprt0 = {.d32 = 0 };
-+#if 0
-+	pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+	/* Restart the Phy Clock */
-+	pcgcctl.b.stoppclk = 1;
-+	DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+	dwc_udelay(10);
-+#endif //0
-+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+	DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
-+//      dwc_mdelay(70);
-+	hprt0.b.prtres = 0;	/* Resume */
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+	DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
-+		    DWC_READ_REG32(core_if->host_if->hprt0));
-+
-+	cil_hcd_resume(core_if);
-+
-+	/** Change to L0 state*/
-+	core_if->lx_state = DWC_OTG_L0;
-+}
-+
-+/**
-+ * This interrupt indicates that the DWC_otg controller has detected a
-+ * resume or remote wakeup sequence. If the DWC_otg controller is in
-+ * low power mode, the handler must brings the controller out of low
-+ * power mode. The controller automatically begins resume
-+ * signaling. The handler schedules a time to stop resume signaling.
-+ */
-+int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
-+{
-+	gintsts_data_t gintsts;
-+
-+	DWC_DEBUGPL(DBG_ANY,
-+		    "++Resume and Remote Wakeup Detected Interrupt++\n");
-+
-+	DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
-+
-+	if (dwc_otg_is_device_mode(core_if)) {
-+		dctl_data_t dctl = {.d32 = 0 };
-+		DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
-+			    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
-+					   dsts));
-+		if (core_if->lx_state == DWC_OTG_L2) {
-+#ifdef PARTIAL_POWER_DOWN
-+			if (core_if->hwcfg4.b.power_optimiz) {
-+				pcgcctl_data_t power = {.d32 = 0 };
-+
-+				power.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+				DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
-+					    power.d32);
-+
-+				power.b.stoppclk = 0;
-+				DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+				power.b.pwrclmp = 0;
-+				DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+				power.b.rstpdwnmodule = 0;
-+				DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+			}
-+#endif
-+			/* Clear the Remote Wakeup Signaling */
-+			dctl.b.rmtwkupsig = 1;
-+			DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+					 dctl, dctl.d32, 0);
-+
-+			DWC_SPINUNLOCK(core_if->lock);
-+			if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+				core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+			}
-+			DWC_SPINLOCK(core_if->lock);
-+		} else {
-+			glpmcfg_data_t lpmcfg;
-+			lpmcfg.d32 =
-+			    DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+			lpmcfg.b.hird_thres &= (~(1 << 4));
-+			DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
-+					lpmcfg.d32);
-+		}
-+		/** Change to L0 state*/
-+		core_if->lx_state = DWC_OTG_L0;
-+	} else {
-+		if (core_if->lx_state != DWC_OTG_L1) {
-+			pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+
-+			/* Restart the Phy Clock */
-+			pcgcctl.b.stoppclk = 1;
-+			DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+			DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
-+		} else {
-+			/** Change to L0 state*/
-+			core_if->lx_state = DWC_OTG_L0;
-+		}
-+	}
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.wkupintr = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * Device disconnect.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
-+{
-+	gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+	gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
-+	gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+	DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+	if (!core_if->hibernation_suspend) {
-+		DWC_PRINTF("Already exited from Hibernation\n");
-+		return 1;
-+	}
-+
-+	/* Switch on the voltage to the core */
-+	gpwrdn.b.pwrdnswtch = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Reset the core */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Disable power clamps*/
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnclmp = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	/* Remove reset the core signal */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+	dwc_udelay(10);
-+
-+	/* Disable PMU interrupt */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuintsel = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	core_if->hibernation_suspend = 0;
-+
-+	/* Disable PMU */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuactv = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	if (gpwrdn_temp.b.idsts) {
-+		core_if->op_state = B_PERIPHERAL;
-+		dwc_otg_core_init(core_if);
-+		dwc_otg_enable_global_interrupts(core_if);
-+		cil_pcd_start(core_if);
-+	} else {
-+		core_if->op_state = A_HOST;
-+		dwc_otg_core_init(core_if);
-+		dwc_otg_enable_global_interrupts(core_if);
-+		cil_hcd_start(core_if);
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * remote wakeup sequence.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
-+{
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	DWC_DEBUGPL(DBG_ANY,
-+		    "++Powerdown Remote Wakeup Detected Interrupt++\n");
-+
-+	if (!core_if->hibernation_suspend) {
-+		DWC_PRINTF("Already exited from Hibernation\n");
-+		return 1;
-+	}
-+
-+	gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+	if (gpwrdn.b.idsts) {	// Device Mode
-+		if ((core_if->power_down == 2)
-+		    && (core_if->hibernation_suspend == 1)) {
-+			dwc_otg_device_hibernation_restore(core_if, 0, 0);
-+		}
-+	} else {
-+		if ((core_if->power_down == 2)
-+		    && (core_if->hibernation_suspend == 1)) {
-+			dwc_otg_host_hibernation_restore(core_if, 1, 0);
-+		}
-+	}
-+	return 1;
-+}
-+
-+static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
-+{
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
-+	dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+	DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+	gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+	if (core_if->power_down == 2) {
-+		if (!core_if->hibernation_suspend) {
-+			DWC_PRINTF("Already exited from Hibernation\n");
-+			return 1;
-+		}
-+		DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
-+		/* Switch on the voltage to the core */
-+		gpwrdn.b.pwrdnswtch = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		dwc_udelay(10);
-+
-+		/* Reset the core */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pwrdnrstn = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		dwc_udelay(10);
-+
-+		/* Disable power clamps */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pwrdnclmp = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+		/* Remove reset the core signal */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pwrdnrstn = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+		dwc_udelay(10);
-+
-+		/* Disable PMU interrupt */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pmuintsel = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+		/*Indicates that we are exiting from hibernation */
-+		core_if->hibernation_suspend = 0;
-+
-+		/* Disable PMU */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pmuactv = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		dwc_udelay(10);
-+
-+		gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
-+		if (gpwrdn.b.dis_vbus == 1) {
-+			gpwrdn.d32 = 0;
-+			gpwrdn.b.dis_vbus = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		}
-+
-+		if (gpwrdn_temp.b.idsts) {
-+			core_if->op_state = B_PERIPHERAL;
-+			dwc_otg_core_init(core_if);
-+			dwc_otg_enable_global_interrupts(core_if);
-+			cil_pcd_start(core_if);
-+		} else {
-+			core_if->op_state = A_HOST;
-+			dwc_otg_core_init(core_if);
-+			dwc_otg_enable_global_interrupts(core_if);
-+			cil_hcd_start(core_if);
-+		}
-+	}
-+
-+	if (core_if->adp_enable) {
-+		uint8_t is_host = 0;
-+		DWC_SPINUNLOCK(core_if->lock);
-+		/* Change the core_if's lock to hcd/pcd lock depend on mode? */
-+#ifndef DWC_HOST_ONLY
-+		if (gpwrdn_temp.b.idsts)
-+			core_if->lock = otg_dev->pcd->lock;
-+#endif
-+#ifndef DWC_DEVICE_ONLY
-+		if (!gpwrdn_temp.b.idsts) {
-+				core_if->lock = otg_dev->hcd->lock;
-+				is_host = 1;
-+		}
-+#endif
-+		DWC_PRINTF("RESTART ADP\n");
-+		if (core_if->adp.probe_enabled)
-+			dwc_otg_adp_probe_stop(core_if);
-+		if (core_if->adp.sense_enabled)
-+			dwc_otg_adp_sense_stop(core_if);
-+		if (core_if->adp.sense_timer_started)
-+			DWC_TIMER_CANCEL(core_if->adp.sense_timer);
-+		if (core_if->adp.vbuson_timer_started)
-+			DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
-+		core_if->adp.probe_timer_values[0] = -1;
-+		core_if->adp.probe_timer_values[1] = -1;
-+		core_if->adp.sense_timer_started = 0;
-+		core_if->adp.vbuson_timer_started = 0;
-+		core_if->adp.probe_counter = 0;
-+		core_if->adp.gpwrdn = 0;
-+
-+		/* Disable PMU and restart ADP */
-+		gpwrdn_temp.d32 = 0;
-+		gpwrdn_temp.b.pmuactv = 1;
-+		gpwrdn_temp.b.pmuintsel = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		DWC_PRINTF("Check point 1\n");
-+		dwc_mdelay(110);
-+		dwc_otg_adp_start(core_if, is_host);
-+		DWC_SPINLOCK(core_if->lock);
-+	}
-+
-+
-+	return 1;
-+}
-+
-+static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
-+{
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	int32_t otg_cap_param = core_if->core_params->otg_cap;
-+	DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+
-+	gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+	if (core_if->power_down == 2) {
-+		if (!core_if->hibernation_suspend) {
-+			DWC_PRINTF("Already exited from Hibernation\n");
-+			return 1;
-+		}
-+
-+		if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
-+			 otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
-+			gpwrdn.b.bsessvld == 0) {
-+			/* Save gpwrdn register for further usage if stschng interrupt */
-+			core_if->gr_backup->gpwrdn_local =
-+				DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+			/*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
-+			return 1;
-+		}
-+
-+		/* Switch on the voltage to the core */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pwrdnswtch = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		dwc_udelay(10);
-+
-+		/* Reset the core */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pwrdnrstn = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		dwc_udelay(10);
-+
-+		/* Disable power clamps */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pwrdnclmp = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+		/* Remove reset the core signal */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pwrdnrstn = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+		dwc_udelay(10);
-+
-+		/* Disable PMU interrupt */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pmuintsel = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		dwc_udelay(10);
-+
-+		/*Indicates that we are exiting from hibernation */
-+		core_if->hibernation_suspend = 0;
-+
-+		/* Disable PMU */
-+		gpwrdn.d32 = 0;
-+		gpwrdn.b.pmuactv = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+		dwc_udelay(10);
-+
-+		core_if->op_state = B_PERIPHERAL;
-+		dwc_otg_core_init(core_if);
-+		dwc_otg_enable_global_interrupts(core_if);
-+		cil_pcd_start(core_if);
-+
-+		if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
-+			otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
-+			/*
-+			 * Initiate SRP after initial ADP probe.
-+			 */
-+			dwc_otg_initiate_srp(core_if);
-+		}
-+	}
-+
-+	return 1;
-+}
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * status change either on IDDIG or BSessVld.
-+ */
-+static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
-+{
-+	int retval;
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
-+	dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+
-+	DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+	if (core_if->power_down == 2) {
-+		if (core_if->hibernation_suspend <= 0) {
-+			DWC_PRINTF("Already exited from Hibernation\n");
-+			return 1;
-+		} else
-+			gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
-+
-+	} else {
-+		gpwrdn_temp.d32 = core_if->adp.gpwrdn;
-+	}
-+
-+	gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+	if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
-+		retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
-+	} else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
-+		retval = dwc_otg_handle_pwrdn_session_change(core_if);
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This interrupt indicates that the Wakeup Logic has detected a
-+ * SRP.
-+ */
-+static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
-+{
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+
-+	DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+	if (!core_if->hibernation_suspend) {
-+		DWC_PRINTF("Already exited from Hibernation\n");
-+		return 1;
-+	}
-+#ifdef DWC_DEV_SRPCAP
-+	if (core_if->pwron_timer_started) {
-+		core_if->pwron_timer_started = 0;
-+		DWC_TIMER_CANCEL(core_if->pwron_timer);
-+	}
-+#endif
-+
-+	/* Switch on the voltage to the core */
-+	gpwrdn.b.pwrdnswtch = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Reset the core */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Disable power clamps */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnclmp = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	/* Remove reset the core signal */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+	dwc_udelay(10);
-+
-+	/* Disable PMU interrupt */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuintsel = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	/* Indicates that we are exiting from hibernation */
-+	core_if->hibernation_suspend = 0;
-+
-+	/* Disable PMU */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuactv = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Programm Disable VBUS to 0 */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.dis_vbus = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	/*Initialize the core as Host */
-+	core_if->op_state = A_HOST;
-+	dwc_otg_core_init(core_if);
-+	dwc_otg_enable_global_interrupts(core_if);
-+	cil_hcd_start(core_if);
-+
-+	return 1;
-+}
-+
-+/** This interrupt indicates that restore command after Hibernation
-+ * was completed by the core. */
-+int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
-+{
-+	pcgcctl_data_t pcgcctl;
-+	DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
-+
-+	//TODO De-assert restore signal. 8.a
-+	pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+	if (pcgcctl.b.restoremode == 1) {
-+		gintmsk_data_t gintmsk = {.d32 = 0 };
-+		/*
-+		 * If restore mode is Remote Wakeup,
-+		 * unmask Remote Wakeup interrupt.
-+		 */
-+		gintmsk.b.wkupintr = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+				 0, gintmsk.d32);
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that a device has been disconnected from
-+ * the root port.
-+ */
-+int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
-+{
-+	gintsts_data_t gintsts;
-+
-+	DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
-+		    (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
-+		    op_state_str(core_if));
-+
-+/** @todo Consolidate this if statement. */
-+#ifndef DWC_HOST_ONLY
-+	if (core_if->op_state == B_HOST) {
-+		/* If in device mode Disconnect and stop the HCD, then
-+		 * start the PCD. */
-+		DWC_SPINUNLOCK(core_if->lock);
-+		cil_hcd_disconnect(core_if);
-+		cil_pcd_start(core_if);
-+		DWC_SPINLOCK(core_if->lock);
-+		core_if->op_state = B_PERIPHERAL;
-+	} else if (dwc_otg_is_device_mode(core_if)) {
-+		gotgctl_data_t gotgctl = {.d32 = 0 };
-+		gotgctl.d32 =
-+		    DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
-+		if (gotgctl.b.hstsethnpen == 1) {
-+			/* Do nothing, if HNP in process the OTG
-+			 * interrupt "Host Negotiation Detected"
-+			 * interrupt will do the mode switch.
-+			 */
-+		} else if (gotgctl.b.devhnpen == 0) {
-+			/* If in device mode Disconnect and stop the HCD, then
-+			 * start the PCD. */
-+			DWC_SPINUNLOCK(core_if->lock);
-+			cil_hcd_disconnect(core_if);
-+			cil_pcd_start(core_if);
-+			DWC_SPINLOCK(core_if->lock);
-+			core_if->op_state = B_PERIPHERAL;
-+		} else {
-+			DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
-+		}
-+	} else {
-+		if (core_if->op_state == A_HOST) {
-+			/* A-Cable still connected but device disconnected. */
-+			DWC_SPINUNLOCK(core_if->lock);
-+			cil_hcd_disconnect(core_if);
-+			DWC_SPINLOCK(core_if->lock);
-+			if (core_if->adp_enable) {
-+				gpwrdn_data_t gpwrdn = { .d32 = 0 };
-+				cil_hcd_stop(core_if);
-+				/* Enable Power Down Logic */
-+				gpwrdn.b.pmuintsel = 1;
-+				gpwrdn.b.pmuactv = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+				dwc_otg_adp_probe_start(core_if);
-+
-+				/* Power off the core */
-+				if (core_if->power_down == 2) {
-+					gpwrdn.d32 = 0;
-+					gpwrdn.b.pwrdnswtch = 1;
-+					DWC_MODIFY_REG32
-+					    (&core_if->core_global_regs->gpwrdn,
-+					     gpwrdn.d32, 0);
-+				}
-+			}
-+		}
-+	}
-+#endif
-+	/* Change to L3(OFF) state */
-+	core_if->lx_state = DWC_OTG_L3;
-+
-+	gintsts.d32 = 0;
-+	gintsts.b.disconnect = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that SUSPEND state has been detected on
-+ * the USB.
-+ *
-+ * For HNP the USB Suspend interrupt signals the change from
-+ * "a_peripheral" to "a_host".
-+ *
-+ * When power management is enabled the core will be put in low power
-+ * mode.
-+ */
-+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
-+{
-+	dsts_data_t dsts;
-+	gintsts_data_t gintsts;
-+	dcfg_data_t dcfg;
-+
-+	DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
-+
-+	if (dwc_otg_is_device_mode(core_if)) {
-+		/* Check the Device status register to determine if the Suspend
-+		 * state is active. */
-+		dsts.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+		DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
-+		DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
-+			    "HWCFG4.power Optimize=%d\n",
-+			    dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
-+
-+#ifdef PARTIAL_POWER_DOWN
-+/** @todo Add a module parameter for power management. */
-+
-+		if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
-+			pcgcctl_data_t power = {.d32 = 0 };
-+			DWC_DEBUGPL(DBG_CIL, "suspend\n");
-+
-+			power.b.pwrclmp = 1;
-+			DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
-+
-+			power.b.rstpdwnmodule = 1;
-+			DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
-+
-+			power.b.stoppclk = 1;
-+			DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
-+
-+		} else {
-+			DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
-+		}
-+#endif
-+		/* PCD callback for suspend. Release the lock inside of callback function */
-+		cil_pcd_suspend(core_if);
-+		if (core_if->power_down == 2)
-+		{
-+			dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+			DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
-+			DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
-+
-+			if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
-+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+				gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+				gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+
-+				/* Change to L2(suspend) state */
-+				core_if->lx_state = DWC_OTG_L2;
-+
-+				/* Clear interrupt in gintsts */
-+				gintsts.d32 = 0;
-+				gintsts.b.usbsuspend = 1;
-+				DWC_WRITE_REG32(&core_if->core_global_regs->
-+						gintsts, gintsts.d32);
-+				DWC_PRINTF("Start of hibernation completed\n");
-+				dwc_otg_save_global_regs(core_if);
-+				dwc_otg_save_dev_regs(core_if);
-+
-+				gusbcfg.d32 =
-+				    DWC_READ_REG32(&core_if->core_global_regs->
-+						   gusbcfg);
-+				if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+					/* ULPI interface */
-+					/* Suspend the Phy Clock */
-+					pcgcctl.d32 = 0;
-+					pcgcctl.b.stoppclk = 1;
-+					DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+							 pcgcctl.d32);
-+					dwc_udelay(10);
-+					gpwrdn.b.pmuactv = 1;
-+					DWC_MODIFY_REG32(&core_if->
-+							 core_global_regs->
-+							 gpwrdn, 0, gpwrdn.d32);
-+				} else {
-+					/* UTMI+ Interface */
-+					gpwrdn.b.pmuactv = 1;
-+					DWC_MODIFY_REG32(&core_if->
-+							 core_global_regs->
-+							 gpwrdn, 0, gpwrdn.d32);
-+					dwc_udelay(10);
-+					pcgcctl.b.stoppclk = 1;
-+					DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+							 pcgcctl.d32);
-+					dwc_udelay(10);
-+				}
-+
-+				/* Set flag to indicate that we are in hibernation */
-+				core_if->hibernation_suspend = 1;
-+				/* Enable interrupts from wake up logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pmuintsel = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+				dwc_udelay(10);
-+
-+				/* Unmask device mode interrupts in GPWRDN */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.rst_det_msk = 1;
-+				gpwrdn.b.lnstchng_msk = 1;
-+				gpwrdn.b.sts_chngint_msk = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+				dwc_udelay(10);
-+
-+				/* Enable Power Down Clamp */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pwrdnclmp = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+				dwc_udelay(10);
-+
-+				/* Switch off VDD */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pwrdnswtch = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+
-+				/* Save gpwrdn register for further usage if stschng interrupt */
-+				core_if->gr_backup->gpwrdn_local =
-+							DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+				DWC_PRINTF("Hibernation completed\n");
-+
-+				return 1;
-+			}
-+		} else if (core_if->power_down == 3) {
-+			pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+			dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
-+			DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
-+			DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
-+
-+			if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
-+				DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
-+				core_if->xhib = 1;
-+
-+				/* Clear interrupt in gintsts */
-+				gintsts.d32 = 0;
-+				gintsts.b.usbsuspend = 1;
-+				DWC_WRITE_REG32(&core_if->core_global_regs->
-+					gintsts, gintsts.d32);
-+
-+				dwc_otg_save_global_regs(core_if);
-+				dwc_otg_save_dev_regs(core_if);
-+
-+				/* Wait for 10 PHY clocks */
-+				dwc_udelay(10);
-+
-+				/* Program GPIO register while entering to xHib */
-+				DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
-+
-+				pcgcctl.b.enbl_extnd_hiber = 1;
-+				DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+				DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+				pcgcctl.d32 = 0;
-+				pcgcctl.b.extnd_hiber_pwrclmp = 1;
-+				DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+				pcgcctl.d32 = 0;
-+				pcgcctl.b.extnd_hiber_switch = 1;
-+				core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+				core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
-+				DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+				DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
-+
-+				return 1;
-+			}
-+		}
-+	} else {
-+		if (core_if->op_state == A_PERIPHERAL) {
-+			DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
-+			/* Clear the a_peripheral flag, back to a_host. */
-+			DWC_SPINUNLOCK(core_if->lock);
-+			cil_pcd_stop(core_if);
-+			cil_hcd_start(core_if);
-+			DWC_SPINLOCK(core_if->lock);
-+			core_if->op_state = A_HOST;
-+		}
-+	}
-+
-+	/* Change to L2(suspend) state */
-+	core_if->lx_state = DWC_OTG_L2;
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.usbsuspend = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+
-+static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
-+{
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+	gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+
-+	dwc_udelay(10);
-+
-+	/* Program GPIO register while entering to xHib */
-+	DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
-+
-+	pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
-+	pcgcctl.b.extnd_hiber_pwrclmp = 0;
-+	DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+	dwc_udelay(10);
-+
-+	gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
-+	gpwrdn.b.restore = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
-+	dwc_udelay(10);
-+
-+	restore_lpm_i2c_regs(core_if);
-+
-+	pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+	pcgcctl.b.max_xcvrselect = 1;
-+	pcgcctl.b.ess_reg_restored = 0;
-+	pcgcctl.b.extnd_hiber_switch = 0;
-+	pcgcctl.b.extnd_hiber_pwrclmp = 0;
-+	pcgcctl.b.enbl_extnd_hiber = 1;
-+	DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+
-+	gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
-+	gahbcfg.b.glblintrmsk = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
-+
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
-+
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
-+			core_if->gr_backup->gusbcfg_local);
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
-+			core_if->dr_backup->dcfg);
-+
-+	pcgcctl.d32 = 0;
-+	pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+	pcgcctl.b.max_xcvrselect = 1;
-+	pcgcctl.d32 |= 0x608;
-+	DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+	dwc_udelay(10);
-+
-+	pcgcctl.d32 = 0;
-+	pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
-+	pcgcctl.b.max_xcvrselect = 1;
-+	pcgcctl.b.ess_reg_restored = 1;
-+	pcgcctl.b.enbl_extnd_hiber = 1;
-+	pcgcctl.b.rstpdwnmodule = 1;
-+	pcgcctl.b.restoremode = 1;
-+	DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
-+
-+	DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
-+
-+	return 1;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * This function hadles LPM transaction received interrupt.
-+ */
-+static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	gintsts_data_t gintsts;
-+
-+	if (!core_if->core_params->lpm_enable) {
-+		DWC_PRINTF("Unexpected LPM interrupt\n");
-+	}
-+
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
-+
-+	if (dwc_otg_is_host_mode(core_if)) {
-+		cil_hcd_sleep(core_if);
-+	} else {
-+		lpmcfg.b.hird_thres |= (1 << 4);
-+		DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
-+				lpmcfg.d32);
-+	}
-+
-+	/* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
-+	dwc_udelay(10);
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	if (lpmcfg.b.prt_sleep_sts) {
-+		/* Save the current state */
-+		core_if->lx_state = DWC_OTG_L1;
-+	}
-+
-+	/* Clear interrupt  */
-+	gintsts.d32 = 0;
-+	gintsts.b.lpmtranrcvd = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+	return 1;
-+}
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+
-+/**
-+ * This function returns the Core Interrupt register.
-+ */
-+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd)
-+{
-+	gahbcfg_data_t gahbcfg = {.d32 = 0 };
-+	gintsts_data_t gintsts;
-+	gintmsk_data_t gintmsk;
-+	gintmsk_data_t gintmsk_common = {.d32 = 0 };
-+	gintmsk_common.b.wkupintr = 1;
-+	gintmsk_common.b.sessreqintr = 1;
-+	gintmsk_common.b.conidstschng = 1;
-+	gintmsk_common.b.otgintr = 1;
-+	gintmsk_common.b.modemismatch = 1;
-+	gintmsk_common.b.disconnect = 1;
-+	gintmsk_common.b.usbsuspend = 1;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	gintmsk_common.b.lpmtranrcvd = 1;
-+#endif
-+	gintmsk_common.b.restoredone = 1;
-+	if(dwc_otg_is_device_mode(core_if))
-+	{
-+		/** @todo: The port interrupt occurs while in device
-+		 * mode. Added code to CIL to clear the interrupt for now!
-+		 */
-+		gintmsk_common.b.portintr = 1;
-+	}
-+	gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+	gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+	if(fiq_enable) {
-+		local_fiq_disable();
-+		/* Pull in the interrupts that the FIQ has masked */
-+		gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
-+		gintmsk.d32 |= gintmsk_common.d32;
-+		/* for the upstairs function to reenable - have to read it here in case FIQ triggers again */
-+		reenable_gintmsk->d32 = gintmsk.d32;
-+		local_fiq_enable();
-+	}
-+
-+	gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
-+
-+#ifdef DEBUG
-+	/* if any common interrupts set */
-+	if (gintsts.d32 & gintmsk_common.d32) {
-+		DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x  gintmsk=%08x\n",
-+			    gintsts.d32, gintmsk.d32);
-+	}
-+#endif
-+	if (!fiq_enable){
-+		if (gahbcfg.b.glblintrmsk)
-+			return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
-+		else
-+			return 0;
-+	} else {
-+		/* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface.
-+		 * Can't trust the global interrupt mask bit in this case.
-+		 */
-+		return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
-+	}
-+
-+}
-+
-+/* MACRO for clearing interupt bits in GPWRDN register */
-+#define CLEAR_GPWRDN_INTR(__core_if,__intr) \
-+do { \
-+		gpwrdn_data_t gpwrdn = {.d32=0}; \
-+		gpwrdn.b.__intr = 1; \
-+		DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
-+		0, gpwrdn.d32); \
-+} while (0)
-+
-+/**
-+ * Common interrupt handler.
-+ *
-+ * The common interrupts are those that occur in both Host and Device mode.
-+ * This handler handles the following interrupts:
-+ * - Mode Mismatch Interrupt
-+ * - Disconnect Interrupt
-+ * - OTG Interrupt
-+ * - Connector ID Status Change Interrupt
-+ * - Session Request Interrupt.
-+ * - Resume / Remote Wakeup Detected Interrupt.
-+ * - LPM Transaction Received Interrupt
-+ * - ADP Transaction Received Interrupt
-+ *
-+ */
-+int32_t dwc_otg_handle_common_intr(void *dev)
-+{
-+	int retval = 0;
-+	gintsts_data_t gintsts;
-+	gintmsk_data_t gintmsk_reenable = { .d32 = 0 };
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	dwc_otg_device_t *otg_dev = dev;
-+	dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+	gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+	if (dwc_otg_is_device_mode(core_if))
-+		core_if->frame_num = dwc_otg_get_frame_number(core_if);
-+
-+	if (core_if->lock)
-+		DWC_SPINLOCK(core_if->lock);
-+
-+	if (core_if->power_down == 3 && core_if->xhib == 1) {
-+		DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
-+		retval |= dwc_otg_handle_xhib_exit_intr(core_if);
-+		core_if->xhib = 2;
-+		if (core_if->lock)
-+			DWC_SPINUNLOCK(core_if->lock);
-+
-+		return retval;
-+	}
-+
-+	if (core_if->hibernation_suspend <= 0) {
-+		/* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end
-+		 * of this handler - god only knows why it's done like this
-+		 */
-+		gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd);
-+
-+		if (gintsts.b.modemismatch) {
-+			retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
-+		}
-+		if (gintsts.b.otgintr) {
-+			retval |= dwc_otg_handle_otg_intr(core_if);
-+		}
-+		if (gintsts.b.conidstschng) {
-+			retval |=
-+			    dwc_otg_handle_conn_id_status_change_intr(core_if);
-+		}
-+		if (gintsts.b.disconnect) {
-+			retval |= dwc_otg_handle_disconnect_intr(core_if);
-+		}
-+		if (gintsts.b.sessreqintr) {
-+			retval |= dwc_otg_handle_session_req_intr(core_if);
-+		}
-+		if (gintsts.b.wkupintr) {
-+			retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
-+		}
-+		if (gintsts.b.usbsuspend) {
-+			retval |= dwc_otg_handle_usb_suspend_intr(core_if);
-+		}
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+		if (gintsts.b.lpmtranrcvd) {
-+			retval |= dwc_otg_handle_lpm_intr(core_if);
-+		}
-+#endif
-+		if (gintsts.b.restoredone) {
-+			gintsts.d32 = 0;
-+	                if (core_if->power_down == 2)
-+				core_if->hibernation_suspend = -1;
-+			else if (core_if->power_down == 3 && core_if->xhib == 2) {
-+				gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+				dctl_data_t dctl = {.d32 = 0 };
-+
-+				DWC_WRITE_REG32(&core_if->core_global_regs->
-+						gintsts, 0xFFFFFFFF);
-+
-+				DWC_DEBUGPL(DBG_ANY,
-+					    "RESTORE DONE generated\n");
-+
-+				gpwrdn.b.restore = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+				dwc_udelay(10);
-+
-+				pcgcctl.b.rstpdwnmodule = 1;
-+				DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+
-+				DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
-+				DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
-+				DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
-+				dwc_udelay(50);
-+
-+				dctl.b.pwronprgdone = 1;
-+				DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+				dwc_udelay(10);
-+
-+				dwc_otg_restore_global_regs(core_if);
-+				dwc_otg_restore_dev_regs(core_if, 0);
-+
-+				dctl.d32 = 0;
-+				dctl.b.pwronprgdone = 1;
-+				DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+				dwc_udelay(10);
-+
-+				pcgcctl.d32 = 0;
-+				pcgcctl.b.enbl_extnd_hiber = 1;
-+				DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+
-+				/* The core will be in ON STATE */
-+				core_if->lx_state = DWC_OTG_L0;
-+				core_if->xhib = 0;
-+
-+				DWC_SPINUNLOCK(core_if->lock);
-+				if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+					core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+				}
-+				DWC_SPINLOCK(core_if->lock);
-+
-+			}
-+
-+			gintsts.b.restoredone = 1;
-+			DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
-+			DWC_PRINTF(" --Restore done interrupt received-- \n");
-+			retval |= 1;
-+		}
-+		if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
-+			/* The port interrupt occurs while in device mode with HPRT0
-+			 * Port Enable/Disable.
-+			 */
-+			gintsts.d32 = 0;
-+			gintsts.b.portintr = 1;
-+			DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
-+			retval |= 1;
-+			gintmsk_reenable.b.portintr = 1;
-+
-+		}
-+		/* Did we actually handle anything? if so, unmask the interrupt */
-+//		fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval);
-+//		fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32);
-+//		fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32);
-+		if (retval && fiq_enable) {
-+			DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);
-+		}
-+
-+	} else {
-+		DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
-+
-+		if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
-+			CLEAR_GPWRDN_INTR(core_if, disconn_det);
-+			if (gpwrdn.b.linestate == 0) {
-+				dwc_otg_handle_pwrdn_disconnect_intr(core_if);
-+			} else {
-+				DWC_PRINTF("Disconnect detected while linestate is not 0\n");
-+			}
-+
-+			retval |= 1;
-+		}
-+		if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
-+			CLEAR_GPWRDN_INTR(core_if, lnstschng);
-+			/* remote wakeup from hibernation */
-+			if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
-+				dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
-+			} else {
-+				DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
-+			}
-+			retval |= 1;
-+		}
-+		if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
-+			CLEAR_GPWRDN_INTR(core_if, rst_det);
-+			if (gpwrdn.b.linestate == 0) {
-+				DWC_PRINTF("Reset detected\n");
-+				retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
-+			}
-+		}
-+		if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
-+			CLEAR_GPWRDN_INTR(core_if, srp_det);
-+			dwc_otg_handle_pwrdn_srp_intr(core_if);
-+			retval |= 1;
-+		}
-+	}
-+	/* Handle ADP interrupt here */
-+	if (gpwrdn.b.adp_int) {
-+		DWC_PRINTF("ADP interrupt\n");
-+		CLEAR_GPWRDN_INTR(core_if, adp_int);
-+		dwc_otg_adp_handle_intr(core_if);
-+		retval |= 1;
-+	}
-+	if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
-+		DWC_PRINTF("STS CHNG interrupt asserted\n");
-+		CLEAR_GPWRDN_INTR(core_if, sts_chngint);
-+		dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
-+
-+		retval |= 1;
-+	}
-+	if (core_if->lock)
-+		DWC_SPINUNLOCK(core_if->lock);
-+	return retval;
-+}
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
-@@ -0,0 +1,705 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
-+ * $Revision: #13 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#if !defined(__DWC_CORE_IF_H__)
-+#define __DWC_CORE_IF_H__
-+
-+#include "dwc_os.h"
-+
-+/** @file
-+ * This file defines DWC_OTG Core API
-+ */
-+
-+struct dwc_otg_core_if;
-+typedef struct dwc_otg_core_if dwc_otg_core_if_t;
-+
-+/** Maximum number of Periodic FIFOs */
-+#define MAX_PERIO_FIFOS 15
-+/** Maximum number of Periodic FIFOs */
-+#define MAX_TX_FIFOS 15
-+
-+/** Maximum number of Endpoints/HostChannels */
-+#define MAX_EPS_CHANNELS 16
-+
-+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
-+extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
-+
-+extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
-+
-+extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
-+extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
-+
-+extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
-+
-+/** This function should be called on every hardware interrupt. */
-+extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
-+
-+/** @name OTG Core Parameters */
-+/** @{ */
-+
-+/**
-+ * Specifies the OTG capabilities. The driver will automatically
-+ * detect the value for this parameter if none is specified.
-+ * 0 - HNP and SRP capable (default)
-+ * 1 - SRP Only capable
-+ * 2 - No HNP/SRP capable
-+ */
-+extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
-+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
-+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
-+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
-+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
-+
-+extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
-+#define dwc_param_opt_default 1
-+
-+/**
-+ * Specifies whether to use slave or DMA mode for accessing the data
-+ * FIFOs. The driver will automatically detect the value for this
-+ * parameter if none is specified.
-+ * 0 - Slave
-+ * 1 - DMA (default, if available)
-+ */
-+extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dma_enable_default 1
-+
-+/**
-+ * When DMA mode is enabled specifies whether to use
-+ * address DMA or DMA Descritor mode for accessing the data
-+ * FIFOs in device mode. The driver will automatically detect
-+ * the value for this parameter if none is specified.
-+ * 0 - address DMA
-+ * 1 - DMA Descriptor(default, if available)
-+ */
-+extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
-+					     int32_t val);
-+extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_dma_desc_enable_default 1
-+#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
-+
-+/** The DMA Burst size (applicable only for External DMA
-+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ */
-+extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
-+					    int32_t val);
-+extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dma_burst_size_default 32
-+
-+/**
-+ * Specifies the maximum speed of operation in host and device mode.
-+ * The actual speed depends on the speed of the attached device and
-+ * the value of phy_type. The actual speed depends on the speed of the
-+ * attached device.
-+ * 0 - High Speed (default)
-+ * 1 - Full Speed
-+ */
-+extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
-+#define dwc_param_speed_default 0
-+#define DWC_SPEED_PARAM_HIGH 0
-+#define DWC_SPEED_PARAM_FULL 1
-+
-+/** Specifies whether low power mode is supported when attached
-+ *	to a Full Speed or Low Speed device in host mode.
-+ * 0 - Don't support low power mode (default)
-+ * 1 - Support low power mode
-+ */
-+extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
-+							  core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
-+							      * core_if);
-+#define dwc_param_host_support_fs_ls_low_power_default 0
-+
-+/** Specifies the PHY clock rate in low power mode when connected to a
-+ * Low Speed device in host mode. This parameter is applicable only if
-+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
-+ * then defaults to 6 MHZ otherwise 48 MHZ.
-+ *
-+ * 0 - 48 MHz
-+ * 1 - 6 MHz
-+ */
-+extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
-+						       core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
-+							   core_if);
-+#define dwc_param_host_ls_low_power_phy_clk_default 0
-+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
-+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
-+
-+/**
-+ * 0 - Use cC FIFO size parameters
-+ * 1 - Allow dynamic FIFO sizing (default)
-+ */
-+extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
-+						 int32_t val);
-+extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
-+						     core_if);
-+#define dwc_param_enable_dynamic_fifo_default 1
-+
-+/** Total number of 4-byte words in the data FIFO memory. This
-+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
-+ * Tx FIFOs.
-+ * 32 to 32768 (default 8192)
-+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ */
-+extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
-+					    int32_t val);
-+extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_data_fifo_size_default 8192
-+#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1064)
-+ */
-+extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+					      int32_t val);
-+extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_rx_fifo_size_default 1064
-+
-+/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
-+ * when dynamic FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+						     core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+							 core_if);
-+#define dwc_param_dev_nperio_tx_fifo_size_default 1024
-+
-+/** Number of 4-byte words in each of the periodic Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+						    int32_t val, int fifo_num);
-+extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
-+							core_if, int fifo_num);
-+#define dwc_param_dev_perio_tx_fifo_size_default 256
-+
-+/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
-+					       int32_t val);
-+extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_host_rx_fifo_size_default 1024
-+#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
-+ * when Dynamic FIFO sizing is enabled in the core.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+						      core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
-+							  core_if);
-+//#define dwc_param_host_nperio_tx_fifo_size_default 1024
-+#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
-+
-+/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
-+ * FIFO sizing is enabled.
-+ * 16 to 32768 (default 1024)
-+ */
-+extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
-+						     core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
-+							 core_if);
-+//#define dwc_param_host_perio_tx_fifo_size_default 1024
-+#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
-+
-+/** The maximum transfer size supported in bytes.
-+ * 2047 to 65,535  (default 65,535)
-+ */
-+extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
-+					       int32_t val);
-+extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
-+#define dwc_param_max_transfer_size_default 65535
-+
-+/** The maximum number of packets in a transfer.
-+ * 15 to 511  (default 511)
-+ */
-+extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
-+					      int32_t val);
-+extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
-+#define dwc_param_max_packet_count_default 511
-+
-+/** The number of host channel registers to use.
-+ * 1 to 16 (default 12)
-+ * Note: The FPGA configuration supports a maximum of 12 host channels.
-+ */
-+extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
-+					   int32_t val);
-+extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_host_channels_default 12
-+#define dwc_param_host_channels_default 8 // Broadcom BCM2708
-+
-+/** The number of endpoints in addition to EP0 available for device
-+ * mode operations.
-+ * 1 to 15 (default 6 IN and OUT)
-+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT
-+ * endpoints in addition to EP0.
-+ */
-+extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
-+					   int32_t val);
-+extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_endpoints_default 6
-+
-+/**
-+ * Specifies the type of PHY interface to use. By default, the driver
-+ * will automatically detect the phy_type.
-+ *
-+ * 0 - Full Speed PHY
-+ * 1 - UTMI+ (default)
-+ * 2 - ULPI
-+ */
-+extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
-+#define DWC_PHY_TYPE_PARAM_FS 0
-+#define DWC_PHY_TYPE_PARAM_UTMI 1
-+#define DWC_PHY_TYPE_PARAM_ULPI 2
-+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
-+
-+/**
-+ * Specifies the UTMI+ Data Width. This parameter is
-+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
-+ * PHY_TYPE, this parameter indicates the data width between
-+ * the MAC and the ULPI Wrapper.) Also, this parameter is
-+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
-+ * to "8 and 16 bits", meaning that the core has been
-+ * configured to work at either data path width.
-+ *
-+ * 8 or 16 bits (default 16)
-+ */
-+extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
-+					    int32_t val);
-+extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
-+//#define dwc_param_phy_utmi_width_default 16
-+#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
-+
-+/**
-+ * Specifies whether the ULPI operates at double or single
-+ * data rate. This parameter is only applicable if PHY_TYPE is
-+ * ULPI.
-+ *
-+ * 0 - single data rate ULPI interface with 8 bit wide data
-+ * bus (default)
-+ * 1 - double data rate ULPI interface with 4 bit wide data
-+ * bus
-+ */
-+extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
-+					  int32_t val);
-+extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
-+#define dwc_param_phy_ulpi_ddr_default 0
-+
-+/**
-+ * Specifies whether to use the internal or external supply to
-+ * drive the vbus with a ULPI phy.
-+ */
-+extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
-+					       int32_t val);
-+extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
-+#define DWC_PHY_ULPI_INTERNAL_VBUS 0
-+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
-+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
-+
-+/**
-+ * Specifies whether to use the I2Cinterface for full speed PHY. This
-+ * parameter is only applicable if PHY_TYPE is FS.
-+ * 0 - No (default)
-+ * 1 - Yes
-+ */
-+extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_i2c_enable_default 0
-+
-+extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ulpi_fs_ls_default 0
-+
-+extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ts_dline_default 0
-+
-+/**
-+ * Specifies whether dedicated transmit FIFOs are
-+ * enabled for non periodic IN endpoints in device mode
-+ * 0 - No
-+ * 1 - Yes
-+ */
-+extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
-+						 int32_t val);
-+extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
-+						     core_if);
-+#define dwc_param_en_multiple_tx_fifo_default 1
-+
-+/** Number of 4-byte words in each of the Tx FIFOs in device
-+ * mode when dynamic FIFO sizing is enabled.
-+ * 4 to 768 (default 256)
-+ */
-+extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+					      int fifo_num, int32_t val);
-+extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
-+						  int fifo_num);
-+#define dwc_param_dev_tx_fifo_size_default 768
-+
-+/** Thresholding enable flag-
-+ * bit 0 - enable non-ISO Tx thresholding
-+ * bit 1 - enable ISO Tx thresholding
-+ * bit 2 - enable Rx thresholding
-+ */
-+extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
-+#define dwc_param_thr_ctl_default 0
-+
-+/** Thresholding length for Tx
-+ * FIFOs in 32 bit DWORDs
-+ */
-+extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
-+					   int32_t val);
-+extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
-+#define dwc_param_tx_thr_length_default 64
-+
-+/** Thresholding length for Rx
-+ *	FIFOs in 32 bit DWORDs
-+ */
-+extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
-+					   int32_t val);
-+extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
-+#define dwc_param_rx_thr_length_default 64
-+
-+/**
-+ * Specifies whether LPM (Link Power Management) support is enabled
-+ */
-+extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_lpm_enable_default 1
-+
-+/**
-+ * Specifies whether PTI enhancement is enabled
-+ */
-+extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_pti_enable_default 0
-+
-+/**
-+ * Specifies whether MPI enhancement is enabled
-+ */
-+extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_mpi_enable_default 0
-+
-+/**
-+ * Specifies whether ADP capability is enabled
-+ */
-+extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
-+#define dwc_param_adp_enable_default 0
-+
-+/**
-+ * Specifies whether IC_USB capability is enabled
-+ */
-+
-+extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ic_usb_cap_default 0
-+
-+extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
-+					   int32_t val);
-+extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ahb_thr_ratio_default 0
-+
-+extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
-+#define dwc_param_power_down_default 0
-+
-+extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
-+					int32_t val);
-+extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
-+#define dwc_param_reload_ctl_default 0
-+
-+extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
-+										int32_t val);
-+extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
-+#define dwc_param_dev_out_nak_default 0
-+
-+extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
-+										 int32_t val);
-+extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
-+#define dwc_param_cont_on_bna_default 0
-+
-+extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
-+										 int32_t val);
-+extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
-+#define dwc_param_ahb_single_default 0
-+
-+extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
-+extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
-+#define dwc_param_otg_ver_default 0
-+
-+/** @} */
-+
-+/** @name Access to registers and bit-fields */
-+
-+/**
-+ * Dump core registers and SPRAM
-+ */
-+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
-+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
-+
-+/**
-+ * Get host negotiation status.
-+ */
-+extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get srp status
-+ */
-+extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Set hnpreq bit in the GOTGCTL register.
-+ */
-+extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get Content of SNPSID register.
-+ */
-+extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get current mode.
-+ * Returns 0 if in device mode, and 1 if in host mode.
-+ */
-+extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of hnpcapable field in the GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of hnpcapable field in the GUSBCFG register
-+ */
-+extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of srpcapable field in the GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of srpcapable field in the GUSBCFG register
-+ */
-+extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of devspeed field in the DCFG register
-+ */
-+extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of devspeed field in the DCFG register
-+ */
-+extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get the value of busconnected field from the HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Gets the device enumeration Speed.
-+ */
-+extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of prtpwr field from the HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of flag indicating core state - hibernated or not
-+ */
-+extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Set value of prtpwr field from the HPRT0 register
-+ */
-+extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of prtsusp field from the HPRT0 regsiter
-+ */
-+extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of prtpwr field from the HPRT0 register
-+ */
-+extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of ModeChTimEn field from the HCFG regsiter
-+ */
-+extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of ModeChTimEn field from the HCFG regsiter
-+ */
-+extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of Fram Interval field from the HFIR regsiter
-+ */
-+extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of Frame Interval field from the HFIR regsiter
-+ */
-+extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Set value of prtres field from the HPRT0 register
-+ *FIXME Remove?
-+ */
-+extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of rmtwkupsig bit in DCTL register
-+ */
-+extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of prt_sleep_sts field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of rem_wkup_en field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Get value of appl_resp field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of appl_resp field from the GLPMCFG register
-+ */
-+extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of hsic_connect field from the GLPMCFG register
-+ */
-+extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of hsic_connect field from the GLPMCFG register
-+ */
-+extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * Get value of inv_sel_hsic field from the GLPMCFG register.
-+ */
-+extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
-+/**
-+ * Set value of inv_sel_hsic field from the GLPMFG register.
-+ */
-+extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/*
-+ * Some functions for accessing registers
-+ */
-+
-+/**
-+ *  GOTGCTL register
-+ */
-+extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GUSBCFG register
-+ */
-+extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GRXFSIZ register
-+ */
-+extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GNPTXFSIZ register
-+ */
-+extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GGPIO register
-+ */
-+extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GUID register
-+ */
-+extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * HPRT0 register
-+ */
-+extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
-+extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
-+
-+/**
-+ * GHPTXFSIZE
-+ */
-+extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
-+
-+/** @} */
-+
-+#endif				/* __DWC_CORE_IF_H__ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
-@@ -0,0 +1,117 @@
-+/* ==========================================================================
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_DBG_H__
-+#define __DWC_OTG_DBG_H__
-+
-+/** @file
-+ * This file defines debug levels.
-+ * Debugging support vanishes in non-debug builds.
-+ */
-+
-+/**
-+ * The Debug Level bit-mask variable.
-+ */
-+extern uint32_t g_dbg_lvl;
-+/**
-+ * Set the Debug Level variable.
-+ */
-+static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
-+{
-+	uint32_t old = g_dbg_lvl;
-+	g_dbg_lvl = new;
-+	return old;
-+}
-+
-+#define DBG_USER	(0x1)
-+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
-+#define DBG_CIL		(0x2)
-+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
-+ * messages */
-+#define DBG_CILV	(0x20)
-+/**  When debug level has the DBG_PCD bit set, display PCD (Device) debug
-+ *  messages */
-+#define DBG_PCD		(0x4)
-+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
-+ * messages */
-+#define DBG_PCDV	(0x40)
-+/** When debug level has the DBG_HCD bit set, display Host debug messages */
-+#define DBG_HCD		(0x8)
-+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
-+ * messages */
-+#define DBG_HCDV	(0x80)
-+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
-+ *  mode. */
-+#define DBG_HCD_URB	(0x800)
-+/** When debug level has the DBG_HCDI bit set, display host interrupt
-+ *  messages. */
-+#define DBG_HCDI	(0x1000)
-+
-+/** When debug level has any bit set, display debug messages */
-+#define DBG_ANY		(0xFF)
-+
-+/** All debug messages off */
-+#define DBG_OFF		0
-+
-+/** Prefix string for DWC_DEBUG print macros. */
-+#define USB_DWC "DWC_otg: "
-+
-+/**
-+ * Print a debug message when the Global debug level variable contains
-+ * the bit defined in <code>lvl</code>.
-+ *
-+ * @param[in] lvl - Debug level, use one of the DBG_ constants above.
-+ * @param[in] x - like printf
-+ *
-+ *    Example:<p>
-+ * <code>
-+ *      DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
-+ * </code>
-+ * <br>
-+ * results in:<br>
-+ * <code>
-+ * usb-DWC_otg: dwc_otg_cil_init(ca867000)
-+ * </code>
-+ */
-+#ifdef DEBUG
-+
-+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
-+# define DWC_DEBUGP(x...)	DWC_DEBUGPL(DBG_ANY, x )
-+
-+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
-+
-+#else
-+
-+# define DWC_DEBUGPL(lvl, x...) do{}while(0)
-+# define DWC_DEBUGP(x...)
-+
-+# define CHK_DEBUG_LEVEL(level) (0)
-+
-+#endif /*DEBUG*/
-+#endif
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
-@@ -0,0 +1,1760 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
-+ * $Revision: #92 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+/** @file
-+ * The dwc_otg_driver module provides the initialization and cleanup entry
-+ * points for the DWC_otg driver. This module will be dynamically installed
-+ * after Linux is booted using the insmod command. When the module is
-+ * installed, the dwc_otg_driver_init function is called. When the module is
-+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
-+ *
-+ * This module also defines a data structure for the dwc_otg_driver, which is
-+ * used in conjunction with the standard ARM lm_device structure. These
-+ * structures allow the OTG driver to comply with the standard Linux driver
-+ * model in which devices and drivers are registered with a bus driver. This
-+ * has the benefit that Linux can expose attributes of the driver and device
-+ * in its special sysfs file system. Users can then read or write files in
-+ * this file system to perform diagnostics on the driver components or the
-+ * device.
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_os.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_attr.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_fiq_fsm.h"
-+
-+#define DWC_DRIVER_VERSION	"3.00a 10-AUG-2012"
-+#define DWC_DRIVER_DESC		"HS OTG USB Controller driver"
-+
-+bool microframe_schedule=true;
-+
-+static const char dwc_driver_name[] = "dwc_otg";
-+
-+
-+extern int pcd_init(
-+#ifdef LM_INTERFACE
-+			   struct lm_device *_dev
-+#elif  defined(PCI_INTERFACE)
-+			   struct pci_dev *_dev
-+#elif  defined(PLATFORM_INTERFACE)
-+	struct platform_device *dev
-+#endif
-+    );
-+extern int hcd_init(
-+#ifdef LM_INTERFACE
-+			   struct lm_device *_dev
-+#elif  defined(PCI_INTERFACE)
-+			   struct pci_dev *_dev
-+#elif  defined(PLATFORM_INTERFACE)
-+	struct platform_device *dev
-+#endif
-+    );
-+
-+extern int pcd_remove(
-+#ifdef LM_INTERFACE
-+			     struct lm_device *_dev
-+#elif  defined(PCI_INTERFACE)
-+			     struct pci_dev *_dev
-+#elif  defined(PLATFORM_INTERFACE)
-+	struct platform_device *_dev
-+#endif
-+    );
-+
-+extern void hcd_remove(
-+#ifdef LM_INTERFACE
-+			      struct lm_device *_dev
-+#elif  defined(PCI_INTERFACE)
-+			      struct pci_dev *_dev
-+#elif  defined(PLATFORM_INTERFACE)
-+	struct platform_device *_dev
-+#endif
-+    );
-+
-+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
-+
-+/*-------------------------------------------------------------------------*/
-+/* Encapsulate the module parameter settings */
-+
-+struct dwc_otg_driver_module_params {
-+	int32_t opt;
-+	int32_t otg_cap;
-+	int32_t dma_enable;
-+	int32_t dma_desc_enable;
-+	int32_t dma_burst_size;
-+	int32_t speed;
-+	int32_t host_support_fs_ls_low_power;
-+	int32_t host_ls_low_power_phy_clk;
-+	int32_t enable_dynamic_fifo;
-+	int32_t data_fifo_size;
-+	int32_t dev_rx_fifo_size;
-+	int32_t dev_nperio_tx_fifo_size;
-+	uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+	int32_t host_rx_fifo_size;
-+	int32_t host_nperio_tx_fifo_size;
-+	int32_t host_perio_tx_fifo_size;
-+	int32_t max_transfer_size;
-+	int32_t max_packet_count;
-+	int32_t host_channels;
-+	int32_t dev_endpoints;
-+	int32_t phy_type;
-+	int32_t phy_utmi_width;
-+	int32_t phy_ulpi_ddr;
-+	int32_t phy_ulpi_ext_vbus;
-+	int32_t i2c_enable;
-+	int32_t ulpi_fs_ls;
-+	int32_t ts_dline;
-+	int32_t en_multiple_tx_fifo;
-+	uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
-+	uint32_t thr_ctl;
-+	uint32_t tx_thr_length;
-+	uint32_t rx_thr_length;
-+	int32_t pti_enable;
-+	int32_t mpi_enable;
-+	int32_t lpm_enable;
-+	int32_t ic_usb_cap;
-+	int32_t ahb_thr_ratio;
-+	int32_t power_down;
-+	int32_t reload_ctl;
-+	int32_t dev_out_nak;
-+	int32_t cont_on_bna;
-+	int32_t ahb_single;
-+	int32_t otg_ver;
-+	int32_t adp_enable;
-+};
-+
-+static struct dwc_otg_driver_module_params dwc_otg_module_params = {
-+	.opt = -1,
-+	.otg_cap = -1,
-+	.dma_enable = -1,
-+	.dma_desc_enable = -1,
-+	.dma_burst_size = -1,
-+	.speed = -1,
-+	.host_support_fs_ls_low_power = -1,
-+	.host_ls_low_power_phy_clk = -1,
-+	.enable_dynamic_fifo = -1,
-+	.data_fifo_size = -1,
-+	.dev_rx_fifo_size = -1,
-+	.dev_nperio_tx_fifo_size = -1,
-+	.dev_perio_tx_fifo_size = {
-+				   /* dev_perio_tx_fifo_size_1 */
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1,
-+				   -1
-+				   /* 15 */
-+				   },
-+	.host_rx_fifo_size = -1,
-+	.host_nperio_tx_fifo_size = -1,
-+	.host_perio_tx_fifo_size = -1,
-+	.max_transfer_size = -1,
-+	.max_packet_count = -1,
-+	.host_channels = -1,
-+	.dev_endpoints = -1,
-+	.phy_type = -1,
-+	.phy_utmi_width = -1,
-+	.phy_ulpi_ddr = -1,
-+	.phy_ulpi_ext_vbus = -1,
-+	.i2c_enable = -1,
-+	.ulpi_fs_ls = -1,
-+	.ts_dline = -1,
-+	.en_multiple_tx_fifo = -1,
-+	.dev_tx_fifo_size = {
-+			     /* dev_tx_fifo_size */
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1,
-+			     -1
-+			     /* 15 */
-+			     },
-+	.thr_ctl = -1,
-+	.tx_thr_length = -1,
-+	.rx_thr_length = -1,
-+	.pti_enable = -1,
-+	.mpi_enable = -1,
-+	.lpm_enable = 0,
-+	.ic_usb_cap = -1,
-+	.ahb_thr_ratio = -1,
-+	.power_down = -1,
-+	.reload_ctl = -1,
-+	.dev_out_nak = -1,
-+	.cont_on_bna = -1,
-+	.ahb_single = -1,
-+	.otg_ver = -1,
-+	.adp_enable = -1,
-+};
-+
-+//Global variable to switch the fiq fix on or off
-+bool fiq_enable = 1;
-+// Global variable to enable the split transaction fix
-+bool fiq_fsm_enable = true;
-+//Bulk split-transaction NAK holdoff in microframes
-+uint16_t nak_holdoff = 8;
-+
-+unsigned short fiq_fsm_mask = 0x0F;
-+
-+unsigned short int_ep_interval_min = 0;
-+/**
-+ * This function shows the Driver Version.
-+ */
-+static ssize_t version_show(struct device_driver *dev, char *buf)
-+{
-+	return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
-+			DWC_DRIVER_VERSION);
-+}
-+
-+static DRIVER_ATTR_RO(version);
-+
-+/**
-+ * Global Debug Level Mask.
-+ */
-+uint32_t g_dbg_lvl = 0;		/* OFF */
-+
-+/**
-+ * This function shows the driver Debug Level.
-+ */
-+static ssize_t debuglevel_show(struct device_driver *drv, char *buf)
-+{
-+	return sprintf(buf, "0x%0x\n", g_dbg_lvl);
-+}
-+
-+/**
-+ * This function stores the driver Debug Level.
-+ */
-+static ssize_t debuglevel_store(struct device_driver *drv, const char *buf,
-+			       size_t count)
-+{
-+	g_dbg_lvl = simple_strtoul(buf, NULL, 16);
-+	return count;
-+}
-+
-+static DRIVER_ATTR_RW(debuglevel);
-+
-+/**
-+ * This function is called during module intialization
-+ * to pass module parameters to the DWC_OTG CORE.
-+ */
-+static int set_parameters(dwc_otg_core_if_t * core_if)
-+{
-+	int retval = 0;
-+	int i;
-+
-+	if (dwc_otg_module_params.otg_cap != -1) {
-+		retval +=
-+		    dwc_otg_set_param_otg_cap(core_if,
-+					      dwc_otg_module_params.otg_cap);
-+	}
-+	if (dwc_otg_module_params.dma_enable != -1) {
-+		retval +=
-+		    dwc_otg_set_param_dma_enable(core_if,
-+						 dwc_otg_module_params.
-+						 dma_enable);
-+	}
-+	if (dwc_otg_module_params.dma_desc_enable != -1) {
-+		retval +=
-+		    dwc_otg_set_param_dma_desc_enable(core_if,
-+						      dwc_otg_module_params.
-+						      dma_desc_enable);
-+	}
-+	if (dwc_otg_module_params.opt != -1) {
-+		retval +=
-+		    dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
-+	}
-+	if (dwc_otg_module_params.dma_burst_size != -1) {
-+		retval +=
-+		    dwc_otg_set_param_dma_burst_size(core_if,
-+						     dwc_otg_module_params.
-+						     dma_burst_size);
-+	}
-+	if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
-+		retval +=
-+		    dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
-+								   dwc_otg_module_params.
-+								   host_support_fs_ls_low_power);
-+	}
-+	if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
-+		retval +=
-+		    dwc_otg_set_param_enable_dynamic_fifo(core_if,
-+							  dwc_otg_module_params.
-+							  enable_dynamic_fifo);
-+	}
-+	if (dwc_otg_module_params.data_fifo_size != -1) {
-+		retval +=
-+		    dwc_otg_set_param_data_fifo_size(core_if,
-+						     dwc_otg_module_params.
-+						     data_fifo_size);
-+	}
-+	if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
-+		retval +=
-+		    dwc_otg_set_param_dev_rx_fifo_size(core_if,
-+						       dwc_otg_module_params.
-+						       dev_rx_fifo_size);
-+	}
-+	if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
-+		retval +=
-+		    dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
-+							      dwc_otg_module_params.
-+							      dev_nperio_tx_fifo_size);
-+	}
-+	if (dwc_otg_module_params.host_rx_fifo_size != -1) {
-+		retval +=
-+		    dwc_otg_set_param_host_rx_fifo_size(core_if,
-+							dwc_otg_module_params.host_rx_fifo_size);
-+	}
-+	if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
-+		retval +=
-+		    dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
-+							       dwc_otg_module_params.
-+							       host_nperio_tx_fifo_size);
-+	}
-+	if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
-+		retval +=
-+		    dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
-+							      dwc_otg_module_params.
-+							      host_perio_tx_fifo_size);
-+	}
-+	if (dwc_otg_module_params.max_transfer_size != -1) {
-+		retval +=
-+		    dwc_otg_set_param_max_transfer_size(core_if,
-+							dwc_otg_module_params.
-+							max_transfer_size);
-+	}
-+	if (dwc_otg_module_params.max_packet_count != -1) {
-+		retval +=
-+		    dwc_otg_set_param_max_packet_count(core_if,
-+						       dwc_otg_module_params.
-+						       max_packet_count);
-+	}
-+	if (dwc_otg_module_params.host_channels != -1) {
-+		retval +=
-+		    dwc_otg_set_param_host_channels(core_if,
-+						    dwc_otg_module_params.
-+						    host_channels);
-+	}
-+	if (dwc_otg_module_params.dev_endpoints != -1) {
-+		retval +=
-+		    dwc_otg_set_param_dev_endpoints(core_if,
-+						    dwc_otg_module_params.
-+						    dev_endpoints);
-+	}
-+	if (dwc_otg_module_params.phy_type != -1) {
-+		retval +=
-+		    dwc_otg_set_param_phy_type(core_if,
-+					       dwc_otg_module_params.phy_type);
-+	}
-+	if (dwc_otg_module_params.speed != -1) {
-+		retval +=
-+		    dwc_otg_set_param_speed(core_if,
-+					    dwc_otg_module_params.speed);
-+	}
-+	if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
-+		retval +=
-+		    dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
-+								dwc_otg_module_params.
-+								host_ls_low_power_phy_clk);
-+	}
-+	if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
-+		retval +=
-+		    dwc_otg_set_param_phy_ulpi_ddr(core_if,
-+						   dwc_otg_module_params.
-+						   phy_ulpi_ddr);
-+	}
-+	if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
-+		retval +=
-+		    dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
-+							dwc_otg_module_params.
-+							phy_ulpi_ext_vbus);
-+	}
-+	if (dwc_otg_module_params.phy_utmi_width != -1) {
-+		retval +=
-+		    dwc_otg_set_param_phy_utmi_width(core_if,
-+						     dwc_otg_module_params.
-+						     phy_utmi_width);
-+	}
-+	if (dwc_otg_module_params.ulpi_fs_ls != -1) {
-+		retval +=
-+		    dwc_otg_set_param_ulpi_fs_ls(core_if,
-+						 dwc_otg_module_params.ulpi_fs_ls);
-+	}
-+	if (dwc_otg_module_params.ts_dline != -1) {
-+		retval +=
-+		    dwc_otg_set_param_ts_dline(core_if,
-+					       dwc_otg_module_params.ts_dline);
-+	}
-+	if (dwc_otg_module_params.i2c_enable != -1) {
-+		retval +=
-+		    dwc_otg_set_param_i2c_enable(core_if,
-+						 dwc_otg_module_params.
-+						 i2c_enable);
-+	}
-+	if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
-+		retval +=
-+		    dwc_otg_set_param_en_multiple_tx_fifo(core_if,
-+							  dwc_otg_module_params.
-+							  en_multiple_tx_fifo);
-+	}
-+	for (i = 0; i < 15; i++) {
-+		if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
-+			retval +=
-+			    dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
-+								     dwc_otg_module_params.
-+								     dev_perio_tx_fifo_size
-+								     [i], i);
-+		}
-+	}
-+
-+	for (i = 0; i < 15; i++) {
-+		if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
-+			retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
-+								     dwc_otg_module_params.
-+								     dev_tx_fifo_size
-+								     [i], i);
-+		}
-+	}
-+	if (dwc_otg_module_params.thr_ctl != -1) {
-+		retval +=
-+		    dwc_otg_set_param_thr_ctl(core_if,
-+					      dwc_otg_module_params.thr_ctl);
-+	}
-+	if (dwc_otg_module_params.mpi_enable != -1) {
-+		retval +=
-+		    dwc_otg_set_param_mpi_enable(core_if,
-+						 dwc_otg_module_params.
-+						 mpi_enable);
-+	}
-+	if (dwc_otg_module_params.pti_enable != -1) {
-+		retval +=
-+		    dwc_otg_set_param_pti_enable(core_if,
-+						 dwc_otg_module_params.
-+						 pti_enable);
-+	}
-+	if (dwc_otg_module_params.lpm_enable != -1) {
-+		retval +=
-+		    dwc_otg_set_param_lpm_enable(core_if,
-+						 dwc_otg_module_params.
-+						 lpm_enable);
-+	}
-+	if (dwc_otg_module_params.ic_usb_cap != -1) {
-+		retval +=
-+		    dwc_otg_set_param_ic_usb_cap(core_if,
-+						 dwc_otg_module_params.
-+						 ic_usb_cap);
-+	}
-+	if (dwc_otg_module_params.tx_thr_length != -1) {
-+		retval +=
-+		    dwc_otg_set_param_tx_thr_length(core_if,
-+						    dwc_otg_module_params.tx_thr_length);
-+	}
-+	if (dwc_otg_module_params.rx_thr_length != -1) {
-+		retval +=
-+		    dwc_otg_set_param_rx_thr_length(core_if,
-+						    dwc_otg_module_params.
-+						    rx_thr_length);
-+	}
-+	if (dwc_otg_module_params.ahb_thr_ratio != -1) {
-+		retval +=
-+		    dwc_otg_set_param_ahb_thr_ratio(core_if,
-+						    dwc_otg_module_params.ahb_thr_ratio);
-+	}
-+	if (dwc_otg_module_params.power_down != -1) {
-+		retval +=
-+		    dwc_otg_set_param_power_down(core_if,
-+						 dwc_otg_module_params.power_down);
-+	}
-+	if (dwc_otg_module_params.reload_ctl != -1) {
-+		retval +=
-+		    dwc_otg_set_param_reload_ctl(core_if,
-+						 dwc_otg_module_params.reload_ctl);
-+	}
-+
-+	if (dwc_otg_module_params.dev_out_nak != -1) {
-+		retval +=
-+			dwc_otg_set_param_dev_out_nak(core_if,
-+			dwc_otg_module_params.dev_out_nak);
-+	}
-+
-+	if (dwc_otg_module_params.cont_on_bna != -1) {
-+		retval +=
-+			dwc_otg_set_param_cont_on_bna(core_if,
-+			dwc_otg_module_params.cont_on_bna);
-+	}
-+
-+	if (dwc_otg_module_params.ahb_single != -1) {
-+		retval +=
-+			dwc_otg_set_param_ahb_single(core_if,
-+			dwc_otg_module_params.ahb_single);
-+	}
-+
-+	if (dwc_otg_module_params.otg_ver != -1) {
-+		retval +=
-+		    dwc_otg_set_param_otg_ver(core_if,
-+					      dwc_otg_module_params.otg_ver);
-+	}
-+	if (dwc_otg_module_params.adp_enable != -1) {
-+		retval +=
-+		    dwc_otg_set_param_adp_enable(core_if,
-+						 dwc_otg_module_params.
-+						 adp_enable);
-+	}
-+	return retval;
-+}
-+
-+/**
-+ * This function is the top level interrupt handler for the Common
-+ * (Device and host modes) interrupts.
-+ */
-+static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
-+{
-+	int32_t retval = IRQ_NONE;
-+
-+	retval = dwc_otg_handle_common_intr(dev);
-+	if (retval != 0) {
-+		S3C2410X_CLEAR_EINTPEND();
-+	}
-+	return IRQ_RETVAL(retval);
-+}
-+
-+/**
-+ * This function is called when a lm_device is unregistered with the
-+ * dwc_otg_driver. This happens, for example, when the rmmod command is
-+ * executed. The device may or may not be electrically present. If it is
-+ * present, the driver stops device processing. Any resources used on behalf
-+ * of this device are freed.
-+ *
-+ * @param _dev
-+ */
-+#ifdef LM_INTERFACE
-+#define REM_RETVAL(n)
-+static void dwc_otg_driver_remove(	 struct lm_device *_dev )
-+{       dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
-+#elif  defined(PCI_INTERFACE)
-+#define REM_RETVAL(n)
-+static void dwc_otg_driver_remove(	 struct pci_dev *_dev )
-+{	dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
-+#elif  defined(PLATFORM_INTERFACE)
-+#define REM_RETVAL(n) n
-+static int dwc_otg_driver_remove(        struct platform_device *_dev )
-+{       dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
-+#endif
-+
-+	DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
-+
-+	if (!otg_dev) {
-+		/* Memory allocation for the dwc_otg_device failed. */
-+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
-+                return REM_RETVAL(-ENOMEM);
-+	}
-+#ifndef DWC_DEVICE_ONLY
-+	if (otg_dev->hcd) {
-+		hcd_remove(_dev);
-+	} else {
-+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
-+                return REM_RETVAL(-EINVAL);
-+	}
-+#endif
-+
-+#ifndef DWC_HOST_ONLY
-+	if (otg_dev->pcd) {
-+		pcd_remove(_dev);
-+	} else {
-+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
-+                return REM_RETVAL(-EINVAL);
-+	}
-+#endif
-+	/*
-+	 * Free the IRQ
-+	 */
-+	if (otg_dev->common_irq_installed) {
-+#ifdef PLATFORM_INTERFACE
-+		free_irq(platform_get_irq(_dev, 0), otg_dev);
-+#else
-+		free_irq(_dev->irq, otg_dev);
-+#endif
-+        } else {
-+		DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
-+		return REM_RETVAL(-ENXIO);
-+	}
-+
-+	if (otg_dev->core_if) {
-+		dwc_otg_cil_remove(otg_dev->core_if);
-+	} else {
-+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
-+		return REM_RETVAL(-ENXIO);
-+	}
-+
-+	/*
-+	 * Remove the device attributes
-+	 */
-+	dwc_otg_attr_remove(_dev);
-+
-+	/*
-+	 * Return the memory.
-+	 */
-+	if (otg_dev->os_dep.base) {
-+		iounmap(otg_dev->os_dep.base);
-+	}
-+	DWC_FREE(otg_dev);
-+
-+	/*
-+	 * Clear the drvdata pointer.
-+	 */
-+#ifdef LM_INTERFACE
-+	lm_set_drvdata(_dev, 0);
-+#elif defined(PCI_INTERFACE)
-+        release_mem_region(otg_dev->os_dep.rsrc_start,
-+                           otg_dev->os_dep.rsrc_len);
-+	pci_set_drvdata(_dev, 0);
-+#elif  defined(PLATFORM_INTERFACE)
-+        platform_set_drvdata(_dev, 0);
-+#endif
-+        return REM_RETVAL(0);
-+}
-+
-+/**
-+ * This function is called when an lm_device is bound to a
-+ * dwc_otg_driver. It creates the driver components required to
-+ * control the device (CIL, HCD, and PCD) and it initializes the
-+ * device. The driver components are stored in a dwc_otg_device
-+ * structure. A reference to the dwc_otg_device is saved in the
-+ * lm_device. This allows the driver to access the dwc_otg_device
-+ * structure on subsequent calls to driver methods for this device.
-+ *
-+ * @param _dev Bus device
-+ */
-+static int dwc_otg_driver_probe(
-+#ifdef LM_INTERFACE
-+				       struct lm_device *_dev
-+#elif defined(PCI_INTERFACE)
-+				       struct pci_dev *_dev,
-+				       const struct pci_device_id *id
-+#elif  defined(PLATFORM_INTERFACE)
-+                                       struct platform_device *_dev
-+#endif
-+    )
-+{
-+	int retval = 0;
-+	dwc_otg_device_t *dwc_otg_device;
-+        int devirq;
-+
-+	dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
-+#ifdef LM_INTERFACE
-+	dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
-+#elif defined(PCI_INTERFACE)
-+	if (!id) {
-+		DWC_ERROR("Invalid pci_device_id %p", id);
-+		return -EINVAL;
-+	}
-+
-+	if (!_dev || (pci_enable_device(_dev) < 0)) {
-+		DWC_ERROR("Invalid pci_device %p", _dev);
-+		return -ENODEV;
-+	}
-+	dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
-+	/* other stuff needed as well? */
-+
-+#elif  defined(PLATFORM_INTERFACE)
-+	dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
-+                (unsigned)_dev->resource->start,
-+                (unsigned)(_dev->resource->end - _dev->resource->start));
-+#endif
-+
-+	dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
-+
-+	if (!dwc_otg_device) {
-+		dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
-+		return -ENOMEM;
-+	}
-+
-+	memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
-+	dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
-+	dwc_otg_device->os_dep.platformdev = _dev;
-+
-+	/*
-+	 * Map the DWC_otg Core memory into virtual address space.
-+	 */
-+#ifdef LM_INTERFACE
-+	dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
-+
-+	if (!dwc_otg_device->os_dep.base) {
-+		dev_err(&_dev->dev, "ioremap() failed\n");
-+		DWC_FREE(dwc_otg_device);
-+		return -ENOMEM;
-+	}
-+	dev_dbg(&_dev->dev, "base=0x%08x\n",
-+		(unsigned)dwc_otg_device->os_dep.base);
-+#elif defined(PCI_INTERFACE)
-+	_dev->current_state = PCI_D0;
-+	_dev->dev.power.power_state = PMSG_ON;
-+
-+	if (!_dev->irq) {
-+		DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
-+			  pci_name(_dev));
-+		iounmap(dwc_otg_device->os_dep.base);
-+		DWC_FREE(dwc_otg_device);
-+		return -ENODEV;
-+	}
-+
-+	dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
-+	dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
-+	DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
-+		    (unsigned)dwc_otg_device->os_dep.rsrc_start,
-+		    (unsigned)dwc_otg_device->os_dep.rsrc_len);
-+	if (!request_mem_region
-+	    (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
-+	     "dwc_otg")) {
-+		dev_dbg(&_dev->dev, "error requesting memory\n");
-+		iounmap(dwc_otg_device->os_dep.base);
-+		DWC_FREE(dwc_otg_device);
-+		return -EFAULT;
-+	}
-+
-+	dwc_otg_device->os_dep.base =
-+	    ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
-+			    dwc_otg_device->os_dep.rsrc_len);
-+	if (dwc_otg_device->os_dep.base == NULL) {
-+		dev_dbg(&_dev->dev, "error mapping memory\n");
-+		release_mem_region(dwc_otg_device->os_dep.rsrc_start,
-+				   dwc_otg_device->os_dep.rsrc_len);
-+		iounmap(dwc_otg_device->os_dep.base);
-+		DWC_FREE(dwc_otg_device);
-+		return -EFAULT;
-+	}
-+	dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
-+		dwc_otg_device->os_dep.base);
-+	dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
-+	dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
-+		dwc_otg_device->os_dep.base);
-+	dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
-+		(unsigned)dwc_otg_device->os_dep.rsrc_start,
-+		dwc_otg_device->os_dep.base);
-+
-+	pci_set_master(_dev);
-+	pci_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+        DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
-+                    _dev->resource->start,
-+                    _dev->resource->end - _dev->resource->start + 1);
-+#if 1
-+        if (!request_mem_region(_dev->resource[0].start,
-+                                _dev->resource[0].end - _dev->resource[0].start + 1,
-+                                "dwc_otg")) {
-+          dev_dbg(&_dev->dev, "error reserving mapped memory\n");
-+          retval = -EFAULT;
-+          goto fail;
-+        }
-+
-+	dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
-+                                                      _dev->resource[0].end -
-+                                                      _dev->resource[0].start+1);
-+	if (fiq_enable)
-+	{
-+		if (!request_mem_region(_dev->resource[1].start,
-+	                                _dev->resource[1].end - _dev->resource[1].start + 1,
-+	                                "dwc_otg")) {
-+	          dev_dbg(&_dev->dev, "error reserving mapped memory\n");
-+	          retval = -EFAULT;
-+	          goto fail;
-+	}
-+
-+		dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
-+							    _dev->resource[1].end -
-+							    _dev->resource[1].start + 1);
-+	}
-+
-+#else
-+        {
-+                struct map_desc desc = {
-+                    .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
-+                    .pfn     = __phys_to_pfn((unsigned)_dev->resource->start),
-+                    .length  = SZ_128K,
-+                    .type    = MT_DEVICE
-+                };
-+                iotable_init(&desc, 1);
-+                dwc_otg_device->os_dep.base = (void *)desc.virtual;
-+        }
-+#endif
-+	if (!dwc_otg_device->os_dep.base) {
-+		dev_err(&_dev->dev, "ioremap() failed\n");
-+		retval = -ENOMEM;
-+		goto fail;
-+	}
-+	dev_dbg(&_dev->dev, "base=0x%08x\n",
-+                (unsigned)dwc_otg_device->os_dep.base);
-+#endif
-+
-+	/*
-+	 * Initialize driver data to point to the global DWC_otg
-+	 * Device structure.
-+	 */
-+#ifdef LM_INTERFACE
-+	lm_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+	platform_set_drvdata(_dev, dwc_otg_device);
-+#endif
-+	dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
-+
-+	dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
-+        DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
-+                    dwc_otg_device, dwc_otg_device->core_if);//GRAYG
-+
-+	if (!dwc_otg_device->core_if) {
-+		dev_err(&_dev->dev, "CIL initialization failed!\n");
-+		retval = -ENOMEM;
-+		goto fail;
-+	}
-+
-+	dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
-+	/*
-+	 * Attempt to ensure this device is really a DWC_otg Controller.
-+	 * Read and verify the SNPSID register contents. The value should be
-+	 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
-+	 * as in "OTG version 2.XX" or "OTG version 3.XX".
-+	 */
-+
-+	if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=	0x4F542000) &&
-+		((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
-+		dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
-+			dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
-+		retval = -EINVAL;
-+		goto fail;
-+	}
-+
-+	/*
-+	 * Validate parameter values.
-+	 */
-+	dev_dbg(&_dev->dev, "Calling set_parameters\n");
-+	if (set_parameters(dwc_otg_device->core_if)) {
-+		retval = -EINVAL;
-+		goto fail;
-+	}
-+
-+	/*
-+	 * Create Device Attributes in sysfs
-+	 */
-+	dev_dbg(&_dev->dev, "Calling attr_create\n");
-+	dwc_otg_attr_create(_dev);
-+
-+	/*
-+	 * Disable the global interrupt until all the interrupt
-+	 * handlers are installed.
-+	 */
-+	dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
-+	dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
-+
-+	/*
-+	 * Install the interrupt handler for the common interrupts before
-+	 * enabling common interrupts in core_init below.
-+	 */
-+
-+#if defined(PLATFORM_INTERFACE)
-+	devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);
-+#else
-+	devirq = _dev->irq;
-+#endif
-+	DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
-+		    devirq);
-+	dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
-+	retval = request_irq(devirq, dwc_otg_common_irq,
-+                             IRQF_SHARED,
-+                             "dwc_otg", dwc_otg_device);
-+	if (retval) {
-+		DWC_ERROR("request of irq%d failed\n", devirq);
-+		retval = -EBUSY;
-+		goto fail;
-+	} else {
-+		dwc_otg_device->common_irq_installed = 1;
-+	}
-+
-+#ifndef IRQF_TRIGGER_LOW
-+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+	dev_dbg(&_dev->dev, "Calling set_irq_type\n");
-+	set_irq_type(devirq,
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
-+                     IRQT_LOW
-+#else
-+                     IRQ_TYPE_LEVEL_LOW
-+#endif
-+                    );
-+#endif
-+#endif /*IRQF_TRIGGER_LOW*/
-+
-+	/*
-+	 * Initialize the DWC_otg core.
-+	 */
-+	dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
-+	dwc_otg_core_init(dwc_otg_device->core_if);
-+
-+#ifndef DWC_HOST_ONLY
-+	/*
-+	 * Initialize the PCD
-+	 */
-+	dev_dbg(&_dev->dev, "Calling pcd_init\n");
-+	retval = pcd_init(_dev);
-+	if (retval != 0) {
-+		DWC_ERROR("pcd_init failed\n");
-+		dwc_otg_device->pcd = NULL;
-+		goto fail;
-+	}
-+#endif
-+#ifndef DWC_DEVICE_ONLY
-+	/*
-+	 * Initialize the HCD
-+	 */
-+	dev_dbg(&_dev->dev, "Calling hcd_init\n");
-+	retval = hcd_init(_dev);
-+	if (retval != 0) {
-+		DWC_ERROR("hcd_init failed\n");
-+		dwc_otg_device->hcd = NULL;
-+		goto fail;
-+	}
-+#endif
-+        /* Recover from drvdata having been overwritten by hcd_init() */
-+#ifdef LM_INTERFACE
-+	lm_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PLATFORM_INTERFACE)
-+	platform_set_drvdata(_dev, dwc_otg_device);
-+#elif defined(PCI_INTERFACE)
-+	pci_set_drvdata(_dev, dwc_otg_device);
-+	dwc_otg_device->os_dep.pcidev = _dev;
-+#endif
-+
-+	/*
-+	 * Enable the global interrupt after all the interrupt
-+	 * handlers are installed if there is no ADP support else
-+	 * perform initial actions required for Internal ADP logic.
-+	 */
-+	if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
-+	        dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
-+		dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
-+	        dev_dbg(&_dev->dev, "Done\n");
-+	} else
-+		dwc_otg_adp_start(dwc_otg_device->core_if,
-+							dwc_otg_is_host_mode(dwc_otg_device->core_if));
-+
-+	return 0;
-+
-+fail:
-+	dwc_otg_driver_remove(_dev);
-+	return retval;
-+}
-+
-+/**
-+ * This structure defines the methods to be called by a bus driver
-+ * during the lifecycle of a device on that bus. Both drivers and
-+ * devices are registered with a bus driver. The bus driver matches
-+ * devices to drivers based on information in the device and driver
-+ * structures.
-+ *
-+ * The probe function is called when the bus driver matches a device
-+ * to this driver. The remove function is called when a device is
-+ * unregistered with the bus driver.
-+ */
-+#ifdef LM_INTERFACE
-+static struct lm_driver dwc_otg_driver = {
-+	.drv = {.name = (char *)dwc_driver_name,},
-+	.probe = dwc_otg_driver_probe,
-+	.remove = dwc_otg_driver_remove,
-+        // 'suspend' and 'resume' absent
-+};
-+#elif defined(PCI_INTERFACE)
-+static const struct pci_device_id pci_ids[] = { {
-+						 PCI_DEVICE(0x16c3, 0xabcd),
-+						 .driver_data =
-+						 (unsigned long)0xdeadbeef,
-+						 }, { /* end: all zeroes */ }
-+};
-+
-+MODULE_DEVICE_TABLE(pci, pci_ids);
-+
-+/* pci driver glue; this is a "new style" PCI driver module */
-+static struct pci_driver dwc_otg_driver = {
-+	.name = "dwc_otg",
-+	.id_table = pci_ids,
-+
-+	.probe = dwc_otg_driver_probe,
-+	.remove = dwc_otg_driver_remove,
-+
-+	.driver = {
-+		   .name = (char *)dwc_driver_name,
-+		   },
-+};
-+#elif defined(PLATFORM_INTERFACE)
-+static struct platform_device_id platform_ids[] = {
-+        {
-+              .name = "bcm2708_usb",
-+              .driver_data = (kernel_ulong_t) 0xdeadbeef,
-+        },
-+        { /* end: all zeroes */ }
-+};
-+MODULE_DEVICE_TABLE(platform, platform_ids);
-+
-+static const struct of_device_id dwc_otg_of_match_table[] = {
-+	{ .compatible = "brcm,bcm2708-usb", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table);
-+
-+static struct platform_driver dwc_otg_driver = {
-+	.driver = {
-+		.name = (char *)dwc_driver_name,
-+		.of_match_table = dwc_otg_of_match_table,
-+		},
-+        .id_table = platform_ids,
-+
-+	.probe = dwc_otg_driver_probe,
-+	.remove = dwc_otg_driver_remove,
-+        // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
-+};
-+#endif
-+
-+/**
-+ * This function is called when the dwc_otg_driver is installed with the
-+ * insmod command. It registers the dwc_otg_driver structure with the
-+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function
-+ * to be called. In addition, the bus driver will automatically expose
-+ * attributes defined for the device and driver in the special sysfs file
-+ * system.
-+ *
-+ * @return
-+ */
-+static int __init dwc_otg_driver_init(void)
-+{
-+	int retval = 0;
-+	int error;
-+        struct device_driver *drv;
-+
-+	if(fiq_fsm_enable && !fiq_enable) {
-+		printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n");
-+		fiq_enable = 1;
-+	}
-+
-+	printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
-+	       DWC_DRIVER_VERSION,
-+#ifdef LM_INTERFACE
-+               "logicmodule");
-+	retval = lm_driver_register(&dwc_otg_driver);
-+        drv = &dwc_otg_driver.drv;
-+#elif defined(PCI_INTERFACE)
-+               "pci");
-+	retval = pci_register_driver(&dwc_otg_driver);
-+        drv = &dwc_otg_driver.driver;
-+#elif defined(PLATFORM_INTERFACE)
-+               "platform");
-+	retval = platform_driver_register(&dwc_otg_driver);
-+        drv = &dwc_otg_driver.driver;
-+#endif
-+	if (retval < 0) {
-+		printk(KERN_ERR "%s retval=%d\n", __func__, retval);
-+		return retval;
-+	}
-+	printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled");
-+	printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled");
-+	printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled");
-+
-+	error = driver_create_file(drv, &driver_attr_version);
-+#ifdef DEBUG
-+	error = driver_create_file(drv, &driver_attr_debuglevel);
-+#endif
-+	return retval;
-+}
-+
-+module_init(dwc_otg_driver_init);
-+
-+/**
-+ * This function is called when the driver is removed from the kernel
-+ * with the rmmod command. The driver unregisters itself with its bus
-+ * driver.
-+ *
-+ */
-+static void __exit dwc_otg_driver_cleanup(void)
-+{
-+	printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
-+
-+#ifdef LM_INTERFACE
-+	driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
-+	driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
-+	lm_driver_unregister(&dwc_otg_driver);
-+#elif defined(PCI_INTERFACE)
-+	driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
-+	driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
-+	pci_unregister_driver(&dwc_otg_driver);
-+#elif defined(PLATFORM_INTERFACE)
-+	driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
-+	driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
-+	platform_driver_unregister(&dwc_otg_driver);
-+#endif
-+
-+	printk(KERN_INFO "%s module removed\n", dwc_driver_name);
-+}
-+
-+module_exit(dwc_otg_driver_cleanup);
-+
-+MODULE_DESCRIPTION(DWC_DRIVER_DESC);
-+MODULE_AUTHOR("Synopsys Inc.");
-+MODULE_LICENSE("GPL");
-+
-+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
-+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
-+module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
-+MODULE_PARM_DESC(opt, "OPT Mode");
-+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
-+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
-+
-+module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
-+		   0444);
-+MODULE_PARM_DESC(dma_desc_enable,
-+		 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
-+
-+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
-+		   0444);
-+MODULE_PARM_DESC(dma_burst_size,
-+		 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
-+module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
-+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
-+module_param_named(host_support_fs_ls_low_power,
-+		   dwc_otg_module_params.host_support_fs_ls_low_power, int,
-+		   0444);
-+MODULE_PARM_DESC(host_support_fs_ls_low_power,
-+		 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
-+module_param_named(host_ls_low_power_phy_clk,
-+		   dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
-+MODULE_PARM_DESC(host_ls_low_power_phy_clk,
-+		 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
-+module_param_named(enable_dynamic_fifo,
-+		   dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
-+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
-+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
-+		   0444);
-+MODULE_PARM_DESC(data_fifo_size,
-+		 "Total number of words in the data FIFO memory 32-32768");
-+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
-+		   int, 0444);
-+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
-+module_param_named(dev_nperio_tx_fifo_size,
-+		   dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
-+		 "Number of words in the non-periodic Tx FIFO 16-32768");
-+module_param_named(dev_perio_tx_fifo_size_1,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_2,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_3,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_4,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_5,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_6,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_7,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_8,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_9,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_10,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_11,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_12,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_13,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_14,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(dev_perio_tx_fifo_size_15,
-+		   dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
-+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
-+		 "Number of words in the periodic Tx FIFO 4-768");
-+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
-+		   int, 0444);
-+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
-+module_param_named(host_nperio_tx_fifo_size,
-+		   dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(host_nperio_tx_fifo_size,
-+		 "Number of words in the non-periodic Tx FIFO 16-32768");
-+module_param_named(host_perio_tx_fifo_size,
-+		   dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
-+MODULE_PARM_DESC(host_perio_tx_fifo_size,
-+		 "Number of words in the host periodic Tx FIFO 16-32768");
-+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
-+		   int, 0444);
-+/** @todo Set the max to 512K, modify checks */
-+MODULE_PARM_DESC(max_transfer_size,
-+		 "The maximum transfer size supported in bytes 2047-65535");
-+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
-+		   int, 0444);
-+MODULE_PARM_DESC(max_packet_count,
-+		 "The maximum number of packets in a transfer 15-511");
-+module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
-+		   0444);
-+MODULE_PARM_DESC(host_channels,
-+		 "The number of host channel registers to use 1-16");
-+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
-+		   0444);
-+MODULE_PARM_DESC(dev_endpoints,
-+		 "The number of endpoints in addition to EP0 available for device mode 1-15");
-+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
-+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
-+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
-+		   0444);
-+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
-+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
-+MODULE_PARM_DESC(phy_ulpi_ddr,
-+		 "ULPI at double or single data rate 0=Single 1=Double");
-+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
-+		   int, 0444);
-+MODULE_PARM_DESC(phy_ulpi_ext_vbus,
-+		 "ULPI PHY using internal or external vbus 0=Internal");
-+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
-+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
-+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
-+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
-+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
-+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
-+module_param_named(debug, g_dbg_lvl, int, 0444);
-+MODULE_PARM_DESC(debug, "");
-+
-+module_param_named(en_multiple_tx_fifo,
-+		   dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
-+MODULE_PARM_DESC(en_multiple_tx_fifo,
-+		 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
-+module_param_named(dev_tx_fifo_size_1,
-+		   dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_2,
-+		   dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_3,
-+		   dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_4,
-+		   dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_5,
-+		   dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_6,
-+		   dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_7,
-+		   dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_8,
-+		   dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_9,
-+		   dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_10,
-+		   dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_11,
-+		   dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_12,
-+		   dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_13,
-+		   dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_14,
-+		   dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
-+module_param_named(dev_tx_fifo_size_15,
-+		   dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
-+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
-+
-+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
-+MODULE_PARM_DESC(thr_ctl,
-+		 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
-+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
-+		   0444);
-+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
-+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
-+		   0444);
-+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
-+
-+module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
-+module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
-+module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
-+MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
-+module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
-+MODULE_PARM_DESC(ic_usb_cap,
-+		 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
-+module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
-+		   0444);
-+MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
-+module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
-+MODULE_PARM_DESC(power_down, "Power Down Mode");
-+module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
-+MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
-+module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
-+MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
-+module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
-+MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
-+module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
-+MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
-+module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
-+MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
-+module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
-+MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
-+module_param(microframe_schedule, bool, 0444);
-+MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
-+
-+module_param(fiq_enable, bool, 0444);
-+MODULE_PARM_DESC(fiq_enable, "Enable the FIQ");
-+module_param(nak_holdoff, ushort, 0644);
-+MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8");
-+module_param(fiq_fsm_enable, bool, 0444);
-+MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask");
-+module_param(fiq_fsm_mask, ushort, 0444);
-+MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n"
-+					"Bit 0 : Non-periodic split transactions\n"
-+					"Bit 1 : Periodic split transactions\n"
-+					"Bit 2 : High-speed multi-transfer isochronous\n"
-+					"All other bits should be set 0.");
-+module_param(int_ep_interval_min, ushort, 0644);
-+MODULE_PARM_DESC(int_ep_interval_min, "Clamp high-speed Interrupt endpoints to a minimum polling interval.\n"
-+					"0..1 = Use endpoint default\n"
-+					"2..n = Minimum interval n microframes. Use powers of 2.\n");
-+
-+/** @page "Module Parameters"
-+ *
-+ * The following parameters may be specified when starting the module.
-+ * These parameters define how the DWC_otg controller should be
-+ * configured. Parameter values are passed to the CIL initialization
-+ * function dwc_otg_cil_init
-+ *
-+ * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
-+ *
-+
-+ <table>
-+ <tr><td>Parameter Name</td><td>Meaning</td></tr>
-+
-+ <tr>
-+ <td>otg_cap</td>
-+ <td>Specifies the OTG capabilities. The driver will automatically detect the
-+ value for this parameter if none is specified.
-+ - 0: HNP and SRP capable (default, if available)
-+ - 1: SRP Only capable
-+ - 2: No HNP/SRP capable
-+ </td></tr>
-+
-+ <tr>
-+ <td>dma_enable</td>
-+ <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Slave
-+ - 1: DMA (default, if available)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dma_burst_size</td>
-+ <td>The DMA Burst size (applicable only for External DMA Mode).
-+ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
-+ </td></tr>
-+
-+ <tr>
-+ <td>speed</td>
-+ <td>Specifies the maximum speed of operation in host and device mode. The
-+ actual speed depends on the speed of the attached device and the value of
-+ phy_type.
-+ - 0: High Speed (default)
-+ - 1: Full Speed
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_support_fs_ls_low_power</td>
-+ <td>Specifies whether low power mode is supported when attached to a Full
-+ Speed or Low Speed device in host mode.
-+ - 0: Don't support low power mode (default)
-+ - 1: Support low power mode
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_ls_low_power_phy_clk</td>
-+ <td>Specifies the PHY clock rate in low power mode when connected to a Low
-+ Speed device in host mode. This parameter is applicable only if
-+ HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
-+ - 0: 48 MHz (default)
-+ - 1: 6 MHz
-+ </td></tr>
-+
-+ <tr>
-+ <td>enable_dynamic_fifo</td>
-+ <td> Specifies whether FIFOs may be resized by the driver software.
-+ - 0: Use cC FIFO size parameters
-+ - 1: Allow dynamic FIFO sizing (default)
-+ </td></tr>
-+
-+ <tr>
-+ <td>data_fifo_size</td>
-+ <td>Total number of 4-byte words in the data FIFO memory. This memory
-+ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
-+ - Values: 32 to 32768 (default 8192)
-+
-+ Note: The total FIFO memory depth in the FPGA configuration is 8192.
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_rx_fifo_size</td>
-+ <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
-+ FIFO sizing is enabled.
-+ - Values: 16 to 32768 (default 1064)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_nperio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
-+ dynamic FIFO sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
-+ <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
-+ when dynamic FIFO sizing is enabled.
-+ - Values: 4 to 768 (default 256)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_rx_fifo_size</td>
-+ <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
-+ sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_nperio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
-+ dynamic FIFO sizing is enabled in the core.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_perio_tx_fifo_size</td>
-+ <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
-+ sizing is enabled.
-+ - Values: 16 to 32768 (default 1024)
-+ </td></tr>
-+
-+ <tr>
-+ <td>max_transfer_size</td>
-+ <td>The maximum transfer size supported in bytes.
-+ - Values: 2047 to 65,535 (default 65,535)
-+ </td></tr>
-+
-+ <tr>
-+ <td>max_packet_count</td>
-+ <td>The maximum number of packets in a transfer.
-+ - Values: 15 to 511 (default 511)
-+ </td></tr>
-+
-+ <tr>
-+ <td>host_channels</td>
-+ <td>The number of host channel registers to use.
-+ - Values: 1 to 16 (default 12)
-+
-+ Note: The FPGA configuration supports a maximum of 12 host channels.
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_endpoints</td>
-+ <td>The number of endpoints in addition to EP0 available for device mode
-+ operations.
-+ - Values: 1 to 15 (default 6 IN and OUT)
-+
-+ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
-+ addition to EP0.
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_type</td>
-+ <td>Specifies the type of PHY interface to use. By default, the driver will
-+ automatically detect the phy_type.
-+ - 0: Full Speed
-+ - 1: UTMI+ (default, if available)
-+ - 2: ULPI
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_utmi_width</td>
-+ <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
-+ phy_type of UTMI+. Also, this parameter is applicable only if the
-+ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
-+ core has been configured to work at either data path width.
-+ - Values: 8 or 16 bits (default 16)
-+ </td></tr>
-+
-+ <tr>
-+ <td>phy_ulpi_ddr</td>
-+ <td>Specifies whether the ULPI operates at double or single data rate. This
-+ parameter is only applicable if phy_type is ULPI.
-+ - 0: single data rate ULPI interface with 8 bit wide data bus (default)
-+ - 1: double data rate ULPI interface with 4 bit wide data bus
-+ </td></tr>
-+
-+ <tr>
-+ <td>i2c_enable</td>
-+ <td>Specifies whether to use the I2C interface for full speed PHY. This
-+ parameter is only applicable if PHY_TYPE is FS.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>ulpi_fs_ls</td>
-+ <td>Specifies whether to use ULPI FS/LS mode only.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>ts_dline</td>
-+ <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
-+ - 0: Disabled (default)
-+ - 1: Enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>en_multiple_tx_fifo</td>
-+ <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Disabled
-+ - 1: Enabled (default, if available)
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
-+ <td>Number of 4-byte words in each of the Tx FIFOs in device mode
-+ when dynamic FIFO sizing is enabled.
-+ - Values: 4 to 768 (default 256)
-+ </td></tr>
-+
-+ <tr>
-+ <td>tx_thr_length</td>
-+ <td>Transmit Threshold length in 32 bit double words
-+ - Values: 8 to 128 (default 64)
-+ </td></tr>
-+
-+ <tr>
-+ <td>rx_thr_length</td>
-+ <td>Receive Threshold length in 32 bit double words
-+ - Values: 8 to 128 (default 64)
-+ </td></tr>
-+
-+<tr>
-+ <td>thr_ctl</td>
-+ <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
-+ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
-+ Rx transfers accordingly.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - Values: 0 to 7 (default 0)
-+ Bit values indicate:
-+ - 0: Thresholding disabled
-+ - 1: Thresholding enabled
-+ </td></tr>
-+
-+<tr>
-+ <td>dma_desc_enable</td>
-+ <td>Specifies whether to enable Descriptor DMA mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Descriptor DMA disabled
-+ - 1: Descriptor DMA (default, if available)
-+ </td></tr>
-+
-+<tr>
-+ <td>mpi_enable</td>
-+ <td>Specifies whether to enable MPI enhancement mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: MPI disabled (default)
-+ - 1: MPI enable
-+ </td></tr>
-+
-+<tr>
-+ <td>pti_enable</td>
-+ <td>Specifies whether to enable PTI enhancement support.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: PTI disabled (default)
-+ - 1: PTI enable
-+ </td></tr>
-+
-+<tr>
-+ <td>lpm_enable</td>
-+ <td>Specifies whether to enable LPM support.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: LPM disabled
-+ - 1: LPM enable (default, if available)
-+ </td></tr>
-+
-+<tr>
-+ <td>ic_usb_cap</td>
-+ <td>Specifies whether to enable IC_USB capability.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: IC_USB disabled (default, if available)
-+ - 1: IC_USB enable
-+ </td></tr>
-+
-+<tr>
-+ <td>ahb_thr_ratio</td>
-+ <td>Specifies AHB Threshold ratio.
-+ - Values: 0 to 3 (default 0)
-+ </td></tr>
-+
-+<tr>
-+ <td>power_down</td>
-+ <td>Specifies Power Down(Hibernation) Mode.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: Power Down disabled (default)
-+ - 2: Power Down enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>reload_ctl</td>
-+ <td>Specifies whether dynamic reloading of the HFIR register is allowed during
-+ run time. The driver will automatically detect the value for this parameter if
-+ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
-+ the core might misbehave.
-+ - 0: Reload Control disabled (default)
-+ - 1: Reload Control enabled
-+ </td></tr>
-+
-+ <tr>
-+ <td>dev_out_nak</td>
-+ <td>Specifies whether  Device OUT NAK enhancement enabled or no.
-+ The driver will automatically detect the value for this parameter if
-+ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
-+ - 0: The core does not set NAK after Bulk OUT transfer complete (default)
-+ - 1: The core sets NAK after Bulk OUT transfer complete
-+ </td></tr>
-+
-+ <tr>
-+ <td>cont_on_bna</td>
-+ <td>Specifies whether Enable Continue on BNA enabled or no.
-+ After receiving BNA interrupt the core disables the endpoint,when the
-+ endpoint is re-enabled by the application the
-+ - 0: Core starts processing from the DOEPDMA descriptor (default)
-+ - 1: Core starts processing from the descriptor which received the BNA.
-+ This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
-+ </td></tr>
-+
-+ <tr>
-+ <td>ahb_single</td>
-+ <td>This bit when programmed supports SINGLE transfers for remainder data
-+ in a transfer for DMA mode of operation.
-+ - 0: The remainder data will be sent using INCR burst size (default)
-+ - 1: The remainder data will be sent using SINGLE burst size.
-+ </td></tr>
-+
-+<tr>
-+ <td>adp_enable</td>
-+ <td>Specifies whether ADP feature is enabled.
-+ The driver will automatically detect the value for this parameter if none is
-+ specified.
-+ - 0: ADP feature disabled (default)
-+ - 1: ADP feature enabled
-+ </td></tr>
-+
-+  <tr>
-+ <td>otg_ver</td>
-+ <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
-+ USB OTG device.
-+ - 0: OTG 2.0 support disabled (default)
-+ - 1: OTG 2.0 support enabled
-+ </td></tr>
-+
-+*/
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.h
-@@ -0,0 +1,86 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
-+ * $Revision: #19 $
-+ * $Date: 2010/11/15 $
-+ * $Change: 1627671 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_DRIVER_H__
-+#define __DWC_OTG_DRIVER_H__
-+
-+/** @file
-+ * This file contains the interface to the Linux driver.
-+ */
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_otg_core_if.h"
-+
-+/* Type declarations */
-+struct dwc_otg_pcd;
-+struct dwc_otg_hcd;
-+
-+/**
-+ * This structure is a wrapper that encapsulates the driver components used to
-+ * manage a single DWC_otg controller.
-+ */
-+typedef struct dwc_otg_device {
-+	/** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
-+	 * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
-+	 * require this. */
-+	struct os_dependent os_dep;
-+
-+	/** Pointer to the core interface structure. */
-+	dwc_otg_core_if_t *core_if;
-+
-+	/** Pointer to the PCD structure. */
-+	struct dwc_otg_pcd *pcd;
-+
-+	/** Pointer to the HCD structure. */
-+	struct dwc_otg_hcd *hcd;
-+
-+	/** Flag to indicate whether the common IRQ handler is installed. */
-+	uint8_t common_irq_installed;
-+
-+} dwc_otg_device_t;
-+
-+/*We must clear S3C24XX_EINTPEND external interrupt register
-+ * because after clearing in this register trigerred IRQ from
-+ * H/W core in kernel interrupt can be occured again before OTG
-+ * handlers clear all IRQ sources of Core registers because of
-+ * timing latencies and Low Level IRQ Type.
-+ */
-+#ifdef CONFIG_MACH_IPMATE
-+#define  S3C2410X_CLEAR_EINTPEND()   \
-+do { \
-+	__raw_writel(1UL << 11,S3C24XX_EINTPEND); \
-+} while (0)
-+#else
-+#define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
-+#endif
-+
-+#endif
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-@@ -0,0 +1,1389 @@
-+/*
-+ * dwc_otg_fiq_fsm.c - The finite state machine FIQ
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *	* Redistributions of source code must retain the above copyright
-+ *	  notice, this list of conditions and the following disclaimer.
-+ *	* Redistributions in binary form must reproduce the above copyright
-+ *	  notice, this list of conditions and the following disclaimer in the
-+ *	  documentation and/or other materials provided with the distribution.
-+ *	* Neither the name of Raspberry Pi nor the
-+ *	  names of its contributors may be used to endorse or promote products
-+ *	  derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * This FIQ implements functionality that performs split transactions on
-+ * the dwc_otg hardware without any outside intervention. A split transaction
-+ * is "queued" by nominating a specific host channel to perform the entirety
-+ * of a split transaction. This FIQ will then perform the microframe-precise
-+ * scheduling required in each phase of the transaction until completion.
-+ *
-+ * The FIQ functionality is glued into the Synopsys driver via the entry point
-+ * in the FSM enqueue function, and at the exit point in handling a HC interrupt
-+ * for a FSM-enabled channel.
-+ *
-+ * NB: Large parts of this implementation have architecture-specific code.
-+ * For porting this functionality to other ARM machines, the minimum is required:
-+ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed
-+ *   to the FIQ
-+ * - A method of forcing a software generated interrupt from FIQ mode that then
-+ *   triggers an IRQ entry (with the dwc USB handler called by this IRQ number)
-+ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same
-+ *   processor core - there is no locking between the FIQ and IRQ (aside from
-+ *   local_fiq_disable)
-+ *
-+ */
-+
-+#include "dwc_otg_fiq_fsm.h"
-+
-+
-+char buffer[1000*16];
-+int wptr;
-+void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...)
-+{
-+	enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR;
-+	va_list args;
-+	char text[17];
-+	hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) };
-+
-+	if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR)
-+	{
-+		snprintf(text, 9, " %4d:%1u  ", hfnum.b.frnum/8, hfnum.b.frnum & 7);
-+		va_start(args, fmt);
-+		vsnprintf(text+8, 9, fmt, args);
-+		va_end(args);
-+
-+		memcpy(buffer + wptr, text, 16);
-+		wptr = (wptr + 16) % sizeof(buffer);
-+	}
-+}
-+
-+/**
-+ * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock
-+ * Must be called with local interrupts and FIQ disabled.
-+ */
-+#if defined(CONFIG_ARCH_BCM2835) && defined(CONFIG_SMP)
-+inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
-+{
-+	unsigned long tmp;
-+	uint32_t newval;
-+	fiq_lock_t lockval;
-+	/* Nested locking, yay. If we are on the same CPU as the fiq, then the disable
-+	 * will be sufficient. If we are on a different CPU, then the lock protects us. */
-+	prefetchw(&lock->slock);
-+	asm volatile (
-+	"1:     ldrex   %0, [%3]\n"
-+	"       add     %1, %0, %4\n"
-+	"       strex   %2, %1, [%3]\n"
-+	"       teq     %2, #0\n"
-+	"       bne     1b"
-+	: "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
-+	: "r" (&lock->slock), "I" (1 << 16)
-+	: "cc");
-+
-+	while (lockval.tickets.next != lockval.tickets.owner) {
-+		wfe();
-+		lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
-+	}
-+	smp_mb();
-+}
-+#else
-+inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { }
-+#endif
-+
-+/**
-+ * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock
-+ */
-+#if defined(CONFIG_ARCH_BCM2835) && defined(CONFIG_SMP)
-+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
-+{
-+	smp_mb();
-+	lock->tickets.owner++;
-+	dsb_sev();
-+}
-+#else
-+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { }
-+#endif
-+
-+/**
-+ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction
-+ * @channel: channel to re-enable
-+ */
-+static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force)
-+{
-+	hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) };
-+
-+	hcchar.b.chen = 0;
-+	if (st->channel[n].hcchar_copy.b.eptype & 0x1) {
-+		hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+		/* Hardware bug workaround: update the ssplit index */
-+		if (st->channel[n].hcsplt_copy.b.spltena)
-+			st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
-+
-+		hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0	: 1;
-+	}
-+
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
-+	hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+	hcchar.b.chen = 1;
-+
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
-+	fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force);
-+}
-+
-+/**
-+ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage
-+ * @st: Pointer to the channel's state
-+ * @n : channel number
-+ *
-+ * Change host channel registers to perform a complete-split transaction. Being mindful of the
-+ * endpoint direction, set control regs up correctly.
-+ */
-+static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n)
-+{
-+	hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) };
-+	hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+
-+	hcsplt.b.compsplt = 1;
-+	if (st->channel[n].hcchar_copy.b.epdir == 1) {
-+		// If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket.
-+		hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
-+	} else {
-+		// If OUT, the CSPLIT result contains handshake only.
-+		hctsiz.b.xfersize = 0;
-+	}
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+	mb();
-+}
-+
-+/**
-+ * fiq_fsm_restart_np_pending() - Restart a single non-periodic contended transfer
-+ * @st: Pointer to the channel's state
-+ * @num_channels: Total number of host channels
-+ * @orig_channel: Channel index of completed transfer
-+ *
-+ * In the case where an IN and OUT transfer are simultaneously scheduled to the
-+ * same device/EP, inadequate hub implementations will misbehave. Once the first
-+ * transfer is complete, a pending non-periodic split can then be issued.
-+ */
-+static void notrace fiq_fsm_restart_np_pending(struct fiq_state *st, int num_channels, int orig_channel)
-+{
-+	int i;
-+	int dev_addr = st->channel[orig_channel].hcchar_copy.b.devaddr;
-+	int ep_num = st->channel[orig_channel].hcchar_copy.b.epnum;
-+	for (i = 0; i < num_channels; i++) {
-+		if (st->channel[i].fsm == FIQ_NP_SSPLIT_PENDING &&
-+			st->channel[i].hcchar_copy.b.devaddr == dev_addr &&
-+			st->channel[i].hcchar_copy.b.epnum == ep_num) {
-+			st->channel[i].fsm = FIQ_NP_SSPLIT_STARTED;
-+			fiq_fsm_restart_channel(st, i, 0);
-+			break;
-+		}
-+	}
-+}
-+
-+static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n)
-+{
-+	/* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */
-+	hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+
-+	if (st->channel[n].hcchar_copy.b.epdir == 0) {
-+		return st->channel[n].hctsiz_copy.b.xfersize;
-+	} else {
-+		return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize;
-+	}
-+
-+}
-+
-+
-+/**
-+ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT
-+ *
-+ * Of use only for IN periodic transfers.
-+ */
-+static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n)
-+{
-+	hcdma_data_t hcdma;
-+	int i = st->channel[n].dma_info.index;
-+	int len;
-+	struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
-+
-+	len = fiq_get_xfer_len(st, n);
-+	fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
-+	st->channel[n].dma_info.slot_len[i] = len;
-+	i++;
-+	if (i > 6)
-+		BUG();
-+
-+	hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
-+	FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+	st->channel[n].dma_info.index = i;
-+	return 0;
-+}
-+
-+/**
-+ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ
-+ */
-+static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n)
-+{
-+	hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
-+	hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
-+	hctsiz.b.pktcnt = 1;
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+}
-+
-+/**
-+ * fiq_iso_out_advance() - update DMA address and split position bits
-+ * for isochronous OUT transactions.
-+ *
-+ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and
-+ * Split-BEGIN states are not handled - this is done when the transaction was queued.
-+ *
-+ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state.
-+ */
-+static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n)
-+{
-+	hcsplt_data_t hcsplt;
-+	hctsiz_data_t hctsiz;
-+	hcdma_data_t hcdma;
-+	struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
-+	int last = 0;
-+	int i = st->channel[n].dma_info.index;
-+
-+	fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i);
-+	i++;
-+	if (i == 4)
-+		last = 1;
-+	if (st->channel[n].dma_info.slot_len[i+1] == 255)
-+		last = 1;
-+
-+	/* New DMA address - address of bounce buffer referred to in index */
-+	hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
-+	//hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
-+	//hcdma.d32 += st->channel[n].dma_info.slot_len[i];
-+	fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
-+	fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
-+	hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT);
-+	hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ);
-+	hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID;
-+	/* Set up new packet length */
-+	hctsiz.b.pktcnt = 1;
-+	hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i];
-+	fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32);
-+
-+	st->channel[n].dma_info.index++;
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
-+	FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+	return last;
-+}
-+
-+/**
-+ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT
-+ *
-+ * Despite the limitations of the DWC core, we can force a microframe pipeline of
-+ * isochronous OUT start-split transactions while waiting for a corresponding other-type
-+ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it
-+ * is very unlikely that filling the start-split FIFO will cause data loss.
-+ * This allows much better interleaving of transactions in an order-independent way-
-+ * there is no requirement to prioritise isochronous, just a state-space search has
-+ * to be performed on each periodic start-split complete interrupt.
-+ */
-+static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n)
-+{
-+	int hub_addr = st->channel[n].hub_addr;
-+	int port_addr = st->channel[n].port_addr;
-+	int i, poked = 0;
-+	for (i = 0; i < num_channels; i++) {
-+		if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
-+			continue;
-+		if (st->channel[i].hub_addr == hub_addr &&
-+			st->channel[i].port_addr == port_addr) {
-+			switch (st->channel[i].fsm) {
-+			case FIQ_PER_ISO_OUT_PENDING:
-+				if (st->channel[i].nrpackets == 1) {
-+					st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST;
-+				} else {
-+					st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+				}
-+				fiq_fsm_restart_channel(st, i, 0);
-+				poked = 1;
-+				break;
-+
-+			default:
-+				break;
-+			}
-+		}
-+		if (poked)
-+			break;
-+	}
-+	return poked;
-+}
-+
-+/**
-+ * fiq_fsm_tt_in_use() - search for host channels using this TT
-+ * @n: Channel to use as reference
-+ *
-+ */
-+int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n)
-+{
-+	int hub_addr = st->channel[n].hub_addr;
-+	int port_addr = st->channel[n].port_addr;
-+	int i, in_use = 0;
-+	for (i = 0; i < num_channels; i++) {
-+		if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
-+			continue;
-+		switch (st->channel[i].fsm) {
-+		/* TT is reserved for channels that are in the middle of a periodic
-+		 * split transaction.
-+		 */
-+		case FIQ_PER_SSPLIT_STARTED:
-+		case FIQ_PER_CSPLIT_WAIT:
-+		case FIQ_PER_CSPLIT_NYET1:
-+		//case FIQ_PER_CSPLIT_POLL:
-+		case FIQ_PER_ISO_OUT_ACTIVE:
-+		case FIQ_PER_ISO_OUT_LAST:
-+			if (st->channel[i].hub_addr == hub_addr &&
-+				st->channel[i].port_addr == port_addr) {
-+				in_use = 1;
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+		if (in_use)
-+			break;
-+	}
-+	return in_use;
-+}
-+
-+/**
-+ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need
-+ * 			to be issued for this IN transaction.
-+ *
-+ * We cannot tell the inbound PID of a data packet due to hardware limitations.
-+ * we need to make an educated guess as to whether we need to queue another CSPLIT
-+ * or not. A no-brainer is when we have received enough data to fill the endpoint
-+ * size, but for endpoints that give variable-length data then we have to resort
-+ * to heuristics.
-+ *
-+ * We also return whether this is the last CSPLIT to be queued, again based on
-+ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions.
-+ * Note: requires at least 1 CSPLIT to have been performed prior to being called.
-+ */
-+
-+/*
-+ * We need some way of guaranteeing if a returned periodic packet of size X
-+ * has a DATA0 PID.
-+ * The heuristic value of 144 bytes assumes that the received data has maximal
-+ * bit-stuffing and the clock frequency of the transmitting device is at the lowest
-+ * permissible limit. If the transfer length results in a final packet size
-+ * 144 < p <= 188, then an erroneous CSPLIT will be issued.
-+ * Also used to ensure that an endpoint will nominally only return a single
-+ * complete-split worth of data.
-+ */
-+#define DATA0_PID_HEURISTIC 144
-+
-+static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last)
-+{
-+
-+	int i;
-+	int total_len = 0;
-+	int more_needed = 1;
-+	struct fiq_channel_state *st = &state->channel[n];
-+
-+	for (i = 0; i < st->dma_info.index; i++) {
-+			total_len += st->dma_info.slot_len[i];
-+	}
-+
-+	*probably_last = 0;
-+
-+	if (st->hcchar_copy.b.eptype == 0x3) {
-+		/*
-+		 * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data
-+		 * then this is definitely the last CSPLIT.
-+		 */
-+		*probably_last = 1;
-+	} else {
-+		/* Isoc IN. This is a bit risky if we are the first transaction:
-+		 * we may have been held off slightly. */
-+		if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) {
-+			more_needed = 0;
-+		}
-+		/* If in the next uframe we will receive enough data to fill the endpoint,
-+		 * then only issue 1 more csplit.
-+		 */
-+		if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC)
-+			*probably_last = 1;
-+	}
-+
-+	if (total_len >= st->hctsiz_copy.b.xfersize ||
-+		i == 6 || total_len == 0)
-+		/* Note: due to bit stuffing it is possible to have > 6 CSPLITs for
-+		 * a single endpoint. Accepting more would completely break our scheduling mechanism though
-+		 * - in these extreme cases we will pass through a truncated packet.
-+		 */
-+		more_needed = 0;
-+
-+	return more_needed;
-+}
-+
-+/**
-+ * fiq_fsm_too_late() - Test transaction for lateness
-+ *
-+ * If a SSPLIT for a large IN transaction is issued too late in a frame,
-+ * the hub will disable the port to the device and respond with ERR handshakes.
-+ * The hub status endpoint will not reflect this change.
-+ * Returns 1 if we will issue a SSPLIT that will result in a device babble.
-+ */
-+int notrace fiq_fsm_too_late(struct fiq_state *st, int n)
-+{
-+	int uframe;
-+	hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+	uframe = hfnum.b.frnum & 0x7;
-+	if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) {
-+		return 1;
-+	} else {
-+		return 0;
-+	}
-+}
-+
-+
-+/**
-+ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline
-+ *
-+ * Search pending transactions in the start-split pending state and queue them.
-+ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4).
-+ * Note: we specifically don't do isochronous OUT transactions first because better
-+ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT.
-+ */
-+static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels)
-+{
-+	int n;
-+	hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
-+	if ((hfnum.b.frnum & 0x7) == 5)
-+		return;
-+	for (n = 0; n < num_channels; n++) {
-+		if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) {
-+			/* Check to see if any other transactions are using this TT */
-+			if(!fiq_fsm_tt_in_use(st, num_channels, n)) {
-+				if (!fiq_fsm_too_late(st, n)) {
-+					st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
-+					fiq_print(FIQDBG_INT, st, "NEXTPER ");
-+					fiq_fsm_restart_channel(st, n, 0);
-+				} else {
-+					st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+				}
-+				break;
-+			}
-+		}
-+	}
-+	for (n = 0; n < num_channels; n++) {
-+		if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) {
-+			if (!fiq_fsm_tt_in_use(st, num_channels, n)) {
-+				fiq_print(FIQDBG_INT, st, "NEXTISO ");
-+				if (st->channel[n].nrpackets == 1)
-+					st->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
-+				else
-+					st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+				fiq_fsm_restart_channel(st, n, 0);
-+				break;
-+			}
-+		}
-+	}
-+}
-+
-+/**
-+ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data
-+ * @state:	Pointer to fiq_state
-+ * @n:		Channel transaction is active on
-+ * @hcint:	Copy of host channel interrupt register
-+ *
-+ * Returns 0 if there are no more transactions for this HC to do, 1
-+ * otherwise.
-+ */
-+static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint)
-+{
-+	struct fiq_channel_state *st = &state->channel[n];
-+	int xfer_len = 0, nrpackets = 0;
-+	hcdma_data_t hcdma;
-+	fiq_print(FIQDBG_INT, state, "HSISO %02d", n);
-+
-+	xfer_len = fiq_get_xfer_len(state, n);
-+	st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len;
-+
-+	st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32;
-+
-+	st->hs_isoc_info.index++;
-+	if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) {
-+		return 0;
-+	}
-+
-+	/* grab the next DMA address offset from the array */
-+	hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
-+	FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+
-+	/* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
-+	 * the core needs to be told to send the correct number. Caution: for IN transfers,
-+	 * this is always set to the maximum size of the endpoint. */
-+	xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length;
-+	/* Integer divide in a FIQ: fun. FIXME: make this not suck */
-+	nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
-+	if (nrpackets == 0)
-+		nrpackets = 1;
-+	st->hcchar_copy.b.multicnt = nrpackets;
-+	st->hctsiz_copy.b.pktcnt = nrpackets;
-+
-+	/* Initial PID also needs to be set */
-+	if (st->hcchar_copy.b.epdir == 0) {
-+		st->hctsiz_copy.b.xfersize = xfer_len;
-+		switch (st->hcchar_copy.b.multicnt) {
-+		case 1:
-+			st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+			break;
-+		case 2:
-+		case 3:
-+			st->hctsiz_copy.b.pid = DWC_PID_MDATA;
-+			break;
-+		}
-+
-+	} else {
-+		switch (st->hcchar_copy.b.multicnt) {
-+		st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
-+		case 1:
-+			st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+			break;
-+		case 2:
-+			st->hctsiz_copy.b.pid = DWC_PID_DATA1;
-+			break;
-+		case 3:
-+			st->hctsiz_copy.b.pid = DWC_PID_DATA2;
-+			break;
-+		}
-+	}
-+	FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32);
-+	FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32);
-+	/* Channel is enabled on hcint handler exit */
-+	fiq_print(FIQDBG_INT, state, "HSISOOUT");
-+	return 1;
-+}
-+
-+
-+/**
-+ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler
-+ * @state:	Pointer to the state struct passed from banked FIQ mode registers.
-+ * @num_channels:	set according to the DWC hardware configuration
-+ *
-+ * The SOF handler in FSM mode has two functions
-+ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's
-+ *    nothing to do
-+ * 2. Advance certain FSM states that require either a microframe delay, or a microframe
-+ *    of holdoff.
-+ *
-+ * The second part is architecture-specific to mach-bcm2835 -
-+ * a sane interrupt controller would have a mask register for ARM interrupt sources
-+ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt
-+ * number (USB) can be enabled. This means that certain parts of the USB specification
-+ * that require "wait a little while, then issue another packet" cannot be fulfilled with
-+ * the timing granularity required to achieve optimal throughout. The workaround is to use
-+ * the SOF "timer" (125uS) to perform this task.
-+ */
-+static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels)
-+{
-+	hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) };
-+	int n;
-+	int kick_irq = 0;
-+
-+	if ((hfnum.b.frnum & 0x7) == 1) {
-+		/* We cannot issue csplits for transactions in the last frame past (n+1).1
-+		 * Check to see if there are any transactions that are stale.
-+		 * Boot them out.
-+		 */
-+		for (n = 0; n < num_channels; n++) {
-+			switch (state->channel[n].fsm) {
-+			case FIQ_PER_CSPLIT_WAIT:
-+			case FIQ_PER_CSPLIT_NYET1:
-+			case FIQ_PER_CSPLIT_POLL:
-+			case FIQ_PER_CSPLIT_LAST:
-+				/* Check if we are no longer in the same full-speed frame. */
-+				if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) <
-+						(hfnum.b.frnum & ~0x7))
-+					state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+				break;
-+			default:
-+				break;
-+			}
-+		}
-+	}
-+
-+	for (n = 0; n < num_channels; n++) {
-+		switch (state->channel[n].fsm) {
-+
-+		case FIQ_NP_SSPLIT_RETRY:
-+		case FIQ_NP_IN_CSPLIT_RETRY:
-+		case FIQ_NP_OUT_CSPLIT_RETRY:
-+			fiq_fsm_restart_channel(state, n, 0);
-+			break;
-+
-+		case FIQ_HS_ISOC_SLEEPING:
-+			/* Is it time to wake this channel yet? */
-+			if (--state->channel[n].uframe_sleeps == 0) {
-+				state->channel[n].fsm = FIQ_HS_ISOC_TURBO;
-+				fiq_fsm_restart_channel(state, n, 0);
-+			}
-+			break;
-+
-+		case FIQ_PER_SSPLIT_QUEUED:
-+			if ((hfnum.b.frnum & 0x7) == 5)
-+				break;
-+			if(!fiq_fsm_tt_in_use(state, num_channels, n)) {
-+				if (!fiq_fsm_too_late(state, n)) {
-+					fiq_print(FIQDBG_INT, state, "SOF GO %01d", n);
-+					fiq_fsm_restart_channel(state, n, 0);
-+					state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
-+				} else {
-+					/* Transaction cannot be started without risking a device babble error */
-+					state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
-+					state->haintmsk_saved.b2.chint &= ~(1 << n);
-+					FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
-+					kick_irq |= 1;
-+				}
-+			}
-+			break;
-+
-+		case FIQ_PER_ISO_OUT_PENDING:
-+			/* Ordinarily, this should be poked after the SSPLIT
-+			 * complete interrupt for a competing transfer on the same
-+			 * TT. Doesn't happen for aborted transactions though.
-+			 */
-+			if ((hfnum.b.frnum & 0x7) >= 5)
-+				break;
-+			if (!fiq_fsm_tt_in_use(state, num_channels, n)) {
-+				/* Hardware bug. SOF can sometimes occur after the channel halt interrupt
-+				 * that caused this.
-+				 */
-+					fiq_fsm_restart_channel(state, n, 0);
-+					fiq_print(FIQDBG_INT, state, "SOF ISOC");
-+					if (state->channel[n].nrpackets == 1) {
-+						state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
-+					} else {
-+						state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+					}
-+			}
-+			break;
-+
-+		case FIQ_PER_CSPLIT_WAIT:
-+			/* we are guaranteed to be in this state if and only if the SSPLIT interrupt
-+			 * occurred when the bus transaction occurred. The SOF interrupt reversal bug
-+			 * will utterly bugger this up though.
-+			 */
-+			if (hfnum.b.frnum != state->channel[n].expected_uframe) {
-+				fiq_print(FIQDBG_INT, state, "SOFCS %d ", n);
-+				state->channel[n].fsm = FIQ_PER_CSPLIT_POLL;
-+				fiq_fsm_restart_channel(state, n, 0);
-+				fiq_fsm_start_next_periodic(state, num_channels);
-+
-+			}
-+			break;
-+
-+		case FIQ_PER_SPLIT_TIMEOUT:
-+		case FIQ_DEQUEUE_ISSUED:
-+			/* Ugly: we have to force a HCD interrupt.
-+			 * Poke the mask for the channel in question.
-+			 * We will take a fake SOF because of this, but
-+			 * that's OK.
-+			 */
-+			state->haintmsk_saved.b2.chint &= ~(1 << n);
-+			FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
-+			kick_irq |= 1;
-+			break;
-+
-+		default:
-+			break;
-+		}
-+	}
-+
-+	if (state->kick_np_queues ||
-+			dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum))
-+		kick_irq |= 1;
-+
-+	return !kick_irq;
-+}
-+
-+
-+/**
-+ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler
-+ * @state: Pointer to the FIQ state struct
-+ * @num_channels: Number of channels as per hardware config
-+ * @n: channel for which HAINT(i) was raised
-+ *
-+ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well.
-+ */
-+static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n)
-+{
-+	hcint_data_t hcint;
-+	hcintmsk_data_t hcintmsk;
-+	hcint_data_t hcint_probe;
-+	hcchar_data_t hcchar;
-+	int handled = 0;
-+	int restart = 0;
-+	int last_csplit = 0;
-+	int start_next_periodic = 0;
-+	struct fiq_channel_state *st = &state->channel[n];
-+	hfnum_data_t hfnum;
-+
-+	hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT);
-+	hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK);
-+	hcint_probe.d32 = hcint.d32 & hcintmsk.d32;
-+
-+	if (st->fsm != FIQ_PASSTHROUGH) {
-+		fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm);
-+		fiq_print(FIQDBG_INT, state, "%08x", hcint.d32);
-+	}
-+
-+	switch (st->fsm) {
-+
-+	case FIQ_PASSTHROUGH:
-+	case FIQ_DEQUEUE_ISSUED:
-+		/* doesn't belong to us, kick it upstairs */
-+		break;
-+
-+	case FIQ_PASSTHROUGH_ERRORSTATE:
-+		/* We are here to emulate the error recovery mechanism of the dwc HCD.
-+		 * Several interrupts are unmasked if a previous transaction failed - it's
-+		 * death for the FIQ to attempt to handle them as the channel isn't halted.
-+		 * Emulate what the HCD does in this situation: mask and continue.
-+		 * The FSM has no other state setup so this has to be handled out-of-band.
-+		 */
-+		fiq_print(FIQDBG_ERR, state, "ERRST %02d", n);
-+		if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {
-+			fiq_print(FIQDBG_ERR, state, "RESET %02d", n);
-+			/* In some random cases we can get a NAK interrupt coincident with a Xacterr
-+			 * interrupt, after the device has disappeared.
-+			 */
-+			if (!hcint.b.xacterr)
-+				st->nr_errors = 0;
-+			hcintmsk.b.nak = 0;
-+			hcintmsk.b.ack = 0;
-+			hcintmsk.b.datatglerr = 0;
-+			FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32);
-+			return 1;
-+		}
-+		if (hcint_probe.b.chhltd) {
-+			fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n);
-+			fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32);
-+			return 0;
-+		}
-+		break;
-+
-+	/* Non-periodic state groups */
-+	case FIQ_NP_SSPLIT_STARTED:
-+	case FIQ_NP_SSPLIT_RETRY:
-+		/* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */
-+		if (hcint.b.ack) {
-+			/* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction
-+			 * will start shortly. SOF needs to kick the transaction to prevent a NYET flood.
-+			 */
-+			if(st->hcchar_copy.b.epdir == 1)
-+				st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
-+			else
-+				st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+			st->nr_errors = 0;
-+			handled = 1;
-+			fiq_fsm_setup_csplit(state, n);
-+		} else if (hcint.b.nak) {
-+			// No buffer space in TT. Retry on a uframe boundary.
-+			st->fsm = FIQ_NP_SSPLIT_RETRY;
-+			handled = 1;
-+		} else if (hcint.b.xacterr) {
-+			// The only other one we care about is xacterr. This implies HS bus error - retry.
-+			st->nr_errors++;
-+			st->fsm = FIQ_NP_SSPLIT_RETRY;
-+			if (st->nr_errors >= 3) {
-+				st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+			} else {
-+				handled = 1;
-+				restart = 1;
-+			}
-+		} else {
-+			st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+			handled = 0;
-+			restart = 0;
-+		}
-+		break;
-+
-+	case FIQ_NP_IN_CSPLIT_RETRY:
-+		/* Received a CSPLIT done interrupt.
-+		 * Expected Data/NAK/STALL/NYET for IN.
-+		 */
-+		if (hcint.b.xfercomp) {
-+			/* For IN, data is present. */
-+			st->fsm = FIQ_NP_SPLIT_DONE;
-+		} else if (hcint.b.nak) {
-+			/* no endpoint data. Punt it upstairs */
-+			st->fsm = FIQ_NP_SPLIT_DONE;
-+		} else if (hcint.b.nyet) {
-+			/* CSPLIT NYET - retry on a uframe boundary. */
-+			handled = 1;
-+			st->nr_errors = 0;
-+		} else if (hcint.b.datatglerr) {
-+			/* data toggle errors do not set the xfercomp bit. */
-+			st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+		} else if (hcint.b.xacterr) {
-+			/* HS error. Retry immediate */
-+			st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
-+			st->nr_errors++;
-+			if (st->nr_errors >= 3) {
-+				st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+			} else {
-+				handled = 1;
-+				restart = 1;
-+			}
-+		} else if (hcint.b.stall || hcint.b.bblerr) {
-+			/* A STALL implies either a LS bus error or a genuine STALL. */
-+			st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+		} else {
-+			/*  Hardware bug. It's possible in some cases to
-+			 *  get a channel halt with nothing else set when
-+			 *  the response was a NYET. Treat as local 3-strikes retry.
-+			 */
-+			hcint_data_t hcint_test = hcint;
-+			hcint_test.b.chhltd = 0;
-+			if (!hcint_test.d32) {
-+				st->nr_errors++;
-+				if (st->nr_errors >= 3) {
-+					st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+				} else {
-+					handled = 1;
-+				}
-+			} else {
-+				/* Bail out if something unexpected happened */
-+				st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+			}
-+		}
-+		if (st->fsm != FIQ_NP_IN_CSPLIT_RETRY) {
-+			fiq_fsm_restart_np_pending(state, num_channels, n);
-+		}
-+		break;
-+
-+	case FIQ_NP_OUT_CSPLIT_RETRY:
-+		/* Received a CSPLIT done interrupt.
-+		 * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/
-+		if (hcint.b.xfercomp) {
-+			st->fsm = FIQ_NP_SPLIT_DONE;
-+		} else if (hcint.b.nak) {
-+			// The HCD will implement the holdoff on frame boundaries.
-+			st->fsm = FIQ_NP_SPLIT_DONE;
-+		} else if (hcint.b.nyet) {
-+			// Hub still processing.
-+			st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+			handled = 1;
-+			st->nr_errors = 0;
-+			//restart = 1;
-+		} else if (hcint.b.xacterr) {
-+			/* HS error. retry immediate */
-+			st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
-+			st->nr_errors++;
-+			if (st->nr_errors >= 3) {
-+				st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+			} else {
-+				handled = 1;
-+				restart = 1;
-+			}
-+		} else if (hcint.b.stall) {
-+			/* LS bus error or genuine stall */
-+			st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
-+		} else {
-+			/*
-+			 * Hardware bug. It's possible in some cases to get a
-+			 * channel halt with nothing else set when the response was a NYET.
-+			 * Treat as local 3-strikes retry.
-+			 */
-+			hcint_data_t hcint_test = hcint;
-+			hcint_test.b.chhltd = 0;
-+			if (!hcint_test.d32) {
-+				st->nr_errors++;
-+				if (st->nr_errors >= 3) {
-+					st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+				} else {
-+					handled = 1;
-+				}
-+			} else {
-+				// Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it.
-+				st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
-+			}
-+		}
-+		if (st->fsm != FIQ_NP_OUT_CSPLIT_RETRY) {
-+			fiq_fsm_restart_np_pending(state, num_channels, n);
-+		}
-+		break;
-+
-+	/* Periodic split states (except isoc out) */
-+	case FIQ_PER_SSPLIT_STARTED:
-+		/* Expect an ACK or failure for SSPLIT */
-+		if (hcint.b.ack) {
-+			/*
-+			 * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs.
-+			 * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1
-+			 * point for microframe n-3, the packet will not appear on the bus until microframe n.
-+			 * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus
-+			 * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1
-+			 * coincident with SOF for n+1.
-+			 * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place.
-+			 * These appear to be caused by timing/clock crossing bugs within the core itself.
-+			 * State machine workaround.
-+			 */
-+			hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+			hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+			fiq_fsm_setup_csplit(state, n);
-+			/* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct
-+			 * time. If not, then we're in the next SOF.
-+			 */
-+			if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) {
-+				fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n);
-+				st->expected_uframe = hfnum.b.frnum;
-+				st->fsm = FIQ_PER_CSPLIT_WAIT;
-+			} else {
-+				fiq_print(FIQDBG_INT, state, "CSPOL  %01d", n);
-+				/* For isochronous IN endpoints,
-+				 * we need to hold off if we are expecting a lot of data */
-+				if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) {
-+					start_next_periodic = 1;
-+				}
-+				/* Danger will robinson: we are in a broken state. If our first interrupt after
-+				 * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable
-+				 * lag. Unmask the NYET interrupt.
-+				 */
-+				st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
-+				st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1;
-+				restart = 1;
-+			}
-+			handled = 1;
-+		} else if (hcint.b.xacterr) {
-+			/* 3-strikes retry is enabled, we have hit our max nr_errors */
-+			st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+			start_next_periodic = 1;
-+		} else {
-+			st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+			start_next_periodic = 1;
-+		}
-+		/* We can now queue the next isochronous OUT transaction, if one is pending. */
-+		if(fiq_fsm_tt_next_isoc(state, num_channels, n)) {
-+			fiq_print(FIQDBG_INT, state, "NEXTISO ");
-+		}
-+		break;
-+
-+	case FIQ_PER_CSPLIT_NYET1:
-+		/* First CSPLIT attempt was a NYET. If we get a subsequent NYET,
-+		 * we are too late and the TT has dropped its CSPLIT fifo.
-+		 */
-+		hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+		hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+		start_next_periodic = 1;
-+		if (hcint.b.nak) {
-+			st->fsm = FIQ_PER_SPLIT_DONE;
-+		} else if (hcint.b.xfercomp) {
-+			fiq_increment_dma_buf(state, num_channels, n);
-+			st->fsm = FIQ_PER_CSPLIT_POLL;
-+			st->nr_errors = 0;
-+			if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+				handled = 1;
-+				restart = 1;
-+				if (!last_csplit)
-+					start_next_periodic = 0;
-+			} else {
-+				st->fsm = FIQ_PER_SPLIT_DONE;
-+			}
-+		} else if (hcint.b.nyet) {
-+			/* Doh. Data lost. */
-+			st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+		} else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+			st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+		} else {
-+			st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+		}
-+		break;
-+
-+	case FIQ_PER_CSPLIT_BROKEN_NYET1:
-+		/*
-+		 * we got here because our host channel is in the delayed-interrupt
-+		 * state and we cannot take a NYET interrupt any later than when it
-+		 * occurred. Disable then re-enable the channel if this happens to force
-+		 * CSPLITs to occur at the right time.
-+		 */
-+		hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+		hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+		fiq_print(FIQDBG_INT, state, "BROK: %01d ", n);
-+		if (hcint.b.nak) {
-+			st->fsm = FIQ_PER_SPLIT_DONE;
-+			start_next_periodic = 1;
-+		} else if (hcint.b.xfercomp) {
-+			fiq_increment_dma_buf(state, num_channels, n);
-+			if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+				st->fsm = FIQ_PER_CSPLIT_POLL;
-+				handled = 1;
-+				restart = 1;
-+				start_next_periodic = 1;
-+				/* Reload HCTSIZ for the next transfer */
-+				fiq_fsm_reload_hctsiz(state, n);
-+				if (!last_csplit)
-+					start_next_periodic = 0;
-+			} else {
-+				st->fsm = FIQ_PER_SPLIT_DONE;
-+			}
-+		} else if (hcint.b.nyet) {
-+			st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+			start_next_periodic = 1;
-+		} else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+			/* Local 3-strikes retry is handled by the core. This is a ERR response.*/
-+			st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+		} else {
-+			st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+		}
-+		break;
-+
-+	case FIQ_PER_CSPLIT_POLL:
-+		hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+		hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
-+		start_next_periodic = 1;
-+		if (hcint.b.nak) {
-+			st->fsm = FIQ_PER_SPLIT_DONE;
-+		} else if (hcint.b.xfercomp) {
-+			fiq_increment_dma_buf(state, num_channels, n);
-+			if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
-+				handled = 1;
-+				restart = 1;
-+				/* Reload HCTSIZ for the next transfer */
-+				fiq_fsm_reload_hctsiz(state, n);
-+				if (!last_csplit)
-+					start_next_periodic = 0;
-+			} else {
-+				st->fsm = FIQ_PER_SPLIT_DONE;
-+			}
-+		} else if (hcint.b.nyet) {
-+			/* Are we a NYET after the first data packet? */
-+			if (st->nrpackets == 0) {
-+				st->fsm = FIQ_PER_CSPLIT_NYET1;
-+				handled = 1;
-+				restart = 1;
-+			} else {
-+				/* We got a NYET when polling CSPLITs. Can happen
-+				 * if our heuristic fails, or if someone disables us
-+				 * for any significant length of time.
-+				 */
-+				if (st->nr_errors >= 3) {
-+					st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
-+				} else {
-+					st->fsm = FIQ_PER_SPLIT_DONE;
-+				}
-+			}
-+		} else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
-+			/* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/
-+			st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
-+		} else {
-+			st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
-+		}
-+		break;
-+
-+	case FIQ_HS_ISOC_TURBO:
-+		if (fiq_fsm_update_hs_isoc(state, n, hcint)) {
-+			/* more transactions to come */
-+			handled = 1;
-+			fiq_print(FIQDBG_INT, state, "HSISO M ");
-+			/* For strided transfers, put ourselves to sleep */
-+			if (st->hs_isoc_info.stride > 1) {
-+				st->uframe_sleeps = st->hs_isoc_info.stride - 1;
-+				st->fsm = FIQ_HS_ISOC_SLEEPING;
-+			} else {
-+				restart = 1;
-+			}
-+		} else {
-+			st->fsm = FIQ_HS_ISOC_DONE;
-+			fiq_print(FIQDBG_INT, state, "HSISO F ");
-+		}
-+		break;
-+
-+	case FIQ_HS_ISOC_ABORTED:
-+		/* This abort is called by the driver rewriting the state mid-transaction
-+		 * which allows the dequeue mechanism to work more effectively.
-+		 */
-+		break;
-+
-+	case FIQ_PER_ISO_OUT_ACTIVE:
-+		if (hcint.b.ack) {
-+			if(fiq_iso_out_advance(state, num_channels, n)) {
-+				/* last OUT transfer */
-+				st->fsm = FIQ_PER_ISO_OUT_LAST;
-+				/*
-+				 * Assuming the periodic FIFO in the dwc core
-+				 * actually does its job properly, we can queue
-+				 * the next ssplit now and in theory, the wire
-+				 * transactions will be in-order.
-+				 */
-+				// No it doesn't. It appears to process requests in host channel order.
-+				//start_next_periodic = 1;
-+			}
-+			handled = 1;
-+			restart = 1;
-+		} else {
-+			/*
-+			 * Isochronous transactions carry on regardless. Log the error
-+			 * and continue.
-+			 */
-+			//explode += 1;
-+			st->nr_errors++;
-+			if(fiq_iso_out_advance(state, num_channels, n)) {
-+				st->fsm = FIQ_PER_ISO_OUT_LAST;
-+				//start_next_periodic = 1;
-+			}
-+			handled = 1;
-+			restart = 1;
-+		}
-+		break;
-+
-+	case FIQ_PER_ISO_OUT_LAST:
-+		if (hcint.b.ack) {
-+			/* All done here */
-+			st->fsm = FIQ_PER_ISO_OUT_DONE;
-+		} else {
-+			st->fsm = FIQ_PER_ISO_OUT_DONE;
-+			st->nr_errors++;
-+		}
-+		start_next_periodic = 1;
-+		break;
-+
-+	case FIQ_PER_SPLIT_TIMEOUT:
-+		/* SOF kicked us because we overran. */
-+		start_next_periodic = 1;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	if (handled) {
-+		FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32);
-+	} else {
-+		/* Copy the regs into the state so the IRQ knows what to do */
-+		st->hcint_copy.d32 = hcint.d32;
-+	}
-+
-+	if (restart) {
-+		/* Restart always implies handled. */
-+		if (restart == 2) {
-+			/* For complete-split INs, the show must go on.
-+			 * Force a channel restart */
-+			fiq_fsm_restart_channel(state, n, 1);
-+		} else {
-+			fiq_fsm_restart_channel(state, n, 0);
-+		}
-+	}
-+	if (start_next_periodic) {
-+		fiq_fsm_start_next_periodic(state, num_channels);
-+	}
-+	if (st->fsm != FIQ_PASSTHROUGH)
-+		fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm);
-+
-+	return handled;
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ
-+ * @state:		pointer to state struct passed from the banked FIQ mode registers.
-+ * @num_channels:	set according to the DWC hardware configuration
-+ * @dma:		pointer to DMA bounce buffers for split transaction slots
-+ *
-+ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode
-+ * inside an EHCI or similar host controller regarding split transactions. The DWC core
-+ * interrupts each and every time a split transaction packet is received or sent successfully.
-+ * This results in either an interrupt storm when everything is working "properly", or
-+ * the interrupt latency of the system in general breaks time-sensitive periodic split
-+ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ
-+ * solves these problems.
-+ *
-+ * Return: void
-+ */
-+void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
-+{
-+	gintsts_data_t gintsts, gintsts_handled;
-+	gintmsk_data_t gintmsk;
-+	//hfnum_data_t hfnum;
-+	haint_data_t haint, haint_handled;
-+	haintmsk_data_t haintmsk;
-+	int kick_irq = 0;
-+
-+	gintsts_handled.d32 = 0;
-+	haint_handled.d32 = 0;
-+
-+	fiq_fsm_spin_lock(&state->lock);
-+	gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
-+	gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
-+	gintsts.d32 &= gintmsk.d32;
-+
-+	if (gintsts.b.sofintr) {
-+		/* For FSM mode, SOF is required to keep the state machine advance for
-+		 * certain stages of the periodic pipeline. It's death to mask this
-+		 * interrupt in that case.
-+		 */
-+
-+		if (!fiq_fsm_do_sof(state, num_channels)) {
-+			/* Kick IRQ once. Queue advancement means that all pending transactions
-+			 * will get serviced when the IRQ finally executes.
-+			 */
-+			if (state->gintmsk_saved.b.sofintr == 1)
-+				kick_irq |= 1;
-+			state->gintmsk_saved.b.sofintr = 0;
-+		}
-+		gintsts_handled.b.sofintr = 1;
-+	}
-+
-+	if (gintsts.b.hcintr) {
-+		int i;
-+		haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);
-+		haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);
-+		haint.d32 &= haintmsk.d32;
-+		haint_handled.d32 = 0;
-+		for (i=0; i<num_channels; i++) {
-+			if (haint.b2.chint & (1 << i)) {
-+				if(!fiq_fsm_do_hcintr(state, num_channels, i)) {
-+					/* HCINT was not handled in FIQ
-+					 * HAINT is level-sensitive, leading to level-sensitive ginststs.b.hcint bit.
-+					 * Mask HAINT(i) but keep top-level hcint unmasked.
-+					 */
-+					state->haintmsk_saved.b2.chint &= ~(1 << i);
-+				} else {
-+					/* do_hcintr cleaned up after itself, but clear haint */
-+					haint_handled.b2.chint |= (1 << i);
-+				}
-+			}
-+		}
-+
-+		if (haint_handled.b2.chint) {
-+			FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32);
-+		}
-+
-+		if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) {
-+			/*
-+			 * This is necessary to avoid multiple retriggers of the MPHI in the case
-+			 * where interrupts are held off and HCINTs start to pile up.
-+			 * Only wake up the IRQ if a new interrupt came in, was not handled and was
-+			 * masked.
-+			 */
-+			haintmsk.d32 &= state->haintmsk_saved.d32;
-+			FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);
-+			kick_irq |= 1;
-+		}
-+		/* Top-Level interrupt - always handled because it's level-sensitive */
-+		gintsts_handled.b.hcintr = 1;
-+	}
-+
-+
-+	/* Clear the bits in the saved register that were not handled but were triggered. */
-+	state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
-+
-+	/* FIQ didn't handle something - mask has changed - write new mask */
-+	if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) {
-+		gintmsk.d32 &= state->gintmsk_saved.d32;
-+		gintmsk.b.sofintr = 1;
-+		FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+//		fiq_print(FIQDBG_INT, state, "KICKGINT");
-+//		fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32);
-+//		fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32);
-+		kick_irq |= 1;
-+	}
-+
-+	if (gintsts_handled.d32) {
-+		/* Only applies to edge-sensitive bits in GINTSTS */
-+		FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
-+	}
-+
-+	/* We got an interrupt, didn't handle it. */
-+	if (kick_irq) {
-+		state->mphi_int_count++;
-+		FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
-+		FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
-+
-+	}
-+	state->fiq_done++;
-+	mb();
-+	fiq_fsm_spin_unlock(&state->lock);
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_nop() - FIQ "lite"
-+ * @state:	pointer to state struct passed from the banked FIQ mode registers.
-+ *
-+ * The "nop" handler does not intervene on any interrupts other than SOF.
-+ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals
-+ * with non-periodic/periodic queues) needs to be kicked.
-+ *
-+ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second.
-+ *
-+ * Return: void
-+ */
-+void notrace dwc_otg_fiq_nop(struct fiq_state *state)
-+{
-+	gintsts_data_t gintsts, gintsts_handled;
-+	gintmsk_data_t gintmsk;
-+	hfnum_data_t hfnum;
-+
-+	fiq_fsm_spin_lock(&state->lock);
-+	hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
-+	gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
-+	gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
-+	gintsts.d32 &= gintmsk.d32;
-+	gintsts_handled.d32 = 0;
-+
-+	if (gintsts.b.sofintr) {
-+		if (!state->kick_np_queues &&
-+				dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) {
-+			/* SOF handled, no work to do, just ACK interrupt */
-+			gintsts_handled.b.sofintr = 1;
-+		} else {
-+			/* Kick IRQ */
-+			state->gintmsk_saved.b.sofintr = 0;
-+		}
-+	}
-+
-+	/* Reset handled interrupts */
-+	if(gintsts_handled.d32) {
-+		FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
-+	}
-+
-+	/* Clear the bits in the saved register that were not handled but were triggered. */
-+	state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
-+
-+	/* We got an interrupt, didn't handle it and want to mask it */
-+	if (~(state->gintmsk_saved.d32)) {
-+		state->mphi_int_count++;
-+		gintmsk.d32 &= state->gintmsk_saved.d32;
-+		FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+		/* Force a clear before another dummy send */
-+		FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
-+		FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
-+		FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
-+
-+	}
-+	state->fiq_done++;
-+	mb();
-+	fiq_fsm_spin_unlock(&state->lock);
-+}
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
-@@ -0,0 +1,372 @@
-+/*
-+ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *	* Redistributions of source code must retain the above copyright
-+ *	  notice, this list of conditions and the following disclaimer.
-+ *	* Redistributions in binary form must reproduce the above copyright
-+ *	  notice, this list of conditions and the following disclaimer in the
-+ *	  documentation and/or other materials provided with the distribution.
-+ *	* Neither the name of Raspberry Pi nor the
-+ *	  names of its contributors may be used to endorse or promote products
-+ *	  derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * This FIQ implements functionality that performs split transactions on
-+ * the dwc_otg hardware without any outside intervention. A split transaction
-+ * is "queued" by nominating a specific host channel to perform the entirety
-+ * of a split transaction. This FIQ will then perform the microframe-precise
-+ * scheduling required in each phase of the transaction until completion.
-+ *
-+ * The FIQ functionality has been surgically implanted into the Synopsys
-+ * vendor-provided driver.
-+ *
-+ */
-+
-+#ifndef DWC_OTG_FIQ_FSM_H_
-+#define DWC_OTG_FIQ_FSM_H_
-+
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_hcd.h"
-+#include <linux/kernel.h>
-+#include <linux/irqflags.h>
-+#include <linux/string.h>
-+#include <asm/barrier.h>
-+
-+#if 0
-+#define FLAME_ON(x)					\
-+do {							\
-+	int gpioreg;                                    \
-+							\
-+	gpioreg = readl(__io_address(0x20200000+0x8));	\
-+	gpioreg &= ~(7 << (x-20)*3);			\
-+	gpioreg |= 0x1 << (x-20)*3;			\
-+	writel(gpioreg, __io_address(0x20200000+0x8));	\
-+							\
-+	writel(1<<x, __io_address(0x20200000+(0x1C)));	\
-+} while (0)
-+
-+#define FLAME_OFF(x)					\
-+do {							\
-+	writel(1<<x, __io_address(0x20200000+(0x28)));	\
-+} while (0)
-+#else
-+#define FLAME_ON(x) do { } while (0)
-+#define FLAME_OFF(X) do { } while (0)
-+#endif
-+
-+/* This is a quick-and-dirty arch-specific register read/write. We know that
-+ * writes to a peripheral on BCM2835 will always arrive in-order, also that
-+ * reads and writes are executed in-order therefore the need for memory barriers
-+ * is obviated if we're only talking to USB.
-+ */
-+#define FIQ_WRITE(_addr_,_data_) (*(volatile unsigned int *) (_addr_) = (_data_))
-+#define FIQ_READ(_addr_) (*(volatile unsigned int *) (_addr_))
-+
-+/* FIQ-ified register definitions. Offsets are from dwc_regs_base. */
-+#define GINTSTS		0x014
-+#define GINTMSK		0x018
-+/* Debug register. Poll the top of the received packets FIFO. */
-+#define GRXSTSR		0x01C
-+#define HFNUM		0x408
-+#define HAINT		0x414
-+#define HAINTMSK	0x418
-+#define HPRT0		0x440
-+
-+/* HC_regs start from an offset of 0x500 */
-+#define HC_START	0x500
-+#define HC_OFFSET	0x020
-+
-+#define HC_DMA		0x514
-+
-+#define HCCHAR		0x00
-+#define HCSPLT		0x04
-+#define HCINT		0x08
-+#define HCINTMSK	0x0C
-+#define HCTSIZ		0x10
-+
-+#define ISOC_XACTPOS_ALL 	0b11
-+#define ISOC_XACTPOS_BEGIN	0b10
-+#define ISOC_XACTPOS_MID	0b00
-+#define ISOC_XACTPOS_END	0b01
-+
-+#define DWC_PID_DATA2	0b01
-+#define DWC_PID_MDATA	0b11
-+#define DWC_PID_DATA1	0b10
-+#define DWC_PID_DATA0	0b00
-+
-+typedef struct {
-+	volatile void* base;
-+	volatile void* ctrl;
-+	volatile void* outdda;
-+	volatile void* outddb;
-+	volatile void* intstat;
-+} mphi_regs_t;
-+
-+enum fiq_debug_level {
-+	FIQDBG_SCHED = (1 << 0),
-+	FIQDBG_INT   = (1 << 1),
-+	FIQDBG_ERR   = (1 << 2),
-+	FIQDBG_PORTHUB = (1 << 3),
-+};
-+
-+typedef struct {
-+	union {
-+		uint32_t slock;
-+		struct _tickets {
-+			uint16_t owner;
-+			uint16_t next;
-+		} tickets;
-+	};
-+} fiq_lock_t;
-+
-+struct fiq_state;
-+
-+extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);
-+#if 0
-+#define fiq_print _fiq_print
-+#else
-+#define fiq_print(x, y, ...)
-+#endif
-+
-+extern bool fiq_enable, fiq_fsm_enable;
-+extern ushort nak_holdoff;
-+
-+/**
-+ * enum fiq_fsm_state - The FIQ FSM states.
-+ *
-+ * This is the "core" of the FIQ FSM. Broadly, the FSM states follow the
-+ * USB2.0 specification for host responses to various transaction states.
-+ * There are modifications to this host state machine because of a variety of
-+ * quirks and limitations in the dwc_otg hardware.
-+ *
-+ * The fsm state is also used to communicate back to the driver on completion of
-+ * a split transaction. The end states are used in conjunction with the interrupts
-+ * raised by the final transaction.
-+ */
-+enum fiq_fsm_state {
-+	/* FIQ isn't enabled for this host channel */
-+	FIQ_PASSTHROUGH = 0,
-+	/* For the first interrupt received for this channel,
-+	 * the FIQ has to ack any interrupts indicating success. */
-+	FIQ_PASSTHROUGH_ERRORSTATE = 31,
-+	/* Nonperiodic state groups */
-+	FIQ_NP_SSPLIT_STARTED = 1,
-+	FIQ_NP_SSPLIT_RETRY = 2,
-+	/* TT contention - working around hub bugs */
-+	FIQ_NP_SSPLIT_PENDING = 33,
-+	FIQ_NP_OUT_CSPLIT_RETRY = 3,
-+	FIQ_NP_IN_CSPLIT_RETRY = 4,
-+	FIQ_NP_SPLIT_DONE = 5,
-+	FIQ_NP_SPLIT_LS_ABORTED = 6,
-+	/* This differentiates a HS transaction error from a LS one
-+	 * (handling the hub state is different) */
-+	FIQ_NP_SPLIT_HS_ABORTED = 7,
-+
-+	/* Periodic state groups */
-+	/* Periodic transactions are either started directly by the IRQ handler
-+	 * or deferred if the TT is already in use.
-+	 */
-+	FIQ_PER_SSPLIT_QUEUED = 8,
-+	FIQ_PER_SSPLIT_STARTED = 9,
-+	FIQ_PER_SSPLIT_LAST = 10,
-+
-+
-+	FIQ_PER_ISO_OUT_PENDING = 11,
-+	FIQ_PER_ISO_OUT_ACTIVE = 12,
-+	FIQ_PER_ISO_OUT_LAST = 13,
-+	FIQ_PER_ISO_OUT_DONE = 27,
-+
-+	FIQ_PER_CSPLIT_WAIT = 14,
-+	FIQ_PER_CSPLIT_NYET1 = 15,
-+	FIQ_PER_CSPLIT_BROKEN_NYET1 = 28,
-+	FIQ_PER_CSPLIT_NYET_FAFF = 29,
-+	/* For multiple CSPLITs (large isoc IN, or delayed interrupt) */
-+	FIQ_PER_CSPLIT_POLL = 16,
-+	/* The last CSPLIT for a transaction has been issued, differentiates
-+	 * for the state machine to queue the next packet.
-+	 */
-+	FIQ_PER_CSPLIT_LAST = 17,
-+
-+	FIQ_PER_SPLIT_DONE = 18,
-+	FIQ_PER_SPLIT_LS_ABORTED = 19,
-+	FIQ_PER_SPLIT_HS_ABORTED = 20,
-+	FIQ_PER_SPLIT_NYET_ABORTED = 21,
-+	/* Frame rollover has occurred without the transaction finishing. */
-+	FIQ_PER_SPLIT_TIMEOUT = 22,
-+
-+	/* FIQ-accelerated HS Isochronous state groups */
-+	FIQ_HS_ISOC_TURBO = 23,
-+	/* For interval > 1, SOF wakes up the isochronous FSM */
-+	FIQ_HS_ISOC_SLEEPING = 24,
-+	FIQ_HS_ISOC_DONE = 25,
-+	FIQ_HS_ISOC_ABORTED = 26,
-+	FIQ_DEQUEUE_ISSUED = 30,
-+	FIQ_TEST = 32,
-+};
-+
-+struct fiq_stack {
-+	int magic1;
-+	uint8_t stack[2048];
-+	int magic2;
-+};
-+
-+
-+/**
-+ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel)
-+ * @index:	Number of slots reported used for IN transactions / number of slots
-+ *			transmitted for an OUT transaction
-+ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused)
-+ *
-+ * Split transaction transfers can have variable length depending on other bus
-+ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore
-+ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers
-+ * can happen per-frame.
-+ */
-+struct fiq_dma_info {
-+	u8 index;
-+	u8 slot_len[6];
-+};
-+
-+struct __attribute__((packed)) fiq_split_dma_slot {
-+	u8 buf[188];
-+};
-+
-+struct fiq_dma_channel {
-+	struct __attribute__((packed)) fiq_split_dma_slot index[6];
-+};
-+
-+struct fiq_dma_blob {
-+	struct __attribute__((packed)) fiq_dma_channel channel[0];
-+};
-+
-+/**
-+ * struct fiq_hs_isoc_info - USB2.0 isochronous data
-+ * @iso_frame:	Pointer to the array of OTG URB iso_frame_descs.
-+ * @nrframes:	Total length of iso_frame_desc array
-+ * @index:	Current index (FIQ-maintained)
-+ * @stride:	Interval in uframes between HS isoc transactions
-+ */
-+struct fiq_hs_isoc_info {
-+	struct dwc_otg_hcd_iso_packet_desc *iso_desc;
-+	unsigned int nrframes;
-+	unsigned int index;
-+	unsigned int stride;
-+};
-+
-+/**
-+ * struct fiq_channel_state - FIQ state machine storage
-+ * @fsm:	Current state of the channel as understood by the FIQ
-+ * @nr_errors:	Number of transaction errors on this split-transaction
-+ * @hub_addr:   SSPLIT/CSPLIT destination hub
-+ * @port_addr:  SSPLIT/CSPLIT destination port - always 1 if single TT hub
-+ * @nrpackets:  For isoc OUT, the number of split-OUT packets to transmit. For
-+ * 		split-IN, number of CSPLIT data packets that were received.
-+ * @hcchar_copy:
-+ * @hcsplt_copy:
-+ * @hcintmsk_copy:
-+ * @hctsiz_copy:	Copies of the host channel registers.
-+ * 			For use as scratch, or for returning state.
-+ *
-+ * The fiq_channel_state is state storage between interrupts for a host channel. The
-+ * FSM state is stored here. Members of this structure must only be set up by the
-+ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ
-+ * has updated the state to either a COMPLETE state group or ABORT state group.
-+ */
-+
-+struct fiq_channel_state {
-+	enum fiq_fsm_state fsm;
-+	unsigned int nr_errors;
-+	unsigned int hub_addr;
-+	unsigned int port_addr;
-+	/* Hardware bug workaround: sometimes channel halt interrupts are
-+	 * delayed until the next SOF. Keep track of when we expected to get interrupted. */
-+	unsigned int expected_uframe;
-+	/* number of uframes remaining (for interval > 1 HS isoc transfers) before next transfer */
-+	unsigned int uframe_sleeps;
-+	/* in/out for communicating number of dma buffers used, or number of ISOC to do */
-+	unsigned int nrpackets;
-+	struct fiq_dma_info dma_info;
-+	struct fiq_hs_isoc_info hs_isoc_info;
-+	/* Copies of HC registers - in/out communication from/to IRQ handler
-+	 * and for ease of channel setup. A bit of mungeing is performed - for
-+	 * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint.
-+	 */
-+	hcchar_data_t hcchar_copy;
-+	hcsplt_data_t hcsplt_copy;
-+	hcint_data_t hcint_copy;
-+	hcintmsk_data_t hcintmsk_copy;
-+	hctsiz_data_t hctsiz_copy;
-+	hcdma_data_t hcdma_copy;
-+};
-+
-+/**
-+ * struct fiq_state - top-level FIQ state machine storage
-+ * @mphi_regs:		virtual address of the MPHI peripheral register file
-+ * @dwc_regs_base:	virtual address of the base of the DWC core register file
-+ * @dma_base:		physical address for the base of the DMA bounce buffers
-+ * @dummy_send:		Scratch area for sending a fake message to the MPHI peripheral
-+ * @gintmsk_saved:	Top-level mask of interrupts that the FIQ has not handled.
-+ * 			Used for determining which interrupts fired to set off the IRQ handler.
-+ * @haintmsk_saved:	Mask of interrupts from host channels that the FIQ did not handle internally.
-+ * @np_count:		Non-periodic transactions in the active queue
-+ * @np_sent:		Count of non-periodic transactions that have completed
-+ * @next_sched_frame:	For periodic transactions handled by the driver's SOF-driven queuing mechanism,
-+ * 			this is the next frame on which a SOF interrupt is required. Used to hold off
-+ * 			passing SOF through to the driver until necessary.
-+ * @channel[n]:		Per-channel FIQ state. Allocated during init depending on the number of host
-+ * 			channels configured into the core logic.
-+ *
-+ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub.
-+ * It contains top-level state information.
-+ */
-+struct fiq_state {
-+	fiq_lock_t lock;
-+	mphi_regs_t mphi_regs;
-+	void *dwc_regs_base;
-+	dma_addr_t dma_base;
-+	struct fiq_dma_blob *fiq_dmab;
-+	void *dummy_send;
-+	gintmsk_data_t gintmsk_saved;
-+	haintmsk_data_t haintmsk_saved;
-+	int mphi_int_count;
-+	unsigned int fiq_done;
-+	unsigned int kick_np_queues;
-+	unsigned int next_sched_frame;
-+#ifdef FIQ_DEBUG
-+	char * buffer;
-+	unsigned int bufsiz;
-+#endif
-+	struct fiq_channel_state channel[0];
-+};
-+
-+extern void fiq_fsm_spin_lock(fiq_lock_t *lock);
-+
-+extern void fiq_fsm_spin_unlock(fiq_lock_t *lock);
-+
-+extern int fiq_fsm_too_late(struct fiq_state *st, int n);
-+
-+extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n);
-+
-+extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels);
-+
-+extern void dwc_otg_fiq_nop(struct fiq_state *state);
-+
-+#endif /* DWC_OTG_FIQ_FSM_H_ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
-@@ -0,0 +1,80 @@
-+/*
-+ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ
-+ *
-+ * Copyright (c) 2013 Raspberry Pi Foundation
-+ *
-+ * Author: Jonathan Bell <jonathan@raspberrypi.org>
-+ * All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *	* Redistributions of source code must retain the above copyright
-+ *	  notice, this list of conditions and the following disclaimer.
-+ *	* Redistributions in binary form must reproduce the above copyright
-+ *	  notice, this list of conditions and the following disclaimer in the
-+ *	  documentation and/or other materials provided with the distribution.
-+ *	* Neither the name of Raspberry Pi nor the
-+ *	  names of its contributors may be used to endorse or promote products
-+ *	  derived from this software without specific prior written permission.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+
-+#include <asm/assembler.h>
-+#include <linux/linkage.h>
-+
-+
-+.text
-+
-+.global _dwc_otg_fiq_stub_end;
-+
-+/**
-+  * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow
-+  * a C-style function call with arguments from the FIQ banked registers.
-+  * r0 = &hcd->fiq_state
-+  * r1 = &hcd->num_channels
-+  * r2 = &hcd->dma_buffers
-+  * Tramples: r0, r1, r2, r4, fp, ip
-+  */
-+
-+ENTRY(_dwc_otg_fiq_stub)
-+	/* Stash unbanked regs - SP will have been set up for us */
-+	mov ip, sp;
-+	stmdb sp!, {r0-r12, lr};
-+#ifdef FIQ_DEBUG
-+	// Cycle profiling - read cycle counter at start
-+	mrc p15, 0, r5, c15, c12, 1;
-+#endif
-+	/* r11 = fp, don't trample it */
-+	mov r4, fp;
-+	/* set EABI frame size */
-+	sub fp, ip, #512;
-+
-+	/* for fiq NOP mode - just need state */
-+	mov r0, r8;
-+	/* r9 = num_channels */
-+	mov r1, r9;
-+	/* r10 = struct *dma_bufs */
-+//	mov r2, r10;
-+
-+	/* r4 = &fiq_c_function */
-+	blx r4;
-+#ifdef FIQ_DEBUG
-+	mrc p15, 0, r4, c15, c12, 1;
-+	subs r5, r5, r4;
-+	// r5 is now the cycle count time for executing the FIQ. Store it somewhere?
-+#endif
-+	ldmia sp!, {r0-r12, lr};
-+	subs pc, lr, #4;
-+_dwc_otg_fiq_stub_end:
-+END(_dwc_otg_fiq_stub)
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
-@@ -0,0 +1,4283 @@
-+
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
-+ * $Revision: #104 $
-+ * $Date: 2011/10/24 $
-+ * $Change: 1871159 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/** @file
-+ * This file implements HCD Core. All code in this file is portable and doesn't
-+ * use any OS specific functions.
-+ * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
-+ * header file.
-+ */
-+
-+#include <linux/usb.h>
-+#include <linux/usb/hcd.h>
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+#include "dwc_otg_fiq_fsm.h"
-+
-+extern bool microframe_schedule;
-+extern uint16_t fiq_fsm_mask, nak_holdoff;
-+
-+//#define DEBUG_HOST_CHANNELS
-+#ifdef DEBUG_HOST_CHANNELS
-+static int last_sel_trans_num_per_scheduled = 0;
-+static int last_sel_trans_num_nonper_scheduled = 0;
-+static int last_sel_trans_num_avail_hc_at_start = 0;
-+static int last_sel_trans_num_avail_hc_at_end = 0;
-+#endif /* DEBUG_HOST_CHANNELS */
-+
-+
-+dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
-+{
-+	return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
-+}
-+
-+/**
-+ * Connection timeout function.  An OTG host is required to display a
-+ * message if the device does not connect within 10 seconds.
-+ */
-+void dwc_otg_hcd_connect_timeout(void *ptr)
-+{
-+	DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
-+	DWC_PRINTF("Connect Timeout\n");
-+	__DWC_ERROR("Device Not Connected/Responding\n");
-+}
-+
-+#if defined(DEBUG)
-+static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	if (qh->channel != NULL) {
-+		dwc_hc_t *hc = qh->channel;
-+		dwc_list_link_t *item;
-+		dwc_otg_qh_t *qh_item;
-+		int num_channels = hcd->core_if->core_params->host_channels;
-+		int i;
-+
-+		dwc_otg_hc_regs_t *hc_regs;
-+		hcchar_data_t hcchar;
-+		hcsplt_data_t hcsplt;
-+		hctsiz_data_t hctsiz;
-+		uint32_t hcdma;
-+
-+		hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+		hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+		hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+		hcdma = DWC_READ_REG32(&hc_regs->hcdma);
-+
-+		DWC_PRINTF("  Assigned to channel %p:\n", hc);
-+		DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
-+			   hcsplt.d32);
-+		DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
-+			   hcdma);
-+		DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
-+			   hc->dev_addr, hc->ep_num, hc->ep_is_in);
-+		DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
-+		DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
-+		DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
-+		DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
-+		DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
-+		DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
-+		DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
-+		DWC_PRINTF("    qh: %p\n", hc->qh);
-+		DWC_PRINTF("  NP inactive sched:\n");
-+		DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
-+			qh_item =
-+			    DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+			DWC_PRINTF("    %p\n", qh_item);
-+		}
-+		DWC_PRINTF("  NP active sched:\n");
-+		DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
-+			qh_item =
-+			    DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+			DWC_PRINTF("    %p\n", qh_item);
-+		}
-+		DWC_PRINTF("  Channels: \n");
-+		for (i = 0; i < num_channels; i++) {
-+			dwc_hc_t *hc = hcd->hc_ptr_array[i];
-+			DWC_PRINTF("    %2d: %p\n", i, hc);
-+		}
-+	}
-+}
-+#else
-+#define dump_channel_info(hcd, qh)
-+#endif /* DEBUG */
-+
-+/**
-+ * Work queue function for starting the HCD when A-Cable is connected.
-+ * The hcd_start() must be called in a process context.
-+ */
-+static void hcd_start_func(void *_vp)
-+{
-+	dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
-+	if (hcd) {
-+		hcd->fops->start(hcd);
-+	}
-+}
-+
-+static void del_xfer_timers(dwc_otg_hcd_t * hcd)
-+{
-+#ifdef DEBUG
-+	int i;
-+	int num_channels = hcd->core_if->core_params->host_channels;
-+	for (i = 0; i < num_channels; i++) {
-+		DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
-+	}
-+#endif
-+}
-+
-+static void del_timers(dwc_otg_hcd_t * hcd)
-+{
-+	del_xfer_timers(hcd);
-+	DWC_TIMER_CANCEL(hcd->conn_timer);
-+}
-+
-+/**
-+ * Processes all the URBs in a single list of QHs. Completes them with
-+ * -ESHUTDOWN and frees the QTD.
-+ */
-+static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
-+{
-+	dwc_list_link_t *qh_item, *qh_tmp;
-+	dwc_otg_qh_t *qh;
-+	dwc_otg_qtd_t *qtd, *qtd_tmp;
-+
-+	DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) {
-+		qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
-+		DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
-+					 &qh->qtd_list, qtd_list_entry) {
-+			qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+			if (qtd->urb != NULL) {
-+				hcd->fops->complete(hcd, qtd->urb->priv,
-+						    qtd->urb, -DWC_E_SHUTDOWN);
-+				dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+			}
-+
-+		}
-+		if(qh->channel) {
-+			/* Using hcchar.chen == 1 is not a reliable test.
-+			 * It is possible that the channel has already halted
-+			 * but not yet been through the IRQ handler.
-+			 */
-+			if (fiq_fsm_enable && (hcd->fiq_state->channel[qh->channel->hc_num].fsm != FIQ_PASSTHROUGH)) {
-+				qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
-+				qh->channel->halt_pending = 1;
-+			} else {
-+				dwc_otg_hc_halt(hcd->core_if, qh->channel,
-+						DWC_OTG_HC_XFER_URB_DEQUEUE);
-+			}
-+			qh->channel = NULL;
-+		}
-+		dwc_otg_hcd_qh_remove(hcd, qh);
-+	}
-+}
-+
-+/**
-+ * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic
-+ * and periodic schedules. The QTD associated with each URB is removed from
-+ * the schedule and freed. This function may be called when a disconnect is
-+ * detected or when the HCD is being stopped.
-+ */
-+static void kill_all_urbs(dwc_otg_hcd_t * hcd)
-+{
-+	kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
-+	kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
-+	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
-+	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
-+	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
-+	kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
-+}
-+
-+/**
-+ * Start the connection timer.  An OTG host is required to display a
-+ * message if the device does not connect within 10 seconds.  The
-+ * timer is deleted if a port connect interrupt occurs before the
-+ * timer expires.
-+ */
-+static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
-+{
-+	DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
-+}
-+
-+/**
-+ * HCD Callback function for disconnect of the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_session_start_cb(void *p)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd;
-+	DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
-+	dwc_otg_hcd = p;
-+	dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
-+	return 1;
-+}
-+
-+/**
-+ * HCD Callback function for starting the HCD when A-Cable is
-+ * connected.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_start_cb(void *p)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = p;
-+	dwc_otg_core_if_t *core_if;
-+	hprt0_data_t hprt0;
-+
-+	core_if = dwc_otg_hcd->core_if;
-+
-+	if (core_if->op_state == B_HOST) {
-+		/*
-+		 * Reset the port.  During a HNP mode switch the reset
-+		 * needs to occur within 1ms and have a duration of at
-+		 * least 50ms.
-+		 */
-+		hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+		hprt0.b.prtrst = 1;
-+		DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+	}
-+	DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
-+				   hcd_start_func, dwc_otg_hcd, 50,
-+				   "start hcd");
-+
-+	return 1;
-+}
-+
-+/**
-+ * HCD Callback function for disconnect of the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_disconnect_cb(void *p)
-+{
-+	gintsts_data_t intr;
-+	dwc_otg_hcd_t *dwc_otg_hcd = p;
-+
-+	DWC_SPINLOCK(dwc_otg_hcd->lock);
-+	/*
-+	 * Set status flags for the hub driver.
-+	 */
-+	dwc_otg_hcd->flags.b.port_connect_status_change = 1;
-+	dwc_otg_hcd->flags.b.port_connect_status = 0;
-+	if(fiq_enable) {
-+		local_fiq_disable();
-+		fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+	}
-+	/*
-+	 * Shutdown any transfers in process by clearing the Tx FIFO Empty
-+	 * interrupt mask and status bits and disabling subsequent host
-+	 * channel interrupts.
-+	 */
-+	intr.d32 = 0;
-+	intr.b.nptxfempty = 1;
-+	intr.b.ptxfempty = 1;
-+	intr.b.hcintr = 1;
-+	DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
-+			 intr.d32, 0);
-+	DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
-+			 intr.d32, 0);
-+
-+	del_timers(dwc_otg_hcd);
-+
-+	/*
-+	 * Turn off the vbus power only if the core has transitioned to device
-+	 * mode. If still in host mode, need to keep power on to detect a
-+	 * reconnection.
-+	 */
-+	if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
-+		if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
-+			hprt0_data_t hprt0 = {.d32 = 0 };
-+			DWC_PRINTF("Disconnect: PortPower off\n");
-+			hprt0.b.prtpwr = 0;
-+			DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
-+					hprt0.d32);
-+		}
-+
-+		dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
-+	}
-+
-+	/* Respond with an error status to all URBs in the schedule. */
-+	kill_all_urbs(dwc_otg_hcd);
-+
-+	if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
-+		/* Clean up any host channels that were in use. */
-+		int num_channels;
-+		int i;
-+		dwc_hc_t *channel;
-+		dwc_otg_hc_regs_t *hc_regs;
-+		hcchar_data_t hcchar;
-+
-+		num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
-+
-+		if (!dwc_otg_hcd->core_if->dma_enable) {
-+			/* Flush out any channel requests in slave mode. */
-+			for (i = 0; i < num_channels; i++) {
-+				channel = dwc_otg_hcd->hc_ptr_array[i];
-+				if (DWC_CIRCLEQ_EMPTY_ENTRY
-+				    (channel, hc_list_entry)) {
-+					hc_regs =
-+					    dwc_otg_hcd->core_if->
-+					    host_if->hc_regs[i];
-+					hcchar.d32 =
-+					    DWC_READ_REG32(&hc_regs->hcchar);
-+					if (hcchar.b.chen) {
-+						hcchar.b.chen = 0;
-+						hcchar.b.chdis = 1;
-+						hcchar.b.epdir = 0;
-+						DWC_WRITE_REG32
-+						    (&hc_regs->hcchar,
-+						     hcchar.d32);
-+					}
-+				}
-+			}
-+		}
-+
-+		if(fiq_fsm_enable) {
-+			for(i=0; i < 128; i++) {
-+				dwc_otg_hcd->hub_port[i] = 0;
-+			}
-+		}
-+	}
-+
-+	if(fiq_enable) {
-+		fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+		local_fiq_enable();
-+	}
-+
-+	if (dwc_otg_hcd->fops->disconnect) {
-+		dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
-+	}
-+
-+	DWC_SPINUNLOCK(dwc_otg_hcd->lock);
-+	return 1;
-+}
-+
-+/**
-+ * HCD Callback function for stopping the HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int32_t dwc_otg_hcd_stop_cb(void *p)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = p;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
-+	dwc_otg_hcd_stop(dwc_otg_hcd);
-+	return 1;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * HCD Callback function for sleep of HCD.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int dwc_otg_hcd_sleep_cb(void *p)
-+{
-+	dwc_otg_hcd_t *hcd = p;
-+
-+	dwc_otg_hcd_free_hc_from_lpm(hcd);
-+
-+	return 0;
-+}
-+#endif
-+
-+
-+/**
-+ * HCD Callback function for Remote Wakeup.
-+ *
-+ * @param p void pointer to the <code>struct usb_hcd</code>
-+ */
-+static int dwc_otg_hcd_rem_wakeup_cb(void *p)
-+{
-+	dwc_otg_hcd_t *hcd = p;
-+
-+	if (hcd->core_if->lx_state == DWC_OTG_L2) {
-+		hcd->flags.b.port_suspend_change = 1;
-+	}
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	else {
-+		hcd->flags.b.port_l1_change = 1;
-+	}
-+#endif
-+	return 0;
-+}
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ */
-+void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
-+{
-+	hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
-+
-+	/*
-+	 * The root hub should be disconnected before this function is called.
-+	 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
-+	 * and the QH lists (via ..._hcd_endpoint_disable).
-+	 */
-+
-+	/* Turn off all host-specific interrupts. */
-+	dwc_otg_disable_host_interrupts(hcd->core_if);
-+
-+	/* Turn off the vbus power */
-+	DWC_PRINTF("PortPower off\n");
-+	hprt0.b.prtpwr = 0;
-+	DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
-+	dwc_mdelay(1);
-+}
-+
-+int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
-+			    dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
-+			    int atomic_alloc)
-+{
-+	int retval = 0;
-+	uint8_t needs_scheduling = 0;
-+	dwc_otg_transaction_type_e tr_type;
-+	dwc_otg_qtd_t *qtd;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	hprt0_data_t hprt0 = { .d32 = 0 };
-+
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+	if (NULL == hcd->core_if) {
-+		DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
-+		/* No longer connected. */
-+		return -DWC_E_INVALID;
-+	}
-+#endif
-+	if (!hcd->flags.b.port_connect_status) {
-+		/* No longer connected. */
-+		DWC_ERROR("Not connected\n");
-+		return -DWC_E_NO_DEVICE;
-+	}
-+
-+	/* Some core configurations cannot support LS traffic on a FS root port */
-+	if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) &&
-+		(hcd->core_if->hwcfg2.b.fs_phy_type == 1) &&
-+		(hcd->core_if->hwcfg2.b.hs_phy_type == 1)) {
-+			hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
-+			if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
-+				return -DWC_E_NO_DEVICE;
-+			}
-+	}
-+
-+	qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
-+	if (qtd == NULL) {
-+		DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
-+		return -DWC_E_NO_MEMORY;
-+	}
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+	if (qtd->urb == NULL) {
-+		DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
-+		return -DWC_E_NO_MEMORY;
-+	}
-+	if (qtd->urb->priv == NULL) {
-+		DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
-+		return -DWC_E_NO_MEMORY;
-+	}
-+#endif
-+	intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
-+	if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1;
-+	if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP))
-+		/* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
-+		needs_scheduling = 0;
-+
-+	retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
-+            // creates a new queue in ep_handle if it doesn't exist already
-+	if (retval < 0) {
-+		DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
-+			  "Error status %d\n", retval);
-+		dwc_otg_hcd_qtd_free(qtd);
-+		return retval;
-+	}
-+
-+	if(needs_scheduling) {
-+		tr_type = dwc_otg_hcd_select_transactions(hcd);
-+		if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+			dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+		}
-+	}
-+	return retval;
-+}
-+
-+int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
-+			    dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+	dwc_otg_qh_t *qh;
-+	dwc_otg_qtd_t *urb_qtd;
-+	BUG_ON(!hcd);
-+	BUG_ON(!dwc_otg_urb);
-+
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+
-+	if (hcd == NULL) {
-+		DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
-+		return -DWC_E_INVALID;
-+	}
-+	if (dwc_otg_urb == NULL) {
-+		DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
-+		return -DWC_E_INVALID;
-+	}
-+	if (dwc_otg_urb->qtd == NULL) {
-+		DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
-+		return -DWC_E_INVALID;
-+	}
-+	urb_qtd = dwc_otg_urb->qtd;
-+	BUG_ON(!urb_qtd);
-+	if (urb_qtd->qh == NULL) {
-+		DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
-+		return -DWC_E_INVALID;
-+	}
-+#else
-+	urb_qtd = dwc_otg_urb->qtd;
-+	BUG_ON(!urb_qtd);
-+#endif
-+	qh = urb_qtd->qh;
-+	BUG_ON(!qh);
-+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+		if (urb_qtd->in_process) {
-+			dump_channel_info(hcd, qh);
-+		}
-+	}
-+#ifdef DEBUG /* integrity checks (Broadcom) */
-+	if (hcd->core_if == NULL) {
-+		DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
-+		return -DWC_E_INVALID;
-+	}
-+#endif
-+	if (urb_qtd->in_process && qh->channel) {
-+		/* The QTD is in process (it has been assigned to a channel). */
-+		if (hcd->flags.b.port_connect_status) {
-+			int n = qh->channel->hc_num;
-+			/*
-+			 * If still connected (i.e. in host mode), halt the
-+			 * channel so it can be used for other transfers. If
-+			 * no longer connected, the host registers can't be
-+			 * written to halt the channel since the core is in
-+			 * device mode.
-+			 */
-+			/* In FIQ FSM mode, we need to shut down carefully.
-+			 * The FIQ may attempt to restart a disabled channel */
-+			if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {
-+				qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
-+				qh->channel->halt_pending = 1;
-+				//hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED;
-+			} else {
-+				dwc_otg_hc_halt(hcd->core_if, qh->channel,
-+						DWC_OTG_HC_XFER_URB_DEQUEUE);
-+			}
-+		}
-+	}
-+
-+	/*
-+	 * Free the QTD and clean up the associated QH. Leave the QH in the
-+	 * schedule if it has any remaining QTDs.
-+	 */
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
-+                    "delete %sQueue handler\n",
-+                    hcd->core_if->dma_desc_enable?"DMA ":"");
-+	if (!hcd->core_if->dma_desc_enable) {
-+		uint8_t b = urb_qtd->in_process;
-+		if (nak_holdoff && qh->do_split && dwc_qh_is_non_per(qh))
-+			qh->nak_frame = 0xFFFF;
-+		dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
-+		if (b) {
-+			dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
-+			qh->channel = NULL;
-+		} else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+			dwc_otg_hcd_qh_remove(hcd, qh);
-+		}
-+	} else {
-+		dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
-+	}
-+	return 0;
-+}
-+
-+int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
-+				 int retry)
-+{
-+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+	int retval = 0;
-+	dwc_irqflags_t flags;
-+
-+	if (retry < 0) {
-+		retval = -DWC_E_INVALID;
-+		goto done;
-+	}
-+
-+	if (!qh) {
-+		retval = -DWC_E_INVALID;
-+		goto done;
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+
-+	while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
-+		DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+		retry--;
-+		dwc_msleep(5);
-+		DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+	}
-+
-+	dwc_otg_hcd_qh_remove(hcd, qh);
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+	/*
-+	 * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
-+	 * and qh_free to prevent stack dump on DWC_DMA_FREE() with
-+	 * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
-+	 * and dwc_otg_hcd_frame_list_alloc().
-+	 */
-+	dwc_otg_hcd_qh_free(hcd, qh);
-+
-+done:
-+	return retval;
-+}
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+	int retval = 0;
-+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+	if (!qh)
-+		return -DWC_E_INVALID;
-+
-+	qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+	return retval;
-+}
-+#endif
-+
-+/**
-+ * HCD Callback structure for handling mode switching.
-+ */
-+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
-+	.start = dwc_otg_hcd_start_cb,
-+	.stop = dwc_otg_hcd_stop_cb,
-+	.disconnect = dwc_otg_hcd_disconnect_cb,
-+	.session_start = dwc_otg_hcd_session_start_cb,
-+	.resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	.sleep = dwc_otg_hcd_sleep_cb,
-+#endif
-+	.p = 0,
-+};
-+
-+/**
-+ * Reset tasklet function
-+ */
-+static void reset_tasklet_func(void *data)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
-+	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+	hprt0_data_t hprt0;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
-+
-+	hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+	hprt0.b.prtrst = 1;
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+	dwc_mdelay(60);
-+
-+	hprt0.b.prtrst = 0;
-+	DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+	dwc_otg_hcd->flags.b.port_reset_change = 1;
-+}
-+
-+static void completion_tasklet_func(void *ptr)
-+{
-+	dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr;
-+	struct urb *urb;
-+	urb_tq_entry_t *item;
-+	dwc_irqflags_t flags;
-+
-+	/* This could just be spin_lock_irq */
-+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+	while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) {
-+		item = DWC_TAILQ_FIRST(&hcd->completed_urb_list);
-+		urb = item->urb;
-+		DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item,
-+				urb_tq_entries);
-+		DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+		DWC_FREE(item);
-+
-+		usb_hcd_giveback_urb(hcd->priv, urb, urb->status);
-+
-+
-+		DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+	}
-+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+	return;
-+}
-+
-+static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
-+{
-+	dwc_list_link_t *item;
-+	dwc_otg_qh_t *qh;
-+	dwc_irqflags_t flags;
-+
-+	if (!qh_list->next) {
-+		/* The list hasn't been initialized yet. */
-+		return;
-+	}
-+	/*
-+	 * Hold spinlock here. Not needed in that case if bellow
-+	 * function is being called from ISR
-+	 */
-+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+	/* Ensure there are no QTDs or URBs left. */
-+	kill_urbs_in_qh_list(hcd, qh_list);
-+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+
-+	DWC_LIST_FOREACH(item, qh_list) {
-+		qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
-+		dwc_otg_hcd_qh_remove_and_free(hcd, qh);
-+	}
-+}
-+
-+/**
-+ * Exit from Hibernation if Host did not detect SRP from connected SRP capable
-+ * Device during SRP time by host power up.
-+ */
-+void dwc_otg_hcd_power_up(void *ptr)
-+{
-+	gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+	dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+
-+	DWC_PRINTF("%s called\n", __FUNCTION__);
-+
-+	if (!core_if->hibernation_suspend) {
-+		DWC_PRINTF("Already exited from Hibernation\n");
-+		return;
-+	}
-+
-+	/* Switch on the voltage to the core */
-+	gpwrdn.b.pwrdnswtch = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Reset the core */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Disable power clamps */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnclmp = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	/* Remove reset the core signal */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pwrdnrstn = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
-+	dwc_udelay(10);
-+
-+	/* Disable PMU interrupt */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuintsel = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	core_if->hibernation_suspend = 0;
-+
-+	/* Disable PMU */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.pmuactv = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+	dwc_udelay(10);
-+
-+	/* Enable VBUS */
-+	gpwrdn.d32 = 0;
-+	gpwrdn.b.dis_vbus = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
-+
-+	core_if->op_state = A_HOST;
-+	dwc_otg_core_init(core_if);
-+	dwc_otg_enable_global_interrupts(core_if);
-+	cil_hcd_start(core_if);
-+}
-+
-+void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)
-+{
-+	struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+	struct fiq_dma_blob *blob = hcd->fiq_dmab;
-+	int i;
-+
-+	st->fsm = FIQ_PASSTHROUGH;
-+	st->hcchar_copy.d32 = 0;
-+	st->hcsplt_copy.d32 = 0;
-+	st->hcint_copy.d32 = 0;
-+	st->hcintmsk_copy.d32 = 0;
-+	st->hctsiz_copy.d32 = 0;
-+	st->hcdma_copy.d32 = 0;
-+	st->nr_errors = 0;
-+	st->hub_addr = 0;
-+	st->port_addr = 0;
-+	st->expected_uframe = 0;
-+	st->nrpackets = 0;
-+	st->dma_info.index = 0;
-+	for (i = 0; i < 6; i++)
-+		st->dma_info.slot_len[i] = 255;
-+	st->hs_isoc_info.index = 0;
-+	st->hs_isoc_info.iso_desc = NULL;
-+	st->hs_isoc_info.nrframes = 0;
-+
-+	DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);
-+}
-+
-+/**
-+ * Frees secondary storage associated with the dwc_otg_hcd structure contained
-+ * in the struct usb_hcd field.
-+ */
-+static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	struct device *dev = dwc_otg_hcd_to_dev(dwc_otg_hcd);
-+	int i;
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
-+
-+	del_timers(dwc_otg_hcd);
-+
-+	/* Free memory for QH/QTD lists */
-+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
-+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
-+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
-+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
-+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
-+	qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
-+
-+	/* Free memory for the host channels. */
-+	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+		dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
-+
-+#ifdef DEBUG
-+		if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
-+			DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
-+		}
-+#endif
-+		if (hc != NULL) {
-+			DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
-+				    i, hc);
-+			DWC_FREE(hc);
-+		}
-+	}
-+
-+	if (dwc_otg_hcd->core_if->dma_enable) {
-+		if (dwc_otg_hcd->status_buf_dma) {
-+			DWC_DMA_FREE(dev, DWC_OTG_HCD_STATUS_BUF_SIZE,
-+				     dwc_otg_hcd->status_buf,
-+				     dwc_otg_hcd->status_buf_dma);
-+		}
-+	} else if (dwc_otg_hcd->status_buf != NULL) {
-+		DWC_FREE(dwc_otg_hcd->status_buf);
-+	}
-+	DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
-+	/* Set core_if's lock pointer to NULL */
-+	dwc_otg_hcd->core_if->lock = NULL;
-+
-+	DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
-+	DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
-+	DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);
-+	DWC_FREE(dwc_otg_hcd->fiq_state);
-+
-+#ifdef DWC_DEV_SRPCAP
-+	if (dwc_otg_hcd->core_if->power_down == 2 &&
-+	    dwc_otg_hcd->core_if->pwron_timer) {
-+		DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
-+	}
-+#endif
-+	DWC_FREE(dwc_otg_hcd);
-+}
-+
-+int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
-+{
-+	struct device *dev = dwc_otg_hcd_to_dev(hcd);
-+	int retval = 0;
-+	int num_channels;
-+	int i;
-+	dwc_hc_t *channel;
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
-+	DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock);
-+#else
-+	hcd->lock = DWC_SPINLOCK_ALLOC();
-+#endif
-+        DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
-+                    hcd, core_if);
-+	if (!hcd->lock) {
-+		DWC_ERROR("Could not allocate lock for pcd");
-+		DWC_FREE(hcd);
-+		retval = -DWC_E_NO_MEMORY;
-+		goto out;
-+	}
-+	hcd->core_if = core_if;
-+
-+	/* Register the HCD CIL Callbacks */
-+	dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
-+					   &hcd_cil_callbacks, hcd);
-+
-+	/* Initialize the non-periodic schedule. */
-+	DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
-+	DWC_LIST_INIT(&hcd->non_periodic_sched_active);
-+
-+	/* Initialize the periodic schedule. */
-+	DWC_LIST_INIT(&hcd->periodic_sched_inactive);
-+	DWC_LIST_INIT(&hcd->periodic_sched_ready);
-+	DWC_LIST_INIT(&hcd->periodic_sched_assigned);
-+	DWC_LIST_INIT(&hcd->periodic_sched_queued);
-+	DWC_TAILQ_INIT(&hcd->completed_urb_list);
-+	/*
-+	 * Create a host channel descriptor for each host channel implemented
-+	 * in the controller. Initialize the channel descriptor array.
-+	 */
-+	DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
-+	num_channels = hcd->core_if->core_params->host_channels;
-+	DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
-+	for (i = 0; i < num_channels; i++) {
-+		channel = DWC_ALLOC(sizeof(dwc_hc_t));
-+		if (channel == NULL) {
-+			retval = -DWC_E_NO_MEMORY;
-+			DWC_ERROR("%s: host channel allocation failed\n",
-+				  __func__);
-+			dwc_otg_hcd_free(hcd);
-+			goto out;
-+		}
-+		channel->hc_num = i;
-+		hcd->hc_ptr_array[i] = channel;
-+#ifdef DEBUG
-+		hcd->core_if->hc_xfer_timer[i] =
-+		    DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
-+				    &hcd->core_if->hc_xfer_info[i]);
-+#endif
-+		DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
-+			    channel);
-+	}
-+
-+	if (fiq_enable) {
-+		hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels));
-+		if (!hcd->fiq_state) {
-+			retval = -DWC_E_NO_MEMORY;
-+			DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__);
-+			dwc_otg_hcd_free(hcd);
-+			goto out;
-+		}
-+		DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
-+
-+		for (i = 0; i < num_channels; i++) {
-+			hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
-+		}
-+		hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16);
-+
-+		hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));
-+		if (!hcd->fiq_stack) {
-+			retval = -DWC_E_NO_MEMORY;
-+			DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__);
-+			dwc_otg_hcd_free(hcd);
-+			goto out;
-+		}
-+		hcd->fiq_stack->magic1 = 0xDEADBEEF;
-+		hcd->fiq_stack->magic2 = 0xD00DFEED;
-+		hcd->fiq_state->gintmsk_saved.d32 = ~0;
-+		hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
-+
-+		/* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools
-+		 * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels)
-+		 * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some
-+		 * moderately readable array casts.
-+		 */
-+		hcd->fiq_dmab = DWC_DMA_ALLOC(dev, (sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
-+		DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
-+				(unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
-+				sizeof(struct fiq_dma_channel) * num_channels);
-+
-+		DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
-+
-+		/* pointer for debug in fiq_print */
-+		hcd->fiq_state->fiq_dmab = hcd->fiq_dmab;
-+		if (fiq_fsm_enable) {
-+			int i;
-+			for (i=0; i < hcd->core_if->core_params->host_channels; i++) {
-+				dwc_otg_cleanup_fiq_channel(hcd, i);
-+			}
-+			DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s",
-+				(fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "",
-+				(fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "",
-+				(fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "",
-+				(fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : "");
-+		}
-+	}
-+
-+	/* Initialize the Connection timeout timer. */
-+	hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
-+					  dwc_otg_hcd_connect_timeout, 0);
-+
-+	printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled");
-+	if (microframe_schedule)
-+		init_hcd_usecs(hcd);
-+
-+	/* Initialize reset tasklet. */
-+	hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
-+
-+	hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet",
-+						completion_tasklet_func, hcd);
-+#ifdef DWC_DEV_SRPCAP
-+	if (hcd->core_if->power_down == 2) {
-+		/* Initialize Power on timer for Host power up in case hibernation */
-+		hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
-+									dwc_otg_hcd_power_up, core_if);
-+	}
-+#endif
-+
-+	/*
-+	 * Allocate space for storing data on status transactions. Normally no
-+	 * data is sent, but this space acts as a bit bucket. This must be
-+	 * done after usb_add_hcd since that function allocates the DMA buffer
-+	 * pool.
-+	 */
-+	if (hcd->core_if->dma_enable) {
-+		hcd->status_buf =
-+		    DWC_DMA_ALLOC(dev, DWC_OTG_HCD_STATUS_BUF_SIZE,
-+				  &hcd->status_buf_dma);
-+	} else {
-+		hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
-+	}
-+	if (!hcd->status_buf) {
-+		retval = -DWC_E_NO_MEMORY;
-+		DWC_ERROR("%s: status_buf allocation failed\n", __func__);
-+		dwc_otg_hcd_free(hcd);
-+		goto out;
-+	}
-+
-+	hcd->otg_port = 1;
-+	hcd->frame_list = NULL;
-+	hcd->frame_list_dma = 0;
-+	hcd->periodic_qh_count = 0;
-+
-+	DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port));
-+#ifdef FIQ_DEBUG
-+	DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc));
-+#endif
-+
-+out:
-+	return retval;
-+}
-+
-+void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
-+{
-+	/* Turn off all host-specific interrupts. */
-+	dwc_otg_disable_host_interrupts(hcd->core_if);
-+
-+	dwc_otg_hcd_free(hcd);
-+}
-+
-+/**
-+ * Initializes dynamic portions of the DWC_otg HCD state.
-+ */
-+static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
-+{
-+	int num_channels;
-+	int i;
-+	dwc_hc_t *channel;
-+	dwc_hc_t *channel_tmp;
-+
-+	hcd->flags.d32 = 0;
-+
-+	hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
-+	if (!microframe_schedule) {
-+		hcd->non_periodic_channels = 0;
-+		hcd->periodic_channels = 0;
-+	} else {
-+		hcd->available_host_channels = hcd->core_if->core_params->host_channels;
-+	}
-+	/*
-+	 * Put all channels in the free channel list and clean up channel
-+	 * states.
-+	 */
-+	DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
-+				 &hcd->free_hc_list, hc_list_entry) {
-+		DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
-+	}
-+
-+	num_channels = hcd->core_if->core_params->host_channels;
-+	for (i = 0; i < num_channels; i++) {
-+		channel = hcd->hc_ptr_array[i];
-+		DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
-+					hc_list_entry);
-+		dwc_otg_hc_cleanup(hcd->core_if, channel);
-+	}
-+
-+	/* Initialize the DWC core for host mode operation. */
-+	dwc_otg_core_host_init(hcd->core_if);
-+
-+	/* Set core_if's lock pointer to the hcd->lock */
-+	hcd->core_if->lock = hcd->lock;
-+}
-+
-+/**
-+ * Assigns transactions from a QTD to a free host channel and initializes the
-+ * host channel to perform the transactions. The host channel is removed from
-+ * the free list.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param qh Transactions from the first QTD for this QH are selected and
-+ * assigned to a free host channel.
-+ */
-+static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	dwc_hc_t *hc;
-+	dwc_otg_qtd_t *qtd;
-+	dwc_otg_hcd_urb_t *urb;
-+	void* ptr = NULL;
-+	uint32_t intr_enable;
-+	unsigned long flags;
-+	gintmsk_data_t gintmsk = { .d32 = 0, };
-+	struct device *dev = dwc_otg_hcd_to_dev(hcd);
-+
-+	qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+	urb = qtd->urb;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
-+
-+	if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))
-+		urb->actual_length = urb->length;
-+
-+
-+	hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
-+
-+	/* Remove the host channel from the free list. */
-+	DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+	qh->channel = hc;
-+
-+	qtd->in_process = 1;
-+
-+	/*
-+	 * Use usb_pipedevice to determine device address. This address is
-+	 * 0 before the SET_ADDRESS command and the correct address afterward.
-+	 */
-+	hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
-+	hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
-+	hc->speed = qh->dev_speed;
-+	hc->max_packet = dwc_max_packet(qh->maxp);
-+
-+	hc->xfer_started = 0;
-+	hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
-+	hc->error_state = (qtd->error_count > 0);
-+	hc->halt_on_queue = 0;
-+	hc->halt_pending = 0;
-+	hc->requests = 0;
-+
-+	/*
-+	 * The following values may be modified in the transfer type section
-+	 * below. The xfer_len value may be reduced when the transfer is
-+	 * started to accommodate the max widths of the XferSize and PktCnt
-+	 * fields in the HCTSIZn register.
-+	 */
-+
-+	hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
-+	if (hc->ep_is_in) {
-+		hc->do_ping = 0;
-+	} else {
-+		hc->do_ping = qh->ping_state;
-+	}
-+
-+	hc->data_pid_start = qh->data_toggle;
-+	hc->multi_count = 1;
-+
-+	if (hcd->core_if->dma_enable) {
-+		hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
-+
-+		/* For non-dword aligned case */
-+		if (((unsigned long)hc->xfer_buff & 0x3)
-+		    && !hcd->core_if->dma_desc_enable) {
-+			ptr = (uint8_t *) urb->buf + urb->actual_length;
-+		}
-+	} else {
-+		hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
-+	}
-+	hc->xfer_len = urb->length - urb->actual_length;
-+	hc->xfer_count = 0;
-+
-+	/*
-+	 * Set the split attributes
-+	 */
-+	hc->do_split = 0;
-+	if (qh->do_split) {
-+		uint32_t hub_addr, port_addr;
-+		hc->do_split = 1;
-+		hc->start_pkt_count = 1;
-+		hc->xact_pos = qtd->isoc_split_pos;
-+		/* We don't need to do complete splits anymore */
-+//		if(fiq_fsm_enable)
-+		if (0)
-+			hc->complete_split = qtd->complete_split = 0;
-+		else
-+			hc->complete_split = qtd->complete_split;
-+
-+		hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
-+		hc->hub_addr = (uint8_t) hub_addr;
-+		hc->port_addr = (uint8_t) port_addr;
-+	}
-+
-+	switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
-+	case UE_CONTROL:
-+		hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
-+		switch (qtd->control_phase) {
-+		case DWC_OTG_CONTROL_SETUP:
-+			DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
-+			hc->do_ping = 0;
-+			hc->ep_is_in = 0;
-+			hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
-+			if (hcd->core_if->dma_enable) {
-+				hc->xfer_buff = (uint8_t *) urb->setup_dma;
-+			} else {
-+				hc->xfer_buff = (uint8_t *) urb->setup_packet;
-+			}
-+			hc->xfer_len = 8;
-+			ptr = NULL;
-+			break;
-+		case DWC_OTG_CONTROL_DATA:
-+			DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
-+			hc->data_pid_start = qtd->data_toggle;
-+			break;
-+		case DWC_OTG_CONTROL_STATUS:
-+			/*
-+			 * Direction is opposite of data direction or IN if no
-+			 * data.
-+			 */
-+			DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
-+			if (urb->length == 0) {
-+				hc->ep_is_in = 1;
-+			} else {
-+				hc->ep_is_in =
-+				    dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
-+			}
-+			if (hc->ep_is_in) {
-+				hc->do_ping = 0;
-+			}
-+
-+			hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
-+
-+			hc->xfer_len = 0;
-+			if (hcd->core_if->dma_enable) {
-+				hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
-+			} else {
-+				hc->xfer_buff = (uint8_t *) hcd->status_buf;
-+			}
-+			ptr = NULL;
-+			break;
-+		}
-+		break;
-+	case UE_BULK:
-+		hc->ep_type = DWC_OTG_EP_TYPE_BULK;
-+		break;
-+	case UE_INTERRUPT:
-+		hc->ep_type = DWC_OTG_EP_TYPE_INTR;
-+		break;
-+	case UE_ISOCHRONOUS:
-+		{
-+			struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+			hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
-+
-+			if (hcd->core_if->dma_desc_enable)
-+				break;
-+
-+			frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
-+
-+			frame_desc->status = 0;
-+
-+			if (hcd->core_if->dma_enable) {
-+				hc->xfer_buff = (uint8_t *) urb->dma;
-+			} else {
-+				hc->xfer_buff = (uint8_t *) urb->buf;
-+			}
-+			hc->xfer_buff +=
-+			    frame_desc->offset + qtd->isoc_split_offset;
-+			hc->xfer_len =
-+			    frame_desc->length - qtd->isoc_split_offset;
-+
-+			/* For non-dword aligned buffers */
-+			if (((unsigned long)hc->xfer_buff & 0x3)
-+			    && hcd->core_if->dma_enable) {
-+				ptr =
-+				    (uint8_t *) urb->buf + frame_desc->offset +
-+				    qtd->isoc_split_offset;
-+			} else
-+				ptr = NULL;
-+
-+			if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
-+				if (hc->xfer_len <= 188) {
-+					hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+				} else {
-+					hc->xact_pos =
-+					    DWC_HCSPLIT_XACTPOS_BEGIN;
-+				}
-+			}
-+		}
-+		break;
-+	}
-+	/* non DWORD-aligned buffer case */
-+	if (ptr) {
-+		uint32_t buf_size;
-+		if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+			buf_size = hcd->core_if->core_params->max_transfer_size;
-+		} else {
-+			buf_size = 4096;
-+		}
-+		if (!qh->dw_align_buf) {
-+			qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(dev, buf_size,
-+							 &qh->dw_align_buf_dma);
-+			if (!qh->dw_align_buf) {
-+				DWC_ERROR
-+				    ("%s: Failed to allocate memory to handle "
-+				     "non-dword aligned buffer case\n",
-+				     __func__);
-+				return;
-+			}
-+		}
-+		if (!hc->ep_is_in) {
-+			dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
-+		}
-+		hc->align_buff = qh->dw_align_buf_dma;
-+	} else {
-+		hc->align_buff = 0;
-+	}
-+
-+	if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+	    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+		/*
-+		 * This value may be modified when the transfer is started to
-+		 * reflect the actual transfer length.
-+		 */
-+		hc->multi_count = dwc_hb_mult(qh->maxp);
-+	}
-+
-+	if (hcd->core_if->dma_desc_enable)
-+		hc->desc_list_addr = qh->desc_list_dma;
-+
-+	dwc_otg_hc_init(hcd->core_if, hc);
-+
-+	local_irq_save(flags);
-+
-+	if (fiq_enable) {
-+		local_fiq_disable();
-+		fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+	}
-+
-+	/* Enable the top level host channel interrupt. */
-+	intr_enable = (1 << hc->hc_num);
-+	DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable);
-+
-+	/* Make sure host channel interrupts are enabled. */
-+	gintmsk.b.hcintr = 1;
-+	DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+
-+	if (fiq_enable) {
-+		fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+		local_fiq_enable();
-+	}
-+
-+	local_irq_restore(flags);
-+	hc->qh = qh;
-+}
-+
-+
-+/**
-+ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ
-+ * @hcd:	Pointer to the dwc_otg_hcd struct
-+ * @qh:	pointer to the endpoint's queue head
-+ *
-+ * Transaction start/end control flow is grafted onto the existing dwc_otg
-+ * mechanisms, to avoid spaghettifying the functions more than they already are.
-+ * This function's eligibility check is altered by debug parameter.
-+ *
-+ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction.
-+ */
-+
-+int fiq_fsm_transaction_suitable(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
-+{
-+	if (qh->do_split) {
-+		switch (qh->ep_type) {
-+		case UE_CONTROL:
-+		case UE_BULK:
-+			if (fiq_fsm_mask & (1 << 0))
-+				return 1;
-+			break;
-+		case UE_INTERRUPT:
-+		case UE_ISOCHRONOUS:
-+			if (fiq_fsm_mask & (1 << 1))
-+				return 1;
-+			break;
-+		default:
-+			break;
-+		}
-+	} else if (qh->ep_type == UE_ISOCHRONOUS) {
-+		if (fiq_fsm_mask & (1 << 2)) {
-+			/* ISOCH support. We test for compatibility:
-+			 * - DWORD aligned buffers
-+			 * - Must be at least 2 transfers (otherwise pointless to use the FIQ)
-+			 * If yes, then the fsm enqueue function will handle the state machine setup.
-+			 */
-+			dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+			dwc_otg_hcd_urb_t *urb = qtd->urb;
-+			dwc_dma_t ptr;
-+			int i;
-+
-+			if (urb->packet_count < 2)
-+				return 0;
-+			for (i = 0; i < urb->packet_count; i++) {
-+				ptr = urb->dma + urb->iso_descs[i].offset;
-+				if (ptr & 0x3)
-+					return 0;
-+			}
-+			return 1;
-+		}
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers
-+ * @hcd: Pointer to the dwc_otg_hcd struct
-+ * @qh: Pointer to the endpoint's queue head
-+ *
-+ * Periodic split transactions are transmitted modulo 188 bytes.
-+ * This necessitates slicing data up into buckets for isochronous out
-+ * and fixing up the DMA address for all IN transfers.
-+ *
-+ * Returns 1 if the DMA bounce buffers have been used, 0 if the default
-+ * HC buffer has been used.
-+ */
-+int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh)
-+ {
-+	int frame_length, i = 0;
-+	uint8_t *ptr = NULL;
-+	dwc_hc_t *hc = qh->channel;
-+	struct fiq_dma_blob *blob;
-+	struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+	for (i = 0; i < 6; i++) {
-+		st->dma_info.slot_len[i] = 255;
-+	}
-+	st->dma_info.index = 0;
-+	i = 0;
-+	if (hc->ep_is_in) {
-+		/*
-+		 * Set dma_regs to bounce buffer. FIQ will update the
-+		 * state depending on transaction progress.
-+		 */
-+		blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-+		st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
-+		/* Calculate the max number of CSPLITS such that the FIQ can time out
-+		 * a transaction if it fails.
-+		 */
-+		frame_length = st->hcchar_copy.b.mps;
-+		do {
-+			i++;
-+			frame_length -= 188;
-+		} while (frame_length >= 0);
-+		st->nrpackets = i;
-+		return 1;
-+	} else {
-+		if (qh->ep_type == UE_ISOCHRONOUS) {
-+
-+			dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+			frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+			frame_length = frame_desc->length;
-+
-+			/* Virtual address for bounce buffers */
-+			blob = hcd->fiq_dmab;
-+
-+			ptr = qtd->urb->buf + frame_desc->offset;
-+			if (frame_length == 0) {
-+				/*
-+				 * for isochronous transactions, we must still transmit a packet
-+				 * even if the length is zero.
-+				 */
-+				st->dma_info.slot_len[0] = 0;
-+				st->nrpackets = 1;
-+			} else {
-+				do {
-+					if (frame_length <= 188) {
-+						dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);
-+						st->dma_info.slot_len[i] = frame_length;
-+						ptr += frame_length;
-+					} else {
-+						dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);
-+						st->dma_info.slot_len[i] = 188;
-+						ptr += 188;
-+					}
-+					i++;
-+					frame_length -= 188;
-+				} while (frame_length > 0);
-+				st->nrpackets = i;
-+			}
-+			ptr = qtd->urb->buf + frame_desc->offset;
-+			/* Point the HC at the DMA address of the bounce buffers */
-+			blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
-+			st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
-+
-+			/* fixup xfersize to the actual packet size */
-+			st->hctsiz_copy.b.pid = 0;
-+			st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0];
-+			return 1;
-+		} else {
-+			/* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */
-+			return 0;
-+		}
-+	}
-+}
-+
-+/**
-+ * fiq_fsm_np_tt_contended() - Avoid performing contended non-periodic transfers
-+ * @hcd: Pointer to the dwc_otg_hcd struct
-+ * @qh: Pointer to the endpoint's queue head
-+ *
-+ * Certain hub chips don't differentiate between IN and OUT non-periodic pipes
-+ * with the same endpoint number. If transfers get completed out of order
-+ * (disregarding the direction token) then the hub can lock up
-+ * or return erroneous responses.
-+ *
-+ * Returns 1 if initiating the transfer would cause contention, 0 otherwise.
-+ */
-+int fiq_fsm_np_tt_contended(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
-+{
-+	int i;
-+	struct fiq_channel_state *st;
-+	int dev_addr = qh->channel->dev_addr;
-+	int ep_num = qh->channel->ep_num;
-+	for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
-+		if (i == qh->channel->hc_num)
-+			continue;
-+		st = &hcd->fiq_state->channel[i];
-+		switch (st->fsm) {
-+		case FIQ_NP_SSPLIT_STARTED:
-+		case FIQ_NP_SSPLIT_RETRY:
-+		case FIQ_NP_SSPLIT_PENDING:
-+		case FIQ_NP_OUT_CSPLIT_RETRY:
-+		case FIQ_NP_IN_CSPLIT_RETRY:
-+			if (st->hcchar_copy.b.devaddr == dev_addr &&
-+				st->hcchar_copy.b.epnum == ep_num)
-+				return 1;
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+	return 0;
-+}
-+
-+/*
-+ * Pushing a periodic request into the queue near the EOF1 point
-+ * in a microframe causes erroneous behaviour (frmovrun) interrupt.
-+ * Usually, the request goes out on the bus causing a transfer but
-+ * the core does not transfer the data to memory.
-+ * This guard interval (in number of 60MHz clocks) is required which
-+ * must cater for CPU latency between reading the value and enabling
-+ * the channel.
-+ */
-+#define PERIODIC_FRREM_BACKOFF 1000
-+
-+int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
-+{
-+	dwc_hc_t *hc = qh->channel;
-+	dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+	dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+	int frame;
-+	struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
-+	int xfer_len, nrpackets;
-+	hcdma_data_t hcdma;
-+	hfnum_data_t hfnum;
-+
-+	if (st->fsm != FIQ_PASSTHROUGH)
-+		return 0;
-+
-+	st->nr_errors = 0;
-+
-+	st->hcchar_copy.d32 = 0;
-+	st->hcchar_copy.b.mps = hc->max_packet;
-+	st->hcchar_copy.b.epdir = hc->ep_is_in;
-+	st->hcchar_copy.b.devaddr = hc->dev_addr;
-+	st->hcchar_copy.b.epnum = hc->ep_num;
-+	st->hcchar_copy.b.eptype = hc->ep_type;
-+
-+	st->hcintmsk_copy.b.chhltd = 1;
-+
-+	frame = dwc_otg_hcd_get_frame_number(hcd);
-+	st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
-+
-+	st->hcchar_copy.b.lspddev = 0;
-+	/* Enable the channel later as a final register write. */
-+
-+	st->hcsplt_copy.d32 = 0;
-+
-+	st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs;
-+	st->hs_isoc_info.nrframes = qtd->urb->packet_count;
-+	/* grab the next DMA address offset from the array */
-+	st->hcdma_copy.d32 = qtd->urb->dma;
-+	hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset;
-+
-+	/* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
-+	 * the core needs to be told to send the correct number. Caution: for IN transfers,
-+	 * this is always set to the maximum size of the endpoint. */
-+	xfer_len = st->hs_isoc_info.iso_desc[0].length;
-+	nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
-+	if (nrpackets == 0)
-+		nrpackets = 1;
-+	st->hcchar_copy.b.multicnt = nrpackets;
-+	st->hctsiz_copy.b.pktcnt = nrpackets;
-+
-+	/* Initial PID also needs to be set */
-+	if (st->hcchar_copy.b.epdir == 0) {
-+		st->hctsiz_copy.b.xfersize = xfer_len;
-+		switch (st->hcchar_copy.b.multicnt) {
-+		case 1:
-+			st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+			break;
-+		case 2:
-+		case 3:
-+			st->hctsiz_copy.b.pid = DWC_PID_MDATA;
-+			break;
-+		}
-+
-+	} else {
-+		st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
-+		switch (st->hcchar_copy.b.multicnt) {
-+		case 1:
-+			st->hctsiz_copy.b.pid = DWC_PID_DATA0;
-+			break;
-+		case 2:
-+			st->hctsiz_copy.b.pid = DWC_PID_DATA1;
-+			break;
-+		case 3:
-+			st->hctsiz_copy.b.pid = DWC_PID_DATA2;
-+			break;
-+		}
-+	}
-+
-+	st->hs_isoc_info.stride = qh->interval;
-+	st->uframe_sleeps = 0;
-+
-+	fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ  %01d ", hc->hc_num);
-+	fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32);
-+	fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
-+	fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
-+	hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+	local_fiq_disable();
-+	fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+	DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
-+	DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
-+	DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
-+	DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+	DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
-+	if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
-+		/* Prevent queueing near EOF1. Bad things happen if a periodic
-+		 * split transaction is queued very close to EOF. SOF interrupt handler
-+		 * will wake this channel at the next interrupt.
-+		 */
-+		st->fsm = FIQ_HS_ISOC_SLEEPING;
-+		st->uframe_sleeps = 1;
-+	} else {
-+		st->fsm = FIQ_HS_ISOC_TURBO;
-+		st->hcchar_copy.b.chen = 1;
-+		DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+	}
-+	mb();
-+	st->hcchar_copy.b.chen = 0;
-+	fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+	local_fiq_enable();
-+	return 0;
-+}
-+
-+
-+/**
-+ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state
-+ * @hcd: Pointer to the dwc_otg_hcd struct
-+ * @qh: Pointer to the endpoint's queue head
-+ *
-+ * This overrides the dwc_otg driver's normal method of queueing a transaction.
-+ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup
-+ * for the nominated host channel.
-+ *
-+ * For periodic transfers, it also peeks at the FIQ state to see if an immediate
-+ * start is possible. If not, then the FIQ is left to start the transfer.
-+ */
-+int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
-+{
-+	int start_immediate = 1, i;
-+	hfnum_data_t hfnum;
-+	dwc_hc_t *hc = qh->channel;
-+	dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
-+	/* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */
-+	int hub_addr, port_addr, frame, uframe;
-+	struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
-+
-+	/*
-+	 * Non-periodic channel assignments stay in the non_periodic_active queue.
-+	 * Therefore we get repeatedly called until the FIQ's done processing this channel.
-+	 */
-+	if (qh->channel->xfer_started == 1)
-+		return 0;
-+
-+	if (st->fsm != FIQ_PASSTHROUGH) {
-+		pr_warn_ratelimited("%s:%d: Queue called for an active channel\n", __func__, __LINE__);
-+		return 0;
-+	}
-+
-+	qh->channel->xfer_started = 1;
-+
-+	st->nr_errors = 0;
-+
-+	st->hcchar_copy.d32 = 0;
-+	st->hcchar_copy.b.mps = hc->max_packet;
-+	st->hcchar_copy.b.epdir = hc->ep_is_in;
-+	st->hcchar_copy.b.devaddr = hc->dev_addr;
-+	st->hcchar_copy.b.epnum = hc->ep_num;
-+	st->hcchar_copy.b.eptype = hc->ep_type;
-+	if (hc->ep_type & 0x1) {
-+		if (hc->ep_is_in)
-+			st->hcchar_copy.b.multicnt = 3;
-+		else
-+			/* Docs say set this to 1, but driver sets to 0! */
-+			st->hcchar_copy.b.multicnt = 0;
-+	} else {
-+		st->hcchar_copy.b.multicnt = 1;
-+		st->hcchar_copy.b.oddfrm = 0;
-+	}
-+	st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0;
-+	/* Enable the channel later as a final register write. */
-+
-+	st->hcsplt_copy.d32 = 0;
-+	if(qh->do_split) {
-+		hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr);
-+		st->hcsplt_copy.b.compsplt = 0;
-+		st->hcsplt_copy.b.spltena = 1;
-+		// XACTPOS is for isoc-out only but needs initialising anyway.
-+		st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL;
-+		if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) {
-+			/* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL.
-+			 * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ
-+			 * will update as necessary.
-+			 */
-+			if (hc->xfer_len > 188) {
-+				st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN;
-+			}
-+		}
-+		st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr;
-+		st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr;
-+		st->hub_addr = hub_addr;
-+		st->port_addr = port_addr;
-+	}
-+
-+	st->hctsiz_copy.d32 = 0;
-+	st->hctsiz_copy.b.dopng = 0;
-+	st->hctsiz_copy.b.pid = hc->data_pid_start;
-+
-+	if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
-+		hc->xfer_len = hc->max_packet;
-+	} else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
-+		hc->xfer_len = 188;
-+	}
-+	st->hctsiz_copy.b.xfersize = hc->xfer_len;
-+
-+	st->hctsiz_copy.b.pktcnt = 1;
-+
-+	if (hc->ep_type & 0x1) {
-+		/*
-+		 * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers,
-+		 * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array.
-+		 * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt
-+		 * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set
-+		 * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ
-+		 * must not touch internal driver state.
-+		 */
-+		if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) {
-+			if (hc->align_buff) {
-+				st->hcdma_copy.d32 = hc->align_buff;
-+			} else {
-+				st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+			}
-+		}
-+	} else {
-+		if (hc->align_buff) {
-+			st->hcdma_copy.d32 = hc->align_buff;
-+		} else {
-+			st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+		}
-+	}
-+	/* The FIQ depends upon no other interrupts being enabled except channel halt.
-+	 * Fixup channel interrupt mask. */
-+	st->hcintmsk_copy.d32 = 0;
-+	st->hcintmsk_copy.b.chhltd = 1;
-+	st->hcintmsk_copy.b.ahberr = 1;
-+
-+	/* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions
-+	 * as Control puts the transfer into the non-periodic request queue and the
-+	 * non-periodic handler in the hub. Makes things lots easier.
-+	 */
-+	if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) {
-+		st->hcchar_copy.b.multicnt = 0;
-+		st->hcchar_copy.b.oddfrm = 0;
-+		st->hcchar_copy.b.eptype = UE_CONTROL;
-+		if (hc->align_buff) {
-+			st->hcdma_copy.d32 = hc->align_buff;
-+		} else {
-+			st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
-+		}
-+	}
-+	DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
-+	DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
-+	DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
-+	DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+	DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
-+
-+	local_fiq_disable();
-+	fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+
-+	if (hc->ep_type & 0x1) {
-+		hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+		frame = (hfnum.b.frnum & ~0x7) >> 3;
-+		uframe = hfnum.b.frnum & 0x7;
-+		if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
-+			/* Prevent queueing near EOF1. Bad things happen if a periodic
-+			 * split transaction is queued very close to EOF.
-+			 */
-+			start_immediate = 0;
-+		} else if (uframe == 5) {
-+			start_immediate = 0;
-+		} else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) {
-+			start_immediate = 0;
-+		} else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) {
-+			start_immediate = 0;
-+		} else {
-+			/* Search through all host channels to determine if a transaction
-+			 * is currently in progress */
-+			for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
-+				if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH)
-+					continue;
-+				switch (hcd->fiq_state->channel[i].fsm) {
-+				/* TT is reserved for channels that are in the middle of a periodic
-+				 * split transaction.
-+				 */
-+				case FIQ_PER_SSPLIT_STARTED:
-+				case FIQ_PER_CSPLIT_WAIT:
-+				case FIQ_PER_CSPLIT_NYET1:
-+				case FIQ_PER_CSPLIT_POLL:
-+				case FIQ_PER_ISO_OUT_ACTIVE:
-+				case FIQ_PER_ISO_OUT_LAST:
-+					if (hcd->fiq_state->channel[i].hub_addr == hub_addr &&
-+							hcd->fiq_state->channel[i].port_addr == port_addr) {
-+						start_immediate = 0;
-+					}
-+					break;
-+				default:
-+					break;
-+				}
-+				if (!start_immediate)
-+					break;
-+			}
-+		}
-+	}
-+	if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT)
-+		start_immediate = 1;
-+
-+	fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate);
-+	fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem);
-+	//fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr);
-+	//fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
-+	//fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
-+	switch (hc->ep_type) {
-+		case UE_CONTROL:
-+		case UE_BULK:
-+			if (fiq_fsm_np_tt_contended(hcd, qh)) {
-+				st->fsm = FIQ_NP_SSPLIT_PENDING;
-+				start_immediate = 0;
-+			} else {
-+				st->fsm = FIQ_NP_SSPLIT_STARTED;
-+			}
-+			break;
-+		case UE_ISOCHRONOUS:
-+			if (hc->ep_is_in) {
-+				if (start_immediate) {
-+					st->fsm = FIQ_PER_SSPLIT_STARTED;
-+				} else {
-+					st->fsm = FIQ_PER_SSPLIT_QUEUED;
-+				}
-+			} else {
-+				if (start_immediate) {
-+					/* Single-isoc OUT packets don't require FIQ involvement */
-+					if (st->nrpackets == 1) {
-+						st->fsm = FIQ_PER_ISO_OUT_LAST;
-+					} else {
-+						st->fsm = FIQ_PER_ISO_OUT_ACTIVE;
-+					}
-+				} else {
-+					st->fsm = FIQ_PER_ISO_OUT_PENDING;
-+				}
-+			}
-+			break;
-+		case UE_INTERRUPT:
-+			if (fiq_fsm_mask & 0x8) {
-+				if (fiq_fsm_np_tt_contended(hcd, qh)) {
-+					st->fsm = FIQ_NP_SSPLIT_PENDING;
-+					start_immediate = 0;
-+				} else {
-+					st->fsm = FIQ_NP_SSPLIT_STARTED;
-+				}
-+			} else if (start_immediate) {
-+					st->fsm = FIQ_PER_SSPLIT_STARTED;
-+			} else {
-+				st->fsm = FIQ_PER_SSPLIT_QUEUED;
-+			}
-+		default:
-+			break;
-+	}
-+	if (start_immediate) {
-+		/* Set the oddfrm bit as close as possible to actual queueing */
-+		frame = dwc_otg_hcd_get_frame_number(hcd);
-+		st->expected_uframe = (frame + 1) & 0x3FFF;
-+		st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
-+		st->hcchar_copy.b.chen = 1;
-+		DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
-+	}
-+	mb();
-+	fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+	local_fiq_enable();
-+	return 0;
-+}
-+
-+
-+/**
-+ * This function selects transactions from the HCD transfer schedule and
-+ * assigns them to available host channels. It is called from HCD interrupt
-+ * handler functions.
-+ *
-+ * @param hcd The HCD state structure.
-+ *
-+ * @return The types of new transactions that were assigned to host channels.
-+ */
-+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
-+{
-+	dwc_list_link_t *qh_ptr;
-+	dwc_otg_qh_t *qh;
-+	int num_channels;
-+	dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
-+
-+#ifdef DEBUG_HOST_CHANNELS
-+	last_sel_trans_num_per_scheduled = 0;
-+	last_sel_trans_num_nonper_scheduled = 0;
-+	last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;
-+#endif /* DEBUG_HOST_CHANNELS */
-+
-+	/* Process entries in the periodic ready list. */
-+	qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
-+
-+	while (qh_ptr != &hcd->periodic_sched_ready &&
-+	       !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+
-+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+
-+		if (microframe_schedule) {
-+			// Make sure we leave one channel for non periodic transactions.
-+			if (hcd->available_host_channels <= 1) {
-+				break;
-+			}
-+			hcd->available_host_channels--;
-+#ifdef DEBUG_HOST_CHANNELS
-+			last_sel_trans_num_per_scheduled++;
-+#endif /* DEBUG_HOST_CHANNELS */
-+		}
-+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+		assign_and_init_hc(hcd, qh);
-+
-+		/*
-+		 * Move the QH from the periodic ready schedule to the
-+		 * periodic assigned schedule.
-+		 */
-+		qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+		DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+				   &qh->qh_list_entry);
-+	}
-+
-+	/*
-+	 * Process entries in the inactive portion of the non-periodic
-+	 * schedule. Some free host channels may not be used if they are
-+	 * reserved for periodic transfers.
-+	 */
-+	qh_ptr = hcd->non_periodic_sched_inactive.next;
-+	num_channels = hcd->core_if->core_params->host_channels;
-+	while (qh_ptr != &hcd->non_periodic_sched_inactive &&
-+	       (microframe_schedule || hcd->non_periodic_channels <
-+		num_channels - hcd->periodic_channels) &&
-+	       !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+
-+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+		/*
-+		 * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission
-+		 * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed
-+		 * cheeky devices that just hold off using NAKs
-+		 */
-+		if (fiq_enable && nak_holdoff && qh->do_split) {
-+			if (qh->nak_frame != 0xffff) {
-+				uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8);
-+				uint16_t frame = dwc_otg_hcd_get_frame_number(hcd);
-+				if (dwc_frame_num_le(frame, next_frame)) {
-+					if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) {
-+						hcd->fiq_state->next_sched_frame = next_frame;
-+					}
-+					qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+					continue;
-+				} else {
-+					qh->nak_frame = 0xFFFF;
-+				}
-+			}
-+		}
-+
-+		if (microframe_schedule) {
-+				if (hcd->available_host_channels < 1) {
-+					break;
-+				}
-+				hcd->available_host_channels--;
-+#ifdef DEBUG_HOST_CHANNELS
-+				last_sel_trans_num_nonper_scheduled++;
-+#endif /* DEBUG_HOST_CHANNELS */
-+		}
-+
-+		assign_and_init_hc(hcd, qh);
-+
-+		/*
-+		 * Move the QH from the non-periodic inactive schedule to the
-+		 * non-periodic active schedule.
-+		 */
-+		qh_ptr = DWC_LIST_NEXT(qh_ptr);
-+		DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
-+				   &qh->qh_list_entry);
-+
-+		if (!microframe_schedule)
-+			hcd->non_periodic_channels++;
-+	}
-+	/* we moved a non-periodic QH to the active schedule. If the inactive queue is empty,
-+	 * stop the FIQ from kicking us. We could potentially still have elements here if we
-+	 * ran out of host channels.
-+	 */
-+	if (fiq_enable) {
-+		if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) {
-+			hcd->fiq_state->kick_np_queues = 0;
-+		} else {
-+			/* For each entry remaining in the NP inactive queue,
-+			* if this a NAK'd retransmit then don't set the kick flag.
-+			*/
-+			if(nak_holdoff) {
-+				DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) {
-+					qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+					if (qh->nak_frame == 0xFFFF) {
-+						hcd->fiq_state->kick_np_queues = 1;
-+					}
-+				}
-+			}
-+		}
-+	}
-+	if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned))
-+		ret_val |= DWC_OTG_TRANSACTION_PERIODIC;
-+
-+	if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active))
-+		ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC;
-+
-+
-+#ifdef DEBUG_HOST_CHANNELS
-+	last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;
-+#endif /* DEBUG_HOST_CHANNELS */
-+	return ret_val;
-+}
-+
-+/**
-+ * Attempts to queue a single transaction request for a host channel
-+ * associated with either a periodic or non-periodic transfer. This function
-+ * assumes that there is space available in the appropriate request queue. For
-+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
-+ * is available in the appropriate Tx FIFO.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param hc Host channel descriptor associated with either a periodic or
-+ * non-periodic transfer.
-+ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
-+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
-+ * transfers.
-+ *
-+ * @return 1 if a request is queued and more requests may be needed to
-+ * complete the transfer, 0 if no more requests are required for this
-+ * transfer, -1 if there is insufficient space in the Tx FIFO.
-+ */
-+static int queue_transaction(dwc_otg_hcd_t * hcd,
-+			     dwc_hc_t * hc, uint16_t fifo_dwords_avail)
-+{
-+	int retval;
-+
-+	if (hcd->core_if->dma_enable) {
-+		if (hcd->core_if->dma_desc_enable) {
-+			if (!hc->xfer_started
-+			    || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
-+				dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
-+				hc->qh->ping_state = 0;
-+			}
-+		} else if (!hc->xfer_started) {
-+			if (fiq_fsm_enable && hc->error_state) {
-+				hcd->fiq_state->channel[hc->hc_num].nr_errors =
-+					DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count;
-+				hcd->fiq_state->channel[hc->hc_num].fsm =
-+					FIQ_PASSTHROUGH_ERRORSTATE;
-+			}
-+			dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+			hc->qh->ping_state = 0;
-+		}
-+		retval = 0;
-+	} else if (hc->halt_pending) {
-+		/* Don't queue a request if the channel has been halted. */
-+		retval = 0;
-+	} else if (hc->halt_on_queue) {
-+		dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
-+		retval = 0;
-+	} else if (hc->do_ping) {
-+		if (!hc->xfer_started) {
-+			dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+		}
-+		retval = 0;
-+	} else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
-+		if ((fifo_dwords_avail * 4) >= hc->max_packet) {
-+			if (!hc->xfer_started) {
-+				dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+				retval = 1;
-+			} else {
-+				retval =
-+				    dwc_otg_hc_continue_transfer(hcd->core_if,
-+								 hc);
-+			}
-+		} else {
-+			retval = -1;
-+		}
-+	} else {
-+		if (!hc->xfer_started) {
-+			dwc_otg_hc_start_transfer(hcd->core_if, hc);
-+			retval = 1;
-+		} else {
-+			retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
-+		}
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * Processes periodic channels for the next frame and queues transactions for
-+ * these channels to the DWC_otg controller. After queueing transactions, the
-+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
-+ * to queue as Periodic Tx FIFO or request queue space becomes available.
-+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
-+ */
-+static void process_periodic_channels(dwc_otg_hcd_t * hcd)
-+{
-+	hptxsts_data_t tx_status;
-+	dwc_list_link_t *qh_ptr;
-+	dwc_otg_qh_t *qh;
-+	int status = 0;
-+	int no_queue_space = 0;
-+	int no_fifo_space = 0;
-+
-+	dwc_otg_host_global_regs_t *host_regs;
-+	host_regs = hcd->core_if->host_if->host_global_regs;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
-+#ifdef DEBUG
-+	tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+	DWC_DEBUGPL(DBG_HCDV,
-+		    "  P Tx Req Queue Space Avail (before queue): %d\n",
-+		    tx_status.b.ptxqspcavail);
-+	DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
-+		    tx_status.b.ptxfspcavail);
-+#endif
-+
-+	qh_ptr = hcd->periodic_sched_assigned.next;
-+	while (qh_ptr != &hcd->periodic_sched_assigned) {
-+		tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+		if (tx_status.b.ptxqspcavail == 0) {
-+			no_queue_space = 1;
-+			break;
-+		}
-+
-+		qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
-+
-+		// Do not send a split start transaction any later than frame .6
-+		// Note, we have to schedule a periodic in .5 to make it go in .6
-+		if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6)
-+		{
-+			qh_ptr = qh_ptr->next;
-+			hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7;
-+			continue;
-+		}
-+
-+		if (fiq_fsm_enable && fiq_fsm_transaction_suitable(hcd, qh)) {
-+			if (qh->do_split)
-+				fiq_fsm_queue_split_transaction(hcd, qh);
-+			else
-+				fiq_fsm_queue_isoc_transaction(hcd, qh);
-+		} else {
-+
-+			/*
-+			 * Set a flag if we're queueing high-bandwidth in slave mode.
-+			 * The flag prevents any halts to get into the request queue in
-+			 * the middle of multiple high-bandwidth packets getting queued.
-+			 */
-+			if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
-+				hcd->core_if->queuing_high_bandwidth = 1;
-+			}
-+			status = queue_transaction(hcd, qh->channel,
-+							tx_status.b.ptxfspcavail);
-+			if (status < 0) {
-+				no_fifo_space = 1;
-+				break;
-+			}
-+		}
-+
-+		/*
-+		 * In Slave mode, stay on the current transfer until there is
-+		 * nothing more to do or the high-bandwidth request count is
-+		 * reached. In DMA mode, only need to queue one request. The
-+		 * controller automatically handles multiple packets for
-+		 * high-bandwidth transfers.
-+		 */
-+		if (hcd->core_if->dma_enable || status == 0 ||
-+		    qh->channel->requests == qh->channel->multi_count) {
-+			qh_ptr = qh_ptr->next;
-+			/*
-+			 * Move the QH from the periodic assigned schedule to
-+			 * the periodic queued schedule.
-+			 */
-+			DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
-+					   &qh->qh_list_entry);
-+
-+			/* done queuing high bandwidth */
-+			hcd->core_if->queuing_high_bandwidth = 0;
-+		}
-+	}
-+
-+	if (!hcd->core_if->dma_enable) {
-+		dwc_otg_core_global_regs_t *global_regs;
-+		gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+		global_regs = hcd->core_if->core_global_regs;
-+		intr_mask.b.ptxfempty = 1;
-+#ifdef DEBUG
-+		tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
-+		DWC_DEBUGPL(DBG_HCDV,
-+			    "  P Tx Req Queue Space Avail (after queue): %d\n",
-+			    tx_status.b.ptxqspcavail);
-+		DWC_DEBUGPL(DBG_HCDV,
-+			    "  P Tx FIFO Space Avail (after queue): %d\n",
-+			    tx_status.b.ptxfspcavail);
-+#endif
-+		if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
-+		    no_queue_space || no_fifo_space) {
-+			/*
-+			 * May need to queue more transactions as the request
-+			 * queue or Tx FIFO empties. Enable the periodic Tx
-+			 * FIFO empty interrupt. (Always use the half-empty
-+			 * level to ensure that new requests are loaded as
-+			 * soon as possible.)
-+			 */
-+			DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
-+					 intr_mask.d32);
-+		} else {
-+			/*
-+			 * Disable the Tx FIFO empty interrupt since there are
-+			 * no more transactions that need to be queued right
-+			 * now. This function is called from interrupt
-+			 * handlers to queue more transactions as transfer
-+			 * states change.
-+			 */
-+			DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
-+					 0);
-+		}
-+	}
-+}
-+
-+/**
-+ * Processes active non-periodic channels and queues transactions for these
-+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx
-+ * FIFO Empty interrupt is enabled if there are more transactions to queue as
-+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
-+ * FIFO Empty interrupt is disabled.
-+ */
-+static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
-+{
-+	gnptxsts_data_t tx_status;
-+	dwc_list_link_t *orig_qh_ptr;
-+	dwc_otg_qh_t *qh;
-+	int status;
-+	int no_queue_space = 0;
-+	int no_fifo_space = 0;
-+	int more_to_do = 0;
-+
-+	dwc_otg_core_global_regs_t *global_regs =
-+	    hcd->core_if->core_global_regs;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
-+#ifdef DEBUG
-+	tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+	DWC_DEBUGPL(DBG_HCDV,
-+		    "  NP Tx Req Queue Space Avail (before queue): %d\n",
-+		    tx_status.b.nptxqspcavail);
-+	DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
-+		    tx_status.b.nptxfspcavail);
-+#endif
-+	/*
-+	 * Keep track of the starting point. Skip over the start-of-list
-+	 * entry.
-+	 */
-+	if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
-+		hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
-+	}
-+	orig_qh_ptr = hcd->non_periodic_qh_ptr;
-+
-+	/*
-+	 * Process once through the active list or until no more space is
-+	 * available in the request queue or the Tx FIFO.
-+	 */
-+	do {
-+		tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+		if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
-+			no_queue_space = 1;
-+			break;
-+		}
-+
-+		qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
-+				    qh_list_entry);
-+
-+		if(fiq_fsm_enable && fiq_fsm_transaction_suitable(hcd, qh)) {
-+			fiq_fsm_queue_split_transaction(hcd, qh);
-+		} else {
-+			status = queue_transaction(hcd, qh->channel,
-+						tx_status.b.nptxfspcavail);
-+
-+			if (status > 0) {
-+				more_to_do = 1;
-+			} else if (status < 0) {
-+				no_fifo_space = 1;
-+				break;
-+			}
-+		}
-+		/* Advance to next QH, skipping start-of-list entry. */
-+		hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
-+		if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
-+			hcd->non_periodic_qh_ptr =
-+			    hcd->non_periodic_qh_ptr->next;
-+		}
-+
-+	} while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
-+
-+	if (!hcd->core_if->dma_enable) {
-+		gintmsk_data_t intr_mask = {.d32 = 0 };
-+		intr_mask.b.nptxfempty = 1;
-+
-+#ifdef DEBUG
-+		tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+		DWC_DEBUGPL(DBG_HCDV,
-+			    "  NP Tx Req Queue Space Avail (after queue): %d\n",
-+			    tx_status.b.nptxqspcavail);
-+		DWC_DEBUGPL(DBG_HCDV,
-+			    "  NP Tx FIFO Space Avail (after queue): %d\n",
-+			    tx_status.b.nptxfspcavail);
-+#endif
-+		if (more_to_do || no_queue_space || no_fifo_space) {
-+			/*
-+			 * May need to queue more transactions as the request
-+			 * queue or Tx FIFO empties. Enable the non-periodic
-+			 * Tx FIFO empty interrupt. (Always use the half-empty
-+			 * level to ensure that new requests are loaded as
-+			 * soon as possible.)
-+			 */
-+			DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
-+					 intr_mask.d32);
-+		} else {
-+			/*
-+			 * Disable the Tx FIFO empty interrupt since there are
-+			 * no more transactions that need to be queued right
-+			 * now. This function is called from interrupt
-+			 * handlers to queue more transactions as transfer
-+			 * states change.
-+			 */
-+			DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
-+					 0);
-+		}
-+	}
-+}
-+
-+/**
-+ * This function processes the currently active host channels and queues
-+ * transactions for these channels to the DWC_otg controller. It is called
-+ * from HCD interrupt handler functions.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param tr_type The type(s) of transactions to queue (non-periodic,
-+ * periodic, or both).
-+ */
-+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
-+				    dwc_otg_transaction_type_e tr_type)
-+{
-+#ifdef DEBUG_SOF
-+	DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
-+#endif
-+	/* Process host channels associated with periodic transfers. */
-+	if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
-+	     tr_type == DWC_OTG_TRANSACTION_ALL) &&
-+	    !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
-+
-+		process_periodic_channels(hcd);
-+	}
-+
-+	/* Process host channels associated with non-periodic transfers. */
-+	if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
-+	    tr_type == DWC_OTG_TRANSACTION_ALL) {
-+		if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
-+			process_non_periodic_channels(hcd);
-+		} else {
-+			/*
-+			 * Ensure NP Tx FIFO empty interrupt is disabled when
-+			 * there are no non-periodic transfers to process.
-+			 */
-+			gintmsk_data_t gintmsk = {.d32 = 0 };
-+			gintmsk.b.nptxfempty = 1;
-+
-+			if (fiq_enable) {
-+				local_fiq_disable();
-+				fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+				DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+				fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+				local_fiq_enable();
-+			} else {
-+				DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+			}
-+		}
-+	}
-+}
-+
-+#ifdef DWC_HS_ELECT_TST
-+/*
-+ * Quick and dirty hack to implement the HS Electrical Test
-+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
-+ *
-+ * This code was copied from our userspace app "hset". It sends a
-+ * Get Device Descriptor control sequence in two parts, first the
-+ * Setup packet by itself, followed some time later by the In and
-+ * Ack packets. Rather than trying to figure out how to add this
-+ * functionality to the normal driver code, we just hijack the
-+ * hardware, using these two function to drive the hardware
-+ * directly.
-+ */
-+
-+static dwc_otg_core_global_regs_t *global_regs;
-+static dwc_otg_host_global_regs_t *hc_global_regs;
-+static dwc_otg_hc_regs_t *hc_regs;
-+static uint32_t *data_fifo;
-+
-+static void do_setup(void)
-+{
-+	gintsts_data_t gintsts;
-+	hctsiz_data_t hctsiz;
-+	hcchar_data_t hcchar;
-+	haint_data_t haint;
-+	hcint_data_t hcint;
-+
-+	/* Enable HAINTs */
-+	DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
-+
-+	/* Enable HCINTs */
-+	DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
-+
-+	/* Read GINTSTS */
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/* Read HAINT */
-+	haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+	/* Read HCINT */
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+	/* Read HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+	/* Clear HCINT */
-+	DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+	/* Clear HAINT */
-+	DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+	/* Clear GINTSTS */
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	/* Read GINTSTS */
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/*
-+	 * Send Setup packet (Get Device Descriptor)
-+	 */
-+
-+	/* Make sure channel is disabled */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	if (hcchar.b.chen) {
-+		hcchar.b.chdis = 1;
-+//              hcchar.b.chen = 1;
-+		DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+		//sleep(1);
-+		dwc_mdelay(1000);
-+
-+		/* Read GINTSTS */
-+		gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+		/* Read HAINT */
-+		haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+		/* Read HCINT */
-+		hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+		/* Read HCCHAR */
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+		/* Clear HCINT */
-+		DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+		/* Clear HAINT */
-+		DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+		/* Clear GINTSTS */
-+		DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	}
-+
-+	/* Set HCTSIZ */
-+	hctsiz.d32 = 0;
-+	hctsiz.b.xfersize = 8;
-+	hctsiz.b.pktcnt = 1;
-+	hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
-+	DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+	/* Set HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+	hcchar.b.epdir = 0;
-+	hcchar.b.epnum = 0;
-+	hcchar.b.mps = 8;
-+	hcchar.b.chen = 1;
-+	DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+	/* Fill FIFO with Setup data for Get Device Descriptor */
-+	data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
-+	DWC_WRITE_REG32(data_fifo++, 0x01000680);
-+	DWC_WRITE_REG32(data_fifo++, 0x00080000);
-+
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/* Wait for host channel interrupt */
-+	do {
-+		gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+	} while (gintsts.b.hcintr == 0);
-+
-+	/* Disable HCINTs */
-+	DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
-+
-+	/* Disable HAINTs */
-+	DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
-+
-+	/* Read HAINT */
-+	haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+	/* Read HCINT */
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+	/* Read HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+	/* Clear HCINT */
-+	DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+	/* Clear HAINT */
-+	DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+	/* Clear GINTSTS */
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	/* Read GINTSTS */
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+}
-+
-+static void do_in_ack(void)
-+{
-+	gintsts_data_t gintsts;
-+	hctsiz_data_t hctsiz;
-+	hcchar_data_t hcchar;
-+	haint_data_t haint;
-+	hcint_data_t hcint;
-+	host_grxsts_data_t grxsts;
-+
-+	/* Enable HAINTs */
-+	DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
-+
-+	/* Enable HCINTs */
-+	DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
-+
-+	/* Read GINTSTS */
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/* Read HAINT */
-+	haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+	/* Read HCINT */
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+	/* Read HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+	/* Clear HCINT */
-+	DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+	/* Clear HAINT */
-+	DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+	/* Clear GINTSTS */
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	/* Read GINTSTS */
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/*
-+	 * Receive Control In packet
-+	 */
-+
-+	/* Make sure channel is disabled */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	if (hcchar.b.chen) {
-+		hcchar.b.chdis = 1;
-+		hcchar.b.chen = 1;
-+		DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+		//sleep(1);
-+		dwc_mdelay(1000);
-+
-+		/* Read GINTSTS */
-+		gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+		/* Read HAINT */
-+		haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+		/* Read HCINT */
-+		hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+		/* Read HCCHAR */
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+		/* Clear HCINT */
-+		DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+		/* Clear HAINT */
-+		DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+		/* Clear GINTSTS */
-+		DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	}
-+
-+	/* Set HCTSIZ */
-+	hctsiz.d32 = 0;
-+	hctsiz.b.xfersize = 8;
-+	hctsiz.b.pktcnt = 1;
-+	hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
-+	DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+	/* Set HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+	hcchar.b.epdir = 1;
-+	hcchar.b.epnum = 0;
-+	hcchar.b.mps = 8;
-+	hcchar.b.chen = 1;
-+	DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/* Wait for receive status queue interrupt */
-+	do {
-+		gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+	} while (gintsts.b.rxstsqlvl == 0);
-+
-+	/* Read RXSTS */
-+	grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+	/* Clear RXSTSQLVL in GINTSTS */
-+	gintsts.d32 = 0;
-+	gintsts.b.rxstsqlvl = 1;
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	switch (grxsts.b.pktsts) {
-+	case DWC_GRXSTS_PKTSTS_IN:
-+		/* Read the data into the host buffer */
-+		if (grxsts.b.bcnt > 0) {
-+			int i;
-+			int word_count = (grxsts.b.bcnt + 3) / 4;
-+
-+			data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
-+
-+			for (i = 0; i < word_count; i++) {
-+				(void)DWC_READ_REG32(data_fifo++);
-+			}
-+		}
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/* Wait for receive status queue interrupt */
-+	do {
-+		gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+	} while (gintsts.b.rxstsqlvl == 0);
-+
-+	/* Read RXSTS */
-+	grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+	/* Clear RXSTSQLVL in GINTSTS */
-+	gintsts.d32 = 0;
-+	gintsts.b.rxstsqlvl = 1;
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	switch (grxsts.b.pktsts) {
-+	case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/* Wait for host channel interrupt */
-+	do {
-+		gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+	} while (gintsts.b.hcintr == 0);
-+
-+	/* Read HAINT */
-+	haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+	/* Read HCINT */
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+	/* Read HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+	/* Clear HCINT */
-+	DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+	/* Clear HAINT */
-+	DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+	/* Clear GINTSTS */
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	/* Read GINTSTS */
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+//      usleep(100000);
-+//      mdelay(100);
-+	dwc_mdelay(1);
-+
-+	/*
-+	 * Send handshake packet
-+	 */
-+
-+	/* Read HAINT */
-+	haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+	/* Read HCINT */
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+	/* Read HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+	/* Clear HCINT */
-+	DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+	/* Clear HAINT */
-+	DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+	/* Clear GINTSTS */
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	/* Read GINTSTS */
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/* Make sure channel is disabled */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	if (hcchar.b.chen) {
-+		hcchar.b.chdis = 1;
-+		hcchar.b.chen = 1;
-+		DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+		//sleep(1);
-+		dwc_mdelay(1000);
-+
-+		/* Read GINTSTS */
-+		gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+		/* Read HAINT */
-+		haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+		/* Read HCINT */
-+		hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+		/* Read HCCHAR */
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+		/* Clear HCINT */
-+		DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+		/* Clear HAINT */
-+		DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+		/* Clear GINTSTS */
-+		DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	}
-+
-+	/* Set HCTSIZ */
-+	hctsiz.d32 = 0;
-+	hctsiz.b.xfersize = 0;
-+	hctsiz.b.pktcnt = 1;
-+	hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
-+	DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
-+
-+	/* Set HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+	hcchar.b.epdir = 0;
-+	hcchar.b.epnum = 0;
-+	hcchar.b.mps = 8;
-+	hcchar.b.chen = 1;
-+	DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
-+
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+
-+	/* Wait for host channel interrupt */
-+	do {
-+		gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+	} while (gintsts.b.hcintr == 0);
-+
-+	/* Disable HCINTs */
-+	DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
-+
-+	/* Disable HAINTs */
-+	DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
-+
-+	/* Read HAINT */
-+	haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
-+
-+	/* Read HCINT */
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+
-+	/* Read HCCHAR */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+
-+	/* Clear HCINT */
-+	DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
-+
-+	/* Clear HAINT */
-+	DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
-+
-+	/* Clear GINTSTS */
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	/* Read GINTSTS */
-+	gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
-+}
-+#endif
-+
-+/** Handles hub class-specific requests. */
-+int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
-+			    uint16_t typeReq,
-+			    uint16_t wValue,
-+			    uint16_t wIndex, uint8_t * buf, uint16_t wLength)
-+{
-+	int retval = 0;
-+
-+	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+	usb_hub_descriptor_t *hub_desc;
-+	hprt0_data_t hprt0 = {.d32 = 0 };
-+
-+	uint32_t port_status;
-+
-+	switch (typeReq) {
-+	case UCR_CLEAR_HUB_FEATURE:
-+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+			    "ClearHubFeature 0x%x\n", wValue);
-+		switch (wValue) {
-+		case UHF_C_HUB_LOCAL_POWER:
-+		case UHF_C_HUB_OVER_CURRENT:
-+			/* Nothing required here */
-+			break;
-+		default:
-+			retval = -DWC_E_INVALID;
-+			DWC_ERROR("DWC OTG HCD - "
-+				  "ClearHubFeature request %xh unknown\n",
-+				  wValue);
-+		}
-+		break;
-+	case UCR_CLEAR_PORT_FEATURE:
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+		if (wValue != UHF_PORT_L1)
-+#endif
-+			if (!wIndex || wIndex > 1)
-+				goto error;
-+
-+		switch (wValue) {
-+		case UHF_PORT_ENABLE:
-+			DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
-+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+			hprt0.b.prtena = 1;
-+			DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+			break;
-+		case UHF_PORT_SUSPEND:
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
-+
-+			if (core_if->power_down == 2) {
-+				dwc_otg_host_hibernation_restore(core_if, 0, 0);
-+			} else {
-+				DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+				dwc_mdelay(5);
-+
-+				hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+				hprt0.b.prtres = 1;
-+				DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+				hprt0.b.prtsusp = 0;
-+				/* Clear Resume bit */
-+				dwc_mdelay(100);
-+				hprt0.b.prtres = 0;
-+				DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+			}
-+			break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+		case UHF_PORT_L1:
-+			{
-+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+				glpmcfg_data_t lpmcfg = {.d32 = 0 };
-+
-+				lpmcfg.d32 =
-+				    DWC_READ_REG32(&core_if->
-+						   core_global_regs->glpmcfg);
-+				lpmcfg.b.en_utmi_sleep = 0;
-+				lpmcfg.b.hird_thres &= (~(1 << 4));
-+				lpmcfg.b.prt_sleep_sts = 1;
-+				DWC_WRITE_REG32(&core_if->
-+						core_global_regs->glpmcfg,
-+						lpmcfg.d32);
-+
-+				/* Clear Enbl_L1Gating bit. */
-+				pcgcctl.b.enbl_sleep_gating = 1;
-+				DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
-+						 0);
-+
-+				dwc_mdelay(5);
-+
-+				hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+				hprt0.b.prtres = 1;
-+				DWC_WRITE_REG32(core_if->host_if->hprt0,
-+						hprt0.d32);
-+				/* This bit will be cleared in wakeup interrupt handle */
-+				break;
-+			}
-+#endif
-+		case UHF_PORT_POWER:
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_POWER\n");
-+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+			hprt0.b.prtpwr = 0;
-+			DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+			break;
-+		case UHF_PORT_INDICATOR:
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
-+			/* Port inidicator not supported */
-+			break;
-+		case UHF_C_PORT_CONNECTION:
-+			/* Clears drivers internal connect status change
-+			 * flag */
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
-+			dwc_otg_hcd->flags.b.port_connect_status_change = 0;
-+			break;
-+		case UHF_C_PORT_RESET:
-+			/* Clears the driver's internal Port Reset Change
-+			 * flag */
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
-+			dwc_otg_hcd->flags.b.port_reset_change = 0;
-+			break;
-+		case UHF_C_PORT_ENABLE:
-+			/* Clears the driver's internal Port
-+			 * Enable/Disable Change flag */
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
-+			dwc_otg_hcd->flags.b.port_enable_change = 0;
-+			break;
-+		case UHF_C_PORT_SUSPEND:
-+			/* Clears the driver's internal Port Suspend
-+			 * Change flag, which is set when resume signaling on
-+			 * the host port is complete */
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
-+			dwc_otg_hcd->flags.b.port_suspend_change = 0;
-+			break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+		case UHF_C_PORT_L1:
-+			dwc_otg_hcd->flags.b.port_l1_change = 0;
-+			break;
-+#endif
-+		case UHF_C_PORT_OVER_CURRENT:
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
-+			dwc_otg_hcd->flags.b.port_over_current_change = 0;
-+			break;
-+		default:
-+			retval = -DWC_E_INVALID;
-+			DWC_ERROR("DWC OTG HCD - "
-+				  "ClearPortFeature request %xh "
-+				  "unknown or unsupported\n", wValue);
-+		}
-+		break;
-+	case UCR_GET_HUB_DESCRIPTOR:
-+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+			    "GetHubDescriptor\n");
-+		hub_desc = (usb_hub_descriptor_t *) buf;
-+		hub_desc->bDescLength = 9;
-+		hub_desc->bDescriptorType = 0x29;
-+		hub_desc->bNbrPorts = 1;
-+		USETW(hub_desc->wHubCharacteristics, 0x08);
-+		hub_desc->bPwrOn2PwrGood = 1;
-+		hub_desc->bHubContrCurrent = 0;
-+		hub_desc->DeviceRemovable[0] = 0;
-+		hub_desc->DeviceRemovable[1] = 0xff;
-+		break;
-+	case UCR_GET_HUB_STATUS:
-+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+			    "GetHubStatus\n");
-+		DWC_MEMSET(buf, 0, 4);
-+		break;
-+	case UCR_GET_PORT_STATUS:
-+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+			    "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
-+			    wIndex, dwc_otg_hcd->flags.d32);
-+		if (!wIndex || wIndex > 1)
-+			goto error;
-+
-+		port_status = 0;
-+
-+		if (dwc_otg_hcd->flags.b.port_connect_status_change)
-+			port_status |= (1 << UHF_C_PORT_CONNECTION);
-+
-+		if (dwc_otg_hcd->flags.b.port_enable_change)
-+			port_status |= (1 << UHF_C_PORT_ENABLE);
-+
-+		if (dwc_otg_hcd->flags.b.port_suspend_change)
-+			port_status |= (1 << UHF_C_PORT_SUSPEND);
-+
-+		if (dwc_otg_hcd->flags.b.port_l1_change)
-+			port_status |= (1 << UHF_C_PORT_L1);
-+
-+		if (dwc_otg_hcd->flags.b.port_reset_change) {
-+			port_status |= (1 << UHF_C_PORT_RESET);
-+		}
-+
-+		if (dwc_otg_hcd->flags.b.port_over_current_change) {
-+			DWC_WARN("Overcurrent change detected\n");
-+			port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
-+		}
-+
-+		if (!dwc_otg_hcd->flags.b.port_connect_status) {
-+			/*
-+			 * The port is disconnected, which means the core is
-+			 * either in device mode or it soon will be. Just
-+			 * return 0's for the remainder of the port status
-+			 * since the port register can't be read if the core
-+			 * is in device mode.
-+			 */
-+			*((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
-+			break;
-+		}
-+
-+		hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
-+		DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
-+
-+		if (hprt0.b.prtconnsts)
-+			port_status |= (1 << UHF_PORT_CONNECTION);
-+
-+		if (hprt0.b.prtena)
-+			port_status |= (1 << UHF_PORT_ENABLE);
-+
-+		if (hprt0.b.prtsusp)
-+			port_status |= (1 << UHF_PORT_SUSPEND);
-+
-+		if (hprt0.b.prtovrcurract)
-+			port_status |= (1 << UHF_PORT_OVER_CURRENT);
-+
-+		if (hprt0.b.prtrst)
-+			port_status |= (1 << UHF_PORT_RESET);
-+
-+		if (hprt0.b.prtpwr)
-+			port_status |= (1 << UHF_PORT_POWER);
-+
-+		if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
-+			port_status |= (1 << UHF_PORT_HIGH_SPEED);
-+		else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
-+			port_status |= (1 << UHF_PORT_LOW_SPEED);
-+
-+		if (hprt0.b.prttstctl)
-+			port_status |= (1 << UHF_PORT_TEST);
-+		if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
-+			port_status |= (1 << UHF_PORT_L1);
-+		}
-+		/*
-+		   For Synopsys HW emulation of Power down wkup_control asserts the
-+		   hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
-+		   We intentionally tell the software that port is in L2Suspend state.
-+		   Only for STE.
-+		*/
-+		if ((core_if->power_down == 2)
-+		    && (core_if->hibernation_suspend == 1)) {
-+			port_status |= (1 << UHF_PORT_SUSPEND);
-+		}
-+		/* USB_PORT_FEAT_INDICATOR unsupported always 0 */
-+
-+		*((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
-+
-+		break;
-+	case UCR_SET_HUB_FEATURE:
-+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+			    "SetHubFeature\n");
-+		/* No HUB features supported */
-+		break;
-+	case UCR_SET_PORT_FEATURE:
-+		if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
-+			goto error;
-+
-+		if (!dwc_otg_hcd->flags.b.port_connect_status) {
-+			/*
-+			 * The port is disconnected, which means the core is
-+			 * either in device mode or it soon will be. Just
-+			 * return without doing anything since the port
-+			 * register can't be written if the core is in device
-+			 * mode.
-+			 */
-+			break;
-+		}
-+
-+		switch (wValue) {
-+		case UHF_PORT_SUSPEND:
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
-+			if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
-+				goto error;
-+			}
-+			if (core_if->power_down == 2) {
-+				int timeout = 300;
-+				dwc_irqflags_t flags;
-+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+				gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+				gusbcfg_data_t gusbcfg = {.d32 = 0 };
-+#ifdef DWC_DEV_SRPCAP
-+				int32_t otg_cap_param = core_if->core_params->otg_cap;
-+#endif
-+				DWC_PRINTF("Preparing for complete power-off\n");
-+
-+				/* Save registers before hibernation */
-+				dwc_otg_save_global_regs(core_if);
-+				dwc_otg_save_host_regs(core_if);
-+
-+				hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+				hprt0.b.prtsusp = 1;
-+				hprt0.b.prtena = 0;
-+				DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+				/* Spin hprt0.b.prtsusp to became 1 */
-+				do {
-+					hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+					if (hprt0.b.prtsusp) {
-+						break;
-+					}
-+					dwc_mdelay(1);
-+				} while (--timeout);
-+				if (!timeout) {
-+					DWC_WARN("Suspend wasn't genereted\n");
-+				}
-+				dwc_udelay(10);
-+
-+				/*
-+				 * We need to disable interrupts to prevent servicing of any IRQ
-+				 * during going to hibernation
-+				 */
-+				DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+				core_if->lx_state = DWC_OTG_L2;
-+#ifdef DWC_DEV_SRPCAP
-+				hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+				hprt0.b.prtpwr = 0;
-+				hprt0.b.prtena = 0;
-+				DWC_WRITE_REG32(core_if->host_if->hprt0,
-+						hprt0.d32);
-+#endif
-+				gusbcfg.d32 =
-+				    DWC_READ_REG32(&core_if->core_global_regs->
-+						   gusbcfg);
-+				if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+					/* ULPI interface */
-+					/* Suspend the Phy Clock */
-+					pcgcctl.d32 = 0;
-+					pcgcctl.b.stoppclk = 1;
-+					DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+							 pcgcctl.d32);
-+					dwc_udelay(10);
-+					gpwrdn.b.pmuactv = 1;
-+					DWC_MODIFY_REG32(&core_if->
-+							 core_global_regs->
-+							 gpwrdn, 0, gpwrdn.d32);
-+				} else {
-+					/* UTMI+ Interface */
-+					gpwrdn.b.pmuactv = 1;
-+					DWC_MODIFY_REG32(&core_if->
-+							 core_global_regs->
-+							 gpwrdn, 0, gpwrdn.d32);
-+					dwc_udelay(10);
-+					pcgcctl.b.stoppclk = 1;
-+					DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
-+					dwc_udelay(10);
-+				}
-+#ifdef DWC_DEV_SRPCAP
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.dis_vbus = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+#endif
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pmuintsel = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+				dwc_udelay(10);
-+
-+				gpwrdn.d32 = 0;
-+#ifdef DWC_DEV_SRPCAP
-+				gpwrdn.b.srp_det_msk = 1;
-+#endif
-+				gpwrdn.b.disconn_det_msk = 1;
-+				gpwrdn.b.lnstchng_msk = 1;
-+				gpwrdn.b.sts_chngint_msk = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+				dwc_udelay(10);
-+
-+				/* Enable Power Down Clamp and all interrupts in GPWRDN */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pwrdnclmp = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+				dwc_udelay(10);
-+
-+				/* Switch off VDD */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pwrdnswtch = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+
-+#ifdef DWC_DEV_SRPCAP
-+				if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
-+				{
-+					core_if->pwron_timer_started = 1;
-+					DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
-+				}
-+#endif
-+				/* Save gpwrdn register for further usage if stschng interrupt */
-+				core_if->gr_backup->gpwrdn_local =
-+						DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
-+
-+				/* Set flag to indicate that we are in hibernation */
-+				core_if->hibernation_suspend = 1;
-+				DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
-+
-+				DWC_PRINTF("Host hibernation completed\n");
-+				// Exit from case statement
-+				break;
-+
-+			}
-+			if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
-+			    dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
-+				gotgctl_data_t gotgctl = {.d32 = 0 };
-+				gotgctl.b.hstsethnpen = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gotgctl, 0, gotgctl.d32);
-+				core_if->op_state = A_SUSPEND;
-+			}
-+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+			hprt0.b.prtsusp = 1;
-+			DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+			{
-+				dwc_irqflags_t flags;
-+				/* Update lx_state */
-+				DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+				core_if->lx_state = DWC_OTG_L2;
-+				DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+			}
-+			/* Suspend the Phy Clock */
-+			{
-+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+				pcgcctl.b.stoppclk = 1;
-+				DWC_MODIFY_REG32(core_if->pcgcctl, 0,
-+						 pcgcctl.d32);
-+				dwc_udelay(10);
-+			}
-+
-+			/* For HNP the bus must be suspended for at least 200ms. */
-+			if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
-+				pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+				pcgcctl.b.stoppclk = 1;
-+                DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+				dwc_mdelay(200);
-+			}
-+
-+			/** @todo - check how sw can wait for 1 sec to check asesvld??? */
-+#if 0 //vahrama !!!!!!!!!!!!!!!!!!
-+			if (core_if->adp_enable) {
-+				gotgctl_data_t gotgctl = {.d32 = 0 };
-+				gpwrdn_data_t gpwrdn;
-+
-+				while (gotgctl.b.asesvld == 1) {
-+					gotgctl.d32 =
-+					    DWC_READ_REG32(&core_if->
-+							   core_global_regs->
-+							   gotgctl);
-+					dwc_mdelay(100);
-+				}
-+
-+				/* Enable Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pmuactv = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+
-+				/* Unmask SRP detected interrupt from Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.srp_det_msk = 1;
-+				DWC_MODIFY_REG32(&core_if->core_global_regs->
-+						 gpwrdn, 0, gpwrdn.d32);
-+
-+				dwc_otg_adp_probe_start(core_if);
-+			}
-+#endif
-+			break;
-+		case UHF_PORT_POWER:
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "SetPortFeature - USB_PORT_FEAT_POWER\n");
-+			hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+			hprt0.b.prtpwr = 1;
-+			DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+			break;
-+		case UHF_PORT_RESET:
-+			if ((core_if->power_down == 2)
-+			    && (core_if->hibernation_suspend == 1)) {
-+				/* If we are going to exit from Hibernated
-+				 * state via USB RESET.
-+				 */
-+				dwc_otg_host_hibernation_restore(core_if, 0, 1);
-+			} else {
-+				hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+
-+				DWC_DEBUGPL(DBG_HCD,
-+					    "DWC OTG HCD HUB CONTROL - "
-+					    "SetPortFeature - USB_PORT_FEAT_RESET\n");
-+				{
-+					pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+					pcgcctl.b.enbl_sleep_gating = 1;
-+					pcgcctl.b.stoppclk = 1;
-+					DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
-+					DWC_WRITE_REG32(core_if->pcgcctl, 0);
-+				}
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+				{
-+					glpmcfg_data_t lpmcfg;
-+					lpmcfg.d32 =
-+						DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+					if (lpmcfg.b.prt_sleep_sts) {
-+						lpmcfg.b.en_utmi_sleep = 0;
-+						lpmcfg.b.hird_thres &= (~(1 << 4));
-+						DWC_WRITE_REG32
-+						    (&core_if->core_global_regs->glpmcfg,
-+						     lpmcfg.d32);
-+						dwc_mdelay(1);
-+					}
-+				}
-+#endif
-+				hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+				/* Clear suspend bit if resetting from suspended state. */
-+				hprt0.b.prtsusp = 0;
-+				/* When B-Host the Port reset bit is set in
-+				 * the Start HCD Callback function, so that
-+				 * the reset is started within 1ms of the HNP
-+				 * success interrupt. */
-+				if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
-+					hprt0.b.prtpwr = 1;
-+					hprt0.b.prtrst = 1;
-+					DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
-+					DWC_WRITE_REG32(core_if->host_if->hprt0,
-+							hprt0.d32);
-+				}
-+				/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
-+				dwc_mdelay(60);
-+				hprt0.b.prtrst = 0;
-+				DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+				core_if->lx_state = DWC_OTG_L0;	/* Now back to the on state */
-+			}
-+			break;
-+#ifdef DWC_HS_ELECT_TST
-+		case UHF_PORT_TEST:
-+			{
-+				uint32_t t;
-+				gintmsk_data_t gintmsk;
-+
-+				t = (wIndex >> 8);	/* MSB wIndex USB */
-+				DWC_DEBUGPL(DBG_HCD,
-+					    "DWC OTG HCD HUB CONTROL - "
-+					    "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
-+					    t);
-+				DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
-+				if (t < 6) {
-+					hprt0.d32 = dwc_otg_read_hprt0(core_if);
-+					hprt0.b.prttstctl = t;
-+					DWC_WRITE_REG32(core_if->host_if->hprt0,
-+							hprt0.d32);
-+				} else {
-+					/* Setup global vars with reg addresses (quick and
-+					 * dirty hack, should be cleaned up)
-+					 */
-+					global_regs = core_if->core_global_regs;
-+					hc_global_regs =
-+					    core_if->host_if->host_global_regs;
-+					hc_regs =
-+					    (dwc_otg_hc_regs_t *) ((char *)
-+								   global_regs +
-+								   0x500);
-+					data_fifo =
-+					    (uint32_t *) ((char *)global_regs +
-+							  0x1000);
-+
-+					if (t == 6) {	/* HS_HOST_PORT_SUSPEND_RESUME */
-+						/* Save current interrupt mask */
-+						gintmsk.d32 =
-+						    DWC_READ_REG32
-+						    (&global_regs->gintmsk);
-+
-+						/* Disable all interrupts while we muck with
-+						 * the hardware directly
-+						 */
-+						DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+						/* 15 second delay per the test spec */
-+						dwc_mdelay(15000);
-+
-+						/* Drive suspend on the root port */
-+						hprt0.d32 =
-+						    dwc_otg_read_hprt0(core_if);
-+						hprt0.b.prtsusp = 1;
-+						hprt0.b.prtres = 0;
-+						DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+						/* 15 second delay per the test spec */
-+						dwc_mdelay(15000);
-+
-+						/* Drive resume on the root port */
-+						hprt0.d32 =
-+						    dwc_otg_read_hprt0(core_if);
-+						hprt0.b.prtsusp = 0;
-+						hprt0.b.prtres = 1;
-+						DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+						dwc_mdelay(100);
-+
-+						/* Clear the resume bit */
-+						hprt0.b.prtres = 0;
-+						DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
-+
-+						/* Restore interrupts */
-+						DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+					} else if (t == 7) {	/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
-+						/* Save current interrupt mask */
-+						gintmsk.d32 =
-+						    DWC_READ_REG32
-+						    (&global_regs->gintmsk);
-+
-+						/* Disable all interrupts while we muck with
-+						 * the hardware directly
-+						 */
-+						DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+						/* 15 second delay per the test spec */
-+						dwc_mdelay(15000);
-+
-+						/* Send the Setup packet */
-+						do_setup();
-+
-+						/* 15 second delay so nothing else happens for awhile */
-+						dwc_mdelay(15000);
-+
-+						/* Restore interrupts */
-+						DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+					} else if (t == 8) {	/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
-+						/* Save current interrupt mask */
-+						gintmsk.d32 =
-+						    DWC_READ_REG32
-+						    (&global_regs->gintmsk);
-+
-+						/* Disable all interrupts while we muck with
-+						 * the hardware directly
-+						 */
-+						DWC_WRITE_REG32(&global_regs->gintmsk, 0);
-+
-+						/* Send the Setup packet */
-+						do_setup();
-+
-+						/* 15 second delay so nothing else happens for awhile */
-+						dwc_mdelay(15000);
-+
-+						/* Send the In and Ack packets */
-+						do_in_ack();
-+
-+						/* 15 second delay so nothing else happens for awhile */
-+						dwc_mdelay(15000);
-+
-+						/* Restore interrupts */
-+						DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
-+					}
-+				}
-+				break;
-+			}
-+#endif /* DWC_HS_ELECT_TST */
-+
-+		case UHF_PORT_INDICATOR:
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
-+				    "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
-+			/* Not supported */
-+			break;
-+		default:
-+			retval = -DWC_E_INVALID;
-+			DWC_ERROR("DWC OTG HCD - "
-+				  "SetPortFeature request %xh "
-+				  "unknown or unsupported\n", wValue);
-+			break;
-+		}
-+		break;
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	case UCR_SET_AND_TEST_PORT_FEATURE:
-+		if (wValue != UHF_PORT_L1) {
-+			goto error;
-+		}
-+		{
-+			int portnum, hird, devaddr, remwake;
-+			glpmcfg_data_t lpmcfg;
-+			uint32_t time_usecs;
-+			gintsts_data_t gintsts;
-+			gintmsk_data_t gintmsk;
-+
-+			if (!dwc_otg_get_param_lpm_enable(core_if)) {
-+				goto error;
-+			}
-+			if (wValue != UHF_PORT_L1 || wLength != 1) {
-+				goto error;
-+			}
-+			/* Check if the port currently is in SLEEP state */
-+			lpmcfg.d32 =
-+			    DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+			if (lpmcfg.b.prt_sleep_sts) {
-+				DWC_INFO("Port is already in sleep mode\n");
-+				buf[0] = 0;	/* Return success */
-+				break;
-+			}
-+
-+			portnum = wIndex & 0xf;
-+			hird = (wIndex >> 4) & 0xf;
-+			devaddr = (wIndex >> 8) & 0x7f;
-+			remwake = (wIndex >> 15);
-+
-+			if (portnum != 1) {
-+				retval = -DWC_E_INVALID;
-+				DWC_WARN
-+				    ("Wrong port number(%d) in SetandTestPortFeature request\n",
-+				     portnum);
-+				break;
-+			}
-+
-+			DWC_PRINTF
-+			    ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
-+			     portnum, hird, devaddr, remwake);
-+			/* Disable LPM interrupt */
-+			gintmsk.d32 = 0;
-+			gintmsk.b.lpmtranrcvd = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+					 gintmsk.d32, 0);
-+
-+			if (dwc_otg_hcd_send_lpm
-+			    (dwc_otg_hcd, devaddr, hird, remwake)) {
-+				retval = -DWC_E_INVALID;
-+				break;
-+			}
-+
-+			time_usecs = 10 * (lpmcfg.b.retry_count + 1);
-+			/* We will consider timeout if time_usecs microseconds pass,
-+			 * and we don't receive LPM transaction status.
-+			 * After receiving non-error responce(ACK/NYET/STALL) from device,
-+			 *  core will set lpmtranrcvd bit.
-+			 */
-+			do {
-+				gintsts.d32 =
-+				    DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+				if (gintsts.b.lpmtranrcvd) {
-+					break;
-+				}
-+				dwc_udelay(1);
-+			} while (--time_usecs);
-+			/* lpm_int bit will be cleared in LPM interrupt handler */
-+
-+			/* Now fill status
-+			 * 0x00 - Success
-+			 * 0x10 - NYET
-+			 * 0x11 - Timeout
-+			 */
-+			if (!gintsts.b.lpmtranrcvd) {
-+				buf[0] = 0x3;	/* Completion code is Timeout */
-+				dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
-+			} else {
-+				lpmcfg.d32 =
-+				    DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+				if (lpmcfg.b.lpm_resp == 0x3) {
-+					/* ACK responce from the device */
-+					buf[0] = 0x00;	/* Success */
-+				} else if (lpmcfg.b.lpm_resp == 0x2) {
-+					/* NYET responce from the device */
-+					buf[0] = 0x2;
-+				} else {
-+					/* Otherwise responce with Timeout */
-+					buf[0] = 0x3;
-+				}
-+			}
-+			DWC_PRINTF("Device responce to LPM trans is %x\n",
-+				   lpmcfg.b.lpm_resp);
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
-+					 gintmsk.d32);
-+
-+			break;
-+		}
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+	default:
-+error:
-+		retval = -DWC_E_INVALID;
-+		DWC_WARN("DWC OTG HCD - "
-+			 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
-+			 typeReq, wIndex, wValue);
-+		break;
-+	}
-+
-+	return retval;
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/** Returns index of host channel to perform LPM transaction. */
-+int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
-+{
-+	dwc_otg_core_if_t *core_if = hcd->core_if;
-+	dwc_hc_t *hc;
-+	hcchar_data_t hcchar;
-+	gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+	if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
-+		DWC_PRINTF("No free channel to select for LPM transaction\n");
-+		return -1;
-+	}
-+
-+	hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
-+
-+	/* Mask host channel interrupts. */
-+	gintmsk.b.hcintr = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
-+
-+	/* Fill fields that core needs for LPM transaction */
-+	hcchar.b.devaddr = devaddr;
-+	hcchar.b.epnum = 0;
-+	hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
-+	hcchar.b.mps = 64;
-+	hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
-+	hcchar.b.epdir = 0;	/* OUT */
-+	DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
-+			hcchar.d32);
-+
-+	/* Remove the host channel from the free list. */
-+	DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+	DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
-+
-+	return hc->hc_num;
-+}
-+
-+/** Release hc after performing LPM transaction */
-+void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
-+{
-+	dwc_hc_t *hc;
-+	glpmcfg_data_t lpmcfg;
-+	uint8_t hc_num;
-+
-+	lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
-+	hc_num = lpmcfg.b.lpm_chan_index;
-+
-+	hc = hcd->hc_ptr_array[hc_num];
-+
-+	DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
-+	/* Return host channel to free list */
-+	DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+}
-+
-+int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
-+			 uint8_t bRemoteWake)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	pcgcctl_data_t pcgcctl = {.d32 = 0 };
-+	int channel;
-+
-+	channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
-+	if (channel < 0) {
-+		return channel;
-+	}
-+
-+	pcgcctl.b.enbl_sleep_gating = 1;
-+	DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
-+
-+	/* Read LPM config register */
-+	lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
-+
-+	/* Program LPM transaction fields */
-+	lpmcfg.b.rem_wkup_en = bRemoteWake;
-+	lpmcfg.b.hird = hird;
-+	lpmcfg.b.hird_thres = 0x1c;
-+	lpmcfg.b.lpm_chan_index = channel;
-+	lpmcfg.b.en_utmi_sleep = 1;
-+	/* Program LPM config register */
-+	DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+	/* Send LPM transaction */
-+	lpmcfg.b.send_lpm = 1;
-+	DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+	return 0;
-+}
-+
-+#endif /* CONFIG_USB_DWC_OTG_LPM */
-+
-+int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
-+{
-+	int retval;
-+
-+	if (port != 1) {
-+		return -DWC_E_INVALID;
-+	}
-+
-+	retval = (hcd->flags.b.port_connect_status_change ||
-+		  hcd->flags.b.port_reset_change ||
-+		  hcd->flags.b.port_enable_change ||
-+		  hcd->flags.b.port_suspend_change ||
-+		  hcd->flags.b.port_over_current_change);
-+#ifdef DEBUG
-+	if (retval) {
-+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
-+			    " Root port status changed\n");
-+		DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
-+			    hcd->flags.b.port_connect_status_change);
-+		DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
-+			    hcd->flags.b.port_reset_change);
-+		DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
-+			    hcd->flags.b.port_enable_change);
-+		DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
-+			    hcd->flags.b.port_suspend_change);
-+		DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
-+			    hcd->flags.b.port_over_current_change);
-+	}
-+#endif
-+	return retval;
-+}
-+
-+int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	hfnum_data_t hfnum;
-+	hfnum.d32 =
-+	    DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
-+			   hfnum);
-+
-+#ifdef DEBUG_SOF
-+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
-+		    hfnum.b.frnum);
-+#endif
-+	return hfnum.b.frnum;
-+}
-+
-+int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
-+		      struct dwc_otg_hcd_function_ops *fops)
-+{
-+	int retval = 0;
-+
-+	hcd->fops = fops;
-+	if (!dwc_otg_is_device_mode(hcd->core_if) &&
-+		(!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
-+		dwc_otg_hcd_reinit(hcd);
-+	} else {
-+		retval = -DWC_E_NO_DEVICE;
-+	}
-+
-+	return retval;
-+}
-+
-+void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
-+{
-+	return hcd->priv;
-+}
-+
-+void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
-+{
-+	hcd->priv = priv_data;
-+}
-+
-+uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
-+{
-+	return hcd->otg_port;
-+}
-+
-+uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
-+{
-+	uint32_t is_b_host;
-+	if (hcd->core_if->op_state == B_HOST) {
-+		is_b_host = 1;
-+	} else {
-+		is_b_host = 0;
-+	}
-+
-+	return is_b_host;
-+}
-+
-+dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
-+					 int iso_desc_count, int atomic_alloc)
-+{
-+	dwc_otg_hcd_urb_t *dwc_otg_urb;
-+	uint32_t size;
-+
-+	size =
-+	    sizeof(*dwc_otg_urb) +
-+	    iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
-+	if (atomic_alloc)
-+		dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
-+	else
-+		dwc_otg_urb = DWC_ALLOC(size);
-+
-+        if (dwc_otg_urb)
-+		dwc_otg_urb->packet_count = iso_desc_count;
-+        else {
-+		DWC_ERROR("**** DWC OTG HCD URB alloc - "
-+			"%salloc of %db failed\n",
-+			atomic_alloc?"atomic ":"", size);
-+	}
-+	return dwc_otg_urb;
-+}
-+
-+void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+				  uint8_t dev_addr, uint8_t ep_num,
-+				  uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
-+{
-+	dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
-+			      ep_type, ep_dir, mps);
-+#if 0
-+	DWC_PRINTF
-+	    ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
-+	     dev_addr, ep_num, ep_dir, ep_type, mps);
-+#endif
-+}
-+
-+void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+				void *urb_handle, void *buf, dwc_dma_t dma,
-+				uint32_t buflen, void *setup_packet,
-+				dwc_dma_t setup_dma, uint32_t flags,
-+				uint16_t interval)
-+{
-+	dwc_otg_urb->priv = urb_handle;
-+	dwc_otg_urb->buf = buf;
-+	dwc_otg_urb->dma = dma;
-+	dwc_otg_urb->length = buflen;
-+	dwc_otg_urb->setup_packet = setup_packet;
-+	dwc_otg_urb->setup_dma = setup_dma;
-+	dwc_otg_urb->flags = flags;
-+	dwc_otg_urb->interval = interval;
-+	dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+	return dwc_otg_urb->status;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+	return dwc_otg_urb->actual_length;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
-+{
-+	return dwc_otg_urb->error_count;
-+}
-+
-+void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+					 int desc_num, uint32_t offset,
-+					 uint32_t length)
-+{
-+	dwc_otg_urb->iso_descs[desc_num].offset = offset;
-+	dwc_otg_urb->iso_descs[desc_num].length = length;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+					     int desc_num)
-+{
-+	return dwc_otg_urb->iso_descs[desc_num].status;
-+}
-+
-+uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
-+						    dwc_otg_urb, int desc_num)
-+{
-+	return dwc_otg_urb->iso_descs[desc_num].actual_length;
-+}
-+
-+int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+	int allocated = 0;
-+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+
-+	if (qh) {
-+		if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+			allocated = 1;
-+		}
-+	}
-+	return allocated;
-+}
-+
-+int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+	int freed = 0;
-+	DWC_ASSERT(qh, "qh is not allocated\n");
-+
-+	if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+		freed = 1;
-+	}
-+
-+	return freed;
-+}
-+
-+uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
-+{
-+	dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
-+	DWC_ASSERT(qh, "qh is not allocated\n");
-+	return qh->usecs;
-+}
-+
-+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
-+{
-+#ifdef DEBUG
-+	int num_channels;
-+	int i;
-+	gnptxsts_data_t np_tx_status;
-+	hptxsts_data_t p_tx_status;
-+
-+	num_channels = hcd->core_if->core_params->host_channels;
-+	DWC_PRINTF("\n");
-+	DWC_PRINTF
-+	    ("************************************************************\n");
-+	DWC_PRINTF("HCD State:\n");
-+	DWC_PRINTF("  Num channels: %d\n", num_channels);
-+	for (i = 0; i < num_channels; i++) {
-+		dwc_hc_t *hc = hcd->hc_ptr_array[i];
-+		DWC_PRINTF("  Channel %d:\n", i);
-+		DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
-+			   hc->dev_addr, hc->ep_num, hc->ep_is_in);
-+		DWC_PRINTF("    speed: %d\n", hc->speed);
-+		DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
-+		DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
-+		DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
-+		DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
-+		DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
-+		DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
-+		DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
-+		DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
-+		DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
-+		DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
-+		DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
-+		DWC_PRINTF("    do_split: %d\n", hc->do_split);
-+		DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
-+		DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
-+		DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
-+		DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
-+		DWC_PRINTF("    requests: %d\n", hc->requests);
-+		DWC_PRINTF("    qh: %p\n", hc->qh);
-+		if (hc->xfer_started) {
-+			hfnum_data_t hfnum;
-+			hcchar_data_t hcchar;
-+			hctsiz_data_t hctsiz;
-+			hcint_data_t hcint;
-+			hcintmsk_data_t hcintmsk;
-+			hfnum.d32 =
-+			    DWC_READ_REG32(&hcd->core_if->
-+					   host_if->host_global_regs->hfnum);
-+			hcchar.d32 =
-+			    DWC_READ_REG32(&hcd->core_if->host_if->
-+					   hc_regs[i]->hcchar);
-+			hctsiz.d32 =
-+			    DWC_READ_REG32(&hcd->core_if->host_if->
-+					   hc_regs[i]->hctsiz);
-+			hcint.d32 =
-+			    DWC_READ_REG32(&hcd->core_if->host_if->
-+					   hc_regs[i]->hcint);
-+			hcintmsk.d32 =
-+			    DWC_READ_REG32(&hcd->core_if->host_if->
-+					   hc_regs[i]->hcintmsk);
-+			DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
-+			DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
-+			DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
-+			DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
-+			DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
-+		}
-+		if (hc->xfer_started && hc->qh) {
-+			dwc_otg_qtd_t *qtd;
-+			dwc_otg_hcd_urb_t *urb;
-+
-+			DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
-+				if (!qtd->in_process)
-+					break;
-+
-+				urb = qtd->urb;
-+			DWC_PRINTF("    URB Info:\n");
-+			DWC_PRINTF("      qtd: %p, urb: %p\n", qtd, urb);
-+			if (urb) {
-+				DWC_PRINTF("      Dev: %d, EP: %d %s\n",
-+					   dwc_otg_hcd_get_dev_addr(&urb->
-+								    pipe_info),
-+					   dwc_otg_hcd_get_ep_num(&urb->
-+								  pipe_info),
-+					   dwc_otg_hcd_is_pipe_in(&urb->
-+								  pipe_info) ?
-+					   "IN" : "OUT");
-+				DWC_PRINTF("      Max packet size: %d\n",
-+					   dwc_otg_hcd_get_mps(&urb->
-+							       pipe_info));
-+				DWC_PRINTF("      transfer_buffer: %p\n",
-+					   urb->buf);
-+				DWC_PRINTF("      transfer_dma: %p\n",
-+					   (void *)urb->dma);
-+				DWC_PRINTF("      transfer_buffer_length: %d\n",
-+					   urb->length);
-+					DWC_PRINTF("      actual_length: %d\n",
-+						   urb->actual_length);
-+				}
-+			}
-+		}
-+	}
-+	DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
-+	DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
-+	DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
-+	np_tx_status.d32 =
-+	    DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
-+	DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
-+		   np_tx_status.b.nptxqspcavail);
-+	DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
-+		   np_tx_status.b.nptxfspcavail);
-+	p_tx_status.d32 =
-+	    DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
-+	DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
-+		   p_tx_status.b.ptxqspcavail);
-+	DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
-+	dwc_otg_hcd_dump_frrem(hcd);
-+	dwc_otg_dump_global_registers(hcd->core_if);
-+	dwc_otg_dump_host_registers(hcd->core_if);
-+	DWC_PRINTF
-+	    ("************************************************************\n");
-+	DWC_PRINTF("\n");
-+#endif
-+}
-+
-+#ifdef DEBUG
-+void dwc_print_setup_data(uint8_t * setup)
-+{
-+	int i;
-+	if (CHK_DEBUG_LEVEL(DBG_HCD)) {
-+		DWC_PRINTF("Setup Data = MSB ");
-+		for (i = 7; i >= 0; i--)
-+			DWC_PRINTF("%02x ", setup[i]);
-+		DWC_PRINTF("\n");
-+		DWC_PRINTF("  bmRequestType Tranfer = %s\n",
-+			   (setup[0] & 0x80) ? "Device-to-Host" :
-+			   "Host-to-Device");
-+		DWC_PRINTF("  bmRequestType Type = ");
-+		switch ((setup[0] & 0x60) >> 5) {
-+		case 0:
-+			DWC_PRINTF("Standard\n");
-+			break;
-+		case 1:
-+			DWC_PRINTF("Class\n");
-+			break;
-+		case 2:
-+			DWC_PRINTF("Vendor\n");
-+			break;
-+		case 3:
-+			DWC_PRINTF("Reserved\n");
-+			break;
-+		}
-+		DWC_PRINTF("  bmRequestType Recipient = ");
-+		switch (setup[0] & 0x1f) {
-+		case 0:
-+			DWC_PRINTF("Device\n");
-+			break;
-+		case 1:
-+			DWC_PRINTF("Interface\n");
-+			break;
-+		case 2:
-+			DWC_PRINTF("Endpoint\n");
-+			break;
-+		case 3:
-+			DWC_PRINTF("Other\n");
-+			break;
-+		default:
-+			DWC_PRINTF("Reserved\n");
-+			break;
-+		}
-+		DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
-+		DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
-+		DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
-+		DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
-+	}
-+}
-+#endif
-+
-+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
-+{
-+#if 0
-+	DWC_PRINTF("Frame remaining at SOF:\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->frrem_samples, hcd->frrem_accum,
-+		   (hcd->frrem_samples > 0) ?
-+		   hcd->frrem_accum / hcd->frrem_samples : 0);
-+
-+	DWC_PRINTF("\n");
-+	DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->core_if->hfnum_7_samples,
-+		   hcd->core_if->hfnum_7_frrem_accum,
-+		   (hcd->core_if->hfnum_7_samples >
-+		    0) ? hcd->core_if->hfnum_7_frrem_accum /
-+		   hcd->core_if->hfnum_7_samples : 0);
-+	DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->core_if->hfnum_0_samples,
-+		   hcd->core_if->hfnum_0_frrem_accum,
-+		   (hcd->core_if->hfnum_0_samples >
-+		    0) ? hcd->core_if->hfnum_0_frrem_accum /
-+		   hcd->core_if->hfnum_0_samples : 0);
-+	DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->core_if->hfnum_other_samples,
-+		   hcd->core_if->hfnum_other_frrem_accum,
-+		   (hcd->core_if->hfnum_other_samples >
-+		    0) ? hcd->core_if->hfnum_other_frrem_accum /
-+		   hcd->core_if->hfnum_other_samples : 0);
-+
-+	DWC_PRINTF("\n");
-+	DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
-+		   (hcd->hfnum_7_samples_a > 0) ?
-+		   hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
-+	DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
-+		   (hcd->hfnum_0_samples_a > 0) ?
-+		   hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
-+	DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
-+		   (hcd->hfnum_other_samples_a > 0) ?
-+		   hcd->hfnum_other_frrem_accum_a /
-+		   hcd->hfnum_other_samples_a : 0);
-+
-+	DWC_PRINTF("\n");
-+	DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
-+		   (hcd->hfnum_7_samples_b > 0) ?
-+		   hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
-+	DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
-+		   (hcd->hfnum_0_samples_b > 0) ?
-+		   hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
-+	DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
-+	DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
-+		   hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
-+		   (hcd->hfnum_other_samples_b > 0) ?
-+		   hcd->hfnum_other_frrem_accum_b /
-+		   hcd->hfnum_other_samples_b : 0);
-+#endif
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
-@@ -0,0 +1,870 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
-+ * $Revision: #58 $
-+ * $Date: 2011/09/15 $
-+ * $Change: 1846647 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+#ifndef __DWC_HCD_H__
-+#define __DWC_HCD_H__
-+
-+#include "dwc_otg_os_dep.h"
-+#include "usb.h"
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_list.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_fiq_fsm.h"
-+#include "dwc_otg_driver.h"
-+
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the structures, constants, and interfaces for
-+ * the Host Contoller Driver (HCD).
-+ *
-+ * The Host Controller Driver (HCD) is responsible for translating requests
-+ * from the USB Driver into the appropriate actions on the DWC_otg controller.
-+ * It isolates the USBD from the specifics of the controller by providing an
-+ * API to the USBD.
-+ */
-+
-+struct dwc_otg_hcd_pipe_info {
-+	uint8_t dev_addr;
-+	uint8_t ep_num;
-+	uint8_t pipe_type;
-+	uint8_t pipe_dir;
-+	uint16_t mps;
-+};
-+
-+struct dwc_otg_hcd_iso_packet_desc {
-+	uint32_t offset;
-+	uint32_t length;
-+	uint32_t actual_length;
-+	uint32_t status;
-+};
-+
-+struct dwc_otg_qtd;
-+
-+struct dwc_otg_hcd_urb {
-+	void *priv;
-+	struct dwc_otg_qtd *qtd;
-+	void *buf;
-+	dwc_dma_t dma;
-+	void *setup_packet;
-+	dwc_dma_t setup_dma;
-+	uint32_t length;
-+	uint32_t actual_length;
-+	uint32_t status;
-+	uint32_t error_count;
-+	uint32_t packet_count;
-+	uint32_t flags;
-+	uint16_t interval;
-+	struct dwc_otg_hcd_pipe_info pipe_info;
-+	struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
-+};
-+
-+static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+	return pipe->ep_num;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
-+						*pipe)
-+{
-+	return pipe->pipe_type;
-+}
-+
-+static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+	return pipe->mps;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
-+					       *pipe)
-+{
-+	return pipe->dev_addr;
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
-+					       *pipe)
-+{
-+	return (pipe->pipe_type == UE_ISOCHRONOUS);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
-+					      *pipe)
-+{
-+	return (pipe->pipe_type == UE_INTERRUPT);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
-+					       *pipe)
-+{
-+	return (pipe->pipe_type == UE_BULK);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
-+						  *pipe)
-+{
-+	return (pipe->pipe_type == UE_CONTROL);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
-+{
-+	return (pipe->pipe_dir == UE_DIR_IN);
-+}
-+
-+static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
-+					      *pipe)
-+{
-+	return (!dwc_otg_hcd_is_pipe_in(pipe));
-+}
-+
-+static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
-+					 uint8_t devaddr, uint8_t ep_num,
-+					 uint8_t pipe_type, uint8_t pipe_dir,
-+					 uint16_t mps)
-+{
-+	pipe->dev_addr = devaddr;
-+	pipe->ep_num = ep_num;
-+	pipe->pipe_type = pipe_type;
-+	pipe->pipe_dir = pipe_dir;
-+	pipe->mps = mps;
-+}
-+
-+/**
-+ * Phases for control transfers.
-+ */
-+typedef enum dwc_otg_control_phase {
-+	DWC_OTG_CONTROL_SETUP,
-+	DWC_OTG_CONTROL_DATA,
-+	DWC_OTG_CONTROL_STATUS
-+} dwc_otg_control_phase_e;
-+
-+/** Transaction types. */
-+typedef enum dwc_otg_transaction_type {
-+	DWC_OTG_TRANSACTION_NONE          = 0,
-+	DWC_OTG_TRANSACTION_PERIODIC      = 1,
-+	DWC_OTG_TRANSACTION_NON_PERIODIC  = 2,
-+	DWC_OTG_TRANSACTION_ALL           = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC
-+} dwc_otg_transaction_type_e;
-+
-+struct dwc_otg_qh;
-+
-+/**
-+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
-+ * interrupt, or isochronous transfer. A single QTD is created for each URB
-+ * (of one of these types) submitted to the HCD. The transfer associated with
-+ * a QTD may require one or multiple transactions.
-+ *
-+ * A QTD is linked to a Queue Head, which is entered in either the
-+ * non-periodic or periodic schedule for execution. When a QTD is chosen for
-+ * execution, some or all of its transactions may be executed. After
-+ * execution, the state of the QTD is updated. The QTD may be retired if all
-+ * its transactions are complete or if an error occurred. Otherwise, it
-+ * remains in the schedule so more transactions can be executed later.
-+ */
-+typedef struct dwc_otg_qtd {
-+	/**
-+	 * Determines the PID of the next data packet for the data phase of
-+	 * control transfers. Ignored for other transfer types.<br>
-+	 * One of the following values:
-+	 *	- DWC_OTG_HC_PID_DATA0
-+	 *	- DWC_OTG_HC_PID_DATA1
-+	 */
-+	uint8_t data_toggle;
-+
-+	/** Current phase for control transfers (Setup, Data, or Status). */
-+	dwc_otg_control_phase_e control_phase;
-+
-+	/** Keep track of the current split type
-+	 * for FS/LS endpoints on a HS Hub */
-+	uint8_t complete_split;
-+
-+	/** How many bytes transferred during SSPLIT OUT */
-+	uint32_t ssplit_out_xfer_count;
-+
-+	/**
-+	 * Holds the number of bus errors that have occurred for a transaction
-+	 * within this transfer.
-+	 */
-+	uint8_t error_count;
-+
-+	/**
-+	 * Index of the next frame descriptor for an isochronous transfer. A
-+	 * frame descriptor describes the buffer position and length of the
-+	 * data to be transferred in the next scheduled (micro)frame of an
-+	 * isochronous transfer. It also holds status for that transaction.
-+	 * The frame index starts at 0.
-+	 */
-+	uint16_t isoc_frame_index;
-+
-+	/** Position of the ISOC split on full/low speed */
-+	uint8_t isoc_split_pos;
-+
-+	/** Position of the ISOC split in the buffer for the current frame */
-+	uint16_t isoc_split_offset;
-+
-+	/** URB for this transfer */
-+	struct dwc_otg_hcd_urb *urb;
-+
-+	struct dwc_otg_qh *qh;
-+
-+	/** This list of QTDs */
-+	 DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
-+
-+	/** Indicates if this QTD is currently processed by HW. */
-+	uint8_t in_process;
-+
-+	/** Number of DMA descriptors for this QTD */
-+	uint8_t n_desc;
-+
-+	/**
-+	 * Last activated frame(packet) index.
-+	 * Used in Descriptor DMA mode only.
-+	 */
-+	uint16_t isoc_frame_index_last;
-+
-+} dwc_otg_qtd_t;
-+
-+DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
-+
-+/**
-+ * A Queue Head (QH) holds the static characteristics of an endpoint and
-+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
-+ * be entered in either the non-periodic or periodic schedule.
-+ */
-+typedef struct dwc_otg_qh {
-+	/**
-+	 * Endpoint type.
-+	 * One of the following values:
-+	 *	- UE_CONTROL
-+	 *	- UE_BULK
-+	 *	- UE_INTERRUPT
-+	 *	- UE_ISOCHRONOUS
-+	 */
-+	uint8_t ep_type;
-+	uint8_t ep_is_in;
-+
-+	/** wMaxPacketSize Field of Endpoint Descriptor. */
-+	uint16_t maxp;
-+
-+	/**
-+	 * Device speed.
-+	 * One of the following values:
-+	 *	- DWC_OTG_EP_SPEED_LOW
-+	 *	- DWC_OTG_EP_SPEED_FULL
-+	 *	- DWC_OTG_EP_SPEED_HIGH
-+	 */
-+	uint8_t dev_speed;
-+
-+	/**
-+	 * Determines the PID of the next data packet for non-control
-+	 * transfers. Ignored for control transfers.<br>
-+	 * One of the following values:
-+	 *	- DWC_OTG_HC_PID_DATA0
-+	 *	- DWC_OTG_HC_PID_DATA1
-+	 */
-+	uint8_t data_toggle;
-+
-+	/** Ping state if 1. */
-+	uint8_t ping_state;
-+
-+	/**
-+	 * List of QTDs for this QH.
-+	 */
-+	struct dwc_otg_qtd_list qtd_list;
-+
-+	/** Host channel currently processing transfers for this QH. */
-+	struct dwc_hc *channel;
-+
-+	/** Full/low speed endpoint on high-speed hub requires split. */
-+	uint8_t do_split;
-+
-+	/** @name Periodic schedule information */
-+	/** @{ */
-+
-+	/** Bandwidth in microseconds per (micro)frame. */
-+	uint16_t usecs;
-+
-+	/** Interval between transfers in (micro)frames. */
-+	uint16_t interval;
-+
-+	/**
-+	 * (micro)frame to initialize a periodic transfer. The transfer
-+	 * executes in the following (micro)frame.
-+	 */
-+	uint16_t sched_frame;
-+
-+	/*
-+	** Frame a NAK was received on this queue head, used to minimise NAK retransmission
-+	*/
-+	uint16_t nak_frame;
-+
-+	/** (micro)frame at which last start split was initialized. */
-+	uint16_t start_split_frame;
-+
-+	/** @} */
-+
-+	/**
-+	 * Used instead of original buffer if
-+	 * it(physical address) is not dword-aligned.
-+	 */
-+	uint8_t *dw_align_buf;
-+	dwc_dma_t dw_align_buf_dma;
-+
-+	/** Entry for QH in either the periodic or non-periodic schedule. */
-+	dwc_list_link_t qh_list_entry;
-+
-+	/** @name Descriptor DMA support */
-+	/** @{ */
-+
-+	/** Descriptor List. */
-+	dwc_otg_host_dma_desc_t *desc_list;
-+
-+	/** Descriptor List physical address. */
-+	dwc_dma_t desc_list_dma;
-+
-+	/**
-+	 * Xfer Bytes array.
-+	 * Each element corresponds to a descriptor and indicates
-+	 * original XferSize size value for the descriptor.
-+	 */
-+	uint32_t *n_bytes;
-+
-+	/** Actual number of transfer descriptors in a list. */
-+	uint16_t ntd;
-+
-+	/** First activated isochronous transfer descriptor index. */
-+	uint8_t td_first;
-+	/** Last activated isochronous transfer descriptor index. */
-+	uint8_t td_last;
-+
-+	/** @} */
-+
-+
-+	uint16_t speed;
-+	uint16_t frame_usecs[8];
-+
-+	uint32_t skip_count;
-+} dwc_otg_qh_t;
-+
-+DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
-+
-+typedef struct urb_tq_entry {
-+	struct urb *urb;
-+	DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries;
-+} urb_tq_entry_t;
-+
-+DWC_TAILQ_HEAD(urb_list, urb_tq_entry);
-+
-+/**
-+ * This structure holds the state of the HCD, including the non-periodic and
-+ * periodic schedules.
-+ */
-+struct dwc_otg_hcd {
-+	/** The DWC otg device pointer */
-+	struct dwc_otg_device *otg_dev;
-+	/** DWC OTG Core Interface Layer */
-+	dwc_otg_core_if_t *core_if;
-+
-+	/** Function HCD driver callbacks */
-+	struct dwc_otg_hcd_function_ops *fops;
-+
-+	/** Internal DWC HCD Flags */
-+	volatile union dwc_otg_hcd_internal_flags {
-+		uint32_t d32;
-+		struct {
-+			unsigned port_connect_status_change:1;
-+			unsigned port_connect_status:1;
-+			unsigned port_reset_change:1;
-+			unsigned port_enable_change:1;
-+			unsigned port_suspend_change:1;
-+			unsigned port_over_current_change:1;
-+			unsigned port_l1_change:1;
-+			unsigned port_speed:2;
-+			unsigned reserved:24;
-+		} b;
-+	} flags;
-+
-+	/**
-+	 * Inactive items in the non-periodic schedule. This is a list of
-+	 * Queue Heads. Transfers associated with these Queue Heads are not
-+	 * currently assigned to a host channel.
-+	 */
-+	dwc_list_link_t non_periodic_sched_inactive;
-+
-+	/**
-+	 * Active items in the non-periodic schedule. This is a list of
-+	 * Queue Heads. Transfers associated with these Queue Heads are
-+	 * currently assigned to a host channel.
-+	 */
-+	dwc_list_link_t non_periodic_sched_active;
-+
-+	/**
-+	 * Pointer to the next Queue Head to process in the active
-+	 * non-periodic schedule.
-+	 */
-+	dwc_list_link_t *non_periodic_qh_ptr;
-+
-+	/**
-+	 * Inactive items in the periodic schedule. This is a list of QHs for
-+	 * periodic transfers that are _not_ scheduled for the next frame.
-+	 * Each QH in the list has an interval counter that determines when it
-+	 * needs to be scheduled for execution. This scheduling mechanism
-+	 * allows only a simple calculation for periodic bandwidth used (i.e.
-+	 * must assume that all periodic transfers may need to execute in the
-+	 * same frame). However, it greatly simplifies scheduling and should
-+	 * be sufficient for the vast majority of OTG hosts, which need to
-+	 * connect to a small number of peripherals at one time.
-+	 *
-+	 * Items move from this list to periodic_sched_ready when the QH
-+	 * interval counter is 0 at SOF.
-+	 */
-+	dwc_list_link_t periodic_sched_inactive;
-+
-+	/**
-+	 * List of periodic QHs that are ready for execution in the next
-+	 * frame, but have not yet been assigned to host channels.
-+	 *
-+	 * Items move from this list to periodic_sched_assigned as host
-+	 * channels become available during the current frame.
-+	 */
-+	dwc_list_link_t periodic_sched_ready;
-+
-+	/**
-+	 * List of periodic QHs to be executed in the next frame that are
-+	 * assigned to host channels.
-+	 *
-+	 * Items move from this list to periodic_sched_queued as the
-+	 * transactions for the QH are queued to the DWC_otg controller.
-+	 */
-+	dwc_list_link_t periodic_sched_assigned;
-+
-+	/**
-+	 * List of periodic QHs that have been queued for execution.
-+	 *
-+	 * Items move from this list to either periodic_sched_inactive or
-+	 * periodic_sched_ready when the channel associated with the transfer
-+	 * is released. If the interval for the QH is 1, the item moves to
-+	 * periodic_sched_ready because it must be rescheduled for the next
-+	 * frame. Otherwise, the item moves to periodic_sched_inactive.
-+	 */
-+	dwc_list_link_t periodic_sched_queued;
-+
-+	/**
-+	 * Total bandwidth claimed so far for periodic transfers. This value
-+	 * is in microseconds per (micro)frame. The assumption is that all
-+	 * periodic transfers may occur in the same (micro)frame.
-+	 */
-+	uint16_t periodic_usecs;
-+
-+	/**
-+	 * Total bandwidth claimed so far for all periodic transfers
-+	 * in a frame.
-+	 * This will include a mixture of HS and FS transfers.
-+	 * Units are microseconds per (micro)frame.
-+	 * We have a budget per frame and have to schedule
-+	 * transactions accordingly.
-+	 * Watch out for the fact that things are actually scheduled for the
-+	 * "next frame".
-+	 */
-+	uint16_t                frame_usecs[8];
-+
-+
-+	/**
-+	 * Frame number read from the core at SOF. The value ranges from 0 to
-+	 * DWC_HFNUM_MAX_FRNUM.
-+	 */
-+	uint16_t frame_number;
-+
-+	/**
-+	 * Count of periodic QHs, if using several eps. For SOF enable/disable.
-+	 */
-+	uint16_t periodic_qh_count;
-+
-+	/**
-+	 * Free host channels in the controller. This is a list of
-+	 * dwc_hc_t items.
-+	 */
-+	struct hc_list free_hc_list;
-+	/**
-+	 * Number of host channels assigned to periodic transfers. Currently
-+	 * assuming that there is a dedicated host channel for each periodic
-+	 * transaction and at least one host channel available for
-+	 * non-periodic transactions.
-+	 */
-+	int periodic_channels; /* microframe_schedule==0 */
-+
-+	/**
-+	 * Number of host channels assigned to non-periodic transfers.
-+	 */
-+	int non_periodic_channels; /* microframe_schedule==0 */
-+
-+	/**
-+	 * Number of host channels assigned to non-periodic transfers.
-+	 */
-+	int available_host_channels;
-+
-+	/**
-+	 * Array of pointers to the host channel descriptors. Allows accessing
-+	 * a host channel descriptor given the host channel number. This is
-+	 * useful in interrupt handlers.
-+	 */
-+	struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
-+
-+	/**
-+	 * Buffer to use for any data received during the status phase of a
-+	 * control transfer. Normally no data is transferred during the status
-+	 * phase. This buffer is used as a bit bucket.
-+	 */
-+	uint8_t *status_buf;
-+
-+	/**
-+	 * DMA address for status_buf.
-+	 */
-+	dma_addr_t status_buf_dma;
-+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
-+
-+	/**
-+	 * Connection timer. An OTG host must display a message if the device
-+	 * does not connect. Started when the VBus power is turned on via
-+	 * sysfs attribute "buspower".
-+	 */
-+	dwc_timer_t *conn_timer;
-+
-+	/* Tasket to do a reset */
-+	dwc_tasklet_t *reset_tasklet;
-+
-+	dwc_tasklet_t *completion_tasklet;
-+	struct urb_list completed_urb_list;
-+
-+	/*  */
-+	dwc_spinlock_t *lock;
-+	/**
-+	 * Private data that could be used by OS wrapper.
-+	 */
-+	void *priv;
-+
-+	uint8_t otg_port;
-+
-+	/** Frame List */
-+	uint32_t *frame_list;
-+
-+	/** Hub - Port assignment */
-+	int hub_port[128];
-+#ifdef FIQ_DEBUG
-+	int hub_port_alloc[2048];
-+#endif
-+
-+	/** Frame List DMA address */
-+	dma_addr_t frame_list_dma;
-+
-+	struct fiq_stack *fiq_stack;
-+	struct fiq_state *fiq_state;
-+
-+	/** Virtual address for split transaction DMA bounce buffers */
-+	struct fiq_dma_blob *fiq_dmab;
-+
-+#ifdef DEBUG
-+	uint32_t frrem_samples;
-+	uint64_t frrem_accum;
-+
-+	uint32_t hfnum_7_samples_a;
-+	uint64_t hfnum_7_frrem_accum_a;
-+	uint32_t hfnum_0_samples_a;
-+	uint64_t hfnum_0_frrem_accum_a;
-+	uint32_t hfnum_other_samples_a;
-+	uint64_t hfnum_other_frrem_accum_a;
-+
-+	uint32_t hfnum_7_samples_b;
-+	uint64_t hfnum_7_frrem_accum_b;
-+	uint32_t hfnum_0_samples_b;
-+	uint64_t hfnum_0_frrem_accum_b;
-+	uint32_t hfnum_other_samples_b;
-+	uint64_t hfnum_other_frrem_accum_b;
-+#endif
-+};
-+
-+static inline struct device *dwc_otg_hcd_to_dev(struct dwc_otg_hcd *hcd)
-+{
-+	return &hcd->otg_dev->os_dep.platformdev->dev;
-+}
-+
-+/** @name Transaction Execution Functions */
-+/** @{ */
-+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
-+								  * hcd);
-+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
-+					   dwc_otg_transaction_type_e tr_type);
-+
-+int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh);
-+void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh);
-+
-+extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
-+extern int fiq_fsm_transaction_suitable(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
-+extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num);
-+
-+/** @} */
-+
-+/** @name Interrupt Handler Functions */
-+/** @{ */
-+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
-+							 dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
-+							dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
-+							   dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
-+							   dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
-+							     dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
-+					    uint32_t num);
-+extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
-+						       dwc_otg_hcd);
-+/** @} */
-+
-+/** @name Schedule Queue Functions */
-+/** @{ */
-+
-+/* Implemented in dwc_otg_hcd_queue.c */
-+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
-+					   dwc_otg_hcd_urb_t * urb, int atomic_alloc);
-+extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+				      int sched_csplit);
-+
-+/** Remove and free a QH */
-+static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
-+						  dwc_otg_qh_t * qh)
-+{
-+	dwc_irqflags_t flags;
-+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+	dwc_otg_hcd_qh_remove(hcd, qh);
-+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+	dwc_otg_hcd_qh_free(hcd, qh);
-+}
-+
-+/** Allocates memory for a QH structure.
-+ * @return Returns the memory allocate or NULL on error. */
-+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
-+{
-+	if (atomic_alloc)
-+		return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
-+	else
-+		return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
-+}
-+
-+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
-+					     int atomic_alloc);
-+extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
-+extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
-+			       dwc_otg_qh_t ** qh, int atomic_alloc);
-+
-+/** Allocates memory for a QTD structure.
-+ * @return Returns the memory allocate or NULL on error. */
-+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
-+{
-+	if (atomic_alloc)
-+		return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
-+	else
-+		return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
-+}
-+
-+/** Frees the memory for a QTD structure.  QTD should already be removed from
-+ * list.
-+ * @param qtd QTD to free.*/
-+static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
-+{
-+	DWC_FREE(qtd);
-+}
-+
-+/** Removes a QTD from list.
-+ * @param hcd HCD instance.
-+ * @param qtd QTD to remove from list.
-+ * @param qh QTD belongs to.
-+ */
-+static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
-+					  dwc_otg_qtd_t * qtd,
-+					  dwc_otg_qh_t * qh)
-+{
-+	DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
-+}
-+
-+/** Remove and free a QTD
-+  * Need to disable IRQ and hold hcd lock while calling this function out of
-+  * interrupt servicing chain */
-+static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
-+						   dwc_otg_qtd_t * qtd,
-+						   dwc_otg_qh_t * qh)
-+{
-+	dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
-+	dwc_otg_hcd_qtd_free(qtd);
-+}
-+
-+/** @} */
-+
-+/** @name Descriptor DMA Supporting Functions */
-+/** @{ */
-+
-+extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
-+					   dwc_hc_t * hc,
-+					   dwc_otg_hc_regs_t * hc_regs,
-+					   dwc_otg_halt_status_e halt_status);
-+
-+extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
-+
-+/** @} */
-+
-+/** @name Internal Functions */
-+/** @{ */
-+dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
-+/** @} */
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
-+					   uint8_t devaddr);
-+extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
-+#endif
-+
-+/** Gets the QH that contains the list_head */
-+#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
-+
-+/** Gets the QTD that contains the list_head */
-+#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
-+
-+/** Check if QH is non-periodic  */
-+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
-+				     (_qh_ptr_->ep_type == UE_CONTROL))
-+
-+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
-+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
-+
-+/** Packet size for any kind of endpoint descriptor */
-+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
-+
-+/**
-+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is
-+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
-+ * frame number when the max frame number is reached.
-+ */
-+static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
-+{
-+	return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
-+	    (DWC_HFNUM_MAX_FRNUM >> 1);
-+}
-+
-+/**
-+ * Returns true if _frame1 is greater than _frame2. The comparison is done
-+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
-+ * number when the max frame number is reached.
-+ */
-+static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
-+{
-+	return (frame1 != frame2) &&
-+	    (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
-+	     (DWC_HFNUM_MAX_FRNUM >> 1));
-+}
-+
-+/**
-+ * Increments _frame by the amount specified by _inc. The addition is done
-+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
-+ */
-+static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
-+{
-+	return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
-+}
-+
-+static inline uint16_t dwc_full_frame_num(uint16_t frame)
-+{
-+	return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
-+}
-+
-+static inline uint16_t dwc_micro_frame_num(uint16_t frame)
-+{
-+	return frame & 0x7;
-+}
-+
-+extern void init_hcd_usecs(dwc_otg_hcd_t *_hcd);
-+
-+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
-+				  dwc_otg_hc_regs_t * hc_regs,
-+				  dwc_otg_qtd_t * qtd);
-+
-+#ifdef DEBUG
-+/**
-+ * Macro to sample the remaining PHY clocks left in the current frame. This
-+ * may be used during debugging to determine the average time it takes to
-+ * execute sections of code. There are two possible sample points, "a" and
-+ * "b", so the _letter argument must be one of these values.
-+ *
-+ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
-+ * example, "cat /sys/devices/lm0/hcd_frrem".
-+ */
-+#define dwc_sample_frrem(_hcd, _qh, _letter) \
-+{ \
-+	hfnum_data_t hfnum; \
-+	dwc_otg_qtd_t *qtd; \
-+	qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
-+	if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
-+		hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
-+		switch (hfnum.b.frnum & 0x7) { \
-+		case 7: \
-+			_hcd->hfnum_7_samples_##_letter++; \
-+			_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
-+			break; \
-+		case 0: \
-+			_hcd->hfnum_0_samples_##_letter++; \
-+			_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
-+			break; \
-+		default: \
-+			_hcd->hfnum_other_samples_##_letter++; \
-+			_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
-+			break; \
-+		} \
-+	} \
-+}
-+#else
-+#define dwc_sample_frrem(_hcd, _qh, _letter)
-+#endif
-+#endif
-+#endif /* DWC_DEVICE_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
-@@ -0,0 +1,1134 @@
-+/*==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
-+ * $Revision: #10 $
-+ * $Date: 2011/10/20 $
-+ * $Change: 1869464 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/** @file
-+ * This file contains Descriptor DMA support implementation for host mode.
-+ */
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+extern bool microframe_schedule;
-+
-+static inline uint8_t frame_list_idx(uint16_t frame)
-+{
-+	return (frame & (MAX_FRLIST_EN_NUM - 1));
-+}
-+
-+static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
-+{
-+	return (idx + inc) &
-+	    (((speed ==
-+	       DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
-+	      MAX_DMA_DESC_NUM_GENERIC) - 1);
-+}
-+
-+static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
-+{
-+	return (idx - inc) &
-+	    (((speed ==
-+	       DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
-+	      MAX_DMA_DESC_NUM_GENERIC) - 1);
-+}
-+
-+static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
-+{
-+	return (((qh->ep_type == UE_ISOCHRONOUS)
-+		 && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
-+		? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
-+}
-+static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
-+{
-+	return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
-+		? ((qh->interval + 8 - 1) / 8)
-+		: qh->interval);
-+}
-+
-+static int desc_list_alloc(struct device *dev, dwc_otg_qh_t * qh)
-+{
-+	int retval = 0;
-+
-+	qh->desc_list = (dwc_otg_host_dma_desc_t *)
-+	    DWC_DMA_ALLOC(dev, sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
-+			  &qh->desc_list_dma);
-+
-+	if (!qh->desc_list) {
-+		retval = -DWC_E_NO_MEMORY;
-+		DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
-+
-+	}
-+
-+	dwc_memset(qh->desc_list, 0x00,
-+		   sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
-+
-+	qh->n_bytes =
-+	    (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
-+
-+	if (!qh->n_bytes) {
-+		retval = -DWC_E_NO_MEMORY;
-+		DWC_ERROR
-+		    ("%s: Failed to allocate array for descriptors' size actual values\n",
-+		     __func__);
-+
-+	}
-+	return retval;
-+
-+}
-+
-+static void desc_list_free(struct device *dev, dwc_otg_qh_t * qh)
-+{
-+	if (qh->desc_list) {
-+		DWC_DMA_FREE(dev, max_desc_num(qh), qh->desc_list,
-+			     qh->desc_list_dma);
-+		qh->desc_list = NULL;
-+	}
-+
-+	if (qh->n_bytes) {
-+		DWC_FREE(qh->n_bytes);
-+		qh->n_bytes = NULL;
-+	}
-+}
-+
-+static int frame_list_alloc(dwc_otg_hcd_t * hcd)
-+{
-+	struct device *dev = dwc_otg_hcd_to_dev(hcd);
-+	int retval = 0;
-+
-+	if (hcd->frame_list)
-+		return 0;
-+
-+	hcd->frame_list = DWC_DMA_ALLOC(dev, 4 * MAX_FRLIST_EN_NUM,
-+					&hcd->frame_list_dma);
-+	if (!hcd->frame_list) {
-+		retval = -DWC_E_NO_MEMORY;
-+		DWC_ERROR("%s: Frame List allocation failed\n", __func__);
-+	}
-+
-+	dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
-+
-+	return retval;
-+}
-+
-+static void frame_list_free(dwc_otg_hcd_t * hcd)
-+{
-+	struct device *dev = dwc_otg_hcd_to_dev(hcd);
-+
-+	if (!hcd->frame_list)
-+		return;
-+
-+	DWC_DMA_FREE(dev, 4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
-+	hcd->frame_list = NULL;
-+}
-+
-+static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
-+{
-+
-+	hcfg_data_t hcfg;
-+
-+	hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
-+
-+	if (hcfg.b.perschedena) {
-+		/* already enabled */
-+		return;
-+	}
-+
-+	DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
-+			hcd->frame_list_dma);
-+
-+	switch (fr_list_en) {
-+	case 64:
-+		hcfg.b.frlisten = 3;
-+		break;
-+	case 32:
-+		hcfg.b.frlisten = 2;
-+		break;
-+	case 16:
-+		hcfg.b.frlisten = 1;
-+		break;
-+	case 8:
-+		hcfg.b.frlisten = 0;
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	hcfg.b.perschedena = 1;
-+
-+	DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
-+	DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+
-+}
-+
-+static void per_sched_disable(dwc_otg_hcd_t * hcd)
-+{
-+	hcfg_data_t hcfg;
-+
-+	hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
-+
-+	if (!hcfg.b.perschedena) {
-+		/* already disabled */
-+		return;
-+	}
-+	hcfg.b.perschedena = 0;
-+
-+	DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
-+	DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
-+}
-+
-+/*
-+ * Activates/Deactivates FrameList entries for the channel
-+ * based on endpoint servicing period.
-+ */
-+void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
-+{
-+	uint16_t i, j, inc;
-+	dwc_hc_t *hc = NULL;
-+
-+	if (!qh->channel) {
-+		DWC_ERROR("qh->channel = %p", qh->channel);
-+		return;
-+	}
-+
-+	if (!hcd) {
-+		DWC_ERROR("------hcd = %p", hcd);
-+		return;
-+	}
-+
-+	if (!hcd->frame_list) {
-+		DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
-+		return;
-+	}
-+
-+	hc = qh->channel;
-+	inc = frame_incr_val(qh);
-+	if (qh->ep_type == UE_ISOCHRONOUS)
-+		i = frame_list_idx(qh->sched_frame);
-+	else
-+		i = 0;
-+
-+	j = i;
-+	do {
-+		if (enable)
-+			hcd->frame_list[j] |= (1 << hc->hc_num);
-+		else
-+			hcd->frame_list[j] &= ~(1 << hc->hc_num);
-+		j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
-+	}
-+	while (j != i);
-+	if (!enable)
-+		return;
-+	hc->schinfo = 0;
-+	if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
-+		j = 1;
-+		/* TODO - check this */
-+		inc = (8 + qh->interval - 1) / qh->interval;
-+		for (i = 0; i < inc; i++) {
-+			hc->schinfo |= j;
-+			j = j << qh->interval;
-+		}
-+	} else {
-+		hc->schinfo = 0xff;
-+	}
-+}
-+
-+#if 1
-+void dump_frame_list(dwc_otg_hcd_t * hcd)
-+{
-+	int i = 0;
-+	DWC_PRINTF("--FRAME LIST (hex) --\n");
-+	for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
-+		DWC_PRINTF("%x\t", hcd->frame_list[i]);
-+		if (!(i % 8) && i)
-+			DWC_PRINTF("\n");
-+	}
-+	DWC_PRINTF("\n----\n");
-+
-+}
-+#endif
-+
-+static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	dwc_hc_t *hc = qh->channel;
-+	if (dwc_qh_is_non_per(qh)) {
-+		if (!microframe_schedule)
-+			hcd->non_periodic_channels--;
-+		else
-+			hcd->available_host_channels++;
-+	} else
-+		update_frame_list(hcd, qh, 0);
-+
-+	/*
-+	 * The condition is added to prevent double cleanup try in case of device
-+	 * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
-+	 */
-+	if (hc->qh) {
-+		dwc_otg_hc_cleanup(hcd->core_if, hc);
-+		DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+		hc->qh = NULL;
-+	}
-+
-+	qh->channel = NULL;
-+	qh->ntd = 0;
-+
-+	if (qh->desc_list) {
-+		dwc_memset(qh->desc_list, 0x00,
-+			   sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
-+	}
-+}
-+
-+/**
-+ * Initializes a QH structure's Descriptor DMA related members.
-+ * Allocates memory for descriptor list.
-+ * On first periodic QH, allocates memory for FrameList
-+ * and enables periodic scheduling.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	struct device *dev = dwc_otg_hcd_to_dev(hcd);
-+	int retval = 0;
-+
-+	if (qh->do_split) {
-+		DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
-+		return -1;
-+	}
-+
-+	retval = desc_list_alloc(dev, qh);
-+
-+	if ((retval == 0)
-+	    && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
-+		if (!hcd->frame_list) {
-+			retval = frame_list_alloc(hcd);
-+			/* Enable periodic schedule on first periodic QH */
-+			if (retval == 0)
-+				per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
-+		}
-+	}
-+
-+	qh->ntd = 0;
-+
-+	return retval;
-+}
-+
-+/**
-+ * Frees descriptor list memory associated with the QH.
-+ * If QH is periodic and the last, frees FrameList memory
-+ * and disables periodic scheduling.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ */
-+void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	struct device *dev = dwc_otg_hcd_to_dev(hcd);
-+
-+	desc_list_free(dev, qh);
-+
-+	/*
-+	 * Channel still assigned due to some reasons.
-+	 * Seen on Isoc URB dequeue. Channel halted but no subsequent
-+	 * ChHalted interrupt to release the channel. Afterwards
-+	 * when it comes here from endpoint disable routine
-+	 * channel remains assigned.
-+	 */
-+	if (qh->channel)
-+		release_channel_ddma(hcd, qh);
-+
-+	if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
-+	    && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {
-+
-+		per_sched_disable(hcd);
-+		frame_list_free(hcd);
-+	}
-+}
-+
-+static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
-+{
-+	if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
-+		/*
-+		 * Descriptor set(8 descriptors) index
-+		 * which is 8-aligned.
-+		 */
-+		return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
-+	} else {
-+		return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
-+	}
-+}
-+
-+/*
-+ * Determine starting frame for Isochronous transfer.
-+ * Few frames skipped to prevent race condition with HC.
-+ */
-+static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+				   uint8_t * skip_frames)
-+{
-+	uint16_t frame = 0;
-+	hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
-+
-+	/* sched_frame is always frame number(not uFrame) both in FS and HS !! */
-+
-+	/*
-+	 * skip_frames is used to limit activated descriptors number
-+	 * to avoid the situation when HC services the last activated
-+	 * descriptor firstly.
-+	 * Example for FS:
-+	 * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
-+	 * corresponding to curr_frame+1, the descriptor corresponding to frame 2
-+	 * will be fetched. If the number of descriptors is max=64 (or greather) the
-+	 * list will be fully programmed with Active descriptors and it is possible
-+	 * case(rare) that the latest descriptor(considering rollback) corresponding
-+	 * to frame 2 will be serviced first. HS case is more probable because, in fact,
-+	 * up to 11 uframes(16 in the code) may be skipped.
-+	 */
-+	if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
-+		/*
-+		 * Consider uframe counter also, to start xfer asap.
-+		 * If half of the frame elapsed skip 2 frames otherwise
-+		 * just 1 frame.
-+		 * Starting descriptor index must be 8-aligned, so
-+		 * if the current frame is near to complete the next one
-+		 * is skipped as well.
-+		 */
-+
-+		if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
-+			*skip_frames = 2 * 8;
-+			frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
-+		} else {
-+			*skip_frames = 1 * 8;
-+			frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
-+		}
-+
-+		frame = dwc_full_frame_num(frame);
-+	} else {
-+		/*
-+		 * Two frames are skipped for FS - the current and the next.
-+		 * But for descriptor programming, 1 frame(descriptor) is enough,
-+		 * see example above.
-+		 */
-+		*skip_frames = 1;
-+		frame = dwc_frame_num_inc(hcd->frame_number, 2);
-+	}
-+
-+	return frame;
-+}
-+
-+/*
-+ * Calculate initial descriptor index for isochronous transfer
-+ * based on scheduled frame.
-+ */
-+static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	uint16_t frame = 0, fr_idx, fr_idx_tmp;
-+	uint8_t skip_frames = 0;
-+	/*
-+	 * With current ISOC processing algorithm the channel is being
-+	 * released when no more QTDs in the list(qh->ntd == 0).
-+	 * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
-+	 *
-+	 * So qh->channel != NULL branch is not used and just not removed from the
-+	 * source file. It is required for another possible approach which is,
-+	 * do not disable and release the channel when ISOC session completed,
-+	 * just move QH to inactive schedule until new QTD arrives.
-+	 * On new QTD, the QH moved back to 'ready' schedule,
-+	 * starting frame and therefore starting desc_index are recalculated.
-+	 * In this case channel is released only on ep_disable.
-+	 */
-+
-+	/* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
-+	if (qh->channel) {
-+		frame = calc_starting_frame(hcd, qh, &skip_frames);
-+		/*
-+		 * Calculate initial descriptor index based on FrameList current bitmap
-+		 * and servicing period.
-+		 */
-+		fr_idx_tmp = frame_list_idx(frame);
-+		fr_idx =
-+		    (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
-+		     fr_idx_tmp)
-+		    % frame_incr_val(qh);
-+		fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
-+	} else {
-+		qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
-+		fr_idx = frame_list_idx(qh->sched_frame);
-+	}
-+
-+	qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
-+
-+	return skip_frames;
-+}
-+
-+#define	ISOC_URB_GIVEBACK_ASAP
-+
-+#define MAX_ISOC_XFER_SIZE_FS 1023
-+#define MAX_ISOC_XFER_SIZE_HS 3072
-+#define DESCNUM_THRESHOLD 4
-+
-+static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+			       uint8_t skip_frames)
-+{
-+	struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+	dwc_otg_qtd_t *qtd;
-+	dwc_otg_host_dma_desc_t *dma_desc;
-+	uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
-+
-+	idx = qh->td_last;
-+	inc = qh->interval;
-+	n_desc = 0;
-+
-+	ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
-+	if (skip_frames && !qh->channel)
-+		ntd_max = ntd_max - skip_frames / qh->interval;
-+
-+	max_xfer_size =
-+	    (qh->dev_speed ==
-+	     DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
-+	    MAX_ISOC_XFER_SIZE_FS;
-+
-+	DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
-+		while ((qh->ntd < ntd_max)
-+		       && (qtd->isoc_frame_index_last <
-+			   qtd->urb->packet_count)) {
-+
-+			dma_desc = &qh->desc_list[idx];
-+			dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
-+
-+			frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
-+
-+			if (frame_desc->length > max_xfer_size)
-+				qh->n_bytes[idx] = max_xfer_size;
-+			else
-+				qh->n_bytes[idx] = frame_desc->length;
-+			dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
-+			dma_desc->status.b_isoc.a = 1;
-+			dma_desc->status.b_isoc.sts = 0;
-+
-+			dma_desc->buf = qtd->urb->dma + frame_desc->offset;
-+
-+			qh->ntd++;
-+
-+			qtd->isoc_frame_index_last++;
-+
-+#ifdef	ISOC_URB_GIVEBACK_ASAP
-+			/*
-+			 * Set IOC for each descriptor corresponding to the
-+			 * last frame of the URB.
-+			 */
-+			if (qtd->isoc_frame_index_last ==
-+			    qtd->urb->packet_count)
-+				dma_desc->status.b_isoc.ioc = 1;
-+
-+#endif
-+			idx = desclist_idx_inc(idx, inc, qh->dev_speed);
-+			n_desc++;
-+
-+		}
-+		qtd->in_process = 1;
-+	}
-+
-+	qh->td_last = idx;
-+
-+#ifdef	ISOC_URB_GIVEBACK_ASAP
-+	/* Set IOC for the last descriptor if descriptor list is full */
-+	if (qh->ntd == ntd_max) {
-+		idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
-+		qh->desc_list[idx].status.b_isoc.ioc = 1;
-+	}
-+#else
-+	/*
-+	 * Set IOC bit only for one descriptor.
-+	 * Always try to be ahead of HW processing,
-+	 * i.e. on IOC generation driver activates next descriptors but
-+	 * core continues to process descriptors followed the one with IOC set.
-+	 */
-+
-+	if (n_desc > DESCNUM_THRESHOLD) {
-+		/*
-+		 * Move IOC "up". Required even if there is only one QTD
-+		 * in the list, cause QTDs migth continue to be queued,
-+		 * but during the activation it was only one queued.
-+		 * Actually more than one QTD might be in the list if this function called
-+		 * from XferCompletion - QTDs was queued during HW processing of the previous
-+		 * descriptor chunk.
-+		 */
-+		idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
-+	} else {
-+		/*
-+		 * Set the IOC for the latest descriptor
-+		 * if either number of descriptor is not greather than threshold
-+		 * or no more new descriptors activated.
-+		 */
-+		idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
-+	}
-+
-+	qh->desc_list[idx].status.b_isoc.ioc = 1;
-+#endif
-+}
-+
-+static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+
-+	dwc_hc_t *hc;
-+	dwc_otg_host_dma_desc_t *dma_desc;
-+	dwc_otg_qtd_t *qtd;
-+	int num_packets, len, n_desc = 0;
-+
-+	hc = qh->channel;
-+
-+	/*
-+	 * Start with hc->xfer_buff initialized in
-+	 * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
-+	 * this pointer re-assigned to the buffer of the currently processed QTD.
-+	 * For non-SG request there is always one QTD active.
-+	 */
-+
-+	DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
-+
-+		if (n_desc) {
-+			/* SG request - more than 1 QTDs */
-+			hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
-+			hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
-+		}
-+
-+		qtd->n_desc = 0;
-+
-+		do {
-+			dma_desc = &qh->desc_list[n_desc];
-+			len = hc->xfer_len;
-+
-+			if (len > MAX_DMA_DESC_SIZE)
-+				len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
-+
-+			if (hc->ep_is_in) {
-+				if (len > 0) {
-+					num_packets = (len + hc->max_packet - 1) / hc->max_packet;
-+				} else {
-+					/* Need 1 packet for transfer length of 0. */
-+					num_packets = 1;
-+				}
-+				/* Always program an integral # of max packets for IN transfers. */
-+				len = num_packets * hc->max_packet;
-+			}
-+
-+			dma_desc->status.b.n_bytes = len;
-+
-+			qh->n_bytes[n_desc] = len;
-+
-+			if ((qh->ep_type == UE_CONTROL)
-+			    && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
-+				dma_desc->status.b.sup = 1;	/* Setup Packet */
-+
-+			dma_desc->status.b.a = 1;	/* Active descriptor */
-+			dma_desc->status.b.sts = 0;
-+
-+			dma_desc->buf =
-+			    ((unsigned long)hc->xfer_buff & 0xffffffff);
-+
-+			/*
-+			 * Last descriptor(or single) of IN transfer
-+			 * with actual size less than MaxPacket.
-+			 */
-+			if (len > hc->xfer_len) {
-+				hc->xfer_len = 0;
-+			} else {
-+				hc->xfer_buff += len;
-+				hc->xfer_len -= len;
-+			}
-+
-+			qtd->n_desc++;
-+			n_desc++;
-+		}
-+		while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
-+
-+
-+		qtd->in_process = 1;
-+
-+		if (qh->ep_type == UE_CONTROL)
-+			break;
-+
-+		if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
-+			break;
-+	}
-+
-+	if (n_desc) {
-+		/* Request Transfer Complete interrupt for the last descriptor */
-+		qh->desc_list[n_desc - 1].status.b.ioc = 1;
-+		/* End of List indicator */
-+		qh->desc_list[n_desc - 1].status.b.eol = 1;
-+
-+		hc->ntd = n_desc;
-+	}
-+}
-+
-+/**
-+ * For Control and Bulk endpoints initializes descriptor list
-+ * and starts the transfer.
-+ *
-+ * For Interrupt and Isochronous endpoints initializes descriptor list
-+ * then updates FrameList, marking appropriate entries as active.
-+ * In case of Isochronous, the starting descriptor index is calculated based
-+ * on the scheduled frame, but only on the first transfer descriptor within a session.
-+ * Then starts the transfer via enabling the channel.
-+ * For Isochronous endpoint the channel is not halted on XferComplete
-+ * interrupt so remains assigned to the endpoint(QH) until session is done.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh The QH to init.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	/* Channel is already assigned */
-+	dwc_hc_t *hc = qh->channel;
-+	uint8_t skip_frames = 0;
-+
-+	switch (hc->ep_type) {
-+	case DWC_OTG_EP_TYPE_CONTROL:
-+	case DWC_OTG_EP_TYPE_BULK:
-+		init_non_isoc_dma_desc(hcd, qh);
-+
-+		dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+		break;
-+	case DWC_OTG_EP_TYPE_INTR:
-+		init_non_isoc_dma_desc(hcd, qh);
-+
-+		update_frame_list(hcd, qh, 1);
-+
-+		dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+		break;
-+	case DWC_OTG_EP_TYPE_ISOC:
-+
-+		if (!qh->ntd)
-+			skip_frames = recalc_initial_desc_idx(hcd, qh);
-+
-+		init_isoc_dma_desc(hcd, qh, skip_frames);
-+
-+		if (!hc->xfer_started) {
-+
-+			update_frame_list(hcd, qh, 1);
-+
-+			/*
-+			 * Always set to max, instead of actual size.
-+			 * Otherwise ntd will be changed with
-+			 * channel being enabled. Not recommended.
-+			 *
-+			 */
-+			hc->ntd = max_desc_num(qh);
-+			/* Enable channel only once for ISOC */
-+			dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
-+		}
-+
-+		break;
-+	default:
-+
-+		break;
-+	}
-+}
-+
-+static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
-+				    dwc_hc_t * hc,
-+				    dwc_otg_hc_regs_t * hc_regs,
-+				    dwc_otg_halt_status_e halt_status)
-+{
-+	struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+	dwc_otg_qtd_t *qtd, *qtd_tmp;
-+	dwc_otg_qh_t *qh;
-+	dwc_otg_host_dma_desc_t *dma_desc;
-+	uint16_t idx, remain;
-+	uint8_t urb_compl;
-+
-+	qh = hc->qh;
-+	idx = qh->td_first;
-+
-+	if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+		DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
-+		    qtd->in_process = 0;
-+		return;
-+	} else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
-+		   (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
-+		/*
-+		 * Channel is halted in these error cases.
-+		 * Considered as serious issues.
-+		 * Complete all URBs marking all frames as failed,
-+		 * irrespective whether some of the descriptors(frames) succeeded or no.
-+		 * Pass error code to completion routine as well, to
-+		 * update urb->status, some of class drivers might use it to stop
-+		 * queing transfer requests.
-+		 */
-+		int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
-+		    ? (-DWC_E_IO)
-+		    : (-DWC_E_OVERFLOW);
-+
-+		DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+			for (idx = 0; idx < qtd->urb->packet_count; idx++) {
-+				frame_desc = &qtd->urb->iso_descs[idx];
-+				frame_desc->status = err;
-+			}
-+			hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
-+			dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+		}
-+		return;
-+	}
-+
-+	DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+
-+		if (!qtd->in_process)
-+			break;
-+
-+		urb_compl = 0;
-+
-+		do {
-+
-+			dma_desc = &qh->desc_list[idx];
-+
-+			frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+			remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
-+
-+			if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
-+				/*
-+				 * XactError or, unable to complete all the transactions
-+				 * in the scheduled micro-frame/frame,
-+				 * both indicated by DMA_DESC_STS_PKTERR.
-+				 */
-+				qtd->urb->error_count++;
-+				frame_desc->actual_length = qh->n_bytes[idx] - remain;
-+				frame_desc->status = -DWC_E_PROTOCOL;
-+			} else {
-+				/* Success */
-+
-+				frame_desc->actual_length = qh->n_bytes[idx] - remain;
-+				frame_desc->status = 0;
-+			}
-+
-+			if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
-+				/*
-+				 * urb->status is not used for isoc transfers here.
-+				 * The individual frame_desc status are used instead.
-+				 */
-+
-+				hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+				dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+
-+				/*
-+				 * This check is necessary because urb_dequeue can be called
-+				 * from urb complete callback(sound driver example).
-+				 * All pending URBs are dequeued there, so no need for
-+				 * further processing.
-+				 */
-+				if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+					return;
-+				}
-+
-+				urb_compl = 1;
-+
-+			}
-+
-+			qh->ntd--;
-+
-+			/* Stop if IOC requested descriptor reached */
-+			if (dma_desc->status.b_isoc.ioc) {
-+				idx = desclist_idx_inc(idx, qh->interval, hc->speed);
-+				goto stop_scan;
-+			}
-+
-+			idx = desclist_idx_inc(idx, qh->interval, hc->speed);
-+
-+			if (urb_compl)
-+				break;
-+		}
-+		while (idx != qh->td_first);
-+	}
-+stop_scan:
-+	qh->td_first = idx;
-+}
-+
-+uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
-+				       dwc_hc_t * hc,
-+				       dwc_otg_qtd_t * qtd,
-+				       dwc_otg_host_dma_desc_t * dma_desc,
-+				       dwc_otg_halt_status_e halt_status,
-+				       uint32_t n_bytes, uint8_t * xfer_done)
-+{
-+
-+	uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
-+	dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+	if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
-+		urb->status = -DWC_E_IO;
-+		return 1;
-+	}
-+	if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
-+		switch (halt_status) {
-+		case DWC_OTG_HC_XFER_STALL:
-+			urb->status = -DWC_E_PIPE;
-+			break;
-+		case DWC_OTG_HC_XFER_BABBLE_ERR:
-+			urb->status = -DWC_E_OVERFLOW;
-+			break;
-+		case DWC_OTG_HC_XFER_XACT_ERR:
-+			urb->status = -DWC_E_PROTOCOL;
-+			break;
-+		default:
-+			DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
-+				  halt_status);
-+			break;
-+		}
-+		return 1;
-+	}
-+
-+	if (dma_desc->status.b.a == 1) {
-+		DWC_DEBUGPL(DBG_HCDV,
-+			    "Active descriptor encountered on channel %d\n",
-+			    hc->hc_num);
-+		return 0;
-+	}
-+
-+	if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
-+		if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
-+			urb->actual_length += n_bytes - remain;
-+			if (remain || urb->actual_length == urb->length) {
-+				/*
-+				 * For Control Data stage do not set urb->status=0 to prevent
-+				 * URB callback. Set it when Status phase done. See below.
-+				 */
-+				*xfer_done = 1;
-+			}
-+
-+		} else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
-+			urb->status = 0;
-+			*xfer_done = 1;
-+		}
-+		/* No handling for SETUP stage */
-+	} else {
-+		/* BULK and INTR */
-+		urb->actual_length += n_bytes - remain;
-+		if (remain || urb->actual_length == urb->length) {
-+			urb->status = 0;
-+			*xfer_done = 1;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
-+					dwc_hc_t * hc,
-+					dwc_otg_hc_regs_t * hc_regs,
-+					dwc_otg_halt_status_e halt_status)
-+{
-+	dwc_otg_hcd_urb_t *urb = NULL;
-+	dwc_otg_qtd_t *qtd, *qtd_tmp;
-+	dwc_otg_qh_t *qh;
-+	dwc_otg_host_dma_desc_t *dma_desc;
-+	uint32_t n_bytes, n_desc, i;
-+	uint8_t failed = 0, xfer_done;
-+
-+	n_desc = 0;
-+
-+	qh = hc->qh;
-+
-+	if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+		DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
-+			qtd->in_process = 0;
-+		}
-+		return;
-+	}
-+
-+	DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
-+
-+		urb = qtd->urb;
-+
-+		n_bytes = 0;
-+		xfer_done = 0;
-+
-+		for (i = 0; i < qtd->n_desc; i++) {
-+			dma_desc = &qh->desc_list[n_desc];
-+
-+			n_bytes = qh->n_bytes[n_desc];
-+
-+			failed =
-+			    update_non_isoc_urb_state_ddma(hcd, hc, qtd,
-+							   dma_desc,
-+							   halt_status, n_bytes,
-+							   &xfer_done);
-+
-+			if (failed
-+			    || (xfer_done
-+				&& (urb->status != -DWC_E_IN_PROGRESS))) {
-+
-+				hcd->fops->complete(hcd, urb->priv, urb,
-+						    urb->status);
-+				dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+
-+				if (failed)
-+					goto stop_scan;
-+			} else if (qh->ep_type == UE_CONTROL) {
-+				if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
-+					if (urb->length > 0) {
-+						qtd->control_phase = DWC_OTG_CONTROL_DATA;
-+					} else {
-+						qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+					}
-+					DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
-+				} else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
-+					if (xfer_done) {
-+						qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+						DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
-+					} else if (i + 1 == qtd->n_desc) {
-+						/*
-+						 * Last descriptor for Control data stage which is
-+						 * not completed yet.
-+						 */
-+						dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+					}
-+				}
-+			}
-+
-+			n_desc++;
-+		}
-+
-+	}
-+
-+stop_scan:
-+
-+	if (qh->ep_type != UE_CONTROL) {
-+		/*
-+		 * Resetting the data toggle for bulk
-+		 * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
-+		 */
-+		if (halt_status == DWC_OTG_HC_XFER_STALL)
-+			qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+		else
-+			dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+	}
-+
-+	if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+		hcint_data_t hcint;
-+		hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+		if (hcint.b.nyet) {
-+			/*
-+			 * Got a NYET on the last transaction of the transfer. It
-+			 * means that the endpoint should be in the PING state at the
-+			 * beginning of the next transfer.
-+			 */
-+			qh->ping_state = 1;
-+			clear_hc_int(hc_regs, nyet);
-+		}
-+
-+	}
-+
-+}
-+
-+/**
-+ * This function is called from interrupt handlers.
-+ * Scans the descriptor list, updates URB's status and
-+ * calls completion routine for the URB if it's done.
-+ * Releases the channel to be used by other transfers.
-+ * In case of Isochronous endpoint the channel is not halted until
-+ * the end of the session, i.e. QTD list is empty.
-+ * If periodic channel released the FrameList is updated accordingly.
-+ *
-+ * Calls transaction selection routines to activate pending transfers.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param hc Host channel, the transfer is completed on.
-+ * @param hc_regs Host channel registers.
-+ * @param halt_status Reason the channel is being halted,
-+ *		      or just XferComplete for isochronous transfer
-+ */
-+void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
-+				    dwc_hc_t * hc,
-+				    dwc_otg_hc_regs_t * hc_regs,
-+				    dwc_otg_halt_status_e halt_status)
-+{
-+	uint8_t continue_isoc_xfer = 0;
-+	dwc_otg_transaction_type_e tr_type;
-+	dwc_otg_qh_t *qh = hc->qh;
-+
-+	if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+
-+		complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+
-+		/* Release the channel if halted or session completed */
-+		if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
-+		    DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+
-+			/* Halt the channel if session completed */
-+			if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+				dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
-+			}
-+
-+			release_channel_ddma(hcd, qh);
-+			dwc_otg_hcd_qh_remove(hcd, qh);
-+		} else {
-+			/* Keep in assigned schedule to continue transfer */
-+			DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+					   &qh->qh_list_entry);
-+			continue_isoc_xfer = 1;
-+
-+		}
-+		/** @todo Consider the case when period exceeds FrameList size.
-+		 *  Frame Rollover interrupt should be used.
-+		 */
-+	} else {
-+		/* Scan descriptor list to complete the URB(s), then release the channel */
-+		complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+
-+		release_channel_ddma(hcd, qh);
-+		dwc_otg_hcd_qh_remove(hcd, qh);
-+
-+		if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+			/* Add back to inactive non-periodic schedule on normal completion */
-+			dwc_otg_hcd_qh_add(hcd, qh);
-+		}
-+
-+	}
-+	tr_type = dwc_otg_hcd_select_transactions(hcd);
-+	if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
-+		if (continue_isoc_xfer) {
-+			if (tr_type == DWC_OTG_TRANSACTION_NONE) {
-+				tr_type = DWC_OTG_TRANSACTION_PERIODIC;
-+			} else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
-+				tr_type = DWC_OTG_TRANSACTION_ALL;
-+			}
-+		}
-+		dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+	}
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
-@@ -0,0 +1,417 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
-+ * $Revision: #12 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+#ifndef __DWC_HCD_IF_H__
-+#define __DWC_HCD_IF_H__
-+
-+#include "dwc_otg_core_if.h"
-+
-+/** @file
-+ * This file defines DWC_OTG HCD Core API.
-+ */
-+
-+struct dwc_otg_hcd;
-+typedef struct dwc_otg_hcd dwc_otg_hcd_t;
-+
-+struct dwc_otg_hcd_urb;
-+typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
-+
-+/** @name HCD Function Driver Callbacks */
-+/** @{ */
-+
-+/** This function is called whenever core switches to host mode. */
-+typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
-+
-+/** This function is called when device has been disconnected */
-+typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
-+
-+/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
-+typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+						   void *urb_handle,
-+						   uint32_t * hub_addr,
-+						   uint32_t * port_addr);
-+/** Via this function HCD core gets device speed */
-+typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+						void *urb_handle);
-+
-+/** This function is called when urb is completed */
-+typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
-+					      void *urb_handle,
-+					      dwc_otg_hcd_urb_t * dwc_otg_urb,
-+					      int32_t status);
-+
-+/** Via this function HCD core gets b_hnp_enable parameter */
-+typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
-+
-+struct dwc_otg_hcd_function_ops {
-+	dwc_otg_hcd_start_cb_t start;
-+	dwc_otg_hcd_disconnect_cb_t disconnect;
-+	dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
-+	dwc_otg_hcd_speed_from_urb_cb_t speed;
-+	dwc_otg_hcd_complete_urb_cb_t complete;
-+	dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
-+};
-+/** @} */
-+
-+/** @name HCD Core API */
-+/** @{ */
-+/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
-+extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
-+
-+/** This function should be called to initiate HCD Core.
-+ *
-+ * @param hcd The HCD
-+ * @param core_if The DWC_OTG Core
-+ *
-+ * Returns -DWC_E_NO_MEMORY if no enough memory.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
-+
-+/** Frees HCD
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
-+
-+/** This function should be called on every hardware interrupt.
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ *
-+ * Returns non zero if interrupt is handled
-+ * Return 0 if interrupt is not handled
-+ */
-+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
-+
-+/** This function is used to handle the fast interrupt
-+ *
-+ */
-+extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);
-+
-+/**
-+ * Returns private data set by
-+ * dwc_otg_hcd_set_priv_data function.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Set private data.
-+ *
-+ * @param hcd The HCD
-+ * @param priv_data pointer to be stored in private data
-+ */
-+extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
-+
-+/**
-+ * This function initializes the HCD Core.
-+ *
-+ * @param hcd The HCD
-+ * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
-+ *
-+ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
-+			     struct dwc_otg_hcd_function_ops *fops);
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Handles hub class-specific requests.
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param typeReq Request Type
-+ * @param wValue wValue from control request
-+ * @param wIndex wIndex from control request
-+ * @param buf data buffer
-+ * @param wLength data buffer length
-+ *
-+ * Returns -DWC_E_INVALID if invalid argument is passed
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
-+				   uint16_t typeReq, uint16_t wValue,
-+				   uint16_t wIndex, uint8_t * buf,
-+				   uint16_t wLength);
-+
-+/**
-+ * Returns otg port number.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Returns OTG version - either 1.3 or 2.0.
-+ *
-+ * @param core_if The core_if structure pointer
-+ */
-+extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
-+
-+/**
-+ * Returns 1 if currently core is acting as B host, and 0 otherwise.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Returns current frame number.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Dumps hcd state.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Dump the average frame remaining at SOF. This can be used to
-+ * determine average interrupt latency. Frame remaining is also shown for
-+ * start transfer and two additional sample points.
-+ * Currently this function is not implemented.
-+ *
-+ * @param hcd The HCD
-+ */
-+extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
-+
-+/**
-+ * Sends LPM transaction to the local device.
-+ *
-+ * @param hcd The HCD
-+ * @param devaddr Device Address
-+ * @param hird Host initiated resume duration
-+ * @param bRemoteWake Value of bRemoteWake field in LPM transaction
-+ *
-+ * Returns negative value if sending LPM transaction was not succeeded.
-+ * Returns 0 on success.
-+ */
-+extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
-+				uint8_t hird, uint8_t bRemoteWake);
-+
-+/* URB interface */
-+
-+/**
-+ * Allocates memory for dwc_otg_hcd_urb structure.
-+ * Allocated memory should be freed by call of DWC_FREE.
-+ *
-+ * @param hcd The HCD
-+ * @param iso_desc_count Count of ISOC descriptors
-+ * @param atomic_alloc Specefies whether to perform atomic allocation.
-+ */
-+extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
-+						int iso_desc_count,
-+						int atomic_alloc);
-+
-+/**
-+ * Set pipe information in URB.
-+ *
-+ * @param hcd_urb DWC_OTG URB
-+ * @param devaddr Device Address
-+ * @param ep_num Endpoint Number
-+ * @param ep_type Endpoint Type
-+ * @param ep_dir Endpoint Direction
-+ * @param mps Max Packet Size
-+ */
-+extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
-+					 uint8_t devaddr, uint8_t ep_num,
-+					 uint8_t ep_type, uint8_t ep_dir,
-+					 uint16_t mps);
-+
-+/* Transfer flags */
-+#define URB_GIVEBACK_ASAP 0x1
-+#define URB_SEND_ZERO_PACKET 0x2
-+
-+/**
-+ * Sets dwc_otg_hcd_urb parameters.
-+ *
-+ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
-+ * @param urb_handle Unique handle for request, this will be passed back
-+ * to function driver in completion callback.
-+ * @param buf The buffer for the data
-+ * @param dma The DMA buffer for the data
-+ * @param buflen Transfer length
-+ * @param sp Buffer for setup data
-+ * @param sp_dma DMA address of setup data buffer
-+ * @param flags Transfer flags
-+ * @param interval Polling interval for interrupt or isochronous transfers.
-+ */
-+extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
-+				       void *urb_handle, void *buf,
-+				       dwc_dma_t dma, uint32_t buflen, void *sp,
-+				       dwc_dma_t sp_dma, uint32_t flags,
-+				       uint16_t interval);
-+
-+/** Gets status from dwc_otg_hcd_urb
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
-+
-+/** Gets actual length from dwc_otg_hcd_urb
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
-+						  dwc_otg_urb);
-+
-+/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
-+						dwc_otg_urb);
-+
-+/** Set ISOC descriptor offset and length
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ * @param offset Offset from beginig of buffer.
-+ * @param length Transaction length
-+ */
-+extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
-+						int desc_num, uint32_t offset,
-+						uint32_t length);
-+
-+/** Get status of ISOC descriptor, specified by desc_num
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
-+						    dwc_otg_urb, int desc_num);
-+
-+/** Get actual length of ISOC descriptor, specified by desc_num
-+ *
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param desc_num ISOC descriptor number
-+ */
-+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
-+							   dwc_otg_urb,
-+							   int desc_num);
-+
-+/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param dwc_otg_urb DWC_OTG URB
-+ * @param ep_handle Out parameter for returning endpoint handle
-+ * @param atomic_alloc Flag to do atomic allocation if needed
-+ *
-+ * Returns -DWC_E_NO_DEVICE if no device is connected.
-+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
-+ * Returns 0 on success.
-+ */
-+extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
-+				   dwc_otg_hcd_urb_t * dwc_otg_urb,
-+				   void **ep_handle, int atomic_alloc);
-+
-+/** De-queue the specified URB
-+ *
-+ * @param dwc_otg_hcd The HCD
-+ * @param dwc_otg_urb DWC_OTG URB
-+ */
-+extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
-+				   dwc_otg_hcd_urb_t * dwc_otg_urb);
-+
-+/** Frees resources in the DWC_otg controller related to a given endpoint.
-+ * Any URBs for the endpoint must already be dequeued.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
-+ * @param retry Number of retries if there are queued transfers.
-+ *
-+ * Returns -DWC_E_INVALID if invalid arguments are passed.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
-+					int retry);
-+
-+/* Resets the data toggle in qh structure. This function can be called from
-+ * usb_clear_halt routine.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
-+ *
-+ * Returns -DWC_E_INVALID if invalid arguments are passed.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
-+
-+/** Returns 1 if status of specified port is changed and 0 otherwise.
-+ *
-+ * @param hcd The HCD
-+ * @param port Port number
-+ */
-+extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
-+
-+/** Call this function to check if bandwidth was allocated for specified endpoint.
-+ * Only for ISOC and INTERRUPT endpoints.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
-+					      void *ep_handle);
-+
-+/** Call this function to check if bandwidth was freed for specified endpoint.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
-+
-+/** Returns bandwidth allocated for specified endpoint in microseconds.
-+ * Only for ISOC and INTERRUPT endpoints.
-+ *
-+ * @param hcd The HCD
-+ * @param ep_handle Endpoint handle
-+ */
-+extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
-+					    void *ep_handle);
-+
-+/** @} */
-+
-+#endif /* __DWC_HCD_IF_H__ */
-+#endif /* DWC_DEVICE_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
-@@ -0,0 +1,2752 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
-+ * $Revision: #89 $
-+ * $Date: 2011/10/20 $
-+ * $Change: 1869487 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+#include <linux/jiffies.h>
-+#include <asm/fiq.h>
-+
-+
-+extern bool microframe_schedule;
-+
-+/** @file
-+ * This file contains the implementation of the HCD Interrupt handlers.
-+ */
-+
-+int fiq_done, int_done;
-+
-+#ifdef FIQ_DEBUG
-+char buffer[1000*16];
-+int wptr;
-+void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...)
-+{
-+	FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB;
-+	va_list args;
-+	char text[17];
-+	hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) };
-+
-+	if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR)
-+	{
-+		local_fiq_disable();
-+		snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937);
-+		va_start(args, fmt);
-+		vsnprintf(text+8, 9, fmt, args);
-+		va_end(args);
-+
-+		memcpy(buffer + wptr, text, 16);
-+		wptr = (wptr + 16) % sizeof(buffer);
-+		local_fiq_enable();
-+	}
-+}
-+#endif
-+
-+/** This function handles interrupts for the HCD. */
-+int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	int retval = 0;
-+	static int last_time;
-+	dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
-+	gintsts_data_t gintsts;
-+	gintmsk_data_t gintmsk;
-+	hfnum_data_t hfnum;
-+	haintmsk_data_t haintmsk;
-+
-+#ifdef DEBUG
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+
-+#endif
-+
-+	gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+	gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+	/* Exit from ISR if core is hibernated */
-+	if (core_if->hibernation_suspend == 1) {
-+		goto exit_handler_routine;
-+	}
-+	DWC_SPINLOCK(dwc_otg_hcd->lock);
-+	/* Check if HOST Mode */
-+	if (dwc_otg_is_host_mode(core_if)) {
-+		if (fiq_enable) {
-+			local_fiq_disable();
-+			fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+			/* Pull in from the FIQ's disabled mask */
-+			gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32);
-+			dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0;
-+		}
-+
-+		if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) {
-+			gintsts.b.hcintr = 1;
-+		}
-+
-+		/* Danger will robinson: fake a SOF if necessary */
-+		if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) {
-+			gintsts.b.sofintr = 1;
-+		}
-+		gintsts.d32 &= gintmsk.d32;
-+
-+		if (fiq_enable) {
-+			fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+			local_fiq_enable();
-+		}
-+
-+		if (!gintsts.d32) {
-+			goto exit_handler_routine;
-+		}
-+
-+#ifdef DEBUG
-+		// We should be OK doing this because the common interrupts should already have been serviced
-+		/* Don't print debug message in the interrupt handler on SOF */
-+#ifndef DEBUG_SOF
-+		if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+			DWC_DEBUGPL(DBG_HCDI, "\n");
-+#endif
-+
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+		if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+			DWC_DEBUGPL(DBG_HCDI,
-+				    "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
-+				    gintsts.d32, core_if);
-+#endif
-+		hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);
-+		if (gintsts.b.sofintr) {
-+			retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
-+		}
-+
-+		if (gintsts.b.rxstsqlvl) {
-+			retval |=
-+			    dwc_otg_hcd_handle_rx_status_q_level_intr
-+			    (dwc_otg_hcd);
-+		}
-+		if (gintsts.b.nptxfempty) {
-+			retval |=
-+			    dwc_otg_hcd_handle_np_tx_fifo_empty_intr
-+			    (dwc_otg_hcd);
-+		}
-+		if (gintsts.b.i2cintr) {
-+			/** @todo Implement i2cintr handler. */
-+		}
-+		if (gintsts.b.portintr) {
-+
-+			gintmsk_data_t gintmsk = { .b.portintr = 1};
-+			retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
-+			if (fiq_enable) {
-+				local_fiq_disable();
-+				fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+				DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+				fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+				local_fiq_enable();
-+			} else {
-+				DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
-+			}
-+		}
-+		if (gintsts.b.hcintr) {
-+			retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
-+		}
-+		if (gintsts.b.ptxfempty) {
-+			retval |=
-+			    dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
-+			    (dwc_otg_hcd);
-+		}
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+		if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+		{
-+			DWC_DEBUGPL(DBG_HCDI,
-+				    "DWC OTG HCD Finished Servicing Interrupts\n");
-+			DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
-+				    DWC_READ_REG32(&global_regs->gintsts));
-+			DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
-+				    DWC_READ_REG32(&global_regs->gintmsk));
-+		}
-+#endif
-+
-+#ifdef DEBUG
-+#ifndef DEBUG_SOF
-+		if (gintsts.d32 != DWC_SOF_INTR_MASK)
-+#endif
-+			DWC_DEBUGPL(DBG_HCDI, "\n");
-+#endif
-+
-+	}
-+
-+exit_handler_routine:
-+	if (fiq_enable)	{
-+		gintmsk_data_t gintmsk_new;
-+		haintmsk_data_t haintmsk_new;
-+		local_fiq_disable();
-+		fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+		gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32;
-+		if(fiq_fsm_enable)
-+			haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32;
-+		else
-+			haintmsk_new.d32 = 0x0000FFFF;
-+
-+		/* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */
-+		if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {
-+				DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));
-+				if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
-+					fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
-+					DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));
-+					while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))
-+						;
-+					DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));
-+					dwc_otg_hcd->fiq_state->mphi_int_count = 0;
-+				}
-+				int_done++;
-+		}
-+		haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
-+		/* Re-enable interrupts that the FIQ masked (first time round) */
-+		FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32);
-+		fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+		local_fiq_enable();
-+
-+		if ((jiffies / HZ) > last_time) {
-+			//dwc_otg_qh_t *qh;
-+			//dwc_list_link_t *cur;
-+			/* Once a second output the fiq and irq numbers, useful for debug */
-+			last_time = jiffies / HZ;
-+		//	 DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d",
-+		//	dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels,
-+		//	dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done);
-+			 //printk(KERN_WARNING "Periodic queues:\n");
-+		}
-+	}
-+
-+	DWC_SPINUNLOCK(dwc_otg_hcd->lock);
-+	return retval;
-+}
-+
-+#ifdef DWC_TRACK_MISSED_SOFS
-+
-+#warning Compiling code to track missed SOFs
-+#define FRAME_NUM_ARRAY_SIZE 1000
-+/**
-+ * This function is for debug only.
-+ */
-+static inline void track_missed_sofs(uint16_t curr_frame_number)
-+{
-+	static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
-+	static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
-+	static int frame_num_idx = 0;
-+	static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
-+	static int dumped_frame_num_array = 0;
-+
-+	if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
-+		if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
-+		    curr_frame_number) {
-+			frame_num_array[frame_num_idx] = curr_frame_number;
-+			last_frame_num_array[frame_num_idx++] = last_frame_num;
-+		}
-+	} else if (!dumped_frame_num_array) {
-+		int i;
-+		DWC_PRINTF("Frame     Last Frame\n");
-+		DWC_PRINTF("-----     ----------\n");
-+		for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
-+			DWC_PRINTF("0x%04x    0x%04x\n",
-+				   frame_num_array[i], last_frame_num_array[i]);
-+		}
-+		dumped_frame_num_array = 1;
-+	}
-+	last_frame_num = curr_frame_number;
-+}
-+#endif
-+
-+/**
-+ * Handles the start-of-frame interrupt in host mode. Non-periodic
-+ * transactions may be queued to the DWC_otg controller for the current
-+ * (micro)frame. Periodic transactions may be queued to the controller for the
-+ * next (micro)frame.
-+ */
-+int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
-+{
-+	hfnum_data_t hfnum;
-+	gintsts_data_t gintsts = { .d32 = 0 };
-+	dwc_list_link_t *qh_entry;
-+	dwc_otg_qh_t *qh;
-+	dwc_otg_transaction_type_e tr_type;
-+	int did_something = 0;
-+	int32_t next_sched_frame = -1;
-+
-+	hfnum.d32 =
-+	    DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
-+
-+#ifdef DEBUG_SOF
-+	DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
-+#endif
-+	hcd->frame_number = hfnum.b.frnum;
-+
-+#ifdef DEBUG
-+	hcd->frrem_accum += hfnum.b.frrem;
-+	hcd->frrem_samples++;
-+#endif
-+
-+#ifdef DWC_TRACK_MISSED_SOFS
-+	track_missed_sofs(hcd->frame_number);
-+#endif
-+	/* Determine whether any periodic QHs should be executed. */
-+	qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
-+	while (qh_entry != &hcd->periodic_sched_inactive) {
-+		qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
-+		qh_entry = qh_entry->next;
-+		if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
-+
-+			/*
-+			 * Move QH to the ready list to be executed next
-+			 * (micro)frame.
-+			 */
-+			DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
-+					   &qh->qh_list_entry);
-+
-+			did_something = 1;
-+		}
-+		else
-+		{
-+			if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))
-+			{
-+				next_sched_frame = qh->sched_frame;
-+			}
-+		}
-+	}
-+	if (fiq_enable)
-+		hcd->fiq_state->next_sched_frame = next_sched_frame;
-+
-+	tr_type = dwc_otg_hcd_select_transactions(hcd);
-+	if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+		dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+		did_something = 1;
-+	}
-+
-+	/* Clear interrupt - but do not trample on the FIQ sof */
-+	if (!fiq_fsm_enable) {
-+		gintsts.b.sofintr = 1;
-+		DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
-+	}
-+	return 1;
-+}
-+
-+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
-+ * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
-+ * memory if the DWC_otg controller is operating in Slave mode. */
-+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	host_grxsts_data_t grxsts;
-+	dwc_hc_t *hc = NULL;
-+
-+	DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
-+
-+	grxsts.d32 =
-+	    DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
-+
-+	hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
-+	if (!hc) {
-+		DWC_ERROR("Unable to get corresponding channel\n");
-+		return 0;
-+	}
-+
-+	/* Packet Status */
-+	DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
-+	DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
-+	DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
-+		    hc->data_pid_start);
-+	DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
-+
-+	switch (grxsts.b.pktsts) {
-+	case DWC_GRXSTS_PKTSTS_IN:
-+		/* Read the data into the host buffer. */
-+		if (grxsts.b.bcnt > 0) {
-+			dwc_otg_read_packet(dwc_otg_hcd->core_if,
-+					    hc->xfer_buff, grxsts.b.bcnt);
-+
-+			/* Update the HC fields for the next packet received. */
-+			hc->xfer_count += grxsts.b.bcnt;
-+			hc->xfer_buff += grxsts.b.bcnt;
-+		}
-+
-+	case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
-+	case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
-+	case DWC_GRXSTS_PKTSTS_CH_HALTED:
-+		/* Handled in interrupt, just ignore data */
-+		break;
-+	default:
-+		DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
-+			  grxsts.b.pktsts);
-+		break;
-+	}
-+
-+	return 1;
-+}
-+
-+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
-+ * data packets may be written to the FIFO for OUT transfers. More requests
-+ * may be written to the non-periodic request queue for IN transfers. This
-+ * interrupt is enabled only in Slave mode. */
-+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
-+	dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
-+				       DWC_OTG_TRANSACTION_NON_PERIODIC);
-+	return 1;
-+}
-+
-+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
-+ * packets may be written to the FIFO for OUT transfers. More requests may be
-+ * written to the periodic request queue for IN transfers. This interrupt is
-+ * enabled only in Slave mode. */
-+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
-+	dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
-+				       DWC_OTG_TRANSACTION_PERIODIC);
-+	return 1;
-+}
-+
-+/** There are multiple conditions that can cause a port interrupt. This function
-+ * determines which interrupt conditions have occurred and handles them
-+ * appropriately. */
-+int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	int retval = 0;
-+	hprt0_data_t hprt0;
-+	hprt0_data_t hprt0_modify;
-+
-+	hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+	hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+
-+	/* Clear appropriate bits in HPRT0 to clear the interrupt bit in
-+	 * GINTSTS */
-+
-+	hprt0_modify.b.prtena = 0;
-+	hprt0_modify.b.prtconndet = 0;
-+	hprt0_modify.b.prtenchng = 0;
-+	hprt0_modify.b.prtovrcurrchng = 0;
-+
-+	/* Port Connect Detected
-+	 * Set flag and clear if detected */
-+	if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
-+		// Dont modify port status if we are in hibernation state
-+		hprt0_modify.b.prtconndet = 1;
-+		hprt0_modify.b.prtenchng = 1;
-+		DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
-+		hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+		return retval;
-+	}
-+
-+	if (hprt0.b.prtconndet) {
-+		/** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
-+		if (dwc_otg_hcd->core_if->adp_enable &&
-+				dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
-+			DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
-+			DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
-+			dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
-+			/* TODO - check if this is required, as
-+			 * host initialization was already performed
-+			 * after initial ADP probing
-+			 */
-+			/*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
-+			dwc_otg_core_init(dwc_otg_hcd->core_if);
-+			dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
-+			cil_hcd_start(dwc_otg_hcd->core_if);*/
-+		} else {
-+
-+			DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
-+				    "Port Connect Detected--\n", hprt0.d32);
-+			dwc_otg_hcd->flags.b.port_connect_status_change = 1;
-+			dwc_otg_hcd->flags.b.port_connect_status = 1;
-+			hprt0_modify.b.prtconndet = 1;
-+
-+			/* B-Device has connected, Delete the connection timer. */
-+			DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
-+		}
-+		/* The Hub driver asserts a reset when it sees port connect
-+		 * status change flag */
-+		retval |= 1;
-+	}
-+
-+	/* Port Enable Changed
-+	 * Clear if detected - Set internal flag if disabled */
-+	if (hprt0.b.prtenchng) {
-+		DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
-+			    "Port Enable Changed--\n", hprt0.d32);
-+		hprt0_modify.b.prtenchng = 1;
-+		if (hprt0.b.prtena == 1) {
-+			hfir_data_t hfir;
-+			int do_reset = 0;
-+			dwc_otg_core_params_t *params =
-+			    dwc_otg_hcd->core_if->core_params;
-+			dwc_otg_core_global_regs_t *global_regs =
-+			    dwc_otg_hcd->core_if->core_global_regs;
-+			dwc_otg_host_if_t *host_if =
-+			    dwc_otg_hcd->core_if->host_if;
-+
-+			dwc_otg_hcd->flags.b.port_speed = hprt0.b.prtspd;
-+			if (microframe_schedule)
-+				init_hcd_usecs(dwc_otg_hcd);
-+
-+			/* Every time when port enables calculate
-+			 * HFIR.FrInterval
-+			 */
-+			hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
-+			hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
-+			DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
-+
-+			/* Check if we need to adjust the PHY clock speed for
-+			 * low power and adjust it */
-+			if (params->host_support_fs_ls_low_power) {
-+				gusbcfg_data_t usbcfg;
-+
-+				usbcfg.d32 =
-+				    DWC_READ_REG32(&global_regs->gusbcfg);
-+
-+				if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
-+				    || hprt0.b.prtspd ==
-+				    DWC_HPRT0_PRTSPD_FULL_SPEED) {
-+					/*
-+					 * Low power
-+					 */
-+					hcfg_data_t hcfg;
-+					if (usbcfg.b.phylpwrclksel == 0) {
-+						/* Set PHY low power clock select for FS/LS devices */
-+						usbcfg.b.phylpwrclksel = 1;
-+						DWC_WRITE_REG32
-+						    (&global_regs->gusbcfg,
-+						     usbcfg.d32);
-+						do_reset = 1;
-+					}
-+
-+					hcfg.d32 =
-+					    DWC_READ_REG32
-+					    (&host_if->host_global_regs->hcfg);
-+
-+					if (hprt0.b.prtspd ==
-+					    DWC_HPRT0_PRTSPD_LOW_SPEED
-+					    && params->host_ls_low_power_phy_clk
-+					    ==
-+					    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
-+					{
-+						/* 6 MHZ */
-+						DWC_DEBUGPL(DBG_CIL,
-+							    "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
-+						if (hcfg.b.fslspclksel !=
-+						    DWC_HCFG_6_MHZ) {
-+							hcfg.b.fslspclksel =
-+							    DWC_HCFG_6_MHZ;
-+							DWC_WRITE_REG32
-+							    (&host_if->host_global_regs->hcfg,
-+							     hcfg.d32);
-+							do_reset = 1;
-+						}
-+					} else {
-+						/* 48 MHZ */
-+						DWC_DEBUGPL(DBG_CIL,
-+							    "FS_PHY programming HCFG to 48 MHz ()\n");
-+						if (hcfg.b.fslspclksel !=
-+						    DWC_HCFG_48_MHZ) {
-+							hcfg.b.fslspclksel =
-+							    DWC_HCFG_48_MHZ;
-+							DWC_WRITE_REG32
-+							    (&host_if->host_global_regs->hcfg,
-+							     hcfg.d32);
-+							do_reset = 1;
-+						}
-+					}
-+				} else {
-+					/*
-+					 * Not low power
-+					 */
-+					if (usbcfg.b.phylpwrclksel == 1) {
-+						usbcfg.b.phylpwrclksel = 0;
-+						DWC_WRITE_REG32
-+						    (&global_regs->gusbcfg,
-+						     usbcfg.d32);
-+						do_reset = 1;
-+					}
-+				}
-+
-+				if (do_reset) {
-+					DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
-+				}
-+			}
-+
-+			if (!do_reset) {
-+				/* Port has been enabled set the reset change flag */
-+				dwc_otg_hcd->flags.b.port_reset_change = 1;
-+			}
-+		} else {
-+			dwc_otg_hcd->flags.b.port_enable_change = 1;
-+		}
-+		retval |= 1;
-+	}
-+
-+	/** Overcurrent Change Interrupt */
-+	if (hprt0.b.prtovrcurrchng) {
-+		DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
-+			    "Port Overcurrent Changed--\n", hprt0.d32);
-+		dwc_otg_hcd->flags.b.port_over_current_change = 1;
-+		hprt0_modify.b.prtovrcurrchng = 1;
-+		retval |= 1;
-+	}
-+
-+	/* Clear Port Interrupts */
-+	DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
-+
-+	return retval;
-+}
-+
-+/** This interrupt indicates that one or more host channels has a pending
-+ * interrupt. There are multiple conditions that can cause each host channel
-+ * interrupt. This function determines which conditions have occurred for each
-+ * host channel interrupt and handles them appropriately. */
-+int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	int i;
-+	int retval = 0;
-+	haint_data_t haint = { .d32 = 0 } ;
-+
-+	/* Clear appropriate bits in HCINTn to clear the interrupt bit in
-+	 * GINTSTS */
-+
-+	if (!fiq_fsm_enable)
-+		haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
-+
-+	// Overwrite with saved interrupts from fiq handler
-+	if(fiq_fsm_enable)
-+	{
-+		/* check the mask? */
-+		local_fiq_disable();
-+		fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
-+		haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint);
-+		dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
-+		fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
-+		local_fiq_enable();
-+	}
-+
-+	for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
-+		if (haint.b2.chint & (1 << i)) {
-+			retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
-+		}
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * Gets the actual length of a transfer after the transfer halts. _halt_status
-+ * holds the reason for the halt.
-+ *
-+ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
-+ * *short_read is set to 1 upon return if less than the requested
-+ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
-+ * return. short_read may also be NULL on entry, in which case it remains
-+ * unchanged.
-+ */
-+static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
-+				       dwc_otg_hc_regs_t * hc_regs,
-+				       dwc_otg_qtd_t * qtd,
-+				       dwc_otg_halt_status_e halt_status,
-+				       int *short_read)
-+{
-+	hctsiz_data_t hctsiz;
-+	uint32_t length;
-+
-+	if (short_read != NULL) {
-+		*short_read = 0;
-+	}
-+	hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+
-+	if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
-+		if (hc->ep_is_in) {
-+			length = hc->xfer_len - hctsiz.b.xfersize;
-+			if (short_read != NULL) {
-+				*short_read = (hctsiz.b.xfersize != 0);
-+			}
-+		} else if (hc->qh->do_split) {
-+				//length = split_out_xfersize[hc->hc_num];
-+				length = qtd->ssplit_out_xfer_count;
-+		} else {
-+			length = hc->xfer_len;
-+		}
-+	} else {
-+		/*
-+		 * Must use the hctsiz.pktcnt field to determine how much data
-+		 * has been transferred. This field reflects the number of
-+		 * packets that have been transferred via the USB. This is
-+		 * always an integral number of packets if the transfer was
-+		 * halted before its normal completion. (Can't use the
-+		 * hctsiz.xfersize field because that reflects the number of
-+		 * bytes transferred via the AHB, not the USB).
-+		 */
-+		length =
-+		    (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
-+	}
-+
-+	return length;
-+}
-+
-+/**
-+ * Updates the state of the URB after a Transfer Complete interrupt on the
-+ * host channel. Updates the actual_length field of the URB based on the
-+ * number of bytes transferred via the host channel. Sets the URB status
-+ * if the data transfer is finished.
-+ *
-+ * @return 1 if the data transfer specified by the URB is completely finished,
-+ * 0 otherwise.
-+ */
-+static int update_urb_state_xfer_comp(dwc_hc_t * hc,
-+				      dwc_otg_hc_regs_t * hc_regs,
-+				      dwc_otg_hcd_urb_t * urb,
-+				      dwc_otg_qtd_t * qtd)
-+{
-+	int xfer_done = 0;
-+	int short_read = 0;
-+
-+	int xfer_length;
-+
-+	xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
-+					     DWC_OTG_HC_XFER_COMPLETE,
-+					     &short_read);
-+
-+	if (urb->actual_length + xfer_length > urb->length) {
-+		printk_once(KERN_DEBUG "dwc_otg: DEVICE:%03d : %s:%d:trimming xfer length\n",
-+			hc->dev_addr, __func__, __LINE__);
-+		xfer_length = urb->length - urb->actual_length;
-+	}
-+
-+	/* non DWORD-aligned buffer case handling. */
-+	if (hc->align_buff && xfer_length && hc->ep_is_in) {
-+		dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
-+			   xfer_length);
-+	}
-+
-+	urb->actual_length += xfer_length;
-+
-+	if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
-+	    (urb->flags & URB_SEND_ZERO_PACKET)
-+	    && (urb->actual_length == urb->length)
-+	    && !(urb->length % hc->max_packet)) {
-+		xfer_done = 0;
-+	} else if (short_read || urb->actual_length >= urb->length) {
-+		xfer_done = 1;
-+		urb->status = 0;
-+	}
-+
-+#ifdef DEBUG
-+	{
-+		hctsiz_data_t hctsiz;
-+		hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+		DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
-+			    __func__, (hc->ep_is_in ? "IN" : "OUT"),
-+			    hc->hc_num);
-+		DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
-+		DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
-+			    hctsiz.b.xfersize);
-+		DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
-+			    urb->length);
-+		DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
-+			    urb->actual_length);
-+		DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
-+			    short_read, xfer_done);
-+	}
-+#endif
-+
-+	return xfer_done;
-+}
-+
-+/*
-+ * Save the starting data toggle for the next transfer. The data toggle is
-+ * saved in the QH for non-control transfers and it's saved in the QTD for
-+ * control transfers.
-+ */
-+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
-+			     dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
-+{
-+	hctsiz_data_t hctsiz;
-+	hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+
-+	if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
-+		dwc_otg_qh_t *qh = hc->qh;
-+		if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
-+			qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+		} else {
-+			qh->data_toggle = DWC_OTG_HC_PID_DATA1;
-+		}
-+	} else {
-+		if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
-+			qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
-+		} else {
-+			qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
-+		}
-+	}
-+}
-+
-+/**
-+ * Updates the state of an Isochronous URB when the transfer is stopped for
-+ * any reason. The fields of the current entry in the frame descriptor array
-+ * are set based on the transfer state and the input _halt_status. Completes
-+ * the Isochronous URB if all the URB frames have been completed.
-+ *
-+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
-+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
-+ */
-+static dwc_otg_halt_status_e
-+update_isoc_urb_state(dwc_otg_hcd_t * hcd,
-+		      dwc_hc_t * hc,
-+		      dwc_otg_hc_regs_t * hc_regs,
-+		      dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
-+{
-+	dwc_otg_hcd_urb_t *urb = qtd->urb;
-+	dwc_otg_halt_status_e ret_val = halt_status;
-+	struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+
-+	frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
-+	switch (halt_status) {
-+	case DWC_OTG_HC_XFER_COMPLETE:
-+		frame_desc->status = 0;
-+		frame_desc->actual_length =
-+		    get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
-+
-+		/* non DWORD-aligned buffer case handling. */
-+		if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
-+			dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
-+				   hc->qh->dw_align_buf, frame_desc->actual_length);
-+		}
-+
-+		break;
-+	case DWC_OTG_HC_XFER_FRAME_OVERRUN:
-+		urb->error_count++;
-+		if (hc->ep_is_in) {
-+			frame_desc->status = -DWC_E_NO_STREAM_RES;
-+		} else {
-+			frame_desc->status = -DWC_E_COMMUNICATION;
-+		}
-+		frame_desc->actual_length = 0;
-+		break;
-+	case DWC_OTG_HC_XFER_BABBLE_ERR:
-+		urb->error_count++;
-+		frame_desc->status = -DWC_E_OVERFLOW;
-+		/* Don't need to update actual_length in this case. */
-+		break;
-+	case DWC_OTG_HC_XFER_XACT_ERR:
-+		urb->error_count++;
-+		frame_desc->status = -DWC_E_PROTOCOL;
-+		frame_desc->actual_length =
-+		    get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
-+
-+		/* non DWORD-aligned buffer case handling. */
-+		if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
-+			dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
-+				   hc->qh->dw_align_buf, frame_desc->actual_length);
-+		}
-+		/* Skip whole frame */
-+		if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
-+		    hc->ep_is_in && hcd->core_if->dma_enable) {
-+			qtd->complete_split = 0;
-+			qtd->isoc_split_offset = 0;
-+		}
-+
-+		break;
-+	default:
-+		DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
-+		break;
-+	}
-+	if (++qtd->isoc_frame_index == urb->packet_count) {
-+		/*
-+		 * urb->status is not used for isoc transfers.
-+		 * The individual frame_desc statuses are used instead.
-+		 */
-+		hcd->fops->complete(hcd, urb->priv, urb, 0);
-+		ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
-+	} else {
-+		ret_val = DWC_OTG_HC_XFER_COMPLETE;
-+	}
-+	return ret_val;
-+}
-+
-+/**
-+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
-+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
-+ * still linked to the QH, the QH is added to the end of the inactive
-+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic
-+ * schedule if no more QTDs are linked to the QH.
-+ */
-+static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
-+{
-+	int continue_split = 0;
-+	dwc_otg_qtd_t *qtd;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
-+
-+	qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
-+
-+	if (qtd->complete_split) {
-+		continue_split = 1;
-+	} else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
-+		   qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
-+		continue_split = 1;
-+	}
-+
-+	if (free_qtd) {
-+		dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
-+		continue_split = 0;
-+	}
-+
-+	qh->channel = NULL;
-+	dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
-+}
-+
-+/**
-+ * Releases a host channel for use by other transfers. Attempts to select and
-+ * queue more transactions since at least one host channel is available.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param hc The host channel to release.
-+ * @param qtd The QTD associated with the host channel. This QTD may be freed
-+ * if the transfer is complete or an error has occurred.
-+ * @param halt_status Reason the channel is being released. This status
-+ * determines the actions taken by this function.
-+ */
-+static void release_channel(dwc_otg_hcd_t * hcd,
-+			    dwc_hc_t * hc,
-+			    dwc_otg_qtd_t * qtd,
-+			    dwc_otg_halt_status_e halt_status)
-+{
-+	dwc_otg_transaction_type_e tr_type;
-+	int free_qtd;
-+
-+	int hog_port = 0;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d, xfer_len %d\n",
-+		    __func__, hc->hc_num, halt_status, hc->xfer_len);
-+
-+	if(fiq_fsm_enable && hc->do_split) {
-+		if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) {
-+			if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID ||
-+					hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) {
-+				hog_port = 0;
-+			}
-+		}
-+	}
-+
-+	switch (halt_status) {
-+	case DWC_OTG_HC_XFER_URB_COMPLETE:
-+		free_qtd = 1;
-+		break;
-+	case DWC_OTG_HC_XFER_AHB_ERR:
-+	case DWC_OTG_HC_XFER_STALL:
-+	case DWC_OTG_HC_XFER_BABBLE_ERR:
-+		free_qtd = 1;
-+		break;
-+	case DWC_OTG_HC_XFER_XACT_ERR:
-+		if (qtd->error_count >= 3) {
-+			DWC_DEBUGPL(DBG_HCDV,
-+				    "  Complete URB with transaction error\n");
-+			free_qtd = 1;
-+			qtd->urb->status = -DWC_E_PROTOCOL;
-+			hcd->fops->complete(hcd, qtd->urb->priv,
-+					    qtd->urb, -DWC_E_PROTOCOL);
-+		} else {
-+			free_qtd = 0;
-+		}
-+		break;
-+	case DWC_OTG_HC_XFER_URB_DEQUEUE:
-+		/*
-+		 * The QTD has already been removed and the QH has been
-+		 * deactivated. Don't want to do anything except release the
-+		 * host channel and try to queue more transfers.
-+		 */
-+		goto cleanup;
-+	case DWC_OTG_HC_XFER_NO_HALT_STATUS:
-+		free_qtd = 0;
-+		break;
-+	case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
-+		DWC_DEBUGPL(DBG_HCDV,
-+			"  Complete URB with I/O error\n");
-+		free_qtd = 1;
-+		qtd->urb->status = -DWC_E_IO;
-+		hcd->fops->complete(hcd, qtd->urb->priv,
-+			qtd->urb, -DWC_E_IO);
-+		break;
-+	default:
-+		free_qtd = 0;
-+		break;
-+	}
-+
-+	deactivate_qh(hcd, hc->qh, free_qtd);
-+
-+cleanup:
-+	/*
-+	 * Release the host channel for use by other transfers. The cleanup
-+	 * function clears the channel interrupt enables and conditions, so
-+	 * there's no need to clear the Channel Halted interrupt separately.
-+	 */
-+	if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH)
-+		dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num);
-+	dwc_otg_hc_cleanup(hcd->core_if, hc);
-+	DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
-+
-+	if (!microframe_schedule) {
-+		switch (hc->ep_type) {
-+		case DWC_OTG_EP_TYPE_CONTROL:
-+		case DWC_OTG_EP_TYPE_BULK:
-+			hcd->non_periodic_channels--;
-+			break;
-+
-+		default:
-+			/*
-+			 * Don't release reservations for periodic channels here.
-+			 * That's done when a periodic transfer is descheduled (i.e.
-+			 * when the QH is removed from the periodic schedule).
-+			 */
-+			break;
-+		}
-+	} else {
-+		hcd->available_host_channels++;
-+		fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels);
-+	}
-+
-+	/* Try to queue more transfers now that there's a free channel. */
-+	tr_type = dwc_otg_hcd_select_transactions(hcd);
-+	if (tr_type != DWC_OTG_TRANSACTION_NONE) {
-+		dwc_otg_hcd_queue_transactions(hcd, tr_type);
-+	}
-+}
-+
-+/**
-+ * Halts a host channel. If the channel cannot be halted immediately because
-+ * the request queue is full, this function ensures that the FIFO empty
-+ * interrupt for the appropriate queue is enabled so that the halt request can
-+ * be queued when there is space in the request queue.
-+ *
-+ * This function may also be called in DMA mode. In that case, the channel is
-+ * simply released since the core always halts the channel automatically in
-+ * DMA mode.
-+ */
-+static void halt_channel(dwc_otg_hcd_t * hcd,
-+			 dwc_hc_t * hc,
-+			 dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
-+{
-+	if (hcd->core_if->dma_enable) {
-+		release_channel(hcd, hc, qtd, halt_status);
-+		return;
-+	}
-+
-+	/* Slave mode processing... */
-+	dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
-+
-+	if (hc->halt_on_queue) {
-+		gintmsk_data_t gintmsk = {.d32 = 0 };
-+		dwc_otg_core_global_regs_t *global_regs;
-+		global_regs = hcd->core_if->core_global_regs;
-+
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+		    hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
-+			/*
-+			 * Make sure the Non-periodic Tx FIFO empty interrupt
-+			 * is enabled so that the non-periodic schedule will
-+			 * be processed.
-+			 */
-+			gintmsk.b.nptxfempty = 1;
-+			if (fiq_enable) {
-+				local_fiq_disable();
-+				fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+				DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+				fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+				local_fiq_enable();
-+			} else {
-+				DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+			}
-+		} else {
-+			/*
-+			 * Move the QH from the periodic queued schedule to
-+			 * the periodic assigned schedule. This allows the
-+			 * halt to be queued when the periodic schedule is
-+			 * processed.
-+			 */
-+			DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
-+					   &hc->qh->qh_list_entry);
-+
-+			/*
-+			 * Make sure the Periodic Tx FIFO Empty interrupt is
-+			 * enabled so that the periodic schedule will be
-+			 * processed.
-+			 */
-+			gintmsk.b.ptxfempty = 1;
-+			if (fiq_enable) {
-+				local_fiq_disable();
-+				fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+				DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+				fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+				local_fiq_enable();
-+			} else {
-+				DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
-+			}
-+		}
-+	}
-+}
-+
-+/**
-+ * Performs common cleanup for non-periodic transfers after a Transfer
-+ * Complete interrupt. This function should be called after any endpoint type
-+ * specific handling is finished to release the host channel.
-+ */
-+static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
-+				       dwc_hc_t * hc,
-+				       dwc_otg_hc_regs_t * hc_regs,
-+				       dwc_otg_qtd_t * qtd,
-+				       dwc_otg_halt_status_e halt_status)
-+{
-+	hcint_data_t hcint;
-+
-+	qtd->error_count = 0;
-+
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+	if (hcint.b.nyet) {
-+		/*
-+		 * Got a NYET on the last transaction of the transfer. This
-+		 * means that the endpoint should be in the PING state at the
-+		 * beginning of the next transfer.
-+		 */
-+		hc->qh->ping_state = 1;
-+		clear_hc_int(hc_regs, nyet);
-+	}
-+
-+	/*
-+	 * Always halt and release the host channel to make it available for
-+	 * more transfers. There may still be more phases for a control
-+	 * transfer or more data packets for a bulk transfer at this point,
-+	 * but the host channel is still halted. A channel will be reassigned
-+	 * to the transfer when the non-periodic schedule is processed after
-+	 * the channel is released. This allows transactions to be queued
-+	 * properly via dwc_otg_hcd_queue_transactions, which also enables the
-+	 * Tx FIFO Empty interrupt if necessary.
-+	 */
-+	if (hc->ep_is_in) {
-+		/*
-+		 * IN transfers in Slave mode require an explicit disable to
-+		 * halt the channel. (In DMA mode, this call simply releases
-+		 * the channel.)
-+		 */
-+		halt_channel(hcd, hc, qtd, halt_status);
-+	} else {
-+		/*
-+		 * The channel is automatically disabled by the core for OUT
-+		 * transfers in Slave mode.
-+		 */
-+		release_channel(hcd, hc, qtd, halt_status);
-+	}
-+}
-+
-+/**
-+ * Performs common cleanup for periodic transfers after a Transfer Complete
-+ * interrupt. This function should be called after any endpoint type specific
-+ * handling is finished to release the host channel.
-+ */
-+static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
-+				   dwc_hc_t * hc,
-+				   dwc_otg_hc_regs_t * hc_regs,
-+				   dwc_otg_qtd_t * qtd,
-+				   dwc_otg_halt_status_e halt_status)
-+{
-+	hctsiz_data_t hctsiz;
-+	qtd->error_count = 0;
-+
-+	hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+	if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
-+		/* Core halts channel in these cases. */
-+		release_channel(hcd, hc, qtd, halt_status);
-+	} else {
-+		/* Flush any outstanding requests from the Tx queue. */
-+		halt_channel(hcd, hc, qtd, halt_status);
-+	}
-+}
-+
-+static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
-+					     dwc_hc_t * hc,
-+					     dwc_otg_hc_regs_t * hc_regs,
-+					     dwc_otg_qtd_t * qtd)
-+{
-+	uint32_t len;
-+	struct dwc_otg_hcd_iso_packet_desc *frame_desc;
-+	frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+
-+	len = get_actual_xfer_length(hc, hc_regs, qtd,
-+				     DWC_OTG_HC_XFER_COMPLETE, NULL);
-+
-+	if (!len) {
-+		qtd->complete_split = 0;
-+		qtd->isoc_split_offset = 0;
-+		return 0;
-+	}
-+	frame_desc->actual_length += len;
-+
-+	if (hc->align_buff && len)
-+		dwc_memcpy(qtd->urb->buf + frame_desc->offset +
-+			   qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
-+	qtd->isoc_split_offset += len;
-+
-+	if (frame_desc->length == frame_desc->actual_length) {
-+		frame_desc->status = 0;
-+		qtd->isoc_frame_index++;
-+		qtd->complete_split = 0;
-+		qtd->isoc_split_offset = 0;
-+	}
-+
-+	if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+		hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+		release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+	} else {
-+		release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+	}
-+
-+	return 1;		/* Indicates that channel released */
-+}
-+
-+/**
-+ * Handles a host channel Transfer Complete interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
-+				       dwc_hc_t * hc,
-+				       dwc_otg_hc_regs_t * hc_regs,
-+				       dwc_otg_qtd_t * qtd)
-+{
-+	int urb_xfer_done;
-+	dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+	dwc_otg_hcd_urb_t *urb = qtd->urb;
-+	int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "Transfer Complete--\n", hc->hc_num);
-+
-+	if (hcd->core_if->dma_desc_enable) {
-+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
-+		if (pipe_type == UE_ISOCHRONOUS) {
-+			/* Do not disable the interrupt, just clear it */
-+			clear_hc_int(hc_regs, xfercomp);
-+			return 1;
-+		}
-+		goto handle_xfercomp_done;
-+	}
-+
-+	/*
-+	 * Handle xfer complete on CSPLIT.
-+	 */
-+
-+	if (hc->qh->do_split) {
-+		if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
-+		    && hcd->core_if->dma_enable) {
-+			if (qtd->complete_split
-+			    && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
-+							     qtd))
-+				goto handle_xfercomp_done;
-+		} else {
-+			qtd->complete_split = 0;
-+		}
-+	}
-+
-+	/* Update the QTD and URB states. */
-+	switch (pipe_type) {
-+	case UE_CONTROL:
-+		switch (qtd->control_phase) {
-+		case DWC_OTG_CONTROL_SETUP:
-+			if (urb->length > 0) {
-+				qtd->control_phase = DWC_OTG_CONTROL_DATA;
-+			} else {
-+				qtd->control_phase = DWC_OTG_CONTROL_STATUS;
-+			}
-+			DWC_DEBUGPL(DBG_HCDV,
-+				    "  Control setup transaction done\n");
-+			halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+			break;
-+		case DWC_OTG_CONTROL_DATA:{
-+				urb_xfer_done =
-+				    update_urb_state_xfer_comp(hc, hc_regs, urb,
-+							       qtd);
-+				if (urb_xfer_done) {
-+					qtd->control_phase =
-+					    DWC_OTG_CONTROL_STATUS;
-+					DWC_DEBUGPL(DBG_HCDV,
-+						    "  Control data transfer done\n");
-+				} else {
-+					dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+				}
-+				halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+				break;
-+			}
-+		case DWC_OTG_CONTROL_STATUS:
-+			DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
-+			if (urb->status == -DWC_E_IN_PROGRESS) {
-+				urb->status = 0;
-+			}
-+			hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+			halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+			break;
-+		}
-+
-+		complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+		break;
-+	case UE_BULK:
-+		DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
-+		urb_xfer_done =
-+		    update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
-+		if (urb_xfer_done) {
-+			hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+			halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+		} else {
-+			halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+		}
-+
-+		dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+		complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+		break;
-+	case UE_INTERRUPT:
-+		DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
-+		urb_xfer_done =
-+			update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
-+
-+		/*
-+		 * Interrupt URB is done on the first transfer complete
-+		 * interrupt.
-+		 */
-+		if (urb_xfer_done) {
-+				hcd->fops->complete(hcd, urb->priv, urb, urb->status);
-+				halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
-+		} else {
-+				halt_status = DWC_OTG_HC_XFER_COMPLETE;
-+		}
-+
-+		dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+		complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+		break;
-+	case UE_ISOCHRONOUS:
-+		DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
-+		if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
-+			halt_status =
-+			    update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+						  DWC_OTG_HC_XFER_COMPLETE);
-+		}
-+		complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
-+		break;
-+	}
-+
-+handle_xfercomp_done:
-+	disable_hc_int(hc_regs, xfercompl);
-+
-+	return 1;
-+}
-+
-+/**
-+ * Handles a host channel STALL interrupt. This handler may be called in
-+ * either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
-+				    dwc_hc_t * hc,
-+				    dwc_otg_hc_regs_t * hc_regs,
-+				    dwc_otg_qtd_t * qtd)
-+{
-+	dwc_otg_hcd_urb_t *urb = qtd->urb;
-+	int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+
-+	DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
-+		    "STALL Received--\n", hc->hc_num);
-+
-+	if (hcd->core_if->dma_desc_enable) {
-+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
-+		goto handle_stall_done;
-+	}
-+
-+	if (pipe_type == UE_CONTROL) {
-+		hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
-+	}
-+
-+	if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
-+		hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
-+		/*
-+		 * USB protocol requires resetting the data toggle for bulk
-+		 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
-+		 * setup command is issued to the endpoint. Anticipate the
-+		 * CLEAR_FEATURE command since a STALL has occurred and reset
-+		 * the data toggle now.
-+		 */
-+		hc->qh->data_toggle = 0;
-+	}
-+
-+	halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
-+
-+handle_stall_done:
-+	disable_hc_int(hc_regs, stall);
-+
-+	return 1;
-+}
-+
-+/*
-+ * Updates the state of the URB when a transfer has been stopped due to an
-+ * abnormal condition before the transfer completes. Modifies the
-+ * actual_length field of the URB to reflect the number of bytes that have
-+ * actually been transferred via the host channel.
-+ */
-+static void update_urb_state_xfer_intr(dwc_hc_t * hc,
-+				       dwc_otg_hc_regs_t * hc_regs,
-+				       dwc_otg_hcd_urb_t * urb,
-+				       dwc_otg_qtd_t * qtd,
-+				       dwc_otg_halt_status_e halt_status)
-+{
-+	uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
-+							    halt_status, NULL);
-+
-+	if (urb->actual_length + bytes_transferred > urb->length) {
-+		printk_once(KERN_DEBUG "dwc_otg: DEVICE:%03d : %s:%d:trimming xfer length\n",
-+			hc->dev_addr, __func__, __LINE__);
-+		bytes_transferred = urb->length - urb->actual_length;
-+	}
-+
-+	/* non DWORD-aligned buffer case handling. */
-+	if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
-+		dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
-+			   bytes_transferred);
-+	}
-+
-+	urb->actual_length += bytes_transferred;
-+
-+#ifdef DEBUG
-+	{
-+		hctsiz_data_t hctsiz;
-+		hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+		DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
-+			    __func__, (hc->ep_is_in ? "IN" : "OUT"),
-+			    hc->hc_num);
-+		DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
-+			    hc->start_pkt_count);
-+		DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
-+		DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
-+		DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
-+			    bytes_transferred);
-+		DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
-+			    urb->actual_length);
-+		DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
-+			    urb->length);
-+	}
-+#endif
-+}
-+
-+/**
-+ * Handles a host channel NAK interrupt. This handler may be called in either
-+ * DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
-+				  dwc_hc_t * hc,
-+				  dwc_otg_hc_regs_t * hc_regs,
-+				  dwc_otg_qtd_t * qtd)
-+{
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "NAK Received--\n", hc->hc_num);
-+
-+	/*
-+	 * When we get bulk NAKs then remember this so we holdoff on this qh until
-+	 * the beginning of the next frame
-+	 */
-+	switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+		case UE_BULK:
-+		case UE_CONTROL:
-+		if (nak_holdoff && qtd->qh->do_split)
-+			hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd);
-+	}
-+
-+	/*
-+	 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
-+	 * interrupt.  Re-start the SSPLIT transfer.
-+	 */
-+	if (hc->do_split) {
-+		if (hc->complete_split) {
-+			qtd->error_count = 0;
-+		}
-+		qtd->complete_split = 0;
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+		goto handle_nak_done;
-+	}
-+
-+	switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+	case UE_CONTROL:
-+	case UE_BULK:
-+		if (hcd->core_if->dma_enable && hc->ep_is_in) {
-+			/*
-+			 * NAK interrupts are enabled on bulk/control IN
-+			 * transfers in DMA mode for the sole purpose of
-+			 * resetting the error count after a transaction error
-+			 * occurs. The core will continue transferring data.
-+			 * Disable other interrupts unmasked for the same
-+			 * reason.
-+			 */
-+			disable_hc_int(hc_regs, datatglerr);
-+			disable_hc_int(hc_regs, ack);
-+			qtd->error_count = 0;
-+			goto handle_nak_done;
-+		}
-+
-+		/*
-+		 * NAK interrupts normally occur during OUT transfers in DMA
-+		 * or Slave mode. For IN transfers, more requests will be
-+		 * queued as request queue space is available.
-+		 */
-+		qtd->error_count = 0;
-+
-+		if (!hc->qh->ping_state) {
-+			update_urb_state_xfer_intr(hc, hc_regs,
-+						   qtd->urb, qtd,
-+						   DWC_OTG_HC_XFER_NAK);
-+			dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+
-+			if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
-+				hc->qh->ping_state = 1;
-+		}
-+
-+		/*
-+		 * Halt the channel so the transfer can be re-started from
-+		 * the appropriate point or the PING protocol will
-+		 * start/continue.
-+		 */
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+		break;
-+	case UE_INTERRUPT:
-+		qtd->error_count = 0;
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
-+		break;
-+	case UE_ISOCHRONOUS:
-+		/* Should never get called for isochronous transfers. */
-+		DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
-+		break;
-+	}
-+
-+handle_nak_done:
-+	disable_hc_int(hc_regs, nak);
-+
-+	return 1;
-+}
-+
-+/**
-+ * Handles a host channel ACK interrupt. This interrupt is enabled when
-+ * performing the PING protocol in Slave mode, when errors occur during
-+ * either Slave mode or DMA mode, and during Start Split transactions.
-+ */
-+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
-+				  dwc_hc_t * hc,
-+				  dwc_otg_hc_regs_t * hc_regs,
-+				  dwc_otg_qtd_t * qtd)
-+{
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "ACK Received--\n", hc->hc_num);
-+
-+	if (hc->do_split) {
-+		/*
-+		 * Handle ACK on SSPLIT.
-+		 * ACK should not occur in CSPLIT.
-+		 */
-+		if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
-+			qtd->ssplit_out_xfer_count = hc->xfer_len;
-+		}
-+		if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
-+			/* Don't need complete for isochronous out transfers. */
-+			qtd->complete_split = 1;
-+		}
-+
-+		/* ISOC OUT */
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
-+			switch (hc->xact_pos) {
-+			case DWC_HCSPLIT_XACTPOS_ALL:
-+				break;
-+			case DWC_HCSPLIT_XACTPOS_END:
-+				qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+				qtd->isoc_split_offset = 0;
-+				break;
-+			case DWC_HCSPLIT_XACTPOS_BEGIN:
-+			case DWC_HCSPLIT_XACTPOS_MID:
-+				/*
-+				 * For BEGIN or MID, calculate the length for
-+				 * the next microframe to determine the correct
-+				 * SSPLIT token, either MID or END.
-+				 */
-+				{
-+					struct dwc_otg_hcd_iso_packet_desc
-+					*frame_desc;
-+
-+					frame_desc =
-+					    &qtd->urb->
-+					    iso_descs[qtd->isoc_frame_index];
-+					qtd->isoc_split_offset += 188;
-+
-+					if ((frame_desc->length -
-+					     qtd->isoc_split_offset) <= 188) {
-+						qtd->isoc_split_pos =
-+						    DWC_HCSPLIT_XACTPOS_END;
-+					} else {
-+						qtd->isoc_split_pos =
-+						    DWC_HCSPLIT_XACTPOS_MID;
-+					}
-+
-+				}
-+				break;
-+			}
-+		} else {
-+			halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
-+		}
-+	} else {
-+		/*
-+		 * An unmasked ACK on a non-split DMA transaction is
-+		 * for the sole purpose of resetting error counts. Disable other
-+		 * interrupts unmasked for the same reason.
-+		 */
-+		if(hcd->core_if->dma_enable) {
-+			disable_hc_int(hc_regs, datatglerr);
-+			disable_hc_int(hc_regs, nak);
-+		}
-+		qtd->error_count = 0;
-+
-+		if (hc->qh->ping_state) {
-+			hc->qh->ping_state = 0;
-+			/*
-+			 * Halt the channel so the transfer can be re-started
-+			 * from the appropriate point. This only happens in
-+			 * Slave mode. In DMA mode, the ping_state is cleared
-+			 * when the transfer is started because the core
-+			 * automatically executes the PING, then the transfer.
-+			 */
-+			halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
-+		}
-+	}
-+
-+	/*
-+	 * If the ACK occurred when _not_ in the PING state, let the channel
-+	 * continue transferring data after clearing the error count.
-+	 */
-+
-+	disable_hc_int(hc_regs, ack);
-+
-+	return 1;
-+}
-+
-+/**
-+ * Handles a host channel NYET interrupt. This interrupt should only occur on
-+ * Bulk and Control OUT endpoints and for complete split transactions. If a
-+ * NYET occurs at the same time as a Transfer Complete interrupt, it is
-+ * handled in the xfercomp interrupt handler, not here. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
-+				   dwc_hc_t * hc,
-+				   dwc_otg_hc_regs_t * hc_regs,
-+				   dwc_otg_qtd_t * qtd)
-+{
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "NYET Received--\n", hc->hc_num);
-+
-+	/*
-+	 * NYET on CSPLIT
-+	 * re-do the CSPLIT immediately on non-periodic
-+	 */
-+	if (hc->do_split && hc->complete_split) {
-+		if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
-+		    && hcd->core_if->dma_enable) {
-+			qtd->complete_split = 0;
-+			qtd->isoc_split_offset = 0;
-+			if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
-+				hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+			}
-+			else
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+			goto handle_nyet_done;
-+		}
-+
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+		    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+			int frnum = dwc_otg_hcd_get_frame_number(hcd);
-+
-+			// With the FIQ running we only ever see the failed NYET
-+			if (dwc_full_frame_num(frnum) !=
-+			    dwc_full_frame_num(hc->qh->sched_frame) ||
-+			    fiq_fsm_enable) {
-+				/*
-+				 * No longer in the same full speed frame.
-+				 * Treat this as a transaction error.
-+				 */
-+#if 0
-+				/** @todo Fix system performance so this can
-+				 * be treated as an error. Right now complete
-+				 * splits cannot be scheduled precisely enough
-+				 * due to other system activity, so this error
-+				 * occurs regularly in Slave mode.
-+				 */
-+				qtd->error_count++;
-+#endif
-+				qtd->complete_split = 0;
-+				halt_channel(hcd, hc, qtd,
-+					     DWC_OTG_HC_XFER_XACT_ERR);
-+				/** @todo add support for isoc release */
-+				goto handle_nyet_done;
-+			}
-+		}
-+
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
-+		goto handle_nyet_done;
-+	}
-+
-+	hc->qh->ping_state = 1;
-+	qtd->error_count = 0;
-+
-+	update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
-+				   DWC_OTG_HC_XFER_NYET);
-+	dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+
-+	/*
-+	 * Halt the channel and re-start the transfer so the PING
-+	 * protocol will start.
-+	 */
-+	halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
-+
-+handle_nyet_done:
-+	disable_hc_int(hc_regs, nyet);
-+	return 1;
-+}
-+
-+/**
-+ * Handles a host channel babble interrupt. This handler may be called in
-+ * either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
-+				     dwc_hc_t * hc,
-+				     dwc_otg_hc_regs_t * hc_regs,
-+				     dwc_otg_qtd_t * qtd)
-+{
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "Babble Error--\n", hc->hc_num);
-+
-+	if (hcd->core_if->dma_desc_enable) {
-+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+					       DWC_OTG_HC_XFER_BABBLE_ERR);
-+		goto handle_babble_done;
-+	}
-+
-+	if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
-+		hcd->fops->complete(hcd, qtd->urb->priv,
-+				    qtd->urb, -DWC_E_OVERFLOW);
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
-+	} else {
-+		dwc_otg_halt_status_e halt_status;
-+		halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+						    DWC_OTG_HC_XFER_BABBLE_ERR);
-+		halt_channel(hcd, hc, qtd, halt_status);
-+	}
-+
-+handle_babble_done:
-+	disable_hc_int(hc_regs, bblerr);
-+	return 1;
-+}
-+
-+/**
-+ * Handles a host channel AHB error interrupt. This handler is only called in
-+ * DMA mode.
-+ */
-+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
-+				     dwc_hc_t * hc,
-+				     dwc_otg_hc_regs_t * hc_regs,
-+				     dwc_otg_qtd_t * qtd)
-+{
-+	hcchar_data_t hcchar;
-+	hcsplt_data_t hcsplt;
-+	hctsiz_data_t hctsiz;
-+	uint32_t hcdma;
-+	char *pipetype, *speed;
-+
-+	dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "AHB Error--\n", hc->hc_num);
-+
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+	hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+	hcdma = DWC_READ_REG32(&hc_regs->hcdma);
-+
-+	DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
-+	DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
-+	DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
-+	DWC_ERROR("  Device address: %d\n",
-+		  dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
-+	DWC_ERROR("  Endpoint: %d, %s\n",
-+		  dwc_otg_hcd_get_ep_num(&urb->pipe_info),
-+		  (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
-+
-+	switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
-+	case UE_CONTROL:
-+		pipetype = "CONTROL";
-+		break;
-+	case UE_BULK:
-+		pipetype = "BULK";
-+		break;
-+	case UE_INTERRUPT:
-+		pipetype = "INTERRUPT";
-+		break;
-+	case UE_ISOCHRONOUS:
-+		pipetype = "ISOCHRONOUS";
-+		break;
-+	default:
-+		pipetype = "UNKNOWN";
-+		break;
-+	}
-+
-+	DWC_ERROR("  Endpoint type: %s\n", pipetype);
-+
-+	switch (hc->speed) {
-+	case DWC_OTG_EP_SPEED_HIGH:
-+		speed = "HIGH";
-+		break;
-+	case DWC_OTG_EP_SPEED_FULL:
-+		speed = "FULL";
-+		break;
-+	case DWC_OTG_EP_SPEED_LOW:
-+		speed = "LOW";
-+		break;
-+	default:
-+		speed = "UNKNOWN";
-+		break;
-+	};
-+
-+	DWC_ERROR("  Speed: %s\n", speed);
-+
-+	DWC_ERROR("  Max packet size: %d\n",
-+		  dwc_otg_hcd_get_mps(&urb->pipe_info));
-+	DWC_ERROR("  Data buffer length: %d\n", urb->length);
-+	DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
-+		  urb->buf, (void *)urb->dma);
-+	DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
-+		  urb->setup_packet, (void *)urb->setup_dma);
-+	DWC_ERROR("  Interval: %d\n", urb->interval);
-+
-+	/* Core haltes the channel for Descriptor DMA mode */
-+	if (hcd->core_if->dma_desc_enable) {
-+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+					       DWC_OTG_HC_XFER_AHB_ERR);
-+		goto handle_ahberr_done;
-+	}
-+
-+	hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
-+
-+	/*
-+	 * Force a channel halt. Don't call halt_channel because that won't
-+	 * write to the HCCHARn register in DMA mode to force the halt.
-+	 */
-+	dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
-+handle_ahberr_done:
-+	disable_hc_int(hc_regs, ahberr);
-+	return 1;
-+}
-+
-+/**
-+ * Handles a host channel transaction error interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
-+				      dwc_hc_t * hc,
-+				      dwc_otg_hc_regs_t * hc_regs,
-+				      dwc_otg_qtd_t * qtd)
-+{
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "Transaction Error--\n", hc->hc_num);
-+
-+	if (hcd->core_if->dma_desc_enable) {
-+		dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+					       DWC_OTG_HC_XFER_XACT_ERR);
-+		goto handle_xacterr_done;
-+	}
-+
-+	switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+	case UE_CONTROL:
-+	case UE_BULK:
-+		qtd->error_count++;
-+		if (!hc->qh->ping_state) {
-+
-+			update_urb_state_xfer_intr(hc, hc_regs,
-+						   qtd->urb, qtd,
-+						   DWC_OTG_HC_XFER_XACT_ERR);
-+			dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+			if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
-+				hc->qh->ping_state = 1;
-+			}
-+		}
-+
-+		/*
-+		 * Halt the channel so the transfer can be re-started from
-+		 * the appropriate point or the PING protocol will start.
-+		 */
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+		break;
-+	case UE_INTERRUPT:
-+		qtd->error_count++;
-+		if (hc->do_split && hc->complete_split) {
-+			qtd->complete_split = 0;
-+		}
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+		break;
-+	case UE_ISOCHRONOUS:
-+		{
-+			dwc_otg_halt_status_e halt_status;
-+			halt_status =
-+			    update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+						  DWC_OTG_HC_XFER_XACT_ERR);
-+
-+			halt_channel(hcd, hc, qtd, halt_status);
-+		}
-+		break;
-+	}
-+handle_xacterr_done:
-+	disable_hc_int(hc_regs, xacterr);
-+
-+	return 1;
-+}
-+
-+/**
-+ * Handles a host channel frame overrun interrupt. This handler may be called
-+ * in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
-+				       dwc_hc_t * hc,
-+				       dwc_otg_hc_regs_t * hc_regs,
-+				       dwc_otg_qtd_t * qtd)
-+{
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "Frame Overrun--\n", hc->hc_num);
-+
-+	switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
-+	case UE_CONTROL:
-+	case UE_BULK:
-+		break;
-+	case UE_INTERRUPT:
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
-+		break;
-+	case UE_ISOCHRONOUS:
-+		{
-+			dwc_otg_halt_status_e halt_status;
-+			halt_status =
-+			    update_isoc_urb_state(hcd, hc, hc_regs, qtd,
-+						  DWC_OTG_HC_XFER_FRAME_OVERRUN);
-+
-+			halt_channel(hcd, hc, qtd, halt_status);
-+		}
-+		break;
-+	}
-+
-+	disable_hc_int(hc_regs, frmovrun);
-+
-+	return 1;
-+}
-+
-+/**
-+ * Handles a host channel data toggle error interrupt. This handler may be
-+ * called in either DMA mode or Slave mode.
-+ */
-+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
-+					 dwc_hc_t * hc,
-+					 dwc_otg_hc_regs_t * hc_regs,
-+					 dwc_otg_qtd_t * qtd)
-+{
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		"Data Toggle Error on %s transfer--\n",
-+		hc->hc_num, (hc->ep_is_in ? "IN" : "OUT"));
-+
-+	/* Data toggles on split transactions cause the hc to halt.
-+	 * restart transfer */
-+	if(hc->qh->do_split)
-+	{
-+		qtd->error_count++;
-+		dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+		update_urb_state_xfer_intr(hc, hc_regs,
-+			qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+	} else if (hc->ep_is_in) {
-+		/* An unmasked data toggle error on a non-split DMA transaction is
-+		 * for the sole purpose of resetting error counts. Disable other
-+		 * interrupts unmasked for the same reason.
-+		 */
-+		if(hcd->core_if->dma_enable) {
-+			disable_hc_int(hc_regs, ack);
-+			disable_hc_int(hc_regs, nak);
-+		}
-+		qtd->error_count = 0;
-+	}
-+
-+	disable_hc_int(hc_regs, datatglerr);
-+
-+	return 1;
-+}
-+
-+#ifdef DEBUG
-+/**
-+ * This function is for debug only. It checks that a valid halt status is set
-+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
-+ * taken and a warning is issued.
-+ * @return 1 if halt status is ok, 0 otherwise.
-+ */
-+static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
-+				 dwc_hc_t * hc,
-+				 dwc_otg_hc_regs_t * hc_regs,
-+				 dwc_otg_qtd_t * qtd)
-+{
-+	hcchar_data_t hcchar;
-+	hctsiz_data_t hctsiz;
-+	hcint_data_t hcint;
-+	hcintmsk_data_t hcintmsk;
-+	hcsplt_data_t hcsplt;
-+
-+	if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
-+		/*
-+		 * This code is here only as a check. This condition should
-+		 * never happen. Ignore the halt if it does occur.
-+		 */
-+		hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+		hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
-+		hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+		hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+		hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
-+		DWC_WARN
-+		    ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
-+		     "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
-+		     "hcint 0x%08x, hcintmsk 0x%08x, "
-+		     "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
-+		     hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
-+		     hcintmsk.d32, hcsplt.d32, qtd->complete_split);
-+
-+		DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
-+			 __func__, hc->hc_num);
-+		DWC_WARN("\n");
-+		clear_hc_int(hc_regs, chhltd);
-+		return 0;
-+	}
-+
-+	/*
-+	 * This code is here only as a check. hcchar.chdis should
-+	 * never be set when the halt interrupt occurs. Halt the
-+	 * channel again if it does occur.
-+	 */
-+	hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
-+	if (hcchar.b.chdis) {
-+		DWC_WARN("%s: hcchar.chdis set unexpectedly, "
-+			 "hcchar 0x%08x, trying to halt again\n",
-+			 __func__, hcchar.d32);
-+		clear_hc_int(hc_regs, chhltd);
-+		hc->halt_pending = 0;
-+		halt_channel(hcd, hc, qtd, hc->halt_status);
-+		return 0;
-+	}
-+
-+	return 1;
-+}
-+#endif
-+
-+/**
-+ * Handles a host Channel Halted interrupt in DMA mode. This handler
-+ * determines the reason the channel halted and proceeds accordingly.
-+ */
-+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
-+				      dwc_hc_t * hc,
-+				      dwc_otg_hc_regs_t * hc_regs,
-+				      dwc_otg_qtd_t * qtd)
-+{
-+	int out_nak_enh = 0;
-+	hcint_data_t hcint;
-+	hcintmsk_data_t hcintmsk;
-+	/* For core with OUT NAK enhancement, the flow for high-
-+	 * speed CONTROL/BULK OUT is handled a little differently.
-+	 */
-+	if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
-+		if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
-+		    (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
-+		     hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
-+			out_nak_enh = 1;
-+		}
-+	}
-+
-+	if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
-+	    (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
-+	     && !hcd->core_if->dma_desc_enable)) {
-+		/*
-+		 * Just release the channel. A dequeue can happen on a
-+		 * transfer timeout. In the case of an AHB Error, the channel
-+		 * was forced to halt because there's no way to gracefully
-+		 * recover.
-+		 */
-+		if (hcd->core_if->dma_desc_enable)
-+			dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
-+						       hc->halt_status);
-+		else
-+			release_channel(hcd, hc, qtd, hc->halt_status);
-+		return;
-+	}
-+
-+	/* Read the HCINTn register to determine the cause for the halt. */
-+
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+	hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+
-+	if (hcint.b.xfercomp) {
-+		/** @todo This is here because of a possible hardware bug.  Spec
-+		 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
-+		 * interrupt w/ACK bit set should occur, but I only see the
-+		 * XFERCOMP bit, even with it masked out.  This is a workaround
-+		 * for that behavior.  Should fix this when hardware is fixed.
-+		 */
-+		if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
-+			handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
-+		}
-+		handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
-+	} else if (hcint.b.stall) {
-+		handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+	} else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
-+		if (out_nak_enh) {
-+			if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
-+				DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n");
-+				qtd->error_count = 0;
-+			} else {
-+				DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n");
-+			}
-+		}
-+
-+		/*
-+		 * Must handle xacterr before nak or ack. Could get a xacterr
-+		 * at the same time as either of these on a BULK/CONTROL OUT
-+		 * that started with a PING. The xacterr takes precedence.
-+		 */
-+		handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+	} else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
-+		handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+	} else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
-+		handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+	} else if (hcint.b.bblerr) {
-+		handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+	} else if (hcint.b.frmovrun) {
-+		handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
-+	} else if (hcint.b.datatglerr) {
-+		handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
-+	} else if (!out_nak_enh) {
-+		if (hcint.b.nyet) {
-+			/*
-+			 * Must handle nyet before nak or ack. Could get a nyet at the
-+			 * same time as either of those on a BULK/CONTROL OUT that
-+			 * started with a PING. The nyet takes precedence.
-+			 */
-+			handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.nak && !hcintmsk.b.nak) {
-+			/*
-+			 * If nak is not masked, it's because a non-split IN transfer
-+			 * is in an error state. In that case, the nak is handled by
-+			 * the nak interrupt handler, not here. Handle nak here for
-+			 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
-+			 * rewinding the buffer pointer.
-+			 */
-+			handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.ack && !hcintmsk.b.ack) {
-+			/*
-+			 * If ack is not masked, it's because a non-split IN transfer
-+			 * is in an error state. In that case, the ack is handled by
-+			 * the ack interrupt handler, not here. Handle ack here for
-+			 * split transfers. Start splits halt on ACK.
-+			 */
-+			handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
-+		} else {
-+			if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
-+			    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
-+				/*
-+				 * A periodic transfer halted with no other channel
-+				 * interrupts set. Assume it was halted by the core
-+				 * because it could not be completed in its scheduled
-+				 * (micro)frame.
-+				 */
-+#ifdef DEBUG
-+				DWC_PRINTF
-+				    ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
-+				     __func__, hc->hc_num);
-+#endif
-+				halt_channel(hcd, hc, qtd,
-+					     DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
-+			} else {
-+				DWC_ERROR
-+				    ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
-+				     "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
-+				     __func__, hc->hc_num, hcint.d32,
-+				     DWC_READ_REG32(&hcd->
-+						    core_if->core_global_regs->
-+						    gintsts));
-+				/* Failthrough: use 3-strikes rule */
-+				qtd->error_count++;
-+				dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+				update_urb_state_xfer_intr(hc, hc_regs,
-+					   qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+				halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+			}
-+
-+		}
-+	} else {
-+		DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
-+			   hcint.d32);
-+		/* Failthrough: use 3-strikes rule */
-+		qtd->error_count++;
-+		dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+		update_urb_state_xfer_intr(hc, hc_regs,
-+			   qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+		halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
-+	}
-+}
-+
-+/**
-+ * Handles a host channel Channel Halted interrupt.
-+ *
-+ * In slave mode, this handler is called only when the driver specifically
-+ * requests a halt. This occurs during handling other host channel interrupts
-+ * (e.g. nak, xacterr, stall, nyet, etc.).
-+ *
-+ * In DMA mode, this is the interrupt that occurs when the core has finished
-+ * processing a transfer on a channel. Other host channel interrupts (except
-+ * ahberr) are disabled in DMA mode.
-+ */
-+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
-+				     dwc_hc_t * hc,
-+				     dwc_otg_hc_regs_t * hc_regs,
-+				     dwc_otg_qtd_t * qtd)
-+{
-+	DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
-+		    "Channel Halted--\n", hc->hc_num);
-+
-+	if (hcd->core_if->dma_enable) {
-+		handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
-+	} else {
-+#ifdef DEBUG
-+		if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
-+			return 1;
-+		}
-+#endif
-+		release_channel(hcd, hc, qtd, hc->halt_status);
-+	}
-+
-+	return 1;
-+}
-+
-+
-+/**
-+ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on
-+ * FIQ transfer completion
-+ * @hcd:	Pointer to dwc_otg_hcd struct
-+ * @num:	Host channel number
-+ *
-+ * 1. Un-mangle the status as recorded in each iso_frame_desc status
-+ * 2. Copy it from the dwc_otg_urb into the real URB
-+ */
-+void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
-+{
-+	struct dwc_otg_hcd_urb *dwc_urb = qtd->urb;
-+	int nr_frames = dwc_urb->packet_count;
-+	int i;
-+	hcint_data_t frame_hcint;
-+
-+	for (i = 0; i < nr_frames; i++) {
-+		frame_hcint.d32 = dwc_urb->iso_descs[i].status;
-+		if (frame_hcint.b.xfercomp) {
-+			dwc_urb->iso_descs[i].status = 0;
-+			dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length;
-+		} else if (frame_hcint.b.frmovrun) {
-+			if (qh->ep_is_in)
-+				dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES;
-+			else
-+				dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION;
-+			dwc_urb->error_count++;
-+			dwc_urb->iso_descs[i].actual_length = 0;
-+		} else if (frame_hcint.b.xacterr) {
-+			dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL;
-+			dwc_urb->error_count++;
-+			dwc_urb->iso_descs[i].actual_length = 0;
-+		} else if (frame_hcint.b.bblerr) {
-+			dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW;
-+			dwc_urb->error_count++;
-+			dwc_urb->iso_descs[i].actual_length = 0;
-+		} else {
-+			/* Something went wrong */
-+			dwc_urb->iso_descs[i].status = -1;
-+			dwc_urb->iso_descs[i].actual_length = 0;
-+			dwc_urb->error_count++;
-+		}
-+	}
-+	qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval * (nr_frames - 1));
-+
-+	//printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n",
-+	//			__FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count);
-+}
-+
-+/**
-+ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions
-+ * @hcd:	Pointer to dwc_otg_hcd struct
-+ * @num:	Host channel number
-+ *
-+ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state.
-+ * Returns total length of data or -1 if the buffers were not used.
-+ *
-+ */
-+int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
-+{
-+	dwc_hc_t *hc = qh->channel;
-+	struct fiq_dma_blob *blob = hcd->fiq_dmab;
-+	struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+	uint8_t *ptr = NULL;
-+	int index = 0, len = 0;
-+	int i = 0;
-+	if (hc->ep_is_in) {
-+		/* Copy data out of the DMA bounce buffers to the URB's buffer.
-+		 * The align_buf is ignored as this is ignored on FSM enqueue. */
-+		ptr = qtd->urb->buf;
-+		if (qh->ep_type == UE_ISOCHRONOUS) {
-+			/* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */
-+			index = qtd->isoc_frame_index;
-+			ptr += qtd->urb->iso_descs[index].offset;
-+		} else {
-+			/* Need to increment by actual_length for interrupt IN */
-+			ptr += qtd->urb->actual_length;
-+		}
-+
-+		for (i = 0; i < st->dma_info.index; i++) {
-+			len += st->dma_info.slot_len[i];
-+			dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);
-+			ptr += st->dma_info.slot_len[i];
-+		}
-+		return len;
-+	} else {
-+		/* OUT endpoints - nothing to do. */
-+		return -1;
-+	}
-+
-+}
-+/**
-+ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt
-+ * 				 from a channel handled in the FIQ
-+ * @hcd:	Pointer to dwc_otg_hcd struct
-+ * @num:	Host channel number
-+ *
-+ * If a host channel interrupt was received by the IRQ and this was a channel
-+ * used by the FIQ, the execution flow for transfer completion is substantially
-+ * different from the normal (messy) path. This function and its friends handles
-+ * channel cleanup and transaction completion from a FIQ transaction.
-+ */
-+void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num)
-+{
-+	struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
-+	dwc_hc_t *hc = hcd->hc_ptr_array[num];
-+	dwc_otg_qtd_t *qtd;
-+	dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num];
-+	hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy;
-+	hctsiz_data_t hctsiz = hcd->fiq_state->channel[num].hctsiz_copy;
-+	int hostchannels  = 0;
-+	fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm);
-+
-+	hostchannels = hcd->available_host_channels;
-+	if (hc->halt_pending) {
-+		/* Dequeue: The FIQ was allowed to complete the transfer but state has been cleared. */
-+		if (hc->qh && st->fsm == FIQ_NP_SPLIT_DONE &&
-+				hcint.b.xfercomp && hc->qh->ep_type == UE_BULK) {
-+			if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
-+				hc->qh->data_toggle = DWC_OTG_HC_PID_DATA1;
-+			} else {
-+				hc->qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+			}
-+		}
-+		release_channel(hcd, hc, NULL, hc->halt_status);
-+		return;
-+	}
-+
-+	qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
-+	switch (st->fsm) {
-+	case FIQ_TEST:
-+		break;
-+
-+	case FIQ_DEQUEUE_ISSUED:
-+		/* Handled above, but keep for posterity */
-+		release_channel(hcd, hc, NULL, hc->halt_status);
-+		break;
-+
-+	case FIQ_NP_SPLIT_DONE:
-+		/* Nonperiodic transaction complete. */
-+		if (!hc->ep_is_in) {
-+			qtd->ssplit_out_xfer_count = hc->xfer_len;
-+		}
-+		if (hcint.b.xfercomp) {
-+			handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.nak) {
-+			handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+		} else {
-+			DWC_WARN("Unexpected IRQ state on FSM transaction:"
-+					"dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\n",
-+				hc->dev_addr, hc->ep_num, st->fsm, hcint.d32);
-+			release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+		}
-+		break;
-+
-+	case FIQ_NP_SPLIT_HS_ABORTED:
-+		/* A HS abort is a 3-strikes on the HS bus at any point in the transaction.
-+		 * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that
-+		 * because there's no guarantee which order a non-periodic split happened in.
-+		 * We could end up clearing a perfectly good transaction out of the buffer.
-+		 */
-+		if (hcint.b.xacterr) {
-+			qtd->error_count += st->nr_errors;
-+			handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.ahberr) {
-+			handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+		} else {
-+			DWC_WARN("Unexpected IRQ state on FSM transaction:"
-+					"dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\n",
-+				hc->dev_addr, hc->ep_num, st->fsm, hcint.d32);
-+			release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+		}
-+		break;
-+
-+	case FIQ_NP_SPLIT_LS_ABORTED:
-+		/* A few cases can cause this - either an unknown state on a SSPLIT or
-+		 * STALL/data toggle error response on a CSPLIT */
-+		if (hcint.b.stall) {
-+			handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.datatglerr) {
-+			handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.bblerr) {
-+			handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.ahberr) {
-+			handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
-+		} else {
-+			DWC_WARN("Unexpected IRQ state on FSM transaction:"
-+					"dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\n",
-+				hc->dev_addr, hc->ep_num, st->fsm, hcint.d32);
-+			release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+		}
-+		break;
-+
-+	case FIQ_PER_SPLIT_DONE:
-+		/* Isoc IN or Interrupt IN/OUT */
-+
-+		/* Flow control here is different from the normal execution by the driver.
-+		* We need to completely ignore most of the driver's method of handling
-+		* split transactions and do it ourselves.
-+		*/
-+		if (hc->ep_type == UE_INTERRUPT) {
-+			if (hcint.b.nak) {
-+					handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
-+			} else if (hc->ep_is_in) {
-+				int len;
-+				len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
-+				//printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length);
-+				qtd->urb->actual_length += len;
-+				if (qtd->urb->actual_length >= qtd->urb->length) {
-+					qtd->urb->status = 0;
-+					hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+					release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+				} else {
-+					/* Interrupt transfer not complete yet - is it a short read? */
-+					if (len < hc->max_packet) {
-+						/* Interrupt transaction complete */
-+						qtd->urb->status = 0;
-+						hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+						release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+					} else {
-+						/* Further transactions required */
-+						release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+					}
-+				}
-+			} else {
-+				/* Interrupt OUT complete. */
-+				dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
-+				qtd->urb->actual_length += hc->xfer_len;
-+				if (qtd->urb->actual_length >= qtd->urb->length) {
-+					qtd->urb->status = 0;
-+					hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
-+					release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+				} else {
-+					release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+				}
-+			}
-+		} else {
-+			/* ISOC IN complete. */
-+			struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+			int len = 0;
-+			/* Record errors, update qtd. */
-+			if (st->nr_errors) {
-+				frame_desc->actual_length = 0;
-+				frame_desc->status = -DWC_E_PROTOCOL;
-+			} else {
-+				frame_desc->status = 0;
-+				/* Unswizzle dma */
-+				len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
-+				frame_desc->actual_length = len;
-+			}
-+			qtd->isoc_frame_index++;
-+			if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+				hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+			} else {
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+			}
-+		}
-+		break;
-+
-+	case FIQ_PER_ISO_OUT_DONE: {
-+			struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+			/* Record errors, update qtd. */
-+			if (st->nr_errors) {
-+				frame_desc->actual_length = 0;
-+				frame_desc->status = -DWC_E_PROTOCOL;
-+			} else {
-+				frame_desc->status = 0;
-+				frame_desc->actual_length = frame_desc->length;
-+			}
-+			qtd->isoc_frame_index++;
-+			qtd->isoc_split_offset = 0;
-+			if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+				hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+			} else {
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+			}
-+		}
-+		break;
-+
-+	case FIQ_PER_SPLIT_NYET_ABORTED:
-+		/* Doh. lost the data. */
-+		printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
-+				"- FIQ reported NYET. Data may have been lost.\n",
-+				hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
-+		if (hc->ep_type == UE_ISOCHRONOUS) {
-+			struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+			/* Record errors, update qtd. */
-+			frame_desc->actual_length = 0;
-+			frame_desc->status = -DWC_E_PROTOCOL;
-+			qtd->isoc_frame_index++;
-+			qtd->isoc_split_offset = 0;
-+			if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+				hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+			} else {
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+			}
-+		} else {
-+			release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+		}
-+		break;
-+
-+	case FIQ_HS_ISOC_DONE:
-+		/* The FIQ has performed a whole pile of isochronous transactions.
-+		 * The status is recorded as the interrupt state should the transaction
-+		 * fail.
-+		 */
-+		dwc_otg_fiq_unmangle_isoc(hcd, hc->qh, qtd, num);
-+		hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+		release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+		break;
-+
-+	case FIQ_PER_SPLIT_LS_ABORTED:
-+		if (hcint.b.xacterr) {
-+			/* Hub has responded with an ERR packet. Device
-+			 * has been unplugged or the port has been disabled.
-+			 * TODO: need to issue a reset to the hub port. */
-+			qtd->error_count += 3;
-+			handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.stall) {
-+			handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
-+		} else if (hcint.b.bblerr) {
-+			handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
-+		} else {
-+			printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed "
-+				"- FIQ reported FSM=%d. Data may have been lost.\n",
-+				st->fsm, hc->dev_addr, hc->ep_num);
-+			release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+		}
-+		break;
-+
-+	case FIQ_PER_SPLIT_HS_ABORTED:
-+		/* Either the SSPLIT phase suffered transaction errors or something
-+		 * unexpected happened.
-+		 */
-+		qtd->error_count += 3;
-+		handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
-+		release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+		break;
-+
-+	case FIQ_PER_SPLIT_TIMEOUT:
-+		/* Couldn't complete in the nominated frame */
-+		printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
-+				"- FIQ timed out. Data may have been lost.\n",
-+				hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
-+		if (hc->ep_type == UE_ISOCHRONOUS) {
-+			struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
-+			/* Record errors, update qtd. */
-+			frame_desc->actual_length = 0;
-+			if (hc->ep_is_in) {
-+				frame_desc->status = -DWC_E_NO_STREAM_RES;
-+			} else {
-+				frame_desc->status = -DWC_E_COMMUNICATION;
-+			}
-+			qtd->isoc_frame_index++;
-+			if (qtd->isoc_frame_index == qtd->urb->packet_count) {
-+				hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
-+			} else {
-+				release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
-+			}
-+		} else {
-+			release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+		}
-+		break;
-+
-+	default:
-+		DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x", 
-+					hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num);
-+		qtd->error_count++;
-+		release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
-+	}
-+	return;
-+}
-+
-+/** Handles interrupt for a specific Host Channel */
-+int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
-+{
-+	int retval = 0;
-+	hcint_data_t hcint;
-+	hcintmsk_data_t hcintmsk;
-+	dwc_hc_t *hc;
-+	dwc_otg_hc_regs_t *hc_regs;
-+	dwc_otg_qtd_t *qtd;
-+
-+	DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
-+
-+	hc = dwc_otg_hcd->hc_ptr_array[num];
-+	hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
-+	if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
-+		/* A dequeue was issued for this transfer. Our QTD has gone away
-+		 * but in the case of a FIQ transfer, the transfer would have run
-+		 * to completion.
-+		 */
-+		if (fiq_fsm_enable && dwc_otg_hcd->fiq_state->channel[num].fsm != FIQ_PASSTHROUGH) {
-+			dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
-+		} else {
-+			release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);
-+		}
-+		return 1;
-+	}
-+	qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
-+
-+	/*
-+	 * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ.
-+	 * Execution path is fundamentally different for the channels after a FIQ has completed
-+	 * a split transaction.
-+	 */
-+	if (fiq_fsm_enable) {
-+		switch (dwc_otg_hcd->fiq_state->channel[num].fsm) {
-+			case FIQ_PASSTHROUGH:
-+				break;
-+			case FIQ_PASSTHROUGH_ERRORSTATE:
-+				/* Hook into the error count */
-+				fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num);
-+				if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
-+					qtd->error_count = 0;
-+					fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET   ");
-+				}
-+				break;
-+			default:
-+				dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
-+				return 1;
-+		}
-+	}
-+
-+	hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
-+	hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
-+	hcint.d32 = hcint.d32 & hcintmsk.d32;
-+	if (!dwc_otg_hcd->core_if->dma_enable) {
-+		if (hcint.b.chhltd && hcint.d32 != 0x2) {
-+			hcint.b.chhltd = 0;
-+		}
-+	}
-+
-+	if (hcint.b.xfercomp) {
-+		retval |=
-+		    handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+		/*
-+		 * If NYET occurred at same time as Xfer Complete, the NYET is
-+		 * handled by the Xfer Complete interrupt handler. Don't want
-+		 * to call the NYET interrupt handler in this case.
-+		 */
-+		hcint.b.nyet = 0;
-+	}
-+	if (hcint.b.chhltd) {
-+		retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.ahberr) {
-+		retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.stall) {
-+		retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.nak) {
-+		retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.ack) {
-+		if(!hcint.b.chhltd)
-+			retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.nyet) {
-+		retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.xacterr) {
-+		retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.bblerr) {
-+		retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.frmovrun) {
-+		retval |=
-+		    handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+	if (hcint.b.datatglerr) {
-+		retval |=
-+		    handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
-+	}
-+
-+	return retval;
-+}
-+#endif /* DWC_DEVICE_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
-@@ -0,0 +1,1007 @@
-+
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
-+ * $Revision: #20 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1872981 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the implementation of the HCD. In Linux, the HCD
-+ * implements the hc_driver API.
-+ */
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/string.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/version.h>
-+#include <asm/io.h>
-+#include <asm/fiq.h>
-+#include <linux/usb.h>
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
-+#include <../drivers/usb/core/hcd.h>
-+#else
-+#include <linux/usb/hcd.h>
-+#endif
-+#include <asm/bug.h>
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
-+#define USB_URB_EP_LINKING 1
-+#else
-+#define USB_URB_EP_LINKING 0
-+#endif
-+
-+#include "dwc_otg_hcd_if.h"
-+#include "dwc_otg_dbg.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_hcd.h"
-+
-+extern unsigned char  _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;
-+
-+/**
-+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
-+ * qualified with its direction (possible 32 endpoints per device).
-+ */
-+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
-+						     ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
-+
-+static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
-+
-+extern bool fiq_enable;
-+
-+/** @name Linux HC Driver API Functions */
-+/** @{ */
-+/* manage i/o requests, device state */
-+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+		       struct usb_host_endpoint *ep,
-+#endif
-+		       struct urb *urb, gfp_t mem_flags);
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
-+#endif
-+#else /* kernels at or post 2.6.30 */
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,
-+                               struct urb *urb, int status);
-+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */
-+
-+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
-+#endif
-+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
-+extern int hcd_start(struct usb_hcd *hcd);
-+extern void hcd_stop(struct usb_hcd *hcd);
-+static int get_frame_number(struct usb_hcd *hcd);
-+extern int hub_status_data(struct usb_hcd *hcd, char *buf);
-+extern int hub_control(struct usb_hcd *hcd,
-+		       u16 typeReq,
-+		       u16 wValue, u16 wIndex, char *buf, u16 wLength);
-+
-+struct wrapper_priv_data {
-+	dwc_otg_hcd_t *dwc_otg_hcd;
-+};
-+
-+/** @} */
-+
-+static struct hc_driver dwc_otg_hc_driver = {
-+
-+	.description = dwc_otg_hcd_name,
-+	.product_desc = "DWC OTG Controller",
-+	.hcd_priv_size = sizeof(struct wrapper_priv_data),
-+
-+	.irq = dwc_otg_hcd_irq,
-+
-+	.flags = HCD_MEMORY | HCD_USB2,
-+
-+	//.reset =
-+	.start = hcd_start,
-+	//.suspend =
-+	//.resume =
-+	.stop = hcd_stop,
-+
-+	.urb_enqueue = dwc_otg_urb_enqueue,
-+	.urb_dequeue = dwc_otg_urb_dequeue,
-+	.endpoint_disable = endpoint_disable,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+	.endpoint_reset = endpoint_reset,
-+#endif
-+	.get_frame_number = get_frame_number,
-+
-+	.hub_status_data = hub_status_data,
-+	.hub_control = hub_control,
-+	//.bus_suspend =
-+	//.bus_resume =
-+};
-+
-+/** Gets the dwc_otg_hcd from a struct usb_hcd */
-+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
-+{
-+	struct wrapper_priv_data *p;
-+	p = (struct wrapper_priv_data *)(hcd->hcd_priv);
-+	return p->dwc_otg_hcd;
-+}
-+
-+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
-+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
-+{
-+	return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
-+}
-+
-+/** Gets the usb_host_endpoint associated with an URB. */
-+inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
-+{
-+	struct usb_device *dev = urb->dev;
-+	int ep_num = usb_pipeendpoint(urb->pipe);
-+
-+	if (usb_pipein(urb->pipe))
-+		return dev->ep_in[ep_num];
-+	else
-+		return dev->ep_out[ep_num];
-+}
-+
-+static int _disconnect(dwc_otg_hcd_t * hcd)
-+{
-+	struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+
-+	usb_hcd->self.is_b_host = 0;
-+	return 0;
-+}
-+
-+static int _start(dwc_otg_hcd_t * hcd)
-+{
-+	struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+
-+	usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
-+	hcd_start(usb_hcd);
-+
-+	return 0;
-+}
-+
-+static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
-+		     uint32_t * port_addr)
-+{
-+   struct urb *urb = (struct urb *)urb_handle;
-+   struct usb_bus *bus;
-+#if 1 //GRAYG - temporary
-+   if (NULL == urb_handle)
-+      DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
-+   if (NULL == urb->dev)
-+      DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
-+   if (NULL == port_addr)
-+      DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
-+#endif
-+   if (urb->dev->tt) {
-+        if (NULL == urb->dev->tt->hub) {
-+                DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
-+                           __func__); //GRAYG
-+                //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
-+                *hub_addr = 0; //GRAYG
-+                // we probably shouldn't have a transaction translator if
-+                // there's no associated hub?
-+        } else {
-+		bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
-+		if (urb->dev->tt->hub == bus->root_hub)
-+			*hub_addr = 0;
-+		else
-+			*hub_addr = urb->dev->tt->hub->devnum;
-+	}
-+	*port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1;
-+   } else {
-+        *hub_addr = 0;
-+	*port_addr = urb->dev->ttport;
-+   }
-+   return 0;
-+}
-+
-+static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
-+{
-+	struct urb *urb = (struct urb *)urb_handle;
-+	return urb->dev->speed;
-+}
-+
-+static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
-+{
-+	struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
-+	return usb_hcd->self.b_hnp_enable;
-+}
-+
-+static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
-+				   struct urb *urb)
-+{
-+	hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
-+	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+		hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
-+	} else {
-+		hcd_to_bus(hcd)->bandwidth_int_reqs++;
-+	}
-+}
-+
-+static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
-+			       struct urb *urb)
-+{
-+	hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
-+	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+		hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
-+	} else {
-+		hcd_to_bus(hcd)->bandwidth_int_reqs--;
-+	}
-+}
-+
-+/**
-+ * Sets the final status of an URB and returns it to the device driver. Any
-+ * required cleanup of the URB is performed.  The HCD lock should be held on
-+ * entry.
-+ */
-+static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
-+		     dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
-+{
-+	struct urb *urb = (struct urb *)urb_handle;
-+	urb_tq_entry_t *new_entry;
-+	int rc = 0;
-+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+		DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
-+			   __func__, urb, usb_pipedevice(urb->pipe),
-+			   usb_pipeendpoint(urb->pipe),
-+			   usb_pipein(urb->pipe) ? "IN" : "OUT", status);
-+		if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+			int i;
-+			for (i = 0; i < urb->number_of_packets; i++) {
-+				DWC_PRINTF("  ISO Desc %d status: %d\n",
-+					   i, urb->iso_frame_desc[i].status);
-+			}
-+		}
-+	}
-+	new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t));
-+	urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
-+	/* Convert status value. */
-+	switch (status) {
-+	case -DWC_E_PROTOCOL:
-+		status = -EPROTO;
-+		break;
-+	case -DWC_E_IN_PROGRESS:
-+		status = -EINPROGRESS;
-+		break;
-+	case -DWC_E_PIPE:
-+		status = -EPIPE;
-+		break;
-+	case -DWC_E_IO:
-+		status = -EIO;
-+		break;
-+	case -DWC_E_TIMEOUT:
-+		status = -ETIMEDOUT;
-+		break;
-+	case -DWC_E_OVERFLOW:
-+		status = -EOVERFLOW;
-+		break;
-+	case -DWC_E_SHUTDOWN:
-+		status = -ESHUTDOWN;
-+		break;
-+	default:
-+		if (status) {
-+			DWC_PRINTF("Uknown urb status %d\n", status);
-+
-+		}
-+	}
-+
-+	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+		int i;
-+
-+		urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
-+		urb->actual_length = 0;
-+		for (i = 0; i < urb->number_of_packets; ++i) {
-+			urb->iso_frame_desc[i].actual_length =
-+			    dwc_otg_hcd_urb_get_iso_desc_actual_length
-+			    (dwc_otg_urb, i);
-+			urb->actual_length += urb->iso_frame_desc[i].actual_length;
-+			urb->iso_frame_desc[i].status =
-+			    dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
-+		}
-+	}
-+
-+	urb->status = status;
-+	urb->hcpriv = NULL;
-+	if (!status) {
-+		if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
-+		    (urb->actual_length < urb->transfer_buffer_length)) {
-+			urb->status = -EREMOTEIO;
-+		}
-+	}
-+
-+	if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
-+	    (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
-+		struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
-+		if (ep) {
-+			free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
-+					   dwc_otg_hcd_get_ep_bandwidth(hcd,
-+									ep->hcpriv),
-+					   urb);
-+		}
-+	}
-+	DWC_FREE(dwc_otg_urb);
-+	if (!new_entry) {
-+		DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n");
-+		urb->status = -EPROTO;
-+		/* don't schedule the tasklet -
-+		 * directly return the packet here with error. */
-+#if USB_URB_EP_LINKING
-+		usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
-+#endif
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+		usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
-+#else
-+		usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
-+#endif
-+	} else {
-+		new_entry->urb = urb;
-+#if USB_URB_EP_LINKING
-+		rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
-+		if(0 == rc) {
-+			usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
-+		}
-+#endif
-+		if(0 == rc) {
-+			DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry,
-+						urb_tq_entries);
-+			DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet);
-+		}
-+	}
-+	return 0;
-+}
-+
-+static struct dwc_otg_hcd_function_ops hcd_fops = {
-+	.start = _start,
-+	.disconnect = _disconnect,
-+	.hub_info = _hub_info,
-+	.speed = _speed,
-+	.complete = _complete,
-+	.get_b_hnp_enable = _get_b_hnp_enable,
-+};
-+
-+static struct fiq_handler fh = {
-+  .name = "usb_fiq",
-+};
-+
-+static void hcd_init_fiq(void *cookie)
-+{
-+	dwc_otg_device_t *otg_dev = cookie;
-+	dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
-+	struct pt_regs regs;
-+	int irq;
-+
-+	if (claim_fiq(&fh)) {
-+		DWC_ERROR("Can't claim FIQ");
-+		BUG();
-+	}
-+	DWC_WARN("FIQ on core %d at 0x%08x",
-+				smp_processor_id(),
-+				(fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
-+	DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
-+		set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
-+	memset(&regs,0,sizeof(regs));
-+
-+	regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
-+	if (fiq_fsm_enable) {
-+		regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
-+		//regs.ARM_r10 = dwc_otg_hcd->dma;
-+		regs.ARM_fp = (long) dwc_otg_fiq_fsm;
-+	} else {
-+		regs.ARM_fp = (long) dwc_otg_fiq_nop;
-+	}
-+
-+	regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
-+
-+//		__show_regs(&regs);
-+	set_fiq_regs(&regs);
-+
-+	//Set the mphi periph to  the required registers
-+	dwc_otg_hcd->fiq_state->mphi_regs.base    = otg_dev->os_dep.mphi_base;
-+	dwc_otg_hcd->fiq_state->mphi_regs.ctrl    = otg_dev->os_dep.mphi_base + 0x4c;
-+	dwc_otg_hcd->fiq_state->mphi_regs.outdda  = otg_dev->os_dep.mphi_base + 0x28;
-+	dwc_otg_hcd->fiq_state->mphi_regs.outddb  = otg_dev->os_dep.mphi_base + 0x2c;
-+	dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
-+	dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
-+	DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
-+	//Enable mphi peripheral
-+	writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
-+#ifdef DEBUG
-+	if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
-+		DWC_WARN("MPHI periph has been enabled");
-+	else
-+		DWC_WARN("MPHI periph has NOT been enabled");
-+#endif
-+	// Enable FIQ interrupt from USB peripheral
-+#ifdef CONFIG_MULTI_IRQ_HANDLER
-+	irq = platform_get_irq(otg_dev->os_dep.platformdev, 1);
-+#else
-+	irq = INTERRUPT_VC_USB;
-+#endif
-+	if (irq < 0) {
-+		DWC_ERROR("Can't get FIQ irq");
-+		return;
-+	}
-+	enable_fiq(irq);
-+	local_fiq_enable();
-+}
-+
-+/**
-+ * Initializes the HCD. This function allocates memory for and initializes the
-+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
-+ * USB bus with the core and calls the hc_driver->start() function. It returns
-+ * a negative error on failure.
-+ */
-+int hcd_init(dwc_bus_dev_t *_dev)
-+{
-+	struct usb_hcd *hcd = NULL;
-+	dwc_otg_hcd_t *dwc_otg_hcd = NULL;
-+	dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+	int retval = 0;
-+        u64 dmamask;
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
-+
-+	/* Set device flags indicating whether the HCD supports DMA. */
-+	if (dwc_otg_is_dma_enable(otg_dev->core_if))
-+                dmamask = DMA_BIT_MASK(32);
-+        else
-+                dmamask = 0;
-+
-+#if    defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
-+        dma_set_mask(&_dev->dev, dmamask);
-+        dma_set_coherent_mask(&_dev->dev, dmamask);
-+#elif  defined(PCI_INTERFACE)
-+        pci_set_dma_mask(_dev, dmamask);
-+        pci_set_consistent_dma_mask(_dev, dmamask);
-+#endif
-+
-+	/*
-+	 * Allocate memory for the base HCD plus the DWC OTG HCD.
-+	 * Initialize the base HCD.
-+	 */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+	hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
-+#else
-+	hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
-+	hcd->has_tt = 1;
-+//      hcd->uses_new_polling = 1;
-+//      hcd->poll_rh = 0;
-+#endif
-+	if (!hcd) {
-+		retval = -ENOMEM;
-+		goto error1;
-+	}
-+
-+	hcd->regs = otg_dev->os_dep.base;
-+
-+
-+	/* Initialize the DWC OTG HCD. */
-+	dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
-+	if (!dwc_otg_hcd) {
-+		goto error2;
-+	}
-+	((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
-+	    dwc_otg_hcd;
-+	otg_dev->hcd = dwc_otg_hcd;
-+	otg_dev->hcd->otg_dev = otg_dev;
-+
-+	if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
-+		goto error2;
-+	}
-+
-+	if (fiq_enable) {
-+		if (num_online_cpus() > 1) {
-+			/* bcm2709: can run the FIQ on a separate core to IRQs */
-+			smp_call_function_single(1, hcd_init_fiq, otg_dev, 1);
-+		} else {
-+			smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
-+		}
-+	}
-+
-+	hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later
-+	hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
-+#endif
-+	/* Don't support SG list at this point */
-+	hcd->self.sg_tablesize = 0;
-+#endif
-+	/*
-+	 * Finish generic HCD initialization and start the HCD. This function
-+	 * allocates the DMA buffer pool, registers the USB bus, requests the
-+	 * IRQ line, and calls hcd_start method.
-+	 */
-+#ifdef PLATFORM_INTERFACE
-+	retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED);
-+#else
-+	retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED);
-+#endif
-+	if (retval < 0) {
-+		goto error2;
-+	}
-+
-+	dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
-+	return 0;
-+
-+error2:
-+	usb_put_hcd(hcd);
-+error1:
-+	return retval;
-+}
-+
-+/**
-+ * Removes the HCD.
-+ * Frees memory and resources associated with the HCD and deregisters the bus.
-+ */
-+void hcd_remove(dwc_bus_dev_t *_dev)
-+{
-+	dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+	dwc_otg_hcd_t *dwc_otg_hcd;
-+	struct usb_hcd *hcd;
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
-+
-+	if (!otg_dev) {
-+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
-+		return;
-+	}
-+
-+	dwc_otg_hcd = otg_dev->hcd;
-+
-+	if (!dwc_otg_hcd) {
-+		DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
-+		return;
-+	}
-+
-+	hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
-+
-+	if (!hcd) {
-+		DWC_DEBUGPL(DBG_ANY,
-+			    "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
-+			    __func__);
-+		return;
-+	}
-+	usb_remove_hcd(hcd);
-+	dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
-+	dwc_otg_hcd_remove(dwc_otg_hcd);
-+	usb_put_hcd(hcd);
-+}
-+
-+/* =========================================================================
-+ *  Linux HC Driver Functions
-+ * ========================================================================= */
-+
-+/** Initializes the DWC_otg controller and its root hub and prepares it for host
-+ * mode operation. Activates the root port. Returns 0 on success and a negative
-+ * error code on failure. */
-+int hcd_start(struct usb_hcd *hcd)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+	struct usb_bus *bus;
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
-+	bus = hcd_to_bus(hcd);
-+
-+	hcd->state = HC_STATE_RUNNING;
-+	if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
-+		return 0;
-+	}
-+
-+	/* Initialize and connect root hub if one is not already attached */
-+	if (bus->root_hub) {
-+		DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
-+		/* Inform the HUB driver to resume. */
-+		usb_hcd_resume_root_hub(hcd);
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
-+ * stopped.
-+ */
-+void hcd_stop(struct usb_hcd *hcd)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+	dwc_otg_hcd_stop(dwc_otg_hcd);
-+}
-+
-+/** Returns the current frame number. */
-+static int get_frame_number(struct usb_hcd *hcd)
-+{
-+	hprt0_data_t hprt0;
-+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+	hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
-+	if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
-+		return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3;
-+	else
-+		return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
-+}
-+
-+#ifdef DEBUG
-+static void dump_urb_info(struct urb *urb, char *fn_name)
-+{
-+	DWC_PRINTF("%s, urb %p\n", fn_name, urb);
-+	DWC_PRINTF("  Device address: %d\n", usb_pipedevice(urb->pipe));
-+	DWC_PRINTF("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
-+		   (usb_pipein(urb->pipe) ? "IN" : "OUT"));
-+	DWC_PRINTF("  Endpoint type: %s\n", ( {
-+					     char *pipetype;
-+					     switch (usb_pipetype(urb->pipe)) {
-+case PIPE_CONTROL:
-+pipetype = "CONTROL"; break; case PIPE_BULK:
-+pipetype = "BULK"; break; case PIPE_INTERRUPT:
-+pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
-+pipetype = "ISOCHRONOUS"; break; default:
-+					     pipetype = "UNKNOWN"; break;};
-+					     pipetype;}
-+		   )) ;
-+	DWC_PRINTF("  Speed: %s\n", ( {
-+				     char *speed; switch (urb->dev->speed) {
-+case USB_SPEED_HIGH:
-+speed = "HIGH"; break; case USB_SPEED_FULL:
-+speed = "FULL"; break; case USB_SPEED_LOW:
-+speed = "LOW"; break; default:
-+				     speed = "UNKNOWN"; break;};
-+				     speed;}
-+		   )) ;
-+	DWC_PRINTF("  Max packet size: %d\n",
-+		   usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
-+	DWC_PRINTF("  Data buffer length: %d\n", urb->transfer_buffer_length);
-+	DWC_PRINTF("  Transfer buffer: %p, Transfer DMA: %p\n",
-+		   urb->transfer_buffer, (void *)urb->transfer_dma);
-+	DWC_PRINTF("  Setup buffer: %p, Setup DMA: %p\n",
-+		   urb->setup_packet, (void *)urb->setup_dma);
-+	DWC_PRINTF("  Interval: %d\n", urb->interval);
-+	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
-+		int i;
-+		for (i = 0; i < urb->number_of_packets; i++) {
-+			DWC_PRINTF("  ISO Desc %d:\n", i);
-+			DWC_PRINTF("    offset: %d, length %d\n",
-+				   urb->iso_frame_desc[i].offset,
-+				   urb->iso_frame_desc[i].length);
-+		}
-+	}
-+}
-+#endif
-+
-+/** Starts processing a USB transfer request specified by a USB Request Block
-+ * (URB). mem_flags indicates the type of memory allocation to use while
-+ * processing this URB. */
-+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+		       struct usb_host_endpoint *ep,
-+#endif
-+		       struct urb *urb, gfp_t mem_flags)
-+{
-+	int retval = 0;
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
-+	struct usb_host_endpoint *ep = urb->ep;
-+#endif
-+	dwc_irqflags_t irqflags;
-+        void **ref_ep_hcpriv = &ep->hcpriv;
-+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+	dwc_otg_hcd_urb_t *dwc_otg_urb;
-+	int i;
-+	int alloc_bandwidth = 0;
-+	uint8_t ep_type = 0;
-+	uint32_t flags = 0;
-+	void *buf;
-+
-+#ifdef DEBUG
-+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+		dump_urb_info(urb, "dwc_otg_urb_enqueue");
-+	}
-+#endif
-+
-+	if (!urb->transfer_buffer && urb->transfer_buffer_length)
-+		return -EINVAL;
-+
-+	if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
-+	    || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
-+		if (!dwc_otg_hcd_is_bandwidth_allocated
-+		    (dwc_otg_hcd, ref_ep_hcpriv)) {
-+			alloc_bandwidth = 1;
-+		}
-+	}
-+
-+	switch (usb_pipetype(urb->pipe)) {
-+	case PIPE_CONTROL:
-+		ep_type = USB_ENDPOINT_XFER_CONTROL;
-+		break;
-+	case PIPE_ISOCHRONOUS:
-+		ep_type = USB_ENDPOINT_XFER_ISOC;
-+		break;
-+	case PIPE_BULK:
-+		ep_type = USB_ENDPOINT_XFER_BULK;
-+		break;
-+	case PIPE_INTERRUPT:
-+		ep_type = USB_ENDPOINT_XFER_INT;
-+		break;
-+	default:
-+                DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe));
-+	}
-+
-+        /* # of packets is often 0 - do we really need to call this then? */
-+	dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
-+					    urb->number_of_packets,
-+					    mem_flags == GFP_ATOMIC ? 1 : 0);
-+
-+	if(dwc_otg_urb == NULL)
-+		return -ENOMEM;
-+
-+	if (!dwc_otg_urb && urb->number_of_packets)
-+		return -ENOMEM;
-+
-+	dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
-+				     usb_pipeendpoint(urb->pipe), ep_type,
-+				     usb_pipein(urb->pipe),
-+				     usb_maxpacket(urb->dev, urb->pipe,
-+						   !(usb_pipein(urb->pipe))));
-+
-+	buf = urb->transfer_buffer;
-+	if (hcd->self.uses_dma && !buf && urb->transfer_buffer_length) {
-+		/*
-+		 * Calculate virtual address from physical address,
-+		 * because some class driver may not fill transfer_buffer.
-+		 * In Buffer DMA mode virual address is used,
-+		 * when handling non DWORD aligned buffers.
-+		 */
-+		buf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma);
-+		dev_warn_once(&urb->dev->dev,
-+			      "USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\n",
-+			      &urb->transfer_dma, buf);
-+	}
-+
-+	if (!(urb->transfer_flags & URB_NO_INTERRUPT))
-+		flags |= URB_GIVEBACK_ASAP;
-+	if (urb->transfer_flags & URB_ZERO_PACKET)
-+		flags |= URB_SEND_ZERO_PACKET;
-+
-+	dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
-+				   urb->transfer_dma,
-+				   urb->transfer_buffer_length,
-+				   urb->setup_packet,
-+				   urb->setup_dma, flags, urb->interval);
-+
-+	for (i = 0; i < urb->number_of_packets; ++i) {
-+		dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
-+						    urb->
-+						    iso_frame_desc[i].offset,
-+						    urb->
-+						    iso_frame_desc[i].length);
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
-+	urb->hcpriv = dwc_otg_urb;
-+#if USB_URB_EP_LINKING
-+	retval = usb_hcd_link_urb_to_ep(hcd, urb);
-+	if (0 == retval)
-+#endif
-+	{
-+		retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
-+						/*(dwc_otg_qh_t **)*/
-+						ref_ep_hcpriv, 1);
-+		if (0 == retval) {
-+			if (alloc_bandwidth) {
-+				allocate_bus_bandwidth(hcd,
-+						dwc_otg_hcd_get_ep_bandwidth(
-+							dwc_otg_hcd, *ref_ep_hcpriv),
-+						urb);
-+			}
-+		} else {
-+			DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval);
-+#if USB_URB_EP_LINKING
-+			usb_hcd_unlink_urb_from_ep(hcd, urb);
-+#endif
-+			DWC_FREE(dwc_otg_urb);
-+			urb->hcpriv = NULL;
-+			if (retval == -DWC_E_NO_DEVICE)
-+				retval = -ENODEV;
-+		}
-+	}
-+#if USB_URB_EP_LINKING
-+	else
-+	{
-+		DWC_FREE(dwc_otg_urb);
-+		urb->hcpriv = NULL;
-+	}
-+#endif
-+	DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
-+	return retval;
-+}
-+
-+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
-+ * success.  */
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
-+#else
-+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
-+#endif
-+{
-+	dwc_irqflags_t flags;
-+	dwc_otg_hcd_t *dwc_otg_hcd;
-+        int rc;
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
-+
-+	dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+#ifdef DEBUG
-+	if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+		dump_urb_info(urb, "dwc_otg_urb_dequeue");
-+	}
-+#endif
-+
-+	DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+	rc = usb_hcd_check_unlink_urb(hcd, urb, status);
-+	if (0 == rc) {
-+		if(urb->hcpriv != NULL) {
-+	                dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,
-+	                                    (dwc_otg_hcd_urb_t *)urb->hcpriv);
-+
-+		        DWC_FREE(urb->hcpriv);
-+			urb->hcpriv = NULL;
-+		}
-+        }
-+
-+        if (0 == rc) {
-+		/* Higher layer software sets URB status. */
-+#if USB_URB_EP_LINKING
-+                usb_hcd_unlink_urb_from_ep(hcd, urb);
-+#endif
-+		DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+                usb_hcd_giveback_urb(hcd, urb);
-+#else
-+                usb_hcd_giveback_urb(hcd, urb, status);
-+#endif
-+                if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
-+                        DWC_PRINTF("Called usb_hcd_giveback_urb() \n");
-+                        DWC_PRINTF("  1urb->status = %d\n", urb->status);
-+                }
-+                DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n");
-+        } else {
-+		DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+                DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n",
-+                            rc);
-+        }
-+
-+	return rc;
-+}
-+
-+/* Frees resources in the DWC_otg controller related to a given endpoint. Also
-+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint
-+ * must already be dequeued. */
-+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+	DWC_DEBUGPL(DBG_HCD,
-+		    "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
-+		    "endpoint=%d\n", ep->desc.bEndpointAddress,
-+		    dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
-+	dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
-+	ep->hcpriv = NULL;
-+}
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
-+/* Resets endpoint specific parameter values, in current version used to reset
-+ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
-+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
-+{
-+	dwc_irqflags_t flags;
-+	struct usb_device *udev = NULL;
-+	int epnum = usb_endpoint_num(&ep->desc);
-+	int is_out = usb_endpoint_dir_out(&ep->desc);
-+	int is_control = usb_endpoint_xfer_control(&ep->desc);
-+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+        struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep);
-+
-+	if (dev)
-+		udev = to_usb_device(dev);
-+	else
-+		return;
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
-+
-+	DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
-+	usb_settoggle(udev, epnum, is_out, 0);
-+	if (is_control)
-+		usb_settoggle(udev, epnum, !is_out, 0);
-+
-+	if (ep->hcpriv) {
-+		dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
-+	}
-+	DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
-+}
-+#endif
-+
-+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
-+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
-+ * interrupt.
-+ *
-+ * This function is called by the USB core when an interrupt occurs */
-+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+	int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
-+	if (retval != 0) {
-+		S3C2410X_CLEAR_EINTPEND();
-+	}
-+	return IRQ_RETVAL(retval);
-+}
-+
-+/** Creates Status Change bitmap for the root hub and root port. The bitmap is
-+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
-+ * is the status change indicator for the single root port. Returns 1 if either
-+ * change indicator is 1, otherwise returns 0. */
-+int hub_status_data(struct usb_hcd *hcd, char *buf)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
-+
-+	buf[0] = 0;
-+	buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
-+
-+	return (buf[0] != 0);
-+}
-+
-+/** Handles hub class-specific requests. */
-+int hub_control(struct usb_hcd *hcd,
-+		u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
-+{
-+	int retval;
-+
-+	retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
-+					 typeReq, wValue, wIndex, buf, wLength);
-+
-+	switch (retval) {
-+	case -DWC_E_INVALID:
-+		retval = -EINVAL;
-+		break;
-+	}
-+
-+	return retval;
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
-@@ -0,0 +1,971 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
-+ * $Revision: #44 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_DEVICE_ONLY
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the functions to manage Queue Heads and Queue
-+ * Transfer Descriptors.
-+ */
-+
-+#include "dwc_otg_hcd.h"
-+#include "dwc_otg_regs.h"
-+
-+extern bool microframe_schedule;
-+extern unsigned short int_ep_interval_min;
-+
-+/**
-+ * Free each QTD in the QH's QTD-list then free the QH.  QH should already be
-+ * removed from a list.  QTD list should already be empty if called from URB
-+ * Dequeue.
-+ *
-+ * @param hcd HCD instance.
-+ * @param qh The QH to free.
-+ */
-+void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	dwc_otg_qtd_t *qtd, *qtd_tmp;
-+	dwc_irqflags_t flags;
-+	uint32_t buf_size = 0;
-+	uint8_t *align_buf_virt = NULL;
-+	dwc_dma_t align_buf_dma;
-+	struct device *dev = dwc_otg_hcd_to_dev(hcd);
-+
-+	/* Free each QTD in the QTD list */
-+	DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
-+	DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
-+		DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
-+		dwc_otg_hcd_qtd_free(qtd);
-+	}
-+
-+	if (hcd->core_if->dma_desc_enable) {
-+		dwc_otg_hcd_qh_free_ddma(hcd, qh);
-+	} else if (qh->dw_align_buf) {
-+		if (qh->ep_type == UE_ISOCHRONOUS) {
-+			buf_size = 4096;
-+		} else {
-+			buf_size = hcd->core_if->core_params->max_transfer_size;
-+		}
-+		align_buf_virt = qh->dw_align_buf;
-+		align_buf_dma = qh->dw_align_buf_dma;
-+	}
-+
-+	DWC_FREE(qh);
-+	DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
-+	if (align_buf_virt)
-+		DWC_DMA_FREE(dev, buf_size, align_buf_virt, align_buf_dma);
-+	return;
-+}
-+
-+#define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)
-+#define HS_HOST_DELAY		5	/* nanoseconds */
-+#define FS_LS_HOST_DELAY	1000	/* nanoseconds */
-+#define HUB_LS_SETUP		333	/* nanoseconds */
-+#define NS_TO_US(ns)		((ns + 500) / 1000)
-+				/* convert & round nanoseconds to microseconds */
-+
-+static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
-+{
-+	unsigned long retval;
-+
-+	switch (speed) {
-+	case USB_SPEED_HIGH:
-+		if (is_isoc) {
-+			retval =
-+			    ((38 * 8 * 2083) +
-+			     (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
-+			    HS_HOST_DELAY;
-+		} else {
-+			retval =
-+			    ((55 * 8 * 2083) +
-+			     (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
-+			    HS_HOST_DELAY;
-+		}
-+		break;
-+	case USB_SPEED_FULL:
-+		if (is_isoc) {
-+			retval =
-+			    (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
-+			if (is_in) {
-+				retval = 7268 + FS_LS_HOST_DELAY + retval;
-+			} else {
-+				retval = 6265 + FS_LS_HOST_DELAY + retval;
-+			}
-+		} else {
-+			retval =
-+			    (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
-+			retval = 9107 + FS_LS_HOST_DELAY + retval;
-+		}
-+		break;
-+	case USB_SPEED_LOW:
-+		if (is_in) {
-+			retval =
-+			    (67667 * (31 + 10 * BitStuffTime(bytecount))) /
-+			    1000;
-+			retval =
-+			    64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
-+			    retval;
-+		} else {
-+			retval =
-+			    (66700 * (31 + 10 * BitStuffTime(bytecount))) /
-+			    1000;
-+			retval =
-+			    64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
-+			    retval;
-+		}
-+		break;
-+	default:
-+		DWC_WARN("Unknown device speed\n");
-+		retval = -1;
-+	}
-+
-+	return NS_TO_US(retval);
-+}
-+
-+/**
-+ * Initializes a QH structure.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh  The QH to init.
-+ * @param urb Holds the information about the device/endpoint that we need
-+ * 	      to initialize the QH.
-+ */
-+#define SCHEDULE_SLOP 10
-+void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
-+{
-+	char *speed, *type;
-+	int dev_speed;
-+	uint32_t hub_addr, hub_port;
-+
-+	dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
-+
-+	/* Initialize QH */
-+	qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
-+	qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
-+
-+	qh->data_toggle = DWC_OTG_HC_PID_DATA0;
-+	qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
-+	DWC_CIRCLEQ_INIT(&qh->qtd_list);
-+	DWC_LIST_INIT(&qh->qh_list_entry);
-+	qh->channel = NULL;
-+
-+	/* FS/LS Enpoint on HS Hub
-+	 * NOT virtual root hub */
-+	dev_speed = hcd->fops->speed(hcd, urb->priv);
-+
-+	hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
-+	qh->do_split = 0;
-+	if (microframe_schedule)
-+		qh->speed = dev_speed;
-+
-+	qh->nak_frame = 0xffff;
-+
-+	if (((dev_speed == USB_SPEED_LOW) ||
-+	     (dev_speed == USB_SPEED_FULL)) &&
-+	    (hub_addr != 0 && hub_addr != 1)) {
-+		DWC_DEBUGPL(DBG_HCD,
-+			    "QH init: EP %d: TT found at hub addr %d, for port %d\n",
-+			    dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
-+			    hub_port);
-+		qh->do_split = 1;
-+		qh->skip_count = 0;
-+	}
-+
-+	if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
-+		/* Compute scheduling parameters once and save them. */
-+		hprt0_data_t hprt;
-+
-+		/** @todo Account for split transfers in the bus time. */
-+		int bytecount =
-+		    dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
-+
-+		qh->usecs =
-+		    calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
-+				  qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
-+				  bytecount);
-+		/* Start in a slightly future (micro)frame. */
-+		qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
-+						    SCHEDULE_SLOP);
-+		qh->interval = urb->interval;
-+
-+		hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
-+		if (hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) {
-+			if (dev_speed == USB_SPEED_LOW ||
-+					dev_speed == USB_SPEED_FULL) {
-+				qh->interval *= 8;
-+				qh->sched_frame |= 0x7;
-+				qh->start_split_frame = qh->sched_frame;
-+			} else if (int_ep_interval_min >= 2 &&
-+					qh->interval < int_ep_interval_min &&
-+					qh->ep_type == UE_INTERRUPT) {
-+				qh->interval = int_ep_interval_min;
-+			}
-+		}
-+	}
-+
-+	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
-+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
-+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
-+		    dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
-+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
-+		    dwc_otg_hcd_get_ep_num(&urb->pipe_info),
-+		    dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
-+	switch (dev_speed) {
-+	case USB_SPEED_LOW:
-+		qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
-+		speed = "low";
-+		break;
-+	case USB_SPEED_FULL:
-+		qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
-+		speed = "full";
-+		break;
-+	case USB_SPEED_HIGH:
-+		qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
-+		speed = "high";
-+		break;
-+	default:
-+		speed = "?";
-+		break;
-+	}
-+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
-+
-+	switch (qh->ep_type) {
-+	case UE_ISOCHRONOUS:
-+		type = "isochronous";
-+		break;
-+	case UE_INTERRUPT:
-+		type = "interrupt";
-+		break;
-+	case UE_CONTROL:
-+		type = "control";
-+		break;
-+	case UE_BULK:
-+		type = "bulk";
-+		break;
-+	default:
-+		type = "?";
-+		break;
-+	}
-+
-+	DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n", type);
-+
-+#ifdef DEBUG
-+	if (qh->ep_type == UE_INTERRUPT) {
-+		DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
-+			    qh->usecs);
-+		DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
-+			    qh->interval);
-+	}
-+#endif
-+
-+}
-+
-+/**
-+ * This function allocates and initializes a QH.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param urb Holds the information about the device/endpoint that we need
-+ * 	      to initialize the QH.
-+ * @param atomic_alloc Flag to do atomic allocation if needed
-+ *
-+ * @return Returns pointer to the newly allocated QH, or NULL on error. */
-+dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
-+				    dwc_otg_hcd_urb_t * urb, int atomic_alloc)
-+{
-+	dwc_otg_qh_t *qh;
-+
-+	/* Allocate memory */
-+	/** @todo add memflags argument */
-+	qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
-+	if (qh == NULL) {
-+		DWC_ERROR("qh allocation failed");
-+		return NULL;
-+	}
-+
-+	qh_init(hcd, qh, urb);
-+
-+	if (hcd->core_if->dma_desc_enable
-+	    && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
-+		dwc_otg_hcd_qh_free(hcd, qh);
-+		return NULL;
-+	}
-+
-+	return qh;
-+}
-+
-+/* microframe_schedule=0 start */
-+
-+/**
-+ * Checks that a channel is available for a periodic transfer.
-+ *
-+ * @return 0 if successful, negative error code otherise.
-+ */
-+static int periodic_channel_available(dwc_otg_hcd_t * hcd)
-+{
-+	/*
-+	 * Currently assuming that there is a dedicated host channnel for each
-+	 * periodic transaction plus at least one host channel for
-+	 * non-periodic transactions.
-+	 */
-+	int status;
-+	int num_channels;
-+
-+	num_channels = hcd->core_if->core_params->host_channels;
-+	if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
-+	    && (hcd->periodic_channels < num_channels - 1)) {
-+		status = 0;
-+	} else {
-+		DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
-+			__func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels);	//NOTICE
-+		status = -DWC_E_NO_SPACE;
-+	}
-+
-+	return status;
-+}
-+
-+/**
-+ * Checks that there is sufficient bandwidth for the specified QH in the
-+ * periodic schedule. For simplicity, this calculation assumes that all the
-+ * transfers in the periodic schedule may occur in the same (micro)frame.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH containing periodic bandwidth required.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	int status;
-+	int16_t max_claimed_usecs;
-+
-+	status = 0;
-+
-+	if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
-+		/*
-+		 * High speed mode.
-+		 * Max periodic usecs is 80% x 125 usec = 100 usec.
-+		 */
-+
-+		max_claimed_usecs = 100 - qh->usecs;
-+	} else {
-+		/*
-+		 * Full speed mode.
-+		 * Max periodic usecs is 90% x 1000 usec = 900 usec.
-+		 */
-+		max_claimed_usecs = 900 - qh->usecs;
-+	}
-+
-+	if (hcd->periodic_usecs > max_claimed_usecs) {
-+		DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs);	//NOTICE
-+		status = -DWC_E_NO_SPACE;
-+	}
-+
-+	return status;
-+}
-+
-+/* microframe_schedule=0 end */
-+
-+/**
-+ * Microframe scheduler
-+ * track the total use in hcd->frame_usecs
-+ * keep each qh use in qh->frame_usecs
-+ * when surrendering the qh then donate the time back
-+ */
-+const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
-+
-+/*
-+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init
-+ */
-+void init_hcd_usecs(dwc_otg_hcd_t *_hcd)
-+{
-+	int i;
-+	if (_hcd->flags.b.port_speed == DWC_HPRT0_PRTSPD_FULL_SPEED) {
-+		_hcd->frame_usecs[0] = 900;
-+		for (i = 1; i < 8; i++)
-+			_hcd->frame_usecs[i] = 0;
-+	} else {
-+		for (i = 0; i < 8; i++)
-+			_hcd->frame_usecs[i] = max_uframe_usecs[i];
-+	}
-+}
-+
-+static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+	int i;
-+	unsigned short utime;
-+	int t_left;
-+	int ret;
-+	int done;
-+
-+	ret = -1;
-+	utime = _qh->usecs;
-+	t_left = utime;
-+	i = 0;
-+	done = 0;
-+	while (done == 0) {
-+		/* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
-+		if (utime <= _hcd->frame_usecs[i]) {
-+			_hcd->frame_usecs[i] -= utime;
-+			_qh->frame_usecs[i] += utime;
-+			t_left -= utime;
-+			ret = i;
-+			done = 1;
-+			return ret;
-+		} else {
-+			i++;
-+			if (i == 8) {
-+				done = 1;
-+				ret = -1;
-+			}
-+		}
-+	}
-+	return ret;
-+ }
-+
-+/*
-+ * use this for FS apps that can span multiple uframes
-+  */
-+static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+	int i;
-+	int j;
-+	unsigned short utime;
-+	int t_left;
-+	int ret;
-+	int done;
-+	unsigned short xtime;
-+
-+	ret = -1;
-+	utime = _qh->usecs;
-+	t_left = utime;
-+	i = 0;
-+	done = 0;
-+loop:
-+	while (done == 0) {
-+		if(_hcd->frame_usecs[i] <= 0) {
-+			i++;
-+			if (i == 8) {
-+				done = 1;
-+				ret = -1;
-+			}
-+			goto loop;
-+		}
-+
-+		/*
-+		 * we need n consecutive slots
-+		 * so use j as a start slot j plus j+1 must be enough time (for now)
-+		 */
-+		xtime= _hcd->frame_usecs[i];
-+		for (j = i+1 ; j < 8 ; j++ ) {
-+                       /*
-+                        * if we add this frame remaining time to xtime we may
-+                        * be OK, if not we need to test j for a complete frame
-+                        */
-+                       if ((xtime+_hcd->frame_usecs[j]) < utime) {
-+                               if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
-+                                       j = 8;
-+                                       ret = -1;
-+                                       continue;
-+                               }
-+                       }
-+                       if (xtime >= utime) {
-+                               ret = i;
-+                               j = 8;  /* stop loop with a good value ret */
-+                               continue;
-+                       }
-+                       /* add the frame time to x time */
-+                       xtime += _hcd->frame_usecs[j];
-+		       /* we must have a fully available next frame or break */
-+		       if ((xtime < utime)
-+				       && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
-+			       ret = -1;
-+			       j = 8;  /* stop loop with a bad value ret */
-+			       continue;
-+		       }
-+		}
-+		if (ret >= 0) {
-+			t_left = utime;
-+			for (j = i; (t_left>0) && (j < 8); j++ ) {
-+				t_left -= _hcd->frame_usecs[j];
-+				if ( t_left <= 0 ) {
-+					_qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
-+					_hcd->frame_usecs[j]= -t_left;
-+					ret = i;
-+					done = 1;
-+				} else {
-+					_qh->frame_usecs[j] += _hcd->frame_usecs[j];
-+					_hcd->frame_usecs[j] = 0;
-+				}
-+			}
-+		} else {
-+			i++;
-+			if (i == 8) {
-+				done = 1;
-+				ret = -1;
-+			}
-+		}
-+	}
-+	return ret;
-+}
-+
-+static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
-+{
-+	int ret;
-+	ret = -1;
-+
-+	if (_qh->speed == USB_SPEED_HIGH ||
-+		_hcd->flags.b.port_speed == DWC_HPRT0_PRTSPD_FULL_SPEED) {
-+		/* if this is a hs transaction we need a full frame - or account for FS usecs */
-+		ret = find_single_uframe(_hcd, _qh);
-+	} else {
-+		/* if this is a fs transaction we may need a sequence of frames */
-+		ret = find_multi_uframe(_hcd, _qh);
-+	}
-+	return ret;
-+}
-+
-+/**
-+ * Checks that the max transfer size allowed in a host channel is large enough
-+ * to handle the maximum data transfer in a single (micro)frame for a periodic
-+ * transfer.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for a periodic endpoint.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	int status;
-+	uint32_t max_xfer_size;
-+	uint32_t max_channel_xfer_size;
-+
-+	status = 0;
-+
-+	max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
-+	max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
-+
-+	if (max_xfer_size > max_channel_xfer_size) {
-+		DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
-+				__func__, max_xfer_size, max_channel_xfer_size);	//NOTICE
-+		status = -DWC_E_NO_SPACE;
-+	}
-+
-+	return status;
-+}
-+
-+
-+
-+/**
-+ * Schedules an interrupt or isochronous transfer in the periodic schedule.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for the periodic transfer. The QH should already contain the
-+ * scheduling information.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	int status = 0;
-+
-+	if (microframe_schedule) {
-+		int frame;
-+		status = find_uframe(hcd, qh);
-+		frame = -1;
-+		if (status == 0) {
-+			frame = 7;
-+		} else {
-+			if (status > 0 )
-+				frame = status-1;
-+		}
-+
-+		/* Set the new frame up */
-+		if (frame > -1) {
-+			qh->sched_frame &= ~0x7;
-+			qh->sched_frame |= (frame & 7);
-+		}
-+
-+		if (status != -1)
-+			status = 0;
-+	} else {
-+		status = periodic_channel_available(hcd);
-+		if (status) {
-+			DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__);	//NOTICE
-+			return status;
-+		}
-+
-+		status = check_periodic_bandwidth(hcd, qh);
-+	}
-+	if (status) {
-+		DWC_INFO("%s: Insufficient periodic bandwidth for "
-+			    "periodic transfer.\n", __func__);
-+		return -DWC_E_NO_SPACE;
-+	}
-+	status = check_max_xfer_size(hcd, qh);
-+	if (status) {
-+		DWC_INFO("%s: Channel max transfer size too small "
-+			    "for periodic transfer.\n", __func__);
-+		return status;
-+	}
-+
-+	if (hcd->core_if->dma_desc_enable) {
-+		/* Don't rely on SOF and start in ready schedule */
-+		DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
-+	}
-+	else {
-+		if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)))
-+		{
-+			hcd->fiq_state->next_sched_frame = qh->sched_frame;
-+
-+		}
-+		/* Always start in the inactive schedule. */
-+		DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
-+	}
-+
-+	if (!microframe_schedule) {
-+		/* Reserve the periodic channel. */
-+		hcd->periodic_channels++;
-+	}
-+
-+	/* Update claimed usecs per (micro)frame. */
-+	hcd->periodic_usecs += qh->usecs;
-+
-+	return status;
-+}
-+
-+
-+/**
-+ * This function adds a QH to either the non periodic or periodic schedule if
-+ * it is not already in the schedule. If the QH is already in the schedule, no
-+ * action is taken.
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	int status = 0;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+		/* QH already in a schedule. */
-+		return status;
-+	}
-+
-+	/* Add the new QH to the appropriate schedule */
-+	if (dwc_qh_is_non_per(qh)) {
-+		/* Always start in the inactive schedule. */
-+		DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
-+				     &qh->qh_list_entry);
-+		//hcd->fiq_state->kick_np_queues = 1;
-+	} else {
-+		status = schedule_periodic(hcd, qh);
-+		if ( !hcd->periodic_qh_count ) {
-+			intr_mask.b.sofintr = 1;
-+			if (fiq_enable) {
-+				local_fiq_disable();
-+				fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+				DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+				fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+				local_fiq_enable();
-+			} else {
-+				DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
-+			}
-+		}
-+		hcd->periodic_qh_count++;
-+	}
-+
-+	return status;
-+}
-+
-+/**
-+ * Removes an interrupt or isochronous transfer from the periodic schedule.
-+ *
-+ * @param hcd The HCD state structure for the DWC OTG controller.
-+ * @param qh QH for the periodic transfer.
-+ */
-+static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	int i;
-+	DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
-+
-+	/* Update claimed usecs per (micro)frame. */
-+	hcd->periodic_usecs -= qh->usecs;
-+
-+	if (!microframe_schedule) {
-+		/* Release the periodic channel reservation. */
-+		hcd->periodic_channels--;
-+	} else {
-+		for (i = 0; i < 8; i++) {
-+			hcd->frame_usecs[i] += qh->frame_usecs[i];
-+			qh->frame_usecs[i] = 0;
-+		}
-+	}
-+}
-+
-+/**
-+ * Removes a QH from either the non-periodic or periodic schedule.  Memory is
-+ * not freed.
-+ *
-+ * @param hcd The HCD state structure.
-+ * @param qh QH to remove from schedule. */
-+void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
-+{
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
-+		/* QH is not in a schedule. */
-+		return;
-+	}
-+
-+	if (dwc_qh_is_non_per(qh)) {
-+		if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
-+			hcd->non_periodic_qh_ptr =
-+			    hcd->non_periodic_qh_ptr->next;
-+		}
-+		DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
-+		//if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive))
-+		//	hcd->fiq_state->kick_np_queues = 1;
-+	} else {
-+		deschedule_periodic(hcd, qh);
-+		hcd->periodic_qh_count--;
-+		if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
-+			intr_mask.b.sofintr = 1;
-+			if (fiq_enable) {
-+				local_fiq_disable();
-+				fiq_fsm_spin_lock(&hcd->fiq_state->lock);
-+				DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
-+				fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+				local_fiq_enable();
-+			} else {
-+				DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
-+			}
-+		}
-+	}
-+}
-+
-+/**
-+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active
-+ * non-periodic schedule. The QH is added to the inactive non-periodic
-+ * schedule if any QTDs are still attached to the QH.
-+ *
-+ * For periodic QHs, the QH is removed from the periodic queued schedule. If
-+ * there are any QTDs still attached to the QH, the QH is added to either the
-+ * periodic inactive schedule or the periodic ready schedule and its next
-+ * scheduled frame is calculated. The QH is placed in the ready schedule if
-+ * the scheduled frame has been reached already. Otherwise it's placed in the
-+ * inactive schedule. If there are no QTDs attached to the QH, the QH is
-+ * completely removed from the periodic schedule.
-+ */
-+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
-+			       int sched_next_periodic_split)
-+{
-+	if (dwc_qh_is_non_per(qh)) {
-+		dwc_otg_hcd_qh_remove(hcd, qh);
-+		if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+			/* Add back to inactive non-periodic schedule. */
-+			dwc_otg_hcd_qh_add(hcd, qh);
-+			//hcd->fiq_state->kick_np_queues = 1;
-+		} else {
-+			if(nak_holdoff && qh->do_split) {
-+				qh->nak_frame = 0xFFFF;
-+			}
-+		}
-+	} else {
-+		uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
-+
-+		if (qh->do_split) {
-+			/* Schedule the next continuing periodic split transfer */
-+			if (sched_next_periodic_split) {
-+
-+				qh->sched_frame = frame_number;
-+
-+				if (dwc_frame_num_le(frame_number,
-+						     dwc_frame_num_inc
-+						     (qh->start_split_frame,
-+						      1))) {
-+					/*
-+					 * Allow one frame to elapse after start
-+					 * split microframe before scheduling
-+					 * complete split, but DONT if we are
-+					 * doing the next start split in the
-+					 * same frame for an ISOC out.
-+					 */
-+					if ((qh->ep_type != UE_ISOCHRONOUS) ||
-+					    (qh->ep_is_in != 0)) {
-+						qh->sched_frame =
-+						    dwc_frame_num_inc(qh->sched_frame, 1);
-+					}
-+				}
-+			} else {
-+				qh->sched_frame =
-+				    dwc_frame_num_inc(qh->start_split_frame,
-+						      qh->interval);
-+				if (dwc_frame_num_le
-+				    (qh->sched_frame, frame_number)) {
-+					qh->sched_frame = frame_number;
-+				}
-+				qh->sched_frame |= 0x7;
-+				qh->start_split_frame = qh->sched_frame;
-+			}
-+		} else {
-+			qh->sched_frame =
-+			    dwc_frame_num_inc(qh->sched_frame, qh->interval);
-+			if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
-+				qh->sched_frame = frame_number;
-+			}
-+		}
-+
-+		if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
-+			dwc_otg_hcd_qh_remove(hcd, qh);
-+		} else {
-+			/*
-+			 * Remove from periodic_sched_queued and move to
-+			 * appropriate queue.
-+			 */
-+			if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||
-+			(!microframe_schedule && qh->sched_frame == frame_number)) {
-+				DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
-+						   &qh->qh_list_entry);
-+			} else {
-+				if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame))
-+				{
-+					hcd->fiq_state->next_sched_frame = qh->sched_frame;
-+				}
-+
-+				DWC_LIST_MOVE_HEAD
-+				    (&hcd->periodic_sched_inactive,
-+				     &qh->qh_list_entry);
-+			}
-+		}
-+	}
-+}
-+
-+/**
-+ * This function allocates and initializes a QTD.
-+ *
-+ * @param urb The URB to create a QTD from.  Each URB-QTD pair will end up
-+ * 	      pointing to each other so each pair should have a unique correlation.
-+ * @param atomic_alloc Flag to do atomic alloc if needed
-+ *
-+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */
-+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
-+{
-+	dwc_otg_qtd_t *qtd;
-+
-+	qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
-+	if (qtd == NULL) {
-+		return NULL;
-+	}
-+
-+	dwc_otg_hcd_qtd_init(qtd, urb);
-+	return qtd;
-+}
-+
-+/**
-+ * Initializes a QTD structure.
-+ *
-+ * @param qtd The QTD to initialize.
-+ * @param urb The URB to use for initialization.  */
-+void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
-+{
-+	dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
-+	qtd->urb = urb;
-+	if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
-+		/*
-+		 * The only time the QTD data toggle is used is on the data
-+		 * phase of control transfers. This phase always starts with
-+		 * DATA1.
-+		 */
-+		qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
-+		qtd->control_phase = DWC_OTG_CONTROL_SETUP;
-+	}
-+
-+	/* start split */
-+	qtd->complete_split = 0;
-+	qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
-+	qtd->isoc_split_offset = 0;
-+	qtd->in_process = 0;
-+
-+	/* Store the qtd ptr in the urb to reference what QTD. */
-+	urb->qtd = qtd;
-+	return;
-+}
-+
-+/**
-+ * This function adds a QTD to the QTD-list of a QH.  It will find the correct
-+ * QH to place the QTD into.  If it does not find a QH, then it will create a
-+ * new QH. If the QH to which the QTD is added is not currently scheduled, it
-+ * is placed into the proper schedule based on its EP type.
-+ * HCD lock must be held and interrupts must be disabled on entry
-+ *
-+ * @param[in] qtd The QTD to add
-+ * @param[in] hcd The DWC HCD structure
-+ * @param[out] qh out parameter to return queue head
-+ * @param atomic_alloc Flag to do atomic alloc if needed
-+ *
-+ * @return 0 if successful, negative error code otherwise.
-+ */
-+int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
-+			dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
-+{
-+	int retval = 0;
-+	dwc_otg_hcd_urb_t *urb = qtd->urb;
-+
-+	/*
-+	 * Get the QH which holds the QTD-list to insert to. Create QH if it
-+	 * doesn't exist.
-+	 */
-+	if (*qh == NULL) {
-+		*qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
-+		if (*qh == NULL) {
-+			retval = -DWC_E_NO_MEMORY;
-+			goto done;
-+		} else {
-+			if (fiq_enable)
-+				hcd->fiq_state->kick_np_queues = 1;
-+		}
-+	}
-+	retval = dwc_otg_hcd_qh_add(hcd, *qh);
-+	if (retval == 0) {
-+		DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
-+					qtd_list_entry);
-+		qtd->qh = *qh;
-+	}
-+done:
-+
-+	return retval;
-+}
-+
-+#endif /* DWC_DEVICE_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
-@@ -0,0 +1,188 @@
-+#ifndef _DWC_OS_DEP_H_
-+#define _DWC_OS_DEP_H_
-+
-+/**
-+ * @file
-+ *
-+ * This file contains OS dependent structures.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/slab.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/ctype.h>
-+#include <linux/string.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/jiffies.h>
-+#include <linux/delay.h>
-+#include <linux/timer.h>
-+#include <linux/workqueue.h>
-+#include <linux/stat.h>
-+#include <linux/pci.h>
-+
-+#include <linux/version.h>
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
-+# include <linux/irq.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
-+# include <linux/usb/ch9.h>
-+#else
-+# include <linux/usb_ch9.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
-+# include <linux/usb/gadget.h>
-+#else
-+# include <linux/usb_gadget.h>
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-+# include <asm/irq.h>
-+#endif
-+
-+#ifdef PCI_INTERFACE
-+# include <asm/io.h>
-+#endif
-+
-+#ifdef LM_INTERFACE
-+# include <asm/unaligned.h>
-+# include <asm/sizes.h>
-+# include <asm/param.h>
-+# include <asm/io.h>
-+# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
-+#  include <asm/arch/hardware.h>
-+#  include <asm/arch/lm.h>
-+#  include <asm/arch/irqs.h>
-+#  include <asm/arch/regs-irq.h>
-+# else
-+/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
-+   here we assume that the machine architecture provides definitions
-+   in its own header
-+*/
-+#  include <mach/lm.h>
-+#  include <mach/hardware.h>
-+# endif
-+#endif
-+
-+#ifdef PLATFORM_INTERFACE
-+#include <linux/platform_device.h>
-+#include <asm/mach/map.h>
-+#endif
-+
-+/** The OS page size */
-+#define DWC_OS_PAGE_SIZE	PAGE_SIZE
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
-+typedef int gfp_t;
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
-+# define IRQF_SHARED SA_SHIRQ
-+#endif
-+
-+typedef struct os_dependent {
-+	/** Base address returned from ioremap() */
-+	void *base;
-+
-+	/** Register offset for Diagnostic API */
-+	uint32_t reg_offset;
-+
-+	/** Base address for MPHI peripheral */
-+	void *mphi_base;
-+
-+#ifdef LM_INTERFACE
-+	struct lm_device *lmdev;
-+#elif  defined(PCI_INTERFACE)
-+	struct pci_dev *pcidev;
-+
-+	/** Start address of a PCI region */
-+	resource_size_t rsrc_start;
-+
-+	/** Length address of a PCI region */
-+	resource_size_t rsrc_len;
-+#elif  defined(PLATFORM_INTERFACE)
-+	struct platform_device *platformdev;
-+#endif
-+
-+} os_dependent_t;
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+
-+
-+
-+/* Type for the our device on the chosen bus */
-+#if   defined(LM_INTERFACE)
-+typedef struct lm_device       dwc_bus_dev_t;
-+#elif defined(PCI_INTERFACE)
-+typedef struct pci_dev         dwc_bus_dev_t;
-+#elif defined(PLATFORM_INTERFACE)
-+typedef struct platform_device dwc_bus_dev_t;
-+#endif
-+
-+/* Helper macro to retrieve drvdata from the device on the chosen bus */
-+#if    defined(LM_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)
-+#elif  defined(PCI_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)
-+#elif  defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)
-+#endif
-+
-+/**
-+ * Helper macro returning the otg_device structure of a given struct device
-+ *
-+ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+                struct lm_device *lm_dev = \
-+                        container_of(_dev, struct lm_device, dev); \
-+                _var = lm_get_drvdata(lm_dev); \
-+        } while (0)
-+
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+                _var = dev_get_drvdata(_dev); \
-+        } while (0)
-+
-+#elif defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
-+                struct platform_device *platform_dev = \
-+                        container_of(_dev, struct platform_device, dev); \
-+                _var = platform_get_drvdata(platform_dev); \
-+        } while (0)
-+#endif
-+
-+
-+/**
-+ * Helper macro returning the struct dev of the given struct os_dependent
-+ *
-+ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)
-+ */
-+#ifdef LM_INTERFACE
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+        ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)
-+#elif defined(PCI_INTERFACE)
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+        ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)
-+#elif defined(PLATFORM_INTERFACE)
-+#define DWC_OTG_OS_GETDEV(_osdep) \
-+        ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)
-+#endif
-+
-+
-+
-+
-+#endif /* _DWC_OS_DEP_H_ */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
-@@ -0,0 +1,2725 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
-+ * $Revision: #101 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+/** @file
-+ * This file implements PCD Core. All code in this file is portable and doesn't
-+ * use any OS specific functions.
-+ * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
-+ * header file, which can be used to implement OS specific PCD interface.
-+ *
-+ * An important function of the PCD is managing interrupts generated
-+ * by the DWC_otg controller. The implementation of the DWC_otg device
-+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
-+ *
-+ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
-+ * @todo Does it work when the request size is greater than DEPTSIZ
-+ * transfer size
-+ *
-+ */
-+
-+#include "dwc_otg_pcd.h"
-+
-+#ifdef DWC_UTE_CFI
-+#include "dwc_otg_cfi.h"
-+
-+extern int init_cfi(cfiobject_t * cfiobj);
-+#endif
-+
-+/**
-+ * Choose endpoint from ep arrays using usb_ep structure.
-+ */
-+static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
-+{
-+	int i;
-+	if (pcd->ep0.priv == handle) {
-+		return &pcd->ep0;
-+	}
-+	for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
-+		if (pcd->in_ep[i].priv == handle)
-+			return &pcd->in_ep[i];
-+		if (pcd->out_ep[i].priv == handle)
-+			return &pcd->out_ep[i];
-+	}
-+
-+	return NULL;
-+}
-+
-+/**
-+ * This function completes a request.  It call's the request call back.
-+ */
-+void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
-+			  int32_t status)
-+{
-+	unsigned stopped = ep->stopped;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
-+	DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
-+
-+	/* don't modify queue heads during completion callback */
-+	ep->stopped = 1;
-+	/* spin_unlock/spin_lock now done in fops->complete() */
-+	ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
-+				req->actual);
-+
-+	if (ep->pcd->request_pending > 0) {
-+		--ep->pcd->request_pending;
-+	}
-+
-+	ep->stopped = stopped;
-+	DWC_FREE(req);
-+}
-+
-+/**
-+ * This function terminates all the requsts in the EP request queue.
-+ */
-+void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
-+{
-+	dwc_otg_pcd_request_t *req;
-+
-+	ep->stopped = 1;
-+
-+	/* called with irqs blocked?? */
-+	while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+		dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
-+	}
-+}
-+
-+void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
-+		       const struct dwc_otg_pcd_function_ops *fops)
-+{
-+	pcd->fops = fops;
-+}
-+
-+/**
-+ * PCD Callback function for initializing the PCD when switching to
-+ * device mode.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_start_cb(void *p)
-+{
-+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+	/*
-+	 * Initialized the Core for Device mode.
-+	 */
-+	if (dwc_otg_is_device_mode(core_if)) {
-+		dwc_otg_core_dev_init(core_if);
-+		/* Set core_if's lock pointer to the pcd->lock */
-+		core_if->lock = pcd->lock;
-+	}
-+	return 1;
-+}
-+
-+/** CFI-specific buffer allocation function for EP */
-+#ifdef DWC_UTE_CFI
-+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
-+			      size_t buflen, int flags)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+	ep = get_ep_from_handle(pcd, pep);
-+	if (!ep) {
-+		DWC_WARN("bad ep\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
-+					  flags);
-+}
-+#else
-+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
-+			      size_t buflen, int flags);
-+#endif
-+
-+/**
-+ * PCD Callback function for notifying the PCD when resuming from
-+ * suspend.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_resume_cb(void *p)
-+{
-+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+
-+	if (pcd->fops->resume) {
-+		pcd->fops->resume(pcd);
-+	}
-+
-+	/* Stop the SRP timeout timer. */
-+	if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
-+	    || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
-+		if (GET_CORE_IF(pcd)->srp_timer_started) {
-+			GET_CORE_IF(pcd)->srp_timer_started = 0;
-+			DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
-+		}
-+	}
-+	return 1;
-+}
-+
-+/**
-+ * PCD Callback function for notifying the PCD device is suspended.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_suspend_cb(void *p)
-+{
-+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+
-+	if (pcd->fops->suspend) {
-+		DWC_SPINUNLOCK(pcd->lock);
-+		pcd->fops->suspend(pcd);
-+		DWC_SPINLOCK(pcd->lock);
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * PCD Callback function for stopping the PCD when switching to Host
-+ * mode.
-+ *
-+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>
-+ */
-+static int32_t dwc_otg_pcd_stop_cb(void *p)
-+{
-+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
-+	extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
-+
-+	dwc_otg_pcd_stop(pcd);
-+	return 1;
-+}
-+
-+/**
-+ * PCD Callback structure for handling mode switching.
-+ */
-+static dwc_otg_cil_callbacks_t pcd_callbacks = {
-+	.start = dwc_otg_pcd_start_cb,
-+	.stop = dwc_otg_pcd_stop_cb,
-+	.suspend = dwc_otg_pcd_suspend_cb,
-+	.resume_wakeup = dwc_otg_pcd_resume_cb,
-+	.p = 0,			/* Set at registration */
-+};
-+
-+/**
-+ * This function allocates a DMA Descriptor chain for the Endpoint
-+ * buffer to be used for a transfer to/from the specified endpoint.
-+ */
-+dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(struct device *dev,
-+						    dwc_dma_t * dma_desc_addr,
-+						    uint32_t count)
-+{
-+	return DWC_DMA_ALLOC_ATOMIC(dev, count * sizeof(dwc_otg_dev_dma_desc_t),
-+							dma_desc_addr);
-+}
-+
-+/**
-+ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
-+ */
-+void dwc_otg_ep_free_desc_chain(struct device *dev,
-+				dwc_otg_dev_dma_desc_t * desc_addr,
-+				uint32_t dma_desc_addr, uint32_t count)
-+{
-+	DWC_DMA_FREE(dev, count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
-+		     dma_desc_addr);
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
-+					dwc_ep_t * dwc_ep)
-+{
-+
-+	dsts_data_t dsts = {.d32 = 0 };
-+	depctl_data_t depctl = {.d32 = 0 };
-+	volatile uint32_t *addr;
-+	int i, j;
-+	uint32_t len;
-+
-+	if (dwc_ep->is_in)
-+		dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
-+	else
-+		dwc_ep->desc_cnt =
-+		    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+		    dwc_ep->bInterval;
-+
-+	/** Allocate descriptors for double buffering */
-+	dwc_ep->iso_desc_addr =
-+	    dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
-+					dwc_ep->desc_cnt * 2);
-+	if (dwc_ep->desc_addr) {
-+		DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
-+		return;
-+	}
-+
-+	dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+	/** ISO OUT EP */
-+	if (dwc_ep->is_in == 0) {
-+		dev_dma_desc_sts_t sts = {.d32 = 0 };
-+		dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
-+		dma_addr_t dma_ad;
-+		uint32_t data_per_desc;
-+		dwc_otg_dev_out_ep_regs_t *out_regs =
-+		    core_if->dev_if->out_ep_regs[dwc_ep->num];
-+		int offset;
-+
-+		addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
-+		dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
-+
-+		/** Buffer 0 descriptors setup */
-+		dma_ad = dwc_ep->dma_addr0;
-+
-+		sts.b_iso_out.bs = BS_HOST_READY;
-+		sts.b_iso_out.rxsts = 0;
-+		sts.b_iso_out.l = 0;
-+		sts.b_iso_out.sp = 0;
-+		sts.b_iso_out.ioc = 0;
-+		sts.b_iso_out.pid = 0;
-+		sts.b_iso_out.framenum = 0;
-+
-+		offset = 0;
-+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+		     i += dwc_ep->pkt_per_frm) {
-+
-+			for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+				uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+				if (len > dwc_ep->data_per_frame)
-+					data_per_desc =
-+					    dwc_ep->data_per_frame -
-+					    j * dwc_ep->maxpacket;
-+				else
-+					data_per_desc = dwc_ep->maxpacket;
-+				len = data_per_desc % 4;
-+				if (len)
-+					data_per_desc += 4 - len;
-+
-+				sts.b_iso_out.rxbytes = data_per_desc;
-+				dma_desc->buf = dma_ad;
-+				dma_desc->status.d32 = sts.d32;
-+
-+				offset += data_per_desc;
-+				dma_desc++;
-+				dma_ad += data_per_desc;
-+			}
-+		}
-+
-+		for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+			uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+			if (len > dwc_ep->data_per_frame)
-+				data_per_desc =
-+				    dwc_ep->data_per_frame -
-+				    j * dwc_ep->maxpacket;
-+			else
-+				data_per_desc = dwc_ep->maxpacket;
-+			len = data_per_desc % 4;
-+			if (len)
-+				data_per_desc += 4 - len;
-+			sts.b_iso_out.rxbytes = data_per_desc;
-+			dma_desc->buf = dma_ad;
-+			dma_desc->status.d32 = sts.d32;
-+
-+			offset += data_per_desc;
-+			dma_desc++;
-+			dma_ad += data_per_desc;
-+		}
-+
-+		sts.b_iso_out.ioc = 1;
-+		len = (j + 1) * dwc_ep->maxpacket;
-+		if (len > dwc_ep->data_per_frame)
-+			data_per_desc =
-+			    dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
-+		else
-+			data_per_desc = dwc_ep->maxpacket;
-+		len = data_per_desc % 4;
-+		if (len)
-+			data_per_desc += 4 - len;
-+		sts.b_iso_out.rxbytes = data_per_desc;
-+
-+		dma_desc->buf = dma_ad;
-+		dma_desc->status.d32 = sts.d32;
-+		dma_desc++;
-+
-+		/** Buffer 1 descriptors setup */
-+		sts.b_iso_out.ioc = 0;
-+		dma_ad = dwc_ep->dma_addr1;
-+
-+		offset = 0;
-+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+		     i += dwc_ep->pkt_per_frm) {
-+			for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+				uint32_t len = (j + 1) * dwc_ep->maxpacket;
-+				if (len > dwc_ep->data_per_frame)
-+					data_per_desc =
-+					    dwc_ep->data_per_frame -
-+					    j * dwc_ep->maxpacket;
-+				else
-+					data_per_desc = dwc_ep->maxpacket;
-+				len = data_per_desc % 4;
-+				if (len)
-+					data_per_desc += 4 - len;
-+
-+				data_per_desc =
-+				    sts.b_iso_out.rxbytes = data_per_desc;
-+				dma_desc->buf = dma_ad;
-+				dma_desc->status.d32 = sts.d32;
-+
-+				offset += data_per_desc;
-+				dma_desc++;
-+				dma_ad += data_per_desc;
-+			}
-+		}
-+		for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+			data_per_desc =
-+			    ((j + 1) * dwc_ep->maxpacket >
-+			     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+			    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+			data_per_desc +=
-+			    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+			sts.b_iso_out.rxbytes = data_per_desc;
-+			dma_desc->buf = dma_ad;
-+			dma_desc->status.d32 = sts.d32;
-+
-+			offset += data_per_desc;
-+			dma_desc++;
-+			dma_ad += data_per_desc;
-+		}
-+
-+		sts.b_iso_out.ioc = 1;
-+		sts.b_iso_out.l = 1;
-+		data_per_desc =
-+		    ((j + 1) * dwc_ep->maxpacket >
-+		     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+		    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+		data_per_desc +=
-+		    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+		sts.b_iso_out.rxbytes = data_per_desc;
-+
-+		dma_desc->buf = dma_ad;
-+		dma_desc->status.d32 = sts.d32;
-+
-+		dwc_ep->next_frame = 0;
-+
-+		/** Write dma_ad into DOEPDMA register */
-+		DWC_WRITE_REG32(&(out_regs->doepdma),
-+				(uint32_t) dwc_ep->iso_dma_desc_addr);
-+
-+	}
-+	/** ISO IN EP */
-+	else {
-+		dev_dma_desc_sts_t sts = {.d32 = 0 };
-+		dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
-+		dma_addr_t dma_ad;
-+		dwc_otg_dev_in_ep_regs_t *in_regs =
-+		    core_if->dev_if->in_ep_regs[dwc_ep->num];
-+		unsigned int frmnumber;
-+		fifosize_data_t txfifosize, rxfifosize;
-+
-+		txfifosize.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
-+				   dtxfsts);
-+		rxfifosize.d32 =
-+		    DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
-+
-+		addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+
-+		dma_ad = dwc_ep->dma_addr0;
-+
-+		dsts.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+		sts.b_iso_in.bs = BS_HOST_READY;
-+		sts.b_iso_in.txsts = 0;
-+		sts.b_iso_in.sp =
-+		    (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
-+		sts.b_iso_in.ioc = 0;
-+		sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
-+
-+		frmnumber = dwc_ep->next_frame;
-+
-+		sts.b_iso_in.framenum = frmnumber;
-+		sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
-+		sts.b_iso_in.l = 0;
-+
-+		/** Buffer 0 descriptors setup */
-+		for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+			dma_desc->buf = dma_ad;
-+			dma_desc->status.d32 = sts.d32;
-+			dma_desc++;
-+
-+			dma_ad += dwc_ep->data_per_frame;
-+			sts.b_iso_in.framenum += dwc_ep->bInterval;
-+		}
-+
-+		sts.b_iso_in.ioc = 1;
-+		dma_desc->buf = dma_ad;
-+		dma_desc->status.d32 = sts.d32;
-+		++dma_desc;
-+
-+		/** Buffer 1 descriptors setup */
-+		sts.b_iso_in.ioc = 0;
-+		dma_ad = dwc_ep->dma_addr1;
-+
-+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+		     i += dwc_ep->pkt_per_frm) {
-+			dma_desc->buf = dma_ad;
-+			dma_desc->status.d32 = sts.d32;
-+			dma_desc++;
-+
-+			dma_ad += dwc_ep->data_per_frame;
-+			sts.b_iso_in.framenum += dwc_ep->bInterval;
-+
-+			sts.b_iso_in.ioc = 0;
-+		}
-+		sts.b_iso_in.ioc = 1;
-+		sts.b_iso_in.l = 1;
-+
-+		dma_desc->buf = dma_ad;
-+		dma_desc->status.d32 = sts.d32;
-+
-+		dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
-+
-+		/** Write dma_ad into diepdma register */
-+		DWC_WRITE_REG32(&(in_regs->diepdma),
-+				(uint32_t) dwc_ep->iso_dma_desc_addr);
-+	}
-+	/** Enable endpoint, clear nak  */
-+	depctl.d32 = 0;
-+	depctl.b.epena = 1;
-+	depctl.b.usbactep = 1;
-+	depctl.b.cnak = 1;
-+
-+	DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+	depctl.d32 = DWC_READ_REG32(addr);
-+}
-+
-+/**
-+ * This function initializes a descriptor chain for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
-+				       dwc_ep_t * ep)
-+{
-+	depctl_data_t depctl = {.d32 = 0 };
-+	volatile uint32_t *addr;
-+
-+	if (ep->is_in) {
-+		addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+	} else {
-+		addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+	}
-+
-+	if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
-+		return;
-+	} else {
-+		deptsiz_data_t deptsiz = {.d32 = 0 };
-+
-+		ep->xfer_len =
-+		    ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
-+		ep->pkt_cnt =
-+		    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+		ep->xfer_count = 0;
-+		ep->xfer_buff =
-+		    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
-+		ep->dma_addr =
-+		    (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
-+
-+		if (ep->is_in) {
-+			/* Program the transfer size and packet count
-+			 *      as follows: xfersize = N * maxpacket +
-+			 *      short_packet pktcnt = N + (short_packet
-+			 *      exist ? 1 : 0)
-+			 */
-+			deptsiz.b.mc = ep->pkt_per_frm;
-+			deptsiz.b.xfersize = ep->xfer_len;
-+			deptsiz.b.pktcnt =
-+			    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
-+			DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+					dieptsiz, deptsiz.d32);
-+
-+			/* Write the DMA register */
-+			DWC_WRITE_REG32(&
-+					(core_if->dev_if->in_ep_regs[ep->num]->
-+					 diepdma), (uint32_t) ep->dma_addr);
-+
-+		} else {
-+			deptsiz.b.pktcnt =
-+			    (ep->xfer_len + (ep->maxpacket - 1)) /
-+			    ep->maxpacket;
-+			deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
-+
-+			DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
-+					doeptsiz, deptsiz.d32);
-+
-+			/* Write the DMA register */
-+			DWC_WRITE_REG32(&
-+					(core_if->dev_if->out_ep_regs[ep->num]->
-+					 doepdma), (uint32_t) ep->dma_addr);
-+
-+		}
-+		/** Enable endpoint, clear nak  */
-+		depctl.d32 = 0;
-+		depctl.b.epena = 1;
-+		depctl.b.cnak = 1;
-+
-+		DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+	}
-+}
-+
-+/**
-+ * This function does the setup for a data transfer for an EP and
-+ * starts the transfer. For an IN transfer, the packets will be
-+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
-+ * the packets are unloaded from the Rx FIFO in the ISR.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
-+					  dwc_ep_t * ep)
-+{
-+	if (core_if->dma_enable) {
-+		if (core_if->dma_desc_enable) {
-+			if (ep->is_in) {
-+				ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
-+			} else {
-+				ep->desc_cnt = ep->pkt_cnt;
-+			}
-+			dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
-+		} else {
-+			if (core_if->pti_enh_enable) {
-+				dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
-+			} else {
-+				ep->cur_pkt_addr =
-+				    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
-+				    xfer_buff0;
-+				ep->cur_pkt_dma_addr =
-+				    (ep->proc_buf_num) ? ep->dma_addr1 : ep->
-+				    dma_addr0;
-+				dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
-+			}
-+		}
-+	} else {
-+		ep->cur_pkt_addr =
-+		    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
-+		ep->cur_pkt_dma_addr =
-+		    (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
-+		dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
-+	}
-+}
-+
-+/**
-+ * This function stops transfer for an EP and
-+ * resets the ep's variables.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ */
-+
-+void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	depctl_data_t depctl = {.d32 = 0 };
-+	volatile uint32_t *addr;
-+
-+	if (ep->is_in == 1) {
-+		addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
-+	} else {
-+		addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
-+	}
-+
-+	/* disable the ep */
-+	depctl.d32 = DWC_READ_REG32(addr);
-+
-+	depctl.b.epdis = 1;
-+	depctl.b.snak = 1;
-+
-+	DWC_WRITE_REG32(addr, depctl.d32);
-+
-+	if (core_if->dma_desc_enable &&
-+	    ep->iso_desc_addr && ep->iso_dma_desc_addr) {
-+		dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
-+					   ep->iso_dma_desc_addr,
-+					   ep->desc_cnt * 2);
-+	}
-+
-+	/* reset varibales */
-+	ep->dma_addr0 = 0;
-+	ep->dma_addr1 = 0;
-+	ep->xfer_buff0 = 0;
-+	ep->xfer_buff1 = 0;
-+	ep->data_per_frame = 0;
-+	ep->data_pattern_frame = 0;
-+	ep->sync_frame = 0;
-+	ep->buf_proc_intrvl = 0;
-+	ep->bInterval = 0;
-+	ep->proc_buf_num = 0;
-+	ep->pkt_per_frm = 0;
-+	ep->pkt_per_frm = 0;
-+	ep->desc_cnt = 0;
-+	ep->iso_desc_addr = 0;
-+	ep->iso_dma_desc_addr = 0;
-+}
-+
-+int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
-+			     uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
-+			     dwc_dma_t dma1, int sync_frame, int dp_frame,
-+			     int data_per_frame, int start_frame,
-+			     int buf_proc_intrvl, void *req_handle,
-+			     int atomic_alloc)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_irqflags_t flags = 0;
-+	dwc_ep_t *dwc_ep;
-+	int32_t frm_data;
-+	dsts_data_t dsts;
-+	dwc_otg_core_if_t *core_if;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+
-+	if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
-+		DWC_WARN("bad ep\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+	core_if = GET_CORE_IF(pcd);
-+	dwc_ep = &ep->dwc_ep;
-+
-+	if (ep->iso_req_handle) {
-+		DWC_WARN("ISO request in progress\n");
-+	}
-+
-+	dwc_ep->dma_addr0 = dma0;
-+	dwc_ep->dma_addr1 = dma1;
-+
-+	dwc_ep->xfer_buff0 = buf0;
-+	dwc_ep->xfer_buff1 = buf1;
-+
-+	dwc_ep->data_per_frame = data_per_frame;
-+
-+	/** @todo - pattern data support is to be implemented in the future */
-+	dwc_ep->data_pattern_frame = dp_frame;
-+	dwc_ep->sync_frame = sync_frame;
-+
-+	dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
-+
-+	dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
-+
-+	dwc_ep->proc_buf_num = 0;
-+
-+	dwc_ep->pkt_per_frm = 0;
-+	frm_data = ep->dwc_ep.data_per_frame;
-+	while (frm_data > 0) {
-+		dwc_ep->pkt_per_frm++;
-+		frm_data -= ep->dwc_ep.maxpacket;
-+	}
-+
-+	dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+	if (start_frame == -1) {
-+		dwc_ep->next_frame = dsts.b.soffn + 1;
-+		if (dwc_ep->bInterval != 1) {
-+			dwc_ep->next_frame =
-+			    dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
-+						  dwc_ep->next_frame %
-+						  dwc_ep->bInterval);
-+		}
-+	} else {
-+		dwc_ep->next_frame = start_frame;
-+	}
-+
-+	if (!core_if->pti_enh_enable) {
-+		dwc_ep->pkt_cnt =
-+		    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+		    dwc_ep->bInterval;
-+	} else {
-+		dwc_ep->pkt_cnt =
-+		    (dwc_ep->data_per_frame *
-+		     (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
-+		     - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
-+	}
-+
-+	if (core_if->dma_desc_enable) {
-+		dwc_ep->desc_cnt =
-+		    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
-+		    dwc_ep->bInterval;
-+	}
-+
-+	if (atomic_alloc) {
-+		dwc_ep->pkt_info =
-+		    DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+	} else {
-+		dwc_ep->pkt_info =
-+		    DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+	}
-+	if (!dwc_ep->pkt_info) {
-+		DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+		return -DWC_E_NO_MEMORY;
-+	}
-+	if (core_if->pti_enh_enable) {
-+		dwc_memset(dwc_ep->pkt_info, 0,
-+			   sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
-+	}
-+
-+	dwc_ep->cur_pkt = 0;
-+	ep->iso_req_handle = req_handle;
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+	dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
-+	return 0;
-+}
-+
-+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
-+			    void *req_handle)
-+{
-+	dwc_irqflags_t flags = 0;
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_ep_t *dwc_ep;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+	if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
-+		DWC_WARN("bad ep\n");
-+		return -DWC_E_INVALID;
-+	}
-+	dwc_ep = &ep->dwc_ep;
-+
-+	dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
-+
-+	DWC_FREE(dwc_ep->pkt_info);
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+	if (ep->iso_req_handle != req_handle) {
-+		DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+	ep->iso_req_handle = 0;
-+	return 0;
-+}
-+
-+/**
-+ * This function is used for perodical data exchnage between PCD and gadget drivers.
-+ * for Isochronous EPs
-+ *
-+ *	- Every time a sync period completes this function is called to
-+ *	  perform data exchange between PCD and gadget
-+ */
-+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
-+			     void *req_handle)
-+{
-+	int i;
-+	dwc_ep_t *dwc_ep;
-+
-+	dwc_ep = &ep->dwc_ep;
-+
-+	DWC_SPINUNLOCK(ep->pcd->lock);
-+	pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
-+				 dwc_ep->proc_buf_num ^ 0x1);
-+	DWC_SPINLOCK(ep->pcd->lock);
-+
-+	for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
-+		dwc_ep->pkt_info[i].status = 0;
-+		dwc_ep->pkt_info[i].offset = 0;
-+		dwc_ep->pkt_info[i].length = 0;
-+	}
-+}
-+
-+int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
-+				     void *iso_req_handle)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_ep_t *dwc_ep;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+	if (!ep->desc || ep->dwc_ep.num == 0) {
-+		DWC_WARN("bad ep\n");
-+		return -DWC_E_INVALID;
-+	}
-+	dwc_ep = &ep->dwc_ep;
-+
-+	return dwc_ep->pkt_cnt;
-+}
-+
-+void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
-+				       void *iso_req_handle, int packet,
-+				       int *status, int *actual, int *offset)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_ep_t *dwc_ep;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+	if (!ep)
-+		DWC_WARN("bad ep\n");
-+
-+	dwc_ep = &ep->dwc_ep;
-+
-+	*status = dwc_ep->pkt_info[packet].status;
-+	*actual = dwc_ep->pkt_info[packet].length;
-+	*offset = dwc_ep->pkt_info[packet].offset;
-+}
-+
-+#endif /* DWC_EN_ISOC */
-+
-+static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
-+				uint32_t is_in, uint32_t ep_num)
-+{
-+	/* Init EP structure */
-+	pcd_ep->desc = 0;
-+	pcd_ep->pcd = pcd;
-+	pcd_ep->stopped = 1;
-+	pcd_ep->queue_sof = 0;
-+
-+	/* Init DWC ep structure */
-+	pcd_ep->dwc_ep.is_in = is_in;
-+	pcd_ep->dwc_ep.num = ep_num;
-+	pcd_ep->dwc_ep.active = 0;
-+	pcd_ep->dwc_ep.tx_fifo_num = 0;
-+	/* Control until ep is actvated */
-+	pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
-+	pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
-+	pcd_ep->dwc_ep.dma_addr = 0;
-+	pcd_ep->dwc_ep.start_xfer_buff = 0;
-+	pcd_ep->dwc_ep.xfer_buff = 0;
-+	pcd_ep->dwc_ep.xfer_len = 0;
-+	pcd_ep->dwc_ep.xfer_count = 0;
-+	pcd_ep->dwc_ep.sent_zlp = 0;
-+	pcd_ep->dwc_ep.total_len = 0;
-+	pcd_ep->dwc_ep.desc_addr = 0;
-+	pcd_ep->dwc_ep.dma_desc_addr = 0;
-+	DWC_CIRCLEQ_INIT(&pcd_ep->queue);
-+}
-+
-+/**
-+ * Initialize ep's
-+ */
-+static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
-+{
-+	int i;
-+	uint32_t hwcfg1;
-+	dwc_otg_pcd_ep_t *ep;
-+	int in_ep_cntr, out_ep_cntr;
-+	uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
-+	uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
-+
-+	/**
-+	 * Initialize the EP0 structure.
-+	 */
-+	ep = &pcd->ep0;
-+	dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
-+
-+	in_ep_cntr = 0;
-+	hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
-+	for (i = 1; in_ep_cntr < num_in_eps; i++) {
-+		if ((hwcfg1 & 0x1) == 0) {
-+			dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
-+			in_ep_cntr++;
-+			/**
-+			 * @todo NGS: Add direction to EP, based on contents
-+			 * of HWCFG1.  Need a copy of HWCFG1 in pcd structure?
-+			 * sprintf(";r
-+			 */
-+			dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
-+
-+			DWC_CIRCLEQ_INIT(&ep->queue);
-+		}
-+		hwcfg1 >>= 2;
-+	}
-+
-+	out_ep_cntr = 0;
-+	hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
-+	for (i = 1; out_ep_cntr < num_out_eps; i++) {
-+		if ((hwcfg1 & 0x1) == 0) {
-+			dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
-+			out_ep_cntr++;
-+			/**
-+			 * @todo NGS: Add direction to EP, based on contents
-+			 * of HWCFG1.  Need a copy of HWCFG1 in pcd structure?
-+			 * sprintf(";r
-+			 */
-+			dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
-+			DWC_CIRCLEQ_INIT(&ep->queue);
-+		}
-+		hwcfg1 >>= 2;
-+	}
-+
-+	pcd->ep0state = EP0_DISCONNECT;
-+	pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
-+	pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
-+}
-+
-+/**
-+ * This function is called when the SRP timer expires. The SRP should
-+ * complete within 6 seconds.
-+ */
-+static void srp_timeout(void *ptr)
-+{
-+	gotgctl_data_t gotgctl;
-+	dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
-+	volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
-+
-+	gotgctl.d32 = DWC_READ_REG32(addr);
-+
-+	core_if->srp_timer_started = 0;
-+
-+	if (core_if->adp_enable) {
-+		if (gotgctl.b.bsesvld == 0) {
-+			gpwrdn_data_t gpwrdn = {.d32 = 0 };
-+			DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
-+			/* Power off the core */
-+			if (core_if->power_down == 2) {
-+				gpwrdn.b.pwrdnswtch = 1;
-+				DWC_MODIFY_REG32(&core_if->
-+						 core_global_regs->gpwrdn,
-+						 gpwrdn.d32, 0);
-+			}
-+
-+			gpwrdn.d32 = 0;
-+			gpwrdn.b.pmuintsel = 1;
-+			gpwrdn.b.pmuactv = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
-+					 gpwrdn.d32);
-+			dwc_otg_adp_probe_start(core_if);
-+		} else {
-+			DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
-+			core_if->op_state = B_PERIPHERAL;
-+			dwc_otg_core_init(core_if);
-+			dwc_otg_enable_global_interrupts(core_if);
-+			cil_pcd_start(core_if);
-+		}
-+	}
-+
-+	if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
-+	    (core_if->core_params->i2c_enable)) {
-+		DWC_PRINTF("SRP Timeout\n");
-+
-+		if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
-+			if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
-+				core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
-+			}
-+
-+			/* Clear Session Request */
-+			gotgctl.d32 = 0;
-+			gotgctl.b.sesreq = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
-+					 gotgctl.d32, 0);
-+
-+			core_if->srp_success = 0;
-+		} else {
-+			__DWC_ERROR("Device not connected/responding\n");
-+			gotgctl.b.sesreq = 0;
-+			DWC_WRITE_REG32(addr, gotgctl.d32);
-+		}
-+	} else if (gotgctl.b.sesreq) {
-+		DWC_PRINTF("SRP Timeout\n");
-+
-+		__DWC_ERROR("Device not connected/responding\n");
-+		gotgctl.b.sesreq = 0;
-+		DWC_WRITE_REG32(addr, gotgctl.d32);
-+	} else {
-+		DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
-+	}
-+}
-+
-+/**
-+ * Tasklet
-+ *
-+ */
-+extern void start_next_request(dwc_otg_pcd_ep_t * ep);
-+
-+static void start_xfer_tasklet_func(void *data)
-+{
-+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+	int i;
-+	depctl_data_t diepctl;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
-+
-+	diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
-+
-+	if (pcd->ep0.queue_sof) {
-+		pcd->ep0.queue_sof = 0;
-+		start_next_request(&pcd->ep0);
-+		// break;
-+	}
-+
-+	for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
-+		depctl_data_t diepctl;
-+		diepctl.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
-+
-+		if (pcd->in_ep[i].queue_sof) {
-+			pcd->in_ep[i].queue_sof = 0;
-+			start_next_request(&pcd->in_ep[i]);
-+			// break;
-+		}
-+	}
-+
-+	return;
-+}
-+
-+/**
-+ * This function initialized the PCD portion of the driver.
-+ *
-+ */
-+dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_device_t *otg_dev)
-+{
-+	struct device *dev = &otg_dev->os_dep.platformdev->dev;
-+	dwc_otg_core_if_t *core_if = otg_dev->core_if;
-+	dwc_otg_pcd_t *pcd = NULL;
-+	dwc_otg_dev_if_t *dev_if;
-+	int i;
-+
-+	/*
-+	 * Allocate PCD structure
-+	 */
-+	pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
-+
-+	if (pcd == NULL) {
-+		return NULL;
-+	}
-+
-+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
-+	DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock);
-+#else
-+	pcd->lock = DWC_SPINLOCK_ALLOC();
-+#endif
-+        DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
-+                    pcd, core_if);//GRAYG
-+	if (!pcd->lock) {
-+		DWC_ERROR("Could not allocate lock for pcd");
-+		DWC_FREE(pcd);
-+		return NULL;
-+	}
-+	/* Set core_if's lock pointer to hcd->lock */
-+	core_if->lock = pcd->lock;
-+	pcd->core_if = core_if;
-+
-+	dev_if = core_if->dev_if;
-+	dev_if->isoc_ep = NULL;
-+
-+	if (core_if->hwcfg4.b.ded_fifo_en) {
-+		DWC_PRINTF("Dedicated Tx FIFOs mode\n");
-+	} else {
-+		DWC_PRINTF("Shared Tx FIFO mode\n");
-+	}
-+
-+	/*
-+	 * Initialized the Core for Device mode here if there is nod ADP support.
-+	 * Otherwise it will be done later in dwc_otg_adp_start routine.
-+	 */
-+	if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
-+		dwc_otg_core_dev_init(core_if);
-+	}
-+
-+	/*
-+	 * Register the PCD Callbacks.
-+	 */
-+	dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
-+
-+	/*
-+	 * Initialize the DMA buffer for SETUP packets
-+	 */
-+	if (GET_CORE_IF(pcd)->dma_enable) {
-+		pcd->setup_pkt =
-+		    DWC_DMA_ALLOC(dev, sizeof(*pcd->setup_pkt) * 5,
-+				  &pcd->setup_pkt_dma_handle);
-+		if (pcd->setup_pkt == NULL) {
-+			DWC_FREE(pcd);
-+			return NULL;
-+		}
-+
-+		pcd->status_buf =
-+		    DWC_DMA_ALLOC(dev, sizeof(uint16_t),
-+				  &pcd->status_buf_dma_handle);
-+		if (pcd->status_buf == NULL) {
-+			DWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5,
-+				     pcd->setup_pkt, pcd->setup_pkt_dma_handle);
-+			DWC_FREE(pcd);
-+			return NULL;
-+		}
-+
-+		if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+			dev_if->setup_desc_addr[0] =
-+			    dwc_otg_ep_alloc_desc_chain(dev,
-+				&dev_if->dma_setup_desc_addr[0], 1);
-+			dev_if->setup_desc_addr[1] =
-+			    dwc_otg_ep_alloc_desc_chain(dev,
-+				&dev_if->dma_setup_desc_addr[1], 1);
-+			dev_if->in_desc_addr =
-+			    dwc_otg_ep_alloc_desc_chain(dev,
-+				&dev_if->dma_in_desc_addr, 1);
-+			dev_if->out_desc_addr =
-+			    dwc_otg_ep_alloc_desc_chain(dev,
-+				&dev_if->dma_out_desc_addr, 1);
-+			pcd->data_terminated = 0;
-+
-+			if (dev_if->setup_desc_addr[0] == 0
-+			    || dev_if->setup_desc_addr[1] == 0
-+			    || dev_if->in_desc_addr == 0
-+			    || dev_if->out_desc_addr == 0) {
-+
-+				if (dev_if->out_desc_addr)
-+					dwc_otg_ep_free_desc_chain(dev,
-+					     dev_if->out_desc_addr,
-+					     dev_if->dma_out_desc_addr, 1);
-+				if (dev_if->in_desc_addr)
-+					dwc_otg_ep_free_desc_chain(dev,
-+					     dev_if->in_desc_addr,
-+					     dev_if->dma_in_desc_addr, 1);
-+				if (dev_if->setup_desc_addr[1])
-+					dwc_otg_ep_free_desc_chain(dev,
-+					     dev_if->setup_desc_addr[1],
-+					     dev_if->dma_setup_desc_addr[1], 1);
-+				if (dev_if->setup_desc_addr[0])
-+					dwc_otg_ep_free_desc_chain(dev,
-+					     dev_if->setup_desc_addr[0],
-+					     dev_if->dma_setup_desc_addr[0], 1);
-+
-+				DWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5,
-+					     pcd->setup_pkt,
-+					     pcd->setup_pkt_dma_handle);
-+				DWC_DMA_FREE(dev, sizeof(*pcd->status_buf),
-+					     pcd->status_buf,
-+					     pcd->status_buf_dma_handle);
-+
-+				DWC_FREE(pcd);
-+
-+				return NULL;
-+			}
-+		}
-+	} else {
-+		pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
-+		if (pcd->setup_pkt == NULL) {
-+			DWC_FREE(pcd);
-+			return NULL;
-+		}
-+
-+		pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
-+		if (pcd->status_buf == NULL) {
-+			DWC_FREE(pcd->setup_pkt);
-+			DWC_FREE(pcd);
-+			return NULL;
-+		}
-+	}
-+
-+	dwc_otg_pcd_reinit(pcd);
-+
-+	/* Allocate the cfi object for the PCD */
-+#ifdef DWC_UTE_CFI
-+	pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
-+	if (NULL == pcd->cfi)
-+		goto fail;
-+	if (init_cfi(pcd->cfi)) {
-+		CFI_INFO("%s: Failed to init the CFI object\n", __func__);
-+		goto fail;
-+	}
-+#endif
-+
-+	/* Initialize tasklets */
-+	pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
-+						 start_xfer_tasklet_func, pcd);
-+	pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
-+						do_test_mode, pcd);
-+
-+	/* Initialize SRP timer */
-+	core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
-+
-+	if (core_if->core_params->dev_out_nak) {
-+		/**
-+		* Initialize xfer timeout timer. Implemented for
-+		* 2.93a feature "Device DDMA OUT NAK Enhancement"
-+		*/
-+		for(i = 0; i < MAX_EPS_CHANNELS; i++) {
-+			pcd->core_if->ep_xfer_timer[i] =
-+				DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
-+				&pcd->core_if->ep_xfer_info[i]);
-+		}
-+	}
-+
-+	return pcd;
-+#ifdef DWC_UTE_CFI
-+fail:
-+#endif
-+	if (pcd->setup_pkt)
-+		DWC_FREE(pcd->setup_pkt);
-+	if (pcd->status_buf)
-+		DWC_FREE(pcd->status_buf);
-+#ifdef DWC_UTE_CFI
-+	if (pcd->cfi)
-+		DWC_FREE(pcd->cfi);
-+#endif
-+	if (pcd)
-+		DWC_FREE(pcd);
-+	return NULL;
-+
-+}
-+
-+/**
-+ * Remove PCD specific data
-+ */
-+void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+	struct device *dev = dwc_otg_pcd_to_dev(pcd);
-+	int i;
-+
-+	if (pcd->core_if->core_params->dev_out_nak) {
-+		for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+			DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
-+			pcd->core_if->ep_xfer_info[i].state = 0;
-+		}
-+	}
-+
-+	if (GET_CORE_IF(pcd)->dma_enable) {
-+		DWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
-+			     pcd->setup_pkt_dma_handle);
-+		DWC_DMA_FREE(dev, sizeof(uint16_t), pcd->status_buf,
-+			     pcd->status_buf_dma_handle);
-+		if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+			dwc_otg_ep_free_desc_chain(dev,
-+						   dev_if->setup_desc_addr[0],
-+						   dev_if->dma_setup_desc_addr
-+						   [0], 1);
-+			dwc_otg_ep_free_desc_chain(dev,
-+						   dev_if->setup_desc_addr[1],
-+						   dev_if->dma_setup_desc_addr
-+						   [1], 1);
-+			dwc_otg_ep_free_desc_chain(dev,
-+						   dev_if->in_desc_addr,
-+						   dev_if->dma_in_desc_addr, 1);
-+			dwc_otg_ep_free_desc_chain(dev,
-+						   dev_if->out_desc_addr,
-+						   dev_if->dma_out_desc_addr,
-+						   1);
-+		}
-+	} else {
-+		DWC_FREE(pcd->setup_pkt);
-+		DWC_FREE(pcd->status_buf);
-+	}
-+	DWC_SPINLOCK_FREE(pcd->lock);
-+	/* Set core_if's lock pointer to NULL */
-+	pcd->core_if->lock = NULL;
-+
-+	DWC_TASK_FREE(pcd->start_xfer_tasklet);
-+	DWC_TASK_FREE(pcd->test_mode_tasklet);
-+	if (pcd->core_if->core_params->dev_out_nak) {
-+		for (i = 0; i < MAX_EPS_CHANNELS; i++) {
-+			if (pcd->core_if->ep_xfer_timer[i]) {
-+					DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
-+			}
-+		}
-+	}
-+
-+/* Release the CFI object's dynamic memory */
-+#ifdef DWC_UTE_CFI
-+	if (pcd->cfi->ops.release) {
-+		pcd->cfi->ops.release(pcd->cfi);
-+	}
-+#endif
-+
-+	DWC_FREE(pcd);
-+}
-+
-+/**
-+ * Returns whether registered pcd is dual speed or not
-+ */
-+uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+	if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
-+	    ((core_if->hwcfg2.b.hs_phy_type == 2) &&
-+	     (core_if->hwcfg2.b.fs_phy_type == 1) &&
-+	     (core_if->core_params->ulpi_fs_ls))) {
-+		return 0;
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * Returns whether registered pcd is OTG capable or not
-+ */
-+uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	gusbcfg_data_t usbcfg = {.d32 = 0 };
-+
-+	usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
-+	if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
-+		return 0;
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * This function assigns periodic Tx FIFO to an periodic EP
-+ * in shared Tx FIFO mode
-+ */
-+static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+	uint32_t TxMsk = 1;
-+	int i;
-+
-+	for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
-+		if ((TxMsk & core_if->tx_msk) == 0) {
-+			core_if->tx_msk |= TxMsk;
-+			return i + 1;
-+		}
-+		TxMsk <<= 1;
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * This function assigns periodic Tx FIFO to an periodic EP
-+ * in shared Tx FIFO mode
-+ */
-+static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
-+{
-+	uint32_t PerTxMsk = 1;
-+	int i;
-+	for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
-+		if ((PerTxMsk & core_if->p_tx_msk) == 0) {
-+			core_if->p_tx_msk |= PerTxMsk;
-+			return i + 1;
-+		}
-+		PerTxMsk <<= 1;
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * This function releases periodic Tx FIFO
-+ * in shared Tx FIFO mode
-+ */
-+static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
-+				  uint32_t fifo_num)
-+{
-+	core_if->p_tx_msk =
-+	    (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
-+}
-+
-+/**
-+ * This function releases periodic Tx FIFO
-+ * in shared Tx FIFO mode
-+ */
-+static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
-+{
-+	core_if->tx_msk =
-+	    (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
-+}
-+
-+/**
-+ * This function is being called from gadget
-+ * to enable PCD endpoint.
-+ */
-+int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
-+			  const uint8_t * ep_desc, void *usb_ep)
-+{
-+	int num, dir;
-+	dwc_otg_pcd_ep_t *ep = NULL;
-+	const usb_endpoint_descriptor_t *desc;
-+	dwc_irqflags_t flags;
-+	fifosize_data_t dptxfsiz = {.d32 = 0 };
-+	gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+	gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
-+	int retval = 0;
-+	int i, epcount;
-+	struct device *dev = dwc_otg_pcd_to_dev(pcd);
-+
-+	desc = (const usb_endpoint_descriptor_t *)ep_desc;
-+
-+	if (!desc) {
-+		pcd->ep0.priv = usb_ep;
-+		ep = &pcd->ep0;
-+		retval = -DWC_E_INVALID;
-+		goto out;
-+	}
-+
-+	num = UE_GET_ADDR(desc->bEndpointAddress);
-+	dir = UE_GET_DIR(desc->bEndpointAddress);
-+
-+	if (!desc->wMaxPacketSize) {
-+		DWC_WARN("bad maxpacketsize\n");
-+		retval = -DWC_E_INVALID;
-+		goto out;
-+	}
-+
-+	if (dir == UE_DIR_IN) {
-+		epcount = pcd->core_if->dev_if->num_in_eps;
-+		for (i = 0; i < epcount; i++) {
-+			if (num == pcd->in_ep[i].dwc_ep.num) {
-+				ep = &pcd->in_ep[i];
-+				break;
-+			}
-+		}
-+	} else {
-+		epcount = pcd->core_if->dev_if->num_out_eps;
-+		for (i = 0; i < epcount; i++) {
-+			if (num == pcd->out_ep[i].dwc_ep.num) {
-+				ep = &pcd->out_ep[i];
-+				break;
-+			}
-+		}
-+	}
-+
-+	if (!ep) {
-+		DWC_WARN("bad address\n");
-+		retval = -DWC_E_INVALID;
-+		goto out;
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+	ep->desc = desc;
-+	ep->priv = usb_ep;
-+
-+	/*
-+	 * Activate the EP
-+	 */
-+	ep->stopped = 0;
-+
-+	ep->dwc_ep.is_in = (dir == UE_DIR_IN);
-+	ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
-+
-+	ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
-+
-+	if (ep->dwc_ep.is_in) {
-+		if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+			ep->dwc_ep.tx_fifo_num = 0;
-+
-+			if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
-+				/*
-+				 * if ISOC EP then assign a Periodic Tx FIFO.
-+				 */
-+				ep->dwc_ep.tx_fifo_num =
-+				    assign_perio_tx_fifo(GET_CORE_IF(pcd));
-+			}
-+		} else {
-+			/*
-+			 * if Dedicated FIFOs mode is on then assign a Tx FIFO.
-+			 */
-+			ep->dwc_ep.tx_fifo_num =
-+			    assign_tx_fifo(GET_CORE_IF(pcd));
-+		}
-+
-+		/* Calculating EP info controller base address */
-+		if (ep->dwc_ep.tx_fifo_num
-+		    && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+			gdfifocfg.d32 =
-+			    DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+					   core_global_regs->gdfifocfg);
-+			gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
-+			dptxfsiz.d32 =
-+			    (DWC_READ_REG32
-+			     (&GET_CORE_IF(pcd)->core_global_regs->
-+			      dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);
-+			gdfifocfg.b.epinfobase =
-+			    gdfifocfgbase.d32 + dptxfsiz.d32;
-+			if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
-+				DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
-+						core_global_regs->gdfifocfg,
-+						gdfifocfg.d32);
-+			}
-+		}
-+	}
-+	/* Set initial data PID. */
-+	if (ep->dwc_ep.type == UE_BULK) {
-+		ep->dwc_ep.data_pid_start = 0;
-+	}
-+
-+	/* Alloc DMA Descriptors */
-+	if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+#ifndef DWC_UTE_PER_IO
-+		if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
-+#endif
-+			ep->dwc_ep.desc_addr =
-+			    dwc_otg_ep_alloc_desc_chain(dev,
-+						&ep->dwc_ep.dma_desc_addr,
-+						MAX_DMA_DESC_CNT);
-+			if (!ep->dwc_ep.desc_addr) {
-+				DWC_WARN("%s, can't allocate DMA descriptor\n",
-+					 __func__);
-+				retval = -DWC_E_SHUTDOWN;
-+				DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+				goto out;
-+			}
-+#ifndef DWC_UTE_PER_IO
-+		}
-+#endif
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
-+		    (ep->dwc_ep.is_in ? "IN" : "OUT"),
-+		    ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
-+#ifdef DWC_UTE_PER_IO
-+	ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
-+#endif
-+	if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+		ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
-+		ep->dwc_ep.frame_num = 0xFFFFFFFF;
-+	}
-+
-+	dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+
-+#ifdef DWC_UTE_CFI
-+	if (pcd->cfi->ops.ep_enable) {
-+		pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
-+	}
-+#endif
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+out:
-+	return retval;
-+}
-+
-+/**
-+ * This function is being called from gadget
-+ * to disable PCD endpoint.
-+ */
-+int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_irqflags_t flags;
-+	dwc_otg_dev_dma_desc_t *desc_addr;
-+	dwc_dma_t dma_desc_addr;
-+	gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
-+	gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
-+	fifosize_data_t dptxfsiz = {.d32 = 0 };
-+	struct device *dev = dwc_otg_pcd_to_dev(pcd);
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+
-+	if (!ep || !ep->desc) {
-+		DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+	dwc_otg_request_nuke(ep);
-+
-+	dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+	if (pcd->core_if->core_params->dev_out_nak) {
-+		DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
-+		pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
-+	}
-+	ep->desc = NULL;
-+	ep->stopped = 1;
-+
-+	gdfifocfg.d32 =
-+	    DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
-+	gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
-+
-+	if (ep->dwc_ep.is_in) {
-+		if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+			/* Flush the Tx FIFO */
-+			dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),
-+					      ep->dwc_ep.tx_fifo_num);
-+		}
-+		release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
-+		release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
-+		if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
-+			/* Decreasing EPinfo Base Addr */
-+			dptxfsiz.d32 =
-+			    (DWC_READ_REG32
-+			     (&GET_CORE_IF(pcd)->
-+				core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
-+			gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
-+			if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
-+				DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
-+					gdfifocfg.d32);
-+			}
-+		}
-+	}
-+
-+	/* Free DMA Descriptors */
-+	if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+		if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
-+			desc_addr = ep->dwc_ep.desc_addr;
-+			dma_desc_addr = ep->dwc_ep.dma_desc_addr;
-+
-+			/* Cannot call dma_free_coherent() with IRQs disabled */
-+			DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+			dwc_otg_ep_free_desc_chain(dev, desc_addr, dma_desc_addr,
-+						   MAX_DMA_DESC_CNT);
-+
-+			goto out_unlocked;
-+		}
-+	}
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+out_unlocked:
-+	DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
-+		    ep->dwc_ep.is_in ? "IN" : "OUT");
-+	return 0;
-+
-+}
-+
-+/******************************************************************************/
-+#ifdef DWC_UTE_PER_IO
-+
-+/**
-+ * Free the request and its extended parts
-+ *
-+ */
-+void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
-+{
-+	DWC_FREE(req->ext_req.per_io_frame_descs);
-+	DWC_FREE(req);
-+}
-+
-+/**
-+ * Start the next request in the endpoint's queue.
-+ *
-+ */
-+int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
-+					dwc_otg_pcd_ep_t * ep)
-+{
-+	int i;
-+	dwc_otg_pcd_request_t *req = NULL;
-+	dwc_ep_t *dwcep = NULL;
-+	struct dwc_iso_xreq_port *ereq = NULL;
-+	struct dwc_iso_pkt_desc_port *ddesc_iso;
-+	uint16_t nat;
-+	depctl_data_t diepctl;
-+
-+	dwcep = &ep->dwc_ep;
-+
-+	if (dwcep->xiso_active_xfers > 0) {
-+#if 0	//Disable this to decrease s/w overhead that is crucial for Isoc transfers
-+		DWC_WARN("There are currently active transfers for EP%d \
-+				(active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers,
-+				dwcep->xiso_queued_xfers);
-+#endif
-+		return 0;
-+	}
-+
-+	nat = UGETW(ep->desc->wMaxPacketSize);
-+	nat = (nat >> 11) & 0x03;
-+
-+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+		ereq = &req->ext_req;
-+		ep->stopped = 0;
-+
-+		/* Get the frame number */
-+		dwcep->xiso_frame_num =
-+		    dwc_otg_get_frame_number(GET_CORE_IF(pcd));
-+		DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
-+
-+		ddesc_iso = ereq->per_io_frame_descs;
-+
-+		if (dwcep->is_in) {
-+			/* Setup DMA Descriptor chain for IN Isoc request */
-+			for (i = 0; i < ereq->pio_pkt_count; i++) {
-+				//if ((i % (nat + 1)) == 0)
-+				if ( i > 0 )
-+					dwcep->xiso_frame_num =
-+					    (dwcep->xiso_bInterval +
-+										dwcep->xiso_frame_num) & 0x3FFF;
-+				dwcep->desc_addr[i].buf =
-+				    req->dma + ddesc_iso[i].offset;
-+				dwcep->desc_addr[i].status.b_iso_in.txbytes =
-+				    ddesc_iso[i].length;
-+				dwcep->desc_addr[i].status.b_iso_in.framenum =
-+				    dwcep->xiso_frame_num;
-+				dwcep->desc_addr[i].status.b_iso_in.bs =
-+				    BS_HOST_READY;
-+				dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
-+				dwcep->desc_addr[i].status.b_iso_in.sp =
-+				    (ddesc_iso[i].length %
-+				     dwcep->maxpacket) ? 1 : 0;
-+				dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
-+				dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
-+				dwcep->desc_addr[i].status.b_iso_in.l = 0;
-+
-+				/* Process the last descriptor */
-+				if (i == ereq->pio_pkt_count - 1) {
-+					dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
-+					dwcep->desc_addr[i].status.b_iso_in.l = 1;
-+				}
-+			}
-+
-+			/* Setup and start the transfer for this endpoint */
-+			dwcep->xiso_active_xfers++;
-+			DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
-+					in_ep_regs[dwcep->num]->diepdma,
-+					dwcep->dma_desc_addr);
-+			diepctl.d32 = 0;
-+			diepctl.b.epena = 1;
-+			diepctl.b.cnak = 1;
-+			DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
-+					 in_ep_regs[dwcep->num]->diepctl, 0,
-+					 diepctl.d32);
-+		} else {
-+			/* Setup DMA Descriptor chain for OUT Isoc request */
-+			for (i = 0; i < ereq->pio_pkt_count; i++) {
-+				//if ((i % (nat + 1)) == 0)
-+				dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
-+										dwcep->xiso_frame_num) & 0x3FFF;
-+				dwcep->desc_addr[i].buf =
-+				    req->dma + ddesc_iso[i].offset;
-+				dwcep->desc_addr[i].status.b_iso_out.rxbytes =
-+				    ddesc_iso[i].length;
-+				dwcep->desc_addr[i].status.b_iso_out.framenum =
-+				    dwcep->xiso_frame_num;
-+				dwcep->desc_addr[i].status.b_iso_out.bs =
-+				    BS_HOST_READY;
-+				dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
-+				dwcep->desc_addr[i].status.b_iso_out.sp =
-+				    (ddesc_iso[i].length %
-+				     dwcep->maxpacket) ? 1 : 0;
-+				dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
-+				dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
-+				dwcep->desc_addr[i].status.b_iso_out.l = 0;
-+
-+				/* Process the last descriptor */
-+				if (i == ereq->pio_pkt_count - 1) {
-+					dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
-+					dwcep->desc_addr[i].status.b_iso_out.l = 1;
-+				}
-+			}
-+
-+			/* Setup and start the transfer for this endpoint */
-+			dwcep->xiso_active_xfers++;
-+			DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
-+					dev_if->out_ep_regs[dwcep->num]->
-+					doepdma, dwcep->dma_desc_addr);
-+			diepctl.d32 = 0;
-+			diepctl.b.epena = 1;
-+			diepctl.b.cnak = 1;
-+			DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+					 dev_if->out_ep_regs[dwcep->num]->
-+					 doepctl, 0, diepctl.d32);
-+		}
-+
-+	} else {
-+		ep->stopped = 1;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ *	- Remove the request from the queue
-+ */
-+void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
-+{
-+	dwc_otg_pcd_request_t *req = NULL;
-+	struct dwc_iso_xreq_port *ereq = NULL;
-+	struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
-+	dwc_ep_t *dwcep = NULL;
-+	int i;
-+
-+	//DWC_DEBUG();
-+	dwcep = &ep->dwc_ep;
-+
-+	/* Get the first pending request from the queue */
-+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+		if (!req) {
-+			DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+			return;
-+		}
-+		dwcep->xiso_active_xfers--;
-+		dwcep->xiso_queued_xfers--;
-+		/* Remove this request from the queue */
-+		DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
-+	} else {
-+		DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+		return;
-+	}
-+
-+	ep->stopped = 1;
-+	ereq = &req->ext_req;
-+	ddesc_iso = ereq->per_io_frame_descs;
-+
-+	if (dwcep->xiso_active_xfers < 0) {
-+		DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
-+			 dwcep->xiso_active_xfers);
-+	}
-+
-+	/* Fill the Isoc descs of portable extended req from dma descriptors */
-+	for (i = 0; i < ereq->pio_pkt_count; i++) {
-+		if (dwcep->is_in) {	/* IN endpoints */
-+			ddesc_iso[i].actual_length = ddesc_iso[i].length -
-+			    dwcep->desc_addr[i].status.b_iso_in.txbytes;
-+			ddesc_iso[i].status =
-+			    dwcep->desc_addr[i].status.b_iso_in.txsts;
-+		} else {	/* OUT endpoints */
-+			ddesc_iso[i].actual_length = ddesc_iso[i].length -
-+			    dwcep->desc_addr[i].status.b_iso_out.rxbytes;
-+			ddesc_iso[i].status =
-+			    dwcep->desc_addr[i].status.b_iso_out.rxsts;
-+		}
-+	}
-+
-+	DWC_SPINUNLOCK(ep->pcd->lock);
-+
-+	/* Call the completion function in the non-portable logic */
-+	ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
-+				      &req->ext_req);
-+
-+	DWC_SPINLOCK(ep->pcd->lock);
-+
-+	/* Free the request - specific freeing needed for extended request object */
-+	dwc_pcd_xiso_ereq_free(ep, req);
-+
-+	/* Start the next request */
-+	dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
-+
-+	return;
-+}
-+
-+/**
-+ * Create and initialize the Isoc pkt descriptors of the extended request.
-+ *
-+ */
-+static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
-+					     void *ereq_nonport,
-+					     int atomic_alloc)
-+{
-+	struct dwc_iso_xreq_port *ereq = NULL;
-+	struct dwc_iso_xreq_port *req_mapped = NULL;
-+	struct dwc_iso_pkt_desc_port *ipds = NULL;	/* To be created in this function */
-+	uint32_t pkt_count;
-+	int i;
-+
-+	ereq = &req->ext_req;
-+	req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
-+	pkt_count = req_mapped->pio_pkt_count;
-+
-+	/* Create the isoc descs */
-+	if (atomic_alloc) {
-+		ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
-+	} else {
-+		ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
-+	}
-+
-+	if (!ipds) {
-+		DWC_ERROR("Failed to allocate isoc descriptors");
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	/* Initialize the extended request fields */
-+	ereq->per_io_frame_descs = ipds;
-+	ereq->error_count = 0;
-+	ereq->pio_alloc_pkt_count = pkt_count;
-+	ereq->pio_pkt_count = pkt_count;
-+	ereq->tr_sub_flags = req_mapped->tr_sub_flags;
-+
-+	/* Init the Isoc descriptors */
-+	for (i = 0; i < pkt_count; i++) {
-+		ipds[i].length = req_mapped->per_io_frame_descs[i].length;
-+		ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
-+		ipds[i].status = req_mapped->per_io_frame_descs[i].status;	/* 0 */
-+		ipds[i].actual_length =
-+		    req_mapped->per_io_frame_descs[i].actual_length;
-+	}
-+
-+	return 0;
-+}
-+
-+static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
-+{
-+	struct dwc_iso_pkt_desc_port *xfd = NULL;
-+	int i;
-+
-+	DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
-+	DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
-+	DWC_DEBUG("error_count=%d", ereq->error_count);
-+	DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
-+	DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
-+	DWC_DEBUG("res=%d", ereq->res);
-+
-+	for (i = 0; i < ereq->pio_pkt_count; i++) {
-+		xfd = &ereq->per_io_frame_descs[0];
-+		DWC_DEBUG("FD #%d", i);
-+
-+		DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
-+		DWC_DEBUG("xfd->length=%d", xfd->length);
-+		DWC_DEBUG("xfd->offset=%d", xfd->offset);
-+		DWC_DEBUG("xfd->status=%d", xfd->status);
-+	}
-+}
-+
-+/**
-+ *
-+ */
-+int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+			      uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
-+			      int zero, void *req_handle, int atomic_alloc,
-+			      void *ereq_nonport)
-+{
-+	dwc_otg_pcd_request_t *req = NULL;
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_irqflags_t flags;
-+	int res;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+	if (!ep) {
-+		DWC_WARN("bad ep\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	/* We support this extension only for DDMA mode */
-+	if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
-+		if (!GET_CORE_IF(pcd)->dma_desc_enable)
-+			return -DWC_E_INVALID;
-+
-+	/* Create a dwc_otg_pcd_request_t object */
-+	if (atomic_alloc) {
-+		req = DWC_ALLOC_ATOMIC(sizeof(*req));
-+	} else {
-+		req = DWC_ALLOC(sizeof(*req));
-+	}
-+
-+	if (!req) {
-+		return -DWC_E_NO_MEMORY;
-+	}
-+
-+	/* Create the Isoc descs for this request which shall be the exact match
-+	 * of the structure sent to us from the non-portable logic */
-+	res =
-+	    dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
-+	if (res) {
-+		DWC_WARN("Failed to init the Isoc descriptors");
-+		DWC_FREE(req);
-+		return res;
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+	DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
-+	req->buf = buf;
-+	req->dma = dma_buf;
-+	req->length = buflen;
-+	req->sent_zlp = zero;
-+	req->priv = req_handle;
-+
-+	//DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+	ep->dwc_ep.dma_addr = dma_buf;
-+	ep->dwc_ep.start_xfer_buff = buf;
-+	ep->dwc_ep.xfer_buff = buf;
-+	ep->dwc_ep.xfer_len = 0;
-+	ep->dwc_ep.xfer_count = 0;
-+	ep->dwc_ep.sent_zlp = 0;
-+	ep->dwc_ep.total_len = buflen;
-+
-+	/* Add this request to the tail */
-+	DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+	ep->dwc_ep.xiso_queued_xfers++;
-+
-+//DWC_DEBUG("CP_0");
-+//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
-+//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
-+//prn_ext_request(&req->ext_req);
-+
-+	//DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+	/* If the req->status == ASAP  then check if there is any active transfer
-+	 * for this endpoint. If no active transfers, then get the first entry
-+	 * from the queue and start that transfer
-+	 */
-+	if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
-+		res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
-+		if (res) {
-+			DWC_WARN("Failed to start the next Isoc transfer");
-+			DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+			DWC_FREE(req);
-+			return res;
-+		}
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+	return 0;
-+}
-+
-+#endif
-+/* END ifdef DWC_UTE_PER_IO ***************************************************/
-+int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+			 uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
-+			 int zero, void *req_handle, int atomic_alloc)
-+{
-+	struct device *dev = dwc_otg_pcd_to_dev(pcd);
-+	dwc_irqflags_t flags;
-+	dwc_otg_pcd_request_t *req;
-+	dwc_otg_pcd_ep_t *ep;
-+	uint32_t max_transfer;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+	if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
-+		DWC_WARN("bad ep\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (atomic_alloc) {
-+		req = DWC_ALLOC_ATOMIC(sizeof(*req));
-+	} else {
-+		req = DWC_ALLOC(sizeof(*req));
-+	}
-+
-+	if (!req) {
-+		return -DWC_E_NO_MEMORY;
-+	}
-+	DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
-+	if (!GET_CORE_IF(pcd)->core_params->opt) {
-+		if (ep->dwc_ep.num != 0) {
-+			DWC_ERROR("queue req %p, len %d buf %p\n",
-+				  req_handle, buflen, buf);
-+		}
-+	}
-+
-+	req->buf = buf;
-+	req->dma = dma_buf;
-+	req->length = buflen;
-+	req->sent_zlp = zero;
-+	req->priv = req_handle;
-+	req->dw_align_buf = NULL;
-+	if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
-+			&& !GET_CORE_IF(pcd)->dma_desc_enable)
-+		req->dw_align_buf = DWC_DMA_ALLOC(dev, buflen,
-+				 &req->dw_align_buf_dma);
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+	/*
-+	 * After adding request to the queue for IN ISOC wait for In Token Received
-+	 * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token
-+	 * Received when EP is disabled interrupt to obtain starting microframe
-+	 * (odd/even) start transfer
-+	 */
-+	if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+		if (req != 0) {
-+			depctl_data_t depctl = {.d32 =
-+				    DWC_READ_REG32(&pcd->core_if->dev_if->
-+						   in_ep_regs[ep->dwc_ep.num]->
-+						   diepctl) };
-+			++pcd->request_pending;
-+
-+			DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+			if (ep->dwc_ep.is_in) {
-+				depctl.b.cnak = 1;
-+				DWC_WRITE_REG32(&pcd->core_if->dev_if->
-+						in_ep_regs[ep->dwc_ep.num]->
-+						diepctl, depctl.d32);
-+			}
-+
-+			DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+		}
-+		return 0;
-+	}
-+
-+	/*
-+	 * For EP0 IN without premature status, zlp is required?
-+	 */
-+	if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
-+		DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
-+		//_req->zero = 1;
-+	}
-+
-+	/* Start the transfer */
-+	if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
-+		/* EP0 Transfer? */
-+		if (ep->dwc_ep.num == 0) {
-+			switch (pcd->ep0state) {
-+			case EP0_IN_DATA_PHASE:
-+				DWC_DEBUGPL(DBG_PCD,
-+					    "%s ep0: EP0_IN_DATA_PHASE\n",
-+					    __func__);
-+				break;
-+
-+			case EP0_OUT_DATA_PHASE:
-+				DWC_DEBUGPL(DBG_PCD,
-+					    "%s ep0: EP0_OUT_DATA_PHASE\n",
-+					    __func__);
-+				if (pcd->request_config) {
-+					/* Complete STATUS PHASE */
-+					ep->dwc_ep.is_in = 1;
-+					pcd->ep0state = EP0_IN_STATUS_PHASE;
-+				}
-+				break;
-+
-+			case EP0_IN_STATUS_PHASE:
-+				DWC_DEBUGPL(DBG_PCD,
-+					    "%s ep0: EP0_IN_STATUS_PHASE\n",
-+					    __func__);
-+				break;
-+
-+			default:
-+				DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
-+					    pcd->ep0state);
-+				DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+				return -DWC_E_SHUTDOWN;
-+			}
-+
-+			ep->dwc_ep.dma_addr = dma_buf;
-+			ep->dwc_ep.start_xfer_buff = buf;
-+			ep->dwc_ep.xfer_buff = buf;
-+			ep->dwc_ep.xfer_len = buflen;
-+			ep->dwc_ep.xfer_count = 0;
-+			ep->dwc_ep.sent_zlp = 0;
-+			ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
-+
-+			if (zero) {
-+				if ((ep->dwc_ep.xfer_len %
-+				     ep->dwc_ep.maxpacket == 0)
-+				    && (ep->dwc_ep.xfer_len != 0)) {
-+					ep->dwc_ep.sent_zlp = 1;
-+				}
-+
-+			}
-+
-+			dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
-+						   &ep->dwc_ep);
-+		}		// non-ep0 endpoints
-+		else {
-+#ifdef DWC_UTE_CFI
-+			if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+				/* store the request length */
-+				ep->dwc_ep.cfi_req_len = buflen;
-+				pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
-+								ep, req);
-+			} else {
-+#endif
-+				max_transfer =
-+				    GET_CORE_IF(ep->pcd)->core_params->
-+				    max_transfer_size;
-+
-+				/* Setup and start the Transfer */
-+				if (req->dw_align_buf){
-+					if (ep->dwc_ep.is_in)
-+						dwc_memcpy(req->dw_align_buf,
-+							   buf, buflen);
-+					ep->dwc_ep.dma_addr =
-+					    req->dw_align_buf_dma;
-+					ep->dwc_ep.start_xfer_buff =
-+					    req->dw_align_buf;
-+					ep->dwc_ep.xfer_buff =
-+					    req->dw_align_buf;
-+				} else {
-+					ep->dwc_ep.dma_addr = dma_buf;
-+					ep->dwc_ep.start_xfer_buff = buf;
-+                                        ep->dwc_ep.xfer_buff = buf;
-+				}
-+				ep->dwc_ep.xfer_len = 0;
-+				ep->dwc_ep.xfer_count = 0;
-+				ep->dwc_ep.sent_zlp = 0;
-+				ep->dwc_ep.total_len = buflen;
-+
-+				ep->dwc_ep.maxxfer = max_transfer;
-+				if (GET_CORE_IF(pcd)->dma_desc_enable) {
-+					uint32_t out_max_xfer =
-+					    DDMA_MAX_TRANSFER_SIZE -
-+					    (DDMA_MAX_TRANSFER_SIZE % 4);
-+					if (ep->dwc_ep.is_in) {
-+						if (ep->dwc_ep.maxxfer >
-+						    DDMA_MAX_TRANSFER_SIZE) {
-+							ep->dwc_ep.maxxfer =
-+							    DDMA_MAX_TRANSFER_SIZE;
-+						}
-+					} else {
-+						if (ep->dwc_ep.maxxfer >
-+						    out_max_xfer) {
-+							ep->dwc_ep.maxxfer =
-+							    out_max_xfer;
-+						}
-+					}
-+				}
-+				if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
-+					ep->dwc_ep.maxxfer -=
-+					    (ep->dwc_ep.maxxfer %
-+					     ep->dwc_ep.maxpacket);
-+				}
-+
-+				if (zero) {
-+					if ((ep->dwc_ep.total_len %
-+					     ep->dwc_ep.maxpacket == 0)
-+					    && (ep->dwc_ep.total_len != 0)) {
-+						ep->dwc_ep.sent_zlp = 1;
-+					}
-+				}
-+#ifdef DWC_UTE_CFI
-+			}
-+#endif
-+			dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
-+						  &ep->dwc_ep);
-+		}
-+	}
-+
-+	if (req != 0) {
-+		++pcd->request_pending;
-+		DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
-+		if (ep->dwc_ep.is_in && ep->stopped
-+		    && !(GET_CORE_IF(pcd)->dma_enable)) {
-+			/** @todo NGS Create a function for this. */
-+			diepmsk_data_t diepmsk = {.d32 = 0 };
-+			diepmsk.b.intktxfemp = 1;
-+			if (GET_CORE_IF(pcd)->multiproc_int_enable) {
-+				DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+						 dev_if->dev_global_regs->diepeachintmsk
-+						 [ep->dwc_ep.num], 0,
-+						 diepmsk.d32);
-+			} else {
-+				DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
-+						 dev_if->dev_global_regs->
-+						 diepmsk, 0, diepmsk.d32);
-+			}
-+
-+		}
-+	}
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+	return 0;
-+}
-+
-+int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+			   void *req_handle)
-+{
-+	dwc_irqflags_t flags;
-+	dwc_otg_pcd_request_t *req;
-+	dwc_otg_pcd_ep_t *ep;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+	if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
-+		DWC_WARN("bad argument\n");
-+		return -DWC_E_INVALID;
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+
-+	/* make sure it's actually queued on this endpoint */
-+	DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
-+		if (req->priv == (void *)req_handle) {
-+			break;
-+		}
-+	}
-+
-+	if (req->priv != (void *)req_handle) {
-+		DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
-+		dwc_otg_request_done(ep, req, -DWC_E_RESTART);
-+	} else {
-+		req = NULL;
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+	return req ? 0 : -DWC_E_SHUTDOWN;
-+
-+}
-+
-+/**
-+ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
-+ *
-+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
-+ * requests. If the gadget driver clears the halt status, it will
-+ * automatically unwedge the endpoint.
-+ *
-+ * Returns zero on success, else negative DWC error code.
-+ */
-+int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_irqflags_t flags;
-+	int retval = 0;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+
-+	if ((!ep->desc && ep != &pcd->ep0) ||
-+	    (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
-+		DWC_WARN("%s, bad ep\n", __func__);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
-+			 ep->dwc_ep.is_in ? "IN" : "OUT");
-+		retval = -DWC_E_AGAIN;
-+	} else {
-+                /* This code needs to be reviewed */
-+		if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
-+			dtxfsts_data_t txstatus;
-+			fifosize_data_t txfifosize;
-+
-+			txfifosize.d32 =
-+			    DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+					   core_global_regs->dtxfsiz[ep->dwc_ep.
-+								     tx_fifo_num]);
-+			txstatus.d32 =
-+			    DWC_READ_REG32(&GET_CORE_IF(pcd)->
-+					   dev_if->in_ep_regs[ep->dwc_ep.num]->
-+					   dtxfsts);
-+
-+			if (txstatus.b.txfspcavail < txfifosize.b.depth) {
-+				DWC_WARN("%s() Data In Tx Fifo\n", __func__);
-+				retval = -DWC_E_AGAIN;
-+			} else {
-+				if (ep->dwc_ep.num == 0) {
-+					pcd->ep0state = EP0_STALL;
-+				}
-+
-+				ep->stopped = 1;
-+				dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
-+						     &ep->dwc_ep);
-+			}
-+		} else {
-+			if (ep->dwc_ep.num == 0) {
-+				pcd->ep0state = EP0_STALL;
-+			}
-+
-+			ep->stopped = 1;
-+			dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+		}
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+	return retval;
-+}
-+
-+int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_irqflags_t flags;
-+	int retval = 0;
-+
-+	ep = get_ep_from_handle(pcd, ep_handle);
-+
-+	if (!ep || (!ep->desc && ep != &pcd->ep0) ||
-+	    (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
-+		DWC_WARN("%s, bad ep\n", __func__);
-+		return -DWC_E_INVALID;
-+	}
-+
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
-+			 ep->dwc_ep.is_in ? "IN" : "OUT");
-+		retval = -DWC_E_AGAIN;
-+	} else if (value == 0) {
-+		dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+	} else if (value == 1) {
-+		if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
-+			dtxfsts_data_t txstatus;
-+			fifosize_data_t txfifosize;
-+
-+			txfifosize.d32 =
-+			    DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
-+					   dtxfsiz[ep->dwc_ep.tx_fifo_num]);
-+			txstatus.d32 =
-+			    DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+					   in_ep_regs[ep->dwc_ep.num]->dtxfsts);
-+
-+			if (txstatus.b.txfspcavail < txfifosize.b.depth) {
-+				DWC_WARN("%s() Data In Tx Fifo\n", __func__);
-+				retval = -DWC_E_AGAIN;
-+			} else {
-+				if (ep->dwc_ep.num == 0) {
-+					pcd->ep0state = EP0_STALL;
-+				}
-+
-+				ep->stopped = 1;
-+				dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
-+						     &ep->dwc_ep);
-+			}
-+		} else {
-+			if (ep->dwc_ep.num == 0) {
-+				pcd->ep0state = EP0_STALL;
-+			}
-+
-+			ep->stopped = 1;
-+			dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+		}
-+	} else if (value == 2) {
-+		ep->dwc_ep.stall_clear_flag = 0;
-+	} else if (value == 3) {
-+		ep->dwc_ep.stall_clear_flag = 1;
-+	}
-+
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function initiates remote wakeup of the host from suspend state.
-+ */
-+void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
-+{
-+	dctl_data_t dctl = { 0 };
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dsts_data_t dsts;
-+
-+	dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+	if (!dsts.b.suspsts) {
-+		DWC_WARN("Remote wakeup while is not in suspend state\n");
-+	}
-+	/* Check if DEVICE_REMOTE_WAKEUP feature enabled */
-+	if (pcd->remote_wakeup_enable) {
-+		if (set) {
-+
-+			if (core_if->adp_enable) {
-+				gpwrdn_data_t gpwrdn;
-+
-+				dwc_otg_adp_probe_stop(core_if);
-+
-+				/* Mask SRP detected interrupt from Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.srp_det_msk = 1;
-+				DWC_MODIFY_REG32(&core_if->
-+						 core_global_regs->gpwrdn,
-+						 gpwrdn.d32, 0);
-+
-+				/* Disable Power Down Logic */
-+				gpwrdn.d32 = 0;
-+				gpwrdn.b.pmuactv = 1;
-+				DWC_MODIFY_REG32(&core_if->
-+						 core_global_regs->gpwrdn,
-+						 gpwrdn.d32, 0);
-+
-+				/*
-+				 * Initialize the Core for Device mode.
-+				 */
-+				core_if->op_state = B_PERIPHERAL;
-+				dwc_otg_core_init(core_if);
-+				dwc_otg_enable_global_interrupts(core_if);
-+				cil_pcd_start(core_if);
-+
-+				dwc_otg_initiate_srp(core_if);
-+			}
-+
-+			dctl.b.rmtwkupsig = 1;
-+			DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+					 dctl, 0, dctl.d32);
-+			DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
-+
-+			dwc_mdelay(2);
-+			DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+					 dctl, dctl.d32, 0);
-+			DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
-+		}
-+	} else {
-+		DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
-+	}
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+/**
-+ * This function initiates remote wakeup of the host from L1 sleep state.
-+ */
-+void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
-+{
-+	glpmcfg_data_t lpmcfg;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+
-+	/* Check if we are in L1 state */
-+	if (!lpmcfg.b.prt_sleep_sts) {
-+		DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
-+		return;
-+	}
-+
-+	/* Check if host allows remote wakeup */
-+	if (!lpmcfg.b.rem_wkup_en) {
-+		DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
-+		return;
-+	}
-+
-+	/* Check if Resume OK */
-+	if (!lpmcfg.b.sleep_state_resumeok) {
-+		DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
-+		return;
-+	}
-+
-+	lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
-+	lpmcfg.b.en_utmi_sleep = 0;
-+	lpmcfg.b.hird_thres &= (~(1 << 4));
-+	DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
-+
-+	if (set) {
-+		dctl_data_t dctl = {.d32 = 0 };
-+		dctl.b.rmtwkupsig = 1;
-+		/* Set RmtWkUpSig bit to start remote wakup signaling.
-+		 * Hardware will automatically clear this bit.
-+		 */
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+				 0, dctl.d32);
-+		DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
-+	}
-+
-+}
-+#endif
-+
-+/**
-+ * Performs remote wakeup.
-+ */
-+void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_irqflags_t flags;
-+	if (dwc_otg_is_device_mode(core_if)) {
-+		DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+		if (core_if->lx_state == DWC_OTG_L1) {
-+			dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
-+		} else {
-+#endif
-+			dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+		}
-+#endif
-+		DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+	}
-+	return;
-+}
-+
-+void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dctl_data_t dctl = { 0 };
-+
-+	if (dwc_otg_is_device_mode(core_if)) {
-+		dctl.b.sftdiscon = 1;
-+		DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
-+		dwc_udelay(no_of_usecs);
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
-+
-+	} else{
-+		DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
-+	}
-+	return;
-+
-+}
-+
-+int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
-+{
-+	dsts_data_t dsts;
-+	gotgctl_data_t gotgctl;
-+
-+	/*
-+	 * This function starts the Protocol if no session is in progress. If
-+	 * a session is already in progress, but the device is suspended,
-+	 * remote wakeup signaling is started.
-+	 */
-+
-+	/* Check if valid session */
-+	gotgctl.d32 =
-+	    DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
-+	if (gotgctl.b.bsesvld) {
-+		/* Check if suspend state */
-+		dsts.d32 =
-+		    DWC_READ_REG32(&
-+				   (GET_CORE_IF(pcd)->dev_if->
-+				    dev_global_regs->dsts));
-+		if (dsts.b.suspsts) {
-+			dwc_otg_pcd_remote_wakeup(pcd, 1);
-+		}
-+	} else {
-+		dwc_otg_pcd_initiate_srp(pcd);
-+	}
-+
-+	return 0;
-+
-+}
-+
-+/**
-+ * Start the SRP timer to detect when the SRP does not complete within
-+ * 6 seconds.
-+ *
-+ * @param pcd the pcd structure.
-+ */
-+void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_irqflags_t flags;
-+	DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
-+	dwc_otg_initiate_srp(GET_CORE_IF(pcd));
-+	DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
-+}
-+
-+int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
-+{
-+	return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
-+}
-+
-+int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
-+{
-+	return GET_CORE_IF(pcd)->core_params->lpm_enable;
-+}
-+
-+uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
-+{
-+	return pcd->b_hnp_enable;
-+}
-+
-+uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
-+{
-+	return pcd->a_hnp_support;
-+}
-+
-+uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
-+{
-+	return pcd->a_alt_hnp_support;
-+}
-+
-+int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
-+{
-+	return pcd->remote_wakeup_enable;
-+}
-+
-+#endif /* DWC_HOST_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
-@@ -0,0 +1,273 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
-+ * $Revision: #48 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+#if !defined(__DWC_PCD_H__)
-+#define __DWC_PCD_H__
-+
-+#include "dwc_otg_os_dep.h"
-+#include "usb.h"
-+#include "dwc_otg_cil.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_driver.h"
-+
-+struct cfiobject;
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the structures, constants, and interfaces for
-+ * the Perpherial Contoller Driver (PCD).
-+ *
-+ * The Peripheral Controller Driver (PCD) for Linux will implement the
-+ * Gadget API, so that the existing Gadget drivers can be used. For
-+ * the Mass Storage Function driver the File-backed USB Storage Gadget
-+ * (FBS) driver will be used.  The FBS driver supports the
-+ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
-+ * transports.
-+ *
-+ */
-+
-+/** Invalid DMA Address */
-+#define DWC_DMA_ADDR_INVALID	(~(dwc_dma_t)0)
-+
-+/** Max Transfer size for any EP */
-+#define DDMA_MAX_TRANSFER_SIZE 65535
-+
-+/**
-+ * Get the pointer to the core_if from the pcd pointer.
-+ */
-+#define GET_CORE_IF( _pcd ) (_pcd->core_if)
-+
-+/**
-+ * States of EP0.
-+ */
-+typedef enum ep0_state {
-+	EP0_DISCONNECT,		/* no host */
-+	EP0_IDLE,
-+	EP0_IN_DATA_PHASE,
-+	EP0_OUT_DATA_PHASE,
-+	EP0_IN_STATUS_PHASE,
-+	EP0_OUT_STATUS_PHASE,
-+	EP0_STALL,
-+} ep0state_e;
-+
-+/** Fordward declaration.*/
-+struct dwc_otg_pcd;
-+
-+/** DWC_otg iso request structure.
-+ *
-+ */
-+typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
-+
-+#ifdef DWC_UTE_PER_IO
-+
-+/**
-+ * This shall be the exact analogy of the same type structure defined in the
-+ * usb_gadget.h. Each descriptor contains
-+ */
-+struct dwc_iso_pkt_desc_port {
-+	uint32_t offset;
-+	uint32_t length;	/* expected length */
-+	uint32_t actual_length;
-+	uint32_t status;
-+};
-+
-+struct dwc_iso_xreq_port {
-+	/** transfer/submission flag */
-+	uint32_t tr_sub_flags;
-+	/** Start the request ASAP */
-+#define DWC_EREQ_TF_ASAP		0x00000002
-+	/** Just enqueue the request w/o initiating a transfer */
-+#define DWC_EREQ_TF_ENQUEUE		0x00000004
-+
-+	/**
-+	* count of ISO packets attached to this request - shall
-+	* not exceed the pio_alloc_pkt_count
-+	*/
-+	uint32_t pio_pkt_count;
-+	/** count of ISO packets allocated for this request */
-+	uint32_t pio_alloc_pkt_count;
-+	/** number of ISO packet errors */
-+	uint32_t error_count;
-+	/** reserved for future extension */
-+	uint32_t res;
-+	/** Will be allocated and freed in the UTE gadget and based on the CFC value */
-+	struct dwc_iso_pkt_desc_port *per_io_frame_descs;
-+};
-+#endif
-+/** DWC_otg request structure.
-+ * This structure is a list of requests.
-+ */
-+typedef struct dwc_otg_pcd_request {
-+	void *priv;
-+	void *buf;
-+	dwc_dma_t dma;
-+	uint32_t length;
-+	uint32_t actual;
-+	unsigned sent_zlp:1;
-+    /**
-+     * Used instead of original buffer if
-+     * it(physical address) is not dword-aligned.
-+     **/
-+     uint8_t *dw_align_buf;
-+     dwc_dma_t dw_align_buf_dma;
-+
-+	 DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
-+#ifdef DWC_UTE_PER_IO
-+	struct dwc_iso_xreq_port ext_req;
-+	//void *priv_ereq_nport; /*  */
-+#endif
-+} dwc_otg_pcd_request_t;
-+
-+DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
-+
-+/**	  PCD EP structure.
-+ * This structure describes an EP, there is an array of EPs in the PCD
-+ * structure.
-+ */
-+typedef struct dwc_otg_pcd_ep {
-+	/** USB EP Descriptor */
-+	const usb_endpoint_descriptor_t *desc;
-+
-+	/** queue of dwc_otg_pcd_requests. */
-+	struct req_list queue;
-+	unsigned stopped:1;
-+	unsigned disabling:1;
-+	unsigned dma:1;
-+	unsigned queue_sof:1;
-+
-+#ifdef DWC_EN_ISOC
-+	/** ISOC req handle passed */
-+	void *iso_req_handle;
-+#endif				//_EN_ISOC_
-+
-+	/** DWC_otg ep data. */
-+	dwc_ep_t dwc_ep;
-+
-+	/** Pointer to PCD */
-+	struct dwc_otg_pcd *pcd;
-+
-+	void *priv;
-+} dwc_otg_pcd_ep_t;
-+
-+/** DWC_otg PCD Structure.
-+ * This structure encapsulates the data for the dwc_otg PCD.
-+ */
-+struct dwc_otg_pcd {
-+	const struct dwc_otg_pcd_function_ops *fops;
-+	/** The DWC otg device pointer */
-+	struct dwc_otg_device *otg_dev;
-+	/** Core Interface */
-+	dwc_otg_core_if_t *core_if;
-+	/** State of EP0 */
-+	ep0state_e ep0state;
-+	/** EP0 Request is pending */
-+	unsigned ep0_pending:1;
-+	/** Indicates when SET CONFIGURATION Request is in process */
-+	unsigned request_config:1;
-+	/** The state of the Remote Wakeup Enable. */
-+	unsigned remote_wakeup_enable:1;
-+	/** The state of the B-Device HNP Enable. */
-+	unsigned b_hnp_enable:1;
-+	/** The state of A-Device HNP Support. */
-+	unsigned a_hnp_support:1;
-+	/** The state of the A-Device Alt HNP support. */
-+	unsigned a_alt_hnp_support:1;
-+	/** Count of pending Requests */
-+	unsigned request_pending;
-+
-+	/** SETUP packet for EP0
-+	 * This structure is allocated as a DMA buffer on PCD initialization
-+	 * with enough space for up to 3 setup packets.
-+	 */
-+	union {
-+		usb_device_request_t req;
-+		uint32_t d32[2];
-+	} *setup_pkt;
-+
-+	dwc_dma_t setup_pkt_dma_handle;
-+
-+	/* Additional buffer and flag for CTRL_WR premature case */
-+	uint8_t *backup_buf;
-+	unsigned data_terminated;
-+
-+	/** 2-byte dma buffer used to return status from GET_STATUS */
-+	uint16_t *status_buf;
-+	dwc_dma_t status_buf_dma_handle;
-+
-+	/** EP0 */
-+	dwc_otg_pcd_ep_t ep0;
-+
-+	/** Array of IN EPs. */
-+	dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
-+	/** Array of OUT EPs. */
-+	dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
-+	/** number of valid EPs in the above array. */
-+//        unsigned      num_eps : 4;
-+	dwc_spinlock_t *lock;
-+
-+	/** Tasklet to defer starting of TEST mode transmissions until
-+	 *	Status Phase has been completed.
-+	 */
-+	dwc_tasklet_t *test_mode_tasklet;
-+
-+	/** Tasklet to delay starting of xfer in DMA mode */
-+	dwc_tasklet_t *start_xfer_tasklet;
-+
-+	/** The test mode to enter when the tasklet is executed. */
-+	unsigned test_mode;
-+	/** The cfi_api structure that implements most of the CFI API
-+	 * and OTG specific core configuration functionality
-+	 */
-+#ifdef DWC_UTE_CFI
-+	struct cfiobject *cfi;
-+#endif
-+
-+};
-+
-+static inline struct device *dwc_otg_pcd_to_dev(struct dwc_otg_pcd *pcd)
-+{
-+	return &pcd->otg_dev->os_dep.platformdev->dev;
-+}
-+
-+//FIXME this functions should be static, and this prototypes should be removed
-+extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
-+extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
-+				 dwc_otg_pcd_request_t * req, int32_t status);
-+
-+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
-+			     void *req_handle);
-+
-+extern void do_test_mode(void *data);
-+#endif
-+#endif /* DWC_HOST_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
-@@ -0,0 +1,361 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
-+ * $Revision: #11 $
-+ * $Date: 2011/10/26 $
-+ * $Change: 1873028 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+#if !defined(__DWC_PCD_IF_H__)
-+#define __DWC_PCD_IF_H__
-+
-+//#include "dwc_os.h"
-+#include "dwc_otg_core_if.h"
-+#include "dwc_otg_driver.h"
-+
-+/** @file
-+ * This file defines DWC_OTG PCD Core API.
-+ */
-+
-+struct dwc_otg_pcd;
-+typedef struct dwc_otg_pcd dwc_otg_pcd_t;
-+
-+/** Maxpacket size for EP0 */
-+#define MAX_EP0_SIZE	64
-+/** Maxpacket size for any EP */
-+#define MAX_PACKET_SIZE 1024
-+
-+/** @name Function Driver Callbacks */
-+/** @{ */
-+
-+/** This function will be called whenever a previously queued request has
-+ * completed.  The status value will be set to -DWC_E_SHUTDOWN to indicated a
-+ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
-+ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
-+ * parameters. */
-+typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+				    void *req_handle, int32_t status,
-+				    uint32_t actual);
-+/**
-+ * This function will be called whenever a previousle queued ISOC request has
-+ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
-+ * function.
-+ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
-+ * functions.
-+ */
-+typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+					 void *req_handle, int proc_buf_num);
-+/** This function should handle any SETUP request that cannot be handled by the
-+ * PCD Core.  This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
-+ * class-specific requests, etc.  The function must non-blocking.
-+ *
-+ * Returns 0 on success.
-+ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
-+ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
-+ * Returns -DWC_E_SHUTDOWN on any other error. */
-+typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
-+/** This is called whenever the device has been disconnected.  The function
-+ * driver should take appropriate action to clean up all pending requests in the
-+ * PCD Core, remove all endpoints (except ep0), and initialize back to reset
-+ * state. */
-+typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has been connected. */
-+typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
-+/** This function is called when device has been suspended */
-+typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has received LPM tokens, i.e.
-+ * device has been sent to sleep state. */
-+typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called when device has been resumed
-+ * from suspend(L2) or L1 sleep state. */
-+typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called whenever hnp params has been changed.
-+ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
-+ * to get hnp parameters. */
-+typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
-+/** This function is called whenever USB RESET is detected. */
-+typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
-+
-+typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
-+
-+/**
-+ *
-+ * @param ep_handle	Void pointer to the usb_ep structure
-+ * @param ereq_port Pointer to the extended request structure created in the
-+ *					portable part.
-+ */
-+typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
-+				     void *req_handle, int32_t status,
-+				     void *ereq_port);
-+/** Function Driver Ops Data Structure */
-+struct dwc_otg_pcd_function_ops {
-+	dwc_connect_cb_t connect;
-+	dwc_disconnect_cb_t disconnect;
-+	dwc_setup_cb_t setup;
-+	dwc_completion_cb_t complete;
-+	dwc_isoc_completion_cb_t isoc_complete;
-+	dwc_suspend_cb_t suspend;
-+	dwc_sleep_cb_t sleep;
-+	dwc_resume_cb_t resume;
-+	dwc_reset_cb_t reset;
-+	dwc_hnp_params_changed_cb_t hnp_changed;
-+	cfi_setup_cb_t cfi_setup;
-+#ifdef DWC_UTE_PER_IO
-+	xiso_completion_cb_t xisoc_complete;
-+#endif
-+};
-+/** @} */
-+
-+/** @name Function Driver Functions */
-+/** @{ */
-+
-+/** Call this function to get pointer on dwc_otg_pcd_t,
-+ * this pointer will be used for all PCD API functions.
-+ *
-+ * @param core_if The DWC_OTG Core
-+ */
-+extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_device_t *otg_dev);
-+
-+/** Frees PCD allocated by dwc_otg_pcd_init
-+ *
-+ * @param pcd The PCD
-+ */
-+extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
-+
-+/** Call this to bind the function driver to the PCD Core.
-+ *
-+ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
-+ * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
-+ */
-+extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
-+			      const struct dwc_otg_pcd_function_ops *fops);
-+
-+/** Enables an endpoint for use.  This function enables an endpoint in
-+ * the PCD.  The endpoint is described by the ep_desc which has the
-+ * same format as a USB ep descriptor.  The ep_handle parameter is used to refer
-+ * to the endpoint from other API functions and in callbacks.  Normally this
-+ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
-+ * core for that interface.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_desc Endpoint descriptor
-+ * @param usb_ep Handle on endpoint, that will be used to identify endpoint.
-+ */
-+extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
-+				 const uint8_t * ep_desc, void *usb_ep);
-+
-+/** Disable the endpoint referenced by ep_handle.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error occurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
-+
-+/** Queue a data transfer request on the endpoint referenced by ep_handle.
-+ * After the transfer is completes, the complete callback will be called with
-+ * the request status.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param buf The buffer for the data
-+ * @param dma_buf The DMA buffer for the data
-+ * @param buflen The length of the data transfer
-+ * @param zero Specifies whether to send zero length last packet.
-+ * @param req_handle Set this handle to any value to use to reference this
-+ * request in the ep_dequeue function or from the complete callback
-+ * @param atomic_alloc If driver need to perform atomic allocations
-+ * for internal data structures.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+				uint8_t * buf, dwc_dma_t dma_buf,
-+				uint32_t buflen, int zero, void *req_handle,
-+				int atomic_alloc);
-+#ifdef DWC_UTE_PER_IO
-+/**
-+ *
-+ * @param ereq_nonport	Pointer to the extended request part of the
-+ *						usb_request structure defined in usb_gadget.h file.
-+ */
-+extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+				     uint8_t * buf, dwc_dma_t dma_buf,
-+				     uint32_t buflen, int zero,
-+				     void *req_handle, int atomic_alloc,
-+				     void *ereq_nonport);
-+
-+#endif
-+
-+/** De-queue the specified data transfer that has not yet completed.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
-+				  void *req_handle);
-+
-+/** Halt (STALL) an endpoint or clear it.
-+ *
-+ * Returns -DWC_E_INVALID if invalid parameters were passed.
-+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.
-+ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
-+ * Returns 0 on success. */
-+extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
-+
-+/** This function */
-+extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
-+
-+/** This function should be called on every hardware interrupt */
-+extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns current frame number */
-+extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
-+
-+/**
-+ * Start isochronous transfers on the endpoint referenced by ep_handle.
-+ * For isochronous transfers duble buffering is used.
-+ * After processing each of buffers comlete callback will be called with
-+ * status for each transaction.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param buf0 The virtual address of first data buffer
-+ * @param buf1 The virtual address of second data buffer
-+ * @param dma0 The DMA address of first data buffer
-+ * @param dma1 The DMA address of second data buffer
-+ * @param sync_frame Data pattern frame number
-+ * @param dp_frame Data size for pattern frame
-+ * @param data_per_frame Data size for regular frame
-+ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
-+ * @param buf_proc_intrvl Interval of ISOC Buffer processing
-+ * @param req_handle Handle of ISOC request
-+ * @param atomic_alloc Specefies whether to perform atomic allocation for
-+ * 			internal data structures.
-+ *
-+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.
-+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
-+ * Returns -DW_E_SHUTDOWN for any other error.
-+ * Returns 0 on success
-+ */
-+extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
-+				    uint8_t * buf0, uint8_t * buf1,
-+				    dwc_dma_t dma0, dwc_dma_t dma1,
-+				    int sync_frame, int dp_frame,
-+				    int data_per_frame, int start_frame,
-+				    int buf_proc_intrvl, void *req_handle,
-+				    int atomic_alloc);
-+
-+/** Stop ISOC transfers on endpoint referenced by ep_handle.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param req_handle Handle of ISOC request
-+ *
-+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
-+ * Returns 0 on success
-+ */
-+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
-+			    void *req_handle);
-+
-+/** Get ISOC packet status.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param iso_req_handle Isochronoush request handle
-+ * @param packet Number of packet
-+ * @param status Out parameter for returning status
-+ * @param actual Out parameter for returning actual length
-+ * @param offset Out parameter for returning offset
-+ *
-+ */
-+extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
-+					      void *ep_handle,
-+					      void *iso_req_handle, int packet,
-+					      int *status, int *actual,
-+					      int *offset);
-+
-+/** Get ISOC packet count.
-+ *
-+ * @param pcd The PCD
-+ * @param ep_handle The handle of the endpoint
-+ * @param iso_req_handle
-+ */
-+extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
-+					    void *ep_handle,
-+					    void *iso_req_handle);
-+
-+/** This function starts the SRP Protocol if no session is in progress. If
-+ * a session is already in progress, but the device is suspended,
-+ * remote wakeup signaling is started.
-+ */
-+extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
-+extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
-+extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
-+
-+/** Initiate SRP */
-+extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
-+
-+/** Starts remote wakeup signaling. */
-+extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
-+
-+/** Starts micorsecond soft disconnect. */
-+extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
-+/** This function returns whether device is dualspeed.*/
-+extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
-+
-+/** This function returns whether device is otg. */
-+extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
-+
-+/** These functions allow to get hnp parameters */
-+extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
-+extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
-+extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
-+
-+/** CFI specific Interface functions */
-+/** Allocate a cfi buffer */
-+extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
-+				     dwc_dma_t * addr, size_t buflen,
-+				     int flags);
-+
-+/******************************************************************************/
-+
-+/** @} */
-+
-+#endif				/* __DWC_PCD_IF_H__ */
-+
-+#endif				/* DWC_HOST_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
-@@ -0,0 +1,5148 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
-+ * $Revision: #116 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+#include "dwc_otg_pcd.h"
-+
-+#ifdef DWC_UTE_CFI
-+#include "dwc_otg_cfi.h"
-+#endif
-+
-+#ifdef DWC_UTE_PER_IO
-+extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
-+#endif
-+//#define PRINT_CFI_DMA_DESCS
-+
-+#define DEBUG_EP0
-+
-+/**
-+ * This function updates OTG.
-+ */
-+static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
-+{
-+
-+	if (reset) {
-+		pcd->b_hnp_enable = 0;
-+		pcd->a_hnp_support = 0;
-+		pcd->a_alt_hnp_support = 0;
-+	}
-+
-+	if (pcd->fops->hnp_changed) {
-+		pcd->fops->hnp_changed(pcd);
-+	}
-+}
-+
-+/** @file
-+ * This file contains the implementation of the PCD Interrupt handlers.
-+ *
-+ * The PCD handles the device interrupts.  Many conditions can cause a
-+ * device interrupt. When an interrupt occurs, the device interrupt
-+ * service routine determines the cause of the interrupt and
-+ * dispatches handling to the appropriate function. These interrupt
-+ * handling functions are described below.
-+ * All interrupt registers are processed from LSB to MSB.
-+ */
-+
-+/**
-+ * This function prints the ep0 state for debug purposes.
-+ */
-+static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
-+{
-+#ifdef DEBUG
-+	char str[40];
-+
-+	switch (pcd->ep0state) {
-+	case EP0_DISCONNECT:
-+		dwc_strcpy(str, "EP0_DISCONNECT");
-+		break;
-+	case EP0_IDLE:
-+		dwc_strcpy(str, "EP0_IDLE");
-+		break;
-+	case EP0_IN_DATA_PHASE:
-+		dwc_strcpy(str, "EP0_IN_DATA_PHASE");
-+		break;
-+	case EP0_OUT_DATA_PHASE:
-+		dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
-+		break;
-+	case EP0_IN_STATUS_PHASE:
-+		dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
-+		break;
-+	case EP0_OUT_STATUS_PHASE:
-+		dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
-+		break;
-+	case EP0_STALL:
-+		dwc_strcpy(str, "EP0_STALL");
-+		break;
-+	default:
-+		dwc_strcpy(str, "EP0_INVALID");
-+	}
-+
-+	DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
-+#endif
-+}
-+
-+/**
-+ * This function calculate the size of the payload in the memory
-+ * for out endpoints and prints size for debug purposes(used in
-+ * 2.93a DevOutNak feature).
-+ */
-+static inline void print_memory_payload(dwc_otg_pcd_t * pcd,  dwc_ep_t * ep)
-+{
-+#ifdef DEBUG
-+	deptsiz_data_t deptsiz_init = {.d32 = 0 };
-+	deptsiz_data_t deptsiz_updt = {.d32 = 0 };
-+	int pack_num;
-+	unsigned payload;
-+
-+	deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
-+	deptsiz_updt.d32 =
-+		DWC_READ_REG32(&pcd->core_if->dev_if->
-+						out_ep_regs[ep->num]->doeptsiz);
-+	/* Payload will be */
-+	payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
-+	/* Packet count is decremented every time a packet
-+	 * is written to the RxFIFO not in to the external memory
-+	 * So, if payload == 0, then it means no packet was sent to ext memory*/
-+	pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
-+	DWC_DEBUGPL(DBG_PCDV,
-+		"Payload for EP%d-%s\n",
-+		ep->num, (ep->is_in ? "IN" : "OUT"));
-+	DWC_DEBUGPL(DBG_PCDV,
-+		"Number of transfered bytes = 0x%08x\n", payload);
-+	DWC_DEBUGPL(DBG_PCDV,
-+		"Number of transfered packets = %d\n", pack_num);
-+#endif
-+}
-+
-+
-+#ifdef DWC_UTE_CFI
-+static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
-+			      const uint8_t * epname, int descnum)
-+{
-+	CFI_INFO
-+	    ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
-+	     epname, descnum, ddesc->buf, ddesc->status.b.bytes,
-+	     ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
-+	     ddesc->status.b.bs);
-+}
-+#endif
-+
-+/**
-+ * This function returns pointer to in ep struct with number ep_num
-+ */
-+static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
-+{
-+	int i;
-+	int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
-+	if (ep_num == 0) {
-+		return &pcd->ep0;
-+	} else {
-+		for (i = 0; i < num_in_eps; ++i) {
-+			if (pcd->in_ep[i].dwc_ep.num == ep_num)
-+				return &pcd->in_ep[i];
-+		}
-+		return 0;
-+	}
-+}
-+
-+/**
-+ * This function returns pointer to out ep struct with number ep_num
-+ */
-+static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
-+{
-+	int i;
-+	int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
-+	if (ep_num == 0) {
-+		return &pcd->ep0;
-+	} else {
-+		for (i = 0; i < num_out_eps; ++i) {
-+			if (pcd->out_ep[i].dwc_ep.num == ep_num)
-+				return &pcd->out_ep[i];
-+		}
-+		return 0;
-+	}
-+}
-+
-+/**
-+ * This functions gets a pointer to an EP from the wIndex address
-+ * value of the control request.
-+ */
-+dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
-+{
-+	dwc_otg_pcd_ep_t *ep;
-+	uint32_t ep_num = UE_GET_ADDR(wIndex);
-+
-+	if (ep_num == 0) {
-+		ep = &pcd->ep0;
-+	} else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {	/* in ep */
-+		ep = &pcd->in_ep[ep_num - 1];
-+	} else {
-+		ep = &pcd->out_ep[ep_num - 1];
-+	}
-+
-+	return ep;
-+}
-+
-+/**
-+ * This function checks the EP request queue, if the queue is not
-+ * empty the next request is started.
-+ */
-+void start_next_request(dwc_otg_pcd_ep_t * ep)
-+{
-+	dwc_otg_pcd_request_t *req = 0;
-+	uint32_t max_transfer =
-+	    GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
-+
-+#ifdef DWC_UTE_CFI
-+	struct dwc_otg_pcd *pcd;
-+	pcd = ep->pcd;
-+#endif
-+
-+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+
-+#ifdef DWC_UTE_CFI
-+		if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+			ep->dwc_ep.cfi_req_len = req->length;
-+			pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
-+		} else {
-+#endif
-+			/* Setup and start the Transfer */
-+			if (req->dw_align_buf) {
-+				ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
-+				ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
-+				ep->dwc_ep.xfer_buff = req->dw_align_buf;
-+			} else {
-+				ep->dwc_ep.dma_addr = req->dma;
-+				ep->dwc_ep.start_xfer_buff = req->buf;
-+				ep->dwc_ep.xfer_buff = req->buf;
-+			}
-+			ep->dwc_ep.sent_zlp = 0;
-+			ep->dwc_ep.total_len = req->length;
-+			ep->dwc_ep.xfer_len = 0;
-+			ep->dwc_ep.xfer_count = 0;
-+
-+			ep->dwc_ep.maxxfer = max_transfer;
-+			if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
-+				uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
-+				    - (DDMA_MAX_TRANSFER_SIZE % 4);
-+				if (ep->dwc_ep.is_in) {
-+					if (ep->dwc_ep.maxxfer >
-+					    DDMA_MAX_TRANSFER_SIZE) {
-+						ep->dwc_ep.maxxfer =
-+						    DDMA_MAX_TRANSFER_SIZE;
-+					}
-+				} else {
-+					if (ep->dwc_ep.maxxfer > out_max_xfer) {
-+						ep->dwc_ep.maxxfer =
-+						    out_max_xfer;
-+					}
-+				}
-+			}
-+			if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
-+				ep->dwc_ep.maxxfer -=
-+				    (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
-+			}
-+			if (req->sent_zlp) {
-+				if ((ep->dwc_ep.total_len %
-+				     ep->dwc_ep.maxpacket == 0)
-+				    && (ep->dwc_ep.total_len != 0)) {
-+					ep->dwc_ep.sent_zlp = 1;
-+				}
-+
-+			}
-+#ifdef DWC_UTE_CFI
-+		}
-+#endif
-+		dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
-+	} else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+		DWC_PRINTF("There are no more ISOC requests \n");
-+		ep->dwc_ep.frame_num = 0xFFFFFFFF;
-+	}
-+}
-+
-+/**
-+ * This function handles the SOF Interrupts. At this time the SOF
-+ * Interrupt is disabled.
-+ */
-+int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+	gintsts_data_t gintsts;
-+
-+	DWC_DEBUGPL(DBG_PCD, "SOF\n");
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.sofintr = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * This function handles the Rx Status Queue Level Interrupt, which
-+ * indicates that there is a least one packet in the Rx FIFO.  The
-+ * packets are moved from the FIFO to memory, where they will be
-+ * processed when the Endpoint Interrupt Register indicates Transfer
-+ * Complete or SETUP Phase Done.
-+ *
-+ * Repeat the following until the Rx Status Queue is empty:
-+ *	 -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
-+ *		info
-+ *	 -# If Receive FIFO is empty then skip to step Clear the interrupt
-+ *		and exit
-+ *	 -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
-+ *		SETUP data to the buffer
-+ *	 -# If OUT Data Packet call dwc_otg_read_packet to copy the data
-+ *		to the destination buffer
-+ */
-+int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	gintmsk_data_t gintmask = {.d32 = 0 };
-+	device_grxsts_data_t status;
-+	dwc_otg_pcd_ep_t *ep;
-+	gintsts_data_t gintsts;
-+#ifdef DEBUG
-+	static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
-+#endif
-+
-+	//DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
-+	/* Disable the Rx Status Queue Level interrupt */
-+	gintmask.b.rxstsqlvl = 1;
-+	DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
-+
-+	/* Get the Status from the top of the FIFO */
-+	status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
-+
-+	DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
-+		    "pktsts:%x Frame:%d(0x%0x)\n",
-+		    status.b.epnum, status.b.bcnt,
-+		    dpid_str[status.b.dpid],
-+		    status.b.pktsts, status.b.fn, status.b.fn);
-+	/* Get pointer to EP structure */
-+	ep = get_out_ep(pcd, status.b.epnum);
-+
-+	switch (status.b.pktsts) {
-+	case DWC_DSTS_GOUT_NAK:
-+		DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
-+		break;
-+	case DWC_STS_DATA_UPDT:
-+		DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
-+		if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
-+			/** @todo NGS Check for buffer overflow? */
-+			dwc_otg_read_packet(core_if,
-+					    ep->dwc_ep.xfer_buff,
-+					    status.b.bcnt);
-+			ep->dwc_ep.xfer_count += status.b.bcnt;
-+			ep->dwc_ep.xfer_buff += status.b.bcnt;
-+		}
-+		break;
-+	case DWC_STS_XFER_COMP:
-+		DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
-+		break;
-+	case DWC_DSTS_SETUP_COMP:
-+#ifdef DEBUG_EP0
-+		DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
-+#endif
-+		break;
-+	case DWC_DSTS_SETUP_UPDT:
-+		dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
-+#ifdef DEBUG_EP0
-+		DWC_DEBUGPL(DBG_PCD,
-+			    "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
-+			    pcd->setup_pkt->req.bmRequestType,
-+			    pcd->setup_pkt->req.bRequest,
-+			    UGETW(pcd->setup_pkt->req.wValue),
-+			    UGETW(pcd->setup_pkt->req.wIndex),
-+			    UGETW(pcd->setup_pkt->req.wLength));
-+#endif
-+		ep->dwc_ep.xfer_count += status.b.bcnt;
-+		break;
-+	default:
-+		DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
-+			    status.b.pktsts);
-+		break;
-+	}
-+
-+	/* Enable the Rx Status Queue Level interrupt */
-+	DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.rxstsqlvl = 1;
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	//DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
-+	return 1;
-+}
-+
-+/**
-+ * This function examines the Device IN Token Learning Queue to
-+ * determine the EP number of the last IN token received.  This
-+ * implementation is for the Mass Storage device where there are only
-+ * 2 IN EPs (Control-IN and BULK-IN).
-+ *
-+ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
-+ * are 8 EP Numbers in each of the other possible DTKNQ Registers.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ *
-+ */
-+static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_device_global_regs_t *dev_global_regs =
-+	    core_if->dev_if->dev_global_regs;
-+	const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
-+	/* Number of Token Queue Registers */
-+	const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
-+	dtknq1_data_t dtknqr1;
-+	uint32_t in_tkn_epnums[4];
-+	int ndx = 0;
-+	int i = 0;
-+	volatile uint32_t *addr = &dev_global_regs->dtknqr1;
-+	int epnum = 0;
-+
-+	//DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
-+
-+	/* Read the DTKNQ Registers */
-+	for (i = 0; i < DTKNQ_REG_CNT; i++) {
-+		in_tkn_epnums[i] = DWC_READ_REG32(addr);
-+		DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
-+			    in_tkn_epnums[i]);
-+		if (addr == &dev_global_regs->dvbusdis) {
-+			addr = &dev_global_regs->dtknqr3_dthrctl;
-+		} else {
-+			++addr;
-+		}
-+
-+	}
-+
-+	/* Copy the DTKNQR1 data to the bit field. */
-+	dtknqr1.d32 = in_tkn_epnums[0];
-+	/* Get the EP numbers */
-+	in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
-+	ndx = dtknqr1.b.intknwptr - 1;
-+
-+	//DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
-+	if (ndx == -1) {
-+		/** @todo Find a simpler way to calculate the max
-+		 * queue position.*/
-+		int cnt = TOKEN_Q_DEPTH;
-+		if (TOKEN_Q_DEPTH <= 6) {
-+			cnt = TOKEN_Q_DEPTH - 1;
-+		} else if (TOKEN_Q_DEPTH <= 14) {
-+			cnt = TOKEN_Q_DEPTH - 7;
-+		} else if (TOKEN_Q_DEPTH <= 22) {
-+			cnt = TOKEN_Q_DEPTH - 15;
-+		} else {
-+			cnt = TOKEN_Q_DEPTH - 23;
-+		}
-+		epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
-+	} else {
-+		if (ndx <= 5) {
-+			epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
-+		} else if (ndx <= 13) {
-+			ndx -= 6;
-+			epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
-+		} else if (ndx <= 21) {
-+			ndx -= 14;
-+			epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
-+		} else if (ndx <= 29) {
-+			ndx -= 22;
-+			epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
-+		}
-+	}
-+	//DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
-+	return epnum;
-+}
-+
-+/**
-+ * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
-+ * The active request is checked for the next packet to be loaded into
-+ * the non-periodic Tx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	dwc_otg_dev_in_ep_regs_t *ep_regs;
-+	gnptxsts_data_t txstatus = {.d32 = 0 };
-+	gintsts_data_t gintsts;
-+
-+	int epnum = 0;
-+	dwc_otg_pcd_ep_t *ep = 0;
-+	uint32_t len = 0;
-+	int dwords;
-+
-+	/* Get the epnum from the IN Token Learning Queue. */
-+	epnum = get_ep_of_last_in_token(core_if);
-+	ep = get_in_ep(pcd, epnum);
-+
-+	DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
-+
-+	ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+	len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+	if (len > ep->dwc_ep.maxpacket) {
-+		len = ep->dwc_ep.maxpacket;
-+	}
-+	dwords = (len + 3) / 4;
-+
-+	/* While there is space in the queue and space in the FIFO and
-+	 * More data to tranfer, Write packets to the Tx FIFO */
-+	txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+	DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
-+
-+	while (txstatus.b.nptxqspcavail > 0 &&
-+	       txstatus.b.nptxfspcavail > dwords &&
-+	       ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
-+		/* Write the FIFO */
-+		dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
-+		len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+
-+		if (len > ep->dwc_ep.maxpacket) {
-+			len = ep->dwc_ep.maxpacket;
-+		}
-+
-+		dwords = (len + 3) / 4;
-+		txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
-+		DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
-+		    DWC_READ_REG32(&global_regs->gnptxsts));
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.nptxfempty = 1;
-+	DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * This function is called when dedicated Tx FIFO Empty interrupt occurs.
-+ * The active request is checked for the next packet to be loaded into
-+ * apropriate Tx FIFO.
-+ */
-+static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	dwc_otg_dev_in_ep_regs_t *ep_regs;
-+	dtxfsts_data_t txstatus = {.d32 = 0 };
-+	dwc_otg_pcd_ep_t *ep = 0;
-+	uint32_t len = 0;
-+	int dwords;
-+
-+	ep = get_in_ep(pcd, epnum);
-+
-+	DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
-+
-+	ep_regs = core_if->dev_if->in_ep_regs[epnum];
-+
-+	len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+
-+	if (len > ep->dwc_ep.maxpacket) {
-+		len = ep->dwc_ep.maxpacket;
-+	}
-+
-+	dwords = (len + 3) / 4;
-+
-+	/* While there is space in the queue and space in the FIFO and
-+	 * More data to tranfer, Write packets to the Tx FIFO */
-+	txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+	DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
-+
-+	while (txstatus.b.txfspcavail > dwords &&
-+	       ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
-+	       ep->dwc_ep.xfer_len != 0) {
-+		/* Write the FIFO */
-+		dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
-+
-+		len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
-+		if (len > ep->dwc_ep.maxpacket) {
-+			len = ep->dwc_ep.maxpacket;
-+		}
-+
-+		dwords = (len + 3) / 4;
-+		txstatus.d32 =
-+		    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
-+		DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
-+			    txstatus.d32);
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
-+		    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
-+
-+	return 1;
-+}
-+
-+/**
-+ * This function is called when the Device is disconnected. It stops
-+ * any active requests and informs the Gadget driver of the
-+ * disconnect.
-+ */
-+void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
-+{
-+	int i, num_in_eps, num_out_eps;
-+	dwc_otg_pcd_ep_t *ep;
-+
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_SPINLOCK(pcd->lock);
-+
-+	num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
-+	num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
-+	/* don't disconnect drivers more than once */
-+	if (pcd->ep0state == EP0_DISCONNECT) {
-+		DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
-+		DWC_SPINUNLOCK(pcd->lock);
-+		return;
-+	}
-+	pcd->ep0state = EP0_DISCONNECT;
-+
-+	/* Reset the OTG state. */
-+	dwc_otg_pcd_update_otg(pcd, 1);
-+
-+	/* Disable the NP Tx Fifo Empty Interrupt. */
-+	intr_mask.b.nptxfempty = 1;
-+	DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+			 intr_mask.d32, 0);
-+
-+	/* Flush the FIFOs */
-+	/**@todo NGS Flush Periodic FIFOs */
-+	dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
-+	dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
-+
-+	/* prevent new request submissions, kill any outstanding requests  */
-+	ep = &pcd->ep0;
-+	dwc_otg_request_nuke(ep);
-+	/* prevent new request submissions, kill any outstanding requests  */
-+	for (i = 0; i < num_in_eps; i++) {
-+		dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
-+		dwc_otg_request_nuke(ep);
-+	}
-+	/* prevent new request submissions, kill any outstanding requests  */
-+	for (i = 0; i < num_out_eps; i++) {
-+		dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
-+		dwc_otg_request_nuke(ep);
-+	}
-+
-+	/* report disconnect; the driver is already quiesced */
-+	if (pcd->fops->disconnect) {
-+		DWC_SPINUNLOCK(pcd->lock);
-+		pcd->fops->disconnect(pcd);
-+		DWC_SPINLOCK(pcd->lock);
-+	}
-+	DWC_SPINUNLOCK(pcd->lock);
-+}
-+
-+/**
-+ * This interrupt indicates that ...
-+ */
-+int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
-+{
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	gintsts_data_t gintsts;
-+
-+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
-+	intr_mask.b.i2cintr = 1;
-+	DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+			 intr_mask.d32, 0);
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.i2cintr = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that ...
-+ */
-+int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
-+{
-+	gintsts_data_t gintsts;
-+#if defined(VERBOSE)
-+	DWC_PRINTF("Early Suspend Detected\n");
-+#endif
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.erlysuspend = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+	return 1;
-+}
-+
-+/**
-+ * This function configures EPO to receive SETUP packets.
-+ *
-+ * @todo NGS: Update the comments from the HW FS.
-+ *
-+ *	-# Program the following fields in the endpoint specific registers
-+ *	for Control OUT EP 0, in order to receive a setup packet
-+ *	- DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
-+ *	  setup packets)
-+ *	- DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
-+ *	  to back setup packets)
-+ *		- In DMA mode, DOEPDMA0 Register with a memory address to
-+ *		  store any setup packets received
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param pcd	  Programming view of the PCD.
-+ */
-+static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
-+				 dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+	depctl_data_t doepctl = {.d32 = 0 };
-+
-+#ifdef VERBOSE
-+	DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
-+		    DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+#endif
-+	if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+		doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
-+		if (doepctl.b.epena) {
-+			return;
-+		}
-+	}
-+
-+	doeptsize0.b.supcnt = 3;
-+	doeptsize0.b.pktcnt = 1;
-+	doeptsize0.b.xfersize = 8 * 3;
-+
-+	if (core_if->dma_enable) {
-+		if (!core_if->dma_desc_enable) {
-+			/** put here as for Hermes mode deptisz register should not be written */
-+			DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
-+					doeptsize0.d32);
-+
-+			/** @todo dma needs to handle multiple setup packets (up to 3) */
-+			DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
-+					pcd->setup_pkt_dma_handle);
-+		} else {
-+			dev_if->setup_desc_index =
-+			    (dev_if->setup_desc_index + 1) & 1;
-+			dma_desc =
-+			    dev_if->setup_desc_addr[dev_if->setup_desc_index];
-+
-+			/** DMA Descriptor Setup */
-+			dma_desc->status.b.bs = BS_HOST_BUSY;
-+			if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+				dma_desc->status.b.sr = 0;
-+				dma_desc->status.b.mtrf = 0;
-+			}
-+			dma_desc->status.b.l = 1;
-+			dma_desc->status.b.ioc = 1;
-+			dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
-+			dma_desc->buf = pcd->setup_pkt_dma_handle;
-+			dma_desc->status.b.sts = 0;
-+			dma_desc->status.b.bs = BS_HOST_READY;
-+
-+			/** DOEPDMA0 Register write */
-+			DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
-+					dev_if->dma_setup_desc_addr
-+					[dev_if->setup_desc_index]);
-+		}
-+
-+	} else {
-+		/** put here as for Hermes mode deptisz register should not be written */
-+		DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
-+				doeptsize0.d32);
-+	}
-+
-+	/** DOEPCTL0 Register write cnak will be set after setup interrupt */
-+	doepctl.d32 = 0;
-+	doepctl.b.epena = 1;
-+	if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
-+	doepctl.b.cnak = 1;
-+	DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
-+	} else {
-+		DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
-+	}
-+
-+#ifdef VERBOSE
-+	DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
-+		    DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
-+	DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
-+		    DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
-+#endif
-+}
-+
-+/**
-+ * This interrupt occurs when a USB Reset is detected. When the USB
-+ * Reset Interrupt occurs the device state is set to DEFAULT and the
-+ * EP0 state is set to IDLE.
-+ *	-#	Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
-+ *	-#	Unmask the following interrupt bits
-+ *		- DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
-+ *	- DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
-+ *	- DOEPMSK.SETUP = 1
-+ *	- DOEPMSK.XferCompl = 1
-+ *	- DIEPMSK.XferCompl = 1
-+ *	- DIEPMSK.TimeOut = 1
-+ *	-# Program the following fields in the endpoint specific registers
-+ *	for Control OUT EP 0, in order to receive a setup packet
-+ *	- DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
-+ *	  setup packets)
-+ *	- DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
-+ *	  to back setup packets)
-+ *		- In DMA mode, DOEPDMA0 Register with a memory address to
-+ *		  store any setup packets received
-+ * At this point, all the required initialization, except for enabling
-+ * the control 0 OUT endpoint is done, for receiving SETUP packets.
-+ */
-+int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	depctl_data_t doepctl = {.d32 = 0 };
-+	depctl_data_t diepctl = {.d32 = 0 };
-+	daint_data_t daintmsk = {.d32 = 0 };
-+	doepmsk_data_t doepmsk = {.d32 = 0 };
-+	diepmsk_data_t diepmsk = {.d32 = 0 };
-+	dcfg_data_t dcfg = {.d32 = 0 };
-+	grstctl_t resetctl = {.d32 = 0 };
-+	dctl_data_t dctl = {.d32 = 0 };
-+	int i = 0;
-+	gintsts_data_t gintsts;
-+	pcgcctl_data_t power = {.d32 = 0 };
-+
-+	power.d32 = DWC_READ_REG32(core_if->pcgcctl);
-+	if (power.b.stoppclk) {
-+		power.d32 = 0;
-+		power.b.stoppclk = 1;
-+		DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+
-+		power.b.pwrclmp = 1;
-+		DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+
-+		power.b.rstpdwnmodule = 1;
-+		DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
-+	}
-+
-+	core_if->lx_state = DWC_OTG_L0;
-+
-+	DWC_PRINTF("USB RESET\n");
-+#ifdef DWC_EN_ISOC
-+	for (i = 1; i < 16; ++i) {
-+		dwc_otg_pcd_ep_t *ep;
-+		dwc_ep_t *dwc_ep;
-+		ep = get_in_ep(pcd, i);
-+		if (ep != 0) {
-+			dwc_ep = &ep->dwc_ep;
-+			dwc_ep->next_frame = 0xffffffff;
-+		}
-+	}
-+#endif /* DWC_EN_ISOC */
-+
-+	/* reset the HNP settings */
-+	dwc_otg_pcd_update_otg(pcd, 1);
-+
-+	/* Clear the Remote Wakeup Signalling */
-+	dctl.b.rmtwkupsig = 1;
-+	DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
-+
-+	/* Set NAK for all OUT EPs */
-+	doepctl.b.snak = 1;
-+	for (i = 0; i <= dev_if->num_out_eps; i++) {
-+		DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
-+	}
-+
-+	/* Flush the NP Tx FIFO */
-+	dwc_otg_flush_tx_fifo(core_if, 0x10);
-+	/* Flush the Learning Queue */
-+	resetctl.b.intknqflsh = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+	if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
-+		core_if->start_predict = 0;
-+		for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
-+			core_if->nextep_seq[i] = 0xff;	// 0xff - EP not active
-+		}
-+		core_if->nextep_seq[0] = 0;
-+		core_if->first_in_nextep_seq = 0;
-+		diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
-+		diepctl.b.nextep = 0;
-+		DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
-+
-+		/* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
-+		dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+		dcfg.b.epmscnt = 2;
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+		DWC_DEBUGPL(DBG_PCDV,
-+			    "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+			__func__, core_if->first_in_nextep_seq);
-+		for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+			DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
-+		}
-+	}
-+
-+	if (core_if->multiproc_int_enable) {
-+		daintmsk.b.inep0 = 1;
-+		daintmsk.b.outep0 = 1;
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
-+				daintmsk.d32);
-+
-+		doepmsk.b.setup = 1;
-+		doepmsk.b.xfercompl = 1;
-+		doepmsk.b.ahberr = 1;
-+		doepmsk.b.epdisabled = 1;
-+
-+		if ((core_if->dma_desc_enable) ||
-+		    (core_if->dma_enable
-+		     && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
-+			doepmsk.b.stsphsercvd = 1;
-+		}
-+		if (core_if->dma_desc_enable)
-+			doepmsk.b.bna = 1;
-+/*
-+		doepmsk.b.babble = 1;
-+		doepmsk.b.nyet = 1;
-+
-+		if (core_if->dma_enable) {
-+			doepmsk.b.nak = 1;
-+		}
-+*/
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
-+				doepmsk.d32);
-+
-+		diepmsk.b.xfercompl = 1;
-+		diepmsk.b.timeout = 1;
-+		diepmsk.b.epdisabled = 1;
-+		diepmsk.b.ahberr = 1;
-+		diepmsk.b.intknepmis = 1;
-+		if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+			diepmsk.b.intknepmis = 0;
-+
-+/*		if (core_if->dma_desc_enable) {
-+			diepmsk.b.bna = 1;
-+		}
-+*/
-+/*
-+		if (core_if->dma_enable) {
-+			diepmsk.b.nak = 1;
-+		}
-+*/
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
-+				diepmsk.d32);
-+	} else {
-+		daintmsk.b.inep0 = 1;
-+		daintmsk.b.outep0 = 1;
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
-+				daintmsk.d32);
-+
-+		doepmsk.b.setup = 1;
-+		doepmsk.b.xfercompl = 1;
-+		doepmsk.b.ahberr = 1;
-+		doepmsk.b.epdisabled = 1;
-+
-+		if ((core_if->dma_desc_enable) ||
-+		    (core_if->dma_enable
-+		     && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
-+			doepmsk.b.stsphsercvd = 1;
-+		}
-+		if (core_if->dma_desc_enable)
-+			doepmsk.b.bna = 1;
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
-+
-+		diepmsk.b.xfercompl = 1;
-+		diepmsk.b.timeout = 1;
-+		diepmsk.b.epdisabled = 1;
-+		diepmsk.b.ahberr = 1;
-+		if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
-+			diepmsk.b.intknepmis = 0;
-+/*
-+		if (core_if->dma_desc_enable) {
-+			diepmsk.b.bna = 1;
-+		}
-+*/
-+
-+		DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
-+	}
-+
-+	/* Reset Device Address */
-+	dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
-+	dcfg.b.devaddr = 0;
-+	DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
-+
-+	/* setup EP0 to receive SETUP packets */
-+	if (core_if->snpsid <= OTG_CORE_REV_2_94a)
-+		ep0_out_start(core_if, pcd);
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.usbreset = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * Get the device speed from the device status register and convert it
-+ * to USB speed constant.
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ */
-+static int get_device_speed(dwc_otg_core_if_t * core_if)
-+{
-+	dsts_data_t dsts;
-+	int speed = 0;
-+	dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
-+
-+	switch (dsts.b.enumspd) {
-+	case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
-+		speed = USB_SPEED_HIGH;
-+		break;
-+	case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
-+	case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
-+		speed = USB_SPEED_FULL;
-+		break;
-+
-+	case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
-+		speed = USB_SPEED_LOW;
-+		break;
-+	}
-+
-+	return speed;
-+}
-+
-+/**
-+ * Read the device status register and set the device speed in the
-+ * data structure.
-+ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
-+ */
-+int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+	gintsts_data_t gintsts;
-+	gusbcfg_data_t gusbcfg;
-+	dwc_otg_core_global_regs_t *global_regs =
-+	    GET_CORE_IF(pcd)->core_global_regs;
-+	uint8_t utmi16b, utmi8b;
-+	int speed;
-+	DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
-+
-+	if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
-+		utmi16b = 6;	//vahrama old value was 6;
-+		utmi8b = 9;
-+	} else {
-+		utmi16b = 4;
-+		utmi8b = 8;
-+	}
-+	dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+	if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
-+		ep0_out_start(GET_CORE_IF(pcd), pcd);
-+	}
-+
-+#ifdef DEBUG_EP0
-+	print_ep0_state(pcd);
-+#endif
-+
-+	if (pcd->ep0state == EP0_DISCONNECT) {
-+		pcd->ep0state = EP0_IDLE;
-+	} else if (pcd->ep0state == EP0_STALL) {
-+		pcd->ep0state = EP0_IDLE;
-+	}
-+
-+	pcd->ep0state = EP0_IDLE;
-+
-+	ep0->stopped = 0;
-+
-+	speed = get_device_speed(GET_CORE_IF(pcd));
-+	pcd->fops->connect(pcd, speed);
-+
-+	/* Set USB turnaround time based on device speed and PHY interface. */
-+	gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
-+	if (speed == USB_SPEED_HIGH) {
-+		if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+		    DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
-+			/* ULPI interface */
-+			gusbcfg.b.usbtrdtim = 9;
-+		}
-+		if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+		    DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
-+			/* UTMI+ interface */
-+			if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
-+				gusbcfg.b.usbtrdtim = utmi8b;
-+			} else if (GET_CORE_IF(pcd)->hwcfg4.
-+				   b.utmi_phy_data_width == 1) {
-+				gusbcfg.b.usbtrdtim = utmi16b;
-+			} else if (GET_CORE_IF(pcd)->
-+				   core_params->phy_utmi_width == 8) {
-+				gusbcfg.b.usbtrdtim = utmi8b;
-+			} else {
-+				gusbcfg.b.usbtrdtim = utmi16b;
-+			}
-+		}
-+		if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
-+		    DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
-+			/* UTMI+  OR  ULPI interface */
-+			if (gusbcfg.b.ulpi_utmi_sel == 1) {
-+				/* ULPI interface */
-+				gusbcfg.b.usbtrdtim = 9;
-+			} else {
-+				/* UTMI+ interface */
-+				if (GET_CORE_IF(pcd)->
-+				    core_params->phy_utmi_width == 16) {
-+					gusbcfg.b.usbtrdtim = utmi16b;
-+				} else {
-+					gusbcfg.b.usbtrdtim = utmi8b;
-+				}
-+			}
-+		}
-+	} else {
-+		/* Full or low speed */
-+		gusbcfg.b.usbtrdtim = 9;
-+	}
-+	DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.enumdone = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that the ISO OUT Packet was dropped due to
-+ * Rx FIFO full or Rx Status Queue Full.  If this interrupt occurs
-+ * read all the data from the Rx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
-+{
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	gintsts_data_t gintsts;
-+
-+	DWC_WARN("INTERRUPT Handler not implemented for %s\n",
-+		 "ISOC Out Dropped");
-+
-+	intr_mask.b.isooutdrop = 1;
-+	DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+			 intr_mask.d32, 0);
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.isooutdrop = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates the end of the portion of the micro-frame
-+ * for periodic transactions.  If there is a periodic transaction for
-+ * the next frame, load the packets into the EP periodic Tx FIFO.
-+ */
-+int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
-+{
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	gintsts_data_t gintsts;
-+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
-+
-+	intr_mask.b.eopframe = 1;
-+	DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+			 intr_mask.d32, 0);
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.eopframe = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that EP of the packet on the top of the
-+ * non-periodic Tx FIFO does not match EP of the IN Token received.
-+ *
-+ * The "Device IN Token Queue" Registers are read to determine the
-+ * order the IN Tokens have been received. The non-periodic Tx FIFO
-+ * is flushed, so it can be reloaded in the order seen in the IN Token
-+ * Queue.
-+ */
-+int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
-+{
-+	gintsts_data_t gintsts;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dctl_data_t dctl;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
-+		core_if->start_predict = 1;
-+
-+		DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
-+
-+		gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+		if (!gintsts.b.ginnakeff) {
-+			/* Disable EP Mismatch interrupt */
-+			intr_mask.d32 = 0;
-+			intr_mask.b.epmismatch = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
-+			/* Enable the Global IN NAK Effective Interrupt */
-+			intr_mask.d32 = 0;
-+			intr_mask.b.ginnakeff = 1;
-+			DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
-+			/* Set the global non-periodic IN NAK handshake */
-+			dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+			dctl.b.sgnpinnak = 1;
-+			DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+		} else {
-+			DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
-+		}
-+		/* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
-+		 * handler after Global IN NAK Effective interrupt will be asserted */
-+	}
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.epmismatch = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt is valid only in DMA mode. This interrupt indicates that the
-+ * core has stopped fetching data for IN endpoints due to the unavailability of
-+ * TxFIFO space or Request Queue space. This interrupt is used by the
-+ * application for an endpoint mismatch algorithm.
-+ *
-+ * @param pcd The PCD
-+ */
-+int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
-+{
-+	gintsts_data_t gintsts;
-+	gintmsk_data_t gintmsk_data;
-+	dctl_data_t dctl;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
-+
-+	/* Clear the global non-periodic IN NAK handshake */
-+	dctl.d32 = 0;
-+	dctl.b.cgnpinnak = 1;
-+	DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+	/* Mask GINTSTS.FETSUSP interrupt */
-+	gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+	gintmsk_data.b.fetsusp = 0;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.fetsusp = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
-+
-+	return 1;
-+}
-+/**
-+ * This funcion stalls EP0.
-+ */
-+static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
-+{
-+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+	usb_device_request_t *ctrl = &pcd->setup_pkt->req;
-+	DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
-+		 ctrl->bmRequestType, ctrl->bRequest, err_val);
-+
-+	ep0->dwc_ep.is_in = 1;
-+	dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+	pcd->ep0.stopped = 1;
-+	pcd->ep0state = EP0_IDLE;
-+	ep0_out_start(GET_CORE_IF(pcd), pcd);
-+}
-+
-+/**
-+ * This functions delegates the setup command to the gadget driver.
-+ */
-+static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
-+				   usb_device_request_t * ctrl)
-+{
-+	int ret = 0;
-+	DWC_SPINUNLOCK(pcd->lock);
-+	ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
-+	DWC_SPINLOCK(pcd->lock);
-+	if (ret < 0) {
-+		ep0_do_stall(pcd, ret);
-+	}
-+
-+	/** @todo This is a g_file_storage gadget driver specific
-+	 * workaround: a DELAYED_STATUS result from the fsg_setup
-+	 * routine will result in the gadget queueing a EP0 IN status
-+	 * phase for a two-stage control transfer. Exactly the same as
-+	 * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
-+	 * specific request.  Need a generic way to know when the gadget
-+	 * driver will queue the status phase. Can we assume when we
-+	 * call the gadget driver setup() function that it will always
-+	 * queue and require the following flag? Need to look into
-+	 * this.
-+	 */
-+
-+	if (ret == 256 + 999) {
-+		pcd->request_config = 1;
-+	}
-+}
-+
-+#ifdef DWC_UTE_CFI
-+/**
-+ * This functions delegates the CFI setup commands to the gadget driver.
-+ * This function will return a negative value to indicate a failure.
-+ */
-+static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
-+				   struct cfi_usb_ctrlrequest *ctrl_req)
-+{
-+	int ret = 0;
-+
-+	if (pcd->fops && pcd->fops->cfi_setup) {
-+		DWC_SPINUNLOCK(pcd->lock);
-+		ret = pcd->fops->cfi_setup(pcd, ctrl_req);
-+		DWC_SPINLOCK(pcd->lock);
-+		if (ret < 0) {
-+			ep0_do_stall(pcd, ret);
-+			return ret;
-+		}
-+	}
-+
-+	return ret;
-+}
-+#endif
-+
-+/**
-+ * This function starts the Zero-Length Packet for the IN status phase
-+ * of a 2 stage control transfer.
-+ */
-+static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+	if (pcd->ep0state == EP0_STALL) {
-+		return;
-+	}
-+
-+	pcd->ep0state = EP0_IN_STATUS_PHASE;
-+
-+	/* Prepare for more SETUP Packets */
-+	DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
-+	if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
-+	    && (pcd->core_if->dma_desc_enable)
-+	    && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
-+		DWC_DEBUGPL(DBG_PCDV,
-+			    "Data terminated wait next packet in out_desc_addr\n");
-+		pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
-+		pcd->data_terminated = 1;
-+	}
-+	ep0->dwc_ep.xfer_len = 0;
-+	ep0->dwc_ep.xfer_count = 0;
-+	ep0->dwc_ep.is_in = 1;
-+	ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
-+	dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+
-+	/* Prepare for more SETUP Packets */
-+	//ep0_out_start(GET_CORE_IF(pcd), pcd);
-+}
-+
-+/**
-+ * This function starts the Zero-Length Packet for the OUT status phase
-+ * of a 2 stage control transfer.
-+ */
-+static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+	if (pcd->ep0state == EP0_STALL) {
-+		DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
-+		return;
-+	}
-+	pcd->ep0state = EP0_OUT_STATUS_PHASE;
-+
-+	DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
-+	ep0->dwc_ep.xfer_len = 0;
-+	ep0->dwc_ep.xfer_count = 0;
-+	ep0->dwc_ep.is_in = 0;
-+	ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
-+	dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+
-+	/* Prepare for more SETUP Packets */
-+	if (GET_CORE_IF(pcd)->dma_enable == 0) {
-+		ep0_out_start(GET_CORE_IF(pcd), pcd);
-+	}
-+}
-+
-+/**
-+ * Clear the EP halt (STALL) and if pending requests start the
-+ * transfer.
-+ */
-+static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
-+{
-+	if (ep->dwc_ep.stall_clear_flag == 0)
-+		dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
-+
-+	/* Reactive the EP */
-+	dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
-+	if (ep->stopped) {
-+		ep->stopped = 0;
-+		/* If there is a request in the EP queue start it */
-+
-+		/** @todo FIXME: this causes an EP mismatch in DMA mode.
-+		 * epmismatch not yet implemented. */
-+
-+		/*
-+		 * Above fixme is solved by implmenting a tasklet to call the
-+		 * start_next_request(), outside of interrupt context at some
-+		 * time after the current time, after a clear-halt setup packet.
-+		 * Still need to implement ep mismatch in the future if a gadget
-+		 * ever uses more than one endpoint at once
-+		 */
-+		ep->queue_sof = 1;
-+		DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
-+	}
-+	/* Start Control Status Phase */
-+	do_setup_in_status_phase(pcd);
-+}
-+
-+/**
-+ * This function is called when the SET_FEATURE TEST_MODE Setup packet
-+ * is sent from the host.  The Device Control register is written with
-+ * the Test Mode bits set to the specified Test Mode.  This is done as
-+ * a tasklet so that the "Status" phase of the control transfer
-+ * completes before transmitting the TEST packets.
-+ *
-+ * @todo This has not been tested since the tasklet struct was put
-+ * into the PCD struct!
-+ *
-+ */
-+void do_test_mode(void *data)
-+{
-+	dctl_data_t dctl;
-+	dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	int test_mode = pcd->test_mode;
-+
-+//        DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
-+
-+	dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+	switch (test_mode) {
-+	case 1:		// TEST_J
-+		dctl.b.tstctl = 1;
-+		break;
-+
-+	case 2:		// TEST_K
-+		dctl.b.tstctl = 2;
-+		break;
-+
-+	case 3:		// TEST_SE0_NAK
-+		dctl.b.tstctl = 3;
-+		break;
-+
-+	case 4:		// TEST_PACKET
-+		dctl.b.tstctl = 4;
-+		break;
-+
-+	case 5:		// TEST_FORCE_ENABLE
-+		dctl.b.tstctl = 5;
-+		break;
-+	}
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+}
-+
-+/**
-+ * This function process the GET_STATUS Setup Commands.
-+ */
-+static inline void do_get_status(dwc_otg_pcd_t * pcd)
-+{
-+	usb_device_request_t ctrl = pcd->setup_pkt->req;
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+	uint16_t *status = pcd->status_buf;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+
-+#ifdef DEBUG_EP0
-+	DWC_DEBUGPL(DBG_PCD,
-+		    "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
-+		    ctrl.bmRequestType, ctrl.bRequest,
-+		    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+		    UGETW(ctrl.wLength));
-+#endif
-+
-+	switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+	case UT_DEVICE:
-+		if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
-+			DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
-+			DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
-+			DWC_PRINTF("OTG CAP - %d, %d\n",
-+				   core_if->core_params->otg_cap,
-+						DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
-+			if (core_if->otg_ver == 1
-+			    && core_if->core_params->otg_cap ==
-+			    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+				uint8_t *otgsts = (uint8_t*)pcd->status_buf;
-+				*otgsts = (core_if->otg_sts & 0x1);
-+				pcd->ep0_pending = 1;
-+				ep0->dwc_ep.start_xfer_buff =
-+				    (uint8_t *) otgsts;
-+				ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
-+				ep0->dwc_ep.dma_addr =
-+				    pcd->status_buf_dma_handle;
-+				ep0->dwc_ep.xfer_len = 1;
-+				ep0->dwc_ep.xfer_count = 0;
-+				ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
-+				dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
-+							   &ep0->dwc_ep);
-+				return;
-+			} else {
-+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+				return;
-+			}
-+			break;
-+		} else {
-+			*status = 0x1;	/* Self powered */
-+			*status |= pcd->remote_wakeup_enable << 1;
-+			break;
-+		}
-+	case UT_INTERFACE:
-+		*status = 0;
-+		break;
-+
-+	case UT_ENDPOINT:
-+		ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+		if (ep == 0 || UGETW(ctrl.wLength) > 2) {
-+			ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+			return;
-+		}
-+		/** @todo check for EP stall */
-+		*status = ep->stopped;
-+		break;
-+	}
-+	pcd->ep0_pending = 1;
-+	ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
-+	ep0->dwc_ep.xfer_buff = (uint8_t *) status;
-+	ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
-+	ep0->dwc_ep.xfer_len = 2;
-+	ep0->dwc_ep.xfer_count = 0;
-+	ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
-+	dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
-+}
-+
-+/**
-+ * This function process the SET_FEATURE Setup Commands.
-+ */
-+static inline void do_set_feature(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+	usb_device_request_t ctrl = pcd->setup_pkt->req;
-+	dwc_otg_pcd_ep_t *ep = 0;
-+	int32_t otg_cap_param = core_if->core_params->otg_cap;
-+	gotgctl_data_t gotgctl = {.d32 = 0 };
-+
-+	DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
-+		    ctrl.bmRequestType, ctrl.bRequest,
-+		    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+		    UGETW(ctrl.wLength));
-+	DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
-+
-+	switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+	case UT_DEVICE:
-+		switch (UGETW(ctrl.wValue)) {
-+		case UF_DEVICE_REMOTE_WAKEUP:
-+			pcd->remote_wakeup_enable = 1;
-+			break;
-+
-+		case UF_TEST_MODE:
-+			/* Setup the Test Mode tasklet to do the Test
-+			 * Packet generation after the SETUP Status
-+			 * phase has completed. */
-+
-+			/** @todo This has not been tested since the
-+			 * tasklet struct was put into the PCD
-+			 * struct! */
-+			pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
-+			DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
-+			break;
-+
-+		case UF_DEVICE_B_HNP_ENABLE:
-+			DWC_DEBUGPL(DBG_PCDV,
-+				    "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
-+
-+			/* dev may initiate HNP */
-+			if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+				pcd->b_hnp_enable = 1;
-+				dwc_otg_pcd_update_otg(pcd, 0);
-+				DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
-+				/**@todo Is the gotgctl.devhnpen cleared
-+				 * by a USB Reset? */
-+				gotgctl.b.devhnpen = 1;
-+				gotgctl.b.hnpreq = 1;
-+				DWC_WRITE_REG32(&global_regs->gotgctl,
-+						gotgctl.d32);
-+			} else {
-+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+				return;
-+			}
-+			break;
-+
-+		case UF_DEVICE_A_HNP_SUPPORT:
-+			/* RH port supports HNP */
-+			DWC_DEBUGPL(DBG_PCDV,
-+				    "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
-+			if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+				pcd->a_hnp_support = 1;
-+				dwc_otg_pcd_update_otg(pcd, 0);
-+			} else {
-+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+				return;
-+			}
-+			break;
-+
-+		case UF_DEVICE_A_ALT_HNP_SUPPORT:
-+			/* other RH port does */
-+			DWC_DEBUGPL(DBG_PCDV,
-+				    "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
-+			if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
-+				pcd->a_alt_hnp_support = 1;
-+				dwc_otg_pcd_update_otg(pcd, 0);
-+			} else {
-+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+				return;
-+			}
-+			break;
-+
-+		default:
-+			ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+			return;
-+
-+		}
-+		do_setup_in_status_phase(pcd);
-+		break;
-+
-+	case UT_INTERFACE:
-+		do_gadget_setup(pcd, &ctrl);
-+		break;
-+
-+	case UT_ENDPOINT:
-+		if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
-+			ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+			if (ep == 0) {
-+				ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+				return;
-+			}
-+			ep->stopped = 1;
-+			dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
-+		}
-+		do_setup_in_status_phase(pcd);
-+		break;
-+	}
-+}
-+
-+/**
-+ * This function process the CLEAR_FEATURE Setup Commands.
-+ */
-+static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
-+{
-+	usb_device_request_t ctrl = pcd->setup_pkt->req;
-+	dwc_otg_pcd_ep_t *ep = 0;
-+
-+	DWC_DEBUGPL(DBG_PCD,
-+		    "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
-+		    ctrl.bmRequestType, ctrl.bRequest,
-+		    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+		    UGETW(ctrl.wLength));
-+
-+	switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
-+	case UT_DEVICE:
-+		switch (UGETW(ctrl.wValue)) {
-+		case UF_DEVICE_REMOTE_WAKEUP:
-+			pcd->remote_wakeup_enable = 0;
-+			break;
-+
-+		case UF_TEST_MODE:
-+			/** @todo Add CLEAR_FEATURE for TEST modes. */
-+			break;
-+
-+		default:
-+			ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+			return;
-+		}
-+		do_setup_in_status_phase(pcd);
-+		break;
-+
-+	case UT_ENDPOINT:
-+		ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
-+		if (ep == 0) {
-+			ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
-+			return;
-+		}
-+
-+		pcd_clear_halt(pcd, ep);
-+
-+		break;
-+	}
-+}
-+
-+/**
-+ * This function process the SET_ADDRESS Setup Commands.
-+ */
-+static inline void do_set_address(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+	usb_device_request_t ctrl = pcd->setup_pkt->req;
-+
-+	if (ctrl.bmRequestType == UT_DEVICE) {
-+		dcfg_data_t dcfg = {.d32 = 0 };
-+
-+#ifdef DEBUG_EP0
-+//                      DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
-+#endif
-+		dcfg.b.devaddr = UGETW(ctrl.wValue);
-+		DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
-+		do_setup_in_status_phase(pcd);
-+	}
-+}
-+
-+/**
-+ *	This function processes SETUP commands. In Linux, the USB Command
-+ *	processing is done in two places - the first being the PCD and the
-+ *	second in the Gadget Driver (for example, the File-Backed Storage
-+ *	Gadget Driver).
-+ *
-+ * <table>
-+ * <tr><td>Command	</td><td>Driver </td><td>Description</td></tr>
-+ *
-+ * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
-+ * defined in chapter 9 of the USB 2.0 Specification chapter 9
-+ * </td></tr>
-+ *
-+ * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
-+ * requests are the ENDPOINT_HALT feature is procesed, all others the
-+ * interface requests are ignored.</td></tr>
-+ *
-+ * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
-+ * requests are processed by the PCD.  Interface requests are passed
-+ * to the Gadget Driver.</td></tr>
-+ *
-+ * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
-+ * with device address received </td></tr>
-+ *
-+ * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
-+ * requested descriptor</td></tr>
-+ *
-+ * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
-+ * not implemented by any of the existing Gadget Drivers.</td></tr>
-+ *
-+ * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
-+ * all EPs and enable EPs for new configuration.</td></tr>
-+ *
-+ * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
-+ * the current configuration</td></tr>
-+ *
-+ * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
-+ * EPs and enable EPs for new configuration.</td></tr>
-+ *
-+ * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
-+ * current interface.</td></tr>
-+ *
-+ * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
-+ * message.</td></tr>
-+ * </table>
-+ *
-+ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
-+ * processed by pcd_setup. Calling the Function Driver's setup function from
-+ * pcd_setup processes the gadget SETUP commands.
-+ */
-+static inline void pcd_setup(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	usb_device_request_t ctrl = pcd->setup_pkt->req;
-+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+
-+	deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+
-+#ifdef DWC_UTE_CFI
-+	int retval = 0;
-+	struct cfi_usb_ctrlrequest cfi_req;
-+#endif
-+
-+	doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
-+
-+	/** In BDMA more then 1 setup packet is not supported till 3.00a */
-+	if (core_if->dma_enable && core_if->dma_desc_enable == 0
-+	    && (doeptsize0.b.supcnt < 2)
-+	    && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
-+		DWC_ERROR
-+		    ("\n\n-----------	 CANNOT handle > 1 setup packet in DMA mode\n\n");
-+	}
-+	if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
-+	    && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
-+		ctrl =
-+		    (pcd->setup_pkt +
-+		     (3 - doeptsize0.b.supcnt - 1 +
-+		      ep0->dwc_ep.stp_rollover))->req;
-+	}
-+#ifdef DEBUG_EP0
-+	DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
-+		    ctrl.bmRequestType, ctrl.bRequest,
-+		    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
-+		    UGETW(ctrl.wLength));
-+#endif
-+
-+	/* Clean up the request queue */
-+	dwc_otg_request_nuke(ep0);
-+	ep0->stopped = 0;
-+
-+	if (ctrl.bmRequestType & UE_DIR_IN) {
-+		ep0->dwc_ep.is_in = 1;
-+		pcd->ep0state = EP0_IN_DATA_PHASE;
-+	} else {
-+		ep0->dwc_ep.is_in = 0;
-+		pcd->ep0state = EP0_OUT_DATA_PHASE;
-+	}
-+
-+	if (UGETW(ctrl.wLength) == 0) {
-+		ep0->dwc_ep.is_in = 1;
-+		pcd->ep0state = EP0_IN_STATUS_PHASE;
-+	}
-+
-+	if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
-+
-+#ifdef DWC_UTE_CFI
-+		DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
-+
-+		//printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
-+				ctrl.bRequestType, ctrl.bRequest);
-+		if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
-+			if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
-+				retval = cfi_setup(pcd, &cfi_req);
-+				if (retval < 0) {
-+					ep0_do_stall(pcd, retval);
-+					pcd->ep0_pending = 0;
-+					return;
-+				}
-+
-+				/* if need gadget setup then call it and check the retval */
-+				if (pcd->cfi->need_gadget_att) {
-+					retval =
-+					    cfi_gadget_setup(pcd,
-+							     &pcd->
-+							     cfi->ctrl_req);
-+					if (retval < 0) {
-+						pcd->ep0_pending = 0;
-+						return;
-+					}
-+				}
-+
-+				if (pcd->cfi->need_status_in_complete) {
-+					do_setup_in_status_phase(pcd);
-+				}
-+				return;
-+			}
-+		}
-+#endif
-+
-+		/* handle non-standard (class/vendor) requests in the gadget driver */
-+		do_gadget_setup(pcd, &ctrl);
-+		return;
-+	}
-+
-+	/** @todo NGS: Handle bad setup packet? */
-+
-+///////////////////////////////////////////
-+//// --- Standard Request handling --- ////
-+
-+	switch (ctrl.bRequest) {
-+	case UR_GET_STATUS:
-+		do_get_status(pcd);
-+		break;
-+
-+	case UR_CLEAR_FEATURE:
-+		do_clear_feature(pcd);
-+		break;
-+
-+	case UR_SET_FEATURE:
-+		do_set_feature(pcd);
-+		break;
-+
-+	case UR_SET_ADDRESS:
-+		do_set_address(pcd);
-+		break;
-+
-+	case UR_SET_INTERFACE:
-+	case UR_SET_CONFIG:
-+//              _pcd->request_config = 1;       /* Configuration changed */
-+		do_gadget_setup(pcd, &ctrl);
-+		break;
-+
-+	case UR_SYNCH_FRAME:
-+		do_gadget_setup(pcd, &ctrl);
-+		break;
-+
-+	default:
-+		/* Call the Gadget Driver's setup functions */
-+		do_gadget_setup(pcd, &ctrl);
-+		break;
-+	}
-+}
-+
-+/**
-+ * This function completes the ep0 control transfer.
-+ */
-+static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	dwc_otg_dev_in_ep_regs_t *in_ep_regs =
-+	    dev_if->in_ep_regs[ep->dwc_ep.num];
-+#ifdef DEBUG_EP0
-+	dwc_otg_dev_out_ep_regs_t *out_ep_regs =
-+	    dev_if->out_ep_regs[ep->dwc_ep.num];
-+#endif
-+	deptsiz0_data_t deptsiz;
-+	dev_dma_desc_sts_t desc_sts;
-+	dwc_otg_pcd_request_t *req;
-+	int is_last = 0;
-+	dwc_otg_pcd_t *pcd = ep->pcd;
-+
-+#ifdef DWC_UTE_CFI
-+	struct cfi_usb_ctrlrequest *ctrlreq;
-+	int retval = -DWC_E_NOT_SUPPORTED;
-+#endif
-+
-+        desc_sts.b.bytes = 0;
-+
-+	if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		if (ep->dwc_ep.is_in) {
-+#ifdef DEBUG_EP0
-+			DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
-+#endif
-+			do_setup_out_status_phase(pcd);
-+		} else {
-+#ifdef DEBUG_EP0
-+			DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
-+#endif
-+
-+#ifdef DWC_UTE_CFI
-+			ctrlreq = &pcd->cfi->ctrl_req;
-+
-+			if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
-+				if (ctrlreq->bRequest > 0xB0
-+				    && ctrlreq->bRequest < 0xBF) {
-+
-+					/* Return if the PCD failed to handle the request */
-+					if ((retval =
-+					     pcd->cfi->ops.
-+					     ctrl_write_complete(pcd->cfi,
-+								 pcd)) < 0) {
-+						CFI_INFO
-+						    ("ERROR setting a new value in the PCD(%d)\n",
-+						     retval);
-+						ep0_do_stall(pcd, retval);
-+						pcd->ep0_pending = 0;
-+						return 0;
-+					}
-+
-+					/* If the gadget needs to be notified on the request */
-+					if (pcd->cfi->need_gadget_att == 1) {
-+						//retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
-+						retval =
-+						    cfi_gadget_setup(pcd,
-+								     &pcd->cfi->
-+								     ctrl_req);
-+
-+						/* Return from the function if the gadget failed to process
-+						 * the request properly - this should never happen !!!
-+						 */
-+						if (retval < 0) {
-+							CFI_INFO
-+							    ("ERROR setting a new value in the gadget(%d)\n",
-+							     retval);
-+							pcd->ep0_pending = 0;
-+							return 0;
-+						}
-+					}
-+
-+					CFI_INFO("%s: RETVAL=%d\n", __func__,
-+						 retval);
-+					/* If we hit here then the PCD and the gadget has properly
-+					 * handled the request - so send the ZLP IN to the host.
-+					 */
-+					/* @todo: MAS - decide whether we need to start the setup
-+					 * stage based on the need_setup value of the cfi object
-+					 */
-+					do_setup_in_status_phase(pcd);
-+					pcd->ep0_pending = 0;
-+					return 1;
-+				}
-+			}
-+#endif
-+
-+			do_setup_in_status_phase(pcd);
-+		}
-+		pcd->ep0_pending = 0;
-+		return 1;
-+	}
-+
-+	if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		return 0;
-+	}
-+	req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+
-+	if (pcd->ep0state == EP0_OUT_STATUS_PHASE
-+	    || pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+		is_last = 1;
-+	} else if (ep->dwc_ep.is_in) {
-+		deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
-+		if (core_if->dma_desc_enable != 0)
-+			desc_sts = dev_if->in_desc_addr->status;
-+#ifdef DEBUG_EP0
-+		DWC_DEBUGPL(DBG_PCDV, "%d len=%d  xfersize=%d pktcnt=%d\n",
-+			    ep->dwc_ep.num, ep->dwc_ep.xfer_len,
-+			    deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+#endif
-+
-+		if (((core_if->dma_desc_enable == 0)
-+		     && (deptsiz.b.xfersize == 0))
-+		    || ((core_if->dma_desc_enable != 0)
-+			&& (desc_sts.b.bytes == 0))) {
-+			req->actual = ep->dwc_ep.xfer_count;
-+			/* Is a Zero Len Packet needed? */
-+			if (req->sent_zlp) {
-+#ifdef DEBUG_EP0
-+				DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
-+#endif
-+				req->sent_zlp = 0;
-+			}
-+			do_setup_out_status_phase(pcd);
-+		}
-+	} else {
-+		/* ep0-OUT */
-+#ifdef DEBUG_EP0
-+		deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
-+		DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
-+			    ep->dwc_ep.num, ep->dwc_ep.xfer_len,
-+			    deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+#endif
-+		req->actual = ep->dwc_ep.xfer_count;
-+
-+		/* Is a Zero Len Packet needed? */
-+		if (req->sent_zlp) {
-+#ifdef DEBUG_EP0
-+			DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
-+#endif
-+			req->sent_zlp = 0;
-+		}
-+		/* For older cores do setup in status phase in Slave/BDMA modes,
-+		 * starting from 3.00 do that only in slave, and for DMA modes
-+		 * just re-enable ep 0 OUT here*/
-+		if (core_if->dma_enable == 0
-+		    || (core_if->dma_desc_enable == 0
-+			&& core_if->snpsid <= OTG_CORE_REV_2_94a)) {
-+			do_setup_in_status_phase(pcd);
-+		} else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+			DWC_DEBUGPL(DBG_PCDV,
-+				    "Enable out ep before in status phase\n");
-+			ep0_out_start(core_if, pcd);
-+		}
-+	}
-+
-+	/* Complete the request */
-+	if (is_last) {
-+		dwc_otg_request_done(ep, req, 0);
-+		ep->dwc_ep.start_xfer_buff = 0;
-+		ep->dwc_ep.xfer_buff = 0;
-+		ep->dwc_ep.xfer_len = 0;
-+		return 1;
-+	}
-+	return 0;
-+}
-+
-+#ifdef DWC_UTE_CFI
-+/**
-+ * This function calculates traverses all the CFI DMA descriptors and
-+ * and accumulates the bytes that are left to be transfered.
-+ *
-+ * @return The total bytes left to transfered, or a negative value as failure
-+ */
-+static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
-+{
-+	int32_t ret = 0;
-+	int i;
-+	struct dwc_otg_dma_desc *ddesc = NULL;
-+	struct cfi_ep *cfiep;
-+
-+	/* See if the pcd_ep has its respective cfi_ep mapped */
-+	cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
-+	if (!cfiep) {
-+		CFI_INFO("%s: Failed to find ep\n", __func__);
-+		return -1;
-+	}
-+
-+	ddesc = ep->dwc_ep.descs;
-+
-+	for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
-+
-+#if defined(PRINT_CFI_DMA_DESCS)
-+		print_desc(ddesc, ep->ep.name, i);
-+#endif
-+		ret += ddesc->status.b.bytes;
-+		ddesc++;
-+	}
-+
-+	if (ret)
-+		CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
-+			 ret);
-+
-+	return ret;
-+}
-+#endif
-+
-+/**
-+ * This function completes the request for the EP. If there are
-+ * additional requests for the EP in the queue they will be started.
-+ */
-+static void complete_ep(dwc_otg_pcd_ep_t * ep)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+	struct device *dev = dwc_otg_pcd_to_dev(ep->pcd);
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	dwc_otg_dev_in_ep_regs_t *in_ep_regs =
-+	    dev_if->in_ep_regs[ep->dwc_ep.num];
-+	deptsiz_data_t deptsiz;
-+	dev_dma_desc_sts_t desc_sts;
-+	dwc_otg_pcd_request_t *req = 0;
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+	uint32_t byte_count = 0;
-+	int is_last = 0;
-+	int i;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
-+		    (ep->dwc_ep.is_in ? "IN" : "OUT"));
-+
-+	/* Get any pending requests */
-+	if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+		req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+		if (!req) {
-+			DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+			return;
-+		}
-+	} else {
-+		DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+		return;
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
-+
-+	if (ep->dwc_ep.is_in) {
-+		deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
-+
-+		if (core_if->dma_enable) {
-+			if (core_if->dma_desc_enable == 0) {
-+				if (deptsiz.b.xfersize == 0
-+				    && deptsiz.b.pktcnt == 0) {
-+					byte_count =
-+					    ep->dwc_ep.xfer_len -
-+					    ep->dwc_ep.xfer_count;
-+
-+					ep->dwc_ep.xfer_buff += byte_count;
-+					ep->dwc_ep.dma_addr += byte_count;
-+					ep->dwc_ep.xfer_count += byte_count;
-+
-+					DWC_DEBUGPL(DBG_PCDV,
-+						    "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
-+						    ep->dwc_ep.num,
-+						    (ep->dwc_ep.
-+						     is_in ? "IN" : "OUT"),
-+						    ep->dwc_ep.xfer_len,
-+						    deptsiz.b.xfersize,
-+						    deptsiz.b.pktcnt);
-+
-+					if (ep->dwc_ep.xfer_len <
-+					    ep->dwc_ep.total_len) {
-+						dwc_otg_ep_start_transfer
-+						    (core_if, &ep->dwc_ep);
-+					} else if (ep->dwc_ep.sent_zlp) {
-+						/*
-+						 * This fragment of code should initiate 0
-+						 * length transfer in case if it is queued
-+						 * a transfer with size divisible to EPs max
-+						 * packet size and with usb_request zero field
-+						 * is set, which means that after data is transfered,
-+						 * it is also should be transfered
-+						 * a 0 length packet at the end. For Slave and
-+						 * Buffer DMA modes in this case SW has
-+						 * to initiate 2 transfers one with transfer size,
-+						 * and the second with 0 size. For Descriptor
-+						 * DMA mode SW is able to initiate a transfer,
-+						 * which will handle all the packets including
-+						 * the last  0 length.
-+						 */
-+						ep->dwc_ep.sent_zlp = 0;
-+						dwc_otg_ep_start_zl_transfer
-+						    (core_if, &ep->dwc_ep);
-+					} else {
-+						is_last = 1;
-+					}
-+				} else {
-+					if (ep->dwc_ep.type ==
-+					    DWC_OTG_EP_TYPE_ISOC) {
-+						req->actual = 0;
-+						dwc_otg_request_done(ep, req, 0);
-+
-+						ep->dwc_ep.start_xfer_buff = 0;
-+						ep->dwc_ep.xfer_buff = 0;
-+						ep->dwc_ep.xfer_len = 0;
-+
-+						/* If there is a request in the queue start it. */
-+						start_next_request(ep);
-+					} else
-+						DWC_WARN
-+						("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
-+						ep->dwc_ep.num,
-+						(ep->dwc_ep.is_in ? "IN" : "OUT"),
-+						deptsiz.b.xfersize,
-+						deptsiz.b.pktcnt);
-+				}
-+			} else {
-+				dma_desc = ep->dwc_ep.desc_addr;
-+				byte_count = 0;
-+				ep->dwc_ep.sent_zlp = 0;
-+
-+#ifdef DWC_UTE_CFI
-+				CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
-+					 ep->dwc_ep.buff_mode);
-+				if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+					int residue;
-+
-+					residue = cfi_calc_desc_residue(ep);
-+					if (residue < 0)
-+						return;
-+
-+					byte_count = residue;
-+				} else {
-+#endif
-+					for (i = 0; i < ep->dwc_ep.desc_cnt;
-+					     ++i) {
-+					desc_sts = dma_desc->status;
-+					byte_count += desc_sts.b.bytes;
-+					dma_desc++;
-+				}
-+#ifdef DWC_UTE_CFI
-+				}
-+#endif
-+				if (byte_count == 0) {
-+					ep->dwc_ep.xfer_count =
-+					    ep->dwc_ep.total_len;
-+					is_last = 1;
-+				} else {
-+					DWC_WARN("Incomplete transfer\n");
-+				}
-+			}
-+		} else {
-+			if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
-+				DWC_DEBUGPL(DBG_PCDV,
-+					    "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
-+					    ep->dwc_ep.num,
-+					    ep->dwc_ep.is_in ? "IN" : "OUT",
-+					    ep->dwc_ep.xfer_len,
-+					    deptsiz.b.xfersize,
-+					    deptsiz.b.pktcnt);
-+
-+				/*      Check if the whole transfer was completed,
-+				 *      if no, setup transfer for next portion of data
-+				 */
-+				if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+					dwc_otg_ep_start_transfer(core_if,
-+								  &ep->dwc_ep);
-+				} else if (ep->dwc_ep.sent_zlp) {
-+					/*
-+					 * This fragment of code should initiate 0
-+					 * length trasfer in case if it is queued
-+					 * a trasfer with size divisible to EPs max
-+					 * packet size and with usb_request zero field
-+					 * is set, which means that after data is transfered,
-+					 * it is also should be transfered
-+					 * a 0 length packet at the end. For Slave and
-+					 * Buffer DMA modes in this case SW has
-+					 * to initiate 2 transfers one with transfer size,
-+					 * and the second with 0 size. For Desriptor
-+					 * DMA mode SW is able to initiate a transfer,
-+					 * which will handle all the packets including
-+					 * the last  0 legth.
-+					 */
-+					ep->dwc_ep.sent_zlp = 0;
-+					dwc_otg_ep_start_zl_transfer(core_if,
-+								     &ep->dwc_ep);
-+				} else {
-+					is_last = 1;
-+				}
-+			} else {
-+				DWC_WARN
-+				    ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
-+				     ep->dwc_ep.num,
-+				     (ep->dwc_ep.is_in ? "IN" : "OUT"),
-+				     deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+			}
-+		}
-+	} else {
-+		dwc_otg_dev_out_ep_regs_t *out_ep_regs =
-+		    dev_if->out_ep_regs[ep->dwc_ep.num];
-+		desc_sts.d32 = 0;
-+		if (core_if->dma_enable) {
-+			if (core_if->dma_desc_enable) {
-+				dma_desc = ep->dwc_ep.desc_addr;
-+				byte_count = 0;
-+				ep->dwc_ep.sent_zlp = 0;
-+
-+#ifdef DWC_UTE_CFI
-+				CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
-+					 ep->dwc_ep.buff_mode);
-+				if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+					int residue;
-+					residue = cfi_calc_desc_residue(ep);
-+					if (residue < 0)
-+						return;
-+					byte_count = residue;
-+				} else {
-+#endif
-+
-+					for (i = 0; i < ep->dwc_ep.desc_cnt;
-+					     ++i) {
-+						desc_sts = dma_desc->status;
-+						byte_count += desc_sts.b.bytes;
-+						dma_desc++;
-+					}
-+
-+#ifdef DWC_UTE_CFI
-+				}
-+#endif
-+				/* Checking for interrupt Out transfers with not
-+				 * dword aligned mps sizes
-+				 */
-+				if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
-+							(ep->dwc_ep.maxpacket%4)) {
-+					ep->dwc_ep.xfer_count =
-+					    ep->dwc_ep.total_len - byte_count;
-+					if ((ep->dwc_ep.xfer_len %
-+					     ep->dwc_ep.maxpacket)
-+					    && (ep->dwc_ep.xfer_len /
-+						ep->dwc_ep.maxpacket <
-+						MAX_DMA_DESC_CNT))
-+						ep->dwc_ep.xfer_len -=
-+						    (ep->dwc_ep.desc_cnt -
-+						     1) * ep->dwc_ep.maxpacket +
-+						    ep->dwc_ep.xfer_len %
-+						    ep->dwc_ep.maxpacket;
-+					else
-+						ep->dwc_ep.xfer_len -=
-+						    ep->dwc_ep.desc_cnt *
-+						    ep->dwc_ep.maxpacket;
-+					if (ep->dwc_ep.xfer_len > 0) {
-+						dwc_otg_ep_start_transfer
-+						    (core_if, &ep->dwc_ep);
-+					} else {
-+						is_last = 1;
-+					}
-+				} else {
-+					ep->dwc_ep.xfer_count =
-+					    ep->dwc_ep.total_len - byte_count +
-+					    ((4 -
-+					      (ep->dwc_ep.
-+					       total_len & 0x3)) & 0x3);
-+					is_last = 1;
-+				}
-+			} else {
-+				deptsiz.d32 = 0;
-+				deptsiz.d32 =
-+				    DWC_READ_REG32(&out_ep_regs->doeptsiz);
-+
-+				byte_count = (ep->dwc_ep.xfer_len -
-+					      ep->dwc_ep.xfer_count -
-+					      deptsiz.b.xfersize);
-+				ep->dwc_ep.xfer_buff += byte_count;
-+				ep->dwc_ep.dma_addr += byte_count;
-+				ep->dwc_ep.xfer_count += byte_count;
-+
-+				/*      Check if the whole transfer was completed,
-+				 *      if no, setup transfer for next portion of data
-+				 */
-+				if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+					dwc_otg_ep_start_transfer(core_if,
-+								  &ep->dwc_ep);
-+				} else if (ep->dwc_ep.sent_zlp) {
-+					/*
-+					 * This fragment of code should initiate 0
-+					 * length trasfer in case if it is queued
-+					 * a trasfer with size divisible to EPs max
-+					 * packet size and with usb_request zero field
-+					 * is set, which means that after data is transfered,
-+					 * it is also should be transfered
-+					 * a 0 length packet at the end. For Slave and
-+					 * Buffer DMA modes in this case SW has
-+					 * to initiate 2 transfers one with transfer size,
-+					 * and the second with 0 size. For Desriptor
-+					 * DMA mode SW is able to initiate a transfer,
-+					 * which will handle all the packets including
-+					 * the last  0 legth.
-+					 */
-+					ep->dwc_ep.sent_zlp = 0;
-+					dwc_otg_ep_start_zl_transfer(core_if,
-+								     &ep->dwc_ep);
-+				} else {
-+					is_last = 1;
-+				}
-+			}
-+		} else {
-+			/*      Check if the whole transfer was completed,
-+			 *      if no, setup transfer for next portion of data
-+			 */
-+			if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
-+				dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
-+			} else if (ep->dwc_ep.sent_zlp) {
-+				/*
-+				 * This fragment of code should initiate 0
-+				 * length transfer in case if it is queued
-+				 * a transfer with size divisible to EPs max
-+				 * packet size and with usb_request zero field
-+				 * is set, which means that after data is transfered,
-+				 * it is also should be transfered
-+				 * a 0 length packet at the end. For Slave and
-+				 * Buffer DMA modes in this case SW has
-+				 * to initiate 2 transfers one with transfer size,
-+				 * and the second with 0 size. For Descriptor
-+				 * DMA mode SW is able to initiate a transfer,
-+				 * which will handle all the packets including
-+				 * the last  0 length.
-+				 */
-+				ep->dwc_ep.sent_zlp = 0;
-+				dwc_otg_ep_start_zl_transfer(core_if,
-+							     &ep->dwc_ep);
-+			} else {
-+				is_last = 1;
-+			}
-+		}
-+
-+		DWC_DEBUGPL(DBG_PCDV,
-+			    "addr %p,	 %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
-+			    &out_ep_regs->doeptsiz, ep->dwc_ep.num,
-+			    ep->dwc_ep.is_in ? "IN" : "OUT",
-+			    ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
-+			    deptsiz.b.xfersize, deptsiz.b.pktcnt);
-+	}
-+
-+	/* Complete the request */
-+	if (is_last) {
-+#ifdef DWC_UTE_CFI
-+		if (ep->dwc_ep.buff_mode != BM_STANDARD) {
-+			req->actual = ep->dwc_ep.cfi_req_len - byte_count;
-+		} else {
-+#endif
-+			req->actual = ep->dwc_ep.xfer_count;
-+#ifdef DWC_UTE_CFI
-+		}
-+#endif
-+		if (req->dw_align_buf) {
-+			if (!ep->dwc_ep.is_in) {
-+				dwc_memcpy(req->buf, req->dw_align_buf, req->length);
-+			}
-+			DWC_DMA_FREE(dev, req->length, req->dw_align_buf,
-+				     req->dw_align_buf_dma);
-+		}
-+
-+		dwc_otg_request_done(ep, req, 0);
-+
-+		ep->dwc_ep.start_xfer_buff = 0;
-+		ep->dwc_ep.xfer_buff = 0;
-+		ep->dwc_ep.xfer_len = 0;
-+
-+		/* If there is a request in the queue start it. */
-+		start_next_request(ep);
-+	}
-+}
-+
-+#ifdef DWC_EN_ISOC
-+
-+/**
-+ * This function BNA interrupt for Isochronous EPs
-+ *
-+ */
-+static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
-+{
-+	dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+	volatile uint32_t *addr;
-+	depctl_data_t depctl = {.d32 = 0 };
-+	dwc_otg_pcd_t *pcd = ep->pcd;
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+	int i;
-+
-+	dma_desc =
-+	    dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
-+
-+	if (dwc_ep->is_in) {
-+		dev_dma_desc_sts_t sts = {.d32 = 0 };
-+		for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+			sts.d32 = dma_desc->status.d32;
-+			sts.b_iso_in.bs = BS_HOST_READY;
-+			dma_desc->status.d32 = sts.d32;
-+		}
-+	} else {
-+		dev_dma_desc_sts_t sts = {.d32 = 0 };
-+		for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+			sts.d32 = dma_desc->status.d32;
-+			sts.b_iso_out.bs = BS_HOST_READY;
-+			dma_desc->status.d32 = sts.d32;
-+		}
-+	}
-+
-+	if (dwc_ep->is_in == 0) {
-+		addr =
-+		    &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
-+							   num]->doepctl;
-+	} else {
-+		addr =
-+		    &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+	}
-+	depctl.b.epena = 1;
-+	DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
-+}
-+
-+/**
-+ * This function sets latest iso packet information(non-PTI mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	deptsiz_data_t deptsiz = {.d32 = 0 };
-+	dma_addr_t dma_addr;
-+	uint32_t offset;
-+
-+	if (ep->proc_buf_num)
-+		dma_addr = ep->dma_addr1;
-+	else
-+		dma_addr = ep->dma_addr0;
-+
-+	if (ep->is_in) {
-+		deptsiz.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->
-+				   in_ep_regs[ep->num]->dieptsiz);
-+		offset = ep->data_per_frame;
-+	} else {
-+		deptsiz.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->
-+				   out_ep_regs[ep->num]->doeptsiz);
-+		offset =
-+		    ep->data_per_frame +
-+		    (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
-+	}
-+
-+	if (!deptsiz.b.xfersize) {
-+		ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
-+		ep->pkt_info[ep->cur_pkt].offset =
-+		    ep->cur_pkt_dma_addr - dma_addr;
-+		ep->pkt_info[ep->cur_pkt].status = 0;
-+	} else {
-+		ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
-+		ep->pkt_info[ep->cur_pkt].offset =
-+		    ep->cur_pkt_dma_addr - dma_addr;
-+		ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
-+	}
-+	ep->cur_pkt_addr += offset;
-+	ep->cur_pkt_dma_addr += offset;
-+	ep->cur_pkt++;
-+}
-+
-+/**
-+ * This function sets latest iso packet information(DDMA mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
-+				   dwc_ep_t * dwc_ep)
-+{
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+	dev_dma_desc_sts_t sts = {.d32 = 0 };
-+	iso_pkt_info_t *iso_packet;
-+	uint32_t data_per_desc;
-+	uint32_t offset;
-+	int i, j;
-+
-+	iso_packet = dwc_ep->pkt_info;
-+
-+	/** Reinit closed DMA Descriptors*/
-+	/** ISO OUT EP */
-+	if (dwc_ep->is_in == 0) {
-+		dma_desc =
-+		    dwc_ep->iso_desc_addr +
-+		    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+		offset = 0;
-+
-+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+		     i += dwc_ep->pkt_per_frm) {
-+			for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+				data_per_desc =
-+				    ((j + 1) * dwc_ep->maxpacket >
-+				     dwc_ep->
-+				     data_per_frame) ? dwc_ep->data_per_frame -
-+				    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+				data_per_desc +=
-+				    (data_per_desc % 4) ? (4 -
-+							   data_per_desc %
-+							   4) : 0;
-+
-+				sts.d32 = dma_desc->status.d32;
-+
-+				/* Write status in iso_packet_decsriptor  */
-+				iso_packet->status =
-+				    sts.b_iso_out.rxsts +
-+				    (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+				if (iso_packet->status) {
-+					iso_packet->status = -DWC_E_NO_DATA;
-+				}
-+
-+				/* Received data length */
-+				if (!sts.b_iso_out.rxbytes) {
-+					iso_packet->length =
-+					    data_per_desc -
-+					    sts.b_iso_out.rxbytes;
-+				} else {
-+					iso_packet->length =
-+					    data_per_desc -
-+					    sts.b_iso_out.rxbytes + (4 -
-+								     dwc_ep->data_per_frame
-+								     % 4);
-+				}
-+
-+				iso_packet->offset = offset;
-+
-+				offset += data_per_desc;
-+				dma_desc++;
-+				iso_packet++;
-+			}
-+		}
-+
-+		for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+			data_per_desc =
-+			    ((j + 1) * dwc_ep->maxpacket >
-+			     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+			    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+			data_per_desc +=
-+			    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+
-+			sts.d32 = dma_desc->status.d32;
-+
-+			/* Write status in iso_packet_decsriptor  */
-+			iso_packet->status =
-+			    sts.b_iso_out.rxsts +
-+			    (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+			if (iso_packet->status) {
-+				iso_packet->status = -DWC_E_NO_DATA;
-+			}
-+
-+			/* Received data length */
-+			iso_packet->length =
-+			    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
-+
-+			iso_packet->offset = offset;
-+
-+			offset += data_per_desc;
-+			iso_packet++;
-+			dma_desc++;
-+		}
-+
-+		sts.d32 = dma_desc->status.d32;
-+
-+		/* Write status in iso_packet_decsriptor  */
-+		iso_packet->status =
-+		    sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
-+		if (iso_packet->status) {
-+			iso_packet->status = -DWC_E_NO_DATA;
-+		}
-+		/* Received data length */
-+		if (!sts.b_iso_out.rxbytes) {
-+			iso_packet->length =
-+			    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
-+		} else {
-+			iso_packet->length =
-+			    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
-+			    (4 - dwc_ep->data_per_frame % 4);
-+		}
-+
-+		iso_packet->offset = offset;
-+	} else {
-+/** ISO IN EP */
-+
-+		dma_desc =
-+		    dwc_ep->iso_desc_addr +
-+		    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+		for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+			sts.d32 = dma_desc->status.d32;
-+
-+			/* Write status in iso packet descriptor */
-+			iso_packet->status =
-+			    sts.b_iso_in.txsts +
-+			    (sts.b_iso_in.bs ^ BS_DMA_DONE);
-+			if (iso_packet->status != 0) {
-+				iso_packet->status = -DWC_E_NO_DATA;
-+
-+			}
-+			/* Bytes has been transfered */
-+			iso_packet->length =
-+			    dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
-+
-+			dma_desc++;
-+			iso_packet++;
-+		}
-+
-+		sts.d32 = dma_desc->status.d32;
-+		while (sts.b_iso_in.bs == BS_DMA_BUSY) {
-+			sts.d32 = dma_desc->status.d32;
-+		}
-+
-+		/* Write status in iso packet descriptor ??? do be done with ERROR codes */
-+		iso_packet->status =
-+		    sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
-+		if (iso_packet->status != 0) {
-+			iso_packet->status = -DWC_E_NO_DATA;
-+		}
-+
-+		/* Bytes has been transfered */
-+		iso_packet->length =
-+		    dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
-+	}
-+}
-+
-+/**
-+ * This function reinitialize DMA Descriptors for Isochronous transfer
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP to start the transfer on.
-+ *
-+ */
-+static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
-+{
-+	int i, j;
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+	dma_addr_t dma_ad;
-+	volatile uint32_t *addr;
-+	dev_dma_desc_sts_t sts = {.d32 = 0 };
-+	uint32_t data_per_desc;
-+
-+	if (dwc_ep->is_in == 0) {
-+		addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
-+	} else {
-+		addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+	}
-+
-+	if (dwc_ep->proc_buf_num == 0) {
-+		/** Buffer 0 descriptors setup */
-+		dma_ad = dwc_ep->dma_addr0;
-+	} else {
-+		/** Buffer 1 descriptors setup */
-+		dma_ad = dwc_ep->dma_addr1;
-+	}
-+
-+	/** Reinit closed DMA Descriptors*/
-+	/** ISO OUT EP */
-+	if (dwc_ep->is_in == 0) {
-+		dma_desc =
-+		    dwc_ep->iso_desc_addr +
-+		    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+		sts.b_iso_out.bs = BS_HOST_READY;
-+		sts.b_iso_out.rxsts = 0;
-+		sts.b_iso_out.l = 0;
-+		sts.b_iso_out.sp = 0;
-+		sts.b_iso_out.ioc = 0;
-+		sts.b_iso_out.pid = 0;
-+		sts.b_iso_out.framenum = 0;
-+
-+		for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
-+		     i += dwc_ep->pkt_per_frm) {
-+			for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
-+				data_per_desc =
-+				    ((j + 1) * dwc_ep->maxpacket >
-+				     dwc_ep->
-+				     data_per_frame) ? dwc_ep->data_per_frame -
-+				    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+				data_per_desc +=
-+				    (data_per_desc % 4) ? (4 -
-+							   data_per_desc %
-+							   4) : 0;
-+				sts.b_iso_out.rxbytes = data_per_desc;
-+				dma_desc->buf = dma_ad;
-+				dma_desc->status.d32 = sts.d32;
-+
-+				dma_ad += data_per_desc;
-+				dma_desc++;
-+			}
-+		}
-+
-+		for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
-+
-+			data_per_desc =
-+			    ((j + 1) * dwc_ep->maxpacket >
-+			     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+			    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+			data_per_desc +=
-+			    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+			sts.b_iso_out.rxbytes = data_per_desc;
-+
-+			dma_desc->buf = dma_ad;
-+			dma_desc->status.d32 = sts.d32;
-+
-+			dma_desc++;
-+			dma_ad += data_per_desc;
-+		}
-+
-+		sts.b_iso_out.ioc = 1;
-+		sts.b_iso_out.l = dwc_ep->proc_buf_num;
-+
-+		data_per_desc =
-+		    ((j + 1) * dwc_ep->maxpacket >
-+		     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
-+		    j * dwc_ep->maxpacket : dwc_ep->maxpacket;
-+		data_per_desc +=
-+		    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
-+		sts.b_iso_out.rxbytes = data_per_desc;
-+
-+		dma_desc->buf = dma_ad;
-+		dma_desc->status.d32 = sts.d32;
-+	} else {
-+/** ISO IN EP */
-+
-+		dma_desc =
-+		    dwc_ep->iso_desc_addr +
-+		    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
-+
-+		sts.b_iso_in.bs = BS_HOST_READY;
-+		sts.b_iso_in.txsts = 0;
-+		sts.b_iso_in.sp = 0;
-+		sts.b_iso_in.ioc = 0;
-+		sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
-+		sts.b_iso_in.framenum = dwc_ep->next_frame;
-+		sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
-+		sts.b_iso_in.l = 0;
-+
-+		for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
-+			dma_desc->buf = dma_ad;
-+			dma_desc->status.d32 = sts.d32;
-+
-+			sts.b_iso_in.framenum += dwc_ep->bInterval;
-+			dma_ad += dwc_ep->data_per_frame;
-+			dma_desc++;
-+		}
-+
-+		sts.b_iso_in.ioc = 1;
-+		sts.b_iso_in.l = dwc_ep->proc_buf_num;
-+
-+		dma_desc->buf = dma_ad;
-+		dma_desc->status.d32 = sts.d32;
-+
-+		dwc_ep->next_frame =
-+		    sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
-+	}
-+	dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+}
-+
-+/**
-+ * This function is to handle Iso EP transfer complete interrupt
-+ * in case Iso out packet was dropped
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param dwc_ep The EP for wihich transfer complete was asserted
-+ *
-+ */
-+static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
-+					   dwc_ep_t * dwc_ep)
-+{
-+	uint32_t dma_addr;
-+	uint32_t drp_pkt;
-+	uint32_t drp_pkt_cnt;
-+	deptsiz_data_t deptsiz = {.d32 = 0 };
-+	depctl_data_t depctl = {.d32 = 0 };
-+	int i;
-+
-+	deptsiz.d32 =
-+	    DWC_READ_REG32(&core_if->dev_if->
-+			   out_ep_regs[dwc_ep->num]->doeptsiz);
-+
-+	drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
-+	drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
-+
-+	/* Setting dropped packets status */
-+	for (i = 0; i < drp_pkt_cnt; ++i) {
-+		dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
-+		drp_pkt++;
-+		deptsiz.b.pktcnt--;
-+	}
-+
-+	if (deptsiz.b.pktcnt > 0) {
-+		deptsiz.b.xfersize =
-+		    dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
-+					deptsiz.b.pktcnt) * dwc_ep->maxpacket;
-+	} else {
-+		deptsiz.b.xfersize = 0;
-+		deptsiz.b.pktcnt = 0;
-+	}
-+
-+	DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
-+			deptsiz.d32);
-+
-+	if (deptsiz.b.pktcnt > 0) {
-+		if (dwc_ep->proc_buf_num) {
-+			dma_addr =
-+			    dwc_ep->dma_addr1 + dwc_ep->xfer_len -
-+			    deptsiz.b.xfersize;
-+		} else {
-+			dma_addr =
-+			    dwc_ep->dma_addr0 + dwc_ep->xfer_len -
-+			    deptsiz.b.xfersize;;
-+		}
-+
-+		DWC_WRITE_REG32(&core_if->dev_if->
-+				out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
-+
-+		/** Re-enable endpoint, clear nak  */
-+		depctl.d32 = 0;
-+		depctl.b.epena = 1;
-+		depctl.b.cnak = 1;
-+
-+		DWC_MODIFY_REG32(&core_if->dev_if->
-+				 out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
-+				 depctl.d32);
-+		return 0;
-+	} else {
-+		return 1;
-+	}
-+}
-+
-+/**
-+ * This function sets iso packets information(PTI mode)
-+ *
-+ * @param core_if Programming view of DWC_otg controller.
-+ * @param ep The EP to start the transfer on.
-+ *
-+ */
-+static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
-+{
-+	int i, j;
-+	dma_addr_t dma_ad;
-+	iso_pkt_info_t *packet_info = ep->pkt_info;
-+	uint32_t offset;
-+	uint32_t frame_data;
-+	deptsiz_data_t deptsiz;
-+
-+	if (ep->proc_buf_num == 0) {
-+		/** Buffer 0 descriptors setup */
-+		dma_ad = ep->dma_addr0;
-+	} else {
-+		/** Buffer 1 descriptors setup */
-+		dma_ad = ep->dma_addr1;
-+	}
-+
-+	if (ep->is_in) {
-+		deptsiz.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
-+				   dieptsiz);
-+	} else {
-+		deptsiz.d32 =
-+		    DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
-+				   doeptsiz);
-+	}
-+
-+	if (!deptsiz.b.xfersize) {
-+		offset = 0;
-+		for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
-+			frame_data = ep->data_per_frame;
-+			for (j = 0; j < ep->pkt_per_frm; ++j) {
-+
-+				/* Packet status - is not set as initially
-+				 * it is set to 0 and if packet was sent
-+				 successfully, status field will remain 0*/
-+
-+				/* Bytes has been transfered */
-+				packet_info->length =
-+				    (ep->maxpacket <
-+				     frame_data) ? ep->maxpacket : frame_data;
-+
-+				/* Received packet offset */
-+				packet_info->offset = offset;
-+				offset += packet_info->length;
-+				frame_data -= packet_info->length;
-+
-+				packet_info++;
-+			}
-+		}
-+		return 1;
-+	} else {
-+		/* This is a workaround for in case of Transfer Complete with
-+		 * PktDrpSts interrupts merging - in this case Transfer complete
-+		 * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
-+		 * set and with DOEPTSIZ register non zero. Investigations showed,
-+		 * that this happens when Out packet is dropped, but because of
-+		 * interrupts merging during first interrupt handling PktDrpSts
-+		 * bit is cleared and for next merged interrupts it is not reset.
-+		 * In this case SW hadles the interrupt as if PktDrpSts bit is set.
-+		 */
-+		if (ep->is_in) {
-+			return 1;
-+		} else {
-+			return handle_iso_out_pkt_dropped(core_if, ep);
-+		}
-+	}
-+}
-+
-+/**
-+ * This function is to handle Iso EP transfer complete interrupt
-+ *
-+ * @param pcd The PCD
-+ * @param ep The EP for which transfer complete was asserted
-+ *
-+ */
-+static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
-+	dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+	uint8_t is_last = 0;
-+
-+	if (ep->dwc_ep.next_frame == 0xffffffff) {
-+		DWC_WARN("Next frame is not set!\n");
-+		return;
-+	}
-+
-+	if (core_if->dma_enable) {
-+		if (core_if->dma_desc_enable) {
-+			set_ddma_iso_pkts_info(core_if, dwc_ep);
-+			reinit_ddma_iso_xfer(core_if, dwc_ep);
-+			is_last = 1;
-+		} else {
-+			if (core_if->pti_enh_enable) {
-+				if (set_iso_pkts_info(core_if, dwc_ep)) {
-+					dwc_ep->proc_buf_num =
-+					    (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+					dwc_otg_iso_ep_start_buf_transfer
-+					    (core_if, dwc_ep);
-+					is_last = 1;
-+				}
-+			} else {
-+				set_current_pkt_info(core_if, dwc_ep);
-+				if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+					is_last = 1;
-+					dwc_ep->cur_pkt = 0;
-+					dwc_ep->proc_buf_num =
-+					    (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+					if (dwc_ep->proc_buf_num) {
-+						dwc_ep->cur_pkt_addr =
-+						    dwc_ep->xfer_buff1;
-+						dwc_ep->cur_pkt_dma_addr =
-+						    dwc_ep->dma_addr1;
-+					} else {
-+						dwc_ep->cur_pkt_addr =
-+						    dwc_ep->xfer_buff0;
-+						dwc_ep->cur_pkt_dma_addr =
-+						    dwc_ep->dma_addr0;
-+					}
-+
-+				}
-+				dwc_otg_iso_ep_start_frm_transfer(core_if,
-+								  dwc_ep);
-+			}
-+		}
-+	} else {
-+		set_current_pkt_info(core_if, dwc_ep);
-+		if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+			is_last = 1;
-+			dwc_ep->cur_pkt = 0;
-+			dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+			if (dwc_ep->proc_buf_num) {
-+				dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
-+				dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
-+			} else {
-+				dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
-+				dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
-+			}
-+
-+		}
-+		dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
-+	}
-+	if (is_last)
-+		dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+/**
-+ * This function handle BNA interrupt for Non Isochronous EPs
-+ *
-+ */
-+static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
-+{
-+	dwc_ep_t *dwc_ep = &ep->dwc_ep;
-+	volatile uint32_t *addr;
-+	depctl_data_t depctl = {.d32 = 0 };
-+	dwc_otg_pcd_t *pcd = ep->pcd;
-+	dwc_otg_dev_dma_desc_t *dma_desc;
-+	dev_dma_desc_sts_t sts = {.d32 = 0 };
-+	dwc_otg_core_if_t *core_if = ep->pcd->core_if;
-+	int i, start;
-+
-+	if (!dwc_ep->desc_cnt)
-+		DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
-+			 (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
-+
-+	if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
-+							&& dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
-+		uint32_t doepdma;
-+		dwc_otg_dev_out_ep_regs_t *out_regs =
-+			core_if->dev_if->out_ep_regs[dwc_ep->num];
-+		doepdma = DWC_READ_REG32(&(out_regs->doepdma));
-+		start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
-+		dma_desc = &(dwc_ep->desc_addr[start]);
-+	} else {
-+		start = 0;
-+		dma_desc = dwc_ep->desc_addr;
-+	}
-+
-+
-+	for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
-+		sts.d32 = dma_desc->status.d32;
-+		sts.b.bs = BS_HOST_READY;
-+		dma_desc->status.d32 = sts.d32;
-+	}
-+
-+	if (dwc_ep->is_in == 0) {
-+		addr =
-+		    &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
-+		    doepctl;
-+	} else {
-+		addr =
-+		    &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
-+	}
-+	depctl.b.epena = 1;
-+	depctl.b.cnak = 1;
-+	DWC_MODIFY_REG32(addr, 0, depctl.d32);
-+}
-+
-+/**
-+ * This function handles EP0 Control transfers.
-+ *
-+ * The state of the control transfers are tracked in
-+ * <code>ep0state</code>.
-+ */
-+static void handle_ep0(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
-+	dev_dma_desc_sts_t desc_sts;
-+	deptsiz0_data_t deptsiz;
-+	uint32_t byte_count;
-+
-+#ifdef DEBUG_EP0
-+	DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
-+	print_ep0_state(pcd);
-+#endif
-+
-+//      DWC_PRINTF("HANDLE EP0\n");
-+
-+	switch (pcd->ep0state) {
-+	case EP0_DISCONNECT:
-+		break;
-+
-+	case EP0_IDLE:
-+		pcd->request_config = 0;
-+
-+		pcd_setup(pcd);
-+		break;
-+
-+	case EP0_IN_DATA_PHASE:
-+#ifdef DEBUG_EP0
-+		DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
-+			    ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
-+			    ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
-+#endif
-+
-+		if (core_if->dma_enable != 0) {
-+			/*
-+			 * For EP0 we can only program 1 packet at a time so we
-+			 * need to do the make calculations after each complete.
-+			 * Call write_packet to make the calculations, as in
-+			 * slave mode, and use those values to determine if we
-+			 * can complete.
-+			 */
-+			if (core_if->dma_desc_enable == 0) {
-+				deptsiz.d32 =
-+				    DWC_READ_REG32(&core_if->
-+						   dev_if->in_ep_regs[0]->
-+						   dieptsiz);
-+				byte_count =
-+				    ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
-+			} else {
-+				desc_sts =
-+				    core_if->dev_if->in_desc_addr->status;
-+				byte_count =
-+				    ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
-+			}
-+			ep0->dwc_ep.xfer_count += byte_count;
-+			ep0->dwc_ep.xfer_buff += byte_count;
-+			ep0->dwc_ep.dma_addr += byte_count;
-+		}
-+		if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
-+			dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+						      &ep0->dwc_ep);
-+			DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
-+		} else if (ep0->dwc_ep.sent_zlp) {
-+			dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+						      &ep0->dwc_ep);
-+			ep0->dwc_ep.sent_zlp = 0;
-+			DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
-+		} else {
-+			ep0_complete_request(ep0);
-+			DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
-+		}
-+		break;
-+	case EP0_OUT_DATA_PHASE:
-+#ifdef DEBUG_EP0
-+		DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
-+			    ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
-+			    ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
-+#endif
-+		if (core_if->dma_enable != 0) {
-+			if (core_if->dma_desc_enable == 0) {
-+				deptsiz.d32 =
-+				    DWC_READ_REG32(&core_if->
-+						   dev_if->out_ep_regs[0]->
-+						   doeptsiz);
-+				byte_count =
-+				    ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
-+			} else {
-+				desc_sts =
-+				    core_if->dev_if->out_desc_addr->status;
-+				byte_count =
-+				    ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
-+			}
-+			ep0->dwc_ep.xfer_count += byte_count;
-+			ep0->dwc_ep.xfer_buff += byte_count;
-+			ep0->dwc_ep.dma_addr += byte_count;
-+		}
-+		if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
-+			dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+						      &ep0->dwc_ep);
-+			DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
-+		} else if (ep0->dwc_ep.sent_zlp) {
-+			dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
-+						      &ep0->dwc_ep);
-+			ep0->dwc_ep.sent_zlp = 0;
-+			DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
-+		} else {
-+			ep0_complete_request(ep0);
-+			DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
-+		}
-+		break;
-+
-+	case EP0_IN_STATUS_PHASE:
-+	case EP0_OUT_STATUS_PHASE:
-+		DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
-+		ep0_complete_request(ep0);
-+		pcd->ep0state = EP0_IDLE;
-+		ep0->stopped = 1;
-+		ep0->dwc_ep.is_in = 0;	/* OUT for next SETUP */
-+
-+		/* Prepare for more SETUP Packets */
-+		if (core_if->dma_enable) {
-+			ep0_out_start(core_if, pcd);
-+		}
-+		break;
-+
-+	case EP0_STALL:
-+		DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
-+		break;
-+	}
-+#ifdef DEBUG_EP0
-+	print_ep0_state(pcd);
-+#endif
-+}
-+
-+/**
-+ * Restart transfer
-+ */
-+static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
-+{
-+	dwc_otg_core_if_t *core_if;
-+	dwc_otg_dev_if_t *dev_if;
-+	deptsiz_data_t dieptsiz = {.d32 = 0 };
-+	dwc_otg_pcd_ep_t *ep;
-+
-+	ep = get_in_ep(pcd, epnum);
-+
-+#ifdef DWC_EN_ISOC
-+	if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+		return;
-+	}
-+#endif /* DWC_EN_ISOC  */
-+
-+	core_if = GET_CORE_IF(pcd);
-+	dev_if = core_if->dev_if;
-+
-+	dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
-+
-+	DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
-+		    " stopped=%d\n", ep->dwc_ep.xfer_buff,
-+		    ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
-+	/*
-+	 * If xfersize is 0 and pktcnt in not 0, resend the last packet.
-+	 */
-+	if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
-+	    ep->dwc_ep.start_xfer_buff != 0) {
-+		if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
-+			ep->dwc_ep.xfer_count = 0;
-+			ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
-+			ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
-+		} else {
-+			ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
-+			/* convert packet size to dwords. */
-+			ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
-+			ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
-+		}
-+		ep->stopped = 0;
-+		DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
-+			    "xfer_len=%0x stopped=%d\n",
-+			    ep->dwc_ep.xfer_buff,
-+			    ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
-+			    ep->stopped);
-+		if (epnum == 0) {
-+			dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
-+		} else {
-+			dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
-+		}
-+	}
-+}
-+
-+/*
-+ * This function create new nextep sequnce based on Learn Queue.
-+ *
-+ * @param core_if Programming view of DWC_otg controller
-+ */
-+void predict_nextep_seq( dwc_otg_core_if_t * core_if)
-+{
-+	dwc_otg_device_global_regs_t *dev_global_regs =
-+	    core_if->dev_if->dev_global_regs;
-+	const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
-+	/* Number of Token Queue Registers */
-+	const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
-+	dtknq1_data_t dtknqr1;
-+	uint32_t in_tkn_epnums[4];
-+	uint8_t seqnum[MAX_EPS_CHANNELS];
-+	uint8_t intkn_seq[TOKEN_Q_DEPTH];
-+	grstctl_t resetctl = {.d32 = 0 };
-+	uint8_t temp;
-+	int ndx = 0;
-+	int start = 0;
-+	int end = 0;
-+	int sort_done = 0;
-+	int i = 0;
-+	volatile uint32_t *addr = &dev_global_regs->dtknqr1;
-+
-+
-+	DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
-+
-+	/* Read the DTKNQ Registers */
-+	for (i = 0; i < DTKNQ_REG_CNT; i++) {
-+		in_tkn_epnums[i] = DWC_READ_REG32(addr);
-+		DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
-+			    in_tkn_epnums[i]);
-+		if (addr == &dev_global_regs->dvbusdis) {
-+			addr = &dev_global_regs->dtknqr3_dthrctl;
-+		} else {
-+			++addr;
-+		}
-+
-+	}
-+
-+	/* Copy the DTKNQR1 data to the bit field. */
-+	dtknqr1.d32 = in_tkn_epnums[0];
-+	if (dtknqr1.b.wrap_bit) {
-+		ndx = dtknqr1.b.intknwptr;
-+		end = ndx -1;
-+		if (end < 0)
-+			end = TOKEN_Q_DEPTH -1;
-+	} else {
-+		ndx = 0;
-+		end = dtknqr1.b.intknwptr -1;
-+		if (end < 0)
-+			end = 0;
-+	}
-+	start = ndx;
-+
-+	/* Fill seqnum[] by initial values: EP number + 31 */
-+	for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+		seqnum[i] = i +31;
-+	}
-+
-+	/* Fill intkn_seq[] from in_tkn_epnums[0] */
-+	for (i=0; i < 6; i++)
-+		intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
-+
-+	if (TOKEN_Q_DEPTH > 6) {
-+		/* Fill intkn_seq[] from in_tkn_epnums[1] */
-+		for (i=6; i < 14; i++)
-+			intkn_seq[i] =
-+			    (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
-+	}
-+
-+	if (TOKEN_Q_DEPTH > 14) {
-+		/* Fill intkn_seq[] from in_tkn_epnums[1] */
-+		for (i=14; i < 22; i++)
-+			intkn_seq[i] =
-+			    (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
-+	}
-+
-+	if (TOKEN_Q_DEPTH > 22) {
-+		/* Fill intkn_seq[] from in_tkn_epnums[1] */
-+		for (i=22; i < 30; i++)
-+			intkn_seq[i] =
-+			    (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
-+		    start, end);
-+	for (i=0; i<TOKEN_Q_DEPTH; i++)
-+		DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
-+
-+	/* Update seqnum based on intkn_seq[] */
-+	i = 0;
-+	do {
-+		seqnum[intkn_seq[ndx]] = i;
-+		ndx++;
-+		i++;
-+		if (ndx == TOKEN_Q_DEPTH)
-+			ndx = 0;
-+	} while ( i < TOKEN_Q_DEPTH );
-+
-+	/* Mark non active EP's in seqnum[] by 0xff */
-+	for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
-+		if (core_if->nextep_seq[i] == 0xff )
-+			seqnum[i] = 0xff;
-+	}
-+
-+	/* Sort seqnum[] */
-+	sort_done = 0;
-+	while (!sort_done) {
-+		sort_done = 1;
-+		for (i=0; i<core_if->dev_if->num_in_eps; i++) {
-+			if (seqnum[i] > seqnum[i+1]) {
-+				temp = seqnum[i];
-+				seqnum[i] = seqnum[i+1];
-+				seqnum[i+1] = temp;
-+				sort_done = 0;
-+			}
-+		}
-+	}
-+
-+	ndx = start + seqnum[0];
-+	if (ndx >= TOKEN_Q_DEPTH)
-+		ndx = ndx % TOKEN_Q_DEPTH;
-+	core_if->first_in_nextep_seq = intkn_seq[ndx];
-+
-+	/* Update seqnum[] by EP numbers  */
-+	for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
-+		ndx = start + i;
-+		if (seqnum[i] < 31) {
-+			ndx = start + seqnum[i];
-+			if (ndx >= TOKEN_Q_DEPTH)
-+				ndx = ndx % TOKEN_Q_DEPTH;
-+			seqnum[i] = intkn_seq[ndx];
-+		} else {
-+			if (seqnum[i] < 0xff) {
-+				seqnum[i] = seqnum[i] - 31;
-+			} else {
-+				break;
-+			}
-+		}
-+	}
-+
-+	/* Update nextep_seq[] based on seqnum[] */
-+	for (i=0; i<core_if->dev_if->num_in_eps; i++) {
-+		if (seqnum[i] != 0xff) {
-+			if (seqnum[i+1] != 0xff) {
-+				core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
-+			} else {
-+				core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
-+				break;
-+			}
-+		} else {
-+			break;
-+		}
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
-+		__func__, core_if->first_in_nextep_seq);
-+	for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
-+		DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
-+	}
-+
-+	/* Flush the Learning Queue */
-+	resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
-+	resetctl.b.intknqflsh = 1;
-+	DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
-+
-+
-+}
-+
-+/**
-+ * handle the IN EP disable interrupt.
-+ */
-+static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
-+					     const uint32_t epnum)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	deptsiz_data_t dieptsiz = {.d32 = 0 };
-+	dctl_data_t dctl = {.d32 = 0 };
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_ep_t *dwc_ep;
-+	gintmsk_data_t gintmsk_data;
-+	depctl_data_t depctl;
-+	uint32_t diepdma;
-+	uint32_t remain_to_transfer = 0;
-+	uint8_t i;
-+	uint32_t xfer_size;
-+
-+	ep = get_in_ep(pcd, epnum);
-+	dwc_ep = &ep->dwc_ep;
-+
-+	if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+		dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
-+		complete_ep(ep);
-+		return;
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
-+		    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
-+	dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
-+	depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+
-+	DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
-+		    dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
-+
-+	if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
-+		if (ep->stopped) {
-+			if (core_if->en_multiple_tx_fifo)
-+				/* Flush the Tx FIFO */
-+				dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
-+			/* Clear the Global IN NP NAK */
-+			dctl.d32 = 0;
-+			dctl.b.cgnpinnak = 1;
-+			DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+			/* Restart the transaction */
-+			if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
-+				restart_transfer(pcd, epnum);
-+			}
-+		} else {
-+			/* Restart the transaction */
-+			if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
-+				restart_transfer(pcd, epnum);
-+			}
-+			DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
-+		}
-+		return;
-+	}
-+
-+	if (core_if->start_predict > 2) {	// NP IN EP
-+		core_if->start_predict--;
-+		return;
-+	}
-+
-+	core_if->start_predict--;
-+
-+	if (core_if->start_predict == 1) {	// All NP IN Ep's disabled now
-+
-+		predict_nextep_seq(core_if);
-+
-+		/* Update all active IN EP's NextEP field based of nextep_seq[] */
-+		for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
-+			depctl.d32 =
-+			    DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+			if (core_if->nextep_seq[i] != 0xff) {	// Active NP IN EP
-+				depctl.b.nextep = core_if->nextep_seq[i];
-+				DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+			}
-+		}
-+		/* Flush Shared NP TxFIFO */
-+		dwc_otg_flush_tx_fifo(core_if, 0);
-+		/* Rewind buffers */
-+		if (!core_if->dma_desc_enable) {
-+			i = core_if->first_in_nextep_seq;
-+			do {
-+				ep = get_in_ep(pcd, i);
-+				dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+				xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
-+				if (xfer_size > ep->dwc_ep.maxxfer)
-+					xfer_size = ep->dwc_ep.maxxfer;
-+				depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+				if (dieptsiz.b.pktcnt != 0) {
-+					if (xfer_size == 0) {
-+						remain_to_transfer = 0;
-+					} else {
-+						if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
-+							remain_to_transfer =
-+								dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
-+						} else {
-+							remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
-+								+ (xfer_size % ep->dwc_ep.maxpacket);
-+						}
-+					}
-+					diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
-+					dieptsiz.b.xfersize = remain_to_transfer;
-+					DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
-+					diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
-+					DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
-+				}
-+				i = core_if->nextep_seq[i];
-+			} while (i != core_if->first_in_nextep_seq);
-+		} else { // dma_desc_enable
-+				DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
-+		}
-+
-+		/* Restart transfers in predicted sequences */
-+		i = core_if->first_in_nextep_seq;
-+		do {
-+			dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+			depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+			if (dieptsiz.b.pktcnt != 0) {
-+				depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+				depctl.b.epena = 1;
-+				depctl.b.cnak = 1;
-+				DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
-+			}
-+			i = core_if->nextep_seq[i];
-+		} while (i != core_if->first_in_nextep_seq);
-+
-+		/* Clear the global non-periodic IN NAK handshake */
-+		dctl.d32 = 0;
-+		dctl.b.cgnpinnak = 1;
-+		DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+		/* Unmask EP Mismatch interrupt */
-+		gintmsk_data.d32 = 0;
-+		gintmsk_data.b.epmismatch = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
-+
-+		core_if->start_predict = 0;
-+
-+	}
-+}
-+
-+/**
-+ * Handler for the IN EP timeout handshake interrupt.
-+ */
-+static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
-+					     const uint32_t epnum)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+
-+#ifdef DEBUG
-+	deptsiz_data_t dieptsiz = {.d32 = 0 };
-+	uint32_t num = 0;
-+#endif
-+	dctl_data_t dctl = {.d32 = 0 };
-+	dwc_otg_pcd_ep_t *ep;
-+
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	ep = get_in_ep(pcd, epnum);
-+
-+	/* Disable the NP Tx Fifo Empty Interrrupt */
-+	if (!core_if->dma_enable) {
-+		intr_mask.b.nptxfempty = 1;
-+		DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+				 intr_mask.d32, 0);
-+	}
-+	/** @todo NGS Check EP type.
-+	 * Implement for Periodic EPs */
-+	/*
-+	 * Non-periodic EP
-+	 */
-+	/* Enable the Global IN NAK Effective Interrupt */
-+	intr_mask.b.ginnakeff = 1;
-+	DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
-+
-+	/* Set Global IN NAK */
-+	dctl.b.sgnpinnak = 1;
-+	DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
-+
-+	ep->stopped = 1;
-+
-+#ifdef DEBUG
-+	dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
-+	DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
-+		    dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
-+#endif
-+
-+#ifdef DISABLE_PERIODIC_EP
-+	/*
-+	 * Set the NAK bit for this EP to
-+	 * start the disable process.
-+	 */
-+	diepctl.d32 = 0;
-+	diepctl.b.snak = 1;
-+	DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
-+			 diepctl.d32);
-+	ep->disabling = 1;
-+	ep->stopped = 1;
-+#endif
-+}
-+
-+/**
-+ * Handler for the IN EP NAK interrupt.
-+ */
-+static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
-+					    const uint32_t epnum)
-+{
-+	/** @todo implement ISR */
-+	dwc_otg_core_if_t *core_if;
-+	diepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
-+	core_if = GET_CORE_IF(pcd);
-+	intr_mask.b.nak = 1;
-+
-+	if (core_if->multiproc_int_enable) {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+				 diepeachintmsk[epnum], intr_mask.d32, 0);
-+	} else {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
-+				 intr_mask.d32, 0);
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP Babble interrupt.
-+ */
-+static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
-+						const uint32_t epnum)
-+{
-+	/** @todo implement ISR */
-+	dwc_otg_core_if_t *core_if;
-+	doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
-+		   "OUT EP Babble");
-+	core_if = GET_CORE_IF(pcd);
-+	intr_mask.b.babble = 1;
-+
-+	if (core_if->multiproc_int_enable) {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+				 doepeachintmsk[epnum], intr_mask.d32, 0);
-+	} else {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+				 intr_mask.d32, 0);
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP NAK interrupt.
-+ */
-+static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
-+					     const uint32_t epnum)
-+{
-+	/** @todo implement ISR */
-+	dwc_otg_core_if_t *core_if;
-+	doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
-+	core_if = GET_CORE_IF(pcd);
-+	intr_mask.b.nak = 1;
-+
-+	if (core_if->multiproc_int_enable) {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+				 doepeachintmsk[epnum], intr_mask.d32, 0);
-+	} else {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+				 intr_mask.d32, 0);
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * Handler for the OUT EP NYET interrupt.
-+ */
-+static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
-+					      const uint32_t epnum)
-+{
-+	/** @todo implement ISR */
-+	dwc_otg_core_if_t *core_if;
-+	doepmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
-+	core_if = GET_CORE_IF(pcd);
-+	intr_mask.b.nyet = 1;
-+
-+	if (core_if->multiproc_int_enable) {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
-+				 doepeachintmsk[epnum], intr_mask.d32, 0);
-+	} else {
-+		DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+				 intr_mask.d32, 0);
-+	}
-+
-+	return 1;
-+}
-+
-+/**
-+ * This interrupt indicates that an IN EP has a pending Interrupt.
-+ * The sequence for handling the IN EP interrupt is shown below:
-+ * -#	Read the Device All Endpoint Interrupt register
-+ * -#	Repeat the following for each IN EP interrupt bit set (from
-+ *		LSB to MSB).
-+ * -#	Read the Device Endpoint Interrupt (DIEPINTn) register
-+ * -#	If "Transfer Complete" call the request complete function
-+ * -#	If "Endpoint Disabled" complete the EP disable procedure.
-+ * -#	If "AHB Error Interrupt" log error
-+ * -#	If "Time-out Handshake" log error
-+ * -#	If "IN Token Received when TxFIFO Empty" write packet to Tx
-+ *		FIFO.
-+ * -#	If "IN Token EP Mismatch" (disable, this is handled by EP
-+ *		Mismatch Interrupt)
-+ */
-+static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
-+{
-+#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
-+do { \
-+		diepint_data_t diepint = {.d32=0}; \
-+		diepint.b.__intr = 1; \
-+		DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
-+		diepint.d32); \
-+} while (0)
-+
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	dwc_otg_dev_if_t *dev_if = core_if->dev_if;
-+	diepint_data_t diepint = {.d32 = 0 };
-+	depctl_data_t depctl = {.d32 = 0 };
-+	uint32_t ep_intr;
-+	uint32_t epnum = 0;
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_ep_t *dwc_ep;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
-+
-+	/* Read in the device interrupt bits */
-+	ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
-+
-+	/* Service the Device IN interrupts for each endpoint */
-+	while (ep_intr) {
-+		if (ep_intr & 0x1) {
-+			uint32_t empty_msk;
-+			/* Get EP pointer */
-+			ep = get_in_ep(pcd, epnum);
-+			dwc_ep = &ep->dwc_ep;
-+
-+			depctl.d32 =
-+			    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+			empty_msk =
-+			    DWC_READ_REG32(&dev_if->
-+					   dev_global_regs->dtknqr4_fifoemptymsk);
-+
-+			DWC_DEBUGPL(DBG_PCDV,
-+				    "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
-+				    epnum, empty_msk, depctl.d32);
-+
-+			DWC_DEBUGPL(DBG_PCD,
-+				    "EP%d-%s: type=%d, mps=%d\n",
-+				    dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
-+				    dwc_ep->type, dwc_ep->maxpacket);
-+
-+			diepint.d32 =
-+			    dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
-+
-+			DWC_DEBUGPL(DBG_PCDV,
-+				    "EP %d Interrupt Register - 0x%x\n", epnum,
-+				    diepint.d32);
-+			/* Transfer complete */
-+			if (diepint.b.xfercompl) {
-+				/* Disable the NP Tx FIFO Empty
-+				 * Interrupt */
-+				if (core_if->en_multiple_tx_fifo == 0) {
-+					intr_mask.b.nptxfempty = 1;
-+					DWC_MODIFY_REG32
-+					    (&core_if->core_global_regs->gintmsk,
-+					     intr_mask.d32, 0);
-+				} else {
-+					/* Disable the Tx FIFO Empty Interrupt for this EP */
-+					uint32_t fifoemptymsk =
-+					    0x1 << dwc_ep->num;
-+					DWC_MODIFY_REG32(&core_if->
-+							 dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
-+							 fifoemptymsk, 0);
-+				}
-+				/* Clear the bit in DIEPINTn for this interrupt */
-+				CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
-+
-+				/* Complete the transfer */
-+				if (epnum == 0) {
-+					handle_ep0(pcd);
-+				}
-+#ifdef DWC_EN_ISOC
-+				else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+					if (!ep->stopped)
-+						complete_iso_ep(pcd, ep);
-+				}
-+#endif /* DWC_EN_ISOC */
-+#ifdef DWC_UTE_PER_IO
-+				else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+					if (!ep->stopped)
-+						complete_xiso_ep(ep);
-+				}
-+#endif /* DWC_UTE_PER_IO */
-+				else {
-+					if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
-+							dwc_ep->bInterval > 1) {
-+						dwc_ep->frame_num += dwc_ep->bInterval;
-+						if (dwc_ep->frame_num > 0x3FFF)
-+						{
-+							dwc_ep->frm_overrun = 1;
-+							dwc_ep->frame_num &= 0x3FFF;
-+						} else
-+							dwc_ep->frm_overrun = 0;
-+					}
-+					complete_ep(ep);
-+					if(diepint.b.nak)
-+						CLEAR_IN_EP_INTR(core_if, epnum, nak);
-+				}
-+			}
-+			/* Endpoint disable      */
-+			if (diepint.b.epdisabled) {
-+				DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
-+					    epnum);
-+				handle_in_ep_disable_intr(pcd, epnum);
-+
-+				/* Clear the bit in DIEPINTn for this interrupt */
-+				CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
-+			}
-+			/* AHB Error */
-+			if (diepint.b.ahberr) {
-+				DWC_ERROR("EP%d IN AHB Error\n", epnum);
-+				/* Clear the bit in DIEPINTn for this interrupt */
-+				CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
-+			}
-+			/* TimeOUT Handshake (non-ISOC IN EPs) */
-+			if (diepint.b.timeout) {
-+				DWC_ERROR("EP%d IN Time-out\n", epnum);
-+				handle_in_ep_timeout_intr(pcd, epnum);
-+
-+				CLEAR_IN_EP_INTR(core_if, epnum, timeout);
-+			}
-+			/** IN Token received with TxF Empty */
-+			if (diepint.b.intktxfemp) {
-+				DWC_DEBUGPL(DBG_ANY,
-+					    "EP%d IN TKN TxFifo Empty\n",
-+					    epnum);
-+				if (!ep->stopped && epnum != 0) {
-+
-+					diepmsk_data_t diepmsk = {.d32 = 0 };
-+					diepmsk.b.intktxfemp = 1;
-+
-+					if (core_if->multiproc_int_enable) {
-+						DWC_MODIFY_REG32
-+						    (&dev_if->dev_global_regs->diepeachintmsk
-+						     [epnum], diepmsk.d32, 0);
-+					} else {
-+						DWC_MODIFY_REG32
-+						    (&dev_if->dev_global_regs->diepmsk,
-+						     diepmsk.d32, 0);
-+					}
-+				} else if (core_if->dma_desc_enable
-+					   && epnum == 0
-+					   && pcd->ep0state ==
-+					   EP0_OUT_STATUS_PHASE) {
-+					// EP0 IN set STALL
-+					depctl.d32 =
-+					    DWC_READ_REG32(&dev_if->in_ep_regs
-+							   [epnum]->diepctl);
-+
-+					/* set the disable and stall bits */
-+					if (depctl.b.epena) {
-+						depctl.b.epdis = 1;
-+					}
-+					depctl.b.stall = 1;
-+					DWC_WRITE_REG32(&dev_if->in_ep_regs
-+							[epnum]->diepctl,
-+							depctl.d32);
-+				}
-+				CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
-+			}
-+			/** IN Token Received with EP mismatch */
-+			if (diepint.b.intknepmis) {
-+				DWC_DEBUGPL(DBG_ANY,
-+					    "EP%d IN TKN EP Mismatch\n", epnum);
-+				CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
-+			}
-+			/** IN Endpoint NAK Effective */
-+			if (diepint.b.inepnakeff) {
-+				DWC_DEBUGPL(DBG_ANY,
-+					    "EP%d IN EP NAK Effective\n",
-+					    epnum);
-+				/* Periodic EP */
-+				if (ep->disabling) {
-+					depctl.d32 = 0;
-+					depctl.b.snak = 1;
-+					depctl.b.epdis = 1;
-+					DWC_MODIFY_REG32(&dev_if->in_ep_regs
-+							 [epnum]->diepctl,
-+							 depctl.d32,
-+							 depctl.d32);
-+				}
-+				CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
-+
-+			}
-+
-+			/** IN EP Tx FIFO Empty Intr */
-+			if (diepint.b.emptyintr) {
-+				DWC_DEBUGPL(DBG_ANY,
-+					    "EP%d Tx FIFO Empty Intr \n",
-+					    epnum);
-+				write_empty_tx_fifo(pcd, epnum);
-+
-+				CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
-+
-+			}
-+
-+			/** IN EP BNA Intr */
-+			if (diepint.b.bna) {
-+				CLEAR_IN_EP_INTR(core_if, epnum, bna);
-+				if (core_if->dma_desc_enable) {
-+#ifdef DWC_EN_ISOC
-+					if (dwc_ep->type ==
-+					    DWC_OTG_EP_TYPE_ISOC) {
-+						/*
-+						 * This checking is performed to prevent first "false" BNA
-+						 * handling occuring right after reconnect
-+						 */
-+						if (dwc_ep->next_frame !=
-+						    0xffffffff)
-+							dwc_otg_pcd_handle_iso_bna(ep);
-+					} else
-+#endif				/* DWC_EN_ISOC */
-+					{
-+						dwc_otg_pcd_handle_noniso_bna(ep);
-+					}
-+				}
-+			}
-+			/* NAK Interrutp */
-+			if (diepint.b.nak) {
-+				DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
-+					    epnum);
-+				if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+					depctl_data_t depctl;
-+					if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
-+						ep->dwc_ep.frame_num = core_if->frame_num;
-+						if (ep->dwc_ep.bInterval > 1) {
-+							depctl.d32 = 0;
-+							depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
-+							if (ep->dwc_ep.frame_num & 0x1) {
-+								depctl.b.setd1pid = 1;
-+								depctl.b.setd0pid = 0;
-+							} else {
-+								depctl.b.setd0pid = 1;
-+								depctl.b.setd1pid = 0;
-+							}
-+							DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
-+						}
-+						start_next_request(ep);
-+					}
-+					ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
-+					if (dwc_ep->frame_num > 0x3FFF)	{
-+						dwc_ep->frm_overrun = 1;
-+						dwc_ep->frame_num &= 0x3FFF;
-+					} else
-+						dwc_ep->frm_overrun = 0;
-+				}
-+
-+				CLEAR_IN_EP_INTR(core_if, epnum, nak);
-+			}
-+		}
-+		epnum++;
-+		ep_intr >>= 1;
-+	}
-+
-+	return 1;
-+#undef CLEAR_IN_EP_INTR
-+}
-+
-+/**
-+ * This interrupt indicates that an OUT EP has a pending Interrupt.
-+ * The sequence for handling the OUT EP interrupt is shown below:
-+ * -#	Read the Device All Endpoint Interrupt register
-+ * -#	Repeat the following for each OUT EP interrupt bit set (from
-+ *		LSB to MSB).
-+ * -#	Read the Device Endpoint Interrupt (DOEPINTn) register
-+ * -#	If "Transfer Complete" call the request complete function
-+ * -#	If "Endpoint Disabled" complete the EP disable procedure.
-+ * -#	If "AHB Error Interrupt" log error
-+ * -#	If "Setup Phase Done" process Setup Packet (See Standard USB
-+ *		Command Processing)
-+ */
-+static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
-+{
-+#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
-+do { \
-+		doepint_data_t doepint = {.d32=0}; \
-+		doepint.b.__intr = 1; \
-+		DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
-+		doepint.d32); \
-+} while (0)
-+
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	uint32_t ep_intr;
-+	doepint_data_t doepint = {.d32 = 0 };
-+	uint32_t epnum = 0;
-+	dwc_otg_pcd_ep_t *ep;
-+	dwc_ep_t *dwc_ep;
-+	dctl_data_t dctl = {.d32 = 0 };
-+	gintmsk_data_t gintmsk = {.d32 = 0 };
-+
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
-+
-+	/* Read in the device interrupt bits */
-+	ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
-+
-+	while (ep_intr) {
-+		if (ep_intr & 0x1) {
-+			/* Get EP pointer */
-+			ep = get_out_ep(pcd, epnum);
-+			dwc_ep = &ep->dwc_ep;
-+
-+#ifdef VERBOSE
-+			DWC_DEBUGPL(DBG_PCDV,
-+				    "EP%d-%s: type=%d, mps=%d\n",
-+				    dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
-+				    dwc_ep->type, dwc_ep->maxpacket);
-+#endif
-+			doepint.d32 =
-+			    dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
-+			/* Moved this interrupt upper due to core deffect of asserting
-+			 * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */
-+			if (doepint.b.stsphsercvd) {
-+				deptsiz0_data_t deptsiz;
-+				CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
-+				deptsiz.d32 =
-+				    DWC_READ_REG32(&core_if->dev_if->
-+						   out_ep_regs[0]->doeptsiz);
-+				if (core_if->snpsid >= OTG_CORE_REV_3_00a
-+				    && core_if->dma_enable
-+				    && core_if->dma_desc_enable == 0
-+				    && doepint.b.xfercompl
-+				    && deptsiz.b.xfersize == 24) {
-+					CLEAR_OUT_EP_INTR(core_if, epnum,
-+							  xfercompl);
-+					doepint.b.xfercompl = 0;
-+					ep0_out_start(core_if, pcd);
-+				}
-+				if ((core_if->dma_desc_enable) ||
-+				    (core_if->dma_enable
-+				     && core_if->snpsid >=
-+				     OTG_CORE_REV_3_00a)) {
-+					do_setup_in_status_phase(pcd);
-+				}
-+			}
-+			/* Transfer complete */
-+			if (doepint.b.xfercompl) {
-+
-+				if (epnum == 0) {
-+					/* Clear the bit in DOEPINTn for this interrupt */
-+					CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
-+					if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
-+						DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
-+							DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
-+							doepint.d32);
-+						DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
-+							DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
-+
-+						if (core_if->snpsid >= OTG_CORE_REV_3_00a
-+							&& core_if->dma_enable == 0) {
-+							doepint_data_t doepint;
-+							doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+														out_ep_regs[0]->doepint);
-+							if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
-+								CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+								goto exit_xfercompl;
-+							}
-+						}
-+						/* In case of DDMA  look at SR bit to go to the Data Stage */
-+						if (core_if->dma_desc_enable) {
-+							dev_dma_desc_sts_t status = {.d32 = 0};
-+							if (pcd->ep0state == EP0_IDLE) {
-+								status.d32 = core_if->dev_if->setup_desc_addr[core_if->
-+											dev_if->setup_desc_index]->status.d32;
-+								if(pcd->data_terminated) {
-+									 pcd->data_terminated = 0;
-+									 status.d32 = core_if->dev_if->out_desc_addr->status.d32;
-+									 dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
-+								}
-+								if (status.b.sr) {
-+									if (doepint.b.setup) {
-+										DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
-+										/* Already started data stage, clear setup */
-+										CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+										doepint.b.setup = 0;
-+										handle_ep0(pcd);
-+										/* Prepare for more setup packets */
-+										if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
-+											pcd->ep0state == EP0_IN_DATA_PHASE) {
-+											ep0_out_start(core_if, pcd);
-+										}
-+
-+										goto exit_xfercompl;
-+									} else {
-+										/* Prepare for more setup packets */
-+										DWC_DEBUGPL(DBG_PCDV,
-+											"EP0_IDLE SR=1 setup=0 new setup comes\n");
-+										ep0_out_start(core_if, pcd);
-+									}
-+								}
-+							} else {
-+								dwc_otg_pcd_request_t *req;
-+								dev_dma_desc_sts_t status = {.d32 = 0};
-+								diepint_data_t diepint0;
-+								diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+															in_ep_regs[0]->diepint);
-+
-+								if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
-+									DWC_ERROR("EP0 is stalled/disconnected\n");
-+								}
-+
-+								/* Clear IN xfercompl if set */
-+								if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
-+									|| pcd->ep0state == EP0_IN_DATA_PHASE)) {
-+									DWC_WRITE_REG32(&core_if->dev_if->
-+										in_ep_regs[0]->diepint, diepint0.d32);
-+								}
-+
-+								status.d32 = core_if->dev_if->setup_desc_addr[core_if->
-+									dev_if->setup_desc_index]->status.d32;
-+
-+								if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
-+									&& (pcd->ep0state == EP0_OUT_DATA_PHASE))
-+									status.d32 = core_if->dev_if->out_desc_addr->status.d32;
-+								if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
-+									status.d32 = core_if->dev_if->
-+									out_desc_addr->status.d32;
-+
-+								if (status.b.sr) {
-+									if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+										DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
-+									} else {
-+										DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
-+										req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+										if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
-+											pcd->ep0state == EP0_OUT_DATA_PHASE) {
-+												/* Read arrived setup packet from req->buf */
-+												dwc_memcpy(&pcd->setup_pkt->req,
-+													req->buf + ep->dwc_ep.xfer_count, 8);
-+										}
-+										req->actual = ep->dwc_ep.xfer_count;
-+										dwc_otg_request_done(ep, req, -ECONNRESET);
-+										ep->dwc_ep.start_xfer_buff = 0;
-+										ep->dwc_ep.xfer_buff = 0;
-+										ep->dwc_ep.xfer_len = 0;
-+									}
-+									pcd->ep0state = EP0_IDLE;
-+									if (doepint.b.setup) {
-+										DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
-+										/* Data stage started, clear setup */
-+										CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+										doepint.b.setup = 0;
-+										handle_ep0(pcd);
-+										/* Prepare for setup packets if ep0in was enabled*/
-+										if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+											ep0_out_start(core_if, pcd);
-+										}
-+
-+										goto exit_xfercompl;
-+									} else {
-+										/* Prepare for more setup packets */
-+										DWC_DEBUGPL(DBG_PCDV,
-+											"EP0_IDLE SR=1 setup=0 new setup comes 2\n");
-+										ep0_out_start(core_if, pcd);
-+									}
-+								}
-+							}
-+						}
-+						if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable
-+							&& core_if->dma_desc_enable == 0) {
-+							doepint_data_t doepint_temp = {.d32 = 0};
-+							deptsiz0_data_t doeptsize0 = {.d32 = 0 };
-+							doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
-+															out_ep_regs[ep->dwc_ep.num]->doepint);
-+							doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+															out_ep_regs[ep->dwc_ep.num]->doeptsiz);
-+							if (pcd->ep0state == EP0_IDLE) {
-+								if (doepint_temp.b.sr) {
-+									CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+								}
-+									doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+																	out_ep_regs[0]->doepint);
-+									if (doeptsize0.b.supcnt == 3) {
-+										DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
-+										ep->dwc_ep.stp_rollover = 1;
-+									}
-+									if (doepint.b.setup) {
-+retry:
-+										/* Already started data stage, clear setup */
-+										CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+										doepint.b.setup = 0;
-+										handle_ep0(pcd);
-+										ep->dwc_ep.stp_rollover = 0;
-+										/* Prepare for more setup packets */
-+										if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
-+											pcd->ep0state == EP0_IN_DATA_PHASE) {
-+											ep0_out_start(core_if, pcd);
-+										}
-+										goto exit_xfercompl;
-+									} else {
-+										/* Prepare for more setup packets */
-+										DWC_DEBUGPL(DBG_ANY,
-+											"EP0_IDLE SR=1 setup=0 new setup comes\n");
-+										doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+																	out_ep_regs[0]->doepint);
-+										if(doepint.b.setup)
-+											goto retry;
-+										ep0_out_start(core_if, pcd);
-+									}
-+							} else {
-+								dwc_otg_pcd_request_t *req;
-+								diepint_data_t diepint0 = {.d32 = 0};
-+								doepint_data_t doepint_temp = {.d32 = 0};
-+								depctl_data_t diepctl0;
-+								diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+																in_ep_regs[0]->diepint);
-+								diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
-+																in_ep_regs[0]->diepctl);
-+
-+								if (pcd->ep0state == EP0_IN_DATA_PHASE
-+									|| pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+									if (diepint0.b.xfercompl) {
-+										DWC_WRITE_REG32(&core_if->dev_if->
-+											in_ep_regs[0]->diepint, diepint0.d32);
-+									}
-+									if (diepctl0.b.epena) {
-+										diepint_data_t diepint = {.d32 = 0};
-+										diepctl0.b.snak = 1;
-+										DWC_WRITE_REG32(&core_if->dev_if->
-+														in_ep_regs[0]->diepctl, diepctl0.d32);
-+										do {
-+											dwc_udelay(10);
-+											diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+												in_ep_regs[0]->diepint);
-+										} while (!diepint.b.inepnakeff);
-+										diepint.b.inepnakeff = 1;
-+										DWC_WRITE_REG32(&core_if->dev_if->
-+											in_ep_regs[0]->diepint, diepint.d32);
-+										diepctl0.d32 = 0;
-+										diepctl0.b.epdis = 1;
-+										DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
-+														diepctl0.d32);
-+										do {
-+											dwc_udelay(10);
-+											diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
-+												in_ep_regs[0]->diepint);
-+										} while (!diepint.b.epdisabled);
-+										diepint.b.epdisabled = 1;
-+										DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
-+															diepint.d32);
-+									}
-+								}
-+								doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
-+																out_ep_regs[ep->dwc_ep.num]->doepint);
-+								if (doepint_temp.b.sr) {
-+									CLEAR_OUT_EP_INTR(core_if, epnum, sr);
-+									if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+										DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
-+									} else {
-+										DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
-+										req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+										if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
-+											pcd->ep0state == EP0_OUT_DATA_PHASE) {
-+												/* Read arrived setup packet from req->buf */
-+												dwc_memcpy(&pcd->setup_pkt->req,
-+													req->buf + ep->dwc_ep.xfer_count, 8);
-+										}
-+										req->actual = ep->dwc_ep.xfer_count;
-+										dwc_otg_request_done(ep, req, -ECONNRESET);
-+										ep->dwc_ep.start_xfer_buff = 0;
-+										ep->dwc_ep.xfer_buff = 0;
-+										ep->dwc_ep.xfer_len = 0;
-+									}
-+									pcd->ep0state = EP0_IDLE;
-+									if (doepint.b.setup) {
-+										DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
-+										/* Data stage started, clear setup */
-+										CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+										doepint.b.setup = 0;
-+										handle_ep0(pcd);
-+										/* Prepare for setup packets if ep0in was enabled*/
-+										if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
-+											ep0_out_start(core_if, pcd);
-+										}
-+										goto exit_xfercompl;
-+									} else {
-+										/* Prepare for more setup packets */
-+										DWC_DEBUGPL(DBG_PCDV,
-+											"EP0_IDLE SR=1 setup=0 new setup comes 2\n");
-+										ep0_out_start(core_if, pcd);
-+									}
-+								}
-+							}
-+						}
-+						if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
-+							handle_ep0(pcd);
-+exit_xfercompl:
-+						DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
-+							dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
-+					} else {
-+					if (core_if->dma_desc_enable == 0
-+					    || pcd->ep0state != EP0_IDLE)
-+						handle_ep0(pcd);
-+					}
-+#ifdef DWC_EN_ISOC
-+				} else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+					if (doepint.b.pktdrpsts == 0) {
-+						/* Clear the bit in DOEPINTn for this interrupt */
-+						CLEAR_OUT_EP_INTR(core_if,
-+								  epnum,
-+								  xfercompl);
-+						complete_iso_ep(pcd, ep);
-+					} else {
-+
-+						doepint_data_t doepint = {.d32 = 0 };
-+						doepint.b.xfercompl = 1;
-+						doepint.b.pktdrpsts = 1;
-+						DWC_WRITE_REG32
-+						    (&core_if->dev_if->out_ep_regs
-+						     [epnum]->doepint,
-+						     doepint.d32);
-+						if (handle_iso_out_pkt_dropped
-+						    (core_if, dwc_ep)) {
-+							complete_iso_ep(pcd,
-+									ep);
-+						}
-+					}
-+#endif /* DWC_EN_ISOC */
-+#ifdef DWC_UTE_PER_IO
-+				} else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+					CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
-+					if (!ep->stopped)
-+						complete_xiso_ep(ep);
-+#endif /* DWC_UTE_PER_IO */
-+				} else {
-+					/* Clear the bit in DOEPINTn for this interrupt */
-+					CLEAR_OUT_EP_INTR(core_if, epnum,
-+							  xfercompl);
-+
-+					if (core_if->core_params->dev_out_nak) {
-+						DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
-+						pcd->core_if->ep_xfer_info[epnum].state = 0;
-+#ifdef DEBUG
-+						print_memory_payload(pcd, dwc_ep);
-+#endif
-+					}
-+					complete_ep(ep);
-+				}
-+
-+			}
-+
-+			/* Endpoint disable      */
-+			if (doepint.b.epdisabled) {
-+
-+				/* Clear the bit in DOEPINTn for this interrupt */
-+				CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
-+				if (core_if->core_params->dev_out_nak) {
-+#ifdef DEBUG
-+					print_memory_payload(pcd, dwc_ep);
-+#endif
-+					/* In case of timeout condition */
-+					if (core_if->ep_xfer_info[epnum].state == 2) {
-+						dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+										dev_global_regs->dctl);
-+						dctl.b.cgoutnak = 1;
-+						DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+																dctl.d32);
-+						/* Unmask goutnakeff interrupt which was masked
-+						 * during handle nak out interrupt */
-+						gintmsk.b.goutnakeff = 1;
-+						DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
-+																0, gintmsk.d32);
-+
-+						complete_ep(ep);
-+					}
-+				}
-+				if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
-+				{
-+					dctl_data_t dctl;
-+					gintmsk_data_t intr_mask = {.d32 = 0};
-+					dwc_otg_pcd_request_t *req = 0;
-+
-+					dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+						dev_global_regs->dctl);
-+					dctl.b.cgoutnak = 1;
-+					DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
-+						dctl.d32);
-+
-+					intr_mask.d32 = 0;
-+					intr_mask.b.incomplisoout = 1;
-+
-+					/* Get any pending requests */
-+					if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
-+						req = DWC_CIRCLEQ_FIRST(&ep->queue);
-+						if (!req) {
-+							DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
-+						} else {
-+							dwc_otg_request_done(ep, req, 0);
-+							start_next_request(ep);
-+						}
-+					} else {
-+						DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
-+					}
-+				}
-+			}
-+			/* AHB Error */
-+			if (doepint.b.ahberr) {
-+				DWC_ERROR("EP%d OUT AHB Error\n", epnum);
-+				DWC_ERROR("EP%d DEPDMA=0x%08x \n",
-+					  epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
-+				CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
-+			}
-+			/* Setup Phase Done (contorl EPs) */
-+			if (doepint.b.setup) {
-+#ifdef DEBUG_EP0
-+				DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
-+#endif
-+				CLEAR_OUT_EP_INTR(core_if, epnum, setup);
-+
-+				handle_ep0(pcd);
-+			}
-+
-+			/** OUT EP BNA Intr */
-+			if (doepint.b.bna) {
-+				CLEAR_OUT_EP_INTR(core_if, epnum, bna);
-+				if (core_if->dma_desc_enable) {
-+#ifdef DWC_EN_ISOC
-+					if (dwc_ep->type ==
-+					    DWC_OTG_EP_TYPE_ISOC) {
-+						/*
-+						 * This checking is performed to prevent first "false" BNA
-+						 * handling occuring right after reconnect
-+						 */
-+						if (dwc_ep->next_frame !=
-+						    0xffffffff)
-+							dwc_otg_pcd_handle_iso_bna(ep);
-+					} else
-+#endif				/* DWC_EN_ISOC */
-+					{
-+						dwc_otg_pcd_handle_noniso_bna(ep);
-+					}
-+				}
-+			}
-+			/* Babble Interrupt */
-+			if (doepint.b.babble) {
-+				DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
-+					    epnum);
-+				handle_out_ep_babble_intr(pcd, epnum);
-+
-+				CLEAR_OUT_EP_INTR(core_if, epnum, babble);
-+			}
-+			if (doepint.b.outtknepdis) {
-+				DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
-+					disabled\n",epnum);
-+				if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+					doepmsk_data_t doepmsk = {.d32 = 0};
-+					ep->dwc_ep.frame_num = core_if->frame_num;
-+					if (ep->dwc_ep.bInterval > 1) {
-+						depctl_data_t depctl;
-+						depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
-+													out_ep_regs[epnum]->doepctl);
-+						if (ep->dwc_ep.frame_num & 0x1) {
-+							depctl.b.setd1pid = 1;
-+							depctl.b.setd0pid = 0;
-+						} else {
-+							depctl.b.setd0pid = 1;
-+							depctl.b.setd1pid = 0;
-+						}
-+						DWC_WRITE_REG32(&core_if->dev_if->
-+										out_ep_regs[epnum]->doepctl, depctl.d32);
-+					}
-+					start_next_request(ep);
-+					doepmsk.b.outtknepdis = 1;
-+					DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
-+								 doepmsk.d32, 0);
-+				}
-+				CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
-+			}
-+
-+			/* NAK Interrutp */
-+			if (doepint.b.nak) {
-+				DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
-+				handle_out_ep_nak_intr(pcd, epnum);
-+
-+				CLEAR_OUT_EP_INTR(core_if, epnum, nak);
-+			}
-+			/* NYET Interrutp */
-+			if (doepint.b.nyet) {
-+				DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
-+				handle_out_ep_nyet_intr(pcd, epnum);
-+
-+				CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
-+			}
-+		}
-+
-+		epnum++;
-+		ep_intr >>= 1;
-+	}
-+
-+	return 1;
-+
-+#undef CLEAR_OUT_EP_INTR
-+}
-+static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
-+{
-+	int retval = 0;
-+	if(!frm_overrun && curr_fr >= trgt_fr)
-+		retval = 1;
-+	else if (frm_overrun
-+		 && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
-+		retval = 1;
-+	return retval;
-+}
-+/**
-+ * Incomplete ISO IN Transfer Interrupt.
-+ * This interrupt indicates one of the following conditions occurred
-+ * while transmitting an ISOC transaction.
-+ * - Corrupted IN Token for ISOC EP.
-+ * - Packet not complete in FIFO.
-+ * The follow actions will be taken:
-+ *	-#	Determine the EP
-+ *	-#	Set incomplete flag in dwc_ep structure
-+ *	-#	Disable EP; when "Endpoint Disabled" interrupt is received
-+ *		Flush FIFO
-+ */
-+int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
-+{
-+	gintsts_data_t gintsts;
-+
-+#ifdef DWC_EN_ISOC
-+	dwc_otg_dev_if_t *dev_if;
-+	deptsiz_data_t deptsiz = {.d32 = 0 };
-+	depctl_data_t depctl = {.d32 = 0 };
-+	dsts_data_t dsts = {.d32 = 0 };
-+	dwc_ep_t *dwc_ep;
-+	int i;
-+
-+	dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+	for (i = 1; i <= dev_if->num_in_eps; ++i) {
-+		dwc_ep = &pcd->in_ep[i].dwc_ep;
-+		if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+			deptsiz.d32 =
-+			    DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
-+			depctl.d32 =
-+			    DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+
-+			if (depctl.b.epdis && deptsiz.d32) {
-+				set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
-+				if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+					dwc_ep->cur_pkt = 0;
-+					dwc_ep->proc_buf_num =
-+					    (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+
-+					if (dwc_ep->proc_buf_num) {
-+						dwc_ep->cur_pkt_addr =
-+						    dwc_ep->xfer_buff1;
-+						dwc_ep->cur_pkt_dma_addr =
-+						    dwc_ep->dma_addr1;
-+					} else {
-+						dwc_ep->cur_pkt_addr =
-+						    dwc_ep->xfer_buff0;
-+						dwc_ep->cur_pkt_dma_addr =
-+						    dwc_ep->dma_addr0;
-+					}
-+
-+				}
-+
-+				dsts.d32 =
-+				    DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+						   dev_global_regs->dsts);
-+				dwc_ep->next_frame = dsts.b.soffn;
-+
-+				dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
-+								  (pcd),
-+								  dwc_ep);
-+			}
-+		}
-+	}
-+
-+#else
-+	depctl_data_t depctl = {.d32 = 0 };
-+	dwc_ep_t *dwc_ep;
-+	dwc_otg_dev_if_t *dev_if;
-+	int i;
-+	dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+	DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
-+
-+	for (i = 1; i <= dev_if->num_in_eps; ++i) {
-+		dwc_ep = &pcd->in_ep[i-1].dwc_ep;
-+		depctl.d32 =
-+			DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+		if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
-+			if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
-+							dwc_ep->frm_overrun))
-+			{
-+				depctl.d32 =
-+					DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+				depctl.b.snak = 1;
-+				depctl.b.epdis = 1;
-+				DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
-+			}
-+		}
-+	}
-+
-+	/*intr_mask.b.incomplisoin = 1;
-+	DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+			 intr_mask.d32, 0);	 */
-+#endif				//DWC_EN_ISOC
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.incomplisoin = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * Incomplete ISO OUT Transfer Interrupt.
-+ *
-+ * This interrupt indicates that the core has dropped an ISO OUT
-+ * packet. The following conditions can be the cause:
-+ * - FIFO Full, the entire packet would not fit in the FIFO.
-+ * - CRC Error
-+ * - Corrupted Token
-+ * The follow actions will be taken:
-+ *	-#	Determine the EP
-+ *	-#	Set incomplete flag in dwc_ep structure
-+ *	-#	Read any data from the FIFO
-+ *	-#	Disable EP. When "Endpoint Disabled" interrupt is received
-+ *		re-enable EP.
-+ */
-+int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
-+{
-+
-+	gintsts_data_t gintsts;
-+
-+#ifdef DWC_EN_ISOC
-+	dwc_otg_dev_if_t *dev_if;
-+	deptsiz_data_t deptsiz = {.d32 = 0 };
-+	depctl_data_t depctl = {.d32 = 0 };
-+	dsts_data_t dsts = {.d32 = 0 };
-+	dwc_ep_t *dwc_ep;
-+	int i;
-+
-+	dev_if = GET_CORE_IF(pcd)->dev_if;
-+
-+	for (i = 1; i <= dev_if->num_out_eps; ++i) {
-+		dwc_ep = &pcd->in_ep[i].dwc_ep;
-+		if (pcd->out_ep[i].dwc_ep.active &&
-+		    pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
-+			deptsiz.d32 =
-+			    DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
-+			depctl.d32 =
-+			    DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+
-+			if (depctl.b.epdis && deptsiz.d32) {
-+				set_current_pkt_info(GET_CORE_IF(pcd),
-+						     &pcd->out_ep[i].dwc_ep);
-+				if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
-+					dwc_ep->cur_pkt = 0;
-+					dwc_ep->proc_buf_num =
-+					    (dwc_ep->proc_buf_num ^ 1) & 0x1;
-+
-+					if (dwc_ep->proc_buf_num) {
-+						dwc_ep->cur_pkt_addr =
-+						    dwc_ep->xfer_buff1;
-+						dwc_ep->cur_pkt_dma_addr =
-+						    dwc_ep->dma_addr1;
-+					} else {
-+						dwc_ep->cur_pkt_addr =
-+						    dwc_ep->xfer_buff0;
-+						dwc_ep->cur_pkt_dma_addr =
-+						    dwc_ep->dma_addr0;
-+					}
-+
-+				}
-+
-+				dsts.d32 =
-+				    DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
-+						   dev_global_regs->dsts);
-+				dwc_ep->next_frame = dsts.b.soffn;
-+
-+				dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
-+								  (pcd),
-+								  dwc_ep);
-+			}
-+		}
-+	}
-+#else
-+	/** @todo implement ISR */
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	dwc_otg_core_if_t *core_if;
-+	deptsiz_data_t deptsiz = {.d32 = 0 };
-+	depctl_data_t depctl = {.d32 = 0 };
-+	dctl_data_t dctl = {.d32 = 0 };
-+	dwc_ep_t *dwc_ep = NULL;
-+	int i;
-+	core_if = GET_CORE_IF(pcd);
-+
-+	for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
-+		dwc_ep = &pcd->out_ep[i].dwc_ep;
-+		depctl.d32 =
-+			DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
-+		if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
-+			core_if->dev_if->isoc_ep = dwc_ep;
-+			deptsiz.d32 =
-+					DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
-+				break;
-+		}
-+	}
-+	dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
-+	gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
-+	intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
-+
-+	if (!intr_mask.b.goutnakeff) {
-+		/* Unmask it */
-+		intr_mask.b.goutnakeff = 1;
-+		DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
-+	}
-+	if (!gintsts.b.goutnakeff) {
-+		dctl.b.sgoutnak = 1;
-+	}
-+	DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
-+
-+	depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
-+	if (depctl.b.epena) {
-+		depctl.b.epdis = 1;
-+		depctl.b.snak = 1;
-+	}
-+	DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
-+
-+	intr_mask.d32 = 0;
-+	intr_mask.b.incomplisoout = 1;
-+
-+#endif /* DWC_EN_ISOC */
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.incomplisoout = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * This function handles the Global IN NAK Effective interrupt.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+	depctl_data_t diepctl = {.d32 = 0 };
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	gintsts_data_t gintsts;
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+	int i;
-+
-+	DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
-+
-+	/* Disable all active IN EPs */
-+	for (i = 0; i <= dev_if->num_in_eps; i++) {
-+		diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
-+		if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
-+			if (core_if->start_predict > 0)
-+				core_if->start_predict++;
-+			diepctl.b.epdis = 1;
-+			diepctl.b.snak = 1;
-+			DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
-+		}
-+	}
-+
-+
-+	/* Disable the Global IN NAK Effective Interrupt */
-+	intr_mask.b.ginnakeff = 1;
-+	DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+			 intr_mask.d32, 0);
-+
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.ginnakeff = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * OUT NAK Effective.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
-+	gintmsk_data_t intr_mask = {.d32 = 0 };
-+	gintsts_data_t gintsts;
-+	depctl_data_t doepctl;
-+	int i;
-+
-+	/* Disable the Global OUT NAK Effective Interrupt */
-+	intr_mask.b.goutnakeff = 1;
-+	DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
-+		intr_mask.d32, 0);
-+
-+	/* If DEV OUT NAK enabled*/
-+	if (pcd->core_if->core_params->dev_out_nak) {
-+		/* Run over all out endpoints to determine the ep number on
-+		 * which the timeout has happened
-+		 */
-+		for (i = 0; i <= dev_if->num_out_eps; i++) {
-+			if ( pcd->core_if->ep_xfer_info[i].state == 2 )
-+				break;
-+		}
-+		if (i > dev_if->num_out_eps) {
-+			dctl_data_t dctl;
-+			dctl.d32 =
-+			    DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
-+			dctl.b.cgoutnak = 1;
-+			DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
-+				dctl.d32);
-+			goto out;
-+		}
-+
-+		/* Disable the endpoint */
-+		doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
-+		if (doepctl.b.epena) {
-+			doepctl.b.epdis = 1;
-+			doepctl.b.snak = 1;
-+		}
-+		DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
-+		return 1;
-+	}
-+	/* We come here from Incomplete ISO OUT handler */
-+	if (dev_if->isoc_ep) {
-+		dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
-+		uint32_t epnum = dwc_ep->num;
-+		doepint_data_t doepint;
-+		doepint.d32 =
-+		    DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
-+		dev_if->isoc_ep = NULL;
-+		doepctl.d32 =
-+		    DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
-+		DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
-+		if (doepctl.b.epena) {
-+			doepctl.b.epdis = 1;
-+			doepctl.b.snak = 1;
-+		}
-+		DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
-+				doepctl.d32);
-+		return 1;
-+	} else
-+		DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
-+			   "Global OUT NAK Effective\n");
-+
-+out:
-+	/* Clear interrupt */
-+	gintsts.d32 = 0;
-+	gintsts.b.goutnakeff = 1;
-+	DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
-+			gintsts.d32);
-+
-+	return 1;
-+}
-+
-+/**
-+ * PCD interrupt handler.
-+ *
-+ * The PCD handles the device interrupts.  Many conditions can cause a
-+ * device interrupt. When an interrupt occurs, the device interrupt
-+ * service routine determines the cause of the interrupt and
-+ * dispatches handling to the appropriate function. These interrupt
-+ * handling functions are described below.
-+ *
-+ * All interrupt registers are processed from LSB to MSB.
-+ *
-+ */
-+int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
-+{
-+	dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
-+#ifdef VERBOSE
-+	dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
-+#endif
-+	gintsts_data_t gintr_status;
-+	int32_t retval = 0;
-+
-+	/* Exit from ISR if core is hibernated */
-+	if (core_if->hibernation_suspend == 1) {
-+		return retval;
-+	}
-+#ifdef VERBOSE
-+	DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x	 gintmsk=%08x\n",
-+		    __func__,
-+		    DWC_READ_REG32(&global_regs->gintsts),
-+		    DWC_READ_REG32(&global_regs->gintmsk));
-+#endif
-+
-+	if (dwc_otg_is_device_mode(core_if)) {
-+		DWC_SPINLOCK(pcd->lock);
-+#ifdef VERBOSE
-+		DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
-+			    __func__,
-+			    DWC_READ_REG32(&global_regs->gintsts),
-+			    DWC_READ_REG32(&global_regs->gintmsk));
-+#endif
-+
-+		gintr_status.d32 = dwc_otg_read_core_intr(core_if);
-+
-+		DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
-+			    __func__, gintr_status.d32);
-+
-+		if (gintr_status.b.sofintr) {
-+			retval |= dwc_otg_pcd_handle_sof_intr(pcd);
-+		}
-+		if (gintr_status.b.rxstsqlvl) {
-+			retval |=
-+			    dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
-+		}
-+		if (gintr_status.b.nptxfempty) {
-+			retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
-+		}
-+		if (gintr_status.b.goutnakeff) {
-+			retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
-+		}
-+		if (gintr_status.b.i2cintr) {
-+			retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
-+		}
-+		if (gintr_status.b.erlysuspend) {
-+			retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
-+		}
-+		if (gintr_status.b.usbreset) {
-+			retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
-+		}
-+		if (gintr_status.b.enumdone) {
-+			retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
-+		}
-+		if (gintr_status.b.isooutdrop) {
-+			retval |=
-+			    dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
-+			    (pcd);
-+		}
-+		if (gintr_status.b.eopframe) {
-+			retval |=
-+			    dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
-+		}
-+		if (gintr_status.b.inepint) {
-+			if (!core_if->multiproc_int_enable) {
-+				retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
-+			}
-+		}
-+		if (gintr_status.b.outepintr) {
-+			if (!core_if->multiproc_int_enable) {
-+				retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
-+			}
-+		}
-+		if (gintr_status.b.epmismatch) {
-+			retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
-+		}
-+		if (gintr_status.b.fetsusp) {
-+			retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
-+		}
-+		if (gintr_status.b.ginnakeff) {
-+			retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
-+		}
-+		if (gintr_status.b.incomplisoin) {
-+			retval |=
-+			    dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
-+		}
-+		if (gintr_status.b.incomplisoout) {
-+			retval |=
-+			    dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
-+		}
-+
-+		/* In MPI mode Device Endpoints interrupts are asserted
-+		 * without setting outepintr and inepint bits set, so these
-+		 * Interrupt handlers are called without checking these bit-fields
-+		 */
-+		if (core_if->multiproc_int_enable) {
-+			retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
-+			retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
-+		}
-+#ifdef VERBOSE
-+		DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
-+			    DWC_READ_REG32(&global_regs->gintsts));
-+#endif
-+		DWC_SPINUNLOCK(pcd->lock);
-+	}
-+	return retval;
-+}
-+
-+#endif /* DWC_HOST_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
-@@ -0,0 +1,1280 @@
-+ /* ==========================================================================
-+  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
-+  * $Revision: #21 $
-+  * $Date: 2012/08/10 $
-+  * $Change: 2047372 $
-+  *
-+  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+  * otherwise expressly agreed to in writing between Synopsys and you.
-+  *
-+  * The Software IS NOT an item of Licensed Software or Licensed Product under
-+  * any End User Software License Agreement or Agreement for Licensed Product
-+  * with Synopsys or any supplement thereto. You are permitted to use and
-+  * redistribute this Software in source and binary forms, with or without
-+  * modification, provided that redistributions of source code must retain this
-+  * notice. You may not view, use, disclose, copy or distribute this file or
-+  * any information contained herein except pursuant to this license grant from
-+  * Synopsys. If you do not agree with this notice, including the disclaimer
-+  * below, then you are not authorized to use the Software.
-+  *
-+  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+  * DAMAGE.
-+  * ========================================================================== */
-+#ifndef DWC_HOST_ONLY
-+
-+/** @file
-+ * This file implements the Peripheral Controller Driver.
-+ *
-+ * The Peripheral Controller Driver (PCD) is responsible for
-+ * translating requests from the Function Driver into the appropriate
-+ * actions on the DWC_otg controller. It isolates the Function Driver
-+ * from the specifics of the controller by providing an API to the
-+ * Function Driver.
-+ *
-+ * The Peripheral Controller Driver for Linux will implement the
-+ * Gadget API, so that the existing Gadget drivers can be used.
-+ * (Gadget Driver is the Linux terminology for a Function Driver.)
-+ *
-+ * The Linux Gadget API is defined in the header file
-+ * <code><linux/usb_gadget.h></code>.  The USB EP operations API is
-+ * defined in the structure <code>usb_ep_ops</code> and the USB
-+ * Controller API is defined in the structure
-+ * <code>usb_gadget_ops</code>.
-+ *
-+ */
-+
-+#include "dwc_otg_os_dep.h"
-+#include "dwc_otg_pcd_if.h"
-+#include "dwc_otg_pcd.h"
-+#include "dwc_otg_driver.h"
-+#include "dwc_otg_dbg.h"
-+
-+extern bool fiq_enable;
-+
-+static struct gadget_wrapper {
-+	dwc_otg_pcd_t *pcd;
-+
-+	struct usb_gadget gadget;
-+	struct usb_gadget_driver *driver;
-+
-+	struct usb_ep ep0;
-+	struct usb_ep in_ep[16];
-+	struct usb_ep out_ep[16];
-+
-+} *gadget_wrapper;
-+
-+/* Display the contents of the buffer */
-+extern void dump_msg(const u8 * buf, unsigned int length);
-+/**
-+ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case
-+ * if the endpoint is not found
-+ */
-+static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
-+{
-+	int i;
-+	if (pcd->ep0.priv == handle) {
-+		return &pcd->ep0;
-+	}
-+
-+	for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
-+		if (pcd->in_ep[i].priv == handle)
-+			return &pcd->in_ep[i];
-+		if (pcd->out_ep[i].priv == handle)
-+			return &pcd->out_ep[i];
-+	}
-+
-+	return NULL;
-+}
-+
-+/* USB Endpoint Operations */
-+/*
-+ * The following sections briefly describe the behavior of the Gadget
-+ * API endpoint operations implemented in the DWC_otg driver
-+ * software. Detailed descriptions of the generic behavior of each of
-+ * these functions can be found in the Linux header file
-+ * include/linux/usb_gadget.h.
-+ *
-+ * The Gadget API provides wrapper functions for each of the function
-+ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
-+ * function, which then calls the underlying PCD function. The
-+ * following sections are named according to the wrapper
-+ * functions. Within each section, the corresponding DWC_otg PCD
-+ * function name is specified.
-+ *
-+ */
-+
-+/**
-+ * This function is called by the Gadget Driver for each EP to be
-+ * configured for the current configuration (SET_CONFIGURATION).
-+ *
-+ * This function initializes the dwc_otg_ep_t data structure, and then
-+ * calls dwc_otg_ep_activate.
-+ */
-+static int ep_enable(struct usb_ep *usb_ep,
-+		     const struct usb_endpoint_descriptor *ep_desc)
-+{
-+	int retval;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
-+
-+	if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
-+		DWC_WARN("%s, bad ep or descriptor\n", __func__);
-+		return -EINVAL;
-+	}
-+	if (usb_ep == &gadget_wrapper->ep0) {
-+		DWC_WARN("%s, bad ep(0)\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	/* Check FIFO size? */
-+	if (!ep_desc->wMaxPacketSize) {
-+		DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
-+		return -ERANGE;
-+	}
-+
-+	if (!gadget_wrapper->driver ||
-+	    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+		DWC_WARN("%s, bogus device state\n", __func__);
-+		return -ESHUTDOWN;
-+	}
-+
-+	/* Delete after check - MAS */
-+#if 0
-+	nat = (uint32_t) ep_desc->wMaxPacketSize;
-+	printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
-+	nat = (nat >> 11) & 0x03;
-+	printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
-+#endif
-+	retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
-+				       (const uint8_t *)ep_desc,
-+				       (void *)usb_ep);
-+	if (retval) {
-+		DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
-+		return -EINVAL;
-+	}
-+
-+	usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
-+
-+	return 0;
-+}
-+
-+/**
-+ * This function is called when an EP is disabled due to disconnect or
-+ * change in configuration. Any pending requests will terminate with a
-+ * status of -ESHUTDOWN.
-+ *
-+ * This function modifies the dwc_otg_ep_t data structure for this EP,
-+ * and then calls dwc_otg_ep_deactivate.
-+ */
-+static int ep_disable(struct usb_ep *usb_ep)
-+{
-+	int retval;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
-+	if (!usb_ep) {
-+		DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
-+			    usb_ep ? usb_ep->name : NULL);
-+		return -EINVAL;
-+	}
-+
-+	retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
-+	if (retval) {
-+		retval = -EINVAL;
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function allocates a request object to use with the specified
-+ * endpoint.
-+ *
-+ * @param ep The endpoint to be used with with the request
-+ * @param gfp_flags the GFP_* flags to use.
-+ */
-+static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
-+						     gfp_t gfp_flags)
-+{
-+	struct usb_request *usb_req;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
-+	if (0 == ep) {
-+		DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
-+		return 0;
-+	}
-+	usb_req = kzalloc(sizeof(*usb_req), gfp_flags);
-+	if (0 == usb_req) {
-+		DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
-+		return 0;
-+	}
-+	usb_req->dma = DWC_DMA_ADDR_INVALID;
-+
-+	return usb_req;
-+}
-+
-+/**
-+ * This function frees a request object.
-+ *
-+ * @param ep The endpoint associated with the request
-+ * @param req The request being freed
-+ */
-+static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
-+{
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
-+
-+	if (0 == ep || 0 == req) {
-+		DWC_WARN("%s() %s\n", __func__,
-+			 "Invalid ep or req argument!\n");
-+		return;
-+	}
-+
-+	kfree(req);
-+}
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+/**
-+ * This function allocates an I/O buffer to be used for a transfer
-+ * to/from the specified endpoint.
-+ *
-+ * @param usb_ep The endpoint to be used with with the request
-+ * @param bytes The desired number of bytes for the buffer
-+ * @param dma Pointer to the buffer's DMA address; must be valid
-+ * @param gfp_flags the GFP_* flags to use.
-+ * @return address of a new buffer or null is buffer could not be allocated.
-+ */
-+static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
-+				      dma_addr_t * dma, gfp_t gfp_flags)
-+{
-+	void *buf;
-+	dwc_otg_pcd_t *pcd = 0;
-+
-+	pcd = gadget_wrapper->pcd;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
-+		    dma, gfp_flags);
-+
-+	/* Check dword alignment */
-+	if ((bytes & 0x3UL) != 0) {
-+		DWC_WARN("%s() Buffer size is not a multiple of"
-+			 "DWORD size (%d)", __func__, bytes);
-+	}
-+
-+	buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
-+	WARN_ON(!buf);
-+
-+	/* Check dword alignment */
-+	if (((int)buf & 0x3UL) != 0) {
-+		DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
-+			 __func__, buf);
-+	}
-+
-+	return buf;
-+}
-+
-+/**
-+ * This function frees an I/O buffer that was allocated by alloc_buffer.
-+ *
-+ * @param usb_ep the endpoint associated with the buffer
-+ * @param buf address of the buffer
-+ * @param dma The buffer's DMA address
-+ * @param bytes The number of bytes of the buffer
-+ */
-+static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
-+				    dma_addr_t dma, unsigned bytes)
-+{
-+	dwc_otg_pcd_t *pcd = 0;
-+
-+	pcd = gadget_wrapper->pcd;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
-+
-+	dma_free_coherent(NULL, bytes, buf, dma);
-+}
-+#endif
-+
-+/**
-+ * This function is used to submit an I/O Request to an EP.
-+ *
-+ *	- When the request completes the request's completion callback
-+ *	  is called to return the request to the driver.
-+ *	- An EP, except control EPs, may have multiple requests
-+ *	  pending.
-+ *	- Once submitted the request cannot be examined or modified.
-+ *	- Each request is turned into one or more packets.
-+ *	- A BULK EP can queue any amount of data; the transfer is
-+ *	  packetized.
-+ *	- Zero length Packets are specified with the request 'zero'
-+ *	  flag.
-+ */
-+static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
-+		    gfp_t gfp_flags)
-+{
-+	dwc_otg_pcd_t *pcd;
-+	struct dwc_otg_pcd_ep *ep = NULL;
-+	int retval = 0, is_isoc_ep = 0;
-+	dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
-+		    __func__, usb_ep, usb_req, gfp_flags);
-+
-+	if (!usb_req || !usb_req->complete || !usb_req->buf) {
-+		DWC_WARN("bad params\n");
-+		return -EINVAL;
-+	}
-+
-+	if (!usb_ep) {
-+		DWC_WARN("bad ep\n");
-+		return -EINVAL;
-+	}
-+
-+	pcd = gadget_wrapper->pcd;
-+	if (!gadget_wrapper->driver ||
-+	    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+		DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
-+			    gadget_wrapper->gadget.speed);
-+		DWC_WARN("bogus device state\n");
-+		return -ESHUTDOWN;
-+	}
-+
-+	DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
-+		    usb_ep->name, usb_req, usb_req->length, usb_req->buf);
-+
-+	usb_req->status = -EINPROGRESS;
-+	usb_req->actual = 0;
-+
-+	ep = ep_from_handle(pcd, usb_ep);
-+	if (ep == NULL)
-+		is_isoc_ep = 0;
-+	else
-+		is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+	dma_addr = usb_req->dma;
-+#else
-+	if (GET_CORE_IF(pcd)->dma_enable) {
-+                dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
-+                struct device *dev = NULL;
-+
-+                if (otg_dev != NULL)
-+                        dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
-+
-+		if (usb_req->length != 0 &&
-+                    usb_req->dma == DWC_DMA_ADDR_INVALID) {
-+                        dma_addr = dma_map_single(dev, usb_req->buf,
-+                                                  usb_req->length,
-+                                                  ep->dwc_ep.is_in ?
-+                                                        DMA_TO_DEVICE:
-+                                                        DMA_FROM_DEVICE);
-+		}
-+	}
-+#endif
-+
-+#ifdef DWC_UTE_PER_IO
-+	if (is_isoc_ep == 1) {
-+		retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
-+			usb_req->length, usb_req->zero, usb_req,
-+			gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
-+		if (retval)
-+			return -EINVAL;
-+
-+		return 0;
-+	}
-+#endif
-+	retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
-+				      usb_req->length, usb_req->zero, usb_req,
-+				      gfp_flags == GFP_ATOMIC ? 1 : 0);
-+	if (retval) {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * This function cancels an I/O request from an EP.
-+ */
-+static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
-+{
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
-+
-+	if (!usb_ep || !usb_req) {
-+		DWC_WARN("bad argument\n");
-+		return -EINVAL;
-+	}
-+	if (!gadget_wrapper->driver ||
-+	    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+		DWC_WARN("bogus device state\n");
-+		return -ESHUTDOWN;
-+	}
-+	if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+/**
-+ * usb_ep_set_halt stalls an endpoint.
-+ *
-+ * usb_ep_clear_halt clears an endpoint halt and resets its data
-+ * toggle.
-+ *
-+ * Both of these functions are implemented with the same underlying
-+ * function. The behavior depends on the value argument.
-+ *
-+ * @param[in] usb_ep the Endpoint to halt or clear halt.
-+ * @param[in] value
-+ *	- 0 means clear_halt.
-+ *	- 1 means set_halt,
-+ *	- 2 means clear stall lock flag.
-+ *	- 3 means set  stall lock flag.
-+ */
-+static int ep_halt(struct usb_ep *usb_ep, int value)
-+{
-+	int retval = 0;
-+
-+	DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
-+
-+	if (!usb_ep) {
-+		DWC_WARN("bad ep\n");
-+		return -EINVAL;
-+	}
-+
-+	retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
-+	if (retval == -DWC_E_AGAIN) {
-+		return -EAGAIN;
-+	} else if (retval) {
-+		retval = -EINVAL;
-+	}
-+
-+	return retval;
-+}
-+
-+//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
-+#if 0
-+/**
-+ * ep_wedge: sets the halt feature and ignores clear requests
-+ *
-+ * @usb_ep: the endpoint being wedged
-+ *
-+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
-+ * requests. If the gadget driver clears the halt status, it will
-+ * automatically unwedge the endpoint.
-+ *
-+ * Returns zero on success, else negative errno. *
-+ * Check usb_ep_set_wedge() at "usb_gadget.h" for details
-+ */
-+static int ep_wedge(struct usb_ep *usb_ep)
-+{
-+	int retval = 0;
-+
-+	DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
-+
-+	if (!usb_ep) {
-+		DWC_WARN("bad ep\n");
-+		return -EINVAL;
-+	}
-+
-+	retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
-+	if (retval == -DWC_E_AGAIN) {
-+		retval = -EAGAIN;
-+	} else if (retval) {
-+		retval = -EINVAL;
-+	}
-+
-+	return retval;
-+}
-+#endif
-+
-+#ifdef DWC_EN_ISOC
-+/**
-+ * This function is used to submit an ISOC Transfer Request to an EP.
-+ *
-+ *	- Every time a sync period completes the request's completion callback
-+ *	  is called to provide data to the gadget driver.
-+ *	- Once submitted the request cannot be modified.
-+ *	- Each request is turned into periodic data packets untill ISO
-+ *	  Transfer is stopped..
-+ */
-+static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
-+			gfp_t gfp_flags)
-+{
-+	int retval = 0;
-+
-+	if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
-+		DWC_WARN("bad params\n");
-+		return -EINVAL;
-+	}
-+
-+	if (!usb_ep) {
-+		DWC_PRINTF("bad params\n");
-+		return -EINVAL;
-+	}
-+
-+	req->status = -EINPROGRESS;
-+
-+	retval =
-+	    dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
-+				     req->buf1, req->dma0, req->dma1,
-+				     req->sync_frame, req->data_pattern_frame,
-+				     req->data_per_frame,
-+				     req->
-+				     flags & USB_REQ_ISO_ASAP ? -1 :
-+				     req->start_frame, req->buf_proc_intrvl,
-+				     req, gfp_flags == GFP_ATOMIC ? 1 : 0);
-+
-+	if (retval) {
-+		return -EINVAL;
-+	}
-+
-+	return retval;
-+}
-+
-+/**
-+ * This function stops ISO EP Periodic Data Transfer.
-+ */
-+static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
-+{
-+	int retval = 0;
-+	if (!usb_ep) {
-+		DWC_WARN("bad ep\n");
-+	}
-+
-+	if (!gadget_wrapper->driver ||
-+	    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
-+		DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
-+			    gadget_wrapper->gadget.speed);
-+		DWC_WARN("bogus device state\n");
-+	}
-+
-+	dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
-+	if (retval) {
-+		retval = -EINVAL;
-+	}
-+
-+	return retval;
-+}
-+
-+static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
-+						 int packets, gfp_t gfp_flags)
-+{
-+	struct usb_iso_request *pReq = NULL;
-+	uint32_t req_size;
-+
-+	req_size = sizeof(struct usb_iso_request);
-+	req_size +=
-+	    (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
-+
-+	pReq = kmalloc(req_size, gfp_flags);
-+	if (!pReq) {
-+		DWC_WARN("Can't allocate Iso Request\n");
-+		return 0;
-+	}
-+	pReq->iso_packet_desc0 = (void *)(pReq + 1);
-+
-+	pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
-+
-+	return pReq;
-+}
-+
-+static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
-+{
-+	kfree(req);
-+}
-+
-+static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
-+	.ep_ops = {
-+		   .enable = ep_enable,
-+		   .disable = ep_disable,
-+
-+		   .alloc_request = dwc_otg_pcd_alloc_request,
-+		   .free_request = dwc_otg_pcd_free_request,
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+		   .alloc_buffer = dwc_otg_pcd_alloc_buffer,
-+		   .free_buffer = dwc_otg_pcd_free_buffer,
-+#endif
-+
-+		   .queue = ep_queue,
-+		   .dequeue = ep_dequeue,
-+
-+		   .set_halt = ep_halt,
-+		   .fifo_status = 0,
-+		   .fifo_flush = 0,
-+		   },
-+	.iso_ep_start = iso_ep_start,
-+	.iso_ep_stop = iso_ep_stop,
-+	.alloc_iso_request = alloc_iso_request,
-+	.free_iso_request = free_iso_request,
-+};
-+
-+#else
-+
-+	int (*enable) (struct usb_ep *ep,
-+		const struct usb_endpoint_descriptor *desc);
-+	int (*disable) (struct usb_ep *ep);
-+
-+	struct usb_request *(*alloc_request) (struct usb_ep *ep,
-+		gfp_t gfp_flags);
-+	void (*free_request) (struct usb_ep *ep, struct usb_request *req);
-+
-+	int (*queue) (struct usb_ep *ep, struct usb_request *req,
-+		gfp_t gfp_flags);
-+	int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
-+
-+	int (*set_halt) (struct usb_ep *ep, int value);
-+	int (*set_wedge) (struct usb_ep *ep);
-+
-+	int (*fifo_status) (struct usb_ep *ep);
-+	void (*fifo_flush) (struct usb_ep *ep);
-+static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
-+	.enable = ep_enable,
-+	.disable = ep_disable,
-+
-+	.alloc_request = dwc_otg_pcd_alloc_request,
-+	.free_request = dwc_otg_pcd_free_request,
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
-+	.alloc_buffer = dwc_otg_pcd_alloc_buffer,
-+	.free_buffer = dwc_otg_pcd_free_buffer,
-+#else
-+	/* .set_wedge = ep_wedge, */
-+        .set_wedge = NULL, /* uses set_halt instead */
-+#endif
-+
-+	.queue = ep_queue,
-+	.dequeue = ep_dequeue,
-+
-+	.set_halt = ep_halt,
-+	.fifo_status = 0,
-+	.fifo_flush = 0,
-+
-+};
-+
-+#endif /* _EN_ISOC_ */
-+/*	Gadget Operations */
-+/**
-+ * The following gadget operations will be implemented in the DWC_otg
-+ * PCD. Functions in the API that are not described below are not
-+ * implemented.
-+ *
-+ * The Gadget API provides wrapper functions for each of the function
-+ * pointers defined in usb_gadget_ops. The Gadget Driver calls the
-+ * wrapper function, which then calls the underlying PCD function. The
-+ * following sections are named according to the wrapper functions
-+ * (except for ioctl, which doesn't have a wrapper function). Within
-+ * each section, the corresponding DWC_otg PCD function name is
-+ * specified.
-+ *
-+ */
-+
-+/**
-+ *Gets the USB Frame number of the last SOF.
-+ */
-+static int get_frame_number(struct usb_gadget *gadget)
-+{
-+	struct gadget_wrapper *d;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
-+
-+	if (gadget == 0) {
-+		return -ENODEV;
-+	}
-+
-+	d = container_of(gadget, struct gadget_wrapper, gadget);
-+	return dwc_otg_pcd_get_frame_number(d->pcd);
-+}
-+
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+static int test_lpm_enabled(struct usb_gadget *gadget)
-+{
-+	struct gadget_wrapper *d;
-+
-+	d = container_of(gadget, struct gadget_wrapper, gadget);
-+
-+	return dwc_otg_pcd_is_lpm_enabled(d->pcd);
-+}
-+#endif
-+
-+/**
-+ * Initiates Session Request Protocol (SRP) to wakeup the host if no
-+ * session is in progress. If a session is already in progress, but
-+ * the device is suspended, remote wakeup signaling is started.
-+ *
-+ */
-+static int wakeup(struct usb_gadget *gadget)
-+{
-+	struct gadget_wrapper *d;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
-+
-+	if (gadget == 0) {
-+		return -ENODEV;
-+	} else {
-+		d = container_of(gadget, struct gadget_wrapper, gadget);
-+	}
-+	dwc_otg_pcd_wakeup(d->pcd);
-+	return 0;
-+}
-+
-+static const struct usb_gadget_ops dwc_otg_pcd_ops = {
-+	.get_frame = get_frame_number,
-+	.wakeup = wakeup,
-+#ifdef CONFIG_USB_DWC_OTG_LPM
-+	.lpm_support = test_lpm_enabled,
-+#endif
-+	// current versions must always be self-powered
-+};
-+
-+static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
-+{
-+	int retval = -DWC_E_NOT_SUPPORTED;
-+	if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
-+		retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
-+						       (struct usb_ctrlrequest
-+							*)bytes);
-+	}
-+
-+	if (retval == -ENOTSUPP) {
-+		retval = -DWC_E_NOT_SUPPORTED;
-+	} else if (retval < 0) {
-+		retval = -DWC_E_INVALID;
-+	}
-+
-+	return retval;
-+}
-+
-+#ifdef DWC_EN_ISOC
-+static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+			  void *req_handle, int proc_buf_num)
-+{
-+	int i, packet_count;
-+	struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
-+	struct usb_iso_request *iso_req = req_handle;
-+
-+	if (proc_buf_num) {
-+		iso_packet = iso_req->iso_packet_desc1;
-+	} else {
-+		iso_packet = iso_req->iso_packet_desc0;
-+	}
-+	packet_count =
-+	    dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
-+	for (i = 0; i < packet_count; ++i) {
-+		int status;
-+		int actual;
-+		int offset;
-+		dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
-+						  i, &status, &actual, &offset);
-+		switch (status) {
-+		case -DWC_E_NO_DATA:
-+			status = -ENODATA;
-+			break;
-+		default:
-+			if (status) {
-+				DWC_PRINTF("unknown status in isoc packet\n");
-+			}
-+
-+		}
-+		iso_packet[i].status = status;
-+		iso_packet[i].offset = offset;
-+		iso_packet[i].actual_length = actual;
-+	}
-+
-+	iso_req->status = 0;
-+	iso_req->process_buffer(ep_handle, iso_req);
-+
-+	return 0;
-+}
-+#endif /* DWC_EN_ISOC */
-+
-+#ifdef DWC_UTE_PER_IO
-+/**
-+ * Copy the contents of the extended request to the Linux usb_request's
-+ * extended part and call the gadget's completion.
-+ *
-+ * @param pcd			Pointer to the pcd structure
-+ * @param ep_handle		Void pointer to the usb_ep structure
-+ * @param req_handle	Void pointer to the usb_request structure
-+ * @param status		Request status returned from the portable logic
-+ * @param ereq_port		Void pointer to the extended request structure
-+ *						created in the the portable part that contains the
-+ *						results of the processed iso packets.
-+ */
-+static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+			   void *req_handle, int32_t status, void *ereq_port)
-+{
-+	struct dwc_ute_iso_req_ext *ereqorg = NULL;
-+	struct dwc_iso_xreq_port *ereqport = NULL;
-+	struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
-+	int i;
-+	struct usb_request *req;
-+	//struct dwc_ute_iso_packet_descriptor *
-+	//int status = 0;
-+
-+	req = (struct usb_request *)req_handle;
-+	ereqorg = &req->ext_req;
-+	ereqport = (struct dwc_iso_xreq_port *)ereq_port;
-+	desc_org = ereqorg->per_io_frame_descs;
-+
-+	if (req && req->complete) {
-+		/* Copy the request data from the portable logic to our request */
-+		for (i = 0; i < ereqport->pio_pkt_count; i++) {
-+			desc_org[i].actual_length =
-+			    ereqport->per_io_frame_descs[i].actual_length;
-+			desc_org[i].status =
-+			    ereqport->per_io_frame_descs[i].status;
-+		}
-+
-+		switch (status) {
-+		case -DWC_E_SHUTDOWN:
-+			req->status = -ESHUTDOWN;
-+			break;
-+		case -DWC_E_RESTART:
-+			req->status = -ECONNRESET;
-+			break;
-+		case -DWC_E_INVALID:
-+			req->status = -EINVAL;
-+			break;
-+		case -DWC_E_TIMEOUT:
-+			req->status = -ETIMEDOUT;
-+			break;
-+		default:
-+			req->status = status;
-+		}
-+
-+		/* And call the gadget's completion */
-+		req->complete(ep_handle, req);
-+	}
-+
-+	return 0;
-+}
-+#endif /* DWC_UTE_PER_IO */
-+
-+static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
-+		     void *req_handle, int32_t status, uint32_t actual)
-+{
-+	struct usb_request *req = (struct usb_request *)req_handle;
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
-+	struct dwc_otg_pcd_ep *ep = NULL;
-+#endif
-+
-+	if (req && req->complete) {
-+		switch (status) {
-+		case -DWC_E_SHUTDOWN:
-+			req->status = -ESHUTDOWN;
-+			break;
-+		case -DWC_E_RESTART:
-+			req->status = -ECONNRESET;
-+			break;
-+		case -DWC_E_INVALID:
-+			req->status = -EINVAL;
-+			break;
-+		case -DWC_E_TIMEOUT:
-+			req->status = -ETIMEDOUT;
-+			break;
-+		default:
-+			req->status = status;
-+
-+		}
-+
-+		req->actual = actual;
-+		DWC_SPINUNLOCK(pcd->lock);
-+		req->complete(ep_handle, req);
-+		DWC_SPINLOCK(pcd->lock);
-+	}
-+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
-+	ep = ep_from_handle(pcd, ep_handle);
-+	if (GET_CORE_IF(pcd)->dma_enable) {
-+                if (req->length != 0) {
-+                        dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
-+                        struct device *dev = NULL;
-+
-+                        if (otg_dev != NULL)
-+                                  dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
-+
-+			dma_unmap_single(dev, req->dma, req->length,
-+                                         ep->dwc_ep.is_in ?
-+                                                DMA_TO_DEVICE: DMA_FROM_DEVICE);
-+                }
-+	}
-+#endif
-+
-+	return 0;
-+}
-+
-+static int _connect(dwc_otg_pcd_t * pcd, int speed)
-+{
-+	gadget_wrapper->gadget.speed = speed;
-+	return 0;
-+}
-+
-+static int _disconnect(dwc_otg_pcd_t * pcd)
-+{
-+	if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
-+		gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
-+	}
-+	return 0;
-+}
-+
-+static int _resume(dwc_otg_pcd_t * pcd)
-+{
-+	if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
-+		gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
-+	}
-+
-+	return 0;
-+}
-+
-+static int _suspend(dwc_otg_pcd_t * pcd)
-+{
-+	if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
-+		gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
-+	}
-+	return 0;
-+}
-+
-+/**
-+ * This function updates the otg values in the gadget structure.
-+ */
-+static int _hnp_changed(dwc_otg_pcd_t * pcd)
-+{
-+
-+	if (!gadget_wrapper->gadget.is_otg)
-+		return 0;
-+
-+	gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
-+	gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
-+	gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
-+	return 0;
-+}
-+
-+static int _reset(dwc_otg_pcd_t * pcd)
-+{
-+	return 0;
-+}
-+
-+#ifdef DWC_UTE_CFI
-+static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
-+{
-+	int retval = -DWC_E_INVALID;
-+	if (gadget_wrapper->driver->cfi_feature_setup) {
-+		retval =
-+		    gadget_wrapper->driver->
-+		    cfi_feature_setup(&gadget_wrapper->gadget,
-+				      (struct cfi_usb_ctrlrequest *)cfi_req);
-+	}
-+
-+	return retval;
-+}
-+#endif
-+
-+static const struct dwc_otg_pcd_function_ops fops = {
-+	.complete = _complete,
-+#ifdef DWC_EN_ISOC
-+	.isoc_complete = _isoc_complete,
-+#endif
-+	.setup = _setup,
-+	.disconnect = _disconnect,
-+	.connect = _connect,
-+	.resume = _resume,
-+	.suspend = _suspend,
-+	.hnp_changed = _hnp_changed,
-+	.reset = _reset,
-+#ifdef DWC_UTE_CFI
-+	.cfi_setup = _cfi_setup,
-+#endif
-+#ifdef DWC_UTE_PER_IO
-+	.xisoc_complete = _xisoc_complete,
-+#endif
-+};
-+
-+/**
-+ * This function is the top level PCD interrupt handler.
-+ */
-+static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
-+{
-+	dwc_otg_pcd_t *pcd = dev;
-+	int32_t retval = IRQ_NONE;
-+
-+	retval = dwc_otg_pcd_handle_intr(pcd);
-+	if (retval != 0) {
-+		S3C2410X_CLEAR_EINTPEND();
-+	}
-+	return IRQ_RETVAL(retval);
-+}
-+
-+/**
-+ * This function initialized the usb_ep structures to there default
-+ * state.
-+ *
-+ * @param d Pointer on gadget_wrapper.
-+ */
-+void gadget_add_eps(struct gadget_wrapper *d)
-+{
-+	static const char *names[] = {
-+
-+		"ep0",
-+		"ep1in",
-+		"ep2in",
-+		"ep3in",
-+		"ep4in",
-+		"ep5in",
-+		"ep6in",
-+		"ep7in",
-+		"ep8in",
-+		"ep9in",
-+		"ep10in",
-+		"ep11in",
-+		"ep12in",
-+		"ep13in",
-+		"ep14in",
-+		"ep15in",
-+		"ep1out",
-+		"ep2out",
-+		"ep3out",
-+		"ep4out",
-+		"ep5out",
-+		"ep6out",
-+		"ep7out",
-+		"ep8out",
-+		"ep9out",
-+		"ep10out",
-+		"ep11out",
-+		"ep12out",
-+		"ep13out",
-+		"ep14out",
-+		"ep15out"
-+	};
-+
-+	int i;
-+	struct usb_ep *ep;
-+	int8_t dev_endpoints;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
-+
-+	INIT_LIST_HEAD(&d->gadget.ep_list);
-+	d->gadget.ep0 = &d->ep0;
-+	d->gadget.speed = USB_SPEED_UNKNOWN;
-+
-+	INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
-+
-+	/**
-+	 * Initialize the EP0 structure.
-+	 */
-+	ep = &d->ep0;
-+
-+	/* Init the usb_ep structure. */
-+	ep->name = names[0];
-+	ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+	/**
-+	 * @todo NGS: What should the max packet size be set to
-+	 * here?  Before EP type is set?
-+	 */
-+	ep->maxpacket = MAX_PACKET_SIZE;
-+	dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
-+
-+	list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+
-+	/**
-+	 * Initialize the EP structures.
-+	 */
-+	dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
-+
-+	for (i = 0; i < dev_endpoints; i++) {
-+		ep = &d->in_ep[i];
-+
-+		/* Init the usb_ep structure. */
-+		ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
-+		ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+		/**
-+		 * @todo NGS: What should the max packet size be set to
-+		 * here?  Before EP type is set?
-+		 */
-+		ep->maxpacket = MAX_PACKET_SIZE;
-+		list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+	}
-+
-+	dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
-+
-+	for (i = 0; i < dev_endpoints; i++) {
-+		ep = &d->out_ep[i];
-+
-+		/* Init the usb_ep structure. */
-+		ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
-+		ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
-+
-+		/**
-+		 * @todo NGS: What should the max packet size be set to
-+		 * here?  Before EP type is set?
-+		 */
-+		ep->maxpacket = MAX_PACKET_SIZE;
-+
-+		list_add_tail(&ep->ep_list, &d->gadget.ep_list);
-+	}
-+
-+	/* remove ep0 from the list.  There is a ep0 pointer. */
-+	list_del_init(&d->ep0.ep_list);
-+
-+	d->ep0.maxpacket = MAX_EP0_SIZE;
-+}
-+
-+/**
-+ * This function releases the Gadget device.
-+ * required by device_unregister().
-+ *
-+ * @todo Should this do something?	Should it free the PCD?
-+ */
-+static void dwc_otg_pcd_gadget_release(struct device *dev)
-+{
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
-+}
-+
-+static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)
-+{
-+	static char pcd_name[] = "dwc_otg_pcd";
-+	dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+	struct gadget_wrapper *d;
-+	int retval;
-+
-+	d = DWC_ALLOC(sizeof(*d));
-+	if (d == NULL) {
-+		return NULL;
-+	}
-+
-+	memset(d, 0, sizeof(*d));
-+
-+	d->gadget.name = pcd_name;
-+	d->pcd = otg_dev->pcd;
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
-+	strcpy(d->gadget.dev.bus_id, "gadget");
-+#else
-+	dev_set_name(&d->gadget.dev, "%s", "gadget");
-+#endif
-+
-+	d->gadget.dev.parent = &_dev->dev;
-+	d->gadget.dev.release = dwc_otg_pcd_gadget_release;
-+	d->gadget.ops = &dwc_otg_pcd_ops;
-+	d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;
-+	d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
-+
-+	d->driver = 0;
-+	/* Register the gadget device */
-+	retval = device_register(&d->gadget.dev);
-+	if (retval != 0) {
-+		DWC_ERROR("device_register failed\n");
-+		DWC_FREE(d);
-+		return NULL;
-+	}
-+
-+	return d;
-+}
-+
-+static void free_wrapper(struct gadget_wrapper *d)
-+{
-+	if (d->driver) {
-+		/* should have been done already by driver model core */
-+		DWC_WARN("driver '%s' is still registered\n",
-+			 d->driver->driver.name);
-+#ifdef CONFIG_USB_GADGET
-+		usb_gadget_unregister_driver(d->driver);
-+#endif
-+	}
-+
-+	device_unregister(&d->gadget.dev);
-+	DWC_FREE(d);
-+}
-+
-+/**
-+ * This function initialized the PCD portion of the driver.
-+ *
-+ */
-+int pcd_init(dwc_bus_dev_t *_dev)
-+{
-+	dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+	int retval = 0;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
-+
-+	otg_dev->pcd = dwc_otg_pcd_init(otg_dev);
-+
-+	if (!otg_dev->pcd) {
-+		DWC_ERROR("dwc_otg_pcd_init failed\n");
-+		return -ENOMEM;
-+	}
-+
-+	otg_dev->pcd->otg_dev = otg_dev;
-+	gadget_wrapper = alloc_wrapper(_dev);
-+
-+	/*
-+	 * Initialize EP structures
-+	 */
-+	gadget_add_eps(gadget_wrapper);
-+	/*
-+	 * Setup interupt handler
-+	 */
-+#ifdef PLATFORM_INTERFACE
-+	DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
-+                    platform_get_irq(_dev, fiq_enable ? 0 : 1));
-+	retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq,
-+			     IRQF_SHARED, gadget_wrapper->gadget.name,
-+			     otg_dev->pcd);
-+	if (retval != 0) {
-+		DWC_ERROR("request of irq%d failed\n",
-+                          platform_get_irq(_dev, fiq_enable ? 0 : 1));
-+		free_wrapper(gadget_wrapper);
-+		return -EBUSY;
-+	}
-+#else
-+	DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
-+                    _dev->irq);
-+	retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
-+			     IRQF_SHARED | IRQF_DISABLED,
-+			     gadget_wrapper->gadget.name, otg_dev->pcd);
-+	if (retval != 0) {
-+		DWC_ERROR("request of irq%d failed\n", _dev->irq);
-+		free_wrapper(gadget_wrapper);
-+		return -EBUSY;
-+	}
-+#endif
-+
-+	dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
-+
-+	return retval;
-+}
-+
-+/**
-+ * Cleanup the PCD.
-+ */
-+void pcd_remove(dwc_bus_dev_t *_dev)
-+{
-+	dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
-+	dwc_otg_pcd_t *pcd = otg_dev->pcd;
-+
-+	DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
-+
-+	/*
-+	 * Free the IRQ
-+	 */
-+#ifdef PLATFORM_INTERFACE
-+	free_irq(platform_get_irq(_dev, 0), pcd);
-+#else
-+	free_irq(_dev->irq, pcd);
-+#endif
-+	dwc_otg_pcd_remove(otg_dev->pcd);
-+	free_wrapper(gadget_wrapper);
-+	otg_dev->pcd = 0;
-+}
-+
-+#endif /* DWC_HOST_ONLY */
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_regs.h
-@@ -0,0 +1,2550 @@
-+/* ==========================================================================
-+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
-+ * $Revision: #98 $
-+ * $Date: 2012/08/10 $
-+ * $Change: 2047372 $
-+ *
-+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
-+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
-+ * otherwise expressly agreed to in writing between Synopsys and you.
-+ *
-+ * The Software IS NOT an item of Licensed Software or Licensed Product under
-+ * any End User Software License Agreement or Agreement for Licensed Product
-+ * with Synopsys or any supplement thereto. You are permitted to use and
-+ * redistribute this Software in source and binary forms, with or without
-+ * modification, provided that redistributions of source code must retain this
-+ * notice. You may not view, use, disclose, copy or distribute this file or
-+ * any information contained herein except pursuant to this license grant from
-+ * Synopsys. If you do not agree with this notice, including the disclaimer
-+ * below, then you are not authorized to use the Software.
-+ *
-+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
-+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-+ * DAMAGE.
-+ * ========================================================================== */
-+
-+#ifndef __DWC_OTG_REGS_H__
-+#define __DWC_OTG_REGS_H__
-+
-+#include "dwc_otg_core_if.h"
-+
-+/**
-+ * @file
-+ *
-+ * This file contains the data structures for accessing the DWC_otg core registers.
-+ *
-+ * The application interfaces with the HS OTG core by reading from and
-+ * writing to the Control and Status Register (CSR) space through the
-+ * AHB Slave interface. These registers are 32 bits wide, and the
-+ * addresses are 32-bit-block aligned.
-+ * CSRs are classified as follows:
-+ * - Core Global Registers
-+ * - Device Mode Registers
-+ * - Device Global Registers
-+ * - Device Endpoint Specific Registers
-+ * - Host Mode Registers
-+ * - Host Global Registers
-+ * - Host Port CSRs
-+ * - Host Channel Specific Registers
-+ *
-+ * Only the Core Global registers can be accessed in both Device and
-+ * Host modes. When the HS OTG core is operating in one mode, either
-+ * Device or Host, the application must not access registers from the
-+ * other mode. When the core switches from one mode to another, the
-+ * registers in the new mode of operation must be reprogrammed as they
-+ * would be after a power-on reset.
-+ */
-+
-+/****************************************************************************/
-+/** DWC_otg Core registers .
-+ * The dwc_otg_core_global_regs structure defines the size
-+ * and relative field offsets for the Core Global registers.
-+ */
-+typedef struct dwc_otg_core_global_regs {
-+	/** OTG Control and Status Register.  <i>Offset: 000h</i> */
-+	volatile uint32_t gotgctl;
-+	/** OTG Interrupt Register.	 <i>Offset: 004h</i> */
-+	volatile uint32_t gotgint;
-+	/**Core AHB Configuration Register.	 <i>Offset: 008h</i> */
-+	volatile uint32_t gahbcfg;
-+
-+#define DWC_GLBINTRMASK		0x0001
-+#define DWC_DMAENABLE		0x0020
-+#define DWC_NPTXEMPTYLVL_EMPTY	0x0080
-+#define DWC_NPTXEMPTYLVL_HALFEMPTY	0x0000
-+#define DWC_PTXEMPTYLVL_EMPTY	0x0100
-+#define DWC_PTXEMPTYLVL_HALFEMPTY	0x0000
-+
-+	/**Core USB Configuration Register.	 <i>Offset: 00Ch</i> */
-+	volatile uint32_t gusbcfg;
-+	/**Core Reset Register.	 <i>Offset: 010h</i> */
-+	volatile uint32_t grstctl;
-+	/**Core Interrupt Register.	 <i>Offset: 014h</i> */
-+	volatile uint32_t gintsts;
-+	/**Core Interrupt Mask Register.  <i>Offset: 018h</i> */
-+	volatile uint32_t gintmsk;
-+	/**Receive Status Queue Read Register (Read Only).	<i>Offset: 01Ch</i> */
-+	volatile uint32_t grxstsr;
-+	/**Receive Status Queue Read & POP Register (Read Only).  <i>Offset: 020h</i>*/
-+	volatile uint32_t grxstsp;
-+	/**Receive FIFO Size Register.	<i>Offset: 024h</i> */
-+	volatile uint32_t grxfsiz;
-+	/**Non Periodic Transmit FIFO Size Register.  <i>Offset: 028h</i> */
-+	volatile uint32_t gnptxfsiz;
-+	/**Non Periodic Transmit FIFO/Queue Status Register (Read
-+	 * Only). <i>Offset: 02Ch</i> */
-+	volatile uint32_t gnptxsts;
-+	/**I2C Access Register.	 <i>Offset: 030h</i> */
-+	volatile uint32_t gi2cctl;
-+	/**PHY Vendor Control Register.	 <i>Offset: 034h</i> */
-+	volatile uint32_t gpvndctl;
-+	/**General Purpose Input/Output Register.  <i>Offset: 038h</i> */
-+	volatile uint32_t ggpio;
-+	/**User ID Register.  <i>Offset: 03Ch</i> */
-+	volatile uint32_t guid;
-+	/**Synopsys ID Register (Read Only).  <i>Offset: 040h</i> */
-+	volatile uint32_t gsnpsid;
-+	/**User HW Config1 Register (Read Only).  <i>Offset: 044h</i> */
-+	volatile uint32_t ghwcfg1;
-+	/**User HW Config2 Register (Read Only).  <i>Offset: 048h</i> */
-+	volatile uint32_t ghwcfg2;
-+#define DWC_SLAVE_ONLY_ARCH 0
-+#define DWC_EXT_DMA_ARCH 1
-+#define DWC_INT_DMA_ARCH 2
-+
-+#define DWC_MODE_HNP_SRP_CAPABLE	0
-+#define DWC_MODE_SRP_ONLY_CAPABLE	1
-+#define DWC_MODE_NO_HNP_SRP_CAPABLE		2
-+#define DWC_MODE_SRP_CAPABLE_DEVICE		3
-+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE	4
-+#define DWC_MODE_SRP_CAPABLE_HOST	5
-+#define DWC_MODE_NO_SRP_CAPABLE_HOST	6
-+
-+	/**User HW Config3 Register (Read Only).  <i>Offset: 04Ch</i> */
-+	volatile uint32_t ghwcfg3;
-+	/**User HW Config4 Register (Read Only).  <i>Offset: 050h</i>*/
-+	volatile uint32_t ghwcfg4;
-+	/** Core LPM Configuration register <i>Offset: 054h</i>*/
-+	volatile uint32_t glpmcfg;
-+	/** Global PowerDn Register <i>Offset: 058h</i> */
-+	volatile uint32_t gpwrdn;
-+	/** Global DFIFO SW Config Register  <i>Offset: 05Ch</i> */
-+	volatile uint32_t gdfifocfg;
-+	/** ADP Control Register  <i>Offset: 060h</i> */
-+	volatile uint32_t adpctl;
-+	/** Reserved  <i>Offset: 064h-0FFh</i> */
-+	volatile uint32_t reserved39[39];
-+	/** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
-+	volatile uint32_t hptxfsiz;
-+	/** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
-+		otherwise Device Transmit FIFO#n Register.
-+	 * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
-+	volatile uint32_t dtxfsiz[15];
-+} dwc_otg_core_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields of the Core OTG Control
-+ * and Status Register (GOTGCTL).  Set the bits using the bit
-+ * fields then write the <i>d32</i> value to the register.
-+ */
-+typedef union gotgctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned sesreqscs:1;
-+		unsigned sesreq:1;
-+		unsigned vbvalidoven:1;
-+		unsigned vbvalidovval:1;
-+		unsigned avalidoven:1;
-+		unsigned avalidovval:1;
-+		unsigned bvalidoven:1;
-+		unsigned bvalidovval:1;
-+		unsigned hstnegscs:1;
-+		unsigned hnpreq:1;
-+		unsigned hstsethnpen:1;
-+		unsigned devhnpen:1;
-+		unsigned reserved12_15:4;
-+		unsigned conidsts:1;
-+		unsigned dbnctime:1;
-+		unsigned asesvld:1;
-+		unsigned bsesvld:1;
-+		unsigned otgver:1;
-+		unsigned reserved1:1;
-+		unsigned multvalidbc:5;
-+		unsigned chirpen:1;
-+		unsigned reserved28_31:4;
-+	} b;
-+} gotgctl_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core OTG Interrupt Register
-+ * (GOTGINT).  Set/clear the bits using the bit fields then write the <i>d32</i>
-+ * value to the register.
-+ */
-+typedef union gotgint_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Current Mode */
-+		unsigned reserved0_1:2;
-+
-+		/** Session End Detected */
-+		unsigned sesenddet:1;
-+
-+		unsigned reserved3_7:5;
-+
-+		/** Session Request Success Status Change */
-+		unsigned sesreqsucstschng:1;
-+		/** Host Negotiation Success Status Change */
-+		unsigned hstnegsucstschng:1;
-+
-+		unsigned reserved10_16:7;
-+
-+		/** Host Negotiation Detected */
-+		unsigned hstnegdet:1;
-+		/** A-Device Timeout Change */
-+		unsigned adevtoutchng:1;
-+		/** Debounce Done */
-+		unsigned debdone:1;
-+		/** Multi-Valued input changed */
-+		unsigned mvic:1;
-+
-+		unsigned reserved31_21:11;
-+
-+	} b;
-+} gotgint_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core AHB Configuration
-+ * Register (GAHBCFG). Set/clear the bits using the bit fields then
-+ * write the <i>d32</i> value to the register.
-+ */
-+typedef union gahbcfg_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned glblintrmsk:1;
-+#define DWC_GAHBCFG_GLBINT_ENABLE		1
-+
-+		unsigned hburstlen:4;
-+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE	0
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR		1
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4		3
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8		5
-+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16	7
-+
-+		unsigned dmaenable:1;
-+#define DWC_GAHBCFG_DMAENABLE			1
-+		unsigned reserved:1;
-+		unsigned nptxfemplvl_txfemplvl:1;
-+		unsigned ptxfemplvl:1;
-+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY		1
-+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY	0
-+		unsigned reserved9_20:12;
-+		unsigned remmemsupp:1;
-+		unsigned notialldmawrit:1;
-+		unsigned ahbsingle:1;
-+		unsigned reserved24_31:8;
-+	} b;
-+} gahbcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core USB Configuration
-+ * Register (GUSBCFG). Set the bits using the bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union gusbcfg_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned toutcal:3;
-+		unsigned phyif:1;
-+		unsigned ulpi_utmi_sel:1;
-+		unsigned fsintf:1;
-+		unsigned physel:1;
-+		unsigned ddrsel:1;
-+		unsigned srpcap:1;
-+		unsigned hnpcap:1;
-+		unsigned usbtrdtim:4;
-+		unsigned reserved1:1;
-+		unsigned phylpwrclksel:1;
-+		unsigned otgutmifssel:1;
-+		unsigned ulpi_fsls:1;
-+		unsigned ulpi_auto_res:1;
-+		unsigned ulpi_clk_sus_m:1;
-+		unsigned ulpi_ext_vbus_drv:1;
-+		unsigned ulpi_int_vbus_indicator:1;
-+		unsigned term_sel_dl_pulse:1;
-+		unsigned indicator_complement:1;
-+		unsigned indicator_pass_through:1;
-+		unsigned ulpi_int_prot_dis:1;
-+		unsigned ic_usb_cap:1;
-+		unsigned ic_traffic_pull_remove:1;
-+		unsigned tx_end_delay:1;
-+		unsigned force_host_mode:1;
-+		unsigned force_dev_mode:1;
-+		unsigned reserved31:1;
-+	} b;
-+} gusbcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core Reset Register
-+ * (GRSTCTL).  Set/clear the bits using the bit fields then write the
-+ * <i>d32</i> value to the register.
-+ */
-+typedef union grstctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Core Soft Reset (CSftRst) (Device and Host)
-+		 *
-+		 * The application can flush the control logic in the
-+		 * entire core using this bit. This bit resets the
-+		 * pipelines in the AHB Clock domain as well as the
-+		 * PHY Clock domain.
-+		 *
-+		 * The state machines are reset to an IDLE state, the
-+		 * control bits in the CSRs are cleared, all the
-+		 * transmit FIFOs and the receive FIFO are flushed.
-+		 *
-+		 * The status mask bits that control the generation of
-+		 * the interrupt, are cleared, to clear the
-+		 * interrupt. The interrupt status bits are not
-+		 * cleared, so the application can get the status of
-+		 * any events that occurred in the core after it has
-+		 * set this bit.
-+		 *
-+		 * Any transactions on the AHB are terminated as soon
-+		 * as possible following the protocol. Any
-+		 * transactions on the USB are terminated immediately.
-+		 *
-+		 * The configuration settings in the CSRs are
-+		 * unchanged, so the software doesn't have to
-+		 * reprogram these registers (Device
-+		 * Configuration/Host Configuration/Core System
-+		 * Configuration/Core PHY Configuration).
-+		 *
-+		 * The application can write to this bit, any time it
-+		 * wants to reset the core. This is a self clearing
-+		 * bit and the core clears this bit after all the
-+		 * necessary logic is reset in the core, which may
-+		 * take several clocks, depending on the current state
-+		 * of the core.
-+		 */
-+		unsigned csftrst:1;
-+		/** Hclk Soft Reset
-+		 *
-+		 * The application uses this bit to reset the control logic in
-+		 * the AHB clock domain. Only AHB clock domain pipelines are
-+		 * reset.
-+		 */
-+		unsigned hsftrst:1;
-+		/** Host Frame Counter Reset (Host Only)<br>
-+		 *
-+		 * The application can reset the (micro)frame number
-+		 * counter inside the core, using this bit. When the
-+		 * (micro)frame counter is reset, the subsequent SOF
-+		 * sent out by the core, will have a (micro)frame
-+		 * number of 0.
-+		 */
-+		unsigned hstfrm:1;
-+		/** In Token Sequence Learning Queue Flush
-+		 * (INTknQFlsh) (Device Only)
-+		 */
-+		unsigned intknqflsh:1;
-+		/** RxFIFO Flush (RxFFlsh) (Device and Host)
-+		 *
-+		 * The application can flush the entire Receive FIFO
-+		 * using this bit. The application must first
-+		 * ensure that the core is not in the middle of a
-+		 * transaction. The application should write into
-+		 * this bit, only after making sure that neither the
-+		 * DMA engine is reading from the RxFIFO nor the MAC
-+		 * is writing the data in to the FIFO. The
-+		 * application should wait until the bit is cleared
-+		 * before performing any other operations. This bit
-+		 * will takes 8 clocks (slowest of PHY or AHB clock)
-+		 * to clear.
-+		 */
-+		unsigned rxfflsh:1;
-+		/** TxFIFO Flush (TxFFlsh) (Device and Host).
-+		 *
-+		 * This bit is used to selectively flush a single or
-+		 * all transmit FIFOs. The application must first
-+		 * ensure that the core is not in the middle of a
-+		 * transaction. The application should write into
-+		 * this bit, only after making sure that neither the
-+		 * DMA engine is writing into the TxFIFO nor the MAC
-+		 * is reading the data out of the FIFO. The
-+		 * application should wait until the core clears this
-+		 * bit, before performing any operations. This bit
-+		 * will takes 8 clocks (slowest of PHY or AHB clock)
-+		 * to clear.
-+		 */
-+		unsigned txfflsh:1;
-+
-+		/** TxFIFO Number (TxFNum) (Device and Host).
-+		 *
-+		 * This is the FIFO number which needs to be flushed,
-+		 * using the TxFIFO Flush bit. This field should not
-+		 * be changed until the TxFIFO Flush bit is cleared by
-+		 * the core.
-+		 *	 - 0x0 : Non Periodic TxFIFO Flush
-+		 *	 - 0x1 : Periodic TxFIFO #1 Flush in device mode
-+		 *	   or Periodic TxFIFO in host mode
-+		 *	 - 0x2 : Periodic TxFIFO #2 Flush in device mode.
-+		 *	 - ...
-+		 *	 - 0xF : Periodic TxFIFO #15 Flush in device mode
-+		 *	 - 0x10: Flush all the Transmit NonPeriodic and
-+		 *	   Transmit Periodic FIFOs in the core
-+		 */
-+		unsigned txfnum:5;
-+		/** Reserved */
-+		unsigned reserved11_29:19;
-+		/** DMA Request Signal.	 Indicated DMA request is in
-+		 * probress. Used for debug purpose. */
-+		unsigned dmareq:1;
-+		/** AHB Master Idle.  Indicates the AHB Master State
-+		 * Machine is in IDLE condition. */
-+		unsigned ahbidle:1;
-+	} b;
-+} grstctl_t;
-+
-+/**
-+ * This union represents the bit fields of the Core Interrupt Mask
-+ * Register (GINTMSK). Set/clear the bits using the bit fields then
-+ * write the <i>d32</i> value to the register.
-+ */
-+typedef union gintmsk_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned reserved0:1;
-+		unsigned modemismatch:1;
-+		unsigned otgintr:1;
-+		unsigned sofintr:1;
-+		unsigned rxstsqlvl:1;
-+		unsigned nptxfempty:1;
-+		unsigned ginnakeff:1;
-+		unsigned goutnakeff:1;
-+		unsigned ulpickint:1;
-+		unsigned i2cintr:1;
-+		unsigned erlysuspend:1;
-+		unsigned usbsuspend:1;
-+		unsigned usbreset:1;
-+		unsigned enumdone:1;
-+		unsigned isooutdrop:1;
-+		unsigned eopframe:1;
-+		unsigned restoredone:1;
-+		unsigned epmismatch:1;
-+		unsigned inepintr:1;
-+		unsigned outepintr:1;
-+		unsigned incomplisoin:1;
-+		unsigned incomplisoout:1;
-+		unsigned fetsusp:1;
-+		unsigned resetdet:1;
-+		unsigned portintr:1;
-+		unsigned hcintr:1;
-+		unsigned ptxfempty:1;
-+		unsigned lpmtranrcvd:1;
-+		unsigned conidstschng:1;
-+		unsigned disconnect:1;
-+		unsigned sessreqintr:1;
-+		unsigned wkupintr:1;
-+	} b;
-+} gintmsk_data_t;
-+/**
-+ * This union represents the bit fields of the Core Interrupt Register
-+ * (GINTSTS).  Set/clear the bits using the bit fields then write the
-+ * <i>d32</i> value to the register.
-+ */
-+typedef union gintsts_data {
-+	/** raw register data */
-+	uint32_t d32;
-+#define DWC_SOF_INTR_MASK 0x0008
-+	/** register bits */
-+	struct {
-+#define DWC_HOST_MODE 1
-+		unsigned curmode:1;
-+		unsigned modemismatch:1;
-+		unsigned otgintr:1;
-+		unsigned sofintr:1;
-+		unsigned rxstsqlvl:1;
-+		unsigned nptxfempty:1;
-+		unsigned ginnakeff:1;
-+		unsigned goutnakeff:1;
-+		unsigned ulpickint:1;
-+		unsigned i2cintr:1;
-+		unsigned erlysuspend:1;
-+		unsigned usbsuspend:1;
-+		unsigned usbreset:1;
-+		unsigned enumdone:1;
-+		unsigned isooutdrop:1;
-+		unsigned eopframe:1;
-+		unsigned restoredone:1;
-+		unsigned epmismatch:1;
-+		unsigned inepint:1;
-+		unsigned outepintr:1;
-+		unsigned incomplisoin:1;
-+		unsigned incomplisoout:1;
-+		unsigned fetsusp:1;
-+		unsigned resetdet:1;
-+		unsigned portintr:1;
-+		unsigned hcintr:1;
-+		unsigned ptxfempty:1;
-+		unsigned lpmtranrcvd:1;
-+		unsigned conidstschng:1;
-+		unsigned disconnect:1;
-+		unsigned sessreqintr:1;
-+		unsigned wkupintr:1;
-+	} b;
-+} gintsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Receive Status Read and
-+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
-+ * element then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union device_grxsts_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned epnum:4;
-+		unsigned bcnt:11;
-+		unsigned dpid:2;
-+
-+#define DWC_STS_DATA_UPDT		0x2	// OUT Data Packet
-+#define DWC_STS_XFER_COMP		0x3	// OUT Data Transfer Complete
-+
-+#define DWC_DSTS_GOUT_NAK		0x1	// Global OUT NAK
-+#define DWC_DSTS_SETUP_COMP		0x4	// Setup Phase Complete
-+#define DWC_DSTS_SETUP_UPDT 0x6	// SETUP Packet
-+		unsigned pktsts:4;
-+		unsigned fn:4;
-+		unsigned reserved25_31:7;
-+	} b;
-+} device_grxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Receive Status Read and
-+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
-+ * element then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union host_grxsts_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned chnum:4;
-+		unsigned bcnt:11;
-+		unsigned dpid:2;
-+
-+		unsigned pktsts:4;
-+#define DWC_GRXSTS_PKTSTS_IN			  0x2
-+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP	  0x3
-+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
-+#define DWC_GRXSTS_PKTSTS_CH_HALTED		  0x7
-+
-+		unsigned reserved21_31:11;
-+	} b;
-+} host_grxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
-+ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
-+ * then read out the bits using the <i>b</i>it elements.
-+ */
-+typedef union fifosize_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned startaddr:16;
-+		unsigned depth:16;
-+	} b;
-+} fifosize_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Non-Periodic Transmit
-+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
-+ * <i>d32</i> element then read out the bits using the <i>b</i>it
-+ * elements.
-+ */
-+typedef union gnptxsts_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned nptxfspcavail:16;
-+		unsigned nptxqspcavail:8;
-+		/** Top of the Non-Periodic Transmit Request Queue
-+		 *	- bit 24 - Terminate (Last entry for the selected
-+		 *	  channel/EP)
-+		 *	- bits 26:25 - Token Type
-+		 *	  - 2'b00 - IN/OUT
-+		 *	  - 2'b01 - Zero Length OUT
-+		 *	  - 2'b10 - PING/Complete Split
-+		 *	  - 2'b11 - Channel Halt
-+		 *	- bits 30:27 - Channel/EP Number
-+		 */
-+		unsigned nptxqtop_terminate:1;
-+		unsigned nptxqtop_token:2;
-+		unsigned nptxqtop_chnep:4;
-+		unsigned reserved:1;
-+	} b;
-+} gnptxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Transmit
-+ * FIFO Status Register (DTXFSTS). Read the register into the
-+ * <i>d32</i> element then read out the bits using the <i>b</i>it
-+ * elements.
-+ */
-+typedef union dtxfsts_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned txfspcavail:16;
-+		unsigned reserved:16;
-+	} b;
-+} dtxfsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the I2C Control Register
-+ * (I2CCTL). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gi2cctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned rwdata:8;
-+		unsigned regaddr:8;
-+		unsigned addr:7;
-+		unsigned i2cen:1;
-+		unsigned ack:1;
-+		unsigned i2csuspctl:1;
-+		unsigned i2cdevaddr:2;
-+		unsigned i2cdatse0:1;
-+		unsigned reserved:1;
-+		unsigned rw:1;
-+		unsigned bsydne:1;
-+	} b;
-+} gi2cctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the PHY Vendor Control Register
-+ * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gpvndctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned regdata:8;
-+		unsigned vctrl:8;
-+		unsigned regaddr16_21:6;
-+		unsigned regwr:1;
-+		unsigned reserved23_24:2;
-+		unsigned newregreq:1;
-+		unsigned vstsbsy:1;
-+		unsigned vstsdone:1;
-+		unsigned reserved28_30:3;
-+		unsigned disulpidrvr:1;
-+	} b;
-+} gpvndctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the General Purpose
-+ * Input/Output Register (GGPIO).
-+ * Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union ggpio_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned gpi:16;
-+		unsigned gpo:16;
-+	} b;
-+} ggpio_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User ID Register
-+ * (GUID). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union guid_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned rwdata:32;
-+	} b;
-+} guid_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Synopsys ID Register
-+ * (GSNPSID). Read the register into the <i>d32</i> element then read out the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gsnpsid_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned rwdata:32;
-+	} b;
-+} gsnpsid_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config1
-+ * Register.  Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg1_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned ep_dir0:2;
-+		unsigned ep_dir1:2;
-+		unsigned ep_dir2:2;
-+		unsigned ep_dir3:2;
-+		unsigned ep_dir4:2;
-+		unsigned ep_dir5:2;
-+		unsigned ep_dir6:2;
-+		unsigned ep_dir7:2;
-+		unsigned ep_dir8:2;
-+		unsigned ep_dir9:2;
-+		unsigned ep_dir10:2;
-+		unsigned ep_dir11:2;
-+		unsigned ep_dir12:2;
-+		unsigned ep_dir13:2;
-+		unsigned ep_dir14:2;
-+		unsigned ep_dir15:2;
-+	} b;
-+} hwcfg1_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config2
-+ * Register.  Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg2_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/* GHWCFG2 */
-+		unsigned op_mode:3;
-+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
-+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
-+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
-+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
-+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
-+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
-+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
-+
-+		unsigned architecture:2;
-+		unsigned point2point:1;
-+		unsigned hs_phy_type:2;
-+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
-+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
-+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
-+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
-+
-+		unsigned fs_phy_type:2;
-+		unsigned num_dev_ep:4;
-+		unsigned num_host_chan:4;
-+		unsigned perio_ep_supported:1;
-+		unsigned dynamic_fifo:1;
-+		unsigned multi_proc_int:1;
-+		unsigned reserved21:1;
-+		unsigned nonperio_tx_q_depth:2;
-+		unsigned host_perio_tx_q_depth:2;
-+		unsigned dev_token_q_depth:5;
-+		unsigned otg_enable_ic_usb:1;
-+	} b;
-+} hwcfg2_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config3
-+ * Register.  Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg3_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/* GHWCFG3 */
-+		unsigned xfer_size_cntr_width:4;
-+		unsigned packet_size_cntr_width:3;
-+		unsigned otg_func:1;
-+		unsigned i2c:1;
-+		unsigned vendor_ctrl_if:1;
-+		unsigned optional_features:1;
-+		unsigned synch_reset_type:1;
-+		unsigned adp_supp:1;
-+		unsigned otg_enable_hsic:1;
-+		unsigned bc_support:1;
-+		unsigned otg_lpm_en:1;
-+		unsigned dfifo_depth:16;
-+	} b;
-+} hwcfg3_data_t;
-+
-+/**
-+ * This union represents the bit fields in the User HW Config4
-+ * Register.  Read the register into the <i>d32</i> element then read
-+ * out the bits using the <i>b</i>it elements.
-+ */
-+typedef union hwcfg4_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned num_dev_perio_in_ep:4;
-+		unsigned power_optimiz:1;
-+		unsigned min_ahb_freq:1;
-+		unsigned hiber:1;
-+		unsigned xhiber:1;
-+		unsigned reserved:6;
-+		unsigned utmi_phy_data_width:2;
-+		unsigned num_dev_mode_ctrl_ep:4;
-+		unsigned iddig_filt_en:1;
-+		unsigned vbus_valid_filt_en:1;
-+		unsigned a_valid_filt_en:1;
-+		unsigned b_valid_filt_en:1;
-+		unsigned session_end_filt_en:1;
-+		unsigned ded_fifo_en:1;
-+		unsigned num_in_eps:4;
-+		unsigned desc_dma:1;
-+		unsigned desc_dma_dyn:1;
-+	} b;
-+} hwcfg4_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core LPM Configuration
-+ * Register (GLPMCFG). Set the bits using bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union glpmctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** LPM-Capable (LPMCap) (Device and Host)
-+		 * The application uses this bit to control
-+		 * the DWC_otg core LPM capabilities.
-+		 */
-+		unsigned lpm_cap_en:1;
-+		/** LPM response programmed by application (AppL1Res) (Device)
-+		 * Handshake response to LPM token pre-programmed
-+		 * by device application software.
-+		 */
-+		unsigned appl_resp:1;
-+		/** Host Initiated Resume Duration (HIRD) (Device and Host)
-+		 * In Host mode this field indicates the value of HIRD
-+		 * to be sent in an LPM transaction.
-+		 * In Device mode this field is updated with the
-+		 * Received LPM Token HIRD bmAttribute
-+		 * when an ACK/NYET/STALL response is sent
-+		 * to an LPM transaction.
-+		 */
-+		unsigned hird:4;
-+		/** RemoteWakeEnable (bRemoteWake) (Device and Host)
-+		 * In Host mode this bit indicates the value of remote
-+		 * wake up to be sent in wIndex field of LPM transaction.
-+		 * In Device mode this field is updated with the
-+		 * Received LPM Token bRemoteWake bmAttribute
-+		 * when an ACK/NYET/STALL response is sent
-+		 * to an LPM transaction.
-+		 */
-+		unsigned rem_wkup_en:1;
-+		/** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
-+		 * The application uses this bit to control
-+		 * the utmi_sleep_n assertion to the PHY when in L1 state.
-+		 */
-+		unsigned en_utmi_sleep:1;
-+		/** HIRD Threshold (HIRD_Thres) (Device and Host)
-+		 */
-+		unsigned hird_thres:5;
-+		/** LPM Response (CoreL1Res) (Device and Host)
-+		 * In Host mode this bit contains handsake response to
-+		 * LPM transaction.
-+		 * In Device mode the response of the core to
-+		 * LPM transaction received is reflected in these two bits.
-+			- 0x0 : ERROR (No handshake response)
-+			- 0x1 : STALL
-+			- 0x2 : NYET
-+			- 0x3 : ACK
-+		 */
-+		unsigned lpm_resp:2;
-+		/** Port Sleep Status (SlpSts) (Device and Host)
-+		 * This bit is set as long as a Sleep condition
-+		 * is present on the USB bus.
-+		 */
-+		unsigned prt_sleep_sts:1;
-+		/** Sleep State Resume OK (L1ResumeOK) (Device and Host)
-+		 * Indicates that the application or host
-+		 * can start resume from Sleep state.
-+		 */
-+		unsigned sleep_state_resumeok:1;
-+		/** LPM channel Index (LPM_Chnl_Indx) (Host)
-+		 * The channel number on which the LPM transaction
-+		 * has to be applied while sending
-+		 * an LPM transaction to the local device.
-+		 */
-+		unsigned lpm_chan_index:4;
-+		/** LPM Retry Count (LPM_Retry_Cnt) (Host)
-+		 * Number host retries that would be performed
-+		 * if the device response was not valid response.
-+		 */
-+		unsigned retry_count:3;
-+		/** Send LPM Transaction (SndLPM) (Host)
-+		 * When set by application software,
-+		 * an LPM transaction containing two tokens
-+		 * is sent.
-+		 */
-+		unsigned send_lpm:1;
-+		/** LPM Retry status (LPM_RetryCnt_Sts) (Host)
-+		 * Number of LPM Host Retries still remaining
-+		 * to be transmitted for the current LPM sequence
-+		 */
-+		unsigned retry_count_sts:3;
-+		unsigned reserved28_29:2;
-+		/** In host mode once this bit is set, the host
-+		 * configures to drive the HSIC Idle state on the bus.
-+		 * It then waits for the  device to initiate the Connect sequence.
-+		 * In device mode once this bit is set, the device waits for
-+		 * the HSIC Idle line state on the bus. Upon receving the Idle
-+		 * line state, it initiates the HSIC Connect sequence.
-+		 */
-+		unsigned hsic_connect:1;
-+		/** This bit overrides and functionally inverts
-+		 * the if_select_hsic input port signal.
-+		 */
-+		unsigned inv_sel_hsic:1;
-+	} b;
-+} glpmcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields of the Core ADP Timer, Control and
-+ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
-+ * the <i>d32</i> value to the register.
-+ */
-+typedef union adpctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Probe Discharge (PRB_DSCHG)
-+		 *  These bits set the times for TADP_DSCHG.
-+		 *  These bits are defined as follows:
-+		 *  2'b00 - 4 msec
-+		 *  2'b01 - 8 msec
-+		 *  2'b10 - 16 msec
-+		 *  2'b11 - 32 msec
-+		 */
-+		unsigned prb_dschg:2;
-+		/** Probe Delta (PRB_DELTA)
-+		 *  These bits set the resolution for RTIM   value.
-+		 *  The bits are defined in units of 32 kHz clock cycles as follows:
-+		 *  2'b00  -  1 cycles
-+		 *  2'b01  -  2 cycles
-+		 *  2'b10 -  3 cycles
-+		 *  2'b11 - 4 cycles
-+		 *  For example if this value is chosen to 2'b01, it means that RTIM
-+		 *  increments for every 3(three) 32Khz clock cycles.
-+		 */
-+		unsigned prb_delta:2;
-+		/** Probe Period (PRB_PER)
-+		 *  These bits sets the TADP_PRD as shown in Figure 4 as follows:
-+		 *  2'b00  -  0.625 to 0.925 sec (typical 0.775 sec)
-+		 *  2'b01  -  1.25 to 1.85 sec (typical 1.55 sec)
-+		 *  2'b10  -  1.9 to 2.6 sec (typical 2.275 sec)
-+		 *  2'b11  -  Reserved
-+		 */
-+		unsigned prb_per:2;
-+		/** These bits capture the latest time it took for VBUS to ramp from
-+		 *  VADP_SINK to VADP_PRB.
-+		 *  0x000  -  1 cycles
-+		 *  0x001  -  2 cycles
-+		 *  0x002  -  3 cycles
-+		 *  etc
-+		 *  0x7FF  -  2048 cycles
-+		 *  A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
-+		*/
-+		unsigned rtim:11;
-+		/** Enable Probe (EnaPrb)
-+		 *  When programmed to 1'b1, the core performs a probe operation.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned enaprb:1;
-+		/** Enable Sense (EnaSns)
-+		 *  When programmed to 1'b1, the core performs a Sense operation.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned enasns:1;
-+		/** ADP Reset (ADPRes)
-+		 *  When set, ADP controller is reset.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned adpres:1;
-+		/** ADP Enable (ADPEn)
-+		 *  When set, the core performs either ADP probing or sensing
-+		 *  based on EnaPrb or EnaSns.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned adpen:1;
-+		/** ADP Probe Interrupt (ADP_PRB_INT)
-+		 *  When this bit is set, it means that the VBUS
-+		 *  voltage is greater than VADP_PRB or VADP_PRB is reached.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned adp_prb_int:1;
-+		/**
-+		 *  ADP Sense Interrupt (ADP_SNS_INT)
-+		 *  When this bit is set, it means that the VBUS voltage is greater than
-+		 *  VADP_SNS value or VADP_SNS is reached.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned adp_sns_int:1;
-+		/** ADP Tomeout Interrupt (ADP_TMOUT_INT)
-+		 *  This bit is relevant only for an ADP probe.
-+		 *  When this bit is set, it means that the ramp time has
-+		 *  completed ie ADPCTL.RTIM has reached its terminal value
-+		 *  of 0x7FF.  This is a debug feature that allows software
-+		 *  to read the ramp time after each cycle.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned adp_tmout_int:1;
-+		/** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
-+		 *  When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned adp_prb_int_msk:1;
-+		/** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
-+		 *  When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned adp_sns_int_msk:1;
-+		/** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
-+		 *  When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
-+		 *  This bit is valid only if OTG_Ver = 1'b1.
-+		 */
-+		unsigned adp_tmout_int_msk:1;
-+		/** Access Request
-+		 * 2'b00 - Read/Write Valid (updated by the core)
-+		 * 2'b01 - Read
-+		 * 2'b00 - Write
-+		 * 2'b00 - Reserved
-+		 */
-+		unsigned ar:2;
-+		 /** Reserved */
-+		unsigned reserved29_31:3;
-+	} b;
-+} adpctl_data_t;
-+
-+////////////////////////////////////////////
-+// Device Registers
-+/**
-+ * Device Global Registers. <i>Offsets 800h-BFFh</i>
-+ *
-+ * The following structures define the size and relative field offsets
-+ * for the Device Mode Registers.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_global_regs {
-+	/** Device Configuration Register. <i>Offset 800h</i> */
-+	volatile uint32_t dcfg;
-+	/** Device Control Register. <i>Offset: 804h</i> */
-+	volatile uint32_t dctl;
-+	/** Device Status Register (Read Only). <i>Offset: 808h</i> */
-+	volatile uint32_t dsts;
-+	/** Reserved. <i>Offset: 80Ch</i> */
-+	uint32_t unused;
-+	/** Device IN Endpoint Common Interrupt Mask
-+	 * Register. <i>Offset: 810h</i> */
-+	volatile uint32_t diepmsk;
-+	/** Device OUT Endpoint Common Interrupt Mask
-+	 * Register. <i>Offset: 814h</i> */
-+	volatile uint32_t doepmsk;
-+	/** Device All Endpoints Interrupt Register.  <i>Offset: 818h</i> */
-+	volatile uint32_t daint;
-+	/** Device All Endpoints Interrupt Mask Register.  <i>Offset:
-+	 * 81Ch</i> */
-+	volatile uint32_t daintmsk;
-+	/** Device IN Token Queue Read Register-1 (Read Only).
-+	 * <i>Offset: 820h</i> */
-+	volatile uint32_t dtknqr1;
-+	/** Device IN Token Queue Read Register-2 (Read Only).
-+	 * <i>Offset: 824h</i> */
-+	volatile uint32_t dtknqr2;
-+	/** Device VBUS	 discharge Register.  <i>Offset: 828h</i> */
-+	volatile uint32_t dvbusdis;
-+	/** Device VBUS Pulse Register.	 <i>Offset: 82Ch</i> */
-+	volatile uint32_t dvbuspulse;
-+	/** Device IN Token Queue Read Register-3 (Read Only). /
-+	 *	Device Thresholding control register (Read/Write)
-+	 * <i>Offset: 830h</i> */
-+	volatile uint32_t dtknqr3_dthrctl;
-+	/** Device IN Token Queue Read Register-4 (Read Only). /
-+	 *	Device IN EPs empty Inr. Mask Register (Read/Write)
-+	 * <i>Offset: 834h</i> */
-+	volatile uint32_t dtknqr4_fifoemptymsk;
-+	/** Device Each Endpoint Interrupt Register (Read Only). /
-+	 * <i>Offset: 838h</i> */
-+	volatile uint32_t deachint;
-+	/** Device Each Endpoint Interrupt mask Register (Read/Write). /
-+	 * <i>Offset: 83Ch</i> */
-+	volatile uint32_t deachintmsk;
-+	/** Device Each In Endpoint Interrupt mask Register (Read/Write). /
-+	 * <i>Offset: 840h</i> */
-+	volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
-+	/** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
-+	 * <i>Offset: 880h</i> */
-+	volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
-+} dwc_otg_device_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Configuration
-+ * Register.  Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.  Write the
-+ * <i>d32</i> member to the dcfg register.
-+ */
-+typedef union dcfg_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Device Speed */
-+		unsigned devspd:2;
-+		/** Non Zero Length Status OUT Handshake */
-+		unsigned nzstsouthshk:1;
-+#define DWC_DCFG_SEND_STALL 1
-+
-+		unsigned ena32khzs:1;
-+		/** Device Addresses */
-+		unsigned devaddr:7;
-+		/** Periodic Frame Interval */
-+		unsigned perfrint:2;
-+#define DWC_DCFG_FRAME_INTERVAL_80 0
-+#define DWC_DCFG_FRAME_INTERVAL_85 1
-+#define DWC_DCFG_FRAME_INTERVAL_90 2
-+#define DWC_DCFG_FRAME_INTERVAL_95 3
-+
-+		/** Enable Device OUT NAK for bulk in DDMA mode */
-+		unsigned endevoutnak:1;
-+
-+		unsigned reserved14_17:4;
-+		/** In Endpoint Mis-match count */
-+		unsigned epmscnt:5;
-+		/** Enable Descriptor DMA in Device mode */
-+		unsigned descdma:1;
-+		unsigned perschintvl:2;
-+		unsigned resvalid:6;
-+	} b;
-+} dcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Control
-+ * Register.  Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union dctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Remote Wakeup */
-+		unsigned rmtwkupsig:1;
-+		/** Soft Disconnect */
-+		unsigned sftdiscon:1;
-+		/** Global Non-Periodic IN NAK Status */
-+		unsigned gnpinnaksts:1;
-+		/** Global OUT NAK Status */
-+		unsigned goutnaksts:1;
-+		/** Test Control */
-+		unsigned tstctl:3;
-+		/** Set Global Non-Periodic IN NAK */
-+		unsigned sgnpinnak:1;
-+		/** Clear Global Non-Periodic IN NAK */
-+		unsigned cgnpinnak:1;
-+		/** Set Global OUT NAK */
-+		unsigned sgoutnak:1;
-+		/** Clear Global OUT NAK */
-+		unsigned cgoutnak:1;
-+		/** Power-On Programming Done */
-+		unsigned pwronprgdone:1;
-+		/** Reserved */
-+		unsigned reserved:1;
-+		/** Global Multi Count */
-+		unsigned gmc:2;
-+		/** Ignore Frame Number for ISOC EPs */
-+		unsigned ifrmnum:1;
-+		/** NAK on Babble */
-+		unsigned nakonbble:1;
-+		/** Enable Continue on BNA */
-+		unsigned encontonbna:1;
-+
-+		unsigned reserved18_31:14;
-+	} b;
-+} dctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device Status
-+ * Register.  Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union dsts_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Suspend Status */
-+		unsigned suspsts:1;
-+		/** Enumerated Speed */
-+		unsigned enumspd:2;
-+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
-+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
-+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ		   2
-+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ		   3
-+		/** Erratic Error */
-+		unsigned errticerr:1;
-+		unsigned reserved4_7:4;
-+		/** Frame or Microframe Number of the received SOF */
-+		unsigned soffn:14;
-+		unsigned reserved22_31:10;
-+	} b;
-+} dsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN EP Interrupt
-+ * Register and the Device IN EP Common Mask Register.
-+ *
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ *	 bits using the <i>b</i>it elements.
-+ */
-+typedef union diepint_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Transfer complete mask */
-+		unsigned xfercompl:1;
-+		/** Endpoint disable mask */
-+		unsigned epdisabled:1;
-+		/** AHB Error mask */
-+		unsigned ahberr:1;
-+		/** TimeOUT Handshake mask (non-ISOC EPs) */
-+		unsigned timeout:1;
-+		/** IN Token received with TxF Empty mask */
-+		unsigned intktxfemp:1;
-+		/** IN Token Received with EP mismatch mask */
-+		unsigned intknepmis:1;
-+		/** IN Endpoint NAK Effective mask */
-+		unsigned inepnakeff:1;
-+		/** Reserved */
-+		unsigned emptyintr:1;
-+
-+		unsigned txfifoundrn:1;
-+
-+		/** BNA Interrupt mask */
-+		unsigned bna:1;
-+
-+		unsigned reserved10_12:3;
-+		/** BNA Interrupt mask */
-+		unsigned nak:1;
-+
-+		unsigned reserved14_31:18;
-+	} b;
-+} diepint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN EP
-+ * Common/Dedicated Interrupt Mask Register.
-+ */
-+typedef union diepint_data diepmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device OUT EP Interrupt
-+ * Registerand Device OUT EP Common Interrupt Mask Register.
-+ *
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ *	 bits using the <i>b</i>it elements.
-+ */
-+typedef union doepint_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Transfer complete */
-+		unsigned xfercompl:1;
-+		/** Endpoint disable  */
-+		unsigned epdisabled:1;
-+		/** AHB Error */
-+		unsigned ahberr:1;
-+		/** Setup Phase Done (contorl EPs) */
-+		unsigned setup:1;
-+		/** OUT Token Received when Endpoint Disabled */
-+		unsigned outtknepdis:1;
-+
-+		unsigned stsphsercvd:1;
-+		/** Back-to-Back SETUP Packets Received */
-+		unsigned back2backsetup:1;
-+
-+		unsigned reserved7:1;
-+		/** OUT packet Error */
-+		unsigned outpkterr:1;
-+		/** BNA Interrupt */
-+		unsigned bna:1;
-+
-+		unsigned reserved10:1;
-+		/** Packet Drop Status */
-+		unsigned pktdrpsts:1;
-+		/** Babble Interrupt */
-+		unsigned babble:1;
-+		/** NAK Interrupt */
-+		unsigned nak:1;
-+		/** NYET Interrupt */
-+		unsigned nyet:1;
-+		/** Bit indicating setup packet received */
-+		unsigned sr:1;
-+
-+		unsigned reserved16_31:16;
-+	} b;
-+} doepint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device OUT EP
-+ * Common/Dedicated Interrupt Mask Register.
-+ */
-+typedef union doepint_data doepmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device All EP Interrupt
-+ * and Mask Registers.
-+ * - Read the register into the <i>d32</i> member then set/clear the
-+ *	 bits using the <i>b</i>it elements.
-+ */
-+typedef union daint_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** IN Endpoint bits */
-+		unsigned in:16;
-+		/** OUT Endpoint bits */
-+		unsigned out:16;
-+	} ep;
-+	struct {
-+		/** IN Endpoint bits */
-+		unsigned inep0:1;
-+		unsigned inep1:1;
-+		unsigned inep2:1;
-+		unsigned inep3:1;
-+		unsigned inep4:1;
-+		unsigned inep5:1;
-+		unsigned inep6:1;
-+		unsigned inep7:1;
-+		unsigned inep8:1;
-+		unsigned inep9:1;
-+		unsigned inep10:1;
-+		unsigned inep11:1;
-+		unsigned inep12:1;
-+		unsigned inep13:1;
-+		unsigned inep14:1;
-+		unsigned inep15:1;
-+		/** OUT Endpoint bits */
-+		unsigned outep0:1;
-+		unsigned outep1:1;
-+		unsigned outep2:1;
-+		unsigned outep3:1;
-+		unsigned outep4:1;
-+		unsigned outep5:1;
-+		unsigned outep6:1;
-+		unsigned outep7:1;
-+		unsigned outep8:1;
-+		unsigned outep9:1;
-+		unsigned outep10:1;
-+		unsigned outep11:1;
-+		unsigned outep12:1;
-+		unsigned outep13:1;
-+		unsigned outep14:1;
-+		unsigned outep15:1;
-+	} b;
-+} daint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device IN Token Queue
-+ * Read Registers.
-+ * - Read the register into the <i>d32</i> member.
-+ * - READ-ONLY Register
-+ */
-+typedef union dtknq1_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** In Token Queue Write Pointer */
-+		unsigned intknwptr:5;
-+		/** Reserved */
-+		unsigned reserved05_06:2;
-+		/** write pointer has wrapped. */
-+		unsigned wrap_bit:1;
-+		/** EP Numbers of IN Tokens 0 ... 4 */
-+		unsigned epnums0_5:24;
-+	} b;
-+} dtknq1_data_t;
-+
-+/**
-+ * This union represents Threshold control Register
-+ * - Read and write the register into the <i>d32</i> member.
-+ * - READ-WRITABLE Register
-+ */
-+typedef union dthrctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** non ISO Tx Thr. Enable */
-+		unsigned non_iso_thr_en:1;
-+		/** ISO Tx Thr. Enable */
-+		unsigned iso_thr_en:1;
-+		/** Tx Thr. Length */
-+		unsigned tx_thr_len:9;
-+		/** AHB Threshold ratio */
-+		unsigned ahb_thr_ratio:2;
-+		/** Reserved */
-+		unsigned reserved13_15:3;
-+		/** Rx Thr. Enable */
-+		unsigned rx_thr_en:1;
-+		/** Rx Thr. Length */
-+		unsigned rx_thr_len:9;
-+		unsigned reserved26:1;
-+		/** Arbiter Parking Enable*/
-+		unsigned arbprken:1;
-+		/** Reserved */
-+		unsigned reserved28_31:4;
-+	} b;
-+} dthrctl_data_t;
-+
-+/**
-+ * Device Logical IN Endpoint-Specific Registers. <i>Offsets
-+ * 900h-AFCh</i>
-+ *
-+ * There will be one set of endpoint registers per logical endpoint
-+ * implemented.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_in_ep_regs {
-+	/** Device IN Endpoint Control Register. <i>Offset:900h +
-+	 * (ep_num * 20h) + 00h</i> */
-+	volatile uint32_t diepctl;
-+	/** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
-+	uint32_t reserved04;
-+	/** Device IN Endpoint Interrupt Register. <i>Offset:900h +
-+	 * (ep_num * 20h) + 08h</i> */
-+	volatile uint32_t diepint;
-+	/** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
-+	uint32_t reserved0C;
-+	/** Device IN Endpoint Transfer Size
-+	 * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
-+	volatile uint32_t dieptsiz;
-+	/** Device IN Endpoint DMA Address Register. <i>Offset:900h +
-+	 * (ep_num * 20h) + 14h</i> */
-+	volatile uint32_t diepdma;
-+	/** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
-+	 * (ep_num * 20h) + 18h</i> */
-+	volatile uint32_t dtxfsts;
-+	/** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
-+	 * (ep_num * 20h) + 1Ch</i> */
-+	volatile uint32_t diepdmab;
-+} dwc_otg_dev_in_ep_regs_t;
-+
-+/**
-+ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
-+ * B00h-CFCh</i>
-+ *
-+ * There will be one set of endpoint registers per logical endpoint
-+ * implemented.
-+ *
-+ * <i>These registers are visible only in Device mode and must not be
-+ * accessed in Host mode, as the results are unknown.</i>
-+ */
-+typedef struct dwc_otg_dev_out_ep_regs {
-+	/** Device OUT Endpoint Control Register. <i>Offset:B00h +
-+	 * (ep_num * 20h) + 00h</i> */
-+	volatile uint32_t doepctl;
-+	/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
-+	uint32_t reserved04;
-+	/** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
-+	 * (ep_num * 20h) + 08h</i> */
-+	volatile uint32_t doepint;
-+	/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
-+	uint32_t reserved0C;
-+	/** Device OUT Endpoint Transfer Size Register. <i>Offset:
-+	 * B00h + (ep_num * 20h) + 10h</i> */
-+	volatile uint32_t doeptsiz;
-+	/** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
-+	 * + (ep_num * 20h) + 14h</i> */
-+	volatile uint32_t doepdma;
-+	/** Reserved. <i>Offset:B00h + 	 * (ep_num * 20h) + 18h</i> */
-+	uint32_t unused;
-+	/** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
-+	 * + (ep_num * 20h) + 1Ch</i> */
-+	uint32_t doepdmab;
-+} dwc_otg_dev_out_ep_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP Control
-+ * Register.  Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union depctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Maximum Packet Size
-+		 * IN/OUT EPn
-+		 * IN/OUT EP0 - 2 bits
-+		 *	 2'b00: 64 Bytes
-+		 *	 2'b01: 32
-+		 *	 2'b10: 16
-+		 *	 2'b11: 8 */
-+		unsigned mps:11;
-+#define DWC_DEP0CTL_MPS_64	 0
-+#define DWC_DEP0CTL_MPS_32	 1
-+#define DWC_DEP0CTL_MPS_16	 2
-+#define DWC_DEP0CTL_MPS_8	 3
-+
-+		/** Next Endpoint
-+		 * IN EPn/IN EP0
-+		 * OUT EPn/OUT EP0 - reserved */
-+		unsigned nextep:4;
-+
-+		/** USB Active Endpoint */
-+		unsigned usbactep:1;
-+
-+		/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
-+		 * This field contains the PID of the packet going to
-+		 * be received or transmitted on this endpoint. The
-+		 * application should program the PID of the first
-+		 * packet going to be received or transmitted on this
-+		 * endpoint , after the endpoint is
-+		 * activated. Application use the SetD1PID and
-+		 * SetD0PID fields of this register to program either
-+		 * D0 or D1 PID.
-+		 *
-+		 * The encoding for this field is
-+		 *	 - 0: D0
-+		 *	 - 1: D1
-+		 */
-+		unsigned dpid:1;
-+
-+		/** NAK Status */
-+		unsigned naksts:1;
-+
-+		/** Endpoint Type
-+		 *	2'b00: Control
-+		 *	2'b01: Isochronous
-+		 *	2'b10: Bulk
-+		 *	2'b11: Interrupt */
-+		unsigned eptype:2;
-+
-+		/** Snoop Mode
-+		 * OUT EPn/OUT EP0
-+		 * IN EPn/IN EP0 - reserved */
-+		unsigned snp:1;
-+
-+		/** Stall Handshake */
-+		unsigned stall:1;
-+
-+		/** Tx Fifo Number
-+		 * IN EPn/IN EP0
-+		 * OUT EPn/OUT EP0 - reserved */
-+		unsigned txfnum:4;
-+
-+		/** Clear NAK */
-+		unsigned cnak:1;
-+		/** Set NAK */
-+		unsigned snak:1;
-+		/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
-+		 * Writing to this field sets the Endpoint DPID (DPID)
-+		 * field in this register to DATA0. Set Even
-+		 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
-+		 * Writing to this field sets the Even/Odd
-+		 * (micro)frame (EO_FrNum) field to even (micro)
-+		 * frame.
-+		 */
-+		unsigned setd0pid:1;
-+		/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
-+		 * Writing to this field sets the Endpoint DPID (DPID)
-+		 * field in this register to DATA1 Set Odd
-+		 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
-+		 * Writing to this field sets the Even/Odd
-+		 * (micro)frame (EO_FrNum) field to odd (micro) frame.
-+		 */
-+		unsigned setd1pid:1;
-+
-+		/** Endpoint Disable */
-+		unsigned epdis:1;
-+		/** Endpoint Enable */
-+		unsigned epena:1;
-+	} b;
-+} depctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP Transfer
-+ * Size Register.  Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union deptsiz_data {
-+		/** raw register data */
-+	uint32_t d32;
-+		/** register bits */
-+	struct {
-+		/** Transfer size */
-+		unsigned xfersize:19;
-+/** Max packet count for EP (pow(2,10)-1) */
-+#define MAX_PKT_CNT 1023
-+		/** Packet Count */
-+		unsigned pktcnt:10;
-+		/** Multi Count - Periodic IN endpoints */
-+		unsigned mc:2;
-+		unsigned reserved:1;
-+	} b;
-+} deptsiz_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Device EP 0 Transfer
-+ * Size Register.  Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union deptsiz0_data {
-+		/** raw register data */
-+	uint32_t d32;
-+		/** register bits */
-+	struct {
-+		/** Transfer size */
-+		unsigned xfersize:7;
-+				/** Reserved */
-+		unsigned reserved7_18:12;
-+		/** Packet Count */
-+		unsigned pktcnt:2;
-+				/** Reserved */
-+		unsigned reserved21_28:8;
-+				/**Setup Packet Count (DOEPTSIZ0 Only) */
-+		unsigned supcnt:2;
-+		unsigned reserved31;
-+	} b;
-+} deptsiz0_data_t;
-+
-+/////////////////////////////////////////////////
-+// DMA Descriptor Specific Structures
-+//
-+
-+/** Buffer status definitions */
-+
-+#define BS_HOST_READY	0x0
-+#define BS_DMA_BUSY		0x1
-+#define BS_DMA_DONE		0x2
-+#define BS_HOST_BUSY	0x3
-+
-+/** Receive/Transmit status definitions */
-+
-+#define RTS_SUCCESS		0x0
-+#define RTS_BUFFLUSH	0x1
-+#define RTS_RESERVED	0x2
-+#define RTS_BUFERR		0x3
-+
-+/**
-+ * This union represents the bit fields in the DMA Descriptor
-+ * status quadlet. Read the quadlet into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
-+ * <i>b_iso_in</i> elements.
-+ */
-+typedef union dev_dma_desc_sts {
-+		/** raw register data */
-+	uint32_t d32;
-+		/** quadlet bits */
-+	struct {
-+		/** Received number of bytes */
-+		unsigned bytes:16;
-+		/** NAK bit - only for OUT EPs */
-+		unsigned nak:1;
-+		unsigned reserved17_22:6;
-+		/** Multiple Transfer - only for OUT EPs */
-+		unsigned mtrf:1;
-+		/** Setup Packet received - only for OUT EPs */
-+		unsigned sr:1;
-+		/** Interrupt On Complete */
-+		unsigned ioc:1;
-+		/** Short Packet */
-+		unsigned sp:1;
-+		/** Last */
-+		unsigned l:1;
-+		/** Receive Status */
-+		unsigned sts:2;
-+		/** Buffer Status */
-+		unsigned bs:2;
-+	} b;
-+
-+//#ifdef DWC_EN_ISOC
-+		/** iso out quadlet bits */
-+	struct {
-+		/** Received number of bytes */
-+		unsigned rxbytes:11;
-+
-+		unsigned reserved11:1;
-+		/** Frame Number */
-+		unsigned framenum:11;
-+		/** Received ISO Data PID */
-+		unsigned pid:2;
-+		/** Interrupt On Complete */
-+		unsigned ioc:1;
-+		/** Short Packet */
-+		unsigned sp:1;
-+		/** Last */
-+		unsigned l:1;
-+		/** Receive Status */
-+		unsigned rxsts:2;
-+		/** Buffer Status */
-+		unsigned bs:2;
-+	} b_iso_out;
-+
-+		/** iso in quadlet bits */
-+	struct {
-+		/** Transmited number of bytes */
-+		unsigned txbytes:12;
-+		/** Frame Number */
-+		unsigned framenum:11;
-+		/** Transmited ISO Data PID */
-+		unsigned pid:2;
-+		/** Interrupt On Complete */
-+		unsigned ioc:1;
-+		/** Short Packet */
-+		unsigned sp:1;
-+		/** Last */
-+		unsigned l:1;
-+		/** Transmit Status */
-+		unsigned txsts:2;
-+		/** Buffer Status */
-+		unsigned bs:2;
-+	} b_iso_in;
-+//#endif                                /* DWC_EN_ISOC */
-+} dev_dma_desc_sts_t;
-+
-+/**
-+ * DMA Descriptor structure
-+ *
-+ * DMA Descriptor structure contains two quadlets:
-+ * Status quadlet and Data buffer pointer.
-+ */
-+typedef struct dwc_otg_dev_dma_desc {
-+	/** DMA Descriptor status quadlet */
-+	dev_dma_desc_sts_t status;
-+	/** DMA Descriptor data buffer pointer */
-+	uint32_t buf;
-+} dwc_otg_dev_dma_desc_t;
-+
-+/**
-+ * The dwc_otg_dev_if structure contains information needed to manage
-+ * the DWC_otg controller acting in device mode. It represents the
-+ * programming view of the device-specific aspects of the controller.
-+ */
-+typedef struct dwc_otg_dev_if {
-+	/** Pointer to device Global registers.
-+	 * Device Global Registers starting at offset 800h
-+	 */
-+	dwc_otg_device_global_regs_t *dev_global_regs;
-+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
-+
-+	/**
-+	 * Device Logical IN Endpoint-Specific Registers 900h-AFCh
-+	 */
-+	dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
-+#define DWC_DEV_IN_EP_REG_OFFSET 0x900
-+#define DWC_EP_REG_OFFSET 0x20
-+
-+	/** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
-+	dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
-+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
-+
-+	/* Device configuration information */
-+	uint8_t speed;				 /**< Device Speed	0: Unknown, 1: LS, 2:FS, 3: HS */
-+	uint8_t num_in_eps;		 /**< Number # of Tx EP range: 0-15 exept ep0 */
-+	uint8_t num_out_eps;		 /**< Number # of Rx EP range: 0-15 exept ep 0*/
-+
-+	/** Size of periodic FIFOs (Bytes) */
-+	uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
-+
-+	/** Size of Tx FIFOs (Bytes) */
-+	uint16_t tx_fifo_size[MAX_TX_FIFOS];
-+
-+	/** Thresholding enable flags and length varaiables **/
-+	uint16_t rx_thr_en;
-+	uint16_t iso_tx_thr_en;
-+	uint16_t non_iso_tx_thr_en;
-+
-+	uint16_t rx_thr_length;
-+	uint16_t tx_thr_length;
-+
-+	/**
-+	 * Pointers to the DMA Descriptors for EP0 Control
-+	 * transfers (virtual and physical)
-+	 */
-+
-+	/** 2 descriptors for SETUP packets */
-+	dwc_dma_t dma_setup_desc_addr[2];
-+	dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
-+
-+	/** Pointer to Descriptor with latest SETUP packet */
-+	dwc_otg_dev_dma_desc_t *psetup;
-+
-+	/** Index of current SETUP handler descriptor */
-+	uint32_t setup_desc_index;
-+
-+	/** Descriptor for Data In or Status In phases */
-+	dwc_dma_t dma_in_desc_addr;
-+	dwc_otg_dev_dma_desc_t *in_desc_addr;
-+
-+	/** Descriptor for Data Out or Status Out phases */
-+	dwc_dma_t dma_out_desc_addr;
-+	dwc_otg_dev_dma_desc_t *out_desc_addr;
-+
-+	/** Setup Packet Detected - if set clear NAK when queueing */
-+	uint32_t spd;
-+	/** Isoc ep pointer on which incomplete happens */
-+	void *isoc_ep;
-+
-+} dwc_otg_dev_if_t;
-+
-+/////////////////////////////////////////////////
-+// Host Mode Register Structures
-+//
-+/**
-+ * The Host Global Registers structure defines the size and relative
-+ * field offsets for the Host Mode Global Registers.  Host Global
-+ * Registers offsets 400h-7FFh.
-+*/
-+typedef struct dwc_otg_host_global_regs {
-+	/** Host Configuration Register.   <i>Offset: 400h</i> */
-+	volatile uint32_t hcfg;
-+	/** Host Frame Interval Register.	<i>Offset: 404h</i> */
-+	volatile uint32_t hfir;
-+	/** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
-+	volatile uint32_t hfnum;
-+	/** Reserved.	<i>Offset: 40Ch</i> */
-+	uint32_t reserved40C;
-+	/** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
-+	volatile uint32_t hptxsts;
-+	/** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
-+	volatile uint32_t haint;
-+	/** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
-+	volatile uint32_t haintmsk;
-+	/** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
-+	volatile uint32_t hflbaddr;
-+} dwc_otg_host_global_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Configuration Register.
-+ * Read the register into the <i>d32</i> member then set/clear the bits using
-+ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
-+ */
-+typedef union hcfg_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		/** FS/LS Phy Clock Select */
-+		unsigned fslspclksel:2;
-+#define DWC_HCFG_30_60_MHZ 0
-+#define DWC_HCFG_48_MHZ	   1
-+#define DWC_HCFG_6_MHZ	   2
-+
-+		/** FS/LS Only Support */
-+		unsigned fslssupp:1;
-+		unsigned reserved3_6:4;
-+		/** Enable 32-KHz Suspend Mode */
-+		unsigned ena32khzs:1;
-+		/** Resume Validation Periiod */
-+		unsigned resvalid:8;
-+		unsigned reserved16_22:7;
-+		/** Enable Scatter/gather DMA in Host mode */
-+		unsigned descdma:1;
-+		/** Frame List Entries */
-+		unsigned frlisten:2;
-+		/** Enable Periodic Scheduling */
-+		unsigned perschedena:1;
-+		unsigned reserved27_30:4;
-+		unsigned modechtimen:1;
-+	} b;
-+} hcfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Frame Remaing/Number
-+ * Register.
-+ */
-+typedef union hfir_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		unsigned frint:16;
-+		unsigned hfirrldctrl:1;
-+		unsigned reserved:15;
-+	} b;
-+} hfir_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Frame Remaing/Number
-+ * Register.
-+ */
-+typedef union hfnum_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		unsigned frnum:16;
-+#define DWC_HFNUM_MAX_FRNUM 0x3FFF
-+		unsigned frrem:16;
-+	} b;
-+} hfnum_data_t;
-+
-+typedef union hptxsts_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		unsigned ptxfspcavail:16;
-+		unsigned ptxqspcavail:8;
-+		/** Top of the Periodic Transmit Request Queue
-+		 *	- bit 24 - Terminate (last entry for the selected channel)
-+		 *	- bits 26:25 - Token Type
-+		 *	  - 2'b00 - Zero length
-+		 *	  - 2'b01 - Ping
-+		 *	  - 2'b10 - Disable
-+		 *	- bits 30:27 - Channel Number
-+		 *	- bit 31 - Odd/even microframe
-+		 */
-+		unsigned ptxqtop_terminate:1;
-+		unsigned ptxqtop_token:2;
-+		unsigned ptxqtop_chnum:4;
-+		unsigned ptxqtop_odd:1;
-+	} b;
-+} hptxsts_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Port Control and Status
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hprt0 register.
-+ */
-+typedef union hprt0_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned prtconnsts:1;
-+		unsigned prtconndet:1;
-+		unsigned prtena:1;
-+		unsigned prtenchng:1;
-+		unsigned prtovrcurract:1;
-+		unsigned prtovrcurrchng:1;
-+		unsigned prtres:1;
-+		unsigned prtsusp:1;
-+		unsigned prtrst:1;
-+		unsigned reserved9:1;
-+		unsigned prtlnsts:2;
-+		unsigned prtpwr:1;
-+		unsigned prttstctl:4;
-+		unsigned prtspd:2;
-+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
-+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
-+#define DWC_HPRT0_PRTSPD_LOW_SPEED	2
-+		unsigned reserved19_31:13;
-+	} b;
-+} hprt0_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union haint_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned ch0:1;
-+		unsigned ch1:1;
-+		unsigned ch2:1;
-+		unsigned ch3:1;
-+		unsigned ch4:1;
-+		unsigned ch5:1;
-+		unsigned ch6:1;
-+		unsigned ch7:1;
-+		unsigned ch8:1;
-+		unsigned ch9:1;
-+		unsigned ch10:1;
-+		unsigned ch11:1;
-+		unsigned ch12:1;
-+		unsigned ch13:1;
-+		unsigned ch14:1;
-+		unsigned ch15:1;
-+		unsigned reserved:16;
-+	} b;
-+
-+	struct {
-+		unsigned chint:16;
-+		unsigned reserved:16;
-+	} b2;
-+} haint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union haintmsk_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned ch0:1;
-+		unsigned ch1:1;
-+		unsigned ch2:1;
-+		unsigned ch3:1;
-+		unsigned ch4:1;
-+		unsigned ch5:1;
-+		unsigned ch6:1;
-+		unsigned ch7:1;
-+		unsigned ch8:1;
-+		unsigned ch9:1;
-+		unsigned ch10:1;
-+		unsigned ch11:1;
-+		unsigned ch12:1;
-+		unsigned ch13:1;
-+		unsigned ch14:1;
-+		unsigned ch15:1;
-+		unsigned reserved:16;
-+	} b;
-+
-+	struct {
-+		unsigned chint:16;
-+		unsigned reserved:16;
-+	} b2;
-+} haintmsk_data_t;
-+
-+/**
-+ * Host Channel Specific Registers. <i>500h-5FCh</i>
-+ */
-+typedef struct dwc_otg_hc_regs {
-+	/** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
-+	volatile uint32_t hcchar;
-+	/** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
-+	volatile uint32_t hcsplt;
-+	/** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
-+	volatile uint32_t hcint;
-+	/** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
-+	volatile uint32_t hcintmsk;
-+	/** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
-+	volatile uint32_t hctsiz;
-+	/** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
-+	volatile uint32_t hcdma;
-+	volatile uint32_t reserved;
-+	/** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
-+	volatile uint32_t hcdmab;
-+} dwc_otg_hc_regs_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Characteristics
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcchar register.
-+ */
-+typedef union hcchar_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		/** Maximum packet size in bytes */
-+		unsigned mps:11;
-+
-+		/** Endpoint number */
-+		unsigned epnum:4;
-+
-+		/** 0: OUT, 1: IN */
-+		unsigned epdir:1;
-+
-+		unsigned reserved:1;
-+
-+		/** 0: Full/high speed device, 1: Low speed device */
-+		unsigned lspddev:1;
-+
-+		/** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
-+		unsigned eptype:2;
-+
-+		/** Packets per frame for periodic transfers. 0 is reserved. */
-+		unsigned multicnt:2;
-+
-+		/** Device address */
-+		unsigned devaddr:7;
-+
-+		/**
-+		 * Frame to transmit periodic transaction.
-+		 * 0: even, 1: odd
-+		 */
-+		unsigned oddfrm:1;
-+
-+		/** Channel disable */
-+		unsigned chdis:1;
-+
-+		/** Channel enable */
-+		unsigned chen:1;
-+	} b;
-+} hcchar_data_t;
-+
-+typedef union hcsplt_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		/** Port Address */
-+		unsigned prtaddr:7;
-+
-+		/** Hub Address */
-+		unsigned hubaddr:7;
-+
-+		/** Transaction Position */
-+		unsigned xactpos:2;
-+#define DWC_HCSPLIT_XACTPOS_MID 0
-+#define DWC_HCSPLIT_XACTPOS_END 1
-+#define DWC_HCSPLIT_XACTPOS_BEGIN 2
-+#define DWC_HCSPLIT_XACTPOS_ALL 3
-+
-+		/** Do Complete Split */
-+		unsigned compsplt:1;
-+
-+		/** Reserved */
-+		unsigned reserved:14;
-+
-+		/** Split Enble */
-+		unsigned spltena:1;
-+	} b;
-+} hcsplt_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host All Interrupt
-+ * Register.
-+ */
-+typedef union hcint_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** Transfer Complete */
-+		unsigned xfercomp:1;
-+		/** Channel Halted */
-+		unsigned chhltd:1;
-+		/** AHB Error */
-+		unsigned ahberr:1;
-+		/** STALL Response Received */
-+		unsigned stall:1;
-+		/** NAK Response Received */
-+		unsigned nak:1;
-+		/** ACK Response Received */
-+		unsigned ack:1;
-+		/** NYET Response Received */
-+		unsigned nyet:1;
-+		/** Transaction Err */
-+		unsigned xacterr:1;
-+		/** Babble Error */
-+		unsigned bblerr:1;
-+		/** Frame Overrun */
-+		unsigned frmovrun:1;
-+		/** Data Toggle Error */
-+		unsigned datatglerr:1;
-+		/** Buffer Not Available (only for DDMA mode) */
-+		unsigned bna:1;
-+		/** Exessive transaction error (only for DDMA mode) */
-+		unsigned xcs_xact:1;
-+		/** Frame List Rollover interrupt */
-+		unsigned frm_list_roll:1;
-+		/** Reserved */
-+		unsigned reserved14_31:18;
-+	} b;
-+} hcint_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Interrupt Mask
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcintmsk register.
-+ */
-+typedef union hcintmsk_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		unsigned xfercompl:1;
-+		unsigned chhltd:1;
-+		unsigned ahberr:1;
-+		unsigned stall:1;
-+		unsigned nak:1;
-+		unsigned ack:1;
-+		unsigned nyet:1;
-+		unsigned xacterr:1;
-+		unsigned bblerr:1;
-+		unsigned frmovrun:1;
-+		unsigned datatglerr:1;
-+		unsigned bna:1;
-+		unsigned xcs_xact:1;
-+		unsigned frm_list_roll:1;
-+		unsigned reserved14_31:18;
-+	} b;
-+} hcintmsk_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host Channel Transfer Size
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
-+ * hcchar register.
-+ */
-+
-+typedef union hctsiz_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		/** Total transfer size in bytes */
-+		unsigned xfersize:19;
-+
-+		/** Data packets to transfer */
-+		unsigned pktcnt:10;
-+
-+		/**
-+		 * Packet ID for next data packet
-+		 * 0: DATA0
-+		 * 1: DATA2
-+		 * 2: DATA1
-+		 * 3: MDATA (non-Control), SETUP (Control)
-+		 */
-+		unsigned pid:2;
-+#define DWC_HCTSIZ_DATA0 0
-+#define DWC_HCTSIZ_DATA1 2
-+#define DWC_HCTSIZ_DATA2 1
-+#define DWC_HCTSIZ_MDATA 3
-+#define DWC_HCTSIZ_SETUP 3
-+
-+		/** Do PING protocol when 1 */
-+		unsigned dopng:1;
-+	} b;
-+
-+	/** register bits */
-+	struct {
-+		/** Scheduling information */
-+		unsigned schinfo:8;
-+
-+		/** Number of transfer descriptors.
-+		 * Max value:
-+		 * 64 in general,
-+		 * 256 only for HS isochronous endpoint.
-+		 */
-+		unsigned ntd:8;
-+
-+		/** Data packets to transfer */
-+		unsigned reserved16_28:13;
-+
-+		/**
-+		 * Packet ID for next data packet
-+		 * 0: DATA0
-+		 * 1: DATA2
-+		 * 2: DATA1
-+		 * 3: MDATA (non-Control)
-+		 */
-+		unsigned pid:2;
-+
-+		/** Do PING protocol when 1 */
-+		unsigned dopng:1;
-+	} b_ddma;
-+} hctsiz_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Host DMA Address
-+ * Register used in Descriptor DMA mode.
-+ */
-+typedef union hcdma_data {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		unsigned reserved0_2:3;
-+		/** Current Transfer Descriptor. Not used for ISOC */
-+		unsigned ctd:8;
-+		/** Start Address of Descriptor List */
-+		unsigned dma_addr:21;
-+	} b;
-+} hcdma_data_t;
-+
-+/**
-+ * This union represents the bit fields in the DMA Descriptor
-+ * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union host_dma_desc_sts {
-+	/** raw register data */
-+	uint32_t d32;
-+	/** quadlet bits */
-+
-+	/* for non-isochronous  */
-+	struct {
-+		/** Number of bytes */
-+		unsigned n_bytes:17;
-+		/** QTD offset to jump when Short Packet received - only for IN EPs */
-+		unsigned qtd_offset:6;
-+		/**
-+		 * Set to request the core to jump to alternate QTD if
-+		 * Short Packet received - only for IN EPs
-+		 */
-+		unsigned a_qtd:1;
-+		 /**
-+		  * Setup Packet bit. When set indicates that buffer contains
-+		  * setup packet.
-+		  */
-+		unsigned sup:1;
-+		/** Interrupt On Complete */
-+		unsigned ioc:1;
-+		/** End of List */
-+		unsigned eol:1;
-+		unsigned reserved27:1;
-+		/** Rx/Tx Status */
-+		unsigned sts:2;
-+#define DMA_DESC_STS_PKTERR	1
-+		unsigned reserved30:1;
-+		/** Active Bit */
-+		unsigned a:1;
-+	} b;
-+	/* for isochronous */
-+	struct {
-+		/** Number of bytes */
-+		unsigned n_bytes:12;
-+		unsigned reserved12_24:13;
-+		/** Interrupt On Complete */
-+		unsigned ioc:1;
-+		unsigned reserved26_27:2;
-+		/** Rx/Tx Status */
-+		unsigned sts:2;
-+		unsigned reserved30:1;
-+		/** Active Bit */
-+		unsigned a:1;
-+	} b_isoc;
-+} host_dma_desc_sts_t;
-+
-+#define	MAX_DMA_DESC_SIZE		131071
-+#define MAX_DMA_DESC_NUM_GENERIC	64
-+#define MAX_DMA_DESC_NUM_HS_ISOC	256
-+#define MAX_FRLIST_EN_NUM		64
-+/**
-+ * Host-mode DMA Descriptor structure
-+ *
-+ * DMA Descriptor structure contains two quadlets:
-+ * Status quadlet and Data buffer pointer.
-+ */
-+typedef struct dwc_otg_host_dma_desc {
-+	/** DMA Descriptor status quadlet */
-+	host_dma_desc_sts_t status;
-+	/** DMA Descriptor data buffer pointer */
-+	uint32_t buf;
-+} dwc_otg_host_dma_desc_t;
-+
-+/** OTG Host Interface Structure.
-+ *
-+ * The OTG Host Interface Structure structure contains information
-+ * needed to manage the DWC_otg controller acting in host mode. It
-+ * represents the programming view of the host-specific aspects of the
-+ * controller.
-+ */
-+typedef struct dwc_otg_host_if {
-+	/** Host Global Registers starting at offset 400h.*/
-+	dwc_otg_host_global_regs_t *host_global_regs;
-+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
-+
-+	/** Host Port 0 Control and Status Register */
-+	volatile uint32_t *hprt0;
-+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
-+
-+	/** Host Channel Specific Registers at offsets 500h-5FCh. */
-+	dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
-+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
-+#define DWC_OTG_CHAN_REGS_OFFSET 0x20
-+
-+	/* Host configuration information */
-+	/** Number of Host Channels (range: 1-16) */
-+	uint8_t num_host_channels;
-+	/** Periodic EPs supported (0: no, 1: yes) */
-+	uint8_t perio_eps_supported;
-+	/** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
-+	uint16_t perio_tx_fifo_size;
-+
-+} dwc_otg_host_if_t;
-+
-+/**
-+ * This union represents the bit fields in the Power and Clock Gating Control
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union pcgcctl_data {
-+	/** raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		/** Stop Pclk */
-+		unsigned stoppclk:1;
-+		/** Gate Hclk */
-+		unsigned gatehclk:1;
-+		/** Power Clamp */
-+		unsigned pwrclmp:1;
-+		/** Reset Power Down Modules */
-+		unsigned rstpdwnmodule:1;
-+		/** Reserved */
-+		unsigned reserved:1;
-+		/** Enable Sleep Clock Gating (Enbl_L1Gating) */
-+		unsigned enbl_sleep_gating:1;
-+		/** PHY In Sleep (PhySleep) */
-+		unsigned phy_in_sleep:1;
-+		/** Deep Sleep*/
-+		unsigned deep_sleep:1;
-+		unsigned resetaftsusp:1;
-+		unsigned restoremode:1;
-+		unsigned enbl_extnd_hiber:1;
-+		unsigned extnd_hiber_pwrclmp:1;
-+		unsigned extnd_hiber_switch:1;
-+		unsigned ess_reg_restored:1;
-+		unsigned prt_clk_sel:2;
-+		unsigned port_power:1;
-+		unsigned max_xcvrselect:2;
-+		unsigned max_termsel:1;
-+		unsigned mac_dev_addr:7;
-+		unsigned p2hd_dev_enum_spd:2;
-+		unsigned p2hd_prt_spd:2;
-+		unsigned if_dev_mode:1;
-+	} b;
-+} pcgcctl_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Global Data FIFO Software
-+ * Configuration Register. Read the register into the <i>d32</i> member then
-+ * set/clear the bits using the <i>b</i>it elements.
-+ */
-+typedef union gdfifocfg_data {
-+	/* raw register data */
-+	uint32_t d32;
-+	/** register bits */
-+	struct {
-+		/** OTG Data FIFO depth */
-+		unsigned gdfifocfg:16;
-+		/** Start address of EP info controller */
-+		unsigned epinfobase:16;
-+	} b;
-+} gdfifocfg_data_t;
-+
-+/**
-+ * This union represents the bit fields in the Global Power Down Register
-+ * Register. Read the register into the <i>d32</i> member then set/clear the
-+ * bits using the <i>b</i>it elements.
-+ */
-+typedef union gpwrdn_data {
-+	/* raw register data */
-+	uint32_t d32;
-+
-+	/** register bits */
-+	struct {
-+		/** PMU Interrupt Select */
-+		unsigned pmuintsel:1;
-+		/** PMU Active */
-+		unsigned pmuactv:1;
-+		/** Restore */
-+		unsigned restore:1;
-+		/** Power Down Clamp */
-+		unsigned pwrdnclmp:1;
-+		/** Power Down Reset */
-+		unsigned pwrdnrstn:1;
-+		/** Power Down Switch */
-+		unsigned pwrdnswtch:1;
-+		/** Disable VBUS */
-+		unsigned dis_vbus:1;
-+		/** Line State Change */
-+		unsigned lnstschng:1;
-+		/** Line state change mask */
-+		unsigned lnstchng_msk:1;
-+		/** Reset Detected */
-+		unsigned rst_det:1;
-+		/** Reset Detect mask */
-+		unsigned rst_det_msk:1;
-+		/** Disconnect Detected */
-+		unsigned disconn_det:1;
-+		/** Disconnect Detect mask */
-+		unsigned disconn_det_msk:1;
-+		/** Connect Detected*/
-+		unsigned connect_det:1;
-+		/** Connect Detected Mask*/
-+		unsigned connect_det_msk:1;
-+		/** SRP Detected */
-+		unsigned srp_det:1;
-+		/** SRP Detect mask */
-+		unsigned srp_det_msk:1;
-+		/** Status Change Interrupt */
-+		unsigned sts_chngint:1;
-+		/** Status Change Interrupt Mask */
-+		unsigned sts_chngint_msk:1;
-+		/** Line State */
-+		unsigned linestate:2;
-+		/** Indicates current mode(status of IDDIG signal) */
-+		unsigned idsts:1;
-+		/** B Session Valid signal status*/
-+		unsigned bsessvld:1;
-+		/** ADP Event Detected */
-+		unsigned adp_int:1;
-+		/** Multi Valued ID pin */
-+		unsigned mult_val_id_bc:5;
-+		/** Reserved 24_31 */
-+		unsigned reserved29_31:3;
-+	} b;
-+} gpwrdn_data_t;
-+
-+#endif
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/test/Makefile
-@@ -0,0 +1,16 @@
-+
-+PERL=/usr/bin/perl
-+PL_TESTS=test_sysfs.pl test_mod_param.pl
-+
-+.PHONY : test
-+test : perl_tests
-+
-+perl_tests :
-+	@echo
-+	@echo Running perl tests
-+	@for test in $(PL_TESTS); do \
-+	  if $(PERL) ./$$test ; then \
-+	    echo "=======> $$test, PASSED" ; \
-+	  else echo "=======> $$test, FAILED" ; \
-+	  fi \
-+	done
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
-@@ -0,0 +1,337 @@
-+package dwc_otg_test;
-+
-+use strict;
-+use Exporter ();
-+
-+use vars qw(@ISA @EXPORT
-+$sysfsdir $paramdir $errors $params
-+);
-+
-+@ISA = qw(Exporter);
-+
-+#
-+# Globals
-+#
-+$sysfsdir = "/sys/devices/lm0";
-+$paramdir = "/sys/module/dwc_otg";
-+$errors = 0;
-+
-+$params = [
-+	   {
-+	    NAME => "otg_cap",
-+	    DEFAULT => 0,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 2
-+	   },
-+	   {
-+	    NAME => "dma_enable",
-+	    DEFAULT => 0,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 1
-+	   },
-+	   {
-+	    NAME => "dma_burst_size",
-+	    DEFAULT => 32,
-+	    ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
-+	    LOW => 1,
-+	    HIGH => 256
-+	   },
-+	   {
-+	    NAME => "host_speed",
-+	    DEFAULT => 0,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 1
-+	   },
-+	   {
-+	    NAME => "host_support_fs_ls_low_power",
-+	    DEFAULT => 0,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 1
-+	   },
-+	   {
-+	    NAME => "host_ls_low_power_phy_clk",
-+	    DEFAULT => 0,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 1
-+	   },
-+	   {
-+	    NAME => "dev_speed",
-+	    DEFAULT => 0,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 1
-+	   },
-+	   {
-+	    NAME => "enable_dynamic_fifo",
-+	    DEFAULT => 1,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 1
-+	   },
-+	   {
-+	    NAME => "data_fifo_size",
-+	    DEFAULT => 8192,
-+	    ENUM => [],
-+	    LOW => 32,
-+	    HIGH => 32768
-+	   },
-+	   {
-+	    NAME => "dev_rx_fifo_size",
-+	    DEFAULT => 1064,
-+	    ENUM => [],
-+	    LOW => 16,
-+	    HIGH => 32768
-+	   },
-+	   {
-+	    NAME => "dev_nperio_tx_fifo_size",
-+	    DEFAULT => 1024,
-+	    ENUM => [],
-+	    LOW => 16,
-+	    HIGH => 32768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_1",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_2",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_3",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_4",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_5",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_6",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_7",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_8",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_9",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_10",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_11",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_12",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_13",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_14",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "dev_perio_tx_fifo_size_15",
-+	    DEFAULT => 256,
-+	    ENUM => [],
-+	    LOW => 4,
-+	    HIGH => 768
-+	   },
-+	   {
-+	    NAME => "host_rx_fifo_size",
-+	    DEFAULT => 1024,
-+	    ENUM => [],
-+	    LOW => 16,
-+	    HIGH => 32768
-+	   },
-+	   {
-+	    NAME => "host_nperio_tx_fifo_size",
-+	    DEFAULT => 1024,
-+	    ENUM => [],
-+	    LOW => 16,
-+	    HIGH => 32768
-+	   },
-+	   {
-+	    NAME => "host_perio_tx_fifo_size",
-+	    DEFAULT => 1024,
-+	    ENUM => [],
-+	    LOW => 16,
-+	    HIGH => 32768
-+	   },
-+	   {
-+	    NAME => "max_transfer_size",
-+	    DEFAULT => 65535,
-+	    ENUM => [],
-+	    LOW => 2047,
-+	    HIGH => 65535
-+	   },
-+	   {
-+	    NAME => "max_packet_count",
-+	    DEFAULT => 511,
-+	    ENUM => [],
-+	    LOW => 15,
-+	    HIGH => 511
-+	   },
-+	   {
-+	    NAME => "host_channels",
-+	    DEFAULT => 12,
-+	    ENUM => [],
-+	    LOW => 1,
-+	    HIGH => 16
-+	   },
-+	   {
-+	    NAME => "dev_endpoints",
-+	    DEFAULT => 6,
-+	    ENUM => [],
-+	    LOW => 1,
-+	    HIGH => 15
-+	   },
-+	   {
-+	    NAME => "phy_type",
-+	    DEFAULT => 1,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 2
-+	   },
-+	   {
-+	    NAME => "phy_utmi_width",
-+	    DEFAULT => 16,
-+	    ENUM => [8, 16],
-+	    LOW => 8,
-+	    HIGH => 16
-+	   },
-+	   {
-+	    NAME => "phy_ulpi_ddr",
-+	    DEFAULT => 0,
-+	    ENUM => [],
-+	    LOW => 0,
-+	    HIGH => 1
-+	   },
-+	  ];
-+
-+
-+#
-+#
-+sub check_arch {
-+  $_ = `uname -m`;
-+  chomp;
-+  unless (m/armv4tl/) {
-+    warn "# \n# Can't execute on $_.  Run on integrator platform.\n# \n";
-+    return 0;
-+  }
-+  return 1;
-+}
-+
-+#
-+#
-+sub load_module {
-+  my $params = shift;
-+  print "\nRemoving Module\n";
-+  system "rmmod dwc_otg";
-+  print "Loading Module\n";
-+  if ($params ne "") {
-+    print "Module Parameters: $params\n";
-+  }
-+  if (system("modprobe dwc_otg $params")) {
-+    warn "Unable to load module\n";
-+    return 0;
-+  }
-+  return 1;
-+}
-+
-+#
-+#
-+sub test_status {
-+  my $arg = shift;
-+
-+  print "\n";
-+
-+  if (defined $arg) {
-+    warn "WARNING: $arg\n";
-+  }
-+
-+  if ($errors > 0) {
-+    warn "TEST FAILED with $errors errors\n";
-+    return 0;
-+  } else {
-+    print "TEST PASSED\n";
-+    return 0 if (defined $arg);
-+  }
-+  return 1;
-+}
-+
-+#
-+#
-+@EXPORT = qw(
-+$sysfsdir
-+$paramdir
-+$params
-+$errors
-+check_arch
-+load_module
-+test_status
-+);
-+
-+1;
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/test/test_mod_param.pl
-@@ -0,0 +1,133 @@
-+#!/usr/bin/perl -w
-+#
-+# Run this program on the integrator.
-+#
-+# - Tests module parameter default values.
-+# - Tests setting of valid module parameter values via modprobe.
-+# - Tests invalid module parameter values.
-+# -----------------------------------------------------------------------------
-+use strict;
-+use dwc_otg_test;
-+
-+check_arch() or die;
-+
-+#
-+#
-+sub test {
-+  my ($param,$expected) = @_;
-+  my $value = get($param);
-+
-+  if ($value == $expected) {
-+    print "$param = $value, okay\n";
-+  }
-+
-+  else {
-+    warn "ERROR: value of $param != $expected, $value\n";
-+    $errors ++;
-+  }
-+}
-+
-+#
-+#
-+sub get {
-+  my $param = shift;
-+  my $tmp = `cat $paramdir/$param`;
-+  chomp $tmp;
-+  return $tmp;
-+}
-+
-+#
-+#
-+sub test_main {
-+
-+  print "\nTesting Module Parameters\n";
-+
-+  load_module("") or die;
-+
-+  # Test initial values
-+  print "\nTesting Default Values\n";
-+  foreach (@{$params}) {
-+    test ($_->{NAME}, $_->{DEFAULT});
-+  }
-+
-+  # Test low value
-+  print "\nTesting Low Value\n";
-+  my $cmd_params = "";
-+  foreach (@{$params}) {
-+    $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
-+  }
-+  load_module($cmd_params) or die;
-+
-+  foreach (@{$params}) {
-+    test ($_->{NAME}, $_->{LOW});
-+  }
-+
-+  # Test high value
-+  print "\nTesting High Value\n";
-+  $cmd_params = "";
-+  foreach (@{$params}) {
-+    $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
-+  }
-+  load_module($cmd_params) or die;
-+
-+  foreach (@{$params}) {
-+    test ($_->{NAME}, $_->{HIGH});
-+  }
-+
-+  # Test Enum
-+  print "\nTesting Enumerated\n";
-+  foreach (@{$params}) {
-+    if (defined $_->{ENUM}) {
-+      my $value;
-+      foreach $value (@{$_->{ENUM}}) {
-+	$cmd_params = "$_->{NAME}=$value";
-+	load_module($cmd_params) or die;
-+	test ($_->{NAME}, $value);
-+      }
-+    }
-+  }
-+
-+  # Test Invalid Values
-+  print "\nTesting Invalid Values\n";
-+  $cmd_params = "";
-+  foreach (@{$params}) {
-+    $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
-+  }
-+  load_module($cmd_params) or die;
-+
-+  foreach (@{$params}) {
-+    test ($_->{NAME}, $_->{DEFAULT});
-+  }
-+
-+  $cmd_params = "";
-+  foreach (@{$params}) {
-+    $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
-+  }
-+  load_module($cmd_params) or die;
-+
-+  foreach (@{$params}) {
-+    test ($_->{NAME}, $_->{DEFAULT});
-+  }
-+
-+  print "\nTesting Enumerated\n";
-+  foreach (@{$params}) {
-+    if (defined $_->{ENUM}) {
-+      my $value;
-+      foreach $value (@{$_->{ENUM}}) {
-+	$value = $value + 1;
-+	$cmd_params = "$_->{NAME}=$value";
-+	load_module($cmd_params) or die;
-+	test ($_->{NAME}, $_->{DEFAULT});
-+	$value = $value - 2;
-+	$cmd_params = "$_->{NAME}=$value";
-+	load_module($cmd_params) or die;
-+	test ($_->{NAME}, $_->{DEFAULT});
-+      }
-+    }
-+  }
-+
-+  test_status() or die;
-+}
-+
-+test_main();
-+0;
---- /dev/null
-+++ b/drivers/usb/host/dwc_otg/test/test_sysfs.pl
-@@ -0,0 +1,193 @@
-+#!/usr/bin/perl -w
-+#
-+# Run this program on the integrator
-+# - Tests select sysfs attributes.
-+# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
-+# -----------------------------------------------------------------------------
-+use strict;
-+use dwc_otg_test;
-+
-+check_arch() or die;
-+
-+#
-+#
-+sub test {
-+  my ($attr,$expected) = @_;
-+  my $string = get($attr);
-+
-+  if ($string eq $expected) {
-+    printf("$attr = $string, okay\n");
-+  }
-+  else {
-+    warn "ERROR: value of $attr != $expected, $string\n";
-+    $errors ++;
-+  }
-+}
-+
-+#
-+#
-+sub set {
-+  my ($reg, $value) = @_;
-+  system "echo $value > $sysfsdir/$reg";
-+}
-+
-+#
-+#
-+sub get {
-+  my $attr = shift;
-+  my $string = `cat $sysfsdir/$attr`;
-+  chomp $string;
-+  if ($string =~ m/\s\=\s/) {
-+    my $tmp;
-+    ($tmp, $string) = split /\s=\s/, $string;
-+  }
-+  return $string;
-+}
-+
-+#
-+#
-+sub test_main {
-+  print("\nTesting Sysfs Attributes\n");
-+
-+  load_module("") or die;
-+
-+  # Test initial values of regoffset/regvalue/guid/gsnpsid
-+  print("\nTesting Default Values\n");
-+
-+  test("regoffset", "0xffffffff");
-+  test("regvalue", "invalid offset");
-+  test("guid", "0x12345678");	# this will fail if it has been changed
-+  test("gsnpsid", "0x4f54200a");
-+
-+  # Test operation of regoffset/regvalue
-+  print("\nTesting regoffset\n");
-+  set('regoffset', '5a5a5a5a');
-+  test("regoffset", "0xffffffff");
-+
-+  set('regoffset', '0');
-+  test("regoffset", "0x00000000");
-+
-+  set('regoffset', '40000');
-+  test("regoffset", "0x00000000");
-+
-+  set('regoffset', '3ffff');
-+  test("regoffset", "0x0003ffff");
-+
-+  set('regoffset', '1');
-+  test("regoffset", "0x00000001");
-+
-+  print("\nTesting regvalue\n");
-+  set('regoffset', '3c');
-+  test("regvalue", "0x12345678");
-+  set('regvalue', '5a5a5a5a');
-+  test("regvalue", "0x5a5a5a5a");
-+  set('regvalue','a5a5a5a5');
-+  test("regvalue", "0xa5a5a5a5");
-+  set('guid','12345678');
-+
-+  # Test HNP Capable
-+  print("\nTesting HNP Capable bit\n");
-+  set('hnpcapable', '1');
-+  test("hnpcapable", "0x1");
-+  set('hnpcapable','0');
-+  test("hnpcapable", "0x0");
-+
-+  set('regoffset','0c');
-+
-+  my $old = get('gusbcfg');
-+  print("setting hnpcapable\n");
-+  set('hnpcapable', '1');
-+  test("hnpcapable", "0x1");
-+  test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
-+  test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
-+
-+  $old = get('gusbcfg');
-+  print("clearing hnpcapable\n");
-+  set('hnpcapable', '0');
-+  test("hnpcapable", "0x0");
-+  test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
-+  test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
-+
-+  # Test SRP Capable
-+  print("\nTesting SRP Capable bit\n");
-+  set('srpcapable', '1');
-+  test("srpcapable", "0x1");
-+  set('srpcapable','0');
-+  test("srpcapable", "0x0");
-+
-+  set('regoffset','0c');
-+
-+  $old = get('gusbcfg');
-+  print("setting srpcapable\n");
-+  set('srpcapable', '1');
-+  test("srpcapable", "0x1");
-+  test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
-+  test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
-+
-+  $old = get('gusbcfg');
-+  print("clearing srpcapable\n");
-+  set('srpcapable', '0');
-+  test("srpcapable", "0x0");
-+  test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
-+  test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
-+
-+  # Test GGPIO
-+  print("\nTesting GGPIO\n");
-+  set('ggpio','5a5a5a5a');
-+  test('ggpio','0x5a5a0000');
-+  set('ggpio','a5a5a5a5');
-+  test('ggpio','0xa5a50000');
-+  set('ggpio','11110000');
-+  test('ggpio','0x11110000');
-+  set('ggpio','00001111');
-+  test('ggpio','0x00000000');
-+
-+  # Test DEVSPEED
-+  print("\nTesting DEVSPEED\n");
-+  set('regoffset','800');
-+  $old = get('regvalue');
-+  set('devspeed','0');
-+  test('devspeed','0x0');
-+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
-+  set('devspeed','1');
-+  test('devspeed','0x1');
-+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
-+  set('devspeed','2');
-+  test('devspeed','0x2');
-+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
-+  set('devspeed','3');
-+  test('devspeed','0x3');
-+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
-+  set('devspeed','4');
-+  test('devspeed','0x0');
-+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
-+  set('devspeed','5');
-+  test('devspeed','0x1');
-+  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
-+
-+
-+  #  mode	Returns the current mode:0 for device mode1 for host mode	Read
-+  #  hnp	Initiate the Host Negotiation Protocol.  Read returns the status.	Read/Write
-+  #  srp	Initiate the Session Request Protocol.  Read returns the status.	Read/Write
-+  #  buspower	Get or Set the Power State of the bus (0 - Off or 1 - On) 	Read/Write
-+  #  bussuspend	Suspend the USB bus.	Read/Write
-+  #  busconnected	Get the connection status of the bus 	Read
-+
-+  #  gotgctl	Get or set the Core Control Status Register.	Read/Write
-+  ##  gusbcfg	Get or set the Core USB Configuration Register	Read/Write
-+  #  grxfsiz	Get or set the Receive FIFO Size Register	Read/Write
-+  #  gnptxfsiz	Get or set the non-periodic Transmit Size Register	Read/Write
-+  #  gpvndctl	Get or set the PHY Vendor Control Register	Read/Write
-+  ##  ggpio	Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits.	Read/Write
-+  ##  guid	Get or set the value of the User ID Register	Read/Write
-+  ##  gsnpsid	Get the value of the Synopsys ID Regester	Read
-+  ##  devspeed	Get or set the device speed setting in the DCFG register	Read/Write
-+  #  enumspeed	Gets the device enumeration Speed.	Read
-+  #  hptxfsiz	Get the value of the Host Periodic Transmit FIFO	Read
-+  #  hprt0	Get or Set the value in the Host Port Control and Status Register	Read/Write
-+
-+  test_status("TEST NYI") or die;
-+}
-+
-+test_main();
-+0;
diff --git a/target/linux/brcm2708/patches-4.14/950-0038-bcm2708-framebuffer-driver.patch b/target/linux/brcm2708/patches-4.14/950-0038-bcm2708-framebuffer-driver.patch
deleted file mode 100644
index ab9ec567a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0038-bcm2708-framebuffer-driver.patch
+++ /dev/null
@@ -1,3452 +0,0 @@
-From 0643c9d81a31858a733825bcc605a135f47a6aec Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Wed, 17 Jun 2015 17:06:34 +0100
-Subject: [PATCH 038/454] bcm2708 framebuffer driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
-
-bcm2708_fb : Implement blanking support using the mailbox property interface
-
-bcm2708_fb: Add pan and vsync controls
-
-bcm2708_fb: DMA acceleration for fb_copyarea
-
-Based on http://www.raspberrypi.org/phpBB3/viewtopic.php?p=62425#p62425
-Also used Simon's dmaer_master module as a reference for tweaking DMA
-settings for better performance.
-
-For now busylooping only. IRQ support might be added later.
-With non-overclocked Raspberry Pi, the performance is ~360 MB/s
-for simple copy or ~260 MB/s for two-pass copy (used when dragging
-windows to the right).
-
-In the case of using DMA channel 0, the performance improves
-to ~440 MB/s.
-
-For comparison, VFP optimized CPU copy can only do ~114 MB/s in
-the same conditions (hindered by reading uncached source buffer).
-
-Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
-
-bcm2708_fb: report number of dma copies
-
-Add a counter (exported via debugfs) reporting the
-number of dma copies that the framebuffer driver
-has done, in order to help evaluate different
-optimization strategies.
-
-Signed-off-by: Luke Diamand <luked@broadcom.com>
-
-bcm2708_fb: use IRQ for DMA copies
-
-The copyarea ioctl() uses DMA to speed things along. This
-was busy-waiting for completion. This change supports using
-an interrupt instead for larger transfers. For small
-transfers, busy-waiting is still likely to be faster.
-
-Signed-off-by: Luke Diamand <luke@diamand.org>
-
-bcm2708: Make ioctl logging quieter
-
-video: fbdev: bcm2708_fb: Don't panic on error
-
-No need to panic the kernel if the video driver fails.
-Just print a message and return an error.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-fbdev: bcm2708_fb: Add ARCH_BCM2835 support
-
-Add Device Tree support.
-Pass the device to dma_alloc_coherent() in order to get the
-correct bus address on ARCH_BCM2835.
-Use the new DMA legacy API header file.
-Including <mach/platform.h> is not necessary.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-BCM270x_DT: Add bcm2708-fb device
-
-Add bcm2708-fb to Device Tree and don't add the
-platform device when booting in DT mode.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/video/fbdev/Kconfig               |   14 +
- drivers/video/fbdev/Makefile              |    1 +
- drivers/video/fbdev/bcm2708_fb.c          |  844 +++++++
- drivers/video/logo/logo_linux_clut224.ppm | 2483 ++++++++-------------
- 4 files changed, 1740 insertions(+), 1602 deletions(-)
- create mode 100644 drivers/video/fbdev/bcm2708_fb.c
-
---- a/drivers/video/fbdev/Kconfig
-+++ b/drivers/video/fbdev/Kconfig
-@@ -236,6 +236,20 @@ config FB_TILEBLITTING
- comment "Frame buffer hardware drivers"
- 	depends on FB
- 
-+config FB_BCM2708
-+	tristate "BCM2708 framebuffer support"
-+	depends on FB && RASPBERRYPI_FIRMWARE
-+	select FB_CFB_FILLRECT
-+	select FB_CFB_COPYAREA
-+	select FB_CFB_IMAGEBLIT
-+	help
-+	  This framebuffer device driver is for the BCM2708 framebuffer.
-+
-+	  If you want to compile this as a module (=code which can be
-+	  inserted into and removed from the running kernel), say M
-+	  here and read <file:Documentation/kbuild/modules.txt>.  The module
-+	  will be called bcm2708_fb.
-+
- config FB_GRVGA
- 	tristate "Aeroflex Gaisler framebuffer support"
- 	depends on FB && SPARC
---- a/drivers/video/fbdev/Makefile
-+++ b/drivers/video/fbdev/Makefile
-@@ -11,6 +11,7 @@ obj-$(CONFIG_FB_MACMODES)      += macmod
- obj-$(CONFIG_FB_WMT_GE_ROPS)   += wmt_ge_rops.o
- 
- # Hardware specific drivers go first
-+obj-$(CONFIG_FB_BCM2708)	  += bcm2708_fb.o
- obj-$(CONFIG_FB_AMIGA)            += amifb.o c2p_planar.o
- obj-$(CONFIG_FB_ARC)              += arcfb.o
- obj-$(CONFIG_FB_CLPS711X)	  += clps711x-fb.o
---- /dev/null
-+++ b/drivers/video/fbdev/bcm2708_fb.c
-@@ -0,0 +1,844 @@
-+/*
-+ *  linux/drivers/video/bcm2708_fb.c
-+ *
-+ * Copyright (C) 2010 Broadcom
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file COPYING in the main directory of this archive
-+ * for more details.
-+ *
-+ * Broadcom simple framebuffer driver
-+ *
-+ * This file is derived from cirrusfb.c
-+ * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
-+ *
-+ */
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/slab.h>
-+#include <linux/mm.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/list.h>
-+#include <linux/platform_data/dma-bcm2708.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/printk.h>
-+#include <linux/console.h>
-+#include <linux/debugfs.h>
-+#include <asm/sizes.h>
-+#include <linux/io.h>
-+#include <linux/dma-mapping.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+//#define BCM2708_FB_DEBUG
-+#define MODULE_NAME "bcm2708_fb"
-+
-+#ifdef BCM2708_FB_DEBUG
-+#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+
-+/* This is limited to 16 characters when displayed by X startup */
-+static const char *bcm2708_name = "BCM2708 FB";
-+
-+#define DRIVER_NAME "bcm2708_fb"
-+
-+static int fbwidth = 800;  /* module parameter */
-+static int fbheight = 480; /* module parameter */
-+static int fbdepth = 32;   /* module parameter */
-+static int fbswap = 0;     /* module parameter */
-+
-+static u32 dma_busy_wait_threshold = 1<<15;
-+module_param(dma_busy_wait_threshold, int, 0644);
-+MODULE_PARM_DESC(dma_busy_wait_threshold, "Busy-wait for DMA completion below this area");
-+
-+struct fb_alloc_tags {
-+	struct rpi_firmware_property_tag_header tag1;
-+	u32 xres, yres;
-+	struct rpi_firmware_property_tag_header tag2;
-+	u32 xres_virtual, yres_virtual;
-+	struct rpi_firmware_property_tag_header tag3;
-+	u32 bpp;
-+	struct rpi_firmware_property_tag_header tag4;
-+	u32 xoffset, yoffset;
-+	struct rpi_firmware_property_tag_header tag5;
-+	u32 base, screen_size;
-+	struct rpi_firmware_property_tag_header tag6;
-+	u32 pitch;
-+};
-+
-+struct bcm2708_fb_stats {
-+	struct debugfs_regset32 regset;
-+	u32 dma_copies;
-+	u32 dma_irqs;
-+};
-+
-+struct bcm2708_fb {
-+	struct fb_info fb;
-+	struct platform_device *dev;
-+	struct rpi_firmware *fw;
-+	u32 cmap[16];
-+	u32 gpu_cmap[256];
-+	int dma_chan;
-+	int dma_irq;
-+	void __iomem *dma_chan_base;
-+	void *cb_base;		/* DMA control blocks */
-+	dma_addr_t cb_handle;
-+	struct dentry *debugfs_dir;
-+	wait_queue_head_t dma_waitq;
-+	struct bcm2708_fb_stats stats;
-+	unsigned long fb_bus_address;
-+};
-+
-+#define to_bcm2708(info)	container_of(info, struct bcm2708_fb, fb)
-+
-+static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb)
-+{
-+	debugfs_remove_recursive(fb->debugfs_dir);
-+	fb->debugfs_dir = NULL;
-+}
-+
-+static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb)
-+{
-+	static struct debugfs_reg32 stats_registers[] = {
-+		{
-+			"dma_copies",
-+			offsetof(struct bcm2708_fb_stats, dma_copies)
-+		},
-+		{
-+			"dma_irqs",
-+			offsetof(struct bcm2708_fb_stats, dma_irqs)
-+		},
-+	};
-+
-+	fb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL);
-+	if (!fb->debugfs_dir) {
-+		pr_warn("%s: could not create debugfs entry\n",
-+			__func__);
-+		return -EFAULT;
-+	}
-+
-+	fb->stats.regset.regs = stats_registers;
-+	fb->stats.regset.nregs = ARRAY_SIZE(stats_registers);
-+	fb->stats.regset.base = &fb->stats;
-+
-+	if (!debugfs_create_regset32(
-+		"stats", 0444, fb->debugfs_dir, &fb->stats.regset)) {
-+		pr_warn("%s: could not create statistics registers\n",
-+			__func__);
-+		goto fail;
-+	}
-+	return 0;
-+
-+fail:
-+	bcm2708_fb_debugfs_deinit(fb);
-+	return -EFAULT;
-+}
-+
-+static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var)
-+{
-+	int ret = 0;
-+
-+	memset(&var->transp, 0, sizeof(var->transp));
-+
-+	var->red.msb_right = 0;
-+	var->green.msb_right = 0;
-+	var->blue.msb_right = 0;
-+
-+	switch (var->bits_per_pixel) {
-+	case 1:
-+	case 2:
-+	case 4:
-+	case 8:
-+		var->red.length = var->bits_per_pixel;
-+		var->red.offset = 0;
-+		var->green.length = var->bits_per_pixel;
-+		var->green.offset = 0;
-+		var->blue.length = var->bits_per_pixel;
-+		var->blue.offset = 0;
-+		break;
-+	case 16:
-+		var->red.length = 5;
-+		var->blue.length = 5;
-+		/*
-+		 * Green length can be 5 or 6 depending whether
-+		 * we're operating in RGB555 or RGB565 mode.
-+		 */
-+		if (var->green.length != 5 && var->green.length != 6)
-+			var->green.length = 6;
-+		break;
-+	case 24:
-+		var->red.length = 8;
-+		var->blue.length = 8;
-+		var->green.length = 8;
-+		break;
-+	case 32:
-+		var->red.length = 8;
-+		var->green.length = 8;
-+		var->blue.length = 8;
-+		var->transp.length = 8;
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		break;
-+	}
-+
-+	/*
-+	 * >= 16bpp displays have separate colour component bitfields
-+	 * encoded in the pixel data.  Calculate their position from
-+	 * the bitfield length defined above.
-+	 */
-+	if (ret == 0 && var->bits_per_pixel >= 24 && fbswap) {
-+		var->blue.offset = 0;
-+		var->green.offset = var->blue.offset + var->blue.length;
-+		var->red.offset = var->green.offset + var->green.length;
-+		var->transp.offset = var->red.offset + var->red.length;
-+	} else if (ret == 0 && var->bits_per_pixel >= 24) {
-+		var->red.offset = 0;
-+		var->green.offset = var->red.offset + var->red.length;
-+		var->blue.offset = var->green.offset + var->green.length;
-+		var->transp.offset = var->blue.offset + var->blue.length;
-+	} else if (ret == 0 && var->bits_per_pixel >= 16) {
-+		var->blue.offset = 0;
-+		var->green.offset = var->blue.offset + var->blue.length;
-+		var->red.offset = var->green.offset + var->green.length;
-+		var->transp.offset = var->red.offset + var->red.length;
-+	}
-+
-+	return ret;
-+}
-+
-+static int bcm2708_fb_check_var(struct fb_var_screeninfo *var,
-+				struct fb_info *info)
-+{
-+	/* info input, var output */
-+	print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info,
-+		info->var.xres, info->var.yres, info->var.xres_virtual,
-+		info->var.yres_virtual, (int)info->screen_size,
-+		info->var.bits_per_pixel);
-+	print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var,
-+		var->xres, var->yres, var->xres_virtual, var->yres_virtual,
-+		var->bits_per_pixel);
-+
-+	if (!var->bits_per_pixel)
-+		var->bits_per_pixel = 16;
-+
-+	if (bcm2708_fb_set_bitfields(var) != 0) {
-+		pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n",
-+		     var->bits_per_pixel);
-+		return -EINVAL;
-+	}
-+
-+
-+	if (var->xres_virtual < var->xres)
-+		var->xres_virtual = var->xres;
-+	/* use highest possible virtual resolution */
-+	if (var->yres_virtual == -1) {
-+		var->yres_virtual = 480;
-+
-+		pr_err
-+		    ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n",
-+		     var->xres_virtual, var->yres_virtual);
-+	}
-+	if (var->yres_virtual < var->yres)
-+		var->yres_virtual = var->yres;
-+
-+	if (var->xoffset < 0)
-+		var->xoffset = 0;
-+	if (var->yoffset < 0)
-+		var->yoffset = 0;
-+
-+	/* truncate xoffset and yoffset to maximum if too high */
-+	if (var->xoffset > var->xres_virtual - var->xres)
-+		var->xoffset = var->xres_virtual - var->xres - 1;
-+	if (var->yoffset > var->yres_virtual - var->yres)
-+		var->yoffset = var->yres_virtual - var->yres - 1;
-+
-+	return 0;
-+}
-+
-+static int bcm2708_fb_set_par(struct fb_info *info)
-+{
-+	struct bcm2708_fb *fb = to_bcm2708(info);
-+	struct fb_alloc_tags fbinfo = {
-+		.tag1 = { RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT,
-+			  8, 0, },
-+			.xres = info->var.xres,
-+			.yres = info->var.yres,
-+		.tag2 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT,
-+			  8, 0, },
-+			.xres_virtual = info->var.xres_virtual,
-+			.yres_virtual = info->var.yres_virtual,
-+		.tag3 = { RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH, 4, 0 },
-+			.bpp = info->var.bits_per_pixel,
-+		.tag4 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET, 8, 0 },
-+			.xoffset = info->var.xoffset,
-+			.yoffset = info->var.yoffset,
-+		.tag5 = { RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE, 8, 0 },
-+			.base = 0,
-+			.screen_size = 0,
-+		.tag6 = { RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH, 4, 0 },
-+			.pitch = 0,
-+	};
-+	int ret;
-+
-+	print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info,
-+		info->var.xres, info->var.yres, info->var.xres_virtual,
-+		info->var.yres_virtual, (int)info->screen_size,
-+		info->var.bits_per_pixel);
-+
-+	ret = rpi_firmware_property_list(fb->fw, &fbinfo, sizeof(fbinfo));
-+	if (ret) {
-+		dev_err(info->device,
-+			"Failed to allocate GPU framebuffer (%d)\n", ret);
-+		return ret;
-+	}
-+
-+	if (info->var.bits_per_pixel <= 8)
-+		fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
-+	else
-+		fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
-+
-+	fb->fb.fix.line_length = fbinfo.pitch;
-+	fbinfo.base |= 0x40000000;
-+	fb->fb_bus_address = fbinfo.base;
-+	fbinfo.base &= ~0xc0000000;
-+	fb->fb.fix.smem_start = fbinfo.base;
-+	fb->fb.fix.smem_len = fbinfo.pitch * fbinfo.yres_virtual;
-+	fb->fb.screen_size = fbinfo.screen_size;
-+	if (fb->fb.screen_base)
-+		iounmap(fb->fb.screen_base);
-+	fb->fb.screen_base = ioremap_wc(fbinfo.base, fb->fb.screen_size);
-+	if (!fb->fb.screen_base) {
-+		/* the console may currently be locked */
-+		console_trylock();
-+		console_unlock();
-+		dev_err(info->device, "Failed to set screen_base\n");
-+		return -ENOMEM;
-+	}
-+
-+	print_debug
-+	    ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d\n",
-+	     (void *)fb->fb.screen_base, (void *)fb->fb_bus_address,
-+	     fbinfo.xres, fbinfo.yres, fbinfo.bpp,
-+	     fbinfo.pitch, (int)fb->fb.screen_size);
-+
-+	return 0;
-+}
-+
-+static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
-+{
-+	unsigned int mask = (1 << bf->length) - 1;
-+
-+	return (val >> (16 - bf->length) & mask) << bf->offset;
-+}
-+
-+
-+static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red,
-+				unsigned int green, unsigned int blue,
-+				unsigned int transp, struct fb_info *info)
-+{
-+	struct bcm2708_fb *fb = to_bcm2708(info);
-+
-+	/*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/
-+	if (fb->fb.var.bits_per_pixel <= 8) {
-+		if (regno < 256) {
-+			/* blue [23:16], green [15:8], red [7:0] */
-+			fb->gpu_cmap[regno] = ((red   >> 8) & 0xff) << 0 |
-+					      ((green >> 8) & 0xff) << 8 |
-+					      ((blue  >> 8) & 0xff) << 16;
-+		}
-+		/* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */
-+		/* So just call it for what looks like the last colour in a list for now. */
-+		if (regno == 15 || regno == 255) {
-+			struct packet {
-+				u32 offset;
-+				u32 length;
-+				u32 cmap[256];
-+			} *packet;
-+			int ret;
-+
-+			packet = kmalloc(sizeof(*packet), GFP_KERNEL);
-+			if (!packet)
-+				return -ENOMEM;
-+			packet->offset = 0;
-+			packet->length = regno + 1;
-+			memcpy(packet->cmap, fb->gpu_cmap, sizeof(packet->cmap));
-+			ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE,
-+						    packet, (2 + packet->length) * sizeof(u32));
-+			if (ret || packet->offset)
-+				dev_err(info->device, "Failed to set palette (%d,%u)\n",
-+					ret, packet->offset);
-+			kfree(packet);
-+		}
-+        } else if (regno < 16) {
-+		fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
-+		    convert_bitfield(blue, &fb->fb.var.blue) |
-+		    convert_bitfield(green, &fb->fb.var.green) |
-+		    convert_bitfield(red, &fb->fb.var.red);
-+	}
-+	return regno > 255;
-+}
-+
-+static int bcm2708_fb_blank(int blank_mode, struct fb_info *info)
-+{
-+	struct bcm2708_fb *fb = to_bcm2708(info);
-+	u32 value;
-+	int ret;
-+
-+	switch (blank_mode) {
-+	case FB_BLANK_UNBLANK:
-+		value = 0;
-+		break;
-+	case FB_BLANK_NORMAL:
-+	case FB_BLANK_VSYNC_SUSPEND:
-+	case FB_BLANK_HSYNC_SUSPEND:
-+	case FB_BLANK_POWERDOWN:
-+		value = 1;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK,
-+				    &value, sizeof(value));
-+	if (ret)
-+		dev_err(info->device, "bcm2708_fb_blank(%d) failed: %d\n",
-+			blank_mode, ret);
-+
-+	return ret;
-+}
-+
-+static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
-+{
-+	s32 result;
-+	info->var.xoffset = var->xoffset;
-+	info->var.yoffset = var->yoffset;
-+	result = bcm2708_fb_set_par(info);
-+	if (result != 0)
-+		pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result);
-+	return result;
-+}
-+
-+static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
-+{
-+	struct bcm2708_fb *fb = to_bcm2708(info);
-+	u32 dummy = 0;
-+	int ret;
-+
-+	switch (cmd) {
-+	case FBIO_WAITFORVSYNC:
-+		ret = rpi_firmware_property(fb->fw,
-+					    RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC,
-+					    &dummy, sizeof(dummy));
-+		break;
-+	default:
-+		dev_dbg(info->device, "Unknown ioctl 0x%x\n", cmd);
-+		return -ENOTTY;
-+	}
-+
-+	if (ret)
-+		dev_err(info->device, "ioctl 0x%x failed (%d)\n", cmd, ret);
-+
-+	return ret;
-+}
-+static void bcm2708_fb_fillrect(struct fb_info *info,
-+				const struct fb_fillrect *rect)
-+{
-+	/* (is called) print_debug("bcm2708_fb_fillrect\n"); */
-+	cfb_fillrect(info, rect);
-+}
-+
-+/* A helper function for configuring dma control block */
-+static void set_dma_cb(struct bcm2708_dma_cb *cb,
-+		       int        burst_size,
-+		       dma_addr_t dst,
-+		       int        dst_stride,
-+		       dma_addr_t src,
-+		       int        src_stride,
-+		       int        w,
-+		       int        h)
-+{
-+	cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH |
-+		   BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |
-+		   BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE;
-+	cb->dst = dst;
-+	cb->src = src;
-+	/*
-+	 * This is not really obvious from the DMA documentation,
-+	 * but the top 16 bits must be programmmed to "height -1"
-+	 * and not "height" in 2D mode.
-+	 */
-+	cb->length = ((h - 1) << 16) | w;
-+	cb->stride = ((dst_stride - w) << 16) | (u16)(src_stride - w);
-+	cb->pad[0] = 0;
-+	cb->pad[1] = 0;
-+}
-+
-+static void bcm2708_fb_copyarea(struct fb_info *info,
-+				const struct fb_copyarea *region)
-+{
-+	struct bcm2708_fb *fb = to_bcm2708(info);
-+	struct bcm2708_dma_cb *cb = fb->cb_base;
-+	int bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3;
-+	/* Channel 0 supports larger bursts and is a bit faster */
-+	int burst_size = (fb->dma_chan == 0) ? 8 : 2;
-+	int pixels = region->width * region->height;
-+
-+	/* Fallback to cfb_copyarea() if we don't like something */
-+	if (in_atomic() ||
-+	    bytes_per_pixel > 4 ||
-+	    info->var.xres * info->var.yres > 1920 * 1200 ||
-+	    region->width <= 0 || region->width > info->var.xres ||
-+	    region->height <= 0 || region->height > info->var.yres ||
-+	    region->sx < 0 || region->sx >= info->var.xres ||
-+	    region->sy < 0 || region->sy >= info->var.yres ||
-+	    region->dx < 0 || region->dx >= info->var.xres ||
-+	    region->dy < 0 || region->dy >= info->var.yres ||
-+	    region->sx + region->width > info->var.xres ||
-+	    region->dx + region->width > info->var.xres ||
-+	    region->sy + region->height > info->var.yres ||
-+	    region->dy + region->height > info->var.yres) {
-+		cfb_copyarea(info, region);
-+		return;
-+	}
-+
-+	if (region->dy == region->sy && region->dx > region->sx) {
-+		/*
-+		 * A difficult case of overlapped copy. Because DMA can't
-+		 * copy individual scanlines in backwards direction, we need
-+		 * two-pass processing. We do it by programming a chain of dma
-+		 * control blocks in the first 16K part of the buffer and use
-+		 * the remaining 48K as the intermediate temporary scratch
-+		 * buffer. The buffer size is sufficient to handle up to
-+		 * 1920x1200 resolution at 32bpp pixel depth.
-+		 */
-+		int y;
-+		dma_addr_t control_block_pa = fb->cb_handle;
-+		dma_addr_t scratchbuf = fb->cb_handle + 16 * 1024;
-+		int scanline_size = bytes_per_pixel * region->width;
-+		int scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size;
-+
-+		for (y = 0; y < region->height; y += scanlines_per_cb) {
-+			dma_addr_t src =
-+				fb->fb_bus_address +
-+				bytes_per_pixel * region->sx +
-+				(region->sy + y) * fb->fb.fix.line_length;
-+			dma_addr_t dst =
-+				fb->fb_bus_address +
-+				bytes_per_pixel * region->dx +
-+				(region->dy + y) * fb->fb.fix.line_length;
-+
-+			if (region->height - y < scanlines_per_cb)
-+				scanlines_per_cb = region->height - y;
-+
-+			set_dma_cb(cb, burst_size, scratchbuf, scanline_size,
-+				   src, fb->fb.fix.line_length,
-+				   scanline_size, scanlines_per_cb);
-+			control_block_pa += sizeof(struct bcm2708_dma_cb);
-+			cb->next = control_block_pa;
-+			cb++;
-+
-+			set_dma_cb(cb, burst_size, dst, fb->fb.fix.line_length,
-+				   scratchbuf, scanline_size,
-+				   scanline_size, scanlines_per_cb);
-+			control_block_pa += sizeof(struct bcm2708_dma_cb);
-+			cb->next = control_block_pa;
-+			cb++;
-+		}
-+		/* move the pointer back to the last dma control block */
-+		cb--;
-+	} else {
-+		/* A single dma control block is enough. */
-+		int sy, dy, stride;
-+		if (region->dy <= region->sy) {
-+			/* processing from top to bottom */
-+			dy = region->dy;
-+			sy = region->sy;
-+			stride = fb->fb.fix.line_length;
-+		} else {
-+			/* processing from bottom to top */
-+			dy = region->dy + region->height - 1;
-+			sy = region->sy + region->height - 1;
-+			stride = -fb->fb.fix.line_length;
-+		}
-+		set_dma_cb(cb, burst_size,
-+			   fb->fb_bus_address + dy * fb->fb.fix.line_length +
-+						   bytes_per_pixel * region->dx,
-+			   stride,
-+			   fb->fb_bus_address + sy * fb->fb.fix.line_length +
-+						   bytes_per_pixel * region->sx,
-+			   stride,
-+			   region->width * bytes_per_pixel,
-+			   region->height);
-+	}
-+
-+	/* end of dma control blocks chain */
-+	cb->next = 0;
-+
-+
-+	if (pixels < dma_busy_wait_threshold) {
-+		bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
-+		bcm_dma_wait_idle(fb->dma_chan_base);
-+	} else {
-+		void __iomem *dma_chan = fb->dma_chan_base;
-+		cb->info |= BCM2708_DMA_INT_EN;
-+		bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
-+		while (bcm_dma_is_busy(dma_chan)) {
-+			wait_event_interruptible(
-+				fb->dma_waitq,
-+				!bcm_dma_is_busy(dma_chan));
-+		}
-+		fb->stats.dma_irqs++;
-+	}
-+	fb->stats.dma_copies++;
-+}
-+
-+static void bcm2708_fb_imageblit(struct fb_info *info,
-+				 const struct fb_image *image)
-+{
-+	/* (is called) print_debug("bcm2708_fb_imageblit\n"); */
-+	cfb_imageblit(info, image);
-+}
-+
-+static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt)
-+{
-+	struct bcm2708_fb *fb = cxt;
-+
-+	/* FIXME: should read status register to check if this is
-+	 * actually interrupting us or not, in case this interrupt
-+	 * ever becomes shared amongst several DMA channels
-+	 *
-+	 * readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_IRQ;
-+	 */
-+
-+	/* acknowledge the interrupt */
-+	writel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS);
-+
-+	wake_up(&fb->dma_waitq);
-+	return IRQ_HANDLED;
-+}
-+
-+static struct fb_ops bcm2708_fb_ops = {
-+	.owner = THIS_MODULE,
-+	.fb_check_var = bcm2708_fb_check_var,
-+	.fb_set_par = bcm2708_fb_set_par,
-+	.fb_setcolreg = bcm2708_fb_setcolreg,
-+	.fb_blank = bcm2708_fb_blank,
-+	.fb_fillrect = bcm2708_fb_fillrect,
-+	.fb_copyarea = bcm2708_fb_copyarea,
-+	.fb_imageblit = bcm2708_fb_imageblit,
-+	.fb_pan_display = bcm2708_fb_pan_display,
-+	.fb_ioctl = bcm2708_ioctl,
-+};
-+
-+static int bcm2708_fb_register(struct bcm2708_fb *fb)
-+{
-+	int ret;
-+
-+	fb->fb.fbops = &bcm2708_fb_ops;
-+	fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA;
-+	fb->fb.pseudo_palette = fb->cmap;
-+
-+	strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id));
-+	fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
-+	fb->fb.fix.type_aux = 0;
-+	fb->fb.fix.xpanstep = 1;
-+	fb->fb.fix.ypanstep = 1;
-+	fb->fb.fix.ywrapstep = 0;
-+	fb->fb.fix.accel = FB_ACCEL_NONE;
-+
-+	fb->fb.var.xres = fbwidth;
-+	fb->fb.var.yres = fbheight;
-+	fb->fb.var.xres_virtual = fbwidth;
-+	fb->fb.var.yres_virtual = fbheight;
-+	fb->fb.var.bits_per_pixel = fbdepth;
-+	fb->fb.var.vmode = FB_VMODE_NONINTERLACED;
-+	fb->fb.var.activate = FB_ACTIVATE_NOW;
-+	fb->fb.var.nonstd = 0;
-+	fb->fb.var.height = -1;		/* height of picture in mm    */
-+	fb->fb.var.width = -1;		/* width of picture in mm    */
-+	fb->fb.var.accel_flags = 0;
-+
-+	fb->fb.monspecs.hfmin = 0;
-+	fb->fb.monspecs.hfmax = 100000;
-+	fb->fb.monspecs.vfmin = 0;
-+	fb->fb.monspecs.vfmax = 400;
-+	fb->fb.monspecs.dclkmin = 1000000;
-+	fb->fb.monspecs.dclkmax = 100000000;
-+
-+	bcm2708_fb_set_bitfields(&fb->fb.var);
-+	init_waitqueue_head(&fb->dma_waitq);
-+
-+	/*
-+	 * Allocate colourmap.
-+	 */
-+
-+	fb_set_var(&fb->fb, &fb->fb.var);
-+	ret = bcm2708_fb_set_par(&fb->fb);
-+	if (ret)
-+		return ret;
-+
-+	print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n", fbwidth,
-+		fbheight, fbdepth, fbswap);
-+
-+	ret = register_framebuffer(&fb->fb);
-+	print_debug("BCM2708FB: register framebuffer (%d)\n", ret);
-+	if (ret == 0)
-+		goto out;
-+
-+	print_debug("BCM2708FB: cannot register framebuffer (%d)\n", ret);
-+out:
-+	return ret;
-+}
-+
-+static int bcm2708_fb_probe(struct platform_device *dev)
-+{
-+	struct device_node *fw_np;
-+	struct rpi_firmware *fw;
-+	struct bcm2708_fb *fb;
-+	int ret;
-+
-+	fw_np = of_parse_phandle(dev->dev.of_node, "firmware", 0);
-+/* Remove comment when booting without Device Tree is no longer supported
-+	if (!fw_np) {
-+		dev_err(&dev->dev, "Missing firmware node\n");
-+		return -ENOENT;
-+	}
-+*/
-+	fw = rpi_firmware_get(fw_np);
-+	if (!fw)
-+		return -EPROBE_DEFER;
-+
-+	fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL);
-+	if (!fb) {
-+		dev_err(&dev->dev,
-+			"could not allocate new bcm2708_fb struct\n");
-+		ret = -ENOMEM;
-+		goto free_region;
-+	}
-+
-+	fb->fw = fw;
-+	bcm2708_fb_debugfs_init(fb);
-+
-+	fb->cb_base = dma_alloc_writecombine(&dev->dev, SZ_64K,
-+					     &fb->cb_handle, GFP_KERNEL);
-+	if (!fb->cb_base) {
-+		dev_err(&dev->dev, "cannot allocate DMA CBs\n");
-+		ret = -ENOMEM;
-+		goto free_fb;
-+	}
-+
-+	pr_info("BCM2708FB: allocated DMA memory %08x\n",
-+	       fb->cb_handle);
-+
-+	ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK,
-+				 &fb->dma_chan_base, &fb->dma_irq);
-+	if (ret < 0) {
-+		dev_err(&dev->dev, "couldn't allocate a DMA channel\n");
-+		goto free_cb;
-+	}
-+	fb->dma_chan = ret;
-+
-+	ret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq,
-+			  0, "bcm2708_fb dma", fb);
-+	if (ret) {
-+		pr_err("%s: failed to request DMA irq\n", __func__);
-+		goto free_dma_chan;
-+	}
-+
-+
-+	pr_info("BCM2708FB: allocated DMA channel %d @ %p\n",
-+	       fb->dma_chan, fb->dma_chan_base);
-+
-+	fb->dev = dev;
-+	fb->fb.device = &dev->dev;
-+
-+	ret = bcm2708_fb_register(fb);
-+	if (ret == 0) {
-+		platform_set_drvdata(dev, fb);
-+		goto out;
-+	}
-+
-+free_dma_chan:
-+	bcm_dma_chan_free(fb->dma_chan);
-+free_cb:
-+	dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);
-+free_fb:
-+	kfree(fb);
-+free_region:
-+	dev_err(&dev->dev, "probe failed, err %d\n", ret);
-+out:
-+	return ret;
-+}
-+
-+static int bcm2708_fb_remove(struct platform_device *dev)
-+{
-+	struct bcm2708_fb *fb = platform_get_drvdata(dev);
-+
-+	platform_set_drvdata(dev, NULL);
-+
-+	if (fb->fb.screen_base)
-+		iounmap(fb->fb.screen_base);
-+	unregister_framebuffer(&fb->fb);
-+
-+	dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);
-+	bcm_dma_chan_free(fb->dma_chan);
-+
-+	bcm2708_fb_debugfs_deinit(fb);
-+
-+	free_irq(fb->dma_irq, fb);
-+
-+	kfree(fb);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id bcm2708_fb_of_match_table[] = {
-+	{ .compatible = "brcm,bcm2708-fb", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, bcm2708_fb_of_match_table);
-+
-+static struct platform_driver bcm2708_fb_driver = {
-+	.probe = bcm2708_fb_probe,
-+	.remove = bcm2708_fb_remove,
-+	.driver = {
-+		   .name = DRIVER_NAME,
-+		   .owner = THIS_MODULE,
-+		   .of_match_table = bcm2708_fb_of_match_table,
-+		   },
-+};
-+
-+static int __init bcm2708_fb_init(void)
-+{
-+	return platform_driver_register(&bcm2708_fb_driver);
-+}
-+
-+module_init(bcm2708_fb_init);
-+
-+static void __exit bcm2708_fb_exit(void)
-+{
-+	platform_driver_unregister(&bcm2708_fb_driver);
-+}
-+
-+module_exit(bcm2708_fb_exit);
-+
-+module_param(fbwidth, int, 0644);
-+module_param(fbheight, int, 0644);
-+module_param(fbdepth, int, 0644);
-+module_param(fbswap, int, 0644);
-+
-+MODULE_DESCRIPTION("BCM2708 framebuffer driver");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer");
-+MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer");
-+MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer");
-+MODULE_PARM_DESC(fbswap, "Swap order of red and blue in 24 and 32 bit modes");
---- a/drivers/video/logo/logo_linux_clut224.ppm
-+++ b/drivers/video/logo/logo_linux_clut224.ppm
-@@ -1,1604 +1,883 @@
- P3
--# Standard 224-color Linux logo
--80 80
-+63 80
- 255
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  6   6   6   6   6   6  10  10  10  10  10  10
-- 10  10  10   6   6   6   6   6   6   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   6   6   6  10  10  10  14  14  14
-- 22  22  22  26  26  26  30  30  30  34  34  34
-- 30  30  30  30  30  30  26  26  26  18  18  18
-- 14  14  14  10  10  10   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  6   6   6  14  14  14  26  26  26  42  42  42
-- 54  54  54  66  66  66  78  78  78  78  78  78
-- 78  78  78  74  74  74  66  66  66  54  54  54
-- 42  42  42  26  26  26  18  18  18  10  10  10
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   1   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 22  22  22  42  42  42  66  66  66  86  86  86
-- 66  66  66  38  38  38  38  38  38  22  22  22
-- 26  26  26  34  34  34  54  54  54  66  66  66
-- 86  86  86  70  70  70  46  46  46  26  26  26
-- 14  14  14   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   1   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0  10  10  10  26  26  26
-- 50  50  50  82  82  82  58  58  58   6   6   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  6   6   6  54  54  54  86  86  86  66  66  66
-- 38  38  38  18  18  18   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   6   6   6  22  22  22  50  50  50
-- 78  78  78  34  34  34   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   6   6   6  70  70  70
-- 78  78  78  46  46  46  22  22  22   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   1   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  6   6   6  18  18  18  42  42  42  82  82  82
-- 26  26  26   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  14  14  14
-- 46  46  46  34  34  34   6   6   6   2   2   6
-- 42  42  42  78  78  78  42  42  42  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   1   0   0   0   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
-- 10  10  10  30  30  30  66  66  66  58  58  58
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  26  26  26
-- 86  86  86 101 101 101  46  46  46  10  10  10
--  2   2   6  58  58  58  70  70  70  34  34  34
-- 10  10  10   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   1   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
-- 14  14  14  42  42  42  86  86  86  10  10  10
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  30  30  30
-- 94  94  94  94  94  94  58  58  58  26  26  26
--  2   2   6   6   6   6  78  78  78  54  54  54
-- 22  22  22   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 22  22  22  62  62  62  62  62  62   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  26  26  26
-- 54  54  54  38  38  38  18  18  18  10  10  10
--  2   2   6   2   2   6  34  34  34  82  82  82
-- 38  38  38  14  14  14   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 30  30  30  78  78  78  30  30  30   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  10  10  10
-- 10  10  10   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  78  78  78
-- 50  50  50  18  18  18   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   1   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 38  38  38  86  86  86  14  14  14   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  54  54  54
-- 66  66  66  26  26  26   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 42  42  42  82  82  82   2   2   6   2   2   6
--  2   2   6   6   6   6  10  10  10   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   6   6   6
-- 14  14  14  10  10  10   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  18  18  18
-- 82  82  82  34  34  34  10  10  10   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   1   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 46  46  46  86  86  86   2   2   6   2   2   6
--  6   6   6   6   6   6  22  22  22  34  34  34
--  6   6   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6  18  18  18  34  34  34
-- 10  10  10  50  50  50  22  22  22   2   2   6
--  2   2   6   2   2   6   2   2   6  10  10  10
-- 86  86  86  42  42  42  14  14  14   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   1   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 46  46  46  86  86  86   2   2   6   2   2   6
-- 38  38  38 116 116 116  94  94  94  22  22  22
-- 22  22  22   2   2   6   2   2   6   2   2   6
-- 14  14  14  86  86  86 138 138 138 162 162 162
--154 154 154  38  38  38  26  26  26   6   6   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 86  86  86  46  46  46  14  14  14   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 46  46  46  86  86  86   2   2   6  14  14  14
--134 134 134 198 198 198 195 195 195 116 116 116
-- 10  10  10   2   2   6   2   2   6   6   6   6
--101  98  89 187 187 187 210 210 210 218 218 218
--214 214 214 134 134 134  14  14  14   6   6   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 86  86  86  50  50  50  18  18  18   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   1   0   0   0
--  0   0   1   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 46  46  46  86  86  86   2   2   6  54  54  54
--218 218 218 195 195 195 226 226 226 246 246 246
-- 58  58  58   2   2   6   2   2   6  30  30  30
--210 210 210 253 253 253 174 174 174 123 123 123
--221 221 221 234 234 234  74  74  74   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 70  70  70  58  58  58  22  22  22   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 46  46  46  82  82  82   2   2   6 106 106 106
--170 170 170  26  26  26  86  86  86 226 226 226
--123 123 123  10  10  10  14  14  14  46  46  46
--231 231 231 190 190 190   6   6   6  70  70  70
-- 90  90  90 238 238 238 158 158 158   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 70  70  70  58  58  58  22  22  22   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   1   0   0   0
--  0   0   1   0   0   1   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 42  42  42  86  86  86   6   6   6 116 116 116
--106 106 106   6   6   6  70  70  70 149 149 149
--128 128 128  18  18  18  38  38  38  54  54  54
--221 221 221 106 106 106   2   2   6  14  14  14
-- 46  46  46 190 190 190 198 198 198   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 74  74  74  62  62  62  22  22  22   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   1   0   0   0
--  0   0   1   0   0   0   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 42  42  42  94  94  94  14  14  14 101 101 101
--128 128 128   2   2   6  18  18  18 116 116 116
--118  98  46 121  92   8 121  92   8  98  78  10
--162 162 162 106 106 106   2   2   6   2   2   6
--  2   2   6 195 195 195 195 195 195   6   6   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 74  74  74  62  62  62  22  22  22   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   1   0   0   1
--  0   0   1   0   0   0   0   0   1   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 38  38  38  90  90  90  14  14  14  58  58  58
--210 210 210  26  26  26  54  38   6 154 114  10
--226 170  11 236 186  11 225 175  15 184 144  12
--215 174  15 175 146  61  37  26   9   2   2   6
-- 70  70  70 246 246 246 138 138 138   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 70  70  70  66  66  66  26  26  26   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 38  38  38  86  86  86  14  14  14  10  10  10
--195 195 195 188 164 115 192 133   9 225 175  15
--239 182  13 234 190  10 232 195  16 232 200  30
--245 207  45 241 208  19 232 195  16 184 144  12
--218 194 134 211 206 186  42  42  42   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 50  50  50  74  74  74  30  30  30   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 34  34  34  86  86  86  14  14  14   2   2   6
--121  87  25 192 133   9 219 162  10 239 182  13
--236 186  11 232 195  16 241 208  19 244 214  54
--246 218  60 246 218  38 246 215  20 241 208  19
--241 208  19 226 184  13 121  87  25   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 50  50  50  82  82  82  34  34  34  10  10  10
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 34  34  34  82  82  82  30  30  30  61  42   6
--180 123   7 206 145  10 230 174  11 239 182  13
--234 190  10 238 202  15 241 208  19 246 218  74
--246 218  38 246 215  20 246 215  20 246 215  20
--226 184  13 215 174  15 184 144  12   6   6   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 26  26  26  94  94  94  42  42  42  14  14  14
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 30  30  30  78  78  78  50  50  50 104  69   6
--192 133   9 216 158  10 236 178  12 236 186  11
--232 195  16 241 208  19 244 214  54 245 215  43
--246 215  20 246 215  20 241 208  19 198 155  10
--200 144  11 216 158  10 156 118  10   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  6   6   6  90  90  90  54  54  54  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 30  30  30  78  78  78  46  46  46  22  22  22
--137  92   6 210 162  10 239 182  13 238 190  10
--238 202  15 241 208  19 246 215  20 246 215  20
--241 208  19 203 166  17 185 133  11 210 150  10
--216 158  10 210 150  10 102  78  10   2   2   6
--  6   6   6  54  54  54  14  14  14   2   2   6
--  2   2   6  62  62  62  74  74  74  30  30  30
-- 10  10  10   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 34  34  34  78  78  78  50  50  50   6   6   6
-- 94  70  30 139 102  15 190 146  13 226 184  13
--232 200  30 232 195  16 215 174  15 190 146  13
--168 122  10 192 133   9 210 150  10 213 154  11
--202 150  34 182 157 106 101  98  89   2   2   6
--  2   2   6  78  78  78 116 116 116  58  58  58
--  2   2   6  22  22  22  90  90  90  46  46  46
-- 18  18  18   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 38  38  38  86  86  86  50  50  50   6   6   6
--128 128 128 174 154 114 156 107  11 168 122  10
--198 155  10 184 144  12 197 138  11 200 144  11
--206 145  10 206 145  10 197 138  11 188 164 115
--195 195 195 198 198 198 174 174 174  14  14  14
--  2   2   6  22  22  22 116 116 116 116 116 116
-- 22  22  22   2   2   6  74  74  74  70  70  70
-- 30  30  30  10  10  10   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  18  18  18
-- 50  50  50 101 101 101  26  26  26  10  10  10
--138 138 138 190 190 190 174 154 114 156 107  11
--197 138  11 200 144  11 197 138  11 192 133   9
--180 123   7 190 142  34 190 178 144 187 187 187
--202 202 202 221 221 221 214 214 214  66  66  66
--  2   2   6   2   2   6  50  50  50  62  62  62
--  6   6   6   2   2   6  10  10  10  90  90  90
-- 50  50  50  18  18  18   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0  10  10  10  34  34  34
-- 74  74  74  74  74  74   2   2   6   6   6   6
--144 144 144 198 198 198 190 190 190 178 166 146
--154 121  60 156 107  11 156 107  11 168 124  44
--174 154 114 187 187 187 190 190 190 210 210 210
--246 246 246 253 253 253 253 253 253 182 182 182
--  6   6   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  62  62  62
-- 74  74  74  34  34  34  14  14  14   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0  10  10  10  22  22  22  54  54  54
-- 94  94  94  18  18  18   2   2   6  46  46  46
--234 234 234 221 221 221 190 190 190 190 190 190
--190 190 190 187 187 187 187 187 187 190 190 190
--190 190 190 195 195 195 214 214 214 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
-- 82  82  82   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  14  14  14
-- 86  86  86  54  54  54  22  22  22   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  6   6   6  18  18  18  46  46  46  90  90  90
-- 46  46  46  18  18  18   6   6   6 182 182 182
--253 253 253 246 246 246 206 206 206 190 190 190
--190 190 190 190 190 190 190 190 190 190 190 190
--206 206 206 231 231 231 250 250 250 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--202 202 202  14  14  14   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 42  42  42  86  86  86  42  42  42  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 14  14  14  38  38  38  74  74  74  66  66  66
--  2   2   6   6   6   6  90  90  90 250 250 250
--253 253 253 253 253 253 238 238 238 198 198 198
--190 190 190 190 190 190 195 195 195 221 221 221
--246 246 246 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253  82  82  82   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6  78  78  78  70  70  70  34  34  34
-- 14  14  14   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 34  34  34  66  66  66  78  78  78   6   6   6
--  2   2   6  18  18  18 218 218 218 253 253 253
--253 253 253 253 253 253 253 253 253 246 246 246
--226 226 226 231 231 231 246 246 246 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 178 178 178   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6  18  18  18  90  90  90  62  62  62
-- 30  30  30  10  10  10   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0  10  10  10  26  26  26
-- 58  58  58  90  90  90  18  18  18   2   2   6
--  2   2   6 110 110 110 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 231 231 231  18  18  18   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6  18  18  18  94  94  94
-- 54  54  54  26  26  26  10  10  10   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   6   6   6  22  22  22  50  50  50
-- 90  90  90  26  26  26   2   2   6   2   2   6
-- 14  14  14 195 195 195 250 250 250 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--250 250 250 242 242 242  54  54  54   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6  38  38  38
-- 86  86  86  50  50  50  22  22  22   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  6   6   6  14  14  14  38  38  38  82  82  82
-- 34  34  34   2   2   6   2   2   6   2   2   6
-- 42  42  42 195 195 195 246 246 246 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--242 242 242 242 242 242 250 250 250 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 250 250 250 246 246 246 238 238 238
--226 226 226 231 231 231 101 101 101   6   6   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 38  38  38  82  82  82  42  42  42  14  14  14
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
-- 10  10  10  26  26  26  62  62  62  66  66  66
--  2   2   6   2   2   6   2   2   6   6   6   6
-- 70  70  70 170 170 170 206 206 206 234 234 234
--246 246 246 250 250 250 250 250 250 238 238 238
--226 226 226 231 231 231 238 238 238 250 250 250
--250 250 250 250 250 250 246 246 246 231 231 231
--214 214 214 206 206 206 202 202 202 202 202 202
--198 198 198 202 202 202 182 182 182  18  18  18
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6  62  62  62  66  66  66  30  30  30
-- 10  10  10   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
-- 14  14  14  42  42  42  82  82  82  18  18  18
--  2   2   6   2   2   6   2   2   6  10  10  10
-- 94  94  94 182 182 182 218 218 218 242 242 242
--250 250 250 253 253 253 253 253 253 250 250 250
--234 234 234 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 246 246 246
--238 238 238 226 226 226 210 210 210 202 202 202
--195 195 195 195 195 195 210 210 210 158 158 158
--  6   6   6  14  14  14  50  50  50  14  14  14
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   6   6   6  86  86  86  46  46  46
-- 18  18  18   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 22  22  22  54  54  54  70  70  70   2   2   6
--  2   2   6  10  10  10   2   2   6  22  22  22
--166 166 166 231 231 231 250 250 250 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--242 242 242 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 246 246 246
--231 231 231 206 206 206 198 198 198 226 226 226
-- 94  94  94   2   2   6   6   6   6  38  38  38
-- 30  30  30   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6  62  62  62  66  66  66
-- 26  26  26  10  10  10   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 30  30  30  74  74  74  50  50  50   2   2   6
-- 26  26  26  26  26  26   2   2   6 106 106 106
--238 238 238 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 246 246 246 218 218 218 202 202 202
--210 210 210  14  14  14   2   2   6   2   2   6
-- 30  30  30  22  22  22   2   2   6   2   2   6
--  2   2   6   2   2   6  18  18  18  86  86  86
-- 42  42  42  14  14  14   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 42  42  42  90  90  90  22  22  22   2   2   6
-- 42  42  42   2   2   6  18  18  18 218 218 218
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 250 250 250 221 221 221
--218 218 218 101 101 101   2   2   6  14  14  14
-- 18  18  18  38  38  38  10  10  10   2   2   6
--  2   2   6   2   2   6   2   2   6  78  78  78
-- 58  58  58  22  22  22   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  18  18  18
-- 54  54  54  82  82  82   2   2   6  26  26  26
-- 22  22  22   2   2   6 123 123 123 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--238 238 238 198 198 198   6   6   6  38  38  38
-- 58  58  58  26  26  26  38  38  38   2   2   6
--  2   2   6   2   2   6   2   2   6  46  46  46
-- 78  78  78  30  30  30  10  10  10   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0  10  10  10  30  30  30
-- 74  74  74  58  58  58   2   2   6  42  42  42
--  2   2   6  22  22  22 231 231 231 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 246 246 246  46  46  46  38  38  38
-- 42  42  42  14  14  14  38  38  38  14  14  14
--  2   2   6   2   2   6   2   2   6   6   6   6
-- 86  86  86  46  46  46  14  14  14   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   6   6   6  14  14  14  42  42  42
-- 90  90  90  18  18  18  18  18  18  26  26  26
--  2   2   6 116 116 116 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 250 250 250 238 238 238
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253  94  94  94   6   6   6
--  2   2   6   2   2   6  10  10  10  34  34  34
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 74  74  74  58  58  58  22  22  22   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0  10  10  10  26  26  26  66  66  66
-- 82  82  82   2   2   6  38  38  38   6   6   6
-- 14  14  14 210 210 210 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 246 246 246 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 144 144 144   2   2   6
--  2   2   6   2   2   6   2   2   6  46  46  46
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 42  42  42  74  74  74  30  30  30  10  10  10
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  6   6   6  14  14  14  42  42  42  90  90  90
-- 26  26  26   6   6   6  42  42  42   2   2   6
-- 74  74  74 250 250 250 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 242 242 242 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 182 182 182   2   2   6
--  2   2   6   2   2   6   2   2   6  46  46  46
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 10  10  10  86  86  86  38  38  38  10  10  10
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
-- 10  10  10  26  26  26  66  66  66  82  82  82
--  2   2   6  22  22  22  18  18  18   2   2   6
--149 149 149 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 206 206 206   2   2   6
--  2   2   6   2   2   6   2   2   6  38  38  38
--  2   2   6   2   2   6   2   2   6   2   2   6
--  6   6   6  86  86  86  46  46  46  14  14  14
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 18  18  18  46  46  46  86  86  86  18  18  18
--  2   2   6  34  34  34  10  10  10   6   6   6
--210 210 210 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 221 221 221   6   6   6
--  2   2   6   2   2   6   6   6   6  30  30  30
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6  82  82  82  54  54  54  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 26  26  26  66  66  66  62  62  62   2   2   6
--  2   2   6  38  38  38  10  10  10  26  26  26
--238 238 238 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 238 238 238
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231   6   6   6
--  2   2   6   2   2   6  10  10  10  30  30  30
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6  66  66  66  58  58  58  22  22  22
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 38  38  38  78  78  78   6   6   6   2   2   6
--  2   2   6  46  46  46  14  14  14  42  42  42
--246 246 246 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234  10  10  10
--  2   2   6   2   2   6  22  22  22  14  14  14
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6  66  66  66  62  62  62  22  22  22
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  18  18  18
-- 50  50  50  74  74  74   2   2   6   2   2   6
-- 14  14  14  70  70  70  34  34  34  62  62  62
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234  14  14  14
--  2   2   6   2   2   6  30  30  30   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6  66  66  66  62  62  62  22  22  22
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  18  18  18
-- 54  54  54  62  62  62   2   2   6   2   2   6
--  2   2   6  30  30  30  46  46  46  70  70  70
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 226 226 226  10  10  10
--  2   2   6   6   6   6  30  30  30   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6  66  66  66  58  58  58  22  22  22
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  22  22  22
-- 58  58  58  62  62  62   2   2   6   2   2   6
--  2   2   6   2   2   6  30  30  30  78  78  78
--250 250 250 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 206 206 206   2   2   6
-- 22  22  22  34  34  34  18  14   6  22  22  22
-- 26  26  26  18  18  18   6   6   6   2   2   6
--  2   2   6  82  82  82  54  54  54  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  26  26  26
-- 62  62  62 106 106 106  74  54  14 185 133  11
--210 162  10 121  92   8   6   6   6  62  62  62
--238 238 238 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 246 246 246
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 158 158 158  18  18  18
-- 14  14  14   2   2   6   2   2   6   2   2   6
--  6   6   6  18  18  18  66  66  66  38  38  38
--  6   6   6  94  94  94  50  50  50  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 10  10  10  10  10  10  18  18  18  38  38  38
-- 78  78  78 142 134 106 216 158  10 242 186  14
--246 190  14 246 190  14 156 118  10  10  10  10
-- 90  90  90 238 238 238 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 246 230 190
--238 204  91 238 204  91 181 142  44  37  26   9
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6  38  38  38  46  46  46
-- 26  26  26 106 106 106  54  54  54  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   6   6   6  14  14  14  22  22  22
-- 30  30  30  38  38  38  50  50  50  70  70  70
--106 106 106 190 142  34 226 170  11 242 186  14
--246 190  14 246 190  14 246 190  14 154 114  10
--  6   6   6  74  74  74 226 226 226 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 231 231 231 250 250 250
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 228 184  62
--241 196  14 241 208  19 232 195  16  38  30  10
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   6   6   6  30  30  30  26  26  26
--203 166  17 154 142  90  66  66  66  26  26  26
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  6   6   6  18  18  18  38  38  38  58  58  58
-- 78  78  78  86  86  86 101 101 101 123 123 123
--175 146  61 210 150  10 234 174  13 246 186  14
--246 190  14 246 190  14 246 190  14 238 190  10
--102  78  10   2   2   6  46  46  46 198 198 198
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 234 234 234 242 242 242
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 224 178  62
--242 186  14 241 196  14 210 166  10  22  18   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   6   6   6 121  92   8
--238 202  15 232 195  16  82  82  82  34  34  34
-- 10  10  10   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
-- 14  14  14  38  38  38  70  70  70 154 122  46
--190 142  34 200 144  11 197 138  11 197 138  11
--213 154  11 226 170  11 242 186  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--225 175  15  46  32   6   2   2   6  22  22  22
--158 158 158 250 250 250 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 250 250 250 242 242 242 224 178  62
--239 182  13 236 186  11 213 154  11  46  32   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6  61  42   6 225 175  15
--238 190  10 236 186  11 112 100  78  42  42  42
-- 14  14  14   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 22  22  22  54  54  54 154 122  46 213 154  11
--226 170  11 230 174  11 226 170  11 226 170  11
--236 178  12 242 186  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--241 196  14 184 144  12  10  10  10   2   2   6
--  6   6   6 116 116 116 242 242 242 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 231 231 231 198 198 198 214 170  54
--236 178  12 236 178  12 210 150  10 137  92   6
-- 18  14   6   2   2   6   2   2   6   2   2   6
--  6   6   6  70  47   6 200 144  11 236 178  12
--239 182  13 239 182  13 124 112  88  58  58  58
-- 22  22  22   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 30  30  30  70  70  70 180 133  36 226 170  11
--239 182  13 242 186  14 242 186  14 246 186  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 232 195  16  98  70   6   2   2   6
--  2   2   6   2   2   6  66  66  66 221 221 221
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 206 206 206 198 198 198 214 166  58
--230 174  11 230 174  11 216 158  10 192 133   9
--163 110   8 116  81   8 102  78  10 116  81   8
--167 114   7 197 138  11 226 170  11 239 182  13
--242 186  14 242 186  14 162 146  94  78  78  78
-- 34  34  34  14  14  14   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 30  30  30  78  78  78 190 142  34 226 170  11
--239 182  13 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 241 196  14 203 166  17  22  18   6
--  2   2   6   2   2   6   2   2   6  38  38  38
--218 218 218 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--250 250 250 206 206 206 198 198 198 202 162  69
--226 170  11 236 178  12 224 166  10 210 150  10
--200 144  11 197 138  11 192 133   9 197 138  11
--210 150  10 226 170  11 242 186  14 246 190  14
--246 190  14 246 186  14 225 175  15 124 112  88
-- 62  62  62  30  30  30  14  14  14   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 30  30  30  78  78  78 174 135  50 224 166  10
--239 182  13 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 241 196  14 139 102  15
--  2   2   6   2   2   6   2   2   6   2   2   6
-- 78  78  78 250 250 250 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--250 250 250 214 214 214 198 198 198 190 150  46
--219 162  10 236 178  12 234 174  13 224 166  10
--216 158  10 213 154  11 213 154  11 216 158  10
--226 170  11 239 182  13 246 190  14 246 190  14
--246 190  14 246 190  14 242 186  14 206 162  42
--101 101 101  58  58  58  30  30  30  14  14  14
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 30  30  30  74  74  74 174 135  50 216 158  10
--236 178  12 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 241 196  14 226 184  13
-- 61  42   6   2   2   6   2   2   6   2   2   6
-- 22  22  22 238 238 238 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 226 226 226 187 187 187 180 133  36
--216 158  10 236 178  12 239 182  13 236 178  12
--230 174  11 226 170  11 226 170  11 230 174  11
--236 178  12 242 186  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 186  14 239 182  13
--206 162  42 106 106 106  66  66  66  34  34  34
-- 14  14  14   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 26  26  26  70  70  70 163 133  67 213 154  11
--236 178  12 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 241 196  14
--190 146  13  18  14   6   2   2   6   2   2   6
-- 46  46  46 246 246 246 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 221 221 221  86  86  86 156 107  11
--216 158  10 236 178  12 242 186  14 246 186  14
--242 186  14 239 182  13 239 182  13 242 186  14
--242 186  14 246 186  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--242 186  14 225 175  15 142 122  72  66  66  66
-- 30  30  30  10  10  10   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 26  26  26  70  70  70 163 133  67 210 150  10
--236 178  12 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--232 195  16 121  92   8  34  34  34 106 106 106
--221 221 221 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--242 242 242  82  82  82  18  14   6 163 110   8
--216 158  10 236 178  12 242 186  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 242 186  14 163 133  67
-- 46  46  46  18  18  18   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  10  10  10
-- 30  30  30  78  78  78 163 133  67 210 150  10
--236 178  12 246 186  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--241 196  14 215 174  15 190 178 144 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 218 218 218
-- 58  58  58   2   2   6  22  18   6 167 114   7
--216 158  10 236 178  12 246 186  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 186  14 242 186  14 190 150  46
-- 54  54  54  22  22  22   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 38  38  38  86  86  86 180 133  36 213 154  11
--236 178  12 246 186  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 232 195  16 190 146  13 214 214 214
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 250 250 250 170 170 170  26  26  26
--  2   2   6   2   2   6  37  26   9 163 110   8
--219 162  10 239 182  13 246 186  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 186  14 236 178  12 224 166  10 142 122  72
-- 46  46  46  18  18  18   6   6   6   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  18  18  18
-- 50  50  50 109 106  95 192 133   9 224 166  10
--242 186  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--242 186  14 226 184  13 210 162  10 142 110  46
--226 226 226 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--253 253 253 253 253 253 253 253 253 253 253 253
--198 198 198  66  66  66   2   2   6   2   2   6
--  2   2   6   2   2   6  50  34   6 156 107  11
--219 162  10 239 182  13 246 186  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 242 186  14
--234 174  13 213 154  11 154 122  46  66  66  66
-- 30  30  30  10  10  10   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  22  22  22
-- 58  58  58 154 121  60 206 145  10 234 174  13
--242 186  14 246 186  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 186  14 236 178  12 210 162  10 163 110   8
-- 61  42   6 138 138 138 218 218 218 250 250 250
--253 253 253 253 253 253 253 253 253 250 250 250
--242 242 242 210 210 210 144 144 144  66  66  66
--  6   6   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6  61  42   6 163 110   8
--216 158  10 236 178  12 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 239 182  13 230 174  11 216 158  10
--190 142  34 124 112  88  70  70  70  38  38  38
-- 18  18  18   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  22  22  22
-- 62  62  62 168 124  44 206 145  10 224 166  10
--236 178  12 239 182  13 242 186  14 242 186  14
--246 186  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 236 178  12 216 158  10 175 118   6
-- 80  54   7   2   2   6   6   6   6  30  30  30
-- 54  54  54  62  62  62  50  50  50  38  38  38
-- 14  14  14   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   6   6   6  80  54   7 167 114   7
--213 154  11 236 178  12 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 190  14 242 186  14 239 182  13 239 182  13
--230 174  11 210 150  10 174 135  50 124 112  88
-- 82  82  82  54  54  54  34  34  34  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  18  18  18
-- 50  50  50 158 118  36 192 133   9 200 144  11
--216 158  10 219 162  10 224 166  10 226 170  11
--230 174  11 236 178  12 239 182  13 239 182  13
--242 186  14 246 186  14 246 190  14 246 190  14
--246 190  14 246 190  14 246 190  14 246 190  14
--246 186  14 230 174  11 210 150  10 163 110   8
--104  69   6  10  10  10   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   6   6   6  91  60   6 167 114   7
--206 145  10 230 174  11 242 186  14 246 190  14
--246 190  14 246 190  14 246 186  14 242 186  14
--239 182  13 230 174  11 224 166  10 213 154  11
--180 133  36 124 112  88  86  86  86  58  58  58
-- 38  38  38  22  22  22  10  10  10   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0  14  14  14
-- 34  34  34  70  70  70 138 110  50 158 118  36
--167 114   7 180 123   7 192 133   9 197 138  11
--200 144  11 206 145  10 213 154  11 219 162  10
--224 166  10 230 174  11 239 182  13 242 186  14
--246 186  14 246 186  14 246 186  14 246 186  14
--239 182  13 216 158  10 185 133  11 152  99   6
--104  69   6  18  14   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   2   2   6   2   2   6   2   2   6
--  2   2   6   6   6   6  80  54   7 152  99   6
--192 133   9 219 162  10 236 178  12 239 182  13
--246 186  14 242 186  14 239 182  13 236 178  12
--224 166  10 206 145  10 192 133   9 154 121  60
-- 94  94  94  62  62  62  42  42  42  22  22  22
-- 14  14  14   6   6   6   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   6   6   6
-- 18  18  18  34  34  34  58  58  58  78  78  78
--101  98  89 124 112  88 142 110  46 156 107  11
--163 110   8 167 114   7 175 118   6 180 123   7
--185 133  11 197 138  11 210 150  10 219 162  10
--226 170  11 236 178  12 236 178  12 234 174  13
--219 162  10 197 138  11 163 110   8 130  83   6
-- 91  60   6  10  10  10   2   2   6   2   2   6
-- 18  18  18  38  38  38  38  38  38  38  38  38
-- 38  38  38  38  38  38  38  38  38  38  38  38
-- 38  38  38  38  38  38  26  26  26   2   2   6
--  2   2   6   6   6   6  70  47   6 137  92   6
--175 118   6 200 144  11 219 162  10 230 174  11
--234 174  13 230 174  11 219 162  10 210 150  10
--192 133   9 163 110   8 124 112  88  82  82  82
-- 50  50  50  30  30  30  14  14  14   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  6   6   6  14  14  14  22  22  22  34  34  34
-- 42  42  42  58  58  58  74  74  74  86  86  86
--101  98  89 122 102  70 130  98  46 121  87  25
--137  92   6 152  99   6 163 110   8 180 123   7
--185 133  11 197 138  11 206 145  10 200 144  11
--180 123   7 156 107  11 130  83   6 104  69   6
-- 50  34   6  54  54  54 110 110 110 101  98  89
-- 86  86  86  82  82  82  78  78  78  78  78  78
-- 78  78  78  78  78  78  78  78  78  78  78  78
-- 78  78  78  82  82  82  86  86  86  94  94  94
--106 106 106 101 101 101  86  66  34 124  80   6
--156 107  11 180 123   7 192 133   9 200 144  11
--206 145  10 200 144  11 192 133   9 175 118   6
--139 102  15 109 106  95  70  70  70  42  42  42
-- 22  22  22  10  10  10   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   6   6   6  10  10  10
-- 14  14  14  22  22  22  30  30  30  38  38  38
-- 50  50  50  62  62  62  74  74  74  90  90  90
--101  98  89 112 100  78 121  87  25 124  80   6
--137  92   6 152  99   6 152  99   6 152  99   6
--138  86   6 124  80   6  98  70   6  86  66  30
--101  98  89  82  82  82  58  58  58  46  46  46
-- 38  38  38  34  34  34  34  34  34  34  34  34
-- 34  34  34  34  34  34  34  34  34  34  34  34
-- 34  34  34  34  34  34  38  38  38  42  42  42
-- 54  54  54  82  82  82  94  86  76  91  60   6
--134  86   6 156 107  11 167 114   7 175 118   6
--175 118   6 167 114   7 152  99   6 121  87  25
--101  98  89  62  62  62  34  34  34  18  18  18
--  6   6   6   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   6   6   6   6   6   6  10  10  10
-- 18  18  18  22  22  22  30  30  30  42  42  42
-- 50  50  50  66  66  66  86  86  86 101  98  89
--106  86  58  98  70   6 104  69   6 104  69   6
--104  69   6  91  60   6  82  62  34  90  90  90
-- 62  62  62  38  38  38  22  22  22  14  14  14
-- 10  10  10  10  10  10  10  10  10  10  10  10
-- 10  10  10  10  10  10   6   6   6  10  10  10
-- 10  10  10  10  10  10  10  10  10  14  14  14
-- 22  22  22  42  42  42  70  70  70  89  81  66
-- 80  54   7 104  69   6 124  80   6 137  92   6
--134  86   6 116  81   8 100  82  52  86  86  86
-- 58  58  58  30  30  30  14  14  14   6   6   6
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   0   0   0   0   0   0   0   0   0
--  0   0   0   6   6   6  10  10  10  14  14  14
-- 18  18  18  26  26  26  38  38  38  54  54  54
-- 70  70  70  86  86  86  94  86  76  89  81  66
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diff --git a/target/linux/brcm2708/patches-4.14/950-0039-dmaengine-Add-support-for-BCM2708.patch b/target/linux/brcm2708/patches-4.14/950-0039-dmaengine-Add-support-for-BCM2708.patch
deleted file mode 100644
index 2c6373ac2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0039-dmaengine-Add-support-for-BCM2708.patch
+++ /dev/null
@@ -1,623 +0,0 @@
-From e0dcf539876b6da0763bd87d0f072a0197c97ee1 Mon Sep 17 00:00:00 2001
-From: Florian Meier <florian.meier@koalo.de>
-Date: Fri, 22 Nov 2013 14:22:53 +0100
-Subject: [PATCH 039/454] dmaengine: Add support for BCM2708
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
-Currently it only supports cyclic DMA.
-
-Signed-off-by: Florian Meier <florian.meier@koalo.de>
-
-dmaengine: expand functionality by supporting scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels
-
-DMA: fix cyclic LITE length overflow bug
-
-dmaengine: bcm2708: Remove chancnt affectations
-
-Mirror bcm2835-dma.c commit 9eba5536a7434c69d8c185d4bd1c70734d92287d:
-chancnt is already filled by dma_async_device_register, which uses the channel
-list to know how much channels there is.
-
-Since it's already filled, we can safely remove it from the drivers' probe
-function.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dmaengine: bcm2708: overwrite dreq only if it is not set
-
-dreq is set when the DMA channel is fetched from Device Tree.
-slave_id is set using dmaengine_slave_config().
-Only overwrite dreq with slave_id if it is not set.
-
-dreq/slave_id in the cyclic DMA case is not touched, because I don't
-have hardware to test with.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dmaengine: bcm2708: do device registration in the board file
-
-Don't register the device in the driver. Do it in the board file.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dmaengine: bcm2708: don't restrict DT support to ARCH_BCM2835
-
-Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now.
-Add Device Tree support to the non ARCH_BCM2835 case.
-Use the same driver name regardless of architecture.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-BCM270x_DT: add bcm2835-dma entry
-
-Add Device Tree entry for bcm2835-dma.
-The entry doesn't contain any resources since they are handled
-by the arch/arm/mach-bcm270x/dma.c driver.
-In non-DT mode, don't add the device in the board file.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-bcm2708-dmaengine: Add debug options
-
-BCM270x: Add memory and irq resources to dmaengine device and DT
-
-Prepare for merging of the legacy DMA API arch driver dma.c
-with bcm2708-dmaengine by adding memory and irq resources both
-to platform file device and Device Tree node.
-Don't use BCM_DMAMAN_DRIVER_NAME so we don't have to include mach/dma.h
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dmaengine: bcm2708: Merge with arch dma.c driver and disable dma.c
-
-Merge the legacy DMA API driver with bcm2708-dmaengine.
-This is done so we can use bcm2708_fb on ARCH_BCM2835 (mailbox
-driver is also needed).
-
-Changes to the dma.c code:
-- Use BIT() macro.
-- Cutdown some comments to one line.
-- Add mutex to vc_dmaman and use this, since the dev lock is locked
-  during probing of the engine part.
-- Add global g_dmaman variable since drvdata is used by the engine part.
-- Restructure for readability:
-  vc_dmaman_chan_alloc()
-  vc_dmaman_chan_free()
-  bcm_dma_chan_free()
-- Restructure bcm_dma_chan_alloc() to simplify error handling.
-- Use device irq resources instead of hardcoded bcm_dma_irqs table.
-- Remove dev_dmaman_register() and code it directly.
-- Remove dev_dmaman_deregister() and code it directly.
-- Simplify bcm_dmaman_probe() using devm_* functions.
-- Get dmachans from DT if available.
-- Keep 'dma.dmachans' module argument name for backwards compatibility.
-
-Make it available on ARCH_BCM2835 as well.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dmaengine: bcm2708: set residue_granularity field
-
-bcm2708-dmaengine supports residue reporting at burst level
-but didn't report this via the residue_granularity field.
-
-Without this field set properly we get playback issues with I2S cards.
-
-dmaengine: bcm2708-dmaengine: Fix memory leak when stopping a running transfer
-
-bcm2708-dmaengine: Use more DMA channels (but not 12)
-
-1) Only the bcm2708_fb drivers uses the legacy DMA API, and
-it requires a BULK-capable channel, so all other types
-(FAST, NORMAL and LITE) can be made available to the regular
-DMA API.
-
-2) DMA channels 11-14 share an interrupt. The driver can't
-handle this, so don't use channels 12-14 (12 was used, probably
-because it appears to have an interrupt, but in reality that
-interrupt is for activity on ANY channel). This may explain
-a lockup encountered when running out of DMA channels.
-
-The combined effect of this patch is to leave 7 DMA channels
-available + channel 0 for bcm2708_fb via the legacy API.
-
-See: https://github.com/raspberrypi/linux/issues/1110
-     https://github.com/raspberrypi/linux/issues/1108
-
-dmaengine: bcm2708: Make legacy API available for bcm2835-dma
-
-bcm2708_fb uses the legacy DMA API, so in order to start using
-bcm2835-dma, bcm2835-dma has to support the legacy API. Make this
-possible by exporting bcm_dmaman_probe() and bcm_dmaman_remove().
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dmaengine: bcm2708: Change DT compatible string
-
-Both bcm2835-dma and bcm2708-dmaengine have the same compatible string.
-So change compatible to "brcm,bcm2708-dma".
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-dmaengine: bcm2708: Remove driver but keep legacy API
-
-Dropping non-DT support means we don't need this driver,
-but we still need the legacy DMA API.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-bcm2708-dmaengine - Fix arm64 portability/build issues
----
- drivers/dma/Kconfig                       |   6 +-
- drivers/dma/Makefile                      |   1 +
- drivers/dma/bcm2708-dmaengine.c           | 281 ++++++++++++++++++++++
- include/linux/platform_data/dma-bcm2708.h | 143 +++++++++++
- 4 files changed, 430 insertions(+), 1 deletion(-)
- create mode 100644 drivers/dma/bcm2708-dmaengine.c
- create mode 100644 include/linux/platform_data/dma-bcm2708.h
-
---- a/drivers/dma/Kconfig
-+++ b/drivers/dma/Kconfig
-@@ -131,7 +131,7 @@ config COH901318
- 
- config DMA_BCM2835
- 	tristate "BCM2835 DMA engine support"
--	depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
-+	depends on ARCH_BCM2835
- 	select DMA_ENGINE
- 	select DMA_VIRTUAL_CHANNELS
- 
-@@ -535,6 +535,10 @@ config TIMB_DMA
- 	help
- 	  Enable support for the Timberdale FPGA DMA engine.
- 
-+config DMA_BCM2708
-+	tristate "BCM2708 DMA legacy API support"
-+	depends on DMA_BCM2835
-+
- config TI_CPPI41
- 	tristate "CPPI 4.1 DMA support"
- 	depends on (ARCH_OMAP || ARCH_DAVINCI_DA8XX)
---- a/drivers/dma/Makefile
-+++ b/drivers/dma/Makefile
-@@ -21,6 +21,7 @@ obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
- obj-$(CONFIG_AXI_DMAC) += dma-axi-dmac.o
- obj-$(CONFIG_BCM_SBA_RAID) += bcm-sba-raid.o
- obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
-+obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
- obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
- obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
- obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o
---- /dev/null
-+++ b/drivers/dma/bcm2708-dmaengine.c
-@@ -0,0 +1,281 @@
-+/*
-+ * BCM2708 legacy DMA API
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/platform_data/dma-bcm2708.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/spinlock.h>
-+
-+#include "virt-dma.h"
-+
-+#define CACHE_LINE_MASK 31
-+#define DEFAULT_DMACHAN_BITMAP 0x10  /* channel 4 only */
-+
-+/* valid only for channels 0 - 14, 15 has its own base address */
-+#define BCM2708_DMA_CHAN(n)	((n) << 8) /* base address */
-+#define BCM2708_DMA_CHANIO(dma_base, n) \
-+	((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n)))
-+
-+struct vc_dmaman {
-+	void __iomem *dma_base;
-+	u32 chan_available; /* bitmap of available channels */
-+	u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
-+	struct mutex lock;
-+};
-+
-+static struct device *dmaman_dev;	/* we assume there's only one! */
-+static struct vc_dmaman *g_dmaman;	/* DMA manager */
-+
-+/* DMA Auxiliary Functions */
-+
-+/* A DMA buffer on an arbitrary boundary may separate a cache line into a
-+   section inside the DMA buffer and another section outside it.
-+   Even if we flush DMA buffers from the cache there is always the chance that
-+   during a DMA someone will access the part of a cache line that is outside
-+   the DMA buffer - which will then bring in unwelcome data.
-+   Without being able to dictate our own buffer pools we must insist that
-+   DMA buffers consist of a whole number of cache lines.
-+*/
-+extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
-+{
-+	int i;
-+
-+	for (i = 0; i < sg_len; i++) {
-+		if (sg_ptr[i].offset & CACHE_LINE_MASK ||
-+		    sg_ptr[i].length & CACHE_LINE_MASK)
-+			return 0;
-+	}
-+
-+	return 1;
-+}
-+EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
-+
-+extern void bcm_dma_start(void __iomem *dma_chan_base,
-+			  dma_addr_t control_block)
-+{
-+	dsb(sy);	/* ARM data synchronization (push) operation */
-+
-+	writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
-+	writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_start);
-+
-+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
-+{
-+	dsb(sy);
-+
-+	/* ugly busy wait only option for now */
-+	while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
-+		cpu_relax();
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_wait_idle);
-+
-+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
-+{
-+	dsb(sy);
-+
-+	return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
-+
-+/* Complete an ongoing DMA (assuming its results are to be ignored)
-+   Does nothing if there is no DMA in progress.
-+   This routine waits for the current AXI transfer to complete before
-+   terminating the current DMA. If the current transfer is hung on a DREQ used
-+   by an uncooperative peripheral the AXI transfer may never complete.	In this
-+   case the routine times out and return a non-zero error code.
-+   Use of this routine doesn't guarantee that the ongoing or aborted DMA
-+   does not produce an interrupt.
-+*/
-+extern int bcm_dma_abort(void __iomem *dma_chan_base)
-+{
-+	unsigned long int cs;
-+	int rc = 0;
-+
-+	cs = readl(dma_chan_base + BCM2708_DMA_CS);
-+
-+	if (BCM2708_DMA_ACTIVE & cs) {
-+		long int timeout = 10000;
-+
-+		/* write 0 to the active bit - pause the DMA */
-+		writel(0, dma_chan_base + BCM2708_DMA_CS);
-+
-+		/* wait for any current AXI transfer to complete */
-+		while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
-+			cs = readl(dma_chan_base + BCM2708_DMA_CS);
-+
-+		if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
-+			/* we'll un-pause when we set of our next DMA */
-+			rc = -ETIMEDOUT;
-+
-+		} else if (BCM2708_DMA_ACTIVE & cs) {
-+			/* terminate the control block chain */
-+			writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
-+
-+			/* abort the whole DMA */
-+			writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
-+			       dma_chan_base + BCM2708_DMA_CS);
-+		}
-+	}
-+
-+	return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_abort);
-+
-+ /* DMA Manager Device Methods */
-+
-+static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
-+			   u32 chans_available)
-+{
-+	dmaman->dma_base = dma_base;
-+	dmaman->chan_available = chans_available;
-+	dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c;  /* 2 & 3 */
-+	dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01;  /* 0 */
-+	dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe;  /* 1 to 7 */
-+	dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00;  /* 8 to 14 */
-+}
-+
-+static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
-+				unsigned required_feature_set)
-+{
-+	u32 chans;
-+	int chan = 0;
-+	int feature;
-+
-+	chans = dmaman->chan_available;
-+	for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
-+		/* select the subset of available channels with the desired
-+		   features */
-+		if (required_feature_set & (1 << feature))
-+			chans &= dmaman->has_feature[feature];
-+
-+	if (!chans)
-+		return -ENOENT;
-+
-+	/* return the ordinal of the first channel in the bitmap */
-+	while (chans != 0 && (chans & 1) == 0) {
-+		chans >>= 1;
-+		chan++;
-+	}
-+	/* claim the channel */
-+	dmaman->chan_available &= ~(1 << chan);
-+
-+	return chan;
-+}
-+
-+static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
-+{
-+	if (chan < 0)
-+		return -EINVAL;
-+
-+	if ((1 << chan) & dmaman->chan_available)
-+		return -EIDRM;
-+
-+	dmaman->chan_available |= (1 << chan);
-+
-+	return 0;
-+}
-+
-+/* DMA Manager Monitor */
-+
-+extern int bcm_dma_chan_alloc(unsigned required_feature_set,
-+			      void __iomem **out_dma_base, int *out_dma_irq)
-+{
-+	struct vc_dmaman *dmaman = g_dmaman;
-+	struct platform_device *pdev = to_platform_device(dmaman_dev);
-+	struct resource *r;
-+	int chan;
-+
-+	if (!dmaman_dev)
-+		return -ENODEV;
-+
-+	mutex_lock(&dmaman->lock);
-+	chan = vc_dmaman_chan_alloc(dmaman, required_feature_set);
-+	if (chan < 0)
-+		goto out;
-+
-+	r = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan);
-+	if (!r) {
-+		dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n",
-+			chan);
-+		vc_dmaman_chan_free(dmaman, chan);
-+		chan = -ENOENT;
-+		goto out;
-+	}
-+
-+	*out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan);
-+	*out_dma_irq = r->start;
-+	dev_dbg(dmaman_dev,
-+		"Legacy API allocated channel=%d, base=%p, irq=%i\n",
-+		chan, *out_dma_base, *out_dma_irq);
-+
-+out:
-+	mutex_unlock(&dmaman->lock);
-+
-+	return chan;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
-+
-+extern int bcm_dma_chan_free(int channel)
-+{
-+	struct vc_dmaman *dmaman = g_dmaman;
-+	int rc;
-+
-+	if (!dmaman_dev)
-+		return -ENODEV;
-+
-+	mutex_lock(&dmaman->lock);
-+	rc = vc_dmaman_chan_free(dmaman, channel);
-+	mutex_unlock(&dmaman->lock);
-+
-+	return rc;
-+}
-+EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
-+
-+int bcm_dmaman_probe(struct platform_device *pdev, void __iomem *base,
-+		     u32 chans_available)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct vc_dmaman *dmaman;
-+
-+	dmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL);
-+	if (!dmaman)
-+		return -ENOMEM;
-+
-+	mutex_init(&dmaman->lock);
-+	vc_dmaman_init(dmaman, base, chans_available);
-+	g_dmaman = dmaman;
-+	dmaman_dev = dev;
-+
-+	dev_info(dev, "DMA legacy API manager at %p, dmachans=0x%x\n",
-+		 base, chans_available);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(bcm_dmaman_probe);
-+
-+int bcm_dmaman_remove(struct platform_device *pdev)
-+{
-+	dmaman_dev = NULL;
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(bcm_dmaman_remove);
-+
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/include/linux/platform_data/dma-bcm2708.h
-@@ -0,0 +1,143 @@
-+/*
-+ *  Copyright (C) 2010 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#ifndef _PLAT_BCM2708_DMA_H
-+#define _PLAT_BCM2708_DMA_H
-+
-+/* DMA CS Control and Status bits */
-+#define BCM2708_DMA_ACTIVE	BIT(0)
-+#define BCM2708_DMA_INT		BIT(2)
-+#define BCM2708_DMA_ISPAUSED	BIT(4)  /* Pause requested or not active */
-+#define BCM2708_DMA_ISHELD	BIT(5)  /* Is held by DREQ flow control */
-+#define BCM2708_DMA_ERR		BIT(8)
-+#define BCM2708_DMA_ABORT	BIT(30) /* stop current CB, go to next, WO */
-+#define BCM2708_DMA_RESET	BIT(31) /* WO, self clearing */
-+
-+/* DMA control block "info" field bits */
-+#define BCM2708_DMA_INT_EN	BIT(0)
-+#define BCM2708_DMA_TDMODE	BIT(1)
-+#define BCM2708_DMA_WAIT_RESP	BIT(3)
-+#define BCM2708_DMA_D_INC	BIT(4)
-+#define BCM2708_DMA_D_WIDTH	BIT(5)
-+#define BCM2708_DMA_D_DREQ	BIT(6)
-+#define BCM2708_DMA_S_INC	BIT(8)
-+#define BCM2708_DMA_S_WIDTH	BIT(9)
-+#define BCM2708_DMA_S_DREQ	BIT(10)
-+
-+#define	BCM2708_DMA_BURST(x)	(((x) & 0xf) << 12)
-+#define	BCM2708_DMA_PER_MAP(x)	((x) << 16)
-+#define	BCM2708_DMA_WAITS(x)	(((x) & 0x1f) << 21)
-+
-+#define BCM2708_DMA_DREQ_EMMC	11
-+#define BCM2708_DMA_DREQ_SDHOST	13
-+
-+#define BCM2708_DMA_CS		0x00 /* Control and Status */
-+#define BCM2708_DMA_ADDR	0x04
-+/* the current control block appears in the following registers - read only */
-+#define BCM2708_DMA_INFO	0x08
-+#define BCM2708_DMA_SOURCE_AD	0x0c
-+#define BCM2708_DMA_DEST_AD	0x10
-+#define BCM2708_DMA_NEXTCB	0x1C
-+#define BCM2708_DMA_DEBUG	0x20
-+
-+#define BCM2708_DMA4_CS		(BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS)
-+#define BCM2708_DMA4_ADDR	(BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR)
-+
-+#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
-+
-+/* When listing features we can ask for when allocating DMA channels give
-+   those with higher priority smaller ordinal numbers */
-+#define BCM_DMA_FEATURE_FAST_ORD	0
-+#define BCM_DMA_FEATURE_BULK_ORD	1
-+#define BCM_DMA_FEATURE_NORMAL_ORD	2
-+#define BCM_DMA_FEATURE_LITE_ORD	3
-+#define BCM_DMA_FEATURE_FAST		BIT(BCM_DMA_FEATURE_FAST_ORD)
-+#define BCM_DMA_FEATURE_BULK		BIT(BCM_DMA_FEATURE_BULK_ORD)
-+#define BCM_DMA_FEATURE_NORMAL		BIT(BCM_DMA_FEATURE_NORMAL_ORD)
-+#define BCM_DMA_FEATURE_LITE		BIT(BCM_DMA_FEATURE_LITE_ORD)
-+#define BCM_DMA_FEATURE_COUNT		4
-+
-+struct bcm2708_dma_cb {
-+	u32 info;
-+	u32 src;
-+	u32 dst;
-+	u32 length;
-+	u32 stride;
-+	u32 next;
-+	u32 pad[2];
-+};
-+
-+struct scatterlist;
-+struct platform_device;
-+
-+#ifdef CONFIG_DMA_BCM2708
-+
-+int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
-+void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block);
-+void bcm_dma_wait_idle(void __iomem *dma_chan_base);
-+bool bcm_dma_is_busy(void __iomem *dma_chan_base);
-+int bcm_dma_abort(void __iomem *dma_chan_base);
-+
-+/* return channel no or -ve error */
-+int bcm_dma_chan_alloc(unsigned preferred_feature_set,
-+		       void __iomem **out_dma_base, int *out_dma_irq);
-+int bcm_dma_chan_free(int channel);
-+
-+int bcm_dmaman_probe(struct platform_device *pdev, void __iomem *base,
-+		     u32 chans_available);
-+int bcm_dmaman_remove(struct platform_device *pdev);
-+
-+#else /* CONFIG_DMA_BCM2708 */
-+
-+static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr,
-+					  int sg_len)
-+{
-+	return 0;
-+}
-+
-+static inline void bcm_dma_start(void __iomem *dma_chan_base,
-+				 dma_addr_t control_block) { }
-+
-+static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { }
-+
-+static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base)
-+{
-+	return false;
-+}
-+
-+static inline int bcm_dma_abort(void __iomem *dma_chan_base)
-+{
-+	return -EINVAL;
-+}
-+
-+static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set,
-+				     void __iomem **out_dma_base,
-+				     int *out_dma_irq)
-+{
-+	return -EINVAL;
-+}
-+
-+static inline int bcm_dma_chan_free(int channel)
-+{
-+	return -EINVAL;
-+}
-+
-+static inline int bcm_dmaman_probe(struct platform_device *pdev,
-+				   void __iomem *base, u32 chans_available)
-+{
-+	return 0;
-+}
-+
-+static inline int bcm_dmaman_remove(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+
-+#endif /* CONFIG_DMA_BCM2708 */
-+
-+#endif /* _PLAT_BCM2708_DMA_H */
diff --git a/target/linux/brcm2708/patches-4.14/950-0040-MMC-added-alternative-MMC-driver.patch b/target/linux/brcm2708/patches-4.14/950-0040-MMC-added-alternative-MMC-driver.patch
deleted file mode 100644
index f10a1d3c7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0040-MMC-added-alternative-MMC-driver.patch
+++ /dev/null
@@ -1,1865 +0,0 @@
-From e567a7eb59832a76c36cf531967a56d3ff906584 Mon Sep 17 00:00:00 2001
-From: gellert <gellert@raspberrypi.org>
-Date: Fri, 15 Aug 2014 16:35:06 +0100
-Subject: [PATCH 040/454] MMC: added alternative MMC driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-mmc: Disable CMD23 transfers on all cards
-
-Pending wire-level investigation of these types of transfers
-and associated errors on bcm2835-mmc, disable for now. Fallback of
-CMD18/CMD25 transfers will be used automatically by the MMC layer.
-
-Reported/Tested-by: Gellert Weisz <gellert@raspberrypi.org>
-
-mmc: bcm2835-mmc: enable DT support for all architectures
-
-Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now.
-Enable Device Tree support for all architectures.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-mmc: bcm2835-mmc: fix probe error handling
-
-Probe error handling is broken in several places.
-Simplify error handling by using device managed functions.
-Replace pr_{err,info} with dev_{err,info}.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-bcm2835-mmc: Add locks when accessing sdhost registers
-
-bcm2835-mmc: Add range of debug options for slowing things down
-
-bcm2835-mmc: Add option to disable some delays
-
-bcm2835-mmc: Add option to disable MMC_QUIRK_BLK_NO_CMD23
-
-bcm2835-mmc: Default to disabling MMC_QUIRK_BLK_NO_CMD23
-
-bcm2835-mmc: Adding overclocking option
-
-Allow a different clock speed to be substitued for a requested 50MHz.
-This option is exposed using the "overclock_50" DT parameter.
-Note that the mmc interface is restricted to EVEN integer divisions of
-250MHz, and the highest sensible option is 63 (250/4 = 62.5), the
-next being 125 (250/2) which is much too high.
-
-Use at your own risk.
-
-bcm2835-mmc: Round up the overclock, so 62 works for 62.5Mhz
-
-Also only warn once for each overclock setting.
-
-mmc: bcm2835-mmc: Make available on ARCH_BCM2835
-
-Make the bcm2835-mmc driver available for use on ARCH_BCM2835.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-BCM270x_DT: add bcm2835-mmc entry
-
-Add Device Tree entry for bcm2835-mmc.
-In non-DT mode, don't add the device in the board file.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-bcm2835-mmc: Don't overwrite MMC capabilities from DT
-
-bcm2835-mmc: Don't override bus width capabilities from devicetree
-
-Take out the force setting of the MMC_CAP_4_BIT_DATA host capability
-so that the result read from devicetree via mmc_of_parse() is
-preserved.
-
-bcm2835-mmc: Only claim one DMA channel
-
-With both MMC controllers enabled there are few DMA channels left. The
-bcm2835-mmc driver only uses DMA in one direction at a time, so it
-doesn't need to claim two channels.
-
-See: https://github.com/raspberrypi/linux/issues/1327
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/mmc/core/block.c       |   28 +-
- drivers/mmc/core/core.c        |    3 +-
- drivers/mmc/core/host.c        |   17 +-
- drivers/mmc/core/quirks.h      |    8 +
- drivers/mmc/host/Kconfig       |   29 +
- drivers/mmc/host/Makefile      |    1 +
- drivers/mmc/host/bcm2835-mmc.c | 1584 ++++++++++++++++++++++++++++++++
- include/linux/mmc/card.h       |    2 +
- 8 files changed, 1667 insertions(+), 5 deletions(-)
- create mode 100644 drivers/mmc/host/bcm2835-mmc.c
-
---- a/drivers/mmc/core/block.c
-+++ b/drivers/mmc/core/block.c
-@@ -131,6 +131,13 @@ static DEFINE_MUTEX(open_lock);
- module_param(perdev_minors, int, 0444);
- MODULE_PARM_DESC(perdev_minors, "Minors numbers to allocate per device");
- 
-+/*
-+ * Allow quirks to be overridden for the current card
-+ */
-+static char *card_quirks;
-+module_param(card_quirks, charp, 0644);
-+MODULE_PARM_DESC(card_quirks, "Force the use of the indicated quirks (a bitfield)");
-+
- static inline int mmc_blk_part_switch(struct mmc_card *card,
- 				      unsigned int part_type);
- 
-@@ -2514,6 +2521,7 @@ static int mmc_blk_probe(struct mmc_card
- {
- 	struct mmc_blk_data *md, *part_md;
- 	char cap_str[10];
-+	char quirk_str[24];
- 
- 	/*
- 	 * Check that the card supports the command class(es) we need.
-@@ -2521,7 +2529,16 @@ static int mmc_blk_probe(struct mmc_card
- 	if (!(card->csd.cmdclass & CCC_BLOCK_READ))
- 		return -ENODEV;
- 
--	mmc_fixup_device(card, mmc_blk_fixups);
-+	if (card_quirks) {
-+		unsigned long quirks;
-+		if (kstrtoul(card_quirks, 0, &quirks) == 0)
-+			card->quirks = (unsigned int)quirks;
-+		else
-+			pr_err("mmc_block: Invalid card_quirks parameter '%s'\n",
-+			       card_quirks);
-+	}
-+	else
-+		mmc_fixup_device(card, mmc_blk_fixups);
- 
- 	md = mmc_blk_alloc(card);
- 	if (IS_ERR(md))
-@@ -2529,9 +2546,14 @@ static int mmc_blk_probe(struct mmc_card
- 
- 	string_get_size((u64)get_capacity(md->disk), 512, STRING_UNITS_2,
- 			cap_str, sizeof(cap_str));
--	pr_info("%s: %s %s %s %s\n",
-+	if (card->quirks)
-+		snprintf(quirk_str, sizeof(quirk_str),
-+			 " (quirks 0x%08x)", card->quirks);
-+	else
-+		quirk_str[0] = '\0';
-+	pr_info("%s: %s %s %s%s%s\n",
- 		md->disk->disk_name, mmc_card_id(card), mmc_card_name(card),
--		cap_str, md->read_only ? "(ro)" : "");
-+		cap_str, md->read_only ? " (ro)" : "", quirk_str);
- 
- 	if (mmc_blk_alloc_parts(card, md))
- 		goto out;
---- a/drivers/mmc/core/core.c
-+++ b/drivers/mmc/core/core.c
-@@ -2210,7 +2210,8 @@ EXPORT_SYMBOL(mmc_erase);
- int mmc_can_erase(struct mmc_card *card)
- {
- 	if ((card->host->caps & MMC_CAP_ERASE) &&
--	    (card->csd.cmdclass & CCC_ERASE) && card->erase_size)
-+	    (card->csd.cmdclass & CCC_ERASE) && card->erase_size &&
-+	    !(card->quirks & MMC_QUIRK_ERASE_BROKEN))
- 		return 1;
- 	return 0;
- }
---- a/drivers/mmc/core/host.c
-+++ b/drivers/mmc/core/host.c
-@@ -350,15 +350,30 @@ struct mmc_host *mmc_alloc_host(int extr
- {
- 	int err;
- 	struct mmc_host *host;
-+	int id;
- 
- 	host = kzalloc(sizeof(struct mmc_host) + extra, GFP_KERNEL);
- 	if (!host)
- 		return NULL;
- 
-+	/* If OF aliases exist, start dynamic assignment after highest */
-+	id = of_alias_get_highest_id("mmc");
-+	id = (id < 0) ? 0 : id + 1;
-+
-+	/* If this devices has OF node, maybe it has an alias */
-+	if (dev->of_node) {
-+		int of_id = of_alias_get_id(dev->of_node, "mmc");
-+
-+		if (of_id < 0)
-+			dev_warn(dev, "/aliases ID not available\n");
-+		else
-+			id = of_id;
-+	}
-+
- 	/* scanning will be enabled when we're ready */
- 	host->rescan_disable = 1;
- 
--	err = ida_simple_get(&mmc_host_ida, 0, 0, GFP_KERNEL);
-+	err = ida_simple_get(&mmc_host_ida, id, 0, GFP_KERNEL);
- 	if (err < 0) {
- 		kfree(host);
- 		return NULL;
---- a/drivers/mmc/core/quirks.h
-+++ b/drivers/mmc/core/quirks.h
-@@ -99,6 +99,14 @@ static const struct mmc_fixup mmc_blk_fi
- 	MMC_FIXUP("V10016", CID_MANFID_KINGSTON, CID_OEMID_ANY, add_quirk_mmc,
- 		  MMC_QUIRK_TRIM_BROKEN),
- 
-+	/*
-+	 *  On some Kingston SD cards, multiple erases of less than 64
-+	 *  sectors can cause corruption.
-+	 */
-+	MMC_FIXUP("SD16G", 0x41, 0x3432, add_quirk, MMC_QUIRK_ERASE_BROKEN),
-+	MMC_FIXUP("SD32G", 0x41, 0x3432, add_quirk, MMC_QUIRK_ERASE_BROKEN),
-+	MMC_FIXUP("SD64G", 0x41, 0x3432, add_quirk, MMC_QUIRK_ERASE_BROKEN),
-+
- 	END_FIXUP
- };
- 
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -4,6 +4,35 @@
- 
- comment "MMC/SD/SDIO Host Controller Drivers"
- 
-+config MMC_BCM2835_MMC
-+	tristate "MMC support on BCM2835"
-+	depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
-+	help
-+	  This selects the MMC Interface on BCM2835.
-+
-+	  If you have a controller with this interface, say Y or M here.
-+
-+	  If unsure, say N.
-+
-+config MMC_BCM2835_DMA
-+	bool "DMA support on BCM2835 Arasan controller"
-+	depends on MMC_BCM2835_MMC
-+	help
-+	  Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
-+	  based chips.
-+
-+	  If unsure, say N.
-+
-+config MMC_BCM2835_PIO_DMA_BARRIER
-+	int "Block count limit for PIO transfers"
-+	depends on MMC_BCM2835_MMC && MMC_BCM2835_DMA
-+	range 0 256
-+	default 2
-+	help
-+	  The inclusive limit in bytes under which PIO will be used instead of DMA
-+
-+	  If unsure, say 2 here.
-+
- config MMC_DEBUG
- 	bool "MMC host drivers debugging"
- 	depends on MMC != n
---- a/drivers/mmc/host/Makefile
-+++ b/drivers/mmc/host/Makefile
-@@ -20,6 +20,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C)	+= sdhci-s3c
- obj-$(CONFIG_MMC_SDHCI_SIRF)   	+= sdhci-sirf.o
- obj-$(CONFIG_MMC_SDHCI_F_SDH30)	+= sdhci_f_sdh30.o
- obj-$(CONFIG_MMC_SDHCI_SPEAR)	+= sdhci-spear.o
-+obj-$(CONFIG_MMC_BCM2835_MMC)	+= bcm2835-mmc.o
- obj-$(CONFIG_MMC_WBSD)		+= wbsd.o
- obj-$(CONFIG_MMC_AU1X)		+= au1xmmc.o
- obj-$(CONFIG_MMC_MTK)		+= mtk-sd.o
---- /dev/null
-+++ b/drivers/mmc/host/bcm2835-mmc.c
-@@ -0,0 +1,1584 @@
-+/*
-+ * BCM2835 MMC host driver.
-+ *
-+ * Author:      Gellert Weisz <gellert@raspberrypi.org>
-+ *              Copyright 2014
-+ *
-+ * Based on
-+ *  sdhci-bcm2708.c by Broadcom
-+ *  sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
-+ *  sdhci.c and sdhci-pci.c by Pierre Ossman
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/mmc/mmc.h>
-+#include <linux/mmc/host.h>
-+#include <linux/mmc/sd.h>
-+#include <linux/scatterlist.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/err.h>
-+#include <linux/blkdev.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/of_dma.h>
-+
-+#include "sdhci.h"
-+
-+
-+#define DRIVER_NAME "mmc-bcm2835"
-+
-+#define DBG(f, x...) \
-+pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
-+
-+#ifndef CONFIG_MMC_BCM2835_DMA
-+ #define FORCE_PIO
-+#endif
-+
-+
-+/* the inclusive limit in bytes under which PIO will be used instead of DMA */
-+#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
-+#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
-+#else
-+#define PIO_DMA_BARRIER 00
-+#endif
-+
-+#define MIN_FREQ 400000
-+#define TIMEOUT_VAL 0xE
-+#define BCM2835_SDHCI_WRITE_DELAY(f)	(((2 * 1000000) / f) + 1)
-+
-+
-+unsigned mmc_debug;
-+unsigned mmc_debug2;
-+
-+struct bcm2835_host {
-+	spinlock_t				lock;
-+
-+	void __iomem			*ioaddr;
-+	u32						bus_addr;
-+
-+	struct mmc_host			*mmc;
-+
-+	u32						timeout;
-+
-+	int						clock;	/* Current clock speed */
-+	u8						pwr;	/* Current voltage */
-+
-+	unsigned int			max_clk;		/* Max possible freq */
-+	unsigned int			timeout_clk;	/* Timeout freq (KHz) */
-+	unsigned int			clk_mul;		/* Clock Muliplier value */
-+
-+	struct tasklet_struct	finish_tasklet;		/* Tasklet structures */
-+
-+	struct timer_list		timer;			/* Timer for timeouts */
-+
-+	struct sg_mapping_iter	sg_miter;		/* SG state for PIO */
-+	unsigned int			blocks;			/* remaining PIO blocks */
-+
-+	int						irq;			/* Device IRQ */
-+
-+
-+	u32						ier;			/* cached registers */
-+
-+	struct mmc_request		*mrq;			/* Current request */
-+	struct mmc_command		*cmd;			/* Current command */
-+	struct mmc_data			*data;			/* Current data request */
-+	unsigned int			data_early:1;		/* Data finished before cmd */
-+
-+	wait_queue_head_t		buf_ready_int;		/* Waitqueue for Buffer Read Ready interrupt */
-+
-+	u32						thread_isr;
-+
-+	u32						shadow;
-+
-+	/*DMA part*/
-+	struct dma_chan			*dma_chan_rxtx;		/* DMA channel for reads and writes */
-+	struct dma_slave_config		dma_cfg_rx;
-+	struct dma_slave_config		dma_cfg_tx;
-+	struct dma_async_tx_descriptor	*tx_desc;	/* descriptor */
-+
-+	bool					have_dma;
-+	bool					use_dma;
-+	bool					wait_for_dma;
-+	/*end of DMA part*/
-+
-+	int						max_delay;	/* maximum length of time spent waiting */
-+
-+	int						flags;				/* Host attributes */
-+#define SDHCI_REQ_USE_DMA	(1<<2)	/* Use DMA for this req. */
-+#define SDHCI_DEVICE_DEAD	(1<<3)	/* Device unresponsive */
-+#define SDHCI_AUTO_CMD12	(1<<6)	/* Auto CMD12 support */
-+#define SDHCI_AUTO_CMD23	(1<<7)	/* Auto CMD23 support */
-+#define SDHCI_SDIO_IRQ_ENABLED	(1<<9)	/* SDIO irq enabled */
-+
-+	u32				overclock_50;	/* frequency to use when 50MHz is requested (in MHz) */
-+	u32				max_overclock;	/* Highest reported */
-+};
-+
-+
-+static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from)
-+{
-+	unsigned delay;
-+	lockdep_assert_held_once(&host->lock);
-+	writel(val, host->ioaddr + reg);
-+	udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ)));
-+
-+	delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf);
-+	if (delay && !((1<<from) & mmc_debug2))
-+		udelay(delay);
-+}
-+
-+static inline void mmc_raw_writel(struct bcm2835_host *host, u32 val, int reg)
-+{
-+	unsigned delay;
-+	lockdep_assert_held_once(&host->lock);
-+	writel(val, host->ioaddr + reg);
-+
-+	delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf);
-+	if (delay)
-+		udelay(delay);
-+}
-+
-+static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg)
-+{
-+	lockdep_assert_held_once(&host->lock);
-+	return readl(host->ioaddr + reg);
-+}
-+
-+static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg)
-+{
-+	u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow :
-+		bcm2835_mmc_readl(host, reg & ~3);
-+	u32 word_num = (reg >> 1) & 1;
-+	u32 word_shift = word_num * 16;
-+	u32 mask = 0xffff << word_shift;
-+	u32 newval = (oldval & ~mask) | (val << word_shift);
-+
-+	if (reg == SDHCI_TRANSFER_MODE)
-+		host->shadow = newval;
-+	else
-+		bcm2835_mmc_writel(host, newval, reg & ~3, 0);
-+
-+}
-+
-+static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg)
-+{
-+	u32 oldval = bcm2835_mmc_readl(host, reg & ~3);
-+	u32 byte_num = reg & 3;
-+	u32 byte_shift = byte_num * 8;
-+	u32 mask = 0xff << byte_shift;
-+	u32 newval = (oldval & ~mask) | (val << byte_shift);
-+
-+	bcm2835_mmc_writel(host, newval, reg & ~3, 1);
-+}
-+
-+
-+static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg)
-+{
-+	u32 val = bcm2835_mmc_readl(host, (reg & ~3));
-+	u32 word_num = (reg >> 1) & 1;
-+	u32 word_shift = word_num * 16;
-+	u32 word = (val >> word_shift) & 0xffff;
-+
-+	return word;
-+}
-+
-+static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg)
-+{
-+	u32 val = bcm2835_mmc_readl(host, (reg & ~3));
-+	u32 byte_num = reg & 3;
-+	u32 byte_shift = byte_num * 8;
-+	u32 byte = (val >> byte_shift) & 0xff;
-+
-+	return byte;
-+}
-+
-+static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear)
-+{
-+	u32 ier;
-+
-+	ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE);
-+	ier &= ~clear;
-+	/* change which requests generate IRQs - makes no difference to
-+	   the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
-+	bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2);
-+}
-+
-+
-+static void bcm2835_mmc_dumpregs(struct bcm2835_host *host)
-+{
-+	pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
-+		mmc_hostname(host->mmc));
-+
-+	pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
-+		bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS),
-+		bcm2835_mmc_readw(host, SDHCI_HOST_VERSION));
-+	pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
-+		bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE),
-+		bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT));
-+	pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
-+		bcm2835_mmc_readl(host, SDHCI_ARGUMENT),
-+		bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE));
-+	pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
-+		bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE),
-+		bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL));
-+	pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
-+		bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL),
-+		bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL));
-+	pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
-+		bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL),
-+		bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL));
-+	pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
-+		bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL),
-+		bcm2835_mmc_readl(host, SDHCI_INT_STATUS));
-+	pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
-+		bcm2835_mmc_readl(host, SDHCI_INT_ENABLE),
-+		bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE));
-+	pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
-+		bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR),
-+		bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS));
-+	pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
-+		bcm2835_mmc_readl(host, SDHCI_CAPABILITIES),
-+		bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1));
-+	pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
-+		bcm2835_mmc_readw(host, SDHCI_COMMAND),
-+		bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT));
-+	pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
-+		bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2));
-+
-+	pr_debug(DRIVER_NAME ": ===========================================\n");
-+}
-+
-+
-+static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask)
-+{
-+	unsigned long timeout;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+	bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
-+
-+	if (mask & SDHCI_RESET_ALL)
-+		host->clock = 0;
-+
-+	/* Wait max 100 ms */
-+	timeout = 100;
-+
-+	/* hw clears the bit when it's done */
-+	while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
-+		if (timeout == 0) {
-+			pr_err("%s: Reset 0x%x never completed.\n",
-+				mmc_hostname(host->mmc), (int)mask);
-+			bcm2835_mmc_dumpregs(host);
-+			return;
-+		}
-+		timeout--;
-+		spin_unlock_irqrestore(&host->lock, flags);
-+		mdelay(1);
-+		spin_lock_irqsave(&host->lock, flags);
-+	}
-+
-+	if (100-timeout > 10 && 100-timeout > host->max_delay) {
-+		host->max_delay = 100-timeout;
-+		pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+	}
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
-+
-+static void bcm2835_mmc_init(struct bcm2835_host *host, int soft)
-+{
-+	unsigned long flags;
-+	if (soft)
-+		bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
-+	else
-+		bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+	host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
-+		    SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
-+		    SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
-+		    SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
-+		    SDHCI_INT_RESPONSE;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+	bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3);
-+	bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3);
-+	spin_unlock_irqrestore(&host->lock, flags);
-+
-+	if (soft) {
-+		/* force clock reconfiguration */
-+		host->clock = 0;
-+		bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios);
-+	}
-+}
-+
-+
-+
-+static void bcm2835_mmc_finish_data(struct bcm2835_host *host);
-+
-+static void bcm2835_mmc_dma_complete(void *param)
-+{
-+	struct bcm2835_host *host = param;
-+	struct dma_chan *dma_chan;
-+	unsigned long flags;
-+	u32 dir_data;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	host->use_dma = false;
-+
-+	if (host->data && !(host->data->flags & MMC_DATA_WRITE)) {
-+		/* otherwise handled in SDHCI IRQ */
-+		dma_chan = host->dma_chan_rxtx;
-+		dir_data = DMA_FROM_DEVICE;
-+
-+		dma_unmap_sg(dma_chan->device->dev,
-+		     host->data->sg, host->data->sg_len,
-+		     dir_data);
-+
-+		bcm2835_mmc_finish_data(host);
-+	} else if (host->wait_for_dma) {
-+		host->wait_for_dma = false;
-+		tasklet_schedule(&host->finish_tasklet);
-+	}
-+
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host)
-+{
-+	unsigned long flags;
-+	size_t blksize, len, chunk;
-+
-+	u32 uninitialized_var(scratch);
-+	u8 *buf;
-+
-+	blksize = host->data->blksz;
-+	chunk = 0;
-+
-+	local_irq_save(flags);
-+
-+	while (blksize) {
-+		if (!sg_miter_next(&host->sg_miter))
-+			BUG();
-+
-+		len = min(host->sg_miter.length, blksize);
-+
-+		blksize -= len;
-+		host->sg_miter.consumed = len;
-+
-+		buf = host->sg_miter.addr;
-+
-+		while (len) {
-+			if (chunk == 0) {
-+				scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER);
-+				chunk = 4;
-+			}
-+
-+			*buf = scratch & 0xFF;
-+
-+			buf++;
-+			scratch >>= 8;
-+			chunk--;
-+			len--;
-+		}
-+	}
-+
-+	sg_miter_stop(&host->sg_miter);
-+
-+	local_irq_restore(flags);
-+}
-+
-+static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host)
-+{
-+	unsigned long flags;
-+	size_t blksize, len, chunk;
-+	u32 scratch;
-+	u8 *buf;
-+
-+	blksize = host->data->blksz;
-+	chunk = 0;
-+	chunk = 0;
-+	scratch = 0;
-+
-+	local_irq_save(flags);
-+
-+	while (blksize) {
-+		if (!sg_miter_next(&host->sg_miter))
-+			BUG();
-+
-+		len = min(host->sg_miter.length, blksize);
-+
-+		blksize -= len;
-+		host->sg_miter.consumed = len;
-+
-+		buf = host->sg_miter.addr;
-+
-+		while (len) {
-+			scratch |= (u32)*buf << (chunk * 8);
-+
-+			buf++;
-+			chunk++;
-+			len--;
-+
-+			if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
-+				mmc_raw_writel(host, scratch, SDHCI_BUFFER);
-+				chunk = 0;
-+				scratch = 0;
-+			}
-+		}
-+	}
-+
-+	sg_miter_stop(&host->sg_miter);
-+
-+	local_irq_restore(flags);
-+}
-+
-+
-+static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host)
-+{
-+	u32 mask;
-+
-+	BUG_ON(!host->data);
-+
-+	if (host->blocks == 0)
-+		return;
-+
-+	if (host->data->flags & MMC_DATA_READ)
-+		mask = SDHCI_DATA_AVAILABLE;
-+	else
-+		mask = SDHCI_SPACE_AVAILABLE;
-+
-+	while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
-+
-+		if (host->data->flags & MMC_DATA_READ)
-+			bcm2835_bcm2835_mmc_read_block_pio(host);
-+		else
-+			bcm2835_bcm2835_mmc_write_block_pio(host);
-+
-+		host->blocks--;
-+
-+		/* QUIRK used in sdhci.c removes the 'if' */
-+		/* but it seems this is unnecessary */
-+		if (host->blocks == 0)
-+			break;
-+
-+
-+	}
-+}
-+
-+
-+static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host)
-+{
-+	u32 len, dir_data, dir_slave;
-+	struct dma_async_tx_descriptor *desc = NULL;
-+	struct dma_chan *dma_chan;
-+
-+
-+	WARN_ON(!host->data);
-+
-+	if (!host->data)
-+		return;
-+
-+	if (host->blocks == 0)
-+		return;
-+
-+	dma_chan = host->dma_chan_rxtx;
-+	if (host->data->flags & MMC_DATA_READ) {
-+		dir_data = DMA_FROM_DEVICE;
-+		dir_slave = DMA_DEV_TO_MEM;
-+	} else {
-+		dir_data = DMA_TO_DEVICE;
-+		dir_slave = DMA_MEM_TO_DEV;
-+	}
-+
-+	/* The parameters have already been validated, so this will not fail */
-+	(void)dmaengine_slave_config(dma_chan,
-+				     (dir_data == DMA_FROM_DEVICE) ?
-+				     &host->dma_cfg_rx :
-+				     &host->dma_cfg_tx);
-+
-+	BUG_ON(!dma_chan->device);
-+	BUG_ON(!dma_chan->device->dev);
-+	BUG_ON(!host->data->sg);
-+
-+	len = dma_map_sg(dma_chan->device->dev, host->data->sg,
-+			 host->data->sg_len, dir_data);
-+	if (len > 0) {
-+		desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
-+					       len, dir_slave,
-+					       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+	} else {
-+		dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
-+	}
-+	if (desc) {
-+		unsigned long flags;
-+		spin_lock_irqsave(&host->lock, flags);
-+		bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
-+						    SDHCI_INT_SPACE_AVAIL);
-+		host->tx_desc = desc;
-+		desc->callback = bcm2835_mmc_dma_complete;
-+		desc->callback_param = host;
-+		spin_unlock_irqrestore(&host->lock, flags);
-+		dmaengine_submit(desc);
-+		dma_async_issue_pending(dma_chan);
-+	}
-+
-+}
-+
-+
-+
-+static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host)
-+{
-+	u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
-+	u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
-+
-+	if (host->use_dma)
-+		host->ier = (host->ier & ~pio_irqs) | dma_irqs;
-+	else
-+		host->ier = (host->ier & ~dma_irqs) | pio_irqs;
-+
-+	bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4);
-+	bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4);
-+}
-+
-+
-+static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+	u8 count;
-+	struct mmc_data *data = cmd->data;
-+
-+	WARN_ON(host->data);
-+
-+	if (data || (cmd->flags & MMC_RSP_BUSY)) {
-+		count = TIMEOUT_VAL;
-+		bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
-+	}
-+
-+	if (!data)
-+		return;
-+
-+	/* Sanity checks */
-+	BUG_ON(data->blksz * data->blocks > 524288);
-+	BUG_ON(data->blksz > host->mmc->max_blk_size);
-+	BUG_ON(data->blocks > 65535);
-+
-+	host->data = data;
-+	host->data_early = 0;
-+	host->data->bytes_xfered = 0;
-+
-+
-+	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
-+		int flags;
-+
-+		flags = SG_MITER_ATOMIC;
-+		if (host->data->flags & MMC_DATA_READ)
-+			flags |= SG_MITER_TO_SG;
-+		else
-+			flags |= SG_MITER_FROM_SG;
-+		sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
-+		host->blocks = data->blocks;
-+	}
-+
-+	host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;
-+
-+	bcm2835_mmc_set_transfer_irqs(host);
-+
-+	/* Set the DMA boundary value and block size */
-+	bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
-+		data->blksz), SDHCI_BLOCK_SIZE);
-+	bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
-+
-+	BUG_ON(!host->data);
-+}
-+
-+static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host,
-+	struct mmc_command *cmd)
-+{
-+	u16 mode;
-+	struct mmc_data *data = cmd->data;
-+
-+	if (data == NULL) {
-+		/* clear Auto CMD settings for no data CMDs */
-+		mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE);
-+		bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
-+				SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
-+		return;
-+	}
-+
-+	WARN_ON(!host->data);
-+
-+	mode = SDHCI_TRNS_BLK_CNT_EN;
-+
-+	if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) {
-+		mode |= SDHCI_TRNS_MULTI;
-+
-+		/*
-+		 * If we are sending CMD23, CMD12 never gets sent
-+		 * on successful completion (so no Auto-CMD12).
-+		 */
-+		if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
-+			mode |= SDHCI_TRNS_AUTO_CMD12;
-+		else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
-+			mode |= SDHCI_TRNS_AUTO_CMD23;
-+			bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5);
-+		}
-+	}
-+
-+	if (data->flags & MMC_DATA_READ)
-+		mode |= SDHCI_TRNS_READ;
-+	if (host->flags & SDHCI_REQ_USE_DMA)
-+		mode |= SDHCI_TRNS_DMA;
-+
-+	bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE);
-+}
-+
-+void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+	int flags;
-+	u32 mask;
-+	unsigned long timeout;
-+
-+	WARN_ON(host->cmd);
-+
-+	/* Wait max 10 ms */
-+	timeout = 1000;
-+
-+	mask = SDHCI_CMD_INHIBIT;
-+	if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
-+		mask |= SDHCI_DATA_INHIBIT;
-+
-+	/* We shouldn't wait for data inihibit for stop commands, even
-+	   though they might use busy signaling */
-+	if (host->mrq->data && (cmd == host->mrq->data->stop))
-+		mask &= ~SDHCI_DATA_INHIBIT;
-+
-+	while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
-+		if (timeout == 0) {
-+			pr_err("%s: Controller never released inhibit bit(s).\n",
-+				mmc_hostname(host->mmc));
-+			bcm2835_mmc_dumpregs(host);
-+			cmd->error = -EIO;
-+			tasklet_schedule(&host->finish_tasklet);
-+			return;
-+		}
-+		timeout--;
-+		udelay(10);
-+	}
-+
-+	if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {
-+		host->max_delay = (1000-timeout)/100;
-+		pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+	}
-+
-+	timeout = jiffies;
-+	if (!cmd->data && cmd->busy_timeout > 9000)
-+		timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
-+	else
-+		timeout += 10 * HZ;
-+	mod_timer(&host->timer, timeout);
-+
-+	host->cmd = cmd;
-+	host->use_dma = false;
-+
-+	bcm2835_mmc_prepare_data(host, cmd);
-+
-+	bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6);
-+
-+	bcm2835_mmc_set_transfer_mode(host, cmd);
-+
-+	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
-+		pr_err("%s: Unsupported response type!\n",
-+			mmc_hostname(host->mmc));
-+		cmd->error = -EINVAL;
-+		tasklet_schedule(&host->finish_tasklet);
-+		return;
-+	}
-+
-+	if (!(cmd->flags & MMC_RSP_PRESENT))
-+		flags = SDHCI_CMD_RESP_NONE;
-+	else if (cmd->flags & MMC_RSP_136)
-+		flags = SDHCI_CMD_RESP_LONG;
-+	else if (cmd->flags & MMC_RSP_BUSY)
-+		flags = SDHCI_CMD_RESP_SHORT_BUSY;
-+	else
-+		flags = SDHCI_CMD_RESP_SHORT;
-+
-+	if (cmd->flags & MMC_RSP_CRC)
-+		flags |= SDHCI_CMD_CRC;
-+	if (cmd->flags & MMC_RSP_OPCODE)
-+		flags |= SDHCI_CMD_INDEX;
-+
-+	if (cmd->data)
-+		flags |= SDHCI_CMD_DATA;
-+
-+	bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
-+}
-+
-+
-+static void bcm2835_mmc_finish_data(struct bcm2835_host *host)
-+{
-+	struct mmc_data *data;
-+
-+	BUG_ON(!host->data);
-+
-+	data = host->data;
-+	host->data = NULL;
-+
-+	if (data->error)
-+		data->bytes_xfered = 0;
-+	else
-+		data->bytes_xfered = data->blksz * data->blocks;
-+
-+	/*
-+	 * Need to send CMD12 if -
-+	 * a) open-ended multiblock transfer (no CMD23)
-+	 * b) error in multiblock transfer
-+	 */
-+	if (data->stop &&
-+	    (data->error ||
-+	     !host->mrq->sbc)) {
-+
-+		/*
-+		 * The controller needs a reset of internal state machines
-+		 * upon error conditions.
-+		 */
-+		if (data->error) {
-+			bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
-+			bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
-+		}
-+
-+		bcm2835_mmc_send_command(host, data->stop);
-+	} else if (host->use_dma) {
-+		host->wait_for_dma = true;
-+	} else {
-+		tasklet_schedule(&host->finish_tasklet);
-+	}
-+}
-+
-+static void bcm2835_mmc_finish_command(struct bcm2835_host *host)
-+{
-+	int i;
-+
-+	BUG_ON(host->cmd == NULL);
-+
-+	if (host->cmd->flags & MMC_RSP_PRESENT) {
-+		if (host->cmd->flags & MMC_RSP_136) {
-+			/* CRC is stripped so we need to do some shifting. */
-+			for (i = 0; i < 4; i++) {
-+				host->cmd->resp[i] = bcm2835_mmc_readl(host,
-+					SDHCI_RESPONSE + (3-i)*4) << 8;
-+				if (i != 3)
-+					host->cmd->resp[i] |=
-+						bcm2835_mmc_readb(host,
-+						SDHCI_RESPONSE + (3-i)*4-1);
-+			}
-+		} else {
-+			host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE);
-+		}
-+	}
-+
-+	host->cmd->error = 0;
-+
-+	/* Finished CMD23, now send actual command. */
-+	if (host->cmd == host->mrq->sbc) {
-+		host->cmd = NULL;
-+		bcm2835_mmc_send_command(host, host->mrq->cmd);
-+
-+		if (host->mrq->cmd->data && host->use_dma) {
-+			/* DMA transfer starts now, PIO starts after interrupt */
-+			bcm2835_mmc_transfer_dma(host);
-+		}
-+	} else {
-+
-+		/* Processed actual command. */
-+		if (host->data && host->data_early)
-+			bcm2835_mmc_finish_data(host);
-+
-+		if (!host->cmd->data)
-+			tasklet_schedule(&host->finish_tasklet);
-+
-+		host->cmd = NULL;
-+	}
-+}
-+
-+
-+static void bcm2835_mmc_timeout_timer(unsigned long data)
-+{
-+	struct bcm2835_host *host;
-+	unsigned long flags;
-+
-+	host = (struct bcm2835_host *)data;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	if (host->mrq) {
-+		pr_err("%s: Timeout waiting for hardware interrupt.\n",
-+			mmc_hostname(host->mmc));
-+		bcm2835_mmc_dumpregs(host);
-+
-+		if (host->data) {
-+			host->data->error = -ETIMEDOUT;
-+			bcm2835_mmc_finish_data(host);
-+		} else {
-+			if (host->cmd)
-+				host->cmd->error = -ETIMEDOUT;
-+			else
-+				host->mrq->cmd->error = -ETIMEDOUT;
-+
-+			tasklet_schedule(&host->finish_tasklet);
-+		}
-+	}
-+
-+	mmiowb();
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+
-+static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
-+{
-+	if (!(host->flags & SDHCI_DEVICE_DEAD)) {
-+		if (enable)
-+			host->ier |= SDHCI_INT_CARD_INT;
-+		else
-+			host->ier &= ~SDHCI_INT_CARD_INT;
-+
-+		bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7);
-+		bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7);
-+		mmiowb();
-+	}
-+}
-+
-+static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
-+{
-+	struct bcm2835_host *host = mmc_priv(mmc);
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+	if (enable)
-+		host->flags |= SDHCI_SDIO_IRQ_ENABLED;
-+	else
-+		host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
-+
-+	bcm2835_mmc_enable_sdio_irq_nolock(host, enable);
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+
-+	BUG_ON(intmask == 0);
-+
-+	if (!host->cmd) {
-+		pr_err("%s: Got command interrupt 0x%08x even "
-+			"though no command operation was in progress.\n",
-+			mmc_hostname(host->mmc), (unsigned)intmask);
-+		bcm2835_mmc_dumpregs(host);
-+		return;
-+	}
-+
-+	if (intmask & SDHCI_INT_TIMEOUT)
-+		host->cmd->error = -ETIMEDOUT;
-+	else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
-+			SDHCI_INT_INDEX)) {
-+			host->cmd->error = -EILSEQ;
-+	}
-+
-+	if (host->cmd->error) {
-+		tasklet_schedule(&host->finish_tasklet);
-+		return;
-+	}
-+
-+	if (intmask & SDHCI_INT_RESPONSE)
-+		bcm2835_mmc_finish_command(host);
-+
-+}
-+
-+static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+	struct dma_chan *dma_chan;
-+	u32 dir_data;
-+
-+	BUG_ON(intmask == 0);
-+
-+	if (!host->data) {
-+		/*
-+		 * The "data complete" interrupt is also used to
-+		 * indicate that a busy state has ended. See comment
-+		 * above in sdhci_cmd_irq().
-+		 */
-+		if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
-+			if (intmask & SDHCI_INT_DATA_END) {
-+				bcm2835_mmc_finish_command(host);
-+				return;
-+			}
-+		}
-+
-+		pr_debug("%s: Got data interrupt 0x%08x even "
-+			"though no data operation was in progress.\n",
-+			mmc_hostname(host->mmc), (unsigned)intmask);
-+		bcm2835_mmc_dumpregs(host);
-+
-+		return;
-+	}
-+
-+	if (intmask & SDHCI_INT_DATA_TIMEOUT)
-+		host->data->error = -ETIMEDOUT;
-+	else if (intmask & SDHCI_INT_DATA_END_BIT)
-+		host->data->error = -EILSEQ;
-+	else if ((intmask & SDHCI_INT_DATA_CRC) &&
-+		SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND))
-+			!= MMC_BUS_TEST_R)
-+		host->data->error = -EILSEQ;
-+
-+	if (host->use_dma) {
-+		if  (host->data->flags & MMC_DATA_WRITE) {
-+			/* IRQ handled here */
-+
-+			dma_chan = host->dma_chan_rxtx;
-+			dir_data = DMA_TO_DEVICE;
-+			dma_unmap_sg(dma_chan->device->dev,
-+				 host->data->sg, host->data->sg_len,
-+				 dir_data);
-+
-+			bcm2835_mmc_finish_data(host);
-+		}
-+
-+	} else {
-+		if (host->data->error)
-+			bcm2835_mmc_finish_data(host);
-+		else {
-+			if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
-+				bcm2835_mmc_transfer_pio(host);
-+
-+			if (intmask & SDHCI_INT_DATA_END) {
-+				if (host->cmd) {
-+					/*
-+					 * Data managed to finish before the
-+					 * command completed. Make sure we do
-+					 * things in the proper order.
-+					 */
-+					host->data_early = 1;
-+				} else {
-+					bcm2835_mmc_finish_data(host);
-+				}
-+			}
-+		}
-+	}
-+}
-+
-+
-+static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id)
-+{
-+	irqreturn_t result = IRQ_NONE;
-+	struct bcm2835_host *host = dev_id;
-+	u32 intmask, mask, unexpected = 0;
-+	int max_loops = 16;
-+
-+	spin_lock(&host->lock);
-+
-+	intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+
-+	if (!intmask || intmask == 0xffffffff) {
-+		result = IRQ_NONE;
-+		goto out;
-+	}
-+
-+	do {
-+		/* Clear selected interrupts. */
-+		mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
-+				  SDHCI_INT_BUS_POWER);
-+		bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8);
-+
-+
-+		if (intmask & SDHCI_INT_CMD_MASK)
-+			bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
-+
-+		if (intmask & SDHCI_INT_DATA_MASK)
-+			bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
-+
-+		if (intmask & SDHCI_INT_BUS_POWER)
-+			pr_err("%s: Card is consuming too much power!\n",
-+				mmc_hostname(host->mmc));
-+
-+		if (intmask & SDHCI_INT_CARD_INT) {
-+			bcm2835_mmc_enable_sdio_irq_nolock(host, false);
-+			host->thread_isr |= SDHCI_INT_CARD_INT;
-+			result = IRQ_WAKE_THREAD;
-+		}
-+
-+		intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
-+			     SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
-+			     SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
-+			     SDHCI_INT_CARD_INT);
-+
-+		if (intmask) {
-+			unexpected |= intmask;
-+			bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9);
-+		}
-+
-+		if (result == IRQ_NONE)
-+			result = IRQ_HANDLED;
-+
-+		intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+	} while (intmask && --max_loops);
-+out:
-+	spin_unlock(&host->lock);
-+
-+	if (unexpected) {
-+		pr_err("%s: Unexpected interrupt 0x%08x.\n",
-+			   mmc_hostname(host->mmc), unexpected);
-+		bcm2835_mmc_dumpregs(host);
-+	}
-+
-+	return result;
-+}
-+
-+static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id)
-+{
-+	struct bcm2835_host *host = dev_id;
-+	unsigned long flags;
-+	u32 isr;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+	isr = host->thread_isr;
-+	host->thread_isr = 0;
-+	spin_unlock_irqrestore(&host->lock, flags);
-+
-+	if (isr & SDHCI_INT_CARD_INT) {
-+		sdio_run_irqs(host->mmc);
-+
-+		spin_lock_irqsave(&host->lock, flags);
-+		if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
-+			bcm2835_mmc_enable_sdio_irq_nolock(host, true);
-+		spin_unlock_irqrestore(&host->lock, flags);
-+	}
-+
-+	return isr ? IRQ_HANDLED : IRQ_NONE;
-+}
-+
-+
-+
-+void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock)
-+{
-+	int div = 0; /* Initialized for compiler warning */
-+	int real_div = div, clk_mul = 1;
-+	u16 clk = 0;
-+	unsigned long timeout;
-+	unsigned int input_clock = clock;
-+
-+	if (host->overclock_50 && (clock == 50000000))
-+		clock = host->overclock_50 * 1000000 + 999999;
-+
-+	host->mmc->actual_clock = 0;
-+
-+	bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL);
-+
-+	if (clock == 0)
-+		return;
-+
-+	/* Version 3.00 divisors must be a multiple of 2. */
-+	if (host->max_clk <= clock)
-+		div = 1;
-+	else {
-+		for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
-+			 div += 2) {
-+			if ((host->max_clk / div) <= clock)
-+				break;
-+		}
-+	}
-+
-+	real_div = div;
-+	div >>= 1;
-+
-+	if (real_div)
-+		clock = (host->max_clk * clk_mul) / real_div;
-+	host->mmc->actual_clock = clock;
-+
-+	if ((clock > input_clock) && (clock > host->max_overclock)) {
-+		pr_warn("%s: Overclocking to %dHz\n",
-+			mmc_hostname(host->mmc), clock);
-+		host->max_overclock = clock;
-+	}
-+
-+	clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
-+	clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
-+		<< SDHCI_DIVIDER_HI_SHIFT;
-+	clk |= SDHCI_CLOCK_INT_EN;
-+	bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+
-+	/* Wait max 20 ms */
-+	timeout = 20;
-+	while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL))
-+		& SDHCI_CLOCK_INT_STABLE)) {
-+		if (timeout == 0) {
-+			pr_err("%s: Internal clock never "
-+				"stabilised.\n", mmc_hostname(host->mmc));
-+			bcm2835_mmc_dumpregs(host);
-+			return;
-+		}
-+		timeout--;
-+		mdelay(1);
-+	}
-+
-+	if (20-timeout > 10 && 20-timeout > host->max_delay) {
-+		host->max_delay = 20-timeout;
-+		pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
-+	}
-+
-+	clk |= SDHCI_CLOCK_CARD_EN;
-+	bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+}
-+
-+static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+	struct bcm2835_host *host;
-+	unsigned long flags;
-+
-+	host = mmc_priv(mmc);
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	WARN_ON(host->mrq != NULL);
-+
-+	host->mrq = mrq;
-+
-+	if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
-+		bcm2835_mmc_send_command(host, mrq->sbc);
-+	else
-+		bcm2835_mmc_send_command(host, mrq->cmd);
-+
-+	mmiowb();
-+	spin_unlock_irqrestore(&host->lock, flags);
-+
-+	if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) {
-+		/* DMA transfer starts now, PIO starts after interrupt */
-+		bcm2835_mmc_transfer_dma(host);
-+	}
-+}
-+
-+
-+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-+{
-+
-+	struct bcm2835_host *host = mmc_priv(mmc);
-+	unsigned long flags;
-+	u8 ctrl;
-+	u16 clk, ctrl_2;
-+
-+	pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n",
-+		 ios->clock, ios->power_mode, ios->bus_width,
-+		 ios->timing, ios->signal_voltage, ios->drv_type);
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	if (!ios->clock || ios->clock != host->clock) {
-+		bcm2835_mmc_set_clock(host, ios->clock);
-+		host->clock = ios->clock;
-+	}
-+
-+	if (host->pwr != SDHCI_POWER_330) {
-+		host->pwr = SDHCI_POWER_330;
-+		bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
-+	}
-+
-+	ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL);
-+
-+	/* set bus width */
-+	ctrl &= ~SDHCI_CTRL_8BITBUS;
-+	if (ios->bus_width == MMC_BUS_WIDTH_4)
-+		ctrl |= SDHCI_CTRL_4BITBUS;
-+	else
-+		ctrl &= ~SDHCI_CTRL_4BITBUS;
-+
-+	ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */
-+
-+
-+	bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-+	/*
-+	 * We only need to set Driver Strength if the
-+	 * preset value enable is not set.
-+	 */
-+	ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2);
-+	ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
-+	if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
-+		ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
-+	else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
-+		ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
-+
-+	bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
-+
-+	/* Reset SD Clock Enable */
-+	clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL);
-+	clk &= ~SDHCI_CLOCK_CARD_EN;
-+	bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
-+
-+	/* Re-enable SD Clock */
-+	bcm2835_mmc_set_clock(host, host->clock);
-+	bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-+
-+	mmiowb();
-+
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+
-+static struct mmc_host_ops bcm2835_ops = {
-+	.request = bcm2835_mmc_request,
-+	.set_ios = bcm2835_mmc_set_ios,
-+	.enable_sdio_irq = bcm2835_mmc_enable_sdio_irq,
-+};
-+
-+
-+static void bcm2835_mmc_tasklet_finish(unsigned long param)
-+{
-+	struct bcm2835_host *host;
-+	unsigned long flags;
-+	struct mmc_request *mrq;
-+
-+	host = (struct bcm2835_host *)param;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	/*
-+	 * If this tasklet gets rescheduled while running, it will
-+	 * be run again afterwards but without any active request.
-+	 */
-+	if (!host->mrq) {
-+		spin_unlock_irqrestore(&host->lock, flags);
-+		return;
-+	}
-+
-+	del_timer(&host->timer);
-+
-+	mrq = host->mrq;
-+
-+	/*
-+	 * The controller needs a reset of internal state machines
-+	 * upon error conditions.
-+	 */
-+	if (!(host->flags & SDHCI_DEVICE_DEAD) &&
-+	    ((mrq->cmd && mrq->cmd->error) ||
-+		 (mrq->data && (mrq->data->error ||
-+		  (mrq->data->stop && mrq->data->stop->error))))) {
-+
-+		spin_unlock_irqrestore(&host->lock, flags);
-+		bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
-+		bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
-+		spin_lock_irqsave(&host->lock, flags);
-+	}
-+
-+	host->mrq = NULL;
-+	host->cmd = NULL;
-+	host->data = NULL;
-+
-+	mmiowb();
-+
-+	spin_unlock_irqrestore(&host->lock, flags);
-+	mmc_request_done(host->mmc, mrq);
-+}
-+
-+
-+
-+static int bcm2835_mmc_add_host(struct bcm2835_host *host)
-+{
-+	struct mmc_host *mmc = host->mmc;
-+	struct device *dev = mmc->parent;
-+#ifndef FORCE_PIO
-+	struct dma_slave_config cfg;
-+#endif
-+	int ret;
-+
-+	bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+	host->clk_mul = 0;
-+
-+	mmc->f_max = host->max_clk;
-+	mmc->f_max = host->max_clk;
-+	mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
-+
-+	/* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
-+	host->timeout_clk = mmc->f_max / 1000;
-+	mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
-+
-+	/* host controller capabilities */
-+	mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL |
-+		MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED |
-+		MMC_CAP_MMC_HIGHSPEED;
-+
-+	mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
-+
-+	host->flags = SDHCI_AUTO_CMD23;
-+
-+	dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2);
-+#ifdef FORCE_PIO
-+	dev_info(dev, "Forcing PIO mode\n");
-+	host->have_dma = false;
-+#else
-+	if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {
-+		dev_err(dev, "%s: Unable to initialise DMA channel. Falling back to PIO\n",
-+			DRIVER_NAME);
-+		host->have_dma = false;
-+	} else {
-+		dev_info(dev, "DMA channel allocated");
-+
-+		cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+		cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+		cfg.slave_id = 11;		/* DREQ channel */
-+
-+		/* Validate the slave configurations */
-+
-+		cfg.direction = DMA_MEM_TO_DEV;
-+		cfg.src_addr = 0;
-+		cfg.dst_addr = host->bus_addr + SDHCI_BUFFER;
-+
-+		ret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);
-+
-+		if (ret == 0) {
-+			host->dma_cfg_tx = cfg;
-+
-+			cfg.direction = DMA_DEV_TO_MEM;
-+			cfg.src_addr = host->bus_addr + SDHCI_BUFFER;
-+			cfg.dst_addr = 0;
-+
-+			ret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);
-+		}
-+
-+		if (ret == 0) {
-+			host->dma_cfg_rx = cfg;
-+
-+			host->have_dma = true;
-+		} else {
-+			pr_err("%s: unable to configure DMA channel. "
-+			       "Falling back to PIO\n",
-+			       mmc_hostname(mmc));
-+			dma_release_channel(host->dma_chan_rxtx);
-+			host->dma_chan_rxtx = NULL;
-+			host->have_dma = false;
-+		}
-+	}
-+#endif
-+	mmc->max_segs = 128;
-+	mmc->max_req_size = 524288;
-+	mmc->max_seg_size = mmc->max_req_size;
-+	mmc->max_blk_size = 512;
-+	mmc->max_blk_count =  65535;
-+
-+	/* report supported voltage ranges */
-+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-+
-+	tasklet_init(&host->finish_tasklet,
-+		bcm2835_mmc_tasklet_finish, (unsigned long)host);
-+
-+	setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host);
-+	init_waitqueue_head(&host->buf_ready_int);
-+
-+	bcm2835_mmc_init(host, 0);
-+	ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq,
-+					bcm2835_mmc_thread_irq, IRQF_SHARED,
-+					mmc_hostname(mmc), host);
-+	if (ret) {
-+		dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret);
-+		goto untasklet;
-+	}
-+
-+	mmiowb();
-+	mmc_add_host(mmc);
-+
-+	return 0;
-+
-+untasklet:
-+	tasklet_kill(&host->finish_tasklet);
-+
-+	return ret;
-+}
-+
-+static int bcm2835_mmc_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct device_node *node = dev->of_node;
-+	struct clk *clk;
-+	struct resource *iomem;
-+	struct bcm2835_host *host;
-+	struct mmc_host *mmc;
-+	const __be32 *addr;
-+	int ret;
-+
-+	mmc = mmc_alloc_host(sizeof(*host), dev);
-+	if (!mmc)
-+		return -ENOMEM;
-+
-+	mmc->ops = &bcm2835_ops;
-+	host = mmc_priv(mmc);
-+	host->mmc = mmc;
-+	host->timeout = msecs_to_jiffies(1000);
-+	spin_lock_init(&host->lock);
-+
-+	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	host->ioaddr = devm_ioremap_resource(dev, iomem);
-+	if (IS_ERR(host->ioaddr)) {
-+		ret = PTR_ERR(host->ioaddr);
-+		goto err;
-+	}
-+
-+	addr = of_get_address(node, 0, NULL, NULL);
-+	if (!addr) {
-+		dev_err(dev, "could not get DMA-register address\n");
-+		return -ENODEV;
-+	}
-+	host->bus_addr = be32_to_cpup(addr);
-+	pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n",
-+		 (unsigned long)host->ioaddr,
-+		 (unsigned long)iomem->start,
-+		 (unsigned long)host->bus_addr);
-+
-+#ifndef FORCE_PIO
-+	if (node) {
-+		host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx");
-+		if (!host->dma_chan_rxtx)
-+			host->dma_chan_rxtx =
-+				dma_request_slave_channel(dev, "tx");
-+		if (!host->dma_chan_rxtx)
-+			host->dma_chan_rxtx =
-+				dma_request_slave_channel(dev, "rx");
-+	} else {
-+		dma_cap_mask_t mask;
-+
-+		dma_cap_zero(mask);
-+		/* we don't care about the channel, any would work */
-+		dma_cap_set(DMA_SLAVE, mask);
-+		host->dma_chan_rxtx = dma_request_channel(mask, NULL, NULL);
-+	}
-+#endif
-+	clk = devm_clk_get(dev, NULL);
-+	if (IS_ERR(clk)) {
-+		ret = PTR_ERR(clk);
-+		if (ret == -EPROBE_DEFER)
-+			dev_info(dev, "could not get clk, deferring probe\n");
-+		else
-+			dev_err(dev, "could not get clk\n");
-+		goto err;
-+	}
-+
-+	host->max_clk = clk_get_rate(clk);
-+
-+	host->irq = platform_get_irq(pdev, 0);
-+	if (host->irq <= 0) {
-+		dev_err(dev, "get IRQ failed\n");
-+		ret = -EINVAL;
-+		goto err;
-+	}
-+
-+	if (node) {
-+		mmc_of_parse(mmc);
-+
-+		/* Read any custom properties */
-+		of_property_read_u32(node,
-+				     "brcm,overclock-50",
-+				     &host->overclock_50);
-+	} else {
-+		mmc->caps |= MMC_CAP_4_BIT_DATA;
-+	}
-+
-+	ret = bcm2835_mmc_add_host(host);
-+	if (ret)
-+		goto err;
-+
-+	platform_set_drvdata(pdev, host);
-+
-+	return 0;
-+err:
-+	mmc_free_host(mmc);
-+
-+	return ret;
-+}
-+
-+static int bcm2835_mmc_remove(struct platform_device *pdev)
-+{
-+	struct bcm2835_host *host = platform_get_drvdata(pdev);
-+	unsigned long flags;
-+	int dead;
-+	u32 scratch;
-+
-+	dead = 0;
-+	scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
-+	if (scratch == (u32)-1)
-+		dead = 1;
-+
-+
-+	if (dead) {
-+		spin_lock_irqsave(&host->lock, flags);
-+
-+		host->flags |= SDHCI_DEVICE_DEAD;
-+
-+		if (host->mrq) {
-+			pr_err("%s: Controller removed during "
-+				" transfer!\n", mmc_hostname(host->mmc));
-+
-+			host->mrq->cmd->error = -ENOMEDIUM;
-+			tasklet_schedule(&host->finish_tasklet);
-+		}
-+
-+		spin_unlock_irqrestore(&host->lock, flags);
-+	}
-+
-+	mmc_remove_host(host->mmc);
-+
-+	if (!dead)
-+		bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
-+
-+	free_irq(host->irq, host);
-+
-+	del_timer_sync(&host->timer);
-+
-+	tasklet_kill(&host->finish_tasklet);
-+
-+	mmc_free_host(host->mmc);
-+	platform_set_drvdata(pdev, NULL);
-+
-+	return 0;
-+}
-+
-+
-+static const struct of_device_id bcm2835_mmc_match[] = {
-+	{ .compatible = "brcm,bcm2835-mmc" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, bcm2835_mmc_match);
-+
-+
-+
-+static struct platform_driver bcm2835_mmc_driver = {
-+	.probe      = bcm2835_mmc_probe,
-+	.remove     = bcm2835_mmc_remove,
-+	.driver     = {
-+		.name		= DRIVER_NAME,
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= bcm2835_mmc_match,
-+	},
-+};
-+module_platform_driver(bcm2835_mmc_driver);
-+
-+module_param(mmc_debug, uint, 0644);
-+module_param(mmc_debug2, uint, 0644);
-+MODULE_ALIAS("platform:mmc-bcm2835");
-+MODULE_DESCRIPTION("BCM2835 SDHCI driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Gellert Weisz");
---- a/include/linux/mmc/card.h
-+++ b/include/linux/mmc/card.h
-@@ -269,6 +269,8 @@ struct mmc_card {
- #define MMC_QUIRK_TRIM_BROKEN	(1<<12)		/* Skip trim */
- #define MMC_QUIRK_BROKEN_HPI	(1<<13)		/* Disable broken HPI support */
- 
-+#define MMC_QUIRK_ERASE_BROKEN	(1<<31)		/* Skip erase */
-+
- 	bool			reenable_cmdq;	/* Re-enable Command Queue */
- 
- 	unsigned int		erase_size;	/* erase size in sectors */
diff --git a/target/linux/brcm2708/patches-4.14/950-0041-Adding-bcm2835-sdhost-driver-and-an-overlay-to-enabl.patch b/target/linux/brcm2708/patches-4.14/950-0041-Adding-bcm2835-sdhost-driver-and-an-overlay-to-enabl.patch
deleted file mode 100644
index 86e0e2e9c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0041-Adding-bcm2835-sdhost-driver-and-an-overlay-to-enabl.patch
+++ /dev/null
@@ -1,2401 +0,0 @@
-From f6ef8b1ebd154b65626191b38ca2cde8274d3ecd Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 25 Mar 2015 17:49:47 +0000
-Subject: [PATCH 041/454] Adding bcm2835-sdhost driver, and an overlay to
- enable it
-
-BCM2835 has two SD card interfaces. This driver uses the other one.
-
-bcm2835-sdhost: Error handling fix, and code clarification
-
-bcm2835-sdhost: Adding overclocking option
-
-Allow a different clock speed to be substitued for a requested 50MHz.
-This option is exposed using the "overclock_50" DT parameter.
-Note that the sdhost interface is restricted to integer divisions of
-core_freq, and the highest sensible option for a core_freq of 250MHz
-is 84 (250/3 = 83.3MHz), the next being 125 (250/2) which is much too
-high.
-
-Use at your own risk.
-
-bcm2835-sdhost: Round up the overclock, so 62 works for 62.5Mhz
-
-Also only warn once for each overclock setting.
-
-bcm2835-sdhost: Improve error handling and recovery
-
-1) Expose the hw_reset method to the MMC framework, removing many
-   internal calls by the driver.
-
-2) Reduce overclock setting on error.
-
-3) Increase timeout to cope with high capacity cards.
-
-4) Add properties and parameters to control pio_limit and debug.
-
-5) Reduce messages at probe time.
-
-bcm2835-sdhost: Further improve overclock back-off
-
-bcm2835-sdhost: Clear HBLC for PIO mode
-
-Also update pio_limit default in overlay README.
-
-bcm2835-sdhost: Add the ERASE capability
-
-See: https://github.com/raspberrypi/linux/issues/1076
-
-bcm2835-sdhost: Ignore CRC7 for MMC CMD1
-
-It seems that the sdhost interface returns CRC7 errors for CMD1,
-which is the MMC-specific SEND_OP_COND. Returning these errors to
-the MMC layer causes a downward spiral, but ignoring them seems
-to be harmless.
-
-bcm2835-mmc/sdhost: Remove ARCH_BCM2835 differences
-
-The bcm2835-mmc driver (and -sdhost driver that copied from it)
-contains code to handle SDIO interrupts in a threaded interrupt
-handler rather than waking the MMC framework thread. The change
-follows a patch from Russell King that adds the facility as the
-preferred way of working.
-
-However, the new code path is only present in ARCH_BCM2835
-builds, which I have taken to be a way of testing the waters
-rather than making the change across the board; I can't see
-any technical reason why it wouldn't be enabled for MACH_BCM270X
-builds. So this patch standardises on the ARCH_BCM2835 code,
-removing the old code paths.
-
-bcm2835-sdhost: Don't log timeout errors unless debug=1
-
-The MMC card-discovery process generates timeouts. This is
-expected behaviour, so reporting it to the user serves no purpose.
-Suppress the reporting of timeout errors unless the debug flag
-is on.
-
-bcm2835-sdhost: Add workaround for odd behaviour on some cards
-
-For reasons not understood, the sdhost driver fails when reading
-sectors very near the end of some SD cards. The problem could
-be related to the similar issue that reading the final sector
-of any card as part of a multiple read never completes, and the
-workaround is an extension of the mechanism introduced to solve
-that problem which ensures those sectors are always read singly.
-
-bcm2835-sdhost: Major revision
-
-This is a significant revision of the bcm2835-sdhost driver. It
-improves on the original in a number of ways:
-
-1) Through the use of CMD23 for reads it appears to avoid problems
-   reading some sectors on certain high speed cards.
-2) Better atomicity to prevent crashes.
-3) Higher performance.
-4) Activity logging included, for easier diagnosis in the event
-   of a problem.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-bcm2835-sdhost: Restore ATOMIC flag to PIO sg mapping
-
-Allocation problems have been seen in a wireless driver, and
-this is the only change which might have been responsible.
-
-SQUASH: bcm2835-sdhost: Only claim one DMA channel
-
-With both MMC controllers enabled there are few DMA channels left. The
-bcm2835-sdhost driver only uses DMA in one direction at a time, so it
-doesn't need to claim two channels.
-
-See: https://github.com/raspberrypi/linux/issues/1327
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-bcm2835-sdhost: Workaround for "slow" sectors
-
-Some cards have been seen to cause timeouts after certain sectors are
-read. This workaround enforces a minimum delay between the stop after
-reading one of those sectors and a subsequent data command.
-
-Using CMD23 (SET_BLOCK_COUNT) avoids this problem, so good cards will
-not be penalised by this workaround.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-bcm2835-sdhost: Firmware manages the clock divisor
-
-The bcm2835-sdhost driver hands control of the CDIV clock divisor
-register to matching firmware, allowing it to adjust to a changing
-core clock. This removes the need to use the performance governor or
-to enable io_is_busy on the on-demand governor in order to get the
-best SD performance.
-
-N.B. As SD clocks must be an integer divisor of the core clock, it is
-possible that the SD clock for "turbo" mode can be different (even
-lower) than "normal" mode.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-bcm2835-sdhost: Reset the clock in task context
-
-Since reprogramming the clock can now involve a round-trip to the
-firmware it must not be done at atomic context, and a tasklet
-is not a task.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-bcm2835-sdhost: Don't exit cmd wait loop on error
-
-The FAIL flag can be set in the CMD register before command processing
-is complete, leading to spurious "failed to complete" errors. This has
-the effect of promoting harmless CRC7 errors during CMD1 processing
-into errors that can delay and even prevent booting.
-
-Also:
-1) Convert the last KERN_ERROR message in the register dumping to
-   KERN_INFO.
-2) Remove an unnecessary reset call from  bcm2835_sdhost_add_host.
-
-See: https://github.com/raspberrypi/linux/pull/1492
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-bcm2835-sdhost: mmc_card_blockaddr fix
-
-Get the definition of mmc_card_blockaddr from drivers/mmc/core/card.h.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/mmc/host/Kconfig          |   10 +
- drivers/mmc/host/Makefile         |    1 +
- drivers/mmc/host/bcm2835-sdhost.c | 2193 +++++++++++++++++++++++++++++
- 3 files changed, 2204 insertions(+)
- create mode 100644 drivers/mmc/host/bcm2835-sdhost.c
-
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -33,6 +33,16 @@ config MMC_BCM2835_PIO_DMA_BARRIER
- 
- 	  If unsure, say 2 here.
- 
-+config MMC_BCM2835_SDHOST
-+	tristate "Support for the SDHost controller on BCM2708/9"
-+	depends on ARCH_BCM2835
-+	help
-+	  This selects the SDHost controller on BCM2835/6.
-+
-+	  If you have a controller with this interface, say Y or M here.
-+
-+	  If unsure, say N.
-+
- config MMC_DEBUG
- 	bool "MMC host drivers debugging"
- 	depends on MMC != n
---- a/drivers/mmc/host/Makefile
-+++ b/drivers/mmc/host/Makefile
-@@ -21,6 +21,7 @@ obj-$(CONFIG_MMC_SDHCI_SIRF)   	+= sdhci
- obj-$(CONFIG_MMC_SDHCI_F_SDH30)	+= sdhci_f_sdh30.o
- obj-$(CONFIG_MMC_SDHCI_SPEAR)	+= sdhci-spear.o
- obj-$(CONFIG_MMC_BCM2835_MMC)	+= bcm2835-mmc.o
-+obj-$(CONFIG_MMC_BCM2835_SDHOST)	+= bcm2835-sdhost.o
- obj-$(CONFIG_MMC_WBSD)		+= wbsd.o
- obj-$(CONFIG_MMC_AU1X)		+= au1xmmc.o
- obj-$(CONFIG_MMC_MTK)		+= mtk-sd.o
---- /dev/null
-+++ b/drivers/mmc/host/bcm2835-sdhost.c
-@@ -0,0 +1,2193 @@
-+/*
-+ * BCM2835 SD host driver.
-+ *
-+ * Author:      Phil Elwell <phil@raspberrypi.org>
-+ *              Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
-+ *
-+ * Based on
-+ *  mmc-bcm2835.c by Gellert Weisz
-+ * which is, in turn, based on
-+ *  sdhci-bcm2708.c by Broadcom
-+ *  sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
-+ *  sdhci.c and sdhci-pci.c by Pierre Ossman
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms and conditions of the GNU General Public License,
-+ * version 2, as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-+ * more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+#define FIFO_READ_THRESHOLD     4
-+#define FIFO_WRITE_THRESHOLD    4
-+#define ALLOW_CMD23_READ        1
-+#define ALLOW_CMD23_WRITE       0
-+#define ENABLE_LOG              1
-+#define SDDATA_FIFO_PIO_BURST   8
-+#define CMD_DALLY_US            1
-+
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/mmc/mmc.h>
-+#include <linux/mmc/host.h>
-+#include <linux/mmc/sd.h>
-+#include <linux/mmc/sdio.h>
-+#include <linux/scatterlist.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+#include <linux/clk.h>
-+#include <linux/platform_device.h>
-+#include <linux/err.h>
-+#include <linux/blkdev.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/of_dma.h>
-+#include <linux/time.h>
-+#include <linux/workqueue.h>
-+#include <linux/interrupt.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+/* For mmc_card_blockaddr */
-+#include "../core/card.h"
-+
-+#define DRIVER_NAME "sdhost-bcm2835"
-+
-+#define SDCMD  0x00 /* Command to SD card              - 16 R/W */
-+#define SDARG  0x04 /* Argument to SD card             - 32 R/W */
-+#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
-+#define SDCDIV 0x0c /* Start value for clock divider   - 11 R/W */
-+#define SDRSP0 0x10 /* SD card response (31:0)         - 32 R   */
-+#define SDRSP1 0x14 /* SD card response (63:32)        - 32 R   */
-+#define SDRSP2 0x18 /* SD card response (95:64)        - 32 R   */
-+#define SDRSP3 0x1c /* SD card response (127:96)       - 32 R   */
-+#define SDHSTS 0x20 /* SD host status                  - 11 R   */
-+#define SDVDD  0x30 /* SD card power control           -  1 R/W */
-+#define SDEDM  0x34 /* Emergency Debug Mode            - 13 R/W */
-+#define SDHCFG 0x38 /* Host configuration              -  2 R/W */
-+#define SDHBCT 0x3c /* Host byte count (debug)         - 32 R/W */
-+#define SDDATA 0x40 /* Data to/from SD card            - 32 R/W */
-+#define SDHBLC 0x50 /* Host block count (SDIO/SDHC)    -  9 R/W */
-+
-+#define SDCMD_NEW_FLAG                  0x8000
-+#define SDCMD_FAIL_FLAG                 0x4000
-+#define SDCMD_BUSYWAIT                  0x800
-+#define SDCMD_NO_RESPONSE               0x400
-+#define SDCMD_LONG_RESPONSE             0x200
-+#define SDCMD_WRITE_CMD                 0x80
-+#define SDCMD_READ_CMD                  0x40
-+#define SDCMD_CMD_MASK                  0x3f
-+
-+#define SDCDIV_MAX_CDIV                 0x7ff
-+
-+#define SDHSTS_BUSY_IRPT                0x400
-+#define SDHSTS_BLOCK_IRPT               0x200
-+#define SDHSTS_SDIO_IRPT                0x100
-+#define SDHSTS_REW_TIME_OUT             0x80
-+#define SDHSTS_CMD_TIME_OUT             0x40
-+#define SDHSTS_CRC16_ERROR              0x20
-+#define SDHSTS_CRC7_ERROR               0x10
-+#define SDHSTS_FIFO_ERROR               0x08
-+/* Reserved */
-+/* Reserved */
-+#define SDHSTS_DATA_FLAG                0x01
-+
-+#define SDHSTS_TRANSFER_ERROR_MASK      (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR)
-+#define SDHSTS_ERROR_MASK               (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK)
-+
-+#define SDHCFG_BUSY_IRPT_EN     (1<<10)
-+#define SDHCFG_BLOCK_IRPT_EN    (1<<8)
-+#define SDHCFG_SDIO_IRPT_EN     (1<<5)
-+#define SDHCFG_DATA_IRPT_EN     (1<<4)
-+#define SDHCFG_SLOW_CARD        (1<<3)
-+#define SDHCFG_WIDE_EXT_BUS     (1<<2)
-+#define SDHCFG_WIDE_INT_BUS     (1<<1)
-+#define SDHCFG_REL_CMD_LINE     (1<<0)
-+
-+#define SDEDM_FORCE_DATA_MODE   (1<<19)
-+#define SDEDM_CLOCK_PULSE       (1<<20)
-+#define SDEDM_BYPASS            (1<<21)
-+
-+#define SDEDM_WRITE_THRESHOLD_SHIFT 9
-+#define SDEDM_READ_THRESHOLD_SHIFT 14
-+#define SDEDM_THRESHOLD_MASK     0x1f
-+
-+#define SDEDM_FSM_MASK           0xf
-+#define SDEDM_FSM_IDENTMODE      0x0
-+#define SDEDM_FSM_DATAMODE       0x1
-+#define SDEDM_FSM_READDATA       0x2
-+#define SDEDM_FSM_WRITEDATA      0x3
-+#define SDEDM_FSM_READWAIT       0x4
-+#define SDEDM_FSM_READCRC        0x5
-+#define SDEDM_FSM_WRITECRC       0x6
-+#define SDEDM_FSM_WRITEWAIT1     0x7
-+#define SDEDM_FSM_POWERDOWN      0x8
-+#define SDEDM_FSM_POWERUP        0x9
-+#define SDEDM_FSM_WRITESTART1    0xa
-+#define SDEDM_FSM_WRITESTART2    0xb
-+#define SDEDM_FSM_GENPULSES      0xc
-+#define SDEDM_FSM_WRITEWAIT2     0xd
-+#define SDEDM_FSM_STARTPOWDOWN   0xf
-+
-+#define SDDATA_FIFO_WORDS        16
-+
-+#define USE_CMD23_FLAGS          ((ALLOW_CMD23_READ * MMC_DATA_READ) | \
-+				  (ALLOW_CMD23_WRITE * MMC_DATA_WRITE))
-+
-+#define MHZ 1000000
-+
-+
-+struct bcm2835_host {
-+	spinlock_t		lock;
-+
-+	void __iomem		*ioaddr;
-+	u32			bus_addr;
-+
-+	struct mmc_host		*mmc;
-+
-+	u32			pio_timeout;	/* In jiffies */
-+
-+	int			clock;		/* Current clock speed */
-+
-+	bool			slow_card;	/* Force 11-bit divisor */
-+
-+	unsigned int		max_clk;	/* Max possible freq */
-+
-+	struct tasklet_struct	finish_tasklet;	/* Tasklet structures */
-+
-+	struct work_struct	cmd_wait_wq;	/* Workqueue function */
-+
-+	struct timer_list	timer;		/* Timer for timeouts */
-+
-+	struct sg_mapping_iter	sg_miter;	/* SG state for PIO */
-+	unsigned int		blocks;		/* remaining PIO blocks */
-+
-+	int			irq;		/* Device IRQ */
-+
-+	u32			cmd_quick_poll_retries;
-+	u32			ns_per_fifo_word;
-+
-+	/* cached registers */
-+	u32			hcfg;
-+	u32			cdiv;
-+
-+	struct mmc_request		*mrq;			/* Current request */
-+	struct mmc_command		*cmd;			/* Current command */
-+	struct mmc_data			*data;			/* Current data request */
-+	unsigned int			data_complete:1;	/* Data finished before cmd */
-+
-+	unsigned int			flush_fifo:1;		/* Drain the fifo when finishing */
-+
-+	unsigned int			use_busy:1;		/* Wait for busy interrupt */
-+
-+	unsigned int			use_sbc:1;		/* Send CMD23 */
-+
-+	unsigned int			debug:1;		/* Enable debug output */
-+	unsigned int			firmware_sets_cdiv:1;	/* Let the firmware manage the clock */
-+	unsigned int			reset_clock:1;		/* Reset the clock fore the next request */
-+
-+	/*DMA part*/
-+	struct dma_chan			*dma_chan_rxtx;		/* DMA channel for reads and writes */
-+	struct dma_chan			*dma_chan;		/* Channel in use */
-+	struct dma_slave_config		dma_cfg_rx;
-+	struct dma_slave_config		dma_cfg_tx;
-+	struct dma_async_tx_descriptor	*dma_desc;
-+	u32				dma_dir;
-+	u32				drain_words;
-+	struct page 			*drain_page;
-+	u32				drain_offset;
-+
-+	bool				allow_dma;
-+	bool				use_dma;
-+	/*end of DMA part*/
-+
-+	int				max_delay;	/* maximum length of time spent waiting */
-+	struct timeval			stop_time;	/* when the last stop was issued */
-+	u32				delay_after_stop; /* minimum time between stop and subsequent data transfer */
-+	u32				delay_after_this_stop; /* minimum time between this stop and subsequent data transfer */
-+	u32				user_overclock_50; /* User's preferred frequency to use when 50MHz is requested (in MHz) */
-+	u32				overclock_50;	/* frequency to use when 50MHz is requested (in MHz) */
-+	u32				overclock;	/* Current frequency if overclocked, else zero */
-+	u32				pio_limit;	/* Maximum block count for PIO (0 = always DMA) */
-+
-+	u32				sectors;	/* Cached card size in sectors */
-+};
-+
-+#if ENABLE_LOG
-+
-+struct log_entry_struct {
-+	char event[4];
-+	u32 timestamp;
-+	u32 param1;
-+	u32 param2;
-+};
-+
-+typedef struct log_entry_struct LOG_ENTRY_T;
-+
-+LOG_ENTRY_T *sdhost_log_buf;
-+dma_addr_t sdhost_log_addr;
-+static u32 sdhost_log_idx;
-+static spinlock_t log_lock;
-+static void __iomem *timer_base;
-+
-+#define LOG_ENTRIES (256*1)
-+#define LOG_SIZE (sizeof(LOG_ENTRY_T)*LOG_ENTRIES)
-+
-+static void log_init(struct device *dev, u32 bus_to_phys)
-+{
-+	spin_lock_init(&log_lock);
-+	sdhost_log_buf = dma_zalloc_coherent(dev, LOG_SIZE, &sdhost_log_addr,
-+					     GFP_KERNEL);
-+	if (sdhost_log_buf) {
-+		pr_info("sdhost: log_buf @ %p (%x)\n",
-+			sdhost_log_buf, sdhost_log_addr);
-+		timer_base = ioremap_nocache(bus_to_phys + 0x7e003000, SZ_4K);
-+		if (!timer_base)
-+			pr_err("sdhost: failed to remap timer\n");
-+	}
-+	else
-+		pr_err("sdhost: failed to allocate log buf\n");
-+}
-+
-+static void log_event_impl(const char *event, u32 param1, u32 param2)
-+{
-+	if (sdhost_log_buf) {
-+		LOG_ENTRY_T *entry;
-+		unsigned long flags;
-+
-+		spin_lock_irqsave(&log_lock, flags);
-+
-+		entry = sdhost_log_buf + sdhost_log_idx;
-+		memcpy(entry->event, event, 4);
-+		entry->timestamp = (readl(timer_base + 4) & 0x3fffffff) +
-+			(smp_processor_id()<<30);
-+		entry->param1 = param1;
-+		entry->param2 = param2;
-+		sdhost_log_idx = (sdhost_log_idx + 1) % LOG_ENTRIES;
-+
-+		spin_unlock_irqrestore(&log_lock, flags);
-+	}
-+}
-+
-+static void log_dump(void)
-+{
-+	if (sdhost_log_buf) {
-+		LOG_ENTRY_T *entry;
-+		unsigned long flags;
-+		int idx;
-+
-+		spin_lock_irqsave(&log_lock, flags);
-+
-+		idx = sdhost_log_idx;
-+		do {
-+			entry = sdhost_log_buf + idx;
-+			if (entry->event[0] != '\0')
-+				pr_info("[%08x] %.4s %x %x\n",
-+				       entry->timestamp,
-+				       entry->event,
-+				       entry->param1,
-+				       entry->param2);
-+			idx = (idx + 1) % LOG_ENTRIES;
-+		} while (idx != sdhost_log_idx);
-+
-+		spin_unlock_irqrestore(&log_lock, flags);
-+	}
-+}
-+
-+#define log_event(event, param1, param2) log_event_impl(event, param1, param2)
-+
-+#else
-+
-+#define log_init(x) (void)0
-+#define log_event(event, param1, param2) (void)0
-+#define log_dump() (void)0
-+
-+#endif
-+
-+static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg)
-+{
-+	writel(val, host->ioaddr + reg);
-+}
-+
-+static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg)
-+{
-+	return readl(host->ioaddr + reg);
-+}
-+
-+static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg)
-+{
-+	return readl_relaxed(host->ioaddr + reg);
-+}
-+
-+static void bcm2835_sdhost_dumpcmd(struct bcm2835_host *host,
-+				   struct mmc_command *cmd,
-+				   const char *label)
-+{
-+	if (cmd)
-+		pr_info("%s:%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
-+			mmc_hostname(host->mmc),
-+			(cmd == host->cmd) ? '>' : ' ',
-+			label, cmd->opcode, cmd->arg, cmd->flags,
-+			cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
-+			cmd->error);
-+}
-+
-+static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host)
-+{
-+	if (host->mrq)
-+	{
-+		bcm2835_sdhost_dumpcmd(host, host->mrq->sbc, "sbc");
-+		bcm2835_sdhost_dumpcmd(host, host->mrq->cmd, "cmd");
-+		if (host->mrq->data)
-+			pr_info("%s: data blocks %x blksz %x - err %d\n",
-+			       mmc_hostname(host->mmc),
-+			       host->mrq->data->blocks,
-+			       host->mrq->data->blksz,
-+			       host->mrq->data->error);
-+		bcm2835_sdhost_dumpcmd(host, host->mrq->stop, "stop");
-+	}
-+
-+	pr_info("%s: =========== REGISTER DUMP ===========\n",
-+		mmc_hostname(host->mmc));
-+
-+	pr_info("%s: SDCMD  0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDCMD));
-+	pr_info("%s: SDARG  0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDARG));
-+	pr_info("%s: SDTOUT 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDTOUT));
-+	pr_info("%s: SDCDIV 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDCDIV));
-+	pr_info("%s: SDRSP0 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDRSP0));
-+	pr_info("%s: SDRSP1 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDRSP1));
-+	pr_info("%s: SDRSP2 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDRSP2));
-+	pr_info("%s: SDRSP3 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDRSP3));
-+	pr_info("%s: SDHSTS 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDHSTS));
-+	pr_info("%s: SDVDD  0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDVDD));
-+	pr_info("%s: SDEDM  0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDEDM));
-+	pr_info("%s: SDHCFG 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDHCFG));
-+	pr_info("%s: SDHBCT 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDHBCT));
-+	pr_info("%s: SDHBLC 0x%08x\n",
-+		mmc_hostname(host->mmc),
-+		bcm2835_sdhost_read(host, SDHBLC));
-+
-+	pr_info("%s: ===========================================\n",
-+		mmc_hostname(host->mmc));
-+}
-+
-+static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on)
-+{
-+	bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD);
-+}
-+
-+static void bcm2835_sdhost_reset_internal(struct bcm2835_host *host)
-+{
-+	u32 temp;
-+
-+	if (host->debug)
-+		pr_info("%s: reset\n", mmc_hostname(host->mmc));
-+
-+	bcm2835_sdhost_set_power(host, false);
-+
-+	bcm2835_sdhost_write(host, 0, SDCMD);
-+	bcm2835_sdhost_write(host, 0, SDARG);
-+	bcm2835_sdhost_write(host, 0xf00000, SDTOUT);
-+	bcm2835_sdhost_write(host, 0, SDCDIV);
-+	bcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */
-+	bcm2835_sdhost_write(host, 0, SDHCFG);
-+	bcm2835_sdhost_write(host, 0, SDHBCT);
-+	bcm2835_sdhost_write(host, 0, SDHBLC);
-+
-+	/* Limit fifo usage due to silicon bug */
-+	temp = bcm2835_sdhost_read(host, SDEDM);
-+	temp &= ~((SDEDM_THRESHOLD_MASK<<SDEDM_READ_THRESHOLD_SHIFT) |
-+		  (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));
-+	temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
-+		(FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
-+	bcm2835_sdhost_write(host, temp, SDEDM);
-+	mdelay(10);
-+	bcm2835_sdhost_set_power(host, true);
-+	mdelay(10);
-+	host->clock = 0;
-+	host->sectors = 0;
-+	bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+	bcm2835_sdhost_write(host, SDCDIV_MAX_CDIV, SDCDIV);
-+	mmiowb();
-+}
-+
-+static void bcm2835_sdhost_reset(struct mmc_host *mmc)
-+{
-+	struct bcm2835_host *host = mmc_priv(mmc);
-+	unsigned long flags;
-+	spin_lock_irqsave(&host->lock, flags);
-+	log_event("RST<", 0, 0);
-+
-+	bcm2835_sdhost_reset_internal(host);
-+
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
-+
-+static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft)
-+{
-+	pr_debug("bcm2835_sdhost_init(%d)\n", soft);
-+
-+	/* Set interrupt enables */
-+	host->hcfg = SDHCFG_BUSY_IRPT_EN;
-+
-+	bcm2835_sdhost_reset_internal(host);
-+
-+	if (soft) {
-+		/* force clock reconfiguration */
-+		host->clock = 0;
-+		bcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios);
-+	}
-+}
-+
-+static void bcm2835_sdhost_wait_transfer_complete(struct bcm2835_host *host)
-+{
-+	int timediff;
-+	u32 alternate_idle;
-+	u32 edm;
-+
-+	alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?
-+		SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
-+
-+	edm = bcm2835_sdhost_read(host, SDEDM);
-+
-+	log_event("WTC<", edm, 0);
-+
-+	timediff = 0;
-+
-+	while (1) {
-+		u32 fsm = edm & SDEDM_FSM_MASK;
-+		if ((fsm == SDEDM_FSM_IDENTMODE) ||
-+		    (fsm == SDEDM_FSM_DATAMODE))
-+			break;
-+		if (fsm == alternate_idle) {
-+			bcm2835_sdhost_write(host,
-+					     edm | SDEDM_FORCE_DATA_MODE,
-+					     SDEDM);
-+			break;
-+		}
-+
-+		timediff++;
-+		if (timediff == 100000) {
-+			pr_err("%s: wait_transfer_complete - still waiting after %d retries\n",
-+			       mmc_hostname(host->mmc),
-+			       timediff);
-+			log_dump();
-+			bcm2835_sdhost_dumpregs(host);
-+			host->mrq->data->error = -ETIMEDOUT;
-+			log_event("WTC!", edm, 0);
-+			return;
-+		}
-+		cpu_relax();
-+		edm = bcm2835_sdhost_read(host, SDEDM);
-+	}
-+	log_event("WTC>", edm, 0);
-+}
-+
-+static void bcm2835_sdhost_finish_data(struct bcm2835_host *host);
-+
-+static void bcm2835_sdhost_dma_complete(void *param)
-+{
-+	struct bcm2835_host *host = param;
-+	struct mmc_data *data = host->data;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+	log_event("DMA<", (u32)host->data, bcm2835_sdhost_read(host, SDHSTS));
-+	log_event("DMA ", bcm2835_sdhost_read(host, SDCMD),
-+		  bcm2835_sdhost_read(host, SDEDM));
-+
-+	if (host->dma_chan) {
-+		dma_unmap_sg(host->dma_chan->device->dev,
-+			     data->sg, data->sg_len,
-+			     host->dma_dir);
-+
-+		host->dma_chan = NULL;
-+	}
-+
-+	if (host->drain_words) {
-+		void *page;
-+		u32 *buf;
-+
-+		page = kmap_atomic(host->drain_page);
-+		buf = page + host->drain_offset;
-+
-+		while (host->drain_words) {
-+			u32 edm = bcm2835_sdhost_read(host, SDEDM);
-+			if ((edm >> 4) & 0x1f)
-+				*(buf++) = bcm2835_sdhost_read(host,
-+							       SDDATA);
-+			host->drain_words--;
-+		}
-+
-+		kunmap_atomic(page);
-+	}
-+
-+	bcm2835_sdhost_finish_data(host);
-+
-+	log_event("DMA>", (u32)host->data, 0);
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host)
-+{
-+	unsigned long flags;
-+	size_t blksize, len;
-+	u32 *buf;
-+	unsigned long wait_max;
-+
-+	blksize = host->data->blksz;
-+
-+	wait_max = jiffies + msecs_to_jiffies(host->pio_timeout);
-+
-+	local_irq_save(flags);
-+
-+	while (blksize) {
-+		int copy_words;
-+		u32 hsts = 0;
-+
-+		if (!sg_miter_next(&host->sg_miter)) {
-+			host->data->error = -EINVAL;
-+			break;
-+		}
-+
-+		len = min(host->sg_miter.length, blksize);
-+		if (len % 4) {
-+			host->data->error = -EINVAL;
-+			break;
-+		}
-+
-+		blksize -= len;
-+		host->sg_miter.consumed = len;
-+
-+		buf = (u32 *)host->sg_miter.addr;
-+
-+		copy_words = len/4;
-+
-+		while (copy_words) {
-+			int burst_words, words;
-+			u32 edm;
-+
-+			burst_words = SDDATA_FIFO_PIO_BURST;
-+			if (burst_words > copy_words)
-+				burst_words = copy_words;
-+			edm = bcm2835_sdhost_read(host, SDEDM);
-+			words = ((edm >> 4) & 0x1f);
-+
-+			if (words < burst_words) {
-+				int fsm_state = (edm & SDEDM_FSM_MASK);
-+				if ((fsm_state != SDEDM_FSM_READDATA) &&
-+				    (fsm_state != SDEDM_FSM_READWAIT) &&
-+				    (fsm_state != SDEDM_FSM_READCRC)) {
-+					hsts = bcm2835_sdhost_read(host,
-+								   SDHSTS);
-+					pr_info("%s: fsm %x, hsts %x\n",
-+					       mmc_hostname(host->mmc),
-+					       fsm_state, hsts);
-+					if (hsts & SDHSTS_ERROR_MASK)
-+						break;
-+				}
-+
-+				if (time_after(jiffies, wait_max)) {
-+					pr_err("%s: PIO read timeout - EDM %x\n",
-+					       mmc_hostname(host->mmc),
-+					       edm);
-+					hsts = SDHSTS_REW_TIME_OUT;
-+					break;
-+				}
-+				ndelay((burst_words - words) *
-+				       host->ns_per_fifo_word);
-+				continue;
-+			} else if (words > copy_words) {
-+				words = copy_words;
-+			}
-+
-+			copy_words -= words;
-+
-+			while (words) {
-+				*(buf++) = bcm2835_sdhost_read(host, SDDATA);
-+				words--;
-+			}
-+		}
-+
-+		if (hsts & SDHSTS_ERROR_MASK)
-+			break;
-+	}
-+
-+	sg_miter_stop(&host->sg_miter);
-+
-+	local_irq_restore(flags);
-+}
-+
-+static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host)
-+{
-+	unsigned long flags;
-+	size_t blksize, len;
-+	u32 *buf;
-+	unsigned long wait_max;
-+
-+	blksize = host->data->blksz;
-+
-+	wait_max = jiffies + msecs_to_jiffies(host->pio_timeout);
-+
-+	local_irq_save(flags);
-+
-+	while (blksize) {
-+		int copy_words;
-+		u32 hsts = 0;
-+
-+		if (!sg_miter_next(&host->sg_miter)) {
-+			host->data->error = -EINVAL;
-+			break;
-+		}
-+
-+		len = min(host->sg_miter.length, blksize);
-+		if (len % 4) {
-+			host->data->error = -EINVAL;
-+			break;
-+		}
-+
-+		blksize -= len;
-+		host->sg_miter.consumed = len;
-+
-+		buf = (u32 *)host->sg_miter.addr;
-+
-+		copy_words = len/4;
-+
-+		while (copy_words) {
-+			int burst_words, words;
-+			u32 edm;
-+
-+			burst_words = SDDATA_FIFO_PIO_BURST;
-+			if (burst_words > copy_words)
-+				burst_words = copy_words;
-+			edm = bcm2835_sdhost_read(host, SDEDM);
-+			words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);
-+
-+			if (words < burst_words) {
-+				int fsm_state = (edm & SDEDM_FSM_MASK);
-+				if ((fsm_state != SDEDM_FSM_WRITEDATA) &&
-+				    (fsm_state != SDEDM_FSM_WRITESTART1) &&
-+				    (fsm_state != SDEDM_FSM_WRITESTART2)) {
-+					hsts = bcm2835_sdhost_read(host,
-+								   SDHSTS);
-+					pr_info("%s: fsm %x, hsts %x\n",
-+					       mmc_hostname(host->mmc),
-+					       fsm_state, hsts);
-+					if (hsts & SDHSTS_ERROR_MASK)
-+						break;
-+				}
-+
-+				if (time_after(jiffies, wait_max)) {
-+					pr_err("%s: PIO write timeout - EDM %x\n",
-+					       mmc_hostname(host->mmc),
-+					       edm);
-+					hsts = SDHSTS_REW_TIME_OUT;
-+					break;
-+				}
-+				ndelay((burst_words - words) *
-+				       host->ns_per_fifo_word);
-+				continue;
-+			} else if (words > copy_words) {
-+				words = copy_words;
-+			}
-+
-+			copy_words -= words;
-+
-+			while (words) {
-+				bcm2835_sdhost_write(host, *(buf++), SDDATA);
-+				words--;
-+			}
-+		}
-+
-+		if (hsts & SDHSTS_ERROR_MASK)
-+			break;
-+	}
-+
-+	sg_miter_stop(&host->sg_miter);
-+
-+	local_irq_restore(flags);
-+}
-+
-+static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host)
-+{
-+	u32 sdhsts;
-+	bool is_read;
-+	BUG_ON(!host->data);
-+	log_event("XFP<", (u32)host->data, host->blocks);
-+
-+	is_read = (host->data->flags & MMC_DATA_READ) != 0;
-+	if (is_read)
-+		bcm2835_sdhost_read_block_pio(host);
-+	else
-+		bcm2835_sdhost_write_block_pio(host);
-+
-+	sdhsts = bcm2835_sdhost_read(host, SDHSTS);
-+	if (sdhsts & (SDHSTS_CRC16_ERROR |
-+		      SDHSTS_CRC7_ERROR |
-+		      SDHSTS_FIFO_ERROR)) {
-+		pr_err("%s: %s transfer error - HSTS %x\n",
-+		       mmc_hostname(host->mmc),
-+		       is_read ? "read" : "write",
-+		       sdhsts);
-+		host->data->error = -EILSEQ;
-+	} else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
-+			      SDHSTS_REW_TIME_OUT))) {
-+		pr_err("%s: %s timeout error - HSTS %x\n",
-+		       mmc_hostname(host->mmc),
-+		       is_read ? "read" : "write",
-+		       sdhsts);
-+		host->data->error = -ETIMEDOUT;
-+	}
-+	log_event("XFP>", (u32)host->data, host->blocks);
-+}
-+
-+static void bcm2835_sdhost_prepare_dma(struct bcm2835_host *host,
-+	struct mmc_data *data)
-+{
-+	int len, dir_data, dir_slave;
-+	struct dma_async_tx_descriptor *desc = NULL;
-+	struct dma_chan *dma_chan;
-+
-+	log_event("PRD<", (u32)data, 0);
-+	pr_debug("bcm2835_sdhost_prepare_dma()\n");
-+
-+	dma_chan = host->dma_chan_rxtx;
-+	if (data->flags & MMC_DATA_READ) {
-+		dir_data = DMA_FROM_DEVICE;
-+		dir_slave = DMA_DEV_TO_MEM;
-+	} else {
-+		dir_data = DMA_TO_DEVICE;
-+		dir_slave = DMA_MEM_TO_DEV;
-+	}
-+	log_event("PRD1", (u32)dma_chan, 0);
-+
-+	BUG_ON(!dma_chan->device);
-+	BUG_ON(!dma_chan->device->dev);
-+	BUG_ON(!data->sg);
-+
-+	/* The block doesn't manage the FIFO DREQs properly for multi-block
-+	   transfers, so don't attempt to DMA the final few words.
-+	   Unfortunately this requires the final sg entry to be trimmed.
-+	   N.B. This code demands that the overspill is contained in
-+	   a single sg entry.
-+	*/
-+
-+	host->drain_words = 0;
-+	if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {
-+		struct scatterlist *sg;
-+		u32 len;
-+		int i;
-+
-+		len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,
-+			  (u32)data->blocks * data->blksz);
-+
-+		for_each_sg(data->sg, sg, data->sg_len, i) {
-+			if (sg_is_last(sg)) {
-+				BUG_ON(sg->length < len);
-+				sg->length -= len;
-+				host->drain_page = sg_page(sg);
-+				host->drain_offset = sg->offset + sg->length;
-+			}
-+		}
-+		host->drain_words = len/4;
-+	}
-+
-+	/* The parameters have already been validated, so this will not fail */
-+	(void)dmaengine_slave_config(dma_chan,
-+				     (dir_data == DMA_FROM_DEVICE) ?
-+				     &host->dma_cfg_rx :
-+				     &host->dma_cfg_tx);
-+
-+	len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
-+			 dir_data);
-+
-+	log_event("PRD2", len, 0);
-+	if (len > 0)
-+		desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
-+					       len, dir_slave,
-+					       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+	log_event("PRD3", (u32)desc, 0);
-+
-+	if (desc) {
-+		desc->callback = bcm2835_sdhost_dma_complete;
-+		desc->callback_param = host;
-+		host->dma_desc = desc;
-+		host->dma_chan = dma_chan;
-+		host->dma_dir = dir_data;
-+	}
-+	log_event("PDM>", (u32)data, 0);
-+}
-+
-+static void bcm2835_sdhost_start_dma(struct bcm2835_host *host)
-+{
-+	log_event("SDMA", (u32)host->data, (u32)host->dma_chan);
-+	dmaengine_submit(host->dma_desc);
-+	dma_async_issue_pending(host->dma_chan);
-+}
-+
-+static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host)
-+{
-+	u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
-+		SDHCFG_BUSY_IRPT_EN;
-+	if (host->dma_desc)
-+		host->hcfg = (host->hcfg & ~all_irqs) |
-+			SDHCFG_BUSY_IRPT_EN;
-+	else
-+		host->hcfg = (host->hcfg & ~all_irqs) |
-+			SDHCFG_DATA_IRPT_EN |
-+			SDHCFG_BUSY_IRPT_EN;
-+
-+	bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+}
-+
-+static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
-+{
-+	struct mmc_data *data = cmd->data;
-+
-+	WARN_ON(host->data);
-+
-+	host->data = data;
-+	if (!data)
-+		return;
-+
-+	/* Sanity checks */
-+	BUG_ON(data->blksz * data->blocks > 524288);
-+	BUG_ON(data->blksz > host->mmc->max_blk_size);
-+	BUG_ON(data->blocks > 65535);
-+
-+	host->data_complete = 0;
-+	host->flush_fifo = 0;
-+	host->data->bytes_xfered = 0;
-+
-+	if (!host->sectors && host->mmc->card) {
-+		struct mmc_card *card = host->mmc->card;
-+		if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {
-+			/*
-+			 * The EXT_CSD sector count is in number of 512 byte
-+			 * sectors.
-+			 */
-+			host->sectors = card->ext_csd.sectors;
-+		} else {
-+			/*
-+			 * The CSD capacity field is in units of read_blkbits.
-+			 * set_capacity takes units of 512 bytes.
-+			 */
-+			host->sectors = card->csd.capacity <<
-+				(card->csd.read_blkbits - 9);
-+		}
-+	}
-+
-+	if (!host->dma_desc) {
-+		/* Use PIO */
-+		int flags = SG_MITER_ATOMIC;
-+
-+		if (data->flags & MMC_DATA_READ)
-+			flags |= SG_MITER_TO_SG;
-+		else
-+			flags |= SG_MITER_FROM_SG;
-+		sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
-+		host->blocks = data->blocks;
-+	}
-+
-+	bcm2835_sdhost_set_transfer_irqs(host);
-+
-+	bcm2835_sdhost_write(host, data->blksz, SDHBCT);
-+	bcm2835_sdhost_write(host, data->blocks, SDHBLC);
-+
-+	BUG_ON(!host->data);
-+}
-+
-+bool bcm2835_sdhost_send_command(struct bcm2835_host *host,
-+				 struct mmc_command *cmd)
-+{
-+	u32 sdcmd, sdhsts;
-+	unsigned long timeout;
-+	int delay;
-+
-+	WARN_ON(host->cmd);
-+	log_event("CMD<", cmd->opcode, cmd->arg);
-+
-+	if (cmd->data)
-+		pr_debug("%s: send_command %d 0x%x "
-+			 "(flags 0x%x) - %s %d*%d\n",
-+			 mmc_hostname(host->mmc),
-+			 cmd->opcode, cmd->arg, cmd->flags,
-+			 (cmd->data->flags & MMC_DATA_READ) ?
-+			 "read" : "write", cmd->data->blocks,
-+			 cmd->data->blksz);
-+	else
-+		pr_debug("%s: send_command %d 0x%x (flags 0x%x)\n",
-+			 mmc_hostname(host->mmc),
-+			 cmd->opcode, cmd->arg, cmd->flags);
-+
-+	/* Wait max 100 ms */
-+	timeout = 10000;
-+
-+	while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) {
-+		if (timeout == 0) {
-+			pr_warn("%s: previous command never completed.\n",
-+				mmc_hostname(host->mmc));
-+			if (host->debug)
-+				bcm2835_sdhost_dumpregs(host);
-+			cmd->error = -EILSEQ;
-+			tasklet_schedule(&host->finish_tasklet);
-+			return false;
-+		}
-+		timeout--;
-+		udelay(10);
-+	}
-+
-+	delay = (10000 - timeout)/100;
-+	if (delay > host->max_delay) {
-+		host->max_delay = delay;
-+		pr_warning("%s: controller hung for %d ms\n",
-+			   mmc_hostname(host->mmc),
-+			   host->max_delay);
-+	}
-+
-+	timeout = jiffies;
-+	if (!cmd->data && cmd->busy_timeout > 9000)
-+		timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
-+	else
-+		timeout += 10 * HZ;
-+	mod_timer(&host->timer, timeout);
-+
-+	host->cmd = cmd;
-+
-+	/* Clear any error flags */
-+	sdhsts = bcm2835_sdhost_read(host, SDHSTS);
-+	if (sdhsts & SDHSTS_ERROR_MASK)
-+		bcm2835_sdhost_write(host, sdhsts, SDHSTS);
-+
-+	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
-+		pr_err("%s: unsupported response type!\n",
-+			mmc_hostname(host->mmc));
-+		cmd->error = -EINVAL;
-+		tasklet_schedule(&host->finish_tasklet);
-+		return false;
-+	}
-+
-+	bcm2835_sdhost_prepare_data(host, cmd);
-+
-+	bcm2835_sdhost_write(host, cmd->arg, SDARG);
-+
-+	sdcmd = cmd->opcode & SDCMD_CMD_MASK;
-+
-+	host->use_busy = 0;
-+	if (!(cmd->flags & MMC_RSP_PRESENT)) {
-+		sdcmd |= SDCMD_NO_RESPONSE;
-+	} else {
-+		if (cmd->flags & MMC_RSP_136)
-+			sdcmd |= SDCMD_LONG_RESPONSE;
-+		if (cmd->flags & MMC_RSP_BUSY) {
-+			sdcmd |= SDCMD_BUSYWAIT;
-+			host->use_busy = 1;
-+		}
-+	}
-+
-+	if (cmd->data) {
-+		log_event("CMDD", cmd->data->blocks, cmd->data->blksz);
-+		if (host->delay_after_this_stop) {
-+			struct timeval now;
-+			int time_since_stop;
-+			do_gettimeofday(&now);
-+			time_since_stop = (now.tv_sec - host->stop_time.tv_sec);
-+			if (time_since_stop < 2) {
-+				/* Possibly less than one second */
-+				time_since_stop = time_since_stop * 1000000 +
-+					(now.tv_usec - host->stop_time.tv_usec);
-+				if (time_since_stop <
-+				    host->delay_after_this_stop)
-+					udelay(host->delay_after_this_stop -
-+					       time_since_stop);
-+			}
-+		}
-+
-+		host->delay_after_this_stop = host->delay_after_stop;
-+		if ((cmd->data->flags & MMC_DATA_READ) && !host->use_sbc) {
-+			/* See if read crosses one of the hazardous sectors */
-+			u32 first_blk, last_blk;
-+
-+			/* Intentionally include the following sector because
-+			   without CMD23/SBC the read may run on. */
-+			first_blk = host->mrq->cmd->arg;
-+			last_blk = first_blk + cmd->data->blocks;
-+
-+			if (((last_blk >= (host->sectors - 64)) &&
-+			     (first_blk <= (host->sectors - 64))) ||
-+			    ((last_blk >= (host->sectors - 32)) &&
-+			     (first_blk <= (host->sectors - 32)))) {
-+				host->delay_after_this_stop =
-+					max(250u, host->delay_after_stop);
-+			}
-+		}
-+
-+		if (cmd->data->flags & MMC_DATA_WRITE)
-+			sdcmd |= SDCMD_WRITE_CMD;
-+		if (cmd->data->flags & MMC_DATA_READ)
-+			sdcmd |= SDCMD_READ_CMD;
-+	}
-+
-+	bcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD);
-+
-+	return true;
-+}
-+
-+static void bcm2835_sdhost_finish_command(struct bcm2835_host *host,
-+					  unsigned long *irq_flags);
-+static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host);
-+
-+static void bcm2835_sdhost_finish_data(struct bcm2835_host *host)
-+{
-+	struct mmc_data *data;
-+
-+	data = host->data;
-+	BUG_ON(!data);
-+
-+	log_event("FDA<", (u32)host->mrq, (u32)host->cmd);
-+	pr_debug("finish_data(error %d, stop %d, sbc %d)\n",
-+	       data->error, data->stop ? 1 : 0,
-+	       host->mrq->sbc ? 1 : 0);
-+
-+	host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
-+	bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+
-+	data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);
-+
-+	host->data_complete = 1;
-+
-+	if (host->cmd) {
-+		/*
-+		 * Data managed to finish before the
-+		 * command completed. Make sure we do
-+		 * things in the proper order.
-+		 */
-+		pr_debug("Finished early - HSTS %x\n",
-+			 bcm2835_sdhost_read(host, SDHSTS));
-+	}
-+	else
-+		bcm2835_sdhost_transfer_complete(host);
-+	log_event("FDA>", (u32)host->mrq, (u32)host->cmd);
-+}
-+
-+static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host)
-+{
-+	struct mmc_data *data;
-+
-+	BUG_ON(host->cmd);
-+	BUG_ON(!host->data);
-+	BUG_ON(!host->data_complete);
-+
-+	data = host->data;
-+	host->data = NULL;
-+
-+	log_event("TCM<", (u32)data, data->error);
-+	pr_debug("transfer_complete(error %d, stop %d)\n",
-+	       data->error, data->stop ? 1 : 0);
-+
-+	/*
-+	 * Need to send CMD12 if -
-+	 * a) open-ended multiblock transfer (no CMD23)
-+	 * b) error in multiblock transfer
-+	 */
-+	if (host->mrq->stop && (data->error || !host->use_sbc)) {
-+		if (bcm2835_sdhost_send_command(host, host->mrq->stop)) {
-+			/* No busy, so poll for completion */
-+			if (!host->use_busy)
-+				bcm2835_sdhost_finish_command(host, NULL);
-+
-+			if (host->delay_after_this_stop)
-+				do_gettimeofday(&host->stop_time);
-+		}
-+	} else {
-+		bcm2835_sdhost_wait_transfer_complete(host);
-+		tasklet_schedule(&host->finish_tasklet);
-+	}
-+	log_event("TCM>", (u32)data, 0);
-+}
-+
-+/* If irq_flags is valid, the caller is in a thread context and is allowed
-+   to sleep */
-+static void bcm2835_sdhost_finish_command(struct bcm2835_host *host,
-+					  unsigned long *irq_flags)
-+{
-+	u32 sdcmd;
-+	u32 retries;
-+#ifdef DEBUG
-+	struct timeval before, after;
-+	int timediff = 0;
-+#endif
-+
-+	log_event("FCM<", (u32)host->mrq, (u32)host->cmd);
-+	pr_debug("finish_command(%x)\n", bcm2835_sdhost_read(host, SDCMD));
-+
-+	BUG_ON(!host->cmd || !host->mrq);
-+
-+	/* Poll quickly at first */
-+
-+	retries = host->cmd_quick_poll_retries;
-+	if (!retries) {
-+		/* Work out how many polls take 1us by timing 10us */
-+		struct timeval start, now;
-+		int us_diff;
-+
-+		retries = 1;
-+		do {
-+			int i;
-+
-+			retries *= 2;
-+
-+			do_gettimeofday(&start);
-+
-+			for (i = 0; i < retries; i++) {
-+				cpu_relax();
-+				sdcmd = bcm2835_sdhost_read(host, SDCMD);
-+			}
-+
-+			do_gettimeofday(&now);
-+			us_diff = (now.tv_sec - start.tv_sec) * 1000000 +
-+				(now.tv_usec - start.tv_usec);
-+		} while (us_diff < 10);
-+
-+		host->cmd_quick_poll_retries = ((retries * us_diff + 9)*CMD_DALLY_US)/10 + 1;
-+		retries = 1; // We've already waited long enough this time
-+	}
-+
-+	for (sdcmd = bcm2835_sdhost_read(host, SDCMD);
-+	     (sdcmd & SDCMD_NEW_FLAG) && retries;
-+	     retries--) {
-+		cpu_relax();
-+		sdcmd = bcm2835_sdhost_read(host, SDCMD);
-+	}
-+
-+	if (!retries) {
-+		unsigned long wait_max;
-+
-+		if (!irq_flags) {
-+			/* Schedule the work */
-+			log_event("CWWQ", 0, 0);
-+			schedule_work(&host->cmd_wait_wq);
-+			return;
-+		}
-+
-+		/* Wait max 100 ms */
-+		wait_max = jiffies + msecs_to_jiffies(100);
-+		while (time_before(jiffies, wait_max)) {
-+			spin_unlock_irqrestore(&host->lock, *irq_flags);
-+			usleep_range(1, 10);
-+			spin_lock_irqsave(&host->lock, *irq_flags);
-+			sdcmd = bcm2835_sdhost_read(host, SDCMD);
-+			if (!(sdcmd & SDCMD_NEW_FLAG))
-+				break;
-+		}
-+	}
-+
-+	/* Check for errors */
-+	if (sdcmd & SDCMD_NEW_FLAG) {
-+		if (host->debug) {
-+			pr_err("%s: command %d never completed.\n",
-+			       mmc_hostname(host->mmc), host->cmd->opcode);
-+			bcm2835_sdhost_dumpregs(host);
-+		}
-+		host->cmd->error = -EILSEQ;
-+		tasklet_schedule(&host->finish_tasklet);
-+		return;
-+	} else if (sdcmd & SDCMD_FAIL_FLAG) {
-+		u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
-+
-+		/* Clear the errors */
-+		bcm2835_sdhost_write(host, SDHSTS_ERROR_MASK, SDHSTS);
-+
-+		if (host->debug)
-+			pr_info("%s: error detected - CMD %x, HSTS %03x, EDM %x\n",
-+				mmc_hostname(host->mmc), sdcmd, sdhsts,
-+				bcm2835_sdhost_read(host, SDEDM));
-+
-+		if ((sdhsts & SDHSTS_CRC7_ERROR) &&
-+		    (host->cmd->opcode == 1)) {
-+			if (host->debug)
-+				pr_info("%s: ignoring CRC7 error for CMD1\n",
-+					mmc_hostname(host->mmc));
-+		} else {
-+			if (sdhsts & SDHSTS_CMD_TIME_OUT) {
-+				if (host->debug)
-+					pr_warn("%s: command %d timeout\n",
-+					       mmc_hostname(host->mmc),
-+					       host->cmd->opcode);
-+				host->cmd->error = -ETIMEDOUT;
-+			} else {
-+				pr_warn("%s: unexpected command %d error\n",
-+				       mmc_hostname(host->mmc),
-+				       host->cmd->opcode);
-+				host->cmd->error = -EILSEQ;
-+			}
-+			tasklet_schedule(&host->finish_tasklet);
-+			return;
-+		}
-+	}
-+
-+	if (host->cmd->flags & MMC_RSP_PRESENT) {
-+		if (host->cmd->flags & MMC_RSP_136) {
-+			int i;
-+			for (i = 0; i < 4; i++)
-+				host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4);
-+			pr_debug("%s: finish_command %08x %08x %08x %08x\n",
-+				 mmc_hostname(host->mmc),
-+				 host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]);
-+			log_event("RSP ", host->cmd->resp[0], host->cmd->resp[1]);
-+		} else {
-+			host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0);
-+			pr_debug("%s: finish_command %08x\n",
-+				 mmc_hostname(host->mmc),
-+				 host->cmd->resp[0]);
-+			log_event("RSP ", host->cmd->resp[0], 0);
-+		}
-+	}
-+
-+	if (host->cmd == host->mrq->sbc) {
-+		/* Finished CMD23, now send actual command. */
-+		host->cmd = NULL;
-+		if (bcm2835_sdhost_send_command(host, host->mrq->cmd)) {
-+			if (host->data && host->dma_desc)
-+				/* DMA transfer starts now, PIO starts after irq */
-+				bcm2835_sdhost_start_dma(host);
-+
-+			if (!host->use_busy)
-+				bcm2835_sdhost_finish_command(host, NULL);
-+		}
-+	} else if (host->cmd == host->mrq->stop) {
-+		/* Finished CMD12 */
-+		tasklet_schedule(&host->finish_tasklet);
-+	} else {
-+		/* Processed actual command. */
-+		host->cmd = NULL;
-+		if (!host->data)
-+			tasklet_schedule(&host->finish_tasklet);
-+		else if (host->data_complete)
-+			bcm2835_sdhost_transfer_complete(host);
-+	}
-+	log_event("FCM>", (u32)host->mrq, (u32)host->cmd);
-+}
-+
-+static void bcm2835_sdhost_timeout(unsigned long data)
-+{
-+	struct bcm2835_host *host;
-+	unsigned long flags;
-+
-+	host = (struct bcm2835_host *)data;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+	log_event("TIM<", 0, 0);
-+
-+	if (host->mrq) {
-+		pr_err("%s: timeout waiting for hardware interrupt.\n",
-+			mmc_hostname(host->mmc));
-+		log_dump();
-+		bcm2835_sdhost_dumpregs(host);
-+
-+		if (host->data) {
-+			host->data->error = -ETIMEDOUT;
-+			bcm2835_sdhost_finish_data(host);
-+		} else {
-+			if (host->cmd)
-+				host->cmd->error = -ETIMEDOUT;
-+			else
-+				host->mrq->cmd->error = -ETIMEDOUT;
-+
-+			pr_debug("timeout_timer tasklet_schedule\n");
-+			tasklet_schedule(&host->finish_tasklet);
-+		}
-+	}
-+
-+	mmiowb();
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+	log_event("IRQB", (u32)host->cmd, intmask);
-+	if (!host->cmd) {
-+		pr_err("%s: got command busy interrupt 0x%08x even "
-+			"though no command operation was in progress.\n",
-+			mmc_hostname(host->mmc), (unsigned)intmask);
-+		bcm2835_sdhost_dumpregs(host);
-+		return;
-+	}
-+
-+	if (!host->use_busy) {
-+		pr_err("%s: got command busy interrupt 0x%08x even "
-+			"though not expecting one.\n",
-+			mmc_hostname(host->mmc), (unsigned)intmask);
-+		bcm2835_sdhost_dumpregs(host);
-+		return;
-+	}
-+	host->use_busy = 0;
-+
-+	if (intmask & SDHSTS_ERROR_MASK)
-+	{
-+		pr_err("sdhost_busy_irq: intmask %x, data %p\n", intmask, host->mrq->data);
-+		if (intmask & SDHSTS_CRC7_ERROR)
-+			host->cmd->error = -EILSEQ;
-+		else if (intmask & (SDHSTS_CRC16_ERROR |
-+				    SDHSTS_FIFO_ERROR)) {
-+			if (host->mrq->data)
-+				host->mrq->data->error = -EILSEQ;
-+			else
-+				host->cmd->error = -EILSEQ;
-+		} else if (intmask & SDHSTS_REW_TIME_OUT) {
-+			if (host->mrq->data)
-+				host->mrq->data->error = -ETIMEDOUT;
-+			else
-+				host->cmd->error = -ETIMEDOUT;
-+		} else if (intmask & SDHSTS_CMD_TIME_OUT)
-+			host->cmd->error = -ETIMEDOUT;
-+
-+		if (host->debug) {
-+			log_dump();
-+			bcm2835_sdhost_dumpregs(host);
-+		}
-+	}
-+	else
-+		bcm2835_sdhost_finish_command(host, NULL);
-+}
-+
-+static void bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+	/* There are no dedicated data/space available interrupt
-+	   status bits, so it is necessary to use the single shared
-+	   data/space available FIFO status bits. It is therefore not
-+	   an error to get here when there is no data transfer in
-+	   progress. */
-+	log_event("IRQD", (u32)host->data, intmask);
-+	if (!host->data)
-+		return;
-+
-+	if (intmask & (SDHSTS_CRC16_ERROR |
-+		       SDHSTS_FIFO_ERROR |
-+		       SDHSTS_REW_TIME_OUT)) {
-+		if (intmask & (SDHSTS_CRC16_ERROR |
-+			       SDHSTS_FIFO_ERROR))
-+			host->data->error = -EILSEQ;
-+		else
-+			host->data->error = -ETIMEDOUT;
-+
-+		if (host->debug) {
-+			log_dump();
-+			bcm2835_sdhost_dumpregs(host);
-+		}
-+	}
-+
-+	if (host->data->error) {
-+		bcm2835_sdhost_finish_data(host);
-+	} else if (host->data->flags & MMC_DATA_WRITE) {
-+		/* Use the block interrupt for writes after the first block */
-+		host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
-+		host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
-+		bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+		bcm2835_sdhost_transfer_pio(host);
-+	} else {
-+		bcm2835_sdhost_transfer_pio(host);
-+		host->blocks--;
-+		if ((host->blocks == 0) || host->data->error)
-+			bcm2835_sdhost_finish_data(host);
-+	}
-+}
-+
-+static void bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask)
-+{
-+	log_event("IRQK", (u32)host->data, intmask);
-+	if (!host->data) {
-+		pr_err("%s: got block interrupt 0x%08x even "
-+			"though no data operation was in progress.\n",
-+			mmc_hostname(host->mmc), (unsigned)intmask);
-+		bcm2835_sdhost_dumpregs(host);
-+		return;
-+	}
-+
-+	if (intmask & (SDHSTS_CRC16_ERROR |
-+		       SDHSTS_FIFO_ERROR |
-+		       SDHSTS_REW_TIME_OUT)) {
-+		if (intmask & (SDHSTS_CRC16_ERROR |
-+			       SDHSTS_FIFO_ERROR))
-+			host->data->error = -EILSEQ;
-+		else
-+			host->data->error = -ETIMEDOUT;
-+
-+		if (host->debug) {
-+			log_dump();
-+			bcm2835_sdhost_dumpregs(host);
-+		}
-+	}
-+
-+	if (!host->dma_desc) {
-+		BUG_ON(!host->blocks);
-+		if (host->data->error || (--host->blocks == 0)) {
-+			bcm2835_sdhost_finish_data(host);
-+		} else {
-+			bcm2835_sdhost_transfer_pio(host);
-+		}
-+	} else if (host->data->flags & MMC_DATA_WRITE) {
-+		bcm2835_sdhost_finish_data(host);
-+	}
-+}
-+
-+static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id)
-+{
-+	irqreturn_t result = IRQ_NONE;
-+	struct bcm2835_host *host = dev_id;
-+	u32 intmask;
-+
-+	spin_lock(&host->lock);
-+
-+	intmask = bcm2835_sdhost_read(host, SDHSTS);
-+	log_event("IRQ<", intmask, 0);
-+
-+	bcm2835_sdhost_write(host,
-+			     SDHSTS_BUSY_IRPT |
-+			     SDHSTS_BLOCK_IRPT |
-+			     SDHSTS_SDIO_IRPT |
-+			     SDHSTS_DATA_FLAG,
-+			     SDHSTS);
-+
-+	if (intmask & SDHSTS_BLOCK_IRPT) {
-+		bcm2835_sdhost_block_irq(host, intmask);
-+		result = IRQ_HANDLED;
-+	}
-+
-+	if (intmask & SDHSTS_BUSY_IRPT) {
-+		bcm2835_sdhost_busy_irq(host, intmask);
-+		result = IRQ_HANDLED;
-+	}
-+
-+	/* There is no true data interrupt status bit, so it is
-+	   necessary to qualify the data flag with the interrupt
-+	   enable bit */
-+	if ((intmask & SDHSTS_DATA_FLAG) &&
-+	    (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
-+		bcm2835_sdhost_data_irq(host, intmask);
-+		result = IRQ_HANDLED;
-+	}
-+
-+	mmiowb();
-+
-+	log_event("IRQ>", bcm2835_sdhost_read(host, SDHSTS), 0);
-+	spin_unlock(&host->lock);
-+
-+	return result;
-+}
-+
-+void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock)
-+{
-+	int div = 0; /* Initialized for compiler warning */
-+	unsigned int input_clock = clock;
-+	unsigned long flags;
-+
-+	if (host->debug)
-+		pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock);
-+
-+	if ((host->overclock_50 > 50) &&
-+	    (clock == 50*MHZ))
-+		clock = host->overclock_50 * MHZ + (MHZ - 1);
-+
-+	/* The SDCDIV register has 11 bits, and holds (div - 2).
-+	   But in data mode the max is 50MHz wihout a minimum, and only the
-+	   bottom 3 bits are used. Since the switch over is automatic (unless
-+	   we have marked the card as slow...), chosen values have to make
-+	   sense in both modes.
-+	   Ident mode must be 100-400KHz, so can range check the requested
-+	   clock. CMD15 must be used to return to data mode, so this can be
-+	   monitored.
-+
-+	   clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
-+                           4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
-+
-+			 623->400KHz/27.8MHz
-+			 reset value (507)->491159/50MHz
-+
-+	   BUT, the 3-bit clock divisor in data mode is too small if the
-+	   core clock is higher than 250MHz, so instead use the SLOW_CARD
-+	   configuration bit to force the use of the ident clock divisor
-+	   at all times.
-+	*/
-+
-+	host->mmc->actual_clock = 0;
-+
-+	if (host->firmware_sets_cdiv) {
-+		u32 msg[3] = { clock, 0, 0 };
-+
-+		rpi_firmware_property(rpi_firmware_get(NULL),
-+				      RPI_FIRMWARE_SET_SDHOST_CLOCK,
-+				      &msg, sizeof(msg));
-+
-+		clock = max(msg[1], msg[2]);
-+		spin_lock_irqsave(&host->lock, flags);
-+	} else {
-+		spin_lock_irqsave(&host->lock, flags);
-+		if (clock < 100000) {
-+			/* Can't stop the clock, but make it as slow as
-+			 * possible to show willing
-+			 */
-+			host->cdiv = SDCDIV_MAX_CDIV;
-+			bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
-+			mmiowb();
-+			spin_unlock_irqrestore(&host->lock, flags);
-+			return;
-+		}
-+
-+		div = host->max_clk / clock;
-+		if (div < 2)
-+			div = 2;
-+		if ((host->max_clk / div) > clock)
-+			div++;
-+		div -= 2;
-+
-+		if (div > SDCDIV_MAX_CDIV)
-+			div = SDCDIV_MAX_CDIV;
-+
-+		clock = host->max_clk / (div + 2);
-+
-+		host->cdiv = div;
-+		bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
-+
-+		if (host->debug)
-+			pr_info("%s: clock=%d -> max_clk=%d, cdiv=%x "
-+				"(actual clock %d)\n",
-+				mmc_hostname(host->mmc), input_clock,
-+				host->max_clk, host->cdiv,
-+				clock);
-+	}
-+
-+	/* Calibrate some delays */
-+
-+	host->ns_per_fifo_word = (1000000000/clock) *
-+		((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);
-+
-+	if (input_clock == 50 * MHZ) {
-+		if (clock > input_clock) {
-+			/* Save the closest value, to make it easier
-+			   to reduce in the event of error */
-+			host->overclock_50 = (clock/MHZ);
-+
-+			if (clock != host->overclock) {
-+				pr_info("%s: overclocking to %dHz\n",
-+					mmc_hostname(host->mmc), clock);
-+				host->overclock = clock;
-+			}
-+		} else if (host->overclock) {
-+			host->overclock = 0;
-+			if (clock == 50 * MHZ)
-+				pr_warn("%s: cancelling overclock\n",
-+					mmc_hostname(host->mmc));
-+		}
-+	} else if (input_clock == 0) {
-+		/* Reset the preferred overclock when the clock is stopped.
-+		 * This always happens during initialisation. */
-+		host->overclock_50 = host->user_overclock_50;
-+		host->overclock = 0;
-+	}
-+
-+	/* Set the timeout to 500ms */
-+	bcm2835_sdhost_write(host, clock/2, SDTOUT);
-+
-+	host->mmc->actual_clock = clock;
-+	host->clock = input_clock;
-+	host->reset_clock = 0;
-+
-+	mmiowb();
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+	struct bcm2835_host *host;
-+	unsigned long flags;
-+	u32 edm, fsm;
-+
-+	host = mmc_priv(mmc);
-+
-+	if (host->debug) {
-+		struct mmc_command *cmd = mrq->cmd;
-+		BUG_ON(!cmd);
-+		if (cmd->data)
-+			pr_info("%s: cmd %d 0x%x (flags 0x%x) - %s %d*%d\n",
-+				mmc_hostname(mmc),
-+				cmd->opcode, cmd->arg, cmd->flags,
-+				(cmd->data->flags & MMC_DATA_READ) ?
-+				"read" : "write", cmd->data->blocks,
-+				cmd->data->blksz);
-+		else
-+			pr_info("%s: cmd %d 0x%x (flags 0x%x)\n",
-+				mmc_hostname(mmc),
-+				cmd->opcode, cmd->arg, cmd->flags);
-+	}
-+
-+	/* Reset the error statuses in case this is a retry */
-+	if (mrq->sbc)
-+		mrq->sbc->error = 0;
-+	if (mrq->cmd)
-+		mrq->cmd->error = 0;
-+	if (mrq->data)
-+		mrq->data->error = 0;
-+	if (mrq->stop)
-+		mrq->stop->error = 0;
-+
-+	if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
-+		pr_err("%s: unsupported block size (%d bytes)\n",
-+		       mmc_hostname(mmc), mrq->data->blksz);
-+		mrq->cmd->error = -EINVAL;
-+		mmc_request_done(mmc, mrq);
-+		return;
-+	}
-+
-+	if (host->use_dma && mrq->data &&
-+	    (mrq->data->blocks > host->pio_limit))
-+		bcm2835_sdhost_prepare_dma(host, mrq->data);
-+
-+	if (host->reset_clock)
-+	    bcm2835_sdhost_set_clock(host, host->clock);
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	WARN_ON(host->mrq != NULL);
-+	host->mrq = mrq;
-+
-+	edm = bcm2835_sdhost_read(host, SDEDM);
-+	fsm = edm & SDEDM_FSM_MASK;
-+
-+	log_event("REQ<", (u32)mrq, edm);
-+	if ((fsm != SDEDM_FSM_IDENTMODE) &&
-+	    (fsm != SDEDM_FSM_DATAMODE)) {
-+		log_event("REQ!", (u32)mrq, edm);
-+		if (host->debug) {
-+			pr_warn("%s: previous command (%d) not complete (EDM %x)\n",
-+			       mmc_hostname(host->mmc),
-+			       bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK,
-+			       edm);
-+			log_dump();
-+			bcm2835_sdhost_dumpregs(host);
-+		}
-+		mrq->cmd->error = -EILSEQ;
-+		tasklet_schedule(&host->finish_tasklet);
-+		mmiowb();
-+		spin_unlock_irqrestore(&host->lock, flags);
-+		return;
-+	}
-+
-+	host->use_sbc = !!mrq->sbc &&
-+		(host->mrq->data->flags & USE_CMD23_FLAGS);
-+	if (host->use_sbc) {
-+		if (bcm2835_sdhost_send_command(host, mrq->sbc)) {
-+			if (!host->use_busy)
-+				bcm2835_sdhost_finish_command(host, &flags);
-+		}
-+	} else if (bcm2835_sdhost_send_command(host, mrq->cmd)) {
-+		if (host->data && host->dma_desc)
-+			/* DMA transfer starts now, PIO starts after irq */
-+			bcm2835_sdhost_start_dma(host);
-+
-+		if (!host->use_busy)
-+			bcm2835_sdhost_finish_command(host, &flags);
-+	}
-+
-+	log_event("CMD ", (u32)mrq->cmd->opcode,
-+		   mrq->data ? (u32)mrq->data->blksz : 0);
-+	mmiowb();
-+
-+	log_event("REQ>", (u32)mrq, 0);
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
-+{
-+
-+	struct bcm2835_host *host = mmc_priv(mmc);
-+	unsigned long flags;
-+
-+	if (host->debug)
-+		pr_info("%s: ios clock %d, pwr %d, bus_width %d, "
-+			"timing %d, vdd %d, drv_type %d\n",
-+			mmc_hostname(mmc),
-+			ios->clock, ios->power_mode, ios->bus_width,
-+			ios->timing, ios->signal_voltage, ios->drv_type);
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	log_event("IOS<", ios->clock, 0);
-+
-+	/* set bus width */
-+	host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
-+	if (ios->bus_width == MMC_BUS_WIDTH_4)
-+		host->hcfg |= SDHCFG_WIDE_EXT_BUS;
-+
-+	host->hcfg |= SDHCFG_WIDE_INT_BUS;
-+
-+	/* Disable clever clock switching, to cope with fast core clocks */
-+	host->hcfg |= SDHCFG_SLOW_CARD;
-+
-+	bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
-+
-+	mmiowb();
-+
-+	spin_unlock_irqrestore(&host->lock, flags);
-+
-+	if (!ios->clock || ios->clock != host->clock)
-+		bcm2835_sdhost_set_clock(host, ios->clock);
-+}
-+
-+static struct mmc_host_ops bcm2835_sdhost_ops = {
-+	.request = bcm2835_sdhost_request,
-+	.set_ios = bcm2835_sdhost_set_ios,
-+	.hw_reset = bcm2835_sdhost_reset,
-+};
-+
-+static void bcm2835_sdhost_cmd_wait_work(struct work_struct *work)
-+{
-+	struct bcm2835_host *host;
-+	unsigned long flags;
-+
-+	host = container_of(work, struct bcm2835_host, cmd_wait_wq);
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	log_event("CWK<", (u32)host->cmd, (u32)host->mrq);
-+
-+	/*
-+	 * If this tasklet gets rescheduled while running, it will
-+	 * be run again afterwards but without any active request.
-+	 */
-+	if (!host->mrq) {
-+		spin_unlock_irqrestore(&host->lock, flags);
-+		return;
-+	}
-+
-+	bcm2835_sdhost_finish_command(host, &flags);
-+
-+	mmiowb();
-+
-+	log_event("CWK>", (u32)host->cmd, 0);
-+
-+	spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
-+static void bcm2835_sdhost_tasklet_finish(unsigned long param)
-+{
-+	struct bcm2835_host *host;
-+	unsigned long flags;
-+	struct mmc_request *mrq;
-+	struct dma_chan *terminate_chan = NULL;
-+
-+	host = (struct bcm2835_host *)param;
-+
-+	spin_lock_irqsave(&host->lock, flags);
-+
-+	log_event("TSK<", (u32)host->mrq, 0);
-+	/*
-+	 * If this tasklet gets rescheduled while running, it will
-+	 * be run again afterwards but without any active request.
-+	 */
-+	if (!host->mrq) {
-+		spin_unlock_irqrestore(&host->lock, flags);
-+		return;
-+	}
-+
-+	del_timer(&host->timer);
-+
-+	mrq = host->mrq;
-+
-+	/* Drop the overclock after any data corruption, or after any
-+	 * error while overclocked. Ignore errors for status commands,
-+	 * as they are likely when a card is ejected. */
-+	if (host->overclock) {
-+		if ((mrq->cmd && mrq->cmd->error &&
-+		     (mrq->cmd->opcode != MMC_SEND_STATUS)) ||
-+		    (mrq->data && mrq->data->error) ||
-+		    (mrq->stop && mrq->stop->error) ||
-+		    (mrq->sbc && mrq->sbc->error)) {
-+			host->overclock_50--;
-+			pr_warn("%s: reducing overclock due to errors\n",
-+				mmc_hostname(host->mmc));
-+			host->reset_clock = 1;
-+			mrq->cmd->error = -ETIMEDOUT;
-+			mrq->cmd->retries = 1;
-+		}
-+	}
-+
-+	host->mrq = NULL;
-+	host->cmd = NULL;
-+	host->data = NULL;
-+
-+	mmiowb();
-+
-+	host->dma_desc = NULL;
-+	terminate_chan = host->dma_chan;
-+	host->dma_chan = NULL;
-+
-+	spin_unlock_irqrestore(&host->lock, flags);
-+
-+	if (terminate_chan)
-+	{
-+		int err = dmaengine_terminate_all(terminate_chan);
-+		if (err)
-+			pr_err("%s: failed to terminate DMA (%d)\n",
-+			       mmc_hostname(host->mmc), err);
-+	}
-+
-+	/* The SDHOST block doesn't report any errors for a disconnected
-+	   interface. All cards and SDIO devices should report some supported
-+	   voltage range, so a zero response to SEND_OP_COND, IO_SEND_OP_COND
-+	   or APP_SEND_OP_COND can be treated as an error. */
-+	if (((mrq->cmd->opcode == MMC_SEND_OP_COND) ||
-+	     (mrq->cmd->opcode == SD_IO_SEND_OP_COND) ||
-+	     (mrq->cmd->opcode == SD_APP_OP_COND)) &&
-+	    (mrq->cmd->error == 0) &&
-+	    (mrq->cmd->resp[0] == 0)) {
-+		mrq->cmd->error = -ETIMEDOUT;
-+		if (host->debug)
-+			pr_info("%s: faking timeout due to zero OCR\n",
-+				mmc_hostname(host->mmc));
-+	}
-+
-+	mmc_request_done(host->mmc, mrq);
-+	log_event("TSK>", (u32)mrq, 0);
-+}
-+
-+int bcm2835_sdhost_add_host(struct bcm2835_host *host)
-+{
-+	struct mmc_host *mmc;
-+	struct dma_slave_config cfg;
-+	char pio_limit_string[20];
-+	int ret;
-+
-+	mmc = host->mmc;
-+
-+	mmc->f_max = host->max_clk;
-+	mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
-+
-+	mmc->max_busy_timeout =  (~(unsigned int)0)/(mmc->f_max/1000);
-+
-+	pr_debug("f_max %d, f_min %d, max_busy_timeout %d\n",
-+		 mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
-+
-+	/* host controller capabilities */
-+	mmc->caps |=
-+		MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
-+		MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE |
-+		((ALLOW_CMD23_READ|ALLOW_CMD23_WRITE) * MMC_CAP_CMD23);
-+
-+	spin_lock_init(&host->lock);
-+
-+	if (host->allow_dma) {
-+		if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {
-+			pr_err("%s: unable to initialise DMA channel. "
-+			       "Falling back to PIO\n",
-+			       mmc_hostname(mmc));
-+			host->use_dma = false;
-+		} else {
-+			cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+			cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+			cfg.slave_id = 13;		/* DREQ channel */
-+
-+			/* Validate the slave configurations */
-+
-+			cfg.direction = DMA_MEM_TO_DEV;
-+			cfg.src_addr = 0;
-+			cfg.dst_addr = host->bus_addr + SDDATA;
-+
-+			ret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);
-+
-+			if (ret == 0) {
-+				host->dma_cfg_tx = cfg;
-+
-+				cfg.direction = DMA_DEV_TO_MEM;
-+				cfg.src_addr = host->bus_addr + SDDATA;
-+				cfg.dst_addr = 0;
-+
-+				ret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);
-+			}
-+
-+			if (ret == 0) {
-+				host->dma_cfg_rx = cfg;
-+
-+				host->use_dma = true;
-+			} else {
-+				pr_err("%s: unable to configure DMA channel. "
-+				       "Falling back to PIO\n",
-+				       mmc_hostname(mmc));
-+				dma_release_channel(host->dma_chan_rxtx);
-+				host->dma_chan_rxtx = NULL;
-+				host->use_dma = false;
-+			}
-+		}
-+	} else {
-+		host->use_dma = false;
-+	}
-+
-+	mmc->max_segs = 128;
-+	mmc->max_req_size = 524288;
-+	mmc->max_seg_size = mmc->max_req_size;
-+	mmc->max_blk_size = 512;
-+	mmc->max_blk_count =  65535;
-+
-+	/* report supported voltage ranges */
-+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
-+
-+	tasklet_init(&host->finish_tasklet,
-+		bcm2835_sdhost_tasklet_finish, (unsigned long)host);
-+
-+	INIT_WORK(&host->cmd_wait_wq, bcm2835_sdhost_cmd_wait_work);
-+
-+	setup_timer(&host->timer, bcm2835_sdhost_timeout,
-+		    (unsigned long)host);
-+
-+	bcm2835_sdhost_init(host, 0);
-+
-+	ret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/,
-+				  mmc_hostname(mmc), host);
-+	if (ret) {
-+		pr_err("%s: failed to request IRQ %d: %d\n",
-+		       mmc_hostname(mmc), host->irq, ret);
-+		goto untasklet;
-+	}
-+
-+	mmiowb();
-+	mmc_add_host(mmc);
-+
-+	pio_limit_string[0] = '\0';
-+	if (host->use_dma && (host->pio_limit > 0))
-+		sprintf(pio_limit_string, " (>%d)", host->pio_limit);
-+	pr_info("%s: %s loaded - DMA %s%s\n",
-+		mmc_hostname(mmc), DRIVER_NAME,
-+		host->use_dma ? "enabled" : "disabled",
-+		pio_limit_string);
-+
-+	return 0;
-+
-+untasklet:
-+	tasklet_kill(&host->finish_tasklet);
-+
-+	return ret;
-+}
-+
-+static int bcm2835_sdhost_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct device_node *node = dev->of_node;
-+	struct clk *clk;
-+	struct resource *iomem;
-+	struct bcm2835_host *host;
-+	struct mmc_host *mmc;
-+	const __be32 *addr;
-+	u32 msg[3];
-+	int ret;
-+
-+	pr_debug("bcm2835_sdhost_probe\n");
-+	mmc = mmc_alloc_host(sizeof(*host), dev);
-+	if (!mmc)
-+		return -ENOMEM;
-+
-+	mmc->ops = &bcm2835_sdhost_ops;
-+	host = mmc_priv(mmc);
-+	host->mmc = mmc;
-+	host->pio_timeout = msecs_to_jiffies(500);
-+	host->pio_limit = 1;
-+	host->max_delay = 1; /* Warn if over 1ms */
-+	host->allow_dma = 1;
-+	spin_lock_init(&host->lock);
-+
-+	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	host->ioaddr = devm_ioremap_resource(dev, iomem);
-+	if (IS_ERR(host->ioaddr)) {
-+		ret = PTR_ERR(host->ioaddr);
-+		goto err;
-+	}
-+
-+	addr = of_get_address(node, 0, NULL, NULL);
-+	if (!addr) {
-+		dev_err(dev, "could not get DMA-register address\n");
-+		return -ENODEV;
-+	}
-+	host->bus_addr = be32_to_cpup(addr);
-+	pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n",
-+		 (unsigned long)host->ioaddr,
-+		 (unsigned long)iomem->start,
-+		 (unsigned long)host->bus_addr);
-+
-+	if (node) {
-+		/* Read any custom properties */
-+		of_property_read_u32(node,
-+				     "brcm,delay-after-stop",
-+				     &host->delay_after_stop);
-+		of_property_read_u32(node,
-+				     "brcm,overclock-50",
-+				     &host->user_overclock_50);
-+		of_property_read_u32(node,
-+				     "brcm,pio-limit",
-+				     &host->pio_limit);
-+		host->allow_dma =
-+			!of_property_read_bool(node, "brcm,force-pio");
-+		host->debug = of_property_read_bool(node, "brcm,debug");
-+	}
-+
-+	host->dma_chan = NULL;
-+	host->dma_desc = NULL;
-+
-+	/* Formally recognise the other way of disabling DMA */
-+	if (host->pio_limit == 0x7fffffff)
-+		host->allow_dma = false;
-+
-+	if (host->allow_dma) {
-+		if (node) {
-+			host->dma_chan_rxtx =
-+				dma_request_slave_channel(dev, "rx-tx");
-+			if (!host->dma_chan_rxtx)
-+				host->dma_chan_rxtx =
-+					dma_request_slave_channel(dev, "tx");
-+			if (!host->dma_chan_rxtx)
-+				host->dma_chan_rxtx =
-+					dma_request_slave_channel(dev, "rx");
-+		} else {
-+			dma_cap_mask_t mask;
-+
-+			dma_cap_zero(mask);
-+			/* we don't care about the channel, any would work */
-+			dma_cap_set(DMA_SLAVE, mask);
-+			host->dma_chan_rxtx =
-+				dma_request_channel(mask, NULL, NULL);
-+		}
-+	}
-+
-+	clk = devm_clk_get(dev, NULL);
-+	if (IS_ERR(clk)) {
-+		ret = PTR_ERR(clk);
-+		if (ret == -EPROBE_DEFER)
-+			dev_info(dev, "could not get clk, deferring probe\n");
-+		else
-+			dev_err(dev, "could not get clk\n");
-+		goto err;
-+	}
-+
-+	host->max_clk = clk_get_rate(clk);
-+
-+	host->irq = platform_get_irq(pdev, 0);
-+	if (host->irq <= 0) {
-+		dev_err(dev, "get IRQ failed\n");
-+		ret = -EINVAL;
-+		goto err;
-+	}
-+
-+	pr_debug(" - max_clk %lx, irq %d\n",
-+		 (unsigned long)host->max_clk,
-+		 (int)host->irq);
-+
-+	log_init(dev, iomem->start - host->bus_addr);
-+
-+	if (node)
-+		mmc_of_parse(mmc);
-+	else
-+		mmc->caps |= MMC_CAP_4_BIT_DATA;
-+
-+	msg[0] = 0;
-+	msg[1] = ~0;
-+	msg[2] = ~0;
-+
-+	rpi_firmware_property(rpi_firmware_get(NULL),
-+			      RPI_FIRMWARE_SET_SDHOST_CLOCK,
-+			      &msg, sizeof(msg));
-+
-+	host->firmware_sets_cdiv = (msg[1] != ~0);
-+
-+	ret = bcm2835_sdhost_add_host(host);
-+	if (ret)
-+		goto err;
-+
-+	platform_set_drvdata(pdev, host);
-+
-+	pr_debug("bcm2835_sdhost_probe -> OK\n");
-+
-+	return 0;
-+
-+err:
-+	pr_debug("bcm2835_sdhost_probe -> err %d\n", ret);
-+	mmc_free_host(mmc);
-+
-+	return ret;
-+}
-+
-+static int bcm2835_sdhost_remove(struct platform_device *pdev)
-+{
-+	struct bcm2835_host *host = platform_get_drvdata(pdev);
-+
-+	pr_debug("bcm2835_sdhost_remove\n");
-+
-+	mmc_remove_host(host->mmc);
-+
-+	bcm2835_sdhost_set_power(host, false);
-+
-+	free_irq(host->irq, host);
-+
-+	del_timer_sync(&host->timer);
-+
-+	tasklet_kill(&host->finish_tasklet);
-+
-+	mmc_free_host(host->mmc);
-+	platform_set_drvdata(pdev, NULL);
-+
-+	pr_debug("bcm2835_sdhost_remove - OK\n");
-+	return 0;
-+}
-+
-+static const struct of_device_id bcm2835_sdhost_match[] = {
-+	{ .compatible = "brcm,bcm2835-sdhost" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match);
-+
-+static struct platform_driver bcm2835_sdhost_driver = {
-+	.probe      = bcm2835_sdhost_probe,
-+	.remove     = bcm2835_sdhost_remove,
-+	.driver     = {
-+		.name		= DRIVER_NAME,
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= bcm2835_sdhost_match,
-+	},
-+};
-+module_platform_driver(bcm2835_sdhost_driver);
-+
-+MODULE_ALIAS("platform:sdhost-bcm2835");
-+MODULE_DESCRIPTION("BCM2835 SDHost driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Phil Elwell");
diff --git a/target/linux/brcm2708/patches-4.14/950-0042-vc_mem-Add-vc_mem-driver-for-querying-firmware-memor.patch b/target/linux/brcm2708/patches-4.14/950-0042-vc_mem-Add-vc_mem-driver-for-querying-firmware-memor.patch
deleted file mode 100644
index d357d6a66..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0042-vc_mem-Add-vc_mem-driver-for-querying-firmware-memor.patch
+++ /dev/null
@@ -1,515 +0,0 @@
-From 43f40efdd02431bdbf5d90418af2d6cc17b08db5 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Fri, 28 Oct 2016 15:36:43 +0100
-Subject: [PATCH 042/454] vc_mem: Add vc_mem driver for querying firmware
- memory addresses
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
-
-BCM270x: Move vc_mem
-
-Make the vc_mem module available for ARCH_BCM2835 by moving it.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/char/broadcom/Kconfig   |  18 ++
- drivers/char/broadcom/Makefile  |   1 +
- drivers/char/broadcom/vc_mem.c  | 422 ++++++++++++++++++++++++++++++++
- include/linux/broadcom/vc_mem.h |  35 +++
- 4 files changed, 476 insertions(+)
- create mode 100644 drivers/char/broadcom/Kconfig
- create mode 100644 drivers/char/broadcom/Makefile
- create mode 100644 drivers/char/broadcom/vc_mem.c
- create mode 100644 include/linux/broadcom/vc_mem.h
-
---- /dev/null
-+++ b/drivers/char/broadcom/Kconfig
-@@ -0,0 +1,18 @@
-+#
-+# Broadcom char driver config
-+#
-+
-+menuconfig BRCM_CHAR_DRIVERS
-+	bool "Broadcom Char Drivers"
-+	help
-+	  Broadcom's char drivers
-+
-+if BRCM_CHAR_DRIVERS
-+
-+config BCM2708_VCMEM
-+	bool "Videocore Memory"
-+        default y
-+        help
-+          Helper for videocore memory access and total size allocation.
-+
-+endif
---- /dev/null
-+++ b/drivers/char/broadcom/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_BCM2708_VCMEM)	+= vc_mem.o
---- /dev/null
-+++ b/drivers/char/broadcom/vc_mem.c
-@@ -0,0 +1,422 @@
-+/*****************************************************************************
-+* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/fs.h>
-+#include <linux/device.h>
-+#include <linux/cdev.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/debugfs.h>
-+#include <linux/uaccess.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/broadcom/vc_mem.h>
-+
-+#define DRIVER_NAME  "vc-mem"
-+
-+// Device (/dev) related variables
-+static dev_t vc_mem_devnum = 0;
-+static struct class *vc_mem_class = NULL;
-+static struct cdev vc_mem_cdev;
-+static int vc_mem_inited = 0;
-+
-+#ifdef CONFIG_DEBUG_FS
-+static struct dentry *vc_mem_debugfs_entry;
-+#endif
-+
-+/*
-+ * Videocore memory addresses and size
-+ *
-+ * Drivers that wish to know the videocore memory addresses and sizes should
-+ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
-+ * headers. This allows the other drivers to not be tied down to a a certain
-+ * address/size at compile time.
-+ *
-+ * In the future, the goal is to have the videocore memory virtual address and
-+ * size be calculated at boot time rather than at compile time. The decision of
-+ * where the videocore memory resides and its size would be in the hands of the
-+ * bootloader (and/or kernel). When that happens, the values of these variables
-+ * would be calculated and assigned in the init function.
-+ */
-+// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
-+unsigned long mm_vc_mem_phys_addr = 0x00000000;
-+unsigned int mm_vc_mem_size = 0;
-+unsigned int mm_vc_mem_base = 0;
-+
-+EXPORT_SYMBOL(mm_vc_mem_phys_addr);
-+EXPORT_SYMBOL(mm_vc_mem_size);
-+EXPORT_SYMBOL(mm_vc_mem_base);
-+
-+static uint phys_addr = 0;
-+static uint mem_size = 0;
-+static uint mem_base = 0;
-+
-+
-+/****************************************************************************
-+*
-+*   vc_mem_open
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_open(struct inode *inode, struct file *file)
-+{
-+	(void) inode;
-+	(void) file;
-+
-+	pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+	return 0;
-+}
-+
-+/****************************************************************************
-+*
-+*   vc_mem_release
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_release(struct inode *inode, struct file *file)
-+{
-+	(void) inode;
-+	(void) file;
-+
-+	pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+	return 0;
-+}
-+
-+/****************************************************************************
-+*
-+*   vc_mem_get_size
-+*
-+***************************************************************************/
-+
-+static void
-+vc_mem_get_size(void)
-+{
-+}
-+
-+/****************************************************************************
-+*
-+*   vc_mem_get_base
-+*
-+***************************************************************************/
-+
-+static void
-+vc_mem_get_base(void)
-+{
-+}
-+
-+/****************************************************************************
-+*
-+*   vc_mem_get_current_size
-+*
-+***************************************************************************/
-+
-+int
-+vc_mem_get_current_size(void)
-+{
-+	return mm_vc_mem_size;
-+}
-+
-+EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
-+
-+/****************************************************************************
-+*
-+*   vc_mem_ioctl
-+*
-+***************************************************************************/
-+
-+static long
-+vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+	int rc = 0;
-+
-+	(void) cmd;
-+	(void) arg;
-+
-+	pr_debug("%s: called file = 0x%p\n", __func__, file);
-+
-+	switch (cmd) {
-+	case VC_MEM_IOC_MEM_PHYS_ADDR:
-+		{
-+			pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
-+				__func__, (void *) mm_vc_mem_phys_addr);
-+
-+			if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
-+					 sizeof (mm_vc_mem_phys_addr)) != 0) {
-+				rc = -EFAULT;
-+			}
-+			break;
-+		}
-+	case VC_MEM_IOC_MEM_SIZE:
-+		{
-+			// Get the videocore memory size first
-+			vc_mem_get_size();
-+
-+			pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
-+				mm_vc_mem_size);
-+
-+			if (copy_to_user((void *) arg, &mm_vc_mem_size,
-+					 sizeof (mm_vc_mem_size)) != 0) {
-+				rc = -EFAULT;
-+			}
-+			break;
-+		}
-+	case VC_MEM_IOC_MEM_BASE:
-+		{
-+			// Get the videocore memory base
-+			vc_mem_get_base();
-+
-+			pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
-+				mm_vc_mem_base);
-+
-+			if (copy_to_user((void *) arg, &mm_vc_mem_base,
-+					 sizeof (mm_vc_mem_base)) != 0) {
-+				rc = -EFAULT;
-+			}
-+			break;
-+		}
-+	case VC_MEM_IOC_MEM_LOAD:
-+		{
-+			// Get the videocore memory base
-+			vc_mem_get_base();
-+
-+			pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
-+				mm_vc_mem_base);
-+
-+			if (copy_to_user((void *) arg, &mm_vc_mem_base,
-+					 sizeof (mm_vc_mem_base)) != 0) {
-+				rc = -EFAULT;
-+			}
-+			break;
-+		}
-+	default:
-+		{
-+			return -ENOTTY;
-+		}
-+	}
-+	pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
-+
-+	return rc;
-+}
-+
-+/****************************************************************************
-+*
-+*   vc_mem_mmap
-+*
-+***************************************************************************/
-+
-+static int
-+vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
-+{
-+	int rc = 0;
-+	unsigned long length = vma->vm_end - vma->vm_start;
-+	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
-+
-+	pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
-+		__func__, (long) vma->vm_start, (long) vma->vm_end,
-+		(long) vma->vm_pgoff);
-+
-+	if (offset + length > mm_vc_mem_size) {
-+		pr_err("%s: length %ld is too big\n", __func__, length);
-+		return -EINVAL;
-+	}
-+	// Do not cache the memory map
-+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-+
-+	rc = remap_pfn_range(vma, vma->vm_start,
-+			     (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
-+			     vma->vm_pgoff, length, vma->vm_page_prot);
-+	if (rc != 0) {
-+		pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
-+	}
-+
-+	return rc;
-+}
-+
-+/****************************************************************************
-+*
-+*   File Operations for the driver.
-+*
-+***************************************************************************/
-+
-+static const struct file_operations vc_mem_fops = {
-+	.owner = THIS_MODULE,
-+	.open = vc_mem_open,
-+	.release = vc_mem_release,
-+	.unlocked_ioctl = vc_mem_ioctl,
-+	.mmap = vc_mem_mmap,
-+};
-+
-+#ifdef CONFIG_DEBUG_FS
-+static void vc_mem_debugfs_deinit(void)
-+{
-+	debugfs_remove_recursive(vc_mem_debugfs_entry);
-+	vc_mem_debugfs_entry = NULL;
-+}
-+
-+
-+static int vc_mem_debugfs_init(
-+	struct device *dev)
-+{
-+	vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
-+	if (!vc_mem_debugfs_entry) {
-+		dev_warn(dev, "could not create debugfs entry\n");
-+		return -EFAULT;
-+	}
-+
-+	if (!debugfs_create_x32("vc_mem_phys_addr",
-+				0444,
-+				vc_mem_debugfs_entry,
-+				(u32 *)&mm_vc_mem_phys_addr)) {
-+		dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
-+			__func__);
-+		goto fail;
-+	}
-+
-+	if (!debugfs_create_x32("vc_mem_size",
-+				0444,
-+				vc_mem_debugfs_entry,
-+				(u32 *)&mm_vc_mem_size)) {
-+		dev_warn(dev, "%s:could not create vc_mem_size entry\n",
-+			__func__);
-+		goto fail;
-+	}
-+
-+	if (!debugfs_create_x32("vc_mem_base",
-+				0444,
-+				vc_mem_debugfs_entry,
-+				(u32 *)&mm_vc_mem_base)) {
-+		dev_warn(dev, "%s:could not create vc_mem_base entry\n",
-+			 __func__);
-+		goto fail;
-+	}
-+
-+	return 0;
-+
-+fail:
-+	vc_mem_debugfs_deinit();
-+	return -EFAULT;
-+}
-+
-+#endif /* CONFIG_DEBUG_FS */
-+
-+
-+/****************************************************************************
-+*
-+*   vc_mem_init
-+*
-+***************************************************************************/
-+
-+static int __init
-+vc_mem_init(void)
-+{
-+	int rc = -EFAULT;
-+	struct device *dev;
-+
-+	pr_debug("%s: called\n", __func__);
-+
-+	mm_vc_mem_phys_addr = phys_addr;
-+	mm_vc_mem_size = mem_size;
-+	mm_vc_mem_base = mem_base;
-+
-+	vc_mem_get_size();
-+
-+	pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
-+		mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
-+
-+	if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
-+		pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
-+		       __func__, rc);
-+		goto out_err;
-+	}
-+
-+	cdev_init(&vc_mem_cdev, &vc_mem_fops);
-+	if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
-+		pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
-+		goto out_unregister;
-+	}
-+
-+	vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
-+	if (IS_ERR(vc_mem_class)) {
-+		rc = PTR_ERR(vc_mem_class);
-+		pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
-+		goto out_cdev_del;
-+	}
-+
-+	dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
-+			    DRIVER_NAME);
-+	if (IS_ERR(dev)) {
-+		rc = PTR_ERR(dev);
-+		pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
-+		goto out_class_destroy;
-+	}
-+
-+#ifdef CONFIG_DEBUG_FS
-+	/* don't fail if the debug entries cannot be created */
-+	vc_mem_debugfs_init(dev);
-+#endif
-+
-+	vc_mem_inited = 1;
-+	return 0;
-+
-+	device_destroy(vc_mem_class, vc_mem_devnum);
-+
-+      out_class_destroy:
-+	class_destroy(vc_mem_class);
-+	vc_mem_class = NULL;
-+
-+      out_cdev_del:
-+	cdev_del(&vc_mem_cdev);
-+
-+      out_unregister:
-+	unregister_chrdev_region(vc_mem_devnum, 1);
-+
-+      out_err:
-+	return -1;
-+}
-+
-+/****************************************************************************
-+*
-+*   vc_mem_exit
-+*
-+***************************************************************************/
-+
-+static void __exit
-+vc_mem_exit(void)
-+{
-+	pr_debug("%s: called\n", __func__);
-+
-+	if (vc_mem_inited) {
-+#if CONFIG_DEBUG_FS
-+		vc_mem_debugfs_deinit();
-+#endif
-+		device_destroy(vc_mem_class, vc_mem_devnum);
-+		class_destroy(vc_mem_class);
-+		cdev_del(&vc_mem_cdev);
-+		unregister_chrdev_region(vc_mem_devnum, 1);
-+	}
-+}
-+
-+module_init(vc_mem_init);
-+module_exit(vc_mem_exit);
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Broadcom Corporation");
-+
-+module_param(phys_addr, uint, 0644);
-+module_param(mem_size, uint, 0644);
-+module_param(mem_base, uint, 0644);
---- /dev/null
-+++ b/include/linux/broadcom/vc_mem.h
-@@ -0,0 +1,35 @@
-+/*****************************************************************************
-+* Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.
-+*
-+* Unless you and Broadcom execute a separate written software license
-+* agreement governing use of this software, this software is licensed to you
-+* under the terms of the GNU General Public License version 2, available at
-+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+* Notwithstanding the above, under no circumstances may you combine this
-+* software in any way with any other Broadcom software provided under a
-+* license other than the GPL, without Broadcom's express prior written
-+* consent.
-+*****************************************************************************/
-+
-+#ifndef _VC_MEM_H
-+#define _VC_MEM_H
-+
-+#include <linux/ioctl.h>
-+
-+#define VC_MEM_IOC_MAGIC  'v'
-+
-+#define VC_MEM_IOC_MEM_PHYS_ADDR    _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
-+#define VC_MEM_IOC_MEM_SIZE         _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
-+#define VC_MEM_IOC_MEM_BASE         _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
-+#define VC_MEM_IOC_MEM_LOAD         _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
-+
-+#if defined( __KERNEL__ )
-+#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
-+
-+extern unsigned long mm_vc_mem_phys_addr;
-+extern unsigned int  mm_vc_mem_size;
-+extern int vc_mem_get_current_size( void );
-+#endif
-+
-+#endif  /* _VC_MEM_H */
diff --git a/target/linux/brcm2708/patches-4.14/950-0043-vcsm-VideoCore-shared-memory-service-for-BCM2835.patch b/target/linux/brcm2708/patches-4.14/950-0043-vcsm-VideoCore-shared-memory-service-for-BCM2835.patch
deleted file mode 100644
index 40bf53ec4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0043-vcsm-VideoCore-shared-memory-service-for-BCM2835.patch
+++ /dev/null
@@ -1,4851 +0,0 @@
-From af66401c883e2b3d23d20687ebd05cbc8878404e Mon Sep 17 00:00:00 2001
-From: Tim Gover <tgover@broadcom.com>
-Date: Tue, 22 Jul 2014 15:41:04 +0100
-Subject: [PATCH 043/454] vcsm: VideoCore shared memory service for BCM2835
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add experimental support for the VideoCore shared memory service.
-This allows user processes to allocate memory from VideoCore's
-GPU relocatable heap and mmap the buffers. Additionally, the memory
-handles can passed to other VideoCore services such as MMAL, OpenMax
-and DispmanX
-
-TODO
-* This driver was originally released for BCM28155 which has a different
-  cache architecture to BCM2835. Consequently, in this release only
-  uncached mappings are supported. However, there's no fundamental
-  reason which cached mappings cannot be support or BCM2835
-* More refactoring is required to remove the typedefs.
-* Re-enable the some of the commented out debug-fs statistics which were
-  disabled when migrating code from proc-fs.
-* There's a lot of code to support sharing of VCSM in order to support
-  Android. This could probably done more cleanly or perhaps just
-  removed.
-
-Signed-off-by: Tim Gover <timgover@gmail.com>
-
-config: Disable VC_SM for now to fix hang with cutdown kernel
-
-vcsm: Use boolean as it cannot be built as module
-
-On building the bcm_vc_sm as a module we get the following error:
-
-v7_dma_flush_range and do_munmap are undefined in vc-sm.ko.
-
-Fix by making it not an option to build as module
-
-vcsm: Add ioctl for custom cache flushing
-
-vc-sm: Move headers out of arch directory
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-vcsm: Treat EBUSY as success rather than SIGBUS
-
-Currently if two cores access the same page concurrently one will return VM_FAULT_NOPAGE
-and the other VM_FAULT_SIGBUS crashing the user code.
-
-Also report when mapping fails.
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
-
-vcsm: Provide new ioctl to clean/invalidate a 2D block
-
-vcsm: Convert to loading via device tree.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-
-VCSM: New option to import a DMABUF for VPU use
-
-Takes a dmabuf, and then calls over to the VPU to wrap
-it into a suitable handle.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-
-vcsm: fix multi-platform build
-
-vcsm: add macros for cache functions
-
-vcsm: use dma APIs for cache functions
-
-* Will handle multi-platform builds
-
-vcsm: Fix up macros to avoid breaking numbers used by existing apps
----
- drivers/char/Kconfig                     |    2 +
- drivers/char/Makefile                    |    1 +
- drivers/char/broadcom/Kconfig            |   10 +
- drivers/char/broadcom/Makefile           |    1 +
- drivers/char/broadcom/vc_sm/Makefile     |    9 +
- drivers/char/broadcom/vc_sm/vc_sm_defs.h |  237 ++
- drivers/char/broadcom/vc_sm/vc_sm_knl.h  |   58 +
- drivers/char/broadcom/vc_sm/vc_vchi_sm.c |  516 ++++
- drivers/char/broadcom/vc_sm/vc_vchi_sm.h |  102 +
- drivers/char/broadcom/vc_sm/vmcs_sm.c    | 3493 ++++++++++++++++++++++
- include/linux/broadcom/vmcs_sm_ioctl.h   |  280 ++
- 11 files changed, 4709 insertions(+)
- create mode 100644 drivers/char/broadcom/vc_sm/Makefile
- create mode 100644 drivers/char/broadcom/vc_sm/vc_sm_defs.h
- create mode 100644 drivers/char/broadcom/vc_sm/vc_sm_knl.h
- create mode 100644 drivers/char/broadcom/vc_sm/vc_vchi_sm.c
- create mode 100644 drivers/char/broadcom/vc_sm/vc_vchi_sm.h
- create mode 100644 drivers/char/broadcom/vc_sm/vmcs_sm.c
- create mode 100644 include/linux/broadcom/vmcs_sm_ioctl.h
-
---- a/drivers/char/Kconfig
-+++ b/drivers/char/Kconfig
-@@ -5,6 +5,8 @@
- 
- menu "Character devices"
- 
-+source "drivers/char/broadcom/Kconfig"
-+
- source "drivers/tty/Kconfig"
- 
- config DEVMEM
---- a/drivers/char/Makefile
-+++ b/drivers/char/Makefile
-@@ -60,3 +60,4 @@ js-rtc-y = rtc.o
- obj-$(CONFIG_TILE_SROM)		+= tile-srom.o
- obj-$(CONFIG_XILLYBUS)		+= xillybus/
- obj-$(CONFIG_POWERNV_OP_PANEL)	+= powernv-op-panel.o
-+obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/
---- a/drivers/char/broadcom/Kconfig
-+++ b/drivers/char/broadcom/Kconfig
-@@ -16,3 +16,13 @@ config BCM2708_VCMEM
-           Helper for videocore memory access and total size allocation.
- 
- endif
-+
-+config BCM_VC_SM
-+	bool "VMCS Shared Memory"
-+	depends on BCM2835_VCHIQ
-+	select BCM2708_VCMEM
-+	select DMA_SHARED_BUFFER
-+	default n
-+	help
-+	Support for the VC shared memory on the Broadcom reference
-+	design. Uses the VCHIQ stack.
---- a/drivers/char/broadcom/Makefile
-+++ b/drivers/char/broadcom/Makefile
-@@ -1 +1,2 @@
- obj-$(CONFIG_BCM2708_VCMEM)	+= vc_mem.o
-+obj-$(CONFIG_BCM_VC_SM)         += vc_sm/
---- /dev/null
-+++ b/drivers/char/broadcom/vc_sm/Makefile
-@@ -0,0 +1,9 @@
-+ccflags-$(CONFIG_BCM_VC_SM) += -Werror -Wall -Wstrict-prototypes -Wno-trigraphs -O2
-+ccflags-$(CONFIG_BCM_VC_SM) += -I"drivers/staging/vc04_services" -I"drivers/staging/vc04_services/interface/vchi" -I"drivers/staging/vc04_services/interface/vchiq_arm" -I"$(srctree)/fs/"
-+ccflags-$(CONFIG_BCM_VC_SM) += -DOS_ASSERT_FAILURE -D__STDC_VERSION=199901L -D__STDC_VERSION__=199901L -D__VCCOREVER__=0 -D__KERNEL__ -D__linux__
-+
-+obj-$(CONFIG_BCM_VC_SM) := vc-sm.o
-+
-+vc-sm-objs := \
-+    vmcs_sm.o \
-+    vc_vchi_sm.o
---- /dev/null
-+++ b/drivers/char/broadcom/vc_sm/vc_sm_defs.h
-@@ -0,0 +1,237 @@
-+/*
-+ ****************************************************************************
-+ * Copyright 2011 Broadcom Corporation.  All rights reserved.
-+ *
-+ * Unless you and Broadcom execute a separate written software license
-+ * agreement governing use of this software, this software is licensed to you
-+ * under the terms of the GNU General Public License version 2, available at
-+ * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+ *
-+ * Notwithstanding the above, under no circumstances may you combine this
-+ * software in any way with any other Broadcom software provided under a
-+ * license other than the GPL, without Broadcom's express prior written
-+ * consent.
-+ ****************************************************************************
-+ */
-+
-+#ifndef __VC_SM_DEFS_H__INCLUDED__
-+#define __VC_SM_DEFS_H__INCLUDED__
-+
-+/* FourCC code used for VCHI connection */
-+#define VC_SM_SERVER_NAME MAKE_FOURCC("SMEM")
-+
-+/* Maximum message length */
-+#define VC_SM_MAX_MSG_LEN (sizeof(union vc_sm_msg_union_t) + \
-+	sizeof(struct vc_sm_msg_hdr_t))
-+#define VC_SM_MAX_RSP_LEN (sizeof(union vc_sm_msg_union_t))
-+
-+/* Resource name maximum size */
-+#define VC_SM_RESOURCE_NAME 32
-+
-+enum vc_sm_msg_type {
-+	/* Message types supported for HOST->VC direction */
-+
-+	/* Allocate shared memory block */
-+	VC_SM_MSG_TYPE_ALLOC,
-+	/* Lock allocated shared memory block */
-+	VC_SM_MSG_TYPE_LOCK,
-+	/* Unlock allocated shared memory block */
-+	VC_SM_MSG_TYPE_UNLOCK,
-+	/* Unlock allocated shared memory block, do not answer command */
-+	VC_SM_MSG_TYPE_UNLOCK_NOANS,
-+	/* Free shared memory block */
-+	VC_SM_MSG_TYPE_FREE,
-+	/* Resize a shared memory block */
-+	VC_SM_MSG_TYPE_RESIZE,
-+	/* Walk the allocated shared memory block(s) */
-+	VC_SM_MSG_TYPE_WALK_ALLOC,
-+
-+	/* A previously applied action will need to be reverted */
-+	VC_SM_MSG_TYPE_ACTION_CLEAN,
-+
-+	/*
-+	 * Import a physical address and wrap into a MEM_HANDLE_T.
-+	 * Release with VC_SM_MSG_TYPE_FREE.
-+	 */
-+	VC_SM_MSG_TYPE_IMPORT,
-+
-+	/* Message types supported for VC->HOST direction */
-+
-+	/*
-+	 * VC has finished with an imported memory allocation.
-+	 * Release any Linux reference counts on the underlying block.
-+	 */
-+	VC_SM_MSG_TYPE_RELEASED,
-+
-+	VC_SM_MSG_TYPE_MAX
-+};
-+
-+/* Type of memory to be allocated */
-+enum vc_sm_alloc_type_t {
-+	VC_SM_ALLOC_CACHED,
-+	VC_SM_ALLOC_NON_CACHED,
-+};
-+
-+/* Message header for all messages in HOST->VC direction */
-+struct vc_sm_msg_hdr_t {
-+	int32_t type;
-+	uint32_t trans_id;
-+	uint8_t body[0];
-+
-+};
-+
-+/* Request to allocate memory (HOST->VC) */
-+struct vc_sm_alloc_t {
-+	/* type of memory to allocate */
-+	enum vc_sm_alloc_type_t type;
-+	/* byte amount of data to allocate per unit */
-+	uint32_t base_unit;
-+	/* number of unit to allocate */
-+	uint32_t num_unit;
-+	/* alignement to be applied on allocation */
-+	uint32_t alignement;
-+	/* identity of who allocated this block */
-+	uint32_t allocator;
-+	/* resource name (for easier tracking on vc side) */
-+	char name[VC_SM_RESOURCE_NAME];
-+
-+};
-+
-+/* Result of a requested memory allocation (VC->HOST) */
-+struct vc_sm_alloc_result_t {
-+	/* Transaction identifier */
-+	uint32_t trans_id;
-+
-+	/* Resource handle */
-+	uint32_t res_handle;
-+	/* Pointer to resource buffer */
-+	uint32_t res_mem;
-+	/* Resource base size (bytes) */
-+	uint32_t res_base_size;
-+	/* Resource number */
-+	uint32_t res_num;
-+
-+};
-+
-+/* Request to free a previously allocated memory (HOST->VC) */
-+struct vc_sm_free_t {
-+	/* Resource handle (returned from alloc) */
-+	uint32_t res_handle;
-+	/* Resource buffer (returned from alloc) */
-+	uint32_t res_mem;
-+
-+};
-+
-+/* Request to lock a previously allocated memory (HOST->VC) */
-+struct vc_sm_lock_unlock_t {
-+	/* Resource handle (returned from alloc) */
-+	uint32_t res_handle;
-+	/* Resource buffer (returned from alloc) */
-+	uint32_t res_mem;
-+
-+};
-+
-+/* Request to resize a previously allocated memory (HOST->VC) */
-+struct vc_sm_resize_t {
-+	/* Resource handle (returned from alloc) */
-+	uint32_t res_handle;
-+	/* Resource buffer (returned from alloc) */
-+	uint32_t res_mem;
-+	/* Resource *new* size requested (bytes) */
-+	uint32_t res_new_size;
-+
-+};
-+
-+/* Result of a requested memory lock (VC->HOST) */
-+struct vc_sm_lock_result_t {
-+	/* Transaction identifier */
-+	uint32_t trans_id;
-+
-+	/* Resource handle */
-+	uint32_t res_handle;
-+	/* Pointer to resource buffer */
-+	uint32_t res_mem;
-+	/*
-+	 * Pointer to former resource buffer if the memory
-+	 * was reallocated
-+	 */
-+	uint32_t res_old_mem;
-+
-+};
-+
-+/* Generic result for a request (VC->HOST) */
-+struct vc_sm_result_t {
-+	/* Transaction identifier */
-+	uint32_t trans_id;
-+
-+	int32_t success;
-+
-+};
-+
-+/* Request to revert a previously applied action (HOST->VC) */
-+struct vc_sm_action_clean_t {
-+	/* Action of interest */
-+	enum vc_sm_msg_type res_action;
-+	/* Transaction identifier for the action of interest */
-+	uint32_t action_trans_id;
-+
-+};
-+
-+/* Request to remove all data associated with a given allocator (HOST->VC) */
-+struct vc_sm_free_all_t {
-+	/* Allocator identifier */
-+	uint32_t allocator;
-+};
-+
-+/* Request to import memory (HOST->VC) */
-+struct vc_sm_import {
-+	/* type of memory to allocate */
-+	enum vc_sm_alloc_type_t type;
-+	/* pointer to the VC (ie physical) address of the allocated memory */
-+	uint32_t addr;
-+	/* size of buffer */
-+	uint32_t size;
-+	/* opaque handle returned in RELEASED messages */
-+	int32_t  kernel_id;
-+	/* Allocator identifier */
-+	uint32_t allocator;
-+	/* resource name (for easier tracking on vc side) */
-+	char     name[VC_SM_RESOURCE_NAME];
-+};
-+
-+/* Result of a requested memory import (VC->HOST) */
-+struct vc_sm_import_result {
-+	/* Transaction identifier */
-+	uint32_t trans_id;
-+
-+	/* Resource handle */
-+	uint32_t res_handle;
-+};
-+
-+/* Notification that VC has finished with an allocation (VC->HOST) */
-+struct vc_sm_released {
-+	/* pointer to the VC (ie physical) address of the allocated memory */
-+	uint32_t addr;
-+	/* size of buffer */
-+	uint32_t size;
-+	/* opaque handle returned in RELEASED messages */
-+	int32_t  kernel_id;
-+};
-+
-+/* Union of ALL messages */
-+union vc_sm_msg_union_t {
-+	struct vc_sm_alloc_t alloc;
-+	struct vc_sm_alloc_result_t alloc_result;
-+	struct vc_sm_free_t free;
-+	struct vc_sm_lock_unlock_t lock_unlock;
-+	struct vc_sm_action_clean_t action_clean;
-+	struct vc_sm_resize_t resize;
-+	struct vc_sm_lock_result_t lock_result;
-+	struct vc_sm_result_t result;
-+	struct vc_sm_free_all_t free_all;
-+	struct vc_sm_import import;
-+	struct vc_sm_import_result import_result;
-+	struct vc_sm_released released;
-+};
-+
-+#endif /* __VC_SM_DEFS_H__INCLUDED__ */
---- /dev/null
-+++ b/drivers/char/broadcom/vc_sm/vc_sm_knl.h
-@@ -0,0 +1,58 @@
-+/*
-+ ****************************************************************************
-+ * Copyright 2011 Broadcom Corporation.  All rights reserved.
-+ *
-+ * Unless you and Broadcom execute a separate written software license
-+ * agreement governing use of this software, this software is licensed to you
-+ * under the terms of the GNU General Public License version 2, available at
-+ * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+ *
-+ * Notwithstanding the above, under no circumstances may you combine this
-+ * software in any way with any other Broadcom software provided under a
-+ * license other than the GPL, without Broadcom's express prior written
-+ * consent.
-+ ****************************************************************************
-+ */
-+
-+#ifndef __VC_SM_KNL_H__INCLUDED__
-+#define __VC_SM_KNL_H__INCLUDED__
-+
-+#if !defined(__KERNEL__)
-+#error "This interface is for kernel use only..."
-+#endif
-+
-+/* Type of memory to be locked (ie mapped) */
-+enum vc_sm_lock_cache_mode {
-+	VC_SM_LOCK_CACHED,
-+	VC_SM_LOCK_NON_CACHED,
-+};
-+
-+/* Cache functions */
-+#define VCSM_CACHE_OP_INV       0x01
-+#define VCSM_CACHE_OP_CLEAN     0x02
-+#define VCSM_CACHE_OP_FLUSH     0x03
-+
-+/* Allocate a shared memory handle and block. */
-+int vc_sm_alloc(struct vc_sm_alloc_t *alloc, int *handle);
-+
-+/* Free a previously allocated shared memory handle and block. */
-+int vc_sm_free(int handle);
-+
-+/* Lock a memory handle for use by kernel. */
-+int vc_sm_lock(int handle, enum vc_sm_lock_cache_mode mode,
-+	       unsigned long *data);
-+
-+/* Unlock a memory handle in use by kernel. */
-+int vc_sm_unlock(int handle, int flush, int no_vc_unlock);
-+
-+/* Get an internal resource handle mapped from the external one. */
-+int vc_sm_int_handle(int handle);
-+
-+/* Map a shared memory region for use by kernel. */
-+int vc_sm_map(int handle, unsigned int sm_addr,
-+	      enum vc_sm_lock_cache_mode mode, unsigned long *data);
-+
-+/* Import a block of memory into the GPU space. */
-+int vc_sm_import_dmabuf(struct dma_buf *dmabuf, int *handle);
-+
-+#endif /* __VC_SM_KNL_H__INCLUDED__ */
---- /dev/null
-+++ b/drivers/char/broadcom/vc_sm/vc_vchi_sm.c
-@@ -0,0 +1,516 @@
-+/*
-+ ****************************************************************************
-+ * Copyright 2011-2012 Broadcom Corporation.  All rights reserved.
-+ *
-+ * Unless you and Broadcom execute a separate written software license
-+ * agreement governing use of this software, this software is licensed to you
-+ * under the terms of the GNU General Public License version 2, available at
-+ * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+ *
-+ * Notwithstanding the above, under no circumstances may you combine this
-+ * software in any way with any other Broadcom software provided under a
-+ * license other than the GPL, without Broadcom's express prior written
-+ * consent.
-+ ****************************************************************************
-+ */
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/semaphore.h>
-+#include <linux/mutex.h>
-+#include <linux/slab.h>
-+#include <linux/kthread.h>
-+
-+#include "vc_vchi_sm.h"
-+
-+#define VC_SM_VER  1
-+#define VC_SM_MIN_VER 0
-+
-+/* ---- Private Constants and Types -------------------------------------- */
-+
-+/* Command blocks come from a pool */
-+#define SM_MAX_NUM_CMD_RSP_BLKS 32
-+
-+struct sm_cmd_rsp_blk {
-+	struct list_head head;	/* To create lists */
-+	struct semaphore sema;	/* To be signaled when the response is there */
-+
-+	uint16_t id;
-+	uint16_t length;
-+
-+	uint8_t msg[VC_SM_MAX_MSG_LEN];
-+
-+	uint32_t wait:1;
-+	uint32_t sent:1;
-+	uint32_t alloc:1;
-+
-+};
-+
-+struct sm_instance {
-+	uint32_t num_connections;
-+	VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS];
-+	struct task_struct *io_thread;
-+	struct semaphore io_sema;
-+
-+	uint32_t trans_id;
-+
-+	struct mutex lock;
-+	struct list_head cmd_list;
-+	struct list_head rsp_list;
-+	struct list_head dead_list;
-+
-+	struct sm_cmd_rsp_blk free_blk[SM_MAX_NUM_CMD_RSP_BLKS];
-+	struct list_head free_list;
-+	struct mutex free_lock;
-+	struct semaphore free_sema;
-+
-+};
-+
-+/* ---- Private Variables ------------------------------------------------ */
-+
-+/* ---- Private Function Prototypes -------------------------------------- */
-+
-+/* ---- Private Functions ------------------------------------------------ */
-+static int
-+bcm2835_vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle,
-+		       void *data,
-+		       unsigned int size)
-+{
-+	return vchi_queue_kernel_message(handle,
-+					 data,
-+					 size);
-+}
-+
-+static struct
-+sm_cmd_rsp_blk *vc_vchi_cmd_create(struct sm_instance *instance,
-+		enum vc_sm_msg_type id, void *msg,
-+		uint32_t size, int wait)
-+{
-+	struct sm_cmd_rsp_blk *blk;
-+	struct vc_sm_msg_hdr_t *hdr;
-+
-+	if (down_interruptible(&instance->free_sema)) {
-+		blk = kmalloc(sizeof(*blk), GFP_KERNEL);
-+		if (!blk)
-+			return NULL;
-+
-+		blk->alloc = 1;
-+		sema_init(&blk->sema, 0);
-+	} else {
-+		mutex_lock(&instance->free_lock);
-+		blk =
-+		    list_first_entry(&instance->free_list,
-+				    struct sm_cmd_rsp_blk, head);
-+		list_del(&blk->head);
-+		mutex_unlock(&instance->free_lock);
-+	}
-+
-+	blk->sent = 0;
-+	blk->wait = wait;
-+	blk->length = sizeof(*hdr) + size;
-+
-+	hdr = (struct vc_sm_msg_hdr_t *) blk->msg;
-+	hdr->type = id;
-+	mutex_lock(&instance->lock);
-+	hdr->trans_id = blk->id = ++instance->trans_id;
-+	mutex_unlock(&instance->lock);
-+
-+	if (size)
-+		memcpy(hdr->body, msg, size);
-+
-+	return blk;
-+}
-+
-+static void
-+vc_vchi_cmd_delete(struct sm_instance *instance, struct sm_cmd_rsp_blk *blk)
-+{
-+	if (blk->alloc) {
-+		kfree(blk);
-+		return;
-+	}
-+
-+	mutex_lock(&instance->free_lock);
-+	list_add(&blk->head, &instance->free_list);
-+	mutex_unlock(&instance->free_lock);
-+	up(&instance->free_sema);
-+}
-+
-+static int vc_vchi_sm_videocore_io(void *arg)
-+{
-+	struct sm_instance *instance = arg;
-+	struct sm_cmd_rsp_blk *cmd = NULL, *cmd_tmp;
-+	struct vc_sm_result_t *reply;
-+	uint32_t reply_len;
-+	int32_t status;
-+	int svc_use = 1;
-+
-+	while (1) {
-+		if (svc_use)
-+			vchi_service_release(instance->vchi_handle[0]);
-+		svc_use = 0;
-+		if (!down_interruptible(&instance->io_sema)) {
-+			vchi_service_use(instance->vchi_handle[0]);
-+			svc_use = 1;
-+
-+			do {
-+				/*
-+				 * Get new command and move it to response list
-+				 */
-+				mutex_lock(&instance->lock);
-+				if (list_empty(&instance->cmd_list)) {
-+					/* no more commands to process */
-+					mutex_unlock(&instance->lock);
-+					break;
-+				}
-+				cmd =
-+				    list_first_entry(&instance->cmd_list,
-+						     struct sm_cmd_rsp_blk,
-+						     head);
-+				list_move(&cmd->head, &instance->rsp_list);
-+				cmd->sent = 1;
-+				mutex_unlock(&instance->lock);
-+
-+				/* Send the command */
-+				status = bcm2835_vchi_msg_queue(
-+						instance->vchi_handle[0],
-+						cmd->msg, cmd->length);
-+				if (status) {
-+					pr_err("%s: failed to queue message (%d)",
-+					     __func__, status);
-+				}
-+
-+				/* If no reply is needed then we're done */
-+				if (!cmd->wait) {
-+					mutex_lock(&instance->lock);
-+					list_del(&cmd->head);
-+					mutex_unlock(&instance->lock);
-+					vc_vchi_cmd_delete(instance, cmd);
-+					continue;
-+				}
-+
-+				if (status) {
-+					up(&cmd->sema);
-+					continue;
-+				}
-+
-+			} while (1);
-+
-+			while (!vchi_msg_peek
-+			       (instance->vchi_handle[0], (void **)&reply,
-+				&reply_len, VCHI_FLAGS_NONE)) {
-+				mutex_lock(&instance->lock);
-+				list_for_each_entry(cmd, &instance->rsp_list,
-+						    head) {
-+					if (cmd->id == reply->trans_id)
-+						break;
-+				}
-+				mutex_unlock(&instance->lock);
-+
-+				if (&cmd->head == &instance->rsp_list) {
-+					pr_debug("%s: received response %u, throw away...",
-+					     __func__, reply->trans_id);
-+				} else if (reply_len > sizeof(cmd->msg)) {
-+					pr_err("%s: reply too big (%u) %u, throw away...",
-+					     __func__, reply_len,
-+					     reply->trans_id);
-+				} else {
-+					memcpy(cmd->msg, reply, reply_len);
-+					up(&cmd->sema);
-+				}
-+
-+				vchi_msg_remove(instance->vchi_handle[0]);
-+			}
-+
-+			/* Go through the dead list and free them */
-+			mutex_lock(&instance->lock);
-+			list_for_each_entry_safe(cmd, cmd_tmp,
-+						 &instance->dead_list, head) {
-+				list_del(&cmd->head);
-+				vc_vchi_cmd_delete(instance, cmd);
-+			}
-+			mutex_unlock(&instance->lock);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static void vc_sm_vchi_callback(void *param,
-+				const VCHI_CALLBACK_REASON_T reason,
-+				void *msg_handle)
-+{
-+	struct sm_instance *instance = param;
-+
-+	(void)msg_handle;
-+
-+	switch (reason) {
-+	case VCHI_CALLBACK_MSG_AVAILABLE:
-+		up(&instance->io_sema);
-+		break;
-+
-+	case VCHI_CALLBACK_SERVICE_CLOSED:
-+		pr_info("%s: service CLOSED!!", __func__);
-+	default:
-+		break;
-+	}
-+}
-+
-+struct sm_instance *vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance,
-+				    VCHI_CONNECTION_T **vchi_connections,
-+				    uint32_t num_connections)
-+{
-+	uint32_t i;
-+	struct sm_instance *instance;
-+	int status;
-+
-+	pr_debug("%s: start", __func__);
-+
-+	if (num_connections > VCHI_MAX_NUM_CONNECTIONS) {
-+		pr_err("%s: unsupported number of connections %u (max=%u)",
-+			__func__, num_connections, VCHI_MAX_NUM_CONNECTIONS);
-+
-+		goto err_null;
-+	}
-+	/* Allocate memory for this instance */
-+	instance = kzalloc(sizeof(*instance), GFP_KERNEL);
-+
-+	/* Misc initialisations */
-+	mutex_init(&instance->lock);
-+	sema_init(&instance->io_sema, 0);
-+	INIT_LIST_HEAD(&instance->cmd_list);
-+	INIT_LIST_HEAD(&instance->rsp_list);
-+	INIT_LIST_HEAD(&instance->dead_list);
-+	INIT_LIST_HEAD(&instance->free_list);
-+	sema_init(&instance->free_sema, SM_MAX_NUM_CMD_RSP_BLKS);
-+	mutex_init(&instance->free_lock);
-+	for (i = 0; i < SM_MAX_NUM_CMD_RSP_BLKS; i++) {
-+		sema_init(&instance->free_blk[i].sema, 0);
-+		list_add(&instance->free_blk[i].head, &instance->free_list);
-+	}
-+
-+	/* Open the VCHI service connections */
-+	instance->num_connections = num_connections;
-+	for (i = 0; i < num_connections; i++) {
-+		SERVICE_CREATION_T params = {
-+			VCHI_VERSION_EX(VC_SM_VER, VC_SM_MIN_VER),
-+			VC_SM_SERVER_NAME,
-+			vchi_connections[i],
-+			0,
-+			0,
-+			vc_sm_vchi_callback,
-+			instance,
-+			0,
-+			0,
-+			0,
-+		};
-+
-+		status = vchi_service_open(vchi_instance,
-+					   &params, &instance->vchi_handle[i]);
-+		if (status) {
-+			pr_err("%s: failed to open VCHI service (%d)",
-+					__func__, status);
-+
-+			goto err_close_services;
-+		}
-+	}
-+
-+	/* Create the thread which takes care of all io to/from videoocore. */
-+	instance->io_thread = kthread_create(&vc_vchi_sm_videocore_io,
-+					     (void *)instance, "SMIO");
-+	if (instance->io_thread == NULL) {
-+		pr_err("%s: failed to create SMIO thread", __func__);
-+
-+		goto err_close_services;
-+	}
-+	set_user_nice(instance->io_thread, -10);
-+	wake_up_process(instance->io_thread);
-+
-+	pr_debug("%s: success - instance 0x%x", __func__,
-+		 (unsigned int)instance);
-+	return instance;
-+
-+err_close_services:
-+	for (i = 0; i < instance->num_connections; i++) {
-+		if (instance->vchi_handle[i] != NULL)
-+			vchi_service_close(instance->vchi_handle[i]);
-+	}
-+	kfree(instance);
-+err_null:
-+	pr_debug("%s: FAILED", __func__);
-+	return NULL;
-+}
-+
-+int vc_vchi_sm_stop(struct sm_instance **handle)
-+{
-+	struct sm_instance *instance;
-+	uint32_t i;
-+
-+	if (handle == NULL) {
-+		pr_err("%s: invalid pointer to handle %p", __func__, handle);
-+		goto lock;
-+	}
-+
-+	if (*handle == NULL) {
-+		pr_err("%s: invalid handle %p", __func__, *handle);
-+		goto lock;
-+	}
-+
-+	instance = *handle;
-+
-+	/* Close all VCHI service connections */
-+	for (i = 0; i < instance->num_connections; i++) {
-+		int32_t success;
-+
-+		vchi_service_use(instance->vchi_handle[i]);
-+
-+		success = vchi_service_close(instance->vchi_handle[i]);
-+	}
-+
-+	kfree(instance);
-+
-+	*handle = NULL;
-+	return 0;
-+
-+lock:
-+	return -EINVAL;
-+}
-+
-+int vc_vchi_sm_send_msg(struct sm_instance *handle,
-+			enum vc_sm_msg_type msg_id,
-+			void *msg, uint32_t msg_size,
-+			void *result, uint32_t result_size,
-+			uint32_t *cur_trans_id, uint8_t wait_reply)
-+{
-+	int status = 0;
-+	struct sm_instance *instance = handle;
-+	struct sm_cmd_rsp_blk *cmd_blk;
-+
-+	if (handle == NULL) {
-+		pr_err("%s: invalid handle", __func__);
-+		return -EINVAL;
-+	}
-+	if (msg == NULL) {
-+		pr_err("%s: invalid msg pointer", __func__);
-+		return -EINVAL;
-+	}
-+
-+	cmd_blk =
-+	    vc_vchi_cmd_create(instance, msg_id, msg, msg_size, wait_reply);
-+	if (cmd_blk == NULL) {
-+		pr_err("[%s]: failed to allocate global tracking resource",
-+			__func__);
-+		return -ENOMEM;
-+	}
-+
-+	if (cur_trans_id != NULL)
-+		*cur_trans_id = cmd_blk->id;
-+
-+	mutex_lock(&instance->lock);
-+	list_add_tail(&cmd_blk->head, &instance->cmd_list);
-+	mutex_unlock(&instance->lock);
-+	up(&instance->io_sema);
-+
-+	if (!wait_reply)
-+		/* We're done */
-+		return 0;
-+
-+	/* Wait for the response */
-+	if (down_interruptible(&cmd_blk->sema)) {
-+		mutex_lock(&instance->lock);
-+		if (!cmd_blk->sent) {
-+			list_del(&cmd_blk->head);
-+			mutex_unlock(&instance->lock);
-+			vc_vchi_cmd_delete(instance, cmd_blk);
-+			return -ENXIO;
-+		}
-+		mutex_unlock(&instance->lock);
-+
-+		mutex_lock(&instance->lock);
-+		list_move(&cmd_blk->head, &instance->dead_list);
-+		mutex_unlock(&instance->lock);
-+		up(&instance->io_sema);
-+		return -EINTR;	/* We're done */
-+	}
-+
-+	if (result && result_size) {
-+		memcpy(result, cmd_blk->msg, result_size);
-+	} else {
-+		struct vc_sm_result_t *res =
-+			(struct vc_sm_result_t *) cmd_blk->msg;
-+		status = (res->success == 0) ? 0 : -ENXIO;
-+	}
-+
-+	mutex_lock(&instance->lock);
-+	list_del(&cmd_blk->head);
-+	mutex_unlock(&instance->lock);
-+	vc_vchi_cmd_delete(instance, cmd_blk);
-+	return status;
-+}
-+
-+int vc_vchi_sm_alloc(struct sm_instance *handle, struct vc_sm_alloc_t *msg,
-+		     struct vc_sm_alloc_result_t *result,
-+		     uint32_t *cur_trans_id)
-+{
-+	return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ALLOC,
-+				   msg, sizeof(*msg), result, sizeof(*result),
-+				   cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_free(struct sm_instance *handle,
-+		    struct vc_sm_free_t *msg, uint32_t *cur_trans_id)
-+{
-+	return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_FREE,
-+				   msg, sizeof(*msg), 0, 0, cur_trans_id, 0);
-+}
-+
-+int vc_vchi_sm_lock(struct sm_instance *handle,
-+		    struct vc_sm_lock_unlock_t *msg,
-+		    struct vc_sm_lock_result_t *result,
-+		    uint32_t *cur_trans_id)
-+{
-+	return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_LOCK,
-+				   msg, sizeof(*msg), result, sizeof(*result),
-+				   cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_unlock(struct sm_instance *handle,
-+		      struct vc_sm_lock_unlock_t *msg,
-+		      uint32_t *cur_trans_id, uint8_t wait_reply)
-+{
-+	return vc_vchi_sm_send_msg(handle, wait_reply ?
-+				   VC_SM_MSG_TYPE_UNLOCK :
-+				   VC_SM_MSG_TYPE_UNLOCK_NOANS, msg,
-+				   sizeof(*msg), 0, 0, cur_trans_id,
-+				   wait_reply);
-+}
-+
-+int vc_vchi_sm_resize(struct sm_instance *handle, struct vc_sm_resize_t *msg,
-+		      uint32_t *cur_trans_id)
-+{
-+	return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_RESIZE,
-+				   msg, sizeof(*msg), 0, 0, cur_trans_id, 1);
-+}
-+
-+int vc_vchi_sm_walk_alloc(struct sm_instance *handle)
-+{
-+	return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_WALK_ALLOC,
-+				   0, 0, 0, 0, 0, 0);
-+}
-+
-+int vc_vchi_sm_clean_up(struct sm_instance *handle,
-+			struct vc_sm_action_clean_t *msg)
-+{
-+	return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ACTION_CLEAN,
-+				   msg, sizeof(*msg), 0, 0, 0, 0);
-+}
-+
-+int vc_vchi_sm_import(struct sm_instance *handle, struct vc_sm_import *msg,
-+		      struct vc_sm_import_result *result,
-+		      uint32_t *cur_trans_id)
-+{
-+	return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_IMPORT,
-+				   msg, sizeof(*msg), result, sizeof(*result),
-+				   cur_trans_id, 1);
-+}
---- /dev/null
-+++ b/drivers/char/broadcom/vc_sm/vc_vchi_sm.h
-@@ -0,0 +1,102 @@
-+/*
-+ ****************************************************************************
-+ * Copyright 2011 Broadcom Corporation.  All rights reserved.
-+ *
-+ * Unless you and Broadcom execute a separate written software license
-+ * agreement governing use of this software, this software is licensed to you
-+ * under the terms of the GNU General Public License version 2, available at
-+ * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+ *
-+ * Notwithstanding the above, under no circumstances may you combine this
-+ * software in any way with any other Broadcom software provided under a
-+ * license other than the GPL, without Broadcom's express prior written
-+ * consent.
-+ ****************************************************************************
-+ */
-+
-+#ifndef __VC_VCHI_SM_H__INCLUDED__
-+#define __VC_VCHI_SM_H__INCLUDED__
-+
-+#include "interface/vchi/vchi.h"
-+
-+#include "vc_sm_defs.h"
-+
-+/*
-+ * Forward declare.
-+ */
-+struct sm_instance;
-+
-+/*
-+ * Initialize the shared memory service, opens up vchi connection to talk to it.
-+ */
-+struct sm_instance *vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance,
-+				    VCHI_CONNECTION_T **vchi_connections,
-+				    uint32_t num_connections);
-+
-+/*
-+ * Terminates the shared memory service.
-+ */
-+int vc_vchi_sm_stop(struct sm_instance **handle);
-+
-+/*
-+ * Ask the shared memory service to allocate some memory on videocre and
-+ * return the result of this allocation (which upon success will be a pointer
-+ * to some memory in videocore space).
-+ */
-+int vc_vchi_sm_alloc(struct sm_instance *handle, struct vc_sm_alloc_t *alloc,
-+		     struct vc_sm_alloc_result_t *alloc_result,
-+		     uint32_t *trans_id);
-+
-+/*
-+ * Ask the shared memory service to free up some memory that was previously
-+ * allocated by the vc_vchi_sm_alloc function call.
-+ */
-+int vc_vchi_sm_free(struct sm_instance *handle,
-+		    struct vc_sm_free_t *free, uint32_t *trans_id);
-+
-+/*
-+ * Ask the shared memory service to lock up some memory that was previously
-+ * allocated by the vc_vchi_sm_alloc function call.
-+ */
-+int vc_vchi_sm_lock(struct sm_instance *handle,
-+		    struct vc_sm_lock_unlock_t *lock_unlock,
-+		    struct vc_sm_lock_result_t *lock_result,
-+		    uint32_t *trans_id);
-+
-+/*
-+ * Ask the shared memory service to unlock some memory that was previously
-+ * allocated by the vc_vchi_sm_alloc function call.
-+ */
-+int vc_vchi_sm_unlock(struct sm_instance *handle,
-+		      struct vc_sm_lock_unlock_t *lock_unlock,
-+		      uint32_t *trans_id, uint8_t wait_reply);
-+
-+/*
-+ * Ask the shared memory service to resize some memory that was previously
-+ * allocated by the vc_vchi_sm_alloc function call.
-+ */
-+int vc_vchi_sm_resize(struct sm_instance *handle,
-+		      struct vc_sm_resize_t *resize, uint32_t *trans_id);
-+
-+/*
-+ * Walk the allocated resources on the videocore side, the allocation will
-+ * show up in the log.  This is purely for debug/information and takes no
-+ * specific actions.
-+ */
-+int vc_vchi_sm_walk_alloc(struct sm_instance *handle);
-+
-+/*
-+ * Clean up following a previously interrupted action which left the system
-+ * in a bad state of some sort.
-+ */
-+int vc_vchi_sm_clean_up(struct sm_instance *handle,
-+			struct vc_sm_action_clean_t *action_clean);
-+
-+/*
-+ * Import a contiguous block of memory and wrap it in a GPU MEM_HANDLE_T.
-+ */
-+int vc_vchi_sm_import(struct sm_instance *handle, struct vc_sm_import *msg,
-+		      struct vc_sm_import_result *result,
-+		      uint32_t *cur_trans_id);
-+
-+#endif /* __VC_VCHI_SM_H__INCLUDED__ */
---- /dev/null
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -0,0 +1,3493 @@
-+/*
-+ ****************************************************************************
-+ * Copyright 2011-2012 Broadcom Corporation.  All rights reserved.
-+ *
-+ * Unless you and Broadcom execute a separate written software license
-+ * agreement governing use of this software, this software is licensed to you
-+ * under the terms of the GNU General Public License version 2, available at
-+ * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+ *
-+ * Notwithstanding the above, under no circumstances may you combine this
-+ * software in any way with any other Broadcom software provided under a
-+ * license other than the GPL, without Broadcom's express prior written
-+ * consent.
-+ ****************************************************************************
-+ */
-+
-+/* ---- Include Files ----------------------------------------------------- */
-+
-+#include <linux/cdev.h>
-+#include <linux/broadcom/vc_mem.h>
-+#include <linux/device.h>
-+#include <linux/debugfs.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dma-buf.h>
-+#include <linux/errno.h>
-+#include <linux/fs.h>
-+#include <linux/hugetlb.h>
-+#include <linux/ioctl.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/mm.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pfn.h>
-+#include <linux/proc_fs.h>
-+#include <linux/pagemap.h>
-+#include <linux/semaphore.h>
-+#include <linux/slab.h>
-+#include <linux/seq_file.h>
-+#include <linux/types.h>
-+#include <asm/cacheflush.h>
-+
-+#include "vchiq_connected.h"
-+#include "vc_vchi_sm.h"
-+
-+#include <linux/broadcom/vmcs_sm_ioctl.h>
-+#include "vc_sm_knl.h"
-+
-+/* ---- Private Constants and Types --------------------------------------- */
-+
-+#define DEVICE_NAME              "vcsm"
-+#define DRIVER_NAME		 "bcm2835-vcsm"
-+#define DEVICE_MINOR             0
-+
-+#define VC_SM_DIR_ROOT_NAME       "vc-smem"
-+#define VC_SM_DIR_ALLOC_NAME      "alloc"
-+#define VC_SM_STATE               "state"
-+#define VC_SM_STATS               "statistics"
-+#define VC_SM_RESOURCES           "resources"
-+#define VC_SM_DEBUG               "debug"
-+#define VC_SM_WRITE_BUF_SIZE      128
-+
-+/* Statistics tracked per resource and globally. */
-+enum sm_stats_t {
-+	/* Attempt. */
-+	ALLOC,
-+	FREE,
-+	LOCK,
-+	UNLOCK,
-+	MAP,
-+	FLUSH,
-+	INVALID,
-+	IMPORT,
-+
-+	END_ATTEMPT,
-+
-+	/* Failure. */
-+	ALLOC_FAIL,
-+	FREE_FAIL,
-+	LOCK_FAIL,
-+	UNLOCK_FAIL,
-+	MAP_FAIL,
-+	FLUSH_FAIL,
-+	INVALID_FAIL,
-+	IMPORT_FAIL,
-+
-+	END_ALL,
-+
-+};
-+
-+static const char *const sm_stats_human_read[] = {
-+	"Alloc",
-+	"Free",
-+	"Lock",
-+	"Unlock",
-+	"Map",
-+	"Cache Flush",
-+	"Cache Invalidate",
-+	"Import",
-+};
-+
-+typedef int (*VC_SM_SHOW) (struct seq_file *s, void *v);
-+struct sm_pde_t {
-+	VC_SM_SHOW show;          /* Debug fs function hookup. */
-+	struct dentry *dir_entry; /* Debug fs directory entry. */
-+	void *priv_data;          /* Private data */
-+
-+};
-+
-+/* Single resource allocation tracked for all devices. */
-+struct sm_mmap {
-+	struct list_head map_list;	/* Linked list of maps. */
-+
-+	struct sm_resource_t *resource;	/* Pointer to the resource. */
-+
-+	pid_t res_pid;			/* PID owning that resource. */
-+	unsigned int res_vc_hdl;	/* Resource handle (videocore). */
-+	unsigned int res_usr_hdl;	/* Resource handle (user). */
-+
-+	unsigned long res_addr;	/* Mapped virtual address. */
-+	struct vm_area_struct *vma;	/* VM area for this mapping. */
-+	unsigned int ref_count;		/* Reference count to this vma. */
-+
-+	/* Used to link maps associated with a resource. */
-+	struct list_head resource_map_list;
-+};
-+
-+/* Single resource allocation tracked for each opened device. */
-+struct sm_resource_t {
-+	struct list_head resource_list;	/* List of resources. */
-+	struct list_head global_resource_list;	/* Global list of resources. */
-+
-+	pid_t pid;		/* PID owning that resource. */
-+	uint32_t res_guid;	/* Unique identifier. */
-+	uint32_t lock_count;	/* Lock count for this resource. */
-+	uint32_t ref_count;	/* Ref count for this resource. */
-+
-+	uint32_t res_handle;	/* Resource allocation handle. */
-+	void *res_base_mem;	/* Resource base memory address. */
-+	uint32_t res_size;	/* Resource size allocated. */
-+	enum vmcs_sm_cache_e res_cached;	/* Resource cache type. */
-+	struct sm_resource_t *res_shared;	/* Shared resource */
-+
-+	enum sm_stats_t res_stats[END_ALL];	/* Resource statistics. */
-+
-+	uint8_t map_count;	/* Counter of mappings for this resource. */
-+	struct list_head map_list;	/* Maps associated with a resource. */
-+
-+	/* DMABUF related fields */
-+	struct dma_buf *dma_buf;
-+	struct dma_buf_attachment *attach;
-+	struct sg_table *sgt;
-+	dma_addr_t dma_addr;
-+
-+	struct sm_priv_data_t *private;
-+	bool map;		/* whether to map pages up front */
-+};
-+
-+/* Private file data associated with each opened device. */
-+struct sm_priv_data_t {
-+	struct list_head resource_list; /* List of resources. */
-+
-+	pid_t pid;                      /* PID of creator. */
-+
-+	struct dentry *dir_pid;	   /* Debug fs entries root. */
-+	struct sm_pde_t dir_stats; /* Debug fs entries statistics sub-tree. */
-+	struct sm_pde_t dir_res;   /* Debug fs resource sub-tree. */
-+
-+	int restart_sys;           /* Tracks restart on interrupt. */
-+	enum vc_sm_msg_type int_action; /* Interrupted action. */
-+	uint32_t int_trans_id;     /* Interrupted transaction. */
-+
-+};
-+
-+/* Global state information. */
-+struct sm_state_t {
-+	struct platform_device *pdev;
-+	struct sm_instance *sm_handle;	/* Handle for videocore service. */
-+	struct dentry *dir_root;   /* Debug fs entries root. */
-+	struct dentry *dir_alloc;  /* Debug fs entries allocations. */
-+	struct sm_pde_t dir_stats; /* Debug fs entries statistics sub-tree. */
-+	struct sm_pde_t dir_state; /* Debug fs entries state sub-tree. */
-+	struct dentry *debug;      /* Debug fs entries debug. */
-+
-+	struct mutex map_lock;          /* Global map lock. */
-+	struct list_head map_list;      /* List of maps. */
-+	struct list_head resource_list;	/* List of resources. */
-+
-+	enum sm_stats_t deceased[END_ALL];    /* Natural termination stats. */
-+	enum sm_stats_t terminated[END_ALL];  /* Forced termination stats. */
-+	uint32_t res_deceased_cnt;	      /* Natural termination counter. */
-+	uint32_t res_terminated_cnt;	      /* Forced termination counter. */
-+
-+	struct cdev sm_cdev;	/* Device. */
-+	dev_t sm_devid;		/* Device identifier. */
-+	struct class *sm_class;	/* Class. */
-+	struct device *sm_dev;	/* Device. */
-+
-+	struct sm_priv_data_t *data_knl;    /* Kernel internal data tracking. */
-+
-+	struct mutex lock;	/* Global lock. */
-+	uint32_t guid;		/* GUID (next) tracker. */
-+
-+};
-+
-+/* ---- Private Variables ----------------------------------------------- */
-+
-+static struct sm_state_t *sm_state;
-+static int sm_inited;
-+
-+#if 0
-+static const char *const sm_cache_map_vector[] = {
-+	"(null)",
-+	"host",
-+	"videocore",
-+	"host+videocore",
-+};
-+#endif
-+
-+/* ---- Private Function Prototypes -------------------------------------- */
-+
-+/* ---- Private Functions ------------------------------------------------ */
-+
-+static inline unsigned int vcaddr_to_pfn(unsigned long vc_addr)
-+{
-+	unsigned long pfn = vc_addr & 0x3FFFFFFF;
-+
-+	pfn += mm_vc_mem_phys_addr;
-+	pfn >>= PAGE_SHIFT;
-+	return pfn;
-+}
-+
-+/*
-+ * Carries over to the state statistics the statistics once owned by a deceased
-+ * resource.
-+ */
-+static void vc_sm_resource_deceased(struct sm_resource_t *p_res, int terminated)
-+{
-+	if (sm_state != NULL) {
-+		if (p_res != NULL) {
-+			int ix;
-+
-+			if (terminated)
-+				sm_state->res_terminated_cnt++;
-+			else
-+				sm_state->res_deceased_cnt++;
-+
-+			for (ix = 0; ix < END_ALL; ix++) {
-+				if (terminated)
-+					sm_state->terminated[ix] +=
-+					    p_res->res_stats[ix];
-+				else
-+					sm_state->deceased[ix] +=
-+					    p_res->res_stats[ix];
-+			}
-+		}
-+	}
-+}
-+
-+/*
-+ * Fetch a videocore handle corresponding to a mapping of the pid+address
-+ * returns 0 (ie NULL) if no such handle exists in the global map.
-+ */
-+static unsigned int vmcs_sm_vc_handle_from_pid_and_address(unsigned int pid,
-+							   unsigned int addr)
-+{
-+	struct sm_mmap *map = NULL;
-+	unsigned int handle = 0;
-+
-+	if (!sm_state || addr == 0)
-+		goto out;
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	/* Lookup the resource. */
-+	if (!list_empty(&sm_state->map_list)) {
-+		list_for_each_entry(map, &sm_state->map_list, map_list) {
-+			if (map->res_pid != pid || map->res_addr != addr)
-+				continue;
-+
-+			pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n",
-+				__func__, map, map->res_pid, map->res_addr,
-+				map->res_vc_hdl, map->res_usr_hdl);
-+
-+			handle = map->res_vc_hdl;
-+			break;
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+	/*
-+	 * Use a debug log here as it may be a valid situation that we query
-+	 * for something that is not mapped, we do not want a kernel log each
-+	 * time around.
-+	 *
-+	 * There are other error log that would pop up accordingly if someone
-+	 * subsequently tries to use something invalid after being told not to
-+	 * use it...
-+	 */
-+	if (handle == 0) {
-+		pr_debug("[%s]: not a valid map (pid %u, addr %x)\n",
-+			__func__, pid, addr);
-+	}
-+
-+	return handle;
-+}
-+
-+/*
-+ * Fetch a user handle corresponding to a mapping of the pid+address
-+ * returns 0 (ie NULL) if no such handle exists in the global map.
-+ */
-+static unsigned int vmcs_sm_usr_handle_from_pid_and_address(unsigned int pid,
-+							    unsigned int addr)
-+{
-+	struct sm_mmap *map = NULL;
-+	unsigned int handle = 0;
-+
-+	if (!sm_state || addr == 0)
-+		goto out;
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	/* Lookup the resource. */
-+	if (!list_empty(&sm_state->map_list)) {
-+		list_for_each_entry(map, &sm_state->map_list, map_list) {
-+			if (map->res_pid != pid || map->res_addr != addr)
-+				continue;
-+
-+			pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n",
-+				__func__, map, map->res_pid, map->res_addr,
-+				map->res_usr_hdl, map->res_vc_hdl);
-+
-+			handle = map->res_usr_hdl;
-+			break;
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+	/*
-+	 * Use a debug log here as it may be a valid situation that we query
-+	 * for something that is not mapped yet.
-+	 *
-+	 * There are other error log that would pop up accordingly if someone
-+	 * subsequently tries to use something invalid after being told not to
-+	 * use it...
-+	 */
-+	if (handle == 0)
-+		pr_debug("[%s]: not a valid map (pid %u, addr %x)\n",
-+			__func__, pid, addr);
-+
-+	return handle;
-+}
-+
-+#if defined(DO_NOT_USE)
-+/*
-+ * Fetch an address corresponding to a mapping of the pid+handle
-+ * returns 0 (ie NULL) if no such address exists in the global map.
-+ */
-+static unsigned int vmcs_sm_usr_address_from_pid_and_vc_handle(unsigned int pid,
-+							       unsigned int hdl)
-+{
-+	struct sm_mmap *map = NULL;
-+	unsigned int addr = 0;
-+
-+	if (sm_state == NULL || hdl == 0)
-+		goto out;
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	/* Lookup the resource. */
-+	if (!list_empty(&sm_state->map_list)) {
-+		list_for_each_entry(map, &sm_state->map_list, map_list) {
-+			if (map->res_pid != pid || map->res_vc_hdl != hdl)
-+				continue;
-+
-+			pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n",
-+				__func__, map, map->res_pid, map->res_vc_hdl,
-+				map->res_usr_hdl, map->res_addr);
-+
-+			addr = map->res_addr;
-+			break;
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+	/*
-+	 * Use a debug log here as it may be a valid situation that we query
-+	 * for something that is not mapped, we do not want a kernel log each
-+	 * time around.
-+	 *
-+	 * There are other error log that would pop up accordingly if someone
-+	 * subsequently tries to use something invalid after being told not to
-+	 * use it...
-+	 */
-+	if (addr == 0)
-+		pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n",
-+			__func__, pid, hdl);
-+
-+	return addr;
-+}
-+#endif
-+
-+/*
-+ * Fetch an address corresponding to a mapping of the pid+handle
-+ * returns 0 (ie NULL) if no such address exists in the global map.
-+ */
-+static unsigned int vmcs_sm_usr_address_from_pid_and_usr_handle(unsigned int
-+								pid,
-+								unsigned int
-+								hdl)
-+{
-+	struct sm_mmap *map = NULL;
-+	unsigned int addr = 0;
-+
-+	if (sm_state == NULL || hdl == 0)
-+		goto out;
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	/* Lookup the resource. */
-+	if (!list_empty(&sm_state->map_list)) {
-+		list_for_each_entry(map, &sm_state->map_list, map_list) {
-+			if (map->res_pid != pid || map->res_usr_hdl != hdl)
-+				continue;
-+
-+			pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n",
-+				__func__, map, map->res_pid, map->res_vc_hdl,
-+				map->res_usr_hdl, map->res_addr);
-+
-+			addr = map->res_addr;
-+			break;
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+out:
-+	/*
-+	 * Use a debug log here as it may be a valid situation that we query
-+	 * for something that is not mapped, we do not want a kernel log each
-+	 * time around.
-+	 *
-+	 * There are other error log that would pop up accordingly if someone
-+	 * subsequently tries to use something invalid after being told not to
-+	 * use it...
-+	 */
-+	if (addr == 0)
-+		pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", __func__,
-+				pid, hdl);
-+
-+	return addr;
-+}
-+
-+/* Adds a resource mapping to the global data list. */
-+static void vmcs_sm_add_map(struct sm_state_t *state,
-+			    struct sm_resource_t *resource, struct sm_mmap *map)
-+{
-+	mutex_lock(&(state->map_lock));
-+
-+	/* Add to the global list of mappings */
-+	list_add(&map->map_list, &state->map_list);
-+
-+	/* Add to the list of mappings for this resource */
-+	list_add(&map->resource_map_list, &resource->map_list);
-+	resource->map_count++;
-+
-+	mutex_unlock(&(state->map_lock));
-+
-+	pr_debug("[%s]: added map %p (pid %u, vc-hdl %x, usr-hdl %x, addr %lx)\n",
-+		__func__, map, map->res_pid, map->res_vc_hdl,
-+		map->res_usr_hdl, map->res_addr);
-+}
-+
-+/* Removes a resource mapping from the global data list. */
-+static void vmcs_sm_remove_map(struct sm_state_t *state,
-+			       struct sm_resource_t *resource,
-+			       struct sm_mmap *map)
-+{
-+	mutex_lock(&(state->map_lock));
-+
-+	/* Remove from the global list of mappings */
-+	list_del(&map->map_list);
-+
-+	/* Remove from the list of mapping for this resource */
-+	list_del(&map->resource_map_list);
-+	if (resource->map_count > 0)
-+		resource->map_count--;
-+
-+	mutex_unlock(&(state->map_lock));
-+
-+	pr_debug("[%s]: removed map %p (pid %d, vc-hdl %x, usr-hdl %x, addr %lx)\n",
-+		__func__, map, map->res_pid, map->res_vc_hdl, map->res_usr_hdl,
-+		map->res_addr);
-+
-+	kfree(map);
-+}
-+
-+/* Read callback for the global state proc entry. */
-+static int vc_sm_global_state_show(struct seq_file *s, void *v)
-+{
-+	struct sm_mmap *map = NULL;
-+	struct sm_resource_t *resource = NULL;
-+	int map_count = 0;
-+	int resource_count = 0;
-+
-+	if (sm_state == NULL)
-+		return 0;
-+
-+	seq_printf(s, "\nVC-ServiceHandle     0x%x\n",
-+		   (unsigned int)sm_state->sm_handle);
-+
-+	/* Log all applicable mapping(s). */
-+
-+	mutex_lock(&(sm_state->map_lock));
-+	seq_puts(s, "\nResources\n");
-+	if (!list_empty(&sm_state->resource_list)) {
-+		list_for_each_entry(resource, &sm_state->resource_list,
-+				    global_resource_list) {
-+			resource_count++;
-+
-+			seq_printf(s, "\nResource                %p\n",
-+				   resource);
-+			seq_printf(s, "           PID          %u\n",
-+				   resource->pid);
-+			seq_printf(s, "           RES_GUID     0x%x\n",
-+				   resource->res_guid);
-+			seq_printf(s, "           LOCK_COUNT   %u\n",
-+				   resource->lock_count);
-+			seq_printf(s, "           REF_COUNT    %u\n",
-+				   resource->ref_count);
-+			seq_printf(s, "           res_handle   0x%X\n",
-+				   resource->res_handle);
-+			seq_printf(s, "           res_base_mem %p\n",
-+				   resource->res_base_mem);
-+			seq_printf(s, "           SIZE         %d\n",
-+				   resource->res_size);
-+			seq_printf(s, "           DMABUF       %p\n",
-+				   resource->dma_buf);
-+			seq_printf(s, "           ATTACH       %p\n",
-+				   resource->attach);
-+			seq_printf(s, "           SGT          %p\n",
-+				   resource->sgt);
-+			seq_printf(s, "           DMA_ADDR     %pad\n",
-+				   &resource->dma_addr);
-+		}
-+	}
-+	seq_printf(s, "\n\nTotal resource count:   %d\n\n", resource_count);
-+
-+	seq_puts(s, "\nMappings\n");
-+	if (!list_empty(&sm_state->map_list)) {
-+		list_for_each_entry(map, &sm_state->map_list, map_list) {
-+			map_count++;
-+
-+			seq_printf(s, "\nMapping                0x%x\n",
-+				   (unsigned int)map);
-+			seq_printf(s, "           TGID        %u\n",
-+				   map->res_pid);
-+			seq_printf(s, "           VC-HDL      0x%x\n",
-+				   map->res_vc_hdl);
-+			seq_printf(s, "           USR-HDL     0x%x\n",
-+				   map->res_usr_hdl);
-+			seq_printf(s, "           USR-ADDR    0x%lx\n",
-+				   map->res_addr);
-+			seq_printf(s, "           SIZE        %d\n",
-+				   map->resource->res_size);
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+	seq_printf(s, "\n\nTotal map count:   %d\n\n", map_count);
-+
-+	return 0;
-+}
-+
-+static int vc_sm_global_statistics_show(struct seq_file *s, void *v)
-+{
-+	int ix;
-+
-+	/* Global state tracked statistics. */
-+	if (sm_state != NULL) {
-+		seq_puts(s, "\nDeceased Resources Statistics\n");
-+
-+		seq_printf(s, "\nNatural Cause (%u occurences)\n",
-+			   sm_state->res_deceased_cnt);
-+		for (ix = 0; ix < END_ATTEMPT; ix++) {
-+			if (sm_state->deceased[ix] > 0) {
-+				seq_printf(s, "                %u\t%s\n",
-+					   sm_state->deceased[ix],
-+					   sm_stats_human_read[ix]);
-+			}
-+		}
-+		seq_puts(s, "\n");
-+		for (ix = 0; ix < END_ATTEMPT; ix++) {
-+			if (sm_state->deceased[ix + END_ATTEMPT] > 0) {
-+				seq_printf(s, "                %u\tFAILED %s\n",
-+					   sm_state->deceased[ix + END_ATTEMPT],
-+					   sm_stats_human_read[ix]);
-+			}
-+		}
-+
-+		seq_printf(s, "\nForcefull (%u occurences)\n",
-+			   sm_state->res_terminated_cnt);
-+		for (ix = 0; ix < END_ATTEMPT; ix++) {
-+			if (sm_state->terminated[ix] > 0) {
-+				seq_printf(s, "                %u\t%s\n",
-+					   sm_state->terminated[ix],
-+					   sm_stats_human_read[ix]);
-+			}
-+		}
-+		seq_puts(s, "\n");
-+		for (ix = 0; ix < END_ATTEMPT; ix++) {
-+			if (sm_state->terminated[ix + END_ATTEMPT] > 0) {
-+				seq_printf(s, "                %u\tFAILED %s\n",
-+					   sm_state->terminated[ix +
-+								END_ATTEMPT],
-+					   sm_stats_human_read[ix]);
-+			}
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+#if 0
-+/* Read callback for the statistics proc entry. */
-+static int vc_sm_statistics_show(struct seq_file *s, void *v)
-+{
-+	int ix;
-+	struct sm_priv_data_t *file_data;
-+	struct sm_resource_t *resource;
-+	int res_count = 0;
-+	struct sm_pde_t *p_pde;
-+
-+	p_pde = (struct sm_pde_t *)(s->private);
-+	file_data = (struct sm_priv_data_t *)(p_pde->priv_data);
-+
-+	if (file_data == NULL)
-+		return 0;
-+
-+	/* Per process statistics. */
-+
-+	seq_printf(s, "\nStatistics for TGID %d\n", file_data->pid);
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	if (!list_empty(&file_data->resource_list)) {
-+		list_for_each_entry(resource, &file_data->resource_list,
-+				    resource_list) {
-+			res_count++;
-+
-+			seq_printf(s, "\nGUID:         0x%x\n\n",
-+				   resource->res_guid);
-+			for (ix = 0; ix < END_ATTEMPT; ix++) {
-+				if (resource->res_stats[ix] > 0) {
-+					seq_printf(s,
-+						   "                %u\t%s\n",
-+						   resource->res_stats[ix],
-+						   sm_stats_human_read[ix]);
-+				}
-+			}
-+			seq_puts(s, "\n");
-+			for (ix = 0; ix < END_ATTEMPT; ix++) {
-+				if (resource->res_stats[ix + END_ATTEMPT] > 0) {
-+					seq_printf(s,
-+						   "                %u\tFAILED %s\n",
-+						   resource->res_stats[
-+						   ix + END_ATTEMPT],
-+						   sm_stats_human_read[ix]);
-+				}
-+			}
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+	seq_printf(s, "\nResources Count %d\n", res_count);
-+
-+	return 0;
-+}
-+#endif
-+
-+#if 0
-+/* Read callback for the allocation proc entry.  */
-+static int vc_sm_alloc_show(struct seq_file *s, void *v)
-+{
-+	struct sm_priv_data_t *file_data;
-+	struct sm_resource_t *resource;
-+	int alloc_count = 0;
-+	struct sm_pde_t *p_pde;
-+
-+	p_pde = (struct sm_pde_t *)(s->private);
-+	file_data = (struct sm_priv_data_t *)(p_pde->priv_data);
-+
-+	if (!file_data)
-+		return 0;
-+
-+	/* Per process statistics.  */
-+	seq_printf(s, "\nAllocation for TGID %d\n", file_data->pid);
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	if (!list_empty(&file_data->resource_list)) {
-+		list_for_each_entry(resource, &file_data->resource_list,
-+				    resource_list) {
-+			alloc_count++;
-+
-+			seq_printf(s, "\nGUID:              0x%x\n",
-+				   resource->res_guid);
-+			seq_printf(s, "Lock Count:        %u\n",
-+				   resource->lock_count);
-+			seq_printf(s, "Mapped:            %s\n",
-+				   (resource->map_count ? "yes" : "no"));
-+			seq_printf(s, "VC-handle:         0x%x\n",
-+				   resource->res_handle);
-+			seq_printf(s, "VC-address:        0x%p\n",
-+				   resource->res_base_mem);
-+			seq_printf(s, "VC-size (bytes):   %u\n",
-+				   resource->res_size);
-+			seq_printf(s, "Cache:             %s\n",
-+				   sm_cache_map_vector[resource->res_cached]);
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+	seq_printf(s, "\n\nTotal allocation count: %d\n\n", alloc_count);
-+
-+	return 0;
-+}
-+#endif
-+
-+static int vc_sm_seq_file_show(struct seq_file *s, void *v)
-+{
-+	struct sm_pde_t *sm_pde;
-+
-+	sm_pde = (struct sm_pde_t *)(s->private);
-+
-+	if (sm_pde && sm_pde->show)
-+		sm_pde->show(s, v);
-+
-+	return 0;
-+}
-+
-+static int vc_sm_single_open(struct inode *inode, struct file *file)
-+{
-+	return single_open(file, vc_sm_seq_file_show, inode->i_private);
-+}
-+
-+static const struct file_operations vc_sm_debug_fs_fops = {
-+	.open = vc_sm_single_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+};
-+
-+/*
-+ * Adds a resource to the private data list which tracks all the allocated
-+ * data.
-+ */
-+static void vmcs_sm_add_resource(struct sm_priv_data_t *privdata,
-+				 struct sm_resource_t *resource)
-+{
-+	mutex_lock(&(sm_state->map_lock));
-+	list_add(&resource->resource_list, &privdata->resource_list);
-+	list_add(&resource->global_resource_list, &sm_state->resource_list);
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+	pr_debug("[%s]: added resource %p (base addr %p, hdl %x, size %u, cache %u)\n",
-+		__func__, resource, resource->res_base_mem,
-+		resource->res_handle, resource->res_size, resource->res_cached);
-+}
-+
-+/*
-+ * Locates a resource and acquire a reference on it.
-+ * The resource won't be deleted while there is a reference on it.
-+ */
-+static struct sm_resource_t *vmcs_sm_acquire_resource(struct sm_priv_data_t
-+						      *private,
-+						      unsigned int res_guid)
-+{
-+	struct sm_resource_t *resource, *ret = NULL;
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	list_for_each_entry(resource, &private->resource_list, resource_list) {
-+		if (resource->res_guid != res_guid)
-+			continue;
-+
-+		pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+			__func__, resource, resource->res_guid,
-+			resource->res_base_mem, resource->res_handle,
-+			resource->res_size, resource->res_cached);
-+		resource->ref_count++;
-+		ret = resource;
-+		break;
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+	return ret;
-+}
-+
-+/*
-+ * Locates a resource and acquire a reference on it.
-+ * The resource won't be deleted while there is a reference on it.
-+ */
-+static struct sm_resource_t *vmcs_sm_acquire_first_resource(
-+		struct sm_priv_data_t *private)
-+{
-+	struct sm_resource_t *resource, *ret = NULL;
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	list_for_each_entry(resource, &private->resource_list, resource_list) {
-+		pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+			__func__, resource, resource->res_guid,
-+			resource->res_base_mem, resource->res_handle,
-+			resource->res_size, resource->res_cached);
-+		resource->ref_count++;
-+		ret = resource;
-+		break;
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+	return ret;
-+}
-+
-+/*
-+ * Locates a resource and acquire a reference on it.
-+ * The resource won't be deleted while there is a reference on it.
-+ */
-+static struct sm_resource_t *vmcs_sm_acquire_global_resource(unsigned int
-+							     res_guid)
-+{
-+	struct sm_resource_t *resource, *ret = NULL;
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	list_for_each_entry(resource, &sm_state->resource_list,
-+			    global_resource_list) {
-+		if (resource->res_guid != res_guid)
-+			continue;
-+
-+		pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n",
-+			__func__, resource, resource->res_guid,
-+			resource->res_base_mem, resource->res_handle,
-+			resource->res_size, resource->res_cached);
-+		resource->ref_count++;
-+		ret = resource;
-+		break;
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+	return ret;
-+}
-+
-+/*
-+ * Release a previously acquired resource.
-+ * The resource will be deleted when its refcount reaches 0.
-+ */
-+static void vmcs_sm_release_resource(struct sm_resource_t *resource, int force)
-+{
-+	struct sm_priv_data_t *private = resource->private;
-+	struct sm_mmap *map, *map_tmp;
-+	struct sm_resource_t *res_tmp;
-+	int ret;
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	if (--resource->ref_count) {
-+		if (force)
-+			pr_err("[%s]: resource %p in use\n", __func__, resource);
-+
-+		mutex_unlock(&(sm_state->map_lock));
-+		return;
-+	}
-+
-+	/* Time to free the resource. Start by removing it from the list */
-+	list_del(&resource->resource_list);
-+	list_del(&resource->global_resource_list);
-+
-+	/*
-+	 * Walk the global resource list, find out if the resource is used
-+	 * somewhere else. In which case we don't want to delete it.
-+	 */
-+	list_for_each_entry(res_tmp, &sm_state->resource_list,
-+			    global_resource_list) {
-+		if (res_tmp->res_handle == resource->res_handle) {
-+			resource->res_handle = 0;
-+			break;
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+
-+	pr_debug("[%s]: freeing data - guid %x, hdl %x, base address %p\n",
-+		__func__, resource->res_guid, resource->res_handle,
-+		resource->res_base_mem);
-+	resource->res_stats[FREE]++;
-+
-+	/* Make sure the resource we're removing is unmapped first */
-+	if (resource->map_count && !list_empty(&resource->map_list)) {
-+		down_write(&current->mm->mmap_sem);
-+		list_for_each_entry_safe(map, map_tmp, &resource->map_list,
-+					 resource_map_list) {
-+			ret =
-+			    do_munmap(current->mm, map->res_addr,
-+				      resource->res_size, NULL);
-+			if (ret) {
-+				pr_err("[%s]: could not unmap resource %p\n",
-+					__func__, resource);
-+			}
-+		}
-+		up_write(&current->mm->mmap_sem);
-+	}
-+
-+	/* Free up the videocore allocated resource. */
-+	if (resource->res_handle) {
-+		struct vc_sm_free_t free = {
-+			resource->res_handle, (uint32_t)resource->res_base_mem
-+		};
-+		int status = vc_vchi_sm_free(sm_state->sm_handle, &free,
-+					     &private->int_trans_id);
-+		if (status != 0 && status != -EINTR) {
-+			pr_err("[%s]: failed to free memory on videocore (status: %u, trans_id: %u)\n",
-+			     __func__, status, private->int_trans_id);
-+			resource->res_stats[FREE_FAIL]++;
-+			ret = -EPERM;
-+		}
-+	}
-+
-+	if (resource->sgt)
-+		dma_buf_unmap_attachment(resource->attach, resource->sgt,
-+					 DMA_BIDIRECTIONAL);
-+	if (resource->attach)
-+		dma_buf_detach(resource->dma_buf, resource->attach);
-+	if (resource->dma_buf)
-+		dma_buf_put(resource->dma_buf);
-+
-+	/* Free up the shared resource. */
-+	if (resource->res_shared)
-+		vmcs_sm_release_resource(resource->res_shared, 0);
-+
-+	/* Free up the local resource tracking this allocation. */
-+	vc_sm_resource_deceased(resource, force);
-+	kfree(resource);
-+}
-+
-+/*
-+ * Dump the map table for the driver.  If process is -1, dumps the whole table,
-+ * if process is a valid pid (non -1) dump only the entries associated with the
-+ * pid of interest.
-+ */
-+static void vmcs_sm_host_walk_map_per_pid(int pid)
-+{
-+	struct sm_mmap *map = NULL;
-+
-+	/* Make sure the device was started properly. */
-+	if (sm_state == NULL) {
-+		pr_err("[%s]: invalid device\n", __func__);
-+		return;
-+	}
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	/* Log all applicable mapping(s). */
-+	if (!list_empty(&sm_state->map_list)) {
-+		list_for_each_entry(map, &sm_state->map_list, map_list) {
-+			if (pid == -1 || map->res_pid == pid) {
-+				pr_info("[%s]: tgid: %u - vc-hdl: %x, usr-hdl: %x, usr-addr: %lx\n",
-+				     __func__, map->res_pid, map->res_vc_hdl,
-+				     map->res_usr_hdl, map->res_addr);
-+			}
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+}
-+
-+/*
-+ * Dump the allocation table from host side point of view.  This only dumps the
-+ * data allocated for this process/device referenced by the file_data.
-+ */
-+static void vmcs_sm_host_walk_alloc(struct sm_priv_data_t *file_data)
-+{
-+	struct sm_resource_t *resource = NULL;
-+
-+	/* Make sure the device was started properly. */
-+	if ((sm_state == NULL) || (file_data == NULL)) {
-+		pr_err("[%s]: invalid device\n", __func__);
-+		return;
-+	}
-+
-+	mutex_lock(&(sm_state->map_lock));
-+
-+	if (!list_empty(&file_data->resource_list)) {
-+		list_for_each_entry(resource, &file_data->resource_list,
-+				    resource_list) {
-+			pr_info("[%s]: guid: %x - hdl: %x, vc-mem: %p, size: %u, cache: %u\n",
-+			     __func__, resource->res_guid, resource->res_handle,
-+			     resource->res_base_mem, resource->res_size,
-+			     resource->res_cached);
-+		}
-+	}
-+
-+	mutex_unlock(&(sm_state->map_lock));
-+}
-+
-+/* Create support for private data tracking. */
-+static struct sm_priv_data_t *vc_sm_create_priv_data(pid_t id)
-+{
-+	char alloc_name[32];
-+	struct sm_priv_data_t *file_data = NULL;
-+
-+	/* Allocate private structure. */
-+	file_data = kzalloc(sizeof(*file_data), GFP_KERNEL);
-+
-+	if (!file_data) {
-+		pr_err("[%s]: cannot allocate file data\n", __func__);
-+		goto out;
-+	}
-+
-+	snprintf(alloc_name, sizeof(alloc_name), "%d", id);
-+
-+	INIT_LIST_HEAD(&file_data->resource_list);
-+	file_data->pid = id;
-+	file_data->dir_pid = debugfs_create_dir(alloc_name,
-+			sm_state->dir_alloc);
-+#if 0
-+  /* TODO: fix this to support querying statistics per pid */
-+
-+	if (IS_ERR_OR_NULL(file_data->dir_pid)) {
-+		file_data->dir_pid = NULL;
-+	} else {
-+		struct dentry *dir_entry;
-+
-+		dir_entry = debugfs_create_file(VC_SM_RESOURCES, 0444,
-+				file_data->dir_pid, file_data,
-+				vc_sm_debug_fs_fops);
-+
-+		file_data->dir_res.dir_entry = dir_entry;
-+		file_data->dir_res.priv_data = file_data;
-+		file_data->dir_res.show = &vc_sm_alloc_show;
-+
-+		dir_entry = debugfs_create_file(VC_SM_STATS, 0444,
-+				file_data->dir_pid, file_data,
-+				vc_sm_debug_fs_fops);
-+
-+		file_data->dir_res.dir_entry = dir_entry;
-+		file_data->dir_res.priv_data = file_data;
-+		file_data->dir_res.show = &vc_sm_statistics_show;
-+	}
-+	pr_debug("[%s]: private data allocated %p\n", __func__, file_data);
-+
-+#endif
-+out:
-+	return file_data;
-+}
-+
-+/*
-+ * Open the device.  Creates a private state to help track all allocation
-+ * associated with this device.
-+ */
-+static int vc_sm_open(struct inode *inode, struct file *file)
-+{
-+	int ret = 0;
-+
-+	/* Make sure the device was started properly. */
-+	if (!sm_state) {
-+		pr_err("[%s]: invalid device\n", __func__);
-+		ret = -EPERM;
-+		goto out;
-+	}
-+
-+	file->private_data = vc_sm_create_priv_data(current->tgid);
-+	if (file->private_data == NULL) {
-+		pr_err("[%s]: failed to create data tracker\n", __func__);
-+
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+out:
-+	return ret;
-+}
-+
-+/*
-+ * Close the device.  Free up all resources still associated with this device
-+ * at the time.
-+ */
-+static int vc_sm_release(struct inode *inode, struct file *file)
-+{
-+	struct sm_priv_data_t *file_data =
-+	    (struct sm_priv_data_t *)file->private_data;
-+	struct sm_resource_t *resource;
-+	int ret = 0;
-+
-+	/* Make sure the device was started properly. */
-+	if (sm_state == NULL || file_data == NULL) {
-+		pr_err("[%s]: invalid device\n", __func__);
-+		ret = -EPERM;
-+		goto out;
-+	}
-+
-+	pr_debug("[%s]: using private data %p\n", __func__, file_data);
-+
-+	if (file_data->restart_sys == -EINTR) {
-+		struct vc_sm_action_clean_t action_clean;
-+
-+		pr_debug("[%s]: releasing following EINTR on %u (trans_id: %u) (likely due to signal)...\n",
-+			__func__, file_data->int_action,
-+			file_data->int_trans_id);
-+
-+		action_clean.res_action = file_data->int_action;
-+		action_clean.action_trans_id = file_data->int_trans_id;
-+
-+		vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean);
-+	}
-+
-+	while ((resource = vmcs_sm_acquire_first_resource(file_data)) != NULL) {
-+		vmcs_sm_release_resource(resource, 0);
-+		vmcs_sm_release_resource(resource, 1);
-+	}
-+
-+	/* Remove the corresponding proc entry. */
-+	debugfs_remove_recursive(file_data->dir_pid);
-+
-+	/* Terminate the private data. */
-+	kfree(file_data);
-+
-+out:
-+	return ret;
-+}
-+
-+static void vcsm_vma_open(struct vm_area_struct *vma)
-+{
-+	struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
-+
-+	pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n",
-+		__func__, vma->vm_start, vma->vm_end, (int)current->tgid,
-+		(int)vma->vm_pgoff);
-+
-+	map->ref_count++;
-+}
-+
-+static void vcsm_vma_close(struct vm_area_struct *vma)
-+{
-+	struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data;
-+
-+	pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n",
-+		__func__, vma->vm_start, vma->vm_end, (int)current->tgid,
-+		(int)vma->vm_pgoff);
-+
-+	map->ref_count--;
-+
-+	/* Remove from the map table. */
-+	if (map->ref_count == 0)
-+		vmcs_sm_remove_map(sm_state, map->resource, map);
-+}
-+
-+static int vcsm_vma_fault(struct vm_fault *vmf)
-+{
-+	struct sm_mmap *map = (struct sm_mmap *)vmf->vma->vm_private_data;
-+	struct sm_resource_t *resource = map->resource;
-+	pgoff_t page_offset;
-+	unsigned long pfn;
-+	int ret = 0;
-+
-+	/* Lock the resource if necessary. */
-+	if (!resource->lock_count) {
-+		struct vc_sm_lock_unlock_t lock_unlock;
-+		struct vc_sm_lock_result_t lock_result;
-+		int status;
-+
-+		lock_unlock.res_handle = resource->res_handle;
-+		lock_unlock.res_mem = (uint32_t)resource->res_base_mem;
-+
-+		pr_debug("[%s]: attempt to lock data - hdl %x, base address %p\n",
-+			__func__, lock_unlock.res_handle,
-+			(void *)lock_unlock.res_mem);
-+
-+		/* Lock the videocore allocated resource. */
-+		status = vc_vchi_sm_lock(sm_state->sm_handle,
-+					 &lock_unlock, &lock_result, 0);
-+		if (status || !lock_result.res_mem) {
-+			pr_err("[%s]: failed to lock memory on videocore (status: %u)\n",
-+					__func__, status);
-+			resource->res_stats[LOCK_FAIL]++;
-+			return VM_FAULT_SIGBUS;
-+		}
-+
-+		pfn = vcaddr_to_pfn((unsigned long)resource->res_base_mem);
-+		outer_inv_range(__pfn_to_phys(pfn),
-+				__pfn_to_phys(pfn) + resource->res_size);
-+
-+		resource->res_stats[LOCK]++;
-+		resource->lock_count++;
-+
-+		/* Keep track of the new base memory. */
-+		if (lock_result.res_mem &&
-+		    lock_result.res_old_mem &&
-+		    (lock_result.res_mem != lock_result.res_old_mem)) {
-+			resource->res_base_mem = (void *)lock_result.res_mem;
-+		}
-+	}
-+
-+	/* We don't use vmf->pgoff since that has the fake offset */
-+	page_offset = ((unsigned long)vmf->address - vmf->vma->vm_start);
-+	pfn = (uint32_t)resource->res_base_mem & 0x3FFFFFFF;
-+	pfn += mm_vc_mem_phys_addr;
-+	pfn += page_offset;
-+	pfn >>= PAGE_SHIFT;
-+
-+	/* Finally, remap it */
-+	ret = vm_insert_pfn(vmf->vma, (unsigned long)vmf->address, pfn);
-+
-+	switch (ret) {
-+	case 0:
-+	case -ERESTARTSYS:
-+	/*
-+	 * EBUSY is ok: this just means that another thread
-+	 * already did the job.
-+	 */
-+	case -EBUSY:
-+		return VM_FAULT_NOPAGE;
-+	case -ENOMEM:
-+	case -EAGAIN:
-+		pr_err("[%s]: failed to map page pfn:%lx virt:%lx ret:%d\n", __func__,
-+			pfn, (unsigned long)vmf->address, ret);
-+		return VM_FAULT_OOM;
-+	default:
-+		pr_err("[%s]: failed to map page pfn:%lx virt:%lx ret:%d\n", __func__,
-+			pfn, (unsigned long)vmf->address, ret);
-+		return VM_FAULT_SIGBUS;
-+	}
-+}
-+
-+static const struct vm_operations_struct vcsm_vm_ops = {
-+	.open = vcsm_vma_open,
-+	.close = vcsm_vma_close,
-+	.fault = vcsm_vma_fault,
-+};
-+
-+/* Walks a VMA and clean each valid page from the cache */
-+static void vcsm_vma_cache_clean_page_range(unsigned long addr,
-+					    unsigned long end)
-+{
-+	pgd_t *pgd;
-+	pud_t *pud;
-+	pmd_t *pmd;
-+	pte_t *pte;
-+	unsigned long pgd_next, pud_next, pmd_next;
-+
-+	if (addr >= end)
-+		return;
-+
-+	/* Walk PGD */
-+	pgd = pgd_offset(current->mm, addr);
-+	do {
-+		pgd_next = pgd_addr_end(addr, end);
-+
-+		if (pgd_none(*pgd) || pgd_bad(*pgd))
-+			continue;
-+
-+		/* Walk PUD */
-+		pud = pud_offset(pgd, addr);
-+		do {
-+			pud_next = pud_addr_end(addr, pgd_next);
-+			if (pud_none(*pud) || pud_bad(*pud))
-+				continue;
-+
-+			/* Walk PMD */
-+			pmd = pmd_offset(pud, addr);
-+			do {
-+				pmd_next = pmd_addr_end(addr, pud_next);
-+				if (pmd_none(*pmd) || pmd_bad(*pmd))
-+					continue;
-+
-+				/* Walk PTE */
-+				pte = pte_offset_map(pmd, addr);
-+				do {
-+					if (pte_none(*pte)
-+					    || !pte_present(*pte))
-+						continue;
-+
-+					/* Clean + invalidate */
-+					dmac_flush_range((const void *) addr,
-+							 (const void *)
-+							 (addr + PAGE_SIZE));
-+
-+				} while (pte++, addr +=
-+					 PAGE_SIZE, addr != pmd_next);
-+				pte_unmap(pte);
-+
-+			} while (pmd++, addr = pmd_next, addr != pud_next);
-+
-+		} while (pud++, addr = pud_next, addr != pgd_next);
-+	} while (pgd++, addr = pgd_next, addr != end);
-+}
-+
-+/* Map an allocated data into something that the user space. */
-+static int vc_sm_mmap(struct file *file, struct vm_area_struct *vma)
-+{
-+	int ret = 0;
-+	struct sm_priv_data_t *file_data =
-+	    (struct sm_priv_data_t *)file->private_data;
-+	struct sm_resource_t *resource = NULL;
-+	struct sm_mmap *map = NULL;
-+
-+	/* Make sure the device was started properly. */
-+	if ((sm_state == NULL) || (file_data == NULL)) {
-+		pr_err("[%s]: invalid device\n", __func__);
-+		return -EPERM;
-+	}
-+
-+	pr_debug("[%s]: private data %p, guid %x\n", __func__, file_data,
-+		((unsigned int)vma->vm_pgoff << PAGE_SHIFT));
-+
-+	/*
-+	 * We lookup to make sure that the data we are being asked to mmap is
-+	 * something that we allocated.
-+	 *
-+	 * We use the offset information as the key to tell us which resource
-+	 * we are mapping.
-+	 */
-+	resource = vmcs_sm_acquire_resource(file_data,
-+					    ((unsigned int)vma->vm_pgoff <<
-+					     PAGE_SHIFT));
-+	if (resource == NULL) {
-+		pr_err("[%s]: failed to locate resource for guid %x\n", __func__,
-+			((unsigned int)vma->vm_pgoff << PAGE_SHIFT));
-+		return -ENOMEM;
-+	}
-+
-+	pr_debug("[%s]: guid %x, tgid %u, %u, %u\n",
-+		__func__, resource->res_guid, current->tgid, resource->pid,
-+		file_data->pid);
-+
-+	/* Check permissions. */
-+	if (resource->pid && (resource->pid != current->tgid)) {
-+		pr_err("[%s]: current tgid %u != %u owner\n",
-+			__func__, current->tgid, resource->pid);
-+		ret = -EPERM;
-+		goto error;
-+	}
-+
-+	/* Verify that what we are asked to mmap is proper. */
-+	if (resource->res_size != (unsigned int)(vma->vm_end - vma->vm_start)) {
-+		pr_err("[%s]: size inconsistency (resource: %u - mmap: %u)\n",
-+			__func__,
-+			resource->res_size,
-+			(unsigned int)(vma->vm_end - vma->vm_start));
-+
-+		ret = -EINVAL;
-+		goto error;
-+	}
-+
-+	/*
-+	 * Keep track of the tuple in the global resource list such that one
-+	 * can do a mapping lookup for address/memory handle.
-+	 */
-+	map = kzalloc(sizeof(*map), GFP_KERNEL);
-+	if (map == NULL) {
-+		pr_err("[%s]: failed to allocate global tracking resource\n",
-+			__func__);
-+		ret = -ENOMEM;
-+		goto error;
-+	}
-+
-+	map->res_pid = current->tgid;
-+	map->res_vc_hdl = resource->res_handle;
-+	map->res_usr_hdl = resource->res_guid;
-+	map->res_addr = (unsigned long)vma->vm_start;
-+	map->resource = resource;
-+	map->vma = vma;
-+	vmcs_sm_add_map(sm_state, resource, map);
-+
-+	/*
-+	 * We are not actually mapping the pages, we just provide a fault
-+	 * handler to allow pages to be mapped when accessed
-+	 */
-+	vma->vm_flags |=
-+	    VM_IO | VM_PFNMAP | VM_DONTCOPY | VM_DONTEXPAND;
-+	vma->vm_ops = &vcsm_vm_ops;
-+	vma->vm_private_data = map;
-+
-+	/* vm_pgoff is the first PFN of the mapped memory */
-+	vma->vm_pgoff = (unsigned long)resource->res_base_mem & 0x3FFFFFFF;
-+	vma->vm_pgoff += mm_vc_mem_phys_addr;
-+	vma->vm_pgoff >>= PAGE_SHIFT;
-+
-+	if ((resource->res_cached == VMCS_SM_CACHE_NONE) ||
-+	    (resource->res_cached == VMCS_SM_CACHE_VC)) {
-+		/* Allocated non host cached memory, honour it. */
-+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-+	}
-+
-+	pr_debug("[%s]: resource %p (guid %x) - cnt %u, base address %p, handle %x, size %u (%u), cache %u\n",
-+		__func__,
-+		resource, resource->res_guid, resource->lock_count,
-+		resource->res_base_mem, resource->res_handle,
-+		resource->res_size, (unsigned int)(vma->vm_end - vma->vm_start),
-+		resource->res_cached);
-+
-+	pr_debug("[%s]: resource %p (base address %p, handle %x) - map-count %d, usr-addr %x\n",
-+		__func__, resource, resource->res_base_mem,
-+		resource->res_handle, resource->map_count,
-+		(unsigned int)vma->vm_start);
-+
-+	vcsm_vma_open(vma);
-+	resource->res_stats[MAP]++;
-+	vmcs_sm_release_resource(resource, 0);
-+
-+	if (resource->map) {
-+		/* We don't use vmf->pgoff since that has the fake offset */
-+		unsigned long addr;
-+
-+		for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {
-+			/* Finally, remap it */
-+			unsigned long pfn = (unsigned long)resource->res_base_mem & 0x3FFFFFFF;
-+
-+			pfn += mm_vc_mem_phys_addr;
-+			pfn += addr - vma->vm_start;
-+			pfn >>= PAGE_SHIFT;
-+			ret = vm_insert_pfn(vma, addr, pfn);
-+		}
-+	}
-+
-+	return 0;
-+
-+error:
-+	resource->res_stats[MAP_FAIL]++;
-+	vmcs_sm_release_resource(resource, 0);
-+	return ret;
-+}
-+
-+/* Allocate a shared memory handle and block. */
-+int vc_sm_ioctl_alloc(struct sm_priv_data_t *private,
-+		      struct vmcs_sm_ioctl_alloc *ioparam)
-+{
-+	int ret = 0;
-+	int status;
-+	struct sm_resource_t *resource;
-+	struct vc_sm_alloc_t alloc = { 0 };
-+	struct vc_sm_alloc_result_t result = { 0 };
-+	enum vmcs_sm_cache_e cached = ioparam->cached;
-+	bool map = false;
-+
-+	/* flag to requst buffer is mapped up front, rather than lazily */
-+	if (cached & 0x80) {
-+		map = true;
-+		cached &= ~0x80;
-+	}
-+
-+	/* Setup our allocation parameters */
-+	alloc.type = ((cached == VMCS_SM_CACHE_VC)
-+		      || (cached ==
-+			  VMCS_SM_CACHE_BOTH)) ? VC_SM_ALLOC_CACHED :
-+	    VC_SM_ALLOC_NON_CACHED;
-+	alloc.base_unit = ioparam->size;
-+	alloc.num_unit = ioparam->num;
-+	alloc.allocator = current->tgid;
-+	/* Align to kernel page size */
-+	alloc.alignement = 4096;
-+	/* Align the size to the kernel page size */
-+	alloc.base_unit =
-+	    (alloc.base_unit + alloc.alignement - 1) & ~(alloc.alignement - 1);
-+	if (*ioparam->name) {
-+		memcpy(alloc.name, ioparam->name, sizeof(alloc.name) - 1);
-+	} else {
-+		memcpy(alloc.name, VMCS_SM_RESOURCE_NAME_DEFAULT,
-+		       sizeof(VMCS_SM_RESOURCE_NAME_DEFAULT));
-+	}
-+
-+	pr_debug("[%s]: attempt to allocate \"%s\" data - type %u, base %u (%u), num %u, alignement %u\n",
-+		__func__, alloc.name, alloc.type, ioparam->size,
-+		alloc.base_unit, alloc.num_unit, alloc.alignement);
-+
-+	/* Allocate local resource to track this allocation. */
-+	resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-+	if (!resource) {
-+		ret = -ENOMEM;
-+		goto error;
-+	}
-+	INIT_LIST_HEAD(&resource->map_list);
-+	resource->ref_count++;
-+	resource->pid = current->tgid;
-+
-+	/* Allocate the videocore resource. */
-+	status = vc_vchi_sm_alloc(sm_state->sm_handle, &alloc, &result,
-+				  &private->int_trans_id);
-+	if (status == -EINTR) {
-+		pr_debug("[%s]: requesting allocate memory action restart (trans_id: %u)\n",
-+			__func__, private->int_trans_id);
-+		ret = -ERESTARTSYS;
-+		private->restart_sys = -EINTR;
-+		private->int_action = VC_SM_MSG_TYPE_ALLOC;
-+		goto error;
-+	} else if (status != 0 || !result.res_mem) {
-+		pr_err("[%s]: failed to allocate memory on videocore (status: %u, trans_id: %u)\n",
-+		     __func__, status, private->int_trans_id);
-+		ret = -ENOMEM;
-+		resource->res_stats[ALLOC_FAIL]++;
-+		goto error;
-+	}
-+
-+	/* Keep track of the resource we created. */
-+	resource->private = private;
-+	resource->res_handle = result.res_handle;
-+	resource->res_base_mem = (void *)result.res_mem;
-+	resource->res_size = alloc.base_unit * alloc.num_unit;
-+	resource->res_cached = cached;
-+	resource->map = map;
-+
-+	/*
-+	 * Kernel/user GUID.  This global identifier is used for mmap'ing the
-+	 * allocated region from user space, it is passed as the mmap'ing
-+	 * offset, we use it to 'hide' the videocore handle/address.
-+	 */
-+	mutex_lock(&sm_state->lock);
-+	resource->res_guid = ++sm_state->guid;
-+	mutex_unlock(&sm_state->lock);
-+	resource->res_guid <<= PAGE_SHIFT;
-+
-+	vmcs_sm_add_resource(private, resource);
-+
-+	pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n",
-+		__func__, resource->res_guid, resource->res_handle,
-+		resource->res_base_mem, resource->res_size,
-+		resource->res_cached);
-+
-+	/* We're done */
-+	resource->res_stats[ALLOC]++;
-+	ioparam->handle = resource->res_guid;
-+	return 0;
-+
-+error:
-+	pr_err("[%s]: failed to allocate \"%s\" data (%i) - type %u, base %u (%u), num %u, alignment %u\n",
-+	     __func__, alloc.name, ret, alloc.type, ioparam->size,
-+	     alloc.base_unit, alloc.num_unit, alloc.alignement);
-+	if (resource != NULL) {
-+		vc_sm_resource_deceased(resource, 1);
-+		kfree(resource);
-+	}
-+	return ret;
-+}
-+
-+/* Share an allocate memory handle and block.*/
-+int vc_sm_ioctl_alloc_share(struct sm_priv_data_t *private,
-+			    struct vmcs_sm_ioctl_alloc_share *ioparam)
-+{
-+	struct sm_resource_t *resource, *shared_resource;
-+	int ret = 0;
-+
-+	pr_debug("[%s]: attempt to share resource %u\n", __func__,
-+			ioparam->handle);
-+
-+	shared_resource = vmcs_sm_acquire_global_resource(ioparam->handle);
-+	if (shared_resource == NULL) {
-+		ret = -ENOMEM;
-+		goto error;
-+	}
-+
-+	/* Allocate local resource to track this allocation. */
-+	resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-+	if (resource == NULL) {
-+		pr_err("[%s]: failed to allocate local tracking resource\n",
-+			__func__);
-+		ret = -ENOMEM;
-+		goto error;
-+	}
-+	INIT_LIST_HEAD(&resource->map_list);
-+	resource->ref_count++;
-+	resource->pid = current->tgid;
-+
-+	/* Keep track of the resource we created. */
-+	resource->private = private;
-+	resource->res_handle = shared_resource->res_handle;
-+	resource->res_base_mem = shared_resource->res_base_mem;
-+	resource->res_size = shared_resource->res_size;
-+	resource->res_cached = shared_resource->res_cached;
-+	resource->res_shared = shared_resource;
-+
-+	mutex_lock(&sm_state->lock);
-+	resource->res_guid = ++sm_state->guid;
-+	mutex_unlock(&sm_state->lock);
-+	resource->res_guid <<= PAGE_SHIFT;
-+
-+	vmcs_sm_add_resource(private, resource);
-+
-+	pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n",
-+		__func__, resource->res_guid, resource->res_handle,
-+		resource->res_base_mem, resource->res_size,
-+		resource->res_cached);
-+
-+	/* We're done */
-+	resource->res_stats[ALLOC]++;
-+	ioparam->handle = resource->res_guid;
-+	ioparam->size = resource->res_size;
-+	return 0;
-+
-+error:
-+	pr_err("[%s]: failed to share %u\n", __func__, ioparam->handle);
-+	if (shared_resource != NULL)
-+		vmcs_sm_release_resource(shared_resource, 0);
-+
-+	return ret;
-+}
-+
-+/* Free a previously allocated shared memory handle and block.*/
-+static int vc_sm_ioctl_free(struct sm_priv_data_t *private,
-+			    struct vmcs_sm_ioctl_free *ioparam)
-+{
-+	struct sm_resource_t *resource =
-+	    vmcs_sm_acquire_resource(private, ioparam->handle);
-+
-+	if (resource == NULL) {
-+		pr_err("[%s]: resource for guid %u does not exist\n", __func__,
-+			ioparam->handle);
-+		return -EINVAL;
-+	}
-+
-+	/* Check permissions. */
-+	if (resource->pid && (resource->pid != current->tgid)) {
-+		pr_err("[%s]: current tgid %u != %u owner\n",
-+			__func__, current->tgid, resource->pid);
-+		vmcs_sm_release_resource(resource, 0);
-+		return -EPERM;
-+	}
-+
-+	vmcs_sm_release_resource(resource, 0);
-+	vmcs_sm_release_resource(resource, 0);
-+	return 0;
-+}
-+
-+/* Resize a previously allocated shared memory handle and block. */
-+static int vc_sm_ioctl_resize(struct sm_priv_data_t *private,
-+			      struct vmcs_sm_ioctl_resize *ioparam)
-+{
-+	int ret = 0;
-+	int status;
-+	struct vc_sm_resize_t resize;
-+	struct sm_resource_t *resource;
-+
-+	/* Locate resource from GUID. */
-+	resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+	if (!resource) {
-+		pr_err("[%s]: failed resource - guid %x\n",
-+				__func__, ioparam->handle);
-+		ret = -EFAULT;
-+		goto error;
-+	}
-+
-+	/*
-+	 * If the resource is locked, its reference count will be not NULL,
-+	 * in which case we will not be allowed to resize it anyways, so
-+	 * reject the attempt here.
-+	 */
-+	if (resource->lock_count != 0) {
-+		pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n",
-+		     __func__, ioparam->handle, resource->lock_count);
-+		ret = -EFAULT;
-+		goto error;
-+	}
-+
-+	/* Check permissions. */
-+	if (resource->pid && (resource->pid != current->tgid)) {
-+		pr_err("[%s]: current tgid %u != %u owner\n", __func__,
-+				current->tgid, resource->pid);
-+		ret = -EPERM;
-+		goto error;
-+	}
-+
-+	if (resource->map_count != 0) {
-+		pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n",
-+		     __func__, ioparam->handle, resource->map_count);
-+		ret = -EFAULT;
-+		goto error;
-+	}
-+
-+	resize.res_handle = resource->res_handle;
-+	resize.res_mem = (uint32_t)resource->res_base_mem;
-+	resize.res_new_size = ioparam->new_size;
-+
-+	pr_debug("[%s]: attempt to resize data - guid %x, hdl %x, base address %p\n",
-+		__func__, ioparam->handle, resize.res_handle,
-+		(void *)resize.res_mem);
-+
-+	/* Resize the videocore allocated resource. */
-+	status = vc_vchi_sm_resize(sm_state->sm_handle, &resize,
-+				   &private->int_trans_id);
-+	if (status == -EINTR) {
-+		pr_debug("[%s]: requesting resize memory action restart (trans_id: %u)\n",
-+			__func__, private->int_trans_id);
-+		ret = -ERESTARTSYS;
-+		private->restart_sys = -EINTR;
-+		private->int_action = VC_SM_MSG_TYPE_RESIZE;
-+		goto error;
-+	} else if (status) {
-+		pr_err("[%s]: failed to resize memory on videocore (status: %u, trans_id: %u)\n",
-+		     __func__, status, private->int_trans_id);
-+		ret = -EPERM;
-+		goto error;
-+	}
-+
-+	pr_debug("[%s]: success to resize data - hdl %x, size %d -> %d\n",
-+		__func__, resize.res_handle, resource->res_size,
-+		resize.res_new_size);
-+
-+	/* Successfully resized, save the information and inform the user. */
-+	ioparam->old_size = resource->res_size;
-+	resource->res_size = resize.res_new_size;
-+
-+error:
-+	if (resource)
-+		vmcs_sm_release_resource(resource, 0);
-+
-+	return ret;
-+}
-+
-+/* Lock a previously allocated shared memory handle and block. */
-+static int vc_sm_ioctl_lock(struct sm_priv_data_t *private,
-+			    struct vmcs_sm_ioctl_lock_unlock *ioparam,
-+			    int change_cache, enum vmcs_sm_cache_e cache_type,
-+			    unsigned int vc_addr)
-+{
-+	int status;
-+	struct vc_sm_lock_unlock_t lock;
-+	struct vc_sm_lock_result_t result;
-+	struct sm_resource_t *resource;
-+	int ret = 0;
-+	struct sm_mmap *map, *map_tmp;
-+	unsigned long phys_addr;
-+
-+	map = NULL;
-+
-+	/* Locate resource from GUID. */
-+	resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+	if (resource == NULL) {
-+		ret = -EINVAL;
-+		goto error;
-+	}
-+
-+	/* Check permissions. */
-+	if (resource->pid && (resource->pid != current->tgid)) {
-+		pr_err("[%s]: current tgid %u != %u owner\n", __func__,
-+				current->tgid, resource->pid);
-+		ret = -EPERM;
-+		goto error;
-+	}
-+
-+	lock.res_handle = resource->res_handle;
-+	lock.res_mem = (uint32_t)resource->res_base_mem;
-+
-+	/* Take the lock and get the address to be mapped. */
-+	if (vc_addr == 0) {
-+		pr_debug("[%s]: attempt to lock data - guid %x, hdl %x, base address %p\n",
-+			__func__, ioparam->handle, lock.res_handle,
-+			(void *)lock.res_mem);
-+
-+		/* Lock the videocore allocated resource. */
-+		status = vc_vchi_sm_lock(sm_state->sm_handle, &lock, &result,
-+					 &private->int_trans_id);
-+		if (status == -EINTR) {
-+			pr_debug("[%s]: requesting lock memory action restart (trans_id: %u)\n",
-+				__func__, private->int_trans_id);
-+			ret = -ERESTARTSYS;
-+			private->restart_sys = -EINTR;
-+			private->int_action = VC_SM_MSG_TYPE_LOCK;
-+			goto error;
-+		} else if (status ||
-+			   (!status && !(void *)result.res_mem)) {
-+			pr_err("[%s]: failed to lock memory on videocore (status: %u, trans_id: %u)\n",
-+			     __func__, status, private->int_trans_id);
-+			ret = -EPERM;
-+			resource->res_stats[LOCK_FAIL]++;
-+			goto error;
-+		}
-+
-+		pr_debug("[%s]: succeed to lock data - hdl %x, base address %p (%p), ref-cnt %d\n",
-+			__func__, lock.res_handle, (void *)result.res_mem,
-+			(void *)lock.res_mem, resource->lock_count);
-+	}
-+	/* Lock assumed taken already, address to be mapped is known. */
-+	else
-+		resource->res_base_mem = (void *)vc_addr;
-+
-+	resource->res_stats[LOCK]++;
-+	resource->lock_count++;
-+
-+	/* Keep track of the new base memory allocation if it has changed. */
-+	if ((vc_addr == 0) &&
-+	    ((void *)result.res_mem) &&
-+	    ((void *)result.res_old_mem) &&
-+	    (result.res_mem != result.res_old_mem)) {
-+		resource->res_base_mem = (void *)result.res_mem;
-+
-+		/* Kernel allocated resources. */
-+		if (resource->pid == 0) {
-+			if (!list_empty(&resource->map_list)) {
-+				list_for_each_entry_safe(map, map_tmp,
-+							 &resource->map_list,
-+							 resource_map_list) {
-+					if (map->res_addr) {
-+						iounmap((void *)map->res_addr);
-+						map->res_addr = 0;
-+
-+						vmcs_sm_remove_map(sm_state,
-+								map->resource,
-+								map);
-+						break;
-+					}
-+				}
-+			}
-+		}
-+	}
-+
-+	if (change_cache)
-+		resource->res_cached = cache_type;
-+
-+	if (resource->map_count) {
-+		ioparam->addr =
-+		    vmcs_sm_usr_address_from_pid_and_usr_handle(
-+				    current->tgid, ioparam->handle);
-+
-+		pr_debug("[%s] map_count %d private->pid %d current->tgid %d hnd %x addr %u\n",
-+			__func__, resource->map_count, private->pid,
-+			current->tgid, ioparam->handle, ioparam->addr);
-+	} else {
-+		/* Kernel allocated resources. */
-+		if (resource->pid == 0) {
-+			pr_debug("[%s]: attempt mapping kernel resource - guid %x, hdl %x\n",
-+				__func__, ioparam->handle, lock.res_handle);
-+
-+			ioparam->addr = 0;
-+
-+			map = kzalloc(sizeof(*map), GFP_KERNEL);
-+			if (map == NULL) {
-+				pr_err("[%s]: failed allocating tracker\n",
-+						__func__);
-+				ret = -ENOMEM;
-+				goto error;
-+			} else {
-+				phys_addr = (uint32_t)resource->res_base_mem &
-+				    0x3FFFFFFF;
-+				phys_addr += mm_vc_mem_phys_addr;
-+				if (resource->res_cached
-+						== VMCS_SM_CACHE_HOST) {
-+					ioparam->addr = (unsigned long)
-+					/* TODO - make cached work */
-+					    ioremap_nocache(phys_addr,
-+							   resource->res_size);
-+
-+					pr_debug("[%s]: mapping kernel - guid %x, hdl %x - cached mapping %u\n",
-+						__func__, ioparam->handle,
-+						lock.res_handle, ioparam->addr);
-+				} else {
-+					ioparam->addr = (unsigned long)
-+					    ioremap_nocache(phys_addr,
-+							    resource->res_size);
-+
-+					pr_debug("[%s]: mapping kernel- guid %x, hdl %x - non cached mapping %u\n",
-+						__func__, ioparam->handle,
-+						lock.res_handle, ioparam->addr);
-+				}
-+
-+				map->res_pid = 0;
-+				map->res_vc_hdl = resource->res_handle;
-+				map->res_usr_hdl = resource->res_guid;
-+				map->res_addr = ioparam->addr;
-+				map->resource = resource;
-+				map->vma = NULL;
-+
-+				vmcs_sm_add_map(sm_state, resource, map);
-+			}
-+		} else
-+			ioparam->addr = 0;
-+	}
-+
-+error:
-+	if (resource)
-+		vmcs_sm_release_resource(resource, 0);
-+
-+	return ret;
-+}
-+
-+/* Unlock a previously allocated shared memory handle and block.*/
-+static int vc_sm_ioctl_unlock(struct sm_priv_data_t *private,
-+			      struct vmcs_sm_ioctl_lock_unlock *ioparam,
-+			      int flush, int wait_reply, int no_vc_unlock)
-+{
-+	int status;
-+	struct vc_sm_lock_unlock_t unlock;
-+	struct sm_mmap *map, *map_tmp;
-+	struct sm_resource_t *resource;
-+	int ret = 0;
-+
-+	map = NULL;
-+
-+	/* Locate resource from GUID. */
-+	resource = vmcs_sm_acquire_resource(private, ioparam->handle);
-+	if (resource == NULL) {
-+		ret = -EINVAL;
-+		goto error;
-+	}
-+
-+	/* Check permissions. */
-+	if (resource->pid && (resource->pid != current->tgid)) {
-+		pr_err("[%s]: current tgid %u != %u owner\n",
-+			__func__, current->tgid, resource->pid);
-+		ret = -EPERM;
-+		goto error;
-+	}
-+
-+	unlock.res_handle = resource->res_handle;
-+	unlock.res_mem = (uint32_t)resource->res_base_mem;
-+
-+	pr_debug("[%s]: attempt to unlock data - guid %x, hdl %x, base address %p\n",
-+		__func__, ioparam->handle, unlock.res_handle,
-+		(void *)unlock.res_mem);
-+
-+	/* User space allocated resources. */
-+	if (resource->pid) {
-+		/* Flush if requested */
-+		if (resource->res_cached && flush) {
-+			dma_addr_t phys_addr = 0;
-+
-+			resource->res_stats[FLUSH]++;
-+
-+			phys_addr =
-+			    (dma_addr_t)((uint32_t)resource->res_base_mem &
-+					 0x3FFFFFFF);
-+			phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+			/* L1 cache flush */
-+			down_read(&current->mm->mmap_sem);
-+			list_for_each_entry(map, &resource->map_list,
-+					    resource_map_list) {
-+				if (map->vma) {
-+					unsigned long start;
-+					unsigned long end;
-+
-+					start = map->vma->vm_start;
-+					end = map->vma->vm_end;
-+
-+					vcsm_vma_cache_clean_page_range(
-+							start, end);
-+				}
-+			}
-+			up_read(&current->mm->mmap_sem);
-+
-+			/* L2 cache flush */
-+			outer_clean_range(phys_addr,
-+					  phys_addr +
-+					  (size_t) resource->res_size);
-+		}
-+
-+		/* We need to zap all the vmas associated with this resource */
-+		if (resource->lock_count == 1) {
-+			down_read(&current->mm->mmap_sem);
-+			list_for_each_entry(map, &resource->map_list,
-+					    resource_map_list) {
-+				if (map->vma) {
-+					zap_vma_ptes(map->vma,
-+						     map->vma->vm_start,
-+						     map->vma->vm_end -
-+						     map->vma->vm_start);
-+				}
-+			}
-+			up_read(&current->mm->mmap_sem);
-+		}
-+	}
-+	/* Kernel allocated resources. */
-+	else {
-+		/* Global + Taken in this context */
-+		if (resource->ref_count == 2) {
-+			if (!list_empty(&resource->map_list)) {
-+				list_for_each_entry_safe(map, map_tmp,
-+						&resource->map_list,
-+						resource_map_list) {
-+					if (map->res_addr) {
-+						if (flush &&
-+								(resource->res_cached ==
-+									VMCS_SM_CACHE_HOST)) {
-+							unsigned long
-+								phys_addr;
-+							phys_addr = (uint32_t)
-+								resource->res_base_mem & 0x3FFFFFFF;
-+							phys_addr +=
-+								mm_vc_mem_phys_addr;
-+
-+							/* L1 cache flush */
-+							dmac_flush_range((const
-+										void
-+										*)
-+									map->res_addr, (const void *)
-+									(map->res_addr + resource->res_size));
-+
-+							/* L2 cache flush */
-+							outer_clean_range
-+								(phys_addr,
-+								 phys_addr +
-+								 (size_t)
-+								 resource->res_size);
-+						}
-+
-+						iounmap((void *)map->res_addr);
-+						map->res_addr = 0;
-+
-+						vmcs_sm_remove_map(sm_state,
-+								map->resource,
-+								map);
-+						break;
-+					}
-+				}
-+			}
-+		}
-+	}
-+
-+	if (resource->lock_count) {
-+		/* Bypass the videocore unlock. */
-+		if (no_vc_unlock)
-+			status = 0;
-+		/* Unlock the videocore allocated resource. */
-+		else {
-+			status =
-+			    vc_vchi_sm_unlock(sm_state->sm_handle, &unlock,
-+					      &private->int_trans_id,
-+					      wait_reply);
-+			if (status == -EINTR) {
-+				pr_debug("[%s]: requesting unlock memory action restart (trans_id: %u)\n",
-+					__func__, private->int_trans_id);
-+
-+				ret = -ERESTARTSYS;
-+				resource->res_stats[UNLOCK]--;
-+				private->restart_sys = -EINTR;
-+				private->int_action = VC_SM_MSG_TYPE_UNLOCK;
-+				goto error;
-+			} else if (status != 0) {
-+				pr_err("[%s]: failed to unlock vc mem (status: %u, trans_id: %u)\n",
-+				     __func__, status, private->int_trans_id);
-+
-+				ret = -EPERM;
-+				resource->res_stats[UNLOCK_FAIL]++;
-+				goto error;
-+			}
-+		}
-+
-+		resource->res_stats[UNLOCK]++;
-+		resource->lock_count--;
-+	}
-+
-+	pr_debug("[%s]: success to unlock data - hdl %x, base address %p, ref-cnt %d\n",
-+		__func__, unlock.res_handle, (void *)unlock.res_mem,
-+		resource->lock_count);
-+
-+error:
-+	if (resource)
-+		vmcs_sm_release_resource(resource, 0);
-+
-+	return ret;
-+}
-+
-+/* Import a contiguous block of memory to be shared with VC. */
-+int vc_sm_ioctl_import_dmabuf(struct sm_priv_data_t *private,
-+			      struct vmcs_sm_ioctl_import_dmabuf *ioparam,
-+			      struct dma_buf *src_dma_buf)
-+{
-+	int ret = 0;
-+	int status;
-+	struct sm_resource_t *resource = NULL;
-+	struct vc_sm_import import = { 0 };
-+	struct vc_sm_import_result result = { 0 };
-+	struct dma_buf *dma_buf;
-+	struct dma_buf_attachment *attach = NULL;
-+	struct sg_table *sgt = NULL;
-+
-+	/* Setup our allocation parameters */
-+	if (src_dma_buf) {
-+		get_dma_buf(src_dma_buf);
-+		dma_buf = src_dma_buf;
-+	} else {
-+		dma_buf = dma_buf_get(ioparam->dmabuf_fd);
-+	}
-+	if (IS_ERR(dma_buf))
-+		return PTR_ERR(dma_buf);
-+
-+	attach = dma_buf_attach(dma_buf, &sm_state->pdev->dev);
-+	if (IS_ERR(attach)) {
-+		ret = PTR_ERR(attach);
-+		goto error;
-+	}
-+
-+	sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
-+	if (IS_ERR(sgt)) {
-+		ret = PTR_ERR(sgt);
-+		goto error;
-+	}
-+
-+	/* Verify that the address block is contiguous */
-+	if (sgt->nents != 1) {
-+		ret = -ENOMEM;
-+		goto error;
-+	}
-+
-+	import.type = ((ioparam->cached == VMCS_SM_CACHE_VC) ||
-+		       (ioparam->cached == VMCS_SM_CACHE_BOTH)) ?
-+				VC_SM_ALLOC_CACHED : VC_SM_ALLOC_NON_CACHED;
-+	import.addr = (uint32_t)sg_dma_address(sgt->sgl);
-+	import.size = sg_dma_len(sgt->sgl);
-+	import.allocator = current->tgid;
-+
-+	if (*ioparam->name)
-+		memcpy(import.name, ioparam->name, sizeof(import.name) - 1);
-+	else
-+		memcpy(import.name, VMCS_SM_RESOURCE_NAME_DEFAULT,
-+		       sizeof(VMCS_SM_RESOURCE_NAME_DEFAULT));
-+
-+	pr_debug("[%s]: attempt to import \"%s\" data - type %u, addr %p, size %u\n",
-+		 __func__, import.name, import.type,
-+		 (void *)import.addr, import.size);
-+
-+	/* Allocate local resource to track this allocation. */
-+	resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-+	if (!resource) {
-+		ret = -ENOMEM;
-+		goto error;
-+	}
-+	INIT_LIST_HEAD(&resource->map_list);
-+	resource->ref_count++;
-+	resource->pid = current->tgid;
-+
-+	/* Allocate the videocore resource. */
-+	status = vc_vchi_sm_import(sm_state->sm_handle, &import, &result,
-+				   &private->int_trans_id);
-+	if (status == -EINTR) {
-+		pr_debug("[%s]: requesting import memory action restart (trans_id: %u)\n",
-+			 __func__, private->int_trans_id);
-+		ret = -ERESTARTSYS;
-+		private->restart_sys = -EINTR;
-+		private->int_action = VC_SM_MSG_TYPE_IMPORT;
-+		goto error;
-+	} else if (status || !result.res_handle) {
-+		pr_debug("[%s]: failed to import memory on videocore (status: %u, trans_id: %u)\n",
-+			 __func__, status, private->int_trans_id);
-+		ret = -ENOMEM;
-+		resource->res_stats[ALLOC_FAIL]++;
-+		goto error;
-+	}
-+
-+	/* Keep track of the resource we created. */
-+	resource->private = private;
-+	resource->res_handle = result.res_handle;
-+	resource->res_size = import.size;
-+	resource->res_cached = ioparam->cached;
-+
-+	resource->dma_buf = dma_buf;
-+	resource->attach = attach;
-+	resource->sgt = sgt;
-+	resource->dma_addr = sg_dma_address(sgt->sgl);
-+
-+	/*
-+	 * Kernel/user GUID.  This global identifier is used for mmap'ing the
-+	 * allocated region from user space, it is passed as the mmap'ing
-+	 * offset, we use it to 'hide' the videocore handle/address.
-+	 */
-+	mutex_lock(&sm_state->lock);
-+	resource->res_guid = ++sm_state->guid;
-+	mutex_unlock(&sm_state->lock);
-+	resource->res_guid <<= PAGE_SHIFT;
-+
-+	vmcs_sm_add_resource(private, resource);
-+
-+	/* We're done */
-+	resource->res_stats[IMPORT]++;
-+	ioparam->handle = resource->res_guid;
-+	return 0;
-+
-+error:
-+	resource->res_stats[IMPORT_FAIL]++;
-+	if (resource) {
-+		vc_sm_resource_deceased(resource, 1);
-+		kfree(resource);
-+	}
-+	if (sgt)
-+		dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);
-+	if (attach)
-+		dma_buf_detach(dma_buf, attach);
-+	dma_buf_put(dma_buf);
-+	return ret;
-+}
-+
-+/* Handle control from host. */
-+static long vc_sm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+	int ret = 0;
-+	unsigned int cmdnr = _IOC_NR(cmd);
-+	struct sm_priv_data_t *file_data =
-+	    (struct sm_priv_data_t *)file->private_data;
-+	struct sm_resource_t *resource = NULL;
-+
-+	/* Validate we can work with this device. */
-+	if ((sm_state == NULL) || (file_data == NULL)) {
-+		pr_err("[%s]: invalid device\n", __func__);
-+		ret = -EPERM;
-+		goto out;
-+	}
-+
-+	pr_debug("[%s]: cmd %x tgid %u, owner %u\n", __func__, cmdnr,
-+			current->tgid, file_data->pid);
-+
-+	/* Action is a re-post of a previously interrupted action? */
-+	if (file_data->restart_sys == -EINTR) {
-+		struct vc_sm_action_clean_t action_clean;
-+
-+		pr_debug("[%s]: clean up of action %u (trans_id: %u) following EINTR\n",
-+			__func__, file_data->int_action,
-+			file_data->int_trans_id);
-+
-+		action_clean.res_action = file_data->int_action;
-+		action_clean.action_trans_id = file_data->int_trans_id;
-+
-+		vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean);
-+
-+		file_data->restart_sys = 0;
-+	}
-+
-+	/* Now process the command. */
-+	switch (cmdnr) {
-+		/* New memory allocation.
-+		 */
-+	case VMCS_SM_CMD_ALLOC:
-+		{
-+			struct vmcs_sm_ioctl_alloc ioparam;
-+
-+			/* Get the parameter data. */
-+			if (copy_from_user
-+			    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ret = vc_sm_ioctl_alloc(file_data, &ioparam);
-+			if (!ret &&
-+			    (copy_to_user((void *)arg,
-+					  &ioparam, sizeof(ioparam)) != 0)) {
-+				struct vmcs_sm_ioctl_free freeparam = {
-+					ioparam.handle
-+				};
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+						__func__, cmdnr);
-+				vc_sm_ioctl_free(file_data, &freeparam);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Share existing memory allocation. */
-+	case VMCS_SM_CMD_ALLOC_SHARE:
-+		{
-+			struct vmcs_sm_ioctl_alloc_share ioparam;
-+
-+			/* Get the parameter data. */
-+			if (copy_from_user
-+			    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ret = vc_sm_ioctl_alloc_share(file_data, &ioparam);
-+
-+			/* Copy result back to user. */
-+			if (!ret
-+			    && copy_to_user((void *)arg, &ioparam,
-+					    sizeof(ioparam)) != 0) {
-+				struct vmcs_sm_ioctl_free freeparam = {
-+					ioparam.handle
-+				};
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+						__func__, cmdnr);
-+				vc_sm_ioctl_free(file_data, &freeparam);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+	case VMCS_SM_CMD_IMPORT_DMABUF:
-+		{
-+			struct vmcs_sm_ioctl_import_dmabuf ioparam;
-+
-+			/* Get the parameter data. */
-+			if (copy_from_user
-+			    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+				       __func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ret = vc_sm_ioctl_import_dmabuf(file_data, &ioparam,
-+							NULL);
-+			if (!ret &&
-+			    (copy_to_user((void *)arg,
-+					  &ioparam, sizeof(ioparam)) != 0)) {
-+				struct vmcs_sm_ioctl_free freeparam = {
-+					ioparam.handle
-+				};
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				       __func__, cmdnr);
-+				vc_sm_ioctl_free(file_data, &freeparam);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Lock (attempt to) *and* register a cache behavior change. */
-+	case VMCS_SM_CMD_LOCK_CACHE:
-+		{
-+			struct vmcs_sm_ioctl_lock_cache ioparam;
-+			struct vmcs_sm_ioctl_lock_unlock lock;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user
-+			    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			lock.handle = ioparam.handle;
-+			ret =
-+			    vc_sm_ioctl_lock(file_data, &lock, 1,
-+					     ioparam.cached, 0);
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Lock (attempt to) existing memory allocation. */
-+	case VMCS_SM_CMD_LOCK:
-+		{
-+			struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user
-+			    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ret = vc_sm_ioctl_lock(file_data, &ioparam, 0, 0, 0);
-+
-+			/* Copy result back to user. */
-+			if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam))
-+			    != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				     __func__, cmdnr);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Unlock (attempt to) existing memory allocation. */
-+	case VMCS_SM_CMD_UNLOCK:
-+		{
-+			struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user
-+			    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ret = vc_sm_ioctl_unlock(file_data, &ioparam, 0, 1, 0);
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Resize (attempt to) existing memory allocation. */
-+	case VMCS_SM_CMD_RESIZE:
-+		{
-+			struct vmcs_sm_ioctl_resize ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user
-+			    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ret = vc_sm_ioctl_resize(file_data, &ioparam);
-+
-+			/* Copy result back to user. */
-+			if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam))
-+			    != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				     __func__, cmdnr);
-+				ret = -EFAULT;
-+			}
-+			goto out;
-+		}
-+		break;
-+
-+		/* Terminate existing memory allocation.
-+		 */
-+	case VMCS_SM_CMD_FREE:
-+		{
-+			struct vmcs_sm_ioctl_free ioparam;
-+
-+			/* Get parameter data.
-+			 */
-+			if (copy_from_user
-+			    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ret = vc_sm_ioctl_free(file_data, &ioparam);
-+
-+			/* Done.
-+			 */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Walk allocation on videocore, information shows up in the
-+		 ** videocore log.
-+		 */
-+	case VMCS_SM_CMD_VC_WALK_ALLOC:
-+		{
-+			pr_debug("[%s]: invoking walk alloc\n", __func__);
-+
-+			if (vc_vchi_sm_walk_alloc(sm_state->sm_handle) != 0)
-+				pr_err("[%s]: failed to walk-alloc on videocore\n",
-+				     __func__);
-+
-+			/* Done.
-+			 */
-+			goto out;
-+		}
-+		break;
-+		/* Walk mapping table on host, information shows up in the
-+		 ** kernel log.
-+		 */
-+	case VMCS_SM_CMD_HOST_WALK_MAP:
-+		{
-+			/* Use pid of -1 to tell to walk the whole map. */
-+			vmcs_sm_host_walk_map_per_pid(-1);
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Walk mapping table per process on host.  */
-+	case VMCS_SM_CMD_HOST_WALK_PID_ALLOC:
-+		{
-+			struct vmcs_sm_ioctl_walk ioparam;
-+
-+			/* Get parameter data.  */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			vmcs_sm_host_walk_alloc(file_data);
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Walk allocation per process on host.  */
-+	case VMCS_SM_CMD_HOST_WALK_PID_MAP:
-+		{
-+			struct vmcs_sm_ioctl_walk ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			vmcs_sm_host_walk_map_per_pid(ioparam.pid);
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Gets the size of the memory associated with a user handle. */
-+	case VMCS_SM_CMD_SIZE_USR_HANDLE:
-+		{
-+			struct vmcs_sm_ioctl_size ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			/* Locate resource from GUID. */
-+			resource =
-+			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+			if (resource != NULL) {
-+				ioparam.size = resource->res_size;
-+				vmcs_sm_release_resource(resource, 0);
-+			} else {
-+				ioparam.size = 0;
-+			}
-+
-+			if (copy_to_user((void *)arg,
-+					 &ioparam, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				     __func__, cmdnr);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Verify we are dealing with a valid resource. */
-+	case VMCS_SM_CMD_CHK_USR_HANDLE:
-+		{
-+			struct vmcs_sm_ioctl_chk ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			/* Locate resource from GUID. */
-+			resource =
-+			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+			if (resource == NULL)
-+				ret = -EINVAL;
-+			/*
-+			 * If the resource is cacheable, return additional
-+			 * information that may be needed to flush the cache.
-+			 */
-+			else if ((resource->res_cached == VMCS_SM_CACHE_HOST) ||
-+				 (resource->res_cached == VMCS_SM_CACHE_BOTH)) {
-+				ioparam.addr =
-+				    vmcs_sm_usr_address_from_pid_and_usr_handle
-+				    (current->tgid, ioparam.handle);
-+				ioparam.size = resource->res_size;
-+				ioparam.cache = resource->res_cached;
-+			} else {
-+				ioparam.addr = 0;
-+				ioparam.size = 0;
-+				ioparam.cache = resource->res_cached;
-+			}
-+
-+			if (resource)
-+				vmcs_sm_release_resource(resource, 0);
-+
-+			if (copy_to_user((void *)arg,
-+					 &ioparam, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/*
-+		 * Maps a user handle given the process and the virtual address.
-+		 */
-+	case VMCS_SM_CMD_MAPPED_USR_HANDLE:
-+		{
-+			struct vmcs_sm_ioctl_map ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ioparam.handle =
-+			    vmcs_sm_usr_handle_from_pid_and_address(
-+					    ioparam.pid, ioparam.addr);
-+
-+			resource =
-+			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+			if ((resource != NULL)
-+			    && ((resource->res_cached == VMCS_SM_CACHE_HOST)
-+				|| (resource->res_cached ==
-+				    VMCS_SM_CACHE_BOTH))) {
-+				ioparam.size = resource->res_size;
-+			} else {
-+				ioparam.size = 0;
-+			}
-+
-+			if (resource)
-+				vmcs_sm_release_resource(resource, 0);
-+
-+			if (copy_to_user((void *)arg,
-+					 &ioparam, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				     __func__, cmdnr);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/*
-+		 * Maps a videocore handle given process and virtual address.
-+		 */
-+	case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR:
-+		{
-+			struct vmcs_sm_ioctl_map ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			ioparam.handle = vmcs_sm_vc_handle_from_pid_and_address(
-+					    ioparam.pid, ioparam.addr);
-+
-+			if (copy_to_user((void *)arg,
-+					 &ioparam, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				     __func__, cmdnr);
-+
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Maps a videocore handle given process and user handle. */
-+	case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL:
-+		{
-+			struct vmcs_sm_ioctl_map ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			/* Locate resource from GUID. */
-+			resource =
-+			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+			if (resource != NULL) {
-+				ioparam.handle = resource->res_handle;
-+				vmcs_sm_release_resource(resource, 0);
-+			} else {
-+				ioparam.handle = 0;
-+			}
-+
-+			if (copy_to_user((void *)arg,
-+					 &ioparam, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				     __func__, cmdnr);
-+
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/*
-+		 * Maps a videocore address given process and videocore handle.
-+		 */
-+	case VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL:
-+		{
-+			struct vmcs_sm_ioctl_map ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			/* Locate resource from GUID. */
-+			resource =
-+			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+			if (resource != NULL) {
-+				ioparam.addr =
-+					(unsigned int)resource->res_base_mem;
-+				vmcs_sm_release_resource(resource, 0);
-+			} else {
-+				ioparam.addr = 0;
-+			}
-+
-+			if (copy_to_user((void *)arg,
-+					 &ioparam, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				     __func__, cmdnr);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Maps a user address given process and vc handle. */
-+	case VMCS_SM_CMD_MAPPED_USR_ADDRESS:
-+		{
-+			struct vmcs_sm_ioctl_map ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			/*
-+			 * Return the address information from the mapping,
-+			 * 0 (ie NULL) if it cannot locate the actual mapping.
-+			 */
-+			ioparam.addr =
-+			    vmcs_sm_usr_address_from_pid_and_usr_handle
-+			    (ioparam.pid, ioparam.handle);
-+
-+			if (copy_to_user((void *)arg,
-+					 &ioparam, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-to-user for cmd %x\n",
-+				     __func__, cmdnr);
-+				ret = -EFAULT;
-+			}
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Flush the cache for a given mapping. */
-+	case VMCS_SM_CMD_FLUSH:
-+		{
-+			struct vmcs_sm_ioctl_cache ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			/* Locate resource from GUID. */
-+			resource =
-+			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+
-+			if ((resource != NULL) && resource->res_cached) {
-+				dma_addr_t phys_addr = 0;
-+
-+				resource->res_stats[FLUSH]++;
-+
-+				phys_addr =
-+				    (dma_addr_t)((uint32_t)
-+						 resource->res_base_mem &
-+						 0x3FFFFFFF);
-+				phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+				/* L1 cache flush */
-+				down_read(&current->mm->mmap_sem);
-+				vcsm_vma_cache_clean_page_range((unsigned long)
-+								ioparam.addr,
-+								(unsigned long)
-+								ioparam.addr +
-+								ioparam.size);
-+				up_read(&current->mm->mmap_sem);
-+
-+				/* L2 cache flush */
-+				outer_clean_range(phys_addr,
-+						  phys_addr +
-+						  (size_t) ioparam.size);
-+			} else if (resource == NULL) {
-+				ret = -EINVAL;
-+				goto out;
-+			}
-+
-+			if (resource)
-+				vmcs_sm_release_resource(resource, 0);
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+		/* Invalidate the cache for a given mapping. */
-+	case VMCS_SM_CMD_INVALID:
-+		{
-+			struct vmcs_sm_ioctl_cache ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+
-+			/* Locate resource from GUID. */
-+			resource =
-+			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
-+
-+			if ((resource != NULL) && resource->res_cached) {
-+				dma_addr_t phys_addr = 0;
-+
-+				resource->res_stats[INVALID]++;
-+
-+				phys_addr =
-+				    (dma_addr_t)((uint32_t)
-+						 resource->res_base_mem &
-+						 0x3FFFFFFF);
-+				phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
-+
-+				/* L2 cache invalidate */
-+				outer_inv_range(phys_addr,
-+						phys_addr +
-+						(size_t) ioparam.size);
-+
-+				/* L1 cache invalidate */
-+				down_read(&current->mm->mmap_sem);
-+				vcsm_vma_cache_clean_page_range((unsigned long)
-+								ioparam.addr,
-+								(unsigned long)
-+								ioparam.addr +
-+								ioparam.size);
-+				up_read(&current->mm->mmap_sem);
-+			} else if (resource == NULL) {
-+				ret = -EINVAL;
-+				goto out;
-+			}
-+
-+			if (resource)
-+				vmcs_sm_release_resource(resource, 0);
-+
-+			/* Done. */
-+			goto out;
-+		}
-+		break;
-+
-+	/* Flush/Invalidate the cache for a given mapping. */
-+	case VMCS_SM_CMD_CLEAN_INVALID:
-+		{
-+			int i;
-+			struct vmcs_sm_ioctl_clean_invalid ioparam;
-+
-+			/* Get parameter data. */
-+			if (copy_from_user(&ioparam,
-+					   (void *)arg, sizeof(ioparam)) != 0) {
-+				pr_err("[%s]: failed to copy-from-user for cmd %x\n",
-+						__func__, cmdnr);
-+				ret = -EFAULT;
-+				goto out;
-+			}
-+			for (i = 0; i < sizeof(ioparam.s) / sizeof(*ioparam.s); i++) {
-+				switch (ioparam.s[i].cmd) {
-+				case VCSM_CACHE_OP_INV:	/* L1/L2 invalidate virtual range */
-+				case VCSM_CACHE_OP_FLUSH: /* L1/L2 clean physical range */
-+				case VCSM_CACHE_OP_CLEAN: /* L1/L2 clean+invalidate all */
-+					/* Locate resource from GUID. */
-+					resource =
-+					    vmcs_sm_acquire_resource(file_data, ioparam.s[i].handle);
-+
-+					if ((resource != NULL) && resource->res_cached) {
-+						unsigned long base = ioparam.s[i].addr & ~(PAGE_SIZE - 1);
-+						unsigned long end = (ioparam.s[i].addr + ioparam.s[i].size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
-+
-+						resource->res_stats[ioparam.s[i].cmd == 1 ? INVALID : FLUSH]++;
-+
-+						/* L1/L2 cache flush */
-+						down_read(&current->mm->mmap_sem);
-+						vcsm_vma_cache_clean_page_range(base, end);
-+						up_read(&current->mm->mmap_sem);
-+					} else if (resource == NULL) {
-+						ret = -EINVAL;
-+						goto out;
-+					}
-+
-+					if (resource)
-+						vmcs_sm_release_resource(resource, 0);
-+
-+					break;
-+				default:
-+					break; /* NOOP */
-+				}
-+			}
-+		}
-+		break;
-+	/* Flush/Invalidate the cache for a given mapping. */
-+	case VMCS_SM_CMD_CLEAN_INVALID2:
-+		{
-+				int i, j;
-+				struct vmcs_sm_ioctl_clean_invalid2 ioparam;
-+				struct vmcs_sm_ioctl_clean_invalid_block *block = NULL;
-+
-+				/* Get parameter data. */
-+				if (copy_from_user(&ioparam,
-+						   (void *)arg, sizeof(ioparam)) != 0) {
-+					pr_err("[%s]: failed to copy-from-user header for cmd %x\n",
-+							__func__, cmdnr);
-+					ret = -EFAULT;
-+					goto out;
-+				}
-+				block = kmalloc(ioparam.op_count *
-+						sizeof(struct vmcs_sm_ioctl_clean_invalid_block),
-+						GFP_KERNEL);
-+				if (!block) {
-+					ret = -EFAULT;
-+					goto out;
-+				}
-+				if (copy_from_user(block,
-+						   (void *)(arg + sizeof(ioparam)), ioparam.op_count * sizeof(struct vmcs_sm_ioctl_clean_invalid_block)) != 0) {
-+					pr_err("[%s]: failed to copy-from-user payload for cmd %x\n",
-+							__func__, cmdnr);
-+					ret = -EFAULT;
-+					goto out;
-+				}
-+
-+				for (i = 0; i < ioparam.op_count; i++) {
-+					const struct vmcs_sm_ioctl_clean_invalid_block * const op = block + i;
-+					void (*op_fn)(const void *, const void *);
-+
-+					switch(op->invalidate_mode & 3) {
-+						case VCSM_CACHE_OP_INV:
-+							op_fn = dmac_inv_range;
-+							break;
-+						case VCSM_CACHE_OP_CLEAN:
-+							op_fn = dmac_clean_range;
-+							break;
-+						case VCSM_CACHE_OP_FLUSH:
-+							op_fn = dmac_flush_range;
-+							break;
-+						default:
-+							op_fn = 0;
-+							break;
-+					}
-+
-+					if ((op->invalidate_mode & ~3) != 0) {
-+						ret = -EINVAL;
-+						break;
-+					}
-+
-+					if (op_fn == 0)
-+						continue;
-+
-+					for (j = 0; j < op->block_count; ++j) {
-+						const char * const base = (const char *)op->start_address + j * op->inter_block_stride;
-+						const char * const end = base + op->block_size;
-+						op_fn(base, end);
-+					}
-+				}
-+				kfree(block);
-+			}
-+		break;
-+
-+	default:
-+		{
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+		break;
-+	}
-+
-+out:
-+	return ret;
-+}
-+
-+/* Device operations that we managed in this driver. */
-+static const struct file_operations vmcs_sm_ops = {
-+	.owner = THIS_MODULE,
-+	.unlocked_ioctl = vc_sm_ioctl,
-+	.open = vc_sm_open,
-+	.release = vc_sm_release,
-+	.mmap = vc_sm_mmap,
-+};
-+
-+/* Creation of device. */
-+static int vc_sm_create_sharedmemory(void)
-+{
-+	int ret;
-+
-+	if (sm_state == NULL) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	/* Create a device class for creating dev nodes. */
-+	sm_state->sm_class = class_create(THIS_MODULE, "vc-sm");
-+	if (IS_ERR(sm_state->sm_class)) {
-+		pr_err("[%s]: unable to create device class\n", __func__);
-+		ret = PTR_ERR(sm_state->sm_class);
-+		goto out;
-+	}
-+
-+	/* Create a character driver. */
-+	ret = alloc_chrdev_region(&sm_state->sm_devid,
-+				  DEVICE_MINOR, 1, DEVICE_NAME);
-+	if (ret != 0) {
-+		pr_err("[%s]: unable to allocate device number\n", __func__);
-+		goto out_dev_class_destroy;
-+	}
-+
-+	cdev_init(&sm_state->sm_cdev, &vmcs_sm_ops);
-+	ret = cdev_add(&sm_state->sm_cdev, sm_state->sm_devid, 1);
-+	if (ret != 0) {
-+		pr_err("[%s]: unable to register device\n", __func__);
-+		goto out_chrdev_unreg;
-+	}
-+
-+	/* Create a device node. */
-+	sm_state->sm_dev = device_create(sm_state->sm_class,
-+					 NULL,
-+					 MKDEV(MAJOR(sm_state->sm_devid),
-+					       DEVICE_MINOR), NULL,
-+					 DEVICE_NAME);
-+	if (IS_ERR(sm_state->sm_dev)) {
-+		pr_err("[%s]: unable to create device node\n", __func__);
-+		ret = PTR_ERR(sm_state->sm_dev);
-+		goto out_chrdev_del;
-+	}
-+
-+	goto out;
-+
-+out_chrdev_del:
-+	cdev_del(&sm_state->sm_cdev);
-+out_chrdev_unreg:
-+	unregister_chrdev_region(sm_state->sm_devid, 1);
-+out_dev_class_destroy:
-+	class_destroy(sm_state->sm_class);
-+	sm_state->sm_class = NULL;
-+out:
-+	return ret;
-+}
-+
-+/* Termination of the device. */
-+static int vc_sm_remove_sharedmemory(void)
-+{
-+	int ret;
-+
-+	if (sm_state == NULL) {
-+		/* Nothing to do. */
-+		ret = 0;
-+		goto out;
-+	}
-+
-+	/* Remove the sharedmemory character driver. */
-+	cdev_del(&sm_state->sm_cdev);
-+
-+	/* Unregister region. */
-+	unregister_chrdev_region(sm_state->sm_devid, 1);
-+
-+	ret = 0;
-+	goto out;
-+
-+out:
-+	return ret;
-+}
-+
-+/* Videocore connected.  */
-+static void vc_sm_connected_init(void)
-+{
-+	int ret;
-+	VCHI_INSTANCE_T vchi_instance;
-+	VCHI_CONNECTION_T *vchi_connection = NULL;
-+
-+	pr_info("[%s]: start\n", __func__);
-+
-+	/*
-+	 * Initialize and create a VCHI connection for the shared memory service
-+	 * running on videocore.
-+	 */
-+	ret = vchi_initialise(&vchi_instance);
-+	if (ret != 0) {
-+		pr_err("[%s]: failed to initialise VCHI instance (ret=%d)\n",
-+			__func__, ret);
-+
-+		ret = -EIO;
-+		goto err_free_mem;
-+	}
-+
-+	ret = vchi_connect(NULL, 0, vchi_instance);
-+	if (ret != 0) {
-+		pr_err("[%s]: failed to connect VCHI instance (ret=%d)\n",
-+			__func__, ret);
-+
-+		ret = -EIO;
-+		goto err_free_mem;
-+	}
-+
-+	/* Initialize an instance of the shared memory service. */
-+	sm_state->sm_handle =
-+	    vc_vchi_sm_init(vchi_instance, &vchi_connection, 1);
-+	if (sm_state->sm_handle == NULL) {
-+		pr_err("[%s]: failed to initialize shared memory service\n",
-+			__func__);
-+
-+		ret = -EPERM;
-+		goto err_free_mem;
-+	}
-+
-+	/* Create a debug fs directory entry (root). */
-+	sm_state->dir_root = debugfs_create_dir(VC_SM_DIR_ROOT_NAME, NULL);
-+	if (!sm_state->dir_root) {
-+		pr_err("[%s]: failed to create \'%s\' directory entry\n",
-+			__func__, VC_SM_DIR_ROOT_NAME);
-+
-+		ret = -EPERM;
-+		goto err_stop_sm_service;
-+	}
-+
-+	sm_state->dir_state.show = &vc_sm_global_state_show;
-+	sm_state->dir_state.dir_entry = debugfs_create_file(VC_SM_STATE,
-+			0444, sm_state->dir_root, &sm_state->dir_state,
-+			&vc_sm_debug_fs_fops);
-+
-+	sm_state->dir_stats.show = &vc_sm_global_statistics_show;
-+	sm_state->dir_stats.dir_entry = debugfs_create_file(VC_SM_STATS,
-+			0444, sm_state->dir_root, &sm_state->dir_stats,
-+			&vc_sm_debug_fs_fops);
-+
-+	/* Create the proc entry children. */
-+	sm_state->dir_alloc = debugfs_create_dir(VC_SM_DIR_ALLOC_NAME,
-+			sm_state->dir_root);
-+
-+	/* Create a shared memory device. */
-+	ret = vc_sm_create_sharedmemory();
-+	if (ret != 0) {
-+		pr_err("[%s]: failed to create shared memory device\n",
-+			__func__);
-+		goto err_remove_debugfs;
-+	}
-+
-+	INIT_LIST_HEAD(&sm_state->map_list);
-+	INIT_LIST_HEAD(&sm_state->resource_list);
-+
-+	sm_state->data_knl = vc_sm_create_priv_data(0);
-+	if (sm_state->data_knl == NULL) {
-+		pr_err("[%s]: failed to create kernel private data tracker\n",
-+			__func__);
-+		goto err_remove_shared_memory;
-+	}
-+
-+	/* Done! */
-+	sm_inited = 1;
-+	goto out;
-+
-+err_remove_shared_memory:
-+	vc_sm_remove_sharedmemory();
-+err_remove_debugfs:
-+	debugfs_remove_recursive(sm_state->dir_root);
-+err_stop_sm_service:
-+	vc_vchi_sm_stop(&sm_state->sm_handle);
-+err_free_mem:
-+	kfree(sm_state);
-+out:
-+	pr_info("[%s]: end - returning %d\n", __func__, ret);
-+}
-+
-+/* Driver loading. */
-+static int bcm2835_vcsm_probe(struct platform_device *pdev)
-+{
-+	pr_info("vc-sm: Videocore shared memory driver\n");
-+
-+	sm_state = kzalloc(sizeof(*sm_state), GFP_KERNEL);
-+	if (!sm_state)
-+		return -ENOMEM;
-+	sm_state->pdev = pdev;
-+	mutex_init(&sm_state->lock);
-+	mutex_init(&sm_state->map_lock);
-+
-+	vchiq_add_connected_callback(vc_sm_connected_init);
-+	return 0;
-+}
-+
-+/* Driver unloading. */
-+static int bcm2835_vcsm_remove(struct platform_device *pdev)
-+{
-+	pr_debug("[%s]: start\n", __func__);
-+	if (sm_inited) {
-+		/* Remove shared memory device. */
-+		vc_sm_remove_sharedmemory();
-+
-+		/* Remove all proc entries. */
-+		debugfs_remove_recursive(sm_state->dir_root);
-+
-+		/* Stop the videocore shared memory service. */
-+		vc_vchi_sm_stop(&sm_state->sm_handle);
-+
-+		/* Free the memory for the state structure. */
-+		mutex_destroy(&(sm_state->map_lock));
-+		kfree(sm_state);
-+	}
-+
-+	pr_debug("[%s]: end\n", __func__);
-+	return 0;
-+}
-+
-+#if defined(__KERNEL__)
-+/* Allocate a shared memory handle and block. */
-+int vc_sm_alloc(struct vc_sm_alloc_t *alloc, int *handle)
-+{
-+	struct vmcs_sm_ioctl_alloc ioparam = { 0 };
-+	int ret;
-+	struct sm_resource_t *resource;
-+
-+	/* Validate we can work with this device. */
-+	if (sm_state == NULL || alloc == NULL || handle == NULL) {
-+		pr_err("[%s]: invalid input\n", __func__);
-+		return -EPERM;
-+	}
-+
-+	ioparam.size = alloc->base_unit;
-+	ioparam.num = alloc->num_unit;
-+	ioparam.cached =
-+	    alloc->type == VC_SM_ALLOC_CACHED ? VMCS_SM_CACHE_VC : 0;
-+
-+	ret = vc_sm_ioctl_alloc(sm_state->data_knl, &ioparam);
-+
-+	if (ret == 0) {
-+		resource =
-+		    vmcs_sm_acquire_resource(sm_state->data_knl,
-+					     ioparam.handle);
-+		if (resource) {
-+			resource->pid = 0;
-+			vmcs_sm_release_resource(resource, 0);
-+
-+			/* Assign valid handle at this time. */
-+			*handle = ioparam.handle;
-+		} else {
-+			ret = -ENOMEM;
-+		}
-+	}
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_alloc);
-+
-+/* Get an internal resource handle mapped from the external one. */
-+int vc_sm_int_handle(int handle)
-+{
-+	struct sm_resource_t *resource;
-+	int ret = 0;
-+
-+	/* Validate we can work with this device. */
-+	if (sm_state == NULL || handle == 0) {
-+		pr_err("[%s]: invalid input\n", __func__);
-+		return 0;
-+	}
-+
-+	/* Locate resource from GUID. */
-+	resource = vmcs_sm_acquire_resource(sm_state->data_knl, handle);
-+	if (resource) {
-+		ret = resource->res_handle;
-+		vmcs_sm_release_resource(resource, 0);
-+	}
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_int_handle);
-+
-+/* Free a previously allocated shared memory handle and block. */
-+int vc_sm_free(int handle)
-+{
-+	struct vmcs_sm_ioctl_free ioparam = { handle };
-+
-+	/* Validate we can work with this device. */
-+	if (sm_state == NULL || handle == 0) {
-+		pr_err("[%s]: invalid input\n", __func__);
-+		return -EPERM;
-+	}
-+
-+	return vc_sm_ioctl_free(sm_state->data_knl, &ioparam);
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_free);
-+
-+/* Lock a memory handle for use by kernel. */
-+int vc_sm_lock(int handle, enum vc_sm_lock_cache_mode mode,
-+	       unsigned long *data)
-+{
-+	struct vmcs_sm_ioctl_lock_unlock ioparam;
-+	int ret;
-+
-+	/* Validate we can work with this device. */
-+	if (sm_state == NULL || handle == 0 || data == NULL) {
-+		pr_err("[%s]: invalid input\n", __func__);
-+		return -EPERM;
-+	}
-+
-+	*data = 0;
-+
-+	ioparam.handle = handle;
-+	ret = vc_sm_ioctl_lock(sm_state->data_knl,
-+			       &ioparam,
-+			       1,
-+			       ((mode ==
-+				 VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST :
-+				VMCS_SM_CACHE_NONE), 0);
-+
-+	*data = ioparam.addr;
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_lock);
-+
-+/* Unlock a memory handle in use by kernel. */
-+int vc_sm_unlock(int handle, int flush, int no_vc_unlock)
-+{
-+	struct vmcs_sm_ioctl_lock_unlock ioparam;
-+
-+	/* Validate we can work with this device. */
-+	if (sm_state == NULL || handle == 0) {
-+		pr_err("[%s]: invalid input\n", __func__);
-+		return -EPERM;
-+	}
-+
-+	ioparam.handle = handle;
-+	return vc_sm_ioctl_unlock(sm_state->data_knl,
-+				  &ioparam, flush, 0, no_vc_unlock);
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_unlock);
-+
-+/* Map a shared memory region for use by kernel. */
-+int vc_sm_map(int handle, unsigned int sm_addr,
-+	      enum vc_sm_lock_cache_mode mode, unsigned long *data)
-+{
-+	struct vmcs_sm_ioctl_lock_unlock ioparam;
-+	int ret;
-+
-+	/* Validate we can work with this device. */
-+	if (sm_state == NULL || handle == 0 || data == NULL || sm_addr == 0) {
-+		pr_err("[%s]: invalid input\n", __func__);
-+		return -EPERM;
-+	}
-+
-+	*data = 0;
-+
-+	ioparam.handle = handle;
-+	ret = vc_sm_ioctl_lock(sm_state->data_knl,
-+			       &ioparam,
-+			       1,
-+			       ((mode ==
-+				 VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST :
-+				VMCS_SM_CACHE_NONE), sm_addr);
-+
-+	*data = ioparam.addr;
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_map);
-+
-+/* Import a dmabuf to be shared with VC. */
-+int vc_sm_import_dmabuf(struct dma_buf *dmabuf, int *handle)
-+{
-+	struct vmcs_sm_ioctl_import_dmabuf ioparam = { 0 };
-+	int ret;
-+	struct sm_resource_t *resource;
-+
-+	/* Validate we can work with this device. */
-+	if (!sm_state || !dmabuf || !handle) {
-+		pr_err("[%s]: invalid input\n", __func__);
-+		return -EPERM;
-+	}
-+
-+	ioparam.cached = 0;
-+	strcpy(ioparam.name, "KRNL DMABUF");
-+
-+	ret = vc_sm_ioctl_import_dmabuf(sm_state->data_knl, &ioparam, dmabuf);
-+
-+	if (!ret) {
-+		resource = vmcs_sm_acquire_resource(sm_state->data_knl,
-+						    ioparam.handle);
-+		if (resource) {
-+			resource->pid = 0;
-+			vmcs_sm_release_resource(resource, 0);
-+
-+			/* Assign valid handle at this time.*/
-+			*handle = ioparam.handle;
-+		} else {
-+			ret = -ENOMEM;
-+		}
-+	}
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(vc_sm_import_dmabuf);
-+#endif
-+
-+/*
-+ *   Register the driver with device tree
-+ */
-+
-+static const struct of_device_id bcm2835_vcsm_of_match[] = {
-+	{.compatible = "raspberrypi,bcm2835-vcsm",},
-+	{ /* sentinel */ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, bcm2835_vcsm_of_match);
-+
-+static struct platform_driver bcm2835_vcsm_driver = {
-+	.probe = bcm2835_vcsm_probe,
-+	.remove = bcm2835_vcsm_remove,
-+	.driver = {
-+		   .name = DRIVER_NAME,
-+		   .owner = THIS_MODULE,
-+		   .of_match_table = bcm2835_vcsm_of_match,
-+		   },
-+};
-+
-+module_platform_driver(bcm2835_vcsm_driver);
-+
-+MODULE_AUTHOR("Broadcom");
-+MODULE_DESCRIPTION("VideoCore SharedMemory Driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/linux/broadcom/vmcs_sm_ioctl.h
-@@ -0,0 +1,280 @@
-+/*****************************************************************************
-+*  Copyright 2011 Broadcom Corporation.  All rights reserved.
-+*
-+*  Unless you and Broadcom execute a separate written software license
-+*  agreement governing use of this software, this software is licensed to you
-+*  under the terms of the GNU General Public License version 2, available at
-+*  http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-+*
-+*  Notwithstanding the above, under no circumstances may you combine this
-+*  software in any way with any other Broadcom software provided under a
-+*  license other than the GPL, without Broadcom's express prior written
-+*  consent.
-+*
-+*****************************************************************************/
-+
-+#if !defined(__VMCS_SM_IOCTL_H__INCLUDED__)
-+#define __VMCS_SM_IOCTL_H__INCLUDED__
-+
-+/* ---- Include Files ---------------------------------------------------- */
-+
-+#if defined(__KERNEL__)
-+#include <linux/types.h>	/* Needed for standard types */
-+#else
-+#include <stdint.h>
-+#endif
-+
-+#include <linux/ioctl.h>
-+
-+/* ---- Constants and Types ---------------------------------------------- */
-+
-+#define VMCS_SM_RESOURCE_NAME               32
-+#define VMCS_SM_RESOURCE_NAME_DEFAULT       "sm-host-resource"
-+
-+/* Type define used to create unique IOCTL number */
-+#define VMCS_SM_MAGIC_TYPE                  'I'
-+
-+/* IOCTL commands */
-+enum vmcs_sm_cmd_e {
-+	VMCS_SM_CMD_ALLOC = 0x5A,	/* Start at 0x5A arbitrarily */
-+	VMCS_SM_CMD_ALLOC_SHARE,
-+	VMCS_SM_CMD_LOCK,
-+	VMCS_SM_CMD_LOCK_CACHE,
-+	VMCS_SM_CMD_UNLOCK,
-+	VMCS_SM_CMD_RESIZE,
-+	VMCS_SM_CMD_UNMAP,
-+	VMCS_SM_CMD_FREE,
-+	VMCS_SM_CMD_FLUSH,
-+	VMCS_SM_CMD_INVALID,
-+
-+	VMCS_SM_CMD_SIZE_USR_HANDLE,
-+	VMCS_SM_CMD_CHK_USR_HANDLE,
-+
-+	VMCS_SM_CMD_MAPPED_USR_HANDLE,
-+	VMCS_SM_CMD_MAPPED_USR_ADDRESS,
-+	VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,
-+	VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,
-+	VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,
-+
-+	VMCS_SM_CMD_VC_WALK_ALLOC,
-+	VMCS_SM_CMD_HOST_WALK_MAP,
-+	VMCS_SM_CMD_HOST_WALK_PID_ALLOC,
-+	VMCS_SM_CMD_HOST_WALK_PID_MAP,
-+
-+	VMCS_SM_CMD_CLEAN_INVALID,
-+	VMCS_SM_CMD_CLEAN_INVALID2,
-+
-+	VMCS_SM_CMD_IMPORT_DMABUF,
-+
-+	VMCS_SM_CMD_LAST	/* Do not delete */
-+};
-+
-+/* Cache type supported, conveniently matches the user space definition in
-+** user-vcsm.h.
-+*/
-+enum vmcs_sm_cache_e {
-+	VMCS_SM_CACHE_NONE,
-+	VMCS_SM_CACHE_HOST,
-+	VMCS_SM_CACHE_VC,
-+	VMCS_SM_CACHE_BOTH,
-+};
-+
-+/* IOCTL Data structures */
-+struct vmcs_sm_ioctl_alloc {
-+	/* user -> kernel */
-+	unsigned int size;
-+	unsigned int num;
-+	enum vmcs_sm_cache_e cached;
-+	char name[VMCS_SM_RESOURCE_NAME];
-+
-+	/* kernel -> user */
-+	unsigned int handle;
-+	/* unsigned int base_addr; */
-+};
-+
-+struct vmcs_sm_ioctl_alloc_share {
-+	/* user -> kernel */
-+	unsigned int handle;
-+	unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_free {
-+	/* user -> kernel */
-+	unsigned int handle;
-+	/* unsigned int base_addr; */
-+};
-+
-+struct vmcs_sm_ioctl_lock_unlock {
-+	/* user -> kernel */
-+	unsigned int handle;
-+
-+	/* kernel -> user */
-+	unsigned int addr;
-+};
-+
-+struct vmcs_sm_ioctl_lock_cache {
-+	/* user -> kernel */
-+	unsigned int handle;
-+	enum vmcs_sm_cache_e cached;
-+};
-+
-+struct vmcs_sm_ioctl_resize {
-+	/* user -> kernel */
-+	unsigned int handle;
-+	unsigned int new_size;
-+
-+	/* kernel -> user */
-+	unsigned int old_size;
-+};
-+
-+struct vmcs_sm_ioctl_map {
-+	/* user -> kernel */
-+	/* and kernel -> user */
-+	unsigned int pid;
-+	unsigned int handle;
-+	unsigned int addr;
-+
-+	/* kernel -> user */
-+	unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_walk {
-+	/* user -> kernel */
-+	unsigned int pid;
-+};
-+
-+struct vmcs_sm_ioctl_chk {
-+	/* user -> kernel */
-+	unsigned int handle;
-+
-+	/* kernel -> user */
-+	unsigned int addr;
-+	unsigned int size;
-+	enum vmcs_sm_cache_e cache;
-+};
-+
-+struct vmcs_sm_ioctl_size {
-+	/* user -> kernel */
-+	unsigned int handle;
-+
-+	/* kernel -> user */
-+	unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_cache {
-+	/* user -> kernel */
-+	unsigned int handle;
-+	unsigned int addr;
-+	unsigned int size;
-+};
-+
-+struct vmcs_sm_ioctl_clean_invalid {
-+	/* user -> kernel */
-+	struct {
-+		unsigned int cmd;
-+		unsigned int handle;
-+		unsigned int addr;
-+		unsigned int size;
-+	} s[8];
-+};
-+
-+struct vmcs_sm_ioctl_clean_invalid2 {
-+	uint8_t op_count;
-+	uint8_t zero[3];
-+	struct vmcs_sm_ioctl_clean_invalid_block {
-+		uint16_t invalidate_mode;
-+		uint16_t block_count;
-+		void *   start_address;
-+		uint32_t block_size;
-+		uint32_t inter_block_stride;
-+	} s[0];
-+};
-+
-+struct vmcs_sm_ioctl_import_dmabuf {
-+	/* user -> kernel */
-+	int dmabuf_fd;
-+	enum vmcs_sm_cache_e cached;
-+	char name[VMCS_SM_RESOURCE_NAME];
-+
-+	/* kernel -> user */
-+	unsigned int handle;
-+};
-+
-+/* IOCTL numbers */
-+#define VMCS_SM_IOCTL_MEM_ALLOC\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC,\
-+	 struct vmcs_sm_ioctl_alloc)
-+#define VMCS_SM_IOCTL_MEM_ALLOC_SHARE\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC_SHARE,\
-+	 struct vmcs_sm_ioctl_alloc_share)
-+#define VMCS_SM_IOCTL_MEM_LOCK\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK,\
-+	 struct vmcs_sm_ioctl_lock_unlock)
-+#define VMCS_SM_IOCTL_MEM_LOCK_CACHE\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK_CACHE,\
-+	 struct vmcs_sm_ioctl_lock_cache)
-+#define VMCS_SM_IOCTL_MEM_UNLOCK\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_UNLOCK,\
-+	 struct vmcs_sm_ioctl_lock_unlock)
-+#define VMCS_SM_IOCTL_MEM_RESIZE\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_RESIZE,\
-+	 struct vmcs_sm_ioctl_resize)
-+#define VMCS_SM_IOCTL_MEM_FREE\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FREE,\
-+	 struct vmcs_sm_ioctl_free)
-+#define VMCS_SM_IOCTL_MEM_FLUSH\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FLUSH,\
-+	 struct vmcs_sm_ioctl_cache)
-+#define VMCS_SM_IOCTL_MEM_INVALID\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_INVALID,\
-+	 struct vmcs_sm_ioctl_cache)
-+#define VMCS_SM_IOCTL_MEM_CLEAN_INVALID\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CLEAN_INVALID,\
-+	 struct vmcs_sm_ioctl_clean_invalid)
-+#define VMCS_SM_IOCTL_MEM_CLEAN_INVALID2\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CLEAN_INVALID2,\
-+	 struct vmcs_sm_ioctl_clean_invalid2)
-+
-+#define VMCS_SM_IOCTL_SIZE_USR_HDL\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_SIZE_USR_HANDLE,\
-+	 struct vmcs_sm_ioctl_size)
-+#define VMCS_SM_IOCTL_CHK_USR_HDL\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CHK_USR_HANDLE,\
-+	 struct vmcs_sm_ioctl_chk)
-+
-+#define VMCS_SM_IOCTL_MAP_USR_HDL\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_HANDLE,\
-+	 struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_USR_ADDRESS\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_ADDRESS,\
-+	 struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_ADDR\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,\
-+	 struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_HDL\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,\
-+	 struct vmcs_sm_ioctl_map)
-+#define VMCS_SM_IOCTL_MAP_VC_ADDR_FR_HDL\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,\
-+	 struct vmcs_sm_ioctl_map)
-+
-+#define VMCS_SM_IOCTL_VC_WALK_ALLOC\
-+	_IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_VC_WALK_ALLOC)
-+#define VMCS_SM_IOCTL_HOST_WALK_MAP\
-+	_IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_MAP)
-+#define VMCS_SM_IOCTL_HOST_WALK_PID_ALLOC\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_ALLOC,\
-+	 struct vmcs_sm_ioctl_walk)
-+#define VMCS_SM_IOCTL_HOST_WALK_PID_MAP\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_MAP,\
-+	 struct vmcs_sm_ioctl_walk)
-+
-+#define VMCS_SM_IOCTL_MEM_IMPORT_DMABUF\
-+	_IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_IMPORT_DMABUF,\
-+	 struct vmcs_sm_ioctl_import_dmabuf)
-+
-+/* ---- Variable Externs ------------------------------------------------- */
-+
-+/* ---- Function Prototypes ---------------------------------------------- */
-+
-+#endif /* __VMCS_SM_IOCTL_H__INCLUDED__ */
diff --git a/target/linux/brcm2708/patches-4.14/950-0044-Add-dev-gpiomem-device-for-rootless-user-GPIO-access.patch b/target/linux/brcm2708/patches-4.14/950-0044-Add-dev-gpiomem-device-for-rootless-user-GPIO-access.patch
deleted file mode 100644
index e7bd8d9e7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0044-Add-dev-gpiomem-device-for-rootless-user-GPIO-access.patch
+++ /dev/null
@@ -1,303 +0,0 @@
-From 818357c73f5869dfc9e98224f91e116fd23d5246 Mon Sep 17 00:00:00 2001
-From: Luke Wren <luke@raspberrypi.org>
-Date: Fri, 21 Aug 2015 23:14:48 +0100
-Subject: [PATCH 044/454] Add /dev/gpiomem device for rootless user GPIO access
-
-Signed-off-by: Luke Wren <luke@raspberrypi.org>
-
-bcm2835-gpiomem: Fix for ARCH_BCM2835 builds
-
-Build on ARCH_BCM2835, and fail to probe if no IO resource.
-
-See: https://github.com/raspberrypi/linux/issues/1154
----
- drivers/char/broadcom/Kconfig           |   9 +
- drivers/char/broadcom/Makefile          |   3 +
- drivers/char/broadcom/bcm2835-gpiomem.c | 258 ++++++++++++++++++++++++
- 3 files changed, 270 insertions(+)
- create mode 100644 drivers/char/broadcom/bcm2835-gpiomem.c
-
---- a/drivers/char/broadcom/Kconfig
-+++ b/drivers/char/broadcom/Kconfig
-@@ -26,3 +26,12 @@ config BCM_VC_SM
- 	help
- 	Support for the VC shared memory on the Broadcom reference
- 	design. Uses the VCHIQ stack.
-+
-+config BCM2835_DEVGPIOMEM
-+	tristate "/dev/gpiomem rootless GPIO access via mmap() on the BCM2835"
-+	default m
-+	help
-+		Provides users with root-free access to the GPIO registers
-+		on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO
-+		register page to the user's pointer.
-+
---- a/drivers/char/broadcom/Makefile
-+++ b/drivers/char/broadcom/Makefile
-@@ -1,2 +1,5 @@
- obj-$(CONFIG_BCM2708_VCMEM)	+= vc_mem.o
- obj-$(CONFIG_BCM_VC_SM)         += vc_sm/
-+
-+obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o
-+
---- /dev/null
-+++ b/drivers/char/broadcom/bcm2835-gpiomem.c
-@@ -0,0 +1,258 @@
-+/**
-+ * GPIO memory device driver
-+ *
-+ * Creates a chardev /dev/gpiomem which will provide user access to
-+ * the BCM2835's GPIO registers when it is mmap()'d.
-+ * No longer need root for user GPIO access, but without relaxing permissions
-+ * on /dev/mem.
-+ *
-+ * Written by Luke Wren <luke@raspberrypi.org>
-+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/cdev.h>
-+#include <linux/pagemap.h>
-+#include <linux/io.h>
-+
-+#define DEVICE_NAME "bcm2835-gpiomem"
-+#define DRIVER_NAME "gpiomem-bcm2835"
-+#define DEVICE_MINOR 0
-+
-+struct bcm2835_gpiomem_instance {
-+	unsigned long gpio_regs_phys;
-+	struct device *dev;
-+};
-+
-+static struct cdev bcm2835_gpiomem_cdev;
-+static dev_t bcm2835_gpiomem_devid;
-+static struct class *bcm2835_gpiomem_class;
-+static struct device *bcm2835_gpiomem_dev;
-+static struct bcm2835_gpiomem_instance *inst;
-+
-+
-+/****************************************************************************
-+*
-+*   GPIO mem chardev file ops
-+*
-+***************************************************************************/
-+
-+static int bcm2835_gpiomem_open(struct inode *inode, struct file *file)
-+{
-+	int dev = iminor(inode);
-+	int ret = 0;
-+
-+	if (dev != DEVICE_MINOR) {
-+		dev_err(inst->dev, "Unknown minor device: %d", dev);
-+		ret = -ENXIO;
-+	}
-+	return ret;
-+}
-+
-+static int bcm2835_gpiomem_release(struct inode *inode, struct file *file)
-+{
-+	int dev = iminor(inode);
-+	int ret = 0;
-+
-+	if (dev != DEVICE_MINOR) {
-+		dev_err(inst->dev, "Unknown minor device %d", dev);
-+		ret = -ENXIO;
-+	}
-+	return ret;
-+}
-+
-+static const struct vm_operations_struct bcm2835_gpiomem_vm_ops = {
-+#ifdef CONFIG_HAVE_IOREMAP_PROT
-+	.access = generic_access_phys
-+#endif
-+};
-+
-+static int bcm2835_gpiomem_mmap(struct file *file, struct vm_area_struct *vma)
-+{
-+	/* Ignore what the user says - they're getting the GPIO regs
-+	   whether they like it or not! */
-+	unsigned long gpio_page = inst->gpio_regs_phys >> PAGE_SHIFT;
-+
-+	vma->vm_page_prot = phys_mem_access_prot(file, gpio_page,
-+						 PAGE_SIZE,
-+						 vma->vm_page_prot);
-+	vma->vm_ops = &bcm2835_gpiomem_vm_ops;
-+	if (remap_pfn_range(vma, vma->vm_start,
-+			gpio_page,
-+			PAGE_SIZE,
-+			vma->vm_page_prot)) {
-+		return -EAGAIN;
-+	}
-+	return 0;
-+}
-+
-+static const struct file_operations
-+bcm2835_gpiomem_fops = {
-+	.owner = THIS_MODULE,
-+	.open = bcm2835_gpiomem_open,
-+	.release = bcm2835_gpiomem_release,
-+	.mmap = bcm2835_gpiomem_mmap,
-+};
-+
-+
-+ /****************************************************************************
-+*
-+*   Probe and remove functions
-+*
-+***************************************************************************/
-+
-+
-+static int bcm2835_gpiomem_probe(struct platform_device *pdev)
-+{
-+	int err;
-+	void *ptr_err;
-+	struct device *dev = &pdev->dev;
-+	struct resource *ioresource;
-+
-+	/* Allocate buffers and instance data */
-+
-+	inst = kzalloc(sizeof(struct bcm2835_gpiomem_instance), GFP_KERNEL);
-+
-+	if (!inst) {
-+		err = -ENOMEM;
-+		goto failed_inst_alloc;
-+	}
-+
-+	inst->dev = dev;
-+
-+	ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (ioresource) {
-+		inst->gpio_regs_phys = ioresource->start;
-+	} else {
-+		dev_err(inst->dev, "failed to get IO resource");
-+		err = -ENOENT;
-+		goto failed_get_resource;
-+	}
-+
-+	/* Create character device entries */
-+
-+	err = alloc_chrdev_region(&bcm2835_gpiomem_devid,
-+				  DEVICE_MINOR, 1, DEVICE_NAME);
-+	if (err != 0) {
-+		dev_err(inst->dev, "unable to allocate device number");
-+		goto failed_alloc_chrdev;
-+	}
-+	cdev_init(&bcm2835_gpiomem_cdev, &bcm2835_gpiomem_fops);
-+	bcm2835_gpiomem_cdev.owner = THIS_MODULE;
-+	err = cdev_add(&bcm2835_gpiomem_cdev, bcm2835_gpiomem_devid, 1);
-+	if (err != 0) {
-+		dev_err(inst->dev, "unable to register device");
-+		goto failed_cdev_add;
-+	}
-+
-+	/* Create sysfs entries */
-+
-+	bcm2835_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME);
-+	ptr_err = bcm2835_gpiomem_class;
-+	if (IS_ERR(ptr_err))
-+		goto failed_class_create;
-+
-+	bcm2835_gpiomem_dev = device_create(bcm2835_gpiomem_class, NULL,
-+					bcm2835_gpiomem_devid, NULL,
-+					"gpiomem");
-+	ptr_err = bcm2835_gpiomem_dev;
-+	if (IS_ERR(ptr_err))
-+		goto failed_device_create;
-+
-+	dev_info(inst->dev, "Initialised: Registers at 0x%08lx",
-+		inst->gpio_regs_phys);
-+
-+	return 0;
-+
-+failed_device_create:
-+	class_destroy(bcm2835_gpiomem_class);
-+failed_class_create:
-+	cdev_del(&bcm2835_gpiomem_cdev);
-+	err = PTR_ERR(ptr_err);
-+failed_cdev_add:
-+	unregister_chrdev_region(bcm2835_gpiomem_devid, 1);
-+failed_alloc_chrdev:
-+failed_get_resource:
-+	kfree(inst);
-+failed_inst_alloc:
-+	dev_err(inst->dev, "could not load bcm2835_gpiomem");
-+	return err;
-+}
-+
-+static int bcm2835_gpiomem_remove(struct platform_device *pdev)
-+{
-+	struct device *dev = inst->dev;
-+
-+	kfree(inst);
-+	device_destroy(bcm2835_gpiomem_class, bcm2835_gpiomem_devid);
-+	class_destroy(bcm2835_gpiomem_class);
-+	cdev_del(&bcm2835_gpiomem_cdev);
-+	unregister_chrdev_region(bcm2835_gpiomem_devid, 1);
-+
-+	dev_info(dev, "GPIO mem driver removed - OK");
-+	return 0;
-+}
-+
-+ /****************************************************************************
-+*
-+*   Register the driver with device tree
-+*
-+***************************************************************************/
-+
-+static const struct of_device_id bcm2835_gpiomem_of_match[] = {
-+	{.compatible = "brcm,bcm2835-gpiomem",},
-+	{ /* sentinel */ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, bcm2835_gpiomem_of_match);
-+
-+static struct platform_driver bcm2835_gpiomem_driver = {
-+	.probe = bcm2835_gpiomem_probe,
-+	.remove = bcm2835_gpiomem_remove,
-+	.driver = {
-+		   .name = DRIVER_NAME,
-+		   .owner = THIS_MODULE,
-+		   .of_match_table = bcm2835_gpiomem_of_match,
-+		   },
-+};
-+
-+module_platform_driver(bcm2835_gpiomem_driver);
-+
-+MODULE_ALIAS("platform:gpiomem-bcm2835");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("gpiomem driver for accessing GPIO from userspace");
-+MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
diff --git a/target/linux/brcm2708/patches-4.14/950-0045-Add-SMI-driver.patch b/target/linux/brcm2708/patches-4.14/950-0045-Add-SMI-driver.patch
deleted file mode 100644
index a871f1f7d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0045-Add-SMI-driver.patch
+++ /dev/null
@@ -1,1930 +0,0 @@
-From 2be5cef158a838f98f42e9d9e4d5f6caf57ec2e2 Mon Sep 17 00:00:00 2001
-From: Luke Wren <wren6991@gmail.com>
-Date: Sat, 5 Sep 2015 01:14:45 +0100
-Subject: [PATCH 045/454] Add SMI driver
-
-Signed-off-by: Luke Wren <wren6991@gmail.com>
----
- .../bindings/misc/brcm,bcm2835-smi-dev.txt    |  17 +
- .../bindings/misc/brcm,bcm2835-smi.txt        |  48 +
- drivers/char/broadcom/Kconfig                 |   8 +
- drivers/char/broadcom/Makefile                |   2 +-
- drivers/char/broadcom/bcm2835_smi_dev.c       | 402 +++++++
- drivers/misc/Kconfig                          |   8 +
- drivers/misc/Makefile                         |   1 +
- drivers/misc/bcm2835_smi.c                    | 985 ++++++++++++++++++
- include/linux/broadcom/bcm2835_smi.h          | 391 +++++++
- 9 files changed, 1861 insertions(+), 1 deletion(-)
- create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
- create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
- create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c
- create mode 100644 drivers/misc/bcm2835_smi.c
- create mode 100644 include/linux/broadcom/bcm2835_smi.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
-@@ -0,0 +1,17 @@
-+* Broadcom BCM2835 SMI character device driver.
-+
-+SMI or secondary memory interface is a peripheral specific to certain Broadcom
-+SOCs, and is helpful for talking to things like parallel-interface displays
-+and NAND flashes (in fact, most things with a parallel register interface).
-+
-+This driver adds a character device which provides a user-space interface to
-+an instance of the SMI driver.
-+
-+Required properties:
-+- compatible: "brcm,bcm2835-smi-dev"
-+- smi_handle: a phandle to the smi node.
-+
-+Optional properties:
-+- None.
-+
-+
---- /dev/null
-+++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
-@@ -0,0 +1,48 @@
-+* Broadcom BCM2835 SMI driver.
-+
-+SMI or secondary memory interface is a peripheral specific to certain Broadcom
-+SOCs, and is helpful for talking to things like parallel-interface displays
-+and NAND flashes (in fact, most things with a parallel register interface).
-+
-+Required properties:
-+- compatible: "brcm,bcm2835-smi"
-+- reg: Should contain location and length of SMI registers and SMI clkman regs
-+- interrupts: *the* SMI interrupt.
-+- pinctrl-names: should be "default".
-+- pinctrl-0: the phandle of the gpio pin node.
-+- brcm,smi-clock-source: the clock source for clkman
-+- brcm,smi-clock-divisor: the integer clock divisor for clkman
-+- dmas: the dma controller phandle and the DREQ number (4 on a 2835)
-+- dma-names: the name used by the driver to request its channel.
-+  Should be "rx-tx".
-+
-+Optional properties:
-+- None.
-+
-+Examples:
-+
-+8 data pin configuration:
-+
-+smi: smi@7e600000 {
-+	compatible = "brcm,bcm2835-smi";
-+	reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>;
-+	interrupts = <2 16>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&smi_pins>;
-+	brcm,smi-clock-source = <6>;
-+	brcm,smi-clock-divisor = <4>;
-+	dmas = <&dma 4>;
-+	dma-names = "rx-tx";
-+
-+	status = "okay";
-+};
-+
-+smi_pins: smi_pins {
-+	brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
-+	/* Alt 1: SMI */
-+	brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>;
-+	/* /CS, /WE and /OE are pulled high, as they are
-+	   generally active low signals */
-+	brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>;
-+};
-+
---- a/drivers/char/broadcom/Kconfig
-+++ b/drivers/char/broadcom/Kconfig
-@@ -35,3 +35,11 @@ config BCM2835_DEVGPIOMEM
- 		on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO
- 		register page to the user's pointer.
- 
-+config BCM2835_SMI_DEV
-+	tristate "Character device driver for BCM2835 Secondary Memory Interface"
-+	depends on BCM2835_SMI
-+	default m
-+	help
-+		This driver provides a character device interface (ioctl + read/write) to
-+		Broadcom's Secondary Memory interface. The low-level functionality is provided
-+		by the SMI driver itself.
---- a/drivers/char/broadcom/Makefile
-+++ b/drivers/char/broadcom/Makefile
-@@ -2,4 +2,4 @@ obj-$(CONFIG_BCM2708_VCMEM)	+= vc_mem.o
- obj-$(CONFIG_BCM_VC_SM)         += vc_sm/
- 
- obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o
--
-+obj-$(CONFIG_BCM2835_SMI_DEV)	+= bcm2835_smi_dev.o
---- /dev/null
-+++ b/drivers/char/broadcom/bcm2835_smi_dev.c
-@@ -0,0 +1,402 @@
-+/**
-+ * Character device driver for Broadcom Secondary Memory Interface
-+ *
-+ * Written by Luke Wren <luke@raspberrypi.org>
-+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/mm.h>
-+#include <linux/pagemap.h>
-+#include <linux/fs.h>
-+#include <linux/cdev.h>
-+#include <linux/fs.h>
-+
-+#include <linux/broadcom/bcm2835_smi.h>
-+
-+#define DEVICE_NAME "bcm2835-smi-dev"
-+#define DRIVER_NAME "smi-dev-bcm2835"
-+#define DEVICE_MINOR 0
-+
-+static struct cdev bcm2835_smi_cdev;
-+static dev_t bcm2835_smi_devid;
-+static struct class *bcm2835_smi_class;
-+static struct device *bcm2835_smi_dev;
-+
-+struct bcm2835_smi_dev_instance {
-+	struct device *dev;
-+};
-+
-+static struct bcm2835_smi_instance *smi_inst;
-+static struct bcm2835_smi_dev_instance *inst;
-+
-+static const char *const ioctl_names[] = {
-+	"READ_SETTINGS",
-+	"WRITE_SETTINGS",
-+	"ADDRESS"
-+};
-+
-+/****************************************************************************
-+*
-+*   SMI chardev file ops
-+*
-+***************************************************************************/
-+static long
-+bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-+{
-+	long ret = 0;
-+
-+	dev_info(inst->dev, "serving ioctl...");
-+
-+	switch (cmd) {
-+	case BCM2835_SMI_IOC_GET_SETTINGS:{
-+		struct smi_settings *settings;
-+
-+		dev_info(inst->dev, "Reading SMI settings to user.");
-+		settings = bcm2835_smi_get_settings_from_regs(smi_inst);
-+		if (copy_to_user((void *)arg, settings,
-+				 sizeof(struct smi_settings)))
-+			dev_err(inst->dev, "settings copy failed.");
-+		break;
-+	}
-+	case BCM2835_SMI_IOC_WRITE_SETTINGS:{
-+		struct smi_settings *settings;
-+
-+		dev_info(inst->dev, "Setting user's SMI settings.");
-+		settings = bcm2835_smi_get_settings_from_regs(smi_inst);
-+		if (copy_from_user(settings, (void *)arg,
-+				   sizeof(struct smi_settings)))
-+			dev_err(inst->dev, "settings copy failed.");
-+		else
-+			bcm2835_smi_set_regs_from_settings(smi_inst);
-+		break;
-+	}
-+	case BCM2835_SMI_IOC_ADDRESS:
-+		dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg);
-+		bcm2835_smi_set_address(smi_inst, arg);
-+		break;
-+	default:
-+		dev_err(inst->dev, "invalid ioctl cmd: %d", cmd);
-+		ret = -ENOTTY;
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static int bcm2835_smi_open(struct inode *inode, struct file *file)
-+{
-+	int dev = iminor(inode);
-+
-+	dev_dbg(inst->dev, "SMI device opened.");
-+
-+	if (dev != DEVICE_MINOR) {
-+		dev_err(inst->dev,
-+			"bcm2835_smi_release: Unknown minor device: %d",
-+			dev);
-+		return -ENXIO;
-+	}
-+
-+	return 0;
-+}
-+
-+static int bcm2835_smi_release(struct inode *inode, struct file *file)
-+{
-+	int dev = iminor(inode);
-+
-+	if (dev != DEVICE_MINOR) {
-+		dev_err(inst->dev,
-+			"bcm2835_smi_release: Unknown minor device %d", dev);
-+		return -ENXIO;
-+	}
-+
-+	return 0;
-+}
-+
-+static ssize_t dma_bounce_user(
-+	enum dma_transfer_direction dma_dir,
-+	char __user *user_ptr,
-+	size_t count,
-+	struct bcm2835_smi_bounce_info *bounce)
-+{
-+	int chunk_size;
-+	int chunk_no = 0;
-+	int count_left = count;
-+
-+	while (count_left) {
-+		int rv;
-+		void *buf;
-+
-+		/* Wait for current chunk to complete: */
-+		if (down_timeout(&bounce->callback_sem,
-+			msecs_to_jiffies(1000))) {
-+			dev_err(inst->dev, "DMA bounce timed out");
-+			count -= (count_left);
-+			break;
-+		}
-+
-+		if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1)
-+			dev_err(inst->dev, "WARNING: Ring buffer overflow");
-+		chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
-+			DMA_BOUNCE_BUFFER_SIZE : count_left;
-+		buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
-+		if (dma_dir == DMA_DEV_TO_MEM)
-+			rv = copy_to_user(user_ptr, buf, chunk_size);
-+		else
-+			rv = copy_from_user(buf, user_ptr, chunk_size);
-+		if (rv)
-+			dev_err(inst->dev, "copy_*_user() failed!: %d", rv);
-+		user_ptr += chunk_size;
-+		count_left -= chunk_size;
-+		chunk_no++;
-+	}
-+	return count;
-+}
-+
-+static ssize_t
-+bcm2835_read_file(struct file *f, char __user *user_ptr,
-+		  size_t count, loff_t *offs)
-+{
-+	int odd_bytes;
-+
-+	dev_dbg(inst->dev, "User reading %d bytes from SMI.", count);
-+	/* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */
-+	if (count > DMA_THRESHOLD_BYTES)
-+		odd_bytes = count & 0x3;
-+	else
-+		odd_bytes = count;
-+	count -= odd_bytes;
-+	if (count) {
-+		struct bcm2835_smi_bounce_info *bounce;
-+
-+		count = bcm2835_smi_user_dma(smi_inst,
-+			DMA_DEV_TO_MEM, user_ptr, count,
-+			&bounce);
-+		if (count)
-+			count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr,
-+				count, bounce);
-+	}
-+	if (odd_bytes) {
-+		/* Read from FIFO directly if not using DMA */
-+		uint8_t buf[DMA_THRESHOLD_BYTES];
-+
-+		bcm2835_smi_read_buf(smi_inst, buf, odd_bytes);
-+		if (copy_to_user(user_ptr, buf, odd_bytes))
-+			dev_err(inst->dev, "copy_to_user() failed.");
-+		count += odd_bytes;
-+
-+	}
-+	return count;
-+}
-+
-+static ssize_t
-+bcm2835_write_file(struct file *f, const char __user *user_ptr,
-+		   size_t count, loff_t *offs)
-+{
-+	int odd_bytes;
-+
-+	dev_dbg(inst->dev, "User writing %d bytes to SMI.", count);
-+	if (count > DMA_THRESHOLD_BYTES)
-+		odd_bytes = count & 0x3;
-+	else
-+		odd_bytes = count;
-+	count -= odd_bytes;
-+	if (count) {
-+		struct bcm2835_smi_bounce_info *bounce;
-+
-+		count = bcm2835_smi_user_dma(smi_inst,
-+			DMA_MEM_TO_DEV, (char __user *)user_ptr, count,
-+			&bounce);
-+		if (count)
-+			count = dma_bounce_user(DMA_MEM_TO_DEV,
-+				(char __user *)user_ptr,
-+				count, bounce);
-+	}
-+	if (odd_bytes) {
-+		uint8_t buf[DMA_THRESHOLD_BYTES];
-+
-+		if (copy_from_user(buf, user_ptr, odd_bytes))
-+			dev_err(inst->dev, "copy_from_user() failed.");
-+		else
-+			bcm2835_smi_write_buf(smi_inst, buf, odd_bytes);
-+		count += odd_bytes;
-+	}
-+	return count;
-+}
-+
-+static const struct file_operations
-+bcm2835_smi_fops = {
-+	.owner = THIS_MODULE,
-+	.unlocked_ioctl = bcm2835_smi_ioctl,
-+	.open = bcm2835_smi_open,
-+	.release = bcm2835_smi_release,
-+	.read = bcm2835_read_file,
-+	.write = bcm2835_write_file,
-+};
-+
-+
-+/****************************************************************************
-+*
-+*   bcm2835_smi_probe - called when the driver is loaded.
-+*
-+***************************************************************************/
-+
-+static int bcm2835_smi_dev_probe(struct platform_device *pdev)
-+{
-+	int err;
-+	void *ptr_err;
-+	struct device *dev = &pdev->dev;
-+	struct device_node *node = dev->of_node, *smi_node;
-+
-+	if (!node) {
-+		dev_err(dev, "No device tree node supplied!");
-+		return -EINVAL;
-+	}
-+
-+	smi_node = of_parse_phandle(node, "smi_handle", 0);
-+
-+	if (!smi_node) {
-+		dev_err(dev, "No such property: smi_handle");
-+		return -ENXIO;
-+	}
-+
-+	smi_inst = bcm2835_smi_get(smi_node);
-+
-+	if (!smi_inst)
-+		return -EPROBE_DEFER;
-+
-+	/* Allocate buffers and instance data */
-+
-+	inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
-+
-+	if (!inst)
-+		return -ENOMEM;
-+
-+	inst->dev = dev;
-+
-+	/* Create character device entries */
-+
-+	err = alloc_chrdev_region(&bcm2835_smi_devid,
-+				  DEVICE_MINOR, 1, DEVICE_NAME);
-+	if (err != 0) {
-+		dev_err(inst->dev, "unable to allocate device number");
-+		return -ENOMEM;
-+	}
-+	cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops);
-+	bcm2835_smi_cdev.owner = THIS_MODULE;
-+	err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1);
-+	if (err != 0) {
-+		dev_err(inst->dev, "unable to register device");
-+		err = -ENOMEM;
-+		goto failed_cdev_add;
-+	}
-+
-+	/* Create sysfs entries */
-+
-+	bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME);
-+	ptr_err = bcm2835_smi_class;
-+	if (IS_ERR(ptr_err))
-+		goto failed_class_create;
-+
-+	bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL,
-+					bcm2835_smi_devid, NULL,
-+					"smi");
-+	ptr_err = bcm2835_smi_dev;
-+	if (IS_ERR(ptr_err))
-+		goto failed_device_create;
-+
-+	dev_info(inst->dev, "initialised");
-+
-+	return 0;
-+
-+failed_device_create:
-+	class_destroy(bcm2835_smi_class);
-+failed_class_create:
-+	cdev_del(&bcm2835_smi_cdev);
-+	err = PTR_ERR(ptr_err);
-+failed_cdev_add:
-+	unregister_chrdev_region(bcm2835_smi_devid, 1);
-+	dev_err(dev, "could not load bcm2835_smi_dev");
-+	return err;
-+}
-+
-+/****************************************************************************
-+*
-+*   bcm2835_smi_remove - called when the driver is unloaded.
-+*
-+***************************************************************************/
-+
-+static int bcm2835_smi_dev_remove(struct platform_device *pdev)
-+{
-+	device_destroy(bcm2835_smi_class, bcm2835_smi_devid);
-+	class_destroy(bcm2835_smi_class);
-+	cdev_del(&bcm2835_smi_cdev);
-+	unregister_chrdev_region(bcm2835_smi_devid, 1);
-+
-+	dev_info(inst->dev, "SMI character dev removed - OK");
-+	return 0;
-+}
-+
-+/****************************************************************************
-+*
-+*   Register the driver with device tree
-+*
-+***************************************************************************/
-+
-+static const struct of_device_id bcm2835_smi_dev_of_match[] = {
-+	{.compatible = "brcm,bcm2835-smi-dev",},
-+	{ /* sentinel */ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match);
-+
-+static struct platform_driver bcm2835_smi_dev_driver = {
-+	.probe = bcm2835_smi_dev_probe,
-+	.remove = bcm2835_smi_dev_remove,
-+	.driver = {
-+		   .name = DRIVER_NAME,
-+		   .owner = THIS_MODULE,
-+		   .of_match_table = bcm2835_smi_dev_of_match,
-+		   },
-+};
-+
-+module_platform_driver(bcm2835_smi_dev_driver);
-+
-+MODULE_ALIAS("platform:smi-dev-bcm2835");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION(
-+	"Character device driver for BCM2835's secondary memory interface");
-+MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
---- a/drivers/misc/Kconfig
-+++ b/drivers/misc/Kconfig
-@@ -10,6 +10,14 @@ config SENSORS_LIS3LV02D
- 	select INPUT_POLLDEV
- 	default n
- 
-+config BCM2835_SMI
-+	tristate "Broadcom 283x Secondary Memory Interface driver"
-+	depends on ARCH_BCM2835
-+	default m
-+	help
-+		Driver for enabling and using Broadcom's Secondary/Slow Memory Interface.
-+		Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h
-+
- config AD525X_DPOT
- 	tristate "Analog Devices Digital Potentiometers"
- 	depends on (I2C || SPI) && SYSFS
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -10,6 +10,7 @@ obj-$(CONFIG_AD525X_DPOT_SPI)	+= ad525x_
- obj-$(CONFIG_INTEL_MID_PTI)	+= pti.o
- obj-$(CONFIG_ATMEL_SSC)		+= atmel-ssc.o
- obj-$(CONFIG_ATMEL_TCLIB)	+= atmel_tclib.o
-+obj-$(CONFIG_BCM2835_SMI)	+= bcm2835_smi.o
- obj-$(CONFIG_DUMMY_IRQ)		+= dummy-irq.o
- obj-$(CONFIG_ICS932S401)	+= ics932s401.o
- obj-$(CONFIG_LKDTM)		+= lkdtm.o
---- /dev/null
-+++ b/drivers/misc/bcm2835_smi.c
-@@ -0,0 +1,985 @@
-+/**
-+ * Broadcom Secondary Memory Interface driver
-+ *
-+ * Written by Luke Wren <luke@raspberrypi.org>
-+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_address.h>
-+#include <linux/of_platform.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/pagemap.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmaengine.h>
-+#include <linux/semaphore.h>
-+#include <linux/spinlock.h>
-+#include <linux/io.h>
-+
-+#define BCM2835_SMI_IMPLEMENTATION
-+#include <linux/broadcom/bcm2835_smi.h>
-+
-+#define DRIVER_NAME "smi-bcm2835"
-+
-+#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE)
-+
-+#define DMA_WRITE_TO_MEM true
-+#define DMA_READ_FROM_MEM false
-+
-+struct bcm2835_smi_instance {
-+	struct device *dev;
-+	struct smi_settings settings;
-+	__iomem void *smi_regs_ptr, *cm_smi_regs_ptr;
-+	dma_addr_t smi_regs_busaddr;
-+
-+	struct dma_chan *dma_chan;
-+	struct dma_slave_config dma_config;
-+
-+	struct bcm2835_smi_bounce_info bounce;
-+
-+	struct scatterlist buffer_sgl;
-+
-+	int clock_source;
-+	int clock_divisor;
-+
-+	/* Sometimes we are called into in an atomic context (e.g. by
-+	   JFFS2 + MTD) so we can't use a mutex */
-+	spinlock_t transaction_lock;
-+};
-+
-+/****************************************************************************
-+*
-+*   SMI clock manager setup
-+*
-+***************************************************************************/
-+
-+static inline void write_smi_cm_reg(struct bcm2835_smi_instance *inst,
-+	u32 val, unsigned reg)
-+{
-+	writel(CM_PWD | val, inst->cm_smi_regs_ptr + reg);
-+}
-+
-+static inline u32 read_smi_cm_reg(struct bcm2835_smi_instance *inst,
-+	unsigned reg)
-+{
-+	return readl(inst->cm_smi_regs_ptr + reg);
-+}
-+
-+static void smi_setup_clock(struct bcm2835_smi_instance *inst)
-+{
-+	dev_dbg(inst->dev, "Setting up clock...");
-+	/* Disable SMI clock and wait for it to stop. */
-+	write_smi_cm_reg(inst, 0, CM_SMI_CTL);
-+	while (read_smi_cm_reg(inst, CM_SMI_CTL) & CM_SMI_CTL_BUSY)
-+		;
-+
-+	write_smi_cm_reg(inst, (inst->clock_divisor << CM_SMI_DIV_DIVI_OFFS),
-+	       CM_SMI_DIV);
-+	write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS),
-+	       CM_SMI_CTL);
-+
-+	/* Enable the clock */
-+	write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS) |
-+	       CM_SMI_CTL_ENAB, CM_SMI_CTL);
-+}
-+
-+/****************************************************************************
-+*
-+*   SMI peripheral setup
-+*
-+***************************************************************************/
-+
-+static inline void write_smi_reg(struct bcm2835_smi_instance *inst,
-+	u32 val, unsigned reg)
-+{
-+	writel(val, inst->smi_regs_ptr + reg);
-+}
-+
-+static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg)
-+{
-+	return readl(inst->smi_regs_ptr + reg);
-+}
-+
-+/* Token-paste macro for e.g SMIDSR_RSTROBE ->  value of SMIDSR_RSTROBE_MASK */
-+#define _CONCAT(x, y) x##y
-+#define CONCAT(x, y) _CONCAT(x, y)
-+
-+#define SET_BIT_FIELD(dest, field, bits) ((dest) = \
-+	((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \
-+	 CONCAT(field, _MASK)))
-+#define GET_BIT_FIELD(src, field) (((src) & \
-+	CONCAT(field, _MASK)) >> CONCAT(field, _OFFS))
-+
-+static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst,
-+	const char *label)
-+{
-+	dev_err(inst->dev, "SMI context dump: %s", label);
-+	dev_err(inst->dev, "SMICS:  0x%08x", read_smi_reg(inst, SMICS));
-+	dev_err(inst->dev, "SMIL:   0x%08x", read_smi_reg(inst, SMIL));
-+	dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0));
-+	dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0));
-+	dev_err(inst->dev, "SMIDC:  0x%08x", read_smi_reg(inst, SMIDC));
-+	dev_err(inst->dev, "SMIFD:  0x%08x", read_smi_reg(inst, SMIFD));
-+	dev_err(inst->dev, " ");
-+}
-+
-+static inline void smi_dump_context(struct bcm2835_smi_instance *inst)
-+{
-+	smi_dump_context_labelled(inst, "");
-+}
-+
-+static void smi_get_default_settings(struct bcm2835_smi_instance *inst)
-+{
-+	struct smi_settings *settings = &inst->settings;
-+
-+	settings->data_width = SMI_WIDTH_16BIT;
-+	settings->pack_data = true;
-+
-+	settings->read_setup_time = 1;
-+	settings->read_hold_time = 1;
-+	settings->read_pace_time = 1;
-+	settings->read_strobe_time = 3;
-+
-+	settings->write_setup_time = settings->read_setup_time;
-+	settings->write_hold_time = settings->read_hold_time;
-+	settings->write_pace_time = settings->read_pace_time;
-+	settings->write_strobe_time = settings->read_strobe_time;
-+
-+	settings->dma_enable = true;
-+	settings->dma_passthrough_enable = false;
-+	settings->dma_read_thresh = 0x01;
-+	settings->dma_write_thresh = 0x3f;
-+	settings->dma_panic_read_thresh = 0x20;
-+	settings->dma_panic_write_thresh = 0x20;
-+}
-+
-+void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst)
-+{
-+	struct smi_settings *settings = &inst->settings;
-+	int smidsr_temp = 0, smidsw_temp = 0, smics_temp,
-+	    smidcs_temp, smidc_temp = 0;
-+
-+	spin_lock(&inst->transaction_lock);
-+
-+	/* temporarily disable the peripheral: */
-+	smics_temp = read_smi_reg(inst, SMICS);
-+	write_smi_reg(inst, 0, SMICS);
-+	smidcs_temp = read_smi_reg(inst, SMIDCS);
-+	write_smi_reg(inst, 0, SMIDCS);
-+
-+	if (settings->pack_data)
-+		smics_temp |= SMICS_PXLDAT;
-+	else
-+		smics_temp &= ~SMICS_PXLDAT;
-+
-+	SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width);
-+	SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time);
-+	SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time);
-+	SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time);
-+	SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time);
-+	write_smi_reg(inst, smidsr_temp, SMIDSR0);
-+
-+	SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width);
-+	if (settings->data_width == SMI_WIDTH_8BIT)
-+		smidsw_temp |= SMIDSW_WSWAP;
-+	else
-+		smidsw_temp &= ~SMIDSW_WSWAP;
-+	SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time);
-+	SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time);
-+	SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time);
-+	SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE,
-+			settings->write_strobe_time);
-+	write_smi_reg(inst, smidsw_temp, SMIDSW0);
-+
-+	SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh);
-+	SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh);
-+	SET_BIT_FIELD(smidc_temp, SMIDC_PANICR,
-+		      settings->dma_panic_read_thresh);
-+	SET_BIT_FIELD(smidc_temp, SMIDC_PANICW,
-+		      settings->dma_panic_write_thresh);
-+	if (settings->dma_passthrough_enable) {
-+		smidc_temp |= SMIDC_DMAP;
-+		smidsr_temp |= SMIDSR_RDREQ;
-+		write_smi_reg(inst, smidsr_temp, SMIDSR0);
-+		smidsw_temp |= SMIDSW_WDREQ;
-+		write_smi_reg(inst, smidsw_temp, SMIDSW0);
-+	} else
-+		smidc_temp &= ~SMIDC_DMAP;
-+	if (settings->dma_enable)
-+		smidc_temp |= SMIDC_DMAEN;
-+	else
-+		smidc_temp &= ~SMIDC_DMAEN;
-+
-+	write_smi_reg(inst, smidc_temp, SMIDC);
-+
-+	/* re-enable (if was previously enabled) */
-+	write_smi_reg(inst, smics_temp, SMICS);
-+	write_smi_reg(inst, smidcs_temp, SMIDCS);
-+
-+	spin_unlock(&inst->transaction_lock);
-+}
-+EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings);
-+
-+struct smi_settings *bcm2835_smi_get_settings_from_regs
-+	(struct bcm2835_smi_instance *inst)
-+{
-+	struct smi_settings *settings = &inst->settings;
-+	int smidsr, smidsw, smidc;
-+
-+	spin_lock(&inst->transaction_lock);
-+
-+	smidsr = read_smi_reg(inst, SMIDSR0);
-+	smidsw = read_smi_reg(inst, SMIDSW0);
-+	smidc = read_smi_reg(inst, SMIDC);
-+
-+	settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ?
-+	    true : false;
-+
-+	settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH);
-+	settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP);
-+	settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD);
-+	settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE);
-+	settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE);
-+
-+	settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP);
-+	settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD);
-+	settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE);
-+	settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE);
-+
-+	settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR);
-+	settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW);
-+	settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR);
-+	settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW);
-+	settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false;
-+	settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false;
-+
-+	spin_unlock(&inst->transaction_lock);
-+
-+	return settings;
-+}
-+EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs);
-+
-+static inline void smi_set_address(struct bcm2835_smi_instance *inst,
-+	unsigned int address)
-+{
-+	int smia_temp = 0, smida_temp = 0;
-+
-+	SET_BIT_FIELD(smia_temp, SMIA_ADDR, address);
-+	SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address);
-+
-+	/* Write to both address registers - user doesn't care whether we're
-+	   doing programmed or direct transfers. */
-+	write_smi_reg(inst, smia_temp, SMIA);
-+	write_smi_reg(inst, smida_temp, SMIDA);
-+}
-+
-+static void smi_setup_regs(struct bcm2835_smi_instance *inst)
-+{
-+
-+	dev_dbg(inst->dev, "Initialising SMI registers...");
-+	/* Disable the peripheral if already enabled */
-+	write_smi_reg(inst, 0, SMICS);
-+	write_smi_reg(inst, 0, SMIDCS);
-+
-+	smi_get_default_settings(inst);
-+	bcm2835_smi_set_regs_from_settings(inst);
-+	smi_set_address(inst, 0);
-+
-+	write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS);
-+	write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE,
-+		SMIDCS);
-+}
-+
-+/****************************************************************************
-+*
-+*   Low-level SMI access functions
-+*   Other modules should use the exported higher-level functions e.g.
-+*   bcm2835_smi_write_buf() unless they have a good reason to use these
-+*
-+***************************************************************************/
-+
-+static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst)
-+{
-+	int timeout = 0;
-+
-+	write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS);
-+	write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS);
-+	/* Make sure things happen in the right order...*/
-+	mb();
-+	while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
-+		++timeout < 10000)
-+		;
-+	if (timeout < 10000)
-+		return read_smi_reg(inst, SMIDD);
-+
-+	dev_err(inst->dev,
-+		"SMI direct read timed out (is the clock set up correctly?)");
-+	return 0;
-+}
-+
-+static inline void smi_write_single_word(struct bcm2835_smi_instance *inst,
-+	uint32_t data)
-+{
-+	int timeout = 0;
-+
-+	write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS);
-+	write_smi_reg(inst, data, SMIDD);
-+	write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START,
-+		SMIDCS);
-+
-+	while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
-+		++timeout < 10000)
-+		;
-+	if (timeout >= 10000)
-+		dev_err(inst->dev,
-+		"SMI direct write timed out (is the clock set up correctly?)");
-+}
-+
-+/* Initiates a programmed read into the read FIFO. It is up to the caller to
-+ * read data from the FIFO -  either via paced DMA transfer,
-+ * or polling SMICS_RXD to check whether data is available.
-+ * SMICS_ACTIVE will go low upon completion. */
-+static void smi_init_programmed_read(struct bcm2835_smi_instance *inst,
-+	int num_transfers)
-+{
-+	int smics_temp;
-+
-+	/* Disable the peripheral: */
-+	smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE);
-+	write_smi_reg(inst, smics_temp, SMICS);
-+	while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
-+		;
-+
-+	/* Program the transfer count: */
-+	write_smi_reg(inst, num_transfers, SMIL);
-+
-+	/* re-enable and start: */
-+	smics_temp |= SMICS_ENABLE;
-+	write_smi_reg(inst, smics_temp, SMICS);
-+	smics_temp |= SMICS_CLEAR;
-+	/* Just to be certain: */
-+	mb();
-+	while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
-+		;
-+	write_smi_reg(inst, smics_temp, SMICS);
-+	smics_temp |= SMICS_START;
-+	write_smi_reg(inst, smics_temp, SMICS);
-+}
-+
-+/* Initiates a programmed write sequence, using data from the write FIFO.
-+ * It is up to the caller to initiate a DMA transfer before calling,
-+ * or use another method to keep the write FIFO topped up.
-+ * SMICS_ACTIVE will go low upon completion.
-+ */
-+static void smi_init_programmed_write(struct bcm2835_smi_instance *inst,
-+	int num_transfers)
-+{
-+	int smics_temp;
-+
-+	/* Disable the peripheral: */
-+	smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
-+	write_smi_reg(inst, smics_temp, SMICS);
-+	while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
-+		;
-+
-+	/* Program the transfer count: */
-+	write_smi_reg(inst, num_transfers, SMIL);
-+
-+	/* setup, re-enable and start: */
-+	smics_temp |= SMICS_WRITE | SMICS_ENABLE;
-+	write_smi_reg(inst, smics_temp, SMICS);
-+	smics_temp |= SMICS_START;
-+	write_smi_reg(inst, smics_temp, SMICS);
-+}
-+
-+/* Initiate a read and then poll FIFO for data, reading out as it appears. */
-+static void smi_read_fifo(struct bcm2835_smi_instance *inst,
-+	uint32_t *dest, int n_bytes)
-+{
-+	if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
-+		smi_dump_context_labelled(inst,
-+			"WARNING: read FIFO not empty at start of read call.");
-+		while (read_smi_reg(inst, SMICS))
-+			;
-+	}
-+
-+	/* Dispatch the read: */
-+	if (inst->settings.data_width == SMI_WIDTH_8BIT)
-+		smi_init_programmed_read(inst, n_bytes);
-+	else if (inst->settings.data_width == SMI_WIDTH_16BIT)
-+		smi_init_programmed_read(inst, n_bytes / 2);
-+	else {
-+		dev_err(inst->dev, "Unsupported data width for read.");
-+		return;
-+	}
-+
-+	/* Poll FIFO to keep it empty */
-+	while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
-+		if (read_smi_reg(inst, SMICS) & SMICS_RXD)
-+			*dest++ = read_smi_reg(inst, SMID);
-+
-+	/* Ensure that the FIFO is emptied */
-+	if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
-+		int fifo_count;
-+
-+		fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD),
-+			SMIFD_FCNT);
-+		while (fifo_count--)
-+			*dest++ = read_smi_reg(inst, SMID);
-+	}
-+
-+	if (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
-+		smi_dump_context_labelled(inst,
-+			"WARNING: transaction finished but done bit not set.");
-+
-+	if (read_smi_reg(inst, SMICS) & SMICS_RXD)
-+		smi_dump_context_labelled(inst,
-+			"WARNING: read FIFO not empty at end of read call.");
-+
-+}
-+
-+/* Initiate a write, and then keep the FIFO topped up. */
-+static void smi_write_fifo(struct bcm2835_smi_instance *inst,
-+	uint32_t *src, int n_bytes)
-+{
-+	int i, timeout = 0;
-+
-+	/* Empty FIFOs if not already so */
-+	if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) {
-+		smi_dump_context_labelled(inst,
-+		    "WARNING: write fifo not empty at start of write call.");
-+		write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR,
-+			SMICS);
-+	}
-+
-+	/* Initiate the transfer */
-+	if (inst->settings.data_width == SMI_WIDTH_8BIT)
-+		smi_init_programmed_write(inst, n_bytes);
-+	else if (inst->settings.data_width == SMI_WIDTH_16BIT)
-+		smi_init_programmed_write(inst, n_bytes / 2);
-+	else {
-+		dev_err(inst->dev, "Unsupported data width for write.");
-+		return;
-+	}
-+	/* Fill the FIFO: */
-+	for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) {
-+		while (!(read_smi_reg(inst, SMICS) & SMICS_TXD))
-+			;
-+		write_smi_reg(inst, *src++, SMID);
-+	}
-+	/* Busy wait... */
-+	while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout <
-+		1000000)
-+		;
-+	if (timeout >= 1000000)
-+		smi_dump_context_labelled(inst,
-+			"Timed out on write operation!");
-+	if (!(read_smi_reg(inst, SMICS) & SMICS_TXE))
-+		smi_dump_context_labelled(inst,
-+			"WARNING: FIFO not empty at end of write operation.");
-+}
-+
-+/****************************************************************************
-+*
-+*   SMI DMA operations
-+*
-+***************************************************************************/
-+
-+/* Disable SMI and put it into the correct direction before doing DMA setup.
-+   Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */
-+static void smi_disable(struct bcm2835_smi_instance *inst,
-+	enum dma_transfer_direction direction)
-+{
-+	int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
-+
-+	if (direction == DMA_DEV_TO_MEM)
-+		smics_temp &= ~SMICS_WRITE;
-+	else
-+		smics_temp |= SMICS_WRITE;
-+	write_smi_reg(inst, smics_temp, SMICS);
-+	while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
-+		;
-+}
-+
-+static struct scatterlist *smi_scatterlist_from_buffer(
-+	struct bcm2835_smi_instance *inst,
-+	dma_addr_t buf,
-+	size_t len,
-+	struct scatterlist *sg)
-+{
-+	sg_init_table(sg, 1);
-+	sg_dma_address(sg) = buf;
-+	sg_dma_len(sg) = len;
-+	return sg;
-+}
-+
-+static void smi_dma_callback_user_copy(void *param)
-+{
-+	/* Notify the bottom half that a chunk is ready for user copy */
-+	struct bcm2835_smi_instance *inst =
-+		(struct bcm2835_smi_instance *)param;
-+
-+	up(&inst->bounce.callback_sem);
-+}
-+
-+/* Creates a descriptor, assigns the given callback, and submits the
-+   descriptor to dmaengine. Does not block - can queue up multiple
-+   descriptors and then wait for them all to complete.
-+   sg_len is the number of control blocks, NOT the number of bytes.
-+   dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM.
-+   callback can be NULL - in this case it is not called. */
-+static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl(
-+	struct bcm2835_smi_instance *inst,
-+	struct scatterlist *sgl,
-+	size_t sg_len,
-+	enum dma_transfer_direction dir,
-+	dma_async_tx_callback callback)
-+{
-+	struct dma_async_tx_descriptor *desc;
-+
-+	desc = dmaengine_prep_slave_sg(inst->dma_chan,
-+				       sgl,
-+				       sg_len,
-+				       dir,
-+				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK |
-+				       DMA_PREP_FENCE);
-+	if (!desc) {
-+		dev_err(inst->dev, "read_sgl: dma slave preparation failed!");
-+		write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE,
-+			SMICS);
-+		while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
-+			cpu_relax();
-+		write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE,
-+			SMICS);
-+		return NULL;
-+	}
-+	desc->callback = callback;
-+	desc->callback_param = inst;
-+	if (dmaengine_submit(desc) < 0)
-+		return NULL;
-+	return desc;
-+}
-+
-+/* NB this function blocks until the transfer is complete */
-+static void
-+smi_dma_read_sgl(struct bcm2835_smi_instance *inst,
-+	struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
-+{
-+	struct dma_async_tx_descriptor *desc;
-+
-+	/* Disable SMI and set to read before dispatching DMA - if SMI is in
-+	 * write mode and TX fifo is empty, it will generate a DREQ which may
-+	 * cause the read DMA to complete before the SMI read command is even
-+	 * dispatched! We want to dispatch DMA before SMI read so that reading
-+	 * is gapless, for logic analyser.
-+	 */
-+
-+	smi_disable(inst, DMA_DEV_TO_MEM);
-+
-+	desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL);
-+	dma_async_issue_pending(inst->dma_chan);
-+
-+	if (inst->settings.data_width == SMI_WIDTH_8BIT)
-+		smi_init_programmed_read(inst, n_bytes);
-+	else
-+		smi_init_programmed_read(inst, n_bytes / 2);
-+
-+	if (dma_wait_for_async_tx(desc) == DMA_ERROR)
-+		smi_dump_context_labelled(inst, "DMA timeout!");
-+}
-+
-+static void
-+smi_dma_write_sgl(struct bcm2835_smi_instance *inst,
-+	struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
-+{
-+	struct dma_async_tx_descriptor *desc;
-+
-+	if (inst->settings.data_width == SMI_WIDTH_8BIT)
-+		smi_init_programmed_write(inst, n_bytes);
-+	else
-+		smi_init_programmed_write(inst, n_bytes / 2);
-+
-+	desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL);
-+	dma_async_issue_pending(inst->dma_chan);
-+
-+	if (dma_wait_for_async_tx(desc) == DMA_ERROR)
-+		smi_dump_context_labelled(inst, "DMA timeout!");
-+	else
-+		/* Wait for SMI to finish our writes */
-+		while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
-+			cpu_relax();
-+}
-+
-+ssize_t bcm2835_smi_user_dma(
-+	struct bcm2835_smi_instance *inst,
-+	enum dma_transfer_direction dma_dir,
-+	char __user *user_ptr, size_t count,
-+	struct bcm2835_smi_bounce_info **bounce)
-+{
-+	int chunk_no = 0, chunk_size, count_left = count;
-+	struct scatterlist *sgl;
-+	void (*init_trans_func)(struct bcm2835_smi_instance *, int);
-+
-+	spin_lock(&inst->transaction_lock);
-+
-+	if (dma_dir == DMA_DEV_TO_MEM)
-+		init_trans_func = smi_init_programmed_read;
-+	else
-+		init_trans_func = smi_init_programmed_write;
-+
-+	smi_disable(inst, dma_dir);
-+
-+	sema_init(&inst->bounce.callback_sem, 0);
-+	if (bounce)
-+		*bounce = &inst->bounce;
-+	while (count_left) {
-+		chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
-+			DMA_BOUNCE_BUFFER_SIZE : count_left;
-+		if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) {
-+			sgl =
-+			&inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
-+		} else {
-+			sgl = smi_scatterlist_from_buffer(
-+				inst,
-+				inst->bounce.phys[
-+					chunk_no % DMA_BOUNCE_BUFFER_COUNT],
-+				chunk_size,
-+				&inst->buffer_sgl);
-+		}
-+
-+		if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir,
-+			smi_dma_callback_user_copy
-+		)) {
-+			dev_err(inst->dev, "sgl submit failed");
-+			count = 0;
-+			goto out;
-+		}
-+		count_left -= chunk_size;
-+		chunk_no++;
-+	}
-+	dma_async_issue_pending(inst->dma_chan);
-+
-+	if (inst->settings.data_width == SMI_WIDTH_8BIT)
-+		init_trans_func(inst, count);
-+	else if (inst->settings.data_width == SMI_WIDTH_16BIT)
-+		init_trans_func(inst, count / 2);
-+out:
-+	spin_unlock(&inst->transaction_lock);
-+	return count;
-+}
-+EXPORT_SYMBOL(bcm2835_smi_user_dma);
-+
-+
-+/****************************************************************************
-+*
-+*   High level buffer transfer functions - for use by other drivers
-+*
-+***************************************************************************/
-+
-+/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */
-+void bcm2835_smi_write_buf(
-+	struct bcm2835_smi_instance *inst,
-+	const void *buf, size_t n_bytes)
-+{
-+	int odd_bytes = n_bytes & 0x3;
-+
-+	n_bytes -= odd_bytes;
-+
-+	spin_lock(&inst->transaction_lock);
-+
-+	if (n_bytes > DMA_THRESHOLD_BYTES) {
-+		dma_addr_t phy_addr = dma_map_single(
-+			inst->dev,
-+			(void *)buf,
-+			n_bytes,
-+			DMA_MEM_TO_DEV);
-+		struct scatterlist *sgl =
-+			smi_scatterlist_from_buffer(inst, phy_addr, n_bytes,
-+				&inst->buffer_sgl);
-+
-+		if (!sgl) {
-+			smi_dump_context_labelled(inst,
-+			"Error: could not create scatterlist for write!");
-+			goto out;
-+		}
-+		smi_dma_write_sgl(inst, sgl, 1, n_bytes);
-+
-+		dma_unmap_single
-+			(inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV);
-+	} else if (n_bytes) {
-+		smi_write_fifo(inst, (uint32_t *) buf, n_bytes);
-+	}
-+	buf += n_bytes;
-+
-+	if (inst->settings.data_width == SMI_WIDTH_8BIT) {
-+		while (odd_bytes--)
-+			smi_write_single_word(inst, *(uint8_t *) (buf++));
-+	} else {
-+		while (odd_bytes >= 2) {
-+			smi_write_single_word(inst, *(uint16_t *)buf);
-+			buf += 2;
-+			odd_bytes -= 2;
-+		}
-+		if (odd_bytes) {
-+			/* Reading an odd number of bytes on a 16 bit bus is
-+			   a user bug. It's kinder to fail early and tell them
-+			   than to e.g. transparently give them the bottom byte
-+			   of a 16 bit transfer. */
-+			dev_err(inst->dev,
-+		"WARNING: odd number of bytes specified for wide transfer.");
-+			dev_err(inst->dev,
-+		"At least one byte dropped as a result.");
-+			dump_stack();
-+		}
-+	}
-+out:
-+	spin_unlock(&inst->transaction_lock);
-+}
-+EXPORT_SYMBOL(bcm2835_smi_write_buf);
-+
-+void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst,
-+	void *buf, size_t n_bytes)
-+{
-+
-+	/* SMI is inherently 32-bit, which causes surprising amounts of mess
-+	   for bytes % 4 != 0. Easiest to avoid this mess altogether
-+	   by handling remainder separately. */
-+	int odd_bytes = n_bytes & 0x3;
-+
-+	spin_lock(&inst->transaction_lock);
-+	n_bytes -= odd_bytes;
-+	if (n_bytes > DMA_THRESHOLD_BYTES) {
-+		dma_addr_t phy_addr = dma_map_single(inst->dev,
-+						     buf, n_bytes,
-+						     DMA_DEV_TO_MEM);
-+		struct scatterlist *sgl = smi_scatterlist_from_buffer(
-+			inst, phy_addr, n_bytes,
-+			&inst->buffer_sgl);
-+		if (!sgl) {
-+			smi_dump_context_labelled(inst,
-+			"Error: could not create scatterlist for read!");
-+			goto out;
-+		}
-+		smi_dma_read_sgl(inst, sgl, 1, n_bytes);
-+		dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM);
-+	} else if (n_bytes) {
-+		smi_read_fifo(inst, (uint32_t *)buf, n_bytes);
-+	}
-+	buf += n_bytes;
-+
-+	if (inst->settings.data_width == SMI_WIDTH_8BIT) {
-+		while (odd_bytes--)
-+			*((uint8_t *) (buf++)) = smi_read_single_word(inst);
-+	} else {
-+		while (odd_bytes >= 2) {
-+			*(uint16_t *) buf = smi_read_single_word(inst);
-+			buf += 2;
-+			odd_bytes -= 2;
-+		}
-+		if (odd_bytes) {
-+			dev_err(inst->dev,
-+		"WARNING: odd number of bytes specified for wide transfer.");
-+			dev_err(inst->dev,
-+		"At least one byte dropped as a result.");
-+			dump_stack();
-+		}
-+	}
-+out:
-+	spin_unlock(&inst->transaction_lock);
-+}
-+EXPORT_SYMBOL(bcm2835_smi_read_buf);
-+
-+void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
-+	unsigned int address)
-+{
-+	spin_lock(&inst->transaction_lock);
-+	smi_set_address(inst, address);
-+	spin_unlock(&inst->transaction_lock);
-+}
-+EXPORT_SYMBOL(bcm2835_smi_set_address);
-+
-+struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node)
-+{
-+	struct platform_device *pdev;
-+
-+	if (!node)
-+		return NULL;
-+
-+	pdev = of_find_device_by_node(node);
-+	if (!pdev)
-+		return NULL;
-+
-+	return platform_get_drvdata(pdev);
-+}
-+EXPORT_SYMBOL(bcm2835_smi_get);
-+
-+/****************************************************************************
-+*
-+*   bcm2835_smi_probe - called when the driver is loaded.
-+*
-+***************************************************************************/
-+
-+static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst)
-+{
-+	int i, rv = 0;
-+
-+	inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx");
-+
-+	inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+	inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+	inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID;
-+	inst->dma_config.dst_addr = inst->dma_config.src_addr;
-+	/* Direction unimportant - always overridden by prep_slave_sg */
-+	inst->dma_config.direction = DMA_DEV_TO_MEM;
-+	dmaengine_slave_config(inst->dma_chan, &inst->dma_config);
-+	/* Alloc and map bounce buffers */
-+	for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) {
-+		inst->bounce.buffer[i] =
-+		dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE,
-+				&inst->bounce.phys[i],
-+				GFP_KERNEL);
-+		if (!inst->bounce.buffer[i]) {
-+			dev_err(inst->dev, "Could not allocate buffer!");
-+			rv = -ENOMEM;
-+			break;
-+		}
-+		smi_scatterlist_from_buffer(
-+			inst,
-+			inst->bounce.phys[i],
-+			DMA_BOUNCE_BUFFER_SIZE,
-+			&inst->bounce.sgl[i]
-+		);
-+	}
-+
-+	return rv;
-+}
-+
-+static int bcm2835_smi_probe(struct platform_device *pdev)
-+{
-+	int err;
-+	struct device *dev = &pdev->dev;
-+	struct device_node *node = dev->of_node;
-+	struct resource *ioresource;
-+	struct bcm2835_smi_instance *inst;
-+
-+	/* Allocate buffers and instance data */
-+
-+	inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance),
-+		GFP_KERNEL);
-+
-+	if (!inst)
-+		return -ENOMEM;
-+
-+	inst->dev = dev;
-+	spin_lock_init(&inst->transaction_lock);
-+
-+	/* We require device tree support */
-+	if (!node)
-+		return -EINVAL;
-+
-+	ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
-+	ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	inst->cm_smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
-+	inst->smi_regs_busaddr = be32_to_cpu(
-+		*of_get_address(node, 0, NULL, NULL));
-+	of_property_read_u32(node,
-+			     "brcm,smi-clock-source",
-+			     &inst->clock_source);
-+	of_property_read_u32(node,
-+			     "brcm,smi-clock-divisor",
-+			     &inst->clock_divisor);
-+
-+	err = bcm2835_smi_dma_setup(inst);
-+	if (err)
-+		return err;
-+
-+	/* Finally, do peripheral setup */
-+
-+	smi_setup_clock(inst);
-+	smi_setup_regs(inst);
-+
-+	platform_set_drvdata(pdev, inst);
-+
-+	dev_info(inst->dev, "initialised");
-+
-+	return 0;
-+}
-+
-+/****************************************************************************
-+*
-+*   bcm2835_smi_remove - called when the driver is unloaded.
-+*
-+***************************************************************************/
-+
-+static int bcm2835_smi_remove(struct platform_device *pdev)
-+{
-+	struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev);
-+	struct device *dev = inst->dev;
-+
-+	dev_info(dev, "SMI device removed - OK");
-+	return 0;
-+}
-+
-+/****************************************************************************
-+*
-+*   Register the driver with device tree
-+*
-+***************************************************************************/
-+
-+static const struct of_device_id bcm2835_smi_of_match[] = {
-+	{.compatible = "brcm,bcm2835-smi",},
-+	{ /* sentinel */ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match);
-+
-+static struct platform_driver bcm2835_smi_driver = {
-+	.probe = bcm2835_smi_probe,
-+	.remove = bcm2835_smi_remove,
-+	.driver = {
-+		   .name = DRIVER_NAME,
-+		   .owner = THIS_MODULE,
-+		   .of_match_table = bcm2835_smi_of_match,
-+		   },
-+};
-+
-+module_platform_driver(bcm2835_smi_driver);
-+
-+MODULE_ALIAS("platform:smi-bcm2835");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface");
-+MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
---- /dev/null
-+++ b/include/linux/broadcom/bcm2835_smi.h
-@@ -0,0 +1,391 @@
-+/**
-+ * Declarations and definitions for Broadcom's Secondary Memory Interface
-+ *
-+ * Written by Luke Wren <luke@raspberrypi.org>
-+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
-+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef BCM2835_SMI_H
-+#define BCM2835_SMI_H
-+
-+#include <linux/ioctl.h>
-+
-+#ifndef __KERNEL__
-+#include <stdint.h>
-+#include <stdbool.h>
-+#endif
-+
-+#define BCM2835_SMI_IOC_MAGIC 0x1
-+#define BCM2835_SMI_INVALID_HANDLE (~0)
-+
-+/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
-+#define BCM2835_SMI_IOC_GET_SETTINGS    _IO(BCM2835_SMI_IOC_MAGIC, 0)
-+#define BCM2835_SMI_IOC_WRITE_SETTINGS  _IO(BCM2835_SMI_IOC_MAGIC, 1)
-+#define BCM2835_SMI_IOC_ADDRESS	 _IO(BCM2835_SMI_IOC_MAGIC, 2)
-+#define BCM2835_SMI_IOC_MAX	     2
-+
-+#define SMI_WIDTH_8BIT 0
-+#define SMI_WIDTH_16BIT 1
-+#define SMI_WIDTH_9BIT 2
-+#define SMI_WIDTH_18BIT 3
-+
-+/* max number of bytes where DMA will not be used */
-+#define DMA_THRESHOLD_BYTES 128
-+#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
-+#define DMA_BOUNCE_BUFFER_COUNT 3
-+
-+
-+struct smi_settings {
-+	int data_width;
-+	/* Whether or not to pack multiple SMI transfers into a
-+	   single 32 bit FIFO word */
-+	bool pack_data;
-+
-+	/* Timing for reads (writes the same but for WE)
-+	 *
-+	 * OE ----------+	   +--------------------
-+	 *		|	   |
-+	 *		+----------+
-+	 * SD -<==============================>-----------
-+	 * SA -<=========================================>-
-+	 *    <-setup->  <-strobe ->  <-hold ->  <- pace ->
-+	 */
-+
-+	int read_setup_time;
-+	int read_hold_time;
-+	int read_pace_time;
-+	int read_strobe_time;
-+
-+	int write_setup_time;
-+	int write_hold_time;
-+	int write_pace_time;
-+	int write_strobe_time;
-+
-+	bool dma_enable;		/* DREQs */
-+	bool dma_passthrough_enable;	/* External DREQs */
-+	int dma_read_thresh;
-+	int dma_write_thresh;
-+	int dma_panic_read_thresh;
-+	int dma_panic_write_thresh;
-+};
-+
-+/****************************************************************************
-+*
-+*   Declare exported SMI functions
-+*
-+***************************************************************************/
-+
-+#ifdef __KERNEL__
-+
-+#include <linux/dmaengine.h> /* for enum dma_transfer_direction */
-+#include <linux/of.h>
-+#include <linux/semaphore.h>
-+
-+struct bcm2835_smi_instance;
-+
-+struct bcm2835_smi_bounce_info {
-+	struct semaphore callback_sem;
-+	void *buffer[DMA_BOUNCE_BUFFER_COUNT];
-+	dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
-+	struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
-+};
-+
-+
-+void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
-+
-+struct smi_settings *bcm2835_smi_get_settings_from_regs(
-+	struct bcm2835_smi_instance *inst);
-+
-+void bcm2835_smi_write_buf(
-+	struct bcm2835_smi_instance *inst,
-+	const void *buf,
-+	size_t n_bytes);
-+
-+void bcm2835_smi_read_buf(
-+	struct bcm2835_smi_instance *inst,
-+	void *buf,
-+	size_t n_bytes);
-+
-+void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
-+	unsigned int address);
-+
-+ssize_t bcm2835_smi_user_dma(
-+	struct bcm2835_smi_instance *inst,
-+	enum dma_transfer_direction dma_dir,
-+	char __user *user_ptr,
-+	size_t count,
-+	struct bcm2835_smi_bounce_info **bounce);
-+
-+struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
-+
-+#endif /* __KERNEL__ */
-+
-+/****************************************************************
-+*
-+*	Implementation-only declarations
-+*
-+****************************************************************/
-+
-+#ifdef BCM2835_SMI_IMPLEMENTATION
-+
-+/* Clock manager registers for SMI clock: */
-+#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
-+/* Clock manager "password" to protect registers from spurious writes */
-+#define CM_PWD (0x5a << 24)
-+
-+#define CM_SMI_CTL	0x00
-+#define CM_SMI_DIV	0x04
-+
-+#define CM_SMI_CTL_FLIP (1 << 8)
-+#define CM_SMI_CTL_BUSY (1 << 7)
-+#define CM_SMI_CTL_KILL (1 << 5)
-+#define CM_SMI_CTL_ENAB (1 << 4)
-+#define CM_SMI_CTL_SRC_MASK (0xf)
-+#define CM_SMI_CTL_SRC_OFFS (0)
-+
-+#define CM_SMI_DIV_DIVI_MASK (0xf <<  12)
-+#define CM_SMI_DIV_DIVI_OFFS (12)
-+#define CM_SMI_DIV_DIVF_MASK (0xff << 4)
-+#define CM_SMI_DIV_DIVF_OFFS (4)
-+
-+/* SMI register mapping:*/
-+#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
-+
-+#define SMICS	0x00	/* control + status register		*/
-+#define SMIL	0x04	/* length/count (n external txfers)	*/
-+#define SMIA	0x08	/* address register			*/
-+#define SMID	0x0c	/* data register			*/
-+#define SMIDSR0	0x10	/* device 0 read settings		*/
-+#define SMIDSW0	0x14	/* device 0 write settings		*/
-+#define SMIDSR1	0x18	/* device 1 read settings		*/
-+#define SMIDSW1	0x1c	/* device 1 write settings		*/
-+#define SMIDSR2	0x20	/* device 2 read settings		*/
-+#define SMIDSW2	0x24	/* device 2 write settings		*/
-+#define SMIDSR3	0x28	/* device 3 read settings		*/
-+#define SMIDSW3	0x2c	/* device 3 write settings		*/
-+#define SMIDC	0x30	/* DMA control registers		*/
-+#define SMIDCS	0x34	/* direct control/status register	*/
-+#define SMIDA	0x38	/* direct address register		*/
-+#define SMIDD	0x3c	/* direct data registers		*/
-+#define SMIFD	0x40	/* FIFO debug register			*/
-+
-+
-+
-+/* Control and Status register bits:
-+ * SMICS_RXF	: RX fifo full: 1 when RX fifo is full
-+ * SMICS_TXE	: TX fifo empty: 1 when empty.
-+ * SMICS_RXD	: RX fifo contains data: 1 when there is data.
-+ * SMICS_TXD	: TX fifo can accept data: 1 when true.
-+ * SMICS_RXR	: RX fifo needs reading: 1 when fifo more than 3/4 full, or
-+ *		  when "DONE" and fifo not emptied.
-+ * SMICS_TXW	: TX fifo needs writing: 1 when less than 1/4 full.
-+ * SMICS_AFERR	: AXI FIFO error: 1 when fifo read when empty or written
-+ *		  when full. Write 1 to clear.
-+ * SMICS_EDREQ	: 1 when external DREQ received.
-+ * SMICS_PXLDAT	:  Pixel data:	write 1 to enable pixel transfer modes.
-+ * SMICS_SETERR	: 1 if there was an error writing to setup regs (e.g.
-+ *		  tx was in progress). Write 1 to clear.
-+ * SMICS_PVMODE	: Set to 1 to enable pixel valve mode.
-+ * SMICS_INTR	: Set to 1 to enable interrupt on RX.
-+ * SMICS_INTT	: Set to 1 to enable interrupt on TX.
-+ * SMICS_INTD	: Set to 1 to enable interrupt on DONE condition.
-+ * SMICS_TEEN	: Tear effect mode enabled: Programmed transfers will wait
-+ *		  for a TE trigger before writing.
-+ * SMICS_PAD1	: Padding settings for external transfers. For writes: the
-+ *		  number of bytes initially written to  the TX fifo that
-+ * SMICS_PAD0	: should be ignored. For reads: the number of bytes that will
-+ *		  be read before the data, and should be dropped.
-+ * SMICS_WRITE	: Transfer direction: 1 = write to external device, 0 = read
-+ * SMICS_CLEAR	: Write 1 to clear the FIFOs.
-+ * SMICS_START	: Write 1 to start the programmed transfer.
-+ * SMICS_ACTIVE	: Reads as 1 when a programmed transfer is underway.
-+ * SMICS_DONE	: Reads as 1 when transfer finished. For RX, not set until
-+ *		  FIFO emptied.
-+ * SMICS_ENABLE	: Set to 1 to enable the SMI peripheral, 0 to disable.
-+ */
-+
-+#define SMICS_RXF	(1 << 31)
-+#define SMICS_TXE	(1 << 30)
-+#define SMICS_RXD	(1 << 29)
-+#define SMICS_TXD	(1 << 28)
-+#define SMICS_RXR	(1 << 27)
-+#define SMICS_TXW	(1 << 26)
-+#define SMICS_AFERR	(1 << 25)
-+#define SMICS_EDREQ	(1 << 15)
-+#define SMICS_PXLDAT	(1 << 14)
-+#define SMICS_SETERR	(1 << 13)
-+#define SMICS_PVMODE	(1 << 12)
-+#define SMICS_INTR	(1 << 11)
-+#define SMICS_INTT	(1 << 10)
-+#define SMICS_INTD	(1 << 9)
-+#define SMICS_TEEN	(1 << 8)
-+#define SMICS_PAD1	(1 << 7)
-+#define SMICS_PAD0	(1 << 6)
-+#define SMICS_WRITE	(1 << 5)
-+#define SMICS_CLEAR	(1 << 4)
-+#define SMICS_START	(1 << 3)
-+#define SMICS_ACTIVE	(1 << 2)
-+#define SMICS_DONE	(1 << 1)
-+#define SMICS_ENABLE	(1 << 0)
-+
-+/* Address register bits: */
-+
-+#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
-+#define SMIA_DEVICE_OFFS (8)
-+#define SMIA_ADDR_MASK (0x3f)	/* bits 5 -> 0 */
-+#define SMIA_ADDR_OFFS (0)
-+
-+/* DMA control register bits:
-+ * SMIDC_DMAEN	: DMA enable: set 1: DMA requests will be issued.
-+ * SMIDC_DMAP	: DMA passthrough: when set to 0, top two data pins are used by
-+ *		  SMI as usual. When set to 1, the top two pins are used for
-+ *		  external DREQs: pin 16 read request, 17 write.
-+ * SMIDC_PANIC*	: Threshold at which DMA will panic during read/write.
-+ * SMIDC_REQ*	: Threshold at which DMA will generate a DREQ.
-+ */
-+
-+#define SMIDC_DMAEN		(1 << 28)
-+#define SMIDC_DMAP		(1 << 24)
-+#define SMIDC_PANICR_MASK	(0x3f << 18)
-+#define SMIDC_PANICR_OFFS	(18)
-+#define SMIDC_PANICW_MASK	(0x3f << 12)
-+#define SMIDC_PANICW_OFFS	(12)
-+#define SMIDC_REQR_MASK		(0x3f << 6)
-+#define SMIDC_REQR_OFFS		(6)
-+#define SMIDC_REQW_MASK		(0x3f)
-+#define SMIDC_REQW_OFFS		(0)
-+
-+/* Device settings register bits: same for all 4 (or 3?) device register sets.
-+ * Device read settings:
-+ * SMIDSR_RWIDTH	: Read transfer width. 00 = 8bit, 01 = 16bit,
-+ *			  10 = 18bit, 11 = 9bit.
-+ * SMIDSR_RSETUP	: Read setup time: number of core cycles between chip
-+ *			  select/address and read strobe. Min 1, max 64.
-+ * SMIDSR_MODE68	: 1 for System 68 mode (i.e. enable + direction pins,
-+ *			  rather than OE + WE pin)
-+ * SMIDSR_FSETUP	: If set to 1, setup time only applies to first
-+ *			  transfer after address change.
-+ * SMIDSR_RHOLD		: Number of core cycles between read strobe going
-+ *			  inactive and CS/address going inactive. Min 1, max 64
-+ * SMIDSR_RPACEALL	: When set to 1, this device's RPACE value will always
-+ *			  be used for the next transaction, even if it is not
-+ *			  to this device.
-+ * SMIDSR_RPACE		: Number of core cycles spent waiting between CS
-+ *			  deassert and start of next transfer. Min 1, max 128
-+ * SMIDSR_RDREQ		: 1 = use external DMA request on SD16 to pace reads
-+ *			  from device. Must also set DMAP in SMICS.
-+ * SMIDSR_RSTROBE	: Number of cycles to assert the read strobe.
-+ *			  min 1, max 128.
-+ */
-+#define SMIDSR_RWIDTH_MASK	((1<<31)|(1<<30))
-+#define SMIDSR_RWIDTH_OFFS	(30)
-+#define SMIDSR_RSETUP_MASK	(0x3f << 24)
-+#define SMIDSR_RSETUP_OFFS	(24)
-+#define SMIDSR_MODE68		(1 << 23)
-+#define SMIDSR_FSETUP		(1 << 22)
-+#define SMIDSR_RHOLD_MASK	(0x3f << 16)
-+#define SMIDSR_RHOLD_OFFS	(16)
-+#define SMIDSR_RPACEALL		(1 << 15)
-+#define SMIDSR_RPACE_MASK	(0x7f << 8)
-+#define SMIDSR_RPACE_OFFS	(8)
-+#define SMIDSR_RDREQ		(1 << 7)
-+#define SMIDSR_RSTROBE_MASK	(0x7f)
-+#define SMIDSR_RSTROBE_OFFS	(0)
-+
-+/* Device write settings:
-+ * SMIDSW_WWIDTH	: Write transfer width. 00 = 8bit, 01 = 16bit,
-+ *			  10= 18bit, 11 = 9bit.
-+ * SMIDSW_WSETUP	: Number of cycles between CS assert and write strobe.
-+ *			  Min 1, max 64.
-+ * SMIDSW_WFORMAT	: Pixel format of input. 0 = 16bit RGB 565,
-+ *			  1 = 32bit RGBA 8888
-+ * SMIDSW_WSWAP		: 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
-+ * SMIDSW_WHOLD		: Time between WE deassert and CS deassert. 1 to 64
-+ * SMIDSW_WPACEALL	: 1: this device's WPACE will be used for the next
-+ *			  transfer, regardless of that transfer's device.
-+ * SMIDSW_WPACE		: Cycles between CS deassert and next CS assert.
-+ *			  Min 1, max 128
-+ * SMIDSW_WDREQ		: Use external DREQ on pin 17 to pace writes. DMAP must
-+ *			  be set in SMICS.
-+ * SMIDSW_WSTROBE	: Number of cycles to assert the write strobe.
-+ *			  Min 1, max 128
-+ */
-+#define SMIDSW_WWIDTH_MASK	 ((1<<31)|(1<<30))
-+#define SMIDSW_WWIDTH_OFFS	(30)
-+#define SMIDSW_WSETUP_MASK	(0x3f << 24)
-+#define SMIDSW_WSETUP_OFFS	(24)
-+#define SMIDSW_WFORMAT		(1 << 23)
-+#define SMIDSW_WSWAP		(1 << 22)
-+#define SMIDSW_WHOLD_MASK	(0x3f << 16)
-+#define SMIDSW_WHOLD_OFFS	(16)
-+#define SMIDSW_WPACEALL		(1 << 15)
-+#define SMIDSW_WPACE_MASK	(0x7f << 8)
-+#define SMIDSW_WPACE_OFFS	(8)
-+#define SMIDSW_WDREQ		(1 << 7)
-+#define SMIDSW_WSTROBE_MASK	 (0x7f)
-+#define SMIDSW_WSTROBE_OFFS	 (0)
-+
-+/* Direct transfer control + status register
-+ * SMIDCS_WRITE	: Direction of transfer: 1 -> write, 0 -> read
-+ * SMIDCS_DONE	: 1 when a transfer has finished. Write 1 to clear.
-+ * SMIDCS_START	: Write 1 to start a transfer, if one is not already underway.
-+ * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
-+ */
-+
-+#define SMIDCS_WRITE		(1 << 3)
-+#define SMIDCS_DONE		(1 << 2)
-+#define SMIDCS_START		(1 << 1)
-+#define SMIDCS_ENABLE		(1 << 0)
-+
-+/* Direct transfer address register
-+ * SMIDA_DEVICE	: Indicates which of the device settings banks should be used.
-+ * SMIDA_ADDR	: The value to be asserted on the address pins.
-+ */
-+
-+#define SMIDA_DEVICE_MASK	((1<<9)|(1<<8))
-+#define SMIDA_DEVICE_OFFS	(8)
-+#define SMIDA_ADDR_MASK		(0x3f)
-+#define SMIDA_ADDR_OFFS		(0)
-+
-+/* FIFO debug register
-+ * SMIFD_FLVL	: The high-tide mark of FIFO count during the most recent txfer
-+ * SMIFD_FCNT	: The current FIFO count.
-+ */
-+#define SMIFD_FLVL_MASK		(0x3f << 8)
-+#define SMIFD_FLVL_OFFS		(8)
-+#define SMIFD_FCNT_MASK		(0x3f)
-+#define SMIFD_FCNT_OFFS		(0)
-+
-+#endif /* BCM2835_SMI_IMPLEMENTATION */
-+
-+#endif /* BCM2835_SMI_H */
diff --git a/target/linux/brcm2708/patches-4.14/950-0046-MISC-bcm2835-smi-use-clock-manager-and-fix-reload-is.patch b/target/linux/brcm2708/patches-4.14/950-0046-MISC-bcm2835-smi-use-clock-manager-and-fix-reload-is.patch
deleted file mode 100644
index b3d866341..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0046-MISC-bcm2835-smi-use-clock-manager-and-fix-reload-is.patch
+++ /dev/null
@@ -1,170 +0,0 @@
-From af71606e2a65286f07c5908399f275f62fcbe2b9 Mon Sep 17 00:00:00 2001
-From: Martin Sperl <kernel@martin.sperl.org>
-Date: Tue, 26 Apr 2016 14:59:21 +0000
-Subject: [PATCH 046/454] MISC: bcm2835: smi: use clock manager and fix reload
- issues
-
-Use clock manager instead of self-made clockmanager.
-
-Also fix some error paths that showd up during development
-(especially missing release of dma resources on rmmod)
-
-Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
----
- drivers/misc/bcm2835_smi.c | 86 +++++++++++++-------------------------
- 1 file changed, 28 insertions(+), 58 deletions(-)
-
---- a/drivers/misc/bcm2835_smi.c
-+++ b/drivers/misc/bcm2835_smi.c
-@@ -34,6 +34,7 @@
-  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- 
-+#include <linux/clk.h>
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/of.h>
-@@ -62,7 +63,7 @@
- struct bcm2835_smi_instance {
- 	struct device *dev;
- 	struct smi_settings settings;
--	__iomem void *smi_regs_ptr, *cm_smi_regs_ptr;
-+	__iomem void *smi_regs_ptr;
- 	dma_addr_t smi_regs_busaddr;
- 
- 	struct dma_chan *dma_chan;
-@@ -72,8 +73,7 @@ struct bcm2835_smi_instance {
- 
- 	struct scatterlist buffer_sgl;
- 
--	int clock_source;
--	int clock_divisor;
-+	struct clk *clk;
- 
- 	/* Sometimes we are called into in an atomic context (e.g. by
- 	   JFFS2 + MTD) so we can't use a mutex */
-@@ -82,42 +82,6 @@ struct bcm2835_smi_instance {
- 
- /****************************************************************************
- *
--*   SMI clock manager setup
--*
--***************************************************************************/
--
--static inline void write_smi_cm_reg(struct bcm2835_smi_instance *inst,
--	u32 val, unsigned reg)
--{
--	writel(CM_PWD | val, inst->cm_smi_regs_ptr + reg);
--}
--
--static inline u32 read_smi_cm_reg(struct bcm2835_smi_instance *inst,
--	unsigned reg)
--{
--	return readl(inst->cm_smi_regs_ptr + reg);
--}
--
--static void smi_setup_clock(struct bcm2835_smi_instance *inst)
--{
--	dev_dbg(inst->dev, "Setting up clock...");
--	/* Disable SMI clock and wait for it to stop. */
--	write_smi_cm_reg(inst, 0, CM_SMI_CTL);
--	while (read_smi_cm_reg(inst, CM_SMI_CTL) & CM_SMI_CTL_BUSY)
--		;
--
--	write_smi_cm_reg(inst, (inst->clock_divisor << CM_SMI_DIV_DIVI_OFFS),
--	       CM_SMI_DIV);
--	write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS),
--	       CM_SMI_CTL);
--
--	/* Enable the clock */
--	write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS) |
--	       CM_SMI_CTL_ENAB, CM_SMI_CTL);
--}
--
--/****************************************************************************
--*
- *   SMI peripheral setup
- *
- ***************************************************************************/
-@@ -894,42 +858,40 @@ static int bcm2835_smi_probe(struct plat
- 	struct device_node *node = dev->of_node;
- 	struct resource *ioresource;
- 	struct bcm2835_smi_instance *inst;
-+	const __be32 *addr;
- 
-+	/* We require device tree support */
-+	if (!node)
-+		return -EINVAL;
- 	/* Allocate buffers and instance data */
--
- 	inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance),
- 		GFP_KERNEL);
--
- 	if (!inst)
- 		return -ENOMEM;
- 
- 	inst->dev = dev;
- 	spin_lock_init(&inst->transaction_lock);
- 
--	/* We require device tree support */
--	if (!node)
--		return -EINVAL;
--
- 	ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
--	ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
--	inst->cm_smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
--	inst->smi_regs_busaddr = be32_to_cpu(
--		*of_get_address(node, 0, NULL, NULL));
--	of_property_read_u32(node,
--			     "brcm,smi-clock-source",
--			     &inst->clock_source);
--	of_property_read_u32(node,
--			     "brcm,smi-clock-divisor",
--			     &inst->clock_divisor);
-+	if (IS_ERR(inst->smi_regs_ptr)) {
-+		err = PTR_ERR(inst->smi_regs_ptr);
-+		goto err;
-+	}
-+	addr = of_get_address(node, 0, NULL, NULL);
-+	inst->smi_regs_busaddr = be32_to_cpu(addr);
- 
- 	err = bcm2835_smi_dma_setup(inst);
- 	if (err)
--		return err;
-+		goto err;
- 
--	/* Finally, do peripheral setup */
-+	/* request clock */
-+	inst->clk = devm_clk_get(dev, NULL);
-+	if (!inst->clk)
-+		goto err;
-+	clk_prepare_enable(inst->clk);
- 
--	smi_setup_clock(inst);
-+	/* Finally, do peripheral setup */
- 	smi_setup_regs(inst);
- 
- 	platform_set_drvdata(pdev, inst);
-@@ -937,6 +899,9 @@ static int bcm2835_smi_probe(struct plat
- 	dev_info(inst->dev, "initialised");
- 
- 	return 0;
-+err:
-+	kfree(inst);
-+	return err;
- }
- 
- /****************************************************************************
-@@ -950,6 +915,11 @@ static int bcm2835_smi_remove(struct pla
- 	struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev);
- 	struct device *dev = inst->dev;
- 
-+	dmaengine_terminate_all(inst->dma_chan);
-+	dma_release_channel(inst->dma_chan);
-+
-+	clk_disable_unprepare(inst->clk);
-+
- 	dev_info(dev, "SMI device removed - OK");
- 	return 0;
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0047-Add-SMI-NAND-driver.patch b/target/linux/brcm2708/patches-4.14/950-0047-Add-SMI-NAND-driver.patch
deleted file mode 100644
index 847a73ad3..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0047-Add-SMI-NAND-driver.patch
+++ /dev/null
@@ -1,357 +0,0 @@
-From 8582c304a9c1c56fddef2a742324c796be4a748b Mon Sep 17 00:00:00 2001
-From: Luke Wren <wren6991@gmail.com>
-Date: Sat, 5 Sep 2015 01:16:10 +0100
-Subject: [PATCH 047/454] Add SMI NAND driver
-
-Signed-off-by: Luke Wren <wren6991@gmail.com>
----
- .../bindings/mtd/brcm,bcm2835-smi-nand.txt    |  42 +++
- drivers/mtd/nand/Kconfig                      |   7 +
- drivers/mtd/nand/Makefile                     |   1 +
- drivers/mtd/nand/bcm2835_smi_nand.c           | 267 ++++++++++++++++++
- 4 files changed, 317 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt
- create mode 100644 drivers/mtd/nand/bcm2835_smi_nand.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt
-@@ -0,0 +1,42 @@
-+* BCM2835 SMI NAND flash
-+
-+This driver is a shim between the BCM2835 SMI driver (SMI is a peripheral for
-+talking to parallel register interfaces) and Linux's MTD layer.
-+
-+Required properties:
-+- compatible: "brcm,bcm2835-smi-nand"
-+- status: "okay"
-+
-+Optional properties:
-+- partition@n, where n is an integer from a consecutive sequence starting at 0
-+	- Difficult to store partition table on NAND device - normally put it
-+	in the source code, kernel bootparams, or device tree (the best way!)
-+	- Sub-properties:
-+		- label: the partition name, as shown by mtdinfo /dev/mtd*
-+		- reg: the size and offset of this partition.
-+		- (optional) read-only: an empty property flagging as read only
-+
-+Example:
-+
-+nand: flash@0 {
-+	compatible = "brcm,bcm2835-smi-nand";
-+	status = "okay";
-+
-+	partition@0 {
-+		label = "stage2";
-+		// 128k
-+		reg = <0 0x20000>;
-+		read-only;
-+	};
-+	partition@1 {
-+		label = "firmware";
-+		// 16M
-+		reg = <0x20000 0x1000000>;
-+		read-only;
-+	};
-+	partition@2 {
-+		label = "root";
-+		// 2G
-+		reg = <0x1020000 0x80000000>;
-+	};
-+};
-\ No newline at end of file
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -40,6 +40,13 @@ config MTD_SM_COMMON
- 	tristate
- 	default n
- 
-+config MTD_NAND_BCM2835_SMI
-+        tristate "Use Broadcom's Secondary Memory Interface as a NAND controller (BCM283x)"
-+        depends on BCM2835_SMI
-+        default m
-+        help
-+	  Uses the BCM2835's SMI peripheral as a NAND controller.
-+
- config MTD_NAND_DENALI
- 	tristate
- 
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_NAND_DENALI)		+= denali
- obj-$(CONFIG_MTD_NAND_DENALI_PCI)	+= denali_pci.o
- obj-$(CONFIG_MTD_NAND_DENALI_DT)	+= denali_dt.o
- obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o
-+obj-$(CONFIG_MTD_NAND_BCM2835_SMI)	+= bcm2835_smi_nand.o
- obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
- obj-$(CONFIG_MTD_NAND_S3C2410)		+= s3c2410.o
- obj-$(CONFIG_MTD_NAND_TANGO)		+= tango_nand.o
---- /dev/null
-+++ b/drivers/mtd/nand/bcm2835_smi_nand.c
-@@ -0,0 +1,267 @@
-+/**
-+ * NAND flash driver for Broadcom Secondary Memory Interface
-+ *
-+ * Written by Luke Wren <luke@raspberrypi.org>
-+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/mtd/rawnand.h>
-+#include <linux/mtd/partitions.h>
-+
-+#include <linux/broadcom/bcm2835_smi.h>
-+
-+#define DEVICE_NAME "bcm2835-smi-nand"
-+#define DRIVER_NAME "smi-nand-bcm2835"
-+
-+struct bcm2835_smi_nand_host {
-+	struct bcm2835_smi_instance *smi_inst;
-+	struct nand_chip nand_chip;
-+	struct mtd_info mtd;
-+	struct device *dev;
-+};
-+
-+/****************************************************************************
-+*
-+*   NAND functionality implementation
-+*
-+****************************************************************************/
-+
-+#define SMI_NAND_CLE_PIN 0x01
-+#define SMI_NAND_ALE_PIN 0x02
-+
-+static inline void bcm2835_smi_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
-+					     unsigned int ctrl)
-+{
-+	uint32_t cmd32 = cmd;
-+	uint32_t addr = ~(SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN);
-+	struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
-+	struct bcm2835_smi_instance *inst = host->smi_inst;
-+
-+	if (ctrl & NAND_CLE)
-+		addr |= SMI_NAND_CLE_PIN;
-+	if (ctrl & NAND_ALE)
-+		addr |= SMI_NAND_ALE_PIN;
-+	/* Lower ALL the CS pins! */
-+	if (ctrl & NAND_NCE)
-+		addr &= (SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN);
-+
-+	bcm2835_smi_set_address(inst, addr);
-+
-+	if (cmd != NAND_CMD_NONE)
-+		bcm2835_smi_write_buf(inst, &cmd32, 1);
-+}
-+
-+static inline uint8_t bcm2835_smi_nand_read_byte(struct mtd_info *mtd)
-+{
-+	uint8_t byte;
-+	struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
-+	struct bcm2835_smi_instance *inst = host->smi_inst;
-+
-+	bcm2835_smi_read_buf(inst, &byte, 1);
-+	return byte;
-+}
-+
-+static inline void bcm2835_smi_nand_write_byte(struct mtd_info *mtd,
-+					       uint8_t byte)
-+{
-+	struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
-+	struct bcm2835_smi_instance *inst = host->smi_inst;
-+
-+	bcm2835_smi_write_buf(inst, &byte, 1);
-+}
-+
-+static inline void bcm2835_smi_nand_write_buf(struct mtd_info *mtd,
-+					      const uint8_t *buf, int len)
-+{
-+	struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
-+	struct bcm2835_smi_instance *inst = host->smi_inst;
-+
-+	bcm2835_smi_write_buf(inst, buf, len);
-+}
-+
-+static inline void bcm2835_smi_nand_read_buf(struct mtd_info *mtd,
-+					     uint8_t *buf, int len)
-+{
-+	struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
-+	struct bcm2835_smi_instance *inst = host->smi_inst;
-+
-+	bcm2835_smi_read_buf(inst, buf, len);
-+}
-+
-+/****************************************************************************
-+*
-+*   Probe and remove functions
-+*
-+***************************************************************************/
-+
-+static int bcm2835_smi_nand_probe(struct platform_device *pdev)
-+{
-+	struct bcm2835_smi_nand_host *host;
-+	struct nand_chip *this;
-+	struct mtd_info *mtd;
-+	struct device *dev = &pdev->dev;
-+	struct device_node *node = dev->of_node, *smi_node;
-+	struct mtd_part_parser_data ppdata;
-+	struct smi_settings *smi_settings;
-+	struct bcm2835_smi_instance *smi_inst;
-+	int ret = -ENXIO;
-+
-+	if (!node) {
-+		dev_err(dev, "No device tree node supplied!");
-+		return -EINVAL;
-+	}
-+
-+	smi_node = of_parse_phandle(node, "smi_handle", 0);
-+
-+	/* Request use of SMI peripheral: */
-+	smi_inst = bcm2835_smi_get(smi_node);
-+
-+	if (!smi_inst) {
-+		dev_err(dev, "Could not register with SMI.");
-+		return -EPROBE_DEFER;
-+	}
-+
-+	/* Set SMI timing and bus width */
-+
-+	smi_settings = bcm2835_smi_get_settings_from_regs(smi_inst);
-+
-+	smi_settings->data_width = SMI_WIDTH_8BIT;
-+	smi_settings->read_setup_time = 2;
-+	smi_settings->read_hold_time = 1;
-+	smi_settings->read_pace_time = 1;
-+	smi_settings->read_strobe_time = 3;
-+
-+	smi_settings->write_setup_time = 2;
-+	smi_settings->write_hold_time = 1;
-+	smi_settings->write_pace_time = 1;
-+	smi_settings->write_strobe_time = 3;
-+
-+	bcm2835_smi_set_regs_from_settings(smi_inst);
-+
-+	host = devm_kzalloc(dev, sizeof(struct bcm2835_smi_nand_host),
-+		GFP_KERNEL);
-+	if (!host)
-+		return -ENOMEM;
-+
-+	host->dev = dev;
-+	host->smi_inst = smi_inst;
-+
-+	platform_set_drvdata(pdev, host);
-+
-+	/* Link the structures together */
-+
-+	this = &host->nand_chip;
-+	mtd = &host->mtd;
-+	mtd->priv = this;
-+	mtd->owner = THIS_MODULE;
-+	mtd->dev.parent = dev;
-+	mtd->name = DRIVER_NAME;
-+
-+	/* 20 us command delay time... */
-+	this->chip_delay = 20;
-+
-+	this->priv = host;
-+	this->cmd_ctrl = bcm2835_smi_nand_cmd_ctrl;
-+	this->read_byte = bcm2835_smi_nand_read_byte;
-+	this->write_byte = bcm2835_smi_nand_write_byte;
-+	this->write_buf = bcm2835_smi_nand_write_buf;
-+	this->read_buf = bcm2835_smi_nand_read_buf;
-+
-+	this->ecc.mode = NAND_ECC_SOFT;
-+
-+	/* Should never be accessed directly: */
-+
-+	this->IO_ADDR_R = (void *)0xdeadbeef;
-+	this->IO_ADDR_W = (void *)0xdeadbeef;
-+
-+	/* First scan to find the device and get the page size */
-+
-+	if (nand_scan_ident(mtd, 1, NULL))
-+		return -ENXIO;
-+
-+	/* Second phase scan */
-+
-+	if (nand_scan_tail(mtd))
-+		return -ENXIO;
-+
-+	ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
-+	if (!ret)
-+		return 0;
-+
-+	nand_release(mtd);
-+	return -EINVAL;
-+}
-+
-+static int bcm2835_smi_nand_remove(struct platform_device *pdev)
-+{
-+	struct bcm2835_smi_nand_host *host = platform_get_drvdata(pdev);
-+
-+	nand_release(&host->mtd);
-+
-+	return 0;
-+}
-+
-+/****************************************************************************
-+*
-+*   Register the driver with device tree
-+*
-+***************************************************************************/
-+
-+static const struct of_device_id bcm2835_smi_nand_of_match[] = {
-+	{.compatible = "brcm,bcm2835-smi-nand",},
-+	{ /* sentinel */ }
-+};
-+
-+MODULE_DEVICE_TABLE(of, bcm2835_smi_nand_of_match);
-+
-+static struct platform_driver bcm2835_smi_nand_driver = {
-+	.probe = bcm2835_smi_nand_probe,
-+	.remove = bcm2835_smi_nand_remove,
-+	.driver = {
-+		.name = DRIVER_NAME,
-+		.owner = THIS_MODULE,
-+		.of_match_table = bcm2835_smi_nand_of_match,
-+	},
-+};
-+
-+module_platform_driver(bcm2835_smi_nand_driver);
-+
-+MODULE_ALIAS("platform:smi-nand-bcm2835");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION
-+	("Driver for NAND chips using Broadcom Secondary Memory Interface");
-+MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
diff --git a/target/linux/brcm2708/patches-4.14/950-0048-lirc-added-support-for-RaspberryPi-GPIO.patch b/target/linux/brcm2708/patches-4.14/950-0048-lirc-added-support-for-RaspberryPi-GPIO.patch
deleted file mode 100644
index 2e48035c6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0048-lirc-added-support-for-RaspberryPi-GPIO.patch
+++ /dev/null
@@ -1,852 +0,0 @@
-From ecc83f926bd3cf3c9e62389494f39a0939949ef3 Mon Sep 17 00:00:00 2001
-From: Aron Szabo <aron@aron.ws>
-Date: Sat, 16 Jun 2012 12:15:55 +0200
-Subject: [PATCH 048/454] lirc: added support for RaspberryPi GPIO
-
-lirc_rpi: Use read_current_timer to determine transmitter delay. Thanks to jjmz and others
-See: https://github.com/raspberrypi/linux/issues/525
-
-lirc: Remove restriction on gpio pins that can be used with lirc
-
-Compute Module, for example could use different pins
-
-lirc_rpi: Add parameter to specify input pin pull
-
-Depending on the connected IR circuitry it might be desirable to change the
-gpios internal pull from it pull-down default behaviour. Add a module
-parameter to allow the user to set it explicitly.
-
-Signed-off-by: Julian Scheel <julian@jusst.de>
-
-lirc-rpi: Use the higher-level irq control functions
-
-This module used to access the irq_chip methods of the
-gpio controller directly, rather than going through the
-standard enable_irq/irq_set_irq_type functions. This
-caused problems on pinctrl-bcm2835 which only implements
-the irq_enable/disable methods and not irq_unmask/mask.
-
-lirc-rpi: Correct the interrupt usage
-
-1) Correct the use of enable_irq (i.e. don't call it so often)
-2) Correct the shutdown sequence.
-3) Avoid a bcm2708_gpio driver quirk by setting the irq flags earlier
-
-lirc-rpi: use getnstimeofday instead of read_current_timer
-
-read_current_timer isn't guaranteed to return values in
-microseconds, and indeed it doesn't on a Pi2.
-
-Issue: linux#827
-
-lirc-rpi: Add device tree support, and a suitable overlay
-
-The overlay supports DT parameters that match the old module
-parameters, except that gpio_in_pull should be set using the
-strings "up", "down" or "off".
-
-lirc-rpi: Also support pinctrl-bcm2835 in non-DT mode
-
-fix auto-sense in lirc_rpi driver
-
-On a Raspberry Pi 2, the lirc_rpi driver might receive spurious
-interrupts and change it's low-active / high-active setting.
-When this happens, the IR remote control stops working.
-
-This patch disables this auto-detection if the 'sense' parameter
-was set in the device tree, making the driver robust to such
-spurious interrupts.
----
- drivers/staging/media/lirc/Kconfig    |   6 +
- drivers/staging/media/lirc/Makefile   |   1 +
- drivers/staging/media/lirc/lirc_rpi.c | 733 ++++++++++++++++++++++++++
- include/linux/platform_data/bcm2708.h |  23 +
- 4 files changed, 763 insertions(+)
- create mode 100644 drivers/staging/media/lirc/lirc_rpi.c
- create mode 100644 include/linux/platform_data/bcm2708.h
-
---- a/drivers/staging/media/lirc/Kconfig
-+++ b/drivers/staging/media/lirc/Kconfig
-@@ -12,6 +12,12 @@ menuconfig LIRC_STAGING
- 
- if LIRC_STAGING
- 
-+config LIRC_RPI
-+	tristate "Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi"
-+	depends on LIRC
-+	help
-+	  Driver for Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi
-+
- config LIRC_ZILOG
- 	tristate "Zilog/Hauppauge IR Transmitter"
- 	depends on LIRC && I2C
---- a/drivers/staging/media/lirc/Makefile
-+++ b/drivers/staging/media/lirc/Makefile
-@@ -3,4 +3,5 @@
- 
- # Each configuration option enables a list of files.
- 
-+obj-$(CONFIG_LIRC_RPI)		+= lirc_rpi.o
- obj-$(CONFIG_LIRC_ZILOG)	+= lirc_zilog.o
---- /dev/null
-+++ b/drivers/staging/media/lirc/lirc_rpi.c
-@@ -0,0 +1,733 @@
-+/*
-+ * lirc_rpi.c
-+ *
-+ * lirc_rpi - Device driver that records pulse- and pause-lengths
-+ *	      (space-lengths) (just like the lirc_serial driver does)
-+ *	      between GPIO interrupt events on the Raspberry Pi.
-+ *	      Lots of code has been taken from the lirc_serial module,
-+ *	      so I would like say thanks to the authors.
-+ *
-+ * Copyright (C) 2012 Aron Robert Szabo <aron@reon.hu>,
-+ *		      Michael Bishop <cleverca22@gmail.com>
-+ *  This program is free software; you can redistribute it and/or modify
-+ *  it under the terms of the GNU General Public License as published by
-+ *  the Free Software Foundation; either version 2 of the License, or
-+ *  (at your option) any later version.
-+ *
-+ *  This program is distributed in the hope that it will be useful,
-+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *  GNU General Public License for more details.
-+ *
-+ *  You should have received a copy of the GNU General Public License
-+ *  along with this program; if not, write to the Free Software
-+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/sched.h>
-+#include <linux/kernel.h>
-+#include <linux/time.h>
-+#include <linux/timex.h>
-+#include <linux/timekeeping.h>
-+#include <linux/string.h>
-+#include <linux/delay.h>
-+#include <linux/platform_device.h>
-+#include <linux/irq.h>
-+#include <linux/spinlock.h>
-+#include <media/lirc.h>
-+#include <media/lirc_dev.h>
-+#include <linux/gpio.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_data/bcm2708.h>
-+
-+#define LIRC_DRIVER_NAME "lirc_rpi"
-+#define RBUF_LEN 256
-+#define LIRC_TRANSMITTER_LATENCY 50
-+
-+#ifndef MAX_UDELAY_MS
-+#define MAX_UDELAY_US 5000
-+#else
-+#define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
-+#endif
-+
-+#define dprintk(fmt, args...)					\
-+	do {							\
-+		if (debug)					\
-+			printk(KERN_DEBUG LIRC_DRIVER_NAME ": "	\
-+			       fmt, ## args);			\
-+	} while (0)
-+
-+/* module parameters */
-+
-+/* set the default GPIO input pin */
-+static int gpio_in_pin = 18;
-+/* set the default pull behaviour for input pin */
-+static int gpio_in_pull = BCM2708_PULL_DOWN;
-+/* set the default GPIO output pin */
-+static int gpio_out_pin = 17;
-+/* enable debugging messages */
-+static bool debug;
-+/* -1 = auto, 0 = active high, 1 = active low */
-+static int sense = -1;
-+/* use softcarrier by default */
-+static bool softcarrier = 1;
-+/* 0 = do not invert output, 1 = invert output */
-+static bool invert = 0;
-+
-+struct gpio_chip *gpiochip;
-+static int irq_num;
-+static int auto_sense = 1;
-+
-+/* forward declarations */
-+static long send_pulse(unsigned long length);
-+static void send_space(long length);
-+static void lirc_rpi_exit(void);
-+
-+static struct platform_device *lirc_rpi_dev;
-+static struct timeval lasttv = { 0, 0 };
-+static struct lirc_buffer rbuf;
-+static spinlock_t lock;
-+
-+/* initialized/set in init_timing_params() */
-+static unsigned int freq = 38000;
-+static unsigned int duty_cycle = 50;
-+static unsigned long period;
-+static unsigned long pulse_width;
-+static unsigned long space_width;
-+
-+static void safe_udelay(unsigned long usecs)
-+{
-+	while (usecs > MAX_UDELAY_US) {
-+		udelay(MAX_UDELAY_US);
-+		usecs -= MAX_UDELAY_US;
-+	}
-+	udelay(usecs);
-+}
-+
-+static unsigned long read_current_us(void)
-+{
-+	struct timespec now;
-+	getnstimeofday(&now);
-+	return (now.tv_sec * 1000000) + (now.tv_nsec/1000);
-+}
-+
-+static int init_timing_params(unsigned int new_duty_cycle,
-+	unsigned int new_freq)
-+{
-+	if (1000 * 1000000L / new_freq * new_duty_cycle / 100 <=
-+	    LIRC_TRANSMITTER_LATENCY)
-+		return -EINVAL;
-+	if (1000 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <=
-+	    LIRC_TRANSMITTER_LATENCY)
-+		return -EINVAL;
-+	duty_cycle = new_duty_cycle;
-+	freq = new_freq;
-+	period = 1000 * 1000000L / freq;
-+	pulse_width = period * duty_cycle / 100;
-+	space_width = period - pulse_width;
-+	dprintk("in init_timing_params, freq=%d pulse=%ld, "
-+		"space=%ld\n", freq, pulse_width, space_width);
-+	return 0;
-+}
-+
-+static long send_pulse_softcarrier(unsigned long length)
-+{
-+	int flag;
-+	unsigned long actual, target;
-+	unsigned long actual_us, initial_us, target_us;
-+
-+	length *= 1000;
-+
-+	actual = 0; target = 0; flag = 0;
-+	actual_us = read_current_us();
-+
-+	while (actual < length) {
-+		if (flag) {
-+			gpiochip->set(gpiochip, gpio_out_pin, invert);
-+			target += space_width;
-+		} else {
-+			gpiochip->set(gpiochip, gpio_out_pin, !invert);
-+			target += pulse_width;
-+		}
-+		initial_us = actual_us;
-+		target_us = actual_us + (target - actual) / 1000;
-+		/*
-+		 * Note - we've checked in ioctl that the pulse/space
-+		 * widths are big enough so that d is > 0
-+		 */
-+		if  ((int)(target_us - actual_us) > 0)
-+			udelay(target_us - actual_us);
-+		actual_us = read_current_us();
-+		actual += (actual_us - initial_us) * 1000;
-+		flag = !flag;
-+	}
-+	return (actual-length) / 1000;
-+}
-+
-+static long send_pulse(unsigned long length)
-+{
-+	if (length <= 0)
-+		return 0;
-+
-+	if (softcarrier) {
-+		return send_pulse_softcarrier(length);
-+	} else {
-+		gpiochip->set(gpiochip, gpio_out_pin, !invert);
-+		safe_udelay(length);
-+		return 0;
-+	}
-+}
-+
-+static void send_space(long length)
-+{
-+	gpiochip->set(gpiochip, gpio_out_pin, invert);
-+	if (length <= 0)
-+		return;
-+	safe_udelay(length);
-+}
-+
-+static void rbwrite(int l)
-+{
-+	if (lirc_buffer_full(&rbuf)) {
-+		/* no new signals will be accepted */
-+		dprintk("Buffer overrun\n");
-+		return;
-+	}
-+	lirc_buffer_write(&rbuf, (void *)&l);
-+}
-+
-+static void frbwrite(int l)
-+{
-+	/* simple noise filter */
-+	static int pulse, space;
-+	static unsigned int ptr;
-+
-+	if (ptr > 0 && (l & PULSE_BIT)) {
-+		pulse += l & PULSE_MASK;
-+		if (pulse > 250) {
-+			rbwrite(space);
-+			rbwrite(pulse | PULSE_BIT);
-+			ptr = 0;
-+			pulse = 0;
-+		}
-+		return;
-+	}
-+	if (!(l & PULSE_BIT)) {
-+		if (ptr == 0) {
-+			if (l > 20000) {
-+				space = l;
-+				ptr++;
-+				return;
-+			}
-+		} else {
-+			if (l > 20000) {
-+				space += pulse;
-+				if (space > PULSE_MASK)
-+					space = PULSE_MASK;
-+				space += l;
-+				if (space > PULSE_MASK)
-+					space = PULSE_MASK;
-+				pulse = 0;
-+				return;
-+			}
-+			rbwrite(space);
-+			rbwrite(pulse | PULSE_BIT);
-+			ptr = 0;
-+			pulse = 0;
-+		}
-+	}
-+	rbwrite(l);
-+}
-+
-+static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs)
-+{
-+	struct timeval tv;
-+	long deltv;
-+	int data;
-+	int signal;
-+
-+	/* use the GPIO signal level */
-+	signal = gpiochip->get(gpiochip, gpio_in_pin);
-+
-+	if (sense != -1) {
-+		/* get current time */
-+		do_gettimeofday(&tv);
-+
-+		/* calc time since last interrupt in microseconds */
-+		deltv = tv.tv_sec-lasttv.tv_sec;
-+		if (tv.tv_sec < lasttv.tv_sec ||
-+		    (tv.tv_sec == lasttv.tv_sec &&
-+		     tv.tv_usec < lasttv.tv_usec)) {
-+			printk(KERN_WARNING LIRC_DRIVER_NAME
-+			       ": AIEEEE: your clock just jumped backwards\n");
-+			printk(KERN_WARNING LIRC_DRIVER_NAME
-+			       ": %d %d %lx %lx %lx %lx\n", signal, sense,
-+			       tv.tv_sec, lasttv.tv_sec,
-+			       tv.tv_usec, lasttv.tv_usec);
-+			data = PULSE_MASK;
-+		} else if (deltv > 15) {
-+			data = PULSE_MASK; /* really long time */
-+			if (!(signal^sense)) {
-+				/* sanity check */
-+				printk(KERN_DEBUG LIRC_DRIVER_NAME
-+				       ": AIEEEE: %d %d %lx %lx %lx %lx\n",
-+				       signal, sense, tv.tv_sec, lasttv.tv_sec,
-+				       tv.tv_usec, lasttv.tv_usec);
-+				/*
-+				 * detecting pulse while this
-+				 * MUST be a space!
-+				 */
-+				if (auto_sense) {
-+					sense = sense ? 0 : 1;
-+				}
-+			}
-+		} else {
-+			data = (int) (deltv*1000000 +
-+				      (tv.tv_usec - lasttv.tv_usec));
-+		}
-+		frbwrite(signal^sense ? data : (data|PULSE_BIT));
-+		lasttv = tv;
-+		wake_up_interruptible(&rbuf.wait_poll);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int is_right_chip(struct gpio_chip *chip, void *data)
-+{
-+	dprintk("is_right_chip %s %d\n", chip->label, strcmp(data, chip->label));
-+
-+	if (strcmp(data, chip->label) == 0)
-+		return 1;
-+	return 0;
-+}
-+
-+static inline int read_bool_property(const struct device_node *np,
-+				     const char *propname,
-+				     bool *out_value)
-+{
-+	u32 value = 0;
-+	int err = of_property_read_u32(np, propname, &value);
-+	if (err == 0)
-+		*out_value = (value != 0);
-+	return err;
-+}
-+
-+static void read_pin_settings(struct device_node *node)
-+{
-+	u32 pin;
-+	int index;
-+
-+	for (index = 0;
-+	     of_property_read_u32_index(
-+		     node,
-+		     "brcm,pins",
-+		     index,
-+		     &pin) == 0;
-+	     index++) {
-+		u32 function;
-+		int err;
-+		err = of_property_read_u32_index(
-+			node,
-+			"brcm,function",
-+			index,
-+			&function);
-+		if (err == 0) {
-+			if (function == 1) /* Output */
-+				gpio_out_pin = pin;
-+			else if (function == 0) /* Input */
-+				gpio_in_pin = pin;
-+		}
-+	}
-+}
-+
-+static int init_port(void)
-+{
-+	int i, nlow, nhigh;
-+	struct device_node *node;
-+
-+	node = lirc_rpi_dev->dev.of_node;
-+
-+	gpiochip = gpiochip_find("bcm2708_gpio", is_right_chip);
-+
-+	/*
-+	 * Because of the lack of a setpull function, only support
-+	 * pinctrl-bcm2835 if using device tree.
-+	*/
-+	if (!gpiochip && node)
-+		gpiochip = gpiochip_find("pinctrl-bcm2835", is_right_chip);
-+
-+	if (!gpiochip) {
-+		pr_err(LIRC_DRIVER_NAME ": gpio chip not found!\n");
-+		return -ENODEV;
-+	}
-+
-+	if (node) {
-+		struct device_node *pins_node;
-+
-+		pins_node = of_parse_phandle(node, "pinctrl-0", 0);
-+		if (!pins_node) {
-+			printk(KERN_ERR LIRC_DRIVER_NAME
-+			       ": pinctrl settings not found!\n");
-+			return -EINVAL;
-+		}
-+
-+		read_pin_settings(pins_node);
-+
-+		of_property_read_u32(node, "rpi,sense", &sense);
-+
-+		read_bool_property(node, "rpi,softcarrier", &softcarrier);
-+
-+		read_bool_property(node, "rpi,invert", &invert);
-+
-+		read_bool_property(node, "rpi,debug", &debug);
-+
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	gpiochip->set(gpiochip, gpio_out_pin, invert);
-+
-+	irq_num = gpiochip->to_irq(gpiochip, gpio_in_pin);
-+	dprintk("to_irq %d\n", irq_num);
-+
-+	/* if pin is high, then this must be an active low receiver. */
-+	if (sense == -1) {
-+		/* wait 1/2 sec for the power supply */
-+		msleep(500);
-+
-+		/*
-+		 * probe 9 times every 0.04s, collect "votes" for
-+		 * active high/low
-+		 */
-+		nlow = 0;
-+		nhigh = 0;
-+		for (i = 0; i < 9; i++) {
-+			if (gpiochip->get(gpiochip, gpio_in_pin))
-+				nlow++;
-+			else
-+				nhigh++;
-+			msleep(40);
-+		}
-+		sense = (nlow >= nhigh ? 1 : 0);
-+		printk(KERN_INFO LIRC_DRIVER_NAME
-+		       ": auto-detected active %s receiver on GPIO pin %d\n",
-+		       sense ? "low" : "high", gpio_in_pin);
-+	} else {
-+		printk(KERN_INFO LIRC_DRIVER_NAME
-+		       ": manually using active %s receiver on GPIO pin %d\n",
-+		       sense ? "low" : "high", gpio_in_pin);
-+		auto_sense = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+// called when the character device is opened
-+static int set_use_inc(void *data)
-+{
-+	int result;
-+
-+	/* initialize timestamp */
-+	do_gettimeofday(&lasttv);
-+
-+	result = request_irq(irq_num,
-+			     (irq_handler_t) irq_handler,
-+			     IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING,
-+			     LIRC_DRIVER_NAME, (void*) 0);
-+
-+	switch (result) {
-+	case -EBUSY:
-+		printk(KERN_ERR LIRC_DRIVER_NAME
-+		       ": IRQ %d is busy\n",
-+		       irq_num);
-+		return -EBUSY;
-+	case -EINVAL:
-+		printk(KERN_ERR LIRC_DRIVER_NAME
-+		       ": Bad irq number or handler\n");
-+		return -EINVAL;
-+	default:
-+		dprintk("Interrupt %d obtained\n",
-+			irq_num);
-+		break;
-+	};
-+
-+	/* initialize pulse/space widths */
-+	init_timing_params(duty_cycle, freq);
-+
-+	return 0;
-+}
-+
-+static void set_use_dec(void *data)
-+{
-+	/* GPIO Pin Falling/Rising Edge Detect Disable */
-+	irq_set_irq_type(irq_num, 0);
-+	disable_irq(irq_num);
-+
-+	free_irq(irq_num, (void *) 0);
-+
-+	dprintk(KERN_INFO LIRC_DRIVER_NAME
-+		": freed IRQ %d\n", irq_num);
-+}
-+
-+static ssize_t lirc_write(struct file *file, const char *buf,
-+	size_t n, loff_t *ppos)
-+{
-+	int i, count;
-+	unsigned long flags;
-+	long delta = 0;
-+	int *wbuf;
-+
-+	count = n / sizeof(int);
-+	if (n % sizeof(int) || count % 2 == 0)
-+		return -EINVAL;
-+	wbuf = memdup_user(buf, n);
-+	if (IS_ERR(wbuf))
-+		return PTR_ERR(wbuf);
-+	spin_lock_irqsave(&lock, flags);
-+
-+	for (i = 0; i < count; i++) {
-+		if (i%2)
-+			send_space(wbuf[i] - delta);
-+		else
-+			delta = send_pulse(wbuf[i]);
-+	}
-+	gpiochip->set(gpiochip, gpio_out_pin, invert);
-+
-+	spin_unlock_irqrestore(&lock, flags);
-+	kfree(wbuf);
-+	return n;
-+}
-+
-+static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
-+{
-+	int result;
-+	__u32 value;
-+
-+	switch (cmd) {
-+	case LIRC_GET_SEND_MODE:
-+		return -ENOIOCTLCMD;
-+		break;
-+
-+	case LIRC_SET_SEND_MODE:
-+		result = get_user(value, (__u32 *) arg);
-+		if (result)
-+			return result;
-+		/* only LIRC_MODE_PULSE supported */
-+		if (value != LIRC_MODE_PULSE)
-+			return -ENOSYS;
-+		break;
-+
-+	case LIRC_GET_LENGTH:
-+		return -ENOSYS;
-+		break;
-+
-+	case LIRC_SET_SEND_DUTY_CYCLE:
-+		dprintk("SET_SEND_DUTY_CYCLE\n");
-+		result = get_user(value, (__u32 *) arg);
-+		if (result)
-+			return result;
-+		if (value <= 0 || value > 100)
-+			return -EINVAL;
-+		return init_timing_params(value, freq);
-+		break;
-+
-+	case LIRC_SET_SEND_CARRIER:
-+		dprintk("SET_SEND_CARRIER\n");
-+		result = get_user(value, (__u32 *) arg);
-+		if (result)
-+			return result;
-+		if (value > 500000 || value < 20000)
-+			return -EINVAL;
-+		return init_timing_params(duty_cycle, value);
-+		break;
-+
-+	default:
-+		return lirc_dev_fop_ioctl(filep, cmd, arg);
-+	}
-+	return 0;
-+}
-+
-+static const struct file_operations lirc_fops = {
-+	.owner		= THIS_MODULE,
-+	.write		= lirc_write,
-+	.unlocked_ioctl	= lirc_ioctl,
-+	.read		= lirc_dev_fop_read,
-+	.poll		= lirc_dev_fop_poll,
-+	.open		= lirc_dev_fop_open,
-+	.release	= lirc_dev_fop_close,
-+	.llseek		= no_llseek,
-+};
-+
-+static struct lirc_driver driver = {
-+	.name		= LIRC_DRIVER_NAME,
-+	.minor		= -1,
-+	.code_length	= 1,
-+	.data		= NULL,
-+	.rbuf		= &rbuf,
-+	.fops		= &lirc_fops,
-+	.dev		= NULL,
-+	.owner		= THIS_MODULE,
-+};
-+
-+static const struct of_device_id lirc_rpi_of_match[] = {
-+	{ .compatible = "rpi,lirc-rpi", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, lirc_rpi_of_match);
-+
-+static struct platform_driver lirc_rpi_driver = {
-+	.driver = {
-+		.name   = LIRC_DRIVER_NAME,
-+		.owner  = THIS_MODULE,
-+		.of_match_table = of_match_ptr(lirc_rpi_of_match),
-+	},
-+};
-+
-+static int __init lirc_rpi_init(void)
-+{
-+	struct device_node *node;
-+	int result;
-+
-+	/* Init read buffer. */
-+	result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN);
-+	if (result < 0)
-+		return -ENOMEM;
-+
-+	result = platform_driver_register(&lirc_rpi_driver);
-+	if (result) {
-+		printk(KERN_ERR LIRC_DRIVER_NAME
-+		       ": lirc register returned %d\n", result);
-+		goto exit_buffer_free;
-+	}
-+
-+	node = of_find_compatible_node(NULL, NULL,
-+				       lirc_rpi_of_match[0].compatible);
-+
-+	if (node) {
-+		/* DT-enabled */
-+		lirc_rpi_dev = of_find_device_by_node(node);
-+		WARN_ON(lirc_rpi_dev->dev.of_node != node);
-+		of_node_put(node);
-+	}
-+	else {
-+		lirc_rpi_dev = platform_device_alloc(LIRC_DRIVER_NAME, 0);
-+		if (!lirc_rpi_dev) {
-+			result = -ENOMEM;
-+			goto exit_driver_unregister;
-+		}
-+
-+		result = platform_device_add(lirc_rpi_dev);
-+		if (result)
-+			goto exit_device_put;
-+	}
-+
-+	return 0;
-+
-+	exit_device_put:
-+	platform_device_put(lirc_rpi_dev);
-+
-+	exit_driver_unregister:
-+	platform_driver_unregister(&lirc_rpi_driver);
-+
-+	exit_buffer_free:
-+	lirc_buffer_free(&rbuf);
-+
-+	return result;
-+}
-+
-+static void lirc_rpi_exit(void)
-+{
-+	set_use_dec(NULL);
-+	if (!lirc_rpi_dev->dev.of_node)
-+		platform_device_unregister(lirc_rpi_dev);
-+	platform_driver_unregister(&lirc_rpi_driver);
-+	lirc_buffer_free(&rbuf);
-+}
-+
-+static int __init lirc_rpi_init_module(void)
-+{
-+	int result;
-+
-+	result = lirc_rpi_init();
-+	if (result)
-+		return result;
-+
-+	result = init_port();
-+	if (result < 0)
-+		goto exit_rpi;
-+
-+	driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE |
-+			  LIRC_CAN_SET_SEND_CARRIER |
-+			  LIRC_CAN_SEND_PULSE |
-+			  LIRC_CAN_REC_MODE2;
-+
-+	driver.dev = &lirc_rpi_dev->dev;
-+	driver.minor = lirc_register_driver(&driver);
-+
-+	if (driver.minor < 0) {
-+		printk(KERN_ERR LIRC_DRIVER_NAME
-+		       ": device registration failed with %d\n", result);
-+		result = -EIO;
-+		goto exit_rpi;
-+	}
-+
-+	printk(KERN_INFO LIRC_DRIVER_NAME ": driver registered!\n");
-+
-+	set_use_inc(NULL);
-+
-+	return 0;
-+
-+	exit_rpi:
-+	lirc_rpi_exit();
-+
-+	return result;
-+}
-+
-+static void __exit lirc_rpi_exit_module(void)
-+{
-+	lirc_unregister_driver(driver.minor);
-+
-+	gpio_free(gpio_out_pin);
-+	gpio_free(gpio_in_pin);
-+
-+	lirc_rpi_exit();
-+
-+	printk(KERN_INFO LIRC_DRIVER_NAME ": cleaned up module\n");
-+}
-+
-+module_init(lirc_rpi_init_module);
-+module_exit(lirc_rpi_exit_module);
-+
-+MODULE_DESCRIPTION("Infra-red receiver and blaster driver for Raspberry Pi GPIO.");
-+MODULE_AUTHOR("Aron Robert Szabo <aron@reon.hu>");
-+MODULE_AUTHOR("Michael Bishop <cleverca22@gmail.com>");
-+MODULE_LICENSE("GPL");
-+
-+module_param(gpio_out_pin, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM"
-+		 " processor. (default 17");
-+
-+module_param(gpio_in_pin, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor."
-+		 " (default 18");
-+
-+module_param(gpio_in_pull, int, S_IRUGO);
-+MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration."
-+		 " (0 = off, 1 = up, 2 = down, default down)");
-+
-+module_param(sense, int, S_IRUGO);
-+MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit"
-+		 " (0 = active high, 1 = active low )");
-+
-+module_param(softcarrier, bool, S_IRUGO);
-+MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)");
-+
-+module_param(invert, bool, S_IRUGO);
-+MODULE_PARM_DESC(invert, "Invert output (0 = off, 1 = on, default off");
-+
-+module_param(debug, bool, S_IRUGO | S_IWUSR);
-+MODULE_PARM_DESC(debug, "Enable debugging messages");
---- /dev/null
-+++ b/include/linux/platform_data/bcm2708.h
-@@ -0,0 +1,23 @@
-+/*
-+ * include/linux/platform_data/bcm2708.h
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * (C) 2014 Julian Scheel <julian@jusst.de>
-+ *
-+ */
-+#ifndef __BCM2708_H_
-+#define __BCM2708_H_
-+
-+typedef enum {
-+	BCM2708_PULL_OFF,
-+	BCM2708_PULL_UP,
-+	BCM2708_PULL_DOWN
-+} bcm2708_gpio_pull_t;
-+
-+extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
-+		bcm2708_gpio_pull_t value);
-+
-+#endif
diff --git a/target/linux/brcm2708/patches-4.14/950-0049-Add-cpufreq-driver.patch b/target/linux/brcm2708/patches-4.14/950-0049-Add-cpufreq-driver.patch
deleted file mode 100644
index 4886d28ff..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0049-Add-cpufreq-driver.patch
+++ /dev/null
@@ -1,259 +0,0 @@
-From 1466a5baed955602aa2f5283a41b3988794d3caf Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Wed, 3 Jul 2013 00:49:20 +0100
-Subject: [PATCH 049/454] Add cpufreq driver
-
-Signed-off-by: popcornmix <popcornmix@gmail.com>
-
-bcm2835-cpufreq: Change licence to GPLv2
-
-Signed-off-by: Eben Upton <eben.upton@broadcom.com>
-Signed-off-by: Dom Cobley <dom@raspberrypi.com>
----
- drivers/cpufreq/Kconfig.arm       |   9 ++
- drivers/cpufreq/Makefile          |   1 +
- drivers/cpufreq/bcm2835-cpufreq.c | 210 ++++++++++++++++++++++++++++++
- 3 files changed, 220 insertions(+)
- create mode 100644 drivers/cpufreq/bcm2835-cpufreq.c
-
---- a/drivers/cpufreq/Kconfig.arm
-+++ b/drivers/cpufreq/Kconfig.arm
-@@ -237,6 +237,15 @@ config ARM_TANGO_CPUFREQ
- 	depends on CPUFREQ_DT && ARCH_TANGO
- 	default y
- 
-+config ARM_BCM2835_CPUFREQ
-+	depends on RASPBERRYPI_FIRMWARE
-+	bool "BCM2835 Driver"
-+	default y
-+	help
-+	  This adds the CPUFreq driver for BCM2835
-+
-+	  If in doubt, say N.
-+
- config ARM_TEGRA20_CPUFREQ
- 	bool "Tegra20 CPUFreq support"
- 	depends on ARCH_TEGRA
---- a/drivers/cpufreq/Makefile
-+++ b/drivers/cpufreq/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_ARM_SCPI_CPUFREQ)		+= scpi-
- obj-$(CONFIG_ARM_SPEAR_CPUFREQ)		+= spear-cpufreq.o
- obj-$(CONFIG_ARM_STI_CPUFREQ)		+= sti-cpufreq.o
- obj-$(CONFIG_ARM_TANGO_CPUFREQ)		+= tango-cpufreq.o
-+obj-$(CONFIG_ARM_BCM2835_CPUFREQ)	+= bcm2835-cpufreq.o
- obj-$(CONFIG_ARM_TEGRA20_CPUFREQ)	+= tegra20-cpufreq.o
- obj-$(CONFIG_ARM_TEGRA124_CPUFREQ)	+= tegra124-cpufreq.o
- obj-$(CONFIG_ARM_TEGRA186_CPUFREQ)	+= tegra186-cpufreq.o
---- /dev/null
-+++ b/drivers/cpufreq/bcm2835-cpufreq.c
-@@ -0,0 +1,210 @@
-+/*
-+ * Copyright 2011 Broadcom Corporation.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; version 2
-+ * of the License.
-+ *
-+ * This driver dynamically manages the CPU Frequency of the ARM
-+ * processor. Messages are sent to Videocore either setting or requesting the
-+ * frequency of the ARM in order to match an appropiate frequency to the current
-+ * usage of the processor. The policy which selects the frequency to use is
-+ * defined in the kernel .config file, but can be changed during runtime.
-+ */
-+
-+/* ---------- INCLUDES ---------- */
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+/* ---------- DEFINES ---------- */
-+/*#define CPUFREQ_DEBUG_ENABLE*/		/* enable debugging */
-+#define MODULE_NAME "bcm2835-cpufreq"
-+
-+#define VCMSG_ID_ARM_CLOCK 0x000000003		/* Clock/Voltage ID's */
-+
-+/* debug printk macros */
-+#ifdef CPUFREQ_DEBUG_ENABLE
-+#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#else
-+#define print_debug(fmt,...)
-+#endif
-+#define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__)
-+#define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__)
-+
-+/* ---------- GLOBALS ---------- */
-+static struct cpufreq_driver bcm2835_cpufreq_driver;	/* the cpufreq driver global */
-+static unsigned int min_frequency, max_frequency;
-+static struct cpufreq_frequency_table bcm2835_freq_table[3];
-+
-+/*
-+ ===============================================
-+  clk_rate either gets or sets the clock rates.
-+ ===============================================
-+*/
-+
-+static int bcm2835_cpufreq_clock_property(u32 tag, u32 id, u32 *val)
-+{
-+	struct rpi_firmware *fw = rpi_firmware_get(NULL);
-+	struct {
-+		u32 id;
-+		u32 val;
-+	} packet;
-+	int ret;
-+
-+	packet.id = id;
-+	packet.val = *val;
-+	ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet));
-+	if (ret)
-+		return ret;
-+
-+	*val = packet.val;
-+
-+	return 0;
-+}
-+
-+static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate)
-+{
-+	u32 rate = arm_rate * 1000;
-+	int ret;
-+
-+	ret = bcm2835_cpufreq_clock_property(RPI_FIRMWARE_SET_CLOCK_RATE, VCMSG_ID_ARM_CLOCK, &rate);
-+	if (ret) {
-+		print_err("Failed to set clock: %d (%d)\n", arm_rate, ret);
-+		return 0;
-+	}
-+
-+	rate /= 1000;
-+	print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, rate);
-+
-+	return rate;
-+}
-+
-+static uint32_t bcm2835_cpufreq_get_clock(int tag)
-+{
-+	u32 rate;
-+	int ret;
-+
-+	ret = bcm2835_cpufreq_clock_property(tag, VCMSG_ID_ARM_CLOCK, &rate);
-+	if (ret) {
-+		print_err("Failed to get clock (%d)\n", ret);
-+		return 0;
-+	}
-+
-+	rate /= 1000;
-+	print_debug("%s frequency = %u\n",
-+		tag == RPI_FIRMWARE_GET_CLOCK_RATE ? "Current":
-+		tag == RPI_FIRMWARE_GET_MIN_CLOCK_RATE ? "Min":
-+		tag == RPI_FIRMWARE_GET_MAX_CLOCK_RATE ? "Max":
-+		"Unexpected", rate);
-+
-+	return rate;
-+}
-+
-+/*
-+ ====================================================
-+  Module Initialisation registers the cpufreq driver
-+ ====================================================
-+*/
-+static int __init bcm2835_cpufreq_module_init(void)
-+{
-+	print_debug("IN\n");
-+	return cpufreq_register_driver(&bcm2835_cpufreq_driver);
-+}
-+
-+/*
-+ =============
-+  Module exit
-+ =============
-+*/
-+static void __exit bcm2835_cpufreq_module_exit(void)
-+{
-+	print_debug("IN\n");
-+	cpufreq_unregister_driver(&bcm2835_cpufreq_driver);
-+	return;
-+}
-+
-+/*
-+ ==============================================================
-+  Initialisation function sets up the CPU policy for first use
-+ ==============================================================
-+*/
-+static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy)
-+{
-+	/* measured value of how long it takes to change frequency */
-+	const unsigned int transition_latency = 355000; /* ns */
-+
-+	if (!rpi_firmware_get(NULL)) {
-+		print_err("Firmware is not available\n");
-+		return -ENODEV;
-+	}
-+
-+	/* now find out what the maximum and minimum frequencies are */
-+	min_frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MIN_CLOCK_RATE);
-+	max_frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MAX_CLOCK_RATE);
-+
-+	if (min_frequency == max_frequency) {
-+		bcm2835_freq_table[0].frequency = min_frequency;
-+		bcm2835_freq_table[1].frequency = CPUFREQ_TABLE_END;
-+	} else {
-+		bcm2835_freq_table[0].frequency = min_frequency;
-+		bcm2835_freq_table[1].frequency = max_frequency;
-+		bcm2835_freq_table[2].frequency = CPUFREQ_TABLE_END;
-+	}
-+
-+	print_info("min=%d max=%d\n", min_frequency, max_frequency);
-+	return cpufreq_generic_init(policy, bcm2835_freq_table, transition_latency);
-+}
-+
-+/*
-+ =====================================================================
-+  Target index function chooses the requested frequency from the table
-+ =====================================================================
-+*/
-+
-+static int bcm2835_cpufreq_driver_target_index(struct cpufreq_policy *policy, unsigned int state)
-+{
-+	unsigned int target_freq = state == 0 ? min_frequency : max_frequency;
-+	unsigned int cur = bcm2835_cpufreq_set_clock(policy->cur, target_freq);
-+
-+	if (!cur)
-+	{
-+		print_err("Error occurred setting a new frequency (%d)\n", target_freq);
-+		return -EINVAL;
-+	}
-+	print_debug("%s: %i: freq %d->%d\n", policy->governor->name, state, policy->cur, cur);
-+	return 0;
-+}
-+
-+/*
-+ ======================================================
-+  Get function returns the current frequency from table
-+ ======================================================
-+*/
-+
-+static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu)
-+{
-+	unsigned int actual_rate = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_CLOCK_RATE);
-+	print_debug("cpu%d: freq=%d\n", cpu, actual_rate);
-+	return actual_rate <= min_frequency ? min_frequency : max_frequency;
-+}
-+
-+/* the CPUFreq driver */
-+static struct cpufreq_driver bcm2835_cpufreq_driver = {
-+	.name         = "BCM2835 CPUFreq",
-+	.init         = bcm2835_cpufreq_driver_init,
-+	.verify       = cpufreq_generic_frequency_table_verify,
-+	.target_index = bcm2835_cpufreq_driver_target_index,
-+	.get          = bcm2835_cpufreq_driver_get,
-+	.attr         = cpufreq_generic_attr,
-+};
-+
-+MODULE_AUTHOR("Dorian Peake and Dom Cobley");
-+MODULE_DESCRIPTION("CPU frequency driver for BCM2835 chip");
-+MODULE_LICENSE("GPL");
-+
-+module_init(bcm2835_cpufreq_module_init);
-+module_exit(bcm2835_cpufreq_module_exit);
diff --git a/target/linux/brcm2708/patches-4.14/950-0050-Add-Chris-Boot-s-i2c-driver.patch b/target/linux/brcm2708/patches-4.14/950-0050-Add-Chris-Boot-s-i2c-driver.patch
deleted file mode 100644
index 541f361b6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0050-Add-Chris-Boot-s-i2c-driver.patch
+++ /dev/null
@@ -1,660 +0,0 @@
-From 3f29d388c56ea2bb3ef07cc4d6f61a2e5b5ec397 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Wed, 17 Jun 2015 15:44:08 +0100
-Subject: [PATCH 050/454] Add Chris Boot's i2c driver
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-i2c-bcm2708: fixed baudrate
-
-Fixed issue where the wrong CDIV value was set for baudrates below 3815 Hz (for 250MHz bus clock).
-In that case the computed CDIV value was more than 0xffff. However the CDIV register width is only 16 bits.
-This resulted in incorrect setting of CDIV and higher baudrate than intended.
-Example: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0x1704 -> 42430Hz
-After correction: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0xffff -> 3815Hz
-The correct baudrate is shown in the log after the cdiv > 0xffff correction.
-
-Perform I2C combined transactions when possible
-
-Perform I2C combined transactions whenever possible, within the
-restrictions of the Broadcomm Serial Controller.
-
-Disable DONE interrupt during TA poll
-
-Prevent interrupt from being triggered if poll is missed and transfer
-starts and finishes.
-
-i2c: Make combined transactions optional and disabled by default
-
-i2c: bcm2708: add device tree support
-
-Add DT support to driver and add to .dtsi file.
-Setup pins in .dts file.
-i2c is disabled by default.
-
-Signed-off-by: Noralf Tronnes <notro@tronnes.org>
-
-bcm2708: don't register i2c controllers when using DT
-
-The devices for the i2c controllers are in the Device Tree.
-Only register devices when not using DT.
-
-Signed-off-by: Noralf Tronnes <notro@tronnes.org>
-
-I2C: Only register the I2C device for the current board revision
-
-i2c_bcm2708: Fix clock reference counting
-
-Fix grabbing lock from atomic context in i2c driver
-
-2 main changes:
-- check for timeouts in the bcm2708_bsc_setup function as indicated by this comment:
-      /* poll for transfer start bit (should only take 1-20 polls) */
-  This implies that the setup function can now fail so account for this everywhere it's called
-- Removed the clk_get_rate call from inside the setup function as it locks a mutex and that's not ok since we call it from under a spin lock.
-
-i2c-bcm2708: When using DT, leave the GPIO setup to pinctrl
-
-i2c-bcm2708: Increase timeouts to allow larger transfers
-
-Use the timeout value provided by the I2C_TIMEOUT ioctl when waiting
-for completion. The default timeout is 1 second.
-
-See: https://github.com/raspberrypi/linux/issues/260
-
-i2c-bcm2708/BCM270X_DT: Add support for I2C2
-
-The third I2C bus (I2C2) is normally reserved for HDMI use. Careless
-use of this bus can break an attached display - use with caution.
-
-It is recommended to disable accesses by VideoCore by setting
-hdmi_ignore_edid=1 or hdmi_edid_file=1 in config.txt.
-
-The interface is disabled by default - enable using the
-i2c2_iknowwhatimdoing DT parameter.
-
-bcm2708-spi: Don't use static pin configuration with DT
-
-Also remove superfluous error checking - the SPI framework ensures the
-validity of the chip_select value.
-
-i2c-bcm2708: Remove non-DT support
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-Set the BSC_CLKT clock streching timeout to 35ms as per SMBus specs.
-
-Fixes i2c_bcm2708: Write to FIFO correctly - v2 (#1574)
-
-* i2c: fix i2c_bcm2708: Clear FIFO before sending data
-
-Make sure FIFO gets cleared before trying to send
-data in case of a repeated start (COMBINED=Y).
-
-* i2c: fix i2c_bcm2708: Only write to FIFO when not full
-
-Check if FIFO can accept data before writing.
-To avoid a peripheral read on the last iteration of a loop,
-both bcm2708_bsc_fifo_fill and ~drain are changed as well.
----
- drivers/i2c/busses/Kconfig       |  19 ++
- drivers/i2c/busses/Makefile      |   2 +
- drivers/i2c/busses/i2c-bcm2708.c | 512 +++++++++++++++++++++++++++++++
- 3 files changed, 533 insertions(+)
- create mode 100644 drivers/i2c/busses/i2c-bcm2708.c
-
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -8,6 +8,25 @@ menu "I2C Hardware Bus support"
- comment "PC SMBus host controller drivers"
- 	depends on PCI
- 
-+config I2C_BCM2708
-+	tristate "BCM2708 BSC"
-+	depends on ARCH_BCM2835
-+	help
-+	  Enabling this option will add BSC (Broadcom Serial Controller)
-+	  support for the BCM2708. BSC is a Broadcom proprietary bus compatible
-+	  with I2C/TWI/SMBus.
-+
-+config I2C_BCM2708_BAUDRATE
-+	prompt "BCM2708 I2C baudrate"
-+	depends on I2C_BCM2708
-+	int
-+	default 100000
-+	help
-+	  Set the I2C baudrate. This will alter the default value. A
-+	  different baudrate can be set by using a module parameter as well. If
-+	  no parameter is provided when loading, this is the value that will be
-+	  used.
-+
- config I2C_ALI1535
- 	tristate "ALI 1535"
- 	depends on PCI
---- a/drivers/i2c/busses/Makefile
-+++ b/drivers/i2c/busses/Makefile
-@@ -3,6 +3,8 @@
- # Makefile for the i2c bus drivers.
- #
- 
-+obj-$(CONFIG_I2C_BCM2708)	+= i2c-bcm2708.o
-+
- # ACPI drivers
- obj-$(CONFIG_I2C_SCMI)		+= i2c-scmi.o
- 
---- /dev/null
-+++ b/drivers/i2c/busses/i2c-bcm2708.c
-@@ -0,0 +1,512 @@
-+/*
-+ * Driver for Broadcom BCM2708 BSC Controllers
-+ *
-+ * Copyright (C) 2012 Chris Boot & Frank Buss
-+ *
-+ * This driver is inspired by:
-+ * i2c-ocores.c, by Peter Korsgaard <jacmet@sunsite.dk>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/spinlock.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/slab.h>
-+#include <linux/i2c.h>
-+#include <linux/interrupt.h>
-+#include <linux/sched.h>
-+#include <linux/wait.h>
-+
-+/* BSC register offsets */
-+#define BSC_C			0x00
-+#define BSC_S			0x04
-+#define BSC_DLEN		0x08
-+#define BSC_A			0x0c
-+#define BSC_FIFO		0x10
-+#define BSC_DIV			0x14
-+#define BSC_DEL			0x18
-+#define BSC_CLKT		0x1c
-+
-+/* Bitfields in BSC_C */
-+#define BSC_C_I2CEN		0x00008000
-+#define BSC_C_INTR		0x00000400
-+#define BSC_C_INTT		0x00000200
-+#define BSC_C_INTD		0x00000100
-+#define BSC_C_ST		0x00000080
-+#define BSC_C_CLEAR_1		0x00000020
-+#define BSC_C_CLEAR_2		0x00000010
-+#define BSC_C_READ		0x00000001
-+
-+/* Bitfields in BSC_S */
-+#define BSC_S_CLKT		0x00000200
-+#define BSC_S_ERR		0x00000100
-+#define BSC_S_RXF		0x00000080
-+#define BSC_S_TXE		0x00000040
-+#define BSC_S_RXD		0x00000020
-+#define BSC_S_TXD		0x00000010
-+#define BSC_S_RXR		0x00000008
-+#define BSC_S_TXW		0x00000004
-+#define BSC_S_DONE		0x00000002
-+#define BSC_S_TA		0x00000001
-+
-+#define I2C_WAIT_LOOP_COUNT	200
-+
-+#define DRV_NAME		"bcm2708_i2c"
-+
-+static unsigned int baudrate;
-+module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
-+MODULE_PARM_DESC(baudrate, "The I2C baudrate");
-+
-+static bool combined = false;
-+module_param(combined, bool, 0644);
-+MODULE_PARM_DESC(combined, "Use combined transactions");
-+
-+struct bcm2708_i2c {
-+	struct i2c_adapter adapter;
-+
-+	spinlock_t lock;
-+	void __iomem *base;
-+	int irq;
-+	struct clk *clk;
-+	u32 cdiv;
-+	u32 clk_tout;
-+
-+	struct completion done;
-+
-+	struct i2c_msg *msg;
-+	int pos;
-+	int nmsgs;
-+	bool error;
-+};
-+
-+static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg)
-+{
-+	return readl(bi->base + reg);
-+}
-+
-+static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val)
-+{
-+	writel(val, bi->base + reg);
-+}
-+
-+static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi)
-+{
-+	bcm2708_wr(bi, BSC_C, 0);
-+	bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
-+}
-+
-+static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi)
-+{
-+	while ((bi->pos < bi->msg->len) && (bcm2708_rd(bi, BSC_S) & BSC_S_RXD))
-+		bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO);
-+}
-+
-+static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi)
-+{
-+	while ((bi->pos < bi->msg->len) && (bcm2708_rd(bi, BSC_S) & BSC_S_TXD))
-+		bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
-+}
-+
-+static inline int bcm2708_bsc_setup(struct bcm2708_i2c *bi)
-+{
-+	u32 cdiv, s, clk_tout;
-+	u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;
-+	int wait_loops = I2C_WAIT_LOOP_COUNT;
-+
-+	/* Can't call clk_get_rate as it locks a mutex and here we are spinlocked.
-+	 * Use the value that we cached in the probe.
-+	 */
-+	cdiv = bi->cdiv;
-+	clk_tout = bi->clk_tout;
-+
-+	if (bi->msg->flags & I2C_M_RD)
-+		c |= BSC_C_INTR | BSC_C_READ;
-+	else
-+		c |= BSC_C_INTT;
-+
-+	bcm2708_wr(bi, BSC_CLKT, clk_tout);
-+	bcm2708_wr(bi, BSC_DIV, cdiv);
-+	bcm2708_wr(bi, BSC_A, bi->msg->addr);
-+	bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
-+	if (combined)
-+	{
-+		/* Do the next two messages meet combined transaction criteria?
-+		   - Current message is a write, next message is a read
-+		   - Both messages to same slave address
-+		   - Write message can fit inside FIFO (16 bytes or less) */
-+		if ( (bi->nmsgs > 1) &&
-+			!(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) &&
-+			 (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) {
-+
-+			/* Clear FIFO */
-+			bcm2708_wr(bi, BSC_C, BSC_C_CLEAR_1);
-+
-+			/* Fill FIFO with entire write message (16 byte FIFO) */
-+			while (bi->pos < bi->msg->len) {
-+				bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
-+			}
-+			/* Start write transfer (no interrupts, don't clear FIFO) */
-+			bcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST);
-+
-+			/* poll for transfer start bit (should only take 1-20 polls) */
-+			do {
-+				s = bcm2708_rd(bi, BSC_S);
-+			} while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)) && --wait_loops >= 0);
-+
-+			/* did we time out or some error occured? */
-+			if (wait_loops < 0 || (s & (BSC_S_ERR | BSC_S_CLKT))) {
-+				return -1;
-+			}
-+
-+			/* Send next read message before the write transfer finishes. */
-+			bi->nmsgs--;
-+			bi->msg++;
-+			bi->pos = 0;
-+			bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
-+			c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ;
-+		}
-+	}
-+	bcm2708_wr(bi, BSC_C, c);
-+
-+	return 0;
-+}
-+
-+static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id)
-+{
-+	struct bcm2708_i2c *bi = dev_id;
-+	bool handled = true;
-+	u32 s;
-+	int ret;
-+
-+	spin_lock(&bi->lock);
-+
-+	/* we may see camera interrupts on the "other" I2C channel
-+		   Just return if we've not sent anything */
-+	if (!bi->nmsgs || !bi->msg) {
-+		goto early_exit;
-+	}
-+
-+	s = bcm2708_rd(bi, BSC_S);
-+
-+	if (s & (BSC_S_CLKT | BSC_S_ERR)) {
-+		bcm2708_bsc_reset(bi);
-+		bi->error = true;
-+
-+		bi->msg = 0; /* to inform the that all work is done */
-+		bi->nmsgs = 0;
-+		/* wake up our bh */
-+		complete(&bi->done);
-+	} else if (s & BSC_S_DONE) {
-+		bi->nmsgs--;
-+
-+		if (bi->msg->flags & I2C_M_RD) {
-+			bcm2708_bsc_fifo_drain(bi);
-+		}
-+
-+		bcm2708_bsc_reset(bi);
-+
-+		if (bi->nmsgs) {
-+			/* advance to next message */
-+			bi->msg++;
-+			bi->pos = 0;
-+			ret = bcm2708_bsc_setup(bi);
-+			if (ret < 0) {
-+				bcm2708_bsc_reset(bi);
-+				bi->error = true;
-+				bi->msg = 0; /* to inform the that all work is done */
-+				bi->nmsgs = 0;
-+				/* wake up our bh */
-+				complete(&bi->done);
-+				goto early_exit;
-+			}
-+		} else {
-+			bi->msg = 0; /* to inform the that all work is done */
-+			bi->nmsgs = 0;
-+			/* wake up our bh */
-+			complete(&bi->done);
-+		}
-+	} else if (s & BSC_S_TXW) {
-+		bcm2708_bsc_fifo_fill(bi);
-+	} else if (s & BSC_S_RXR) {
-+		bcm2708_bsc_fifo_drain(bi);
-+	} else {
-+		handled = false;
-+	}
-+
-+early_exit:
-+	spin_unlock(&bi->lock);
-+
-+	return handled ? IRQ_HANDLED : IRQ_NONE;
-+}
-+
-+static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap,
-+	struct i2c_msg *msgs, int num)
-+{
-+	struct bcm2708_i2c *bi = adap->algo_data;
-+	unsigned long flags;
-+	int ret;
-+
-+	spin_lock_irqsave(&bi->lock, flags);
-+
-+	reinit_completion(&bi->done);
-+	bi->msg = msgs;
-+	bi->pos = 0;
-+	bi->nmsgs = num;
-+	bi->error = false;
-+
-+	ret = bcm2708_bsc_setup(bi);
-+
-+	spin_unlock_irqrestore(&bi->lock, flags);
-+
-+	/* check the result of the setup */
-+	if (ret < 0)
-+	{
-+		dev_err(&adap->dev, "transfer setup timed out\n");
-+		goto error_timeout;
-+	}
-+
-+	ret = wait_for_completion_timeout(&bi->done, adap->timeout);
-+	if (ret == 0) {
-+		dev_err(&adap->dev, "transfer timed out\n");
-+		goto error_timeout;
-+	}
-+
-+	ret = bi->error ? -EIO : num;
-+	return ret;
-+
-+error_timeout:
-+	spin_lock_irqsave(&bi->lock, flags);
-+	bcm2708_bsc_reset(bi);
-+	bi->msg = 0; /* to inform the interrupt handler that there's nothing else to be done */
-+	bi->nmsgs = 0;
-+	spin_unlock_irqrestore(&bi->lock, flags);
-+	return -ETIMEDOUT;
-+}
-+
-+static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap)
-+{
-+	return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL;
-+}
-+
-+static struct i2c_algorithm bcm2708_i2c_algorithm = {
-+	.master_xfer = bcm2708_i2c_master_xfer,
-+	.functionality = bcm2708_i2c_functionality,
-+};
-+
-+static int bcm2708_i2c_probe(struct platform_device *pdev)
-+{
-+	struct resource *regs;
-+	int irq, err = -ENOMEM;
-+	struct clk *clk;
-+	struct bcm2708_i2c *bi;
-+	struct i2c_adapter *adap;
-+	unsigned long bus_hz;
-+	u32 cdiv, clk_tout;
-+	u32 baud;
-+
-+	baud = CONFIG_I2C_BCM2708_BAUDRATE;
-+
-+	if (pdev->dev.of_node) {
-+		u32 bus_clk_rate;
-+		pdev->id = of_alias_get_id(pdev->dev.of_node, "i2c");
-+		if (pdev->id < 0) {
-+			dev_err(&pdev->dev, "alias is missing\n");
-+			return -EINVAL;
-+		}
-+		if (!of_property_read_u32(pdev->dev.of_node,
-+					"clock-frequency", &bus_clk_rate))
-+			baud = bus_clk_rate;
-+		else
-+			dev_warn(&pdev->dev,
-+				"Could not read clock-frequency property\n");
-+	}
-+
-+	if (baudrate)
-+		baud = baudrate;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(&pdev->dev, "could not get IO memory\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_err(&pdev->dev, "could not get IRQ\n");
-+		return irq;
-+	}
-+
-+	clk = clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(clk)) {
-+		dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
-+		return PTR_ERR(clk);
-+	}
-+
-+	err = clk_prepare_enable(clk);
-+	if (err) {
-+		dev_err(&pdev->dev, "could not enable clk: %d\n", err);
-+		goto out_clk_put;
-+	}
-+
-+	bi = kzalloc(sizeof(*bi), GFP_KERNEL);
-+	if (!bi)
-+		goto out_clk_disable;
-+
-+	platform_set_drvdata(pdev, bi);
-+
-+	adap = &bi->adapter;
-+	adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC;
-+	adap->algo = &bcm2708_i2c_algorithm;
-+	adap->algo_data = bi;
-+	adap->dev.parent = &pdev->dev;
-+	adap->nr = pdev->id;
-+	strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-+	adap->dev.of_node = pdev->dev.of_node;
-+
-+	switch (pdev->id) {
-+	case 0:
-+		adap->class = I2C_CLASS_HWMON;
-+		break;
-+	case 1:
-+		adap->class = I2C_CLASS_DDC;
-+		break;
-+	case 2:
-+		adap->class = I2C_CLASS_DDC;
-+		break;
-+	default:
-+		dev_err(&pdev->dev, "can only bind to BSC 0, 1 or 2\n");
-+		err = -ENXIO;
-+		goto out_free_bi;
-+	}
-+
-+	spin_lock_init(&bi->lock);
-+	init_completion(&bi->done);
-+
-+	bi->base = ioremap(regs->start, resource_size(regs));
-+	if (!bi->base) {
-+		dev_err(&pdev->dev, "could not remap memory\n");
-+		goto out_free_bi;
-+	}
-+
-+	bi->irq = irq;
-+	bi->clk = clk;
-+
-+	err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED,
-+			dev_name(&pdev->dev), bi);
-+	if (err) {
-+		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
-+		goto out_iounmap;
-+	}
-+
-+	bcm2708_bsc_reset(bi);
-+
-+	err = i2c_add_numbered_adapter(adap);
-+	if (err < 0) {
-+		dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err);
-+		goto out_free_irq;
-+	}
-+
-+	bus_hz = clk_get_rate(bi->clk);
-+	cdiv = bus_hz / baud;
-+	if (cdiv > 0xffff) {
-+		cdiv = 0xffff;
-+		baud = bus_hz / cdiv;
-+	}
-+
-+	clk_tout = 35/1000*baud; //35ms timeout as per SMBus specs.
-+	if (clk_tout > 0xffff)
-+		clk_tout = 0xffff;
-+	
-+	bi->cdiv = cdiv;
-+	bi->clk_tout = clk_tout;
-+
-+	dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n",
-+		pdev->id, (unsigned long)regs->start, irq, baud);
-+
-+	return 0;
-+
-+out_free_irq:
-+	free_irq(bi->irq, bi);
-+out_iounmap:
-+	iounmap(bi->base);
-+out_free_bi:
-+	kfree(bi);
-+out_clk_disable:
-+	clk_disable_unprepare(clk);
-+out_clk_put:
-+	clk_put(clk);
-+	return err;
-+}
-+
-+static int bcm2708_i2c_remove(struct platform_device *pdev)
-+{
-+	struct bcm2708_i2c *bi = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+
-+	i2c_del_adapter(&bi->adapter);
-+	free_irq(bi->irq, bi);
-+	iounmap(bi->base);
-+	clk_disable_unprepare(bi->clk);
-+	clk_put(bi->clk);
-+	kfree(bi);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id bcm2708_i2c_of_match[] = {
-+        { .compatible = "brcm,bcm2708-i2c" },
-+        {},
-+};
-+MODULE_DEVICE_TABLE(of, bcm2708_i2c_of_match);
-+
-+static struct platform_driver bcm2708_i2c_driver = {
-+	.driver		= {
-+		.name	= DRV_NAME,
-+		.owner	= THIS_MODULE,
-+		.of_match_table = bcm2708_i2c_of_match,
-+	},
-+	.probe		= bcm2708_i2c_probe,
-+	.remove		= bcm2708_i2c_remove,
-+};
-+
-+// module_platform_driver(bcm2708_i2c_driver);
-+
-+
-+static int __init bcm2708_i2c_init(void)
-+{
-+	return platform_driver_register(&bcm2708_i2c_driver);
-+}
-+
-+static void __exit bcm2708_i2c_exit(void)
-+{
-+	platform_driver_unregister(&bcm2708_i2c_driver);
-+}
-+
-+module_init(bcm2708_i2c_init);
-+module_exit(bcm2708_i2c_exit);
-+
-+
-+
-+MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708");
-+MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/target/linux/brcm2708/patches-4.14/950-0051-char-broadcom-Add-vcio-module.patch b/target/linux/brcm2708/patches-4.14/950-0051-char-broadcom-Add-vcio-module.patch
deleted file mode 100644
index 11edfb1b3..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0051-char-broadcom-Add-vcio-module.patch
+++ /dev/null
@@ -1,220 +0,0 @@
-From 8783aa0977780bc848678c6d4c506128e1ff0b6f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Fri, 26 Jun 2015 14:27:06 +0200
-Subject: [PATCH 051/454] char: broadcom: Add vcio module
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add module for accessing the mailbox property channel through
-/dev/vcio. Was previously in bcm2708-vcio.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/char/broadcom/Kconfig  |   6 ++
- drivers/char/broadcom/Makefile |   1 +
- drivers/char/broadcom/vcio.c   | 175 +++++++++++++++++++++++++++++++++
- 3 files changed, 182 insertions(+)
- create mode 100644 drivers/char/broadcom/vcio.c
-
---- a/drivers/char/broadcom/Kconfig
-+++ b/drivers/char/broadcom/Kconfig
-@@ -15,6 +15,12 @@ config BCM2708_VCMEM
-         help
-           Helper for videocore memory access and total size allocation.
- 
-+config BCM_VCIO
-+	tristate "Mailbox userspace access"
-+	depends on BCM2835_MBOX
-+	help
-+	  Gives access to the mailbox property channel from userspace.
-+
- endif
- 
- config BCM_VC_SM
---- a/drivers/char/broadcom/Makefile
-+++ b/drivers/char/broadcom/Makefile
-@@ -1,4 +1,5 @@
- obj-$(CONFIG_BCM2708_VCMEM)	+= vc_mem.o
-+obj-$(CONFIG_BCM_VCIO)		+= vcio.o
- obj-$(CONFIG_BCM_VC_SM)         += vc_sm/
- 
- obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o
---- /dev/null
-+++ b/drivers/char/broadcom/vcio.c
-@@ -0,0 +1,175 @@
-+/*
-+ *  Copyright (C) 2010 Broadcom
-+ *  Copyright (C) 2015 Noralf Trønnes
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-+
-+#include <linux/cdev.h>
-+#include <linux/device.h>
-+#include <linux/fs.h>
-+#include <linux/init.h>
-+#include <linux/ioctl.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/uaccess.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+#define MBOX_CHAN_PROPERTY 8
-+
-+#define VCIO_IOC_MAGIC 100
-+#define IOCTL_MBOX_PROPERTY _IOWR(VCIO_IOC_MAGIC, 0, char *)
-+
-+static struct {
-+	dev_t devt;
-+	struct cdev cdev;
-+	struct class *class;
-+	struct rpi_firmware *fw;
-+} vcio;
-+
-+static int vcio_user_property_list(void *user)
-+{
-+	u32 *buf, size;
-+	int ret;
-+
-+	/* The first 32-bit is the size of the buffer */
-+	if (copy_from_user(&size, user, sizeof(size)))
-+		return -EFAULT;
-+
-+	buf = kmalloc(size, GFP_KERNEL);
-+	if (!buf)
-+		return -ENOMEM;
-+
-+	if (copy_from_user(buf, user, size)) {
-+		kfree(buf);
-+		return -EFAULT;
-+	}
-+
-+	/* Strip off protocol encapsulation */
-+	ret = rpi_firmware_property_list(vcio.fw, &buf[2], size - 12);
-+	if (ret) {
-+		kfree(buf);
-+		return ret;
-+	}
-+
-+	buf[1] = RPI_FIRMWARE_STATUS_SUCCESS;
-+	if (copy_to_user(user, buf, size))
-+		ret = -EFAULT;
-+
-+	kfree(buf);
-+
-+	return ret;
-+}
-+
-+static int vcio_device_open(struct inode *inode, struct file *file)
-+{
-+	try_module_get(THIS_MODULE);
-+
-+	return 0;
-+}
-+
-+static int vcio_device_release(struct inode *inode, struct file *file)
-+{
-+	module_put(THIS_MODULE);
-+
-+	return 0;
-+}
-+
-+static long vcio_device_ioctl(struct file *file, unsigned int ioctl_num,
-+			      unsigned long ioctl_param)
-+{
-+	switch (ioctl_num) {
-+	case IOCTL_MBOX_PROPERTY:
-+		return vcio_user_property_list((void *)ioctl_param);
-+	default:
-+		pr_err("unknown ioctl: %d\n", ioctl_num);
-+		return -EINVAL;
-+	}
-+}
-+
-+const struct file_operations vcio_fops = {
-+	.unlocked_ioctl = vcio_device_ioctl,
-+	.open = vcio_device_open,
-+	.release = vcio_device_release,
-+};
-+
-+static int __init vcio_init(void)
-+{
-+	struct device_node *np;
-+	static struct device *dev;
-+	int ret;
-+
-+	np = of_find_compatible_node(NULL, NULL,
-+				     "raspberrypi,bcm2835-firmware");
-+/* Uncomment this when we only boot with Device Tree
-+	if (!of_device_is_available(np))
-+		return -ENODEV;
-+*/
-+	vcio.fw = rpi_firmware_get(np);
-+	if (!vcio.fw)
-+		return -ENODEV;
-+
-+	ret = alloc_chrdev_region(&vcio.devt, 0, 1, "vcio");
-+	if (ret) {
-+		pr_err("failed to allocate device number\n");
-+		return ret;
-+	}
-+
-+	cdev_init(&vcio.cdev, &vcio_fops);
-+	vcio.cdev.owner = THIS_MODULE;
-+	ret = cdev_add(&vcio.cdev, vcio.devt, 1);
-+	if (ret) {
-+		pr_err("failed to register device\n");
-+		goto err_unregister_chardev;
-+	}
-+
-+	/*
-+	 * Create sysfs entries
-+	 * 'bcm2708_vcio' is used for backwards compatibility so we don't break
-+	 * userspace. Raspian has a udev rule that changes the permissions.
-+	 */
-+	vcio.class = class_create(THIS_MODULE, "bcm2708_vcio");
-+	if (IS_ERR(vcio.class)) {
-+		ret = PTR_ERR(vcio.class);
-+		pr_err("failed to create class\n");
-+		goto err_cdev_del;
-+	}
-+
-+	dev = device_create(vcio.class, NULL, vcio.devt, NULL, "vcio");
-+	if (IS_ERR(dev)) {
-+		ret = PTR_ERR(dev);
-+		pr_err("failed to create device\n");
-+		goto err_class_destroy;
-+	}
-+
-+	return 0;
-+
-+err_class_destroy:
-+	class_destroy(vcio.class);
-+err_cdev_del:
-+	cdev_del(&vcio.cdev);
-+err_unregister_chardev:
-+	unregister_chrdev_region(vcio.devt, 1);
-+
-+	return ret;
-+}
-+module_init(vcio_init);
-+
-+static void __exit vcio_exit(void)
-+{
-+	device_destroy(vcio.class, vcio.devt);
-+	class_destroy(vcio.class);
-+	cdev_del(&vcio.cdev);
-+	unregister_chrdev_region(vcio.devt, 1);
-+}
-+module_exit(vcio_exit);
-+
-+MODULE_AUTHOR("Gray Girling");
-+MODULE_AUTHOR("Noralf Trønnes");
-+MODULE_DESCRIPTION("Mailbox userspace access");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/brcm2708/patches-4.14/950-0052-firmware-bcm2835-Support-ARCH_BCM270x.patch b/target/linux/brcm2708/patches-4.14/950-0052-firmware-bcm2835-Support-ARCH_BCM270x.patch
deleted file mode 100644
index 57adad39c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0052-firmware-bcm2835-Support-ARCH_BCM270x.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From ece6072fd68653329941477989fa12fd1334c001 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Fri, 26 Jun 2015 14:25:01 +0200
-Subject: [PATCH 052/454] firmware: bcm2835: Support ARCH_BCM270x
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Support booting without Device Tree.
-Turn on USB power.
-Load driver early because of lacking support for deferred probing
-in many drivers.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-firmware: bcm2835: Don't turn on USB power
-
-The raspberrypi-power driver is now used to turn on USB power.
-
-This partly reverts commit:
-firmware: bcm2835: Support ARCH_BCM270x
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/firmware/raspberrypi.c | 19 +++++++++++++++++--
- 1 file changed, 17 insertions(+), 2 deletions(-)
-
---- a/drivers/firmware/raspberrypi.c
-+++ b/drivers/firmware/raspberrypi.c
-@@ -28,6 +28,8 @@ struct rpi_firmware {
- 	u32 enabled;
- };
- 
-+static struct platform_device *g_pdev;
-+
- static DEFINE_MUTEX(transaction_lock);
- 
- static void response_callback(struct mbox_client *cl, void *msg)
-@@ -207,6 +209,7 @@ static int rpi_firmware_probe(struct pla
- 	init_completion(&fw->c);
- 
- 	platform_set_drvdata(pdev, fw);
-+	g_pdev = pdev;
- 
- 	rpi_firmware_print_firmware_revision(fw);
- 
-@@ -218,6 +221,7 @@ static int rpi_firmware_remove(struct pl
- 	struct rpi_firmware *fw = platform_get_drvdata(pdev);
- 
- 	mbox_free_channel(fw->chan);
-+	g_pdev = NULL;
- 
- 	return 0;
- }
-@@ -230,7 +234,7 @@ static int rpi_firmware_remove(struct pl
-  */
- struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node)
- {
--	struct platform_device *pdev = of_find_device_by_node(firmware_node);
-+	struct platform_device *pdev = g_pdev;
- 
- 	if (!pdev)
- 		return NULL;
-@@ -253,7 +257,18 @@ static struct platform_driver rpi_firmwa
- 	.probe		= rpi_firmware_probe,
- 	.remove		= rpi_firmware_remove,
- };
--module_platform_driver(rpi_firmware_driver);
-+
-+static int __init rpi_firmware_init(void)
-+{
-+	return platform_driver_register(&rpi_firmware_driver);
-+}
-+subsys_initcall(rpi_firmware_init);
-+
-+static void __init rpi_firmware_exit(void)
-+{
-+	platform_driver_unregister(&rpi_firmware_driver);
-+}
-+module_exit(rpi_firmware_exit);
- 
- MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
- MODULE_DESCRIPTION("Raspberry Pi firmware driver");
diff --git a/target/linux/brcm2708/patches-4.14/950-0053-scripts-Add-mkknlimg-and-knlinfo-scripts-from-tools-.patch b/target/linux/brcm2708/patches-4.14/950-0053-scripts-Add-mkknlimg-and-knlinfo-scripts-from-tools-.patch
deleted file mode 100644
index ed2af04ad..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0053-scripts-Add-mkknlimg-and-knlinfo-scripts-from-tools-.patch
+++ /dev/null
@@ -1,523 +0,0 @@
-From 1451eae50acf35f852b7218722a0f28d78eaeb98 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 11 May 2015 09:00:42 +0100
-Subject: [PATCH 053/454] scripts: Add mkknlimg and knlinfo scripts from tools
- repo
-
-The Raspberry Pi firmware looks for a trailer on the kernel image to
-determine whether it was compiled with Device Tree support enabled.
-If the firmware finds a kernel without this trailer, or which has a
-trailer indicating that it isn't DT-capable, it disables DT support
-and reverts to using ATAGs.
-
-The mkknlimg utility adds that trailer, having first analysed the
-image to look for signs of DT support and the kernel version string.
-
-knlinfo displays the contents of the trailer in the given kernel image.
-
-scripts/mkknlimg: Add support for ARCH_BCM2835
-
-Add a new trailer field indicating whether this is an ARCH_BCM2835
-build, as opposed to MACH_BCM2708/9. If the loader finds this flag
-is set it changes the default base dtb file name from bcm270x...
-to bcm283y...
-
-Also update knlinfo to show the status of the field.
-
-scripts/mkknlimg: Improve ARCH_BCM2835 detection
-
-The board support code contains sufficient strings to be able to
-distinguish 2708 vs. 2835 builds, so remove the check for
-bcm2835-pm-wdt which could exist in either.
-
-Also, since the canned configuration is no longer built in (it's
-a module), remove the config string checking.
-
-See: https://github.com/raspberrypi/linux/issues/1157
-
-scripts: Multi-platform support for mkknlimg and knlinfo
-
-The firmware uses tags in the kernel trailer to choose which dtb file
-to load. Current firmware loads bcm2835-*.dtb if the '283x' tag is true,
-otherwise it loads bcm270*.dtb. This scheme breaks if an image supports
-multiple platforms.
-
-This patch adds '270X' and '283X' tags to indicate support for RPi and
-upstream platforms, respectively. '283x' (note lower case 'x') is left
-for old firmware, and is only set if the image only supports upstream
-builds.
-
-scripts/mkknlimg: Append a trailer for all input
-
-Now that the firmware assumes an unsigned kernel is DT-capable, it is
-helpful to be able to mark a kernel as being non-DT-capable.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-scripts/knlinfo: Decode DDTK atom
-
-Show the DDTK atom as being a boolean.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-mkknlimg: Retain downstream-kernel detection
-
-With the death of ARCH_BCM2708 and ARCH_BCM2709, a new way is needed to
-determine if this is a "downstream" build that wants the firmware to
-load a bcm27xx .dtb. The vc_cma driver is used downstream but not
-upstream, making vc_cma_init a suitable predicate symbol.
-
-mkknlimg: Find some more downstream-only strings
-
-See: https://github.com/raspberrypi/linux/issues/1920
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- scripts/knlinfo  | 171 ++++++++++++++++++++++++++++++
- scripts/mkknlimg | 265 +++++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 436 insertions(+)
- create mode 100755 scripts/knlinfo
- create mode 100755 scripts/mkknlimg
-
---- /dev/null
-+++ b/scripts/knlinfo
-@@ -0,0 +1,171 @@
-+#!/usr/bin/env perl
-+# ----------------------------------------------------------------------
-+# knlinfo by Phil Elwell for Raspberry Pi
-+#
-+# (c) 2014,2015 Raspberry Pi (Trading) Limited <info@raspberrypi.org>
-+#
-+# Licensed under the terms of the GNU General Public License.
-+# ----------------------------------------------------------------------
-+
-+use strict;
-+use integer;
-+
-+use Fcntl ":seek";
-+
-+my $trailer_magic = 'RPTL';
-+
-+my %atom_formats =
-+(
-+    'DDTK' => \&format_bool,
-+    'DTOK' => \&format_bool,
-+    'KVer' => \&format_string,
-+    '270X' => \&format_bool,
-+    '283X' => \&format_bool,
-+    '283x' => \&format_bool,
-+);
-+
-+if (@ARGV != 1)
-+{
-+	print ("Usage: knlinfo <kernel image>\n");
-+	exit(1);
-+}
-+
-+my $kernel_file = $ARGV[0];
-+
-+
-+my ($atoms, $pos) = read_trailer($kernel_file);
-+
-+exit(1) if (!$atoms);
-+
-+printf("Kernel trailer found at %d/0x%x:\n", $pos, $pos);
-+
-+foreach my $atom (@$atoms)
-+{
-+    printf("  %s: %s\n", $atom->[0], format_atom($atom));
-+}
-+
-+exit(0);
-+
-+sub read_trailer
-+{
-+	my ($kernel_file) = @_;
-+	my $fh;
-+
-+	if (!open($fh, '<', $kernel_file))
-+	{
-+		print ("* Failed to open '$kernel_file'\n");
-+		return undef;
-+	}
-+
-+	if (!seek($fh, -12, SEEK_END))
-+	{
-+		print ("* seek error in '$kernel_file'\n");
-+		return undef;
-+	}
-+
-+	my $last_bytes;
-+	sysread($fh, $last_bytes, 12);
-+
-+	my ($trailer_len, $data_len, $magic) = unpack('VVa4', $last_bytes);
-+
-+	if (($magic ne $trailer_magic) || ($data_len != 4))
-+	{
-+		print ("* no trailer\n");
-+		return undef;
-+	}
-+	if (!seek($fh, -12, SEEK_END))
-+	{
-+		print ("* seek error in '$kernel_file'\n");
-+		return undef;
-+	}
-+
-+	$trailer_len -= 12;
-+
-+	while ($trailer_len > 0)
-+	{
-+		if ($trailer_len < 8)
-+		{
-+			print ("* truncated atom header in trailer\n");
-+			return undef;
-+		}
-+		if (!seek($fh, -8, SEEK_CUR))
-+		{
-+			print ("* seek error in '$kernel_file'\n");
-+			return undef;
-+		}
-+		$trailer_len -= 8;
-+
-+		my $atom_hdr;
-+		sysread($fh, $atom_hdr, 8);
-+		my ($atom_len, $atom_type) = unpack('Va4', $atom_hdr);
-+
-+		if ($trailer_len < $atom_len)
-+		{
-+			print ("* truncated atom data in trailer\n");
-+			return undef;
-+		}
-+
-+		my $rounded_len = (($atom_len + 3) & ~3);
-+		if (!seek($fh, -(8 + $rounded_len), SEEK_CUR))
-+		{
-+			print ("* seek error in '$kernel_file'\n");
-+			return undef;
-+		}
-+		$trailer_len -= $rounded_len;
-+
-+		my $atom_data;
-+		sysread($fh, $atom_data, $atom_len);
-+
-+		if (!seek($fh, -$atom_len, SEEK_CUR))
-+		{
-+			print ("* seek error in '$kernel_file'\n");
-+			return undef;
-+		}
-+
-+		push @$atoms, [ $atom_type, $atom_data ];
-+	}
-+
-+ 	if (($$atoms[-1][0] eq "\x00\x00\x00\x00") &&
-+	    ($$atoms[-1][1] eq ""))
-+	{
-+		pop @$atoms;
-+	}
-+	else
-+	{
-+		print ("* end marker missing from trailer\n");
-+	}
-+
-+	return ($atoms, tell($fh));
-+}
-+
-+sub format_atom
-+{
-+    my ($atom) = @_;
-+
-+    my $format_func = $atom_formats{$atom->[0]} || \&format_hex;
-+    return $format_func->($atom->[1]);
-+}
-+
-+sub format_bool
-+{
-+    my ($data) = @_;
-+    return unpack('V', $data) ? 'y' : 'n';
-+}
-+
-+sub format_int
-+{
-+    my ($data) = @_;
-+    return unpack('V', $data);
-+}
-+
-+sub format_string
-+{
-+    my ($data) = @_;
-+    return '"'.$data.'"';
-+}
-+
-+sub format_hex
-+{
-+    my ($data) = @_;
-+    return unpack('H*', $data);
-+}
---- /dev/null
-+++ b/scripts/mkknlimg
-@@ -0,0 +1,265 @@
-+#!/usr/bin/env perl
-+# ----------------------------------------------------------------------
-+# mkknlimg by Phil Elwell for Raspberry Pi
-+# based on extract-ikconfig by Dick Streefland
-+#
-+# (c) 2009,2010 Dick Streefland <dick@streefland.net>
-+# (c) 2014,2015 Raspberry Pi (Trading) Limited <info@raspberrypi.org>
-+#
-+# Licensed under the terms of the GNU General Public License.
-+# ----------------------------------------------------------------------
-+
-+use strict;
-+use warnings;
-+use integer;
-+
-+use constant FLAG_PI   => 0x01;
-+use constant FLAG_DTOK => 0x02;
-+use constant FLAG_DDTK => 0x04;
-+use constant FLAG_270X => 0x08;
-+use constant FLAG_283X => 0x10;
-+
-+my $trailer_magic = 'RPTL';
-+
-+my $tmpfile1 = "/tmp/mkknlimg_$$.1";
-+my $tmpfile2 = "/tmp/mkknlimg_$$.2";
-+
-+my $dtok = 0;
-+my $ddtk = 0;
-+my $is_270x = 0;
-+my $is_283x = 0;
-+
-+while (@ARGV && ($ARGV[0] =~ /^-/))
-+{
-+    my $arg = shift(@ARGV);
-+    if ($arg eq '--dtok')
-+    {
-+	$dtok = 1;
-+    }
-+    elsif ($arg eq '--ddtk')
-+    {
-+	$ddtk = 1;
-+    }
-+    elsif ($arg eq '--270x')
-+    {
-+	$is_270x = 1;
-+    }
-+    elsif ($arg eq '--283x')
-+    {
-+	$is_283x = 1;
-+    }
-+    else
-+    {
-+	print ("* Unknown option '$arg'\n");
-+	usage();
-+    }
-+}
-+
-+usage() if (@ARGV != 2);
-+
-+my $kernel_file = $ARGV[0];
-+my $out_file = $ARGV[1];
-+
-+if (! -r $kernel_file)
-+{
-+    print ("* File '$kernel_file' not found\n");
-+    usage();
-+}
-+
-+my $wanted_strings =
-+{
-+	'bcm2708_fb' => FLAG_PI | FLAG_270X,
-+	'brcm,bcm2835-mmc' => FLAG_PI,
-+	'brcm,bcm2835-sdhost' => FLAG_PI,
-+	'brcm,bcm2708-pinctrl' => FLAG_PI | FLAG_DTOK,
-+	'brcm,bcm2835-gpio' => FLAG_PI | FLAG_DTOK,
-+	'brcm,bcm2708' => FLAG_PI | FLAG_DTOK | FLAG_270X,
-+	'brcm,bcm2709' => FLAG_PI | FLAG_DTOK | FLAG_270X,
-+	'brcm,bcm2835' => FLAG_PI | FLAG_DTOK | FLAG_283X,
-+	'brcm,bcm2836' => FLAG_PI | FLAG_DTOK | FLAG_283X,
-+	'of_cfs_init' => FLAG_DTOK | FLAG_DDTK,
-+	'vc_cma_init' => FLAG_PI | FLAG_270X,
-+	'vc-mem' => FLAG_PI | FLAG_270X,
-+};
-+
-+my $res = try_extract($kernel_file, $tmpfile1);
-+$res ||= try_decompress('\037\213\010', 'xy',    'gunzip', 0,
-+			$kernel_file, $tmpfile1, $tmpfile2);
-+$res ||= try_decompress('\3757zXZ\000', 'abcde', 'unxz --single-stream', -1,
-+			$kernel_file, $tmpfile1, $tmpfile2);
-+$res ||= try_decompress('BZh',          'xy',    'bunzip2', 0,
-+			$kernel_file, $tmpfile1, $tmpfile2);
-+$res ||= try_decompress('\135\0\0\0',   'xxx',   'unlzma', 0,
-+			$kernel_file, $tmpfile1, $tmpfile2);
-+$res ||= try_decompress('\211\114\132', 'xy',    'lzop -d', 0,
-+			$kernel_file, $tmpfile1, $tmpfile2);
-+$res ||= try_decompress('\002\041\114\030', 'xy',    'lz4 -d', 1,
-+			$kernel_file, $tmpfile1, $tmpfile2);
-+
-+my $append_trailer;
-+my $trailer;
-+my $kver = '?';
-+
-+$append_trailer = 1;
-+
-+if ($res)
-+{
-+    $kver = $res->{'kver'} || '?';
-+    my $flags = $res->{'flags'};
-+    print("Version: $kver\n");
-+
-+    if ($flags & FLAG_PI)
-+    {
-+	$dtok ||= ($flags & FLAG_DTOK) != 0;
-+	$is_270x ||= ($flags & FLAG_270X) != 0;
-+	$is_283x ||= ($flags & FLAG_283X) != 0;
-+	$ddtk ||= ($flags & FLAG_DDTK) != 0;
-+    }
-+    else
-+    {
-+	print ("* This doesn't look like a Raspberry Pi kernel.\n");
-+    }
-+}
-+elsif (!$dtok)
-+{
-+    print ("* Is this a valid kernel?\n");
-+}
-+
-+if ($append_trailer)
-+{
-+    printf("DT: %s\n", $dtok ? "y" : "n");
-+    printf("DDT: %s\n", $ddtk ? "y" : "n");
-+    printf("270x: %s\n", $is_270x ? "y" : "n");
-+    printf("283x: %s\n", $is_283x ? "y" : "n");
-+
-+    my @atoms;
-+
-+    push @atoms, [ $trailer_magic, pack('V', 0) ];
-+    push @atoms, [ 'KVer', $kver ];
-+    push @atoms, [ 'DTOK', pack('V', $dtok) ];
-+    push @atoms, [ 'DDTK', pack('V', $ddtk) ];
-+    push @atoms, [ '270X', pack('V', $is_270x) ];
-+    push @atoms, [ '283X', pack('V', $is_283x) ];
-+    push @atoms, [ '283x', pack('V', $is_283x && !$is_270x) ];
-+
-+    $trailer = pack_trailer(\@atoms);
-+    $atoms[0]->[1] = pack('V', length($trailer));
-+
-+    $trailer = pack_trailer(\@atoms);
-+}
-+
-+my $ofh;
-+my $total_len = 0;
-+
-+if ($out_file eq $kernel_file)
-+{
-+    die "* Failed to open '$out_file' for append\n"
-+	if (!open($ofh, '>>', $out_file));
-+    $total_len = tell($ofh);
-+}
-+else
-+{
-+    die "* Failed to open '$kernel_file'\n"
-+	if (!open(my $ifh, '<', $kernel_file));
-+    die "* Failed to create '$out_file'\n"
-+	if (!open($ofh, '>', $out_file));
-+
-+    my $copybuf;
-+    while (1)
-+    {
-+	my $bytes = sysread($ifh, $copybuf, 64*1024);
-+	last if (!$bytes);
-+	syswrite($ofh, $copybuf, $bytes);
-+	$total_len += $bytes;
-+    }
-+    close($ifh);
-+}
-+
-+if ($trailer)
-+{
-+    # Pad to word-alignment
-+    syswrite($ofh, "\x000\x000\x000", (-$total_len & 0x3));
-+    syswrite($ofh, $trailer);
-+}
-+
-+close($ofh);
-+
-+exit($trailer ? 0 : 1);
-+
-+END {
-+	unlink($tmpfile1) if ($tmpfile1);
-+	unlink($tmpfile2) if ($tmpfile2);
-+}
-+
-+
-+sub usage
-+{
-+	print ("Usage: mkknlimg [--dtok] [--270x] [--283x] <vmlinux|zImage|bzImage> <outfile>\n");
-+	exit(1);
-+}
-+
-+sub try_extract
-+{
-+	my ($knl, $tmp) = @_;
-+
-+	my $ver = `strings "$knl" | grep -a -E "^Linux version [1-9]"`;
-+
-+	return undef if (!$ver);
-+
-+	chomp($ver);
-+
-+	my $res = { 'kver'=>$ver };
-+	$res->{'flags'} = strings_to_flags($knl, $wanted_strings);
-+
-+	return $res;
-+}
-+
-+
-+sub try_decompress
-+{
-+	my ($magic, $subst, $zcat, $idx, $knl, $tmp1, $tmp2) = @_;
-+
-+	my $pos = `tr "$magic\n$subst" "\n$subst=" < "$knl" | grep -abo "^$subst"`;
-+	if ($pos)
-+	{
-+		chomp($pos);
-+		$pos = (split(/[\r\n]+/, $pos))[$idx];
-+		return undef if (!defined($pos));
-+		$pos =~ s/:.*[\r\n]*$//s;
-+		my $cmd = "tail -c+$pos \"$knl\" | $zcat > $tmp2 2> /dev/null";
-+		my $err = (system($cmd) >> 8);
-+		return undef if (($err != 0) && ($err != 2));
-+
-+		return try_extract($tmp2, $tmp1);
-+	}
-+
-+	return undef;
-+}
-+
-+sub strings_to_flags
-+{
-+	my ($knl, $strings) = @_;
-+	my $string_pattern = '^('.join('|', keys(%$strings)).')$';
-+	my $flags = 0;
-+
-+	my @matches = `strings \"$knl\" | grep -E \"$string_pattern\"`;
-+	foreach my $match (@matches)
-+	{
-+	    chomp($match);
-+	    $flags |= $strings->{$match};
-+	}
-+
-+	return $flags;
-+}
-+
-+sub pack_trailer
-+{
-+	my ($atoms) = @_;
-+	my $trailer = pack('VV', 0, 0);
-+	for (my $i = $#$atoms; $i>=0; $i--)
-+	{
-+		my $atom = $atoms->[$i];
-+		$trailer .= pack('a*x!4Va4', $atom->[1], length($atom->[1]), $atom->[0]);
-+	}
-+	return $trailer;
-+}
diff --git a/target/linux/brcm2708/patches-4.14/950-0054-BCM2708-Add-core-Device-Tree-support.patch b/target/linux/brcm2708/patches-4.14/950-0054-BCM2708-Add-core-Device-Tree-support.patch
deleted file mode 100644
index 027fc258d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0054-BCM2708-Add-core-Device-Tree-support.patch
+++ /dev/null
@@ -1,12054 +0,0 @@
-From 89e5d6fae1a69dc41d9f1ba54dd20b2d994e3632 Mon Sep 17 00:00:00 2001
-From: notro <notro@tronnes.org>
-Date: Wed, 9 Jul 2014 14:46:08 +0200
-Subject: [PATCH 054/454] BCM2708: Add core Device Tree support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add the bare minimum needed to boot BCM2708 from a Device Tree.
-
-Signed-off-by: Noralf Tronnes <notro@tronnes.org>
-
-BCM2708: DT: change 'axi' nodename to 'soc'
-
-Change DT node named 'axi' to 'soc' so it matches ARCH_BCM2835.
-The VC4 bootloader fills in certain properties in the 'axi' subtree,
-but since this is part of an upstreaming effort, the name is changed.
-
-Signed-off-by: Noralf Tronnes notro@tronnes.org
-
-BCM2708_DT: Correct length of the peripheral space
-
-Use dts-dirs feature for overlays.
-
-The kernel makefiles have a dts-dirs target that is for vendor subdirectories.
-
-Using this fixes the install_dtbs target, which previously did not install the overlays.
-
-BCM270X_DT: configure I2S DMA channels
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
-
-BCM270X_DT: switch to bcm2835-i2s
-
-I2S soundcard drivers with proper devicetree support (i.e. not linking
-to the cpu_dai/platform via name but to cpu/platform via of_node)
-will work out of the box without any modifications.
-
-When the kernel is compiled without devicetree support the platform
-code will instantiate the bcm2708-i2s driver and I2S soundcard drivers
-will link to it via name, as before.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
-
-SDIO-overlay: add poll_once-boolean parameter
-
-Add paramter to toggle sdio-device-polling
-done every second or once at boot-time.
-
-Signed-off-by: Patrick Boettcher <patrick.boettcher@posteo.de>
-
-BCM270X_DT: Make mmc overlay compatible with current firmware
-
-The original DT overlay logic followed a merge-then-patch procedure,
-i.e. parameters are applied to the loaded overlay before the overlay
-is merged into the base DTB. This sequence has been changed to
-patch-then-merge, in order to support parameterised node names, and
-to protect against bad overlays. As a result, overrides (parameters)
-must only target labels in the overlay, but the overlay can obviously target nodes in the base DTB.
-
-mmc-overlay.dts (that switches back to the original mmc sdcard
-driver) is the only overlay violating that rule, and this patch
-fixes it.
-
-bcm270x_dt: Use the sdhost MMC controller by default
-
-The "mmc" overlay reverts to using the other controller.
-
-squash: Add cprman to dt
-
-BCM270X_DT: Use clk_core for I2C interfaces
-
-BCM270X_DT: Use bcm283x.dtsi, bcm2835.dtsi and bcm2836.dtsi
-
-The mainline Device Tree files are quite close to downstream now.
-Let's use bcm283x.dtsi, bcm2835.dtsi and bcm2836.dtsi as base files
-for our dts files.
-
-Mainline dts files are based on these files:
-
-          bcm2835-rpi.dtsi
-  bcm2835.dtsi    bcm2836.dtsi
-          bcm283x.dtsi
-
-Current downstream are based on these:
-
-  bcm2708.dtsi    bcm2709.dtsi    bcm2710.dtsi
-             bcm2708_common.dtsi
-
-This patch introduces this dependency:
-
-  bcm2708.dtsi    bcm2709.dtsi
-          bcm2708-rpi.dtsi
-          bcm270x.dtsi
-  bcm2835.dtsi    bcm2836.dtsi
-          bcm283x.dtsi
-
-And:
-          bcm2710.dtsi
-          bcm2708-rpi.dtsi
-          bcm270x.dtsi
-          bcm283x.dtsi
-
-bcm270x.dtsi contains the downstream bcm283x.dtsi diff.
-bcm2708-rpi.dtsi is the downstream version of bcm2835-rpi.dtsi.
-
-Other changes:
-- The led node has moved from /soc/leds to /leds. This is not a problem
-  since the label is used to reference it.
-- The clk_osc reg property changes from 6 to 3.
-- The gpu nodes has their interrupt property set in the base file.
-- the clocks label does not point to the /clocks node anymore, but
-  points to the cprman node. This is not a problem since the overlays
-  that use the clock node refer to it directly: target-path = "/clocks";
-- some nodes now have 2 labels since mainline and downstream differs in
-  this respect: cprman/clocks, spi0/spi, gpu/vc4.
-- some nodes doesn't have an explicit status = "okay" since they're not
-  disabled in the base file: watchdog and random.
-- gpiomem doesn't need an explicit status = "okay".
-- bcm2708-rpi-cm.dts got the hpd-gpios property from bcm2708_common.dtsi,
-  it's now set directly in that file.
-- bcm2709-rpi-2-b.dts has the timer node moved from /soc/timer to /timer.
-- Removed clock-frequency property on the bcm{2709,2710}.dtsi timer nodes.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-BCM270X_DT: Use raspberrypi-power to turn on USB power
-
-Use the raspberrypi-power driver to turn on USB power.
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
-
-BCM270X_DT: Add a .dtbo target, use for overlays
-
-Change the filenames and extensions to keep the pre-DDT style of
-overlay (<name>-overlay.dtb) distinct from new ones that use a
-different style of local fixups (<name>.dtbo), and to match other
-platforms.
-
-The RPi firmware uses the DDTK trailer atom to choose which type of
-overlay to use for each kernel.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-BCM270X_DT: Don't generate "linux,phandle" props
-
-The EPAPR standard says to use "phandle" properties to store phandles,
-rather than the deprecated "linux,phandle" version. By default, dtc
-generates both, but adding "-H epapr" causes it to only generate
-"phandle"s, saving some space and clutter.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-BCM270X_DT: Add overlay for enc28j60 on SPI2
-
-Works on SPI2 for compute module
-
-BCM270X_DT: Add midi-uart0 overlay
-
-MIDI requires 31.25kbaud, a baudrate unsupported by Linux. The
-midi-uart0 overlay configures uart0 (ttyAMA0) to use a fake clock
-so that requesting 38.4kbaud actually gets 31.25kbaud.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-BCM270X_DT: Add i2c-sensor overlay
-
-The i2c-sensor overlay is a container for various pressure and
-temperature sensors, currently bmp085 and bmp280. The standalone
-bmp085_i2c-sensor overlay is now deprecated.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-BCM270X_DT: overlays/*-overlay.dtb -> overlays/*.dtbo (#1752)
-
-We now create overlays as .dtbo files.
-
-build: support for .dtbo files for dtb overlays
-
-Kernel 4.4.6+ on RaspberryPi support .dtbo files for overlays, instead of .dtb.
-Patch the kernel, which has faulty rules to generate .dtbo the way yocto does
-
-Signed-off-by: Herve Jourdain <herve.jourdain@neuf.fr>
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-
-BCM270X: Drop position requirement for CMA in VC4 overlay.
-
-No longer necessary since 2aefcd576195a739a7a256099571c9c4a401005f,
-and will probably let peeople that want to choose a larger CMA
-allocation (particularly on pi0/1).
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-
-BCM270X_DT: RPi Device Tree tidy
-
-Use the upstream sdhost node, add thermal-zones, and factor out some
-common elements.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/Makefile                             |    2 +
- arch/arm/boot/.gitignore                      |    1 +
- arch/arm/boot/dts/Makefile                    |   20 +
- arch/arm/boot/dts/bcm2708-rpi-0-w.dts         |  165 ++
- arch/arm/boot/dts/bcm2708-rpi-b-plus.dts      |  122 ++
- arch/arm/boot/dts/bcm2708-rpi-b.dts           |  112 ++
- arch/arm/boot/dts/bcm2708-rpi-cm.dts          |   95 +
- arch/arm/boot/dts/bcm2708-rpi-cm.dtsi         |   17 +
- arch/arm/boot/dts/bcm2708-rpi.dtsi            |  162 ++
- arch/arm/boot/dts/bcm2708.dtsi                |   20 +
- arch/arm/boot/dts/bcm2709-rpi-2-b.dts         |  122 ++
- arch/arm/boot/dts/bcm2709.dtsi                |   22 +
- arch/arm/boot/dts/bcm270x.dtsi                |  181 ++
- arch/arm/boot/dts/bcm2710-rpi-3-b.dts         |  194 ++
- arch/arm/boot/dts/bcm2710-rpi-cm3.dts         |  129 ++
- arch/arm/boot/dts/bcm2710.dtsi                |   32 +
- arch/arm/boot/dts/overlays/Makefile           |  128 ++
- arch/arm/boot/dts/overlays/README             | 1678 +++++++++++++++++
- .../dts/overlays/adau1977-adc-overlay.dts     |   40 +
- .../dts/overlays/adau7002-simple-overlay.dts  |   52 +
- .../arm/boot/dts/overlays/ads1015-overlay.dts |   98 +
- .../arm/boot/dts/overlays/ads1115-overlay.dts |  103 +
- .../arm/boot/dts/overlays/ads7846-overlay.dts |   89 +
- .../overlays/akkordion-iqdacplus-overlay.dts  |   49 +
- .../allo-boss-dac-pcm512x-audio-overlay.dts   |   59 +
- .../dts/overlays/allo-digione-overlay.dts     |   44 +
- .../allo-piano-dac-pcm512x-audio-overlay.dts  |   54 +
- ...o-piano-dac-plus-pcm512x-audio-overlay.dts |   55 +
- .../boot/dts/overlays/at86rf233-overlay.dts   |   57 +
- .../overlays/audioinjector-addons-overlay.dts |   55 +
- .../audioinjector-wm8731-audio-overlay.dts    |   39 +
- .../boot/dts/overlays/audremap-overlay.dts    |   19 +
- .../overlays/bmp085_i2c-sensor-overlay.dts    |   23 +
- arch/arm/boot/dts/overlays/dht11-overlay.dts  |   39 +
- .../dts/overlays/dionaudio-loco-overlay.dts   |   39 +
- .../overlays/dionaudio-loco-v2-overlay.dts    |   49 +
- arch/arm/boot/dts/overlays/dpi18-overlay.dts  |   31 +
- arch/arm/boot/dts/overlays/dpi24-overlay.dts  |   31 +
- .../arm/boot/dts/overlays/dwc-otg-overlay.dts |   20 +
- arch/arm/boot/dts/overlays/dwc2-overlay.dts   |   28 +
- .../boot/dts/overlays/enc28j60-overlay.dts    |   53 +
- .../dts/overlays/enc28j60-spi2-overlay.dts    |   47 +
- .../boot/dts/overlays/fe-pi-audio-overlay.dts |   70 +
- arch/arm/boot/dts/overlays/goodix-overlay.dts |   46 +
- .../googlevoicehat-soundcard-overlay.dts      |   49 +
- .../arm/boot/dts/overlays/gpio-ir-overlay.dts |   44 +
- .../boot/dts/overlays/gpio-ir-tx-overlay.dts  |   34 +
- .../dts/overlays/gpio-poweroff-overlay.dts    |   34 +
- .../dts/overlays/gpio-shutdown-overlay.dts    |   80 +
- .../dts/overlays/hifiberry-amp-overlay.dts    |   39 +
- .../dts/overlays/hifiberry-dac-overlay.dts    |   34 +
- .../overlays/hifiberry-dacplus-overlay.dts    |   59 +
- .../dts/overlays/hifiberry-digi-overlay.dts   |   41 +
- .../overlays/hifiberry-digi-pro-overlay.dts   |   43 +
- arch/arm/boot/dts/overlays/hy28a-overlay.dts  |   93 +
- arch/arm/boot/dts/overlays/hy28b-overlay.dts  |  148 ++
- .../boot/dts/overlays/i2c-bcm2708-overlay.dts |   13 +
- .../boot/dts/overlays/i2c-gpio-overlay.dts    |   43 +
- .../arm/boot/dts/overlays/i2c-mux-overlay.dts |  139 ++
- .../dts/overlays/i2c-pwm-pca9685a-overlay.dts |   26 +
- .../dts/overlays/i2c-rtc-gpio-overlay.dts     |  183 ++
- .../arm/boot/dts/overlays/i2c-rtc-overlay.dts |  181 ++
- .../boot/dts/overlays/i2c-sensor-overlay.dts  |  206 ++
- .../dts/overlays/i2c0-bcm2708-overlay.dts     |   61 +
- .../dts/overlays/i2c1-bcm2708-overlay.dts     |   34 +
- .../dts/overlays/i2s-gpio28-31-overlay.dts    |   18 +
- .../boot/dts/overlays/iqaudio-dac-overlay.dts |   46 +
- .../dts/overlays/iqaudio-dacplus-overlay.dts  |   49 +
- .../iqaudio-digi-wm8804-audio-overlay.dts     |   47 +
- .../dts/overlays/justboom-dac-overlay.dts     |   46 +
- .../dts/overlays/justboom-digi-overlay.dts    |   41 +
- .../boot/dts/overlays/lirc-rpi-overlay.dts    |   57 +
- .../boot/dts/overlays/mcp23017-overlay.dts    |   54 +
- .../boot/dts/overlays/mcp23s17-overlay.dts    |  732 +++++++
- .../dts/overlays/mcp2515-can0-overlay.dts     |   73 +
- .../dts/overlays/mcp2515-can1-overlay.dts     |   73 +
- .../arm/boot/dts/overlays/mcp3008-overlay.dts |  205 ++
- .../boot/dts/overlays/midi-uart0-overlay.dts  |   36 +
- .../boot/dts/overlays/midi-uart1-overlay.dts  |   43 +
- arch/arm/boot/dts/overlays/mmc-overlay.dts    |   39 +
- .../arm/boot/dts/overlays/mpu6050-overlay.dts |   28 +
- .../arm/boot/dts/overlays/mz61581-overlay.dts |  117 ++
- .../arm/boot/dts/overlays/papirus-overlay.dts |   89 +
- .../boot/dts/overlays/pi3-act-led-overlay.dts |   27 +
- .../dts/overlays/pi3-disable-bt-overlay.dts   |   46 +
- .../dts/overlays/pi3-disable-wifi-overlay.dts |   13 +
- .../dts/overlays/pi3-miniuart-bt-overlay.dts  |   74 +
- .../boot/dts/overlays/piscreen-overlay.dts    |  102 +
- .../boot/dts/overlays/piscreen2r-overlay.dts  |  106 ++
- .../arm/boot/dts/overlays/pisound-overlay.dts |  120 ++
- .../arm/boot/dts/overlays/pitft22-overlay.dts |   69 +
- .../overlays/pitft28-capacitive-overlay.dts   |   91 +
- .../overlays/pitft28-resistive-overlay.dts    |  121 ++
- .../overlays/pitft35-resistive-overlay.dts    |  121 ++
- .../boot/dts/overlays/pps-gpio-overlay.dts    |   35 +
- .../boot/dts/overlays/pwm-2chan-overlay.dts   |   47 +
- .../boot/dts/overlays/pwm-ir-tx-overlay.dts   |   40 +
- arch/arm/boot/dts/overlays/pwm-overlay.dts    |   43 +
- .../arm/boot/dts/overlays/qca7000-overlay.dts |   52 +
- .../boot/dts/overlays/raspidac3-overlay.dts   |   49 +
- .../dts/overlays/rotary-encoder-overlay.dts   |   43 +
- .../dts/overlays/rpi-backlight-overlay.dts    |   21 +
- .../overlays/rpi-cirrus-wm5102-overlay.dts    |  146 ++
- .../arm/boot/dts/overlays/rpi-dac-overlay.dts |   34 +
- .../boot/dts/overlays/rpi-display-overlay.dts |   89 +
- .../boot/dts/overlays/rpi-ft5406-overlay.dts  |   30 +
- .../boot/dts/overlays/rpi-proto-overlay.dts   |   39 +
- .../boot/dts/overlays/rpi-sense-overlay.dts   |   47 +
- arch/arm/boot/dts/overlays/rpi-tv-overlay.dts |   31 +
- .../rra-digidac1-wm8741-audio-overlay.dts     |   49 +
- .../dts/overlays/sc16is750-i2c-overlay.dts    |   37 +
- .../dts/overlays/sc16is752-spi1-overlay.dts   |   61 +
- arch/arm/boot/dts/overlays/sdhost-overlay.dts |   31 +
- .../boot/dts/overlays/sdio-1bit-overlay.dts   |   37 +
- arch/arm/boot/dts/overlays/sdio-overlay.dts   |   37 +
- .../arm/boot/dts/overlays/sdtweak-overlay.dts |   23 +
- .../arm/boot/dts/overlays/smi-dev-overlay.dts |   18 +
- .../boot/dts/overlays/smi-nand-overlay.dts    |   69 +
- arch/arm/boot/dts/overlays/smi-overlay.dts    |   37 +
- .../dts/overlays/spi-gpio35-39-overlay.dts    |   31 +
- .../arm/boot/dts/overlays/spi-rtc-overlay.dts |   33 +
- .../arm/boot/dts/overlays/spi0-cs-overlay.dts |   29 +
- .../boot/dts/overlays/spi0-hw-cs-overlay.dts  |   26 +
- .../boot/dts/overlays/spi1-1cs-overlay.dts    |   57 +
- .../boot/dts/overlays/spi1-2cs-overlay.dts    |   69 +
- .../boot/dts/overlays/spi1-3cs-overlay.dts    |   81 +
- .../boot/dts/overlays/spi2-1cs-overlay.dts    |   57 +
- .../boot/dts/overlays/spi2-2cs-overlay.dts    |   69 +
- .../boot/dts/overlays/spi2-3cs-overlay.dts    |   81 +
- .../boot/dts/overlays/tinylcd35-overlay.dts   |  224 +++
- arch/arm/boot/dts/overlays/uart1-overlay.dts  |   38 +
- .../dts/overlays/vc4-fkms-v3d-overlay.dts     |   89 +
- .../boot/dts/overlays/vc4-kms-v3d-overlay.dts |  151 ++
- arch/arm/boot/dts/overlays/vga666-overlay.dts |   30 +
- .../arm/boot/dts/overlays/w1-gpio-overlay.dts |   41 +
- .../dts/overlays/w1-gpio-pullup-overlay.dts   |   43 +
- .../arm/boot/dts/overlays/wittypi-overlay.dts |   44 +
- scripts/Makefile.dtbinst                      |    8 +-
- scripts/Makefile.lib                          |   11 +
- 139 files changed, 11113 insertions(+), 2 deletions(-)
- create mode 100644 arch/arm/boot/dts/bcm2708-rpi-0-w.dts
- create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
- create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b.dts
- create mode 100644 arch/arm/boot/dts/bcm2708-rpi-cm.dts
- create mode 100644 arch/arm/boot/dts/bcm2708-rpi-cm.dtsi
- create mode 100644 arch/arm/boot/dts/bcm2708-rpi.dtsi
- create mode 100644 arch/arm/boot/dts/bcm2708.dtsi
- create mode 100644 arch/arm/boot/dts/bcm2709-rpi-2-b.dts
- create mode 100644 arch/arm/boot/dts/bcm2709.dtsi
- create mode 100644 arch/arm/boot/dts/bcm270x.dtsi
- create mode 100644 arch/arm/boot/dts/bcm2710-rpi-3-b.dts
- create mode 100644 arch/arm/boot/dts/bcm2710-rpi-cm3.dts
- create mode 100644 arch/arm/boot/dts/bcm2710.dtsi
- create mode 100644 arch/arm/boot/dts/overlays/Makefile
- create mode 100644 arch/arm/boot/dts/overlays/README
- create mode 100644 arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/ads1015-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/ads1115-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/ads7846-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/allo-digione-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/at86rf233-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/audremap-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/dht11-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/dpi18-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/dpi24-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/dwc-otg-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/dwc2-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/enc28j60-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/goodix-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/gpio-ir-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/hy28a-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/hy28b-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c-mux-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c0-bcm2708-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2c1-bcm2708-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/justboom-dac-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/justboom-digi-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/mcp23017-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/mcp23s17-overlay.dts
- create mode 100755 arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts
- create mode 100755 arch/arm/boot/dts/overlays/mcp3008-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/midi-uart0-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/midi-uart1-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/mmc-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/mpu6050-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/mz61581-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/papirus-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pi3-act-led-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pi3-disable-bt-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pi3-disable-wifi-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pi3-miniuart-bt-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/piscreen-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/piscreen2r-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pisound-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pitft22-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pps-gpio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/pwm-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/qca7000-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/raspidac3-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rpi-dac-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rpi-display-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rpi-proto-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rpi-sense-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rpi-tv-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/sdhost-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/sdio-1bit-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/sdio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/sdtweak-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/smi-dev-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/smi-nand-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/smi-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi-rtc-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi0-cs-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi0-hw-cs-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/tinylcd35-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/uart1-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/vga666-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/wittypi-overlay.dts
-
---- a/arch/arm/Makefile
-+++ b/arch/arm/Makefile
-@@ -341,6 +341,8 @@ $(INSTALL_TARGETS):
- 
- %.dtb: | scripts
- 	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
-+%.dtbo: | scripts
-+	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
- 
- PHONY += dtbs dtbs_install
- 
---- a/arch/arm/boot/.gitignore
-+++ b/arch/arm/boot/.gitignore
-@@ -3,3 +3,4 @@ zImage
- xipImage
- bootpImage
- uImage
-+*.dtb*
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -1,6 +1,15 @@
- # SPDX-License-Identifier: GPL-2.0
- ifeq ($(CONFIG_OF),y)
- 
-+dtb-$(CONFIG_ARCH_BCM2835) += \
-+	bcm2708-rpi-b.dtb \
-+	bcm2708-rpi-b-plus.dtb \
-+	bcm2708-rpi-cm.dtb \
-+	bcm2708-rpi-0-w.dtb \
-+	bcm2709-rpi-2-b.dtb \
-+	bcm2710-rpi-3-b.dtb \
-+	bcm2710-rpi-cm3.dtb
-+
- dtb-$(CONFIG_ARCH_ALPINE) += \
- 	alpine-db.dtb
- dtb-$(CONFIG_MACH_ARTPEC6) += \
-@@ -1069,10 +1078,21 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dt
- dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \
- 	aspeed-bmc-opp-romulus.dtb \
- 	aspeed-ast2500-evb.dtb
-+
-+targets += dtbs dtbs_install
-+targets += $(dtb-y)
-+
- endif
- 
- dtstree		:= $(srctree)/$(src)
- dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
- 
- always		:= $(dtb-y)
-+subdir-y	:= overlays
- clean-files	:= *.dtb
-+
-+# Enable fixups to support overlays on BCM2835 platforms
-+ifeq ($(CONFIG_ARCH_BCM2835),y)
-+	DTC_FLAGS ?= -@ -H epapr
-+	dts-dirs += overlays
-+endif
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2708-rpi-0-w.dts
-@@ -0,0 +1,165 @@
-+/dts-v1/;
-+
-+#include "bcm2708.dtsi"
-+
-+/ {
-+	model = "Raspberry Pi Zero W";
-+
-+	chosen {
-+		bootargs = "8250.nr_uarts=1";
-+	};
-+
-+	aliases {
-+		serial0 = &uart1;
-+		serial1 = &uart0;
-+	};
-+};
-+
-+&gpio {
-+	spi0_pins: spi0_pins {
-+		brcm,pins = <9 10 11>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	spi0_cs_pins: spi0_cs_pins {
-+		brcm,pins = <8 7>;
-+		brcm,function = <1>; /* output */
-+	};
-+
-+	i2c0_pins: i2c0 {
-+		brcm,pins = <0 1>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2c1_pins: i2c1 {
-+		brcm,pins = <2 3>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2s_pins: i2s {
-+		brcm,pins = <18 19 20 21>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	sdio_pins: sdio_pins {
-+		brcm,pins = <34 35 36 37 38 39>;
-+		brcm,function = <7>; /* ALT3 = SD1 */
-+		brcm,pull = <0 2 2 2 2 2>;
-+	};
-+
-+	bt_pins: bt_pins {
-+		brcm,pins = <43>;
-+		brcm,function = <4>; /* alt0:GPCLK2 */
-+		brcm,pull = <0>; /* none */
-+	};
-+
-+	uart0_pins: uart0_pins {
-+		brcm,pins = <30 31 32 33>;
-+		brcm,function = <7>; /* alt3=UART0 */
-+		brcm,pull = <2 0 0 2>; /* up none none up */
-+	};
-+
-+	uart1_pins: uart1_pins {
-+		brcm,pins;
-+		brcm,function;
-+		brcm,pull;
-+	};
-+
-+	audio_pins: audio_pins {
-+		brcm,pins = <>;
-+		brcm,function = <>;
-+	};
-+};
-+
-+&mmc {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdio_pins>;
-+	non-removable;
-+	bus-width = <4>;
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_pins &bt_pins>;
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
-+	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+
-+	spidev0: spidev@0{
-+		compatible = "spidev";
-+		reg = <0>;	/* CE0 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+
-+	spidev1: spidev@1{
-+		compatible = "spidev";
-+		reg = <1>;	/* CE1 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c2 {
-+	clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+	#sound-dai-cells = <0>;
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&random {
-+	status = "okay";
-+};
-+
-+&leds {
-+	act_led: act {
-+		label = "led0";
-+		linux,default-trigger = "mmc0";
-+		gpios = <&gpio 47 0>;
-+	};
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
-+};
-+
-+&audio {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&audio_pins>;
-+};
-+
-+/ {
-+	__overrides__ {
-+		act_led_gpio = <&act_led>,"gpios:4";
-+		act_led_activelow = <&act_led>,"gpios:8";
-+		act_led_trigger = <&act_led>,"linux,default-trigger";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
-@@ -0,0 +1,122 @@
-+/dts-v1/;
-+
-+#include "bcm2708.dtsi"
-+#include "bcm283x-rpi-smsc9514.dtsi"
-+
-+/ {
-+	model = "Raspberry Pi Model B+";
-+};
-+
-+&gpio {
-+	spi0_pins: spi0_pins {
-+		brcm,pins = <9 10 11>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	spi0_cs_pins: spi0_cs_pins {
-+		brcm,pins = <8 7>;
-+		brcm,function = <1>; /* output */
-+	};
-+
-+	i2c0_pins: i2c0 {
-+		brcm,pins = <0 1>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2c1_pins: i2c1 {
-+		brcm,pins = <2 3>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2s_pins: i2s {
-+		brcm,pins = <18 19 20 21>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	audio_pins: audio_pins {
-+		brcm,pins = <40 45>;
-+		brcm,function = <4>;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
-+	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+
-+	spidev0: spidev@0{
-+		compatible = "spidev";
-+		reg = <0>;	/* CE0 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+
-+	spidev1: spidev@1{
-+		compatible = "spidev";
-+		reg = <1>;	/* CE1 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c2 {
-+	clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+	act_led: act {
-+		label = "led0";
-+		linux,default-trigger = "mmc0";
-+		gpios = <&gpio 47 0>;
-+	};
-+
-+	pwr_led: pwr {
-+		label = "led1";
-+		linux,default-trigger = "input";
-+		gpios = <&gpio 35 0>;
-+	};
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
-+};
-+
-+&audio {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&audio_pins>;
-+};
-+
-+/ {
-+	__overrides__ {
-+		act_led_gpio = <&act_led>,"gpios:4";
-+		act_led_activelow = <&act_led>,"gpios:8";
-+		act_led_trigger = <&act_led>,"linux,default-trigger";
-+
-+		pwr_led_gpio = <&pwr_led>,"gpios:4";
-+		pwr_led_activelow = <&pwr_led>,"gpios:8";
-+		pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts
-@@ -0,0 +1,112 @@
-+/dts-v1/;
-+
-+#include "bcm2708.dtsi"
-+#include "bcm283x-rpi-smsc9512.dtsi"
-+
-+/ {
-+	model = "Raspberry Pi Model B";
-+};
-+
-+&gpio {
-+	spi0_pins: spi0_pins {
-+		brcm,pins = <9 10 11>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	spi0_cs_pins: spi0_cs_pins {
-+		brcm,pins = <8 7>;
-+		brcm,function = <1>; /* output */
-+	};
-+
-+	i2c0_pins: i2c0 {
-+		brcm,pins = <0 1>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2c1_pins: i2c1 {
-+		brcm,pins = <2 3>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2s_pins: i2s {
-+		brcm,pins = <28 29 30 31>;
-+		brcm,function = <6>; /* alt2 */
-+	};
-+
-+	audio_pins: audio_pins {
-+		brcm,pins = <40 45>;
-+		brcm,function = <4>;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
-+	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+
-+	spidev0: spidev@0{
-+		compatible = "spidev";
-+		reg = <0>;	/* CE0 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+
-+	spidev1: spidev@1{
-+		compatible = "spidev";
-+		reg = <1>;	/* CE1 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c2 {
-+	clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+	act_led: act {
-+		label = "led0";
-+		linux,default-trigger = "mmc0";
-+		gpios = <&gpio 16 1>;
-+	};
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
-+};
-+
-+&audio {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&audio_pins>;
-+};
-+
-+/ {
-+	__overrides__ {
-+		act_led_gpio = <&act_led>,"gpios:4";
-+		act_led_activelow = <&act_led>,"gpios:8";
-+		act_led_trigger = <&act_led>,"linux,default-trigger";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts
-@@ -0,0 +1,95 @@
-+/dts-v1/;
-+
-+#include "bcm2708-rpi-cm.dtsi"
-+
-+/ {
-+	model = "Raspberry Pi Compute Module";
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&gpio {
-+	spi0_pins: spi0_pins {
-+		brcm,pins = <9 10 11>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	spi0_cs_pins: spi0_cs_pins {
-+		brcm,pins = <8 7>;
-+		brcm,function = <1>; /* output */
-+	};
-+
-+	i2c0_pins: i2c0 {
-+		brcm,pins = <0 1>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2c1_pins: i2c1 {
-+		brcm,pins = <2 3>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2s_pins: i2s {
-+		brcm,pins = <18 19 20 21>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	audio_pins: audio_pins {
-+		brcm,pins;
-+		brcm,function;
-+	};
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
-+	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+
-+	spidev0: spidev@0{
-+		compatible = "spidev";
-+		reg = <0>;	/* CE0 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+
-+	spidev1: spidev@1{
-+		compatible = "spidev";
-+		reg = <1>;	/* CE1 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c2 {
-+	clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&audio {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&audio_pins>;
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi
-@@ -0,0 +1,17 @@
-+#include "bcm2708.dtsi"
-+
-+&leds {
-+	act_led: act {
-+		label = "led0";
-+		linux,default-trigger = "mmc0";
-+		gpios = <&gpio 47 0>;
-+	};
-+};
-+
-+/ {
-+	__overrides__ {
-+		act_led_gpio = <&act_led>,"gpios:4";
-+		act_led_activelow = <&act_led>,"gpios:8";
-+		act_led_trigger = <&act_led>,"linux,default-trigger";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2708-rpi.dtsi
-@@ -0,0 +1,162 @@
-+/* Downstream version of bcm2835-rpi.dtsi */
-+
-+#include <dt-bindings/power/raspberrypi-power.h>
-+
-+/ {
-+	memory {
-+		device_type = "memory";
-+		reg = <0x0 0x0>;
-+	};
-+
-+	aliases {
-+		audio = &audio;
-+		aux = &aux;
-+		sound = &sound;
-+		soc = &soc;
-+		dma = &dma;
-+		intc = &intc;
-+		watchdog = &watchdog;
-+		random = &random;
-+		mailbox = &mailbox;
-+		gpio = &gpio;
-+		uart0 = &uart0;
-+		sdhost = &sdhost;
-+		mmc0 = &sdhost;
-+		i2s = &i2s;
-+		spi0 = &spi0;
-+		i2c0 = &i2c0;
-+		uart1 = &uart1;
-+		spi1 = &spi1;
-+		spi2 = &spi2;
-+		mmc = &mmc;
-+		mmc1 = &mmc;
-+		i2c1 = &i2c1;
-+		i2c2 = &i2c2;
-+		usb = &usb;
-+		leds = &leds;
-+		fb = &fb;
-+		vchiq = &vchiq;
-+		thermal = &thermal;
-+		axiperf = &axiperf;
-+	};
-+
-+	leds: leds {
-+		compatible = "gpio-leds";
-+	};
-+
-+	soc {
-+		gpiomem {
-+			compatible = "brcm,bcm2835-gpiomem";
-+			reg = <0x7e200000 0x1000>;
-+		};
-+
-+		firmware: firmware {
-+			compatible = "raspberrypi,bcm2835-firmware";
-+			mboxes = <&mailbox>;
-+		};
-+
-+		power: power {
-+			compatible = "raspberrypi,bcm2835-power";
-+			firmware = <&firmware>;
-+			#power-domain-cells = <1>;
-+		};
-+
-+		fb: fb {
-+			compatible = "brcm,bcm2708-fb";
-+			firmware = <&firmware>;
-+			status = "disabled";
-+		};
-+
-+		vchiq: vchiq {
-+			compatible = "brcm,bcm2835-vchiq";
-+			reg = <0x7e00b840 0xf>;
-+			interrupts = <0 2>;
-+			cache-line-size = <32>;
-+			firmware = <&firmware>;
-+		};
-+
-+		vcsm: vcsm {
-+			compatible = "raspberrypi,bcm2835-vcsm";
-+			firmware = <&firmware>;
-+			status = "okay";
-+		};
-+
-+		thermal: thermal@7e212000 {
-+			#thermal-sensor-cells = <0>;
-+			status = "okay";
-+		};
-+
-+		/* Onboard audio */
-+		audio: audio {
-+			compatible = "brcm,bcm2835-audio";
-+			brcm,pwm-channels = <8>;
-+			status = "disabled";
-+		};
-+
-+		/* External sound card */
-+		sound: sound {
-+			status = "disabled";
-+		};
-+	};
-+
-+	__overrides__ {
-+		cache_line_size = <&vchiq>, "cache-line-size:0";
-+
-+		uart0 = <&uart0>,"status";
-+		uart1 = <&uart1>,"status";
-+		i2s = <&i2s>,"status";
-+		spi = <&spi0>,"status";
-+		i2c0 = <&i2c0>,"status";
-+		i2c1 = <&i2c1>,"status";
-+		i2c2_iknowwhatimdoing = <&i2c2>,"status";
-+		i2c0_baudrate = <&i2c0>,"clock-frequency:0";
-+		i2c1_baudrate = <&i2c1>,"clock-frequency:0";
-+		i2c2_baudrate = <&i2c2>,"clock-frequency:0";
-+
-+		audio = <&audio>,"status";
-+		watchdog = <&watchdog>,"status";
-+		random = <&random>,"status";
-+		sd_overclock = <&sdhost>,"brcm,overclock-50:0";
-+		sd_force_pio = <&sdhost>,"brcm,force-pio?";
-+		sd_pio_limit = <&sdhost>,"brcm,pio-limit:0";
-+		sd_debug     = <&sdhost>,"brcm,debug";
-+		axiperf      = <&axiperf>,"status";
-+	};
-+};
-+
-+&dma {
-+	brcm,dma-channel-mask = <0x7f34>;
-+};
-+
-+&hdmi {
-+	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-+};
-+
-+&usb {
-+	power-domains = <&power RPI_POWER_DOMAIN_USB>;
-+};
-+
-+&clocks {
-+	firmware = <&firmware>;
-+};
-+
-+sdhost_pins: &sdhost_gpio48 {
-+	/* Add alias */
-+};
-+
-+&sdhost {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdhost_gpio48>;
-+	bus-width = <4>;
-+	brcm,overclock-50 = <0>;
-+	brcm,pio-limit = <1>;
-+	status = "okay";
-+};
-+
-+&fb {
-+	status = "okay";
-+};
-+
-+&cpu_thermal {
-+	/delete-node/ trips;
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2708.dtsi
-@@ -0,0 +1,20 @@
-+#include "bcm2835.dtsi"
-+#include "bcm270x.dtsi"
-+#include "bcm2708-rpi.dtsi"
-+
-+/ {
-+	soc {
-+		timer@7e003000 {
-+			compatible = "brcm,bcm2835-system-timer";
-+			reg = <0x7e003000 0x1000>;
-+			interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
-+			clock-frequency = <1000000>;
-+		};
-+	};
-+
-+	/delete-node/ cpus;
-+
-+	__overrides__ {
-+		arm_freq;
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
-@@ -0,0 +1,122 @@
-+/dts-v1/;
-+
-+#include "bcm2709.dtsi"
-+#include "bcm283x-rpi-smsc9514.dtsi"
-+
-+/ {
-+	model = "Raspberry Pi 2 Model B";
-+};
-+
-+&gpio {
-+	spi0_pins: spi0_pins {
-+		brcm,pins = <9 10 11>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	spi0_cs_pins: spi0_cs_pins {
-+		brcm,pins = <8 7>;
-+		brcm,function = <1>; /* output */
-+	};
-+
-+	i2c0_pins: i2c0 {
-+		brcm,pins = <0 1>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2c1_pins: i2c1 {
-+		brcm,pins = <2 3>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2s_pins: i2s {
-+		brcm,pins = <18 19 20 21>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	audio_pins: audio_pins {
-+		brcm,pins = <40 45>;
-+		brcm,function = <4>;
-+	};
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
-+	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+
-+	spidev0: spidev@0{
-+		compatible = "spidev";
-+		reg = <0>;	/* CE0 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+
-+	spidev1: spidev@1{
-+		compatible = "spidev";
-+		reg = <1>;	/* CE1 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c2 {
-+	clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+	act_led: act {
-+		label = "led0";
-+		linux,default-trigger = "mmc0";
-+		gpios = <&gpio 47 0>;
-+	};
-+
-+	pwr_led: pwr {
-+		label = "led1";
-+		linux,default-trigger = "input";
-+		gpios = <&gpio 35 0>;
-+	};
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
-+};
-+
-+&audio {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&audio_pins>;
-+};
-+
-+/ {
-+	__overrides__ {
-+		act_led_gpio = <&act_led>,"gpios:4";
-+		act_led_activelow = <&act_led>,"gpios:8";
-+		act_led_trigger = <&act_led>,"linux,default-trigger";
-+
-+		pwr_led_gpio = <&pwr_led>,"gpios:4";
-+		pwr_led_activelow = <&pwr_led>,"gpios:8";
-+		pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2709.dtsi
-@@ -0,0 +1,22 @@
-+#include "bcm2836.dtsi"
-+#include "bcm270x.dtsi"
-+#include "bcm2708-rpi.dtsi"
-+
-+/ {
-+	soc {
-+		ranges = <0x7e000000 0x3f000000 0x01000000>,
-+		         <0x40000000 0x40000000 0x00040000>;
-+
-+		syscon@40000000 {
-+			compatible = "brcm,bcm2836-arm-local", "syscon";
-+			reg = <0x40000000 0x100>;
-+		};
-+	};
-+
-+	__overrides__ {
-+		arm_freq = <&v7_cpu0>, "clock-frequency:0",
-+			   <&v7_cpu1>, "clock-frequency:0",
-+			   <&v7_cpu2>, "clock-frequency:0",
-+			   <&v7_cpu3>, "clock-frequency:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm270x.dtsi
-@@ -0,0 +1,181 @@
-+/* Downstream bcm283x.dtsi diff */
-+#include "dt-bindings/power/raspberrypi-power.h"
-+
-+/ {
-+	chosen {
-+		bootargs = "";
-+	};
-+
-+	soc: soc {
-+
-+		/delete-node/ timer@7e003000;
-+
-+		watchdog: watchdog@7e100000 {
-+			/* Add alias */
-+		};
-+
-+		cprman: cprman@7e101000 {
-+			/* Add alias */
-+		};
-+
-+		random: rng@7e104000 {
-+			/* Add alias */
-+		};
-+
-+		gpio@7e200000 { /* gpio */
-+			interrupts = <2 17>, <2 18>;
-+		};
-+
-+		serial@7e201000 { /* uart0 */
-+			/* Enable CTS bug workaround */
-+			cts-event-workaround;
-+		};
-+
-+		i2s@7e203000 { /* i2s */
-+			#sound-dai-cells = <0>;
-+			reg = <0x7e203000 0x24>;
-+			clocks = <&clocks BCM2835_CLOCK_PCM>;
-+		};
-+
-+		spi0: spi@7e204000 {
-+			/* Add alias */
-+			dmas = <&dma 6>, <&dma 7>;
-+			dma-names = "tx", "rx";
-+		};
-+
-+		pixelvalve0: pixelvalve@7e206000 {
-+			/* Add alias */
-+			status = "disabled";
-+		};
-+
-+		pixelvalve1: pixelvalve@7e207000 {
-+			/* Add alias */
-+			status = "disabled";
-+		};
-+
-+		dpi: dpi@7e208000 {
-+			compatible = "brcm,bcm2835-dpi";
-+			reg = <0x7e208000 0x8c>;
-+			clocks = <&clocks BCM2835_CLOCK_VPU>,
-+				 <&clocks BCM2835_CLOCK_DPI>;
-+			clock-names = "core", "pixel";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+		};
-+
-+		/delete-node/ sdhci@7e300000;
-+
-+		mmc: mmc@7e300000 {
-+			compatible = "brcm,bcm2835-mmc";
-+			reg = <0x7e300000 0x100>;
-+			interrupts = <2 30>;
-+			clocks = <&clocks BCM2835_CLOCK_EMMC>;
-+			dmas = <&dma 11>;
-+			dma-names = "rx-tx";
-+			brcm,overclock-50 = <0>;
-+			status = "disabled";
-+		};
-+
-+		hvs: hvs@7e400000 {
-+			/* Add alias */
-+			status = "disabled";
-+		};
-+
-+		firmwarekms: firmwarekms@7e600000 {
-+			compatible = "raspberrypi,rpi-firmware-kms";
-+			/* SMI interrupt reg */
-+			reg = <0x7e600000 0x100>;
-+			interrupts = <2 16>;
-+			brcm,firmware = <&firmware>;
-+			status = "disabled";
-+		};
-+
-+		smi: smi@7e600000 {
-+			compatible = "brcm,bcm2835-smi";
-+			reg = <0x7e600000 0x100>;
-+			interrupts = <2 16>;
-+			clocks = <&clocks BCM2835_CLOCK_SMI>;
-+			assigned-clocks = <&cprman BCM2835_CLOCK_SMI>;
-+			assigned-clock-rates = <125000000>;
-+			dmas = <&dma 4>;
-+			dma-names = "rx-tx";
-+			status = "disabled";
-+		};
-+
-+		pixelvalve2: pixelvalve@7e807000 {
-+			/* Add alias */
-+			status = "disabled";
-+		};
-+
-+		hdmi@7e902000 { /* hdmi */
-+			status = "disabled";
-+		};
-+
-+		usb@7e980000 { /* usb */
-+			compatible = "brcm,bcm2708-usb";
-+			reg = <0x7e980000 0x10000>,
-+			      <0x7e006000 0x1000>;
-+			interrupts = <2 0>,
-+				     <1 9>;
-+		};
-+
-+		v3d@7ec00000 { /* vd3 */
-+			compatible = "brcm,vc4-v3d";
-+			power-domains = <&power RPI_POWER_DOMAIN_V3D>;
-+			status = "disabled";
-+		};
-+
-+		gpu: gpu {
-+			/* Add alias */
-+			status = "disabled";
-+		};
-+
-+		axiperf: axiperf {
-+			compatible = "brcm,bcm2835-axiperf";
-+			reg = <0x7e009800 0x100>,
-+			      <0x7ee08000 0x100>;
-+			firmware = <&firmware>;
-+			status = "disabled";
-+		};
-+	};
-+
-+	vdd_5v0_reg: fixedregulator_5v0 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "5v0";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		regulator-always-on;
-+	};
-+
-+	vdd_3v3_reg: fixedregulator_3v3 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "3v3";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-always-on;
-+	};
-+};
-+
-+/* Configure and use the auxilliary interrupt controller */
-+
-+&aux {
-+	interrupts = <1 29>;
-+	interrupt-controller;
-+	#interrupt-cells = <1>;
-+};
-+
-+&uart1 {
-+	interrupt-parent = <&aux>;
-+	interrupts = <0>;
-+};
-+
-+&spi1 {
-+	interrupt-parent = <&aux>;
-+	interrupts = <1>;
-+};
-+
-+&spi2 {
-+	interrupt-parent = <&aux>;
-+	interrupts = <2>;
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-@@ -0,0 +1,194 @@
-+/dts-v1/;
-+
-+#ifdef RPI364
-+/memreserve/ 0x00000000 0x00001000;
-+#endif
-+
-+#include "bcm2710.dtsi"
-+#include "bcm283x-rpi-smsc9514.dtsi"
-+
-+/ {
-+	model = "Raspberry Pi 3 Model B";
-+
-+	chosen {
-+		bootargs = "8250.nr_uarts=1";
-+	};
-+
-+	aliases {
-+		serial0 = &uart1;
-+		serial1 = &uart0;
-+	};
-+};
-+
-+&gpio {
-+	spi0_pins: spi0_pins {
-+		brcm,pins = <9 10 11>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	spi0_cs_pins: spi0_cs_pins {
-+		brcm,pins = <8 7>;
-+		brcm,function = <1>; /* output */
-+	};
-+
-+	i2c0_pins: i2c0 {
-+		brcm,pins = <0 1>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2c1_pins: i2c1 {
-+		brcm,pins = <2 3>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2s_pins: i2s {
-+		brcm,pins = <18 19 20 21>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	sdio_pins: sdio_pins {
-+		brcm,pins =     <34 35 36 37 38 39>;
-+		brcm,function = <7>; // alt3 = SD1
-+		brcm,pull =     <0 2 2 2 2 2>;
-+	};
-+
-+	bt_pins: bt_pins {
-+		brcm,pins = <43>;
-+		brcm,function = <4>; /* alt0:GPCLK2 */
-+		brcm,pull = <0>;
-+	};
-+
-+	uart0_pins: uart0_pins {
-+		brcm,pins = <32 33>;
-+		brcm,function = <7>; /* alt3=UART0 */
-+		brcm,pull = <0 2>;
-+	};
-+
-+	uart1_pins: uart1_pins {
-+		brcm,pins;
-+		brcm,function;
-+		brcm,pull;
-+	};
-+
-+	audio_pins: audio_pins {
-+		brcm,pins = <40 41>;
-+		brcm,function = <4>;
-+	};
-+};
-+
-+&mmc {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdio_pins>;
-+	non-removable;
-+	bus-width = <4>;
-+	status = "okay";
-+	brcm,overclock-50 = <0>;
-+};
-+
-+&soc {
-+	virtgpio: virtgpio {
-+		compatible = "brcm,bcm2835-virtgpio";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		firmware = <&firmware>;
-+		status = "okay";
-+	};
-+
-+	expgpio: expgpio {
-+		compatible = "brcm,bcm2835-expgpio";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		firmware = <&firmware>;
-+		status = "okay";
-+	};
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_pins &bt_pins>;
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
-+	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+
-+	spidev0: spidev@0{
-+		compatible = "spidev";
-+		reg = <0>;	/* CE0 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+
-+	spidev1: spidev@1{
-+		compatible = "spidev";
-+		reg = <1>;	/* CE1 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c2 {
-+	clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+	act_led: act {
-+		label = "led0";
-+		linux,default-trigger = "mmc0";
-+		gpios = <&virtgpio 0 0>;
-+	};
-+
-+	pwr_led: pwr {
-+		label = "led1";
-+		linux,default-trigger = "input";
-+		gpios = <&expgpio 7 0>;
-+	};
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>;
-+};
-+
-+&audio {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&audio_pins>;
-+};
-+
-+/ {
-+	__overrides__ {
-+		act_led_gpio = <&act_led>,"gpios:4";
-+		act_led_activelow = <&act_led>,"gpios:8";
-+		act_led_trigger = <&act_led>,"linux,default-trigger";
-+
-+		pwr_led_gpio = <&pwr_led>,"gpios:4";
-+		pwr_led_activelow = <&pwr_led>,"gpios:8";
-+		pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts
-@@ -0,0 +1,129 @@
-+/dts-v1/;
-+
-+#include "bcm2710.dtsi"
-+
-+/ {
-+	model = "Raspberry Pi Compute Module 3";
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&gpio {
-+	spi0_pins: spi0_pins {
-+		brcm,pins = <9 10 11>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	spi0_cs_pins: spi0_cs_pins {
-+		brcm,pins = <8 7>;
-+		brcm,function = <1>; /* output */
-+	};
-+
-+	i2c0_pins: i2c0 {
-+		brcm,pins = <0 1>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2c1_pins: i2c1 {
-+		brcm,pins = <2 3>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2s_pins: i2s {
-+		brcm,pins = <18 19 20 21>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	audio_pins: audio_pins {
-+		brcm,pins;
-+		brcm,function;
-+	};
-+};
-+
-+&soc {
-+	virtgpio: virtgpio {
-+		compatible = "brcm,bcm2835-virtgpio";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		firmware = <&firmware>;
-+		status = "okay";
-+	};
-+
-+	expgpio: expgpio {
-+		compatible = "brcm,bcm2835-expgpio";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		firmware = <&firmware>;
-+		status = "okay";
-+	};
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
-+	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+
-+	spidev0: spidev@0{
-+		compatible = "spidev";
-+		reg = <0>;	/* CE0 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+
-+	spidev1: spidev@1{
-+		compatible = "spidev";
-+		reg = <1>;	/* CE1 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c2 {
-+	clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+	act_led: act {
-+		label = "led0";
-+		linux,default-trigger = "mmc0";
-+		gpios = <&virtgpio 0 0>;
-+	};
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&expgpio 0 GPIO_ACTIVE_LOW>;
-+};
-+
-+&audio {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&audio_pins>;
-+};
-+
-+/ {
-+	__overrides__ {
-+		act_led_gpio = <&act_led>,"gpios:4";
-+		act_led_activelow = <&act_led>,"gpios:8";
-+		act_led_trigger = <&act_led>,"linux,default-trigger";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2710.dtsi
-@@ -0,0 +1,32 @@
-+#include "bcm2837.dtsi"
-+#include "bcm270x.dtsi"
-+#include "bcm2708-rpi.dtsi"
-+
-+/ {
-+	compatible = "brcm,bcm2837", "brcm,bcm2836";
-+
-+	soc {
-+
-+		arm-pmu {
-+#ifdef RPI364
-+			compatible = "arm,armv8-pmuv3", "arm,cortex-a7-pmu";
-+#else
-+			compatible = "arm,cortex-a7-pmu";
-+#endif
-+			interrupt-parent = <&local_intc>;
-+			interrupts = <9>;
-+		};
-+
-+		syscon@40000000 {
-+			compatible = "brcm,bcm2836-arm-local", "syscon";
-+			reg = <0x40000000 0x100>;
-+		};
-+	};
-+
-+	__overrides__ {
-+		arm_freq = <&cpu0>, "clock-frequency:0",
-+		       <&cpu1>, "clock-frequency:0",
-+		       <&cpu2>, "clock-frequency:0",
-+		       <&cpu3>, "clock-frequency:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -0,0 +1,128 @@
-+# Overlays for the Raspberry Pi platform
-+
-+dtbo-$(CONFIG_ARCH_BCM2835) += \
-+	adau1977-adc.dtbo \
-+	adau7002-simple.dtbo \
-+	ads1015.dtbo \
-+	ads1115.dtbo \
-+	ads7846.dtbo \
-+	akkordion-iqdacplus.dtbo \
-+	allo-boss-dac-pcm512x-audio.dtbo \
-+	allo-digione.dtbo \
-+	allo-piano-dac-pcm512x-audio.dtbo \
-+	allo-piano-dac-plus-pcm512x-audio.dtbo \
-+	at86rf233.dtbo \
-+	audioinjector-addons.dtbo \
-+	audioinjector-wm8731-audio.dtbo \
-+	audremap.dtbo \
-+	bmp085_i2c-sensor.dtbo \
-+	dht11.dtbo \
-+	dionaudio-loco.dtbo \
-+	dionaudio-loco-v2.dtbo \
-+	dpi18.dtbo \
-+	dpi24.dtbo \
-+	dwc-otg.dtbo \
-+	dwc2.dtbo \
-+	enc28j60.dtbo \
-+	enc28j60-spi2.dtbo \
-+	fe-pi-audio.dtbo \
-+	goodix.dtbo \
-+	googlevoicehat-soundcard.dtbo \
-+	gpio-ir.dtbo \
-+	gpio-ir-tx.dtbo \
-+	gpio-poweroff.dtbo \
-+	gpio-shutdown.dtbo \
-+	hifiberry-amp.dtbo \
-+	hifiberry-dac.dtbo \
-+	hifiberry-dacplus.dtbo \
-+	hifiberry-digi.dtbo \
-+	hifiberry-digi-pro.dtbo \
-+	hy28a.dtbo \
-+	hy28b.dtbo \
-+	i2c-bcm2708.dtbo \
-+	i2c-gpio.dtbo \
-+	i2c-mux.dtbo \
-+	i2c-pwm-pca9685a.dtbo \
-+	i2c-rtc.dtbo \
-+	i2c-rtc-gpio.dtbo \
-+	i2c-sensor.dtbo \
-+	i2c0-bcm2708.dtbo \
-+	i2c1-bcm2708.dtbo \
-+	i2s-gpio28-31.dtbo \
-+	iqaudio-dac.dtbo \
-+	iqaudio-dacplus.dtbo \
-+	iqaudio-digi-wm8804-audio.dtbo \
-+	justboom-dac.dtbo \
-+	justboom-digi.dtbo \
-+	lirc-rpi.dtbo \
-+	mcp23017.dtbo \
-+	mcp23s17.dtbo \
-+	mcp2515-can0.dtbo \
-+	mcp2515-can1.dtbo \
-+	mcp3008.dtbo \
-+	midi-uart0.dtbo \
-+	midi-uart1.dtbo \
-+	mmc.dtbo \
-+	mpu6050.dtbo \
-+	mz61581.dtbo \
-+	papirus.dtbo \
-+	pi3-act-led.dtbo \
-+	pi3-disable-bt.dtbo \
-+	pi3-disable-wifi.dtbo \
-+	pi3-miniuart-bt.dtbo \
-+	piscreen.dtbo \
-+	piscreen2r.dtbo \
-+	pisound.dtbo \
-+	pitft22.dtbo \
-+	pitft28-capacitive.dtbo \
-+	pitft28-resistive.dtbo \
-+	pitft35-resistive.dtbo \
-+	pps-gpio.dtbo \
-+	pwm.dtbo \
-+	pwm-2chan.dtbo \
-+	pwm-ir-tx.dtbo \
-+	qca7000.dtbo \
-+	raspidac3.dtbo \
-+	rotary-encoder.dtbo \
-+	rpi-backlight.dtbo \
-+	rpi-cirrus-wm5102.dtbo \
-+	rpi-dac.dtbo \
-+	rpi-display.dtbo \
-+	rpi-ft5406.dtbo \
-+	rpi-proto.dtbo \
-+	rpi-sense.dtbo \
-+	rpi-tv.dtbo \
-+	rra-digidac1-wm8741-audio.dtbo \
-+	sc16is750-i2c.dtbo \
-+	sc16is752-spi1.dtbo \
-+	sdhost.dtbo \
-+	sdio.dtbo \
-+	sdio-1bit.dtbo \
-+	sdtweak.dtbo \
-+	smi.dtbo \
-+	smi-dev.dtbo \
-+	smi-nand.dtbo \
-+	spi-gpio35-39.dtbo \
-+	spi-rtc.dtbo \
-+	spi0-cs.dtbo \
-+	spi0-hw-cs.dtbo \
-+	spi1-1cs.dtbo \
-+	spi1-2cs.dtbo \
-+	spi1-3cs.dtbo \
-+	spi2-1cs.dtbo \
-+	spi2-2cs.dtbo \
-+	spi2-3cs.dtbo \
-+	tinylcd35.dtbo \
-+	uart1.dtbo \
-+	vc4-fkms-v3d.dtbo \
-+	vc4-kms-v3d.dtbo \
-+	vga666.dtbo \
-+	w1-gpio.dtbo \
-+	w1-gpio-pullup.dtbo \
-+	wittypi.dtbo
-+
-+targets += dtbs dtbs_install
-+targets += $(dtbo-y)
-+
-+always		:= $(dtbo-y)
-+clean-files	:= *.dtbo
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -0,0 +1,1678 @@
-+Introduction
-+============
-+
-+This directory contains Device Tree overlays. Device Tree makes it possible
-+to support many hardware configurations with a single kernel and without the
-+need to explicitly load or blacklist kernel modules. Note that this isn't a
-+"pure" Device Tree configuration (c.f. MACH_BCM2835) - some on-board devices
-+are still configured by the board support code, but the intention is to
-+eventually reach that goal.
-+
-+On Raspberry Pi, Device Tree usage is controlled from /boot/config.txt. By
-+default, the Raspberry Pi kernel boots with device tree enabled. You can
-+completely disable DT usage (for now) by adding:
-+
-+    device_tree=
-+
-+to your config.txt, which should cause your Pi to revert to the old way of
-+doing things after a reboot.
-+
-+In /boot you will find a .dtb for each base platform. This describes the
-+hardware that is part of the Raspberry Pi board. The loader (start.elf and its
-+siblings) selects the .dtb file appropriate for the platform by name, and reads
-+it into memory. At this point, all of the optional interfaces (i2c, i2s, spi)
-+are disabled, but they can be enabled using Device Tree parameters:
-+
-+    dtparam=i2c=on,i2s=on,spi=on
-+
-+However, this shouldn't be necessary in many use cases because loading an
-+overlay that requires one of those interfaces will cause it to be enabled
-+automatically, and it is advisable to only enable interfaces if they are
-+needed.
-+
-+Configuring additional, optional hardware is done using Device Tree overlays
-+(see below).
-+
-+GPIO numbering uses the hardware pin numbering scheme (aka BCM scheme) and
-+not the physical pin numbers.
-+
-+raspi-config
-+============
-+
-+The Advanced Options section of the raspi-config utility can enable and disable
-+Device Tree use, as well as toggling the I2C and SPI interfaces. Note that it
-+is possible to both enable an interface and blacklist the driver, if for some
-+reason you should want to defer the loading.
-+
-+Modules
-+=======
-+
-+As well as describing the hardware, Device Tree also gives enough information
-+to allow suitable driver modules to be located and loaded, with the corollary
-+that unneeded modules are not loaded. As a result it should be possible to
-+remove lines from /etc/modules, and /etc/modprobe.d/raspi-blacklist.conf can
-+have its contents deleted (or commented out).
-+
-+Using Overlays
-+==============
-+
-+Overlays are loaded using the "dtoverlay" directive. As an example, consider
-+the popular lirc-rpi module, the Linux Infrared Remote Control driver. In the
-+pre-DT world this would be loaded from /etc/modules, with an explicit
-+"modprobe lirc-rpi" command, or programmatically by lircd. With DT enabled,
-+this becomes a line in config.txt:
-+
-+    dtoverlay=lirc-rpi
-+
-+This causes the file /boot/overlays/lirc-rpi.dtbo to be loaded. By
-+default it will use GPIOs 17 (out) and 18 (in), but this can be modified using
-+DT parameters:
-+
-+    dtoverlay=lirc-rpi,gpio_out_pin=17,gpio_in_pin=13
-+
-+Parameters always have default values, although in some cases (e.g. "w1-gpio")
-+it is necessary to provided multiple overlays in order to get the desired
-+behaviour. See the list of overlays below for a description of the parameters
-+and their defaults.
-+
-+The Overlay and Parameter Reference
-+===================================
-+
-+N.B. When editing this file, please preserve the indentation levels to make it
-+simple to parse programmatically. NO HARD TABS.
-+
-+
-+Name:   <The base DTB>
-+Info:   Configures the base Raspberry Pi hardware
-+Load:   <loaded automatically>
-+Params:
-+        audio                   Set to "on" to enable the onboard ALSA audio
-+                                interface (default "off")
-+
-+        i2c_arm                 Set to "on" to enable the ARM's i2c interface
-+                                (default "off")
-+
-+        i2c_vc                  Set to "on" to enable the i2c interface
-+                                usually reserved for the VideoCore processor
-+                                (default "off")
-+
-+        i2c                     An alias for i2c_arm
-+
-+        i2c_arm_baudrate        Set the baudrate of the ARM's i2c interface
-+                                (default "100000")
-+
-+        i2c_vc_baudrate         Set the baudrate of the VideoCore i2c interface
-+                                (default "100000")
-+
-+        i2c_baudrate            An alias for i2c_arm_baudrate
-+
-+        i2s                     Set to "on" to enable the i2s interface
-+                                (default "off")
-+
-+        spi                     Set to "on" to enable the spi interfaces
-+                                (default "off")
-+
-+        random                  Set to "on" to enable the hardware random
-+                                number generator (default "on")
-+
-+        sd_overclock            Clock (in MHz) to use when the MMC framework
-+                                requests 50MHz
-+
-+        sd_force_pio            Disable DMA support for SD driver (default off)
-+
-+        sd_pio_limit            Number of blocks above which to use DMA for
-+                                SD card (default 1)
-+
-+        sd_debug                Enable debug output from SD driver (default off)
-+
-+        uart0                   Set to "off" to disable uart0 (default "on")
-+
-+        uart1                   Set to "on" or "off" to enable or disable uart1
-+                                (default varies)
-+
-+        watchdog                Set to "on" to enable the hardware watchdog
-+                                (default "off")
-+
-+        act_led_trigger         Choose which activity the LED tracks.
-+                                Use "heartbeat" for a nice load indicator.
-+                                (default "mmc")
-+
-+        act_led_activelow       Set to "on" to invert the sense of the LED
-+                                (default "off")
-+                                N.B. For Pi3 see pi3-act-led overlay.
-+
-+        act_led_gpio            Set which GPIO to use for the activity LED
-+                                (in case you want to connect it to an external
-+                                device)
-+                                (default "16" on a non-Plus board, "47" on a
-+                                Plus or Pi 2)
-+                                N.B. For Pi3 see pi3-act-led overlay.
-+
-+        pwr_led_trigger
-+        pwr_led_activelow
-+        pwr_led_gpio
-+                                As for act_led_*, but using the PWR LED.
-+                                Not available on Model A/B boards.
-+
-+        N.B. It is recommended to only enable those interfaces that are needed.
-+        Leaving all interfaces enabled can lead to unwanted behaviour (i2c_vc
-+        interfering with Pi Camera, I2S and SPI hogging GPIO pins, etc.)
-+        Note also that i2c, i2c_arm and i2c_vc are aliases for the physical
-+        interfaces i2c0 and i2c1. Use of the numeric variants is still possible
-+        but deprecated because the ARM/VC assignments differ between board
-+        revisions. The same board-specific mapping applies to i2c_baudrate,
-+        and the other i2c baudrate parameters.
-+
-+
-+Name:   adau1977-adc
-+Info:   Overlay for activation of ADAU1977 ADC codec over I2C for control
-+        and I2S for data.
-+Load:   dtoverlay=adau1977-adc
-+Params: <None>
-+
-+
-+Name:   adau7002-simple
-+Info:   Overlay for the activation of ADAU7002 stereo PDM to I2S converter.
-+Load:   dtoverlay=adau7002-simple,<param>=<val>
-+Params: card-name               Override the default, "adau7002", card name.
-+
-+
-+Name:   ads1015
-+Info:   Overlay for activation of Texas Instruments ADS1015 ADC over I2C
-+Load:   dtoverlay=ads1015,<param>=<val>
-+Params: addr                    I2C bus address of device. Set based on how the
-+                                addr pin is wired. (default=0x48 assumes addr
-+                                is pulled to GND)
-+        cha_enable              Enable virtual channel a. (default=true)
-+        cha_cfg                 Set the configuration for virtual channel a.
-+                                (default=4 configures this channel for the
-+                                voltage at A0 with respect to GND)
-+        cha_datarate            Set the datarate (samples/sec) for this channel.
-+                                (default=4 sets 1600 sps)
-+        cha_gain                Set the gain of the Programmable Gain
-+                                Amplifier for this channel. (default=2 sets the
-+                                full scale of the channel to 2.048 Volts)
-+
-+        Channel (ch) parameters can be set for each enabled channel.
-+        A maximum of 4 channels can be enabled (letters a thru d).
-+        For more information refer to the device datasheet at:
-+        http://www.ti.com/lit/ds/symlink/ads1015.pdf
-+
-+
-+Name:   ads1115
-+Info:   Texas Instruments ADS1115 ADC
-+Load:   dtoverlay=ads1115,<param>[=<val>]
-+Params: addr                    I2C bus address of device. Set based on how the
-+                                addr pin is wired. (default=0x48 assumes addr
-+                                is pulled to GND)
-+        cha_enable              Enable virtual channel a.
-+        cha_cfg                 Set the configuration for virtual channel a.
-+                                (default=4 configures this channel for the
-+                                voltage at A0 with respect to GND)
-+        cha_datarate            Set the datarate (samples/sec) for this channel.
-+                                (default=7 sets 860 sps)
-+        cha_gain                Set the gain of the Programmable Gain
-+                                Amplifier for this channel. (Default 1 sets the
-+                                full scale of the channel to 4.096 Volts)
-+
-+        Channel parameters can be set for each enabled channel.
-+        A maximum of 4 channels can be enabled (letters a thru d).
-+        For more information refer to the device datasheet at:
-+        http://www.ti.com/lit/ds/symlink/ads1115.pdf
-+
-+
-+Name:   ads7846
-+Info:   ADS7846 Touch controller
-+Load:   dtoverlay=ads7846,<param>=<val>
-+Params: cs                      SPI bus Chip Select (default 1)
-+        speed                   SPI bus speed (default 2MHz, max 3.25MHz)
-+        penirq                  GPIO used for PENIRQ. REQUIRED
-+        penirq_pull             Set GPIO pull (default 0=none, 2=pullup)
-+        swapxy                  Swap x and y axis
-+        xmin                    Minimum value on the X axis (default 0)
-+        ymin                    Minimum value on the Y axis (default 0)
-+        xmax                    Maximum value on the X axis (default 4095)
-+        ymax                    Maximum value on the Y axis (default 4095)
-+        pmin                    Minimum reported pressure value (default 0)
-+        pmax                    Maximum reported pressure value (default 65535)
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+                                (default 400)
-+
-+        penirq is required and usually xohms (60-100) has to be set as well.
-+        Apart from that, pmax (255) and swapxy are also common.
-+        The rest of the calibration can be done with xinput-calibrator.
-+        See: github.com/notro/fbtft/wiki/FBTFT-on-Raspian
-+        Device Tree binding document:
-+        www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt
-+
-+
-+Name:   akkordion-iqdacplus
-+Info:   Configures the Digital Dreamtime Akkordion Music Player (based on the
-+        OEM IQAudIO DAC+ or DAC Zero module).
-+Load:   dtoverlay=akkordion-iqdacplus,<param>=<val>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control. Enable with
-+                                dtoverlay=akkordion-iqdacplus,24db_digital_gain
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24db_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+
-+
-+Name:   allo-boss-dac-pcm512x-audio
-+Info:   Configures the Allo Boss DAC audio cards.
-+Load:   dtoverlay=allo-boss-dac-pcm512x-audio,<param>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control. Enable with
-+                                "dtoverlay=allo-boss-dac-pcm512x-audio,
-+                                24db_digital_gain"
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24db_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+        slave                   Force Boss DAC into slave mode, using Pi a
-+                                master for bit clock and frame clock. Enable
-+                                with "dtoverlay=allo-boss-dac-pcm512x-audio,
-+                                slave"
-+
-+
-+Name:   allo-digione
-+Info:   Configures the Allo Digione audio card
-+Load:   dtoverlay=allo-digione
-+Params: <None>
-+
-+
-+Name:   allo-piano-dac-pcm512x-audio
-+Info:   Configures the Allo Piano DAC (2.0/2.1) audio cards.
-+        (NB. This initial support is for 2.0 channel audio ONLY! ie. stereo.
-+        The subwoofer outputs on the Piano 2.1 are not currently supported!)
-+Load:   dtoverlay=allo-piano-dac-pcm512x-audio,<param>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control.
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24db_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+
-+
-+Name:   allo-piano-dac-plus-pcm512x-audio
-+Info:   Configures the Allo Piano DAC (2.1) audio cards.
-+Load:   dtoverlay=allo-piano-dac-plus-pcm512x-audio,<param>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control.
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24db_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+        glb_mclk                This option is only with Kali board. If enabled,
-+                                MCLK for Kali is used and PLL is disabled for
-+                                better voice quality. (default Off)
-+
-+
-+Name:   at86rf233
-+Info:   Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver,
-+        connected to spi0.0
-+Load:   dtoverlay=at86rf233,<param>=<val>
-+Params: interrupt               GPIO used for INT (default 23)
-+        reset                   GPIO used for Reset (default 24)
-+        sleep                   GPIO used for Sleep (default 25)
-+        speed                   SPI bus speed in Hz (default 3000000)
-+        trim                    Fine tuning of the internal capacitance
-+                                arrays (0=+0pF, 15=+4.5pF, default 15)
-+
-+
-+Name:   audioinjector-addons
-+Info:   Configures the audioinjector.net audio add on soundcards
-+Load:   dtoverlay=audioinjector-addons
-+Params: <None>
-+
-+
-+Name:   audioinjector-wm8731-audio
-+Info:   Configures the audioinjector.net audio add on soundcard
-+Load:   dtoverlay=audioinjector-wm8731-audio
-+Params: <None>
-+
-+
-+Name:   audremap
-+Info:   Switches PWM sound output to pins 12 (Right) & 13 (Left)
-+Load:   dtoverlay=audremap,<param>=<val>
-+Params: swap_lr                 Reverse the channel allocation, which will also
-+                                swap the audio jack outputs (default off)
-+        enable_jack             Don't switch off the audio jack output
-+                                (default off)
-+
-+
-+Name:   bmp085_i2c-sensor
-+Info:   This overlay is now deprecated - see i2c-sensor
-+Load:   dtoverlay=bmp085_i2c-sensor
-+Params: <None>
-+
-+
-+Name:   dht11
-+Info:   Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors
-+        Also sometimes found with the part number(s) AM230x.
-+Load:   dtoverlay=dht11,<param>=<val>
-+Params: gpiopin                 GPIO connected to the sensor's DATA output.
-+                                (default 4)
-+
-+
-+Name:   dionaudio-loco
-+Info:   Configures the Dion Audio LOCO DAC-AMP
-+Load:   dtoverlay=dionaudio-loco
-+Params: <None>
-+
-+
-+Name:   dionaudio-loco-v2
-+Info:   Configures the Dion Audio LOCO-V2 DAC-AMP
-+Load:   dtoverlay=dionaudio-loco-v2,<param>=<val>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control. Enable with
-+                                "dtoverlay=hifiberry-dacplus,24db_digital_gain"
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24dB_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+
-+
-+Name:   dpi18
-+Info:   Overlay for a generic 18-bit DPI display
-+        This uses GPIOs 0-21 (so no I2C, uart etc.), and activates the output
-+        2-3 seconds after the kernel has started.
-+Load:   dtoverlay=dpi18
-+Params: <None>
-+
-+
-+Name:   dpi24
-+Info:   Overlay for a generic 24-bit DPI display
-+        This uses GPIOs 0-27 (so no I2C, uart etc.), and activates the output
-+        2-3 seconds after the kernel has started.
-+Load:   dtoverlay=dpi24
-+Params: <None>
-+
-+
-+Name:   dwc-otg
-+Info:   Selects the dwc_otg USB controller driver which has fiq support. This
-+        is the default on all except the Pi Zero which defaults to dwc2.
-+Load:   dtoverlay=dwc-otg
-+Params: <None>
-+
-+
-+Name:   dwc2
-+Info:   Selects the dwc2 USB controller driver
-+Load:   dtoverlay=dwc2,<param>=<val>
-+Params: dr_mode                 Dual role mode: "host", "peripheral" or "otg"
-+
-+        g-rx-fifo-size          Size of rx fifo size in gadget mode
-+
-+        g-np-tx-fifo-size       Size of non-periodic tx fifo size in gadget
-+                                mode
-+
-+
-+[ The ds1307-rtc overlay has been deleted. See i2c-rtc. ]
-+
-+
-+Name:   enc28j60
-+Info:   Overlay for the Microchip ENC28J60 Ethernet Controller on SPI0
-+Load:   dtoverlay=enc28j60,<param>=<val>
-+Params: int_pin                 GPIO used for INT (default 25)
-+
-+        speed                   SPI bus speed (default 12000000)
-+
-+
-+Name:   enc28j60-spi2
-+Info:   Overlay for the Microchip ENC28J60 Ethernet Controller on SPI2
-+Load:   dtoverlay=enc28j60-spi2,<param>=<val>
-+Params: int_pin                 GPIO used for INT (default 39)
-+
-+        speed                   SPI bus speed (default 12000000)
-+
-+
-+Name:   fe-pi-audio
-+Info:   Configures the Fe-Pi Audio Sound Card
-+Load:   dtoverlay=fe-pi-audio
-+Params: <None>
-+
-+
-+Name:   goodix
-+Info:   Enables I2C connected Goodix gt9271 multiple touch controller using
-+        GPIOs 4 and 17 (pins 7 and 11 on GPIO header) for interrupt and reset.
-+Load:   dtoverlay=goodix,<param>=<val>
-+Params: interrupt               GPIO used for interrupt (default 4)
-+        reset                   GPIO used for reset (default 17)
-+
-+
-+Name:   googlevoicehat-soundcard
-+Info:   Configures the Google voiceHAT soundcard
-+Load:   dtoverlay=googlevoicehat-soundcard
-+Params: <None>
-+
-+
-+Name:   gpio-ir
-+Info:   Use GPIO pin as rc-core style infrared receiver input. The rc-core-
-+        based gpio_ir_recv driver maps received keys directly to a
-+        /dev/input/event* device, all decoding is done by the kernel - LIRC is
-+        not required! The key mapping and other decoding parameters can be
-+        configured by "ir-keytable" tool.
-+Load:   dtoverlay=gpio-ir,<param>=<val>
-+Params: gpio_pin                Input pin number. Default is 18.
-+
-+        gpio_pull               Desired pull-up/down state (off, down, up)
-+                                Default is "down".
-+
-+        rc-map-name             Default rc keymap (can also be changed by
-+                                ir-keytable), defaults to "rc-rc6-mce"
-+
-+
-+Name:   gpio-ir-tx
-+Info:   Use GPIO pin as bit-banged infrared transmitter output.
-+        This is an alternative to "pwm-ir-tx". gpio-ir-tx doesn't require
-+        a PWM so it can be used together with onboard analog audio.
-+Load:   dtoverlay=gpio-ir-tx,<param>=<val>
-+Params: gpio_pin                Output GPIO (default 18)
-+
-+        invert                  "1" = invert the output (make it active-low).
-+                                Default is "0" (active-high).
-+
-+
-+Name:   gpio-poweroff
-+Info:   Drives a GPIO high or low on poweroff (including halt). Enabling this
-+        overlay will prevent the ability to boot by driving GPIO3 low.
-+Load:   dtoverlay=gpio-poweroff,<param>=<val>
-+Params: gpiopin                 GPIO for signalling (default 26)
-+
-+        active_low              Set if the power control device requires a
-+                                high->low transition to trigger a power-down.
-+                                Note that this will require the support of a
-+                                custom dt-blob.bin to prevent a power-down
-+                                during the boot process, and that a reboot
-+                                will also cause the pin to go low.
-+
-+
-+Name:   gpio-shutdown
-+Info:   Initiates a shutdown when GPIO pin changes. The given GPIO pin
-+        is configured as an input key that generates KEY_POWER events.
-+        This event is handled by systemd-logind by initiating a
-+        shutdown. Systemd versions older than 225 need an udev rule
-+        enable listening to the input device:
-+
-+                ACTION!="REMOVE", SUBSYSTEM=="input", KERNEL=="event*", \
-+                        SUBSYSTEMS=="platform", DRIVERS=="gpio-keys", \
-+                        ATTRS{keys}=="116", TAG+="power-switch"
-+
-+        This overlay only handles shutdown. After shutdown, the system
-+        can be powered up again by driving GPIO3 low. The default
-+        configuration uses GPIO3 with a pullup, so if you connect a
-+        button between GPIO3 and GND (pin 5 and 6 on the 40-pin header),
-+        you get a shutdown and power-up button.
-+Load:   dtoverlay=gpio-shutdown,<param>=<val>
-+Params: gpio_pin                GPIO pin to trigger on (default 3)
-+
-+        active_low              When this is 1 (active low), a falling
-+                                edge generates a key down event and a
-+                                rising edge generates a key up event.
-+                                When this is 0 (active high), this is
-+                                reversed. The default is 1 (active low).
-+
-+        gpio_pull               Desired pull-up/down state (off, down, up)
-+                                Default is "up".
-+
-+                                Note that the default pin (GPIO3) has an
-+                                external pullup.
-+
-+
-+Name:   hifiberry-amp
-+Info:   Configures the HifiBerry Amp and Amp+ audio cards
-+Load:   dtoverlay=hifiberry-amp
-+Params: <None>
-+
-+
-+Name:   hifiberry-dac
-+Info:   Configures the HifiBerry DAC audio card
-+Load:   dtoverlay=hifiberry-dac
-+Params: <None>
-+
-+
-+Name:   hifiberry-dacplus
-+Info:   Configures the HifiBerry DAC+ audio card
-+Load:   dtoverlay=hifiberry-dacplus,<param>=<val>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control. Enable with
-+                                "dtoverlay=hifiberry-dacplus,24db_digital_gain"
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24dB_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+        slave                   Force DAC+ Pro into slave mode, using Pi as
-+                                master for bit clock and frame clock.
-+
-+
-+Name:   hifiberry-digi
-+Info:   Configures the HifiBerry Digi and Digi+ audio card
-+Load:   dtoverlay=hifiberry-digi
-+Params: <None>
-+
-+
-+Name:   hifiberry-digi-pro
-+Info:   Configures the HifiBerry Digi+ Pro audio card
-+Load:   dtoverlay=hifiberry-digi-pro
-+Params: <None>
-+
-+
-+Name:   hy28a
-+Info:   HY28A - 2.8" TFT LCD Display Module by HAOYU Electronics
-+        Default values match Texy's display shield
-+Load:   dtoverlay=hy28a,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+
-+        resetgpio               GPIO used to reset controller
-+
-+        ledgpio                 GPIO used to control backlight
-+
-+
-+Name:   hy28b
-+Info:   HY28B - 2.8" TFT LCD Display Module by HAOYU Electronics
-+        Default values match Texy's display shield
-+Load:   dtoverlay=hy28b,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+
-+        resetgpio               GPIO used to reset controller
-+
-+        ledgpio                 GPIO used to control backlight
-+
-+
-+Name:   i2c-bcm2708
-+Info:   Fall back to the i2c_bcm2708 driver for the i2c_arm bus.
-+Load:   dtoverlay=i2c-bcm2708
-+Params: <None>
-+
-+
-+Name:   i2c-gpio
-+Info:   Adds support for software i2c controller on gpio pins
-+Load:   dtoverlay=i2c-gpio,<param>=<val>
-+Params: i2c_gpio_sda            GPIO used for I2C data (default "23")
-+
-+        i2c_gpio_scl            GPIO used for I2C clock (default "24")
-+
-+        i2c_gpio_delay_us       Clock delay in microseconds
-+                                (default "2" = ~100kHz)
-+
-+
-+Name:   i2c-mux
-+Info:   Adds support for a number of I2C bus multiplexers on i2c_arm
-+Load:   dtoverlay=i2c-mux,<param>=<val>
-+Params: pca9542                 Select the NXP PCA9542 device
-+
-+        pca9545                 Select the NXP PCA9545 device
-+
-+        pca9548                 Select the NXP PCA9548 device
-+
-+        addr                    Change I2C address of the device (default 0x70)
-+
-+
-+[ The i2c-mux-pca9548a overlay has been deleted. See i2c-mux. ]
-+
-+
-+Name:   i2c-pwm-pca9685a
-+Info:   Adds support for an NXP PCA9685A I2C PWM controller on i2c_arm
-+Load:   dtoverlay=i2c-pwm-pca9685a,<param>=<val>
-+Params: addr                    I2C address of PCA9685A (default 0x40)
-+
-+
-+Name:   i2c-rtc
-+Info:   Adds support for a number of I2C Real Time Clock devices
-+Load:   dtoverlay=i2c-rtc,<param>=<val>
-+Params: abx80x                  Select one of the ABx80x family:
-+                                  AB0801, AB0803, AB0804, AB0805,
-+                                  AB1801, AB1803, AB1804, AB1805
-+
-+        ds1307                  Select the DS1307 device
-+
-+        ds1339                  Select the DS1339 device
-+
-+        ds3231                  Select the DS3231 device
-+
-+        m41t62                  Select the M41T62 device
-+
-+        mcp7940x                Select the MCP7940x device
-+
-+        mcp7941x                Select the MCP7941x device
-+
-+        pcf2127                 Select the PCF2127 device
-+
-+        pcf8523                 Select the PCF8523 device
-+
-+        pcf8563                 Select the PCF8563 device
-+
-+        trickle-diode-type      Diode type for trickle charge - "standard" or
-+                                "schottky" (ABx80x only)
-+
-+        trickle-resistor-ohms   Resistor value for trickle charge (DS1339,
-+                                ABx80x)
-+
-+        wakeup-source           Specify that the RTC can be used as a wakeup
-+                                source
-+
-+
-+Name:   i2c-rtc-gpio
-+Info:   Adds support for a number of I2C Real Time Clock devices
-+        using the software i2c controller
-+Load:   dtoverlay=i2c-rtc-gpio,<param>=<val>
-+Params: abx80x                  Select one of the ABx80x family:
-+                                  AB0801, AB0803, AB0804, AB0805,
-+                                  AB1801, AB1803, AB1804, AB1805
-+
-+        ds1307                  Select the DS1307 device
-+
-+        ds1339                  Select the DS1339 device
-+
-+        ds3231                  Select the DS3231 device
-+
-+        mcp7940x                Select the MCP7940x device
-+
-+        mcp7941x                Select the MCP7941x device
-+
-+        pcf2127                 Select the PCF2127 device
-+
-+        pcf8523                 Select the PCF8523 device
-+
-+        pcf8563                 Select the PCF8563 device
-+
-+        trickle-diode-type      Diode type for trickle charge - "standard" or
-+                                "schottky" (ABx80x only)
-+
-+        trickle-resistor-ohms   Resistor value for trickle charge (DS1339,
-+                                ABx80x)
-+
-+        wakeup-source           Specify that the RTC can be used as a wakeup
-+                                source
-+
-+        i2c_gpio_sda            GPIO used for I2C data (default "23")
-+
-+        i2c_gpio_scl            GPIO used for I2C clock (default "24")
-+
-+        i2c_gpio_delay_us       Clock delay in microseconds
-+                                (default "2" = ~100kHz)
-+
-+
-+Name:   i2c-sensor
-+Info:   Adds support for a number of I2C barometric pressure and temperature
-+        sensors on i2c_arm
-+Load:   dtoverlay=i2c-sensor,<param>=<val>
-+Params: addr                    Set the address for the BME280, BMP280, TMP102,
-+                                HDC100X, LM75 or SHT3x
-+
-+        bme280                  Select the Bosch Sensortronic BME280
-+                                Valid addresses 0x76-0x77, default 0x76
-+
-+        bmp085                  Select the Bosch Sensortronic BMP085
-+
-+        bmp180                  Select the Bosch Sensortronic BMP180
-+
-+        bmp280                  Select the Bosch Sensortronic BMP280
-+                                Valid addresses 0x76-0x77, default 0x76
-+
-+        hdc100x                 Select the Texas Instruments HDC100x temp sensor
-+                                Valid addresses 0x40-0x43, default 0x40
-+
-+        htu21                   Select the HTU21 temperature and humidity sensor
-+
-+        lm75                    Select the Maxim LM75 temperature sensor
-+                                Valid addresses 0x48-0x4f, default 0x4f
-+
-+        lm75addr                Deprecated - use addr parameter instead
-+
-+        si7020                  Select the Silicon Labs Si7013/20/21 humidity/
-+                                temperature sensor
-+
-+        tmp102                  Select the Texas Instruments TMP102 temp sensor
-+                                Valid addresses 0x48-0x4b, default 0x48
-+
-+        tsl4531                 Select the AMS TSL4531 digital ambient light
-+                                sensor
-+
-+        veml6070                Select the Vishay VEML6070 ultraviolet light
-+                                sensor
-+
-+        sht3x                   Select the Sensiron SHT3x temperature and
-+                                humidity sensor. Valid addresses 0x44-0x45,
-+                                default 0x44
-+
-+
-+Name:   i2c0-bcm2708
-+Info:   Enable the i2c_bcm2708 driver for the i2c0 bus. Not all pin combinations
-+        are usable on all platforms.
-+Load:   dtoverlay=i2c0-bcm2708,<param>=<val>
-+Params: sda0_pin                GPIO pin for SDA0 (deprecated - use pins_*)
-+        scl0_pin                GPIO pin for SCL0 (deprecated - use pins_*)
-+        pins_0_1                Use pins 0 and 1 (default)
-+        pins_28_29              Use pins 28 and 29
-+        pins_44_45              Use pins 44 and 45
-+        pins_46_47              Use pins 46 and 47
-+
-+
-+Name:   i2c1-bcm2708
-+Info:   Enable the i2c_bcm2708 driver for the i2c1 bus
-+Load:   dtoverlay=i2c1-bcm2708,<param>=<val>
-+Params: sda1_pin                GPIO pin for SDA1 (2 or 44 - default 2)
-+        scl1_pin                GPIO pin for SCL1 (3 or 45 - default 3)
-+        pin_func                Alternative pin function (4 (alt0), 6 (alt2) -
-+                                default 4)
-+
-+
-+Name:   i2s-gpio28-31
-+Info:   move I2S function block to GPIO 28 to 31
-+Load:   dtoverlay=i2s-gpio28-31
-+Params: <None>
-+
-+
-+Name:   iqaudio-dac
-+Info:   Configures the IQaudio DAC audio card
-+Load:   dtoverlay=iqaudio-dac,<param>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control. Enable with
-+                                "dtoverlay=iqaudio-dac,24db_digital_gain"
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24db_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+
-+
-+Name:   iqaudio-dacplus
-+Info:   Configures the IQaudio DAC+ audio card
-+Load:   dtoverlay=iqaudio-dacplus,<param>=<val>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control. Enable with
-+                                "dtoverlay=iqaudio-dacplus,24db_digital_gain"
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24db_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+        auto_mute_amp           If specified, unmute/mute the IQaudIO amp when
-+                                starting/stopping audio playback.
-+        unmute_amp              If specified, unmute the IQaudIO amp once when
-+                                the DAC driver module loads.
-+
-+
-+Name:   iqaudio-digi-wm8804-audio
-+Info:   Configures the IQAudIO Digi WM8804 audio card
-+Load:   dtoverlay=iqaudio-digi-wm8804-audio,<param>=<val>
-+Params: card_name               Override the default, "IQAudIODigi", card name.
-+        dai_name                Override the default, "IQAudIO Digi", dai name.
-+        dai_stream_name         Override the default, "IQAudIO Digi HiFi",
-+                                dai stream name.
-+
-+
-+Name:   justboom-dac
-+Info:   Configures the JustBoom DAC HAT, Amp HAT, DAC Zero and Amp Zero audio
-+        cards
-+Load:   dtoverlay=justboom-dac,<param>=<val>
-+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec
-+                                Digital volume control. Enable with
-+                                "dtoverlay=justboom-dac,24db_digital_gain"
-+                                (The default behaviour is that the Digital
-+                                volume control is limited to a maximum of
-+                                0dB. ie. it can attenuate but not provide
-+                                gain. For most users, this will be desired
-+                                as it will prevent clipping. By appending
-+                                the 24dB_digital_gain parameter, the Digital
-+                                volume control will allow up to 24dB of
-+                                gain. If this parameter is enabled, it is the
-+                                responsibility of the user to ensure that
-+                                the Digital volume control is set to a value
-+                                that does not result in clipping/distortion!)
-+
-+
-+Name:   justboom-digi
-+Info:   Configures the JustBoom Digi HAT and Digi Zero audio cards
-+Load:   dtoverlay=justboom-digi
-+Params: <None>
-+
-+
-+Name:   lirc-rpi
-+Info:   Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi)
-+        Consult the module documentation for more details.
-+Load:   dtoverlay=lirc-rpi,<param>=<val>
-+Params: gpio_out_pin            GPIO for output (default "17")
-+
-+        gpio_in_pin             GPIO for input (default "18")
-+
-+        gpio_in_pull            Pull up/down/off on the input pin
-+                                (default "down")
-+
-+        sense                   Override the IR receive auto-detection logic:
-+                                 "0" = force active-high
-+                                 "1" = force active-low
-+                                 "-1" = use auto-detection
-+                                (default "-1")
-+
-+        softcarrier             Turn the software carrier "on" or "off"
-+                                (default "on")
-+
-+        invert                  "on" = invert the output pin (default "off")
-+
-+        debug                   "on" = enable additional debug messages
-+                                (default "off")
-+
-+
-+Name:   mcp23017
-+Info:   Configures the MCP23017 I2C GPIO expander
-+Load:   dtoverlay=mcp23017,<param>=<val>
-+Params: gpiopin                 Gpio pin connected to the INTA output of the
-+                                MCP23017 (default: 4)
-+
-+        addr                    I2C address of the MCP23017 (default: 0x20)
-+
-+
-+Name:   mcp23s17
-+Info:   Configures the MCP23S08/17 SPI GPIO expanders.
-+        If devices are present on SPI1 or SPI2, those interfaces must be enabled
-+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
-+        If interrupts are enabled for a device on a given CS# on a SPI bus, that
-+        device must be the only one present on that SPI bus/CS#.
-+Load:   dtoverlay=mcp23s17,<param>=<val>
-+Params: s08-spi<n>-<m>-present  4-bit integer, bitmap indicating MCP23S08
-+                                devices present on SPI<n>, CS#<m>
-+
-+        s17-spi<n>-<m>-present  8-bit integer, bitmap indicating MCP23S17
-+                                devices present on SPI<n>, CS#<m>
-+
-+        s08-spi<n>-<m>-int-gpio integer, enables interrupts on a single
-+                                MCP23S08 device on SPI<n>, CS#<m>, specifies
-+                                the GPIO pin to which INT output of MCP23S08
-+                                is connected.
-+
-+        s17-spi<n>-<m>-int-gpio integer, enables mirrored interrupts on a
-+                                single MCP23S17 device on SPI<n>, CS#<m>,
-+                                specifies the GPIO pin to which either INTA
-+                                or INTB output of MCP23S17 is connected.
-+
-+
-+Name:   mcp2515-can0
-+Info:   Configures the MCP2515 CAN controller on spi0.0
-+Load:   dtoverlay=mcp2515-can0,<param>=<val>
-+Params: oscillator              Clock frequency for the CAN controller (Hz)
-+
-+        spimaxfrequency         Maximum SPI frequence (Hz)
-+
-+        interrupt               GPIO for interrupt signal
-+
-+
-+Name:   mcp2515-can1
-+Info:   Configures the MCP2515 CAN controller on spi0.1
-+Load:   dtoverlay=mcp2515-can1,<param>=<val>
-+Params: oscillator              Clock frequency for the CAN controller (Hz)
-+
-+        spimaxfrequency         Maximum SPI frequence (Hz)
-+
-+        interrupt               GPIO for interrupt signal
-+
-+
-+Name:   mcp3008
-+Info:   Configures MCP3008 A/D converters
-+        For devices on spi1 or spi2, the interfaces should be enabled
-+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
-+Load:   dtoverlay=mcp3008,<param>[=<val>]
-+Params: spi<n>-<m>-present      boolean, configure device at spi<n>, cs<m>
-+        spi<n>-<m>-speed        integer, set the spi bus speed for this device
-+
-+
-+Name:   midi-uart0
-+Info:   Configures UART0 (ttyAMA0) so that a requested 38.4kbaud actually gets
-+        31.25kbaud, the frequency required for MIDI
-+Load:   dtoverlay=midi-uart0
-+Params: <None>
-+
-+
-+Name:   midi-uart1
-+Info:   Configures UART1 (ttyS0) so that a requested 38.4kbaud actually gets
-+        31.25kbaud, the frequency required for MIDI
-+Load:   dtoverlay=midi-uart1
-+Params: <None>
-+
-+
-+Name:   mmc
-+Info:   Selects the bcm2835-mmc SD/MMC driver, optionally with overclock
-+Load:   dtoverlay=mmc,<param>=<val>
-+Params: overclock_50            Clock (in MHz) to use when the MMC framework
-+                                requests 50MHz
-+
-+
-+Name:   mpu6050
-+Info:   Overlay for i2c connected mpu6050 imu
-+Load:   dtoverlay=mpu6050,<param>=<val>
-+Params: interrupt               GPIO pin for interrupt (default 4)
-+
-+
-+Name:   mz61581
-+Info:   MZ61581 display by Tontec
-+Load:   dtoverlay=mz61581,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        txbuflen                Transmit buffer length (default 32768)
-+
-+        debug                   Debug output level {0-7}
-+
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+
-+
-+Name:   papirus
-+Info:   PaPiRus ePaper Screen by Pi Supply (both HAT and pHAT)
-+Load:   dtoverlay=papirus,<param>=<val>
-+Params: panel                   Display panel (required):
-+                                1.44": e1144cs021
-+                                2.0":  e2200cs021
-+                                2.7":  e2271cs021
-+
-+        speed                   Display SPI bus speed
-+
-+
-+[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]
-+
-+
-+[ The pcf8523-rtc overlay has been deleted. See i2c-rtc. ]
-+
-+
-+[ The pcf8563-rtc overlay has been deleted. See i2c-rtc. ]
-+
-+
-+Name:   pi3-act-led
-+Info:   Pi3 uses a GPIO expander to drive the LEDs which can only be accessed
-+        from the VPU. There is a special driver for this with a separate DT
-+        node, which has the unfortunate consequence of breaking the
-+        act_led_gpio and act_led_activelow dtparams.
-+        This overlay changes the GPIO controller back to the standard one and
-+        restores the dtparams.
-+Load:   dtoverlay=pi3-act-led,<param>=<val>
-+Params: activelow               Set to "on" to invert the sense of the LED
-+                                (default "off")
-+
-+        gpio                    Set which GPIO to use for the activity LED
-+                                (in case you want to connect it to an external
-+                                device)
-+                                REQUIRED
-+
-+
-+Name:   pi3-disable-bt
-+Info:   Disable Pi3 Bluetooth and restore UART0/ttyAMA0 over GPIOs 14 & 15
-+        N.B. To disable the systemd service that initialises the modem so it
-+        doesn't use the UART, use 'sudo systemctl disable hciuart'.
-+Load:   dtoverlay=pi3-disable-bt
-+Params: <None>
-+
-+
-+Name:   pi3-disable-wifi
-+Info:   Disable Pi3 onboard WiFi
-+Load:   dtoverlay=pi3-disable-wifi
-+Params: <None>
-+
-+
-+Name:   pi3-miniuart-bt
-+Info:   Switch Pi3 Bluetooth function to use the mini-UART (ttyS0) and restore
-+        UART0/ttyAMA0 over GPIOs 14 & 15. Note that this may reduce the maximum
-+        usable baudrate.
-+        N.B. It is also necessary to edit /lib/systemd/system/hciuart.service
-+        and replace ttyAMA0 with ttyS0, unless you have a system with udev rules
-+        that create /dev/serial0 and /dev/serial1, in which case use
-+        /dev/serial1 instead because it will always be correct. Furthermore,
-+        you must also set core_freq=250 in config.txt or the miniuart will not
-+        work.
-+Load:   dtoverlay=pi3-miniuart-bt
-+Params: <None>
-+
-+
-+Name:   piscreen
-+Info:   PiScreen display by OzzMaker.com
-+Load:   dtoverlay=piscreen,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+
-+
-+Name:   piscreen2r
-+Info:   PiScreen 2 with resistive TP display by OzzMaker.com
-+Load:   dtoverlay=piscreen2r,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+
-+
-+Name:   pisound
-+Info:   Configures the Blokas Labs pisound card
-+Load:   dtoverlay=pisound
-+Params: <None>
-+
-+
-+Name:   pitft22
-+Info:   Adafruit PiTFT 2.2" screen
-+Load:   dtoverlay=pitft22,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+
-+Name:   pitft28-capacitive
-+Info:   Adafruit PiTFT 2.8" capacitive touch screen
-+Load:   dtoverlay=pitft28-capacitive,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+        touch-sizex             Touchscreen size x (default 240)
-+
-+        touch-sizey             Touchscreen size y (default 320)
-+
-+        touch-invx              Touchscreen inverted x axis
-+
-+        touch-invy              Touchscreen inverted y axis
-+
-+        touch-swapxy            Touchscreen swapped x y axis
-+
-+
-+Name:   pitft28-resistive
-+Info:   Adafruit PiTFT 2.8" resistive touch screen
-+Load:   dtoverlay=pitft28-resistive,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+
-+Name:   pitft35-resistive
-+Info:   Adafruit PiTFT 3.5" resistive touch screen
-+Load:   dtoverlay=pitft35-resistive,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+
-+Name:   pps-gpio
-+Info:   Configures the pps-gpio (pulse-per-second time signal via GPIO).
-+Load:   dtoverlay=pps-gpio,<param>=<val>
-+Params: gpiopin                 Input GPIO (default "18")
-+        assert_falling_edge     When present, assert is indicated by a falling
-+                                edge, rather than by a rising edge
-+
-+
-+Name:   pwm
-+Info:   Configures a single PWM channel
-+        Legal pin,function combinations for each channel:
-+          PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0)            52,5(Alt1)
-+          PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1)
-+        N.B.:
-+          1) Pin 18 is the only one available on all platforms, and
-+             it is the one used by the I2S audio interface.
-+             Pins 12 and 13 might be better choices on an A+, B+ or Pi2.
-+          2) The onboard analogue audio output uses both PWM channels.
-+          3) So be careful mixing audio and PWM.
-+          4) Currently the clock must have been enabled and configured
-+             by other means.
-+Load:   dtoverlay=pwm,<param>=<val>
-+Params: pin                     Output pin (default 18) - see table
-+        func                    Pin function (default 2 = Alt5) - see above
-+        clock                   PWM clock frequency (informational)
-+
-+
-+Name:   pwm-2chan
-+Info:   Configures both PWM channels
-+        Legal pin,function combinations for each channel:
-+          PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0)            52,5(Alt1)
-+          PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1)
-+        N.B.:
-+          1) Pin 18 is the only one available on all platforms, and
-+             it is the one used by the I2S audio interface.
-+             Pins 12 and 13 might be better choices on an A+, B+ or Pi2.
-+          2) The onboard analogue audio output uses both PWM channels.
-+          3) So be careful mixing audio and PWM.
-+          4) Currently the clock must have been enabled and configured
-+             by other means.
-+Load:   dtoverlay=pwm-2chan,<param>=<val>
-+Params: pin                     Output pin (default 18) - see table
-+        pin2                    Output pin for other channel (default 19)
-+        func                    Pin function (default 2 = Alt5) - see above
-+        func2                   Function for pin2 (default 2 = Alt5)
-+        clock                   PWM clock frequency (informational)
-+
-+
-+Name:   pwm-ir-tx
-+Info:   Use GPIO pin as pwm-assisted infrared transmitter output.
-+        This is an alternative to "gpio-ir-tx". pwm-ir-tx makes use
-+        of PWM0 to reduce the CPU load during transmission compared to
-+        gpio-ir-tx which uses bit-banging.
-+        Legal pin,function combinations are:
-+          12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1)
-+Load:   dtoverlay=pwm-ir-tx,<param>=<val>
-+Params: gpio_pin                Output GPIO (default 18)
-+
-+        func                    Pin function (default 2 = Alt5)
-+
-+
-+Name:   qca7000
-+Info:   I2SE's Evaluation Board for PLC Stamp micro
-+Load:   dtoverlay=qca7000,<param>=<val>
-+Params: int_pin                 GPIO pin for interrupt signal (default 23)
-+
-+        speed                   SPI bus speed (default 12 MHz)
-+
-+
-+Name:   raspidac3
-+Info:   Configures the RaspiDAV Rev.3x audio card
-+Load:   dtoverlay=raspidac3
-+Params: <None>
-+
-+
-+Name:   rotary-encoder
-+Info:   Overlay for GPIO connected rotary encoder.
-+Load:   dtoverlay=rotary-encoder,<param>=<val>
-+Params: rotary0_pin_a           GPIO connected to rotary encoder channel A
-+                                (default 4).
-+        rotary0_pin_b           GPIO connected to rotary encoder channel B
-+                                (default 17).
-+
-+
-+Name:   rpi-backlight
-+Info:   Raspberry Pi official display backlight driver
-+Load:   dtoverlay=rpi-backlight
-+Params: <None>
-+
-+
-+Name:   rpi-cirrus-wm5102
-+Info:   Configures the Cirrus Logic Audio Card
-+Load:   dtoverlay=rpi-cirrus-wm5102
-+Params: <None>
-+
-+
-+Name:   rpi-dac
-+Info:   Configures the RPi DAC audio card
-+Load:   dtoverlay=rpi-dac
-+Params: <None>
-+
-+
-+Name:   rpi-display
-+Info:   RPi-Display - 2.8" Touch Display by Watterott
-+Load:   dtoverlay=rpi-display,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+        rotate                  Display rotation {0,90,180,270}
-+        fps                     Delay between frame updates
-+        debug                   Debug output level {0-7}
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+        swapxy                  Swap x and y axis
-+
-+
-+Name:   rpi-ft5406
-+Info:   Official Raspberry Pi display touchscreen
-+Load:   dtoverlay=rpi-ft5406,<param>=<val>
-+Params: touchscreen-size-x      Touchscreen X resolution (default 800)
-+        touchscreen-size-y      Touchscreen Y resolution (default 600);
-+        touchscreen-inverted-x  Invert touchscreen X coordinates (default 0);
-+        touchscreen-inverted-y  Invert touchscreen Y coordinates (default 0);
-+        touchscreen-swapped-x-y Swap X and Y cordinates (default 0);
-+
-+
-+Name:   rpi-proto
-+Info:   Configures the RPi Proto audio card
-+Load:   dtoverlay=rpi-proto
-+Params: <None>
-+
-+
-+Name:   rpi-sense
-+Info:   Raspberry Pi Sense HAT
-+Load:   dtoverlay=rpi-sense
-+Params: <None>
-+
-+
-+Name:   rpi-tv
-+Info:   Raspberry Pi TV HAT
-+Load:   dtoverlay=rpi-tv
-+Params: <None>
-+
-+
-+Name:   rra-digidac1-wm8741-audio
-+Info:   Configures the Red Rocks Audio DigiDAC1 soundcard
-+Load:   dtoverlay=rra-digidac1-wm8741-audio
-+Params: <None>
-+
-+
-+Name:   sc16is750-i2c
-+Info:   Overlay for the NXP SC16IS750 UART with I2C Interface
-+        Enables the chip on I2C1 at 0x48. To select another address,
-+        please refer to table 10 in reference manual.
-+
-+Load:   dtoverlay=sc16is750-i2c,<param>=<val>
-+Params: int_pin                 GPIO used for IRQ (default 24)
-+        addr                    Address (default 0x48)
-+
-+
-+Name:   sc16is752-spi1
-+Info:   Overlay for the NXP SC16IS752 Dual UART with SPI Interface
-+        Enables the chip on SPI1.
-+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:
-+              A+, B+, Zero and PI2 B; as well as the Compute Module.
-+
-+Load:   dtoverlay=sc16is752-spi1,<param>=<val>
-+Params: int_pin                 GPIO used for IRQ (default 24)
-+
-+
-+Name:   sdhost
-+Info:   Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock.
-+        N.B. This overlay is designed for situations where the mmc driver is
-+        the default, so it disables the other (mmc) interface - this will kill
-+        WiFi on a Pi3. If this isn't what you want, either use the sdtweak
-+        overlay or the new sd_* dtparams of the base DTBs.
-+Load:   dtoverlay=sdhost,<param>=<val>
-+Params: overclock_50            Clock (in MHz) to use when the MMC framework
-+                                requests 50MHz
-+
-+        force_pio               Disable DMA support (default off)
-+
-+        pio_limit               Number of blocks above which to use DMA
-+                                (default 1)
-+
-+        debug                   Enable debug output (default off)
-+
-+
-+Name:   sdio
-+Info:   Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock,
-+        and enables SDIO via GPIOs 22-27.
-+Load:   dtoverlay=sdio,<param>=<val>
-+Params: sdio_overclock          SDIO Clock (in MHz) to use when the MMC
-+                                framework requests 50MHz
-+
-+        poll_once               Disable SDIO-device polling every second
-+                                (default on: polling once at boot-time)
-+
-+        bus_width               Set the SDIO host bus width (default 4 bits)
-+
-+
-+Name:   sdio-1bit
-+Info:   Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock,
-+        and enables 1-bit SDIO via GPIOs 22-25.
-+Load:   dtoverlay=sdio-1bit,<param>=<val>
-+Params: sdio_overclock          SDIO Clock (in MHz) to use when the MMC
-+                                framework requests 50MHz
-+
-+        poll_once               Disable SDIO-device polling every second
-+                                (default on: polling once at boot-time)
-+
-+
-+Name:   sdtweak
-+Info:   Tunes the bcm2835-sdhost SD/MMC driver
-+        N.B. This functionality is now available via the sd_* dtparams in the
-+        base DTB.
-+Load:   dtoverlay=sdtweak,<param>=<val>
-+Params: overclock_50            Clock (in MHz) to use when the MMC framework
-+                                requests 50MHz
-+
-+        force_pio               Disable DMA support (default off)
-+
-+        pio_limit               Number of blocks above which to use DMA
-+                                (default 1)
-+
-+        debug                   Enable debug output (default off)
-+
-+
-+Name:   smi
-+Info:   Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25!
-+Load:   dtoverlay=smi
-+Params: <None>
-+
-+
-+Name:   smi-dev
-+Info:   Enables the userspace interface for the SMI driver
-+Load:   dtoverlay=smi-dev
-+Params: <None>
-+
-+
-+Name:   smi-nand
-+Info:   Enables access to NAND flash via the SMI interface
-+Load:   dtoverlay=smi-nand
-+Params: <None>
-+
-+
-+Name:   spi-gpio35-39
-+Info:   Move SPI function block to GPIO 35 to 39
-+Load:   dtoverlay=spi-gpio35-39
-+Params: <None>
-+
-+
-+Name:   spi-rtc
-+Info:   Adds support for a number of SPI Real Time Clock devices
-+Load:   dtoverlay=spi-rtc,<param>=<val>
-+Params: pcf2123                 Select the PCF2123 device
-+
-+
-+Name:   spi0-cs
-+Info:   Allows the (software) CS pins for SPI0 to be changed
-+Load:   dtoverlay=spi0-cs,<param>=<val>
-+Params: cs0_pin                 GPIO pin for CS0 (default 8)
-+        cs1_pin                 GPIO pin for CS1 (default 7)
-+
-+
-+Name:   spi0-hw-cs
-+Info:   Re-enables hardware CS/CE (chip selects) for SPI0
-+Load:   dtoverlay=spi0-hw-cs
-+Params: <None>
-+
-+
-+Name:   spi1-1cs
-+Info:   Enables spi1 with a single chip select (CS) line and associated spidev
-+        dev node. The gpio pin number for the CS line and spidev device node
-+        creation are configurable.
-+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:
-+              A+, B+, Zero and PI2 B; as well as the Compute Module.
-+Load:   dtoverlay=spi1-1cs,<param>=<val>
-+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
-+        cs0_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev1.0 (default
-+                                is 'okay' or enabled).
-+
-+
-+Name:   spi1-2cs
-+Info:   Enables spi1 with two chip select (CS) lines and associated spidev
-+        dev nodes. The gpio pin numbers for the CS lines and spidev device node
-+        creation are configurable.
-+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:
-+              A+, B+, Zero and PI2 B; as well as the Compute Module.
-+Load:   dtoverlay=spi1-2cs,<param>=<val>
-+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
-+        cs1_pin                 GPIO pin for CS1 (default 17 - BCM SPI1_CE1).
-+        cs0_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev1.0 (default
-+                                is 'okay' or enabled).
-+        cs1_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev1.1 (default
-+                                is 'okay' or enabled).
-+
-+
-+Name:   spi1-3cs
-+Info:   Enables spi1 with three chip select (CS) lines and associated spidev
-+        dev nodes. The gpio pin numbers for the CS lines and spidev device node
-+        creation are configurable.
-+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:
-+              A+, B+, Zero and PI2 B; as well as the Compute Module.
-+Load:   dtoverlay=spi1-3cs,<param>=<val>
-+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
-+        cs1_pin                 GPIO pin for CS1 (default 17 - BCM SPI1_CE1).
-+        cs2_pin                 GPIO pin for CS2 (default 16 - BCM SPI1_CE2).
-+        cs0_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev1.0 (default
-+                                is 'okay' or enabled).
-+        cs1_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev1.1 (default
-+                                is 'okay' or enabled).
-+        cs2_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev1.2 (default
-+                                is 'okay' or enabled).
-+
-+
-+Name:   spi2-1cs
-+Info:   Enables spi2 with a single chip select (CS) line and associated spidev
-+        dev node. The gpio pin number for the CS line and spidev device node
-+        creation are configurable.
-+        N.B.: spi2 is only accessible with the Compute Module.
-+Load:   dtoverlay=spi2-1cs,<param>=<val>
-+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).
-+        cs0_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev2.0 (default
-+                                is 'okay' or enabled).
-+
-+
-+Name:   spi2-2cs
-+Info:   Enables spi2 with two chip select (CS) lines and associated spidev
-+        dev nodes. The gpio pin numbers for the CS lines and spidev device node
-+        creation are configurable.
-+        N.B.: spi2 is only accessible with the Compute Module.
-+Load:   dtoverlay=spi2-2cs,<param>=<val>
-+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).
-+        cs1_pin                 GPIO pin for CS1 (default 44 - BCM SPI2_CE1).
-+        cs0_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev2.0 (default
-+                                is 'okay' or enabled).
-+        cs1_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev2.1 (default
-+                                is 'okay' or enabled).
-+
-+
-+Name:   spi2-3cs
-+Info:   Enables spi2 with three chip select (CS) lines and associated spidev
-+        dev nodes. The gpio pin numbers for the CS lines and spidev device node
-+        creation are configurable.
-+        N.B.: spi2 is only accessible with the Compute Module.
-+Load:   dtoverlay=spi2-3cs,<param>=<val>
-+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).
-+        cs1_pin                 GPIO pin for CS1 (default 44 - BCM SPI2_CE1).
-+        cs2_pin                 GPIO pin for CS2 (default 45 - BCM SPI2_CE2).
-+        cs0_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev2.0 (default
-+                                is 'okay' or enabled).
-+        cs1_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev2.1 (default
-+                                is 'okay' or enabled).
-+        cs2_spidev              Set to 'disabled' to stop the creation of a
-+                                userspace device node /dev/spidev2.2 (default
-+                                is 'okay' or enabled).
-+
-+
-+Name:   tinylcd35
-+Info:   3.5" Color TFT Display by www.tinylcd.com
-+        Options: Touch, RTC, keypad
-+Load:   dtoverlay=tinylcd35,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+        touch                   Enable touch panel
-+
-+        touchgpio               Touch controller IRQ GPIO
-+
-+        xohms                   Touchpanel: Resistance of X-plate in ohms
-+
-+        rtc-pcf                 PCF8563 Real Time Clock
-+
-+        rtc-ds                  DS1307 Real Time Clock
-+
-+        keypad                  Enable keypad
-+
-+        Examples:
-+            Display with touchpanel, PCF8563 RTC and keypad:
-+                dtoverlay=tinylcd35,touch,rtc-pcf,keypad
-+            Old touch display:
-+                dtoverlay=tinylcd35,touch,touchgpio=3
-+
-+
-+Name:   uart1
-+Info:   Enable uart1 in place of uart0
-+Load:   dtoverlay=uart1,<param>=<val>
-+Params: txd1_pin                GPIO pin for TXD1 (14, 32 or 40 - default 14)
-+
-+        rxd1_pin                GPIO pin for RXD1 (15, 33 or 41 - default 15)
-+
-+
-+Name:   vc4-fkms-v3d
-+Info:   Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx
-+        display stack.
-+Load:   dtoverlay=vc4-fkms-v3d,<param>
-+Params: cma-256                 CMA is 256MB, 256MB-aligned (needs 1GB)
-+        cma-192                 CMA is 192MB, 256MB-aligned (needs 1GB)
-+        cma-128                 CMA is 128MB, 128MB-aligned
-+        cma-96                  CMA is 96MB, 128MB-aligned
-+        cma-64                  CMA is 64MB, 64MB-aligned
-+
-+
-+Name:   vc4-kms-v3d
-+Info:   Enable Eric Anholt's DRM VC4 HDMI/HVS/V3D driver. Running startx or
-+        booting to GUI while this overlay is in use will cause interesting
-+        lockups.
-+Load:   dtoverlay=vc4-kms-v3d,<param>
-+Params: cma-256                 CMA is 256MB, 256MB-aligned (needs 1GB)
-+        cma-192                 CMA is 192MB, 256MB-aligned (needs 1GB)
-+        cma-128                 CMA is 128MB, 128MB-aligned
-+        cma-96                  CMA is 96MB, 128MB-aligned
-+        cma-64                  CMA is 64MB, 64MB-aligned
-+
-+
-+Name:   vga666
-+Info:   Overlay for the Fen Logic VGA666 board
-+        This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds
-+        after the kernel has started.
-+Load:   dtoverlay=vga666
-+Params: <None>
-+
-+
-+Name:   w1-gpio
-+Info:   Configures the w1-gpio Onewire interface module.
-+        Use this overlay if you *don't* need a GPIO to drive an external pullup.
-+Load:   dtoverlay=w1-gpio,<param>=<val>
-+Params: gpiopin                 GPIO for I/O (default "4")
-+
-+        pullup                  Non-zero, "on", or "y" to enable the parasitic
-+                                power (2-wire, power-on-data) feature
-+
-+
-+Name:   w1-gpio-pullup
-+Info:   Configures the w1-gpio Onewire interface module.
-+        Use this overlay if you *do* need a GPIO to drive an external pullup.
-+Load:   dtoverlay=w1-gpio-pullup,<param>=<val>
-+Params: gpiopin                 GPIO for I/O (default "4")
-+
-+        pullup                  Non-zero, "on", or "y" to enable the parasitic
-+                                power (2-wire, power-on-data) feature
-+
-+        extpullup               GPIO for external pullup (default "5")
-+
-+
-+Name:   wittypi
-+Info:   Configures the wittypi RTC module.
-+Load:   dtoverlay=wittypi,<param>=<val>
-+Params: led_gpio                GPIO for LED (default "17")
-+        led_trigger             Choose which activity the LED tracks (default
-+                                "default-on")
-+
-+
-+Troubleshooting
-+===============
-+
-+If you are experiencing problems that you think are DT-related, enable DT
-+diagnostic output by adding this to /boot/config.txt:
-+
-+    dtdebug=on
-+
-+and rebooting. Then run:
-+
-+    sudo vcdbg log msg
-+
-+and look for relevant messages.
-+
-+Further reading
-+===============
-+
-+This is only meant to be a quick introduction to the subject of Device Tree on
-+Raspberry Pi. There is a more complete explanation here:
-+
-+http://www.raspberrypi.org/documentation/configuration/device-tree.md
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts
-@@ -0,0 +1,40 @@
-+// Definitions for ADAU1977 ADC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+    
-+	fragment@0 {
-+        	target = <&i2c>;
-+        	
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+			
-+			adau1977: codec@11 {
-+                        	compatible = "adi,adau1977";
-+                        	reg = <0x11>;
-+                        	reset-gpios = <&gpio 5 0>;
-+				AVDD-supply = <&vdd_3v3_reg>;
-+                	};
-+        	};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "adi,adau1977-adc";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts
-@@ -0,0 +1,52 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+    compatible = "brcm,bcm2708";
-+
-+    fragment@0 {
-+        target = <&i2s>;
-+        __overlay__ {
-+            status = "okay";
-+        };
-+    };
-+
-+    fragment@1 {
-+        target-path = "/";
-+        __overlay__ {
-+                adau7002_codec: adau7002-codec {
-+                #sound-dai-cells = <0>;
-+                compatible = "adi,adau7002";
-+/*                IOVDD-supply = <&supply>;*/
-+                status = "okay";
-+            };
-+        };
-+    };
-+
-+    fragment@2 {
-+        target = <&sound>;
-+            sound_overlay: __overlay__ {
-+            compatible = "simple-audio-card";
-+            simple-audio-card,format = "i2s";
-+            simple-audio-card,name = "adau7002";
-+            simple-audio-card,bitclock-slave = <&dailink0_slave>;
-+            simple-audio-card,frame-slave = <&dailink0_slave>;
-+            simple-audio-card,widgets =
-+                    "Microphone", "Microphone Jack";
-+            simple-audio-card,routing =
-+                    "PDM_DAT", "Microphone Jack";
-+            status = "okay";
-+            simple-audio-card,cpu {
-+                sound-dai = <&i2s>;
-+            };
-+            dailink0_slave: simple-audio-card,codec {
-+                sound-dai = <&adau7002_codec>;
-+            };
-+        };
-+    };
-+
-+
-+    __overrides__ {
-+        card-name = <&sound_overlay>,"simple-audio-card,name";
-+    };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/ads1015-overlay.dts
-@@ -0,0 +1,98 @@
-+/*
-+ * 2016 - Erik Sejr
-+ */
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+    compatible = "brcm,bcm2708";
-+    /* ----------- ADS1015 ------------ */
-+    fragment@0 {
-+        target = <&i2c_arm>;
-+        __overlay__ {
-+            #address-cells = <1>;
-+            #size-cells = <0>;
-+            status = "okay";
-+            ads1015: ads1015 {
-+                compatible = "ti,ads1015";
-+                status = "okay";
-+                #address-cells = <1>;
-+                #size-cells = <0>;
-+                reg = <0x48>;
-+            };
-+        };
-+    };
-+
-+    fragment@1 {
-+        target-path = "i2c_arm/ads1015";
-+        __overlay__ {
-+            #address-cells = <1>;
-+            #size-cells = <0>;
-+            channel_a: channel_a {
-+                reg = <4>;
-+                ti,gain = <2>;
-+                ti,datarate = <4>;
-+            };
-+        };
-+    };
-+
-+    fragment@2 {
-+        target-path = "i2c_arm/ads1015";
-+        __dormant__ {
-+            #address-cells = <1>;
-+            #size-cells = <0>;
-+            channel_b: channel_b {
-+                reg = <5>;
-+                ti,gain = <2>;
-+                ti,datarate = <4>;
-+            };
-+        };
-+    };
-+
-+    fragment@3 {
-+        target-path = "i2c_arm/ads1015";
-+        __dormant__ {
-+            #address-cells = <1>;
-+            #size-cells = <0>;
-+            channel_c: channel_c {
-+                reg = <6>;
-+                ti,gain = <2>;
-+                ti,datarate = <4>;
-+            };
-+        };
-+    };
-+
-+    fragment@4 {
-+        target-path = "i2c_arm/ads1015";
-+        __dormant__ {
-+            #address-cells = <1>;
-+            #size-cells = <0>;
-+            channel_d: channel_d {
-+                reg = <7>;
-+                ti,gain = <2>;
-+                ti,datarate = <4>;
-+            };
-+        };
-+    };
-+
-+    __overrides__ {
-+        addr =            <&ads1015>,"reg:0";
-+        cha_enable =      <0>,"=1";
-+        cha_cfg =         <&channel_a>,"reg:0";
-+        cha_gain =        <&channel_a>,"ti,gain:0";
-+        cha_datarate =    <&channel_a>,"ti,datarate:0";
-+        chb_enable =      <0>,"=2";
-+        chb_cfg =         <&channel_b>,"reg:0";
-+        chb_gain =        <&channel_b>,"ti,gain:0";
-+        chb_datarate =    <&channel_b>,"ti,datarate:0";
-+        chc_enable =      <0>,"=3";
-+        chc_cfg =         <&channel_c>,"reg:0";
-+        chc_gain =        <&channel_c>,"ti,gain:0";
-+        chc_datarate =    <&channel_c>,"ti,datarate:0";
-+        chd_enable =      <0>,"=4";
-+        chd_cfg =         <&channel_d>,"reg:0";
-+        chd_gain =        <&channel_d>,"ti,gain:0";
-+        chd_datarate =    <&channel_d>,"ti,datarate:0";
-+   };
-+
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/ads1115-overlay.dts
-@@ -0,0 +1,103 @@
-+/*
-+ * TI ADS1115 multi-channel ADC overlay
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ads1115: ads1115 {
-+				compatible = "ti,ads1115";
-+				status = "okay";
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				reg = <0x48>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "i2c_arm/ads1115";
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			channel_a: channel_a {
-+				reg = <4>;
-+				ti,gain = <1>;
-+				ti,datarate = <7>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "i2c_arm/ads1115";
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			channel_b: channel_b {
-+				reg = <5>;
-+				ti,gain = <1>;
-+				ti,datarate = <7>;
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target-path = "i2c_arm/ads1115";
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			channel_c: channel_c {
-+				reg = <6>;
-+				ti,gain = <1>;
-+				ti,datarate = <7>;
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target-path = "i2c_arm/ads1115";
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			channel_d: channel_d {
-+				reg = <7>;
-+				ti,gain = <1>;
-+				ti,datarate = <7>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		addr =            <&ads1115>,"reg:0";
-+		cha_enable =      <0>,"=1";
-+		cha_cfg =         <&channel_a>,"reg:0";
-+		cha_gain =        <&channel_a>,"ti,gain:0";
-+		cha_datarate =    <&channel_a>,"ti,datarate:0";
-+		chb_enable =      <0>,"=2";
-+		chb_cfg =         <&channel_b>,"reg:0";
-+		chb_gain =        <&channel_b>,"ti,gain:0";
-+		chb_datarate =    <&channel_b>,"ti,datarate:0";
-+		chc_enable =      <0>,"=3";
-+		chc_cfg =         <&channel_c>,"reg:0";
-+		chc_gain =        <&channel_c>,"ti,gain:0";
-+		chc_datarate =    <&channel_c>,"ti,datarate:0";
-+		chd_enable =      <0>,"=4";
-+		chd_cfg =         <&channel_d>,"reg:0";
-+		chd_gain =        <&channel_d>,"ti,gain:0";
-+		chd_datarate =    <&channel_d>,"ti,datarate:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/ads7846-overlay.dts
-@@ -0,0 +1,89 @@
-+/*
-+ * Generic Device Tree overlay for the ADS7846 touch controller
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			ads7846_pins: ads7846_pins {
-+				brcm,pins = <255>; /* illegal default value */
-+				brcm,function = <0>; /* in */
-+				brcm,pull = <0>; /* none */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			ads7846: ads7846@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&ads7846_pins>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <255 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 255 0>;
-+
-+				/* driver defaults */
-+				ti,x-min = /bits/ 16 <0>;
-+				ti,y-min = /bits/ 16 <0>;
-+				ti,x-max = /bits/ 16 <0x0FFF>;
-+				ti,y-max = /bits/ 16 <0x0FFF>;
-+				ti,pressure-min = /bits/ 16 <0>;
-+				ti,pressure-max = /bits/ 16 <0xFFFF>;
-+				ti,x-plate-ohms = /bits/ 16 <400>;
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		cs =     <&ads7846>,"reg:0";
-+		speed =  <&ads7846>,"spi-max-frequency:0";
-+		penirq = <&ads7846_pins>,"brcm,pins:0", /* REQUIRED */
-+			 <&ads7846>,"interrupts:0",
-+			 <&ads7846>,"pendown-gpio:4";
-+		penirq_pull = <&ads7846_pins>,"brcm,pull:0";
-+		swapxy = <&ads7846>,"ti,swap-xy?";
-+		xmin =   <&ads7846>,"ti,x-min;0";
-+		ymin =   <&ads7846>,"ti,y-min;0";
-+		xmax =   <&ads7846>,"ti,x-max;0";
-+		ymax =   <&ads7846>,"ti,y-max;0";
-+		pmin =   <&ads7846>,"ti,pressure-min;0";
-+		pmax =   <&ads7846>,"ti,pressure-max;0";
-+		xohms =  <&ads7846>,"ti,x-plate-ohms;0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts
-@@ -0,0 +1,49 @@
-+// Definitions for Digital Dreamtime Akkordion using IQaudIO DAC+ or DACZero
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5122@4c {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4c>;
-+				AVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				CPVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		frag2: __overlay__ {
-+			compatible = "iqaudio,iqaudio-dac";
-+			card_name = "Akkordion";
-+			dai_name = "IQaudIO DAC";
-+			dai_stream_name = "IQaudIO DAC HiFi";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain = <&frag2>,"iqaudio,24db_digital_gain?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts
-@@ -0,0 +1,59 @@
-+/*
-+ * Definitions for Allo Boss DAC board
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/clocks";
-+		__overlay__ {
-+			boss_osc: boss_osc {
-+				compatible = "allo,dac-clk";
-+				#clock-cells = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5122@4d {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				clocks = <&boss_osc>;
-+				reg = <0x4d>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&sound>;
-+		boss_dac: __overlay__ {
-+			compatible = "allo,boss-dac";
-+			i2s-controller = <&i2s>;
-+			mute-gpios = <&gpio 6 1>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain = <&boss_dac>,"allo,24db_digital_gain?";
-+		slave = <&boss_dac>,"allo,slave?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/allo-digione-overlay.dts
-@@ -0,0 +1,44 @@
-+// Definitions for Allo DigiOne
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			wm8804@3b {
-+				#sound-dai-cells = <0>;
-+				compatible = "wlf,wm8804";
-+				reg = <0x3b>;
-+				PVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+				wlf,reset-gpio = <&gpio 17 0>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "allo,allo-digione";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+			clock44-gpio = <&gpio 5 0>;
-+			clock48-gpio = <&gpio 6 0>;
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts
-@@ -0,0 +1,54 @@
-+/*
-+ * Definitions for Allo Piano DAC (2.0/2.1) boards
-+ *
-+ * NB. The Piano DAC 2.1 board contains 2x TI PCM5142 DAC's. One DAC is stereo
-+ * (left/right) and the other provides a subwoofer output, using DSP on the
-+ * chip for digital high/low pass crossover.
-+ * The initial support for this hardware, that doesn't require any codec driver
-+ * modifications, uses only one DAC chip for stereo (left/right) output, the
-+ * chip with 0x4c slave address. The other chip at 0x4d is currently ignored!
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5142@4c {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5142";
-+				reg = <0x4c>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		piano_dac: __overlay__ {
-+			compatible = "allo,piano-dac";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain =
-+			<&piano_dac>,"allo,24db_digital_gain?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts
-@@ -0,0 +1,55 @@
-+// Definitions for Piano DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			allo_pcm5122_4c: pcm5122@4c {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4c>;
-+				status = "okay";
-+			};
-+			allo_pcm5122_4d: pcm5122@4d {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4d>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		piano_dac: __overlay__ {
-+			compatible = "allo,piano-dac-plus";
-+			audio-codec = <&allo_pcm5122_4c &allo_pcm5122_4d>;
-+			i2s-controller = <&i2s>;
-+			mute1-gpios = <&gpio 6 1>;
-+			mute2-gpios = <&gpio 25 1>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain =
-+			<&piano_dac>,"allo,24db_digital_gain?";
-+		glb_mclk =
-+			<&piano_dac>,"allo,glb_mclk?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/at86rf233-overlay.dts
-@@ -0,0 +1,57 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/* Overlay for Atmel AT86RF233 IEEE 802.15.4 WPAN transceiver on spi0.0 */
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "okay";
-+
-+			lowpan0: at86rf233@0 {
-+				compatible = "atmel,at86rf233";
-+				reg = <0>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <23 4>; /* active high */
-+				reset-gpio = <&gpio 24 1>;
-+				sleep-gpio = <&gpio 25 1>;
-+				spi-max-frequency = <3000000>;
-+				xtal-trim = /bits/ 8 <0xf>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			lowpan0_pins: lowpan0_pins {
-+				brcm,pins = <23 24 25>;
-+				brcm,function = <0 1 1>; /* in out out */
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		interrupt = <&lowpan0>, "interrupts:0",
-+			<&lowpan0_pins>, "brcm,pins:0";
-+		reset     = <&lowpan0>, "reset-gpio:4",
-+			<&lowpan0_pins>, "brcm,pins:4";
-+		sleep     = <&lowpan0>, "sleep-gpio:4",
-+			<&lowpan0_pins>, "brcm,pins:8";
-+		speed     = <&lowpan0>, "spi-max-frequency:0";
-+		trim      = <&lowpan0>, "xtal-trim.0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts
-@@ -0,0 +1,55 @@
-+// Definitions for audioinjector.net audio add on soundcard
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			cs42448: cs42448@48 {
-+				#sound-dai-cells = <0>;
-+				compatible = "cirrus,cs42448";
-+				reg = <0x48>;
-+				clocks = <&cs42448_mclk>;
-+				clock-names = "mclk";
-+				VA-supply = <&vdd_5v0_reg>;
-+				VD-supply = <&vdd_3v3_reg>;
-+				VLS-supply = <&vdd_3v3_reg>;
-+				VLC-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+
-+			cs42448_mclk: codec-mclk {
-+				compatible = "fixed-clock";
-+				#clock-cells = <0>;
-+				clock-frequency = <49152000>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "ai,audioinjector-octo-soundcard";
-+			mult-gpios = <&gpio 27 0>, <&gpio 22 0>, <&gpio 23 0>,
-+				     <&gpio 24 0>;
-+			reset-gpios = <&gpio 5 0>;
-+			i2s-controller = <&i2s>;
-+			codec = <&cs42448>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts
-@@ -0,0 +1,39 @@
-+// Definitions for audioinjector.net audio add on soundcard
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			wm8731@1a {
-+				#sound-dai-cells = <0>;
-+				compatible = "wlf,wm8731";
-+				reg = <0x1a>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "ai,audioinjector-pi-soundcard";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/audremap-overlay.dts
-@@ -0,0 +1,19 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+        compatible = "brcm,bcm2708";
-+
-+        fragment@0 {
-+                target = <&audio_pins>;
-+                frag0: __overlay__ {
-+                        brcm,pins = < 12 13 >;
-+                        brcm,function = < 4 >; /* alt0 alt0 */
-+                };
-+        };
-+
-+	__overrides__ {
-+		swap_lr = <&frag0>, "swap_lr?";
-+		enable_jack = <&frag0>, "enable_jack?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts
-@@ -0,0 +1,23 @@
-+// Definitions for BMP085/BMP180 digital barometric pressure and temperature sensors from Bosch Sensortec
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+        compatible = "brcm,bcm2708";
-+
-+        fragment@0 {
-+                target = <&i2c_arm>;
-+                __overlay__ {
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+                        status = "okay";
-+
-+                        bmp085@77 {
-+                                compatible = "bosch,bmp085";
-+                                reg = <0x77>;
-+                                default-oversampling = <3>;
-+                                status = "okay";
-+                        };
-+                };
-+        };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/dht11-overlay.dts
-@@ -0,0 +1,39 @@
-+/*
-+ * Overlay for the DHT11/21/22 humidity/temperature sensor modules.
-+ */
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+
-+			dht11: dht11@0 {
-+				compatible = "dht11";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&dht11_pins>;
-+				gpios = <&gpio 4 0>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			dht11_pins: dht11_pins {
-+				brcm,pins = <4>;
-+				brcm,function = <0>; // in
-+				brcm,pull = <0>; // off
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpiopin = <&dht11_pins>,"brcm,pins:0",
-+			<&dht11>,"gpios:4";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts
-@@ -0,0 +1,39 @@
-+// Definitions for Dion Audio LOCO DAC-AMP
-+
-+/*
-+ * PCM5242 DAC (in hardware mode) and TPA3118 AMP.
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/";
-+		__overlay__ {
-+			pcm5102a-codec {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5102a";
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "dionaudio,loco-pcm5242-tpa3118";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts
-@@ -0,0 +1,49 @@
-+/*
-+ * Definitions for Dion Audio LOCO-V2 DAC-AMP
-+ *  eg. dtoverlay=dionaudio-loco-v2
-+ *
-+ * PCM5242 DAC (in software mode) and TPA3255 AMP.
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&sound>;
-+		frag0: __overlay__ {
-+			compatible = "dionaudio,dionaudio-loco-v2";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5122@4c {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4d>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain = <&frag0>,"dionaudio,24db_digital_gain?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/dpi18-overlay.dts
-@@ -0,0 +1,31 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	// There is no DPI driver module, but we need a platform device
-+	// node (that doesn't already use pinctrl) to hang the pinctrl
-+	// reference on - leds will do
-+
-+	fragment@0 {
-+		target = <&leds>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&dpi18_pins>;
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			dpi18_pins: dpi18_pins {
-+				brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
-+					     12 13 14 15 16 17 18 19 20
-+					     21>;
-+				brcm,function = <6>; /* alt2 */
-+				brcm,pull = <0>; /* no pull */
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/dpi24-overlay.dts
-@@ -0,0 +1,31 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	// There is no DPI driver module, but we need a platform device
-+	// node (that doesn't already use pinctrl) to hang the pinctrl
-+	// reference on - leds will do
-+
-+	fragment@0 {
-+		target = <&leds>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&dpi24_pins>;
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			dpi24_pins: dpi24_pins {
-+				brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
-+					     12 13 14 15 16 17 18 19 20
-+					     21 22 23 24 25 26 27>;
-+				brcm,function = <6>; /* alt2 */
-+				brcm,pull = <0>; /* no pull */
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/dwc-otg-overlay.dts
-@@ -0,0 +1,20 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&usb>;
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		__overlay__ {
-+			compatible = "brcm,bcm2708-usb";
-+			reg = <0x7e980000 0x10000>,
-+			      <0x7e006000 0x1000>;
-+			interrupts = <2 0>,
-+				     <1 9>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/dwc2-overlay.dts
-@@ -0,0 +1,28 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&usb>;
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		dwc2_usb: __overlay__ {
-+			compatible = "brcm,bcm2835-usb";
-+			reg = <0x7e980000 0x10000>;
-+			interrupts = <1 9>;
-+			dr_mode = "otg";
-+			g-np-tx-fifo-size = <32>;
-+			g-rx-fifo-size = <256>;
-+			g-tx-fifo-size = <512 512 512 512 512 768>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		dr_mode = <&dwc2_usb>, "dr_mode";
-+		g-np-tx-fifo-size = <&dwc2_usb>,"g-np-tx-fifo-size:0";
-+		g-rx-fifo-size = <&dwc2_usb>,"g-rx-fifo-size:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/enc28j60-overlay.dts
-@@ -0,0 +1,53 @@
-+// Overlay for the Microchip ENC28J60 Ethernet Controller
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "okay";
-+
-+			eth1: enc28j60@0{
-+				compatible = "microchip,enc28j60";
-+				reg = <0>; /* CE0 */
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&eth1_pins>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <25 0x2>; /* falling edge */
-+				spi-max-frequency = <12000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			eth1_pins: eth1_pins {
-+				brcm,pins = <25>;
-+				brcm,function = <0>; /* in */
-+				brcm,pull = <0>; /* none */
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		int_pin = <&eth1>, "interrupts:0",
-+		          <&eth1_pins>, "brcm,pins:0";
-+		speed   = <&eth1>, "spi-max-frequency:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts
-@@ -0,0 +1,47 @@
-+// Overlay for the Microchip ENC28J60 Ethernet Controller - SPI2 Compute Module
-+// Interrupt pin: 39
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&spi2>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "okay";
-+
-+			eth1: enc28j60@0{
-+				compatible = "microchip,enc28j60";
-+				reg = <0>; /* CE0 */
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&eth1_pins>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <39 0x2>; /* falling edge */
-+				spi-max-frequency = <12000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			eth1_pins: eth1_pins {
-+				brcm,pins = <39>;
-+				brcm,function = <0>; /* in */
-+				brcm,pull = <0>; /* none */
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		int_pin = <&eth1>, "interrupts:0",
-+		          <&eth1_pins>, "brcm,pins:0";
-+		speed   = <&eth1>, "spi-max-frequency:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts
-@@ -0,0 +1,70 @@
-+// Definitions for Fe-Pi Audio
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&clocks>;
-+		__overlay__ {
-+			sgtl5000_mclk: sgtl5000_mclk {
-+				compatible = "fixed-clock";
-+				#clock-cells = <0>;
-+				clock-frequency = <12288000>;
-+				clock-output-names = "sgtl5000-mclk";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&soc>;
-+		__overlay__ {
-+			reg_1v8: reg_1v8@0 {
-+				compatible = "regulator-fixed";
-+				regulator-name = "1V8";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-always-on;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			sgtl5000@0a {
-+				#sound-dai-cells = <0>;
-+				compatible = "fepi,sgtl5000";
-+				reg = <0x0a>;
-+				clocks = <&sgtl5000_mclk>;
-+				micbias-resistor-k-ohms = <2>;
-+				micbias-voltage-m-volts = <3000>;
-+				VDDA-supply = <&vdd_3v3_reg>;
-+				VDDIO-supply = <&vdd_3v3_reg>;
-+				VDDD-supply = <&reg_1v8>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "fe-pi,fe-pi-audio";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/goodix-overlay.dts
-@@ -0,0 +1,46 @@
-+// Device tree overlay for I2C connected Goodix gt9271 multiple touch controller
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			goodix_pins: goodix_pins {
-+				brcm,pins = <4 17>; // interrupt and reset
-+				brcm,function = <0 0>; // in
-+				brcm,pull = <2 2>; // pull-up
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			gt9271: gt9271@14 {
-+				compatible = "goodix,gt9271";
-+				reg = <0x14>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&goodix_pins>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <4 2>; // high-to-low edge triggered
-+				irq-gpios = <&gpio 4 0>; // Pin7 on GPIO header
-+				reset-gpios = <&gpio 17 0>; // Pin11 on GPIO header
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		interrupt = <&goodix_pins>,"brcm,pins:0",
-+			<&gt9271>,"interrupts:0",
-+			<&gt9271>,"irq-gpios:4";
-+		reset = <&goodix_pins>,"brcm,pins:4",
-+			<&gt9271>,"reset-gpios:4";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts
-@@ -0,0 +1,49 @@
-+// Definitions for Google voiceHAT v1 soundcard overlay
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			googlevoicehat_pins: googlevoicehat_pins {
-+				brcm,pins = <16>;
-+				brcm,function = <1>; /* out */
-+				brcm,pull = <0>; /* up */
-+			};
-+		};
-+	};
-+
-+
-+	fragment@2 {
-+		target-path = "/";
-+		__overlay__ {
-+			voicehat-codec {
-+				#sound-dai-cells = <0>;
-+				compatible = "google,voicehat";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&googlevoicehat_pins>;
-+				sdmode-gpios= <&gpio 16 0>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "googlevoicehat,googlevoicehat-soundcard";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts
-@@ -0,0 +1,44 @@
-+// Definitions for ir-gpio module
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+        compatible = "brcm,bcm2708";
-+
-+        fragment@0 {
-+                target-path = "/";
-+                __overlay__ {
-+                        gpio_ir: ir-receiver {
-+                                compatible = "gpio-ir-receiver";
-+
-+                                // pin number, high or low
-+                                gpios = <&gpio 18 1>;
-+
-+                                // parameter for keymap name
-+                                linux,rc-map-name = "rc-rc6-mce";
-+
-+                                status = "okay";
-+                        };
-+                };
-+        };
-+
-+        fragment@1 {
-+                target = <&gpio>;
-+                __overlay__ {
-+                        gpio_ir_pins: gpio_ir_pins {
-+                                brcm,pins = <18>;                       // pin 18
-+                                brcm,function = <0>;                    // in
-+                                brcm,pull = <1>;                        // down
-+                        };
-+                };
-+        };
-+
-+        __overrides__ {
-+                // parameters
-+                gpio_pin =      <&gpio_ir>,"gpios:4",
-+                                        <&gpio_ir_pins>,"brcm,pins:0";  // pin number
-+                gpio_pull = <&gpio_ir_pins>,"brcm,pull:0";              // pull-up/down state
-+
-+                rc-map-name = <&gpio_ir>,"linux,rc-map-name";           // default rc map
-+        };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts
-@@ -0,0 +1,34 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			gpio_ir_tx_pins: gpio_ir_tx_pins {
-+				brcm,pins = <18>;
-+				brcm,function = <1>;	// out
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/";
-+		__overlay__ {
-+			gpio_ir_tx: gpio-ir-transmitter {
-+				compatible = "gpio-ir-tx";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&gpio_ir_tx_pins>;
-+				gpios = <&gpio 18 0>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpio_pin = <&gpio_ir_tx>, "gpios:4",
-+			   <&gpio_ir_tx_pins>, "brcm,pins:0";	// pin number
-+		invert = <&gpio_ir_tx>, "gpios:8";		// 1 = active low
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts
-@@ -0,0 +1,34 @@
-+// Definitions for gpio-poweroff module
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			power_ctrl: power_ctrl {
-+				compatible = "gpio-poweroff";
-+				gpios = <&gpio 26 0>;
-+				force;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			power_ctrl_pins: power_ctrl_pins {
-+				brcm,pins = <26>;
-+				brcm,function = <1>; // out
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpiopin =       <&power_ctrl>,"gpios:4",
-+				<&power_ctrl_pins>,"brcm,pins:0";
-+		active_low =    <&power_ctrl>,"gpios:8";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts
-@@ -0,0 +1,80 @@
-+// Definitions for gpio-poweroff module
-+/dts-v1/;
-+/plugin/;
-+
-+// This overlay sets up an input device that generates KEY_POWER events
-+// when a given GPIO pin changes. It defaults to using GPIO3, which can
-+// also be used to wake up (start) the Rpi again after shutdown. Since
-+// wakeup is active-low, this defaults to active-low with a pullup
-+// enabled, but all of this can be changed using overlay parameters (but
-+// note that GPIO3 has an external pullup on at least some boards).
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		// Configure the gpio pin controller
-+		target = <&gpio>;
-+		__overlay__ {
-+			// Define a pinctrl state, that sets up the gpio
-+			// as an input with a pullup enabled. This does
-+			// not take effect by itself, only when referenced
-+			// by a "pinctrl client", as is done below. See:
-+			//   https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
-+			//   https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
-+			pin_state: shutdown_button_pins {
-+				brcm,pins = <3>; // gpio number
-+				brcm,function = <0>; // 0 = input, 1 = output
-+				brcm,pull = <2>; // 0 = none, 1 = pull down, 2 = pull up
-+			};
-+		};
-+	};
-+	fragment@1 {
-+		// Add a new device to the /soc devicetree node
-+		target-path = "/soc";
-+		__overlay__ {
-+			shutdown_button {
-+				// Let the gpio-keys driver handle this device. See:
-+				// https://www.kernel.org/doc/Documentation/devicetree/bindings/input/gpio-keys.txt
-+				compatible = "gpio-keys";
-+
-+				// Declare a single pinctrl state (referencing the one declared above) and name it
-+				// default, so it is activated automatically.
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&pin_state>;
-+
-+				// Enable this device
-+				status = "okay";
-+
-+				// Define a single key, called "shutdown" that monitors the gpio and sends KEY_POWER
-+				// (keycode 116, see
-+				// https://github.com/torvalds/linux/blob/v4.12/include/uapi/linux/input-event-codes.h#L190)
-+				button: shutdown {
-+					label = "shutdown";
-+					linux,code = <116>; // KEY_POWER
-+					gpios = <&gpio 3 1>;
-+				};
-+			};
-+		};
-+	};
-+
-+	// This defines parameters that can be specified when loading
-+	// the overlay. Each foo = line specifies one parameter, named
-+	// foo. The rest of the specification gives properties where the
-+	// parameter value is inserted into (changing the values above
-+	// or adding new ones).
-+	__overrides__ {
-+		// Allow overriding the GPIO number.
-+		gpio_pin = <&button>,"gpios:4",
-+		           <&pin_state>,"brcm,pins:0";
-+
-+		// Allow changing the internal pullup/down state. 0 = none, 1 = pulldown, 2 = pullup
-+		// Note that GPIO3 and GPIO2 are the I2c pins and have an external pullup (at least
-+                // on some boards).
-+		gpio_pull = <&pin_state>,"brcm,pull:0";
-+
-+		// Allow setting the active_low flag. 0 = active high, 1 = active low
-+		active_low = <&button>,"gpios:8";
-+	};
-+
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts
-@@ -0,0 +1,39 @@
-+// Definitions for HiFiBerry Amp/Amp+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			tas5713@1b {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,tas5713";
-+				reg = <0x1b>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "hifiberry,hifiberry-amp";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts
-@@ -0,0 +1,34 @@
-+// Definitions for HiFiBerry DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/";
-+		__overlay__ {
-+			pcm5102a-codec {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5102a";
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "hifiberry,hifiberry-dac";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts
-@@ -0,0 +1,59 @@
-+// Definitions for HiFiBerry DAC+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/clocks";
-+		__overlay__ {
-+			dacpro_osc: dacpro_osc {
-+				compatible = "hifiberry,dacpro-clk";
-+				#clock-cells = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5122@4d {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4d>;
-+				clocks = <&dacpro_osc>;
-+				AVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				CPVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&sound>;
-+		hifiberry_dacplus: __overlay__ {
-+			compatible = "hifiberry,hifiberry-dacplus";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain =
-+			<&hifiberry_dacplus>,"hifiberry,24db_digital_gain?";
-+		slave = <&hifiberry_dacplus>,"hifiberry-dacplus,slave?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts
-@@ -0,0 +1,41 @@
-+// Definitions for HiFiBerry Digi
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			wm8804@3b {
-+				#sound-dai-cells = <0>;
-+				compatible = "wlf,wm8804";
-+				reg = <0x3b>;
-+				PVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "hifiberry,hifiberry-digi";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts
-@@ -0,0 +1,43 @@
-+// Definitions for HiFiBerry Digi Pro
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			wm8804@3b {
-+				#sound-dai-cells = <0>;
-+				compatible = "wlf,wm8804";
-+				reg = <0x3b>;
-+				PVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "hifiberry,hifiberry-digi";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+			clock44-gpio = <&gpio 5 0>;
-+			clock48-gpio = <&gpio 6 0>;
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hy28a-overlay.dts
-@@ -0,0 +1,93 @@
-+/*
-+ * Device Tree overlay for HY28A display
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			hy28a_pins: hy28a_pins {
-+				brcm,pins = <17 25 18>;
-+				brcm,function = <0 1 1>; /* in out out */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			hy28a: hy28a@0{
-+				compatible = "ilitek,ili9320";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&hy28a_pins>;
-+
-+				spi-max-frequency = <32000000>;
-+				spi-cpol;
-+				spi-cpha;
-+				rotate = <270>;
-+				bgr;
-+				fps = <50>;
-+				buswidth = <8>;
-+				startbyte = <0x70>;
-+				reset-gpios = <&gpio 25 0>;
-+				led-gpios = <&gpio 18 1>;
-+				debug = <0>;
-+			};
-+
-+			hy28a_ts: hy28a-ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <17 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 17 0>;
-+				ti,x-plate-ohms = /bits/ 16 <100>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		speed =		<&hy28a>,"spi-max-frequency:0";
-+		rotate =	<&hy28a>,"rotate:0";
-+		fps =		<&hy28a>,"fps:0";
-+		debug =		<&hy28a>,"debug:0";
-+		xohms =		<&hy28a_ts>,"ti,x-plate-ohms;0";
-+		resetgpio =	<&hy28a>,"reset-gpios:4",
-+				<&hy28a_pins>, "brcm,pins:1";
-+		ledgpio =	<&hy28a>,"led-gpios:4",
-+				<&hy28a_pins>, "brcm,pins:2";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hy28b-overlay.dts
-@@ -0,0 +1,148 @@
-+/*
-+ * Device Tree overlay for HY28b display shield by Texy
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			hy28b_pins: hy28b_pins {
-+				brcm,pins = <17 25 18>;
-+				brcm,function = <0 1 1>; /* in out out */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			hy28b: hy28b@0{
-+				compatible = "ilitek,ili9325";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&hy28b_pins>;
-+
-+				spi-max-frequency = <48000000>;
-+				spi-cpol;
-+				spi-cpha;
-+				rotate = <270>;
-+				bgr;
-+				fps = <50>;
-+				buswidth = <8>;
-+				startbyte = <0x70>;
-+				reset-gpios = <&gpio 25 0>;
-+				led-gpios = <&gpio 18 1>;
-+
-+				gamma = "04 1F 4 7 7 0 7 7 6 0\n0F 00 1 7 4 0 0 0 6 7";
-+
-+				init = <0x10000e7 0x0010
-+					0x1000000 0x0001
-+					0x1000001 0x0100
-+					0x1000002 0x0700
-+				        0x1000003 0x1030
-+					0x1000004 0x0000
-+					0x1000008 0x0207
-+					0x1000009 0x0000
-+				        0x100000a 0x0000
-+					0x100000c 0x0001
-+					0x100000d 0x0000
-+					0x100000f 0x0000
-+				        0x1000010 0x0000
-+					0x1000011 0x0007
-+					0x1000012 0x0000
-+					0x1000013 0x0000
-+				        0x2000032
-+					0x1000010 0x1590
-+					0x1000011 0x0227
-+				        0x2000032
-+					0x1000012 0x009c
-+				        0x2000032
-+				        0x1000013 0x1900
-+					0x1000029 0x0023
-+					0x100002b 0x000e
-+				        0x2000032
-+				        0x1000020 0x0000
-+					0x1000021 0x0000
-+				        0x2000032
-+					0x1000050 0x0000
-+				        0x1000051 0x00ef
-+					0x1000052 0x0000
-+					0x1000053 0x013f
-+					0x1000060 0xa700
-+				        0x1000061 0x0001
-+					0x100006a 0x0000
-+					0x1000080 0x0000
-+					0x1000081 0x0000
-+				        0x1000082 0x0000
-+					0x1000083 0x0000
-+					0x1000084 0x0000
-+					0x1000085 0x0000
-+				        0x1000090 0x0010
-+					0x1000092 0x0000
-+					0x1000093 0x0003
-+					0x1000095 0x0110
-+				        0x1000097 0x0000
-+					0x1000098 0x0000
-+					0x1000007 0x0133
-+					0x1000020 0x0000
-+				        0x1000021 0x0000
-+				        0x2000064>;
-+				debug = <0>;
-+			};
-+
-+			hy28b_ts: hy28b-ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <17 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 17 0>;
-+				ti,x-plate-ohms = /bits/ 16 <100>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		speed = 	<&hy28b>,"spi-max-frequency:0";
-+		rotate = 	<&hy28b>,"rotate:0";
-+		fps = 		<&hy28b>,"fps:0";
-+		debug = 	<&hy28b>,"debug:0";
-+		xohms =		<&hy28b_ts>,"ti,x-plate-ohms;0";
-+		resetgpio =	<&hy28b>,"reset-gpios:4",
-+				<&hy28b_pins>, "brcm,pins:1";
-+		ledgpio =	<&hy28b>,"led-gpios:4",
-+				<&hy28b_pins>, "brcm,pins:2";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts
-@@ -0,0 +1,13 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__overlay__ {
-+			compatible = "brcm,bcm2708-i2c";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts
-@@ -0,0 +1,43 @@
-+// Overlay for i2c_gpio bitbanging host bus.
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			i2c_gpio: i2c@0 {
-+				compatible = "i2c-gpio";
-+				gpios = <&gpio 23 0 /* sda */
-+					 &gpio 24 0 /* scl */
-+					>;
-+				i2c-gpio,delay-us = <2>;        /* ~100 kHz */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/aliases";
-+		__overlay__ {
-+			i2c_gpio = "/i2c@0";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "/__symbols__";
-+		__overlay__ {
-+			i2c_gpio = "/i2c@0";
-+		};
-+	};
-+
-+	__overrides__ {
-+		i2c_gpio_sda = <&i2c_gpio>,"gpios:4";
-+		i2c_gpio_scl = <&i2c_gpio>,"gpios:16";
-+		i2c_gpio_delay_us = <&i2c_gpio>,"i2c-gpio,delay-us:0";
-+	};
-+};
-+
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts
-@@ -0,0 +1,139 @@
-+// Umbrella I2C Mux overlay
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pca9542: mux@70 {
-+				compatible = "nxp,pca9542";
-+				reg = <0x70>;
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				i2c@0 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <0>;
-+				};
-+				i2c@1 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <1>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pca9545: mux@70 {
-+				compatible = "nxp,pca9545";
-+				reg = <0x70>;
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				i2c@0 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <0>;
-+				};
-+				i2c@1 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <1>;
-+				};
-+				i2c@2 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <2>;
-+				};
-+				i2c@3 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <3>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pca9548: mux@70 {
-+				compatible = "nxp,pca9548";
-+				reg = <0x70>;
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				i2c@0 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <0>;
-+				};
-+				i2c@1 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <1>;
-+				};
-+				i2c@2 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <2>;
-+				};
-+				i2c@3 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <3>;
-+				};
-+				i2c@4 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <4>;
-+				};
-+				i2c@5 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <5>;
-+				};
-+				i2c@6 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <6>;
-+				};
-+				i2c@7 {
-+					#address-cells = <1>;
-+					#size-cells = <0>;
-+					reg = <7>;
-+				};
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		pca9542 = <0>, "+0";
-+		pca9545 = <0>, "+1";
-+		pca9548 = <0>, "+2";
-+
-+		addr =  <&pca9542>,"reg:0",
-+			<&pca9545>,"reg:0",
-+			<&pca9548>,"reg:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts
-@@ -0,0 +1,26 @@
-+// Definitions for NXP PCA9685A I2C PWM controller on ARM I2C bus.
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pca: pca@40 {
-+				compatible = "nxp,pca9685";
-+				#pwm-cells = <2>;
-+				reg = <0x40>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		addr = <&pca>,"reg:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts
-@@ -0,0 +1,183 @@
-+// Definitions for several I2C based Real Time Clocks
-+// Available through i2c-gpio
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			i2c_gpio: i2c-gpio-rtc@0 {
-+				compatible = "i2c-gpio";
-+				gpios = <&gpio 23 0 /* sda */
-+					 &gpio 24 0 /* scl */
-+					>;
-+				i2c-gpio,delay-us = <2>;        /* ~100 kHz */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			abx80x: abx80x@69 {
-+				compatible = "abracon,abx80x";
-+				reg = <0x69>;
-+				abracon,tc-diode = "standard";
-+				abracon,tc-resistor = <0>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ds1307: ds1307@68 {
-+				compatible = "maxim,ds1307";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ds1339: ds1339@68 {
-+				compatible = "dallas,ds1339";
-+				trickle-resistor-ohms = <0>;
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ds3231: ds3231@68 {
-+				compatible = "maxim,ds3231";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@5 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			mcp7940x: mcp7940x@6f {
-+				compatible = "microchip,mcp7940x";
-+				reg = <0x6f>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@6 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			mcp7941x: mcp7941x@6f {
-+				compatible = "microchip,mcp7941x";
-+				reg = <0x6f>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@7 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcf2127: pcf2127@51 {
-+				compatible = "nxp,pcf2127";
-+				reg = <0x51>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@8 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcf8523: pcf8523@68 {
-+				compatible = "nxp,pcf8523";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@9 {
-+		target = <&i2c_gpio>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcf8563: pcf8563@51 {
-+				compatible = "nxp,pcf8563";
-+				reg = <0x51>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		abx80x = <0>,"+1";
-+		ds1307 = <0>,"+2";
-+		ds1339 = <0>,"+3";
-+		ds3231 = <0>,"+4";
-+		mcp7940x = <0>,"+5";
-+		mcp7941x = <0>,"+6";
-+		pcf2127 = <0>,"+7";
-+		pcf8523 = <0>,"+8";
-+		pcf8563 = <0>,"+9";
-+		trickle-diode-type = <&abx80x>,"abracon,tc-diode";
-+		trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0",
-+					<&abx80x>,"abracon,tc-resistor";
-+		wakeup-source = <&ds1339>,"wakeup-source?",
-+				<&ds3231>,"wakeup-source?",
-+				<&mcp7940x>,"wakeup-source?",
-+					<&mcp7941x>,"wakeup-source?";
-+		i2c_gpio_sda = <&i2c_gpio>,"gpios:4";
-+		i2c_gpio_scl = <&i2c_gpio>,"gpios:16";
-+		i2c_gpio_delay_us = <&i2c_gpio>,"i2c-gpio,delay-us:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts
-@@ -0,0 +1,181 @@
-+// Definitions for several I2C based Real Time Clocks
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			abx80x: abx80x@69 {
-+				compatible = "abracon,abx80x";
-+				reg = <0x69>;
-+				abracon,tc-diode = "standard";
-+				abracon,tc-resistor = <0>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ds1307: ds1307@68 {
-+				compatible = "maxim,ds1307";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ds1339: ds1339@68 {
-+				compatible = "dallas,ds1339";
-+				trickle-resistor-ohms = <0>;
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ds3231: ds3231@68 {
-+				compatible = "maxim,ds3231";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			mcp7940x: mcp7940x@6f {
-+				compatible = "microchip,mcp7940x";
-+				reg = <0x6f>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@5 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			mcp7941x: mcp7941x@6f {
-+				compatible = "microchip,mcp7941x";
-+				reg = <0x6f>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@6 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcf2127: pcf2127@51 {
-+				compatible = "nxp,pcf2127";
-+				reg = <0x51>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@7 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcf8523: pcf8523@68 {
-+				compatible = "nxp,pcf8523";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@8 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcf8563: pcf8563@51 {
-+				compatible = "nxp,pcf8563";
-+				reg = <0x51>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@9 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			m41t62: m41t62@68 {
-+				compatible = "st,m41t62";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		abx80x = <0>,"+0";
-+		ds1307 = <0>,"+1";
-+		ds1339 = <0>,"+2";
-+		ds3231 = <0>,"+3";
-+		mcp7940x = <0>,"+4";
-+		mcp7941x = <0>,"+5";
-+		pcf2127 = <0>,"+6";
-+		pcf8523 = <0>,"+7";
-+		pcf8563 = <0>,"+8";
-+		m41t62 = <0>,"+9";
-+		trickle-diode-type = <&abx80x>,"abracon,tc-diode";
-+		trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0",
-+					<&abx80x>,"abracon,tc-resistor";
-+		wakeup-source = <&ds1339>,"wakeup-source?",
-+				<&ds3231>,"wakeup-source?",
-+				<&mcp7940x>,"wakeup-source?",
-+				<&mcp7941x>,"wakeup-source?",
-+				<&m41t62>,"wakeup-source?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts
-@@ -0,0 +1,206 @@
-+// Definitions for I2C based sensors using the Industrial IO or HWMON interface.
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			bme280: bme280@76 {
-+				compatible = "bosch,bme280";
-+				reg = <0x76>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			bmp085: bmp085@77 {
-+				compatible = "bosch,bmp085";
-+				reg = <0x77>;
-+				default-oversampling = <3>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			bmp180: bmp180@77 {
-+				compatible = "bosch,bmp180";
-+				reg = <0x77>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			bmp280: bmp280@76 {
-+				compatible = "bosch,bmp280";
-+				reg = <0x76>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			htu21: htu21@40 {
-+				compatible = "htu21";
-+				reg = <0x40>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@5 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			lm75: lm75@4f {
-+				compatible = "lm75";
-+				reg = <0x4f>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@6 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			si7020: si7020@40 {
-+				compatible = "si7020";
-+				reg = <0x40>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@7 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			tmp102: tmp102@48 {
-+				compatible = "ti,tmp102";
-+				reg = <0x48>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@8 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			hdc100x: hdc100x@40 {
-+				compatible = "hdc100x";
-+				reg = <0x40>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@9 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			tsl4531: tsl4531@29 {
-+				compatible = "tsl4531";
-+				reg = <0x29>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@10 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			veml6070: veml6070@38 {
-+				compatible = "veml6070";
-+				reg = <0x38>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@11 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			sht3x: sht3x@44 {
-+				compatible = "sht3x";
-+				reg = <0x44>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		addr =  <&bme280>,"reg:0", <&bmp280>,"reg:0", <&tmp102>,"reg:0",
-+			<&lm75>,"reg:0", <&hdc100x>,"reg:0", <&sht3x>,"reg:0";
-+		bme280 = <0>,"+0";
-+		bmp085 = <0>,"+1";
-+		bmp180 = <0>,"+2";
-+		bmp280 = <0>,"+3";
-+		htu21 = <0>,"+4";
-+		lm75 = <0>,"+5";
-+		lm75addr = <&lm75>,"reg:0";
-+		si7020 = <0>,"+6";
-+		tmp102 = <0>,"+7";
-+		hdc100x = <0>,"+8";
-+		tsl4531 = <0>,"+9";
-+		veml6070 = <0>,"+10";
-+		sht3x = <0>,"+11";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c0-bcm2708-overlay.dts
-@@ -0,0 +1,61 @@
-+/*
-+ * Device tree overlay for i2c_bcm2708, i2c0 bus
-+ *
-+ * Compile:
-+ * dtc -@ -I dts -O dtb -o i2c0-bcm2708-overlay.dtb i2c0-bcm2708-overlay.dts
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+   compatible = "brcm,bcm2708";
-+
-+   fragment@0 {
-+      target = <&i2c0>;
-+      __overlay__ {
-+         status = "okay";
-+      };
-+   };
-+
-+   fragment@1 {
-+      target = <&i2c0_pins>;
-+      frag1: __overlay__ {
-+         brcm,pins = <0 1>;
-+         brcm,function = <4>; /* alt0 */
-+      };
-+   };
-+
-+   fragment@2 {
-+      target = <&i2c0_pins>;
-+      __dormant__ {
-+         brcm,pins = <28 29>;
-+         brcm,function = <4>; /* alt0 */
-+      };
-+   };
-+
-+   fragment@3 {
-+      target = <&i2c0_pins>;
-+      __dormant__ {
-+         brcm,pins = <44 45>;
-+         brcm,function = <5>; /* alt1 */
-+      };
-+   };
-+
-+   fragment@4 {
-+      target = <&i2c0_pins>;
-+      __dormant__ {
-+         brcm,pins = <46 47>;
-+         brcm,function = <4>; /* alt0 */
-+      };
-+   };
-+
-+   __overrides__ {
-+      sda0_pin = <&frag1>,"brcm,pins:0";
-+      scl0_pin = <&frag1>,"brcm,pins:4";
-+      pins_0_1   = <0>,"+1-2-3-4";
-+      pins_28_29 = <0>,"-1+2-3-4";
-+      pins_44_45 = <0>,"-1-2+3-4";
-+      pins_46_47 = <0>,"-1-2-3+4";
-+   };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2c1-bcm2708-overlay.dts
-@@ -0,0 +1,34 @@
-+/*
-+ * Device tree overlay for i2c_bcm2708, i2c1 bus
-+ *
-+ * Compile:
-+ * dtc -@ -I dts -O dtb -o i2c1-bcm2708-overlay.dtb i2c1-bcm2708-overlay.dts
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+   compatible = "brcm,bcm2708";
-+
-+   fragment@0 {
-+      target = <&i2c1>;
-+      __overlay__ {
-+         pinctrl-0 = <&i2c1_pins>;
-+         status = "okay";
-+      };
-+   };
-+
-+   fragment@1 {
-+      target = <&i2c1_pins>;
-+         pins: __overlay__ {
-+         brcm,pins = <2 3>;
-+         brcm,function = <4>; /* alt 0 */
-+      };
-+   };
-+   __overrides__ {
-+      sda1_pin = <&pins>,"brcm,pins:0";
-+      scl1_pin = <&pins>,"brcm,pins:4";
-+      pin_func = <&pins>,"brcm,function:0";
-+   };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts
-@@ -0,0 +1,18 @@
-+/*
-+ * Device tree overlay to move i2s to gpio 28 to 31 on CM
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&i2s_pins>;
-+		__overlay__ {
-+			brcm,pins = <28 29 30 31>;
-+			brcm,function = <6>; /* alt2 */
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts
-@@ -0,0 +1,46 @@
-+// Definitions for IQaudIO DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5122@4c {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4c>;
-+				AVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				CPVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		frag2: __overlay__ {
-+			compatible = "iqaudio,iqaudio-dac";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain = <&frag2>,"iqaudio,24db_digital_gain?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts
-@@ -0,0 +1,49 @@
-+// Definitions for IQaudIO DAC+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5122@4c {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4c>;
-+				AVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				CPVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		iqaudio_dac: __overlay__ {
-+			compatible = "iqaudio,iqaudio-dac";
-+			i2s-controller = <&i2s>;
-+			mute-gpios = <&gpio 22 0>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain = <&iqaudio_dac>,"iqaudio,24db_digital_gain?";
-+		auto_mute_amp = <&iqaudio_dac>,"iqaudio-dac,auto-mute-amp?";
-+		unmute_amp = <&iqaudio_dac>,"iqaudio-dac,unmute-amp?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts
-@@ -0,0 +1,47 @@
-+// Definitions for IQAudIO Digi WM8804 audio board
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			wm8804@3b {
-+				#sound-dai-cells = <0>;
-+				compatible = "wlf,wm8804";
-+				reg = <0x3b>;
-+				status = "okay";
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				PVDD-supply = <&vdd_3v3_reg>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		wm8804_digi: __overlay__ {
-+			compatible = "iqaudio,wm8804-digi";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		card_name = <&wm8804_digi>,"wm8804-digi,card-name";
-+		dai_name = <&wm8804_digi>,"wm8804-digi,dai-name";
-+		dai_stream_name = <&wm8804_digi>,"wm8804-digi,dai-stream-name";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts
-@@ -0,0 +1,46 @@
-+// Definitions for JustBoom DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5122@4d {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4d>;
-+				AVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				CPVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		frag2: __overlay__ {
-+			compatible = "justboom,justboom-dac";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		24db_digital_gain = <&frag2>,"justboom,24db_digital_gain?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts
-@@ -0,0 +1,41 @@
-+// Definitions for JustBoom Digi
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			wm8804@3b {
-+				#sound-dai-cells = <0>;
-+				compatible = "wlf,wm8804";
-+				reg = <0x3b>;
-+				PVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "justboom,justboom-digi";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts
-@@ -0,0 +1,57 @@
-+// Definitions for lirc-rpi module
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			lirc_rpi: lirc_rpi {
-+				compatible = "rpi,lirc-rpi";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&lirc_pins>;
-+				status = "okay";
-+
-+				// Override autodetection of IR receiver circuit
-+				// (0 = active high, 1 = active low, -1 = no override )
-+				rpi,sense = <0xffffffff>;
-+
-+				// Software carrier
-+				// (0 = off, 1 = on)
-+				rpi,softcarrier = <1>;
-+
-+				// Invert output
-+				// (0 = off, 1 = on)
-+				rpi,invert = <0>;
-+
-+				// Enable debugging messages
-+				// (0 = off, 1 = on)
-+				rpi,debug = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			lirc_pins: lirc_pins {
-+				brcm,pins = <17 18>;
-+				brcm,function = <1 0>; // out in
-+				brcm,pull = <0 1>; // off down
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpio_out_pin =  <&lirc_pins>,"brcm,pins:0";
-+		gpio_in_pin =   <&lirc_pins>,"brcm,pins:4";
-+		gpio_in_pull =  <&lirc_pins>,"brcm,pull:4";
-+
-+		sense =         <&lirc_rpi>,"rpi,sense:0";
-+		softcarrier =   <&lirc_rpi>,"rpi,softcarrier:0";
-+		invert =        <&lirc_rpi>,"rpi,invert:0";
-+		debug =         <&lirc_rpi>,"rpi,debug:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mcp23017-overlay.dts
-@@ -0,0 +1,54 @@
-+// Definitions for MCP23017 Gpio Extender from Microchip Semiconductor
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			mcp23017_pins: mcp23017_pins {
-+				brcm,pins = <4>;
-+				brcm,function = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp23017: mcp@20 {
-+				compatible = "microchip,mcp23017";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells=<2>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <4 2>;
-+				interrupt-controller;
-+				microchip,irq-mirror;
-+
-+				status = "okay";
-+			};
-+		};
-+	};
-+	
-+	__overrides__ {
-+		gpiopin = <&mcp23017_pins>,"brcm,pins:0",
-+				<&mcp23017>,"interrupts:0";
-+		addr = <&mcp23017>,"reg:0";
-+	};
-+};
-+
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts
-@@ -0,0 +1,732 @@
-+// Overlay for MCP23S08/17 GPIO Extenders from Microchip Semiconductor
-+
-+// dtparams:
-+//     s08-spi<n>-<m>-present  - 4-bit integer, bitmap indicating MCP23S08 devices present on SPI<n>, CS#<m>.
-+//     s17-spi<n>-<m>-present  - 8-bit integer, bitmap indicating MCP23S17 devices present on SPI<n>, CS#<m>.
-+//     s08-spi<n>-<m>-int-gpio - integer, enables interrupts on a single MCP23S08 device on SPI<n>, CS#<m>, specifies the GPIO pin to which INT output is connected.
-+//     s17-spi<n>-<m>-int-gpio - integer, enables mirrored interrupts on a single MCP23S17 device on SPI<n>, CS#<m>, specifies the GPIO pin to which either INTA or INTB output is connected.
-+//
-+// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
-+// If interrupts are enabled for a device on a given CS# on a SPI bus, that device must be the only one present on that SPI bus/CS#.
-+//
-+// Example 1: A single MCP23S17 device on SPI0, CS#0 with its SPI addr set to 0 and INTA output connected to GPIO25:
-+// dtoverlay=mcp23s17:s17-spi0-0-present=1,s17-spi0-0-int-gpio=25
-+//
-+// Example 2: Two MCP23S08 devices on SPI1, CS#0 with their addrs set to 2 and 3. Three MCP23S17 devices on SPI1, CS#1 with their addrs set to 0, 1 and 7:
-+// dtoverlay=spi1-2cs
-+// dtoverlay=mcp23s17:s08-spi1-0-present=12,s17-spi1-1-present=131
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	// disable spi-dev on spi0.0
-+	fragment@0 {
-+		target = <&spidev0>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi0.1
-+	fragment@1 {
-+		target = <&spidev1>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi1.0
-+	fragment@2 {
-+		target-path = "spi1/spidev@0";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi1.1
-+	fragment@3 {
-+		target-path = "spi1/spidev@1";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi1.2
-+	fragment@4 {
-+		target-path = "spi1/spidev@2";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi2.0
-+	fragment@5 {
-+		target-path = "spi2/spidev@0";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi2.1
-+	fragment@6 {
-+		target-path = "spi2/spidev@1";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi2.2
-+	fragment@7 {
-+		target-path = "spi2/spidev@2";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// enable one or more mcp23s08s on spi0.0
-+	fragment@8 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s08_00: mcp23s08@0 {
-+				compatible = "microchip,mcp23s08";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi0-0-present parameter */
-+     				reg = <0>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi0-0-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s08s on spi0.1
-+	fragment@9 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s08_01: mcp23s08@1 {
-+				compatible = "microchip,mcp23s08";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi0-1-present parameter */
-+     				reg = <1>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi0-1-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s08s on spi1.0
-+	fragment@10 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s08_10: mcp23s08@0 {
-+				compatible = "microchip,mcp23s08";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-0-present parameter */
-+     				reg = <0>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-0-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s08s on spi1.1
-+	fragment@11 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s08_11: mcp23s08@1 {
-+				compatible = "microchip,mcp23s08";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-1-present parameter */
-+     				reg = <1>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-1-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s08s on spi1.2
-+	fragment@12 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s08_12: mcp23s08@2 {
-+				compatible = "microchip,mcp23s08";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-2-present parameter */
-+     				reg = <2>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-2-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s08s on spi2.0
-+	fragment@13 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s08_20: mcp23s08@0 {
-+				compatible = "microchip,mcp23s08";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-0-present parameter */
-+     				reg = <0>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-0-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s08s on spi2.1
-+	fragment@14 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s08_21: mcp23s08@1 {
-+				compatible = "microchip,mcp23s08";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-1-present parameter */
-+     				reg = <1>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-1-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s08s on spi2.2
-+	fragment@15 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s08_22: mcp23s08@2 {
-+				compatible = "microchip,mcp23s08";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-2-present parameter */
-+     				reg = <2>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-2-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s17s on spi0.0
-+	fragment@16 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s17_00: mcp23s17@0 {
-+				compatible = "microchip,mcp23s17";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi0-0-present parameter */
-+     				reg = <0>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi0-0-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s17s on spi0.1
-+	fragment@17 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s17_01: mcp23s17@1 {
-+				compatible = "microchip,mcp23s17";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi0-1-present parameter */
-+     				reg = <1>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi0-1-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s17s on spi1.0
-+	fragment@18 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s17_10: mcp23s17@0 {
-+				compatible = "microchip,mcp23s17";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-0-present parameter */
-+     				reg = <0>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-0-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s17s on spi1.1
-+	fragment@19 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s17_11: mcp23s17@1 {
-+				compatible = "microchip,mcp23s17";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-1-present parameter */
-+     				reg = <1>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-1-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s17s on spi1.2
-+	fragment@20 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s17_12: mcp23s17@2 {
-+				compatible = "microchip,mcp23s17";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-2-present parameter */
-+     				reg = <2>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-2-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s17s on spi2.0
-+	fragment@21 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s17_20: mcp23s17@0 {
-+				compatible = "microchip,mcp23s17";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-0-present parameter */
-+     				reg = <0>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-0-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s17s on spi2.1
-+	fragment@22 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s17_21: mcp23s17@1 {
-+				compatible = "microchip,mcp23s17";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-1-present parameter */
-+     				reg = <1>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-1-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// enable one or more mcp23s17s on spi2.2
-+	fragment@23 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			mcp23s17_22: mcp23s17@2 {
-+				compatible = "microchip,mcp23s17";
-+  				gpio-controller;
-+  				#gpio-cells = <2>;
-+    				microchip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-2-present parameter */
-+     				reg = <2>;
-+    				spi-max-frequency = <500000>;
-+				status = "okay";
-+				#interrupt-cells=<2>;
-+				interrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-2-int-gpio parameter */
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.0 as a input with no pull-up/down
-+	fragment@24 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			spi0_0_int_pins: spi0_0_int_pins {
-+				brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi0-0-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.1 as a input with no pull-up/down
-+	fragment@25 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			spi0_1_int_pins: spi0_1_int_pins {
-+				brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi0-1-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.0 as a input with no pull-up/down
-+	fragment@26 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			spi1_0_int_pins: spi1_0_int_pins {
-+				brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-0-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.1 as a input with no pull-up/down
-+	fragment@27 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			spi1_1_int_pins: spi1_1_int_pins {
-+				brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-1-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.2 as a input with no pull-up/down
-+	fragment@28 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			spi1_2_int_pins: spi1_2_int_pins {
-+				brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-2-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.0 as a input with no pull-up/down
-+	fragment@29 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			spi2_0_int_pins: spi2_0_int_pins {
-+				brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-0-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.1 as a input with no pull-up/down
-+	fragment@30 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			spi2_1_int_pins: spi2_1_int_pins {
-+				brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-1-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.2 as a input with no pull-up/down
-+	fragment@31 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			spi2_2_int_pins: spi2_2_int_pins {
-+				brcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-2-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s08 on spi0.0.
-+	// Use default active low interrupt signalling.
-+	fragment@32 {
-+		target = <&mcp23s08_00>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s08 on spi0.1.
-+	// Use default active low interrupt signalling.
-+	fragment@33 {
-+		target = <&mcp23s08_01>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s08 on spi1.0.
-+	// Use default active low interrupt signalling.
-+	fragment@34 {
-+		target = <&mcp23s08_10>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s08 on spi1.1.
-+	// Use default active low interrupt signalling.
-+	fragment@35 {
-+		target = <&mcp23s08_11>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s08 on spi1.2.
-+	// Use default active low interrupt signalling.
-+	fragment@36 {
-+		target = <&mcp23s08_12>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s08 on spi2.0.
-+	// Use default active low interrupt signalling.
-+	fragment@37 {
-+		target = <&mcp23s08_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s08 on spi2.1.
-+	// Use default active low interrupt signalling.
-+	fragment@38 {
-+		target = <&mcp23s08_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s08 on spi2.2.
-+	// Use default active low interrupt signalling.
-+	fragment@39 {
-+		target = <&mcp23s08_22>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s17 on spi0.0.
-+	// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
-+	// Use default active low interrupt signalling.
-+	fragment@40 {
-+		target = <&mcp23s17_00>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			microchip,irq-mirror;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s17 on spi0.1.
-+	// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
-+	// Configure INTA/B outputs of mcp23s08/17 as active low.
-+	fragment@41 {
-+		target = <&mcp23s17_01>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			microchip,irq-mirror;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s17 on spi1.0.
-+	// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
-+	// Configure INTA/B outputs of mcp23s08/17 as active low.
-+	fragment@42 {
-+		target = <&mcp23s17_10>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			microchip,irq-mirror;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s17 on spi1.1.
-+	// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
-+	// Configure INTA/B outputs of mcp23s08/17 as active low.
-+	fragment@43 {
-+		target = <&mcp23s17_11>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			microchip,irq-mirror;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s17 on spi1.2.
-+	// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
-+	// Configure INTA/B outputs of mcp23s08/17 as active low.
-+	fragment@44 {
-+		target = <&mcp23s17_12>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			microchip,irq-mirror;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s17 on spi2.0.
-+	// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
-+	// Configure INTA/B outputs of mcp23s08/17 as active low.
-+	fragment@45 {
-+		target = <&mcp23s17_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			microchip,irq-mirror;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s17 on spi2.1.
-+	// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
-+	// Configure INTA/B outputs of mcp23s08/17 as active low.
-+	fragment@46 {
-+		target = <&mcp23s17_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			microchip,irq-mirror;
-+		};
-+	};
-+
-+	// Enable interrupts for a mcp23s17 on spi2.2.
-+	// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
-+	// Configure INTA/B outputs of mcp23s08/17 as active low.
-+	fragment@47 {
-+		target = <&mcp23s17_22>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			microchip,irq-mirror;
-+		};
-+	};
-+
-+	__overrides__ {
-+		s08-spi0-0-present = <0>,"+0+8",  <&mcp23s08_00>,"microchip,spi-present-mask:0";
-+		s08-spi0-1-present = <0>,"+1+9",  <&mcp23s08_01>,"microchip,spi-present-mask:0";
-+		s08-spi1-0-present = <0>,"+2+10", <&mcp23s08_10>,"microchip,spi-present-mask:0";
-+		s08-spi1-1-present = <0>,"+3+11", <&mcp23s08_11>,"microchip,spi-present-mask:0";
-+		s08-spi1-2-present = <0>,"+4+12", <&mcp23s08_12>,"microchip,spi-present-mask:0";
-+		s08-spi2-0-present = <0>,"+5+13", <&mcp23s08_20>,"microchip,spi-present-mask:0";
-+		s08-spi2-1-present = <0>,"+6+14", <&mcp23s08_21>,"microchip,spi-present-mask:0";
-+		s08-spi2-2-present = <0>,"+7+15", <&mcp23s08_22>,"microchip,spi-present-mask:0";
-+		s17-spi0-0-present = <0>,"+0+16", <&mcp23s17_00>,"microchip,spi-present-mask:0";
-+		s17-spi0-1-present = <0>,"+1+17", <&mcp23s17_01>,"microchip,spi-present-mask:0";
-+		s17-spi1-0-present = <0>,"+2+18", <&mcp23s17_10>,"microchip,spi-present-mask:0";
-+		s17-spi1-1-present = <0>,"+3+19", <&mcp23s17_11>,"microchip,spi-present-mask:0";
-+		s17-spi1-2-present = <0>,"+4+20", <&mcp23s17_12>,"microchip,spi-present-mask:0";
-+		s17-spi2-0-present = <0>,"+5+21", <&mcp23s17_20>,"microchip,spi-present-mask:0";
-+		s17-spi2-1-present = <0>,"+6+22", <&mcp23s17_21>,"microchip,spi-present-mask:0";
-+		s17-spi2-2-present = <0>,"+7+23", <&mcp23s17_22>,"microchip,spi-present-mask:0";
-+		s08-spi0-0-int-gpio = <0>,"+24+32", <&spi0_0_int_pins>,"brcm,pins:0", <&mcp23s08_00>,"interrupts:0";
-+		s08-spi0-1-int-gpio = <0>,"+25+33", <&spi0_1_int_pins>,"brcm,pins:0", <&mcp23s08_01>,"interrupts:0";
-+		s08-spi1-0-int-gpio = <0>,"+26+34", <&spi1_0_int_pins>,"brcm,pins:0", <&mcp23s08_10>,"interrupts:0";
-+		s08-spi1-1-int-gpio = <0>,"+27+35", <&spi1_1_int_pins>,"brcm,pins:0", <&mcp23s08_11>,"interrupts:0";
-+		s08-spi1-2-int-gpio = <0>,"+28+36", <&spi1_2_int_pins>,"brcm,pins:0", <&mcp23s08_12>,"interrupts:0";
-+		s08-spi2-0-int-gpio = <0>,"+29+37", <&spi2_0_int_pins>,"brcm,pins:0", <&mcp23s08_20>,"interrupts:0";
-+		s08-spi2-1-int-gpio = <0>,"+30+38", <&spi2_1_int_pins>,"brcm,pins:0", <&mcp23s08_21>,"interrupts:0";
-+		s08-spi2-2-int-gpio = <0>,"+31+39", <&spi2_2_int_pins>,"brcm,pins:0", <&mcp23s08_22>,"interrupts:0";
-+		s17-spi0-0-int-gpio = <0>,"+24+40", <&spi0_0_int_pins>,"brcm,pins:0", <&mcp23s17_00>,"interrupts:0";
-+		s17-spi0-1-int-gpio = <0>,"+25+41", <&spi0_1_int_pins>,"brcm,pins:0", <&mcp23s17_01>,"interrupts:0";
-+		s17-spi1-0-int-gpio = <0>,"+26+42", <&spi1_0_int_pins>,"brcm,pins:0", <&mcp23s17_10>,"interrupts:0";
-+		s17-spi1-1-int-gpio = <0>,"+27+43", <&spi1_1_int_pins>,"brcm,pins:0", <&mcp23s17_11>,"interrupts:0";
-+		s17-spi1-2-int-gpio = <0>,"+28+44", <&spi1_2_int_pins>,"brcm,pins:0", <&mcp23s17_12>,"interrupts:0";
-+		s17-spi2-0-int-gpio = <0>,"+29+45", <&spi2_0_int_pins>,"brcm,pins:0", <&mcp23s17_20>,"interrupts:0";
-+		s17-spi2-1-int-gpio = <0>,"+30+46", <&spi2_1_int_pins>,"brcm,pins:0", <&mcp23s17_21>,"interrupts:0";
-+		s17-spi2-2-int-gpio = <0>,"+31+47", <&spi2_2_int_pins>,"brcm,pins:0", <&mcp23s17_22>,"interrupts:0";
-+	};
-+};
-+
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts
-@@ -0,0 +1,73 @@
-+/*
-+ * Device tree overlay for mcp251x/can0 on spi0.0
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+    compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
-+    /* disable spi-dev for spi0.0 */
-+    fragment@0 {
-+        target = <&spi0>;
-+        __overlay__ {
-+            status = "okay";
-+        };
-+    };
-+
-+    fragment@1 {
-+	target = <&spidev0>;
-+	__overlay__ {
-+	    status = "disabled";
-+	};
-+    };
-+
-+    /* the interrupt pin of the can-controller */
-+    fragment@2 {
-+        target = <&gpio>;
-+        __overlay__ {
-+            can0_pins: can0_pins {
-+                brcm,pins = <25>;
-+                brcm,function = <0>; /* input */
-+            };
-+        };
-+    };
-+
-+    /* the clock/oscillator of the can-controller */
-+    fragment@3 {
-+        target-path = "/clocks";
-+        __overlay__ {
-+            /* external oscillator of mcp2515 on SPI0.0 */
-+            can0_osc: can0_osc {
-+                compatible = "fixed-clock";
-+                #clock-cells = <0>;
-+                clock-frequency  = <16000000>;
-+            };
-+        };
-+    };
-+
-+    /* the spi config of the can-controller itself binding everything together */
-+    fragment@4 {
-+        target = <&spi0>;
-+        __overlay__ {
-+            /* needed to avoid dtc warning */
-+            #address-cells = <1>;
-+            #size-cells = <0>;
-+            can0: mcp2515@0 {
-+                reg = <0>;
-+                compatible = "microchip,mcp2515";
-+                pinctrl-names = "default";
-+                pinctrl-0 = <&can0_pins>;
-+                spi-max-frequency = <10000000>;
-+                interrupt-parent = <&gpio>;
-+                interrupts = <25 8>; /* IRQ_TYPE_LEVEL_LOW */
-+                clocks = <&can0_osc>;
-+            };
-+        };
-+    };
-+    __overrides__ {
-+        oscillator = <&can0_osc>,"clock-frequency:0";
-+        spimaxfrequency = <&can0>,"spi-max-frequency:0";
-+        interrupt = <&can0_pins>,"brcm,pins:0",<&can0>,"interrupts:0";
-+    };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts
-@@ -0,0 +1,73 @@
-+/*
-+ * Device tree overlay for mcp251x/can1 on spi0.1 edited by petit_miner
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+    compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
-+    /* disable spi-dev for spi0.1 */
-+    fragment@0 {
-+        target = <&spi0>;
-+        __overlay__ {
-+            status = "okay";
-+        };
-+    };
-+
-+    fragment@1 {
-+	target = <&spidev1>;
-+	__overlay__ {
-+	    status = "disabled";
-+	};
-+    };
-+
-+    /* the interrupt pin of the can-controller */
-+    fragment@2 {
-+        target = <&gpio>;
-+        __overlay__ {
-+            can1_pins: can1_pins {
-+                brcm,pins = <25>;
-+                brcm,function = <0>; /* input */
-+            };
-+        };
-+    };
-+
-+    /* the clock/oscillator of the can-controller */
-+    fragment@3 {
-+        target-path = "/clocks";
-+        __overlay__ {
-+            /* external oscillator of mcp2515 on spi0.1 */
-+            can1_osc: can1_osc {
-+                compatible = "fixed-clock";
-+                #clock-cells = <0>;
-+                clock-frequency  = <16000000>;
-+            };
-+        };
-+    };
-+
-+    /* the spi config of the can-controller itself binding everything together */
-+    fragment@4 {
-+        target = <&spi0>;
-+        __overlay__ {
-+            /* needed to avoid dtc warning */
-+            #address-cells = <1>;
-+            #size-cells = <0>;
-+            can1: mcp2515@1 {
-+                reg = <1>;
-+                compatible = "microchip,mcp2515";
-+                pinctrl-names = "default";
-+                pinctrl-0 = <&can1_pins>;
-+                spi-max-frequency = <10000000>;
-+                interrupt-parent = <&gpio>;
-+                interrupts = <25 8>; /* IRQ_TYPE_LEVEL_LOW */
-+                clocks = <&can1_osc>;
-+            };
-+        };
-+    };
-+    __overrides__ {
-+        oscillator = <&can1_osc>,"clock-frequency:0";
-+        spimaxfrequency = <&can1>,"spi-max-frequency:0";
-+        interrupt = <&can1_pins>,"brcm,pins:0",<&can1>,"interrupts:0";
-+    };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mcp3008-overlay.dts
-@@ -0,0 +1,205 @@
-+/*
-+ * Device tree overlay for Microchip mcp3008 10-Bit A/D Converters
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spidev0>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev1>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "spi1/spidev@0";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target-path = "spi1/spidev@1";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@4 {
-+		target-path = "spi1/spidev@2";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@5 {
-+		target-path = "spi2/spidev@0";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@6 {
-+		target-path = "spi2/spidev@1";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@7 {
-+		target-path = "spi2/spidev@2";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@8 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3008_00: mcp3008@0 {
-+				compatible = "mcp3008";
-+				reg = <0>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@9 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3008_01: mcp3008@1 {
-+				compatible = "mcp3008";
-+				reg = <1>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@10 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3008_10: mcp3008@0 {
-+				compatible = "mcp3008";
-+				reg = <0>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@11 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3008_11: mcp3008@1 {
-+				compatible = "mcp3008";
-+				reg = <1>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@12 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3008_12: mcp3008@2 {
-+				compatible = "mcp3008";
-+				reg = <2>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@13 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3008_20: mcp3008@0 {
-+				compatible = "mcp3008";
-+				reg = <0>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@14 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3008_21: mcp3008@1 {
-+				compatible = "mcp3008";
-+				reg = <1>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@15 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3008_22: mcp3008@2 {
-+				compatible = "mcp3008";
-+				reg = <2>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		spi0-0-present = <0>, "+0+8";
-+		spi0-1-present = <0>, "+1+9";
-+		spi1-0-present = <0>, "+2+10";
-+		spi1-1-present = <0>, "+3+11";
-+		spi1-2-present = <0>, "+4+12";
-+		spi2-0-present = <0>, "+5+13";
-+		spi2-1-present = <0>, "+6+14";
-+		spi2-2-present = <0>, "+7+15";
-+		spi0-0-speed = <&mcp3008_00>, "spi-max-frequency:0";
-+		spi0-1-speed = <&mcp3008_01>, "spi-max-frequency:0";
-+		spi1-0-speed = <&mcp3008_10>, "spi-max-frequency:0";
-+		spi1-1-speed = <&mcp3008_11>, "spi-max-frequency:0";
-+		spi1-2-speed = <&mcp3008_12>, "spi-max-frequency:0";
-+		spi2-0-speed = <&mcp3008_20>, "spi-max-frequency:0";
-+		spi2-1-speed = <&mcp3008_21>, "spi-max-frequency:0";
-+		spi2-2-speed = <&mcp3008_22>, "spi-max-frequency:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/midi-uart0-overlay.dts
-@@ -0,0 +1,36 @@
-+/dts-v1/;
-+/plugin/;
-+
-+#include <dt-bindings/clock/bcm2835.h>
-+
-+/*
-+ * Fake a higher clock rate to get a larger divisor, and thereby a lower
-+ * baudrate. The real clock is 48MHz, which we scale so that requesting
-+ * 38.4kHz results in an actual 31.25kHz.
-+ *
-+ *   48000000*38400/31250 = 58982400
-+ */
-+
-+/{
-+	compatible = "brcm,bcm2835";
-+
-+	fragment@0 {
-+		target-path = "/clocks";
-+		__overlay__ {
-+			midi_clk: midi_clk {
-+				compatible = "fixed-clock";
-+				#clock-cells = <0>;
-+				clock-output-names = "uart0_pclk";
-+				clock-frequency = <58982400>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&uart0>;
-+		__overlay__ {
-+			clocks = <&midi_clk>,
-+			         <&clocks BCM2835_CLOCK_VPU>;
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts
-@@ -0,0 +1,43 @@
-+/dts-v1/;
-+/plugin/;
-+
-+#include <dt-bindings/clock/bcm2835-aux.h>
-+
-+/*
-+ * Fake a higher clock rate to get a larger divisor, and thereby a lower
-+ * baudrate. The real clock is 48MHz, which we scale so that requesting
-+ * 38.4kHz results in an actual 31.25kHz.
-+ *
-+ *   48000000*38400/31250 = 58982400
-+ */
-+
-+/{
-+	compatible = "brcm,bcm2835";
-+
-+	fragment@0 {
-+		target-path = "/clocks";
-+		__overlay__ {
-+			midi_clk: clock@5 {
-+				compatible = "fixed-factor-clock";
-+				#clock-cells = <0>;
-+				clocks = <&aux BCM2835_AUX_CLOCK_UART>;
-+				clock-mult = <38400>;
-+				clock-div  = <31250>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&uart1>;
-+		__overlay__ {
-+			clocks = <&midi_clk>;
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&aux>;
-+		__overlay__ {
-+			clock-output-names = "aux_uart", "aux_spi1", "aux_spi2";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts
-@@ -0,0 +1,39 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&mmc>;
-+		frag0: __overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&mmc_pins>;
-+			bus-width = <4>;
-+			brcm,overclock-50 = <0>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			mmc_pins: mmc_pins {
-+				brcm,pins = <48 49 50 51 52 53>;
-+				brcm,function = <7>; /* alt3 */
-+				brcm,pull = <0 2 2 2 2 2>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sdhost>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	__overrides__ {
-+		overclock_50     = <&frag0>,"brcm,overclock-50:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mpu6050-overlay.dts
-@@ -0,0 +1,28 @@
-+// Definitions for MPU6050
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+        compatible = "brcm,bcm2708";
-+
-+        fragment@0 {
-+                target = <&i2c1>;
-+                __overlay__ {
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+                        status = "okay";
-+                        clock-frequency = <400000>;
-+
-+                        mpu6050: mpu6050@68 {
-+                                compatible = "invensense,mpu6050";
-+                                reg = <0x68>;
-+                                interrupt-parent = <&gpio>;
-+                                interrupts = <4 1>;
-+                        };
-+                };
-+        };
-+
-+        __overrides__ {
-+                interrupt = <&mpu6050>,"interrupts:0";
-+        };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mz61581-overlay.dts
-@@ -0,0 +1,117 @@
-+/*
-+ * Device Tree overlay for MZ61581-PI-EXT 2014.12.28 by Tontec
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			mz61581_pins: mz61581_pins {
-+				brcm,pins = <4 15 18 25>;
-+				brcm,function = <0 1 1 1>; /* in out out out */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mz61581: mz61581@0{
-+				compatible = "samsung,s6d02a1";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&mz61581_pins>;
-+
-+				spi-max-frequency = <128000000>;
-+				spi-cpol;
-+				spi-cpha;
-+
-+				width = <320>;
-+				height = <480>;
-+				rotate = <270>;
-+				bgr;
-+				fps = <30>;
-+				buswidth = <8>;
-+				txbuflen = <32768>;
-+
-+				reset-gpios = <&gpio 15 0>;
-+				dc-gpios = <&gpio 25 0>;
-+				led-gpios = <&gpio 18 0>;
-+
-+				init = <0x10000b0 00
-+					0x1000011
-+					0x20000ff
-+					0x10000b3 0x02 0x00 0x00 0x00
-+					0x10000c0 0x13 0x3b 0x00 0x02 0x00 0x01 0x00 0x43
-+					0x10000c1 0x08 0x16 0x08 0x08
-+					0x10000c4 0x11 0x07 0x03 0x03
-+					0x10000c6 0x00
-+					0x10000c8 0x03 0x03 0x13 0x5c 0x03 0x07 0x14 0x08 0x00 0x21 0x08 0x14 0x07 0x53 0x0c 0x13 0x03 0x03 0x21 0x00
-+					0x1000035 0x00
-+					0x1000036 0xa0
-+					0x100003a 0x55
-+					0x1000044 0x00 0x01
-+					0x10000d0 0x07 0x07 0x1d 0x03
-+					0x10000d1 0x03 0x30 0x10
-+					0x10000d2 0x03 0x14 0x04
-+					0x1000029
-+					0x100002c>;
-+
-+				/* This is a workaround to make sure the init sequence slows down and doesn't fail */
-+				debug = <3>;
-+			};
-+
-+			mz61581_ts: mz61581_ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <4 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 4 0>;
-+
-+				ti,x-plate-ohms = /bits/ 16 <60>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		speed =   <&mz61581>, "spi-max-frequency:0";
-+		rotate =  <&mz61581>, "rotate:0";
-+		fps =     <&mz61581>, "fps:0";
-+		txbuflen = <&mz61581>, "txbuflen:0";
-+		debug =   <&mz61581>, "debug:0";
-+		xohms =   <&mz61581_ts>,"ti,x-plate-ohms;0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/papirus-overlay.dts
-@@ -0,0 +1,89 @@
-+/* PaPiRus ePaper Screen by Pi Supply */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			display_temp: lm75@48 {
-+				compatible = "lm75b";
-+				reg = <0x48>;
-+				status = "okay";
-+				#thermal-sensor-cells = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/";
-+		__overlay__ {
-+			thermal-zones {
-+				display {
-+					polling-delay-passive = <0>;
-+					polling-delay = <0>;
-+					thermal-sensors = <&display_temp>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+
-+			spidev@0{
-+				status = "disabled";
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			repaper_pins: repaper_pins {
-+				brcm,pins = <14 15 23 24 25>;
-+				brcm,function = <1 1 1 1 0>; /* out out out out in */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			repaper: repaper@0{
-+				compatible = "not_set";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&repaper_pins>;
-+
-+				spi-max-frequency = <8000000>;
-+
-+				panel-on-gpios = <&gpio 23 0>;
-+				border-gpios = <&gpio 14 0>;
-+				discharge-gpios = <&gpio 15 0>;
-+				reset-gpios = <&gpio 24 0>;
-+				busy-gpios = <&gpio 25 0>;
-+
-+				repaper-thermal-zone = "display";
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		panel = <&repaper>, "compatible";
-+		speed = <&repaper>, "spi-max-frequency:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pi3-act-led-overlay.dts
-@@ -0,0 +1,27 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/* Pi3 uses a GPIO expander to drive the LEDs which can only be accessed
-+   from the VPU. There is a special driver for this with a separate DT node,
-+   which has the unfortunate consequence of breaking the act_led_gpio and
-+   act_led_activelow dtparams.
-+
-+   This overlay changes the GPIO controller back to the standard one and
-+   restores the dtparams.
-+*/
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&act_led>;
-+		frag0: __overlay__ {
-+			gpios = <&gpio 0 0>;
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpio = <&frag0>,"gpios:4";
-+		activelow = <&frag0>,"gpios:8";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pi3-disable-bt-overlay.dts
-@@ -0,0 +1,46 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/* Disable Bluetooth and restore UART0/ttyAMA0 over GPIOs 14 & 15.
-+   To disable the systemd service that initialises the modem so it doesn't use
-+   the UART:
-+
-+       sudo systemctl disable hciuart
-+*/
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&uart1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&uart0>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&uart0_pins>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&uart0_pins>;
-+		__overlay__ {
-+			brcm,pins;
-+			brcm,function;
-+			brcm,pull;
-+		};
-+	};
-+
-+	fragment@3 {
-+		target-path = "/aliases";
-+		__overlay__ {
-+			serial0 = "/soc/serial@7e201000";
-+			serial1 = "/soc/serial@7e215040";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pi3-disable-wifi-overlay.dts
-@@ -0,0 +1,13 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&mmc>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pi3-miniuart-bt-overlay.dts
-@@ -0,0 +1,74 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/* Switch Pi3 Bluetooth function to use the mini-UART (ttyS0) and restore
-+   UART0/ttyAMA0 over GPIOs 14 & 15. Note that this may reduce the maximum
-+   usable baudrate.
-+
-+   It is also necessary to edit /lib/systemd/system/hciuart.service and
-+   replace ttyAMA0 with ttyS0, unless you have a system with udev rules
-+   that create /dev/serial0 and /dev/serial1, in which case use /dev/serial1
-+   instead because it will always be correct.
-+
-+   If cmdline.txt uses the alias serial0 to refer to the user-accessable port
-+   then the firmware will replace with the appropriate port whether or not
-+   this overlay is used.
-+*/
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&uart0>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&uart0_pins>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&uart1>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&uart1_pins &bt_pins &fake_bt_cts>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&uart0_pins>;
-+		__overlay__ {
-+			brcm,pins;
-+			brcm,function;
-+			brcm,pull;
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&uart1_pins>;
-+		__overlay__ {
-+			brcm,pins = <32 33>;
-+			brcm,function = <2>; /* alt5=UART1 */
-+			brcm,pull = <0 2>;
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			fake_bt_cts: fake_bt_cts {
-+				brcm,pins = <31>;
-+				brcm,function = <1>; /* output */
-+			};
-+		};
-+	};
-+
-+	fragment@5 {
-+		target-path = "/aliases";
-+		__overlay__ {
-+			serial0 = "/soc/serial@7e201000";
-+			serial1 = "/soc/serial@7e215040";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/piscreen-overlay.dts
-@@ -0,0 +1,102 @@
-+/*
-+ * Device Tree overlay for PiScreen 3.5" display shield by Ozzmaker
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			piscreen_pins: piscreen_pins {
-+				brcm,pins = <17 25 24 22>;
-+				brcm,function = <0 1 1 1>; /* in out out out */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			piscreen: piscreen@0{
-+				compatible = "ilitek,ili9486";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&piscreen_pins>;
-+
-+				spi-max-frequency = <24000000>;
-+				rotate = <270>;
-+				bgr;
-+				fps = <30>;
-+				buswidth = <8>;
-+				regwidth = <16>;
-+				reset-gpios = <&gpio 25 0>;
-+				dc-gpios = <&gpio 24 0>;
-+				led-gpios = <&gpio 22 1>;
-+				debug = <0>;
-+
-+				init = <0x10000b0 0x00
-+				        0x1000011
-+					0x20000ff
-+					0x100003a 0x55
-+					0x1000036 0x28
-+					0x10000c2 0x44
-+					0x10000c5 0x00 0x00 0x00 0x00
-+					0x10000e0 0x0f 0x1f 0x1c 0x0c 0x0f 0x08 0x48 0x98 0x37 0x0a 0x13 0x04 0x11 0x0d 0x00
-+					0x10000e1 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00
-+					0x10000e2 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00
-+					0x1000011
-+					0x1000029>;
-+			};
-+
-+			piscreen_ts: piscreen-ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <17 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 17 0>;
-+				ti,swap-xy;
-+				ti,x-plate-ohms = /bits/ 16 <100>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		speed =		<&piscreen>,"spi-max-frequency:0";
-+		rotate =	<&piscreen>,"rotate:0";
-+		fps =		<&piscreen>,"fps:0";
-+		debug =		<&piscreen>,"debug:0";
-+		xohms =		<&piscreen_ts>,"ti,x-plate-ohms;0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts
-@@ -0,0 +1,106 @@
-+ /*
-+ * Device Tree overlay for PiScreen2 3.5" TFT with resistive touch  by Ozzmaker.com
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			piscreen2_pins: piscreen2_pins {
-+				brcm,pins = <17 25 24 22>;
-+				brcm,function = <0 1 1 1>; /* in out out out */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			piscreen2: piscreen2@0{
-+				compatible = "ilitek,ili9486";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&piscreen2_pins>;
-+				bgr;
-+				spi-max-frequency = <64000000>;
-+				rotate = <90>;
-+				fps = <30>;
-+				buswidth = <8>;
-+				regwidth = <16>;
-+				txbuflen = <32768>;
-+				reset-gpios = <&gpio 25 0>;
-+				dc-gpios = <&gpio 24 0>;
-+				led-gpios = <&gpio 22 1>;
-+				debug = <0>;
-+
-+                                init = <0x10000b0 0x00
-+                                        0x1000011
-+                                        0x20000ff
-+                                        0x100003a 0x55
-+                                        0x1000036 0x28
-+                                        0x10000c0 0x11 0x09
-+                                        0x10000c1 0x41
-+                                        0x10000c5 0x00 0x00 0x00 0x00
-+                                        0x10000b6 0x00 0x02
-+                                        0x10000f7 0xa9 0x51 0x2c 0x2
-+                                        0x10000be 0x00 0x04
-+                                        0x10000e9 0x00
-+                                        0x1000011
-+                                        0x1000029>;
-+
-+			};
-+
-+			piscreen2_ts: piscreen2-ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <17 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 17 0>;
-+				ti,swap-xy;
-+				ti,x-plate-ohms = /bits/ 16 <100>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		speed =		<&piscreen2>,"spi-max-frequency:0";
-+		rotate =	<&piscreen2>,"rotate:0";
-+		fps =		<&piscreen2>,"fps:0";
-+		debug =		<&piscreen2>,"debug:0";
-+		xohms =		<&piscreen2_ts>,"ti,x-plate-ohms;0";
-+	};
-+};
-+
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pisound-overlay.dts
-@@ -0,0 +1,120 @@
-+/*
-+ * pisound Linux kernel module.
-+ * Copyright (C) 2016  Vilniaus Blokas UAB, http://blokas.io/pisound
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; version 2 of the
-+ * License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			pisound_spi: pisound_spi@0{
-+				compatible = "blokaslabs,pisound-spi";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&spi0_pins>;
-+				spi-max-frequency = <1000000>;
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target-path = "/";
-+		__overlay__ {
-+			pcm5102a-codec {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5102a";
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@5 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "blokaslabs,pisound";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+
-+			pinctrl-0 = <&pisound_button_pins>;
-+
-+			osr-gpios =
-+				<&gpio 13 GPIO_ACTIVE_HIGH>,
-+				<&gpio 26 GPIO_ACTIVE_HIGH>,
-+				<&gpio 16 GPIO_ACTIVE_HIGH>;
-+
-+			reset-gpios =
-+				<&gpio 12 GPIO_ACTIVE_HIGH>,
-+				<&gpio 24 GPIO_ACTIVE_HIGH>;
-+
-+			data_available-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
-+
-+			button-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+
-+	fragment@6 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&pisound_button_pins>;
-+
-+			pisound_button_pins: pisound_button_pins {
-+				brcm,pins = <17>;
-+				brcm,function = <0>; // Input
-+				brcm,pull = <2>; // Pull-Up
-+			};
-+		};
-+	};
-+
-+	fragment@7 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pitft22-overlay.dts
-@@ -0,0 +1,69 @@
-+/*
-+ * Device Tree overlay for pitft by Adafruit
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+        compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+        fragment@0 {
-+                target = <&spi0>;
-+                __overlay__ {
-+                        status = "okay";
-+
-+                        spidev@0{
-+                                status = "disabled";
-+                        };
-+
-+                        spidev@1{
-+                                status = "disabled";
-+                        };
-+                };
-+        };
-+
-+        fragment@1 {
-+                target = <&gpio>;
-+                __overlay__ {
-+                        pitft_pins: pitft_pins {
-+                                brcm,pins = <25>;
-+                                brcm,function = <1>; /* out */
-+                                brcm,pull = <0>; /* none */
-+                        };
-+                };
-+        };
-+
-+        fragment@2 {
-+                target = <&spi0>;
-+                __overlay__ {
-+                        /* needed to avoid dtc warning */
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+
-+                        pitft: pitft@0{
-+                                compatible = "ilitek,ili9340";
-+                                reg = <0>;
-+                                pinctrl-names = "default";
-+                                pinctrl-0 = <&pitft_pins>;
-+
-+                                spi-max-frequency = <32000000>;
-+                                rotate = <90>;
-+                                fps = <25>;
-+                                bgr;
-+                                buswidth = <8>;
-+                                dc-gpios = <&gpio 25 0>;
-+                                debug = <0>;
-+                        };
-+
-+                };
-+        };
-+
-+        __overrides__ {
-+                speed =   <&pitft>,"spi-max-frequency:0";
-+                rotate =  <&pitft>,"rotate:0";
-+                fps =     <&pitft>,"fps:0";
-+                debug =   <&pitft>,"debug:0";
-+        };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts
-@@ -0,0 +1,91 @@
-+/*
-+ * Device Tree overlay for Adafruit PiTFT 2.8" capacitive touch screen
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+        compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+        fragment@0 {
-+                target = <&spi0>;
-+                __overlay__ {
-+                        status = "okay";
-+                };
-+        };
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+        fragment@2 {
-+                target = <&gpio>;
-+                __overlay__ {
-+                        pitft_pins: pitft_pins {
-+                                brcm,pins = <24 25>;
-+                                brcm,function = <0 1>; /* in out */
-+                                brcm,pull = <2 0>; /* pullup none */
-+                        };
-+                };
-+        };
-+
-+        fragment@3 {
-+                target = <&spi0>;
-+                __overlay__ {
-+                        /* needed to avoid dtc warning */
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+
-+                        pitft: pitft@0{
-+                                compatible = "ilitek,ili9340";
-+                                reg = <0>;
-+                                pinctrl-names = "default";
-+                                pinctrl-0 = <&pitft_pins>;
-+
-+                                spi-max-frequency = <32000000>;
-+                                rotate = <90>;
-+                                fps = <25>;
-+                                bgr;
-+                                buswidth = <8>;
-+                                dc-gpios = <&gpio 25 0>;
-+                                debug = <0>;
-+                        };
-+                };
-+        };
-+
-+        fragment@4 {
-+                target = <&i2c1>;
-+                __overlay__ {
-+                        /* needed to avoid dtc warning */
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+
-+                        ft6236: ft6236@38 {
-+                                compatible = "focaltech,ft6236";
-+                                reg = <0x38>;
-+
-+                                interrupt-parent = <&gpio>;
-+                                interrupts = <24 2>;
-+                                touchscreen-size-x = <240>;
-+                                touchscreen-size-y = <320>;
-+                        };
-+                };
-+        };
-+
-+        __overrides__ {
-+                speed =   <&pitft>,"spi-max-frequency:0";
-+                rotate =  <&pitft>,"rotate:0";
-+                fps =     <&pitft>,"fps:0";
-+                debug =   <&pitft>,"debug:0";
-+                touch-sizex = <&ft6236>,"touchscreen-size-x?";
-+                touch-sizey = <&ft6236>,"touchscreen-size-y?";
-+                touch-invx  = <&ft6236>,"touchscreen-inverted-x?";
-+                touch-invy  = <&ft6236>,"touchscreen-inverted-y?";
-+                touch-swapxy = <&ft6236>,"touchscreen-swapped-x-y?";
-+        };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts
-@@ -0,0 +1,121 @@
-+/*
-+ * Device Tree overlay for Adafruit PiTFT 2.8" resistive touch screen
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			pitft_pins: pitft_pins {
-+				brcm,pins = <24 25>;
-+				brcm,function = <0 1>; /* in out */
-+				brcm,pull = <2 0>; /* pullup none */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			pitft: pitft@0{
-+				compatible = "ilitek,ili9340";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&pitft_pins>;
-+
-+				spi-max-frequency = <32000000>;
-+				rotate = <90>;
-+				fps = <25>;
-+				bgr;
-+				buswidth = <8>;
-+				dc-gpios = <&gpio 25 0>;
-+				debug = <0>;
-+			};
-+
-+			pitft_ts@1 {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				compatible = "st,stmpe610";
-+				reg = <1>;
-+
-+				spi-max-frequency = <500000>;
-+				irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */
-+				interrupts = <24 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				interrupt-controller;
-+
-+				stmpe_touchscreen {
-+					compatible = "st,stmpe-ts";
-+					st,sample-time = <4>;
-+					st,mod-12b = <1>;
-+					st,ref-sel = <0>;
-+					st,adc-freq = <2>;
-+					st,ave-ctrl = <3>;
-+					st,touch-det-delay = <4>;
-+					st,settling = <2>;
-+					st,fraction-z = <7>;
-+					st,i-drive = <0>;
-+				};
-+
-+				stmpe_gpio: stmpe_gpio {
-+					#gpio-cells = <2>;
-+					compatible = "st,stmpe-gpio";
-+					/*
-+					 * only GPIO2 is wired/available
-+					 * and it is wired to the backlight
-+					 */
-+					st,norequest-mask = <0x7b>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@5 {
-+		target-path = "/soc";
-+		__overlay__ {
-+			backlight {
-+				compatible = "gpio-backlight";
-+				gpios = <&stmpe_gpio 2 0>;
-+				default-on;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		speed =   <&pitft>,"spi-max-frequency:0";
-+		rotate =  <&pitft>,"rotate:0";
-+		fps =     <&pitft>,"fps:0";
-+		debug =   <&pitft>,"debug:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts
-@@ -0,0 +1,121 @@
-+/*
-+ * Device Tree overlay for Adafruit PiTFT 3.5" resistive touch screen
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			pitft_pins: pitft_pins {
-+				brcm,pins = <24 25>;
-+				brcm,function = <0 1>; /* in out */
-+				brcm,pull = <2 0>; /* pullup none */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			pitft: pitft@0{
-+				compatible = "himax,hx8357d";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&pitft_pins>;
-+
-+				spi-max-frequency = <32000000>;
-+				rotate = <90>;
-+				fps = <25>;
-+				bgr;
-+				buswidth = <8>;
-+				dc-gpios = <&gpio 25 0>;
-+				debug = <0>;
-+			};
-+
-+			pitft_ts@1 {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				compatible = "st,stmpe610";
-+				reg = <1>;
-+
-+				spi-max-frequency = <500000>;
-+				irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */
-+				interrupts = <24 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				interrupt-controller;
-+
-+				stmpe_touchscreen {
-+					compatible = "st,stmpe-ts";
-+					st,sample-time = <4>;
-+					st,mod-12b = <1>;
-+					st,ref-sel = <0>;
-+					st,adc-freq = <2>;
-+					st,ave-ctrl = <3>;
-+					st,touch-det-delay = <4>;
-+					st,settling = <2>;
-+					st,fraction-z = <7>;
-+					st,i-drive = <0>;
-+				};
-+
-+				stmpe_gpio: stmpe_gpio {
-+					#gpio-cells = <2>;
-+					compatible = "st,stmpe-gpio";
-+					/*
-+					 * only GPIO2 is wired/available
-+					 * and it is wired to the backlight
-+					 */
-+					st,norequest-mask = <0x7b>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@5 {
-+		target-path = "/soc";
-+		__overlay__ {
-+			backlight {
-+				compatible = "gpio-backlight";
-+				gpios = <&stmpe_gpio 2 0>;
-+				default-on;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		speed =   <&pitft>,"spi-max-frequency:0";
-+		rotate =  <&pitft>,"rotate:0";
-+		fps =     <&pitft>,"fps:0";
-+		debug =   <&pitft>,"debug:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts
-@@ -0,0 +1,35 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			pps: pps {
-+				compatible = "pps-gpio";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&pps_pins>;
-+				gpios = <&gpio 18 0>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			pps_pins: pps_pins {
-+				brcm,pins =     <18>;
-+				brcm,function = <0>;    // in
-+				brcm,pull =     <0>;    // off
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpiopin = <&pps>,"gpios:4",
-+			  <&pps_pins>,"brcm,pins:0";
-+		assert_falling_edge = <&pps>,"assert-falling-edge?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts
-@@ -0,0 +1,47 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/*
-+This is the 2-channel overlay - only use it if you need both channels.
-+
-+Legal pin,function combinations for each channel:
-+  PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0)            52,5(Alt1)
-+  PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1)
-+
-+N.B.:
-+  1) Pin 18 is the only one available on all platforms, and
-+     it is the one used by the I2S audio interface.
-+     Pins 12 and 13 might be better choices on an A+, B+ or Pi2.
-+  2) The onboard analogue audio output uses both PWM channels.
-+  3) So be careful mixing audio and PWM.
-+*/
-+
-+/ {
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			pwm_pins: pwm_pins {
-+				brcm,pins = <18 19>;
-+				brcm,function = <2 2>; /* Alt5 */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&pwm>;
-+		frag1: __overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&pwm_pins>;
-+			assigned-clock-rates = <100000000>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		pin   = <&pwm_pins>,"brcm,pins:0";
-+		pin2  = <&pwm_pins>,"brcm,pins:4";
-+		func  = <&pwm_pins>,"brcm,function:0";
-+		func2 = <&pwm_pins>,"brcm,function:4";
-+		clock = <&frag1>,"assigned-clock-rates:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts
-@@ -0,0 +1,40 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			pwm0_pins: pwm0_pins {
-+				brcm,pins = <18>;
-+				brcm,function = <2>; /* Alt5 */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&pwm>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&pwm0_pins>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "/";
-+		__overlay__ {
-+			pwm-ir-transmitter {
-+				compatible = "pwm-ir-tx";
-+				pwms = <&pwm 0 100>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpio_pin = <&pwm0_pins>, "brcm,pins:0";
-+		func = <&pwm0_pins>,"brcm,function:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pwm-overlay.dts
-@@ -0,0 +1,43 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/*
-+Legal pin,function combinations for each channel:
-+  PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0)            52,5(Alt1)
-+  PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1)
-+
-+N.B.:
-+  1) Pin 18 is the only one available on all platforms, and
-+     it is the one used by the I2S audio interface.
-+     Pins 12 and 13 might be better choices on an A+, B+ or Pi2.
-+  2) The onboard analogue audio output uses both PWM channels.
-+  3) So be careful mixing audio and PWM.
-+*/
-+
-+/ {
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			pwm_pins: pwm_pins {
-+				brcm,pins = <18>;
-+				brcm,function = <2>; /* Alt5 */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&pwm>;
-+		frag1: __overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&pwm_pins>;
-+			assigned-clock-rates = <100000000>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		pin   = <&pwm_pins>,"brcm,pins:0";
-+		func  = <&pwm_pins>,"brcm,function:0";
-+		clock = <&frag1>,"assigned-clock-rates:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/qca7000-overlay.dts
-@@ -0,0 +1,52 @@
-+// Overlay for the Qualcomm Atheros QCA7000 on I2SE's PLC Stamp micro EVK
-+// Visit: https://www.i2se.com/product/plc-stamp-micro-evk for details
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "okay";
-+
-+			spidev@0 {
-+				status = "disabled";
-+			};
-+
-+			eth1: qca7000@0 {
-+				compatible = "qca,qca7000";
-+				reg = <0>; /* CE0 */
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&eth1_pins>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <23 0x1>; /* rising edge */
-+				spi-max-frequency = <12000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			eth1_pins: eth1_pins {
-+				brcm,pins = <23>;
-+				brcm,function = <0>; /* in */
-+				brcm,pull = <0>; /* none */
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		int_pin = <&eth1>, "interrupts:0",
-+		          <&eth1_pins>, "brcm,pins:0";
-+		speed   = <&eth1>, "spi-max-frequency:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/raspidac3-overlay.dts
-@@ -0,0 +1,49 @@
-+// Definitions for RaspiDACv3
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			pcm5122@4c {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm5122";
-+				reg = <0x4c>;
-+				AVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				CPVDD-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+
-+			tpa6130a2: tpa6130a2@60 {
-+				compatible = "ti,tpa6130a2";
-+				reg = <0x60>;
-+				Vdd-supply = <&vdd_3v3_reg>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "jg,raspidacv3";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts
-@@ -0,0 +1,43 @@
-+// Device tree overlay for GPIO connected rotary encoder.
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			rotary0_pins: rotary0_pins {
-+				brcm,pins = <4 17>; /* gpio 4 17 */
-+				brcm,function = <0 0>; /* input */
-+				brcm,pull = <2 2>; /* pull-up */
-+			};
-+
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/";
-+		__overlay__ {
-+			rotary0: rotary@0 {
-+					compatible = "rotary-encoder";
-+					status = "okay";
-+					pinctrl-names = "default";
-+					pinctrl-0 = <&rotary0_pins>;
-+					gpios = <&gpio 4 0>, <&gpio 17 0>;
-+					linux,axis = <0>; /* REL_X */
-+					rotary-encoder,encoding = "gray";
-+					rotary-encoder,relative-axis;
-+			};
-+		};
-+
-+	};  
-+
-+	__overrides__ {
-+		rotary0_pin_a = <&rotary0>,"gpios:4",
-+				<&rotary0_pins>,"brcm,pins:0";
-+		rotary0_pin_b = <&rotary0>,"gpios:16",
-+				<&rotary0_pins>,"brcm,pins:4";
-+	};  
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts
-@@ -0,0 +1,21 @@
-+/*
-+ * Devicetree overlay for mailbox-driven Raspberry Pi DSI Display
-+ * backlight controller
-+ */
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			rpi_backlight: rpi_backlight {
-+				compatible = "raspberrypi,rpi-backlight";
-+				firmware = <&firmware>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts
-@@ -0,0 +1,146 @@
-+// Definitions for the Cirrus Logic Audio Card
-+/dts-v1/;
-+/plugin/;
-+#include <dt-bindings/pinctrl/bcm2835.h>
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/mfd/arizona.h>
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			wlf_pins: wlf_pins {
-+				brcm,pins = <17 22 27 8>;
-+				brcm,function = <
-+					BCM2835_FSEL_GPIO_OUT
-+					BCM2835_FSEL_GPIO_OUT
-+					BCM2835_FSEL_GPIO_IN
-+					BCM2835_FSEL_GPIO_OUT
-+				>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "/";
-+		__overlay__ {
-+			rpi_cirrus_reg_1v8: rpi_cirrus_reg_1v8 {
-+				compatible = "regulator-fixed";
-+				regulator-name = "RPi-Cirrus 1v8";
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+				regulator-always-on;
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			spidev@0{
-+				status = "disabled";
-+			};
-+
-+			spidev@1{
-+				status = "disabled";
-+			};
-+
-+			wm5102@1{
-+				compatible = "wlf,wm5102";
-+				reg = <1>;
-+
-+				spi-max-frequency = <500000>;
-+
-+				interrupt-parent = <&gpio>;
-+				interrupts = <27 8>;
-+				interrupt-controller;
-+				#interrupt-cells = <2>;
-+
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+
-+				LDOVDD-supply = <&rpi_cirrus_reg_1v8>;
-+				AVDD-supply = <&rpi_cirrus_reg_1v8>;
-+				DBVDD1-supply = <&rpi_cirrus_reg_1v8>;
-+				DBVDD2-supply = <&vdd_3v3_reg>;
-+				DBVDD3-supply = <&vdd_3v3_reg>;
-+				CPVDD-supply = <&rpi_cirrus_reg_1v8>;
-+				SPKVDDL-supply = <&vdd_5v0_reg>;
-+				SPKVDDR-supply = <&vdd_5v0_reg>;
-+				DCVDD-supply = <&arizona_ldo1>;
-+
-+				wlf,reset = <&gpio 17 GPIO_ACTIVE_HIGH>;
-+				wlf,ldoena = <&gpio 22 GPIO_ACTIVE_HIGH>;
-+				wlf,gpio-defaults = <
-+					ARIZONA_GP_DEFAULT
-+					ARIZONA_GP_DEFAULT
-+					ARIZONA_GP_DEFAULT
-+					ARIZONA_GP_DEFAULT
-+					ARIZONA_GP_DEFAULT
-+				>;
-+				wlf,micd-configs = <0 1 0>;
-+				wlf,dmic-ref = <
-+					ARIZONA_DMIC_MICVDD
-+					ARIZONA_DMIC_MICBIAS2
-+					ARIZONA_DMIC_MICVDD
-+					ARIZONA_DMIC_MICVDD
-+				>;
-+				wlf,inmode = <
-+					ARIZONA_INMODE_DIFF
-+					ARIZONA_INMODE_DMIC
-+					ARIZONA_INMODE_SE
-+					ARIZONA_INMODE_DIFF
-+				>;
-+				status = "okay";
-+
-+				arizona_ldo1: ldo1 {
-+					regulator-name = "LDO1";
-+					// default constraints as in
-+					// arizona-ldo1.c
-+					regulator-min-microvolt = <1200000>;
-+					regulator-max-microvolt = <1800000>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			wm8804@3b {
-+				compatible = "wlf,wm8804";
-+				reg = <0x3b>;
-+				status = "okay";
-+				PVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+				wlf,reset-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
-+			};
-+		};
-+	};
-+
-+	fragment@5 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "wlf,rpi-cirrus";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts
-@@ -0,0 +1,34 @@
-+// Definitions for RPi DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/";
-+		__overlay__ {
-+			pcm1794a-codec {
-+				#sound-dai-cells = <0>;
-+				compatible = "ti,pcm1794a";
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "rpi,rpi-dac";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-display-overlay.dts
-@@ -0,0 +1,89 @@
-+/*
-+ * Device Tree overlay for rpi-display by Watterott
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			rpi_display_pins: rpi_display_pins {
-+				brcm,pins = <18 23 24 25>;
-+				brcm,function = <1 1 1 0>; /* out out out in */
-+				brcm,pull = <0 0 0 2>; /* - - - up */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			rpidisplay: rpi-display@0{
-+				compatible = "ilitek,ili9341";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&rpi_display_pins>;
-+
-+				spi-max-frequency = <32000000>;
-+				rotate = <270>;
-+				bgr;
-+				fps = <30>;
-+				buswidth = <8>;
-+				reset-gpios = <&gpio 23 0>;
-+				dc-gpios = <&gpio 24 0>;
-+				led-gpios = <&gpio 18 1>;
-+				debug = <0>;
-+			};
-+
-+			rpidisplay_ts: rpi-display-ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <25 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 25 0>;
-+				ti,x-plate-ohms = /bits/ 16 <60>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		speed =   <&rpidisplay>,"spi-max-frequency:0";
-+		rotate =  <&rpidisplay>,"rotate:0";
-+		fps =     <&rpidisplay>,"fps:0";
-+		debug =   <&rpidisplay>,"debug:0";
-+		xohms =   <&rpidisplay_ts>,"ti,x-plate-ohms;0";
-+		swapxy =  <&rpidisplay_ts>,"ti,swap-xy?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts
-@@ -0,0 +1,30 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			rpi_ft5406: rpi_ft5406 {
-+				compatible = "rpi,rpi-ft5406";
-+				firmware = <&firmware>;
-+				status = "okay";
-+				touchscreen-size-x = <800>;
-+				touchscreen-size-y = <600>;
-+				touchscreen-inverted-x = <0>;
-+				touchscreen-inverted-y = <0>;
-+				touchscreen-swapped-x-y = <0>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		touchscreen-size-x = <&rpi_ft5406>,"touchscreen-size-x:0";
-+		touchscreen-size-y = <&rpi_ft5406>,"touchscreen-size-y:0";
-+		touchscreen-inverted-x = <&rpi_ft5406>,"touchscreen-inverted-x:0";
-+		touchscreen-inverted-y = <&rpi_ft5406>,"touchscreen-inverted-y:0";
-+		touchscreen-swapped-x-y = <&rpi_ft5406>,"touchscreen-swapped-x-y:0";
-+        };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts
-@@ -0,0 +1,39 @@
-+// Definitions for Rpi-Proto
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			wm8731@1a {
-+				#sound-dai-cells = <0>;
-+				compatible = "wlf,wm8731";
-+				reg = <0x1a>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "rpi,rpi-proto";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts
-@@ -0,0 +1,47 @@
-+// rpi-sense HAT
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			rpi-sense@46 {
-+				compatible = "rpi,rpi-sense";
-+				reg = <0x46>;
-+				keys-int-gpios = <&gpio 23 1>;
-+				status = "okay";
-+			};
-+
-+			lsm9ds1-magn@1c {
-+				compatible = "st,lsm9ds1-magn";
-+				reg = <0x1c>;
-+				status = "okay";
-+			};
-+
-+			lsm9ds1-accel6a {
-+				compatible = "st,lsm9ds1-accel";
-+				reg = <0x6a>;
-+				status = "okay";
-+			};
-+
-+			lps25h-press@5c {
-+				compatible = "st,lps25h-press";
-+				reg = <0x5c>;
-+				status = "okay";
-+			};
-+
-+			hts221-humid@5f {
-+				compatible = "st,hts221-humid";
-+				reg = <0x5f>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts
-@@ -0,0 +1,31 @@
-+// rpi-tv HAT
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "okay";
-+
-+			spidev@0 {
-+				status = "disabled";
-+			};
-+
-+			cxd2880@0 {
-+				compatible = "sony,cxd2880";
-+				reg = <0>; /* CE0 */
-+				spi-max-frequency = <50000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts
-@@ -0,0 +1,49 @@
-+// Definitions for RRA DigiDAC1 Audio card
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			wm8804@3b {
-+				#sound-dai-cells = <0>;
-+				compatible = "wlf,wm8804";
-+				reg = <0x3b>;
-+				status = "okay";
-+				PVDD-supply = <&vdd_3v3_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+			};
-+
-+			wm8742: wm8741@1a {
-+				compatible = "wlf,wm8741";
-+				reg = <0x1a>;
-+				status = "okay";
-+				AVDD-supply = <&vdd_5v0_reg>;
-+				DVDD-supply = <&vdd_3v3_reg>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "rra,digidac1-soundcard";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts
-@@ -0,0 +1,37 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			sc16is750: sc16is750@48 {
-+				compatible = "nxp,sc16is750";
-+				reg = <0x48>; /* address */
-+				clocks = <&sc16is750_clk>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */
-+				#gpio-cells = <2>;
-+
-+				sc16is750_clk: sc16is750_clk {
-+					compatible = "fixed-clock";
-+					#clock-cells = <0>;
-+					clock-frequency = <14745600>;
-+				};
-+			};
-+		};
-+	};
-+
-+
-+	__overrides__ {
-+		int_pin = <&sc16is750>,"interrupts:0";
-+		addr = <&sc16is750>,"reg:0";
-+	};
-+
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts
-@@ -0,0 +1,61 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			spi1_pins: spi1_pins {
-+				brcm,pins = <19 20 21>;
-+				brcm,function = <3>; /* alt4 */
-+			};
-+
-+			spi1_cs_pins: spi1_cs_pins {
-+				brcm,pins = <18>;
-+				brcm,function = <1>; /* output */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi1>;
-+		frag1: __overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
-+			cs-gpios = <&gpio 18 1>;
-+			status = "okay";
-+
-+			sc16is752: sc16is752@0 {
-+				compatible = "nxp,sc16is752";
-+				reg = <0>; /* CE0 */
-+				clocks = <&sc16is752_clk>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */
-+				#gpio-controller;
-+				#gpio-cells = <2>;
-+				spi-max-frequency = <4000000>;
-+
-+				sc16is752_clk: sc16is752_clk {
-+					compatible = "fixed-clock";
-+					#clock-cells = <0>;
-+					clock-frequency = <14745600>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&aux>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+    __overrides__ {
-+      int_pin = <&sc16is752>,"interrupts:0";
-+    };
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts
-@@ -0,0 +1,31 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/* Provide backwards compatible aliases for the old sdhost dtparams. */
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&sdhost>;
-+		frag0: __overlay__ {
-+			brcm,overclock-50 = <0>;
-+			brcm,pio-limit = <1>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&mmc>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	__overrides__ {
-+		overclock_50     = <&frag0>,"brcm,overclock-50:0";
-+		force_pio        = <&frag0>,"brcm,force-pio?";
-+		pio_limit        = <&frag0>,"brcm,pio-limit:0";
-+		debug            = <&frag0>,"brcm,debug?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/sdio-1bit-overlay.dts
-@@ -0,0 +1,37 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/* Enable 1-bit SDIO from MMC interface via GPIOs 22-25. Includes sdhost overlay. */
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&mmc>;
-+		sdio_mmc: __overlay__ {
-+			compatible = "brcm,bcm2835-mmc";
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sdio_pins>;
-+			non-removable;
-+			bus-width = <1>;
-+			brcm,overclock-50 = <0>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			sdio_pins: sdio_pins {
-+				brcm,pins = <22 23 24 25>;
-+				brcm,function = <7>; /* ALT3 = SD1 */
-+				brcm,pull = <0 2 2 2>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		poll_once = <&sdio_mmc>,"non-removable?";
-+		sdio_overclock = <&sdio_mmc>,"brcm,overclock-50:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts
-@@ -0,0 +1,37 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/* Enable SDIO from MMC interface via GPIOs 22-27. Includes sdhost overlay. */
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&mmc>;
-+		sdio_mmc: __overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sdio_pins>;
-+			non-removable;
-+			bus-width = <4>;
-+			brcm,overclock-50 = <0>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			sdio_pins: sdio_pins {
-+				brcm,pins = <22 23 24 25 26 27>;
-+				brcm,function = <7>; /* ALT3 = SD1 */
-+				brcm,pull = <0 2 2 2 2 2>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		poll_once = <&sdio_mmc>,"non-removable?";
-+		bus_width = <&sdio_mmc>,"bus-width:0";
-+		sdio_overclock = <&sdio_mmc>,"brcm,overclock-50:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/sdtweak-overlay.dts
-@@ -0,0 +1,23 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/* Provide backwards compatible aliases for the old sdhost dtparams. */
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&sdhost>;
-+		frag0: __overlay__ {
-+			brcm,overclock-50 = <0>;
-+			brcm,pio-limit = <1>;
-+		};
-+	};
-+
-+	__overrides__ {
-+		overclock_50     = <&frag0>,"brcm,overclock-50:0";
-+		force_pio        = <&frag0>,"brcm,force-pio?";
-+		pio_limit        = <&frag0>,"brcm,pio-limit:0";
-+		debug            = <&frag0>,"brcm,debug?";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/smi-dev-overlay.dts
-@@ -0,0 +1,18 @@
-+// Description: Overlay to enable character device interface for SMI.
-+// Author:	Luke Wren <luke@raspberrypi.org>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	fragment@0 {
-+		target = <&soc>;
-+		__overlay__ {
-+			smi_dev {
-+				compatible = "brcm,bcm2835-smi-dev";
-+				smi_handle = <&smi>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/smi-nand-overlay.dts
-@@ -0,0 +1,69 @@
-+// Description: Overlay to enable NAND flash through
-+// the secondary memory interface
-+// Author:	Luke Wren
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&smi>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&smi_pins>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&soc>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			nand: flash@0 {
-+				compatible = "brcm,bcm2835-smi-nand";
-+				smi_handle = <&smi>;
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				status = "okay";
-+
-+				partition@0 {
-+					label = "stage2";
-+					// 128k
-+					reg = <0 0x20000>;
-+					read-only;
-+				};
-+				partition@1 {
-+					label = "firmware";
-+					// 16M
-+					reg = <0x20000 0x1000000>;
-+					read-only;
-+				};
-+				partition@2 {
-+					label = "root";
-+					// 2G (will need to use 64 bit for >=4G)
-+					reg = <0x1020000 0x80000000>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			smi_pins: smi_pins {
-+				brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
-+					12 13 14 15>;
-+				/* Alt 1: SMI */
-+				brcm,function = <5 5 5 5 5 5 5 5 5 5 5
-+					5 5 5 5 5>;
-+				/* /CS, /WE and /OE are pulled high, as they are
-+				   generally active low signals */
-+				brcm,pull = <2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0>;
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/smi-overlay.dts
-@@ -0,0 +1,37 @@
-+// Description:	Overlay to enable the secondary memory interface peripheral
-+// Author:	Luke Wren
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&smi>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&smi_pins>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			smi_pins: smi_pins {
-+				/* Don't configure the top two address bits, as
-+				   these are already used as ID_SD and ID_SC */
-+				brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15
-+					     16 17 18 19 20 21 22 23 24 25>;
-+				/* Alt 0: SMI */
-+				brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
-+						 5 5 5 5 5 5 5 5 5>;
-+				/* /CS, /WE and /OE are pulled high, as they are
-+				   generally active low signals */
-+				brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0
-+					     0 0 0 0 0 0 0>;
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts
-@@ -0,0 +1,31 @@
-+/*
-+ * Device tree overlay to move spi0 to gpio 35 to 39 on CM
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			cs-gpios = <&gpio 36 1>, <&gpio 35 1>;
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi0_cs_pins>;
-+		__overlay__ {
-+			brcm,pins = <36 35>;
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spi0_pins>;
-+		__overlay__ {
-+			brcm,pins = <37 38 39>;
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts
-@@ -0,0 +1,33 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&spidev0>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			rtc-pcf2123@0 {
-+				compatible = "nxp,rtc-pcf2123";
-+				spi-max-frequency = <5000000>;
-+				spi-cs-high = <1>;
-+				reg = <0>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		pcf2123 = <0>, "=0=1";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi0-cs-overlay.dts
-@@ -0,0 +1,29 @@
-+/dts-v1/;
-+/plugin/;
-+
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0_cs_pins>;
-+		frag0: __overlay__ {
-+			brcm,pins = <8 7>;
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi0>;
-+		frag1: __overlay__ {
-+			cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		cs0_pin  = <&frag0>,"brcm,pins:0",
-+			   <&frag1>,"cs-gpios:4";
-+		cs1_pin  = <&frag0>,"brcm,pins:4",
-+			   <&frag1>,"cs-gpios:16";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi0-hw-cs-overlay.dts
-@@ -0,0 +1,26 @@
-+/*
-+ * Device tree overlay to re-enable hardware CS for SPI0
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			cs-gpios = <0>, <0>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi0_cs_pins>;
-+		__overlay__ {
-+			brcm,pins = <8 7>;
-+			brcm,function = <4>; /* alt0 */
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts
-@@ -0,0 +1,57 @@
-+/dts-v1/;
-+/plugin/;
-+
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			spi1_pins: spi1_pins {
-+				brcm,pins = <19 20 21>;
-+				brcm,function = <3>; /* alt4 */
-+			};
-+
-+			spi1_cs_pins: spi1_cs_pins {
-+				brcm,pins = <18>;
-+				brcm,function = <1>; /* output */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi1>;
-+		frag1: __overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
-+			cs-gpios = <&gpio 18 1>;
-+			status = "okay";
-+
-+			spidev1_0: spidev@0 {
-+				compatible = "spidev";
-+				reg = <0>;      /* CE0 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&aux>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		cs0_pin  = <&spi1_cs_pins>,"brcm,pins:0",
-+			   <&frag1>,"cs-gpios:4";
-+		cs0_spidev = <&spidev1_0>,"status";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts
-@@ -0,0 +1,69 @@
-+/dts-v1/;
-+/plugin/;
-+
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			spi1_pins: spi1_pins {
-+				brcm,pins = <19 20 21>;
-+				brcm,function = <3>; /* alt4 */
-+			};
-+
-+			spi1_cs_pins: spi1_cs_pins {
-+				brcm,pins = <18 17>;
-+				brcm,function = <1>; /* output */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi1>;
-+		frag1: __overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
-+			cs-gpios = <&gpio 18 1>, <&gpio 17 1>;
-+			status = "okay";
-+
-+			spidev1_0: spidev@0 {
-+				compatible = "spidev";
-+				reg = <0>;      /* CE0 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+
-+			spidev1_1: spidev@1 {
-+				compatible = "spidev";
-+				reg = <1>;      /* CE1 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&aux>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		cs0_pin  = <&spi1_cs_pins>,"brcm,pins:0",
-+			   <&frag1>,"cs-gpios:4";
-+		cs1_pin  = <&spi1_cs_pins>,"brcm,pins:4",
-+			   <&frag1>,"cs-gpios:16";
-+		cs0_spidev = <&spidev1_0>,"status";
-+		cs1_spidev = <&spidev1_1>,"status";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts
-@@ -0,0 +1,81 @@
-+/dts-v1/;
-+/plugin/;
-+
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			spi1_pins: spi1_pins {
-+				brcm,pins = <19 20 21>;
-+				brcm,function = <3>; /* alt4 */
-+			};
-+
-+			spi1_cs_pins: spi1_cs_pins {
-+				brcm,pins = <18 17 16>;
-+				brcm,function = <1>; /* output */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi1>;
-+		frag1: __overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
-+			cs-gpios = <&gpio 18 1>, <&gpio 17 1>, <&gpio 16 1>;
-+			status = "okay";
-+
-+			spidev1_0: spidev@0 {
-+				compatible = "spidev";
-+				reg = <0>;      /* CE0 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+
-+			spidev1_1: spidev@1 {
-+				compatible = "spidev";
-+				reg = <1>;      /* CE1 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+
-+			spidev1_2: spidev@2 {
-+				compatible = "spidev";
-+				reg = <2>;      /* CE2 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&aux>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		cs0_pin  = <&spi1_cs_pins>,"brcm,pins:0",
-+			   <&frag1>,"cs-gpios:4";
-+		cs1_pin  = <&spi1_cs_pins>,"brcm,pins:4",
-+			   <&frag1>,"cs-gpios:16";
-+		cs2_pin  = <&spi1_cs_pins>,"brcm,pins:8",
-+			   <&frag1>,"cs-gpios:28";
-+		cs0_spidev = <&spidev1_0>,"status";
-+		cs1_spidev = <&spidev1_1>,"status";
-+		cs2_spidev = <&spidev1_2>,"status";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts
-@@ -0,0 +1,57 @@
-+/dts-v1/;
-+/plugin/;
-+
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			spi2_pins: spi2_pins {
-+				brcm,pins = <40 41 42>;
-+				brcm,function = <3>; /* alt4 */
-+			};
-+
-+			spi2_cs_pins: spi2_cs_pins {
-+				brcm,pins = <43>;
-+				brcm,function = <1>; /* output */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi2>;
-+		frag1: __overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&spi2_pins &spi2_cs_pins>;
-+			cs-gpios = <&gpio 43 1>;
-+			status = "okay";
-+
-+			spidev2_0: spidev@0 {
-+				compatible = "spidev";
-+				reg = <0>;      /* CE0 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&aux>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		cs0_pin  = <&spi2_cs_pins>,"brcm,pins:0",
-+			   <&frag1>,"cs-gpios:4";
-+		cs0_spidev = <&spidev2_0>,"status";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts
-@@ -0,0 +1,69 @@
-+/dts-v1/;
-+/plugin/;
-+
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			spi2_pins: spi2_pins {
-+				brcm,pins = <40 41 42>;
-+				brcm,function = <3>; /* alt4 */
-+			};
-+
-+			spi2_cs_pins: spi2_cs_pins {
-+				brcm,pins = <43 44>;
-+				brcm,function = <1>; /* output */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi2>;
-+		frag1: __overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&spi2_pins &spi2_cs_pins>;
-+			cs-gpios = <&gpio 43 1>, <&gpio 44 1>;
-+			status = "okay";
-+
-+			spidev2_0: spidev@0 {
-+				compatible = "spidev";
-+				reg = <0>;      /* CE0 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+
-+			spidev2_1: spidev@1 {
-+				compatible = "spidev";
-+				reg = <1>;      /* CE1 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&aux>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		cs0_pin  = <&spi2_cs_pins>,"brcm,pins:0",
-+			   <&frag1>,"cs-gpios:4";
-+		cs1_pin  = <&spi2_cs_pins>,"brcm,pins:4",
-+			   <&frag1>,"cs-gpios:16";
-+		cs0_spidev = <&spidev2_0>,"status";
-+		cs1_spidev = <&spidev2_1>,"status";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts
-@@ -0,0 +1,81 @@
-+/dts-v1/;
-+/plugin/;
-+
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			spi2_pins: spi2_pins {
-+				brcm,pins = <40 41 42>;
-+				brcm,function = <3>; /* alt4 */
-+			};
-+
-+			spi2_cs_pins: spi2_cs_pins {
-+				brcm,pins = <43 44 45>;
-+				brcm,function = <1>; /* output */
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spi2>;
-+		frag1: __overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&spi2_pins &spi2_cs_pins>;
-+			cs-gpios = <&gpio 43 1>, <&gpio 44 1>, <&gpio 45 1>;
-+			status = "okay";
-+
-+			spidev2_0: spidev@0 {
-+				compatible = "spidev";
-+				reg = <0>;      /* CE0 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+
-+			spidev2_1: spidev@1 {
-+				compatible = "spidev";
-+				reg = <1>;      /* CE1 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+
-+			spidev2_2: spidev@2 {
-+				compatible = "spidev";
-+				reg = <2>;      /* CE2 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <125000000>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&aux>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		cs0_pin  = <&spi2_cs_pins>,"brcm,pins:0",
-+			   <&frag1>,"cs-gpios:4";
-+		cs1_pin  = <&spi2_cs_pins>,"brcm,pins:4",
-+			   <&frag1>,"cs-gpios:16";
-+		cs2_pin  = <&spi2_cs_pins>,"brcm,pins:8",
-+			   <&frag1>,"cs-gpios:28";
-+		cs0_spidev = <&spidev2_0>,"status";
-+		cs1_spidev = <&spidev2_1>,"status";
-+		cs2_spidev = <&spidev2_2>,"status";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts
-@@ -0,0 +1,224 @@
-+/*
-+ * tinylcd35-overlay.dts
-+ *
-+ * -------------------------------------------------
-+ * www.tinlylcd.com
-+ * -------------------------------------------------
-+ * Device---Driver-----BUS       GPIO's
-+ * display  tinylcd35  spi0.0    25 24 18
-+ * touch    ads7846    spi0.1    5
-+ * rtc      ds1307     i2c1-0068
-+ * rtc      pcf8563    i2c1-0051
-+ * keypad   gpio-keys  --------- 17 22 27 23 28
-+ *
-+ *
-+ * TinyLCD.com 3.5 inch TFT
-+ *
-+ *  Version 001
-+ *  5/3/2015  -- Noralf Trønnes     Initial Device tree framework
-+ *  10/3/2015 -- tinylcd@gmail.com  added ds1307 support.
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			tinylcd35_pins: tinylcd35_pins {
-+				brcm,pins = <25 24 18>;
-+				brcm,function = <1>; /* out */
-+			};
-+			tinylcd35_ts_pins: tinylcd35_ts_pins {
-+				brcm,pins = <5>;
-+				brcm,function = <0>; /* in */
-+			};
-+			keypad_pins: keypad_pins {
-+				brcm,pins = <4 17 22 23 27>;
-+				brcm,function = <0>; /* in */
-+				brcm,pull = <1>; /* down */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			tinylcd35: tinylcd35@0{
-+				compatible = "neosec,tinylcd";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&tinylcd35_pins>,
-+					    <&tinylcd35_ts_pins>;
-+
-+				spi-max-frequency = <48000000>;
-+				rotate = <270>;
-+				fps = <20>;
-+				bgr;
-+				buswidth = <8>;
-+				reset-gpios = <&gpio 25 0>;
-+				dc-gpios = <&gpio 24 0>;
-+				led-gpios = <&gpio 18 1>;
-+				debug = <0>;
-+
-+				init = <0x10000B0 0x80
-+					0x10000C0 0x0A 0x0A
-+					0x10000C1 0x01 0x01
-+					0x10000C2 0x33
-+					0x10000C5 0x00 0x42 0x80
-+					0x10000B1 0xD0 0x11
-+					0x10000B4 0x02
-+					0x10000B6 0x00 0x22 0x3B
-+					0x10000B7 0x07
-+					0x1000036 0x58
-+					0x10000F0 0x36 0xA5 0xD3
-+					0x10000E5 0x80
-+					0x10000E5 0x01
-+					0x10000B3 0x00
-+					0x10000E5 0x00
-+					0x10000F0 0x36 0xA5 0x53
-+					0x10000E0 0x00 0x35 0x33 0x00 0x00 0x00 0x00 0x35 0x33 0x00 0x00 0x00
-+					0x100003A 0x55
-+					0x1000011
-+					0x2000001
-+					0x1000029>;
-+			};
-+
-+			tinylcd35_ts: tinylcd35_ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+				status = "disabled";
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <5 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 5 0>;
-+				ti,x-plate-ohms = /bits/ 16 <100>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+
-+	/*  RTC    */
-+
-+	fragment@5 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "okay";
-+
-+			pcf8563: pcf8563@51 {
-+				compatible = "nxp,pcf8563";
-+				reg = <0x51>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@6 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "okay";
-+
-+			ds1307: ds1307@68 {
-+				compatible = "maxim,ds1307";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	/*
-+	 * Values for input event code is found under the
-+	 * 'Keys and buttons' heading in include/uapi/linux/input.h
-+	 */
-+	fragment@7 {
-+		target-path = "/soc";
-+		__overlay__ {
-+			keypad: keypad {
-+				compatible = "gpio-keys";
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&keypad_pins>;
-+				status = "disabled";
-+				autorepeat;
-+
-+				button@17 {
-+					label = "GPIO KEY_UP";
-+					linux,code = <103>;
-+					gpios = <&gpio 17 0>;
-+				};
-+				button@22 {
-+					label = "GPIO KEY_DOWN";
-+					linux,code = <108>;
-+					gpios = <&gpio 22 0>;
-+				};
-+				button@27 {
-+					label = "GPIO KEY_LEFT";
-+					linux,code = <105>;
-+					gpios = <&gpio 27 0>;
-+				};
-+				button@23 {
-+					label = "GPIO KEY_RIGHT";
-+					linux,code = <106>;
-+					gpios = <&gpio 23 0>;
-+				};
-+				button@4 {
-+					label = "GPIO KEY_ENTER";
-+					linux,code = <28>;
-+					gpios = <&gpio 4 0>;
-+				};
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		speed =      <&tinylcd35>,"spi-max-frequency:0";
-+		rotate =     <&tinylcd35>,"rotate:0";
-+		fps =        <&tinylcd35>,"fps:0";
-+		debug =      <&tinylcd35>,"debug:0";
-+		touch =      <&tinylcd35_ts>,"status";
-+		touchgpio =  <&tinylcd35_ts_pins>,"brcm,pins:0",
-+			     <&tinylcd35_ts>,"interrupts:0",
-+			     <&tinylcd35_ts>,"pendown-gpio:4";
-+		xohms =      <&tinylcd35_ts>,"ti,x-plate-ohms;0";
-+		rtc-pcf =    <0>,"=5";
-+		rtc-ds =     <0>,"=6";
-+		keypad =     <&keypad>,"status";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/uart1-overlay.dts
-@@ -0,0 +1,38 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&uart1>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&uart1_pins>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			uart1_pins: uart1_pins {
-+				brcm,pins = <14 15>;
-+				brcm,function = <2>; /* alt5 */
-+				brcm,pull = <0 2>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "/chosen";
-+		__overlay__ {
-+			bootargs = "8250.nr_uarts=1";
-+		};
-+	};
-+
-+	__overrides__ {
-+		txd1_pin = <&uart1_pins>,"brcm,pins:0";
-+		rxd1_pin = <&uart1_pins>,"brcm,pins:4";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts
-@@ -0,0 +1,89 @@
-+/*
-+ * vc4-fkms-v3d-overlay.dts
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target-path = "/chosen";
-+		__overlay__ {
-+			bootargs = "cma=256M";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=192M";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=128M";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=96M";
-+		};
-+	};
-+
-+	fragment@4 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=64M";
-+		};
-+	};
-+
-+	fragment@5 {
-+		target = <&fb>;
-+		__overlay__  {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@6 {
-+		target = <&firmwarekms>;
-+		__overlay__  {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@7 {
-+		target = <&v3d>;
-+		__overlay__  {
-+			interrupts = <1 10>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@8 {
-+		target = <&gpu>;
-+		__overlay__  {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@9 {
-+		target-path = "/soc/dma";
-+		__overlay__ {
-+			brcm,dma-channel-mask = <0x7f35>;
-+		};
-+	};
-+
-+	__overrides__ {
-+		cma-256 = <0>,"+0-1-2-3-4";
-+		cma-192 = <0>,"-0+1-2-3-4";
-+		cma-128 = <0>,"-0-1+2-3-4";
-+		cma-96  = <0>,"-0-1-2+3-4";
-+		cma-64  = <0>,"-0-1-2-3+4";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
-@@ -0,0 +1,151 @@
-+/*
-+ * vc4-kms-v3d-overlay.dts
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+#include <dt-bindings/clock/bcm2835.h>
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target-path = "/chosen";
-+		__overlay__ {
-+			bootargs = "cma=256M";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=192M";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=128M";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=96M";
-+		};
-+	};
-+
-+	fragment@4 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=64M";
-+		};
-+	};
-+
-+	fragment@5 {
-+		target = <&i2c2>;
-+		__overlay__  {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@6 {
-+		target = <&cprman>;
-+		__overlay__  {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@7 {
-+		target = <&fb>;
-+		__overlay__  {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@8 {
-+		target = <&pixelvalve0>;
-+		__overlay__  {
-+			interrupts = <2 13>; /* pwa0 */
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@9 {
-+		target = <&pixelvalve1>;
-+		__overlay__  {
-+			interrupts = <2 14>; /* pwa1 */
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@10 {
-+		target = <&pixelvalve2>;
-+		__overlay__  {
-+			interrupts = <2 10>; /* pixelvalve */
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@11 {
-+		target = <&hvs>;
-+		__overlay__  {
-+			interrupts = <2 1>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@12 {
-+		target = <&hdmi>;
-+		__overlay__  {
-+			interrupts = <2 8>, <2 9>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@13 {
-+		target = <&v3d>;
-+		__overlay__  {
-+			interrupts = <1 10>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@14 {
-+		target = <&gpu>;
-+		__overlay__  {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@15 {
-+		target-path = "/soc/dma";
-+		__overlay__ {
-+			brcm,dma-channel-mask = <0x7f35>;
-+		};
-+	};
-+
-+
-+	fragment@16 {
-+		target = <&clocks>;
-+		__overlay__  {
-+			claim-clocks = <
-+				BCM2835_PLLD_DSI0
-+				BCM2835_PLLD_DSI1
-+				BCM2835_PLLH_AUX
-+				BCM2835_PLLH_PIX
-+			>;
-+		};
-+	};
-+
-+	__overrides__ {
-+		cma-256 = <0>,"+0-1-2-3-4";
-+		cma-192 = <0>,"-0+1-2-3-4";
-+		cma-128 = <0>,"-0-1+2-3-4";
-+		cma-96  = <0>,"-0-1-2+3-4";
-+		cma-64  = <0>,"-0-1-2-3+4";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/vga666-overlay.dts
-@@ -0,0 +1,30 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	// There is no VGA driver module, but we need a platform device
-+	// node (that doesn't already use pinctrl) to hang the pinctrl
-+	// reference on - leds will do
-+
-+	fragment@0 {
-+		target = <&leds>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&vga666_pins>;
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			vga666_pins: vga666_pins {
-+				brcm,pins = <2 3 4 5 6 7 8 9 10 11 12
-+					     13 14 15 16 17 18 19 20 21>;
-+				brcm,function = <6>; /* alt2 */
-+				brcm,pull = <0>; /* no pull */
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts
-@@ -0,0 +1,41 @@
-+// Definitions for w1-gpio module (without external pullup)
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+
-+			w1: onewire@0 {
-+				compatible = "w1-gpio";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&w1_pins>;
-+				gpios = <&gpio 4 0>;
-+				rpi,parasitic-power = <0>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			w1_pins: w1_pins@0 {
-+				brcm,pins = <4>;
-+				brcm,function = <0>; // in (initially)
-+				brcm,pull = <0>; // off
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpiopin =       <&w1>,"gpios:4",
-+				<&w1>,"reg:0",
-+				<&w1_pins>,"brcm,pins:0",
-+				<&w1_pins>,"reg:0";
-+		pullup =        <&w1>,"rpi,parasitic-power:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts
-@@ -0,0 +1,43 @@
-+// Definitions for w1-gpio module (with external pullup)
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+
-+			w1: onewire@0 {
-+				compatible = "w1-gpio";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&w1_pins>;
-+				gpios = <&gpio 4 0>, <&gpio 5 1>;
-+				rpi,parasitic-power = <0>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			w1_pins: w1_pins@0 {
-+				brcm,pins = <4 5>;
-+				brcm,function = <0 1>; // in out
-+				brcm,pull = <0 0>; // off off
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpiopin =       <&w1>,"gpios:4",
-+				<&w1>,"reg:0",
-+				<&w1_pins>,"brcm,pins:0",
-+				<&w1_pins>,"reg:0";
-+		extpullup =     <&w1>,"gpios:16",
-+				<&w1_pins>,"brcm,pins:4";
-+		pullup =        <&w1>,"rpi,parasitic-power:0";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/wittypi-overlay.dts
-@@ -0,0 +1,44 @@
-+/*
-+ * Device Tree overlay for Witty Pi extension board by UUGear
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&leds>;
-+		__overlay__ {
-+			compatible = "gpio-leds";
-+			wittypi_led: wittypi_led {
-+				label = "wittypi_led";
-+				linux,default-trigger = "default-on";
-+				gpios = <&gpio 17 0>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			rtc: ds1337@68 {
-+				compatible = "dallas,ds1337";
-+				reg = <0x68>;
-+				wakeup-source;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		led_gpio =	<&wittypi_led>,"gpios:4";
-+		led_trigger =	<&wittypi_led>,"linux,default-trigger";
-+	};
-+
-+};
---- a/scripts/Makefile.dtbinst
-+++ b/scripts/Makefile.dtbinst
-@@ -22,6 +22,7 @@ include scripts/Kbuild.include
- include $(src)/Makefile
- 
- dtbinst-files	:= $(dtb-y)
-+dtboinst-files	:= $(dtbo-y)
- dtbinst-dirs	:= $(dts-dirs)
- 
- # Helper targets for Installing DTBs into the boot directory
-@@ -33,10 +34,13 @@ install-dir = $(patsubst $(dtbinst_root)
- $(dtbinst-files): %.dtb: $(obj)/%.dtb
- 	$(call cmd,dtb_install,$(install-dir))
- 
-+$(dtboinst-files): %.dtbo: $(obj)/%.dtbo
-+	$(call cmd,dtb_install,$(install-dir))
-+
- $(dtbinst-dirs):
- 	$(Q)$(MAKE) $(dtbinst)=$(obj)/$@
- 
--PHONY += $(dtbinst-files) $(dtbinst-dirs)
--__dtbs_install: $(dtbinst-files) $(dtbinst-dirs)
-+PHONY += $(dtbinst-files) $(dtboinst-files) $(dtbinst-dirs)
-+__dtbs_install: $(dtbinst-files) $(dtboinst-files) $(dtbinst-dirs)
- 
- .PHONY: $(PHONY)
---- a/scripts/Makefile.lib
-+++ b/scripts/Makefile.lib
-@@ -316,6 +316,17 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
- $(obj)/%.dtb: $(src)/%.dts FORCE
- 	$(call if_changed_dep,dtc)
- 
-+quiet_cmd_dtco = DTCO    $@
-+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
-+	$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
-+	$(DTC) -@ -H epapr -O dtb -o $@ -b 0 \
-+		-i $(dir $<) $(DTC_FLAGS) \
-+		-d $(depfile).dtc.tmp $(dtc-tmp) ; \
-+	cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
-+
-+$(obj)/%.dtbo: $(src)/%-overlay.dts FORCE
-+	$(call if_changed_dep,dtco)
-+
- dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
- 
- # Bzip2
diff --git a/target/linux/brcm2708/patches-4.14/950-0055-BCM270x_DT-Add-pwr_led-and-the-required-input-trigge.patch b/target/linux/brcm2708/patches-4.14/950-0055-BCM270x_DT-Add-pwr_led-and-the-required-input-trigge.patch
deleted file mode 100644
index 12f17397d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0055-BCM270x_DT-Add-pwr_led-and-the-required-input-trigge.patch
+++ /dev/null
@@ -1,167 +0,0 @@
-From 55006c315659a66183d5513c1b441651a3c9a5fd Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 6 Feb 2015 13:50:57 +0000
-Subject: [PATCH 055/454] BCM270x_DT: Add pwr_led, and the required "input"
- trigger
-
-The "input" trigger makes the associated GPIO an input.  This is to support
-the Raspberry Pi PWR LED, which is driven by external hardware in normal use.
-
-N.B. pwr_led is not available on Model A or B boards.
-
-leds-gpio: Implement the brightness_get method
-
-The power LED uses some clever logic that means it is driven
-by a voltage measuring circuit when configured as input, otherwise
-it is driven by the GPIO output value. This patch wires up the
-brightness_get method for leds-gpio so that user-space can monitor
-the LED value via /sys/class/gpio/led1/brightness. Using the input
-trigger this returns an indication of the system power health,
-otherwise it is just whatever value the trigger has written most
-recently.
-
-See: https://github.com/raspberrypi/linux/issues/1064
----
- drivers/leds/leds-gpio.c             | 17 ++++++++-
- drivers/leds/trigger/Kconfig         |  7 ++++
- drivers/leds/trigger/Makefile        |  1 +
- drivers/leds/trigger/ledtrig-input.c | 54 ++++++++++++++++++++++++++++
- include/linux/leds.h                 |  3 ++
- 5 files changed, 81 insertions(+), 1 deletion(-)
- create mode 100644 drivers/leds/trigger/ledtrig-input.c
-
---- a/drivers/leds/leds-gpio.c
-+++ b/drivers/leds/leds-gpio.c
-@@ -50,8 +50,15 @@ static void gpio_led_set(struct led_clas
- 		led_dat->platform_gpio_blink_set(led_dat->gpiod, level,
- 						 NULL, NULL);
- 		led_dat->blinking = 0;
-+	} else if (led_dat->cdev.flags & SET_GPIO_INPUT) {
-+		gpiod_direction_input(led_dat->gpiod);
-+		led_dat->cdev.flags &= ~SET_GPIO_INPUT;
-+	} else if (led_dat->cdev.flags & SET_GPIO_OUTPUT) {
-+		gpiod_direction_output(led_dat->gpiod, level);
-+		led_dat->cdev.flags &= ~SET_GPIO_OUTPUT;
- 	} else {
--		if (led_dat->can_sleep)
-+		if (led_dat->can_sleep ||
-+			(led_dat->cdev.flags & (SET_GPIO_INPUT | SET_GPIO_OUTPUT) ))
- 			gpiod_set_value_cansleep(led_dat->gpiod, level);
- 		else
- 			gpiod_set_value(led_dat->gpiod, level);
-@@ -65,6 +72,13 @@ static int gpio_led_set_blocking(struct
- 	return 0;
- }
- 
-+static enum led_brightness gpio_led_get(struct led_classdev *led_cdev)
-+{
-+	struct gpio_led_data *led_dat =
-+		container_of(led_cdev, struct gpio_led_data, cdev);
-+	return gpiod_get_value_cansleep(led_dat->gpiod) ? LED_FULL : LED_OFF;
-+}
-+
- static int gpio_blink_set(struct led_classdev *led_cdev,
- 	unsigned long *delay_on, unsigned long *delay_off)
- {
-@@ -122,6 +136,7 @@ static int create_gpio_led(const struct
- 		led_dat->platform_gpio_blink_set = blink_set;
- 		led_dat->cdev.blink_set = gpio_blink_set;
- 	}
-+	led_dat->cdev.brightness_get = gpio_led_get;
- 	if (template->default_state == LEDS_GPIO_DEFSTATE_KEEP) {
- 		state = gpiod_get_value_cansleep(led_dat->gpiod);
- 		if (state < 0)
---- a/drivers/leds/trigger/Kconfig
-+++ b/drivers/leds/trigger/Kconfig
-@@ -116,6 +116,13 @@ config LEDS_TRIGGER_CAMERA
- 	  This enables direct flash/torch on/off by the driver, kernel space.
- 	  If unsure, say Y.
- 
-+config LEDS_TRIGGER_INPUT
-+	tristate "LED Input Trigger"
-+	depends on LEDS_TRIGGERS
-+	help
-+	  This allows the GPIOs assigned to be LEDs to be initialised to inputs.
-+	  If unsure, say Y.
-+
- config LEDS_TRIGGER_PANIC
- 	bool "LED Panic Trigger"
- 	depends on LEDS_TRIGGERS
---- a/drivers/leds/trigger/Makefile
-+++ b/drivers/leds/trigger/Makefile
-@@ -10,5 +10,6 @@ obj-$(CONFIG_LEDS_TRIGGER_CPU)		+= ledtr
- obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON)	+= ledtrig-default-on.o
- obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT)	+= ledtrig-transient.o
- obj-$(CONFIG_LEDS_TRIGGER_CAMERA)	+= ledtrig-camera.o
-+obj-$(CONFIG_LEDS_TRIGGER_INPUT)	+= ledtrig-input.o
- obj-$(CONFIG_LEDS_TRIGGER_PANIC)	+= ledtrig-panic.o
- obj-$(CONFIG_LEDS_TRIGGER_NETDEV)	+= ledtrig-netdev.o
---- /dev/null
-+++ b/drivers/leds/trigger/ledtrig-input.c
-@@ -0,0 +1,54 @@
-+/*
-+ * Set LED GPIO to Input "Trigger"
-+ *
-+ * Copyright 2015 Phil Elwell <phil@raspberrypi.org>
-+ *
-+ * Based on Nick Forbes's ledtrig-default-on.c.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
-+#include "../leds.h"
-+
-+static void input_trig_activate(struct led_classdev *led_cdev)
-+{
-+	led_cdev->flags |= SET_GPIO_INPUT;
-+	led_set_brightness(led_cdev, 0);
-+}
-+
-+static void input_trig_deactivate(struct led_classdev *led_cdev)
-+{
-+	led_cdev->flags |= SET_GPIO_OUTPUT;
-+	led_set_brightness(led_cdev, 0);
-+}
-+
-+static struct led_trigger input_led_trigger = {
-+	.name     = "input",
-+	.activate = input_trig_activate,
-+	.deactivate = input_trig_deactivate,
-+};
-+
-+static int __init input_trig_init(void)
-+{
-+	return led_trigger_register(&input_led_trigger);
-+}
-+
-+static void __exit input_trig_exit(void)
-+{
-+	led_trigger_unregister(&input_led_trigger);
-+}
-+
-+module_init(input_trig_init);
-+module_exit(input_trig_exit);
-+
-+MODULE_AUTHOR("Phil Elwell <phil@raspberrypi.org>");
-+MODULE_DESCRIPTION("Set LED GPIO to Input \"trigger\"");
-+MODULE_LICENSE("GPL");
---- a/include/linux/leds.h
-+++ b/include/linux/leds.h
-@@ -50,6 +50,9 @@ struct led_classdev {
- #define LED_PANIC_INDICATOR	(1 << 20)
- #define LED_BRIGHT_HW_CHANGED	(1 << 21)
- #define LED_RETAIN_AT_SHUTDOWN	(1 << 22)
-+	/* Additions for Raspberry Pi PWR LED */
-+#define SET_GPIO_INPUT		(1 << 30)
-+#define SET_GPIO_OUTPUT		(1 << 31)
- 
- 	/* set_brightness_work / blink_timer flags, atomic, private. */
- 	unsigned long		work_flags;
diff --git a/target/linux/brcm2708/patches-4.14/950-0056-fbdev-add-FBIOCOPYAREA-ioctl.patch b/target/linux/brcm2708/patches-4.14/950-0056-fbdev-add-FBIOCOPYAREA-ioctl.patch
deleted file mode 100644
index b01c2203e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0056-fbdev-add-FBIOCOPYAREA-ioctl.patch
+++ /dev/null
@@ -1,264 +0,0 @@
-From d56622a9c76ab913da66bb22c3158b10f9fb0543 Mon Sep 17 00:00:00 2001
-From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
-Date: Mon, 17 Jun 2013 13:32:11 +0300
-Subject: [PATCH 056/454] fbdev: add FBIOCOPYAREA ioctl
-
-Based on the patch authored by Ali Gholami Rudi at
-    https://lkml.org/lkml/2009/7/13/153
-
-Provide an ioctl for userspace applications, but only if this operation
-is hardware accelerated (otherwide it does not make any sense).
-
-Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
-
-bcm2708_fb: Add ioctl for reading gpu memory through dma
----
- drivers/video/fbdev/bcm2708_fb.c | 111 +++++++++++++++++++++++++++++++
- drivers/video/fbdev/core/fbmem.c |  36 ++++++++++
- include/uapi/linux/fb.h          |  12 ++++
- 3 files changed, 159 insertions(+)
-
---- a/drivers/video/fbdev/bcm2708_fb.c
-+++ b/drivers/video/fbdev/bcm2708_fb.c
-@@ -31,8 +31,10 @@
- #include <linux/console.h>
- #include <linux/debugfs.h>
- #include <asm/sizes.h>
-+#include <linux/uaccess.h>
- #include <linux/io.h>
- #include <linux/dma-mapping.h>
-+#include <linux/cred.h>
- #include <soc/bcm2835/raspberrypi-firmware.h>
- 
- //#define BCM2708_FB_DEBUG
-@@ -94,6 +96,7 @@ struct bcm2708_fb {
- 	wait_queue_head_t dma_waitq;
- 	struct bcm2708_fb_stats stats;
- 	unsigned long fb_bus_address;
-+	struct { u32 base, length; } gpu;
- };
- 
- #define to_bcm2708(info)	container_of(info, struct bcm2708_fb, fb)
-@@ -426,6 +429,106 @@ static int bcm2708_fb_pan_display(struct
- 	return result;
- }
- 
-+static void dma_memcpy(struct bcm2708_fb *fb, dma_addr_t dst, dma_addr_t src, int size)
-+{
-+	int burst_size = (fb->dma_chan == 0) ? 8 : 2;
-+	struct bcm2708_dma_cb *cb = fb->cb_base;
-+
-+	cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH |
-+		   BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |
-+		   BCM2708_DMA_D_INC;
-+	cb->dst = dst;
-+	cb->src = src;
-+	cb->length = size;
-+	cb->stride = 0;
-+	cb->pad[0] = 0;
-+	cb->pad[1] = 0;
-+	cb->next = 0;
-+
-+	if (size < dma_busy_wait_threshold) {
-+		bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
-+		bcm_dma_wait_idle(fb->dma_chan_base);
-+	} else {
-+		void __iomem *dma_chan = fb->dma_chan_base;
-+		cb->info |= BCM2708_DMA_INT_EN;
-+		bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
-+		while (bcm_dma_is_busy(dma_chan)) {
-+			wait_event_interruptible(
-+				fb->dma_waitq,
-+				!bcm_dma_is_busy(dma_chan));
-+		}
-+		fb->stats.dma_irqs++;
-+	}
-+	fb->stats.dma_copies++;
-+}
-+
-+#define INTALIAS_NORMAL(x) ((x)&~0xc0000000) // address with no aliases
-+#define INTALIAS_L1L2_NONALLOCATING(x) (((x)&~0xc0000000)|0x80000000) // cache coherent but non-allocating in L1 and L2
-+
-+static long vc_mem_copy(struct bcm2708_fb *fb, unsigned long arg)
-+{
-+	struct fb_dmacopy ioparam;
-+	size_t size = PAGE_SIZE;
-+	u32 *buf = NULL;
-+	dma_addr_t bus_addr;
-+	long rc = 0;
-+	size_t offset;
-+
-+	/* restrict this to root user */
-+	if (!uid_eq(current_euid(), GLOBAL_ROOT_UID))
-+	{
-+		rc = -EFAULT;
-+		goto out;
-+	}
-+
-+	/* Get the parameter data.
-+	 */
-+	if (copy_from_user
-+	    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {
-+		pr_err("[%s]: failed to copy-from-user\n",
-+				__func__);
-+		rc = -EFAULT;
-+		goto out;
-+	}
-+
-+	if (fb->gpu.base == 0 || fb->gpu.length == 0) {
-+		pr_err("[%s]: Unable to determine gpu memory (%x,%x)\n", __func__, fb->gpu.base, fb->gpu.length);
-+		return -EFAULT;
-+	}
-+
-+	if (INTALIAS_NORMAL(ioparam.src) < fb->gpu.base || INTALIAS_NORMAL(ioparam.src) >= fb->gpu.base + fb->gpu.length) {
-+		pr_err("[%s]: Invalid memory access %x (%x-%x)", __func__, INTALIAS_NORMAL(ioparam.src), fb->gpu.base, fb->gpu.base + fb->gpu.length);
-+		return -EFAULT;
-+	}
-+
-+	buf = dma_alloc_coherent(fb->fb.device, PAGE_ALIGN(size), &bus_addr,
-+				 GFP_ATOMIC);
-+	if (!buf) {
-+		pr_err("[%s]: failed to dma_alloc_coherent(%d)\n",
-+				__func__, size);
-+		rc = -ENOMEM;
-+		goto out;
-+	}
-+
-+	for (offset = 0; offset < ioparam.length; offset += size) {
-+		size_t remaining = ioparam.length - offset;
-+		size_t s = min(size, remaining);
-+		unsigned char *p = (unsigned char *)ioparam.src + offset;
-+		unsigned char *q = (unsigned char *)ioparam.dst + offset;
-+		dma_memcpy(fb, bus_addr, INTALIAS_L1L2_NONALLOCATING((dma_addr_t)p), size);
-+		if (copy_to_user(q, buf, s) != 0) {
-+			pr_err("[%s]: failed to copy-to-user\n",
-+					__func__);
-+			rc = -EFAULT;
-+			goto out;
-+		}
-+	}
-+out:
-+	if (buf)
-+		dma_free_coherent(fb->fb.device, PAGE_ALIGN(size), buf, bus_addr);
-+	return rc;
-+}
-+
- static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
- {
- 	struct bcm2708_fb *fb = to_bcm2708(info);
-@@ -438,6 +541,9 @@ static int bcm2708_ioctl(struct fb_info
- 					    RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC,
- 					    &dummy, sizeof(dummy));
- 		break;
-+	case FBIODMACOPY:
-+		ret = vc_mem_copy(fb, arg);
-+		break;
- 	default:
- 		dev_dbg(info->device, "Unknown ioctl 0x%x\n", cmd);
- 		return -ENOTTY;
-@@ -760,6 +866,11 @@ static int bcm2708_fb_probe(struct platf
- 	fb->dev = dev;
- 	fb->fb.device = &dev->dev;
- 
-+	// failure here isn't fatal, but we'll fail in vc_mem_copy if fb->gpu is not valid
-+	rpi_firmware_property(fb->fw,
-+				    RPI_FIRMWARE_GET_VC_MEMORY,
-+				    &fb->gpu, sizeof(fb->gpu));
-+
- 	ret = bcm2708_fb_register(fb);
- 	if (ret == 0) {
- 		platform_set_drvdata(dev, fb);
---- a/drivers/video/fbdev/core/fbmem.c
-+++ b/drivers/video/fbdev/core/fbmem.c
-@@ -1086,6 +1086,31 @@ fb_blank(struct fb_info *info, int blank
- }
- EXPORT_SYMBOL(fb_blank);
- 
-+static int fb_copyarea_user(struct fb_info *info,
-+			    struct fb_copyarea *copy)
-+{
-+	int ret = 0;
-+	if (!lock_fb_info(info))
-+		return -ENODEV;
-+	if (copy->dx >= info->var.xres ||
-+	    copy->sx >= info->var.xres ||
-+	    copy->width > info->var.xres ||
-+	    copy->dy >= info->var.yres ||
-+	    copy->sy >= info->var.yres ||
-+	    copy->height > info->var.yres ||
-+	    copy->dx + copy->width > info->var.xres ||
-+	    copy->sx + copy->width > info->var.xres ||
-+	    copy->dy + copy->height > info->var.yres ||
-+	    copy->sy + copy->height > info->var.yres) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+	info->fbops->fb_copyarea(info, copy);
-+out:
-+	unlock_fb_info(info);
-+	return ret;
-+}
-+
- static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
- 			unsigned long arg)
- {
-@@ -1096,6 +1121,7 @@ static long do_fb_ioctl(struct fb_info *
- 	struct fb_cmap cmap_from;
- 	struct fb_cmap_user cmap;
- 	struct fb_event event;
-+	struct fb_copyarea copy;
- 	void __user *argp = (void __user *)arg;
- 	long ret = 0;
- 
-@@ -1213,6 +1239,15 @@ static long do_fb_ioctl(struct fb_info *
- 		unlock_fb_info(info);
- 		console_unlock();
- 		break;
-+	case FBIOCOPYAREA:
-+		if (info->flags & FBINFO_HWACCEL_COPYAREA) {
-+			/* only provide this ioctl if it is accelerated */
-+			if (copy_from_user(&copy, argp, sizeof(copy)))
-+				return -EFAULT;
-+			ret = fb_copyarea_user(info, &copy);
-+			break;
-+		}
-+		/* fall through */
- 	default:
- 		if (!lock_fb_info(info))
- 			return -ENODEV;
-@@ -1358,6 +1393,7 @@ static long fb_compat_ioctl(struct file
- 	case FBIOPAN_DISPLAY:
- 	case FBIOGET_CON2FBMAP:
- 	case FBIOPUT_CON2FBMAP:
-+	case FBIOCOPYAREA:
- 		arg = (unsigned long) compat_ptr(arg);
- 	case FBIOBLANK:
- 		ret = do_fb_ioctl(info, cmd, arg);
---- a/include/uapi/linux/fb.h
-+++ b/include/uapi/linux/fb.h
-@@ -35,6 +35,12 @@
- #define FBIOPUT_MODEINFO        0x4617
- #define FBIOGET_DISPINFO        0x4618
- #define FBIO_WAITFORVSYNC	_IOW('F', 0x20, __u32)
-+/*
-+ * HACK: use 'z' in order not to clash with any other ioctl numbers which might
-+ * be concurrently added to the mainline kernel
-+ */
-+#define FBIOCOPYAREA		_IOW('z', 0x21, struct fb_copyarea)
-+#define FBIODMACOPY 		_IOW('z', 0x22, struct fb_dmacopy)
- 
- #define FB_TYPE_PACKED_PIXELS		0	/* Packed Pixels	*/
- #define FB_TYPE_PLANES			1	/* Non interleaved planes */
-@@ -347,6 +353,12 @@ struct fb_copyarea {
- 	__u32 sy;
- };
- 
-+struct fb_dmacopy {
-+	void *dst;
-+	__u32 src;
-+	__u32 length;
-+};
-+
- struct fb_fillrect {
- 	__u32 dx;	/* screen-relative */
- 	__u32 dy;
diff --git a/target/linux/brcm2708/patches-4.14/950-0057-Speed-up-console-framebuffer-imageblit-function.patch b/target/linux/brcm2708/patches-4.14/950-0057-Speed-up-console-framebuffer-imageblit-function.patch
deleted file mode 100644
index a6d3234f2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0057-Speed-up-console-framebuffer-imageblit-function.patch
+++ /dev/null
@@ -1,209 +0,0 @@
-From 0b3eb7b8f3ac701b27253ce407041ed69784306e Mon Sep 17 00:00:00 2001
-From: Harm Hanemaaijer <fgenfb@yahoo.com>
-Date: Thu, 20 Jun 2013 20:21:39 +0200
-Subject: [PATCH 057/454] Speed up console framebuffer imageblit function
-
-Especially on platforms with a slower CPU but a relatively high
-framebuffer fill bandwidth, like current ARM devices, the existing
-console monochrome imageblit function used to draw console text is
-suboptimal for common pixel depths such as 16bpp and 32bpp. The existing
-code is quite general and can deal with several pixel depths. By creating
-special case functions for 16bpp and 32bpp, by far the most common pixel
-formats used on modern systems, a significant speed-up is attained
-which can be readily felt on ARM-based devices like the Raspberry Pi
-and the Allwinner platform, but should help any platform using the
-fb layer.
-
-The special case functions allow constant folding, eliminating a number
-of instructions including divide operations, and allow the use of an
-unrolled loop, eliminating instructions with a variable shift size,
-reducing source memory access instructions, and eliminating excessive
-branching. These unrolled loops also allow much better code optimization
-by the C compiler. The code that selects which optimized variant is used
-is also simplified, eliminating integer divide instructions.
-
-The speed-up, measured by timing 'cat file.txt' in the console, varies
-between 40% and 70%, when testing on the Raspberry Pi and Allwinner
-ARM-based platforms, depending on font size and the pixel depth, with
-the greater benefit for 32bpp.
-
-Signed-off-by: Harm Hanemaaijer <fgenfb@yahoo.com>
----
- drivers/video/fbdev/core/cfbimgblt.c | 152 ++++++++++++++++++++++++++-
- 1 file changed, 147 insertions(+), 5 deletions(-)
-
---- a/drivers/video/fbdev/core/cfbimgblt.c
-+++ b/drivers/video/fbdev/core/cfbimgblt.c
-@@ -28,6 +28,11 @@
-  *
-  *  Also need to add code to deal with cards endians that are different than
-  *  the native cpu endians. I also need to deal with MSB position in the word.
-+ *  Modified by Harm Hanemaaijer (fgenfb@yahoo.com) 2013:
-+ *  - Provide optimized versions of fast_imageblit for 16 and 32bpp that are
-+ *    significantly faster than the previous implementation.
-+ *  - Simplify the fast/slow_imageblit selection code, avoiding integer
-+ *    divides.
-  */
- #include <linux/module.h>
- #include <linux/string.h>
-@@ -262,6 +267,133 @@ static inline void fast_imageblit(const
- 	}
- }	
- 	
-+/*
-+ * Optimized fast_imageblit for bpp == 16. ppw = 2, bit_mask = 3 folded
-+ * into the code, main loop unrolled.
-+ */
-+
-+static inline void fast_imageblit16(const struct fb_image *image,
-+				    struct fb_info *p, u8 __iomem * dst1,
-+				    u32 fgcolor, u32 bgcolor)
-+{
-+	u32 fgx = fgcolor, bgx = bgcolor;
-+	u32 spitch = (image->width + 7) / 8;
-+	u32 end_mask, eorx;
-+	const char *s = image->data, *src;
-+	u32 __iomem *dst;
-+	const u32 *tab = NULL;
-+	int i, j, k;
-+
-+	tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le;
-+
-+	fgx <<= 16;
-+	bgx <<= 16;
-+	fgx |= fgcolor;
-+	bgx |= bgcolor;
-+
-+	eorx = fgx ^ bgx;
-+	k = image->width / 2;
-+
-+	for (i = image->height; i--;) {
-+		dst = (u32 __iomem *) dst1;
-+		src = s;
-+
-+		j = k;
-+		while (j >= 4) {
-+			u8 bits = *src;
-+			end_mask = tab[(bits >> 6) & 3];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[(bits >> 4) & 3];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[(bits >> 2) & 3];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[bits & 3];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			src++;
-+			j -= 4;
-+		}
-+		if (j != 0) {
-+			u8 bits = *src;
-+			end_mask = tab[(bits >> 6) & 3];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			if (j >= 2) {
-+				end_mask = tab[(bits >> 4) & 3];
-+				FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+				if (j == 3) {
-+					end_mask = tab[(bits >> 2) & 3];
-+					FB_WRITEL((end_mask & eorx) ^ bgx, dst);
-+				}
-+			}
-+		}
-+		dst1 += p->fix.line_length;
-+		s += spitch;
-+	}
-+}
-+
-+/*
-+ * Optimized fast_imageblit for bpp == 32. ppw = 1, bit_mask = 1 folded
-+ * into the code, main loop unrolled.
-+ */
-+
-+static inline void fast_imageblit32(const struct fb_image *image,
-+				    struct fb_info *p, u8 __iomem * dst1,
-+				    u32 fgcolor, u32 bgcolor)
-+{
-+	u32 fgx = fgcolor, bgx = bgcolor;
-+	u32 spitch = (image->width + 7) / 8;
-+	u32 end_mask, eorx;
-+	const char *s = image->data, *src;
-+	u32 __iomem *dst;
-+	const u32 *tab = NULL;
-+	int i, j, k;
-+
-+	tab = cfb_tab32;
-+
-+	eorx = fgx ^ bgx;
-+	k = image->width;
-+
-+	for (i = image->height; i--;) {
-+		dst = (u32 __iomem *) dst1;
-+		src = s;
-+
-+		j = k;
-+		while (j >= 8) {
-+			u8 bits = *src;
-+			end_mask = tab[(bits >> 7) & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[(bits >> 6) & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[(bits >> 5) & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[(bits >> 4) & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[(bits >> 3) & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[(bits >> 2) & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[(bits >> 1) & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			end_mask = tab[bits & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+			src++;
-+			j -= 8;
-+		}
-+		if (j != 0) {
-+			u32 bits = (u32) * src;
-+			while (j > 1) {
-+				end_mask = tab[(bits >> 7) & 1];
-+				FB_WRITEL((end_mask & eorx) ^ bgx, dst++);
-+				bits <<= 1;
-+				j--;
-+			}
-+			end_mask = tab[(bits >> 7) & 1];
-+			FB_WRITEL((end_mask & eorx) ^ bgx, dst);
-+		}
-+		dst1 += p->fix.line_length;
-+		s += spitch;
-+	}
-+}
-+
- void cfb_imageblit(struct fb_info *p, const struct fb_image *image)
- {
- 	u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
-@@ -294,11 +426,21 @@ void cfb_imageblit(struct fb_info *p, co
- 			bgcolor = image->bg_color;
- 		}	
- 		
--		if (32 % bpp == 0 && !start_index && !pitch_index && 
--		    ((width & (32/bpp-1)) == 0) &&
--		    bpp >= 8 && bpp <= 32) 			
--			fast_imageblit(image, p, dst1, fgcolor, bgcolor);
--		else 
-+		if (!start_index && !pitch_index) {
-+			if (bpp == 32)
-+				fast_imageblit32(image, p, dst1, fgcolor,
-+						 bgcolor);
-+			else if (bpp == 16 && (width & 1) == 0)
-+				fast_imageblit16(image, p, dst1, fgcolor,
-+						 bgcolor);
-+			else if (bpp == 8 && (width & 3) == 0)
-+				fast_imageblit(image, p, dst1, fgcolor,
-+					       bgcolor);
-+			else
-+				slow_imageblit(image, p, dst1, fgcolor,
-+					       bgcolor,
-+					       start_index, pitch_index);
-+		} else
- 			slow_imageblit(image, p, dst1, fgcolor, bgcolor,
- 					start_index, pitch_index);
- 	} else
diff --git a/target/linux/brcm2708/patches-4.14/950-0058-enabling-the-realtime-clock-1-wire-chip-DS1307-and-1.patch b/target/linux/brcm2708/patches-4.14/950-0058-enabling-the-realtime-clock-1-wire-chip-DS1307-and-1.patch
deleted file mode 100644
index d43410206..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0058-enabling-the-realtime-clock-1-wire-chip-DS1307-and-1.patch
+++ /dev/null
@@ -1,221 +0,0 @@
-From dc2d8a486db8a21cd998b0bdb117d30b8034aceb Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Wed, 8 May 2013 11:46:50 +0100
-Subject: [PATCH 058/454] enabling the realtime clock 1-wire chip DS1307 and
- 1-wire on GPIO4 (as a module)
-
-1-wire: Add support for configuring pin for w1-gpio kernel module
-See: https://github.com/raspberrypi/linux/pull/457
-
-Add bitbanging pullups, use them for w1-gpio
-
-Allows parasite power to work, uses module option pullup=1
-
-bcm2708: Ensure 1-wire pullup is disabled by default, and expose as module parameter
-
-Signed-off-by: Alex J Lennon <ajlennon@dynamicdevices.co.uk>
-
-w1-gpio: Add gpiopin module parameter and correctly free up gpio pull-up pin, if set
-
-Signed-off-by: Alex J Lennon <ajlennon@dynamicdevices.co.uk>
-
-w1-gpio: Sort out the pullup/parasitic power tangle
----
- drivers/w1/masters/w1-gpio.c | 69 ++++++++++++++++++++++++++++++++----
- drivers/w1/w1_int.c          | 14 ++++++++
- drivers/w1/w1_io.c           | 18 ++++++++--
- include/linux/w1-gpio.h      |  1 +
- include/linux/w1.h           |  6 ++++
- 5 files changed, 99 insertions(+), 9 deletions(-)
-
---- a/drivers/w1/masters/w1-gpio.c
-+++ b/drivers/w1/masters/w1-gpio.c
-@@ -22,6 +22,19 @@
- 
- #include <linux/w1.h>
- 
-+static int w1_gpio_pullup = 0;
-+static int w1_gpio_pullup_orig = 0;
-+module_param_named(pullup, w1_gpio_pullup, int, 0);
-+MODULE_PARM_DESC(pullup, "Enable parasitic power (power on data) mode");
-+static int w1_gpio_pullup_pin = -1;
-+static int w1_gpio_pullup_pin_orig = -1;
-+module_param_named(extpullup, w1_gpio_pullup_pin, int, 0);
-+MODULE_PARM_DESC(extpullup, "GPIO external pullup pin number");
-+static int w1_gpio_pin = -1;
-+static int w1_gpio_pin_orig = -1;
-+module_param_named(gpiopin, w1_gpio_pin, int, 0);
-+MODULE_PARM_DESC(gpiopin, "GPIO pin number");
-+
- static u8 w1_gpio_set_pullup(void *data, int delay)
- {
- 	struct w1_gpio_platform_data *pdata = data;
-@@ -66,6 +79,16 @@ static u8 w1_gpio_read_bit(void *data)
- 	return gpio_get_value(pdata->pin) ? 1 : 0;
- }
- 
-+static void w1_gpio_bitbang_pullup(void *data, u8 on)
-+{
-+	struct w1_gpio_platform_data *pdata = data;
-+
-+	if (on)
-+		gpio_direction_output(pdata->pin, 1);
-+	else
-+		gpio_direction_input(pdata->pin);
-+}
-+
- #if defined(CONFIG_OF)
- static const struct of_device_id w1_gpio_dt_ids[] = {
- 	{ .compatible = "w1-gpio" },
-@@ -79,6 +102,7 @@ static int w1_gpio_probe_dt(struct platf
- 	struct w1_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
- 	struct device_node *np = pdev->dev.of_node;
- 	int gpio;
-+	u32 value;
- 
- 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
- 	if (!pdata)
-@@ -87,6 +111,9 @@ static int w1_gpio_probe_dt(struct platf
- 	if (of_get_property(np, "linux,open-drain", NULL))
- 		pdata->is_open_drain = 1;
- 
-+	if (of_property_read_u32(np, "rpi,parasitic-power", &value) == 0)
-+	    pdata->parasitic_power = (value != 0);
-+
- 	gpio = of_get_gpio(np, 0);
- 	if (gpio < 0) {
- 		if (gpio != -EPROBE_DEFER)
-@@ -102,7 +129,7 @@ static int w1_gpio_probe_dt(struct platf
- 	if (gpio == -EPROBE_DEFER)
- 		return gpio;
- 	/* ignore other errors as the pullup gpio is optional */
--	pdata->ext_pullup_enable_pin = gpio;
-+	pdata->ext_pullup_enable_pin = (gpio >= 0) ? gpio : -1;
- 
- 	pdev->dev.platform_data = pdata;
- 
-@@ -134,6 +161,22 @@ static int w1_gpio_probe(struct platform
- 		return -ENOMEM;
- 	}
- 
-+	w1_gpio_pin_orig = pdata->pin;
-+	w1_gpio_pullup_pin_orig = pdata->ext_pullup_enable_pin;
-+	w1_gpio_pullup_orig = pdata->parasitic_power;
-+
-+	if(gpio_is_valid(w1_gpio_pin)) {
-+		pdata->pin = w1_gpio_pin;
-+		pdata->ext_pullup_enable_pin = -1;
-+		pdata->parasitic_power = -1;
-+	}
-+	pdata->parasitic_power |= w1_gpio_pullup;
-+	if(gpio_is_valid(w1_gpio_pullup_pin)) {
-+		pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin;
-+	}
-+
-+	dev_info(&pdev->dev, "gpio pin %d, external pullup pin %d, parasitic power %d\n", pdata->pin, pdata->ext_pullup_enable_pin, pdata->parasitic_power);
-+
- 	err = devm_gpio_request(&pdev->dev, pdata->pin, "w1");
- 	if (err) {
- 		dev_err(&pdev->dev, "gpio_request (pin) failed\n");
-@@ -163,6 +206,14 @@ static int w1_gpio_probe(struct platform
- 		master->set_pullup = w1_gpio_set_pullup;
- 	}
- 
-+	if (pdata->parasitic_power) {
-+		if (pdata->is_open_drain)
-+			printk(KERN_ERR "w1-gpio 'pullup'(parasitic power) "
-+			       "option doesn't work with open drain GPIO\n");
-+		else
-+			master->bitbang_pullup = w1_gpio_bitbang_pullup;
-+	}
-+
- 	err = w1_add_master_device(master);
- 	if (err) {
- 		dev_err(&pdev->dev, "w1_add_master device failed\n");
-@@ -193,6 +244,10 @@ static int w1_gpio_remove(struct platfor
- 
- 	w1_remove_master_device(master);
- 
-+	pdata->pin = w1_gpio_pin_orig;
-+	pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin_orig;
-+	pdata->parasitic_power = w1_gpio_pullup_orig;
-+
- 	return 0;
- }
- 
---- a/drivers/w1/w1_int.c
-+++ b/drivers/w1/w1_int.c
-@@ -114,6 +114,20 @@ int w1_add_master_device(struct w1_bus_m
- 		return(-EINVAL);
- 	}
- 
-+	/* bitbanging hardware uses bitbang_pullup, other hardware uses set_pullup
-+	 * and takes care of timing itself */
-+	if (!master->write_byte && !master->touch_bit && master->set_pullup) {
-+		printk(KERN_ERR "w1_add_master_device: set_pullup requires "
-+			"write_byte or touch_bit, disabling\n");
-+		master->set_pullup = NULL;
-+	}
-+
-+	if (master->set_pullup && master->bitbang_pullup) {
-+		printk(KERN_ERR "w1_add_master_device: set_pullup should not "
-+		       "be set when bitbang_pullup is used, disabling\n");
-+		master->set_pullup = NULL;
-+	}
-+
- 	/* Lock until the device is added (or not) to w1_masters. */
- 	mutex_lock(&w1_mlock);
- 	/* Search for the first available id (starting at 1). */
---- a/drivers/w1/w1_io.c
-+++ b/drivers/w1/w1_io.c
-@@ -126,10 +126,22 @@ static void w1_pre_write(struct w1_maste
- static void w1_post_write(struct w1_master *dev)
- {
- 	if (dev->pullup_duration) {
--		if (dev->enable_pullup && dev->bus_master->set_pullup)
--			dev->bus_master->set_pullup(dev->bus_master->data, 0);
--		else
-+		if (dev->enable_pullup) {
-+			if (dev->bus_master->set_pullup) {
-+				dev->bus_master->set_pullup(dev->
-+							    bus_master->data,
-+							    0);
-+			} else if (dev->bus_master->bitbang_pullup) {
-+				dev->bus_master->
-+				    bitbang_pullup(dev->bus_master->data, 1);
- 			msleep(dev->pullup_duration);
-+				dev->bus_master->
-+				    bitbang_pullup(dev->bus_master->data, 0);
-+			}
-+		} else {
-+			msleep(dev->pullup_duration);
-+		}
-+
- 		dev->pullup_duration = 0;
- 	}
- }
---- a/include/linux/w1-gpio.h
-+++ b/include/linux/w1-gpio.h
-@@ -18,6 +18,7 @@
- struct w1_gpio_platform_data {
- 	unsigned int pin;
- 	unsigned int is_open_drain:1;
-+	unsigned int parasitic_power:1;
- 	void (*enable_external_pullup)(int enable);
- 	unsigned int ext_pullup_enable_pin;
- 	unsigned int pullup_duration;
---- a/include/linux/w1.h
-+++ b/include/linux/w1.h
-@@ -157,6 +157,12 @@ struct w1_bus_master {
- 
- 	u8		(*set_pullup)(void *, int);
- 
-+	/**
-+	 * Turns the pullup on/off in bitbanging mode, takes an on/off argument.
-+	 * @return -1=Error, 0=completed
-+	 */
-+	void (*bitbang_pullup) (void *, u8);
-+
- 	void		(*search)(void *, struct w1_master *,
- 		u8, w1_slave_found_callback);
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0059-Added-Device-IDs-for-August-DVB-T-205.patch b/target/linux/brcm2708/patches-4.14/950-0059-Added-Device-IDs-for-August-DVB-T-205.patch
deleted file mode 100644
index d394f77b4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0059-Added-Device-IDs-for-August-DVB-T-205.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From 349f66715513ef170b3aa895e81ebd83ac006c70 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Wed, 3 Jul 2013 00:54:08 +0100
-Subject: [PATCH 059/454] Added Device IDs for August DVB-T 205
-
----
- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
-+++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
-@@ -1917,6 +1917,10 @@ static const struct usb_device_id rtl28x
- 		&rtl28xxu_props, "Compro VideoMate U650F", NULL) },
- 	{ DVB_USB_DEVICE(USB_VID_KWORLD_2, 0xd394,
- 		&rtl28xxu_props, "MaxMedia HU394-T", NULL) },
-+	{ DVB_USB_DEVICE(USB_VID_GTEK, 0xb803 /*USB_PID_AUGUST_DVBT205*/,
-+		&rtl28xxu_props, "August DVB-T 205", NULL) },
-+	{ DVB_USB_DEVICE(USB_VID_GTEK, 0xa803 /*USB_PID_AUGUST_DVBT205*/,
-+		&rtl28xxu_props, "August DVB-T 205", NULL) },
- 	{ DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a03,
- 		&rtl28xxu_props, "Leadtek WinFast DTV Dongle mini", NULL) },
- 	{ DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A,
diff --git a/target/linux/brcm2708/patches-4.14/950-0060-rpi-ft5406-Add-touchscreen-driver-for-pi-LCD-display.patch b/target/linux/brcm2708/patches-4.14/950-0060-rpi-ft5406-Add-touchscreen-driver-for-pi-LCD-display.patch
deleted file mode 100644
index 799a384db..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0060-rpi-ft5406-Add-touchscreen-driver-for-pi-LCD-display.patch
+++ /dev/null
@@ -1,340 +0,0 @@
-From 0a9850b65c2ad0183684790cb6fefb2f59eca573 Mon Sep 17 00:00:00 2001
-From: Gordon Hollingworth <gordon@raspberrypi.org>
-Date: Tue, 12 May 2015 14:47:56 +0100
-Subject: [PATCH 060/454] rpi-ft5406: Add touchscreen driver for pi LCD display
-
-Fix driver detection failure Check that the buffer response is non-zero meaning the touchscreen was detected
-
-rpi-ft5406: Use firmware API
-
-RPI-FT5406: Enable aarch64 support through explicit iomem interface
-
-Signed-off-by: Gerhard de Clercq <gerharddeclercq@outlook.com>
----
- drivers/input/touchscreen/Kconfig      |   7 +
- drivers/input/touchscreen/Makefile     |   1 +
- drivers/input/touchscreen/rpi-ft5406.c | 292 +++++++++++++++++++++++++
- 3 files changed, 300 insertions(+)
- create mode 100644 drivers/input/touchscreen/rpi-ft5406.c
-
---- a/drivers/input/touchscreen/Kconfig
-+++ b/drivers/input/touchscreen/Kconfig
-@@ -628,6 +628,13 @@ config TOUCHSCREEN_EDT_FT5X06
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called edt-ft5x06.
- 
-+config TOUCHSCREEN_RPI_FT5406
-+	tristate "Raspberry Pi FT5406 driver"
-+	depends on RASPBERRYPI_FIRMWARE
-+	help
-+	  Say Y here to enable the Raspberry Pi memory based FT5406 device
-+
-+
- config TOUCHSCREEN_MIGOR
- 	tristate "Renesas MIGO-R touchscreen"
- 	depends on (SH_MIGOR || COMPILE_TEST) && I2C
---- a/drivers/input/touchscreen/Makefile
-+++ b/drivers/input/touchscreen/Makefile
-@@ -30,6 +30,7 @@ obj-$(CONFIG_TOUCHSCREEN_DA9034)	+= da90
- obj-$(CONFIG_TOUCHSCREEN_DA9052)	+= da9052_tsi.o
- obj-$(CONFIG_TOUCHSCREEN_DYNAPRO)	+= dynapro.o
- obj-$(CONFIG_TOUCHSCREEN_EDT_FT5X06)	+= edt-ft5x06.o
-+obj-$(CONFIG_TOUCHSCREEN_RPI_FT5406)	+= rpi-ft5406.o
- obj-$(CONFIG_TOUCHSCREEN_HAMPSHIRE)	+= hampshire.o
- obj-$(CONFIG_TOUCHSCREEN_GUNZE)		+= gunze.o
- obj-$(CONFIG_TOUCHSCREEN_EETI)		+= eeti_ts.o
---- /dev/null
-+++ b/drivers/input/touchscreen/rpi-ft5406.c
-@@ -0,0 +1,292 @@
-+/*
-+ * Driver for memory based ft5406 touchscreen
-+ *
-+ * Copyright (C) 2015 Raspberry Pi
-+ *
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+
-+#include <linux/module.h>
-+#include <linux/interrupt.h>
-+#include <linux/input.h>
-+#include <linux/irq.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+#include <linux/bitops.h>
-+#include <linux/input/mt.h>
-+#include <linux/kthread.h>
-+#include <linux/platform_device.h>
-+#include <linux/stddef.h>
-+#include <asm/io.h>
-+#include <linux/dma-mapping.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+#define MAXIMUM_SUPPORTED_POINTS 10
-+struct ft5406_regs {
-+	uint8_t device_mode;
-+	uint8_t gesture_id;
-+	uint8_t num_points;
-+	struct ft5406_touch {
-+		uint8_t xh;
-+		uint8_t xl;
-+		uint8_t yh;
-+		uint8_t yl;
-+		uint8_t res1;
-+		uint8_t res2;
-+	} point[MAXIMUM_SUPPORTED_POINTS];
-+};
-+
-+#define SCREEN_WIDTH  800
-+#define SCREEN_HEIGHT 480
-+
-+struct ft5406 {
-+	struct platform_device * pdev;
-+	struct input_dev       * input_dev;
-+	void __iomem           * ts_base;
-+	dma_addr_t		 bus_addr;
-+	struct task_struct     * thread;
-+};
-+
-+/* Thread to poll for touchscreen events
-+ * 
-+ * This thread polls the memory based register copy of the ft5406 registers
-+ * using the number of points register to know whether the copy has been
-+ * updated (we write 99 to the memory copy, the GPU will write between 
-+ * 0 - 10 points)
-+ */
-+static int ft5406_thread(void *arg)
-+{
-+	struct ft5406 *ts = (struct ft5406 *) arg;
-+	struct ft5406_regs regs;
-+	int known_ids = 0;
-+	
-+	while(!kthread_should_stop())
-+	{
-+		// 60fps polling
-+		msleep_interruptible(17);
-+		memcpy_fromio(&regs, ts->ts_base, sizeof(struct ft5406_regs));
-+		iowrite8(99, ts->ts_base + offsetof(struct ft5406_regs, num_points));
-+		// Do not output if theres no new information (num_points is 99)
-+		// or we have no touch points and don't need to release any
-+		if(!(regs.num_points == 99 || (regs.num_points == 0 && known_ids == 0)))
-+		{
-+			int i;
-+			int modified_ids = 0, released_ids;
-+			for(i = 0; i < regs.num_points; i++)
-+			{
-+				int x = (((int) regs.point[i].xh & 0xf) << 8) + regs.point[i].xl;
-+				int y = (((int) regs.point[i].yh & 0xf) << 8) + regs.point[i].yl;
-+				int touchid = (regs.point[i].yh >> 4) & 0xf;
-+				
-+				modified_ids |= 1 << touchid;
-+
-+				if(!((1 << touchid) & known_ids))
-+					dev_dbg(&ts->pdev->dev, "x = %d, y = %d, touchid = %d\n", x, y, touchid);
-+				
-+				input_mt_slot(ts->input_dev, touchid);
-+				input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 1);
-+
-+				input_report_abs(ts->input_dev, ABS_MT_POSITION_X, x);
-+				input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, y);
-+
-+			}
-+
-+			released_ids = known_ids & ~modified_ids;
-+			for(i = 0; released_ids && i < MAXIMUM_SUPPORTED_POINTS; i++)
-+			{
-+				if(released_ids & (1<<i))
-+				{
-+					dev_dbg(&ts->pdev->dev, "Released %d, known = %x modified = %x\n", i, known_ids, modified_ids);
-+					input_mt_slot(ts->input_dev, i);
-+					input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 0);
-+					modified_ids &= ~(1 << i);
-+				}
-+			}
-+			known_ids = modified_ids;
-+			
-+			input_mt_report_pointer_emulation(ts->input_dev, true);
-+			input_sync(ts->input_dev);
-+		}
-+			
-+	}
-+	
-+	return 0;
-+}
-+
-+static int ft5406_probe(struct platform_device *pdev)
-+{
-+	int err = 0;
-+	struct device *dev = &pdev->dev;
-+	struct device_node *np = dev->of_node;
-+	struct ft5406 * ts;
-+	struct device_node *fw_node;
-+	struct rpi_firmware *fw;
-+	u32 touchbuf;
-+	
-+	dev_info(dev, "Probing device\n");
-+	
-+	fw_node = of_parse_phandle(np, "firmware", 0);
-+	if (!fw_node) {
-+		dev_err(dev, "Missing firmware node\n");
-+		return -ENOENT;
-+	}
-+
-+	fw = rpi_firmware_get(fw_node);
-+	if (!fw)
-+		return -EPROBE_DEFER;
-+
-+	ts = devm_kzalloc(dev, sizeof(struct ft5406), GFP_KERNEL);
-+	if (!ts) {
-+		dev_err(dev, "Failed to allocate memory\n");
-+		return -ENOMEM;
-+	}
-+
-+	ts->input_dev = input_allocate_device();
-+	if (!ts->input_dev) {
-+		dev_err(dev, "Failed to allocate input device\n");
-+		return -ENOMEM;
-+	}
-+
-+	ts->ts_base = dma_zalloc_coherent(dev, PAGE_SIZE, &ts->bus_addr, GFP_KERNEL);
-+	if (!ts->ts_base) {
-+		pr_err("[%s]: failed to dma_alloc_coherent(%ld)\n",
-+				__func__, PAGE_SIZE);
-+		err = -ENOMEM;
-+		goto out;
-+	}
-+
-+	touchbuf = (u32)ts->bus_addr;
-+	err = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_SET_TOUCHBUF,
-+				    &touchbuf, sizeof(touchbuf));
-+
-+	if (err || touchbuf != 0) {
-+		dev_warn(dev, "Failed to set touchbuf, trying to get err:%x\n", err);
-+		dma_free_coherent(dev, PAGE_SIZE, ts->ts_base, ts->bus_addr);
-+		ts->ts_base = 0;
-+		ts->bus_addr = 0;
-+	}
-+
-+	if (!ts->ts_base) {
-+		dev_warn(dev, "set failed, trying get (err:%d touchbuf:%x virt:%p bus:%x)\n", err, touchbuf, ts->ts_base, ts->bus_addr);
-+
-+		err = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF,
-+				    &touchbuf, sizeof(touchbuf));
-+		if (err) {
-+			dev_err(dev, "Failed to get touch buffer\n");
-+			goto out;
-+		}
-+
-+		if (!touchbuf) {
-+			dev_err(dev, "Touchscreen not detected\n");
-+			err = -ENODEV;
-+			goto out;
-+		}
-+
-+		dev_dbg(dev, "Got TS buffer 0x%x\n", touchbuf);
-+
-+		// mmap the physical memory
-+		touchbuf &= ~0xc0000000;
-+		ts->ts_base = ioremap(touchbuf, sizeof(struct ft5406_regs));
-+		if (ts->ts_base == NULL)
-+		{
-+			dev_err(dev, "Failed to map physical address\n");
-+			err = -ENOMEM;
-+			goto out;
-+		}
-+	}
-+	platform_set_drvdata(pdev, ts);
-+	ts->pdev = pdev;
-+	
-+	ts->input_dev->name = "FT5406 memory based driver";
-+	
-+	__set_bit(EV_KEY, ts->input_dev->evbit);
-+	__set_bit(EV_SYN, ts->input_dev->evbit);
-+	__set_bit(EV_ABS, ts->input_dev->evbit);
-+
-+	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_X, 0,
-+			     SCREEN_WIDTH, 0, 0);
-+	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_Y, 0,
-+			     SCREEN_HEIGHT, 0, 0);
-+
-+	input_mt_init_slots(ts->input_dev, MAXIMUM_SUPPORTED_POINTS, INPUT_MT_DIRECT);
-+
-+	input_set_drvdata(ts->input_dev, ts);
-+	
-+	err = input_register_device(ts->input_dev);
-+	if (err) {
-+		dev_err(dev, "could not register input device, %d\n",
-+			err);
-+		goto out;
-+	}
-+
-+	// create thread to poll the touch events
-+	ts->thread = kthread_run(ft5406_thread, ts, "ft5406");
-+	if(ts->thread == NULL)
-+	{
-+		dev_err(dev, "Failed to create kernel thread");
-+		err = -ENOMEM;
-+		goto out;
-+	}
-+
-+	return 0;
-+
-+out:
-+	if (ts->bus_addr) {
-+		dma_free_coherent(dev, PAGE_SIZE, ts->ts_base, ts->bus_addr);
-+		ts->bus_addr = 0;
-+		ts->ts_base = NULL;
-+	} else if (ts->ts_base) {
-+		iounmap(ts->ts_base);
-+		ts->ts_base = NULL;
-+	}
-+	if (ts->input_dev) {
-+		input_unregister_device(ts->input_dev);
-+		ts->input_dev = NULL;
-+	}
-+	return err;
-+}
-+
-+static int ft5406_remove(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct ft5406 *ts = (struct ft5406 *) platform_get_drvdata(pdev);
-+	
-+	dev_info(dev, "Removing rpi-ft5406\n");
-+	
-+	kthread_stop(ts->thread);
-+
-+	if (ts->bus_addr)
-+		dma_free_coherent(dev, PAGE_SIZE, ts->ts_base, ts->bus_addr);
-+	else if (ts->ts_base)
-+		iounmap(ts->ts_base);
-+	if (ts->input_dev)
-+		input_unregister_device(ts->input_dev);
-+	
-+	return 0;
-+}
-+
-+static const struct of_device_id ft5406_match[] = {
-+	{ .compatible = "rpi,rpi-ft5406", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, ft5406_match);
-+
-+static struct platform_driver ft5406_driver = {
-+	.driver = {
-+		.name   = "rpi-ft5406",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = ft5406_match,
-+	},
-+	.probe          = ft5406_probe,
-+	.remove         = ft5406_remove,
-+};
-+
-+module_platform_driver(ft5406_driver);
-+
-+MODULE_AUTHOR("Gordon Hollingworth");
-+MODULE_DESCRIPTION("Touchscreen driver for memory based FT5406");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/brcm2708/patches-4.14/950-0061-Improve-__copy_to_user-and-__copy_from_user-performa.patch b/target/linux/brcm2708/patches-4.14/950-0061-Improve-__copy_to_user-and-__copy_from_user-performa.patch
deleted file mode 100644
index 924fef4cb..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0061-Improve-__copy_to_user-and-__copy_from_user-performa.patch
+++ /dev/null
@@ -1,1552 +0,0 @@
-From 7e9af733a0be196ed305ec367ea18c13525feb81 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Mon, 28 Nov 2016 16:50:04 +0000
-Subject: [PATCH 061/454] Improve __copy_to_user and __copy_from_user
- performance
-
-Provide a __copy_from_user that uses memcpy. On BCM2708, use
-optimised memcpy/memmove/memcmp/memset implementations.
-
-arch/arm: Add mmiocpy/set aliases for memcpy/set
-
-See: https://github.com/raspberrypi/linux/issues/1082
-
-copy_from_user: CPU_SW_DOMAIN_PAN compatibility
-
-The downstream copy_from_user acceleration must also play nice with
-CONFIG_CPU_SW_DOMAIN_PAN.
-
-See: https://github.com/raspberrypi/linux/issues/1381
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/include/asm/string.h      |   5 +
- arch/arm/include/asm/uaccess.h     |   3 +
- arch/arm/lib/Makefile              |  15 +-
- arch/arm/lib/arm-mem.h             | 159 +++++++++
- arch/arm/lib/copy_from_user.S      |   4 +-
- arch/arm/lib/exports_rpi.c         |  37 +++
- arch/arm/lib/memcmp_rpi.S          | 285 ++++++++++++++++
- arch/arm/lib/memcpy_rpi.S          |  61 ++++
- arch/arm/lib/memcpymove.h          | 506 +++++++++++++++++++++++++++++
- arch/arm/lib/memmove_rpi.S         |  61 ++++
- arch/arm/lib/memset_rpi.S          | 128 ++++++++
- arch/arm/lib/uaccess_with_memcpy.c | 120 ++++++-
- arch/arm/mach-bcm/Kconfig          |   7 +
- 13 files changed, 1385 insertions(+), 6 deletions(-)
- create mode 100644 arch/arm/lib/arm-mem.h
- create mode 100644 arch/arm/lib/exports_rpi.c
- create mode 100644 arch/arm/lib/memcmp_rpi.S
- create mode 100644 arch/arm/lib/memcpy_rpi.S
- create mode 100644 arch/arm/lib/memcpymove.h
- create mode 100644 arch/arm/lib/memmove_rpi.S
- create mode 100644 arch/arm/lib/memset_rpi.S
-
---- a/arch/arm/include/asm/string.h
-+++ b/arch/arm/include/asm/string.h
-@@ -39,6 +39,11 @@ static inline void *memset64(uint64_t *p
- 	return __memset64(p, v, n * 8, v >> 32);
- }
- 
-+#ifdef CONFIG_BCM2835_FAST_MEMCPY
-+#define __HAVE_ARCH_MEMCMP
-+extern int memcmp(const void *, const void *, size_t);
-+#endif
-+
- extern void __memzero(void *ptr, __kernel_size_t n);
- 
- #define memset(p,v,n)							\
---- a/arch/arm/include/asm/uaccess.h
-+++ b/arch/arm/include/asm/uaccess.h
-@@ -459,6 +459,9 @@ do {									\
- extern unsigned long __must_check
- arm_copy_from_user(void *to, const void __user *from, unsigned long n);
- 
-+extern unsigned long __must_check
-+__copy_from_user_std(void *to, const void __user *from, unsigned long n);
-+
- static inline unsigned long __must_check
- raw_copy_from_user(void *to, const void __user *from, unsigned long n)
- {
---- a/arch/arm/lib/Makefile
-+++ b/arch/arm/lib/Makefile
-@@ -7,9 +7,8 @@
- 
- lib-y		:= backtrace.o changebit.o csumipv6.o csumpartial.o   \
- 		   csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
--		   delay.o delay-loop.o findbit.o memchr.o memcpy.o   \
--		   memmove.o memset.o memzero.o setbit.o              \
--		   strchr.o strrchr.o                                 \
-+		   delay.o delay-loop.o findbit.o memchr.o memzero.o  \
-+		   setbit.o strchr.o strrchr.o                        \
- 		   testchangebit.o testclearbit.o testsetbit.o        \
- 		   ashldi3.o ashrdi3.o lshrdi3.o muldi3.o             \
- 		   ucmpdi2.o lib1funcs.o div64.o                      \
-@@ -19,6 +18,16 @@ lib-y		:= backtrace.o changebit.o csumip
- mmu-y		:= clear_user.o copy_page.o getuser.o putuser.o       \
- 		   copy_from_user.o copy_to_user.o
- 
-+# Choose optimised implementations for Raspberry Pi
-+ifeq ($(CONFIG_BCM2835_FAST_MEMCPY),y)
-+  CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600
-+  CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672
-+  obj-$(CONFIG_MODULES) += exports_rpi.o
-+  lib-y        += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o
-+else
-+  lib-y        += memcpy.o memmove.o memset.o
-+endif
-+
- # using lib_ here won't override already available weak symbols
- obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
- 
---- /dev/null
-+++ b/arch/arm/lib/arm-mem.h
-@@ -0,0 +1,159 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+    * Redistributions of source code must retain the above copyright
-+      notice, this list of conditions and the following disclaimer.
-+    * Redistributions in binary form must reproduce the above copyright
-+      notice, this list of conditions and the following disclaimer in the
-+      documentation and/or other materials provided with the distribution.
-+    * Neither the name of the copyright holder nor the
-+      names of its contributors may be used to endorse or promote products
-+      derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+.macro myfunc fname
-+ .func fname
-+ .global fname
-+fname:
-+.endm
-+
-+.macro preload_leading_step1  backwards, ptr, base
-+/* If the destination is already 16-byte aligned, then we need to preload
-+ * between 0 and prefetch_distance (inclusive) cache lines ahead so there
-+ * are no gaps when the inner loop starts.
-+ */
-+ .if backwards
-+        sub     ptr, base, #1
-+        bic     ptr, ptr, #31
-+ .else
-+        bic     ptr, base, #31
-+ .endif
-+ .set OFFSET, 0
-+ .rept prefetch_distance+1
-+        pld     [ptr, #OFFSET]
-+  .if backwards
-+   .set OFFSET, OFFSET-32
-+  .else
-+   .set OFFSET, OFFSET+32
-+  .endif
-+ .endr
-+.endm
-+
-+.macro preload_leading_step2  backwards, ptr, base, leading_bytes, tmp
-+/* However, if the destination is not 16-byte aligned, we may need to
-+ * preload one more cache line than that. The question we need to ask is:
-+ * are the leading bytes more than the amount by which the source
-+ * pointer will be rounded down for preloading, and if so, by how many
-+ * cache lines?
-+ */
-+ .if backwards
-+/* Here we compare against how many bytes we are into the
-+ * cache line, counting down from the highest such address.
-+ * Effectively, we want to calculate
-+ *     leading_bytes = dst&15
-+ *     cacheline_offset = 31-((src-leading_bytes-1)&31)
-+ *     extra_needed = leading_bytes - cacheline_offset
-+ * and test if extra_needed is <= 0, or rearranging:
-+ *     leading_bytes + (src-leading_bytes-1)&31 <= 31
-+ */
-+        mov     tmp, base, lsl #32-5
-+        sbc     tmp, tmp, leading_bytes, lsl #32-5
-+        adds    tmp, tmp, leading_bytes, lsl #32-5
-+        bcc     61f
-+        pld     [ptr, #-32*(prefetch_distance+1)]
-+ .else
-+/* Effectively, we want to calculate
-+ *     leading_bytes = (-dst)&15
-+ *     cacheline_offset = (src+leading_bytes)&31
-+ *     extra_needed = leading_bytes - cacheline_offset
-+ * and test if extra_needed is <= 0.
-+ */
-+        mov     tmp, base, lsl #32-5
-+        add     tmp, tmp, leading_bytes, lsl #32-5
-+        rsbs    tmp, tmp, leading_bytes, lsl #32-5
-+        bls     61f
-+        pld     [ptr, #32*(prefetch_distance+1)]
-+ .endif
-+61:
-+.endm
-+
-+.macro preload_trailing  backwards, base, remain, tmp
-+        /* We need either 0, 1 or 2 extra preloads */
-+ .if backwards
-+        rsb     tmp, base, #0
-+        mov     tmp, tmp, lsl #32-5
-+ .else
-+        mov     tmp, base, lsl #32-5
-+ .endif
-+        adds    tmp, tmp, remain, lsl #32-5
-+        adceqs  tmp, tmp, #0
-+        /* The instruction above has two effects: ensures Z is only
-+         * set if C was clear (so Z indicates that both shifted quantities
-+         * were 0), and clears C if Z was set (so C indicates that the sum
-+         * of the shifted quantities was greater and not equal to 32) */
-+        beq     82f
-+ .if backwards
-+        sub     tmp, base, #1
-+        bic     tmp, tmp, #31
-+ .else
-+        bic     tmp, base, #31
-+ .endif
-+        bcc     81f
-+ .if backwards
-+        pld     [tmp, #-32*(prefetch_distance+1)]
-+81:
-+        pld     [tmp, #-32*prefetch_distance]
-+ .else
-+        pld     [tmp, #32*(prefetch_distance+2)]
-+81:
-+        pld     [tmp, #32*(prefetch_distance+1)]
-+ .endif
-+82:
-+.endm
-+
-+.macro preload_all    backwards, narrow_case, shift, base, remain, tmp0, tmp1
-+ .if backwards
-+        sub     tmp0, base, #1
-+        bic     tmp0, tmp0, #31
-+        pld     [tmp0]
-+        sub     tmp1, base, remain, lsl #shift
-+ .else
-+        bic     tmp0, base, #31
-+        pld     [tmp0]
-+        add     tmp1, base, remain, lsl #shift
-+        sub     tmp1, tmp1, #1
-+ .endif
-+        bic     tmp1, tmp1, #31
-+        cmp     tmp1, tmp0
-+        beq     92f
-+ .if narrow_case
-+        /* In this case, all the data fits in either 1 or 2 cache lines */
-+        pld     [tmp1]
-+ .else
-+91:
-+  .if backwards
-+        sub     tmp0, tmp0, #32
-+  .else
-+        add     tmp0, tmp0, #32
-+  .endif
-+        cmp     tmp0, tmp1
-+        pld     [tmp0]
-+        bne     91b
-+ .endif
-+92:
-+.endm
---- a/arch/arm/lib/copy_from_user.S
-+++ b/arch/arm/lib/copy_from_user.S
-@@ -89,7 +89,8 @@
- 
- 	.text
- 
--ENTRY(arm_copy_from_user)
-+ENTRY(__copy_from_user_std)
-+WEAK(arm_copy_from_user)
- #ifdef CONFIG_CPU_SPECTRE
- 	get_thread_info r3
- 	ldr	r3, [r3, #TI_ADDR_LIMIT]
-@@ -103,6 +104,7 @@ ENTRY(arm_copy_from_user)
- #include "copy_template.S"
- 
- ENDPROC(arm_copy_from_user)
-+ENDPROC(__copy_from_user_std)
- 
- 	.pushsection .fixup,"ax"
- 	.align 0
---- /dev/null
-+++ b/arch/arm/lib/exports_rpi.c
-@@ -0,0 +1,37 @@
-+/**
-+ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+
-+EXPORT_SYMBOL(memcmp);
---- /dev/null
-+++ b/arch/arm/lib/memcmp_rpi.S
-@@ -0,0 +1,285 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+    * Redistributions of source code must retain the above copyright
-+      notice, this list of conditions and the following disclaimer.
-+    * Redistributions in binary form must reproduce the above copyright
-+      notice, this list of conditions and the following disclaimer in the
-+      documentation and/or other materials provided with the distribution.
-+    * Neither the name of the copyright holder nor the
-+      names of its contributors may be used to endorse or promote products
-+      derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+    .text
-+    .arch armv6
-+    .object_arch armv4
-+    .arm
-+    .altmacro
-+    .p2align 2
-+
-+.macro memcmp_process_head  unaligned
-+ .if unaligned
-+        ldr     DAT0, [S_1], #4
-+        ldr     DAT1, [S_1], #4
-+        ldr     DAT2, [S_1], #4
-+        ldr     DAT3, [S_1], #4
-+ .else
-+        ldmia   S_1!, {DAT0, DAT1, DAT2, DAT3}
-+ .endif
-+        ldmia   S_2!, {DAT4, DAT5, DAT6, DAT7}
-+.endm
-+
-+.macro memcmp_process_tail
-+        cmp     DAT0, DAT4
-+        cmpeq   DAT1, DAT5
-+        cmpeq   DAT2, DAT6
-+        cmpeq   DAT3, DAT7
-+        bne     200f
-+.endm
-+
-+.macro memcmp_leading_31bytes
-+        movs    DAT0, OFF, lsl #31
-+        ldrmib  DAT0, [S_1], #1
-+        ldrcsh  DAT1, [S_1], #2
-+        ldrmib  DAT4, [S_2], #1
-+        ldrcsh  DAT5, [S_2], #2
-+        movpl   DAT0, #0
-+        movcc   DAT1, #0
-+        movpl   DAT4, #0
-+        movcc   DAT5, #0
-+        submi   N, N, #1
-+        subcs   N, N, #2
-+        cmp     DAT0, DAT4
-+        cmpeq   DAT1, DAT5
-+        bne     200f
-+        movs    DAT0, OFF, lsl #29
-+        ldrmi   DAT0, [S_1], #4
-+        ldrcs   DAT1, [S_1], #4
-+        ldrcs   DAT2, [S_1], #4
-+        ldrmi   DAT4, [S_2], #4
-+        ldmcsia S_2!, {DAT5, DAT6}
-+        movpl   DAT0, #0
-+        movcc   DAT1, #0
-+        movcc   DAT2, #0
-+        movpl   DAT4, #0
-+        movcc   DAT5, #0
-+        movcc   DAT6, #0
-+        submi   N, N, #4
-+        subcs   N, N, #8
-+        cmp     DAT0, DAT4
-+        cmpeq   DAT1, DAT5
-+        cmpeq   DAT2, DAT6
-+        bne     200f
-+        tst     OFF, #16
-+        beq     105f
-+        memcmp_process_head  1
-+        sub     N, N, #16
-+        memcmp_process_tail
-+105:
-+.endm
-+
-+.macro memcmp_trailing_15bytes  unaligned
-+        movs    N, N, lsl #29
-+ .if unaligned
-+        ldrcs   DAT0, [S_1], #4
-+        ldrcs   DAT1, [S_1], #4
-+ .else
-+        ldmcsia S_1!, {DAT0, DAT1}
-+ .endif
-+        ldrmi   DAT2, [S_1], #4
-+        ldmcsia S_2!, {DAT4, DAT5}
-+        ldrmi   DAT6, [S_2], #4
-+        movcc   DAT0, #0
-+        movcc   DAT1, #0
-+        movpl   DAT2, #0
-+        movcc   DAT4, #0
-+        movcc   DAT5, #0
-+        movpl   DAT6, #0
-+        cmp     DAT0, DAT4
-+        cmpeq   DAT1, DAT5
-+        cmpeq   DAT2, DAT6
-+        bne     200f
-+        movs    N, N, lsl #2
-+        ldrcsh  DAT0, [S_1], #2
-+        ldrmib  DAT1, [S_1]
-+        ldrcsh  DAT4, [S_2], #2
-+        ldrmib  DAT5, [S_2]
-+        movcc   DAT0, #0
-+        movpl   DAT1, #0
-+        movcc   DAT4, #0
-+        movpl   DAT5, #0
-+        cmp     DAT0, DAT4
-+        cmpeq   DAT1, DAT5
-+        bne     200f
-+.endm
-+
-+.macro memcmp_long_inner_loop  unaligned
-+110:
-+        memcmp_process_head  unaligned
-+        pld     [S_2, #prefetch_distance*32 + 16]
-+        memcmp_process_tail
-+        memcmp_process_head  unaligned
-+        pld     [S_1, OFF]
-+        memcmp_process_tail
-+        subs    N, N, #32
-+        bhs     110b
-+        /* Just before the final (prefetch_distance+1) 32-byte blocks,
-+         * deal with final preloads */
-+        preload_trailing  0, S_1, N, DAT0
-+        preload_trailing  0, S_2, N, DAT0
-+        add     N, N, #(prefetch_distance+2)*32 - 16
-+120:
-+        memcmp_process_head  unaligned
-+        memcmp_process_tail
-+        subs    N, N, #16
-+        bhs     120b
-+        /* Trailing words and bytes */
-+        tst     N, #15
-+        beq     199f
-+        memcmp_trailing_15bytes  unaligned
-+199:    /* Reached end without detecting a difference */
-+        mov     a1, #0
-+        setend  le
-+        pop     {DAT1-DAT6, pc}
-+.endm
-+
-+.macro memcmp_short_inner_loop  unaligned
-+        subs    N, N, #16     /* simplifies inner loop termination */
-+        blo     122f
-+120:
-+        memcmp_process_head  unaligned
-+        memcmp_process_tail
-+        subs    N, N, #16
-+        bhs     120b
-+122:    /* Trailing words and bytes */
-+        tst     N, #15
-+        beq     199f
-+        memcmp_trailing_15bytes  unaligned
-+199:    /* Reached end without detecting a difference */
-+        mov     a1, #0
-+        setend  le
-+        pop     {DAT1-DAT6, pc}
-+.endm
-+
-+/*
-+ * int memcmp(const void *s1, const void *s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to buffer 1
-+ * a2 = pointer to buffer 2
-+ * a3 = number of bytes to compare (as unsigned chars)
-+ * On exit:
-+ * a1 = >0/=0/<0 if s1 >/=/< s2
-+ */
-+
-+.set prefetch_distance, 2
-+
-+ENTRY(memcmp)
-+        S_1     .req    a1
-+        S_2     .req    a2
-+        N       .req    a3
-+        DAT0    .req    a4
-+        DAT1    .req    v1
-+        DAT2    .req    v2
-+        DAT3    .req    v3
-+        DAT4    .req    v4
-+        DAT5    .req    v5
-+        DAT6    .req    v6
-+        DAT7    .req    ip
-+        OFF     .req    lr
-+
-+        push    {DAT1-DAT6, lr}
-+        setend  be /* lowest-addressed bytes are most significant */
-+
-+        /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */
-+        cmp     N, #(prefetch_distance+3)*32 - 1
-+        blo     170f
-+
-+        /* Long case */
-+        /* Adjust N so that the decrement instruction can also test for
-+         * inner loop termination. We want it to stop when there are
-+         * (prefetch_distance+1) complete blocks to go. */
-+        sub     N, N, #(prefetch_distance+2)*32
-+        preload_leading_step1  0, DAT0, S_1
-+        preload_leading_step1  0, DAT1, S_2
-+        tst     S_2, #31
-+        beq     154f
-+        rsb     OFF, S_2, #0 /* no need to AND with 15 here */
-+        preload_leading_step2  0, DAT0, S_1, OFF, DAT2
-+        preload_leading_step2  0, DAT1, S_2, OFF, DAT2
-+        memcmp_leading_31bytes
-+154:    /* Second source now cacheline (32-byte) aligned; we have at
-+         * least one prefetch to go. */
-+        /* Prefetch offset is best selected such that it lies in the
-+         * first 8 of each 32 bytes - but it's just as easy to aim for
-+         * the first one */
-+        and     OFF, S_1, #31
-+        rsb     OFF, OFF, #32*prefetch_distance
-+        tst     S_1, #3
-+        bne     140f
-+        memcmp_long_inner_loop  0
-+140:    memcmp_long_inner_loop  1
-+
-+170:    /* Short case */
-+        teq     N, #0
-+        beq     199f
-+        preload_all 0, 0, 0, S_1, N, DAT0, DAT1
-+        preload_all 0, 0, 0, S_2, N, DAT0, DAT1
-+        tst     S_2, #3
-+        beq     174f
-+172:    subs    N, N, #1
-+        blo     199f
-+        ldrb    DAT0, [S_1], #1
-+        ldrb    DAT4, [S_2], #1
-+        cmp     DAT0, DAT4
-+        bne     200f
-+        tst     S_2, #3
-+        bne     172b
-+174:    /* Second source now 4-byte aligned; we have 0 or more bytes to go */
-+        tst     S_1, #3
-+        bne     140f
-+        memcmp_short_inner_loop  0
-+140:    memcmp_short_inner_loop  1
-+
-+200:    /* Difference found: determine sign. */
-+        movhi   a1, #1
-+        movlo   a1, #-1
-+        setend  le
-+        pop     {DAT1-DAT6, pc}
-+
-+        .unreq  S_1
-+        .unreq  S_2
-+        .unreq  N
-+        .unreq  DAT0
-+        .unreq  DAT1
-+        .unreq  DAT2
-+        .unreq  DAT3
-+        .unreq  DAT4
-+        .unreq  DAT5
-+        .unreq  DAT6
-+        .unreq  DAT7
-+        .unreq  OFF
-+ENDPROC(memcmp)
---- /dev/null
-+++ b/arch/arm/lib/memcpy_rpi.S
-@@ -0,0 +1,61 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+    * Redistributions of source code must retain the above copyright
-+      notice, this list of conditions and the following disclaimer.
-+    * Redistributions in binary form must reproduce the above copyright
-+      notice, this list of conditions and the following disclaimer in the
-+      documentation and/or other materials provided with the distribution.
-+    * Neither the name of the copyright holder nor the
-+      names of its contributors may be used to endorse or promote products
-+      derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+#include "memcpymove.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+    .text
-+    .arch armv6
-+    .object_arch armv4
-+    .arm
-+    .altmacro
-+    .p2align 2
-+
-+/*
-+ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to destination
-+ * a2 = pointer to source
-+ * a3 = number of bytes to copy
-+ * On exit:
-+ * a1 preserved
-+ */
-+
-+.set prefetch_distance, 3
-+
-+ENTRY(mmiocpy)
-+ENTRY(memcpy)
-+        memcpy  0
-+ENDPROC(memcpy)
-+ENDPROC(mmiocpy)
---- /dev/null
-+++ b/arch/arm/lib/memcpymove.h
-@@ -0,0 +1,506 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+    * Redistributions of source code must retain the above copyright
-+      notice, this list of conditions and the following disclaimer.
-+    * Redistributions in binary form must reproduce the above copyright
-+      notice, this list of conditions and the following disclaimer in the
-+      documentation and/or other materials provided with the distribution.
-+    * Neither the name of the copyright holder nor the
-+      names of its contributors may be used to endorse or promote products
-+      derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+.macro unaligned_words  backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8
-+ .if words == 1
-+  .if backwards
-+        mov     r1, r0, lsl #32-align*8
-+        ldr     r0, [S, #-4]!
-+        orr     r1, r1, r0, lsr #align*8
-+        str     r1, [D, #-4]!
-+  .else
-+        mov     r0, r1, lsr #align*8
-+        ldr     r1, [S, #4]!
-+        orr     r0, r0, r1, lsl #32-align*8
-+        str     r0, [D], #4
-+  .endif
-+ .elseif words == 2
-+  .if backwards
-+        ldr     r1, [S, #-4]!
-+        mov     r2, r0, lsl #32-align*8
-+        ldr     r0, [S, #-4]!
-+        orr     r2, r2, r1, lsr #align*8
-+        mov     r1, r1, lsl #32-align*8
-+        orr     r1, r1, r0, lsr #align*8
-+        stmdb   D!, {r1, r2}
-+  .else
-+        ldr     r1, [S, #4]!
-+        mov     r0, r2, lsr #align*8
-+        ldr     r2, [S, #4]!
-+        orr     r0, r0, r1, lsl #32-align*8
-+        mov     r1, r1, lsr #align*8
-+        orr     r1, r1, r2, lsl #32-align*8
-+        stmia   D!, {r0, r1}
-+  .endif
-+ .elseif words == 4
-+  .if backwards
-+        ldmdb   S!, {r2, r3}
-+        mov     r4, r0, lsl #32-align*8
-+        ldmdb   S!, {r0, r1}
-+        orr     r4, r4, r3, lsr #align*8
-+        mov     r3, r3, lsl #32-align*8
-+        orr     r3, r3, r2, lsr #align*8
-+        mov     r2, r2, lsl #32-align*8
-+        orr     r2, r2, r1, lsr #align*8
-+        mov     r1, r1, lsl #32-align*8
-+        orr     r1, r1, r0, lsr #align*8
-+        stmdb   D!, {r1, r2, r3, r4}
-+  .else
-+        ldmib   S!, {r1, r2}
-+        mov     r0, r4, lsr #align*8
-+        ldmib   S!, {r3, r4}
-+        orr     r0, r0, r1, lsl #32-align*8
-+        mov     r1, r1, lsr #align*8
-+        orr     r1, r1, r2, lsl #32-align*8
-+        mov     r2, r2, lsr #align*8
-+        orr     r2, r2, r3, lsl #32-align*8
-+        mov     r3, r3, lsr #align*8
-+        orr     r3, r3, r4, lsl #32-align*8
-+        stmia   D!, {r0, r1, r2, r3}
-+  .endif
-+ .elseif words == 8
-+  .if backwards
-+        ldmdb   S!, {r4, r5, r6, r7}
-+        mov     r8, r0, lsl #32-align*8
-+        ldmdb   S!, {r0, r1, r2, r3}
-+   .if use_pld
-+        pld     [S, OFF]
-+   .endif
-+        orr     r8, r8, r7, lsr #align*8
-+        mov     r7, r7, lsl #32-align*8
-+        orr     r7, r7, r6, lsr #align*8
-+        mov     r6, r6, lsl #32-align*8
-+        orr     r6, r6, r5, lsr #align*8
-+        mov     r5, r5, lsl #32-align*8
-+        orr     r5, r5, r4, lsr #align*8
-+        mov     r4, r4, lsl #32-align*8
-+        orr     r4, r4, r3, lsr #align*8
-+        mov     r3, r3, lsl #32-align*8
-+        orr     r3, r3, r2, lsr #align*8
-+        mov     r2, r2, lsl #32-align*8
-+        orr     r2, r2, r1, lsr #align*8
-+        mov     r1, r1, lsl #32-align*8
-+        orr     r1, r1, r0, lsr #align*8
-+        stmdb   D!, {r5, r6, r7, r8}
-+        stmdb   D!, {r1, r2, r3, r4}
-+  .else
-+        ldmib   S!, {r1, r2, r3, r4}
-+        mov     r0, r8, lsr #align*8
-+        ldmib   S!, {r5, r6, r7, r8}
-+   .if use_pld
-+        pld     [S, OFF]
-+   .endif
-+        orr     r0, r0, r1, lsl #32-align*8
-+        mov     r1, r1, lsr #align*8
-+        orr     r1, r1, r2, lsl #32-align*8
-+        mov     r2, r2, lsr #align*8
-+        orr     r2, r2, r3, lsl #32-align*8
-+        mov     r3, r3, lsr #align*8
-+        orr     r3, r3, r4, lsl #32-align*8
-+        mov     r4, r4, lsr #align*8
-+        orr     r4, r4, r5, lsl #32-align*8
-+        mov     r5, r5, lsr #align*8
-+        orr     r5, r5, r6, lsl #32-align*8
-+        mov     r6, r6, lsr #align*8
-+        orr     r6, r6, r7, lsl #32-align*8
-+        mov     r7, r7, lsr #align*8
-+        orr     r7, r7, r8, lsl #32-align*8
-+        stmia   D!, {r0, r1, r2, r3}
-+        stmia   D!, {r4, r5, r6, r7}
-+  .endif
-+ .endif
-+.endm
-+
-+.macro memcpy_leading_15bytes  backwards, align
-+        movs    DAT1, DAT2, lsl #31
-+        sub     N, N, DAT2
-+ .if backwards
-+        ldrmib  DAT0, [S, #-1]!
-+        ldrcsh  DAT1, [S, #-2]!
-+        strmib  DAT0, [D, #-1]!
-+        strcsh  DAT1, [D, #-2]!
-+ .else
-+        ldrmib  DAT0, [S], #1
-+        ldrcsh  DAT1, [S], #2
-+        strmib  DAT0, [D], #1
-+        strcsh  DAT1, [D], #2
-+ .endif
-+        movs    DAT1, DAT2, lsl #29
-+ .if backwards
-+        ldrmi   DAT0, [S, #-4]!
-+  .if align == 0
-+        ldmcsdb S!, {DAT1, DAT2}
-+  .else
-+        ldrcs   DAT2, [S, #-4]!
-+        ldrcs   DAT1, [S, #-4]!
-+  .endif
-+        strmi   DAT0, [D, #-4]!
-+        stmcsdb D!, {DAT1, DAT2}
-+ .else
-+        ldrmi   DAT0, [S], #4
-+  .if align == 0
-+        ldmcsia S!, {DAT1, DAT2}
-+  .else
-+        ldrcs   DAT1, [S], #4
-+        ldrcs   DAT2, [S], #4
-+  .endif
-+        strmi   DAT0, [D], #4
-+        stmcsia D!, {DAT1, DAT2}
-+ .endif
-+.endm
-+
-+.macro memcpy_trailing_15bytes  backwards, align
-+        movs    N, N, lsl #29
-+ .if backwards
-+  .if align == 0
-+        ldmcsdb S!, {DAT0, DAT1}
-+  .else
-+        ldrcs   DAT1, [S, #-4]!
-+        ldrcs   DAT0, [S, #-4]!
-+  .endif
-+        ldrmi   DAT2, [S, #-4]!
-+        stmcsdb D!, {DAT0, DAT1}
-+        strmi   DAT2, [D, #-4]!
-+ .else
-+  .if align == 0
-+        ldmcsia S!, {DAT0, DAT1}
-+  .else
-+        ldrcs   DAT0, [S], #4
-+        ldrcs   DAT1, [S], #4
-+  .endif
-+        ldrmi   DAT2, [S], #4
-+        stmcsia D!, {DAT0, DAT1}
-+        strmi   DAT2, [D], #4
-+ .endif
-+        movs    N, N, lsl #2
-+ .if backwards
-+        ldrcsh  DAT0, [S, #-2]!
-+        ldrmib  DAT1, [S, #-1]
-+        strcsh  DAT0, [D, #-2]!
-+        strmib  DAT1, [D, #-1]
-+ .else
-+        ldrcsh  DAT0, [S], #2
-+        ldrmib  DAT1, [S]
-+        strcsh  DAT0, [D], #2
-+        strmib  DAT1, [D]
-+ .endif
-+.endm
-+
-+.macro memcpy_long_inner_loop  backwards, align
-+ .if align != 0
-+  .if backwards
-+        ldr     DAT0, [S, #-align]!
-+  .else
-+        ldr     LAST, [S, #-align]!
-+  .endif
-+ .endif
-+110:
-+ .if align == 0
-+  .if backwards
-+        ldmdb   S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+        pld     [S, OFF]
-+        stmdb   D!, {DAT4, DAT5, DAT6, LAST}
-+        stmdb   D!, {DAT0, DAT1, DAT2, DAT3}
-+  .else
-+        ldmia   S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+        pld     [S, OFF]
-+        stmia   D!, {DAT0, DAT1, DAT2, DAT3}
-+        stmia   D!, {DAT4, DAT5, DAT6, LAST}
-+  .endif
-+ .else
-+        unaligned_words  backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST
-+ .endif
-+        subs    N, N, #32
-+        bhs     110b
-+        /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */
-+        preload_trailing  backwards, S, N, OFF
-+        add     N, N, #(prefetch_distance+2)*32 - 32
-+120:
-+ .if align == 0
-+  .if backwards
-+        ldmdb   S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+        stmdb   D!, {DAT4, DAT5, DAT6, LAST}
-+        stmdb   D!, {DAT0, DAT1, DAT2, DAT3}
-+  .else
-+        ldmia   S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}
-+        stmia   D!, {DAT0, DAT1, DAT2, DAT3}
-+        stmia   D!, {DAT4, DAT5, DAT6, LAST}
-+  .endif
-+ .else
-+        unaligned_words  backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST
-+ .endif
-+        subs    N, N, #32
-+        bhs     120b
-+        tst     N, #16
-+ .if align == 0
-+  .if backwards
-+        ldmnedb S!, {DAT0, DAT1, DAT2, LAST}
-+        stmnedb D!, {DAT0, DAT1, DAT2, LAST}
-+  .else
-+        ldmneia S!, {DAT0, DAT1, DAT2, LAST}
-+        stmneia D!, {DAT0, DAT1, DAT2, LAST}
-+  .endif
-+ .else
-+        beq     130f
-+        unaligned_words  backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST
-+130:
-+ .endif
-+        /* Trailing words and bytes */
-+        tst      N, #15
-+        beq      199f
-+ .if align != 0
-+        add     S, S, #align
-+ .endif
-+        memcpy_trailing_15bytes  backwards, align
-+199:
-+        pop     {DAT3, DAT4, DAT5, DAT6, DAT7}
-+        pop     {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy_medium_inner_loop  backwards, align
-+120:
-+ .if backwards
-+  .if align == 0
-+        ldmdb   S!, {DAT0, DAT1, DAT2, LAST}
-+  .else
-+        ldr     LAST, [S, #-4]!
-+        ldr     DAT2, [S, #-4]!
-+        ldr     DAT1, [S, #-4]!
-+        ldr     DAT0, [S, #-4]!
-+  .endif
-+        stmdb   D!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+  .if align == 0
-+        ldmia   S!, {DAT0, DAT1, DAT2, LAST}
-+  .else
-+        ldr     DAT0, [S], #4
-+        ldr     DAT1, [S], #4
-+        ldr     DAT2, [S], #4
-+        ldr     LAST, [S], #4
-+  .endif
-+        stmia   D!, {DAT0, DAT1, DAT2, LAST}
-+ .endif
-+        subs     N, N, #16
-+        bhs      120b
-+        /* Trailing words and bytes */
-+        tst      N, #15
-+        beq      199f
-+        memcpy_trailing_15bytes  backwards, align
-+199:
-+        pop     {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy_short_inner_loop  backwards, align
-+        tst     N, #16
-+ .if backwards
-+  .if align == 0
-+        ldmnedb S!, {DAT0, DAT1, DAT2, LAST}
-+  .else
-+        ldrne   LAST, [S, #-4]!
-+        ldrne   DAT2, [S, #-4]!
-+        ldrne   DAT1, [S, #-4]!
-+        ldrne   DAT0, [S, #-4]!
-+  .endif
-+        stmnedb D!, {DAT0, DAT1, DAT2, LAST}
-+ .else
-+  .if align == 0
-+        ldmneia S!, {DAT0, DAT1, DAT2, LAST}
-+  .else
-+        ldrne   DAT0, [S], #4
-+        ldrne   DAT1, [S], #4
-+        ldrne   DAT2, [S], #4
-+        ldrne   LAST, [S], #4
-+  .endif
-+        stmneia D!, {DAT0, DAT1, DAT2, LAST}
-+ .endif
-+        memcpy_trailing_15bytes  backwards, align
-+199:
-+        pop     {D, DAT1, DAT2, pc}
-+.endm
-+
-+.macro memcpy backwards
-+        D       .req    a1
-+        S       .req    a2
-+        N       .req    a3
-+        DAT0    .req    a4
-+        DAT1    .req    v1
-+        DAT2    .req    v2
-+        DAT3    .req    v3
-+        DAT4    .req    v4
-+        DAT5    .req    v5
-+        DAT6    .req    v6
-+        DAT7    .req    sl
-+        LAST    .req    ip
-+        OFF     .req    lr
-+
-+        .cfi_startproc
-+
-+        push    {D, DAT1, DAT2, lr}
-+
-+        .cfi_def_cfa_offset 16
-+        .cfi_rel_offset D, 0
-+        .cfi_undefined  S
-+        .cfi_undefined  N
-+        .cfi_undefined  DAT0
-+        .cfi_rel_offset DAT1, 4
-+        .cfi_rel_offset DAT2, 8
-+        .cfi_undefined  LAST
-+        .cfi_rel_offset lr, 12
-+
-+ .if backwards
-+        add     D, D, N
-+        add     S, S, N
-+ .endif
-+
-+        /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */
-+        cmp     N, #31
-+        blo     170f
-+        /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */
-+        cmp     N, #(prefetch_distance+3)*32 - 1
-+        blo     160f
-+
-+        /* Long case */
-+        push    {DAT3, DAT4, DAT5, DAT6, DAT7}
-+
-+        .cfi_def_cfa_offset 36
-+        .cfi_rel_offset D, 20
-+        .cfi_rel_offset DAT1, 24
-+        .cfi_rel_offset DAT2, 28
-+        .cfi_rel_offset DAT3, 0
-+        .cfi_rel_offset DAT4, 4
-+        .cfi_rel_offset DAT5, 8
-+        .cfi_rel_offset DAT6, 12
-+        .cfi_rel_offset DAT7, 16
-+        .cfi_rel_offset lr, 32
-+
-+        /* Adjust N so that the decrement instruction can also test for
-+         * inner loop termination. We want it to stop when there are
-+         * (prefetch_distance+1) complete blocks to go. */
-+        sub     N, N, #(prefetch_distance+2)*32
-+        preload_leading_step1  backwards, DAT0, S
-+ .if backwards
-+        /* Bug in GAS: it accepts, but mis-assembles the instruction
-+         * ands    DAT2, D, #60, 2
-+         * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow)
-+         */
-+        .word   0xE210513C
-+        beq     154f
-+ .else
-+        ands    DAT2, D, #15
-+        beq     154f
-+        rsb     DAT2, DAT2, #16 /* number of leading bytes until destination aligned */
-+ .endif
-+        preload_leading_step2  backwards, DAT0, S, DAT2, OFF
-+        memcpy_leading_15bytes backwards, 1
-+154:    /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */
-+        /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */
-+ .if backwards
-+        rsb     OFF, S, #3
-+        and     OFF, OFF, #28
-+        sub     OFF, OFF, #32*(prefetch_distance+1)
-+ .else
-+        and     OFF, S, #28
-+        rsb     OFF, OFF, #32*prefetch_distance
-+ .endif
-+        movs    DAT0, S, lsl #31
-+        bhi     157f
-+        bcs     156f
-+        bmi     155f
-+        memcpy_long_inner_loop  backwards, 0
-+155:    memcpy_long_inner_loop  backwards, 1
-+156:    memcpy_long_inner_loop  backwards, 2
-+157:    memcpy_long_inner_loop  backwards, 3
-+
-+        .cfi_def_cfa_offset 16
-+        .cfi_rel_offset D, 0
-+        .cfi_rel_offset DAT1, 4
-+        .cfi_rel_offset DAT2, 8
-+        .cfi_same_value DAT3
-+        .cfi_same_value DAT4
-+        .cfi_same_value DAT5
-+        .cfi_same_value DAT6
-+        .cfi_same_value DAT7
-+        .cfi_rel_offset lr, 12
-+
-+160:    /* Medium case */
-+        preload_all  backwards, 0, 0, S, N, DAT2, OFF
-+        sub     N, N, #16     /* simplifies inner loop termination */
-+ .if backwards
-+        ands    DAT2, D, #15
-+        beq     164f
-+ .else
-+        ands    DAT2, D, #15
-+        beq     164f
-+        rsb     DAT2, DAT2, #16
-+ .endif
-+        memcpy_leading_15bytes backwards, align
-+164:    /* Destination now 16-byte aligned; we have at least one 16-byte output block */
-+        tst     S, #3
-+        bne     140f
-+        memcpy_medium_inner_loop  backwards, 0
-+140:    memcpy_medium_inner_loop  backwards, 1
-+
-+170:    /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */
-+        teq     N, #0
-+        beq     199f
-+        preload_all  backwards, 1, 0, S, N, DAT2, LAST
-+        tst     D, #3
-+        beq     174f
-+172:    subs    N, N, #1
-+        blo     199f
-+ .if backwards
-+        ldrb    DAT0, [S, #-1]!
-+        strb    DAT0, [D, #-1]!
-+ .else
-+        ldrb    DAT0, [S], #1
-+        strb    DAT0, [D], #1
-+ .endif
-+        tst     D, #3
-+        bne     172b
-+174:    /* Destination now 4-byte aligned; we have 0 or more output bytes to go */
-+        tst     S, #3
-+        bne     140f
-+        memcpy_short_inner_loop  backwards, 0
-+140:    memcpy_short_inner_loop  backwards, 1
-+
-+        .cfi_endproc
-+
-+        .unreq  D
-+        .unreq  S
-+        .unreq  N
-+        .unreq  DAT0
-+        .unreq  DAT1
-+        .unreq  DAT2
-+        .unreq  DAT3
-+        .unreq  DAT4
-+        .unreq  DAT5
-+        .unreq  DAT6
-+        .unreq  DAT7
-+        .unreq  LAST
-+        .unreq  OFF
-+.endm
---- /dev/null
-+++ b/arch/arm/lib/memmove_rpi.S
-@@ -0,0 +1,61 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+    * Redistributions of source code must retain the above copyright
-+      notice, this list of conditions and the following disclaimer.
-+    * Redistributions in binary form must reproduce the above copyright
-+      notice, this list of conditions and the following disclaimer in the
-+      documentation and/or other materials provided with the distribution.
-+    * Neither the name of the copyright holder nor the
-+      names of its contributors may be used to endorse or promote products
-+      derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+#include "memcpymove.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+    .text
-+    .arch armv6
-+    .object_arch armv4
-+    .arm
-+    .altmacro
-+    .p2align 2
-+
-+/*
-+ * void *memmove(void *s1, const void *s2, size_t n);
-+ * On entry:
-+ * a1 = pointer to destination
-+ * a2 = pointer to source
-+ * a3 = number of bytes to copy
-+ * On exit:
-+ * a1 preserved
-+ */
-+
-+.set prefetch_distance, 3
-+
-+ENTRY(memmove)
-+        cmp     a2, a1
-+        bpl     memcpy  /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */
-+        memcpy  1
-+ENDPROC(memmove)
---- /dev/null
-+++ b/arch/arm/lib/memset_rpi.S
-@@ -0,0 +1,128 @@
-+/*
-+Copyright (c) 2013, Raspberry Pi Foundation
-+Copyright (c) 2013, RISC OS Open Ltd
-+All rights reserved.
-+
-+Redistribution and use in source and binary forms, with or without
-+modification, are permitted provided that the following conditions are met:
-+    * Redistributions of source code must retain the above copyright
-+      notice, this list of conditions and the following disclaimer.
-+    * Redistributions in binary form must reproduce the above copyright
-+      notice, this list of conditions and the following disclaimer in the
-+      documentation and/or other materials provided with the distribution.
-+    * Neither the name of the copyright holder nor the
-+      names of its contributors may be used to endorse or promote products
-+      derived from this software without specific prior written permission.
-+
-+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+*/
-+
-+#include <linux/linkage.h>
-+#include "arm-mem.h"
-+
-+/* Prevent the stack from becoming executable */
-+#if defined(__linux__) && defined(__ELF__)
-+.section .note.GNU-stack,"",%progbits
-+#endif
-+
-+    .text
-+    .arch armv6
-+    .object_arch armv4
-+    .arm
-+    .altmacro
-+    .p2align 2
-+
-+/*
-+ *  void *memset(void *s, int c, size_t n);
-+ *  On entry:
-+ *  a1 = pointer to buffer to fill
-+ *  a2 = byte pattern to fill with (caller-narrowed)
-+ *  a3 = number of bytes to fill
-+ *  On exit:
-+ *  a1 preserved
-+ */
-+ENTRY(mmioset)
-+ENTRY(memset)
-+ENTRY(__memset32)
-+ENTRY(__memset64)
-+
-+        S       .req    a1
-+        DAT0    .req    a2
-+        N       .req    a3
-+        DAT1    .req    a4
-+        DAT2    .req    ip
-+        DAT3    .req    lr
-+
-+        orr     DAT0, DAT0, lsl #8
-+        push    {S, lr}
-+        orr     DAT0, DAT0, lsl #16
-+        mov     DAT1, DAT0
-+
-+        /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */
-+        cmp     N, #31
-+        blo     170f
-+
-+161:    sub     N, N, #16     /* simplifies inner loop termination */
-+        /* Leading words and bytes */
-+        tst     S, #15
-+        beq     164f
-+        rsb     DAT3, S, #0   /* bits 0-3 = number of leading bytes until aligned */
-+        movs    DAT2, DAT3, lsl #31
-+        submi   N, N, #1
-+        strmib  DAT0, [S], #1
-+        subcs   N, N, #2
-+        strcsh  DAT0, [S], #2
-+        movs    DAT2, DAT3, lsl #29
-+        submi   N, N, #4
-+        strmi   DAT0, [S], #4
-+        subcs   N, N, #8
-+        stmcsia S!, {DAT0, DAT1}
-+164:    /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */
-+        mov     DAT2, DAT0
-+        mov     DAT3, DAT0
-+        /* Now the inner loop of 16-byte stores */
-+165:    stmia   S!, {DAT0, DAT1, DAT2, DAT3}
-+        subs    N, N, #16
-+        bhs     165b
-+166:    /* Trailing words and bytes */
-+        movs    N, N, lsl #29
-+        stmcsia S!, {DAT0, DAT1}
-+        strmi   DAT0, [S], #4
-+        movs    N, N, lsl #2
-+        strcsh  DAT0, [S], #2
-+        strmib  DAT0, [S]
-+199:    pop     {S, pc}
-+
-+170:    /* Short case */
-+        mov     DAT2, DAT0
-+        mov     DAT3, DAT0
-+        tst     S, #3
-+        beq     174f
-+172:    subs    N, N, #1
-+        blo     199b
-+        strb    DAT0, [S], #1
-+        tst     S, #3
-+        bne     172b
-+174:    tst     N, #16
-+        stmneia S!, {DAT0, DAT1, DAT2, DAT3}
-+        b       166b
-+
-+        .unreq  S
-+        .unreq  DAT0
-+        .unreq  N
-+        .unreq  DAT1
-+        .unreq  DAT2
-+        .unreq  DAT3
-+ENDPROC(__memset64)
-+ENDPROC(__memset32)
-+ENDPROC(memset)
-+ENDPROC(mmioset)
---- a/arch/arm/lib/uaccess_with_memcpy.c
-+++ b/arch/arm/lib/uaccess_with_memcpy.c
-@@ -22,6 +22,14 @@
- #include <asm/current.h>
- #include <asm/page.h>
- 
-+#ifndef COPY_FROM_USER_THRESHOLD
-+#define COPY_FROM_USER_THRESHOLD 64
-+#endif
-+
-+#ifndef COPY_TO_USER_THRESHOLD
-+#define COPY_TO_USER_THRESHOLD 64
-+#endif
-+
- static int
- pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
- {
-@@ -84,7 +92,44 @@ pin_page_for_write(const void __user *_a
- 	return 1;
- }
- 
--static unsigned long noinline
-+static int
-+pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)
-+{
-+	unsigned long addr = (unsigned long)_addr;
-+	pgd_t *pgd;
-+	pmd_t *pmd;
-+	pte_t *pte;
-+	pud_t *pud;
-+	spinlock_t *ptl;
-+
-+	pgd = pgd_offset(current->mm, addr);
-+	if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd)))
-+	{
-+		return 0;
-+	}
-+	pud = pud_offset(pgd, addr);
-+	if (unlikely(pud_none(*pud) || pud_bad(*pud)))
-+	{
-+		return 0;
-+	}
-+
-+	pmd = pmd_offset(pud, addr);
-+	if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd)))
-+		return 0;
-+
-+	pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl);
-+	if (unlikely(!pte_present(*pte) || !pte_young(*pte))) {
-+		pte_unmap_unlock(pte, ptl);
-+		return 0;
-+	}
-+
-+	*ptep = pte;
-+	*ptlp = ptl;
-+
-+	return 1;
-+}
-+
-+unsigned long noinline
- __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n)
- {
- 	unsigned long ua_flags;
-@@ -137,6 +182,57 @@ out:
- 	return n;
- }
- 
-+unsigned long noinline
-+__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n)
-+{
-+	unsigned long ua_flags;
-+	int atomic;
-+
-+	if (unlikely(segment_eq(get_fs(), KERNEL_DS))) {
-+		memcpy(to, (const void *)from, n);
-+		return 0;
-+	}
-+
-+	/* the mmap semaphore is taken only if not in an atomic context */
-+	atomic = in_atomic();
-+
-+	if (!atomic)
-+		down_read(&current->mm->mmap_sem);
-+	while (n) {
-+		pte_t *pte;
-+		spinlock_t *ptl;
-+		int tocopy;
-+
-+		while (!pin_page_for_read(from, &pte, &ptl)) {
-+			char temp;
-+			if (!atomic)
-+				up_read(&current->mm->mmap_sem);
-+			if (__get_user(temp, (char __user *)from))
-+				goto out;
-+			if (!atomic)
-+				down_read(&current->mm->mmap_sem);
-+		}
-+
-+		tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1;
-+		if (tocopy > n)
-+			tocopy = n;
-+
-+		ua_flags = uaccess_save_and_enable();
-+		memcpy(to, (const void *)from, tocopy);
-+		uaccess_restore(ua_flags);
-+		to += tocopy;
-+		from += tocopy;
-+		n -= tocopy;
-+
-+		pte_unmap_unlock(pte, ptl);
-+	}
-+	if (!atomic)
-+		up_read(&current->mm->mmap_sem);
-+
-+out:
-+	return n;
-+}
-+
- unsigned long
- arm_copy_to_user(void __user *to, const void *from, unsigned long n)
- {
-@@ -147,7 +243,7 @@ arm_copy_to_user(void __user *to, const
- 	 * With frame pointer disabled, tail call optimization kicks in
- 	 * as well making this test almost invisible.
- 	 */
--	if (n < 64) {
-+	if (n < COPY_TO_USER_THRESHOLD) {
- 		unsigned long ua_flags = uaccess_save_and_enable();
- 		n = __copy_to_user_std(to, from, n);
- 		uaccess_restore(ua_flags);
-@@ -156,6 +252,26 @@ arm_copy_to_user(void __user *to, const
- 	}
- 	return n;
- }
-+
-+unsigned long __must_check
-+arm_copy_from_user(void *to, const void __user *from, unsigned long n)
-+{
-+	/*
-+	 * This test is stubbed out of the main function above to keep
-+	 * the overhead for small copies low by avoiding a large
-+	 * register dump on the stack just to reload them right away.
-+	 * With frame pointer disabled, tail call optimization kicks in
-+	 * as well making this test almost invisible.
-+	 */
-+	if (n < COPY_TO_USER_THRESHOLD) {
-+		unsigned long ua_flags = uaccess_save_and_enable();
-+		n = __copy_from_user_std(to, from, n);
-+		uaccess_restore(ua_flags);
-+	} else {
-+		n = __copy_from_user_memcpy(to, from, n);
-+	}
-+	return n;
-+}
- 	
- static unsigned long noinline
- __clear_user_memset(void __user *addr, unsigned long n)
---- a/arch/arm/mach-bcm/Kconfig
-+++ b/arch/arm/mach-bcm/Kconfig
-@@ -177,6 +177,13 @@ config ARCH_BCM_53573
- 	  The base chip is BCM53573 and there are some packaging modifications
- 	  like BCM47189 and BCM47452.
- 
-+config BCM2835_FAST_MEMCPY
-+	bool "Enable optimized __copy_to_user and __copy_from_user"
-+	depends on ARCH_BCM2835 && ARCH_MULTI_V6
-+	default y
-+	help
-+	  Optimized versions of __copy_to_user and __copy_from_user for Pi1.
-+
- config ARCH_BCM_63XX
- 	bool "Broadcom BCM63xx DSL SoC"
- 	depends on ARCH_MULTI_V7
diff --git a/target/linux/brcm2708/patches-4.14/950-0062-gpio-poweroff-Allow-it-to-work-on-Raspberry-Pi.patch b/target/linux/brcm2708/patches-4.14/950-0062-gpio-poweroff-Allow-it-to-work-on-Raspberry-Pi.patch
deleted file mode 100644
index cb63ba4aa..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0062-gpio-poweroff-Allow-it-to-work-on-Raspberry-Pi.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From d55078160629e7e13d52332bfcea765bec882f3f Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 25 Jun 2015 12:16:11 +0100
-Subject: [PATCH 062/454] gpio-poweroff: Allow it to work on Raspberry Pi
-
-The Raspberry Pi firmware manages the power-down and reboot
-process. To do this it installs a pm_power_off handler, causing
-the gpio-poweroff module to abort the probe function.
-
-This patch introduces a "force" DT property that overrides that
-behaviour, and also adds a DT overlay to enable and control it.
-
-Note that running in an active-low configuration (DT parameter
-"active_low") requires a custom dt-blob.bin and probably won't
-allow a reboot without switching off, so an external inversion
-of the trigger signal may be preferable.
----
- drivers/power/reset/gpio-poweroff.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/power/reset/gpio-poweroff.c
-+++ b/drivers/power/reset/gpio-poweroff.c
-@@ -49,9 +49,11 @@ static int gpio_poweroff_probe(struct pl
- {
- 	bool input = false;
- 	enum gpiod_flags flags;
-+	bool force = false;
- 
- 	/* If a pm_power_off function has already been added, leave it alone */
--	if (pm_power_off != NULL) {
-+	force = of_property_read_bool(pdev->dev.of_node, "force");
-+	if (!force && (pm_power_off != NULL)) {
- 		dev_err(&pdev->dev,
- 			"%s: pm_power_off function already registered",
- 		       __func__);
diff --git a/target/linux/brcm2708/patches-4.14/950-0063-mfd-Add-Raspberry-Pi-Sense-HAT-core-driver.patch b/target/linux/brcm2708/patches-4.14/950-0063-mfd-Add-Raspberry-Pi-Sense-HAT-core-driver.patch
deleted file mode 100644
index fe5107745..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0063-mfd-Add-Raspberry-Pi-Sense-HAT-core-driver.patch
+++ /dev/null
@@ -1,837 +0,0 @@
-From 4c08dcd53ff11b058b4f6aa55da6a19f7ea03d97 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <pelwell@users.noreply.github.com>
-Date: Tue, 14 Jul 2015 14:32:47 +0100
-Subject: [PATCH 063/454] mfd: Add Raspberry Pi Sense HAT core driver
-
----
- drivers/input/joystick/Kconfig           |   8 +
- drivers/input/joystick/Makefile          |   1 +
- drivers/input/joystick/rpisense-js.c     | 153 ++++++++++++
- drivers/mfd/Kconfig                      |   8 +
- drivers/mfd/Makefile                     |   1 +
- drivers/mfd/rpisense-core.c              | 157 ++++++++++++
- drivers/video/fbdev/Kconfig              |  13 +
- drivers/video/fbdev/Makefile             |   1 +
- drivers/video/fbdev/rpisense-fb.c        | 293 +++++++++++++++++++++++
- include/linux/mfd/rpisense/core.h        |  47 ++++
- include/linux/mfd/rpisense/framebuffer.h |  32 +++
- include/linux/mfd/rpisense/joystick.h    |  35 +++
- 12 files changed, 749 insertions(+)
- create mode 100644 drivers/input/joystick/rpisense-js.c
- create mode 100644 drivers/mfd/rpisense-core.c
- create mode 100644 drivers/video/fbdev/rpisense-fb.c
- create mode 100644 include/linux/mfd/rpisense/core.h
- create mode 100644 include/linux/mfd/rpisense/framebuffer.h
- create mode 100644 include/linux/mfd/rpisense/joystick.h
-
---- a/drivers/input/joystick/Kconfig
-+++ b/drivers/input/joystick/Kconfig
-@@ -351,4 +351,12 @@ config JOYSTICK_PSXPAD_SPI_FF
- 
- 	  To drive rumble motor a dedicated power supply is required.
- 
-+config JOYSTICK_RPISENSE
-+	tristate "Raspberry Pi Sense HAT joystick"
-+	depends on GPIOLIB && INPUT
-+	select MFD_RPISENSE_CORE
-+
-+	help
-+	  This is the joystick driver for the Raspberry Pi Sense HAT
-+
- endif
---- a/drivers/input/joystick/Makefile
-+++ b/drivers/input/joystick/Makefile
-@@ -34,4 +34,5 @@ obj-$(CONFIG_JOYSTICK_WARRIOR)		+= warri
- obj-$(CONFIG_JOYSTICK_XPAD)		+= xpad.o
- obj-$(CONFIG_JOYSTICK_ZHENHUA)		+= zhenhua.o
- obj-$(CONFIG_JOYSTICK_WALKERA0701)	+= walkera0701.o
-+obj-$(CONFIG_JOYSTICK_RPISENSE)		+= rpisense-js.o
- 
---- /dev/null
-+++ b/drivers/input/joystick/rpisense-js.c
-@@ -0,0 +1,153 @@
-+/*
-+ * Raspberry Pi Sense HAT joystick driver
-+ * http://raspberrypi.org
-+ *
-+ * Copyright (C) 2015 Raspberry Pi
-+ *
-+ * Author: Serge Schneider
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ */
-+
-+#include <linux/module.h>
-+
-+#include <linux/mfd/rpisense/joystick.h>
-+#include <linux/mfd/rpisense/core.h>
-+
-+static struct rpisense *rpisense;
-+static unsigned char keymap[5] = {KEY_DOWN, KEY_RIGHT, KEY_UP, KEY_ENTER, KEY_LEFT,};
-+
-+static void keys_work_fn(struct work_struct *work)
-+{
-+	int i;
-+	static s32 prev_keys;
-+	struct rpisense_js *rpisense_js = &rpisense->joystick;
-+	s32 keys = rpisense_reg_read(rpisense, RPISENSE_KEYS);
-+	s32 changes = keys ^ prev_keys;
-+
-+	prev_keys = keys;
-+	for (i = 0; i < 5; i++) {
-+		if (changes & 1) {
-+			input_report_key(rpisense_js->keys_dev,
-+					 keymap[i], keys & 1);
-+		}
-+		changes >>= 1;
-+		keys >>= 1;
-+	}
-+	input_sync(rpisense_js->keys_dev);
-+}
-+
-+static irqreturn_t keys_irq_handler(int irq, void *pdev)
-+{
-+	struct rpisense_js *rpisense_js = &rpisense->joystick;
-+
-+	schedule_work(&rpisense_js->keys_work_s);
-+	return IRQ_HANDLED;
-+}
-+
-+static int rpisense_js_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	int i;
-+	struct rpisense_js *rpisense_js;
-+
-+	rpisense = rpisense_get_dev();
-+	rpisense_js = &rpisense->joystick;
-+
-+	INIT_WORK(&rpisense_js->keys_work_s, keys_work_fn);
-+
-+	rpisense_js->keys_dev = input_allocate_device();
-+	if (!rpisense_js->keys_dev) {
-+		dev_err(&pdev->dev, "Could not allocate input device.\n");
-+		return -ENOMEM;
-+	}
-+
-+	rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY);
-+	for (i = 0; i < ARRAY_SIZE(keymap); i++) {
-+		set_bit(keymap[i],
-+			rpisense_js->keys_dev->keybit);
-+	}
-+
-+	rpisense_js->keys_dev->name = "Raspberry Pi Sense HAT Joystick";
-+	rpisense_js->keys_dev->phys = "rpi-sense-joy/input0";
-+	rpisense_js->keys_dev->id.bustype = BUS_I2C;
-+	rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP);
-+	rpisense_js->keys_dev->keycode = keymap;
-+	rpisense_js->keys_dev->keycodesize = sizeof(unsigned char);
-+	rpisense_js->keys_dev->keycodemax = ARRAY_SIZE(keymap);
-+
-+	ret = input_register_device(rpisense_js->keys_dev);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Could not register input device.\n");
-+		goto err_keys_alloc;
-+	}
-+
-+	ret = gpiod_direction_input(rpisense_js->keys_desc);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Could not set keys-int direction.\n");
-+		goto err_keys_reg;
-+	}
-+
-+	rpisense_js->keys_irq = gpiod_to_irq(rpisense_js->keys_desc);
-+	if (rpisense_js->keys_irq < 0) {
-+		dev_err(&pdev->dev, "Could not determine keys-int IRQ.\n");
-+		ret = rpisense_js->keys_irq;
-+		goto err_keys_reg;
-+	}
-+
-+	ret = devm_request_irq(&pdev->dev, rpisense_js->keys_irq,
-+			       keys_irq_handler, IRQF_TRIGGER_RISING,
-+			       "keys", &pdev->dev);
-+	if (ret) {
-+		dev_err(&pdev->dev, "IRQ request failed.\n");
-+		goto err_keys_reg;
-+	}
-+	return 0;
-+err_keys_reg:
-+	input_unregister_device(rpisense_js->keys_dev);
-+err_keys_alloc:
-+	input_free_device(rpisense_js->keys_dev);
-+	return ret;
-+}
-+
-+static int rpisense_js_remove(struct platform_device *pdev)
-+{
-+	struct rpisense_js *rpisense_js = &rpisense->joystick;
-+
-+	input_unregister_device(rpisense_js->keys_dev);
-+	input_free_device(rpisense_js->keys_dev);
-+	return 0;
-+}
-+
-+#ifdef CONFIG_OF
-+static const struct of_device_id rpisense_js_id[] = {
-+	{ .compatible = "rpi,rpi-sense-js" },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, rpisense_js_id);
-+#endif
-+
-+static struct platform_device_id rpisense_js_device_id[] = {
-+	{ .name = "rpi-sense-js" },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(platform, rpisense_js_device_id);
-+
-+static struct platform_driver rpisense_js_driver = {
-+	.probe = rpisense_js_probe,
-+	.remove = rpisense_js_remove,
-+	.driver = {
-+		.name = "rpi-sense-js",
-+		.owner = THIS_MODULE,
-+	},
-+};
-+
-+module_platform_driver(rpisense_js_driver);
-+
-+MODULE_DESCRIPTION("Raspberry Pi Sense HAT joystick driver");
-+MODULE_AUTHOR("Serge Schneider <serge@raspberrypi.org>");
-+MODULE_LICENSE("GPL");
---- a/drivers/mfd/Kconfig
-+++ b/drivers/mfd/Kconfig
-@@ -10,6 +10,14 @@ config MFD_CORE
- 	select IRQ_DOMAIN
- 	default n
- 
-+config MFD_RPISENSE_CORE
-+	tristate "Raspberry Pi Sense HAT core functions"
-+	depends on I2C
-+	select MFD_CORE
-+	help
-+	  This is the core driver for the Raspberry Pi Sense HAT. This provides
-+	  the necessary functions to communicate with the hardware.
-+
- config MFD_CS5535
- 	tristate "AMD CS5535 and CS5536 southbridge core functions"
- 	select MFD_CORE
---- a/drivers/mfd/Makefile
-+++ b/drivers/mfd/Makefile
-@@ -227,3 +227,4 @@ obj-$(CONFIG_MFD_SUN4I_GPADC)	+= sun4i-g
- obj-$(CONFIG_MFD_STM32_LPTIMER)	+= stm32-lptimer.o
- obj-$(CONFIG_MFD_STM32_TIMERS) 	+= stm32-timers.o
- obj-$(CONFIG_MFD_MXS_LRADC)     += mxs-lradc.o
-+obj-$(CONFIG_MFD_RPISENSE_CORE)	+= rpisense-core.o
---- /dev/null
-+++ b/drivers/mfd/rpisense-core.c
-@@ -0,0 +1,157 @@
-+/*
-+ * Raspberry Pi Sense HAT core driver
-+ * http://raspberrypi.org
-+ *
-+ * Copyright (C) 2015 Raspberry Pi
-+ *
-+ * Author: Serge Schneider
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ *  This driver is based on wm8350 implementation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/i2c.h>
-+#include <linux/platform_device.h>
-+#include <linux/mfd/rpisense/core.h>
-+#include <linux/slab.h>
-+
-+static struct rpisense *rpisense;
-+
-+static void rpisense_client_dev_register(struct rpisense *rpisense,
-+					 const char *name,
-+					 struct platform_device **pdev)
-+{
-+	int ret;
-+
-+	*pdev = platform_device_alloc(name, -1);
-+	if (*pdev == NULL) {
-+		dev_err(rpisense->dev, "Failed to allocate %s\n", name);
-+		return;
-+	}
-+
-+	(*pdev)->dev.parent = rpisense->dev;
-+	platform_set_drvdata(*pdev, rpisense);
-+	ret = platform_device_add(*pdev);
-+	if (ret != 0) {
-+		dev_err(rpisense->dev, "Failed to register %s: %d\n",
-+			name, ret);
-+		platform_device_put(*pdev);
-+		*pdev = NULL;
-+	}
-+}
-+
-+static int rpisense_probe(struct i2c_client *i2c,
-+			       const struct i2c_device_id *id)
-+{
-+	int ret;
-+	struct rpisense_js *rpisense_js;
-+
-+	rpisense = devm_kzalloc(&i2c->dev, sizeof(struct rpisense), GFP_KERNEL);
-+	if (rpisense == NULL)
-+		return -ENOMEM;
-+
-+	i2c_set_clientdata(i2c, rpisense);
-+	rpisense->dev = &i2c->dev;
-+	rpisense->i2c_client = i2c;
-+
-+	ret = rpisense_reg_read(rpisense, RPISENSE_WAI);
-+	if (ret > 0) {
-+		if (ret != 's')
-+			return -EINVAL;
-+	} else {
-+		return ret;
-+	}
-+	ret = rpisense_reg_read(rpisense, RPISENSE_VER);
-+	if (ret < 0)
-+		return ret;
-+
-+	dev_info(rpisense->dev,
-+		 "Raspberry Pi Sense HAT firmware version %i\n", ret);
-+
-+	rpisense_js = &rpisense->joystick;
-+	rpisense_js->keys_desc = devm_gpiod_get(&i2c->dev,
-+						"keys-int", GPIOD_IN);
-+	if (IS_ERR(rpisense_js->keys_desc)) {
-+		dev_warn(&i2c->dev, "Failed to get keys-int descriptor.\n");
-+		rpisense_js->keys_desc = gpio_to_desc(23);
-+		if (rpisense_js->keys_desc == NULL) {
-+			dev_err(&i2c->dev, "GPIO23 fallback failed.\n");
-+			return PTR_ERR(rpisense_js->keys_desc);
-+		}
-+	}
-+	rpisense_client_dev_register(rpisense, "rpi-sense-js",
-+				     &(rpisense->joystick.pdev));
-+	rpisense_client_dev_register(rpisense, "rpi-sense-fb",
-+				     &(rpisense->framebuffer.pdev));
-+
-+	return 0;
-+}
-+
-+static int rpisense_remove(struct i2c_client *i2c)
-+{
-+	struct rpisense *rpisense = i2c_get_clientdata(i2c);
-+
-+	platform_device_unregister(rpisense->joystick.pdev);
-+	return 0;
-+}
-+
-+struct rpisense *rpisense_get_dev(void)
-+{
-+	return rpisense;
-+}
-+EXPORT_SYMBOL_GPL(rpisense_get_dev);
-+
-+s32 rpisense_reg_read(struct rpisense *rpisense, int reg)
-+{
-+	int ret = i2c_smbus_read_byte_data(rpisense->i2c_client, reg);
-+
-+	if (ret < 0)
-+		dev_err(rpisense->dev, "Read from reg %d failed\n", reg);
-+	/* Due to the BCM270x I2C clock stretching bug, some values
-+	 * may have MSB set. Clear it to avoid incorrect values.
-+	 * */
-+	return ret & 0x7F;
-+}
-+EXPORT_SYMBOL_GPL(rpisense_reg_read);
-+
-+int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count)
-+{
-+	int ret = i2c_master_send(rpisense->i2c_client, buf, count);
-+
-+	if (ret < 0)
-+		dev_err(rpisense->dev, "Block write failed\n");
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(rpisense_block_write);
-+
-+static const struct i2c_device_id rpisense_i2c_id[] = {
-+	{ "rpi-sense", 0 },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(i2c, rpisense_i2c_id);
-+
-+
-+static struct i2c_driver rpisense_driver = {
-+	.driver = {
-+		   .name = "rpi-sense",
-+		   .owner = THIS_MODULE,
-+	},
-+	.probe = rpisense_probe,
-+	.remove = rpisense_remove,
-+	.id_table = rpisense_i2c_id,
-+};
-+
-+module_i2c_driver(rpisense_driver);
-+
-+MODULE_DESCRIPTION("Raspberry Pi Sense HAT core driver");
-+MODULE_AUTHOR("Serge Schneider <serge@raspberrypi.org>");
-+MODULE_LICENSE("GPL");
-+
---- a/drivers/video/fbdev/Kconfig
-+++ b/drivers/video/fbdev/Kconfig
-@@ -2510,3 +2510,16 @@ config FB_SM712
- 	  This driver is also available as a module. The module will be
- 	  called sm712fb. If you want to compile it as a module, say M
- 	  here and read <file:Documentation/kbuild/modules.txt>.
-+
-+config FB_RPISENSE
-+	tristate "Raspberry Pi Sense HAT framebuffer"
-+	depends on FB
-+	select MFD_RPISENSE_CORE
-+	select FB_SYS_FOPS
-+	select FB_SYS_FILLRECT
-+	select FB_SYS_COPYAREA
-+	select FB_SYS_IMAGEBLIT
-+	select FB_DEFERRED_IO
-+
-+	help
-+	  This is the framebuffer driver for the Raspberry Pi Sense HAT
---- a/drivers/video/fbdev/Makefile
-+++ b/drivers/video/fbdev/Makefile
-@@ -148,6 +148,7 @@ obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
- obj-$(CONFIG_FB_MXS)		  += mxsfb.o
- obj-$(CONFIG_FB_SSD1307)	  += ssd1307fb.o
- obj-$(CONFIG_FB_SIMPLE)           += simplefb.o
-+obj-$(CONFIG_FB_RPISENSE)	  += rpisense-fb.o
- 
- # the test framebuffer is last
- obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
---- /dev/null
-+++ b/drivers/video/fbdev/rpisense-fb.c
-@@ -0,0 +1,293 @@
-+/*
-+ * Raspberry Pi Sense HAT framebuffer driver
-+ * http://raspberrypi.org
-+ *
-+ * Copyright (C) 2015 Raspberry Pi
-+ *
-+ * Author: Serge Schneider
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/errno.h>
-+#include <linux/string.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/uaccess.h>
-+#include <linux/delay.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+
-+#include <linux/mfd/rpisense/framebuffer.h>
-+#include <linux/mfd/rpisense/core.h>
-+
-+static bool lowlight;
-+module_param(lowlight, bool, 0);
-+MODULE_PARM_DESC(lowlight, "Reduce LED matrix brightness to one third");
-+
-+static struct rpisense *rpisense;
-+
-+struct rpisense_fb_param {
-+	char __iomem *vmem;
-+	u8 *vmem_work;
-+	u32 vmemsize;
-+	u8 *gamma;
-+};
-+
-+static u8 gamma_default[32] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
-+			       0x02, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07,
-+			       0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0E, 0x0F, 0x11,
-+			       0x12, 0x14, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,};
-+
-+static u8 gamma_low[32] = {0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-+			   0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02,
-+			   0x03, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06,
-+			   0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x0A, 0x0A,};
-+
-+static u8 gamma_user[32];
-+
-+static struct rpisense_fb_param rpisense_fb_param = {
-+	.vmem = NULL,
-+	.vmemsize = 128,
-+	.gamma = gamma_default,
-+};
-+
-+static struct fb_deferred_io rpisense_fb_defio;
-+
-+static struct fb_fix_screeninfo rpisense_fb_fix = {
-+	.id =		"RPi-Sense FB",
-+	.type =		FB_TYPE_PACKED_PIXELS,
-+	.visual =	FB_VISUAL_TRUECOLOR,
-+	.xpanstep =	0,
-+	.ypanstep =	0,
-+	.ywrapstep =	0,
-+	.accel =	FB_ACCEL_NONE,
-+	.line_length =	16,
-+};
-+
-+static struct fb_var_screeninfo rpisense_fb_var = {
-+	.xres		= 8,
-+	.yres		= 8,
-+	.xres_virtual	= 8,
-+	.yres_virtual	= 8,
-+	.bits_per_pixel = 16,
-+	.red		= {11, 5, 0},
-+	.green		= {5, 6, 0},
-+	.blue		= {0, 5, 0},
-+};
-+
-+static ssize_t rpisense_fb_write(struct fb_info *info,
-+				 const char __user *buf, size_t count,
-+				 loff_t *ppos)
-+{
-+	ssize_t res = fb_sys_write(info, buf, count, ppos);
-+
-+	schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
-+	return res;
-+}
-+
-+static void rpisense_fb_fillrect(struct fb_info *info,
-+				 const struct fb_fillrect *rect)
-+{
-+	sys_fillrect(info, rect);
-+	schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
-+}
-+
-+static void rpisense_fb_copyarea(struct fb_info *info,
-+				 const struct fb_copyarea *area)
-+{
-+	sys_copyarea(info, area);
-+	schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
-+}
-+
-+static void rpisense_fb_imageblit(struct fb_info *info,
-+				  const struct fb_image *image)
-+{
-+	sys_imageblit(info, image);
-+	schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
-+}
-+
-+static void rpisense_fb_deferred_io(struct fb_info *info,
-+				struct list_head *pagelist)
-+{
-+	int i;
-+	int j;
-+	u8 *vmem_work = rpisense_fb_param.vmem_work;
-+	u16 *mem = (u16 *)rpisense_fb_param.vmem;
-+	u8 *gamma = rpisense_fb_param.gamma;
-+
-+	vmem_work[0] = 0;
-+	for (j = 0; j < 8; j++) {
-+		for (i = 0; i < 8; i++) {
-+			vmem_work[(j * 24) + i + 1] =
-+				gamma[(mem[(j * 8) + i] >> 11) & 0x1F];
-+			vmem_work[(j * 24) + (i + 8) + 1] =
-+				gamma[(mem[(j * 8) + i] >> 6) & 0x1F];
-+			vmem_work[(j * 24) + (i + 16) + 1] =
-+				gamma[(mem[(j * 8) + i]) & 0x1F];
-+		}
-+	}
-+	rpisense_block_write(rpisense, vmem_work, 193);
-+}
-+
-+static struct fb_deferred_io rpisense_fb_defio = {
-+	.delay		= HZ/100,
-+	.deferred_io	= rpisense_fb_deferred_io,
-+};
-+
-+static int rpisense_fb_ioctl(struct fb_info *info, unsigned int cmd,
-+			     unsigned long arg)
-+{
-+	switch (cmd) {
-+	case SENSEFB_FBIOGET_GAMMA:
-+		if (copy_to_user((void __user *) arg, rpisense_fb_param.gamma,
-+				 sizeof(u8[32])))
-+			return -EFAULT;
-+		return 0;
-+	case SENSEFB_FBIOSET_GAMMA:
-+		if (copy_from_user(gamma_user, (void __user *)arg,
-+				   sizeof(u8[32])))
-+			return -EFAULT;
-+		rpisense_fb_param.gamma = gamma_user;
-+		schedule_delayed_work(&info->deferred_work,
-+				      rpisense_fb_defio.delay);
-+		return 0;
-+	case SENSEFB_FBIORESET_GAMMA:
-+		switch (arg) {
-+		case 0:
-+			rpisense_fb_param.gamma = gamma_default;
-+			break;
-+		case 1:
-+			rpisense_fb_param.gamma = gamma_low;
-+			break;
-+		case 2:
-+			rpisense_fb_param.gamma = gamma_user;
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		schedule_delayed_work(&info->deferred_work,
-+				      rpisense_fb_defio.delay);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+	return 0;
-+}
-+
-+static struct fb_ops rpisense_fb_ops = {
-+	.owner		= THIS_MODULE,
-+	.fb_read	= fb_sys_read,
-+	.fb_write	= rpisense_fb_write,
-+	.fb_fillrect	= rpisense_fb_fillrect,
-+	.fb_copyarea	= rpisense_fb_copyarea,
-+	.fb_imageblit	= rpisense_fb_imageblit,
-+	.fb_ioctl	= rpisense_fb_ioctl,
-+};
-+
-+static int rpisense_fb_probe(struct platform_device *pdev)
-+{
-+	struct fb_info *info;
-+	int ret = -ENOMEM;
-+	struct rpisense_fb *rpisense_fb;
-+
-+	rpisense = rpisense_get_dev();
-+	rpisense_fb = &rpisense->framebuffer;
-+
-+	rpisense_fb_param.vmem = vzalloc(rpisense_fb_param.vmemsize);
-+	if (!rpisense_fb_param.vmem)
-+		return ret;
-+
-+	rpisense_fb_param.vmem_work = devm_kmalloc(&pdev->dev, 193, GFP_KERNEL);
-+	if (!rpisense_fb_param.vmem_work)
-+		goto err_malloc;
-+
-+	info = framebuffer_alloc(0, &pdev->dev);
-+	if (!info) {
-+		dev_err(&pdev->dev, "Could not allocate framebuffer.\n");
-+		goto err_malloc;
-+	}
-+	rpisense_fb->info = info;
-+
-+	rpisense_fb_fix.smem_start = (unsigned long)rpisense_fb_param.vmem;
-+	rpisense_fb_fix.smem_len = rpisense_fb_param.vmemsize;
-+
-+	info->fbops = &rpisense_fb_ops;
-+	info->fix = rpisense_fb_fix;
-+	info->var = rpisense_fb_var;
-+	info->fbdefio = &rpisense_fb_defio;
-+	info->flags = FBINFO_FLAG_DEFAULT | FBINFO_VIRTFB;
-+	info->screen_base = rpisense_fb_param.vmem;
-+	info->screen_size = rpisense_fb_param.vmemsize;
-+
-+	if (lowlight)
-+		rpisense_fb_param.gamma = gamma_low;
-+
-+	fb_deferred_io_init(info);
-+
-+	ret = register_framebuffer(info);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Could not register framebuffer.\n");
-+		goto err_fballoc;
-+	}
-+
-+	fb_info(info, "%s frame buffer device\n", info->fix.id);
-+	schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);
-+	return 0;
-+err_fballoc:
-+	framebuffer_release(info);
-+err_malloc:
-+	vfree(rpisense_fb_param.vmem);
-+	return ret;
-+}
-+
-+static int rpisense_fb_remove(struct platform_device *pdev)
-+{
-+	struct rpisense_fb *rpisense_fb = &rpisense->framebuffer;
-+	struct fb_info *info = rpisense_fb->info;
-+
-+	if (info) {
-+		unregister_framebuffer(info);
-+		fb_deferred_io_cleanup(info);
-+		framebuffer_release(info);
-+		vfree(rpisense_fb_param.vmem);
-+	}
-+
-+	return 0;
-+}
-+
-+#ifdef CONFIG_OF
-+static const struct of_device_id rpisense_fb_id[] = {
-+	{ .compatible = "rpi,rpi-sense-fb" },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, rpisense_fb_id);
-+#endif
-+
-+static struct platform_device_id rpisense_fb_device_id[] = {
-+	{ .name = "rpi-sense-fb" },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(platform, rpisense_fb_device_id);
-+
-+static struct platform_driver rpisense_fb_driver = {
-+	.probe = rpisense_fb_probe,
-+	.remove = rpisense_fb_remove,
-+	.driver = {
-+		.name = "rpi-sense-fb",
-+		.owner = THIS_MODULE,
-+	},
-+};
-+
-+module_platform_driver(rpisense_fb_driver);
-+
-+MODULE_DESCRIPTION("Raspberry Pi Sense HAT framebuffer driver");
-+MODULE_AUTHOR("Serge Schneider <serge@raspberrypi.org>");
-+MODULE_LICENSE("GPL");
-+
---- /dev/null
-+++ b/include/linux/mfd/rpisense/core.h
-@@ -0,0 +1,47 @@
-+/*
-+ * Raspberry Pi Sense HAT core driver
-+ * http://raspberrypi.org
-+ *
-+ * Copyright (C) 2015 Raspberry Pi
-+ *
-+ * Author: Serge Schneider
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ */
-+
-+#ifndef __LINUX_MFD_RPISENSE_CORE_H_
-+#define __LINUX_MFD_RPISENSE_CORE_H_
-+
-+#include <linux/mfd/rpisense/joystick.h>
-+#include <linux/mfd/rpisense/framebuffer.h>
-+
-+/*
-+ * Register values.
-+ */
-+#define RPISENSE_FB			0x00
-+#define RPISENSE_WAI			0xF0
-+#define RPISENSE_VER			0xF1
-+#define RPISENSE_KEYS			0xF2
-+#define RPISENSE_EE_WP			0xF3
-+
-+#define RPISENSE_ID			's'
-+
-+struct rpisense {
-+	struct device *dev;
-+	struct i2c_client *i2c_client;
-+
-+	/* Client devices */
-+	struct rpisense_js joystick;
-+	struct rpisense_fb framebuffer;
-+};
-+
-+struct rpisense *rpisense_get_dev(void);
-+s32 rpisense_reg_read(struct rpisense *rpisense, int reg);
-+int rpisense_reg_write(struct rpisense *rpisense, int reg, u16 val);
-+int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count);
-+
-+#endif
---- /dev/null
-+++ b/include/linux/mfd/rpisense/framebuffer.h
-@@ -0,0 +1,32 @@
-+/*
-+ * Raspberry Pi Sense HAT framebuffer driver
-+ * http://raspberrypi.org
-+ *
-+ * Copyright (C) 2015 Raspberry Pi
-+ *
-+ * Author: Serge Schneider
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ */
-+
-+#ifndef __LINUX_RPISENSE_FB_H_
-+#define __LINUX_RPISENSE_FB_H_
-+
-+#define SENSEFB_FBIO_IOC_MAGIC 0xF1
-+
-+#define SENSEFB_FBIOGET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 0)
-+#define SENSEFB_FBIOSET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 1)
-+#define SENSEFB_FBIORESET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 2)
-+
-+struct rpisense;
-+
-+struct rpisense_fb {
-+	struct platform_device *pdev;
-+	struct fb_info *info;
-+};
-+
-+#endif
---- /dev/null
-+++ b/include/linux/mfd/rpisense/joystick.h
-@@ -0,0 +1,35 @@
-+/*
-+ * Raspberry Pi Sense HAT joystick driver
-+ * http://raspberrypi.org
-+ *
-+ * Copyright (C) 2015 Raspberry Pi
-+ *
-+ * Author: Serge Schneider
-+ *
-+ *  This program is free software; you can redistribute  it and/or modify it
-+ *  under  the terms of  the GNU General  Public License as published by the
-+ *  Free Software Foundation;  either version 2 of the  License, or (at your
-+ *  option) any later version.
-+ *
-+ */
-+
-+#ifndef __LINUX_RPISENSE_JOYSTICK_H_
-+#define __LINUX_RPISENSE_JOYSTICK_H_
-+
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/platform_device.h>
-+
-+struct rpisense;
-+
-+struct rpisense_js {
-+	struct platform_device *pdev;
-+	struct input_dev *keys_dev;
-+	struct gpio_desc *keys_desc;
-+	struct work_struct keys_work_s;
-+	int keys_irq;
-+};
-+
-+
-+#endif
diff --git a/target/linux/brcm2708/patches-4.14/950-0064-ASoC-Add-support-for-HifiBerry-DAC.patch b/target/linux/brcm2708/patches-4.14/950-0064-ASoC-Add-support-for-HifiBerry-DAC.patch
deleted file mode 100644
index 7306e674f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0064-ASoC-Add-support-for-HifiBerry-DAC.patch
+++ /dev/null
@@ -1,170 +0,0 @@
-From d8e006c632e99c1f7440673181104768135a64e4 Mon Sep 17 00:00:00 2001
-From: Florian Meier <florian.meier@koalo.de>
-Date: Fri, 22 Nov 2013 19:19:08 +0100
-Subject: [PATCH 064/454] ASoC: Add support for HifiBerry DAC
-
-This adds a machine driver for the HifiBerry DAC.
-It is a sound card that can
-be stacked onto the Raspberry Pi.
-
-Signed-off-by: Florian Meier <florian.meier@koalo.de>
----
- sound/soc/bcm/Kconfig         |   9 ++-
- sound/soc/bcm/Makefile        |   4 ++
- sound/soc/bcm/hifiberry_dac.c | 124 ++++++++++++++++++++++++++++++++++
- 3 files changed, 136 insertions(+), 1 deletion(-)
- create mode 100644 sound/soc/bcm/hifiberry_dac.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -16,4 +16,11 @@ config SND_SOC_CYGNUS
- 	  Say Y if you want to add support for ASoC audio on Broadcom
- 	  Cygnus chips (bcm958300, bcm958305, bcm911360)
- 
--	  If you don't know what to do here, say N.
-\ No newline at end of file
-+	  If you don't know what to do here, say N.
-+
-+config SND_BCM2708_SOC_HIFIBERRY_DAC
-+        tristate "Support for HifiBerry DAC"
-+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+        select SND_SOC_PCM5102A
-+        help
-+         Say Y or M if you want to add support for HifiBerry DAC.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -8,3 +8,7 @@ snd-soc-cygnus-objs := cygnus-pcm.o cygn
- 
- obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-cygnus.o
- 
-+# BCM2708 Machine Support
-+snd-soc-hifiberry-dac-objs := hifiberry_dac.o
-+
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/hifiberry_dac.c
-@@ -0,0 +1,124 @@
-+/*
-+ * ASoC Driver for HifiBerry DAC
-+ *
-+ * Author:	Florian Meier <florian.meier@koalo.de>
-+ *		Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_hifiberry_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	return 0;
-+}
-+
-+static int snd_rpi_hifiberry_dac_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_dac_ops = {
-+	.hw_params = snd_rpi_hifiberry_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_dac_dai[] = {
-+{
-+	.name		= "HifiBerry DAC",
-+	.stream_name	= "HifiBerry DAC HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm5102a-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm5102a-codec",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_hifiberry_dac_ops,
-+	.init		= snd_rpi_hifiberry_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_dac = {
-+	.name         = "snd_rpi_hifiberry_dac",
-+	.driver_name  = "HifiberryDac",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_hifiberry_dac_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_hifiberry_dac_dai),
-+};
-+
-+static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_hifiberry_dac.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+	    struct device_node *i2s_node;
-+	    struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0];
-+	    i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					"i2s-controller", 0);
-+
-+	    if (i2s_node) {
-+		dai->cpu_dai_name = NULL;
-+		dai->cpu_of_node = i2s_node;
-+		dai->platform_name = NULL;
-+		dai->platform_of_node = i2s_node;
-+	    }
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_hifiberry_dac);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_hifiberry_dac);
-+}
-+
-+static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = {
-+	{ .compatible = "hifiberry,hifiberry-dac", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match);
-+
-+static struct platform_driver snd_rpi_hifiberry_dac_driver = {
-+        .driver = {
-+                .name   = "snd-hifiberry-dac",
-+                .owner  = THIS_MODULE,
-+		.of_match_table = snd_rpi_hifiberry_dac_of_match,
-+        },
-+        .probe          = snd_rpi_hifiberry_dac_probe,
-+        .remove         = snd_rpi_hifiberry_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for HifiBerry DAC");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0065-ASoC-Add-support-for-Rpi-DAC.patch b/target/linux/brcm2708/patches-4.14/950-0065-ASoC-Add-support-for-Rpi-DAC.patch
deleted file mode 100644
index fd6ac834c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0065-ASoC-Add-support-for-Rpi-DAC.patch
+++ /dev/null
@@ -1,272 +0,0 @@
-From 69baa142d45454f74dddff0863a6432fe0664b5e Mon Sep 17 00:00:00 2001
-From: Florian Meier <florian.meier@koalo.de>
-Date: Mon, 25 Jan 2016 15:48:59 +0000
-Subject: [PATCH 065/454] ASoC: Add support for Rpi-DAC
-
----
- sound/soc/bcm/Kconfig       |   7 +++
- sound/soc/bcm/Makefile      |   2 +
- sound/soc/bcm/rpi-dac.c     | 119 ++++++++++++++++++++++++++++++++++++
- sound/soc/codecs/Kconfig    |   5 ++
- sound/soc/codecs/Makefile   |   2 +
- sound/soc/codecs/pcm1794a.c |  69 +++++++++++++++++++++
- 6 files changed, 204 insertions(+)
- create mode 100644 sound/soc/bcm/rpi-dac.c
- create mode 100644 sound/soc/codecs/pcm1794a.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -24,3 +24,10 @@ config SND_BCM2708_SOC_HIFIBERRY_DAC
-         select SND_SOC_PCM5102A
-         help
-          Say Y or M if you want to add support for HifiBerry DAC.
-+
-+config SND_BCM2708_SOC_RPI_DAC
-+        tristate "Support for RPi-DAC"
-+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+        select SND_SOC_PCM1794A
-+        help
-+         Say Y or M if you want to add support for RPi-DAC.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -10,5 +10,7 @@ obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-
- 
- # BCM2708 Machine Support
- snd-soc-hifiberry-dac-objs := hifiberry_dac.o
-+snd-soc-rpi-dac-objs := rpi-dac.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/rpi-dac.c
-@@ -0,0 +1,119 @@
-+/*
-+ * ASoC Driver for RPi-DAC.
-+ *
-+ * Author:	Florian Meier <florian.meier@koalo.de>
-+ *		Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_rpi_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	return 0;
-+}
-+
-+static int snd_rpi_rpi_dac_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_rpi_dac_ops = {
-+	.hw_params = snd_rpi_rpi_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = {
-+{
-+	.name		= "RPi-DAC",
-+	.stream_name	= "RPi-DAC HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm1794a-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm1794a-codec",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_rpi_dac_ops,
-+	.init		= snd_rpi_rpi_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_rpi_dac = {
-+	.name         = "snd_rpi_rpi_dac",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_rpi_dac_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_rpi_dac_dai),
-+};
-+
-+static int snd_rpi_rpi_dac_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_rpi_dac.dev = &pdev->dev;
-+	
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0];
-+		i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+	}
-+	
-+	ret = snd_soc_register_card(&snd_rpi_rpi_dac);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_rpi_dac_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_rpi_dac);
-+}
-+
-+static const struct of_device_id snd_rpi_rpi_dac_of_match[] = {
-+	{ .compatible = "rpi,rpi-dac", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match);
-+
-+static struct platform_driver snd_rpi_rpi_dac_driver = {
-+        .driver = {
-+                .name   = "snd-rpi-dac",
-+                .owner  = THIS_MODULE,
-+                .of_match_table = snd_rpi_rpi_dac_of_match,
-+        },
-+        .probe          = snd_rpi_rpi_dac_probe,
-+        .remove         = snd_rpi_rpi_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_rpi_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for RPi-DAC");
-+MODULE_LICENSE("GPL v2");
---- a/sound/soc/codecs/Kconfig
-+++ b/sound/soc/codecs/Kconfig
-@@ -109,6 +109,7 @@ config SND_SOC_ALL_CODECS
- 	select SND_SOC_PCM1681 if I2C
- 	select SND_SOC_PCM179X_I2C if I2C
- 	select SND_SOC_PCM179X_SPI if SPI_MASTER
-+	select SND_SOC_PCM1794A if I2C
- 	select SND_SOC_PCM3008
- 	select SND_SOC_PCM3168A_I2C if I2C
- 	select SND_SOC_PCM3168A_SPI if SPI_MASTER
-@@ -753,6 +754,10 @@ config SND_SOC_RT5616
- 	tristate "Realtek RT5616 CODEC"
- 	depends on I2C
- 
-+config SND_SOC_PCM1794A
-+	tristate
-+	depends on I2C
-+
- config SND_SOC_RT5631
- 	tristate "Realtek ALC5631/RT5631 CODEC"
- 	depends on I2C
---- a/sound/soc/codecs/Makefile
-+++ b/sound/soc/codecs/Makefile
-@@ -105,6 +105,7 @@ snd-soc-pcm1681-objs := pcm1681.o
- snd-soc-pcm179x-codec-objs := pcm179x.o
- snd-soc-pcm179x-i2c-objs := pcm179x-i2c.o
- snd-soc-pcm179x-spi-objs := pcm179x-spi.o
-+snd-soc-pcm1794a-objs := pcm1794a.o
- snd-soc-pcm3008-objs := pcm3008.o
- snd-soc-pcm3168a-objs := pcm3168a.o
- snd-soc-pcm3168a-i2c-objs := pcm3168a-i2c.o
-@@ -353,6 +354,7 @@ obj-$(CONFIG_SND_SOC_PCM5102A)	+= snd-so
- obj-$(CONFIG_SND_SOC_PCM512x)	+= snd-soc-pcm512x.o
- obj-$(CONFIG_SND_SOC_PCM512x_I2C)	+= snd-soc-pcm512x-i2c.o
- obj-$(CONFIG_SND_SOC_PCM512x_SPI)	+= snd-soc-pcm512x-spi.o
-+obj-$(CONFIG_SND_SOC_PCM1794A)	+= snd-soc-pcm1794a.o
- obj-$(CONFIG_SND_SOC_RL6231)	+= snd-soc-rl6231.o
- obj-$(CONFIG_SND_SOC_RL6347A)	+= snd-soc-rl6347a.o
- obj-$(CONFIG_SND_SOC_RT274)	+= snd-soc-rt274.o
---- /dev/null
-+++ b/sound/soc/codecs/pcm1794a.c
-@@ -0,0 +1,69 @@
-+/*
-+ * Driver for the PCM1794A codec
-+ *
-+ * Author:	Florian Meier <florian.meier@koalo.de>
-+ *		Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/soc.h>
-+
-+static struct snd_soc_dai_driver pcm1794a_dai = {
-+	.name = "pcm1794a-hifi",
-+	.playback = {
-+		.channels_min = 2,
-+		.channels_max = 2,
-+		.rates = SNDRV_PCM_RATE_8000_192000,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE |
-+			   SNDRV_PCM_FMTBIT_S24_LE
-+	},
-+};
-+
-+static struct snd_soc_codec_driver soc_codec_dev_pcm1794a;
-+
-+static int pcm1794a_probe(struct platform_device *pdev)
-+{
-+	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm1794a,
-+			&pcm1794a_dai, 1);
-+}
-+
-+static int pcm1794a_remove(struct platform_device *pdev)
-+{
-+	snd_soc_unregister_codec(&pdev->dev);
-+	return 0;
-+}
-+
-+static const struct of_device_id pcm1794a_of_match[] = {
-+	{ .compatible = "ti,pcm1794a", },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, pcm1794a_of_match);
-+
-+static struct platform_driver pcm1794a_codec_driver = {
-+	.probe 		= pcm1794a_probe,
-+	.remove 	= pcm1794a_remove,
-+	.driver		= {
-+		.name	= "pcm1794a-codec",
-+		.owner	= THIS_MODULE,
-+		.of_match_table = of_match_ptr(pcm1794a_of_match),
-+	},
-+};
-+
-+module_platform_driver(pcm1794a_codec_driver);
-+
-+MODULE_DESCRIPTION("ASoC PCM1794A codec driver");
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0066-ASoC-wm8804-Implement-MCLK-configuration-options-add.patch b/target/linux/brcm2708/patches-4.14/950-0066-ASoC-wm8804-Implement-MCLK-configuration-options-add.patch
deleted file mode 100644
index db88e0118..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0066-ASoC-wm8804-Implement-MCLK-configuration-options-add.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From eeb120030591b06ea9f9a09383180f8f24f2baba Mon Sep 17 00:00:00 2001
-From: Daniel Matuschek <info@crazy-audio.com>
-Date: Wed, 15 Jan 2014 21:41:23 +0100
-Subject: [PATCH 066/454] ASoC: wm8804: Implement MCLK configuration options,
- add 32bit support WM8804 can run with PLL frequencies of 256xfs and 128xfs
- for most sample rates. At 192kHz only 128xfs is supported. The existing
- driver selects 128xfs automatically for some lower samples rates. By using an
- additional mclk_div divider, it is now possible to control the behaviour.
- This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It
- should allow lower jitter and better signal quality. The behavior has to be
- controlled by the sound card driver, because some sample frequency share the
- same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only
- difference is the MCLK divider.
-
-This also added support for 32bit data.
-
-Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
----
- sound/soc/codecs/wm8804.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/sound/soc/codecs/wm8804.c
-+++ b/sound/soc/codecs/wm8804.c
-@@ -304,6 +304,7 @@ static int wm8804_hw_params(struct snd_p
- 		blen = 0x1;
- 		break;
- 	case 24:
-+	case 32:
- 		blen = 0x2;
- 		break;
- 	default:
-@@ -515,7 +516,7 @@ static const struct snd_soc_dai_ops wm88
- };
- 
- #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
--			SNDRV_PCM_FMTBIT_S24_LE)
-+			SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
- 
- #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
- 		      SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
-@@ -543,7 +544,7 @@ static struct snd_soc_dai_driver wm8804_
- };
- 
- static const struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
--	.idle_bias_off = true,
-+	.idle_bias_off = false,
- 
- 	.component_driver = {
- 		.dapm_widgets		= wm8804_dapm_widgets,
diff --git a/target/linux/brcm2708/patches-4.14/950-0067-ASoC-BCM-Add-support-for-HiFiBerry-Digi.-Driver-is-b.patch b/target/linux/brcm2708/patches-4.14/950-0067-ASoC-BCM-Add-support-for-HiFiBerry-Digi.-Driver-is-b.patch
deleted file mode 100644
index f77ab539f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0067-ASoC-BCM-Add-support-for-HiFiBerry-Digi.-Driver-is-b.patch
+++ /dev/null
@@ -1,339 +0,0 @@
-From fbea312ab9d1b0edd50eb6947bc4905a9d25617a Mon Sep 17 00:00:00 2001
-From: Daniel Matuschek <info@crazy-audio.com>
-Date: Wed, 15 Jan 2014 21:42:08 +0100
-Subject: [PATCH 067/454] ASoC: BCM:Add support for HiFiBerry Digi. Driver is
- based on the patched WM8804 driver.
-
-Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
-
-Add a parameter to turn off SPDIF output if no audio is playing
-
-This patch adds the paramater auto_shutdown_output to the kernel module.
-Default behaviour of the module is the same, but when auto_shutdown_output
-is set to 1, the SPDIF oputput will shutdown if no stream is playing.
-
-bugfix for 32kHz sample rate, was missing
-
-HiFiBerry Digi: set SPDIF status bits for sample rate
-
-The HiFiBerry Digi driver did not signal the sample rate in the SPDIF status bits.
-While this is optional, some DACs and receivers do not accept this signal. This patch
-adds the sample rate bits in the SPDIF status block.
-
-Added HiFiBerry Digi+ Pro driver
-
-Signed-off-by: Daniel Matuschek <daniel@hifiberry.com>
----
- sound/soc/bcm/Kconfig          |   7 +
- sound/soc/bcm/Makefile         |   2 +
- sound/soc/bcm/hifiberry_digi.c | 276 +++++++++++++++++++++++++++++++++
- 3 files changed, 285 insertions(+)
- create mode 100644 sound/soc/bcm/hifiberry_digi.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -25,6 +25,13 @@ config SND_BCM2708_SOC_HIFIBERRY_DAC
-         help
-          Say Y or M if you want to add support for HifiBerry DAC.
- 
-+config SND_BCM2708_SOC_HIFIBERRY_DIGI
-+        tristate "Support for HifiBerry Digi"
-+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+        select SND_SOC_WM8804
-+        help
-+         Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board.
-+
- config SND_BCM2708_SOC_RPI_DAC
-         tristate "Support for RPi-DAC"
-         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -10,7 +10,9 @@ obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-
- 
- # BCM2708 Machine Support
- snd-soc-hifiberry-dac-objs := hifiberry_dac.o
-+snd-soc-hifiberry-digi-objs := hifiberry_digi.o
- snd-soc-rpi-dac-objs := rpi-dac.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/hifiberry_digi.c
-@@ -0,0 +1,276 @@
-+/*
-+ * ASoC Driver for HifiBerry Digi
-+ *
-+ * Author: Daniel Matuschek <info@crazy-audio.com>
-+ * based on the HifiBerry DAC driver by Florian Meier <florian.meier@koalo.de>
-+ *	Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+#include <linux/gpio/consumer.h>
-+
-+#include "../codecs/wm8804.h"
-+
-+static short int auto_shutdown_output = 0;
-+module_param(auto_shutdown_output, short, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
-+MODULE_PARM_DESC(auto_shutdown_output, "Shutdown SP/DIF output if playback is stopped");
-+
-+#define CLK_44EN_RATE 22579200UL
-+#define CLK_48EN_RATE 24576000UL
-+
-+static bool snd_rpi_hifiberry_is_digipro;
-+static struct gpio_desc *snd_rpi_hifiberry_clk44gpio;
-+static struct gpio_desc *snd_rpi_hifiberry_clk48gpio;
-+
-+static int samplerate=44100;
-+
-+static uint32_t snd_rpi_hifiberry_digi_enable_clock(int sample_rate)
-+{
-+	switch (sample_rate) {
-+	case 11025:
-+	case 22050:
-+	case 44100:
-+	case 88200:
-+	case 176400:
-+		gpiod_set_value_cansleep(snd_rpi_hifiberry_clk44gpio, 1);
-+		gpiod_set_value_cansleep(snd_rpi_hifiberry_clk48gpio, 0);
-+		return CLK_44EN_RATE;
-+	default:
-+		gpiod_set_value_cansleep(snd_rpi_hifiberry_clk48gpio, 1);
-+		gpiod_set_value_cansleep(snd_rpi_hifiberry_clk44gpio, 0);
-+		return CLK_48EN_RATE;
-+	}
-+}
-+
-+
-+static int snd_rpi_hifiberry_digi_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	/* enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	/* Initialize Digi+ Pro hardware */
-+	if (snd_rpi_hifiberry_is_digipro) {
-+		struct snd_soc_dai_link *dai = rtd->dai_link;
-+
-+		dai->name = "HiFiBerry Digi+ Pro";
-+		dai->stream_name = "HiFiBerry Digi+ Pro HiFi";
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_rpi_hifiberry_digi_startup(struct snd_pcm_substream *substream) {
-+	/* turn on digital output */
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00);
-+	return 0;
-+}
-+
-+static void snd_rpi_hifiberry_digi_shutdown(struct snd_pcm_substream *substream) {
-+	/* turn off output */
-+	if (auto_shutdown_output) {
-+		/* turn off output */
-+		struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+		struct snd_soc_codec *codec = rtd->codec;
-+		snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c);
-+	}
-+}
-+
-+
-+static int snd_rpi_hifiberry_digi_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	int sysclk = 27000000; /* This is fixed on this board */
-+
-+	long mclk_freq=0;
-+	int mclk_div=1;
-+	int sampling_freq=1;
-+
-+	int ret;
-+
-+	samplerate = params_rate(params);
-+
-+	if (samplerate<=96000) {
-+		mclk_freq=samplerate*256;
-+		mclk_div=WM8804_MCLKDIV_256FS;
-+	} else {
-+		mclk_freq=samplerate*128;
-+		mclk_div=WM8804_MCLKDIV_128FS;
-+	}
-+
-+	if (snd_rpi_hifiberry_is_digipro)
-+		sysclk = snd_rpi_hifiberry_digi_enable_clock(samplerate);
-+	
-+	switch (samplerate) {
-+		case 32000:
-+			sampling_freq=0x03;
-+			break;
-+		case 44100:
-+			sampling_freq=0x00;
-+			break;
-+		case 48000:
-+			sampling_freq=0x02;
-+			break;
-+		case 88200:
-+			sampling_freq=0x08;
-+			break;
-+		case 96000:
-+			sampling_freq=0x0a;
-+			break;
-+		case 176400:
-+			sampling_freq=0x0c;
-+			break;
-+		case 192000:
-+			sampling_freq=0x0e;
-+			break;
-+		default:
-+			dev_err(codec->dev,
-+			"Failed to set WM8804 SYSCLK, unsupported samplerate %d\n",
-+			samplerate);
-+	}
-+
-+	snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
-+	snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
-+
-+	ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
-+					sysclk, SND_SOC_CLOCK_OUT);
-+
-+	if (ret < 0) {
-+		dev_err(codec->dev,
-+		"Failed to set WM8804 SYSCLK: %d\n", ret);
-+		return ret;
-+	}
-+
-+	/* Enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	/* Power on */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
-+
-+	/* set sampling frequency status bits */
-+	snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq);
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai,64);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_digi_ops = {
-+	.hw_params = snd_rpi_hifiberry_digi_hw_params,
-+        .startup = snd_rpi_hifiberry_digi_startup,
-+        .shutdown = snd_rpi_hifiberry_digi_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_digi_dai[] = {
-+{
-+	.name		= "HifiBerry Digi",
-+	.stream_name	= "HifiBerry Digi HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "wm8804-spdif",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "wm8804.1-003b",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBM_CFM,
-+	.ops		= &snd_rpi_hifiberry_digi_ops,
-+	.init		= snd_rpi_hifiberry_digi_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_digi = {
-+	.name         = "snd_rpi_hifiberry_digi",
-+	.driver_name  = "HifiberryDigi",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_hifiberry_digi_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_hifiberry_digi_dai),
-+};
-+
-+static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_hifiberry_digi.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+	    struct device_node *i2s_node;
-+	    struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0];
-+	    i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					"i2s-controller", 0);
-+
-+	    if (i2s_node) {
-+		dai->cpu_dai_name = NULL;
-+		dai->cpu_of_node = i2s_node;
-+		dai->platform_name = NULL;
-+		dai->platform_of_node = i2s_node;
-+	    }
-+
-+	    snd_rpi_hifiberry_is_digipro = 1;
-+
-+	    snd_rpi_hifiberry_clk44gpio =
-+		devm_gpiod_get(&pdev->dev, "clock44", GPIOD_OUT_LOW);
-+	    if (IS_ERR(snd_rpi_hifiberry_clk44gpio))
-+		snd_rpi_hifiberry_is_digipro = 0;
-+
-+	    snd_rpi_hifiberry_clk48gpio =
-+		devm_gpiod_get(&pdev->dev, "clock48", GPIOD_OUT_LOW);
-+	    if (IS_ERR(snd_rpi_hifiberry_clk48gpio))
-+		snd_rpi_hifiberry_is_digipro = 0;
-+
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_hifiberry_digi);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_hifiberry_digi);
-+}
-+
-+static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = {
-+	{ .compatible = "hifiberry,hifiberry-digi", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match);
-+
-+static struct platform_driver snd_rpi_hifiberry_digi_driver = {
-+	.driver = {
-+		.name   = "snd-hifiberry-digi",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_rpi_hifiberry_digi_of_match,
-+	},
-+	.probe          = snd_rpi_hifiberry_digi_probe,
-+	.remove         = snd_rpi_hifiberry_digi_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_digi_driver);
-+
-+MODULE_AUTHOR("Daniel Matuschek <info@crazy-audio.com>");
-+MODULE_DESCRIPTION("ASoC Driver for HifiBerry Digi");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0068-Add-IQaudIO-Sound-Card-support-for-Raspberry-Pi.patch b/target/linux/brcm2708/patches-4.14/950-0068-Add-IQaudIO-Sound-Card-support-for-Raspberry-Pi.patch
deleted file mode 100644
index 2e8fc0a77..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0068-Add-IQaudIO-Sound-Card-support-for-Raspberry-Pi.patch
+++ /dev/null
@@ -1,330 +0,0 @@
-From d79b90e9d5f9d873f4366004ac7bb4aa46a8db2e Mon Sep 17 00:00:00 2001
-From: Gordon Garrity <gordon@iqaudio.com>
-Date: Sat, 8 Mar 2014 16:56:57 +0000
-Subject: [PATCH 068/454] Add IQaudIO Sound Card support for Raspberry Pi
-
-Set a limit of 0dB on Digital Volume Control
-
-The main volume control in the PCM512x DAC has a range up to
-+24dB. This is dangerously loud and can potentially cause massive
-clipping in the output stages. Therefore this sets a sensible
-limit of 0dB for this control.
-
-Allow up to 24dB digital gain to be applied when using IQAudIO DAC+
-
-24db_digital_gain DT param can be used to specify that PCM512x
-codec "Digital" volume control should not be limited to 0dB gain,
-and if specified will allow the full 24dB gain.
-
-Modify IQAudIO DAC+ ASoC driver to set card/dai config from dt
-
-Add the ability to set the card name, dai name and dai stream name, from
-dt config.
-
-Signed-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
-
-IQaudIO: auto-mute for AMP+ and DigiAMP+
-
-IQAudIO amplifier mute via GPIO22. Add dt params for "one-shot" unmute
-and auto mute.
-
-Revision 2, auto mute implementing HiassofT suggestion to mute/unmute
-using set_bias_level, rather than startup/shutdown....
-"By default DAPM waits 5 seconds (pmdown_time) before shutting down
-playback streams so a close/stop immediately followed by open/start
-doesn't trigger an amp mute+unmute."
-
-Tested on both AMP+ (via DAC+) and DigiAMP+, with both options...
-
-dtoverlay=iqaudio-dacplus,unmute_amp
- "one-shot" unmute when kernel module loads.
-
-dtoverlay=iqaudio-dacplus,auto_mute_amp
- Unmute amp when ALSA device opened by a client. Mute, with 5 second delay
- when ALSA device closed. (Re-opening the device within the 5 second close
- window, will cancel mute.)
-
-Revision 4, using gpiod.
-
-Revision 5, clean-up formatting before adding mute code.
- - Convert tab plus 4 space formatting to 2x tab
- - Remove '// NOT USED' commented code
-
-Revision 6, don't attempt to "one-shot" unmute amp, unless card is
-successfully registered.
-
-Signed-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
----
- sound/soc/bcm/Kconfig       |   7 ++
- sound/soc/bcm/Makefile      |   2 +
- sound/soc/bcm/iqaudio-dac.c | 239 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 248 insertions(+)
- create mode 100644 sound/soc/bcm/iqaudio-dac.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -38,3 +38,10 @@ config SND_BCM2708_SOC_RPI_DAC
-         select SND_SOC_PCM1794A
-         help
-          Say Y or M if you want to add support for RPi-DAC.
-+
-+config SND_BCM2708_SOC_IQAUDIO_DAC
-+	tristate "Support for IQaudIO-DAC"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM512x_I2C
-+	help
-+	  Say Y or M if you want to add support for IQaudIO-DAC.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -12,7 +12,9 @@ obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-
- snd-soc-hifiberry-dac-objs := hifiberry_dac.o
- snd-soc-hifiberry-digi-objs := hifiberry_digi.o
- snd-soc-rpi-dac-objs := rpi-dac.o
-+snd-soc-iqaudio-dac-objs := iqaudio-dac.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/iqaudio-dac.c
-@@ -0,0 +1,239 @@
-+/*
-+ * ASoC Driver for IQaudIO DAC
-+ *
-+ * Author:	Florian Meier <florian.meier@koalo.de>
-+ *		Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static bool digital_gain_0db_limit = true;
-+
-+static struct gpio_desc *mute_gpio;
-+
-+static int snd_rpi_iqaudio_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	if (digital_gain_0db_limit)
-+	{
-+		int ret;
-+		struct snd_soc_card *card = rtd->card;
-+
-+		ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_rpi_iqaudio_dac_hw_params(struct snd_pcm_substream *substream,
-+	struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+static void snd_rpi_iqaudio_gpio_mute(struct snd_soc_card *card)
-+{
-+	if (mute_gpio) {
-+		dev_info(card->dev, "%s: muting amp using GPIO22\n",
-+			 __func__);
-+		gpiod_set_value_cansleep(mute_gpio, 0);
-+	}
-+}
-+
-+static void snd_rpi_iqaudio_gpio_unmute(struct snd_soc_card *card)
-+{
-+	if (mute_gpio) {
-+		dev_info(card->dev, "%s: un-muting amp using GPIO22\n",
-+			 __func__);
-+		gpiod_set_value_cansleep(mute_gpio, 1);
-+	}
-+}
-+
-+static int snd_rpi_iqaudio_set_bias_level(struct snd_soc_card *card,
-+	struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)
-+{
-+	struct snd_soc_pcm_runtime *rtd;
-+	struct snd_soc_dai *codec_dai;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	codec_dai = rtd->codec_dai;
-+
-+	if (dapm->dev != codec_dai->dev)
-+		return 0;
-+
-+	switch (level) {
-+	case SND_SOC_BIAS_PREPARE:
-+		if (dapm->bias_level != SND_SOC_BIAS_STANDBY)
-+			break;
-+
-+		/* UNMUTE AMP */
-+		snd_rpi_iqaudio_gpio_unmute(card);
-+
-+		break;
-+	case SND_SOC_BIAS_STANDBY:
-+		if (dapm->bias_level != SND_SOC_BIAS_PREPARE)
-+			break;
-+
-+		/* MUTE AMP */
-+		snd_rpi_iqaudio_gpio_mute(card);
-+
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_iqaudio_dac_ops = {
-+	.hw_params = snd_rpi_iqaudio_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = {
-+{
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm512x-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm512x.1-004c",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_iqaudio_dac_ops,
-+	.init		= snd_rpi_iqaudio_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_iqaudio_dac = {
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_iqaudio_dac_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai),
-+};
-+
-+static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+	bool gpio_unmute = false;
-+
-+	snd_rpi_iqaudio_dac.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_card *card = &snd_rpi_iqaudio_dac;
-+		struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0];
-+		bool auto_gpio_mute = false;
-+
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					    "i2s-controller", 0);
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+
-+		digital_gain_0db_limit = !of_property_read_bool(
-+			pdev->dev.of_node, "iqaudio,24db_digital_gain");
-+
-+		if (of_property_read_string(pdev->dev.of_node, "card_name",
-+					    &card->name))
-+			card->name = "IQaudIODAC";
-+
-+		if (of_property_read_string(pdev->dev.of_node, "dai_name",
-+					    &dai->name))
-+			dai->name = "IQaudIO DAC";
-+
-+		if (of_property_read_string(pdev->dev.of_node,
-+					"dai_stream_name", &dai->stream_name))
-+			dai->stream_name = "IQaudIO DAC HiFi";
-+
-+		/* gpio_unmute - one time unmute amp using GPIO */
-+		gpio_unmute = of_property_read_bool(pdev->dev.of_node,
-+						    "iqaudio-dac,unmute-amp");
-+
-+		/* auto_gpio_mute - mute/unmute amp using GPIO */
-+		auto_gpio_mute = of_property_read_bool(pdev->dev.of_node,
-+						"iqaudio-dac,auto-mute-amp");
-+
-+		if (auto_gpio_mute || gpio_unmute) {
-+			mute_gpio = devm_gpiod_get_optional(&pdev->dev, "mute",
-+							    GPIOD_OUT_LOW);
-+			if (IS_ERR(mute_gpio)) {
-+				ret = PTR_ERR(mute_gpio);
-+				dev_err(&pdev->dev,
-+					"Failed to get mute gpio: %d\n", ret);
-+				return ret;
-+			}
-+
-+			if (auto_gpio_mute && mute_gpio)
-+				snd_rpi_iqaudio_dac.set_bias_level =
-+						snd_rpi_iqaudio_set_bias_level;
-+		}
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_iqaudio_dac);
-+	if (ret) {
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(&pdev->dev,
-+				"snd_soc_register_card() failed: %d\n", ret);
-+		return ret;
-+	}
-+
-+	if (gpio_unmute && mute_gpio)
-+		snd_rpi_iqaudio_gpio_unmute(&snd_rpi_iqaudio_dac);
-+
-+	return 0;
-+}
-+
-+static int snd_rpi_iqaudio_dac_remove(struct platform_device *pdev)
-+{
-+	snd_rpi_iqaudio_gpio_mute(&snd_rpi_iqaudio_dac);
-+
-+	return snd_soc_unregister_card(&snd_rpi_iqaudio_dac);
-+}
-+
-+static const struct of_device_id iqaudio_of_match[] = {
-+	{ .compatible = "iqaudio,iqaudio-dac", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, iqaudio_of_match);
-+
-+static struct platform_driver snd_rpi_iqaudio_dac_driver = {
-+	.driver = {
-+		.name   = "snd-rpi-iqaudio-dac",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = iqaudio_of_match,
-+	},
-+	.probe          = snd_rpi_iqaudio_dac_probe,
-+	.remove         = snd_rpi_iqaudio_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_iqaudio_dac_driver);
-+
-+MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
-+MODULE_DESCRIPTION("ASoC Driver for IQAudio DAC");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0069-Added-support-for-HiFiBerry-DAC.patch b/target/linux/brcm2708/patches-4.14/950-0069-Added-support-for-HiFiBerry-DAC.patch
deleted file mode 100644
index d588c7f49..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0069-Added-support-for-HiFiBerry-DAC.patch
+++ /dev/null
@@ -1,623 +0,0 @@
-From 24dce10447553c0c46db8aed95e7b8bd9ad63850 Mon Sep 17 00:00:00 2001
-From: Daniel Matuschek <info@crazy-audio.com>
-Date: Mon, 4 Aug 2014 10:06:56 +0200
-Subject: [PATCH 069/454] Added support for HiFiBerry DAC+
-
-The driver is based on the HiFiBerry DAC driver. However HiFiBerry DAC+ uses
-a different codec chip (PCM5122), therefore a new driver is necessary.
-
-Add support for the HiFiBerry DAC+ Pro.
-
-The HiFiBerry DAC+ and DAC+ Pro products both use the existing bcm sound driver with the DAC+ Pro having a special clock device driver representing the two high precision oscillators.
-
-An addition bug fix is included for the PCM512x codec where by the physical size of the sample frame is used in the calculation of the LRCK divisor as it was found to be wrong when using 24-bit depth sample contained in a little endian 4-byte sample frame.
-
-Limit PCM512x "Digital" gain to 0dB by default with HiFiBerry DAC+
-
-24db_digital_gain DT param can be used to specify that PCM512x
-codec "Digital" volume control should not be limited to 0dB gain,
-and if specified will allow the full 24dB gain.
-
-Add dt param to force HiFiBerry DAC+ Pro into slave mode
-
-"dtoverlay=hifiberry-dacplus,slave"
-
-Add 'slave' param to use HiFiBerry DAC+ Pro in slave mode,
-with Pi as master for bit and frame clock.
-
-Signed-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
-
-Fixed a bug when using 352.8kHz sample rate
-
-Signed-off-by: Daniel Matuschek <daniel@hifiberry.com>
----
- drivers/clk/Makefile               |   1 +
- drivers/clk/clk-hifiberry-dacpro.c | 160 +++++++++++++
- sound/soc/bcm/Kconfig              |   7 +
- sound/soc/bcm/Makefile             |   2 +
- sound/soc/bcm/hifiberry_dacplus.c  | 360 +++++++++++++++++++++++++++++
- sound/soc/codecs/pcm512x.c         |   3 +-
- 6 files changed, 532 insertions(+), 1 deletion(-)
- create mode 100644 drivers/clk/clk-hifiberry-dacpro.c
- create mode 100644 sound/soc/bcm/hifiberry_dacplus.c
-
---- a/drivers/clk/Makefile
-+++ b/drivers/clk/Makefile
-@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg
- obj-$(CONFIG_COMMON_CLK_GEMINI)		+= clk-gemini.o
- obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o
- obj-$(CONFIG_CLK_HSDK)			+= clk-hsdk-pll.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += clk-hifiberry-dacpro.o
- obj-$(CONFIG_COMMON_CLK_MAX77686)	+= clk-max77686.o
- obj-$(CONFIG_ARCH_MOXART)		+= clk-moxart.o
- obj-$(CONFIG_ARCH_NOMADIK)		+= clk-nomadik.o
---- /dev/null
-+++ b/drivers/clk/clk-hifiberry-dacpro.c
-@@ -0,0 +1,160 @@
-+/*
-+ * Clock Driver for HiFiBerry DAC Pro
-+ *
-+ * Author: Stuart MacLean
-+ *         Copyright 2015
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/clkdev.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/slab.h>
-+#include <linux/platform_device.h>
-+
-+/* Clock rate of CLK44EN attached to GPIO6 pin */
-+#define CLK_44EN_RATE 22579200UL
-+/* Clock rate of CLK48EN attached to GPIO3 pin */
-+#define CLK_48EN_RATE 24576000UL
-+
-+/**
-+ * struct hifiberry_dacpro_clk - Common struct to the HiFiBerry DAC Pro
-+ * @hw: clk_hw for the common clk framework
-+ * @mode: 0 => CLK44EN, 1 => CLK48EN
-+ */
-+struct clk_hifiberry_hw {
-+	struct clk_hw hw;
-+	uint8_t mode;
-+};
-+
-+#define to_hifiberry_clk(_hw) container_of(_hw, struct clk_hifiberry_hw, hw)
-+
-+static const struct of_device_id clk_hifiberry_dacpro_dt_ids[] = {
-+	{ .compatible = "hifiberry,dacpro-clk",},
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, clk_hifiberry_dacpro_dt_ids);
-+
-+static unsigned long clk_hifiberry_dacpro_recalc_rate(struct clk_hw *hw,
-+	unsigned long parent_rate)
-+{
-+	return (to_hifiberry_clk(hw)->mode == 0) ? CLK_44EN_RATE :
-+		CLK_48EN_RATE;
-+}
-+
-+static long clk_hifiberry_dacpro_round_rate(struct clk_hw *hw,
-+	unsigned long rate, unsigned long *parent_rate)
-+{
-+	long actual_rate;
-+
-+	if (rate <= CLK_44EN_RATE) {
-+		actual_rate = (long)CLK_44EN_RATE;
-+	} else if (rate >= CLK_48EN_RATE) {
-+		actual_rate = (long)CLK_48EN_RATE;
-+	} else {
-+		long diff44Rate = (long)(rate - CLK_44EN_RATE);
-+		long diff48Rate = (long)(CLK_48EN_RATE - rate);
-+
-+		if (diff44Rate < diff48Rate)
-+			actual_rate = (long)CLK_44EN_RATE;
-+		else
-+			actual_rate = (long)CLK_48EN_RATE;
-+	}
-+	return actual_rate;
-+}
-+
-+
-+static int clk_hifiberry_dacpro_set_rate(struct clk_hw *hw,
-+	unsigned long rate, unsigned long parent_rate)
-+{
-+	unsigned long actual_rate;
-+	struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw);
-+
-+	actual_rate = (unsigned long)clk_hifiberry_dacpro_round_rate(hw, rate,
-+		&parent_rate);
-+	clk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1;
-+	return 0;
-+}
-+
-+
-+const struct clk_ops clk_hifiberry_dacpro_rate_ops = {
-+	.recalc_rate = clk_hifiberry_dacpro_recalc_rate,
-+	.round_rate = clk_hifiberry_dacpro_round_rate,
-+	.set_rate = clk_hifiberry_dacpro_set_rate,
-+};
-+
-+static int clk_hifiberry_dacpro_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct clk_hifiberry_hw *proclk;
-+	struct clk *clk;
-+	struct device *dev;
-+	struct clk_init_data init;
-+
-+	dev = &pdev->dev;
-+
-+	proclk = kzalloc(sizeof(struct clk_hifiberry_hw), GFP_KERNEL);
-+	if (!proclk)
-+		return -ENOMEM;
-+
-+	init.name = "clk-hifiberry-dacpro";
-+	init.ops = &clk_hifiberry_dacpro_rate_ops;
-+	init.flags = CLK_IS_BASIC;
-+	init.parent_names = NULL;
-+	init.num_parents = 0;
-+
-+	proclk->mode = 0;
-+	proclk->hw.init = &init;
-+
-+	clk = devm_clk_register(dev, &proclk->hw);
-+	if (!IS_ERR(clk)) {
-+		ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
-+			clk);
-+	} else {
-+		dev_err(dev, "Fail to register clock driver\n");
-+		kfree(proclk);
-+		ret = PTR_ERR(clk);
-+	}
-+	return ret;
-+}
-+
-+static int clk_hifiberry_dacpro_remove(struct platform_device *pdev)
-+{
-+	of_clk_del_provider(pdev->dev.of_node);
-+	return 0;
-+}
-+
-+static struct platform_driver clk_hifiberry_dacpro_driver = {
-+	.probe = clk_hifiberry_dacpro_probe,
-+	.remove = clk_hifiberry_dacpro_remove,
-+	.driver = {
-+		.name = "clk-hifiberry-dacpro",
-+		.of_match_table = clk_hifiberry_dacpro_dt_ids,
-+	},
-+};
-+
-+static int __init clk_hifiberry_dacpro_init(void)
-+{
-+	return platform_driver_register(&clk_hifiberry_dacpro_driver);
-+}
-+core_initcall(clk_hifiberry_dacpro_init);
-+
-+static void __exit clk_hifiberry_dacpro_exit(void)
-+{
-+	platform_driver_unregister(&clk_hifiberry_dacpro_driver);
-+}
-+module_exit(clk_hifiberry_dacpro_exit);
-+
-+MODULE_DESCRIPTION("HiFiBerry DAC Pro clock driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:clk-hifiberry-dacpro");
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -25,6 +25,13 @@ config SND_BCM2708_SOC_HIFIBERRY_DAC
-         help
-          Say Y or M if you want to add support for HifiBerry DAC.
- 
-+config SND_BCM2708_SOC_HIFIBERRY_DACPLUS
-+        tristate "Support for HifiBerry DAC+"
-+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+        select SND_SOC_PCM512x
-+        help
-+         Say Y or M if you want to add support for HifiBerry DAC+.
-+
- config SND_BCM2708_SOC_HIFIBERRY_DIGI
-         tristate "Support for HifiBerry Digi"
-         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -10,11 +10,13 @@ obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-
- 
- # BCM2708 Machine Support
- snd-soc-hifiberry-dac-objs := hifiberry_dac.o
-+snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
- snd-soc-hifiberry-digi-objs := hifiberry_digi.o
- snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/hifiberry_dacplus.c
-@@ -0,0 +1,360 @@
-+/*
-+ * ASoC Driver for HiFiBerry DAC+ / DAC Pro
-+ *
-+ * Author:	Daniel Matuschek, Stuart MacLean <stuart@hifiberry.com>
-+ *		Copyright 2014-2015
-+ *		based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/kernel.h>
-+#include <linux/clk.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/slab.h>
-+#include <linux/delay.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/pcm512x.h"
-+
-+#define HIFIBERRY_DACPRO_NOCLOCK 0
-+#define HIFIBERRY_DACPRO_CLK44EN 1
-+#define HIFIBERRY_DACPRO_CLK48EN 2
-+
-+struct pcm512x_priv {
-+	struct regmap *regmap;
-+	struct clk *sclk;
-+};
-+
-+/* Clock rate of CLK44EN attached to GPIO6 pin */
-+#define CLK_44EN_RATE 22579200UL
-+/* Clock rate of CLK48EN attached to GPIO3 pin */
-+#define CLK_48EN_RATE 24576000UL
-+
-+static bool slave;
-+static bool snd_rpi_hifiberry_is_dacpro;
-+static bool digital_gain_0db_limit = true;
-+
-+static void snd_rpi_hifiberry_dacplus_select_clk(struct snd_soc_codec *codec,
-+	int clk_id)
-+{
-+	switch (clk_id) {
-+	case HIFIBERRY_DACPRO_NOCLOCK:
-+		snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x00);
-+		break;
-+	case HIFIBERRY_DACPRO_CLK44EN:
-+		snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x20);
-+		break;
-+	case HIFIBERRY_DACPRO_CLK48EN:
-+		snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x04);
-+		break;
-+	}
-+}
-+
-+static void snd_rpi_hifiberry_dacplus_clk_gpio(struct snd_soc_codec *codec)
-+{
-+	snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x24, 0x24);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02);
-+}
-+
-+static bool snd_rpi_hifiberry_dacplus_is_sclk(struct snd_soc_codec *codec)
-+{
-+	int sck;
-+
-+	sck = snd_soc_read(codec, PCM512x_RATE_DET_4);
-+	return (!(sck & 0x40));
-+}
-+
-+static bool snd_rpi_hifiberry_dacplus_is_sclk_sleep(
-+	struct snd_soc_codec *codec)
-+{
-+	msleep(2);
-+	return snd_rpi_hifiberry_dacplus_is_sclk(codec);
-+}
-+
-+static bool snd_rpi_hifiberry_dacplus_is_pro_card(struct snd_soc_codec *codec)
-+{
-+	bool isClk44EN, isClk48En, isNoClk;
-+
-+	snd_rpi_hifiberry_dacplus_clk_gpio(codec);
-+
-+	snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_CLK44EN);
-+	isClk44EN = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec);
-+
-+	snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_NOCLOCK);
-+	isNoClk = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec);
-+
-+	snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_CLK48EN);
-+	isClk48En = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec);
-+
-+	return (isClk44EN && isClk48En && !isNoClk);
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_clk_for_rate(int sample_rate)
-+{
-+	int type;
-+
-+	switch (sample_rate) {
-+	case 11025:
-+	case 22050:
-+	case 44100:
-+	case 88200:
-+	case 176400:
-+	case 352800:
-+		type = HIFIBERRY_DACPRO_CLK44EN;
-+		break;
-+	default:
-+		type = HIFIBERRY_DACPRO_CLK48EN;
-+		break;
-+	}
-+	return type;
-+}
-+
-+static void snd_rpi_hifiberry_dacplus_set_sclk(struct snd_soc_codec *codec,
-+	int sample_rate)
-+{
-+	struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
-+
-+	if (!IS_ERR(pcm512x->sclk)) {
-+		int ctype;
-+
-+		ctype = snd_rpi_hifiberry_dacplus_clk_for_rate(sample_rate);
-+		clk_set_rate(pcm512x->sclk, (ctype == HIFIBERRY_DACPRO_CLK44EN)
-+			? CLK_44EN_RATE : CLK_48EN_RATE);
-+		snd_rpi_hifiberry_dacplus_select_clk(codec, ctype);
-+	}
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct pcm512x_priv *priv;
-+
-+	if (slave)
-+		snd_rpi_hifiberry_is_dacpro = false;
-+	else
-+		snd_rpi_hifiberry_is_dacpro =
-+				snd_rpi_hifiberry_dacplus_is_pro_card(codec);
-+
-+	if (snd_rpi_hifiberry_is_dacpro) {
-+		struct snd_soc_dai_link *dai = rtd->dai_link;
-+
-+		dai->name = "HiFiBerry DAC+ Pro";
-+		dai->stream_name = "HiFiBerry DAC+ Pro HiFi";
-+		dai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
-+			| SND_SOC_DAIFMT_CBM_CFM;
-+
-+		snd_soc_update_bits(codec, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11);
-+		snd_soc_update_bits(codec, PCM512x_MASTER_MODE, 0x03, 0x03);
-+		snd_soc_update_bits(codec, PCM512x_MASTER_CLKDIV_2, 0x7f, 63);
-+	} else {
-+		priv = snd_soc_codec_get_drvdata(codec);
-+		priv->sclk = ERR_PTR(-ENOENT);
-+	}
-+
-+	snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);
-+
-+	if (digital_gain_0db_limit)
-+	{
-+		int ret;
-+		struct snd_soc_card *card = rtd->card;
-+
-+		ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_update_rate_den(
-+	struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
-+	struct snd_ratnum *rats_no_pll;
-+	unsigned int num = 0, den = 0;
-+	int err;
-+
-+	rats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL);
-+	if (!rats_no_pll)
-+		return -ENOMEM;
-+
-+	rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
-+	rats_no_pll->den_min = 1;
-+	rats_no_pll->den_max = 128;
-+	rats_no_pll->den_step = 1;
-+
-+	err = snd_interval_ratnum(hw_param_interval(params,
-+		SNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den);
-+	if (err >= 0 && den) {
-+		params->rate_num = num;
-+		params->rate_den = den;
-+	}
-+
-+	devm_kfree(rtd->dev, rats_no_pll);
-+	return 0;
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro(
-+	struct snd_soc_dai *cpu_dai, struct snd_pcm_hw_params *params)
-+{
-+	int bratio = snd_pcm_format_physical_width(params_format(params))
-+		* params_channels(params);
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, bratio);
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_hw_params(
-+	struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
-+{
-+	int ret;
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	if (snd_rpi_hifiberry_is_dacpro) {
-+		struct snd_soc_codec *codec = rtd->codec;
-+
-+		snd_rpi_hifiberry_dacplus_set_sclk(codec,
-+			params_rate(params));
-+
-+		ret = snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro(cpu_dai,
-+			params);
-+		if (!ret)
-+			ret = snd_rpi_hifiberry_dacplus_update_rate_den(
-+				substream, params);
-+	} else {
-+		ret = snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+	}
-+	return ret;
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_startup(
-+	struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);
-+	return 0;
-+}
-+
-+static void snd_rpi_hifiberry_dacplus_shutdown(
-+	struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_hifiberry_dacplus_ops = {
-+	.hw_params = snd_rpi_hifiberry_dacplus_hw_params,
-+	.startup = snd_rpi_hifiberry_dacplus_startup,
-+	.shutdown = snd_rpi_hifiberry_dacplus_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_dacplus_dai[] = {
-+{
-+	.name		= "HiFiBerry DAC+",
-+	.stream_name	= "HiFiBerry DAC+ HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm512x-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm512x.1-004d",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_hifiberry_dacplus_ops,
-+	.init		= snd_rpi_hifiberry_dacplus_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_hifiberry_dacplus = {
-+	.name         = "snd_rpi_hifiberry_dacplus",
-+	.driver_name  = "HifiberryDacp",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_hifiberry_dacplus_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_hifiberry_dacplus_dai),
-+};
-+
-+static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_hifiberry_dacplus.dev = &pdev->dev;
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai;
-+
-+		dai = &snd_rpi_hifiberry_dacplus_dai[0];
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+			"i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+
-+		digital_gain_0db_limit = !of_property_read_bool(
-+			pdev->dev.of_node, "hifiberry,24db_digital_gain");
-+		slave = of_property_read_bool(pdev->dev.of_node,
-+						"hifiberry-dacplus,slave");
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev,
-+			"snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus);
-+}
-+
-+static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = {
-+	{ .compatible = "hifiberry,hifiberry-dacplus", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match);
-+
-+static struct platform_driver snd_rpi_hifiberry_dacplus_driver = {
-+	.driver = {
-+		.name   = "snd-rpi-hifiberry-dacplus",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_rpi_hifiberry_dacplus_of_match,
-+	},
-+	.probe          = snd_rpi_hifiberry_dacplus_probe,
-+	.remove         = snd_rpi_hifiberry_dacplus_remove,
-+};
-+
-+module_platform_driver(snd_rpi_hifiberry_dacplus_driver);
-+
-+MODULE_AUTHOR("Daniel Matuschek <daniel@hifiberry.com>");
-+MODULE_DESCRIPTION("ASoC Driver for HiFiBerry DAC+");
-+MODULE_LICENSE("GPL v2");
---- a/sound/soc/codecs/pcm512x.c
-+++ b/sound/soc/codecs/pcm512x.c
-@@ -851,7 +851,8 @@ static int pcm512x_set_dividers(struct s
- 	int fssp;
- 	int gpio;
- 
--	lrclk_div = snd_soc_params_to_frame_size(params);
-+	lrclk_div = snd_pcm_format_physical_width(params_format(params))
-+		* params_channels(params);
- 	if (lrclk_div == 0) {
- 		dev_err(dev, "No LRCLK?\n");
- 		return -EINVAL;
diff --git a/target/linux/brcm2708/patches-4.14/950-0070-Added-driver-for-HiFiBerry-Amp-amplifier-add-on-boar.patch b/target/linux/brcm2708/patches-4.14/950-0070-Added-driver-for-HiFiBerry-Amp-amplifier-add-on-boar.patch
deleted file mode 100644
index 04fa21c40..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0070-Added-driver-for-HiFiBerry-Amp-amplifier-add-on-boar.patch
+++ /dev/null
@@ -1,820 +0,0 @@
-From afd0d9bcdc3f811b81246a02a697d42cb4803534 Mon Sep 17 00:00:00 2001
-From: Daniel Matuschek <info@crazy-audio.com>
-Date: Mon, 4 Aug 2014 11:09:58 +0200
-Subject: [PATCH 070/454] Added driver for HiFiBerry Amp amplifier add-on board
-
-The driver contains a low-level hardware driver for the TAS5713 and the
-drivers for the Raspberry Pi I2S subsystem.
-
-TAS5713: return error if initialisation fails
-
-Existing TAS5713 driver logs errors during initialisation, but does not return
-an error code. Therefore even if initialisation fails, the driver will still be
-loaded, but won't work. This patch fixes this. I2C communication error will now
-reported correctly by a non-zero return code.
-
-HiFiBerry Amp: fix device-tree problems
-
-Some code to load the driver based on device-tree-overlays was missing. This is added by this patch.
----
- sound/soc/bcm/Kconfig         |   7 +
- sound/soc/bcm/Makefile        |   2 +
- sound/soc/bcm/hifiberry_amp.c | 128 ++++++++++++
- sound/soc/codecs/Kconfig      |   4 +
- sound/soc/codecs/Makefile     |   2 +
- sound/soc/codecs/tas5713.c    | 371 ++++++++++++++++++++++++++++++++++
- sound/soc/codecs/tas5713.h    | 210 +++++++++++++++++++
- 7 files changed, 724 insertions(+)
- create mode 100644 sound/soc/bcm/hifiberry_amp.c
- create mode 100644 sound/soc/codecs/tas5713.c
- create mode 100644 sound/soc/codecs/tas5713.h
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -39,6 +39,13 @@ config SND_BCM2708_SOC_HIFIBERRY_DIGI
-         help
-          Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board.
- 
-+config SND_BCM2708_SOC_HIFIBERRY_AMP
-+        tristate "Support for the HifiBerry Amp"
-+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+        select SND_SOC_TAS5713
-+        help
-+         Say Y or M if you want to add support for the HifiBerry Amp amplifier board.
-+
- config SND_BCM2708_SOC_RPI_DAC
-         tristate "Support for RPi-DAC"
-         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -9,12 +9,14 @@ snd-soc-cygnus-objs := cygnus-pcm.o cygn
- obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-cygnus.o
- 
- # BCM2708 Machine Support
-+snd-soc-hifiberry-amp-objs := hifiberry_amp.o
- snd-soc-hifiberry-dac-objs := hifiberry_dac.o
- snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
- snd-soc-hifiberry-digi-objs := hifiberry_digi.o
- snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
- 
-+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
---- /dev/null
-+++ b/sound/soc/bcm/hifiberry_amp.c
-@@ -0,0 +1,128 @@
-+/*
-+ * ASoC Driver for HifiBerry AMP
-+ *
-+ * Author:	Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ *		Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_hifiberry_amp_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	// ToDo: init of the dsp-registers.
-+	return 0;
-+}
-+
-+static int snd_rpi_hifiberry_amp_hw_params( struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params )
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+}
-+
-+static struct snd_soc_ops snd_rpi_hifiberry_amp_ops = {
-+	.hw_params = snd_rpi_hifiberry_amp_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_hifiberry_amp_dai[] = {
-+    {
-+		.name			= "HifiBerry AMP",
-+		.stream_name	= "HifiBerry AMP HiFi",
-+		.cpu_dai_name	= "bcm2708-i2s.0",
-+		.codec_dai_name	= "tas5713-hifi",
-+		.platform_name	= "bcm2708-i2s.0",
-+		.codec_name		= "tas5713.1-001b",
-+		.dai_fmt		= SND_SOC_DAIFMT_I2S |
-+						  SND_SOC_DAIFMT_NB_NF |
-+						  SND_SOC_DAIFMT_CBS_CFS,
-+		.ops			= &snd_rpi_hifiberry_amp_ops,
-+		.init			= snd_rpi_hifiberry_amp_init,
-+	},
-+};
-+
-+
-+static struct snd_soc_card snd_rpi_hifiberry_amp = {
-+	.name         = "snd_rpi_hifiberry_amp",
-+	.driver_name  = "HifiberryAmp",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_hifiberry_amp_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_hifiberry_amp_dai),
-+};
-+
-+static const struct of_device_id snd_rpi_hifiberry_amp_of_match[] = {
-+        { .compatible = "hifiberry,hifiberry-amp", },
-+        {},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_amp_of_match);
-+
-+
-+static int snd_rpi_hifiberry_amp_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_hifiberry_amp.dev = &pdev->dev;
-+
-+        if (pdev->dev.of_node) {
-+            struct device_node *i2s_node;
-+            struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_amp_dai[0];
-+            i2s_node = of_parse_phandle(pdev->dev.of_node,
-+                                        "i2s-controller", 0);
-+
-+            if (i2s_node) {
-+                dai->cpu_dai_name = NULL;
-+                dai->cpu_of_node = i2s_node;
-+                dai->platform_name = NULL;
-+                dai->platform_of_node = i2s_node;
-+            }
-+        }
-+
-+	ret = snd_soc_register_card(&snd_rpi_hifiberry_amp);
-+
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+
-+static int snd_rpi_hifiberry_amp_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_hifiberry_amp);
-+}
-+
-+
-+static struct platform_driver snd_rpi_hifiberry_amp_driver = {
-+        .driver = {
-+                .name   = "snd-hifiberry-amp",
-+                .owner  = THIS_MODULE,
-+		.of_match_table = snd_rpi_hifiberry_amp_of_match,
-+        },
-+        .probe          = snd_rpi_hifiberry_amp_probe,
-+        .remove         = snd_rpi_hifiberry_amp_remove,
-+};
-+
-+
-+module_platform_driver(snd_rpi_hifiberry_amp_driver);
-+
-+
-+MODULE_AUTHOR("Sebastian Eickhoff <basti.eickhoff@googlemail.com>");
-+MODULE_DESCRIPTION("ASoC driver for HiFiBerry-AMP");
-+MODULE_LICENSE("GPL v2");
---- a/sound/soc/codecs/Kconfig
-+++ b/sound/soc/codecs/Kconfig
-@@ -152,6 +152,7 @@ config SND_SOC_ALL_CODECS
- 	select SND_SOC_TFA9879 if I2C
- 	select SND_SOC_TLV320AIC23_I2C if I2C
- 	select SND_SOC_TLV320AIC23_SPI if SPI_MASTER
-+	select SND_SOC_TAS5713 if I2C
- 	select SND_SOC_TLV320AIC26 if SPI_MASTER
- 	select SND_SOC_TLV320AIC31XX if I2C
- 	select SND_SOC_TLV320AIC32X4_I2C if I2C
-@@ -888,6 +889,9 @@ config SND_SOC_TFA9879
- 	tristate "NXP Semiconductors TFA9879 amplifier"
- 	depends on I2C
- 
-+config SND_SOC_TAS5713
-+	tristate
-+
- config SND_SOC_TLV320AIC23
- 	tristate
- 
---- a/sound/soc/codecs/Makefile
-+++ b/sound/soc/codecs/Makefile
-@@ -158,6 +158,7 @@ snd-soc-tas5086-objs := tas5086.o
- snd-soc-tas571x-objs := tas571x.o
- snd-soc-tas5720-objs := tas5720.o
- snd-soc-tfa9879-objs := tfa9879.o
-+snd-soc-tas5713-objs := tas5713.o
- snd-soc-tlv320aic23-objs := tlv320aic23.o
- snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o
- snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o
-@@ -397,6 +398,7 @@ obj-$(CONFIG_SND_SOC_TAS5086)	+= snd-soc
- obj-$(CONFIG_SND_SOC_TAS571X)	+= snd-soc-tas571x.o
- obj-$(CONFIG_SND_SOC_TAS5720)	+= snd-soc-tas5720.o
- obj-$(CONFIG_SND_SOC_TFA9879)	+= snd-soc-tfa9879.o
-+obj-$(CONFIG_SND_SOC_TAS5713)	+= snd-soc-tas5713.o
- obj-$(CONFIG_SND_SOC_TLV320AIC23)	+= snd-soc-tlv320aic23.o
- obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C)	+= snd-soc-tlv320aic23-i2c.o
- obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI)	+= snd-soc-tlv320aic23-spi.o
---- /dev/null
-+++ b/sound/soc/codecs/tas5713.c
-@@ -0,0 +1,371 @@
-+/*
-+ * ASoC Driver for TAS5713
-+ *
-+ * Author:	Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ *		Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/pm.h>
-+#include <linux/i2c.h>
-+#include <linux/of_device.h>
-+#include <linux/spi/spi.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/slab.h>
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/initval.h>
-+#include <sound/tlv.h>
-+
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/fs.h>
-+#include <asm/uaccess.h>
-+
-+#include "tas5713.h"
-+
-+
-+static struct i2c_client *i2c;
-+
-+struct tas5713_priv {
-+	struct regmap *regmap;
-+	int mclk_div;
-+	struct snd_soc_codec *codec;
-+};
-+
-+static struct tas5713_priv *priv_data;
-+
-+
-+
-+
-+/*
-+ *    _   _    ___   _      ___         _           _
-+ *   /_\ | |  / __| /_\    / __|___ _ _| |_ _ _ ___| |___
-+ *  / _ \| |__\__ \/ _ \  | (__/ _ \ ' \  _| '_/ _ \ (_-<
-+ * /_/ \_\____|___/_/ \_\  \___\___/_||_\__|_| \___/_/__/
-+ *
-+ */
-+
-+static const DECLARE_TLV_DB_SCALE(tas5713_vol_tlv, -10000, 50, 1);
-+
-+
-+static const struct snd_kcontrol_new tas5713_snd_controls[] = {
-+	SOC_SINGLE_TLV  ("Master"    , TAS5713_VOL_MASTER, 0, 248, 1, tas5713_vol_tlv),
-+	SOC_DOUBLE_R_TLV("Channels"  , TAS5713_VOL_CH1, TAS5713_VOL_CH2, 0, 248, 1, tas5713_vol_tlv)
-+};
-+
-+
-+
-+
-+/*
-+ *  __  __         _    _            ___      _
-+ * |  \/  |__ _ __| |_ (_)_ _  ___  |   \ _ _(_)_ _____ _ _
-+ * | |\/| / _` / _| ' \| | ' \/ -_) | |) | '_| \ V / -_) '_|
-+ * |_|  |_\__,_\__|_||_|_|_||_\___| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static int tas5713_hw_params(struct snd_pcm_substream *substream,
-+			    struct snd_pcm_hw_params *params,
-+			    struct snd_soc_dai *dai)
-+{
-+	u16 blen = 0x00;
-+
-+	struct snd_soc_codec *codec;
-+	codec = dai->codec;
-+	priv_data->codec = dai->codec;
-+
-+	switch (params_format(params)) {
-+	case SNDRV_PCM_FORMAT_S16_LE:
-+		blen = 0x03;
-+		break;
-+	case SNDRV_PCM_FORMAT_S20_3LE:
-+		blen = 0x1;
-+		break;
-+	case SNDRV_PCM_FORMAT_S24_LE:
-+		blen = 0x04;
-+		break;
-+	case SNDRV_PCM_FORMAT_S32_LE:
-+		blen = 0x05;
-+		break;
-+	default:
-+		dev_err(dai->dev, "Unsupported word length: %u\n",
-+			params_format(params));
-+		return -EINVAL;
-+	}
-+
-+	// set word length
-+	snd_soc_update_bits(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x7, blen);
-+
-+	return 0;
-+}
-+
-+
-+static int tas5713_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
-+{
-+	unsigned int val = 0;
-+
-+	struct tas5713_priv *tas5713;
-+	struct snd_soc_codec *codec = dai->codec;
-+	tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+	if (mute) {
-+		val = TAS5713_SOFT_MUTE_ALL;
-+	}
-+
-+	return regmap_write(tas5713->regmap, TAS5713_SOFT_MUTE, val);
-+}
-+
-+
-+static const struct snd_soc_dai_ops tas5713_dai_ops = {
-+	.hw_params 		= tas5713_hw_params,
-+	.mute_stream	= tas5713_mute_stream,
-+};
-+
-+
-+static struct snd_soc_dai_driver tas5713_dai = {
-+	.name		= "tas5713-hifi",
-+	.playback 	= {
-+		.stream_name	= "Playback",
-+		.channels_min	= 2,
-+		.channels_max	= 2,
-+		.rates		    = SNDRV_PCM_RATE_8000_48000,
-+		.formats	    = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE ),
-+	},
-+	.ops        = &tas5713_dai_ops,
-+};
-+
-+
-+
-+
-+/*
-+ *   ___         _          ___      _
-+ *  / __|___  __| |___ __  |   \ _ _(_)_ _____ _ _
-+ * | (__/ _ \/ _` / -_) _| | |) | '_| \ V / -_) '_|
-+ *  \___\___/\__,_\___\__| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static int tas5713_remove(struct snd_soc_codec *codec)
-+{
-+	struct tas5713_priv *tas5713;
-+
-+	tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+	return 0;
-+}
-+
-+
-+static int tas5713_probe(struct snd_soc_codec *codec)
-+{
-+	struct tas5713_priv *tas5713;
-+	int i, ret;
-+
-+	i2c = container_of(codec->dev, struct i2c_client, dev);
-+
-+	tas5713 = snd_soc_codec_get_drvdata(codec);
-+
-+	// Reset error
-+	ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00);
-+	if (ret < 0) return ret;
-+
-+	// Trim oscillator
-+	ret = snd_soc_write(codec, TAS5713_OSC_TRIM, 0x00);
-+	if (ret < 0) return ret;
-+	msleep(1000);
-+
-+	// Reset error
-+	ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00);
-+	if (ret < 0) return ret;
-+
-+	// Clock mode: 44/48kHz, MCLK=64xfs
-+	ret = snd_soc_write(codec, TAS5713_CLOCK_CTRL, 0x60);
-+	if (ret < 0) return ret;
-+
-+	// I2S 24bit
-+	ret = snd_soc_write(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x05);
-+	if (ret < 0) return ret;
-+
-+	// Unmute
-+	ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00);
-+	if (ret < 0) return ret;
-+	ret = snd_soc_write(codec, TAS5713_SOFT_MUTE, 0x00);
-+	if (ret < 0) return ret;
-+
-+	// Set volume to 0db
-+	ret = snd_soc_write(codec, TAS5713_VOL_MASTER, 0x00);
-+	if (ret < 0) return ret;
-+
-+	// Now start programming the default initialization sequence
-+	for (i = 0; i < ARRAY_SIZE(tas5713_init_sequence); ++i) {
-+		ret = i2c_master_send(i2c,
-+				     tas5713_init_sequence[i].data,
-+				     tas5713_init_sequence[i].size);
-+		if (ret < 0) {
-+			printk(KERN_INFO "TAS5713 CODEC PROBE: InitSeq returns: %d\n", ret);
-+		}
-+	}
-+
-+	// Unmute
-+	ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00);
-+	if (ret < 0) return ret;
-+
-+	return 0;
-+}
-+
-+
-+static struct snd_soc_codec_driver soc_codec_dev_tas5713 = {
-+	.probe = tas5713_probe,
-+	.remove = tas5713_remove,
-+	.component_driver = {
-+		.controls = tas5713_snd_controls,
-+		.num_controls = ARRAY_SIZE(tas5713_snd_controls),
-+	},
-+};
-+
-+
-+
-+
-+/*
-+ *   ___ ___ ___   ___      _
-+ *  |_ _|_  ) __| |   \ _ _(_)_ _____ _ _
-+ *   | | / / (__  | |) | '_| \ V / -_) '_|
-+ *  |___/___\___| |___/|_| |_|\_/\___|_|
-+ *
-+ */
-+
-+static const struct reg_default tas5713_reg_defaults[] = {
-+	{ 0x07 ,0x80 },     // R7  - VOL_MASTER    - -40dB
-+	{ 0x08 ,  30 },     // R8  - VOL_CH1	   -   0dB
-+	{ 0x09 ,  30 },     // R9  - VOL_CH2       -   0dB
-+	{ 0x0A ,0x80 },     // R10 - VOL_HEADPHONE - -40dB
-+};
-+
-+
-+static bool tas5713_reg_volatile(struct device *dev, unsigned int reg)
-+{
-+	switch (reg) {
-+		case TAS5713_DEVICE_ID:
-+		case TAS5713_ERROR_STATUS:
-+			return true;
-+	default:
-+			return false;
-+	}
-+}
-+
-+
-+static const struct of_device_id tas5713_of_match[] = {
-+	{ .compatible = "ti,tas5713", },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, tas5713_of_match);
-+
-+
-+static struct regmap_config tas5713_regmap_config = {
-+	.reg_bits = 8,
-+	.val_bits = 8,
-+
-+	.max_register = TAS5713_MAX_REGISTER,
-+	.volatile_reg = tas5713_reg_volatile,
-+
-+	.cache_type = REGCACHE_RBTREE,
-+	.reg_defaults = tas5713_reg_defaults,
-+	.num_reg_defaults = ARRAY_SIZE(tas5713_reg_defaults),
-+};
-+
-+
-+static int tas5713_i2c_probe(struct i2c_client *i2c,
-+			    const struct i2c_device_id *id)
-+{
-+	int ret;
-+
-+	priv_data = devm_kzalloc(&i2c->dev, sizeof *priv_data, GFP_KERNEL);
-+	if (!priv_data)
-+		return -ENOMEM;
-+
-+	priv_data->regmap = devm_regmap_init_i2c(i2c, &tas5713_regmap_config);
-+	if (IS_ERR(priv_data->regmap)) {
-+		ret = PTR_ERR(priv_data->regmap);
-+		return ret;
-+	}
-+
-+	i2c_set_clientdata(i2c, priv_data);
-+
-+	ret = snd_soc_register_codec(&i2c->dev,
-+				     &soc_codec_dev_tas5713, &tas5713_dai, 1);
-+
-+	return ret;
-+}
-+
-+
-+static int tas5713_i2c_remove(struct i2c_client *i2c)
-+{
-+	snd_soc_unregister_codec(&i2c->dev);
-+	i2c_set_clientdata(i2c, NULL);
-+
-+	kfree(priv_data);
-+
-+	return 0;
-+}
-+
-+
-+static const struct i2c_device_id tas5713_i2c_id[] = {
-+	{ "tas5713", 0 },
-+	{ }
-+};
-+
-+MODULE_DEVICE_TABLE(i2c, tas5713_i2c_id);
-+
-+
-+static struct i2c_driver tas5713_i2c_driver = {
-+	.driver = {
-+		.name = "tas5713",
-+		.owner = THIS_MODULE,
-+		.of_match_table = tas5713_of_match,
-+	},
-+	.probe = tas5713_i2c_probe,
-+	.remove = tas5713_i2c_remove,
-+	.id_table = tas5713_i2c_id
-+};
-+
-+
-+static int __init tas5713_modinit(void)
-+{
-+	int ret = 0;
-+
-+	ret = i2c_add_driver(&tas5713_i2c_driver);
-+	if (ret) {
-+		printk(KERN_ERR "Failed to register tas5713 I2C driver: %d\n",
-+		       ret);
-+	}
-+
-+	return ret;
-+}
-+module_init(tas5713_modinit);
-+
-+
-+static void __exit tas5713_exit(void)
-+{
-+	i2c_del_driver(&tas5713_i2c_driver);
-+}
-+module_exit(tas5713_exit);
-+
-+
-+MODULE_AUTHOR("Sebastian Eickhoff <basti.eickhoff@googlemail.com>");
-+MODULE_DESCRIPTION("ASoC driver for TAS5713");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/sound/soc/codecs/tas5713.h
-@@ -0,0 +1,210 @@
-+/*
-+ * ASoC Driver for TAS5713
-+ *
-+ * Author:      Sebastian Eickhoff <basti.eickhoff@googlemail.com>
-+ *              Copyright 2014
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#ifndef _TAS5713_H
-+#define _TAS5713_H
-+
-+
-+// TAS5713 I2C-bus register addresses
-+
-+#define TAS5713_CLOCK_CTRL              0x00
-+#define TAS5713_DEVICE_ID               0x01
-+#define TAS5713_ERROR_STATUS            0x02
-+#define TAS5713_SYSTEM_CTRL1            0x03
-+#define TAS5713_SERIAL_DATA_INTERFACE   0x04
-+#define TAS5713_SYSTEM_CTRL2            0x05
-+#define TAS5713_SOFT_MUTE               0x06
-+#define TAS5713_VOL_MASTER              0x07
-+#define TAS5713_VOL_CH1                 0x08
-+#define TAS5713_VOL_CH2                 0x09
-+#define TAS5713_VOL_HEADPHONE           0x0A
-+#define TAS5713_VOL_CONFIG              0x0E
-+#define TAS5713_MODULATION_LIMIT        0x10
-+#define TAS5713_IC_DLY_CH1              0x11
-+#define TAS5713_IC_DLY_CH2              0x12
-+#define TAS5713_IC_DLY_CH3              0x13
-+#define TAS5713_IC_DLY_CH4              0x14
-+
-+#define TAS5713_START_STOP_PERIOD       0x1A
-+#define TAS5713_OSC_TRIM                0x1B
-+#define TAS5713_BKND_ERR                0x1C
-+
-+#define TAS5713_INPUT_MUX               0x20
-+#define TAS5713_SRC_SELECT_CH4          0x21
-+#define TAS5713_PWM_MUX                 0x25
-+
-+#define TAS5713_CH1_BQ0                 0x29
-+#define TAS5713_CH1_BQ1                 0x2A
-+#define TAS5713_CH1_BQ2                 0x2B
-+#define TAS5713_CH1_BQ3                 0x2C
-+#define TAS5713_CH1_BQ4                 0x2D
-+#define TAS5713_CH1_BQ5                 0x2E
-+#define TAS5713_CH1_BQ6                 0x2F
-+#define TAS5713_CH1_BQ7                 0x58
-+#define TAS5713_CH1_BQ8                 0x59
-+
-+#define TAS5713_CH2_BQ0                 0x30
-+#define TAS5713_CH2_BQ1                 0x31
-+#define TAS5713_CH2_BQ2                 0x32
-+#define TAS5713_CH2_BQ3                 0x33
-+#define TAS5713_CH2_BQ4                 0x34
-+#define TAS5713_CH2_BQ5                 0x35
-+#define TAS5713_CH2_BQ6                 0x36
-+#define TAS5713_CH2_BQ7                 0x5C
-+#define TAS5713_CH2_BQ8                 0x5D
-+
-+#define TAS5713_CH4_BQ0                 0x5A
-+#define TAS5713_CH4_BQ1                 0x5B
-+#define TAS5713_CH3_BQ0                 0x5E
-+#define TAS5713_CH3_BQ1                 0x5F
-+
-+#define TAS5713_DRC1_SOFTENING_FILTER_ALPHA_OMEGA       0x3B
-+#define TAS5713_DRC1_ATTACK_RELEASE_RATE                0x3C
-+#define TAS5713_DRC2_SOFTENING_FILTER_ALPHA_OMEGA       0x3E
-+#define TAS5713_DRC2_ATTACK_RELEASE_RATE                0x3F
-+#define TAS5713_DRC1_ATTACK_RELEASE_THRES               0x40
-+#define TAS5713_DRC2_ATTACK_RELEASE_THRES               0x43
-+#define TAS5713_DRC_CTRL                                0x46
-+
-+#define TAS5713_BANK_SW_CTRL            0x50
-+#define TAS5713_CH1_OUTPUT_MIXER        0x51
-+#define TAS5713_CH2_OUTPUT_MIXER        0x52
-+#define TAS5713_CH1_INPUT_MIXER         0x53
-+#define TAS5713_CH2_INPUT_MIXER         0x54
-+#define TAS5713_OUTPUT_POST_SCALE       0x56
-+#define TAS5713_OUTPUT_PRESCALE         0x57
-+
-+#define TAS5713_IDF_POST_SCALE          0x62
-+
-+#define TAS5713_CH1_INLINE_MIXER        0x70
-+#define TAS5713_CH1_INLINE_DRC_EN_MIXER 0x71
-+#define TAS5713_CH1_R_CHANNEL_MIXER     0x72
-+#define TAS5713_CH1_L_CHANNEL_MIXER     0x73
-+#define TAS5713_CH2_INLINE_MIXER        0x74
-+#define TAS5713_CH2_INLINE_DRC_EN_MIXER 0x75
-+#define TAS5713_CH2_L_CHANNEL_MIXER     0x76
-+#define TAS5713_CH2_R_CHANNEL_MIXER     0x77
-+
-+#define TAS5713_UPDATE_DEV_ADDR_KEY     0xF8
-+#define TAS5713_UPDATE_DEV_ADDR_REG     0xF9
-+
-+#define TAS5713_REGISTER_COUNT          0x46
-+#define TAS5713_MAX_REGISTER            0xF9
-+
-+
-+// Bitmasks for registers
-+#define TAS5713_SOFT_MUTE_ALL           0x07
-+
-+
-+
-+struct tas5713_init_command {
-+        const int size;
-+        const char *const data;
-+};
-+
-+static const struct tas5713_init_command tas5713_init_sequence[] = {
-+
-+        // Trim oscillator
-+    { .size = 2,  .data = "\x1B\x00" },
-+    // System control register 1 (0x03): block DC
-+    { .size = 2,  .data = "\x03\x80" },
-+    // Mute everything
-+    { .size = 2,  .data = "\x05\x40" },
-+    // Modulation limit register (0x10): 97.7%
-+    { .size = 2,  .data = "\x10\x02" },
-+    // Interchannel delay registers
-+    // (0x11, 0x12, 0x13, and 0x14): BD mode
-+    { .size = 2,  .data = "\x11\xB8" },
-+    { .size = 2,  .data = "\x12\x60" },
-+    { .size = 2,  .data = "\x13\xA0" },
-+    { .size = 2,  .data = "\x14\x48" },
-+    // PWM shutdown group register (0x19): no shutdown
-+    { .size = 2,  .data = "\x19\x00" },
-+    // Input multiplexer register (0x20): BD mode
-+    { .size = 2,  .data = "\x20\x00\x89\x77\x72" },
-+    // PWM output mux register (0x25)
-+    // Channel 1 --> OUTA, channel 1 neg --> OUTB
-+    // Channel 2 --> OUTC, channel 2 neg --> OUTD
-+    { .size = 5,  .data = "\x25\x01\x02\x13\x45" },
-+    // DRC control (0x46): DRC off
-+    { .size = 5,  .data = "\x46\x00\x00\x00\x00" },
-+    // BKND_ERR register (0x1C): 299ms reset period
-+    { .size = 2,  .data = "\x1C\x07" },
-+    // Mute channel 3
-+    { .size = 2,  .data = "\x0A\xFF" },
-+    // Volume configuration register (0x0E): volume slew 512 steps
-+    { .size = 2,  .data = "\x0E\x90" },
-+    // Clock control register (0x00): 44/48kHz, MCLK=64xfs
-+    { .size = 2,  .data = "\x00\x60" },
-+    // Bank switch and eq control (0x50): no bank switching
-+    { .size = 5,  .data = "\x50\x00\x00\x00\x00" },
-+    // Volume registers (0x07, 0x08, 0x09, 0x0A)
-+    { .size = 2,  .data = "\x07\x20" },
-+    { .size = 2,  .data = "\x08\x30" },
-+    { .size = 2,  .data = "\x09\x30" },
-+    { .size = 2,  .data = "\x0A\xFF" },
-+    // 0x72, 0x73, 0x76, 0x77 input mixer:
-+    // no intermix between channels
-+    { .size = 5,  .data = "\x72\x00\x00\x00\x00" },
-+    { .size = 5,  .data = "\x73\x00\x80\x00\x00" },
-+    { .size = 5,  .data = "\x76\x00\x00\x00\x00" },
-+    { .size = 5,  .data = "\x77\x00\x80\x00\x00" },
-+    // 0x70, 0x71, 0x74, 0x75 inline DRC mixer:
-+    // no inline DRC inmix
-+    { .size = 5,  .data = "\x70\x00\x80\x00\x00" },
-+    { .size = 5,  .data = "\x71\x00\x00\x00\x00" },
-+    { .size = 5,  .data = "\x74\x00\x80\x00\x00" },
-+    { .size = 5,  .data = "\x75\x00\x00\x00\x00" },
-+    // 0x56, 0x57 Output scale
-+    { .size = 5,  .data = "\x56\x00\x80\x00\x00" },
-+    { .size = 5,  .data = "\x57\x00\x02\x00\x00" },
-+    // 0x3B, 0x3c
-+    { .size = 9,  .data = "\x3B\x00\x08\x00\x00\x00\x78\x00\x00" },
-+    { .size = 9,  .data = "\x3C\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+    { .size = 9,  .data = "\x3E\x00\x08\x00\x00\x00\x78\x00\x00" },
-+    { .size = 9,  .data = "\x3F\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+    { .size = 9,  .data = "\x40\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+    { .size = 9,  .data = "\x43\x00\x00\x01\x00\xFF\xFF\xFF\x00" },
-+    // 0x51, 0x52: output mixer
-+    { .size = 9,  .data = "\x51\x00\x80\x00\x00\x00\x00\x00\x00" },
-+    { .size = 9,  .data = "\x52\x00\x80\x00\x00\x00\x00\x00\x00" },
-+    // PEQ defaults
-+    { .size = 21,  .data = "\x29\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x2A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x2B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x2C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x2D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x2E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x2F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x30\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x31\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x32\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x33\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x34\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x35\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x36\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x58\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x59\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x5C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x5D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x5E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x5F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x5A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+    { .size = 21,  .data = "\x5B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" },
-+};
-+
-+
-+#endif  /* _TAS5713_H */
diff --git a/target/linux/brcm2708/patches-4.14/950-0071-Add-driver-for-rpi-proto.patch b/target/linux/brcm2708/patches-4.14/950-0071-Add-driver-for-rpi-proto.patch
deleted file mode 100644
index bf0775e43..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0071-Add-driver-for-rpi-proto.patch
+++ /dev/null
@@ -1,210 +0,0 @@
-From 02c03307c0ba3108e22b12066ac681194b4d22e0 Mon Sep 17 00:00:00 2001
-From: Waldemar Brodkorb <wbrodkorb@conet.de>
-Date: Wed, 25 Mar 2015 09:26:17 +0100
-Subject: [PATCH 071/454] Add driver for rpi-proto
-
-Forward port of 3.10.x driver from https://github.com/koalo
-We are using a custom board and would like to use rpi 3.18.x
-kernel. Patch works fine for our embedded system.
-
-URL to the audio chip:
-http://www.mikroe.com/add-on-boards/audio-voice/audio-codec-proto/
-
-Playback tested with devicetree enabled.
-
-Signed-off-by: Waldemar Brodkorb <wbrodkorb@conet.de>
----
- sound/soc/bcm/Kconfig     |   7 ++
- sound/soc/bcm/Makefile    |   2 +
- sound/soc/bcm/rpi-proto.c | 153 ++++++++++++++++++++++++++++++++++++++
- 3 files changed, 162 insertions(+)
- create mode 100644 sound/soc/bcm/rpi-proto.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -53,6 +53,13 @@ config SND_BCM2708_SOC_RPI_DAC
-         help
-          Say Y or M if you want to add support for RPi-DAC.
- 
-+config SND_BCM2708_SOC_RPI_PROTO
-+	tristate "Support for Rpi-PROTO"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_WM8731
-+	help
-+	  Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731).
-+
- config SND_BCM2708_SOC_IQAUDIO_DAC
- 	tristate "Support for IQaudIO-DAC"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -14,6 +14,7 @@ snd-soc-hifiberry-dac-objs := hifiberry_
- snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
- snd-soc-hifiberry-digi-objs := hifiberry_digi.o
- snd-soc-rpi-dac-objs := rpi-dac.o
-+snd-soc-rpi-proto-objs := rpi-proto.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-@@ -21,4 +22,5 @@ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_D
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/rpi-proto.c
-@@ -0,0 +1,153 @@
-+/*
-+ * ASoC driver for PROTO AudioCODEC (with a WM8731)
-+ * connected to a Raspberry Pi
-+ *
-+ * Author:      Florian Meier, <koalo@koalo.de>
-+ *	      Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/wm8731.h"
-+
-+static const unsigned int wm8731_rates_12288000[] = {
-+	8000, 32000, 48000, 96000,
-+};
-+
-+static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = {
-+	.list = wm8731_rates_12288000,
-+	.count = ARRAY_SIZE(wm8731_rates_12288000),
-+};
-+
-+static int snd_rpi_proto_startup(struct snd_pcm_substream *substream)
-+{
-+	/* Setup constraints, because there is a 12.288 MHz XTAL on the board */
-+	snd_pcm_hw_constraint_list(substream->runtime, 0,
-+				SNDRV_PCM_HW_PARAM_RATE,
-+				&wm8731_constraints_12288000);
-+	return 0;
-+}
-+
-+static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+	int sysclk = 12288000; /* This is fixed on this board */
-+
-+	/* Set proto bclk */
-+	int ret = snd_soc_dai_set_bclk_ratio(cpu_dai,32*2);
-+	if (ret < 0){
-+		dev_err(codec->dev,
-+				"Failed to set BCLK ratio %d\n", ret);
-+		return ret;
-+	}
-+
-+	/* Set proto sysclk */
-+	ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
-+			sysclk, SND_SOC_CLOCK_IN);
-+	if (ret < 0) {
-+		dev_err(codec->dev,
-+				"Failed to set WM8731 SYSCLK: %d\n", ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_proto_ops = {
-+	.startup = snd_rpi_proto_startup,
-+	.hw_params = snd_rpi_proto_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_proto_dai[] = {
-+{
-+	.name		= "WM8731",
-+	.stream_name	= "WM8731 HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "wm8731-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "wm8731.1-001a",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S
-+				| SND_SOC_DAIFMT_NB_NF
-+				| SND_SOC_DAIFMT_CBM_CFM,
-+	.ops		= &snd_rpi_proto_ops,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_proto = {
-+	.name		= "snd_rpi_proto",
-+	.owner		= THIS_MODULE,
-+	.dai_link	= snd_rpi_proto_dai,
-+	.num_links	= ARRAY_SIZE(snd_rpi_proto_dai),
-+};
-+
-+static int snd_rpi_proto_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_proto.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai = &snd_rpi_proto_dai[0];
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+				            "i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_proto);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev,
-+				"snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+
-+static int snd_rpi_proto_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_proto);
-+}
-+
-+static const struct of_device_id snd_rpi_proto_of_match[] = {
-+	{ .compatible = "rpi,rpi-proto", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_proto_of_match);
-+
-+static struct platform_driver snd_rpi_proto_driver = {
-+	.driver = {
-+		.name   = "snd-rpi-proto",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_rpi_proto_of_match,
-+	},
-+	.probe	  = snd_rpi_proto_probe,
-+	.remove	 = snd_rpi_proto_remove,
-+};
-+
-+module_platform_driver(snd_rpi_proto_driver);
-+
-+MODULE_AUTHOR("Florian Meier");
-+MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/brcm2708/patches-4.14/950-0072-RaspiDAC3-support.patch b/target/linux/brcm2708/patches-4.14/950-0072-RaspiDAC3-support.patch
deleted file mode 100644
index a6ccdbac4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0072-RaspiDAC3-support.patch
+++ /dev/null
@@ -1,238 +0,0 @@
-From 478195495a0753278414ad5f7ecdfd9b50432c6b Mon Sep 17 00:00:00 2001
-From: Jan Grulich <jan@grulich.eu>
-Date: Mon, 24 Aug 2015 16:03:47 +0100
-Subject: [PATCH 072/454] RaspiDAC3 support
-
-Signed-off-by: Jan Grulich <jan@grulich.eu>
-
-config: fix RaspiDAC Rev.3x dependencies
-
-Change depends to SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-like the other I2S soundcard drivers.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/Kconfig     |   8 ++
- sound/soc/bcm/Makefile    |   2 +
- sound/soc/bcm/raspidac3.c | 186 ++++++++++++++++++++++++++++++++++++++
- 3 files changed, 196 insertions(+)
- create mode 100644 sound/soc/bcm/raspidac3.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -66,3 +66,11 @@ config SND_BCM2708_SOC_IQAUDIO_DAC
- 	select SND_SOC_PCM512x_I2C
- 	help
- 	  Say Y or M if you want to add support for IQaudIO-DAC.
-+
-+config SND_BCM2708_SOC_RASPIDAC3
-+	tristate "Support for RaspiDAC Rev.3x"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM512x_I2C
-+	select SND_SOC_TPA6130A2
-+	help
-+	  Say Y or M if you want to add support for RaspiDAC Rev.3x.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -16,6 +16,7 @@ snd-soc-hifiberry-digi-objs := hifiberry
- snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-rpi-proto-objs := rpi-proto.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
-+snd-soc-raspidac3-objs := raspidac3.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
-@@ -24,3 +25,4 @@ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_D
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o
---- /dev/null
-+++ b/sound/soc/bcm/raspidac3.c
-@@ -0,0 +1,186 @@
-+/*
-+ * ASoC Driver for RaspiDAC v3
-+ *
-+ * Author:	Jan Grulich <jan@grulich.eu>
-+ *		Copyright 2015
-+ *              based on code by Daniel Matuschek <daniel@hifiberry.com>
-+ *		based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+#include <sound/soc-dapm.h>
-+
-+#include "../codecs/pcm512x.h"
-+#include "../codecs/tpa6130a2.h"
-+
-+/* sound card init */
-+static int snd_rpi_raspidac3_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	int ret;
-+	struct snd_soc_card *card = rtd->card;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
-+
-+	ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207);
-+	if (ret < 0)
-+		dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
-+	else {
-+		struct snd_kcontrol *kctl;
-+
-+		ret = snd_soc_limit_volume(card,
-+					   "TPA6130A2 Headphone Playback Volume",
-+					   54);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set TPA6130A2 volume limit: %d\n",
-+				 ret);
-+		kctl = snd_soc_card_get_kcontrol(card,
-+						 "TPA6130A2 Headphone Playback Volume");
-+		if (kctl) {
-+			strcpy(kctl->id.name, "Headphones Playback Volume");
-+			/* disable the volume dB scale so alsamixer works */
-+			kctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
-+		}
-+
-+		kctl = snd_soc_card_get_kcontrol(card,
-+						 "TPA6130A2 Headphone Playback Switch");
-+		if (kctl)
-+			strcpy(kctl->id.name, "Headphones Playback Switch");
-+	}
-+
-+	return 0;
-+}
-+
-+/* set hw parameters */
-+static int snd_rpi_raspidac3_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* startup */
-+static int snd_rpi_raspidac3_startup(struct snd_pcm_substream *substream) {
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
-+	return 0;
-+}
-+
-+/* shutdown */
-+static void snd_rpi_raspidac3_shutdown(struct snd_pcm_substream *substream) {
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_raspidac3_ops = {
-+	.hw_params = snd_rpi_raspidac3_hw_params,
-+	.startup = snd_rpi_raspidac3_startup,
-+	.shutdown = snd_rpi_raspidac3_shutdown,
-+};
-+
-+/* interface setup */
-+static struct snd_soc_dai_link snd_rpi_raspidac3_dai[] = {
-+{
-+	.name		= "RaspiDAC Rev.3x",
-+	.stream_name	= "RaspiDAC HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm512x-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm512x.1-004c",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_raspidac3_ops,
-+	.init		= snd_rpi_raspidac3_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_raspidac3 = {
-+	.name         = "RaspiDAC Rev.3x HiFi Audio Card",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_raspidac3_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_raspidac3_dai),
-+};
-+
-+/* sound card test */
-+static int snd_rpi_raspidac3_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_raspidac3.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+	    struct device_node *i2s_node;
-+	    struct snd_soc_dai_link *dai = &snd_rpi_raspidac3_dai[0];
-+	    i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					"i2s-controller", 0);
-+
-+	    if (i2s_node) {
-+		dai->cpu_dai_name = NULL;
-+		dai->cpu_of_node = i2s_node;
-+		dai->platform_name = NULL;
-+		dai->platform_of_node = i2s_node;
-+	    }
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_raspidac3);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev,
-+			"snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+/* sound card disconnect */
-+static int snd_rpi_raspidac3_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_raspidac3);
-+}
-+
-+static const struct of_device_id raspidac3_of_match[] = {
-+	{ .compatible = "jg,raspidacv3", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, raspidac3_of_match);
-+
-+/* sound card platform driver */
-+static struct platform_driver snd_rpi_raspidac3_driver = {
-+	.driver = {
-+		.name   = "snd-rpi-raspidac3",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = raspidac3_of_match,
-+	},
-+	.probe          = snd_rpi_raspidac3_probe,
-+	.remove         = snd_rpi_raspidac3_remove,
-+};
-+
-+module_platform_driver(snd_rpi_raspidac3_driver);
-+
-+MODULE_AUTHOR("Jan Grulich <jan@grulich.eu>");
-+MODULE_DESCRIPTION("ASoC Driver for RaspiDAC Rev.3x");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0073-Add-Support-for-JustBoom-Audio-boards.patch b/target/linux/brcm2708/patches-4.14/950-0073-Add-Support-for-JustBoom-Audio-boards.patch
deleted file mode 100644
index a522e4566..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0073-Add-Support-for-JustBoom-Audio-boards.patch
+++ /dev/null
@@ -1,448 +0,0 @@
-From c86b5cd0c5a5ba9b9937bc9cecbc3b25a4f037ad Mon Sep 17 00:00:00 2001
-From: Aaron Shaw <shawaj@gmail.com>
-Date: Thu, 7 Apr 2016 21:26:21 +0100
-Subject: [PATCH 073/454] Add Support for JustBoom Audio boards
-
-justboom-dac: Adjust for ALSA API change
-
-As of 4.4, snd_soc_limit_volume now takes a struct snd_soc_card *
-rather than a struct snd_soc_codec *.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- sound/soc/bcm/Kconfig         |  14 +++
- sound/soc/bcm/Makefile        |   4 +
- sound/soc/bcm/justboom-dac.c  | 163 +++++++++++++++++++++++++
- sound/soc/bcm/justboom-digi.c | 216 ++++++++++++++++++++++++++++++++++
- 4 files changed, 397 insertions(+)
- create mode 100644 sound/soc/bcm/justboom-dac.c
- create mode 100644 sound/soc/bcm/justboom-digi.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -60,6 +60,20 @@ config SND_BCM2708_SOC_RPI_PROTO
- 	help
- 	  Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731).
- 
-+config SND_BCM2708_SOC_JUSTBOOM_DAC
-+	tristate "Support for JustBoom DAC"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM512x
-+	help
-+	  Say Y or M if you want to add support for JustBoom DAC.
-+
-+config SND_BCM2708_SOC_JUSTBOOM_DIGI
-+	tristate "Support for JustBoom Digi"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_WM8804
-+	help
-+	  Say Y or M if you want to add support for JustBoom Digi.
-+
- config SND_BCM2708_SOC_IQAUDIO_DAC
- 	tristate "Support for IQaudIO-DAC"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -13,6 +13,8 @@ snd-soc-hifiberry-amp-objs := hifiberry_
- snd-soc-hifiberry-dac-objs := hifiberry_dac.o
- snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
- snd-soc-hifiberry-digi-objs := hifiberry_digi.o
-+snd-soc-justboom-dac-objs := justboom-dac.o
-+snd-soc-justboom-digi-objs := justboom-digi.o
- snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-rpi-proto-objs := rpi-proto.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
-@@ -22,6 +24,8 @@ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_A
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
-+obj-$(CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC) += snd-soc-justboom-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI) += snd-soc-justboom-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/justboom-dac.c
-@@ -0,0 +1,163 @@
-+/*
-+ * ASoC Driver for JustBoom DAC Raspberry Pi HAT Sound Card
-+ *
-+ * Author:	Milan Neskovic
-+ *		Copyright 2016
-+ *		based on code by Daniel Matuschek <info@crazy-audio.com>
-+ *		based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/pcm512x.h"
-+
-+static bool digital_gain_0db_limit = true;
-+
-+static int snd_rpi_justboom_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
-+
-+	if (digital_gain_0db_limit)
-+	{
-+		int ret;
-+		struct snd_soc_card *card = rtd->card;
-+
-+		ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_rpi_justboom_dac_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+	/*return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);*/
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+static int snd_rpi_justboom_dac_startup(struct snd_pcm_substream *substream) {
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
-+	return 0;
-+}
-+
-+static void snd_rpi_justboom_dac_shutdown(struct snd_pcm_substream *substream) {
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_justboom_dac_ops = {
-+	.hw_params = snd_rpi_justboom_dac_hw_params,
-+	.startup = snd_rpi_justboom_dac_startup,
-+	.shutdown = snd_rpi_justboom_dac_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_justboom_dac_dai[] = {
-+{
-+	.name		= "JustBoom DAC",
-+	.stream_name	= "JustBoom DAC HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm512x-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm512x.1-004d",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_justboom_dac_ops,
-+	.init		= snd_rpi_justboom_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_justboom_dac = {
-+	.name         = "snd_rpi_justboom_dac",
-+	.driver_name  = "JustBoomDac",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_justboom_dac_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_justboom_dac_dai),
-+};
-+
-+static int snd_rpi_justboom_dac_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_justboom_dac.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+	    struct device_node *i2s_node;
-+	    struct snd_soc_dai_link *dai = &snd_rpi_justboom_dac_dai[0];
-+	    i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					"i2s-controller", 0);
-+
-+	    if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+	    }
-+
-+	    digital_gain_0db_limit = !of_property_read_bool(
-+			pdev->dev.of_node, "justboom,24db_digital_gain");
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_justboom_dac);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev,
-+			"snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_justboom_dac_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_justboom_dac);
-+}
-+
-+static const struct of_device_id snd_rpi_justboom_dac_of_match[] = {
-+	{ .compatible = "justboom,justboom-dac", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_justboom_dac_of_match);
-+
-+static struct platform_driver snd_rpi_justboom_dac_driver = {
-+	.driver = {
-+		.name   = "snd-rpi-justboom-dac",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_rpi_justboom_dac_of_match,
-+	},
-+	.probe          = snd_rpi_justboom_dac_probe,
-+	.remove         = snd_rpi_justboom_dac_remove,
-+};
-+
-+module_platform_driver(snd_rpi_justboom_dac_driver);
-+
-+MODULE_AUTHOR("Milan Neskovic <info@justboom.co>");
-+MODULE_DESCRIPTION("ASoC Driver for JustBoom PI DAC HAT Sound Card");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/sound/soc/bcm/justboom-digi.c
-@@ -0,0 +1,216 @@
-+/*
-+ * ASoC Driver for JustBoom Raspberry Pi Digi HAT Sound Card
-+ *
-+ * Author:	Milan Neskovic
-+ *		Copyright 2016
-+ *		based on code by Daniel Matuschek <info@crazy-audio.com>
-+ *		based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/wm8804.h"
-+
-+static int snd_rpi_justboom_digi_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	/* enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	return 0;
-+}
-+
-+static int snd_rpi_justboom_digi_startup(struct snd_pcm_substream *substream) {
-+	/* turn on digital output */
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00);
-+	return 0;
-+}
-+
-+static void snd_rpi_justboom_digi_shutdown(struct snd_pcm_substream *substream) {
-+	/* turn off output */
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c);
-+}
-+
-+static int snd_rpi_justboom_digi_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	int sysclk = 27000000; /* This is fixed on this board */
-+
-+	long mclk_freq=0;
-+	int mclk_div=1;
-+	int sampling_freq=1;
-+
-+	int ret;
-+
-+	int samplerate = params_rate(params);
-+
-+	if (samplerate<=96000) {
-+		mclk_freq=samplerate*256;
-+		mclk_div=WM8804_MCLKDIV_256FS;
-+	} else {
-+		mclk_freq=samplerate*128;
-+		mclk_div=WM8804_MCLKDIV_128FS;
-+	}
-+
-+	switch (samplerate) {
-+		case 32000:
-+			sampling_freq=0x03;
-+			break;
-+		case 44100:
-+			sampling_freq=0x00;
-+			break;
-+		case 48000:
-+			sampling_freq=0x02;
-+			break;
-+		case 88200:
-+			sampling_freq=0x08;
-+			break;
-+		case 96000:
-+			sampling_freq=0x0a;
-+			break;
-+		case 176400:
-+			sampling_freq=0x0c;
-+			break;
-+		case 192000:
-+			sampling_freq=0x0e;
-+			break;
-+		default:
-+			dev_err(codec->dev,
-+			"Failed to set WM8804 SYSCLK, unsupported samplerate %d\n",
-+			samplerate);
-+	}
-+
-+	snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
-+	snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
-+
-+	ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
-+					sysclk, SND_SOC_CLOCK_OUT);
-+	if (ret < 0) {
-+		dev_err(codec->dev,
-+		"Failed to set WM8804 SYSCLK: %d\n", ret);
-+		return ret;
-+	}
-+
-+	/* Enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	/* Power on */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
-+
-+	/* set sampling frequency status bits */
-+	snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq);
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai,64);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_justboom_digi_ops = {
-+	.hw_params = snd_rpi_justboom_digi_hw_params,
-+        .startup = snd_rpi_justboom_digi_startup,
-+        .shutdown = snd_rpi_justboom_digi_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_justboom_digi_dai[] = {
-+{
-+	.name		= "JustBoom Digi",
-+	.stream_name	= "JustBoom Digi HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "wm8804-spdif",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "wm8804.1-003b",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBM_CFM,
-+	.ops		= &snd_rpi_justboom_digi_ops,
-+	.init		= snd_rpi_justboom_digi_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_justboom_digi = {
-+	.name         = "snd_rpi_justboom_digi",
-+	.driver_name  = "JustBoomDigi",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_justboom_digi_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_justboom_digi_dai),
-+};
-+
-+static int snd_rpi_justboom_digi_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_justboom_digi.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+	    struct device_node *i2s_node;
-+	    struct snd_soc_dai_link *dai = &snd_rpi_justboom_digi_dai[0];
-+	    i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					"i2s-controller", 0);
-+
-+	    if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+	    }
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_justboom_digi);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev,
-+			"snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_justboom_digi_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_justboom_digi);
-+}
-+
-+static const struct of_device_id snd_rpi_justboom_digi_of_match[] = {
-+	{ .compatible = "justboom,justboom-digi", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_justboom_digi_of_match);
-+
-+static struct platform_driver snd_rpi_justboom_digi_driver = {
-+	.driver = {
-+		.name   = "snd-rpi-justboom-digi",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_rpi_justboom_digi_of_match,
-+	},
-+	.probe          = snd_rpi_justboom_digi_probe,
-+	.remove         = snd_rpi_justboom_digi_remove,
-+};
-+
-+module_platform_driver(snd_rpi_justboom_digi_driver);
-+
-+MODULE_AUTHOR("Milan Neskovic <info@justboom.co>");
-+MODULE_DESCRIPTION("ASoC Driver for JustBoom PI Digi HAT Sound Card");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0074-ARM-adau1977-adc-Add-basic-machine-driver-for-adau19.patch b/target/linux/brcm2708/patches-4.14/950-0074-ARM-adau1977-adc-Add-basic-machine-driver-for-adau19.patch
deleted file mode 100644
index 00163cbcb..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0074-ARM-adau1977-adc-Add-basic-machine-driver-for-adau19.patch
+++ /dev/null
@@ -1,177 +0,0 @@
-From d40ccbe0dbe26b7468ea1383e41d43179ff7c366 Mon Sep 17 00:00:00 2001
-From: Andrey Grodzovsky <andrey2805@gmail.com>
-Date: Tue, 3 May 2016 22:10:59 -0400
-Subject: [PATCH 074/454] ARM: adau1977-adc: Add basic machine driver for
- adau1977 codec driver.
-
-This commit adds basic support for the codec usage including: Device tree overlay,
-binding I2S bus and setting I2S mode, clock source and frequency setting according
-to spec.
-
-Signed-off-by: Andrey Grodzovsky <andrey2805@gmail.com>
----
- sound/soc/bcm/Kconfig        |   7 ++
- sound/soc/bcm/Makefile       |   2 +
- sound/soc/bcm/adau1977-adc.c | 125 +++++++++++++++++++++++++++++++++++
- 3 files changed, 134 insertions(+)
- create mode 100644 sound/soc/bcm/adau1977-adc.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -88,3 +88,10 @@ config SND_BCM2708_SOC_RASPIDAC3
- 	select SND_SOC_TPA6130A2
- 	help
- 	  Say Y or M if you want to add support for RaspiDAC Rev.3x.
-+
-+config SND_BCM2708_SOC_ADAU1977_ADC
-+	tristate "Support for ADAU1977 ADC"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_ADAU1977_I2C
-+	help
-+	  Say Y or M if you want to add support for ADAU1977 ADC.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -9,6 +9,7 @@ snd-soc-cygnus-objs := cygnus-pcm.o cygn
- obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-cygnus.o
- 
- # BCM2708 Machine Support
-+snd-soc-adau1977-adc-objs := adau1977-adc.o
- snd-soc-hifiberry-amp-objs := hifiberry_amp.o
- snd-soc-hifiberry-dac-objs := hifiberry_dac.o
- snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
-@@ -20,6 +21,7 @@ snd-soc-rpi-proto-objs := rpi-proto.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
- snd-soc-raspidac3-objs := raspidac3.o
- 
-+obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
---- /dev/null
-+++ b/sound/soc/bcm/adau1977-adc.c
-@@ -0,0 +1,125 @@
-+/*
-+ * ASoC Driver for ADAU1977 ADC
-+ *
-+ * Author:	Andrey Grodzovsky <andrey2805@gmail.com>
-+ *		Copyright 2016
-+ *
-+ * This file is based on hifibery_dac driver by Florian Meier.
-+ * 
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+enum adau1977_clk_id {
-+    ADAU1977_SYSCLK,
-+};
-+ 
-+enum adau1977_sysclk_src {
-+    ADAU1977_SYSCLK_SRC_MCLK,
-+    ADAU1977_SYSCLK_SRC_LRCLK,
-+};
-+
-+static int eval_adau1977_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	int ret;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+	
-+	ret = snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 0, 0);
-+	if (ret < 0)
-+		return ret;
-+
-+	return snd_soc_codec_set_sysclk(rtd->codec, ADAU1977_SYSCLK,
-+			ADAU1977_SYSCLK_SRC_MCLK, 11289600, SND_SOC_CLOCK_IN);
-+}
-+ 
-+static struct snd_soc_dai_link snd_rpi_adau1977_dai[] = {
-+	{
-+	.name = "adau1977",
-+	.stream_name = "ADAU1977", 
-+	.cpu_dai_name = "bcm2708-i2s.0", 
-+	.codec_dai_name = "adau1977-hifi",
-+	.platform_name = "bcm2708-i2s.0",
-+	.codec_name = "adau1977.1-0011",
-+	.init = eval_adau1977_init,
-+	.dai_fmt = SND_SOC_DAIFMT_I2S |
-+		SND_SOC_DAIFMT_NB_NF |
-+		SND_SOC_DAIFMT_CBM_CFM,
-+	},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_adau1977_adc = {
-+	.name         = "snd_rpi_adau1977_adc",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_adau1977_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_adau1977_dai),
-+};
-+
-+static int snd_adau1977_adc_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_adau1977_adc.dev = &pdev->dev;
-+	if (pdev->dev.of_node) {
-+	    struct device_node *i2s_node;
-+	    struct snd_soc_dai_link *dai = &snd_rpi_adau1977_dai[0];
-+	    i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					"i2s-controller", 0);
-+
-+	    if (i2s_node) {
-+		dai->cpu_dai_name = NULL;
-+		dai->cpu_of_node = i2s_node;
-+		dai->platform_name = NULL;
-+		dai->platform_of_node = i2s_node;
-+	    }
-+	}
-+
-+	ret = snd_soc_register_card(&snd_adau1977_adc);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_adau1977_adc_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_adau1977_adc);
-+}
-+
-+static const struct of_device_id snd_adau1977_adc_of_match[] = {
-+	{ .compatible = "adi,adau1977-adc", },
-+	{},
-+};
-+
-+MODULE_DEVICE_TABLE(of, snd_adau1977_adc_of_match);
-+
-+static struct platform_driver snd_adau1977_adc_driver = {
-+        .driver = {
-+                .name   = "snd-adau1977-adc",
-+                .owner  = THIS_MODULE,
-+		.of_match_table = snd_adau1977_adc_of_match,
-+        },
-+        .probe          = snd_adau1977_adc_probe,
-+        .remove         = snd_adau1977_adc_remove,
-+};
-+
-+module_platform_driver(snd_adau1977_adc_driver);
-+
-+MODULE_AUTHOR("Andrey Grodzovsky <andrey2805@gmail.com>");
-+MODULE_DESCRIPTION("ASoC Driver for ADAU1977 ADC");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0075-New-AudioInjector.net-Pi-soundcard-with-low-jitter-a.patch b/target/linux/brcm2708/patches-4.14/950-0075-New-AudioInjector.net-Pi-soundcard-with-low-jitter-a.patch
deleted file mode 100644
index 81ca0b52d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0075-New-AudioInjector.net-Pi-soundcard-with-low-jitter-a.patch
+++ /dev/null
@@ -1,246 +0,0 @@
-From ef421b47c67af36f31730fe5e6088cfb672369ea Mon Sep 17 00:00:00 2001
-From: Matt Flax <flatmax@flatmax.org>
-Date: Mon, 16 May 2016 21:36:31 +1000
-Subject: [PATCH 075/454] New AudioInjector.net Pi soundcard with low jitter
- audio in and out.
-
-Contains the sound/soc/bcm ALSA machine driver and necessary alterations to the Kconfig and Makefile.
-Adds the dts overlay and updates the Makefile and README.
-Updates the relevant defconfig files to enable building for the Raspberry Pi.
-Thanks to Phil Elwell (pelwell) for the review, simple-card concepts and discussion. Thanks to Clive Messer for overlay naming suggestions.
-
-Added support for headphones, microphone and bclk_ratio settings.
-
-This patch adds headphone and microphone capability to the Audio Injector sound card. The patch also sets the bit clock ratio for use in the bcm2835-i2s driver. The bcm2835-i2s can't handle an 8 kHz sample rate when the bit clock is at 12 MHz because its register is only 10 bits wide which can't represent the ch2 offset of 1508. For that reason, the rate constraint is added.
----
- sound/soc/bcm/Kconfig                      |   7 +
- sound/soc/bcm/Makefile                     |   3 +
- sound/soc/bcm/audioinjector-pi-soundcard.c | 193 +++++++++++++++++++++
- 3 files changed, 203 insertions(+)
- create mode 100644 sound/soc/bcm/audioinjector-pi-soundcard.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -95,3 +95,10 @@ config SND_BCM2708_SOC_ADAU1977_ADC
- 	select SND_SOC_ADAU1977_I2C
- 	help
- 	  Say Y or M if you want to add support for ADAU1977 ADC.
-+
-+config SND_AUDIOINJECTOR_PI_SOUNDCARD
-+	tristate "Support for audioinjector.net Pi add on soundcard"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_WM8731
-+	help
-+	  Say Y or M if you want to add support for audioinjector.net Pi Hat
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -20,6 +20,7 @@ snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-rpi-proto-objs := rpi-proto.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
- snd-soc-raspidac3-objs := raspidac3.o
-+snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-@@ -32,3 +33,5 @@ obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) +=
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o
-+obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
-+
---- /dev/null
-+++ b/sound/soc/bcm/audioinjector-pi-soundcard.c
-@@ -0,0 +1,193 @@
-+/*
-+ * ASoC Driver for AudioInjector Pi add on soundcard
-+ *
-+ *  Created on: 13-May-2016
-+ *      Author: flatmax@flatmax.org
-+ *              based on code by  Cliff Cai <Cliff.Cai@analog.com> for the ssm2602 machine blackfin.
-+ *              with help from Lars-Peter Clausen for simplifying the original code to use the dai_fmt field.
-+ *		i2s_node code taken from the other sound/soc/bcm machine drivers.
-+ *
-+ * Copyright (C) 2016 Flatmax Pty. Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/types.h>
-+
-+#include <sound/core.h>
-+#include <sound/soc.h>
-+#include <sound/pcm_params.h>
-+#include <sound/control.h>
-+
-+#include "../codecs/wm8731.h"
-+
-+static const unsigned int bcm2835_rates_12000000[] = {
-+	8000, 16000, 32000, 44100, 48000, 96000, 88200,
-+};
-+
-+static struct snd_pcm_hw_constraint_list bcm2835_constraints_12000000 = {
-+	.list = bcm2835_rates_12000000,
-+	.count = ARRAY_SIZE(bcm2835_rates_12000000),
-+};
-+
-+static int snd_audioinjector_pi_soundcard_startup(struct snd_pcm_substream *substream)
-+{
-+	/* Setup constraints, because there is a 12 MHz XTAL on the board */
-+	snd_pcm_hw_constraint_list(substream->runtime, 0,
-+				SNDRV_PCM_HW_PARAM_RATE,
-+				&bcm2835_constraints_12000000);
-+	return 0;
-+}
-+
-+static int snd_audioinjector_pi_soundcard_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	switch (params_rate(params)){
-+		case 8000:
-+			return snd_soc_dai_set_bclk_ratio(cpu_dai, 1);
-+		case 16000:
-+			return snd_soc_dai_set_bclk_ratio(cpu_dai, 750);
-+		case 32000:
-+			return snd_soc_dai_set_bclk_ratio(cpu_dai, 375);
-+		case 44100:
-+			return snd_soc_dai_set_bclk_ratio(cpu_dai, 272);
-+		case 48000:
-+			return snd_soc_dai_set_bclk_ratio(cpu_dai, 250);
-+		case 88200:
-+			return snd_soc_dai_set_bclk_ratio(cpu_dai, 136);
-+		case 96000:
-+			return snd_soc_dai_set_bclk_ratio(cpu_dai, 125);
-+		default:
-+			return snd_soc_dai_set_bclk_ratio(cpu_dai, 125);
-+	}
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_audioinjector_pi_soundcard_ops = {
-+	.startup = snd_audioinjector_pi_soundcard_startup,
-+	.hw_params = snd_audioinjector_pi_soundcard_hw_params,
-+};
-+
-+static int audioinjector_pi_soundcard_dai_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	return snd_soc_dai_set_sysclk(rtd->codec_dai, WM8731_SYSCLK_XTAL, 12000000, SND_SOC_CLOCK_IN);
-+}
-+
-+static struct snd_soc_dai_link audioinjector_pi_soundcard_dai[] = {
-+	{
-+		.name = "AudioInjector audio",
-+		.stream_name = "AudioInjector audio",
-+		.cpu_dai_name	= "bcm2708-i2s.0",
-+		.codec_dai_name = "wm8731-hifi",
-+		.platform_name	= "bcm2835-i2s.0",
-+		.codec_name = "wm8731.1-001a",
-+		.ops = &snd_audioinjector_pi_soundcard_ops,
-+		.init = audioinjector_pi_soundcard_dai_init,
-+		.dai_fmt = SND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF,
-+	},
-+};
-+
-+static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = {
-+	SND_SOC_DAPM_HP("Headphone Jack", NULL),
-+	SND_SOC_DAPM_SPK("Ext Spk", NULL),
-+	SND_SOC_DAPM_LINE("Line In Jacks", NULL),
-+	SND_SOC_DAPM_MIC("Microphone", NULL),
-+};
-+
-+static const struct snd_soc_dapm_route audioinjector_audio_map[] = {
-+	/* headphone connected to LHPOUT, RHPOUT */
-+	{"Headphone Jack", NULL, "LHPOUT"},
-+	{"Headphone Jack", NULL, "RHPOUT"},
-+
-+	/* speaker connected to LOUT, ROUT */
-+	{"Ext Spk", NULL, "ROUT"},
-+	{"Ext Spk", NULL, "LOUT"},
-+
-+	/* line inputs */
-+	{"Line In Jacks", NULL, "Line Input"},
-+
-+	/* mic is connected to Mic Jack, with WM8731 Mic Bias */
-+	{"Microphone", NULL, "Mic Bias"},
-+};
-+
-+static struct snd_soc_card snd_soc_audioinjector = {
-+	.name = "audioinjector-pi-soundcard",
-+	.dai_link = audioinjector_pi_soundcard_dai,
-+	.num_links = ARRAY_SIZE(audioinjector_pi_soundcard_dai),
-+
-+	.dapm_widgets = wm8731_dapm_widgets,
-+	.num_dapm_widgets = ARRAY_SIZE(wm8731_dapm_widgets),
-+	.dapm_routes = audioinjector_audio_map,
-+	.num_dapm_routes = ARRAY_SIZE(audioinjector_audio_map),
-+};
-+
-+static int audioinjector_pi_soundcard_probe(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = &snd_soc_audioinjector;
-+	int ret;
-+	
-+	card->dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct snd_soc_dai_link *dai = &audioinjector_pi_soundcard_dai[0];
-+		struct device_node *i2s_node = of_parse_phandle(pdev->dev.of_node,
-+								"i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		} else
-+			if (!dai->cpu_of_node) {
-+				dev_err(&pdev->dev, "Property 'i2s-controller' missing or invalid\n");
-+				return -EINVAL;
-+			}
-+	}
-+
-+	if ((ret = snd_soc_register_card(card))) {
-+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
-+	}
-+	return ret;
-+}
-+
-+static int audioinjector_pi_soundcard_remove(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = platform_get_drvdata(pdev);
-+	return snd_soc_unregister_card(card);
-+
-+}
-+
-+static const struct of_device_id audioinjector_pi_soundcard_of_match[] = {
-+	{ .compatible = "ai,audioinjector-pi-soundcard", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, audioinjector_pi_soundcard_of_match);
-+
-+static struct platform_driver audioinjector_pi_soundcard_driver = {
-+       .driver         = {
-+		.name   = "audioinjector-stereo",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = audioinjector_pi_soundcard_of_match,
-+       },
-+       .probe          = audioinjector_pi_soundcard_probe,
-+       .remove         = audioinjector_pi_soundcard_remove,
-+};
-+
-+module_platform_driver(audioinjector_pi_soundcard_driver);
-+MODULE_AUTHOR("Matt Flax <flatmax@flatmax.org>");
-+MODULE_DESCRIPTION("AudioInjector.net Pi Soundcard");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:audioinjector-pi-soundcard");
-+
diff --git a/target/linux/brcm2708/patches-4.14/950-0076-Add-IQAudIO-Digi-WM8804-board-support.patch b/target/linux/brcm2708/patches-4.14/950-0076-Add-IQAudIO-Digi-WM8804-board-support.patch
deleted file mode 100644
index 19c14204b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0076-Add-IQAudIO-Digi-WM8804-board-support.patch
+++ /dev/null
@@ -1,295 +0,0 @@
-From e6a023d12a233e5866e716d82aa4dd5464e8e145 Mon Sep 17 00:00:00 2001
-From: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
-Date: Thu, 30 Jun 2016 18:38:42 +0100
-Subject: [PATCH 076/454] Add IQAudIO Digi WM8804 board support
-
-Support IQAudIO Digi board with iqaudio_digi machine driver and
- iqaudio-digi-wm8804-audio overlay.
-
-NB. Machine driver is a cut and paste of hifiberry_digi code, with format
-    and general cleanup to comply with kernel coding standards.
-
-Signed-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
----
- sound/soc/bcm/Kconfig        |   7 +
- sound/soc/bcm/Makefile       |   2 +
- sound/soc/bcm/iqaudio_digi.c | 239 +++++++++++++++++++++++++++++++++++
- 3 files changed, 248 insertions(+)
- create mode 100644 sound/soc/bcm/iqaudio_digi.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -81,6 +81,13 @@ config SND_BCM2708_SOC_IQAUDIO_DAC
- 	help
- 	  Say Y or M if you want to add support for IQaudIO-DAC.
- 
-+config SND_BCM2708_SOC_IQAUDIO_DIGI
-+        tristate "Support for IQAudIO Digi"
-+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+        select SND_SOC_WM8804
-+        help
-+         Say Y or M if you want to add support for IQAudIO Digital IO board.
-+
- config SND_BCM2708_SOC_RASPIDAC3
- 	tristate "Support for RaspiDAC Rev.3x"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -19,6 +19,7 @@ snd-soc-justboom-digi-objs := justboom-d
- snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-rpi-proto-objs := rpi-proto.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
-+snd-soc-iqaudio-digi-objs := iqaudio_digi.o
- snd-soc-raspidac3-objs := raspidac3.o
- snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
- 
-@@ -32,6 +33,7 @@ obj-$(CONFIG_SND_BCM2708_SOC_JUSTBOOM_DI
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI) += snd-soc-iqaudio-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o
- obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
- 
---- /dev/null
-+++ b/sound/soc/bcm/iqaudio_digi.c
-@@ -0,0 +1,239 @@
-+/*
-+ * ASoC Driver for IQAudIO WM8804 Digi
-+ *
-+ * Author: Daniel Matuschek <info@crazy-audio.com>
-+ * based on the HifiBerry DAC driver by Florian Meier <florian.meier@koalo.de>
-+ *	Copyright 2013
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/wm8804.h"
-+
-+static short int auto_shutdown_output;
-+module_param(auto_shutdown_output, short,
-+	      S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
-+MODULE_PARM_DESC(auto_shutdown_output, "Shutdown SP/DIF output if playback is stopped");
-+
-+static int snd_rpi_iqaudio_digi_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	/* enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	return 0;
-+}
-+
-+static int snd_rpi_iqaudio_digi_startup(struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	/* turn on digital output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00);
-+
-+	return 0;
-+}
-+
-+static void snd_rpi_iqaudio_digi_shutdown(struct snd_pcm_substream *substream)
-+{
-+	if (auto_shutdown_output) {
-+		struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+		struct snd_soc_codec *codec = rtd->codec;
-+
-+		/* turn off digital output */
-+		snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c);
-+	}
-+}
-+
-+
-+static int snd_rpi_iqaudio_digi_hw_params(struct snd_pcm_substream *substream,
-+	struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	int sysclk = 27000000; /* This is fixed on this board */
-+
-+	long mclk_freq = 0;
-+	int mclk_div = 1;
-+	int sampling_freq = 1;
-+
-+	int ret;
-+
-+	int samplerate = params_rate(params);
-+
-+	if (samplerate <= 96000) {
-+		mclk_freq = samplerate * 256;
-+		mclk_div = WM8804_MCLKDIV_256FS;
-+	} else {
-+		mclk_freq = samplerate * 128;
-+		mclk_div = WM8804_MCLKDIV_128FS;
-+	}
-+
-+	switch (samplerate) {
-+	case 32000:
-+		sampling_freq = 0x03;
-+		break;
-+	case 44100:
-+		sampling_freq = 0x00;
-+		break;
-+	case 48000:
-+		sampling_freq = 0x02;
-+		break;
-+	case 88200:
-+		sampling_freq = 0x08;
-+		break;
-+	case 96000:
-+		sampling_freq = 0x0a;
-+		break;
-+	case 176400:
-+		sampling_freq = 0x0c;
-+		break;
-+	case 192000:
-+		sampling_freq = 0x0e;
-+		break;
-+	default:
-+		dev_err(codec->dev, "Failed to set WM8804 SYSCLK, unsupported samplerate %d\n",
-+			samplerate);
-+	}
-+
-+	snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
-+	snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
-+
-+	ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
-+					sysclk, SND_SOC_CLOCK_OUT);
-+	if (ret < 0) {
-+		dev_err(codec->dev, "Failed to set WM8804 SYSCLK: %d\n", ret);
-+		return ret;
-+	}
-+
-+	/* Enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	/* Power on */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
-+
-+	/* set sampling frequency status bits */
-+	snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq);
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_iqaudio_digi_ops = {
-+	.hw_params	= snd_rpi_iqaudio_digi_hw_params,
-+	.startup	= snd_rpi_iqaudio_digi_startup,
-+	.shutdown	= snd_rpi_iqaudio_digi_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_iqaudio_digi_dai[] = {
-+{
-+	.name		= "IQAudIO Digi",
-+	.stream_name	= "IQAudIO Digi HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "wm8804-spdif",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "wm8804.1-003b",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S |
-+			  SND_SOC_DAIFMT_NB_NF |
-+			  SND_SOC_DAIFMT_CBM_CFM,
-+	.ops		= &snd_rpi_iqaudio_digi_ops,
-+	.init		= snd_rpi_iqaudio_digi_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_iqaudio_digi = {
-+	.name		= "IQAudIODigi",
-+	.owner		= THIS_MODULE,
-+	.dai_link	= snd_rpi_iqaudio_digi_dai,
-+	.num_links	= ARRAY_SIZE(snd_rpi_iqaudio_digi_dai),
-+};
-+
-+static int snd_rpi_iqaudio_digi_probe(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = &snd_rpi_iqaudio_digi;
-+	char *prefix = "wm8804-digi,";
-+	char prop[128];
-+	struct device_node *np;
-+	int ret = 0;
-+
-+	snd_rpi_iqaudio_digi.dev = &pdev->dev;
-+
-+	np = pdev->dev.of_node;
-+	if (np) {
-+		struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_digi_dai[0];
-+		struct device_node *i2s_node;
-+
-+		i2s_node = of_parse_phandle(np, "i2s-controller", 0);
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+
-+		snprintf(prop, sizeof(prop), "%scard-name", prefix);
-+		of_property_read_string(np, prop, &card->name);
-+
-+		snprintf(prop, sizeof(prop), "%sdai-name", prefix);
-+		of_property_read_string(np, prop, &dai->name);
-+
-+		snprintf(prop, sizeof(prop), "%sdai-stream-name", prefix);
-+		of_property_read_string(np, prop, &dai->stream_name);
-+	}
-+
-+	ret = snd_soc_register_card(card);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
-+			ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_iqaudio_digi_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_iqaudio_digi);
-+}
-+
-+static const struct of_device_id snd_rpi_iqaudio_digi_of_match[] = {
-+	{ .compatible = "iqaudio,wm8804-digi", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_iqaudio_digi_of_match);
-+
-+static struct platform_driver snd_rpi_iqaudio_digi_driver = {
-+	.driver = {
-+		.name		= "IQAudIODigi",
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= snd_rpi_iqaudio_digi_of_match,
-+	},
-+	.probe  = snd_rpi_iqaudio_digi_probe,
-+	.remove = snd_rpi_iqaudio_digi_remove,
-+};
-+
-+module_platform_driver(snd_rpi_iqaudio_digi_driver);
-+
-+MODULE_AUTHOR("Daniel Matuschek <info@crazy-audio.com>");
-+MODULE_DESCRIPTION("ASoC Driver for IQAudIO WM8804 Digi");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0077-New-driver-for-RRA-DigiDAC1-soundcard-using-WM8741-W.patch b/target/linux/brcm2708/patches-4.14/950-0077-New-driver-for-RRA-DigiDAC1-soundcard-using-WM8741-W.patch
deleted file mode 100644
index 0b6168b4f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0077-New-driver-for-RRA-DigiDAC1-soundcard-using-WM8741-W.patch
+++ /dev/null
@@ -1,468 +0,0 @@
-From b41def5d536b4389e2648286c03e1354a3cc1523 Mon Sep 17 00:00:00 2001
-From: escalator2015 <jmtasende@gmail.com>
-Date: Tue, 24 May 2016 16:20:09 +0100
-Subject: [PATCH 077/454] New driver for RRA DigiDAC1 soundcard using WM8741 +
- WM8804
-
----
- sound/soc/bcm/Kconfig              |   8 +
- sound/soc/bcm/Makefile             |   2 +
- sound/soc/bcm/digidac1-soundcard.c | 422 +++++++++++++++++++++++++++++
- 3 files changed, 432 insertions(+)
- create mode 100644 sound/soc/bcm/digidac1-soundcard.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -109,3 +109,11 @@ config SND_AUDIOINJECTOR_PI_SOUNDCARD
- 	select SND_SOC_WM8731
- 	help
- 	  Say Y or M if you want to add support for audioinjector.net Pi Hat
-+
-+config SND_DIGIDAC1_SOUNDCARD
-+        tristate "Support for Red Rocks Audio DigiDAC1"
-+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+        select SND_SOC_WM8804
-+        select SND_SOC_WM8741
-+        help
-+         Say Y or M if you want to add support for Red Rocks Audio DigiDAC1 board.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -22,6 +22,7 @@ snd-soc-iqaudio-dac-objs := iqaudio-dac.
- snd-soc-iqaudio-digi-objs := iqaudio_digi.o
- snd-soc-raspidac3-objs := raspidac3.o
- snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
-+snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-@@ -36,4 +37,5 @@ obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI) += snd-soc-iqaudio-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o
- obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
-+obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o
- 
---- /dev/null
-+++ b/sound/soc/bcm/digidac1-soundcard.c
-@@ -0,0 +1,422 @@
-+/*
-+ * ASoC Driver for RRA DigiDAC1
-+ * Copyright 2016
-+ * Author: José M. Tasende <vintage@redrocksaudio.es>
-+ * based on the HifiBerry DAC driver by Florian Meier <florian.meier@koalo.de>
-+ * and the Wolfson card driver by Nikesh Oswal, <Nikesh.Oswal@wolfsonmicro.com>
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/i2c.h>
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+#include <sound/soc-dapm.h>
-+#include <sound/tlv.h>
-+#include <linux/regulator/consumer.h>
-+
-+#include "../codecs/wm8804.h"
-+#include "../codecs/wm8741.h"
-+
-+#define WM8741_NUM_SUPPLIES 2
-+
-+/* codec private data */
-+struct wm8741_priv {
-+	struct wm8741_platform_data pdata;
-+	struct regmap *regmap;
-+	struct regulator_bulk_data supplies[WM8741_NUM_SUPPLIES];
-+	unsigned int sysclk;
-+	const struct snd_pcm_hw_constraint_list *sysclk_constraints;
-+};
-+
-+static int samplerate = 44100;
-+
-+/* New Alsa Controls not exposed by original wm8741 codec driver	*/
-+/* in actual driver the att. adjustment is wrong because		*/
-+/* this DAC has a coarse attenuation register with 4dB steps		*/
-+/* and a fine level register with 0.125dB steps				*/
-+/* each register has 32 steps so combining both we have	1024 steps	*/
-+/* of 0.125 dB.								*/
-+/* The original level controls from driver are removed at startup	*/
-+/* and replaced by the corrected ones.					*/
-+/* The same wm8741 driver can be used for wm8741 and wm8742 devices	*/
-+
-+static const DECLARE_TLV_DB_SCALE(dac_tlv_fine, 0, 13, 0);
-+static const DECLARE_TLV_DB_SCALE(dac_tlv_coarse, -12700, 400, 1);
-+static const char *w8741_dither[4] = {"Off", "RPDF", "TPDF", "HPDF"};
-+static const char *w8741_filter[5] = {
-+		"Type 1", "Type 2", "Type 3", "Type 4", "Type 5"};
-+static const char *w8741_switch[2] = {"Off", "On"};
-+static const struct soc_enum w8741_enum[] = {
-+SOC_ENUM_SINGLE(WM8741_MODE_CONTROL_2, 0, 4, w8741_dither),/* dithering type */
-+SOC_ENUM_SINGLE(WM8741_FILTER_CONTROL, 0, 5, w8741_filter),/* filter type */
-+SOC_ENUM_SINGLE(WM8741_FORMAT_CONTROL, 6, 2, w8741_switch),/* phase invert */
-+SOC_ENUM_SINGLE(WM8741_VOLUME_CONTROL, 0, 2, w8741_switch),/* volume ramp */
-+SOC_ENUM_SINGLE(WM8741_VOLUME_CONTROL, 3, 2, w8741_switch),/* soft mute */
-+};
-+
-+static const struct snd_kcontrol_new w8741_snd_controls_stereo[] = {
-+SOC_DOUBLE_R_TLV("DAC Fine Playback Volume", WM8741_DACLLSB_ATTENUATION,
-+		WM8741_DACRLSB_ATTENUATION, 0, 31, 1, dac_tlv_fine),
-+SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8741_DACLMSB_ATTENUATION,
-+		WM8741_DACRMSB_ATTENUATION, 0, 31, 1, dac_tlv_coarse),
-+SOC_ENUM("DAC Dither", w8741_enum[0]),
-+SOC_ENUM("DAC Digital Filter", w8741_enum[1]),
-+SOC_ENUM("DAC Phase Invert", w8741_enum[2]),
-+SOC_ENUM("DAC Volume Ramp", w8741_enum[3]),
-+SOC_ENUM("DAC Soft Mute", w8741_enum[4]),
-+};
-+
-+static const struct snd_kcontrol_new w8741_snd_controls_mono_left[] = {
-+SOC_SINGLE_TLV("DAC Fine Playback Volume", WM8741_DACLLSB_ATTENUATION,
-+		0, 31, 0, dac_tlv_fine),
-+SOC_SINGLE_TLV("Digital Playback Volume", WM8741_DACLMSB_ATTENUATION,
-+		0, 31, 1, dac_tlv_coarse),
-+SOC_ENUM("DAC Dither", w8741_enum[0]),
-+SOC_ENUM("DAC Digital Filter", w8741_enum[1]),
-+SOC_ENUM("DAC Phase Invert", w8741_enum[2]),
-+SOC_ENUM("DAC Volume Ramp", w8741_enum[3]),
-+SOC_ENUM("DAC Soft Mute", w8741_enum[4]),
-+};
-+
-+static const struct snd_kcontrol_new w8741_snd_controls_mono_right[] = {
-+SOC_SINGLE_TLV("DAC Fine Playback Volume", WM8741_DACRLSB_ATTENUATION,
-+	0, 31, 0, dac_tlv_fine),
-+SOC_SINGLE_TLV("Digital Playback Volume", WM8741_DACRMSB_ATTENUATION,
-+	0, 31, 1, dac_tlv_coarse),
-+SOC_ENUM("DAC Dither", w8741_enum[0]),
-+SOC_ENUM("DAC Digital Filter", w8741_enum[1]),
-+SOC_ENUM("DAC Phase Invert", w8741_enum[2]),
-+SOC_ENUM("DAC Volume Ramp", w8741_enum[3]),
-+SOC_ENUM("DAC Soft Mute", w8741_enum[4]),
-+};
-+
-+static int w8741_add_controls(struct snd_soc_codec *codec)
-+{
-+	struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);
-+
-+	switch (wm8741->pdata.diff_mode) {
-+	case WM8741_DIFF_MODE_STEREO:
-+	case WM8741_DIFF_MODE_STEREO_REVERSED:
-+		snd_soc_add_codec_controls(codec,
-+				w8741_snd_controls_stereo,
-+				ARRAY_SIZE(w8741_snd_controls_stereo));
-+		break;
-+	case WM8741_DIFF_MODE_MONO_LEFT:
-+		snd_soc_add_codec_controls(codec,
-+				w8741_snd_controls_mono_left,
-+				ARRAY_SIZE(w8741_snd_controls_mono_left));
-+		break;
-+	case WM8741_DIFF_MODE_MONO_RIGHT:
-+		snd_soc_add_codec_controls(codec,
-+				w8741_snd_controls_mono_right,
-+				ARRAY_SIZE(w8741_snd_controls_mono_right));
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int digidac1_soundcard_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_card *card = rtd->card;
-+	struct snd_soc_pcm_runtime *wm8741_rtd;
-+	struct snd_soc_codec *wm8741_codec;
-+	struct snd_card *sound_card = card->snd_card;
-+	struct snd_kcontrol *kctl;
-+	int ret;
-+
-+	wm8741_rtd = snd_soc_get_pcm_runtime(card, card->dai_link[1].name);
-+	if (!wm8741_rtd) {
-+		dev_warn(card->dev, "digidac1_soundcard_init: couldn't get wm8741 rtd\n");
-+		return -EFAULT;
-+	}
-+	wm8741_codec = wm8741_rtd->codec;
-+	ret = w8741_add_controls(wm8741_codec);
-+	if (ret < 0)
-+		dev_warn(card->dev, "Failed to add new wm8741 controls: %d\n",
-+		ret);
-+
-+	/* enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	kctl = snd_soc_card_get_kcontrol(card,
-+		"Playback Volume");
-+	if (kctl) {
-+		kctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
-+		snd_ctl_remove(sound_card, kctl);
-+		}
-+	kctl = snd_soc_card_get_kcontrol(card,
-+		"Fine Playback Volume");
-+	if (kctl) {
-+		kctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
-+		snd_ctl_remove(sound_card, kctl);
-+		}
-+	return 0;
-+}
-+
-+static int digidac1_soundcard_startup(struct snd_pcm_substream *substream)
-+{
-+	/* turn on wm8804 digital output */
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_card *card = rtd->card;
-+	struct snd_soc_pcm_runtime *wm8741_rtd;
-+	struct snd_soc_codec *wm8741_codec;
-+
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00);
-+	wm8741_rtd = snd_soc_get_pcm_runtime(card, card->dai_link[1].name);
-+	if (!wm8741_rtd) {
-+		dev_warn(card->dev, "digidac1_soundcard_startup: couldn't get WM8741 rtd\n");
-+		return -EFAULT;
-+	}
-+	wm8741_codec = wm8741_rtd->codec;
-+
-+	/* latch wm8741 level */
-+	snd_soc_update_bits(wm8741_codec, WM8741_DACLLSB_ATTENUATION,
-+		WM8741_UPDATELL, WM8741_UPDATELL);
-+	snd_soc_update_bits(wm8741_codec, WM8741_DACLMSB_ATTENUATION,
-+		WM8741_UPDATELM, WM8741_UPDATELM);
-+	snd_soc_update_bits(wm8741_codec, WM8741_DACRLSB_ATTENUATION,
-+		WM8741_UPDATERL, WM8741_UPDATERL);
-+	snd_soc_update_bits(wm8741_codec, WM8741_DACRMSB_ATTENUATION,
-+		WM8741_UPDATERM, WM8741_UPDATERM);
-+
-+	return 0;
-+}
-+
-+static void digidac1_soundcard_shutdown(struct snd_pcm_substream *substream)
-+{
-+	/* turn off wm8804 digital output */
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c);
-+}
-+
-+static int digidac1_soundcard_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+	struct snd_soc_card *card = rtd->card;
-+	struct snd_soc_pcm_runtime *wm8741_rtd;
-+	struct snd_soc_codec *wm8741_codec;
-+
-+	int sysclk = 27000000;
-+	long mclk_freq = 0;
-+	int mclk_div = 1;
-+	int sampling_freq = 1;
-+	int ret;
-+
-+	wm8741_rtd = snd_soc_get_pcm_runtime(card, card->dai_link[1].name);
-+	if (!wm8741_rtd) {
-+		dev_warn(card->dev, "digidac1_soundcard_hw_params: couldn't get WM8741 rtd\n");
-+		return -EFAULT;
-+	}
-+	wm8741_codec = wm8741_rtd->codec;
-+	samplerate = params_rate(params);
-+
-+	if (samplerate <= 96000) {
-+		mclk_freq = samplerate*256;
-+		mclk_div = WM8804_MCLKDIV_256FS;
-+	} else {
-+		mclk_freq = samplerate*128;
-+		mclk_div = WM8804_MCLKDIV_128FS;
-+		}
-+
-+	switch (samplerate) {
-+	case 32000:
-+		sampling_freq = 0x03;
-+		break;
-+	case 44100:
-+		sampling_freq = 0x00;
-+		break;
-+	case 48000:
-+		sampling_freq = 0x02;
-+		break;
-+	case 88200:
-+		sampling_freq = 0x08;
-+		break;
-+	case 96000:
-+		sampling_freq = 0x0a;
-+		break;
-+	case 176400:
-+		sampling_freq = 0x0c;
-+		break;
-+	case 192000:
-+		sampling_freq = 0x0e;
-+		break;
-+	default:
-+		dev_err(codec->dev,
-+		"Failed to set WM8804 SYSCLK, unsupported samplerate %d\n",
-+		samplerate);
-+	}
-+
-+	snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
-+	snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
-+
-+	ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
-+		sysclk, SND_SOC_CLOCK_OUT);
-+	if (ret < 0) {
-+		dev_err(codec->dev,
-+		"Failed to set WM8804 SYSCLK: %d\n", ret);
-+		return ret;
-+	}
-+	/* Enable wm8804 TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	/* wm8804 Power on */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
-+
-+	/* wm8804 set sampling frequency status bits */
-+	snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq);
-+
-+	/* Now update wm8741 registers for the correct oversampling */
-+	if (samplerate <= 48000)
-+		snd_soc_update_bits(wm8741_codec, WM8741_MODE_CONTROL_1,
-+		 WM8741_OSR_MASK, 0x00);
-+	else if (samplerate <= 96000)
-+		snd_soc_update_bits(wm8741_codec, WM8741_MODE_CONTROL_1,
-+		 WM8741_OSR_MASK, 0x20);
-+	else
-+		snd_soc_update_bits(wm8741_codec, WM8741_MODE_CONTROL_1,
-+		 WM8741_OSR_MASK, 0x40);
-+
-+	/* wm8741 bit size */
-+	switch (params_width(params)) {
-+	case 16:
-+		snd_soc_update_bits(wm8741_codec, WM8741_FORMAT_CONTROL,
-+		 WM8741_IWL_MASK, 0x00);
-+		break;
-+	case 20:
-+		snd_soc_update_bits(wm8741_codec, WM8741_FORMAT_CONTROL,
-+		 WM8741_IWL_MASK, 0x01);
-+		break;
-+	case 24:
-+		snd_soc_update_bits(wm8741_codec, WM8741_FORMAT_CONTROL,
-+		 WM8741_IWL_MASK, 0x02);
-+		break;
-+	case 32:
-+		snd_soc_update_bits(wm8741_codec, WM8741_FORMAT_CONTROL,
-+		 WM8741_IWL_MASK, 0x03);
-+		break;
-+	default:
-+		dev_dbg(codec->dev, "wm8741_hw_params:    Unsupported bit size param = %d",
-+			params_width(params));
-+		return -EINVAL;
-+	}
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+}
-+/* machine stream operations */
-+static struct snd_soc_ops digidac1_soundcard_ops = {
-+	.hw_params	= digidac1_soundcard_hw_params,
-+	.startup	= digidac1_soundcard_startup,
-+	.shutdown	= digidac1_soundcard_shutdown,
-+};
-+
-+static struct snd_soc_dai_link digidac1_soundcard_dai[] = {
-+	{
-+	.name		= "RRA DigiDAC1",
-+	.stream_name	= "RRA DigiDAC1 HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "wm8804-spdif",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "wm8804.1-003b",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBM_CFM,
-+	.ops		= &digidac1_soundcard_ops,
-+	.init		= digidac1_soundcard_init,
-+	},
-+	{
-+	.name		= "RRA DigiDAC11",
-+	.stream_name	= "RRA DigiDAC11 HiFi",
-+	.cpu_dai_name	= "wm8804-spdif",
-+	.codec_dai_name	= "wm8741",
-+	.codec_name	= "wm8741.1-001a",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S
-+			| SND_SOC_DAIFMT_NB_NF
-+			| SND_SOC_DAIFMT_CBS_CFS,
-+	},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card digidac1_soundcard = {
-+	.name		= "digidac1-soundcard",
-+	.owner		= THIS_MODULE,
-+	.dai_link	= digidac1_soundcard_dai,
-+	.num_links	= ARRAY_SIZE(digidac1_soundcard_dai),
-+};
-+
-+static int digidac1_soundcard_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	digidac1_soundcard.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai = &digidac1_soundcard_dai[0];
-+
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					"i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+	}
-+
-+	ret = snd_soc_register_card(&digidac1_soundcard);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
-+			ret);
-+
-+	return ret;
-+}
-+
-+static int digidac1_soundcard_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&digidac1_soundcard);
-+}
-+
-+static const struct of_device_id digidac1_soundcard_of_match[] = {
-+	{ .compatible = "rra,digidac1-soundcard", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, digidac1_soundcard_of_match);
-+
-+static struct platform_driver digidac1_soundcard_driver = {
-+	.driver = {
-+			.name		= "digidac1-audio",
-+			.owner		= THIS_MODULE,
-+			.of_match_table	= digidac1_soundcard_of_match,
-+	},
-+	.probe		= digidac1_soundcard_probe,
-+	.remove		= digidac1_soundcard_remove,
-+};
-+
-+module_platform_driver(digidac1_soundcard_driver);
-+
-+MODULE_AUTHOR("José M. Tasende <vintage@redrocksaudio.es>");
-+MODULE_DESCRIPTION("ASoC Driver for RRA DigiDAC1");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0078-Add-support-for-Dion-Audio-LOCO-DAC-AMP-HAT.patch b/target/linux/brcm2708/patches-4.14/950-0078-Add-support-for-Dion-Audio-LOCO-DAC-AMP-HAT.patch
deleted file mode 100644
index b4100f889..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0078-Add-support-for-Dion-Audio-LOCO-DAC-AMP-HAT.patch
+++ /dev/null
@@ -1,168 +0,0 @@
-From 9c8fd5fed9eab2705563f65ee898ef6ccce9333f Mon Sep 17 00:00:00 2001
-From: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
-Date: Sat, 2 Jul 2016 16:26:19 +0100
-Subject: [PATCH 078/454] Add support for Dion Audio LOCO DAC-AMP HAT
-
-Using dedicated machine driver and pcm5102a codec driver.
-
-Signed-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
----
- sound/soc/bcm/Kconfig          |   7 ++
- sound/soc/bcm/Makefile         |   3 +-
- sound/soc/bcm/dionaudio_loco.c | 121 +++++++++++++++++++++++++++++++++
- 3 files changed, 130 insertions(+), 1 deletion(-)
- create mode 100644 sound/soc/bcm/dionaudio_loco.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -117,3 +117,10 @@ config SND_DIGIDAC1_SOUNDCARD
-         select SND_SOC_WM8741
-         help
-          Say Y or M if you want to add support for Red Rocks Audio DigiDAC1 board.
-+
-+config SND_BCM2708_SOC_DIONAUDIO_LOCO
-+	tristate "Support for Dion Audio LOCO DAC-AMP"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM5102a
-+	help
-+	  Say Y or M if you want to add support for Dion Audio LOCO.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -23,6 +23,7 @@ snd-soc-iqaudio-digi-objs := iqaudio_dig
- snd-soc-raspidac3-objs := raspidac3.o
- snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
- snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o
-+snd-soc-dionaudio-loco-objs := dionaudio_loco.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-@@ -38,4 +39,4 @@ obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DIG
- obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o
- obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
- obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o
--
-+obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o
---- /dev/null
-+++ b/sound/soc/bcm/dionaudio_loco.c
-@@ -0,0 +1,121 @@
-+/*
-+ * ASoC Driver for Dion Audio LOCO DAC-AMP
-+ *
-+ * Author:      Miquel Blauw <info@dionaudio.nl>
-+ *              Copyright 2016
-+ *
-+ * Based on the software of the RPi-DAC writen by Florian Meier
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_dionaudio_loco_hw_params(
-+	struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_dionaudio_loco_ops = {
-+	.hw_params = snd_rpi_dionaudio_loco_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_dionaudio_loco_dai[] = {
-+{
-+	.name		= "DionAudio LOCO",
-+	.stream_name	= "DionAudio LOCO DAC-AMP",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm5102a-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm5102a-codec",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S |
-+			  SND_SOC_DAIFMT_NB_NF |
-+			  SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_dionaudio_loco_ops,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_dionaudio_loco = {
-+	.name		= "snd_rpi_dionaudio_loco",
-+	.dai_link	= snd_rpi_dionaudio_loco_dai,
-+	.num_links	= ARRAY_SIZE(snd_rpi_dionaudio_loco_dai),
-+};
-+
-+static int snd_rpi_dionaudio_loco_probe(struct platform_device *pdev)
-+{
-+	struct device_node *np;
-+	int ret = 0;
-+
-+	snd_rpi_dionaudio_loco.dev = &pdev->dev;
-+
-+	np = pdev->dev.of_node;
-+	if (np) {
-+		struct snd_soc_dai_link *dai = &snd_rpi_dionaudio_loco_dai[0];
-+		struct device_node *i2s_np;
-+
-+		i2s_np = of_parse_phandle(np, "i2s-controller", 0);
-+		if (i2s_np) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_np;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_np;
-+		}
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_dionaudio_loco);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
-+			ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_dionaudio_loco_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_dionaudio_loco);
-+}
-+
-+static const struct of_device_id snd_rpi_dionaudio_loco_of_match[] = {
-+	{ .compatible = "dionaudio,loco-pcm5242-tpa3118", },
-+	{ /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_dionaudio_loco_of_match);
-+
-+static struct platform_driver snd_rpi_dionaudio_loco_driver = {
-+	.driver = {
-+		.name		= "snd-dionaudio-loco",
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= snd_rpi_dionaudio_loco_of_match,
-+	},
-+	.probe  = snd_rpi_dionaudio_loco_probe,
-+	.remove = snd_rpi_dionaudio_loco_remove,
-+};
-+
-+module_platform_driver(snd_rpi_dionaudio_loco_driver);
-+
-+MODULE_AUTHOR("Miquel Blauw <info@dionaudio.nl>");
-+MODULE_DESCRIPTION("ASoC Driver for DionAudio LOCO");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0079-Allo-Piano-DAC-boards-Initial-2-channel-stereo-suppo.patch b/target/linux/brcm2708/patches-4.14/950-0079-Allo-Piano-DAC-boards-Initial-2-channel-stereo-suppo.patch
deleted file mode 100644
index cf461bb14..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0079-Allo-Piano-DAC-boards-Initial-2-channel-stereo-suppo.patch
+++ /dev/null
@@ -1,202 +0,0 @@
-From 661bd422e6881e357a9e267548e446bdff71a797 Mon Sep 17 00:00:00 2001
-From: Clive Messer <clive.m.messer@gmail.com>
-Date: Mon, 19 Sep 2016 14:01:04 +0100
-Subject: [PATCH 079/454] Allo Piano DAC boards: Initial 2 channel (stereo)
- support (#1645)
-
-Add initial 2 channel (stereo) support for Allo Piano DAC (2.0/2.1) boards,
-using allo-piano-dac-pcm512x-audio overlay and allo-piano-dac ALSA ASoC
-machine driver.
-
-NB. The initial support is 2 channel (stereo) ONLY!
-(The Piano DAC 2.1 will only support 2 channel (stereo) left/right output,
- pending an update to the upstream pcm512x codec driver, which will have
- to be submitted via upstream. With the initial downstream support,
- provided by this patch, the Piano DAC 2.1 subwoofer outputs will
- not function.)
-
-Signed-off-by: Baswaraj K <jaikumar@cem-solutions.net>
-Signed-off-by: Clive Messer <clive.messer@digitaldreamtime.co.uk>
-Tested-by: Clive Messer <clive.messer@digitaldreamtime.co.uk>
----
- sound/soc/bcm/Kconfig          |   7 ++
- sound/soc/bcm/Makefile         |   2 +
- sound/soc/bcm/allo-piano-dac.c | 144 +++++++++++++++++++++++++++++++++
- 3 files changed, 153 insertions(+)
- create mode 100644 sound/soc/bcm/allo-piano-dac.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -124,3 +124,10 @@ config SND_BCM2708_SOC_DIONAUDIO_LOCO
- 	select SND_SOC_PCM5102a
- 	help
- 	  Say Y or M if you want to add support for Dion Audio LOCO.
-+
-+config SND_BCM2708_SOC_ALLO_PIANO_DAC
-+	tristate "Support for Allo Piano DAC"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM512x_I2C
-+	help
-+	  Say Y or M if you want to add support for Allo Piano DAC.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -24,6 +24,7 @@ snd-soc-raspidac3-objs := raspidac3.o
- snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
- snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o
- snd-soc-dionaudio-loco-objs := dionaudio_loco.o
-+snd-soc-allo-piano-dac-objs := allo-piano-dac.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-@@ -40,3 +41,4 @@ obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3)
- obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
- obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o
- obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o
-+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/allo-piano-dac.c
-@@ -0,0 +1,144 @@
-+/*
-+ * ALSA ASoC Machine Driver for Allo Piano DAC
-+ *
-+ * Author:	Baswaraj K <jaikumar@cem-solutions.net>
-+ *		Copyright 2016
-+ *		based on code by Daniel Matuschek <info@crazy-audio.com>
-+ *		based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+
-+static bool digital_gain_0db_limit = true;
-+
-+static int snd_allo_piano_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	if (digital_gain_0db_limit) {
-+		int ret;
-+		struct snd_soc_card *card = rtd->card;
-+
-+		ret = snd_soc_limit_volume(card, "Digital Playback Volume",
-+					   207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n",
-+				 ret);
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_allo_piano_dac_hw_params(
-+	struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_allo_piano_dac_ops = {
-+	.hw_params = snd_allo_piano_dac_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_allo_piano_dac_dai[] = {
-+{
-+	.name		= "Piano DAC",
-+	.stream_name	= "Piano DAC HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm512x-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm512x.1-004c",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S |
-+			  SND_SOC_DAIFMT_NB_NF |
-+			  SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_allo_piano_dac_ops,
-+	.init		= snd_allo_piano_dac_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_allo_piano_dac = {
-+	.name         = "PianoDAC",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_allo_piano_dac_dai,
-+	.num_links    = ARRAY_SIZE(snd_allo_piano_dac_dai),
-+};
-+
-+static int snd_allo_piano_dac_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_allo_piano_dac.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai;
-+
-+		dai = &snd_allo_piano_dac_dai[0];
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					    "i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+
-+		digital_gain_0db_limit = !of_property_read_bool(
-+			pdev->dev.of_node, "allo,24db_digital_gain");
-+	}
-+
-+	ret = snd_soc_register_card(&snd_allo_piano_dac);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev,
-+			"snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_allo_piano_dac_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_allo_piano_dac);
-+}
-+
-+static const struct of_device_id snd_allo_piano_dac_of_match[] = {
-+	{ .compatible = "allo,piano-dac", },
-+	{ /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, snd_allo_piano_dac_of_match);
-+
-+static struct platform_driver snd_allo_piano_dac_driver = {
-+	.driver = {
-+		.name   = "snd-allo-piano-dac",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_allo_piano_dac_of_match,
-+	},
-+	.probe          = snd_allo_piano_dac_probe,
-+	.remove         = snd_allo_piano_dac_remove,
-+};
-+
-+module_platform_driver(snd_allo_piano_dac_driver);
-+
-+MODULE_AUTHOR("Baswaraj K <jaikumar@cem-solutions.net>");
-+MODULE_DESCRIPTION("ALSA ASoC Machine Driver for Allo Piano DAC");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0080-Add-support-for-Allo-Piano-DAC-2.1-plus-add-on-board.patch b/target/linux/brcm2708/patches-4.14/950-0080-Add-support-for-Allo-Piano-DAC-2.1-plus-add-on-board.patch
deleted file mode 100644
index 04060d92d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0080-Add-support-for-Allo-Piano-DAC-2.1-plus-add-on-board.patch
+++ /dev/null
@@ -1,1083 +0,0 @@
-From 649b1181f032801c12e17196618c032cdb3cb587 Mon Sep 17 00:00:00 2001
-From: Raashid Muhammed <raashidmuhammed@zilogic.com>
-Date: Mon, 27 Mar 2017 12:35:00 +0530
-Subject: [PATCH 080/454] Add support for Allo Piano DAC 2.1 plus add-on board
- for Raspberry Pi.
-
-The Piano DAC 2.1 has support for 4 channels with subwoofer.
-
-Signed-off-by: Baswaraj K <jaikumar@cem-solutions.net>
-Reviewed-by: Vijay Kumar B. <vijaykumar@zilogic.com>
-Reviewed-by: Raashid Muhammed <raashidmuhammed@zilogic.com>
-
-Add clock changes and mute gpios (#1938)
-
-Also improve code style and adhere to ALSA coding conventions.
-
-Signed-off-by: Baswaraj K <jaikumar@cem-solutions.net>
-Reviewed-by: Vijay Kumar B. <vijaykumar@zilogic.com>
-Reviewed-by: Raashid Muhammed <raashidmuhammed@zilogic.com>
-
-PianoPlus: Dual Mono & Dual Stereo features added (#2069)
-
-allo-piano-dac-plus: Master volume added + fixes
-
-Master volume added, which controls both DACs volumes.
-
-See: https://github.com/raspberrypi/linux/pull/2149
-
-Also fix initial max volume, default mode value, and unmute.
-
-Signed-off-by: allocom <sparky-dev@allo.com>
----
- sound/soc/bcm/Kconfig               |    7 +
- sound/soc/bcm/Makefile              |    2 +
- sound/soc/bcm/allo-piano-dac-plus.c | 1014 +++++++++++++++++++++++++++
- 3 files changed, 1023 insertions(+)
- create mode 100644 sound/soc/bcm/allo-piano-dac-plus.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -131,3 +131,10 @@ config SND_BCM2708_SOC_ALLO_PIANO_DAC
- 	select SND_SOC_PCM512x_I2C
- 	help
- 	  Say Y or M if you want to add support for Allo Piano DAC.
-+
-+config SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS
-+	tristate "Support for Allo Piano DAC Plus"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM512x_I2C
-+	help
-+	  Say Y or M if you want to add support for Allo Piano DAC Plus.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -25,6 +25,7 @@ snd-soc-audioinjector-pi-soundcard-objs
- snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o
- snd-soc-dionaudio-loco-objs := dionaudio_loco.o
- snd-soc-allo-piano-dac-objs := allo-piano-dac.o
-+snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-@@ -42,3 +43,4 @@ obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDC
- obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o
- obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o
---- /dev/null
-+++ b/sound/soc/bcm/allo-piano-dac-plus.c
-@@ -0,0 +1,1014 @@
-+/*
-+ * ALSA ASoC Machine Driver for Allo Piano DAC Plus Subwoofer
-+ *
-+ * Author:	Baswaraj K <jaikumar@cem-solutions.net>
-+ *		Copyright 2016
-+ *		based on code by Daniel Matuschek <info@crazy-audio.com>
-+ *		based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/gpio/consumer.h>
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <linux/firmware.h>
-+#include <linux/delay.h>
-+#include <sound/tlv.h>
-+#include "../codecs/pcm512x.h"
-+
-+#define P_DAC_LEFT_MUTE		0x10
-+#define P_DAC_RIGHT_MUTE	0x01
-+#define P_DAC_MUTE		0x11
-+#define P_DAC_UNMUTE		0x00
-+#define P_MUTE			1
-+#define P_UNMUTE		0
-+
-+struct dsp_code {
-+	char i2c_addr;
-+	char offset;
-+	char val;
-+};
-+
-+struct glb_pool {
-+	struct mutex lock;
-+	unsigned int dual_mode;
-+	unsigned int set_lowpass;
-+	unsigned int set_mode;
-+	unsigned int set_rate;
-+	unsigned int dsp_page_number;
-+};
-+
-+static bool digital_gain_0db_limit = true;
-+bool glb_mclk;
-+
-+static struct gpio_desc *mute_gpio[2];
-+
-+static const char * const allo_piano_mode_texts[] = {
-+	"None",
-+	"2.0",
-+	"2.1",
-+	"2.2",
-+};
-+
-+static const SOC_ENUM_SINGLE_DECL(allo_piano_mode_enum,
-+		0, 0, allo_piano_mode_texts);
-+
-+static const char * const allo_piano_dual_mode_texts[] = {
-+	"None",
-+	"Dual-Mono",
-+	"Dual-Stereo",
-+};
-+
-+static const SOC_ENUM_SINGLE_DECL(allo_piano_dual_mode_enum,
-+		0, 0, allo_piano_dual_mode_texts);
-+
-+static const char * const allo_piano_dsp_low_pass_texts[] = {
-+	"60",
-+	"70",
-+	"80",
-+	"90",
-+	"100",
-+	"110",
-+	"120",
-+	"130",
-+	"140",
-+	"150",
-+	"160",
-+	"170",
-+	"180",
-+	"190",
-+	"200",
-+};
-+
-+static const SOC_ENUM_SINGLE_DECL(allo_piano_enum,
-+		0, 0, allo_piano_dsp_low_pass_texts);
-+
-+static int __snd_allo_piano_dsp_program(struct snd_soc_pcm_runtime *rtd,
-+		unsigned int mode, unsigned int rate, unsigned int lowpass)
-+{
-+	const struct firmware *fw;
-+	struct snd_soc_card *card = rtd->card;
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	char firmware_name[60];
-+	int ret = 0, dac = 0;
-+
-+	if (rate <= 46000)
-+		rate = 44100;
-+	else if (rate <= 68000)
-+		rate = 48000;
-+	else if (rate <= 92000)
-+		rate = 88200;
-+	else if (rate <= 136000)
-+		rate = 96000;
-+	else if (rate <= 184000)
-+		rate = 176400;
-+	else
-+		rate = 192000;
-+
-+	if (lowpass > 14)
-+		glb_ptr->set_lowpass = lowpass = 0;
-+
-+	if (mode > 3)
-+		glb_ptr->set_mode = mode = 0;
-+
-+	if (mode > 0)
-+		glb_ptr->dual_mode = 0;
-+
-+	/* same configuration loaded */
-+	if ((rate == glb_ptr->set_rate) && (lowpass == glb_ptr->set_lowpass)
-+			&& (mode == glb_ptr->set_mode))
-+		return 0;
-+
-+	switch (mode) {
-+	case 0: /* None */
-+		return 1;
-+
-+	case 1: /* 2.0 */
-+		snd_soc_write(rtd->codec_dais[0]->codec,
-+				PCM512x_MUTE, P_DAC_UNMUTE);
-+		snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_MUTE, P_DAC_MUTE);
-+		glb_ptr->set_rate = rate;
-+		glb_ptr->set_mode = mode;
-+		glb_ptr->set_lowpass = lowpass;
-+		return 1;
-+
-+	default:
-+		snd_soc_write(rtd->codec_dais[0]->codec,
-+				PCM512x_MUTE, P_DAC_UNMUTE);
-+		snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_MUTE, P_DAC_UNMUTE);
-+	}
-+
-+	for (dac = 0; dac < rtd->num_codecs; dac++) {
-+		struct dsp_code *dsp_code_read;
-+		struct snd_soc_codec *codec = rtd->codec_dais[dac]->codec;
-+		int i = 1;
-+
-+		if (dac == 0) { /* high */
-+			snprintf(firmware_name, sizeof(firmware_name),
-+				"allo/piano/2.2/allo-piano-dsp-%d-%d-%d.bin",
-+				rate, ((lowpass * 10) + 60), dac);
-+		} else { /* low */
-+			snprintf(firmware_name, sizeof(firmware_name),
-+				"allo/piano/2.%d/allo-piano-dsp-%d-%d-%d.bin",
-+				(mode - 1), rate, ((lowpass * 10) + 60), dac);
-+		}
-+
-+		dev_info(codec->dev, "Dsp Firmware File Name: %s\n",
-+				firmware_name);
-+
-+		ret = request_firmware(&fw, firmware_name, codec->dev);
-+		if (ret < 0) {
-+			dev_err(codec->dev,
-+				"Error: Allo Piano Firmware %s missing. %d\n",
-+				firmware_name, ret);
-+			goto err;
-+		}
-+
-+		while (i < (fw->size - 1)) {
-+			dsp_code_read = (struct dsp_code *)&fw->data[i];
-+
-+			if (dsp_code_read->offset == 0) {
-+				glb_ptr->dsp_page_number = dsp_code_read->val;
-+				ret = snd_soc_write(rtd->codec_dais[dac]->codec,
-+						PCM512x_PAGE_BASE(0),
-+						dsp_code_read->val);
-+
-+			} else if (dsp_code_read->offset != 0) {
-+				ret = snd_soc_write(rtd->codec_dais[dac]->codec,
-+					(PCM512x_PAGE_BASE(
-+						glb_ptr->dsp_page_number) +
-+					dsp_code_read->offset),
-+					dsp_code_read->val);
-+			}
-+			if (ret < 0) {
-+				dev_err(codec->dev,
-+					"Failed to write Register: %d\n", ret);
-+				release_firmware(fw);
-+				goto err;
-+			}
-+			i = i + 3;
-+		}
-+		release_firmware(fw);
-+	}
-+	glb_ptr->set_rate = rate;
-+	glb_ptr->set_mode = mode;
-+	glb_ptr->set_lowpass = lowpass;
-+	return 1;
-+
-+err:
-+	return ret;
-+}
-+
-+static int snd_allo_piano_dsp_program(struct snd_soc_pcm_runtime *rtd,
-+		unsigned int mode, unsigned int rate, unsigned int lowpass)
-+{
-+	struct snd_soc_card *card = rtd->card;
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	int ret = 0;
-+
-+	mutex_lock(&glb_ptr->lock);
-+
-+	ret = __snd_allo_piano_dsp_program(rtd, mode, rate, lowpass);
-+
-+	mutex_unlock(&glb_ptr->lock);
-+
-+	return ret;
-+}
-+
-+static int snd_allo_piano_dual_mode_get(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+
-+	ucontrol->value.integer.value[0] = glb_ptr->dual_mode;
-+
-+	return 0;
-+}
-+
-+static int snd_allo_piano_dual_mode_put(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	struct snd_soc_pcm_runtime *rtd;
-+	struct snd_card *snd_card_ptr = card->snd_card;
-+	struct snd_kcontrol *kctl;
-+	struct soc_mixer_control *mc;
-+	unsigned int left_val = 0, right_val = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+
-+	if (ucontrol->value.integer.value[0] > 0) {
-+		glb_ptr->dual_mode = ucontrol->value.integer.value[0];
-+		glb_ptr->set_mode = 0;
-+	} else {
-+		if (glb_ptr->set_mode <= 0) {
-+			glb_ptr->dual_mode = 1;
-+			glb_ptr->set_mode = 0;
-+		} else {
-+			glb_ptr->dual_mode = 0;
-+			return 0;
-+		}
-+	}
-+
-+	if (glb_ptr->dual_mode == 1) { // Dual Mono
-+		snd_soc_write(rtd->codec_dais[0]->codec,
-+				PCM512x_MUTE, P_DAC_RIGHT_MUTE);
-+		snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_MUTE, P_DAC_LEFT_MUTE);
-+		snd_soc_write(rtd->codec_dais[0]->codec,
-+				PCM512x_DIGITAL_VOLUME_3, 0xff);
-+		snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_DIGITAL_VOLUME_2, 0xff);
-+
-+		list_for_each_entry(kctl, &snd_card_ptr->controls, list) {
-+			if (!strncmp(kctl->id.name, "Digital Playback Volume",
-+					sizeof(kctl->id.name))) {
-+				mc = (struct soc_mixer_control *)
-+					kctl->private_value;
-+				mc->rreg = mc->reg;
-+				break;
-+			}
-+		}
-+	} else {
-+		left_val = snd_soc_read(rtd->codec_dais[0]->codec,
-+						PCM512x_DIGITAL_VOLUME_2);
-+		right_val = snd_soc_read(rtd->codec_dais[1]->codec,
-+						PCM512x_DIGITAL_VOLUME_3);
-+
-+		list_for_each_entry(kctl, &snd_card_ptr->controls, list) {
-+			if (!strncmp(kctl->id.name, "Digital Playback Volume",
-+					sizeof(kctl->id.name))) {
-+				mc = (struct soc_mixer_control *)
-+					kctl->private_value;
-+				mc->rreg = PCM512x_DIGITAL_VOLUME_3;
-+				break;
-+			}
-+		}
-+
-+		snd_soc_write(rtd->codec_dais[0]->codec,
-+				PCM512x_DIGITAL_VOLUME_3, left_val);
-+		snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_DIGITAL_VOLUME_2, right_val);
-+		snd_soc_write(rtd->codec_dais[0]->codec,
-+				PCM512x_MUTE, P_DAC_UNMUTE);
-+		snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_MUTE, P_DAC_UNMUTE);
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_allo_piano_mode_get(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+
-+	ucontrol->value.integer.value[0] = glb_ptr->set_mode;
-+	return 0;
-+}
-+
-+static int snd_allo_piano_mode_put(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_pcm_runtime *rtd;
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	struct snd_card *snd_card_ptr = card->snd_card;
-+	struct snd_kcontrol *kctl;
-+	struct soc_mixer_control *mc;
-+	unsigned int left_val = 0, right_val = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+
-+	if ((glb_ptr->dual_mode == 1) &&
-+			(ucontrol->value.integer.value[0] > 0)) {
-+		left_val = snd_soc_read(rtd->codec_dais[0]->codec,
-+						PCM512x_DIGITAL_VOLUME_2);
-+		right_val = snd_soc_read(rtd->codec_dais[1]->codec,
-+						PCM512x_DIGITAL_VOLUME_2);
-+
-+		list_for_each_entry(kctl, &snd_card_ptr->controls, list) {
-+			if (!strncmp(kctl->id.name, "Digital Playback Volume",
-+					sizeof(kctl->id.name))) {
-+				mc = (struct soc_mixer_control *)
-+					kctl->private_value;
-+				mc->rreg = PCM512x_DIGITAL_VOLUME_3;
-+				break;
-+			}
-+		}
-+		snd_soc_write(rtd->codec_dais[0]->codec,
-+				PCM512x_DIGITAL_VOLUME_3, left_val);
-+		snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_DIGITAL_VOLUME_3, right_val);
-+	}
-+
-+	return(snd_allo_piano_dsp_program(rtd,
-+				ucontrol->value.integer.value[0],
-+				glb_ptr->set_rate, glb_ptr->set_lowpass));
-+}
-+
-+static int snd_allo_piano_lowpass_get(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+
-+	ucontrol->value.integer.value[0] = glb_ptr->set_lowpass;
-+	return 0;
-+}
-+
-+static int snd_allo_piano_lowpass_put(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_pcm_runtime *rtd;
-+	struct glb_pool *glb_ptr = card->drvdata;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	return(snd_allo_piano_dsp_program(rtd,
-+				glb_ptr->set_mode, glb_ptr->set_rate,
-+				ucontrol->value.integer.value[0]));
-+}
-+
-+static int pcm512x_get_reg_sub(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct soc_mixer_control *mc =
-+		(struct soc_mixer_control *)kcontrol->private_value;
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	struct snd_soc_pcm_runtime *rtd;
-+	unsigned int left_val = 0;
-+	unsigned int right_val = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	right_val = snd_soc_read(rtd->codec_dais[1]->codec,
-+			PCM512x_DIGITAL_VOLUME_3);
-+	if (right_val < 0)
-+		return right_val;
-+
-+	if (glb_ptr->dual_mode != 1) {
-+		left_val = snd_soc_read(rtd->codec_dais[1]->codec,
-+				PCM512x_DIGITAL_VOLUME_2);
-+		if (left_val < 0)
-+			return left_val;
-+
-+	} else {
-+		left_val = right_val;
-+	}
-+
-+	ucontrol->value.integer.value[0] =
-+				(~(left_val >> mc->shift)) & mc->max;
-+	ucontrol->value.integer.value[1] =
-+				(~(right_val >> mc->shift)) & mc->max;
-+
-+	return 0;
-+}
-+
-+static int pcm512x_set_reg_sub(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct soc_mixer_control *mc =
-+		(struct soc_mixer_control *)kcontrol->private_value;
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	struct snd_soc_pcm_runtime *rtd;
-+	unsigned int left_val = (ucontrol->value.integer.value[0] & mc->max);
-+	unsigned int right_val = (ucontrol->value.integer.value[1] & mc->max);
-+	int ret = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	if (glb_ptr->dual_mode != 1) {
-+		ret = snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_DIGITAL_VOLUME_2, (~left_val));
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	if (digital_gain_0db_limit) {
-+		ret = snd_soc_limit_volume(card, "Subwoofer Playback Volume",
-+					207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n",
-+				ret);
-+	}
-+
-+	ret = snd_soc_write(rtd->codec_dais[1]->codec,
-+			PCM512x_DIGITAL_VOLUME_3, (~right_val));
-+	if (ret < 0)
-+		return ret;
-+
-+	return 1;
-+}
-+
-+static int pcm512x_get_reg_sub_switch(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_pcm_runtime *rtd;
-+	int val = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	val = snd_soc_read(rtd->codec_dais[1]->codec, PCM512x_MUTE);
-+	if (val < 0)
-+		return val;
-+
-+	ucontrol->value.integer.value[0] =
-+			(val & P_DAC_LEFT_MUTE) ? P_UNMUTE : P_MUTE;
-+	ucontrol->value.integer.value[1] =
-+			(val & P_DAC_RIGHT_MUTE) ? P_UNMUTE : P_MUTE;
-+
-+	return val;
-+}
-+
-+static int pcm512x_set_reg_sub_switch(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_pcm_runtime *rtd;
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	unsigned int left_val = (ucontrol->value.integer.value[0]);
-+	unsigned int right_val = (ucontrol->value.integer.value[1]);
-+	int ret = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	if (glb_ptr->set_mode != 1) {
-+		ret = snd_soc_write(rtd->codec_dais[1]->codec, PCM512x_MUTE,
-+				~((left_val & 0x01)<<4 | (right_val & 0x01)));
-+		if (ret < 0)
-+			return ret;
-+	}
-+	return 1;
-+
-+}
-+
-+static int pcm512x_get_reg_master(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct soc_mixer_control *mc =
-+		(struct soc_mixer_control *)kcontrol->private_value;
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	struct snd_soc_pcm_runtime *rtd;
-+	unsigned int left_val = 0, right_val = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+
-+	left_val = snd_soc_read(rtd->codec_dais[0]->codec,
-+			PCM512x_DIGITAL_VOLUME_2);
-+	if (left_val < 0)
-+		return left_val;
-+
-+	if (glb_ptr->dual_mode == 1) {
-+		right_val = snd_soc_read(rtd->codec_dais[1]->codec,
-+				PCM512x_DIGITAL_VOLUME_3);
-+		if (right_val < 0)
-+			return right_val;
-+	} else {
-+		right_val = snd_soc_read(rtd->codec_dais[0]->codec,
-+				PCM512x_DIGITAL_VOLUME_3);
-+		if (right_val < 0)
-+			return right_val;
-+	}
-+
-+	ucontrol->value.integer.value[0] =
-+		(~(left_val  >> mc->shift)) & mc->max;
-+	ucontrol->value.integer.value[1] =
-+		(~(right_val >> mc->shift)) & mc->max;
-+
-+	return 0;
-+}
-+
-+static int pcm512x_set_reg_master(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct soc_mixer_control *mc =
-+		(struct soc_mixer_control *)kcontrol->private_value;
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	struct snd_soc_pcm_runtime *rtd;
-+	unsigned int left_val = (ucontrol->value.integer.value[0] & mc->max);
-+	unsigned int right_val = (ucontrol->value.integer.value[1] & mc->max);
-+	int ret = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+
-+	if (digital_gain_0db_limit) {
-+		ret = snd_soc_limit_volume(card, "Master Playback Volume",
-+					207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n",
-+				ret);
-+	}
-+
-+	if (glb_ptr->dual_mode != 1) {
-+		ret = snd_soc_write(rtd->codec_dais[1]->codec,
-+				PCM512x_DIGITAL_VOLUME_2, (~left_val));
-+		if (ret < 0)
-+			return ret;
-+
-+		ret = snd_soc_write(rtd->codec_dais[0]->codec,
-+				PCM512x_DIGITAL_VOLUME_3, (~right_val));
-+		if (ret < 0)
-+			return ret;
-+
-+	}
-+
-+	ret = snd_soc_write(rtd->codec_dais[1]->codec,
-+			PCM512x_DIGITAL_VOLUME_3, (~right_val));
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = snd_soc_write(rtd->codec_dais[0]->codec,
-+			PCM512x_DIGITAL_VOLUME_2, (~left_val));
-+	if (ret < 0)
-+		return ret;
-+	return 1;
-+}
-+
-+static int pcm512x_get_reg_master_switch(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	struct snd_soc_pcm_runtime *rtd;
-+	int val = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+
-+	val = snd_soc_read(rtd->codec_dais[0]->codec, PCM512x_MUTE);
-+	if (val < 0)
-+		return val;
-+
-+	ucontrol->value.integer.value[0] =
-+			(val & P_DAC_LEFT_MUTE) ? P_UNMUTE : P_MUTE;
-+
-+	if (glb_ptr->dual_mode == 1) {
-+		val = snd_soc_read(rtd->codec_dais[1]->codec, PCM512x_MUTE);
-+		if (val < 0)
-+			return val;
-+	}
-+	ucontrol->value.integer.value[1] =
-+			(val & P_DAC_RIGHT_MUTE) ? P_UNMUTE : P_MUTE;
-+
-+	return val;
-+}
-+
-+static int pcm512x_set_reg_master_switch(struct snd_kcontrol *kcontrol,
-+		struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_pcm_runtime *rtd;
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	unsigned int left_val = (ucontrol->value.integer.value[0]);
-+	unsigned int right_val = (ucontrol->value.integer.value[1]);
-+	int ret = 0;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	if (glb_ptr->dual_mode == 1) {
-+		ret = snd_soc_write(rtd->codec_dais[0]->codec, PCM512x_MUTE,
-+				~((left_val & 0x01)<<4));
-+		if (ret < 0)
-+			return ret;
-+		ret = snd_soc_write(rtd->codec_dais[1]->codec, PCM512x_MUTE,
-+				~((right_val & 0x01)));
-+		if (ret < 0)
-+			return ret;
-+
-+	} else if (glb_ptr->set_mode == 1) {
-+		ret = snd_soc_write(rtd->codec_dais[0]->codec, PCM512x_MUTE,
-+				~((left_val & 0x01)<<4 | (right_val & 0x01)));
-+		if (ret < 0)
-+			return ret;
-+
-+	} else {
-+		ret = snd_soc_write(rtd->codec_dais[0]->codec, PCM512x_MUTE,
-+				~((left_val & 0x01)<<4 | (right_val & 0x01)));
-+		if (ret < 0)
-+			return ret;
-+
-+		ret = snd_soc_write(rtd->codec_dais[1]->codec, PCM512x_MUTE,
-+				~((left_val & 0x01)<<4 | (right_val & 0x01)));
-+		if (ret < 0)
-+			return ret;
-+	}
-+	return 1;
-+}
-+
-+static const DECLARE_TLV_DB_SCALE(digital_tlv_sub, -10350, 50, 1);
-+static const DECLARE_TLV_DB_SCALE(digital_tlv_master, -10350, 50, 1);
-+
-+static const struct snd_kcontrol_new allo_piano_controls[] = {
-+	SOC_ENUM_EXT("Subwoofer mode Route",
-+			allo_piano_mode_enum,
-+			snd_allo_piano_mode_get,
-+			snd_allo_piano_mode_put),
-+
-+	SOC_ENUM_EXT("Dual Mode Route",
-+			allo_piano_dual_mode_enum,
-+			snd_allo_piano_dual_mode_get,
-+			snd_allo_piano_dual_mode_put),
-+
-+	SOC_ENUM_EXT("Lowpass Route", allo_piano_enum,
-+			snd_allo_piano_lowpass_get,
-+			snd_allo_piano_lowpass_put),
-+
-+	SOC_DOUBLE_R_EXT_TLV("Subwoofer Playback Volume",
-+			PCM512x_DIGITAL_VOLUME_2,
-+			PCM512x_DIGITAL_VOLUME_3, 0, 255, 1,
-+			pcm512x_get_reg_sub,
-+			pcm512x_set_reg_sub,
-+			digital_tlv_sub),
-+
-+	SOC_DOUBLE_EXT("Subwoofer Playback Switch",
-+			PCM512x_MUTE,
-+			PCM512x_RQML_SHIFT,
-+			PCM512x_RQMR_SHIFT, 1, 1,
-+			pcm512x_get_reg_sub_switch,
-+			pcm512x_set_reg_sub_switch),
-+
-+	SOC_DOUBLE_R_EXT_TLV("Master Playback Volume",
-+			PCM512x_DIGITAL_VOLUME_2,
-+			PCM512x_DIGITAL_VOLUME_3, 0, 255, 1,
-+			pcm512x_get_reg_master,
-+			pcm512x_set_reg_master,
-+			digital_tlv_master),
-+
-+	SOC_DOUBLE_EXT("Master Playback Switch",
-+			PCM512x_MUTE,
-+			PCM512x_RQML_SHIFT,
-+			PCM512x_RQMR_SHIFT, 1, 1,
-+			pcm512x_get_reg_master_switch,
-+			pcm512x_set_reg_master_switch),
-+};
-+
-+static int snd_allo_piano_dac_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_card *card = rtd->card;
-+	struct glb_pool *glb_ptr;
-+
-+	glb_ptr = kmalloc(sizeof(struct glb_pool), GFP_KERNEL);
-+	if (!glb_ptr)
-+		return -ENOMEM;
-+
-+	memset(glb_ptr, 0x00, sizeof(glb_ptr));
-+	card->drvdata = glb_ptr;
-+	glb_ptr->dual_mode = 2;
-+	glb_ptr->set_mode = 0;
-+
-+	mutex_init(&glb_ptr->lock);
-+
-+	if (digital_gain_0db_limit) {
-+		int ret;
-+
-+		ret = snd_soc_limit_volume(card, "Digital Playback Volume",
-+					207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n",
-+				ret);
-+	}
-+	return 0;
-+}
-+
-+static void snd_allo_piano_gpio_mute(struct snd_soc_card *card)
-+{
-+	if (mute_gpio[0])
-+		gpiod_set_value_cansleep(mute_gpio[0], P_MUTE);
-+
-+	if (mute_gpio[1])
-+		gpiod_set_value_cansleep(mute_gpio[1], P_MUTE);
-+}
-+
-+static void snd_allo_piano_gpio_unmute(struct snd_soc_card *card)
-+{
-+	if (mute_gpio[0])
-+		gpiod_set_value_cansleep(mute_gpio[0], P_UNMUTE);
-+
-+	if (mute_gpio[1])
-+		gpiod_set_value_cansleep(mute_gpio[1], P_UNMUTE);
-+}
-+
-+static int snd_allo_piano_set_bias_level(struct snd_soc_card *card,
-+	struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)
-+{
-+	struct snd_soc_pcm_runtime *rtd;
-+	struct snd_soc_dai *codec_dai;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	codec_dai = rtd->codec_dai;
-+
-+	if (dapm->dev != codec_dai->dev)
-+		return 0;
-+
-+	switch (level) {
-+	case SND_SOC_BIAS_PREPARE:
-+		if (dapm->bias_level != SND_SOC_BIAS_STANDBY)
-+			break;
-+		/* UNMUTE DAC */
-+		snd_allo_piano_gpio_unmute(card);
-+		break;
-+
-+	case SND_SOC_BIAS_STANDBY:
-+		if (dapm->bias_level != SND_SOC_BIAS_PREPARE)
-+			break;
-+		/* MUTE DAC */
-+		snd_allo_piano_gpio_mute(card);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_allo_piano_dac_startup(
-+	struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_card *card = rtd->card;
-+
-+	snd_allo_piano_gpio_mute(card);
-+
-+	return 0;
-+}
-+
-+static int snd_allo_piano_dac_hw_params(
-+		struct snd_pcm_substream *substream,
-+		struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+	unsigned int rate = params_rate(params);
-+	struct snd_soc_card *card = rtd->card;
-+	struct glb_pool *glb_ptr = card->drvdata;
-+	int ret = 0, val = 0, dac;
-+
-+	for (dac = 0; (glb_mclk && dac < 2); dac++) {
-+		/* Configure the PLL clock reference for both the Codecs */
-+		val = snd_soc_read(rtd->codec_dais[dac]->codec,
-+					PCM512x_RATE_DET_4);
-+		if (val < 0) {
-+			dev_err(rtd->codec_dais[dac]->codec->dev,
-+				"Failed to read register PCM512x_RATE_DET_4\n");
-+			return val;
-+		}
-+
-+		if (val & 0x40) {
-+			snd_soc_write(rtd->codec_dais[dac]->codec,
-+					PCM512x_PLL_REF,
-+					PCM512x_SREF_BCK);
-+
-+			dev_info(rtd->codec_dais[dac]->codec->dev,
-+				"Setting BCLK as input clock & Enable PLL\n");
-+		} else {
-+			snd_soc_write(rtd->codec_dais[dac]->codec,
-+					PCM512x_PLL_EN,
-+					0x00);
-+
-+			snd_soc_write(rtd->codec_dais[dac]->codec,
-+					PCM512x_PLL_REF,
-+					PCM512x_SREF_SCK);
-+
-+			dev_info(rtd->codec_dais[dac]->codec->dev,
-+				"Setting SCLK as input clock & disabled PLL\n");
-+		}
-+	}
-+
-+	ret = snd_allo_piano_dsp_program(rtd, glb_ptr->set_mode, rate,
-+						glb_ptr->set_lowpass);
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+
-+	return ret;
-+}
-+
-+static int snd_allo_piano_dac_prepare(
-+	struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_card *card = rtd->card;
-+
-+	snd_allo_piano_gpio_unmute(card);
-+
-+	return 0;
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_allo_piano_dac_ops = {
-+	.startup = snd_allo_piano_dac_startup,
-+	.hw_params = snd_allo_piano_dac_hw_params,
-+	.prepare = snd_allo_piano_dac_prepare,
-+};
-+
-+static struct snd_soc_dai_link_component allo_piano_2_1_codecs[] = {
-+	{
-+		.dai_name = "pcm512x-hifi",
-+	},
-+	{
-+		.dai_name = "pcm512x-hifi",
-+	},
-+};
-+
-+static struct snd_soc_dai_link snd_allo_piano_dac_dai[] = {
-+	{
-+		.name		= "PianoDACPlus",
-+		.stream_name	= "PianoDACPlus",
-+		.cpu_dai_name	= "bcm2708-i2s.0",
-+		.platform_name	= "bcm2708-i2s.0",
-+		.codecs		= allo_piano_2_1_codecs,
-+		.num_codecs	= 2,
-+		.dai_fmt	= SND_SOC_DAIFMT_I2S |
-+				SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBS_CFS,
-+		.ops		= &snd_allo_piano_dac_ops,
-+		.init		= snd_allo_piano_dac_init,
-+	},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_allo_piano_dac = {
-+	.name = "PianoDACPlus",
-+	.owner = THIS_MODULE,
-+	.dai_link = snd_allo_piano_dac_dai,
-+	.num_links = ARRAY_SIZE(snd_allo_piano_dac_dai),
-+	.controls = allo_piano_controls,
-+	.num_controls = ARRAY_SIZE(allo_piano_controls),
-+};
-+
-+static int snd_allo_piano_dac_probe(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = &snd_allo_piano_dac;
-+	int ret = 0, i = 0;
-+
-+	card->dev = &pdev->dev;
-+	platform_set_drvdata(pdev, &snd_allo_piano_dac);
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai;
-+
-+		dai = &snd_allo_piano_dac_dai[0];
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+						"i2s-controller", 0);
-+		if (i2s_node) {
-+			for (i = 0; i < card->num_links; i++) {
-+				dai->cpu_dai_name = NULL;
-+				dai->cpu_of_node = i2s_node;
-+				dai->platform_name = NULL;
-+				dai->platform_of_node = i2s_node;
-+			}
-+		}
-+		digital_gain_0db_limit =
-+			!of_property_read_bool(pdev->dev.of_node,
-+						"allo,24db_digital_gain");
-+
-+		glb_mclk = of_property_read_bool(pdev->dev.of_node,
-+						"allo,glb_mclk");
-+
-+		allo_piano_2_1_codecs[0].of_node =
-+			of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
-+		if (!allo_piano_2_1_codecs[0].of_node) {
-+			dev_err(&pdev->dev,
-+				"Property 'audio-codec' missing or invalid\n");
-+			return -EINVAL;
-+		}
-+
-+		allo_piano_2_1_codecs[1].of_node =
-+			of_parse_phandle(pdev->dev.of_node, "audio-codec", 1);
-+		if (!allo_piano_2_1_codecs[1].of_node) {
-+			dev_err(&pdev->dev,
-+				"Property 'audio-codec' missing or invalid\n");
-+			return -EINVAL;
-+		}
-+
-+		mute_gpio[0] = devm_gpiod_get_optional(&pdev->dev, "mute1",
-+							GPIOD_OUT_LOW);
-+		if (IS_ERR(mute_gpio[0])) {
-+			ret = PTR_ERR(mute_gpio[0]);
-+			dev_err(&pdev->dev,
-+				"failed to get mute1 gpio6: %d\n", ret);
-+			return ret;
-+		}
-+
-+		mute_gpio[1] = devm_gpiod_get_optional(&pdev->dev, "mute2",
-+							GPIOD_OUT_LOW);
-+		if (IS_ERR(mute_gpio[1])) {
-+			ret = PTR_ERR(mute_gpio[1]);
-+			dev_err(&pdev->dev,
-+				"failed to get mute2 gpio25: %d\n", ret);
-+			return ret;
-+		}
-+
-+		if (mute_gpio[0] && mute_gpio[1])
-+			snd_allo_piano_dac.set_bias_level =
-+				snd_allo_piano_set_bias_level;
-+
-+		ret = snd_soc_register_card(&snd_allo_piano_dac);
-+		if (ret < 0) {
-+			dev_err(&pdev->dev,
-+				"snd_soc_register_card() failed: %d\n", ret);
-+			return ret;
-+		}
-+
-+		if ((mute_gpio[0]) && (mute_gpio[1]))
-+			snd_allo_piano_gpio_mute(&snd_allo_piano_dac);
-+
-+		return 0;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static int snd_allo_piano_dac_remove(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = platform_get_drvdata(pdev);
-+
-+	kfree(&card->drvdata);
-+	snd_allo_piano_gpio_mute(&snd_allo_piano_dac);
-+	return snd_soc_unregister_card(&snd_allo_piano_dac);
-+}
-+
-+static const struct of_device_id snd_allo_piano_dac_of_match[] = {
-+	{ .compatible = "allo,piano-dac-plus", },
-+	{ /* sentinel */ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, snd_allo_piano_dac_of_match);
-+
-+static struct platform_driver snd_allo_piano_dac_driver = {
-+	.driver = {
-+		.name = "snd-allo-piano-dac-plus",
-+		.owner = THIS_MODULE,
-+		.of_match_table = snd_allo_piano_dac_of_match,
-+	},
-+	.probe = snd_allo_piano_dac_probe,
-+	.remove = snd_allo_piano_dac_remove,
-+};
-+
-+module_platform_driver(snd_allo_piano_dac_driver);
-+
-+MODULE_AUTHOR("Baswaraj K <jaikumar@cem-solutions.net>");
-+MODULE_DESCRIPTION("ALSA ASoC Machine Driver for Allo Piano DAC Plus");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0081-Add-support-for-Allo-Boss-DAC-add-on-board-for-Raspb.patch b/target/linux/brcm2708/patches-4.14/950-0081-Add-support-for-Allo-Boss-DAC-add-on-board-for-Raspb.patch
deleted file mode 100644
index c560d92db..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0081-Add-support-for-Allo-Boss-DAC-add-on-board-for-Raspb.patch
+++ /dev/null
@@ -1,693 +0,0 @@
-From cbcb43856238e359086ac491f41d5d38b834268f Mon Sep 17 00:00:00 2001
-From: BabuSubashChandar <babuenir@gmail.com>
-Date: Tue, 28 Mar 2017 20:04:42 +0530
-Subject: [PATCH 081/454] Add support for Allo Boss DAC add-on board for
- Raspberry Pi. (#1924)
-
-Signed-off-by: Baswaraj K <jaikumar@cem-solutions.net>
-Reviewed-by: Deepak <deepak@zilogic.com>
-Reviewed-by: BabuSubashChandar <babusubashchandar@zilogic.com>
-
-Add support for new clock rate and mute gpios.
-
-Signed-off-by: Baswaraj K <jaikumar@cem-solutions.net>
-Reviewed-by: Deepak <deepak@zilogic.com>
-Reviewed-by: BabuSubashChandar <babusubashchandar@zilogic.com>
----
- drivers/clk/Makefile          |   1 +
- drivers/clk/clk-allo-dac.c    | 161 ++++++++++++
- sound/soc/bcm/Kconfig         |   7 +
- sound/soc/bcm/Makefile        |   2 +
- sound/soc/bcm/allo-boss-dac.c | 461 ++++++++++++++++++++++++++++++++++
- 5 files changed, 632 insertions(+)
- create mode 100644 drivers/clk/clk-allo-dac.c
- create mode 100644 sound/soc/bcm/allo-boss-dac.c
-
---- a/drivers/clk/Makefile
-+++ b/drivers/clk/Makefile
-@@ -18,6 +18,7 @@ endif
- 
- # hardware specific clock types
- # please keep this section sorted lexicographically by file path name
-+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC)	+= clk-allo-dac.o
- obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
- obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
- obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
---- /dev/null
-+++ b/drivers/clk/clk-allo-dac.c
-@@ -0,0 +1,161 @@
-+/*
-+ * Clock Driver for Allo DAC
-+ *
-+ * Author:	Baswaraj K <jaikumar@cem-solutions.net>
-+ *		Copyright 2016
-+ *		based on code by Stuart MacLean
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/clkdev.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/slab.h>
-+#include <linux/platform_device.h>
-+
-+/* Clock rate of CLK44EN attached to GPIO6 pin */
-+#define CLK_44EN_RATE 45158400UL
-+/* Clock rate of CLK48EN attached to GPIO3 pin */
-+#define CLK_48EN_RATE 49152000UL
-+
-+/**
-+ * struct allo_dac_clk - Common struct to the Allo DAC
-+ * @hw: clk_hw for the common clk framework
-+ * @mode: 0 => CLK44EN, 1 => CLK48EN
-+ */
-+struct clk_allo_hw {
-+	struct clk_hw hw;
-+	uint8_t mode;
-+};
-+
-+#define to_allo_clk(_hw) container_of(_hw, struct clk_allo_hw, hw)
-+
-+static const struct of_device_id clk_allo_dac_dt_ids[] = {
-+	{ .compatible = "allo,dac-clk",},
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, clk_allo_dac_dt_ids);
-+
-+static unsigned long clk_allo_dac_recalc_rate(struct clk_hw *hw,
-+	unsigned long parent_rate)
-+{
-+	return (to_allo_clk(hw)->mode == 0) ? CLK_44EN_RATE :
-+		CLK_48EN_RATE;
-+}
-+
-+static long clk_allo_dac_round_rate(struct clk_hw *hw,
-+	unsigned long rate, unsigned long *parent_rate)
-+{
-+	long actual_rate;
-+
-+	if (rate <= CLK_44EN_RATE) {
-+		actual_rate = (long)CLK_44EN_RATE;
-+	} else if (rate >= CLK_48EN_RATE) {
-+		actual_rate = (long)CLK_48EN_RATE;
-+	} else {
-+		long diff44Rate = (long)(rate - CLK_44EN_RATE);
-+		long diff48Rate = (long)(CLK_48EN_RATE - rate);
-+
-+		if (diff44Rate < diff48Rate)
-+			actual_rate = (long)CLK_44EN_RATE;
-+		else
-+			actual_rate = (long)CLK_48EN_RATE;
-+	}
-+	return actual_rate;
-+}
-+
-+
-+static int clk_allo_dac_set_rate(struct clk_hw *hw,
-+	unsigned long rate, unsigned long parent_rate)
-+{
-+	unsigned long actual_rate;
-+	struct clk_allo_hw *clk = to_allo_clk(hw);
-+
-+	actual_rate = (unsigned long)clk_allo_dac_round_rate(hw, rate,
-+		&parent_rate);
-+	clk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1;
-+	return 0;
-+}
-+
-+
-+const struct clk_ops clk_allo_dac_rate_ops = {
-+	.recalc_rate = clk_allo_dac_recalc_rate,
-+	.round_rate = clk_allo_dac_round_rate,
-+	.set_rate = clk_allo_dac_set_rate,
-+};
-+
-+static int clk_allo_dac_probe(struct platform_device *pdev)
-+{
-+	int ret;
-+	struct clk_allo_hw *proclk;
-+	struct clk *clk;
-+	struct device *dev;
-+	struct clk_init_data init;
-+
-+	dev = &pdev->dev;
-+
-+	proclk = kzalloc(sizeof(struct clk_allo_hw), GFP_KERNEL);
-+	if (!proclk)
-+		return -ENOMEM;
-+
-+	init.name = "clk-allo-dac";
-+	init.ops = &clk_allo_dac_rate_ops;
-+	init.flags = CLK_IS_BASIC;
-+	init.parent_names = NULL;
-+	init.num_parents = 0;
-+
-+	proclk->mode = 0;
-+	proclk->hw.init = &init;
-+
-+	clk = devm_clk_register(dev, &proclk->hw);
-+	if (!IS_ERR(clk)) {
-+		ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
-+			clk);
-+	} else {
-+		dev_err(dev, "Fail to register clock driver\n");
-+		kfree(proclk);
-+		ret = PTR_ERR(clk);
-+	}
-+	return ret;
-+}
-+
-+static int clk_allo_dac_remove(struct platform_device *pdev)
-+{
-+	of_clk_del_provider(pdev->dev.of_node);
-+	return 0;
-+}
-+
-+static struct platform_driver clk_allo_dac_driver = {
-+	.probe = clk_allo_dac_probe,
-+	.remove = clk_allo_dac_remove,
-+	.driver = {
-+		.name = "clk-allo-dac",
-+		.of_match_table = clk_allo_dac_dt_ids,
-+	},
-+};
-+
-+static int __init clk_allo_dac_init(void)
-+{
-+	return platform_driver_register(&clk_allo_dac_driver);
-+}
-+core_initcall(clk_allo_dac_init);
-+
-+static void __exit clk_allo_dac_exit(void)
-+{
-+	platform_driver_unregister(&clk_allo_dac_driver);
-+}
-+module_exit(clk_allo_dac_exit);
-+
-+MODULE_DESCRIPTION("Allo DAC clock driver");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:clk-allo-dac");
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -138,3 +138,10 @@ config SND_BCM2708_SOC_ALLO_PIANO_DAC_PL
- 	select SND_SOC_PCM512x_I2C
- 	help
- 	  Say Y or M if you want to add support for Allo Piano DAC Plus.
-+
-+config SND_BCM2708_SOC_ALLO_BOSS_DAC
-+	tristate "Support for Allo Boss DAC"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM512x_I2C
-+	help
-+	  Say Y or M if you want to add support for Allo Boss DAC.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -24,6 +24,7 @@ snd-soc-raspidac3-objs := raspidac3.o
- snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
- snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o
- snd-soc-dionaudio-loco-objs := dionaudio_loco.o
-+snd-soc-allo-boss-dac-objs := allo-boss-dac.o
- snd-soc-allo-piano-dac-objs := allo-piano-dac.o
- snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o
- 
-@@ -42,5 +43,6 @@ obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3)
- obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
- obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o
- obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o
-+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC) += snd-soc-allo-boss-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o
---- /dev/null
-+++ b/sound/soc/bcm/allo-boss-dac.c
-@@ -0,0 +1,461 @@
-+/*
-+ * ALSA ASoC Machine Driver for Allo Boss DAC
-+ *
-+ * Author:	Baswaraj K <jaikumar@cem-solutions.net>
-+ *		Copyright 2017
-+ *		based on code by Daniel Matuschek,
-+ *				 Stuart MacLean <stuart@hifiberry.com>
-+ *		based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include "../codecs/pcm512x.h"
-+
-+#define ALLO_BOSS_NOCLOCK 0
-+#define ALLO_BOSS_CLK44EN 1
-+#define ALLO_BOSS_CLK48EN 2
-+
-+struct pcm512x_priv {
-+	struct regmap *regmap;
-+	struct clk *sclk;
-+};
-+
-+static struct gpio_desc *mute_gpio;
-+
-+/* Clock rate of CLK44EN attached to GPIO6 pin */
-+#define CLK_44EN_RATE 45158400UL
-+/* Clock rate of CLK48EN attached to GPIO3 pin */
-+#define CLK_48EN_RATE 49152000UL
-+
-+static bool slave;
-+static bool snd_soc_allo_boss_master;
-+static bool digital_gain_0db_limit = true;
-+
-+static void snd_allo_boss_select_clk(struct snd_soc_codec *codec,
-+	int clk_id)
-+{
-+	switch (clk_id) {
-+	case ALLO_BOSS_NOCLOCK:
-+		snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x00);
-+		break;
-+	case ALLO_BOSS_CLK44EN:
-+		snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x20);
-+		break;
-+	case ALLO_BOSS_CLK48EN:
-+		snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x04);
-+		break;
-+	}
-+}
-+
-+static void snd_allo_boss_clk_gpio(struct snd_soc_codec *codec)
-+{
-+	snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x24, 0x24);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02);
-+}
-+
-+static bool snd_allo_boss_is_sclk(struct snd_soc_codec *codec)
-+{
-+	int sck;
-+
-+	sck = snd_soc_read(codec, PCM512x_RATE_DET_4);
-+	return (!(sck & 0x40));
-+}
-+
-+static bool snd_allo_boss_is_sclk_sleep(
-+	struct snd_soc_codec *codec)
-+{
-+	msleep(2);
-+	return snd_allo_boss_is_sclk(codec);
-+}
-+
-+static bool snd_allo_boss_is_master_card(struct snd_soc_codec *codec)
-+{
-+	bool isClk44EN, isClk48En, isNoClk;
-+
-+	snd_allo_boss_clk_gpio(codec);
-+
-+	snd_allo_boss_select_clk(codec, ALLO_BOSS_CLK44EN);
-+	isClk44EN = snd_allo_boss_is_sclk_sleep(codec);
-+
-+	snd_allo_boss_select_clk(codec, ALLO_BOSS_NOCLOCK);
-+	isNoClk = snd_allo_boss_is_sclk_sleep(codec);
-+
-+	snd_allo_boss_select_clk(codec, ALLO_BOSS_CLK48EN);
-+	isClk48En = snd_allo_boss_is_sclk_sleep(codec);
-+
-+	return (isClk44EN && isClk48En && !isNoClk);
-+}
-+
-+static int snd_allo_boss_clk_for_rate(int sample_rate)
-+{
-+	int type;
-+
-+	switch (sample_rate) {
-+	case 11025:
-+	case 22050:
-+	case 44100:
-+	case 88200:
-+	case 176400:
-+	case 352800:
-+		type = ALLO_BOSS_CLK44EN;
-+		break;
-+	default:
-+		type = ALLO_BOSS_CLK48EN;
-+		break;
-+	}
-+	return type;
-+}
-+
-+static void snd_allo_boss_set_sclk(struct snd_soc_codec *codec,
-+	int sample_rate)
-+{
-+	struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
-+
-+	if (!IS_ERR(pcm512x->sclk)) {
-+		int ctype;
-+
-+		ctype =	snd_allo_boss_clk_for_rate(sample_rate);
-+		clk_set_rate(pcm512x->sclk, (ctype == ALLO_BOSS_CLK44EN)
-+				? CLK_44EN_RATE : CLK_48EN_RATE);
-+		snd_allo_boss_select_clk(codec, ctype);
-+	}
-+}
-+
-+static int snd_allo_boss_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct pcm512x_priv *priv = snd_soc_codec_get_drvdata(codec);
-+
-+	if (slave)
-+		snd_soc_allo_boss_master = false;
-+	else
-+		snd_soc_allo_boss_master =
-+			snd_allo_boss_is_master_card(codec);
-+
-+	if (snd_soc_allo_boss_master) {
-+		struct snd_soc_dai_link *dai = rtd->dai_link;
-+
-+		dai->name = "BossDAC";
-+		dai->stream_name = "Boss DAC HiFi [Master]";
-+		dai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
-+			| SND_SOC_DAIFMT_CBM_CFM;
-+
-+		snd_soc_update_bits(codec, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11);
-+		snd_soc_update_bits(codec, PCM512x_MASTER_MODE, 0x03, 0x03);
-+		snd_soc_update_bits(codec, PCM512x_MASTER_CLKDIV_2, 0x7f, 63);
-+		/*
-+		* Default sclk to CLK_48EN_RATE, otherwise codec
-+		*  pcm512x_dai_startup_master method could call
-+		*  snd_pcm_hw_constraint_ratnums using CLK_44EN/64
-+		*  which will mask 384k sample rate.
-+		*/
-+		if (!IS_ERR(priv->sclk))
-+			clk_set_rate(priv->sclk, CLK_48EN_RATE);
-+	} else {
-+		priv->sclk = ERR_PTR(-ENOENT);
-+	}
-+
-+	snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02);
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);
-+
-+	if (digital_gain_0db_limit) {
-+		int ret;
-+		struct snd_soc_card *card = rtd->card;
-+
-+		ret = snd_soc_limit_volume(card, "Digital Playback Volume",
-+				207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n",
-+					ret);
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_allo_boss_update_rate_den(
-+	struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
-+	struct snd_ratnum *rats_no_pll;
-+	unsigned int num = 0, den = 0;
-+	int err;
-+
-+	rats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL);
-+	if (!rats_no_pll)
-+		return -ENOMEM;
-+
-+	rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
-+	rats_no_pll->den_min = 1;
-+	rats_no_pll->den_max = 128;
-+	rats_no_pll->den_step = 1;
-+
-+	err = snd_interval_ratnum(hw_param_interval(params,
-+		SNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den);
-+	if (err >= 0 && den) {
-+		params->rate_num = num;
-+		params->rate_den = den;
-+	}
-+
-+	devm_kfree(rtd->dev, rats_no_pll);
-+	return 0;
-+}
-+
-+static int snd_allo_boss_set_bclk_ratio_pro(
-+	struct snd_soc_dai *cpu_dai, struct snd_pcm_hw_params *params)
-+{
-+	int bratio = snd_pcm_format_physical_width(params_format(params))
-+		* params_channels(params);
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, bratio);
-+}
-+
-+static void snd_allo_boss_gpio_mute(struct snd_soc_card *card)
-+{
-+	if (mute_gpio)
-+		gpiod_set_value_cansleep(mute_gpio, 1);
-+}
-+
-+static void snd_allo_boss_gpio_unmute(struct snd_soc_card *card)
-+{
-+	if (mute_gpio)
-+		gpiod_set_value_cansleep(mute_gpio, 0);
-+}
-+
-+static int snd_allo_boss_set_bias_level(struct snd_soc_card *card,
-+	struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)
-+{
-+	struct snd_soc_pcm_runtime *rtd;
-+	struct snd_soc_dai *codec_dai;
-+
-+	rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name);
-+	codec_dai = rtd->codec_dai;
-+
-+	if (dapm->dev != codec_dai->dev)
-+		return 0;
-+
-+	switch (level) {
-+	case SND_SOC_BIAS_PREPARE:
-+		if (dapm->bias_level != SND_SOC_BIAS_STANDBY)
-+			break;
-+		/* UNMUTE DAC */
-+		snd_allo_boss_gpio_unmute(card);
-+		break;
-+
-+	case SND_SOC_BIAS_STANDBY:
-+		if (dapm->bias_level != SND_SOC_BIAS_PREPARE)
-+			break;
-+		/* MUTE DAC */
-+		snd_allo_boss_gpio_mute(card);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_allo_boss_hw_params(
-+	struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
-+{
-+	int ret = 0;
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+
-+	if (snd_soc_allo_boss_master) {
-+		struct snd_soc_codec *codec = rtd->codec;
-+
-+		snd_allo_boss_set_sclk(codec,
-+			params_rate(params));
-+
-+		ret = snd_allo_boss_set_bclk_ratio_pro(cpu_dai,
-+			params);
-+		if (!ret)
-+			ret = snd_allo_boss_update_rate_den(
-+				substream, params);
-+	} else {
-+		ret = snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+	}
-+	return ret;
-+}
-+
-+static int snd_allo_boss_startup(
-+	struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_card *card = rtd->card;
-+
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);
-+	snd_allo_boss_gpio_mute(card);
-+
-+	if (snd_soc_allo_boss_master) {
-+		struct pcm512x_priv *priv = snd_soc_codec_get_drvdata(codec);
-+		/*
-+		 * Default sclk to CLK_48EN_RATE, otherwise codec
-+		 * pcm512x_dai_startup_master method could call
-+		 * snd_pcm_hw_constraint_ratnums using CLK_44EN/64
-+		 * which will mask 384k sample rate.
-+		 */
-+		if (!IS_ERR(priv->sclk))
-+			clk_set_rate(priv->sclk, CLK_48EN_RATE);
-+	}
-+
-+	return 0;
-+}
-+
-+static void snd_allo_boss_shutdown(
-+	struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);
-+}
-+
-+static int snd_allo_boss_prepare(
-+	struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_card *card = rtd->card;
-+
-+	snd_allo_boss_gpio_unmute(card);
-+	return 0;
-+}
-+/* machine stream operations */
-+static struct snd_soc_ops snd_allo_boss_ops = {
-+	.hw_params = snd_allo_boss_hw_params,
-+	.startup = snd_allo_boss_startup,
-+	.shutdown = snd_allo_boss_shutdown,
-+	.prepare = snd_allo_boss_prepare,
-+};
-+
-+static struct snd_soc_dai_link snd_allo_boss_dai[] = {
-+{
-+	.name		= "Boss DAC",
-+	.stream_name	= "Boss DAC HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm512x-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm512x.1-004d",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S |
-+			  SND_SOC_DAIFMT_NB_NF |
-+			  SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_allo_boss_ops,
-+	.init		= snd_allo_boss_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_allo_boss = {
-+	.name         = "BossDAC",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_allo_boss_dai,
-+	.num_links    = ARRAY_SIZE(snd_allo_boss_dai),
-+};
-+
-+static int snd_allo_boss_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_allo_boss.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai;
-+
-+		dai = &snd_allo_boss_dai[0];
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					    "i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+
-+		digital_gain_0db_limit = !of_property_read_bool(
-+			pdev->dev.of_node, "allo,24db_digital_gain");
-+		slave = of_property_read_bool(pdev->dev.of_node,
-+						"allo,slave");
-+
-+		mute_gpio = devm_gpiod_get_optional(&pdev->dev, "mute",
-+							GPIOD_OUT_LOW);
-+		if (IS_ERR(mute_gpio)) {
-+			ret = PTR_ERR(mute_gpio);
-+			dev_err(&pdev->dev,
-+				"failed to get mute gpio: %d\n", ret);
-+			return ret;
-+		}
-+
-+		if (mute_gpio)
-+			snd_allo_boss.set_bias_level =
-+				snd_allo_boss_set_bias_level;
-+
-+		ret = snd_soc_register_card(&snd_allo_boss);
-+		if (ret) {
-+			dev_err(&pdev->dev,
-+				"snd_soc_register_card() failed: %d\n", ret);
-+			return ret;
-+		}
-+
-+		if (mute_gpio)
-+			snd_allo_boss_gpio_mute(&snd_allo_boss);
-+
-+		return 0;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static int snd_allo_boss_remove(struct platform_device *pdev)
-+{
-+	snd_allo_boss_gpio_mute(&snd_allo_boss);
-+	return snd_soc_unregister_card(&snd_allo_boss);
-+}
-+
-+static const struct of_device_id snd_allo_boss_of_match[] = {
-+	{ .compatible = "allo,boss-dac", },
-+	{ /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, snd_allo_boss_of_match);
-+
-+static struct platform_driver snd_allo_boss_driver = {
-+	.driver = {
-+		.name   = "snd-allo-boss-dac",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_allo_boss_of_match,
-+	},
-+	.probe          = snd_allo_boss_probe,
-+	.remove         = snd_allo_boss_remove,
-+};
-+
-+module_platform_driver(snd_allo_boss_driver);
-+
-+MODULE_AUTHOR("Baswaraj K <jaikumar@cem-solutions.net>");
-+MODULE_DESCRIPTION("ALSA ASoC Machine Driver for Allo Boss DAC");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0082-Support-for-Blokas-Labs-pisound-board.patch b/target/linux/brcm2708/patches-4.14/950-0082-Support-for-Blokas-Labs-pisound-board.patch
deleted file mode 100644
index 658f18cff..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0082-Support-for-Blokas-Labs-pisound-board.patch
+++ /dev/null
@@ -1,1192 +0,0 @@
-From 16123264d8fb86c7c9efaed230a4b0028c3be800 Mon Sep 17 00:00:00 2001
-From: gtrainavicius <gtrainavicius@users.noreply.github.com>
-Date: Sun, 23 Oct 2016 12:06:53 +0300
-Subject: [PATCH 082/454] Support for Blokas Labs pisound board
-
-Pisound dynamic overlay (#1760)
-
-Restructuring pisound-overlay.dts, so it can be loaded and unloaded dynamically using dtoverlay.
-
-Print a logline when the kernel module is removed.
-
-pisound improvements:
-
-* Added a writable sysfs object to enable scripts / user space software
-to blink MIDI activity LEDs for variable duration.
-* Improved hw_param constraints setting.
-* Added compatibility with S16_LE sample format.
-* Exposed some simple placeholder volume controls, so the card appears
-in volumealsa widget.
-
-Signed-off-by: Giedrius Trainavicius <giedrius@blokas.io>
----
- .../devicetree/bindings/vendor-prefixes.txt   |    1 +
- sound/soc/bcm/Kconfig                         |    6 +
- sound/soc/bcm/Makefile                        |    2 +
- sound/soc/bcm/pisound.c                       | 1123 +++++++++++++++++
- 4 files changed, 1132 insertions(+)
- create mode 100644 sound/soc/bcm/pisound.c
-
---- a/Documentation/devicetree/bindings/vendor-prefixes.txt
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
-@@ -49,6 +49,7 @@ axentia	Axentia Technologies AB
- axis	Axis Communications AB
- bananapi BIPAI KEJI LIMITED
- bhf	Beckhoff Automation GmbH & Co. KG
-+blokaslabs	Vilniaus Blokas UAB
- boe	BOE Technology Group Co., Ltd.
- bosch	Bosch Sensortec GmbH
- boundary	Boundary Devices Inc.
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -145,3 +145,9 @@ config SND_BCM2708_SOC_ALLO_BOSS_DAC
- 	select SND_SOC_PCM512x_I2C
- 	help
- 	  Say Y or M if you want to add support for Allo Boss DAC.
-+
-+config SND_PISOUND
-+	tristate "Support for Blokas Labs pisound"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	help
-+	  Say Y or M if you want to add support for Blokas Labs pisound.
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -27,6 +27,7 @@ snd-soc-dionaudio-loco-objs := dionaudio
- snd-soc-allo-boss-dac-objs := allo-boss-dac.o
- snd-soc-allo-piano-dac-objs := allo-piano-dac.o
- snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o
-+snd-soc-pisound-objs := pisound.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-@@ -46,3 +47,4 @@ obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_L
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC) += snd-soc-allo-boss-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o
-+obj-$(CONFIG_SND_PISOUND) += snd-soc-pisound.o
---- /dev/null
-+++ b/sound/soc/bcm/pisound.c
-@@ -0,0 +1,1123 @@
-+/*
-+ * pisound Linux kernel module.
-+ * Copyright (C) 2016  Vilniaus Blokas UAB, http://blokas.io/pisound
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; version 2 of the
-+ * License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-+ * MA  02110-1301, USA.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/gpio.h>
-+#include <linux/kobject.h>
-+#include <linux/sysfs.h>
-+#include <linux/delay.h>
-+#include <linux/spi/spi.h>
-+#include <linux/interrupt.h>
-+#include <linux/kfifo.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+#include <sound/rawmidi.h>
-+#include <sound/asequencer.h>
-+#include <sound/control.h>
-+
-+static int pisnd_spi_init(struct device *dev);
-+static void pisnd_spi_uninit(void);
-+
-+static void pisnd_spi_send(uint8_t val);
-+static uint8_t pisnd_spi_recv(uint8_t *buffer, uint8_t length);
-+
-+typedef void (*pisnd_spi_recv_cb)(void *data);
-+static void pisnd_spi_set_callback(pisnd_spi_recv_cb cb, void *data);
-+
-+static const char *pisnd_spi_get_serial(void);
-+static const char *pisnd_spi_get_id(void);
-+static const char *pisnd_spi_get_version(void);
-+
-+static int pisnd_midi_init(struct snd_card *card);
-+static void pisnd_midi_uninit(void);
-+
-+#define PISOUND_LOG_PREFIX "pisound: "
-+
-+#ifdef DEBUG
-+#	define printd(...) pr_alert(PISOUND_LOG_PREFIX __VA_ARGS__)
-+#else
-+#	define printd(...) do {} while (0)
-+#endif
-+
-+#define printe(...) pr_err(PISOUND_LOG_PREFIX __VA_ARGS__)
-+#define printi(...) pr_info(PISOUND_LOG_PREFIX __VA_ARGS__)
-+
-+static int pisnd_output_open(struct snd_rawmidi_substream *substream)
-+{
-+	return 0;
-+}
-+
-+static int pisnd_output_close(struct snd_rawmidi_substream *substream)
-+{
-+	return 0;
-+}
-+
-+static void pisnd_output_trigger(
-+	struct snd_rawmidi_substream *substream,
-+	int up
-+	)
-+{
-+	uint8_t data;
-+
-+	if (!up)
-+		return;
-+
-+	while (snd_rawmidi_transmit_peek(substream, &data, 1)) {
-+		pisnd_spi_send(data);
-+		snd_rawmidi_transmit_ack(substream, 1);
-+	}
-+}
-+
-+static void pisnd_output_drain(struct snd_rawmidi_substream *substream)
-+{
-+	uint8_t data;
-+
-+	while (snd_rawmidi_transmit_peek(substream, &data, 1)) {
-+		pisnd_spi_send(data);
-+
-+		snd_rawmidi_transmit_ack(substream, 1);
-+	}
-+}
-+
-+static int pisnd_input_open(struct snd_rawmidi_substream *substream)
-+{
-+	return 0;
-+}
-+
-+static int pisnd_input_close(struct snd_rawmidi_substream *substream)
-+{
-+	return 0;
-+}
-+
-+static void pisnd_midi_recv_callback(void *substream)
-+{
-+	uint8_t data[128];
-+	uint8_t n = 0;
-+
-+	while ((n = pisnd_spi_recv(data, sizeof(data)))) {
-+		int res = snd_rawmidi_receive(substream, data, n);
-+		(void)res;
-+		printd("midi recv 0x%02x, res = %d\n", data, res);
-+	}
-+}
-+
-+static void pisnd_input_trigger(struct snd_rawmidi_substream *substream, int up)
-+{
-+	if (up) {
-+		pisnd_spi_set_callback(pisnd_midi_recv_callback, substream);
-+		pisnd_midi_recv_callback(substream);
-+	} else {
-+		pisnd_spi_set_callback(NULL, NULL);
-+	}
-+}
-+
-+static struct snd_rawmidi *g_rmidi;
-+
-+static struct snd_rawmidi_ops pisnd_output_ops = {
-+	.open = pisnd_output_open,
-+	.close = pisnd_output_close,
-+	.trigger = pisnd_output_trigger,
-+	.drain = pisnd_output_drain,
-+};
-+
-+static struct snd_rawmidi_ops pisnd_input_ops = {
-+	.open = pisnd_input_open,
-+	.close = pisnd_input_close,
-+	.trigger = pisnd_input_trigger,
-+};
-+
-+static void pisnd_get_port_info(
-+	struct snd_rawmidi *rmidi,
-+	int number,
-+	struct snd_seq_port_info *seq_port_info
-+	)
-+{
-+	seq_port_info->type =
-+		SNDRV_SEQ_PORT_TYPE_MIDI_GENERIC |
-+		SNDRV_SEQ_PORT_TYPE_HARDWARE |
-+		SNDRV_SEQ_PORT_TYPE_PORT;
-+	seq_port_info->midi_voices = 0;
-+}
-+
-+static struct snd_rawmidi_global_ops pisnd_global_ops = {
-+	.get_port_info = pisnd_get_port_info,
-+};
-+
-+static int pisnd_midi_init(struct snd_card *card)
-+{
-+	int err = snd_rawmidi_new(card, "pisound MIDI", 0, 1, 1, &g_rmidi);
-+
-+	if (err < 0) {
-+		printe("snd_rawmidi_new failed: %d\n", err);
-+		return err;
-+	}
-+
-+	strcpy(g_rmidi->name, "pisound MIDI ");
-+	strcat(g_rmidi->name, pisnd_spi_get_serial());
-+
-+	g_rmidi->info_flags =
-+		SNDRV_RAWMIDI_INFO_OUTPUT |
-+		SNDRV_RAWMIDI_INFO_INPUT |
-+		SNDRV_RAWMIDI_INFO_DUPLEX;
-+
-+	g_rmidi->ops = &pisnd_global_ops;
-+
-+	g_rmidi->private_data = (void *)0;
-+
-+	snd_rawmidi_set_ops(
-+		g_rmidi,
-+		SNDRV_RAWMIDI_STREAM_OUTPUT,
-+		&pisnd_output_ops
-+		);
-+
-+	snd_rawmidi_set_ops(
-+		g_rmidi,
-+		SNDRV_RAWMIDI_STREAM_INPUT,
-+		&pisnd_input_ops
-+		);
-+
-+	return 0;
-+}
-+
-+static void pisnd_midi_uninit(void)
-+{
-+}
-+
-+static void *g_recvData;
-+static pisnd_spi_recv_cb g_recvCallback;
-+
-+#define FIFO_SIZE 512
-+
-+static char g_serial_num[11];
-+static char g_id[25];
-+static char g_version[5];
-+
-+static uint8_t g_ledFlashDuration;
-+static bool    g_ledFlashDurationChanged;
-+
-+DEFINE_KFIFO(spi_fifo_in,  uint8_t, FIFO_SIZE);
-+DEFINE_KFIFO(spi_fifo_out, uint8_t, FIFO_SIZE);
-+
-+static struct gpio_desc *data_available;
-+static struct gpio_desc *spi_reset;
-+
-+static struct spi_device *pisnd_spi_device;
-+
-+static struct workqueue_struct *pisnd_workqueue;
-+static struct work_struct pisnd_work_process;
-+
-+static void pisnd_work_handler(struct work_struct *work);
-+
-+static uint16_t spi_transfer16(uint16_t val);
-+
-+static int pisnd_init_workqueues(void)
-+{
-+	pisnd_workqueue = create_singlethread_workqueue("pisnd_workqueue");
-+	INIT_WORK(&pisnd_work_process, pisnd_work_handler);
-+
-+	return 0;
-+}
-+
-+static void pisnd_uninit_workqueues(void)
-+{
-+	flush_workqueue(pisnd_workqueue);
-+	destroy_workqueue(pisnd_workqueue);
-+
-+	pisnd_workqueue = NULL;
-+}
-+
-+static bool pisnd_spi_has_more(void)
-+{
-+	return gpiod_get_value(data_available);
-+}
-+
-+enum task_e {
-+	TASK_PROCESS = 0,
-+};
-+
-+static void pisnd_schedule_process(enum task_e task)
-+{
-+	if (pisnd_spi_device != NULL &&
-+		pisnd_workqueue != NULL &&
-+		!work_pending(&pisnd_work_process)
-+		) {
-+		printd("schedule: has more = %d\n", pisnd_spi_has_more());
-+		if (task == TASK_PROCESS)
-+			queue_work(pisnd_workqueue, &pisnd_work_process);
-+	}
-+}
-+
-+static irqreturn_t data_available_interrupt_handler(int irq, void *dev_id)
-+{
-+	if (irq == gpiod_to_irq(data_available) && pisnd_spi_has_more()) {
-+		printd("schedule from irq\n");
-+		pisnd_schedule_process(TASK_PROCESS);
-+	}
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static DEFINE_SPINLOCK(spilock);
-+static unsigned long spilockflags;
-+
-+static uint16_t spi_transfer16(uint16_t val)
-+{
-+	int err;
-+	struct spi_transfer transfer;
-+	struct spi_message msg;
-+	uint8_t txbuf[2];
-+	uint8_t rxbuf[2];
-+
-+	if (!pisnd_spi_device) {
-+		printe("pisnd_spi_device null, returning\n");
-+		return 0;
-+	}
-+
-+	spi_message_init(&msg);
-+
-+	memset(&transfer, 0, sizeof(transfer));
-+	memset(&rxbuf, 0, sizeof(rxbuf));
-+
-+	txbuf[0] = val >> 8;
-+	txbuf[1] = val & 0xff;
-+
-+	transfer.tx_buf = &txbuf;
-+	transfer.rx_buf = &rxbuf;
-+	transfer.len = sizeof(txbuf);
-+	transfer.speed_hz = 125000;
-+	transfer.delay_usecs = 100;
-+	spi_message_add_tail(&transfer, &msg);
-+
-+	spin_lock_irqsave(&spilock, spilockflags);
-+	err = spi_sync(pisnd_spi_device, &msg);
-+	spin_unlock_irqrestore(&spilock, spilockflags);
-+
-+	if (err < 0) {
-+		printe("spi_sync error %d\n", err);
-+		return 0;
-+	}
-+
-+	printd("received: %02x%02x\n", rxbuf[0], rxbuf[1]);
-+	printd("hasMore %d\n", pisnd_spi_has_more());
-+
-+	return (rxbuf[0] << 8) | rxbuf[1];
-+}
-+
-+static int spi_read_bytes(char *dst, size_t length, uint8_t *bytesRead)
-+{
-+	uint16_t rx;
-+	uint8_t size;
-+	uint8_t i;
-+
-+	memset(dst, 0, length);
-+	*bytesRead = 0;
-+
-+	 rx = spi_transfer16(0);
-+	if (!(rx >> 8))
-+		return -EINVAL;
-+
-+	size = rx & 0xff;
-+
-+	if (size > length)
-+		return -EINVAL;
-+
-+	for (i = 0; i < size; ++i) {
-+		rx = spi_transfer16(0);
-+		if (!(rx >> 8))
-+			return -EINVAL;
-+
-+		dst[i] = rx & 0xff;
-+	}
-+
-+	*bytesRead = i;
-+
-+	return 0;
-+}
-+
-+static int spi_device_match(struct device *dev, void *data)
-+{
-+	struct spi_device *spi = container_of(dev, struct spi_device, dev);
-+
-+	printd("      %s %s %dkHz %d bits mode=0x%02X\n",
-+		spi->modalias, dev_name(dev), spi->max_speed_hz/1000,
-+		spi->bits_per_word, spi->mode);
-+
-+	if (strcmp("pisound-spi", spi->modalias) == 0) {
-+		printi("\tFound!\n");
-+		return 1;
-+	}
-+
-+	printe("\tNot found!\n");
-+	return 0;
-+}
-+
-+static struct spi_device *pisnd_spi_find_device(void)
-+{
-+	struct device *dev;
-+
-+	printi("Searching for spi device...\n");
-+	dev = bus_find_device(&spi_bus_type, NULL, NULL, spi_device_match);
-+	if (dev != NULL)
-+		return container_of(dev, struct spi_device, dev);
-+	else
-+		return NULL;
-+}
-+
-+static void pisnd_work_handler(struct work_struct *work)
-+{
-+	uint16_t rx;
-+	uint16_t tx;
-+	uint8_t val;
-+
-+	if (work == &pisnd_work_process) {
-+		if (pisnd_spi_device == NULL)
-+			return;
-+
-+		do {
-+			val = 0;
-+			tx = 0;
-+
-+			if (g_ledFlashDurationChanged) {
-+				tx = 0xf000 | g_ledFlashDuration;
-+				g_ledFlashDuration = 0;
-+				g_ledFlashDurationChanged = false;
-+			} else if (kfifo_get(&spi_fifo_out, &val)) {
-+				tx = 0x0f00 | val;
-+			}
-+
-+			rx = spi_transfer16(tx);
-+
-+			if (rx & 0xff00) {
-+				kfifo_put(&spi_fifo_in, rx & 0xff);
-+				if (kfifo_len(&spi_fifo_in) > 16
-+					&& g_recvCallback)
-+					g_recvCallback(g_recvData);
-+			}
-+		} while (rx != 0
-+			|| !kfifo_is_empty(&spi_fifo_out)
-+			|| pisnd_spi_has_more()
-+			|| g_ledFlashDurationChanged
-+			);
-+
-+		if (!kfifo_is_empty(&spi_fifo_in) && g_recvCallback)
-+			g_recvCallback(g_recvData);
-+	}
-+}
-+
-+static int pisnd_spi_gpio_init(struct device *dev)
-+{
-+	spi_reset = gpiod_get_index(dev, "reset", 1, GPIOD_ASIS);
-+	data_available = gpiod_get_index(dev, "data_available", 0, GPIOD_ASIS);
-+
-+	gpiod_direction_output(spi_reset, 1);
-+	gpiod_direction_input(data_available);
-+
-+	/* Reset the slave. */
-+	gpiod_set_value(spi_reset, false);
-+	mdelay(1);
-+	gpiod_set_value(spi_reset, true);
-+
-+	/* Give time for spi slave to start. */
-+	mdelay(64);
-+
-+	return 0;
-+}
-+
-+static void pisnd_spi_gpio_uninit(void)
-+{
-+	gpiod_set_value(spi_reset, false);
-+	gpiod_put(spi_reset);
-+	spi_reset = NULL;
-+
-+	gpiod_put(data_available);
-+	data_available = NULL;
-+}
-+
-+static int pisnd_spi_gpio_irq_init(struct device *dev)
-+{
-+	return request_irq(
-+		gpiod_to_irq(data_available),
-+		data_available_interrupt_handler,
-+		IRQF_TIMER | IRQF_TRIGGER_RISING,
-+		"data_available_int",
-+		NULL
-+		);
-+}
-+
-+static void pisnd_spi_gpio_irq_uninit(void)
-+{
-+	free_irq(gpiod_to_irq(data_available), NULL);
-+}
-+
-+static int spi_read_info(void)
-+{
-+	uint16_t tmp;
-+	uint8_t count;
-+	uint8_t n;
-+	uint8_t i;
-+	uint8_t j;
-+	char buffer[257];
-+	int ret;
-+	char *p;
-+
-+	memset(g_serial_num, 0, sizeof(g_serial_num));
-+	memset(g_version, 0, sizeof(g_version));
-+	memset(g_id, 0, sizeof(g_id));
-+
-+	tmp = spi_transfer16(0);
-+
-+	if (!(tmp >> 8))
-+		return -EINVAL;
-+
-+	 count = tmp & 0xff;
-+
-+	for (i = 0; i < count; ++i) {
-+		memset(buffer, 0, sizeof(buffer));
-+		ret = spi_read_bytes(buffer, sizeof(buffer)-1, &n);
-+
-+		if (ret < 0)
-+			return ret;
-+
-+		switch (i) {
-+		case 0:
-+			if (n != 2)
-+				return -EINVAL;
-+
-+			snprintf(
-+				g_version,
-+				sizeof(g_version),
-+				"%x.%02x",
-+				buffer[0],
-+				buffer[1]
-+				);
-+			break;
-+		case 1:
-+			if (n >= sizeof(g_serial_num))
-+				return -EINVAL;
-+
-+			memcpy(g_serial_num, buffer, sizeof(g_serial_num));
-+			break;
-+		case 2:
-+			{
-+				if (n >= sizeof(g_id))
-+					return -EINVAL;
-+
-+				p = g_id;
-+				for (j = 0; j < n; ++j)
-+					p += sprintf(p, "%02x", buffer[j]);
-+			}
-+			break;
-+		default:
-+			break;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int pisnd_spi_init(struct device *dev)
-+{
-+	int ret;
-+	struct spi_device *spi;
-+
-+	memset(g_serial_num, 0, sizeof(g_serial_num));
-+	memset(g_id, 0, sizeof(g_id));
-+	memset(g_version, 0, sizeof(g_version));
-+
-+	spi = pisnd_spi_find_device();
-+
-+	if (spi != NULL) {
-+		printd("initializing spi!\n");
-+		pisnd_spi_device = spi;
-+		ret = spi_setup(pisnd_spi_device);
-+	} else {
-+		printe("SPI device not found, deferring!\n");
-+		return -EPROBE_DEFER;
-+	}
-+
-+	ret = pisnd_spi_gpio_init(dev);
-+
-+	if (ret < 0) {
-+		printe("SPI GPIO init failed: %d\n", ret);
-+		spi_dev_put(pisnd_spi_device);
-+		pisnd_spi_device = NULL;
-+		pisnd_spi_gpio_uninit();
-+		return ret;
-+	}
-+
-+	ret = spi_read_info();
-+
-+	if (ret < 0) {
-+		printe("Reading card info failed: %d\n", ret);
-+		spi_dev_put(pisnd_spi_device);
-+		pisnd_spi_device = NULL;
-+		pisnd_spi_gpio_uninit();
-+		return ret;
-+	}
-+
-+	/* Flash the LEDs. */
-+	spi_transfer16(0xf008);
-+
-+	ret = pisnd_spi_gpio_irq_init(dev);
-+	if (ret < 0) {
-+		printe("SPI irq request failed: %d\n", ret);
-+		spi_dev_put(pisnd_spi_device);
-+		pisnd_spi_device = NULL;
-+		pisnd_spi_gpio_irq_uninit();
-+		pisnd_spi_gpio_uninit();
-+	}
-+
-+	ret = pisnd_init_workqueues();
-+	if (ret != 0) {
-+		printe("Workqueue initialization failed: %d\n", ret);
-+		spi_dev_put(pisnd_spi_device);
-+		pisnd_spi_device = NULL;
-+		pisnd_spi_gpio_irq_uninit();
-+		pisnd_spi_gpio_uninit();
-+		pisnd_uninit_workqueues();
-+		return ret;
-+	}
-+
-+	if (pisnd_spi_has_more()) {
-+		printd("data is available, scheduling from init\n");
-+		pisnd_schedule_process(TASK_PROCESS);
-+	}
-+
-+	return 0;
-+}
-+
-+static void pisnd_spi_uninit(void)
-+{
-+	pisnd_uninit_workqueues();
-+
-+	spi_dev_put(pisnd_spi_device);
-+	pisnd_spi_device = NULL;
-+
-+	pisnd_spi_gpio_irq_uninit();
-+	pisnd_spi_gpio_uninit();
-+}
-+
-+static void pisnd_spi_flash_leds(uint8_t duration)
-+{
-+	g_ledFlashDuration = duration;
-+	g_ledFlashDurationChanged = true;
-+	printd("schedule from spi_flash_leds\n");
-+	pisnd_schedule_process(TASK_PROCESS);
-+}
-+
-+static void pisnd_spi_send(uint8_t val)
-+{
-+	kfifo_put(&spi_fifo_out, val);
-+	printd("schedule from spi_send\n");
-+	pisnd_schedule_process(TASK_PROCESS);
-+}
-+
-+static uint8_t pisnd_spi_recv(uint8_t *buffer, uint8_t length)
-+{
-+	return kfifo_out(&spi_fifo_in, buffer, length);
-+}
-+
-+static void pisnd_spi_set_callback(pisnd_spi_recv_cb cb, void *data)
-+{
-+	g_recvData = data;
-+	g_recvCallback = cb;
-+}
-+
-+static const char *pisnd_spi_get_serial(void)
-+{
-+	if (strlen(g_serial_num))
-+		return g_serial_num;
-+
-+	return "";
-+}
-+
-+static const char *pisnd_spi_get_id(void)
-+{
-+	if (strlen(g_id))
-+		return g_id;
-+
-+	return "";
-+}
-+
-+static const char *pisnd_spi_get_version(void)
-+{
-+	if (strlen(g_version))
-+		return g_version;
-+
-+	return "";
-+}
-+
-+static const struct of_device_id pisound_of_match[] = {
-+	{ .compatible = "blokaslabs,pisound", },
-+	{ .compatible = "blokaslabs,pisound-spi", },
-+	{},
-+};
-+
-+enum {
-+	SWITCH = 0,
-+	VOLUME = 1,
-+};
-+
-+static int pisnd_ctl_info(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_info *uinfo)
-+{
-+	if (kcontrol->private_value == SWITCH) {
-+		uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
-+		uinfo->count = 1;
-+		uinfo->value.integer.min = 0;
-+		uinfo->value.integer.max = 1;
-+		return 0;
-+	} else if (kcontrol->private_value == VOLUME) {
-+		uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+		uinfo->count = 1;
-+		uinfo->value.integer.min = 0;
-+		uinfo->value.integer.max = 100;
-+		return 0;
-+	}
-+	return -EINVAL;
-+}
-+
-+static int pisnd_ctl_get(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	if (kcontrol->private_value == SWITCH) {
-+		ucontrol->value.integer.value[0] = 1;
-+		return 0;
-+	} else if (kcontrol->private_value == VOLUME) {
-+		ucontrol->value.integer.value[0] = 100;
-+		return 0;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static struct snd_kcontrol_new pisnd_ctl[] = {
-+	{
-+		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+		.name = "PCM Playback Switch",
-+		.index = 0,
-+		.private_value = SWITCH,
-+		.access = SNDRV_CTL_ELEM_ACCESS_READ,
-+		.info = pisnd_ctl_info,
-+		.get = pisnd_ctl_get,
-+	},
-+	{
-+		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
-+		.name = "PCM Playback Volume",
-+		.index = 0,
-+		.private_value = VOLUME,
-+		.access = SNDRV_CTL_ELEM_ACCESS_READ,
-+		.info = pisnd_ctl_info,
-+		.get = pisnd_ctl_get,
-+	},
-+};
-+
-+static int pisnd_ctl_init(struct snd_card *card)
-+{
-+	int err, i;
-+
-+	for (i = 0; i < ARRAY_SIZE(pisnd_ctl); ++i) {
-+		err = snd_ctl_add(card, snd_ctl_new1(&pisnd_ctl[i], NULL));
-+		if (err < 0)
-+			return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static int pisnd_ctl_uninit(void)
-+{
-+	return 0;
-+}
-+
-+static struct gpio_desc *osr0, *osr1, *osr2;
-+static struct gpio_desc *reset;
-+static struct gpio_desc *button;
-+
-+static int pisnd_hw_params(
-+	struct snd_pcm_substream *substream,
-+	struct snd_pcm_hw_params *params
-+	)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	/* pisound runs on fixed 32 clock counts per channel,
-+	 * as generated by the master ADC.
-+	 */
-+	snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2);
-+
-+	printd("rate   = %d\n", params_rate(params));
-+	printd("ch     = %d\n", params_channels(params));
-+	printd("bits   = %u\n",
-+		snd_pcm_format_physical_width(params_format(params)));
-+	printd("format = %d\n", params_format(params));
-+
-+	gpiod_set_value(reset, false);
-+
-+	switch (params_rate(params)) {
-+	case 48000:
-+		gpiod_set_value(osr0, true);
-+		gpiod_set_value(osr1, false);
-+		gpiod_set_value(osr2, false);
-+		break;
-+	case 96000:
-+		gpiod_set_value(osr0, true);
-+		gpiod_set_value(osr1, true);
-+		gpiod_set_value(osr2, false);
-+		break;
-+	case 192000:
-+		gpiod_set_value(osr0, true);
-+		gpiod_set_value(osr1, true);
-+		gpiod_set_value(osr2, true);
-+		break;
-+	default:
-+		printe("Unsupported rate %u!\n", params_rate(params));
-+		return -EINVAL;
-+	}
-+
-+	gpiod_set_value(reset, true);
-+
-+	return 0;
-+}
-+
-+static unsigned int rates[3] = {
-+	48000, 96000, 192000
-+};
-+
-+static struct snd_pcm_hw_constraint_list constraints_rates = {
-+	.count = ARRAY_SIZE(rates),
-+	.list = rates,
-+	.mask = 0,
-+};
-+
-+static int pisnd_startup(struct snd_pcm_substream *substream)
-+{
-+	int err = snd_pcm_hw_constraint_list(
-+		substream->runtime,
-+		0,
-+		SNDRV_PCM_HW_PARAM_RATE,
-+		&constraints_rates
-+		);
-+
-+	if (err < 0)
-+		return err;
-+
-+	err = snd_pcm_hw_constraint_single(
-+		substream->runtime,
-+		SNDRV_PCM_HW_PARAM_CHANNELS,
-+		2
-+		);
-+
-+	if (err < 0)
-+		return err;
-+
-+	err = snd_pcm_hw_constraint_mask64(
-+		substream->runtime,
-+		SNDRV_PCM_HW_PARAM_FORMAT,
-+		SNDRV_PCM_FMTBIT_S16_LE |
-+		SNDRV_PCM_FMTBIT_S24_LE |
-+		SNDRV_PCM_FMTBIT_S32_LE
-+		);
-+
-+	if (err < 0)
-+		return err;
-+
-+	return 0;
-+}
-+
-+static struct snd_soc_ops pisnd_ops = {
-+	.startup = pisnd_startup,
-+	.hw_params = pisnd_hw_params,
-+};
-+
-+static struct snd_soc_dai_link pisnd_dai[] = {
-+	{
-+		.name           = "pisound",
-+		.stream_name    = "pisound",
-+		.cpu_dai_name   = "bcm2708-i2s.0",
-+		.codec_dai_name = "snd-soc-dummy-dai",
-+		.platform_name  = "bcm2708-i2s.0",
-+		.codec_name     = "snd-soc-dummy",
-+		.dai_fmt        =
-+			SND_SOC_DAIFMT_I2S |
-+			SND_SOC_DAIFMT_NB_NF |
-+			SND_SOC_DAIFMT_CBM_CFM,
-+		.ops            = &pisnd_ops,
-+	},
-+};
-+
-+static int pisnd_card_probe(struct snd_soc_card *card)
-+{
-+	int err = pisnd_midi_init(card->snd_card);
-+
-+	if (err < 0) {
-+		printe("pisnd_midi_init failed: %d\n", err);
-+		return err;
-+	}
-+
-+	err = pisnd_ctl_init(card->snd_card);
-+	if (err < 0) {
-+		printe("pisnd_ctl_init failed: %d\n", err);
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static int pisnd_card_remove(struct snd_soc_card *card)
-+{
-+	pisnd_ctl_uninit();
-+	pisnd_midi_uninit();
-+	return 0;
-+}
-+
-+static struct snd_soc_card pisnd_card = {
-+	.name         = "pisound",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = pisnd_dai,
-+	.num_links    = ARRAY_SIZE(pisnd_dai),
-+	.probe        = pisnd_card_probe,
-+	.remove       = pisnd_card_remove,
-+};
-+
-+static int pisnd_init_gpio(struct device *dev)
-+{
-+	osr0 = gpiod_get_index(dev, "osr", 0, GPIOD_ASIS);
-+	osr1 = gpiod_get_index(dev, "osr", 1, GPIOD_ASIS);
-+	osr2 = gpiod_get_index(dev, "osr", 2, GPIOD_ASIS);
-+
-+	reset = gpiod_get_index(dev, "reset", 0, GPIOD_ASIS);
-+
-+	button = gpiod_get_index(dev, "button", 0, GPIOD_ASIS);
-+
-+	gpiod_direction_output(osr0,  1);
-+	gpiod_direction_output(osr1,  1);
-+	gpiod_direction_output(osr2,  1);
-+	gpiod_direction_output(reset, 1);
-+
-+	gpiod_set_value(reset, false);
-+	gpiod_set_value(osr0,   true);
-+	gpiod_set_value(osr1,  false);
-+	gpiod_set_value(osr2,  false);
-+	gpiod_set_value(reset,  true);
-+
-+	gpiod_export(button, false);
-+
-+	return 0;
-+}
-+
-+static int pisnd_uninit_gpio(void)
-+{
-+	int i;
-+
-+	struct gpio_desc **gpios[] = {
-+		&osr0, &osr1, &osr2, &reset, &button,
-+	};
-+
-+	gpiod_unexport(button);
-+
-+	for (i = 0; i < ARRAY_SIZE(gpios); ++i) {
-+		if (*gpios[i] == NULL) {
-+			printd("weird, GPIO[%d] is NULL already\n", i);
-+			continue;
-+		}
-+
-+		gpiod_put(*gpios[i]);
-+		*gpios[i] = NULL;
-+	}
-+
-+	return 0;
-+}
-+
-+static struct kobject *pisnd_kobj;
-+
-+static ssize_t pisnd_serial_show(
-+	struct kobject *kobj,
-+	struct kobj_attribute *attr,
-+	char *buf
-+	)
-+{
-+	return sprintf(buf, "%s\n", pisnd_spi_get_serial());
-+}
-+
-+static ssize_t pisnd_id_show(
-+	struct kobject *kobj,
-+	struct kobj_attribute *attr,
-+	char *buf
-+	)
-+{
-+	return sprintf(buf, "%s\n", pisnd_spi_get_id());
-+}
-+
-+static ssize_t pisnd_version_show(
-+	struct kobject *kobj,
-+	struct kobj_attribute *attr,
-+	char *buf
-+	)
-+{
-+	return sprintf(buf, "%s\n", pisnd_spi_get_version());
-+}
-+
-+static ssize_t pisnd_led_store(
-+	struct kobject *kobj,
-+	struct kobj_attribute *attr,
-+	const char *buf,
-+	size_t length
-+	)
-+{
-+	uint32_t timeout;
-+	int err;
-+
-+	err = kstrtou32(buf, 10, &timeout);
-+
-+	if (err == 0 && timeout <= 255)
-+		pisnd_spi_flash_leds(timeout);
-+
-+	return length;
-+}
-+
-+static struct kobj_attribute pisnd_serial_attribute =
-+	__ATTR(serial, 0444, pisnd_serial_show, NULL);
-+static struct kobj_attribute pisnd_id_attribute =
-+	__ATTR(id, 0444, pisnd_id_show, NULL);
-+static struct kobj_attribute pisnd_version_attribute =
-+	__ATTR(version, 0444, pisnd_version_show, NULL);
-+static struct kobj_attribute pisnd_led_attribute =
-+	__ATTR(led, 0644, NULL, pisnd_led_store);
-+
-+static struct attribute *attrs[] = {
-+	&pisnd_serial_attribute.attr,
-+	&pisnd_id_attribute.attr,
-+	&pisnd_version_attribute.attr,
-+	&pisnd_led_attribute.attr,
-+	NULL
-+};
-+
-+static struct attribute_group attr_group = { .attrs = attrs };
-+
-+static int pisnd_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+	int i;
-+
-+	ret = pisnd_spi_init(&pdev->dev);
-+	if (ret < 0) {
-+		printe("pisnd_spi_init failed: %d\n", ret);
-+		return ret;
-+	}
-+
-+	printi("Detected pisound card:\n");
-+	printi("\tSerial:  %s\n", pisnd_spi_get_serial());
-+	printi("\tVersion: %s\n", pisnd_spi_get_version());
-+	printi("\tId:      %s\n", pisnd_spi_get_id());
-+
-+	pisnd_kobj = kobject_create_and_add("pisound", kernel_kobj);
-+	if (!pisnd_kobj) {
-+		pisnd_spi_uninit();
-+		return -ENOMEM;
-+	}
-+
-+	ret = sysfs_create_group(pisnd_kobj, &attr_group);
-+	if (ret < 0) {
-+		pisnd_spi_uninit();
-+		kobject_put(pisnd_kobj);
-+		return -ENOMEM;
-+	}
-+
-+	pisnd_init_gpio(&pdev->dev);
-+	pisnd_card.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+
-+		i2s_node = of_parse_phandle(
-+			pdev->dev.of_node,
-+			"i2s-controller",
-+			0
-+			);
-+
-+		for (i = 0; i < pisnd_card.num_links; ++i) {
-+			struct snd_soc_dai_link *dai = &pisnd_dai[i];
-+
-+			if (i2s_node) {
-+				dai->cpu_dai_name = NULL;
-+				dai->cpu_of_node = i2s_node;
-+				dai->platform_name = NULL;
-+				dai->platform_of_node = i2s_node;
-+				dai->stream_name = pisnd_spi_get_serial();
-+			}
-+		}
-+	}
-+
-+	ret = snd_soc_register_card(&pisnd_card);
-+
-+	if (ret < 0) {
-+		if (ret != -EPROBE_DEFER)
-+			printe("snd_soc_register_card() failed: %d\n", ret);
-+		pisnd_uninit_gpio();
-+		kobject_put(pisnd_kobj);
-+		pisnd_spi_uninit();
-+	}
-+
-+	return ret;
-+}
-+
-+static int pisnd_remove(struct platform_device *pdev)
-+{
-+	printi("Unloading.\n");
-+
-+	if (pisnd_kobj) {
-+		kobject_put(pisnd_kobj);
-+		pisnd_kobj = NULL;
-+	}
-+
-+	pisnd_spi_uninit();
-+
-+	/* Turn off */
-+	gpiod_set_value(reset, false);
-+	pisnd_uninit_gpio();
-+
-+	return snd_soc_unregister_card(&pisnd_card);
-+}
-+
-+MODULE_DEVICE_TABLE(of, pisound_of_match);
-+
-+static struct platform_driver pisnd_driver = {
-+	.driver = {
-+		.name           = "snd-rpi-pisound",
-+		.owner          = THIS_MODULE,
-+		.of_match_table = pisound_of_match,
-+	},
-+	.probe              = pisnd_probe,
-+	.remove             = pisnd_remove,
-+};
-+
-+module_platform_driver(pisnd_driver);
-+
-+MODULE_AUTHOR("Giedrius Trainavicius <giedrius@blokas.io>");
-+MODULE_DESCRIPTION("ASoC Driver for pisound, http://blokas.io/pisound");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0083-ASoC-Add-driver-for-Cirrus-Logic-Audio-Card.patch b/target/linux/brcm2708/patches-4.14/950-0083-ASoC-Add-driver-for-Cirrus-Logic-Audio-Card.patch
deleted file mode 100644
index 118c43d6c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0083-ASoC-Add-driver-for-Cirrus-Logic-Audio-Card.patch
+++ /dev/null
@@ -1,1060 +0,0 @@
-From 7c7641a4796fa9740ed038f96484f1088587b22d Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Sun, 22 Jan 2017 12:49:37 +0100
-Subject: [PATCH 083/454] ASoC: Add driver for Cirrus Logic Audio Card
-
-Note: due to problems with deferred probing of regulators
-the following softdep should be added to a modprobe.d file
-
-softdep arizona-spi pre: arizona-ldo1
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/Kconfig      |    9 +
- sound/soc/bcm/Makefile     |    2 +
- sound/soc/bcm/rpi-cirrus.c | 1003 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 1014 insertions(+)
- create mode 100644 sound/soc/bcm/rpi-cirrus.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -46,6 +46,15 @@ config SND_BCM2708_SOC_HIFIBERRY_AMP
-         help
-          Say Y or M if you want to add support for the HifiBerry Amp amplifier board.
- 
-+config SND_BCM2708_SOC_RPI_CIRRUS
-+        tristate "Support for Cirrus Logic Audio Card"
-+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+        select SND_SOC_WM5102
-+        select SND_SOC_WM8804
-+        help
-+         Say Y or M if you want to add support for the Wolfson and
-+         Cirrus Logic audio cards.
-+
- config SND_BCM2708_SOC_RPI_DAC
-         tristate "Support for RPi-DAC"
-         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -16,6 +16,7 @@ snd-soc-hifiberry-dacplus-objs := hifibe
- snd-soc-hifiberry-digi-objs := hifiberry_digi.o
- snd-soc-justboom-dac-objs := justboom-dac.o
- snd-soc-justboom-digi-objs := justboom-digi.o
-+snd-soc-rpi-cirrus-objs := rpi-cirrus.o
- snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-rpi-proto-objs := rpi-proto.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
-@@ -36,6 +37,7 @@ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_D
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC) += snd-soc-justboom-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI) += snd-soc-justboom-digi.o
-+obj-$(CONFIG_SND_BCM2708_SOC_RPI_CIRRUS) += snd-soc-rpi-cirrus.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
---- /dev/null
-+++ b/sound/soc/bcm/rpi-cirrus.c
-@@ -0,0 +1,1003 @@
-+/*
-+ * ASoC machine driver for Cirrus Logic Audio Card
-+ * (with WM5102 and WM8804 codecs)
-+ *
-+ * Copyright 2015-2017 Matthias Reichl <hias@horus.com>
-+ *
-+ * Based on rpi-cirrus-sound-pi driver (c) Wolfson / Cirrus Logic Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/slab.h>
-+#include <linux/list.h>
-+#include <linux/delay.h>
-+#include <sound/pcm_params.h>
-+
-+#include <linux/mfd/arizona/registers.h>
-+
-+#include "../codecs/wm5102.h"
-+#include "../codecs/wm8804.h"
-+
-+#define WM8804_CLKOUT_HZ 12000000
-+
-+#define RPI_CIRRUS_DEFAULT_RATE 44100
-+#define WM5102_MAX_SYSCLK_1 49152000 /* max sysclk for 4K family */
-+#define WM5102_MAX_SYSCLK_2 45158400 /* max sysclk for 11.025K family */
-+
-+static inline unsigned int calc_sysclk(unsigned int rate)
-+{
-+	return (rate % 4000) ? WM5102_MAX_SYSCLK_2 : WM5102_MAX_SYSCLK_1;
-+}
-+
-+enum {
-+	DAI_WM5102 = 0,
-+	DAI_WM8804,
-+};
-+
-+struct rpi_cirrus_priv {
-+	/* mutex for synchronzing FLL1 access with DAPM */
-+	struct mutex lock;
-+	unsigned int card_rate;
-+	int sync_path_enable;
-+	int fll1_freq; /* negative means RefClock in spdif rx case */
-+
-+	/* track hw params/free for substreams */
-+	unsigned int params_set;
-+	unsigned int min_rate_idx, max_rate_idx;
-+	unsigned char iec958_status[4];
-+};
-+
-+/* helper functions */
-+static inline struct snd_soc_pcm_runtime *get_wm5102_runtime(
-+	struct snd_soc_card *card) {
-+	return snd_soc_get_pcm_runtime(card, card->dai_link[DAI_WM5102].name);
-+}
-+
-+static inline struct snd_soc_pcm_runtime *get_wm8804_runtime(
-+	struct snd_soc_card *card) {
-+	return snd_soc_get_pcm_runtime(card, card->dai_link[DAI_WM8804].name);
-+}
-+
-+
-+struct rate_info {
-+	unsigned int value;
-+	char *text;
-+};
-+
-+static struct rate_info min_rates[] = {
-+	{     0, "off"},
-+	{ 32000, "32kHz"},
-+	{ 44100, "44.1kHz"}
-+};
-+
-+#define NUM_MIN_RATES ARRAY_SIZE(min_rates)
-+
-+static int rpi_cirrus_min_rate_info(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_info *uinfo)
-+{
-+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
-+	uinfo->count = 1;
-+	uinfo->value.enumerated.items = NUM_MIN_RATES;
-+
-+	if (uinfo->value.enumerated.item >= NUM_MIN_RATES)
-+		uinfo->value.enumerated.item = NUM_MIN_RATES - 1;
-+	strcpy(uinfo->value.enumerated.name,
-+		min_rates[uinfo->value.enumerated.item].text);
-+	return 0;
-+}
-+
-+static int rpi_cirrus_min_rate_get(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+
-+	ucontrol->value.enumerated.item[0] = priv->min_rate_idx;
-+	return 0;
-+}
-+
-+static int rpi_cirrus_min_rate_put(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	int changed = 0;
-+
-+	if (priv->min_rate_idx != ucontrol->value.enumerated.item[0]) {
-+		changed = 1;
-+		priv->min_rate_idx = ucontrol->value.enumerated.item[0];
-+	}
-+
-+	return changed;
-+}
-+
-+static struct rate_info max_rates[] = {
-+	{     0, "off"},
-+	{ 48000, "48kHz"},
-+	{ 96000, "96kHz"}
-+};
-+
-+#define NUM_MAX_RATES ARRAY_SIZE(max_rates)
-+
-+static int rpi_cirrus_max_rate_info(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_info *uinfo)
-+{
-+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
-+	uinfo->count = 1;
-+	uinfo->value.enumerated.items = NUM_MAX_RATES;
-+	if (uinfo->value.enumerated.item >= NUM_MAX_RATES)
-+		uinfo->value.enumerated.item = NUM_MAX_RATES - 1;
-+	strcpy(uinfo->value.enumerated.name,
-+		max_rates[uinfo->value.enumerated.item].text);
-+	return 0;
-+}
-+
-+static int rpi_cirrus_max_rate_get(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+
-+	ucontrol->value.enumerated.item[0] = priv->max_rate_idx;
-+	return 0;
-+}
-+
-+static int rpi_cirrus_max_rate_put(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	int changed = 0;
-+
-+	if (priv->max_rate_idx != ucontrol->value.enumerated.item[0]) {
-+		changed = 1;
-+		priv->max_rate_idx = ucontrol->value.enumerated.item[0];
-+	}
-+
-+	return changed;
-+}
-+
-+static int rpi_cirrus_spdif_info(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_info *uinfo)
-+{
-+	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
-+	uinfo->count = 1;
-+	return 0;
-+}
-+
-+static int rpi_cirrus_spdif_playback_get(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	int i;
-+
-+	for (i = 0; i < 4; i++)
-+		ucontrol->value.iec958.status[i] = priv->iec958_status[i];
-+
-+	return 0;
-+}
-+
-+static int rpi_cirrus_spdif_playback_put(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_codec *wm8804_codec = get_wm8804_runtime(card)->codec;
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	unsigned char *stat = priv->iec958_status;
-+	unsigned char *ctrl_stat = ucontrol->value.iec958.status;
-+	unsigned int mask;
-+	int i, changed = 0;
-+
-+	for (i = 0; i < 4; i++) {
-+		mask = (i == 3) ? 0x3f : 0xff;
-+		if ((ctrl_stat[i] & mask) != (stat[i] & mask)) {
-+			changed = 1;
-+			stat[i] = ctrl_stat[i] & mask;
-+			snd_soc_update_bits(wm8804_codec,
-+				WM8804_SPDTX1 + i, mask, stat[i]);
-+		}
-+	}
-+
-+	return changed;
-+}
-+
-+static int rpi_cirrus_spdif_mask_get(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	ucontrol->value.iec958.status[0] = 0xff;
-+	ucontrol->value.iec958.status[1] = 0xff;
-+	ucontrol->value.iec958.status[2] = 0xff;
-+	ucontrol->value.iec958.status[3] = 0x3f;
-+
-+	return 0;
-+}
-+
-+static int rpi_cirrus_spdif_capture_get(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_codec *wm8804_codec = get_wm8804_runtime(card)->codec;
-+	unsigned int mask;
-+	int i;
-+
-+	for (i = 0; i < 4; i++) {
-+		mask = (i == 3) ? 0x3f : 0xff;
-+		ucontrol->value.iec958.status[i] =
-+			snd_soc_read(wm8804_codec, WM8804_RXCHAN1 + i) & mask;
-+	}
-+
-+	return 0;
-+}
-+
-+#define SPDIF_FLAG_CTRL(desc, reg, bit, invert) \
-+{ \
-+		.access =  SNDRV_CTL_ELEM_ACCESS_READ \
-+			   | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
-+		.iface =   SNDRV_CTL_ELEM_IFACE_MIXER, \
-+		.name =    SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) \
-+				desc " Flag", \
-+		.info =    snd_ctl_boolean_mono_info, \
-+		.get =     rpi_cirrus_spdif_status_flag_get, \
-+		.private_value = \
-+			(bit) | ((reg) << 8) | ((invert) << 16) \
-+}
-+
-+static int rpi_cirrus_spdif_status_flag_get(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_codec *wm8804_codec = get_wm8804_runtime(card)->codec;
-+
-+	unsigned int bit = kcontrol->private_value & 0xff;
-+	unsigned int reg = (kcontrol->private_value >> 8) & 0xff;
-+	unsigned int invert = (kcontrol->private_value >> 16) & 0xff;
-+
-+	bool flag = snd_soc_read(wm8804_codec, reg) & (1 << bit);
-+
-+	ucontrol->value.integer.value[0] = invert ? !flag : flag;
-+
-+	return 0;
-+}
-+
-+static const char * const recovered_frequency_texts[] = {
-+	"176.4/192 kHz",
-+	"88.2/96 kHz",
-+	"44.1/48 kHz",
-+	"32 kHz"
-+};
-+
-+#define NUM_RECOVERED_FREQUENCIES \
-+	ARRAY_SIZE(recovered_frequency_texts)
-+
-+static int rpi_cirrus_recovered_frequency_info(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_info *uinfo)
-+{
-+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
-+	uinfo->count = 1;
-+	uinfo->value.enumerated.items = NUM_RECOVERED_FREQUENCIES;
-+	if (uinfo->value.enumerated.item >= NUM_RECOVERED_FREQUENCIES)
-+		uinfo->value.enumerated.item = NUM_RECOVERED_FREQUENCIES - 1;
-+	strcpy(uinfo->value.enumerated.name,
-+		recovered_frequency_texts[uinfo->value.enumerated.item]);
-+	return 0;
-+}
-+
-+static int rpi_cirrus_recovered_frequency_get(struct snd_kcontrol *kcontrol,
-+	struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct snd_soc_codec *wm8804_codec = get_wm8804_runtime(card)->codec;
-+
-+	ucontrol->value.enumerated.item[0] =
-+		(snd_soc_read(wm8804_codec, WM8804_SPDSTAT) >> 4) & 0x03;
-+	return 0;
-+}
-+
-+static const struct snd_kcontrol_new rpi_cirrus_controls[] = {
-+	{
-+		.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,
-+		.name =    "Min Sample Rate",
-+		.info =    rpi_cirrus_min_rate_info,
-+		.get =     rpi_cirrus_min_rate_get,
-+		.put =     rpi_cirrus_min_rate_put,
-+	},
-+	{
-+		.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,
-+		.name =    "Max Sample Rate",
-+		.info =    rpi_cirrus_max_rate_info,
-+		.get =     rpi_cirrus_max_rate_get,
-+		.put =     rpi_cirrus_max_rate_put,
-+	},
-+	{
-+		.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,
-+		.name =    SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
-+		.info =    rpi_cirrus_spdif_info,
-+		.get =     rpi_cirrus_spdif_playback_get,
-+		.put =     rpi_cirrus_spdif_playback_put,
-+	},
-+	{
-+		.access =  SNDRV_CTL_ELEM_ACCESS_READ
-+			   | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
-+		.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,
-+		.name =    SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
-+		.info =    rpi_cirrus_spdif_info,
-+		.get =     rpi_cirrus_spdif_capture_get,
-+	},
-+	{
-+		.access =  SNDRV_CTL_ELEM_ACCESS_READ,
-+		.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,
-+		.name =    SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
-+		.info =    rpi_cirrus_spdif_info,
-+		.get =     rpi_cirrus_spdif_mask_get,
-+	},
-+	{
-+		.access =  SNDRV_CTL_ELEM_ACCESS_READ
-+			   | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
-+		.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,
-+		.name =    SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE)
-+				"Recovered Frequency",
-+		.info =    rpi_cirrus_recovered_frequency_info,
-+		.get =     rpi_cirrus_recovered_frequency_get,
-+	},
-+	SPDIF_FLAG_CTRL("Audio", WM8804_SPDSTAT, 0, 1),
-+	SPDIF_FLAG_CTRL("Non-PCM", WM8804_SPDSTAT, 1, 0),
-+	SPDIF_FLAG_CTRL("Copyright", WM8804_SPDSTAT, 2, 1),
-+	SPDIF_FLAG_CTRL("De-Emphasis", WM8804_SPDSTAT, 3, 0),
-+	SPDIF_FLAG_CTRL("Lock", WM8804_SPDSTAT, 6, 1),
-+	SPDIF_FLAG_CTRL("Invalid", WM8804_INTSTAT, 1, 0),
-+	SPDIF_FLAG_CTRL("TransErr", WM8804_INTSTAT, 3, 0),
-+};
-+
-+static const char * const linein_micbias_texts[] = {
-+	"off", "on",
-+};
-+
-+static SOC_ENUM_SINGLE_VIRT_DECL(linein_micbias_enum,
-+	linein_micbias_texts);
-+
-+static const struct snd_kcontrol_new linein_micbias_mux =
-+	SOC_DAPM_ENUM("Route", linein_micbias_enum);
-+
-+static int rpi_cirrus_spdif_rx_enable_event(struct snd_soc_dapm_widget *w,
-+	struct snd_kcontrol *kcontrol, int event);
-+
-+const struct snd_soc_dapm_widget rpi_cirrus_dapm_widgets[] = {
-+	SND_SOC_DAPM_MIC("DMIC", NULL),
-+	SND_SOC_DAPM_MIC("Headset Mic", NULL),
-+	SND_SOC_DAPM_INPUT("Line Input"),
-+	SND_SOC_DAPM_MIC("Line Input with Micbias", NULL),
-+	SND_SOC_DAPM_MUX("Line Input Micbias", SND_SOC_NOPM, 0, 0,
-+		&linein_micbias_mux),
-+	SND_SOC_DAPM_INPUT("dummy SPDIF in"),
-+	SND_SOC_DAPM_PGA_E("dummy SPDIFRX", SND_SOC_NOPM, 0, 0, NULL, 0,
-+		rpi_cirrus_spdif_rx_enable_event,
-+		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
-+	SND_SOC_DAPM_INPUT("Dummy Input"),
-+	SND_SOC_DAPM_OUTPUT("Dummy Output"),
-+};
-+
-+const struct snd_soc_dapm_route rpi_cirrus_dapm_routes[] = {
-+	{ "IN1L", NULL, "Headset Mic" },
-+	{ "IN1R", NULL, "Headset Mic" },
-+	{ "Headset Mic", NULL, "MICBIAS1" },
-+
-+	{ "IN2L", NULL, "DMIC" },
-+	{ "IN2R", NULL, "DMIC" },
-+	{ "DMIC", NULL, "MICBIAS2" },
-+
-+	{ "IN3L", NULL, "Line Input Micbias" },
-+	{ "IN3R", NULL, "Line Input Micbias" },
-+
-+	{ "Line Input Micbias", "off", "Line Input" },
-+	{ "Line Input Micbias", "on", "Line Input with Micbias" },
-+
-+	/* Make sure MICVDD is enabled, otherwise we get noise */
-+	{ "Line Input", NULL, "MICVDD" },
-+	{ "Line Input with Micbias", NULL, "MICBIAS3" },
-+
-+	/* Dummy routes to check whether SPDIF RX is enabled or not */
-+	{"dummy SPDIFRX", NULL, "dummy SPDIF in"},
-+	{"AIFTX", NULL, "dummy SPDIFRX"},
-+
-+	/*
-+	 * Dummy routes to keep wm5102 from staying off on
-+	 * playback/capture if all mixers are off.
-+	 */
-+	{ "Dummy Output", NULL, "AIF1RX1" },
-+	{ "Dummy Output", NULL, "AIF1RX2" },
-+	{ "AIF1TX1", NULL, "Dummy Input" },
-+	{ "AIF1TX2", NULL, "Dummy Input" },
-+};
-+
-+static int rpi_cirrus_clear_flls(struct snd_soc_card *card,
-+	struct snd_soc_codec *wm5102_codec) {
-+
-+	int ret1, ret2;
-+
-+	ret1 = snd_soc_codec_set_pll(wm5102_codec,
-+		WM5102_FLL1, ARIZONA_FLL_SRC_NONE, 0, 0);
-+	ret2 = snd_soc_codec_set_pll(wm5102_codec,
-+		WM5102_FLL1_REFCLK, ARIZONA_FLL_SRC_NONE, 0, 0);
-+
-+	if (ret1) {
-+		dev_warn(card->dev,
-+			"setting FLL1 to zero failed: %d\n", ret1);
-+		return ret1;
-+	}
-+	if (ret2) {
-+		dev_warn(card->dev,
-+			"setting FLL1_REFCLK to zero failed: %d\n", ret2);
-+		return ret2;
-+	}
-+	return 0;
-+}
-+
-+static int rpi_cirrus_set_fll(struct snd_soc_card *card,
-+	struct snd_soc_codec *wm5102_codec, unsigned int clk_freq)
-+{
-+	int ret = snd_soc_codec_set_pll(wm5102_codec,
-+		WM5102_FLL1,
-+		ARIZONA_CLK_SRC_MCLK1,
-+		WM8804_CLKOUT_HZ,
-+		clk_freq);
-+	if (ret)
-+		dev_err(card->dev, "Failed to set FLL1 to %d: %d\n",
-+			clk_freq, ret);
-+
-+	usleep_range(1000, 2000);
-+	return ret;
-+}
-+
-+static int rpi_cirrus_set_fll_refclk(struct snd_soc_card *card,
-+	struct snd_soc_codec *wm5102_codec,
-+	unsigned int clk_freq, unsigned int aif2_freq)
-+{
-+	int ret = snd_soc_codec_set_pll(wm5102_codec,
-+		WM5102_FLL1_REFCLK,
-+		ARIZONA_CLK_SRC_MCLK1,
-+		WM8804_CLKOUT_HZ,
-+		clk_freq);
-+	if (ret) {
-+		dev_err(card->dev,
-+			"Failed to set FLL1_REFCLK to %d: %d\n",
-+			clk_freq, ret);
-+		return ret;
-+	}
-+
-+	ret = snd_soc_codec_set_pll(wm5102_codec,
-+		WM5102_FLL1,
-+		ARIZONA_CLK_SRC_AIF2BCLK,
-+		aif2_freq, clk_freq);
-+	if (ret)
-+		dev_err(card->dev,
-+			"Failed to set FLL1 with Sync Clock %d to %d: %d\n",
-+			aif2_freq, clk_freq, ret);
-+
-+	usleep_range(1000, 2000);
-+	return ret;
-+}
-+
-+static int rpi_cirrus_spdif_rx_enable_event(struct snd_soc_dapm_widget *w,
-+	struct snd_kcontrol *kcontrol, int event)
-+{
-+	struct snd_soc_card *card = w->dapm->card;
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	struct snd_soc_codec *wm5102_codec = get_wm5102_runtime(card)->codec;
-+
-+	unsigned int clk_freq, aif2_freq;
-+	int ret = 0;
-+
-+	switch (event) {
-+	case SND_SOC_DAPM_POST_PMU:
-+		mutex_lock(&priv->lock);
-+
-+		/* Enable sync path in case of SPDIF capture use case */
-+
-+		clk_freq = calc_sysclk(priv->card_rate);
-+		aif2_freq = 64 * priv->card_rate;
-+
-+		dev_dbg(card->dev,
-+			"spdif_rx: changing FLL1 to use Ref Clock clk: %d spdif: %d\n",
-+			clk_freq, aif2_freq);
-+
-+		ret = rpi_cirrus_clear_flls(card, wm5102_codec);
-+		if (ret) {
-+			dev_err(card->dev, "spdif_rx: failed to clear FLLs\n");
-+			goto out;
-+		}
-+
-+		ret = rpi_cirrus_set_fll_refclk(card, wm5102_codec,
-+			clk_freq, aif2_freq);
-+
-+		if (ret) {
-+			dev_err(card->dev, "spdif_rx: failed to set FLLs\n");
-+			goto out;
-+		}
-+
-+		/* set to negative to indicate we're doing spdif rx */
-+		priv->fll1_freq = -clk_freq;
-+		priv->sync_path_enable = 1;
-+		break;
-+
-+	case SND_SOC_DAPM_POST_PMD:
-+		mutex_lock(&priv->lock);
-+		priv->sync_path_enable = 0;
-+		break;
-+
-+	default:
-+		return 0;
-+	}
-+
-+out:
-+	mutex_unlock(&priv->lock);
-+	return ret;
-+}
-+
-+static int rpi_cirrus_set_bias_level(struct snd_soc_card *card,
-+	struct snd_soc_dapm_context *dapm,
-+	enum snd_soc_bias_level level)
-+{
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	struct snd_soc_pcm_runtime *wm5102_runtime = get_wm5102_runtime(card);
-+	struct snd_soc_codec *wm5102_codec = wm5102_runtime->codec;
-+
-+	int ret = 0;
-+	unsigned int clk_freq;
-+
-+	if (dapm->dev != wm5102_runtime->codec_dai->dev)
-+		return 0;
-+
-+	switch (level) {
-+	case SND_SOC_BIAS_PREPARE:
-+		if (dapm->bias_level == SND_SOC_BIAS_ON)
-+			break;
-+
-+		mutex_lock(&priv->lock);
-+
-+		if (!priv->sync_path_enable) {
-+			clk_freq = calc_sysclk(priv->card_rate);
-+
-+			dev_dbg(card->dev,
-+				"set_bias: changing FLL1 from %d to %d\n",
-+				priv->fll1_freq, clk_freq);
-+
-+			ret = rpi_cirrus_set_fll(card, wm5102_codec, clk_freq);
-+			if (ret)
-+				dev_err(card->dev,
-+					"set_bias: Failed to set FLL1\n");
-+			else
-+				priv->fll1_freq = clk_freq;
-+		}
-+		mutex_unlock(&priv->lock);
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static int rpi_cirrus_set_bias_level_post(struct snd_soc_card *card,
-+	struct snd_soc_dapm_context *dapm,
-+	enum snd_soc_bias_level level)
-+{
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	struct snd_soc_pcm_runtime *wm5102_runtime = get_wm5102_runtime(card);
-+	struct snd_soc_codec *wm5102_codec = wm5102_runtime->codec;
-+
-+	if (dapm->dev != wm5102_runtime->codec_dai->dev)
-+		return 0;
-+
-+	switch (level) {
-+	case SND_SOC_BIAS_STANDBY:
-+		mutex_lock(&priv->lock);
-+
-+		dev_dbg(card->dev,
-+			"set_bias_post: changing FLL1 from %d to off\n",
-+				priv->fll1_freq);
-+
-+		if (rpi_cirrus_clear_flls(card, wm5102_codec))
-+			dev_err(card->dev,
-+				"set_bias_post: failed to clear FLLs\n");
-+		else
-+			priv->fll1_freq = 0;
-+
-+		mutex_unlock(&priv->lock);
-+
-+		break;
-+	default:
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+static int rpi_cirrus_set_wm8804_pll(struct snd_soc_card *card,
-+	struct snd_soc_dai *wm8804_dai, unsigned int rate)
-+{
-+	int ret;
-+
-+	/* use 256fs */
-+	unsigned int clk_freq = rate * 256;
-+
-+	ret = snd_soc_dai_set_pll(wm8804_dai, 0, 0,
-+		WM8804_CLKOUT_HZ, clk_freq);
-+	if (ret) {
-+		dev_err(card->dev,
-+			"Failed to set WM8804 PLL to %d: %d\n", clk_freq, ret);
-+		return ret;
-+	}
-+
-+	/* Set MCLK as PLL Output */
-+	ret = snd_soc_dai_set_sysclk(wm8804_dai,
-+		WM8804_TX_CLKSRC_PLL, clk_freq, 0);
-+	if (ret) {
-+		dev_err(card->dev,
-+			"Failed to set MCLK as PLL Output: %d\n", ret);
-+		return ret;
-+	}
-+
-+	return ret;
-+}
-+
-+static int rpi_cirrus_startup(struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_card *card = rtd->card;
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	unsigned int min_rate = min_rates[priv->min_rate_idx].value;
-+	unsigned int max_rate = max_rates[priv->max_rate_idx].value;
-+
-+	if (min_rate || max_rate) {
-+		if (max_rate == 0)
-+			max_rate = UINT_MAX;
-+
-+		dev_dbg(card->dev,
-+			"startup: limiting rate to %u-%u\n",
-+			min_rate, max_rate);
-+
-+		snd_pcm_hw_constraint_minmax(substream->runtime,
-+			SNDRV_PCM_HW_PARAM_RATE, min_rate, max_rate);
-+	}
-+
-+	return 0;
-+}
-+
-+static struct snd_soc_pcm_stream rpi_cirrus_dai_link2_params = {
-+	.formats = SNDRV_PCM_FMTBIT_S24_LE,
-+	.channels_min = 2,
-+	.channels_max = 2,
-+	.rate_min = RPI_CIRRUS_DEFAULT_RATE,
-+	.rate_max = RPI_CIRRUS_DEFAULT_RATE,
-+};
-+
-+static int rpi_cirrus_hw_params(struct snd_pcm_substream *substream,
-+	struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_card *card = rtd->card;
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	struct snd_soc_dai *bcm_i2s_dai = rtd->cpu_dai;
-+	struct snd_soc_codec *wm5102_codec = rtd->codec;
-+	struct snd_soc_dai *wm8804_dai = get_wm8804_runtime(card)->codec_dai;
-+
-+	int ret;
-+
-+	unsigned int width = snd_pcm_format_physical_width(
-+		params_format(params));
-+	unsigned int rate = params_rate(params);
-+	unsigned int clk_freq = calc_sysclk(rate);
-+
-+	mutex_lock(&priv->lock);
-+
-+	dev_dbg(card->dev, "hw_params: setting rate to %d\n", rate);
-+
-+	ret = snd_soc_dai_set_bclk_ratio(bcm_i2s_dai, 2 * width);
-+	if (ret) {
-+		dev_err(card->dev, "set_bclk_ratio failed: %d\n", ret);
-+		goto out;
-+	}
-+
-+	ret = snd_soc_dai_set_tdm_slot(rtd->codec_dai, 0x03, 0x03, 2, width);
-+	if (ret) {
-+		dev_err(card->dev, "set_tdm_slot failed: %d\n", ret);
-+		goto out;
-+	}
-+
-+	/* WM8804 supports sample rates from 32k only */
-+	if (rate >= 32000) {
-+		ret = rpi_cirrus_set_wm8804_pll(card, wm8804_dai, rate);
-+		if (ret)
-+			goto out;
-+	}
-+
-+	ret = snd_soc_codec_set_sysclk(wm5102_codec,
-+		ARIZONA_CLK_SYSCLK,
-+		ARIZONA_CLK_SRC_FLL1,
-+		clk_freq,
-+		SND_SOC_CLOCK_IN);
-+	if (ret) {
-+		dev_err(card->dev, "Failed to set SYSCLK: %d\n", ret);
-+		goto out;
-+	}
-+
-+	if ((priv->fll1_freq > 0) && (priv->fll1_freq != clk_freq)) {
-+		dev_dbg(card->dev,
-+			"hw_params: changing FLL1 from %d to %d\n",
-+			priv->fll1_freq, clk_freq);
-+
-+		if (rpi_cirrus_clear_flls(card, wm5102_codec)) {
-+			dev_err(card->dev, "hw_params: failed to clear FLLs\n");
-+			goto out;
-+		}
-+
-+		if (rpi_cirrus_set_fll(card, wm5102_codec, clk_freq)) {
-+			dev_err(card->dev, "hw_params: failed to set FLL\n");
-+			goto out;
-+		}
-+
-+		priv->fll1_freq = clk_freq;
-+	}
-+
-+	priv->card_rate = rate;
-+	rpi_cirrus_dai_link2_params.rate_min = rate;
-+	rpi_cirrus_dai_link2_params.rate_max = rate;
-+
-+	priv->params_set |= 1 << substream->stream;
-+
-+out:
-+	mutex_unlock(&priv->lock);
-+
-+	return ret;
-+}
-+
-+static int rpi_cirrus_hw_free(struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_card *card = rtd->card;
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	struct snd_soc_codec *wm5102_codec = rtd->codec;
-+	int ret;
-+	unsigned int old_params_set = priv->params_set;
-+
-+	priv->params_set &= ~(1 << substream->stream);
-+
-+	/* disable sysclk if this was the last open stream */
-+	if (priv->params_set == 0 && old_params_set) {
-+		dev_dbg(card->dev,
-+			"hw_free: Setting SYSCLK to Zero\n");
-+
-+		ret = snd_soc_codec_set_sysclk(wm5102_codec,
-+			ARIZONA_CLK_SYSCLK,
-+			ARIZONA_CLK_SRC_FLL1,
-+			0,
-+			SND_SOC_CLOCK_IN);
-+		if (ret)
-+			dev_err(card->dev,
-+				"hw_free: Failed to set SYSCLK to Zero: %d\n",
-+				ret);
-+	}
-+	return 0;
-+}
-+
-+static int rpi_cirrus_init_wm5102(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+	int ret;
-+
-+	/* no 32kHz input, derive it from sysclk if needed  */
-+	snd_soc_update_bits(codec,
-+			ARIZONA_CLOCK_32K_1, ARIZONA_CLK_32K_SRC_MASK, 2);
-+
-+	if (rpi_cirrus_clear_flls(rtd->card, codec))
-+		dev_warn(rtd->card->dev,
-+			"init_wm5102: failed to clear FLLs\n");
-+
-+	ret = snd_soc_codec_set_sysclk(codec,
-+		ARIZONA_CLK_SYSCLK, ARIZONA_CLK_SRC_FLL1,
-+		0, SND_SOC_CLOCK_IN);
-+	if (ret) {
-+		dev_err(rtd->card->dev,
-+			"Failed to set SYSCLK to Zero: %d\n", ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int rpi_cirrus_init_wm8804(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+	struct snd_soc_card *card = rtd->card;
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	unsigned int mask;
-+	int i, ret;
-+
-+	for (i = 0; i < 4; i++) {
-+		mask = (i == 3) ? 0x3f : 0xff;
-+		priv->iec958_status[i] =
-+			snd_soc_read(codec, WM8804_SPDTX1 + i) & mask;
-+	}
-+
-+	/* Setup for 256fs */
-+	ret = snd_soc_dai_set_clkdiv(codec_dai,
-+		WM8804_MCLK_DIV, WM8804_MCLKDIV_256FS);
-+	if (ret) {
-+		dev_err(card->dev,
-+			"init_wm8804: Failed to set MCLK_DIV to 256fs: %d\n",
-+			ret);
-+		return ret;
-+	}
-+
-+	/* Output OSC on CLKOUT */
-+	ret = snd_soc_dai_set_sysclk(codec_dai,
-+		WM8804_CLKOUT_SRC_OSCCLK, WM8804_CLKOUT_HZ, 0);
-+	if (ret)
-+		dev_err(card->dev,
-+			"init_wm8804: Failed to set CLKOUT as OSC Frequency: %d\n",
-+			ret);
-+
-+	/* Init PLL with default samplerate */
-+	ret = rpi_cirrus_set_wm8804_pll(card, codec_dai,
-+		RPI_CIRRUS_DEFAULT_RATE);
-+	if (ret)
-+		dev_err(card->dev,
-+			"init_wm8804: Failed to setup PLL for %dHz: %d\n",
-+			RPI_CIRRUS_DEFAULT_RATE, ret);
-+
-+	return ret;
-+}
-+
-+static struct snd_soc_ops rpi_cirrus_ops = {
-+	.startup = rpi_cirrus_startup,
-+	.hw_params = rpi_cirrus_hw_params,
-+	.hw_free = rpi_cirrus_hw_free,
-+};
-+
-+static struct snd_soc_dai_link rpi_cirrus_dai[] = {
-+	[DAI_WM5102] = {
-+		.name		= "WM5102",
-+		.stream_name	= "WM5102 AiFi",
-+		.codec_dai_name	= "wm5102-aif1",
-+		.codec_name	= "wm5102-codec",
-+		.dai_fmt	=   SND_SOC_DAIFMT_I2S
-+				  | SND_SOC_DAIFMT_NB_NF
-+				  | SND_SOC_DAIFMT_CBM_CFM,
-+		.ops		= &rpi_cirrus_ops,
-+		.init		= rpi_cirrus_init_wm5102,
-+	},
-+	[DAI_WM8804] = {
-+		.name		= "WM5102 SPDIF",
-+		.stream_name	= "SPDIF Tx/Rx",
-+		.cpu_dai_name	= "wm5102-aif2",
-+		.codec_dai_name	= "wm8804-spdif",
-+		.codec_name	= "wm8804.1-003b",
-+		.dai_fmt	=   SND_SOC_DAIFMT_I2S
-+				  | SND_SOC_DAIFMT_NB_NF
-+				  | SND_SOC_DAIFMT_CBM_CFM,
-+		.ignore_suspend = 1,
-+		.params		= &rpi_cirrus_dai_link2_params,
-+		.init		= rpi_cirrus_init_wm8804,
-+	},
-+};
-+
-+
-+static int rpi_cirrus_late_probe(struct snd_soc_card *card)
-+{
-+	struct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);
-+	struct snd_soc_pcm_runtime *wm5102_runtime = get_wm5102_runtime(card);
-+	struct snd_soc_pcm_runtime *wm8804_runtime = get_wm8804_runtime(card);
-+	int ret;
-+
-+	dev_dbg(card->dev, "iec958_bits: %02x %02x %02x %02x\n",
-+		priv->iec958_status[0],
-+		priv->iec958_status[1],
-+		priv->iec958_status[2],
-+		priv->iec958_status[3]);
-+
-+	ret = snd_soc_dai_set_sysclk(
-+		wm5102_runtime->codec_dai, ARIZONA_CLK_SYSCLK, 0, 0);
-+	if (ret) {
-+		dev_err(card->dev,
-+			"Failed to set WM5102 codec dai clk domain: %d\n", ret);
-+		return ret;
-+	}
-+
-+	ret = snd_soc_dai_set_sysclk(
-+		wm8804_runtime->cpu_dai, ARIZONA_CLK_SYSCLK, 0, 0);
-+	if (ret)
-+		dev_err(card->dev,
-+			"Failed to set WM8804 codec dai clk domain: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+/* audio machine driver */
-+static struct snd_soc_card rpi_cirrus_card = {
-+	.name			= "RPi-Cirrus",
-+	.driver_name		= "RPiCirrus",
-+	.owner			= THIS_MODULE,
-+	.dai_link		= rpi_cirrus_dai,
-+	.num_links		= ARRAY_SIZE(rpi_cirrus_dai),
-+	.late_probe		= rpi_cirrus_late_probe,
-+	.controls		= rpi_cirrus_controls,
-+	.num_controls		= ARRAY_SIZE(rpi_cirrus_controls),
-+	.dapm_widgets		= rpi_cirrus_dapm_widgets,
-+	.num_dapm_widgets	= ARRAY_SIZE(rpi_cirrus_dapm_widgets),
-+	.dapm_routes		= rpi_cirrus_dapm_routes,
-+	.num_dapm_routes	= ARRAY_SIZE(rpi_cirrus_dapm_routes),
-+	.set_bias_level		= rpi_cirrus_set_bias_level,
-+	.set_bias_level_post	= rpi_cirrus_set_bias_level_post,
-+};
-+
-+static int rpi_cirrus_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+	struct rpi_cirrus_priv *priv;
-+	struct device_node *i2s_node;
-+
-+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	priv->min_rate_idx = 1; /* min samplerate 32kHz */
-+	priv->card_rate = RPI_CIRRUS_DEFAULT_RATE;
-+
-+	mutex_init(&priv->lock);
-+
-+	snd_soc_card_set_drvdata(&rpi_cirrus_card, priv);
-+
-+	if (!pdev->dev.of_node)
-+		return -ENODEV;
-+
-+	i2s_node = of_parse_phandle(
-+			pdev->dev.of_node, "i2s-controller", 0);
-+	if (!i2s_node) {
-+		dev_err(&pdev->dev, "i2s-controller missing in DT\n");
-+		return -ENODEV;
-+	}
-+
-+	rpi_cirrus_dai[DAI_WM5102].cpu_of_node = i2s_node;
-+	rpi_cirrus_dai[DAI_WM5102].platform_of_node = i2s_node;
-+
-+	rpi_cirrus_card.dev = &pdev->dev;
-+
-+	ret = devm_snd_soc_register_card(&pdev->dev, &rpi_cirrus_card);
-+	if (ret) {
-+		if (ret == -EPROBE_DEFER)
-+			dev_dbg(&pdev->dev,
-+				"register card requested probe deferral\n");
-+		else
-+			dev_err(&pdev->dev,
-+				"Failed to register card: %d\n", ret);
-+	}
-+
-+	return ret;
-+}
-+
-+static const struct of_device_id rpi_cirrus_of_match[] = {
-+	{ .compatible = "wlf,rpi-cirrus", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, rpi_cirrus_of_match);
-+
-+static struct platform_driver rpi_cirrus_driver = {
-+	.driver	= {
-+		.name   = "snd-rpi-cirrus",
-+		.of_match_table = of_match_ptr(rpi_cirrus_of_match),
-+	},
-+	.probe	= rpi_cirrus_probe,
-+};
-+
-+module_platform_driver(rpi_cirrus_driver);
-+
-+MODULE_AUTHOR("Matthias Reichl <hias@horus.com>");
-+MODULE_DESCRIPTION("ASoC driver for Cirrus Logic Audio Card");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/brcm2708/patches-4.14/950-0084-sound-Support-for-Dion-Audio-LOCO-V2-DAC-AMP-HAT.patch b/target/linux/brcm2708/patches-4.14/950-0084-sound-Support-for-Dion-Audio-LOCO-V2-DAC-AMP-HAT.patch
deleted file mode 100644
index e9aa128a6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0084-sound-Support-for-Dion-Audio-LOCO-V2-DAC-AMP-HAT.patch
+++ /dev/null
@@ -1,190 +0,0 @@
-From 9698288ce060841ca673ed296cc931130a566a12 Mon Sep 17 00:00:00 2001
-From: Miquel <miquelblauw@hotmail.com>
-Date: Fri, 24 Feb 2017 20:51:06 +0100
-Subject: [PATCH 084/454] sound: Support for Dion Audio LOCO-V2 DAC-AMP HAT
-
-Signed-off-by: Miquel Blauw <info@dionaudio.nl>
----
- sound/soc/bcm/Kconfig             |   7 ++
- sound/soc/bcm/Makefile            |   2 +
- sound/soc/bcm/dionaudio_loco-v2.c | 140 ++++++++++++++++++++++++++++++
- 3 files changed, 149 insertions(+)
- create mode 100644 sound/soc/bcm/dionaudio_loco-v2.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -134,6 +134,13 @@ config SND_BCM2708_SOC_DIONAUDIO_LOCO
- 	help
- 	  Say Y or M if you want to add support for Dion Audio LOCO.
- 
-+config SND_BCM2708_SOC_DIONAUDIO_LOCO_V2
-+	tristate "Support for Dion Audio LOCO-V2 DAC-AMP"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM5122
-+	help
-+	  Say Y or M if you want to add support for Dion Audio LOCO-V2.
-+
- config SND_BCM2708_SOC_ALLO_PIANO_DAC
- 	tristate "Support for Allo Piano DAC"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -25,6 +25,7 @@ snd-soc-raspidac3-objs := raspidac3.o
- snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
- snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o
- snd-soc-dionaudio-loco-objs := dionaudio_loco.o
-+snd-soc-dionaudio-loco-v2-objs := dionaudio_loco-v2.o
- snd-soc-allo-boss-dac-objs := allo-boss-dac.o
- snd-soc-allo-piano-dac-objs := allo-piano-dac.o
- snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o
-@@ -46,6 +47,7 @@ obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3)
- obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
- obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o
- obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o
-+obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2) += snd-soc-dionaudio-loco-v2.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC) += snd-soc-allo-boss-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o
---- /dev/null
-+++ b/sound/soc/bcm/dionaudio_loco-v2.c
-@@ -0,0 +1,140 @@
-+/*
-+ * ASoC Driver for Dion Audio LOCO-V2 DAC-AMP
-+ *
-+ * Author:      Miquel Blauw <info@dionaudio.nl>
-+ *              Copyright 2017
-+ *
-+ * Based on the software of the RPi-DAC writen by Florian Meier
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static bool digital_gain_0db_limit = true;
-+
-+static int snd_rpi_dionaudio_loco_v2_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	if (digital_gain_0db_limit) {
-+		int ret;
-+		struct snd_soc_card *card = rtd->card;
-+
-+		ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207);
-+		if (ret < 0)
-+			dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
-+	}
-+
-+	return 0;
-+}
-+
-+static int snd_rpi_dionaudio_loco_v2_hw_params(
-+	struct snd_pcm_substream *substream,
-+	struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_dionaudio_loco_v2_ops = {
-+	.hw_params = snd_rpi_dionaudio_loco_v2_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_dionaudio_loco_v2_dai[] = {
-+{
-+	.name		= "DionAudio LOCO-V2",
-+	.stream_name	= "DionAudio LOCO-V2 DAC-AMP",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "pcm512x-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "pcm512x.1-004d",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+			  SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_dionaudio_loco_v2_ops,
-+	.init		= snd_rpi_dionaudio_loco_v2_init,
-+},};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_dionaudio_loco_v2 = {
-+	.name         = "Dion Audio LOCO-V2",
-+	.dai_link     = snd_rpi_dionaudio_loco_v2_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_dionaudio_loco_v2_dai),
-+};
-+
-+static int snd_rpi_dionaudio_loco_v2_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_dionaudio_loco_v2.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai =
-+					&snd_rpi_dionaudio_loco_v2_dai[0];
-+
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					    "i2s-controller", 0);
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+
-+		digital_gain_0db_limit = !of_property_read_bool(
-+			pdev->dev.of_node, "dionaudio,24db_digital_gain");
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_dionaudio_loco_v2);
-+	if (ret)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
-+			ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_dionaudio_loco_v2_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_dionaudio_loco_v2);
-+}
-+
-+static const struct of_device_id dionaudio_of_match[] = {
-+	{ .compatible = "dionaudio,dionaudio-loco-v2", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, dionaudio_of_match);
-+
-+static struct platform_driver snd_rpi_dionaudio_loco_v2_driver = {
-+	.driver = {
-+		.name   = "snd-rpi-dionaudio-loco-v2",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = dionaudio_of_match,
-+	},
-+	.probe          = snd_rpi_dionaudio_loco_v2_probe,
-+	.remove         = snd_rpi_dionaudio_loco_v2_remove,
-+};
-+
-+module_platform_driver(snd_rpi_dionaudio_loco_v2_driver);
-+
-+MODULE_AUTHOR("Miquel Blauw <info@dionaudio.nl>");
-+MODULE_DESCRIPTION("ASoC Driver for DionAudio LOCO-V2");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0085-Add-support-for-Fe-Pi-audio-sound-card.-1867.patch b/target/linux/brcm2708/patches-4.14/950-0085-Add-support-for-Fe-Pi-audio-sound-card.-1867.patch
deleted file mode 100644
index d92bc84bc..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0085-Add-support-for-Fe-Pi-audio-sound-card.-1867.patch
+++ /dev/null
@@ -1,209 +0,0 @@
-From 5ab1ef51caf57e4419bdc6fe1e59ea99dd54ce09 Mon Sep 17 00:00:00 2001
-From: Fe-Pi <fe-pi@cox.net>
-Date: Wed, 1 Mar 2017 04:42:43 -0700
-Subject: [PATCH 085/454] Add support for Fe-Pi audio sound card. (#1867)
-
-Fe-Pi Audio Sound Card is based on NXP SGTL5000 codec.
-Mechanical specification of the board is the same the Raspberry Pi Zero.
-3.5mm jacks for Headphone/Mic, Line In, and Line Out.
-
-Signed-off-by: Henry Kupis <fe-pi@cox.net>
----
- sound/soc/bcm/Kconfig       |   7 ++
- sound/soc/bcm/Makefile      |   2 +
- sound/soc/bcm/fe-pi-audio.c | 158 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 167 insertions(+)
- create mode 100644 sound/soc/bcm/fe-pi-audio.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -162,6 +162,13 @@ config SND_BCM2708_SOC_ALLO_BOSS_DAC
- 	help
- 	  Say Y or M if you want to add support for Allo Boss DAC.
- 
-+config SND_BCM2708_SOC_FE_PI_AUDIO
-+	tristate "Support for Fe-Pi-Audio"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_SGTL5000
-+	help
-+	  Say Y or M if you want to add support for Fe-Pi-Audio.
-+
- config SND_PISOUND
- 	tristate "Support for Blokas Labs pisound"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -30,6 +30,7 @@ snd-soc-allo-boss-dac-objs := allo-boss-
- snd-soc-allo-piano-dac-objs := allo-piano-dac.o
- snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o
- snd-soc-pisound-objs := pisound.o
-+snd-soc-fe-pi-audio-objs := fe-pi-audio.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
-@@ -52,3 +53,4 @@ obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_D
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o
- obj-$(CONFIG_SND_PISOUND) += snd-soc-pisound.o
-+obj-$(CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO) += snd-soc-fe-pi-audio.o
---- /dev/null
-+++ b/sound/soc/bcm/fe-pi-audio.c
-@@ -0,0 +1,158 @@
-+/*
-+ * ASoC Driver for Fe-Pi Audio Sound Card
-+ *
-+ * Author:	Henry Kupis <kuupaz@gmail.com>
-+ *		Copyright 2016
-+ *		based on code by Florian Meier <florian.meier@koalo.de>
-+ *		based on code by Shawn Guo <shawn.guo@linaro.org>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+#include "../codecs/sgtl5000.h"
-+
-+static int snd_fe_pi_audio_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_card *card = rtd->card;
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	snd_soc_dapm_force_enable_pin(&card->dapm, "LO");
-+	snd_soc_dapm_force_enable_pin(&card->dapm, "ADC");
-+	snd_soc_dapm_force_enable_pin(&card->dapm, "DAC");
-+	snd_soc_dapm_force_enable_pin(&card->dapm, "HP");
-+	snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
-+			SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
-+
-+	return 0;
-+}
-+
-+static int snd_fe_pi_audio_hw_params(struct snd_pcm_substream *substream,
-+	struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct device *dev = rtd->card->dev;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+
-+	int ret;
-+
-+	/* Set SGTL5000's SYSCLK */
-+	ret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, 12288000, SND_SOC_CLOCK_IN);
-+	if (ret) {
-+		dev_err(dev, "could not set codec driver clock params\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+static struct snd_soc_ops snd_fe_pi_audio_ops = {
-+	.hw_params = snd_fe_pi_audio_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_fe_pi_audio_dai[] = {
-+	{
-+		.name		= "FE-PI",
-+		.stream_name	= "Fe-Pi HiFi",
-+		.cpu_dai_name	= "bcm2708-i2s.0",
-+		.codec_dai_name	= "sgtl5000",
-+		.platform_name	= "bcm2708-i2s.0",
-+		.codec_name	= "sgtl5000.1-000a",
-+		.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+					SND_SOC_DAIFMT_CBM_CFM,
-+		.ops		= &snd_fe_pi_audio_ops,
-+		.init		= snd_fe_pi_audio_init,
-+	},
-+};
-+
-+static const struct snd_soc_dapm_route fe_pi_audio_dapm_routes[] = {
-+	{"ADC", NULL, "Mic Bias"},
-+};
-+
-+
-+static struct snd_soc_card fe_pi_audio = {
-+	.name         = "Fe-Pi Audio",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_fe_pi_audio_dai,
-+	.num_links    = ARRAY_SIZE(snd_fe_pi_audio_dai),
-+
-+	.dapm_routes = fe_pi_audio_dapm_routes,
-+	.num_dapm_routes = ARRAY_SIZE(fe_pi_audio_dapm_routes),
-+};
-+
-+static int snd_fe_pi_audio_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+	struct snd_soc_card *card = &fe_pi_audio;
-+	struct device_node *np = pdev->dev.of_node;
-+	struct device_node *i2s_node;
-+	struct snd_soc_dai_link *dai = &snd_fe_pi_audio_dai[0];
-+
-+	fe_pi_audio.dev = &pdev->dev;
-+
-+	i2s_node = of_parse_phandle(np, "i2s-controller", 0);
-+	if (!i2s_node) {
-+		dev_err(&pdev->dev, "i2s_node phandle missing or invalid\n");
-+		return -EINVAL;
-+	}
-+
-+	dai->cpu_dai_name = NULL;
-+	dai->cpu_of_node = i2s_node;
-+	dai->platform_name = NULL;
-+	dai->platform_of_node = i2s_node;
-+
-+	of_node_put(i2s_node);
-+
-+	card->dev = &pdev->dev;
-+	platform_set_drvdata(pdev, card);
-+
-+	ret = snd_soc_register_card(card);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_fe_pi_audio_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&fe_pi_audio);
-+}
-+
-+static const struct of_device_id snd_fe_pi_audio_of_match[] = {
-+	{ .compatible = "fe-pi,fe-pi-audio", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_fe_pi_audio_of_match);
-+
-+static struct platform_driver snd_fe_pi_audio_driver = {
-+        .driver = {
-+                .name   = "snd-fe-pi-audio",
-+                .owner  = THIS_MODULE,
-+                .of_match_table = snd_fe_pi_audio_of_match,
-+        },
-+        .probe          = snd_fe_pi_audio_probe,
-+        .remove         = snd_fe_pi_audio_remove,
-+};
-+
-+module_platform_driver(snd_fe_pi_audio_driver);
-+
-+MODULE_AUTHOR("Henry Kupis <fe-pi@cox.net>");
-+MODULE_DESCRIPTION("ASoC Driver for Fe-Pi Audio");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0086-Add-support-for-the-AudioInjector.net-Octo-sound-car.patch b/target/linux/brcm2708/patches-4.14/950-0086-Add-support-for-the-AudioInjector.net-Octo-sound-car.patch
deleted file mode 100644
index d39648398..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0086-Add-support-for-the-AudioInjector.net-Octo-sound-car.patch
+++ /dev/null
@@ -1,404 +0,0 @@
-From 9dc67d61a5cd72eb80482aa1540e08a51e37172c Mon Sep 17 00:00:00 2001
-From: Matt Flax <flatmax@flatmax.org>
-Date: Wed, 8 Mar 2017 20:04:13 +1100
-Subject: [PATCH 086/454] Add support for the AudioInjector.net Octo sound card
-
-AudioInjector Octo: sample rates, regulators, reset
-
-This patch adds new sample rates to the Audioinjector Octo sound card. The
-new supported rates are (in kHz) :
-96, 48, 32, 24, 16, 8, 88.2, 44.1, 29.4, 22.05, 14.7
-
-Reference the bcm270x DT regulators in the overlay.
-
-This patch adds a reset GPIO for the AudioInjector.net octo sound card.
-
-Audioinjector octo : Make the playback and capture symmetric
-
-This patch ensures that the sample rate and channel count of the audioinjector
-octo sound card are symmetric.
----
- sound/soc/bcm/Kconfig                        |   7 +
- sound/soc/bcm/Makefile                       |   2 +
- sound/soc/bcm/audioinjector-octo-soundcard.c | 341 +++++++++++++++++++
- 3 files changed, 350 insertions(+)
- create mode 100644 sound/soc/bcm/audioinjector-octo-soundcard.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -119,6 +119,13 @@ config SND_AUDIOINJECTOR_PI_SOUNDCARD
- 	help
- 	  Say Y or M if you want to add support for audioinjector.net Pi Hat
- 
-+config SND_AUDIOINJECTOR_OCTO_SOUNDCARD
-+	tristate "Support for audioinjector.net Octo channel (Hat) soundcard"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_CS42XX8_I2C
-+	help
-+	  Say Y or M if you want to add support for audioinjector.net octo add on
-+
- config SND_DIGIDAC1_SOUNDCARD
-         tristate "Support for Red Rocks Audio DigiDAC1"
-         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -23,6 +23,7 @@ snd-soc-iqaudio-dac-objs := iqaudio-dac.
- snd-soc-iqaudio-digi-objs := iqaudio_digi.o
- snd-soc-raspidac3-objs := raspidac3.o
- snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
-+snd-soc-audioinjector-octo-soundcard-objs := audioinjector-octo-soundcard.o
- snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o
- snd-soc-dionaudio-loco-objs := dionaudio_loco.o
- snd-soc-dionaudio-loco-v2-objs := dionaudio_loco-v2.o
-@@ -46,6 +47,7 @@ obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI) += snd-soc-iqaudio-digi.o
- obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o
- obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
-+obj-$(CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD) += snd-soc-audioinjector-octo-soundcard.o
- obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o
- obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o
- obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2) += snd-soc-dionaudio-loco-v2.o
---- /dev/null
-+++ b/sound/soc/bcm/audioinjector-octo-soundcard.c
-@@ -0,0 +1,341 @@
-+/*
-+ * ASoC Driver for AudioInjector Pi octo channel soundcard (hat)
-+ *
-+ *  Created on: 27-October-2016
-+ *      Author: flatmax@flatmax.org
-+ *              based on audioinjector-pi-soundcard.c
-+ *
-+ * Copyright (C) 2016 Flatmax Pty. Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/gpio/consumer.h>
-+
-+#include <sound/core.h>
-+#include <sound/soc.h>
-+#include <sound/pcm_params.h>
-+#include <sound/control.h>
-+
-+static struct gpio_descs *mult_gpios;
-+static struct gpio_desc *codec_rst_gpio;
-+static unsigned int audioinjector_octo_rate;
-+
-+static const unsigned int audioinjector_octo_rates[] = {
-+	96000, 48000, 32000, 24000, 16000, 8000, 88200, 44100, 29400, 22050, 14700,
-+};
-+
-+static struct snd_pcm_hw_constraint_list audioinjector_octo_constraints = {
-+	.list = audioinjector_octo_rates,
-+	.count = ARRAY_SIZE(audioinjector_octo_rates),
-+};
-+
-+static int audioinjector_octo_dai_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	return snd_soc_dai_set_bclk_ratio(rtd->cpu_dai, 64);
-+}
-+
-+static int audioinjector_octo_startup(struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	rtd->cpu_dai->driver->playback.channels_min = 8;
-+	rtd->cpu_dai->driver->playback.channels_max = 8;
-+	rtd->cpu_dai->driver->capture.channels_min = 8;
-+	rtd->cpu_dai->driver->capture.channels_max = 8;
-+	rtd->codec_dai->driver->capture.channels_max = 8;
-+	
-+	snd_pcm_hw_constraint_list(substream->runtime, 0,
-+				SNDRV_PCM_HW_PARAM_RATE,
-+				&audioinjector_octo_constraints);
-+
-+	return 0;
-+}
-+
-+static void audioinjector_octo_shutdown(struct snd_pcm_substream *substream)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	rtd->cpu_dai->driver->playback.channels_min = 2;
-+	rtd->cpu_dai->driver->playback.channels_max = 2;
-+	rtd->cpu_dai->driver->capture.channels_min = 2;
-+	rtd->cpu_dai->driver->capture.channels_max = 2;
-+	rtd->codec_dai->driver->capture.channels_max = 6;
-+}
-+
-+static int audioinjector_octo_hw_params(struct snd_pcm_substream *substream,
-+	struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+
-+	// set codec DAI configuration
-+	int ret = snd_soc_dai_set_fmt(rtd->codec_dai,
-+			SND_SOC_DAIFMT_CBS_CFS|SND_SOC_DAIFMT_DSP_A|
-+			SND_SOC_DAIFMT_NB_NF);
-+	if (ret < 0)
-+		return ret;
-+
-+	// set cpu DAI configuration
-+	ret = snd_soc_dai_set_fmt(rtd->cpu_dai,
-+			SND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|
-+			SND_SOC_DAIFMT_NB_NF);
-+	if (ret < 0)
-+		return ret;
-+
-+	audioinjector_octo_rate = params_rate(params);
-+
-+	// Set the correct sysclock for the codec
-+	switch (audioinjector_octo_rate) {
-+	case 96000:
-+	case 48000:
-+		return snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 49152000,
-+									0);
-+		break;
-+	case 24000:
-+		return snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 49152000/2,
-+									0);
-+		break;
-+	case 32000:
-+	case 16000:
-+		return snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 49152000/3,
-+									0);
-+		break;
-+	case 8000:
-+		return snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 49152000/6,
-+									0);
-+		break;
-+	case 88200:
-+	case 44100:
-+		return snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 45185400,
-+									0);
-+		break;
-+	case 22050:
-+		return snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 45185400/2,
-+									0);
-+		break;
-+	case 29400:
-+	case 14700:
-+		return snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 45185400/3,
-+									0);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int audioinjector_octo_trigger(struct snd_pcm_substream *substream,
-+								int cmd){
-+	int mult[4];
-+	mult[0] = 0;
-+	mult[1] = 0;
-+	mult[2] = 0;
-+	mult[3] = 0;
-+
-+	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_START:
-+	case SNDRV_PCM_TRIGGER_RESUME:
-+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+		switch (audioinjector_octo_rate) {
-+		case 96000:
-+			mult[3] = 1;
-+		case 88200:
-+			mult[1] = 1;
-+			mult[2] = 1;
-+			break;
-+		case 48000:
-+			mult[3] = 1;
-+		case 44100:
-+			mult[2] = 1;
-+			break;
-+		case 32000:
-+			mult[3] = 1;
-+		case 29400:
-+			mult[0] = 1;
-+			mult[1] = 1;
-+			break;
-+		case 24000:
-+			mult[3] = 1;
-+		case 22050:
-+			mult[1] = 1;
-+			break;
-+		case 16000:
-+			mult[3] = 1;
-+		case 14700:
-+			mult[0] = 1;
-+			break;
-+		case 8000:
-+			mult[3] = 1;
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		break;
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+	gpiod_set_array_value_cansleep(mult_gpios->ndescs, mult_gpios->desc,
-+									mult);
-+
-+	return 0;
-+}
-+
-+static struct snd_soc_ops audioinjector_octo_ops = {
-+	.startup	= audioinjector_octo_startup,
-+	.shutdown	= audioinjector_octo_shutdown,
-+	.hw_params = audioinjector_octo_hw_params,
-+	.trigger = audioinjector_octo_trigger,
-+};
-+
-+static struct snd_soc_dai_link audioinjector_octo_dai[] = {
-+	{
-+		.name = "AudioInjector Octo",
-+		.stream_name = "AudioInject-HIFI",
-+		.codec_dai_name = "cs42448",
-+		.ops = &audioinjector_octo_ops,
-+		.init = audioinjector_octo_dai_init,
-+		.symmetric_rates = 1,
-+		.symmetric_channels = 1,
-+	},
-+};
-+
-+static const struct snd_soc_dapm_widget audioinjector_octo_widgets[] = {
-+	SND_SOC_DAPM_OUTPUT("OUTPUTS0"),
-+	SND_SOC_DAPM_OUTPUT("OUTPUTS1"),
-+	SND_SOC_DAPM_OUTPUT("OUTPUTS2"),
-+	SND_SOC_DAPM_OUTPUT("OUTPUTS3"),
-+	SND_SOC_DAPM_INPUT("INPUTS0"),
-+	SND_SOC_DAPM_INPUT("INPUTS1"),
-+	SND_SOC_DAPM_INPUT("INPUTS2"),
-+};
-+
-+static const struct snd_soc_dapm_route audioinjector_octo_route[] = {
-+	/* Balanced outputs */
-+	{"OUTPUTS0", NULL, "AOUT1L"},
-+	{"OUTPUTS0", NULL, "AOUT1R"},
-+	{"OUTPUTS1", NULL, "AOUT2L"},
-+	{"OUTPUTS1", NULL, "AOUT2R"},
-+	{"OUTPUTS2", NULL, "AOUT3L"},
-+	{"OUTPUTS2", NULL, "AOUT3R"},
-+	{"OUTPUTS3", NULL, "AOUT4L"},
-+	{"OUTPUTS3", NULL, "AOUT4R"},
-+
-+	/* Balanced inputs */
-+	{"AIN1L", NULL, "INPUTS0"},
-+	{"AIN1R", NULL, "INPUTS0"},
-+	{"AIN2L", NULL, "INPUTS1"},
-+	{"AIN2R", NULL, "INPUTS1"},
-+	{"AIN3L", NULL, "INPUTS2"},
-+	{"AIN3R", NULL, "INPUTS2"},
-+};
-+
-+static struct snd_soc_card snd_soc_audioinjector_octo = {
-+	.name = "audioinjector-octo-soundcard",
-+	.dai_link = audioinjector_octo_dai,
-+	.num_links = ARRAY_SIZE(audioinjector_octo_dai),
-+
-+	.dapm_widgets = audioinjector_octo_widgets,
-+	.num_dapm_widgets = ARRAY_SIZE(audioinjector_octo_widgets),
-+	.dapm_routes = audioinjector_octo_route,
-+	.num_dapm_routes = ARRAY_SIZE(audioinjector_octo_route),
-+};
-+
-+static int audioinjector_octo_probe(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = &snd_soc_audioinjector_octo;
-+	int ret;
-+
-+	card->dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct snd_soc_dai_link *dai = &audioinjector_octo_dai[0];
-+		struct device_node *i2s_node =
-+					of_parse_phandle(pdev->dev.of_node,
-+							"i2s-controller", 0);
-+		struct device_node *codec_node =
-+					of_parse_phandle(pdev->dev.of_node,
-+								"codec", 0);
-+
-+		mult_gpios = devm_gpiod_get_array_optional(&pdev->dev, "mult",
-+								GPIOD_OUT_LOW);
-+		if (IS_ERR(mult_gpios))
-+			return PTR_ERR(mult_gpios);
-+
-+		codec_rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
-+								GPIOD_OUT_LOW);
-+		if (IS_ERR(codec_rst_gpio))
-+			return PTR_ERR(codec_rst_gpio);
-+
-+		if (codec_rst_gpio)
-+			gpiod_set_value(codec_rst_gpio, 1);
-+		msleep(500);
-+		if (codec_rst_gpio)
-+			gpiod_set_value(codec_rst_gpio, 0);
-+		msleep(500);
-+		if (codec_rst_gpio)
-+			gpiod_set_value(codec_rst_gpio, 1);
-+		msleep(500);
-+
-+		if (i2s_node && codec_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+			dai->codec_name = NULL;
-+			dai->codec_of_node = codec_node;
-+		} else
-+			if (!dai->cpu_of_node) {
-+				dev_err(&pdev->dev,
-+				"i2s-controller missing or invalid in DT\n");
-+				return -EINVAL;
-+			} else {
-+				dev_err(&pdev->dev,
-+				"Property 'codec' missing or invalid\n");
-+				return -EINVAL;
-+			}
-+	}
-+
-+	ret = snd_soc_register_card(card);
-+	if (ret != 0)
-+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
-+	return ret;
-+}
-+
-+static int audioinjector_octo_remove(struct platform_device *pdev)
-+{
-+	struct snd_soc_card *card = platform_get_drvdata(pdev);
-+
-+	return snd_soc_unregister_card(card);
-+}
-+
-+static const struct of_device_id audioinjector_octo_of_match[] = {
-+	{ .compatible = "ai,audioinjector-octo-soundcard", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, audioinjector_octo_of_match);
-+
-+static struct platform_driver audioinjector_octo_driver = {
-+	.driver	= {
-+		.name			= "audioinjector-octo",
-+		.owner			= THIS_MODULE,
-+		.of_match_table = audioinjector_octo_of_match,
-+	},
-+	.probe	= audioinjector_octo_probe,
-+	.remove	= audioinjector_octo_remove,
-+};
-+
-+module_platform_driver(audioinjector_octo_driver);
-+MODULE_AUTHOR("Matt Flax <flatmax@flatmax.org>");
-+MODULE_DESCRIPTION("AudioInjector.net octo Soundcard");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:audioinjector-octo-soundcard");
diff --git a/target/linux/brcm2708/patches-4.14/950-0087-Driver-support-for-Google-voiceHAT-soundcard.patch b/target/linux/brcm2708/patches-4.14/950-0087-Driver-support-for-Google-voiceHAT-soundcard.patch
deleted file mode 100644
index ac02aca89..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0087-Driver-support-for-Google-voiceHAT-soundcard.patch
+++ /dev/null
@@ -1,383 +0,0 @@
-From 5f1aa4352ca253ca76ee49c51292994d517d7e4e Mon Sep 17 00:00:00 2001
-From: Peter Malkin <petermalkin@google.com>
-Date: Mon, 27 Mar 2017 16:38:21 -0700
-Subject: [PATCH 087/454] Driver support for Google voiceHAT soundcard.
-
----
- sound/soc/bcm/Kconfig                    |   7 +
- sound/soc/bcm/Makefile                   |   6 +
- sound/soc/bcm/googlevoicehat-codec.c     | 199 +++++++++++++++++++++++
- sound/soc/bcm/googlevoicehat-soundcard.c | 124 ++++++++++++++
- 4 files changed, 336 insertions(+)
- create mode 100644 sound/soc/bcm/googlevoicehat-codec.c
- create mode 100644 sound/soc/bcm/googlevoicehat-soundcard.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -18,6 +18,13 @@ config SND_SOC_CYGNUS
- 
- 	  If you don't know what to do here, say N.
- 
-+config SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD
-+	tristate "Support for Google voiceHAT soundcard"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_VOICEHAT
-+	help
-+          Say Y or M if you want to add support for voiceHAT soundcard.
-+
- config SND_BCM2708_SOC_HIFIBERRY_DAC
-         tristate "Support for HifiBerry DAC"
-         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -8,8 +8,12 @@ snd-soc-cygnus-objs := cygnus-pcm.o cygn
- 
- obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-cygnus.o
- 
-+# Google voiceHAT custom codec support
-+snd-soc-googlevoicehat-codec-objs := googlevoicehat-codec.o
-+
- # BCM2708 Machine Support
- snd-soc-adau1977-adc-objs := adau1977-adc.o
-+snd-soc-googlevoicehat-soundcard-objs := googlevoicehat-soundcard.o
- snd-soc-hifiberry-amp-objs := hifiberry_amp.o
- snd-soc-hifiberry-dac-objs := hifiberry_dac.o
- snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
-@@ -34,6 +38,8 @@ snd-soc-pisound-objs := pisound.o
- snd-soc-fe-pi-audio-objs := fe-pi-audio.o
- 
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
-+obj-$(CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD) += snd-soc-googlevoicehat-soundcard.o
-+obj-$(CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD)  += snd-soc-googlevoicehat-codec.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
---- /dev/null
-+++ b/sound/soc/bcm/googlevoicehat-codec.c
-@@ -0,0 +1,199 @@
-+/*
-+ * Driver for the Google voiceHAT audio codec for Raspberry Pi.
-+ *
-+ * Author:	Peter Malkin <petermalkin@google.com>
-+ *		Copyright 2016
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/err.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/version.h>
-+#include <sound/pcm.h>
-+#include <sound/soc.h>
-+#include <sound/soc-dai.h>
-+#include <sound/soc-dapm.h>
-+
-+#define ICS43432_RATE_MIN_HZ 7190  /* from data sheet */
-+#define ICS43432_RATE_MAX_HZ 52800 /* from data sheet */
-+#define SDMODE_DELAY_MS \
-+  5 /* Delay in enabling SDMODE after clock settles to remove pop */
-+
-+struct voicehat_priv {
-+  struct delayed_work enable_sdmode_work;
-+  struct gpio_desc *sdmode_gpio;
-+  unsigned int sdmode_delay;
-+};
-+
-+static void voicehat_enable_sdmode_work(struct work_struct *work) {
-+  struct voicehat_priv *voicehat =
-+      container_of(work, struct voicehat_priv, enable_sdmode_work.work);
-+  gpiod_set_value(voicehat->sdmode_gpio, 1);
-+}
-+
-+static int voicehat_codec_probe(struct snd_soc_codec *codec) {
-+  struct voicehat_priv *voicehat = snd_soc_codec_get_drvdata(codec);
-+
-+  voicehat->sdmode_gpio = devm_gpiod_get(codec->dev, "sdmode", GPIOD_OUT_LOW);
-+  if (IS_ERR(voicehat->sdmode_gpio)) {
-+    dev_err(codec->dev, "Unable to allocate GPIO pin\n");
-+    return PTR_ERR(voicehat->sdmode_gpio);
-+  }
-+
-+  INIT_DELAYED_WORK(&voicehat->enable_sdmode_work, voicehat_enable_sdmode_work);
-+  return 0;
-+}
-+
-+static int voicehat_codec_remove(struct snd_soc_codec *codec) {
-+  struct voicehat_priv *voicehat = snd_soc_codec_get_drvdata(codec);
-+
-+  cancel_delayed_work_sync(&voicehat->enable_sdmode_work);
-+
-+  return 0;
-+}
-+
-+static const struct snd_soc_dapm_widget voicehat_dapm_widgets[] = {
-+    SND_SOC_DAPM_OUTPUT("Speaker"),
-+};
-+
-+static const struct snd_soc_dapm_route voicehat_dapm_routes[] = {
-+    {"Speaker", NULL, "HiFi Playback"},
-+};
-+
-+static struct snd_soc_codec_driver voicehat_codec_driver = {
-+    .probe = voicehat_codec_probe,
-+    .remove = voicehat_codec_remove,
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)
-+    .component_driver = {
-+#endif
-+    .dapm_widgets = voicehat_dapm_widgets,
-+    .num_dapm_widgets = ARRAY_SIZE(voicehat_dapm_widgets),
-+    .dapm_routes = voicehat_dapm_routes,
-+    .num_dapm_routes = ARRAY_SIZE(voicehat_dapm_routes),
-+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)
-+    },
-+#endif
-+};
-+
-+static int voicehat_daiops_trigger(struct snd_pcm_substream *substream, int cmd,
-+                                struct snd_soc_dai *dai) {
-+  struct snd_soc_codec *codec = dai->codec;
-+  struct voicehat_priv *voicehat = snd_soc_codec_get_drvdata(codec);
-+
-+  if (voicehat->sdmode_delay == 0) return 0;
-+
-+  dev_dbg(dai->dev, "CMD             %d", cmd);
-+  dev_dbg(dai->dev, "Playback Active %d", dai->playback_active);
-+  dev_dbg(dai->dev, "Capture Active  %d", dai->capture_active);
-+
-+  switch (cmd) {
-+    case SNDRV_PCM_TRIGGER_START:
-+    case SNDRV_PCM_TRIGGER_RESUME:
-+    case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+      if (dai->playback_active) {
-+        dev_info(dai->dev, "Enabling audio amp...\n");
-+        queue_delayed_work(system_power_efficient_wq,
-+                           &voicehat->enable_sdmode_work,
-+                           msecs_to_jiffies(voicehat->sdmode_delay));
-+      }
-+      break;
-+    case SNDRV_PCM_TRIGGER_STOP:
-+    case SNDRV_PCM_TRIGGER_SUSPEND:
-+    case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+      if (dai->playback_active) {
-+        cancel_delayed_work(&voicehat->enable_sdmode_work);
-+        dev_info(dai->dev, "Disabling audio amp...\n");
-+        gpiod_set_value(voicehat->sdmode_gpio, 0);
-+      }
-+      break;
-+  }
-+  return 0;
-+}
-+
-+static const struct snd_soc_dai_ops voicehat_dai_ops = {
-+    .trigger = voicehat_daiops_trigger,
-+};
-+
-+static struct snd_soc_dai_driver voicehat_dai = {
-+    .name = "voicehat-hifi",
-+    .capture = {.stream_name = "HiFi Capture",
-+                .channels_min = 2,
-+                .channels_max = 2,
-+                .rates = SNDRV_PCM_RATE_48000,
-+                .formats = SNDRV_PCM_FMTBIT_S32_LE},
-+    .playback = {.stream_name = "HiFi Playback",
-+                 .channels_min = 2,
-+                 .channels_max = 2,
-+                 .rates = SNDRV_PCM_RATE_48000,
-+                 .formats = SNDRV_PCM_FMTBIT_S32_LE},
-+    .ops = &voicehat_dai_ops,
-+    .symmetric_rates = 1};
-+
-+#ifdef CONFIG_OF
-+static const struct of_device_id voicehat_ids[] = {
-+    {
-+        .compatible = "google,voicehat",
-+    },
-+    {}};
-+MODULE_DEVICE_TABLE(of, voicehat_ids);
-+#endif
-+
-+static int voicehat_platform_probe(struct platform_device *pdev) {
-+  struct voicehat_priv *voicehat;
-+  int ret;
-+
-+  voicehat = devm_kzalloc(&pdev->dev, sizeof(*voicehat), GFP_KERNEL);
-+  if (!voicehat) return -ENOMEM;
-+
-+  ret = device_property_read_u32(&pdev->dev, "voicehat_sdmode_delay",
-+                                 &voicehat->sdmode_delay);
-+
-+  if (ret) {
-+    voicehat->sdmode_delay = SDMODE_DELAY_MS;
-+    dev_info(&pdev->dev,
-+             "property 'voicehat_sdmode_delay' not found default 5 mS");
-+  } else {
-+    dev_info(&pdev->dev, "property 'voicehat_sdmode_delay' found delay= %d mS",
-+             voicehat->sdmode_delay);
-+  }
-+
-+  dev_set_drvdata(&pdev->dev, voicehat);
-+
-+  return snd_soc_register_codec(&pdev->dev, &voicehat_codec_driver, &voicehat_dai, 1);
-+}
-+
-+static int voicehat_platform_remove(struct platform_device *pdev) {
-+  snd_soc_unregister_codec(&pdev->dev);
-+  return 0;
-+}
-+
-+static struct platform_driver voicehat_driver = {
-+    .driver =
-+        {
-+            .name = "voicehat-codec", .of_match_table = of_match_ptr(voicehat_ids),
-+        },
-+    .probe = voicehat_platform_probe,
-+    .remove = voicehat_platform_remove,
-+};
-+
-+module_platform_driver(voicehat_driver);
-+
-+MODULE_DESCRIPTION("Google voiceHAT Codec driver");
-+MODULE_AUTHOR("Peter Malkin <petermalkin@google.com>");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/sound/soc/bcm/googlevoicehat-soundcard.c
-@@ -0,0 +1,124 @@
-+/*
-+ * ASoC Driver for Google voiceHAT SoundCard
-+ *
-+ * Author: Peter Malkin <petermalkin@google.com>
-+ *         Copyright 2016
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+
-+static int snd_rpi_googlevoicehat_soundcard_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	return 0;
-+}
-+
-+static int snd_rpi_googlevoicehat_soundcard_hw_params(
-+	struct snd_pcm_substream *substream,
-+	struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	unsigned int sample_bits =
-+		snd_pcm_format_physical_width(params_format(params));
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_rpi_googlevoicehat_soundcard_ops = {
-+	.hw_params = snd_rpi_googlevoicehat_soundcard_hw_params,
-+};
-+
-+static struct snd_soc_dai_link snd_rpi_googlevoicehat_soundcard_dai[] = {
-+{
-+	.name		= "Google voiceHAT SoundCard",
-+	.stream_name	= "Google voiceHAT SoundCard HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "voicehat-hifi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "voicehat-codec",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
-+				SND_SOC_DAIFMT_CBS_CFS,
-+	.ops		= &snd_rpi_googlevoicehat_soundcard_ops,
-+	.init		= snd_rpi_googlevoicehat_soundcard_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_rpi_googlevoicehat_soundcard = {
-+	.name         = "snd_rpi_googlevoicehat_soundcard",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_rpi_googlevoicehat_soundcard_dai,
-+	.num_links    = ARRAY_SIZE(snd_rpi_googlevoicehat_soundcard_dai),
-+};
-+
-+static int snd_rpi_googlevoicehat_soundcard_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_rpi_googlevoicehat_soundcard.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai = &snd_rpi_googlevoicehat_soundcard_dai[0];
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+					"i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+	}
-+
-+	ret = snd_soc_register_card(&snd_rpi_googlevoicehat_soundcard);
-+	if (ret)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static int snd_rpi_googlevoicehat_soundcard_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_rpi_googlevoicehat_soundcard);
-+}
-+
-+static const struct of_device_id snd_rpi_googlevoicehat_soundcard_of_match[] = {
-+	{ .compatible = "googlevoicehat,googlevoicehat-soundcard", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_rpi_googlevoicehat_soundcard_of_match);
-+
-+static struct platform_driver snd_rpi_googlevoicehat_soundcard_driver = {
-+	.driver = {
-+		.name   = "snd-googlevoicehat-soundcard",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_rpi_googlevoicehat_soundcard_of_match,
-+	},
-+	.probe          = snd_rpi_googlevoicehat_soundcard_probe,
-+	.remove         = snd_rpi_googlevoicehat_soundcard_remove,
-+};
-+
-+module_platform_driver(snd_rpi_googlevoicehat_soundcard_driver);
-+
-+MODULE_AUTHOR("Peter Malkin <petermalkin@google.com>");
-+MODULE_DESCRIPTION("ASoC Driver for Google voiceHAT SoundCard");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0088-Allo-Digione-Driver-2048.patch b/target/linux/brcm2708/patches-4.14/950-0088-Allo-Digione-Driver-2048.patch
deleted file mode 100644
index e017f552d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0088-Allo-Digione-Driver-2048.patch
+++ /dev/null
@@ -1,318 +0,0 @@
-From 525cdff530e74a8428a60859f9308bca825463fd Mon Sep 17 00:00:00 2001
-From: sandeepal <alsandeep@cem-solutions.net>
-Date: Fri, 2 Jun 2017 18:59:46 +0530
-Subject: [PATCH 088/454] Allo Digione Driver (#2048)
-
-Driver for the Allo Digione soundcard
-
-allo-digione: 192kHz clicking sound fix
-
-See: https://github.com/raspberrypi/linux/pull/2149
----
- sound/soc/bcm/Kconfig        |   7 +
- sound/soc/bcm/Makefile       |   2 +
- sound/soc/bcm/allo-digione.c | 265 +++++++++++++++++++++++++++++++++++
- 3 files changed, 274 insertions(+)
- create mode 100644 sound/soc/bcm/allo-digione.c
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -176,6 +176,13 @@ config SND_BCM2708_SOC_ALLO_BOSS_DAC
- 	help
- 	  Say Y or M if you want to add support for Allo Boss DAC.
- 
-+config SND_BCM2708_SOC_ALLO_DIGIONE 
-+        tristate "Support for Allo DigiOne"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_PCM512x_I2C
-+	help
-+	  Say Y or M if you want to add support for Allo DigiOne.
-+
- config SND_BCM2708_SOC_FE_PI_AUDIO
- 	tristate "Support for Fe-Pi-Audio"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -34,6 +34,7 @@ snd-soc-dionaudio-loco-v2-objs := dionau
- snd-soc-allo-boss-dac-objs := allo-boss-dac.o
- snd-soc-allo-piano-dac-objs := allo-piano-dac.o
- snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o
-+snd-soc-allo-digione-objs := allo-digione.o
- snd-soc-pisound-objs := pisound.o
- snd-soc-fe-pi-audio-objs := fe-pi-audio.o
- 
-@@ -60,5 +61,6 @@ obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_L
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC) += snd-soc-allo-boss-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o
-+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE) += snd-soc-allo-digione.o
- obj-$(CONFIG_SND_PISOUND) += snd-soc-pisound.o
- obj-$(CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO) += snd-soc-fe-pi-audio.o
---- /dev/null
-+++ b/sound/soc/bcm/allo-digione.c
-@@ -0,0 +1,265 @@
-+/*
-+ * ASoC Driver for Allo DigiOne
-+ *
-+ * Author: Baswaraj <jaikumar@cemsolutions.net>
-+ *	   Copyright 2017
-+ * based on code by Daniel Matuschek <info@crazy-audio.com>
-+ * based on code by Florian Meier <florian.meier@koalo.de>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+#include <sound/jack.h>
-+#include <linux/gpio/consumer.h>
-+
-+#include "../codecs/wm8804.h"
-+
-+static short int auto_shutdown_output;
-+module_param(auto_shutdown_output, short,
-+		S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
-+MODULE_PARM_DESC(auto_shutdown_output, "Shutdown SP/DIF output if playback is stopped");
-+
-+#define CLK_44EN_RATE 22579200UL
-+#define CLK_48EN_RATE 24576000UL
-+
-+static struct gpio_desc *snd_allo_clk44gpio;
-+static struct gpio_desc *snd_allo_clk48gpio;
-+
-+static int samplerate = 44100;
-+
-+static uint32_t snd_allo_digione_enable_clock(int sample_rate)
-+{
-+	switch (sample_rate) {
-+	case 11025:
-+	case 22050:
-+	case 44100:
-+	case 88200:
-+	case 176400:
-+		gpiod_set_value_cansleep(snd_allo_clk44gpio, 1);
-+		gpiod_set_value_cansleep(snd_allo_clk48gpio, 0);
-+		return CLK_44EN_RATE;
-+	default:
-+		gpiod_set_value_cansleep(snd_allo_clk48gpio, 1);
-+		gpiod_set_value_cansleep(snd_allo_clk44gpio, 0);
-+		return CLK_48EN_RATE;
-+	}
-+}
-+
-+
-+static int snd_allo_digione_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	/* enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	return 0;
-+}
-+
-+static int snd_allo_digione_startup(struct snd_pcm_substream *substream)
-+{
-+	/* turn on digital output */
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_codec *codec = rtd->codec;
-+
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00);
-+	return 0;
-+}
-+
-+static void snd_allo_digione_shutdown(struct snd_pcm_substream *substream)
-+{
-+	/* turn off output */
-+	if (auto_shutdown_output) {
-+		/* turn off output */
-+		struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+		struct snd_soc_codec *codec = rtd->codec;
-+
-+		snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c);
-+	}
-+}
-+
-+static int snd_allo_digione_hw_params(struct snd_pcm_substream *substream,
-+				       struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
-+	struct snd_soc_codec *codec = rtd->codec;
-+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
-+
-+	int sysclk = 27000000; /* This is fixed on this board */
-+
-+	long mclk_freq = 0;
-+	int mclk_div = 1;
-+	int sampling_freq = 1;
-+
-+	int ret;
-+
-+	samplerate = params_rate(params);
-+	mclk_freq = samplerate * 256;
-+	mclk_div = WM8804_MCLKDIV_256FS;
-+
-+	sysclk = snd_allo_digione_enable_clock(samplerate);
-+
-+	switch (samplerate) {
-+	case 32000:
-+		sampling_freq = 0x03;
-+		break;
-+	case 44100:
-+		sampling_freq = 0x00;
-+		break;
-+	case 48000:
-+		sampling_freq = 0x02;
-+		break;
-+	case 88200:
-+		sampling_freq = 0x08;
-+		break;
-+	case 96000:
-+		sampling_freq = 0x0a;
-+		break;
-+	case 176400:
-+		sampling_freq = 0x0c;
-+		break;
-+	case 192000:
-+		sampling_freq = 0x0e;
-+		break;
-+	default:
-+		dev_err(codec->dev,
-+		"Failed to set WM8804 SYSCLK, unsupported samplerate %d\n",
-+		samplerate);
-+	}
-+
-+	snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
-+	snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
-+
-+	ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
-+					sysclk, SND_SOC_CLOCK_OUT);
-+
-+	if (ret < 0) {
-+		dev_err(codec->dev,
-+		"Failed to set WM8804 SYSCLK: %d\n", ret);
-+		return ret;
-+	}
-+
-+	/* Enable TX output */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
-+
-+	/* Power on */
-+	snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
-+
-+	/* set sampling frequency status bits */
-+	snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq);
-+
-+	return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+}
-+
-+/* machine stream operations */
-+static struct snd_soc_ops snd_allo_digione_ops = {
-+	.hw_params	= snd_allo_digione_hw_params,
-+	.startup	= snd_allo_digione_startup,
-+	.shutdown	= snd_allo_digione_shutdown,
-+};
-+
-+static struct snd_soc_dai_link snd_allo_digione_dai[] = {
-+{
-+	.name		= "Allo DigiOne",
-+	.stream_name	= "Allo DigiOne HiFi",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_dai_name	= "wm8804-spdif",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.codec_name	= "wm8804.1-003b",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S |
-+			  SND_SOC_DAIFMT_NB_NF |
-+			  SND_SOC_DAIFMT_CBM_CFM,
-+	.ops		= &snd_allo_digione_ops,
-+	.init		= snd_allo_digione_init,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_allo_digione = {
-+	.name         = "snd_allo_digione",
-+	.driver_name  = "AlloDigiOne",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_allo_digione_dai,
-+	.num_links    = ARRAY_SIZE(snd_allo_digione_dai),
-+};
-+
-+static int snd_allo_digione_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_allo_digione.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai = &snd_allo_digione_dai[0];
-+
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+				"i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+
-+		snd_allo_clk44gpio =
-+			devm_gpiod_get(&pdev->dev, "clock44", GPIOD_OUT_LOW);
-+		if (IS_ERR(snd_allo_clk44gpio))
-+			dev_err(&pdev->dev, "devm_gpiod_get() failed\n");
-+
-+		snd_allo_clk48gpio =
-+			devm_gpiod_get(&pdev->dev, "clock48", GPIOD_OUT_LOW);
-+		if (IS_ERR(snd_allo_clk48gpio))
-+			dev_err(&pdev->dev, "devm_gpiod_get() failed\n");
-+	}
-+
-+	ret = snd_soc_register_card(&snd_allo_digione);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
-+			ret);
-+
-+	return ret;
-+}
-+
-+static int snd_allo_digione_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_allo_digione);
-+}
-+
-+static const struct of_device_id snd_allo_digione_of_match[] = {
-+	{ .compatible = "allo,allo-digione", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_allo_digione_of_match);
-+
-+static struct platform_driver snd_allo_digione_driver = {
-+	.driver = {
-+		.name		= "snd-allo-digione",
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= snd_allo_digione_of_match,
-+	},
-+	.probe  = snd_allo_digione_probe,
-+	.remove = snd_allo_digione_remove,
-+};
-+
-+module_platform_driver(snd_allo_digione_driver);
-+
-+MODULE_AUTHOR("Baswaraj <jaikumar@cem-solutions.net>");
-+MODULE_DESCRIPTION("ASoC Driver for Allo DigiOne");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0089-rpi_display-add-backlight-driver-and-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0089-rpi_display-add-backlight-driver-and-overlay.patch
deleted file mode 100644
index d11ef36ca..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0089-rpi_display-add-backlight-driver-and-overlay.patch
+++ /dev/null
@@ -1,164 +0,0 @@
-From 574dfed6fa4e845eab5632d5f956e7ec879d6416 Mon Sep 17 00:00:00 2001
-From: P33M <P33M@github.com>
-Date: Wed, 21 Oct 2015 14:55:21 +0100
-Subject: [PATCH 089/454] rpi_display: add backlight driver and overlay
-
-Add a mailbox-driven backlight controller for the Raspberry Pi DSI
-touchscreen display. Requires updated GPU firmware to recognise the
-mailbox request.
-
-Signed-off-by: Gordon Hollingworth <gordon@raspberrypi.org>
----
- drivers/video/backlight/Kconfig         |   6 ++
- drivers/video/backlight/Makefile        |   1 +
- drivers/video/backlight/rpi_backlight.c | 119 ++++++++++++++++++++++++
- 3 files changed, 126 insertions(+)
- create mode 100644 drivers/video/backlight/rpi_backlight.c
-
---- a/drivers/video/backlight/Kconfig
-+++ b/drivers/video/backlight/Kconfig
-@@ -265,6 +265,12 @@ config BACKLIGHT_PWM
- 	  If you have a LCD backlight adjustable by PWM, say Y to enable
- 	  this driver.
- 
-+config BACKLIGHT_RPI
-+	tristate "Raspberry Pi display firmware driven backlight"
-+	help
-+	  If you have the Raspberry Pi DSI touchscreen display, say Y to
-+	  enable the mailbox-controlled backlight driver.
-+
- config BACKLIGHT_DA903X
- 	tristate "Backlight Driver for DA9030/DA9034 using WLED"
- 	depends on PMIC_DA903X
---- a/drivers/video/backlight/Makefile
-+++ b/drivers/video/backlight/Makefile
-@@ -51,6 +51,7 @@ obj-$(CONFIG_BACKLIGHT_PANDORA)		+= pand
- obj-$(CONFIG_BACKLIGHT_PCF50633)	+= pcf50633-backlight.o
- obj-$(CONFIG_BACKLIGHT_PM8941_WLED)	+= pm8941-wled.o
- obj-$(CONFIG_BACKLIGHT_PWM)		+= pwm_bl.o
-+obj-$(CONFIG_BACKLIGHT_RPI)			+= rpi_backlight.o
- obj-$(CONFIG_BACKLIGHT_SAHARA)		+= kb3886_bl.o
- obj-$(CONFIG_BACKLIGHT_SKY81452)	+= sky81452-backlight.o
- obj-$(CONFIG_BACKLIGHT_TOSA)		+= tosa_bl.o
---- /dev/null
-+++ b/drivers/video/backlight/rpi_backlight.c
-@@ -0,0 +1,119 @@
-+/*
-+ * rpi_bl.c - Backlight controller through VPU
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/backlight.h>
-+#include <linux/err.h>
-+#include <linux/fb.h>
-+#include <linux/gpio.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_gpio.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+struct rpi_backlight {
-+	struct device *dev;
-+	struct device *fbdev;
-+	struct rpi_firmware *fw;
-+};
-+
-+static int rpi_backlight_update_status(struct backlight_device *bl)
-+{
-+	struct rpi_backlight *gbl = bl_get_data(bl);
-+	int brightness = bl->props.brightness;
-+	int ret;
-+
-+	if (bl->props.power != FB_BLANK_UNBLANK ||
-+	    bl->props.fb_blank != FB_BLANK_UNBLANK ||
-+	    bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
-+		brightness = 0;
-+
-+	ret = rpi_firmware_property(gbl->fw,
-+			RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT,
-+			&brightness, sizeof(brightness));
-+	if (ret) {
-+		dev_err(gbl->dev, "Failed to set brightness\n");
-+		return ret;
-+	}
-+
-+	if (brightness < 0) {
-+		dev_err(gbl->dev, "Backlight change failed\n");
-+		return -EAGAIN;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct backlight_ops rpi_backlight_ops = {
-+	.options	= BL_CORE_SUSPENDRESUME,
-+	.update_status	= rpi_backlight_update_status,
-+};
-+
-+static int rpi_backlight_probe(struct platform_device *pdev)
-+{
-+	struct backlight_properties props;
-+	struct backlight_device *bl;
-+	struct rpi_backlight *gbl;
-+	struct device_node *fw_node;
-+
-+	gbl = devm_kzalloc(&pdev->dev, sizeof(*gbl), GFP_KERNEL);
-+	if (gbl == NULL)
-+		return -ENOMEM;
-+
-+	gbl->dev = &pdev->dev;
-+
-+	fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0);
-+	if (!fw_node) {
-+		dev_err(&pdev->dev, "Missing firmware node\n");
-+		return -ENOENT;
-+	}
-+
-+	gbl->fw = rpi_firmware_get(fw_node);
-+	if (!gbl->fw)
-+		return -EPROBE_DEFER;
-+
-+	memset(&props, 0, sizeof(props));
-+	props.type = BACKLIGHT_RAW;
-+	props.max_brightness = 255;
-+	bl = devm_backlight_device_register(&pdev->dev, dev_name(&pdev->dev),
-+					&pdev->dev, gbl, &rpi_backlight_ops,
-+					&props);
-+	if (IS_ERR(bl)) {
-+		dev_err(&pdev->dev, "failed to register backlight\n");
-+		return PTR_ERR(bl);
-+	}
-+
-+	bl->props.brightness = 255;
-+	backlight_update_status(bl);
-+
-+	platform_set_drvdata(pdev, bl);
-+	return 0;
-+}
-+
-+static const struct of_device_id rpi_backlight_of_match[] = {
-+	{ .compatible = "raspberrypi,rpi-backlight" },
-+	{ /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, rpi_backlight_of_match);
-+
-+static struct platform_driver rpi_backlight_driver = {
-+	.driver		= {
-+		.name		= "rpi-backlight",
-+		.of_match_table = of_match_ptr(rpi_backlight_of_match),
-+	},
-+	.probe		= rpi_backlight_probe,
-+};
-+
-+module_platform_driver(rpi_backlight_driver);
-+
-+MODULE_AUTHOR("Gordon Hollingworth <gordon@raspberrypi.org>");
-+MODULE_DESCRIPTION("Raspberry Pi mailbox based Backlight Driver");
-+MODULE_LICENSE("GPL");
diff --git a/target/linux/brcm2708/patches-4.14/950-0090-bcm2835-virtgpio-Virtual-GPIO-driver.patch b/target/linux/brcm2708/patches-4.14/950-0090-bcm2835-virtgpio-Virtual-GPIO-driver.patch
deleted file mode 100644
index 8b200eb72..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0090-bcm2835-virtgpio-Virtual-GPIO-driver.patch
+++ /dev/null
@@ -1,256 +0,0 @@
-From 4d08e9c723d8fcd0d86e1d779b0e720cab95383a Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Tue, 23 Feb 2016 19:56:04 +0000
-Subject: [PATCH 090/454] bcm2835-virtgpio: Virtual GPIO driver
-
-Add a virtual GPIO driver that uses the firmware mailbox interface to
-request that the VPU toggles LEDs.
----
- drivers/gpio/Kconfig         |   6 +
- drivers/gpio/Makefile        |   1 +
- drivers/gpio/gpio-bcm-virt.c | 214 +++++++++++++++++++++++++++++++++++
- 3 files changed, 221 insertions(+)
- create mode 100644 drivers/gpio/gpio-bcm-virt.c
-
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -134,6 +134,12 @@ config GPIO_BCM_KONA
- 	help
- 	  Turn on GPIO support for Broadcom "Kona" chips.
- 
-+config GPIO_BCM_VIRT
-+	bool "Broadcom Virt GPIO"
-+	depends on OF_GPIO && RASPBERRYPI_FIRMWARE && (ARCH_BCM2835 || COMPILE_TEST)
-+	help
-+	  Turn on virtual GPIO support for Broadcom BCM283X chips.
-+
- config GPIO_BRCMSTB
- 	tristate "BRCMSTB GPIO support"
- 	default y if (ARCH_BRCMSTB || BMIPS_GENERIC)
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -35,6 +35,7 @@ obj-$(CONFIG_GPIO_ASPEED)	+= gpio-aspeed
- obj-$(CONFIG_GPIO_AXP209)	+= gpio-axp209.o
- obj-$(CONFIG_GPIO_BCM_KONA)	+= gpio-bcm-kona.o
- obj-$(CONFIG_GPIO_BD9571MWV)	+= gpio-bd9571mwv.o
-+obj-$(CONFIG_GPIO_BCM_VIRT)	+= gpio-bcm-virt.o
- obj-$(CONFIG_GPIO_BRCMSTB)	+= gpio-brcmstb.o
- obj-$(CONFIG_GPIO_BT8XX)	+= gpio-bt8xx.o
- obj-$(CONFIG_GPIO_CLPS711X)	+= gpio-clps711x.o
---- /dev/null
-+++ b/drivers/gpio/gpio-bcm-virt.c
-@@ -0,0 +1,214 @@
-+/*
-+ *  brcmvirt GPIO driver
-+ *
-+ *  Copyright (C) 2012,2013 Dom Cobley <popcornmix@gmail.com>
-+ *  Based on gpio-clps711x.c by Alexander Shiyan <shc_work@mail.ru>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/gpio.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+#define MODULE_NAME "brcmvirt-gpio"
-+#define NUM_GPIO 2
-+
-+struct brcmvirt_gpio {
-+	struct gpio_chip	gc;
-+	u32 __iomem		*ts_base;
-+	/* two packed 16-bit counts of enabled and disables
-+           Allows host to detect a brief enable that was missed */
-+	u32			enables_disables[NUM_GPIO];
-+	dma_addr_t		bus_addr;
-+};
-+
-+static int brcmvirt_gpio_dir_in(struct gpio_chip *gc, unsigned off)
-+{
-+	struct brcmvirt_gpio *gpio;
-+	gpio = container_of(gc, struct brcmvirt_gpio, gc);
-+	return -EINVAL;
-+}
-+
-+static int brcmvirt_gpio_dir_out(struct gpio_chip *gc, unsigned off, int val)
-+{
-+	struct brcmvirt_gpio *gpio;
-+	gpio = container_of(gc, struct brcmvirt_gpio, gc);
-+	return 0;
-+}
-+
-+static int brcmvirt_gpio_get(struct gpio_chip *gc, unsigned off)
-+{
-+	struct brcmvirt_gpio *gpio;
-+	unsigned v;
-+	gpio = container_of(gc, struct brcmvirt_gpio, gc);
-+	v = readl(gpio->ts_base + off);
-+	return (v >> off) & 1;
-+}
-+
-+static void brcmvirt_gpio_set(struct gpio_chip *gc, unsigned off, int val)
-+{
-+	struct brcmvirt_gpio *gpio;
-+	u16 enables, disables;
-+	s16 diff;
-+	bool lit;
-+	gpio = container_of(gc, struct brcmvirt_gpio, gc);
-+	enables  = gpio->enables_disables[off] >> 16;
-+	disables = gpio->enables_disables[off] >>  0;
-+	diff = (s16)(enables - disables);
-+	lit = diff > 0;
-+	if ((val && lit) || (!val && !lit))
-+		return;
-+	if (val)
-+		enables++;
-+	else
-+		disables++;
-+	diff = (s16)(enables - disables);
-+	BUG_ON(diff != 0 && diff != 1);
-+	gpio->enables_disables[off] = (enables << 16) | (disables << 0);
-+	writel(gpio->enables_disables[off], gpio->ts_base + off);
-+}
-+
-+static int brcmvirt_gpio_probe(struct platform_device *pdev)
-+{
-+	int err = 0;
-+	struct device *dev = &pdev->dev;
-+	struct device_node *np = dev->of_node;
-+	struct device_node *fw_node;
-+	struct rpi_firmware *fw;
-+	struct brcmvirt_gpio *ucb;
-+	u32 gpiovirtbuf;
-+
-+	fw_node = of_parse_phandle(np, "firmware", 0);
-+	if (!fw_node) {
-+		dev_err(dev, "Missing firmware node\n");
-+		return -ENOENT;
-+	}
-+
-+	fw = rpi_firmware_get(fw_node);
-+	if (!fw)
-+		return -EPROBE_DEFER;
-+
-+	ucb = devm_kzalloc(dev, sizeof *ucb, GFP_KERNEL);
-+	if (!ucb) {
-+		err = -EINVAL;
-+		goto out;
-+	}
-+
-+	ucb->ts_base = dma_zalloc_coherent(dev, PAGE_SIZE, &ucb->bus_addr, GFP_KERNEL);
-+	if (!ucb->ts_base) {
-+		pr_err("[%s]: failed to dma_alloc_coherent(%ld)\n",
-+				__func__, PAGE_SIZE);
-+		err = -ENOMEM;
-+		goto out;
-+	}
-+
-+	gpiovirtbuf = (u32)ucb->bus_addr;
-+	err = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF,
-+				    &gpiovirtbuf, sizeof(gpiovirtbuf));
-+
-+	if (err || gpiovirtbuf != 0) {
-+		dev_warn(dev, "Failed to set gpiovirtbuf, trying to get err:%x\n", err);
-+		dma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr);
-+		ucb->ts_base = 0;
-+		ucb->bus_addr = 0;
-+	}
-+
-+	if (!ucb->ts_base) {
-+		err = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF,
-+					    &gpiovirtbuf, sizeof(gpiovirtbuf));
-+
-+		if (err) {
-+			dev_err(dev, "Failed to get gpiovirtbuf\n");
-+			goto out;
-+		}
-+
-+		if (!gpiovirtbuf) {
-+			dev_err(dev, "No virtgpio buffer\n");
-+			err = -ENOENT;
-+			goto out;
-+		}
-+
-+		// mmap the physical memory
-+		gpiovirtbuf &= ~0xc0000000;
-+		ucb->ts_base = ioremap(gpiovirtbuf, 4096);
-+		if (ucb->ts_base == NULL) {
-+			dev_err(dev, "Failed to map physical address\n");
-+			err = -ENOENT;
-+			goto out;
-+		}
-+		ucb->bus_addr = 0;
-+	}
-+	ucb->gc.label = MODULE_NAME;
-+	ucb->gc.owner = THIS_MODULE;
-+	//ucb->gc.dev = dev;
-+	ucb->gc.of_node = np;
-+	ucb->gc.base = 100;
-+	ucb->gc.ngpio = NUM_GPIO;
-+
-+	ucb->gc.direction_input = brcmvirt_gpio_dir_in;
-+	ucb->gc.direction_output = brcmvirt_gpio_dir_out;
-+	ucb->gc.get = brcmvirt_gpio_get;
-+	ucb->gc.set = brcmvirt_gpio_set;
-+	ucb->gc.can_sleep = true;
-+
-+	err = gpiochip_add(&ucb->gc);
-+	if (err)
-+		goto out;
-+
-+	platform_set_drvdata(pdev, ucb);
-+
-+	return 0;
-+out:
-+	if (ucb->bus_addr) {
-+		dma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr);
-+		ucb->bus_addr = 0;
-+		ucb->ts_base = NULL;
-+	} else if (ucb->ts_base) {
-+		iounmap(ucb->ts_base);
-+		ucb->ts_base = NULL;
-+	}
-+	return err;
-+}
-+
-+static int brcmvirt_gpio_remove(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	int err = 0;
-+	struct brcmvirt_gpio *ucb = platform_get_drvdata(pdev);
-+
-+	gpiochip_remove(&ucb->gc);
-+	if (ucb->bus_addr)
-+		dma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr);
-+	else if (ucb->ts_base)
-+		iounmap(ucb->ts_base);
-+	return err;
-+}
-+
-+static const struct of_device_id __maybe_unused brcmvirt_gpio_ids[] = {
-+	{ .compatible = "brcm,bcm2835-virtgpio" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, brcmvirt_gpio_ids);
-+
-+static struct platform_driver brcmvirt_gpio_driver = {
-+	.driver	= {
-+		.name		= MODULE_NAME,
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= of_match_ptr(brcmvirt_gpio_ids),
-+	},
-+	.probe	= brcmvirt_gpio_probe,
-+	.remove	= brcmvirt_gpio_remove,
-+};
-+module_platform_driver(brcmvirt_gpio_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Dom Cobley <popcornmix@gmail.com>");
-+MODULE_DESCRIPTION("brcmvirt GPIO driver");
-+MODULE_ALIAS("platform:brcmvirt-gpio");
diff --git a/target/linux/brcm2708/patches-4.14/950-0091-bcm2835-gpio-exp-Driver-for-GPIO-expander-via-mailbo.patch b/target/linux/brcm2708/patches-4.14/950-0091-bcm2835-gpio-exp-Driver-for-GPIO-expander-via-mailbo.patch
deleted file mode 100644
index 1a58fd261..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0091-bcm2835-gpio-exp-Driver-for-GPIO-expander-via-mailbo.patch
+++ /dev/null
@@ -1,304 +0,0 @@
-From 74e1aacb52fcaf5d07b5d765dca1287e4234f34d Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 20 Feb 2017 17:01:21 +0000
-Subject: [PATCH 091/454] bcm2835-gpio-exp: Driver for GPIO expander via
- mailbox service
-
-Pi3 and Compute Module 3 have a GPIO expander that the
-VPU communicates with.
-There is a mailbox service that now allows control of this
-expander, so add a kernel driver that can make use of it.
-
-Pwr_led node added to device-tree for Pi3.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/gpio/Kconfig        |   7 +
- drivers/gpio/Makefile       |   1 +
- drivers/gpio/gpio-bcm-exp.c | 254 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 262 insertions(+)
- create mode 100644 drivers/gpio/gpio-bcm-exp.c
-
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -128,6 +128,13 @@ config GPIO_AXP209
- 	help
- 	  Say yes to enable GPIO support for the AXP209 PMIC
- 
-+config GPIO_BCM_EXP
-+	bool "Broadcom Exp GPIO"
-+	depends on OF_GPIO && RASPBERRYPI_FIRMWARE && (ARCH_BCM2835 || COMPILE_TEST)
-+	help
-+	  Turn on GPIO support for Broadcom chips using the firmware mailbox
-+	  to communicate with VideoCore on BCM283x chips.
-+
- config GPIO_BCM_KONA
- 	bool "Broadcom Kona GPIO"
- 	depends on OF_GPIO && (ARCH_BCM_MOBILE || COMPILE_TEST)
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizo
- obj-$(CONFIG_GPIO_ATH79)	+= gpio-ath79.o
- obj-$(CONFIG_GPIO_ASPEED)	+= gpio-aspeed.o
- obj-$(CONFIG_GPIO_AXP209)	+= gpio-axp209.o
-+obj-$(CONFIG_GPIO_BCM_EXP)	+= gpio-bcm-exp.o
- obj-$(CONFIG_GPIO_BCM_KONA)	+= gpio-bcm-kona.o
- obj-$(CONFIG_GPIO_BD9571MWV)	+= gpio-bd9571mwv.o
- obj-$(CONFIG_GPIO_BCM_VIRT)	+= gpio-bcm-virt.o
---- /dev/null
-+++ b/drivers/gpio/gpio-bcm-exp.c
-@@ -0,0 +1,254 @@
-+/*
-+ *  Broadcom expander GPIO driver
-+ *
-+ *  Uses the firmware mailbox service to communicate with the
-+ *  GPIO expander on the VPU.
-+ *
-+ *  Copyright (C) 2017 Raspberry Pi Trading Ltd.
-+ *
-+ *  Author: Dave Stevenson <dave.stevenson@raspberrypi.org>
-+ *  Based on gpio-bcm-virt.c by Dom Cobley <popcornmix@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/gpio.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+#define MODULE_NAME "brcmexp-gpio"
-+#define NUM_GPIO 8
-+
-+struct brcmexp_gpio {
-+	struct gpio_chip gc;
-+	struct device *dev;
-+	struct rpi_firmware *fw;
-+};
-+
-+struct gpio_set_config {
-+	u32 gpio, direction, polarity, term_en, term_pull_up, state;
-+};
-+
-+struct gpio_get_config {
-+	u32 gpio, direction, polarity, term_en, term_pull_up;
-+};
-+
-+struct gpio_get_set_state {
-+	u32 gpio, state;
-+};
-+
-+static int brcmexp_gpio_get_polarity(struct gpio_chip *gc, unsigned int off)
-+{
-+	struct brcmexp_gpio *gpio;
-+	struct gpio_get_config get;
-+	int ret;
-+
-+	gpio = container_of(gc, struct brcmexp_gpio, gc);
-+
-+	get.gpio = off + gpio->gc.base;	/* GPIO to update */
-+
-+	ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_GET_GPIO_CONFIG,
-+				    &get, sizeof(get));
-+	if (ret) {
-+		dev_err(gpio->dev,
-+			"Failed to get GPIO %u config (%d)\n", off, ret);
-+		return ret;
-+	}
-+	return get.polarity;
-+}
-+
-+static int brcmexp_gpio_dir_in(struct gpio_chip *gc, unsigned int off)
-+{
-+	struct brcmexp_gpio *gpio;
-+	struct gpio_set_config set_in;
-+	int ret;
-+
-+	gpio = container_of(gc, struct brcmexp_gpio, gc);
-+
-+	set_in.gpio = off + gpio->gc.base;	/* GPIO to update */
-+	set_in.direction = 0;		/* Input */
-+	set_in.polarity = brcmexp_gpio_get_polarity(gc, off);
-+					/* Retain existing setting */
-+	set_in.term_en = 0;		/* termination disabled */
-+	set_in.term_pull_up = 0;	/* n/a as termination disabled */
-+	set_in.state = 0;		/* n/a as configured as an input */
-+
-+	ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_SET_GPIO_CONFIG,
-+				    &set_in, sizeof(set_in));
-+	if (ret) {
-+		dev_err(gpio->dev,
-+			"Failed to set GPIO %u to input (%d)\n",
-+			off, ret);
-+		return ret;
-+	}
-+	return 0;
-+}
-+
-+static int brcmexp_gpio_dir_out(struct gpio_chip *gc, unsigned int off, int val)
-+{
-+	struct brcmexp_gpio *gpio;
-+	struct gpio_set_config set_out;
-+	int ret;
-+
-+	gpio = container_of(gc, struct brcmexp_gpio, gc);
-+
-+	set_out.gpio = off + gpio->gc.base;	/* GPIO to update */
-+	set_out.direction = 1;		/* Output */
-+	set_out.polarity = brcmexp_gpio_get_polarity(gc, off);
-+					/* Retain existing setting */
-+	set_out.term_en = 0;		/* n/a as an output */
-+	set_out.term_pull_up = 0;	/* n/a as termination disabled */
-+	set_out.state = val;		/* Output state */
-+
-+	ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_SET_GPIO_CONFIG,
-+				    &set_out, sizeof(set_out));
-+	if (ret) {
-+		dev_err(gpio->dev,
-+			"Failed to set GPIO %u to output (%d)\n", off, ret);
-+		return ret;
-+	}
-+	return 0;
-+}
-+
-+static int brcmexp_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
-+{
-+	struct brcmexp_gpio *gpio;
-+	struct gpio_get_config get;
-+	int ret;
-+
-+	gpio = container_of(gc, struct brcmexp_gpio, gc);
-+
-+	get.gpio = off + gpio->gc.base;	/* GPIO to update */
-+
-+	ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_GET_GPIO_CONFIG,
-+				    &get, sizeof(get));
-+	if (ret) {
-+		dev_err(gpio->dev,
-+			"Failed to get GPIO %u config (%d)\n", off, ret);
-+		return ret;
-+	}
-+	return get.direction ? GPIOF_DIR_OUT : GPIOF_DIR_IN;
-+}
-+
-+static int brcmexp_gpio_get(struct gpio_chip *gc, unsigned int off)
-+{
-+	struct brcmexp_gpio *gpio;
-+	struct gpio_get_set_state get;
-+	int ret;
-+
-+	gpio = container_of(gc, struct brcmexp_gpio, gc);
-+
-+	get.gpio = off + gpio->gc.base;	/* GPIO to update */
-+	get.state = 0;		/* storage for returned value */
-+
-+	ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_GET_GPIO_STATE,
-+					 &get, sizeof(get));
-+	if (ret) {
-+		dev_err(gpio->dev,
-+			"Failed to get GPIO %u state (%d)\n", off, ret);
-+		return ret;
-+	}
-+	return !!get.state;
-+}
-+
-+static void brcmexp_gpio_set(struct gpio_chip *gc, unsigned int off, int val)
-+{
-+	struct brcmexp_gpio *gpio;
-+	struct gpio_get_set_state set;
-+	int ret;
-+
-+	gpio = container_of(gc, struct brcmexp_gpio, gc);
-+
-+	set.gpio = off + gpio->gc.base;	/* GPIO to update */
-+	set.state = val;	/* Output state */
-+
-+	ret = rpi_firmware_property(gpio->fw, RPI_FIRMWARE_SET_GPIO_STATE,
-+					 &set, sizeof(set));
-+	if (ret)
-+		dev_err(gpio->dev,
-+			"Failed to set GPIO %u state (%d)\n", off, ret);
-+}
-+
-+static int brcmexp_gpio_probe(struct platform_device *pdev)
-+{
-+	int err = 0;
-+	struct device *dev = &pdev->dev;
-+	struct device_node *np = dev->of_node;
-+	struct device_node *fw_node;
-+	struct rpi_firmware *fw;
-+	struct brcmexp_gpio *ucb;
-+
-+	fw_node = of_parse_phandle(np, "firmware", 0);
-+	if (!fw_node) {
-+		dev_err(dev, "Missing firmware node\n");
-+		return -ENOENT;
-+	}
-+
-+	fw = rpi_firmware_get(fw_node);
-+	if (!fw)
-+		return -EPROBE_DEFER;
-+
-+	ucb = devm_kzalloc(dev, sizeof(*ucb), GFP_KERNEL);
-+	if (!ucb)
-+		return -EINVAL;
-+
-+	ucb->fw = fw;
-+	ucb->dev = dev;
-+	ucb->gc.label = MODULE_NAME;
-+	ucb->gc.owner = THIS_MODULE;
-+	ucb->gc.of_node = np;
-+	ucb->gc.base = 128;
-+	ucb->gc.ngpio = NUM_GPIO;
-+
-+	ucb->gc.direction_input = brcmexp_gpio_dir_in;
-+	ucb->gc.direction_output = brcmexp_gpio_dir_out;
-+	ucb->gc.get_direction = brcmexp_gpio_get_direction;
-+	ucb->gc.get = brcmexp_gpio_get;
-+	ucb->gc.set = brcmexp_gpio_set;
-+	ucb->gc.can_sleep = true;
-+
-+	err = gpiochip_add(&ucb->gc);
-+	if (err)
-+		return err;
-+
-+	platform_set_drvdata(pdev, ucb);
-+
-+	return 0;
-+}
-+
-+static int brcmexp_gpio_remove(struct platform_device *pdev)
-+{
-+	struct brcmexp_gpio *ucb = platform_get_drvdata(pdev);
-+
-+	gpiochip_remove(&ucb->gc);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id __maybe_unused brcmexp_gpio_ids[] = {
-+	{ .compatible = "brcm,bcm2835-expgpio" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, brcmexp_gpio_ids);
-+
-+static struct platform_driver brcmexp_gpio_driver = {
-+	.driver	= {
-+		.name		= MODULE_NAME,
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= of_match_ptr(brcmexp_gpio_ids),
-+	},
-+	.probe	= brcmexp_gpio_probe,
-+	.remove	= brcmexp_gpio_remove,
-+};
-+module_platform_driver(brcmexp_gpio_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.org>");
-+MODULE_DESCRIPTION("brcm-exp GPIO driver");
-+MODULE_ALIAS("platform:brcmexp-gpio");
diff --git a/target/linux/brcm2708/patches-4.14/950-0092-amba_pl011-Don-t-use-DT-aliases-for-numbering.patch b/target/linux/brcm2708/patches-4.14/950-0092-amba_pl011-Don-t-use-DT-aliases-for-numbering.patch
deleted file mode 100644
index 0ebe5616b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0092-amba_pl011-Don-t-use-DT-aliases-for-numbering.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 1cf3028d3fd5f374cf75e6487898197c3db230ad Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 23 Feb 2016 17:26:48 +0000
-Subject: [PATCH 092/454] amba_pl011: Don't use DT aliases for numbering
-
-The pl011 driver looks for DT aliases of the form "serial<n>",
-and if found uses <n> as the device ID. This can cause
-/dev/ttyAMA0 to become /dev/ttyAMA1, which is confusing if the
-other serial port is provided by the 8250 driver which doesn't
-use the same logic.
----
- drivers/tty/serial/amba-pl011.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/tty/serial/amba-pl011.c
-+++ b/drivers/tty/serial/amba-pl011.c
-@@ -2598,7 +2598,12 @@ static int pl011_setup_port(struct devic
- 	if (IS_ERR(base))
- 		return PTR_ERR(base);
- 
-+	/* Don't use DT serial<n> aliases - it causes the device to
-+	   be renumbered to ttyAMA1 if it is the second serial port in the
-+	   system, even though the other one is ttyS0. The 8250 driver
-+	   doesn't use this logic, so always remains ttyS0.
- 	index = pl011_probe_dt_alias(index, dev);
-+	*/
- 
- 	uap->old_cr = 0;
- 	uap->port.dev = dev;
diff --git a/target/linux/brcm2708/patches-4.14/950-0093-amba_pl011-Round-input-clock-up.patch b/target/linux/brcm2708/patches-4.14/950-0093-amba_pl011-Round-input-clock-up.patch
deleted file mode 100644
index 90afc6f87..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0093-amba_pl011-Round-input-clock-up.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From d25a404a959a57804908c1d615b2ac85d7c4a18e Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 1 Mar 2017 16:07:39 +0000
-Subject: [PATCH 093/454] amba_pl011: Round input clock up
-
-The UART clock is initialised to be as close to the requested
-frequency as possible without exceeding it. Now that there is a
-clock manager that returns the actual frequencies, an expected
-48MHz clock is reported as 47999625. If the requested baudrate
-== requested clock/16, there is no headroom and the slight
-reduction in actual clock rate results in failure.
-
-Detect cases where it looks like a "round" clock was chosen and
-adjust the reported clock to match that "round" value. As the
-code comment says:
-
-/*
- * If increasing a clock by less than 0.1% changes it
- * from ..999.. to ..000.., round up.
- */
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/tty/serial/amba-pl011.c | 23 +++++++++++++++++++++--
- 1 file changed, 21 insertions(+), 2 deletions(-)
-
---- a/drivers/tty/serial/amba-pl011.c
-+++ b/drivers/tty/serial/amba-pl011.c
-@@ -1672,6 +1672,23 @@ static void pl011_put_poll_char(struct u
- 
- #endif /* CONFIG_CONSOLE_POLL */
- 
-+unsigned long pl011_clk_round(unsigned long clk)
-+{
-+	unsigned long scaler;
-+
-+	/*
-+	 * If increasing a clock by less than 0.1% changes it
-+	 * from ..999.. to ..000.., round up.
-+	 */
-+	scaler = 1;
-+	while (scaler * 100000 < clk)
-+		scaler *= 10;
-+	if ((clk + scaler - 1)/scaler % 1000 == 0)
-+		clk = (clk/scaler + 1) * scaler;
-+
-+	return clk;
-+}
-+
- static int pl011_hwinit(struct uart_port *port)
- {
- 	struct uart_amba_port *uap =
-@@ -1688,7 +1705,7 @@ static int pl011_hwinit(struct uart_port
- 	if (retval)
- 		return retval;
- 
--	uap->port.uartclk = clk_get_rate(uap->clk);
-+	uap->port.uartclk = pl011_clk_round(clk_get_rate(uap->clk));
- 
- 	/* Clear pending error and receive interrupts */
- 	pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
-@@ -2344,7 +2361,7 @@ static int __init pl011_console_setup(st
- 			plat->init();
- 	}
- 
--	uap->port.uartclk = clk_get_rate(uap->clk);
-+	uap->port.uartclk = pl011_clk_round(clk_get_rate(uap->clk));
- 
- 	if (uap->vendor->fixed_options) {
- 		baud = uap->fixed_baud;
-@@ -2529,6 +2546,7 @@ static struct uart_driver amba_reg = {
- 	.cons			= AMBA_CONSOLE,
- };
- 
-+#if 0
- static int pl011_probe_dt_alias(int index, struct device *dev)
- {
- 	struct device_node *np;
-@@ -2560,6 +2578,7 @@ static int pl011_probe_dt_alias(int inde
- 
- 	return ret;
- }
-+#endif
- 
- /* unregisters the driver also if no more ports are left */
- static void pl011_unregister_port(struct uart_amba_port *uap)
diff --git a/target/linux/brcm2708/patches-4.14/950-0094-OF-DT-Overlay-configfs-interface.patch b/target/linux/brcm2708/patches-4.14/950-0094-OF-DT-Overlay-configfs-interface.patch
deleted file mode 100644
index 164b4565b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0094-OF-DT-Overlay-configfs-interface.patch
+++ /dev/null
@@ -1,425 +0,0 @@
-From b12afa082622333816203f0fd2e93051de65de09 Mon Sep 17 00:00:00 2001
-From: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
-Date: Wed, 3 Dec 2014 13:23:28 +0200
-Subject: [PATCH 094/454] OF: DT-Overlay configfs interface
-
-This is a port of Pantelis Antoniou's v3 port that makes use of the
-new upstreamed configfs support for binary attributes.
-
-Original commit message:
-
-Add a runtime interface to using configfs for generic device tree overlay
-usage. With it its possible to use device tree overlays without having
-to use a per-platform overlay manager.
-
-Please see Documentation/devicetree/configfs-overlays.txt for more info.
-
-Changes since v2:
-- Removed ifdef CONFIG_OF_OVERLAY (since for now it's required)
-- Created a documentation entry
-- Slight rewording in Kconfig
-
-Changes since v1:
-- of_resolve() -> of_resolve_phandles().
-
-Originally-signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-DT configfs: Fix build errors on other platforms
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-
-DT configfs: fix build error
-
-There is an error when compiling rpi-4.6.y branch:
-  CC      drivers/of/configfs.o
-drivers/of/configfs.c:291:21: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
-   .default_groups = of_cfs_def_groups,
-                     ^
-drivers/of/configfs.c:291:21: note: (near initialization for 'of_cfs_subsys.su_group.default_groups.next')
-
-The .default_groups is linked list since commit
-1ae1602de028acaa42a0f6ff18d19756f8e825c6.
-This commit uses configfs_add_default_group to fix this problem.
-
-Signed-off-by: Slawomir Stepien <sst@poczta.fm>
----
- .../devicetree/configfs-overlays.txt          |  31 ++
- drivers/of/Kconfig                            |   7 +
- drivers/of/Makefile                           |   1 +
- drivers/of/configfs.c                         | 311 ++++++++++++++++++
- 4 files changed, 350 insertions(+)
- create mode 100644 Documentation/devicetree/configfs-overlays.txt
- create mode 100644 drivers/of/configfs.c
-
---- /dev/null
-+++ b/Documentation/devicetree/configfs-overlays.txt
-@@ -0,0 +1,31 @@
-+Howto use the configfs overlay interface.
-+
-+A device-tree configfs entry is created in /config/device-tree/overlays
-+and and it is manipulated using standard file system I/O.
-+Note that this is a debug level interface, for use by developers and
-+not necessarily something accessed by normal users due to the
-+security implications of having direct access to the kernel's device tree.
-+
-+* To create an overlay you mkdir the directory:
-+
-+	# mkdir /config/device-tree/overlays/foo
-+
-+* Either you echo the overlay firmware file to the path property file.
-+
-+	# echo foo.dtbo >/config/device-tree/overlays/foo/path
-+
-+* Or you cat the contents of the overlay to the dtbo file
-+
-+	# cat foo.dtbo >/config/device-tree/overlays/foo/dtbo
-+
-+The overlay file will be applied, and devices will be created/destroyed
-+as required.
-+
-+To remove it simply rmdir the directory.
-+
-+	# rmdir /config/device-tree/overlays/foo
-+
-+The rationalle of the dual interface (firmware & direct copy) is that each is
-+better suited to different use patterns. The firmware interface is what's
-+intended to be used by hardware managers in the kernel, while the copy interface
-+make sense for developers (since it avoids problems with namespaces).
---- a/drivers/of/Kconfig
-+++ b/drivers/of/Kconfig
-@@ -112,4 +112,11 @@ config OF_OVERLAY
- config OF_NUMA
- 	bool
- 
-+config OF_CONFIGFS
-+	bool "Device Tree Overlay ConfigFS interface"
-+	select CONFIGFS_FS
-+	select OF_OVERLAY
-+	help
-+	  Enable a simple user-space driven DT overlay interface.
-+
- endif # OF
---- a/drivers/of/Makefile
-+++ b/drivers/of/Makefile
-@@ -1,5 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
- obj-y = base.o device.o platform.o property.o
-+obj-$(CONFIG_OF_CONFIGFS) += configfs.o
- obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
- obj-$(CONFIG_OF_FLATTREE) += fdt.o
- obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o
---- /dev/null
-+++ b/drivers/of/configfs.c
-@@ -0,0 +1,311 @@
-+/*
-+ * Configfs entries for device-tree
-+ *
-+ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ */
-+#include <linux/ctype.h>
-+#include <linux/cpu.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_fdt.h>
-+#include <linux/spinlock.h>
-+#include <linux/slab.h>
-+#include <linux/proc_fs.h>
-+#include <linux/configfs.h>
-+#include <linux/types.h>
-+#include <linux/stat.h>
-+#include <linux/limits.h>
-+#include <linux/file.h>
-+#include <linux/vmalloc.h>
-+#include <linux/firmware.h>
-+#include <linux/sizes.h>
-+
-+#include "of_private.h"
-+
-+struct cfs_overlay_item {
-+	struct config_item	item;
-+
-+	char			path[PATH_MAX];
-+
-+	const struct firmware	*fw;
-+	struct device_node	*overlay;
-+	int			ov_id;
-+
-+	void			*dtbo;
-+	int			dtbo_size;
-+};
-+
-+static int create_overlay(struct cfs_overlay_item *overlay, void *blob)
-+{
-+	int err;
-+
-+	/* unflatten the tree */
-+	of_fdt_unflatten_tree(blob, NULL, &overlay->overlay);
-+	if (overlay->overlay == NULL) {
-+		pr_err("%s: failed to unflatten tree\n", __func__);
-+		err = -EINVAL;
-+		goto out_err;
-+	}
-+	pr_debug("%s: unflattened OK\n", __func__);
-+
-+	/* mark it as detached */
-+	of_node_set_flag(overlay->overlay, OF_DETACHED);
-+
-+	/* perform resolution */
-+	err = of_resolve_phandles(overlay->overlay);
-+	if (err != 0) {
-+		pr_err("%s: Failed to resolve tree\n", __func__);
-+		goto out_err;
-+	}
-+	pr_debug("%s: resolved OK\n", __func__);
-+
-+	err = of_overlay_create(overlay->overlay);
-+	if (err < 0) {
-+		pr_err("%s: Failed to create overlay (err=%d)\n",
-+				__func__, err);
-+		goto out_err;
-+	}
-+	overlay->ov_id = err;
-+
-+out_err:
-+	return err;
-+}
-+
-+static inline struct cfs_overlay_item *to_cfs_overlay_item(
-+		struct config_item *item)
-+{
-+	return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
-+}
-+
-+static ssize_t cfs_overlay_item_path_show(struct config_item *item,
-+		char *page)
-+{
-+	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
-+	return sprintf(page, "%s\n", overlay->path);
-+}
-+
-+static ssize_t cfs_overlay_item_path_store(struct config_item *item,
-+		const char *page, size_t count)
-+{
-+	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
-+	const char *p = page;
-+	char *s;
-+	int err;
-+
-+	/* if it's set do not allow changes */
-+	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
-+		return -EPERM;
-+
-+	/* copy to path buffer (and make sure it's always zero terminated */
-+	count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
-+	overlay->path[sizeof(overlay->path) - 1] = '\0';
-+
-+	/* strip trailing newlines */
-+	s = overlay->path + strlen(overlay->path);
-+	while (s > overlay->path && *--s == '\n')
-+		*s = '\0';
-+
-+	pr_debug("%s: path is '%s'\n", __func__, overlay->path);
-+
-+	err = request_firmware(&overlay->fw, overlay->path, NULL);
-+	if (err != 0)
-+		goto out_err;
-+
-+	err = create_overlay(overlay, (void *)overlay->fw->data);
-+	if (err != 0)
-+		goto out_err;
-+
-+	return count;
-+
-+out_err:
-+
-+	release_firmware(overlay->fw);
-+	overlay->fw = NULL;
-+
-+	overlay->path[0] = '\0';
-+	return err;
-+}
-+
-+static ssize_t cfs_overlay_item_status_show(struct config_item *item,
-+		char *page)
-+{
-+	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
-+
-+	return sprintf(page, "%s\n",
-+			overlay->ov_id >= 0 ? "applied" : "unapplied");
-+}
-+
-+CONFIGFS_ATTR(cfs_overlay_item_, path);
-+CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
-+
-+static struct configfs_attribute *cfs_overlay_attrs[] = {
-+	&cfs_overlay_item_attr_path,
-+	&cfs_overlay_item_attr_status,
-+	NULL,
-+};
-+
-+ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
-+		void *buf, size_t max_count)
-+{
-+	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
-+
-+	pr_debug("%s: buf=%p max_count=%zu\n", __func__,
-+			buf, max_count);
-+
-+	if (overlay->dtbo == NULL)
-+		return 0;
-+
-+	/* copy if buffer provided */
-+	if (buf != NULL) {
-+		/* the buffer must be large enough */
-+		if (overlay->dtbo_size > max_count)
-+			return -ENOSPC;
-+
-+		memcpy(buf, overlay->dtbo, overlay->dtbo_size);
-+	}
-+
-+	return overlay->dtbo_size;
-+}
-+
-+ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
-+		const void *buf, size_t count)
-+{
-+	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
-+	int err;
-+
-+	/* if it's set do not allow changes */
-+	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
-+		return -EPERM;
-+
-+	/* copy the contents */
-+	overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
-+	if (overlay->dtbo == NULL)
-+		return -ENOMEM;
-+
-+	overlay->dtbo_size = count;
-+
-+	err = create_overlay(overlay, overlay->dtbo);
-+	if (err != 0)
-+		goto out_err;
-+
-+	return count;
-+
-+out_err:
-+	kfree(overlay->dtbo);
-+	overlay->dtbo = NULL;
-+	overlay->dtbo_size = 0;
-+
-+	return err;
-+}
-+
-+CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
-+
-+static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
-+	&cfs_overlay_item_attr_dtbo,
-+	NULL,
-+};
-+
-+static void cfs_overlay_release(struct config_item *item)
-+{
-+	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
-+
-+	if (overlay->ov_id >= 0)
-+		of_overlay_destroy(overlay->ov_id);
-+	if (overlay->fw)
-+		release_firmware(overlay->fw);
-+	/* kfree with NULL is safe */
-+	kfree(overlay->dtbo);
-+	kfree(overlay);
-+}
-+
-+static struct configfs_item_operations cfs_overlay_item_ops = {
-+	.release	= cfs_overlay_release,
-+};
-+
-+static struct config_item_type cfs_overlay_type = {
-+	.ct_item_ops	= &cfs_overlay_item_ops,
-+	.ct_attrs	= cfs_overlay_attrs,
-+	.ct_bin_attrs	= cfs_overlay_bin_attrs,
-+	.ct_owner	= THIS_MODULE,
-+};
-+
-+static struct config_item *cfs_overlay_group_make_item(
-+		struct config_group *group, const char *name)
-+{
-+	struct cfs_overlay_item *overlay;
-+
-+	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
-+	if (!overlay)
-+		return ERR_PTR(-ENOMEM);
-+	overlay->ov_id = -1;
-+
-+	config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
-+	return &overlay->item;
-+}
-+
-+static void cfs_overlay_group_drop_item(struct config_group *group,
-+		struct config_item *item)
-+{
-+	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
-+
-+	config_item_put(&overlay->item);
-+}
-+
-+static struct configfs_group_operations overlays_ops = {
-+	.make_item	= cfs_overlay_group_make_item,
-+	.drop_item	= cfs_overlay_group_drop_item,
-+};
-+
-+static struct config_item_type overlays_type = {
-+	.ct_group_ops   = &overlays_ops,
-+	.ct_owner       = THIS_MODULE,
-+};
-+
-+static struct configfs_group_operations of_cfs_ops = {
-+	/* empty - we don't allow anything to be created */
-+};
-+
-+static struct config_item_type of_cfs_type = {
-+	.ct_group_ops   = &of_cfs_ops,
-+	.ct_owner       = THIS_MODULE,
-+};
-+
-+struct config_group of_cfs_overlay_group;
-+
-+static struct configfs_subsystem of_cfs_subsys = {
-+	.su_group = {
-+		.cg_item = {
-+			.ci_namebuf = "device-tree",
-+			.ci_type = &of_cfs_type,
-+		},
-+	},
-+	.su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
-+};
-+
-+static int __init of_cfs_init(void)
-+{
-+	int ret;
-+
-+	pr_info("%s\n", __func__);
-+
-+	config_group_init(&of_cfs_subsys.su_group);
-+	config_group_init_type_name(&of_cfs_overlay_group, "overlays",
-+			&overlays_type);
-+	configfs_add_default_group(&of_cfs_overlay_group,
-+			&of_cfs_subsys.su_group);
-+
-+	ret = configfs_register_subsystem(&of_cfs_subsys);
-+	if (ret != 0) {
-+		pr_err("%s: failed to register subsys\n", __func__);
-+		goto out;
-+	}
-+	pr_info("%s: OK\n", __func__);
-+out:
-+	return ret;
-+}
-+late_initcall(of_cfs_init);
diff --git a/target/linux/brcm2708/patches-4.14/950-0095-hci_h5-Don-t-send-conf_req-when-ACTIVE.patch b/target/linux/brcm2708/patches-4.14/950-0095-hci_h5-Don-t-send-conf_req-when-ACTIVE.patch
deleted file mode 100644
index 8b948d93e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0095-hci_h5-Don-t-send-conf_req-when-ACTIVE.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 115d7cec13b86bf47000bfb383086203ee980fcf Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 17 Dec 2015 13:37:07 +0000
-Subject: [PATCH 095/454] hci_h5: Don't send conf_req when ACTIVE
-
-Without this patch, a modem and kernel can continuously bombard each
-other with conf_req and conf_rsp messages, in a demented game of tag.
----
- drivers/bluetooth/hci_h5.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/bluetooth/hci_h5.c
-+++ b/drivers/bluetooth/hci_h5.c
-@@ -308,7 +308,8 @@ static void h5_handle_internal_rx(struct
- 		h5_link_control(hu, conf_req, 3);
- 	} else if (memcmp(data, conf_req, 2) == 0) {
- 		h5_link_control(hu, conf_rsp, 2);
--		h5_link_control(hu, conf_req, 3);
-+		if (h5->state != H5_ACTIVE)
-+		    h5_link_control(hu, conf_req, 3);
- 	} else if (memcmp(data, conf_rsp, 2) == 0) {
- 		if (H5_HDR_LEN(hdr) > 2)
- 			h5->tx_win = (data[2] & 0x07);
diff --git a/target/linux/brcm2708/patches-4.14/950-0096-config-Add-default-configs.patch b/target/linux/brcm2708/patches-4.14/950-0096-config-Add-default-configs.patch
deleted file mode 100644
index 18f1eac1e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0096-config-Add-default-configs.patch
+++ /dev/null
@@ -1,2701 +0,0 @@
-From efc7b64de5f58c41ee101ce8740d29bf430a9adc Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Mon, 13 Apr 2015 17:16:29 +0100
-Subject: [PATCH 096/454] config: Add default configs
-
----
- arch/arm/configs/bcm2709_defconfig | 1339 +++++++++++++++++++++++++++
- arch/arm/configs/bcmrpi_defconfig  | 1344 ++++++++++++++++++++++++++++
- 2 files changed, 2683 insertions(+)
- create mode 100644 arch/arm/configs/bcm2709_defconfig
- create mode 100644 arch/arm/configs/bcmrpi_defconfig
-
---- /dev/null
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -0,0 +1,1339 @@
-+CONFIG_LOCALVERSION="-v7"
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_GENERIC_IRQ_DEBUGFS=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+CONFIG_TASKSTATS=y
-+CONFIG_TASK_DELAY_ACCT=y
-+CONFIG_TASK_XACCT=y
-+CONFIG_TASK_IO_ACCOUNTING=y
-+CONFIG_IKCONFIG=m
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_MEMCG=y
-+CONFIG_BLK_CGROUP=y
-+CONFIG_CGROUP_FREEZER=y
-+CONFIG_CPUSETS=y
-+CONFIG_CGROUP_DEVICE=y
-+CONFIG_CGROUP_CPUACCT=y
-+CONFIG_NAMESPACES=y
-+CONFIG_USER_NS=y
-+CONFIG_SCHED_AUTOGROUP=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+CONFIG_JUMP_LABEL=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLK_DEV_THROTTLING=y
-+CONFIG_PARTITION_ADVANCED=y
-+CONFIG_MAC_PARTITION=y
-+CONFIG_CFQ_GROUP_IOSCHED=y
-+CONFIG_ARCH_BCM=y
-+CONFIG_ARCH_BCM2835=y
-+# CONFIG_CACHE_L2X0 is not set
-+CONFIG_SMP=y
-+CONFIG_VMSPLIT_2G=y
-+CONFIG_PREEMPT_VOLUNTARY=y
-+# CONFIG_CPU_SW_DOMAIN_PAN is not set
-+CONFIG_CLEANCACHE=y
-+CONFIG_FRONTSWAP=y
-+CONFIG_CMA=y
-+CONFIG_ZSMALLOC=m
-+CONFIG_PGTABLE_MAPPING=y
-+CONFIG_UACCESS_WITH_MEMCPY=y
-+CONFIG_SECCOMP=y
-+# CONFIG_ATAGS is not set
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_STAT=y
-+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-+CONFIG_VFP=y
-+CONFIG_NEON=y
-+CONFIG_KERNEL_MODE_NEON=y
-+CONFIG_BINFMT_MISC=m
-+# CONFIG_SUSPEND is not set
-+CONFIG_PM=y
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM_USER=y
-+CONFIG_NET_KEY=m
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE_DEMUX=m
-+CONFIG_NET_IPGRE=m
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IP_PIMSM_V1=y
-+CONFIG_IP_PIMSM_V2=y
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+CONFIG_INET_IPCOMP=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+CONFIG_INET_DIAG=m
-+CONFIG_TCP_CONG_ADVANCED=y
-+CONFIG_TCP_CONG_BBR=m
-+CONFIG_IPV6=m
-+CONFIG_IPV6_ROUTER_PREF=y
-+CONFIG_IPV6_ROUTE_INFO=y
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+CONFIG_IPV6_SIT_6RD=y
-+CONFIG_IPV6_TUNNEL=m
-+CONFIG_IPV6_MULTIPLE_TABLES=y
-+CONFIG_IPV6_SUBTREES=y
-+CONFIG_IPV6_MROUTE=y
-+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IPV6_PIMSM_V2=y
-+CONFIG_NETFILTER=y
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_ZONES=y
-+CONFIG_NF_CONNTRACK_EVENTS=y
-+CONFIG_NF_CONNTRACK_TIMESTAMP=y
-+CONFIG_NF_CONNTRACK_AMANDA=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_H323=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-+CONFIG_NF_CONNTRACK_SNMP=m
-+CONFIG_NF_CONNTRACK_PPTP=m
-+CONFIG_NF_CONNTRACK_SANE=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CONNTRACK_TFTP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XT_SET=m
-+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-+CONFIG_NETFILTER_XT_TARGET_DSCP=m
-+CONFIG_NETFILTER_XT_TARGET_HMARK=m
-+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-+CONFIG_NETFILTER_XT_TARGET_LED=m
-+CONFIG_NETFILTER_XT_TARGET_LOG=m
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-+CONFIG_NETFILTER_XT_TARGET_TEE=m
-+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-+CONFIG_NETFILTER_XT_TARGET_TRACE=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_BPF=m
-+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_CPU=m
-+CONFIG_NETFILTER_XT_MATCH_DCCP=m
-+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-+CONFIG_NETFILTER_XT_MATCH_DSCP=m
-+CONFIG_NETFILTER_XT_MATCH_ESP=m
-+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_HELPER=m
-+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-+CONFIG_NETFILTER_XT_MATCH_IPVS=m
-+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_MAC=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-+CONFIG_NETFILTER_XT_MATCH_OSF=m
-+CONFIG_NETFILTER_XT_MATCH_OWNER=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-+CONFIG_NETFILTER_XT_MATCH_REALM=m
-+CONFIG_NETFILTER_XT_MATCH_RECENT=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-+CONFIG_NETFILTER_XT_MATCH_STRING=m
-+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_TIME=m
-+CONFIG_NETFILTER_XT_MATCH_U32=m
-+CONFIG_IP_SET=m
-+CONFIG_IP_SET_BITMAP_IP=m
-+CONFIG_IP_SET_BITMAP_IPMAC=m
-+CONFIG_IP_SET_BITMAP_PORT=m
-+CONFIG_IP_SET_HASH_IP=m
-+CONFIG_IP_SET_HASH_IPPORT=m
-+CONFIG_IP_SET_HASH_IPPORTIP=m
-+CONFIG_IP_SET_HASH_IPPORTNET=m
-+CONFIG_IP_SET_HASH_NET=m
-+CONFIG_IP_SET_HASH_NETPORT=m
-+CONFIG_IP_SET_HASH_NETIFACE=m
-+CONFIG_IP_SET_LIST_SET=m
-+CONFIG_IP_VS=m
-+CONFIG_IP_VS_PROTO_TCP=y
-+CONFIG_IP_VS_PROTO_UDP=y
-+CONFIG_IP_VS_PROTO_ESP=y
-+CONFIG_IP_VS_PROTO_AH=y
-+CONFIG_IP_VS_PROTO_SCTP=y
-+CONFIG_IP_VS_RR=m
-+CONFIG_IP_VS_WRR=m
-+CONFIG_IP_VS_LC=m
-+CONFIG_IP_VS_WLC=m
-+CONFIG_IP_VS_LBLC=m
-+CONFIG_IP_VS_LBLCR=m
-+CONFIG_IP_VS_DH=m
-+CONFIG_IP_VS_SH=m
-+CONFIG_IP_VS_SED=m
-+CONFIG_IP_VS_NQ=m
-+CONFIG_IP_VS_FTP=m
-+CONFIG_IP_VS_PE_SIP=m
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_MATCH_AH=m
-+CONFIG_IP_NF_MATCH_ECN=m
-+CONFIG_IP_NF_MATCH_RPFILTER=m
-+CONFIG_IP_NF_MATCH_TTL=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_NAT=m
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_IP_NF_TARGET_NETMAP=m
-+CONFIG_IP_NF_TARGET_REDIRECT=m
-+CONFIG_IP_NF_MANGLE=m
-+CONFIG_IP_NF_TARGET_CLUSTERIP=m
-+CONFIG_IP_NF_TARGET_ECN=m
-+CONFIG_IP_NF_TARGET_TTL=m
-+CONFIG_IP_NF_RAW=m
-+CONFIG_IP_NF_ARPTABLES=m
-+CONFIG_IP_NF_ARPFILTER=m
-+CONFIG_IP_NF_ARP_MANGLE=m
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_AH=m
-+CONFIG_IP6_NF_MATCH_EUI64=m
-+CONFIG_IP6_NF_MATCH_FRAG=m
-+CONFIG_IP6_NF_MATCH_OPTS=m
-+CONFIG_IP6_NF_MATCH_HL=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_MATCH_MH=m
-+CONFIG_IP6_NF_MATCH_RPFILTER=m
-+CONFIG_IP6_NF_MATCH_RT=m
-+CONFIG_IP6_NF_TARGET_HL=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+CONFIG_IP6_NF_RAW=m
-+CONFIG_IP6_NF_NAT=m
-+CONFIG_IP6_NF_TARGET_MASQUERADE=m
-+CONFIG_IP6_NF_TARGET_NPT=m
-+CONFIG_BRIDGE_NF_EBTABLES=m
-+CONFIG_BRIDGE_EBT_BROUTE=m
-+CONFIG_BRIDGE_EBT_T_FILTER=m
-+CONFIG_BRIDGE_EBT_T_NAT=m
-+CONFIG_BRIDGE_EBT_802_3=m
-+CONFIG_BRIDGE_EBT_AMONG=m
-+CONFIG_BRIDGE_EBT_ARP=m
-+CONFIG_BRIDGE_EBT_IP=m
-+CONFIG_BRIDGE_EBT_IP6=m
-+CONFIG_BRIDGE_EBT_LIMIT=m
-+CONFIG_BRIDGE_EBT_MARK=m
-+CONFIG_BRIDGE_EBT_PKTTYPE=m
-+CONFIG_BRIDGE_EBT_STP=m
-+CONFIG_BRIDGE_EBT_VLAN=m
-+CONFIG_BRIDGE_EBT_ARPREPLY=m
-+CONFIG_BRIDGE_EBT_DNAT=m
-+CONFIG_BRIDGE_EBT_MARK_T=m
-+CONFIG_BRIDGE_EBT_REDIRECT=m
-+CONFIG_BRIDGE_EBT_SNAT=m
-+CONFIG_BRIDGE_EBT_LOG=m
-+CONFIG_BRIDGE_EBT_NFLOG=m
-+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-+CONFIG_ATM=m
-+CONFIG_L2TP=m
-+CONFIG_L2TP_V3=y
-+CONFIG_L2TP_IP=m
-+CONFIG_L2TP_ETH=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+CONFIG_VLAN_8021Q_GVRP=y
-+CONFIG_ATALK=m
-+CONFIG_6LOWPAN=m
-+CONFIG_IEEE802154=m
-+CONFIG_IEEE802154_6LOWPAN=m
-+CONFIG_MAC802154=m
-+CONFIG_NET_SCHED=y
-+CONFIG_NET_SCH_CBQ=m
-+CONFIG_NET_SCH_HTB=m
-+CONFIG_NET_SCH_HFSC=m
-+CONFIG_NET_SCH_ATM=m
-+CONFIG_NET_SCH_PRIO=m
-+CONFIG_NET_SCH_MULTIQ=m
-+CONFIG_NET_SCH_RED=m
-+CONFIG_NET_SCH_SFB=m
-+CONFIG_NET_SCH_SFQ=m
-+CONFIG_NET_SCH_TEQL=m
-+CONFIG_NET_SCH_TBF=m
-+CONFIG_NET_SCH_GRED=m
-+CONFIG_NET_SCH_DSMARK=m
-+CONFIG_NET_SCH_NETEM=m
-+CONFIG_NET_SCH_DRR=m
-+CONFIG_NET_SCH_MQPRIO=m
-+CONFIG_NET_SCH_CHOKE=m
-+CONFIG_NET_SCH_QFQ=m
-+CONFIG_NET_SCH_CODEL=m
-+CONFIG_NET_SCH_FQ_CODEL=m
-+CONFIG_NET_SCH_FQ=m
-+CONFIG_NET_SCH_HHF=m
-+CONFIG_NET_SCH_PIE=m
-+CONFIG_NET_SCH_INGRESS=m
-+CONFIG_NET_SCH_PLUG=m
-+CONFIG_NET_CLS_BASIC=m
-+CONFIG_NET_CLS_TCINDEX=m
-+CONFIG_NET_CLS_ROUTE4=m
-+CONFIG_NET_CLS_FW=m
-+CONFIG_NET_CLS_U32=m
-+CONFIG_CLS_U32_MARK=y
-+CONFIG_NET_CLS_RSVP=m
-+CONFIG_NET_CLS_RSVP6=m
-+CONFIG_NET_CLS_FLOW=m
-+CONFIG_NET_CLS_CGROUP=m
-+CONFIG_NET_EMATCH=y
-+CONFIG_NET_EMATCH_CMP=m
-+CONFIG_NET_EMATCH_NBYTE=m
-+CONFIG_NET_EMATCH_U32=m
-+CONFIG_NET_EMATCH_META=m
-+CONFIG_NET_EMATCH_TEXT=m
-+CONFIG_NET_EMATCH_IPSET=m
-+CONFIG_NET_CLS_ACT=y
-+CONFIG_NET_ACT_POLICE=m
-+CONFIG_NET_ACT_GACT=m
-+CONFIG_GACT_PROB=y
-+CONFIG_NET_ACT_MIRRED=m
-+CONFIG_NET_ACT_IPT=m
-+CONFIG_NET_ACT_NAT=m
-+CONFIG_NET_ACT_PEDIT=m
-+CONFIG_NET_ACT_SIMP=m
-+CONFIG_NET_ACT_SKBEDIT=m
-+CONFIG_NET_ACT_CSUM=m
-+CONFIG_BATMAN_ADV=m
-+CONFIG_OPENVSWITCH=m
-+CONFIG_NET_PKTGEN=m
-+CONFIG_HAMRADIO=y
-+CONFIG_AX25=m
-+CONFIG_NETROM=m
-+CONFIG_ROSE=m
-+CONFIG_MKISS=m
-+CONFIG_6PACK=m
-+CONFIG_BPQETHER=m
-+CONFIG_BAYCOM_SER_FDX=m
-+CONFIG_BAYCOM_SER_HDX=m
-+CONFIG_YAM=m
-+CONFIG_CAN=m
-+CONFIG_CAN_VCAN=m
-+CONFIG_CAN_SLCAN=m
-+CONFIG_CAN_MCP251X=m
-+CONFIG_CAN_GS_USB=m
-+CONFIG_BT=m
-+CONFIG_BT_RFCOMM=m
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=m
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=m
-+CONFIG_BT_6LOWPAN=m
-+CONFIG_BT_HCIBTUSB=m
-+CONFIG_BT_HCIUART=m
-+CONFIG_BT_HCIUART_3WIRE=y
-+CONFIG_BT_HCIBCM203X=m
-+CONFIG_BT_HCIBPA10X=m
-+CONFIG_BT_HCIBFUSB=m
-+CONFIG_BT_HCIVHCI=m
-+CONFIG_BT_MRVL=m
-+CONFIG_BT_MRVL_SDIO=m
-+CONFIG_BT_ATH3K=m
-+CONFIG_BT_WILINK=m
-+CONFIG_CFG80211=m
-+CONFIG_MAC80211=m
-+CONFIG_MAC80211_MESH=y
-+CONFIG_WIMAX=m
-+CONFIG_RFKILL=m
-+CONFIG_RFKILL_INPUT=y
-+CONFIG_NET_9P=m
-+CONFIG_NFC=m
-+CONFIG_DEVTMPFS=y
-+CONFIG_DEVTMPFS_MOUNT=y
-+CONFIG_DMA_CMA=y
-+CONFIG_CMA_SIZE_MBYTES=5
-+CONFIG_MTD=m
-+CONFIG_MTD_BLOCK=m
-+CONFIG_MTD_M25P80=m
-+CONFIG_MTD_NAND=m
-+CONFIG_MTD_SPI_NOR=m
-+CONFIG_MTD_UBI=m
-+CONFIG_OF_CONFIGFS=y
-+CONFIG_ZRAM=m
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+CONFIG_BLK_DEV_DRBD=m
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_ATA_OVER_ETH=m
-+CONFIG_EEPROM_AT24=m
-+CONFIG_TI_ST=m
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_CHR_DEV_ST=m
-+CONFIG_CHR_DEV_OSST=m
-+CONFIG_BLK_DEV_SR=m
-+CONFIG_CHR_DEV_SG=m
-+CONFIG_SCSI_ISCSI_ATTRS=y
-+CONFIG_ISCSI_TCP=m
-+CONFIG_ISCSI_BOOT_SYSFS=m
-+CONFIG_MD=y
-+CONFIG_MD_LINEAR=m
-+CONFIG_BLK_DEV_DM=m
-+CONFIG_DM_CRYPT=m
-+CONFIG_DM_SNAPSHOT=m
-+CONFIG_DM_THIN_PROVISIONING=m
-+CONFIG_DM_MIRROR=m
-+CONFIG_DM_LOG_USERSPACE=m
-+CONFIG_DM_RAID=m
-+CONFIG_DM_ZERO=m
-+CONFIG_DM_DELAY=m
-+CONFIG_NETDEVICES=y
-+CONFIG_BONDING=m
-+CONFIG_DUMMY=m
-+CONFIG_IFB=m
-+CONFIG_MACVLAN=m
-+CONFIG_VXLAN=m
-+CONFIG_NETCONSOLE=m
-+CONFIG_TUN=m
-+CONFIG_VETH=m
-+CONFIG_ENC28J60=m
-+CONFIG_MDIO_BITBANG=m
-+CONFIG_PPP=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPP_MULTILINK=y
-+CONFIG_PPPOATM=m
-+CONFIG_PPPOE=m
-+CONFIG_PPPOL2TP=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_SLIP=m
-+CONFIG_SLIP_COMPRESSED=y
-+CONFIG_SLIP_SMART=y
-+CONFIG_USB_CATC=m
-+CONFIG_USB_KAWETH=m
-+CONFIG_USB_PEGASUS=m
-+CONFIG_USB_RTL8150=m
-+CONFIG_USB_RTL8152=m
-+CONFIG_USB_LAN78XX=m
-+CONFIG_USB_USBNET=y
-+CONFIG_USB_NET_AX8817X=m
-+CONFIG_USB_NET_AX88179_178A=m
-+CONFIG_USB_NET_CDCETHER=m
-+CONFIG_USB_NET_CDC_EEM=m
-+CONFIG_USB_NET_CDC_NCM=m
-+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-+CONFIG_USB_NET_CDC_MBIM=m
-+CONFIG_USB_NET_DM9601=m
-+CONFIG_USB_NET_SR9700=m
-+CONFIG_USB_NET_SR9800=m
-+CONFIG_USB_NET_SMSC75XX=m
-+CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_NET_GL620A=m
-+CONFIG_USB_NET_NET1080=m
-+CONFIG_USB_NET_PLUSB=m
-+CONFIG_USB_NET_MCS7830=m
-+CONFIG_USB_NET_CDC_SUBSET=m
-+CONFIG_USB_ALI_M5632=y
-+CONFIG_USB_AN2720=y
-+CONFIG_USB_EPSON2888=y
-+CONFIG_USB_KC2190=y
-+CONFIG_USB_NET_ZAURUS=m
-+CONFIG_USB_NET_CX82310_ETH=m
-+CONFIG_USB_NET_KALMIA=m
-+CONFIG_USB_NET_QMI_WWAN=m
-+CONFIG_USB_HSO=m
-+CONFIG_USB_NET_INT51X1=m
-+CONFIG_USB_IPHETH=m
-+CONFIG_USB_SIERRA_NET=m
-+CONFIG_USB_VL600=m
-+CONFIG_ATH9K=m
-+CONFIG_ATH9K_HTC=m
-+CONFIG_CARL9170=m
-+CONFIG_ATH6KL=m
-+CONFIG_ATH6KL_USB=m
-+CONFIG_AR5523=m
-+CONFIG_AT76C50X_USB=m
-+CONFIG_B43=m
-+# CONFIG_B43_PHY_N is not set
-+CONFIG_B43LEGACY=m
-+CONFIG_BRCMFMAC=m
-+CONFIG_BRCMFMAC_USB=y
-+CONFIG_BRCMDBG=y
-+CONFIG_HOSTAP=m
-+CONFIG_P54_COMMON=m
-+CONFIG_P54_USB=m
-+CONFIG_LIBERTAS=m
-+CONFIG_LIBERTAS_USB=m
-+CONFIG_LIBERTAS_SDIO=m
-+CONFIG_LIBERTAS_THINFIRM=m
-+CONFIG_LIBERTAS_THINFIRM_USB=m
-+CONFIG_MWIFIEX=m
-+CONFIG_MWIFIEX_SDIO=m
-+CONFIG_MT7601U=m
-+CONFIG_RT2X00=m
-+CONFIG_RT2500USB=m
-+CONFIG_RT73USB=m
-+CONFIG_RT2800USB=m
-+CONFIG_RT2800USB_RT3573=y
-+CONFIG_RT2800USB_RT53XX=y
-+CONFIG_RT2800USB_RT55XX=y
-+CONFIG_RT2800USB_UNKNOWN=y
-+CONFIG_RTL8187=m
-+CONFIG_RTL8192CU=m
-+CONFIG_RTL8XXXU=m
-+CONFIG_USB_ZD1201=m
-+CONFIG_ZD1211RW=m
-+CONFIG_MAC80211_HWSIM=m
-+CONFIG_USB_NET_RNDIS_WLAN=m
-+CONFIG_WIMAX_I2400M_USB=m
-+CONFIG_IEEE802154_AT86RF230=m
-+CONFIG_IEEE802154_MRF24J40=m
-+CONFIG_IEEE802154_CC2520=m
-+CONFIG_INPUT_MOUSEDEV=y
-+CONFIG_INPUT_JOYDEV=m
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_KEYBOARD_ATKBD is not set
-+CONFIG_KEYBOARD_GPIO=m
-+# CONFIG_INPUT_MOUSE is not set
-+CONFIG_INPUT_JOYSTICK=y
-+CONFIG_JOYSTICK_IFORCE=m
-+CONFIG_JOYSTICK_IFORCE_USB=y
-+CONFIG_JOYSTICK_XPAD=m
-+CONFIG_JOYSTICK_XPAD_FF=y
-+CONFIG_JOYSTICK_XPAD_LEDS=y
-+CONFIG_JOYSTICK_PSXPAD_SPI=m
-+CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-+CONFIG_JOYSTICK_RPISENSE=m
-+CONFIG_INPUT_TOUCHSCREEN=y
-+CONFIG_TOUCHSCREEN_ADS7846=m
-+CONFIG_TOUCHSCREEN_EGALAX=m
-+CONFIG_TOUCHSCREEN_GOODIX=m
-+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-+CONFIG_TOUCHSCREEN_RPI_FT5406=m
-+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-+CONFIG_TOUCHSCREEN_STMPE=m
-+CONFIG_INPUT_MISC=y
-+CONFIG_INPUT_AD714X=m
-+CONFIG_INPUT_ATI_REMOTE2=m
-+CONFIG_INPUT_KEYSPAN_REMOTE=m
-+CONFIG_INPUT_POWERMATE=m
-+CONFIG_INPUT_YEALINK=m
-+CONFIG_INPUT_CM109=m
-+CONFIG_INPUT_UINPUT=m
-+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-+CONFIG_INPUT_ADXL34X=m
-+CONFIG_INPUT_CMA3000=m
-+CONFIG_SERIO=m
-+CONFIG_SERIO_RAW=m
-+CONFIG_GAMEPORT=m
-+CONFIG_GAMEPORT_NS558=m
-+CONFIG_GAMEPORT_L4=m
-+CONFIG_BRCM_CHAR_DRIVERS=y
-+CONFIG_BCM_VCIO=y
-+CONFIG_BCM_VC_SM=y
-+CONFIG_BCM2835_DEVGPIOMEM=y
-+# CONFIG_LEGACY_PTYS is not set
-+CONFIG_SERIAL_8250=y
-+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-+CONFIG_SERIAL_8250_CONSOLE=y
-+# CONFIG_SERIAL_8250_DMA is not set
-+CONFIG_SERIAL_8250_NR_UARTS=1
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=0
-+CONFIG_SERIAL_8250_EXTENDED=y
-+CONFIG_SERIAL_8250_SHARE_IRQ=y
-+CONFIG_SERIAL_8250_BCM2835AUX=y
-+CONFIG_SERIAL_OF_PLATFORM=y
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+CONFIG_SERIAL_SC16IS7XX=m
-+CONFIG_SERIAL_SC16IS7XX_SPI=y
-+CONFIG_TTY_PRINTK=y
-+CONFIG_HW_RANDOM=y
-+CONFIG_RAW_DRIVER=y
-+CONFIG_I2C=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_MUX_GPMUX=m
-+CONFIG_I2C_MUX_PCA954x=m
-+CONFIG_I2C_BCM2708=m
-+CONFIG_I2C_BCM2835=m
-+CONFIG_I2C_GPIO=m
-+CONFIG_I2C_ROBOTFUZZ_OSIF=m
-+CONFIG_SPI=y
-+CONFIG_SPI_BCM2835=m
-+CONFIG_SPI_BCM2835AUX=m
-+CONFIG_SPI_SPIDEV=m
-+CONFIG_SPI_SLAVE=y
-+CONFIG_PPS=m
-+CONFIG_PPS_CLIENT_LDISC=m
-+CONFIG_PPS_CLIENT_GPIO=m
-+CONFIG_GPIO_SYSFS=y
-+CONFIG_GPIO_BCM_EXP=y
-+CONFIG_GPIO_BCM_VIRT=y
-+CONFIG_GPIO_PCF857X=m
-+CONFIG_GPIO_ARIZONA=m
-+CONFIG_GPIO_STMPE=y
-+CONFIG_W1=m
-+CONFIG_W1_MASTER_DS2490=m
-+CONFIG_W1_MASTER_DS2482=m
-+CONFIG_W1_MASTER_DS1WM=m
-+CONFIG_W1_MASTER_GPIO=m
-+CONFIG_W1_SLAVE_THERM=m
-+CONFIG_W1_SLAVE_SMEM=m
-+CONFIG_W1_SLAVE_DS2408=m
-+CONFIG_W1_SLAVE_DS2413=m
-+CONFIG_W1_SLAVE_DS2406=m
-+CONFIG_W1_SLAVE_DS2423=m
-+CONFIG_W1_SLAVE_DS2431=m
-+CONFIG_W1_SLAVE_DS2433=m
-+CONFIG_W1_SLAVE_DS2438=m
-+CONFIG_W1_SLAVE_DS2760=m
-+CONFIG_W1_SLAVE_DS2780=m
-+CONFIG_W1_SLAVE_DS2781=m
-+CONFIG_W1_SLAVE_DS28E04=m
-+CONFIG_POWER_RESET=y
-+CONFIG_POWER_RESET_GPIO=y
-+CONFIG_BATTERY_DS2760=m
-+CONFIG_HWMON=m
-+CONFIG_SENSORS_JC42=m
-+CONFIG_SENSORS_LM75=m
-+CONFIG_SENSORS_SHT21=m
-+CONFIG_SENSORS_SHT3x=m
-+CONFIG_SENSORS_SHTC1=m
-+CONFIG_SENSORS_ADS1015=m
-+CONFIG_SENSORS_INA2XX=m
-+CONFIG_SENSORS_TMP102=m
-+CONFIG_THERMAL=y
-+CONFIG_BCM2835_THERMAL=y
-+CONFIG_WATCHDOG=y
-+CONFIG_GPIO_WATCHDOG=m
-+CONFIG_BCM2835_WDT=y
-+CONFIG_MFD_STMPE=y
-+CONFIG_STMPE_SPI=y
-+CONFIG_MFD_ARIZONA_I2C=m
-+CONFIG_MFD_ARIZONA_SPI=m
-+CONFIG_MFD_WM5102=y
-+CONFIG_REGULATOR=y
-+CONFIG_REGULATOR_FIXED_VOLTAGE=m
-+CONFIG_REGULATOR_ARIZONA_LDO1=m
-+CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-+CONFIG_LIRC=m
-+CONFIG_RC_DEVICES=y
-+CONFIG_RC_ATI_REMOTE=m
-+CONFIG_IR_IMON=m
-+CONFIG_IR_MCEUSB=m
-+CONFIG_IR_REDRAT3=m
-+CONFIG_IR_STREAMZAP=m
-+CONFIG_IR_IGUANA=m
-+CONFIG_IR_TTUSBIR=m
-+CONFIG_RC_LOOPBACK=m
-+CONFIG_IR_GPIO_CIR=m
-+CONFIG_IR_GPIO_TX=m
-+CONFIG_IR_PWM_TX=m
-+CONFIG_MEDIA_SUPPORT=m
-+CONFIG_MEDIA_CAMERA_SUPPORT=y
-+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-+CONFIG_MEDIA_RADIO_SUPPORT=y
-+CONFIG_MEDIA_CONTROLLER=y
-+CONFIG_MEDIA_USB_SUPPORT=y
-+CONFIG_USB_VIDEO_CLASS=m
-+CONFIG_USB_M5602=m
-+CONFIG_USB_STV06XX=m
-+CONFIG_USB_GL860=m
-+CONFIG_USB_GSPCA_BENQ=m
-+CONFIG_USB_GSPCA_CONEX=m
-+CONFIG_USB_GSPCA_CPIA1=m
-+CONFIG_USB_GSPCA_DTCS033=m
-+CONFIG_USB_GSPCA_ETOMS=m
-+CONFIG_USB_GSPCA_FINEPIX=m
-+CONFIG_USB_GSPCA_JEILINJ=m
-+CONFIG_USB_GSPCA_JL2005BCD=m
-+CONFIG_USB_GSPCA_KINECT=m
-+CONFIG_USB_GSPCA_KONICA=m
-+CONFIG_USB_GSPCA_MARS=m
-+CONFIG_USB_GSPCA_MR97310A=m
-+CONFIG_USB_GSPCA_NW80X=m
-+CONFIG_USB_GSPCA_OV519=m
-+CONFIG_USB_GSPCA_OV534=m
-+CONFIG_USB_GSPCA_OV534_9=m
-+CONFIG_USB_GSPCA_PAC207=m
-+CONFIG_USB_GSPCA_PAC7302=m
-+CONFIG_USB_GSPCA_PAC7311=m
-+CONFIG_USB_GSPCA_SE401=m
-+CONFIG_USB_GSPCA_SN9C2028=m
-+CONFIG_USB_GSPCA_SN9C20X=m
-+CONFIG_USB_GSPCA_SONIXB=m
-+CONFIG_USB_GSPCA_SONIXJ=m
-+CONFIG_USB_GSPCA_SPCA500=m
-+CONFIG_USB_GSPCA_SPCA501=m
-+CONFIG_USB_GSPCA_SPCA505=m
-+CONFIG_USB_GSPCA_SPCA506=m
-+CONFIG_USB_GSPCA_SPCA508=m
-+CONFIG_USB_GSPCA_SPCA561=m
-+CONFIG_USB_GSPCA_SPCA1528=m
-+CONFIG_USB_GSPCA_SQ905=m
-+CONFIG_USB_GSPCA_SQ905C=m
-+CONFIG_USB_GSPCA_SQ930X=m
-+CONFIG_USB_GSPCA_STK014=m
-+CONFIG_USB_GSPCA_STK1135=m
-+CONFIG_USB_GSPCA_STV0680=m
-+CONFIG_USB_GSPCA_SUNPLUS=m
-+CONFIG_USB_GSPCA_T613=m
-+CONFIG_USB_GSPCA_TOPRO=m
-+CONFIG_USB_GSPCA_TV8532=m
-+CONFIG_USB_GSPCA_VC032X=m
-+CONFIG_USB_GSPCA_VICAM=m
-+CONFIG_USB_GSPCA_XIRLINK_CIT=m
-+CONFIG_USB_GSPCA_ZC3XX=m
-+CONFIG_USB_PWC=m
-+CONFIG_VIDEO_CPIA2=m
-+CONFIG_USB_ZR364XX=m
-+CONFIG_USB_STKWEBCAM=m
-+CONFIG_USB_S2255=m
-+CONFIG_VIDEO_USBTV=m
-+CONFIG_VIDEO_PVRUSB2=m
-+CONFIG_VIDEO_HDPVR=m
-+CONFIG_VIDEO_USBVISION=m
-+CONFIG_VIDEO_STK1160_COMMON=m
-+CONFIG_VIDEO_GO7007=m
-+CONFIG_VIDEO_GO7007_USB=m
-+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-+CONFIG_VIDEO_AU0828=m
-+CONFIG_VIDEO_AU0828_RC=y
-+CONFIG_VIDEO_CX231XX=m
-+CONFIG_VIDEO_CX231XX_ALSA=m
-+CONFIG_VIDEO_CX231XX_DVB=m
-+CONFIG_VIDEO_TM6000=m
-+CONFIG_VIDEO_TM6000_ALSA=m
-+CONFIG_VIDEO_TM6000_DVB=m
-+CONFIG_DVB_USB=m
-+CONFIG_DVB_USB_A800=m
-+CONFIG_DVB_USB_DIBUSB_MB=m
-+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-+CONFIG_DVB_USB_DIBUSB_MC=m
-+CONFIG_DVB_USB_DIB0700=m
-+CONFIG_DVB_USB_UMT_010=m
-+CONFIG_DVB_USB_CXUSB=m
-+CONFIG_DVB_USB_M920X=m
-+CONFIG_DVB_USB_DIGITV=m
-+CONFIG_DVB_USB_VP7045=m
-+CONFIG_DVB_USB_VP702X=m
-+CONFIG_DVB_USB_GP8PSK=m
-+CONFIG_DVB_USB_NOVA_T_USB2=m
-+CONFIG_DVB_USB_TTUSB2=m
-+CONFIG_DVB_USB_DTT200U=m
-+CONFIG_DVB_USB_OPERA1=m
-+CONFIG_DVB_USB_AF9005=m
-+CONFIG_DVB_USB_AF9005_REMOTE=m
-+CONFIG_DVB_USB_PCTV452E=m
-+CONFIG_DVB_USB_DW2102=m
-+CONFIG_DVB_USB_CINERGY_T2=m
-+CONFIG_DVB_USB_DTV5100=m
-+CONFIG_DVB_USB_FRIIO=m
-+CONFIG_DVB_USB_AZ6027=m
-+CONFIG_DVB_USB_TECHNISAT_USB2=m
-+CONFIG_DVB_USB_V2=m
-+CONFIG_DVB_USB_AF9015=m
-+CONFIG_DVB_USB_AF9035=m
-+CONFIG_DVB_USB_ANYSEE=m
-+CONFIG_DVB_USB_AU6610=m
-+CONFIG_DVB_USB_AZ6007=m
-+CONFIG_DVB_USB_CE6230=m
-+CONFIG_DVB_USB_EC168=m
-+CONFIG_DVB_USB_GL861=m
-+CONFIG_DVB_USB_LME2510=m
-+CONFIG_DVB_USB_MXL111SF=m
-+CONFIG_DVB_USB_RTL28XXU=m
-+CONFIG_DVB_USB_DVBSKY=m
-+CONFIG_SMS_USB_DRV=m
-+CONFIG_DVB_B2C2_FLEXCOP_USB=m
-+CONFIG_DVB_AS102=m
-+CONFIG_VIDEO_EM28XX=m
-+CONFIG_VIDEO_EM28XX_V4L2=m
-+CONFIG_VIDEO_EM28XX_ALSA=m
-+CONFIG_VIDEO_EM28XX_DVB=m
-+CONFIG_V4L_PLATFORM_DRIVERS=y
-+CONFIG_RADIO_SI470X=y
-+CONFIG_USB_SI470X=m
-+CONFIG_I2C_SI470X=m
-+CONFIG_RADIO_SI4713=m
-+CONFIG_I2C_SI4713=m
-+CONFIG_USB_MR800=m
-+CONFIG_USB_DSBR=m
-+CONFIG_RADIO_SHARK=m
-+CONFIG_RADIO_SHARK2=m
-+CONFIG_USB_KEENE=m
-+CONFIG_USB_MA901=m
-+CONFIG_RADIO_TEA5764=m
-+CONFIG_RADIO_SAA7706H=m
-+CONFIG_RADIO_TEF6862=m
-+CONFIG_RADIO_WL1273=m
-+CONFIG_RADIO_WL128X=m
-+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
-+CONFIG_VIDEO_UDA1342=m
-+CONFIG_VIDEO_SONY_BTF_MPX=m
-+CONFIG_VIDEO_TVP5150=m
-+CONFIG_VIDEO_TW2804=m
-+CONFIG_VIDEO_TW9903=m
-+CONFIG_VIDEO_TW9906=m
-+CONFIG_VIDEO_OV7640=m
-+CONFIG_VIDEO_MT9V011=m
-+CONFIG_DRM=m
-+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-+CONFIG_DRM_UDL=m
-+CONFIG_DRM_PANEL_SIMPLE=m
-+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-+CONFIG_DRM_VC4=m
-+CONFIG_DRM_TINYDRM=m
-+CONFIG_TINYDRM_MI0283QT=m
-+CONFIG_TINYDRM_REPAPER=m
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+CONFIG_FB_UDL=m
-+CONFIG_FB_SSD1307=m
-+CONFIG_FB_RPISENSE=m
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+CONFIG_BACKLIGHT_RPI=m
-+CONFIG_BACKLIGHT_GPIO=m
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=m
-+CONFIG_SND_HRTIMER=m
-+CONFIG_SND_SEQUENCER=m
-+CONFIG_SND_SEQ_DUMMY=m
-+CONFIG_SND_DUMMY=m
-+CONFIG_SND_ALOOP=m
-+CONFIG_SND_VIRMIDI=m
-+CONFIG_SND_MTPAV=m
-+CONFIG_SND_SERIAL_U16550=m
-+CONFIG_SND_MPU401=m
-+CONFIG_SND_USB_AUDIO=m
-+CONFIG_SND_USB_UA101=m
-+CONFIG_SND_USB_CAIAQ=m
-+CONFIG_SND_USB_CAIAQ_INPUT=y
-+CONFIG_SND_USB_6FIRE=m
-+CONFIG_SND_SOC=m
-+CONFIG_SND_BCM2835_SOC_I2S=m
-+CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
-+CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m
-+CONFIG_SND_BCM2708_SOC_RPI_DAC=m
-+CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
-+CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m
-+CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m
-+CONFIG_SND_BCM2708_SOC_RASPIDAC3=m
-+CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m
-+CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m
-+CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m
-+CONFIG_SND_DIGIDAC1_SOUNDCARD=m
-+CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m
-+CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m
-+CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m
-+CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m
-+CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m
-+CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m
-+CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m
-+CONFIG_SND_PISOUND=m
-+CONFIG_SND_SOC_ADAU1701=m
-+CONFIG_SND_SOC_ADAU7002=m
-+CONFIG_SND_SOC_AK4554=m
-+CONFIG_SND_SOC_SPDIF=m
-+CONFIG_SND_SOC_WM8804_I2C=m
-+CONFIG_SND_SIMPLE_CARD=m
-+CONFIG_HID_BATTERY_STRENGTH=y
-+CONFIG_HIDRAW=y
-+CONFIG_UHID=m
-+CONFIG_HID_A4TECH=m
-+CONFIG_HID_ACRUX=m
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_ASUS=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_BETOP_FF=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+CONFIG_HID_CYPRESS=m
-+CONFIG_HID_DRAGONRISE=m
-+CONFIG_HID_EMS_FF=m
-+CONFIG_HID_ELECOM=m
-+CONFIG_HID_ELO=m
-+CONFIG_HID_EZKEY=m
-+CONFIG_HID_GEMBIRD=m
-+CONFIG_HID_HOLTEK=m
-+CONFIG_HID_KEYTOUCH=m
-+CONFIG_HID_KYE=m
-+CONFIG_HID_UCLOGIC=m
-+CONFIG_HID_WALTOP=m
-+CONFIG_HID_GYRATION=m
-+CONFIG_HID_TWINHAN=m
-+CONFIG_HID_KENSINGTON=m
-+CONFIG_HID_LCPOWER=m
-+CONFIG_HID_LOGITECH=m
-+CONFIG_HID_LOGITECH_DJ=m
-+CONFIG_LOGITECH_FF=y
-+CONFIG_LOGIRUMBLEPAD2_FF=y
-+CONFIG_LOGIG940_FF=y
-+CONFIG_HID_MAGICMOUSE=m
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+CONFIG_HID_MULTITOUCH=m
-+CONFIG_HID_NTRIG=m
-+CONFIG_HID_ORTEK=m
-+CONFIG_HID_PANTHERLORD=m
-+CONFIG_HID_PETALYNX=m
-+CONFIG_HID_PICOLCD=m
-+CONFIG_HID_ROCCAT=m
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SONY=m
-+CONFIG_SONY_FF=y
-+CONFIG_HID_SPEEDLINK=m
-+CONFIG_HID_SUNPLUS=m
-+CONFIG_HID_GREENASIA=m
-+CONFIG_HID_SMARTJOYPLUS=m
-+CONFIG_HID_TOPSEED=m
-+CONFIG_HID_THINGM=m
-+CONFIG_HID_THRUSTMASTER=m
-+CONFIG_HID_WACOM=m
-+CONFIG_HID_WIIMOTE=m
-+CONFIG_HID_XINMO=m
-+CONFIG_HID_ZEROPLUS=m
-+CONFIG_HID_ZYDACRON=m
-+CONFIG_HID_PID=y
-+CONFIG_USB_HIDDEV=y
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=y
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_REALTEK=m
-+CONFIG_USB_STORAGE_DATAFAB=m
-+CONFIG_USB_STORAGE_FREECOM=m
-+CONFIG_USB_STORAGE_ISD200=m
-+CONFIG_USB_STORAGE_USBAT=m
-+CONFIG_USB_STORAGE_SDDR09=m
-+CONFIG_USB_STORAGE_SDDR55=m
-+CONFIG_USB_STORAGE_JUMPSHOT=m
-+CONFIG_USB_STORAGE_ALAUDA=m
-+CONFIG_USB_STORAGE_ONETOUCH=m
-+CONFIG_USB_STORAGE_KARMA=m
-+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-+CONFIG_USB_STORAGE_ENE_UB6250=m
-+CONFIG_USB_MDC800=m
-+CONFIG_USB_MICROTEK=m
-+CONFIG_USBIP_CORE=m
-+CONFIG_USBIP_VHCI_HCD=m
-+CONFIG_USBIP_HOST=m
-+CONFIG_USB_DWC2=m
-+CONFIG_USB_SERIAL=m
-+CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRCABLE=m
-+CONFIG_USB_SERIAL_ARK3116=m
-+CONFIG_USB_SERIAL_BELKIN=m
-+CONFIG_USB_SERIAL_CH341=m
-+CONFIG_USB_SERIAL_WHITEHEAT=m
-+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+CONFIG_USB_SERIAL_CP210X=m
-+CONFIG_USB_SERIAL_CYPRESS_M8=m
-+CONFIG_USB_SERIAL_EMPEG=m
-+CONFIG_USB_SERIAL_FTDI_SIO=m
-+CONFIG_USB_SERIAL_VISOR=m
-+CONFIG_USB_SERIAL_IPAQ=m
-+CONFIG_USB_SERIAL_IR=m
-+CONFIG_USB_SERIAL_EDGEPORT=m
-+CONFIG_USB_SERIAL_EDGEPORT_TI=m
-+CONFIG_USB_SERIAL_F81232=m
-+CONFIG_USB_SERIAL_GARMIN=m
-+CONFIG_USB_SERIAL_IPW=m
-+CONFIG_USB_SERIAL_IUU=m
-+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-+CONFIG_USB_SERIAL_KEYSPAN=m
-+CONFIG_USB_SERIAL_KLSI=m
-+CONFIG_USB_SERIAL_KOBIL_SCT=m
-+CONFIG_USB_SERIAL_MCT_U232=m
-+CONFIG_USB_SERIAL_METRO=m
-+CONFIG_USB_SERIAL_MOS7720=m
-+CONFIG_USB_SERIAL_MOS7840=m
-+CONFIG_USB_SERIAL_NAVMAN=m
-+CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_OTI6858=m
-+CONFIG_USB_SERIAL_QCAUX=m
-+CONFIG_USB_SERIAL_QUALCOMM=m
-+CONFIG_USB_SERIAL_SPCP8X5=m
-+CONFIG_USB_SERIAL_SAFE=m
-+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-+CONFIG_USB_SERIAL_SYMBOL=m
-+CONFIG_USB_SERIAL_TI=m
-+CONFIG_USB_SERIAL_CYBERJACK=m
-+CONFIG_USB_SERIAL_XIRCOM=m
-+CONFIG_USB_SERIAL_OPTION=m
-+CONFIG_USB_SERIAL_OMNINET=m
-+CONFIG_USB_SERIAL_OPTICON=m
-+CONFIG_USB_SERIAL_XSENS_MT=m
-+CONFIG_USB_SERIAL_WISHBONE=m
-+CONFIG_USB_SERIAL_SSU100=m
-+CONFIG_USB_SERIAL_QT2=m
-+CONFIG_USB_SERIAL_DEBUG=m
-+CONFIG_USB_EMI62=m
-+CONFIG_USB_EMI26=m
-+CONFIG_USB_ADUTUX=m
-+CONFIG_USB_SEVSEG=m
-+CONFIG_USB_RIO500=m
-+CONFIG_USB_LEGOTOWER=m
-+CONFIG_USB_LCD=m
-+CONFIG_USB_CYPRESS_CY7C63=m
-+CONFIG_USB_CYTHERM=m
-+CONFIG_USB_IDMOUSE=m
-+CONFIG_USB_FTDI_ELAN=m
-+CONFIG_USB_APPLEDISPLAY=m
-+CONFIG_USB_LD=m
-+CONFIG_USB_TRANCEVIBRATOR=m
-+CONFIG_USB_IOWARRIOR=m
-+CONFIG_USB_TEST=m
-+CONFIG_USB_ISIGHTFW=m
-+CONFIG_USB_YUREX=m
-+CONFIG_USB_ATM=m
-+CONFIG_USB_SPEEDTOUCH=m
-+CONFIG_USB_CXACRU=m
-+CONFIG_USB_UEAGLEATM=m
-+CONFIG_USB_XUSBATM=m
-+CONFIG_USB_GADGET=m
-+CONFIG_MMC=y
-+CONFIG_MMC_BLOCK_MINORS=32
-+CONFIG_MMC_BCM2835_MMC=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_MMC_BCM2835_SDHOST=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SPI=m
-+CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_ONESHOT=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-+CONFIG_LEDS_TRIGGER_CPU=y
-+CONFIG_LEDS_TRIGGER_GPIO=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TRANSIENT=m
-+CONFIG_LEDS_TRIGGER_CAMERA=m
-+CONFIG_LEDS_TRIGGER_INPUT=y
-+CONFIG_LEDS_TRIGGER_PANIC=y
-+CONFIG_RTC_CLASS=y
-+# CONFIG_RTC_HCTOSYS is not set
-+CONFIG_RTC_DRV_ABX80X=m
-+CONFIG_RTC_DRV_DS1307=m
-+CONFIG_RTC_DRV_DS1374=m
-+CONFIG_RTC_DRV_DS1672=m
-+CONFIG_RTC_DRV_MAX6900=m
-+CONFIG_RTC_DRV_RS5C372=m
-+CONFIG_RTC_DRV_ISL1208=m
-+CONFIG_RTC_DRV_ISL12022=m
-+CONFIG_RTC_DRV_X1205=m
-+CONFIG_RTC_DRV_PCF8523=m
-+CONFIG_RTC_DRV_PCF8563=m
-+CONFIG_RTC_DRV_PCF8583=m
-+CONFIG_RTC_DRV_M41T80=m
-+CONFIG_RTC_DRV_BQ32K=m
-+CONFIG_RTC_DRV_S35390A=m
-+CONFIG_RTC_DRV_FM3130=m
-+CONFIG_RTC_DRV_RX8581=m
-+CONFIG_RTC_DRV_RX8025=m
-+CONFIG_RTC_DRV_EM3027=m
-+CONFIG_RTC_DRV_M41T93=m
-+CONFIG_RTC_DRV_M41T94=m
-+CONFIG_RTC_DRV_DS1302=m
-+CONFIG_RTC_DRV_DS1305=m
-+CONFIG_RTC_DRV_DS1390=m
-+CONFIG_RTC_DRV_R9701=m
-+CONFIG_RTC_DRV_RX4581=m
-+CONFIG_RTC_DRV_RS5C348=m
-+CONFIG_RTC_DRV_MAX6902=m
-+CONFIG_RTC_DRV_PCF2123=m
-+CONFIG_RTC_DRV_DS3232=m
-+CONFIG_RTC_DRV_PCF2127=m
-+CONFIG_RTC_DRV_RV3029C2=m
-+CONFIG_DMADEVICES=y
-+CONFIG_DMA_BCM2835=y
-+CONFIG_DMA_BCM2708=y
-+CONFIG_UIO=m
-+CONFIG_UIO_PDRV_GENIRQ=m
-+CONFIG_STAGING=y
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRNET=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
-+CONFIG_PRISM2_USB=m
-+CONFIG_R8712U=m
-+CONFIG_R8188EU=m
-+CONFIG_VT6656=m
-+CONFIG_SPEAKUP=m
-+CONFIG_SPEAKUP_SYNTH_SOFT=m
-+CONFIG_STAGING_MEDIA=y
-+CONFIG_LIRC_STAGING=y
-+CONFIG_LIRC_RPI=m
-+CONFIG_FB_TFT=m
-+CONFIG_FB_TFT_AGM1264K_FL=m
-+CONFIG_FB_TFT_BD663474=m
-+CONFIG_FB_TFT_HX8340BN=m
-+CONFIG_FB_TFT_HX8347D=m
-+CONFIG_FB_TFT_HX8353D=m
-+CONFIG_FB_TFT_HX8357D=m
-+CONFIG_FB_TFT_ILI9163=m
-+CONFIG_FB_TFT_ILI9320=m
-+CONFIG_FB_TFT_ILI9325=m
-+CONFIG_FB_TFT_ILI9340=m
-+CONFIG_FB_TFT_ILI9341=m
-+CONFIG_FB_TFT_ILI9481=m
-+CONFIG_FB_TFT_ILI9486=m
-+CONFIG_FB_TFT_PCD8544=m
-+CONFIG_FB_TFT_RA8875=m
-+CONFIG_FB_TFT_S6D02A1=m
-+CONFIG_FB_TFT_S6D1121=m
-+CONFIG_FB_TFT_SSD1289=m
-+CONFIG_FB_TFT_SSD1306=m
-+CONFIG_FB_TFT_SSD1331=m
-+CONFIG_FB_TFT_SSD1351=m
-+CONFIG_FB_TFT_ST7735R=m
-+CONFIG_FB_TFT_ST7789V=m
-+CONFIG_FB_TFT_TINYLCD=m
-+CONFIG_FB_TFT_TLS8204=m
-+CONFIG_FB_TFT_UC1701=m
-+CONFIG_FB_TFT_UPD161704=m
-+CONFIG_FB_TFT_WATTEROTT=m
-+CONFIG_FB_FLEX=m
-+CONFIG_FB_TFT_FBTFT_DEVICE=m
-+CONFIG_BCM2835_VCHIQ=y
-+CONFIG_BCM2835_VCHIQ_SUPPORT_MEMDUMP=y
-+CONFIG_SND_BCM2835=m
-+CONFIG_VIDEO_BCM2835=m
-+CONFIG_MAILBOX=y
-+CONFIG_BCM2835_MBOX=y
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_RASPBERRYPI_POWER=y
-+CONFIG_EXTCON=m
-+CONFIG_EXTCON_ARIZONA=m
-+CONFIG_IIO=m
-+CONFIG_IIO_BUFFER_CB=m
-+CONFIG_MCP320X=m
-+CONFIG_MCP3422=m
-+CONFIG_DHT11=m
-+CONFIG_HDC100X=m
-+CONFIG_HTU21=m
-+CONFIG_INV_MPU6050_I2C=m
-+CONFIG_TSL4531=m
-+CONFIG_VEML6070=m
-+CONFIG_BMP280=m
-+CONFIG_PWM_BCM2835=m
-+CONFIG_PWM_PCA9685=m
-+CONFIG_RPI_AXIPERF=m
-+CONFIG_RASPBERRYPI_FIRMWARE=y
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_REISERFS_FS=m
-+CONFIG_REISERFS_FS_XATTR=y
-+CONFIG_REISERFS_FS_POSIX_ACL=y
-+CONFIG_REISERFS_FS_SECURITY=y
-+CONFIG_JFS_FS=m
-+CONFIG_JFS_POSIX_ACL=y
-+CONFIG_JFS_SECURITY=y
-+CONFIG_JFS_STATISTICS=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_QUOTA=y
-+CONFIG_XFS_POSIX_ACL=y
-+CONFIG_XFS_RT=y
-+CONFIG_GFS2_FS=m
-+CONFIG_OCFS2_FS=m
-+CONFIG_BTRFS_FS=m
-+CONFIG_BTRFS_FS_POSIX_ACL=y
-+CONFIG_NILFS2_FS=m
-+CONFIG_F2FS_FS=y
-+CONFIG_FANOTIFY=y
-+CONFIG_QFMT_V1=m
-+CONFIG_QFMT_V2=m
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FUSE_FS=m
-+CONFIG_CUSE=m
-+CONFIG_OVERLAY_FS=m
-+CONFIG_FSCACHE=y
-+CONFIG_FSCACHE_STATS=y
-+CONFIG_FSCACHE_HISTOGRAM=y
-+CONFIG_CACHEFILES=y
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_NTFS_FS=m
-+CONFIG_NTFS_RW=y
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_ECRYPT_FS=m
-+CONFIG_HFS_FS=m
-+CONFIG_HFSPLUS_FS=m
-+CONFIG_JFFS2_FS=m
-+CONFIG_JFFS2_SUMMARY=y
-+CONFIG_UBIFS_FS=m
-+CONFIG_SQUASHFS=m
-+CONFIG_SQUASHFS_XATTR=y
-+CONFIG_SQUASHFS_LZO=y
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_NFS_SWAP=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3_ACL=y
-+CONFIG_NFSD_V4=y
-+CONFIG_CIFS=m
-+CONFIG_CIFS_WEAK_PW_HASH=y
-+CONFIG_CIFS_UPCALL=y
-+CONFIG_CIFS_XATTR=y
-+CONFIG_CIFS_POSIX=y
-+CONFIG_CIFS_ACL=y
-+CONFIG_CIFS_DFS_UPCALL=y
-+CONFIG_CIFS_FSCACHE=y
-+CONFIG_9P_FS=m
-+CONFIG_9P_FS_POSIX_ACL=y
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=m
-+CONFIG_NLS_CODEPAGE_775=m
-+CONFIG_NLS_CODEPAGE_850=m
-+CONFIG_NLS_CODEPAGE_852=m
-+CONFIG_NLS_CODEPAGE_855=m
-+CONFIG_NLS_CODEPAGE_857=m
-+CONFIG_NLS_CODEPAGE_860=m
-+CONFIG_NLS_CODEPAGE_861=m
-+CONFIG_NLS_CODEPAGE_862=m
-+CONFIG_NLS_CODEPAGE_863=m
-+CONFIG_NLS_CODEPAGE_864=m
-+CONFIG_NLS_CODEPAGE_865=m
-+CONFIG_NLS_CODEPAGE_866=m
-+CONFIG_NLS_CODEPAGE_869=m
-+CONFIG_NLS_CODEPAGE_936=m
-+CONFIG_NLS_CODEPAGE_950=m
-+CONFIG_NLS_CODEPAGE_932=m
-+CONFIG_NLS_CODEPAGE_949=m
-+CONFIG_NLS_CODEPAGE_874=m
-+CONFIG_NLS_ISO8859_8=m
-+CONFIG_NLS_CODEPAGE_1250=m
-+CONFIG_NLS_CODEPAGE_1251=m
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=m
-+CONFIG_NLS_ISO8859_2=m
-+CONFIG_NLS_ISO8859_3=m
-+CONFIG_NLS_ISO8859_4=m
-+CONFIG_NLS_ISO8859_5=m
-+CONFIG_NLS_ISO8859_6=m
-+CONFIG_NLS_ISO8859_7=m
-+CONFIG_NLS_ISO8859_9=m
-+CONFIG_NLS_ISO8859_13=m
-+CONFIG_NLS_ISO8859_14=m
-+CONFIG_NLS_ISO8859_15=m
-+CONFIG_NLS_KOI8_R=m
-+CONFIG_NLS_KOI8_U=m
-+CONFIG_DLM=m
-+CONFIG_PRINTK_TIME=y
-+CONFIG_BOOT_PRINTK_DELAY=y
-+CONFIG_DEBUG_MEMORY_INIT=y
-+CONFIG_DETECT_HUNG_TASK=y
-+# CONFIG_RCU_TRACE is not set
-+CONFIG_LATENCYTOP=y
-+CONFIG_IRQSOFF_TRACER=y
-+CONFIG_SCHED_TRACER=y
-+CONFIG_STACK_TRACER=y
-+CONFIG_BLK_DEV_IO_TRACE=y
-+# CONFIG_UPROBE_EVENTS is not set
-+CONFIG_FUNCTION_PROFILER=y
-+CONFIG_KGDB=y
-+CONFIG_KGDB_KDB=y
-+CONFIG_KDB_KEYBOARD=y
-+CONFIG_CRYPTO_USER=m
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_CTS=m
-+CONFIG_CRYPTO_XTS=m
-+CONFIG_CRYPTO_XCBC=m
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_DES=y
-+CONFIG_CRYPTO_LZ4=m
-+CONFIG_CRYPTO_USER_API_SKCIPHER=m
-+# CONFIG_CRYPTO_HW is not set
-+CONFIG_ARM_CRYPTO=y
-+CONFIG_CRYPTO_SHA1_ARM_NEON=m
-+CONFIG_CRYPTO_AES_ARM=m
-+CONFIG_CRYPTO_AES_ARM_BS=m
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
---- /dev/null
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -0,0 +1,1344 @@
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_GENERIC_IRQ_DEBUGFS=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+CONFIG_TASKSTATS=y
-+CONFIG_TASK_DELAY_ACCT=y
-+CONFIG_TASK_XACCT=y
-+CONFIG_TASK_IO_ACCOUNTING=y
-+CONFIG_IKCONFIG=m
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_MEMCG=y
-+CONFIG_BLK_CGROUP=y
-+CONFIG_CGROUP_FREEZER=y
-+CONFIG_CGROUP_DEVICE=y
-+CONFIG_CGROUP_CPUACCT=y
-+CONFIG_NAMESPACES=y
-+CONFIG_USER_NS=y
-+CONFIG_SCHED_AUTOGROUP=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+CONFIG_JUMP_LABEL=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_BLK_DEV_THROTTLING=y
-+CONFIG_PARTITION_ADVANCED=y
-+CONFIG_MAC_PARTITION=y
-+CONFIG_CFQ_GROUP_IOSCHED=y
-+CONFIG_ARCH_MULTI_V6=y
-+# CONFIG_ARCH_MULTI_V7 is not set
-+CONFIG_ARCH_BCM=y
-+CONFIG_ARCH_BCM2835=y
-+# CONFIG_CACHE_L2X0 is not set
-+CONFIG_PREEMPT_VOLUNTARY=y
-+# CONFIG_CPU_SW_DOMAIN_PAN is not set
-+CONFIG_CLEANCACHE=y
-+CONFIG_FRONTSWAP=y
-+CONFIG_CMA=y
-+CONFIG_ZSMALLOC=m
-+CONFIG_PGTABLE_MAPPING=y
-+CONFIG_UACCESS_WITH_MEMCPY=y
-+CONFIG_SECCOMP=y
-+# CONFIG_ATAGS is not set
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_STAT=y
-+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_VFP=y
-+CONFIG_BINFMT_MISC=m
-+# CONFIG_SUSPEND is not set
-+CONFIG_PM=y
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM_USER=y
-+CONFIG_NET_KEY=m
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE_DEMUX=m
-+CONFIG_NET_IPGRE=m
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IP_PIMSM_V1=y
-+CONFIG_IP_PIMSM_V2=y
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+CONFIG_INET_IPCOMP=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+CONFIG_INET_DIAG=m
-+CONFIG_TCP_CONG_ADVANCED=y
-+CONFIG_TCP_CONG_BBR=m
-+CONFIG_IPV6=m
-+CONFIG_IPV6_ROUTER_PREF=y
-+CONFIG_IPV6_ROUTE_INFO=y
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+CONFIG_IPV6_SIT_6RD=y
-+CONFIG_IPV6_TUNNEL=m
-+CONFIG_IPV6_MULTIPLE_TABLES=y
-+CONFIG_IPV6_SUBTREES=y
-+CONFIG_IPV6_MROUTE=y
-+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IPV6_PIMSM_V2=y
-+CONFIG_NETFILTER=y
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_ZONES=y
-+CONFIG_NF_CONNTRACK_EVENTS=y
-+CONFIG_NF_CONNTRACK_TIMESTAMP=y
-+CONFIG_NF_CONNTRACK_AMANDA=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_H323=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-+CONFIG_NF_CONNTRACK_SNMP=m
-+CONFIG_NF_CONNTRACK_PPTP=m
-+CONFIG_NF_CONNTRACK_SANE=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CONNTRACK_TFTP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XT_SET=m
-+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-+CONFIG_NETFILTER_XT_TARGET_DSCP=m
-+CONFIG_NETFILTER_XT_TARGET_HMARK=m
-+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-+CONFIG_NETFILTER_XT_TARGET_LED=m
-+CONFIG_NETFILTER_XT_TARGET_LOG=m
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-+CONFIG_NETFILTER_XT_TARGET_TEE=m
-+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-+CONFIG_NETFILTER_XT_TARGET_TRACE=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_BPF=m
-+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_CPU=m
-+CONFIG_NETFILTER_XT_MATCH_DCCP=m
-+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-+CONFIG_NETFILTER_XT_MATCH_DSCP=m
-+CONFIG_NETFILTER_XT_MATCH_ESP=m
-+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_HELPER=m
-+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-+CONFIG_NETFILTER_XT_MATCH_IPVS=m
-+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_MAC=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-+CONFIG_NETFILTER_XT_MATCH_OSF=m
-+CONFIG_NETFILTER_XT_MATCH_OWNER=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-+CONFIG_NETFILTER_XT_MATCH_REALM=m
-+CONFIG_NETFILTER_XT_MATCH_RECENT=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-+CONFIG_NETFILTER_XT_MATCH_STRING=m
-+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_TIME=m
-+CONFIG_NETFILTER_XT_MATCH_U32=m
-+CONFIG_IP_SET=m
-+CONFIG_IP_SET_BITMAP_IP=m
-+CONFIG_IP_SET_BITMAP_IPMAC=m
-+CONFIG_IP_SET_BITMAP_PORT=m
-+CONFIG_IP_SET_HASH_IP=m
-+CONFIG_IP_SET_HASH_IPPORT=m
-+CONFIG_IP_SET_HASH_IPPORTIP=m
-+CONFIG_IP_SET_HASH_IPPORTNET=m
-+CONFIG_IP_SET_HASH_NET=m
-+CONFIG_IP_SET_HASH_NETPORT=m
-+CONFIG_IP_SET_HASH_NETIFACE=m
-+CONFIG_IP_SET_LIST_SET=m
-+CONFIG_IP_VS=m
-+CONFIG_IP_VS_PROTO_TCP=y
-+CONFIG_IP_VS_PROTO_UDP=y
-+CONFIG_IP_VS_PROTO_ESP=y
-+CONFIG_IP_VS_PROTO_AH=y
-+CONFIG_IP_VS_PROTO_SCTP=y
-+CONFIG_IP_VS_RR=m
-+CONFIG_IP_VS_WRR=m
-+CONFIG_IP_VS_LC=m
-+CONFIG_IP_VS_WLC=m
-+CONFIG_IP_VS_LBLC=m
-+CONFIG_IP_VS_LBLCR=m
-+CONFIG_IP_VS_DH=m
-+CONFIG_IP_VS_SH=m
-+CONFIG_IP_VS_SED=m
-+CONFIG_IP_VS_NQ=m
-+CONFIG_IP_VS_FTP=m
-+CONFIG_IP_VS_PE_SIP=m
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_MATCH_AH=m
-+CONFIG_IP_NF_MATCH_ECN=m
-+CONFIG_IP_NF_MATCH_RPFILTER=m
-+CONFIG_IP_NF_MATCH_TTL=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_NAT=m
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_IP_NF_TARGET_NETMAP=m
-+CONFIG_IP_NF_TARGET_REDIRECT=m
-+CONFIG_IP_NF_MANGLE=m
-+CONFIG_IP_NF_TARGET_CLUSTERIP=m
-+CONFIG_IP_NF_TARGET_ECN=m
-+CONFIG_IP_NF_TARGET_TTL=m
-+CONFIG_IP_NF_RAW=m
-+CONFIG_IP_NF_ARPTABLES=m
-+CONFIG_IP_NF_ARPFILTER=m
-+CONFIG_IP_NF_ARP_MANGLE=m
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_AH=m
-+CONFIG_IP6_NF_MATCH_EUI64=m
-+CONFIG_IP6_NF_MATCH_FRAG=m
-+CONFIG_IP6_NF_MATCH_OPTS=m
-+CONFIG_IP6_NF_MATCH_HL=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_MATCH_MH=m
-+CONFIG_IP6_NF_MATCH_RPFILTER=m
-+CONFIG_IP6_NF_MATCH_RT=m
-+CONFIG_IP6_NF_TARGET_HL=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+CONFIG_IP6_NF_RAW=m
-+CONFIG_IP6_NF_NAT=m
-+CONFIG_IP6_NF_TARGET_MASQUERADE=m
-+CONFIG_IP6_NF_TARGET_NPT=m
-+CONFIG_BRIDGE_NF_EBTABLES=m
-+CONFIG_BRIDGE_EBT_BROUTE=m
-+CONFIG_BRIDGE_EBT_T_FILTER=m
-+CONFIG_BRIDGE_EBT_T_NAT=m
-+CONFIG_BRIDGE_EBT_802_3=m
-+CONFIG_BRIDGE_EBT_AMONG=m
-+CONFIG_BRIDGE_EBT_ARP=m
-+CONFIG_BRIDGE_EBT_IP=m
-+CONFIG_BRIDGE_EBT_IP6=m
-+CONFIG_BRIDGE_EBT_LIMIT=m
-+CONFIG_BRIDGE_EBT_MARK=m
-+CONFIG_BRIDGE_EBT_PKTTYPE=m
-+CONFIG_BRIDGE_EBT_STP=m
-+CONFIG_BRIDGE_EBT_VLAN=m
-+CONFIG_BRIDGE_EBT_ARPREPLY=m
-+CONFIG_BRIDGE_EBT_DNAT=m
-+CONFIG_BRIDGE_EBT_MARK_T=m
-+CONFIG_BRIDGE_EBT_REDIRECT=m
-+CONFIG_BRIDGE_EBT_SNAT=m
-+CONFIG_BRIDGE_EBT_LOG=m
-+CONFIG_BRIDGE_EBT_NFLOG=m
-+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-+CONFIG_ATM=m
-+CONFIG_L2TP=m
-+CONFIG_L2TP_V3=y
-+CONFIG_L2TP_IP=m
-+CONFIG_L2TP_ETH=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+CONFIG_VLAN_8021Q_GVRP=y
-+CONFIG_ATALK=m
-+CONFIG_6LOWPAN=m
-+CONFIG_IEEE802154=m
-+CONFIG_IEEE802154_6LOWPAN=m
-+CONFIG_MAC802154=m
-+CONFIG_NET_SCHED=y
-+CONFIG_NET_SCH_CBQ=m
-+CONFIG_NET_SCH_HTB=m
-+CONFIG_NET_SCH_HFSC=m
-+CONFIG_NET_SCH_ATM=m
-+CONFIG_NET_SCH_PRIO=m
-+CONFIG_NET_SCH_MULTIQ=m
-+CONFIG_NET_SCH_RED=m
-+CONFIG_NET_SCH_SFB=m
-+CONFIG_NET_SCH_SFQ=m
-+CONFIG_NET_SCH_TEQL=m
-+CONFIG_NET_SCH_TBF=m
-+CONFIG_NET_SCH_GRED=m
-+CONFIG_NET_SCH_DSMARK=m
-+CONFIG_NET_SCH_NETEM=m
-+CONFIG_NET_SCH_DRR=m
-+CONFIG_NET_SCH_MQPRIO=m
-+CONFIG_NET_SCH_CHOKE=m
-+CONFIG_NET_SCH_QFQ=m
-+CONFIG_NET_SCH_CODEL=m
-+CONFIG_NET_SCH_FQ_CODEL=m
-+CONFIG_NET_SCH_FQ=m
-+CONFIG_NET_SCH_HHF=m
-+CONFIG_NET_SCH_PIE=m
-+CONFIG_NET_SCH_INGRESS=m
-+CONFIG_NET_SCH_PLUG=m
-+CONFIG_NET_CLS_BASIC=m
-+CONFIG_NET_CLS_TCINDEX=m
-+CONFIG_NET_CLS_ROUTE4=m
-+CONFIG_NET_CLS_FW=m
-+CONFIG_NET_CLS_U32=m
-+CONFIG_CLS_U32_MARK=y
-+CONFIG_NET_CLS_RSVP=m
-+CONFIG_NET_CLS_RSVP6=m
-+CONFIG_NET_CLS_FLOW=m
-+CONFIG_NET_CLS_CGROUP=m
-+CONFIG_NET_EMATCH=y
-+CONFIG_NET_EMATCH_CMP=m
-+CONFIG_NET_EMATCH_NBYTE=m
-+CONFIG_NET_EMATCH_U32=m
-+CONFIG_NET_EMATCH_META=m
-+CONFIG_NET_EMATCH_TEXT=m
-+CONFIG_NET_EMATCH_IPSET=m
-+CONFIG_NET_CLS_ACT=y
-+CONFIG_NET_ACT_POLICE=m
-+CONFIG_NET_ACT_GACT=m
-+CONFIG_GACT_PROB=y
-+CONFIG_NET_ACT_MIRRED=m
-+CONFIG_NET_ACT_IPT=m
-+CONFIG_NET_ACT_NAT=m
-+CONFIG_NET_ACT_PEDIT=m
-+CONFIG_NET_ACT_SIMP=m
-+CONFIG_NET_ACT_SKBEDIT=m
-+CONFIG_NET_ACT_CSUM=m
-+CONFIG_BATMAN_ADV=m
-+CONFIG_OPENVSWITCH=m
-+CONFIG_NET_PKTGEN=m
-+CONFIG_HAMRADIO=y
-+CONFIG_AX25=m
-+CONFIG_NETROM=m
-+CONFIG_ROSE=m
-+CONFIG_MKISS=m
-+CONFIG_6PACK=m
-+CONFIG_BPQETHER=m
-+CONFIG_BAYCOM_SER_FDX=m
-+CONFIG_BAYCOM_SER_HDX=m
-+CONFIG_YAM=m
-+CONFIG_CAN=m
-+CONFIG_CAN_VCAN=m
-+CONFIG_CAN_SLCAN=m
-+CONFIG_CAN_MCP251X=m
-+CONFIG_CAN_GS_USB=m
-+CONFIG_BT=m
-+CONFIG_BT_RFCOMM=m
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=m
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=m
-+CONFIG_BT_6LOWPAN=m
-+CONFIG_BT_HCIBTUSB=m
-+CONFIG_BT_HCIUART=m
-+CONFIG_BT_HCIUART_3WIRE=y
-+CONFIG_BT_HCIBCM203X=m
-+CONFIG_BT_HCIBPA10X=m
-+CONFIG_BT_HCIBFUSB=m
-+CONFIG_BT_HCIVHCI=m
-+CONFIG_BT_MRVL=m
-+CONFIG_BT_MRVL_SDIO=m
-+CONFIG_BT_ATH3K=m
-+CONFIG_BT_WILINK=m
-+CONFIG_CFG80211=m
-+CONFIG_MAC80211=m
-+CONFIG_MAC80211_MESH=y
-+CONFIG_WIMAX=m
-+CONFIG_RFKILL=m
-+CONFIG_RFKILL_INPUT=y
-+CONFIG_NET_9P=m
-+CONFIG_NFC=m
-+CONFIG_DEVTMPFS=y
-+CONFIG_DEVTMPFS_MOUNT=y
-+CONFIG_DMA_CMA=y
-+CONFIG_CMA_SIZE_MBYTES=5
-+CONFIG_MTD=m
-+CONFIG_MTD_BLOCK=m
-+CONFIG_MTD_M25P80=m
-+CONFIG_MTD_NAND=m
-+CONFIG_MTD_SPI_NOR=m
-+CONFIG_MTD_UBI=m
-+CONFIG_OF_CONFIGFS=y
-+CONFIG_ZRAM=m
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+CONFIG_BLK_DEV_DRBD=m
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_ATA_OVER_ETH=m
-+CONFIG_EEPROM_AT24=m
-+CONFIG_TI_ST=m
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_CHR_DEV_ST=m
-+CONFIG_CHR_DEV_OSST=m
-+CONFIG_BLK_DEV_SR=m
-+CONFIG_CHR_DEV_SG=m
-+CONFIG_SCSI_ISCSI_ATTRS=y
-+CONFIG_ISCSI_TCP=m
-+CONFIG_ISCSI_BOOT_SYSFS=m
-+CONFIG_MD=y
-+CONFIG_MD_LINEAR=m
-+CONFIG_BLK_DEV_DM=m
-+CONFIG_DM_CRYPT=m
-+CONFIG_DM_SNAPSHOT=m
-+CONFIG_DM_THIN_PROVISIONING=m
-+CONFIG_DM_MIRROR=m
-+CONFIG_DM_LOG_USERSPACE=m
-+CONFIG_DM_RAID=m
-+CONFIG_DM_ZERO=m
-+CONFIG_DM_DELAY=m
-+CONFIG_NETDEVICES=y
-+CONFIG_BONDING=m
-+CONFIG_DUMMY=m
-+CONFIG_IFB=m
-+CONFIG_MACVLAN=m
-+CONFIG_VXLAN=m
-+CONFIG_NETCONSOLE=m
-+CONFIG_TUN=m
-+CONFIG_VETH=m
-+CONFIG_ENC28J60=m
-+CONFIG_MDIO_BITBANG=m
-+CONFIG_PPP=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPP_MULTILINK=y
-+CONFIG_PPPOATM=m
-+CONFIG_PPPOE=m
-+CONFIG_PPPOL2TP=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_SLIP=m
-+CONFIG_SLIP_COMPRESSED=y
-+CONFIG_SLIP_SMART=y
-+CONFIG_USB_CATC=m
-+CONFIG_USB_KAWETH=m
-+CONFIG_USB_PEGASUS=m
-+CONFIG_USB_RTL8150=m
-+CONFIG_USB_RTL8152=m
-+CONFIG_USB_LAN78XX=m
-+CONFIG_USB_USBNET=y
-+CONFIG_USB_NET_AX8817X=m
-+CONFIG_USB_NET_AX88179_178A=m
-+CONFIG_USB_NET_CDCETHER=m
-+CONFIG_USB_NET_CDC_EEM=m
-+CONFIG_USB_NET_CDC_NCM=m
-+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-+CONFIG_USB_NET_CDC_MBIM=m
-+CONFIG_USB_NET_DM9601=m
-+CONFIG_USB_NET_SR9700=m
-+CONFIG_USB_NET_SR9800=m
-+CONFIG_USB_NET_SMSC75XX=m
-+CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_NET_GL620A=m
-+CONFIG_USB_NET_NET1080=m
-+CONFIG_USB_NET_PLUSB=m
-+CONFIG_USB_NET_MCS7830=m
-+CONFIG_USB_NET_CDC_SUBSET=m
-+CONFIG_USB_ALI_M5632=y
-+CONFIG_USB_AN2720=y
-+CONFIG_USB_EPSON2888=y
-+CONFIG_USB_KC2190=y
-+CONFIG_USB_NET_ZAURUS=m
-+CONFIG_USB_NET_CX82310_ETH=m
-+CONFIG_USB_NET_KALMIA=m
-+CONFIG_USB_NET_QMI_WWAN=m
-+CONFIG_USB_HSO=m
-+CONFIG_USB_NET_INT51X1=m
-+CONFIG_USB_IPHETH=m
-+CONFIG_USB_SIERRA_NET=m
-+CONFIG_USB_VL600=m
-+CONFIG_ATH9K=m
-+CONFIG_ATH9K_HTC=m
-+CONFIG_CARL9170=m
-+CONFIG_ATH6KL=m
-+CONFIG_ATH6KL_USB=m
-+CONFIG_AR5523=m
-+CONFIG_AT76C50X_USB=m
-+CONFIG_B43=m
-+# CONFIG_B43_PHY_N is not set
-+CONFIG_B43LEGACY=m
-+CONFIG_BRCMFMAC=m
-+CONFIG_BRCMFMAC_USB=y
-+CONFIG_BRCMDBG=y
-+CONFIG_HOSTAP=m
-+CONFIG_P54_COMMON=m
-+CONFIG_P54_USB=m
-+CONFIG_LIBERTAS=m
-+CONFIG_LIBERTAS_USB=m
-+CONFIG_LIBERTAS_SDIO=m
-+CONFIG_LIBERTAS_THINFIRM=m
-+CONFIG_LIBERTAS_THINFIRM_USB=m
-+CONFIG_MWIFIEX=m
-+CONFIG_MWIFIEX_SDIO=m
-+CONFIG_MT7601U=m
-+CONFIG_RT2X00=m
-+CONFIG_RT2500USB=m
-+CONFIG_RT73USB=m
-+CONFIG_RT2800USB=m
-+CONFIG_RT2800USB_RT3573=y
-+CONFIG_RT2800USB_RT53XX=y
-+CONFIG_RT2800USB_RT55XX=y
-+CONFIG_RT2800USB_UNKNOWN=y
-+CONFIG_RTL8187=m
-+CONFIG_RTL8192CU=m
-+CONFIG_RTL8XXXU=m
-+CONFIG_USB_ZD1201=m
-+CONFIG_ZD1211RW=m
-+CONFIG_MAC80211_HWSIM=m
-+CONFIG_USB_NET_RNDIS_WLAN=m
-+CONFIG_WIMAX_I2400M_USB=m
-+CONFIG_IEEE802154_AT86RF230=m
-+CONFIG_IEEE802154_MRF24J40=m
-+CONFIG_IEEE802154_CC2520=m
-+CONFIG_INPUT_MOUSEDEV=y
-+CONFIG_INPUT_JOYDEV=m
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_KEYBOARD_ATKBD is not set
-+CONFIG_KEYBOARD_GPIO=m
-+# CONFIG_INPUT_MOUSE is not set
-+CONFIG_INPUT_JOYSTICK=y
-+CONFIG_JOYSTICK_IFORCE=m
-+CONFIG_JOYSTICK_IFORCE_USB=y
-+CONFIG_JOYSTICK_XPAD=m
-+CONFIG_JOYSTICK_XPAD_FF=y
-+CONFIG_JOYSTICK_XPAD_LEDS=y
-+CONFIG_JOYSTICK_PSXPAD_SPI=m
-+CONFIG_JOYSTICK_PSXPAD_SPI_FF=y
-+CONFIG_JOYSTICK_RPISENSE=m
-+CONFIG_INPUT_TOUCHSCREEN=y
-+CONFIG_TOUCHSCREEN_ADS7846=m
-+CONFIG_TOUCHSCREEN_EGALAX=m
-+CONFIG_TOUCHSCREEN_GOODIX=m
-+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
-+CONFIG_TOUCHSCREEN_RPI_FT5406=m
-+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-+CONFIG_TOUCHSCREEN_STMPE=m
-+CONFIG_INPUT_MISC=y
-+CONFIG_INPUT_AD714X=m
-+CONFIG_INPUT_ATI_REMOTE2=m
-+CONFIG_INPUT_KEYSPAN_REMOTE=m
-+CONFIG_INPUT_POWERMATE=m
-+CONFIG_INPUT_YEALINK=m
-+CONFIG_INPUT_CM109=m
-+CONFIG_INPUT_UINPUT=m
-+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-+CONFIG_INPUT_ADXL34X=m
-+CONFIG_INPUT_CMA3000=m
-+CONFIG_SERIO=m
-+CONFIG_SERIO_RAW=m
-+CONFIG_GAMEPORT=m
-+CONFIG_GAMEPORT_NS558=m
-+CONFIG_GAMEPORT_L4=m
-+CONFIG_BRCM_CHAR_DRIVERS=y
-+CONFIG_BCM_VCIO=y
-+CONFIG_BCM_VC_SM=y
-+CONFIG_BCM2835_DEVGPIOMEM=y
-+# CONFIG_LEGACY_PTYS is not set
-+CONFIG_SERIAL_8250=y
-+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-+CONFIG_SERIAL_8250_CONSOLE=y
-+# CONFIG_SERIAL_8250_DMA is not set
-+CONFIG_SERIAL_8250_NR_UARTS=1
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=0
-+CONFIG_SERIAL_8250_EXTENDED=y
-+CONFIG_SERIAL_8250_SHARE_IRQ=y
-+CONFIG_SERIAL_8250_BCM2835AUX=y
-+CONFIG_SERIAL_OF_PLATFORM=y
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+CONFIG_SERIAL_SC16IS7XX=m
-+CONFIG_SERIAL_SC16IS7XX_SPI=y
-+CONFIG_TTY_PRINTK=y
-+CONFIG_HW_RANDOM=y
-+CONFIG_RAW_DRIVER=y
-+CONFIG_I2C=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_MUX_GPMUX=m
-+CONFIG_I2C_MUX_PCA954x=m
-+CONFIG_I2C_BCM2708=m
-+CONFIG_I2C_BCM2835=m
-+CONFIG_I2C_GPIO=m
-+CONFIG_I2C_ROBOTFUZZ_OSIF=m
-+CONFIG_SPI=y
-+CONFIG_SPI_BCM2835=m
-+CONFIG_SPI_BCM2835AUX=m
-+CONFIG_SPI_SPIDEV=m
-+CONFIG_SPI_SLAVE=y
-+CONFIG_PPS=m
-+CONFIG_PPS_CLIENT_LDISC=m
-+CONFIG_PPS_CLIENT_GPIO=m
-+CONFIG_GPIO_SYSFS=y
-+CONFIG_GPIO_PCF857X=m
-+CONFIG_GPIO_ARIZONA=m
-+CONFIG_GPIO_STMPE=y
-+CONFIG_W1=m
-+CONFIG_W1_MASTER_DS2490=m
-+CONFIG_W1_MASTER_DS2482=m
-+CONFIG_W1_MASTER_DS1WM=m
-+CONFIG_W1_MASTER_GPIO=m
-+CONFIG_W1_SLAVE_THERM=m
-+CONFIG_W1_SLAVE_SMEM=m
-+CONFIG_W1_SLAVE_DS2408=m
-+CONFIG_W1_SLAVE_DS2413=m
-+CONFIG_W1_SLAVE_DS2406=m
-+CONFIG_W1_SLAVE_DS2423=m
-+CONFIG_W1_SLAVE_DS2431=m
-+CONFIG_W1_SLAVE_DS2433=m
-+CONFIG_W1_SLAVE_DS2438=m
-+CONFIG_W1_SLAVE_DS2760=m
-+CONFIG_W1_SLAVE_DS2780=m
-+CONFIG_W1_SLAVE_DS2781=m
-+CONFIG_W1_SLAVE_DS28E04=m
-+CONFIG_POWER_RESET=y
-+CONFIG_POWER_RESET_GPIO=y
-+CONFIG_BATTERY_DS2760=m
-+CONFIG_HWMON=m
-+CONFIG_SENSORS_JC42=m
-+CONFIG_SENSORS_LM75=m
-+CONFIG_SENSORS_SHT21=m
-+CONFIG_SENSORS_SHT3x=m
-+CONFIG_SENSORS_SHTC1=m
-+CONFIG_SENSORS_ADS1015=m
-+CONFIG_SENSORS_INA2XX=m
-+CONFIG_SENSORS_TMP102=m
-+CONFIG_THERMAL=y
-+CONFIG_BCM2835_THERMAL=y
-+CONFIG_WATCHDOG=y
-+CONFIG_GPIO_WATCHDOG=m
-+CONFIG_BCM2835_WDT=y
-+CONFIG_MFD_STMPE=y
-+CONFIG_STMPE_SPI=y
-+CONFIG_MFD_ARIZONA_I2C=m
-+CONFIG_MFD_ARIZONA_SPI=m
-+CONFIG_MFD_WM5102=y
-+CONFIG_REGULATOR=y
-+CONFIG_REGULATOR_FIXED_VOLTAGE=m
-+CONFIG_REGULATOR_ARIZONA_LDO1=m
-+CONFIG_REGULATOR_ARIZONA_MICSUPP=m
-+CONFIG_LIRC=m
-+CONFIG_RC_DEVICES=y
-+CONFIG_RC_ATI_REMOTE=m
-+CONFIG_IR_IMON=m
-+CONFIG_IR_MCEUSB=m
-+CONFIG_IR_REDRAT3=m
-+CONFIG_IR_STREAMZAP=m
-+CONFIG_IR_IGUANA=m
-+CONFIG_IR_TTUSBIR=m
-+CONFIG_RC_LOOPBACK=m
-+CONFIG_IR_GPIO_CIR=m
-+CONFIG_IR_GPIO_TX=m
-+CONFIG_IR_PWM_TX=m
-+CONFIG_MEDIA_SUPPORT=m
-+CONFIG_MEDIA_CAMERA_SUPPORT=y
-+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-+CONFIG_MEDIA_RADIO_SUPPORT=y
-+CONFIG_MEDIA_CONTROLLER=y
-+CONFIG_MEDIA_USB_SUPPORT=y
-+CONFIG_USB_VIDEO_CLASS=m
-+CONFIG_USB_M5602=m
-+CONFIG_USB_STV06XX=m
-+CONFIG_USB_GL860=m
-+CONFIG_USB_GSPCA_BENQ=m
-+CONFIG_USB_GSPCA_CONEX=m
-+CONFIG_USB_GSPCA_CPIA1=m
-+CONFIG_USB_GSPCA_DTCS033=m
-+CONFIG_USB_GSPCA_ETOMS=m
-+CONFIG_USB_GSPCA_FINEPIX=m
-+CONFIG_USB_GSPCA_JEILINJ=m
-+CONFIG_USB_GSPCA_JL2005BCD=m
-+CONFIG_USB_GSPCA_KINECT=m
-+CONFIG_USB_GSPCA_KONICA=m
-+CONFIG_USB_GSPCA_MARS=m
-+CONFIG_USB_GSPCA_MR97310A=m
-+CONFIG_USB_GSPCA_NW80X=m
-+CONFIG_USB_GSPCA_OV519=m
-+CONFIG_USB_GSPCA_OV534=m
-+CONFIG_USB_GSPCA_OV534_9=m
-+CONFIG_USB_GSPCA_PAC207=m
-+CONFIG_USB_GSPCA_PAC7302=m
-+CONFIG_USB_GSPCA_PAC7311=m
-+CONFIG_USB_GSPCA_SE401=m
-+CONFIG_USB_GSPCA_SN9C2028=m
-+CONFIG_USB_GSPCA_SN9C20X=m
-+CONFIG_USB_GSPCA_SONIXB=m
-+CONFIG_USB_GSPCA_SONIXJ=m
-+CONFIG_USB_GSPCA_SPCA500=m
-+CONFIG_USB_GSPCA_SPCA501=m
-+CONFIG_USB_GSPCA_SPCA505=m
-+CONFIG_USB_GSPCA_SPCA506=m
-+CONFIG_USB_GSPCA_SPCA508=m
-+CONFIG_USB_GSPCA_SPCA561=m
-+CONFIG_USB_GSPCA_SPCA1528=m
-+CONFIG_USB_GSPCA_SQ905=m
-+CONFIG_USB_GSPCA_SQ905C=m
-+CONFIG_USB_GSPCA_SQ930X=m
-+CONFIG_USB_GSPCA_STK014=m
-+CONFIG_USB_GSPCA_STK1135=m
-+CONFIG_USB_GSPCA_STV0680=m
-+CONFIG_USB_GSPCA_SUNPLUS=m
-+CONFIG_USB_GSPCA_T613=m
-+CONFIG_USB_GSPCA_TOPRO=m
-+CONFIG_USB_GSPCA_TV8532=m
-+CONFIG_USB_GSPCA_VC032X=m
-+CONFIG_USB_GSPCA_VICAM=m
-+CONFIG_USB_GSPCA_XIRLINK_CIT=m
-+CONFIG_USB_GSPCA_ZC3XX=m
-+CONFIG_USB_PWC=m
-+CONFIG_VIDEO_CPIA2=m
-+CONFIG_USB_ZR364XX=m
-+CONFIG_USB_STKWEBCAM=m
-+CONFIG_USB_S2255=m
-+CONFIG_VIDEO_USBTV=m
-+CONFIG_VIDEO_PVRUSB2=m
-+CONFIG_VIDEO_HDPVR=m
-+CONFIG_VIDEO_USBVISION=m
-+CONFIG_VIDEO_STK1160_COMMON=m
-+CONFIG_VIDEO_GO7007=m
-+CONFIG_VIDEO_GO7007_USB=m
-+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-+CONFIG_VIDEO_AU0828=m
-+CONFIG_VIDEO_AU0828_RC=y
-+CONFIG_VIDEO_CX231XX=m
-+CONFIG_VIDEO_CX231XX_ALSA=m
-+CONFIG_VIDEO_CX231XX_DVB=m
-+CONFIG_VIDEO_TM6000=m
-+CONFIG_VIDEO_TM6000_ALSA=m
-+CONFIG_VIDEO_TM6000_DVB=m
-+CONFIG_DVB_USB=m
-+CONFIG_DVB_USB_A800=m
-+CONFIG_DVB_USB_DIBUSB_MB=m
-+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-+CONFIG_DVB_USB_DIBUSB_MC=m
-+CONFIG_DVB_USB_DIB0700=m
-+CONFIG_DVB_USB_UMT_010=m
-+CONFIG_DVB_USB_CXUSB=m
-+CONFIG_DVB_USB_M920X=m
-+CONFIG_DVB_USB_DIGITV=m
-+CONFIG_DVB_USB_VP7045=m
-+CONFIG_DVB_USB_VP702X=m
-+CONFIG_DVB_USB_GP8PSK=m
-+CONFIG_DVB_USB_NOVA_T_USB2=m
-+CONFIG_DVB_USB_TTUSB2=m
-+CONFIG_DVB_USB_DTT200U=m
-+CONFIG_DVB_USB_OPERA1=m
-+CONFIG_DVB_USB_AF9005=m
-+CONFIG_DVB_USB_AF9005_REMOTE=m
-+CONFIG_DVB_USB_PCTV452E=m
-+CONFIG_DVB_USB_DW2102=m
-+CONFIG_DVB_USB_CINERGY_T2=m
-+CONFIG_DVB_USB_DTV5100=m
-+CONFIG_DVB_USB_FRIIO=m
-+CONFIG_DVB_USB_AZ6027=m
-+CONFIG_DVB_USB_TECHNISAT_USB2=m
-+CONFIG_DVB_USB_V2=m
-+CONFIG_DVB_USB_AF9015=m
-+CONFIG_DVB_USB_AF9035=m
-+CONFIG_DVB_USB_ANYSEE=m
-+CONFIG_DVB_USB_AU6610=m
-+CONFIG_DVB_USB_AZ6007=m
-+CONFIG_DVB_USB_CE6230=m
-+CONFIG_DVB_USB_EC168=m
-+CONFIG_DVB_USB_GL861=m
-+CONFIG_DVB_USB_LME2510=m
-+CONFIG_DVB_USB_MXL111SF=m
-+CONFIG_DVB_USB_RTL28XXU=m
-+CONFIG_DVB_USB_DVBSKY=m
-+CONFIG_SMS_USB_DRV=m
-+CONFIG_DVB_B2C2_FLEXCOP_USB=m
-+CONFIG_DVB_AS102=m
-+CONFIG_VIDEO_EM28XX=m
-+CONFIG_VIDEO_EM28XX_V4L2=m
-+CONFIG_VIDEO_EM28XX_ALSA=m
-+CONFIG_VIDEO_EM28XX_DVB=m
-+CONFIG_V4L_PLATFORM_DRIVERS=y
-+CONFIG_RADIO_SI470X=y
-+CONFIG_USB_SI470X=m
-+CONFIG_I2C_SI470X=m
-+CONFIG_RADIO_SI4713=m
-+CONFIG_I2C_SI4713=m
-+CONFIG_USB_MR800=m
-+CONFIG_USB_DSBR=m
-+CONFIG_RADIO_SHARK=m
-+CONFIG_RADIO_SHARK2=m
-+CONFIG_USB_KEENE=m
-+CONFIG_USB_MA901=m
-+CONFIG_RADIO_TEA5764=m
-+CONFIG_RADIO_SAA7706H=m
-+CONFIG_RADIO_TEF6862=m
-+CONFIG_RADIO_WL1273=m
-+CONFIG_RADIO_WL128X=m
-+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
-+CONFIG_VIDEO_UDA1342=m
-+CONFIG_VIDEO_SONY_BTF_MPX=m
-+CONFIG_VIDEO_TVP5150=m
-+CONFIG_VIDEO_TW2804=m
-+CONFIG_VIDEO_TW9903=m
-+CONFIG_VIDEO_TW9906=m
-+CONFIG_VIDEO_OV7640=m
-+CONFIG_VIDEO_MT9V011=m
-+CONFIG_DRM=m
-+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-+CONFIG_DRM_UDL=m
-+CONFIG_DRM_PANEL_SIMPLE=m
-+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
-+CONFIG_DRM_VC4=m
-+CONFIG_DRM_TINYDRM=m
-+CONFIG_TINYDRM_MI0283QT=m
-+CONFIG_TINYDRM_REPAPER=m
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+CONFIG_FB_UDL=m
-+CONFIG_FB_SSD1307=m
-+CONFIG_FB_RPISENSE=m
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+CONFIG_BACKLIGHT_RPI=m
-+CONFIG_BACKLIGHT_GPIO=m
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=m
-+CONFIG_SND_HRTIMER=m
-+CONFIG_SND_SEQUENCER=m
-+CONFIG_SND_SEQ_DUMMY=m
-+CONFIG_SND_DUMMY=m
-+CONFIG_SND_ALOOP=m
-+CONFIG_SND_VIRMIDI=m
-+CONFIG_SND_MTPAV=m
-+CONFIG_SND_SERIAL_U16550=m
-+CONFIG_SND_MPU401=m
-+CONFIG_SND_USB_AUDIO=m
-+CONFIG_SND_USB_UA101=m
-+CONFIG_SND_USB_CAIAQ=m
-+CONFIG_SND_USB_CAIAQ_INPUT=y
-+CONFIG_SND_USB_6FIRE=m
-+CONFIG_SND_SOC=m
-+CONFIG_SND_BCM2835_SOC_I2S=m
-+CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
-+CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m
-+CONFIG_SND_BCM2708_SOC_RPI_DAC=m
-+CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
-+CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m
-+CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m
-+CONFIG_SND_BCM2708_SOC_RASPIDAC3=m
-+CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m
-+CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m
-+CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m
-+CONFIG_SND_DIGIDAC1_SOUNDCARD=m
-+CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m
-+CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m
-+CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m
-+CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m
-+CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m
-+CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m
-+CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m
-+CONFIG_SND_PISOUND=m
-+CONFIG_SND_SOC_ADAU1701=m
-+CONFIG_SND_SOC_ADAU7002=m
-+CONFIG_SND_SOC_AK4554=m
-+CONFIG_SND_SOC_SPDIF=m
-+CONFIG_SND_SOC_WM8804_I2C=m
-+CONFIG_SND_SIMPLE_CARD=m
-+CONFIG_HID_BATTERY_STRENGTH=y
-+CONFIG_HIDRAW=y
-+CONFIG_UHID=m
-+CONFIG_HID_A4TECH=m
-+CONFIG_HID_ACRUX=m
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_ASUS=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_BETOP_FF=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+CONFIG_HID_CYPRESS=m
-+CONFIG_HID_DRAGONRISE=m
-+CONFIG_HID_EMS_FF=m
-+CONFIG_HID_ELECOM=m
-+CONFIG_HID_ELO=m
-+CONFIG_HID_EZKEY=m
-+CONFIG_HID_GEMBIRD=m
-+CONFIG_HID_HOLTEK=m
-+CONFIG_HID_KEYTOUCH=m
-+CONFIG_HID_KYE=m
-+CONFIG_HID_UCLOGIC=m
-+CONFIG_HID_WALTOP=m
-+CONFIG_HID_GYRATION=m
-+CONFIG_HID_TWINHAN=m
-+CONFIG_HID_KENSINGTON=m
-+CONFIG_HID_LCPOWER=m
-+CONFIG_HID_LOGITECH=m
-+CONFIG_HID_LOGITECH_DJ=m
-+CONFIG_LOGITECH_FF=y
-+CONFIG_LOGIRUMBLEPAD2_FF=y
-+CONFIG_LOGIG940_FF=y
-+CONFIG_HID_MAGICMOUSE=m
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+CONFIG_HID_MULTITOUCH=m
-+CONFIG_HID_NTRIG=m
-+CONFIG_HID_ORTEK=m
-+CONFIG_HID_PANTHERLORD=m
-+CONFIG_HID_PETALYNX=m
-+CONFIG_HID_PICOLCD=m
-+CONFIG_HID_ROCCAT=m
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SONY=m
-+CONFIG_SONY_FF=y
-+CONFIG_HID_SPEEDLINK=m
-+CONFIG_HID_SUNPLUS=m
-+CONFIG_HID_GREENASIA=m
-+CONFIG_HID_SMARTJOYPLUS=m
-+CONFIG_HID_TOPSEED=m
-+CONFIG_HID_THINGM=m
-+CONFIG_HID_THRUSTMASTER=m
-+CONFIG_HID_WACOM=m
-+CONFIG_HID_WIIMOTE=m
-+CONFIG_HID_XINMO=m
-+CONFIG_HID_ZEROPLUS=m
-+CONFIG_HID_ZYDACRON=m
-+CONFIG_HID_PID=y
-+CONFIG_USB_HIDDEV=y
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=y
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_REALTEK=m
-+CONFIG_USB_STORAGE_DATAFAB=m
-+CONFIG_USB_STORAGE_FREECOM=m
-+CONFIG_USB_STORAGE_ISD200=m
-+CONFIG_USB_STORAGE_USBAT=m
-+CONFIG_USB_STORAGE_SDDR09=m
-+CONFIG_USB_STORAGE_SDDR55=m
-+CONFIG_USB_STORAGE_JUMPSHOT=m
-+CONFIG_USB_STORAGE_ALAUDA=m
-+CONFIG_USB_STORAGE_ONETOUCH=m
-+CONFIG_USB_STORAGE_KARMA=m
-+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-+CONFIG_USB_STORAGE_ENE_UB6250=m
-+CONFIG_USB_MDC800=m
-+CONFIG_USB_MICROTEK=m
-+CONFIG_USBIP_CORE=m
-+CONFIG_USBIP_VHCI_HCD=m
-+CONFIG_USBIP_HOST=m
-+CONFIG_USB_DWC2=m
-+CONFIG_USB_SERIAL=m
-+CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRCABLE=m
-+CONFIG_USB_SERIAL_ARK3116=m
-+CONFIG_USB_SERIAL_BELKIN=m
-+CONFIG_USB_SERIAL_CH341=m
-+CONFIG_USB_SERIAL_WHITEHEAT=m
-+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+CONFIG_USB_SERIAL_CP210X=m
-+CONFIG_USB_SERIAL_CYPRESS_M8=m
-+CONFIG_USB_SERIAL_EMPEG=m
-+CONFIG_USB_SERIAL_FTDI_SIO=m
-+CONFIG_USB_SERIAL_VISOR=m
-+CONFIG_USB_SERIAL_IPAQ=m
-+CONFIG_USB_SERIAL_IR=m
-+CONFIG_USB_SERIAL_EDGEPORT=m
-+CONFIG_USB_SERIAL_EDGEPORT_TI=m
-+CONFIG_USB_SERIAL_F81232=m
-+CONFIG_USB_SERIAL_GARMIN=m
-+CONFIG_USB_SERIAL_IPW=m
-+CONFIG_USB_SERIAL_IUU=m
-+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-+CONFIG_USB_SERIAL_KEYSPAN=m
-+CONFIG_USB_SERIAL_KLSI=m
-+CONFIG_USB_SERIAL_KOBIL_SCT=m
-+CONFIG_USB_SERIAL_MCT_U232=m
-+CONFIG_USB_SERIAL_METRO=m
-+CONFIG_USB_SERIAL_MOS7720=m
-+CONFIG_USB_SERIAL_MOS7840=m
-+CONFIG_USB_SERIAL_NAVMAN=m
-+CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_OTI6858=m
-+CONFIG_USB_SERIAL_QCAUX=m
-+CONFIG_USB_SERIAL_QUALCOMM=m
-+CONFIG_USB_SERIAL_SPCP8X5=m
-+CONFIG_USB_SERIAL_SAFE=m
-+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-+CONFIG_USB_SERIAL_SYMBOL=m
-+CONFIG_USB_SERIAL_TI=m
-+CONFIG_USB_SERIAL_CYBERJACK=m
-+CONFIG_USB_SERIAL_XIRCOM=m
-+CONFIG_USB_SERIAL_OPTION=m
-+CONFIG_USB_SERIAL_OMNINET=m
-+CONFIG_USB_SERIAL_OPTICON=m
-+CONFIG_USB_SERIAL_XSENS_MT=m
-+CONFIG_USB_SERIAL_WISHBONE=m
-+CONFIG_USB_SERIAL_SSU100=m
-+CONFIG_USB_SERIAL_QT2=m
-+CONFIG_USB_SERIAL_DEBUG=m
-+CONFIG_USB_EMI62=m
-+CONFIG_USB_EMI26=m
-+CONFIG_USB_ADUTUX=m
-+CONFIG_USB_SEVSEG=m
-+CONFIG_USB_RIO500=m
-+CONFIG_USB_LEGOTOWER=m
-+CONFIG_USB_LCD=m
-+CONFIG_USB_CYPRESS_CY7C63=m
-+CONFIG_USB_CYTHERM=m
-+CONFIG_USB_IDMOUSE=m
-+CONFIG_USB_FTDI_ELAN=m
-+CONFIG_USB_APPLEDISPLAY=m
-+CONFIG_USB_LD=m
-+CONFIG_USB_TRANCEVIBRATOR=m
-+CONFIG_USB_IOWARRIOR=m
-+CONFIG_USB_TEST=m
-+CONFIG_USB_ISIGHTFW=m
-+CONFIG_USB_YUREX=m
-+CONFIG_USB_ATM=m
-+CONFIG_USB_SPEEDTOUCH=m
-+CONFIG_USB_CXACRU=m
-+CONFIG_USB_UEAGLEATM=m
-+CONFIG_USB_XUSBATM=m
-+CONFIG_USB_GADGET=m
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_AUDIO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_MASS_STORAGE=m
-+CONFIG_USB_G_SERIAL=m
-+CONFIG_USB_MIDI_GADGET=m
-+CONFIG_USB_G_PRINTER=m
-+CONFIG_USB_CDC_COMPOSITE=m
-+CONFIG_USB_G_ACM_MS=m
-+CONFIG_USB_G_MULTI=m
-+CONFIG_USB_G_HID=m
-+CONFIG_USB_G_WEBCAM=m
-+CONFIG_MMC=y
-+CONFIG_MMC_BLOCK_MINORS=32
-+CONFIG_MMC_BCM2835_MMC=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_MMC_BCM2835_SDHOST=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SPI=m
-+CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_ONESHOT=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-+CONFIG_LEDS_TRIGGER_CPU=y
-+CONFIG_LEDS_TRIGGER_GPIO=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TRANSIENT=m
-+CONFIG_LEDS_TRIGGER_CAMERA=m
-+CONFIG_LEDS_TRIGGER_INPUT=y
-+CONFIG_LEDS_TRIGGER_PANIC=y
-+CONFIG_RTC_CLASS=y
-+# CONFIG_RTC_HCTOSYS is not set
-+CONFIG_RTC_DRV_ABX80X=m
-+CONFIG_RTC_DRV_DS1307=m
-+CONFIG_RTC_DRV_DS1374=m
-+CONFIG_RTC_DRV_DS1672=m
-+CONFIG_RTC_DRV_MAX6900=m
-+CONFIG_RTC_DRV_RS5C372=m
-+CONFIG_RTC_DRV_ISL1208=m
-+CONFIG_RTC_DRV_ISL12022=m
-+CONFIG_RTC_DRV_X1205=m
-+CONFIG_RTC_DRV_PCF8523=m
-+CONFIG_RTC_DRV_PCF8563=m
-+CONFIG_RTC_DRV_PCF8583=m
-+CONFIG_RTC_DRV_M41T80=m
-+CONFIG_RTC_DRV_BQ32K=m
-+CONFIG_RTC_DRV_S35390A=m
-+CONFIG_RTC_DRV_FM3130=m
-+CONFIG_RTC_DRV_RX8581=m
-+CONFIG_RTC_DRV_RX8025=m
-+CONFIG_RTC_DRV_EM3027=m
-+CONFIG_RTC_DRV_M41T93=m
-+CONFIG_RTC_DRV_M41T94=m
-+CONFIG_RTC_DRV_DS1302=m
-+CONFIG_RTC_DRV_DS1305=m
-+CONFIG_RTC_DRV_DS1390=m
-+CONFIG_RTC_DRV_R9701=m
-+CONFIG_RTC_DRV_RX4581=m
-+CONFIG_RTC_DRV_RS5C348=m
-+CONFIG_RTC_DRV_MAX6902=m
-+CONFIG_RTC_DRV_PCF2123=m
-+CONFIG_RTC_DRV_DS3232=m
-+CONFIG_RTC_DRV_PCF2127=m
-+CONFIG_RTC_DRV_RV3029C2=m
-+CONFIG_DMADEVICES=y
-+CONFIG_DMA_BCM2835=y
-+CONFIG_DMA_BCM2708=y
-+CONFIG_UIO=m
-+CONFIG_UIO_PDRV_GENIRQ=m
-+CONFIG_STAGING=y
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRNET=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
-+CONFIG_PRISM2_USB=m
-+CONFIG_R8712U=m
-+CONFIG_R8188EU=m
-+CONFIG_VT6656=m
-+CONFIG_SPEAKUP=m
-+CONFIG_SPEAKUP_SYNTH_SOFT=m
-+CONFIG_STAGING_MEDIA=y
-+CONFIG_LIRC_STAGING=y
-+CONFIG_LIRC_RPI=m
-+CONFIG_FB_TFT=m
-+CONFIG_FB_TFT_AGM1264K_FL=m
-+CONFIG_FB_TFT_BD663474=m
-+CONFIG_FB_TFT_HX8340BN=m
-+CONFIG_FB_TFT_HX8347D=m
-+CONFIG_FB_TFT_HX8353D=m
-+CONFIG_FB_TFT_HX8357D=m
-+CONFIG_FB_TFT_ILI9163=m
-+CONFIG_FB_TFT_ILI9320=m
-+CONFIG_FB_TFT_ILI9325=m
-+CONFIG_FB_TFT_ILI9340=m
-+CONFIG_FB_TFT_ILI9341=m
-+CONFIG_FB_TFT_ILI9481=m
-+CONFIG_FB_TFT_ILI9486=m
-+CONFIG_FB_TFT_PCD8544=m
-+CONFIG_FB_TFT_RA8875=m
-+CONFIG_FB_TFT_S6D02A1=m
-+CONFIG_FB_TFT_S6D1121=m
-+CONFIG_FB_TFT_SSD1289=m
-+CONFIG_FB_TFT_SSD1306=m
-+CONFIG_FB_TFT_SSD1331=m
-+CONFIG_FB_TFT_SSD1351=m
-+CONFIG_FB_TFT_ST7735R=m
-+CONFIG_FB_TFT_ST7789V=m
-+CONFIG_FB_TFT_TINYLCD=m
-+CONFIG_FB_TFT_TLS8204=m
-+CONFIG_FB_TFT_UC1701=m
-+CONFIG_FB_TFT_UPD161704=m
-+CONFIG_FB_TFT_WATTEROTT=m
-+CONFIG_FB_FLEX=m
-+CONFIG_FB_TFT_FBTFT_DEVICE=m
-+CONFIG_BCM2835_VCHIQ=y
-+CONFIG_BCM2835_VCHIQ_SUPPORT_MEMDUMP=y
-+CONFIG_SND_BCM2835=m
-+CONFIG_VIDEO_BCM2835=m
-+CONFIG_MAILBOX=y
-+CONFIG_BCM2835_MBOX=y
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_RASPBERRYPI_POWER=y
-+CONFIG_EXTCON=m
-+CONFIG_EXTCON_ARIZONA=m
-+CONFIG_IIO=m
-+CONFIG_IIO_BUFFER_CB=m
-+CONFIG_MCP320X=m
-+CONFIG_MCP3422=m
-+CONFIG_DHT11=m
-+CONFIG_HDC100X=m
-+CONFIG_HTU21=m
-+CONFIG_INV_MPU6050_I2C=m
-+CONFIG_TSL4531=m
-+CONFIG_VEML6070=m
-+CONFIG_BMP280=m
-+CONFIG_PWM_BCM2835=m
-+CONFIG_PWM_PCA9685=m
-+CONFIG_RPI_AXIPERF=m
-+CONFIG_RASPBERRYPI_FIRMWARE=y
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_REISERFS_FS=m
-+CONFIG_REISERFS_FS_XATTR=y
-+CONFIG_REISERFS_FS_POSIX_ACL=y
-+CONFIG_REISERFS_FS_SECURITY=y
-+CONFIG_JFS_FS=m
-+CONFIG_JFS_POSIX_ACL=y
-+CONFIG_JFS_SECURITY=y
-+CONFIG_JFS_STATISTICS=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_QUOTA=y
-+CONFIG_XFS_POSIX_ACL=y
-+CONFIG_XFS_RT=y
-+CONFIG_GFS2_FS=m
-+CONFIG_OCFS2_FS=m
-+CONFIG_BTRFS_FS=m
-+CONFIG_BTRFS_FS_POSIX_ACL=y
-+CONFIG_NILFS2_FS=m
-+CONFIG_F2FS_FS=y
-+CONFIG_FANOTIFY=y
-+CONFIG_QFMT_V1=m
-+CONFIG_QFMT_V2=m
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FUSE_FS=m
-+CONFIG_CUSE=m
-+CONFIG_OVERLAY_FS=m
-+CONFIG_FSCACHE=y
-+CONFIG_FSCACHE_STATS=y
-+CONFIG_FSCACHE_HISTOGRAM=y
-+CONFIG_CACHEFILES=y
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_NTFS_FS=m
-+CONFIG_NTFS_RW=y
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_ECRYPT_FS=m
-+CONFIG_HFS_FS=m
-+CONFIG_HFSPLUS_FS=m
-+CONFIG_JFFS2_FS=m
-+CONFIG_JFFS2_SUMMARY=y
-+CONFIG_UBIFS_FS=m
-+CONFIG_SQUASHFS=m
-+CONFIG_SQUASHFS_XATTR=y
-+CONFIG_SQUASHFS_LZO=y
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_NFS_SWAP=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3_ACL=y
-+CONFIG_NFSD_V4=y
-+CONFIG_CIFS=m
-+CONFIG_CIFS_WEAK_PW_HASH=y
-+CONFIG_CIFS_UPCALL=y
-+CONFIG_CIFS_XATTR=y
-+CONFIG_CIFS_POSIX=y
-+CONFIG_CIFS_ACL=y
-+CONFIG_CIFS_DFS_UPCALL=y
-+CONFIG_CIFS_FSCACHE=y
-+CONFIG_9P_FS=m
-+CONFIG_9P_FS_POSIX_ACL=y
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=m
-+CONFIG_NLS_CODEPAGE_775=m
-+CONFIG_NLS_CODEPAGE_850=m
-+CONFIG_NLS_CODEPAGE_852=m
-+CONFIG_NLS_CODEPAGE_855=m
-+CONFIG_NLS_CODEPAGE_857=m
-+CONFIG_NLS_CODEPAGE_860=m
-+CONFIG_NLS_CODEPAGE_861=m
-+CONFIG_NLS_CODEPAGE_862=m
-+CONFIG_NLS_CODEPAGE_863=m
-+CONFIG_NLS_CODEPAGE_864=m
-+CONFIG_NLS_CODEPAGE_865=m
-+CONFIG_NLS_CODEPAGE_866=m
-+CONFIG_NLS_CODEPAGE_869=m
-+CONFIG_NLS_CODEPAGE_936=m
-+CONFIG_NLS_CODEPAGE_950=m
-+CONFIG_NLS_CODEPAGE_932=m
-+CONFIG_NLS_CODEPAGE_949=m
-+CONFIG_NLS_CODEPAGE_874=m
-+CONFIG_NLS_ISO8859_8=m
-+CONFIG_NLS_CODEPAGE_1250=m
-+CONFIG_NLS_CODEPAGE_1251=m
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=m
-+CONFIG_NLS_ISO8859_2=m
-+CONFIG_NLS_ISO8859_3=m
-+CONFIG_NLS_ISO8859_4=m
-+CONFIG_NLS_ISO8859_5=m
-+CONFIG_NLS_ISO8859_6=m
-+CONFIG_NLS_ISO8859_7=m
-+CONFIG_NLS_ISO8859_9=m
-+CONFIG_NLS_ISO8859_13=m
-+CONFIG_NLS_ISO8859_14=m
-+CONFIG_NLS_ISO8859_15=m
-+CONFIG_NLS_KOI8_R=m
-+CONFIG_NLS_KOI8_U=m
-+CONFIG_DLM=m
-+CONFIG_PRINTK_TIME=y
-+CONFIG_BOOT_PRINTK_DELAY=y
-+CONFIG_DEBUG_MEMORY_INIT=y
-+CONFIG_DETECT_HUNG_TASK=y
-+CONFIG_LATENCYTOP=y
-+CONFIG_IRQSOFF_TRACER=y
-+CONFIG_SCHED_TRACER=y
-+CONFIG_STACK_TRACER=y
-+CONFIG_BLK_DEV_IO_TRACE=y
-+# CONFIG_UPROBE_EVENTS is not set
-+CONFIG_FUNCTION_PROFILER=y
-+CONFIG_KGDB=y
-+CONFIG_KGDB_KDB=y
-+CONFIG_KDB_KEYBOARD=y
-+CONFIG_CRYPTO_USER=m
-+CONFIG_CRYPTO_CRYPTD=m
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_CTS=m
-+CONFIG_CRYPTO_XTS=m
-+CONFIG_CRYPTO_XCBC=m
-+CONFIG_CRYPTO_SHA512=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_DES=y
-+CONFIG_CRYPTO_LZ4=m
-+CONFIG_CRYPTO_USER_API_SKCIPHER=m
-+# CONFIG_CRYPTO_HW is not set
-+CONFIG_ARM_CRYPTO=y
-+CONFIG_CRYPTO_SHA1_ARM=m
-+CONFIG_CRYPTO_AES_ARM=m
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0097-Add-arm64-configuration-and-device-tree-differences..patch b/target/linux/brcm2708/patches-4.14/950-0097-Add-arm64-configuration-and-device-tree-differences..patch
deleted file mode 100644
index 47199d130..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0097-Add-arm64-configuration-and-device-tree-differences..patch
+++ /dev/null
@@ -1,1406 +0,0 @@
-From 684614f63d128a4ec1e3012698c21a295e3d691e Mon Sep 17 00:00:00 2001
-From: Michael Zoran <mzoran@crowfest.net>
-Date: Wed, 24 Aug 2016 03:35:56 -0700
-Subject: [PATCH 097/454] Add arm64 configuration and device tree differences.
- Disable MMC_BCM2835_SDHOST and MMC_BCM2835 since these drivers are crashing
- at the moment.
-
-ARM64: Modify default config to get raspbian to boot (#1686)
-
-1. Enable emulation of deprecated instructions.
-2. Enable ARM 8.1 and 8.2 features which are not detected at runtime.
-3. Switch the default governer to powersave.
-4. Include the watchdog timer driver in the kernel image rather then a module.
-
-Tested with raspbian-jessie 2016-09-23.
----
- arch/arm64/Kconfig.platforms                  |   22 +
- arch/arm64/boot/dts/broadcom/Makefile         |    1 +
- .../boot/dts/broadcom/bcm2710-rpi-3-b.dts     |    3 +
- arch/arm64/configs/bcmrpi3_defconfig          | 1334 +++++++++++++++++
- 4 files changed, 1360 insertions(+)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts
- create mode 100644 arch/arm64/configs/bcmrpi3_defconfig
-
---- a/arch/arm64/Kconfig.platforms
-+++ b/arch/arm64/Kconfig.platforms
-@@ -1,5 +1,27 @@
- menu "Platform selection"
- 
-+config MACH_BCM2709
-+        bool
-+
-+config ARCH_BCM2709
-+        bool "Broadcom BCM2709 family"
-+        select MACH_BCM2709
-+        select HAVE_SMP
-+        select ARM_AMBA
-+        select COMMON_CLK
-+        select ARCH_HAS_CPUFREQ
-+        select GENERIC_CLOCKEVENTS
-+        select MULTI_IRQ_HANDLER
-+        select SPARSE_IRQ
-+        select MFD_SYSCON
-+        select VC4
-+        select USE_OF
-+        select ARCH_REQUIRE_GPIOLIB
-+        select PINCTRL
-+        select PINCTRL_BCM2835
-+        help
-+          This enables support for Broadcom BCM2709 boards.
-+
- config ARCH_ACTIONS
- 	bool "Actions Semi Platforms"
- 	select OWL_TIMER
---- a/arch/arm64/boot/dts/broadcom/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/Makefile
-@@ -1,5 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
- dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
-+dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-3-b.dtb
- 
- dts-dirs	+= northstar2
- dts-dirs	+= stingray
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts
-@@ -0,0 +1,3 @@
-+#define RPI364
-+
-+#include "../../../../arm/boot/dts/bcm2710-rpi-3-b.dts"
---- /dev/null
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -0,0 +1,1334 @@
-+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
-+CONFIG_PHYS_OFFSET=0
-+CONFIG_LOCALVERSION="-v8"
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_64BIT=y
-+CONFIG_SYSVIPC=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+
-+#
-+# ARM errata workarounds via the alternatives framework
-+#
-+CONFIG_ARM64_ERRATUM_826319=n
-+CONFIG_ARM64_ERRATUM_827319=n
-+CONFIG_ARM64_ERRATUM_824069=n
-+CONFIG_ARM64_ERRATUM_819472=n
-+CONFIG_ARM64_ERRATUM_832075=n
-+CONFIG_ARM64_ERRATUM_845719=n
-+CONFIG_ARM64_ERRATUM_843419=n
-+CONFIG_CAVIUM_ERRATUM_22375=n
-+CONFIG_CAVIUM_ERRATUM_23154=n
-+CONFIG_CAVIUM_ERRATUM_27456=n
-+CONFIG_ARM64_4K_PAGES=y
-+CONFIG_ARM64_VA_BITS_39=y
-+CONFIG_ARM64_VA_BITS=39
-+CONFIG_SCHED_MC=y
-+CONFIG_NR_CPUS=4
-+CONFIG_HOTPLUG_CPU=y
-+CONFIG_ARMV8_DEPRECATED=y
-+CONFIG_SWP_EMULATION=y
-+CONFIG_CP15_BARRIER_EMULATION=y
-+CONFIG_SETEND_EMULATION=y
-+
-+#
-+# ARMv8.1 architectural features
-+#
-+CONFIG_ARM64_HW_AFDBM=y
-+CONFIG_ARM64_PAN=y
-+CONFIG_ARM64_LSE_ATOMICS=y
-+CONFIG_ARM64_VHE=y
-+
-+#
-+# ARMv8.2 architectural features
-+#
-+CONFIG_ARM64_UAO=y
-+CONFIG_ARM64_MODULE_CMODEL_LARGE=n
-+CONFIG_RANDOMIZE_BASE=n
-+
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+CONFIG_TASKSTATS=y
-+CONFIG_TASK_DELAY_ACCT=y
-+CONFIG_TASK_XACCT=y
-+CONFIG_TASK_IO_ACCOUNTING=y
-+CONFIG_IKCONFIG=m
-+CONFIG_IKCONFIG_PROC=y
-+CONFIG_NMI_LOG_BUF_SHIFT=12
-+CONFIG_MEMCG=y
-+CONFIG_BLK_CGROUP=y
-+CONFIG_CGROUP_FREEZER=y
-+CONFIG_CPUSETS=y
-+CONFIG_CGROUP_DEVICE=y
-+CONFIG_CGROUP_CPUACCT=y
-+CONFIG_NAMESPACES=y
-+CONFIG_USER_NS=y
-+CONFIG_SCHED_AUTOGROUP=y
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_COMPAT_BRK is not set
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+CONFIG_JUMP_LABEL=y
-+CONFIG_MODULES=y
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODVERSIONS=y
-+CONFIG_MODULE_SRCVERSION_ALL=y
-+CONFIG_TRIM_UNUSED_KSYMS=y
-+CONFIG_BLK_DEV_THROTTLING=y
-+CONFIG_PARTITION_ADVANCED=y
-+CONFIG_MAC_PARTITION=y
-+CONFIG_CFQ_GROUP_IOSCHED=y
-+CONFIG_ARCH_BCM2709=y
-+# CONFIG_CACHE_L2X0 is not set
-+CONFIG_SMP=y
-+CONFIG_HAVE_ARM_ARCH_TIMER=y
-+CONFIG_VMSPLIT_2G=y
-+CONFIG_PREEMPT_VOLUNTARY=y
-+CONFIG_AEABI=y
-+CONFIG_OABI_COMPAT=y
-+# CONFIG_CPU_SW_DOMAIN_PAN is not set
-+CONFIG_CLEANCACHE=y
-+CONFIG_FRONTSWAP=y
-+CONFIG_CMA=y
-+CONFIG_ZSMALLOC=m
-+CONFIG_PGTABLE_MAPPING=y
-+CONFIG_UACCESS_WITH_MEMCPY=y
-+CONFIG_SECCOMP=y
-+# CONFIG_ATAGS is not set
-+CONFIG_ZBOOT_ROM_TEXT=0x0
-+CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-+CONFIG_VFP=y
-+CONFIG_NEON=y
-+CONFIG_KERNEL_MODE_NEON=y
-+CONFIG_BINFMT_MISC=m
-+CONFIG_COMPAT=y
-+CONFIG_SYSVIPC_COMPAT=y
-+
-+# CONFIG_SUSPEND is not set
-+CONFIG_PM=y
-+CONFIG_NET=y
-+CONFIG_PACKET=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM_USER=y
-+CONFIG_NET_KEY=m
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_IP_MULTIPLE_TABLES=y
-+CONFIG_IP_ROUTE_MULTIPATH=y
-+CONFIG_IP_ROUTE_VERBOSE=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+CONFIG_IP_PNP_RARP=y
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE_DEMUX=m
-+CONFIG_NET_IPGRE=m
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IP_PIMSM_V1=y
-+CONFIG_IP_PIMSM_V2=y
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+CONFIG_INET_IPCOMP=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+CONFIG_INET_DIAG=m
-+CONFIG_IPV6=m
-+CONFIG_IPV6_ROUTER_PREF=y
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+CONFIG_IPV6_TUNNEL=m
-+CONFIG_IPV6_MULTIPLE_TABLES=y
-+CONFIG_IPV6_SUBTREES=y
-+CONFIG_IPV6_MROUTE=y
-+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
-+CONFIG_IPV6_PIMSM_V2=y
-+CONFIG_NETFILTER=y
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_ZONES=y
-+CONFIG_NF_CONNTRACK_EVENTS=y
-+CONFIG_NF_CONNTRACK_TIMESTAMP=y
-+CONFIG_NF_CT_PROTO_DCCP=m
-+CONFIG_NF_CT_PROTO_UDPLITE=m
-+CONFIG_NF_CONNTRACK_AMANDA=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_H323=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-+CONFIG_NF_CONNTRACK_SNMP=m
-+CONFIG_NF_CONNTRACK_PPTP=m
-+CONFIG_NF_CONNTRACK_SANE=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CONNTRACK_TFTP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XT_SET=m
-+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
-+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-+CONFIG_NETFILTER_XT_TARGET_DSCP=m
-+CONFIG_NETFILTER_XT_TARGET_HMARK=m
-+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-+CONFIG_NETFILTER_XT_TARGET_LED=m
-+CONFIG_NETFILTER_XT_TARGET_LOG=m
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-+CONFIG_NETFILTER_XT_TARGET_TEE=m
-+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-+CONFIG_NETFILTER_XT_TARGET_TRACE=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_BPF=m
-+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
-+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_CPU=m
-+CONFIG_NETFILTER_XT_MATCH_DCCP=m
-+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
-+CONFIG_NETFILTER_XT_MATCH_DSCP=m
-+CONFIG_NETFILTER_XT_MATCH_ESP=m
-+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_HELPER=m
-+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-+CONFIG_NETFILTER_XT_MATCH_IPVS=m
-+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-+CONFIG_NETFILTER_XT_MATCH_MAC=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
-+CONFIG_NETFILTER_XT_MATCH_OSF=m
-+CONFIG_NETFILTER_XT_MATCH_OWNER=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-+CONFIG_NETFILTER_XT_MATCH_REALM=m
-+CONFIG_NETFILTER_XT_MATCH_RECENT=m
-+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-+CONFIG_NETFILTER_XT_MATCH_STRING=m
-+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_TIME=m
-+CONFIG_NETFILTER_XT_MATCH_U32=m
-+CONFIG_IP_SET=m
-+CONFIG_IP_SET_BITMAP_IP=m
-+CONFIG_IP_SET_BITMAP_IPMAC=m
-+CONFIG_IP_SET_BITMAP_PORT=m
-+CONFIG_IP_SET_HASH_IP=m
-+CONFIG_IP_SET_HASH_IPPORT=m
-+CONFIG_IP_SET_HASH_IPPORTIP=m
-+CONFIG_IP_SET_HASH_IPPORTNET=m
-+CONFIG_IP_SET_HASH_NET=m
-+CONFIG_IP_SET_HASH_NETPORT=m
-+CONFIG_IP_SET_HASH_NETIFACE=m
-+CONFIG_IP_SET_LIST_SET=m
-+CONFIG_IP_VS=m
-+CONFIG_IP_VS_PROTO_TCP=y
-+CONFIG_IP_VS_PROTO_UDP=y
-+CONFIG_IP_VS_PROTO_ESP=y
-+CONFIG_IP_VS_PROTO_AH=y
-+CONFIG_IP_VS_PROTO_SCTP=y
-+CONFIG_IP_VS_RR=m
-+CONFIG_IP_VS_WRR=m
-+CONFIG_IP_VS_LC=m
-+CONFIG_IP_VS_WLC=m
-+CONFIG_IP_VS_LBLC=m
-+CONFIG_IP_VS_LBLCR=m
-+CONFIG_IP_VS_DH=m
-+CONFIG_IP_VS_SH=m
-+CONFIG_IP_VS_SED=m
-+CONFIG_IP_VS_NQ=m
-+CONFIG_IP_VS_FTP=m
-+CONFIG_IP_VS_PE_SIP=m
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_MATCH_AH=m
-+CONFIG_IP_NF_MATCH_ECN=m
-+CONFIG_IP_NF_MATCH_RPFILTER=m
-+CONFIG_IP_NF_MATCH_TTL=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_NAT=m
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_IP_NF_TARGET_NETMAP=m
-+CONFIG_IP_NF_TARGET_REDIRECT=m
-+CONFIG_IP_NF_MANGLE=m
-+CONFIG_IP_NF_TARGET_CLUSTERIP=m
-+CONFIG_IP_NF_TARGET_ECN=m
-+CONFIG_IP_NF_TARGET_TTL=m
-+CONFIG_IP_NF_RAW=m
-+CONFIG_IP_NF_ARPTABLES=m
-+CONFIG_IP_NF_ARPFILTER=m
-+CONFIG_IP_NF_ARP_MANGLE=m
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_AH=m
-+CONFIG_IP6_NF_MATCH_EUI64=m
-+CONFIG_IP6_NF_MATCH_FRAG=m
-+CONFIG_IP6_NF_MATCH_OPTS=m
-+CONFIG_IP6_NF_MATCH_HL=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_MATCH_MH=m
-+CONFIG_IP6_NF_MATCH_RPFILTER=m
-+CONFIG_IP6_NF_MATCH_RT=m
-+CONFIG_IP6_NF_TARGET_HL=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+CONFIG_IP6_NF_RAW=m
-+CONFIG_IP6_NF_NAT=m
-+CONFIG_IP6_NF_TARGET_MASQUERADE=m
-+CONFIG_IP6_NF_TARGET_NPT=m
-+CONFIG_BRIDGE_NF_EBTABLES=m
-+CONFIG_BRIDGE_EBT_BROUTE=m
-+CONFIG_BRIDGE_EBT_T_FILTER=m
-+CONFIG_BRIDGE_EBT_T_NAT=m
-+CONFIG_BRIDGE_EBT_802_3=m
-+CONFIG_BRIDGE_EBT_AMONG=m
-+CONFIG_BRIDGE_EBT_ARP=m
-+CONFIG_BRIDGE_EBT_IP=m
-+CONFIG_BRIDGE_EBT_IP6=m
-+CONFIG_BRIDGE_EBT_LIMIT=m
-+CONFIG_BRIDGE_EBT_MARK=m
-+CONFIG_BRIDGE_EBT_PKTTYPE=m
-+CONFIG_BRIDGE_EBT_STP=m
-+CONFIG_BRIDGE_EBT_VLAN=m
-+CONFIG_BRIDGE_EBT_ARPREPLY=m
-+CONFIG_BRIDGE_EBT_DNAT=m
-+CONFIG_BRIDGE_EBT_MARK_T=m
-+CONFIG_BRIDGE_EBT_REDIRECT=m
-+CONFIG_BRIDGE_EBT_SNAT=m
-+CONFIG_BRIDGE_EBT_LOG=m
-+CONFIG_BRIDGE_EBT_NFLOG=m
-+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
-+CONFIG_ATM=m
-+CONFIG_L2TP=m
-+CONFIG_L2TP_V3=y
-+CONFIG_L2TP_IP=m
-+CONFIG_L2TP_ETH=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+CONFIG_VLAN_8021Q_GVRP=y
-+CONFIG_ATALK=m
-+CONFIG_6LOWPAN=m
-+CONFIG_IEEE802154=m
-+CONFIG_IEEE802154_6LOWPAN=m
-+CONFIG_MAC802154=m
-+CONFIG_NET_SCHED=y
-+CONFIG_NET_SCH_CBQ=m
-+CONFIG_NET_SCH_HTB=m
-+CONFIG_NET_SCH_HFSC=m
-+CONFIG_NET_SCH_PRIO=m
-+CONFIG_NET_SCH_MULTIQ=m
-+CONFIG_NET_SCH_RED=m
-+CONFIG_NET_SCH_SFB=m
-+CONFIG_NET_SCH_SFQ=m
-+CONFIG_NET_SCH_TEQL=m
-+CONFIG_NET_SCH_TBF=m
-+CONFIG_NET_SCH_GRED=m
-+CONFIG_NET_SCH_DSMARK=m
-+CONFIG_NET_SCH_NETEM=m
-+CONFIG_NET_SCH_DRR=m
-+CONFIG_NET_SCH_MQPRIO=m
-+CONFIG_NET_SCH_CHOKE=m
-+CONFIG_NET_SCH_QFQ=m
-+CONFIG_NET_SCH_CODEL=m
-+CONFIG_NET_SCH_FQ_CODEL=m
-+CONFIG_NET_SCH_INGRESS=m
-+CONFIG_NET_SCH_PLUG=m
-+CONFIG_NET_CLS_BASIC=m
-+CONFIG_NET_CLS_TCINDEX=m
-+CONFIG_NET_CLS_ROUTE4=m
-+CONFIG_NET_CLS_FW=m
-+CONFIG_NET_CLS_U32=m
-+CONFIG_CLS_U32_MARK=y
-+CONFIG_NET_CLS_RSVP=m
-+CONFIG_NET_CLS_RSVP6=m
-+CONFIG_NET_CLS_FLOW=m
-+CONFIG_NET_CLS_CGROUP=m
-+CONFIG_NET_EMATCH=y
-+CONFIG_NET_EMATCH_CMP=m
-+CONFIG_NET_EMATCH_NBYTE=m
-+CONFIG_NET_EMATCH_U32=m
-+CONFIG_NET_EMATCH_META=m
-+CONFIG_NET_EMATCH_TEXT=m
-+CONFIG_NET_EMATCH_IPSET=m
-+CONFIG_NET_CLS_ACT=y
-+CONFIG_NET_ACT_POLICE=m
-+CONFIG_NET_ACT_GACT=m
-+CONFIG_GACT_PROB=y
-+CONFIG_NET_ACT_MIRRED=m
-+CONFIG_NET_ACT_IPT=m
-+CONFIG_NET_ACT_NAT=m
-+CONFIG_NET_ACT_PEDIT=m
-+CONFIG_NET_ACT_SIMP=m
-+CONFIG_NET_ACT_SKBEDIT=m
-+CONFIG_NET_ACT_CSUM=m
-+CONFIG_BATMAN_ADV=m
-+CONFIG_OPENVSWITCH=m
-+CONFIG_NET_PKTGEN=m
-+CONFIG_HAMRADIO=y
-+CONFIG_AX25=m
-+CONFIG_NETROM=m
-+CONFIG_ROSE=m
-+CONFIG_MKISS=m
-+CONFIG_6PACK=m
-+CONFIG_BPQETHER=m
-+CONFIG_BAYCOM_SER_FDX=m
-+CONFIG_BAYCOM_SER_HDX=m
-+CONFIG_YAM=m
-+CONFIG_CAN=m
-+CONFIG_CAN_VCAN=m
-+CONFIG_CAN_MCP251X=m
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRNET=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
-+CONFIG_BT=m
-+CONFIG_BT_RFCOMM=m
-+CONFIG_BT_RFCOMM_TTY=y
-+CONFIG_BT_BNEP=m
-+CONFIG_BT_BNEP_MC_FILTER=y
-+CONFIG_BT_BNEP_PROTO_FILTER=y
-+CONFIG_BT_HIDP=m
-+CONFIG_BT_6LOWPAN=m
-+CONFIG_BT_HCIBTUSB=m
-+CONFIG_BT_HCIUART=m
-+CONFIG_BT_HCIUART_3WIRE=y
-+CONFIG_BT_HCIUART_BCM=y
-+CONFIG_BT_HCIBCM203X=m
-+CONFIG_BT_HCIBPA10X=m
-+CONFIG_BT_HCIBFUSB=m
-+CONFIG_BT_HCIVHCI=m
-+CONFIG_BT_MRVL=m
-+CONFIG_BT_MRVL_SDIO=m
-+CONFIG_BT_ATH3K=m
-+CONFIG_BT_WILINK=m
-+CONFIG_MAC80211=m
-+CONFIG_MAC80211_MESH=y
-+CONFIG_WIMAX=m
-+CONFIG_RFKILL=m
-+CONFIG_RFKILL_INPUT=y
-+CONFIG_NET_9P=m
-+CONFIG_NFC=m
-+CONFIG_DEVTMPFS=y
-+CONFIG_DEVTMPFS_MOUNT=y
-+CONFIG_DMA_CMA=y
-+CONFIG_CMA_SIZE_MBYTES=5
-+CONFIG_MTD=m
-+CONFIG_MTD_BLOCK=m
-+CONFIG_MTD_NAND=m
-+CONFIG_MTD_UBI=m
-+CONFIG_OF_CONFIGFS=y
-+CONFIG_ZRAM=m
-+CONFIG_BLK_DEV_LOOP=y
-+CONFIG_BLK_DEV_CRYPTOLOOP=m
-+CONFIG_BLK_DEV_DRBD=m
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=y
-+CONFIG_CDROM_PKTCDVD=m
-+CONFIG_ATA_OVER_ETH=m
-+CONFIG_EEPROM_AT24=m
-+CONFIG_TI_ST=m
-+CONFIG_SCSI=y
-+# CONFIG_SCSI_PROC_FS is not set
-+CONFIG_BLK_DEV_SD=y
-+CONFIG_CHR_DEV_ST=m
-+CONFIG_CHR_DEV_OSST=m
-+CONFIG_BLK_DEV_SR=m
-+CONFIG_CHR_DEV_SG=m
-+CONFIG_SCSI_ISCSI_ATTRS=y
-+CONFIG_ISCSI_TCP=m
-+CONFIG_ISCSI_BOOT_SYSFS=m
-+CONFIG_MD=y
-+CONFIG_MD_LINEAR=m
-+CONFIG_MD_RAID0=m
-+CONFIG_BLK_DEV_DM=m
-+CONFIG_DM_CRYPT=m
-+CONFIG_DM_SNAPSHOT=m
-+CONFIG_DM_THIN_PROVISIONING=m
-+CONFIG_DM_MIRROR=m
-+CONFIG_DM_LOG_USERSPACE=m
-+CONFIG_DM_RAID=m
-+CONFIG_DM_ZERO=m
-+CONFIG_DM_DELAY=m
-+CONFIG_NETDEVICES=y
-+CONFIG_BONDING=m
-+CONFIG_DUMMY=m
-+CONFIG_IFB=m
-+CONFIG_MACVLAN=m
-+CONFIG_IPVLAN=m
-+CONFIG_VXLAN=m
-+CONFIG_NETCONSOLE=m
-+CONFIG_TUN=m
-+CONFIG_VETH=m
-+CONFIG_ENC28J60=m
-+CONFIG_QCA7000=m
-+CONFIG_MDIO_BITBANG=m
-+CONFIG_PPP=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPP_MULTILINK=y
-+CONFIG_PPPOATM=m
-+CONFIG_PPPOE=m
-+CONFIG_PPPOL2TP=m
-+CONFIG_PPP_ASYNC=m
-+CONFIG_PPP_SYNC_TTY=m
-+CONFIG_SLIP=m
-+CONFIG_SLIP_COMPRESSED=y
-+CONFIG_SLIP_SMART=y
-+CONFIG_USB_CATC=m
-+CONFIG_USB_KAWETH=m
-+CONFIG_USB_PEGASUS=m
-+CONFIG_USB_RTL8150=m
-+CONFIG_USB_RTL8152=m
-+CONFIG_USB_USBNET=y
-+CONFIG_USB_NET_AX8817X=m
-+CONFIG_USB_NET_AX88179_178A=m
-+CONFIG_USB_NET_CDCETHER=m
-+CONFIG_USB_NET_CDC_EEM=m
-+CONFIG_USB_NET_CDC_NCM=m
-+CONFIG_USB_NET_HUAWEI_CDC_NCM=m
-+CONFIG_USB_NET_CDC_MBIM=m
-+CONFIG_USB_NET_DM9601=m
-+CONFIG_USB_NET_SR9700=m
-+CONFIG_USB_NET_SR9800=m
-+CONFIG_USB_NET_SMSC75XX=m
-+CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_NET_GL620A=m
-+CONFIG_USB_NET_NET1080=m
-+CONFIG_USB_NET_PLUSB=m
-+CONFIG_USB_NET_MCS7830=m
-+CONFIG_USB_NET_CDC_SUBSET=m
-+CONFIG_USB_ALI_M5632=y
-+CONFIG_USB_AN2720=y
-+CONFIG_USB_EPSON2888=y
-+CONFIG_USB_KC2190=y
-+CONFIG_USB_NET_ZAURUS=m
-+CONFIG_USB_NET_CX82310_ETH=m
-+CONFIG_USB_NET_KALMIA=m
-+CONFIG_USB_NET_QMI_WWAN=m
-+CONFIG_USB_HSO=m
-+CONFIG_USB_NET_INT51X1=m
-+CONFIG_USB_IPHETH=m
-+CONFIG_USB_SIERRA_NET=m
-+CONFIG_USB_VL600=m
-+CONFIG_ATH9K=m
-+CONFIG_ATH9K_HTC=m
-+CONFIG_CARL9170=m
-+CONFIG_ATH6KL=m
-+CONFIG_ATH6KL_USB=m
-+CONFIG_AR5523=m
-+CONFIG_AT76C50X_USB=m
-+CONFIG_B43=m
-+# CONFIG_B43_PHY_N is not set
-+CONFIG_B43LEGACY=m
-+CONFIG_BRCMFMAC=m
-+CONFIG_BRCMFMAC_USB=y
-+CONFIG_HOSTAP=m
-+CONFIG_P54_COMMON=m
-+CONFIG_P54_USB=m
-+CONFIG_LIBERTAS=m
-+CONFIG_LIBERTAS_USB=m
-+CONFIG_LIBERTAS_SDIO=m
-+CONFIG_LIBERTAS_THINFIRM=m
-+CONFIG_LIBERTAS_THINFIRM_USB=m
-+CONFIG_MWIFIEX=m
-+CONFIG_MWIFIEX_SDIO=m
-+CONFIG_MT7601U=m
-+CONFIG_RT2X00=m
-+CONFIG_RT2500USB=m
-+CONFIG_RT73USB=m
-+CONFIG_RT2800USB=m
-+CONFIG_RT2800USB_RT3573=y
-+CONFIG_RT2800USB_RT53XX=y
-+CONFIG_RT2800USB_RT55XX=y
-+CONFIG_RT2800USB_UNKNOWN=y
-+CONFIG_RTL8187=m
-+CONFIG_RTL8192CU=n
-+CONFIG_USB_ZD1201=m
-+CONFIG_ZD1211RW=m
-+CONFIG_MAC80211_HWSIM=m
-+CONFIG_USB_NET_RNDIS_WLAN=m
-+CONFIG_WIMAX_I2400M_USB=m
-+CONFIG_IEEE802154_AT86RF230=m
-+CONFIG_IEEE802154_MRF24J40=m
-+CONFIG_IEEE802154_CC2520=m
-+CONFIG_INPUT_POLLDEV=m
-+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-+CONFIG_INPUT_JOYDEV=m
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_KEYBOARD_ATKBD is not set
-+CONFIG_KEYBOARD_GPIO=m
-+# CONFIG_INPUT_MOUSE is not set
-+CONFIG_INPUT_JOYSTICK=y
-+CONFIG_JOYSTICK_IFORCE=m
-+CONFIG_JOYSTICK_IFORCE_USB=y
-+CONFIG_JOYSTICK_XPAD=m
-+CONFIG_JOYSTICK_XPAD_FF=y
-+CONFIG_JOYSTICK_XPAD_LEDS=y
-+CONFIG_JOYSTICK_RPISENSE=m
-+CONFIG_INPUT_TOUCHSCREEN=y
-+CONFIG_TOUCHSCREEN_ADS7846=m
-+CONFIG_TOUCHSCREEN_EGALAX=m
-+CONFIG_TOUCHSCREEN_FT6236=m
-+CONFIG_TOUCHSCREEN_RPI_FT5406=m
-+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
-+CONFIG_TOUCHSCREEN_STMPE=m
-+CONFIG_INPUT_MISC=y
-+CONFIG_INPUT_AD714X=m
-+CONFIG_INPUT_ATI_REMOTE2=m
-+CONFIG_INPUT_KEYSPAN_REMOTE=m
-+CONFIG_INPUT_POWERMATE=m
-+CONFIG_INPUT_YEALINK=m
-+CONFIG_INPUT_CM109=m
-+CONFIG_INPUT_UINPUT=m
-+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-+CONFIG_INPUT_ADXL34X=m
-+CONFIG_INPUT_CMA3000=m
-+CONFIG_SERIO=m
-+CONFIG_SERIO_RAW=m
-+CONFIG_GAMEPORT=m
-+CONFIG_GAMEPORT_NS558=m
-+CONFIG_GAMEPORT_L4=m
-+CONFIG_BRCM_CHAR_DRIVERS=n
-+CONFIG_BCM_VC_CMA=n
-+CONFIG_BCM_VCIO=n
-+CONFIG_BCM_VC_SM=n
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_DEVKMEM is not set
-+CONFIG_SERIAL_8250=y
-+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-+CONFIG_SERIAL_8250_CONSOLE=y
-+# CONFIG_SERIAL_8250_DMA is not set
-+CONFIG_SERIAL_8250_NR_UARTS=1
-+CONFIG_SERIAL_8250_RUNTIME_UARTS=0
-+CONFIG_SERIAL_OF_PLATFORM=y
-+CONFIG_SERIAL_AMBA_PL011=y
-+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-+CONFIG_SERIAL_SC16IS7XX=m
-+CONFIG_SERIAL_SC16IS7XX_SPI=y
-+CONFIG_TTY_PRINTK=y
-+CONFIG_HW_RANDOM=y
-+CONFIG_RAW_DRIVER=y
-+CONFIG_I2C=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_MUX_PCA954x=m
-+CONFIG_I2C_BCM2708=m
-+CONFIG_I2C_GPIO=m
-+CONFIG_SPI=y
-+CONFIG_SPI_BCM2835=m
-+CONFIG_SPI_BCM2835AUX=m
-+CONFIG_SPI_SPIDEV=y
-+CONFIG_PPS=m
-+CONFIG_PPS_CLIENT_LDISC=m
-+CONFIG_PPS_CLIENT_GPIO=m
-+CONFIG_GPIO_SYSFS=y
-+CONFIG_GPIO_BCM_VIRT=y
-+CONFIG_GPIO_ARIZONA=m
-+CONFIG_GPIO_STMPE=y
-+CONFIG_GPIO_MCP23S08=m
-+CONFIG_W1=m
-+CONFIG_W1_MASTER_DS2490=m
-+CONFIG_W1_MASTER_DS2482=m
-+CONFIG_W1_MASTER_DS1WM=m
-+CONFIG_W1_MASTER_GPIO=m
-+CONFIG_W1_SLAVE_THERM=m
-+CONFIG_W1_SLAVE_SMEM=m
-+CONFIG_W1_SLAVE_DS2408=m
-+CONFIG_W1_SLAVE_DS2413=m
-+CONFIG_W1_SLAVE_DS2406=m
-+CONFIG_W1_SLAVE_DS2423=m
-+CONFIG_W1_SLAVE_DS2431=m
-+CONFIG_W1_SLAVE_DS2433=m
-+CONFIG_W1_SLAVE_DS2760=m
-+CONFIG_W1_SLAVE_DS2780=m
-+CONFIG_W1_SLAVE_DS2781=m
-+CONFIG_W1_SLAVE_DS28E04=m
-+CONFIG_W1_SLAVE_BQ27000=m
-+CONFIG_BATTERY_DS2760=m
-+CONFIG_POWER_RESET=y
-+CONFIG_POWER_RESET_GPIO=y
-+CONFIG_HWMON=m
-+CONFIG_SENSORS_LM75=m
-+CONFIG_SENSORS_SHT21=m
-+CONFIG_SENSORS_SHTC1=m
-+CONFIG_THERMAL=y
-+CONFIG_THERMAL_BCM2835=y
-+CONFIG_WATCHDOG=y
-+CONFIG_BCM2835_WDT=y
-+CONFIG_UCB1400_CORE=m
-+CONFIG_MFD_STMPE=y
-+CONFIG_STMPE_SPI=y
-+CONFIG_MFD_ARIZONA_I2C=m
-+CONFIG_MFD_ARIZONA_SPI=m
-+CONFIG_MFD_WM5102=y
-+CONFIG_MEDIA_SUPPORT=m
-+CONFIG_MEDIA_CAMERA_SUPPORT=y
-+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-+CONFIG_MEDIA_RADIO_SUPPORT=y
-+CONFIG_MEDIA_RC_SUPPORT=y
-+CONFIG_MEDIA_CONTROLLER=y
-+CONFIG_LIRC=m
-+CONFIG_RC_DEVICES=y
-+CONFIG_RC_ATI_REMOTE=m
-+CONFIG_IR_IMON=m
-+CONFIG_IR_MCEUSB=m
-+CONFIG_IR_REDRAT3=m
-+CONFIG_IR_STREAMZAP=m
-+CONFIG_IR_IGUANA=m
-+CONFIG_IR_TTUSBIR=m
-+CONFIG_RC_LOOPBACK=m
-+CONFIG_IR_GPIO_CIR=m
-+CONFIG_MEDIA_USB_SUPPORT=y
-+CONFIG_USB_VIDEO_CLASS=m
-+CONFIG_USB_M5602=m
-+CONFIG_USB_STV06XX=m
-+CONFIG_USB_GL860=m
-+CONFIG_USB_GSPCA_BENQ=m
-+CONFIG_USB_GSPCA_CONEX=m
-+CONFIG_USB_GSPCA_CPIA1=m
-+CONFIG_USB_GSPCA_DTCS033=m
-+CONFIG_USB_GSPCA_ETOMS=m
-+CONFIG_USB_GSPCA_FINEPIX=m
-+CONFIG_USB_GSPCA_JEILINJ=m
-+CONFIG_USB_GSPCA_JL2005BCD=m
-+CONFIG_USB_GSPCA_KINECT=m
-+CONFIG_USB_GSPCA_KONICA=m
-+CONFIG_USB_GSPCA_MARS=m
-+CONFIG_USB_GSPCA_MR97310A=m
-+CONFIG_USB_GSPCA_NW80X=m
-+CONFIG_USB_GSPCA_OV519=m
-+CONFIG_USB_GSPCA_OV534=m
-+CONFIG_USB_GSPCA_OV534_9=m
-+CONFIG_USB_GSPCA_PAC207=m
-+CONFIG_USB_GSPCA_PAC7302=m
-+CONFIG_USB_GSPCA_PAC7311=m
-+CONFIG_USB_GSPCA_SE401=m
-+CONFIG_USB_GSPCA_SN9C2028=m
-+CONFIG_USB_GSPCA_SN9C20X=m
-+CONFIG_USB_GSPCA_SONIXB=m
-+CONFIG_USB_GSPCA_SONIXJ=m
-+CONFIG_USB_GSPCA_SPCA500=m
-+CONFIG_USB_GSPCA_SPCA501=m
-+CONFIG_USB_GSPCA_SPCA505=m
-+CONFIG_USB_GSPCA_SPCA506=m
-+CONFIG_USB_GSPCA_SPCA508=m
-+CONFIG_USB_GSPCA_SPCA561=m
-+CONFIG_USB_GSPCA_SPCA1528=m
-+CONFIG_USB_GSPCA_SQ905=m
-+CONFIG_USB_GSPCA_SQ905C=m
-+CONFIG_USB_GSPCA_SQ930X=m
-+CONFIG_USB_GSPCA_STK014=m
-+CONFIG_USB_GSPCA_STK1135=m
-+CONFIG_USB_GSPCA_STV0680=m
-+CONFIG_USB_GSPCA_SUNPLUS=m
-+CONFIG_USB_GSPCA_T613=m
-+CONFIG_USB_GSPCA_TOPRO=m
-+CONFIG_USB_GSPCA_TV8532=m
-+CONFIG_USB_GSPCA_VC032X=m
-+CONFIG_USB_GSPCA_VICAM=m
-+CONFIG_USB_GSPCA_XIRLINK_CIT=m
-+CONFIG_USB_GSPCA_ZC3XX=m
-+CONFIG_USB_PWC=m
-+CONFIG_VIDEO_CPIA2=m
-+CONFIG_USB_ZR364XX=m
-+CONFIG_USB_STKWEBCAM=m
-+CONFIG_USB_S2255=m
-+CONFIG_VIDEO_USBTV=m
-+CONFIG_VIDEO_PVRUSB2=m
-+CONFIG_VIDEO_HDPVR=m
-+CONFIG_VIDEO_USBVISION=m
-+CONFIG_VIDEO_STK1160_COMMON=m
-+CONFIG_VIDEO_STK1160_AC97=y
-+CONFIG_VIDEO_GO7007=m
-+CONFIG_VIDEO_GO7007_USB=m
-+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-+CONFIG_VIDEO_AU0828=m
-+CONFIG_VIDEO_AU0828_RC=y
-+CONFIG_VIDEO_CX231XX=m
-+CONFIG_VIDEO_CX231XX_ALSA=m
-+CONFIG_VIDEO_CX231XX_DVB=m
-+CONFIG_VIDEO_TM6000=m
-+CONFIG_VIDEO_TM6000_ALSA=m
-+CONFIG_VIDEO_TM6000_DVB=m
-+CONFIG_DVB_USB=m
-+CONFIG_DVB_USB_A800=m
-+CONFIG_DVB_USB_DIBUSB_MB=m
-+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
-+CONFIG_DVB_USB_DIBUSB_MC=m
-+CONFIG_DVB_USB_DIB0700=m
-+CONFIG_DVB_USB_UMT_010=m
-+CONFIG_DVB_USB_CXUSB=m
-+CONFIG_DVB_USB_M920X=m
-+CONFIG_DVB_USB_DIGITV=m
-+CONFIG_DVB_USB_VP7045=m
-+CONFIG_DVB_USB_VP702X=m
-+CONFIG_DVB_USB_GP8PSK=m
-+CONFIG_DVB_USB_NOVA_T_USB2=m
-+CONFIG_DVB_USB_TTUSB2=m
-+CONFIG_DVB_USB_DTT200U=m
-+CONFIG_DVB_USB_OPERA1=m
-+CONFIG_DVB_USB_AF9005=m
-+CONFIG_DVB_USB_AF9005_REMOTE=m
-+CONFIG_DVB_USB_PCTV452E=m
-+CONFIG_DVB_USB_DW2102=m
-+CONFIG_DVB_USB_CINERGY_T2=m
-+CONFIG_DVB_USB_DTV5100=m
-+CONFIG_DVB_USB_FRIIO=m
-+CONFIG_DVB_USB_AZ6027=m
-+CONFIG_DVB_USB_TECHNISAT_USB2=m
-+CONFIG_DVB_USB_V2=m
-+CONFIG_DVB_USB_AF9015=m
-+CONFIG_DVB_USB_AF9035=m
-+CONFIG_DVB_USB_ANYSEE=m
-+CONFIG_DVB_USB_AU6610=m
-+CONFIG_DVB_USB_AZ6007=m
-+CONFIG_DVB_USB_CE6230=m
-+CONFIG_DVB_USB_EC168=m
-+CONFIG_DVB_USB_GL861=m
-+CONFIG_DVB_USB_LME2510=m
-+CONFIG_DVB_USB_MXL111SF=m
-+CONFIG_DVB_USB_RTL28XXU=m
-+CONFIG_DVB_USB_DVBSKY=m
-+CONFIG_SMS_USB_DRV=m
-+CONFIG_DVB_B2C2_FLEXCOP_USB=m
-+CONFIG_DVB_AS102=m
-+CONFIG_VIDEO_EM28XX=m
-+CONFIG_VIDEO_EM28XX_V4L2=m
-+CONFIG_VIDEO_EM28XX_ALSA=m
-+CONFIG_VIDEO_EM28XX_DVB=m
-+CONFIG_V4L_PLATFORM_DRIVERS=y
-+CONFIG_VIDEO_BCM2835=n
-+CONFIG_VIDEO_BCM2835_MMAL=n
-+CONFIG_RADIO_SI470X=y
-+CONFIG_USB_SI470X=m
-+CONFIG_I2C_SI470X=m
-+CONFIG_RADIO_SI4713=m
-+CONFIG_I2C_SI4713=m
-+CONFIG_USB_MR800=m
-+CONFIG_USB_DSBR=m
-+CONFIG_RADIO_SHARK=m
-+CONFIG_RADIO_SHARK2=m
-+CONFIG_USB_KEENE=m
-+CONFIG_USB_MA901=m
-+CONFIG_RADIO_TEA5764=m
-+CONFIG_RADIO_SAA7706H=m
-+CONFIG_RADIO_TEF6862=m
-+CONFIG_RADIO_WL1273=m
-+CONFIG_RADIO_WL128X=m
-+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
-+CONFIG_VIDEO_UDA1342=m
-+CONFIG_VIDEO_SONY_BTF_MPX=m
-+CONFIG_VIDEO_TVP5150=m
-+CONFIG_VIDEO_TW2804=m
-+CONFIG_VIDEO_TW9903=m
-+CONFIG_VIDEO_TW9906=m
-+CONFIG_VIDEO_OV7640=m
-+CONFIG_VIDEO_MT9V011=m
-+CONFIG_DRM=m
-+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-+CONFIG_DRM_UDL=m
-+CONFIG_DRM_VC4=m
-+CONFIG_FB=y
-+CONFIG_FB_BCM2708=y
-+CONFIG_FB_UDL=m
-+CONFIG_FB_SSD1307=m
-+CONFIG_FB_RPISENSE=m
-+# CONFIG_BACKLIGHT_GENERIC is not set
-+CONFIG_BACKLIGHT_RPI=m
-+CONFIG_BACKLIGHT_GPIO=m
-+CONFIG_FRAMEBUFFER_CONSOLE=y
-+CONFIG_LOGO=y
-+# CONFIG_LOGO_LINUX_MONO is not set
-+# CONFIG_LOGO_LINUX_VGA16 is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=m
-+CONFIG_SND_SEQUENCER=m
-+CONFIG_SND_SEQ_DUMMY=m
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_SEQUENCER_OSS=y
-+CONFIG_SND_HRTIMER=m
-+CONFIG_SND_DUMMY=m
-+CONFIG_SND_ALOOP=m
-+CONFIG_SND_VIRMIDI=m
-+CONFIG_SND_MTPAV=m
-+CONFIG_SND_SERIAL_U16550=m
-+CONFIG_SND_MPU401=m
-+CONFIG_SND_ARM=n
-+CONFIG_SND_BCM2835=n
-+CONFIG_SND_USB_AUDIO=m
-+CONFIG_SND_USB_UA101=m
-+CONFIG_SND_USB_CAIAQ=m
-+CONFIG_SND_USB_CAIAQ_INPUT=y
-+CONFIG_SND_USB_6FIRE=m
-+CONFIG_SND_SOC=m
-+CONFIG_SND_BCM2835_SOC_I2S=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
-+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
-+CONFIG_SND_BCM2708_SOC_RPI_DAC=m
-+CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
-+CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m
-+CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
-+CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m
-+CONFIG_SND_BCM2708_SOC_RASPIDAC3=m
-+CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m
-+CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m
-+CONFIG_SND_DIGIDAC1_SOUNDCARD=m
-+CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m
-+CONFIG_SND_SOC_ADAU1701=m
-+CONFIG_SND_SOC_WM8804_I2C=m
-+CONFIG_SND_SIMPLE_CARD=m
-+CONFIG_SOUND_PRIME=m
-+CONFIG_HIDRAW=y
-+CONFIG_UHID=m
-+CONFIG_HID_A4TECH=m
-+CONFIG_HID_ACRUX=m
-+CONFIG_HID_APPLE=m
-+CONFIG_HID_BELKIN=m
-+CONFIG_HID_BETOP_FF=m
-+CONFIG_HID_CHERRY=m
-+CONFIG_HID_CHICONY=m
-+CONFIG_HID_CYPRESS=m
-+CONFIG_HID_DRAGONRISE=m
-+CONFIG_HID_EMS_FF=m
-+CONFIG_HID_ELECOM=m
-+CONFIG_HID_ELO=m
-+CONFIG_HID_EZKEY=m
-+CONFIG_HID_GEMBIRD=m
-+CONFIG_HID_HOLTEK=m
-+CONFIG_HID_KEYTOUCH=m
-+CONFIG_HID_KYE=m
-+CONFIG_HID_UCLOGIC=m
-+CONFIG_HID_WALTOP=m
-+CONFIG_HID_GYRATION=m
-+CONFIG_HID_TWINHAN=m
-+CONFIG_HID_KENSINGTON=m
-+CONFIG_HID_LCPOWER=m
-+CONFIG_HID_LOGITECH=m
-+CONFIG_HID_LOGITECH_DJ=m
-+CONFIG_LOGITECH_FF=y
-+CONFIG_LOGIRUMBLEPAD2_FF=y
-+CONFIG_LOGIG940_FF=y
-+CONFIG_HID_MAGICMOUSE=m
-+CONFIG_HID_MICROSOFT=m
-+CONFIG_HID_MONTEREY=m
-+CONFIG_HID_MULTITOUCH=m
-+CONFIG_HID_NTRIG=m
-+CONFIG_HID_ORTEK=m
-+CONFIG_HID_PANTHERLORD=m
-+CONFIG_HID_PETALYNX=m
-+CONFIG_HID_PICOLCD=m
-+CONFIG_HID_ROCCAT=m
-+CONFIG_HID_SAMSUNG=m
-+CONFIG_HID_SONY=m
-+CONFIG_HID_SPEEDLINK=m
-+CONFIG_HID_SUNPLUS=m
-+CONFIG_HID_GREENASIA=m
-+CONFIG_HID_SMARTJOYPLUS=m
-+CONFIG_HID_TOPSEED=m
-+CONFIG_HID_THINGM=m
-+CONFIG_HID_THRUSTMASTER=m
-+CONFIG_HID_WACOM=m
-+CONFIG_HID_WIIMOTE=m
-+CONFIG_HID_XINMO=m
-+CONFIG_HID_ZEROPLUS=m
-+CONFIG_HID_ZYDACRON=m
-+CONFIG_HID_PID=y
-+CONFIG_USB_HIDDEV=y
-+CONFIG_USB=y
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=n
-+CONFIG_USB_DWC2=y
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_STORAGE=y
-+CONFIG_USB_STORAGE_REALTEK=m
-+CONFIG_USB_STORAGE_DATAFAB=m
-+CONFIG_USB_STORAGE_FREECOM=m
-+CONFIG_USB_STORAGE_ISD200=m
-+CONFIG_USB_STORAGE_USBAT=m
-+CONFIG_USB_STORAGE_SDDR09=m
-+CONFIG_USB_STORAGE_SDDR55=m
-+CONFIG_USB_STORAGE_JUMPSHOT=m
-+CONFIG_USB_STORAGE_ALAUDA=m
-+CONFIG_USB_STORAGE_ONETOUCH=m
-+CONFIG_USB_STORAGE_KARMA=m
-+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
-+CONFIG_USB_STORAGE_ENE_UB6250=m
-+CONFIG_USB_MDC800=m
-+CONFIG_USB_MICROTEK=m
-+CONFIG_USBIP_CORE=m
-+CONFIG_USBIP_VHCI_HCD=m
-+CONFIG_USBIP_HOST=m
-+CONFIG_USB_SERIAL=m
-+CONFIG_USB_SERIAL_GENERIC=y
-+CONFIG_USB_SERIAL_AIRCABLE=m
-+CONFIG_USB_SERIAL_ARK3116=m
-+CONFIG_USB_SERIAL_BELKIN=m
-+CONFIG_USB_SERIAL_CH341=m
-+CONFIG_USB_SERIAL_WHITEHEAT=m
-+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-+CONFIG_USB_SERIAL_CP210X=m
-+CONFIG_USB_SERIAL_CYPRESS_M8=m
-+CONFIG_USB_SERIAL_EMPEG=m
-+CONFIG_USB_SERIAL_FTDI_SIO=m
-+CONFIG_USB_SERIAL_VISOR=m
-+CONFIG_USB_SERIAL_IPAQ=m
-+CONFIG_USB_SERIAL_IR=m
-+CONFIG_USB_SERIAL_EDGEPORT=m
-+CONFIG_USB_SERIAL_EDGEPORT_TI=m
-+CONFIG_USB_SERIAL_F81232=m
-+CONFIG_USB_SERIAL_GARMIN=m
-+CONFIG_USB_SERIAL_IPW=m
-+CONFIG_USB_SERIAL_IUU=m
-+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-+CONFIG_USB_SERIAL_KEYSPAN=m
-+CONFIG_USB_SERIAL_KLSI=m
-+CONFIG_USB_SERIAL_KOBIL_SCT=m
-+CONFIG_USB_SERIAL_MCT_U232=m
-+CONFIG_USB_SERIAL_METRO=m
-+CONFIG_USB_SERIAL_MOS7720=m
-+CONFIG_USB_SERIAL_MOS7840=m
-+CONFIG_USB_SERIAL_NAVMAN=m
-+CONFIG_USB_SERIAL_PL2303=m
-+CONFIG_USB_SERIAL_OTI6858=m
-+CONFIG_USB_SERIAL_QCAUX=m
-+CONFIG_USB_SERIAL_QUALCOMM=m
-+CONFIG_USB_SERIAL_SPCP8X5=m
-+CONFIG_USB_SERIAL_SAFE=m
-+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
-+CONFIG_USB_SERIAL_SYMBOL=m
-+CONFIG_USB_SERIAL_TI=m
-+CONFIG_USB_SERIAL_CYBERJACK=m
-+CONFIG_USB_SERIAL_XIRCOM=m
-+CONFIG_USB_SERIAL_OPTION=m
-+CONFIG_USB_SERIAL_OMNINET=m
-+CONFIG_USB_SERIAL_OPTICON=m
-+CONFIG_USB_SERIAL_XSENS_MT=m
-+CONFIG_USB_SERIAL_WISHBONE=m
-+CONFIG_USB_SERIAL_SSU100=m
-+CONFIG_USB_SERIAL_QT2=m
-+CONFIG_USB_SERIAL_DEBUG=m
-+CONFIG_USB_EMI62=m
-+CONFIG_USB_EMI26=m
-+CONFIG_USB_ADUTUX=m
-+CONFIG_USB_SEVSEG=m
-+CONFIG_USB_RIO500=m
-+CONFIG_USB_LEGOTOWER=m
-+CONFIG_USB_LCD=m
-+CONFIG_USB_CYPRESS_CY7C63=m
-+CONFIG_USB_CYTHERM=m
-+CONFIG_USB_IDMOUSE=m
-+CONFIG_USB_FTDI_ELAN=m
-+CONFIG_USB_APPLEDISPLAY=m
-+CONFIG_USB_LD=m
-+CONFIG_USB_TRANCEVIBRATOR=m
-+CONFIG_USB_IOWARRIOR=m
-+CONFIG_USB_TEST=m
-+CONFIG_USB_ISIGHTFW=m
-+CONFIG_USB_YUREX=m
-+CONFIG_USB_ATM=m
-+CONFIG_USB_SPEEDTOUCH=m
-+CONFIG_USB_CXACRU=m
-+CONFIG_USB_UEAGLEATM=m
-+CONFIG_USB_XUSBATM=m
-+CONFIG_MMC=y
-+CONFIG_MMC_BLOCK_MINORS=32
-+CONFIG_MMC_BCM2835=y
-+CONFIG_MMC_BCM2835_DMA=y
-+CONFIG_MMC_BCM2835_SDHOST=y
-+CONFIG_MMC_SDHCI=y
-+CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SPI=m
-+CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_ONESHOT=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-+CONFIG_LEDS_TRIGGER_CPU=y
-+CONFIG_LEDS_TRIGGER_GPIO=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TRANSIENT=m
-+CONFIG_LEDS_TRIGGER_CAMERA=m
-+CONFIG_LEDS_TRIGGER_INPUT=y
-+CONFIG_LEDS_TRIGGER_PANIC=y
-+CONFIG_RTC_CLASS=y
-+# CONFIG_RTC_HCTOSYS is not set
-+CONFIG_RTC_DRV_DS1307=m
-+CONFIG_RTC_DRV_DS1374=m
-+CONFIG_RTC_DRV_DS1672=m
-+CONFIG_RTC_DRV_MAX6900=m
-+CONFIG_RTC_DRV_RS5C372=m
-+CONFIG_RTC_DRV_ISL1208=m
-+CONFIG_RTC_DRV_ISL12022=m
-+CONFIG_RTC_DRV_ISL12057=m
-+CONFIG_RTC_DRV_X1205=m
-+CONFIG_RTC_DRV_PCF8523=m
-+CONFIG_RTC_DRV_PCF8563=m
-+CONFIG_RTC_DRV_PCF8583=m
-+CONFIG_RTC_DRV_M41T80=m
-+CONFIG_RTC_DRV_BQ32K=m
-+CONFIG_RTC_DRV_S35390A=m
-+CONFIG_RTC_DRV_FM3130=m
-+CONFIG_RTC_DRV_RX8581=m
-+CONFIG_RTC_DRV_RX8025=m
-+CONFIG_RTC_DRV_EM3027=m
-+CONFIG_RTC_DRV_M41T93=m
-+CONFIG_RTC_DRV_M41T94=m
-+CONFIG_RTC_DRV_DS1302=m
-+CONFIG_RTC_DRV_DS1305=m
-+CONFIG_RTC_DRV_DS1390=m
-+CONFIG_RTC_DRV_R9701=m
-+CONFIG_RTC_DRV_RX4581=m
-+CONFIG_RTC_DRV_RS5C348=m
-+CONFIG_RTC_DRV_MAX6902=m
-+CONFIG_RTC_DRV_PCF2123=m
-+CONFIG_RTC_DRV_DS3232=m
-+CONFIG_RTC_DRV_PCF2127=m
-+CONFIG_RTC_DRV_RV3029C2=m
-+CONFIG_DMADEVICES=y
-+CONFIG_DMA_BCM2835=y
-+CONFIG_DMA_BCM2708=y
-+CONFIG_UIO=m
-+CONFIG_UIO_PDRV_GENIRQ=m
-+CONFIG_STAGING=y
-+CONFIG_PRISM2_USB=m
-+CONFIG_R8712U=m
-+CONFIG_R8188EU=m
-+CONFIG_R8723AU=m
-+CONFIG_VT6656=m
-+CONFIG_SPEAKUP=m
-+CONFIG_SPEAKUP_SYNTH_SOFT=m
-+CONFIG_STAGING_MEDIA=y
-+CONFIG_LIRC_STAGING=y
-+CONFIG_LIRC_IMON=m
-+CONFIG_LIRC_RPI=m
-+CONFIG_LIRC_SASEM=m
-+CONFIG_LIRC_SERIAL=m
-+CONFIG_FB_TFT=m
-+CONFIG_FB_TFT_AGM1264K_FL=m
-+CONFIG_FB_TFT_BD663474=m
-+CONFIG_FB_TFT_HX8340BN=m
-+CONFIG_FB_TFT_HX8347D=m
-+CONFIG_FB_TFT_HX8353D=m
-+CONFIG_FB_TFT_ILI9163=m
-+CONFIG_FB_TFT_ILI9320=m
-+CONFIG_FB_TFT_ILI9325=m
-+CONFIG_FB_TFT_ILI9340=m
-+CONFIG_FB_TFT_ILI9341=m
-+CONFIG_FB_TFT_ILI9481=m
-+CONFIG_FB_TFT_ILI9486=m
-+CONFIG_FB_TFT_PCD8544=m
-+CONFIG_FB_TFT_RA8875=m
-+CONFIG_FB_TFT_S6D02A1=m
-+CONFIG_FB_TFT_S6D1121=m
-+CONFIG_FB_TFT_SSD1289=m
-+CONFIG_FB_TFT_SSD1306=m
-+CONFIG_FB_TFT_SSD1331=m
-+CONFIG_FB_TFT_SSD1351=m
-+CONFIG_FB_TFT_ST7735R=m
-+CONFIG_FB_TFT_TINYLCD=m
-+CONFIG_FB_TFT_TLS8204=m
-+CONFIG_FB_TFT_UC1701=m
-+CONFIG_FB_TFT_UPD161704=m
-+CONFIG_FB_TFT_WATTEROTT=m
-+CONFIG_FB_FLEX=m
-+CONFIG_FB_TFT_FBTFT_DEVICE=m
-+CONFIG_MAILBOX=y
-+CONFIG_BCM2835_MBOX=y
-+# CONFIG_IOMMU_SUPPORT is not set
-+CONFIG_RASPBERRYPI_POWER=y
-+CONFIG_EXTCON=m
-+CONFIG_EXTCON_ARIZONA=m
-+CONFIG_IIO=m
-+CONFIG_IIO_BUFFER=y
-+CONFIG_IIO_BUFFER_CB=m
-+CONFIG_IIO_KFIFO_BUF=m
-+CONFIG_MCP320X=m
-+CONFIG_MCP3422=m
-+CONFIG_DHT11=m
-+CONFIG_PWM_BCM2835=m
-+CONFIG_PWM_PCA9685=m
-+CONFIG_RASPBERRYPI_FIRMWARE=y
-+CONFIG_EXT4_FS=y
-+CONFIG_EXT4_FS_POSIX_ACL=y
-+CONFIG_EXT4_FS_SECURITY=y
-+CONFIG_REISERFS_FS=m
-+CONFIG_REISERFS_FS_XATTR=y
-+CONFIG_REISERFS_FS_POSIX_ACL=y
-+CONFIG_REISERFS_FS_SECURITY=y
-+CONFIG_JFS_FS=m
-+CONFIG_JFS_POSIX_ACL=y
-+CONFIG_JFS_SECURITY=y
-+CONFIG_JFS_STATISTICS=y
-+CONFIG_XFS_FS=m
-+CONFIG_XFS_QUOTA=y
-+CONFIG_XFS_POSIX_ACL=y
-+CONFIG_XFS_RT=y
-+CONFIG_GFS2_FS=m
-+CONFIG_OCFS2_FS=m
-+CONFIG_BTRFS_FS=m
-+CONFIG_BTRFS_FS_POSIX_ACL=y
-+CONFIG_NILFS2_FS=m
-+CONFIG_F2FS_FS=y
-+CONFIG_FANOTIFY=y
-+CONFIG_QFMT_V1=m
-+CONFIG_QFMT_V2=m
-+CONFIG_AUTOFS4_FS=y
-+CONFIG_FUSE_FS=m
-+CONFIG_CUSE=m
-+CONFIG_OVERLAY_FS=m
-+CONFIG_FSCACHE=y
-+CONFIG_FSCACHE_STATS=y
-+CONFIG_FSCACHE_HISTOGRAM=y
-+CONFIG_CACHEFILES=y
-+CONFIG_ISO9660_FS=m
-+CONFIG_JOLIET=y
-+CONFIG_ZISOFS=y
-+CONFIG_UDF_FS=m
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-+CONFIG_NTFS_FS=m
-+CONFIG_NTFS_RW=y
-+CONFIG_TMPFS=y
-+CONFIG_TMPFS_POSIX_ACL=y
-+CONFIG_ECRYPT_FS=m
-+CONFIG_HFS_FS=m
-+CONFIG_HFSPLUS_FS=m
-+CONFIG_JFFS2_FS=m
-+CONFIG_JFFS2_SUMMARY=y
-+CONFIG_UBIFS_FS=m
-+CONFIG_SQUASHFS=m
-+CONFIG_SQUASHFS_XATTR=y
-+CONFIG_SQUASHFS_LZO=y
-+CONFIG_SQUASHFS_XZ=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3_ACL=y
-+CONFIG_NFS_V4=y
-+CONFIG_NFS_SWAP=y
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFS_FSCACHE=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3_ACL=y
-+CONFIG_NFSD_V4=y
-+CONFIG_CIFS=m
-+CONFIG_CIFS_WEAK_PW_HASH=y
-+CONFIG_CIFS_UPCALL=y
-+CONFIG_CIFS_XATTR=y
-+CONFIG_CIFS_POSIX=y
-+CONFIG_CIFS_ACL=y
-+CONFIG_CIFS_DFS_UPCALL=y
-+CONFIG_CIFS_SMB2=y
-+CONFIG_CIFS_FSCACHE=y
-+CONFIG_9P_FS=m
-+CONFIG_9P_FS_POSIX_ACL=y
-+CONFIG_NLS_DEFAULT="utf8"
-+CONFIG_NLS_CODEPAGE_437=y
-+CONFIG_NLS_CODEPAGE_737=m
-+CONFIG_NLS_CODEPAGE_775=m
-+CONFIG_NLS_CODEPAGE_850=m
-+CONFIG_NLS_CODEPAGE_852=m
-+CONFIG_NLS_CODEPAGE_855=m
-+CONFIG_NLS_CODEPAGE_857=m
-+CONFIG_NLS_CODEPAGE_860=m
-+CONFIG_NLS_CODEPAGE_861=m
-+CONFIG_NLS_CODEPAGE_862=m
-+CONFIG_NLS_CODEPAGE_863=m
-+CONFIG_NLS_CODEPAGE_864=m
-+CONFIG_NLS_CODEPAGE_865=m
-+CONFIG_NLS_CODEPAGE_866=m
-+CONFIG_NLS_CODEPAGE_869=m
-+CONFIG_NLS_CODEPAGE_936=m
-+CONFIG_NLS_CODEPAGE_950=m
-+CONFIG_NLS_CODEPAGE_932=m
-+CONFIG_NLS_CODEPAGE_949=m
-+CONFIG_NLS_CODEPAGE_874=m
-+CONFIG_NLS_ISO8859_8=m
-+CONFIG_NLS_CODEPAGE_1250=m
-+CONFIG_NLS_CODEPAGE_1251=m
-+CONFIG_NLS_ASCII=y
-+CONFIG_NLS_ISO8859_1=m
-+CONFIG_NLS_ISO8859_2=m
-+CONFIG_NLS_ISO8859_3=m
-+CONFIG_NLS_ISO8859_4=m
-+CONFIG_NLS_ISO8859_5=m
-+CONFIG_NLS_ISO8859_6=m
-+CONFIG_NLS_ISO8859_7=m
-+CONFIG_NLS_ISO8859_9=m
-+CONFIG_NLS_ISO8859_13=m
-+CONFIG_NLS_ISO8859_14=m
-+CONFIG_NLS_ISO8859_15=m
-+CONFIG_NLS_KOI8_R=m
-+CONFIG_NLS_KOI8_U=m
-+CONFIG_DLM=m
-+CONFIG_PRINTK_TIME=y
-+CONFIG_BOOT_PRINTK_DELAY=y
-+CONFIG_DEBUG_MEMORY_INIT=y
-+CONFIG_DETECT_HUNG_TASK=y
-+CONFIG_TIMER_STATS=y
-+CONFIG_IRQSOFF_TRACER=y
-+CONFIG_SCHED_TRACER=y
-+CONFIG_STACK_TRACER=y
-+CONFIG_BLK_DEV_IO_TRACE=y
-+# CONFIG_KPROBE_EVENT is not set
-+CONFIG_FUNCTION_PROFILER=y
-+CONFIG_KGDB=y
-+CONFIG_KGDB_KDB=y
-+CONFIG_KDB_KEYBOARD=y
-+CONFIG_CRYPTO_USER=m
-+CONFIG_CRYPTO_CBC=y
-+CONFIG_CRYPTO_CTS=m
-+CONFIG_CRYPTO_XTS=m
-+CONFIG_CRYPTO_XCBC=m
-+CONFIG_CRYPTO_TGR192=m
-+CONFIG_CRYPTO_WP512=m
-+CONFIG_CRYPTO_CAST5=m
-+CONFIG_CRYPTO_DES=y
-+CONFIG_CRYPTO_USER_API_SKCIPHER=m
-+CONFIG_ARM64_CRYPTO=y
-+CONFIG_CRC_ITU_T=y
-+CONFIG_LIBCRC32C=y
-+CONFIG_BCM2835_VCHIQ=n
diff --git a/target/linux/brcm2708/patches-4.14/950-0098-ARM64-Make-it-work-again-on-4.9-1790.patch b/target/linux/brcm2708/patches-4.14/950-0098-ARM64-Make-it-work-again-on-4.9-1790.patch
deleted file mode 100644
index eab93774b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0098-ARM64-Make-it-work-again-on-4.9-1790.patch
+++ /dev/null
@@ -1,416 +0,0 @@
-From 3982be6e386a0c2ca0530ca5fc09f37bcb0f2da6 Mon Sep 17 00:00:00 2001
-From: Electron752 <mzoran@crowfest.net>
-Date: Thu, 12 Jan 2017 07:07:08 -0800
-Subject: [PATCH 098/454] ARM64: Make it work again on 4.9 (#1790)
-
-* Invoke the dtc compiler with the same options used in arm mode.
-* ARM64 now uses the bcm2835 platform just like ARM32.
-* ARM64: Update bcmrpi3_defconfig
-
-Signed-off-by: Michael Zoran <mzoran@crowfest.net>
----
- arch/arm64/Kconfig.platforms          |  28 ------
- arch/arm64/boot/dts/broadcom/Makefile |  10 ++-
- arch/arm64/boot/dts/overlays          |   1 +
- arch/arm64/configs/bcmrpi3_defconfig  | 125 ++++++++------------------
- 4 files changed, 48 insertions(+), 116 deletions(-)
- create mode 120000 arch/arm64/boot/dts/overlays
-
-diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
-index 2b9aefe89e94..19ff97b7efe6 100644
---- a/arch/arm64/Kconfig.platforms
-+++ b/arch/arm64/Kconfig.platforms
-@@ -1,33 +1,5 @@
- menu "Platform selection"
- 
--config MACH_BCM2709
--        bool
--
--config ARCH_BCM2709
--        bool "Broadcom BCM2709 family"
--        select MACH_BCM2709
--        select HAVE_SMP
--        select ARM_AMBA
--        select COMMON_CLK
--        select ARCH_HAS_CPUFREQ
--        select GENERIC_CLOCKEVENTS
--        select MULTI_IRQ_HANDLER
--        select SPARSE_IRQ
--        select MFD_SYSCON
--        select VC4
--        select USE_OF
--        select ARCH_REQUIRE_GPIOLIB
--        select PINCTRL
--        select PINCTRL_BCM2835
--        help
--          This enables support for Broadcom BCM2709 boards.
--
--config ARCH_ACTIONS
--	bool "Actions Semi Platforms"
--	select OWL_TIMER
--	help
--	  This enables support for the Actions Semiconductor S900 SoC family.
--
- config ARCH_SUNXI
- 	bool "Allwinner sunxi 64-bit SoC Family"
- 	select ARCH_HAS_RESET_CONTROLLER
-diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
-index d54218055506..3adfeab86f3f 100644
---- a/arch/arm64/boot/dts/broadcom/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/Makefile
-@@ -1,8 +1,16 @@
- # SPDX-License-Identifier: GPL-2.0
-+# Enable fixups to support overlays on BCM2835 platforms
-+
-+ifeq ($(CONFIG_ARCH_BCM2835),y)
-+DTC_FLAGS ?= -@ -H epapr
-+endif
-+
- dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
- dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-3-b.dtb
-+dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb
-+
-+dts-dirs += ../overlays
- 
--dts-dirs	+= northstar2
- dts-dirs	+= stingray
- always		:= $(dtb-y)
- subdir-y	:= $(dts-dirs)
-diff --git a/arch/arm64/boot/dts/overlays b/arch/arm64/boot/dts/overlays
-new file mode 120000
-index 000000000000..ded08646b6f6
---- /dev/null
-+++ b/arch/arm64/boot/dts/overlays
-@@ -0,0 +1 @@
-+../../../arm/boot/dts/overlays
-\ No newline at end of file
-diff --git a/arch/arm64/configs/bcmrpi3_defconfig b/arch/arm64/configs/bcmrpi3_defconfig
-index e6b09fafa27e..c7e891d72969 100644
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -1,52 +1,9 @@
--# CONFIG_ARM_PATCH_PHYS_VIRT is not set
--CONFIG_PHYS_OFFSET=0
- CONFIG_LOCALVERSION="-v8"
- # CONFIG_LOCALVERSION_AUTO is not set
--CONFIG_64BIT=y
- CONFIG_SYSVIPC=y
- CONFIG_POSIX_MQUEUE=y
- CONFIG_NO_HZ=y
- CONFIG_HIGH_RES_TIMERS=y
--
--#
--# ARM errata workarounds via the alternatives framework
--#
--CONFIG_ARM64_ERRATUM_826319=n
--CONFIG_ARM64_ERRATUM_827319=n
--CONFIG_ARM64_ERRATUM_824069=n
--CONFIG_ARM64_ERRATUM_819472=n
--CONFIG_ARM64_ERRATUM_832075=n
--CONFIG_ARM64_ERRATUM_845719=n
--CONFIG_ARM64_ERRATUM_843419=n
--CONFIG_CAVIUM_ERRATUM_22375=n
--CONFIG_CAVIUM_ERRATUM_23154=n
--CONFIG_CAVIUM_ERRATUM_27456=n
--CONFIG_ARM64_4K_PAGES=y
--CONFIG_ARM64_VA_BITS_39=y
--CONFIG_ARM64_VA_BITS=39
--CONFIG_SCHED_MC=y
--CONFIG_NR_CPUS=4
--CONFIG_HOTPLUG_CPU=y
--CONFIG_ARMV8_DEPRECATED=y
--CONFIG_SWP_EMULATION=y
--CONFIG_CP15_BARRIER_EMULATION=y
--CONFIG_SETEND_EMULATION=y
--
--#
--# ARMv8.1 architectural features
--#
--CONFIG_ARM64_HW_AFDBM=y
--CONFIG_ARM64_PAN=y
--CONFIG_ARM64_LSE_ATOMICS=y
--CONFIG_ARM64_VHE=y
--
--#
--# ARMv8.2 architectural features
--#
--CONFIG_ARM64_UAO=y
--CONFIG_ARM64_MODULE_CMODEL_LARGE=n
--CONFIG_RANDOMIZE_BASE=n
--
- CONFIG_BSD_PROCESS_ACCT=y
- CONFIG_BSD_PROCESS_ACCT_V3=y
- CONFIG_TASKSTATS=y
-@@ -55,7 +12,6 @@ CONFIG_TASK_XACCT=y
- CONFIG_TASK_IO_ACCOUNTING=y
- CONFIG_IKCONFIG=m
- CONFIG_IKCONFIG_PROC=y
--CONFIG_NMI_LOG_BUF_SHIFT=12
- CONFIG_MEMCG=y
- CONFIG_BLK_CGROUP=y
- CONFIG_CGROUP_FREEZER=y
-@@ -69,54 +25,49 @@ CONFIG_BLK_DEV_INITRD=y
- CONFIG_EMBEDDED=y
- # CONFIG_COMPAT_BRK is not set
- CONFIG_PROFILING=y
--CONFIG_OPROFILE=m
- CONFIG_KPROBES=y
- CONFIG_JUMP_LABEL=y
- CONFIG_MODULES=y
- CONFIG_MODULE_UNLOAD=y
- CONFIG_MODVERSIONS=y
- CONFIG_MODULE_SRCVERSION_ALL=y
--CONFIG_TRIM_UNUSED_KSYMS=y
- CONFIG_BLK_DEV_THROTTLING=y
- CONFIG_PARTITION_ADVANCED=y
- CONFIG_MAC_PARTITION=y
- CONFIG_CFQ_GROUP_IOSCHED=y
--CONFIG_ARCH_BCM2709=y
--# CONFIG_CACHE_L2X0 is not set
--CONFIG_SMP=y
--CONFIG_HAVE_ARM_ARCH_TIMER=y
--CONFIG_VMSPLIT_2G=y
--CONFIG_PREEMPT_VOLUNTARY=y
--CONFIG_AEABI=y
--CONFIG_OABI_COMPAT=y
--# CONFIG_CPU_SW_DOMAIN_PAN is not set
-+CONFIG_ARCH_BCM2835=y
-+# CONFIG_CAVIUM_ERRATUM_22375 is not set
-+# CONFIG_CAVIUM_ERRATUM_23154 is not set
-+# CONFIG_CAVIUM_ERRATUM_27456 is not set
-+CONFIG_SCHED_MC=y
-+CONFIG_NR_CPUS=4
-+CONFIG_PREEMPT=y
-+CONFIG_HZ_1000=y
- CONFIG_CLEANCACHE=y
- CONFIG_FRONTSWAP=y
- CONFIG_CMA=y
- CONFIG_ZSMALLOC=m
- CONFIG_PGTABLE_MAPPING=y
--CONFIG_UACCESS_WITH_MEMCPY=y
- CONFIG_SECCOMP=y
--# CONFIG_ATAGS is not set
--CONFIG_ZBOOT_ROM_TEXT=0x0
--CONFIG_ZBOOT_ROM_BSS=0x0
-+CONFIG_ARMV8_DEPRECATED=y
-+CONFIG_SWP_EMULATION=y
-+CONFIG_CP15_BARRIER_EMULATION=y
-+CONFIG_SETEND_EMULATION=y
- CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
-+CONFIG_BINFMT_MISC=y
-+CONFIG_COMPAT=y
-+# CONFIG_SUSPEND is not set
-+CONFIG_PM=y
-+CONFIG_CPU_IDLE=y
-+CONFIG_ARM_CPUIDLE=y
- CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_STAT=y
- CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
- CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
- CONFIG_CPU_FREQ_GOV_USERSPACE=y
- CONFIG_CPU_FREQ_GOV_ONDEMAND=y
- CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
- CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
--CONFIG_VFP=y
--CONFIG_NEON=y
--CONFIG_KERNEL_MODE_NEON=y
--CONFIG_BINFMT_MISC=m
--CONFIG_COMPAT=y
--CONFIG_SYSVIPC_COMPAT=y
--
--# CONFIG_SUSPEND is not set
--CONFIG_PM=y
- CONFIG_NET=y
- CONFIG_PACKET=y
- CONFIG_UNIX=y
-@@ -437,6 +388,7 @@ CONFIG_BT_MRVL=m
- CONFIG_BT_MRVL_SDIO=m
- CONFIG_BT_ATH3K=m
- CONFIG_BT_WILINK=m
-+CONFIG_CFG80211=m
- CONFIG_MAC80211=m
- CONFIG_MAC80211_MESH=y
- CONFIG_WIMAX=m
-@@ -490,7 +442,6 @@ CONFIG_BONDING=m
- CONFIG_DUMMY=m
- CONFIG_IFB=m
- CONFIG_MACVLAN=m
--CONFIG_IPVLAN=m
- CONFIG_VXLAN=m
- CONFIG_NETCONSOLE=m
- CONFIG_TUN=m
-@@ -579,8 +530,6 @@ CONFIG_RT2800USB_RT3573=y
- CONFIG_RT2800USB_RT53XX=y
- CONFIG_RT2800USB_RT55XX=y
- CONFIG_RT2800USB_UNKNOWN=y
--CONFIG_RTL8187=m
--CONFIG_RTL8192CU=n
- CONFIG_USB_ZD1201=m
- CONFIG_ZD1211RW=m
- CONFIG_MAC80211_HWSIM=m
-@@ -606,7 +555,7 @@ CONFIG_JOYSTICK_RPISENSE=m
- CONFIG_INPUT_TOUCHSCREEN=y
- CONFIG_TOUCHSCREEN_ADS7846=m
- CONFIG_TOUCHSCREEN_EGALAX=m
--CONFIG_TOUCHSCREEN_FT6236=m
-+CONFIG_TOUCHSCREEN_EKTF2127=m
- CONFIG_TOUCHSCREEN_RPI_FT5406=m
- CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
- CONFIG_TOUCHSCREEN_STMPE=m
-@@ -626,10 +575,8 @@ CONFIG_SERIO_RAW=m
- CONFIG_GAMEPORT=m
- CONFIG_GAMEPORT_NS558=m
- CONFIG_GAMEPORT_L4=m
--CONFIG_BRCM_CHAR_DRIVERS=n
--CONFIG_BCM_VC_CMA=n
--CONFIG_BCM_VCIO=n
--CONFIG_BCM_VC_SM=n
-+# CONFIG_BCM2835_DEVGPIOMEM is not set
-+# CONFIG_BCM2835_SMI_DEV is not set
- # CONFIG_LEGACY_PTYS is not set
- # CONFIG_DEVKMEM is not set
- CONFIG_SERIAL_8250=y
-@@ -638,6 +585,9 @@ CONFIG_SERIAL_8250_CONSOLE=y
- # CONFIG_SERIAL_8250_DMA is not set
- CONFIG_SERIAL_8250_NR_UARTS=1
- CONFIG_SERIAL_8250_RUNTIME_UARTS=0
-+CONFIG_SERIAL_8250_EXTENDED=y
-+CONFIG_SERIAL_8250_SHARE_IRQ=y
-+CONFIG_SERIAL_8250_BCM2835AUX=y
- CONFIG_SERIAL_OF_PLATFORM=y
- CONFIG_SERIAL_AMBA_PL011=y
- CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-@@ -650,6 +600,7 @@ CONFIG_I2C=y
- CONFIG_I2C_CHARDEV=m
- CONFIG_I2C_MUX_PCA954x=m
- CONFIG_I2C_BCM2708=m
-+CONFIG_I2C_BCM2835=m
- CONFIG_I2C_GPIO=m
- CONFIG_SPI=y
- CONFIG_SPI_BCM2835=m
-@@ -681,13 +632,13 @@ CONFIG_W1_SLAVE_DS2780=m
- CONFIG_W1_SLAVE_DS2781=m
- CONFIG_W1_SLAVE_DS28E04=m
- CONFIG_W1_SLAVE_BQ27000=m
--CONFIG_BATTERY_DS2760=m
--CONFIG_POWER_RESET=y
- CONFIG_POWER_RESET_GPIO=y
-+CONFIG_BATTERY_DS2760=m
- CONFIG_HWMON=m
- CONFIG_SENSORS_LM75=m
- CONFIG_SENSORS_SHT21=m
- CONFIG_SENSORS_SHTC1=m
-+CONFIG_SENSORS_INA2XX=m
- CONFIG_THERMAL=y
- CONFIG_THERMAL_BCM2835=y
- CONFIG_WATCHDOG=y
-@@ -835,8 +786,6 @@ CONFIG_VIDEO_EM28XX_V4L2=m
- CONFIG_VIDEO_EM28XX_ALSA=m
- CONFIG_VIDEO_EM28XX_DVB=m
- CONFIG_V4L_PLATFORM_DRIVERS=y
--CONFIG_VIDEO_BCM2835=n
--CONFIG_VIDEO_BCM2835_MMAL=n
- CONFIG_RADIO_SI470X=y
- CONFIG_USB_SI470X=m
- CONFIG_I2C_SI470X=m
-@@ -892,8 +841,6 @@ CONFIG_SND_VIRMIDI=m
- CONFIG_SND_MTPAV=m
- CONFIG_SND_SERIAL_U16550=m
- CONFIG_SND_MPU401=m
--CONFIG_SND_ARM=n
--CONFIG_SND_BCM2835=n
- CONFIG_SND_USB_AUDIO=m
- CONFIG_SND_USB_UA101=m
- CONFIG_SND_USB_CAIAQ=m
-@@ -916,7 +863,10 @@ CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m
- CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m
- CONFIG_SND_DIGIDAC1_SOUNDCARD=m
- CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m
-+CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m
-+CONFIG_SND_PISOUND=m
- CONFIG_SND_SOC_ADAU1701=m
-+CONFIG_SND_SOC_AK4554=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
- CONFIG_SOUND_PRIME=m
-@@ -979,8 +929,6 @@ CONFIG_USB_HIDDEV=y
- CONFIG_USB=y
- CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
- CONFIG_USB_MON=m
--CONFIG_USB_DWCOTG=n
--CONFIG_USB_DWC2=y
- CONFIG_USB_PRINTER=m
- CONFIG_USB_STORAGE=y
- CONFIG_USB_STORAGE_REALTEK=m
-@@ -1001,6 +949,7 @@ CONFIG_USB_MICROTEK=m
- CONFIG_USBIP_CORE=m
- CONFIG_USBIP_VHCI_HCD=m
- CONFIG_USBIP_HOST=m
-+CONFIG_USB_DWC2=y
- CONFIG_USB_SERIAL=m
- CONFIG_USB_SERIAL_GENERIC=y
- CONFIG_USB_SERIAL_AIRCABLE=m
-@@ -1096,6 +1045,7 @@ CONFIG_LEDS_TRIGGER_INPUT=y
- CONFIG_LEDS_TRIGGER_PANIC=y
- CONFIG_RTC_CLASS=y
- # CONFIG_RTC_HCTOSYS is not set
-+CONFIG_RTC_DRV_ABX80X=m
- CONFIG_RTC_DRV_DS1307=m
- CONFIG_RTC_DRV_DS1374=m
- CONFIG_RTC_DRV_DS1672=m
-@@ -1103,7 +1053,6 @@ CONFIG_RTC_DRV_MAX6900=m
- CONFIG_RTC_DRV_RS5C372=m
- CONFIG_RTC_DRV_ISL1208=m
- CONFIG_RTC_DRV_ISL12022=m
--CONFIG_RTC_DRV_ISL12057=m
- CONFIG_RTC_DRV_X1205=m
- CONFIG_RTC_DRV_PCF8523=m
- CONFIG_RTC_DRV_PCF8563=m
-@@ -1137,7 +1086,6 @@ CONFIG_STAGING=y
- CONFIG_PRISM2_USB=m
- CONFIG_R8712U=m
- CONFIG_R8188EU=m
--CONFIG_R8723AU=m
- CONFIG_VT6656=m
- CONFIG_SPEAKUP=m
- CONFIG_SPEAKUP_SYNTH_SOFT=m
-@@ -1153,6 +1101,7 @@ CONFIG_FB_TFT_BD663474=m
- CONFIG_FB_TFT_HX8340BN=m
- CONFIG_FB_TFT_HX8347D=m
- CONFIG_FB_TFT_HX8353D=m
-+CONFIG_FB_TFT_HX8357D=m
- CONFIG_FB_TFT_ILI9163=m
- CONFIG_FB_TFT_ILI9320=m
- CONFIG_FB_TFT_ILI9325=m
-@@ -1176,6 +1125,7 @@ CONFIG_FB_TFT_UPD161704=m
- CONFIG_FB_TFT_WATTEROTT=m
- CONFIG_FB_FLEX=m
- CONFIG_FB_TFT_FBTFT_DEVICE=m
-+# CONFIG_BCM2708_VCHIQ is not set
- CONFIG_MAILBOX=y
- CONFIG_BCM2835_MBOX=y
- # CONFIG_IOMMU_SUPPORT is not set
-@@ -1189,6 +1139,7 @@ CONFIG_IIO_KFIFO_BUF=m
- CONFIG_MCP320X=m
- CONFIG_MCP3422=m
- CONFIG_DHT11=m
-+CONFIG_HTU21=m
- CONFIG_PWM_BCM2835=m
- CONFIG_PWM_PCA9685=m
- CONFIG_RASPBERRYPI_FIRMWARE=y
-@@ -1309,6 +1260,7 @@ CONFIG_BOOT_PRINTK_DELAY=y
- CONFIG_DEBUG_MEMORY_INIT=y
- CONFIG_DETECT_HUNG_TASK=y
- CONFIG_TIMER_STATS=y
-+CONFIG_LATENCYTOP=y
- CONFIG_IRQSOFF_TRACER=y
- CONFIG_SCHED_TRACER=y
- CONFIG_STACK_TRACER=y
-@@ -1331,4 +1283,3 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=m
- CONFIG_ARM64_CRYPTO=y
- CONFIG_CRC_ITU_T=y
- CONFIG_LIBCRC32C=y
--CONFIG_BCM2835_VCHIQ=n
--- 
-2.19.2
-
diff --git a/target/linux/brcm2708/patches-4.14/950-0099-ARM64-Enable-HDMI-audio-and-vc04_services-in-bcmrpi3.patch b/target/linux/brcm2708/patches-4.14/950-0099-ARM64-Enable-HDMI-audio-and-vc04_services-in-bcmrpi3.patch
deleted file mode 100644
index e72109d5f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0099-ARM64-Enable-HDMI-audio-and-vc04_services-in-bcmrpi3.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From a1285856b4182d099c8e3d56700cec02dca7c49b Mon Sep 17 00:00:00 2001
-From: Michael Zoran <mzoran@crowfest.net>
-Date: Thu, 12 Jan 2017 19:10:07 -0800
-Subject: [PATCH 099/454] ARM64: Enable HDMI audio and vc04_services in
- bcmrpi3_defconfig
-
-Signed-off-by: Michael Zoran <mzoran@crowfest.net>
----
- arch/arm64/configs/bcmrpi3_defconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -841,6 +841,7 @@ CONFIG_SND_VIRMIDI=m
- CONFIG_SND_MTPAV=m
- CONFIG_SND_SERIAL_U16550=m
- CONFIG_SND_MPU401=m
-+CONFIG_SND_BCM2835=m
- CONFIG_SND_USB_AUDIO=m
- CONFIG_SND_USB_UA101=m
- CONFIG_SND_USB_CAIAQ=m
-@@ -1125,7 +1126,6 @@ CONFIG_FB_TFT_UPD161704=m
- CONFIG_FB_TFT_WATTEROTT=m
- CONFIG_FB_FLEX=m
- CONFIG_FB_TFT_FBTFT_DEVICE=m
--# CONFIG_BCM2708_VCHIQ is not set
- CONFIG_MAILBOX=y
- CONFIG_BCM2835_MBOX=y
- # CONFIG_IOMMU_SUPPORT is not set
diff --git a/target/linux/brcm2708/patches-4.14/950-0100-ARM64-Run-bcmrpi3_defconfig-through-savedefconfig.patch b/target/linux/brcm2708/patches-4.14/950-0100-ARM64-Run-bcmrpi3_defconfig-through-savedefconfig.patch
deleted file mode 100644
index 3bd5f9e7b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0100-ARM64-Run-bcmrpi3_defconfig-through-savedefconfig.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 44a2cdaba5c5dfa8b580054f4d8576633c7d88f8 Mon Sep 17 00:00:00 2001
-From: Michael Zoran <mzoran@crowfest.net>
-Date: Thu, 12 Jan 2017 19:14:03 -0800
-Subject: [PATCH 100/454] ARM64: Run bcmrpi3_defconfig through savedefconfig.
-
-Signed-off-by: Michael Zoran <mzoran@crowfest.net>
----
- arch/arm64/configs/bcmrpi3_defconfig | 5 -----
- 1 file changed, 5 deletions(-)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -113,8 +113,6 @@ CONFIG_NF_CONNTRACK=m
- CONFIG_NF_CONNTRACK_ZONES=y
- CONFIG_NF_CONNTRACK_EVENTS=y
- CONFIG_NF_CONNTRACK_TIMESTAMP=y
--CONFIG_NF_CT_PROTO_DCCP=m
--CONFIG_NF_CT_PROTO_UDPLITE=m
- CONFIG_NF_CONNTRACK_AMANDA=m
- CONFIG_NF_CONNTRACK_FTP=m
- CONFIG_NF_CONNTRACK_H323=m
-@@ -177,7 +175,6 @@ CONFIG_NETFILTER_XT_MATCH_QUOTA=m
- CONFIG_NETFILTER_XT_MATCH_RATEEST=m
- CONFIG_NETFILTER_XT_MATCH_REALM=m
- CONFIG_NETFILTER_XT_MATCH_RECENT=m
--CONFIG_NETFILTER_XT_MATCH_SOCKET=m
- CONFIG_NETFILTER_XT_MATCH_STATE=m
- CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
- CONFIG_NETFILTER_XT_MATCH_STRING=m
-@@ -578,7 +575,6 @@ CONFIG_GAMEPORT_L4=m
- # CONFIG_BCM2835_DEVGPIOMEM is not set
- # CONFIG_BCM2835_SMI_DEV is not set
- # CONFIG_LEGACY_PTYS is not set
--# CONFIG_DEVKMEM is not set
- CONFIG_SERIAL_8250=y
- # CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
- CONFIG_SERIAL_8250_CONSOLE=y
-@@ -1095,7 +1091,6 @@ CONFIG_LIRC_STAGING=y
- CONFIG_LIRC_IMON=m
- CONFIG_LIRC_RPI=m
- CONFIG_LIRC_SASEM=m
--CONFIG_LIRC_SERIAL=m
- CONFIG_FB_TFT=m
- CONFIG_FB_TFT_AGM1264K_FL=m
- CONFIG_FB_TFT_BD663474=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0101-ARM64-Enable-Kernel-Address-Space-Randomization-1792.patch b/target/linux/brcm2708/patches-4.14/950-0101-ARM64-Enable-Kernel-Address-Space-Randomization-1792.patch
deleted file mode 100644
index 9d5aca948..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0101-ARM64-Enable-Kernel-Address-Space-Randomization-1792.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From e490dd44e4f57da93ef4c42c76dbbbd4fd3124d2 Mon Sep 17 00:00:00 2001
-From: Electron752 <mzoran@crowfest.net>
-Date: Sat, 14 Jan 2017 02:54:26 -0800
-Subject: [PATCH 101/454] ARM64: Enable Kernel Address Space Randomization
- (#1792)
-
-Randomization allows the mapping between virtual addresses and physical
-address to be different on each boot.  This makes it more difficult
-to exploit security vulnerabilities that require knowledge of fixed
-hardware addresses.
-
-The firmware generates a 8 byte random number during bootup and stores
-it in the device tree under chosen/kaslr-seed. This number is used
-to randomize the address mapping.
-
-This change enables this feature in the build configuration for ARM64.
-
-Signed-off-by: Michael Zoran <mzoran@crowfest.net>
----
- arch/arm64/configs/bcmrpi3_defconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -53,6 +53,7 @@ CONFIG_ARMV8_DEPRECATED=y
- CONFIG_SWP_EMULATION=y
- CONFIG_CP15_BARRIER_EMULATION=y
- CONFIG_SETEND_EMULATION=y
-+CONFIG_RANDOMIZE_BASE=y
- CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
- CONFIG_BINFMT_MISC=y
- CONFIG_COMPAT=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0102-ARM64-DWC_OTG-Port-dwc_otg-driver-to-ARM64.patch b/target/linux/brcm2708/patches-4.14/950-0102-ARM64-DWC_OTG-Port-dwc_otg-driver-to-ARM64.patch
deleted file mode 100644
index 18594a3c8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0102-ARM64-DWC_OTG-Port-dwc_otg-driver-to-ARM64.patch
+++ /dev/null
@@ -1,329 +0,0 @@
-From c9a1f4547556a531c4fd61ccde08391ec0ad390c Mon Sep 17 00:00:00 2001
-From: Michael Zoran <mzoran@crowfest.net>
-Date: Sat, 14 Jan 2017 21:33:51 -0800
-Subject: [PATCH 102/454] ARM64/DWC_OTG: Port dwc_otg driver to ARM64
-
-In ARM64, the FIQ mechanism used by this driver is not current
-implemented.   As a workaround, reqular IRQ is used instead
-of FIQ.
-
-In a separate change, the IRQ-CPU mapping is round robined
-on ARM64 to increase concurrency and allow multiple interrupts
-to be serviced at a time.  This reduces the need for FIQ.
-
-Tests Run:
-
-This mechanism is most likely to break when multiple USB devices
-are attached at the same time.  So the system was tested under
-stress.
-
-Devices:
-
-1. USB Speakers playing back a FLAC audio through VLC
-   at 96KHz.(Higher then typically, but supported on my speakers).
-
-2. sftp transferring large files through the buildin ethernet
-   connection which is connected through USB.
-
-3. Keyboard and mouse attached and being used.
-
-Although I do occasionally hear some glitches, the music seems to
-play quite well.
-
-Signed-off-by: Michael Zoran <mzoran@crowfest.net>
----
- drivers/usb/host/dwc_otg/Makefile            |  3 +
- drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c   | 17 +++++
- drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h   | 24 +++++++
- drivers/usb/host/dwc_otg/dwc_otg_hcd.c       |  4 ++
- drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h    |  4 ++
- drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c  |  3 +-
- drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 72 ++++++++++++++++++++
- drivers/usb/host/dwc_otg/dwc_otg_os_dep.h    |  2 +
- 8 files changed, 128 insertions(+), 1 deletion(-)
-
---- a/drivers/usb/host/dwc_otg/Makefile
-+++ b/drivers/usb/host/dwc_otg/Makefile
-@@ -37,7 +37,10 @@ dwc_otg-objs	+= dwc_otg_pcd_linux.o dwc_
- dwc_otg-objs	+= dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
- dwc_otg-objs	+= dwc_otg_adp.o
- dwc_otg-objs	+= dwc_otg_fiq_fsm.o
-+ifneq ($(CONFIG_ARM64),y)
- dwc_otg-objs	+= dwc_otg_fiq_stub.o
-+endif
-+
- ifneq ($(CFI),)
- dwc_otg-objs	+= dwc_otg_cfi.o
- endif
---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-@@ -74,6 +74,21 @@ void notrace _fiq_print(enum fiq_debug_l
- 	}
- }
- 
-+
-+#ifdef CONFIG_ARM64
-+
-+inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
-+{
-+	spin_lock((spinlock_t *)lock);
-+}
-+
-+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
-+{
-+	spin_unlock((spinlock_t *)lock);
-+}
-+
-+#else
-+
- /**
-  * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock
-  * Must be called with local interrupts and FIQ disabled.
-@@ -121,6 +136,8 @@ inline void fiq_fsm_spin_unlock(fiq_lock
- inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { }
- #endif
- 
-+#endif
-+
- /**
-  * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction
-  * @channel: channel to re-enable
---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
-@@ -127,6 +127,12 @@ enum fiq_debug_level {
- 	FIQDBG_PORTHUB = (1 << 3),
- };
- 
-+#ifdef CONFIG_ARM64
-+
-+typedef spinlock_t fiq_lock_t;
-+
-+#else
-+
- typedef struct {
- 	union {
- 		uint32_t slock;
-@@ -137,6 +143,8 @@ typedef struct {
- 	};
- } fiq_lock_t;
- 
-+#endif
-+
- struct fiq_state;
- 
- extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);
-@@ -357,6 +365,22 @@ struct fiq_state {
- 	struct fiq_channel_state channel[0];
- };
- 
-+#ifdef CONFIG_ARM64
-+
-+#ifdef local_fiq_enable
-+#undef local_fiq_enable
-+#endif
-+
-+#ifdef local_fiq_disable
-+#undef local_fiq_disable
-+#endif
-+
-+extern void local_fiq_enable(void);
-+
-+extern void local_fiq_disable(void);
-+
-+#endif
-+
- extern void fiq_fsm_spin_lock(fiq_lock_t *lock);
- 
- extern void fiq_fsm_spin_unlock(fiq_lock_t *lock);
---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
-@@ -1000,6 +1000,10 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd
- 		}
- 		DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
- 
-+#ifdef CONFIG_ARM64
-+		spin_lock_init(&hcd->fiq_state->lock);
-+#endif
-+
- 		for (i = 0; i < num_channels; i++) {
- 			hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
- 		}
---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
-@@ -116,7 +116,11 @@ extern int32_t dwc_otg_hcd_handle_intr(d
- /** This function is used to handle the fast interrupt
-  *
-  */
-+#ifdef CONFIG_ARM64
-+extern void dwc_otg_hcd_handle_fiq(void);
-+#else
- extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);
-+#endif
- 
- /**
-  * Returns private data set by
---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
-@@ -36,8 +36,9 @@
- #include "dwc_otg_regs.h"
- 
- #include <linux/jiffies.h>
-+#ifdef CONFIG_ARM
- #include <asm/fiq.h>
--
-+#endif
- 
- extern bool microframe_schedule;
- 
---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
-@@ -51,7 +51,9 @@
- #include <linux/dma-mapping.h>
- #include <linux/version.h>
- #include <asm/io.h>
-+#ifdef CONFIG_ARM
- #include <asm/fiq.h>
-+#endif
- #include <linux/usb.h>
- #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
- #include <../drivers/usb/core/hcd.h>
-@@ -71,6 +73,13 @@
- #include "dwc_otg_driver.h"
- #include "dwc_otg_hcd.h"
- 
-+#ifndef __virt_to_bus
-+#define __virt_to_bus	__virt_to_phys
-+#define __bus_to_virt	__phys_to_virt
-+#define __pfn_to_bus(x)	__pfn_to_phys(x)
-+#define __bus_to_pfn(x)	__phys_to_pfn(x)
-+#endif
-+
- extern unsigned char  _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;
- 
- /**
-@@ -395,14 +404,49 @@ static struct dwc_otg_hcd_function_ops h
- 	.get_b_hnp_enable = _get_b_hnp_enable,
- };
- 
-+#ifdef CONFIG_ARM64
-+
-+static int simfiq_irq = -1;
-+
-+void local_fiq_enable(void)
-+{
-+	if (simfiq_irq >= 0)
-+		enable_irq(simfiq_irq);
-+}
-+
-+void local_fiq_disable(void)
-+{
-+	if (simfiq_irq >= 0)
-+		disable_irq(simfiq_irq);
-+}
-+
-+irqreturn_t fiq_irq_handler(int irq, void *dev_id)
-+{
-+	dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)dev_id;
-+
-+	if (fiq_fsm_enable)
-+		dwc_otg_fiq_fsm(dwc_otg_hcd->fiq_state, dwc_otg_hcd->core_if->core_params->host_channels);
-+	else
-+		dwc_otg_fiq_nop(dwc_otg_hcd->fiq_state);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+#else
- static struct fiq_handler fh = {
-   .name = "usb_fiq",
- };
- 
-+#endif
-+
- static void hcd_init_fiq(void *cookie)
- {
- 	dwc_otg_device_t *otg_dev = cookie;
- 	dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
-+#ifdef CONFIG_ARM64
-+	int retval = 0;
-+	int irq;
-+#else
- 	struct pt_regs regs;
- 	int irq;
- 
-@@ -430,6 +474,7 @@ static void hcd_init_fiq(void *cookie)
- 
- //		__show_regs(&regs);
- 	set_fiq_regs(&regs);
-+#endif
- 
- 	//Set the mphi periph to  the required registers
- 	dwc_otg_hcd->fiq_state->mphi_regs.base    = otg_dev->os_dep.mphi_base;
-@@ -448,6 +493,23 @@ static void hcd_init_fiq(void *cookie)
- 		DWC_WARN("MPHI periph has NOT been enabled");
- #endif
- 	// Enable FIQ interrupt from USB peripheral
-+#ifdef CONFIG_ARM64
-+	irq = platform_get_irq(otg_dev->os_dep.platformdev, 1);
-+
-+	if (irq < 0) {
-+		DWC_ERROR("Can't get SIM-FIQ irq");
-+		return;
-+	}
-+
-+	retval = request_irq(irq, fiq_irq_handler, 0, "dwc_otg_sim-fiq", dwc_otg_hcd);
-+
-+	if (retval < 0) {
-+		DWC_ERROR("Unable to request SIM-FIQ irq\n");
-+		return;
-+	}
-+
-+	simfiq_irq = irq;
-+#else
- #ifdef CONFIG_MULTI_IRQ_HANDLER
- 	irq = platform_get_irq(otg_dev->os_dep.platformdev, 1);
- #else
-@@ -459,6 +521,8 @@ static void hcd_init_fiq(void *cookie)
- 	}
- 	enable_fiq(irq);
- 	local_fiq_enable();
-+#endif
-+
- }
- 
- /**
-@@ -521,6 +585,13 @@ int hcd_init(dwc_bus_dev_t *_dev)
- 	otg_dev->hcd = dwc_otg_hcd;
- 	otg_dev->hcd->otg_dev = otg_dev;
- 
-+#ifdef CONFIG_ARM64
-+	if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if))
-+		goto error2;
-+
-+	if (fiq_enable)
-+		hcd_init_fiq(otg_dev);
-+#else
- 	if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
- 		goto error2;
- 	}
-@@ -533,6 +604,7 @@ int hcd_init(dwc_bus_dev_t *_dev)
- 			smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
- 		}
- 	}
-+#endif
- 
- 	hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
---- a/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
-@@ -76,8 +76,10 @@
- 
- #ifdef PLATFORM_INTERFACE
- #include <linux/platform_device.h>
-+#ifdef CONFIG_ARM
- #include <asm/mach/map.h>
- #endif
-+#endif
- 
- /** The OS page size */
- #define DWC_OS_PAGE_SIZE	PAGE_SIZE
diff --git a/target/linux/brcm2708/patches-4.14/950-0103-ARM64-Round-Robin-dispatch-IRQs-between-CPUs.patch b/target/linux/brcm2708/patches-4.14/950-0103-ARM64-Round-Robin-dispatch-IRQs-between-CPUs.patch
deleted file mode 100644
index 8e5bcab4e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0103-ARM64-Round-Robin-dispatch-IRQs-between-CPUs.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 7f270d81a7a2bda471606d6334672c88354483e5 Mon Sep 17 00:00:00 2001
-From: Michael Zoran <mzoran@crowfest.net>
-Date: Sat, 14 Jan 2017 21:43:57 -0800
-Subject: [PATCH 103/454] ARM64: Round-Robin dispatch IRQs between CPUs.
-
-IRQ-CPU mapping is round robined on ARM64 to increase
-concurrency and allow multiple interrupts to be serviced
-at a time.  This reduces the need for FIQ.
-
-Signed-off-by: Michael Zoran <mzoran@crowfest.net>
----
- drivers/irqchip/irq-bcm2835.c | 15 ++++++++++++++-
- drivers/irqchip/irq-bcm2836.c | 21 +++++++++++++++++++++
- 2 files changed, 35 insertions(+), 1 deletion(-)
-
---- a/drivers/irqchip/irq-bcm2835.c
-+++ b/drivers/irqchip/irq-bcm2835.c
-@@ -168,10 +168,23 @@ static void armctrl_unmask_irq(struct ir
- 	}
- }
- 
-+#ifdef CONFIG_ARM64
-+void bcm2836_arm_irqchip_spin_gpu_irq(void);
-+
-+static void armctrl_ack_irq(struct irq_data *d)
-+{
-+	bcm2836_arm_irqchip_spin_gpu_irq();
-+}
-+
-+#endif
-+
- static struct irq_chip armctrl_chip = {
- 	.name = "ARMCTRL-level",
- 	.irq_mask = armctrl_mask_irq,
--	.irq_unmask = armctrl_unmask_irq
-+	.irq_unmask = armctrl_unmask_irq,
-+#ifdef CONFIG_ARM64
-+	.irq_ack    = armctrl_ack_irq
-+#endif
- };
- 
- static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
---- a/drivers/irqchip/irq-bcm2836.c
-+++ b/drivers/irqchip/irq-bcm2836.c
-@@ -145,6 +145,27 @@ static void bcm2836_arm_irqchip_unmask_g
- {
- }
- 
-+#ifdef CONFIG_ARM64
-+
-+void bcm2836_arm_irqchip_spin_gpu_irq(void)
-+{
-+	u32 i;
-+	void __iomem *gpurouting = (intc.base + LOCAL_GPU_ROUTING);
-+	u32 routing_val = readl(gpurouting);
-+
-+	for (i = 1; i <= 3; i++) {
-+		u32 new_routing_val = (routing_val + i) & 3;
-+
-+		if (cpu_active(new_routing_val)) {
-+			writel(new_routing_val, gpurouting);
-+			return;
-+		}
-+	}
-+}
-+EXPORT_SYMBOL(bcm2836_arm_irqchip_spin_gpu_irq);
-+
-+#endif
-+
- static struct irq_chip bcm2836_arm_irqchip_gpu = {
- 	.name		= "bcm2836-gpu",
- 	.irq_mask	= bcm2836_arm_irqchip_mask_gpu_irq,
diff --git a/target/linux/brcm2708/patches-4.14/950-0104-ARM64-Enable-DWC_OTG-Driver-In-ARM64-Build-Config-bc.patch b/target/linux/brcm2708/patches-4.14/950-0104-ARM64-Enable-DWC_OTG-Driver-In-ARM64-Build-Config-bc.patch
deleted file mode 100644
index 1bacf6605..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0104-ARM64-Enable-DWC_OTG-Driver-In-ARM64-Build-Config-bc.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 90f1e06a8489a54f217330d14a3192a2afdfacfc Mon Sep 17 00:00:00 2001
-From: Michael Zoran <mzoran@crowfest.net>
-Date: Sat, 14 Jan 2017 21:45:03 -0800
-Subject: [PATCH 104/454] ARM64: Enable DWC_OTG Driver In ARM64 Build
- Config(bcmrpi3_defconfig)
-
-Signed-off-by: Michael Zoran <mzoran@crowfest.net>
----
- arch/arm64/configs/bcmrpi3_defconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -927,6 +927,7 @@ CONFIG_USB_HIDDEV=y
- CONFIG_USB=y
- CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
- CONFIG_USB_MON=m
-+CONFIG_USB_DWCOTG=y
- CONFIG_USB_PRINTER=m
- CONFIG_USB_STORAGE=y
- CONFIG_USB_STORAGE_REALTEK=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0105-ARM64-Force-hardware-emulation-of-deprecated-instruc.patch b/target/linux/brcm2708/patches-4.14/950-0105-ARM64-Force-hardware-emulation-of-deprecated-instruc.patch
deleted file mode 100644
index 888133a1a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0105-ARM64-Force-hardware-emulation-of-deprecated-instruc.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 7173570eda3f800b9658d181d73f0a92cde43b4b Mon Sep 17 00:00:00 2001
-From: Michael Zoran <mzoran@crowfest.net>
-Date: Sat, 11 Feb 2017 01:18:31 -0800
-Subject: [PATCH 105/454] ARM64: Force hardware emulation of deprecated
- instructions.
-
----
- arch/arm64/kernel/armv8_deprecated.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/kernel/armv8_deprecated.c
-+++ b/arch/arm64/kernel/armv8_deprecated.c
-@@ -183,10 +183,15 @@ static void __init register_insn_emulati
- 
- 	switch (ops->status) {
- 	case INSN_DEPRECATED:
-+#if 0
- 		insn->current_mode = INSN_EMULATE;
- 		/* Disable the HW mode if it was turned on at early boot time */
- 		run_all_cpu_set_hw_mode(insn, false);
-+#else
-+		insn->current_mode = INSN_HW;
-+		run_all_cpu_set_hw_mode(insn, true);
- 		insn->max = INSN_HW;
-+#endif
- 		break;
- 	case INSN_OBSOLETE:
- 		insn->current_mode = INSN_UNDEF;
diff --git a/target/linux/brcm2708/patches-4.14/950-0106-build-arm64-Add-rules-for-.dtbo-files-for-dts-overla.patch b/target/linux/brcm2708/patches-4.14/950-0106-build-arm64-Add-rules-for-.dtbo-files-for-dts-overla.patch
deleted file mode 100644
index af3393dc0..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0106-build-arm64-Add-rules-for-.dtbo-files-for-dts-overla.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From ab6c2faa1198b24b3017237df94490ecf7709100 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 10 Feb 2017 17:57:08 -0800
-Subject: [PATCH 106/454] build/arm64: Add rules for .dtbo files for dts
- overlays
-
-We now create overlays as .dtbo files.
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
----
- arch/arm64/Makefile | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/arm64/Makefile
-+++ b/arch/arm64/Makefile
-@@ -132,6 +132,9 @@ zinstall install:
- %.dtb: scripts
- 	$(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@
- 
-+%.dtbo: | scripts
-+	$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
-+
- PHONY += dtbs dtbs_install
- 
- dtbs: prepare scripts
diff --git a/target/linux/brcm2708/patches-4.14/950-0107-enable-drivers-for-GPIO-expander-and-vcio.patch b/target/linux/brcm2708/patches-4.14/950-0107-enable-drivers-for-GPIO-expander-and-vcio.patch
deleted file mode 100644
index baf4ef4e7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0107-enable-drivers-for-GPIO-expander-and-vcio.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 36662b2c2d68495acd402a15706ee9b98115d02a Mon Sep 17 00:00:00 2001
-From: Bilal Amarni <bamarni@users.noreply.github.com>
-Date: Wed, 24 May 2017 10:52:50 +0200
-Subject: [PATCH 107/454] enable drivers for GPIO expander and vcio
-
----
- arch/arm64/configs/bcmrpi3_defconfig | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -573,6 +573,8 @@ CONFIG_SERIO_RAW=m
- CONFIG_GAMEPORT=m
- CONFIG_GAMEPORT_NS558=m
- CONFIG_GAMEPORT_L4=m
-+CONFIG_BRCM_CHAR_DRIVERS=y
-+CONFIG_BCM_VCIO=y
- # CONFIG_BCM2835_DEVGPIOMEM is not set
- # CONFIG_BCM2835_SMI_DEV is not set
- # CONFIG_LEGACY_PTYS is not set
-@@ -607,6 +609,7 @@ CONFIG_PPS=m
- CONFIG_PPS_CLIENT_LDISC=m
- CONFIG_PPS_CLIENT_GPIO=m
- CONFIG_GPIO_SYSFS=y
-+CONFIG_GPIO_BCM_EXP=y
- CONFIG_GPIO_BCM_VIRT=y
- CONFIG_GPIO_ARIZONA=m
- CONFIG_GPIO_STMPE=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0108-bcm2835-aux-Add-aux-interrupt-controller.patch b/target/linux/brcm2708/patches-4.14/950-0108-bcm2835-aux-Add-aux-interrupt-controller.patch
deleted file mode 100644
index bf1c1ab74..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0108-bcm2835-aux-Add-aux-interrupt-controller.patch
+++ /dev/null
@@ -1,164 +0,0 @@
-From 61f87edd9a522d70d979f679d11849d1dc20cedb Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 23 Mar 2017 16:34:46 +0000
-Subject: [PATCH 108/454] bcm2835-aux: Add aux interrupt controller
-
-The AUX block has a shared interrupt line with a register indicating
-which devices have active IRQs. Expose this as a nested interrupt
-controller to avoid sharing problems.
-
-See: https://github.com/raspberrypi/linux/issues/1484
-     https://github.com/raspberrypi/linux/issues/1573
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/clk/bcm/clk-bcm2835-aux.c | 120 ++++++++++++++++++++++++++++++
- 1 file changed, 120 insertions(+)
-
---- a/drivers/clk/bcm/clk-bcm2835-aux.c
-+++ b/drivers/clk/bcm/clk-bcm2835-aux.c
-@@ -17,17 +17,107 @@
- #include <linux/clk/bcm2835.h>
- #include <linux/module.h>
- #include <linux/platform_device.h>
-+#include <linux/interrupt.h>
-+#include <linux/irqdomain.h>
-+#include <linux/of_irq.h>
- #include <dt-bindings/clock/bcm2835-aux.h>
- 
- #define BCM2835_AUXIRQ		0x00
- #define BCM2835_AUXENB		0x04
- 
-+#define BCM2835_AUXIRQ_NUM_IRQS  3
-+
-+#define BCM2835_AUXIRQ_UART_IRQ  0
-+#define BCM2835_AUXIRQ_SPI1_IRQ  1
-+#define BCM2835_AUXIRQ_SPI2_IRQ  2
-+
-+#define BCM2835_AUXIRQ_UART_MASK 0x01
-+#define BCM2835_AUXIRQ_SPI1_MASK 0x02
-+#define BCM2835_AUXIRQ_SPI2_MASK 0x04
-+
-+#define BCM2835_AUXIRQ_ALL_MASK \
-+	(BCM2835_AUXIRQ_UART_MASK | \
-+	 BCM2835_AUXIRQ_SPI1_MASK | \
-+	 BCM2835_AUXIRQ_SPI2_MASK)
-+
-+struct auxirq_state {
-+	void __iomem      *status;
-+	u32                enables;
-+	struct irq_domain *domain;
-+	struct regmap     *local_regmap;
-+};
-+
-+static struct auxirq_state auxirq __read_mostly;
-+
-+static irqreturn_t bcm2835_auxirq_handler(int irq, void *dev_id)
-+{
-+	u32 stat = readl_relaxed(auxirq.status);
-+	u32 masked = stat & auxirq.enables;
-+
-+	if (masked & BCM2835_AUXIRQ_UART_MASK)
-+		generic_handle_irq(irq_linear_revmap(auxirq.domain,
-+						     BCM2835_AUXIRQ_UART_IRQ));
-+
-+	if (masked & BCM2835_AUXIRQ_SPI1_MASK)
-+		generic_handle_irq(irq_linear_revmap(auxirq.domain,
-+						     BCM2835_AUXIRQ_SPI1_IRQ));
-+
-+	if (masked & BCM2835_AUXIRQ_SPI2_MASK)
-+		generic_handle_irq(irq_linear_revmap(auxirq.domain,
-+						     BCM2835_AUXIRQ_SPI2_IRQ));
-+
-+	return (masked & BCM2835_AUXIRQ_ALL_MASK) ? IRQ_HANDLED : IRQ_NONE;
-+}
-+
-+static int bcm2835_auxirq_xlate(struct irq_domain *d,
-+				 struct device_node *ctrlr,
-+				 const u32 *intspec, unsigned int intsize,
-+				 unsigned long *out_hwirq,
-+				 unsigned int *out_type)
-+{
-+	if (WARN_ON(intsize != 1))
-+		return -EINVAL;
-+
-+	if (WARN_ON(intspec[0] >= BCM2835_AUXIRQ_NUM_IRQS))
-+		return -EINVAL;
-+
-+	*out_hwirq = intspec[0];
-+	*out_type = IRQ_TYPE_NONE;
-+	return 0;
-+}
-+
-+static void bcm2835_auxirq_mask(struct irq_data *data)
-+{
-+	irq_hw_number_t hwirq = irqd_to_hwirq(data);
-+
-+	auxirq.enables &= ~(1 << hwirq);
-+}
-+
-+static void bcm2835_auxirq_unmask(struct irq_data *data)
-+{
-+	irq_hw_number_t hwirq = irqd_to_hwirq(data);
-+
-+	auxirq.enables |= (1 << hwirq);
-+}
-+
-+static struct irq_chip bcm2835_auxirq_chip = {
-+	.name = "bcm2835-auxirq",
-+	.irq_mask = bcm2835_auxirq_mask,
-+	.irq_unmask = bcm2835_auxirq_unmask,
-+};
-+
-+static const struct irq_domain_ops bcm2835_auxirq_ops = {
-+	.xlate = bcm2835_auxirq_xlate//irq_domain_xlate_onecell
-+};
-+
- static int bcm2835_aux_clk_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
-+	struct device_node *node = dev->of_node;
- 	struct clk_hw_onecell_data *onecell;
- 	const char *parent;
- 	struct clk *parent_clk;
-+	int parent_irq;
- 	struct resource *res;
- 	void __iomem *reg, *gate;
- 
-@@ -41,6 +131,36 @@ static int bcm2835_aux_clk_probe(struct
- 	if (IS_ERR(reg))
- 		return PTR_ERR(reg);
- 
-+	parent_irq = irq_of_parse_and_map(node, 0);
-+	if (parent_irq) {
-+		int ret;
-+		int i;
-+
-+		/* Manage the AUX irq as well */
-+		auxirq.status = reg + BCM2835_AUXIRQ;
-+		auxirq.domain = irq_domain_add_linear(node,
-+						      BCM2835_AUXIRQ_NUM_IRQS,
-+						      &bcm2835_auxirq_ops,
-+						      NULL);
-+		if (!auxirq.domain)
-+			return -ENXIO;
-+
-+		for (i = 0; i < BCM2835_AUXIRQ_NUM_IRQS; i++) {
-+			unsigned int irq = irq_create_mapping(auxirq.domain, i);
-+
-+			if (irq == 0)
-+				return -ENXIO;
-+
-+			irq_set_chip_and_handler(irq, &bcm2835_auxirq_chip,
-+						 handle_level_irq);
-+		}
-+
-+		ret = devm_request_irq(dev, parent_irq, bcm2835_auxirq_handler,
-+				       0, "bcm2835-auxirq", NULL);
-+		if (ret)
-+			return ret;
-+	}
-+
- 	onecell = devm_kmalloc(dev, sizeof(*onecell) + sizeof(*onecell->hws) *
- 			       BCM2835_AUX_CLOCK_COUNT, GFP_KERNEL);
- 	if (!onecell)
diff --git a/target/linux/brcm2708/patches-4.14/950-0109-raspberrypi-firmware-Export-the-general-transaction-.patch b/target/linux/brcm2708/patches-4.14/950-0109-raspberrypi-firmware-Export-the-general-transaction-.patch
deleted file mode 100644
index 418a8b836..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0109-raspberrypi-firmware-Export-the-general-transaction-.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From ddcdcbd312cc9317cf59637cc436e4d294081894 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 14 Sep 2016 09:16:19 +0100
-Subject: [PATCH 109/454] raspberrypi-firmware: Export the general transaction
- function.
-
-The vc4-firmware-kms module is going to be doing the MBOX FB call.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/firmware/raspberrypi.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/firmware/raspberrypi.c
-+++ b/drivers/firmware/raspberrypi.c
-@@ -42,7 +42,7 @@ static void response_callback(struct mbo
-  * Sends a request to the firmware through the BCM2835 mailbox driver,
-  * and synchronously waits for the reply.
-  */
--static int
-+int
- rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data)
- {
- 	u32 message = MBOX_MSG(chan, data);
-@@ -63,6 +63,7 @@ rpi_firmware_transaction(struct rpi_firm
- 
- 	return ret;
- }
-+EXPORT_SYMBOL_GPL(rpi_firmware_transaction);
- 
- /**
-  * rpi_firmware_property_list - Submit firmware property list
diff --git a/target/linux/brcm2708/patches-4.14/950-0110-drm-vc4-Add-a-mode-for-using-the-closed-firmware-for.patch b/target/linux/brcm2708/patches-4.14/950-0110-drm-vc4-Add-a-mode-for-using-the-closed-firmware-for.patch
deleted file mode 100644
index bd56e4712..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0110-drm-vc4-Add-a-mode-for-using-the-closed-firmware-for.patch
+++ /dev/null
@@ -1,762 +0,0 @@
-From 9dc72ae3f8675264d4157793dd7053b8e09f3004 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 14 Sep 2016 08:39:33 +0100
-Subject: [PATCH 110/454] drm/vc4: Add a mode for using the closed firmware for
- display.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/Makefile           |   1 +
- drivers/gpu/drm/vc4/vc4_crtc.c         |  17 +
- drivers/gpu/drm/vc4/vc4_drv.c          |   1 +
- drivers/gpu/drm/vc4/vc4_drv.h          |   7 +
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 656 +++++++++++++++++++++++++
- 5 files changed, 682 insertions(+)
- create mode 100644 drivers/gpu/drm/vc4/vc4_firmware_kms.c
-
---- a/drivers/gpu/drm/vc4/Makefile
-+++ b/drivers/gpu/drm/vc4/Makefile
-@@ -9,6 +9,7 @@ vc4-y := \
- 	vc4_dpi.o \
- 	vc4_dsi.o \
- 	vc4_fence.o \
-+	vc4_firmware_kms.o \
- 	vc4_kms.o \
- 	vc4_gem.o \
- 	vc4_hdmi.o \
---- a/drivers/gpu/drm/vc4/vc4_crtc.c
-+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
-@@ -164,6 +164,9 @@ bool vc4_crtc_get_scanoutpos(struct drm_
- 	int vblank_lines;
- 	bool ret = false;
- 
-+	if (vc4->firmware_kms)
-+		return 0;
-+
- 	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
- 
- 	/* Get optional system timestamp before query. */
-@@ -682,8 +685,15 @@ static void vc4_crtc_atomic_flush(struct
- 
- static int vc4_enable_vblank(struct drm_crtc *crtc)
- {
-+	struct drm_device *dev = crtc->dev;
-+	struct vc4_dev *vc4 = to_vc4_dev(dev);
- 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- 
-+	if (vc4->firmware_kms) {
-+		/* XXX: Can we mask the SMI interrupt? */
-+		return 0;
-+	}
-+
- 	CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
- 
- 	return 0;
-@@ -691,8 +701,15 @@ static int vc4_enable_vblank(struct drm_
- 
- static void vc4_disable_vblank(struct drm_crtc *crtc)
- {
-+	struct drm_device *dev = crtc->dev;
-+	struct vc4_dev *vc4 = to_vc4_dev(dev);
- 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- 
-+	if (vc4->firmware_kms) {
-+		/* XXX: Can we mask the SMI interrupt? */
-+		return;
-+	}
-+
- 	CRTC_WRITE(PV_INTEN, 0);
- }
- 
---- a/drivers/gpu/drm/vc4/vc4_drv.c
-+++ b/drivers/gpu/drm/vc4/vc4_drv.c
-@@ -317,6 +317,7 @@ static struct platform_driver *const com
- 	&vc4_dsi_driver,
- 	&vc4_hvs_driver,
- 	&vc4_crtc_driver,
-+	&vc4_firmware_kms_driver,
- 	&vc4_v3d_driver,
- };
- 
---- a/drivers/gpu/drm/vc4/vc4_drv.h
-+++ b/drivers/gpu/drm/vc4/vc4_drv.h
-@@ -32,6 +32,9 @@ enum vc4_kernel_bo_type {
- struct vc4_dev {
- 	struct drm_device *dev;
- 
-+	bool firmware_kms;
-+	struct rpi_firmware *firmware;
-+
- 	struct vc4_hdmi *hdmi;
- 	struct vc4_hvs *hvs;
- 	struct vc4_v3d *v3d;
-@@ -539,6 +542,10 @@ int vc4_dsi_debugfs_regs(struct seq_file
- /* vc4_fence.c */
- extern const struct dma_fence_ops vc4_fence_ops;
- 
-+/* vc4_firmware_kms.c */
-+extern struct platform_driver vc4_firmware_kms_driver;
-+void vc4_fkms_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
-+
- /* vc4_gem.c */
- void vc4_gem_init(struct drm_device *dev);
- void vc4_gem_destroy(struct drm_device *dev);
---- /dev/null
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -0,0 +1,656 @@
-+/*
-+ * Copyright (C) 2016 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+/**
-+ * DOC: VC4 firmware KMS module.
-+ *
-+ * As a hack to get us from the current closed source driver world
-+ * toward a totally open stack, implement KMS on top of the Raspberry
-+ * Pi's firmware display stack.
-+ */
-+
-+#include "drm/drm_atomic_helper.h"
-+#include "drm/drm_plane_helper.h"
-+#include "drm/drm_crtc_helper.h"
-+#include "linux/clk.h"
-+#include "linux/debugfs.h"
-+#include "drm/drm_fb_cma_helper.h"
-+#include "linux/component.h"
-+#include "linux/of_device.h"
-+#include "vc4_drv.h"
-+#include "vc4_regs.h"
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+/* The firmware delivers a vblank interrupt to us through the SMI
-+ * hardware, which has only this one register.
-+ */
-+#define SMICS 0x0
-+#define SMICS_INTERRUPTS (BIT(9) | BIT(10) | BIT(11))
-+
-+struct vc4_crtc {
-+	struct drm_crtc base;
-+	struct drm_encoder *encoder;
-+	struct drm_connector *connector;
-+	void __iomem *regs;
-+
-+	struct drm_pending_vblank_event *event;
-+};
-+
-+static inline struct vc4_crtc *to_vc4_crtc(struct drm_crtc *crtc)
-+{
-+	return container_of(crtc, struct vc4_crtc, base);
-+}
-+
-+struct vc4_fkms_encoder {
-+	struct drm_encoder base;
-+};
-+
-+static inline struct vc4_fkms_encoder *
-+to_vc4_fkms_encoder(struct drm_encoder *encoder)
-+{
-+	return container_of(encoder, struct vc4_fkms_encoder, base);
-+}
-+
-+/* VC4 FKMS connector KMS struct */
-+struct vc4_fkms_connector {
-+	struct drm_connector base;
-+
-+	/* Since the connector is attached to just the one encoder,
-+	 * this is the reference to it so we can do the best_encoder()
-+	 * hook.
-+	 */
-+	struct drm_encoder *encoder;
-+};
-+
-+static inline struct vc4_fkms_connector *
-+to_vc4_fkms_connector(struct drm_connector *connector)
-+{
-+	return container_of(connector, struct vc4_fkms_connector, base);
-+}
-+
-+/* Firmware's structure for making an FB mbox call. */
-+struct fbinfo_s {
-+	u32 xres, yres, xres_virtual, yres_virtual;
-+	u32 pitch, bpp;
-+	u32 xoffset, yoffset;
-+	u32 base;
-+	u32 screen_size;
-+	u16 cmap[256];
-+};
-+
-+struct vc4_fkms_plane {
-+	struct drm_plane base;
-+	struct fbinfo_s *fbinfo;
-+	dma_addr_t fbinfo_bus_addr;
-+	u32 pitch;
-+};
-+
-+static inline struct vc4_fkms_plane *to_vc4_fkms_plane(struct drm_plane *plane)
-+{
-+	return (struct vc4_fkms_plane *)plane;
-+}
-+
-+/* Turns the display on/off. */
-+static int vc4_plane_set_primary_blank(struct drm_plane *plane, bool blank)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
-+
-+	u32 packet = blank;
-+	return rpi_firmware_property(vc4->firmware,
-+				     RPI_FIRMWARE_FRAMEBUFFER_BLANK,
-+				     &packet, sizeof(packet));
-+}
-+
-+static void vc4_primary_plane_atomic_update(struct drm_plane *plane,
-+					    struct drm_plane_state *old_state)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
-+	struct vc4_fkms_plane *vc4_plane = to_vc4_fkms_plane(plane);
-+	struct drm_plane_state *state = plane->state;
-+	struct drm_framebuffer *fb = state->fb;
-+	struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
-+	volatile struct fbinfo_s *fbinfo = vc4_plane->fbinfo;
-+	u32 bpp = 32;
-+	int ret;
-+
-+	vc4_plane_set_primary_blank(plane, false);
-+
-+	fbinfo->xres = state->crtc_w;
-+	fbinfo->yres = state->crtc_h;
-+	fbinfo->xres_virtual = state->crtc_w;
-+	fbinfo->yres_virtual = state->crtc_h;
-+	fbinfo->bpp = bpp;
-+	fbinfo->xoffset = state->crtc_x;
-+	fbinfo->yoffset = state->crtc_y;
-+	fbinfo->base = bo->paddr + fb->offsets[0];
-+	fbinfo->pitch = fb->pitches[0];
-+	/* A bug in the firmware makes it so that if the fb->base is
-+	 * set to nonzero, the configured pitch gets overwritten with
-+	 * the previous pitch.  So, to get the configured pitch
-+	 * recomputed, we have to make it allocate itself a new buffer
-+	 * in VC memory, first.
-+	 */
-+	if (vc4_plane->pitch != fb->pitches[0]) {
-+		u32 saved_base = fbinfo->base;
-+		fbinfo->base = 0;
-+
-+		ret = rpi_firmware_transaction(vc4->firmware,
-+					       RPI_FIRMWARE_CHAN_FB,
-+					       vc4_plane->fbinfo_bus_addr);
-+		fbinfo->base = saved_base;
-+
-+		vc4_plane->pitch = fbinfo->pitch;
-+		WARN_ON_ONCE(vc4_plane->pitch != fb->pitches[0]);
-+	}
-+
-+	ret = rpi_firmware_transaction(vc4->firmware,
-+				       RPI_FIRMWARE_CHAN_FB,
-+				       vc4_plane->fbinfo_bus_addr);
-+	WARN_ON_ONCE(fbinfo->pitch != fb->pitches[0]);
-+	WARN_ON_ONCE(fbinfo->base != bo->paddr + fb->offsets[0]);
-+}
-+
-+static void vc4_primary_plane_atomic_disable(struct drm_plane *plane,
-+					     struct drm_plane_state *old_state)
-+{
-+	vc4_plane_set_primary_blank(plane, true);
-+}
-+
-+static void vc4_cursor_plane_atomic_update(struct drm_plane *plane,
-+					   struct drm_plane_state *old_state)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
-+	struct drm_plane_state *state = plane->state;
-+	struct drm_framebuffer *fb = state->fb;
-+	struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
-+	int ret;
-+	u32 packet_state[] = { true, state->crtc_x, state->crtc_y, 0 };
-+	u32 packet_info[] = { state->crtc_w, state->crtc_h,
-+			      0, /* unused */
-+			      bo->paddr + fb->offsets[0],
-+			      0, 0, /* hotx, hoty */};
-+	WARN_ON_ONCE(fb->pitches[0] != state->crtc_w * 4);
-+
-+	ret = rpi_firmware_property(vc4->firmware,
-+				    RPI_FIRMWARE_SET_CURSOR_STATE,
-+				    &packet_state,
-+				    sizeof(packet_state));
-+	if (ret || packet_state[0] != 0)
-+		DRM_ERROR("Failed to set cursor state: 0x%08x\n", packet_state[0]);
-+
-+	ret = rpi_firmware_property(vc4->firmware,
-+				    RPI_FIRMWARE_SET_CURSOR_INFO,
-+				    &packet_info,
-+				    sizeof(packet_info));
-+	if (ret || packet_info[0] != 0)
-+		DRM_ERROR("Failed to set cursor info: 0x%08x\n", packet_info[0]);
-+}
-+
-+static void vc4_cursor_plane_atomic_disable(struct drm_plane *plane,
-+					    struct drm_plane_state *old_state)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
-+	u32 packet_state[] = { false, 0, 0, 0 };
-+	int ret;
-+
-+	ret = rpi_firmware_property(vc4->firmware,
-+				    RPI_FIRMWARE_SET_CURSOR_STATE,
-+				    &packet_state,
-+				    sizeof(packet_state));
-+	if (ret || packet_state[0] != 0)
-+		DRM_ERROR("Failed to set cursor state: 0x%08x\n", packet_state[0]);
-+}
-+
-+static int vc4_plane_atomic_check(struct drm_plane *plane,
-+				  struct drm_plane_state *state)
-+{
-+	return 0;
-+}
-+
-+static void vc4_plane_destroy(struct drm_plane *plane)
-+{
-+	drm_plane_helper_disable(plane);
-+	drm_plane_cleanup(plane);
-+}
-+
-+static const struct drm_plane_funcs vc4_plane_funcs = {
-+	.update_plane = drm_atomic_helper_update_plane,
-+	.disable_plane = drm_atomic_helper_disable_plane,
-+	.destroy = vc4_plane_destroy,
-+	.set_property = NULL,
-+	.reset = drm_atomic_helper_plane_reset,
-+	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
-+	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
-+};
-+
-+static const struct drm_plane_helper_funcs vc4_primary_plane_helper_funcs = {
-+	.prepare_fb = NULL,
-+	.cleanup_fb = NULL,
-+	.atomic_check = vc4_plane_atomic_check,
-+	.atomic_update = vc4_primary_plane_atomic_update,
-+	.atomic_disable = vc4_primary_plane_atomic_disable,
-+};
-+
-+static const struct drm_plane_helper_funcs vc4_cursor_plane_helper_funcs = {
-+	.prepare_fb = NULL,
-+	.cleanup_fb = NULL,
-+	.atomic_check = vc4_plane_atomic_check,
-+	.atomic_update = vc4_cursor_plane_atomic_update,
-+	.atomic_disable = vc4_cursor_plane_atomic_disable,
-+};
-+
-+static struct drm_plane *vc4_fkms_plane_init(struct drm_device *dev,
-+					     enum drm_plane_type type)
-+{
-+	struct drm_plane *plane = NULL;
-+	struct vc4_fkms_plane *vc4_plane;
-+	u32 xrgb8888 = DRM_FORMAT_XRGB8888;
-+	u32 argb8888 = DRM_FORMAT_ARGB8888;
-+	int ret = 0;
-+	bool primary = (type == DRM_PLANE_TYPE_PRIMARY);
-+
-+	vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
-+				 GFP_KERNEL);
-+	if (!vc4_plane) {
-+		ret = -ENOMEM;
-+		goto fail;
-+	}
-+
-+	plane = &vc4_plane->base;
-+	ret = drm_universal_plane_init(dev, plane, 0xff,
-+				       &vc4_plane_funcs,
-+				       primary ? &xrgb8888 : &argb8888, 1, NULL,
-+				       type, NULL);
-+
-+	if (type == DRM_PLANE_TYPE_PRIMARY) {
-+		vc4_plane->fbinfo =
-+			dma_alloc_coherent(dev->dev,
-+					   sizeof(*vc4_plane->fbinfo),
-+					   &vc4_plane->fbinfo_bus_addr,
-+					   GFP_KERNEL);
-+		memset(vc4_plane->fbinfo, 0, sizeof(*vc4_plane->fbinfo));
-+
-+		drm_plane_helper_add(plane, &vc4_primary_plane_helper_funcs);
-+	} else {
-+		drm_plane_helper_add(plane, &vc4_cursor_plane_helper_funcs);
-+	}
-+
-+	return plane;
-+fail:
-+	if (plane)
-+		vc4_plane_destroy(plane);
-+
-+	return ERR_PTR(ret);
-+}
-+
-+static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
-+{
-+	/* Everyting is handled in the planes. */
-+}
-+
-+static void vc4_crtc_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
-+{
-+}
-+
-+static void vc4_crtc_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
-+{
-+}
-+
-+static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
-+				 struct drm_crtc_state *state)
-+{
-+	return 0;
-+}
-+
-+static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
-+				  struct drm_crtc_state *old_state)
-+{
-+}
-+
-+static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
-+{
-+	struct drm_crtc *crtc = &vc4_crtc->base;
-+	struct drm_device *dev = crtc->dev;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&dev->event_lock, flags);
-+	if (vc4_crtc->event) {
-+		drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
-+		vc4_crtc->event = NULL;
-+		drm_crtc_vblank_put(crtc);
-+	}
-+	spin_unlock_irqrestore(&dev->event_lock, flags);
-+}
-+
-+static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
-+{
-+	struct vc4_crtc *vc4_crtc = data;
-+	u32 stat = readl(vc4_crtc->regs + SMICS);
-+	irqreturn_t ret = IRQ_NONE;
-+
-+	if (stat & SMICS_INTERRUPTS) {
-+		writel(0, vc4_crtc->regs + SMICS);
-+		drm_crtc_handle_vblank(&vc4_crtc->base);
-+		vc4_crtc_handle_page_flip(vc4_crtc);
-+		ret = IRQ_HANDLED;
-+	}
-+
-+	return ret;
-+}
-+
-+static int vc4_page_flip(struct drm_crtc *crtc,
-+			 struct drm_framebuffer *fb,
-+			 struct drm_pending_vblank_event *event,
-+			 uint32_t flags, struct drm_modeset_acquire_ctx *ctx)
-+{
-+	if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
-+		DRM_ERROR("Async flips aren't allowed\n");
-+		return -EINVAL;
-+	}
-+
-+	return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
-+}
-+
-+static const struct drm_crtc_funcs vc4_crtc_funcs = {
-+	.set_config = drm_atomic_helper_set_config,
-+	.destroy = drm_crtc_cleanup,
-+	.page_flip = vc4_page_flip,
-+	.set_property = NULL,
-+	.cursor_set = NULL, /* handled by drm_mode_cursor_universal */
-+	.cursor_move = NULL, /* handled by drm_mode_cursor_universal */
-+	.reset = drm_atomic_helper_crtc_reset,
-+	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
-+	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
-+};
-+
-+static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
-+	.mode_set_nofb = vc4_crtc_mode_set_nofb,
-+	.atomic_disable = vc4_crtc_disable,
-+	.atomic_enable = vc4_crtc_enable,
-+	.atomic_check = vc4_crtc_atomic_check,
-+	.atomic_flush = vc4_crtc_atomic_flush,
-+};
-+
-+/* Frees the page flip event when the DRM device is closed with the
-+ * event still outstanding.
-+ */
-+void vc4_fkms_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
-+{
-+	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-+	struct drm_device *dev = crtc->dev;
-+	unsigned long flags;
-+
-+	spin_lock_irqsave(&dev->event_lock, flags);
-+
-+	if (vc4_crtc->event && vc4_crtc->event->base.file_priv == file) {
-+		kfree(&vc4_crtc->event->base);
-+		drm_crtc_vblank_put(crtc);
-+		vc4_crtc->event = NULL;
-+	}
-+
-+	spin_unlock_irqrestore(&dev->event_lock, flags);
-+}
-+
-+static const struct of_device_id vc4_firmware_kms_dt_match[] = {
-+	{ .compatible = "raspberrypi,rpi-firmware-kms" },
-+	{}
-+};
-+
-+static enum drm_connector_status
-+vc4_fkms_connector_detect(struct drm_connector *connector, bool force)
-+{
-+	return connector_status_connected;
-+}
-+
-+static int vc4_fkms_connector_get_modes(struct drm_connector *connector)
-+{
-+	struct drm_device *dev = connector->dev;
-+	struct vc4_dev *vc4 = to_vc4_dev(dev);
-+	u32 wh[2] = {0, 0};
-+	int ret;
-+	struct drm_display_mode *mode;
-+
-+	ret = rpi_firmware_property(vc4->firmware,
-+				    RPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT,
-+				    &wh, sizeof(wh));
-+	if (ret) {
-+		DRM_ERROR("Failed to get screen size: %d (0x%08x 0x%08x)\n",
-+			  ret, wh[0], wh[1]);
-+		return 0;
-+	}
-+
-+	mode = drm_cvt_mode(dev, wh[0], wh[1], 60 /* vrefresh */,
-+			    0, 0, false);
-+	drm_mode_probed_add(connector, mode);
-+
-+	return 1;
-+}
-+
-+static struct drm_encoder *
-+vc4_fkms_connector_best_encoder(struct drm_connector *connector)
-+{
-+	struct vc4_fkms_connector *fkms_connector =
-+		to_vc4_fkms_connector(connector);
-+	return fkms_connector->encoder;
-+}
-+
-+static void vc4_fkms_connector_destroy(struct drm_connector *connector)
-+{
-+	drm_connector_unregister(connector);
-+	drm_connector_cleanup(connector);
-+}
-+
-+static const struct drm_connector_funcs vc4_fkms_connector_funcs = {
-+	.detect = vc4_fkms_connector_detect,
-+	.fill_modes = drm_helper_probe_single_connector_modes,
-+	.destroy = vc4_fkms_connector_destroy,
-+	.reset = drm_atomic_helper_connector_reset,
-+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-+};
-+
-+static const struct drm_connector_helper_funcs vc4_fkms_connector_helper_funcs = {
-+	.get_modes = vc4_fkms_connector_get_modes,
-+	.best_encoder = vc4_fkms_connector_best_encoder,
-+};
-+
-+static struct drm_connector *vc4_fkms_connector_init(struct drm_device *dev,
-+						     struct drm_encoder *encoder)
-+{
-+	struct drm_connector *connector = NULL;
-+	struct vc4_fkms_connector *fkms_connector;
-+	int ret = 0;
-+
-+	fkms_connector = devm_kzalloc(dev->dev, sizeof(*fkms_connector),
-+				      GFP_KERNEL);
-+	if (!fkms_connector) {
-+		ret = -ENOMEM;
-+		goto fail;
-+	}
-+	connector = &fkms_connector->base;
-+
-+	fkms_connector->encoder = encoder;
-+
-+	drm_connector_init(dev, connector, &vc4_fkms_connector_funcs,
-+			   DRM_MODE_CONNECTOR_HDMIA);
-+	drm_connector_helper_add(connector, &vc4_fkms_connector_helper_funcs);
-+
-+	connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
-+			     DRM_CONNECTOR_POLL_DISCONNECT);
-+
-+	connector->interlace_allowed = 0;
-+	connector->doublescan_allowed = 0;
-+
-+	drm_mode_connector_attach_encoder(connector, encoder);
-+
-+	return connector;
-+
-+ fail:
-+	if (connector)
-+		vc4_fkms_connector_destroy(connector);
-+
-+	return ERR_PTR(ret);
-+}
-+
-+static void vc4_fkms_encoder_destroy(struct drm_encoder *encoder)
-+{
-+	drm_encoder_cleanup(encoder);
-+}
-+
-+static const struct drm_encoder_funcs vc4_fkms_encoder_funcs = {
-+	.destroy = vc4_fkms_encoder_destroy,
-+};
-+
-+static void vc4_fkms_encoder_enable(struct drm_encoder *encoder)
-+{
-+}
-+
-+static void vc4_fkms_encoder_disable(struct drm_encoder *encoder)
-+{
-+}
-+
-+static const struct drm_encoder_helper_funcs vc4_fkms_encoder_helper_funcs = {
-+	.enable = vc4_fkms_encoder_enable,
-+	.disable = vc4_fkms_encoder_disable,
-+};
-+
-+static int vc4_fkms_bind(struct device *dev, struct device *master, void *data)
-+{
-+	struct platform_device *pdev = to_platform_device(dev);
-+	struct drm_device *drm = dev_get_drvdata(master);
-+	struct vc4_dev *vc4 = to_vc4_dev(drm);
-+	struct vc4_crtc *vc4_crtc;
-+	struct vc4_fkms_encoder *vc4_encoder;
-+	struct drm_crtc *crtc;
-+	struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
-+	struct device_node *firmware_node;
-+	int ret;
-+
-+	vc4->firmware_kms = true;
-+
-+	vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
-+	if (!vc4_crtc)
-+		return -ENOMEM;
-+	crtc = &vc4_crtc->base;
-+
-+	firmware_node = of_parse_phandle(dev->of_node, "brcm,firmware", 0);
-+	vc4->firmware = rpi_firmware_get(firmware_node);
-+	if (!vc4->firmware) {
-+		DRM_DEBUG("Failed to get Raspberry Pi firmware reference.\n");
-+		return -EPROBE_DEFER;
-+	}
-+	of_node_put(firmware_node);
-+
-+	/* Map the SMI interrupt reg */
-+	vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
-+	if (IS_ERR(vc4_crtc->regs))
-+		return PTR_ERR(vc4_crtc->regs);
-+
-+	/* For now, we create just the primary and the legacy cursor
-+	 * planes.  We should be able to stack more planes on easily,
-+	 * but to do that we would need to compute the bandwidth
-+	 * requirement of the plane configuration, and reject ones
-+	 * that will take too much.
-+	 */
-+	primary_plane = vc4_fkms_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
-+	if (IS_ERR(primary_plane)) {
-+		dev_err(dev, "failed to construct primary plane\n");
-+		ret = PTR_ERR(primary_plane);
-+		goto err;
-+	}
-+
-+	cursor_plane = vc4_fkms_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
-+	if (IS_ERR(cursor_plane)) {
-+		dev_err(dev, "failed to construct cursor plane\n");
-+		ret = PTR_ERR(cursor_plane);
-+		goto err;
-+	}
-+
-+	drm_crtc_init_with_planes(drm, crtc, primary_plane, cursor_plane,
-+				  &vc4_crtc_funcs, NULL);
-+	drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
-+	primary_plane->crtc = crtc;
-+	cursor_plane->crtc = crtc;
-+
-+	vc4_encoder = devm_kzalloc(dev, sizeof(*vc4_encoder), GFP_KERNEL);
-+	if (!vc4_encoder)
-+		return -ENOMEM;
-+	vc4_crtc->encoder = &vc4_encoder->base;
-+	vc4_encoder->base.possible_crtcs |= drm_crtc_mask(crtc) ;
-+	drm_encoder_init(drm, &vc4_encoder->base, &vc4_fkms_encoder_funcs,
-+			 DRM_MODE_ENCODER_TMDS, NULL);
-+	drm_encoder_helper_add(&vc4_encoder->base,
-+			       &vc4_fkms_encoder_helper_funcs);
-+
-+	vc4_crtc->connector = vc4_fkms_connector_init(drm, &vc4_encoder->base);
-+	if (IS_ERR(vc4_crtc->connector)) {
-+		ret = PTR_ERR(vc4_crtc->connector);
-+		goto err_destroy_encoder;
-+	}
-+
-+	writel(0, vc4_crtc->regs + SMICS);
-+	ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
-+			       vc4_crtc_irq_handler, 0, "vc4 firmware kms",
-+			       vc4_crtc);
-+	if (ret)
-+		goto err_destroy_connector;
-+
-+	platform_set_drvdata(pdev, vc4_crtc);
-+
-+	return 0;
-+
-+err_destroy_connector:
-+	vc4_fkms_connector_destroy(vc4_crtc->connector);
-+err_destroy_encoder:
-+	vc4_fkms_encoder_destroy(vc4_crtc->encoder);
-+	list_for_each_entry_safe(destroy_plane, temp,
-+				 &drm->mode_config.plane_list, head) {
-+		if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
-+		    destroy_plane->funcs->destroy(destroy_plane);
-+	}
-+err:
-+	return ret;
-+}
-+
-+static void vc4_fkms_unbind(struct device *dev, struct device *master,
-+			    void *data)
-+{
-+	struct platform_device *pdev = to_platform_device(dev);
-+	struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
-+
-+	vc4_fkms_connector_destroy(vc4_crtc->connector);
-+	vc4_fkms_encoder_destroy(vc4_crtc->encoder);
-+	drm_crtc_cleanup(&vc4_crtc->base);
-+
-+	platform_set_drvdata(pdev, NULL);
-+}
-+
-+static const struct component_ops vc4_fkms_ops = {
-+	.bind   = vc4_fkms_bind,
-+	.unbind = vc4_fkms_unbind,
-+};
-+
-+static int vc4_fkms_probe(struct platform_device *pdev)
-+{
-+	return component_add(&pdev->dev, &vc4_fkms_ops);
-+}
-+
-+static int vc4_fkms_remove(struct platform_device *pdev)
-+{
-+	component_del(&pdev->dev, &vc4_fkms_ops);
-+	return 0;
-+}
-+
-+struct platform_driver vc4_firmware_kms_driver = {
-+	.probe = vc4_fkms_probe,
-+	.remove = vc4_fkms_remove,
-+	.driver = {
-+		.name = "vc4_firmware_kms",
-+		.of_match_table = vc4_firmware_kms_dt_match,
-+	},
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0111-drm-vc4-Name-the-primary-and-cursor-planes-in-fkms.patch b/target/linux/brcm2708/patches-4.14/950-0111-drm-vc4-Name-the-primary-and-cursor-planes-in-fkms.patch
deleted file mode 100644
index b319db475..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0111-drm-vc4-Name-the-primary-and-cursor-planes-in-fkms.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From 3120ff1a8411f838e3c423f7913298141fb0ecd1 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 1 Feb 2017 17:09:18 -0800
-Subject: [PATCH 111/454] drm/vc4: Name the primary and cursor planes in fkms.
-
-This makes debugging nicer, compared to trying to remember what the
-IDs are.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -265,7 +265,7 @@ static struct drm_plane *vc4_fkms_plane_
- 	ret = drm_universal_plane_init(dev, plane, 0xff,
- 				       &vc4_plane_funcs,
- 				       primary ? &xrgb8888 : &argb8888, 1, NULL,
--				       type, NULL);
-+				       type, primary ? "primary" : "cursor");
- 
- 	if (type == DRM_PLANE_TYPE_PRIMARY) {
- 		vc4_plane->fbinfo =
diff --git a/target/linux/brcm2708/patches-4.14/950-0112-drm-vc4-Add-DRM_DEBUG_ATOMIC-for-the-insides-of-fkms.patch b/target/linux/brcm2708/patches-4.14/950-0112-drm-vc4-Add-DRM_DEBUG_ATOMIC-for-the-insides-of-fkms.patch
deleted file mode 100644
index 27634695e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0112-drm-vc4-Add-DRM_DEBUG_ATOMIC-for-the-insides-of-fkms.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 25b6fdbc06c38645e92db8db59c1ebfc5c0b7d59 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 1 Feb 2017 17:10:09 -0800
-Subject: [PATCH 112/454] drm/vc4: Add DRM_DEBUG_ATOMIC for the insides of
- fkms.
-
-Trying to debug weston on fkms involved figuring out what calls I was
-making to the firmware.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -101,6 +101,11 @@ static int vc4_plane_set_primary_blank(s
- 	struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
- 
- 	u32 packet = blank;
-+
-+	DRM_DEBUG_ATOMIC("[PLANE:%d:%s] primary plane %s",
-+			 plane->base.id, plane->name,
-+			 blank ? "blank" : "unblank");
-+
- 	return rpi_firmware_property(vc4->firmware,
- 				     RPI_FIRMWARE_FRAMEBUFFER_BLANK,
- 				     &packet, sizeof(packet));
-@@ -148,6 +153,16 @@ static void vc4_primary_plane_atomic_upd
- 		WARN_ON_ONCE(vc4_plane->pitch != fb->pitches[0]);
- 	}
- 
-+	DRM_DEBUG_ATOMIC("[PLANE:%d:%s] primary update %dx%d@%d +%d,%d 0x%08x/%d\n",
-+			 plane->base.id, plane->name,
-+			 state->crtc_w,
-+			 state->crtc_h,
-+			 bpp,
-+			 state->crtc_x,
-+			 state->crtc_y,
-+			 bo->paddr + fb->offsets[0],
-+			 fb->pitches[0]);
-+
- 	ret = rpi_firmware_transaction(vc4->firmware,
- 				       RPI_FIRMWARE_CHAN_FB,
- 				       vc4_plane->fbinfo_bus_addr);
-@@ -176,6 +191,15 @@ static void vc4_cursor_plane_atomic_upda
- 			      0, 0, /* hotx, hoty */};
- 	WARN_ON_ONCE(fb->pitches[0] != state->crtc_w * 4);
- 
-+	DRM_DEBUG_ATOMIC("[PLANE:%d:%s] update %dx%d cursor at %d,%d (0x%08x/%d)",
-+			 plane->base.id, plane->name,
-+			 state->crtc_w,
-+			 state->crtc_h,
-+			 state->crtc_x,
-+			 state->crtc_y,
-+			 bo->paddr + fb->offsets[0],
-+			 fb->pitches[0]);
-+
- 	ret = rpi_firmware_property(vc4->firmware,
- 				    RPI_FIRMWARE_SET_CURSOR_STATE,
- 				    &packet_state,
-@@ -198,6 +222,8 @@ static void vc4_cursor_plane_atomic_disa
- 	u32 packet_state[] = { false, 0, 0, 0 };
- 	int ret;
- 
-+	DRM_DEBUG_ATOMIC("[PLANE:%d:%s] disabling cursor", plane->base.id, plane->name);
-+
- 	ret = rpi_firmware_property(vc4->firmware,
- 				    RPI_FIRMWARE_SET_CURSOR_STATE,
- 				    &packet_state,
diff --git a/target/linux/brcm2708/patches-4.14/950-0113-drm-vc4-Fix-sending-of-page-flip-completion-events-i.patch b/target/linux/brcm2708/patches-4.14/950-0113-drm-vc4-Fix-sending-of-page-flip-completion-events-i.patch
deleted file mode 100644
index 46c1b9395..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0113-drm-vc4-Fix-sending-of-page-flip-completion-events-i.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 06834226909bcb5bce5b5d0f7612258f8fe35201 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Thu, 2 Feb 2017 09:42:18 -0800
-Subject: [PATCH 113/454] drm/vc4: Fix sending of page flip completion events
- in FKMS mode.
-
-In the rewrite of vc4_crtc.c for fkms, I dropped the part of the
-CRTC's atomic flush handler that moved the completion event from the
-proposed atomic state change to the CRTC's current state.  That meant
-that when full screen pageflipping happened (glxgears -fullscreen in
-X, compton, por weston), the app would end up blocked firever waiting
-to draw its next frame.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -336,6 +336,21 @@ static int vc4_crtc_atomic_check(struct
- static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
- 				  struct drm_crtc_state *old_state)
- {
-+	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-+	struct drm_device *dev = crtc->dev;
-+
-+	if (crtc->state->event) {
-+		unsigned long flags;
-+
-+		crtc->state->event->pipe = drm_crtc_index(crtc);
-+
-+		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
-+
-+		spin_lock_irqsave(&dev->event_lock, flags);
-+		vc4_crtc->event = crtc->state->event;
-+		crtc->state->event = NULL;
-+		spin_unlock_irqrestore(&dev->event_lock, flags);
-+	}
- }
- 
- static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
diff --git a/target/linux/brcm2708/patches-4.14/950-0114-vc4_fkms-Apply-firmware-overscan-offset-to-hardware-.patch b/target/linux/brcm2708/patches-4.14/950-0114-vc4_fkms-Apply-firmware-overscan-offset-to-hardware-.patch
deleted file mode 100644
index 66f6dc835..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0114-vc4_fkms-Apply-firmware-overscan-offset-to-hardware-.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From e7ecdf293b07f35f23684badcab6afa58928257a Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Tue, 18 Apr 2017 21:43:46 +0100
-Subject: [PATCH 114/454] vc4_fkms: Apply firmware overscan offset to hardware
- cursor
-
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -39,6 +39,7 @@ struct vc4_crtc {
- 	void __iomem *regs;
- 
- 	struct drm_pending_vblank_event *event;
-+	u32 overscan[4];
- };
- 
- static inline struct vc4_crtc *to_vc4_crtc(struct drm_crtc *crtc)
-@@ -180,6 +181,7 @@ static void vc4_cursor_plane_atomic_upda
- 					   struct drm_plane_state *old_state)
- {
- 	struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
-+	struct vc4_crtc *vc4_crtc = to_vc4_crtc(plane->crtc);
- 	struct drm_plane_state *state = plane->state;
- 	struct drm_framebuffer *fb = state->fb;
- 	struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
-@@ -200,6 +202,12 @@ static void vc4_cursor_plane_atomic_upda
- 			 bo->paddr + fb->offsets[0],
- 			 fb->pitches[0]);
- 
-+	/* add on the top/left offsets when overscan is active */
-+	if (vc4_crtc) {
-+		packet_state[1] += vc4_crtc->overscan[0];
-+		packet_state[2] += vc4_crtc->overscan[1];
-+	}
-+
- 	ret = rpi_firmware_property(vc4->firmware,
- 				    RPI_FIRMWARE_SET_CURSOR_STATE,
- 				    &packet_state,
-@@ -641,6 +649,15 @@ static int vc4_fkms_bind(struct device *
- 	if (ret)
- 		goto err_destroy_connector;
- 
-+	ret = rpi_firmware_property(vc4->firmware,
-+				    RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN,
-+				    &vc4_crtc->overscan,
-+				    sizeof(vc4_crtc->overscan));
-+	if (ret) {
-+		DRM_ERROR("Failed to get overscan state: 0x%08x\n", vc4_crtc->overscan[0]);
-+		memset(&vc4_crtc->overscan, 0, sizeof(vc4_crtc->overscan));
-+	}
-+
- 	platform_set_drvdata(pdev, vc4_crtc);
- 
- 	return 0;
diff --git a/target/linux/brcm2708/patches-4.14/950-0115-ASoC-bcm2835-Add-support-for-TDM-modes.patch b/target/linux/brcm2708/patches-4.14/950-0115-ASoC-bcm2835-Add-support-for-TDM-modes.patch
deleted file mode 100644
index ce3800cb2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0115-ASoC-bcm2835-Add-support-for-TDM-modes.patch
+++ /dev/null
@@ -1,402 +0,0 @@
-From c2b82810c0272bb29a9b426b017b196436957c76 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Sun, 7 May 2017 11:34:26 +0200
-Subject: [PATCH 115/454] ASoC: bcm2835: Add support for TDM modes
-
-bcm2835 supports arbitrary positioning of channel data within
-a frame and thus is capable of supporting TDM modes. Since
-the driver is limited to 2-channel operations only TDM setups
-with exactly 2 active slots are supported.
-
-Logical TDM slot numbering follows the usual convention:
-
-For I2S-like modes, with a 50% duty-cycle frame clock,
-slots 0, 2, ... are transmitted in the first half of a frame,
-slots 1, 3, ... are transmitted in the second half.
-
-For DSP modes slot numbering is ascending: 0, 1, 2, 3, ...
-
-Channel position calculation has been refactored to use
-TDM info and moved out of hw_params.
-
-set_tdm_slot, set_bclk_ratio and hw_params now check more
-strictly if the configuration is valid. Illegal configurations
-like odd number of slots in I2S mode, data lengths exceeding
-slot width or frame sizes larger than the hardware limit of
-1024 are rejected. Also hw_params now properly checks for
-errors from clk_set_rate.
-
-Allowed PCM formats are already guarded by stream constraints,
-thus the formats check in hw_params has been removed and
-data_length is now retrieved via params_width().
-
-Also standard functions like snd_soc_params_to_bclk are now
-being used instead of manual calculations to make the code
-more readable.
-
-Special care has been taken to ensure that set_bclk_ratio works
-as before. The bclk ratio is mapped to a 2-channel TDM config
-with a slot width of half the ratio. In order to support odd ratios,
-which can't be expressed via a TDM config, the ratio (frame length)
-is stored and used by hw_params.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/bcm2835-i2s.c | 243 ++++++++++++++++++++++++++++--------
- 1 file changed, 190 insertions(+), 53 deletions(-)
-
---- a/sound/soc/bcm/bcm2835-i2s.c
-+++ b/sound/soc/bcm/bcm2835-i2s.c
-@@ -31,6 +31,7 @@
-  * General Public License for more details.
-  */
- 
-+#include <linux/bitops.h>
- #include <linux/clk.h>
- #include <linux/delay.h>
- #include <linux/device.h>
-@@ -99,6 +100,8 @@
- #define BCM2835_I2S_CHWID(v)		(v)
- #define BCM2835_I2S_CH1(v)		((v) << 16)
- #define BCM2835_I2S_CH2(v)		(v)
-+#define BCM2835_I2S_CH1_POS(v)		BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(v))
-+#define BCM2835_I2S_CH2_POS(v)		BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(v))
- 
- #define BCM2835_I2S_TX_PANIC(v)	((v) << 24)
- #define BCM2835_I2S_RX_PANIC(v)	((v) << 16)
-@@ -110,12 +113,19 @@
- #define BCM2835_I2S_INT_RXR		BIT(1)
- #define BCM2835_I2S_INT_TXW		BIT(0)
- 
-+/* Frame length register is 10 bit, maximum length 1024 */
-+#define BCM2835_I2S_MAX_FRAME_LENGTH	1024
-+
- /* General device struct */
- struct bcm2835_i2s_dev {
- 	struct device				*dev;
- 	struct snd_dmaengine_dai_dma_data	dma_data[2];
- 	unsigned int				fmt;
--	unsigned int				bclk_ratio;
-+	unsigned int				tdm_slots;
-+	unsigned int				rx_mask;
-+	unsigned int				tx_mask;
-+	unsigned int				slot_width;
-+	unsigned int				frame_length;
- 
- 	struct regmap				*i2s_regmap;
- 	struct clk				*clk;
-@@ -225,19 +235,117 @@ static int bcm2835_i2s_set_dai_bclk_rati
- 				      unsigned int ratio)
- {
- 	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
--	dev->bclk_ratio = ratio;
-+
-+	if (!ratio) {
-+		dev->tdm_slots = 0;
-+		return 0;
-+	}
-+
-+	if (ratio > BCM2835_I2S_MAX_FRAME_LENGTH)
-+		return -EINVAL;
-+
-+	dev->tdm_slots = 2;
-+	dev->rx_mask = 0x03;
-+	dev->tx_mask = 0x03;
-+	dev->slot_width = ratio / 2;
-+	dev->frame_length = ratio;
-+
- 	return 0;
- }
- 
-+static int bcm2835_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai,
-+	unsigned int tx_mask, unsigned int rx_mask,
-+	int slots, int width)
-+{
-+	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
-+
-+	if (slots) {
-+		if (slots < 0 || width < 0)
-+			return -EINVAL;
-+
-+		/* Limit masks to available slots */
-+		rx_mask &= GENMASK(slots - 1, 0);
-+		tx_mask &= GENMASK(slots - 1, 0);
-+
-+		/*
-+		 * The driver is limited to 2-channel setups.
-+		 * Check that exactly 2 bits are set in the masks.
-+		 */
-+		if (hweight_long((unsigned long) rx_mask) != 2
-+		    || hweight_long((unsigned long) tx_mask) != 2)
-+			return -EINVAL;
-+
-+		if (slots * width > BCM2835_I2S_MAX_FRAME_LENGTH)
-+			return -EINVAL;
-+	}
-+
-+	dev->tdm_slots = slots;
-+
-+	dev->rx_mask = rx_mask;
-+	dev->tx_mask = tx_mask;
-+	dev->slot_width = width;
-+	dev->frame_length = slots * width;
-+
-+	return 0;
-+}
-+
-+/*
-+ * Convert logical slot number into physical slot number.
-+ *
-+ * If odd_offset is 0 sequential number is identical to logical number.
-+ * This is used for DSP modes with slot numbering 0 1 2 3 ...
-+ *
-+ * Otherwise odd_offset defines the physical offset for odd numbered
-+ * slots. This is used for I2S and left/right justified modes to
-+ * translate from logical slot numbers 0 1 2 3 ... into physical slot
-+ * numbers 0 2 ... 3 4 ...
-+ */
-+static int bcm2835_i2s_convert_slot(unsigned int slot, unsigned int odd_offset)
-+{
-+	if (!odd_offset)
-+		return slot;
-+
-+	if (slot & 1)
-+		return (slot >> 1) + odd_offset;
-+
-+	return slot >> 1;
-+}
-+
-+/*
-+ * Calculate channel position from mask and slot width.
-+ *
-+ * Mask must contain exactly 2 set bits.
-+ * Lowest set bit is channel 1 position, highest set bit channel 2.
-+ * The constant offset is added to both channel positions.
-+ *
-+ * If odd_offset is > 0 slot positions are translated to
-+ * I2S-style TDM slot numbering ( 0 2 ... 3 4 ...) with odd
-+ * logical slot numbers starting at physical slot odd_offset.
-+ */
-+static void bcm2835_i2s_calc_channel_pos(
-+	unsigned int *ch1_pos, unsigned int *ch2_pos,
-+	unsigned int mask, unsigned int width,
-+	unsigned int bit_offset, unsigned int odd_offset)
-+{
-+	*ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset)
-+			* width + bit_offset;
-+	*ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset)
-+			* width + bit_offset;
-+}
-+
- static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
- 				 struct snd_pcm_hw_params *params,
- 				 struct snd_soc_dai *dai)
- {
- 	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
--	unsigned int sampling_rate = params_rate(params);
--	unsigned int data_length, data_delay, bclk_ratio;
--	unsigned int ch1pos, ch2pos, mode, format;
-+	unsigned int data_length, data_delay, framesync_length;
-+	unsigned int slots, slot_width, odd_slot_offset;
-+	int frame_length, bclk_rate;
-+	unsigned int rx_mask, tx_mask;
-+	unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
-+	unsigned int mode, format;
- 	uint32_t csreg;
-+	int ret = 0;
- 
- 	/*
- 	 * If a stream is already enabled,
-@@ -248,39 +356,44 @@ static int bcm2835_i2s_hw_params(struct
- 	if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON))
- 		return 0;
- 
--	/*
--	 * Adjust the data length according to the format.
--	 * We prefill the half frame length with an integer
--	 * divider of 2400 as explained at the clock settings.
--	 * Maybe it is overwritten there, if the Integer mode
--	 * does not apply.
--	 */
--	switch (params_format(params)) {
--	case SNDRV_PCM_FORMAT_S16_LE:
--		data_length = 16;
--		break;
--	case SNDRV_PCM_FORMAT_S24_LE:
--		data_length = 24;
--		break;
--	case SNDRV_PCM_FORMAT_S32_LE:
--		data_length = 32;
--		break;
--	default:
--		return -EINVAL;
-+	data_length = params_width(params);
-+	data_delay = 0;
-+	odd_slot_offset = 0;
-+	mode = 0;
-+
-+	if (dev->tdm_slots) {
-+		slots = dev->tdm_slots;
-+		slot_width = dev->slot_width;
-+		frame_length = dev->frame_length;
-+		rx_mask = dev->rx_mask;
-+		tx_mask = dev->tx_mask;
-+		bclk_rate = dev->frame_length * params_rate(params);
-+	} else {
-+		slots = 2;
-+		slot_width = params_width(params);
-+		rx_mask = 0x03;
-+		tx_mask = 0x03;
-+
-+		frame_length = snd_soc_params_to_frame_size(params);
-+		if (frame_length < 0)
-+			return frame_length;
-+
-+		bclk_rate = snd_soc_params_to_bclk(params);
-+		if (bclk_rate < 0)
-+			return bclk_rate;
- 	}
- 
--	/* If bclk_ratio already set, use that one. */
--	if (dev->bclk_ratio)
--		bclk_ratio = dev->bclk_ratio;
--	else
--		/* otherwise calculate a fitting block ratio */
--		bclk_ratio = 2 * data_length;
-+	/* Check if data fits into slots */
-+	if (data_length > slot_width)
-+		return -EINVAL;
- 
- 	/* Clock should only be set up here if CPU is clock master */
- 	switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
- 	case SND_SOC_DAIFMT_CBS_CFS:
- 	case SND_SOC_DAIFMT_CBS_CFM:
--		clk_set_rate(dev->clk, sampling_rate * bclk_ratio);
-+		ret = clk_set_rate(dev->clk, bclk_rate);
-+		if (ret)
-+			return ret;
- 		break;
- 	default:
- 		break;
-@@ -294,9 +407,26 @@ static int bcm2835_i2s_hw_params(struct
- 
- 	format |= BCM2835_I2S_CHWID((data_length-8)&0xf);
- 
-+	/* CH2 format is the same as for CH1 */
-+	format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
-+
- 	switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
- 	case SND_SOC_DAIFMT_I2S:
-+		/* I2S mode needs an even number of slots */
-+		if (slots & 1)
-+			return -EINVAL;
-+
-+		/*
-+		 * Use I2S-style logical slot numbering: even slots
-+		 * are in first half of frame, odd slots in second half.
-+		 */
-+		odd_slot_offset = slots >> 1;
-+
-+		/* MSB starts one cycle after frame start */
- 		data_delay = 1;
-+
-+		/* Setup frame sync signal for 50% duty cycle */
-+		framesync_length = frame_length / 2;
- 		break;
- 	default:
- 		/*
-@@ -307,19 +437,10 @@ static int bcm2835_i2s_hw_params(struct
- 		return -EINVAL;
- 	}
- 
--	ch1pos = data_delay;
--	ch2pos = bclk_ratio / 2 + data_delay;
--
--	switch (params_channels(params)) {
--	case 2:
--	case 8:
--		format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
--		format |= BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(ch1pos));
--		format |= BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(ch2pos));
--		break;
--	default:
--		return -EINVAL;
--	}
-+	bcm2835_i2s_calc_channel_pos(&rx_ch1_pos, &rx_ch2_pos,
-+		rx_mask, slot_width, data_delay, odd_slot_offset);
-+	bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos,
-+		tx_mask, slot_width, data_delay, odd_slot_offset);
- 
- 	/*
- 	 * Set format for both streams.
-@@ -327,11 +448,16 @@ static int bcm2835_i2s_hw_params(struct
- 	 * (and therefore word length) anyway,
- 	 * so the format will be the same.
- 	 */
--	regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, format);
--	regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, format);
-+	regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, 
-+		  format
-+		| BCM2835_I2S_CH1_POS(rx_ch1_pos)
-+		| BCM2835_I2S_CH2_POS(rx_ch2_pos));
-+	regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, 
-+		  format
-+		| BCM2835_I2S_CH1_POS(tx_ch1_pos)
-+		| BCM2835_I2S_CH2_POS(tx_ch2_pos));
- 
- 	/* Setup the I2S mode */
--	mode = 0;
- 
- 	if (data_length <= 16) {
- 		/*
-@@ -343,8 +469,8 @@ static int bcm2835_i2s_hw_params(struct
- 		mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP;
- 	}
- 
--	mode |= BCM2835_I2S_FLEN(bclk_ratio - 1);
--	mode |= BCM2835_I2S_FSLEN(bclk_ratio / 2);
-+	mode |= BCM2835_I2S_FLEN(frame_length - 1);
-+	mode |= BCM2835_I2S_FSLEN(framesync_length);
- 
- 	/* Master or slave? */
- 	switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-@@ -424,7 +550,20 @@ static int bcm2835_i2s_hw_params(struct
- 	/* Clear FIFOs */
- 	bcm2835_i2s_clear_fifos(dev, true, true);
- 
--	return 0;
-+	dev_dbg(dev->dev,
-+		"slots: %d width: %d rx mask: 0x%02x tx_mask: 0x%02x\n",
-+		slots, slot_width, rx_mask, tx_mask);
-+
-+	dev_dbg(dev->dev, "frame len: %d sync len: %d data len: %d\n",
-+		frame_length, framesync_length, data_length);
-+
-+	dev_dbg(dev->dev, "rx pos: %d,%d tx pos: %d,%d\n",
-+		rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos);
-+
-+	dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
-+		params_rate(params), bclk_rate);
-+
-+	return ret;
- }
- 
- static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
-@@ -560,6 +699,7 @@ static const struct snd_soc_dai_ops bcm2
- 	.hw_params	= bcm2835_i2s_hw_params,
- 	.set_fmt	= bcm2835_i2s_set_dai_fmt,
- 	.set_bclk_ratio	= bcm2835_i2s_set_dai_bclk_ratio,
-+	.set_tdm_slot	= bcm2835_i2s_set_dai_tdm_slot,
- };
- 
- static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
-@@ -700,9 +840,6 @@ static int bcm2835_i2s_probe(struct plat
- 	dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags =
- 		SND_DMAENGINE_PCM_DAI_FLAG_PACK;
- 
--	/* BCLK ratio - use default */
--	dev->bclk_ratio = 0;
--
- 	/* Store the pdev */
- 	dev->dev = &pdev->dev;
- 	dev_set_drvdata(&pdev->dev, dev);
diff --git a/target/linux/brcm2708/patches-4.14/950-0116-ASoC-bcm2835-Support-left-right-justified-and-DSP-mo.patch b/target/linux/brcm2708/patches-4.14/950-0116-ASoC-bcm2835-Support-left-right-justified-and-DSP-mo.patch
deleted file mode 100644
index af002128f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0116-ASoC-bcm2835-Support-left-right-justified-and-DSP-mo.patch
+++ /dev/null
@@ -1,246 +0,0 @@
-From d56239568d5f3b2a5519e9b08cba847c1354ad54 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Sun, 7 May 2017 15:30:50 +0200
-Subject: [PATCH 116/454] ASoC: bcm2835: Support left/right justified and DSP
- modes
-
-DSP modes and left/right justified modes can be supported
-on bcm2835 by configuring the frame sync polarity and
-frame sync length registers and by adjusting the
-channel data position registers.
-
-Clock and frame sync polarity handling in hw_params has
-been refactored to make the interaction between logical
-rising/falling edge frame start and physical configuration
-(changed by normal/inverted polarity modes) clearer.
-
-Modes where the first active data bit is transmitted immediately
-after frame start (eg DSP mode B with slot 0 active)
-only work reliable if bcm2835 is configured as frame master.
-In frame slave mode channel swap (or shift, this isn't quite
-clear yet) can occur.
-
-Currently the driver only warns if an unstable configuration
-is detected but doensn't prevent using them.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/bcm2835-i2s.c | 152 +++++++++++++++++++++++-------------
- 1 file changed, 99 insertions(+), 53 deletions(-)
-
---- a/sound/soc/bcm/bcm2835-i2s.c
-+++ b/sound/soc/bcm/bcm2835-i2s.c
-@@ -344,6 +344,9 @@ static int bcm2835_i2s_hw_params(struct
- 	unsigned int rx_mask, tx_mask;
- 	unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
- 	unsigned int mode, format;
-+	bool bit_clock_master = false;
-+	bool frame_sync_master = false;
-+	bool frame_start_falling_edge = false;
- 	uint32_t csreg;
- 	int ret = 0;
- 
-@@ -387,16 +390,39 @@ static int bcm2835_i2s_hw_params(struct
- 	if (data_length > slot_width)
- 		return -EINVAL;
- 
--	/* Clock should only be set up here if CPU is clock master */
-+	/* Check if CPU is bit clock master */
- 	switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
- 	case SND_SOC_DAIFMT_CBS_CFS:
- 	case SND_SOC_DAIFMT_CBS_CFM:
--		ret = clk_set_rate(dev->clk, bclk_rate);
--		if (ret)
--			return ret;
-+		bit_clock_master = true;
-+		break;
-+	case SND_SOC_DAIFMT_CBM_CFS:
-+	case SND_SOC_DAIFMT_CBM_CFM:
-+		bit_clock_master = false;
- 		break;
- 	default:
-+		return -EINVAL;
-+	}
-+
-+	/* Check if CPU is frame sync master */
-+	switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+	case SND_SOC_DAIFMT_CBS_CFS:
-+	case SND_SOC_DAIFMT_CBM_CFS:
-+		frame_sync_master = true;
-+		break;
-+	case SND_SOC_DAIFMT_CBS_CFM:
-+	case SND_SOC_DAIFMT_CBM_CFM:
-+		frame_sync_master = false;
- 		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	/* Clock should only be set up here if CPU is clock master */
-+	if (bit_clock_master) {
-+		ret = clk_set_rate(dev->clk, bclk_rate);
-+		if (ret)
-+			return ret;
- 	}
- 
- 	/* Setup the frame format */
-@@ -427,13 +453,41 @@ static int bcm2835_i2s_hw_params(struct
- 
- 		/* Setup frame sync signal for 50% duty cycle */
- 		framesync_length = frame_length / 2;
-+		frame_start_falling_edge = true;
-+		break;
-+	case SND_SOC_DAIFMT_LEFT_J:
-+		if (slots & 1)
-+			return -EINVAL;
-+
-+		odd_slot_offset = slots >> 1;
-+		data_delay = 0;
-+		framesync_length = frame_length / 2;
-+		frame_start_falling_edge = false;
-+		break;
-+	case SND_SOC_DAIFMT_RIGHT_J:
-+		if (slots & 1)
-+			return -EINVAL;
-+
-+		/* Odd frame lengths aren't supported */
-+		if (frame_length & 1)
-+			return -EINVAL;
-+
-+		odd_slot_offset = slots >> 1;
-+		data_delay = slot_width - data_length;
-+		framesync_length = frame_length / 2;
-+		frame_start_falling_edge = false;
-+		break;
-+	case SND_SOC_DAIFMT_DSP_A:
-+		data_delay = 1;
-+		framesync_length = 1;
-+		frame_start_falling_edge = false;
-+		break;
-+	case SND_SOC_DAIFMT_DSP_B:
-+		data_delay = 0;
-+		framesync_length = 1;
-+		frame_start_falling_edge = false;
- 		break;
- 	default:
--		/*
--		 * TODO
--		 * Others are possible but are not implemented at the moment.
--		 */
--		dev_err(dev->dev, "%s:bad format\n", __func__);
- 		return -EINVAL;
- 	}
- 
-@@ -443,6 +497,15 @@ static int bcm2835_i2s_hw_params(struct
- 		tx_mask, slot_width, data_delay, odd_slot_offset);
- 
- 	/*
-+	 * Transmitting data immediately after frame start, eg
-+	 * in left-justified or DSP mode A, only works stable
-+	 * if bcm2835 is the frame clock master.
-+	 */
-+	if ((!rx_ch1_pos || !tx_ch1_pos) && !frame_sync_master)
-+		dev_warn(dev->dev,
-+			"Unstable slave config detected, L/R may be swapped");
-+
-+	/*
- 	 * Set format for both streams.
- 	 * We cannot set another frame length
- 	 * (and therefore word length) anyway,
-@@ -472,62 +535,38 @@ static int bcm2835_i2s_hw_params(struct
- 	mode |= BCM2835_I2S_FLEN(frame_length - 1);
- 	mode |= BCM2835_I2S_FSLEN(framesync_length);
- 
--	/* Master or slave? */
--	switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
--	case SND_SOC_DAIFMT_CBS_CFS:
--		/* CPU is master */
--		break;
--	case SND_SOC_DAIFMT_CBM_CFS:
--		/*
--		 * CODEC is bit clock master
--		 * CPU is frame master
--		 */
-+	/* CLKM selects bcm2835 clock slave mode */
-+	if (!bit_clock_master)
- 		mode |= BCM2835_I2S_CLKM;
--		break;
--	case SND_SOC_DAIFMT_CBS_CFM:
--		/*
--		 * CODEC is frame master
--		 * CPU is bit clock master
--		 */
-+
-+	/* FSM selects bcm2835 frame sync slave mode */
-+	if (!frame_sync_master)
- 		mode |= BCM2835_I2S_FSM;
-+
-+	/* CLKI selects normal clocking mode, sampling on rising edge */
-+        switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
-+	case SND_SOC_DAIFMT_NB_NF:
-+	case SND_SOC_DAIFMT_NB_IF:
-+		mode |= BCM2835_I2S_CLKI;
- 		break;
--	case SND_SOC_DAIFMT_CBM_CFM:
--		/* CODEC is master */
--		mode |= BCM2835_I2S_CLKM;
--		mode |= BCM2835_I2S_FSM;
-+	case SND_SOC_DAIFMT_IB_NF:
-+	case SND_SOC_DAIFMT_IB_IF:
- 		break;
- 	default:
--		dev_err(dev->dev, "%s:bad master\n", __func__);
- 		return -EINVAL;
- 	}
- 
--	/*
--	 * Invert clocks?
--	 *
--	 * The BCM approach seems to be inverted to the classical I2S approach.
--	 */
-+	/* FSI selects frame start on falling edge */
- 	switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
- 	case SND_SOC_DAIFMT_NB_NF:
--		/* None. Therefore, both for BCM */
--		mode |= BCM2835_I2S_CLKI;
--		mode |= BCM2835_I2S_FSI;
--		break;
--	case SND_SOC_DAIFMT_IB_IF:
--		/* Both. Therefore, none for BCM */
-+	case SND_SOC_DAIFMT_IB_NF:
-+		if (frame_start_falling_edge)
-+			mode |= BCM2835_I2S_FSI;
- 		break;
- 	case SND_SOC_DAIFMT_NB_IF:
--		/*
--		 * Invert only frame sync. Therefore,
--		 * invert only bit clock for BCM
--		 */
--		mode |= BCM2835_I2S_CLKI;
--		break;
--	case SND_SOC_DAIFMT_IB_NF:
--		/*
--		 * Invert only bit clock. Therefore,
--		 * invert only frame sync for BCM
--		 */
--		mode |= BCM2835_I2S_FSI;
-+	case SND_SOC_DAIFMT_IB_IF:
-+		if (!frame_start_falling_edge)
-+			mode |= BCM2835_I2S_FSI;
- 		break;
- 	default:
- 		return -EINVAL;
-@@ -563,6 +602,13 @@ static int bcm2835_i2s_hw_params(struct
- 	dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
- 		params_rate(params), bclk_rate);
- 
-+	dev_dbg(dev->dev, "CLKM: %d CLKI: %d FSM: %d FSI: %d frame start: %s edge\n",
-+		!!(mode & BCM2835_I2S_CLKM),
-+		!!(mode & BCM2835_I2S_CLKI),
-+		!!(mode & BCM2835_I2S_FSM),
-+		!!(mode & BCM2835_I2S_FSI),
-+		(mode & BCM2835_I2S_FSI) ? "falling" : "rising");
-+
- 	return ret;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0117-ASoC-bcm2835-Support-additional-samplerates-up-to-38.patch b/target/linux/brcm2708/patches-4.14/950-0117-ASoC-bcm2835-Support-additional-samplerates-up-to-38.patch
deleted file mode 100644
index 4036fc5d6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0117-ASoC-bcm2835-Support-additional-samplerates-up-to-38.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From d72ed21ec11a87f1fdc0d58f7af1dada3361d57b Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Sun, 7 May 2017 16:19:54 +0200
-Subject: [PATCH 117/454] ASoC: bcm2835: Support additional samplerates up to
- 384kHz
-
-Sample rates are only restricted by the capabilities of the
-clock driver, so use SNDRV_PCM_RATE_CONTINUOUS instead of
-SNDRV_PCM_RATE_8000_192000.
-
-Tests (eg with pcm5122) have shown that bcm2835 works fine
-in 384kHz/32bit stereo mode, so change the maximum allowed
-rate from 192kHz to 384kHz.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/bcm2835-i2s.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
---- a/sound/soc/bcm/bcm2835-i2s.c
-+++ b/sound/soc/bcm/bcm2835-i2s.c
-@@ -765,7 +765,9 @@ static struct snd_soc_dai_driver bcm2835
- 	.playback = {
- 		.channels_min = 2,
- 		.channels_max = 2,
--		.rates =	SNDRV_PCM_RATE_8000_192000,
-+		.rates =	SNDRV_PCM_RATE_CONTINUOUS,
-+		.rate_min =	8000,
-+		.rate_max =	384000,
- 		.formats =	SNDRV_PCM_FMTBIT_S16_LE
- 				| SNDRV_PCM_FMTBIT_S24_LE
- 				| SNDRV_PCM_FMTBIT_S32_LE
-@@ -773,7 +775,9 @@ static struct snd_soc_dai_driver bcm2835
- 	.capture = {
- 		.channels_min = 2,
- 		.channels_max = 2,
--		.rates =	SNDRV_PCM_RATE_8000_192000,
-+		.rates =	SNDRV_PCM_RATE_CONTINUOUS,
-+		.rate_min =	8000,
-+		.rate_max =	384000,
- 		.formats =	SNDRV_PCM_FMTBIT_S16_LE
- 				| SNDRV_PCM_FMTBIT_S24_LE
- 				| SNDRV_PCM_FMTBIT_S32_LE
diff --git a/target/linux/brcm2708/patches-4.14/950-0118-ASoC-bcm2835-Enforce-full-symmetry.patch b/target/linux/brcm2708/patches-4.14/950-0118-ASoC-bcm2835-Enforce-full-symmetry.patch
deleted file mode 100644
index b07a02b9c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0118-ASoC-bcm2835-Enforce-full-symmetry.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 5f88ff5e23cd30d28c0f4604cd159d899fde4dc7 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Sun, 7 May 2017 16:24:57 +0200
-Subject: [PATCH 118/454] ASoC: bcm2835: Enforce full symmetry
-
-bcm2835's configuration registers can't be changed when a stream
-is running, which means asymmetric configurations aren't supported.
-
-Channel and rate symmetry are already enforced by constraints
-but samplebits had been missed.
-
-As hw_params doesn't check for symmetry constraints by itself
-and just returns success if a stream is running this led to
-situations where asymmetric configurations were seeming to
-succeed but of course didn't work because the hardware wasn't
-configured at all.
-
-Fix this by adding the missing samplerate symmetry constraint.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/bcm2835-i2s.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/sound/soc/bcm/bcm2835-i2s.c
-+++ b/sound/soc/bcm/bcm2835-i2s.c
-@@ -783,7 +783,8 @@ static struct snd_soc_dai_driver bcm2835
- 				| SNDRV_PCM_FMTBIT_S32_LE
- 		},
- 	.ops = &bcm2835_i2s_dai_ops,
--	.symmetric_rates = 1
-+	.symmetric_rates = 1,
-+	.symmetric_samplebits = 1,
- };
- 
- static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg)
diff --git a/target/linux/brcm2708/patches-4.14/950-0119-dma-bcm2708-Fix-module-compilation-of-CONFIG_DMA_BCM.patch b/target/linux/brcm2708/patches-4.14/950-0119-dma-bcm2708-Fix-module-compilation-of-CONFIG_DMA_BCM.patch
deleted file mode 100644
index aff50554a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0119-dma-bcm2708-Fix-module-compilation-of-CONFIG_DMA_BCM.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 6156ba379ce50e8a969e4e87c9e1eddb117a9e4c Mon Sep 17 00:00:00 2001
-From: Andrei Gherzan <andrei@gherzan.com>
-Date: Mon, 5 Jun 2017 16:40:38 +0100
-Subject: [PATCH 119/454] dma-bcm2708: Fix module compilation of
- CONFIG_DMA_BCM2708
-
-bcm2708-dmaengine.c defines functions like bcm_dma_start which are
-defined as well in dma-bcm2708.h as inline versions when
-CONFIG_DMA_BCM2708 is not defined. This works fine when
-CONFIG_DMA_BCM2708 is built in, but when it is selected as module build
-fails with redefinition errors because in the build system when
-CONFIG_DMA_BCM2708 is selected as module, the macro becomes
-CONFIG_DMA_BCM2708_MODULE.
-
-This patch makes the header use CONFIG_DMA_BCM2708_MODULE too when
-available.
-
-Fixes https://github.com/raspberrypi/linux/issues/2056
-
-Signed-off-by: Andrei Gherzan <andrei@gherzan.com>
----
- include/linux/platform_data/dma-bcm2708.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/include/linux/platform_data/dma-bcm2708.h
-+++ b/include/linux/platform_data/dma-bcm2708.h
-@@ -75,7 +75,7 @@ struct bcm2708_dma_cb {
- struct scatterlist;
- struct platform_device;
- 
--#ifdef CONFIG_DMA_BCM2708
-+#if defined(CONFIG_DMA_BCM2708) || defined(CONFIG_DMA_BCM2708_MODULE)
- 
- int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
- void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block);
-@@ -138,6 +138,6 @@ static inline int bcm_dmaman_remove(stru
- 	return 0;
- }
- 
--#endif /* CONFIG_DMA_BCM2708 */
-+#endif /* CONFIG_DMA_BCM2708 || CONFIG_DMA_BCM2708_MODULE */
- 
- #endif /* _PLAT_BCM2708_DMA_H */
diff --git a/target/linux/brcm2708/patches-4.14/950-0120-cache-export-clean-and-invalidate.patch b/target/linux/brcm2708/patches-4.14/950-0120-cache-export-clean-and-invalidate.patch
deleted file mode 100644
index 13f49e60c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0120-cache-export-clean-and-invalidate.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From ef48045e357c3ec1bb9a434fac0c814f8a8669ef Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Fri, 25 Aug 2017 19:18:13 +0100
-Subject: [PATCH 120/454] cache: export clean and invalidate
-
----
- arch/arm/mm/cache-v6.S | 4 ++--
- arch/arm/mm/cache-v7.S | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/mm/cache-v6.S
-+++ b/arch/arm/mm/cache-v6.S
-@@ -201,7 +201,7 @@ ENTRY(v6_flush_kern_dcache_area)
-  *	- start   - virtual start address of region
-  *	- end     - virtual end address of region
-  */
--v6_dma_inv_range:
-+ENTRY(v6_dma_inv_range)
- #ifdef CONFIG_DMA_CACHE_RWFO
- 	ldrb	r2, [r0]			@ read for ownership
- 	strb	r2, [r0]			@ write for ownership
-@@ -246,7 +246,7 @@ v6_dma_inv_range:
-  *	- start   - virtual start address of region
-  *	- end     - virtual end address of region
-  */
--v6_dma_clean_range:
-+ENTRY(v6_dma_clean_range)
- 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
- 1:
- #ifdef CONFIG_DMA_CACHE_RWFO
---- a/arch/arm/mm/cache-v7.S
-+++ b/arch/arm/mm/cache-v7.S
-@@ -349,7 +349,7 @@ ENDPROC(v7_flush_kern_dcache_area)
-  *	- start   - virtual start address of region
-  *	- end     - virtual end address of region
-  */
--v7_dma_inv_range:
-+ENTRY(v7_dma_inv_range)
- 	dcache_line_size r2, r3
- 	sub	r3, r2, #1
- 	tst	r0, r3
-@@ -379,7 +379,7 @@ ENDPROC(v7_dma_inv_range)
-  *	- start   - virtual start address of region
-  *	- end     - virtual end address of region
-  */
--v7_dma_clean_range:
-+ENTRY(v7_dma_clean_range)
- 	dcache_line_size r2, r3
- 	sub	r3, r2, #1
- 	bic	r0, r0, r3
diff --git a/target/linux/brcm2708/patches-4.14/950-0121-amba_pl011-Insert-mb-for-correct-FIFO-handling.patch b/target/linux/brcm2708/patches-4.14/950-0121-amba_pl011-Insert-mb-for-correct-FIFO-handling.patch
deleted file mode 100644
index 37fd83e29..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0121-amba_pl011-Insert-mb-for-correct-FIFO-handling.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 436e9b301802720c0bf0f080301263c6e926d723 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 29 Sep 2017 10:32:19 +0100
-Subject: [PATCH 121/454] amba_pl011: Insert mb() for correct FIFO handling
-
-The pl011 register accessor functions use the _relaxed versions of the
-standard readl() and writel() functions, meaning that there are no
-automatic memory barriers. When polling a FIFO status register to check
-for fullness, it is necessary to ensure that any outstanding writes have
-completed; otherwise the flags are effectively stale, making it possible
-that the next write is to a full FIFO.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/tty/serial/amba-pl011.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/tty/serial/amba-pl011.c
-+++ b/drivers/tty/serial/amba-pl011.c
-@@ -1403,6 +1403,7 @@ static bool pl011_tx_char(struct uart_am
- 		return false; /* unable to transmit character */
- 
- 	pl011_write(c, uap, REG_DR);
-+	mb();
- 	uap->port.icount.tx++;
- 
- 	return true;
diff --git a/target/linux/brcm2708/patches-4.14/950-0122-amba_pl011-Add-cts-event-workaround-DT-property.patch b/target/linux/brcm2708/patches-4.14/950-0122-amba_pl011-Add-cts-event-workaround-DT-property.patch
deleted file mode 100644
index 2e994e374..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0122-amba_pl011-Add-cts-event-workaround-DT-property.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From ca1ca821f735ad6284fa0c6228f27415e90f7a8f Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 29 Sep 2017 10:32:19 +0100
-Subject: [PATCH 122/454] amba_pl011: Add cts-event-workaround DT property
-
-The BCM2835 PL011 implementation seems to have a bug that can lead to a
-transmission lockup if CTS changes frequently. A workaround was added to
-the driver with a vendor-specific flag to enable it, but this flag is
-currently not set for ARM implementations.
-
-Add a "cts-event-workaround" property to Pi DTBs and use the presence
-of that property to force the flag to be enabled in the driver.
-
-See: https://github.com/raspberrypi/linux/issues/1280
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- Documentation/devicetree/bindings/serial/pl011.txt | 3 +++
- drivers/tty/serial/amba-pl011.c                    | 5 +++++
- 2 files changed, 8 insertions(+)
-
---- a/Documentation/devicetree/bindings/serial/pl011.txt
-+++ b/Documentation/devicetree/bindings/serial/pl011.txt
-@@ -35,6 +35,9 @@ Optional properties:
- - poll-timeout-ms:
- 	   Poll timeout when auto-poll is set, default
- 	   3000ms.
-+- cts-event-workaround:
-+	   Enables the (otherwise vendor-specific) workaround for the
-+	   CTS-induced TX lockup.
- 
- See also bindings/arm/primecell.txt
- 
---- a/drivers/tty/serial/amba-pl011.c
-+++ b/drivers/tty/serial/amba-pl011.c
-@@ -2681,6 +2681,11 @@ static int pl011_probe(struct amba_devic
- 	if (IS_ERR(uap->clk))
- 		return PTR_ERR(uap->clk);
- 
-+	if (of_property_read_bool(dev->dev.of_node, "cts-event-workaround")) {
-+	    vendor->cts_event_workaround = true;
-+	    dev_info(&dev->dev, "cts_event_workaround enabled\n");
-+	}
-+
- 	uap->reg_offset = vendor->reg_offset;
- 	uap->vendor = vendor;
- 	uap->fifosize = vendor->get_fifosize(dev);
diff --git a/target/linux/brcm2708/patches-4.14/950-0123-amba-pl011-Report-AUTOCTS-capability-to-framework.patch b/target/linux/brcm2708/patches-4.14/950-0123-amba-pl011-Report-AUTOCTS-capability-to-framework.patch
deleted file mode 100644
index f491df2b8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0123-amba-pl011-Report-AUTOCTS-capability-to-framework.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From fc4fafeed9a7cc89b4779681f046a8cc0f506dd9 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 11 Oct 2017 13:48:04 +0100
-Subject: [PATCH 123/454] amba-pl011: Report AUTOCTS capability to framework
-
-The PL011 has full hardware RTS/CTS support which is enabled by
-the driver when flow control is requested. However, it doesn't
-notify the UART framework of the fact, causing the software CTS
-support to be enabled at the same time.
-
-Software CTS triggers the sending of another batch of characters
-when CTS becomes asserted. The pl011 interrupt handler processes
-the CTIS bit before TXIS, which can cause some characters to be
-sent between the time that the TXIS bit first becomes asserted
-and the time it is handled by a call to px011_tx_chars. This
-would be fine were it not for the optimisation in pl011_tx_char
-that assumes the FIFO is half-empty if called from the interrupt
-handler and skips the checking of the FIFO status register before
-sending each character, leading to data loss if the FIFO is more
-than half-full.
-
-Prevent the data loss and improve efficiency by indicating the
-AUTOCTS support.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/tty/serial/amba-pl011.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/tty/serial/amba-pl011.c
-+++ b/drivers/tty/serial/amba-pl011.c
-@@ -2063,9 +2063,11 @@ pl011_set_termios(struct uart_port *port
- 
- 		old_cr |= UART011_CR_CTSEN;
- 		uap->autorts = true;
-+		port->status |= UPSTAT_AUTOCTS;
- 	} else {
- 		old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
- 		uap->autorts = false;
-+		port->status &= ~UPSTAT_AUTOCTS;
- 	}
- 
- 	if (uap->vendor->oversampling) {
diff --git a/target/linux/brcm2708/patches-4.14/950-0124-scripts-Update-mkknlimg-just-in-case.patch b/target/linux/brcm2708/patches-4.14/950-0124-scripts-Update-mkknlimg-just-in-case.patch
deleted file mode 100644
index 93d9a7e31..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0124-scripts-Update-mkknlimg-just-in-case.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From e28a3464c66b5d137de4acb6595ff56a1da7d149 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 25 Oct 2017 09:20:56 +0100
-Subject: [PATCH 124/454] scripts: Update mkknlimg, just in case
-
-With the removal of the vc_cma driver, mkknlimg lost an indication that
-the user had built a downstream kernel. Update the script, adding a few
-more key strings, in case it is still being used.
-
-Note that mkknlimg is now deprecated, except to tag kernels as upstream
-(283x), and thus requiring upstream DTBs.
-
-See: https://github.com/raspberrypi/linux/issues/2239
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- scripts/mkknlimg | 9 +++------
- 1 file changed, 3 insertions(+), 6 deletions(-)
-
---- a/scripts/mkknlimg
-+++ b/scripts/mkknlimg
-@@ -68,18 +68,15 @@ if (! -r $kernel_file)
- 
- my $wanted_strings =
- {
--	'bcm2708_fb' => FLAG_PI | FLAG_270X,
- 	'brcm,bcm2835-mmc' => FLAG_PI,
- 	'brcm,bcm2835-sdhost' => FLAG_PI,
--	'brcm,bcm2708-pinctrl' => FLAG_PI | FLAG_DTOK,
- 	'brcm,bcm2835-gpio' => FLAG_PI | FLAG_DTOK,
--	'brcm,bcm2708' => FLAG_PI | FLAG_DTOK | FLAG_270X,
--	'brcm,bcm2709' => FLAG_PI | FLAG_DTOK | FLAG_270X,
-+	'brcm,bcm2708-fb'   => FLAG_PI | FLAG_DTOK | FLAG_270X,
-+	'brcm,bcm2708-usb'  => FLAG_PI | FLAG_DTOK | FLAG_270X,
- 	'brcm,bcm2835' => FLAG_PI | FLAG_DTOK | FLAG_283X,
- 	'brcm,bcm2836' => FLAG_PI | FLAG_DTOK | FLAG_283X,
-+	'brcm,bcm2837' => FLAG_PI | FLAG_DTOK | FLAG_283X,
- 	'of_cfs_init' => FLAG_DTOK | FLAG_DDTK,
--	'vc_cma_init' => FLAG_PI | FLAG_270X,
--	'vc-mem' => FLAG_PI | FLAG_270X,
- };
- 
- my $res = try_extract($kernel_file, $tmpfile1);
diff --git a/target/linux/brcm2708/patches-4.14/950-0125-AXI-performance-monitor-driver-2222.patch b/target/linux/brcm2708/patches-4.14/950-0125-AXI-performance-monitor-driver-2222.patch
deleted file mode 100644
index 7ca37676b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0125-AXI-performance-monitor-driver-2222.patch
+++ /dev/null
@@ -1,681 +0,0 @@
-From accf80ccafcb88ad0ffffc11bd4e090380af6654 Mon Sep 17 00:00:00 2001
-From: James Hughes <JamesH65@users.noreply.github.com>
-Date: Tue, 14 Nov 2017 15:13:15 +0000
-Subject: [PATCH 125/454] AXI performance monitor driver (#2222)
-
-Uses the debugfs I/F to provide access to the AXI
-bus performance monitors.
-
-Requires the new mailbox peripheral access for access
-to the VPU performance registers, system bus access
-is done using direct register reads.
-
-Signed-off-by: James Hughes <james.hughes@raspberrypi.org>
----
- drivers/perf/Kconfig                   |   7 +
- drivers/perf/Makefile                  |   1 +
- drivers/perf/raspberrypi_axi_monitor.c | 637 +++++++++++++++++++++++++
- 3 files changed, 645 insertions(+)
- create mode 100644 drivers/perf/raspberrypi_axi_monitor.c
-
---- a/drivers/perf/Kconfig
-+++ b/drivers/perf/Kconfig
-@@ -43,4 +43,11 @@ config XGENE_PMU
-         help
-           Say y if you want to use APM X-Gene SoC performance monitors.
- 
-+config RPI_AXIPERF
-+        depends on ARCH_BCM2835
-+        tristate "RaspberryPi AXI Performance monitors"
-+        default n
-+        help
-+          Say y if you want to use Raspberry Pi AXI performance monitors, m if
-+          you want to build it as a module.
- endmenu
---- a/drivers/perf/Makefile
-+++ b/drivers/perf/Makefile
-@@ -4,3 +4,4 @@ obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_ac
- obj-$(CONFIG_QCOM_L2_PMU)	+= qcom_l2_pmu.o
- obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
- obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
-+obj-$(CONFIG_RPI_AXIPERF) += raspberrypi_axi_monitor.o
---- /dev/null
-+++ b/drivers/perf/raspberrypi_axi_monitor.c
-@@ -0,0 +1,637 @@
-+/*
-+ * raspberrypi_axi_monitor.c
-+ *
-+ * Author: james.hughes@raspberrypi.org
-+ *
-+ * Raspberry Pi AXI performance counters.
-+ *
-+ * Copyright (C) 2017 Raspberry Pi Trading Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/debugfs.h>
-+#include <linux/devcoredump.h>
-+#include <linux/device.h>
-+#include <linux/kthread.h>
-+#include <linux/module.h>
-+#include <linux/netdevice.h>
-+#include <linux/mutex.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+#define NUM_MONITORS 2
-+#define NUM_BUS_WATCHERS_PER_MONITOR 3
-+
-+#define SYSTEM_MONITOR 0
-+#define VPU_MONITOR 1
-+
-+#define MAX_BUSES 16
-+#define DEFAULT_SAMPLE_TIME 100
-+
-+#define NUM_BUS_WATCHER_RESULTS 9
-+
-+struct bus_watcher_data {
-+	union	{
-+		u32 results[NUM_BUS_WATCHER_RESULTS];
-+		struct {
-+			u32 atrans;
-+			u32 atwait;
-+			u32 amax;
-+			u32 wtrans;
-+			u32 wtwait;
-+			u32 wmax;
-+			u32 rtrans;
-+			u32 rtwait;
-+			u32 rmax;
-+		};
-+	};
-+};
-+
-+
-+struct rpi_axiperf {
-+	struct platform_device *dev;
-+	struct dentry *root_folder;
-+
-+	struct task_struct *monitor_thread;
-+	struct mutex lock;
-+
-+	struct rpi_firmware *firmware;
-+
-+	/* Sample time spent on for each bus */
-+	int sample_time;
-+
-+	/* Now storage for the per monitor settings and the resulting
-+	 * performance figures
-+	 */
-+	struct {
-+		/* Bit field of buses we want to monitor */
-+		int bus_enabled;
-+		/* Bit field of buses to filter by */
-+		int bus_filter;
-+		/* The current buses being monitored on this monitor */
-+		int current_bus[NUM_BUS_WATCHERS_PER_MONITOR];
-+		/* The last bus monitored on this monitor */
-+		int last_monitored;
-+
-+		/* Set true if this mailbox must use the mailbox interface
-+		 * rather than access registers directly.
-+		 */
-+		int use_mailbox_interface;
-+
-+		/* Current result values */
-+		struct bus_watcher_data results[MAX_BUSES];
-+
-+		struct dentry *debugfs_entry;
-+		void __iomem *base_address;
-+
-+	}  monitor[NUM_MONITORS];
-+
-+};
-+
-+static struct rpi_axiperf *state;
-+
-+/* Two monitors, System and VPU, each with the following register sets.
-+ * Each monitor can only monitor one bus at a time, so we time share them,
-+ * giving each bus 100ms (default, settable via debugfs) of time on its
-+ * associated monitor
-+ * Record results from the three Bus watchers per monitor and push to the sysfs
-+ */
-+
-+/* general registers */
-+const int GEN_CTRL;
-+
-+const int GEN_CTL_ENABLE_BIT	= BIT(0);
-+const int GEN_CTL_RESET_BIT	= BIT(1);
-+
-+/* Bus watcher registers */
-+const int BW_PITCH		= 0x40;
-+
-+const int BW0_CTRL		= 0x40;
-+const int BW1_CTRL		= 0x80;
-+const int BW2_CTRL		= 0xc0;
-+
-+const int BW_ATRANS_OFFSET	= 0x04;
-+const int BW_ATWAIT_OFFSET	= 0x08;
-+const int BW_AMAX_OFFSET	= 0x0c;
-+const int BW_WTRANS_OFFSET	= 0x10;
-+const int BW_WTWAIT_OFFSET	= 0x14;
-+const int BW_WMAX_OFFSET	= 0x18;
-+const int BW_RTRANS_OFFSET	= 0x1c;
-+const int BW_RTWAIT_OFFSET	= 0x20;
-+const int BW_RMAX_OFFSET	= 0x24;
-+
-+const int BW_CTRL_RESET_BIT	= BIT(31);
-+const int BW_CTRL_ENABLE_BIT	= BIT(30);
-+const int BW_CTRL_ENABLE_ID_FILTER_BIT	= BIT(29);
-+const int BW_CTRL_LIMIT_HALT_BIT	= BIT(28);
-+
-+const int BW_CTRL_SOURCE_SHIFT	= 8;
-+const int BW_CTRL_SOURCE_MASK	= GENMASK(12, 8); // 5 bits
-+const int BW_CTRL_BUS_WATCH_SHIFT;
-+const int BW_CTRL_BUS_WATCH_MASK = GENMASK(5, 0); // 6 bits
-+const int BW_CTRL_BUS_FILTER_SHIFT = 8;
-+
-+const static char *bus_filter_strings[] = {
-+	"",
-+	"CORE0_V",
-+	"ICACHE0",
-+	"DCACHE0",
-+	"CORE1_V",
-+	"ICACHE1",
-+	"DCACHE1",
-+	"L2_MAIN",
-+	"HOST_PORT",
-+	"HOST_PORT2",
-+	"HVS",
-+	"ISP",
-+	"VIDEO_DCT",
-+	"VIDEO_SD2AXI",
-+	"CAM0",
-+	"CAM1",
-+	"DMA0",
-+	"DMA1",
-+	"DMA2_VPU",
-+	"JPEG",
-+	"VIDEO_CME",
-+	"TRANSPOSER",
-+	"VIDEO_FME",
-+	"CCP2TX",
-+	"USB",
-+	"V3D0",
-+	"V3D1",
-+	"V3D2",
-+	"AVE",
-+	"DEBUG",
-+	"CPU",
-+	"M30"
-+};
-+
-+const int num_bus_filters = ARRAY_SIZE(bus_filter_strings);
-+
-+const static char *system_bus_string[] = {
-+	"DMA_L2",
-+	"TRANS",
-+	"JPEG",
-+	"SYSTEM_UC",
-+	"DMA_UC",
-+	"SYSTEM_L2",
-+	"CCP2TX",
-+	"MPHI_RX",
-+	"MPHI_TX",
-+	"HVS",
-+	"H264",
-+	"ISP",
-+	"V3D",
-+	"PERIPHERAL",
-+	"CPU_UC",
-+	"CPU_L2"
-+};
-+
-+const int num_system_buses = ARRAY_SIZE(system_bus_string);
-+
-+const static char *vpu_bus_string[] = {
-+	"VPU1_D_L2",
-+	"VPU0_D_L2",
-+	"VPU1_I_L2",
-+	"VPU0_I_L2",
-+	"SYSTEM_L2",
-+	"L2_FLUSH",
-+	"DMA_L2",
-+	"VPU1_D_UC",
-+	"VPU0_D_UC",
-+	"VPU1_I_UC",
-+	"VPU0_I_UC",
-+	"SYSTEM_UC",
-+	"L2_OUT",
-+	"DMA_UC",
-+	"SDRAM",
-+	"L2_IN"
-+};
-+
-+const int num_vpu_buses = ARRAY_SIZE(vpu_bus_string);
-+
-+const static char *monitor_name[] = {
-+	"System",
-+	"VPU"
-+};
-+
-+static inline void write_reg(int monitor, int reg, u32 value)
-+{
-+	writel(value, state->monitor[monitor].base_address + reg);
-+}
-+
-+static inline u32 read_reg(int monitor, u32 reg)
-+{
-+	return readl(state->monitor[monitor].base_address + reg);
-+}
-+
-+static void read_bus_watcher(int monitor, int watcher, u32 *results)
-+{
-+	if (state->monitor[monitor].use_mailbox_interface) {
-+		/* We have 9 results, plus the overheads of start address and
-+		 * length So 11 u32 to define
-+		 */
-+		u32 tmp[11];
-+		int err;
-+
-+		tmp[0] = (u32)(state->monitor[monitor].base_address + watcher
-+				+ BW_ATRANS_OFFSET);
-+		tmp[1] = NUM_BUS_WATCHER_RESULTS;
-+
-+		err = rpi_firmware_property(state->firmware,
-+					    RPI_FIRMWARE_GET_PERIPH_REG,
-+					    tmp, sizeof(tmp));
-+
-+		if (err < 0 || tmp[1] != NUM_BUS_WATCHER_RESULTS)
-+			dev_err_once(&state->dev->dev,
-+				     "Failed to read bus watcher");
-+		else
-+			memcpy(results, &tmp[2],
-+			       NUM_BUS_WATCHER_RESULTS * sizeof(u32));
-+	} else {
-+		int i;
-+		void __iomem *addr = state->monitor[monitor].base_address
-+				+ watcher + BW_ATRANS_OFFSET;
-+		for (i = 0; i < NUM_BUS_WATCHER_RESULTS; i++, addr += 4)
-+			*results++ = readl(addr);
-+	}
-+}
-+
-+static void set_monitor_control(int monitor, u32 set)
-+{
-+	if (state->monitor[monitor].use_mailbox_interface) {
-+		u32 tmp[3] = {(u32)(state->monitor[monitor].base_address +
-+				GEN_CTRL), 1, set};
-+		int err = rpi_firmware_property(state->firmware,
-+						RPI_FIRMWARE_SET_PERIPH_REG,
-+						tmp, sizeof(tmp));
-+
-+		if (err < 0 || tmp[1] != 1)
-+			dev_err_once(&state->dev->dev,
-+				"Failed to set monitor control");
-+	} else
-+		write_reg(monitor, GEN_CTRL, set);
-+}
-+
-+static void set_bus_watcher_control(int monitor, int watcher, u32 set)
-+{
-+	if (state->monitor[monitor].use_mailbox_interface) {
-+		u32 tmp[3] = {(u32)(state->monitor[monitor].base_address +
-+				    watcher), 1, set};
-+		int err = rpi_firmware_property(state->firmware,
-+						RPI_FIRMWARE_SET_PERIPH_REG,
-+						tmp, sizeof(tmp));
-+		if (err < 0 || tmp[1] != 1)
-+			dev_err_once(&state->dev->dev,
-+				"Failed to set bus watcher control");
-+	} else
-+		write_reg(monitor, watcher, set);
-+}
-+
-+static void monitor(struct rpi_axiperf *state)
-+{
-+	int monitor, num_buses[NUM_MONITORS];
-+
-+	mutex_lock(&state->lock);
-+
-+	for (monitor = 0; monitor < NUM_MONITORS; monitor++) {
-+		typeof(state->monitor[0]) *mon = &(state->monitor[monitor]);
-+
-+		/* Anything enabled? */
-+		if (mon->bus_enabled == 0) {
-+			/* No, disable all monitoring for this monitor */
-+			set_monitor_control(monitor, GEN_CTL_RESET_BIT);
-+		} else {
-+			int i;
-+
-+			/* Find out how many busses we want to monitor, and
-+			 * spread our 3 actual monitors over them
-+			 */
-+			num_buses[monitor] = hweight32(mon->bus_enabled);
-+			num_buses[monitor] = min(num_buses[monitor],
-+						 NUM_BUS_WATCHERS_PER_MONITOR);
-+
-+			for (i = 0; i < num_buses[monitor]; i++) {
-+				int bus_control;
-+
-+				do {
-+					mon->last_monitored++;
-+					mon->last_monitored &= 0xf;
-+				} while ((mon->bus_enabled &
-+					 (1 << mon->last_monitored)) == 0);
-+
-+				mon->current_bus[i] = mon->last_monitored;
-+
-+				/* Reset the counters */
-+				set_bus_watcher_control(monitor,
-+							BW0_CTRL +
-+							i*BW_PITCH,
-+							BW_CTRL_RESET_BIT);
-+
-+				bus_control = BW_CTRL_ENABLE_BIT |
-+						mon->current_bus[i];
-+
-+				if (mon->bus_filter) {
-+					bus_control |=
-+						BW_CTRL_ENABLE_ID_FILTER_BIT;
-+					bus_control |=
-+						((mon->bus_filter & 0x1f)
-+						<< BW_CTRL_BUS_FILTER_SHIFT);
-+				}
-+
-+				// Start capture
-+				set_bus_watcher_control(monitor,
-+							BW0_CTRL + i*BW_PITCH,
-+							bus_control);
-+			}
-+		}
-+
-+		/* start monitoring */
-+		set_monitor_control(monitor, GEN_CTL_ENABLE_BIT);
-+	}
-+
-+	mutex_unlock(&state->lock);
-+
-+	msleep(state->sample_time);
-+
-+	/* Now read the results */
-+
-+	mutex_lock(&state->lock);
-+	for (monitor = 0; monitor < NUM_MONITORS; monitor++) {
-+		typeof(state->monitor[0]) *mon = &(state->monitor[monitor]);
-+
-+		/* Anything enabled? */
-+		if (mon->bus_enabled == 0) {
-+			/* No, disable all monitoring for this monitor */
-+			set_monitor_control(monitor, 0);
-+		} else {
-+			int i;
-+
-+			for (i = 0; i < num_buses[monitor]; i++) {
-+				int bus = mon->current_bus[i];
-+
-+				read_bus_watcher(monitor,
-+					BW0_CTRL + i*BW_PITCH,
-+					(u32 *)&mon->results[bus].results);
-+			}
-+		}
-+	}
-+	mutex_unlock(&state->lock);
-+}
-+
-+static int monitor_thread(void *data)
-+{
-+	struct rpi_axiperf *state  = data;
-+
-+	while (1) {
-+		monitor(state);
-+
-+		if (kthread_should_stop())
-+			return 0;
-+	}
-+	return 0;
-+}
-+
-+static ssize_t myreader(struct file *fp, char __user *user_buffer,
-+			size_t count, loff_t *position)
-+{
-+#define INIT_BUFF_SIZE 2048
-+
-+	int i;
-+	int idx = (int)(fp->private_data);
-+	int num_buses, cnt;
-+	char *string_buffer;
-+	int buff_size = INIT_BUFF_SIZE;
-+	char *p;
-+	typeof(state->monitor[0]) *mon = &(state->monitor[idx]);
-+
-+	if (idx < 0 || idx > NUM_MONITORS)
-+		idx = 0;
-+
-+	num_buses = idx == SYSTEM_MONITOR ? num_system_buses : num_vpu_buses;
-+
-+	string_buffer = kmalloc(buff_size, GFP_KERNEL);
-+
-+	if (!string_buffer) {
-+		dev_err(&state->dev->dev,
-+				"Failed temporary string allocation\n");
-+		return 0;
-+	}
-+
-+	p = string_buffer;
-+
-+	mutex_lock(&state->lock);
-+
-+	if (mon->bus_filter) {
-+		int filt = min(mon->bus_filter & 0x1f, num_bus_filters);
-+
-+		cnt = snprintf(p, buff_size,
-+			       "\nMonitoring transactions from %s only\n",
-+			       bus_filter_strings[filt]);
-+		p += cnt;
-+		buff_size -= cnt;
-+	}
-+
-+	cnt = snprintf(p, buff_size, "     Bus   |    Atrans    Atwait      AMax    Wtrans    Wtwait      WMax    Rtrans    Rtwait      RMax\n"
-+				     "======================================================================================================\n");
-+
-+	if (cnt >= buff_size)
-+		goto done;
-+
-+	p += cnt;
-+	buff_size -= cnt;
-+
-+	for (i = 0; i < num_buses; i++) {
-+		if (mon->bus_enabled & (1 << i)) {
-+#define DIVIDER (1024)
-+			typeof(mon->results[0]) *res = &(mon->results[i]);
-+
-+			cnt = snprintf(p, buff_size,
-+					"%10s | %8uK %8uK %8uK %8uK %8uK %8uK %8uK %8uK %8uK\n",
-+					idx == SYSTEM_MONITOR ?
-+						system_bus_string[i] :
-+						vpu_bus_string[i],
-+					res->atrans/DIVIDER,
-+					res->atwait/DIVIDER,
-+					res->amax/DIVIDER,
-+					res->wtrans/DIVIDER,
-+					res->wtwait/DIVIDER,
-+					res->wmax/DIVIDER,
-+					res->rtrans/DIVIDER,
-+					res->rtwait/DIVIDER,
-+					res->rmax/DIVIDER
-+					);
-+			if (cnt >= buff_size)
-+				goto done;
-+
-+			p += cnt;
-+			buff_size -= cnt;
-+		}
-+	}
-+
-+	mutex_unlock(&state->lock);
-+
-+done:
-+
-+	/* did the last string entry exceeed our buffer size? ie out of string
-+	 * buffer space. Null terminate, use what we have.
-+	 */
-+	if (cnt >= buff_size) {
-+		buff_size = 0;
-+		string_buffer[INIT_BUFF_SIZE] = 0;
-+	}
-+
-+	cnt = simple_read_from_buffer(user_buffer, count, position,
-+				      string_buffer,
-+				      INIT_BUFF_SIZE - buff_size);
-+
-+	kfree(string_buffer);
-+
-+	return cnt;
-+}
-+
-+static ssize_t mywriter(struct file *fp, const char __user *user_buffer,
-+			size_t count, loff_t *position)
-+{
-+	int idx = (int)(fp->private_data);
-+
-+	if (idx < 0 || idx > NUM_MONITORS)
-+		idx = 0;
-+
-+	/* At the moment, this does nothing, but in the future it could be
-+	 * used to reset counters etc
-+	 */
-+	return count;
-+}
-+
-+static const struct file_operations fops_debug = {
-+	.read = myreader,
-+	.write = mywriter,
-+	.open = simple_open
-+};
-+
-+static int rpi_axiperf_probe(struct platform_device *pdev)
-+{
-+	int ret = 0, i;
-+	struct device *dev = &pdev->dev;
-+	struct device_node *np = dev->of_node;
-+	struct device_node *fw_node;
-+
-+	state = kzalloc(sizeof(struct rpi_axiperf), GFP_KERNEL);
-+	if (!state)
-+		return -ENOMEM;
-+
-+	/* Get the firmware handle for future rpi-firmware-xxx calls */
-+	fw_node = of_parse_phandle(np, "firmware", 0);
-+	if (!fw_node) {
-+		dev_err(dev, "Missing firmware node\n");
-+		return -ENOENT;
-+	}
-+
-+	state->firmware = rpi_firmware_get(fw_node);
-+	if (!state->firmware)
-+		return -EPROBE_DEFER;
-+
-+	/* Special case for the VPU monitor, we must use the mailbox interface
-+	 * as it is not accessible from the ARM address space.
-+	 */
-+	state->monitor[VPU_MONITOR].use_mailbox_interface = 1;
-+	state->monitor[SYSTEM_MONITOR].use_mailbox_interface = 0;
-+
-+	for (i = 0; i < NUM_MONITORS; i++) {
-+		if (state->monitor[i].use_mailbox_interface) {
-+			 of_property_read_u32_index(np, "reg", i*2,
-+				(u32 *)(&state->monitor[i].base_address));
-+		} else {
-+			struct resource *resource =
-+				platform_get_resource(pdev, IORESOURCE_MEM, i);
-+
-+			state->monitor[i].base_address =
-+				devm_ioremap_resource(&pdev->dev, resource);
-+		}
-+
-+		if (IS_ERR(state->monitor[i].base_address))
-+			return PTR_ERR(state->monitor[i].base_address);
-+
-+		/* Enable all buses by default */
-+		state->monitor[i].bus_enabled = 0xffff;
-+	}
-+
-+	state->dev = pdev;
-+	platform_set_drvdata(pdev, state);
-+
-+	state->sample_time = DEFAULT_SAMPLE_TIME;
-+
-+	/* Set up all the debugfs stuff */
-+	state->root_folder = debugfs_create_dir(KBUILD_MODNAME, NULL);
-+
-+	for (i = 0; i < NUM_MONITORS; i++) {
-+		state->monitor[i].debugfs_entry =
-+			debugfs_create_dir(monitor_name[i], state->root_folder);
-+		if (IS_ERR(state->monitor[i].debugfs_entry))
-+			state->monitor[i].debugfs_entry = NULL;
-+
-+		debugfs_create_file("data", 0444,
-+				    state->monitor[i].debugfs_entry,
-+				    (void *)i, &fops_debug);
-+		debugfs_create_u32("enable", 0644,
-+				   state->monitor[i].debugfs_entry,
-+				   &state->monitor[i].bus_enabled);
-+		debugfs_create_u32("filter", 0644,
-+				   state->monitor[i].debugfs_entry,
-+				   &state->monitor[i].bus_filter);
-+		debugfs_create_u32("sample_time", 0644,
-+				   state->monitor[i].debugfs_entry,
-+				   &state->sample_time);
-+	}
-+
-+	mutex_init(&state->lock);
-+
-+	state->monitor_thread = kthread_run(monitor_thread, state,
-+					    "rpi-axiperfmon");
-+
-+	return ret;
-+
-+}
-+
-+static int rpi_axiperf_remove(struct platform_device *dev)
-+{
-+	int ret = 0;
-+
-+	kthread_stop(state->monitor_thread);
-+
-+	debugfs_remove_recursive(state->root_folder);
-+	state->root_folder = NULL;
-+
-+	return ret;
-+}
-+
-+static const struct of_device_id rpi_axiperf_match[] = {
-+	{
-+		.compatible = "brcm,bcm2835-axiperf",
-+	},
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, rpi_axiperf_match);
-+
-+static struct platform_driver rpi_axiperf_driver  = {
-+	.probe =	rpi_axiperf_probe,
-+	.remove =	rpi_axiperf_remove,
-+	.driver = {
-+		.name   = "rpi-bcm2835-axiperf",
-+		.of_match_table = of_match_ptr(rpi_axiperf_match),
-+	},
-+};
-+
-+module_platform_driver(rpi_axiperf_driver);
-+
-+/* Module information */
-+MODULE_AUTHOR("James Hughes <james.hughes@raspberrypi.org>");
-+MODULE_DESCRIPTION("RPI AXI Performance monitor driver");
-+MODULE_LICENSE("GPL");
-+
diff --git a/target/linux/brcm2708/patches-4.14/950-0126-drm-panel-Add-support-for-the-Raspberry-Pi-7-Touchsc.patch b/target/linux/brcm2708/patches-4.14/950-0126-drm-panel-Add-support-for-the-Raspberry-Pi-7-Touchsc.patch
deleted file mode 100644
index 0f1abf00f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0126-drm-panel-Add-support-for-the-Raspberry-Pi-7-Touchsc.patch
+++ /dev/null
@@ -1,576 +0,0 @@
-From a28a55876fa9df72d7e3c1bc0fc2ea4bd65337f0 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Tue, 26 Apr 2016 13:46:13 -0700
-Subject: [PATCH 126/454] drm/panel: Add support for the Raspberry Pi 7"
- Touchscreen.
-
-This driver communicates with the Atmel microcontroller for sequencing
-the poweron of the TC358762 DSI-DPI bridge and controlling the
-backlight PWM.
-
-The following lines are required in config.txt, to keep the firmware
-from trying to bash our I2C lines and steal the DSI interrupts:
-
-    disable_touchscreen=1
-    ignore_lcd=2
-    mask_gpu_interrupt1=0x1000
-
-This means that the firmware won't power on the panel at boot time (no
-rainbow) and the touchscreen input won't work.  The native input
-driver for the touchscreen still needs to be written.
-
-v2: Set the same default orientation as the closed source firmware
-    used, which is the best for viewing angle.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/panel/Kconfig                 |   8 +
- drivers/gpu/drm/panel/Makefile                |   1 +
- .../drm/panel/panel-raspberrypi-touchscreen.c | 514 ++++++++++++++++++
- 3 files changed, 523 insertions(+)
- create mode 100644 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
-
---- a/drivers/gpu/drm/panel/Kconfig
-+++ b/drivers/gpu/drm/panel/Kconfig
-@@ -73,6 +73,14 @@ config DRM_PANEL_PANASONIC_VVX10F034N00
- 	  WUXGA (1920x1200) Novatek NT1397-based DSI panel as found in some
- 	  Xperia Z2 tablets
- 
-+config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN
-+	tristate "Raspberry Pi 7-inch touchscreen panel"
-+	depends on DRM_MIPI_DSI
-+	help
-+	  Say Y here if you want to enable support for the Raspberry
-+	  Pi 7" Touchscreen.  To compile this driver as a module,
-+	  choose M here.
-+
- config DRM_PANEL_SAMSUNG_S6E3HA2
- 	tristate "Samsung S6E3HA2 DSI video mode panel"
- 	depends on OF
---- a/drivers/gpu/drm/panel/Makefile
-+++ b/drivers/gpu/drm/panel/Makefile
-@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA)
- obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
- obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
- obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o
-+obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o
- obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
- obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
- obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o
---- /dev/null
-+++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
-@@ -0,0 +1,514 @@
-+/*
-+ * Copyright © 2016 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * Portions of this file (derived from panel-simple.c) are:
-+ *
-+ * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
-+ *
-+ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * copy of this software and associated documentation files (the "Software"),
-+ * to deal in the Software without restriction, including without limitation
-+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
-+ * and/or sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following conditions:
-+ *
-+ * The above copyright notice and this permission notice (including the
-+ * next paragraph) shall be included in all copies or substantial portions
-+ * of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-+ * DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/**
-+ * DOC: Raspberry Pi 7" touchscreen panel driver.
-+ *
-+ * The 7" touchscreen consists of a DPI LCD panel, a Toshiba
-+ * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
-+ * controlling power management, the LCD PWM, and the touchscreen.
-+ *
-+ * This driver presents this device as a MIPI DSI panel to the DRM
-+ * driver, and should expose the touchscreen as a HID device.
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/fb.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/i2c.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_graph.h>
-+#include <linux/pm.h>
-+
-+#include <drm/drm_panel.h>
-+#include <drm/drmP.h>
-+#include <drm/drm_crtc.h>
-+#include <drm/drm_mipi_dsi.h>
-+#include <drm/drm_panel.h>
-+
-+/* I2C registers of the Atmel microcontroller. */
-+enum REG_ADDR {
-+	REG_ID = 0x80,
-+	REG_PORTA, // BIT(2) for horizontal flip, BIT(3) for vertical flip
-+	REG_PORTB,
-+	REG_PORTC,
-+	REG_PORTD,
-+	REG_POWERON,
-+	REG_PWM,
-+	REG_DDRA,
-+	REG_DDRB,
-+	REG_DDRC,
-+	REG_DDRD,
-+	REG_TEST,
-+	REG_WR_ADDRL,
-+	REG_WR_ADDRH,
-+	REG_READH,
-+	REG_READL,
-+	REG_WRITEH,
-+	REG_WRITEL,
-+	REG_ID2,
-+};
-+
-+/* We only turn the PWM on or off, without varying values. */
-+#define RPI_TOUCHSCREEN_MAX_BRIGHTNESS 1
-+
-+/* DSI D-PHY Layer Registers */
-+#define D0W_DPHYCONTTX		0x0004
-+#define CLW_DPHYCONTRX		0x0020
-+#define D0W_DPHYCONTRX		0x0024
-+#define D1W_DPHYCONTRX		0x0028
-+#define COM_DPHYCONTRX		0x0038
-+#define CLW_CNTRL		0x0040
-+#define D0W_CNTRL		0x0044
-+#define D1W_CNTRL		0x0048
-+#define DFTMODE_CNTRL		0x0054
-+
-+/* DSI PPI Layer Registers */
-+#define PPI_STARTPPI		0x0104
-+#define PPI_BUSYPPI		0x0108
-+#define PPI_LINEINITCNT		0x0110
-+#define PPI_LPTXTIMECNT		0x0114
-+//#define PPI_LANEENABLE		0x0134
-+//#define PPI_TX_RX_TA		0x013C
-+#define PPI_CLS_ATMR		0x0140
-+#define PPI_D0S_ATMR		0x0144
-+#define PPI_D1S_ATMR		0x0148
-+#define PPI_D0S_CLRSIPOCOUNT	0x0164
-+#define PPI_D1S_CLRSIPOCOUNT	0x0168
-+#define CLS_PRE			0x0180
-+#define D0S_PRE			0x0184
-+#define D1S_PRE			0x0188
-+#define CLS_PREP		0x01A0
-+#define D0S_PREP		0x01A4
-+#define D1S_PREP		0x01A8
-+#define CLS_ZERO		0x01C0
-+#define D0S_ZERO		0x01C4
-+#define D1S_ZERO		0x01C8
-+#define PPI_CLRFLG		0x01E0
-+#define PPI_CLRSIPO		0x01E4
-+#define HSTIMEOUT		0x01F0
-+#define HSTIMEOUTENABLE		0x01F4
-+
-+/* DSI Protocol Layer Registers */
-+#define DSI_STARTDSI		0x0204
-+#define DSI_BUSYDSI		0x0208
-+#define DSI_LANEENABLE		0x0210
-+# define DSI_LANEENABLE_CLOCK		BIT(0)
-+# define DSI_LANEENABLE_D0		BIT(1)
-+# define DSI_LANEENABLE_D1		BIT(2)
-+
-+#define DSI_LANESTATUS0		0x0214
-+#define DSI_LANESTATUS1		0x0218
-+#define DSI_INTSTATUS		0x0220
-+#define DSI_INTMASK		0x0224
-+#define DSI_INTCLR		0x0228
-+#define DSI_LPTXTO		0x0230
-+#define DSI_MODE		0x0260
-+#define DSI_PAYLOAD0		0x0268
-+#define DSI_PAYLOAD1		0x026C
-+#define DSI_SHORTPKTDAT		0x0270
-+#define DSI_SHORTPKTREQ		0x0274
-+#define DSI_BTASTA		0x0278
-+#define DSI_BTACLR		0x027C
-+
-+/* DSI General Registers */
-+#define DSIERRCNT		0x0300
-+#define DSISIGMOD		0x0304
-+
-+/* DSI Application Layer Registers */
-+#define APLCTRL			0x0400
-+#define APLSTAT			0x0404
-+#define APLERR			0x0408
-+#define PWRMOD			0x040C
-+#define RDPKTLN			0x0410
-+#define PXLFMT			0x0414
-+#define MEMWRCMD		0x0418
-+
-+/* LCDC/DPI Host Registers */
-+#define LCDCTRL			0x0420
-+#define HSR			0x0424
-+#define HDISPR			0x0428
-+#define VSR			0x042C
-+#define VDISPR			0x0430
-+#define VFUEN			0x0434
-+
-+/* DBI-B Host Registers */
-+#define DBIBCTRL		0x0440
-+
-+/* SPI Master Registers */
-+#define SPICMR			0x0450
-+#define SPITCR			0x0454
-+
-+/* System Controller Registers */
-+#define SYSSTAT			0x0460
-+#define SYSCTRL			0x0464
-+#define SYSPLL1			0x0468
-+#define SYSPLL2			0x046C
-+#define SYSPLL3			0x0470
-+#define SYSPMCTRL		0x047C
-+
-+/* GPIO Registers */
-+#define GPIOC			0x0480
-+#define GPIOO			0x0484
-+#define GPIOI			0x0488
-+
-+/* I2C Registers */
-+#define I2CCLKCTRL		0x0490
-+
-+/* Chip/Rev Registers */
-+#define IDREG			0x04A0
-+
-+/* Debug Registers */
-+#define WCMDQUEUE		0x0500
-+#define RCMDQUEUE		0x0504
-+
-+struct rpi_touchscreen {
-+	struct drm_panel base;
-+	struct mipi_dsi_device *dsi;
-+	struct i2c_client *bridge_i2c;
-+
-+	/* Version of the firmware on the bridge chip */
-+	int atmel_ver;
-+};
-+
-+static const struct drm_display_mode rpi_touchscreen_modes[] = {
-+	{
-+		/* The DSI PLL can only integer divide from the 2Ghz
-+		 * PLLD, giving us few choices.  We pick a divide by 3
-+		 * as our DSI HS clock, giving us a pixel clock of
-+		 * that divided by 24 bits.  Pad out HFP to get our
-+		 * panel to refresh at 60Hz, even if that doesn't
-+		 * match the datasheet.
-+		 */
-+#define PIXEL_CLOCK ((2000000000 / 3) / 24)
-+#define VREFRESH    60
-+#define VTOTAL      (480 + 7 + 2 + 21)
-+#define HACT        800
-+#define HSW         2
-+#define HBP         46
-+#define HFP         ((PIXEL_CLOCK / (VTOTAL * VREFRESH)) - (HACT + HSW + HBP))
-+
-+		.clock = PIXEL_CLOCK / 1000,
-+		.hdisplay = HACT,
-+		.hsync_start = HACT + HFP,
-+		.hsync_end = HACT + HFP + HSW,
-+		.htotal = HACT + HFP + HSW + HBP,
-+		.vdisplay = 480,
-+		.vsync_start = 480 + 7,
-+		.vsync_end = 480 + 7 + 2,
-+		.vtotal = VTOTAL,
-+		.vrefresh = 60,
-+	},
-+};
-+
-+static struct rpi_touchscreen *panel_to_ts(struct drm_panel *panel)
-+{
-+	return container_of(panel, struct rpi_touchscreen, base);
-+}
-+
-+static u8 rpi_touchscreen_i2c_read(struct rpi_touchscreen *ts, u8 reg)
-+{
-+	return i2c_smbus_read_byte_data(ts->bridge_i2c, reg);
-+}
-+
-+static void rpi_touchscreen_i2c_write(struct rpi_touchscreen *ts,
-+				      u8 reg, u8 val)
-+{
-+	int ret;
-+
-+	ret = i2c_smbus_write_byte_data(ts->bridge_i2c, reg, val);
-+	if (ret)
-+		dev_err(&ts->dsi->dev, "I2C write failed: %d\n", ret);
-+}
-+
-+static int rpi_touchscreen_write(struct rpi_touchscreen *ts, u16 reg, u32 val)
-+{
-+#if 0
-+	/* The firmware uses LP DSI transactions like this to bring up
-+	 * the hardware, which should be faster than using I2C to then
-+	 * pass to the Toshiba.  However, I was unable to get it to
-+	 * work.
-+	 */
-+	u8 msg[] = {
-+		reg,
-+		reg >> 8,
-+		val,
-+		val >> 8,
-+		val >> 16,
-+		val >> 24,
-+	};
-+
-+	mipi_dsi_dcs_write_buffer(ts->dsi, msg, sizeof(msg));
-+#else
-+	rpi_touchscreen_i2c_write(ts, REG_WR_ADDRH, reg >> 8);
-+	rpi_touchscreen_i2c_write(ts, REG_WR_ADDRL, reg);
-+	rpi_touchscreen_i2c_write(ts, REG_WRITEH, val >> 8);
-+	rpi_touchscreen_i2c_write(ts, REG_WRITEL, val);
-+#endif
-+
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_disable(struct drm_panel *panel)
-+{
-+	struct rpi_touchscreen *ts = panel_to_ts(panel);
-+
-+	rpi_touchscreen_i2c_write(ts, REG_PWM, 0);
-+
-+	rpi_touchscreen_i2c_write(ts, REG_POWERON, 0);
-+	udelay(1);
-+
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_noop(struct drm_panel *panel)
-+{
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_enable(struct drm_panel *panel)
-+{
-+	struct rpi_touchscreen *ts = panel_to_ts(panel);
-+	int i;
-+
-+	rpi_touchscreen_i2c_write(ts, REG_POWERON, 1);
-+	/* Wait for nPWRDWN to go low to indicate poweron is done. */
-+	for (i = 0; i < 100; i++) {
-+		if (rpi_touchscreen_i2c_read(ts, REG_PORTB) & 1)
-+			break;
-+	}
-+
-+	rpi_touchscreen_write(ts, DSI_LANEENABLE,
-+			      DSI_LANEENABLE_CLOCK |
-+			      DSI_LANEENABLE_D0 |
-+			      (ts->dsi->lanes > 1 ? DSI_LANEENABLE_D1 : 0));
-+	rpi_touchscreen_write(ts, PPI_D0S_CLRSIPOCOUNT, 0x05);
-+	rpi_touchscreen_write(ts, PPI_D1S_CLRSIPOCOUNT, 0x05);
-+	rpi_touchscreen_write(ts, PPI_D0S_ATMR, 0x00);
-+	rpi_touchscreen_write(ts, PPI_D1S_ATMR, 0x00);
-+	rpi_touchscreen_write(ts, PPI_LPTXTIMECNT, 0x03);
-+
-+	rpi_touchscreen_write(ts, SPICMR, 0x00);
-+	rpi_touchscreen_write(ts, LCDCTRL, 0x00100150);
-+	rpi_touchscreen_write(ts, SYSCTRL, 0x040f);
-+	msleep(100);
-+
-+	rpi_touchscreen_write(ts, PPI_STARTPPI, 0x01);
-+	rpi_touchscreen_write(ts, DSI_STARTDSI, 0x01);
-+	msleep(100);
-+
-+	/* Turn on the backlight. */
-+	rpi_touchscreen_i2c_write(ts, REG_PWM, 255);
-+
-+	/* Default to the same orientation as the closed source
-+	 * firmware used for the panel.  Runtime rotation
-+	 * configuration will be supported using VC4's plane
-+	 * orientation bits.
-+	 */
-+	rpi_touchscreen_i2c_write(ts, REG_PORTA, BIT(2));
-+
-+	return 0;
-+}
-+
-+static int rpi_touchscreen_get_modes(struct drm_panel *panel)
-+{
-+	struct drm_connector *connector = panel->connector;
-+	struct drm_device *drm = panel->drm;
-+	unsigned int i, num = 0;
-+
-+	for (i = 0; i < ARRAY_SIZE(rpi_touchscreen_modes); i++) {
-+		const struct drm_display_mode *m = &rpi_touchscreen_modes[i];
-+		struct drm_display_mode *mode;
-+
-+		mode = drm_mode_duplicate(drm, m);
-+		if (!mode) {
-+			dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
-+				m->hdisplay, m->vdisplay, m->vrefresh);
-+			continue;
-+		}
-+
-+		mode->type |= DRM_MODE_TYPE_DRIVER;
-+
-+		if (i == 0)
-+			mode->type |= DRM_MODE_TYPE_PREFERRED;
-+
-+		drm_mode_set_name(mode);
-+
-+		drm_mode_probed_add(connector, mode);
-+		num++;
-+	}
-+
-+	connector->display_info.bpc = 8;
-+	connector->display_info.width_mm = 154;
-+	connector->display_info.height_mm = 86;
-+
-+	return num;
-+}
-+
-+static const struct drm_panel_funcs rpi_touchscreen_funcs = {
-+	.disable = rpi_touchscreen_disable,
-+	.unprepare = rpi_touchscreen_noop,
-+	.prepare = rpi_touchscreen_noop,
-+	.enable = rpi_touchscreen_enable,
-+	.get_modes = rpi_touchscreen_get_modes,
-+};
-+
-+static struct i2c_client *rpi_touchscreen_get_i2c(struct device *dev,
-+						  const char *name)
-+{
-+	struct device_node *node;
-+	struct i2c_client *client;
-+
-+	node = of_parse_phandle(dev->of_node, name, 0);
-+	if (!node)
-+		return ERR_PTR(-ENODEV);
-+
-+	client = of_find_i2c_device_by_node(node);
-+
-+	of_node_put(node);
-+
-+	return client;
-+}
-+
-+static int rpi_touchscreen_dsi_probe(struct mipi_dsi_device *dsi)
-+{
-+	struct device *dev = &dsi->dev;
-+	struct rpi_touchscreen *ts;
-+	int ret, ver;
-+
-+	ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL);
-+	if (!ts)
-+		return -ENOMEM;
-+
-+	dev_set_drvdata(dev, ts);
-+
-+	ts->dsi = dsi;
-+	dsi->mode_flags = (MIPI_DSI_MODE_VIDEO |
-+			   MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
-+			   MIPI_DSI_MODE_LPM);
-+	dsi->format = MIPI_DSI_FMT_RGB888;
-+	dsi->lanes = 1;
-+
-+	ts->bridge_i2c =
-+		rpi_touchscreen_get_i2c(dev, "raspberrypi,touchscreen-bridge");
-+	if (IS_ERR(ts->bridge_i2c)) {
-+		ret = -EPROBE_DEFER;
-+		return ret;
-+	}
-+
-+	ver = rpi_touchscreen_i2c_read(ts, REG_ID);
-+	if (ver < 0) {
-+		dev_err(dev, "Atmel I2C read failed: %d\n", ver);
-+		return -ENODEV;
-+	}
-+
-+	switch (ver) {
-+	case 0xde:
-+		ts->atmel_ver = 1;
-+		break;
-+	case 0xc3:
-+		ts->atmel_ver = 2;
-+		break;
-+	default:
-+		dev_err(dev, "Unknown Atmel firmware revision: 0x%02x\n", ver);
-+		return -ENODEV;
-+	}
-+
-+	/* Turn off at boot, so we can cleanly sequence powering on. */
-+	rpi_touchscreen_i2c_write(ts, REG_POWERON, 0);
-+
-+	drm_panel_init(&ts->base);
-+	ts->base.dev = dev;
-+	ts->base.funcs = &rpi_touchscreen_funcs;
-+
-+	ret = drm_panel_add(&ts->base);
-+	if (ret < 0)
-+		goto err_release_bridge;
-+
-+	return mipi_dsi_attach(dsi);
-+
-+err_release_bridge:
-+	put_device(&ts->bridge_i2c->dev);
-+	return ret;
-+}
-+
-+static int rpi_touchscreen_dsi_remove(struct mipi_dsi_device *dsi)
-+{
-+	struct device *dev = &dsi->dev;
-+	struct rpi_touchscreen *ts = dev_get_drvdata(dev);
-+	int ret;
-+
-+	ret = mipi_dsi_detach(dsi);
-+	if (ret < 0) {
-+		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
-+		return ret;
-+	}
-+
-+	drm_panel_detach(&ts->base);
-+	drm_panel_remove(&ts->base);
-+
-+	put_device(&ts->bridge_i2c->dev);
-+
-+	return 0;
-+}
-+
-+static void rpi_touchscreen_dsi_shutdown(struct mipi_dsi_device *dsi)
-+{
-+	struct device *dev = &dsi->dev;
-+	struct rpi_touchscreen *ts = dev_get_drvdata(dev);
-+
-+	rpi_touchscreen_i2c_write(ts, REG_POWERON, 0);
-+}
-+
-+static const struct of_device_id rpi_touchscreen_of_match[] = {
-+	{ .compatible = "raspberrypi,touchscreen" },
-+	{ } /* sentinel */
-+};
-+MODULE_DEVICE_TABLE(of, rpi_touchscreen_of_match);
-+
-+static struct mipi_dsi_driver rpi_touchscreen_driver = {
-+	.driver = {
-+		.name = "raspberrypi-touchscreen",
-+		.of_match_table = rpi_touchscreen_of_match,
-+	},
-+	.probe = rpi_touchscreen_dsi_probe,
-+	.remove = rpi_touchscreen_dsi_remove,
-+	.shutdown = rpi_touchscreen_dsi_shutdown,
-+};
-+module_mipi_dsi_driver(rpi_touchscreen_driver);
-+
-+MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
-+MODULE_DESCRIPTION("Raspberry Pi 7-inch touchscreen driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0127-panel-raspberrypi-touchscreen-Fix-NULL-deref-if-prob.patch b/target/linux/brcm2708/patches-4.14/950-0127-panel-raspberrypi-touchscreen-Fix-NULL-deref-if-prob.patch
deleted file mode 100644
index 37e1c63ef..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0127-panel-raspberrypi-touchscreen-Fix-NULL-deref-if-prob.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From d68d26f7f526fce52e71312501f3d07044a3c996 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 12 Apr 2017 17:52:56 -0700
-Subject: [PATCH 127/454] panel-raspberrypi-touchscreen: Fix NULL deref if
- probe order goes wrong.
-
-If the i2c driver hadn't pobed before the panel driver probes, then
-the client would be NULL but we were looking for an ERR_PTR in the
-error case.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
-+++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
-@@ -399,6 +399,9 @@ static struct i2c_client *rpi_touchscree
- 
- 	of_node_put(node);
- 
-+	if (!client)
-+		return ERR_PTR(-EPROBE_DEFER);
-+
- 	return client;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0128-panel-raspberrypi-touchscreen-Round-up-clk-rate-to-f.patch b/target/linux/brcm2708/patches-4.14/950-0128-panel-raspberrypi-touchscreen-Round-up-clk-rate-to-f.patch
deleted file mode 100644
index a61dc66bf..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0128-panel-raspberrypi-touchscreen-Round-up-clk-rate-to-f.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 7f98947db09ad419ca73082230ade1f29f18bd82 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Mon, 6 Mar 2017 12:17:16 -0800
-Subject: [PATCH 128/454] panel-raspberrypi-touchscreen: Round up clk rate to
- fix DSI panel.
-
-Commit 488f9bc8e3def93e0baef53cee2026c2cb0d8956 slightly increased the
-reported rate of PLLD, so the clk driver decided that PLLD/3/8 was now
-higher than our requested pixel clock rate and rejected it in favor of
-PLLD/4/8, which then ran the pixel clock way out of spec.
-
-By bumping the requested clock rate just slightly, we get back to
-PLLD/3/8 like we wanted and the panel displays content again.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
-+++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
-@@ -220,7 +220,12 @@ static const struct drm_display_mode rpi
- #define HBP         46
- #define HFP         ((PIXEL_CLOCK / (VTOTAL * VREFRESH)) - (HACT + HSW + HBP))
- 
--		.clock = PIXEL_CLOCK / 1000,
-+		/* Round up the pixel clock a bit (10khz), so that the
-+		 * "don't run things faster than the requested clock
-+		 * rate" rule of the clk driver doesn't reject the
-+		 * divide-by-3 mode due to rounding error.
-+		 */
-+		.clock = PIXEL_CLOCK / 1000 + 10,
- 		.hdisplay = HACT,
- 		.hsync_start = HACT + HFP,
- 		.hsync_end = HACT + HFP + HSW,
diff --git a/target/linux/brcm2708/patches-4.14/950-0129-BCM270X-Add-the-DSI-panel-to-the-defconfig.patch b/target/linux/brcm2708/patches-4.14/950-0129-BCM270X-Add-the-DSI-panel-to-the-defconfig.patch
deleted file mode 100644
index 9e48da93f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0129-BCM270X-Add-the-DSI-panel-to-the-defconfig.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 1608172019c68c5a1d567d2639843d10f19b60aa Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Thu, 2 Jun 2016 12:29:45 -0700
-Subject: [PATCH 129/454] BCM270X: Add the DSI panel to the defconfig.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- arch/arm64/configs/bcmrpi3_defconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -813,6 +813,8 @@ CONFIG_VIDEO_OV7640=m
- CONFIG_VIDEO_MT9V011=m
- CONFIG_DRM=m
- CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-+CONFIG_DRM_PANEL_SIMPLE=m
-+CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
- CONFIG_DRM_UDL=m
- CONFIG_DRM_VC4=m
- CONFIG_FB=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0130-drm-vc4-Add-support-for-setting-DPMS-in-firmwarekms.patch b/target/linux/brcm2708/patches-4.14/950-0130-drm-vc4-Add-support-for-setting-DPMS-in-firmwarekms.patch
deleted file mode 100644
index b2fede2ce..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0130-drm-vc4-Add-support-for-setting-DPMS-in-firmwarekms.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From 151e7ee8232ce765ed25ce760ed9a65c3ab71fe3 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Thu, 6 Jul 2017 11:45:48 -0700
-Subject: [PATCH 130/454] drm/vc4: Add support for setting DPMS in firmwarekms.
-
-This ensures that the screen goes blank during DPMS (screensaver),
-including the cursor.  Planes don't necessarily get disabled during
-CRTC disable, so we need to be careful to not leave them on or turn
-them back on early.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 40 ++++++++++++++++++++++++--
- 1 file changed, 37 insertions(+), 3 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -36,6 +36,8 @@ struct vc4_crtc {
- 	struct drm_crtc base;
- 	struct drm_encoder *encoder;
- 	struct drm_connector *connector;
-+	struct drm_plane *primary;
-+	struct drm_plane *cursor;
- 	void __iomem *regs;
- 
- 	struct drm_pending_vblank_event *event;
-@@ -124,8 +126,6 @@ static void vc4_primary_plane_atomic_upd
- 	u32 bpp = 32;
- 	int ret;
- 
--	vc4_plane_set_primary_blank(plane, false);
--
- 	fbinfo->xres = state->crtc_w;
- 	fbinfo->yres = state->crtc_h;
- 	fbinfo->xres_virtual = state->crtc_w;
-@@ -169,6 +169,12 @@ static void vc4_primary_plane_atomic_upd
- 				       vc4_plane->fbinfo_bus_addr);
- 	WARN_ON_ONCE(fbinfo->pitch != fb->pitches[0]);
- 	WARN_ON_ONCE(fbinfo->base != bo->paddr + fb->offsets[0]);
-+
-+	/* If the CRTC is on (or going to be on) and we're enabled,
-+	 * then unblank.  Otherwise, stay blank until CRTC enable.
-+	*/
-+	if (state->crtc->state->active)
-+		vc4_plane_set_primary_blank(plane, false);
- }
- 
- static void vc4_primary_plane_atomic_disable(struct drm_plane *plane,
-@@ -186,7 +192,12 @@ static void vc4_cursor_plane_atomic_upda
- 	struct drm_framebuffer *fb = state->fb;
- 	struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
- 	int ret;
--	u32 packet_state[] = { true, state->crtc_x, state->crtc_y, 0 };
-+	u32 packet_state[] = {
-+		state->crtc->state->active,
-+		state->crtc_x,
-+		state->crtc_y,
-+		0
-+	};
- 	u32 packet_info[] = { state->crtc_w, state->crtc_h,
- 			      0, /* unused */
- 			      bo->paddr + fb->offsets[0],
-@@ -329,10 +340,30 @@ static void vc4_crtc_mode_set_nofb(struc
- 
- static void vc4_crtc_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
- {
-+	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-+
-+	/* Always turn the planes off on CRTC disable. In DRM, planes
-+	 * are enabled/disabled through the update/disable hooks
-+	 * above, and the CRTC enable/disable independently controls
-+	 * whether anything scans out at all, but the firmware doesn't
-+	 * give us a CRTC-level control for that.
-+	 */
-+	vc4_cursor_plane_atomic_disable(vc4_crtc->cursor,
-+					vc4_crtc->cursor->state);
-+	vc4_plane_set_primary_blank(vc4_crtc->primary, true);
- }
- 
- static void vc4_crtc_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
- {
-+	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-+
-+	/* Unblank the planes (if they're supposed to be displayed). */
-+	if (vc4_crtc->primary->state->fb)
-+		vc4_plane_set_primary_blank(vc4_crtc->primary, false);
-+	if (vc4_crtc->cursor->state->fb) {
-+		vc4_cursor_plane_atomic_update(vc4_crtc->cursor,
-+					       vc4_crtc->cursor->state);
-+	}
- }
- 
- static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
-@@ -626,6 +657,9 @@ static int vc4_fkms_bind(struct device *
- 	primary_plane->crtc = crtc;
- 	cursor_plane->crtc = crtc;
- 
-+	vc4_crtc->primary = primary_plane;
-+	vc4_crtc->cursor = cursor_plane;
-+
- 	vc4_encoder = devm_kzalloc(dev, sizeof(*vc4_encoder), GFP_KERNEL);
- 	if (!vc4_encoder)
- 		return -ENOMEM;
diff --git a/target/linux/brcm2708/patches-4.14/950-0131-drm-vc4-Fix-pitch-setup-for-T-format-scanout.patch b/target/linux/brcm2708/patches-4.14/950-0131-drm-vc4-Fix-pitch-setup-for-T-format-scanout.patch
deleted file mode 100644
index 4aa018f54..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0131-drm-vc4-Fix-pitch-setup-for-T-format-scanout.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 82f8b13481afeb2400bce276cf88a757fac87a21 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Fri, 14 Jul 2017 17:33:08 -0700
-Subject: [PATCH 131/454] drm/vc4: Fix pitch setup for T-format scanout.
-
-The documentation said to use src_w here, and I didn't consider that
-we actually needed to be using pitch somewhere in our setup.  Fixes
-scanout on my DSI panel when X11 does initial setup with 1920x1080
-HDMI and 800x480 DSI both at 0,0 of the same framebuffer.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Fixes: 98830d91da08 ("drm/vc4: Add T-format scanout support.")
----
- drivers/gpu/drm/vc4/vc4_plane.c | 20 +++++++++++++++-----
- 1 file changed, 15 insertions(+), 5 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -546,14 +546,24 @@ static int vc4_plane_mode_set(struct drm
- 		tiling = SCALER_CTL0_TILING_LINEAR;
- 		pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
- 		break;
--	case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
-+
-+	case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
-+		/* For T-tiled, the FB pitch is "how many bytes from
-+		 * one row to the next, such that pitch * tile_h ==
-+		 * tile_size * tiles_per_row."
-+		 */
-+		u32 tile_size_shift = 12;
-+		u32 tile_h_shift = 5;
-+		u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
-+
- 		tiling = SCALER_CTL0_TILING_256B_OR_T;
- 
--		pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET),
--			  VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L),
--			  VC4_SET_FIELD((vc4_state->src_w[0] + 31) >> 5,
--					SCALER_PITCH0_TILE_WIDTH_R));
-+		pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
-+			  VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
-+			  VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
- 		break;
-+	}
-+
- 	default:
- 		DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
- 			      (long long)fb->modifier);
diff --git a/target/linux/brcm2708/patches-4.14/950-0132-mcp2515-Use-DT-supplied-interrupt-flags.patch b/target/linux/brcm2708/patches-4.14/950-0132-mcp2515-Use-DT-supplied-interrupt-flags.patch
deleted file mode 100644
index 31942750c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0132-mcp2515-Use-DT-supplied-interrupt-flags.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 623c500d1571b7169ad683ad94fe8835023395a5 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 14 Nov 2017 11:03:22 +0000
-Subject: [PATCH 132/454] mcp2515: Use DT-supplied interrupt flags
-
-The MCP2515 datasheet clearly describes a level-triggered interrupt
-pin. Therefore the receiving interrupt controller must also be
-configured for level-triggered operation otherwise there is a danger
-of a missed interrupt condition blocking all subsequent interrupts.
-The ONESHOT flag ensures that the interrupt is masked until the
-threaded interrupt handler exits.
-
-Rather than change the flags globally (they must have worked for at
-least one user), allow the flags to be overridden from Device Tree
-in the event that the device has a DT node.
-
-See: https://github.com/raspberrypi/linux/issues/2175
-     https://github.com/raspberrypi/linux/issues/2263
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/net/can/spi/mcp251x.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/net/can/spi/mcp251x.c
-+++ b/drivers/net/can/spi/mcp251x.c
-@@ -952,6 +952,9 @@ static int mcp251x_open(struct net_devic
- 	priv->tx_skb = NULL;
- 	priv->tx_len = 0;
- 
-+	if (spi->dev.of_node)
-+	    flags = 0;
-+
- 	ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
- 				   flags | IRQF_ONESHOT, DEVICE_NAME, priv);
- 	if (ret) {
diff --git a/target/linux/brcm2708/patches-4.14/950-0133-Tidy-up-of-the-ft5406-driver-to-use-DT-2189.patch b/target/linux/brcm2708/patches-4.14/950-0133-Tidy-up-of-the-ft5406-driver-to-use-DT-2189.patch
deleted file mode 100644
index 18e8dd5ad..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0133-Tidy-up-of-the-ft5406-driver-to-use-DT-2189.patch
+++ /dev/null
@@ -1,382 +0,0 @@
-From f87b44ad810fbb74b50df0df051b468bd30f4900 Mon Sep 17 00:00:00 2001
-From: James Hughes <JamesH65@users.noreply.github.com>
-Date: Thu, 16 Nov 2017 15:56:17 +0000
-Subject: [PATCH 133/454] Tidy up of the ft5406 driver to use DT (#2189)
-
-Driver was using a fixed resolution, this commit
-adds touchscreen size, and coordinate flip and swap
-features via device tree overlays.
-
-Adds overrides so the VC4 can adjust the DT parameters
-appropriately; there is a newer version of the VC4 side
-driver that can now set up the appropriate DT values
-if required.
-
-Signed-off-by: James Hughes <james.hughes@raspberrypi.org>
----
- drivers/input/touchscreen/rpi-ft5406.c | 218 ++++++++++++++++---------
- 1 file changed, 145 insertions(+), 73 deletions(-)
-
---- a/drivers/input/touchscreen/rpi-ft5406.c
-+++ b/drivers/input/touchscreen/rpi-ft5406.c
-@@ -1,7 +1,7 @@
- /*
-  * Driver for memory based ft5406 touchscreen
-  *
-- * Copyright (C) 2015 Raspberry Pi
-+ * Copyright (C) 2015, 2017 Raspberry Pi
-  *
-  *
-  * This program is free software; you can redistribute it and/or modify
-@@ -9,7 +9,6 @@
-  * published by the Free Software Foundation.
-  */
- 
--
- #include <linux/module.h>
- #include <linux/interrupt.h>
- #include <linux/input.h>
-@@ -21,11 +20,15 @@
- #include <linux/kthread.h>
- #include <linux/platform_device.h>
- #include <linux/stddef.h>
--#include <asm/io.h>
-+#include <linux/io.h>
- #include <linux/dma-mapping.h>
- #include <soc/bcm2835/raspberrypi-firmware.h>
- 
- #define MAXIMUM_SUPPORTED_POINTS 10
-+#define FTS_TOUCH_DOWN      0
-+#define FTS_TOUCH_UP        1
-+#define FTS_TOUCH_CONTACT   2
-+
- struct ft5406_regs {
- 	uint8_t device_mode;
- 	uint8_t gesture_id;
-@@ -35,85 +38,125 @@ struct ft5406_regs {
- 		uint8_t xl;
- 		uint8_t yh;
- 		uint8_t yl;
--		uint8_t res1;
--		uint8_t res2;
-+		uint8_t pressure; /* Not supported */
-+		uint8_t area;     /* Not supported */
- 	} point[MAXIMUM_SUPPORTED_POINTS];
- };
- 
--#define SCREEN_WIDTH  800
--#define SCREEN_HEIGHT 480
-+/* These are defaults if the DT entries are missing */
-+#define DEFAULT_SCREEN_WIDTH  800
-+#define DEFAULT_SCREEN_HEIGHT 480
- 
- struct ft5406 {
--	struct platform_device * pdev;
--	struct input_dev       * input_dev;
--	void __iomem           * ts_base;
--	dma_addr_t		 bus_addr;
--	struct task_struct     * thread;
-+	struct platform_device	*pdev;
-+	struct input_dev	*input_dev;
-+	void __iomem		*ts_base;
-+	dma_addr_t		bus_addr;
-+	struct task_struct	*thread;
-+
-+	uint16_t	max_x;
-+	uint16_t	max_y;
-+	uint8_t		hflip;
-+	uint8_t		vflip;
-+	uint8_t		xyswap;
- };
- 
- /* Thread to poll for touchscreen events
-- * 
-+ *
-  * This thread polls the memory based register copy of the ft5406 registers
-  * using the number of points register to know whether the copy has been
-- * updated (we write 99 to the memory copy, the GPU will write between 
-+ * updated (we write 99 to the memory copy, the GPU will write between
-  * 0 - 10 points)
-  */
-+#define ID_TO_BIT(a) (1 << a)
-+
- static int ft5406_thread(void *arg)
- {
- 	struct ft5406 *ts = (struct ft5406 *) arg;
- 	struct ft5406_regs regs;
- 	int known_ids = 0;
--	
--	while(!kthread_should_stop())
--	{
--		// 60fps polling
-+
-+	while (!kthread_should_stop()) {
-+		/* 60fps polling */
- 		msleep_interruptible(17);
- 		memcpy_fromio(&regs, ts->ts_base, sizeof(struct ft5406_regs));
--		iowrite8(99, ts->ts_base + offsetof(struct ft5406_regs, num_points));
--		// Do not output if theres no new information (num_points is 99)
--		// or we have no touch points and don't need to release any
--		if(!(regs.num_points == 99 || (regs.num_points == 0 && known_ids == 0)))
--		{
-+		iowrite8(99,
-+			 ts->ts_base +
-+			 offsetof(struct ft5406_regs, num_points));
-+
-+		/*
-+		 * Do not output if theres no new information (num_points is 99)
-+		 * or we have no touch points and don't need to release any
-+		 */
-+		if (!(regs.num_points == 99 ||
-+		    (regs.num_points == 0 && known_ids == 0))) {
- 			int i;
- 			int modified_ids = 0, released_ids;
--			for(i = 0; i < regs.num_points; i++)
--			{
--				int x = (((int) regs.point[i].xh & 0xf) << 8) + regs.point[i].xl;
--				int y = (((int) regs.point[i].yh & 0xf) << 8) + regs.point[i].yl;
--				int touchid = (regs.point[i].yh >> 4) & 0xf;
--				
--				modified_ids |= 1 << touchid;
- 
--				if(!((1 << touchid) & known_ids))
--					dev_dbg(&ts->pdev->dev, "x = %d, y = %d, touchid = %d\n", x, y, touchid);
--				
--				input_mt_slot(ts->input_dev, touchid);
--				input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 1);
-+			for (i = 0; i < regs.num_points; i++) {
-+				int x = (((int) regs.point[i].xh & 0xf) << 8) +
-+					regs.point[i].xl;
-+				int y = (((int) regs.point[i].yh & 0xf) << 8) +
-+					regs.point[i].yl;
-+				int touchid = (regs.point[i].yh >> 4) & 0xf;
-+				int event_type = (regs.point[i].xh >> 6) & 0x03;
- 
--				input_report_abs(ts->input_dev, ABS_MT_POSITION_X, x);
--				input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, y);
-+				modified_ids |= ID_TO_BIT(touchid);
- 
-+				if (event_type == FTS_TOUCH_DOWN ||
-+				    event_type == FTS_TOUCH_CONTACT) {
-+					if (ts->hflip)
-+						x = ts->max_x - 1 - x;
-+
-+					if (ts->vflip)
-+						y = ts->max_y - 1 - y;
-+
-+					if (ts->xyswap)
-+						swap(x, y);
-+
-+					if (!((ID_TO_BIT(touchid)) & known_ids))
-+						dev_dbg(&ts->pdev->dev,
-+							"x = %d, y = %d, press = %d, touchid = %d\n",
-+							x, y,
-+							regs.point[i].pressure,
-+							touchid);
-+
-+					input_mt_slot(ts->input_dev, touchid);
-+					input_mt_report_slot_state(
-+							ts->input_dev,
-+							MT_TOOL_FINGER,
-+							1);
-+
-+					input_report_abs(ts->input_dev,
-+							 ABS_MT_POSITION_X, x);
-+					input_report_abs(ts->input_dev,
-+							 ABS_MT_POSITION_Y, y);
-+				}
- 			}
- 
- 			released_ids = known_ids & ~modified_ids;
--			for(i = 0; released_ids && i < MAXIMUM_SUPPORTED_POINTS; i++)
--			{
--				if(released_ids & (1<<i))
--				{
--					dev_dbg(&ts->pdev->dev, "Released %d, known = %x modified = %x\n", i, known_ids, modified_ids);
-+			for (i = 0;
-+			     released_ids && i < MAXIMUM_SUPPORTED_POINTS;
-+			     i++) {
-+				if (released_ids & (1<<i)) {
-+					dev_dbg(&ts->pdev->dev,
-+						"Released %d, known = %x, modified = %x\n",
-+						i, known_ids, modified_ids);
- 					input_mt_slot(ts->input_dev, i);
--					input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 0);
--					modified_ids &= ~(1 << i);
-+					input_mt_report_slot_state(
-+							ts->input_dev,
-+							MT_TOOL_FINGER,
-+							0);
-+					modified_ids &= ~(ID_TO_BIT(i));
- 				}
- 			}
- 			known_ids = modified_ids;
--			
-+
- 			input_mt_report_pointer_emulation(ts->input_dev, true);
- 			input_sync(ts->input_dev);
- 		}
--			
- 	}
--	
-+
- 	return 0;
- }
- 
-@@ -122,13 +165,14 @@ static int ft5406_probe(struct platform_
- 	int err = 0;
- 	struct device *dev = &pdev->dev;
- 	struct device_node *np = dev->of_node;
--	struct ft5406 * ts;
-+	struct ft5406 *ts;
- 	struct device_node *fw_node;
- 	struct rpi_firmware *fw;
- 	u32 touchbuf;
--	
-+	u32 val;
-+
- 	dev_info(dev, "Probing device\n");
--	
-+
- 	fw_node = of_parse_phandle(np, "firmware", 0);
- 	if (!fw_node) {
- 		dev_err(dev, "Missing firmware node\n");
-@@ -151,7 +195,8 @@ static int ft5406_probe(struct platform_
- 		return -ENOMEM;
- 	}
- 
--	ts->ts_base = dma_zalloc_coherent(dev, PAGE_SIZE, &ts->bus_addr, GFP_KERNEL);
-+	ts->ts_base = dma_zalloc_coherent(dev, PAGE_SIZE, &ts->bus_addr,
-+					  GFP_KERNEL);
- 	if (!ts->ts_base) {
- 		pr_err("[%s]: failed to dma_alloc_coherent(%ld)\n",
- 				__func__, PAGE_SIZE);
-@@ -164,17 +209,22 @@ static int ft5406_probe(struct platform_
- 				    &touchbuf, sizeof(touchbuf));
- 
- 	if (err || touchbuf != 0) {
--		dev_warn(dev, "Failed to set touchbuf, trying to get err:%x\n", err);
-+		dev_warn(dev, "Failed to set touchbuf, trying to get err:%x\n",
-+			 err);
- 		dma_free_coherent(dev, PAGE_SIZE, ts->ts_base, ts->bus_addr);
- 		ts->ts_base = 0;
- 		ts->bus_addr = 0;
- 	}
- 
- 	if (!ts->ts_base) {
--		dev_warn(dev, "set failed, trying get (err:%d touchbuf:%x virt:%p bus:%x)\n", err, touchbuf, ts->ts_base, ts->bus_addr);
--
--		err = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF,
--				    &touchbuf, sizeof(touchbuf));
-+		dev_warn(dev,
-+		"set failed, trying get (err:%d touchbuf:%x virt:%p bus:%x)\n",
-+		err, touchbuf, ts->ts_base, ts->bus_addr);
-+
-+		err = rpi_firmware_property(
-+				fw,
-+				RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF,
-+				&touchbuf, sizeof(touchbuf));
- 		if (err) {
- 			dev_err(dev, "Failed to get touch buffer\n");
- 			goto out;
-@@ -188,11 +238,10 @@ static int ft5406_probe(struct platform_
- 
- 		dev_dbg(dev, "Got TS buffer 0x%x\n", touchbuf);
- 
--		// mmap the physical memory
-+		/* mmap the physical memory */
- 		touchbuf &= ~0xc0000000;
- 		ts->ts_base = ioremap(touchbuf, sizeof(struct ft5406_regs));
--		if (ts->ts_base == NULL)
--		{
-+		if (ts->ts_base == NULL) {
- 			dev_err(dev, "Failed to map physical address\n");
- 			err = -ENOMEM;
- 			goto out;
-@@ -200,22 +249,46 @@ static int ft5406_probe(struct platform_
- 	}
- 	platform_set_drvdata(pdev, ts);
- 	ts->pdev = pdev;
--	
-+
- 	ts->input_dev->name = "FT5406 memory based driver";
--	
-+
-+	if (of_property_read_u32(np, "touchscreen-size-x", &val) >= 0)
-+		ts->max_x = val;
-+	else
-+		ts->max_x = DEFAULT_SCREEN_WIDTH;
-+
-+	if (of_property_read_u32(np, "touchscreen-size-y", &val) >= 0)
-+		ts->max_y = val;
-+	else
-+		ts->max_y = DEFAULT_SCREEN_HEIGHT;
-+
-+	if (of_property_read_u32(np, "touchscreen-inverted-x", &val) >= 0)
-+		ts->hflip = val;
-+
-+	if (of_property_read_u32(np, "touchscreen-inverted-y", &val) >= 0)
-+		ts->vflip = val;
-+
-+	if (of_property_read_u32(np, "touchscreen-swapped-x-y", &val) >= 0)
-+		ts->xyswap = val;
-+
-+	dev_dbg(dev,
-+		"Touchscreen parameters (%d,%d), hflip=%d, vflip=%d, xyswap=%d",
-+		ts->max_x, ts->max_y, ts->hflip, ts->vflip, ts->xyswap);
-+
- 	__set_bit(EV_KEY, ts->input_dev->evbit);
- 	__set_bit(EV_SYN, ts->input_dev->evbit);
- 	__set_bit(EV_ABS, ts->input_dev->evbit);
- 
- 	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_X, 0,
--			     SCREEN_WIDTH, 0, 0);
-+			     ts->xyswap ? ts->max_y : ts->max_x, 0, 0);
- 	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_Y, 0,
--			     SCREEN_HEIGHT, 0, 0);
-+			     ts->xyswap ? ts->max_x : ts->max_y, 0, 0);
- 
--	input_mt_init_slots(ts->input_dev, MAXIMUM_SUPPORTED_POINTS, INPUT_MT_DIRECT);
-+	input_mt_init_slots(ts->input_dev,
-+			    MAXIMUM_SUPPORTED_POINTS, INPUT_MT_DIRECT);
- 
- 	input_set_drvdata(ts->input_dev, ts);
--	
-+
- 	err = input_register_device(ts->input_dev);
- 	if (err) {
- 		dev_err(dev, "could not register input device, %d\n",
-@@ -223,10 +296,9 @@ static int ft5406_probe(struct platform_
- 		goto out;
- 	}
- 
--	// create thread to poll the touch events
-+	/* create thread that polls the touch events */
- 	ts->thread = kthread_run(ft5406_thread, ts, "ft5406");
--	if(ts->thread == NULL)
--	{
-+	if (ts->thread == NULL) {
- 		dev_err(dev, "Failed to create kernel thread");
- 		err = -ENOMEM;
- 		goto out;
-@@ -254,9 +326,9 @@ static int ft5406_remove(struct platform
- {
- 	struct device *dev = &pdev->dev;
- 	struct ft5406 *ts = (struct ft5406 *) platform_get_drvdata(pdev);
--	
-+
- 	dev_info(dev, "Removing rpi-ft5406\n");
--	
-+
- 	kthread_stop(ts->thread);
- 
- 	if (ts->bus_addr)
-@@ -265,7 +337,7 @@ static int ft5406_remove(struct platform
- 		iounmap(ts->ts_base);
- 	if (ts->input_dev)
- 		input_unregister_device(ts->input_dev);
--	
-+
- 	return 0;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0134-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch b/target/linux/brcm2708/patches-4.14/950-0134-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch
deleted file mode 100644
index 82c499ed6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0134-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From 2a22836f441f494bb193d98ebbcca163c8756a41 Mon Sep 17 00:00:00 2001
-From: notro <notro@tronnes.org>
-Date: Thu, 10 Jul 2014 13:59:47 +0200
-Subject: [PATCH 134/454] pinctrl-bcm2835: Set base to 0 give expected gpio
- numbering
-
-Signed-off-by: Noralf Tronnes <notro@tronnes.org>
----
- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
-+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
-@@ -362,7 +362,7 @@ static const struct gpio_chip bcm2835_gp
- 	.get_direction = bcm2835_gpio_get_direction,
- 	.get = bcm2835_gpio_get,
- 	.set = bcm2835_gpio_set,
--	.base = -1,
-+	.base = 0,
- 	.ngpio = BCM2835_NUM_GPIOS,
- 	.can_sleep = false,
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0135-fiq_fsm-rewind-DMA-pointer-for-OUT-transactions-that.patch b/target/linux/brcm2708/patches-4.14/950-0135-fiq_fsm-rewind-DMA-pointer-for-OUT-transactions-that.patch
deleted file mode 100644
index 65a33f98a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0135-fiq_fsm-rewind-DMA-pointer-for-OUT-transactions-that.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 3d0898f22d62dd7a05c39de9ea7e200689dc6c20 Mon Sep 17 00:00:00 2001
-From: P33M <P33M@users.noreply.github.com>
-Date: Fri, 24 Nov 2017 13:49:26 +0000
-Subject: [PATCH 135/454] fiq_fsm: rewind DMA pointer for OUT transactions that
- fail (#2288)
-
-See: https://github.com/raspberrypi/linux/issues/2140
----
- drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-@@ -267,6 +267,15 @@ static void notrace fiq_fsm_reload_hctsi
- }
- 
- /**
-+ * fiq_fsm_reload_hcdma() - for OUT transactions, rewind DMA pointer
-+ */
-+static void notrace fiq_fsm_reload_hcdma(struct fiq_state *st, int n)
-+{
-+	hcdma_data_t hcdma = st->channel[n].hcdma_copy;
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
-+}
-+
-+/**
-  * fiq_iso_out_advance() - update DMA address and split position bits
-  * for isochronous OUT transactions.
-  *
-@@ -827,11 +836,14 @@ static int notrace noinline fiq_fsm_do_h
- 			fiq_fsm_setup_csplit(state, n);
- 		} else if (hcint.b.nak) {
- 			// No buffer space in TT. Retry on a uframe boundary.
-+			fiq_fsm_reload_hcdma(state, n);
- 			st->fsm = FIQ_NP_SSPLIT_RETRY;
- 			handled = 1;
- 		} else if (hcint.b.xacterr) {
- 			// The only other one we care about is xacterr. This implies HS bus error - retry.
- 			st->nr_errors++;
-+			if(st->hcchar_copy.b.epdir == 0)
-+				fiq_fsm_reload_hcdma(state, n);
- 			st->fsm = FIQ_NP_SSPLIT_RETRY;
- 			if (st->nr_errors >= 3) {
- 				st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
diff --git a/target/linux/brcm2708/patches-4.14/950-0136-cgroup-Disable-cgroup-memory-by-default.patch b/target/linux/brcm2708/patches-4.14/950-0136-cgroup-Disable-cgroup-memory-by-default.patch
deleted file mode 100644
index 9fb4b8180..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0136-cgroup-Disable-cgroup-memory-by-default.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 584bc4a6093ceb9aea07673185ee0084edc8690b Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 27 Nov 2017 17:14:54 +0000
-Subject: [PATCH 136/454] cgroup: Disable cgroup "memory" by default
-
-Some Raspberry Pis have limited RAM and most users won't use the
-cgroup memory support so it is disabled by default. Enable with:
-
-    cgroup_enable=memory
-
-See: https://github.com/raspberrypi/linux/issues/1950
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- kernel/cgroup/cgroup.c | 30 ++++++++++++++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
---- a/kernel/cgroup/cgroup.c
-+++ b/kernel/cgroup/cgroup.c
-@@ -5154,6 +5154,8 @@ int __init cgroup_init_early(void)
- }
- 
- static u16 cgroup_disable_mask __initdata;
-+static u16 cgroup_enable_mask __initdata;
-+static int __init cgroup_disable(char *str);
- 
- /**
-  * cgroup_init - cgroup initialization
-@@ -5192,6 +5194,12 @@ int __init cgroup_init(void)
- 
- 	mutex_unlock(&cgroup_mutex);
- 
-+	/* Apply an implicit disable... */
-+	cgroup_disable("memory");
-+
-+	/* ...knowing that an explicit enable will override it. */
-+	cgroup_disable_mask &= ~cgroup_enable_mask;
-+
- 	for_each_subsys(ss, ssid) {
- 		if (ss->early_init) {
- 			struct cgroup_subsys_state *css =
-@@ -5572,6 +5580,28 @@ static int __init cgroup_disable(char *s
- }
- __setup("cgroup_disable=", cgroup_disable);
- 
-+static int __init cgroup_enable(char *str)
-+{
-+	struct cgroup_subsys *ss;
-+	char *token;
-+	int i;
-+
-+	while ((token = strsep(&str, ",")) != NULL) {
-+		if (!*token)
-+			continue;
-+
-+		for_each_subsys(ss, i) {
-+			if (strcmp(token, ss->name) &&
-+			    strcmp(token, ss->legacy_name))
-+				continue;
-+
-+			cgroup_enable_mask |= 1 << i;
-+		}
-+	}
-+	return 1;
-+}
-+__setup("cgroup_enable=", cgroup_enable);
-+
- /**
-  * css_tryget_online_from_dir - get corresponding css from a cgroup dentry
-  * @dentry: directory dentry of interest
diff --git a/target/linux/brcm2708/patches-4.14/950-0137-pwm-Set-class-for-exported-channels-in-sysfs.patch b/target/linux/brcm2708/patches-4.14/950-0137-pwm-Set-class-for-exported-channels-in-sysfs.patch
deleted file mode 100644
index b204e8e0f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0137-pwm-Set-class-for-exported-channels-in-sysfs.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From dd5e8c9945f3f9a9bd9b307087c2881d8399c87b Mon Sep 17 00:00:00 2001
-From: Gottfried Haider <gottfried.haider@gmail.com>
-Date: Tue, 26 Sep 2017 11:59:51 +0000
-Subject: [PATCH 137/454] pwm: Set class for exported channels in sysfs
-
-[ Upstream commit 7e5d1fd75c3dde9fc10c4472b9368089d1b81d00 ]
-
-Notifications for devices without bus or class set get dropped by
-dev_uevent_filter(). Adding the class to the exported child matches
-what the GPIO subsystem is doing.
-
-With this change exporting a channel triggers a udev event, which
-gives userspace a chance to fixup permissions and makes it possible
-for non-root users to make use of the PWM subsystem.
-
-Signed-off-by: Gottfried Haider <gottfried.haider@gmail.com>
-CC: Thierry Reding <thierry.reding@gmail.com>
-CC: H Hartley Sweeten <hsweeten@visionengravers.com>
-CC: linux-pwm@vger.kernel.org
-CC: linux-arm-kernel@lists.infradead.org
-CC: linux-rpi-kernel@lists.infradead.org
-Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
----
- drivers/pwm/sysfs.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/pwm/sysfs.c
-+++ b/drivers/pwm/sysfs.c
-@@ -263,6 +263,7 @@ static int pwm_export_child(struct devic
- 	export->pwm = pwm;
- 	mutex_init(&export->lock);
- 
-+	export->child.class = parent->class;
- 	export->child.release = pwm_export_release;
- 	export->child.parent = parent;
- 	export->child.devt = MKDEV(0, 0);
diff --git a/target/linux/brcm2708/patches-4.14/950-0138-Updates-for-Pisound-module-code.patch b/target/linux/brcm2708/patches-4.14/950-0138-Updates-for-Pisound-module-code.patch
deleted file mode 100644
index af501d56f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0138-Updates-for-Pisound-module-code.patch
+++ /dev/null
@@ -1,422 +0,0 @@
-From 5f3557a2e88b324e026d44f8fb7eb3ea37bba16b Mon Sep 17 00:00:00 2001
-From: Giedrius Trainavicius <giedrius@blokas.io>
-Date: Tue, 25 Oct 2016 01:47:20 +0300
-Subject: [PATCH 138/454] Updates for Pisound module code:
-
-	* Merged 'Fix a warning in DEBUG builds' (1c8b82b).
-	* Updating some strings and copyright information.
-	* Fix for handling high load of MIDI input and output.
-	* Use dual rate oversampling ratio for 96kHz instead of single
-	  rate one.
-
-Signed-off-by: Giedrius Trainavicius <giedrius@blokas.io>
----
- .../arm/boot/dts/overlays/pisound-overlay.dts |   4 +-
- sound/soc/bcm/pisound.c                       | 209 ++++++++++++------
- 2 files changed, 146 insertions(+), 67 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/pisound-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/pisound-overlay.dts
-@@ -1,6 +1,6 @@
- /*
-- * pisound Linux kernel module.
-- * Copyright (C) 2016  Vilniaus Blokas UAB, http://blokas.io/pisound
-+ * Pisound Linux kernel module.
-+ * Copyright (C) 2016-2017  Vilniaus Blokas UAB, https://blokas.io/pisound
-  *
-  * This program is free software; you can redistribute it and/or
-  * modify it under the terms of the GNU General Public License
---- a/sound/soc/bcm/pisound.c
-+++ b/sound/soc/bcm/pisound.c
-@@ -1,6 +1,6 @@
- /*
-- * pisound Linux kernel module.
-- * Copyright (C) 2016  Vilniaus Blokas UAB, http://blokas.io/pisound
-+ * Pisound Linux kernel module.
-+ * Copyright (C) 2016-2017  Vilniaus Blokas UAB, https://blokas.io/pisound
-  *
-  * This program is free software; you can redistribute it and/or
-  * modify it under the terms of the GNU General Public License
-@@ -28,6 +28,7 @@
- #include <linux/spi/spi.h>
- #include <linux/interrupt.h>
- #include <linux/kfifo.h>
-+#include <linux/jiffies.h>
- 
- #include <sound/core.h>
- #include <sound/pcm.h>
-@@ -41,7 +42,8 @@
- static int pisnd_spi_init(struct device *dev);
- static void pisnd_spi_uninit(void);
- 
--static void pisnd_spi_send(uint8_t val);
-+static void pisnd_spi_flush(void);
-+static void pisnd_spi_start(void);
- static uint8_t pisnd_spi_recv(uint8_t *buffer, uint8_t length);
- 
- typedef void (*pisnd_spi_recv_cb)(void *data);
-@@ -56,7 +58,7 @@ static void pisnd_midi_uninit(void);
- 
- #define PISOUND_LOG_PREFIX "pisound: "
- 
--#ifdef DEBUG
-+#ifdef PISOUND_DEBUG
- #	define printd(...) pr_alert(PISOUND_LOG_PREFIX __VA_ARGS__)
- #else
- #	define printd(...) do {} while (0)
-@@ -65,13 +67,18 @@ static void pisnd_midi_uninit(void);
- #define printe(...) pr_err(PISOUND_LOG_PREFIX __VA_ARGS__)
- #define printi(...) pr_info(PISOUND_LOG_PREFIX __VA_ARGS__)
- 
-+static struct snd_rawmidi *g_rmidi;
-+static struct snd_rawmidi_substream *g_midi_output_substream;
-+
- static int pisnd_output_open(struct snd_rawmidi_substream *substream)
- {
-+	g_midi_output_substream = substream;
- 	return 0;
- }
- 
- static int pisnd_output_close(struct snd_rawmidi_substream *substream)
- {
-+	g_midi_output_substream = NULL;
- 	return 0;
- }
- 
-@@ -80,26 +87,20 @@ static void pisnd_output_trigger(
- 	int up
- 	)
- {
--	uint8_t data;
-+	if (substream != g_midi_output_substream) {
-+		printe("MIDI output trigger called for an unexpected stream!");
-+		return;
-+	}
- 
- 	if (!up)
- 		return;
- 
--	while (snd_rawmidi_transmit_peek(substream, &data, 1)) {
--		pisnd_spi_send(data);
--		snd_rawmidi_transmit_ack(substream, 1);
--	}
-+	pisnd_spi_start();
- }
- 
- static void pisnd_output_drain(struct snd_rawmidi_substream *substream)
- {
--	uint8_t data;
--
--	while (snd_rawmidi_transmit_peek(substream, &data, 1)) {
--		pisnd_spi_send(data);
--
--		snd_rawmidi_transmit_ack(substream, 1);
--	}
-+	pisnd_spi_flush();
- }
- 
- static int pisnd_input_open(struct snd_rawmidi_substream *substream)
-@@ -120,7 +121,7 @@ static void pisnd_midi_recv_callback(voi
- 	while ((n = pisnd_spi_recv(data, sizeof(data)))) {
- 		int res = snd_rawmidi_receive(substream, data, n);
- 		(void)res;
--		printd("midi recv 0x%02x, res = %d\n", data, res);
-+		printd("midi recv %u bytes, res = %d\n", n, res);
- 	}
- }
- 
-@@ -134,8 +135,6 @@ static void pisnd_input_trigger(struct s
- 	}
- }
- 
--static struct snd_rawmidi *g_rmidi;
--
- static struct snd_rawmidi_ops pisnd_output_ops = {
- 	.open = pisnd_output_open,
- 	.close = pisnd_output_close,
-@@ -168,7 +167,11 @@ static struct snd_rawmidi_global_ops pis
- 
- static int pisnd_midi_init(struct snd_card *card)
- {
--	int err = snd_rawmidi_new(card, "pisound MIDI", 0, 1, 1, &g_rmidi);
-+	int err;
-+
-+	g_midi_output_substream = NULL;
-+
-+	err = snd_rawmidi_new(card, "pisound MIDI", 0, 1, 1, &g_rmidi);
- 
- 	if (err < 0) {
- 		printe("snd_rawmidi_new failed: %d\n", err);
-@@ -209,7 +212,7 @@ static void pisnd_midi_uninit(void)
- static void *g_recvData;
- static pisnd_spi_recv_cb g_recvCallback;
- 
--#define FIFO_SIZE 512
-+#define FIFO_SIZE 4096
- 
- static char g_serial_num[11];
- static char g_id[25];
-@@ -231,6 +234,7 @@ static struct work_struct pisnd_work_pro
- 
- static void pisnd_work_handler(struct work_struct *work);
- 
-+static void spi_transfer(const uint8_t *txbuf, uint8_t *rxbuf, int len);
- static uint16_t spi_transfer16(uint16_t val);
- 
- static int pisnd_init_workqueues(void)
-@@ -285,9 +289,6 @@ static unsigned long spilockflags;
- 
- static uint16_t spi_transfer16(uint16_t val)
- {
--	int err;
--	struct spi_transfer transfer;
--	struct spi_message msg;
- 	uint8_t txbuf[2];
- 	uint8_t rxbuf[2];
- 
-@@ -296,19 +297,38 @@ static uint16_t spi_transfer16(uint16_t
- 		return 0;
- 	}
- 
-+	txbuf[0] = val >> 8;
-+	txbuf[1] = val & 0xff;
-+
-+	spi_transfer(txbuf, rxbuf, sizeof(txbuf));
-+
-+	printd("received: %02x%02x\n", rxbuf[0], rxbuf[1]);
-+
-+	return (rxbuf[0] << 8) | rxbuf[1];
-+}
-+
-+static void spi_transfer(const uint8_t *txbuf, uint8_t *rxbuf, int len)
-+{
-+	int err;
-+	struct spi_transfer transfer;
-+	struct spi_message msg;
-+
-+	memset(rxbuf, 0, sizeof(txbuf));
-+
-+	if (!pisnd_spi_device) {
-+		printe("pisnd_spi_device null, returning\n");
-+		return;
-+	}
-+
- 	spi_message_init(&msg);
- 
- 	memset(&transfer, 0, sizeof(transfer));
--	memset(&rxbuf, 0, sizeof(rxbuf));
- 
--	txbuf[0] = val >> 8;
--	txbuf[1] = val & 0xff;
--
--	transfer.tx_buf = &txbuf;
--	transfer.rx_buf = &rxbuf;
--	transfer.len = sizeof(txbuf);
--	transfer.speed_hz = 125000;
--	transfer.delay_usecs = 100;
-+	transfer.tx_buf = txbuf;
-+	transfer.rx_buf = rxbuf;
-+	transfer.len = len;
-+	transfer.speed_hz = 100000;
-+	transfer.delay_usecs = 10;
- 	spi_message_add_tail(&transfer, &msg);
- 
- 	spin_lock_irqsave(&spilock, spilockflags);
-@@ -317,13 +337,10 @@ static uint16_t spi_transfer16(uint16_t
- 
- 	if (err < 0) {
- 		printe("spi_sync error %d\n", err);
--		return 0;
-+		return;
- 	}
- 
--	printd("received: %02x%02x\n", rxbuf[0], rxbuf[1]);
- 	printd("hasMore %d\n", pisnd_spi_has_more());
--
--	return (rxbuf[0] << 8) | rxbuf[1];
- }
- 
- static int spi_read_bytes(char *dst, size_t length, uint8_t *bytesRead)
-@@ -335,7 +352,7 @@ static int spi_read_bytes(char *dst, siz
- 	memset(dst, 0, length);
- 	*bytesRead = 0;
- 
--	 rx = spi_transfer16(0);
-+	rx = spi_transfer16(0);
- 	if (!(rx >> 8))
- 		return -EINVAL;
- 
-@@ -388,35 +405,90 @@ static struct spi_device *pisnd_spi_find
- 
- static void pisnd_work_handler(struct work_struct *work)
- {
--	uint16_t rx;
--	uint16_t tx;
-+	enum { TRANSFER_SIZE = 4 };
-+	enum { PISOUND_OUTPUT_BUFFER_SIZE = 128 };
-+	enum { MIDI_BYTES_PER_SECOND = 3125 };
-+	int out_buffer_used = 0;
-+	unsigned long now;
- 	uint8_t val;
-+	uint8_t txbuf[TRANSFER_SIZE];
-+	uint8_t rxbuf[TRANSFER_SIZE];
-+	uint8_t midibuf[TRANSFER_SIZE];
-+	int i, n;
-+	bool had_data;
-+
-+	unsigned long last_transfer_at = jiffies;
- 
- 	if (work == &pisnd_work_process) {
- 		if (pisnd_spi_device == NULL)
- 			return;
- 
- 		do {
--			val = 0;
--			tx = 0;
-+			if (g_midi_output_substream &&
-+				kfifo_avail(&spi_fifo_out) >= sizeof(midibuf)) {
- 
--			if (g_ledFlashDurationChanged) {
--				tx = 0xf000 | g_ledFlashDuration;
--				g_ledFlashDuration = 0;
--				g_ledFlashDurationChanged = false;
--			} else if (kfifo_get(&spi_fifo_out, &val)) {
--				tx = 0x0f00 | val;
-+				n = snd_rawmidi_transmit_peek(
-+					g_midi_output_substream,
-+					midibuf, sizeof(midibuf)
-+				);
-+
-+				if (n > 0) {
-+					for (i = 0; i < n; ++i)
-+						kfifo_put(
-+							&spi_fifo_out,
-+							midibuf[i]
-+							);
-+					snd_rawmidi_transmit_ack(
-+						g_midi_output_substream,
-+						i
-+						);
-+				}
- 			}
- 
--			rx = spi_transfer16(tx);
-+			had_data = false;
-+			memset(txbuf, 0, sizeof(txbuf));
-+			for (i = 0; i < sizeof(txbuf) &&
-+				out_buffer_used < PISOUND_OUTPUT_BUFFER_SIZE;
-+				i += 2) {
-+
-+				val = 0;
-+
-+				if (g_ledFlashDurationChanged) {
-+					txbuf[i+0] = 0xf0;
-+					txbuf[i+1] = g_ledFlashDuration;
-+					g_ledFlashDuration = 0;
-+					g_ledFlashDurationChanged = false;
-+				} else if (kfifo_get(&spi_fifo_out, &val)) {
-+					txbuf[i+0] = 0x0f;
-+					txbuf[i+1] = val;
-+					++out_buffer_used;
-+				}
-+			}
- 
--			if (rx & 0xff00) {
--				kfifo_put(&spi_fifo_in, rx & 0xff);
--				if (kfifo_len(&spi_fifo_in) > 16
--					&& g_recvCallback)
--					g_recvCallback(g_recvData);
-+			spi_transfer(txbuf, rxbuf, sizeof(txbuf));
-+			/* Estimate the Pisound's MIDI output buffer usage, so
-+			 * that we don't overflow it. Space in the buffer should
-+			 * be becoming available at the UART MIDI byte transfer
-+			 * rate.
-+			 */
-+			now = jiffies;
-+			out_buffer_used -=
-+				(MIDI_BYTES_PER_SECOND / HZ) /
-+				(now - last_transfer_at);
-+			if (out_buffer_used < 0)
-+				out_buffer_used = 0;
-+			last_transfer_at = now;
-+
-+			for (i = 0; i < sizeof(rxbuf); i += 2) {
-+				if (rxbuf[i]) {
-+					kfifo_put(&spi_fifo_in, rxbuf[i+1]);
-+					if (kfifo_len(&spi_fifo_in) > 16 &&
-+						g_recvCallback)
-+						g_recvCallback(g_recvData);
-+					had_data = true;
-+				}
- 			}
--		} while (rx != 0
-+		} while (had_data
- 			|| !kfifo_is_empty(&spi_fifo_out)
- 			|| pisnd_spi_has_more()
- 			|| g_ledFlashDurationChanged
-@@ -492,7 +564,7 @@ static int spi_read_info(void)
- 	if (!(tmp >> 8))
- 		return -EINVAL;
- 
--	 count = tmp & 0xff;
-+	count = tmp & 0xff;
- 
- 	for (i = 0; i < count; ++i) {
- 		memset(buffer, 0, sizeof(buffer));
-@@ -628,10 +700,17 @@ static void pisnd_spi_flash_leds(uint8_t
- 	pisnd_schedule_process(TASK_PROCESS);
- }
- 
--static void pisnd_spi_send(uint8_t val)
-+static void pisnd_spi_flush(void)
-+{
-+	while (!kfifo_is_empty(&spi_fifo_out)) {
-+		pisnd_spi_start();
-+		flush_workqueue(pisnd_workqueue);
-+	}
-+}
-+
-+static void pisnd_spi_start(void)
- {
--	kfifo_put(&spi_fifo_out, val);
--	printd("schedule from spi_send\n");
-+	printd("schedule from spi_start\n");
- 	pisnd_schedule_process(TASK_PROCESS);
- }
- 
-@@ -765,7 +844,7 @@ static int pisnd_hw_params(
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
- 	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- 
--	/* pisound runs on fixed 32 clock counts per channel,
-+	/* Pisound runs on fixed 32 clock counts per channel,
- 	 * as generated by the master ADC.
- 	 */
- 	snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2);
-@@ -786,8 +865,8 @@ static int pisnd_hw_params(
- 		break;
- 	case 96000:
- 		gpiod_set_value(osr0, true);
--		gpiod_set_value(osr1, true);
--		gpiod_set_value(osr2, false);
-+		gpiod_set_value(osr1, false);
-+		gpiod_set_value(osr2, true);
- 		break;
- 	case 192000:
- 		gpiod_set_value(osr0, true);
-@@ -1030,7 +1109,7 @@ static int pisnd_probe(struct platform_d
- 		return ret;
- 	}
- 
--	printi("Detected pisound card:\n");
-+	printi("Detected Pisound card:\n");
- 	printi("\tSerial:  %s\n", pisnd_spi_get_serial());
- 	printi("\tVersion: %s\n", pisnd_spi_get_version());
- 	printi("\tId:      %s\n", pisnd_spi_get_id());
-@@ -1119,5 +1198,5 @@ static struct platform_driver pisnd_driv
- module_platform_driver(pisnd_driver);
- 
- MODULE_AUTHOR("Giedrius Trainavicius <giedrius@blokas.io>");
--MODULE_DESCRIPTION("ASoC Driver for pisound, http://blokas.io/pisound");
-+MODULE_DESCRIPTION("ASoC Driver for Pisound, https://blokas.io/pisound");
- MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0139-overlays-Add-applepi-dac-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0139-overlays-Add-applepi-dac-overlay.patch
deleted file mode 100644
index a60fc8dc9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0139-overlays-Add-applepi-dac-overlay.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From 55b3c295a6dd32de589bcd38c771748773e2d0d2 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sat, 9 Dec 2017 21:45:12 +0000
-Subject: [PATCH 139/454] overlays: Add applepi-dac overlay
-
-See: https://github.com/raspberrypi/linux/issues/2302
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  6 ++
- .../boot/dts/overlays/applepi-dac-overlay.dts | 57 +++++++++++++++++++
- 3 files changed, 64 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/applepi-dac-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -11,6 +11,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	allo-digione.dtbo \
- 	allo-piano-dac-pcm512x-audio.dtbo \
- 	allo-piano-dac-plus-pcm512x-audio.dtbo \
-+	applepi-dac.dtbo \
- 	at86rf233.dtbo \
- 	audioinjector-addons.dtbo \
- 	audioinjector-wm8731-audio.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -337,6 +337,12 @@ Params: 24db_digital_gain       Allow ga
-                                 better voice quality. (default Off)
- 
- 
-+Name:   applepi-dac
-+Info:   Configures the Orchard Audio ApplePi-DAC audio card
-+Load:   dtoverlay=applepi-dac
-+Params: <None>
-+
-+
- Name:   at86rf233
- Info:   Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver,
-         connected to spi0.0
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts
-@@ -0,0 +1,57 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+    compatible = "brcm,bcm2708";
-+
-+    fragment@0 {
-+        target = <&sound>;
-+        __overlay__ {
-+            compatible = "simple-audio-card";
-+            simple-audio-card,name = "ApplePi-DAC";
-+
-+            status = "okay";
-+
-+            playback_link: simple-audio-card,dai-link@1 {
-+                format = "i2s";
-+
-+                p_cpu_dai: cpu {
-+                    sound-dai = <&i2s>;
-+                    dai-tdm-slot-num = <2>;
-+                    dai-tdm-slot-width = <32>;
-+                };
-+
-+                p_codec_dai: codec {
-+                    sound-dai = <&codec_out>;
-+                };
-+            };
-+        };
-+    };
-+
-+    fragment@1 {
-+        target-path = "/";
-+        __overlay__ {
-+            codec_out: pcm1794a-codec {
-+                #sound-dai-cells = <0>;
-+                compatible = "ti,pcm1794a";
-+                status = "okay";
-+            };
-+        };
-+    };
-+
-+    fragment@2 {
-+        target = <&i2s>;
-+        __overlay__ {
-+            #sound-dai-cells = <0>;
-+            status = "okay";
-+        };
-+    };
-+};
-+
-+/*
-+   Written by: Leonid Ayzenshtat
-+   Company: Orchard Audio (www.orchardaudio.com)
-+
-+   compile with:
-+   dtc -@ -H epapr -O dtb -o ApplePi-DAC.dtbo -W no-unit_address_vs_reg ApplePi-DAC.dts
-+*/
diff --git a/target/linux/brcm2708/patches-4.14/950-0140-staging-vchiq_arm-Make-debugfs-failure-non-fatal.patch b/target/linux/brcm2708/patches-4.14/950-0140-staging-vchiq_arm-Make-debugfs-failure-non-fatal.patch
deleted file mode 100644
index 71d6fa9dd..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0140-staging-vchiq_arm-Make-debugfs-failure-non-fatal.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From a200e0d898cd6396061e3a1901ac73df389b6e3d Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 12 Dec 2017 12:12:46 +0000
-Subject: [PATCH 140/454] staging: vchiq_arm: Make debugfs failure non-fatal
-
-It can be useful to be able to open multiple vchiq instances in a
-single process. This currently fails due to a debugfs collision,
-so make such a failure non-fatal.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- .../staging/vc04_services/interface/vchiq_arm/vchiq_arm.c   | 6 +-----
- 1 file changed, 1 insertion(+), 5 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
-@@ -1754,11 +1754,7 @@ vchiq_open(struct inode *inode, struct f
- 		instance->state = state;
- 		instance->pid = current->tgid;
- 
--		ret = vchiq_debugfs_add_instance(instance);
--		if (ret != 0) {
--			kfree(instance);
--			return ret;
--		}
-+		(void)vchiq_debugfs_add_instance(instance);
- 
- 		sema_init(&instance->insert_event, 0);
- 		sema_init(&instance->remove_event, 0);
diff --git a/target/linux/brcm2708/patches-4.14/950-0141-config-Add-PINCTRL_MCP23S08.patch b/target/linux/brcm2708/patches-4.14/950-0141-config-Add-PINCTRL_MCP23S08.patch
deleted file mode 100644
index d4aca4b3b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0141-config-Add-PINCTRL_MCP23S08.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From aff7b255fa4482a1b98147eec74a1468ca50a5d5 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sat, 23 Dec 2017 22:10:37 +0000
-Subject: [PATCH 141/454] config: Add PINCTRL_MCP23S08
-
-As of Linux 4.12, the mcp23s08 driver moved from drivers/gpio to
-drivers/pinctrl. At the same time, the Kconfig symbols changed
-from CONFIG_GPIO_MCP23S08 to CONFIG_PINCTRL_MCP23S08, effectively
-removing the MCP23S17 from the downstream defconfigs. Restore
-support by adding CONFIG_PINCTRL_MCP23S08.
-
-See: https://github.com/raspberrypi/linux/issues/2311
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -613,6 +613,7 @@ CONFIG_SPI_SLAVE=y
- CONFIG_PPS=m
- CONFIG_PPS_CLIENT_LDISC=m
- CONFIG_PPS_CLIENT_GPIO=m
-+CONFIG_PINCTRL_MCP23S08=m
- CONFIG_GPIO_SYSFS=y
- CONFIG_GPIO_BCM_EXP=y
- CONFIG_GPIO_BCM_VIRT=y
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -608,6 +608,7 @@ CONFIG_SPI_SLAVE=y
- CONFIG_PPS=m
- CONFIG_PPS_CLIENT_LDISC=m
- CONFIG_PPS_CLIENT_GPIO=m
-+CONFIG_PINCTRL_MCP23S08=m
- CONFIG_GPIO_SYSFS=y
- CONFIG_GPIO_PCF857X=m
- CONFIG_GPIO_ARIZONA=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0142-Add-Raspberry-Pi-firmware-driver-to-the-dependencies.patch b/target/linux/brcm2708/patches-4.14/950-0142-Add-Raspberry-Pi-firmware-driver-to-the-dependencies.patch
deleted file mode 100644
index 62c997f40..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0142-Add-Raspberry-Pi-firmware-driver-to-the-dependencies.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From 090a9a1964f3477d86cfa1c5e2b4018c7c48b778 Mon Sep 17 00:00:00 2001
-From: Alex Riesen <alexander.riesen@cetitec.com>
-Date: Thu, 21 Dec 2017 09:29:39 +0100
-Subject: [PATCH 142/454] Add Raspberry Pi firmware driver to the dependencies
- of backlight driver
-
-Otherwise the backlight driver fails to build if the firmware
-loading driver is not in the kernel
-
-Signed-off-by: Alex Riesen <alexander.riesen@cetitec.com>
----
- drivers/video/backlight/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/video/backlight/Kconfig
-+++ b/drivers/video/backlight/Kconfig
-@@ -267,6 +267,7 @@ config BACKLIGHT_PWM
- 
- config BACKLIGHT_RPI
- 	tristate "Raspberry Pi display firmware driven backlight"
-+	depends on RASPBERRYPI_FIRMWARE
- 	help
- 	  If you have the Raspberry Pi DSI touchscreen display, say Y to
- 	  enable the mailbox-controlled backlight driver.
diff --git a/target/linux/brcm2708/patches-4.14/950-0143-overlays-Add-media-center-HAT-overlay-2313.patch b/target/linux/brcm2708/patches-4.14/950-0143-overlays-Add-media-center-HAT-overlay-2313.patch
deleted file mode 100644
index 7c13ae318..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0143-overlays-Add-media-center-HAT-overlay-2313.patch
+++ /dev/null
@@ -1,190 +0,0 @@
-From 15aa7a1d49c20f7f41b5c69cea2f46e1e976e660 Mon Sep 17 00:00:00 2001
-From: Aaron Shaw <shawaj@gmail.com>
-Date: Sun, 24 Dec 2017 21:57:05 +0000
-Subject: [PATCH 143/454] overlays: Add media center HAT overlay (#2313)
-
----
- arch/arm/boot/dts/overlays/Makefile           |   1 +
- arch/arm/boot/dts/overlays/README             |  24 ++++
- .../dts/overlays/media-center-overlay.dts     | 132 ++++++++++++++++++
- 3 files changed, 157 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/media-center-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -61,6 +61,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	mcp2515-can0.dtbo \
- 	mcp2515-can1.dtbo \
- 	mcp3008.dtbo \
-+	media-center.dtbo \
- 	midi-uart0.dtbo \
- 	midi-uart1.dtbo \
- 	mmc.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -994,6 +994,30 @@ Params: spi<n>-<m>-present      boolean,
-         spi<n>-<m>-speed        integer, set the spi bus speed for this device
- 
- 
-+Name:   media-center
-+Info:   Media Center HAT - 2.83" Touch Display + extras by Pi Supply
-+Load:   dtoverlay=media-center,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+        rotate                  Display rotation {0,90,180,270}
-+        fps                     Delay between frame updates
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+        swapxy                  Swap x and y axis
-+        gpio_out_pin            GPIO for output (default "17")
-+        gpio_in_pin             GPIO for input (default "18")
-+        gpio_in_pull            Pull up/down/off on the input pin
-+                                (default "down")
-+        sense                   Override the IR receive auto-detection logic:
-+                                 "0" = force active-high
-+                                 "1" = force active-low
-+                                 "-1" = use auto-detection
-+                                (default "-1")
-+        softcarrier             Turn the software carrier "on" or "off"
-+                                (default "on")
-+        invert                  "on" = invert the output pin (default "off")
-+        debug                   "on" = enable additional debug messages
-+                                (default "off")
-+
-+
- Name:   midi-uart0
- Info:   Configures UART0 (ttyAMA0) so that a requested 38.4kbaud actually gets
-         31.25kbaud, the frequency required for MIDI
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/media-center-overlay.dts
-@@ -0,0 +1,132 @@
-+/*
-+ * Device Tree overlay for Media Center HAT by Pi Supply
-+ *
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+
-+			spidev@0{
-+				status = "disabled";
-+			};
-+
-+			spidev@1{
-+				status = "disabled";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			rpi_display_pins: rpi_display_pins {
-+				brcm,pins = <12 23 24 25>;
-+				brcm,function = <1 1 1 0>; /* out out out in */
-+				brcm,pull = <0 0 0 2>; /* - - - up */
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			rpidisplay: rpi-display@0{
-+				compatible = "ilitek,ili9341";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&rpi_display_pins>;
-+
-+				spi-max-frequency = <32000000>;
-+				rotate = <90>;
-+				bgr;
-+				fps = <30>;
-+				buswidth = <8>;
-+				reset-gpios = <&gpio 23 0>;
-+				dc-gpios = <&gpio 24 0>;
-+				led-gpios = <&gpio 12 1>;
-+				debug = <0>;
-+			};
-+
-+			rpidisplay_ts: rpi-display-ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <25 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 25 0>;
-+				ti,x-plate-ohms = /bits/ 16 <60>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target-path = "/";
-+		__overlay__ {
-+			lirc_rpi: lirc_rpi {
-+				compatible = "rpi,lirc-rpi";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&lirc_pins>;
-+				status = "okay";
-+
-+				// Override autodetection of IR receiver circuit
-+				// (0 = active high, 1 = active low, -1 = no override )
-+				rpi,sense = <0xffffffff>;
-+
-+				// Software carrier
-+				// (0 = off, 1 = on)
-+				rpi,softcarrier = <1>;
-+
-+				// Invert output
-+				// (0 = off, 1 = on)
-+				rpi,invert = <0>;
-+
-+				// Enable debugging messages
-+				// (0 = off, 1 = on)
-+				rpi,debug = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			lirc_pins: lirc_pins {
-+				brcm,pins = <6 5>;
-+				brcm,function = <1 0>; // out in
-+				brcm,pull = <0 1>; // off down
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		speed =   <&rpidisplay>,"spi-max-frequency:0";
-+		rotate =  <&rpidisplay>,"rotate:0";
-+		fps =     <&rpidisplay>,"fps:0";
-+		debug =   <&rpidisplay>,"debug:0",
-+		          <&lirc_rpi>,"rpi,debug:0";
-+		xohms =   <&rpidisplay_ts>,"ti,x-plate-ohms;0";
-+		swapxy =  <&rpidisplay_ts>,"ti,swap-xy?";
-+
-+		gpio_out_pin =  <&lirc_pins>,"brcm,pins:0";
-+		gpio_in_pin =   <&lirc_pins>,"brcm,pins:4";
-+		gpio_in_pull =  <&lirc_pins>,"brcm,pull:4";
-+
-+		sense =         <&lirc_rpi>,"rpi,sense:0";
-+		softcarrier =   <&lirc_rpi>,"rpi,softcarrier:0";
-+		invert =        <&lirc_rpi>,"rpi,invert:0";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0144-add-backlight-control-to-rpi-display-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0144-add-backlight-control-to-rpi-display-overlay.patch
deleted file mode 100644
index 6d7de6f51..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0144-add-backlight-control-to-rpi-display-overlay.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 68ad84eea4f5a100756faf1c393b16fbd1468b55 Mon Sep 17 00:00:00 2001
-From: Aaron Shaw <shawaj@gmail.com>
-Date: Thu, 28 Dec 2017 17:31:52 +0000
-Subject: [PATCH 144/454] add backlight control to rpi-display overlay
-
----
- arch/arm/boot/dts/overlays/README                  |  1 +
- arch/arm/boot/dts/overlays/rpi-display-overlay.dts | 14 ++++++++------
- 2 files changed, 9 insertions(+), 6 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1329,6 +1329,7 @@ Params: speed                   Display
-         debug                   Debug output level {0-7}
-         xohms                   Touchpanel sensitivity (X-plate resistance)
-         swapxy                  Swap x and y axis
-+        backlight               Change backlight GPIO pin {e.g. 12, 18}
- 
- 
- Name:   rpi-ft5406
---- a/arch/arm/boot/dts/overlays/rpi-display-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/rpi-display-overlay.dts
-@@ -79,11 +79,13 @@
- 		};
- 	};
- 	__overrides__ {
--		speed =   <&rpidisplay>,"spi-max-frequency:0";
--		rotate =  <&rpidisplay>,"rotate:0";
--		fps =     <&rpidisplay>,"fps:0";
--		debug =   <&rpidisplay>,"debug:0";
--		xohms =   <&rpidisplay_ts>,"ti,x-plate-ohms;0";
--		swapxy =  <&rpidisplay_ts>,"ti,swap-xy?";
-+		speed =     <&rpidisplay>,"spi-max-frequency:0";
-+		rotate =    <&rpidisplay>,"rotate:0";
-+		fps =       <&rpidisplay>,"fps:0";
-+		debug =     <&rpidisplay>,"debug:0";
-+		xohms =     <&rpidisplay_ts>,"ti,x-plate-ohms;0";
-+		swapxy =    <&rpidisplay_ts>,"ti,swap-xy?";
-+		backlight = <&rpidisplay>,"led-gpios:4",
-+		            <&rpi_display_pins>,"brcm,pins:0";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0145-add-backlight-control-to-media-center-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0145-add-backlight-control-to-media-center-overlay.patch
deleted file mode 100644
index 46ab9f7a9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0145-add-backlight-control-to-media-center-overlay.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 857e7afb6b7b60adb1f9ed9e05c3ced0c5ef7370 Mon Sep 17 00:00:00 2001
-From: Aaron Shaw <shawaj@gmail.com>
-Date: Thu, 28 Dec 2017 17:34:54 +0000
-Subject: [PATCH 145/454] add backlight control to media-center overlay
-
----
- arch/arm/boot/dts/overlays/README                |  1 +
- .../boot/dts/overlays/media-center-overlay.dts   | 16 +++++++++-------
- 2 files changed, 10 insertions(+), 7 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1002,6 +1002,7 @@ Params: speed                   Display
-         fps                     Delay between frame updates
-         xohms                   Touchpanel sensitivity (X-plate resistance)
-         swapxy                  Swap x and y axis
-+        backlight               Change backlight GPIO pin {e.g. 12, 18}
-         gpio_out_pin            GPIO for output (default "17")
-         gpio_in_pin             GPIO for input (default "18")
-         gpio_in_pull            Pull up/down/off on the input pin
---- a/arch/arm/boot/dts/overlays/media-center-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/media-center-overlay.dts
-@@ -113,13 +113,15 @@
- 	};
- 
- 	__overrides__ {
--		speed =   <&rpidisplay>,"spi-max-frequency:0";
--		rotate =  <&rpidisplay>,"rotate:0";
--		fps =     <&rpidisplay>,"fps:0";
--		debug =   <&rpidisplay>,"debug:0",
--		          <&lirc_rpi>,"rpi,debug:0";
--		xohms =   <&rpidisplay_ts>,"ti,x-plate-ohms;0";
--		swapxy =  <&rpidisplay_ts>,"ti,swap-xy?";
-+		speed =     <&rpidisplay>,"spi-max-frequency:0";
-+		rotate =    <&rpidisplay>,"rotate:0";
-+		fps =       <&rpidisplay>,"fps:0";
-+		debug =     <&rpidisplay>,"debug:0", 
-+		            <&lirc_rpi>,"rpi,debug:0";
-+		xohms =     <&rpidisplay_ts>,"ti,x-plate-ohms;0";
-+		swapxy =    <&rpidisplay_ts>,"ti,swap-xy?";
-+		backlight = <&rpidisplay>,"led-gpios:4",
-+		            <&rpi_display_pins>,"brcm,pins:0";
- 
- 		gpio_out_pin =  <&lirc_pins>,"brcm,pins:0";
- 		gpio_in_pin =   <&lirc_pins>,"brcm,pins:4";
diff --git a/target/linux/brcm2708/patches-4.14/950-0146-Add-overlay-for-mcp3202-12-bit-ADC.patch b/target/linux/brcm2708/patches-4.14/950-0146-Add-overlay-for-mcp3202-12-bit-ADC.patch
deleted file mode 100644
index 39f6a36db..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0146-Add-overlay-for-mcp3202-12-bit-ADC.patch
+++ /dev/null
@@ -1,248 +0,0 @@
-From ab6b50d10b73ed3150dd80633131b7d56c1c63df Mon Sep 17 00:00:00 2001
-From: penfold42 <penfold42@users.noreply.github.com>
-Date: Tue, 2 Jan 2018 00:15:19 +1100
-Subject: [PATCH 146/454] Add overlay for mcp3202 12 bit ADC
-
----
- arch/arm/boot/dts/overlays/Makefile           |   1 +
- arch/arm/boot/dts/overlays/README             |   9 +
- .../arm/boot/dts/overlays/mcp3202-overlay.dts | 205 ++++++++++++++++++
- 3 files changed, 215 insertions(+)
- create mode 100755 arch/arm/boot/dts/overlays/mcp3202-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -61,6 +61,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	mcp2515-can0.dtbo \
- 	mcp2515-can1.dtbo \
- 	mcp3008.dtbo \
-+	mcp3202.dtbo \
- 	media-center.dtbo \
- 	midi-uart0.dtbo \
- 	midi-uart1.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -994,6 +994,15 @@ Params: spi<n>-<m>-present      boolean,
-         spi<n>-<m>-speed        integer, set the spi bus speed for this device
- 
- 
-+Name:   mcp3202
-+Info:   Configures MCP3202 A/D converters
-+        For devices on spi1 or spi2, the interfaces should be enabled
-+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
-+Load:   dtoverlay=mcp3202,<param>[=<val>]
-+Params: spi<n>-<m>-present      boolean, configure device at spi<n>, cs<m>
-+        spi<n>-<m>-speed        integer, set the spi bus speed for this device
-+
-+
- Name:   media-center
- Info:   Media Center HAT - 2.83" Touch Display + extras by Pi Supply
- Load:   dtoverlay=media-center,<param>=<val>
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mcp3202-overlay.dts
-@@ -0,0 +1,205 @@
-+/*
-+ * Device tree overlay for Microchip mcp3202 12-Bit A/D Converters
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spidev0>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev1>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "spi1/spidev@0";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target-path = "spi1/spidev@1";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@4 {
-+		target-path = "spi1/spidev@2";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@5 {
-+		target-path = "spi2/spidev@0";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@6 {
-+		target-path = "spi2/spidev@1";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@7 {
-+		target-path = "spi2/spidev@2";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@8 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3202_00: mcp3202@0 {
-+				compatible = "mcp3202";
-+				reg = <0>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@9 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3202_01: mcp3202@1 {
-+				compatible = "mcp3202";
-+				reg = <1>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@10 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3202_10: mcp3202@0 {
-+				compatible = "mcp3202";
-+				reg = <0>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@11 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3202_11: mcp3202@1 {
-+				compatible = "mcp3202";
-+				reg = <1>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@12 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3202_12: mcp3202@2 {
-+				compatible = "mcp3202";
-+				reg = <2>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@13 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3202_20: mcp3202@0 {
-+				compatible = "mcp3202";
-+				reg = <0>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@14 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3202_21: mcp3202@1 {
-+				compatible = "mcp3202";
-+				reg = <1>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	fragment@15 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			mcp3202_22: mcp3202@2 {
-+				compatible = "mcp3202";
-+				reg = <2>;
-+				spi-max-frequency = <1600000>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		spi0-0-present = <0>, "+0+8";
-+		spi0-1-present = <0>, "+1+9";
-+		spi1-0-present = <0>, "+2+10";
-+		spi1-1-present = <0>, "+3+11";
-+		spi1-2-present = <0>, "+4+12";
-+		spi2-0-present = <0>, "+5+13";
-+		spi2-1-present = <0>, "+6+14";
-+		spi2-2-present = <0>, "+7+15";
-+		spi0-0-speed = <&mcp3202_00>, "spi-max-frequency:0";
-+		spi0-1-speed = <&mcp3202_01>, "spi-max-frequency:0";
-+		spi1-0-speed = <&mcp3202_10>, "spi-max-frequency:0";
-+		spi1-1-speed = <&mcp3202_11>, "spi-max-frequency:0";
-+		spi1-2-speed = <&mcp3202_12>, "spi-max-frequency:0";
-+		spi2-0-speed = <&mcp3202_20>, "spi-max-frequency:0";
-+		spi2-1-speed = <&mcp3202_21>, "spi-max-frequency:0";
-+		spi2-2-speed = <&mcp3202_22>, "spi-max-frequency:0";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0147-dwc_otg-don-t-unconditionally-force-host-mode-in-dwc.patch b/target/linux/brcm2708/patches-4.14/950-0147-dwc_otg-don-t-unconditionally-force-host-mode-in-dwc.patch
deleted file mode 100644
index 9bea4b363..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0147-dwc_otg-don-t-unconditionally-force-host-mode-in-dwc.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 71f116335e08f82f73efec6da10893f545455b5f Mon Sep 17 00:00:00 2001
-From: P33M <p33m@github.com>
-Date: Tue, 9 Jan 2018 15:16:35 +0000
-Subject: [PATCH 147/454] dwc_otg: don't unconditionally force host mode in
- dwc_otg_cil_init()
-
-Add the ability to disable force_host_mode for those that want to use
-dwc_otg in both device and host modes.
----
- drivers/usb/host/dwc_otg/dwc_otg_cil.c    | 7 ++++++-
- drivers/usb/host/dwc_otg/dwc_otg_driver.c | 7 +++++++
- 2 files changed, 13 insertions(+), 1 deletion(-)
-
---- a/drivers/usb/host/dwc_otg/dwc_otg_cil.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c
-@@ -61,6 +61,8 @@
- #include "dwc_otg_regs.h"
- #include "dwc_otg_cil.h"
- 
-+extern bool cil_force_host;
-+
- static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
- 
- /**
-@@ -192,7 +194,10 @@ dwc_otg_core_if_t *dwc_otg_cil_init(cons
- 		core_if->hptxfsiz.d32 =
- 		DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
- 		gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
--		gusbcfg.b.force_host_mode = 1;
-+		if (cil_force_host)
-+			gusbcfg.b.force_host_mode = 1;
-+		else
-+			gusbcfg.b.force_host_mode = 0;
- 		DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
- 		dwc_mdelay(100);
- 	}
---- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
-@@ -247,6 +247,9 @@ bool fiq_fsm_enable = true;
- //Bulk split-transaction NAK holdoff in microframes
- uint16_t nak_holdoff = 8;
- 
-+//Force host mode during CIL re-init
-+bool cil_force_host = true;
-+
- unsigned short fiq_fsm_mask = 0x0F;
- 
- unsigned short int_ep_interval_min = 0;
-@@ -1403,6 +1406,10 @@ MODULE_PARM_DESC(int_ep_interval_min, "C
- 					"0..1 = Use endpoint default\n"
- 					"2..n = Minimum interval n microframes. Use powers of 2.\n");
- 
-+module_param(cil_force_host, bool, 0644);
-+MODULE_PARM_DESC(cil_force_host, "On a connector-ID status change, "
-+					"force Host Mode regardless of OTG state.");
-+
- /** @page "Module Parameters"
-  *
-  * The following parameters may be specified when starting the module.
diff --git a/target/linux/brcm2708/patches-4.14/950-0148-vcsm-Define-cache-operation-constants-in-user-header.patch b/target/linux/brcm2708/patches-4.14/950-0148-vcsm-Define-cache-operation-constants-in-user-header.patch
deleted file mode 100644
index 780fd6c54..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0148-vcsm-Define-cache-operation-constants-in-user-header.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 2e485e16881f0aad726dd401df6e9f2eb96f64dd Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Thu, 4 Jan 2018 23:58:06 +0900
-Subject: [PATCH 148/454] vcsm: Define cache operation constants in user header
-
-Without this change, users have to use raw values (1, 2, 3) to specify
-cache operation.
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- drivers/char/broadcom/vc_sm/vc_sm_knl.h | 5 -----
- include/linux/broadcom/vmcs_sm_ioctl.h  | 5 +++++
- 2 files changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/char/broadcom/vc_sm/vc_sm_knl.h
-+++ b/drivers/char/broadcom/vc_sm/vc_sm_knl.h
-@@ -27,11 +27,6 @@ enum vc_sm_lock_cache_mode {
- 	VC_SM_LOCK_NON_CACHED,
- };
- 
--/* Cache functions */
--#define VCSM_CACHE_OP_INV       0x01
--#define VCSM_CACHE_OP_CLEAN     0x02
--#define VCSM_CACHE_OP_FLUSH     0x03
--
- /* Allocate a shared memory handle and block. */
- int vc_sm_alloc(struct vc_sm_alloc_t *alloc, int *handle);
- 
---- a/include/linux/broadcom/vmcs_sm_ioctl.h
-+++ b/include/linux/broadcom/vmcs_sm_ioctl.h
-@@ -79,6 +79,11 @@ enum vmcs_sm_cache_e {
- 	VMCS_SM_CACHE_BOTH,
- };
- 
-+/* Cache functions */
-+#define VCSM_CACHE_OP_INV       0x01
-+#define VCSM_CACHE_OP_CLEAN     0x02
-+#define VCSM_CACHE_OP_FLUSH     0x03
-+
- /* IOCTL Data structures */
- struct vmcs_sm_ioctl_alloc {
- 	/* user -> kernel */
diff --git a/target/linux/brcm2708/patches-4.14/950-0149-vcsm-Support-for-finding-user-vc-handle-in-memory-po.patch b/target/linux/brcm2708/patches-4.14/950-0149-vcsm-Support-for-finding-user-vc-handle-in-memory-po.patch
deleted file mode 100644
index 25945fa37..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0149-vcsm-Support-for-finding-user-vc-handle-in-memory-po.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From ef55290ab88bb9a640bb0ab7213b6827c7207ee6 Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Fri, 5 Jan 2018 00:01:30 +0900
-Subject: [PATCH 149/454] vcsm: Support for finding user/vc handle in memory
- pool
-
-vmcs_sm_{usr,vc}_handle_from_pid_and_address() were failing to find
-handle if specified user pointer is not exactly the one that the memory
-locking call returned even if the pointer is in range of map/resource.
-So fixed the functions to match the range.
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- drivers/char/broadcom/vc_sm/vmcs_sm.c | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
---- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -276,7 +276,10 @@ static unsigned int vmcs_sm_vc_handle_fr
- 	/* Lookup the resource. */
- 	if (!list_empty(&sm_state->map_list)) {
- 		list_for_each_entry(map, &sm_state->map_list, map_list) {
--			if (map->res_pid != pid || map->res_addr != addr)
-+			if (map->res_pid != pid)
-+				continue;
-+			if (!(map->res_addr <= addr &&
-+						addr < map->res_addr + map->resource->res_size))
- 				continue;
- 
- 			pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n",
-@@ -326,7 +329,10 @@ static unsigned int vmcs_sm_usr_handle_f
- 	/* Lookup the resource. */
- 	if (!list_empty(&sm_state->map_list)) {
- 		list_for_each_entry(map, &sm_state->map_list, map_list) {
--			if (map->res_pid != pid || map->res_addr != addr)
-+			if (map->res_pid != pid)
-+				continue;
-+			if (!(map->res_addr <= addr &&
-+						addr < map->res_addr + map->resource->res_size))
- 				continue;
- 
- 			pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n",
diff --git a/target/linux/brcm2708/patches-4.14/950-0150-vcsm-Unify-cache-manipulating-functions.patch b/target/linux/brcm2708/patches-4.14/950-0150-vcsm-Unify-cache-manipulating-functions.patch
deleted file mode 100644
index fca1f15ac..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0150-vcsm-Unify-cache-manipulating-functions.patch
+++ /dev/null
@@ -1,389 +0,0 @@
-From 361974032ae1b0eec36c51a8f1cd9b447864fcbd Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Fri, 5 Jan 2018 00:44:00 +0900
-Subject: [PATCH 150/454] vcsm: Unify cache manipulating functions
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- drivers/char/broadcom/vc_sm/vmcs_sm.c | 309 +++++++++++---------------
- 1 file changed, 132 insertions(+), 177 deletions(-)
-
---- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -1256,61 +1256,106 @@ static const struct vm_operations_struct
- 	.fault = vcsm_vma_fault,
- };
- 
--/* Walks a VMA and clean each valid page from the cache */
--static void vcsm_vma_cache_clean_page_range(unsigned long addr,
--					    unsigned long end)
-+static int clean_invalid_mem_2d(const void __user *addr,
-+		const size_t block_count, const size_t block_size, const size_t stride,
-+		const unsigned cache_op)
- {
--	pgd_t *pgd;
--	pud_t *pud;
--	pmd_t *pmd;
--	pte_t *pte;
--	unsigned long pgd_next, pud_next, pmd_next;
--
--	if (addr >= end)
--		return;
--
--	/* Walk PGD */
--	pgd = pgd_offset(current->mm, addr);
--	do {
--		pgd_next = pgd_addr_end(addr, end);
--
--		if (pgd_none(*pgd) || pgd_bad(*pgd))
--			continue;
--
--		/* Walk PUD */
--		pud = pud_offset(pgd, addr);
--		do {
--			pud_next = pud_addr_end(addr, pgd_next);
--			if (pud_none(*pud) || pud_bad(*pud))
--				continue;
--
--			/* Walk PMD */
--			pmd = pmd_offset(pud, addr);
--			do {
--				pmd_next = pmd_addr_end(addr, pud_next);
--				if (pmd_none(*pmd) || pmd_bad(*pmd))
--					continue;
--
--				/* Walk PTE */
--				pte = pte_offset_map(pmd, addr);
--				do {
--					if (pte_none(*pte)
--					    || !pte_present(*pte))
--						continue;
--
--					/* Clean + invalidate */
--					dmac_flush_range((const void *) addr,
--							 (const void *)
--							 (addr + PAGE_SIZE));
--
--				} while (pte++, addr +=
--					 PAGE_SIZE, addr != pmd_next);
--				pte_unmap(pte);
-+	size_t i;
-+	void (*op_fn)(const void*, const void*);
- 
--			} while (pmd++, addr = pmd_next, addr != pud_next);
-+	if (block_size <= 0) {
-+		pr_err("[%s]: size cannot be 0\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	switch (cache_op) {
-+	case VCSM_CACHE_OP_INV:
-+		op_fn = dmac_inv_range;
-+		break;
-+	case VCSM_CACHE_OP_CLEAN:
-+		op_fn = dmac_clean_range;
-+		break;
-+	case VCSM_CACHE_OP_FLUSH:
-+		op_fn = dmac_flush_range;
-+		break;
-+	default:
-+		pr_err("[%s]: Invalid cache_op: 0x%08x\n", __func__, cache_op);
-+		return -EINVAL;
-+	}
-+
-+	for (i = 0; i < block_count; i ++, addr += stride)
-+		op_fn(addr, addr + block_size);
-+
-+	return 0;
-+}
-+
-+static int clean_invalid_mem(const void __user *addr, const size_t size,
-+		const unsigned cache_op)
-+{
-+	return clean_invalid_mem_2d(addr, 1, size, 0, cache_op);
-+}
-+
-+static int clean_invalid_resource(const void __user *addr, const size_t size,
-+		const unsigned cache_op, const int usr_hdl,
-+		struct sm_resource_t *resource)
-+{
-+	int err;
-+	enum sm_stats_t stat_attempt, stat_failure;
-+	void __user *res_addr;
-+
-+	if (resource == NULL) {
-+		pr_err("[%s]: resource is NULL\n", __func__);
-+		return -EINVAL;
-+	}
-+	if (resource->res_cached != VMCS_SM_CACHE_HOST &&
-+				resource->res_cached != VMCS_SM_CACHE_BOTH)
-+		return 0;
-+
-+	switch (cache_op) {
-+	case VCSM_CACHE_OP_INV:
-+		stat_attempt = INVALID;
-+		stat_failure = INVALID_FAIL;
-+		break;
-+	case VCSM_CACHE_OP_CLEAN:
-+		/* Like the original VMCS_SM_CMD_CLEAN_INVALID ioctl handler does. */
-+		stat_attempt = FLUSH;
-+		stat_failure = FLUSH_FAIL;
-+		break;
-+	case VCSM_CACHE_OP_FLUSH:
-+		stat_attempt = FLUSH;
-+		stat_failure = FLUSH_FAIL;
-+		break;
-+	default:
-+		pr_err("[%s]: Invalid cache_op: 0x%08x\n", __func__, cache_op);
-+		return -EINVAL;
-+	}
-+	resource->res_stats[stat_attempt]++;
- 
--		} while (pud++, addr = pud_next, addr != pgd_next);
--	} while (pgd++, addr = pgd_next, addr != end);
-+	if (size > resource->res_size) {
-+		pr_err("[%s]: size (0x%08zu) is larger than res_size (0x%08zu)\n",
-+				__func__, size, resource->res_size);
-+		return -EFAULT;
-+	}
-+	res_addr = (void __user*) vmcs_sm_usr_address_from_pid_and_usr_handle(
-+			current->tgid, usr_hdl);
-+	if (res_addr == NULL) {
-+		pr_err("[%s]: Failed to get user address "
-+				"from pid (%d) and user handle (%d)\n", __func__, current->tgid,
-+				resource->res_handle);
-+		return -EINVAL;
-+	}
-+	if (!(res_addr <= addr && addr + size <= res_addr + resource->res_size)) {
-+		pr_err("[%s]: Addr (0x%p-0x%p) out of range (0x%p-0x%p)\n",
-+				__func__, addr, addr + size, res_addr,
-+				res_addr + resource->res_size);
-+		return -EFAULT;
-+	}
-+
-+	err = clean_invalid_mem(addr, size, cache_op);
-+	if (err)
-+		resource->res_stats[stat_failure]++;
-+
-+	return err;
- }
- 
- /* Map an allocated data into something that the user space. */
-@@ -1952,14 +1997,13 @@ static int vc_sm_ioctl_unlock(struct sm_
- 			list_for_each_entry(map, &resource->map_list,
- 					    resource_map_list) {
- 				if (map->vma) {
--					unsigned long start;
--					unsigned long end;
--
--					start = map->vma->vm_start;
--					end = map->vma->vm_end;
-+					const unsigned long start = map->vma->vm_start;
-+					const unsigned long end = map->vma->vm_end;
- 
--					vcsm_vma_cache_clean_page_range(
--							start, end);
-+					ret = clean_invalid_mem((void __user*) start, end - start,
-+							VCSM_CACHE_OP_FLUSH);
-+					if (ret)
-+						goto error;
- 				}
- 			}
- 			up_read(&current->mm->mmap_sem);
-@@ -2833,41 +2877,17 @@ static long vc_sm_ioctl(struct file *fil
- 			/* Locate resource from GUID. */
- 			resource =
- 			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
--
--			if ((resource != NULL) && resource->res_cached) {
--				dma_addr_t phys_addr = 0;
--
--				resource->res_stats[FLUSH]++;
--
--				phys_addr =
--				    (dma_addr_t)((uint32_t)
--						 resource->res_base_mem &
--						 0x3FFFFFFF);
--				phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
--
--				/* L1 cache flush */
--				down_read(&current->mm->mmap_sem);
--				vcsm_vma_cache_clean_page_range((unsigned long)
--								ioparam.addr,
--								(unsigned long)
--								ioparam.addr +
--								ioparam.size);
--				up_read(&current->mm->mmap_sem);
--
--				/* L2 cache flush */
--				outer_clean_range(phys_addr,
--						  phys_addr +
--						  (size_t) ioparam.size);
--			} else if (resource == NULL) {
-+			if (resource == NULL) {
- 				ret = -EINVAL;
- 				goto out;
- 			}
- 
--			if (resource)
--				vmcs_sm_release_resource(resource, 0);
--
--			/* Done. */
--			goto out;
-+			ret = clean_invalid_resource((void __user*) ioparam.addr,
-+					ioparam.size, VCSM_CACHE_OP_FLUSH, ioparam.handle,
-+					resource);
-+			vmcs_sm_release_resource(resource, 0);
-+			if (ret)
-+				goto out;
- 		}
- 		break;
- 
-@@ -2888,41 +2908,16 @@ static long vc_sm_ioctl(struct file *fil
- 			/* Locate resource from GUID. */
- 			resource =
- 			    vmcs_sm_acquire_resource(file_data, ioparam.handle);
--
--			if ((resource != NULL) && resource->res_cached) {
--				dma_addr_t phys_addr = 0;
--
--				resource->res_stats[INVALID]++;
--
--				phys_addr =
--				    (dma_addr_t)((uint32_t)
--						 resource->res_base_mem &
--						 0x3FFFFFFF);
--				phys_addr += (dma_addr_t)mm_vc_mem_phys_addr;
--
--				/* L2 cache invalidate */
--				outer_inv_range(phys_addr,
--						phys_addr +
--						(size_t) ioparam.size);
--
--				/* L1 cache invalidate */
--				down_read(&current->mm->mmap_sem);
--				vcsm_vma_cache_clean_page_range((unsigned long)
--								ioparam.addr,
--								(unsigned long)
--								ioparam.addr +
--								ioparam.size);
--				up_read(&current->mm->mmap_sem);
--			} else if (resource == NULL) {
-+			if (resource == NULL) {
- 				ret = -EINVAL;
- 				goto out;
- 			}
- 
--			if (resource)
--				vmcs_sm_release_resource(resource, 0);
--
--			/* Done. */
--			goto out;
-+			ret = clean_invalid_resource((void __user*) ioparam.addr,
-+					ioparam.size, VCSM_CACHE_OP_INV, ioparam.handle, resource);
-+			vmcs_sm_release_resource(resource, 0);
-+			if (ret)
-+				goto out;
- 		}
- 		break;
- 
-@@ -2941,43 +2936,27 @@ static long vc_sm_ioctl(struct file *fil
- 				goto out;
- 			}
- 			for (i = 0; i < sizeof(ioparam.s) / sizeof(*ioparam.s); i++) {
--				switch (ioparam.s[i].cmd) {
--				case VCSM_CACHE_OP_INV:	/* L1/L2 invalidate virtual range */
--				case VCSM_CACHE_OP_FLUSH: /* L1/L2 clean physical range */
--				case VCSM_CACHE_OP_CLEAN: /* L1/L2 clean+invalidate all */
--					/* Locate resource from GUID. */
--					resource =
--					    vmcs_sm_acquire_resource(file_data, ioparam.s[i].handle);
--
--					if ((resource != NULL) && resource->res_cached) {
--						unsigned long base = ioparam.s[i].addr & ~(PAGE_SIZE - 1);
--						unsigned long end = (ioparam.s[i].addr + ioparam.s[i].size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
--
--						resource->res_stats[ioparam.s[i].cmd == 1 ? INVALID : FLUSH]++;
--
--						/* L1/L2 cache flush */
--						down_read(&current->mm->mmap_sem);
--						vcsm_vma_cache_clean_page_range(base, end);
--						up_read(&current->mm->mmap_sem);
--					} else if (resource == NULL) {
--						ret = -EINVAL;
--						goto out;
--					}
--
--					if (resource)
--						vmcs_sm_release_resource(resource, 0);
--
--					break;
--				default:
--					break; /* NOOP */
-+				/* Locate resource from GUID. */
-+				resource =
-+					vmcs_sm_acquire_resource(file_data, ioparam.s[i].handle);
-+				if (resource == NULL) {
-+					ret = -EINVAL;
-+					goto out;
- 				}
-+
-+				ret = clean_invalid_resource((void __user*) ioparam.s[i].addr,
-+						ioparam.s[i].size, ioparam.s[i].cmd,
-+						ioparam.s[i].handle, resource);
-+				vmcs_sm_release_resource(resource, 0);
-+				if (ret)
-+					goto out;
- 			}
- 		}
- 		break;
- 	/* Flush/Invalidate the cache for a given mapping. */
- 	case VMCS_SM_CMD_CLEAN_INVALID2:
- 		{
--				int i, j;
-+				int i;
- 				struct vmcs_sm_ioctl_clean_invalid2 ioparam;
- 				struct vmcs_sm_ioctl_clean_invalid_block *block = NULL;
- 
-@@ -3006,36 +2985,12 @@ static long vc_sm_ioctl(struct file *fil
- 
- 				for (i = 0; i < ioparam.op_count; i++) {
- 					const struct vmcs_sm_ioctl_clean_invalid_block * const op = block + i;
--					void (*op_fn)(const void *, const void *);
- 
--					switch(op->invalidate_mode & 3) {
--						case VCSM_CACHE_OP_INV:
--							op_fn = dmac_inv_range;
--							break;
--						case VCSM_CACHE_OP_CLEAN:
--							op_fn = dmac_clean_range;
--							break;
--						case VCSM_CACHE_OP_FLUSH:
--							op_fn = dmac_flush_range;
--							break;
--						default:
--							op_fn = 0;
--							break;
--					}
--
--					if ((op->invalidate_mode & ~3) != 0) {
--						ret = -EINVAL;
--						break;
--					}
--
--					if (op_fn == 0)
--						continue;
--
--					for (j = 0; j < op->block_count; ++j) {
--						const char * const base = (const char *)op->start_address + j * op->inter_block_stride;
--						const char * const end = base + op->block_size;
--						op_fn(base, end);
--					}
-+					ret = clean_invalid_mem_2d((void __user*) op->start_address,
-+							op->block_count, op->block_size,
-+							op->inter_block_stride, op->invalidate_mode);
-+					if (ret)
-+						goto out;
- 				}
- 				kfree(block);
- 			}
diff --git a/target/linux/brcm2708/patches-4.14/950-0151-vcsm-Fix-obscure-conditions.patch b/target/linux/brcm2708/patches-4.14/950-0151-vcsm-Fix-obscure-conditions.patch
deleted file mode 100644
index 3c4f1dc45..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0151-vcsm-Fix-obscure-conditions.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 92b27d4017371772d0370d1e60a32a9f22224c81 Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Mon, 8 Jan 2018 21:07:17 +0900
-Subject: [PATCH 151/454] vcsm: Fix obscure conditions
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- drivers/char/broadcom/vc_sm/vmcs_sm.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -278,8 +278,8 @@ static unsigned int vmcs_sm_vc_handle_fr
- 		list_for_each_entry(map, &sm_state->map_list, map_list) {
- 			if (map->res_pid != pid)
- 				continue;
--			if (!(map->res_addr <= addr &&
--						addr < map->res_addr + map->resource->res_size))
-+			if (addr < map->res_addr ||
-+						addr >= (map->res_addr + map->resource->res_size))
- 				continue;
- 
- 			pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n",
-@@ -1263,7 +1263,7 @@ static int clean_invalid_mem_2d(const vo
- 	size_t i;
- 	void (*op_fn)(const void*, const void*);
- 
--	if (block_size <= 0) {
-+	if (!block_size) {
- 		pr_err("[%s]: size cannot be 0\n", __func__);
- 		return -EINVAL;
- 	}
diff --git a/target/linux/brcm2708/patches-4.14/950-0152-vcsm-Fix-memory-leaking-on-clean_invalid2-ioctl-hand.patch b/target/linux/brcm2708/patches-4.14/950-0152-vcsm-Fix-memory-leaking-on-clean_invalid2-ioctl-hand.patch
deleted file mode 100644
index ebb490d92..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0152-vcsm-Fix-memory-leaking-on-clean_invalid2-ioctl-hand.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From d52c0da67a825372cf071dfe118b23a6bca43e5a Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Mon, 8 Jan 2018 21:11:23 +0900
-Subject: [PATCH 152/454] vcsm: Fix memory leaking on clean_invalid2 ioctl
- handler
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- drivers/char/broadcom/vc_sm/vmcs_sm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -2990,7 +2990,7 @@ static long vc_sm_ioctl(struct file *fil
- 							op->block_count, op->block_size,
- 							op->inter_block_stride, op->invalidate_mode);
- 					if (ret)
--						goto out;
-+						break;
- 				}
- 				kfree(block);
- 			}
diff --git a/target/linux/brcm2708/patches-4.14/950-0153-vcsm-Describe-the-use-of-cache-operation-constants.patch b/target/linux/brcm2708/patches-4.14/950-0153-vcsm-Describe-the-use-of-cache-operation-constants.patch
deleted file mode 100644
index 6cbf624a9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0153-vcsm-Describe-the-use-of-cache-operation-constants.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From d99ef60d169e20b8ab9f0d5b76d4d0e27a37526a Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Mon, 8 Jan 2018 21:15:13 +0900
-Subject: [PATCH 153/454] vcsm: Describe the use of cache operation constants
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- include/linux/broadcom/vmcs_sm_ioctl.h | 13 ++++++++-----
- 1 file changed, 8 insertions(+), 5 deletions(-)
-
---- a/include/linux/broadcom/vmcs_sm_ioctl.h
-+++ b/include/linux/broadcom/vmcs_sm_ioctl.h
-@@ -79,11 +79,6 @@ enum vmcs_sm_cache_e {
- 	VMCS_SM_CACHE_BOTH,
- };
- 
--/* Cache functions */
--#define VCSM_CACHE_OP_INV       0x01
--#define VCSM_CACHE_OP_CLEAN     0x02
--#define VCSM_CACHE_OP_FLUSH     0x03
--
- /* IOCTL Data structures */
- struct vmcs_sm_ioctl_alloc {
- 	/* user -> kernel */
-@@ -173,6 +168,14 @@ struct vmcs_sm_ioctl_cache {
- 	unsigned int size;
- };
- 
-+/*
-+ * Cache functions to be set to struct vmcs_sm_ioctl_clean_invalid cmd and
-+ * vmcs_sm_ioctl_clean_invalid2 invalidate_mode.
-+ */
-+#define VCSM_CACHE_OP_INV       0x01
-+#define VCSM_CACHE_OP_CLEAN     0x02
-+#define VCSM_CACHE_OP_FLUSH     0x03
-+
- struct vmcs_sm_ioctl_clean_invalid {
- 	/* user -> kernel */
- 	struct {
diff --git a/target/linux/brcm2708/patches-4.14/950-0154-vcsm-Fix-obscure-conditions-again.patch b/target/linux/brcm2708/patches-4.14/950-0154-vcsm-Fix-obscure-conditions-again.patch
deleted file mode 100644
index fa2f18cae..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0154-vcsm-Fix-obscure-conditions-again.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From e573dde8103d381a65acfd2be3964b0d1ba93932 Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Tue, 9 Jan 2018 12:33:24 +0900
-Subject: [PATCH 154/454] vcsm: Fix obscure conditions again
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- drivers/char/broadcom/vc_sm/vmcs_sm.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -331,8 +331,8 @@ static unsigned int vmcs_sm_usr_handle_f
- 		list_for_each_entry(map, &sm_state->map_list, map_list) {
- 			if (map->res_pid != pid)
- 				continue;
--			if (!(map->res_addr <= addr &&
--						addr < map->res_addr + map->resource->res_size))
-+			if (addr < map->res_addr ||
-+						addr >= (map->res_addr + map->resource->res_size))
- 				continue;
- 
- 			pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n",
diff --git a/target/linux/brcm2708/patches-4.14/950-0155-vcsm-Add-no-op-cache-operation-constant.patch b/target/linux/brcm2708/patches-4.14/950-0155-vcsm-Add-no-op-cache-operation-constant.patch
deleted file mode 100644
index 138a42abb..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0155-vcsm-Add-no-op-cache-operation-constant.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 068cfca9e8c54902c45b8c35b49191c766d346c9 Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Wed, 10 Jan 2018 04:32:20 +0900
-Subject: [PATCH 155/454] vcsm: Add no-op cache operation constant
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- drivers/char/broadcom/vc_sm/vmcs_sm.c  | 10 ++++++++++
- include/linux/broadcom/vmcs_sm_ioctl.h |  1 +
- 2 files changed, 11 insertions(+)
-
---- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -1269,6 +1269,8 @@ static int clean_invalid_mem_2d(const vo
- 	}
- 
- 	switch (cache_op) {
-+	case VCSM_CACHE_OP_NOP:
-+		return 0;
- 	case VCSM_CACHE_OP_INV:
- 		op_fn = dmac_inv_range;
- 		break;
-@@ -1312,6 +1314,8 @@ static int clean_invalid_resource(const
- 		return 0;
- 
- 	switch (cache_op) {
-+	case VCSM_CACHE_OP_NOP:
-+		return 0;
- 	case VCSM_CACHE_OP_INV:
- 		stat_attempt = INVALID;
- 		stat_failure = INVALID_FAIL;
-@@ -2936,6 +2940,9 @@ static long vc_sm_ioctl(struct file *fil
- 				goto out;
- 			}
- 			for (i = 0; i < sizeof(ioparam.s) / sizeof(*ioparam.s); i++) {
-+				if (ioparam.s[i].cmd == VCSM_CACHE_OP_NOP)
-+					break;
-+
- 				/* Locate resource from GUID. */
- 				resource =
- 					vmcs_sm_acquire_resource(file_data, ioparam.s[i].handle);
-@@ -2989,6 +2996,9 @@ static long vc_sm_ioctl(struct file *fil
- 					ret = clean_invalid_mem_2d((void __user*) op->start_address,
- 							op->block_count, op->block_size,
- 							op->inter_block_stride, op->invalidate_mode);
-+					if (op->invalidate_mode == VCSM_CACHE_OP_NOP)
-+						continue;
-+
- 					if (ret)
- 						break;
- 				}
---- a/include/linux/broadcom/vmcs_sm_ioctl.h
-+++ b/include/linux/broadcom/vmcs_sm_ioctl.h
-@@ -172,6 +172,7 @@ struct vmcs_sm_ioctl_cache {
-  * Cache functions to be set to struct vmcs_sm_ioctl_clean_invalid cmd and
-  * vmcs_sm_ioctl_clean_invalid2 invalidate_mode.
-  */
-+#define VCSM_CACHE_OP_NOP       0x00
- #define VCSM_CACHE_OP_INV       0x01
- #define VCSM_CACHE_OP_CLEAN     0x02
- #define VCSM_CACHE_OP_FLUSH     0x03
diff --git a/target/linux/brcm2708/patches-4.14/950-0156-vcsm-Revert-to-do-page-table-walk-based-cache-manipu.patch b/target/linux/brcm2708/patches-4.14/950-0156-vcsm-Revert-to-do-page-table-walk-based-cache-manipu.patch
deleted file mode 100644
index e0d12eb8b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0156-vcsm-Revert-to-do-page-table-walk-based-cache-manipu.patch
+++ /dev/null
@@ -1,235 +0,0 @@
-From 3e471b58fb766ed5b45ff8b560231da4704c946d Mon Sep 17 00:00:00 2001
-From: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
-Date: Wed, 10 Jan 2018 06:25:51 +0900
-Subject: [PATCH 156/454] vcsm: Revert to do page-table-walk-based cache
- manipulating on some ioctl calls
-
-On FLUSH, INVALID, CLEAN_INVALID ioctl calls, cache operations based on
-page table walk were used in case that the buffer of the cache is not
-pinned.  So reverted to do page-table-based cache manipulating.
-
-Signed-off-by: Sugizaki Yukimasa <i.can.speak.c.and.basic@gmail.com>
----
- drivers/char/broadcom/vc_sm/vmcs_sm.c | 141 ++++++++++++++++++++------
- 1 file changed, 110 insertions(+), 31 deletions(-)
-
---- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -1256,7 +1256,33 @@ static const struct vm_operations_struct
- 	.fault = vcsm_vma_fault,
- };
- 
--static int clean_invalid_mem_2d(const void __user *addr,
-+/* Converts VCSM_CACHE_OP_* to an operating function. */
-+static void (*cache_op_to_func(const unsigned cache_op))
-+		(const void*, const void*)
-+{
-+	switch (cache_op) {
-+	case VCSM_CACHE_OP_NOP:
-+		return NULL;
-+
-+	case VCSM_CACHE_OP_INV:
-+		return dmac_inv_range;
-+
-+	case VCSM_CACHE_OP_CLEAN:
-+		return dmac_clean_range;
-+
-+	case VCSM_CACHE_OP_FLUSH:
-+		return dmac_flush_range;
-+
-+	default:
-+		pr_err("[%s]: Invalid cache_op: 0x%08x\n", __func__, cache_op);
-+		return NULL;
-+	}
-+}
-+
-+/*
-+ * Clean/invalid/flush cache of which buffer is already pinned (i.e. accessed).
-+ */
-+static int clean_invalid_contiguous_mem_2d(const void __user *addr,
- 		const size_t block_count, const size_t block_size, const size_t stride,
- 		const unsigned cache_op)
- {
-@@ -1268,22 +1294,9 @@ static int clean_invalid_mem_2d(const vo
- 		return -EINVAL;
- 	}
- 
--	switch (cache_op) {
--	case VCSM_CACHE_OP_NOP:
--		return 0;
--	case VCSM_CACHE_OP_INV:
--		op_fn = dmac_inv_range;
--		break;
--	case VCSM_CACHE_OP_CLEAN:
--		op_fn = dmac_clean_range;
--		break;
--	case VCSM_CACHE_OP_FLUSH:
--		op_fn = dmac_flush_range;
--		break;
--	default:
--		pr_err("[%s]: Invalid cache_op: 0x%08x\n", __func__, cache_op);
-+	op_fn = cache_op_to_func(cache_op);
-+	if (op_fn == NULL)
- 		return -EINVAL;
--	}
- 
- 	for (i = 0; i < block_count; i ++, addr += stride)
- 		op_fn(addr, addr + block_size);
-@@ -1291,14 +1304,73 @@ static int clean_invalid_mem_2d(const vo
- 	return 0;
- }
- 
--static int clean_invalid_mem(const void __user *addr, const size_t size,
-+/* Clean/invalid/flush cache of which buffer may be non-pinned. */
-+/* The caller must lock current->mm->mmap_sem for read. */
-+static int clean_invalid_mem_walk(unsigned long addr, const size_t size,
- 		const unsigned cache_op)
- {
--	return clean_invalid_mem_2d(addr, 1, size, 0, cache_op);
-+	pgd_t *pgd;
-+	pud_t *pud;
-+	pmd_t *pmd;
-+	pte_t *pte;
-+	unsigned long pgd_next, pud_next, pmd_next;
-+	const unsigned long end = ALIGN(addr + size, PAGE_SIZE);
-+	void (*op_fn)(const void*, const void*);
-+
-+	addr &= PAGE_MASK;
-+
-+	if (addr >= end)
-+		return 0;
-+
-+	op_fn = cache_op_to_func(cache_op);
-+	if (op_fn == NULL)
-+		return -EINVAL;
-+
-+	/* Walk PGD */
-+	pgd = pgd_offset(current->mm, addr);
-+	do {
-+		pgd_next = pgd_addr_end(addr, end);
-+
-+		if (pgd_none(*pgd) || pgd_bad(*pgd))
-+			continue;
-+
-+		/* Walk PUD */
-+		pud = pud_offset(pgd, addr);
-+		do {
-+			pud_next = pud_addr_end(addr, pgd_next);
-+			if (pud_none(*pud) || pud_bad(*pud))
-+				continue;
-+
-+			/* Walk PMD */
-+			pmd = pmd_offset(pud, addr);
-+			do {
-+				pmd_next = pmd_addr_end(addr, pud_next);
-+				if (pmd_none(*pmd) || pmd_bad(*pmd))
-+					continue;
-+
-+				/* Walk PTE */
-+				pte = pte_offset_map(pmd, addr);
-+				do {
-+					if (pte_none(*pte) || !pte_present(*pte))
-+						continue;
-+
-+					op_fn((const void __user*) addr,
-+							(const void __user*) (addr + PAGE_SIZE));
-+				} while (pte++, addr += PAGE_SIZE, addr != pmd_next);
-+				pte_unmap(pte);
-+
-+			} while (pmd++, addr = pmd_next, addr != pud_next);
-+
-+		} while (pud++, addr = pud_next, addr != pgd_next);
-+
-+	} while (pgd++, addr = pgd_next, addr != end);
-+
-+	return 0;
- }
- 
--static int clean_invalid_resource(const void __user *addr, const size_t size,
--		const unsigned cache_op, const int usr_hdl,
-+/* Clean/invalid/flush cache of buffer in resource */
-+static int clean_invalid_resource_walk(const void __user *addr,
-+		const size_t size, const unsigned cache_op, const int usr_hdl,
- 		struct sm_resource_t *resource)
- {
- 	int err;
-@@ -1355,7 +1427,10 @@ static int clean_invalid_resource(const
- 		return -EFAULT;
- 	}
- 
--	err = clean_invalid_mem(addr, size, cache_op);
-+	down_read(&current->mm->mmap_sem);
-+	err = clean_invalid_mem_walk((unsigned long) addr, size, cache_op);
-+	up_read(&current->mm->mmap_sem);
-+
- 	if (err)
- 		resource->res_stats[stat_failure]++;
- 
-@@ -2004,7 +2079,7 @@ static int vc_sm_ioctl_unlock(struct sm_
- 					const unsigned long start = map->vma->vm_start;
- 					const unsigned long end = map->vma->vm_end;
- 
--					ret = clean_invalid_mem((void __user*) start, end - start,
-+					ret = clean_invalid_mem_walk(start, end - start,
- 							VCSM_CACHE_OP_FLUSH);
- 					if (ret)
- 						goto error;
-@@ -2886,7 +2961,7 @@ static long vc_sm_ioctl(struct file *fil
- 				goto out;
- 			}
- 
--			ret = clean_invalid_resource((void __user*) ioparam.addr,
-+			ret = clean_invalid_resource_walk((void __user*) ioparam.addr,
- 					ioparam.size, VCSM_CACHE_OP_FLUSH, ioparam.handle,
- 					resource);
- 			vmcs_sm_release_resource(resource, 0);
-@@ -2917,7 +2992,7 @@ static long vc_sm_ioctl(struct file *fil
- 				goto out;
- 			}
- 
--			ret = clean_invalid_resource((void __user*) ioparam.addr,
-+			ret = clean_invalid_resource_walk((void __user*) ioparam.addr,
- 					ioparam.size, VCSM_CACHE_OP_INV, ioparam.handle, resource);
- 			vmcs_sm_release_resource(resource, 0);
- 			if (ret)
-@@ -2951,16 +3026,19 @@ static long vc_sm_ioctl(struct file *fil
- 					goto out;
- 				}
- 
--				ret = clean_invalid_resource((void __user*) ioparam.s[i].addr,
--						ioparam.s[i].size, ioparam.s[i].cmd,
--						ioparam.s[i].handle, resource);
-+				ret = clean_invalid_resource_walk(
-+						(void __user*) ioparam.s[i].addr, ioparam.s[i].size,
-+						ioparam.s[i].cmd, ioparam.s[i].handle, resource);
- 				vmcs_sm_release_resource(resource, 0);
- 				if (ret)
- 					goto out;
- 			}
- 		}
- 		break;
--	/* Flush/Invalidate the cache for a given mapping. */
-+	/*
-+	 * Flush/Invalidate the cache for a given mapping.
-+	 * Blocks must be pinned (i.e. accessed) before this call.
-+	 */
- 	case VMCS_SM_CMD_CLEAN_INVALID2:
- 		{
- 				int i;
-@@ -2993,12 +3071,13 @@ static long vc_sm_ioctl(struct file *fil
- 				for (i = 0; i < ioparam.op_count; i++) {
- 					const struct vmcs_sm_ioctl_clean_invalid_block * const op = block + i;
- 
--					ret = clean_invalid_mem_2d((void __user*) op->start_address,
--							op->block_count, op->block_size,
--							op->inter_block_stride, op->invalidate_mode);
- 					if (op->invalidate_mode == VCSM_CACHE_OP_NOP)
- 						continue;
- 
-+					ret = clean_invalid_contiguous_mem_2d(
-+							(void __user*) op->start_address, op->block_count,
-+							op->block_size, op->inter_block_stride,
-+							op->invalidate_mode);
- 					if (ret)
- 						break;
- 				}
diff --git a/target/linux/brcm2708/patches-4.14/950-0157-add-gpio-key-overlay-2329.patch b/target/linux/brcm2708/patches-4.14/950-0157-add-gpio-key-overlay-2329.patch
deleted file mode 100644
index f486ece95..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0157-add-gpio-key-overlay-2329.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From e8a650fc27bf1e7d858c997fddd9944e6c222260 Mon Sep 17 00:00:00 2001
-From: Aaron Shaw <shawaj@gmail.com>
-Date: Thu, 4 Jan 2018 15:02:16 +0000
-Subject: [PATCH 157/454] add gpio-key overlay (#2329)
-
-An overlay that allows a Linux key to be bound to a GPIO.
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             | 21 ++++++++
- .../boot/dts/overlays/gpio-key-overlay.dts    | 48 +++++++++++++++++++
- 3 files changed, 70 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/gpio-key-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -31,6 +31,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	googlevoicehat-soundcard.dtbo \
- 	gpio-ir.dtbo \
- 	gpio-ir-tx.dtbo \
-+	gpio-key.dtbo \
- 	gpio-poweroff.dtbo \
- 	gpio-shutdown.dtbo \
- 	hifiberry-amp.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -515,6 +515,27 @@ Params: gpio_pin                Output G
-                                 Default is "0" (active-high).
- 
- 
-+Name:   gpio-key
-+Info:   This is a generic overlay for activating GPIO keypresses using
-+        the gpio-keys library and this dtoverlay. Multiple keys can be
-+        set up using multiple calls to the overlay for configuring
-+        additional buttons or joysticks. You can see available keycodes
-+        at https://github.com/torvalds/linux/blob/v4.12/include/uapi/
-+        linux/input-event-codes.h#L64
-+Load:   dtoverlay=gpio-key,<param>=<val>
-+Params: gpio                    GPIO pin to trigger on (default 3)
-+        active_low              When this is 1 (active low), a falling
-+                                edge generates a key down event and a
-+                                rising edge generates a key up event.
-+                                When this is 0 (active high), this is
-+                                reversed. The default is 1 (active low)
-+        gpio_pull               Desired pull-up/down state (off, down, up)
-+                                Default is "up". Note that the default pin
-+                                (GPIO3) has an external pullup
-+        label                   Set a label for the key
-+        keycode                 Set the key code for the button
-+
-+
- Name:   gpio-poweroff
- Info:   Drives a GPIO high or low on poweroff (including halt). Enabling this
-         overlay will prevent the ability to boot by driving GPIO3 low.
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/gpio-key-overlay.dts
-@@ -0,0 +1,48 @@
-+// Definitions for gpio-key module
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		// Configure the gpio pin controller
-+		target = <&gpio>;
-+		__overlay__ {
-+			pin_state: button_pins@0 {
-+				brcm,pins = <3>; // gpio number
-+				brcm,function = <0>; // 0 = input, 1 = output
-+				brcm,pull = <2>; // 0 = none, 1 = pull down, 2 = pull up
-+			};
-+		};
-+	};
-+	fragment@1 {
-+		target-path = "/";
-+		__overlay__ {
-+			button: button@0 {
-+				compatible = "gpio-keys";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&pin_state>;
-+				status = "okay";
-+
-+				key: key {
-+					linux,code = <116>;
-+					gpios = <&gpio 3 1>;
-+					label = "KEY_POWER";
-+				};
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		gpio =       <&key>,"gpios:4",
-+		             <&button>,"reg:0",
-+		             <&pin_state>,"brcm,pins:0",
-+		             <&pin_state>,"reg:0";
-+		label =      <&key>,"label";
-+		keycode =    <&key>,"linux,code:0";
-+		gpio_pull =  <&pin_state>,"brcm,pull:0";
-+		active_low = <&key>,"gpios:8";
-+	};
-+
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0158-add-additional-overrides-to-rotary-encoder-overlay-2.patch b/target/linux/brcm2708/patches-4.14/950-0158-add-additional-overrides-to-rotary-encoder-overlay-2.patch
deleted file mode 100644
index 003af7d93..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0158-add-additional-overrides-to-rotary-encoder-overlay-2.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 8cf805e57fa5cf4c872883968def037cd7c903cc Mon Sep 17 00:00:00 2001
-From: Aaron Shaw <shawaj@gmail.com>
-Date: Fri, 5 Jan 2018 15:08:37 +0000
-Subject: [PATCH 158/454] add additional overrides to rotary-encoder overlay
- (#2334)
-
----
- arch/arm/boot/dts/overlays/README             | 23 +++++++++++++++++++
- .../dts/overlays/rotary-encoder-overlay.dts   | 18 +++++++++++----
- 2 files changed, 36 insertions(+), 5 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1331,6 +1331,29 @@ Params: rotary0_pin_a           GPIO con
-                                 (default 4).
-         rotary0_pin_b           GPIO connected to rotary encoder channel B
-                                 (default 17).
-+        relative_axis           register a relative axis rather than an
-+                                absolute one. Relative axis will only
-+                                generate +1/-1 events on the input device,
-+                                hence no steps need to be passed.
-+        linux_axis              the input subsystem axis to map to this
-+                                rotary encoder. Defaults to 0 (ABS_X / REL_X)
-+        rollover                Automatic rollover when the rotary value
-+                                becomes greater than the specified steps or
-+                                smaller than 0. For absolute axis only.
-+        steps-per-period        Number of steps (stable states) per period.
-+                                The values have the following meaning:
-+                                1: Full-period mode (default)
-+                                2: Half-period mode
-+                                4: Quarter-period mode
-+        steps                   Number of steps in a full turnaround of the
-+                                encoder. Only relevant for absolute axis.
-+                                Defaults to 24 which is a typical value for
-+                                such devices.
-+        wakeup                  Boolean, rotary encoder can wake up the
-+                                system.
-+        encoding                String, the method used to encode steps.
-+                                Supported are "gray" (the default and more
-+                                common) and "binary".
- 
- 
- Name:   rpi-backlight
---- a/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts
-@@ -28,16 +28,24 @@
- 					gpios = <&gpio 4 0>, <&gpio 17 0>;
- 					linux,axis = <0>; /* REL_X */
- 					rotary-encoder,encoding = "gray";
--					rotary-encoder,relative-axis;
-+					rotary-encoder,steps = <24>; /* 24 default */
-+					rotary-encoder,steps-per-period = <1>; /* corresponds to full period mode. See README */
- 			};
- 		};
- 
- 	};  
- 
- 	__overrides__ {
--		rotary0_pin_a = <&rotary0>,"gpios:4",
--				<&rotary0_pins>,"brcm,pins:0";
--		rotary0_pin_b = <&rotary0>,"gpios:16",
--				<&rotary0_pins>,"brcm,pins:4";
-+		rotary0_pin_a =     <&rotary0>,"gpios:4",
-+		                    <&rotary0_pins>,"brcm,pins:0";
-+		rotary0_pin_b =     <&rotary0>,"gpios:16",
-+		                    <&rotary0_pins>,"brcm,pins:4";
-+		relative_axis =     <&rotary0>,"rotary-encoder,relative-axis?";
-+		linux_axis =        <&rotary0>,"linux,axis:0";
-+		rollover =          <&rotary0>,"rotary-encoder,rollover?";
-+		steps-per-period =  <&rotary0>,"rotary-encoder,steps-per-period:0";
-+		steps =             <&rotary0>,"rotary-encoder,steps:0";
-+		wakeup =            <&rotary0>,"wakeup-source?";
-+		encoding =          <&rotary0>,"rotary-encoder,encoding";
- 	};  
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0159-overlays-Add-uart0-overlay-to-change-pin-usage.patch b/target/linux/brcm2708/patches-4.14/950-0159-overlays-Add-uart0-overlay-to-change-pin-usage.patch
deleted file mode 100644
index a2a30e905..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0159-overlays-Add-uart0-overlay-to-change-pin-usage.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From f0f4af3ddb0fc5ea529c0147ebf8be47b1a80335 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 12 Jan 2018 09:15:01 +0000
-Subject: [PATCH 159/454] overlays: Add uart0 overlay to change pin usage
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile          |  1 +
- arch/arm/boot/dts/overlays/README            | 13 +++++++-
- arch/arm/boot/dts/overlays/uart0-overlay.dts | 32 ++++++++++++++++++++
- 3 files changed, 45 insertions(+), 1 deletion(-)
- create mode 100755 arch/arm/boot/dts/overlays/uart0-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -117,6 +117,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	spi2-2cs.dtbo \
- 	spi2-3cs.dtbo \
- 	tinylcd35.dtbo \
-+	uart0.dtbo \
- 	uart1.dtbo \
- 	vc4-fkms-v3d.dtbo \
- 	vc4-kms-v3d.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1671,8 +1671,19 @@ Params: speed                   Display
-                 dtoverlay=tinylcd35,touch,touchgpio=3
- 
- 
-+Name:   uart0
-+Info:   Change the pin usage of uart0
-+Load:   dtoverlay=uart0,<param>=<val>
-+Params: txd0_pin                GPIO pin for TXD0 (14, 32 or 36 - default 14)
-+
-+        rxd0_pin                GPIO pin for RXD0 (15, 33 or 37 - default 15)
-+
-+        pin_func                Alternative pin function - 4(Alt0) for 14&15,
-+                                7(Alt3) for 32&33, 6(Alt2) for 36&37
-+
-+
- Name:   uart1
--Info:   Enable uart1 in place of uart0
-+Info:   Change the pin usage of uart1
- Load:   dtoverlay=uart1,<param>=<val>
- Params: txd1_pin                GPIO pin for TXD1 (14, 32 or 40 - default 14)
- 
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/uart0-overlay.dts
-@@ -0,0 +1,32 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&uart0>;
-+		__overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&uart0_pins>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			uart0_pins: uart0_pins {
-+				brcm,pins = <14 15>;
-+				brcm,function = <4>; /* alt0 */
-+				brcm,pull = <0 2>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		txd0_pin = <&uart0_pins>,"brcm,pins:0";
-+		rxd0_pin = <&uart0_pins>,"brcm,pins:4";
-+		pin_func = <&uart0_pins>,"brcm,function:0";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0160-overlays-Fix-resetgpio-and-ledgpio-for-hy28a-b.patch b/target/linux/brcm2708/patches-4.14/950-0160-overlays-Fix-resetgpio-and-ledgpio-for-hy28a-b.patch
deleted file mode 100644
index c740d7fa4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0160-overlays-Fix-resetgpio-and-ledgpio-for-hy28a-b.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From c912fa6af8ed1452717a4754960f328b6fc09ff0 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 16 Jan 2018 12:59:17 +0000
-Subject: [PATCH 160/454] overlays: Fix resetgpio and ledgpio for hy28a/b
-
-Offsets for overlay parameters are specified in bytes, not in access
-units.
-
-See: https://github.com/raspberrypi/linux/issues/2344
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/hy28a-overlay.dts | 4 ++--
- arch/arm/boot/dts/overlays/hy28b-overlay.dts | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/hy28a-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/hy28a-overlay.dts
-@@ -86,8 +86,8 @@
- 		debug =		<&hy28a>,"debug:0";
- 		xohms =		<&hy28a_ts>,"ti,x-plate-ohms;0";
- 		resetgpio =	<&hy28a>,"reset-gpios:4",
--				<&hy28a_pins>, "brcm,pins:1";
-+				<&hy28a_pins>, "brcm,pins:4";
- 		ledgpio =	<&hy28a>,"led-gpios:4",
--				<&hy28a_pins>, "brcm,pins:2";
-+				<&hy28a_pins>, "brcm,pins:8";
- 	};
- };
---- a/arch/arm/boot/dts/overlays/hy28b-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/hy28b-overlay.dts
-@@ -141,8 +141,8 @@
- 		debug = 	<&hy28b>,"debug:0";
- 		xohms =		<&hy28b_ts>,"ti,x-plate-ohms;0";
- 		resetgpio =	<&hy28b>,"reset-gpios:4",
--				<&hy28b_pins>, "brcm,pins:1";
-+				<&hy28b_pins>, "brcm,pins:4";
- 		ledgpio =	<&hy28b>,"led-gpios:4",
--				<&hy28b_pins>, "brcm,pins:2";
-+				<&hy28b_pins>, "brcm,pins:8";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0161-ASoC-bcm2835-fix-hw_params-error-when-device-is-in-p.patch b/target/linux/brcm2708/patches-4.14/950-0161-ASoC-bcm2835-fix-hw_params-error-when-device-is-in-p.patch
deleted file mode 100644
index e94199288..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0161-ASoC-bcm2835-fix-hw_params-error-when-device-is-in-p.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 0f409e6c30a04eb85792a6883e81ad2af118c7bd Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <github@hias.horus.com>
-Date: Thu, 18 Jan 2018 12:36:44 +0100
-Subject: [PATCH 161/454] ASoC: bcm2835: fix hw_params error when device is in
- prepared state (#2345)
-
-commit 8d5737a5f53902a916ee1e1cb248c9b8b883b2ea  upstream.
-
-If bcm2835 is configured as bitclock master calling hw_params()
-after prepare() fails with EBUSY. This also makes it impossible to
-use bcm2835 in full duplex mode.
-
-The error is caused by the split clock setup: clk_set_rate
-is called in hw_params, clk_prepare_enable in prepare. As hw_params
-doesn't check if the clock was already enabled clk_set_rate
-fails with EBUSY.
-
-Fix this by moving clock startup from prepare to hw_params and
-let hw_params properly deal with an already set up or enabled
-clock.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/bcm2835-i2s.c | 20 ++++++++++++++------
- 1 file changed, 14 insertions(+), 6 deletions(-)
-
---- a/sound/soc/bcm/bcm2835-i2s.c
-+++ b/sound/soc/bcm/bcm2835-i2s.c
-@@ -130,6 +130,7 @@ struct bcm2835_i2s_dev {
- 	struct regmap				*i2s_regmap;
- 	struct clk				*clk;
- 	bool					clk_prepared;
-+	int					clk_rate;
- };
- 
- static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
-@@ -419,10 +420,19 @@ static int bcm2835_i2s_hw_params(struct
- 	}
- 
- 	/* Clock should only be set up here if CPU is clock master */
--	if (bit_clock_master) {
--		ret = clk_set_rate(dev->clk, bclk_rate);
--		if (ret)
--			return ret;
-+	if (bit_clock_master &&
-+	    (!dev->clk_prepared || dev->clk_rate != bclk_rate)) {
-+		if (dev->clk_prepared)
-+			bcm2835_i2s_stop_clock(dev);
-+
-+		if (dev->clk_rate != bclk_rate) {
-+			ret = clk_set_rate(dev->clk, bclk_rate);
-+			if (ret)
-+				return ret;
-+			dev->clk_rate = bclk_rate;
-+		}
-+
-+		bcm2835_i2s_start_clock(dev);
- 	}
- 
- 	/* Setup the frame format */
-@@ -618,8 +628,6 @@ static int bcm2835_i2s_prepare(struct sn
- 	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
- 	uint32_t cs_reg;
- 
--	bcm2835_i2s_start_clock(dev);
--
- 	/*
- 	 * Clear both FIFOs if the one that should be started
- 	 * is not empty at the moment. This should only happen
diff --git a/target/linux/brcm2708/patches-4.14/950-0162-Input-add-I2C-attached-EETI-EXC3000-multi-touch-driv.patch b/target/linux/brcm2708/patches-4.14/950-0162-Input-add-I2C-attached-EETI-EXC3000-multi-touch-driv.patch
deleted file mode 100644
index 033039e5c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0162-Input-add-I2C-attached-EETI-EXC3000-multi-touch-driv.patch
+++ /dev/null
@@ -1,320 +0,0 @@
-From 99aaee7d1fde86bd2119d84e90435d89d6d3af07 Mon Sep 17 00:00:00 2001
-From: Ahmet Inan <inan@distec.de>
-Date: Sat, 14 Oct 2017 10:10:53 -0700
-Subject: [PATCH 162/454] Input: add I2C attached EETI EXC3000 multi touch
- driver
-
-commit 7e577a17f2eefeef32f1106ebf91e7cd143ba654 upstream.
-beware: code adapted to use the old timer API.
-
-The 3000 series have a new protocol which allows to report up to 5 points
-in a single 66 byte frame. One must always read in 66 byte frames.
-To support up to 10 points, two consecutive frames need to be read:
-The first frame says how many points until sync.
-The second frame must say zero points or both frames must be discarded.
-
-To be able to work with the higher 400KHz I2C bus rate, one must
-successfully send a special package prior _each_ read or the controller
-will refuse to cooperate.
-
-This is a minimal implementation based on egalax_i2c.c (which can be found
-on the internet) and egalax_ts.c but without the vendor interface and no
-power management support.
-
-Signed-off-by: Ahmet Inan <inan@distec.de>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
----
- .../bindings/input/touchscreen/exc3000.txt    |  27 +++
- drivers/input/touchscreen/Kconfig             |  10 +
- drivers/input/touchscreen/Makefile            |   1 +
- drivers/input/touchscreen/exc3000.c           | 223 ++++++++++++++++++
- 4 files changed, 261 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/input/touchscreen/exc3000.txt
- create mode 100644 drivers/input/touchscreen/exc3000.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/input/touchscreen/exc3000.txt
-@@ -0,0 +1,27 @@
-+* EETI EXC3000 Multiple Touch Controller
-+
-+Required properties:
-+- compatible: must be "eeti,exc3000"
-+- reg: i2c slave address
-+- interrupt-parent: the phandle for the interrupt controller
-+- interrupts: touch controller interrupt
-+- touchscreen-size-x: See touchscreen.txt
-+- touchscreen-size-y: See touchscreen.txt
-+
-+Optional properties:
-+- touchscreen-inverted-x: See touchscreen.txt
-+- touchscreen-inverted-y: See touchscreen.txt
-+- touchscreen-swapped-x-y: See touchscreen.txt
-+
-+Example:
-+
-+	touchscreen@2a {
-+		compatible = "eeti,exc3000";
-+		reg = <0x2a>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
-+		touchscreen-size-x = <4096>;
-+		touchscreen-size-y = <4096>;
-+		touchscreen-inverted-x;
-+		touchscreen-swapped-x-y;
-+	};
---- a/drivers/input/touchscreen/Kconfig
-+++ b/drivers/input/touchscreen/Kconfig
-@@ -316,6 +316,16 @@ config TOUCHSCREEN_EGALAX_SERIAL
- 	  To compile this driver as a module, choose M here: the
- 	  module will be called egalax_ts_serial.
- 
-+config TOUCHSCREEN_EXC3000
-+	tristate "EETI EXC3000 multi-touch panel support"
-+	depends on I2C
-+	help
-+	  Say Y here to enable support for I2C connected EETI
-+	  EXC3000 multi-touch panels.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called exc3000.
-+
- config TOUCHSCREEN_FUJITSU
- 	tristate "Fujitsu serial touchscreen"
- 	select SERIO
---- a/drivers/input/touchscreen/Makefile
-+++ b/drivers/input/touchscreen/Makefile
-@@ -39,6 +39,7 @@ obj-$(CONFIG_TOUCHSCREEN_ELAN)		+= elant
- obj-$(CONFIG_TOUCHSCREEN_ELO)		+= elo.o
- obj-$(CONFIG_TOUCHSCREEN_EGALAX)	+= egalax_ts.o
- obj-$(CONFIG_TOUCHSCREEN_EGALAX_SERIAL)	+= egalax_ts_serial.o
-+obj-$(CONFIG_TOUCHSCREEN_EXC3000)	+= exc3000.o
- obj-$(CONFIG_TOUCHSCREEN_FUJITSU)	+= fujitsu_ts.o
- obj-$(CONFIG_TOUCHSCREEN_GOODIX)	+= goodix.o
- obj-$(CONFIG_TOUCHSCREEN_ILI210X)	+= ili210x.o
---- /dev/null
-+++ b/drivers/input/touchscreen/exc3000.c
-@@ -0,0 +1,223 @@
-+/*
-+ * Driver for I2C connected EETI EXC3000 multiple touch controller
-+ *
-+ * Copyright (C) 2017 Ahmet Inan <inan@distec.de>
-+ *
-+ * minimal implementation based on egalax_ts.c and egalax_i2c.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/bitops.h>
-+#include <linux/device.h>
-+#include <linux/i2c.h>
-+#include <linux/input.h>
-+#include <linux/input/mt.h>
-+#include <linux/input/touchscreen.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/timer.h>
-+#include <asm/unaligned.h>
-+
-+#define EXC3000_NUM_SLOTS		10
-+#define EXC3000_SLOTS_PER_FRAME		5
-+#define EXC3000_LEN_FRAME		66
-+#define EXC3000_LEN_POINT		10
-+#define EXC3000_MT_EVENT		6
-+#define EXC3000_TIMEOUT_MS		100
-+
-+struct exc3000_data {
-+	struct i2c_client *client;
-+	struct input_dev *input;
-+	struct touchscreen_properties prop;
-+	struct timer_list timer;
-+	u8 buf[2 * EXC3000_LEN_FRAME];
-+};
-+
-+static void exc3000_report_slots(struct input_dev *input,
-+				 struct touchscreen_properties *prop,
-+				 const u8 *buf, int num)
-+{
-+	for (; num--; buf += EXC3000_LEN_POINT) {
-+		if (buf[0] & BIT(0)) {
-+			input_mt_slot(input, buf[1]);
-+			input_mt_report_slot_state(input, MT_TOOL_FINGER, true);
-+			touchscreen_report_pos(input, prop,
-+					       get_unaligned_le16(buf + 2),
-+					       get_unaligned_le16(buf + 4),
-+					       true);
-+		}
-+	}
-+}
-+
-+static void exc3000_timer(unsigned long d)
-+{
-+	struct exc3000_data *data = (void *)d;
-+
-+	input_mt_sync_frame(data->input);
-+	input_sync(data->input);
-+}
-+
-+static int exc3000_read_frame(struct i2c_client *client, u8 *buf)
-+{
-+	int ret;
-+
-+	ret = i2c_master_send(client, "'", 2);
-+	if (ret < 0)
-+		return ret;
-+
-+	if (ret != 2)
-+		return -EIO;
-+
-+	ret = i2c_master_recv(client, buf, EXC3000_LEN_FRAME);
-+	if (ret < 0)
-+		return ret;
-+
-+	if (ret != EXC3000_LEN_FRAME)
-+		return -EIO;
-+
-+	if (get_unaligned_le16(buf) != EXC3000_LEN_FRAME ||
-+			buf[2] != EXC3000_MT_EVENT)
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int exc3000_read_data(struct i2c_client *client,
-+			     u8 *buf, int *n_slots)
-+{
-+	int error;
-+
-+	error = exc3000_read_frame(client, buf);
-+	if (error)
-+		return error;
-+
-+	*n_slots = buf[3];
-+	if (!*n_slots || *n_slots > EXC3000_NUM_SLOTS)
-+		return -EINVAL;
-+
-+	if (*n_slots > EXC3000_SLOTS_PER_FRAME) {
-+		/* Read 2nd frame to get the rest of the contacts. */
-+		error = exc3000_read_frame(client, buf + EXC3000_LEN_FRAME);
-+		if (error)
-+			return error;
-+
-+		/* 2nd chunk must have number of contacts set to 0. */
-+		if (buf[EXC3000_LEN_FRAME + 3] != 0)
-+			return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static irqreturn_t exc3000_interrupt(int irq, void *dev_id)
-+{
-+	struct exc3000_data *data = dev_id;
-+	struct input_dev *input = data->input;
-+	u8 *buf = data->buf;
-+	int slots, total_slots;
-+	int error;
-+
-+	error = exc3000_read_data(data->client, buf, &total_slots);
-+	if (error) {
-+		/* Schedule a timer to release "stuck" contacts */
-+		mod_timer(&data->timer,
-+			  jiffies + msecs_to_jiffies(EXC3000_TIMEOUT_MS));
-+		goto out;
-+	}
-+
-+	/*
-+	 * We read full state successfully, no contacts will be "stuck".
-+	 */
-+	del_timer_sync(&data->timer);
-+
-+	while (total_slots > 0) {
-+		slots = min(total_slots, EXC3000_SLOTS_PER_FRAME);
-+		exc3000_report_slots(input, &data->prop, buf + 4, slots);
-+		total_slots -= slots;
-+		buf += EXC3000_LEN_FRAME;
-+	}
-+
-+	input_mt_sync_frame(input);
-+	input_sync(input);
-+
-+out:
-+	return IRQ_HANDLED;
-+}
-+
-+static int exc3000_probe(struct i2c_client *client,
-+			 const struct i2c_device_id *id)
-+{
-+	struct exc3000_data *data;
-+	struct input_dev *input;
-+	int error;
-+
-+	data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
-+	if (!data)
-+		return -ENOMEM;
-+
-+	data->client = client;
-+	setup_timer(&data->timer, exc3000_timer, (unsigned long)data);
-+
-+	input = devm_input_allocate_device(&client->dev);
-+	if (!input)
-+		return -ENOMEM;
-+
-+	data->input = input;
-+
-+	input->name = "EETI EXC3000 Touch Screen";
-+	input->id.bustype = BUS_I2C;
-+
-+	input_set_abs_params(input, ABS_MT_POSITION_X, 0, 4095, 0, 0);
-+	input_set_abs_params(input, ABS_MT_POSITION_Y, 0, 4095, 0, 0);
-+	touchscreen_parse_properties(input, true, &data->prop);
-+
-+	error = input_mt_init_slots(input, EXC3000_NUM_SLOTS,
-+				    INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED);
-+	if (error)
-+		return error;
-+
-+	error = input_register_device(input);
-+	if (error)
-+		return error;
-+
-+	error = devm_request_threaded_irq(&client->dev, client->irq,
-+					  NULL, exc3000_interrupt, IRQF_ONESHOT,
-+					  client->name, data);
-+	if (error)
-+		return error;
-+
-+	return 0;
-+}
-+
-+static const struct i2c_device_id exc3000_id[] = {
-+	{ "exc3000", 0 },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(i2c, exc3000_id);
-+
-+#ifdef CONFIG_OF
-+static const struct of_device_id exc3000_of_match[] = {
-+	{ .compatible = "eeti,exc3000" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, exc3000_of_match);
-+#endif
-+
-+static struct i2c_driver exc3000_driver = {
-+	.driver = {
-+		.name	= "exc3000",
-+		.of_match_table = of_match_ptr(exc3000_of_match),
-+	},
-+	.id_table	= exc3000_id,
-+	.probe		= exc3000_probe,
-+};
-+
-+module_i2c_driver(exc3000_driver);
-+
-+MODULE_AUTHOR("Ahmet Inan <inan@distec.de>");
-+MODULE_DESCRIPTION("I2C connected EETI EXC3000 multiple touch controller driver");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0163-config-Add-EETI-EXC3000-touch-controller-module.patch b/target/linux/brcm2708/patches-4.14/950-0163-config-Add-EETI-EXC3000-touch-controller-module.patch
deleted file mode 100644
index 449e7d26e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0163-config-Add-EETI-EXC3000-touch-controller-module.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 4f804765c7bc86b7b622c268aa36f872fdad8f5c Mon Sep 17 00:00:00 2001
-From: Ahmet Inan <inan@aicodix.de>
-Date: Fri, 1 Sep 2017 15:14:23 +0200
-Subject: [PATCH 163/454] config: Add EETI EXC3000 touch controller module
-
-Signed-off-by: Ahmet Inan <inan@aicodix.de>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -554,6 +554,7 @@ CONFIG_JOYSTICK_RPISENSE=m
- CONFIG_INPUT_TOUCHSCREEN=y
- CONFIG_TOUCHSCREEN_ADS7846=m
- CONFIG_TOUCHSCREEN_EGALAX=m
-+CONFIG_TOUCHSCREEN_EXC3000=m
- CONFIG_TOUCHSCREEN_GOODIX=m
- CONFIG_TOUCHSCREEN_EDT_FT5X06=m
- CONFIG_TOUCHSCREEN_RPI_FT5406=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -549,6 +549,7 @@ CONFIG_JOYSTICK_RPISENSE=m
- CONFIG_INPUT_TOUCHSCREEN=y
- CONFIG_TOUCHSCREEN_ADS7846=m
- CONFIG_TOUCHSCREEN_EGALAX=m
-+CONFIG_TOUCHSCREEN_EXC3000=m
- CONFIG_TOUCHSCREEN_GOODIX=m
- CONFIG_TOUCHSCREEN_EDT_FT5X06=m
- CONFIG_TOUCHSCREEN_RPI_FT5406=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0164-overlays-Add-EETI-EXC3000-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0164-overlays-Add-EETI-EXC3000-overlay.patch
deleted file mode 100644
index 9db3667b1..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0164-overlays-Add-EETI-EXC3000-overlay.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From e141a75b9cc36a09eb8bda90b530d97a9bb1f21e Mon Sep 17 00:00:00 2001
-From: Ahmet Inan <inan@aicodix.de>
-Date: Fri, 1 Sep 2017 15:18:01 +0200
-Subject: [PATCH 164/454] overlays: Add EETI EXC3000 overlay
-
-Add support for I2C connected EETI EXC3000 multiple touch controller
-using GPIO 4 (pin 7 on GPIO header) for interrupt.
-
-Signed-off-by: Ahmet Inan <inan@aicodix.de>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             | 12 +++++
- .../arm/boot/dts/overlays/exc3000-overlay.dts | 48 +++++++++++++++++++
- 3 files changed, 61 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/exc3000-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -26,6 +26,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	dwc2.dtbo \
- 	enc28j60.dtbo \
- 	enc28j60-spi2.dtbo \
-+	exc3000.dtbo \
- 	fe-pi-audio.dtbo \
- 	goodix.dtbo \
- 	googlevoicehat-soundcard.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -468,6 +468,18 @@ Params: int_pin                 GPIO use
-         speed                   SPI bus speed (default 12000000)
- 
- 
-+Name:   exc3000
-+Info:   Enables I2C connected EETI EXC3000 multiple touch controller using
-+        GPIO 4 (pin 7 on GPIO header) for interrupt.
-+Load:   dtoverlay=exc3000,<param>=<val>
-+Params: interrupt               GPIO used for interrupt (default 4)
-+        sizex                   Touchscreen size x (default 4096)
-+        sizey                   Touchscreen size y (default 4096)
-+        invx                    Touchscreen inverted x axis
-+        invy                    Touchscreen inverted y axis
-+        swapxy                  Touchscreen swapped x y axis
-+
-+
- Name:   fe-pi-audio
- Info:   Configures the Fe-Pi Audio Sound Card
- Load:   dtoverlay=fe-pi-audio
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/exc3000-overlay.dts
-@@ -0,0 +1,48 @@
-+// Device tree overlay for I2C connected EETI EXC3000 multiple touch controller
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			exc3000_pins: exc3000_pins {
-+				brcm,pins = <4>; // interrupt
-+				brcm,function = <0>; // in
-+				brcm,pull = <2>; // pull-up
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			exc3000: exc3000@2a {
-+				compatible = "eeti,exc3000";
-+				reg = <0x2a>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&exc3000_pins>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <4 8>; // active low level-sensitive
-+				touchscreen-size-x = <4096>;
-+				touchscreen-size-y = <4096>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		interrupt = <&exc3000_pins>,"brcm,pins:0",
-+			<&exc3000>,"interrupts:0";
-+		sizex = <&exc3000>,"touchscreen-size-x:0";
-+		sizey = <&exc3000>,"touchscreen-size-y:0";
-+		invx = <&exc3000>,"touchscreen-inverted-x?";
-+		invy = <&exc3000>,"touchscreen-inverted-y?";
-+		swapxy = <&exc3000>,"touchscreen-swapped-x-y?";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0165-Added-support-for-mbed-AudioCODEC-TLV320AIC23B.patch b/target/linux/brcm2708/patches-4.14/950-0165-Added-support-for-mbed-AudioCODEC-TLV320AIC23B.patch
deleted file mode 100644
index 582e2368e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0165-Added-support-for-mbed-AudioCODEC-TLV320AIC23B.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From 921c7f42c3ed6cebea4edff86bbe2b6c1b882d53 Mon Sep 17 00:00:00 2001
-From: Yevhen Kyriukha <kirgene@gmail.com>
-Date: Sun, 14 Jan 2018 13:36:24 +0200
-Subject: [PATCH 165/454] Added support for mbed AudioCODEC (TLV320AIC23B)
-
-Signed-off-by: Yevhen Kyriukha <kirgene@gmail.com>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  6 ++
- .../boot/dts/overlays/mbed-dac-overlay.dts    | 64 +++++++++++++++++++
- 3 files changed, 71 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/mbed-dac-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -58,6 +58,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	justboom-dac.dtbo \
- 	justboom-digi.dtbo \
- 	lirc-rpi.dtbo \
-+	mbed-dac.dtbo \
- 	mcp23017.dtbo \
- 	mcp23s17.dtbo \
- 	mcp2515-can0.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -965,6 +965,12 @@ Params: gpio_out_pin            GPIO for
-                                 (default "off")
- 
- 
-+Name:   mbed-dac
-+Info:   Configures the mbed AudioCODEC (TLV320AIC23B)
-+Load:   dtoverlay=mbed-dac
-+Params: <None>
-+
-+
- Name:   mcp23017
- Info:   Configures the MCP23017 I2C GPIO expander
- Load:   dtoverlay=mcp23017,<param>=<val>
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts
-@@ -0,0 +1,64 @@
-+// Definitions for mbed DAC
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+                        #size-cells = <0>;
-+			status = "okay";
-+
-+			tlv320aic23: codec@1a {
-+				#sound-dai-cells = <0>;
-+				reg = <0x1a>;
-+				compatible = "ti,tlv320aic23";
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "simple-audio-card";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+
-+			simple-audio-card,name = "mbed-DAC";
-+
-+			simple-audio-card,widgets =
-+				"Microphone", "Mic Jack",
-+				"Line", "Line In",
-+				"Headphone", "Headphone Jack";
-+
-+			simple-audio-card,routing =
-+				"Headphone Jack", "LHPOUT",
-+				"Headphone Jack", "RHPOUT",
-+				"LLINEIN", "Line In",
-+				"RLINEIN", "Line In",
-+				"MICIN", "Mic Jack";
-+
-+			simple-audio-card,format = "i2s";
-+
-+			simple-audio-card,cpu {
-+				sound-dai = <&i2s>;
-+			};
-+
-+			sound_master: simple-audio-card,codec {
-+				sound-dai = <&tlv320aic23>;
-+				system-clock-frequency = <12288000>;
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0166-mmc-bcm2835-sdhost-Support-underclocking.patch b/target/linux/brcm2708/patches-4.14/950-0166-mmc-bcm2835-sdhost-Support-underclocking.patch
deleted file mode 100644
index feca38df3..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0166-mmc-bcm2835-sdhost-Support-underclocking.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From c03a6b0585e7c469c199d349405b3967bcf18672 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 22 Jan 2018 12:17:27 +0000
-Subject: [PATCH 166/454] mmc: bcm2835-sdhost: Support underclocking
-
-Support underclocking of the SD bus in two ways:
-1. using the max-frequency DT property (which currently has no DT
-   parameter), and
-2. using the exiting sd_overclock parameter.
-
-The two methods differ slightly - in the former the MMC subsystem is
-aware of the underclocking, while in the latter it isn't - but the
-end results should be the same.
-
-See: https://github.com/raspberrypi/linux/issues/2350
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/mmc/host/bcm2835-sdhost.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/mmc/host/bcm2835-sdhost.c
-+++ b/drivers/mmc/host/bcm2835-sdhost.c
-@@ -1519,8 +1519,7 @@ void bcm2835_sdhost_set_clock(struct bcm
- 	if (host->debug)
- 		pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock);
- 
--	if ((host->overclock_50 > 50) &&
--	    (clock == 50*MHZ))
-+	if (host->overclock_50 && (clock == 50*MHZ))
- 		clock = host->overclock_50 * MHZ + (MHZ - 1);
- 
- 	/* The SDCDIV register has 11 bits, and holds (div - 2).
-@@ -1894,7 +1893,8 @@ int bcm2835_sdhost_add_host(struct bcm28
- 
- 	mmc = host->mmc;
- 
--	mmc->f_max = host->max_clk;
-+	if (!mmc->f_max || mmc->f_max > host->max_clk)
-+		mmc->f_max = host->max_clk;
- 	mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
- 
- 	mmc->max_busy_timeout =  (~(unsigned int)0)/(mmc->f_max/1000);
diff --git a/target/linux/brcm2708/patches-4.14/950-0167-mmc-bcm2835-mmc-Support-underclocking.patch b/target/linux/brcm2708/patches-4.14/950-0167-mmc-bcm2835-mmc-Support-underclocking.patch
deleted file mode 100644
index c0b18c7f4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0167-mmc-bcm2835-mmc-Support-underclocking.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 9cd69b8f61edc246563741cd11d01fa911cd7e91 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 22 Jan 2018 12:22:01 +0000
-Subject: [PATCH 167/454] mmc: bcm2835-mmc: Support underclocking
-
-Support underclocking of the SD bus using the max-frequency DT property
-(which currently has no DT parameter). The sd_overclock parameter
-already provides another way to achieve the same thing which should be
-equivalent in end result, but it is a bug not to support max-frequency
-as well.
-
-See: https://github.com/raspberrypi/linux/issues/2350
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/mmc/host/bcm2835-mmc.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/mmc/host/bcm2835-mmc.c
-+++ b/drivers/mmc/host/bcm2835-mmc.c
-@@ -1310,8 +1310,8 @@ static int bcm2835_mmc_add_host(struct b
- 
- 	host->clk_mul = 0;
- 
--	mmc->f_max = host->max_clk;
--	mmc->f_max = host->max_clk;
-+	if (!mmc->f_max || mmc->f_max > host->max_clk)
-+		mmc->f_max = host->max_clk;
- 	mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
- 
- 	/* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
diff --git a/target/linux/brcm2708/patches-4.14/950-0168-serial-8250-bcm2835aux-suppress-EPROBE_DEFER.patch b/target/linux/brcm2708/patches-4.14/950-0168-serial-8250-bcm2835aux-suppress-EPROBE_DEFER.patch
deleted file mode 100644
index 12d71451e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0168-serial-8250-bcm2835aux-suppress-EPROBE_DEFER.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From b2f38b8f2b4eeee5ac50ddf79170573b9a726ec7 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 22 Jan 2018 17:26:38 +0000
-Subject: [PATCH 168/454] serial: 8250: bcm2835aux - suppress EPROBE_DEFER
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/tty/serial/8250/8250_bcm2835aux.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/tty/serial/8250/8250_bcm2835aux.c
-+++ b/drivers/tty/serial/8250/8250_bcm2835aux.c
-@@ -54,7 +54,8 @@ static int bcm2835aux_serial_probe(struc
- 	data->clk = devm_clk_get(&pdev->dev, NULL);
- 	ret = PTR_ERR_OR_ZERO(data->clk);
- 	if (ret) {
--		dev_err(&pdev->dev, "could not get clk: %d\n", ret);
-+		if (ret != -EPROBE_DEFER)
-+			dev_err(&pdev->dev, "could not get clk: %d\n", ret);
- 		return ret;
- 	}
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0169-irqchip-irq-bcm2836-Remove-regmap-and-syscon-use.patch b/target/linux/brcm2708/patches-4.14/950-0169-irqchip-irq-bcm2836-Remove-regmap-and-syscon-use.patch
deleted file mode 100644
index cfc48364f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0169-irqchip-irq-bcm2836-Remove-regmap-and-syscon-use.patch
+++ /dev/null
@@ -1,142 +0,0 @@
-From bb79a484a01f8f3645bd9b8fc6b15ea0ba961589 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 23 Jan 2018 16:52:45 +0000
-Subject: [PATCH 169/454] irqchip: irq-bcm2836: Remove regmap and syscon use
-
-The syscon node defines a register range that duplicates that used by
-the local_intc node on bcm2836/7. Since irq-bcm2835 and irq-bcm2836 are
-built in and always present together (both drivers are enabled by
-CONFIG_ARCH_BCM2835), it is possible to replace the syscon usage with a
-global variable that simplifies the code. Doing so does lose the
-locking provided by regmap, but as only one side is using the regmap
-interface (irq-bcm2835 uses readl and write) there is no loss of
-atomicity.
-
-See: https://github.com/raspberrypi/firmware/issues/926
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm2709.dtsi |  5 -----
- arch/arm/boot/dts/bcm2710.dtsi |  5 -----
- drivers/irqchip/irq-bcm2835.c  | 32 ++++++++++++--------------------
- drivers/irqchip/irq-bcm2836.c  |  5 +++++
- 4 files changed, 17 insertions(+), 30 deletions(-)
-
---- a/arch/arm/boot/dts/bcm2709.dtsi
-+++ b/arch/arm/boot/dts/bcm2709.dtsi
-@@ -6,11 +6,6 @@
- 	soc {
- 		ranges = <0x7e000000 0x3f000000 0x01000000>,
- 		         <0x40000000 0x40000000 0x00040000>;
--
--		syscon@40000000 {
--			compatible = "brcm,bcm2836-arm-local", "syscon";
--			reg = <0x40000000 0x100>;
--		};
- 	};
- 
- 	__overrides__ {
---- a/arch/arm/boot/dts/bcm2710.dtsi
-+++ b/arch/arm/boot/dts/bcm2710.dtsi
-@@ -16,11 +16,6 @@
- 			interrupt-parent = <&local_intc>;
- 			interrupts = <9>;
- 		};
--
--		syscon@40000000 {
--			compatible = "brcm,bcm2836-arm-local", "syscon";
--			reg = <0x40000000 0x100>;
--		};
- 	};
- 
- 	__overrides__ {
---- a/drivers/irqchip/irq-bcm2835.c
-+++ b/drivers/irqchip/irq-bcm2835.c
-@@ -50,8 +50,6 @@
- #include <linux/of_irq.h>
- #include <linux/irqchip.h>
- #include <linux/irqdomain.h>
--#include <linux/mfd/syscon.h>
--#include <linux/regmap.h>
- 
- #include <asm/exception.h>
- #ifndef CONFIG_ARM64
-@@ -103,7 +101,7 @@ struct armctrl_ic {
- 	void __iomem *enable[NR_BANKS];
- 	void __iomem *disable[NR_BANKS];
- 	struct irq_domain *domain;
--	struct regmap *local_regmap;
-+	void __iomem *local_base;
- };
- 
- static struct armctrl_ic intc __read_mostly;
-@@ -140,24 +138,20 @@ static void armctrl_unmask_irq(struct ir
- 	if (d->hwirq >= NUMBER_IRQS) {
- 		if (num_online_cpus() > 1) {
- 			unsigned int data;
--			int ret;
- 
--			if (!intc.local_regmap) {
--				pr_err("FIQ is disabled due to missing regmap\n");
-+			if (!intc.local_base) {
-+				pr_err("FIQ is disabled due to missing arm_local_intc\n");
- 				return;
- 			}
- 
--			ret = regmap_read(intc.local_regmap,
--					  ARM_LOCAL_GPU_INT_ROUTING, &data);
--			if (ret) {
--				pr_err("Failed to read int routing %d\n", ret);
--				return;
--			}
-+			data = readl_relaxed(intc.local_base +
-+					     ARM_LOCAL_GPU_INT_ROUTING);
- 
- 			data &= ~0xc;
- 			data |= (1 << 2);
--			regmap_write(intc.local_regmap,
--				     ARM_LOCAL_GPU_INT_ROUTING, data);
-+			writel_relaxed(data,
-+				       intc.local_base +
-+				       ARM_LOCAL_GPU_INT_ROUTING);
- 		}
- 
- 		writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
-@@ -256,12 +250,10 @@ static int __init armctrl_of_init(struct
- 	}
- 
- 	if (is_2836) {
--		intc.local_regmap =
--			syscon_regmap_lookup_by_compatible("brcm,bcm2836-arm-local");
--		if (IS_ERR(intc.local_regmap)) {
--			pr_err("Failed to get local register map. FIQ is disabled for cpus > 1\n");
--			intc.local_regmap = NULL;
--		}
-+		extern void __iomem * __attribute__((weak)) arm_local_intc;
-+		intc.local_base = arm_local_intc;
-+		if (!intc.local_base)
-+			pr_err("Failed to get local intc base. FIQ is disabled for cpus > 1\n");
- 	}
- 
- 	/* Make a duplicate irq range which is used to enable FIQ */
---- a/drivers/irqchip/irq-bcm2836.c
-+++ b/drivers/irqchip/irq-bcm2836.c
-@@ -83,6 +83,9 @@ struct bcm2836_arm_irqchip_intc {
- 
- static struct bcm2836_arm_irqchip_intc intc  __read_mostly;
- 
-+void __iomem *arm_local_intc;
-+EXPORT_SYMBOL_GPL(arm_local_intc);
-+
- static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
- 						 unsigned int bit,
- 						 int cpu)
-@@ -310,6 +313,8 @@ static int __init bcm2836_arm_irqchip_l1
- 		panic("%pOF: unable to map local interrupt registers\n", node);
- 	}
- 
-+	arm_local_intc = intc.base;
-+
- 	bcm2835_init_local_timer_frequency();
- 
- 	intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
diff --git a/target/linux/brcm2708/patches-4.14/950-0170-lan78xx-Avoid-spurious-kevent-4-error.patch b/target/linux/brcm2708/patches-4.14/950-0170-lan78xx-Avoid-spurious-kevent-4-error.patch
deleted file mode 100644
index 5731c1418..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0170-lan78xx-Avoid-spurious-kevent-4-error.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From de3b152b3662dbb68537619f2f24a893b59eb2c1 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 24 Jan 2018 15:19:39 +0000
-Subject: [PATCH 170/454] lan78xx: Avoid spurious kevent 4 "error"
-
-lan78xx_defer_event generates an error message whenever the work item
-is already scheduled. lan78xx_open defers three events -
-EVENT_STAT_UPDATE, EVENT_DEV_OPEN and EVENT_LINK_RESET. Being aware
-of the likelihood (or certainty) of an error message, the DEV_OPEN
-event is added to the set of pending events directly, relying on
-the subsequent deferral of the EVENT_LINK_RESET call to schedule the
-work.  Take the same precaution with EVENT_STAT_UPDATE to avoid a
-totally unnecessary error message.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2494,7 +2494,7 @@ static void lan78xx_init_stats(struct la
- 	dev->stats.rollover_max.eee_tx_lpi_transitions = 0xFFFFFFFF;
- 	dev->stats.rollover_max.eee_tx_lpi_time = 0xFFFFFFFF;
- 
--	lan78xx_defer_kevent(dev, EVENT_STAT_UPDATE);
-+	set_bit(EVENT_STAT_UPDATE, &dev->flags);
- }
- 
- static int lan78xx_open(struct net_device *net)
diff --git a/target/linux/brcm2708/patches-4.14/950-0171-overlays-Allow-multiple-pps-gpio-instantiations.patch b/target/linux/brcm2708/patches-4.14/950-0171-overlays-Allow-multiple-pps-gpio-instantiations.patch
deleted file mode 100644
index c614412a0..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0171-overlays-Allow-multiple-pps-gpio-instantiations.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 228a56f5c3e7b796cedb9cf7e55c2bf16c534269 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 24 Jan 2018 20:00:48 +0000
-Subject: [PATCH 171/454] overlays: Allow multiple pps-gpio instantiations
-
-See: https://github.com/raspberrypi/linux/issues/2352
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/pps-gpio-overlay.dts | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts
-@@ -6,7 +6,7 @@
- 	fragment@0 {
- 		target-path = "/";
- 		__overlay__ {
--			pps: pps {
-+			pps: pps@12 {
- 				compatible = "pps-gpio";
- 				pinctrl-names = "default";
- 				pinctrl-0 = <&pps_pins>;
-@@ -19,7 +19,7 @@
- 	fragment@1 {
- 		target = <&gpio>;
- 		__overlay__ {
--			pps_pins: pps_pins {
-+			pps_pins: pps_pins@12 {
- 				brcm,pins =     <18>;
- 				brcm,function = <0>;    // in
- 				brcm,pull =     <0>;    // off
-@@ -29,7 +29,9 @@
- 
- 	__overrides__ {
- 		gpiopin = <&pps>,"gpios:4",
--			  <&pps_pins>,"brcm,pins:0";
-+			  <&pps>,"reg:0",
-+			  <&pps_pins>,"brcm,pins:0",
-+			  <&pps_pins>,"reg:0";
- 		assert_falling_edge = <&pps>,"assert-falling-edge?";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0172-drm-vc4-Use-correct-path-to-trace-include.patch b/target/linux/brcm2708/patches-4.14/950-0172-drm-vc4-Use-correct-path-to-trace-include.patch
deleted file mode 100644
index 5af758a73..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0172-drm-vc4-Use-correct-path-to-trace-include.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 3af0d509b5718cfe7fbaf8c97e769d3df3743de0 Mon Sep 17 00:00:00 2001
-From: Thierry Reding <treding@nvidia.com>
-Date: Fri, 1 Sep 2017 16:49:54 +0200
-Subject: [PATCH 172/454] drm/vc4: Use correct path to trace include
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The header comment in include/trace/define_trace.h specifies that the
-TRACE_INCLUDE_PATH needs to be relative to the define_trace.h header
-rather than the trace file including it. Most instances get that wrong
-and work around it by adding the $(src) directory to the include path.
-
-While this works, it is preferable to refer to the correct path to the
-trace file in the first place and avoid any workaround.
-
-Acked-by: Christian König <christian.koenig@amd.com>
-Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-Signed-off-by: Thierry Reding <treding@nvidia.com>
-Link: https://patchwork.freedesktop.org/patch/msgid/20170901144954.19620-6-thierry.reding@gmail.com
-(cherry picked from commit ff58a15a502a900c35ff2f20182249b65719d6d7)
----
- drivers/gpu/drm/vc4/Makefile    | 2 --
- drivers/gpu/drm/vc4/vc4_trace.h | 2 +-
- 2 files changed, 1 insertion(+), 3 deletions(-)
-
---- a/drivers/gpu/drm/vc4/Makefile
-+++ b/drivers/gpu/drm/vc4/Makefile
-@@ -26,5 +26,3 @@ vc4-y := \
- vc4-$(CONFIG_DEBUG_FS) += vc4_debugfs.o
- 
- obj-$(CONFIG_DRM_VC4)  += vc4.o
--
--CFLAGS_vc4_trace_points.o := -I$(src)
---- a/drivers/gpu/drm/vc4/vc4_trace.h
-+++ b/drivers/gpu/drm/vc4/vc4_trace.h
-@@ -59,5 +59,5 @@ TRACE_EVENT(vc4_wait_for_seqno_end,
- 
- /* This part must be outside protection */
- #undef TRACE_INCLUDE_PATH
--#define TRACE_INCLUDE_PATH .
-+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/vc4
- #include <trace/define_trace.h>
diff --git a/target/linux/brcm2708/patches-4.14/950-0173-drm-vc4-clean-up-error-handling-on-devm_kzalloc-fail.patch b/target/linux/brcm2708/patches-4.14/950-0173-drm-vc4-clean-up-error-handling-on-devm_kzalloc-fail.patch
deleted file mode 100644
index 8976e2a36..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0173-drm-vc4-clean-up-error-handling-on-devm_kzalloc-fail.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 628487eea01248eb722b46636a4b0fe45caaf24f Mon Sep 17 00:00:00 2001
-From: Colin Ian King <colin.king@canonical.com>
-Date: Fri, 8 Sep 2017 15:05:04 +0100
-Subject: [PATCH 173/454] drm/vc4: clean up error handling on devm_kzalloc
- failure
-
-The current error handling when devm_kzalloc fails performs a
-non-null check on connector which is redundant because connector
-is null at that failure point.  Once this is removed, make the
-failure path into a trivial -ENOMEM return to clean up the
-error handling. Also remove need to initialize connector to NULL.
-
-Detected by CoverityScan CID#1339527 ("Logically dead code")
-Signed-off-by: Colin Ian King <colin.king@canonical.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20170908140504.1340-1-colin.king@canonical.com
-(cherry picked from commit 5663077a56804890506c913b3ca9fee78764f8b3)
----
- drivers/gpu/drm/vc4/vc4_hdmi.c | 15 +++------------
- 1 file changed, 3 insertions(+), 12 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_hdmi.c
-+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -309,16 +309,13 @@ static const struct drm_connector_helper
- static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
- 						     struct drm_encoder *encoder)
- {
--	struct drm_connector *connector = NULL;
-+	struct drm_connector *connector;
- 	struct vc4_hdmi_connector *hdmi_connector;
--	int ret = 0;
- 
- 	hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
- 				      GFP_KERNEL);
--	if (!hdmi_connector) {
--		ret = -ENOMEM;
--		goto fail;
--	}
-+	if (!hdmi_connector)
-+		return ERR_PTR(-ENOMEM);
- 	connector = &hdmi_connector->base;
- 
- 	hdmi_connector->encoder = encoder;
-@@ -336,12 +333,6 @@ static struct drm_connector *vc4_hdmi_co
- 	drm_mode_connector_attach_encoder(connector, encoder);
- 
- 	return connector;
--
-- fail:
--	if (connector)
--		vc4_hdmi_connector_destroy(connector);
--
--	return ERR_PTR(ret);
- }
- 
- static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
diff --git a/target/linux/brcm2708/patches-4.14/950-0174-drm-vc4-Add-the-DRM_IOCTL_VC4_GEM_MADVISE-ioctl.patch b/target/linux/brcm2708/patches-4.14/950-0174-drm-vc4-Add-the-DRM_IOCTL_VC4_GEM_MADVISE-ioctl.patch
deleted file mode 100644
index 3d10eb11f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0174-drm-vc4-Add-the-DRM_IOCTL_VC4_GEM_MADVISE-ioctl.patch
+++ /dev/null
@@ -1,870 +0,0 @@
-From 4264bba50d050577580cc6309524e3d92959fff2 Mon Sep 17 00:00:00 2001
-From: Boris Brezillon <boris.brezillon@free-electrons.com>
-Date: Thu, 19 Oct 2017 14:57:48 +0200
-Subject: [PATCH 174/454] drm/vc4: Add the DRM_IOCTL_VC4_GEM_MADVISE ioctl
-
-This ioctl will allow us to purge inactive userspace buffers when the
-system is running out of contiguous memory.
-
-For now, the purge logic is rather dumb in that it does not try to
-release only the amount of BO needed to meet the last CMA alloc request
-but instead purges all objects placed in the purgeable pool as soon as
-we experience a CMA allocation failure.
-
-Note that the in-kernel BO cache is always purged before the purgeable
-cache because those objects are known to be unused while objects marked
-as purgeable by a userspace application/library might have to be
-restored when they are marked back as unpurgeable, which can be
-expensive.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20171019125748.3152-1-boris.brezillon@free-electrons.com
-(cherry picked from commit b9f19259b84dc648f207a46f3581d15eeaedf4b6)
----
- drivers/gpu/drm/vc4/vc4_bo.c    | 287 +++++++++++++++++++++++++++++++-
- drivers/gpu/drm/vc4/vc4_drv.c   |  10 +-
- drivers/gpu/drm/vc4/vc4_drv.h   |  30 ++++
- drivers/gpu/drm/vc4/vc4_gem.c   | 156 ++++++++++++++++-
- drivers/gpu/drm/vc4/vc4_plane.c |  20 +++
- include/uapi/drm/vc4_drm.h      |  19 +++
- 6 files changed, 507 insertions(+), 15 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_bo.c
-+++ b/drivers/gpu/drm/vc4/vc4_bo.c
-@@ -53,6 +53,17 @@ static void vc4_bo_stats_dump(struct vc4
- 			 vc4->bo_labels[i].size_allocated / 1024,
- 			 vc4->bo_labels[i].num_allocated);
- 	}
-+
-+	mutex_lock(&vc4->purgeable.lock);
-+	if (vc4->purgeable.num)
-+		DRM_INFO("%30s: %6zdkb BOs (%d)\n", "userspace BO cache",
-+			 vc4->purgeable.size / 1024, vc4->purgeable.num);
-+
-+	if (vc4->purgeable.purged_num)
-+		DRM_INFO("%30s: %6zdkb BOs (%d)\n", "total purged BO",
-+			 vc4->purgeable.purged_size / 1024,
-+			 vc4->purgeable.purged_num);
-+	mutex_unlock(&vc4->purgeable.lock);
- }
- 
- #ifdef CONFIG_DEBUG_FS
-@@ -75,6 +86,17 @@ int vc4_bo_stats_debugfs(struct seq_file
- 	}
- 	mutex_unlock(&vc4->bo_lock);
- 
-+	mutex_lock(&vc4->purgeable.lock);
-+	if (vc4->purgeable.num)
-+		seq_printf(m, "%30s: %6dkb BOs (%d)\n", "userspace BO cache",
-+			   vc4->purgeable.size / 1024, vc4->purgeable.num);
-+
-+	if (vc4->purgeable.purged_num)
-+		seq_printf(m, "%30s: %6dkb BOs (%d)\n", "total purged BO",
-+			   vc4->purgeable.purged_size / 1024,
-+			   vc4->purgeable.purged_num);
-+	mutex_unlock(&vc4->purgeable.lock);
-+
- 	return 0;
- }
- #endif
-@@ -248,6 +270,109 @@ static void vc4_bo_cache_purge(struct dr
- 	mutex_unlock(&vc4->bo_lock);
- }
- 
-+void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
-+
-+	mutex_lock(&vc4->purgeable.lock);
-+	list_add_tail(&bo->size_head, &vc4->purgeable.list);
-+	vc4->purgeable.num++;
-+	vc4->purgeable.size += bo->base.base.size;
-+	mutex_unlock(&vc4->purgeable.lock);
-+}
-+
-+static void vc4_bo_remove_from_purgeable_pool_locked(struct vc4_bo *bo)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
-+
-+	/* list_del_init() is used here because the caller might release
-+	 * the purgeable lock in order to acquire the madv one and update the
-+	 * madv status.
-+	 * During this short period of time a user might decide to mark
-+	 * the BO as unpurgeable, and if bo->madv is set to
-+	 * VC4_MADV_DONTNEED it will try to remove the BO from the
-+	 * purgeable list which will fail if the ->next/prev fields
-+	 * are set to LIST_POISON1/LIST_POISON2 (which is what
-+	 * list_del() does).
-+	 * Re-initializing the list element guarantees that list_del()
-+	 * will work correctly even if it's a NOP.
-+	 */
-+	list_del_init(&bo->size_head);
-+	vc4->purgeable.num--;
-+	vc4->purgeable.size -= bo->base.base.size;
-+}
-+
-+void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
-+
-+	mutex_lock(&vc4->purgeable.lock);
-+	vc4_bo_remove_from_purgeable_pool_locked(bo);
-+	mutex_unlock(&vc4->purgeable.lock);
-+}
-+
-+static void vc4_bo_purge(struct drm_gem_object *obj)
-+{
-+	struct vc4_bo *bo = to_vc4_bo(obj);
-+	struct drm_device *dev = obj->dev;
-+
-+	WARN_ON(!mutex_is_locked(&bo->madv_lock));
-+	WARN_ON(bo->madv != VC4_MADV_DONTNEED);
-+
-+	drm_vma_node_unmap(&obj->vma_node, dev->anon_inode->i_mapping);
-+
-+	dma_free_wc(dev->dev, obj->size, bo->base.vaddr, bo->base.paddr);
-+	bo->base.vaddr = NULL;
-+	bo->madv = __VC4_MADV_PURGED;
-+}
-+
-+static void vc4_bo_userspace_cache_purge(struct drm_device *dev)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(dev);
-+
-+	mutex_lock(&vc4->purgeable.lock);
-+	while (!list_empty(&vc4->purgeable.list)) {
-+		struct vc4_bo *bo = list_first_entry(&vc4->purgeable.list,
-+						     struct vc4_bo, size_head);
-+		struct drm_gem_object *obj = &bo->base.base;
-+		size_t purged_size = 0;
-+
-+		vc4_bo_remove_from_purgeable_pool_locked(bo);
-+
-+		/* Release the purgeable lock while we're purging the BO so
-+		 * that other people can continue inserting things in the
-+		 * purgeable pool without having to wait for all BOs to be
-+		 * purged.
-+		 */
-+		mutex_unlock(&vc4->purgeable.lock);
-+		mutex_lock(&bo->madv_lock);
-+
-+		/* Since we released the purgeable pool lock before acquiring
-+		 * the BO madv one, the user may have marked the BO as WILLNEED
-+		 * and re-used it in the meantime.
-+		 * Before purging the BO we need to make sure
-+		 * - it is still marked as DONTNEED
-+		 * - it has not been re-inserted in the purgeable list
-+		 * - it is not used by HW blocks
-+		 * If one of these conditions is not met, just skip the entry.
-+		 */
-+		if (bo->madv == VC4_MADV_DONTNEED &&
-+		    list_empty(&bo->size_head) &&
-+		    !refcount_read(&bo->usecnt)) {
-+			purged_size = bo->base.base.size;
-+			vc4_bo_purge(obj);
-+		}
-+		mutex_unlock(&bo->madv_lock);
-+		mutex_lock(&vc4->purgeable.lock);
-+
-+		if (purged_size) {
-+			vc4->purgeable.purged_size += purged_size;
-+			vc4->purgeable.purged_num++;
-+		}
-+	}
-+	mutex_unlock(&vc4->purgeable.lock);
-+}
-+
- static struct vc4_bo *vc4_bo_get_from_cache(struct drm_device *dev,
- 					    uint32_t size,
- 					    enum vc4_kernel_bo_type type)
-@@ -294,6 +419,9 @@ struct drm_gem_object *vc4_create_object
- 	if (!bo)
- 		return ERR_PTR(-ENOMEM);
- 
-+	bo->madv = VC4_MADV_WILLNEED;
-+	refcount_set(&bo->usecnt, 0);
-+	mutex_init(&bo->madv_lock);
- 	mutex_lock(&vc4->bo_lock);
- 	bo->label = VC4_BO_TYPE_KERNEL;
- 	vc4->bo_labels[VC4_BO_TYPE_KERNEL].num_allocated++;
-@@ -331,16 +459,38 @@ struct vc4_bo *vc4_bo_create(struct drm_
- 		 * CMA allocations we've got laying around and try again.
- 		 */
- 		vc4_bo_cache_purge(dev);
-+		cma_obj = drm_gem_cma_create(dev, size);
-+	}
- 
-+	if (IS_ERR(cma_obj)) {
-+		/*
-+		 * Still not enough CMA memory, purge the userspace BO
-+		 * cache and retry.
-+		 * This is sub-optimal since we purge the whole userspace
-+		 * BO cache which forces user that want to re-use the BO to
-+		 * restore its initial content.
-+		 * Ideally, we should purge entries one by one and retry
-+		 * after each to see if CMA allocation succeeds. Or even
-+		 * better, try to find an entry with at least the same
-+		 * size.
-+		 */
-+		vc4_bo_userspace_cache_purge(dev);
- 		cma_obj = drm_gem_cma_create(dev, size);
--		if (IS_ERR(cma_obj)) {
--			DRM_ERROR("Failed to allocate from CMA:\n");
--			vc4_bo_stats_dump(vc4);
--			return ERR_PTR(-ENOMEM);
--		}
-+	}
-+
-+	if (IS_ERR(cma_obj)) {
-+		DRM_ERROR("Failed to allocate from CMA:\n");
-+		vc4_bo_stats_dump(vc4);
-+		return ERR_PTR(-ENOMEM);
- 	}
- 	bo = to_vc4_bo(&cma_obj->base);
- 
-+	/* By default, BOs do not support the MADV ioctl. This will be enabled
-+	 * only on BOs that are exposed to userspace (V3D, V3D_SHADER and DUMB
-+	 * BOs).
-+	 */
-+	bo->madv = __VC4_MADV_NOTSUPP;
-+
- 	mutex_lock(&vc4->bo_lock);
- 	vc4_bo_set_label(&cma_obj->base, type);
- 	mutex_unlock(&vc4->bo_lock);
-@@ -366,6 +516,8 @@ int vc4_dumb_create(struct drm_file *fil
- 	if (IS_ERR(bo))
- 		return PTR_ERR(bo);
- 
-+	bo->madv = VC4_MADV_WILLNEED;
-+
- 	ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle);
- 	drm_gem_object_put_unlocked(&bo->base.base);
- 
-@@ -404,6 +556,12 @@ void vc4_free_object(struct drm_gem_obje
- 	struct vc4_bo *bo = to_vc4_bo(gem_bo);
- 	struct list_head *cache_list;
- 
-+	/* Remove the BO from the purgeable list. */
-+	mutex_lock(&bo->madv_lock);
-+	if (bo->madv == VC4_MADV_DONTNEED && !refcount_read(&bo->usecnt))
-+		vc4_bo_remove_from_purgeable_pool(bo);
-+	mutex_unlock(&bo->madv_lock);
-+
- 	mutex_lock(&vc4->bo_lock);
- 	/* If the object references someone else's memory, we can't cache it.
- 	 */
-@@ -419,7 +577,8 @@ void vc4_free_object(struct drm_gem_obje
- 	}
- 
- 	/* If this object was partially constructed but CMA allocation
--	 * had failed, just free it.
-+	 * had failed, just free it. Can also happen when the BO has been
-+	 * purged.
- 	 */
- 	if (!bo->base.vaddr) {
- 		vc4_bo_destroy(bo);
-@@ -439,6 +598,10 @@ void vc4_free_object(struct drm_gem_obje
- 		bo->validated_shader = NULL;
- 	}
- 
-+	/* Reset madv and usecnt before adding the BO to the cache. */
-+	bo->madv = __VC4_MADV_NOTSUPP;
-+	refcount_set(&bo->usecnt, 0);
-+
- 	bo->t_format = false;
- 	bo->free_time = jiffies;
- 	list_add(&bo->size_head, cache_list);
-@@ -463,6 +626,56 @@ static void vc4_bo_cache_time_work(struc
- 	mutex_unlock(&vc4->bo_lock);
- }
- 
-+int vc4_bo_inc_usecnt(struct vc4_bo *bo)
-+{
-+	int ret;
-+
-+	/* Fast path: if the BO is already retained by someone, no need to
-+	 * check the madv status.
-+	 */
-+	if (refcount_inc_not_zero(&bo->usecnt))
-+		return 0;
-+
-+	mutex_lock(&bo->madv_lock);
-+	switch (bo->madv) {
-+	case VC4_MADV_WILLNEED:
-+		refcount_inc(&bo->usecnt);
-+		ret = 0;
-+		break;
-+	case VC4_MADV_DONTNEED:
-+		/* We shouldn't use a BO marked as purgeable if at least
-+		 * someone else retained its content by incrementing usecnt.
-+		 * Luckily the BO hasn't been purged yet, but something wrong
-+		 * is happening here. Just throw an error instead of
-+		 * authorizing this use case.
-+		 */
-+	case __VC4_MADV_PURGED:
-+		/* We can't use a purged BO. */
-+	default:
-+		/* Invalid madv value. */
-+		ret = -EINVAL;
-+		break;
-+	}
-+	mutex_unlock(&bo->madv_lock);
-+
-+	return ret;
-+}
-+
-+void vc4_bo_dec_usecnt(struct vc4_bo *bo)
-+{
-+	/* Fast path: if the BO is still retained by someone, no need to test
-+	 * the madv value.
-+	 */
-+	if (refcount_dec_not_one(&bo->usecnt))
-+		return;
-+
-+	mutex_lock(&bo->madv_lock);
-+	if (refcount_dec_and_test(&bo->usecnt) &&
-+	    bo->madv == VC4_MADV_DONTNEED)
-+		vc4_bo_add_to_purgeable_pool(bo);
-+	mutex_unlock(&bo->madv_lock);
-+}
-+
- static void vc4_bo_cache_time_timer(unsigned long data)
- {
- 	struct drm_device *dev = (struct drm_device *)data;
-@@ -482,18 +695,52 @@ struct dma_buf *
- vc4_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags)
- {
- 	struct vc4_bo *bo = to_vc4_bo(obj);
-+	struct dma_buf *dmabuf;
-+	int ret;
- 
- 	if (bo->validated_shader) {
- 		DRM_DEBUG("Attempting to export shader BO\n");
- 		return ERR_PTR(-EINVAL);
- 	}
- 
--	return drm_gem_prime_export(dev, obj, flags);
-+	/* Note: as soon as the BO is exported it becomes unpurgeable, because
-+	 * noone ever decrements the usecnt even if the reference held by the
-+	 * exported BO is released. This shouldn't be a problem since we don't
-+	 * expect exported BOs to be marked as purgeable.
-+	 */
-+	ret = vc4_bo_inc_usecnt(bo);
-+	if (ret) {
-+		DRM_ERROR("Failed to increment BO usecnt\n");
-+		return ERR_PTR(ret);
-+	}
-+
-+	dmabuf = drm_gem_prime_export(dev, obj, flags);
-+	if (IS_ERR(dmabuf))
-+		vc4_bo_dec_usecnt(bo);
-+
-+	return dmabuf;
-+}
-+
-+int vc4_fault(struct vm_fault *vmf)
-+{
-+	struct vm_area_struct *vma = vmf->vma;
-+	struct drm_gem_object *obj = vma->vm_private_data;
-+	struct vc4_bo *bo = to_vc4_bo(obj);
-+
-+	/* The only reason we would end up here is when user-space accesses
-+	 * BO's memory after it's been purged.
-+	 */
-+	mutex_lock(&bo->madv_lock);
-+	WARN_ON(bo->madv != __VC4_MADV_PURGED);
-+	mutex_unlock(&bo->madv_lock);
-+
-+	return VM_FAULT_SIGBUS;
- }
- 
- int vc4_mmap(struct file *filp, struct vm_area_struct *vma)
- {
- 	struct drm_gem_object *gem_obj;
-+	unsigned long vm_pgoff;
- 	struct vc4_bo *bo;
- 	int ret;
- 
-@@ -509,16 +756,36 @@ int vc4_mmap(struct file *filp, struct v
- 		return -EINVAL;
- 	}
- 
-+	if (bo->madv != VC4_MADV_WILLNEED) {
-+		DRM_DEBUG("mmaping of %s BO not allowed\n",
-+			  bo->madv == VC4_MADV_DONTNEED ?
-+			  "purgeable" : "purged");
-+		return -EINVAL;
-+	}
-+
- 	/*
- 	 * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), and set the
- 	 * vm_pgoff (used as a fake buffer offset by DRM) to 0 as we want to map
- 	 * the whole buffer.
- 	 */
- 	vma->vm_flags &= ~VM_PFNMAP;
--	vma->vm_pgoff = 0;
- 
-+	/* This ->vm_pgoff dance is needed to make all parties happy:
-+	 * - dma_mmap_wc() uses ->vm_pgoff as an offset within the allocated
-+	 *   mem-region, hence the need to set it to zero (the value set by
-+	 *   the DRM core is a virtual offset encoding the GEM object-id)
-+	 * - the mmap() core logic needs ->vm_pgoff to be restored to its
-+	 *   initial value before returning from this function because it
-+	 *   encodes the  offset of this GEM in the dev->anon_inode pseudo-file
-+	 *   and this information will be used when we invalidate userspace
-+	 *   mappings  with drm_vma_node_unmap() (called from vc4_gem_purge()).
-+	 */
-+	vm_pgoff = vma->vm_pgoff;
-+	vma->vm_pgoff = 0;
- 	ret = dma_mmap_wc(bo->base.base.dev->dev, vma, bo->base.vaddr,
- 			  bo->base.paddr, vma->vm_end - vma->vm_start);
-+	vma->vm_pgoff = vm_pgoff;
-+
- 	if (ret)
- 		drm_gem_vm_close(vma);
- 
-@@ -582,6 +849,8 @@ int vc4_create_bo_ioctl(struct drm_devic
- 	if (IS_ERR(bo))
- 		return PTR_ERR(bo);
- 
-+	bo->madv = VC4_MADV_WILLNEED;
-+
- 	ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle);
- 	drm_gem_object_put_unlocked(&bo->base.base);
- 
-@@ -635,6 +904,8 @@ vc4_create_shader_bo_ioctl(struct drm_de
- 	if (IS_ERR(bo))
- 		return PTR_ERR(bo);
- 
-+	bo->madv = VC4_MADV_WILLNEED;
-+
- 	if (copy_from_user(bo->base.vaddr,
- 			     (void __user *)(uintptr_t)args->data,
- 			     args->size)) {
---- a/drivers/gpu/drm/vc4/vc4_drv.c
-+++ b/drivers/gpu/drm/vc4/vc4_drv.c
-@@ -100,6 +100,7 @@ static int vc4_get_param_ioctl(struct dr
- 	case DRM_VC4_PARAM_SUPPORTS_ETC1:
- 	case DRM_VC4_PARAM_SUPPORTS_THREADED_FS:
- 	case DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER:
-+	case DRM_VC4_PARAM_SUPPORTS_MADVISE:
- 		args->value = true;
- 		break;
- 	default:
-@@ -117,6 +118,12 @@ static void vc4_lastclose(struct drm_dev
- 	drm_fbdev_cma_restore_mode(vc4->fbdev);
- }
- 
-+static const struct vm_operations_struct vc4_vm_ops = {
-+	.fault = vc4_fault,
-+	.open = drm_gem_vm_open,
-+	.close = drm_gem_vm_close,
-+};
-+
- static const struct file_operations vc4_drm_fops = {
- 	.owner = THIS_MODULE,
- 	.open = drm_open,
-@@ -142,6 +149,7 @@ static const struct drm_ioctl_desc vc4_d
- 	DRM_IOCTL_DEF_DRV(VC4_SET_TILING, vc4_set_tiling_ioctl, DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(VC4_GET_TILING, vc4_get_tiling_ioctl, DRM_RENDER_ALLOW),
- 	DRM_IOCTL_DEF_DRV(VC4_LABEL_BO, vc4_label_bo_ioctl, DRM_RENDER_ALLOW),
-+	DRM_IOCTL_DEF_DRV(VC4_GEM_MADVISE, vc4_gem_madvise_ioctl, DRM_RENDER_ALLOW),
- };
- 
- static struct drm_driver vc4_drm_driver = {
-@@ -166,7 +174,7 @@ static struct drm_driver vc4_drm_driver
- 
- 	.gem_create_object = vc4_create_object,
- 	.gem_free_object_unlocked = vc4_free_object,
--	.gem_vm_ops = &drm_gem_cma_vm_ops,
-+	.gem_vm_ops = &vc4_vm_ops,
- 
- 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
- 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
---- a/drivers/gpu/drm/vc4/vc4_drv.h
-+++ b/drivers/gpu/drm/vc4/vc4_drv.h
-@@ -77,6 +77,19 @@ struct vc4_dev {
- 	/* Protects bo_cache and bo_labels. */
- 	struct mutex bo_lock;
- 
-+	/* Purgeable BO pool. All BOs in this pool can have their memory
-+	 * reclaimed if the driver is unable to allocate new BOs. We also
-+	 * keep stats related to the purge mechanism here.
-+	 */
-+	struct {
-+		struct list_head list;
-+		unsigned int num;
-+		size_t size;
-+		unsigned int purged_num;
-+		size_t purged_size;
-+		struct mutex lock;
-+	} purgeable;
-+
- 	uint64_t dma_fence_context;
- 
- 	/* Sequence number for the last job queued in bin_job_list.
-@@ -195,6 +208,16 @@ struct vc4_bo {
- 	 * for user-allocated labels.
- 	 */
- 	int label;
-+
-+	/* Count the number of active users. This is needed to determine
-+	 * whether we can move the BO to the purgeable list or not (when the BO
-+	 * is used by the GPU or the display engine we can't purge it).
-+	 */
-+	refcount_t usecnt;
-+
-+	/* Store purgeable/purged state here */
-+	u32 madv;
-+	struct mutex madv_lock;
- };
- 
- static inline struct vc4_bo *
-@@ -506,6 +529,7 @@ int vc4_get_hang_state_ioctl(struct drm_
- 			     struct drm_file *file_priv);
- int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
- 		       struct drm_file *file_priv);
-+int vc4_fault(struct vm_fault *vmf);
- int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
- struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj);
- int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
-@@ -516,6 +540,10 @@ void *vc4_prime_vmap(struct drm_gem_obje
- int vc4_bo_cache_init(struct drm_device *dev);
- void vc4_bo_cache_destroy(struct drm_device *dev);
- int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
-+int vc4_bo_inc_usecnt(struct vc4_bo *bo);
-+void vc4_bo_dec_usecnt(struct vc4_bo *bo);
-+void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
-+void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
- 
- /* vc4_crtc.c */
- extern struct platform_driver vc4_crtc_driver;
-@@ -564,6 +592,8 @@ void vc4_job_handle_completed(struct vc4
- int vc4_queue_seqno_cb(struct drm_device *dev,
- 		       struct vc4_seqno_cb *cb, uint64_t seqno,
- 		       void (*func)(struct vc4_seqno_cb *cb));
-+int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
-+			  struct drm_file *file_priv);
- 
- /* vc4_hdmi.c */
- extern struct platform_driver vc4_hdmi_driver;
---- a/drivers/gpu/drm/vc4/vc4_gem.c
-+++ b/drivers/gpu/drm/vc4/vc4_gem.c
-@@ -188,11 +188,22 @@ vc4_save_hang_state(struct drm_device *d
- 			continue;
- 
- 		for (j = 0; j < exec[i]->bo_count; j++) {
-+			bo = to_vc4_bo(&exec[i]->bo[j]->base);
-+
-+			/* Retain BOs just in case they were marked purgeable.
-+			 * This prevents the BO from being purged before
-+			 * someone had a chance to dump the hang state.
-+			 */
-+			WARN_ON(!refcount_read(&bo->usecnt));
-+			refcount_inc(&bo->usecnt);
- 			drm_gem_object_get(&exec[i]->bo[j]->base);
- 			kernel_state->bo[k++] = &exec[i]->bo[j]->base;
- 		}
- 
- 		list_for_each_entry(bo, &exec[i]->unref_list, unref_head) {
-+			/* No need to retain BOs coming from the ->unref_list
-+			 * because they are naturally unpurgeable.
-+			 */
- 			drm_gem_object_get(&bo->base.base);
- 			kernel_state->bo[k++] = &bo->base.base;
- 		}
-@@ -233,6 +244,26 @@ vc4_save_hang_state(struct drm_device *d
- 	state->fdbgs = V3D_READ(V3D_FDBGS);
- 	state->errstat = V3D_READ(V3D_ERRSTAT);
- 
-+	/* We need to turn purgeable BOs into unpurgeable ones so that
-+	 * userspace has a chance to dump the hang state before the kernel
-+	 * decides to purge those BOs.
-+	 * Note that BO consistency at dump time cannot be guaranteed. For
-+	 * example, if the owner of these BOs decides to re-use them or mark
-+	 * them purgeable again there's nothing we can do to prevent it.
-+	 */
-+	for (i = 0; i < kernel_state->user_state.bo_count; i++) {
-+		struct vc4_bo *bo = to_vc4_bo(kernel_state->bo[i]);
-+
-+		if (bo->madv == __VC4_MADV_NOTSUPP)
-+			continue;
-+
-+		mutex_lock(&bo->madv_lock);
-+		if (!WARN_ON(bo->madv == __VC4_MADV_PURGED))
-+			bo->madv = VC4_MADV_WILLNEED;
-+		refcount_dec(&bo->usecnt);
-+		mutex_unlock(&bo->madv_lock);
-+	}
-+
- 	spin_lock_irqsave(&vc4->job_lock, irqflags);
- 	if (vc4->hang_state) {
- 		spin_unlock_irqrestore(&vc4->job_lock, irqflags);
-@@ -639,9 +670,6 @@ vc4_queue_submit(struct drm_device *dev,
-  * The command validator needs to reference BOs by their index within
-  * the submitted job's BO list.  This does the validation of the job's
-  * BO list and reference counting for the lifetime of the job.
-- *
-- * Note that this function doesn't need to unreference the BOs on
-- * failure, because that will happen at vc4_complete_exec() time.
-  */
- static int
- vc4_cl_lookup_bos(struct drm_device *dev,
-@@ -693,16 +721,47 @@ vc4_cl_lookup_bos(struct drm_device *dev
- 			DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
- 				  i, handles[i]);
- 			ret = -EINVAL;
--			spin_unlock(&file_priv->table_lock);
--			goto fail;
-+			break;
- 		}
-+
- 		drm_gem_object_get(bo);
- 		exec->bo[i] = (struct drm_gem_cma_object *)bo;
- 	}
- 	spin_unlock(&file_priv->table_lock);
- 
-+	if (ret)
-+		goto fail_put_bo;
-+
-+	for (i = 0; i < exec->bo_count; i++) {
-+		ret = vc4_bo_inc_usecnt(to_vc4_bo(&exec->bo[i]->base));
-+		if (ret)
-+			goto fail_dec_usecnt;
-+	}
-+
-+	kvfree(handles);
-+	return 0;
-+
-+fail_dec_usecnt:
-+	/* Decrease usecnt on acquired objects.
-+	 * We cannot rely on  vc4_complete_exec() to release resources here,
-+	 * because vc4_complete_exec() has no information about which BO has
-+	 * had its ->usecnt incremented.
-+	 * To make things easier we just free everything explicitly and set
-+	 * exec->bo to NULL so that vc4_complete_exec() skips the 'BO release'
-+	 * step.
-+	 */
-+	for (i-- ; i >= 0; i--)
-+		vc4_bo_dec_usecnt(to_vc4_bo(&exec->bo[i]->base));
-+
-+fail_put_bo:
-+	/* Release any reference to acquired objects. */
-+	for (i = 0; i < exec->bo_count && exec->bo[i]; i++)
-+		drm_gem_object_put_unlocked(&exec->bo[i]->base);
-+
- fail:
- 	kvfree(handles);
-+	kvfree(exec->bo);
-+	exec->bo = NULL;
- 	return ret;
- }
- 
-@@ -835,8 +894,12 @@ vc4_complete_exec(struct drm_device *dev
- 	}
- 
- 	if (exec->bo) {
--		for (i = 0; i < exec->bo_count; i++)
-+		for (i = 0; i < exec->bo_count; i++) {
-+			struct vc4_bo *bo = to_vc4_bo(&exec->bo[i]->base);
-+
-+			vc4_bo_dec_usecnt(bo);
- 			drm_gem_object_put_unlocked(&exec->bo[i]->base);
-+		}
- 		kvfree(exec->bo);
- 	}
- 
-@@ -1100,6 +1163,9 @@ vc4_gem_init(struct drm_device *dev)
- 	INIT_WORK(&vc4->job_done_work, vc4_job_done_work);
- 
- 	mutex_init(&vc4->power_lock);
-+
-+	INIT_LIST_HEAD(&vc4->purgeable.list);
-+	mutex_init(&vc4->purgeable.lock);
- }
- 
- void
-@@ -1123,3 +1189,81 @@ vc4_gem_destroy(struct drm_device *dev)
- 	if (vc4->hang_state)
- 		vc4_free_hang_state(dev, vc4->hang_state);
- }
-+
-+int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
-+			  struct drm_file *file_priv)
-+{
-+	struct drm_vc4_gem_madvise *args = data;
-+	struct drm_gem_object *gem_obj;
-+	struct vc4_bo *bo;
-+	int ret;
-+
-+	switch (args->madv) {
-+	case VC4_MADV_DONTNEED:
-+	case VC4_MADV_WILLNEED:
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	if (args->pad != 0)
-+		return -EINVAL;
-+
-+	gem_obj = drm_gem_object_lookup(file_priv, args->handle);
-+	if (!gem_obj) {
-+		DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
-+		return -ENOENT;
-+	}
-+
-+	bo = to_vc4_bo(gem_obj);
-+
-+	/* Only BOs exposed to userspace can be purged. */
-+	if (bo->madv == __VC4_MADV_NOTSUPP) {
-+		DRM_DEBUG("madvise not supported on this BO\n");
-+		ret = -EINVAL;
-+		goto out_put_gem;
-+	}
-+
-+	/* Not sure it's safe to purge imported BOs. Let's just assume it's
-+	 * not until proven otherwise.
-+	 */
-+	if (gem_obj->import_attach) {
-+		DRM_DEBUG("madvise not supported on imported BOs\n");
-+		ret = -EINVAL;
-+		goto out_put_gem;
-+	}
-+
-+	mutex_lock(&bo->madv_lock);
-+
-+	if (args->madv == VC4_MADV_DONTNEED && bo->madv == VC4_MADV_WILLNEED &&
-+	    !refcount_read(&bo->usecnt)) {
-+		/* If the BO is about to be marked as purgeable, is not used
-+		 * and is not already purgeable or purged, add it to the
-+		 * purgeable list.
-+		 */
-+		vc4_bo_add_to_purgeable_pool(bo);
-+	} else if (args->madv == VC4_MADV_WILLNEED &&
-+		   bo->madv == VC4_MADV_DONTNEED &&
-+		   !refcount_read(&bo->usecnt)) {
-+		/* The BO has not been purged yet, just remove it from
-+		 * the purgeable list.
-+		 */
-+		vc4_bo_remove_from_purgeable_pool(bo);
-+	}
-+
-+	/* Save the purged state. */
-+	args->retained = bo->madv != __VC4_MADV_PURGED;
-+
-+	/* Update internal madv state only if the bo was not purged. */
-+	if (bo->madv != __VC4_MADV_PURGED)
-+		bo->madv = args->madv;
-+
-+	mutex_unlock(&bo->madv_lock);
-+
-+	ret = 0;
-+
-+out_put_gem:
-+	drm_gem_object_put_unlocked(gem_obj);
-+
-+	return ret;
-+}
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -23,6 +23,7 @@
- #include <drm/drm_fb_cma_helper.h>
- #include <drm/drm_plane_helper.h>
- 
-+#include "uapi/drm/vc4_drm.h"
- #include "vc4_drv.h"
- #include "vc4_regs.h"
- 
-@@ -776,21 +777,40 @@ static int vc4_prepare_fb(struct drm_pla
- {
- 	struct vc4_bo *bo;
- 	struct dma_fence *fence;
-+	int ret;
- 
- 	if ((plane->state->fb == state->fb) || !state->fb)
- 		return 0;
- 
- 	bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
-+
-+	ret = vc4_bo_inc_usecnt(bo);
-+	if (ret)
-+		return ret;
-+
- 	fence = reservation_object_get_excl_rcu(bo->resv);
- 	drm_atomic_set_fence_for_plane(state, fence);
- 
- 	return 0;
- }
- 
-+static void vc4_cleanup_fb(struct drm_plane *plane,
-+			   struct drm_plane_state *state)
-+{
-+	struct vc4_bo *bo;
-+
-+	if (plane->state->fb == state->fb || !state->fb)
-+		return;
-+
-+	bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
-+	vc4_bo_dec_usecnt(bo);
-+}
-+
- static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
- 	.atomic_check = vc4_plane_atomic_check,
- 	.atomic_update = vc4_plane_atomic_update,
- 	.prepare_fb = vc4_prepare_fb,
-+	.cleanup_fb = vc4_cleanup_fb,
- };
- 
- static void vc4_plane_destroy(struct drm_plane *plane)
---- a/include/uapi/drm/vc4_drm.h
-+++ b/include/uapi/drm/vc4_drm.h
-@@ -41,6 +41,7 @@ extern "C" {
- #define DRM_VC4_SET_TILING                        0x08
- #define DRM_VC4_GET_TILING                        0x09
- #define DRM_VC4_LABEL_BO                          0x0a
-+#define DRM_VC4_GEM_MADVISE                       0x0b
- 
- #define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
- #define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
-@@ -53,6 +54,7 @@ extern "C" {
- #define DRM_IOCTL_VC4_SET_TILING          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)
- #define DRM_IOCTL_VC4_GET_TILING          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)
- #define DRM_IOCTL_VC4_LABEL_BO            DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)
-+#define DRM_IOCTL_VC4_GEM_MADVISE         DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)
- 
- struct drm_vc4_submit_rcl_surface {
- 	__u32 hindex; /* Handle index, or ~0 if not present. */
-@@ -305,6 +307,7 @@ struct drm_vc4_get_hang_state {
- #define DRM_VC4_PARAM_SUPPORTS_ETC1		4
- #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS	5
- #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER	6
-+#define DRM_VC4_PARAM_SUPPORTS_MADVISE		7
- 
- struct drm_vc4_get_param {
- 	__u32 param;
-@@ -333,6 +336,22 @@ struct drm_vc4_label_bo {
- 	__u64 name;
- };
- 
-+/*
-+ * States prefixed with '__' are internal states and cannot be passed to the
-+ * DRM_IOCTL_VC4_GEM_MADVISE ioctl.
-+ */
-+#define VC4_MADV_WILLNEED			0
-+#define VC4_MADV_DONTNEED			1
-+#define __VC4_MADV_PURGED			2
-+#define __VC4_MADV_NOTSUPP			3
-+
-+struct drm_vc4_gem_madvise {
-+	__u32 handle;
-+	__u32 madv;
-+	__u32 retained;
-+	__u32 pad;
-+};
-+
- #if defined(__cplusplus)
- }
- #endif
diff --git a/target/linux/brcm2708/patches-4.14/950-0175-drm-vc4-Fix-false-positive-WARN-backtrace-on-refcoun.patch b/target/linux/brcm2708/patches-4.14/950-0175-drm-vc4-Fix-false-positive-WARN-backtrace-on-refcoun.patch
deleted file mode 100644
index 0d3b4520d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0175-drm-vc4-Fix-false-positive-WARN-backtrace-on-refcoun.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 5537bac0e5c8f3634c5595c21c7d63f0c0263e0e Mon Sep 17 00:00:00 2001
-From: Boris Brezillon <boris.brezillon@free-electrons.com>
-Date: Wed, 22 Nov 2017 21:39:28 +0100
-Subject: [PATCH 175/454] drm/vc4: Fix false positive WARN() backtrace on
- refcount_inc() usage
-
-With CONFIG_REFCOUNT_FULL enabled, refcount_inc() complains when it's
-passed a refcount object that has its counter set to 0. In this driver,
-this is a valid use case since we want to increment ->usecnt only when
-the BO object starts to be used by real HW components and this is
-definitely not the case when the BO is created.
-
-Fix the problem by using refcount_inc_not_zero() instead of
-refcount_inc() and fallback to refcount_set(1) when
-refcount_inc_not_zero() returns false. Note that this 2-steps operation
-is not racy here because the whole section is protected by a mutex
-which guarantees that the counter does not change between the
-refcount_inc_not_zero() and refcount_set() calls.
-
-Fixes: b9f19259b84d ("drm/vc4: Add the DRM_IOCTL_VC4_GEM_MADVISE ioctl")
-Reported-by: Stefan Wahren <stefan.wahren@i2se.com>
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Acked-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20171122203928.28135-1-boris.brezillon@free-electrons.com
-(cherry picked from commit 5bfd40139d55790cbc8e56ad1ce4f974f1fa186d)
----
- drivers/gpu/drm/vc4/vc4_bo.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/vc4/vc4_bo.c
-+++ b/drivers/gpu/drm/vc4/vc4_bo.c
-@@ -639,7 +639,8 @@ int vc4_bo_inc_usecnt(struct vc4_bo *bo)
- 	mutex_lock(&bo->madv_lock);
- 	switch (bo->madv) {
- 	case VC4_MADV_WILLNEED:
--		refcount_inc(&bo->usecnt);
-+		if (!refcount_inc_not_zero(&bo->usecnt))
-+			refcount_set(&bo->usecnt, 1);
- 		ret = 0;
- 		break;
- 	case VC4_MADV_DONTNEED:
diff --git a/target/linux/brcm2708/patches-4.14/950-0176-drm-vc4-Fix-sleeps-during-the-IRQ-handler-for-DSI-tr.patch b/target/linux/brcm2708/patches-4.14/950-0176-drm-vc4-Fix-sleeps-during-the-IRQ-handler-for-DSI-tr.patch
deleted file mode 100644
index d6949b617..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0176-drm-vc4-Fix-sleeps-during-the-IRQ-handler-for-DSI-tr.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From 659c52fe8a86264c5119c0592654898d09fe8f28 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Fri, 13 Oct 2017 17:12:55 -0700
-Subject: [PATCH 176/454] drm/vc4: Fix sleeps during the IRQ handler for DSI
- transactions.
-
-VC4's DSI1 has a bug where the AXI connection is broken for 32-bit
-writes from the CPU, so we use the DMA engine to DMA 32-bit values
-into registers instead.  That sleeps, so we can't do it from the top
-half.
-
-As a solution, use an interrupt thread so that all our writes happen
-when sleeping is is allowed.
-
-v2: Use IRQF_ONESHOT (suggested by Boris)
-v3: Style nitpicks.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20171014001255.32005-1-eric@anholt.net
-Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> (v2)
-(cherry picked from commit af0c8c10564aac5b6d67308129ec09c4ad5db476)
----
- drivers/gpu/drm/vc4/vc4_dsi.c | 32 ++++++++++++++++++++++++++++++--
- 1 file changed, 30 insertions(+), 2 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_dsi.c
-+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
-@@ -1383,6 +1383,27 @@ static void dsi_handle_error(struct vc4_
- 	*ret = IRQ_HANDLED;
- }
- 
-+/*
-+ * Initial handler for port 1 where we need the reg_dma workaround.
-+ * The register DMA writes sleep, so we can't do it in the top half.
-+ * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
-+ * parent interrupt contrller until our interrupt thread is done.
-+ */
-+static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
-+{
-+	struct vc4_dsi *dsi = data;
-+	u32 stat = DSI_PORT_READ(INT_STAT);
-+
-+	if (!stat)
-+		return IRQ_NONE;
-+
-+	return IRQ_WAKE_THREAD;
-+}
-+
-+/*
-+ * Normal IRQ handler for port 0, or the threaded IRQ handler for port
-+ * 1 where we need the reg_dma workaround.
-+ */
- static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
- {
- 	struct vc4_dsi *dsi = data;
-@@ -1566,8 +1587,15 @@ static int vc4_dsi_bind(struct device *d
- 	/* Clear any existing interrupt state. */
- 	DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
- 
--	ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
--			       vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
-+	if (dsi->reg_dma_mem)
-+		ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
-+						vc4_dsi_irq_defer_to_thread_handler,
-+						vc4_dsi_irq_handler,
-+						IRQF_ONESHOT,
-+						"vc4 dsi", dsi);
-+	else
-+		ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
-+				       vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
- 	if (ret) {
- 		if (ret != -EPROBE_DEFER)
- 			dev_err(dev, "Failed to get interrupt: %d\n", ret);
diff --git a/target/linux/brcm2708/patches-4.14/950-0177-drm-vc4-Convert-timers-to-use-timer_setup.patch b/target/linux/brcm2708/patches-4.14/950-0177-drm-vc4-Convert-timers-to-use-timer_setup.patch
deleted file mode 100644
index d3883dc74..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0177-drm-vc4-Convert-timers-to-use-timer_setup.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 98f53bafea86a24d2ae510a72cb24234f6cbb7f2 Mon Sep 17 00:00:00 2001
-From: Kees Cook <keescook@chromium.org>
-Date: Tue, 24 Oct 2017 08:16:48 -0700
-Subject: [PATCH 177/454] drm/vc4: Convert timers to use timer_setup()
-
-In preparation for unconditionally passing the struct timer_list pointer to
-all timer callbacks, switch to using the new timer_setup() and from_timer()
-to pass the timer pointer explicitly.
-
-Cc: Eric Anholt <eric@anholt.net>
-Cc: David Airlie <airlied@linux.ie>
-Cc: dri-devel@lists.freedesktop.org
-Signed-off-by: Kees Cook <keescook@chromium.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20171024151648.GA104538@beast
-Reviewed-by: Eric Anholt <eric@anholt.net>
-(cherry picked from commit 33b54ea1109721dcd07d3f7ee753c07482021eed)
----
- drivers/gpu/drm/vc4/vc4_bo.c  |  9 +++------
- drivers/gpu/drm/vc4/vc4_gem.c | 10 ++++------
- 2 files changed, 7 insertions(+), 12 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_bo.c
-+++ b/drivers/gpu/drm/vc4/vc4_bo.c
-@@ -677,10 +677,9 @@ void vc4_bo_dec_usecnt(struct vc4_bo *bo
- 	mutex_unlock(&bo->madv_lock);
- }
- 
--static void vc4_bo_cache_time_timer(unsigned long data)
-+static void vc4_bo_cache_time_timer(struct timer_list *t)
- {
--	struct drm_device *dev = (struct drm_device *)data;
--	struct vc4_dev *vc4 = to_vc4_dev(dev);
-+	struct vc4_dev *vc4 = from_timer(vc4, t, bo_cache.time_timer);
- 
- 	schedule_work(&vc4->bo_cache.time_work);
- }
-@@ -1042,9 +1041,7 @@ int vc4_bo_cache_init(struct drm_device
- 	INIT_LIST_HEAD(&vc4->bo_cache.time_list);
- 
- 	INIT_WORK(&vc4->bo_cache.time_work, vc4_bo_cache_time_work);
--	setup_timer(&vc4->bo_cache.time_timer,
--		    vc4_bo_cache_time_timer,
--		    (unsigned long)dev);
-+	timer_setup(&vc4->bo_cache.time_timer, vc4_bo_cache_time_timer, 0);
- 
- 	return 0;
- }
---- a/drivers/gpu/drm/vc4/vc4_gem.c
-+++ b/drivers/gpu/drm/vc4/vc4_gem.c
-@@ -312,10 +312,10 @@ vc4_reset_work(struct work_struct *work)
- }
- 
- static void
--vc4_hangcheck_elapsed(unsigned long data)
-+vc4_hangcheck_elapsed(struct timer_list *t)
- {
--	struct drm_device *dev = (struct drm_device *)data;
--	struct vc4_dev *vc4 = to_vc4_dev(dev);
-+	struct vc4_dev *vc4 = from_timer(vc4, t, hangcheck.timer);
-+	struct drm_device *dev = vc4->dev;
- 	uint32_t ct0ca, ct1ca;
- 	unsigned long irqflags;
- 	struct vc4_exec_info *bin_exec, *render_exec;
-@@ -1156,9 +1156,7 @@ vc4_gem_init(struct drm_device *dev)
- 	spin_lock_init(&vc4->job_lock);
- 
- 	INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work);
--	setup_timer(&vc4->hangcheck.timer,
--		    vc4_hangcheck_elapsed,
--		    (unsigned long)dev);
-+	timer_setup(&vc4->hangcheck.timer, vc4_hangcheck_elapsed, 0);
- 
- 	INIT_WORK(&vc4->job_done_work, vc4_job_done_work);
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0178-drm-vc4-Fix-wrong-printk-format-in-vc4_bo_stats_debu.patch b/target/linux/brcm2708/patches-4.14/950-0178-drm-vc4-Fix-wrong-printk-format-in-vc4_bo_stats_debu.patch
deleted file mode 100644
index 57b4d1cc5..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0178-drm-vc4-Fix-wrong-printk-format-in-vc4_bo_stats_debu.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From aff2333a8ffe1dffd7b843872682278d335ee60c Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Wed, 1 Nov 2017 10:57:31 +0100
-Subject: [PATCH 178/454] drm/vc4: Fix wrong printk format in
- vc4_bo_stats_debugfs()
-
-vc4->purgeable.size and vc4->purgeable.purged_size are size_t fields
-and should be printed with a %zd specifier.
-
-Fixes: b9f19259b84d ("drm/vc4: Add the DRM_IOCTL_VC4_GEM_MADVISE ioctl")
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.com>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20171101095731.14878-1-boris.brezillon@free-electrons.com
-(cherry picked from commit 50f365cde4ffb5ae70c3f02384bbb46698aba65c)
----
- drivers/gpu/drm/vc4/vc4_bo.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_bo.c
-+++ b/drivers/gpu/drm/vc4/vc4_bo.c
-@@ -88,11 +88,11 @@ int vc4_bo_stats_debugfs(struct seq_file
- 
- 	mutex_lock(&vc4->purgeable.lock);
- 	if (vc4->purgeable.num)
--		seq_printf(m, "%30s: %6dkb BOs (%d)\n", "userspace BO cache",
-+		seq_printf(m, "%30s: %6zdkb BOs (%d)\n", "userspace BO cache",
- 			   vc4->purgeable.size / 1024, vc4->purgeable.num);
- 
- 	if (vc4->purgeable.purged_num)
--		seq_printf(m, "%30s: %6dkb BOs (%d)\n", "total purged BO",
-+		seq_printf(m, "%30s: %6zdkb BOs (%d)\n", "total purged BO",
- 			   vc4->purgeable.purged_size / 1024,
- 			   vc4->purgeable.purged_num);
- 	mutex_unlock(&vc4->purgeable.lock);
diff --git a/target/linux/brcm2708/patches-4.14/950-0179-drm-vc4-Reject-HDMI-modes-with-too-high-of-clocks.patch b/target/linux/brcm2708/patches-4.14/950-0179-drm-vc4-Reject-HDMI-modes-with-too-high-of-clocks.patch
deleted file mode 100644
index bef281145..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0179-drm-vc4-Reject-HDMI-modes-with-too-high-of-clocks.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From ee3cf448adf29e8948c40d251f87d87a9817515c Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 20 Sep 2017 15:59:34 -0700
-Subject: [PATCH 179/454] drm/vc4: Reject HDMI modes with too high of clocks.
-
-Peter Robinson reported issues on Fedora with 4k monitors not having
-their modes filtered down to 1920x1080 on Raspberry Pi.
-
-v2: Fix vc5 typo in place of vc4.
-
-Cc: Peter Robinson <pbrobinson@redhat.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20170920225935.14566-1-eric@anholt.net
-Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1)
-(cherry picked from commit 32e823c63e90f7535ea1cc5311d25c0233e1456d)
----
- drivers/gpu/drm/vc4/vc4_hdmi.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_hdmi.c
-+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -695,7 +695,22 @@ static void vc4_hdmi_encoder_enable(stru
- 	}
- }
- 
-+static enum drm_mode_status
-+vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
-+			    const struct drm_display_mode *mode)
-+{
-+	/* HSM clock must be 108% of the pixel clock.  Additionally,
-+	 * the AXI clock needs to be at least 25% of pixel clock, but
-+	 * HSM ends up being the limiting factor.
-+	 */
-+	if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100))
-+		return MODE_CLOCK_HIGH;
-+
-+	return MODE_OK;
-+}
-+
- static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
-+	.mode_valid = vc4_hdmi_encoder_mode_valid,
- 	.disable = vc4_hdmi_encoder_disable,
- 	.enable = vc4_hdmi_encoder_enable,
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0180-drm-vc4-Add-support-for-DRM_FORMAT_RGB888-and-DRM_FO.patch b/target/linux/brcm2708/patches-4.14/950-0180-drm-vc4-Add-support-for-DRM_FORMAT_RGB888-and-DRM_FO.patch
deleted file mode 100644
index 5662a800f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0180-drm-vc4-Add-support-for-DRM_FORMAT_RGB888-and-DRM_FO.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From aeb5d9dfb4220360f5a0df416b9d8c4e908c977a Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 16 Nov 2017 14:22:29 +0000
-Subject: [PATCH 180/454] drm/vc4: Add support for DRM_FORMAT_RGB888 and
- DRM_FORMAT_BGR888
-
-Filling out the list of supported formats based on those the
-hardware can support.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/b551205d1c33fa49eef2c33ed2d60c5339b2f299.1510841336.git.dave.stevenson@raspberrypi.org
-(cherry picked from commit 88f8156fba43d040dc5af42f88db2c53d6c69443)
----
- drivers/gpu/drm/vc4/vc4_plane.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -121,6 +121,14 @@ static const struct hvs_format {
- 		.pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
- 	},
- 	{
-+		.drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
-+		.pixel_order = HVS_PIXEL_ORDER_XRGB, .has_alpha = false,
-+	},
-+	{
-+		.drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
-+		.pixel_order = HVS_PIXEL_ORDER_XBGR, .has_alpha = false,
-+	},
-+	{
- 		.drm = DRM_FORMAT_YUV422,
- 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
- 	},
diff --git a/target/linux/brcm2708/patches-4.14/950-0181-drm-vc4-Use-.pixel_order-instead-of-custom-.flip_cbc.patch b/target/linux/brcm2708/patches-4.14/950-0181-drm-vc4-Use-.pixel_order-instead-of-custom-.flip_cbc.patch
deleted file mode 100644
index 72b8d6564..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0181-drm-vc4-Use-.pixel_order-instead-of-custom-.flip_cbc.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From 954b81b93de3cc6baa9e2ebdd4e8dc7b63dab71a Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 16 Nov 2017 14:22:30 +0000
-Subject: [PATCH 181/454] drm/vc4: Use .pixel_order instead of custom
- .flip_cbcr
-
-The hardware has enums for altering the Cr and Cb order,
-so use this instead of having a flag which swaps the
-order the pointers are presented to the hardware
-(that only worked for 3 plane formats anyway).
-
-Explicitly sets .pixel_order in each case, rather than
-relying on then default XYCBCR order being a value 0.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/563872b69c1e5df142cb15ebfca7f20056b8a64c.1510841336.git.dave.stevenson@raspberrypi.org
-(cherry picked from commit 090cb0c690183be849e2bfa0427220f1e435fa30)
----
- drivers/gpu/drm/vc4/vc4_plane.c | 20 ++++++++------------
- 1 file changed, 8 insertions(+), 12 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -86,7 +86,6 @@ static const struct hvs_format {
- 	u32 hvs; /* HVS_FORMAT_* */
- 	u32 pixel_order;
- 	bool has_alpha;
--	bool flip_cbcr;
- } hvs_formats[] = {
- 	{
- 		.drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
-@@ -131,28 +130,32 @@ static const struct hvs_format {
- 	{
- 		.drm = DRM_FORMAT_YUV422,
- 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
-+		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,
- 	},
- 	{
- 		.drm = DRM_FORMAT_YVU422,
- 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
--		.flip_cbcr = true,
-+		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,
- 	},
- 	{
- 		.drm = DRM_FORMAT_YUV420,
- 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
-+		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,
- 	},
- 	{
- 		.drm = DRM_FORMAT_YVU420,
- 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
--		.flip_cbcr = true,
-+		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,
- 	},
- 	{
- 		.drm = DRM_FORMAT_NV12,
- 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
-+		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,
- 	},
- 	{
- 		.drm = DRM_FORMAT_NV16,
- 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
-+		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,
- 	},
- };
- 
-@@ -624,15 +627,8 @@ static int vc4_plane_mode_set(struct drm
- 	 * The pointers may be any byte address.
- 	 */
- 	vc4_state->ptr0_offset = vc4_state->dlist_count;
--	if (!format->flip_cbcr) {
--		for (i = 0; i < num_planes; i++)
--			vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
--	} else {
--		WARN_ON_ONCE(num_planes != 3);
--		vc4_dlist_write(vc4_state, vc4_state->offsets[0]);
--		vc4_dlist_write(vc4_state, vc4_state->offsets[2]);
--		vc4_dlist_write(vc4_state, vc4_state->offsets[1]);
--	}
-+	for (i = 0; i < num_planes; i++)
-+		vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
- 
- 	/* Pointer Context Word 0/1/2: Written by the HVS */
- 	for (i = 0; i < num_planes; i++)
diff --git a/target/linux/brcm2708/patches-4.14/950-0182-drm-vc4-Add-support-for-NV21-and-NV61.patch b/target/linux/brcm2708/patches-4.14/950-0182-drm-vc4-Add-support-for-NV21-and-NV61.patch
deleted file mode 100644
index b14d11783..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0182-drm-vc4-Add-support-for-NV21-and-NV61.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 4c974447d05dc0295676b2ba4554351bf77886f6 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 16 Nov 2017 14:22:31 +0000
-Subject: [PATCH 182/454] drm/vc4: Add support for NV21 and NV61.
-
-NV12 (YUV420 2 plane) and NV16 (YUV422 2 plane) were
-supported, but NV21 and NV61 (same but with Cb and Cr
-swapped) weren't. Add them.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/1f50799525e3401551dff2b0b2828b9ab892f75f.1510841336.git.dave.stevenson@raspberrypi.org
-(cherry picked from commit cb20dd170d6a7d41e0f347998771b0e0db183438)
----
- drivers/gpu/drm/vc4/vc4_plane.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -153,10 +153,20 @@ static const struct hvs_format {
- 		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,
- 	},
- 	{
-+		.drm = DRM_FORMAT_NV21,
-+		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
-+		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,
-+	},
-+	{
- 		.drm = DRM_FORMAT_NV16,
- 		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
- 		.pixel_order = HVS_PIXEL_ORDER_XYCBCR,
- 	},
-+	{
-+		.drm = DRM_FORMAT_NV61,
-+		.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
-+		.pixel_order = HVS_PIXEL_ORDER_XYCRCB,
-+	},
- };
- 
- static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
diff --git a/target/linux/brcm2708/patches-4.14/950-0183-BCM270X-Disable-VEC-unless-vc4-kms-v3d-is-present.patch b/target/linux/brcm2708/patches-4.14/950-0183-BCM270X-Disable-VEC-unless-vc4-kms-v3d-is-present.patch
deleted file mode 100644
index 6513996bf..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0183-BCM270X-Disable-VEC-unless-vc4-kms-v3d-is-present.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From a623333fb06d085d3fb3f802790164f7bc5c16e5 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Mon, 23 Jan 2017 11:41:54 -0800
-Subject: [PATCH 183/454] BCM270X: Disable VEC unless vc4-kms-v3d is present.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-(cherry picked from commit dabd52db47d2e799323639734787e3a338c2b2a5)
----
- arch/arm/boot/dts/bcm2708-rpi.dtsi                 | 4 ++++
- arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts | 7 +++++++
- 2 files changed, 11 insertions(+)
-
---- a/arch/arm/boot/dts/bcm2708-rpi.dtsi
-+++ b/arch/arm/boot/dts/bcm2708-rpi.dtsi
-@@ -160,3 +160,7 @@ sdhost_pins: &sdhost_gpio48 {
- &cpu_thermal {
- 	/delete-node/ trips;
- };
-+
-+&vec {
-+	status = "disabled";
-+};
---- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
-@@ -141,6 +141,13 @@
- 		};
- 	};
- 
-+	fragment@17 {
-+		target = <&vec>;
-+		__overlay__  {
-+			status = "okay";
-+		};
-+	};
-+
- 	__overrides__ {
- 		cma-256 = <0>,"+0-1-2-3-4";
- 		cma-192 = <0>,"-0+1-2-3-4";
diff --git a/target/linux/brcm2708/patches-4.14/950-0184-drm-vc4-Flush-the-caches-before-the-render-jobs-as-w.patch b/target/linux/brcm2708/patches-4.14/950-0184-drm-vc4-Flush-the-caches-before-the-render-jobs-as-w.patch
deleted file mode 100644
index 85f04fd76..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0184-drm-vc4-Flush-the-caches-before-the-render-jobs-as-w.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 5d35ff6d904bcbf00bee99ea493db47360e756bc Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Thu, 21 Dec 2017 13:32:09 -0800
-Subject: [PATCH 184/454] drm/vc4: Flush the caches before the render jobs, as
- well.
-
-If the frame samples from a render target that was just written, its
-cache flush during the binning step may have occurred before the
-previous frame's RCL was completed.  Flush the texture caches again
-before starting each RCL job to make sure that the sampling of the
-previous RCL's output is correct.
-
-Fixes flickering in the top left of 3DMMES Taiji.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Fixes: ca26d28bbaa3 ("drm/vc4: improve throughput by pipelining binning and rendering jobs")
----
- drivers/gpu/drm/vc4/vc4_gem.c | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_gem.c
-+++ b/drivers/gpu/drm/vc4/vc4_gem.c
-@@ -436,6 +436,19 @@ vc4_flush_caches(struct drm_device *dev)
- 		  VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
- }
- 
-+static void
-+vc4_flush_texture_caches(struct drm_device *dev)
-+{
-+	struct vc4_dev *vc4 = to_vc4_dev(dev);
-+
-+	V3D_WRITE(V3D_L2CACTL,
-+		  V3D_L2CACTL_L2CCLR);
-+
-+	V3D_WRITE(V3D_SLCACTL,
-+		  VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
-+		  VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC));
-+}
-+
- /* Sets the registers for the next job to be actually be executed in
-  * the hardware.
-  *
-@@ -474,6 +487,14 @@ vc4_submit_next_render_job(struct drm_de
- 	if (!exec)
- 		return;
- 
-+	/* A previous RCL may have written to one of our textures, and
-+	 * our full cache flush at bin time may have occurred before
-+	 * that RCL completed.  Flush the texture cache now, but not
-+	 * the instructions or uniforms (since we don't write those
-+	 * from an RCL).
-+	 */
-+	vc4_flush_texture_caches(dev);
-+
- 	submit_cl(dev, 1, exec->ct1ca, exec->ct1ea);
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0185-drm-vc4-Add-FB-modifier-support-to-firmwarekms.patch b/target/linux/brcm2708/patches-4.14/950-0185-drm-vc4-Add-FB-modifier-support-to-firmwarekms.patch
deleted file mode 100644
index afb096a1c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0185-drm-vc4-Add-FB-modifier-support-to-firmwarekms.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 37822018786bae32642f9e1dc7da980ebe86ccde Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 7 Jun 2017 14:39:49 -0700
-Subject: [PATCH 185/454] drm/vc4: Add FB modifier support to firmwarekms.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-(cherry picked from commit 11752d73488e08aaeb65fe8289a9c016acde26c2)
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -17,6 +17,7 @@
- #include "drm/drm_atomic_helper.h"
- #include "drm/drm_plane_helper.h"
- #include "drm/drm_crtc_helper.h"
-+#include "drm/drm_fourcc.h"
- #include "linux/clk.h"
- #include "linux/debugfs.h"
- #include "drm/drm_fb_cma_helper.h"
-@@ -135,6 +136,10 @@ static void vc4_primary_plane_atomic_upd
- 	fbinfo->yoffset = state->crtc_y;
- 	fbinfo->base = bo->paddr + fb->offsets[0];
- 	fbinfo->pitch = fb->pitches[0];
-+
-+	if (fb->modifier == DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED)
-+		fbinfo->bpp |= BIT(31);
-+
- 	/* A bug in the firmware makes it so that if the fb->base is
- 	 * set to nonzero, the configured pitch gets overwritten with
- 	 * the previous pitch.  So, to get the configured pitch
diff --git a/target/linux/brcm2708/patches-4.14/950-0186-drm-vc4-Add-missing-enable-disable-vblank-handlers-i.patch b/target/linux/brcm2708/patches-4.14/950-0186-drm-vc4-Add-missing-enable-disable-vblank-handlers-i.patch
deleted file mode 100644
index a9ff9c825..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0186-drm-vc4-Add-missing-enable-disable-vblank-handlers-i.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From d15f2c268d1e5e97fbda9b80b3b9fefe7de2ff44 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Tue, 30 Jan 2018 14:21:02 -0800
-Subject: [PATCH 186/454] drm/vc4: Add missing enable/disable vblank handlers
- in fkms.
-
-Fixes hang at boot in 4.14.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_crtc.c         | 14 --------------
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 15 +++++++++++++++
- 2 files changed, 15 insertions(+), 14 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_crtc.c
-+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
-@@ -685,15 +685,8 @@ static void vc4_crtc_atomic_flush(struct
- 
- static int vc4_enable_vblank(struct drm_crtc *crtc)
- {
--	struct drm_device *dev = crtc->dev;
--	struct vc4_dev *vc4 = to_vc4_dev(dev);
- 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- 
--	if (vc4->firmware_kms) {
--		/* XXX: Can we mask the SMI interrupt? */
--		return 0;
--	}
--
- 	CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
- 
- 	return 0;
-@@ -701,15 +694,8 @@ static int vc4_enable_vblank(struct drm_
- 
- static void vc4_disable_vblank(struct drm_crtc *crtc)
- {
--	struct drm_device *dev = crtc->dev;
--	struct vc4_dev *vc4 = to_vc4_dev(dev);
- 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- 
--	if (vc4->firmware_kms) {
--		/* XXX: Can we mask the SMI interrupt? */
--		return;
--	}
--
- 	CRTC_WRITE(PV_INTEN, 0);
- }
- 
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -441,6 +441,19 @@ static int vc4_page_flip(struct drm_crtc
- 	return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
- }
- 
-+static int vc4_fkms_enable_vblank(struct drm_crtc *crtc)
-+{
-+	/* XXX: Need a way to enable/disable the interrupt, to avoid
-+	 * DRM warnings at boot time.
-+	 */
-+
-+	return 0;
-+}
-+
-+static void vc4_fkms_disable_vblank(struct drm_crtc *crtc)
-+{
-+}
-+
- static const struct drm_crtc_funcs vc4_crtc_funcs = {
- 	.set_config = drm_atomic_helper_set_config,
- 	.destroy = drm_crtc_cleanup,
-@@ -451,6 +464,8 @@ static const struct drm_crtc_funcs vc4_c
- 	.reset = drm_atomic_helper_crtc_reset,
- 	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
- 	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
-+	.enable_vblank = vc4_fkms_enable_vblank,
-+	.disable_vblank = vc4_fkms_disable_vblank,
- };
- 
- static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
diff --git a/target/linux/brcm2708/patches-4.14/950-0187-drm-vc4-Fix-warning-about-vblank-interrupts-before-D.patch b/target/linux/brcm2708/patches-4.14/950-0187-drm-vc4-Fix-warning-about-vblank-interrupts-before-D.patch
deleted file mode 100644
index 9f3dd089a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0187-drm-vc4-Fix-warning-about-vblank-interrupts-before-D.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 5d82a7419bcf798ecc9aa3a140e6a41c486c3bdf Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Mon, 5 Feb 2018 18:01:02 +0000
-Subject: [PATCH 187/454] drm/vc4: Fix warning about vblank interrupts before
- DRM core is ready.
-
-The SMICS interrupt fires continuously, but since it's 1/100 the rate
-of the USB interrupts, we don't really need a way to turn it off.  We
-do need to make sure that we don't tell DRM about it until DRM has
-asked for the interrupt at least once, because otherwise it will throw
-a warning at boot time.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 10 ++++++----
- 1 file changed, 6 insertions(+), 4 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -43,6 +43,7 @@ struct vc4_crtc {
- 
- 	struct drm_pending_vblank_event *event;
- 	u32 overscan[4];
-+	bool vblank_enabled;
- };
- 
- static inline struct vc4_crtc *to_vc4_crtc(struct drm_crtc *crtc)
-@@ -420,7 +421,8 @@ static irqreturn_t vc4_crtc_irq_handler(
- 
- 	if (stat & SMICS_INTERRUPTS) {
- 		writel(0, vc4_crtc->regs + SMICS);
--		drm_crtc_handle_vblank(&vc4_crtc->base);
-+		if (vc4_crtc->vblank_enabled)
-+			drm_crtc_handle_vblank(&vc4_crtc->base);
- 		vc4_crtc_handle_page_flip(vc4_crtc);
- 		ret = IRQ_HANDLED;
- 	}
-@@ -443,9 +445,9 @@ static int vc4_page_flip(struct drm_crtc
- 
- static int vc4_fkms_enable_vblank(struct drm_crtc *crtc)
- {
--	/* XXX: Need a way to enable/disable the interrupt, to avoid
--	 * DRM warnings at boot time.
--	 */
-+	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
-+
-+	vc4_crtc->vblank_enabled = true;
- 
- 	return 0;
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0188-drm-vc4-Skip-SET_CURSOR_INFO-when-the-cursor-content.patch b/target/linux/brcm2708/patches-4.14/950-0188-drm-vc4-Skip-SET_CURSOR_INFO-when-the-cursor-content.patch
deleted file mode 100644
index dcadc3bd8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0188-drm-vc4-Skip-SET_CURSOR_INFO-when-the-cursor-content.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 762daa086f5f91aa9a3064f0e6df9017a24f8d62 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Mon, 5 Feb 2018 18:02:30 +0000
-Subject: [PATCH 188/454] drm/vc4: Skip SET_CURSOR_INFO when the cursor
- contents didn't change.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 30 +++++++++++++++++---------
- 1 file changed, 20 insertions(+), 10 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -204,10 +204,6 @@ static void vc4_cursor_plane_atomic_upda
- 		state->crtc_y,
- 		0
- 	};
--	u32 packet_info[] = { state->crtc_w, state->crtc_h,
--			      0, /* unused */
--			      bo->paddr + fb->offsets[0],
--			      0, 0, /* hotx, hoty */};
- 	WARN_ON_ONCE(fb->pitches[0] != state->crtc_w * 4);
- 
- 	DRM_DEBUG_ATOMIC("[PLANE:%d:%s] update %dx%d cursor at %d,%d (0x%08x/%d)",
-@@ -232,12 +228,26 @@ static void vc4_cursor_plane_atomic_upda
- 	if (ret || packet_state[0] != 0)
- 		DRM_ERROR("Failed to set cursor state: 0x%08x\n", packet_state[0]);
- 
--	ret = rpi_firmware_property(vc4->firmware,
--				    RPI_FIRMWARE_SET_CURSOR_INFO,
--				    &packet_info,
--				    sizeof(packet_info));
--	if (ret || packet_info[0] != 0)
--		DRM_ERROR("Failed to set cursor info: 0x%08x\n", packet_info[0]);
-+	/* Note: When the cursor contents change, the modesetting
-+	 * driver calls drm_mode_cursor_univeral() with
-+	 * DRM_MODE_CURSOR_BO, which means a new fb will be allocated.
-+	 */
-+	if (!old_state ||
-+	    state->crtc_w != old_state->crtc_w ||
-+	    state->crtc_h != old_state->crtc_h ||
-+	    fb != old_state->fb) {
-+		u32 packet_info[] = { state->crtc_w, state->crtc_h,
-+				      0, /* unused */
-+				      bo->paddr + fb->offsets[0],
-+				      0, 0, /* hotx, hoty */};
-+
-+		ret = rpi_firmware_property(vc4->firmware,
-+					    RPI_FIRMWARE_SET_CURSOR_INFO,
-+					    &packet_info,
-+					    sizeof(packet_info));
-+		if (ret || packet_info[0] != 0)
-+			DRM_ERROR("Failed to set cursor info: 0x%08x\n", packet_info[0]);
-+	}
- }
- 
- static void vc4_cursor_plane_atomic_disable(struct drm_plane *plane,
diff --git a/target/linux/brcm2708/patches-4.14/950-0189-drm-vc4-Remove-duplicate-primary-cursor-fields-from-.patch b/target/linux/brcm2708/patches-4.14/950-0189-drm-vc4-Remove-duplicate-primary-cursor-fields-from-.patch
deleted file mode 100644
index 2f215c33c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0189-drm-vc4-Remove-duplicate-primary-cursor-fields-from-.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From cb4fe9fe655a0d6685be00e926842a25bc48b920 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Mon, 5 Feb 2018 18:22:03 +0000
-Subject: [PATCH 189/454] drm/vc4: Remove duplicate primary/cursor fields from
- FKMS driver.
-
-The CRTC has those fields and we can just use them.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 24 +++++++-----------------
- 1 file changed, 7 insertions(+), 17 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
-@@ -37,8 +37,6 @@ struct vc4_crtc {
- 	struct drm_crtc base;
- 	struct drm_encoder *encoder;
- 	struct drm_connector *connector;
--	struct drm_plane *primary;
--	struct drm_plane *cursor;
- 	void __iomem *regs;
- 
- 	struct drm_pending_vblank_event *event;
-@@ -356,29 +354,24 @@ static void vc4_crtc_mode_set_nofb(struc
- 
- static void vc4_crtc_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
- {
--	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
--
- 	/* Always turn the planes off on CRTC disable. In DRM, planes
- 	 * are enabled/disabled through the update/disable hooks
- 	 * above, and the CRTC enable/disable independently controls
- 	 * whether anything scans out at all, but the firmware doesn't
- 	 * give us a CRTC-level control for that.
- 	 */
--	vc4_cursor_plane_atomic_disable(vc4_crtc->cursor,
--					vc4_crtc->cursor->state);
--	vc4_plane_set_primary_blank(vc4_crtc->primary, true);
-+	vc4_cursor_plane_atomic_disable(crtc->cursor, crtc->cursor->state);
-+	vc4_plane_set_primary_blank(crtc->primary, true);
- }
- 
- static void vc4_crtc_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
- {
--	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
--
- 	/* Unblank the planes (if they're supposed to be displayed). */
--	if (vc4_crtc->primary->state->fb)
--		vc4_plane_set_primary_blank(vc4_crtc->primary, false);
--	if (vc4_crtc->cursor->state->fb) {
--		vc4_cursor_plane_atomic_update(vc4_crtc->cursor,
--					       vc4_crtc->cursor->state);
-+	if (crtc->primary->state->fb)
-+		vc4_plane_set_primary_blank(crtc->primary, false);
-+	if (crtc->cursor->state->fb) {
-+		vc4_cursor_plane_atomic_update(crtc->cursor,
-+					       crtc->cursor->state);
- 	}
- }
- 
-@@ -689,9 +682,6 @@ static int vc4_fkms_bind(struct device *
- 	primary_plane->crtc = crtc;
- 	cursor_plane->crtc = crtc;
- 
--	vc4_crtc->primary = primary_plane;
--	vc4_crtc->cursor = cursor_plane;
--
- 	vc4_encoder = devm_kzalloc(dev, sizeof(*vc4_encoder), GFP_KERNEL);
- 	if (!vc4_encoder)
- 		return -ENOMEM;
diff --git a/target/linux/brcm2708/patches-4.14/950-0190-drm-vc4-Don-t-wait-for-vblank-on-fkms-cursor-updates.patch b/target/linux/brcm2708/patches-4.14/950-0190-drm-vc4-Don-t-wait-for-vblank-on-fkms-cursor-updates.patch
deleted file mode 100644
index cee57a57c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0190-drm-vc4-Don-t-wait-for-vblank-on-fkms-cursor-updates.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 2c77eedbc7d668d128af3bec2633d55e01c9e67c Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Mon, 5 Feb 2018 18:53:18 +0000
-Subject: [PATCH 190/454] drm/vc4: Don't wait for vblank on fkms cursor
- updates.
-
-We don't use the same async update path between fkms and normal kms,
-and the normal kms workaround ended up making us wait.  This became a
-larger problem in rpi-4.14.y, as the USB HID update rate throttling
-got (accidentally?) dropped.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_kms.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/vc4/vc4_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_kms.c
-@@ -53,7 +53,8 @@ vc4_atomic_complete_commit(struct drm_at
- 	 * display lists before we free it and potentially reallocate
- 	 * and overwrite the dlist memory with a new modeset.
- 	 */
--	state->legacy_cursor_update = false;
-+	if (!vc4->firmware_kms)
-+		state->legacy_cursor_update = false;
- 
- 	drm_atomic_helper_commit_hw_done(state);
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0191-config-Add-SND_USB_HIFACE-m.patch b/target/linux/brcm2708/patches-4.14/950-0191-config-Add-SND_USB_HIFACE-m.patch
deleted file mode 100644
index 0bebf9731..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0191-config-Add-SND_USB_HIFACE-m.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 6cec997da72fcd729caeac384421f0419aed3020 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 5 Feb 2018 10:37:54 +0000
-Subject: [PATCH 191/454] config: Add SND_USB_HIFACE=m
-
-See: https://github.com/raspberrypi/linux/issues/2368
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -864,6 +864,7 @@ CONFIG_SND_USB_UA101=m
- CONFIG_SND_USB_CAIAQ=m
- CONFIG_SND_USB_CAIAQ_INPUT=y
- CONFIG_SND_USB_6FIRE=m
-+CONFIG_SND_USB_HIFACE=m
- CONFIG_SND_SOC=m
- CONFIG_SND_BCM2835_SOC_I2S=m
- CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -857,6 +857,7 @@ CONFIG_SND_USB_UA101=m
- CONFIG_SND_USB_CAIAQ=m
- CONFIG_SND_USB_CAIAQ_INPUT=y
- CONFIG_SND_USB_6FIRE=m
-+CONFIG_SND_USB_HIFACE=m
- CONFIG_SND_SOC=m
- CONFIG_SND_BCM2835_SOC_I2S=m
- CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0192-mmc-bcm2835-sdhost-Add-include.patch b/target/linux/brcm2708/patches-4.14/950-0192-mmc-bcm2835-sdhost-Add-include.patch
deleted file mode 100644
index eb6d8988d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0192-mmc-bcm2835-sdhost-Add-include.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 64f105cdec2f536a6893b4a2c9b711d21b327821 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 5 Feb 2018 09:35:01 +0000
-Subject: [PATCH 192/454] mmc: bcm2835-sdhost: Add include
-
-highmem.h (needed for kmap_atomic) is pulled in by one of the other
-include files, but only with some CONFIG settings. Make the inclusion
-explicit to cater for cases where the CONFIG setting is absent.
-
-See: https://github.com/raspberrypi/linux/issues/2366
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/mmc/host/bcm2835-sdhost.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mmc/host/bcm2835-sdhost.c
-+++ b/drivers/mmc/host/bcm2835-sdhost.c
-@@ -52,6 +52,7 @@
- #include <linux/time.h>
- #include <linux/workqueue.h>
- #include <linux/interrupt.h>
-+#include <linux/highmem.h>
- #include <soc/bcm2835/raspberrypi-firmware.h>
- 
- /* For mmc_card_blockaddr */
diff --git a/target/linux/brcm2708/patches-4.14/950-0193-hid-Reduce-default-mouse-polling-interval-to-60Hz.patch b/target/linux/brcm2708/patches-4.14/950-0193-hid-Reduce-default-mouse-polling-interval-to-60Hz.patch
deleted file mode 100644
index b211cb8d3..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0193-hid-Reduce-default-mouse-polling-interval-to-60Hz.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From cbfc3e48b94fdb14c5d8d2cc420ff6a4ad8fd39f Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Mon, 14 Jul 2014 22:02:09 +0100
-Subject: [PATCH 193/454] hid: Reduce default mouse polling interval to 60Hz
-
-Reduces overhead when using X
----
- drivers/hid/usbhid/hid-core.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/hid/usbhid/hid-core.c
-+++ b/drivers/hid/usbhid/hid-core.c
-@@ -48,7 +48,7 @@
-  * Module parameters.
-  */
- 
--static unsigned int hid_mousepoll_interval;
-+static unsigned int hid_mousepoll_interval = ~0;
- module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644);
- MODULE_PARM_DESC(mousepoll, "Polling interval of mice");
- 
-@@ -1098,7 +1098,9 @@ static int usbhid_start(struct hid_devic
- 		/* Change the polling interval of mice and joysticks. */
- 		switch (hid->collection->usage) {
- 		case HID_GD_MOUSE:
--			if (hid_mousepoll_interval > 0)
-+			if (hid_mousepoll_interval == ~0 && interval < 16)
-+				interval = 16;
-+			else if (hid_mousepoll_interval != ~0 && hid_mousepoll_interval != 0)
- 				interval = hid_mousepoll_interval;
- 			break;
- 		case HID_GD_JOYSTICK:
diff --git a/target/linux/brcm2708/patches-4.14/950-0194-BCM270X_DT-Minor-cosmetic-DT-tidy.patch b/target/linux/brcm2708/patches-4.14/950-0194-BCM270X_DT-Minor-cosmetic-DT-tidy.patch
deleted file mode 100644
index f118bb2b8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0194-BCM270X_DT-Minor-cosmetic-DT-tidy.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 64a33f1beb4afc4b1b382fdadd6ac79a837a5e6f Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 6 Feb 2018 11:48:17 +0000
-Subject: [PATCH 194/454] BCM270X_DT: Minor cosmetic DT tidy
-
-Deleting the timer node for all bcm27* DTBs than re-adding an identical
-one for bcm2708 is wrong - just delete it where it isn't wanted.
-
-Also change a #include to match the style of similar includes.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm2708.dtsi | 9 ---------
- arch/arm/boot/dts/bcm2709.dtsi | 2 ++
- arch/arm/boot/dts/bcm270x.dtsi | 4 +---
- arch/arm/boot/dts/bcm2710.dtsi | 2 ++
- 4 files changed, 5 insertions(+), 12 deletions(-)
-
---- a/arch/arm/boot/dts/bcm2708.dtsi
-+++ b/arch/arm/boot/dts/bcm2708.dtsi
-@@ -3,15 +3,6 @@
- #include "bcm2708-rpi.dtsi"
- 
- / {
--	soc {
--		timer@7e003000 {
--			compatible = "brcm,bcm2835-system-timer";
--			reg = <0x7e003000 0x1000>;
--			interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
--			clock-frequency = <1000000>;
--		};
--	};
--
- 	/delete-node/ cpus;
- 
- 	__overrides__ {
---- a/arch/arm/boot/dts/bcm2709.dtsi
-+++ b/arch/arm/boot/dts/bcm2709.dtsi
-@@ -6,6 +6,8 @@
- 	soc {
- 		ranges = <0x7e000000 0x3f000000 0x01000000>,
- 		         <0x40000000 0x40000000 0x00040000>;
-+
-+		/delete-node/ timer@7e003000;
- 	};
- 
- 	__overrides__ {
---- a/arch/arm/boot/dts/bcm270x.dtsi
-+++ b/arch/arm/boot/dts/bcm270x.dtsi
-@@ -1,5 +1,5 @@
- /* Downstream bcm283x.dtsi diff */
--#include "dt-bindings/power/raspberrypi-power.h"
-+#include <dt-bindings/power/raspberrypi-power.h>
- 
- / {
- 	chosen {
-@@ -8,8 +8,6 @@
- 
- 	soc: soc {
- 
--		/delete-node/ timer@7e003000;
--
- 		watchdog: watchdog@7e100000 {
- 			/* Add alias */
- 		};
---- a/arch/arm/boot/dts/bcm2710.dtsi
-+++ b/arch/arm/boot/dts/bcm2710.dtsi
-@@ -16,6 +16,8 @@
- 			interrupt-parent = <&local_intc>;
- 			interrupts = <9>;
- 		};
-+
-+		/delete-node/ timer@7e003000;
- 	};
- 
- 	__overrides__ {
diff --git a/target/linux/brcm2708/patches-4.14/950-0195-BCM270X_DT-More-cosmetic-DT-changes.patch b/target/linux/brcm2708/patches-4.14/950-0195-BCM270X_DT-More-cosmetic-DT-changes.patch
deleted file mode 100644
index bf0da352d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0195-BCM270X_DT-More-cosmetic-DT-changes.patch
+++ /dev/null
@@ -1,187 +0,0 @@
-From 6f6916802d79d16acd3339f96a2d87da52fa1ad1 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 6 Feb 2018 13:10:09 +0000
-Subject: [PATCH 195/454] BCM270X_DT: More cosmetic DT changes
-
-Remove unnecessary duplicate labels (but keep spi0).
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm2708-rpi.dtsi            |  5 ----
- arch/arm/boot/dts/bcm270x.dtsi                | 15 ++++------
- .../dts/overlays/vc4-fkms-v3d-overlay.dts     |  2 +-
- .../boot/dts/overlays/vc4-kms-v3d-overlay.dts | 29 +++++++------------
- 4 files changed, 17 insertions(+), 34 deletions(-)
-
---- a/arch/arm/boot/dts/bcm2708-rpi.dtsi
-+++ b/arch/arm/boot/dts/bcm2708-rpi.dtsi
-@@ -81,11 +81,6 @@
- 			status = "okay";
- 		};
- 
--		thermal: thermal@7e212000 {
--			#thermal-sensor-cells = <0>;
--			status = "okay";
--		};
--
- 		/* Onboard audio */
- 		audio: audio {
- 			compatible = "brcm,bcm2835-audio";
---- a/arch/arm/boot/dts/bcm270x.dtsi
-+++ b/arch/arm/boot/dts/bcm270x.dtsi
-@@ -12,10 +12,6 @@
- 			/* Add alias */
- 		};
- 
--		cprman: cprman@7e101000 {
--			/* Add alias */
--		};
--
- 		random: rng@7e104000 {
- 			/* Add alias */
- 		};
-@@ -94,7 +90,7 @@
- 			reg = <0x7e600000 0x100>;
- 			interrupts = <2 16>;
- 			clocks = <&clocks BCM2835_CLOCK_SMI>;
--			assigned-clocks = <&cprman BCM2835_CLOCK_SMI>;
-+			assigned-clocks = <&clocks BCM2835_CLOCK_SMI>;
- 			assigned-clock-rates = <125000000>;
- 			dmas = <&dma 4>;
- 			dma-names = "rx-tx";
-@@ -124,11 +120,6 @@
- 			status = "disabled";
- 		};
- 
--		gpu: gpu {
--			/* Add alias */
--			status = "disabled";
--		};
--
- 		axiperf: axiperf {
- 			compatible = "brcm,bcm2835-axiperf";
- 			reg = <0x7e009800 0x100>,
-@@ -177,3 +168,7 @@
- 	interrupt-parent = <&aux>;
- 	interrupts = <2>;
- };
-+
-+&vc4 {
-+	status = "disabled";
-+};
---- a/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts
-@@ -66,7 +66,7 @@
- 	};
- 
- 	fragment@8 {
--		target = <&gpu>;
-+		target = <&vc4>;
- 		__overlay__  {
- 			status = "okay";
- 		};
---- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
-@@ -53,20 +53,13 @@
- 	};
- 
- 	fragment@6 {
--		target = <&cprman>;
--		__overlay__  {
--			status = "okay";
--		};
--	};
--
--	fragment@7 {
- 		target = <&fb>;
- 		__overlay__  {
- 			status = "disabled";
- 		};
- 	};
- 
--	fragment@8 {
-+	fragment@7 {
- 		target = <&pixelvalve0>;
- 		__overlay__  {
- 			interrupts = <2 13>; /* pwa0 */
-@@ -74,7 +67,7 @@
- 		};
- 	};
- 
--	fragment@9 {
-+	fragment@8 {
- 		target = <&pixelvalve1>;
- 		__overlay__  {
- 			interrupts = <2 14>; /* pwa1 */
-@@ -82,7 +75,7 @@
- 		};
- 	};
- 
--	fragment@10 {
-+	fragment@9 {
- 		target = <&pixelvalve2>;
- 		__overlay__  {
- 			interrupts = <2 10>; /* pixelvalve */
-@@ -90,7 +83,7 @@
- 		};
- 	};
- 
--	fragment@11 {
-+	fragment@10 {
- 		target = <&hvs>;
- 		__overlay__  {
- 			interrupts = <2 1>;
-@@ -98,7 +91,7 @@
- 		};
- 	};
- 
--	fragment@12 {
-+	fragment@11 {
- 		target = <&hdmi>;
- 		__overlay__  {
- 			interrupts = <2 8>, <2 9>;
-@@ -106,7 +99,7 @@
- 		};
- 	};
- 
--	fragment@13 {
-+	fragment@12 {
- 		target = <&v3d>;
- 		__overlay__  {
- 			interrupts = <1 10>;
-@@ -114,14 +107,14 @@
- 		};
- 	};
- 
--	fragment@14 {
--		target = <&gpu>;
-+	fragment@13 {
-+		target = <&vc4>;
- 		__overlay__  {
- 			status = "okay";
- 		};
- 	};
- 
--	fragment@15 {
-+	fragment@14 {
- 		target-path = "/soc/dma";
- 		__overlay__ {
- 			brcm,dma-channel-mask = <0x7f35>;
-@@ -129,7 +122,7 @@
- 	};
- 
- 
--	fragment@16 {
-+	fragment@15 {
- 		target = <&clocks>;
- 		__overlay__  {
- 			claim-clocks = <
-@@ -141,7 +134,7 @@
- 		};
- 	};
- 
--	fragment@17 {
-+	fragment@16 {
- 		target = <&vec>;
- 		__overlay__  {
- 			status = "okay";
diff --git a/target/linux/brcm2708/patches-4.14/950-0196-config-enable-Audio-Graph-Card-module.patch b/target/linux/brcm2708/patches-4.14/950-0196-config-enable-Audio-Graph-Card-module.patch
deleted file mode 100644
index 94f4f0f40..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0196-config-enable-Audio-Graph-Card-module.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 860d9058a2a2c95d7c9638530a1fc167ea73481d Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Tue, 6 Feb 2018 15:37:22 +0100
-Subject: [PATCH 196/454] config: enable Audio Graph Card module
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -898,6 +898,7 @@ CONFIG_SND_SOC_AK4554=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
-+CONFIG_SND_AUDIO_GRAPH_CARD=m
- CONFIG_HID_BATTERY_STRENGTH=y
- CONFIG_HIDRAW=y
- CONFIG_UHID=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -891,6 +891,7 @@ CONFIG_SND_SOC_AK4554=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
-+CONFIG_SND_AUDIO_GRAPH_CARD=m
- CONFIG_HID_BATTERY_STRENGTH=y
- CONFIG_HIDRAW=y
- CONFIG_UHID=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0197-Add-missing-SND_PISOUND-selects-dependency-to-SND_RA.patch b/target/linux/brcm2708/patches-4.14/950-0197-Add-missing-SND_PISOUND-selects-dependency-to-SND_RA.patch
deleted file mode 100644
index 07057c53e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0197-Add-missing-SND_PISOUND-selects-dependency-to-SND_RA.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 6f45fac549af94803eec6278b11b153d11d95d26 Mon Sep 17 00:00:00 2001
-From: Simon van der Veldt <simon.vanderveldt@gmail.com>
-Date: Tue, 6 Feb 2018 15:36:25 +0100
-Subject: [PATCH 197/454] Add missing SND_PISOUND selects dependency to
- SND_RAWMIDI
-
-Without it the Pisound module fails to compile.
-See https://github.com/raspberrypi/linux/issues/2366
-
-Signed-off-by: Simon van der Veldt <simon.vanderveldt@gmail.com>
----
- sound/soc/bcm/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -193,5 +193,6 @@ config SND_BCM2708_SOC_FE_PI_AUDIO
- config SND_PISOUND
- 	tristate "Support for Blokas Labs pisound"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_RAWMIDI
- 	help
- 	  Say Y or M if you want to add support for Blokas Labs pisound.
diff --git a/target/linux/brcm2708/patches-4.14/950-0198-BCM2835-V4L2-Ensure-H264-header-bytes-get-a-sensible.patch b/target/linux/brcm2708/patches-4.14/950-0198-BCM2835-V4L2-Ensure-H264-header-bytes-get-a-sensible.patch
deleted file mode 100644
index 02bfe1476..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0198-BCM2835-V4L2-Ensure-H264-header-bytes-get-a-sensible.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 9b3e8f10d89d6c580eab3340fb1b954f99165b40 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 13 Feb 2017 11:10:50 +0000
-Subject: [PATCH 198/454] BCM2835-V4L2: Ensure H264 header bytes get a sensible
- timestamp
-
-H264 header come off VC with 0 timestamps, which means they get a
-strange timestamp when processed with VC/kernel start times,
-particularly if used with the inline header option.
-Remember the last frame timestamp and use that if set, or otherwise
-use the kernel start time.
-
-https://github.com/raspberrypi/linux/issues/1836
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 30 +++++++++++++++++--
- .../bcm2835-camera/bcm2835-camera.h           |  2 ++
- 2 files changed, 29 insertions(+), 3 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -341,8 +341,13 @@ static void buffer_cb(struct vchiq_mmal_
- 		}
- 	} else {
- 		if (dev->capture.frame_count) {
--			if (dev->capture.vc_start_timestamp != -1 &&
--			    pts != 0) {
-+			if (dev->capture.vc_start_timestamp == -1) {
-+				buf->vb.vb2_buf.timestamp = ktime_get_ns();
-+				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+				 "Buffer time set as current time - %lld",
-+				 buf->vb.vb2_buf.timestamp);
-+
-+			} else if(pts != 0) {
- 				struct timeval timestamp;
- 				s64 runtime_us = pts -
- 				    dev->capture.vc_start_timestamp;
-@@ -375,10 +380,27 @@ static void buffer_cb(struct vchiq_mmal_
- 				buf->vb.vb2_buf.timestamp = timestamp.tv_sec * 1000000000ULL +
- 					timestamp.tv_usec * 1000ULL;
- 			} else {
--				buf->vb.vb2_buf.timestamp = ktime_get_ns();
-+				if (dev->capture.last_timestamp) {
-+					buf->vb.vb2_buf.timestamp = dev->capture.last_timestamp;
-+					v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+					 "Buffer time set as last timestamp - %lld",
-+					 buf->vb.vb2_buf.timestamp);
-+				}
-+				else {
-+					buf->vb.vb2_buf.timestamp =
-+					dev->capture.kernel_start_ts.tv_sec  * 1000000000ULL +
-+					dev->capture.kernel_start_ts.tv_usec * 1000ULL;
-+					v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+					 "Buffer time set as start timestamp - %lld",
-+					 buf->vb.vb2_buf.timestamp);
-+				}
- 			}
-+			dev->capture.last_timestamp = buf->vb.vb2_buf.timestamp;
- 
- 			vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length);
-+			v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+				"Buffer has ts %llu",
-+				dev->capture.last_timestamp);
- 			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
- 
- 			if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS &&
-@@ -547,6 +569,8 @@ static int start_streaming(struct vb2_qu
- 			 "Start time %lld size %d\n",
- 			 dev->capture.vc_start_timestamp, parameter_size);
- 
-+	dev->capture.last_timestamp = 0;
-+
- 	v4l2_get_timestamp(&dev->capture.kernel_start_ts);
- 
- 	/* enable the camera port */
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-@@ -93,6 +93,8 @@ struct bm2835_mmal_dev {
- 		s64         vc_start_timestamp;
- 		/* Kernel start timestamp for streaming */
- 		struct timeval kernel_start_ts;
-+		/* Timestamp of last frame */
-+		u64 		last_timestamp;
- 
- 		struct vchiq_mmal_port  *port; /* port being used for capture */
- 		/* camera port being used for capture */
diff --git a/target/linux/brcm2708/patches-4.14/950-0199-BCM2835-V4L2-Correctly-denote-key-frames-in-encoded-.patch b/target/linux/brcm2708/patches-4.14/950-0199-BCM2835-V4L2-Correctly-denote-key-frames-in-encoded-.patch
deleted file mode 100644
index 1c1d132a5..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0199-BCM2835-V4L2-Correctly-denote-key-frames-in-encoded-.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From e60ac10439b458805c8eba5bd209b51045f944b6 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 13 Feb 2017 13:11:41 +0000
-Subject: [PATCH 199/454] BCM2835-V4L2: Correctly denote key frames in encoded
- data
-
-Forward MMAL key frame flags to the V4L2 buffers.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -398,6 +398,9 @@ static void buffer_cb(struct vchiq_mmal_
- 			dev->capture.last_timestamp = buf->vb.vb2_buf.timestamp;
- 
- 			vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length);
-+			if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_KEYFRAME)
-+				buf->vb.flags |= V4L2_BUF_FLAG_KEYFRAME;
-+
- 			v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
- 				"Buffer has ts %llu",
- 				dev->capture.last_timestamp);
diff --git a/target/linux/brcm2708/patches-4.14/950-0200-bcm2835-camera-Fix-timestamp-calculation-problem-221.patch b/target/linux/brcm2708/patches-4.14/950-0200-bcm2835-camera-Fix-timestamp-calculation-problem-221.patch
deleted file mode 100644
index 9da6ac464..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0200-bcm2835-camera-Fix-timestamp-calculation-problem-221.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From aa6e148bb75f76291e9625316f1f7c73458daf47 Mon Sep 17 00:00:00 2001
-From: David H <davidjhu@gmail.com>
-Date: Wed, 4 Oct 2017 04:43:07 -0700
-Subject: [PATCH 200/454] bcm2835-camera: Fix timestamp calculation problem
- (#2214)
-
-* bcm2835-camera: Fix timestamp calculation problem
-
-Use div_s64_rem() to convert usec timestamp to timeval
-to avoid integer signedness bug.
-
-* bcm2835-camera: Store kernel start time in NSEC instead of USEC
-
-* bcm2835-camera: Reword debug message for clarity
----
- .../bcm2835-camera/bcm2835-camera.c           | 41 +++++--------------
- .../bcm2835-camera/bcm2835-camera.h           |  2 +-
- 2 files changed, 11 insertions(+), 32 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -348,37 +348,17 @@ static void buffer_cb(struct vchiq_mmal_
- 				 buf->vb.vb2_buf.timestamp);
- 
- 			} else if(pts != 0) {
--				struct timeval timestamp;
- 				s64 runtime_us = pts -
- 				    dev->capture.vc_start_timestamp;
--				u32 div = 0;
--				u32 rem = 0;
--
--				div =
--				    div_u64_rem(runtime_us, USEC_PER_SEC, &rem);
--				timestamp.tv_sec =
--				    dev->capture.kernel_start_ts.tv_sec + div;
--				timestamp.tv_usec =
--				    dev->capture.kernel_start_ts.tv_usec + rem;
--
--				if (timestamp.tv_usec >=
--				    USEC_PER_SEC) {
--					timestamp.tv_sec++;
--					timestamp.tv_usec -=
--					    USEC_PER_SEC;
--				}
-+				buf->vb.vb2_buf.timestamp = (runtime_us * NSEC_PER_USEC) +
-+				    dev->capture.kernel_start_timestamp;
- 				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--					 "Convert start time %d.%06d and %llu "
--					 "with offset %llu to %d.%06d\n",
--					 (int)dev->capture.kernel_start_ts.
--					 tv_sec,
--					 (int)dev->capture.kernel_start_ts.
--					 tv_usec,
--					 dev->capture.vc_start_timestamp, pts,
--					 (int)timestamp.tv_sec,
--					 (int)timestamp.tv_usec);
--				buf->vb.vb2_buf.timestamp = timestamp.tv_sec * 1000000000ULL +
--					timestamp.tv_usec * 1000ULL;
-+					 "Buffer time set as converted timestamp - %llu "
-+					 "= (pts [%lld usec] - vc start time [%llu usec]) "
-+					 "+ kernel start time [%llu nsec]\n",
-+					 buf->vb.vb2_buf.timestamp,
-+					 pts, dev->capture.vc_start_timestamp,
-+					 dev->capture.kernel_start_timestamp);
- 			} else {
- 				if (dev->capture.last_timestamp) {
- 					buf->vb.vb2_buf.timestamp = dev->capture.last_timestamp;
-@@ -388,8 +368,7 @@ static void buffer_cb(struct vchiq_mmal_
- 				}
- 				else {
- 					buf->vb.vb2_buf.timestamp =
--					dev->capture.kernel_start_ts.tv_sec  * 1000000000ULL +
--					dev->capture.kernel_start_ts.tv_usec * 1000ULL;
-+					dev->capture.kernel_start_timestamp;
- 					v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
- 					 "Buffer time set as start timestamp - %lld",
- 					 buf->vb.vb2_buf.timestamp);
-@@ -574,7 +553,7 @@ static int start_streaming(struct vb2_qu
- 
- 	dev->capture.last_timestamp = 0;
- 
--	v4l2_get_timestamp(&dev->capture.kernel_start_ts);
-+	dev->capture.kernel_start_timestamp = ktime_get_ns();
- 
- 	/* enable the camera port */
- 	dev->capture.port->cb_ctx = dev;
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-@@ -92,7 +92,7 @@ struct bm2835_mmal_dev {
- 		/* VC start timestamp for streaming */
- 		s64         vc_start_timestamp;
- 		/* Kernel start timestamp for streaming */
--		struct timeval kernel_start_ts;
-+		u64         kernel_start_timestamp;
- 		/* Timestamp of last frame */
- 		u64 		last_timestamp;
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0201-drm-panel-rpi-touchscreen-propagate-errors-in-rpi_to.patch b/target/linux/brcm2708/patches-4.14/950-0201-drm-panel-rpi-touchscreen-propagate-errors-in-rpi_to.patch
deleted file mode 100644
index 923cdf243..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0201-drm-panel-rpi-touchscreen-propagate-errors-in-rpi_to.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 5659b5b9d46a236f53217e6686209863960442e3 Mon Sep 17 00:00:00 2001
-From: Dan Carpenter <dan.carpenter@oracle.com>
-Date: Fri, 20 Oct 2017 03:28:45 +0300
-Subject: [PATCH 201/454] drm/panel: rpi-touchscreen: propagate errors in
- rpi_touchscreen_i2c_read()
-
-There is one caller which checks whether rpi_touchscreen_i2c_read()
-returns negative error codes.  Currently it can't because negative
-error codes are truncated to u8, but that's easy to fix if we change the
-type to int.
-
-Fixes: 2f733d6194bd ("drm/panel: Add support for the Raspberry Pi 7" Touchscreen.")
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20171020002845.kar2wg7gqxg7tzqi@mwanda
-Reviewed-by: Eric Anholt <eric@anholt.net>
-(cherry picked from commit 85b4587f8e94143bafb8b6a4003a5187b9a8753d)
----
- drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
-+++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
-@@ -243,7 +243,7 @@ static struct rpi_touchscreen *panel_to_
- 	return container_of(panel, struct rpi_touchscreen, base);
- }
- 
--static u8 rpi_touchscreen_i2c_read(struct rpi_touchscreen *ts, u8 reg)
-+static int rpi_touchscreen_i2c_read(struct rpi_touchscreen *ts, u8 reg)
- {
- 	return i2c_smbus_read_byte_data(ts->bridge_i2c, reg);
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0202-drm-vc4-Fix-crash-if-we-have-to-unbind-HDMI.patch b/target/linux/brcm2708/patches-4.14/950-0202-drm-vc4-Fix-crash-if-we-have-to-unbind-HDMI.patch
deleted file mode 100644
index fa4f93216..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0202-drm-vc4-Fix-crash-if-we-have-to-unbind-HDMI.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 1254dfa5b20336d10e9cf917cdf94c63b4cc44e1 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Mon, 13 Nov 2017 14:23:48 -0800
-Subject: [PATCH 202/454] drm/vc4: Fix crash if we have to unbind HDMI.
-
-We need the card to unregister before the codec that the card
-references.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_hdmi.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_hdmi.c
-+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
-@@ -1130,7 +1130,7 @@ static int vc4_hdmi_audio_init(struct vc
- 	 * snd_soc_card_get_drvdata() if needed.
- 	 */
- 	snd_soc_card_set_drvdata(card, hdmi);
--	ret = devm_snd_soc_register_card(dev, card);
-+	ret = snd_soc_register_card(card);
- 	if (ret) {
- 		dev_err(dev, "Could not register sound card: %d\n", ret);
- 		goto unregister_codec;
-@@ -1147,13 +1147,16 @@ unregister_codec:
- static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi)
- {
- 	struct device *dev = &hdmi->pdev->dev;
-+	struct snd_soc_card *card = &hdmi->audio.card;
- 
- 	/*
- 	 * If drvdata is not set this means the audio card was not
- 	 * registered, just skip codec unregistration in this case.
- 	 */
--	if (dev_get_drvdata(dev))
-+	if (dev_get_drvdata(dev)) {
-+		snd_soc_unregister_card(card);
- 		snd_soc_unregister_codec(dev);
-+	}
- }
- 
- #ifdef CONFIG_DRM_VC4_HDMI_CEC
diff --git a/target/linux/brcm2708/patches-4.14/950-0203-drm-vc4-Skip-ULPS-latching-when-we-re-in-that-ULPS-s.patch b/target/linux/brcm2708/patches-4.14/950-0203-drm-vc4-Skip-ULPS-latching-when-we-re-in-that-ULPS-s.patch
deleted file mode 100644
index b01062c1b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0203-drm-vc4-Skip-ULPS-latching-when-we-re-in-that-ULPS-s.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From c86b5da9e8c4ca0fedd6cdbfc70cdc5f61b5d711 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Tue, 31 Oct 2017 11:33:10 -0700
-Subject: [PATCH 203/454] drm/vc4: Skip ULPS latching when we're in that ULPS
- state already.
-
-It seems that trying to go from unlatched to unlatched will time out
-waiting for STOP, and we can just skip that.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- drivers/gpu/drm/vc4/vc4_dsi.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_dsi.c
-+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
-@@ -753,6 +753,11 @@ static void vc4_dsi_ulps(struct vc4_dsi
- 			 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
- 			 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
- 	int ret;
-+	bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
-+				       DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
-+
-+	if (ulps == ulps_currently_enabled)
-+		return;
- 
- 	DSI_PORT_WRITE(STAT, stat_ulps);
- 	DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
diff --git a/target/linux/brcm2708/patches-4.14/950-0204-drm-vc4-Move-the-DSI-clock-divider-workaround-closer.patch b/target/linux/brcm2708/patches-4.14/950-0204-drm-vc4-Move-the-DSI-clock-divider-workaround-closer.patch
deleted file mode 100644
index dd0eba5ee..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0204-drm-vc4-Move-the-DSI-clock-divider-workaround-closer.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From ae5d39403c61f4ed691a0a8d94673210475242be Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Tue, 15 Aug 2017 16:47:18 -0700
-Subject: [PATCH 204/454] drm/vc4: Move the DSI clock divider workaround closer
- to the clock call.
-
-We want the adjusted_mode->clock to be the actual clock we're
-expecting to program, so that consumers see the right values for clock
-and vrefresh.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/20170815234722.20700-1-eric@anholt.net
-Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-(cherry picked from commit d409eeafa9ba1c0f2eb75a2619fc787808a545e4)
----
- drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_dsi.c
-+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
-@@ -864,11 +864,7 @@ static bool vc4_dsi_encoder_mode_fixup(s
- 	pll_clock = parent_rate / divider;
- 	pixel_clock_hz = pll_clock / dsi->divider;
- 
--	/* Round up the clk_set_rate() request slightly, since
--	 * PLLD_DSI1 is an integer divider and its rate selection will
--	 * never round up.
--	 */
--	adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
-+	adjusted_mode->clock = pixel_clock_hz / 1000;
- 
- 	/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
- 	adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
-@@ -906,7 +902,11 @@ static void vc4_dsi_encoder_enable(struc
- 		vc4_dsi_dump_regs(dsi);
- 	}
- 
--	phy_clock = pixel_clock_hz * dsi->divider;
-+	/* Round up the clk_set_rate() request slightly, since
-+	 * PLLD_DSI1 is an integer divider and its rate selection will
-+	 * never round up.
-+	 */
-+	phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
- 	ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
- 	if (ret) {
- 		dev_err(&dsi->pdev->dev,
diff --git a/target/linux/brcm2708/patches-4.14/950-0205-dwc_otg-Fix-a-regression-when-dequeueing-isochronous.patch b/target/linux/brcm2708/patches-4.14/950-0205-dwc_otg-Fix-a-regression-when-dequeueing-isochronous.patch
deleted file mode 100644
index 32b5418f2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0205-dwc_otg-Fix-a-regression-when-dequeueing-isochronous.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From e071e9b36cb053f06a10986d987bfeb0e362657c Mon Sep 17 00:00:00 2001
-From: P33M <p33m@github.com>
-Date: Tue, 13 Feb 2018 15:41:35 +0000
-Subject: [PATCH 205/454] dwc_otg: Fix a regression when dequeueing isochronous
- transfers
-
-In 282bed95 (dwc_otg: make nak_holdoff work as intended with empty queues)
-the dequeue mechanism was changed to leave FIQ-enabled transfers to run
-to completion - to avoid leaving hub TT buffers with stale packets lying
-around.
-
-This broke FIQ-accelerated isochronous transfers, as this then meant that
-dozens of transfers were performed after the dequeue function returned.
-
-Restore the state machine fence for isochronous transfers.
----
- drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 16 +++++++++++++++-
- 1 file changed, 15 insertions(+), 1 deletion(-)
-
---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
-@@ -189,13 +189,21 @@ static void kill_urbs_in_qh_list(dwc_otg
- 
- 		}
- 		if(qh->channel) {
-+			int n = qh->channel->hc_num;
- 			/* Using hcchar.chen == 1 is not a reliable test.
- 			 * It is possible that the channel has already halted
- 			 * but not yet been through the IRQ handler.
- 			 */
- 			if (fiq_fsm_enable && (hcd->fiq_state->channel[qh->channel->hc_num].fsm != FIQ_PASSTHROUGH)) {
-+				local_fiq_disable();
-+				fiq_fsm_spin_lock(&hcd->fiq_state->lock);
- 				qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
- 				qh->channel->halt_pending = 1;
-+				if (hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_TURBO ||
-+					hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_SLEEPING)
-+					hcd->fiq_state->channel[n].fsm = FIQ_HS_ISOC_ABORTED;
-+				fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+				local_fiq_enable();
- 			} else {
- 				dwc_otg_hc_halt(hcd->core_if, qh->channel,
- 						DWC_OTG_HC_XFER_URB_DEQUEUE);
-@@ -596,9 +604,15 @@ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_
- 			/* In FIQ FSM mode, we need to shut down carefully.
- 			 * The FIQ may attempt to restart a disabled channel */
- 			if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {
-+				local_fiq_disable();
-+				fiq_fsm_spin_lock(&hcd->fiq_state->lock);
- 				qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
- 				qh->channel->halt_pending = 1;
--				//hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED;
-+				if (hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_TURBO ||
-+					hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_SLEEPING)
-+					hcd->fiq_state->channel[n].fsm = FIQ_HS_ISOC_ABORTED;
-+				fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
-+				local_fiq_enable();
- 			} else {
- 				dwc_otg_hc_halt(hcd->core_if, qh->channel,
- 						DWC_OTG_HC_XFER_URB_DEQUEUE);
diff --git a/target/linux/brcm2708/patches-4.14/950-0206-overlays-Allow-multiple-instances-of-gpio-ir-tx.patch b/target/linux/brcm2708/patches-4.14/950-0206-overlays-Allow-multiple-instances-of-gpio-ir-tx.patch
deleted file mode 100644
index a9e58c53f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0206-overlays-Allow-multiple-instances-of-gpio-ir-tx.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 00267dfa96c9ac658c0bf7be980f2b72ba774921 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 15 Feb 2018 09:36:52 +0000
-Subject: [PATCH 206/454] overlays: Allow multiple instances of gpio-ir[-tx]
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/gpio-ir-overlay.dts    | 10 ++++++----
- arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts | 10 ++++++----
- 2 files changed, 12 insertions(+), 8 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts
-@@ -8,7 +8,7 @@
-         fragment@0 {
-                 target-path = "/";
-                 __overlay__ {
--                        gpio_ir: ir-receiver {
-+                        gpio_ir: ir-receiver@12 {
-                                 compatible = "gpio-ir-receiver";
- 
-                                 // pin number, high or low
-@@ -25,7 +25,7 @@
-         fragment@1 {
-                 target = <&gpio>;
-                 __overlay__ {
--                        gpio_ir_pins: gpio_ir_pins {
-+                        gpio_ir_pins: gpio_ir_pins@12 {
-                                 brcm,pins = <18>;                       // pin 18
-                                 brcm,function = <0>;                    // in
-                                 brcm,pull = <1>;                        // down
-@@ -35,8 +35,10 @@
- 
-         __overrides__ {
-                 // parameters
--                gpio_pin =      <&gpio_ir>,"gpios:4",
--                                        <&gpio_ir_pins>,"brcm,pins:0";  // pin number
-+                gpio_pin =      <&gpio_ir>,"gpios:4",           // pin number
-+                                <&gpio_ir>,"reg:0",
-+                                <&gpio_ir_pins>,"brcm,pins:0",
-+                                <&gpio_ir_pins>,"reg:0";
-                 gpio_pull = <&gpio_ir_pins>,"brcm,pull:0";              // pull-up/down state
- 
-                 rc-map-name = <&gpio_ir>,"linux,rc-map-name";           // default rc map
---- a/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts
-@@ -7,7 +7,7 @@
- 	fragment@0 {
- 		target = <&gpio>;
- 		__overlay__ {
--			gpio_ir_tx_pins: gpio_ir_tx_pins {
-+			gpio_ir_tx_pins: gpio_ir_tx_pins@12 {
- 				brcm,pins = <18>;
- 				brcm,function = <1>;	// out
- 			};
-@@ -17,7 +17,7 @@
- 	fragment@1 {
- 		target-path = "/";
- 		__overlay__ {
--			gpio_ir_tx: gpio-ir-transmitter {
-+			gpio_ir_tx: gpio-ir-transmitter@12 {
- 				compatible = "gpio-ir-tx";
- 				pinctrl-names = "default";
- 				pinctrl-0 = <&gpio_ir_tx_pins>;
-@@ -27,8 +27,10 @@
- 	};
- 
- 	__overrides__ {
--		gpio_pin = <&gpio_ir_tx>, "gpios:4",
--			   <&gpio_ir_tx_pins>, "brcm,pins:0";	// pin number
-+		gpio_pin = <&gpio_ir_tx>, "gpios:4",           	// pin number
-+			   <&gpio_ir_tx>, "reg:0",
-+			   <&gpio_ir_tx_pins>, "brcm,pins:0",
-+			   <&gpio_ir_tx_pins>, "reg:0";
- 		invert = <&gpio_ir_tx>, "gpios:8";		// 1 = active low
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0207-dwc_otg-add-smp_mb-to-prevent-driver-state-corruptio.patch b/target/linux/brcm2708/patches-4.14/950-0207-dwc_otg-add-smp_mb-to-prevent-driver-state-corruptio.patch
deleted file mode 100644
index 7e49003c2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0207-dwc_otg-add-smp_mb-to-prevent-driver-state-corruptio.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From efdde709efccc4f95c7641eea8960dbc31fc58b5 Mon Sep 17 00:00:00 2001
-From: P33M <p33m@github.com>
-Date: Thu, 15 Feb 2018 11:22:44 +0000
-Subject: [PATCH 207/454] dwc_otg: add smp_mb() to prevent driver state
- corruption on boot
-
-Occasional crashes have been seen where the FIQ code dereferences
-invalid/random pointers immediately after being set up, leading to
-panic on boot.
-
-The crash occurs as the FIQ code races against hcd_init_fiq() and
-the hcd_init_fiq() code races against the outstanding memory stores
-from dwc_otg_hcd_init(). Use explicit barriers after touching
-driver state.
----
- drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
-@@ -519,6 +519,11 @@ static void hcd_init_fiq(void *cookie)
- 		DWC_ERROR("Can't get FIQ irq");
- 		return;
- 	}
-+	/*
-+	 * We could take an interrupt immediately after enabling the FIQ.
-+	 * Ensure coherency of hcd->fiq_state.
-+	 */
-+	smp_mb();
- 	enable_fiq(irq);
- 	local_fiq_enable();
- #endif
-@@ -598,7 +603,11 @@ int hcd_init(dwc_bus_dev_t *_dev)
- 
- 	if (fiq_enable) {
- 		if (num_online_cpus() > 1) {
--			/* bcm2709: can run the FIQ on a separate core to IRQs */
-+			/*
-+			 * bcm2709: can run the FIQ on a separate core to IRQs.
-+			 * Ensure driver state is visible to other cores before setting up the FIQ.
-+			 */
-+			smp_mb();
- 			smp_call_function_single(1, hcd_init_fiq, otg_dev, 1);
- 		} else {
- 			smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
diff --git a/target/linux/brcm2708/patches-4.14/950-0208-overlay-Add-missing-pinctrl-reference-to-gpio-ir.patch b/target/linux/brcm2708/patches-4.14/950-0208-overlay-Add-missing-pinctrl-reference-to-gpio-ir.patch
deleted file mode 100644
index 7c1cf015a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0208-overlay-Add-missing-pinctrl-reference-to-gpio-ir.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 6ba6a07ab6d7162652246f895c672ed488877eb1 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 15 Feb 2018 16:03:04 +0000
-Subject: [PATCH 208/454] overlay: Add missing pinctrl reference to gpio-ir
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/gpio-ir-overlay.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts
-@@ -10,6 +10,8 @@
-                 __overlay__ {
-                         gpio_ir: ir-receiver@12 {
-                                 compatible = "gpio-ir-receiver";
-+                                pinctrl-names = "default";
-+                                pinctrl-0 = <&gpio_ir_pins>;
- 
-                                 // pin number, high or low
-                                 gpios = <&gpio 18 1>;
diff --git a/target/linux/brcm2708/patches-4.14/950-0209-ASoC-pcm512x-revert-downstream-changes.patch b/target/linux/brcm2708/patches-4.14/950-0209-ASoC-pcm512x-revert-downstream-changes.patch
deleted file mode 100644
index def4981de..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0209-ASoC-pcm512x-revert-downstream-changes.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From ddb523d853a0d64275424f935d8bb6da4af3b4dc Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:41 +0100
-Subject: [PATCH 209/454] ASoC: pcm512x: revert downstream changes
-
-This partially reverts commit 185ea05465aac8bf02a0d2b2f4289d42c72870b7
-which was added by https://github.com/raspberrypi/linux/pull/1152
-
-The downstream pcm512x changes caused a regression, it broke normal
-use of the 24bit format with the codec, eg when using simple-audio-card.
-
-The actual bug with 24bit playback is the incorrect usage
-of physical_width in various drivers in the downstream tree
-which causes 24bit data to be transmitted with 32 clock
-cycles. So it's not the pcm512x that needs fixing, it's the
-soundcard drivers.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/codecs/pcm512x.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/sound/soc/codecs/pcm512x.c
-+++ b/sound/soc/codecs/pcm512x.c
-@@ -851,8 +851,7 @@ static int pcm512x_set_dividers(struct s
- 	int fssp;
- 	int gpio;
- 
--	lrclk_div = snd_pcm_format_physical_width(params_format(params))
--		* params_channels(params);
-+	lrclk_div = snd_soc_params_to_frame_size(params);
- 	if (lrclk_div == 0) {
- 		dev_err(dev, "No LRCLK?\n");
- 		return -EINVAL;
diff --git a/target/linux/brcm2708/patches-4.14/950-0210-ASoC-allo-boss-dac-fix-S24_LE-format.patch b/target/linux/brcm2708/patches-4.14/950-0210-ASoC-allo-boss-dac-fix-S24_LE-format.patch
deleted file mode 100644
index aa5a1b788..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0210-ASoC-allo-boss-dac-fix-S24_LE-format.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From ae1a548ef0cb1a25242201bca5fefa5090728ea8 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:42 +0100
-Subject: [PATCH 210/454] ASoC: allo-boss-dac: fix S24_LE format
-
-Remove set_bclk_ratio call so 24-bit data is transmitted in
-24 bclk cycles.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/allo-boss-dac.c | 20 ++------------------
- 1 file changed, 2 insertions(+), 18 deletions(-)
-
---- a/sound/soc/bcm/allo-boss-dac.c
-+++ b/sound/soc/bcm/allo-boss-dac.c
-@@ -222,14 +222,6 @@ static int snd_allo_boss_update_rate_den
- 	return 0;
- }
- 
--static int snd_allo_boss_set_bclk_ratio_pro(
--	struct snd_soc_dai *cpu_dai, struct snd_pcm_hw_params *params)
--{
--	int bratio = snd_pcm_format_physical_width(params_format(params))
--		* params_channels(params);
--	return snd_soc_dai_set_bclk_ratio(cpu_dai, bratio);
--}
--
- static void snd_allo_boss_gpio_mute(struct snd_soc_card *card)
- {
- 	if (mute_gpio)
-@@ -281,9 +273,6 @@ static int snd_allo_boss_hw_params(
- {
- 	int ret = 0;
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
--	unsigned int sample_bits =
--		snd_pcm_format_physical_width(params_format(params));
- 
- 	if (snd_soc_allo_boss_master) {
- 		struct snd_soc_codec *codec = rtd->codec;
-@@ -291,13 +280,8 @@ static int snd_allo_boss_hw_params(
- 		snd_allo_boss_set_sclk(codec,
- 			params_rate(params));
- 
--		ret = snd_allo_boss_set_bclk_ratio_pro(cpu_dai,
--			params);
--		if (!ret)
--			ret = snd_allo_boss_update_rate_den(
--				substream, params);
--	} else {
--		ret = snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
-+		ret = snd_allo_boss_update_rate_den(
-+			substream, params);
- 	}
- 	return ret;
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0211-ASoC-allo-piano-dac-plus-fix-S24_LE-format.patch b/target/linux/brcm2708/patches-4.14/950-0211-ASoC-allo-piano-dac-plus-fix-S24_LE-format.patch
deleted file mode 100644
index 374cf0005..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0211-ASoC-allo-piano-dac-plus-fix-S24_LE-format.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 43c0810969b4aee4e7a836212bc2eb8987f31d8a Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:42 +0100
-Subject: [PATCH 211/454] ASoC: allo-piano-dac-plus: fix S24_LE format
-
-Remove set_bclk_ratio call so 24-bit data is transmitted in
-24 bclk cycles.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/allo-piano-dac-plus.c | 5 -----
- 1 file changed, 5 deletions(-)
-
---- a/sound/soc/bcm/allo-piano-dac-plus.c
-+++ b/sound/soc/bcm/allo-piano-dac-plus.c
-@@ -795,9 +795,6 @@ static int snd_allo_piano_dac_hw_params(
- 		struct snd_pcm_hw_params *params)
- {
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
--	unsigned int sample_bits =
--		snd_pcm_format_physical_width(params_format(params));
- 	unsigned int rate = params_rate(params);
- 	struct snd_soc_card *card = rtd->card;
- 	struct glb_pool *glb_ptr = card->drvdata;
-@@ -839,8 +836,6 @@ static int snd_allo_piano_dac_hw_params(
- 	if (ret < 0)
- 		return ret;
- 
--	ret = snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
--
- 	return ret;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0212-ASoC-allo-piano-dac-fix-S24_LE-format.patch b/target/linux/brcm2708/patches-4.14/950-0212-ASoC-allo-piano-dac-fix-S24_LE-format.patch
deleted file mode 100644
index 9220af56f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0212-ASoC-allo-piano-dac-fix-S24_LE-format.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From e2036314d5a510acfd84b2f9f22a6b39e324769e Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:42 +0100
-Subject: [PATCH 212/454] ASoC: allo-piano-dac: fix S24_LE format
-
-Remove set_bclk_ratio call so 24-bit data is transmitted in
-24 bclk cycles.
-
-Also remove hw_params and ops as they are no longer needed.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/allo-piano-dac.c | 18 ------------------
- 1 file changed, 18 deletions(-)
-
---- a/sound/soc/bcm/allo-piano-dac.c
-+++ b/sound/soc/bcm/allo-piano-dac.c
-@@ -42,23 +42,6 @@ static int snd_allo_piano_dac_init(struc
- 	return 0;
- }
- 
--static int snd_allo_piano_dac_hw_params(
--	struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
--{
--	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
--
--	unsigned int sample_bits =
--		snd_pcm_format_physical_width(params_format(params));
--
--	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
--}
--
--/* machine stream operations */
--static struct snd_soc_ops snd_allo_piano_dac_ops = {
--	.hw_params = snd_allo_piano_dac_hw_params,
--};
--
- static struct snd_soc_dai_link snd_allo_piano_dac_dai[] = {
- {
- 	.name		= "Piano DAC",
-@@ -70,7 +53,6 @@ static struct snd_soc_dai_link snd_allo_
- 	.dai_fmt	= SND_SOC_DAIFMT_I2S |
- 			  SND_SOC_DAIFMT_NB_NF |
- 			  SND_SOC_DAIFMT_CBS_CFS,
--	.ops		= &snd_allo_piano_dac_ops,
- 	.init		= snd_allo_piano_dac_init,
- },
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0213-ASoC-dionaudio_loco-v2-fix-S24_LE-format.patch b/target/linux/brcm2708/patches-4.14/950-0213-ASoC-dionaudio_loco-v2-fix-S24_LE-format.patch
deleted file mode 100644
index 3d9fb8acd..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0213-ASoC-dionaudio_loco-v2-fix-S24_LE-format.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 12e578b16bb6aa097a6d451a371fd6ade3d07b5d Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:42 +0100
-Subject: [PATCH 213/454] ASoC: dionaudio_loco-v2: fix S24_LE format
-
-Remove set_bclk_ratio call so 24-bit data is transmitted in
-24 bclk cycles.
-
-Also remove hw_params and ops as they are no longer needed.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/dionaudio_loco-v2.c | 19 -------------------
- 1 file changed, 19 deletions(-)
-
---- a/sound/soc/bcm/dionaudio_loco-v2.c
-+++ b/sound/soc/bcm/dionaudio_loco-v2.c
-@@ -41,24 +41,6 @@ static int snd_rpi_dionaudio_loco_v2_ini
- 	return 0;
- }
- 
--static int snd_rpi_dionaudio_loco_v2_hw_params(
--	struct snd_pcm_substream *substream,
--	struct snd_pcm_hw_params *params)
--{
--	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
--
--	unsigned int sample_bits =
--		snd_pcm_format_physical_width(params_format(params));
--
--	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
--}
--
--/* machine stream operations */
--static struct snd_soc_ops snd_rpi_dionaudio_loco_v2_ops = {
--	.hw_params = snd_rpi_dionaudio_loco_v2_hw_params,
--};
--
- static struct snd_soc_dai_link snd_rpi_dionaudio_loco_v2_dai[] = {
- {
- 	.name		= "DionAudio LOCO-V2",
-@@ -69,7 +51,6 @@ static struct snd_soc_dai_link snd_rpi_d
- 	.codec_name	= "pcm512x.1-004d",
- 	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
- 			  SND_SOC_DAIFMT_CBS_CFS,
--	.ops		= &snd_rpi_dionaudio_loco_v2_ops,
- 	.init		= snd_rpi_dionaudio_loco_v2_init,
- },};
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0214-ASoC-hifiberry_dacplus-fix-S24_LE-format.patch b/target/linux/brcm2708/patches-4.14/950-0214-ASoC-hifiberry_dacplus-fix-S24_LE-format.patch
deleted file mode 100644
index 520ca3636..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0214-ASoC-hifiberry_dacplus-fix-S24_LE-format.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From d94d483e5f0798294aa1eb738c203acc4a7f415e Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:42 +0100
-Subject: [PATCH 214/454] ASoC: hifiberry_dacplus: fix S24_LE format
-
-Remove set_bclk_ratio call so 24-bit data is transmitted in
-24 bclk cycles.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/hifiberry_dacplus.c | 20 +++-----------------
- 1 file changed, 3 insertions(+), 17 deletions(-)
-
---- a/sound/soc/bcm/hifiberry_dacplus.c
-+++ b/sound/soc/bcm/hifiberry_dacplus.c
-@@ -216,20 +216,11 @@ static int snd_rpi_hifiberry_dacplus_upd
- 	return 0;
- }
- 
--static int snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro(
--	struct snd_soc_dai *cpu_dai, struct snd_pcm_hw_params *params)
--{
--	int bratio = snd_pcm_format_physical_width(params_format(params))
--		* params_channels(params);
--	return snd_soc_dai_set_bclk_ratio(cpu_dai, bratio);
--}
--
- static int snd_rpi_hifiberry_dacplus_hw_params(
- 	struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)
- {
--	int ret;
-+	int ret = 0;
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
- 
- 	if (snd_rpi_hifiberry_is_dacpro) {
- 		struct snd_soc_codec *codec = rtd->codec;
-@@ -237,13 +228,8 @@ static int snd_rpi_hifiberry_dacplus_hw_
- 		snd_rpi_hifiberry_dacplus_set_sclk(codec,
- 			params_rate(params));
- 
--		ret = snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro(cpu_dai,
--			params);
--		if (!ret)
--			ret = snd_rpi_hifiberry_dacplus_update_rate_den(
--				substream, params);
--	} else {
--		ret = snd_soc_dai_set_bclk_ratio(cpu_dai, 64);
-+		ret = snd_rpi_hifiberry_dacplus_update_rate_den(
-+			substream, params);
- 	}
- 	return ret;
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0215-ASoC-iqaudio-dac-fix-S24_LE-format.patch b/target/linux/brcm2708/patches-4.14/950-0215-ASoC-iqaudio-dac-fix-S24_LE-format.patch
deleted file mode 100644
index d569d4f78..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0215-ASoC-iqaudio-dac-fix-S24_LE-format.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 7e9c82c499592f518e45cf9d049529470971dac7 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:42 +0100
-Subject: [PATCH 215/454] ASoC: iqaudio-dac: fix S24_LE format
-
-Remove set_bclk_ratio call so 24-bit data is transmitted in
-24 bclk cycles.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/iqaudio-dac.c | 18 ------------------
- 1 file changed, 18 deletions(-)
-
---- a/sound/soc/bcm/iqaudio-dac.c
-+++ b/sound/soc/bcm/iqaudio-dac.c
-@@ -43,18 +43,6 @@ static int snd_rpi_iqaudio_dac_init(stru
- 	return 0;
- }
- 
--static int snd_rpi_iqaudio_dac_hw_params(struct snd_pcm_substream *substream,
--	struct snd_pcm_hw_params *params)
--{
--	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
--
--	unsigned int sample_bits =
--		snd_pcm_format_physical_width(params_format(params));
--
--	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
--}
--
- static void snd_rpi_iqaudio_gpio_mute(struct snd_soc_card *card)
- {
- 	if (mute_gpio) {
-@@ -109,11 +97,6 @@ static int snd_rpi_iqaudio_set_bias_leve
- 	return 0;
- }
- 
--/* machine stream operations */
--static struct snd_soc_ops snd_rpi_iqaudio_dac_ops = {
--	.hw_params = snd_rpi_iqaudio_dac_hw_params,
--};
--
- static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = {
- {
- 	.cpu_dai_name	= "bcm2708-i2s.0",
-@@ -122,7 +105,6 @@ static struct snd_soc_dai_link snd_rpi_i
- 	.codec_name	= "pcm512x.1-004c",
- 	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
- 				SND_SOC_DAIFMT_CBS_CFS,
--	.ops		= &snd_rpi_iqaudio_dac_ops,
- 	.init		= snd_rpi_iqaudio_dac_init,
- },
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0216-ASoC-justboom-dac-fix-S24_LE-format.patch b/target/linux/brcm2708/patches-4.14/950-0216-ASoC-justboom-dac-fix-S24_LE-format.patch
deleted file mode 100644
index ee188c409..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0216-ASoC-justboom-dac-fix-S24_LE-format.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 27a3d69088ae59f17ec5cb2c8b757b422b1589a9 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:43 +0100
-Subject: [PATCH 216/454] ASoC: justboom-dac: fix S24_LE format
-
-Remove set_bclk_ratio call so 24-bit data is transmitted in
-24 bclk cycles.
-
-Also remove hw_params as it's no longer needed.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/justboom-dac.c | 12 ------------
- 1 file changed, 12 deletions(-)
-
---- a/sound/soc/bcm/justboom-dac.c
-+++ b/sound/soc/bcm/justboom-dac.c
-@@ -49,17 +49,6 @@ static int snd_rpi_justboom_dac_init(str
- 	return 0;
- }
- 
--static int snd_rpi_justboom_dac_hw_params(struct snd_pcm_substream *substream,
--				       struct snd_pcm_hw_params *params)
--{
--	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
--	/*return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);*/
--	unsigned int sample_bits =
--		snd_pcm_format_physical_width(params_format(params));
--	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
--}
--
- static int snd_rpi_justboom_dac_startup(struct snd_pcm_substream *substream) {
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
- 	struct snd_soc_codec *codec = rtd->codec;
-@@ -75,7 +64,6 @@ static void snd_rpi_justboom_dac_shutdow
- 
- /* machine stream operations */
- static struct snd_soc_ops snd_rpi_justboom_dac_ops = {
--	.hw_params = snd_rpi_justboom_dac_hw_params,
- 	.startup = snd_rpi_justboom_dac_startup,
- 	.shutdown = snd_rpi_justboom_dac_shutdown,
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0217-ASoC-raspidac3-fix-S24_LE-format.patch b/target/linux/brcm2708/patches-4.14/950-0217-ASoC-raspidac3-fix-S24_LE-format.patch
deleted file mode 100644
index 4b282c116..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0217-ASoC-raspidac3-fix-S24_LE-format.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 0999f5ef037e213e87af656f23ae305d1885b006 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 20:30:43 +0100
-Subject: [PATCH 217/454] ASoC: raspidac3: fix S24_LE format
-
-Remove set_bclk_ratio call so 24-bit data is transmitted in
-24 bclk cycles.
-
-Also remove hw_params as it's no longer needed.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/raspidac3.c | 14 --------------
- 1 file changed, 14 deletions(-)
-
---- a/sound/soc/bcm/raspidac3.c
-+++ b/sound/soc/bcm/raspidac3.c
-@@ -68,19 +68,6 @@ static int snd_rpi_raspidac3_init(struct
- 	return 0;
- }
- 
--/* set hw parameters */
--static int snd_rpi_raspidac3_hw_params(struct snd_pcm_substream *substream,
--				       struct snd_pcm_hw_params *params)
--{
--	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
--
--	unsigned int sample_bits =
--		snd_pcm_format_physical_width(params_format(params));
--
--	return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
--}
--
- /* startup */
- static int snd_rpi_raspidac3_startup(struct snd_pcm_substream *substream) {
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-@@ -98,7 +85,6 @@ static void snd_rpi_raspidac3_shutdown(s
- 
- /* machine stream operations */
- static struct snd_soc_ops snd_rpi_raspidac3_ops = {
--	.hw_params = snd_rpi_raspidac3_hw_params,
- 	.startup = snd_rpi_raspidac3_startup,
- 	.shutdown = snd_rpi_raspidac3_shutdown,
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0218-Generic-Rotary-Encoder-overlay-for-multiple-instance.patch b/target/linux/brcm2708/patches-4.14/950-0218-Generic-Rotary-Encoder-overlay-for-multiple-instance.patch
deleted file mode 100644
index b85d54503..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0218-Generic-Rotary-Encoder-overlay-for-multiple-instance.patch
+++ /dev/null
@@ -1,100 +0,0 @@
-From d61d506099a7e3dc2823927c89ac56478ef9f3a5 Mon Sep 17 00:00:00 2001
-From: Ismael Asensio <isma.af@gmail.com>
-Date: Sun, 18 Feb 2018 18:53:58 +0100
-Subject: [PATCH 218/454] Generic Rotary Encoder overlay for multiple instances
- (#2388)
-
-Modify the rotary-encoder overlay to support multiple instances.
----
- arch/arm/boot/dts/overlays/README             |  4 +-
- .../dts/overlays/rotary-encoder-overlay.dts   | 54 +++++++++++--------
- 2 files changed, 33 insertions(+), 25 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1345,9 +1345,9 @@ Params: <None>
- Name:   rotary-encoder
- Info:   Overlay for GPIO connected rotary encoder.
- Load:   dtoverlay=rotary-encoder,<param>=<val>
--Params: rotary0_pin_a           GPIO connected to rotary encoder channel A
-+Params: pin_a                   GPIO connected to rotary encoder channel A
-                                 (default 4).
--        rotary0_pin_b           GPIO connected to rotary encoder channel B
-+        pin_b                   GPIO connected to rotary encoder channel B
-                                 (default 17).
-         relative_axis           register a relative axis rather than an
-                                 absolute one. Relative axis will only
---- a/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts
-@@ -8,7 +8,7 @@
- 	fragment@0 {
- 		target = <&gpio>;
- 		__overlay__ {
--			rotary0_pins: rotary0_pins {
-+			rotary_pins: rotary_pins@4 {
- 				brcm,pins = <4 17>; /* gpio 4 17 */
- 				brcm,function = <0 0>; /* input */
- 				brcm,pull = <2 2>; /* pull-up */
-@@ -20,32 +20,40 @@
- 	fragment@1 {
- 		target-path = "/";
- 		__overlay__ {
--			rotary0: rotary@0 {
--					compatible = "rotary-encoder";
--					status = "okay";
--					pinctrl-names = "default";
--					pinctrl-0 = <&rotary0_pins>;
--					gpios = <&gpio 4 0>, <&gpio 17 0>;
--					linux,axis = <0>; /* REL_X */
--					rotary-encoder,encoding = "gray";
--					rotary-encoder,steps = <24>; /* 24 default */
--					rotary-encoder,steps-per-period = <1>; /* corresponds to full period mode. See README */
-+			rotary: rotary@4 {
-+				compatible = "rotary-encoder";
-+				status = "okay";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&rotary_pins>;
-+				gpios = <&gpio 4 0>, <&gpio 17 0>;
-+				linux,axis = <0>; /* REL_X */
-+				rotary-encoder,encoding = "gray";
-+				rotary-encoder,steps = <24>; /* 24 default */
-+				rotary-encoder,steps-per-period = <1>; /* corresponds to full period mode. See README */
- 			};
- 		};
- 
- 	};  
- 
- 	__overrides__ {
--		rotary0_pin_a =     <&rotary0>,"gpios:4",
--		                    <&rotary0_pins>,"brcm,pins:0";
--		rotary0_pin_b =     <&rotary0>,"gpios:16",
--		                    <&rotary0_pins>,"brcm,pins:4";
--		relative_axis =     <&rotary0>,"rotary-encoder,relative-axis?";
--		linux_axis =        <&rotary0>,"linux,axis:0";
--		rollover =          <&rotary0>,"rotary-encoder,rollover?";
--		steps-per-period =  <&rotary0>,"rotary-encoder,steps-per-period:0";
--		steps =             <&rotary0>,"rotary-encoder,steps:0";
--		wakeup =            <&rotary0>,"wakeup-source?";
--		encoding =          <&rotary0>,"rotary-encoder,encoding";
--	};  
-+		pin_a =		    <&rotary>,"gpios:4",
-+				    <&rotary_pins>,"brcm,pins:0",
-+				    /* modify reg values to allow multiple instantiation */
-+				    <&rotary>,"reg:0",
-+				    <&rotary_pins>,"reg:0";
-+		pin_b =		    <&rotary>,"gpios:16",
-+				    <&rotary_pins>,"brcm,pins:4";
-+		relative_axis =     <&rotary>,"rotary-encoder,relative-axis?";
-+		linux_axis =        <&rotary>,"linux,axis:0";
-+		rollover =          <&rotary>,"rotary-encoder,rollover?";
-+		steps-per-period =  <&rotary>,"rotary-encoder,steps-per-period:0";
-+		steps =             <&rotary>,"rotary-encoder,steps:0";
-+		wakeup =            <&rotary>,"wakeup-source?";
-+		encoding =          <&rotary>,"rotary-encoder,encoding";
-+                /* legacy parameters*/
-+		rotary0_pin_a =     <&rotary>,"gpios:4",
-+		                    <&rotary_pins>,"brcm,pins:0";
-+		rotary0_pin_b =     <&rotary>,"gpios:16",
-+		                    <&rotary_pins>,"brcm,pins:4";
-+	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0219-Add-support-for-SuperAudioBoard-sound-card-2386.patch b/target/linux/brcm2708/patches-4.14/950-0219-Add-support-for-SuperAudioBoard-sound-card-2386.patch
deleted file mode 100644
index a348d2d6e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0219-Add-support-for-SuperAudioBoard-sound-card-2386.patch
+++ /dev/null
@@ -1,147 +0,0 @@
-From 98f993e9d2b66f3219ac9841ad836ef79a341908 Mon Sep 17 00:00:00 2001
-From: RF William Hollender <whollender@gmail.com>
-Date: Sun, 18 Feb 2018 14:41:43 -0600
-Subject: [PATCH 219/454] Add support for SuperAudioBoard sound card (#2386)
-
-SuperAudioBoard support using simple-audio-card driver.
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  6 ++
- .../dts/overlays/superaudioboard-overlay.dts  | 73 +++++++++++++++++++
- arch/arm/configs/bcm2709_defconfig            |  1 +
- arch/arm/configs/bcmrpi_defconfig             |  1 +
- arch/arm64/configs/bcmrpi3_defconfig          |  1 +
- 6 files changed, 83 insertions(+)
- create mode 100755 arch/arm/boot/dts/overlays/superaudioboard-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -118,6 +118,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	spi2-1cs.dtbo \
- 	spi2-2cs.dtbo \
- 	spi2-3cs.dtbo \
-+	superaudioboard.dtbo \
- 	tinylcd35.dtbo \
- 	uart0.dtbo \
- 	uart1.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1658,6 +1658,12 @@ Params: cs0_pin                 GPIO pin
-                                 is 'okay' or enabled).
- 
- 
-+Name:   superaudioboard
-+Info:   Configures the SuperAudioBoard sound card
-+Load:   dtoverlay=superaudioboard,<param>=<val>
-+Params: gpiopin                 GPIO pin for codec reset
-+
-+
- Name:   tinylcd35
- Info:   3.5" Color TFT Display by www.tinylcd.com
-         Options: Touch, RTC, keypad
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts
-@@ -0,0 +1,73 @@
-+// Definitions for SuperAudioBoard
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "simple-audio-card";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+
-+			simple-audio-card,name = "SuperAudioBoard";
-+
-+			simple-audio-card,widgets =
-+				"Line", "Line In",
-+				"Line", "Line Out";
-+
-+			simple-audio-card,routing =
-+				"Line Out","AOUTA+",
-+				"Line Out","AOUTA-",
-+				"Line Out","AOUTB+",
-+				"Line Out","AOUTB-",
-+				"AINA","Line In",
-+				"AINB","Line In";
-+
-+			simple-audio-card,format = "i2s";
-+
-+			simple-audio-card,bitclock-master = <&sound_master>;
-+			simple-audio-card,frame-master = <&sound_master>;
-+
-+			simple-audio-card,cpu {
-+				sound-dai = <&i2s>;
-+				dai-tdm-slot-num = <2>;
-+				dai-tdm-slot-width = <32>;
-+			};
-+
-+			sound_master: simple-audio-card,codec {
-+				sound-dai = <&cs4271>;
-+				system-clock-frequency = <24576000>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+    
-+	fragment@2 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			cs4271: cs4271@10 {
-+				#sound-dai-cells = <0>;
-+				compatible = "cirrus,cs4271";
-+				reg = <0x10>;
-+				status = "okay";
-+				reset-gpio = <&gpio 26 0>; /* Pin 26, active high */
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		gpiopin = <&cs4271>,"reset-gpio:4";
-+	};
-+};
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -895,6 +895,7 @@ CONFIG_SND_PISOUND=m
- CONFIG_SND_SOC_ADAU1701=m
- CONFIG_SND_SOC_ADAU7002=m
- CONFIG_SND_SOC_AK4554=m
-+CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -888,6 +888,7 @@ CONFIG_SND_PISOUND=m
- CONFIG_SND_SOC_ADAU1701=m
- CONFIG_SND_SOC_ADAU7002=m
- CONFIG_SND_SOC_AK4554=m
-+CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -870,6 +870,7 @@ CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m
- CONFIG_SND_PISOUND=m
- CONFIG_SND_SOC_ADAU1701=m
- CONFIG_SND_SOC_AK4554=m
-+CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
- CONFIG_SOUND_PRIME=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0220-Revert-downstream-wm8804-changes.patch b/target/linux/brcm2708/patches-4.14/950-0220-Revert-downstream-wm8804-changes.patch
deleted file mode 100644
index bbc2ec0ff..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0220-Revert-downstream-wm8804-changes.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 91fb8d2d0718c2de44623a300273f5144e1ebcab Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Fri, 2 Feb 2018 12:00:00 +0100
-Subject: [PATCH 220/454] Revert downstream wm8804 changes
-
-The format change from S24_LE to S24_3LE effectively disables 24-bit
-mode as S24_3LE isn't supported by bcm2835-i2s. This causes issues
-with drivers that want to use wm8804 in 24-bit mode.
-
-Adding the S32_LE format is also incorrect, according to the datasheet
-only 16-24 bit formats are supported.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/codecs/wm8804.c | 5 ++---
- 1 file changed, 2 insertions(+), 3 deletions(-)
-
---- a/sound/soc/codecs/wm8804.c
-+++ b/sound/soc/codecs/wm8804.c
-@@ -304,7 +304,6 @@ static int wm8804_hw_params(struct snd_p
- 		blen = 0x1;
- 		break;
- 	case 24:
--	case 32:
- 		blen = 0x2;
- 		break;
- 	default:
-@@ -516,7 +515,7 @@ static const struct snd_soc_dai_ops wm88
- };
- 
- #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
--			SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
-+			SNDRV_PCM_FMTBIT_S24_LE)
- 
- #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
- 		      SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
-@@ -544,7 +543,7 @@ static struct snd_soc_dai_driver wm8804_
- };
- 
- static const struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
--	.idle_bias_off = false,
-+	.idle_bias_off = true,
- 
- 	.component_driver = {
- 		.dapm_widgets		= wm8804_dapm_widgets,
diff --git a/target/linux/brcm2708/patches-4.14/950-0221-BCM270X_DT-Add-brcm-bcm2835-sdhci-as-a-fallback.patch b/target/linux/brcm2708/patches-4.14/950-0221-BCM270X_DT-Add-brcm-bcm2835-sdhci-as-a-fallback.patch
deleted file mode 100644
index cfeb37e51..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0221-BCM270X_DT-Add-brcm-bcm2835-sdhci-as-a-fallback.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 60dc1c57f4e5904c7ac96408ac9e836034814a8c Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 19 Feb 2018 17:04:42 +0000
-Subject: [PATCH 221/454] BCM270X_DT: Add brcm,bcm2835-sdhci as a fallback
-
-Although downstream uses a different MMC/SDHCI driver there is
-no reason why can't support the upstream as a fallback.
-
-See: https://github.com/raspberrypi/firmware/issues/943
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm270x.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/bcm270x.dtsi
-+++ b/arch/arm/boot/dts/bcm270x.dtsi
-@@ -61,7 +61,7 @@
- 		/delete-node/ sdhci@7e300000;
- 
- 		mmc: mmc@7e300000 {
--			compatible = "brcm,bcm2835-mmc";
-+			compatible = "brcm,bcm2835-mmc", "brcm,bcm2835-sdhci";
- 			reg = <0x7e300000 0x100>;
- 			interrupts = <2 30>;
- 			clocks = <&clocks BCM2835_CLOCK_EMMC>;
diff --git a/target/linux/brcm2708/patches-4.14/950-0222-overlays-i2c-gpio-Support-for-multiple-instances.patch b/target/linux/brcm2708/patches-4.14/950-0222-overlays-i2c-gpio-Support-for-multiple-instances.patch
deleted file mode 100644
index 6e0ca9139..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0222-overlays-i2c-gpio-Support-for-multiple-instances.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 3826d26d2a41f03c82c45465ff4759891c1688c6 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 19 Feb 2018 17:29:15 +0000
-Subject: [PATCH 222/454] overlays: i2c-gpio: Support for multiple instances
-
-Add a 'bus' parameter that, if set to a unique, non-zero
-value, allows multiple i2c-gpio instances to coexist. The chosen
-value doesn't determine the /dev/i2c-* value, but starting with
-1 or 2 and counting upwards seems sensible. N.B. The bus parameter
-has a default value of zero, so one instance doesn't need to specify
-a value.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README               | 3 +++
- arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 2 +-
- 2 files changed, 4 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -693,6 +693,9 @@ Params: i2c_gpio_sda            GPIO use
-         i2c_gpio_delay_us       Clock delay in microseconds
-                                 (default "2" = ~100kHz)
- 
-+        bus                     Set to a unique, non-zero value if wanting
-+                                multiple i2c-gpio busses (default "0")
-+
- 
- Name:   i2c-mux
- Info:   Adds support for a number of I2C bus multiplexers on i2c_arm
---- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts
-@@ -38,6 +38,6 @@
- 		i2c_gpio_sda = <&i2c_gpio>,"gpios:4";
- 		i2c_gpio_scl = <&i2c_gpio>,"gpios:16";
- 		i2c_gpio_delay_us = <&i2c_gpio>,"i2c-gpio,delay-us:0";
-+		bus = <&i2c_gpio>, "reg:0";
- 	};
- };
--
diff --git a/target/linux/brcm2708/patches-4.14/950-0223-i2c-gpio-Also-set-bus-numbers-from-reg-property.patch b/target/linux/brcm2708/patches-4.14/950-0223-i2c-gpio-Also-set-bus-numbers-from-reg-property.patch
deleted file mode 100644
index 89710a990..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0223-i2c-gpio-Also-set-bus-numbers-from-reg-property.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 41ee5de43fef1fb44219a5bb7099af028d241670 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 20 Feb 2018 10:07:27 +0000
-Subject: [PATCH 223/454] i2c-gpio: Also set bus numbers from reg property
-
-I2C busses can be assigned specific bus numbers using aliases in
-Device Tree - string properties where the name is the alias and the
-value is the path to the node. The current DT parameter mechanism
-does not allow property names to be derived from a parameter value
-in any way, so it isn't possible to generate unique or matching
-aliases for nodes from an overlay that can generate multiple
-instances, e.g. i2c-gpio.
-
-Work around this limitation (at least temporarily) by allowing
-the i2c adapter number to be initialised from the "reg" property
-if present.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/i2c/busses/i2c-gpio.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/i2c/busses/i2c-gpio.c
-+++ b/drivers/i2c/busses/i2c-gpio.c
-@@ -223,7 +223,9 @@ static int i2c_gpio_probe(struct platfor
- 	adap->dev.parent = &pdev->dev;
- 	adap->dev.of_node = pdev->dev.of_node;
- 
--	adap->nr = pdev->id;
-+	if (pdev->id != PLATFORM_DEVID_NONE || !pdev->dev.of_node ||
-+	    of_property_read_u32(pdev->dev.of_node, "reg", &adap->nr))
-+		adap->nr = pdev->id;
- 	ret = i2c_bit_add_numbered_bus(adap);
- 	if (ret)
- 		return ret;
diff --git a/target/linux/brcm2708/patches-4.14/950-0224-overlays-i2c-gpio-Explain-bus-numbers-in-README.patch b/target/linux/brcm2708/patches-4.14/950-0224-overlays-i2c-gpio-Explain-bus-numbers-in-README.patch
deleted file mode 100644
index 21715314f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0224-overlays-i2c-gpio-Explain-bus-numbers-in-README.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 5fa522d6069313f96c93c255a20ca40e2d2a6c57 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 20 Feb 2018 10:47:27 +0000
-Subject: [PATCH 224/454] overlays: i2c-gpio: Explain bus numbers in README
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -694,7 +694,11 @@ Params: i2c_gpio_sda            GPIO use
-                                 (default "2" = ~100kHz)
- 
-         bus                     Set to a unique, non-zero value if wanting
--                                multiple i2c-gpio busses (default "0")
-+                                multiple i2c-gpio busses. If set, will be used
-+                                as the preferred bus number (/dev/i2c-<n>). If
-+                                not set, the default value is 0, but the bus
-+                                number will be dynamically assigned - probably
-+                                3.
- 
- 
- Name:   i2c-mux
diff --git a/target/linux/brcm2708/patches-4.14/950-0225-Update-rpi-ft5406-overlay.dts.patch b/target/linux/brcm2708/patches-4.14/950-0225-Update-rpi-ft5406-overlay.dts.patch
deleted file mode 100644
index a5e2d75f7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0225-Update-rpi-ft5406-overlay.dts.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 988c708cb76076829f067d85e227480d97fc2d25 Mon Sep 17 00:00:00 2001
-From: James Hughes <JamesH65@users.noreply.github.com>
-Date: Tue, 20 Feb 2018 13:05:21 +0000
-Subject: [PATCH 225/454] Update rpi-ft5406-overlay.dts
-
-The Y resolution of the touchscreen was incorrectly set to 600, should be 480.
----
- arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts
-@@ -12,7 +12,7 @@
- 				firmware = <&firmware>;
- 				status = "okay";
- 				touchscreen-size-x = <800>;
--				touchscreen-size-y = <600>;
-+				touchscreen-size-y = <480>;
- 				touchscreen-inverted-x = <0>;
- 				touchscreen-inverted-y = <0>;
- 				touchscreen-swapped-x-y = <0>;
diff --git a/target/linux/brcm2708/patches-4.14/950-0226-overlays-Add-overlay-for-missing-AUX-interrupt-contr.patch b/target/linux/brcm2708/patches-4.14/950-0226-overlays-Add-overlay-for-missing-AUX-interrupt-contr.patch
deleted file mode 100644
index a43e79f71..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0226-overlays-Add-overlay-for-missing-AUX-interrupt-contr.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 8134311059a478a79f7c9c9d08163bafa972fd39 Mon Sep 17 00:00:00 2001
-From: Alexander Graf <agraf@suse.de>
-Date: Tue, 20 Feb 2018 17:36:21 +0100
-Subject: [PATCH 226/454] overlays: Add overlay for missing AUX interrupt
- controller support (#2391)
-
-Upstream Linux today does not support the AUX interrupt controller
-yet. To make sure it can use our device tree, add an overlay that
-reverts it to something upstream understands again.
-
-See: https://github.com/raspberrypi/firmware/issues/943
-
-Signed-off-by: Alexander Graf <agraf@suse.de>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  7 ++++
- .../upstream-aux-interrupt-overlay.dts        | 33 +++++++++++++++++++
- 3 files changed, 41 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/upstream-aux-interrupt-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -122,6 +122,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	tinylcd35.dtbo \
- 	uart0.dtbo \
- 	uart1.dtbo \
-+	upstream-aux-interrupt.dtbo \
- 	vc4-fkms-v3d.dtbo \
- 	vc4-kms-v3d.dtbo \
- 	vga666.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1721,6 +1721,13 @@ Params: txd1_pin                GPIO pin
-         rxd1_pin                GPIO pin for RXD1 (15, 33 or 41 - default 15)
- 
- 
-+Name:   upstream-aux-interrupt
-+Info:   Allow usage of downstream .dtb with upstream kernel by binding AUX
-+        devices directly to the shared AUX interrupt line.
-+Load:   dtoverlay=upstream-aux-interrupt
-+Params: <None>
-+
-+
- Name:   vc4-fkms-v3d
- Info:   Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx
-         display stack.
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/upstream-aux-interrupt-overlay.dts
-@@ -0,0 +1,33 @@
-+// Overlay for missing AUX interrupt controller
-+// Instead we bind all AUX devices to the generic AUX interrupt line
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+    compatible = "brcm,bcm2708";
-+
-+    fragment@0 {
-+        target = <&uart1>;
-+        __overlay__ {
-+            interrupt-parent = <&intc>;
-+            interrupts = <0x1 0x1d>;
-+        };
-+    };
-+
-+    fragment@1 {
-+        target = <&spi1>;
-+        __overlay__ {
-+            interrupt-parent = <&intc>;
-+            interrupts = <0x1 0x1d>;
-+        };
-+    };
-+
-+    fragment@2 {
-+        target = <&spi2>;
-+        __overlay__ {
-+            interrupt-parent = <&intc>;
-+            interrupts = <0x1 0x1d>;
-+        };
-+    };
-+};
-+
diff --git a/target/linux/brcm2708/patches-4.14/950-0227-overlays-Add-sc16is752-i2c-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0227-overlays-Add-sc16is752-i2c-overlay.patch
deleted file mode 100644
index 5b97327ea..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0227-overlays-Add-sc16is752-i2c-overlay.patch
+++ /dev/null
@@ -1,95 +0,0 @@
-From c286380fe677e404af0a1226c6589b3f24fafc6c Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 20 Feb 2018 17:32:02 +0000
-Subject: [PATCH 227/454] overlays: Add sc16is752-i2c overlay
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             | 15 +++++--
- .../dts/overlays/sc16is752-i2c-overlay.dts    | 40 +++++++++++++++++++
- 3 files changed, 53 insertions(+), 3 deletions(-)
- create mode 100644 arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -100,6 +100,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	rpi-tv.dtbo \
- 	rra-digidac1-wm8741-audio.dtbo \
- 	sc16is750-i2c.dtbo \
-+	sc16is752-i2c.dtbo \
- 	sc16is752-spi1.dtbo \
- 	sdhost.dtbo \
- 	sdio.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1447,14 +1447,23 @@ Params: <None>
- 
- Name:   sc16is750-i2c
- Info:   Overlay for the NXP SC16IS750 UART with I2C Interface
--        Enables the chip on I2C1 at 0x48. To select another address,
--        please refer to table 10 in reference manual.
--
-+        Enables the chip on I2C1 at 0x48 (or the "addr" parameter value). To
-+        select another address, please refer to table 10 in reference manual.
- Load:   dtoverlay=sc16is750-i2c,<param>=<val>
- Params: int_pin                 GPIO used for IRQ (default 24)
-         addr                    Address (default 0x48)
- 
- 
-+Name:   sc16is752-i2c
-+Info:   Overlay for the NXP SC16IS752 dual UART with I2C Interface
-+        Enables the chip on I2C1 at 0x48 (or the "addr" parameter value). To
-+        select another address, please refer to table 10 in reference manual.
-+Load:   dtoverlay=sc16is752-i2c,<param>=<val>
-+Params: int_pin                 GPIO used for IRQ (default 24)
-+        addr                    Address (default 0x48)
-+        xtal                    On-board crystal frequency (default 14745600)
-+
-+
- Name:   sc16is752-spi1
- Info:   Overlay for the NXP SC16IS752 Dual UART with SPI Interface
-         Enables the chip on SPI1.
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts
-@@ -0,0 +1,40 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835";
-+
-+	fragment@0 {
-+		target = <&i2c1>;
-+
-+		frag1: __overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			sc16is752: sc16is752@48 {
-+				compatible = "nxp,sc16is752";
-+				reg = <0x48>; // i2c address
-+				clocks = <&sc16is752_clk>;
-+				interrupt-parent = <&gpio>;
-+				interrupts = <24 0x2>; /* IRQ_TYPE_EDGE_FALLING */
-+				gpio-controller;
-+				#gpio-cells = <0>;
-+				i2c-max-frequency = <400000>;
-+				status = "okay";
-+
-+				sc16is752_clk: sc16is752_clk {
-+					compatible = "fixed-clock";
-+					#clock-cells = <0>;
-+					clock-frequency = <14745600>;
-+				};
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		int_pin = <&sc16is752>,"interrupts:0";
-+		addr = <&sc16is752>,"reg:0";
-+		xtal = <&sc16is752>,"clock-frequency:0";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0228-bcm2709-enable-usb-gadget-functions.patch b/target/linux/brcm2708/patches-4.14/950-0228-bcm2709-enable-usb-gadget-functions.patch
deleted file mode 100644
index 228eb117a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0228-bcm2709-enable-usb-gadget-functions.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 0367253c999dbed25e2f1cc18bddd09102ae89c3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= <linux@weissschuh.net>
-Date: Fri, 23 Feb 2018 15:25:19 +0100
-Subject: [PATCH 228/454] bcm2709: enable usb gadget functions
-
-they are already in bcmrpi_defconfig
----
- arch/arm/configs/bcm2709_defconfig | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -1057,6 +1057,19 @@ CONFIG_USB_CXACRU=m
- CONFIG_USB_UEAGLEATM=m
- CONFIG_USB_XUSBATM=m
- CONFIG_USB_GADGET=m
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_AUDIO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_MASS_STORAGE=m
-+CONFIG_USB_G_SERIAL=m
-+CONFIG_USB_MIDI_GADGET=m
-+CONFIG_USB_G_PRINTER=m
-+CONFIG_USB_CDC_COMPOSITE=m
-+CONFIG_USB_G_ACM_MS=m
-+CONFIG_USB_G_MULTI=m
-+CONFIG_USB_G_HID=m
-+CONFIG_USB_G_WEBCAM=m
- CONFIG_MMC=y
- CONFIG_MMC_BLOCK_MINORS=32
- CONFIG_MMC_BCM2835_MMC=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0229-ASoC-pcm512x-implement-set_tdm_slot-interface.patch b/target/linux/brcm2708/patches-4.14/950-0229-ASoC-pcm512x-implement-set_tdm_slot-interface.patch
deleted file mode 100644
index 738b56060..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0229-ASoC-pcm512x-implement-set_tdm_slot-interface.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 60e945e3c654aae415773a500b021914461ae928 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Thu, 22 Feb 2018 11:55:06 +0100
-Subject: [PATCH 229/454] ASoC: pcm512x: implement set_tdm_slot interface
-
-PCM512x can accept data padded with additional BCLK cycles
-but the driver currently lacks an interface to configure this.
-
-This leads to the problem that S24_LE format in master mode
-can result in non-integer clock divisors and pcm512x running
-at a rather off rate.
-
-For example 48kHz with 48fs BCLK and SCLK at 24.576MHz uses
-a divisor of 10 (rounded down from 10.6666) and results in a
-51.2kHz LRCLK. With 64fs BCLK a divisor of 8 is used and
-LRCLK runs at exactly 48kHz.
-
-Fix this by providing a minimal set_tdm_slot implementation
-so machine drivers can optionally configure custom BCLK ratios.
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/codecs/pcm512x.c | 28 +++++++++++++++++++++++++++-
- 1 file changed, 27 insertions(+), 1 deletion(-)
-
---- a/sound/soc/codecs/pcm512x.c
-+++ b/sound/soc/codecs/pcm512x.c
-@@ -53,6 +53,7 @@ struct pcm512x_priv {
- 	unsigned long overclock_pll;
- 	unsigned long overclock_dac;
- 	unsigned long overclock_dsp;
-+	int lrclk_div;
- };
- 
- /*
-@@ -851,7 +852,10 @@ static int pcm512x_set_dividers(struct s
- 	int fssp;
- 	int gpio;
- 
--	lrclk_div = snd_soc_params_to_frame_size(params);
-+	if (pcm512x->lrclk_div)
-+		lrclk_div = pcm512x->lrclk_div;
-+	else
-+		lrclk_div = snd_soc_params_to_frame_size(params);
- 	if (lrclk_div == 0) {
- 		dev_err(dev, "No LRCLK?\n");
- 		return -EINVAL;
-@@ -1319,10 +1323,32 @@ static int pcm512x_set_fmt(struct snd_so
- 	return 0;
- }
- 
-+static int pcm512x_set_tdm_slot(struct snd_soc_dai *dai,
-+	unsigned int tx_mask, unsigned int rx_mask,
-+	int slots, int width)
-+{
-+	struct snd_soc_codec *codec = dai->codec;
-+	struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
-+
-+	switch (slots) {
-+	case 0:
-+		pcm512x->lrclk_div = 0;
-+		return 0;
-+	case 2:
-+		if (tx_mask != 0x03 || rx_mask != 0x03)
-+			return -EINVAL;
-+		pcm512x->lrclk_div = slots * width;
-+		return 0;
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
- static const struct snd_soc_dai_ops pcm512x_dai_ops = {
- 	.startup = pcm512x_dai_startup,
- 	.hw_params = pcm512x_hw_params,
- 	.set_fmt = pcm512x_set_fmt,
-+	.set_tdm_slot = pcm512x_set_tdm_slot,
- };
- 
- static struct snd_soc_dai_driver pcm512x_dai = {
diff --git a/target/linux/brcm2708/patches-4.14/950-0230-ASoC-allo-boss-dac-transmit-S24_LE-with-64-BCLK-cycl.patch b/target/linux/brcm2708/patches-4.14/950-0230-ASoC-allo-boss-dac-transmit-S24_LE-with-64-BCLK-cycl.patch
deleted file mode 100644
index 4197d4a1d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0230-ASoC-allo-boss-dac-transmit-S24_LE-with-64-BCLK-cycl.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 1d5b2b562fd800069f4090142e201d696ad1122a Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Thu, 22 Feb 2018 13:07:53 +0100
-Subject: [PATCH 230/454] ASoC: allo-boss-dac: transmit S24_LE with 64 BCLK
- cycles
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/allo-boss-dac.c | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/sound/soc/bcm/allo-boss-dac.c
-+++ b/sound/soc/bcm/allo-boss-dac.c
-@@ -273,6 +273,8 @@ static int snd_allo_boss_hw_params(
- {
- 	int ret = 0;
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	int channels = params_channels(params);
-+	int width = snd_pcm_format_physical_width(params_format(params));
- 
- 	if (snd_soc_allo_boss_master) {
- 		struct snd_soc_codec *codec = rtd->codec;
-@@ -282,7 +284,16 @@ static int snd_allo_boss_hw_params(
- 
- 		ret = snd_allo_boss_update_rate_den(
- 			substream, params);
-+		if (ret)
-+			return ret;
- 	}
-+
-+	ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, 0x03, 0x03,
-+		channels, width);
-+	if (ret)
-+		return ret;
-+	ret = snd_soc_dai_set_tdm_slot(rtd->codec_dai, 0x03, 0x03,
-+		channels, width);
- 	return ret;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0231-ASoC-hifiberry_dacplus-transmit-S24_LE-with-64-BCLK-.patch b/target/linux/brcm2708/patches-4.14/950-0231-ASoC-hifiberry_dacplus-transmit-S24_LE-with-64-BCLK-.patch
deleted file mode 100644
index 8c2bdbc7c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0231-ASoC-hifiberry_dacplus-transmit-S24_LE-with-64-BCLK-.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 05a5419c9e0ec993bc8dafd60e9fbe6c04e9e8c0 Mon Sep 17 00:00:00 2001
-From: Matthias Reichl <hias@horus.com>
-Date: Thu, 22 Feb 2018 13:09:30 +0100
-Subject: [PATCH 231/454] ASoC: hifiberry_dacplus: transmit S24_LE with 64 BCLK
- cycles
-
-Signed-off-by: Matthias Reichl <hias@horus.com>
----
- sound/soc/bcm/hifiberry_dacplus.c | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/sound/soc/bcm/hifiberry_dacplus.c
-+++ b/sound/soc/bcm/hifiberry_dacplus.c
-@@ -221,16 +221,27 @@ static int snd_rpi_hifiberry_dacplus_hw_
- {
- 	int ret = 0;
- 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	int channels = params_channels(params);
-+	int width = 32;
- 
- 	if (snd_rpi_hifiberry_is_dacpro) {
- 		struct snd_soc_codec *codec = rtd->codec;
- 
-+		width = snd_pcm_format_physical_width(params_format(params));
-+
- 		snd_rpi_hifiberry_dacplus_set_sclk(codec,
- 			params_rate(params));
- 
- 		ret = snd_rpi_hifiberry_dacplus_update_rate_den(
- 			substream, params);
- 	}
-+
-+	ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, 0x03, 0x03,
-+		channels, width);
-+	if (ret)
-+		return ret;
-+	ret = snd_soc_dai_set_tdm_slot(rtd->codec_dai, 0x03, 0x03,
-+		channels, width);
- 	return ret;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0232-Fixing-memset-call-in-pisound.c.patch b/target/linux/brcm2708/patches-4.14/950-0232-Fixing-memset-call-in-pisound.c.patch
deleted file mode 100644
index 12e31a886..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0232-Fixing-memset-call-in-pisound.c.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 398bc58d0a05fb080e58051a33915607c71e58df Mon Sep 17 00:00:00 2001
-From: Giedrius <giedrius@blokas.io>
-Date: Sat, 24 Feb 2018 14:47:02 +0200
-Subject: [PATCH 232/454] Fixing memset call in pisound.c
-
-Signed-off-by: Giedrius Trainavicius <giedrius@blokas.io>
----
- sound/soc/bcm/pisound.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/sound/soc/bcm/pisound.c
-+++ b/sound/soc/bcm/pisound.c
-@@ -313,7 +313,7 @@ static void spi_transfer(const uint8_t *
- 	struct spi_transfer transfer;
- 	struct spi_message msg;
- 
--	memset(rxbuf, 0, sizeof(txbuf));
-+	memset(rxbuf, 0, len);
- 
- 	if (!pisnd_spi_device) {
- 		printe("pisnd_spi_device null, returning\n");
diff --git a/target/linux/brcm2708/patches-4.14/950-0233-overlays-Rework-sdio-overlays-to-allow-polling.patch b/target/linux/brcm2708/patches-4.14/950-0233-overlays-Rework-sdio-overlays-to-allow-polling.patch
deleted file mode 100644
index d376bdde8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0233-overlays-Rework-sdio-overlays-to-allow-polling.patch
+++ /dev/null
@@ -1,156 +0,0 @@
-From 152d226fd2eff1fdc1f8881287bf1a7d4560b27e Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 26 Feb 2018 19:46:32 +0000
-Subject: [PATCH 233/454] overlays: Rework sdio overlays to allow polling
-
-MMC/SD interfaces support a DT property (non-removable) that disables
-the usual polling required to detect card removal for a configuration
-that doesn't have hardware card presence detection. This property is
-required for the on-board SDIO WiFi interface, but other uses of the
-interface may want the polling to be re-enabled.
-
-'non-removable' is a boolean DT property - true if present, false if
-absent - and the overlay mechanism does not allow a property in the
-base DTB to be deleted, so if the base DTB has non-removable set
-(which is true for all WiFi-equipped Pis) then an overlay cannot
-unset it.
-
-Modify the SDIO overlays to work around this problem by disabling
-the mmc node and adding a clone to which non-removable may
-optionally be added.
-
-N.B. The default state of poll_once is still true, and the overlay
-does include a non-removable property, but setting poll_once to false
-("off") will remove the property from the overlay before it is applied.
-
-See: https://github.com/raspberrypi/linux/issues/2401
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- .../boot/dts/overlays/sdio-1bit-overlay.dts   | 40 +++++++++++++-----
- arch/arm/boot/dts/overlays/sdio-overlay.dts   | 41 ++++++++++++++-----
- 2 files changed, 59 insertions(+), 22 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/sdio-1bit-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/sdio-1bit-overlay.dts
-@@ -8,21 +8,39 @@
- 
- 	fragment@0 {
- 		target = <&mmc>;
--		sdio_mmc: __overlay__ {
--			compatible = "brcm,bcm2835-mmc";
--			pinctrl-names = "default";
--			pinctrl-0 = <&sdio_pins>;
--			non-removable;
--			bus-width = <1>;
--			brcm,overclock-50 = <0>;
--			status = "okay";
-+		__overlay__ {
-+			status = "disabled";
- 		};
- 	};
- 
- 	fragment@1 {
-+		target = <&soc>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			sdio_1bit: sdio@7e300000 {
-+				compatible = "brcm,bcm2835-mmc",
-+					     "brcm,bcm2835-sdhci";
-+				reg = <0x7e300000 0x100>;
-+				interrupts = <2 30>;
-+				clocks = <&clocks 28/*BCM2835_CLOCK_EMMC*/>;
-+				dmas = <&dma 11>;
-+				dma-names = "rx-tx";
-+				brcm,overclock-50 = <0>;
-+				status = "okay";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&sdio_1bit_pins>;
-+				non-removable;
-+				bus-width = <1>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
- 		target = <&gpio>;
- 		__overlay__ {
--			sdio_pins: sdio_pins {
-+			sdio_1bit_pins: sdio_1bit_pins {
- 				brcm,pins = <22 23 24 25>;
- 				brcm,function = <7>; /* ALT3 = SD1 */
- 				brcm,pull = <0 2 2 2>;
-@@ -31,7 +49,7 @@
- 	};
- 
- 	__overrides__ {
--		poll_once = <&sdio_mmc>,"non-removable?";
--		sdio_overclock = <&sdio_mmc>,"brcm,overclock-50:0";
-+		poll_once = <&sdio_1bit>,"non-removable?";
-+		sdio_overclock = <&sdio_1bit>,"brcm,overclock-50:0";
- 	};
- };
---- a/arch/arm/boot/dts/overlays/sdio-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts
-@@ -8,20 +8,39 @@
- 
- 	fragment@0 {
- 		target = <&mmc>;
--		sdio_mmc: __overlay__ {
--			pinctrl-names = "default";
--			pinctrl-0 = <&sdio_pins>;
--			non-removable;
--			bus-width = <4>;
--			brcm,overclock-50 = <0>;
--			status = "okay";
-+		__overlay__ {
-+			status = "disabled";
- 		};
- 	};
- 
- 	fragment@1 {
-+		target = <&soc>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+
-+			sdio_ovl: sdio@7e300000 {
-+				compatible = "brcm,bcm2835-mmc",
-+					     "brcm,bcm2835-sdhci";
-+				reg = <0x7e300000 0x100>;
-+				interrupts = <2 30>;
-+				clocks = <&clocks 28/*BCM2835_CLOCK_EMMC*/>;
-+				dmas = <&dma 11>;
-+				dma-names = "rx-tx";
-+				brcm,overclock-50 = <0>;
-+				status = "okay";
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&sdio_ovl_pins>;
-+				non-removable;
-+				bus-width = <1>;
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
- 		target = <&gpio>;
- 		__overlay__ {
--			sdio_pins: sdio_pins {
-+			sdio_ovl_pins: sdio_ovl_pins {
- 				brcm,pins = <22 23 24 25 26 27>;
- 				brcm,function = <7>; /* ALT3 = SD1 */
- 				brcm,pull = <0 2 2 2 2 2>;
-@@ -30,8 +49,8 @@
- 	};
- 
- 	__overrides__ {
--		poll_once = <&sdio_mmc>,"non-removable?";
--		bus_width = <&sdio_mmc>,"bus-width:0";
--		sdio_overclock = <&sdio_mmc>,"brcm,overclock-50:0";
-+		poll_once = <&sdio_ovl>,"non-removable?";
-+		bus_width = <&sdio_ovl>,"bus-width:0";
-+		sdio_overclock = <&sdio_ovl>,"brcm,overclock-50:0";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0234-firmware-raspberrypi-Add-a-get_throttled-sysfs-file.patch b/target/linux/brcm2708/patches-4.14/950-0234-firmware-raspberrypi-Add-a-get_throttled-sysfs-file.patch
deleted file mode 100644
index ad6ea4b99..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0234-firmware-raspberrypi-Add-a-get_throttled-sysfs-file.patch
+++ /dev/null
@@ -1,206 +0,0 @@
-From 83a8df1b7fff284fc3c2277c8051f53acde2e64f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
-Date: Sat, 24 Feb 2018 13:41:25 +0100
-Subject: [PATCH 234/454] firmware/raspberrypi: Add a get_throttled sysfs file
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Under-voltage due to inadequate power supplies is a recurring problem for
-new Raspberry Pi users. There are visual indications that an
-under-voltage situation is occuring like blinking power led and a
-lightning icon on the desktop (not shown when using the vc4 driver), but
-for new users it's not obvious that this signifies a critical situation.
-
-This patch provides a twofold improvement to the situation:
-
-Firstly it logs under-voltage events to the kernel log. This provides
-information also for headless installations.
-
-Secondly it provides a sysfs file to read the value. This improves on
-'vcgencmd' by providing change notification. Userspace can poll on the
-file and be notified of changes to the value.
-A script can poll the file and use dbus notification to put a windows on
-the desktop with information about the severity with a recommendation to
-change the power supply. A link to more information can also be provided.
-Only changes to the sticky bits are reported (cleared between readings).
-
-Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
----
- drivers/firmware/raspberrypi.c             | 108 +++++++++++++++++++++
- include/soc/bcm2835/raspberrypi-firmware.h |   1 +
- 2 files changed, 109 insertions(+)
-
---- a/drivers/firmware/raspberrypi.c
-+++ b/drivers/firmware/raspberrypi.c
-@@ -14,6 +14,7 @@
- #include <linux/module.h>
- #include <linux/of_platform.h>
- #include <linux/platform_device.h>
-+#include <linux/workqueue.h>
- #include <soc/bcm2835/raspberrypi-firmware.h>
- 
- #define MBOX_MSG(chan, data28)		(((data28) & ~0xf) | ((chan) & 0xf))
-@@ -21,11 +22,14 @@
- #define MBOX_DATA28(msg)		((msg) & ~0xf)
- #define MBOX_CHAN_PROPERTY		8
- 
-+#define UNDERVOLTAGE_BIT		BIT(0)
-+
- struct rpi_firmware {
- 	struct mbox_client cl;
- 	struct mbox_chan *chan; /* The property channel. */
- 	struct completion c;
- 	u32 enabled;
-+	struct delayed_work get_throttled_poll_work;
- };
- 
- static struct platform_device *g_pdev;
-@@ -166,6 +170,101 @@ int rpi_firmware_property(struct rpi_fir
- }
- EXPORT_SYMBOL_GPL(rpi_firmware_property);
- 
-+static int rpi_firmware_get_throttled(struct rpi_firmware *fw, u32 *value)
-+{
-+	static ktime_t old_timestamp;
-+	static u32 old_value;
-+	u32 new_sticky, old_sticky, new_uv, old_uv;
-+	ktime_t new_timestamp;
-+	s64 elapsed_ms;
-+	int ret;
-+
-+	if (!fw)
-+		return -EBUSY;
-+
-+	/*
-+	 * We can't run faster than the sticky shift (100ms) since we get
-+	 * flipping in the sticky bits that are cleared.
-+	 * This happens on polling, so just return the previous value.
-+	 */
-+	new_timestamp = ktime_get();
-+	elapsed_ms = ktime_ms_delta(new_timestamp, old_timestamp);
-+	if (elapsed_ms < 150) {
-+		*value = old_value;
-+		return 0;
-+	}
-+	old_timestamp = new_timestamp;
-+
-+	/* Clear sticky bits */
-+	*value = 0xffff;
-+
-+	ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_THROTTLED,
-+				    value, sizeof(*value));
-+	if (ret)
-+		return ret;
-+
-+	new_sticky = *value >> 16;
-+	old_sticky = old_value >> 16;
-+	old_value = *value;
-+
-+	/* Only notify about changes in the sticky bits */
-+	if (new_sticky == old_sticky)
-+		return 0;
-+
-+	new_uv = new_sticky & UNDERVOLTAGE_BIT;
-+	old_uv = old_sticky & UNDERVOLTAGE_BIT;
-+
-+	if (new_uv != old_uv) {
-+		if (new_uv)
-+			pr_crit("Under-voltage detected! (0x%08x)\n", *value);
-+		else
-+			pr_info("Voltage normalised (0x%08x)\n", *value);
-+	}
-+
-+	sysfs_notify(&fw->cl.dev->kobj, NULL, "get_throttled");
-+
-+	return 0;
-+}
-+
-+static void get_throttled_poll(struct work_struct *work)
-+{
-+	struct rpi_firmware *fw = container_of(work, struct rpi_firmware,
-+					       get_throttled_poll_work.work);
-+	u32 dummy;
-+	int ret;
-+
-+	ret = rpi_firmware_get_throttled(fw, &dummy);
-+	if (ret)
-+		pr_debug("%s: Failed to read value (%d)", __func__, ret);
-+
-+	schedule_delayed_work(&fw->get_throttled_poll_work, 2 * HZ);
-+}
-+
-+static ssize_t get_throttled_show(struct device *dev,
-+				  struct device_attribute *attr, char *buf)
-+{
-+	struct rpi_firmware *fw = dev_get_drvdata(dev);
-+	u32 value;
-+	int ret;
-+
-+	ret = rpi_firmware_get_throttled(fw, &value);
-+	if (ret)
-+		return ret;
-+
-+	return sprintf(buf, "%x\n", value);
-+}
-+
-+static DEVICE_ATTR_RO(get_throttled);
-+
-+static struct attribute *rpi_firmware_dev_attrs[] = {
-+	&dev_attr_get_throttled.attr,
-+	NULL,
-+};
-+
-+static const struct attribute_group rpi_firmware_dev_group = {
-+	.attrs = rpi_firmware_dev_attrs,
-+};
-+
- static void
- rpi_firmware_print_firmware_revision(struct rpi_firmware *fw)
- {
-@@ -190,6 +289,11 @@ static int rpi_firmware_probe(struct pla
- {
- 	struct device *dev = &pdev->dev;
- 	struct rpi_firmware *fw;
-+	int ret;
-+
-+	ret = devm_device_add_group(dev, &rpi_firmware_dev_group);
-+	if (ret)
-+		return ret;
- 
- 	fw = devm_kzalloc(dev, sizeof(*fw), GFP_KERNEL);
- 	if (!fw)
-@@ -208,12 +312,15 @@ static int rpi_firmware_probe(struct pla
- 	}
- 
- 	init_completion(&fw->c);
-+	INIT_DELAYED_WORK(&fw->get_throttled_poll_work, get_throttled_poll);
- 
- 	platform_set_drvdata(pdev, fw);
- 	g_pdev = pdev;
- 
- 	rpi_firmware_print_firmware_revision(fw);
- 
-+	schedule_delayed_work(&fw->get_throttled_poll_work, 0);
-+
- 	return 0;
- }
- 
-@@ -221,6 +328,7 @@ static int rpi_firmware_remove(struct pl
- {
- 	struct rpi_firmware *fw = platform_get_drvdata(pdev);
- 
-+	cancel_delayed_work_sync(&fw->get_throttled_poll_work);
- 	mbox_free_channel(fw->chan);
- 	g_pdev = NULL;
- 
---- a/include/soc/bcm2835/raspberrypi-firmware.h
-+++ b/include/soc/bcm2835/raspberrypi-firmware.h
-@@ -77,6 +77,7 @@ enum rpi_firmware_property_tag {
- 	RPI_FIRMWARE_GET_EDID_BLOCK =                         0x00030020,
- 	RPI_FIRMWARE_GET_CUSTOMER_OTP =                       0x00030021,
- 	RPI_FIRMWARE_GET_DOMAIN_STATE =                       0x00030030,
-+	RPI_FIRMWARE_GET_THROTTLED =                          0x00030046,
- 	RPI_FIRMWARE_SET_CLOCK_STATE =                        0x00038001,
- 	RPI_FIRMWARE_SET_CLOCK_RATE =                         0x00038002,
- 	RPI_FIRMWARE_SET_VOLTAGE =                            0x00038003,
diff --git a/target/linux/brcm2708/patches-4.14/950-0235-overlays-Add-overlay-for-PiBell-soundcard.patch b/target/linux/brcm2708/patches-4.14/950-0235-overlays-Add-overlay-for-PiBell-soundcard.patch
deleted file mode 100644
index 3ef74df4f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0235-overlays-Add-overlay-for-PiBell-soundcard.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From 36a2db8647b19b0c8576a10ab787b14098049f9b Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 28 Feb 2018 21:29:42 +0000
-Subject: [PATCH 235/454] overlays: Add overlay for PiBell soundcard
-
-This overlay is presented as another example of using the simple card
-driver.
-
-See: https://www.raspberrypi.org/forums/viewtopic.php?f=44&t=99784&p=1279490#p1278971
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  7 ++
- arch/arm/boot/dts/overlays/pibell-overlay.dts | 81 +++++++++++++++++++
- 3 files changed, 89 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/pibell-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -76,6 +76,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	pi3-disable-bt.dtbo \
- 	pi3-disable-wifi.dtbo \
- 	pi3-miniuart-bt.dtbo \
-+	pibell.dtbo \
- 	piscreen.dtbo \
- 	piscreen2r.dtbo \
- 	pisound.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1182,6 +1182,13 @@ Load:   dtoverlay=pi3-miniuart-bt
- Params: <None>
- 
- 
-+Name:   pibell
-+Info:   Configures the pibell audio card.
-+Load:   dtoverlay=pibell,<param>=<val>
-+Params: alsaname                Set the name as it appears in ALSA (default
-+                                "PiBell")
-+
-+
- Name:   piscreen
- Info:   PiScreen display by OzzMaker.com
- Load:   dtoverlay=piscreen,<param>=<val>
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/pibell-overlay.dts
-@@ -0,0 +1,81 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+    compatible = "brcm,bcm2708";
-+
-+    fragment@0 {
-+        target-path = "/";
-+        __overlay__ {
-+            codec_out: spdif-transmitter {
-+                #address-cells = <0>;
-+                #size-cells = <0>;
-+                #sound-dai-cells = <0>;
-+                compatible = "linux,spdif-dit";
-+                status = "okay";
-+            };
-+
-+            codec_in: card-codec {
-+                #sound-dai-cells = <0>;
-+                compatible = "invensense,ics43432";
-+                status = "okay";
-+            };
-+        };
-+    };
-+
-+    fragment@1 {
-+        target = <&i2s>;
-+        __overlay__ {
-+            #sound-dai-cells = <0>;
-+            status = "okay";
-+        };
-+    };
-+
-+    fragment@2 {
-+        target = <&sound>;
-+        snd: __overlay__ {
-+            compatible = "simple-audio-card";
-+            simple-audio-card,name = "PiBell";
-+
-+            status="okay";
-+
-+            capture_link: simple-audio-card,dai-link@0 {
-+                format = "i2s";
-+
-+                r_cpu_dai: cpu {
-+                    sound-dai = <&i2s>;
-+
-+/* example TDM slot configuration
-+                    dai-tdm-slot-num = <2>;
-+                    dai-tdm-slot-width = <32>;
-+*/
-+                };
-+
-+                r_codec_dai: codec {
-+                    sound-dai = <&codec_in>;
-+                };
-+            };
-+
-+            playback_link: simple-audio-card,dai-link@1 {
-+                format = "i2s";
-+
-+                p_cpu_dai: cpu {
-+                    sound-dai = <&i2s>;
-+
-+/* example TDM slot configuration
-+                    dai-tdm-slot-num = <2>;
-+                    dai-tdm-slot-width = <32>;
-+*/
-+                };
-+
-+                p_codec_dai: codec {
-+                    sound-dai = <&codec_out>;
-+                };
-+            };
-+        };
-+    };
-+
-+    __overrides__ {
-+        alsaname = <&snd>, "simple-audio-card,name";
-+    };
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0236-Removing-broken-RaspiDac3-support.patch b/target/linux/brcm2708/patches-4.14/950-0236-Removing-broken-RaspiDac3-support.patch
deleted file mode 100644
index 5f8974fb7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0236-Removing-broken-RaspiDac3-support.patch
+++ /dev/null
@@ -1,339 +0,0 @@
-From 50e9c65f5062bba726f94374127ea89f78102aa3 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 28 Feb 2018 22:28:14 +0000
-Subject: [PATCH 236/454] Removing (broken) RaspiDac3 support...
-
-...at the request of the author.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |   1 -
- arch/arm/boot/dts/overlays/README             |   6 -
- .../boot/dts/overlays/raspidac3-overlay.dts   |  49 -----
- arch/arm/configs/bcm2709_defconfig            |   1 -
- arch/arm/configs/bcmrpi_defconfig             |   1 -
- arch/arm64/configs/bcmrpi3_defconfig          |   1 -
- sound/soc/bcm/Kconfig                         |   8 -
- sound/soc/bcm/Makefile                        |   2 -
- sound/soc/bcm/raspidac3.c                     | 172 ------------------
- 9 files changed, 241 deletions(-)
- delete mode 100644 arch/arm/boot/dts/overlays/raspidac3-overlay.dts
- delete mode 100644 sound/soc/bcm/raspidac3.c
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -89,7 +89,6 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	pwm-2chan.dtbo \
- 	pwm-ir-tx.dtbo \
- 	qca7000.dtbo \
--	raspidac3.dtbo \
- 	rotary-encoder.dtbo \
- 	rpi-backlight.dtbo \
- 	rpi-cirrus-wm5102.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1350,12 +1350,6 @@ Params: int_pin                 GPIO pin
-         speed                   SPI bus speed (default 12 MHz)
- 
- 
--Name:   raspidac3
--Info:   Configures the RaspiDAV Rev.3x audio card
--Load:   dtoverlay=raspidac3
--Params: <None>
--
--
- Name:   rotary-encoder
- Info:   Overlay for GPIO connected rotary encoder.
- Load:   dtoverlay=rotary-encoder,<param>=<val>
---- a/arch/arm/boot/dts/overlays/raspidac3-overlay.dts
-+++ /dev/null
-@@ -1,49 +0,0 @@
--// Definitions for RaspiDACv3
--/dts-v1/;
--/plugin/;
--
--/ {
--	compatible = "brcm,bcm2708";
--
--	fragment@0 {
--		target = <&i2s>;
--		__overlay__ {
--			status = "okay";
--		};
--	};
--
--	fragment@1 {
--		target = <&i2c1>;
--		__overlay__ {
--			#address-cells = <1>;
--			#size-cells = <0>;
--			status = "okay";
--
--			pcm5122@4c {
--				#sound-dai-cells = <0>;
--				compatible = "ti,pcm5122";
--				reg = <0x4c>;
--				AVDD-supply = <&vdd_3v3_reg>;
--				DVDD-supply = <&vdd_3v3_reg>;
--				CPVDD-supply = <&vdd_3v3_reg>;
--				status = "okay";
--			};
--
--			tpa6130a2: tpa6130a2@60 {
--				compatible = "ti,tpa6130a2";
--				reg = <0x60>;
--				Vdd-supply = <&vdd_3v3_reg>;
--				status = "okay";
--			};
--		};
--	};
--
--	fragment@2 {
--		target = <&sound>;
--		__overlay__ {
--			compatible = "jg,raspidacv3";
--			i2s-controller = <&i2s>;
--			status = "okay";
--		};
--	};
--};
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -879,7 +879,6 @@ CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m
- CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m
- CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
- CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m
--CONFIG_SND_BCM2708_SOC_RASPIDAC3=m
- CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m
- CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m
- CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -872,7 +872,6 @@ CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m
- CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m
- CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
- CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m
--CONFIG_SND_BCM2708_SOC_RASPIDAC3=m
- CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m
- CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m
- CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -861,7 +861,6 @@ CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m
- CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m
- CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
- CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m
--CONFIG_SND_BCM2708_SOC_RASPIDAC3=m
- CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m
- CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m
- CONFIG_SND_DIGIDAC1_SOUNDCARD=m
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -104,14 +104,6 @@ config SND_BCM2708_SOC_IQAUDIO_DIGI
-         help
-          Say Y or M if you want to add support for IQAudIO Digital IO board.
- 
--config SND_BCM2708_SOC_RASPIDAC3
--	tristate "Support for RaspiDAC Rev.3x"
--	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
--	select SND_SOC_PCM512x_I2C
--	select SND_SOC_TPA6130A2
--	help
--	  Say Y or M if you want to add support for RaspiDAC Rev.3x.
--
- config SND_BCM2708_SOC_ADAU1977_ADC
- 	tristate "Support for ADAU1977 ADC"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -25,7 +25,6 @@ snd-soc-rpi-dac-objs := rpi-dac.o
- snd-soc-rpi-proto-objs := rpi-proto.o
- snd-soc-iqaudio-dac-objs := iqaudio-dac.o
- snd-soc-iqaudio-digi-objs := iqaudio_digi.o
--snd-soc-raspidac3-objs := raspidac3.o
- snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o
- snd-soc-audioinjector-octo-soundcard-objs := audioinjector-octo-soundcard.o
- snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o
-@@ -52,7 +51,6 @@ obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) +=
- obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI) += snd-soc-iqaudio-digi.o
--obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o
- obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o
- obj-$(CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD) += snd-soc-audioinjector-octo-soundcard.o
- obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o
---- a/sound/soc/bcm/raspidac3.c
-+++ /dev/null
-@@ -1,172 +0,0 @@
--/*
-- * ASoC Driver for RaspiDAC v3
-- *
-- * Author:	Jan Grulich <jan@grulich.eu>
-- *		Copyright 2015
-- *              based on code by Daniel Matuschek <daniel@hifiberry.com>
-- *		based on code by Florian Meier <florian.meier@koalo.de>
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License
-- * version 2 as published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope that it will be useful, but
-- * WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- * General Public License for more details.
-- */
--
--#include <linux/module.h>
--#include <linux/platform_device.h>
--
--#include <sound/core.h>
--#include <sound/pcm.h>
--#include <sound/pcm_params.h>
--#include <sound/soc.h>
--#include <sound/jack.h>
--#include <sound/soc-dapm.h>
--
--#include "../codecs/pcm512x.h"
--#include "../codecs/tpa6130a2.h"
--
--/* sound card init */
--static int snd_rpi_raspidac3_init(struct snd_soc_pcm_runtime *rtd)
--{
--	int ret;
--	struct snd_soc_card *card = rtd->card;
--	struct snd_soc_codec *codec = rtd->codec;
--	snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
--	snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);
--	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
--
--	ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207);
--	if (ret < 0)
--		dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
--	else {
--		struct snd_kcontrol *kctl;
--
--		ret = snd_soc_limit_volume(card,
--					   "TPA6130A2 Headphone Playback Volume",
--					   54);
--		if (ret < 0)
--			dev_warn(card->dev, "Failed to set TPA6130A2 volume limit: %d\n",
--				 ret);
--		kctl = snd_soc_card_get_kcontrol(card,
--						 "TPA6130A2 Headphone Playback Volume");
--		if (kctl) {
--			strcpy(kctl->id.name, "Headphones Playback Volume");
--			/* disable the volume dB scale so alsamixer works */
--			kctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
--		}
--
--		kctl = snd_soc_card_get_kcontrol(card,
--						 "TPA6130A2 Headphone Playback Switch");
--		if (kctl)
--			strcpy(kctl->id.name, "Headphones Playback Switch");
--	}
--
--	return 0;
--}
--
--/* startup */
--static int snd_rpi_raspidac3_startup(struct snd_pcm_substream *substream) {
--	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_codec *codec = rtd->codec;
--	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
--	return 0;
--}
--
--/* shutdown */
--static void snd_rpi_raspidac3_shutdown(struct snd_pcm_substream *substream) {
--	struct snd_soc_pcm_runtime *rtd = substream->private_data;
--	struct snd_soc_codec *codec = rtd->codec;
--	snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
--}
--
--/* machine stream operations */
--static struct snd_soc_ops snd_rpi_raspidac3_ops = {
--	.startup = snd_rpi_raspidac3_startup,
--	.shutdown = snd_rpi_raspidac3_shutdown,
--};
--
--/* interface setup */
--static struct snd_soc_dai_link snd_rpi_raspidac3_dai[] = {
--{
--	.name		= "RaspiDAC Rev.3x",
--	.stream_name	= "RaspiDAC HiFi",
--	.cpu_dai_name	= "bcm2708-i2s.0",
--	.codec_dai_name	= "pcm512x-hifi",
--	.platform_name	= "bcm2708-i2s.0",
--	.codec_name	= "pcm512x.1-004c",
--	.dai_fmt	= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
--				SND_SOC_DAIFMT_CBS_CFS,
--	.ops		= &snd_rpi_raspidac3_ops,
--	.init		= snd_rpi_raspidac3_init,
--},
--};
--
--/* audio machine driver */
--static struct snd_soc_card snd_rpi_raspidac3 = {
--	.name         = "RaspiDAC Rev.3x HiFi Audio Card",
--	.owner        = THIS_MODULE,
--	.dai_link     = snd_rpi_raspidac3_dai,
--	.num_links    = ARRAY_SIZE(snd_rpi_raspidac3_dai),
--};
--
--/* sound card test */
--static int snd_rpi_raspidac3_probe(struct platform_device *pdev)
--{
--	int ret = 0;
--
--	snd_rpi_raspidac3.dev = &pdev->dev;
--
--	if (pdev->dev.of_node) {
--	    struct device_node *i2s_node;
--	    struct snd_soc_dai_link *dai = &snd_rpi_raspidac3_dai[0];
--	    i2s_node = of_parse_phandle(pdev->dev.of_node,
--					"i2s-controller", 0);
--
--	    if (i2s_node) {
--		dai->cpu_dai_name = NULL;
--		dai->cpu_of_node = i2s_node;
--		dai->platform_name = NULL;
--		dai->platform_of_node = i2s_node;
--	    }
--	}
--
--	ret = snd_soc_register_card(&snd_rpi_raspidac3);
--	if (ret && ret != -EPROBE_DEFER)
--		dev_err(&pdev->dev,
--			"snd_soc_register_card() failed: %d\n", ret);
--
--	return ret;
--}
--
--/* sound card disconnect */
--static int snd_rpi_raspidac3_remove(struct platform_device *pdev)
--{
--	return snd_soc_unregister_card(&snd_rpi_raspidac3);
--}
--
--static const struct of_device_id raspidac3_of_match[] = {
--	{ .compatible = "jg,raspidacv3", },
--	{},
--};
--MODULE_DEVICE_TABLE(of, raspidac3_of_match);
--
--/* sound card platform driver */
--static struct platform_driver snd_rpi_raspidac3_driver = {
--	.driver = {
--		.name   = "snd-rpi-raspidac3",
--		.owner  = THIS_MODULE,
--		.of_match_table = raspidac3_of_match,
--	},
--	.probe          = snd_rpi_raspidac3_probe,
--	.remove         = snd_rpi_raspidac3_remove,
--};
--
--module_platform_driver(snd_rpi_raspidac3_driver);
--
--MODULE_AUTHOR("Jan Grulich <jan@grulich.eu>");
--MODULE_DESCRIPTION("ASoC Driver for RaspiDAC Rev.3x");
--MODULE_LICENSE("GPL v2");
diff --git a/target/linux/brcm2708/patches-4.14/950-0237-overlays-Add-updated-mmc1-alias-to-sdio-overlays.patch b/target/linux/brcm2708/patches-4.14/950-0237-overlays-Add-updated-mmc1-alias-to-sdio-overlays.patch
deleted file mode 100644
index c1ed6d26b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0237-overlays-Add-updated-mmc1-alias-to-sdio-overlays.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 8229937ec299133cf93654b9afc46e5288767ace Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 1 Mar 2018 21:36:30 +0000
-Subject: [PATCH 237/454] overlays: Add updated mmc1 alias to sdio overlays
-
-In the downstream RPi kernel, aliases are used to assign instance
-numbers to the SD/MMC interfaces. The updated sdio overlays
-effectively rename the device node, so the mmc1 alias has to be
-updated in order to preserve the mmc1 numbering, otherwise the device
-will appear as mmc2.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/sdio-1bit-overlay.dts | 8 ++++++++
- arch/arm/boot/dts/overlays/sdio-overlay.dts      | 7 +++++++
- 2 files changed, 15 insertions(+)
-
---- a/arch/arm/boot/dts/overlays/sdio-1bit-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/sdio-1bit-overlay.dts
-@@ -48,6 +48,14 @@
- 		};
- 	};
- 
-+	fragment@3 {
-+		target-path = "/aliases";
-+		__overlay__ {
-+			mmc1 = "/soc/sdio@7e300000";
-+		};
-+	};
-+
-+
- 	__overrides__ {
- 		poll_once = <&sdio_1bit>,"non-removable?";
- 		sdio_overclock = <&sdio_1bit>,"brcm,overclock-50:0";
---- a/arch/arm/boot/dts/overlays/sdio-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts
-@@ -48,6 +48,13 @@
- 		};
- 	};
- 
-+	fragment@3 {
-+		target-path = "/aliases";
-+		__overlay__ {
-+			mmc1 = "/soc/sdio@7e300000";
-+		};
-+	};
-+
- 	__overrides__ {
- 		poll_once = <&sdio_ovl>,"non-removable?";
- 		bus_width = <&sdio_ovl>,"bus-width:0";
diff --git a/target/linux/brcm2708/patches-4.14/950-0238-config-Enable-CONFIG_GPIO_MOCKUP-module.patch b/target/linux/brcm2708/patches-4.14/950-0238-config-Enable-CONFIG_GPIO_MOCKUP-module.patch
deleted file mode 100644
index 21593f2c7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0238-config-Enable-CONFIG_GPIO_MOCKUP-module.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 75572d01e21c8ad7a1edfe331cf87073ca3c0134 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Fri, 2 Mar 2018 13:26:51 +0000
-Subject: [PATCH 238/454] config: Enable CONFIG_GPIO_MOCKUP module
-
----
- arch/arm/configs/bcm2709_defconfig | 2 +-
- arch/arm/configs/bcmrpi_defconfig  | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -615,9 +615,9 @@ CONFIG_PPS=m
- CONFIG_PPS_CLIENT_LDISC=m
- CONFIG_PPS_CLIENT_GPIO=m
- CONFIG_PINCTRL_MCP23S08=m
--CONFIG_GPIO_SYSFS=y
- CONFIG_GPIO_BCM_EXP=y
- CONFIG_GPIO_BCM_VIRT=y
-+CONFIG_GPIO_MOCKUP=m
- CONFIG_GPIO_PCF857X=m
- CONFIG_GPIO_ARIZONA=m
- CONFIG_GPIO_STMPE=y
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -610,7 +610,7 @@ CONFIG_PPS=m
- CONFIG_PPS_CLIENT_LDISC=m
- CONFIG_PPS_CLIENT_GPIO=m
- CONFIG_PINCTRL_MCP23S08=m
--CONFIG_GPIO_SYSFS=y
-+CONFIG_GPIO_MOCKUP=m
- CONFIG_GPIO_PCF857X=m
- CONFIG_GPIO_ARIZONA=m
- CONFIG_GPIO_STMPE=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0239-overlays-Add-upstream-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0239-overlays-Add-upstream-overlay.patch
deleted file mode 100644
index 0488fab6d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0239-overlays-Add-upstream-overlay.patch
+++ /dev/null
@@ -1,210 +0,0 @@
-From 1612baf8148e9180f28d7afc93df3ec3cd3e5ce0 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sat, 3 Mar 2018 14:18:03 +0000
-Subject: [PATCH 239/454] overlays: Add 'upstream' overlay
-
-The 'upstream' overlay makes the necessary changes for a downstream
-.dtb to be used with an upstream kernel. It is currently made up from
-three other overlays - vc4-kms-v3d, dwc2 and upstream-aux-interrupt.
-The VPU firmware will soon be made to automatically load this overlay
-when an upstream kernel is detected (using the trailer supplied by the
-mkknlimg script).
-
-See: https://github.com/raspberrypi/linux/pull/2393
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |   1 +
- arch/arm/boot/dts/overlays/README             |  10 +-
- .../boot/dts/overlays/upstream-overlay.dts    | 154 ++++++++++++++++++
- 3 files changed, 164 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/overlays/upstream-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -123,6 +123,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	tinylcd35.dtbo \
- 	uart0.dtbo \
- 	uart1.dtbo \
-+	upstream.dtbo \
- 	upstream-aux-interrupt.dtbo \
- 	vc4-fkms-v3d.dtbo \
- 	vc4-kms-v3d.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1731,9 +1731,17 @@ Params: txd1_pin                GPIO pin
-         rxd1_pin                GPIO pin for RXD1 (15, 33 or 41 - default 15)
- 
- 
-+Name:   upstream
-+Info:   Allow usage of downstream .dtb with upstream kernel. Comprises
-+        vc4-kms-v3d, dwc2 and upstream-aux-interrupt overlays.
-+Load:   dtoverlay=upstream
-+Params: <None>
-+
-+
- Name:   upstream-aux-interrupt
- Info:   Allow usage of downstream .dtb with upstream kernel by binding AUX
--        devices directly to the shared AUX interrupt line.
-+        devices directly to the shared AUX interrupt line. One of the parts
-+        of the 'upstream' overlay
- Load:   dtoverlay=upstream-aux-interrupt
- Params: <None>
- 
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/upstream-overlay.dts
-@@ -0,0 +1,154 @@
-+// redo: ovmerge -c vc4-kms-v3d-overlay.dts,cma-96 dwc2-overlay.dts,dr_mode=otg upstream-aux-interrupt-overlay.dts,
-+
-+/dts-v1/;
-+/plugin/;
-+
-+#include <dt-bindings/clock/bcm2835.h>
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+	fragment@0 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=256M";
-+		};
-+	};
-+	fragment@1 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=192M";
-+		};
-+	};
-+	fragment@2 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=128M";
-+		};
-+	};
-+	fragment@3 {
-+		target-path = "/chosen";
-+		__overlay__ {
-+			bootargs = "cma=96M";
-+		};
-+	};
-+	fragment@4 {
-+		target-path = "/chosen";
-+		__dormant__ {
-+			bootargs = "cma=64M";
-+		};
-+	};
-+	fragment@5 {
-+		target = <&i2c2>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+	fragment@6 {
-+		target = <&fb>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+	fragment@7 {
-+		target = <&pixelvalve0>;
-+		__overlay__ {
-+			interrupts = <2 13>;
-+			status = "okay";
-+		};
-+	};
-+	fragment@8 {
-+		target = <&pixelvalve1>;
-+		__overlay__ {
-+			interrupts = <2 14>;
-+			status = "okay";
-+		};
-+	};
-+	fragment@9 {
-+		target = <&pixelvalve2>;
-+		__overlay__ {
-+			interrupts = <2 10>;
-+			status = "okay";
-+		};
-+	};
-+	fragment@10 {
-+		target = <&hvs>;
-+		__overlay__ {
-+			interrupts = <2 1>;
-+			status = "okay";
-+		};
-+	};
-+	fragment@11 {
-+		target = <&hdmi>;
-+		__overlay__ {
-+			interrupts = <2 8>, <2 9>;
-+			status = "okay";
-+		};
-+	};
-+	fragment@12 {
-+		target = <&v3d>;
-+		__overlay__ {
-+			interrupts = <1 10>;
-+			status = "okay";
-+		};
-+	};
-+	fragment@13 {
-+		target = <&vc4>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+	fragment@14 {
-+		target-path = "/soc/dma";
-+		__overlay__ {
-+			brcm,dma-channel-mask = <0x7f35>;
-+		};
-+	};
-+	fragment@15 {
-+		target = <&clocks>;
-+		__overlay__ {
-+			claim-clocks = <BCM2835_PLLD_DSI0 BCM2835_PLLD_DSI1 BCM2835_PLLH_AUX BCM2835_PLLH_PIX>;
-+		};
-+	};
-+	fragment@16 {
-+		target = <&vec>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+	fragment@17 {
-+		target = <&usb>;
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		dwc2_usb: __overlay__ {
-+			compatible = "brcm,bcm2835-usb";
-+			reg = <0x7e980000 0x10000>;
-+			interrupts = <1 9>;
-+			dr_mode = "otg";
-+			g-np-tx-fifo-size = <32>;
-+			g-rx-fifo-size = <256>;
-+			g-tx-fifo-size = <512 512 512 512 512 768>;
-+			status = "okay";
-+		};
-+	};
-+	fragment@18 {
-+		target = <&uart1>;
-+		__overlay__ {
-+			interrupt-parent = <&intc>;
-+			interrupts = <0x1 0x1d>;
-+		};
-+	};
-+	fragment@19 {
-+		target = <&spi1>;
-+		__overlay__ {
-+			interrupt-parent = <&intc>;
-+			interrupts = <0x1 0x1d>;
-+		};
-+	};
-+	fragment@20 {
-+		target = <&spi2>;
-+		__overlay__ {
-+			interrupt-parent = <&intc>;
-+			interrupts = <0x1 0x1d>;
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0240-audioinjector-octo-Add-continuous-clock-feature.patch b/target/linux/brcm2708/patches-4.14/950-0240-audioinjector-octo-Add-continuous-clock-feature.patch
deleted file mode 100644
index 1eb5fd4c4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0240-audioinjector-octo-Add-continuous-clock-feature.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From f7045758fffa176ea68730ea855415e619bf516d Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sat, 3 Mar 2018 16:25:19 +0000
-Subject: [PATCH 240/454] audioinjector-octo: Add continuous clock feature
-
-By user request, add a switch to prevent the clocks being stopped when
-the stream is paused, stopped or shutdown. Provide access to the switch
-by adding a 'non-stop-clocks' parameter to the audioinjector-addons
-overlay.
-
-See: https://github.com/raspberrypi/linux/issues/2409
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README             |  5 +++--
- .../overlays/audioinjector-addons-overlay.dts |  6 +++++-
- sound/soc/bcm/audioinjector-octo-soundcard.c  | 19 +++++++++++--------
- 3 files changed, 19 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -357,8 +357,9 @@ Params: interrupt               GPIO use
- 
- Name:   audioinjector-addons
- Info:   Configures the audioinjector.net audio add on soundcards
--Load:   dtoverlay=audioinjector-addons
--Params: <None>
-+Load:   dtoverlay=audioinjector-addons,<param>=<val>
-+Params: non-stop-clocks         Keeps the clocks running even when the stream
-+                                is paused or stopped (default off)
- 
- 
- Name:   audioinjector-wm8731-audio
---- a/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts
-@@ -42,7 +42,7 @@
- 
- 	fragment@2 {
- 		target = <&sound>;
--		__overlay__ {
-+		snd: __overlay__ {
- 			compatible = "ai,audioinjector-octo-soundcard";
- 			mult-gpios = <&gpio 27 0>, <&gpio 22 0>, <&gpio 23 0>,
- 				     <&gpio 24 0>;
-@@ -52,4 +52,8 @@
- 			status = "okay";
- 		};
- 	};
-+
-+	__overrides__ {
-+		non-stop-clocks = <&snd>, "non-stop-clocks?";
-+	};
- };
---- a/sound/soc/bcm/audioinjector-octo-soundcard.c
-+++ b/sound/soc/bcm/audioinjector-octo-soundcard.c
-@@ -29,6 +29,7 @@
- static struct gpio_descs *mult_gpios;
- static struct gpio_desc *codec_rst_gpio;
- static unsigned int audioinjector_octo_rate;
-+static bool non_stop_clocks;
- 
- static const unsigned int audioinjector_octo_rates[] = {
- 	96000, 48000, 32000, 24000, 16000, 8000, 88200, 44100, 29400, 22050, 14700,
-@@ -133,12 +134,16 @@ static int audioinjector_octo_hw_params(
- static int audioinjector_octo_trigger(struct snd_pcm_substream *substream,
- 								int cmd){
- 	int mult[4];
--	mult[0] = 0;
--	mult[1] = 0;
--	mult[2] = 0;
--	mult[3] = 0;
-+
-+	memset(mult, 0, sizeof(mult));
- 
- 	switch (cmd) {
-+	case SNDRV_PCM_TRIGGER_STOP:
-+	case SNDRV_PCM_TRIGGER_SUSPEND:
-+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+		if (!non_stop_clocks)
-+			break;
-+		/* Drop through... */
- 	case SNDRV_PCM_TRIGGER_START:
- 	case SNDRV_PCM_TRIGGER_RESUME:
- 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-@@ -177,10 +182,6 @@ static int audioinjector_octo_trigger(st
- 			return -EINVAL;
- 		}
- 		break;
--	case SNDRV_PCM_TRIGGER_STOP:
--	case SNDRV_PCM_TRIGGER_SUSPEND:
--	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
--		break;
- 	default:
- 		return -EINVAL;
- 	}
-@@ -276,6 +277,8 @@ static int audioinjector_octo_probe(stru
- 		if (IS_ERR(codec_rst_gpio))
- 			return PTR_ERR(codec_rst_gpio);
- 
-+		non_stop_clocks = of_property_read_bool(pdev->dev.of_node, "non-stop-clocks");
-+
- 		if (codec_rst_gpio)
- 			gpiod_set_value(codec_rst_gpio, 1);
- 		msleep(500);
diff --git a/target/linux/brcm2708/patches-4.14/950-0241-sound-bcm-Fix-memset-dereference-warning.patch b/target/linux/brcm2708/patches-4.14/950-0241-sound-bcm-Fix-memset-dereference-warning.patch
deleted file mode 100644
index ad575a558..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0241-sound-bcm-Fix-memset-dereference-warning.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From e6566749479de99f0d0c85bd894d9f6280b081b0 Mon Sep 17 00:00:00 2001
-From: Nathan Chancellor <natechancellor@gmail.com>
-Date: Sun, 4 Mar 2018 17:20:25 -0700
-Subject: [PATCH 241/454] sound: bcm: Fix memset dereference warning
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This warning appears with GCC 6.4.0 from toolchains.bootlin.com:
-
-../sound/soc/bcm/allo-piano-dac-plus.c: In function ‘snd_allo_piano_dac_init’:
-../sound/soc/bcm/allo-piano-dac-plus.c:711:30: warning: argument to ‘sizeof’ in ‘memset’ call is the same expression as the destination; did you mean to dereference it? [-Wsizeof-pointer-memaccess]
-  memset(glb_ptr, 0x00, sizeof(glb_ptr));
-                              ^
-
-Suggested-by: Phil Elwell <phil@raspberrypi.org>
-Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
----
- sound/soc/bcm/allo-piano-dac-plus.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/sound/soc/bcm/allo-piano-dac-plus.c
-+++ b/sound/soc/bcm/allo-piano-dac-plus.c
-@@ -704,11 +704,10 @@ static int snd_allo_piano_dac_init(struc
- 	struct snd_soc_card *card = rtd->card;
- 	struct glb_pool *glb_ptr;
- 
--	glb_ptr = kmalloc(sizeof(struct glb_pool), GFP_KERNEL);
-+	glb_ptr = kzalloc(sizeof(struct glb_pool), GFP_KERNEL);
- 	if (!glb_ptr)
- 		return -ENOMEM;
- 
--	memset(glb_ptr, 0x00, sizeof(glb_ptr));
- 	card->drvdata = glb_ptr;
- 	glb_ptr->dual_mode = 2;
- 	glb_ptr->set_mode = 0;
diff --git a/target/linux/brcm2708/patches-4.14/950-0242-staging-vchiq_arm-Remove-unused-variable.patch b/target/linux/brcm2708/patches-4.14/950-0242-staging-vchiq_arm-Remove-unused-variable.patch
deleted file mode 100644
index 891321caf..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0242-staging-vchiq_arm-Remove-unused-variable.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 9819e63ebfc46b01244df58fc0afd3285217cc7b Mon Sep 17 00:00:00 2001
-From: Nathan Chancellor <natechancellor@gmail.com>
-Date: Sat, 3 Mar 2018 23:34:50 -0700
-Subject: [PATCH 242/454] staging: vchiq_arm: Remove unused variable
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This warning appears with GCC 6.4.0 from toolchains.bootlin.com:
-
-../drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c: In function ‘vchiq_open’:
-../drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c:1735:7: warning: unused variable ‘ret’ [-Wunused-variable]
-   int ret;
-       ^~~
-
-This variable's usage was removed by commit 3c980263c592 ("staging:
-vchiq_arm: Make debugfs failure non-fatal"), making it useless.
-
-Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
----
- drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
-@@ -1737,7 +1737,6 @@ vchiq_open(struct inode *inode, struct f
- 	vchiq_log_info(vchiq_arm_log_level, "vchiq_open");
- 	switch (dev) {
- 	case VCHIQ_MINOR: {
--		int ret;
- 		VCHIQ_STATE_T *state = vchiq_get_state();
- 		VCHIQ_INSTANCE_T instance;
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0243-usb-dwb_otg-Fix-unreachable-switch-statement-warning.patch b/target/linux/brcm2708/patches-4.14/950-0243-usb-dwb_otg-Fix-unreachable-switch-statement-warning.patch
deleted file mode 100644
index 490c80b3e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0243-usb-dwb_otg-Fix-unreachable-switch-statement-warning.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 570d1abb82d480fa68b12bf787ea8204bdcdbacc Mon Sep 17 00:00:00 2001
-From: Nathan Chancellor <natechancellor@gmail.com>
-Date: Sun, 4 Mar 2018 20:09:26 -0700
-Subject: [PATCH 243/454] usb: dwb_otg: Fix unreachable switch statement
- warning
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This warning appears with GCC 7.3.0 from toolchains.bootlin.com:
-
-../drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c: In function ‘fiq_fsm_update_hs_isoc’:
-../drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c:595:61: warning: statement will never be executed [-Wswitch-unreachable]
-   st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
-                                            ~~~~~~~~~~~~~~~~~^~~~
-
-Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
----
- drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-@@ -591,8 +591,8 @@ static int notrace noinline fiq_fsm_upda
- 		}
- 
- 	} else {
--		switch (st->hcchar_copy.b.multicnt) {
- 		st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
-+		switch (st->hcchar_copy.b.multicnt) {
- 		case 1:
- 			st->hctsiz_copy.b.pid = DWC_PID_DATA0;
- 			break;
diff --git a/target/linux/brcm2708/patches-4.14/950-0244-ARM-dts-Add-model-specific-compatible-strings.patch b/target/linux/brcm2708/patches-4.14/950-0244-ARM-dts-Add-model-specific-compatible-strings.patch
deleted file mode 100644
index e92c4494f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0244-ARM-dts-Add-model-specific-compatible-strings.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 0c6baed942a4eab2d4af3625e58db03998dece60 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 7 Mar 2018 08:21:29 +0000
-Subject: [PATCH 244/454] ARM: dts: Add model-specific compatible strings
-
-The upstream Pi DTs are model-specific, with both the model and
-compatible strings identifying the model. Downstream groups the
-closely-related models, with only the chip name in the compatible
-strings and a model string patched by the firmware.
-
-Bring the downstream model-specific DTs closer to upstream by
-adding model-specific compatible strings.
-
-See: https://github.com/raspberrypi/firmware/issues/943
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm2708-rpi-0-w.dts | 1 +
- arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 1 +
- arch/arm/boot/dts/bcm2710-rpi-3-b.dts | 1 +
- 3 files changed, 3 insertions(+)
-
---- a/arch/arm/boot/dts/bcm2708-rpi-0-w.dts
-+++ b/arch/arm/boot/dts/bcm2708-rpi-0-w.dts
-@@ -3,6 +3,7 @@
- #include "bcm2708.dtsi"
- 
- / {
-+	compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
- 	model = "Raspberry Pi Zero W";
- 
- 	chosen {
---- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
-+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
-@@ -4,6 +4,7 @@
- #include "bcm283x-rpi-smsc9514.dtsi"
- 
- / {
-+	compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
- 	model = "Raspberry Pi 2 Model B";
- };
- 
---- a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-@@ -8,6 +8,7 @@
- #include "bcm283x-rpi-smsc9514.dtsi"
- 
- / {
-+	compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
- 	model = "Raspberry Pi 3 Model B";
- 
- 	chosen {
diff --git a/target/linux/brcm2708/patches-4.14/950-0245-irqchip-bcm2836-Move-SMP-startup-code-to-arch-arm-v2.patch b/target/linux/brcm2708/patches-4.14/950-0245-irqchip-bcm2836-Move-SMP-startup-code-to-arch-arm-v2.patch
deleted file mode 100644
index 5fc584f1b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0245-irqchip-bcm2836-Move-SMP-startup-code-to-arch-arm-v2.patch
+++ /dev/null
@@ -1,314 +0,0 @@
-From 827d93b06aefb4fd03f9a6a0c3774a14fd5bd291 Mon Sep 17 00:00:00 2001
-From: Stefan Wahren <stefan.wahren@i2se.com>
-Date: Sun, 6 Aug 2017 17:52:02 +0200
-Subject: [PATCH 245/454] irqchip: bcm2836: Move SMP startup code to arch/arm
- (v2)
-
-commit 88bbe85dcd37aa2662c1a83962c15009fc12503e upstream.
-
-In order to easily provide SMP for BCM2837 on 32-bit and 64-bit
-the SMP startup code was placed in irq-bcm2836. That's not the
-right approach. So move this code where it belongs.
-
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
-Fixes: 41f4988cc287 ("irqchip/bcm2836: Add SMP support for the 2836")
-Tested-by: Eric Anholt <eric@anholt.net>
-Acked-by: Marc Zyngier <marc.zyngier@arm.com>
----
- arch/arm/mach-bcm/Makefile          |  5 ++
- arch/arm/mach-bcm/board_bcm2835.c   |  5 +-
- arch/arm/mach-bcm/platsmp.c         | 35 ++++++++++++
- arch/arm/mach-bcm/platsmp.h         | 10 ++++
- drivers/irqchip/irq-bcm2836.c       | 82 +----------------------------
- include/linux/irqchip/irq-bcm2836.h | 70 ++++++++++++++++++++++++
- 6 files changed, 126 insertions(+), 81 deletions(-)
- create mode 100644 arch/arm/mach-bcm/platsmp.h
- create mode 100644 include/linux/irqchip/irq-bcm2836.h
-
---- a/arch/arm/mach-bcm/Makefile
-+++ b/arch/arm/mach-bcm/Makefile
-@@ -43,6 +43,11 @@ endif
- 
- # BCM2835
- obj-$(CONFIG_ARCH_BCM2835)	+= board_bcm2835.o
-+ifeq ($(CONFIG_ARCH_BCM2835),y)
-+ifeq ($(CONFIG_ARM),y)
-+obj-$(CONFIG_SMP)		+= platsmp.o
-+endif
-+endif
- 
- # BCM5301X
- obj-$(CONFIG_ARCH_BCM_5301X)	+= bcm_5301x.o
---- a/arch/arm/mach-bcm/board_bcm2835.c
-+++ b/arch/arm/mach-bcm/board_bcm2835.c
-@@ -21,6 +21,7 @@
- #include <asm/mach/arch.h>
- #include <asm/mach/map.h>
- 
-+#include "platsmp.h"
- #include <linux/dma-mapping.h>
- 
- static void __init bcm2835_init(void)
-@@ -49,6 +50,7 @@ static const char * const bcm2835_compat
- #endif
- #ifdef CONFIG_ARCH_MULTI_V7
- 	"brcm,bcm2836",
-+	"brcm,bcm2837",
- #endif
- 	NULL
- };
-@@ -56,5 +58,6 @@ static const char * const bcm2835_compat
- DT_MACHINE_START(BCM2835, "BCM2835")
- 	.init_machine = bcm2835_init,
- 	.init_early = bcm2835_init_early,
--	.dt_compat = bcm2835_compat
-+	.dt_compat = bcm2835_compat,
-+	.smp = smp_ops(bcm2836_smp_ops),
- MACHINE_END
---- a/arch/arm/mach-bcm/platsmp.c
-+++ b/arch/arm/mach-bcm/platsmp.c
-@@ -17,6 +17,7 @@
- #include <linux/errno.h>
- #include <linux/init.h>
- #include <linux/io.h>
-+#include <linux/irqchip/irq-bcm2836.h>
- #include <linux/jiffies.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-@@ -287,6 +288,35 @@ out:
- 	return ret;
- }
- 
-+static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle)
-+{
-+	void __iomem *intc_base;
-+	struct device_node *dn;
-+	char *name;
-+
-+	name = "brcm,bcm2836-l1-intc";
-+	dn = of_find_compatible_node(NULL, NULL, name);
-+	if (!dn) {
-+		pr_err("unable to find intc node\n");
-+		return -ENODEV;
-+	}
-+
-+	intc_base = of_iomap(dn, 0);
-+	of_node_put(dn);
-+
-+	if (!intc_base) {
-+		pr_err("unable to remap intc base register\n");
-+		return -ENOMEM;
-+	}
-+
-+	writel(virt_to_phys(secondary_startup),
-+	       intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
-+
-+	iounmap(intc_base);
-+
-+	return 0;
-+}
-+
- static const struct smp_operations kona_smp_ops __initconst = {
- 	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
- 	.smp_boot_secondary	= kona_boot_secondary,
-@@ -305,3 +335,8 @@ static const struct smp_operations nsp_s
- 	.smp_boot_secondary	= nsp_boot_secondary,
- };
- CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
-+
-+const struct smp_operations bcm2836_smp_ops __initconst = {
-+	.smp_boot_secondary	= bcm2836_boot_secondary,
-+};
-+CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops);
---- /dev/null
-+++ b/arch/arm/mach-bcm/platsmp.h
-@@ -0,0 +1,10 @@
-+/*
-+ * Copyright (C) 2017 Stefan Wahren <stefan.wahren@i2se.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation version 2.
-+ *
-+ */
-+
-+extern const struct smp_operations bcm2836_smp_ops;
---- a/drivers/irqchip/irq-bcm2836.c
-+++ b/drivers/irqchip/irq-bcm2836.c
-@@ -19,62 +19,9 @@
- #include <linux/of_irq.h>
- #include <linux/irqchip.h>
- #include <linux/irqdomain.h>
--#include <asm/exception.h>
--
--#define LOCAL_CONTROL			0x000
--#define LOCAL_PRESCALER			0x008
-+#include <linux/irqchip/irq-bcm2836.h>
- 
--/*
-- * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
-- * next 2 bits identify the CPU that the GPU FIQ goes to.
-- */
--#define LOCAL_GPU_ROUTING		0x00c
--/* When setting bits 0-3, enables PMU interrupts on that CPU. */
--#define LOCAL_PM_ROUTING_SET		0x010
--/* When setting bits 0-3, disables PMU interrupts on that CPU. */
--#define LOCAL_PM_ROUTING_CLR		0x014
--/*
-- * The low 4 bits of this are the CPU's timer IRQ enables, and the
-- * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
-- * bits).
-- */
--#define LOCAL_TIMER_INT_CONTROL0	0x040
--/*
-- * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
-- * the next 4 bits are the CPU's per-mailbox FIQ enables (which
-- * override the IRQ bits).
-- */
--#define LOCAL_MAILBOX_INT_CONTROL0	0x050
--/*
-- * The CPU's interrupt status register.  Bits are defined by the the
-- * LOCAL_IRQ_* bits below.
-- */
--#define LOCAL_IRQ_PENDING0		0x060
--/* Same status bits as above, but for FIQ. */
--#define LOCAL_FIQ_PENDING0		0x070
--/*
-- * Mailbox write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
-- * these bits are organized by mailbox number and then CPU number.  We
-- * use mailbox 0 for IPIs.  The mailbox's interrupt is raised while
-- * any bit is set.
-- */
--#define LOCAL_MAILBOX0_SET0		0x080
--#define LOCAL_MAILBOX3_SET0		0x08c
--/* Mailbox write-to-clear bits. */
--#define LOCAL_MAILBOX0_CLR0		0x0c0
--#define LOCAL_MAILBOX3_CLR0		0x0cc
--
--#define LOCAL_IRQ_CNTPSIRQ	0
--#define LOCAL_IRQ_CNTPNSIRQ	1
--#define LOCAL_IRQ_CNTHPIRQ	2
--#define LOCAL_IRQ_CNTVIRQ	3
--#define LOCAL_IRQ_MAILBOX0	4
--#define LOCAL_IRQ_MAILBOX1	5
--#define LOCAL_IRQ_MAILBOX2	6
--#define LOCAL_IRQ_MAILBOX3	7
--#define LOCAL_IRQ_GPU_FAST	8
--#define LOCAL_IRQ_PMU_FAST	9
--#define LAST_IRQ		LOCAL_IRQ_PMU_FAST
-+#include <asm/exception.h>
- 
- struct bcm2836_arm_irqchip_intc {
- 	struct irq_domain *domain;
-@@ -240,27 +187,6 @@ static int bcm2836_cpu_dying(unsigned in
- 					     cpu);
- 	return 0;
- }
--
--#ifdef CONFIG_ARM
--static int __init bcm2836_smp_boot_secondary(unsigned int cpu,
--					     struct task_struct *idle)
--{
--	unsigned long secondary_startup_phys =
--		(unsigned long)virt_to_phys((void *)secondary_startup);
--
--	writel(secondary_startup_phys,
--	       intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
--
--	dsb(sy); /* Ensure write has completed before waking the other CPUs */
--	sev();
--
--	return 0;
--}
--
--static const struct smp_operations bcm2836_smp_ops __initconst = {
--	.smp_boot_secondary	= bcm2836_smp_boot_secondary,
--};
--#endif
- #endif
- 
- static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
-@@ -277,10 +203,6 @@ bcm2836_arm_irqchip_smp_init(void)
- 			  bcm2836_cpu_dying);
- 
- 	set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
--
--#ifdef CONFIG_ARM
--	smp_set_ops(&bcm2836_smp_ops);
--#endif
- #endif
- }
- 
---- /dev/null
-+++ b/include/linux/irqchip/irq-bcm2836.h
-@@ -0,0 +1,70 @@
-+/*
-+ * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
-+ *
-+ * Copyright 2015 Broadcom
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#define LOCAL_CONTROL			0x000
-+#define LOCAL_PRESCALER			0x008
-+
-+/*
-+ * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
-+ * next 2 bits identify the CPU that the GPU FIQ goes to.
-+ */
-+#define LOCAL_GPU_ROUTING		0x00c
-+/* When setting bits 0-3, enables PMU interrupts on that CPU. */
-+#define LOCAL_PM_ROUTING_SET		0x010
-+/* When setting bits 0-3, disables PMU interrupts on that CPU. */
-+#define LOCAL_PM_ROUTING_CLR		0x014
-+/*
-+ * The low 4 bits of this are the CPU's timer IRQ enables, and the
-+ * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
-+ * bits).
-+ */
-+#define LOCAL_TIMER_INT_CONTROL0	0x040
-+/*
-+ * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
-+ * the next 4 bits are the CPU's per-mailbox FIQ enables (which
-+ * override the IRQ bits).
-+ */
-+#define LOCAL_MAILBOX_INT_CONTROL0	0x050
-+/*
-+ * The CPU's interrupt status register.  Bits are defined by the the
-+ * LOCAL_IRQ_* bits below.
-+ */
-+#define LOCAL_IRQ_PENDING0		0x060
-+/* Same status bits as above, but for FIQ. */
-+#define LOCAL_FIQ_PENDING0		0x070
-+/*
-+ * Mailbox write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
-+ * these bits are organized by mailbox number and then CPU number.  We
-+ * use mailbox 0 for IPIs.  The mailbox's interrupt is raised while
-+ * any bit is set.
-+ */
-+#define LOCAL_MAILBOX0_SET0		0x080
-+#define LOCAL_MAILBOX3_SET0		0x08c
-+/* Mailbox write-to-clear bits. */
-+#define LOCAL_MAILBOX0_CLR0		0x0c0
-+#define LOCAL_MAILBOX3_CLR0		0x0cc
-+
-+#define LOCAL_IRQ_CNTPSIRQ	0
-+#define LOCAL_IRQ_CNTPNSIRQ	1
-+#define LOCAL_IRQ_CNTHPIRQ	2
-+#define LOCAL_IRQ_CNTVIRQ	3
-+#define LOCAL_IRQ_MAILBOX0	4
-+#define LOCAL_IRQ_MAILBOX1	5
-+#define LOCAL_IRQ_MAILBOX2	6
-+#define LOCAL_IRQ_MAILBOX3	7
-+#define LOCAL_IRQ_GPU_FAST	8
-+#define LOCAL_IRQ_PMU_FAST	9
-+#define LAST_IRQ		LOCAL_IRQ_PMU_FAST
diff --git a/target/linux/brcm2708/patches-4.14/950-0246-arm64-enable-thermal-enable-mmc-2425.patch b/target/linux/brcm2708/patches-4.14/950-0246-arm64-enable-thermal-enable-mmc-2425.patch
deleted file mode 100644
index 53b71b94f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0246-arm64-enable-thermal-enable-mmc-2425.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 47d9d3e72a1ce13f26c65ad87f5fcb8e5158566c Mon Sep 17 00:00:00 2001
-From: Piraty <Piraty@users.noreply.github.com>
-Date: Mon, 12 Mar 2018 17:07:45 +0100
-Subject: [PATCH 246/454] arm64: enable thermal / enable mmc (#2425)
-
----
- arch/arm64/configs/bcmrpi3_defconfig | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -640,7 +640,7 @@ CONFIG_SENSORS_SHT21=m
- CONFIG_SENSORS_SHTC1=m
- CONFIG_SENSORS_INA2XX=m
- CONFIG_THERMAL=y
--CONFIG_THERMAL_BCM2835=y
-+CONFIG_BCM2835_THERMAL=y
- CONFIG_WATCHDOG=y
- CONFIG_BCM2835_WDT=y
- CONFIG_UCB1400_CORE=m
-@@ -1285,3 +1285,5 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=m
- CONFIG_ARM64_CRYPTO=y
- CONFIG_CRC_ITU_T=y
- CONFIG_LIBCRC32C=y
-+CONFIG_MMC_BCM2835_MMC=y
-+CONFIG_MMC_SDHCI_IPROC=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0247-added-capture_clear-option-to-pps-gpio-via-dtoverlay.patch b/target/linux/brcm2708/patches-4.14/950-0247-added-capture_clear-option-to-pps-gpio-via-dtoverlay.patch
deleted file mode 100644
index 545dc555a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0247-added-capture_clear-option-to-pps-gpio-via-dtoverlay.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 61ad2796b48891e5a3e52d290cb51a44259b5799 Mon Sep 17 00:00:00 2001
-From: hdoverobinson <hdoverobinson@gmail.com>
-Date: Tue, 13 Mar 2018 06:58:39 -0400
-Subject: [PATCH 247/454] added capture_clear option to pps-gpio via dtoverlay
- (#2433)
-
----
- arch/arm/boot/dts/overlays/README               | 5 ++++-
- arch/arm/boot/dts/overlays/pps-gpio-overlay.dts | 1 +
- drivers/pps/clients/pps-gpio.c                  | 3 +++
- 3 files changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1287,7 +1287,10 @@ Info:   Configures the pps-gpio (pulse-p
- Load:   dtoverlay=pps-gpio,<param>=<val>
- Params: gpiopin                 Input GPIO (default "18")
-         assert_falling_edge     When present, assert is indicated by a falling
--                                edge, rather than by a rising edge
-+                                edge, rather than by a rising edge (default
-+                                off)
-+        capture_clear           Generate clear events on the trailing edge
-+                                (default off)
- 
- 
- Name:   pwm
---- a/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts
-@@ -33,5 +33,6 @@
- 			  <&pps_pins>,"brcm,pins:0",
- 			  <&pps_pins>,"reg:0";
- 		assert_falling_edge = <&pps>,"assert-falling-edge?";
-+		capture_clear = <&pps>,"capture-clear?";
- 	};
- };
---- a/drivers/pps/clients/pps-gpio.c
-+++ b/drivers/pps/clients/pps-gpio.c
-@@ -119,6 +119,9 @@ static int pps_gpio_probe(struct platfor
- 
- 		if (of_get_property(np, "assert-falling-edge", NULL))
- 			data->assert_falling_edge = true;
-+
-+                if (of_get_property(np, "capture-clear", NULL))
-+                        data->capture_clear = true;
- 	}
- 
- 	/* GPIO setup */
diff --git a/target/linux/brcm2708/patches-4.14/950-0248-bcm2710-rpi-3-b.dts-Remove-duplicate-memreserve.patch b/target/linux/brcm2708/patches-4.14/950-0248-bcm2710-rpi-3-b.dts-Remove-duplicate-memreserve.patch
deleted file mode 100644
index d38a07a9f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0248-bcm2710-rpi-3-b.dts-Remove-duplicate-memreserve.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From fef741eacc51dc666098dfeb48727be6d54fb706 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 14 Mar 2018 11:31:04 +0000
-Subject: [PATCH 248/454] bcm2710-rpi-3-b.dts: Remove duplicate memreserve
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm2710-rpi-3-b.dts | 4 ----
- 1 file changed, 4 deletions(-)
-
---- a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-@@ -1,9 +1,5 @@
- /dts-v1/;
- 
--#ifdef RPI364
--/memreserve/ 0x00000000 0x00001000;
--#endif
--
- #include "bcm2710.dtsi"
- #include "bcm283x-rpi-smsc9514.dtsi"
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0249-config-Set-CONFIG_USB_LAN78XX-y.patch b/target/linux/brcm2708/patches-4.14/950-0249-config-Set-CONFIG_USB_LAN78XX-y.patch
deleted file mode 100644
index f3a968939..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0249-config-Set-CONFIG_USB_LAN78XX-y.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From ce292d4dca0c280360182bb33e982ba8d57fe0bf Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 8 Feb 2018 15:08:57 +0000
-Subject: [PATCH 249/454] config: Set CONFIG_USB_LAN78XX=y
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -461,7 +461,7 @@ CONFIG_USB_KAWETH=m
- CONFIG_USB_PEGASUS=m
- CONFIG_USB_RTL8150=m
- CONFIG_USB_RTL8152=m
--CONFIG_USB_LAN78XX=m
-+CONFIG_USB_LAN78XX=y
- CONFIG_USB_USBNET=y
- CONFIG_USB_NET_AX8817X=m
- CONFIG_USB_NET_AX88179_178A=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0250-BCM270X_DT-Add-Pi-3-dts-files.patch b/target/linux/brcm2708/patches-4.14/950-0250-BCM270X_DT-Add-Pi-3-dts-files.patch
deleted file mode 100644
index 55727d529..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0250-BCM270X_DT-Add-Pi-3-dts-files.patch
+++ /dev/null
@@ -1,274 +0,0 @@
-From 09bd29626a880f4bbcd4d3b3ebbdbaf170e0b27c Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 21 Jul 2017 11:33:25 +0100
-Subject: [PATCH 250/454] BCM270X_DT: Add Pi 3+ dts files
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/Makefile                 |   1 +
- arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts | 183 +++++++++++++++++++++
- arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi |  36 ++++
- arch/arm/boot/dts/overlays/README          |   8 +
- 4 files changed, 228 insertions(+)
- create mode 100644 arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts
- create mode 100644 arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
- 	bcm2708-rpi-0-w.dtb \
- 	bcm2709-rpi-2-b.dtb \
- 	bcm2710-rpi-3-b.dtb \
-+	bcm2710-rpi-3-b-plus.dtb \
- 	bcm2710-rpi-cm3.dtb
- 
- dtb-$(CONFIG_ARCH_ALPINE) += \
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts
-@@ -0,0 +1,183 @@
-+/dts-v1/;
-+
-+#include "bcm2710.dtsi"
-+#include "bcm283x-rpi-lan7515.dtsi"
-+
-+/ {
-+	compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
-+	model = "Raspberry Pi 3 Model B+";
-+
-+	chosen {
-+		bootargs = "8250.nr_uarts=1";
-+	};
-+
-+	aliases {
-+		serial0 = &uart1;
-+		serial1 = &uart0;
-+	};
-+};
-+
-+&gpio {
-+	spi0_pins: spi0_pins {
-+		brcm,pins = <9 10 11>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	spi0_cs_pins: spi0_cs_pins {
-+		brcm,pins = <8 7>;
-+		brcm,function = <1>; /* output */
-+	};
-+
-+	i2c0_pins: i2c0 {
-+		brcm,pins = <0 1>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2c1_pins: i2c1 {
-+		brcm,pins = <2 3>;
-+		brcm,function = <4>;
-+	};
-+
-+	i2s_pins: i2s {
-+		brcm,pins = <18 19 20 21>;
-+		brcm,function = <4>; /* alt0 */
-+	};
-+
-+	sdio_pins: sdio_pins {
-+		brcm,pins =     <34 35 36 37 38 39>;
-+		brcm,function = <7>; // alt3 = SD1
-+		brcm,pull =     <0 2 2 2 2 2>;
-+	};
-+
-+	bt_pins: bt_pins {
-+		brcm,pins = <43>;
-+		brcm,function = <4>; /* alt0:GPCLK2 */
-+		brcm,pull = <0>;
-+	};
-+
-+	uart0_pins: uart0_pins {
-+		brcm,pins = <32 33>;
-+		brcm,function = <7>; /* alt3=UART0 */
-+		brcm,pull = <0 2>;
-+	};
-+
-+	uart1_pins: uart1_pins {
-+		brcm,pins;
-+		brcm,function;
-+		brcm,pull;
-+	};
-+
-+	audio_pins: audio_pins {
-+		brcm,pins = <40 41>;
-+		brcm,function = <4>;
-+	};
-+};
-+
-+&mmc {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&sdio_pins>;
-+	non-removable;
-+	bus-width = <4>;
-+	status = "okay";
-+	brcm,overclock-50 = <0>;
-+};
-+
-+&soc {
-+	expgpio: expgpio {
-+		compatible = "brcm,bcm2835-expgpio";
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		firmware = <&firmware>;
-+		status = "okay";
-+	};
-+};
-+
-+&uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart0_pins &bt_pins>;
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>;
-+	status = "okay";
-+};
-+
-+&spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
-+	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
-+
-+	spidev0: spidev@0{
-+		compatible = "spidev";
-+		reg = <0>;	/* CE0 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+
-+	spidev1: spidev@1{
-+		compatible = "spidev";
-+		reg = <1>;	/* CE1 */
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		spi-max-frequency = <125000000>;
-+	};
-+};
-+
-+&i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c0_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2c1_pins>;
-+	clock-frequency = <100000>;
-+};
-+
-+&i2c2 {
-+	clock-frequency = <100000>;
-+};
-+
-+&i2s {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&i2s_pins>;
-+};
-+
-+&leds {
-+	act_led: act {
-+		label = "led0";
-+		linux,default-trigger = "mmc0";
-+		gpios = <&gpio 29 0>;
-+	};
-+
-+	pwr_led: pwr {
-+		label = "led1";
-+		linux,default-trigger = "default-on";
-+		gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
-+	};
-+};
-+
-+&hdmi {
-+	hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>;
-+};
-+
-+&audio {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&audio_pins>;
-+};
-+
-+/ {
-+	__overrides__ {
-+		act_led_gpio = <&act_led>,"gpios:4";
-+		act_led_activelow = <&act_led>,"gpios:8";
-+		act_led_trigger = <&act_led>,"linux,default-trigger";
-+
-+		pwr_led_gpio = <&pwr_led>,"gpios:4";
-+		pwr_led_activelow = <&pwr_led>,"gpios:8";
-+		pwr_led_trigger = <&pwr_led>,"linux,default-trigger";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
-@@ -0,0 +1,36 @@
-+/ {
-+	aliases {
-+		ethernet0 = &ethernet;
-+	};
-+};
-+
-+&usb {
-+	usb1@1 {
-+		compatible = "usb424,2514";
-+		reg = <1>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		usb1_1@1 {
-+			compatible = "usb424,2514";
-+			reg = <1>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			ethernet: usbether@1 {
-+				compatible = "usb424,7800";
-+				reg = <1>;
-+				microchip,eee-enabled;
-+				microchip,tx-lpi-timer = <600>; /* non-aggressive*/
-+			};
-+		};
-+	};
-+};
-+
-+
-+/ {
-+	__overrides__ {
-+		eee = <&ethernet>,"microchip,eee-enabled?";
-+		tx_lpi_timer = <&ethernet>,"microchip,tx-lpi-timer:0";
-+	};
-+};
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -89,6 +89,10 @@ Params:
-         audio                   Set to "on" to enable the onboard ALSA audio
-                                 interface (default "off")
- 
-+        eee                     Enable Energy Efficient Ethernet support for
-+                                compatible devices (default "on"). See also
-+                                "tx_lpi_timer".
-+
-         i2c_arm                 Set to "on" to enable the ARM's i2c interface
-                                 (default "off")
- 
-@@ -125,6 +129,10 @@ Params:
- 
-         sd_debug                Enable debug output from SD driver (default off)
- 
-+        tx_lpi_timer            Set the delay in microseconds between going idle
-+                                and entering the low power state (default 600).
-+                                Requires EEE to be enabled - see "eee".
-+
-         uart0                   Set to "off" to disable uart0 (default "on")
- 
-         uart1                   Set to "on" or "off" to enable or disable uart1
diff --git a/target/linux/brcm2708/patches-4.14/950-0251-lan78xx-Read-initial-EEE-status-from-DT.patch b/target/linux/brcm2708/patches-4.14/950-0251-lan78xx-Read-initial-EEE-status-from-DT.patch
deleted file mode 100644
index 534ab6d92..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0251-lan78xx-Read-initial-EEE-status-from-DT.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 519f76313689c7e2f03da2e7c91e3c75e68c9034 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 9 Mar 2018 12:01:00 +0000
-Subject: [PATCH 251/454] lan78xx: Read initial EEE status from DT
-
-Add two new DT properties:
-* microchip,eee-enabled  - a boolean to enable EEE
-* microchip,tx-lpi-timer - time in microseconds to wait before entering
-                           low power state
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2510,6 +2510,22 @@ static int lan78xx_open(struct net_devic
- 
- 	netif_dbg(dev, ifup, dev->net, "phy initialised successfully");
- 
-+	if (of_property_read_bool(dev->udev->dev.of_node,
-+				  "microchip,eee-enabled")) {
-+		struct ethtool_eee edata;
-+		memset(&edata, 0, sizeof(edata));
-+		edata.cmd = ETHTOOL_SEEE;
-+		edata.advertised = ADVERTISED_1000baseT_Full |
-+				   ADVERTISED_100baseT_Full;
-+		edata.eee_enabled = true;
-+		edata.tx_lpi_enabled = true;
-+		if (of_property_read_u32(dev->udev->dev.of_node,
-+					 "microchip,tx-lpi-timer",
-+					 &edata.tx_lpi_timer))
-+			edata.tx_lpi_timer = 600; /* non-aggressive */
-+		(void)lan78xx_set_eee(net, &edata);
-+	}
-+
- 	/* for Link Check */
- 	if (dev->urb_intr) {
- 		ret = usb_submit_urb(dev->urb_intr, GFP_KERNEL);
diff --git a/target/linux/brcm2708/patches-4.14/950-0252-lan78xx-Change-LEDs-to-include-10Mb-activity.patch b/target/linux/brcm2708/patches-4.14/950-0252-lan78xx-Change-LEDs-to-include-10Mb-activity.patch
deleted file mode 100644
index 1b21b4a5d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0252-lan78xx-Change-LEDs-to-include-10Mb-activity.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 204bcf730f2f7b0806775bfd02a41e193e813eab Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 9 Mar 2018 17:28:07 +0000
-Subject: [PATCH 252/454] lan78xx: Change LEDs to include 10Mb activity
-
-The default LED modes put 1000Mb/activity on orange and 100Mb/activity
-on green, but this leaves no indication for a 10Mb link. Change the
-defaults to put 10Mb/100Mb/activity on green.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -1998,6 +1998,7 @@ static int lan78xx_phy_init(struct lan78
- {
- 	int ret;
- 	u32 mii_adv;
-+	u32 led_modes;
- 	struct phy_device *phydev = dev->net->phydev;
- 
- 	phydev = phy_find_first(dev->mdiobus);
-@@ -2070,6 +2071,19 @@ static int lan78xx_phy_init(struct lan78
- 	mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
- 	phydev->advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
- 
-+	/* Change LED defaults:
-+	 *   orange = link1000/activity
-+	 *   green  = link10/link100/activity
-+	 * led: 0=link/activity          1=link1000/activity
-+	 *      2=link100/activity       3=link10/activity
-+	 *      4=link100/1000/activity  5=link10/1000/activity
-+	 *      6=link10/100/activity    14=off    15=on
-+	 */
-+	led_modes = phy_read(phydev, 0x1d);
-+	led_modes &= ~0xff;
-+	led_modes |= (1 << 0) | (6 << 4);
-+	(void)phy_write(phydev, 0x1d, led_modes);
-+
- 	genphy_config_aneg(phydev);
- 
- 	dev->fc_autoneg = phydev->autoneg;
diff --git a/target/linux/brcm2708/patches-4.14/950-0253-BCM27XX_DT-Delete-stdout-path-property.patch b/target/linux/brcm2708/patches-4.14/950-0253-BCM27XX_DT-Delete-stdout-path-property.patch
deleted file mode 100644
index b83705c18..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0253-BCM27XX_DT-Delete-stdout-path-property.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 877341073006aff44e678daa775c4dbf55ca60b5 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 16 Mar 2018 10:13:19 +0000
-Subject: [PATCH 253/454] BCM27XX_DT: Delete 'stdout-path' property
-
-The 'stdout-path' property introduced upstream changes the behaviour
-on a non-Bluetooth Pi by enabling a console on UART0 when the user
-may not want one. The boot order is such that /dev/console ends up
-on the serial port instead of tty0.
-
-Delete the property in downstream DTBs to retrurn to the previous
-behaviour of only enabling consoles selected in cmdline.txt.
-
-See: https://github.com/raspberrypi/linux/issues/2436
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm270x.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/boot/dts/bcm270x.dtsi
-+++ b/arch/arm/boot/dts/bcm270x.dtsi
-@@ -4,6 +4,7 @@
- / {
- 	chosen {
- 		bootargs = "";
-+		/delete-property/ stdout-path;
- 	};
- 
- 	soc: soc {
diff --git a/target/linux/brcm2708/patches-4.14/950-0254-Fix-for-Pisound-s-MIDI-Input-getting-blocked-for-a-w.patch b/target/linux/brcm2708/patches-4.14/950-0254-Fix-for-Pisound-s-MIDI-Input-getting-blocked-for-a-w.patch
deleted file mode 100644
index 9d77f45a9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0254-Fix-for-Pisound-s-MIDI-Input-getting-blocked-for-a-w.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From a845f23bddcb2b0e48e8158bb06b0990c4760e7e Mon Sep 17 00:00:00 2001
-From: Giedrius <giedrius@blokas.io>
-Date: Fri, 16 Mar 2018 18:14:31 +0200
-Subject: [PATCH 254/454] Fix for Pisound's MIDI Input getting blocked for a
- while in rare cases.
-
-There was a possible race condition which could lead to Input's FIFO queue
-to be underflown, causing high amount of processing in the worker thread for
-some period of time.
-
-Signed-off-by: Giedrius Trainavicius <giedrius@blokas.io>
----
- sound/soc/bcm/pisound.c | 12 +++++++-----
- 1 file changed, 7 insertions(+), 5 deletions(-)
-
---- a/sound/soc/bcm/pisound.c
-+++ b/sound/soc/bcm/pisound.c
-@@ -56,6 +56,12 @@ static const char *pisnd_spi_get_version
- static int pisnd_midi_init(struct snd_card *card);
- static void pisnd_midi_uninit(void);
- 
-+enum task_e {
-+	TASK_PROCESS = 0,
-+};
-+
-+static void pisnd_schedule_process(enum task_e task);
-+
- #define PISOUND_LOG_PREFIX "pisound: "
- 
- #ifdef PISOUND_DEBUG
-@@ -129,7 +135,7 @@ static void pisnd_input_trigger(struct s
- {
- 	if (up) {
- 		pisnd_spi_set_callback(pisnd_midi_recv_callback, substream);
--		pisnd_midi_recv_callback(substream);
-+		pisnd_schedule_process(TASK_PROCESS);
- 	} else {
- 		pisnd_spi_set_callback(NULL, NULL);
- 	}
-@@ -258,10 +264,6 @@ static bool pisnd_spi_has_more(void)
- 	return gpiod_get_value(data_available);
- }
- 
--enum task_e {
--	TASK_PROCESS = 0,
--};
--
- static void pisnd_schedule_process(enum task_e task)
- {
- 	if (pisnd_spi_device != NULL &&
diff --git a/target/linux/brcm2708/patches-4.14/950-0255-overlays-use-all-seven-dwc2-gadget-fifos.patch b/target/linux/brcm2708/patches-4.14/950-0255-overlays-use-all-seven-dwc2-gadget-fifos.patch
deleted file mode 100644
index 96ad5e483..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0255-overlays-use-all-seven-dwc2-gadget-fifos.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 5c0c93fe305e7ea9bf7088e731cc64252df7ae64 Mon Sep 17 00:00:00 2001
-From: hexameron <hexameron>
-Date: Tue, 20 Mar 2018 12:48:10 +0000
-Subject: [PATCH 255/454] overlays: use all seven dwc2 gadget fifos.
-
-Linux 4.9 needed fifos to be set to their default values,
- leaving the last one (silently) set to zero size.
-From 4.12 Linux allows fifos to be set to any size EXCEPT zero.
-
-Resolves https://github.com/raspberrypi/linux/issues/2390
-
-Signed-off-by: John Greb <h3x4m3r0n@gmail.com>
----
- arch/arm/boot/dts/overlays/dwc2-overlay.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/overlays/dwc2-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/dwc2-overlay.dts
-@@ -15,7 +15,7 @@
- 			dr_mode = "otg";
- 			g-np-tx-fifo-size = <32>;
- 			g-rx-fifo-size = <256>;
--			g-tx-fifo-size = <512 512 512 512 512 768>;
-+			g-tx-fifo-size = <512 512 512 512 512 256 256>;
- 			status = "okay";
- 		};
- 	};
diff --git a/target/linux/brcm2708/patches-4.14/950-0256-overlays-Update-upstream-overlay-with-new-dwc2.patch b/target/linux/brcm2708/patches-4.14/950-0256-overlays-Update-upstream-overlay-with-new-dwc2.patch
deleted file mode 100644
index c6d2a629e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0256-overlays-Update-upstream-overlay-with-new-dwc2.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 31a7809e5c35dc488c7ab889481f25cffc8d8c1b Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 21 Mar 2018 13:53:39 +0000
-Subject: [PATCH 256/454] overlays: Update 'upstream' overlay with new dwc2
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/upstream-overlay.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/overlays/upstream-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/upstream-overlay.dts
-@@ -126,7 +126,7 @@
- 			dr_mode = "otg";
- 			g-np-tx-fifo-size = <32>;
- 			g-rx-fifo-size = <256>;
--			g-tx-fifo-size = <512 512 512 512 512 768>;
-+			g-tx-fifo-size = <512 512 512 512 512 256 256>;
- 			status = "okay";
- 		};
- 	};
diff --git a/target/linux/brcm2708/patches-4.14/950-0257-lan78xx-Read-LED-states-from-Device-Tree.patch b/target/linux/brcm2708/patches-4.14/950-0257-lan78xx-Read-LED-states-from-Device-Tree.patch
deleted file mode 100644
index 0a28a3807..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0257-lan78xx-Read-LED-states-from-Device-Tree.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From b6be512663a34f85e79bd6dd6caeece57d9f6fe0 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 21 Mar 2018 15:59:26 +0000
-Subject: [PATCH 257/454] lan78xx: Read LED states from Device Tree
-
-Add support for DT property "microchip,led-modes", a vector of two
-cells (u32s) in the range 0-15, each of which sets the mode for one
-of the two LEDs. The possible values are:
-
-    0=link/activity          1=link1000/activity
-    2=link100/activity       3=link10/activity
-    4=link100/1000/activity  5=link10/1000/activity
-    6=link10/100/activity    14=off    15=on
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 27 +++++++++++++++++++--------
- 1 file changed, 19 insertions(+), 8 deletions(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -1998,7 +1998,9 @@ static int lan78xx_phy_init(struct lan78
- {
- 	int ret;
- 	u32 mii_adv;
--	u32 led_modes;
-+	u32 led_modes[2];
-+	u32 led_modes_reg;
-+	int i;
- 	struct phy_device *phydev = dev->net->phydev;
- 
- 	phydev = phy_find_first(dev->mdiobus);
-@@ -2071,18 +2073,27 @@ static int lan78xx_phy_init(struct lan78
- 	mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
- 	phydev->advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
- 
--	/* Change LED defaults:
--	 *   orange = link1000/activity
--	 *   green  = link10/link100/activity
-+	/* Set LED modes:
- 	 * led: 0=link/activity          1=link1000/activity
- 	 *      2=link100/activity       3=link10/activity
- 	 *      4=link100/1000/activity  5=link10/1000/activity
- 	 *      6=link10/100/activity    14=off    15=on
- 	 */
--	led_modes = phy_read(phydev, 0x1d);
--	led_modes &= ~0xff;
--	led_modes |= (1 << 0) | (6 << 4);
--	(void)phy_write(phydev, 0x1d, led_modes);
-+
-+	memset(led_modes, ~0, sizeof(led_modes));
-+
-+	of_property_read_u32_array(dev->udev->dev.of_node,
-+				   "microchip,led-modes",
-+				   led_modes, ARRAY_SIZE(led_modes));
-+
-+	led_modes_reg = phy_read(phydev, 0x1d);
-+	for (i = 0; i < ARRAY_SIZE(led_modes); i++) {
-+		if (led_modes[i] != ~0) {
-+			led_modes_reg &= ~(0xf << (i * 4));
-+			led_modes_reg |= (led_modes[i] & 0xf) << (i * 4);
-+		}
-+	}
-+	(void)phy_write(phydev, 0x1d, led_modes_reg);
- 
- 	genphy_config_aneg(phydev);
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0258-BCM27XX_DT-Set-LED-modes-from-Device-Tree.patch b/target/linux/brcm2708/patches-4.14/950-0258-BCM27XX_DT-Set-LED-modes-from-Device-Tree.patch
deleted file mode 100644
index 73d3ff259..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0258-BCM27XX_DT-Set-LED-modes-from-Device-Tree.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 8dfd69beccc1c582fba134825df65f7e5d2f17ad Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 21 Mar 2018 16:04:18 +0000
-Subject: [PATCH 258/454] BCM27XX_DT: Set LED modes from Device Tree
-
-The new default values for LAN7515 (LAN7800) are:
-
-  LED0 = 1 (link1000/activity)
-  LED1 = 6 (link10/link100/activity)
-
-Also add two dtparams - eth_led0 and eth_led1 - to provide user control
-over the LEDs.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi |  7 +++++++
- arch/arm/boot/dts/overlays/README          | 10 ++++++++++
- 2 files changed, 17 insertions(+)
-
---- a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
-+++ b/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
-@@ -22,6 +22,11 @@
- 				reg = <1>;
- 				microchip,eee-enabled;
- 				microchip,tx-lpi-timer = <600>; /* non-aggressive*/
-+				/*
-+				 * led0 = 1:link1000/activity
-+				 * led1 = 6:link10/100/activity
-+				 */
-+				microchip,led-modes = <1 6>;
- 			};
- 		};
- 	};
-@@ -32,5 +37,7 @@
- 	__overrides__ {
- 		eee = <&ethernet>,"microchip,eee-enabled?";
- 		tx_lpi_timer = <&ethernet>,"microchip,tx-lpi-timer:0";
-+		eth_led0 = <&ethernet>,"microchip,led-modes:0";
-+		eth_led1 = <&ethernet>,"microchip,led-modes:4";
- 	};
- };
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -93,6 +93,16 @@ Params:
-                                 compatible devices (default "on"). See also
-                                 "tx_lpi_timer".
- 
-+        eth_led0                Set mode of LED0 (usually orange) (default
-+                                "1"). The legal values are:
-+                                0=link/activity          1=link1000/activity
-+                                2=link100/activity       3=link10/activity
-+                                4=link100/1000/activity  5=link10/1000/activity
-+                                6=link10/100/activity    14=off    15=on
-+
-+        eth_led1                Set mode of LED1 (usually green) (default
-+                                "6"). See eth_led0 for legal values.
-+
-         i2c_arm                 Set to "on" to enable the ARM's i2c interface
-                                 (default "off")
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0259-This-commit-adds-support-for-RP3-B-Plus-in-in-arch-a.patch b/target/linux/brcm2708/patches-4.14/950-0259-This-commit-adds-support-for-RP3-B-Plus-in-in-arch-a.patch
deleted file mode 100644
index 54e97c702..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0259-This-commit-adds-support-for-RP3-B-Plus-in-in-arch-a.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From e94821ffebf0550b7244029b0fe360fd5627fb9b Mon Sep 17 00:00:00 2001
-From: derpeter <derpeter@users.noreply.github.com>
-Date: Sun, 25 Mar 2018 23:27:30 +0200
-Subject: [PATCH 259/454] This commit adds support for RP3-B-Plus in in arch
- arm64 (#2464)
-
----
- arch/arm64/boot/dts/broadcom/Makefile                 | 1 +
- arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts | 3 +++
- arch/arm64/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi | 1 +
- arch/arm64/configs/bcmrpi3_defconfig                  | 1 +
- 4 files changed, 6 insertions(+)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts
- create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi
-
---- a/arch/arm64/boot/dts/broadcom/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/Makefile
-@@ -8,6 +8,7 @@ endif
- dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
- dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-3-b.dtb
- dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb
-+dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb
- 
- dts-dirs += ../overlays
- 
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts
-@@ -0,0 +1,3 @@
-+#define RPI364
-+
-+#include "../../../../arm/boot/dts/bcm2710-rpi-3-b-plus.dts"
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi
-@@ -0,0 +1,43 @@
-+/ {
-+	aliases {
-+		ethernet0 = &ethernet;
-+	};
-+};
-+
-+&usb {
-+	usb1@1 {
-+		compatible = "usb424,2514";
-+		reg = <1>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		usb1_1@1 {
-+			compatible = "usb424,2514";
-+			reg = <1>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			ethernet: usbether@1 {
-+				compatible = "usb424,7800";
-+				reg = <1>;
-+				microchip,eee-enabled;
-+				microchip,tx-lpi-timer = <600>; /* non-aggressive*/
-+				/*
-+				 * led0 = 1:link1000/activity
-+				 * led1 = 6:link10/100/activity
-+				 */
-+				microchip,led-modes = <1 6>;
-+			};
-+		};
-+	};
-+};
-+
-+
-+/ {
-+	__overrides__ {
-+		eee = <&ethernet>,"microchip,eee-enabled?";
-+		tx_lpi_timer = <&ethernet>,"microchip,tx-lpi-timer:0";
-+		eth_led0 = <&ethernet>,"microchip,led-modes:0";
-+		eth_led1 = <&ethernet>,"microchip,led-modes:4";
-+	};
-+};
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -479,6 +479,7 @@ CONFIG_USB_NET_SR9700=m
- CONFIG_USB_NET_SR9800=m
- CONFIG_USB_NET_SMSC75XX=m
- CONFIG_USB_NET_SMSC95XX=y
-+CONFIG_USB_LAN78XX=y
- CONFIG_USB_NET_GL620A=m
- CONFIG_USB_NET_NET1080=m
- CONFIG_USB_NET_PLUSB=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0260-Add-overlay-for-Semtech-SX150X-I2C-GPIO-Expanders.patch b/target/linux/brcm2708/patches-4.14/950-0260-Add-overlay-for-Semtech-SX150X-I2C-GPIO-Expanders.patch
deleted file mode 100644
index d66a88b76..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0260-Add-overlay-for-Semtech-SX150X-I2C-GPIO-Expanders.patch
+++ /dev/null
@@ -1,1759 +0,0 @@
-From 0b2881369a38b0a139ae4a256ea1953750fb6a76 Mon Sep 17 00:00:00 2001
-From: wavelet2 <a3d35232@btinternet.com>
-Date: Thu, 22 Mar 2018 19:08:02 +0000
-Subject: [PATCH 260/454] Add overlay for Semtech SX150X I2C GPIO Expanders
-
----
- arch/arm/boot/dts/overlays/Makefile           |    1 +
- arch/arm/boot/dts/overlays/README             |   19 +
- arch/arm/boot/dts/overlays/sx150x-overlay.dts | 1706 +++++++++++++++++
- 3 files changed, 1726 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/sx150x-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -120,6 +120,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	spi2-2cs.dtbo \
- 	spi2-3cs.dtbo \
- 	superaudioboard.dtbo \
-+	sx150x.dtbo \
- 	tinylcd35.dtbo \
- 	uart0.dtbo \
- 	uart1.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1703,6 +1703,25 @@ Load:   dtoverlay=superaudioboard,<param
- Params: gpiopin                 GPIO pin for codec reset
- 
- 
-+Name:   sx150x
-+Info:   Configures the Semtech SX150X I2C GPIO expanders.
-+Load:   dtoverlay=sx150x,<param>=<val>
-+Params: sx150<x>-<n>-<m>        Enables SX150X device on I2C#<n> with slave
-+                                address <m>. <x> may be 1-9. <n> may be 0 or 1.
-+                                Permissible values of <m> (which is denoted in
-+                                hex) depend on the device variant. For SX1501,
-+                                SX1502, SX1504 and SX1505, <m> may be 20 or 21.
-+                                For SX1503 and SX1506, <m> may be 20. For
-+                                SX1507 and SX1509, <m> may be 3E, 3F, 70 or 71.
-+                                For SX1508, <m> may be 20, 21, 22 or 23.
-+
-+        sx150<x>-<n>-<m>-int-gpio
-+                                Integer, enables interrupts on SX150X device on
-+                                I2C#<n> with slave address <m>, specifies
-+                                the GPIO pin to which NINT output of SX150X is
-+                                connected.
-+
-+
- Name:   tinylcd35
- Info:   3.5" Color TFT Display by www.tinylcd.com
-         Options: Touch, RTC, keypad
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/sx150x-overlay.dts
-@@ -0,0 +1,1706 @@
-+// Definitions for SX150x I2C GPIO Expanders from Semtech
-+
-+// dtparams:
-+//     sx150<x>-<n>-<m>          - Enables SX150X device on I2C#<n> with slave address <m>. <x> may be 1-9.
-+//                                 <n> may be 0 or 1.  Permissible values of <m> (which is denoted in hex)
-+//                                 depend on the device variant.
-+//                                 For SX1501, SX1502, SX1504 and SX1505, <m> may be 20 or 21.
-+//                                 For SX1503 and SX1506, <m> may be 20.
-+//                                 For SX1507 and SX1509, <m> may be 3E, 3F, 70 or 71.
-+//                                 For SX1508, <m> may be 20, 21, 22 or 23.
-+//     sx150<x>-<n>-<m>-int-gpio - Integer, enables interrupts on SX150X device on I2C#<n> with slave address <m>,
-+//                                 specifies the GPIO pin to which NINT output of SX150X is connected.
-+//
-+//
-+// Example 1: A single SX1505 device on I2C#1 with its slave address set to 0x20 and NINT output connected to GPIO25:
-+// dtoverlay=sx150x:sx1505-1-20,sx1505-1-20-int-gpio=25
-+//
-+// Example 2: Two SX1507 devices on I2C#0 with their slave addresses set to 0x3E and 0x70 (interrupts not used):
-+// dtoverlay=sx150x:sx1507-0-3E,sx1507-0-70
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	// Enable I2C#0 interface
-+	fragment@0 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	// Enable I2C#1 interface
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	// Enable a SX1501 on I2C#0 at slave addr 0x20
-+	fragment@2 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1501_0_20: sx150x@20 {
-+				compatible = "semtech,sx1501q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1501-0-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1501 on I2C#1 at slave addr 0x20
-+	fragment@3 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1501_1_20: sx150x@20 {
-+				compatible = "semtech,sx1501q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1501-1-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1501 on I2C#0 at slave addr 0x21
-+	fragment@4 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1501_0_21: sx150x@21 {
-+				compatible = "semtech,sx1501q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1501-0-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1501 on I2C#1 at slave addr 0x21
-+	fragment@5 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1501_1_21: sx150x@21 {
-+				compatible = "semtech,sx1501q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1501-1-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1502 on I2C#0 at slave addr 0x20
-+	fragment@6 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1502_0_20: sx150x@20 {
-+				compatible = "semtech,sx1502q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1502-0-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1502 on I2C#1 at slave addr 0x20
-+	fragment@7 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1502_1_20: sx150x@20 {
-+				compatible = "semtech,sx1502q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1502-1-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1502 on I2C#0 at slave addr 0x21
-+	fragment@8 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1502_0_21: sx150x@21 {
-+				compatible = "semtech,sx1502q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1502-0-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1502 on I2C#1 at slave addr 0x21
-+	fragment@9 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1502_1_21: sx150x@21 {
-+				compatible = "semtech,sx1502q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1501-1-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1503 on I2C#0 at slave addr 0x20
-+	fragment@10 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1503_0_20: sx150x@20 {
-+				compatible = "semtech,sx1503q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1503-0-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1503 on I2C#1 at slave addr 0x20
-+	fragment@11 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1503_1_20: sx150x@20 {
-+				compatible = "semtech,sx1503q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1503-1-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1504 on I2C#0 at slave addr 0x20
-+	fragment@12 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1504_0_20: sx150x@20 {
-+				compatible = "semtech,sx1504q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1504-0-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1504 on I2C#1 at slave addr 0x20
-+	fragment@13 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1504_1_20: sx150x@20 {
-+				compatible = "semtech,sx1504q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1504-1-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1504 on I2C#0 at slave addr 0x21
-+	fragment@14 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1504_0_21: sx150x@21 {
-+				compatible = "semtech,sx1504q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1504-0-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1504 on I2C#1 at slave addr 0x21
-+	fragment@15 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1504_1_21: sx150x@21 {
-+				compatible = "semtech,sx1504q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1504-1-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1505 on I2C#0 at slave addr 0x20
-+	fragment@16 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1505_0_20: sx150x@20 {
-+				compatible = "semtech,sx1505q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1505-0-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1505 on I2C#1 at slave addr 0x20
-+	fragment@17 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1505_1_20: sx150x@20 {
-+				compatible = "semtech,sx1505q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1505-1-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1505 on I2C#0 at slave addr 0x21
-+	fragment@18 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1505_0_21: sx150x@21 {
-+				compatible = "semtech,sx1505q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1505-0-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1505 on I2C#1 at slave addr 0x21
-+	fragment@19 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1505_1_21: sx150x@21 {
-+				compatible = "semtech,sx1505q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1505-1-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1506 on I2C#0 at slave addr 0x20
-+	fragment@20 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1506_0_20: sx150x@20 {
-+				compatible = "semtech,sx1506q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1506-0-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1506 on I2C#1 at slave addr 0x20
-+	fragment@21 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1506_1_20: sx150x@20 {
-+				compatible = "semtech,sx1506q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1506-1-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1507 on I2C#0 at slave addr 0x3E
-+	fragment@22 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1507_0_3E: sx150x@3E {
-+				compatible = "semtech,sx1507q";
-+				reg = <0x3E>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1507_0_3E-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1507 on I2C#1 at slave addr 0x3E
-+	fragment@23 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1507_1_3E: sx150x@3E {
-+				compatible = "semtech,sx1507q";
-+				reg = <0x3E>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1507_1_3E-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1507 on I2C#0 at slave addr 0x3F
-+	fragment@24 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1507_0_3F: sx150x@3F {
-+				compatible = "semtech,sx1507q";
-+				reg = <0x3F>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1507_0_3F-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1507 on I2C#1 at slave addr 0x3F
-+	fragment@25 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1507_1_3F: sx150x@3F {
-+				compatible = "semtech,sx1507q";
-+				reg = <0x3F>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1507_1_3F-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1507 on I2C#0 at slave addr 0x70
-+	fragment@26 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1507_0_70: sx150x@70 {
-+				compatible = "semtech,sx1507q";
-+				reg = <0x70>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1507-0-70-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1507 on I2C#1 at slave addr 0x70
-+	fragment@27 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1507_1_70: sx150x@70 {
-+				compatible = "semtech,sx1507q";
-+				reg = <0x70>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1507-1-70-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1507 on I2C#0 at slave addr 0x71
-+	fragment@28 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1507_0_71: sx150x@71 {
-+				compatible = "semtech,sx1507q";
-+				reg = <0x71>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1507-0-71-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1507 on I2C#1 at slave addr 0x71
-+	fragment@29 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1507_1_71: sx150x@71 {
-+				compatible = "semtech,sx1507q";
-+				reg = <0x71>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1507-1-71-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1508 on I2C#0 at slave addr 0x20
-+	fragment@30 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1508_0_20: sx150x@20 {
-+				compatible = "semtech,sx1508q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1508-0-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1508 on I2C#1 at slave addr 0x20
-+	fragment@31 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1508_1_20: sx150x@20 {
-+				compatible = "semtech,sx1508q";
-+				reg = <0x20>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1508-1-20-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1508 on I2C#0 at slave addr 0x21
-+	fragment@32 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1508_0_21: sx150x@21 {
-+				compatible = "semtech,sx1508q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1508-0-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1508 on I2C#1 at slave addr 0x21
-+	fragment@33 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1508_1_21: sx150x@21 {
-+				compatible = "semtech,sx1508q";
-+				reg = <0x21>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1508-1-21-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1508 on I2C#0 at slave addr 0x22
-+	fragment@34 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1508_0_22: sx150x@22 {
-+				compatible = "semtech,sx1508q";
-+				reg = <0x22>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1508-0-22-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1508 on I2C#1 at slave addr 0x22
-+	fragment@35 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1508_1_22: sx150x@22 {
-+				compatible = "semtech,sx1508q";
-+				reg = <0x22>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1508-1-22-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1508 on I2C#0 at slave addr 0x23
-+	fragment@36 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1508_0_23: sx150x@23 {
-+				compatible = "semtech,sx1508q";
-+				reg = <0x23>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1508-0-23-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1508 on I2C#1 at slave addr 0x23
-+	fragment@37 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1508_1_23: sx150x@23 {
-+				compatible = "semtech,sx1508q";
-+				reg = <0x23>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1508-1-23-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1509 on I2C#0 at slave addr 0x3E
-+	fragment@38 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1509_0_3E: sx150x@3E {
-+				compatible = "semtech,sx1509q";
-+				reg = <0x3E>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1509_0_3E-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1509 on I2C#1 at slave addr 0x3E
-+	fragment@39 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1509_1_3E: sx150x@3E {
-+				compatible = "semtech,sx1509q";
-+				reg = <0x3E>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1509_1_3E-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1509 on I2C#0 at slave addr 0x3F
-+	fragment@40 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1509_0_3F: sx150x@3F {
-+				compatible = "semtech,sx1509q";
-+				reg = <0x3F>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1509_0_3F-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1509 on I2C#1 at slave addr 0x3F
-+	fragment@41 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1509_1_3F: sx150x@3F {
-+				compatible = "semtech,sx1509q";
-+				reg = <0x3F>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1509_1_3F-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1509 on I2C#0 at slave addr 0x70
-+	fragment@42 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1509_0_70: sx150x@70 {
-+				compatible = "semtech,sx1509q";
-+				reg = <0x70>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1509-0-70-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1509 on I2C#1 at slave addr 0x70
-+	fragment@43 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1509_1_70: sx150x@70 {
-+				compatible = "semtech,sx1509q";
-+				reg = <0x70>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1509-1-70-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1509 on I2C#0 at slave addr 0x71
-+	fragment@44 {
-+		target = <&i2c0>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1509_0_71: sx150x@71 {
-+				compatible = "semtech,sx1509q";
-+				reg = <0x71>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1509-0-71-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable a SX1509 on I2C#1 at slave addr 0x71
-+	fragment@45 {
-+		target = <&i2c1>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			sx1509_1_71: sx150x@71 {
-+				compatible = "semtech,sx1509q";
-+				reg = <0x71>;
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				#interrupt-cells = <2>;
-+				interrupts = <25 2>; /* 1st word overwritten by sx1509-1-71-int-gpio parameter
-+				                        2nd word is 2 for falling-edge triggered */
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1501 on I2C#0 at slave addr 0x20
-+	fragment@46 {
-+		target = <&sx1501_0_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1501 on I2C#1 at slave addr 0x20
-+	fragment@47 {
-+		target = <&sx1501_1_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1501 on I2C#0 at slave addr 0x21
-+	fragment@48 {
-+		target = <&sx1501_0_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1501 on I2C#1 at slave addr 0x21
-+	fragment@49 {
-+		target = <&sx1501_1_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1502 on I2C#0 at slave addr 0x20
-+	fragment@50 {
-+		target = <&sx1502_0_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1502 on I2C#1 at slave addr 0x20
-+	fragment@51 {
-+		target = <&sx1502_1_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1502 on I2C#0 at slave addr 0x21
-+	fragment@52 {
-+		target = <&sx1502_0_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1502 on I2C#1 at slave addr 0x21
-+	fragment@53 {
-+		target = <&sx1502_1_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1503 on I2C#0 at slave addr 0x20
-+	fragment@54 {
-+		target = <&sx1503_0_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1503 on I2C#1 at slave addr 0x20
-+	fragment@55 {
-+		target = <&sx1503_1_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1504 on I2C#0 at slave addr 0x20
-+	fragment@56 {
-+		target = <&sx1504_0_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1504 on I2C#1 at slave addr 0x20
-+	fragment@57 {
-+		target = <&sx1504_1_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1504 on I2C#0 at slave addr 0x21
-+	fragment@58 {
-+		target = <&sx1504_0_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1504 on I2C#1 at slave addr 0x21
-+	fragment@59 {
-+		target = <&sx1504_1_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1505 on I2C#0 at slave addr 0x20
-+	fragment@60 {
-+		target = <&sx1505_0_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1505 on I2C#1 at slave addr 0x20
-+	fragment@61 {
-+		target = <&sx1505_1_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1505 on I2C#0 at slave addr 0x21
-+	fragment@62 {
-+		target = <&sx1505_0_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1505 on I2C#1 at slave addr 0x21
-+	fragment@63 {
-+		target = <&sx1505_1_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1506 on I2C#0 at slave addr 0x20
-+	fragment@64 {
-+		target = <&sx1506_0_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1506 on I2C#1 at slave addr 0x20
-+	fragment@65 {
-+		target = <&sx1506_1_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1507 on I2C#0 at slave addr 0x3E
-+	fragment@66 {
-+		target = <&sx1507_0_3E>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_3E_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1507 on I2C#1 at slave addr 0x3E
-+	fragment@67 {
-+		target = <&sx1507_1_3E>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_3E_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1507 on I2C#0 at slave addr 0x3F
-+	fragment@68 {
-+		target = <&sx1507_0_3F>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_3F_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1507 on I2C#1 at slave addr 0x3F
-+	fragment@69 {
-+		target = <&sx1507_1_3F>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_3F_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1507 on I2C#0 at slave addr 0x70
-+	fragment@70 {
-+		target = <&sx1507_0_70>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_70_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1507 on I2C#1 at slave addr 0x70
-+	fragment@71 {
-+		target = <&sx1507_1_70>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_70_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1507 on I2C#0 at slave addr 0x71
-+	fragment@72 {
-+		target = <&sx1507_0_71>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_71_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1507 on I2C#1 at slave addr 0x71
-+	fragment@73 {
-+		target = <&sx1507_1_71>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_71_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1508 on I2C#0 at slave addr 0x20
-+	fragment@74 {
-+		target = <&sx1508_0_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1508 on I2C#1 at slave addr 0x20
-+	fragment@75 {
-+		target = <&sx1508_1_20>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_20_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1508 on I2C#0 at slave addr 0x21
-+	fragment@76 {
-+		target = <&sx1508_0_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1508 on I2C#1 at slave addr 0x21
-+	fragment@77 {
-+		target = <&sx1508_1_21>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_21_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1508 on I2C#0 at slave addr 0x22
-+	fragment@78 {
-+		target = <&sx1508_0_22>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_22_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1508 on I2C#1 at slave addr 0x22
-+	fragment@79 {
-+		target = <&sx1508_1_22>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_22_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1508 on I2C#0 at slave addr 0x23
-+	fragment@80 {
-+		target = <&sx1508_0_23>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_23_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1508 on I2C#1 at slave addr 0x23
-+	fragment@81 {
-+		target = <&sx1508_1_23>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_23_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1509 on I2C#0 at slave addr 0x3E
-+	fragment@82 {
-+		target = <&sx1509_0_3E>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_3E_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1509 on I2C#1 at slave addr 0x3E
-+	fragment@83 {
-+		target = <&sx1509_1_3E>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_3E_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1509 on I2C#0 at slave addr 0x3F
-+	fragment@84 {
-+		target = <&sx1509_0_3F>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_3F_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1509 on I2C#1 at slave addr 0x3F
-+	fragment@85 {
-+		target = <&sx1509_1_3F>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_3F_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1509 on I2C#0 at slave addr 0x70
-+	fragment@86 {
-+		target = <&sx1509_0_70>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_70_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1509 on I2C#1 at slave addr 0x70
-+	fragment@87 {
-+		target = <&sx1509_1_70>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_70_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1509 on I2C#0 at slave addr 0x71
-+	fragment@88 {
-+		target = <&sx1509_0_71>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_0_71_pins>;
-+		};
-+	};
-+
-+	// Enable interrupts for a SX1509 on I2C#1 at slave addr 0x71
-+	fragment@89 {
-+		target = <&sx1509_1_71>;
-+		__dormant__ {
-+			interrupt-parent = <&gpio>;
-+			interrupt-controller;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sx150x_1_71_pins>;
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x20
-+        // Configure as a input with no pull-up/down
-+	fragment@90 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_0_20_pins: sx150x_0_20_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-0-20-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x20
-+        // Configure as a input with no pull-up/down
-+	fragment@91 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_1_20_pins: sx150x_1_20_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-1-20-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x21
-+        // Configure as a input with no pull-up/down
-+	fragment@92 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_0_21_pins: sx150x_0_21_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-0-21-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x21
-+        // Configure as a input with no pull-up/down
-+	fragment@93 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_1_21_pins: sx150x_1_21_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-1-21-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x22
-+        // Configure as a input with no pull-up/down
-+	fragment@94 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_0_22_pins: sx150x_0_22_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-0-22-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x22
-+        // Configure as a input with no pull-up/down
-+	fragment@95 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_1_22_pins: sx150x_1_22_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-1-22-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x23
-+        // Configure as a input with no pull-up/down
-+	fragment@96 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_0_23_pins: sx150x_0_23_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-0-23-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x23
-+        // Configure as a input with no pull-up/down
-+	fragment@97 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_1_23_pins: sx150x_1_23_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-1-23-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x3E
-+        // Configure as a input with no pull-up/down
-+	fragment@98 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_0_3E_pins: sx150x_0_3E_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-0-3E-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x3E
-+        // Configure as a input with no pull-up/down
-+	fragment@99 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_1_3E_pins: sx150x_1_3E_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-1-3E-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x3F
-+        // Configure as a input with no pull-up/down
-+	fragment@100 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_0_3F_pins: sx150x_0_3F_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-0-3F-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x3F
-+        // Configure as a input with no pull-up/down
-+	fragment@101 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_1_3F_pins: sx150x_1_3F_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-1-3F-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x70
-+        // Configure as a input with no pull-up/down
-+	fragment@102 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_0_70_pins: sx150x_0_70_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-0-70-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x70
-+        // Configure as a input with no pull-up/down
-+	fragment@103 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_1_70_pins: sx150x_1_70_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-1-70-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x71
-+        // Configure as a input with no pull-up/down
-+	fragment@104 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_0_71_pins: sx150x_0_71_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-0-71-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x71
-+        // Configure as a input with no pull-up/down
-+	fragment@105 {
-+		target = <&gpio>;
-+		__dormant__ {
-+			sx150x_1_71_pins: sx150x_1_71_pins {
-+				brcm,pins = <0>;  /* overwritten by sx150x-1-71-int-gpio parameter */
-+				brcm,function = <0>;
-+				brcm,pull = <0>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		sx1501-0-20          = <0>,"+0+2";
-+		sx1501-1-20          = <0>,"+1+3";
-+		sx1501-0-21          = <0>,"+0+4";
-+		sx1501-1-21          = <0>,"+1+5";
-+		sx1502-0-20          = <0>,"+0+6";
-+		sx1502-1-20          = <0>,"+1+7";
-+		sx1502-0-21          = <0>,"+0+8";
-+		sx1502-1-21          = <0>,"+1+9";
-+		sx1503-0-20          = <0>,"+0+10";
-+		sx1503-1-20          = <0>,"+1+11";
-+		sx1504-0-20          = <0>,"+0+12";
-+		sx1504-1-20          = <0>,"+1+13";
-+		sx1504-0-21          = <0>,"+0+14";
-+		sx1504-1-21          = <0>,"+1+15";
-+		sx1505-0-20          = <0>,"+0+16";
-+		sx1505-1-20          = <0>,"+1+17";
-+		sx1505-0-21          = <0>,"+0+18";
-+		sx1505-1-21          = <0>,"+1+19";
-+		sx1506-0-20          = <0>,"+0+20";
-+		sx1506-1-20          = <0>,"+1+21";
-+		sx1507-0-3E          = <0>,"+0+22";
-+		sx1507-1-3E          = <0>,"+1+23";
-+		sx1507-0-3F          = <0>,"+0+24";
-+		sx1507-1-3F          = <0>,"+1+25";
-+		sx1507-0-70          = <0>,"+0+26";
-+		sx1507-1-70          = <0>,"+1+27";
-+		sx1507-0-71          = <0>,"+0+28";
-+		sx1507-1-71          = <0>,"+1+29";
-+		sx1508-0-20          = <0>,"+0+30";
-+		sx1508-1-20          = <0>,"+1+31";
-+		sx1508-0-21          = <0>,"+0+32";
-+		sx1508-1-21          = <0>,"+1+33";
-+		sx1508-0-22          = <0>,"+0+34";
-+		sx1508-1-22          = <0>,"+1+35";
-+		sx1508-0-23          = <0>,"+0+36";
-+		sx1508-1-23          = <0>,"+1+37";
-+		sx1509-0-3E          = <0>,"+0+38";
-+		sx1509-1-3E          = <0>,"+1+39";
-+		sx1509-0-3F          = <0>,"+0+40";
-+		sx1509-1-3F          = <0>,"+1+41";
-+		sx1509-0-70          = <0>,"+0+42";
-+		sx1509-1-70          = <0>,"+1+43";
-+		sx1509-0-71          = <0>,"+0+44";
-+		sx1509-1-71          = <0>,"+1+45";
-+		sx1501-0-20-int-gpio = <0>,"+46+90",  <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1501_0_20>,"interrupts:0";
-+		sx1501-1-20-int-gpio = <0>,"+47+91",  <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1501_1_20>,"interrupts:0";
-+		sx1501-0-21-int-gpio = <0>,"+48+92",  <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1501_0_21>,"interrupts:0";
-+		sx1501-1-21-int-gpio = <0>,"+49+93",  <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1501_1_21>,"interrupts:0";
-+		sx1502-0-20-int-gpio = <0>,"+50+90",  <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1502_0_20>,"interrupts:0";
-+		sx1502-1-20-int-gpio = <0>,"+51+91",  <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1502_1_20>,"interrupts:0";
-+		sx1502-0-21-int-gpio = <0>,"+52+92",  <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1502_0_21>,"interrupts:0";
-+		sx1502-1-21-int-gpio = <0>,"+53+93",  <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1502_1_21>,"interrupts:0";
-+		sx1503-0-20-int-gpio = <0>,"+54+90",  <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1503_0_20>,"interrupts:0";
-+		sx1503-1-20-int-gpio = <0>,"+55+91",  <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1503_1_20>,"interrupts:0";
-+		sx1504-0-20-int-gpio = <0>,"+56+90",  <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1504_0_20>,"interrupts:0";
-+		sx1504-1-20-int-gpio = <0>,"+57+91",  <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1504_1_20>,"interrupts:0";
-+		sx1504-0-21-int-gpio = <0>,"+58+92",  <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1504_0_21>,"interrupts:0";
-+		sx1504-1-21-int-gpio = <0>,"+59+93",  <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1504_1_21>,"interrupts:0";
-+		sx1505-0-20-int-gpio = <0>,"+60+90",  <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1505_0_20>,"interrupts:0";
-+		sx1505-1-20-int-gpio = <0>,"+61+91",  <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1505_1_20>,"interrupts:0";
-+		sx1505-0-21-int-gpio = <0>,"+62+92",  <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1505_0_21>,"interrupts:0";
-+		sx1505-1-21-int-gpio = <0>,"+63+93",  <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1505_1_21>,"interrupts:0";
-+		sx1506-0-20-int-gpio = <0>,"+64+90",  <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1506_0_20>,"interrupts:0";
-+		sx1506-1-20-int-gpio = <0>,"+65+91",  <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1506_1_20>,"interrupts:0";
-+		sx1507-0-3E-int-gpio = <0>,"+66+98",  <&sx150x_0_3E_pins>,"brcm,pins:0", <&sx1507_0_3E>,"interrupts:0";
-+		sx1507-1-3E-int-gpio = <0>,"+67+99",  <&sx150x_1_3E_pins>,"brcm,pins:0", <&sx1507_1_3E>,"interrupts:0";
-+		sx1507-0-3F-int-gpio = <0>,"+68+100", <&sx150x_0_3F_pins>,"brcm,pins:0", <&sx1507_0_3F>,"interrupts:0";
-+		sx1507-1-3F-int-gpio = <0>,"+69+101", <&sx150x_1_3F_pins>,"brcm,pins:0", <&sx1507_1_3F>,"interrupts:0";
-+		sx1507-0-70-int-gpio = <0>,"+60+102", <&sx150x_0_70_pins>,"brcm,pins:0", <&sx1507_0_70>,"interrupts:0";
-+		sx1507-1-70-int-gpio = <0>,"+71+103", <&sx150x_1_70_pins>,"brcm,pins:0", <&sx1507_1_70>,"interrupts:0";
-+		sx1507-0-71-int-gpio = <0>,"+72+104", <&sx150x_0_71_pins>,"brcm,pins:0", <&sx1507_0_71>,"interrupts:0";
-+		sx1507-1-71-int-gpio = <0>,"+73+105", <&sx150x_1_71_pins>,"brcm,pins:0", <&sx1507_1_71>,"interrupts:0";
-+		sx1508-0-20-int-gpio = <0>,"+74+90",  <&sx150x_0_20_pins>,"brcm,pins:0", <&sx1508_0_20>,"interrupts:0";
-+		sx1508-1-20-int-gpio = <0>,"+75+91",  <&sx150x_1_20_pins>,"brcm,pins:0", <&sx1508_1_20>,"interrupts:0";
-+		sx1508-0-21-int-gpio = <0>,"+76+92",  <&sx150x_0_21_pins>,"brcm,pins:0", <&sx1508_0_21>,"interrupts:0";
-+		sx1508-1-21-int-gpio = <0>,"+77+93",  <&sx150x_1_21_pins>,"brcm,pins:0", <&sx1508_1_21>,"interrupts:0";
-+		sx1508-0-22-int-gpio = <0>,"+78+94",  <&sx150x_0_22_pins>,"brcm,pins:0", <&sx1508_0_22>,"interrupts:0";
-+		sx1508-1-22-int-gpio = <0>,"+79+95",  <&sx150x_1_22_pins>,"brcm,pins:0", <&sx1508_1_22>,"interrupts:0";
-+		sx1508-0-23-int-gpio = <0>,"+80+96",  <&sx150x_0_23_pins>,"brcm,pins:0", <&sx1508_0_23>,"interrupts:0";
-+		sx1508-1-23-int-gpio = <0>,"+81+97",  <&sx150x_1_23_pins>,"brcm,pins:0", <&sx1508_1_23>,"interrupts:0";
-+		sx1509-0-3E-int-gpio = <0>,"+82+98",  <&sx150x_0_3E_pins>,"brcm,pins:0", <&sx1509_0_3E>,"interrupts:0";
-+		sx1509-1-3E-int-gpio = <0>,"+83+99",  <&sx150x_1_3E_pins>,"brcm,pins:0", <&sx1509_1_3E>,"interrupts:0";
-+		sx1509-0-3F-int-gpio = <0>,"+84+100", <&sx150x_0_3F_pins>,"brcm,pins:0", <&sx1509_0_3F>,"interrupts:0";
-+		sx1509-1-3F-int-gpio = <0>,"+85+101", <&sx150x_1_3F_pins>,"brcm,pins:0", <&sx1509_1_3F>,"interrupts:0";
-+		sx1509-0-70-int-gpio = <0>,"+86+102", <&sx150x_0_70_pins>,"brcm,pins:0", <&sx1509_0_70>,"interrupts:0";
-+		sx1509-1-70-int-gpio = <0>,"+87+103", <&sx150x_1_70_pins>,"brcm,pins:0", <&sx1509_1_70>,"interrupts:0";
-+		sx1509-0-71-int-gpio = <0>,"+88+104", <&sx150x_0_71_pins>,"brcm,pins:0", <&sx1509_0_71>,"interrupts:0";
-+		sx1509-1-71-int-gpio = <0>,"+89+105", <&sx150x_1_71_pins>,"brcm,pins:0", <&sx1509_1_71>,"interrupts:0";
-+	};
-+};
-+
diff --git a/target/linux/brcm2708/patches-4.14/950-0261-usb-dwc_otg-fix-memory-corruption-in-dwc_otg-driver.patch b/target/linux/brcm2708/patches-4.14/950-0261-usb-dwc_otg-fix-memory-corruption-in-dwc_otg-driver.patch
deleted file mode 100644
index 0684cdfbc..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0261-usb-dwc_otg-fix-memory-corruption-in-dwc_otg-driver.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 118227d83e51c2b3e719589eb90846747eb06c62 Mon Sep 17 00:00:00 2001
-From: Paul Zimmerman <Paul.Zimmerman@synopsys.com>
-Date: Tue, 4 Feb 2014 11:21:24 -0800
-Subject: [PATCH 261/454] usb: dwc_otg: fix memory corruption in dwc_otg driver
-
-[Upstream commit 51b1b6491752ac066ee8d32cc66042fcc955fef6]
-
-The move from the staging tree to the main tree exposed a
-longstanding memory corruption bug in the dwc2 driver. The
-reordering of the driver initialization caused the dwc2 driver
-to corrupt the initialization data of the sdhci driver on the
-Raspberry Pi platform, which made the bug show up.
-
-The error is in calling to_usb_device(hsotg->dev), since ->dev
-is not a member of struct usb_device. The easiest fix is to
-just remove the offending code, since it is not really needed.
-
-Thanks to Stephen Warren for tracking down the cause of this.
-
-Reported-by: Andre Heider <a.heider@gmail.com>
-Tested-by: Stephen Warren <swarren@wwwdotorg.org>
-Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-[lukas: port from upstream dwc2 to out-of-tree dwc_otg driver]
-Signed-off-by: Lukas Wunner <lukas@wunner.de>
----
- drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 14 --------------
- 1 file changed, 14 deletions(-)
-
---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
-@@ -1012,25 +1012,11 @@ static void endpoint_disable(struct usb_
- static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
- {
- 	dwc_irqflags_t flags;
--	struct usb_device *udev = NULL;
--	int epnum = usb_endpoint_num(&ep->desc);
--	int is_out = usb_endpoint_dir_out(&ep->desc);
--	int is_control = usb_endpoint_xfer_control(&ep->desc);
- 	dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
--        struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep);
--
--	if (dev)
--		udev = to_usb_device(dev);
--	else
--		return;
- 
- 	DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
- 
- 	DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
--	usb_settoggle(udev, epnum, is_out, 0);
--	if (is_control)
--		usb_settoggle(udev, epnum, !is_out, 0);
--
- 	if (ep->hcpriv) {
- 		dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
- 	}
diff --git a/target/linux/brcm2708/patches-4.14/950-0262-config-Add-NFS_V4_1-support.patch b/target/linux/brcm2708/patches-4.14/950-0262-config-Add-NFS_V4_1-support.patch
deleted file mode 100644
index 14ac6e5a8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0262-config-Add-NFS_V4_1-support.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 6d0c5f3fd5c2cc778d764b6d8b56964e52f5b460 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Thu, 29 Mar 2018 16:01:37 +0100
-Subject: [PATCH 262/454] config: Add NFS_V4_1 support
-
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -1266,6 +1266,7 @@ CONFIG_NFS_FS=y
- CONFIG_NFS_V3_ACL=y
- CONFIG_NFS_V4=y
- CONFIG_NFS_SWAP=y
-+CONFIG_NFS_V4_1=y
- CONFIG_ROOT_NFS=y
- CONFIG_NFS_FSCACHE=y
- CONFIG_NFSD=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -1259,6 +1259,7 @@ CONFIG_NFS_FS=y
- CONFIG_NFS_V3_ACL=y
- CONFIG_NFS_V4=y
- CONFIG_NFS_SWAP=y
-+CONFIG_NFS_V4_1=y
- CONFIG_ROOT_NFS=y
- CONFIG_NFS_FSCACHE=y
- CONFIG_NFSD=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0263-config-Add-IPVLAN-module.patch b/target/linux/brcm2708/patches-4.14/950-0263-config-Add-IPVLAN-module.patch
deleted file mode 100644
index 1066d99e0..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0263-config-Add-IPVLAN-module.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 5c39dca835b0e45a59ff04b79a8accf1f64f26e1 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Thu, 29 Mar 2018 16:05:28 +0100
-Subject: [PATCH 263/454] config: Add IPVLAN module
-
----
- arch/arm/configs/bcm2709_defconfig | 2 ++
- arch/arm/configs/bcmrpi_defconfig  | 2 ++
- 2 files changed, 4 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -346,6 +346,7 @@ CONFIG_NET_ACT_SKBEDIT=m
- CONFIG_NET_ACT_CSUM=m
- CONFIG_BATMAN_ADV=m
- CONFIG_OPENVSWITCH=m
-+CONFIG_NET_L3_MASTER_DEV=y
- CONFIG_NET_PKTGEN=m
- CONFIG_HAMRADIO=y
- CONFIG_AX25=m
-@@ -436,6 +437,7 @@ CONFIG_BONDING=m
- CONFIG_DUMMY=m
- CONFIG_IFB=m
- CONFIG_MACVLAN=m
-+CONFIG_IPVLAN=m
- CONFIG_VXLAN=m
- CONFIG_NETCONSOLE=m
- CONFIG_TUN=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -341,6 +341,7 @@ CONFIG_NET_ACT_SKBEDIT=m
- CONFIG_NET_ACT_CSUM=m
- CONFIG_BATMAN_ADV=m
- CONFIG_OPENVSWITCH=m
-+CONFIG_NET_L3_MASTER_DEV=y
- CONFIG_NET_PKTGEN=m
- CONFIG_HAMRADIO=y
- CONFIG_AX25=m
-@@ -431,6 +432,7 @@ CONFIG_BONDING=m
- CONFIG_DUMMY=m
- CONFIG_IFB=m
- CONFIG_MACVLAN=m
-+CONFIG_IPVLAN=m
- CONFIG_VXLAN=m
- CONFIG_NETCONSOLE=m
- CONFIG_TUN=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0264-Add-overlay-for-JEDEC-SPI-NOR-flash.patch b/target/linux/brcm2708/patches-4.14/950-0264-Add-overlay-for-JEDEC-SPI-NOR-flash.patch
deleted file mode 100644
index 50c04764f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0264-Add-overlay-for-JEDEC-SPI-NOR-flash.patch
+++ /dev/null
@@ -1,352 +0,0 @@
-From 0222de711db11507773604084e20ad6d6960d30b Mon Sep 17 00:00:00 2001
-From: wavelet2 <a3d35232@btinternet.com>
-Date: Mon, 26 Mar 2018 21:05:10 +0100
-Subject: [PATCH 264/454] Add overlay for JEDEC SPI NOR flash
-
----
- arch/arm/boot/dts/overlays/Makefile           |   1 +
- arch/arm/boot/dts/overlays/README             |   9 +
- .../dts/overlays/jedec-spi-nor-overlay.dts    | 309 ++++++++++++++++++
- 3 files changed, 319 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -55,6 +55,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	iqaudio-dac.dtbo \
- 	iqaudio-dacplus.dtbo \
- 	iqaudio-digi-wm8804-audio.dtbo \
-+	jedec-spi-nor.dtbo \
- 	justboom-dac.dtbo \
- 	justboom-digi.dtbo \
- 	lirc-rpi.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -939,6 +939,15 @@ Params: card_name               Override
-                                 dai stream name.
- 
- 
-+Name:   jedec-spi-nor
-+Info:   Adds support for JEDEC-compliant SPI NOR flash devices.  (Note: The
-+        "jedec,spi-nor" kernel driver was formerly known as "m25p80".)
-+Load:   dtoverlay=jedec-spi-nor,<param>=<val>
-+Params: flash-spi<n>-<m>        Enables flash device on SPI<n>, CS#<m>.
-+        flash-fastr-spi<n>-<m>  Enables flash device with fast read capability
-+                                on SPI<n>, CS#<m>.
-+
-+
- Name:   justboom-dac
- Info:   Configures the JustBoom DAC HAT, Amp HAT, DAC Zero and Amp Zero audio
-         cards
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts
-@@ -0,0 +1,309 @@
-+// Overlay for JEDEC SPI-NOR Flash Devices (aka m25p80)
-+
-+// dtparams:
-+//     flash-spi<n>-<m>        - Enables flash device on SPI<n>, CS#<m>.
-+//     flash-fastr-spi<n>-<m>  - Enables flash device with fast read capability on SPI<n>, CS#<m>.
-+//
-+// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
-+//
-+// Example: A single flash device with fast read capability on SPI0, CS#0:
-+// dtoverlay=jedec-spi-nor:flash-fastr-spi0-0
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	// disable spi-dev on spi0.0
-+	fragment@0 {
-+		target = <&spidev0>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi0.1
-+	fragment@1 {
-+		target = <&spidev1>;
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi1.0
-+	fragment@2 {
-+		target-path = "spi1/spidev@0";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi1.1
-+	fragment@3 {
-+		target-path = "spi1/spidev@1";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi1.2
-+	fragment@4 {
-+		target-path = "spi1/spidev@2";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi2.0
-+	fragment@5 {
-+		target-path = "spi2/spidev@0";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi2.1
-+	fragment@6 {
-+		target-path = "spi2/spidev@1";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// disable spi-dev on spi2.2
-+	fragment@7 {
-+		target-path = "spi2/spidev@2";
-+		__dormant__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	// enable flash on spi0.0
-+	fragment@8 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			spi_nor_00: spi_nor@0 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "jedec,spi-nor";
-+				reg = <0>;
-+				spi-max-frequency = <500000>;
-+			};
-+		};
-+	};
-+
-+	// enable flash on spi0.1
-+	fragment@9 {
-+		target = <&spi0>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			spi_nor_01: spi_nor@1 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "jedec,spi-nor";
-+				reg = <1>;
-+				spi-max-frequency = <500000>;
-+			};
-+		};
-+	};
-+
-+	// enable flash on spi1.0
-+	fragment@10 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			spi_nor_10: spi_nor@0 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "jedec,spi-nor";
-+				reg = <0>;
-+				spi-max-frequency = <500000>;
-+			};
-+		};
-+	};
-+
-+	// enable flash on spi1.1
-+	fragment@11 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			spi_nor_11: spi_nor@1 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "jedec,spi-nor";
-+				reg = <1>;
-+				spi-max-frequency = <500000>;
-+			};
-+		};
-+	};
-+
-+	// enable flash on spi1.2
-+	fragment@12 {
-+		target = <&spi1>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			spi_nor_12: spi_nor@2 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "jedec,spi-nor";
-+				reg = <2>;
-+				spi-max-frequency = <500000>;
-+			};
-+		};
-+	};
-+
-+	// enable flash on spi2.0
-+	fragment@13 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			spi_nor_20: spi_nor@0 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "jedec,spi-nor";
-+				reg = <0>;
-+				spi-max-frequency = <500000>;
-+			};
-+		};
-+	};
-+
-+	// enable flash on spi2.1
-+	fragment@14 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			spi_nor_21: spi_nor@1 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "jedec,spi-nor";
-+				reg = <1>;
-+				spi-max-frequency = <500000>;
-+			};
-+		};
-+	};
-+
-+	// enable flash on spi2.2
-+	fragment@15 {
-+		target = <&spi2>;
-+		__dormant__ {
-+			status = "okay";
-+                        #address-cells = <1>;
-+                        #size-cells = <0>;
-+			spi_nor_22: spi_nor@2 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "jedec,spi-nor";
-+				reg = <2>;
-+				spi-max-frequency = <500000>;
-+			};
-+		};
-+	};
-+
-+	// Enable fast read for device on spi0.0.
-+	// Use default active low interrupt signalling.
-+	fragment@16 {
-+		target = <&spi_nor_00>;
-+		__dormant__ {
-+			m25p,fast-read;
-+		};
-+	};
-+
-+	// Enable fast read for device on spi0.1.
-+	// Use default active low interrupt signalling.
-+	fragment@17 {
-+		target = <&spi_nor_01>;
-+		__dormant__ {
-+			m25p,fast-read;
-+		};
-+	};
-+
-+	// Enable fast read for device on spi1.0.
-+	// Use default active low interrupt signalling.
-+	fragment@18 {
-+		target = <&spi_nor_10>;
-+		__dormant__ {
-+			m25p,fast-read;
-+		};
-+	};
-+
-+	// Enable fast read for device on spi1.1.
-+	// Use default active low interrupt signalling.
-+	fragment@19 {
-+		target = <&spi_nor_11>;
-+		__dormant__ {
-+			m25p,fast-read;
-+		};
-+	};
-+
-+	// Enable fast read for device on spi1.2.
-+	// Use default active low interrupt signalling.
-+	fragment@20 {
-+		target = <&spi_nor_12>;
-+		__dormant__ {
-+			m25p,fast-read;
-+		};
-+	};
-+
-+	// Enable fast read for device on spi2.0.
-+	// Use default active low interrupt signalling.
-+	fragment@21 {
-+		target = <&spi_nor_20>;
-+		__dormant__ {
-+			m25p,fast-read;
-+		};
-+	};
-+
-+	// Enable fast read for device on spi2.1.
-+	// Use default active low interrupt signalling.
-+	fragment@22 {
-+		target = <&spi_nor_21>;
-+		__dormant__ {
-+			m25p,fast-read;
-+		};
-+	};
-+
-+	// Enable fast read for device on spi2.2.
-+	// Use default active low interrupt signalling.
-+	fragment@23 {
-+		target = <&spi_nor_22>;
-+		__dormant__ {
-+			m25p,fast-read;
-+		};
-+	};
-+
-+	__overrides__ {
-+		flash-spi0-0       = <0>,"+0+8";
-+		flash-spi0-1       = <0>,"+1+9";
-+		flash-spi1-0       = <0>,"+2+10";
-+		flash-spi1-1       = <0>,"+3+11";
-+		flash-spi1-2       = <0>,"+4+12";
-+		flash-spi2-0       = <0>,"+5+13";
-+		flash-spi2-1       = <0>,"+6+14";
-+		flash-spi2-2       = <0>,"+7+15";
-+		flash-fastr-spi0-0 = <0>,"+0+8+16";
-+		flash-fastr-spi0-1 = <0>,"+1+9+17";
-+		flash-fastr-spi1-0 = <0>,"+2+10+18";
-+		flash-fastr-spi1-1 = <0>,"+3+11+19";
-+		flash-fastr-spi1-2 = <0>,"+4+12+20";
-+		flash-fastr-spi2-0 = <0>,"+5+13+21";
-+		flash-fastr-spi2-1 = <0>,"+6+14+22";
-+		flash-fastr-spi2-2 = <0>,"+7+15+23";
-+	};
-+};
-+
diff --git a/target/linux/brcm2708/patches-4.14/950-0265-net-lan78xx-Allow-for-VLAN-headers-in-timeout.patch b/target/linux/brcm2708/patches-4.14/950-0265-net-lan78xx-Allow-for-VLAN-headers-in-timeout.patch
deleted file mode 100644
index 46f8938e0..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0265-net-lan78xx-Allow-for-VLAN-headers-in-timeout.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 50340b55bb7af7c12259d3bce5da6ba969c58e00 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 4 Apr 2018 16:34:24 +0100
-Subject: [PATCH 265/454] net: lan78xx: Allow for VLAN headers in timeout.
-
-The frame abort timeout being set by lan78xx_set_rx_max_frame_length
-didn't account for any VLAN headers, resulting in very low
-throughput if used with tagged VLANs.
-Use VLAN_ETH_HLEN instead of ETH_HLEN to correct for this.
-
-See https://github.com/raspberrypi/linux/issues/2458
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2194,7 +2194,7 @@ static int lan78xx_change_mtu(struct net
- 	if ((ll_mtu % dev->maxpacket) == 0)
- 		return -EDOM;
- 
--	ret = lan78xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
-+	ret = lan78xx_set_rx_max_frame_length(dev, new_mtu + VLAN_ETH_HLEN);
- 
- 	netdev->mtu = new_mtu;
- 
-@@ -2483,7 +2483,8 @@ static int lan78xx_reset(struct lan78xx_
- 	buf |= FCT_TX_CTL_EN_;
- 	ret = lan78xx_write_reg(dev, FCT_TX_CTL, buf);
- 
--	ret = lan78xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
-+	ret = lan78xx_set_rx_max_frame_length(dev,
-+					      dev->net->mtu + VLAN_ETH_HLEN);
- 
- 	ret = lan78xx_read_reg(dev, MAC_RX, &buf);
- 	buf |= MAC_RX_RXEN_;
diff --git a/target/linux/brcm2708/patches-4.14/950-0266-config-Add-BT_HCIUART_BCM-y-and-SERIAL_DEV_BUS-m.patch b/target/linux/brcm2708/patches-4.14/950-0266-config-Add-BT_HCIUART_BCM-y-and-SERIAL_DEV_BUS-m.patch
deleted file mode 100644
index 35f767c16..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0266-config-Add-BT_HCIUART_BCM-y-and-SERIAL_DEV_BUS-m.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From b20f3d1dcd328fa6204f50f108d9e6ce9a0f7698 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 5 Apr 2018 12:49:00 +0100
-Subject: [PATCH 266/454] config: Add BT_HCIUART_BCM=y and SERIAL_DEV_BUS=m
-
-See: https://github.com/raspberrypi/linux/issues/2479
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 2 ++
- arch/arm/configs/bcmrpi_defconfig  | 2 ++
- 2 files changed, 4 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -374,6 +374,7 @@ CONFIG_BT_6LOWPAN=m
- CONFIG_BT_HCIBTUSB=m
- CONFIG_BT_HCIUART=m
- CONFIG_BT_HCIUART_3WIRE=y
-+CONFIG_BT_HCIUART_BCM=y
- CONFIG_BT_HCIBCM203X=m
- CONFIG_BT_HCIBPA10X=m
- CONFIG_BT_HCIBFUSB=m
-@@ -597,6 +598,7 @@ CONFIG_SERIAL_AMBA_PL011=y
- CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
- CONFIG_SERIAL_SC16IS7XX=m
- CONFIG_SERIAL_SC16IS7XX_SPI=y
-+CONFIG_SERIAL_DEV_BUS=m
- CONFIG_TTY_PRINTK=y
- CONFIG_HW_RANDOM=y
- CONFIG_RAW_DRIVER=y
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -369,6 +369,7 @@ CONFIG_BT_6LOWPAN=m
- CONFIG_BT_HCIBTUSB=m
- CONFIG_BT_HCIUART=m
- CONFIG_BT_HCIUART_3WIRE=y
-+CONFIG_BT_HCIUART_BCM=y
- CONFIG_BT_HCIBCM203X=m
- CONFIG_BT_HCIBPA10X=m
- CONFIG_BT_HCIBFUSB=m
-@@ -592,6 +593,7 @@ CONFIG_SERIAL_AMBA_PL011=y
- CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
- CONFIG_SERIAL_SC16IS7XX=m
- CONFIG_SERIAL_SC16IS7XX_SPI=y
-+CONFIG_SERIAL_DEV_BUS=m
- CONFIG_TTY_PRINTK=y
- CONFIG_HW_RANDOM=y
- CONFIG_RAW_DRIVER=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0267-arm64-Add-CONFIG_SERIAL_DEV_BUS-m-to-bcmrpi3_defconf.patch b/target/linux/brcm2708/patches-4.14/950-0267-arm64-Add-CONFIG_SERIAL_DEV_BUS-m-to-bcmrpi3_defconf.patch
deleted file mode 100644
index 8c9c7b145..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0267-arm64-Add-CONFIG_SERIAL_DEV_BUS-m-to-bcmrpi3_defconf.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From f7c841fc1c7b9269b1ee5a4167f8c45b6339c3de Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 5 Apr 2018 13:29:02 +0100
-Subject: [PATCH 267/454] arm64: Add CONFIG_SERIAL_DEV_BUS=m to
- bcmrpi3_defconfig
-
-See: https://github.com/raspberrypi/linux/issues/2479
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm64/configs/bcmrpi3_defconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -593,6 +593,7 @@ CONFIG_SERIAL_AMBA_PL011=y
- CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
- CONFIG_SERIAL_SC16IS7XX=m
- CONFIG_SERIAL_SC16IS7XX_SPI=y
-+CONFIG_SERIAL_DEV_BUS=m
- CONFIG_TTY_PRINTK=y
- CONFIG_HW_RANDOM=y
- CONFIG_RAW_DRIVER=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0268-lan78xx-Move-enabling-of-EEE-into-PHY-init-code.patch b/target/linux/brcm2708/patches-4.14/950-0268-lan78xx-Move-enabling-of-EEE-into-PHY-init-code.patch
deleted file mode 100644
index b0b75c18f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0268-lan78xx-Move-enabling-of-EEE-into-PHY-init-code.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From b3fe724c76c37a1a3b7744b616a275b44754505f Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 5 Apr 2018 14:46:11 +0100
-Subject: [PATCH 268/454] lan78xx: Move enabling of EEE into PHY init code
-
-Enable EEE mode as soon as possible after connecting to the PHY, and
-before phy_start. This avoids a second link negotiation, which speeds
-up booting and stops the interface failing to become ready.
-
-See: https://github.com/raspberrypi/linux/issues/2437
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 32 ++++++++++++++++----------------
- 1 file changed, 16 insertions(+), 16 deletions(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2073,6 +2073,22 @@ static int lan78xx_phy_init(struct lan78
- 	mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
- 	phydev->advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
- 
-+	if (of_property_read_bool(dev->udev->dev.of_node,
-+				  "microchip,eee-enabled")) {
-+		struct ethtool_eee edata;
-+		memset(&edata, 0, sizeof(edata));
-+		edata.cmd = ETHTOOL_SEEE;
-+		edata.advertised = ADVERTISED_1000baseT_Full |
-+				   ADVERTISED_100baseT_Full;
-+		edata.eee_enabled = true;
-+		edata.tx_lpi_enabled = true;
-+		if (of_property_read_u32(dev->udev->dev.of_node,
-+					 "microchip,tx-lpi-timer",
-+					 &edata.tx_lpi_timer))
-+			edata.tx_lpi_timer = 600; /* non-aggressive */
-+		(void)lan78xx_set_eee(dev->net, &edata);
-+	}
-+
- 	/* Set LED modes:
- 	 * led: 0=link/activity          1=link1000/activity
- 	 *      2=link100/activity       3=link10/activity
-@@ -2536,22 +2552,6 @@ static int lan78xx_open(struct net_devic
- 
- 	netif_dbg(dev, ifup, dev->net, "phy initialised successfully");
- 
--	if (of_property_read_bool(dev->udev->dev.of_node,
--				  "microchip,eee-enabled")) {
--		struct ethtool_eee edata;
--		memset(&edata, 0, sizeof(edata));
--		edata.cmd = ETHTOOL_SEEE;
--		edata.advertised = ADVERTISED_1000baseT_Full |
--				   ADVERTISED_100baseT_Full;
--		edata.eee_enabled = true;
--		edata.tx_lpi_enabled = true;
--		if (of_property_read_u32(dev->udev->dev.of_node,
--					 "microchip,tx-lpi-timer",
--					 &edata.tx_lpi_timer))
--			edata.tx_lpi_timer = 600; /* non-aggressive */
--		(void)lan78xx_set_eee(net, &edata);
--	}
--
- 	/* for Link Check */
- 	if (dev->urb_intr) {
- 		ret = usb_submit_urb(dev->urb_intr, GFP_KERNEL);
diff --git a/target/linux/brcm2708/patches-4.14/950-0269-net-lan78xx-Request-s-w-csum-check-on-VLAN-tagged-pa.patch b/target/linux/brcm2708/patches-4.14/950-0269-net-lan78xx-Request-s-w-csum-check-on-VLAN-tagged-pa.patch
deleted file mode 100644
index a95b82daf..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0269-net-lan78xx-Request-s-w-csum-check-on-VLAN-tagged-pa.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 44136672c6043943bcf0772bb0edfb6fc23354dc Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 9 Apr 2018 14:31:54 +0100
-Subject: [PATCH 269/454] net: lan78xx: Request s/w csum check on VLAN tagged
- packets.
-
-There appears to be some issue in the LAN78xx where the checksum
-computed on a VLAN tagged packet is incorrect, or at least not
-in the form that the kernel is after. This is most easily shown
-by pinging a device via a VLAN tagged interface and it will dump
-out the error message and stack trace from netdev_rx_csum_fault.
-It has also been seen with standard TCP and UDP packets.
-
-Until this is fully understood, request that the network stack
-computes the checksum on packets signalled as having a VLAN tag
-applied.
-
-See https://github.com/raspberrypi/linux/issues/2458
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2952,8 +2952,12 @@ static void lan78xx_rx_csum_offload(stru
- 				    struct sk_buff *skb,
- 				    u32 rx_cmd_a, u32 rx_cmd_b)
- {
-+	/* Checksum offload appears to be flawed if used with VLANs.
-+	 * Elect for sw checksum check instead.
-+	 */
- 	if (!(dev->net->features & NETIF_F_RXCSUM) ||
--	    unlikely(rx_cmd_a & RX_CMD_A_ICSM_)) {
-+	    unlikely(rx_cmd_a & RX_CMD_A_ICSM_) ||
-+	    (rx_cmd_a & RX_CMD_A_FVTG_)) {
- 		skb->ip_summed = CHECKSUM_NONE;
- 	} else {
- 		skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT_));
diff --git a/target/linux/brcm2708/patches-4.14/950-0270-net-lan78xx-Add-support-for-VLAN-filtering.patch b/target/linux/brcm2708/patches-4.14/950-0270-net-lan78xx-Add-support-for-VLAN-filtering.patch
deleted file mode 100644
index b3ffe3e79..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0270-net-lan78xx-Add-support-for-VLAN-filtering.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From c9101bf318db158e88e293aface9ce952657d958 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Tue, 10 Apr 2018 12:39:06 +0100
-Subject: [PATCH 270/454] net: lan78xx: Add support for VLAN filtering.
-
-HW_VLAN_CTAG_FILTER was partially implemented, but not fully to Linux.
-Complete the implementation of this.
-
-See #2458.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2275,7 +2275,7 @@ static int lan78xx_set_features(struct n
- 		pdata->rfe_ctl &= ~(RFE_CTL_ICMP_COE_ | RFE_CTL_IGMP_COE_);
- 	}
- 
--	if (features & NETIF_F_HW_VLAN_CTAG_RX)
-+	if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
- 		pdata->rfe_ctl |= RFE_CTL_VLAN_FILTER_;
- 	else
- 		pdata->rfe_ctl &= ~RFE_CTL_VLAN_FILTER_;
-@@ -2888,6 +2888,9 @@ static int lan78xx_bind(struct lan78xx_n
- 	if (DEFAULT_TSO_CSUM_ENABLE)
- 		dev->net->features |= NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_SG;
- 
-+	if (DEFAULT_VLAN_FILTER_ENABLE)
-+		dev->net->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
-+
- 	dev->net->hw_features = dev->net->features;
- 
- 	ret = lan78xx_setup_irq_domain(dev);
diff --git a/target/linux/brcm2708/patches-4.14/950-0271-net-lan78xx-Add-support-for-VLAN-tag-stripping.patch b/target/linux/brcm2708/patches-4.14/950-0271-net-lan78xx-Add-support-for-VLAN-tag-stripping.patch
deleted file mode 100644
index e1e5500cb..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0271-net-lan78xx-Add-support-for-VLAN-tag-stripping.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 9d4c65d0e7ebfe20bd24e65d52b1df56e90d498e Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Tue, 10 Apr 2018 15:27:51 +0100
-Subject: [PATCH 271/454] net: lan78xx: Add support for VLAN tag stripping.
-
-The chip supports stripping the VLAN tag and reporting it
-in metadata. Implement this as it also appears to solve the
-issues observed in checksum computation.
-
-See #2458.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -64,6 +64,7 @@
- #define DEFAULT_RX_CSUM_ENABLE		(true)
- #define DEFAULT_TSO_CSUM_ENABLE		(true)
- #define DEFAULT_VLAN_FILTER_ENABLE	(true)
-+#define DEFAULT_VLAN_RX_OFFLOAD		(true)
- #define TX_OVERHEAD			(8)
- #define RXW_PADDING			2
- 
-@@ -2275,6 +2276,11 @@ static int lan78xx_set_features(struct n
- 		pdata->rfe_ctl &= ~(RFE_CTL_ICMP_COE_ | RFE_CTL_IGMP_COE_);
- 	}
- 
-+	if (features & NETIF_F_HW_VLAN_CTAG_RX)
-+		pdata->rfe_ctl |= RFE_CTL_VLAN_STRIP_;
-+	else
-+		pdata->rfe_ctl &= ~RFE_CTL_VLAN_STRIP_;
-+
- 	if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
- 		pdata->rfe_ctl |= RFE_CTL_VLAN_FILTER_;
- 	else
-@@ -2888,6 +2894,9 @@ static int lan78xx_bind(struct lan78xx_n
- 	if (DEFAULT_TSO_CSUM_ENABLE)
- 		dev->net->features |= NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_SG;
- 
-+	if (DEFAULT_VLAN_RX_OFFLOAD)
-+		dev->net->features |= NETIF_F_HW_VLAN_CTAG_RX;
-+
- 	if (DEFAULT_VLAN_FILTER_ENABLE)
- 		dev->net->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
- 
-@@ -2968,6 +2977,16 @@ static void lan78xx_rx_csum_offload(stru
- 	}
- }
- 
-+static void lan78xx_rx_vlan_offload(struct lan78xx_net *dev,
-+				    struct sk_buff *skb,
-+				    u32 rx_cmd_a, u32 rx_cmd_b)
-+{
-+	if ((dev->net->features & NETIF_F_HW_VLAN_CTAG_RX) &&
-+	    (rx_cmd_a & RX_CMD_A_FVTG_))
-+		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
-+				       (rx_cmd_b & 0xffff));
-+}
-+
- static void lan78xx_skb_return(struct lan78xx_net *dev, struct sk_buff *skb)
- {
- 	int		status;
-@@ -3032,6 +3051,8 @@ static int lan78xx_rx(struct lan78xx_net
- 			if (skb->len == size) {
- 				lan78xx_rx_csum_offload(dev, skb,
- 							rx_cmd_a, rx_cmd_b);
-+				lan78xx_rx_vlan_offload(dev, skb,
-+							rx_cmd_a, rx_cmd_b);
- 
- 				skb_trim(skb, skb->len - 4); /* remove fcs */
- 				skb->truesize = size + sizeof(struct sk_buff);
-@@ -3050,6 +3071,7 @@ static int lan78xx_rx(struct lan78xx_net
- 			skb_set_tail_pointer(skb2, size);
- 
- 			lan78xx_rx_csum_offload(dev, skb2, rx_cmd_a, rx_cmd_b);
-+			lan78xx_rx_vlan_offload(dev, skb2, rx_cmd_a, rx_cmd_b);
- 
- 			skb_trim(skb2, skb2->len - 4); /* remove fcs */
- 			skb2->truesize = size + sizeof(struct sk_buff);
diff --git a/target/linux/brcm2708/patches-4.14/950-0272-net-lan78xx-Reduce-s-w-csum-check-on-VLANs.patch b/target/linux/brcm2708/patches-4.14/950-0272-net-lan78xx-Reduce-s-w-csum-check-on-VLANs.patch
deleted file mode 100644
index 3582c532f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0272-net-lan78xx-Reduce-s-w-csum-check-on-VLANs.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 126c6760f56d2d7a82c605a54c402a886ae9b5bf Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Tue, 10 Apr 2018 13:08:36 +0100
-Subject: [PATCH 272/454] net: lan78xx: Reduce s/w csum check on VLANs
-
-With HW_VLAN_CTAG_RX enabled we don't observe the checksum
-issue, so amend the workaround to only drop back to s/w
-checksums if VLAN offload is disabled.
-
-See #2458.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2964,12 +2964,13 @@ static void lan78xx_rx_csum_offload(stru
- 				    struct sk_buff *skb,
- 				    u32 rx_cmd_a, u32 rx_cmd_b)
- {
--	/* Checksum offload appears to be flawed if used with VLANs.
--	 * Elect for sw checksum check instead.
-+	/* HW Checksum offload appears to be flawed if used when not stripping
-+	 * VLAN headers.
- 	 */
- 	if (!(dev->net->features & NETIF_F_RXCSUM) ||
- 	    unlikely(rx_cmd_a & RX_CMD_A_ICSM_) ||
--	    (rx_cmd_a & RX_CMD_A_FVTG_)) {
-+	    ((rx_cmd_a & RX_CMD_A_FVTG_) &&
-+	     !(dev->net->features & NETIF_F_HW_VLAN_CTAG_RX))) {
- 		skb->ip_summed = CHECKSUM_NONE;
- 	} else {
- 		skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT_));
diff --git a/target/linux/brcm2708/patches-4.14/950-0273-config-Enable-the-DS1621-I2C-temperature-sensor.patch b/target/linux/brcm2708/patches-4.14/950-0273-config-Enable-the-DS1621-I2C-temperature-sensor.patch
deleted file mode 100644
index 6f73a2b40..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0273-config-Enable-the-DS1621-I2C-temperature-sensor.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From d36a5cf6fe3a4b5116cd68338f11590283d497d2 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sun, 15 Apr 2018 10:35:22 +0100
-Subject: [PATCH 273/454] config: Enable the DS1621 I2C temperature sensor
-
-See: https://github.com/raspberrypi/linux/issues/2509
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -647,6 +647,7 @@ CONFIG_POWER_RESET=y
- CONFIG_POWER_RESET_GPIO=y
- CONFIG_BATTERY_DS2760=m
- CONFIG_HWMON=m
-+CONFIG_SENSORS_DS1621=m
- CONFIG_SENSORS_JC42=m
- CONFIG_SENSORS_LM75=m
- CONFIG_SENSORS_SHT21=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -640,6 +640,7 @@ CONFIG_POWER_RESET=y
- CONFIG_POWER_RESET_GPIO=y
- CONFIG_BATTERY_DS2760=m
- CONFIG_HWMON=m
-+CONFIG_SENSORS_DS1621=m
- CONFIG_SENSORS_JC42=m
- CONFIG_SENSORS_LM75=m
- CONFIG_SENSORS_SHT21=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0274-overlays-Add-ds1621-to-the-i2c-sensor-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0274-overlays-Add-ds1621-to-the-i2c-sensor-overlay.patch
deleted file mode 100644
index fb0298c52..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0274-overlays-Add-ds1621-to-the-i2c-sensor-overlay.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From 3c258618cbc0cddb7076b61a08755aa4f73d27db Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sun, 15 Apr 2018 10:36:15 +0100
-Subject: [PATCH 274/454] overlays: Add ds1621 to the i2c-sensor overlay
-
-The ds1621 enables the Dallas Semiconductors DS1621 temperature
-sensor.
-
-See: https://github.com/raspberrypi/linux/issues/2509
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README             | 15 +++++++++------
- .../boot/dts/overlays/i2c-sensor-overlay.dts  | 19 ++++++++++++++++++-
- 2 files changed, 27 insertions(+), 7 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -821,8 +821,8 @@ Name:   i2c-sensor
- Info:   Adds support for a number of I2C barometric pressure and temperature
-         sensors on i2c_arm
- Load:   dtoverlay=i2c-sensor,<param>=<val>
--Params: addr                    Set the address for the BME280, BMP280, TMP102,
--                                HDC100X, LM75 or SHT3x
-+Params: addr                    Set the address for the BME280, BMP280, DS1621,
-+                                HDC100X, LM75, SHT3x or TMP102
- 
-         bme280                  Select the Bosch Sensortronic BME280
-                                 Valid addresses 0x76-0x77, default 0x76
-@@ -834,6 +834,9 @@ Params: addr                    Set the
-         bmp280                  Select the Bosch Sensortronic BMP280
-                                 Valid addresses 0x76-0x77, default 0x76
- 
-+        ds1621                  Select the Dallas Semiconductors DS1621 temp
-+                                sensor. Valid addresses 0x48-9x4f, default 0x48
-+
-         hdc100x                 Select the Texas Instruments HDC100x temp sensor
-                                 Valid addresses 0x40-0x43, default 0x40
- 
-@@ -844,6 +847,10 @@ Params: addr                    Set the
- 
-         lm75addr                Deprecated - use addr parameter instead
- 
-+        sht3x                   Select the Sensiron SHT3x temperature and
-+                                humidity sensor. Valid addresses 0x44-0x45,
-+                                default 0x44
-+
-         si7020                  Select the Silicon Labs Si7013/20/21 humidity/
-                                 temperature sensor
- 
-@@ -856,10 +863,6 @@ Params: addr                    Set the
-         veml6070                Select the Vishay VEML6070 ultraviolet light
-                                 sensor
- 
--        sht3x                   Select the Sensiron SHT3x temperature and
--                                humidity sensor. Valid addresses 0x44-0x45,
--                                default 0x44
--
- 
- Name:   i2c0-bcm2708
- Info:   Enable the i2c_bcm2708 driver for the i2c0 bus. Not all pin combinations
---- a/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts
-@@ -186,9 +186,25 @@
- 		};
- 	};
- 
-+	fragment@12 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ds1621: ds1621@48 {
-+				compatible = "ds1621";
-+				reg = <0x48>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
- 	__overrides__ {
- 		addr =  <&bme280>,"reg:0", <&bmp280>,"reg:0", <&tmp102>,"reg:0",
--			<&lm75>,"reg:0", <&hdc100x>,"reg:0", <&sht3x>,"reg:0";
-+			<&lm75>,"reg:0", <&hdc100x>,"reg:0", <&sht3x>,"reg:0",
-+			<&ds1621>,"reg:0";
- 		bme280 = <0>,"+0";
- 		bmp085 = <0>,"+1";
- 		bmp180 = <0>,"+2";
-@@ -202,5 +218,6 @@
- 		tsl4531 = <0>,"+9";
- 		veml6070 = <0>,"+10";
- 		sht3x = <0>,"+11";
-+		ds1621 = <0>,"+12";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0275-overlays-Fix-typo-in-README.patch b/target/linux/brcm2708/patches-4.14/950-0275-overlays-Fix-typo-in-README.patch
deleted file mode 100644
index a7b389305..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0275-overlays-Fix-typo-in-README.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From b5b405c12536e216476598de4ff56551bf56ad6e Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 17 Apr 2018 08:59:47 +0100
-Subject: [PATCH 275/454] overlays: Fix typo in README
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -835,7 +835,7 @@ Params: addr                    Set the
-                                 Valid addresses 0x76-0x77, default 0x76
- 
-         ds1621                  Select the Dallas Semiconductors DS1621 temp
--                                sensor. Valid addresses 0x48-9x4f, default 0x48
-+                                sensor. Valid addresses 0x48-0x4f, default 0x48
- 
-         hdc100x                 Select the Texas Instruments HDC100x temp sensor
-                                 Valid addresses 0x40-0x43, default 0x40
diff --git a/target/linux/brcm2708/patches-4.14/950-0276-configs-Add-CONFIG_BCM2835_DEVGPIOMEM-for-aarch64.patch b/target/linux/brcm2708/patches-4.14/950-0276-configs-Add-CONFIG_BCM2835_DEVGPIOMEM-for-aarch64.patch
deleted file mode 100644
index 889f9ffae..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0276-configs-Add-CONFIG_BCM2835_DEVGPIOMEM-for-aarch64.patch
+++ /dev/null
@@ -1,264 +0,0 @@
-From 0bb8b8d035fb67a198fa4502e4b587e2f324bea6 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 17 Apr 2018 09:16:46 +0100
-Subject: [PATCH 276/454] configs: Add CONFIG_BCM2835_DEVGPIOMEM for aarch64
-
-See: https://github.com/raspberrypi/linux/issues/2514
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm64/configs/bcmrpi3_defconfig | 73 +++++++++++-----------------
- 1 file changed, 28 insertions(+), 45 deletions(-)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -352,20 +352,6 @@ CONFIG_YAM=m
- CONFIG_CAN=m
- CONFIG_CAN_VCAN=m
- CONFIG_CAN_MCP251X=m
--CONFIG_IRDA=m
--CONFIG_IRLAN=m
--CONFIG_IRNET=m
--CONFIG_IRCOMM=m
--CONFIG_IRDA_ULTRA=y
--CONFIG_IRDA_CACHE_LAST_LSAP=y
--CONFIG_IRDA_FAST_RR=y
--CONFIG_IRTTY_SIR=m
--CONFIG_KINGSUN_DONGLE=m
--CONFIG_KSDAZZLE_DONGLE=m
--CONFIG_KS959_DONGLE=m
--CONFIG_USB_IRDA=m
--CONFIG_SIGMATEL_FIR=m
--CONFIG_MCS_FIR=m
- CONFIG_BT=m
- CONFIG_BT_RFCOMM=m
- CONFIG_BT_RFCOMM_TTY=y
-@@ -425,7 +411,6 @@ CONFIG_ISCSI_TCP=m
- CONFIG_ISCSI_BOOT_SYSFS=m
- CONFIG_MD=y
- CONFIG_MD_LINEAR=m
--CONFIG_MD_RAID0=m
- CONFIG_BLK_DEV_DM=m
- CONFIG_DM_CRYPT=m
- CONFIG_DM_SNAPSHOT=m
-@@ -445,7 +430,6 @@ CONFIG_NETCONSOLE=m
- CONFIG_TUN=m
- CONFIG_VETH=m
- CONFIG_ENC28J60=m
--CONFIG_QCA7000=m
- CONFIG_MDIO_BITBANG=m
- CONFIG_PPP=m
- CONFIG_PPP_BSDCOMP=m
-@@ -466,6 +450,7 @@ CONFIG_USB_KAWETH=m
- CONFIG_USB_PEGASUS=m
- CONFIG_USB_RTL8150=m
- CONFIG_USB_RTL8152=m
-+CONFIG_USB_LAN78XX=y
- CONFIG_USB_USBNET=y
- CONFIG_USB_NET_AX8817X=m
- CONFIG_USB_NET_AX88179_178A=m
-@@ -479,7 +464,6 @@ CONFIG_USB_NET_SR9700=m
- CONFIG_USB_NET_SR9800=m
- CONFIG_USB_NET_SMSC75XX=m
- CONFIG_USB_NET_SMSC95XX=y
--CONFIG_USB_LAN78XX=y
- CONFIG_USB_NET_GL620A=m
- CONFIG_USB_NET_NET1080=m
- CONFIG_USB_NET_PLUSB=m
-@@ -538,7 +522,6 @@ CONFIG_IEEE802154_AT86RF230=m
- CONFIG_IEEE802154_MRF24J40=m
- CONFIG_IEEE802154_CC2520=m
- CONFIG_INPUT_POLLDEV=m
--# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
- CONFIG_INPUT_JOYDEV=m
- CONFIG_INPUT_EVDEV=m
- # CONFIG_KEYBOARD_ATKBD is not set
-@@ -576,7 +559,7 @@ CONFIG_GAMEPORT_NS558=m
- CONFIG_GAMEPORT_L4=m
- CONFIG_BRCM_CHAR_DRIVERS=y
- CONFIG_BCM_VCIO=y
--# CONFIG_BCM2835_DEVGPIOMEM is not set
-+CONFIG_BCM2835_DEVGPIOMEM=y
- # CONFIG_BCM2835_SMI_DEV is not set
- # CONFIG_LEGACY_PTYS is not set
- CONFIG_SERIAL_8250=y
-@@ -615,7 +598,6 @@ CONFIG_GPIO_BCM_EXP=y
- CONFIG_GPIO_BCM_VIRT=y
- CONFIG_GPIO_ARIZONA=m
- CONFIG_GPIO_STMPE=y
--CONFIG_GPIO_MCP23S08=m
- CONFIG_W1=m
- CONFIG_W1_MASTER_DS2490=m
- CONFIG_W1_MASTER_DS2482=m
-@@ -633,7 +615,6 @@ CONFIG_W1_SLAVE_DS2760=m
- CONFIG_W1_SLAVE_DS2780=m
- CONFIG_W1_SLAVE_DS2781=m
- CONFIG_W1_SLAVE_DS28E04=m
--CONFIG_W1_SLAVE_BQ27000=m
- CONFIG_POWER_RESET_GPIO=y
- CONFIG_BATTERY_DS2760=m
- CONFIG_HWMON=m
-@@ -645,19 +626,11 @@ CONFIG_THERMAL=y
- CONFIG_BCM2835_THERMAL=y
- CONFIG_WATCHDOG=y
- CONFIG_BCM2835_WDT=y
--CONFIG_UCB1400_CORE=m
- CONFIG_MFD_STMPE=y
- CONFIG_STMPE_SPI=y
- CONFIG_MFD_ARIZONA_I2C=m
- CONFIG_MFD_ARIZONA_SPI=m
- CONFIG_MFD_WM5102=y
--CONFIG_MEDIA_SUPPORT=m
--CONFIG_MEDIA_CAMERA_SUPPORT=y
--CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
--CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
--CONFIG_MEDIA_RADIO_SUPPORT=y
--CONFIG_MEDIA_RC_SUPPORT=y
--CONFIG_MEDIA_CONTROLLER=y
- CONFIG_LIRC=m
- CONFIG_RC_DEVICES=y
- CONFIG_RC_ATI_REMOTE=m
-@@ -669,6 +642,12 @@ CONFIG_IR_IGUANA=m
- CONFIG_IR_TTUSBIR=m
- CONFIG_RC_LOOPBACK=m
- CONFIG_IR_GPIO_CIR=m
-+CONFIG_MEDIA_SUPPORT=m
-+CONFIG_MEDIA_CAMERA_SUPPORT=y
-+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-+CONFIG_MEDIA_RADIO_SUPPORT=y
-+CONFIG_MEDIA_CONTROLLER=y
- CONFIG_MEDIA_USB_SUPPORT=y
- CONFIG_USB_VIDEO_CLASS=m
- CONFIG_USB_M5602=m
-@@ -729,7 +708,6 @@ CONFIG_VIDEO_PVRUSB2=m
- CONFIG_VIDEO_HDPVR=m
- CONFIG_VIDEO_USBVISION=m
- CONFIG_VIDEO_STK1160_COMMON=m
--CONFIG_VIDEO_STK1160_AC97=y
- CONFIG_VIDEO_GO7007=m
- CONFIG_VIDEO_GO7007_USB=m
- CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
-@@ -815,9 +793,9 @@ CONFIG_VIDEO_OV7640=m
- CONFIG_VIDEO_MT9V011=m
- CONFIG_DRM=m
- CONFIG_DRM_LOAD_EDID_FIRMWARE=y
-+CONFIG_DRM_UDL=m
- CONFIG_DRM_PANEL_SIMPLE=m
- CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
--CONFIG_DRM_UDL=m
- CONFIG_DRM_VC4=m
- CONFIG_FB=y
- CONFIG_FB_BCM2708=y
-@@ -833,19 +811,15 @@ CONFIG_LOGO=y
- # CONFIG_LOGO_LINUX_VGA16 is not set
- CONFIG_SOUND=y
- CONFIG_SND=m
-+CONFIG_SND_HRTIMER=m
- CONFIG_SND_SEQUENCER=m
- CONFIG_SND_SEQ_DUMMY=m
--CONFIG_SND_MIXER_OSS=m
--CONFIG_SND_PCM_OSS=m
--CONFIG_SND_SEQUENCER_OSS=y
--CONFIG_SND_HRTIMER=m
- CONFIG_SND_DUMMY=m
- CONFIG_SND_ALOOP=m
- CONFIG_SND_VIRMIDI=m
- CONFIG_SND_MTPAV=m
- CONFIG_SND_SERIAL_U16550=m
- CONFIG_SND_MPU401=m
--CONFIG_SND_BCM2835=m
- CONFIG_SND_USB_AUDIO=m
- CONFIG_SND_USB_UA101=m
- CONFIG_SND_USB_CAIAQ=m
-@@ -874,7 +848,6 @@ CONFIG_SND_SOC_AK4554=m
- CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
--CONFIG_SOUND_PRIME=m
- CONFIG_HIDRAW=y
- CONFIG_UHID=m
- CONFIG_HID_A4TECH=m
-@@ -1030,12 +1003,14 @@ CONFIG_USB_UEAGLEATM=m
- CONFIG_USB_XUSBATM=m
- CONFIG_MMC=y
- CONFIG_MMC_BLOCK_MINORS=32
--CONFIG_MMC_BCM2835=y
-+CONFIG_MMC_BCM2835_MMC=y
- CONFIG_MMC_BCM2835_DMA=y
- CONFIG_MMC_BCM2835_SDHOST=y
- CONFIG_MMC_SDHCI=y
- CONFIG_MMC_SDHCI_PLTFM=y
-+CONFIG_MMC_SDHCI_IPROC=m
- CONFIG_MMC_SPI=m
-+CONFIG_MMC_BCM2835=y
- CONFIG_LEDS_CLASS=y
- CONFIG_LEDS_GPIO=y
- CONFIG_LEDS_TRIGGER_TIMER=y
-@@ -1089,6 +1064,20 @@ CONFIG_DMA_BCM2708=y
- CONFIG_UIO=m
- CONFIG_UIO_PDRV_GENIRQ=m
- CONFIG_STAGING=y
-+CONFIG_IRDA=m
-+CONFIG_IRLAN=m
-+CONFIG_IRNET=m
-+CONFIG_IRCOMM=m
-+CONFIG_IRDA_ULTRA=y
-+CONFIG_IRDA_CACHE_LAST_LSAP=y
-+CONFIG_IRDA_FAST_RR=y
-+CONFIG_IRTTY_SIR=m
-+CONFIG_KINGSUN_DONGLE=m
-+CONFIG_KSDAZZLE_DONGLE=m
-+CONFIG_KS959_DONGLE=m
-+CONFIG_USB_IRDA=m
-+CONFIG_SIGMATEL_FIR=m
-+CONFIG_MCS_FIR=m
- CONFIG_PRISM2_USB=m
- CONFIG_R8712U=m
- CONFIG_R8188EU=m
-@@ -1097,9 +1086,7 @@ CONFIG_SPEAKUP=m
- CONFIG_SPEAKUP_SYNTH_SOFT=m
- CONFIG_STAGING_MEDIA=y
- CONFIG_LIRC_STAGING=y
--CONFIG_LIRC_IMON=m
- CONFIG_LIRC_RPI=m
--CONFIG_LIRC_SASEM=m
- CONFIG_FB_TFT=m
- CONFIG_FB_TFT_AGM1264K_FL=m
- CONFIG_FB_TFT_BD663474=m
-@@ -1130,6 +1117,7 @@ CONFIG_FB_TFT_UPD161704=m
- CONFIG_FB_TFT_WATTEROTT=m
- CONFIG_FB_FLEX=m
- CONFIG_FB_TFT_FBTFT_DEVICE=m
-+CONFIG_SND_BCM2835=m
- CONFIG_MAILBOX=y
- CONFIG_BCM2835_MBOX=y
- # CONFIG_IOMMU_SUPPORT is not set
-@@ -1216,7 +1204,6 @@ CONFIG_CIFS_XATTR=y
- CONFIG_CIFS_POSIX=y
- CONFIG_CIFS_ACL=y
- CONFIG_CIFS_DFS_UPCALL=y
--CONFIG_CIFS_SMB2=y
- CONFIG_CIFS_FSCACHE=y
- CONFIG_9P_FS=m
- CONFIG_9P_FS_POSIX_ACL=y
-@@ -1263,13 +1250,11 @@ CONFIG_PRINTK_TIME=y
- CONFIG_BOOT_PRINTK_DELAY=y
- CONFIG_DEBUG_MEMORY_INIT=y
- CONFIG_DETECT_HUNG_TASK=y
--CONFIG_TIMER_STATS=y
- CONFIG_LATENCYTOP=y
- CONFIG_IRQSOFF_TRACER=y
- CONFIG_SCHED_TRACER=y
- CONFIG_STACK_TRACER=y
- CONFIG_BLK_DEV_IO_TRACE=y
--# CONFIG_KPROBE_EVENT is not set
- CONFIG_FUNCTION_PROFILER=y
- CONFIG_KGDB=y
- CONFIG_KGDB_KDB=y
-@@ -1287,5 +1272,3 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=m
- CONFIG_ARM64_CRYPTO=y
- CONFIG_CRC_ITU_T=y
- CONFIG_LIBCRC32C=y
--CONFIG_MMC_BCM2835_MMC=y
--CONFIG_MMC_SDHCI_IPROC=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0277-overlays-Add-combine-option-to-i2c-overlays.patch b/target/linux/brcm2708/patches-4.14/950-0277-overlays-Add-combine-option-to-i2c-overlays.patch
deleted file mode 100644
index 3981686cc..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0277-overlays-Add-combine-option-to-i2c-overlays.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From 1b02fe3ab446613cadcfac08d611b90becb02189 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 18 Apr 2018 17:04:23 +0100
-Subject: [PATCH 277/454] overlays: Add 'combine' option to i2c overlays
-
-The i2c0-bcm2708 and i2c1-bcm2708 overlays allow the I2C pin usage to
-be changed. The names also suggest they revert to the old i2c_bcm2708
-driver, but they don't. The newer i2c_bcm2835 driver forces
-transactions to be combined where possible, but this breaks some
-devices.
-
-Add an option to disable transaction combining, which is currently
-implemented by reverting to the old driver.
-
-See: https://github.com/raspberrypi/firmware/issues/828
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README                   | 12 ++++++++++--
- arch/arm/boot/dts/overlays/i2c0-bcm2708-overlay.dts |  8 ++++++++
- arch/arm/boot/dts/overlays/i2c1-bcm2708-overlay.dts |  9 +++++++++
- 3 files changed, 27 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -865,8 +865,9 @@ Params: addr                    Set the
- 
- 
- Name:   i2c0-bcm2708
--Info:   Enable the i2c_bcm2708 driver for the i2c0 bus. Not all pin combinations
--        are usable on all platforms.
-+Info:   Change i2c0 pin usage. Not all pin combinations are usable on all
-+        platforms - platforms other then Compute Modules can only use this
-+        to disable transaction combining.
- Load:   dtoverlay=i2c0-bcm2708,<param>=<val>
- Params: sda0_pin                GPIO pin for SDA0 (deprecated - use pins_*)
-         scl0_pin                GPIO pin for SCL0 (deprecated - use pins_*)
-@@ -874,15 +875,22 @@ Params: sda0_pin                GPIO pin
-         pins_28_29              Use pins 28 and 29
-         pins_44_45              Use pins 44 and 45
-         pins_46_47              Use pins 46 and 47
-+        combine                 Allow transactions to be combined (default
-+                                "yes")
- 
- 
- Name:   i2c1-bcm2708
-+Info:   Change i2c1 pin usage. Not all pin combinations are usable on all
-+        platforms - platforms other then Compute Modules can only use this
-+        to disable transaction combining.
- Info:   Enable the i2c_bcm2708 driver for the i2c1 bus
- Load:   dtoverlay=i2c1-bcm2708,<param>=<val>
- Params: sda1_pin                GPIO pin for SDA1 (2 or 44 - default 2)
-         scl1_pin                GPIO pin for SCL1 (3 or 45 - default 3)
-         pin_func                Alternative pin function (4 (alt0), 6 (alt2) -
-                                 default 4)
-+        combine                 Allow transactions to be combined (default
-+                                "yes")
- 
- 
- Name:   i2s-gpio28-31
---- a/arch/arm/boot/dts/overlays/i2c0-bcm2708-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/i2c0-bcm2708-overlay.dts
-@@ -50,6 +50,13 @@
-       };
-    };
- 
-+   fragment@5 {
-+      target = <&i2c0>;
-+      __dormant__ {
-+         compatible = "brcm,bcm2708-i2c";
-+      };
-+   };
-+
-    __overrides__ {
-       sda0_pin = <&frag1>,"brcm,pins:0";
-       scl0_pin = <&frag1>,"brcm,pins:4";
-@@ -57,5 +64,6 @@
-       pins_28_29 = <0>,"-1+2-3-4";
-       pins_44_45 = <0>,"-1-2+3-4";
-       pins_46_47 = <0>,"-1-2-3+4";
-+      combine = <0>, "!5";
-    };
- };
---- a/arch/arm/boot/dts/overlays/i2c1-bcm2708-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/i2c1-bcm2708-overlay.dts
-@@ -26,9 +26,18 @@
-          brcm,function = <4>; /* alt 0 */
-       };
-    };
-+
-+   fragment@2 {
-+      target = <&i2c1>;
-+      __dormant__ {
-+         compatible = "brcm,bcm2708-i2c";
-+      };
-+   };
-+
-    __overrides__ {
-       sda1_pin = <&pins>,"brcm,pins:0";
-       scl1_pin = <&pins>,"brcm,pins:4";
-       pin_func = <&pins>,"brcm,function:0";
-+      combine = <0>, "!2";
-    };
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0278-Prevent-voltage-low-warnings-from-filling-log.patch b/target/linux/brcm2708/patches-4.14/950-0278-Prevent-voltage-low-warnings-from-filling-log.patch
deleted file mode 100644
index f83d6704d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0278-Prevent-voltage-low-warnings-from-filling-log.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From cecce8a9e798fbe8571381b6f9f69fd7a0defa37 Mon Sep 17 00:00:00 2001
-From: James Hughes <james.hughes@raspberrypi.org>
-Date: Wed, 18 Apr 2018 13:02:57 +0100
-Subject: [PATCH 278/454] Prevent voltage low warnings from filling log
-
-Although the correct fix for low voltage warnings is to
-improve the power supply, the current implementation
-of the detection can fill the log if the warning
-happens freqently. This replaces the logging with
-slightly custom ratelimited logging.
-
-Signed-off-by: James Hughes <james.hughes@raspberrypi.org>
----
- drivers/firmware/raspberrypi.c | 40 ++++++++++++++++++++++++++++++++--
- 1 file changed, 38 insertions(+), 2 deletions(-)
-
---- a/drivers/firmware/raspberrypi.c
-+++ b/drivers/firmware/raspberrypi.c
-@@ -24,6 +24,38 @@
- 
- #define UNDERVOLTAGE_BIT		BIT(0)
- 
-+
-+/*
-+ * This section defines some rate limited logging that prevent
-+ * repeated messages at much lower Hz than the default kernel settings.
-+ * It's usually 5s, this is 5 minutes.
-+ * Burst 3 means you may get three messages 'quickly', before
-+ * the ratelimiting kicks in.
-+ */
-+#define LOCAL_RATELIMIT_INTERVAL (5 * 60 * HZ)
-+#define LOCAL_RATELIMIT_BURST 3
-+
-+#ifdef CONFIG_PRINTK
-+#define printk_ratelimited_local(fmt, ...)	\
-+({						\
-+	static DEFINE_RATELIMIT_STATE(_rs,	\
-+		LOCAL_RATELIMIT_INTERVAL,	\
-+		LOCAL_RATELIMIT_BURST);		\
-+						\
-+	if (__ratelimit(&_rs))			\
-+		printk(fmt, ##__VA_ARGS__);	\
-+})
-+#else
-+#define printk_ratelimited_local(fmt, ...)	\
-+	no_printk(fmt, ##__VA_ARGS__)
-+#endif
-+
-+#define pr_crit_ratelimited_local(fmt, ...)              \
-+	printk_ratelimited_local(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__)
-+#define pr_info_ratelimited_local(fmt, ...)              \
-+	printk_ratelimited_local(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__)
-+
-+
- struct rpi_firmware {
- 	struct mbox_client cl;
- 	struct mbox_chan *chan; /* The property channel. */
-@@ -216,9 +248,13 @@ static int rpi_firmware_get_throttled(st
- 
- 	if (new_uv != old_uv) {
- 		if (new_uv)
--			pr_crit("Under-voltage detected! (0x%08x)\n", *value);
-+			pr_crit_ratelimited_local(
-+				"Under-voltage detected! (0x%08x)\n",
-+				 *value);
- 		else
--			pr_info("Voltage normalised (0x%08x)\n", *value);
-+			pr_info_ratelimited_local(
-+				"Voltage normalised (0x%08x)\n",
-+				 *value);
- 	}
- 
- 	sysfs_notify(&fw->cl.dev->kobj, NULL, "get_throttled");
diff --git a/target/linux/brcm2708/patches-4.14/950-0279-BCM270X_DT-Add-sdio_overclock-parameter.patch b/target/linux/brcm2708/patches-4.14/950-0279-BCM270X_DT-Add-sdio_overclock-parameter.patch
deleted file mode 100644
index fe1a31ace..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0279-BCM270X_DT-Add-sdio_overclock-parameter.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 3c015b0f686824f1b0815cc028665304ab0981d6 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 24 Apr 2018 14:28:33 +0100
-Subject: [PATCH 279/454] BCM270X_DT: Add sdio_overclock parameter
-
-The Arasan MMC interface is used on some RPis to drive the SDIO
-link to the WiFi controller. The downstream bcm2835-mmc driver,
-like the bcm2835-sdhost driver, can be over- (or under-) clocked.
-Add a common parameter - sdio_overclock - to all DTBs to control it.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm2708-rpi.dtsi | 1 +
- arch/arm/boot/dts/overlays/README  | 3 +++
- 2 files changed, 4 insertions(+)
-
---- a/arch/arm/boot/dts/bcm2708-rpi.dtsi
-+++ b/arch/arm/boot/dts/bcm2708-rpi.dtsi
-@@ -115,6 +115,7 @@
- 		sd_force_pio = <&sdhost>,"brcm,force-pio?";
- 		sd_pio_limit = <&sdhost>,"brcm,pio-limit:0";
- 		sd_debug     = <&sdhost>,"brcm,debug";
-+		sdio_overclock = <&mmc>,"brcm,overclock-50:0";
- 		axiperf      = <&axiperf>,"status";
- 	};
- };
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -139,6 +139,9 @@ Params:
- 
-         sd_debug                Enable debug output from SD driver (default off)
- 
-+        sdio_overclock          Clock (in MHz) to use when the MMC framework
-+                                requests 50MHz for the SDIO/WiFi interface.
-+
-         tx_lpi_timer            Set the delay in microseconds between going idle
-                                 and entering the low power state (default 600).
-                                 Requires EEE to be enabled - see "eee".
diff --git a/target/linux/brcm2708/patches-4.14/950-0280-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch b/target/linux/brcm2708/patches-4.14/950-0280-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch
deleted file mode 100644
index 60e885800..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0280-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From aeb94070e992a60cf33f0300c8317b39e3ae16db Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 24 Apr 2018 14:42:27 +0100
-Subject: [PATCH 280/454] gpiolib: Don't prevent IRQ usage of output GPIOs
-
-Upstream Linux deems using output GPIOs to generate IRQs as a bogus
-use case, even though the BCM2835 GPIO controller is capable of doing
-so. A number of users would like to make use of this facility, so
-disable the checks.
-
-See: https://github.com/raspberrypi/linux/issues/2527
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/gpio/gpiolib.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/gpio/gpiolib.c
-+++ b/drivers/gpio/gpiolib.c
-@@ -53,6 +53,8 @@
- #define	extra_checks	0
- #endif
- 
-+#define dont_test_bit(b,d) (0)
-+
- /* Device and char device-related information */
- static DEFINE_IDA(gpio_ida);
- static dev_t gpio_devt;
-@@ -2303,7 +2305,7 @@ static int _gpiod_direction_output_raw(s
- 	int ret;
- 
- 	/* GPIOs used for IRQs shall not be set as output */
--	if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
-+	if (dont_test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
- 		gpiod_err(desc,
- 			  "%s: tried to set a GPIO tied to an IRQ as output\n",
- 			  __func__);
-@@ -2818,7 +2820,7 @@ int gpiochip_lock_as_irq(struct gpio_chi
- 			set_bit(FLAG_IS_OUT, &desc->flags);
- 	}
- 
--	if (test_bit(FLAG_IS_OUT, &desc->flags)) {
-+	if (dont_test_bit(FLAG_IS_OUT, &desc->flags)) {
- 		chip_err(chip,
- 			  "%s: tried to flag a GPIO set as output for IRQ\n",
- 			  __func__);
diff --git a/target/linux/brcm2708/patches-4.14/950-0281-Drivers-for-Allo-Katana-DAC.patch b/target/linux/brcm2708/patches-4.14/950-0281-Drivers-for-Allo-Katana-DAC.patch
deleted file mode 100644
index 16235f23e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0281-Drivers-for-Allo-Katana-DAC.patch
+++ /dev/null
@@ -1,745 +0,0 @@
-From 87d450d98ef1f69dd6f5255c3b7e665c130935ea Mon Sep 17 00:00:00 2001
-From: allocom <sparky-dev@allo.com>
-Date: Thu, 19 Apr 2018 12:12:26 +0530
-Subject: [PATCH 281/454] Drivers for Allo Katana DAC
-
----
- arch/arm/boot/dts/overlays/Makefile           |   1 +
- arch/arm/boot/dts/overlays/README             |   6 +
- .../allo-katana-dac-audio-overlay.dts         |  46 +++
- arch/arm/configs/bcm2709_defconfig            |   1 +
- arch/arm/configs/bcmrpi_defconfig             |   1 +
- sound/soc/bcm/Kconfig                         |   7 +
- sound/soc/bcm/Makefile                        |   2 +
- sound/soc/bcm/allo-katana-dac.c               | 105 ++++++
- sound/soc/codecs/Kconfig                      |  10 +
- sound/soc/codecs/Makefile                     |   4 +
- sound/soc/codecs/sabre-ess-i2c.c              |  69 ++++
- sound/soc/codecs/sabre-ess.c                  | 300 ++++++++++++++++++
- sound/soc/codecs/sabre-ess.h                  |  62 ++++
- 13 files changed, 614 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts
- create mode 100644 sound/soc/bcm/allo-katana-dac.c
- create mode 100644 sound/soc/codecs/sabre-ess-i2c.c
- create mode 100644 sound/soc/codecs/sabre-ess.c
- create mode 100644 sound/soc/codecs/sabre-ess.h
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -9,6 +9,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	akkordion-iqdacplus.dtbo \
- 	allo-boss-dac-pcm512x-audio.dtbo \
- 	allo-digione.dtbo \
-+	allo-katana-dac-audio.dtbo \
- 	allo-piano-dac-pcm512x-audio.dtbo \
- 	allo-piano-dac-plus-pcm512x-audio.dtbo \
- 	applepi-dac.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -317,6 +317,12 @@ Load:   dtoverlay=allo-digione
- Params: <None>
- 
- 
-+Name:   allo-katana
-+Info:   Configures the Allo Katana audio card
-+Load:   dtoverlay=allo-katana-dac-audio
-+Params: <None>
-+
-+
- Name:   allo-piano-dac-pcm512x-audio
- Info:   Configures the Allo Piano DAC (2.0/2.1) audio cards.
-         (NB. This initial support is for 2.0 channel audio ONLY! ie. stereo.
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts
-@@ -0,0 +1,46 @@
-+/*
-+ * Definitions for Allo Katana DAC boards
-+ *
-+ * NB. The Katana DAC board contains SABER DAC.
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			sabre-ess@30 {
-+				#sound-dai-cells = <0>;
-+				compatible = "saber,sabre-ess";
-+				reg = <0x30>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		katana_dac: __overlay__ {
-+			compatible = "allo,katana-dac";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+		};
-+	};
-+
-+};
-+
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -894,6 +894,7 @@ CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m
- CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m
- CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m
- CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m
-+CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m
- CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m
- CONFIG_SND_PISOUND=m
- CONFIG_SND_SOC_ADAU1701=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -887,6 +887,7 @@ CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m
- CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m
- CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m
- CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m
-+CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m
- CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m
- CONFIG_SND_PISOUND=m
- CONFIG_SND_SOC_ADAU1701=m
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -175,6 +175,13 @@ config SND_BCM2708_SOC_ALLO_DIGIONE
- 	help
- 	  Say Y or M if you want to add support for Allo DigiOne.
- 
-+config SND_BCM2708_SOC_ALLO_KATANA_DAC
-+	tristate "Support for Allo Katana DAC"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	select SND_SOC_SABRE_ESS_I2C
-+	help
-+	  Say Y or M if you want to add support for Allo Katana DAC.
-+
- config SND_BCM2708_SOC_FE_PI_AUDIO
- 	tristate "Support for Fe-Pi-Audio"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -34,6 +34,7 @@ snd-soc-allo-boss-dac-objs := allo-boss-
- snd-soc-allo-piano-dac-objs := allo-piano-dac.o
- snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o
- snd-soc-allo-digione-objs := allo-digione.o
-+snd-soc-allo-katana-dac-objs := allo-katana-dac.o
- snd-soc-pisound-objs := pisound.o
- snd-soc-fe-pi-audio-objs := fe-pi-audio.o
- 
-@@ -60,5 +61,6 @@ obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_D
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE) += snd-soc-allo-digione.o
-+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC) += snd-soc-allo-katana-dac.o
- obj-$(CONFIG_SND_PISOUND) += snd-soc-pisound.o
- obj-$(CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO) += snd-soc-fe-pi-audio.o
---- /dev/null
-+++ b/sound/soc/bcm/allo-katana-dac.c
-@@ -0,0 +1,105 @@
-+/*
-+ * ASoC Driver for KATANA DAC
-+ *
-+ * Author:	Jaikumar <jaikumar@cem-solutions.net>
-+ *		Copyright 2018
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include <sound/core.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/soc.h>
-+
-+static struct snd_soc_dai_link snd_allo_katana_dac_dai[] = {
-+{
-+	.name		= "KATANA DAC",
-+	//.stream_name	= "KATANA DAC HiFi [Master]",
-+	.stream_name	= "KATANA DAC",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	//.codec_dai_name	= "es9038q2m-hifi",
-+	.codec_dai_name	= "sabre-ess",
-+	.platform_name	= "bcm2708-i2s.0",
-+	//.codec_name	= "es9038q2m.1-0030",
-+	.codec_name	= "sabre-ess.1-0030",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S |
-+		SND_SOC_DAIFMT_NB_NF |
-+		SND_SOC_DAIFMT_CBM_CFM,
-+},
-+};
-+
-+/* audio machine driver */
-+static struct snd_soc_card snd_allo_katana_dac = {
-+	.name         = "snd_allo_katana_dac",
-+	.owner        = THIS_MODULE,
-+	.dai_link     = snd_allo_katana_dac_dai,
-+	.num_links    = ARRAY_SIZE(snd_allo_katana_dac_dai),
-+};
-+
-+static int snd_allo_katana_dac_probe(struct platform_device *pdev)
-+{
-+	int ret = 0;
-+
-+	snd_allo_katana_dac.dev = &pdev->dev;
-+
-+	if (pdev->dev.of_node) {
-+		struct device_node *i2s_node;
-+		struct snd_soc_dai_link *dai = &snd_allo_katana_dac_dai[0];
-+
-+		i2s_node = of_parse_phandle(pdev->dev.of_node,
-+				"i2s-controller", 0);
-+
-+		if (i2s_node) {
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = i2s_node;
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = i2s_node;
-+		}
-+	}
-+
-+	ret = snd_soc_register_card(&snd_allo_katana_dac);
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
-+					ret);
-+
-+	return ret;
-+}
-+
-+static int snd_allo_katana_dac_remove(struct platform_device *pdev)
-+{
-+	return snd_soc_unregister_card(&snd_allo_katana_dac);
-+}
-+
-+static const struct of_device_id snd_allo_katana_dac_of_match[] = {
-+	{ .compatible = "allo,katana-dac", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, snd_allo_katana_dac_of_match);
-+
-+static struct platform_driver snd_allo_katana_dac_driver = {
-+	.driver = {
-+		.name   = "snd-katana-dac",
-+		.owner  = THIS_MODULE,
-+		.of_match_table = snd_allo_katana_dac_of_match,
-+	},
-+	.probe          = snd_allo_katana_dac_probe,
-+	.remove         = snd_allo_katana_dac_remove,
-+};
-+
-+module_platform_driver(snd_allo_katana_dac_driver);
-+
-+MODULE_AUTHOR("Jaikumar <jaikumar@cem-solutions.net>");
-+MODULE_DESCRIPTION("ALSA ASoC Machine Driver for Allo Katana DAC");
-+MODULE_LICENSE("GPL v2");
-+
---- a/sound/soc/codecs/Kconfig
-+++ b/sound/soc/codecs/Kconfig
-@@ -77,6 +77,7 @@ config SND_SOC_ALL_CODECS
- 	select SND_SOC_ES8328_SPI if SPI_MASTER
- 	select SND_SOC_ES8328_I2C if I2C
- 	select SND_SOC_ES7134
-+	select SND_SOC_SABRE_ESS_I2C if I2C
- 	select SND_SOC_GTM601
- 	select SND_SOC_HDAC_HDMI
- 	select SND_SOC_ICS43432
-@@ -1186,4 +1187,13 @@ config SND_SOC_TPA6130A2
- 	tristate "Texas Instruments TPA6130A2 headphone amplifier"
- 	depends on I2C
- 
-+config SND_SOC_SABRE_ESS
-+	tristate
-+
-+config SND_SOC_SABRE_ESS_I2C
-+	tristate "Sabre SABRE ESS CODEC - I2C"
-+	depends on I2C
-+	select SND_SOC_SABRE_ESS
-+	select REGMAP_I2C
-+
- endmenu
---- a/sound/soc/codecs/Makefile
-+++ b/sound/soc/codecs/Makefile
-@@ -71,6 +71,8 @@ snd-soc-es8316-objs := es8316.o
- snd-soc-es8328-objs := es8328.o
- snd-soc-es8328-i2c-objs := es8328-i2c.o
- snd-soc-es8328-spi-objs := es8328-spi.o
-+snd-soc-sabre-ess-objs := sabre-ess.o
-+snd-soc-sabre-ess-i2c-objs := sabre-ess-i2c.o
- snd-soc-gtm601-objs := gtm601.o
- snd-soc-hdac-hdmi-objs := hdac_hdmi.o
- snd-soc-ics43432-objs := ics43432.o
-@@ -313,6 +315,8 @@ obj-$(CONFIG_SND_SOC_ES8316)    += snd-s
- obj-$(CONFIG_SND_SOC_ES8328)	+= snd-soc-es8328.o
- obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o
- obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o
-+obj-$(CONFIG_SND_SOC_SABRE_ESS) += snd-soc-sabre-ess.o
-+obj-$(CONFIG_SND_SOC_SABRE_ESS_I2C) += snd-soc-sabre-ess-i2c.o
- obj-$(CONFIG_SND_SOC_GTM601)    += snd-soc-gtm601.o
- obj-$(CONFIG_SND_SOC_HDAC_HDMI) += snd-soc-hdac-hdmi.o
- obj-$(CONFIG_SND_SOC_ICS43432)	+= snd-soc-ics43432.o
---- /dev/null
-+++ b/sound/soc/codecs/sabre-ess-i2c.c
-@@ -0,0 +1,69 @@
-+/*
-+ * Driver for the SABRE ESS CODECs
-+ *
-+ * Author: Jaikumar <jaikumar@cem-solutions.net>	
-+ *		Copyright 2018
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/i2c.h>
-+
-+#include "sabre-ess.h"
-+
-+static int sabre_ess_i2c_probe(struct i2c_client *i2c,
-+			     const struct i2c_device_id *id)
-+{
-+	struct regmap *regmap;
-+	struct regmap_config config = sabre_ess_regmap;
-+
-+	regmap = devm_regmap_init_i2c(i2c, &config);
-+	if (IS_ERR(regmap))
-+		return PTR_ERR(regmap);
-+
-+	return sabre_ess_probe(&i2c->dev, regmap);
-+}
-+
-+static int sabre_ess_i2c_remove(struct i2c_client *i2c)
-+{
-+	sabre_ess_remove(&i2c->dev);
-+	return 0;
-+}
-+
-+static const struct i2c_device_id sabre_ess_i2c_id[] = {
-+	{ "sabre-ess", },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(i2c, sabre_ess_i2c_id);
-+
-+static const struct of_device_id sabre_ess_of_match[] = {
-+	{ .compatible = "saber,sabre-ess", },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, sabre_ess_of_match);
-+
-+static struct i2c_driver sabre_ess_i2c_driver = {
-+	.probe 		= sabre_ess_i2c_probe,
-+	.remove 	= sabre_ess_i2c_remove,
-+	.id_table	= sabre_ess_i2c_id,
-+	.driver		= {
-+		.name	= "sabre-ess",
-+		.of_match_table = sabre_ess_of_match,
-+	},
-+};
-+
-+module_i2c_driver(sabre_ess_i2c_driver);
-+
-+MODULE_DESCRIPTION("ASoC SABRE ESS codec driver - I2C");
-+MODULE_AUTHOR("Jaikumar <jaikumar@cem-solutions.net>");
-+MODULE_LICENSE("GPL v2");
-+
---- /dev/null
-+++ b/sound/soc/codecs/sabre-ess.c
-@@ -0,0 +1,300 @@
-+/*
-+ * Driver for the SABRE ESS CODEC
-+ *
-+ * Author: Jaikumar <jaikumar@cem-solutions.net>
-+ *		Copyright 2018
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/kernel.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/gcd.h>
-+#include <sound/soc.h>
-+#include <sound/soc-dapm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/tlv.h>
-+
-+#include "sabre-ess.h"
-+
-+struct sabre_ess_priv {
-+	struct regmap *regmap;
-+	int fmt;
-+};
-+
-+static const struct reg_default sabre_ess_reg_defaults[] = {
-+	{ SABRE_ESS_RESET,			0x00 },
-+	{ SABRE_ESS_VOLUME_1,		0xF0 },
-+	{ SABRE_ESS_VOLUME_2,		0xF0 },
-+	{ SABRE_ESS_MUTE,			0x00 },
-+	{ SABRE_ESS_DSP_PROGRAM,	0x04 },
-+	{ SABRE_ESS_DEEMPHASIS,		0x00 },
-+	{ SABRE_ESS_DOP,			0x01 },
-+	{ SABRE_ESS_FORMAT,			0xb4 },
-+};
-+
-+static const char * const sabre_ess_dsp_program_texts[] = {
-+	"Linear Phase Fast Roll-off Filter",
-+	"Linear Phase Slow Roll-off Filter",
-+	"Minimum Phase Fast Roll-off Filter",
-+	"Minimum Phase Slow Roll-off Filter",
-+	"Apodizing Fast Roll-off Filter",
-+	"Corrected Minimum Phase Fast Roll-off Filter",
-+	"Brick Wall Filter",
-+};
-+
-+static const unsigned int sabre_ess_dsp_program_values[] = {
-+	0,
-+	1,
-+	2,
-+	3,
-+	4,
-+	6,
-+	7,
-+};
-+
-+static SOC_VALUE_ENUM_SINGLE_DECL(sabre_ess_dsp_program,
-+				  SABRE_ESS_DSP_PROGRAM, 0, 0x07,
-+				  sabre_ess_dsp_program_texts,
-+				  sabre_ess_dsp_program_values);
-+
-+static const char * const sabre_ess_deemphasis_texts[] = {
-+	"Bypass",
-+	"32kHz",
-+	"44.1kHz",
-+	"48kHz",
-+};
-+
-+static const unsigned int sabre_ess_deemphasis_values[] = {
-+	0,
-+	1,
-+	2,
-+	3,
-+};
-+
-+static SOC_VALUE_ENUM_SINGLE_DECL(sabre_ess_deemphasis,
-+				  SABRE_ESS_DEEMPHASIS, 0, 0x03,
-+				  sabre_ess_deemphasis_texts,
-+				  sabre_ess_deemphasis_values);
-+
-+static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(master_tlv, -12700, 0);
-+
-+static const struct snd_kcontrol_new sabre_ess_controls[] = {
-+	SOC_DOUBLE_R_TLV("Master Playback Volume", SABRE_ESS_VOLUME_1,
-+			SABRE_ESS_VOLUME_2, 0, 255, 1, master_tlv),
-+	SOC_DOUBLE("Master Playback Switch", SABRE_ESS_MUTE, 0, 0, 1, 1),
-+	SOC_ENUM("DSP Program Route", sabre_ess_dsp_program),
-+	SOC_ENUM("Deemphasis Route", sabre_ess_deemphasis),
-+	SOC_SINGLE("DoP Playback Switch", SABRE_ESS_DOP, 0, 1, 1)
-+};
-+
-+static bool sabre_ess_readable_register(struct device *dev, unsigned int reg)
-+{
-+	switch (reg) {
-+	case SABRE_ESS_CHIP_ID_REG:
-+		return true;
-+	default:
-+		return reg < 0xff;
-+	}
-+}
-+
-+static int sabre_ess_hw_params(struct snd_pcm_substream *substream,
-+			     struct snd_pcm_hw_params *params,
-+			     struct snd_soc_dai *dai)
-+{
-+	struct snd_soc_codec *codec = dai->codec;
-+	struct sabre_ess_priv *sabre_ess = snd_soc_codec_get_drvdata(codec);
-+	int fmt = 0;
-+	int ret;
-+
-+	dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
-+			params_rate(params),
-+			params_channels(params));
-+
-+	switch (sabre_ess->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+	case SND_SOC_DAIFMT_CBM_CFM: // master
-+		if (params_channels(params) == 2)
-+			fmt = SABRE_ESS_CHAN_STEREO;
-+		else
-+			fmt = SABRE_ESS_CHAN_MONO;
-+
-+		switch (params_width(params)) {
-+		case 16:
-+			fmt |= SABRE_ESS_ALEN_16;
-+			break;
-+		case 24:
-+			fmt |= SABRE_ESS_ALEN_24;
-+			break;
-+		case 32:
-+			fmt |= SABRE_ESS_ALEN_32;
-+			break;
-+		default:
-+			dev_err(codec->dev, "Bad frame size: %d\n",
-+					params_width(params));
-+			return -EINVAL;
-+		}
-+
-+		switch (params_rate(params)) {
-+		case 44100:
-+			fmt |= SABRE_ESS_RATE_44100;
-+			break;
-+		case 48000:
-+			fmt |= SABRE_ESS_RATE_48000;
-+			break;
-+		case 88200:
-+			fmt |= SABRE_ESS_RATE_88200;
-+			break;
-+		case 96000:
-+			fmt |= SABRE_ESS_RATE_96000;
-+			break;
-+		case 176400:
-+			fmt |= SABRE_ESS_RATE_176400;
-+			break;
-+		case 192000:
-+			fmt |= SABRE_ESS_RATE_192000;
-+			break;
-+		case 352800:
-+			fmt |= SABRE_ESS_RATE_352800;
-+			break;
-+		case 384000:
-+			fmt |= SABRE_ESS_RATE_384000;
-+			break;
-+		default:
-+			dev_err(codec->dev, "Bad sample rate: %d\n",
-+					params_rate(params));
-+			return -EINVAL;
-+		}
-+
-+		ret = regmap_write(sabre_ess->regmap, SABRE_ESS_FORMAT, fmt);
-+		if (ret != 0) {
-+			dev_err(codec->dev, "Failed to set format: %d\n", ret);
-+			return ret;
-+		}
-+		break;
-+
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int sabre_ess_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+	struct snd_soc_codec *codec = dai->codec;
-+	struct sabre_ess_priv *sabre_ess = snd_soc_codec_get_drvdata(codec);
-+
-+	sabre_ess->fmt = fmt;
-+
-+	return 0;
-+}
-+
-+static const struct snd_soc_dai_ops sabre_ess_dai_ops = {
-+	.hw_params = sabre_ess_hw_params,
-+	.set_fmt = sabre_ess_set_fmt,
-+};
-+
-+static struct snd_soc_dai_driver sabre_ess_dai = {
-+	.name = "sabre-ess",
-+	.playback = {
-+		.stream_name = "Playback",
-+		.channels_min = 2,
-+		.channels_max = 2,
-+		.rates = SNDRV_PCM_RATE_CONTINUOUS,
-+		.rate_min = 44100,
-+		.rate_max = 384000,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE |
-+			SNDRV_PCM_FMTBIT_S32_LE
-+	},
-+	.ops = &sabre_ess_dai_ops,
-+};
-+
-+static struct snd_soc_codec_driver sabre_ess_codec_driver = {
-+	.idle_bias_off = false,
-+
-+	.component_driver = {
-+		.controls		= sabre_ess_controls,
-+		.num_controls	= ARRAY_SIZE(sabre_ess_controls),
-+	},
-+};
-+
-+static const struct regmap_range_cfg sabre_ess_range = {
-+	.name = "Pages", .range_min = SABRE_ESS_VIRT_BASE,
-+	.range_max = SABRE_ESS_MAX_REGISTER,
-+	.selector_reg = SABRE_ESS_PAGE,
-+	.selector_mask = 0xff,
-+	.window_start = 0, .window_len = 0x100,
-+};
-+
-+const struct regmap_config sabre_ess_regmap = {
-+	.reg_bits = 8,
-+	.val_bits = 8,
-+
-+	.ranges = &sabre_ess_range,
-+	.num_ranges = 1,
-+
-+	.max_register = SABRE_ESS_MAX_REGISTER,
-+	.readable_reg = sabre_ess_readable_register,
-+	.reg_defaults = sabre_ess_reg_defaults,
-+	.num_reg_defaults = ARRAY_SIZE(sabre_ess_reg_defaults),
-+	.cache_type = REGCACHE_RBTREE,
-+};
-+EXPORT_SYMBOL_GPL(sabre_ess_regmap);
-+
-+int sabre_ess_probe(struct device *dev, struct regmap *regmap)
-+{
-+	struct sabre_ess_priv *sabre_ess;
-+	unsigned int chip_id = 0;
-+	int ret;
-+
-+	sabre_ess = devm_kzalloc(dev, sizeof(struct sabre_ess_priv),
-+								GFP_KERNEL);
-+	if (!sabre_ess)
-+		return -ENOMEM;
-+
-+	dev_set_drvdata(dev, sabre_ess);
-+	sabre_ess->regmap = regmap;
-+
-+	ret = regmap_read(regmap, SABRE_ESS_CHIP_ID_REG, &chip_id);
-+	if ((ret != 0) || (chip_id != SABRE_ESS_CHIP_ID)) {
-+		dev_err(dev, "Failed to read Chip or wrong Chip id: %d\n", ret);
-+		return ret;
-+	}
-+	regmap_update_bits(regmap, SABRE_ESS_RESET, 0x01, 0x01);
-+	msleep(10);
-+
-+	ret = snd_soc_register_codec(dev, &sabre_ess_codec_driver,
-+				    &sabre_ess_dai, 1);
-+	if (ret != 0) {
-+		dev_err(dev, "failed to register codec: %d\n", ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(sabre_ess_probe);
-+
-+void sabre_ess_remove(struct device *dev)
-+{
-+	snd_soc_unregister_codec(dev);
-+	pm_runtime_disable(dev);
-+}
-+EXPORT_SYMBOL_GPL(sabre_ess_remove);
-+
-+MODULE_DESCRIPTION("ASoC SABRE ESS codec driver");
-+MODULE_AUTHOR("Jaikumar <jaikumar@cem-solutions.net>");
-+MODULE_LICENSE("GPL v2");
-+
---- /dev/null
-+++ b/sound/soc/codecs/sabre-ess.h
-@@ -0,0 +1,62 @@
-+/*
-+ * Driver for the SABRE ESS CODEC
-+ *
-+ * Author: Jaikumar <jaikumar@cem-solutions.net>
-+ *		Copyright 2018
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#ifndef _SND_SOC_SABRE_ESS_
-+#define _SND_SOC_SABRE_ESS_
-+
-+#include <linux/pm.h>
-+#include <linux/regmap.h>
-+
-+#define SABRE_ESS_CHIP_ID		0x30
-+#define SABRE_ESS_VIRT_BASE		0x100
-+#define SABRE_ESS_PAGE			0
-+
-+#define SABRE_ESS_CHIP_ID_REG	(SABRE_ESS_VIRT_BASE + 0)
-+#define SABRE_ESS_RESET			(SABRE_ESS_VIRT_BASE + 1)
-+#define SABRE_ESS_VOLUME_1		(SABRE_ESS_VIRT_BASE + 2)
-+#define SABRE_ESS_VOLUME_2		(SABRE_ESS_VIRT_BASE + 3)
-+#define SABRE_ESS_MUTE			(SABRE_ESS_VIRT_BASE + 4)
-+#define SABRE_ESS_DSP_PROGRAM	(SABRE_ESS_VIRT_BASE + 5)
-+#define SABRE_ESS_DEEMPHASIS	(SABRE_ESS_VIRT_BASE + 6)
-+#define SABRE_ESS_DOP			(SABRE_ESS_VIRT_BASE + 7)
-+#define SABRE_ESS_FORMAT		(SABRE_ESS_VIRT_BASE + 8)
-+#define SABRE_ESS_COMMAND		(SABRE_ESS_VIRT_BASE + 9)
-+#define SABRE_ESS_MAX_REGISTER	(SABRE_ESS_VIRT_BASE + 9)
-+
-+#define SABRE_ESS_FMT			0xff
-+#define SABRE_ESS_CHAN_MONO		0x00
-+#define SABRE_ESS_CHAN_STEREO	0x80
-+#define SABRE_ESS_ALEN_16		0x10
-+#define SABRE_ESS_ALEN_24		0x20
-+#define SABRE_ESS_ALEN_32		0x30
-+#define SABRE_ESS_RATE_11025	0x01
-+#define SABRE_ESS_RATE_22050	0x02
-+#define SABRE_ESS_RATE_32000	0x03
-+#define SABRE_ESS_RATE_44100	0x04
-+#define SABRE_ESS_RATE_48000	0x05
-+#define SABRE_ESS_RATE_88200	0x06
-+#define SABRE_ESS_RATE_96000	0x07
-+#define SABRE_ESS_RATE_176400	0x08
-+#define SABRE_ESS_RATE_192000	0x09
-+#define SABRE_ESS_RATE_352800	0x0a
-+#define SABRE_ESS_RATE_384000	0x0b
-+
-+extern const struct regmap_config sabre_ess_regmap;
-+
-+int sabre_ess_probe(struct device *dev, struct regmap *regmap);
-+void sabre_ess_remove(struct device *dev);
-+
-+#endif /* _SND_SOC_SABRE_ESS_ */
diff --git a/target/linux/brcm2708/patches-4.14/950-0282-Drivers-for-Allo-Katana-DAC.patch b/target/linux/brcm2708/patches-4.14/950-0282-Drivers-for-Allo-Katana-DAC.patch
deleted file mode 100644
index e104be4f8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0282-Drivers-for-Allo-Katana-DAC.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 5a2eeca047dcbdc107fab80e5b49d194c6e1791a Mon Sep 17 00:00:00 2001
-From: allocom <sparky-dev@allo.com>
-Date: Thu, 19 Apr 2018 12:16:03 +0530
-Subject: [PATCH 282/454] Drivers for Allo Katana DAC
-
----
- sound/soc/bcm/allo-katana-dac.c | 3 ---
- 1 file changed, 3 deletions(-)
-
---- a/sound/soc/bcm/allo-katana-dac.c
-+++ b/sound/soc/bcm/allo-katana-dac.c
-@@ -25,13 +25,10 @@
- static struct snd_soc_dai_link snd_allo_katana_dac_dai[] = {
- {
- 	.name		= "KATANA DAC",
--	//.stream_name	= "KATANA DAC HiFi [Master]",
- 	.stream_name	= "KATANA DAC",
- 	.cpu_dai_name	= "bcm2708-i2s.0",
--	//.codec_dai_name	= "es9038q2m-hifi",
- 	.codec_dai_name	= "sabre-ess",
- 	.platform_name	= "bcm2708-i2s.0",
--	//.codec_name	= "es9038q2m.1-0030",
- 	.codec_name	= "sabre-ess.1-0030",
- 	.dai_fmt	= SND_SOC_DAIFMT_I2S |
- 		SND_SOC_DAIFMT_NB_NF |
diff --git a/target/linux/brcm2708/patches-4.14/950-0283-Driver-for-Allo-Katana-DAC.patch b/target/linux/brcm2708/patches-4.14/950-0283-Driver-for-Allo-Katana-DAC.patch
deleted file mode 100644
index 17df64bed..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0283-Driver-for-Allo-Katana-DAC.patch
+++ /dev/null
@@ -1,1071 +0,0 @@
-From 1db90ec599e116593cc1844ccac021707b45c5cb Mon Sep 17 00:00:00 2001
-From: allocom <sparky-dev@allo.com>
-Date: Tue, 24 Apr 2018 11:19:03 +0530
-Subject: [PATCH 283/454] Driver for Allo Katana DAC
-
----
- .../allo-katana-dac-audio-overlay.dts         |  27 +-
- sound/soc/bcm/Kconfig                         |   4 +-
- sound/soc/bcm/Makefile                        |   4 +-
- sound/soc/bcm/allo-katana-codec.c             | 363 ++++++++++++++++++
- sound/soc/bcm/allo-katana-dac.c               | 102 -----
- sound/soc/codecs/Kconfig                      |  10 -
- sound/soc/codecs/Makefile                     |   4 -
- sound/soc/codecs/sabre-ess-i2c.c              |  69 ----
- sound/soc/codecs/sabre-ess.c                  | 300 ---------------
- sound/soc/codecs/sabre-ess.h                  |  62 ---
- 10 files changed, 387 insertions(+), 558 deletions(-)
- create mode 100644 sound/soc/bcm/allo-katana-codec.c
- delete mode 100644 sound/soc/bcm/allo-katana-dac.c
- delete mode 100644 sound/soc/codecs/sabre-ess-i2c.c
- delete mode 100644 sound/soc/codecs/sabre-ess.c
- delete mode 100644 sound/soc/codecs/sabre-ess.h
-
---- a/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts
-@@ -1,7 +1,5 @@
- /*
-  * Definitions for Allo Katana DAC boards
-- *
-- * NB. The Katana DAC board contains SABER DAC.
-  */
- 
- /dts-v1/;
-@@ -13,7 +11,16 @@
- 	fragment@0 {
- 		target = <&i2s>;
- 		__overlay__ {
-+			#sound-dai-cells = <0>;
- 			status = "okay";
-+			cpu_port: port {
-+				cpu_endpoint: endpoint {
-+					remote-endpoint = <&codec_endpoint>;
-+					bitclock-master = <&codec_endpoint>;
-+					frame-master = <&codec_endpoint>;
-+					dai-format = "i2s";
-+				};
-+			};
- 		};
- 	};
- 
-@@ -24,11 +31,15 @@
- 			#size-cells = <0>;
- 			status = "okay";
- 
--			sabre-ess@30 {
-+			allo-katana-codec@30 {
- 				#sound-dai-cells = <0>;
--				compatible = "saber,sabre-ess";
-+				compatible = "allo,allo-katana-codec";
- 				reg = <0x30>;
--				status = "okay";
-+				port {
-+					codec_endpoint: endpoint {
-+					remote-endpoint = <&cpu_endpoint>;
-+					};
-+				};
- 			};
- 		};
- 	};
-@@ -36,11 +47,11 @@
- 	fragment@2 {
- 		target = <&sound>;
- 		katana_dac: __overlay__ {
--			compatible = "allo,katana-dac";
--			i2s-controller = <&i2s>;
-+			compatible = "audio-graph-card";
-+			label = "Allo Katana";
-+			dais = <&cpu_port>;
- 			status = "okay";
- 		};
- 	};
--
- };
- 
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -178,7 +178,9 @@ config SND_BCM2708_SOC_ALLO_DIGIONE
- config SND_BCM2708_SOC_ALLO_KATANA_DAC
- 	tristate "Support for Allo Katana DAC"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
--	select SND_SOC_SABRE_ESS_I2C
-+	depends on I2C
-+	select REGMAP_I2C
-+	select SND_AUDIO_GRAPH_CARD
- 	help
- 	  Say Y or M if you want to add support for Allo Katana DAC.
- 
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -34,7 +34,7 @@ snd-soc-allo-boss-dac-objs := allo-boss-
- snd-soc-allo-piano-dac-objs := allo-piano-dac.o
- snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o
- snd-soc-allo-digione-objs := allo-digione.o
--snd-soc-allo-katana-dac-objs := allo-katana-dac.o
-+snd-soc-allo-katana-codec-objs := allo-katana-codec.o
- snd-soc-pisound-objs := pisound.o
- snd-soc-fe-pi-audio-objs := fe-pi-audio.o
- 
-@@ -61,6 +61,6 @@ obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_D
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o
- obj-$(CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE) += snd-soc-allo-digione.o
--obj-$(CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC) += snd-soc-allo-katana-dac.o
-+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC) += snd-soc-allo-katana-codec.o
- obj-$(CONFIG_SND_PISOUND) += snd-soc-pisound.o
- obj-$(CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO) += snd-soc-fe-pi-audio.o
---- /dev/null
-+++ b/sound/soc/bcm/allo-katana-codec.c
-@@ -0,0 +1,363 @@
-+/*
-+ * Driver for the ALLO KATANA CODEC
-+ *
-+ * Author: Jaikumar <jaikumar@cem-solutions.net>
-+ *		Copyright 2018
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/kernel.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/gcd.h>
-+#include <sound/soc.h>
-+#include <sound/soc-dapm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/tlv.h>
-+#include <linux/i2c.h>
-+
-+
-+#define KATANA_CODEC_CHIP_ID		0x30
-+#define KATANA_CODEC_VIRT_BASE		0x100
-+#define KATANA_CODEC_PAGE			0
-+
-+#define KATANA_CODEC_CHIP_ID_REG	(KATANA_CODEC_VIRT_BASE + 0)
-+#define KATANA_CODEC_RESET			(KATANA_CODEC_VIRT_BASE + 1)
-+#define KATANA_CODEC_VOLUME_1		(KATANA_CODEC_VIRT_BASE + 2)
-+#define KATANA_CODEC_VOLUME_2		(KATANA_CODEC_VIRT_BASE + 3)
-+#define KATANA_CODEC_MUTE			(KATANA_CODEC_VIRT_BASE + 4)
-+#define KATANA_CODEC_DSP_PROGRAM	(KATANA_CODEC_VIRT_BASE + 5)
-+#define KATANA_CODEC_DEEMPHASIS		(KATANA_CODEC_VIRT_BASE + 6)
-+#define KATANA_CODEC_DOP			(KATANA_CODEC_VIRT_BASE + 7)
-+#define KATANA_CODEC_FORMAT			(KATANA_CODEC_VIRT_BASE + 8)
-+#define KATANA_CODEC_COMMAND		(KATANA_CODEC_VIRT_BASE + 9)
-+#define KATANA_CODEC_MAX_REGISTER	(KATANA_CODEC_VIRT_BASE + 9)
-+
-+#define KATANA_CODEC_FMT			0xff
-+#define KATANA_CODEC_CHAN_MONO		0x00
-+#define KATANA_CODEC_CHAN_STEREO	0x80
-+#define KATANA_CODEC_ALEN_16		0x10
-+#define KATANA_CODEC_ALEN_24		0x20
-+#define KATANA_CODEC_ALEN_32		0x30
-+#define KATANA_CODEC_RATE_11025		0x01
-+#define KATANA_CODEC_RATE_22050		0x02
-+#define KATANA_CODEC_RATE_32000		0x03
-+#define KATANA_CODEC_RATE_44100		0x04
-+#define KATANA_CODEC_RATE_48000		0x05
-+#define KATANA_CODEC_RATE_88200		0x06
-+#define KATANA_CODEC_RATE_96000		0x07
-+#define KATANA_CODEC_RATE_176400	0x08
-+#define KATANA_CODEC_RATE_192000	0x09
-+#define KATANA_CODEC_RATE_352800	0x0a
-+#define KATANA_CODEC_RATE_384000	0x0b
-+
-+
-+struct katana_codec_priv {
-+	struct regmap *regmap;
-+	int fmt;
-+};
-+
-+static const struct reg_default katana_codec_reg_defaults[] = {
-+	{ KATANA_CODEC_RESET,		0x00 },
-+	{ KATANA_CODEC_VOLUME_1,	0xF0 },
-+	{ KATANA_CODEC_VOLUME_2,	0xF0 },
-+	{ KATANA_CODEC_MUTE,		0x00 },
-+	{ KATANA_CODEC_DSP_PROGRAM,	0x04 },
-+	{ KATANA_CODEC_DEEMPHASIS,	0x00 },
-+	{ KATANA_CODEC_DOP,			0x01 },
-+	{ KATANA_CODEC_FORMAT,		0xb4 },
-+};
-+
-+static const char * const katana_codec_dsp_program_texts[] = {
-+	"Linear Phase Fast Roll-off Filter",
-+	"Linear Phase Slow Roll-off Filter",
-+	"Minimum Phase Fast Roll-off Filter",
-+	"Minimum Phase Slow Roll-off Filter",
-+	"Apodizing Fast Roll-off Filter",
-+	"Corrected Minimum Phase Fast Roll-off Filter",
-+	"Brick Wall Filter",
-+};
-+
-+static const unsigned int katana_codec_dsp_program_values[] = {
-+	0,
-+	1,
-+	2,
-+	3,
-+	4,
-+	6,
-+	7,
-+};
-+
-+static SOC_VALUE_ENUM_SINGLE_DECL(katana_codec_dsp_program,
-+				  KATANA_CODEC_DSP_PROGRAM, 0, 0x07,
-+				  katana_codec_dsp_program_texts,
-+				  katana_codec_dsp_program_values);
-+
-+static const char * const katana_codec_deemphasis_texts[] = {
-+	"Bypass",
-+	"32kHz",
-+	"44.1kHz",
-+	"48kHz",
-+};
-+
-+static const unsigned int katana_codec_deemphasis_values[] = {
-+	0,
-+	1,
-+	2,
-+	3,
-+};
-+
-+static SOC_VALUE_ENUM_SINGLE_DECL(katana_codec_deemphasis,
-+				  KATANA_CODEC_DEEMPHASIS, 0, 0x03,
-+				  katana_codec_deemphasis_texts,
-+				  katana_codec_deemphasis_values);
-+
-+static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(master_tlv, -12700, 0);
-+
-+static const struct snd_kcontrol_new katana_codec_controls[] = {
-+	SOC_DOUBLE_R_TLV("Master Playback Volume", KATANA_CODEC_VOLUME_1,
-+			KATANA_CODEC_VOLUME_2, 0, 255, 1, master_tlv),
-+	SOC_DOUBLE("Master Playback Switch", KATANA_CODEC_MUTE, 0, 0, 1, 1),
-+	SOC_ENUM("DSP Program Route", katana_codec_dsp_program),
-+	SOC_ENUM("Deemphasis Route", katana_codec_deemphasis),
-+	SOC_SINGLE("DoP Playback Switch", KATANA_CODEC_DOP, 0, 1, 1)
-+};
-+
-+static bool katana_codec_readable_register(struct device *dev, unsigned int reg)
-+{
-+	switch (reg) {
-+	case KATANA_CODEC_CHIP_ID_REG:
-+		return true;
-+	default:
-+		return reg < 0xff;
-+	}
-+}
-+
-+static int katana_codec_hw_params(struct snd_pcm_substream *substream,
-+			     struct snd_pcm_hw_params *params,
-+			     struct snd_soc_dai *dai)
-+{
-+	struct snd_soc_codec *codec = dai->codec;
-+	struct katana_codec_priv *katana_codec = snd_soc_codec_get_drvdata(codec);
-+	int fmt = 0;
-+	int ret;
-+
-+	dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
-+			params_rate(params),
-+			params_channels(params));
-+
-+	switch (katana_codec->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+	case SND_SOC_DAIFMT_CBM_CFM: // master
-+		if (params_channels(params) == 2)
-+			fmt = KATANA_CODEC_CHAN_STEREO;
-+		else
-+			fmt = KATANA_CODEC_CHAN_MONO;
-+
-+		switch (params_width(params)) {
-+		case 16:
-+			fmt |= KATANA_CODEC_ALEN_16;
-+			break;
-+		case 24:
-+			fmt |= KATANA_CODEC_ALEN_24;
-+			break;
-+		case 32:
-+			fmt |= KATANA_CODEC_ALEN_32;
-+			break;
-+		default:
-+			dev_err(codec->dev, "Bad frame size: %d\n",
-+					params_width(params));
-+			return -EINVAL;
-+		}
-+
-+		switch (params_rate(params)) {
-+		case 44100:
-+			fmt |= KATANA_CODEC_RATE_44100;
-+			break;
-+		case 48000:
-+			fmt |= KATANA_CODEC_RATE_48000;
-+			break;
-+		case 88200:
-+			fmt |= KATANA_CODEC_RATE_88200;
-+			break;
-+		case 96000:
-+			fmt |= KATANA_CODEC_RATE_96000;
-+			break;
-+		case 176400:
-+			fmt |= KATANA_CODEC_RATE_176400;
-+			break;
-+		case 192000:
-+			fmt |= KATANA_CODEC_RATE_192000;
-+			break;
-+		case 352800:
-+			fmt |= KATANA_CODEC_RATE_352800;
-+			break;
-+		case 384000:
-+			fmt |= KATANA_CODEC_RATE_384000;
-+			break;
-+		default:
-+			dev_err(codec->dev, "Bad sample rate: %d\n",
-+					params_rate(params));
-+			return -EINVAL;
-+		}
-+
-+		ret = regmap_write(katana_codec->regmap, KATANA_CODEC_FORMAT, fmt);
-+		if (ret != 0) {
-+			dev_err(codec->dev, "Failed to set format: %d\n", ret);
-+			return ret;
-+		}
-+		break;
-+
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static int katana_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+	struct snd_soc_codec *codec = dai->codec;
-+	struct katana_codec_priv *katana_codec = snd_soc_codec_get_drvdata(codec);
-+
-+	katana_codec->fmt = fmt;
-+
-+	return 0;
-+}
-+
-+static const struct snd_soc_dai_ops katana_codec_dai_ops = {
-+	.hw_params = katana_codec_hw_params,
-+	.set_fmt = katana_codec_set_fmt,
-+};
-+
-+static struct snd_soc_dai_driver katana_codec_dai = {
-+	.name = "allo-katana-codec",
-+	.playback = {
-+		.stream_name = "Playback",
-+		.channels_min = 2,
-+		.channels_max = 2,
-+		.rates = SNDRV_PCM_RATE_CONTINUOUS,
-+		.rate_min = 44100,
-+		.rate_max = 384000,
-+		.formats = SNDRV_PCM_FMTBIT_S16_LE |
-+			SNDRV_PCM_FMTBIT_S32_LE
-+	},
-+	.ops = &katana_codec_dai_ops,
-+};
-+
-+static struct snd_soc_codec_driver katana_codec_codec_driver = {
-+	.idle_bias_off = false,
-+
-+	.component_driver = {
-+		.controls		= katana_codec_controls,
-+		.num_controls	= ARRAY_SIZE(katana_codec_controls),
-+	},
-+};
-+
-+static const struct regmap_range_cfg katana_codec_range = {
-+	.name = "Pages", .range_min = KATANA_CODEC_VIRT_BASE,
-+	.range_max = KATANA_CODEC_MAX_REGISTER,
-+	.selector_reg = KATANA_CODEC_PAGE,
-+	.selector_mask = 0xff,
-+	.window_start = 0, .window_len = 0x100,
-+};
-+
-+const struct regmap_config katana_codec_regmap = {
-+	.reg_bits = 8,
-+	.val_bits = 8,
-+
-+	.ranges = &katana_codec_range,
-+	.num_ranges = 1,
-+
-+	.max_register = KATANA_CODEC_MAX_REGISTER,
-+	.readable_reg = katana_codec_readable_register,
-+	.reg_defaults = katana_codec_reg_defaults,
-+	.num_reg_defaults = ARRAY_SIZE(katana_codec_reg_defaults),
-+	.cache_type = REGCACHE_RBTREE,
-+};
-+
-+static int allo_katana_codec_probe(struct i2c_client *i2c,
-+			     const struct i2c_device_id *id)
-+{
-+	struct regmap *regmap;
-+	struct regmap_config config = katana_codec_regmap;
-+	struct device *dev = &i2c->dev;
-+	struct katana_codec_priv *katana_codec;
-+	unsigned int chip_id = 0;
-+	int ret;
-+
-+	regmap = devm_regmap_init_i2c(i2c, &config);
-+	if (IS_ERR(regmap))
-+		return PTR_ERR(regmap);
-+
-+	katana_codec = devm_kzalloc(dev, sizeof(struct katana_codec_priv),
-+								GFP_KERNEL);
-+	if (!katana_codec)
-+		return -ENOMEM;
-+
-+	dev_set_drvdata(dev, katana_codec);
-+	katana_codec->regmap = regmap;
-+
-+	ret = regmap_read(regmap, KATANA_CODEC_CHIP_ID_REG, &chip_id);
-+	if ((ret != 0) || (chip_id != KATANA_CODEC_CHIP_ID)) {
-+		dev_err(dev, "Failed to read Chip or wrong Chip id: %d\n", ret);
-+		return ret;
-+	}
-+	regmap_update_bits(regmap, KATANA_CODEC_RESET, 0x01, 0x01);
-+	msleep(10);
-+
-+	ret = snd_soc_register_codec(dev, &katana_codec_codec_driver,
-+				    &katana_codec_dai, 1);
-+	if (ret != 0) {
-+		dev_err(dev, "failed to register codec: %d\n", ret);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int allo_katana_codec_remove(struct i2c_client *i2c)
-+{
-+	snd_soc_unregister_codec(&i2c->dev);
-+	return 0;
-+}
-+
-+static const struct i2c_device_id allo_katana_codec_id[] = {
-+	{ "allo-katana-codec", },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(i2c, allo_katana_codec_id);
-+
-+static const struct of_device_id allo_katana_codec_of_match[] = {
-+	{ .compatible = "allo,allo-katana-codec", },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, allo_katana_codec_of_match);
-+
-+static struct i2c_driver allo_katana_codec_driver = {
-+	.probe		= allo_katana_codec_probe,
-+	.remove		= allo_katana_codec_remove,
-+	.id_table	= allo_katana_codec_id,
-+	.driver		= {
-+		.name	= "allo-katana-codec",
-+		.of_match_table = allo_katana_codec_of_match,
-+	},
-+};
-+
-+module_i2c_driver(allo_katana_codec_driver);
-+
-+MODULE_DESCRIPTION("ASoC Allo Katana Codec Driver");
-+MODULE_AUTHOR("Jaikumar <jaikumar@cem-solutions.net>");
-+MODULE_LICENSE("GPL v2");
-+
---- a/sound/soc/bcm/allo-katana-dac.c
-+++ /dev/null
-@@ -1,102 +0,0 @@
--/*
-- * ASoC Driver for KATANA DAC
-- *
-- * Author:	Jaikumar <jaikumar@cem-solutions.net>
-- *		Copyright 2018
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License
-- * version 2 as published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope that it will be useful, but
-- * WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- * General Public License for more details.
-- */
--
--#include <linux/module.h>
--#include <linux/platform_device.h>
--
--#include <sound/core.h>
--#include <sound/pcm.h>
--#include <sound/pcm_params.h>
--#include <sound/soc.h>
--
--static struct snd_soc_dai_link snd_allo_katana_dac_dai[] = {
--{
--	.name		= "KATANA DAC",
--	.stream_name	= "KATANA DAC",
--	.cpu_dai_name	= "bcm2708-i2s.0",
--	.codec_dai_name	= "sabre-ess",
--	.platform_name	= "bcm2708-i2s.0",
--	.codec_name	= "sabre-ess.1-0030",
--	.dai_fmt	= SND_SOC_DAIFMT_I2S |
--		SND_SOC_DAIFMT_NB_NF |
--		SND_SOC_DAIFMT_CBM_CFM,
--},
--};
--
--/* audio machine driver */
--static struct snd_soc_card snd_allo_katana_dac = {
--	.name         = "snd_allo_katana_dac",
--	.owner        = THIS_MODULE,
--	.dai_link     = snd_allo_katana_dac_dai,
--	.num_links    = ARRAY_SIZE(snd_allo_katana_dac_dai),
--};
--
--static int snd_allo_katana_dac_probe(struct platform_device *pdev)
--{
--	int ret = 0;
--
--	snd_allo_katana_dac.dev = &pdev->dev;
--
--	if (pdev->dev.of_node) {
--		struct device_node *i2s_node;
--		struct snd_soc_dai_link *dai = &snd_allo_katana_dac_dai[0];
--
--		i2s_node = of_parse_phandle(pdev->dev.of_node,
--				"i2s-controller", 0);
--
--		if (i2s_node) {
--			dai->cpu_dai_name = NULL;
--			dai->cpu_of_node = i2s_node;
--			dai->platform_name = NULL;
--			dai->platform_of_node = i2s_node;
--		}
--	}
--
--	ret = snd_soc_register_card(&snd_allo_katana_dac);
--	if (ret && ret != -EPROBE_DEFER)
--		dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n",
--					ret);
--
--	return ret;
--}
--
--static int snd_allo_katana_dac_remove(struct platform_device *pdev)
--{
--	return snd_soc_unregister_card(&snd_allo_katana_dac);
--}
--
--static const struct of_device_id snd_allo_katana_dac_of_match[] = {
--	{ .compatible = "allo,katana-dac", },
--	{},
--};
--MODULE_DEVICE_TABLE(of, snd_allo_katana_dac_of_match);
--
--static struct platform_driver snd_allo_katana_dac_driver = {
--	.driver = {
--		.name   = "snd-katana-dac",
--		.owner  = THIS_MODULE,
--		.of_match_table = snd_allo_katana_dac_of_match,
--	},
--	.probe          = snd_allo_katana_dac_probe,
--	.remove         = snd_allo_katana_dac_remove,
--};
--
--module_platform_driver(snd_allo_katana_dac_driver);
--
--MODULE_AUTHOR("Jaikumar <jaikumar@cem-solutions.net>");
--MODULE_DESCRIPTION("ALSA ASoC Machine Driver for Allo Katana DAC");
--MODULE_LICENSE("GPL v2");
--
---- a/sound/soc/codecs/Kconfig
-+++ b/sound/soc/codecs/Kconfig
-@@ -77,7 +77,6 @@ config SND_SOC_ALL_CODECS
- 	select SND_SOC_ES8328_SPI if SPI_MASTER
- 	select SND_SOC_ES8328_I2C if I2C
- 	select SND_SOC_ES7134
--	select SND_SOC_SABRE_ESS_I2C if I2C
- 	select SND_SOC_GTM601
- 	select SND_SOC_HDAC_HDMI
- 	select SND_SOC_ICS43432
-@@ -1187,13 +1186,4 @@ config SND_SOC_TPA6130A2
- 	tristate "Texas Instruments TPA6130A2 headphone amplifier"
- 	depends on I2C
- 
--config SND_SOC_SABRE_ESS
--	tristate
--
--config SND_SOC_SABRE_ESS_I2C
--	tristate "Sabre SABRE ESS CODEC - I2C"
--	depends on I2C
--	select SND_SOC_SABRE_ESS
--	select REGMAP_I2C
--
- endmenu
---- a/sound/soc/codecs/Makefile
-+++ b/sound/soc/codecs/Makefile
-@@ -71,8 +71,6 @@ snd-soc-es8316-objs := es8316.o
- snd-soc-es8328-objs := es8328.o
- snd-soc-es8328-i2c-objs := es8328-i2c.o
- snd-soc-es8328-spi-objs := es8328-spi.o
--snd-soc-sabre-ess-objs := sabre-ess.o
--snd-soc-sabre-ess-i2c-objs := sabre-ess-i2c.o
- snd-soc-gtm601-objs := gtm601.o
- snd-soc-hdac-hdmi-objs := hdac_hdmi.o
- snd-soc-ics43432-objs := ics43432.o
-@@ -315,8 +313,6 @@ obj-$(CONFIG_SND_SOC_ES8316)    += snd-s
- obj-$(CONFIG_SND_SOC_ES8328)	+= snd-soc-es8328.o
- obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o
- obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o
--obj-$(CONFIG_SND_SOC_SABRE_ESS) += snd-soc-sabre-ess.o
--obj-$(CONFIG_SND_SOC_SABRE_ESS_I2C) += snd-soc-sabre-ess-i2c.o
- obj-$(CONFIG_SND_SOC_GTM601)    += snd-soc-gtm601.o
- obj-$(CONFIG_SND_SOC_HDAC_HDMI) += snd-soc-hdac-hdmi.o
- obj-$(CONFIG_SND_SOC_ICS43432)	+= snd-soc-ics43432.o
---- a/sound/soc/codecs/sabre-ess-i2c.c
-+++ /dev/null
-@@ -1,69 +0,0 @@
--/*
-- * Driver for the SABRE ESS CODECs
-- *
-- * Author: Jaikumar <jaikumar@cem-solutions.net>	
-- *		Copyright 2018
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License
-- * version 2 as published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope that it will be useful, but
-- * WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- * General Public License for more details.
-- */
--
--#include <linux/init.h>
--#include <linux/module.h>
--#include <linux/i2c.h>
--
--#include "sabre-ess.h"
--
--static int sabre_ess_i2c_probe(struct i2c_client *i2c,
--			     const struct i2c_device_id *id)
--{
--	struct regmap *regmap;
--	struct regmap_config config = sabre_ess_regmap;
--
--	regmap = devm_regmap_init_i2c(i2c, &config);
--	if (IS_ERR(regmap))
--		return PTR_ERR(regmap);
--
--	return sabre_ess_probe(&i2c->dev, regmap);
--}
--
--static int sabre_ess_i2c_remove(struct i2c_client *i2c)
--{
--	sabre_ess_remove(&i2c->dev);
--	return 0;
--}
--
--static const struct i2c_device_id sabre_ess_i2c_id[] = {
--	{ "sabre-ess", },
--	{ }
--};
--MODULE_DEVICE_TABLE(i2c, sabre_ess_i2c_id);
--
--static const struct of_device_id sabre_ess_of_match[] = {
--	{ .compatible = "saber,sabre-ess", },
--	{ }
--};
--MODULE_DEVICE_TABLE(of, sabre_ess_of_match);
--
--static struct i2c_driver sabre_ess_i2c_driver = {
--	.probe 		= sabre_ess_i2c_probe,
--	.remove 	= sabre_ess_i2c_remove,
--	.id_table	= sabre_ess_i2c_id,
--	.driver		= {
--		.name	= "sabre-ess",
--		.of_match_table = sabre_ess_of_match,
--	},
--};
--
--module_i2c_driver(sabre_ess_i2c_driver);
--
--MODULE_DESCRIPTION("ASoC SABRE ESS codec driver - I2C");
--MODULE_AUTHOR("Jaikumar <jaikumar@cem-solutions.net>");
--MODULE_LICENSE("GPL v2");
--
---- a/sound/soc/codecs/sabre-ess.c
-+++ /dev/null
-@@ -1,300 +0,0 @@
--/*
-- * Driver for the SABRE ESS CODEC
-- *
-- * Author: Jaikumar <jaikumar@cem-solutions.net>
-- *		Copyright 2018
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License
-- * version 2 as published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope that it will be useful, but
-- * WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- * General Public License for more details.
-- */
--
--
--#include <linux/init.h>
--#include <linux/module.h>
--#include <linux/clk.h>
--#include <linux/kernel.h>
--#include <linux/pm_runtime.h>
--#include <linux/regmap.h>
--#include <linux/regulator/consumer.h>
--#include <linux/gcd.h>
--#include <sound/soc.h>
--#include <sound/soc-dapm.h>
--#include <sound/pcm_params.h>
--#include <sound/tlv.h>
--
--#include "sabre-ess.h"
--
--struct sabre_ess_priv {
--	struct regmap *regmap;
--	int fmt;
--};
--
--static const struct reg_default sabre_ess_reg_defaults[] = {
--	{ SABRE_ESS_RESET,			0x00 },
--	{ SABRE_ESS_VOLUME_1,		0xF0 },
--	{ SABRE_ESS_VOLUME_2,		0xF0 },
--	{ SABRE_ESS_MUTE,			0x00 },
--	{ SABRE_ESS_DSP_PROGRAM,	0x04 },
--	{ SABRE_ESS_DEEMPHASIS,		0x00 },
--	{ SABRE_ESS_DOP,			0x01 },
--	{ SABRE_ESS_FORMAT,			0xb4 },
--};
--
--static const char * const sabre_ess_dsp_program_texts[] = {
--	"Linear Phase Fast Roll-off Filter",
--	"Linear Phase Slow Roll-off Filter",
--	"Minimum Phase Fast Roll-off Filter",
--	"Minimum Phase Slow Roll-off Filter",
--	"Apodizing Fast Roll-off Filter",
--	"Corrected Minimum Phase Fast Roll-off Filter",
--	"Brick Wall Filter",
--};
--
--static const unsigned int sabre_ess_dsp_program_values[] = {
--	0,
--	1,
--	2,
--	3,
--	4,
--	6,
--	7,
--};
--
--static SOC_VALUE_ENUM_SINGLE_DECL(sabre_ess_dsp_program,
--				  SABRE_ESS_DSP_PROGRAM, 0, 0x07,
--				  sabre_ess_dsp_program_texts,
--				  sabre_ess_dsp_program_values);
--
--static const char * const sabre_ess_deemphasis_texts[] = {
--	"Bypass",
--	"32kHz",
--	"44.1kHz",
--	"48kHz",
--};
--
--static const unsigned int sabre_ess_deemphasis_values[] = {
--	0,
--	1,
--	2,
--	3,
--};
--
--static SOC_VALUE_ENUM_SINGLE_DECL(sabre_ess_deemphasis,
--				  SABRE_ESS_DEEMPHASIS, 0, 0x03,
--				  sabre_ess_deemphasis_texts,
--				  sabre_ess_deemphasis_values);
--
--static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(master_tlv, -12700, 0);
--
--static const struct snd_kcontrol_new sabre_ess_controls[] = {
--	SOC_DOUBLE_R_TLV("Master Playback Volume", SABRE_ESS_VOLUME_1,
--			SABRE_ESS_VOLUME_2, 0, 255, 1, master_tlv),
--	SOC_DOUBLE("Master Playback Switch", SABRE_ESS_MUTE, 0, 0, 1, 1),
--	SOC_ENUM("DSP Program Route", sabre_ess_dsp_program),
--	SOC_ENUM("Deemphasis Route", sabre_ess_deemphasis),
--	SOC_SINGLE("DoP Playback Switch", SABRE_ESS_DOP, 0, 1, 1)
--};
--
--static bool sabre_ess_readable_register(struct device *dev, unsigned int reg)
--{
--	switch (reg) {
--	case SABRE_ESS_CHIP_ID_REG:
--		return true;
--	default:
--		return reg < 0xff;
--	}
--}
--
--static int sabre_ess_hw_params(struct snd_pcm_substream *substream,
--			     struct snd_pcm_hw_params *params,
--			     struct snd_soc_dai *dai)
--{
--	struct snd_soc_codec *codec = dai->codec;
--	struct sabre_ess_priv *sabre_ess = snd_soc_codec_get_drvdata(codec);
--	int fmt = 0;
--	int ret;
--
--	dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
--			params_rate(params),
--			params_channels(params));
--
--	switch (sabre_ess->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
--	case SND_SOC_DAIFMT_CBM_CFM: // master
--		if (params_channels(params) == 2)
--			fmt = SABRE_ESS_CHAN_STEREO;
--		else
--			fmt = SABRE_ESS_CHAN_MONO;
--
--		switch (params_width(params)) {
--		case 16:
--			fmt |= SABRE_ESS_ALEN_16;
--			break;
--		case 24:
--			fmt |= SABRE_ESS_ALEN_24;
--			break;
--		case 32:
--			fmt |= SABRE_ESS_ALEN_32;
--			break;
--		default:
--			dev_err(codec->dev, "Bad frame size: %d\n",
--					params_width(params));
--			return -EINVAL;
--		}
--
--		switch (params_rate(params)) {
--		case 44100:
--			fmt |= SABRE_ESS_RATE_44100;
--			break;
--		case 48000:
--			fmt |= SABRE_ESS_RATE_48000;
--			break;
--		case 88200:
--			fmt |= SABRE_ESS_RATE_88200;
--			break;
--		case 96000:
--			fmt |= SABRE_ESS_RATE_96000;
--			break;
--		case 176400:
--			fmt |= SABRE_ESS_RATE_176400;
--			break;
--		case 192000:
--			fmt |= SABRE_ESS_RATE_192000;
--			break;
--		case 352800:
--			fmt |= SABRE_ESS_RATE_352800;
--			break;
--		case 384000:
--			fmt |= SABRE_ESS_RATE_384000;
--			break;
--		default:
--			dev_err(codec->dev, "Bad sample rate: %d\n",
--					params_rate(params));
--			return -EINVAL;
--		}
--
--		ret = regmap_write(sabre_ess->regmap, SABRE_ESS_FORMAT, fmt);
--		if (ret != 0) {
--			dev_err(codec->dev, "Failed to set format: %d\n", ret);
--			return ret;
--		}
--		break;
--
--	default:
--		return -EINVAL;
--	}
--
--	return 0;
--}
--
--static int sabre_ess_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
--{
--	struct snd_soc_codec *codec = dai->codec;
--	struct sabre_ess_priv *sabre_ess = snd_soc_codec_get_drvdata(codec);
--
--	sabre_ess->fmt = fmt;
--
--	return 0;
--}
--
--static const struct snd_soc_dai_ops sabre_ess_dai_ops = {
--	.hw_params = sabre_ess_hw_params,
--	.set_fmt = sabre_ess_set_fmt,
--};
--
--static struct snd_soc_dai_driver sabre_ess_dai = {
--	.name = "sabre-ess",
--	.playback = {
--		.stream_name = "Playback",
--		.channels_min = 2,
--		.channels_max = 2,
--		.rates = SNDRV_PCM_RATE_CONTINUOUS,
--		.rate_min = 44100,
--		.rate_max = 384000,
--		.formats = SNDRV_PCM_FMTBIT_S16_LE |
--			SNDRV_PCM_FMTBIT_S32_LE
--	},
--	.ops = &sabre_ess_dai_ops,
--};
--
--static struct snd_soc_codec_driver sabre_ess_codec_driver = {
--	.idle_bias_off = false,
--
--	.component_driver = {
--		.controls		= sabre_ess_controls,
--		.num_controls	= ARRAY_SIZE(sabre_ess_controls),
--	},
--};
--
--static const struct regmap_range_cfg sabre_ess_range = {
--	.name = "Pages", .range_min = SABRE_ESS_VIRT_BASE,
--	.range_max = SABRE_ESS_MAX_REGISTER,
--	.selector_reg = SABRE_ESS_PAGE,
--	.selector_mask = 0xff,
--	.window_start = 0, .window_len = 0x100,
--};
--
--const struct regmap_config sabre_ess_regmap = {
--	.reg_bits = 8,
--	.val_bits = 8,
--
--	.ranges = &sabre_ess_range,
--	.num_ranges = 1,
--
--	.max_register = SABRE_ESS_MAX_REGISTER,
--	.readable_reg = sabre_ess_readable_register,
--	.reg_defaults = sabre_ess_reg_defaults,
--	.num_reg_defaults = ARRAY_SIZE(sabre_ess_reg_defaults),
--	.cache_type = REGCACHE_RBTREE,
--};
--EXPORT_SYMBOL_GPL(sabre_ess_regmap);
--
--int sabre_ess_probe(struct device *dev, struct regmap *regmap)
--{
--	struct sabre_ess_priv *sabre_ess;
--	unsigned int chip_id = 0;
--	int ret;
--
--	sabre_ess = devm_kzalloc(dev, sizeof(struct sabre_ess_priv),
--								GFP_KERNEL);
--	if (!sabre_ess)
--		return -ENOMEM;
--
--	dev_set_drvdata(dev, sabre_ess);
--	sabre_ess->regmap = regmap;
--
--	ret = regmap_read(regmap, SABRE_ESS_CHIP_ID_REG, &chip_id);
--	if ((ret != 0) || (chip_id != SABRE_ESS_CHIP_ID)) {
--		dev_err(dev, "Failed to read Chip or wrong Chip id: %d\n", ret);
--		return ret;
--	}
--	regmap_update_bits(regmap, SABRE_ESS_RESET, 0x01, 0x01);
--	msleep(10);
--
--	ret = snd_soc_register_codec(dev, &sabre_ess_codec_driver,
--				    &sabre_ess_dai, 1);
--	if (ret != 0) {
--		dev_err(dev, "failed to register codec: %d\n", ret);
--		return ret;
--	}
--
--	return 0;
--}
--EXPORT_SYMBOL_GPL(sabre_ess_probe);
--
--void sabre_ess_remove(struct device *dev)
--{
--	snd_soc_unregister_codec(dev);
--	pm_runtime_disable(dev);
--}
--EXPORT_SYMBOL_GPL(sabre_ess_remove);
--
--MODULE_DESCRIPTION("ASoC SABRE ESS codec driver");
--MODULE_AUTHOR("Jaikumar <jaikumar@cem-solutions.net>");
--MODULE_LICENSE("GPL v2");
--
---- a/sound/soc/codecs/sabre-ess.h
-+++ /dev/null
-@@ -1,62 +0,0 @@
--/*
-- * Driver for the SABRE ESS CODEC
-- *
-- * Author: Jaikumar <jaikumar@cem-solutions.net>
-- *		Copyright 2018
-- *
-- * This program is free software; you can redistribute it and/or
-- * modify it under the terms of the GNU General Public License
-- * version 2 as published by the Free Software Foundation.
-- *
-- * This program is distributed in the hope that it will be useful, but
-- * WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- * General Public License for more details.
-- */
--
--#ifndef _SND_SOC_SABRE_ESS_
--#define _SND_SOC_SABRE_ESS_
--
--#include <linux/pm.h>
--#include <linux/regmap.h>
--
--#define SABRE_ESS_CHIP_ID		0x30
--#define SABRE_ESS_VIRT_BASE		0x100
--#define SABRE_ESS_PAGE			0
--
--#define SABRE_ESS_CHIP_ID_REG	(SABRE_ESS_VIRT_BASE + 0)
--#define SABRE_ESS_RESET			(SABRE_ESS_VIRT_BASE + 1)
--#define SABRE_ESS_VOLUME_1		(SABRE_ESS_VIRT_BASE + 2)
--#define SABRE_ESS_VOLUME_2		(SABRE_ESS_VIRT_BASE + 3)
--#define SABRE_ESS_MUTE			(SABRE_ESS_VIRT_BASE + 4)
--#define SABRE_ESS_DSP_PROGRAM	(SABRE_ESS_VIRT_BASE + 5)
--#define SABRE_ESS_DEEMPHASIS	(SABRE_ESS_VIRT_BASE + 6)
--#define SABRE_ESS_DOP			(SABRE_ESS_VIRT_BASE + 7)
--#define SABRE_ESS_FORMAT		(SABRE_ESS_VIRT_BASE + 8)
--#define SABRE_ESS_COMMAND		(SABRE_ESS_VIRT_BASE + 9)
--#define SABRE_ESS_MAX_REGISTER	(SABRE_ESS_VIRT_BASE + 9)
--
--#define SABRE_ESS_FMT			0xff
--#define SABRE_ESS_CHAN_MONO		0x00
--#define SABRE_ESS_CHAN_STEREO	0x80
--#define SABRE_ESS_ALEN_16		0x10
--#define SABRE_ESS_ALEN_24		0x20
--#define SABRE_ESS_ALEN_32		0x30
--#define SABRE_ESS_RATE_11025	0x01
--#define SABRE_ESS_RATE_22050	0x02
--#define SABRE_ESS_RATE_32000	0x03
--#define SABRE_ESS_RATE_44100	0x04
--#define SABRE_ESS_RATE_48000	0x05
--#define SABRE_ESS_RATE_88200	0x06
--#define SABRE_ESS_RATE_96000	0x07
--#define SABRE_ESS_RATE_176400	0x08
--#define SABRE_ESS_RATE_192000	0x09
--#define SABRE_ESS_RATE_352800	0x0a
--#define SABRE_ESS_RATE_384000	0x0b
--
--extern const struct regmap_config sabre_ess_regmap;
--
--int sabre_ess_probe(struct device *dev, struct regmap *regmap);
--void sabre_ess_remove(struct device *dev);
--
--#endif /* _SND_SOC_SABRE_ESS_ */
diff --git a/target/linux/brcm2708/patches-4.14/950-0284-Driver-for-Allo-Katana-DAC.patch b/target/linux/brcm2708/patches-4.14/950-0284-Driver-for-Allo-Katana-DAC.patch
deleted file mode 100644
index aae6ee79a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0284-Driver-for-Allo-Katana-DAC.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From 6062dcfe6db738e78640b738ac6deea3fcf7de44 Mon Sep 17 00:00:00 2001
-From: allocom <sparky-dev@allo.com>
-Date: Wed, 25 Apr 2018 11:43:20 +0530
-Subject: [PATCH 284/454] Driver for Allo Katana DAC
-
----
- arch/arm/boot/dts/overlays/README | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -317,8 +317,8 @@ Load:   dtoverlay=allo-digione
- Params: <None>
- 
- 
--Name:   allo-katana
--Info:   Configures the Allo Katana audio card
-+Name:   allo-katana-dac-audio
-+Info:   Configures the Allo Katana DAC audio card
- Load:   dtoverlay=allo-katana-dac-audio
- Params: <None>
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0285-Reduce-log-spam-when-mailbox-call-not-implemented.patch b/target/linux/brcm2708/patches-4.14/950-0285-Reduce-log-spam-when-mailbox-call-not-implemented.patch
deleted file mode 100644
index 0377aac2d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0285-Reduce-log-spam-when-mailbox-call-not-implemented.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 785c44fa278b7dd7a4b96c64321dc43fa2220f7d Mon Sep 17 00:00:00 2001
-From: James Hughes <james.hughes@raspberrypi.org>
-Date: Fri, 27 Apr 2018 10:13:35 +0100
-Subject: [PATCH 285/454] Reduce log spam when mailbox call not implemented
-
-This changes the logging message when a mailbox call
-fails to the dev_dbg level. In addition, it fixes the
-low voltage detection logging code so that if the
-mailbox call doies fails, it logs at error level
-and flags so the call is no longer attempted.
-
-Signed-off-by: James Hughes <james.hughes@raspberrypi.org>
----
- drivers/firmware/raspberrypi.c | 23 ++++++++++++++++++-----
- 1 file changed, 18 insertions(+), 5 deletions(-)
-
---- a/drivers/firmware/raspberrypi.c
-+++ b/drivers/firmware/raspberrypi.c
-@@ -151,7 +151,7 @@ int rpi_firmware_property_list(struct rp
- 		 * error, if there were multiple tags in the request.
- 		 * But single-tag is the most common, so go with it.
- 		 */
--		dev_err(fw->cl.dev, "Request 0x%08x returned status 0x%08x\n",
-+		dev_dbg(fw->cl.dev, "Request 0x%08x returned status 0x%08x\n",
- 			buf[2], buf[1]);
- 		ret = -EINVAL;
- 	}
-@@ -204,6 +204,7 @@ EXPORT_SYMBOL_GPL(rpi_firmware_property)
- 
- static int rpi_firmware_get_throttled(struct rpi_firmware *fw, u32 *value)
- {
-+	static int old_firmware;
- 	static ktime_t old_timestamp;
- 	static u32 old_value;
- 	u32 new_sticky, old_sticky, new_uv, old_uv;
-@@ -214,6 +215,9 @@ static int rpi_firmware_get_throttled(st
- 	if (!fw)
- 		return -EBUSY;
- 
-+	if (old_firmware)
-+		return -EINVAL;
-+
- 	/*
- 	 * We can't run faster than the sticky shift (100ms) since we get
- 	 * flipping in the sticky bits that are cleared.
-@@ -232,8 +236,17 @@ static int rpi_firmware_get_throttled(st
- 
- 	ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_THROTTLED,
- 				    value, sizeof(*value));
--	if (ret)
-+
-+	if (ret) {
-+		/* If the mailbox call fails once, then it will continue to
-+		 * fail in the future, so no point in continuing to call it
-+		 * Usual failure reason is older firmware
-+		 */
-+		old_firmware = 1;
-+		dev_err(fw->cl.dev, "Get Throttled mailbox call failed");
-+
- 		return ret;
-+	}
- 
- 	new_sticky = *value >> 16;
- 	old_sticky = old_value >> 16;
-@@ -270,10 +283,10 @@ static void get_throttled_poll(struct wo
- 	int ret;
- 
- 	ret = rpi_firmware_get_throttled(fw, &dummy);
--	if (ret)
--		pr_debug("%s: Failed to read value (%d)", __func__, ret);
- 
--	schedule_delayed_work(&fw->get_throttled_poll_work, 2 * HZ);
-+	/* Only reschedule if we are getting valid responses */
-+	if (!ret)
-+		schedule_delayed_work(&fw->get_throttled_poll_work, 2 * HZ);
- }
- 
- static ssize_t get_throttled_show(struct device *dev,
diff --git a/target/linux/brcm2708/patches-4.14/950-0286-config-Add-I2C_TINY_USB-m.patch b/target/linux/brcm2708/patches-4.14/950-0286-config-Add-I2C_TINY_USB-m.patch
deleted file mode 100644
index d1dfc9458..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0286-config-Add-I2C_TINY_USB-m.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 213f6bdc61e20db0df54bbaf5a5cc25ad00804d2 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 27 Apr 2018 16:21:33 +0100
-Subject: [PATCH 286/454] config: Add I2C_TINY_USB=m
-
-Enable the I2C Tiny USB module.
-
-See: https://github.com/raspberrypi/linux/issues/2535
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 2 +-
- arch/arm/configs/bcmrpi_defconfig  | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -610,6 +610,7 @@ CONFIG_I2C_BCM2708=m
- CONFIG_I2C_BCM2835=m
- CONFIG_I2C_GPIO=m
- CONFIG_I2C_ROBOTFUZZ_OSIF=m
-+CONFIG_I2C_TINY_USB=m
- CONFIG_SPI=y
- CONFIG_SPI_BCM2835=m
- CONFIG_SPI_BCM2835AUX=m
-@@ -904,7 +905,6 @@ CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
--CONFIG_SND_AUDIO_GRAPH_CARD=m
- CONFIG_HID_BATTERY_STRENGTH=y
- CONFIG_HIDRAW=y
- CONFIG_UHID=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -605,6 +605,7 @@ CONFIG_I2C_BCM2708=m
- CONFIG_I2C_BCM2835=m
- CONFIG_I2C_GPIO=m
- CONFIG_I2C_ROBOTFUZZ_OSIF=m
-+CONFIG_I2C_TINY_USB=m
- CONFIG_SPI=y
- CONFIG_SPI_BCM2835=m
- CONFIG_SPI_BCM2835AUX=m
-@@ -897,7 +898,6 @@ CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
- CONFIG_SND_SIMPLE_CARD=m
--CONFIG_SND_AUDIO_GRAPH_CARD=m
- CONFIG_HID_BATTERY_STRENGTH=y
- CONFIG_HIDRAW=y
- CONFIG_UHID=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0287-ARM-bcm_defconfig-Re-enable-QCA7000-SPI-driver.patch b/target/linux/brcm2708/patches-4.14/950-0287-ARM-bcm_defconfig-Re-enable-QCA7000-SPI-driver.patch
deleted file mode 100644
index 92cedd106..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0287-ARM-bcm_defconfig-Re-enable-QCA7000-SPI-driver.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From a68f4a5674d114f6ab669c721d6b6972b8083f3a Mon Sep 17 00:00:00 2001
-From: Stefan Wahren <stefan.wahren@i2se.com>
-Date: Thu, 26 Apr 2018 14:49:37 +0200
-Subject: [PATCH 287/454] ARM: bcm_defconfig: Re-enable QCA7000 SPI driver
-
-Since commit b2f98200c73c ("net: qualcomm: make qca_7k_common a
-separate kernel module") the config parameter for the QCA7000 SPI
-driver has changed. So re-enable the QCA7000 SPI driver in all
-defconfigs, so we can use the qca7000-overlay again.
-
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
----
- arch/arm/configs/bcm2709_defconfig   | 1 +
- arch/arm/configs/bcmrpi_defconfig    | 1 +
- arch/arm64/configs/bcmrpi3_defconfig | 1 +
- 3 files changed, 3 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -444,6 +444,7 @@ CONFIG_NETCONSOLE=m
- CONFIG_TUN=m
- CONFIG_VETH=m
- CONFIG_ENC28J60=m
-+CONFIG_QCA7000_SPI=m
- CONFIG_MDIO_BITBANG=m
- CONFIG_PPP=m
- CONFIG_PPP_BSDCOMP=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -439,6 +439,7 @@ CONFIG_NETCONSOLE=m
- CONFIG_TUN=m
- CONFIG_VETH=m
- CONFIG_ENC28J60=m
-+CONFIG_QCA7000_SPI=m
- CONFIG_MDIO_BITBANG=m
- CONFIG_PPP=m
- CONFIG_PPP_BSDCOMP=m
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -430,6 +430,7 @@ CONFIG_NETCONSOLE=m
- CONFIG_TUN=m
- CONFIG_VETH=m
- CONFIG_ENC28J60=m
-+CONFIG_QCA7000_SPI=m
- CONFIG_MDIO_BITBANG=m
- CONFIG_PPP=m
- CONFIG_PPP_BSDCOMP=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0288-config-Add-CONFIG_BATTERY_GAUGE_LTC2941-m.patch b/target/linux/brcm2708/patches-4.14/950-0288-config-Add-CONFIG_BATTERY_GAUGE_LTC2941-m.patch
deleted file mode 100644
index b727c5eb6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0288-config-Add-CONFIG_BATTERY_GAUGE_LTC2941-m.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 83516a5d962a3bb2053334a10060126dfebb5be3 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 30 Apr 2018 15:57:00 +0100
-Subject: [PATCH 288/454] config: Add CONFIG_BATTERY_GAUGE_LTC2941=m
-
-Support the LTC294x range of I2C-connected battery monitors.
-
-See: https://github.com/raspberrypi/linux/issues/2537
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -648,6 +648,7 @@ CONFIG_W1_SLAVE_DS28E04=m
- CONFIG_POWER_RESET=y
- CONFIG_POWER_RESET_GPIO=y
- CONFIG_BATTERY_DS2760=m
-+CONFIG_BATTERY_GAUGE_LTC2941=m
- CONFIG_HWMON=m
- CONFIG_SENSORS_DS1621=m
- CONFIG_SENSORS_JC42=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -641,6 +641,7 @@ CONFIG_W1_SLAVE_DS28E04=m
- CONFIG_POWER_RESET=y
- CONFIG_POWER_RESET_GPIO=y
- CONFIG_BATTERY_DS2760=m
-+CONFIG_BATTERY_GAUGE_LTC2941=m
- CONFIG_HWMON=m
- CONFIG_SENSORS_DS1621=m
- CONFIG_SENSORS_JC42=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0289-overlays-Add-ltc294x-battery-gauge.patch b/target/linux/brcm2708/patches-4.14/950-0289-overlays-Add-ltc294x-battery-gauge.patch
deleted file mode 100644
index 3195b0450..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0289-overlays-Add-ltc294x-battery-gauge.patch
+++ /dev/null
@@ -1,150 +0,0 @@
-From 585ea300fa44cdf3c3259af68c49518bb85e4af2 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 1 May 2018 09:35:56 +0100
-Subject: [PATCH 289/454] overlays: Add ltc294x (battery gauge)
-
-Support the LTC294x range of I2C-connected battery monitors.
-
-See: https://github.com/raspberrypi/linux/issues/2537
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             | 25 ++++++
- .../arm/boot/dts/overlays/ltc294x-overlay.dts | 86 +++++++++++++++++++
- 3 files changed, 112 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/ltc294x-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -60,6 +60,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	justboom-dac.dtbo \
- 	justboom-digi.dtbo \
- 	lirc-rpi.dtbo \
-+	ltc294x.dtbo \
- 	mbed-dac.dtbo \
- 	mcp23017.dtbo \
- 	mcp23s17.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1020,6 +1020,31 @@ Params: gpio_out_pin            GPIO for
-                                 (default "off")
- 
- 
-+Name:   ltc294x
-+Info:   Adds support for the ltc294x family of battery gauges
-+Load:   dtoverlay=ltc294x,<param>=<val>
-+Params: ltc2941                 Select the ltc2941 device
-+
-+        ltc2942                 Select the ltc2942 device
-+
-+        ltc2943                 Select the ltc2943 device
-+
-+        ltc2944                 Select the ltc2944 device
-+
-+        resistor-sense          The sense resistor value in milli-ohms.
-+                                Can be a 32-bit negative value when the battery
-+                                has been connected to the wrong end of the
-+                                resistor.
-+
-+        prescaler-exponent      Range and accuracy of the gauge. The value is
-+                                programmed into the chip only if it differs
-+                                from the current setting.
-+                                For LTC2941 only:
-+                                - Default value is 128
-+                                - the exponent is in the range 0-7 (default 7)
-+                                See the datasheet for more information.
-+
-+
- Name:   mbed-dac
- Info:   Configures the mbed AudioCODEC (TLV320AIC23B)
- Load:   dtoverlay=mbed-dac
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/ltc294x-overlay.dts
-@@ -0,0 +1,86 @@
-+/dts-v1/;
-+/plugin/;
-+
-+
-+/ {
-+	compatible = "brcm,bcm2835";
-+
-+	fragment@0 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ltc2941: ltc2941@64 {
-+				compatible = "lltc,ltc2941";
-+				reg = <0x64>;
-+				lltc,resistor-sense = <50>;
-+				lltc,prescaler-exponent = <7>; 
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ltc2942: ltc2942@64 {
-+				compatible = "lltc,ltc2942";
-+				reg = <0x64>;
-+				lltc,resistor-sense = <50>;
-+				lltc,prescaler-exponent = <7>; 
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ltc2943: ltc2943@64 {
-+				compatible = "lltc,ltc2943";
-+				reg = <0x64>;
-+				lltc,resistor-sense = <50>;
-+				lltc,prescaler-exponent = <7>; 
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ltc2944: ltc2944@64 {
-+				compatible = "lltc,ltc2944";
-+				reg = <0x64>;
-+				lltc,resistor-sense = <50>;
-+				lltc,prescaler-exponent = <7>; 
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		ltc2941 = <0>,"+0";
-+		ltc2942 = <0>,"+1";
-+		ltc2943 = <0>,"+2";
-+		ltc2944 = <0>,"+3";
-+		resistor-sense = <&ltc2941>, "lltc,resistor-sense:0",
-+			         <&ltc2942>, "lltc,resistor-sense:0",
-+				 <&ltc2943>, "lltc,resistor-sense:0",
-+				 <&ltc2944>, "lltc,resistor-sense:0";
-+		prescaler-exponent = <&ltc2941>, "lltc,prescaler-exponent:0",
-+			         <&ltc2942>, "lltc,prescaler-exponent:0",
-+				 <&ltc2943>, "lltc,prescaler-exponent:0",
-+				 <&ltc2944>, "lltc,prescaler-exponent:0";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0290-overlays-Add-support-for-Balena-Fin-board.patch b/target/linux/brcm2708/patches-4.14/950-0290-overlays-Add-support-for-Balena-Fin-board.patch
deleted file mode 100644
index 1c317a6ac..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0290-overlays-Add-support-for-Balena-Fin-board.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From 09e843542826ad1241d77d5ef9abb2bce21a0984 Mon Sep 17 00:00:00 2001
-From: Florin Sarbu <florin@resin.io>
-Date: Mon, 30 Apr 2018 09:11:52 +0200
-Subject: [PATCH 290/454] overlays: Add support for Balena Fin board
-
-Signed-off-by: Florin Sarbu <florin@resin.io>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  7 ++
- .../boot/dts/overlays/balena-fin-overlay.dts  | 79 +++++++++++++++++++
- 3 files changed, 87 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/balena-fin-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -17,6 +17,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	audioinjector-addons.dtbo \
- 	audioinjector-wm8731-audio.dtbo \
- 	audremap.dtbo \
-+	balena-fin.dtbo \
- 	bmp085_i2c-sensor.dtbo \
- 	dht11.dtbo \
- 	dionaudio-loco.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -404,6 +404,13 @@ Params: swap_lr                 Reverse
-                                 (default off)
- 
- 
-+Name:   balena-fin
-+Info:   Overlay that enables WiFi, Bluetooth and the GPIO expander on the
-+        Balena Fin board.
-+Load:   dtoverlay=balena-fin
-+Params: <None>
-+
-+
- Name:   bmp085_i2c-sensor
- Info:   This overlay is now deprecated - see i2c-sensor
- Load:   dtoverlay=bmp085_i2c-sensor
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts
-@@ -0,0 +1,79 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&mmc>;
-+		sdio_wifi: __overlay__ {
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sdio_pins>;
-+			bus-width = <4>;
-+			brcm,overclock-50 = <35>;
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			sdio_pins: sdio_pins {
-+				brcm,pins = <34 35 36 37 38 39>;
-+				brcm,function = <7>; /* ALT3 = SD1 */
-+				brcm,pull = <0 2 2 2 2 2>;
-+			};
-+
-+			power_ctrl_pins: power_ctrl_pins {
-+				brcm,pins = <40>;
-+				brcm,function = <1>; // out
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target-path = "/";
-+		__overlay__ {
-+			// We should investigate how to switch to mmc-pwrseq-sd8787
-+			// Currently that module requires two GPIOs to function since it
-+			// targets a slightly different chip
-+			power_ctrl: power_ctrl {
-+				compatible = "gpio-poweroff";
-+				gpios = <&gpio 40 1>;
-+				force;
-+			};
-+
-+			i2c_soft: i2c@0 {
-+				compatible = "i2c-gpio";
-+				gpios = <&gpio 43 0 /* sda */ &gpio 42 0 /* scl */>;
-+				i2c-gpio,delay-us = <2>; /* ~100 kHz */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&i2c_soft>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			gpio_expander: gpio_expander@20 {
-+				compatible = "nxp,pca9554";
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+				reg = <0x20>;
-+				status = "okay";
-+			};
-+
-+			// rtc clock
-+			ds1307: ds1307@68 {
-+				compatible = "maxim,ds1307";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0291-ARM-dts-bcm283x-Fix-DTC-warnings-about-missing-phy-c.patch b/target/linux/brcm2708/patches-4.14/950-0291-ARM-dts-bcm283x-Fix-DTC-warnings-about-missing-phy-c.patch
deleted file mode 100644
index 402abec75..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0291-ARM-dts-bcm283x-Fix-DTC-warnings-about-missing-phy-c.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 6c69c8a5b2715bebd7c3727c1af78828863ccd4e Mon Sep 17 00:00:00 2001
-From: Stefan Wahren <stefan.wahren@i2se.com>
-Date: Sun, 29 Oct 2017 12:49:05 +0100
-Subject: [PATCH 291/454] ARM: dts: bcm283x: Fix DTC warnings about missing
- phy-cells
-
-commit 014d6da6cb2525d7f48fb08c705cb130cc7b5f4a upstream.
-
-This patch fixes the DTC warnings about missing property #phy-cells.
-
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
----
- arch/arm/boot/dts/bcm283x.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/boot/dts/bcm283x.dtsi
-+++ b/arch/arm/boot/dts/bcm283x.dtsi
-@@ -639,5 +639,6 @@
- 
- 	usbphy: phy {
- 		compatible = "usb-nop-xceiv";
-+		#phy-cells = <0>;
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0292-net-mdiobus-add-unlocked-accessors.patch b/target/linux/brcm2708/patches-4.14/950-0292-net-mdiobus-add-unlocked-accessors.patch
deleted file mode 100644
index 5aec47e60..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0292-net-mdiobus-add-unlocked-accessors.patch
+++ /dev/null
@@ -1,141 +0,0 @@
-From b2b8b06f18281c637da274b18e330bc52351637e Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Tue, 2 Jan 2018 10:58:27 +0000
-Subject: [PATCH 292/454] net: mdiobus: add unlocked accessors
-
-commit 34dc08e4be208539b7c4aa8154a610e1736705e8 upstream.
-
-Add unlocked versions of the bus accessors, which allows access to the
-bus with all the tracing. These accessors validate that the bus mutex
-is held, which is a basic requirement for all mii bus accesses.
-
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/phy/mdio_bus.c | 65 +++++++++++++++++++++++++++++++-------
- include/linux/mdio.h       |  3 ++
- 2 files changed, 56 insertions(+), 12 deletions(-)
-
---- a/drivers/net/phy/mdio_bus.c
-+++ b/drivers/net/phy/mdio_bus.c
-@@ -493,6 +493,55 @@ struct phy_device *mdiobus_scan(struct m
- EXPORT_SYMBOL(mdiobus_scan);
- 
- /**
-+ * __mdiobus_read - Unlocked version of the mdiobus_read function
-+ * @bus: the mii_bus struct
-+ * @addr: the phy address
-+ * @regnum: register number to read
-+ *
-+ * Read a MDIO bus register. Caller must hold the mdio bus lock.
-+ *
-+ * NOTE: MUST NOT be called from interrupt context.
-+ */
-+int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
-+{
-+	int retval;
-+
-+	WARN_ON_ONCE(!mutex_is_locked(&bus->mdio_lock));
-+
-+	retval = bus->read(bus, addr, regnum);
-+
-+	trace_mdio_access(bus, 1, addr, regnum, retval, retval);
-+
-+	return retval;
-+}
-+EXPORT_SYMBOL(__mdiobus_read);
-+
-+/**
-+ * __mdiobus_write - Unlocked version of the mdiobus_write function
-+ * @bus: the mii_bus struct
-+ * @addr: the phy address
-+ * @regnum: register number to write
-+ * @val: value to write to @regnum
-+ *
-+ * Write a MDIO bus register. Caller must hold the mdio bus lock.
-+ *
-+ * NOTE: MUST NOT be called from interrupt context.
-+ */
-+int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val)
-+{
-+	int err;
-+
-+	WARN_ON_ONCE(!mutex_is_locked(&bus->mdio_lock));
-+
-+	err = bus->write(bus, addr, regnum, val);
-+
-+	trace_mdio_access(bus, 0, addr, regnum, val, err);
-+
-+	return err;
-+}
-+EXPORT_SYMBOL(__mdiobus_write);
-+
-+/**
-  * mdiobus_read_nested - Nested version of the mdiobus_read function
-  * @bus: the mii_bus struct
-  * @addr: the phy address
-@@ -512,11 +561,9 @@ int mdiobus_read_nested(struct mii_bus *
- 	BUG_ON(in_interrupt());
- 
- 	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
--	retval = bus->read(bus, addr, regnum);
-+	retval = __mdiobus_read(bus, addr, regnum);
- 	mutex_unlock(&bus->mdio_lock);
- 
--	trace_mdio_access(bus, 1, addr, regnum, retval, retval);
--
- 	return retval;
- }
- EXPORT_SYMBOL(mdiobus_read_nested);
-@@ -538,11 +585,9 @@ int mdiobus_read(struct mii_bus *bus, in
- 	BUG_ON(in_interrupt());
- 
- 	mutex_lock(&bus->mdio_lock);
--	retval = bus->read(bus, addr, regnum);
-+	retval = __mdiobus_read(bus, addr, regnum);
- 	mutex_unlock(&bus->mdio_lock);
- 
--	trace_mdio_access(bus, 1, addr, regnum, retval, retval);
--
- 	return retval;
- }
- EXPORT_SYMBOL(mdiobus_read);
-@@ -568,11 +613,9 @@ int mdiobus_write_nested(struct mii_bus
- 	BUG_ON(in_interrupt());
- 
- 	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
--	err = bus->write(bus, addr, regnum, val);
-+	err = __mdiobus_write(bus, addr, regnum, val);
- 	mutex_unlock(&bus->mdio_lock);
- 
--	trace_mdio_access(bus, 0, addr, regnum, val, err);
--
- 	return err;
- }
- EXPORT_SYMBOL(mdiobus_write_nested);
-@@ -595,11 +638,9 @@ int mdiobus_write(struct mii_bus *bus, i
- 	BUG_ON(in_interrupt());
- 
- 	mutex_lock(&bus->mdio_lock);
--	err = bus->write(bus, addr, regnum, val);
-+	err = __mdiobus_write(bus, addr, regnum, val);
- 	mutex_unlock(&bus->mdio_lock);
- 
--	trace_mdio_access(bus, 0, addr, regnum, val, err);
--
- 	return err;
- }
- EXPORT_SYMBOL(mdiobus_write);
---- a/include/linux/mdio.h
-+++ b/include/linux/mdio.h
-@@ -257,6 +257,9 @@ static inline u16 ethtool_adv_to_mmd_eee
- 	return reg;
- }
- 
-+int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
-+int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
-+
- int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
- int mdiobus_read_nested(struct mii_bus *bus, int addr, u32 regnum);
- int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
diff --git a/target/linux/brcm2708/patches-4.14/950-0293-net-phy-use-unlocked-accessors-for-indirect-MMD-acce.patch b/target/linux/brcm2708/patches-4.14/950-0293-net-phy-use-unlocked-accessors-for-indirect-MMD-acce.patch
deleted file mode 100644
index 9f4cc1c7d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0293-net-phy-use-unlocked-accessors-for-indirect-MMD-acce.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 2d490ea00f141384d57c7e18e44b34e94e572b26 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Tue, 2 Jan 2018 10:58:32 +0000
-Subject: [PATCH 293/454] net: phy: use unlocked accessors for indirect MMD
- accesses
-
-commit 1b2dea2e6a6e3399e88784d57aea80f4fd5e8956 upstream.
-
-Use unlocked accessors for indirect MMD accesses to clause 22 PHYs.
-This permits tracing of these accesses.
-
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/phy/phy-core.c | 11 ++++++-----
- 1 file changed, 6 insertions(+), 5 deletions(-)
-
---- a/drivers/net/phy/phy-core.c
-+++ b/drivers/net/phy/phy-core.c
-@@ -193,13 +193,14 @@ static void mmd_phy_indirect(struct mii_
- 			     u16 regnum)
- {
- 	/* Write the desired MMD Devad */
--	bus->write(bus, phy_addr, MII_MMD_CTRL, devad);
-+	__mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad);
- 
- 	/* Write the desired MMD register address */
--	bus->write(bus, phy_addr, MII_MMD_DATA, regnum);
-+	__mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum);
- 
- 	/* Select the Function : DATA with no post increment */
--	bus->write(bus, phy_addr, MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
-+	__mdiobus_write(bus, phy_addr, MII_MMD_CTRL,
-+			devad | MII_MMD_CTRL_NOINCR);
- }
- 
- /**
-@@ -232,7 +233,7 @@ int phy_read_mmd(struct phy_device *phyd
- 		mmd_phy_indirect(bus, phy_addr, devad, regnum);
- 
- 		/* Read the content of the MMD's selected register */
--		val = bus->read(bus, phy_addr, MII_MMD_DATA);
-+		val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
- 		mutex_unlock(&bus->mdio_lock);
- 	}
- 	return val;
-@@ -271,7 +272,7 @@ int phy_write_mmd(struct phy_device *phy
- 		mmd_phy_indirect(bus, phy_addr, devad, regnum);
- 
- 		/* Write the data into MMD's selected register */
--		bus->write(bus, phy_addr, MII_MMD_DATA, val);
-+		__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
- 		mutex_unlock(&bus->mdio_lock);
- 
- 		ret = 0;
diff --git a/target/linux/brcm2708/patches-4.14/950-0294-net-phy-add-unlocked-accessors.patch b/target/linux/brcm2708/patches-4.14/950-0294-net-phy-add-unlocked-accessors.patch
deleted file mode 100644
index f0b916e86..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0294-net-phy-add-unlocked-accessors.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From 6709752e7233afd929a130ac4f3645348be94c1f Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Tue, 2 Jan 2018 10:58:37 +0000
-Subject: [PATCH 294/454] net: phy: add unlocked accessors
-
-commit 788f9933db6172801336d0ae2dec5bdc7525389f upstream.
-
-Add unlocked versions of the bus accessors, which allows access to the
-bus with all the tracing. These accessors validate that the bus mutex
-is held, which is a basic requirement for all mii bus accesses.
-
-Also added is a read-modify-write unlocked accessor with the same
-locking requirements.
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/phy/phy-core.c | 25 +++++++++++++++++++++++++
- include/linux/phy.h        | 28 ++++++++++++++++++++++++++++
- 2 files changed, 53 insertions(+)
-
---- a/drivers/net/phy/phy-core.c
-+++ b/drivers/net/phy/phy-core.c
-@@ -280,3 +280,28 @@ int phy_write_mmd(struct phy_device *phy
- 	return ret;
- }
- EXPORT_SYMBOL(phy_write_mmd);
-+
-+/**
-+ * __phy_modify() - Convenience function for modifying a PHY register
-+ * @phydev: a pointer to a &struct phy_device
-+ * @regnum: register number
-+ * @mask: bit mask of bits to clear
-+ * @set: bit mask of bits to set
-+ *
-+ * Unlocked helper function which allows a PHY register to be modified as
-+ * new register value = (old register value & mask) | set
-+ */
-+int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set)
-+{
-+	int ret, res;
-+
-+	ret = __phy_read(phydev, regnum);
-+	if (ret >= 0) {
-+		res = __phy_write(phydev, regnum, (ret & ~mask) | set);
-+		if (res < 0)
-+			ret = res;
-+	}
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(__phy_modify);
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -726,6 +726,18 @@ static inline int phy_read(struct phy_de
- }
- 
- /**
-+ * __phy_read - convenience function for reading a given PHY register
-+ * @phydev: the phy_device struct
-+ * @regnum: register number to read
-+ *
-+ * The caller must have taken the MDIO bus lock.
-+ */
-+static inline int __phy_read(struct phy_device *phydev, u32 regnum)
-+{
-+	return __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, regnum);
-+}
-+
-+/**
-  * phy_write - Convenience function for writing a given PHY register
-  * @phydev: the phy_device struct
-  * @regnum: register number to write
-@@ -741,6 +753,22 @@ static inline int phy_write(struct phy_d
- }
- 
- /**
-+ * __phy_write - Convenience function for writing a given PHY register
-+ * @phydev: the phy_device struct
-+ * @regnum: register number to write
-+ * @val: value to write to @regnum
-+ *
-+ * The caller must have taken the MDIO bus lock.
-+ */
-+static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
-+{
-+	return __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, regnum,
-+			       val);
-+}
-+
-+int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
-+
-+/**
-  * phy_interrupt_is_valid - Convenience function for testing a given PHY irq
-  * @phydev: the phy_device struct
-  *
diff --git a/target/linux/brcm2708/patches-4.14/950-0295-net-phy-add-paged-phy-register-accessors.patch b/target/linux/brcm2708/patches-4.14/950-0295-net-phy-add-paged-phy-register-accessors.patch
deleted file mode 100644
index 51866b448..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0295-net-phy-add-paged-phy-register-accessors.patch
+++ /dev/null
@@ -1,208 +0,0 @@
-From 8a74a77e9df9565c247da3df37657d6eabb314c6 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Tue, 2 Jan 2018 10:58:43 +0000
-Subject: [PATCH 295/454] net: phy: add paged phy register accessors
-
-commit 78ffc4acceff48522b92d8fbf8f4a0ffe78838b2 upstream.
-
-Add a set of paged phy register accessors which are inherently safe in
-their design against other accesses interfering with the paged access.
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/phy/phy-core.c | 157 +++++++++++++++++++++++++++++++++++++
- include/linux/phy.h        |  11 +++
- 2 files changed, 168 insertions(+)
-
---- a/drivers/net/phy/phy-core.c
-+++ b/drivers/net/phy/phy-core.c
-@@ -305,3 +305,160 @@ int __phy_modify(struct phy_device *phyd
- 	return ret;
- }
- EXPORT_SYMBOL_GPL(__phy_modify);
-+
-+static int __phy_read_page(struct phy_device *phydev)
-+{
-+	return phydev->drv->read_page(phydev);
-+}
-+
-+static int __phy_write_page(struct phy_device *phydev, int page)
-+{
-+	return phydev->drv->write_page(phydev, page);
-+}
-+
-+/**
-+ * phy_save_page() - take the bus lock and save the current page
-+ * @phydev: a pointer to a &struct phy_device
-+ *
-+ * Take the MDIO bus lock, and return the current page number. On error,
-+ * returns a negative errno. phy_restore_page() must always be called
-+ * after this, irrespective of success or failure of this call.
-+ */
-+int phy_save_page(struct phy_device *phydev)
-+{
-+	mutex_lock(&phydev->mdio.bus->mdio_lock);
-+	return __phy_read_page(phydev);
-+}
-+EXPORT_SYMBOL_GPL(phy_save_page);
-+
-+/**
-+ * phy_select_page() - take the bus lock, save the current page, and set a page
-+ * @phydev: a pointer to a &struct phy_device
-+ * @page: desired page
-+ *
-+ * Take the MDIO bus lock to protect against concurrent access, save the
-+ * current PHY page, and set the current page.  On error, returns a
-+ * negative errno, otherwise returns the previous page number.
-+ * phy_restore_page() must always be called after this, irrespective
-+ * of success or failure of this call.
-+ */
-+int phy_select_page(struct phy_device *phydev, int page)
-+{
-+	int ret, oldpage;
-+
-+	oldpage = ret = phy_save_page(phydev);
-+	if (ret < 0)
-+		return ret;
-+
-+	if (oldpage != page) {
-+		ret = __phy_write_page(phydev, page);
-+		if (ret < 0)
-+			return ret;
-+	}
-+
-+	return oldpage;
-+}
-+EXPORT_SYMBOL_GPL(phy_select_page);
-+
-+/**
-+ * phy_restore_page() - restore the page register and release the bus lock
-+ * @phydev: a pointer to a &struct phy_device
-+ * @oldpage: the old page, return value from phy_save_page() or phy_select_page()
-+ * @ret: operation's return code
-+ *
-+ * Release the MDIO bus lock, restoring @oldpage if it is a valid page.
-+ * This function propagates the earliest error code from the group of
-+ * operations.
-+ *
-+ * Returns:
-+ *   @oldpage if it was a negative value, otherwise
-+ *   @ret if it was a negative errno value, otherwise
-+ *   phy_write_page()'s negative value if it were in error, otherwise
-+ *   @ret.
-+ */
-+int phy_restore_page(struct phy_device *phydev, int oldpage, int ret)
-+{
-+	int r;
-+
-+	if (oldpage >= 0) {
-+		r = __phy_write_page(phydev, oldpage);
-+
-+		/* Propagate the operation return code if the page write
-+		 * was successful.
-+		 */
-+		if (ret >= 0 && r < 0)
-+			ret = r;
-+	} else {
-+		/* Propagate the phy page selection error code */
-+		ret = oldpage;
-+	}
-+
-+	mutex_unlock(&phydev->mdio.bus->mdio_lock);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL_GPL(phy_restore_page);
-+
-+/**
-+ * phy_read_paged() - Convenience function for reading a paged register
-+ * @phydev: a pointer to a &struct phy_device
-+ * @page: the page for the phy
-+ * @regnum: register number
-+ *
-+ * Same rules as for phy_read().
-+ */
-+int phy_read_paged(struct phy_device *phydev, int page, u32 regnum)
-+{
-+	int ret = 0, oldpage;
-+
-+	oldpage = phy_select_page(phydev, page);
-+	if (oldpage >= 0)
-+		ret = __phy_read(phydev, regnum);
-+
-+	return phy_restore_page(phydev, oldpage, ret);
-+}
-+EXPORT_SYMBOL(phy_read_paged);
-+
-+/**
-+ * phy_write_paged() - Convenience function for writing a paged register
-+ * @phydev: a pointer to a &struct phy_device
-+ * @page: the page for the phy
-+ * @regnum: register number
-+ * @val: value to write
-+ *
-+ * Same rules as for phy_write().
-+ */
-+int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val)
-+{
-+	int ret = 0, oldpage;
-+
-+	oldpage = phy_select_page(phydev, page);
-+	if (oldpage >= 0)
-+		ret = __phy_write(phydev, regnum, val);
-+
-+	return phy_restore_page(phydev, oldpage, ret);
-+}
-+EXPORT_SYMBOL(phy_write_paged);
-+
-+/**
-+ * phy_modify_paged() - Convenience function for modifying a paged register
-+ * @phydev: a pointer to a &struct phy_device
-+ * @page: the page for the phy
-+ * @regnum: register number
-+ * @mask: bit mask of bits to clear
-+ * @set: bit mask of bits to set
-+ *
-+ * Same rules as for phy_read() and phy_write().
-+ */
-+int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
-+		     u16 mask, u16 set)
-+{
-+	int ret = 0, oldpage;
-+
-+	oldpage = phy_select_page(phydev, page);
-+	if (oldpage >= 0)
-+		ret = __phy_modify(phydev, regnum, mask, set);
-+
-+	return phy_restore_page(phydev, oldpage, ret);
-+}
-+EXPORT_SYMBOL(phy_modify_paged);
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -644,6 +644,9 @@ struct phy_driver {
- 	int (*write_mmd)(struct phy_device *dev, int devnum, u16 regnum,
- 			 u16 val);
- 
-+	int (*read_page)(struct phy_device *dev);
-+	int (*write_page)(struct phy_device *dev, int page);
-+
- 	/* Get the size and type of the eeprom contained within a plug-in
- 	 * module */
- 	int (*module_info)(struct phy_device *dev,
-@@ -832,6 +835,14 @@ static inline bool phy_is_pseudo_fixed_l
-  */
- int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
- 
-+int phy_save_page(struct phy_device *phydev);
-+int phy_select_page(struct phy_device *phydev, int page);
-+int phy_restore_page(struct phy_device *phydev, int oldpage, int ret);
-+int phy_read_paged(struct phy_device *phydev, int page, u32 regnum);
-+int phy_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val);
-+int phy_modify_paged(struct phy_device *phydev, int page, u32 regnum,
-+		     u16 mask, u16 set);
-+
- struct phy_device *phy_device_create(struct mii_bus *bus, int addr, int phy_id,
- 				     bool is_c45,
- 				     struct phy_c45_device_ids *c45_ids);
diff --git a/target/linux/brcm2708/patches-4.14/950-0296-lan78xx-PHY-DSP-registers-initialization-to-address-.patch b/target/linux/brcm2708/patches-4.14/950-0296-lan78xx-PHY-DSP-registers-initialization-to-address-.patch
deleted file mode 100644
index f2e40fb01..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0296-lan78xx-PHY-DSP-registers-initialization-to-address-.patch
+++ /dev/null
@@ -1,256 +0,0 @@
-From 07667014469b0e1464d1cd77d0b42d523fd3ad46 Mon Sep 17 00:00:00 2001
-From: Raghuram Chary J <raghuramchary.jallipalli@microchip.com>
-Date: Wed, 11 Apr 2018 20:36:36 +0530
-Subject: [PATCH 296/454] lan78xx: PHY DSP registers initialization to address
- EEE link drop issues with long cables
-
-commit 1c2734b31d72316e3faaad88c0c9c46fa92a4b20 upstream.
-
-The patch is to configure DSP registers of PHY device
-to handle Gbe-EEE failures with >40m cable length.
-
-Fixes: 55d7de9de6c3 ("Microchip's LAN7800 family USB 2/3 to 10/100/1000 Ethernet device driver")
-Signed-off-by: Raghuram Chary J <raghuramchary.jallipalli@microchip.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/phy/microchip.c  | 178 ++++++++++++++++++++++++++++++++++-
- include/linux/microchipphy.h |   8 ++
- 2 files changed, 185 insertions(+), 1 deletion(-)
-
---- a/drivers/net/phy/microchip.c
-+++ b/drivers/net/phy/microchip.c
-@@ -20,6 +20,7 @@
- #include <linux/ethtool.h>
- #include <linux/phy.h>
- #include <linux/microchipphy.h>
-+#include <linux/delay.h>
- 
- #define DRIVER_AUTHOR	"WOOJUNG HUH <woojung.huh@microchip.com>"
- #define DRIVER_DESC	"Microchip LAN88XX PHY driver"
-@@ -30,6 +31,16 @@ struct lan88xx_priv {
- 	__u32	wolopts;
- };
- 
-+static int lan88xx_read_page(struct phy_device *phydev)
-+{
-+	return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
-+}
-+
-+static int lan88xx_write_page(struct phy_device *phydev, int page)
-+{
-+	return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
-+}
-+
- static int lan88xx_phy_config_intr(struct phy_device *phydev)
- {
- 	int rc;
-@@ -66,6 +77,150 @@ static int lan88xx_suspend(struct phy_de
- 	return 0;
- }
- 
-+static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
-+			      u32 data)
-+{
-+	int val, save_page, ret = 0;
-+	u16 buf;
-+
-+	/* Save current page */
-+	save_page = phy_save_page(phydev);
-+	if (save_page < 0) {
-+		pr_warn("Failed to get current page\n");
-+		goto err;
-+	}
-+
-+	/* Switch to TR page */
-+	lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
-+
-+	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
-+			  (data & 0xFFFF));
-+	if (ret < 0) {
-+		pr_warn("Failed to write TR low data\n");
-+		goto err;
-+	}
-+
-+	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
-+			  (data & 0x00FF0000) >> 16);
-+	if (ret < 0) {
-+		pr_warn("Failed to write TR high data\n");
-+		goto err;
-+	}
-+
-+	/* Config control bits [15:13] of register */
-+	buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
-+	buf |= 0x8000; /* Set [15] to Packet transmit */
-+
-+	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
-+	if (ret < 0) {
-+		pr_warn("Failed to write data in reg\n");
-+		goto err;
-+	}
-+
-+	usleep_range(1000, 2000);/* Wait for Data to be written */
-+	val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
-+	if (!(val & 0x8000))
-+		pr_warn("TR Register[0x%X] configuration failed\n", regaddr);
-+err:
-+	return phy_restore_page(phydev, save_page, ret);
-+}
-+
-+static void lan88xx_config_TR_regs(struct phy_device *phydev)
-+{
-+	int err;
-+
-+	/* Get access to Channel 0x1, Node 0xF , Register 0x01.
-+	 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
-+	 * MrvlTrFix1000Kp, MasterEnableTR bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x0F82]\n");
-+
-+	/* Get access to Channel b'10, Node b'1101, Register 0x06.
-+	 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
-+	 * SSTrKp1000Mas bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x168C]\n");
-+
-+	/* Get access to Channel b'10, Node b'1111, Register 0x11.
-+	 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
-+	 * bits
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x17A2]\n");
-+
-+	/* Get access to Channel b'10, Node b'1101, Register 0x10.
-+	 * Write 24-bit value 0xEEFFDD to register. Setting
-+	 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
-+	 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x16A0]\n");
-+
-+	/* Get access to Channel b'10, Node b'1101, Register 0x13.
-+	 * Write 24-bit value 0x071448 to register. Setting
-+	 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x16A6]\n");
-+
-+	/* Get access to Channel b'10, Node b'1101, Register 0x12.
-+	 * Write 24-bit value 0x13132F to register. Setting
-+	 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x16A4]\n");
-+
-+	/* Get access to Channel b'10, Node b'1101, Register 0x14.
-+	 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
-+	 * eee_TrKf_freeze_delay bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x16A8]\n");
-+
-+	/* Get access to Channel b'01, Node b'1111, Register 0x34.
-+	 * Write 24-bit value 0x91B06C to register. Setting
-+	 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
-+	 * FastMseSearchUpdGain1000 bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x0FE8]\n");
-+
-+	/* Get access to Channel b'01, Node b'1111, Register 0x3E.
-+	 * Write 24-bit value 0xC0A028 to register. Setting
-+	 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
-+	 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x0FFC]\n");
-+
-+	/* Get access to Channel b'01, Node b'1111, Register 0x35.
-+	 * Write 24-bit value 0x041600 to register. Setting
-+	 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
-+	 * FastMsePhChangeDelay1000 bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x0FEA]\n");
-+
-+	/* Get access to Channel b'10, Node b'1101, Register 0x03.
-+	 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
-+	 */
-+	err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
-+	if (err < 0)
-+		pr_warn("Failed to Set Register[0x1686]\n");
-+}
-+
- static int lan88xx_probe(struct phy_device *phydev)
- {
- 	struct device *dev = &phydev->mdio.dev;
-@@ -132,6 +287,25 @@ static void lan88xx_set_mdix(struct phy_
- 	phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
- }
- 
-+static int lan88xx_config_init(struct phy_device *phydev)
-+{
-+	int val;
-+
-+	genphy_config_init(phydev);
-+	/*Zerodetect delay enable */
-+	val = phy_read_mmd(phydev, MDIO_MMD_PCS,
-+			   PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
-+	val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
-+
-+	phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
-+		      val);
-+
-+	/* Config DSP registers */
-+	lan88xx_config_TR_regs(phydev);
-+
-+	return 0;
-+}
-+
- static int lan88xx_config_aneg(struct phy_device *phydev)
- {
- 	lan88xx_set_mdix(phydev);
-@@ -151,7 +325,7 @@ static struct phy_driver microchip_phy_d
- 	.probe		= lan88xx_probe,
- 	.remove		= lan88xx_remove,
- 
--	.config_init	= genphy_config_init,
-+	.config_init	= lan88xx_config_init,
- 	.config_aneg	= lan88xx_config_aneg,
- 	.read_status	= genphy_read_status,
- 
-@@ -161,6 +335,8 @@ static struct phy_driver microchip_phy_d
- 	.suspend	= lan88xx_suspend,
- 	.resume		= genphy_resume,
- 	.set_wol	= lan88xx_set_wol,
-+	.read_page	= lan88xx_read_page,
-+	.write_page	= lan88xx_write_page,
- } };
- 
- module_phy_driver(microchip_phy_driver);
---- a/include/linux/microchipphy.h
-+++ b/include/linux/microchipphy.h
-@@ -70,4 +70,12 @@
- #define	LAN88XX_MMD3_CHIP_ID			(32877)
- #define	LAN88XX_MMD3_CHIP_REV			(32878)
- 
-+/* DSP registers */
-+#define PHY_ARDENNES_MMD_DEV_3_PHY_CFG		(0x806A)
-+#define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_	(0x2000)
-+#define LAN88XX_EXT_PAGE_ACCESS_TR		(0x52B5)
-+#define LAN88XX_EXT_PAGE_TR_CR			16
-+#define LAN88XX_EXT_PAGE_TR_LOW_DATA		17
-+#define LAN88XX_EXT_PAGE_TR_HIGH_DATA		18
-+
- #endif /* _MICROCHIPPHY_H */
diff --git a/target/linux/brcm2708/patches-4.14/950-0297-Cleanup-of-bcm2708_fb-file-to-kernel-coding-standard.patch b/target/linux/brcm2708/patches-4.14/950-0297-Cleanup-of-bcm2708_fb-file-to-kernel-coding-standard.patch
deleted file mode 100644
index c0007282f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0297-Cleanup-of-bcm2708_fb-file-to-kernel-coding-standard.patch
+++ /dev/null
@@ -1,354 +0,0 @@
-From dc1c33574c4dcf24192cb219ea6caaf2c7804eef Mon Sep 17 00:00:00 2001
-From: James Hughes <james.hughes@raspberrypi.org>
-Date: Thu, 10 May 2018 11:34:38 +0100
-Subject: [PATCH 297/454] Cleanup of bcm2708_fb file to kernel coding standards
-
-Some minor change to function - remove a use of
-in_atomic, plus replacing various debug messages
-that manually specify the function name with
-("%s",.__func__)
-
-Signed-off-by: James Hughes <james.hughes@raspberrypi.org>
----
- drivers/video/fbdev/bcm2708_fb.c | 136 ++++++++++++++++++-------------
- 1 file changed, 81 insertions(+), 55 deletions(-)
-
---- a/drivers/video/fbdev/bcm2708_fb.c
-+++ b/drivers/video/fbdev/bcm2708_fb.c
-@@ -41,9 +41,10 @@
- #define MODULE_NAME "bcm2708_fb"
- 
- #ifdef BCM2708_FB_DEBUG
--#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
-+#define print_debug(fmt, ...) pr_debug("%s:%s:%d: "fmt, \
-+			MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)
- #else
--#define print_debug(fmt,...)
-+#define print_debug(fmt, ...)
- #endif
- 
- /* This is limited to 16 characters when displayed by X startup */
-@@ -51,10 +52,10 @@ static const char *bcm2708_name = "BCM27
- 
- #define DRIVER_NAME "bcm2708_fb"
- 
--static int fbwidth = 800;  /* module parameter */
--static int fbheight = 480; /* module parameter */
--static int fbdepth = 32;   /* module parameter */
--static int fbswap = 0;     /* module parameter */
-+static int fbwidth = 800;	/* module parameter */
-+static int fbheight = 480;	/* module parameter */
-+static int fbdepth = 32;	/* module parameter */
-+static int fbswap;		/* module parameter */
- 
- static u32 dma_busy_wait_threshold = 1<<15;
- module_param(dma_busy_wait_threshold, int, 0644);
-@@ -221,11 +222,13 @@ static int bcm2708_fb_check_var(struct f
- 				struct fb_info *info)
- {
- 	/* info input, var output */
--	print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info,
-+	print_debug("%s(%p) %dx%d (%dx%d), %d, %d\n",
-+		__func__,
-+		info,
- 		info->var.xres, info->var.yres, info->var.xres_virtual,
- 		info->var.yres_virtual, (int)info->screen_size,
- 		info->var.bits_per_pixel);
--	print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var,
-+	print_debug("%s(%p) %dx%d (%dx%d), %d\n", __func__, var,
- 		var->xres, var->yres, var->xres_virtual, var->yres_virtual,
- 		var->bits_per_pixel);
- 
-@@ -233,7 +236,7 @@ static int bcm2708_fb_check_var(struct f
- 		var->bits_per_pixel = 16;
- 
- 	if (bcm2708_fb_set_bitfields(var) != 0) {
--		pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n",
-+		pr_err("%s: invalid bits_per_pixel %d\n", __func__,
- 		     var->bits_per_pixel);
- 		return -EINVAL;
- 	}
-@@ -245,9 +248,8 @@ static int bcm2708_fb_check_var(struct f
- 	if (var->yres_virtual == -1) {
- 		var->yres_virtual = 480;
- 
--		pr_err
--		    ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n",
--		     var->xres_virtual, var->yres_virtual);
-+		pr_err("%s: virtual resolution set to maximum of %dx%d\n",
-+		     __func__, var->xres_virtual, var->yres_virtual);
- 	}
- 	if (var->yres_virtual < var->yres)
- 		var->yres_virtual = var->yres;
-@@ -291,7 +293,7 @@ static int bcm2708_fb_set_par(struct fb_
- 	};
- 	int ret;
- 
--	print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info,
-+	print_debug("%s(%p) %dx%d (%dx%d), %d, %d\n", __func__, info,
- 		info->var.xres, info->var.yres, info->var.xres_virtual,
- 		info->var.yres_virtual, (int)info->screen_size,
- 		info->var.bits_per_pixel);
-@@ -326,11 +328,12 @@ static int bcm2708_fb_set_par(struct fb_
- 		return -ENOMEM;
- 	}
- 
--	print_debug
--	    ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d\n",
--	     (void *)fb->fb.screen_base, (void *)fb->fb_bus_address,
--	     fbinfo.xres, fbinfo.yres, fbinfo.bpp,
--	     fbinfo.pitch, (int)fb->fb.screen_size);
-+	print_debug(
-+	  "%s: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d\n",
-+	  __func__,
-+	  (void *)fb->fb.screen_base, (void *)fb->fb_bus_address,
-+	  fbinfo.xres, fbinfo.yres, fbinfo.bpp,
-+	  fbinfo.pitch, (int)fb->fb.screen_size);
- 
- 	return 0;
- }
-@@ -349,7 +352,6 @@ static int bcm2708_fb_setcolreg(unsigned
- {
- 	struct bcm2708_fb *fb = to_bcm2708(info);
- 
--	/*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/
- 	if (fb->fb.var.bits_per_pixel <= 8) {
- 		if (regno < 256) {
- 			/* blue [23:16], green [15:8], red [7:0] */
-@@ -357,8 +359,12 @@ static int bcm2708_fb_setcolreg(unsigned
- 					      ((green >> 8) & 0xff) << 8 |
- 					      ((blue  >> 8) & 0xff) << 16;
- 		}
--		/* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */
--		/* So just call it for what looks like the last colour in a list for now. */
-+		/* Hack: we need to tell GPU the palette has changed, but
-+		 * currently bcm2708_fb_set_par takes noticeable time when
-+		 * called for every (256) colour
-+		 * So just call it for what looks like the last colour in a
-+		 * list for now.
-+		 */
- 		if (regno == 15 || regno == 255) {
- 			struct packet {
- 				u32 offset;
-@@ -372,19 +378,23 @@ static int bcm2708_fb_setcolreg(unsigned
- 				return -ENOMEM;
- 			packet->offset = 0;
- 			packet->length = regno + 1;
--			memcpy(packet->cmap, fb->gpu_cmap, sizeof(packet->cmap));
--			ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE,
--						    packet, (2 + packet->length) * sizeof(u32));
-+			memcpy(packet->cmap, fb->gpu_cmap,
-+				sizeof(packet->cmap));
-+			ret = rpi_firmware_property(fb->fw,
-+					RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE,
-+					packet,
-+					(2 + packet->length) * sizeof(u32));
- 			if (ret || packet->offset)
--				dev_err(info->device, "Failed to set palette (%d,%u)\n",
-+				dev_err(info->device,
-+					"Failed to set palette (%d,%u)\n",
- 					ret, packet->offset);
- 			kfree(packet);
- 		}
--        } else if (regno < 16) {
-+	} else if (regno < 16) {
- 		fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
--		    convert_bitfield(blue, &fb->fb.var.blue) |
--		    convert_bitfield(green, &fb->fb.var.green) |
--		    convert_bitfield(red, &fb->fb.var.red);
-+		convert_bitfield(blue, &fb->fb.var.blue) |
-+		convert_bitfield(green, &fb->fb.var.green) |
-+		convert_bitfield(red, &fb->fb.var.red);
- 	}
- 	return regno > 255;
- }
-@@ -412,24 +422,28 @@ static int bcm2708_fb_blank(int blank_mo
- 	ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK,
- 				    &value, sizeof(value));
- 	if (ret)
--		dev_err(info->device, "bcm2708_fb_blank(%d) failed: %d\n",
-+		dev_err(info->device, "%s(%d) failed: %d\n", __func__,
- 			blank_mode, ret);
- 
- 	return ret;
- }
- 
--static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
-+static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var,
-+				  struct fb_info *info)
- {
- 	s32 result;
-+
- 	info->var.xoffset = var->xoffset;
- 	info->var.yoffset = var->yoffset;
- 	result = bcm2708_fb_set_par(info);
- 	if (result != 0)
--		pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result);
-+		pr_err("%s(%d,%d) returns=%d\n", __func__,
-+			var->xoffset, var->yoffset, result);
- 	return result;
- }
- 
--static void dma_memcpy(struct bcm2708_fb *fb, dma_addr_t dst, dma_addr_t src, int size)
-+static void dma_memcpy(struct bcm2708_fb *fb, dma_addr_t dst, dma_addr_t src,
-+		       int size)
- {
- 	int burst_size = (fb->dma_chan == 0) ? 8 : 2;
- 	struct bcm2708_dma_cb *cb = fb->cb_base;
-@@ -450,6 +464,7 @@ static void dma_memcpy(struct bcm2708_fb
- 		bcm_dma_wait_idle(fb->dma_chan_base);
- 	} else {
- 		void __iomem *dma_chan = fb->dma_chan_base;
-+
- 		cb->info |= BCM2708_DMA_INT_EN;
- 		bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
- 		while (bcm_dma_is_busy(dma_chan)) {
-@@ -462,8 +477,10 @@ static void dma_memcpy(struct bcm2708_fb
- 	fb->stats.dma_copies++;
- }
- 
--#define INTALIAS_NORMAL(x) ((x)&~0xc0000000) // address with no aliases
--#define INTALIAS_L1L2_NONALLOCATING(x) (((x)&~0xc0000000)|0x80000000) // cache coherent but non-allocating in L1 and L2
-+/* address with no aliases */
-+#define INTALIAS_NORMAL(x) ((x)&~0xc0000000)
-+/* cache coherent but non-allocating in L1 and L2 */
-+#define INTALIAS_L1L2_NONALLOCATING(x) (((x)&~0xc0000000)|0x80000000)
- 
- static long vc_mem_copy(struct bcm2708_fb *fb, unsigned long arg)
- {
-@@ -475,8 +492,7 @@ static long vc_mem_copy(struct bcm2708_f
- 	size_t offset;
- 
- 	/* restrict this to root user */
--	if (!uid_eq(current_euid(), GLOBAL_ROOT_UID))
--	{
-+	if (!uid_eq(current_euid(), GLOBAL_ROOT_UID)) {
- 		rc = -EFAULT;
- 		goto out;
- 	}
-@@ -492,12 +508,16 @@ static long vc_mem_copy(struct bcm2708_f
- 	}
- 
- 	if (fb->gpu.base == 0 || fb->gpu.length == 0) {
--		pr_err("[%s]: Unable to determine gpu memory (%x,%x)\n", __func__, fb->gpu.base, fb->gpu.length);
-+		pr_err("[%s]: Unable to determine gpu memory (%x,%x)\n",
-+			__func__, fb->gpu.base, fb->gpu.length);
- 		return -EFAULT;
- 	}
- 
--	if (INTALIAS_NORMAL(ioparam.src) < fb->gpu.base || INTALIAS_NORMAL(ioparam.src) >= fb->gpu.base + fb->gpu.length) {
--		pr_err("[%s]: Invalid memory access %x (%x-%x)", __func__, INTALIAS_NORMAL(ioparam.src), fb->gpu.base, fb->gpu.base + fb->gpu.length);
-+	if (INTALIAS_NORMAL(ioparam.src) < fb->gpu.base ||
-+		INTALIAS_NORMAL(ioparam.src) >= fb->gpu.base + fb->gpu.length) {
-+		pr_err("[%s]: Invalid memory access %x (%x-%x)", __func__,
-+			INTALIAS_NORMAL(ioparam.src), fb->gpu.base,
-+			fb->gpu.base + fb->gpu.length);
- 		return -EFAULT;
- 	}
- 
-@@ -515,7 +535,9 @@ static long vc_mem_copy(struct bcm2708_f
- 		size_t s = min(size, remaining);
- 		unsigned char *p = (unsigned char *)ioparam.src + offset;
- 		unsigned char *q = (unsigned char *)ioparam.dst + offset;
--		dma_memcpy(fb, bus_addr, INTALIAS_L1L2_NONALLOCATING((dma_addr_t)p), size);
-+
-+		dma_memcpy(fb, bus_addr,
-+			   INTALIAS_L1L2_NONALLOCATING((dma_addr_t)p), size);
- 		if (copy_to_user(q, buf, s) != 0) {
- 			pr_err("[%s]: failed to copy-to-user\n",
- 					__func__);
-@@ -525,11 +547,13 @@ static long vc_mem_copy(struct bcm2708_f
- 	}
- out:
- 	if (buf)
--		dma_free_coherent(fb->fb.device, PAGE_ALIGN(size), buf, bus_addr);
-+		dma_free_coherent(fb->fb.device, PAGE_ALIGN(size), buf,
-+				  bus_addr);
- 	return rc;
- }
- 
--static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
-+static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd,
-+			 unsigned long arg)
- {
- 	struct bcm2708_fb *fb = to_bcm2708(info);
- 	u32 dummy = 0;
-@@ -593,13 +617,13 @@ static void bcm2708_fb_copyarea(struct f
- 	struct bcm2708_fb *fb = to_bcm2708(info);
- 	struct bcm2708_dma_cb *cb = fb->cb_base;
- 	int bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3;
-+
- 	/* Channel 0 supports larger bursts and is a bit faster */
- 	int burst_size = (fb->dma_chan == 0) ? 8 : 2;
- 	int pixels = region->width * region->height;
- 
- 	/* Fallback to cfb_copyarea() if we don't like something */
--	if (in_atomic() ||
--	    bytes_per_pixel > 4 ||
-+	if (bytes_per_pixel > 4 ||
- 	    info->var.xres * info->var.yres > 1920 * 1200 ||
- 	    region->width <= 0 || region->width > info->var.xres ||
- 	    region->height <= 0 || region->height > info->var.yres ||
-@@ -663,6 +687,7 @@ static void bcm2708_fb_copyarea(struct f
- 	} else {
- 		/* A single dma control block is enough. */
- 		int sy, dy, stride;
-+
- 		if (region->dy <= region->sy) {
- 			/* processing from top to bottom */
- 			dy = region->dy;
-@@ -694,6 +719,7 @@ static void bcm2708_fb_copyarea(struct f
- 		bcm_dma_wait_idle(fb->dma_chan_base);
- 	} else {
- 		void __iomem *dma_chan = fb->dma_chan_base;
-+
- 		cb->info |= BCM2708_DMA_INT_EN;
- 		bcm_dma_start(fb->dma_chan_base, fb->cb_handle);
- 		while (bcm_dma_is_busy(dma_chan)) {
-@@ -791,8 +817,8 @@ static int bcm2708_fb_register(struct bc
- 	if (ret)
- 		return ret;
- 
--	print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n", fbwidth,
--		fbheight, fbdepth, fbswap);
-+	print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n",
-+		fbwidth, fbheight, fbdepth, fbswap);
- 
- 	ret = register_framebuffer(&fb->fb);
- 	print_debug("BCM2708FB: register framebuffer (%d)\n", ret);
-@@ -813,19 +839,17 @@ static int bcm2708_fb_probe(struct platf
- 
- 	fw_np = of_parse_phandle(dev->dev.of_node, "firmware", 0);
- /* Remove comment when booting without Device Tree is no longer supported
--	if (!fw_np) {
--		dev_err(&dev->dev, "Missing firmware node\n");
--		return -ENOENT;
--	}
--*/
-+ *	if (!fw_np) {
-+ *		dev_err(&dev->dev, "Missing firmware node\n");
-+ *		return -ENOENT;
-+ *	}
-+ */
- 	fw = rpi_firmware_get(fw_np);
- 	if (!fw)
- 		return -EPROBE_DEFER;
- 
- 	fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL);
- 	if (!fb) {
--		dev_err(&dev->dev,
--			"could not allocate new bcm2708_fb struct\n");
- 		ret = -ENOMEM;
- 		goto free_region;
- 	}
-@@ -866,7 +890,9 @@ static int bcm2708_fb_probe(struct platf
- 	fb->dev = dev;
- 	fb->fb.device = &dev->dev;
- 
--	// failure here isn't fatal, but we'll fail in vc_mem_copy if fb->gpu is not valid
-+	/* failure here isn't fatal, but we'll fail in vc_mem_copy if
-+	 * fb->gpu is not valid
-+	 */
- 	rpi_firmware_property(fb->fw,
- 				    RPI_FIRMWARE_GET_VC_MEMORY,
- 				    &fb->gpu, sizeof(fb->gpu));
diff --git a/target/linux/brcm2708/patches-4.14/950-0298-Add-ability-to-export-gpio-used-by-gpio-poweroff.patch b/target/linux/brcm2708/patches-4.14/950-0298-Add-ability-to-export-gpio-used-by-gpio-poweroff.patch
deleted file mode 100644
index 87cad9a30..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0298-Add-ability-to-export-gpio-used-by-gpio-poweroff.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 62712a1a87724194500e1786a65578964838f4d8 Mon Sep 17 00:00:00 2001
-From: Nick Bulleid <nedbulleid@fastmail.com>
-Date: Thu, 10 May 2018 21:57:02 +0100
-Subject: [PATCH 298/454] Add ability to export gpio used by gpio-poweroff
-
-Signed-off-by: Nick Bulleid <nedbulleid@fastmail.com>
----
- drivers/power/reset/gpio-poweroff.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/drivers/power/reset/gpio-poweroff.c
-+++ b/drivers/power/reset/gpio-poweroff.c
-@@ -50,6 +50,7 @@ static int gpio_poweroff_probe(struct pl
- 	bool input = false;
- 	enum gpiod_flags flags;
- 	bool force = false;
-+	bool export = false;
- 
- 	/* If a pm_power_off function has already been added, leave it alone */
- 	force = of_property_read_bool(pdev->dev.of_node, "force");
-@@ -70,6 +71,12 @@ static int gpio_poweroff_probe(struct pl
- 	if (IS_ERR(reset_gpio))
- 		return PTR_ERR(reset_gpio);
- 
-+	export = of_property_read_bool(pdev->dev.of_node, "export");
-+	if (export) {
-+		gpiod_export(reset_gpio, false);
-+		gpiod_export_link(&pdev->dev, "poweroff-gpio", reset_gpio);
-+	}
-+
- 	pm_power_off = &gpio_poweroff_do_poweroff;
- 	return 0;
- }
-@@ -79,6 +86,8 @@ static int gpio_poweroff_remove(struct p
- 	if (pm_power_off == &gpio_poweroff_do_poweroff)
- 		pm_power_off = NULL;
- 
-+	gpiod_unexport(reset_gpio);
-+
- 	return 0;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0299-Added-export-feature-to-gpio-poweroff-documentation.patch b/target/linux/brcm2708/patches-4.14/950-0299-Added-export-feature-to-gpio-poweroff-documentation.patch
deleted file mode 100644
index 51b39ad38..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0299-Added-export-feature-to-gpio-poweroff-documentation.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 052669bc0d8bba9b93009eedb66c6e9d00a27034 Mon Sep 17 00:00:00 2001
-From: Nick Bulleid <nedbulleid@fastmail.com>
-Date: Sat, 12 May 2018 20:44:34 +0100
-Subject: [PATCH 299/454] Added export feature to gpio-poweroff documentation
-
-Signed-off-by: Nick Bulleid <nedbulleid@fastmail.com>
----
- Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
-+++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
-@@ -27,6 +27,7 @@ Optional properties:
-   it to an output when the power-off handler is called. If this optional
-   property is not specified, the GPIO is initialized as an output in its
-   inactive state.
-+- export : Export the GPIO line to the sysfs system
- 
- Examples:
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0300-Updated-the-gpio-poweroff-overlay-and-README-entry.patch b/target/linux/brcm2708/patches-4.14/950-0300-Updated-the-gpio-poweroff-overlay-and-README-entry.patch
deleted file mode 100644
index 9fc0058b8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0300-Updated-the-gpio-poweroff-overlay-and-README-entry.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From ef6742d53869f0a8da5aacdb6b4cd13fb5540369 Mon Sep 17 00:00:00 2001
-From: Nick Bulleid <nedbulleid@fastmail.com>
-Date: Sat, 12 May 2018 23:22:37 +0100
-Subject: [PATCH 300/454] Updated the gpio-poweroff overlay and README entry
-
-Signed-off-by: Nick Bulleid <nedbulleid@fastmail.com>
----
- arch/arm/boot/dts/overlays/README                    | 3 +++
- arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts | 2 ++
- 2 files changed, 5 insertions(+)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -595,6 +595,9 @@ Params: gpiopin                 GPIO for
-                                 custom dt-blob.bin to prevent a power-down
-                                 during the boot process, and that a reboot
-                                 will also cause the pin to go low.
-+        input                   Set if the gpio pin should be configured as
-+                                an input.
-+        export                  Set to export the configured pin to sysfs
- 
- 
- Name:   gpio-shutdown
---- a/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts
-@@ -30,5 +30,7 @@
- 		gpiopin =       <&power_ctrl>,"gpios:4",
- 				<&power_ctrl_pins>,"brcm,pins:0";
- 		active_low =    <&power_ctrl>,"gpios:8";
-+		input =         <&power_ctrl>,"input?";
-+		export =        <&power_ctrl>,"export?";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0301-config-Add-CONFIG_DM_CACHE.patch b/target/linux/brcm2708/patches-4.14/950-0301-config-Add-CONFIG_DM_CACHE.patch
deleted file mode 100644
index 9ffe16afa..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0301-config-Add-CONFIG_DM_CACHE.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 1bad7d55534c019f27f23242247c215866da8734 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sun, 13 May 2018 21:10:10 +0100
-Subject: [PATCH 301/454] config: Add CONFIG_DM_CACHE
-
-See: https://github.com/raspberrypi/linux/issues/2553
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig   | 1 +
- arch/arm/configs/bcmrpi_defconfig    | 1 +
- arch/arm64/configs/bcmrpi3_defconfig | 1 +
- 3 files changed, 3 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -428,6 +428,7 @@ CONFIG_BLK_DEV_DM=m
- CONFIG_DM_CRYPT=m
- CONFIG_DM_SNAPSHOT=m
- CONFIG_DM_THIN_PROVISIONING=m
-+CONFIG_DM_CACHE=m
- CONFIG_DM_MIRROR=m
- CONFIG_DM_LOG_USERSPACE=m
- CONFIG_DM_RAID=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -423,6 +423,7 @@ CONFIG_BLK_DEV_DM=m
- CONFIG_DM_CRYPT=m
- CONFIG_DM_SNAPSHOT=m
- CONFIG_DM_THIN_PROVISIONING=m
-+CONFIG_DM_CACHE=m
- CONFIG_DM_MIRROR=m
- CONFIG_DM_LOG_USERSPACE=m
- CONFIG_DM_RAID=m
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -415,6 +415,7 @@ CONFIG_BLK_DEV_DM=m
- CONFIG_DM_CRYPT=m
- CONFIG_DM_SNAPSHOT=m
- CONFIG_DM_THIN_PROVISIONING=m
-+CONFIG_DM_CACHE=m
- CONFIG_DM_MIRROR=m
- CONFIG_DM_LOG_USERSPACE=m
- CONFIG_DM_RAID=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0302-firmware-raspberrypi-Add-two-new-messages.patch b/target/linux/brcm2708/patches-4.14/950-0302-firmware-raspberrypi-Add-two-new-messages.patch
deleted file mode 100644
index e7684cbd5..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0302-firmware-raspberrypi-Add-two-new-messages.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 9337adb131fdee07328d8686cdb6b5e2a885baa0 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sat, 12 May 2018 21:23:00 +0100
-Subject: [PATCH 302/454] firmware/raspberrypi: Add two new messages
-
-RPI_FIRMWARE_GET_CLOCK_MEASURED is similar to RPI_FIRMWARE_GET_CLOCK,
-except that it uses a hardware feature to count the clock pulses to
-measure the real clock speed.
-
-RPI_FIRMWARE_NOTIFY_REBOOT informs the firmware that the OS is about to
-reboot, allowing it to make any necessary adjustments.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- include/soc/bcm2835/raspberrypi-firmware.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/soc/bcm2835/raspberrypi-firmware.h
-+++ b/include/soc/bcm2835/raspberrypi-firmware.h
-@@ -78,6 +78,8 @@ enum rpi_firmware_property_tag {
- 	RPI_FIRMWARE_GET_CUSTOMER_OTP =                       0x00030021,
- 	RPI_FIRMWARE_GET_DOMAIN_STATE =                       0x00030030,
- 	RPI_FIRMWARE_GET_THROTTLED =                          0x00030046,
-+	RPI_FIRMWARE_GET_CLOCK_MEASURED =                     0x00030047,
-+	RPI_FIRMWARE_NOTIFY_REBOOT =                          0x00030048,
- 	RPI_FIRMWARE_SET_CLOCK_STATE =                        0x00038001,
- 	RPI_FIRMWARE_SET_CLOCK_RATE =                         0x00038002,
- 	RPI_FIRMWARE_SET_VOLTAGE =                            0x00038003,
diff --git a/target/linux/brcm2708/patches-4.14/950-0303-firmware-raspberrypi-Notify-firmware-of-a-reboot.patch b/target/linux/brcm2708/patches-4.14/950-0303-firmware-raspberrypi-Notify-firmware-of-a-reboot.patch
deleted file mode 100644
index 09a2f68c1..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0303-firmware-raspberrypi-Notify-firmware-of-a-reboot.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From ae200d1bf8417e24ae3445092d75fc10dd7319b7 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sat, 12 May 2018 21:35:43 +0100
-Subject: [PATCH 303/454] firmware/raspberrypi: Notify firmware of a reboot
-
-Register for reboot notifications, sending RPI_FIRMWARE_NOTIFY_REBOOT
-over the mailbox interface on reception.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/firmware/raspberrypi.c | 40 +++++++++++++++++++++++++++++++++-
- 1 file changed, 39 insertions(+), 1 deletion(-)
-
---- a/drivers/firmware/raspberrypi.c
-+++ b/drivers/firmware/raspberrypi.c
-@@ -14,6 +14,7 @@
- #include <linux/module.h>
- #include <linux/of_platform.h>
- #include <linux/platform_device.h>
-+#include <linux/reboot.h>
- #include <linux/workqueue.h>
- #include <soc/bcm2835/raspberrypi-firmware.h>
- 
-@@ -275,6 +276,26 @@ static int rpi_firmware_get_throttled(st
- 	return 0;
- }
- 
-+static int rpi_firmware_notify_reboot(struct notifier_block *nb,
-+				      unsigned long action,
-+				      void *data)
-+{
-+	struct rpi_firmware *fw;
-+	struct platform_device *pdev = g_pdev;
-+
-+	if (!pdev)
-+		return 0;
-+
-+	fw = platform_get_drvdata(pdev);
-+	if (!fw)
-+		return 0;
-+
-+	(void)rpi_firmware_property(fw, RPI_FIRMWARE_NOTIFY_REBOOT,
-+				    0, 0);
-+
-+	return 0;
-+}
-+
- static void get_throttled_poll(struct work_struct *work)
- {
- 	struct rpi_firmware *fw = container_of(work, struct rpi_firmware,
-@@ -416,15 +437,32 @@ static struct platform_driver rpi_firmwa
- 	.remove		= rpi_firmware_remove,
- };
- 
-+static struct notifier_block rpi_firmware_reboot_notifier = {
-+	.notifier_call = rpi_firmware_notify_reboot,
-+};
-+
- static int __init rpi_firmware_init(void)
- {
--	return platform_driver_register(&rpi_firmware_driver);
-+	int ret = register_reboot_notifier(&rpi_firmware_reboot_notifier);
-+	if (ret)
-+		goto out1;
-+	ret = platform_driver_register(&rpi_firmware_driver);
-+	if (ret)
-+		goto out2;
-+
-+	return 0;
-+
-+out2:
-+	unregister_reboot_notifier(&rpi_firmware_reboot_notifier);
-+out1:
-+	return ret;
- }
- subsys_initcall(rpi_firmware_init);
- 
- static void __init rpi_firmware_exit(void)
- {
- 	platform_driver_unregister(&rpi_firmware_driver);
-+	unregister_reboot_notifier(&rpi_firmware_reboot_notifier);
- }
- module_exit(rpi_firmware_exit);
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0304-config-Add-CONFIG_MTD_BLOCK2MTD-m.patch b/target/linux/brcm2708/patches-4.14/950-0304-config-Add-CONFIG_MTD_BLOCK2MTD-m.patch
deleted file mode 100644
index 38ca4fcc4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0304-config-Add-CONFIG_MTD_BLOCK2MTD-m.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 103322cdf8f3d2cfc92b4025930b6e8ff3dafb11 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sun, 20 May 2018 14:35:16 +0100
-Subject: [PATCH 304/454] config: Add CONFIG_MTD_BLOCK2MTD=m
-
-See: https://github.com/raspberrypi/linux/issues/2163
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -398,6 +398,7 @@ CONFIG_CMA_SIZE_MBYTES=5
- CONFIG_MTD=m
- CONFIG_MTD_BLOCK=m
- CONFIG_MTD_M25P80=m
-+CONFIG_MTD_BLOCK2MTD=m
- CONFIG_MTD_NAND=m
- CONFIG_MTD_SPI_NOR=m
- CONFIG_MTD_UBI=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -393,6 +393,7 @@ CONFIG_CMA_SIZE_MBYTES=5
- CONFIG_MTD=m
- CONFIG_MTD_BLOCK=m
- CONFIG_MTD_M25P80=m
-+CONFIG_MTD_BLOCK2MTD=m
- CONFIG_MTD_NAND=m
- CONFIG_MTD_SPI_NOR=m
- CONFIG_MTD_UBI=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0305-config-Add-LZ4-compression-support-to-arm64-kernel-2.patch b/target/linux/brcm2708/patches-4.14/950-0305-config-Add-LZ4-compression-support-to-arm64-kernel-2.patch
deleted file mode 100644
index 6a01a6a17..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0305-config-Add-LZ4-compression-support-to-arm64-kernel-2.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 47008c3c01cc8785371cb30afc3e1ab056195d3e Mon Sep 17 00:00:00 2001
-From: eccgecko <36884529+eccgecko@users.noreply.github.com>
-Date: Sun, 20 May 2018 17:00:39 +0200
-Subject: [PATCH 305/454] config: Add LZ4 compression support to arm64 kernel
- (#2559)
-
----
- arch/arm64/configs/bcmrpi3_defconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -1270,6 +1270,7 @@ CONFIG_CRYPTO_TGR192=m
- CONFIG_CRYPTO_WP512=m
- CONFIG_CRYPTO_CAST5=m
- CONFIG_CRYPTO_DES=y
-+CONFIG_CRYPTO_LZ4=m
- CONFIG_CRYPTO_USER_API_SKCIPHER=m
- CONFIG_ARM64_CRYPTO=y
- CONFIG_CRC_ITU_T=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0306-config-Add-KEYBOARD_MATRIX-m.patch b/target/linux/brcm2708/patches-4.14/950-0306-config-Add-KEYBOARD_MATRIX-m.patch
deleted file mode 100644
index 2c12e631b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0306-config-Add-KEYBOARD_MATRIX-m.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From e3f58b66a589ceabe9d0551e003f355e54442229 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Sun, 20 May 2018 19:31:11 +0100
-Subject: [PATCH 306/454] config: Add KEYBOARD_MATRIX=m
-
-See: https://github.com/raspberrypi/linux/pull/2150
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig   | 1 +
- arch/arm/configs/bcmrpi_defconfig    | 1 +
- arch/arm64/configs/bcmrpi3_defconfig | 1 +
- 3 files changed, 3 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -547,6 +547,7 @@ CONFIG_INPUT_JOYDEV=m
- CONFIG_INPUT_EVDEV=m
- # CONFIG_KEYBOARD_ATKBD is not set
- CONFIG_KEYBOARD_GPIO=m
-+CONFIG_KEYBOARD_MATRIX=m
- # CONFIG_INPUT_MOUSE is not set
- CONFIG_INPUT_JOYSTICK=y
- CONFIG_JOYSTICK_IFORCE=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -542,6 +542,7 @@ CONFIG_INPUT_JOYDEV=m
- CONFIG_INPUT_EVDEV=m
- # CONFIG_KEYBOARD_ATKBD is not set
- CONFIG_KEYBOARD_GPIO=m
-+CONFIG_KEYBOARD_MATRIX=m
- # CONFIG_INPUT_MOUSE is not set
- CONFIG_INPUT_JOYSTICK=y
- CONFIG_JOYSTICK_IFORCE=m
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -528,6 +528,7 @@ CONFIG_INPUT_JOYDEV=m
- CONFIG_INPUT_EVDEV=m
- # CONFIG_KEYBOARD_ATKBD is not set
- CONFIG_KEYBOARD_GPIO=m
-+CONFIG_KEYBOARD_MATRIX=m
- # CONFIG_INPUT_MOUSE is not set
- CONFIG_INPUT_JOYSTICK=y
- CONFIG_JOYSTICK_IFORCE=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0307-Enable-AES-AES-bit-slice-and-AES-NEON-engines-on-arm.patch b/target/linux/brcm2708/patches-4.14/950-0307-Enable-AES-AES-bit-slice-and-AES-NEON-engines-on-arm.patch
deleted file mode 100644
index 03ba477b7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0307-Enable-AES-AES-bit-slice-and-AES-NEON-engines-on-arm.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From d6e7ba1d656451d196d3175780e819abad063edf Mon Sep 17 00:00:00 2001
-From: eccgecko <36884529+eccgecko@users.noreply.github.com>
-Date: Wed, 23 May 2018 19:22:33 +0200
-Subject: [PATCH 307/454] Enable AES, AES bit slice, and AES NEON engines on
- arm64
-
----
- arch/arm64/configs/bcmrpi3_defconfig | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -1274,5 +1274,8 @@ CONFIG_CRYPTO_DES=y
- CONFIG_CRYPTO_LZ4=m
- CONFIG_CRYPTO_USER_API_SKCIPHER=m
- CONFIG_ARM64_CRYPTO=y
-+CONFIG_CRYPTO_AES_ARM64=m
-+CONFIG_CRYPTO_AES_ARM64_BS=m
-+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m
- CONFIG_CRC_ITU_T=y
- CONFIG_LIBCRC32C=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0308-overlays-Add-sdtweak-features-for-network-booting.patch b/target/linux/brcm2708/patches-4.14/950-0308-overlays-Add-sdtweak-features-for-network-booting.patch
deleted file mode 100644
index 8ed0f0aa4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0308-overlays-Add-sdtweak-features-for-network-booting.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From eadd32681787b1828ff92ef5046db6568d52ad55 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 29 May 2018 10:52:11 +0100
-Subject: [PATCH 308/454] overlays: Add sdtweak features for network booting
-
-It has been observed that a Pi with no SD card will poll the interface
-continuously, using up to 10% CPU. Add some new parameters to the
-sdtweak overlay to control this behaviour:
-
-poll_once   Only look for a card once, at boot time. If none is found
-            then the interface is effectively disabled.
-
-enable      Set to "off" or "no" to completely disable the interface.
-
-See: https://github.com/raspberrypi/linux/issues/2567
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README              | 10 ++++++++++
- arch/arm/boot/dts/overlays/sdtweak-overlay.dts |  2 ++
- 2 files changed, 12 insertions(+)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1618,6 +1618,16 @@ Params: overclock_50            Clock (i
- 
-         debug                   Enable debug output (default off)
- 
-+        poll_once               Looks for a card once after booting. Useful
-+                                for network booting scenarios to avoid the
-+                                overhead of continuous polling. N.B. Using
-+                                this option restricts the system to using a
-+                                single card per boot (or none at all).
-+                                (default off)
-+
-+        enable                  Set to off to completely disable the interface
-+                                (default on)
-+
- 
- Name:   smi
- Info:   Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25!
---- a/arch/arm/boot/dts/overlays/sdtweak-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/sdtweak-overlay.dts
-@@ -19,5 +19,7 @@
- 		force_pio        = <&frag0>,"brcm,force-pio?";
- 		pio_limit        = <&frag0>,"brcm,pio-limit:0";
- 		debug            = <&frag0>,"brcm,debug?";
-+		enable           = <&frag0>,"status";
-+		poll_once        = <&frag0>,"non-removable?";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0309-Enable-bbr-module-for-arm64.patch b/target/linux/brcm2708/patches-4.14/950-0309-Enable-bbr-module-for-arm64.patch
deleted file mode 100644
index 15d425e86..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0309-Enable-bbr-module-for-arm64.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 82aed6698be8777c6bbd7d87ad2971c6c6146caa Mon Sep 17 00:00:00 2001
-From: xunzhaocnm <39618369+xunzhaocnm@users.noreply.github.com>
-Date: Thu, 31 May 2018 16:25:09 +0800
-Subject: [PATCH 309/454] Enable bbr module for arm64
-
----
- arch/arm64/configs/bcmrpi3_defconfig | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -308,6 +308,9 @@ CONFIG_NET_SCH_CODEL=m
- CONFIG_NET_SCH_FQ_CODEL=m
- CONFIG_NET_SCH_INGRESS=m
- CONFIG_NET_SCH_PLUG=m
-+CONFIG_NET_SCH_FQ=m
-+CONFIG_TCP_CONG_ADVANCED=y
-+CONFIG_TCP_CONG_BBR=m
- CONFIG_NET_CLS_BASIC=m
- CONFIG_NET_CLS_TCINDEX=m
- CONFIG_NET_CLS_ROUTE4=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0310-Added-mute-stream-func.patch b/target/linux/brcm2708/patches-4.14/950-0310-Added-mute-stream-func.patch
deleted file mode 100644
index b43dd7a5f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0310-Added-mute-stream-func.patch
+++ /dev/null
@@ -1,164 +0,0 @@
-From f0bf1ca3f2e7fc889d0d01c292df4faa25af6d86 Mon Sep 17 00:00:00 2001
-From: Jaikumar <jaikumar@cem-solutions.net>
-Date: Thu, 7 Jun 2018 21:22:45 +0530
-Subject: [PATCH 310/454] Added mute stream func
-
-Signed-off-by: Jaikumar <jaikumar@cem-solutions.net>
----
- sound/soc/bcm/allo-katana-codec.c | 64 ++++++++++++++++++++++---------
- 1 file changed, 46 insertions(+), 18 deletions(-)
-
---- a/sound/soc/bcm/allo-katana-codec.c
-+++ b/sound/soc/bcm/allo-katana-codec.c
-@@ -31,21 +31,23 @@
- 
- #define KATANA_CODEC_CHIP_ID		0x30
- #define KATANA_CODEC_VIRT_BASE		0x100
--#define KATANA_CODEC_PAGE			0
-+#define KATANA_CODEC_PAGE		0
- 
- #define KATANA_CODEC_CHIP_ID_REG	(KATANA_CODEC_VIRT_BASE + 0)
--#define KATANA_CODEC_RESET			(KATANA_CODEC_VIRT_BASE + 1)
-+#define KATANA_CODEC_RESET		(KATANA_CODEC_VIRT_BASE + 1)
- #define KATANA_CODEC_VOLUME_1		(KATANA_CODEC_VIRT_BASE + 2)
- #define KATANA_CODEC_VOLUME_2		(KATANA_CODEC_VIRT_BASE + 3)
--#define KATANA_CODEC_MUTE			(KATANA_CODEC_VIRT_BASE + 4)
-+#define KATANA_CODEC_MUTE		(KATANA_CODEC_VIRT_BASE + 4)
- #define KATANA_CODEC_DSP_PROGRAM	(KATANA_CODEC_VIRT_BASE + 5)
- #define KATANA_CODEC_DEEMPHASIS		(KATANA_CODEC_VIRT_BASE + 6)
--#define KATANA_CODEC_DOP			(KATANA_CODEC_VIRT_BASE + 7)
--#define KATANA_CODEC_FORMAT			(KATANA_CODEC_VIRT_BASE + 8)
-+#define KATANA_CODEC_DOP		(KATANA_CODEC_VIRT_BASE + 7)
-+#define KATANA_CODEC_FORMAT		(KATANA_CODEC_VIRT_BASE + 8)
- #define KATANA_CODEC_COMMAND		(KATANA_CODEC_VIRT_BASE + 9)
--#define KATANA_CODEC_MAX_REGISTER	(KATANA_CODEC_VIRT_BASE + 9)
-+#define KATANA_CODEC_MUTE_STREAM	(KATANA_CODEC_VIRT_BASE + 10)
- 
--#define KATANA_CODEC_FMT			0xff
-+#define KATANA_CODEC_MAX_REGISTER	(KATANA_CODEC_VIRT_BASE + 10)
-+
-+#define KATANA_CODEC_FMT		0xff
- #define KATANA_CODEC_CHAN_MONO		0x00
- #define KATANA_CODEC_CHAN_STEREO	0x80
- #define KATANA_CODEC_ALEN_16		0x10
-@@ -76,7 +78,7 @@ static const struct reg_default katana_c
- 	{ KATANA_CODEC_MUTE,		0x00 },
- 	{ KATANA_CODEC_DSP_PROGRAM,	0x04 },
- 	{ KATANA_CODEC_DEEMPHASIS,	0x00 },
--	{ KATANA_CODEC_DOP,			0x01 },
-+	{ KATANA_CODEC_DOP,		0x01 },
- 	{ KATANA_CODEC_FORMAT,		0xb4 },
- };
- 
-@@ -135,7 +137,8 @@ static const struct snd_kcontrol_new kat
- 	SOC_SINGLE("DoP Playback Switch", KATANA_CODEC_DOP, 0, 1, 1)
- };
- 
--static bool katana_codec_readable_register(struct device *dev, unsigned int reg)
-+static bool katana_codec_readable_register(struct device *dev,
-+				unsigned int reg)
- {
- 	switch (reg) {
- 	case KATANA_CODEC_CHIP_ID_REG:
-@@ -150,13 +153,15 @@ static int katana_codec_hw_params(struct
- 			     struct snd_soc_dai *dai)
- {
- 	struct snd_soc_codec *codec = dai->codec;
--	struct katana_codec_priv *katana_codec = snd_soc_codec_get_drvdata(codec);
-+	struct katana_codec_priv *katana_codec =
-+				snd_soc_codec_get_drvdata(codec);
- 	int fmt = 0;
- 	int ret;
- 
--	dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
-+	dev_dbg(codec->dev, "hw_params %u Hz, %u channels %u bits\n",
- 			params_rate(params),
--			params_channels(params));
-+			params_channels(params),
-+			params_width(params));
- 
- 	switch (katana_codec->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
- 	case SND_SOC_DAIFMT_CBM_CFM: // master
-@@ -212,13 +217,17 @@ static int katana_codec_hw_params(struct
- 			return -EINVAL;
- 		}
- 
--		ret = regmap_write(katana_codec->regmap, KATANA_CODEC_FORMAT, fmt);
-+		ret = regmap_write(katana_codec->regmap, KATANA_CODEC_FORMAT,
-+					fmt);
- 		if (ret != 0) {
- 			dev_err(codec->dev, "Failed to set format: %d\n", ret);
- 			return ret;
- 		}
- 		break;
- 
-+	case SND_SOC_DAIFMT_CBS_CFS:
-+		break;
-+
- 	default:
- 		return -EINVAL;
- 	}
-@@ -229,14 +238,33 @@ static int katana_codec_hw_params(struct
- static int katana_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
- {
- 	struct snd_soc_codec *codec = dai->codec;
--	struct katana_codec_priv *katana_codec = snd_soc_codec_get_drvdata(codec);
-+	struct katana_codec_priv *katana_codec =
-+				snd_soc_codec_get_drvdata(codec);
- 
- 	katana_codec->fmt = fmt;
- 
- 	return 0;
- }
- 
-+int katana_codec_dai_mute_stream(struct snd_soc_dai *dai, int mute,
-+						int stream)
-+{
-+	struct snd_soc_codec *codec = dai->codec;
-+	struct katana_codec_priv *katana_codec =
-+				snd_soc_codec_get_drvdata(codec);
-+	int ret = 0;
-+
-+	ret = regmap_write(katana_codec->regmap, KATANA_CODEC_MUTE_STREAM,
-+				mute);
-+	if (ret != 0) {
-+		dev_err(codec->dev, "Failed to set mute: %d\n", ret);
-+		return ret;
-+	}
-+	return ret;
-+}
-+
- static const struct snd_soc_dai_ops katana_codec_dai_ops = {
-+	.mute_stream = katana_codec_dai_mute_stream,
- 	.hw_params = katana_codec_hw_params,
- 	.set_fmt = katana_codec_set_fmt,
- };
-@@ -260,7 +288,7 @@ static struct snd_soc_codec_driver katan
- 	.idle_bias_off = false,
- 
- 	.component_driver = {
--		.controls		= katana_codec_controls,
-+		.controls	= katana_codec_controls,
- 		.num_controls	= ARRAY_SIZE(katana_codec_controls),
- 	},
- };
-@@ -302,7 +330,7 @@ static int allo_katana_codec_probe(struc
- 		return PTR_ERR(regmap);
- 
- 	katana_codec = devm_kzalloc(dev, sizeof(struct katana_codec_priv),
--								GFP_KERNEL);
-+					GFP_KERNEL);
- 	if (!katana_codec)
- 		return -ENOMEM;
- 
-@@ -350,8 +378,8 @@ static struct i2c_driver allo_katana_cod
- 	.remove		= allo_katana_codec_remove,
- 	.id_table	= allo_katana_codec_id,
- 	.driver		= {
--		.name	= "allo-katana-codec",
--		.of_match_table = allo_katana_codec_of_match,
-+	.name		= "allo-katana-codec",
-+	.of_match_table = allo_katana_codec_of_match,
- 	},
- };
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0311-sc16is7xx-Fix-for-Unexpected-interrupt-8.patch b/target/linux/brcm2708/patches-4.14/950-0311-sc16is7xx-Fix-for-Unexpected-interrupt-8.patch
deleted file mode 100644
index b01e523a1..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0311-sc16is7xx-Fix-for-Unexpected-interrupt-8.patch
+++ /dev/null
@@ -1,110 +0,0 @@
-From d4601b298709e44a998df772ac1c85707603fde4 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 18 May 2018 10:26:59 +0100
-Subject: [PATCH 311/454] sc16is7xx: Fix for "Unexpected interrupt: 8"
-
-The SC16IS752 has an Enhanced Feature Register which is aliased at the
-same address as the Interrupt Identification Register; accessing it
-requires that a magic value is written to the Line Configuration
-Register. If an interrupt is raised while the EFR is mapped in then
-the ISR won't be able to access the IIR, leading to the "Unexpected
-interrupt" error messages.
-
-Avoid the problem by claiming a mutex around accesses to the EFR
-register, also claiming the mutex in the interrupt handler work
-item (this is equivalent to disabling interrupts to interlock against
-a non-threaded interrupt handler).
-
-See: https://github.com/raspberrypi/linux/issues/2529
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/tty/serial/sc16is7xx.c | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/drivers/tty/serial/sc16is7xx.c
-+++ b/drivers/tty/serial/sc16is7xx.c
-@@ -333,6 +333,7 @@ struct sc16is7xx_port {
- 	struct kthread_worker		kworker;
- 	struct task_struct		*kworker_task;
- 	struct kthread_work		irq_work;
-+	struct mutex			efr_lock;
- 	struct sc16is7xx_one		p[0];
- };
- 
-@@ -504,6 +505,21 @@ static int sc16is7xx_set_baud(struct uar
- 		div /= 4;
- 	}
- 
-+	/* In an amazing feat of design, the Enhanced Features Register shares
-+	 * the address of the Interrupt Identification Register, and is
-+	 * switched in by writing a magic value (0xbf) to the Line Control
-+	 * Register. Any interrupt firing during this time will see the EFR
-+	 * where it expects the IIR to be, leading to "Unexpected interrupt"
-+	 * messages.
-+	 *
-+	 * Prevent this possibility by claiming a mutex while accessing the
-+	 * EFR, and claiming the same mutex from within the interrupt handler.
-+	 * This is similar to disabling the interrupt, but that doesn't work
-+	 * because the bulk of the interrupt processing is run as a workqueue
-+	 * job in thread context.
-+	 */
-+	mutex_lock(&s->efr_lock);
-+
- 	lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
- 
- 	/* Open the LCR divisors for configuration */
-@@ -519,6 +535,8 @@ static int sc16is7xx_set_baud(struct uar
- 	/* Put LCR back to the normal mode */
- 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
- 
-+	mutex_unlock(&s->efr_lock);
-+
- 	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
- 			      SC16IS7XX_MCR_CLKSEL_BIT,
- 			      prescaler);
-@@ -701,6 +719,8 @@ static void sc16is7xx_ist(struct kthread
- {
- 	struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
- 
-+	mutex_lock(&s->efr_lock);
-+
- 	while (1) {
- 		bool keep_polling = false;
- 		int i;
-@@ -710,6 +730,8 @@ static void sc16is7xx_ist(struct kthread
- 		if (!keep_polling)
- 			break;
- 	}
-+
-+	mutex_unlock(&s->efr_lock);
- }
- 
- static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
-@@ -904,6 +926,9 @@ static void sc16is7xx_set_termios(struct
- 	if (!(termios->c_cflag & CREAD))
- 		port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
- 
-+	/* As above, claim the mutex while accessing the EFR. */
-+	mutex_lock(&s->efr_lock);
-+
- 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
- 			     SC16IS7XX_LCR_CONF_MODE_B);
- 
-@@ -925,6 +950,8 @@ static void sc16is7xx_set_termios(struct
- 	/* Update LCR register */
- 	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
- 
-+	mutex_unlock(&s->efr_lock);
-+
- 	/* Get baud rate generator configuration */
- 	baud = uart_get_baud_rate(port, termios, old,
- 				  port->uartclk / 16 / 4 / 0xffff,
-@@ -1187,6 +1214,7 @@ static int sc16is7xx_probe(struct device
- 	s->regmap = regmap;
- 	s->devtype = devtype;
- 	dev_set_drvdata(dev, s);
-+	mutex_init(&s->efr_lock);
- 
- 	kthread_init_worker(&s->kworker);
- 	kthread_init_work(&s->irq_work, sc16is7xx_ist);
diff --git a/target/linux/brcm2708/patches-4.14/950-0312-config-Add-CONFIG_SPI_GPIO.patch b/target/linux/brcm2708/patches-4.14/950-0312-config-Add-CONFIG_SPI_GPIO.patch
deleted file mode 100644
index f8bd1460e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0312-config-Add-CONFIG_SPI_GPIO.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 84a10b20192ae300833b1f630f078ed8825bbfa9 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 12 Jun 2018 10:16:07 +0100
-Subject: [PATCH 312/454] config: Add CONFIG_SPI_GPIO
-
-See: https://github.com/raspberrypi/linux/pull/2318
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -618,6 +618,7 @@ CONFIG_I2C_TINY_USB=m
- CONFIG_SPI=y
- CONFIG_SPI_BCM2835=m
- CONFIG_SPI_BCM2835AUX=m
-+CONFIG_SPI_GPIO=m
- CONFIG_SPI_SPIDEV=m
- CONFIG_SPI_SLAVE=y
- CONFIG_PPS=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -613,6 +613,7 @@ CONFIG_I2C_TINY_USB=m
- CONFIG_SPI=y
- CONFIG_SPI_BCM2835=m
- CONFIG_SPI_BCM2835AUX=m
-+CONFIG_SPI_GPIO=m
- CONFIG_SPI_SPIDEV=m
- CONFIG_SPI_SLAVE=y
- CONFIG_PPS=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0313-config-Add-CONFIG_NET_IPVTI-m.patch b/target/linux/brcm2708/patches-4.14/950-0313-config-Add-CONFIG_NET_IPVTI-m.patch
deleted file mode 100644
index 27c0af233..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0313-config-Add-CONFIG_NET_IPVTI-m.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 4495c3e6e8236adf216b4674c32eaa8a0bed2dd5 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 12 Jun 2018 10:54:51 +0100
-Subject: [PATCH 313/454] config: Add CONFIG_NET_IPVTI=m
-
-See: https://github.com/raspberrypi/linux/issues/2581
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -91,6 +91,7 @@ CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
- CONFIG_IP_PIMSM_V1=y
- CONFIG_IP_PIMSM_V2=y
- CONFIG_SYN_COOKIES=y
-+CONFIG_NET_IPVTI=m
- CONFIG_INET_AH=m
- CONFIG_INET_ESP=m
- CONFIG_INET_IPCOMP=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -86,6 +86,7 @@ CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
- CONFIG_IP_PIMSM_V1=y
- CONFIG_IP_PIMSM_V2=y
- CONFIG_SYN_COOKIES=y
-+CONFIG_NET_IPVTI=m
- CONFIG_INET_AH=m
- CONFIG_INET_ESP=m
- CONFIG_INET_IPCOMP=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0314-net-lan78xx-Disable-TCP-Segmentation-Offload-TSO.patch b/target/linux/brcm2708/patches-4.14/950-0314-net-lan78xx-Disable-TCP-Segmentation-Offload-TSO.patch
deleted file mode 100644
index 11b1b22ab..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0314-net-lan78xx-Disable-TCP-Segmentation-Offload-TSO.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From b1311b8bcd1c096c40dca757ba09d88320188e01 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 13 Jun 2018 15:21:10 +0100
-Subject: [PATCH 314/454] net: lan78xx: Disable TCP Segmentation Offload (TSO)
-
-TSO seems to be having issues when packets are dropped and the
-remote end uses Selective Acknowledge (SACK) to denote that
-data is missing. The missing data is never resent, so the
-connection eventually stalls.
-
-There is a module parameter of enable_tso added to allow
-further debugging without forcing a rebuild of the kernel.
-
-https://github.com/raspberrypi/linux/issues/2449
-https://github.com/raspberrypi/linux/issues/2482
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 19 +++++++++++++++++--
- 1 file changed, 17 insertions(+), 2 deletions(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -415,6 +415,15 @@ static int msg_level = -1;
- module_param(msg_level, int, 0);
- MODULE_PARM_DESC(msg_level, "Override default message level");
- 
-+/* TSO seems to be having some issue with Selective Acknowledge (SACK) that
-+ * results in lost data never being retransmitted.
-+ * Disable it by default now, but adds a module parameter to enable it for
-+ * debug purposes (the full cause is not currently understood).
-+ */
-+static bool enable_tso;
-+module_param(enable_tso, bool, 0644);
-+MODULE_PARM_DESC(enable_tso, "Enables TCP segmentation offload");
-+
- static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)
- {
- 	u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
-@@ -2891,8 +2900,14 @@ static int lan78xx_bind(struct lan78xx_n
- 	if (DEFAULT_RX_CSUM_ENABLE)
- 		dev->net->features |= NETIF_F_RXCSUM;
- 
--	if (DEFAULT_TSO_CSUM_ENABLE)
--		dev->net->features |= NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_SG;
-+	if (DEFAULT_TSO_CSUM_ENABLE) {
-+		dev->net->features |= NETIF_F_SG;
-+		/* Use module parameter to control TCP segmentation offload as
-+		 * it appears to cause issues.
-+		 */
-+		if (enable_tso)
-+			dev->net->features |= NETIF_F_TSO | NETIF_F_TSO6;
-+	}
- 
- 	if (DEFAULT_VLAN_RX_OFFLOAD)
- 		dev->net->features |= NETIF_F_HW_VLAN_CTAG_RX;
diff --git a/target/linux/brcm2708/patches-4.14/950-0315-usb-gadget-ethernet-Re-enable-Jumbo-frames.patch b/target/linux/brcm2708/patches-4.14/950-0315-usb-gadget-ethernet-Re-enable-Jumbo-frames.patch
deleted file mode 100644
index 6442338a6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0315-usb-gadget-ethernet-Re-enable-Jumbo-frames.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 1810e953fd59ebb674c292a13eff8d56c88e1c7e Mon Sep 17 00:00:00 2001
-From: John Greb <h3x4m3r0n@gmail.com>
-Date: Sun, 6 May 2018 20:01:57 +0000
-Subject: [PATCH 315/454] usb: gadget ethernet: Re-enable Jumbo frames.
-
-Commit <eea52743eb5654ec6f52b0e8b4aefec952543697> upstream
-
-Fixes: <b3e3893e1253> ("net: use core MTU range checking")
-which patched only one of two functions used to setup the
-USB Gadget Ethernet driver, causing a serious performance
-regression in the ability to increase mtu size above 1500.
-
-Signed-off-by: John Greb <h3x4m3r0n@gmail.com>
-Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
----
- drivers/usb/gadget/function/u_ether.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/usb/gadget/function/u_ether.c
-+++ b/drivers/usb/gadget/function/u_ether.c
-@@ -848,6 +848,10 @@ struct net_device *gether_setup_name_def
- 	net->ethtool_ops = &ops;
- 	SET_NETDEV_DEVTYPE(net, &gadget_type);
- 
-+	/* MTU range: 14 - 15412 */
-+	net->min_mtu = ETH_HLEN;
-+	net->max_mtu = GETHER_MAX_ETH_FRAME_LEN;
-+
- 	return net;
- }
- EXPORT_SYMBOL_GPL(gether_setup_name_default);
diff --git a/target/linux/brcm2708/patches-4.14/950-0316-overlays-Add-gpio-no-irq-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0316-overlays-Add-gpio-no-irq-overlay.patch
deleted file mode 100644
index ba0e4094d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0316-overlays-Add-gpio-no-irq-overlay.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 174a2e7f83a033252da488edd3072f446f82325d Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 19 Jun 2018 15:04:45 +0100
-Subject: [PATCH 316/454] overlays: Add gpio-no-irq overlay
-
-An overlay to disable all GPIO interrupts.
-
-See: https://github.com/raspberrypi/linux/issues/2550
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile                |  1 +
- arch/arm/boot/dts/overlays/README                  |  7 +++++++
- arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts | 14 ++++++++++++++
- 3 files changed, 22 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -35,6 +35,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	gpio-ir.dtbo \
- 	gpio-ir-tx.dtbo \
- 	gpio-key.dtbo \
-+	gpio-no-irq.dtbo \
- 	gpio-poweroff.dtbo \
- 	gpio-shutdown.dtbo \
- 	hifiberry-amp.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -583,6 +583,13 @@ Params: gpio                    GPIO pin
-         keycode                 Set the key code for the button
- 
- 
-+Name:   gpio-no-irq
-+Info:   Use this overlay to disable all GPIO interrupts, which can be useful
-+        for user-space GPIO edge detection systems.
-+Load:   dtoverlay=gpio-no-irq
-+Params: <None>
-+
-+
- Name:   gpio-poweroff
- Info:   Drives a GPIO high or low on poweroff (including halt). Enabling this
-         overlay will prevent the ability to boot by driving GPIO3 low.
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts
-@@ -0,0 +1,14 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835";
-+
-+	fragment@0 {
-+		// Configure the gpio pin controller
-+		target = <&gpio>;
-+		__overlay__ {
-+			    interrupts;
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0317-ifb-fix-packets-checksum.patch b/target/linux/brcm2708/patches-4.14/950-0317-ifb-fix-packets-checksum.patch
deleted file mode 100644
index 43203bc41..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0317-ifb-fix-packets-checksum.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 258289e9f25dae86004eea357177ac9c372addc7 Mon Sep 17 00:00:00 2001
-From: Jon Maxwell <jmaxwell37@gmail.com>
-Date: Fri, 25 May 2018 07:38:29 +1000
-Subject: [PATCH 317/454] ifb: fix packets checksum
-
-commit b1d2e4e03f92734ff524f96c4b2287133de7a4a3 upstream.
-
-Fixup the checksum for CHECKSUM_COMPLETE when pulling skbs on RX path.
-Otherwise we get splats when tc mirred is used to redirect packets to ifb.
-
-Before fix:
-
-nic: hw csum failure
-
-Signed-off-by: Jon Maxwell <jmaxwell37@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/ifb.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/ifb.c
-+++ b/drivers/net/ifb.c
-@@ -102,7 +102,7 @@ static void ifb_ri_tasklet(unsigned long
- 		if (!skb->tc_from_ingress) {
- 			dev_queue_xmit(skb);
- 		} else {
--			skb_pull(skb, skb->mac_len);
-+			skb_pull_rcsum(skb, skb->mac_len);
- 			netif_receive_skb(skb);
- 		}
- 	}
diff --git a/target/linux/brcm2708/patches-4.14/950-0318-netfilter-ip6t_MASQUERADE-add-dependency-on-conntrac.patch b/target/linux/brcm2708/patches-4.14/950-0318-netfilter-ip6t_MASQUERADE-add-dependency-on-conntrac.patch
deleted file mode 100644
index c3c9d5bc4..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0318-netfilter-ip6t_MASQUERADE-add-dependency-on-conntrac.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From af4dba1b5d3cbd0bc724fca24d3d01d2878406df Mon Sep 17 00:00:00 2001
-From: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>
-Date: Mon, 11 Dec 2017 18:19:33 +0300
-Subject: [PATCH 318/454] netfilter: ip6t_MASQUERADE: add dependency on
- conntrack module
-
-commit 23715275e4fb6f64358a499d20928a9e93819f2f upstream.
-
-After commit 4d3a57f23dec ("netfilter: conntrack: do not enable connection
-tracking unless needed") conntrack is disabled by default unless some
-module explicitly declares dependency in particular network namespace.
-
-Fixes: a357b3f80bc8 ("netfilter: nat: add dependencies on conntrack module")
-Signed-off-by: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>
-Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
----
- net/ipv6/netfilter/ip6t_MASQUERADE.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
---- a/net/ipv6/netfilter/ip6t_MASQUERADE.c
-+++ b/net/ipv6/netfilter/ip6t_MASQUERADE.c
-@@ -33,13 +33,19 @@ static int masquerade_tg6_checkentry(con
- 
- 	if (range->flags & NF_NAT_RANGE_MAP_IPS)
- 		return -EINVAL;
--	return 0;
-+	return nf_ct_netns_get(par->net, par->family);
-+}
-+
-+static void masquerade_tg6_destroy(const struct xt_tgdtor_param *par)
-+{
-+	nf_ct_netns_put(par->net, par->family);
- }
- 
- static struct xt_target masquerade_tg6_reg __read_mostly = {
- 	.name		= "MASQUERADE",
- 	.family		= NFPROTO_IPV6,
- 	.checkentry	= masquerade_tg6_checkentry,
-+	.destroy	= masquerade_tg6_destroy,
- 	.target		= masquerade_tg6,
- 	.targetsize	= sizeof(struct nf_nat_range),
- 	.table		= "nat",
diff --git a/target/linux/brcm2708/patches-4.14/950-0319-Allo-Katana-DAC-Updated-default-values.patch b/target/linux/brcm2708/patches-4.14/950-0319-Allo-Katana-DAC-Updated-default-values.patch
deleted file mode 100644
index 7d13d0f69..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0319-Allo-Katana-DAC-Updated-default-values.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From b8f1afeaa6a2a72985aa9de3642bd754fdf82dba Mon Sep 17 00:00:00 2001
-From: Jaikumar <jaikumar@cem-solutions.com>
-Date: Tue, 26 Jun 2018 19:21:00 +0530
-Subject: [PATCH 319/454] Allo Katana DAC: Updated default values
-
-Signed-off-by: Jaikumar <jaikumar@cem-solutions.com>
----
- sound/soc/bcm/allo-katana-codec.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/sound/soc/bcm/allo-katana-codec.c
-+++ b/sound/soc/bcm/allo-katana-codec.c
-@@ -78,7 +78,7 @@ static const struct reg_default katana_c
- 	{ KATANA_CODEC_MUTE,		0x00 },
- 	{ KATANA_CODEC_DSP_PROGRAM,	0x04 },
- 	{ KATANA_CODEC_DEEMPHASIS,	0x00 },
--	{ KATANA_CODEC_DOP,		0x01 },
-+	{ KATANA_CODEC_DOP,		0x00 },
- 	{ KATANA_CODEC_FORMAT,		0xb4 },
- };
- 
-@@ -388,4 +388,3 @@ module_i2c_driver(allo_katana_codec_driv
- MODULE_DESCRIPTION("ASoC Allo Katana Codec Driver");
- MODULE_AUTHOR("Jaikumar <jaikumar@cem-solutions.net>");
- MODULE_LICENSE("GPL v2");
--
diff --git a/target/linux/brcm2708/patches-4.14/950-0320-ARM-bcm283x-Add-missing-interrupt-for-RNG-block.patch b/target/linux/brcm2708/patches-4.14/950-0320-ARM-bcm283x-Add-missing-interrupt-for-RNG-block.patch
deleted file mode 100644
index 0b15b5b8e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0320-ARM-bcm283x-Add-missing-interrupt-for-RNG-block.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From c5d48820a524644594ce8c2e2bf98bedd073b416 Mon Sep 17 00:00:00 2001
-From: Stefan Wahren <stefan.wahren@i2se.com>
-Date: Sat, 18 Nov 2017 14:04:13 +0100
-Subject: [PATCH 320/454] ARM: bcm283x: Add missing interrupt for RNG block
-
-commit 4034600e6f72f7e0a7d8112db3de61469e47fc36 upstream.
-
-This patch adds the missing interrupt property to the RNG block
-of BCM283x.
-
-Link: https://github.com/raspberrypi/linux/issues/2195
-CC: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm/boot/dts/bcm283x.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/boot/dts/bcm283x.dtsi
-+++ b/arch/arm/boot/dts/bcm283x.dtsi
-@@ -135,6 +135,7 @@
- 		rng@7e104000 {
- 			compatible = "brcm,bcm2835-rng";
- 			reg = <0x7e104000 0x10>;
-+			interrupts = <2 29>;
- 		};
- 
- 		mailbox: mailbox@7e00b880 {
diff --git a/target/linux/brcm2708/patches-4.14/950-0321-ov5647-Add-set_fmt-and-get_fmt-calls.patch b/target/linux/brcm2708/patches-4.14/950-0321-ov5647-Add-set_fmt-and-get_fmt-calls.patch
deleted file mode 100644
index 4570e5da9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0321-ov5647-Add-set_fmt-and-get_fmt-calls.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 76ba71d15be13d6c48a63d53c33134dc17736d71 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 20 Mar 2017 16:33:44 +0000
-Subject: [PATCH 321/454] ov5647: Add set_fmt and get_fmt calls.
-
-There's no way to query the subdevice for the supported
-resolutions.
-Add set_fmt and get_fmt implementations.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/ov5647.c | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/drivers/media/i2c/ov5647.c
-+++ b/drivers/media/i2c/ov5647.c
-@@ -442,8 +442,30 @@ static int ov5647_enum_mbus_code(struct
- 	return 0;
- }
- 
-+static int ov5647_set_get_fmt(struct v4l2_subdev *sd,
-+			      struct v4l2_subdev_pad_config *cfg,
-+			      struct v4l2_subdev_format *format)
-+{
-+	struct v4l2_mbus_framefmt *fmt = &format->format;
-+
-+	if (format->pad != 0)
-+		return -EINVAL;
-+
-+	/* Only one format is supported, so return that */
-+	memset(fmt, 0, sizeof(*fmt));
-+	fmt->code = MEDIA_BUS_FMT_SBGGR8_1X8;
-+	fmt->colorspace = V4L2_COLORSPACE_SRGB;
-+	fmt->field = V4L2_FIELD_NONE;
-+	fmt->width = 640;
-+	fmt->height = 480;
-+
-+	return 0;
-+}
-+
- static const struct v4l2_subdev_pad_ops ov5647_subdev_pad_ops = {
- 	.enum_mbus_code = ov5647_enum_mbus_code,
-+	.set_fmt =	  ov5647_set_get_fmt,
-+	.get_fmt =	  ov5647_set_get_fmt,
- };
- 
- static const struct v4l2_subdev_ops ov5647_subdev_ops = {
diff --git a/target/linux/brcm2708/patches-4.14/950-0322-ov5647-dt-add-device-tree-for-PWDN-control.patch b/target/linux/brcm2708/patches-4.14/950-0322-ov5647-dt-add-device-tree-for-PWDN-control.patch
deleted file mode 100644
index b0152b475..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0322-ov5647-dt-add-device-tree-for-PWDN-control.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 09036bbc1f3f3c80cc9f611e4b1fc138a87b9743 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 18 May 2017 15:37:49 +0100
-Subject: [PATCH 322/454] ov5647: dt: add device tree for PWDN control
-
-Add optional GPIO pwdn to connect to the PWDN line on the sensor.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- Documentation/devicetree/bindings/media/i2c/ov5647.txt | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/Documentation/devicetree/bindings/media/i2c/ov5647.txt
-+++ b/Documentation/devicetree/bindings/media/i2c/ov5647.txt
-@@ -10,6 +10,9 @@ Required properties:
- - reg			: I2C slave address of the sensor.
- - clocks		: Reference to the xclk clock.
- 
-+Optional Properties:
-+- pwdn-gpios: reference to the GPIO connected to the pwdn pin, if any.
-+
- The common video interfaces bindings (see video-interfaces.txt) should be
- used to specify link to the image data receiver. The OV5647 device
- node should contain one 'port' child node with an 'endpoint' subnode.
-@@ -26,6 +29,7 @@ Example:
- 			compatible = "ovti,ov5647";
- 			reg = <0x36>;
- 			clocks = <&camera_clk>;
-+			pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
- 			port {
- 				camera_1: endpoint {
- 					remote-endpoint = <&csi1_ep1>;
diff --git a/target/linux/brcm2708/patches-4.14/950-0323-ov5647-Add-support-for-PWDN-GPIO.patch b/target/linux/brcm2708/patches-4.14/950-0323-ov5647-Add-support-for-PWDN-GPIO.patch
deleted file mode 100644
index 022469869..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0323-ov5647-Add-support-for-PWDN-GPIO.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From 34220db79008820c110473fe804cf02af3037889 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 18 May 2017 15:42:34 +0100
-Subject: [PATCH 323/454] ov5647: Add support for PWDN GPIO.
-
-Add support for an optional GPIO connected to PWDN on the sensor.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/ov5647.c | 28 ++++++++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/drivers/media/i2c/ov5647.c
-+++ b/drivers/media/i2c/ov5647.c
-@@ -21,6 +21,7 @@
- 
- #include <linux/clk.h>
- #include <linux/delay.h>
-+#include <linux/gpio/consumer.h>
- #include <linux/i2c.h>
- #include <linux/init.h>
- #include <linux/io.h>
-@@ -35,6 +36,13 @@
- 
- #define SENSOR_NAME "ov5647"
- 
-+/*
-+ * From the datasheet, "20ms after PWDN goes low or 20ms after RESETB goes
-+ * high if reset is inserted after PWDN goes high, host can access sensor's
-+ * SCCB to initialize sensor."
-+ */
-+#define PWDN_ACTIVE_DELAY_MS	20
-+
- #define OV5647_SW_RESET		0x0103
- #define OV5647_REG_CHIPID_H	0x300A
- #define OV5647_REG_CHIPID_L	0x300B
-@@ -77,6 +85,7 @@ struct ov5647 {
- 	unsigned int			height;
- 	int				power_count;
- 	struct clk			*xclk;
-+	struct gpio_desc		*pwdn;
- };
- 
- static inline struct ov5647 *to_state(struct v4l2_subdev *sd)
-@@ -334,6 +343,11 @@ static int ov5647_sensor_power(struct v4
- 	if (on && !ov5647->power_count)	{
- 		dev_dbg(&client->dev, "OV5647 power on\n");
- 
-+		if (ov5647->pwdn) {
-+			gpiod_set_value(ov5647->pwdn, 0);
-+			msleep(PWDN_ACTIVE_DELAY_MS);
-+		}
-+
- 		ret = clk_prepare_enable(ov5647->xclk);
- 		if (ret < 0) {
- 			dev_err(&client->dev, "clk prepare enable failed\n");
-@@ -371,6 +385,8 @@ static int ov5647_sensor_power(struct v4
- 			dev_dbg(&client->dev, "soft stby failed\n");
- 
- 		clk_disable_unprepare(ov5647->xclk);
-+
-+		gpiod_set_value(ov5647->pwdn, 1);
- 	}
- 
- 	/* Update the power count. */
-@@ -583,6 +599,10 @@ static int ov5647_probe(struct i2c_clien
- 		return -EINVAL;
- 	}
- 
-+	/* Request the power down GPIO asserted */
-+	sensor->pwdn = devm_gpiod_get_optional(&client->dev, "pwdn",
-+					       GPIOD_OUT_HIGH);
-+
- 	mutex_init(&sensor->lock);
- 
- 	sd = &sensor->sd;
-@@ -596,7 +616,15 @@ static int ov5647_probe(struct i2c_clien
- 	if (ret < 0)
- 		goto mutex_remove;
- 
-+	if (sensor->pwdn) {
-+		gpiod_set_value(sensor->pwdn, 0);
-+		msleep(PWDN_ACTIVE_DELAY_MS);
-+	}
-+
- 	ret = ov5647_detect(sd);
-+
-+	gpiod_set_value(sensor->pwdn, 1);
-+
- 	if (ret < 0)
- 		goto error;
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0324-ov5647-Add-support-for-non-continuous-clock-mode.patch b/target/linux/brcm2708/patches-4.14/950-0324-ov5647-Add-support-for-non-continuous-clock-mode.patch
deleted file mode 100644
index 62de988cb..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0324-ov5647-Add-support-for-non-continuous-clock-mode.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From f4d559078cab81209b721a83ffd87a40a6fb52c4 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Fri, 23 Jun 2017 17:58:55 +0100
-Subject: [PATCH 324/454] ov5647: Add support for non-continuous clock mode
-
-The driver was only supporting continuous clock mode
-although this was not stated anywhere.
-Non-continuous clock saves a small amount of power and
-on some SoCs is easier to interface with.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/ov5647.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
---- a/drivers/media/i2c/ov5647.c
-+++ b/drivers/media/i2c/ov5647.c
-@@ -86,6 +86,7 @@ struct ov5647 {
- 	int				power_count;
- 	struct clk			*xclk;
- 	struct gpio_desc		*pwdn;
-+	unsigned int			flags;
- };
- 
- static inline struct ov5647 *to_state(struct v4l2_subdev *sd)
-@@ -302,6 +303,7 @@ static int __sensor_init(struct v4l2_sub
- 	int ret;
- 	u8 resetval, rdval;
- 	struct i2c_client *client = v4l2_get_subdevdata(sd);
-+	struct ov5647 *ov5647 = to_state(sd);
- 
- 	ret = ov5647_read(sd, 0x0100, &rdval);
- 	if (ret < 0)
-@@ -329,7 +331,9 @@ static int __sensor_init(struct v4l2_sub
- 			return ret;
- 	}
- 
--	return ov5647_write(sd, 0x4800, 0x04);
-+	return ov5647_write(sd, 0x4800,
-+		    (ov5647->flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK) ?
-+					0x34 : 0x04);
- }
- 
- static int ov5647_sensor_power(struct v4l2_subdev *sd, int on)
-@@ -547,7 +551,7 @@ static const struct v4l2_subdev_internal
- 	.open = ov5647_open,
- };
- 
--static int ov5647_parse_dt(struct device_node *np)
-+static int ov5647_parse_dt(struct device_node *np, struct ov5647 *sensor)
- {
- 	struct v4l2_fwnode_endpoint bus_cfg;
- 	struct device_node *ep;
-@@ -560,6 +564,9 @@ static int ov5647_parse_dt(struct device
- 
- 	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &bus_cfg);
- 
-+	if (!ret)
-+		sensor->flags = bus_cfg.bus.mipi_csi2.flags;
-+
- 	of_node_put(ep);
- 	return ret;
- }
-@@ -579,7 +586,7 @@ static int ov5647_probe(struct i2c_clien
- 		return -ENOMEM;
- 
- 	if (IS_ENABLED(CONFIG_OF) && np) {
--		ret = ov5647_parse_dt(np);
-+		ret = ov5647_parse_dt(np, sensor);
- 		if (ret) {
- 			dev_err(dev, "DT parsing error: %d\n", ret);
- 			return ret;
diff --git a/target/linux/brcm2708/patches-4.14/950-0325-media-tc358743-Increase-FIFO-level-to-374.patch b/target/linux/brcm2708/patches-4.14/950-0325-media-tc358743-Increase-FIFO-level-to-374.patch
deleted file mode 100644
index 76ff62e4b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0325-media-tc358743-Increase-FIFO-level-to-374.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 3dd05bc8d1ec3c98de90e922bb6ed6a27d3a7eaf Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 7 Sep 2017 15:54:40 +0100
-Subject: [PATCH 325/454] media: tc358743: Increase FIFO level to 374.
-
-The existing fixed value of 16 worked for UYVY 720P60 over
-2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888
-1080P60 needs 6 lanes at 594MHz).
-It doesn't allow for lower resolutions to work as the FIFO
-underflows.
-
-374 is required for 1080P24-30 UYVY over 2 lanes @ 972Mbit/s, but
->374 means that the FIFO underflows on 1080P50 UYVY over 2 lanes
-@ 972Mbit/s.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/tc358743.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/media/i2c/tc358743.c
-+++ b/drivers/media/i2c/tc358743.c
-@@ -1782,7 +1782,7 @@ static int tc358743_probe_of(struct tc35
- 	state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
- 	state->pdata.enable_hdcp = false;
- 	/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
--	state->pdata.fifo_level = 16;
-+	state->pdata.fifo_level = 374;
- 	/*
- 	 * The PLL input clock is obtained by dividing refclk by pll_prd.
- 	 * It must be between 6 MHz and 40 MHz, lower frequency is better.
diff --git a/target/linux/brcm2708/patches-4.14/950-0326-tc358743-fix-connected-active-CSI-2-lane-reporting.patch b/target/linux/brcm2708/patches-4.14/950-0326-tc358743-fix-connected-active-CSI-2-lane-reporting.patch
deleted file mode 100644
index cd27a17ce..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0326-tc358743-fix-connected-active-CSI-2-lane-reporting.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From 39770203c368829b4ddb8b01a68870cc336abc41 Mon Sep 17 00:00:00 2001
-From: Philipp Zabel <p.zabel@pengutronix.de>
-Date: Thu, 21 Sep 2017 17:30:24 +0200
-Subject: [PATCH 326/454] tc358743: fix connected/active CSI-2 lane reporting
-
-g_mbus_config was supposed to indicate all supported lane numbers, not
-only the number of those currently in active use. Since the TC358743
-can dynamically reduce the number of active lanes if the required
-bandwidth allows for it, report all lane numbers up to the connected
-number of lanes as supported in pdata mode.
-In device tree mode, do not report lane count and clock mode at all, as
-the receiver driver can determine these from the device tree.
-
-To allow communicating the number of currently active lanes, add a new
-bitfield to the v4l2_mbus_config flags. This is a temporary fix, to be
-used only until a better solution is found.
-
-Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
----
- drivers/media/i2c/tc358743.c  | 30 ++++++++++++++++--------------
- include/media/v4l2-mediabus.h |  8 ++++++++
- 2 files changed, 24 insertions(+), 14 deletions(-)
-
---- a/drivers/media/i2c/tc358743.c
-+++ b/drivers/media/i2c/tc358743.c
-@@ -1458,28 +1458,29 @@ static int tc358743_g_mbus_config(struct
- 			     struct v4l2_mbus_config *cfg)
- {
- 	struct tc358743_state *state = to_state(sd);
-+	const u32 mask = V4L2_MBUS_CSI2_LANE_MASK;
-+
-+	if (state->csi_lanes_in_use > state->bus.num_data_lanes)
-+		return -EINVAL;
- 
- 	cfg->type = V4L2_MBUS_CSI2;
-+	cfg->flags = (state->csi_lanes_in_use << __ffs(mask)) & mask;
-+
-+	/* In DT mode, only report the number of active lanes */
-+	if (sd->dev->of_node)
-+		return 0;
- 
--	/* Support for non-continuous CSI-2 clock is missing in the driver */
--	cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
-+	/* Support for non-continuous CSI-2 clock is missing in pdata mode */
-+	cfg->flags |= V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
- 
--	switch (state->csi_lanes_in_use) {
--	case 1:
-+	if (state->bus.num_data_lanes > 0)
- 		cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
--		break;
--	case 2:
-+	if (state->bus.num_data_lanes > 1)
- 		cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
--		break;
--	case 3:
-+	if (state->bus.num_data_lanes > 2)
- 		cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
--		break;
--	case 4:
-+	if (state->bus.num_data_lanes > 3)
- 		cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
--		break;
--	default:
--		return -EINVAL;
--	}
- 
- 	return 0;
- }
-@@ -1885,6 +1886,7 @@ static int tc358743_probe(struct i2c_cli
- 	if (pdata) {
- 		state->pdata = *pdata;
- 		state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
-+		state->bus.num_data_lanes = 4;
- 	} else {
- 		err = tc358743_probe_of(state);
- 		if (err == -ENODEV)
---- a/include/media/v4l2-mediabus.h
-+++ b/include/media/v4l2-mediabus.h
-@@ -63,6 +63,14 @@
- 					 V4L2_MBUS_CSI2_3_LANE | V4L2_MBUS_CSI2_4_LANE)
- #define V4L2_MBUS_CSI2_CHANNELS		(V4L2_MBUS_CSI2_CHANNEL_0 | V4L2_MBUS_CSI2_CHANNEL_1 | \
- 					 V4L2_MBUS_CSI2_CHANNEL_2 | V4L2_MBUS_CSI2_CHANNEL_3)
-+/*
-+ * Number of lanes in use, 0 == use all available lanes (default)
-+ *
-+ * This is a temporary fix for devices that need to reduce the number of active
-+ * lanes for certain modes, until g_mbus_config() can be replaced with a better
-+ * solution.
-+ */
-+#define V4L2_MBUS_CSI2_LANE_MASK                (0xf << 10)
- 
- /**
-  * enum v4l2_mbus_type - media bus type
diff --git a/target/linux/brcm2708/patches-4.14/950-0327-tc358743-Add-support-for-972Mbit-s-link-freq.patch b/target/linux/brcm2708/patches-4.14/950-0327-tc358743-Add-support-for-972Mbit-s-link-freq.patch
deleted file mode 100644
index c257befd7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0327-tc358743-Add-support-for-972Mbit-s-link-freq.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 78b59478f96887aa293670f6dd494628a3714526 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Fri, 8 Sep 2017 15:11:53 +0100
-Subject: [PATCH 327/454] tc358743: Add support for 972Mbit/s link freq.
-
-Adds register setups for running the CSI lanes at 972Mbit/s,
-which allows 1080P50 UYVY down 2 lanes.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/tc358743.c | 47 +++++++++++++++++++++++++-----------
- 1 file changed, 33 insertions(+), 14 deletions(-)
-
---- a/drivers/media/i2c/tc358743.c
-+++ b/drivers/media/i2c/tc358743.c
-@@ -1803,6 +1803,7 @@ static int tc358743_probe_of(struct tc35
- 	/*
- 	 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
- 	 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
-+	 * 972 Mbps allows 1080P50 UYVY over 2-lane.
- 	 */
- 	bps_pr_lane = 2 * endpoint->link_frequencies[0];
- 	if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
-@@ -1815,23 +1816,41 @@ static int tc358743_probe_of(struct tc35
- 			       state->pdata.refclk_hz * state->pdata.pll_prd;
- 
- 	/*
--	 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
--	 * link frequency). In principle it should be possible to calculate
-+	 * FIXME: These timings are from REF_02 for 594 or 972 Mbps per lane
-+	 * (297 MHz or 486 MHz link frequency).
-+	 * In principle it should be possible to calculate
- 	 * them based on link frequency and resolution.
- 	 */
--	if (bps_pr_lane != 594000000U)
-+	switch (bps_pr_lane) {
-+	default:
- 		dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
--	state->pdata.lineinitcnt = 0xe80;
--	state->pdata.lptxtimecnt = 0x003;
--	/* tclk-preparecnt: 3, tclk-zerocnt: 20 */
--	state->pdata.tclk_headercnt = 0x1403;
--	state->pdata.tclk_trailcnt = 0x00;
--	/* ths-preparecnt: 3, ths-zerocnt: 1 */
--	state->pdata.ths_headercnt = 0x0103;
--	state->pdata.twakeup = 0x4882;
--	state->pdata.tclk_postcnt = 0x008;
--	state->pdata.ths_trailcnt = 0x2;
--	state->pdata.hstxvregcnt = 0;
-+	case 594000000U:
-+		state->pdata.lineinitcnt = 0xe80;
-+		state->pdata.lptxtimecnt = 0x003;
-+		/* tclk-preparecnt: 3, tclk-zerocnt: 20 */
-+		state->pdata.tclk_headercnt = 0x1403;
-+		state->pdata.tclk_trailcnt = 0x00;
-+		/* ths-preparecnt: 3, ths-zerocnt: 1 */
-+		state->pdata.ths_headercnt = 0x0103;
-+		state->pdata.twakeup = 0x4882;
-+		state->pdata.tclk_postcnt = 0x008;
-+		state->pdata.ths_trailcnt = 0x2;
-+		state->pdata.hstxvregcnt = 0;
-+		break;
-+	case 972000000U:
-+		state->pdata.lineinitcnt = 0x1b58;
-+		state->pdata.lptxtimecnt = 0x007;
-+		/* tclk-preparecnt: 6, tclk-zerocnt: 40 */
-+		state->pdata.tclk_headercnt = 0x2806;
-+		state->pdata.tclk_trailcnt = 0x00;
-+		/* ths-preparecnt: 6, ths-zerocnt: 8 */
-+		state->pdata.ths_headercnt = 0x0806;
-+		state->pdata.twakeup = 0x4268;
-+		state->pdata.tclk_postcnt = 0x008;
-+		state->pdata.ths_trailcnt = 0x5;
-+		state->pdata.hstxvregcnt = 0;
-+		break;
-+	}
- 
- 	state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
- 						    GPIOD_OUT_LOW);
diff --git a/target/linux/brcm2708/patches-4.14/950-0328-media-tc358743-Check-I2C-succeeded-during-probe.patch b/target/linux/brcm2708/patches-4.14/950-0328-media-tc358743-Check-I2C-succeeded-during-probe.patch
deleted file mode 100644
index 87d0966f2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0328-media-tc358743-Check-I2C-succeeded-during-probe.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From bce8f86dec02feb9865a6c72e450a1256b33ae2f Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Tue, 28 Nov 2017 10:07:29 +0000
-Subject: [PATCH 328/454] media: tc358743: Check I2C succeeded during probe.
-
-The probe for the TC358743 reads the CHIPID register from
-the device and compares it to the expected value of 0.
-If the I2C request fails then that also returns 0, so
-the driver loads thinking that the device is there.
-
-Generally I2C communications are reliable so there is
-limited need to check the return value on every transfer,
-therefore only amend the one read during probe to check
-for I2C errors.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/tc358743.c | 27 +++++++++++++++++++++++----
- 1 file changed, 23 insertions(+), 4 deletions(-)
-
---- a/drivers/media/i2c/tc358743.c
-+++ b/drivers/media/i2c/tc358743.c
-@@ -119,7 +119,7 @@ static inline struct tc358743_state *to_
- 
- /* --------------- I2C --------------- */
- 
--static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
-+static int i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
- {
- 	struct tc358743_state *state = to_state(sd);
- 	struct i2c_client *client = state->i2c_client;
-@@ -145,6 +145,7 @@ static void i2c_rd(struct v4l2_subdev *s
- 		v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
- 				__func__, reg, client->addr);
- 	}
-+	return err != ARRAY_SIZE(msgs);
- }
- 
- static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
-@@ -201,15 +202,24 @@ static void i2c_wr(struct v4l2_subdev *s
- 	}
- }
- 
--static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
-+static noinline u32 i2c_rdreg_err(struct v4l2_subdev *sd, u16 reg, u32 n,
-+				  int *err)
- {
-+	int error;
- 	__le32 val = 0;
- 
--	i2c_rd(sd, reg, (u8 __force *)&val, n);
-+	error = i2c_rd(sd, reg, (u8 __force *)&val, n);
-+	if (err)
-+		*err = error;
- 
- 	return le32_to_cpu(val);
- }
- 
-+static inline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
-+{
-+	return i2c_rdreg_err(sd, reg, n, NULL);
-+}
-+
- static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
- {
- 	__le32 raw = cpu_to_le32(val);
-@@ -238,6 +248,13 @@ static u16 i2c_rd16(struct v4l2_subdev *
- 	return i2c_rdreg(sd, reg, 2);
- }
- 
-+static int i2c_rd16_err(struct v4l2_subdev *sd, u16 reg, u16 *value)
-+{
-+	int err;
-+	*value = i2c_rdreg_err(sd, reg, 2, &err);
-+	return err;
-+}
-+
- static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
- {
- 	i2c_wrreg(sd, reg, val, 2);
-@@ -1887,6 +1904,7 @@ static int tc358743_probe(struct i2c_cli
- 	struct tc358743_state *state;
- 	struct tc358743_platform_data *pdata = client->dev.platform_data;
- 	struct v4l2_subdev *sd;
-+	u16 chipid;
- 	int err;
- 
- 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
-@@ -1919,7 +1937,8 @@ static int tc358743_probe(struct i2c_cli
- 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
- 
- 	/* i2c access */
--	if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
-+	if (i2c_rd16_err(sd, CHIPID, &chipid) ||
-+	    (chipid & MASK_CHIPID) != 0) {
- 		v4l2_info(sd, "not a TC358743 on address 0x%x\n",
- 			  client->addr << 1);
- 		return -ENODEV;
diff --git a/target/linux/brcm2708/patches-4.14/950-0329-adv7180-Default-to-the-first-valid-input.patch b/target/linux/brcm2708/patches-4.14/950-0329-adv7180-Default-to-the-first-valid-input.patch
deleted file mode 100644
index 92e81d471..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0329-adv7180-Default-to-the-first-valid-input.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 2fd686f36bfd27b00c3c58c88e3e38d3bbb1bbe9 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Tue, 12 Sep 2017 18:15:41 +0100
-Subject: [PATCH 329/454] adv7180: Default to the first valid input
-
-The hardware default is differential CVBS on AIN1 & 2, which
-isn't very useful.
-
-Select the first input that is defined as valid for the
-chip variant (typically CVBS_AIN1).
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/adv7180.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/media/i2c/adv7180.c
-+++ b/drivers/media/i2c/adv7180.c
-@@ -1220,6 +1220,7 @@ static const struct adv7180_chip_info ad
- static int init_device(struct adv7180_state *state)
- {
- 	int ret;
-+	int i;
- 
- 	mutex_lock(&state->mutex);
- 
-@@ -1266,6 +1267,18 @@ static int init_device(struct adv7180_st
- 			goto out_unlock;
- 	}
- 
-+	/* Select first valid input */
-+	for (i = 0; i < 32; i++) {
-+		if (BIT(i) & state->chip_info->valid_input_mask) {
-+			ret = state->chip_info->select_input(state, i);
-+
-+			if (ret == 0) {
-+				state->input = i;
-+				break;
-+			}
-+		}
-+	}
-+
- out_unlock:
- 	mutex_unlock(&state->mutex);
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0330-videodev2-Add-helper-defines-for-printing-FOURCCs.patch b/target/linux/brcm2708/patches-4.14/950-0330-videodev2-Add-helper-defines-for-printing-FOURCCs.patch
deleted file mode 100644
index 1bc2ede2e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0330-videodev2-Add-helper-defines-for-printing-FOURCCs.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 24f3ba4a4b4c471ce60d59b73762f37b4bfacde6 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 11 Sep 2017 15:42:07 +0100
-Subject: [PATCH 330/454] videodev2: Add helper defines for printing FOURCCs
-
-New helper defines that allow printing of a FOURCC using
-printf(V4L2_FOURCC_CONV, V4L2_FOURCC_CONV_ARGS(fourcc));
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- include/uapi/linux/videodev2.h | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/uapi/linux/videodev2.h
-+++ b/include/uapi/linux/videodev2.h
-@@ -82,6 +82,11 @@
- 	((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
- #define v4l2_fourcc_be(a, b, c, d)	(v4l2_fourcc(a, b, c, d) | (1 << 31))
- 
-+#define V4L2_FOURCC_CONV "%c%c%c%c%s"
-+#define V4L2_FOURCC_CONV_ARGS(fourcc) \
-+	(fourcc) & 0x7f, ((fourcc) >> 8) & 0x7f, ((fourcc) >> 16) & 0x7f, \
-+	((fourcc) >> 24) & 0x7f, (fourcc) & BIT(31) ? "-BE" : ""
-+
- /*
-  *	E N U M S
-  */
diff --git a/target/linux/brcm2708/patches-4.14/950-0331-dt-bindings-Document-BCM283x-CSI2-CCP2-receiver.patch b/target/linux/brcm2708/patches-4.14/950-0331-dt-bindings-Document-BCM283x-CSI2-CCP2-receiver.patch
deleted file mode 100644
index e365a81a2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0331-dt-bindings-Document-BCM283x-CSI2-CCP2-receiver.patch
+++ /dev/null
@@ -1,103 +0,0 @@
-From 844bbbb44e2307df671d5862e325432fea629b90 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 11 Sep 2017 15:42:17 +0100
-Subject: [PATCH 331/454] dt-bindings: Document BCM283x CSI2/CCP2 receiver
-
-Document the DT bindings for the CSI2/CCP2 receiver peripheral
-(known as Unicam) on BCM283x SoCs.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Acked-by: Rob Herring <robh@kernel.org>
----
- .../bindings/media/bcm2835-unicam.txt         | 85 +++++++++++++++++++
- 1 file changed, 85 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/media/bcm2835-unicam.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/media/bcm2835-unicam.txt
-@@ -0,0 +1,85 @@
-+Broadcom BCM283x Camera Interface (Unicam)
-+------------------------------------------
-+
-+The Unicam block on BCM283x SoCs is the receiver for either
-+CSI-2 or CCP2 data from image sensors or similar devices.
-+
-+The main platform using this SoC is the Raspberry Pi family of boards.
-+On the Pi the VideoCore firmware can also control this hardware block,
-+and driving it from two different processors will cause issues.
-+To avoid this, the firmware checks the device tree configuration
-+during boot. If it finds device tree nodes called csi0 or csi1 then
-+it will stop the firmware accessing the block, and it can then
-+safely be used via the device tree binding.
-+
-+Required properties:
-+===================
-+- compatible	: must be "brcm,bcm2835-unicam".
-+- reg		: physical base address and length of the register sets for the
-+		  device.
-+- interrupts	: should contain the IRQ line for this Unicam instance.
-+- clocks	: list of clock specifiers, corresponding to entries in
-+		  clock-names property.
-+- clock-names	: must contain an "lp" entry, matching entries in the
-+		  clocks property.
-+
-+Unicam supports a single port node. It should contain one 'port' child node
-+with child 'endpoint' node. Please refer to the bindings defined in
-+Documentation/devicetree/bindings/media/video-interfaces.txt.
-+
-+Within the endpoint node the "remote-endpoint" and "data-lanes" properties
-+are mandatory.
-+Data lane reordering is not supported so the data lanes must be in order,
-+starting at 1. The number of data lanes should represent the number of
-+usable lanes for the hardware block. That may be limited by either the SoC or
-+how the platform presents the interface, and the lower value must be used.
-+
-+Lane reordering is not supported on the clock lane either, so the optional
-+property "clock-lane" will implicitly be <0>.
-+Similarly lane inversion is not supported, therefore "lane-polarities" will
-+implicitly be <0 0 0 0 0>.
-+Neither of these values will be checked.
-+
-+Example:
-+	csi1: csi1@7e801000 {
-+		compatible = "brcm,bcm2835-unicam";
-+		reg = <0x7e801000 0x800>,
-+		      <0x7e802004 0x4>;
-+		interrupts = <2 7>;
-+		clocks = <&clocks BCM2835_CLOCK_CAM1>;
-+		clock-names = "lp";
-+
-+		port {
-+			csi1_ep: endpoint {
-+				remote-endpoint = <&tc358743_0>;
-+				data-lanes = <1 2>;
-+			};
-+		};
-+	};
-+
-+	i2c0: i2c@7e205000 {
-+		tc358743: csi-hdmi-bridge@0f {
-+			compatible = "toshiba,tc358743";
-+			reg = <0x0f>;
-+
-+			clocks = <&tc358743_clk>;
-+			clock-names = "refclk";
-+
-+			tc358743_clk: bridge-clk {
-+				compatible = "fixed-clock";
-+				#clock-cells = <0>;
-+				clock-frequency = <27000000>;
-+			};
-+
-+			port {
-+				tc358743_0: endpoint {
-+					remote-endpoint = <&csi1_ep>;
-+					clock-lanes = <0>;
-+					data-lanes = <1 2>;
-+					clock-noncontinuous;
-+					link-frequencies =
-+						/bits/ 64 <297000000>;
-+				};
-+			};
-+		};
-+	};
diff --git a/target/linux/brcm2708/patches-4.14/950-0332-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-interface.patch b/target/linux/brcm2708/patches-4.14/950-0332-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-interface.patch
deleted file mode 100644
index 0069c2b8e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0332-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-interface.patch
+++ /dev/null
@@ -1,2432 +0,0 @@
-From a961b21904be2f527afd87000d6bbf11d4ddecc8 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 11 Sep 2017 15:42:28 +0100
-Subject: [PATCH 332/454] bcm2835-unicam: Driver for CCP2/CSI2 camera interface
-
-Add driver for the Unicam camera receiver block on
-BCM283x processors.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/platform/Kconfig                |    1 +
- drivers/media/platform/Makefile               |    1 +
- drivers/media/platform/bcm2835/Kconfig        |   14 +
- drivers/media/platform/bcm2835/Makefile       |    3 +
- .../media/platform/bcm2835/bcm2835-unicam.c   | 2100 +++++++++++++++++
- .../media/platform/bcm2835/vc4-regs-unicam.h  |  264 +++
- 6 files changed, 2383 insertions(+)
- create mode 100644 drivers/media/platform/bcm2835/Kconfig
- create mode 100644 drivers/media/platform/bcm2835/Makefile
- create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c
- create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h
-
---- a/drivers/media/platform/Kconfig
-+++ b/drivers/media/platform/Kconfig
-@@ -150,6 +150,7 @@ source "drivers/media/platform/am437x/Kc
- source "drivers/media/platform/xilinx/Kconfig"
- source "drivers/media/platform/rcar-vin/Kconfig"
- source "drivers/media/platform/atmel/Kconfig"
-+source "drivers/media/platform/bcm2835/Kconfig"
- 
- config VIDEO_TI_CAL
- 	tristate "TI CAL (Camera Adaptation Layer) driver"
---- a/drivers/media/platform/Makefile
-+++ b/drivers/media/platform/Makefile
-@@ -91,3 +91,4 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS)		+= qcom/
- obj-$(CONFIG_VIDEO_QCOM_VENUS)		+= qcom/venus/
- 
- obj-y					+= meson/
-+obj-y					+= bcm2835/
---- /dev/null
-+++ b/drivers/media/platform/bcm2835/Kconfig
-@@ -0,0 +1,14 @@
-+# Broadcom VideoCore4 V4L2 camera support
-+
-+config VIDEO_BCM2835_UNICAM
-+	tristate "Broadcom BCM2835 Unicam video capture driver"
-+	depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
-+	depends on ARCH_BCM2835 || COMPILE_TEST
-+	select VIDEOBUF2_DMA_CONTIG
-+	select V4L2_FWNODE
-+	---help---
-+	  Say Y here to enable V4L2 subdevice for CSI2 receiver.
-+	  This is a V4L2 subdevice that interfaces directly to the VC4 peripheral.
-+
-+	   To compile this driver as a module, choose M here. The module
-+	   will be called bcm2835-unicam.
---- /dev/null
-+++ b/drivers/media/platform/bcm2835/Makefile
-@@ -0,0 +1,3 @@
-+# Makefile for BCM2835 Unicam driver
-+
-+obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o
---- /dev/null
-+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
-@@ -0,0 +1,2100 @@
-+/*
-+ * BCM2835 Unicam capture Driver
-+ *
-+ * Copyright (C) 2017 - Raspberry Pi (Trading) Ltd.
-+ *
-+ * Dave Stevenson <dave.stevenson@raspberrypi.org>
-+ *
-+ * Based on TI am437x driver by Benoit Parrot and Lad, Prabhakar and
-+ * TI CAL camera interface driver by Benoit Parrot.
-+ *
-+ *
-+ * There are two camera drivers in the kernel for BCM283x - this one
-+ * and bcm2835-camera (currently in staging).
-+ *
-+ * This driver directly controls the Unicam peripheral - there is no
-+ * involvement with the VideoCore firmware. Unicam receives CSI-2 or
-+ * CCP2 data and writes it into SDRAM. The only potential processing options are
-+ * to repack Bayer data into an alternate format, and applying windowing.
-+ * The repacking does not shift the data, so could repack V4L2_PIX_FMT_Sxxxx10P
-+ * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,
-+ * but not generically up to V4L2_PIX_FMT_Sxxxx16.
-+ * Adding support for repacking and windowing may be added later.
-+ *
-+ * It should be possible to connect this driver to any sensor with a
-+ * suitable output interface and V4L2 subdevice driver.
-+ *
-+ * bcm2835-camera uses the VideoCore firmware to control the sensor,
-+ * Unicam, ISP, and all tuner control loops. Fully processed frames are
-+ * delivered to the driver by the firmware. It only has sensor drivers
-+ * for Omnivision OV5647, and Sony IMX219 sensors.
-+ *
-+ * The two drivers are mutually exclusive for the same Unicam instance.
-+ * The VideoCore firmware checks the device tree configuration during boot.
-+ * If it finds device tree nodes called csi0 or csi1 it will block the
-+ * firmware from accessing the peripheral, and bcm2835-camera will
-+ * not be able to stream data.
-+ *
-+ *
-+ * This program is free software; you may redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; version 2 of the License.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
-+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-+ * SOFTWARE.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/device.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/of_graph.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/slab.h>
-+#include <linux/uaccess.h>
-+#include <linux/videodev2.h>
-+
-+#include <media/v4l2-common.h>
-+#include <media/v4l2-ctrls.h>
-+#include <media/v4l2-dev.h>
-+#include <media/v4l2-device.h>
-+#include <media/v4l2-dv-timings.h>
-+#include <media/v4l2-event.h>
-+#include <media/v4l2-ioctl.h>
-+#include <media/v4l2-fwnode.h>
-+#include <media/videobuf2-dma-contig.h>
-+
-+#include "vc4-regs-unicam.h"
-+
-+#define UNICAM_MODULE_NAME	"unicam"
-+#define UNICAM_VERSION		"0.1.0"
-+
-+static int debug;
-+module_param(debug, int, 0644);
-+MODULE_PARM_DESC(debug, "Debug level 0-3");
-+
-+#define unicam_dbg(level, dev, fmt, arg...)	\
-+		v4l2_dbg(level, debug, &(dev)->v4l2_dev, fmt, ##arg)
-+#define unicam_info(dev, fmt, arg...)	\
-+		v4l2_info(&(dev)->v4l2_dev, fmt, ##arg)
-+#define unicam_err(dev, fmt, arg...)	\
-+		v4l2_err(&(dev)->v4l2_dev, fmt, ##arg)
-+
-+/*
-+ * Stride is a 16 bit register, but also has to be a multiple of 16.
-+ */
-+#define BPL_ALIGNMENT		16
-+#define MAX_BYTESPERLINE	((1 << 16) - BPL_ALIGNMENT)
-+/*
-+ * Max width is therefore determined by the max stride divided by
-+ * the number of bits per pixel. Take 32bpp as a
-+ * worst case.
-+ * No imposed limit on the height, so adopt a square image for want
-+ * of anything better.
-+ */
-+#define MAX_WIDTH	(MAX_BYTESPERLINE / 4)
-+#define MAX_HEIGHT	MAX_WIDTH
-+/* Define a nominal minimum image size */
-+#define MIN_WIDTH	16
-+#define MIN_HEIGHT	16
-+/*
-+ * Whilst Unicam doesn't require any additional padding on the image
-+ * height, various other parts of the BCM283x frameworks require a multiple
-+ * of 16.
-+ * Seeing as image buffers are significantly larger than this extra
-+ * padding, add it in order to simplify integration.
-+ */
-+#define HEIGHT_ALIGNMENT	16
-+
-+/*
-+ * struct unicam_fmt - Unicam media bus format information
-+ * @pixelformat: V4L2 pixel format FCC identifier.
-+ * @code: V4L2 media bus format code.
-+ * @depth: Bits per pixel (when stored in memory).
-+ * @csi_dt: CSI data type.
-+ */
-+struct unicam_fmt {
-+	u32	fourcc;
-+	u32	code;
-+	u8	depth;
-+	u8	csi_dt;
-+};
-+
-+static const struct unicam_fmt formats[] = {
-+	/* YUV Formats */
-+	{
-+		.fourcc		= V4L2_PIX_FMT_YUYV,
-+		.code		= MEDIA_BUS_FMT_YUYV8_2X8,
-+		.depth		= 16,
-+		.csi_dt		= 0x1e,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_UYVY,
-+		.code		= MEDIA_BUS_FMT_UYVY8_2X8,
-+		.depth		= 16,
-+		.csi_dt		= 0x1e,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_YVYU,
-+		.code		= MEDIA_BUS_FMT_YVYU8_2X8,
-+		.depth		= 16,
-+		.csi_dt		= 0x1e,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_VYUY,
-+		.code		= MEDIA_BUS_FMT_VYUY8_2X8,
-+		.depth		= 16,
-+		.csi_dt		= 0x1e,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_YUYV,
-+		.code		= MEDIA_BUS_FMT_YUYV8_1X16,
-+		.depth		= 16,
-+		.csi_dt		= 0x1e,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_UYVY,
-+		.code		= MEDIA_BUS_FMT_UYVY8_1X16,
-+		.depth		= 16,
-+		.csi_dt		= 0x1e,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_YVYU,
-+		.code		= MEDIA_BUS_FMT_YVYU8_1X16,
-+		.depth		= 16,
-+		.csi_dt		= 0x1e,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_VYUY,
-+		.code		= MEDIA_BUS_FMT_VYUY8_1X16,
-+		.depth		= 16,
-+		.csi_dt		= 0x1e,
-+	}, {
-+	/* RGB Formats */
-+		.fourcc		= V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
-+		.code		= MEDIA_BUS_FMT_RGB565_2X8_LE,
-+		.depth		= 16,
-+		.csi_dt		= 0x22,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
-+		.code		= MEDIA_BUS_FMT_RGB565_2X8_BE,
-+		.depth		= 16,
-+		.csi_dt		= 0x22
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
-+		.code		= MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
-+		.depth		= 16,
-+		.csi_dt		= 0x21,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
-+		.code		= MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
-+		.depth		= 16,
-+		.csi_dt		= 0x21,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_RGB24, /* rgb */
-+		.code		= MEDIA_BUS_FMT_RGB888_1X24,
-+		.depth		= 24,
-+		.csi_dt		= 0x24,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_BGR24, /* bgr */
-+		.code		= MEDIA_BUS_FMT_BGR888_1X24,
-+		.depth		= 24,
-+		.csi_dt		= 0x24,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_RGB32, /* argb */
-+		.code		= MEDIA_BUS_FMT_ARGB8888_1X32,
-+		.depth		= 32,
-+		.csi_dt		= 0x0,
-+	}, {
-+	/* Bayer Formats */
-+		.fourcc		= V4L2_PIX_FMT_SBGGR8,
-+		.code		= MEDIA_BUS_FMT_SBGGR8_1X8,
-+		.depth		= 8,
-+		.csi_dt		= 0x2a,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SGBRG8,
-+		.code		= MEDIA_BUS_FMT_SGBRG8_1X8,
-+		.depth		= 8,
-+		.csi_dt		= 0x2a,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SGRBG8,
-+		.code		= MEDIA_BUS_FMT_SGRBG8_1X8,
-+		.depth		= 8,
-+		.csi_dt		= 0x2a,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SRGGB8,
-+		.code		= MEDIA_BUS_FMT_SRGGB8_1X8,
-+		.depth		= 8,
-+		.csi_dt		= 0x2a,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SBGGR10P,
-+		.code		= MEDIA_BUS_FMT_SBGGR10_1X10,
-+		.depth		= 10,
-+		.csi_dt		= 0x2b,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SGBRG10P,
-+		.code		= MEDIA_BUS_FMT_SGBRG10_1X10,
-+		.depth		= 10,
-+		.csi_dt		= 0x2b,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SGRBG10P,
-+		.code		= MEDIA_BUS_FMT_SGRBG10_1X10,
-+		.depth		= 10,
-+		.csi_dt		= 0x2b,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SRGGB10P,
-+		.code		= MEDIA_BUS_FMT_SRGGB10_1X10,
-+		.depth		= 10,
-+		.csi_dt		= 0x2b,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SBGGR12P,
-+		.code		= MEDIA_BUS_FMT_SBGGR12_1X12,
-+		.depth		= 12,
-+		.csi_dt		= 0x2c,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SGBRG12P,
-+		.code		= MEDIA_BUS_FMT_SGBRG12_1X12,
-+		.depth		= 12,
-+		.csi_dt		= 0x2c,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SGRBG12P,
-+		.code		= MEDIA_BUS_FMT_SGRBG12_1X12,
-+		.depth		= 12,
-+		.csi_dt		= 0x2c,
-+	}, {
-+		.fourcc		= V4L2_PIX_FMT_SRGGB12P,
-+		.code		= MEDIA_BUS_FMT_SRGGB12_1X12,
-+		.depth		= 12,
-+		.csi_dt		= 0x2c,
-+	},
-+	/*
-+	 * 14 and 16 bit Bayer formats could be supported, but there are no V4L2
-+	 * defines for 14bit packed Bayer, and no CSI2 data_type for raw 16.
-+	 */
-+};
-+
-+struct unicam_dmaqueue {
-+	struct list_head	active;
-+};
-+
-+struct unicam_buffer {
-+	struct vb2_v4l2_buffer vb;
-+	struct list_head list;
-+};
-+
-+struct unicam_cfg {
-+	/* peripheral base address */
-+	void __iomem *base;
-+	/* clock gating base address */
-+	void __iomem *clk_gate_base;
-+};
-+
-+#define MAX_POSSIBLE_PIX_FMTS (ARRAY_SIZE(formats))
-+
-+struct unicam_device {
-+	/* V4l2 specific parameters */
-+	/* Identifies video device for this channel */
-+	struct video_device video_dev;
-+	struct v4l2_ctrl_handler ctrl_handler;
-+
-+	struct v4l2_fwnode_endpoint endpoint;
-+
-+	struct v4l2_async_subdev asd;
-+
-+	/* unicam cfg */
-+	struct unicam_cfg cfg;
-+	/* clock handle */
-+	struct clk *clock;
-+	/* V4l2 device */
-+	struct v4l2_device v4l2_dev;
-+	/* parent device */
-+	struct platform_device *pdev;
-+	/* subdevice async Notifier */
-+	struct v4l2_async_notifier notifier;
-+	unsigned int sequence;
-+
-+	/* ptr to  sub device */
-+	struct v4l2_subdev *sensor;
-+	/* Pad config for the sensor */
-+	struct v4l2_subdev_pad_config *sensor_config;
-+	/* current input at the sub device */
-+	int current_input;
-+
-+	/* Pointer pointing to current v4l2_buffer */
-+	struct unicam_buffer *cur_frm;
-+	/* Pointer pointing to next v4l2_buffer */
-+	struct unicam_buffer *next_frm;
-+
-+	/* video capture */
-+	const struct unicam_fmt	*fmt;
-+	/* Used to store current pixel format */
-+	struct v4l2_format v_fmt;
-+	/* Used to store current mbus frame format */
-+	struct v4l2_mbus_framefmt m_fmt;
-+
-+	struct unicam_fmt active_fmts[MAX_POSSIBLE_PIX_FMTS];
-+	int num_active_fmt;
-+	unsigned int virtual_channel;
-+	enum v4l2_mbus_type bus_type;
-+	/*
-+	 * Stores bus.mipi_csi2.flags for CSI2 sensors, or
-+	 * bus.mipi_csi1.strobe for CCP2.
-+	 */
-+	unsigned int bus_flags;
-+	unsigned int max_data_lanes;
-+	unsigned int active_data_lanes;
-+
-+	struct v4l2_rect crop;
-+
-+	/* Currently selected input on subdev */
-+	int input;
-+
-+	/* Buffer queue used in video-buf */
-+	struct vb2_queue buffer_queue;
-+	/* Queue of filled frames */
-+	struct unicam_dmaqueue dma_queue;
-+	/* IRQ lock for DMA queue */
-+	spinlock_t dma_queue_lock;
-+	/* lock used to access this structure */
-+	struct mutex lock;
-+	/* Flag to denote that we are processing buffers */
-+	int streaming;
-+};
-+
-+/* Hardware access */
-+#define clk_write(dev, val) writel((val) | 0x5a000000, (dev)->clk_gate_base)
-+#define clk_read(dev) readl((dev)->clk_gate_base)
-+
-+#define reg_read(dev, offset) readl((dev)->base + (offset))
-+#define reg_write(dev, offset, val) writel(val, (dev)->base + (offset))
-+
-+#define reg_read_field(dev, offset, mask) get_field(reg_read((dev), (offset), \
-+						    mask))
-+
-+static inline int get_field(u32 value, u32 mask)
-+{
-+	return (value & mask) >> __ffs(mask);
-+}
-+
-+static inline void set_field(u32 *valp, u32 field, u32 mask)
-+{
-+	u32 val = *valp;
-+
-+	val &= ~mask;
-+	val |= (field << __ffs(mask)) & mask;
-+	*valp = val;
-+}
-+
-+static inline void reg_write_field(struct unicam_cfg *dev, u32 offset,
-+				   u32 field, u32 mask)
-+{
-+	u32 val = reg_read((dev), (offset));
-+
-+	set_field(&val, field, mask);
-+	reg_write((dev), (offset), val);
-+}
-+
-+/* Power management functions */
-+static inline int unicam_runtime_get(struct unicam_device *dev)
-+{
-+	int r;
-+
-+	r = pm_runtime_get_sync(&dev->pdev->dev);
-+
-+	return r;
-+}
-+
-+static inline void unicam_runtime_put(struct unicam_device *dev)
-+{
-+	pm_runtime_put_sync(&dev->pdev->dev);
-+}
-+
-+/* Format setup functions */
-+static int find_mbus_depth_by_code(u32 code)
-+{
-+	const struct unicam_fmt *fmt;
-+	unsigned int k;
-+
-+	for (k = 0; k < ARRAY_SIZE(formats); k++) {
-+		fmt = &formats[k];
-+		if (fmt->code == code)
-+			return fmt->depth;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct unicam_fmt *find_format_by_code(struct unicam_device *dev,
-+						    u32 code)
-+{
-+	const struct unicam_fmt *fmt;
-+	unsigned int k;
-+
-+	for (k = 0; k < dev->num_active_fmt; k++) {
-+		fmt = &dev->active_fmts[k];
-+		if (fmt->code == code)
-+			return fmt;
-+	}
-+
-+	return NULL;
-+}
-+
-+static const struct unicam_fmt *find_format_by_pix(struct unicam_device *dev,
-+						   u32 pixelformat)
-+{
-+	const struct unicam_fmt *fmt;
-+	unsigned int k;
-+
-+	for (k = 0; k < dev->num_active_fmt; k++) {
-+		fmt = &dev->active_fmts[k];
-+		if (fmt->fourcc == pixelformat)
-+			return fmt;
-+	}
-+
-+	return NULL;
-+}
-+
-+static void dump_active_formats(struct unicam_device *dev)
-+{
-+	int i;
-+
-+	for (i = 0; i < dev->num_active_fmt; i++) {
-+		unicam_dbg(3, dev, "active_fmt[%d] (%p) is code %04x, fourcc " V4L2_FOURCC_CONV ", depth %d\n",
-+			   i, &dev->active_fmts[i], dev->active_fmts[i].code,
-+			   V4L2_FOURCC_CONV_ARGS(dev->active_fmts[i].fourcc),
-+			   dev->active_fmts[i].depth);
-+	}
-+}
-+
-+static inline unsigned int bytes_per_line(u32 width,
-+					  const struct unicam_fmt *fmt)
-+{
-+	return ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);
-+}
-+
-+static int __subdev_get_format(struct unicam_device *dev,
-+			       struct v4l2_mbus_framefmt *fmt)
-+{
-+	struct v4l2_subdev_format sd_fmt = {0};
-+	struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
-+	int ret;
-+
-+	sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
-+	sd_fmt.pad = 0;
-+
-+	ret = v4l2_subdev_call(dev->sensor, pad, get_fmt, dev->sensor_config,
-+			       &sd_fmt);
-+	if (ret < 0)
-+		return ret;
-+
-+	*fmt = *mbus_fmt;
-+
-+	unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
-+		   fmt->width, fmt->height, fmt->code);
-+
-+	return 0;
-+}
-+
-+static int __subdev_set_format(struct unicam_device *dev,
-+			       struct v4l2_mbus_framefmt *fmt)
-+{
-+	struct v4l2_subdev_format sd_fmt = {
-+		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
-+	};
-+	struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
-+	int ret;
-+
-+	*mbus_fmt = *fmt;
-+
-+	ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
-+			       &sd_fmt);
-+	if (ret < 0)
-+		return ret;
-+
-+	unicam_dbg(1, dev, "%s %dx%d code:%04x\n", __func__,
-+		   fmt->width, fmt->height, fmt->code);
-+
-+	return 0;
-+}
-+
-+static int unicam_calc_format_size_bpl(struct unicam_device *dev,
-+				       const struct unicam_fmt *fmt,
-+				       struct v4l2_format *f)
-+{
-+	unsigned int min_bytesperline;
-+
-+	v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,
-+			      &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,
-+			      0);
-+
-+	min_bytesperline = bytes_per_line(f->fmt.pix.width, fmt);
-+
-+	if (f->fmt.pix.bytesperline > min_bytesperline &&
-+	    f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)
-+		f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
-+						BPL_ALIGNMENT);
-+	else
-+		f->fmt.pix.bytesperline = min_bytesperline;
-+
-+	/* Align height up for compatibility with other hardware blocks */
-+	f->fmt.pix.sizeimage = ALIGN(f->fmt.pix.height, HEIGHT_ALIGNMENT) *
-+			       f->fmt.pix.bytesperline;
-+
-+	unicam_dbg(3, dev, "%s: fourcc: " V4L2_FOURCC_CONV " size: %dx%d bpl:%d img_size:%d\n",
-+		   __func__,
-+		   V4L2_FOURCC_CONV_ARGS(f->fmt.pix.pixelformat),
-+		   f->fmt.pix.width, f->fmt.pix.height,
-+		   f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
-+
-+	return 0;
-+}
-+
-+static int unicam_reset_format(struct unicam_device *dev)
-+{
-+	struct v4l2_mbus_framefmt mbus_fmt;
-+	int ret;
-+
-+	ret = __subdev_get_format(dev, &mbus_fmt);
-+	if (ret) {
-+		unicam_err(dev, "Failed to get_format - ret %d\n", ret);
-+		return ret;
-+	}
-+
-+	if (mbus_fmt.code != dev->fmt->code) {
-+		unicam_err(dev, "code mismatch - fmt->code %08x, mbus_fmt.code %08x\n",
-+			   dev->fmt->code, mbus_fmt.code);
-+		return ret;
-+	}
-+
-+	v4l2_fill_pix_format(&dev->v_fmt.fmt.pix, &mbus_fmt);
-+	dev->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-+
-+	unicam_calc_format_size_bpl(dev, dev->fmt, &dev->v_fmt);
-+
-+	dev->m_fmt = mbus_fmt;
-+
-+	return 0;
-+}
-+
-+static void unicam_wr_dma_addr(struct unicam_device *dev, unsigned int dmaaddr)
-+{
-+	unicam_dbg(1, dev, "wr_dma_addr %08x-%08x\n",
-+		   dmaaddr, dmaaddr + dev->v_fmt.fmt.pix.sizeimage);
-+	reg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);
-+	reg_write(&dev->cfg, UNICAM_IBEA0,
-+		  dmaaddr + dev->v_fmt.fmt.pix.sizeimage);
-+}
-+
-+static inline void unicam_schedule_next_buffer(struct unicam_device *dev)
-+{
-+	struct unicam_dmaqueue *dma_q = &dev->dma_queue;
-+	struct unicam_buffer *buf;
-+	dma_addr_t addr;
-+
-+	buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
-+	dev->next_frm = buf;
-+	list_del(&buf->list);
-+
-+	addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
-+	unicam_wr_dma_addr(dev, addr);
-+}
-+
-+static inline void unicam_process_buffer_complete(struct unicam_device *dev)
-+{
-+	dev->cur_frm->vb.field = dev->m_fmt.field;
-+	dev->cur_frm->vb.sequence = dev->sequence++;
-+
-+	vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
-+	dev->cur_frm = dev->next_frm;
-+}
-+
-+/*
-+ * unicam_isr : ISR handler for unicam capture
-+ * @irq: irq number
-+ * @dev_id: dev_id ptr
-+ *
-+ * It changes status of the captured buffer, takes next buffer from the queue
-+ * and sets its address in unicam registers
-+ */
-+static irqreturn_t unicam_isr(int irq, void *dev)
-+{
-+	struct unicam_device *unicam = (struct unicam_device *)dev;
-+	struct unicam_cfg *cfg = &unicam->cfg;
-+	struct unicam_dmaqueue *dma_q = &unicam->dma_queue;
-+	int ista, sta;
-+
-+	/*
-+	 * Don't service interrupts if not streaming.
-+	 * Avoids issues if the VPU should enable the
-+	 * peripheral without the kernel knowing (that
-+	 * shouldn't happen, but causes issues if it does).
-+	 */
-+	if (!unicam->streaming)
-+		return IRQ_HANDLED;
-+
-+	sta = reg_read(cfg, UNICAM_STA);
-+	/* Write value back to clear the interrupts */
-+	reg_write(cfg, UNICAM_STA, sta);
-+
-+	ista = reg_read(cfg, UNICAM_ISTA);
-+	/* Write value back to clear the interrupts */
-+	reg_write(cfg, UNICAM_ISTA, ista);
-+
-+	if (!(sta && (UNICAM_IS | UNICAM_PI0)))
-+		return IRQ_HANDLED;
-+
-+	if (ista & UNICAM_FSI) {
-+		/*
-+		 * Timestamp is to be when the first data byte was captured,
-+		 * aka frame start.
-+		 */
-+		if (unicam->cur_frm)
-+			unicam->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
-+	}
-+	if (ista & UNICAM_FEI || sta & UNICAM_PI0) {
-+		/*
-+		 * Ensure we have swapped buffers already as we can't
-+		 * stop the peripheral. Overwrite the frame we've just
-+		 * captured instead.
-+		 */
-+		if (unicam->cur_frm && unicam->cur_frm != unicam->next_frm)
-+			unicam_process_buffer_complete(unicam);
-+	}
-+
-+	if (ista & (UNICAM_FSI | UNICAM_LCI)) {
-+		spin_lock(&unicam->dma_queue_lock);
-+		if (!list_empty(&dma_q->active) &&
-+		    unicam->cur_frm == unicam->next_frm)
-+			unicam_schedule_next_buffer(unicam);
-+		spin_unlock(&unicam->dma_queue_lock);
-+	}
-+
-+	if (reg_read(&unicam->cfg, UNICAM_ICTL) & UNICAM_FCM) {
-+		/* Switch out of trigger mode if selected */
-+		reg_write_field(&unicam->cfg, UNICAM_ICTL, 1, UNICAM_TFC);
-+		reg_write_field(&unicam->cfg, UNICAM_ICTL, 0, UNICAM_FCM);
-+	}
-+	return IRQ_HANDLED;
-+}
-+
-+static int unicam_querycap(struct file *file, void *priv,
-+			   struct v4l2_capability *cap)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	strlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));
-+	strlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));
-+
-+	snprintf(cap->bus_info, sizeof(cap->bus_info),
-+		 "platform:%s", dev->v4l2_dev.name);
-+
-+	return 0;
-+}
-+
-+static int unicam_enum_fmt_vid_cap(struct file *file, void  *priv,
-+				   struct v4l2_fmtdesc *f)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+	const struct unicam_fmt *fmt = NULL;
-+
-+	if (f->index >= dev->num_active_fmt)
-+		return -EINVAL;
-+
-+	fmt = &dev->active_fmts[f->index];
-+
-+	f->pixelformat = fmt->fourcc;
-+
-+	return 0;
-+}
-+
-+static int unicam_g_fmt_vid_cap(struct file *file, void *priv,
-+				struct v4l2_format *f)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	*f = dev->v_fmt;
-+
-+	return 0;
-+}
-+
-+static int unicam_try_fmt_vid_cap(struct file *file, void *priv,
-+				  struct v4l2_format *f)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+	const struct unicam_fmt *fmt;
-+	struct v4l2_subdev_format sd_fmt = {
-+		.which = V4L2_SUBDEV_FORMAT_TRY,
-+	};
-+	struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
-+	int ret;
-+
-+	fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
-+	if (!fmt) {
-+		unicam_dbg(3, dev, "Fourcc format (0x%08x) not found. Use default of %08X\n",
-+			   f->fmt.pix.pixelformat, dev->active_fmts[0].fourcc);
-+
-+		/* Just get the first one enumerated */
-+		fmt = &dev->active_fmts[0];
-+		f->fmt.pix.pixelformat = fmt->fourcc;
-+	}
-+
-+	v4l2_fill_mbus_format(mbus_fmt, &f->fmt.pix, fmt->code);
-+	/*
-+	 * No support for receiving interlaced video, so never
-+	 * request it from the sensor subdev.
-+	 */
-+	mbus_fmt->field = V4L2_FIELD_NONE;
-+
-+	ret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,
-+			       &sd_fmt);
-+	if (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)
-+		return ret;
-+
-+	if (mbus_fmt->field != V4L2_FIELD_NONE)
-+		unicam_info(dev, "Sensor trying to send interlaced video - results may be unpredictable\n");
-+
-+	v4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);
-+	/*
-+	 * Use current colorspace for now, it will get
-+	 * updated properly during s_fmt
-+	 */
-+	f->fmt.pix.colorspace = dev->v_fmt.fmt.pix.colorspace;
-+	return unicam_calc_format_size_bpl(dev, fmt, f);
-+}
-+
-+static int unicam_s_fmt_vid_cap(struct file *file, void *priv,
-+				struct v4l2_format *f)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+	struct vb2_queue *q = &dev->buffer_queue;
-+	const struct unicam_fmt *fmt;
-+	struct v4l2_mbus_framefmt mbus_fmt = {0};
-+	int ret;
-+
-+	if (vb2_is_busy(q))
-+		return -EBUSY;
-+
-+	ret = unicam_try_fmt_vid_cap(file, priv, f);
-+	if (ret < 0)
-+		return ret;
-+
-+	fmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);
-+	if (!fmt) {
-+		/* Unknown pixel format - adopt a default */
-+		fmt = &dev->active_fmts[0];
-+		f->fmt.pix.pixelformat = fmt->fourcc;
-+		return -EINVAL;
-+	}
-+
-+	v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);
-+
-+	ret = __subdev_set_format(dev, &mbus_fmt);
-+	if (ret) {
-+		unicam_dbg(3, dev, "%s __subdev_set_format failed %d\n",
-+			   __func__, ret);
-+		return ret;
-+	}
-+
-+	/* Just double check nothing has gone wrong */
-+	if (mbus_fmt.code != fmt->code) {
-+		unicam_dbg(3, dev,
-+			   "%s subdev changed format on us, this should not happen\n",
-+			   __func__);
-+		return -EINVAL;
-+	}
-+
-+	dev->fmt = fmt;
-+	dev->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;
-+	dev->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;
-+	unicam_reset_format(dev);
-+
-+	unicam_dbg(3, dev, "%s %dx%d, mbus_fmt %08X, V4L2 pix " V4L2_FOURCC_CONV ".\n",
-+		   __func__, dev->v_fmt.fmt.pix.width,
-+		   dev->v_fmt.fmt.pix.height, mbus_fmt.code,
-+		   V4L2_FOURCC_CONV_ARGS(dev->v_fmt.fmt.pix.pixelformat));
-+
-+	*f = dev->v_fmt;
-+
-+	return 0;
-+}
-+
-+static int unicam_queue_setup(struct vb2_queue *vq,
-+			      unsigned int *nbuffers,
-+			      unsigned int *nplanes,
-+			      unsigned int sizes[],
-+			      struct device *alloc_devs[])
-+{
-+	struct unicam_device *dev = vb2_get_drv_priv(vq);
-+	unsigned int size = dev->v_fmt.fmt.pix.sizeimage;
-+
-+	if (vq->num_buffers + *nbuffers < 3)
-+		*nbuffers = 3 - vq->num_buffers;
-+
-+	if (*nplanes) {
-+		if (sizes[0] < size) {
-+			unicam_err(dev, "sizes[0] %i < size %u\n", sizes[0],
-+				   size);
-+			return -EINVAL;
-+		}
-+		size = sizes[0];
-+	}
-+
-+	*nplanes = 1;
-+	sizes[0] = size;
-+
-+	return 0;
-+}
-+
-+static int unicam_buffer_prepare(struct vb2_buffer *vb)
-+{
-+	struct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);
-+	struct unicam_buffer *buf = container_of(vb, struct unicam_buffer,
-+					      vb.vb2_buf);
-+	unsigned long size;
-+
-+	if (WARN_ON(!dev->fmt))
-+		return -EINVAL;
-+
-+	size = dev->v_fmt.fmt.pix.sizeimage;
-+	if (vb2_plane_size(vb, 0) < size) {
-+		unicam_err(dev, "data will not fit into plane (%lu < %lu)\n",
-+			   vb2_plane_size(vb, 0), size);
-+		return -EINVAL;
-+	}
-+
-+	vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
-+	return 0;
-+}
-+
-+static void unicam_buffer_queue(struct vb2_buffer *vb)
-+{
-+	struct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);
-+	struct unicam_buffer *buf = container_of(vb, struct unicam_buffer,
-+					      vb.vb2_buf);
-+	struct unicam_dmaqueue *dma_queue = &dev->dma_queue;
-+	unsigned long flags = 0;
-+
-+	/* recheck locking */
-+	spin_lock_irqsave(&dev->dma_queue_lock, flags);
-+	list_add_tail(&buf->list, &dma_queue->active);
-+	spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
-+}
-+
-+static void unicam_wr_dma_config(struct unicam_device *dev,
-+				 unsigned int stride)
-+{
-+	reg_write(&dev->cfg, UNICAM_IBLS, stride);
-+}
-+
-+static void unicam_set_packing_config(struct unicam_device *dev)
-+{
-+	int mbus_depth = find_mbus_depth_by_code(dev->fmt->code);
-+	int v4l2_depth = dev->fmt->depth;
-+	int pack, unpack;
-+	u32 val;
-+
-+	if (mbus_depth == v4l2_depth) {
-+		unpack = UNICAM_PUM_NONE;
-+		pack = UNICAM_PPM_NONE;
-+	} else {
-+		switch (mbus_depth) {
-+		case 8:
-+			unpack = UNICAM_PUM_UNPACK8;
-+			break;
-+		case 10:
-+			unpack = UNICAM_PUM_UNPACK10;
-+			break;
-+		case 12:
-+			unpack = UNICAM_PUM_UNPACK12;
-+			break;
-+		case 14:
-+			unpack = UNICAM_PUM_UNPACK14;
-+			break;
-+		case 16:
-+			unpack = UNICAM_PUM_UNPACK16;
-+			break;
-+		default:
-+			unpack = UNICAM_PUM_NONE;
-+			break;
-+		}
-+		switch (v4l2_depth) {
-+		case 8:
-+			pack = UNICAM_PPM_PACK8;
-+			break;
-+		case 10:
-+			pack = UNICAM_PPM_PACK10;
-+			break;
-+		case 12:
-+			pack = UNICAM_PPM_PACK12;
-+			break;
-+		case 14:
-+			pack = UNICAM_PPM_PACK14;
-+			break;
-+		case 16:
-+			pack = UNICAM_PPM_PACK16;
-+			break;
-+		default:
-+			pack = UNICAM_PPM_NONE;
-+			break;
-+		}
-+	}
-+
-+	val = 0;
-+	set_field(&val, 2, UNICAM_DEBL_MASK);
-+	set_field(&val, unpack, UNICAM_PUM_MASK);
-+	set_field(&val, pack, UNICAM_PPM_MASK);
-+	reg_write(&dev->cfg, UNICAM_IPIPE, val);
-+}
-+
-+static void unicam_cfg_image_id(struct unicam_device *dev)
-+{
-+	struct unicam_cfg *cfg = &dev->cfg;
-+
-+	if (dev->bus_type == V4L2_MBUS_CSI2) {
-+		/* CSI2 mode */
-+		reg_write(cfg, UNICAM_IDI0,
-+			  (dev->virtual_channel << 6) | dev->fmt->csi_dt);
-+	} else {
-+		/* CCP2 mode */
-+		reg_write(cfg, UNICAM_IDI0, (0x80 | dev->fmt->csi_dt));
-+	}
-+}
-+
-+void unicam_start_rx(struct unicam_device *dev, unsigned long addr)
-+{
-+	struct unicam_cfg *cfg = &dev->cfg;
-+	int line_int_freq = dev->v_fmt.fmt.pix.height >> 2;
-+	unsigned int i;
-+	u32 val;
-+
-+	if (line_int_freq < 128)
-+		line_int_freq = 128;
-+
-+	/* Enable lane clocks */
-+	val = 1;
-+	for (i = 0; i < dev->active_data_lanes; i++)
-+		val = val << 2 | 1;
-+	clk_write(cfg, val);
-+
-+	/* Basic init */
-+	reg_write(cfg, UNICAM_CTRL, UNICAM_MEM);
-+
-+	/* Enable analogue control, and leave in reset. */
-+	val = UNICAM_AR;
-+	set_field(&val, 7, UNICAM_CTATADJ_MASK);
-+	set_field(&val, 7, UNICAM_PTATADJ_MASK);
-+	reg_write(cfg, UNICAM_ANA, val);
-+	usleep_range(1000, 2000);
-+
-+	/* Come out of reset */
-+	reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_AR);
-+
-+	/* Peripheral reset */
-+	reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);
-+	reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);
-+
-+	reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);
-+
-+	/* Enable Rx control. */
-+	val = reg_read(cfg, UNICAM_CTRL);
-+	if (dev->bus_type == V4L2_MBUS_CSI2) {
-+		set_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);
-+		set_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);
-+	} else {
-+		set_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);
-+		set_field(&val, dev->bus_flags, UNICAM_DCM_MASK);
-+	}
-+	/* Packet framer timeout */
-+	set_field(&val, 0xf, UNICAM_PFT_MASK);
-+	set_field(&val, 128, UNICAM_OET_MASK);
-+	reg_write(cfg, UNICAM_CTRL, val);
-+
-+	reg_write(cfg, UNICAM_IHWIN, 0);
-+	reg_write(cfg, UNICAM_IVWIN, 0);
-+
-+	/* AXI bus access QoS setup */
-+	val = reg_read(&dev->cfg, UNICAM_PRI);
-+	set_field(&val, 0, UNICAM_BL_MASK);
-+	set_field(&val, 0, UNICAM_BS_MASK);
-+	set_field(&val, 0xe, UNICAM_PP_MASK);
-+	set_field(&val, 8, UNICAM_NP_MASK);
-+	set_field(&val, 2, UNICAM_PT_MASK);
-+	set_field(&val, 1, UNICAM_PE);
-+	reg_write(cfg, UNICAM_PRI, val);
-+
-+	reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_DDL);
-+
-+	/* Always start in trigger frame capture mode (UNICAM_FCM set) */
-+	val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM;
-+	set_field(&val,  line_int_freq, UNICAM_LCIE_MASK);
-+	reg_write(cfg, UNICAM_ICTL, val);
-+	reg_write(cfg, UNICAM_STA, UNICAM_STA_MASK_ALL);
-+	reg_write(cfg, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);
-+
-+	/* tclk_term_en */
-+	reg_write_field(cfg, UNICAM_CLT, 2, UNICAM_CLT1_MASK);
-+	/* tclk_settle */
-+	reg_write_field(cfg, UNICAM_CLT, 6, UNICAM_CLT2_MASK);
-+	/* td_term_en */
-+	reg_write_field(cfg, UNICAM_DLT, 2, UNICAM_DLT1_MASK);
-+	/* ths_settle */
-+	reg_write_field(cfg, UNICAM_DLT, 6, UNICAM_DLT2_MASK);
-+	/* trx_enable */
-+	reg_write_field(cfg, UNICAM_DLT, 0, UNICAM_DLT3_MASK);
-+
-+	reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_SOE);
-+
-+	/* Packet compare setup - required to avoid missing frame ends */
-+	val = 0;
-+	set_field(&val, 1, UNICAM_PCE);
-+	set_field(&val, 1, UNICAM_GI);
-+	set_field(&val, 1, UNICAM_CPH);
-+	set_field(&val, 0, UNICAM_PCVC_MASK);
-+	set_field(&val, 1, UNICAM_PCDT_MASK);
-+	reg_write(cfg, UNICAM_CMP0, val);
-+
-+	/* Enable clock lane and set up terminations */
-+	val = 0;
-+	if (dev->bus_type == V4L2_MBUS_CSI2) {
-+		/* CSI2 */
-+		set_field(&val, 1, UNICAM_CLE);
-+		set_field(&val, 1, UNICAM_CLLPE);
-+		if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
-+			set_field(&val, 1, UNICAM_CLTRE);
-+			set_field(&val, 1, UNICAM_CLHSE);
-+		}
-+	} else {
-+		/* CCP2 */
-+		set_field(&val, 1, UNICAM_CLE);
-+		set_field(&val, 1, UNICAM_CLHSE);
-+		set_field(&val, 1, UNICAM_CLTRE);
-+	}
-+	reg_write(cfg, UNICAM_CLK, val);
-+
-+	/*
-+	 * Enable required data lanes with appropriate terminations.
-+	 * The same value needs to be written to UNICAM_DATn registers for
-+	 * the active lanes, and 0 for inactive ones.
-+	 */
-+	val = 0;
-+	if (dev->bus_type == V4L2_MBUS_CSI2) {
-+		/* CSI2 */
-+		set_field(&val, 1, UNICAM_DLE);
-+		set_field(&val, 1, UNICAM_DLLPE);
-+		if (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {
-+			set_field(&val, 1, UNICAM_DLTRE);
-+			set_field(&val, 1, UNICAM_DLHSE);
-+		}
-+	} else {
-+		/* CCP2 */
-+		set_field(&val, 1, UNICAM_DLE);
-+		set_field(&val, 1, UNICAM_DLHSE);
-+		set_field(&val, 1, UNICAM_DLTRE);
-+	}
-+	reg_write(cfg, UNICAM_DAT0, val);
-+
-+	if (dev->active_data_lanes == 1)
-+		val = 0;
-+	reg_write(cfg, UNICAM_DAT1, val);
-+
-+	if (dev->max_data_lanes > 2) {
-+		/*
-+		 * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the
-+		 * instance supports more than 2 data lanes.
-+		 */
-+		if (dev->active_data_lanes == 2)
-+			val = 0;
-+		reg_write(cfg, UNICAM_DAT2, val);
-+
-+		if (dev->active_data_lanes == 3)
-+			val = 0;
-+		reg_write(cfg, UNICAM_DAT3, val);
-+	}
-+
-+	unicam_wr_dma_config(dev, dev->v_fmt.fmt.pix.bytesperline);
-+	unicam_wr_dma_addr(dev, addr);
-+	unicam_set_packing_config(dev);
-+	unicam_cfg_image_id(dev);
-+
-+	/* Disabled embedded data */
-+	val = 0;
-+	set_field(&val, 0, UNICAM_EDL_MASK);
-+	reg_write(cfg, UNICAM_DCS, val);
-+
-+	val = reg_read(cfg, UNICAM_MISC);
-+	set_field(&val, 1, UNICAM_FL0);
-+	set_field(&val, 1, UNICAM_FL1);
-+	reg_write(cfg, UNICAM_MISC, val);
-+
-+	/* Enable peripheral */
-+	reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPE);
-+
-+	/* Load image pointers */
-+	reg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_LIP_MASK);
-+
-+	/*
-+	 * Enable trigger only for the first frame to
-+	 * sync correctly to the FS from the source.
-+	 */
-+	reg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_TFC);
-+}
-+
-+static void unicam_disable(struct unicam_device *dev)
-+{
-+	struct unicam_cfg *cfg = &dev->cfg;
-+
-+	/* Analogue lane control disable */
-+	reg_write_field(cfg, UNICAM_ANA, 1, UNICAM_DDL);
-+
-+	/* Stop the output engine */
-+	reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_SOE);
-+
-+	/* Disable the data lanes. */
-+	reg_write(cfg, UNICAM_DAT0, 0);
-+	reg_write(cfg, UNICAM_DAT1, 0);
-+
-+	if (dev->max_data_lanes > 2) {
-+		reg_write(cfg, UNICAM_DAT2, 0);
-+		reg_write(cfg, UNICAM_DAT3, 0);
-+	}
-+
-+	/* Peripheral reset */
-+	reg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);
-+	usleep_range(50, 100);
-+	reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);
-+
-+	/* Disable peripheral */
-+	reg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);
-+
-+	/* Disable all lane clocks */
-+	clk_write(cfg, 0);
-+}
-+
-+static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)
-+{
-+	struct unicam_device *dev = vb2_get_drv_priv(vq);
-+	struct unicam_dmaqueue *dma_q = &dev->dma_queue;
-+	struct unicam_buffer *buf, *tmp;
-+	unsigned long addr = 0;
-+	unsigned long flags;
-+	int ret;
-+
-+	spin_lock_irqsave(&dev->dma_queue_lock, flags);
-+	buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
-+	dev->cur_frm = buf;
-+	dev->next_frm = buf;
-+	list_del(&buf->list);
-+	spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
-+
-+	addr = vb2_dma_contig_plane_dma_addr(&dev->cur_frm->vb.vb2_buf, 0);
-+	dev->sequence = 0;
-+
-+	ret = unicam_runtime_get(dev);
-+	if (ret < 0) {
-+		unicam_dbg(3, dev, "unicam_runtime_get failed\n");
-+		goto err_release_buffers;
-+	}
-+
-+	dev->active_data_lanes = dev->max_data_lanes;
-+	if (dev->bus_type == V4L2_MBUS_CSI2 &&
-+	    v4l2_subdev_has_op(dev->sensor, video, g_mbus_config)) {
-+		struct v4l2_mbus_config mbus_config;
-+
-+		ret = v4l2_subdev_call(dev->sensor, video, g_mbus_config,
-+				       &mbus_config);
-+		if (ret < 0) {
-+			unicam_dbg(3, dev, "g_mbus_config failed\n");
-+			goto err_pm_put;
-+		}
-+
-+		dev->active_data_lanes =
-+			(mbus_config.flags & V4L2_MBUS_CSI2_LANE_MASK) >>
-+					__ffs(V4L2_MBUS_CSI2_LANE_MASK);
-+		if (!dev->active_data_lanes)
-+			dev->active_data_lanes = dev->max_data_lanes;
-+	}
-+	if (dev->active_data_lanes > dev->max_data_lanes) {
-+		unicam_err(dev, "Device has requested %u data lanes, which is >%u configured in DT\n",
-+			   dev->active_data_lanes, dev->max_data_lanes);
-+		ret = -EINVAL;
-+		goto err_pm_put;
-+	}
-+
-+	unicam_dbg(1, dev, "Running with %u data lanes\n",
-+		   dev->active_data_lanes);
-+
-+	ret = clk_set_rate(dev->clock, 100 * 1000 * 1000);
-+	if (ret) {
-+		unicam_err(dev, "failed to set up clock\n");
-+		goto err_pm_put;
-+	}
-+
-+	ret = clk_prepare_enable(dev->clock);
-+	if (ret) {
-+		unicam_err(dev, "Failed to enable CSI clock: %d\n", ret);
-+		goto err_pm_put;
-+	}
-+	ret = v4l2_subdev_call(dev->sensor, core, s_power, 1);
-+	if (ret < 0 && ret != -ENOIOCTLCMD) {
-+		unicam_err(dev, "power on failed in subdev\n");
-+		goto err_clock_unprepare;
-+	}
-+	dev->streaming = 1;
-+
-+	unicam_start_rx(dev, addr);
-+
-+	ret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);
-+	if (ret < 0) {
-+		unicam_err(dev, "stream on failed in subdev\n");
-+		goto err_disable_unicam;
-+	}
-+
-+	return 0;
-+
-+err_disable_unicam:
-+	unicam_disable(dev);
-+	v4l2_subdev_call(dev->sensor, core, s_power, 0);
-+err_clock_unprepare:
-+	clk_disable_unprepare(dev->clock);
-+err_pm_put:
-+	unicam_runtime_put(dev);
-+err_release_buffers:
-+	list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
-+		list_del(&buf->list);
-+		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
-+	}
-+	if (dev->cur_frm != dev->next_frm)
-+		vb2_buffer_done(&dev->next_frm->vb.vb2_buf,
-+				VB2_BUF_STATE_QUEUED);
-+	vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
-+	dev->next_frm = NULL;
-+	dev->cur_frm = NULL;
-+
-+	return ret;
-+}
-+
-+static void unicam_stop_streaming(struct vb2_queue *vq)
-+{
-+	struct unicam_device *dev = vb2_get_drv_priv(vq);
-+	struct unicam_dmaqueue *dma_q = &dev->dma_queue;
-+	struct unicam_buffer *buf, *tmp;
-+	unsigned long flags;
-+
-+	if (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)
-+		unicam_err(dev, "stream off failed in subdev\n");
-+
-+	unicam_disable(dev);
-+
-+	/* Release all active buffers */
-+	spin_lock_irqsave(&dev->dma_queue_lock, flags);
-+	list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
-+		list_del(&buf->list);
-+		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
-+	}
-+
-+	if (dev->cur_frm == dev->next_frm) {
-+		vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
-+	} else {
-+		vb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
-+		vb2_buffer_done(&dev->next_frm->vb.vb2_buf,
-+				VB2_BUF_STATE_ERROR);
-+	}
-+	dev->cur_frm = NULL;
-+	dev->next_frm = NULL;
-+	spin_unlock_irqrestore(&dev->dma_queue_lock, flags);
-+
-+	if (v4l2_subdev_has_op(dev->sensor, core, s_power)) {
-+		if (v4l2_subdev_call(dev->sensor, core, s_power, 0) < 0)
-+			unicam_err(dev, "power off failed in subdev\n");
-+	}
-+
-+	clk_disable_unprepare(dev->clock);
-+	unicam_runtime_put(dev);
-+}
-+
-+static int unicam_enum_input(struct file *file, void *priv,
-+			     struct v4l2_input *inp)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	if (inp->index != 0)
-+		return -EINVAL;
-+
-+	inp->type = V4L2_INPUT_TYPE_CAMERA;
-+	if (v4l2_subdev_has_op(dev->sensor, video, s_dv_timings)) {
-+		inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
-+		inp->std = 0;
-+	} else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {
-+		inp->capabilities = V4L2_IN_CAP_STD;
-+		if (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)
-+					< 0)
-+			inp->std = V4L2_STD_ALL;
-+	} else {
-+		inp->capabilities = 0;
-+		inp->std = 0;
-+	}
-+	sprintf(inp->name, "Camera 0");
-+	return 0;
-+}
-+
-+static int unicam_g_input(struct file *file, void *priv, unsigned int *i)
-+{
-+	*i = 0;
-+
-+	return 0;
-+}
-+
-+static int unicam_s_input(struct file *file, void *priv, unsigned int i)
-+{
-+	/*
-+	 * FIXME: Ideally we would like to be able to query the source
-+	 * subdevice for information over the input connectors it supports,
-+	 * and map that through in to a call to video_ops->s_routing.
-+	 * There is no infrastructure support for defining that within
-+	 * devicetree at present. Until that is implemented we can't
-+	 * map a user physical connector number to s_routing input number.
-+	 */
-+	if (i > 0)
-+		return -EINVAL;
-+
-+	return 0;
-+}
-+
-+static int unicam_querystd(struct file *file, void *priv,
-+			   v4l2_std_id *std)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	return v4l2_subdev_call(dev->sensor, video, querystd, std);
-+}
-+
-+static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	return v4l2_subdev_call(dev->sensor, video, g_std, std);
-+}
-+
-+static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+	int ret;
-+	v4l2_std_id current_std;
-+
-+	ret = v4l2_subdev_call(dev->sensor, video, g_std, &current_std);
-+	if (ret)
-+		return ret;
-+
-+	if (std == current_std)
-+		return 0;
-+
-+	if (vb2_is_busy(&dev->buffer_queue))
-+		return -EBUSY;
-+
-+	ret = v4l2_subdev_call(dev->sensor, video, s_std, std);
-+
-+	/* Force recomputation of bytesperline */
-+	dev->v_fmt.fmt.pix.bytesperline = 0;
-+
-+	unicam_reset_format(dev);
-+
-+	return ret;
-+}
-+
-+static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	return v4l2_subdev_call(dev->sensor, pad, set_edid, edid);
-+}
-+
-+static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	return v4l2_subdev_call(dev->sensor, pad, get_edid, edid);
-+}
-+
-+static int unicam_g_dv_timings(struct file *file, void *priv,
-+			       struct v4l2_dv_timings *timings)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	return v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);
-+}
-+
-+static int unicam_s_dv_timings(struct file *file, void *priv,
-+			       struct v4l2_dv_timings *timings)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+	struct v4l2_dv_timings current_timings;
-+	int ret;
-+
-+	ret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,
-+			       &current_timings);
-+
-+	if (v4l2_match_dv_timings(timings, &current_timings, 0, false))
-+		return 0;
-+
-+	if (vb2_is_busy(&dev->buffer_queue))
-+		return -EBUSY;
-+
-+	ret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);
-+
-+	/* Force recomputation of bytesperline */
-+	dev->v_fmt.fmt.pix.bytesperline = 0;
-+
-+	unicam_reset_format(dev);
-+
-+	return ret;
-+}
-+
-+static int unicam_query_dv_timings(struct file *file, void *priv,
-+				   struct v4l2_dv_timings *timings)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	return v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);
-+}
-+
-+static int unicam_enum_dv_timings(struct file *file, void *priv,
-+				  struct v4l2_enum_dv_timings *timings)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	return v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);
-+}
-+
-+static int unicam_dv_timings_cap(struct file *file, void *priv,
-+				 struct v4l2_dv_timings_cap *cap)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+
-+	return v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);
-+}
-+
-+static int unicam_subscribe_event(struct v4l2_fh *fh,
-+				  const struct v4l2_event_subscription *sub)
-+{
-+	switch (sub->type) {
-+	case V4L2_EVENT_SOURCE_CHANGE:
-+		return v4l2_event_subscribe(fh, sub, 4, NULL);
-+	}
-+
-+	return v4l2_ctrl_subscribe_event(fh, sub);
-+}
-+
-+static int unicam_log_status(struct file *file, void *fh)
-+{
-+	struct unicam_device *dev = video_drvdata(file);
-+	struct unicam_cfg *cfg = &dev->cfg;
-+	u32 reg;
-+
-+	/* status for sub devices */
-+	v4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);
-+
-+	unicam_info(dev, "-----Receiver status-----\n");
-+	unicam_info(dev, "V4L2 width/height:   %ux%u\n",
-+		    dev->v_fmt.fmt.pix.width, dev->v_fmt.fmt.pix.height);
-+	unicam_info(dev, "Mediabus format:     %08x\n", dev->fmt->code);
-+	unicam_info(dev, "V4L2 format:         " V4L2_FOURCC_CONV "\n",
-+		    V4L2_FOURCC_CONV_ARGS(dev->v_fmt.fmt.pix.pixelformat));
-+	reg = reg_read(&dev->cfg, UNICAM_IPIPE);
-+	unicam_info(dev, "Unpacking/packing:   %u / %u\n",
-+		    get_field(reg, UNICAM_PUM_MASK),
-+		    get_field(reg, UNICAM_PPM_MASK));
-+	unicam_info(dev, "----Live data----\n");
-+	unicam_info(dev, "Programmed stride:   %4u\n",
-+		    reg_read(cfg, UNICAM_IBLS));
-+	unicam_info(dev, "Detected resolution: %ux%u\n",
-+		    reg_read(cfg, UNICAM_IHSTA),
-+		    reg_read(cfg, UNICAM_IVSTA));
-+	unicam_info(dev, "Write pointer:       %08x\n",
-+		    reg_read(cfg, UNICAM_IBWP));
-+
-+	return 0;
-+}
-+
-+static void unicam_notify(struct v4l2_subdev *sd,
-+			  unsigned int notification, void *arg)
-+{
-+	struct unicam_device *dev =
-+		container_of(sd->v4l2_dev, struct unicam_device, v4l2_dev);
-+
-+	switch (notification) {
-+	case V4L2_DEVICE_NOTIFY_EVENT:
-+		v4l2_event_queue(&dev->video_dev, arg);
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+static const struct vb2_ops unicam_video_qops = {
-+	.wait_prepare		= vb2_ops_wait_prepare,
-+	.wait_finish		= vb2_ops_wait_finish,
-+	.queue_setup		= unicam_queue_setup,
-+	.buf_prepare		= unicam_buffer_prepare,
-+	.buf_queue		= unicam_buffer_queue,
-+	.start_streaming	= unicam_start_streaming,
-+	.stop_streaming		= unicam_stop_streaming,
-+};
-+
-+/* unicam capture driver file operations */
-+static const struct v4l2_file_operations unicam_fops = {
-+	.owner		= THIS_MODULE,
-+	.open           = v4l2_fh_open,
-+	.release        = vb2_fop_release,
-+	.read		= vb2_fop_read,
-+	.poll		= vb2_fop_poll,
-+	.unlocked_ioctl	= video_ioctl2,
-+	.mmap		= vb2_fop_mmap,
-+};
-+
-+/* unicam capture ioctl operations */
-+static const struct v4l2_ioctl_ops unicam_ioctl_ops = {
-+	.vidioc_querycap		= unicam_querycap,
-+	.vidioc_enum_fmt_vid_cap	= unicam_enum_fmt_vid_cap,
-+	.vidioc_g_fmt_vid_cap		= unicam_g_fmt_vid_cap,
-+	.vidioc_s_fmt_vid_cap		= unicam_s_fmt_vid_cap,
-+	.vidioc_try_fmt_vid_cap		= unicam_try_fmt_vid_cap,
-+
-+	.vidioc_enum_input		= unicam_enum_input,
-+	.vidioc_g_input			= unicam_g_input,
-+	.vidioc_s_input			= unicam_s_input,
-+
-+	.vidioc_querystd		= unicam_querystd,
-+	.vidioc_s_std			= unicam_s_std,
-+	.vidioc_g_std			= unicam_g_std,
-+
-+	.vidioc_g_edid			= unicam_g_edid,
-+	.vidioc_s_edid			= unicam_s_edid,
-+
-+	.vidioc_s_dv_timings		= unicam_s_dv_timings,
-+	.vidioc_g_dv_timings		= unicam_g_dv_timings,
-+	.vidioc_query_dv_timings	= unicam_query_dv_timings,
-+	.vidioc_enum_dv_timings		= unicam_enum_dv_timings,
-+	.vidioc_dv_timings_cap		= unicam_dv_timings_cap,
-+
-+	.vidioc_reqbufs			= vb2_ioctl_reqbufs,
-+	.vidioc_create_bufs		= vb2_ioctl_create_bufs,
-+	.vidioc_prepare_buf		= vb2_ioctl_prepare_buf,
-+	.vidioc_querybuf		= vb2_ioctl_querybuf,
-+	.vidioc_qbuf			= vb2_ioctl_qbuf,
-+	.vidioc_dqbuf			= vb2_ioctl_dqbuf,
-+	.vidioc_expbuf			= vb2_ioctl_expbuf,
-+	.vidioc_streamon		= vb2_ioctl_streamon,
-+	.vidioc_streamoff		= vb2_ioctl_streamoff,
-+
-+	.vidioc_log_status		= unicam_log_status,
-+	.vidioc_subscribe_event		= unicam_subscribe_event,
-+	.vidioc_unsubscribe_event	= v4l2_event_unsubscribe,
-+};
-+
-+/*
-+ * Adds an entry to the active_fmts array
-+ * Returns non-zero if attempting to write off the end of the array.
-+ */
-+static int unicam_add_active_format(struct unicam_device *unicam,
-+				    const struct unicam_fmt *fmt)
-+{
-+	//Ensure we don't run off the end of the array.
-+	if (unicam->num_active_fmt >= MAX_POSSIBLE_PIX_FMTS)
-+		return 1;
-+
-+	unicam->active_fmts[unicam->num_active_fmt] = *fmt;
-+	unicam_dbg(2, unicam,
-+		   "matched fourcc: " V4L2_FOURCC_CONV ": code: %04x idx: %d\n",
-+		   V4L2_FOURCC_CONV_ARGS(fmt->fourcc),
-+		   fmt->code, unicam->num_active_fmt);
-+	unicam->num_active_fmt++;
-+
-+	return 0;
-+}
-+
-+static int
-+unicam_async_bound(struct v4l2_async_notifier *notifier,
-+		   struct v4l2_subdev *subdev,
-+		   struct v4l2_async_subdev *asd)
-+{
-+	struct unicam_device *unicam = container_of(notifier->v4l2_dev,
-+					       struct unicam_device, v4l2_dev);
-+	struct v4l2_subdev_mbus_code_enum mbus_code;
-+	int ret = 0;
-+	int j;
-+
-+	if (unicam->sensor) {
-+		unicam_info(unicam, "Rejecting subdev %s (Already set!!)",
-+			    subdev->name);
-+		return 0;
-+	}
-+
-+	unicam->sensor = subdev;
-+	unicam_dbg(1, unicam, "Using sensor %s for capture\n", subdev->name);
-+
-+	/* Enumerate sub device formats and enable all matching local formats */
-+	unicam->num_active_fmt = 0;
-+	unicam_dbg(2, unicam, "Get supported formats...\n");
-+	for (j = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++j) {
-+		const struct unicam_fmt *fmt = NULL;
-+		int k;
-+
-+		memset(&mbus_code, 0, sizeof(mbus_code));
-+		mbus_code.index = j;
-+		ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
-+				       NULL, &mbus_code);
-+		if (ret < 0) {
-+			unicam_dbg(2, unicam,
-+				   "subdev->enum_mbus_code idx %d returned %d - continue\n",
-+				   j, ret);
-+			continue;
-+		}
-+
-+		unicam_dbg(2, unicam, "subdev %s: code: %04x idx: %d\n",
-+			   subdev->name, mbus_code.code, j);
-+
-+		for (k = 0; k < ARRAY_SIZE(formats); k++) {
-+			if (mbus_code.code == formats[k].code) {
-+				fmt = &formats[k];
-+				break;
-+			}
-+		}
-+		unicam_dbg(2, unicam, "fmt %04x returned as %p, V4L2 FOURCC %04x, csi_dt %02X\n",
-+			   mbus_code.code, fmt, fmt ? fmt->fourcc : 0,
-+			   fmt ? fmt->csi_dt : 0);
-+		if (fmt) {
-+			if (unicam_add_active_format(unicam, fmt)) {
-+				unicam_dbg(1, unicam, "Active fmt list truncated\n");
-+				break;
-+			}
-+		}
-+	}
-+	unicam_dbg(2, unicam,
-+		   "Done all formats\n");
-+	dump_active_formats(unicam);
-+
-+	return 0;
-+}
-+
-+static int unicam_probe_complete(struct unicam_device *unicam)
-+{
-+	struct video_device *vdev;
-+	struct vb2_queue *q;
-+	struct v4l2_mbus_framefmt mbus_fmt = {0};
-+	const struct unicam_fmt *fmt;
-+	int ret;
-+
-+	v4l2_set_subdev_hostdata(unicam->sensor, unicam);
-+
-+	unicam->v4l2_dev.notify = unicam_notify;
-+
-+	unicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);
-+	if (!unicam->sensor_config)
-+		return -ENOMEM;
-+
-+	ret = __subdev_get_format(unicam, &mbus_fmt);
-+	if (ret) {
-+		unicam_err(unicam, "Failed to get_format - ret %d\n", ret);
-+		return ret;
-+	}
-+
-+	fmt = find_format_by_code(unicam, mbus_fmt.code);
-+	if (!fmt) {
-+		/* Default image format not valid. Choose first active fmt. */
-+		fmt = &unicam->active_fmts[0];
-+		mbus_fmt.code = fmt->code;
-+		ret = __subdev_set_format(unicam, &mbus_fmt);
-+		if (ret)
-+			return -EINVAL;
-+	}
-+	if (mbus_fmt.field != V4L2_FIELD_NONE) {
-+		/* Interlaced not supported - disable it now. */
-+		mbus_fmt.field = V4L2_FIELD_NONE;
-+		ret = __subdev_set_format(unicam, &mbus_fmt);
-+		if (ret)
-+			return -EINVAL;
-+	}
-+
-+	unicam->fmt = fmt;
-+	unicam->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
-+
-+	/* Read current subdev format */
-+	unicam_reset_format(unicam);
-+
-+	if (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
-+		v4l2_std_id tvnorms;
-+
-+		if (WARN_ON(!v4l2_subdev_has_op(unicam->sensor, video,
-+						g_tvnorms)))
-+			/*
-+			 * Subdevice should not advertise s_std but not
-+			 * g_tvnorms
-+			 */
-+			return -EINVAL;
-+
-+		ret = v4l2_subdev_call(unicam->sensor, video,
-+				       g_tvnorms, &tvnorms);
-+		if (WARN_ON(ret))
-+			return -EINVAL;
-+		unicam->video_dev.tvnorms |= tvnorms;
-+	}
-+
-+	spin_lock_init(&unicam->dma_queue_lock);
-+	mutex_init(&unicam->lock);
-+
-+	/* Add controls from the subdevice */
-+	ret = v4l2_ctrl_add_handler(&unicam->ctrl_handler,
-+				    unicam->sensor->ctrl_handler, NULL);
-+	if (ret < 0)
-+		return ret;
-+
-+	q = &unicam->buffer_queue;
-+	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
-+	q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
-+	q->drv_priv = unicam;
-+	q->ops = &unicam_video_qops;
-+	q->mem_ops = &vb2_dma_contig_memops;
-+	q->buf_struct_size = sizeof(struct unicam_buffer);
-+	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
-+	q->lock = &unicam->lock;
-+	q->min_buffers_needed = 2;
-+	q->dev = &unicam->pdev->dev;
-+
-+	ret = vb2_queue_init(q);
-+	if (ret) {
-+		unicam_err(unicam, "vb2_queue_init() failed\n");
-+		return ret;
-+	}
-+
-+	INIT_LIST_HEAD(&unicam->dma_queue.active);
-+
-+	vdev = &unicam->video_dev;
-+	strlcpy(vdev->name, UNICAM_MODULE_NAME, sizeof(vdev->name));
-+	vdev->release = video_device_release_empty;
-+	vdev->fops = &unicam_fops;
-+	vdev->ioctl_ops = &unicam_ioctl_ops;
-+	vdev->v4l2_dev = &unicam->v4l2_dev;
-+	vdev->vfl_dir = VFL_DIR_RX;
-+	vdev->queue = q;
-+	vdev->lock = &unicam->lock;
-+	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
-+			    V4L2_CAP_READWRITE;
-+
-+	/* If the source has no controls then remove our ctrl handler. */
-+	if (list_empty(&unicam->ctrl_handler.ctrls))
-+		unicam->v4l2_dev.ctrl_handler = NULL;
-+
-+	video_set_drvdata(vdev, unicam);
-+	ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
-+	if (ret) {
-+		unicam_err(unicam, "Unable to register video device.\n");
-+		return ret;
-+	}
-+
-+	if (!v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_STD);
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_STD);
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUMSTD);
-+	}
-+	if (!v4l2_subdev_has_op(unicam->sensor, video, querystd))
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERYSTD);
-+	if (!v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_EDID);
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_EDID);
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_DV_TIMINGS_CAP);
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_DV_TIMINGS);
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_DV_TIMINGS);
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_DV_TIMINGS);
-+		v4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERY_DV_TIMINGS);
-+	}
-+
-+	ret = v4l2_device_register_subdev_nodes(&unicam->v4l2_dev);
-+	if (ret) {
-+		unicam_err(unicam,
-+			   "Unable to register subdev nodes.\n");
-+		video_unregister_device(&unicam->video_dev);
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
-+static int unicam_async_complete(struct v4l2_async_notifier *notifier)
-+{
-+	struct unicam_device *unicam = container_of(notifier->v4l2_dev,
-+					struct unicam_device, v4l2_dev);
-+
-+	return unicam_probe_complete(unicam);
-+}
-+
-+static const struct v4l2_async_notifier_operations unicam_async_ops = {
-+	.bound = unicam_async_bound,
-+	.complete = unicam_async_complete,
-+};
-+
-+static int of_unicam_connect_subdevs(struct unicam_device *dev)
-+{
-+	struct platform_device *pdev = dev->pdev;
-+	struct device_node *parent, *ep_node = NULL, *remote_ep = NULL,
-+			*sensor_node = NULL;
-+	struct v4l2_fwnode_endpoint *ep;
-+	struct v4l2_async_subdev *asd;
-+	struct v4l2_async_subdev **subdevs = NULL;
-+	unsigned int peripheral_data_lanes;
-+	int ret = -EINVAL;
-+	unsigned int lane;
-+
-+	parent = pdev->dev.of_node;
-+
-+	asd = &dev->asd;
-+	ep = &dev->endpoint;
-+
-+	ep_node = of_graph_get_next_endpoint(parent, NULL);
-+	if (!ep_node) {
-+		unicam_dbg(3, dev, "can't get next endpoint\n");
-+		goto cleanup_exit;
-+	}
-+
-+	unicam_dbg(3, dev, "ep_node is %s\n", ep_node->name);
-+
-+	v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), ep);
-+
-+	for (lane = 0; lane < ep->bus.mipi_csi2.num_data_lanes; lane++) {
-+		if (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {
-+			unicam_err(dev, "Local endpoint - data lane reordering not supported\n");
-+			goto cleanup_exit;
-+		}
-+	}
-+
-+	peripheral_data_lanes = ep->bus.mipi_csi2.num_data_lanes;
-+
-+	sensor_node = of_graph_get_remote_port_parent(ep_node);
-+	if (!sensor_node) {
-+		unicam_dbg(3, dev, "can't get remote parent\n");
-+		goto cleanup_exit;
-+	}
-+	unicam_dbg(3, dev, "sensor_node is %s\n", sensor_node->name);
-+	asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
-+	asd->match.fwnode.fwnode = of_fwnode_handle(sensor_node);
-+
-+	remote_ep = of_graph_get_remote_endpoint(ep_node);
-+	if (!remote_ep) {
-+		unicam_dbg(3, dev, "can't get remote-endpoint\n");
-+		goto cleanup_exit;
-+	}
-+	unicam_dbg(3, dev, "remote_ep is %s\n", remote_ep->name);
-+	v4l2_fwnode_endpoint_parse(of_fwnode_handle(remote_ep), ep);
-+	unicam_dbg(3, dev, "parsed remote_ep to endpoint. nr_of_link_frequencies %u, bus_type %u\n",
-+		   ep->nr_of_link_frequencies, ep->bus_type);
-+
-+	switch (ep->bus_type) {
-+	case V4L2_MBUS_CSI2:
-+		if (ep->bus.mipi_csi2.num_data_lanes >
-+				peripheral_data_lanes) {
-+			unicam_err(dev, "Subdevice %s wants too many data lanes (%u > %u)\n",
-+				   sensor_node->name,
-+				   ep->bus.mipi_csi2.num_data_lanes,
-+				   peripheral_data_lanes);
-+			goto cleanup_exit;
-+		}
-+		for (lane = 0;
-+		     lane < ep->bus.mipi_csi2.num_data_lanes;
-+		     lane++) {
-+			if (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {
-+				unicam_err(dev, "Subdevice %s - incompatible data lane config\n",
-+					   sensor_node->name);
-+				goto cleanup_exit;
-+			}
-+		}
-+		dev->max_data_lanes = ep->bus.mipi_csi2.num_data_lanes;
-+		dev->bus_flags = ep->bus.mipi_csi2.flags;
-+		break;
-+	case V4L2_MBUS_CCP2:
-+		if (ep->bus.mipi_csi1.clock_lane != 0 ||
-+		    ep->bus.mipi_csi1.data_lane != 1) {
-+			unicam_err(dev, "Subdevice %s incompatible lane config\n",
-+				   sensor_node->name);
-+			goto cleanup_exit;
-+		}
-+		dev->max_data_lanes = 1;
-+		dev->bus_flags = ep->bus.mipi_csi1.strobe;
-+		break;
-+	default:
-+		/* Unsupported bus type */
-+		unicam_err(dev, "sub-device %s is not a CSI2 or CCP2 device %d\n",
-+			   sensor_node->name, ep->bus_type);
-+		goto cleanup_exit;
-+	}
-+
-+	/* Store bus type - CSI2 or CCP2 */
-+	dev->bus_type = ep->bus_type;
-+	unicam_dbg(3, dev, "bus_type is %d\n", dev->bus_type);
-+
-+	/* Store Virtual Channel number */
-+	dev->virtual_channel = ep->base.id;
-+
-+	unicam_dbg(3, dev, "v4l2-endpoint: %s\n",
-+		   dev->bus_type == V4L2_MBUS_CSI2 ? "CSI2" : "CCP2");
-+	unicam_dbg(3, dev, "Virtual Channel=%d\n", dev->virtual_channel);
-+	if (dev->bus_type == V4L2_MBUS_CSI2)
-+		unicam_dbg(3, dev, "flags=0x%08x\n", ep->bus.mipi_csi2.flags);
-+	unicam_dbg(3, dev, "num_data_lanes=%d\n", dev->max_data_lanes);
-+
-+	unicam_dbg(1, dev, "found sub-device %s\n", sensor_node->name);
-+
-+	subdevs = devm_kzalloc(&dev->pdev->dev, sizeof(*subdevs), GFP_KERNEL);
-+	if (!subdevs) {
-+		ret = -ENOMEM;
-+		goto cleanup_exit;
-+	}
-+	subdevs[0] = asd;
-+	dev->notifier.subdevs = subdevs;
-+	dev->notifier.num_subdevs = 1;
-+	dev->notifier.ops = &unicam_async_ops;
-+	ret = v4l2_async_notifier_register(&dev->v4l2_dev,
-+					   &dev->notifier);
-+	if (ret) {
-+		unicam_err(dev, "Error registering async notifier - ret %d\n",
-+			   ret);
-+		ret = -EINVAL;
-+	}
-+
-+cleanup_exit:
-+	if (remote_ep)
-+		of_node_put(remote_ep);
-+	if (sensor_node)
-+		of_node_put(sensor_node);
-+	if (ep_node)
-+		of_node_put(ep_node);
-+
-+	return ret;
-+}
-+
-+static int unicam_probe(struct platform_device *pdev)
-+{
-+	struct unicam_cfg *unicam_cfg;
-+	struct unicam_device *unicam;
-+	struct v4l2_ctrl_handler *hdl;
-+	struct resource	*res;
-+	int ret;
-+
-+	unicam = devm_kzalloc(&pdev->dev, sizeof(*unicam), GFP_KERNEL);
-+	if (!unicam)
-+		return -ENOMEM;
-+
-+	unicam->pdev = pdev;
-+	unicam_cfg = &unicam->cfg;
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	unicam_cfg->base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(unicam_cfg->base)) {
-+		unicam_err(unicam, "Failed to get main io block\n");
-+		return PTR_ERR(unicam_cfg->base);
-+	}
-+
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	unicam_cfg->clk_gate_base = devm_ioremap_resource(&pdev->dev, res);
-+	if (IS_ERR(unicam_cfg->clk_gate_base)) {
-+		unicam_err(unicam, "Failed to get 2nd io block\n");
-+		return PTR_ERR(unicam_cfg->clk_gate_base);
-+	}
-+
-+	unicam->clock = devm_clk_get(&pdev->dev, "lp");
-+	if (IS_ERR(unicam->clock)) {
-+		unicam_err(unicam, "Failed to get clock\n");
-+		return PTR_ERR(unicam->clock);
-+	}
-+
-+	ret = platform_get_irq(pdev, 0);
-+	if (ret <= 0) {
-+		dev_err(&pdev->dev, "No IRQ resource\n");
-+		return -ENODEV;
-+	}
-+
-+	ret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,
-+			       "unicam_capture0", unicam);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Unable to request interrupt\n");
-+		return -EINVAL;
-+	}
-+
-+	ret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);
-+	if (ret) {
-+		unicam_err(unicam,
-+			   "Unable to register v4l2 device.\n");
-+		return ret;
-+	}
-+
-+	/* Reserve space for the controls */
-+	hdl = &unicam->ctrl_handler;
-+	ret = v4l2_ctrl_handler_init(hdl, 16);
-+	if (ret < 0)
-+		goto probe_out_v4l2_unregister;
-+	unicam->v4l2_dev.ctrl_handler = hdl;
-+
-+	/* set the driver data in platform device */
-+	platform_set_drvdata(pdev, unicam);
-+
-+	ret = of_unicam_connect_subdevs(unicam);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to connect subdevs\n");
-+		goto free_hdl;
-+	}
-+
-+	/* Enable the block power domain */
-+	pm_runtime_enable(&pdev->dev);
-+
-+	return 0;
-+
-+free_hdl:
-+	v4l2_ctrl_handler_free(hdl);
-+probe_out_v4l2_unregister:
-+	v4l2_device_unregister(&unicam->v4l2_dev);
-+	return ret;
-+}
-+
-+static int unicam_remove(struct platform_device *pdev)
-+{
-+	struct unicam_device *unicam = platform_get_drvdata(pdev);
-+
-+	unicam_dbg(2, unicam, "%s\n", __func__);
-+
-+	pm_runtime_disable(&pdev->dev);
-+
-+	v4l2_async_notifier_unregister(&unicam->notifier);
-+	v4l2_ctrl_handler_free(&unicam->ctrl_handler);
-+	v4l2_device_unregister(&unicam->v4l2_dev);
-+	video_unregister_device(&unicam->video_dev);
-+	if (unicam->sensor_config)
-+		v4l2_subdev_free_pad_config(unicam->sensor_config);
-+
-+	return 0;
-+}
-+
-+static const struct of_device_id unicam_of_match[] = {
-+	{ .compatible = "brcm,bcm2835-unicam", },
-+	{ /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, unicam_of_match);
-+
-+static struct platform_driver unicam_driver = {
-+	.probe		= unicam_probe,
-+	.remove		= unicam_remove,
-+	.driver = {
-+		.name	= UNICAM_MODULE_NAME,
-+		.of_match_table = of_match_ptr(unicam_of_match),
-+	},
-+};
-+
-+module_platform_driver(unicam_driver);
-+
-+MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.org>");
-+MODULE_DESCRIPTION("BCM2835 Unicam driver");
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION(UNICAM_VERSION);
---- /dev/null
-+++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h
-@@ -0,0 +1,264 @@
-+/*
-+ * Copyright (C) 2017 Raspberry Pi Trading.
-+ * Dave Stevenson <dave.stevenson@raspberrypi.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
-+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-+ * SOFTWARE.
-+ */
-+
-+#ifndef VC4_REGS_UNICAM_H
-+#define VC4_REGS_UNICAM_H
-+
-+/*
-+ * The following values are taken from files found within the code drop
-+ * made by Broadcom for the BCM21553 Graphics Driver, predominantly in
-+ * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.
-+ * They have been modified to be only the register offset.
-+ */
-+#define UNICAM_CTRL	0x000
-+#define UNICAM_STA	0x004
-+#define UNICAM_ANA	0x008
-+#define UNICAM_PRI	0x00c
-+#define UNICAM_CLK	0x010
-+#define UNICAM_CLT	0x014
-+#define UNICAM_DAT0	0x018
-+#define UNICAM_DAT1	0x01c
-+#define UNICAM_DAT2	0x020
-+#define UNICAM_DAT3	0x024
-+#define UNICAM_DLT	0x028
-+#define UNICAM_CMP0	0x02c
-+#define UNICAM_CMP1	0x030
-+#define UNICAM_CAP0	0x034
-+#define UNICAM_CAP1	0x038
-+#define UNICAM_ICTL	0x100
-+#define UNICAM_ISTA	0x104
-+#define UNICAM_IDI0	0x108
-+#define UNICAM_IPIPE	0x10c
-+#define UNICAM_IBSA0	0x110
-+#define UNICAM_IBEA0	0x114
-+#define UNICAM_IBLS	0x118
-+#define UNICAM_IBWP	0x11c
-+#define UNICAM_IHWIN	0x120
-+#define UNICAM_IHSTA	0x124
-+#define UNICAM_IVWIN	0x128
-+#define UNICAM_IVSTA	0x12c
-+#define UNICAM_ICC	0x130
-+#define UNICAM_ICS	0x134
-+#define UNICAM_IDC	0x138
-+#define UNICAM_IDPO	0x13c
-+#define UNICAM_IDCA	0x140
-+#define UNICAM_IDCD	0x144
-+#define UNICAM_IDS	0x148
-+#define UNICAM_DCS	0x200
-+#define UNICAM_DBSA0	0x204
-+#define UNICAM_DBEA0	0x208
-+#define UNICAM_DBWP	0x20c
-+#define UNICAM_DBCTL	0x300
-+#define UNICAM_IBSA1	0x304
-+#define UNICAM_IBEA1	0x308
-+#define UNICAM_IDI1	0x30c
-+#define UNICAM_DBSA1	0x310
-+#define UNICAM_DBEA1	0x314
-+#define UNICAM_MISC	0x400
-+
-+/*
-+ * The following bitmasks are from the kernel released by Broadcom
-+ * for Android - https://android.googlesource.com/kernel/bcm/
-+ * The Rhea, Hawaii, and Java chips all contain the same VideoCore4
-+ * Unicam block as BCM2835, as defined in eg
-+ * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.
-+ * Values reworked to use the kernel BIT and GENMASK macros.
-+ *
-+ * Some of the bit mnenomics have been amended to match the datasheet.
-+ */
-+/* UNICAM_CTRL Register */
-+#define UNICAM_CPE		BIT(0)
-+#define UNICAM_MEM		BIT(1)
-+#define UNICAM_CPR		BIT(2)
-+#define UNICAM_CPM_MASK		GENMASK(3, 3)
-+#define UNICAM_CPM_CSI2		0
-+#define UNICAM_CPM_CCP2		1
-+#define UNICAM_SOE		BIT(4)
-+#define UNICAM_DCM_MASK		GENMASK(5, 5)
-+#define UNICAM_DCM_STROBE	0
-+#define UNICAM_DCM_DATA		1
-+#define UNICAM_SLS		BIT(6)
-+#define UNICAM_PFT_MASK		GENMASK(11, 8)
-+#define UNICAM_OET_MASK		GENMASK(20, 12)
-+
-+/* UNICAM_STA Register */
-+#define UNICAM_SYN		BIT(0)
-+#define UNICAM_CS		BIT(1)
-+#define UNICAM_SBE		BIT(2)
-+#define UNICAM_PBE		BIT(3)
-+#define UNICAM_HOE		BIT(4)
-+#define UNICAM_PLE		BIT(5)
-+#define UNICAM_SSC		BIT(6)
-+#define UNICAM_CRCE		BIT(7)
-+#define UNICAM_OES		BIT(8)
-+#define UNICAM_IFO		BIT(9)
-+#define UNICAM_OFO		BIT(10)
-+#define UNICAM_BFO		BIT(11)
-+#define UNICAM_DL		BIT(12)
-+#define UNICAM_PS		BIT(13)
-+#define UNICAM_IS		BIT(14)
-+#define UNICAM_PI0		BIT(15)
-+#define UNICAM_PI1		BIT(16)
-+#define UNICAM_FSI_S		BIT(17)
-+#define UNICAM_FEI_S		BIT(18)
-+#define UNICAM_LCI_S		BIT(19)
-+#define UNICAM_BUF0_RDY		BIT(20)
-+#define UNICAM_BUF0_NO		BIT(21)
-+#define UNICAM_BUF1_RDY		BIT(22)
-+#define UNICAM_BUF1_NO		BIT(23)
-+#define UNICAM_DI		BIT(24)
-+
-+#define UNICAM_STA_MASK_ALL \
-+		(UNICAM_DL + \
-+		UNICAM_SBE + \
-+		UNICAM_PBE + \
-+		UNICAM_HOE + \
-+		UNICAM_PLE + \
-+		UNICAM_SSC + \
-+		UNICAM_CRCE + \
-+		UNICAM_IFO + \
-+		UNICAM_OFO + \
-+		UNICAM_PS + \
-+		UNICAM_PI0 + \
-+		UNICAM_PI1)
-+
-+/* UNICAM_ANA Register */
-+#define UNICAM_APD		BIT(0)
-+#define UNICAM_BPD		BIT(1)
-+#define UNICAM_AR		BIT(2)
-+#define UNICAM_DDL		BIT(3)
-+#define UNICAM_CTATADJ_MASK	GENMASK(7, 4)
-+#define UNICAM_PTATADJ_MASK	GENMASK(11, 8)
-+
-+/* UNICAM_PRI Register */
-+#define UNICAM_PE		BIT(0)
-+#define UNICAM_PT_MASK		GENMASK(2, 1)
-+#define UNICAM_NP_MASK		GENMASK(7, 4)
-+#define UNICAM_PP_MASK		GENMASK(11, 8)
-+#define UNICAM_BS_MASK		GENMASK(15, 12)
-+#define UNICAM_BL_MASK		GENMASK(17, 16)
-+
-+/* UNICAM_CLK Register */
-+#define UNICAM_CLE		BIT(0)
-+#define UNICAM_CLPD		BIT(1)
-+#define UNICAM_CLLPE		BIT(2)
-+#define UNICAM_CLHSE		BIT(3)
-+#define UNICAM_CLTRE		BIT(4)
-+#define UNICAM_CLAC_MASK	GENMASK(8, 5)
-+#define UNICAM_CLSTE		BIT(29)
-+
-+/* UNICAM_CLT Register */
-+#define UNICAM_CLT1_MASK	GENMASK(7, 0)
-+#define UNICAM_CLT2_MASK	GENMASK(15, 8)
-+
-+/* UNICAM_DATn Registers */
-+#define UNICAM_DLE		BIT(0)
-+#define UNICAM_DLPD		BIT(1)
-+#define UNICAM_DLLPE		BIT(2)
-+#define UNICAM_DLHSE		BIT(3)
-+#define UNICAM_DLTRE		BIT(4)
-+#define UNICAM_DLSM		BIT(5)
-+#define UNICAM_DLFO		BIT(28)
-+#define UNICAM_DLSTE		BIT(29)
-+
-+#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)
-+
-+/* UNICAM_DLT Register */
-+#define UNICAM_DLT1_MASK	GENMASK(7, 0)
-+#define UNICAM_DLT2_MASK	GENMASK(15, 8)
-+#define UNICAM_DLT3_MASK	GENMASK(23, 16)
-+
-+/* UNICAM_ICTL Register */
-+#define UNICAM_FSIE		BIT(0)
-+#define UNICAM_FEIE		BIT(1)
-+#define UNICAM_IBOB		BIT(2)
-+#define UNICAM_FCM		BIT(3)
-+#define UNICAM_TFC		BIT(4)
-+#define UNICAM_LIP_MASK		GENMASK(6, 5)
-+#define UNICAM_LCIE_MASK	GENMASK(28, 16)
-+
-+/* UNICAM_IDI0/1 Register */
-+#define UNICAM_ID0_MASK		GENMASK(7, 0)
-+#define UNICAM_ID1_MASK		GENMASK(15, 8)
-+#define UNICAM_ID2_MASK		GENMASK(23, 16)
-+#define UNICAM_ID3_MASK		GENMASK(31, 24)
-+
-+/* UNICAM_ISTA Register */
-+#define UNICAM_FSI		BIT(0)
-+#define UNICAM_FEI		BIT(1)
-+#define UNICAM_LCI		BIT(2)
-+
-+#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)
-+
-+/* UNICAM_IPIPE Register */
-+#define UNICAM_PUM_MASK		GENMASK(2, 0)
-+		/* Unpacking modes */
-+		#define UNICAM_PUM_NONE		0
-+		#define UNICAM_PUM_UNPACK6	1
-+		#define UNICAM_PUM_UNPACK7	2
-+		#define UNICAM_PUM_UNPACK8	3
-+		#define UNICAM_PUM_UNPACK10	4
-+		#define UNICAM_PUM_UNPACK12	5
-+		#define UNICAM_PUM_UNPACK14	6
-+		#define UNICAM_PUM_UNPACK16	7
-+#define UNICAM_DDM_MASK		GENMASK(6, 3)
-+#define UNICAM_PPM_MASK		GENMASK(9, 7)
-+		/* Packing modes */
-+		#define UNICAM_PPM_NONE		0
-+		#define UNICAM_PPM_PACK8	1
-+		#define UNICAM_PPM_PACK10	2
-+		#define UNICAM_PPM_PACK12	3
-+		#define UNICAM_PPM_PACK14	4
-+		#define UNICAM_PPM_PACK16	5
-+#define UNICAM_DEM_MASK		GENMASK(11, 10)
-+#define UNICAM_DEBL_MASK	GENMASK(14, 12)
-+#define UNICAM_ICM_MASK		GENMASK(16, 15)
-+#define UNICAM_IDM_MASK		GENMASK(17, 17)
-+
-+/* UNICAM_ICC Register */
-+#define UNICAM_ICFL_MASK	GENMASK(4, 0)
-+#define UNICAM_ICFH_MASK	GENMASK(9, 5)
-+#define UNICAM_ICST_MASK	GENMASK(12, 10)
-+#define UNICAM_ICLT_MASK	GENMASK(15, 13)
-+#define UNICAM_ICLL_MASK	GENMASK(31, 16)
-+
-+/* UNICAM_DCS Register */
-+#define UNICAM_DIE		BIT(0)
-+#define UNICAM_DIM		BIT(1)
-+#define UNICAM_DBOB		BIT(3)
-+#define UNICAM_FDE		BIT(4)
-+#define UNICAM_LDP		BIT(5)
-+#define UNICAM_EDL_MASK		GENMASK(15, 8)
-+
-+/* UNICAM_DBCTL Register */
-+#define UNICAM_DBEN		BIT(0)
-+#define UNICAM_BUF0_IE		BIT(1)
-+#define UNICAM_BUF1_IE		BIT(2)
-+
-+/* UNICAM_CMP[0,1] register */
-+#define UNICAM_PCE		BIT(31)
-+#define UNICAM_GI		BIT(9)
-+#define UNICAM_CPH		BIT(8)
-+#define UNICAM_PCVC_MASK	GENMASK(7, 6)
-+#define UNICAM_PCDT_MASK	GENMASK(5, 0)
-+
-+/* UNICAM_MISC register */
-+#define UNICAM_FL0		BIT(6)
-+#define UNICAM_FL1		BIT(9)
-+
-+#endif
diff --git a/target/linux/brcm2708/patches-4.14/950-0333-bcm2835-unicam-Revert-changes-for-notifier-fn-ptrs.patch b/target/linux/brcm2708/patches-4.14/950-0333-bcm2835-unicam-Revert-changes-for-notifier-fn-ptrs.patch
deleted file mode 100644
index d4a31868a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0333-bcm2835-unicam-Revert-changes-for-notifier-fn-ptrs.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From b0f01086e440516c03ce61e5597b9a0d2df0a1c0 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 1 Nov 2017 16:17:43 +0000
-Subject: [PATCH 333/454] bcm2835-unicam: Revert changes for notifier fn ptrs
-
-4.15 is using const function pointers for the notifier
-functions. Those changes don't cherry-pick easily, so
-revert those mods in this driver.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/platform/bcm2835/bcm2835-unicam.c | 8 ++------
- 1 file changed, 2 insertions(+), 6 deletions(-)
-
---- a/drivers/media/platform/bcm2835/bcm2835-unicam.c
-+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
-@@ -1833,11 +1833,6 @@ static int unicam_async_complete(struct
- 	return unicam_probe_complete(unicam);
- }
- 
--static const struct v4l2_async_notifier_operations unicam_async_ops = {
--	.bound = unicam_async_bound,
--	.complete = unicam_async_complete,
--};
--
- static int of_unicam_connect_subdevs(struct unicam_device *dev)
- {
- 	struct platform_device *pdev = dev->pdev;
-@@ -1956,7 +1951,8 @@ static int of_unicam_connect_subdevs(str
- 	subdevs[0] = asd;
- 	dev->notifier.subdevs = subdevs;
- 	dev->notifier.num_subdevs = 1;
--	dev->notifier.ops = &unicam_async_ops;
-+	dev->notifier.bound = unicam_async_bound;
-+	dev->notifier.complete = unicam_async_complete;
- 	ret = v4l2_async_notifier_register(&dev->v4l2_dev,
- 					   &dev->notifier);
- 	if (ret) {
diff --git a/target/linux/brcm2708/patches-4.14/950-0334-MAINTAINERS-Add-entry-for-BCM2835-camera-driver.patch b/target/linux/brcm2708/patches-4.14/950-0334-MAINTAINERS-Add-entry-for-BCM2835-camera-driver.patch
deleted file mode 100644
index e35467ec7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0334-MAINTAINERS-Add-entry-for-BCM2835-camera-driver.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From e2e4a7f690ba90dc7dd7bd885530dd7873e8d740 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 11 Sep 2017 15:42:40 +0100
-Subject: [PATCH 334/454] MAINTAINERS: Add entry for BCM2835 camera driver
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- MAINTAINERS | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -2765,6 +2765,13 @@ S:	Maintained
- N:	bcm2835
- F:	drivers/staging/vc04_services
- 
-+BROADCOM BCM2835 CAMERA DRIVER
-+M:	Dave Stevenson <dave.stevenson@raspberrypi.org>
-+L:	linux-media@vger.kernel.org
-+S:	Maintained
-+F:	drivers/media/platform/bcm2835/
-+F:	Documentation/devicetree/bindings/media/bcm2835-unicam.txt
-+
- BROADCOM BCM47XX MIPS ARCHITECTURE
- M:	Hauke Mehrtens <hauke@hauke-m.de>
- M:	Rafał Miłecki <zajec5@gmail.com>
diff --git a/target/linux/brcm2708/patches-4.14/950-0335-defconfig-Enable-Unicam-driver-and-various-sources-o.patch b/target/linux/brcm2708/patches-4.14/950-0335-defconfig-Enable-Unicam-driver-and-various-sources-o.patch
deleted file mode 100644
index 79a88fa46..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0335-defconfig-Enable-Unicam-driver-and-various-sources-o.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 523c96b2a6127bdc1ebe4a35d59bc458cd77fe02 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 11 Apr 2018 11:18:43 +0100
-Subject: [PATCH 335/454] defconfig: Enable Unicam driver and various sources
- on Pi platforms.
-
-Enable:
-	VIDEO_V4L2_SUBDEV_API=y
-	VIDEO_BCM2835_UNICAM=m
-	VIDEO_TC358743=m
-	VIDEO_ADV7180=m
-	VIDEO_OV5647=m
-so that we can receive CSI data from these devices.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 5 +++++
- arch/arm/configs/bcmrpi_defconfig  | 5 +++++
- 2 files changed, 10 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -697,6 +697,7 @@ CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
- CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
- CONFIG_MEDIA_RADIO_SUPPORT=y
- CONFIG_MEDIA_CONTROLLER=y
-+CONFIG_VIDEO_V4L2_SUBDEV_API=y
- CONFIG_MEDIA_USB_SUPPORT=y
- CONFIG_USB_VIDEO_CLASS=m
- CONFIG_USB_M5602=m
-@@ -815,6 +816,7 @@ CONFIG_VIDEO_EM28XX_V4L2=m
- CONFIG_VIDEO_EM28XX_ALSA=m
- CONFIG_VIDEO_EM28XX_DVB=m
- CONFIG_V4L_PLATFORM_DRIVERS=y
-+CONFIG_VIDEO_BCM2835_UNICAM=m
- CONFIG_RADIO_SI470X=y
- CONFIG_USB_SI470X=m
- CONFIG_I2C_SI470X=m
-@@ -834,10 +836,13 @@ CONFIG_RADIO_WL128X=m
- # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
- CONFIG_VIDEO_UDA1342=m
- CONFIG_VIDEO_SONY_BTF_MPX=m
-+CONFIG_VIDEO_ADV7180=m
-+CONFIG_VIDEO_TC358743=m
- CONFIG_VIDEO_TVP5150=m
- CONFIG_VIDEO_TW2804=m
- CONFIG_VIDEO_TW9903=m
- CONFIG_VIDEO_TW9906=m
-+CONFIG_VIDEO_OV5647=m
- CONFIG_VIDEO_OV7640=m
- CONFIG_VIDEO_MT9V011=m
- CONFIG_DRM=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -690,6 +690,7 @@ CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
- CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
- CONFIG_MEDIA_RADIO_SUPPORT=y
- CONFIG_MEDIA_CONTROLLER=y
-+CONFIG_VIDEO_V4L2_SUBDEV_API=y
- CONFIG_MEDIA_USB_SUPPORT=y
- CONFIG_USB_VIDEO_CLASS=m
- CONFIG_USB_M5602=m
-@@ -808,6 +809,7 @@ CONFIG_VIDEO_EM28XX_V4L2=m
- CONFIG_VIDEO_EM28XX_ALSA=m
- CONFIG_VIDEO_EM28XX_DVB=m
- CONFIG_V4L_PLATFORM_DRIVERS=y
-+CONFIG_VIDEO_BCM2835_UNICAM=m
- CONFIG_RADIO_SI470X=y
- CONFIG_USB_SI470X=m
- CONFIG_I2C_SI470X=m
-@@ -827,10 +829,13 @@ CONFIG_RADIO_WL128X=m
- # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
- CONFIG_VIDEO_UDA1342=m
- CONFIG_VIDEO_SONY_BTF_MPX=m
-+CONFIG_VIDEO_ADV7180=m
-+CONFIG_VIDEO_TC358743=m
- CONFIG_VIDEO_TVP5150=m
- CONFIG_VIDEO_TW2804=m
- CONFIG_VIDEO_TW9903=m
- CONFIG_VIDEO_TW9906=m
-+CONFIG_VIDEO_OV5647=m
- CONFIG_VIDEO_OV7640=m
- CONFIG_VIDEO_MT9V011=m
- CONFIG_DRM=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0336-media-adv7180-Nasty-hack-to-allow-input-selection.patch b/target/linux/brcm2708/patches-4.14/950-0336-media-adv7180-Nasty-hack-to-allow-input-selection.patch
deleted file mode 100644
index 27ad30524..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0336-media-adv7180-Nasty-hack-to-allow-input-selection.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From f5bc65a235291381313a7a9769b46afbfc267ae0 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 18 Apr 2018 14:13:32 +0100
-Subject: [PATCH 336/454] media: adv7180: Nasty hack to allow input selection.
-
-Whilst the adv7180 driver support s_routing, nothing else
-does, and there is a missing lump of framework code to
-define the mapping from connectors on a board to the inputs
-they represent on the ADV7180.
-
-Add a nasty hack to take a module parameter that is passed in
-to s_routing on any call to G_STD, or S_STD (or subdev
-g_input_status call).
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/adv7180.c | 30 ++++++++++++++++++++++++++++--
- 1 file changed, 28 insertions(+), 2 deletions(-)
-
---- a/drivers/media/i2c/adv7180.c
-+++ b/drivers/media/i2c/adv7180.c
-@@ -189,6 +189,10 @@
- 
- #define V4L2_CID_ADV_FAST_SWITCH	(V4L2_CID_USER_ADV7180_BASE + 0x00)
- 
-+static int dbg_input;
-+module_param(dbg_input, int, 0644);
-+MODULE_PARM_DESC(dbg_input, "Input number (0-31)");
-+
- struct adv7180_state;
- 
- #define ADV7180_FLAG_RESET_POWERED	BIT(0)
-@@ -405,10 +409,24 @@ out:
- 	return ret;
- }
- 
-+static void adv7180_check_input(struct v4l2_subdev *sd)
-+{
-+	struct adv7180_state *state = to_state(sd);
-+
-+	if (state->input != dbg_input)
-+		if (adv7180_s_routing(sd, dbg_input, 0, 0))
-+			/* Failed - reset dbg_input */
-+			dbg_input = state->input;
-+}
-+
- static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
- {
- 	struct adv7180_state *state = to_state(sd);
--	int ret = mutex_lock_interruptible(&state->mutex);
-+	int ret;
-+
-+	adv7180_check_input(sd);
-+
-+	ret = mutex_lock_interruptible(&state->mutex);
- 	if (ret)
- 		return ret;
- 
-@@ -434,7 +452,11 @@ static int adv7180_program_std(struct ad
- static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
- {
- 	struct adv7180_state *state = to_state(sd);
--	int ret = mutex_lock_interruptible(&state->mutex);
-+	int ret;
-+
-+	adv7180_check_input(sd);
-+
-+	ret = mutex_lock_interruptible(&state->mutex);
- 
- 	if (ret)
- 		return ret;
-@@ -456,6 +478,8 @@ static int adv7180_g_std(struct v4l2_sub
- {
- 	struct adv7180_state *state = to_state(sd);
- 
-+	adv7180_check_input(sd);
-+
- 	*norm = state->curr_norm;
- 
- 	return 0;
-@@ -791,6 +815,8 @@ static int adv7180_s_stream(struct v4l2_
- 		return 0;
- 	}
- 
-+	adv7180_check_input(sd);
-+
- 	/* Must wait until querystd released the lock */
- 	ret = mutex_lock_interruptible(&state->mutex);
- 	if (ret)
diff --git a/target/linux/brcm2708/patches-4.14/950-0337-media-adv7180-Add-YPrPb-support-for-ADV7282M.patch b/target/linux/brcm2708/patches-4.14/950-0337-media-adv7180-Add-YPrPb-support-for-ADV7282M.patch
deleted file mode 100644
index 0007737d0..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0337-media-adv7180-Add-YPrPb-support-for-ADV7282M.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From a2fe75b5c7c3367e2b853f26fed454ce4bda86db Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Mon, 30 Apr 2018 16:44:24 +0100
-Subject: [PATCH 337/454] media: adv7180: Add YPrPb support for ADV7282M
-
-The ADV7282M can support YPbPr on AIN1-3, but this was
-not selectable from the driver. Add it to the list of
-supported input modes.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/adv7180.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/media/i2c/adv7180.c
-+++ b/drivers/media/i2c/adv7180.c
-@@ -1235,6 +1235,7 @@ static const struct adv7180_chip_info ad
- 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
- 		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
- 		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
-+		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
- 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
- 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
- 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
diff --git a/target/linux/brcm2708/patches-4.14/950-0338-arm-dts-bcm2710-rpi-3-b-plus-fix-hpd-gpio-pin.patch b/target/linux/brcm2708/patches-4.14/950-0338-arm-dts-bcm2710-rpi-3-b-plus-fix-hpd-gpio-pin.patch
deleted file mode 100644
index 937589f75..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0338-arm-dts-bcm2710-rpi-3-b-plus-fix-hpd-gpio-pin.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 7ae46019667c122c3e2a5a291b2cd5b62df524f9 Mon Sep 17 00:00:00 2001
-From: Lukas Rusak <lorusak@gmail.com>
-Date: Fri, 29 Jun 2018 10:13:59 -0700
-Subject: [PATCH 338/454] arm: dts: bcm2710-rpi-3-b-plus: fix hpd gpio pin
-
-Signed-off-by: Lukas Rusak <lorusak@gmail.com>
----
- arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts
-+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts
-@@ -162,7 +162,7 @@
- };
- 
- &hdmi {
--	hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>;
-+	hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
- };
- 
- &audio {
diff --git a/target/linux/brcm2708/patches-4.14/950-0339-Add-device-tree-overlay-for-HD44780.patch b/target/linux/brcm2708/patches-4.14/950-0339-Add-device-tree-overlay-for-HD44780.patch
deleted file mode 100644
index 27057cd62..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0339-Add-device-tree-overlay-for-HD44780.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From d1f9b37d299ef8cbd740a3f6cb7f71db887737d6 Mon Sep 17 00:00:00 2001
-From: Jasper Boomer <jasperboomer@gmail.com>
-Date: Sun, 24 Jun 2018 12:20:27 -0400
-Subject: [PATCH 339/454] Add device tree overlay for HD44780
-
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             | 25 ++++++++++
- .../boot/dts/overlays/hd44780-lcd-overlay.dts | 46 +++++++++++++++++++
- 3 files changed, 72 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -38,6 +38,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	gpio-no-irq.dtbo \
- 	gpio-poweroff.dtbo \
- 	gpio-shutdown.dtbo \
-+	hd44780-lcd.dtbo \
- 	hifiberry-amp.dtbo \
- 	hifiberry-dac.dtbo \
- 	hifiberry-dacplus.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -639,6 +639,31 @@ Params: gpio_pin                GPIO pin
-                                 external pullup.
- 
- 
-+Name:   hd44780-lcd
-+Info:   Configures an HD44780 compatible LCD display. Uses 4 gpio pins for
-+        data, 2 gpio pins for enable and register select and 1 optional pin
-+        for enabling/disabling the backlight display.
-+Load:   dtoverlay=hd44780-lcd,<param>=<val>
-+Params: pin_d4                  GPIO pin for data pin D4 (default 6)
-+
-+        pin_d5                  GPIO pin for data pin D5 (default 13)
-+
-+        pin_d6                  GPIO pin for data pin D6 (default 19)
-+
-+        pin_d7                  GPIO pin for data pin D7 (default 26)
-+
-+        pin_en                  GPIO pin for "Enable" (default 21)
-+
-+        pin_rs                  GPIO pin for "Register Select" (default 20)
-+
-+        pin_bl                  Optional pin for enabling/disabling the
-+                                display backlight. (default disabled)
-+
-+        display_height          Height of the display in characters
-+
-+        display_width           Width of the display in characters
-+
-+
- Name:   hifiberry-amp
- Info:   Configures the HifiBerry Amp and Amp+ audio cards
- Load:   dtoverlay=hifiberry-amp
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts
-@@ -0,0 +1,46 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+    compatible = "brcm,bcm2835";
-+
-+    fragment@0 {
-+        target-path = "/";
-+        __overlay__ {
-+            lcd_screen: auxdisplay {
-+                compatible = "hit,hd44780";
-+
-+                data-gpios = <&gpio 6 0>,
-+                             <&gpio 13 0>,
-+                             <&gpio 19 0>,
-+                             <&gpio 26 0>;
-+                enable-gpios = <&gpio 21 0>;
-+                rs-gpios = <&gpio 20 0>;
-+
-+                display-height-chars = <2>;
-+                display-width-chars = <16>;
-+            };
-+
-+        };
-+    };
-+
-+    fragment@1 {
-+       target = <&lcd_screen>;
-+        __dormant__ {
-+            backlight-gpios = <&gpio 12 0>;
-+        };
-+    };
-+
-+    __overrides__ {
-+        pin_d4 = <&lcd_screen>,"data-gpios:4";
-+        pin_d5 = <&lcd_screen>,"data-gpios:16";
-+        pin_d6 = <&lcd_screen>,"data-gpios:28";
-+        pin_d7 = <&lcd_screen>,"data-gpios:40";
-+        pin_en = <&lcd_screen>,"enable-gpios:4";
-+        pin_rs = <&lcd_screen>,"rs-gpios:4";
-+        pin_bl = <0>,"+1", <&lcd_screen>,"backlight-gpios:4";
-+        display_height = <&lcd_screen>,"display-height-chars:0";
-+        display_width = <&lcd_screen>,"display-width-chars:0";
-+    };
-+
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0340-Add-hd44780-module-to-defconfig.patch b/target/linux/brcm2708/patches-4.14/950-0340-Add-hd44780-module-to-defconfig.patch
deleted file mode 100644
index 620976025..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0340-Add-hd44780-module-to-defconfig.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 520999bda431e0bec4d9bd0dc348696b46b31091 Mon Sep 17 00:00:00 2001
-From: Jasper Boomer <jasperboomer@gmail.com>
-Date: Mon, 2 Jul 2018 13:16:22 -0400
-Subject: [PATCH 340/454] Add hd44780 module to defconfig
-
----
- arch/arm/configs/bcm2709_defconfig | 2 ++
- arch/arm/configs/bcmrpi_defconfig  | 2 ++
- 2 files changed, 4 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -1145,6 +1145,8 @@ CONFIG_RTC_DRV_RV3029C2=m
- CONFIG_DMADEVICES=y
- CONFIG_DMA_BCM2835=y
- CONFIG_DMA_BCM2708=y
-+CONFIG_AUXDISPLAY=y
-+CONFIG_HD44780=m
- CONFIG_UIO=m
- CONFIG_UIO_PDRV_GENIRQ=m
- CONFIG_STAGING=y
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -1138,6 +1138,8 @@ CONFIG_RTC_DRV_RV3029C2=m
- CONFIG_DMADEVICES=y
- CONFIG_DMA_BCM2835=y
- CONFIG_DMA_BCM2708=y
-+CONFIG_AUXDISPLAY=y
-+CONFIG_HD44780=m
- CONFIG_UIO=m
- CONFIG_UIO_PDRV_GENIRQ=m
- CONFIG_STAGING=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0341-BCM283x-DT-Add-CSI-nodes-to-the-device-tree.patch b/target/linux/brcm2708/patches-4.14/950-0341-BCM283x-DT-Add-CSI-nodes-to-the-device-tree.patch
deleted file mode 100644
index eb3635a8f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0341-BCM283x-DT-Add-CSI-nodes-to-the-device-tree.patch
+++ /dev/null
@@ -1,189 +0,0 @@
-From ca576b3fd93dff35bdf39f5fd44edf938e545ac9 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 5 Jul 2018 16:43:56 +0100
-Subject: [PATCH 341/454] BCM283x DT: Add CSI nodes to the device tree.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- arch/arm/boot/dts/bcm2708-rpi.dtsi            |  8 ++++++
- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts      |  1 +
- arch/arm/boot/dts/bcm2835-rpi-a.dts           |  1 +
- arch/arm/boot/dts/bcm2835-rpi-b-plus.dts      |  1 +
- arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts      |  1 +
- arch/arm/boot/dts/bcm2835-rpi-b.dts           |  1 +
- arch/arm/boot/dts/bcm2835-rpi-zero.dts        |  1 +
- arch/arm/boot/dts/bcm2835-rpi.dtsi            |  8 ++++++
- arch/arm/boot/dts/bcm2836-rpi-2-b.dts         |  1 +
- arch/arm/boot/dts/bcm2837-rpi-3-b.dts         |  1 +
- arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi |  7 +++++
- arch/arm/boot/dts/bcm283x.dtsi                | 28 +++++++++++++++++++
- .../dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi  |  1 +
- 13 files changed, 60 insertions(+)
- create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi
- create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi
-
---- a/arch/arm/boot/dts/bcm2708-rpi.dtsi
-+++ b/arch/arm/boot/dts/bcm2708-rpi.dtsi
-@@ -160,3 +160,11 @@ sdhost_pins: &sdhost_gpio48 {
- &vec {
- 	status = "disabled";
- };
-+
-+&csi0 {
-+	power-domains = <&power RPI_POWER_DOMAIN_UNICAM0>;
-+};
-+
-+&csi1 {
-+	power-domains = <&power RPI_POWER_DOMAIN_UNICAM1>;
-+};
---- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
-+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
-@@ -3,6 +3,7 @@
- #include "bcm2835.dtsi"
- #include "bcm2835-rpi.dtsi"
- #include "bcm283x-rpi-usb-host.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
---- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
-+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
-@@ -3,6 +3,7 @@
- #include "bcm2835.dtsi"
- #include "bcm2835-rpi.dtsi"
- #include "bcm283x-rpi-usb-host.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,model-a", "brcm,bcm2835";
---- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
-+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
-@@ -4,6 +4,7 @@
- #include "bcm2835-rpi.dtsi"
- #include "bcm283x-rpi-smsc9514.dtsi"
- #include "bcm283x-rpi-usb-host.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
---- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
-+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
-@@ -4,6 +4,7 @@
- #include "bcm2835-rpi.dtsi"
- #include "bcm283x-rpi-smsc9512.dtsi"
- #include "bcm283x-rpi-usb-host.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
---- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
-+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
-@@ -4,6 +4,7 @@
- #include "bcm2835-rpi.dtsi"
- #include "bcm283x-rpi-smsc9512.dtsi"
- #include "bcm283x-rpi-usb-host.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,model-b", "brcm,bcm2835";
---- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
-+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
-@@ -13,6 +13,7 @@
- #include "bcm2835.dtsi"
- #include "bcm2835-rpi.dtsi"
- #include "bcm283x-rpi-usb-otg.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,model-zero", "brcm,bcm2835";
---- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
-+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
-@@ -106,3 +106,11 @@
- &dsi1 {
- 	power-domains = <&power RPI_POWER_DOMAIN_DSI1>;
- };
-+
-+&csi0 {
-+	power-domains = <&power RPI_POWER_DOMAIN_UNICAM0>;
-+};
-+
-+&csi1 {
-+	power-domains = <&power RPI_POWER_DOMAIN_UNICAM1>;
-+};
---- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
-+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
-@@ -4,6 +4,7 @@
- #include "bcm2835-rpi.dtsi"
- #include "bcm283x-rpi-smsc9514.dtsi"
- #include "bcm283x-rpi-usb-host.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
---- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
-+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
-@@ -4,6 +4,7 @@
- #include "bcm2835-rpi.dtsi"
- #include "bcm283x-rpi-smsc9514.dtsi"
- #include "bcm283x-rpi-usb-host.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi
-@@ -0,0 +1,7 @@
-+&csi1 {
-+	port {
-+		endpoint {
-+			data-lanes = <1 2>;
-+		};
-+	};
-+};
---- a/arch/arm/boot/dts/bcm283x.dtsi
-+++ b/arch/arm/boot/dts/bcm283x.dtsi
-@@ -544,6 +544,34 @@
- 			status = "disabled";
- 		};
- 
-+		csi0: csi0@7e800000 {
-+			compatible = "brcm,bcm2835-unicam";
-+			reg = <0x7e800000 0x800>,
-+			      <0x7e802000 0x4>;
-+			interrupts = <2 6>;
-+			clocks = <&clocks BCM2835_CLOCK_CAM0>;
-+			clock-names = "lp";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			#clock-cells = <1>;
-+
-+			status = "disabled";
-+		};
-+
-+		csi1: csi1@7e801000 {
-+			compatible = "brcm,bcm2835-unicam";
-+			reg = <0x7e801000 0x800>,
-+			      <0x7e802004 0x4>;
-+			interrupts = <2 7>;
-+			clocks = <&clocks BCM2835_CLOCK_CAM1>;
-+			clock-names = "lp";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			#clock-cells = <1>;
-+
-+			status = "disabled";
-+		};
-+
- 		i2c1: i2c@7e804000 {
- 			compatible = "brcm,bcm2835-i2c";
- 			reg = <0x7e804000 0x1000>;
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi
-@@ -0,0 +1,7 @@
-+&csi1 {
-+	port {
-+		endpoint {
-+			data-lanes = <1 2>;
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0342-BCM270X_DT-Add-CSI-defines-for-all-the-downstream-Pi.patch b/target/linux/brcm2708/patches-4.14/950-0342-BCM270X_DT-Add-CSI-defines-for-all-the-downstream-Pi.patch
deleted file mode 100644
index f5b4b7129..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0342-BCM270X_DT-Add-CSI-defines-for-all-the-downstream-Pi.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From 998fa413419cc659e7e8646e63000d77d326e08b Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 5 Jul 2018 16:44:16 +0100
-Subject: [PATCH 342/454] BCM270X_DT: Add CSI defines for all the downstream Pi
- platforms
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- arch/arm/boot/dts/bcm2708-rpi-0-w.dts         | 1 +
- arch/arm/boot/dts/bcm2708-rpi-b-plus.dts      | 1 +
- arch/arm/boot/dts/bcm2708-rpi-b.dts           | 1 +
- arch/arm/boot/dts/bcm2708-rpi-cm.dts          | 2 ++
- arch/arm/boot/dts/bcm2709-rpi-2-b.dts         | 1 +
- arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts    | 1 +
- arch/arm/boot/dts/bcm2710-rpi-3-b.dts         | 1 +
- arch/arm/boot/dts/bcm2710-rpi-cm3.dts         | 2 ++
- arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi | 7 +++++++
- arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi | 7 +++++++
- 10 files changed, 24 insertions(+)
- create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi
- create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi
-
---- a/arch/arm/boot/dts/bcm2708-rpi-0-w.dts
-+++ b/arch/arm/boot/dts/bcm2708-rpi-0-w.dts
-@@ -1,6 +1,7 @@
- /dts-v1/;
- 
- #include "bcm2708.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
---- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
-+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
-@@ -2,6 +2,7 @@
- 
- #include "bcm2708.dtsi"
- #include "bcm283x-rpi-smsc9514.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	model = "Raspberry Pi Model B+";
---- a/arch/arm/boot/dts/bcm2708-rpi-b.dts
-+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts
-@@ -2,6 +2,7 @@
- 
- #include "bcm2708.dtsi"
- #include "bcm283x-rpi-smsc9512.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	model = "Raspberry Pi Model B";
---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts
-+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts
-@@ -1,6 +1,8 @@
- /dts-v1/;
- 
- #include "bcm2708-rpi-cm.dtsi"
-+#include "bcm283x-rpi-csi0-2lane.dtsi"
-+#include "bcm283x-rpi-csi1-4lane.dtsi"
- 
- / {
- 	model = "Raspberry Pi Compute Module";
---- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
-+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
-@@ -2,6 +2,7 @@
- 
- #include "bcm2709.dtsi"
- #include "bcm283x-rpi-smsc9514.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
---- a/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts
-+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts
-@@ -2,6 +2,7 @@
- 
- #include "bcm2710.dtsi"
- #include "bcm283x-rpi-lan7515.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
---- a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-@@ -2,6 +2,7 @@
- 
- #include "bcm2710.dtsi"
- #include "bcm283x-rpi-smsc9514.dtsi"
-+#include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
- 	compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
---- a/arch/arm/boot/dts/bcm2710-rpi-cm3.dts
-+++ b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts
-@@ -1,6 +1,8 @@
- /dts-v1/;
- 
- #include "bcm2710.dtsi"
-+#include "bcm283x-rpi-csi0-2lane.dtsi"
-+#include "bcm283x-rpi-csi1-4lane.dtsi"
- 
- / {
- 	model = "Raspberry Pi Compute Module 3";
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi
-@@ -0,0 +1,7 @@
-+&csi0 {
-+	port {
-+		endpoint {
-+			data-lanes = <1 2>;
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi
-@@ -0,0 +1,7 @@
-+&csi1 {
-+	port {
-+		endpoint {
-+			data-lanes = <1 2 3 4>;
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0343-arm-dt-Add-DT-overlays-for-ADV7282M-OV5647-and-TC358.patch b/target/linux/brcm2708/patches-4.14/950-0343-arm-dt-Add-DT-overlays-for-ADV7282M-OV5647-and-TC358.patch
deleted file mode 100644
index 008af64e8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0343-arm-dt-Add-DT-overlays-for-ADV7282M-OV5647-and-TC358.patch
+++ /dev/null
@@ -1,477 +0,0 @@
-From c4146a18836381f09b1ea2f4295cb94aa606f67b Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 5 Jul 2018 16:44:39 +0100
-Subject: [PATCH 343/454] arm: dt: Add DT overlays for ADV7282M, OV5647, and
- TC358743
-
-DT overlays to setup the above devices via i2c_arm and csi1.
-(This currently does not use the i2c-mux-pinctrl driver to
-dynamically switch the pinctrl)
-
-tc358743 is tc358743 running at a default link frequency
-of 972Mbit/s. This allows up to 1080P50 UYVY on 2 lanes.
-There is a parameter to allow changing the link frequency,
-but the only values supported by the driver are 297000000
-for 594Mbit/s, and 486000000 for 972Mbit/s.
-There is also a parameter to enable 4 lane mode (only
-relevant to Compute Module (1 or 3) csi1).
-
-tc358743-audio overlay enables I2S audio from the TC358743
-to the Pi (SD to GPIO20, SCK to GPIO18, WFS to GPIO19).
-
-ADV7282M is the Analog Devices analogue video to CSI bridge
-chip.
-
-OV5647 is the Pi V1.3 camera module. Currently the driver only
-supports VGA 8bit Bayer and very few controls.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |   4 +
- arch/arm/boot/dts/overlays/README             |  51 ++++++++
- .../boot/dts/overlays/adv7282m-overlay.dts    |  75 ++++++++++++
- arch/arm/boot/dts/overlays/ov5647-overlay.dts |  86 ++++++++++++++
- .../dts/overlays/tc358743-audio-overlay.dts   |  51 ++++++++
- .../boot/dts/overlays/tc358743-overlay.dts    | 111 ++++++++++++++++++
- 6 files changed, 378 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/adv7282m-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/ov5647-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts
- create mode 100644 arch/arm/boot/dts/overlays/tc358743-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -6,6 +6,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	ads1015.dtbo \
- 	ads1115.dtbo \
- 	ads7846.dtbo \
-+	adv7282m.dtbo \
- 	akkordion-iqdacplus.dtbo \
- 	allo-boss-dac-pcm512x-audio.dtbo \
- 	allo-digione.dtbo \
-@@ -77,6 +78,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	mmc.dtbo \
- 	mpu6050.dtbo \
- 	mz61581.dtbo \
-+	ov5647.dtbo \
- 	papirus.dtbo \
- 	pi3-act-led.dtbo \
- 	pi3-disable-bt.dtbo \
-@@ -127,6 +129,8 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	spi2-3cs.dtbo \
- 	superaudioboard.dtbo \
- 	sx150x.dtbo \
-+	tc358743.dtbo \
-+	tc358743-audio.dtbo \
- 	tinylcd35.dtbo \
- 	uart0.dtbo \
- 	uart1.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -267,6 +267,15 @@ Params: cs                      SPI bus
-         www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt
- 
- 
-+Name:   adv7282m
-+Info:   Analog Devices ADV7282M analogue video to CSI2 bridge.
-+        Uses Unicam1, which is the standard camera connector on most Pi
-+        variants.
-+Load:   dtoverlay=adv7282m,<param>=<val>
-+Params: i2c_pins_28_29          Use pins 28&29 for the I2C instead of 44&45.
-+                                This is required for Pi B+, 2, 0, and 0W.
-+
-+
- Name:   akkordion-iqdacplus
- Info:   Configures the Digital Dreamtime Akkordion Music Player (based on the
-         OEM IQAudIO DAC+ or DAC Zero module).
-@@ -1232,6 +1241,23 @@ Params: speed                   Display
-         xohms                   Touchpanel sensitivity (X-plate resistance)
- 
- 
-+Name:   ov5647
-+Info:   Omnivision OV5647 camera module.
-+        Uses Unicam 1, which is the standard camera connector on most Pi
-+        variants.
-+Load:   dtoverlay=ov5647,<param>=<val>
-+Params: cam0-pwdn               GPIO used to control the sensor powerdown line.
-+
-+        cam0-led                GPIO used to control the sensor led
-+                                Both these fields should be automatically filled
-+                                in by the firmware to reflect the default GPIO
-+                                configuration of the particular Pi variant in
-+                                use.
-+
-+        i2c_pins_28_29          Use pins 28&29 for the I2C instead of 44&45.
-+                                This is required for Pi B+, 2, 0, and 0W.
-+
-+
- Name:   papirus
- Info:   PaPiRus ePaper Screen by Pi Supply (both HAT and pHAT)
- Load:   dtoverlay=papirus,<param>=<val>
-@@ -1828,6 +1854,31 @@ Params: sx150<x>-<n>-<m>        Enables
-                                 connected.
- 
- 
-+Name:   tc358743
-+Info:   Toshiba TC358743 HDMI to CSI-2 bridge chip.
-+        Uses Unicam 1, which is the standard camera connector on most Pi
-+        variants.
-+Load:   dtoverlay=tc358743,<param>=<val>
-+Params: 4lane                   Use 4 lanes (only applicable to Compute Modules
-+                                CAM1 connector).
-+
-+        link-frequency          Set the link frequency. Only values of 297000000
-+                                (574Mbit/s) and 486000000 (972Mbit/s - default)
-+                                are supported by the driver.
-+
-+        i2c_pins_28_29          Use pins 28&29 for the I2C instead of 44&45.
-+                                This is required for Pi B+, 2, 0, and 0W.
-+
-+
-+Name:   tc358743-audio
-+Info:   Used in combination with the tc358743-fast overlay to route the audio
-+        from the TC358743 over I2S to the Pi.
-+        Wiring is LRCK/WFS to GPIO 19, BCK/SCK to GPIO 18, and DATA/SD to GPIO
-+        20.
-+Load:   dtoverlay=tc358743-audio,<param>=<val>
-+Params: card-name               Override the default, "tc358743", card name.
-+
-+
- Name:   tinylcd35
- Info:   3.5" Color TFT Display by www.tinylcd.com
-         Options: Touch, RTC, keypad
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/adv7282m-overlay.dts
-@@ -0,0 +1,75 @@
-+// Definitions for Analog Devices ADV7282-M video to CSI2 bridge on VC I2C bus
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_vc>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			adv7282: adv7282@21 {
-+				compatible = "adi,adv7282-m";
-+				reg = <0x21>;
-+				status = "okay";
-+				clock-frequency = <24000000>;
-+				port {
-+					adv7282_0: endpoint {
-+						remote-endpoint = <&csi1_ep>;
-+						clock-lanes = <0>;
-+						data-lanes = <1>;
-+						link-frequencies =
-+							/bits/ 64 <297000000>;
-+
-+						mclk-frequency = <12000000>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+	fragment@1 {
-+		target = <&csi1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			port {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				csi1_ep: endpoint {
-+					remote-endpoint = <&adv7282_0>;
-+				};
-+			};
-+		};
-+	};
-+	fragment@2 {
-+		target = <&i2c0_pins>;
-+		__dormant__ {
-+			brcm,pins = <28 29>;
-+			brcm,function = <4>; /* alt0 */
-+		};
-+
-+	};
-+	fragment@3 {
-+		target = <&i2c0_pins>;
-+		__overlay__ {
-+			brcm,pins = <44 45>;
-+			brcm,function = <5>; /* alt1 */
-+		};
-+	};
-+	fragment@4 {
-+		target = <&i2c_vc>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		i2c_pins_28_29 = <0>,"+2-3";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/ov5647-overlay.dts
-@@ -0,0 +1,86 @@
-+// Definitions for OV5647 camera module on VC I2C bus
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_vc>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			ov5647: ov5647@36 {
-+				compatible = "ov5647";
-+				reg = <0x36>;
-+				status = "okay";
-+
-+				pwdn-gpios = <&gpio 41 1>, <&gpio 32 1>;
-+				clocks = <&ov5647_clk>;
-+
-+				ov5647_clk: camera-clk {
-+					compatible = "fixed-clock";
-+					#clock-cells = <0>;
-+					clock-frequency = <25000000>;
-+				};
-+
-+				port {
-+					ov5647_0: endpoint {
-+						remote-endpoint = <&csi1_ep>;
-+						clock-lanes = <0>;
-+						data-lanes = <1 2>;
-+						clock-noncontinuous;
-+						link-frequencies =
-+							/bits/ 64 <297000000>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&csi1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			port {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				csi1_ep: endpoint {
-+					remote-endpoint = <&ov5647_0>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c0_pins>;
-+		__dormant__ {
-+			brcm,pins = <28 29>;
-+			brcm,function = <4>; /* alt0 */
-+		};
-+	};
-+	fragment@3 {
-+		target = <&i2c0_pins>;
-+		__overlay__ {
-+			brcm,pins = <44 45>;
-+			brcm,function = <5>; /* alt1 */
-+		};
-+	};
-+	fragment@4 {
-+		target = <&i2c_vc>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		i2c_pins_28_29 = <0>,"+4-5";
-+		cam0-pwdn = <&ov5647>,"pwdn-gpios:4";
-+		cam0-led = <&ov5647>,"pwdn-gpios:16";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts
-@@ -0,0 +1,51 @@
-+// Definitions to add I2S audio from the Toshiba TC358743 HDMI to CSI2 bridge.
-+// Requires tc358743 overlay to have been loaded to actually function.
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target-path = "/";
-+		__overlay__ {
-+			tc358743_codec: tc358743-codec {
-+				#sound-dai-cells = <0>;
-+				compatible = "linux,spdif-dir";
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		sound_overlay: __overlay__ {
-+			compatible = "simple-audio-card";
-+			simple-audio-card,format = "i2s";
-+			simple-audio-card,name = "tc358743";
-+			simple-audio-card,bitclock-master = <&dailink0_slave>;
-+			simple-audio-card,frame-master = <&dailink0_slave>;
-+			status = "okay";
-+
-+			simple-audio-card,cpu {
-+				sound-dai = <&i2s>;
-+				dai-tdm-slot-num = <2>;
-+				dai-tdm-slot-width = <32>;
-+			};
-+			dailink0_slave: simple-audio-card,codec {
-+				sound-dai = <&tc358743_codec>;
-+			};
-+		};
-+	};
-+
-+	__overrides__ {
-+		card-name = <&sound_overlay>,"simple-audio-card,name";
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/tc358743-overlay.dts
-@@ -0,0 +1,111 @@
-+// Definitions for Toshiba TC358743 HDMI to CSI2 bridge on VC I2C bus
-+/dts-v1/;
-+/plugin/;
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2c_vc>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			tc358743@0f {
-+				compatible = "toshiba,tc358743";
-+				reg = <0x0f>;
-+				status = "okay";
-+
-+				clocks = <&tc358743_clk>;
-+				clock-names = "refclk";
-+
-+				tc358743_clk: bridge-clk {
-+					compatible = "fixed-clock";
-+					#clock-cells = <0>;
-+					clock-frequency = <27000000>;
-+				};
-+
-+				port {
-+					tc358743: endpoint {
-+						remote-endpoint = <&csi1_ep>;
-+						clock-lanes = <0>;
-+						clock-noncontinuous;
-+						link-frequencies =
-+							/bits/ 64 <486000000>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&csi1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			port {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				csi1_ep: endpoint {
-+					remote-endpoint = <&tc358743>;
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&i2c_vc>;
-+		__overlay__ {
-+			tc358743@0f {
-+				port {
-+					endpoint {
-+						data-lanes = <1 2>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&i2c_vc>;
-+		__dormant__ {
-+			tc358743@0f {
-+				port {
-+					endpoint {
-+						data-lanes = <1 2 3 4>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&i2c0_pins>;
-+		__dormant__ {
-+			brcm,pins = <28 29>;
-+			brcm,function = <4>; /* alt0 */
-+		};
-+	};
-+	fragment@5 {
-+		target = <&i2c0_pins>;
-+		__overlay__ {
-+			brcm,pins = <44 45>;
-+			brcm,function = <5>; /* alt1 */
-+		};
-+	};
-+	fragment@6 {
-+		target = <&i2c_vc>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	__overrides__ {
-+		i2c_pins_28_29 = <0>,"+4-5";
-+		4lane = <0>, "-2+3";
-+	        link-frequency = <&tc358743>,"link-frequencies#0";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0344-drm-vc4-Set-premultiplied-for-alpha-formats.patch b/target/linux/brcm2708/patches-4.14/950-0344-drm-vc4-Set-premultiplied-for-alpha-formats.patch
deleted file mode 100644
index cfbdfab0d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0344-drm-vc4-Set-premultiplied-for-alpha-formats.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 641b88e2572a66be56c2c1d5aae9acd38d8c6932 Mon Sep 17 00:00:00 2001
-From: Stefan Schake <stschake@gmail.com>
-Date: Fri, 9 Mar 2018 01:53:34 +0100
-Subject: [PATCH 344/454] drm/vc4: Set premultiplied for alpha formats
-
-commit 05202c241f1476d8e2b30bb2699f6780962972e8 upstream.
-
-Alpha formats in DRM are assumed to be premultiplied, so we should be
-setting the PREMULT bit in the plane configuration for HVS.
-
-Changes from v1:
- - Use correct has_alpha
-
-Signed-off-by: Stefan Schake <stschake@gmail.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/1520556817-97297-2-git-send-email-stschake@gmail.com
----
- drivers/gpu/drm/vc4/vc4_plane.c | 3 ++-
- drivers/gpu/drm/vc4/vc4_regs.h  | 1 +
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -618,13 +618,14 @@ static int vc4_plane_mode_set(struct drm
- 					      SCALER_POS1_SCL_HEIGHT));
- 	}
- 
--	/* Position Word 2: Source Image Size, Alpha Mode */
-+	/* Position Word 2: Source Image Size, Alpha */
- 	vc4_state->pos2_offset = vc4_state->dlist_count;
- 	vc4_dlist_write(vc4_state,
- 			VC4_SET_FIELD(format->has_alpha ?
- 				      SCALER_POS2_ALPHA_MODE_PIPELINE :
- 				      SCALER_POS2_ALPHA_MODE_FIXED,
- 				      SCALER_POS2_ALPHA_MODE) |
-+			(format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
- 			VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
- 			VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
- 
---- a/drivers/gpu/drm/vc4/vc4_regs.h
-+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -877,6 +877,7 @@ enum hvs_pixel_format {
- #define SCALER_POS2_ALPHA_MODE_FIXED		1
- #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO	2
- #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07	3
-+#define SCALER_POS2_ALPHA_PREMULT		BIT(29)
- 
- #define SCALER_POS2_HEIGHT_MASK			VC4_MASK(27, 16)
- #define SCALER_POS2_HEIGHT_SHIFT		16
diff --git a/target/linux/brcm2708/patches-4.14/950-0345-drm-vc4-Check-if-plane-requires-background-fill.patch b/target/linux/brcm2708/patches-4.14/950-0345-drm-vc4-Check-if-plane-requires-background-fill.patch
deleted file mode 100644
index 709af646b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0345-drm-vc4-Check-if-plane-requires-background-fill.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 7771310ee7e9b7291e549e36771de6176d57e24b Mon Sep 17 00:00:00 2001
-From: Stefan Schake <stschake@gmail.com>
-Date: Fri, 9 Mar 2018 01:53:35 +0100
-Subject: [PATCH 345/454] drm/vc4: Check if plane requires background fill
-
-commit 3d67b68a6a3c2deb689c29759a20150c668c286e upstream.
-
-Considering a single plane only, we have to enable background color
-when the plane has an alpha format and could be blending from the
-background or when it doesn't cover the entire screen.
-
-Changes from v1:
- - Drop unrelated change
- - Move needs_bg_fill to plane state
-
-Signed-off-by: Stefan Schake <stschake@gmail.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/1520556817-97297-3-git-send-email-stschake@gmail.com
----
- drivers/gpu/drm/vc4/vc4_plane.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -73,6 +73,12 @@ struct vc4_plane_state {
- 
- 	/* Our allocation in LBM for temporary storage during scaling. */
- 	struct drm_mm_node lbm;
-+
-+	/* Set when the plane has per-pixel alpha content or does not cover
-+	 * the entire screen. This is a hint to the CRTC that it might need
-+	 * to enable background color fill.
-+	 */
-+	bool needs_bg_fill;
- };
- 
- static inline struct vc4_plane_state *
-@@ -521,6 +527,7 @@ static int vc4_plane_mode_set(struct drm
- 	u32 ctl0_offset = vc4_state->dlist_count;
- 	const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
- 	int num_planes = drm_format_num_planes(format->drm);
-+	bool covers_screen;
- 	u32 scl0, scl1, pitch0;
- 	u32 lbm_size, tiling;
- 	unsigned long irqflags;
-@@ -704,6 +711,16 @@ static int vc4_plane_mode_set(struct drm
- 	vc4_state->dlist[ctl0_offset] |=
- 		VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
- 
-+	/* crtc_* are already clipped coordinates. */
-+	covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
-+			vc4_state->crtc_w == state->crtc->mode.hdisplay &&
-+			vc4_state->crtc_h == state->crtc->mode.vdisplay;
-+	/* Background fill might be necessary when the plane has per-pixel
-+	 * alpha content and blends from the background or does not cover
-+	 * the entire screen.
-+	 */
-+	vc4_state->needs_bg_fill = format->has_alpha || !covers_screen;
-+
- 	return 0;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0346-drm-vc4-Move-plane-state-to-header.patch b/target/linux/brcm2708/patches-4.14/950-0346-drm-vc4-Move-plane-state-to-header.patch
deleted file mode 100644
index 9ca1eb212..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0346-drm-vc4-Move-plane-state-to-header.patch
+++ /dev/null
@@ -1,157 +0,0 @@
-From 3747cef056a2b6def75521dc2fd9157b009715e2 Mon Sep 17 00:00:00 2001
-From: Stefan Schake <stschake@gmail.com>
-Date: Fri, 9 Mar 2018 01:53:36 +0100
-Subject: [PATCH 346/454] drm/vc4: Move plane state to header
-
-commit 823646983b5a31732ae82ffa60b74555857eb8a0 upstream.
-
-We need to reference it from the CRTC to make a decision for enabling
-background color fill.
-
-Signed-off-by: Stefan Schake <stschake@gmail.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/1520556817-97297-4-git-send-email-stschake@gmail.com
----
- drivers/gpu/drm/vc4/vc4_drv.h   | 60 +++++++++++++++++++++++++++++++++
- drivers/gpu/drm/vc4/vc4_plane.c | 60 ---------------------------------
- 2 files changed, 60 insertions(+), 60 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_drv.h
-+++ b/drivers/gpu/drm/vc4/vc4_drv.h
-@@ -278,6 +278,66 @@ to_vc4_plane(struct drm_plane *plane)
- 	return (struct vc4_plane *)plane;
- }
- 
-+enum vc4_scaling_mode {
-+	VC4_SCALING_NONE,
-+	VC4_SCALING_TPZ,
-+	VC4_SCALING_PPF,
-+};
-+
-+struct vc4_plane_state {
-+	struct drm_plane_state base;
-+	/* System memory copy of the display list for this element, computed
-+	 * at atomic_check time.
-+	 */
-+	u32 *dlist;
-+	u32 dlist_size; /* Number of dwords allocated for the display list */
-+	u32 dlist_count; /* Number of used dwords in the display list. */
-+
-+	/* Offset in the dlist to various words, for pageflip or
-+	 * cursor updates.
-+	 */
-+	u32 pos0_offset;
-+	u32 pos2_offset;
-+	u32 ptr0_offset;
-+
-+	/* Offset where the plane's dlist was last stored in the
-+	 * hardware at vc4_crtc_atomic_flush() time.
-+	 */
-+	u32 __iomem *hw_dlist;
-+
-+	/* Clipped coordinates of the plane on the display. */
-+	int crtc_x, crtc_y, crtc_w, crtc_h;
-+	/* Clipped area being scanned from in the FB. */
-+	u32 src_x, src_y;
-+
-+	u32 src_w[2], src_h[2];
-+
-+	/* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
-+	enum vc4_scaling_mode x_scaling[2], y_scaling[2];
-+	bool is_unity;
-+	bool is_yuv;
-+
-+	/* Offset to start scanning out from the start of the plane's
-+	 * BO.
-+	 */
-+	u32 offsets[3];
-+
-+	/* Our allocation in LBM for temporary storage during scaling. */
-+	struct drm_mm_node lbm;
-+
-+	/* Set when the plane has per-pixel alpha content or does not cover
-+	 * the entire screen. This is a hint to the CRTC that it might need
-+	 * to enable background color fill.
-+	 */
-+	bool needs_bg_fill;
-+};
-+
-+static inline struct vc4_plane_state *
-+to_vc4_plane_state(struct drm_plane_state *state)
-+{
-+	return (struct vc4_plane_state *)state;
-+}
-+
- enum vc4_encoder_type {
- 	VC4_ENCODER_TYPE_NONE,
- 	VC4_ENCODER_TYPE_HDMI,
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -27,66 +27,6 @@
- #include "vc4_drv.h"
- #include "vc4_regs.h"
- 
--enum vc4_scaling_mode {
--	VC4_SCALING_NONE,
--	VC4_SCALING_TPZ,
--	VC4_SCALING_PPF,
--};
--
--struct vc4_plane_state {
--	struct drm_plane_state base;
--	/* System memory copy of the display list for this element, computed
--	 * at atomic_check time.
--	 */
--	u32 *dlist;
--	u32 dlist_size; /* Number of dwords allocated for the display list */
--	u32 dlist_count; /* Number of used dwords in the display list. */
--
--	/* Offset in the dlist to various words, for pageflip or
--	 * cursor updates.
--	 */
--	u32 pos0_offset;
--	u32 pos2_offset;
--	u32 ptr0_offset;
--
--	/* Offset where the plane's dlist was last stored in the
--	 * hardware at vc4_crtc_atomic_flush() time.
--	 */
--	u32 __iomem *hw_dlist;
--
--	/* Clipped coordinates of the plane on the display. */
--	int crtc_x, crtc_y, crtc_w, crtc_h;
--	/* Clipped area being scanned from in the FB. */
--	u32 src_x, src_y;
--
--	u32 src_w[2], src_h[2];
--
--	/* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
--	enum vc4_scaling_mode x_scaling[2], y_scaling[2];
--	bool is_unity;
--	bool is_yuv;
--
--	/* Offset to start scanning out from the start of the plane's
--	 * BO.
--	 */
--	u32 offsets[3];
--
--	/* Our allocation in LBM for temporary storage during scaling. */
--	struct drm_mm_node lbm;
--
--	/* Set when the plane has per-pixel alpha content or does not cover
--	 * the entire screen. This is a hint to the CRTC that it might need
--	 * to enable background color fill.
--	 */
--	bool needs_bg_fill;
--};
--
--static inline struct vc4_plane_state *
--to_vc4_plane_state(struct drm_plane_state *state)
--{
--	return (struct vc4_plane_state *)state;
--}
--
- static const struct hvs_format {
- 	u32 drm; /* DRM_FORMAT_* */
- 	u32 hvs; /* HVS_FORMAT_* */
diff --git a/target/linux/brcm2708/patches-4.14/950-0347-drm-vc4-Enable-background-color-fill-when-necessary.patch b/target/linux/brcm2708/patches-4.14/950-0347-drm-vc4-Enable-background-color-fill-when-necessary.patch
deleted file mode 100644
index 5598a4619..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0347-drm-vc4-Enable-background-color-fill-when-necessary.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 6510ecc6c76d040cc5a84f7464b5f327f2c556e9 Mon Sep 17 00:00:00 2001
-From: Stefan Schake <stschake@gmail.com>
-Date: Fri, 9 Mar 2018 01:53:37 +0100
-Subject: [PATCH 347/454] drm/vc4: Enable background color fill when necessary
-
-commit 1d49f2e546a5a3258a88f85a1c04fd6feb6def37 upstream.
-
-Using the hint from the plane state, we turn on the background color
-to avoid display corruption from planes blending with the background.
-
-Changes from v1:
- - Use needs_bg_fill from plane state
-
-Signed-off-by: Stefan Schake <stschake@gmail.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/msgid/1520556817-97297-5-git-send-email-stschake@gmail.com
----
- drivers/gpu/drm/vc4/vc4_crtc.c | 25 +++++++++++++++++++++++++
- 1 file changed, 25 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_crtc.c
-+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
-@@ -646,9 +646,12 @@ static void vc4_crtc_atomic_flush(struct
- {
- 	struct drm_device *dev = crtc->dev;
- 	struct vc4_dev *vc4 = to_vc4_dev(dev);
-+	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
- 	struct drm_plane *plane;
-+	struct vc4_plane_state *vc4_plane_state;
- 	bool debug_dump_regs = false;
-+	bool enable_bg_fill = false;
- 	u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
- 	u32 __iomem *dlist_next = dlist_start;
- 
-@@ -659,6 +662,20 @@ static void vc4_crtc_atomic_flush(struct
- 
- 	/* Copy all the active planes' dlist contents to the hardware dlist. */
- 	drm_atomic_crtc_for_each_plane(plane, crtc) {
-+		/* Is this the first active plane? */
-+		if (dlist_next == dlist_start) {
-+			/* We need to enable background fill when a plane
-+			 * could be alpha blending from the background, i.e.
-+			 * where no other plane is underneath. It suffices to
-+			 * consider the first active plane here since we set
-+			 * needs_bg_fill such that either the first plane
-+			 * already needs it or all planes on top blend from
-+			 * the first or a lower plane.
-+			 */
-+			vc4_plane_state = to_vc4_plane_state(plane->state);
-+			enable_bg_fill = vc4_plane_state->needs_bg_fill;
-+		}
-+
- 		dlist_next += vc4_plane_write_dlist(plane, dlist_next);
- 	}
- 
-@@ -667,6 +684,14 @@ static void vc4_crtc_atomic_flush(struct
- 
- 	WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
- 
-+	if (enable_bg_fill)
-+		/* This sets a black background color fill, as is the case
-+		 * with other DRM drivers.
-+		 */
-+		HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
-+			  HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
-+			  SCALER_DISPBKGND_FILL);
-+
- 	/* Only update DISPLIST if the CRTC was already running and is not
- 	 * being disabled.
- 	 * vc4_crtc_enable() takes care of updating the dlist just after
diff --git a/target/linux/brcm2708/patches-4.14/950-0348-overlays-Add-addr-parameter-to-i2c-rtc-gpio.patch b/target/linux/brcm2708/patches-4.14/950-0348-overlays-Add-addr-parameter-to-i2c-rtc-gpio.patch
deleted file mode 100644
index 4f33e2837..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0348-overlays-Add-addr-parameter-to-i2c-rtc-gpio.patch
+++ /dev/null
@@ -1,111 +0,0 @@
-From 454ca715ff9f88c4e02ac892f196da8a1d90d052 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 9 Jul 2018 21:11:32 +0100
-Subject: [PATCH 348/454] overlays: Add addr parameter to i2c-rtc (& -gpio)
-
-See: https://github.com/raspberrypi/linux/issues/2611
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README             | 10 +++++++
- .../dts/overlays/i2c-rtc-gpio-overlay.dts     | 28 +++++++++++++++++++
- .../arm/boot/dts/overlays/i2c-rtc-overlay.dts | 11 ++++++++
- 3 files changed, 49 insertions(+)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -826,6 +826,10 @@ Params: abx80x                  Select o
- 
-         pcf8563                 Select the PCF8563 device
- 
-+        addr                    Sets the address for the RTC. Note that the
-+                                device must be configured to use the specified
-+                                address.
-+
-         trickle-diode-type      Diode type for trickle charge - "standard" or
-                                 "schottky" (ABx80x only)
- 
-@@ -850,6 +854,8 @@ Params: abx80x                  Select o
- 
-         ds3231                  Select the DS3231 device
- 
-+        m41t62                  Select the M41T62 device
-+
-         mcp7940x                Select the MCP7940x device
- 
-         mcp7941x                Select the MCP7941x device
-@@ -860,6 +866,10 @@ Params: abx80x                  Select o
- 
-         pcf8563                 Select the PCF8563 device
- 
-+        addr                    Sets the address for the RTC. Note that the
-+                                device must be configured to use the specified
-+                                address.
-+
-         trickle-diode-type      Diode type for trickle charge - "standard" or
-                                 "schottky" (ABx80x only)
- 
---- a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts
-@@ -159,6 +159,21 @@
- 		};
- 	};
- 
-+	fragment@10 {
-+		target = <&i2c_arm>;
-+		__dormant__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			m41t62: m41t62@68 {
-+				compatible = "st,m41t62";
-+				reg = <0x68>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
- 	__overrides__ {
- 		abx80x = <0>,"+1";
- 		ds1307 = <0>,"+2";
-@@ -169,6 +184,19 @@
- 		pcf2127 = <0>,"+7";
- 		pcf8523 = <0>,"+8";
- 		pcf8563 = <0>,"+9";
-+		m41t62 = <0>,"+10";
-+
-+		addr = <&abx80x>, "reg:0",
-+		       <&ds1307>, "reg:0",
-+		       <&ds1339>, "reg:0",
-+		       <&ds3231>, "reg:0",
-+		       <&mcp7940x>, "reg:0",
-+		       <&mcp7941x>, "reg:0",
-+		       <&pcf2127>, "reg:0",
-+		       <&pcf8523>, "reg:0",
-+		       <&pcf8563>, "reg:0",
-+		       <&m41t62>, "reg:0";
-+
- 		trickle-diode-type = <&abx80x>,"abracon,tc-diode";
- 		trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0",
- 					<&abx80x>,"abracon,tc-resistor";
---- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts
-@@ -169,6 +169,17 @@
- 		pcf8523 = <0>,"+7";
- 		pcf8563 = <0>,"+8";
- 		m41t62 = <0>,"+9";
-+
-+		addr = <&abx80x>, "reg:0",
-+		       <&ds1307>, "reg:0",
-+		       <&ds1339>, "reg:0",
-+		       <&ds3231>, "reg:0",
-+		       <&mcp7940x>, "reg:0",
-+		       <&mcp7941x>, "reg:0",
-+		       <&pcf2127>, "reg:0",
-+		       <&pcf8523>, "reg:0",
-+		       <&pcf8563>, "reg:0",
-+		       <&m41t62>, "reg:0";
- 		trickle-diode-type = <&abx80x>,"abracon,tc-diode";
- 		trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0",
- 					<&abx80x>,"abracon,tc-resistor";
diff --git a/target/linux/brcm2708/patches-4.14/950-0349-drm-vc4-Fix-oops-dereferencing-DPI-s-connector-since.patch b/target/linux/brcm2708/patches-4.14/950-0349-drm-vc4-Fix-oops-dereferencing-DPI-s-connector-since.patch
deleted file mode 100644
index 00585a983..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0349-drm-vc4-Fix-oops-dereferencing-DPI-s-connector-since.patch
+++ /dev/null
@@ -1,78 +0,0 @@
-From 2e4ad74553a929623fd09b2baf2ac73bc4adcd80 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Fri, 9 Mar 2018 15:32:56 -0800
-Subject: [PATCH 349/454] drm/vc4: Fix oops dereferencing DPI's connector since
- panel_bridge.
-
-In the cleanup, I didn't notice that we needed to dereference the
-connector for the bus_format.  Fix the regression by looking up the
-first (and only) connector attached to us, and assume that its
-bus_format is what we want.  Some day it would be good to have that
-part of display_info attached to the bridge, instead.
-
-v2: Fix stray whitespace change
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Fixes: 7b1298e05310 ("drm/vc4: Switch DPI to using the panel-bridge helper.")
-Link: https://patchwork.freedesktop.org/patch/msgid/20180309233256.1667-1-eric@anholt.net
-Reviewed-by: Sean Paul <seanpaul@chromium.org>
-Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
-(cherry picked from commit 721fe38db2010e8d475abf2c1d2bafb6dc031741)
----
- drivers/gpu/drm/vc4/vc4_dpi.c | 25 ++++++++++++++++++++++---
- 1 file changed, 22 insertions(+), 3 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_dpi.c
-+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
-@@ -96,7 +96,6 @@ struct vc4_dpi {
- 	struct platform_device *pdev;
- 
- 	struct drm_encoder *encoder;
--	struct drm_connector *connector;
- 	struct drm_bridge *bridge;
- 	bool is_panel_bridge;
- 
-@@ -166,14 +165,31 @@ static void vc4_dpi_encoder_disable(stru
- 
- static void vc4_dpi_encoder_enable(struct drm_encoder *encoder)
- {
-+	struct drm_device *dev = encoder->dev;
- 	struct drm_display_mode *mode = &encoder->crtc->mode;
- 	struct vc4_dpi_encoder *vc4_encoder = to_vc4_dpi_encoder(encoder);
- 	struct vc4_dpi *dpi = vc4_encoder->dpi;
-+	struct drm_connector_list_iter conn_iter;
-+	struct drm_connector *connector = NULL, *connector_scan;
- 	u32 dpi_c = DPI_ENABLE | DPI_OUTPUT_ENABLE_MODE;
- 	int ret;
- 
--	if (dpi->connector->display_info.num_bus_formats) {
--		u32 bus_format = dpi->connector->display_info.bus_formats[0];
-+	/* Look up the connector attached to DPI so we can get the
-+	 * bus_format.  Ideally the bridge would tell us the
-+	 * bus_format we want, but it doesn't yet, so assume that it's
-+	 * uniform throughout the bridge chain.
-+	 */
-+	drm_connector_list_iter_begin(dev, &conn_iter);
-+	drm_for_each_connector_iter(connector_scan, &conn_iter) {
-+		if (connector_scan->encoder == encoder) {
-+			connector = connector_scan;
-+			break;
-+		}
-+	}
-+	drm_connector_list_iter_end(&conn_iter);
-+
-+	if (connector && connector->display_info.num_bus_formats) {
-+		u32 bus_format = connector->display_info.bus_formats[0];
- 
- 		switch (bus_format) {
- 		case MEDIA_BUS_FMT_RGB888_1X24:
-@@ -201,6 +217,9 @@ static void vc4_dpi_encoder_enable(struc
- 			DRM_ERROR("Unknown media bus format %d\n", bus_format);
- 			break;
- 		}
-+	} else {
-+		/* Default to 24bit if no connector found. */
-+		dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT);
- 	}
- 
- 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
diff --git a/target/linux/brcm2708/patches-4.14/950-0350-ARM-bcm2835-Add-the-DPI-hardware-to-the-device-tree.patch b/target/linux/brcm2708/patches-4.14/950-0350-ARM-bcm2835-Add-the-DPI-hardware-to-the-device-tree.patch
deleted file mode 100644
index 367c6d149..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0350-ARM-bcm2835-Add-the-DPI-hardware-to-the-device-tree.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 0a441eef40f3dc8eef2f5a57d0a053de2226cb3a Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 10 Feb 2016 11:31:52 -0800
-Subject: [PATCH 350/454] ARM: bcm2835: Add the DPI hardware to the device
- tree.
-
-It's currently marked disabled, as it's not useful without a panel
-associated with it and the GPIO pins routed to ALT2.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- arch/arm/boot/dts/bcm283x.dtsi | 11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/arch/arm/boot/dts/bcm283x.dtsi
-+++ b/arch/arm/boot/dts/bcm283x.dtsi
-@@ -438,6 +438,17 @@
- 			interrupts = <2 14>; /* pwa1 */
- 		};
- 
-+		dpi: dpi@7e208000 {
-+			compatible = "brcm,bcm2835-dpi";
-+			reg = <0x7e208000 0x8c>;
-+			clocks = <&clocks BCM2835_CLOCK_VPU>,
-+				 <&clocks BCM2835_CLOCK_DPI>;
-+			clock-names = "core", "pixel";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+		};
-+
- 		dsi0: dsi@7e209000 {
- 			compatible = "brcm,bcm2835-dsi0";
- 			reg = <0x7e209000 0x78>;
diff --git a/target/linux/brcm2708/patches-4.14/950-0351-ARM-BCM270X-Add-the-18-bit-DPI-pinmux-to-the-RPI-DTs.patch b/target/linux/brcm2708/patches-4.14/950-0351-ARM-BCM270X-Add-the-18-bit-DPI-pinmux-to-the-RPI-DTs.patch
deleted file mode 100644
index 280ef0a8d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0351-ARM-BCM270X-Add-the-18-bit-DPI-pinmux-to-the-RPI-DTs.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From e26cf70d54a58a3a1666996374720099ba45ed72 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Fri, 9 Mar 2018 14:24:05 -0800
-Subject: [PATCH 351/454] ARM: BCM270X: Add the 18-bit DPI pinmux to the RPI
- DTs.
-
-This doesn't do anything by default, but trying to put the node in an
-overlay failed for me.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- arch/arm/boot/dts/bcm270x.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm/boot/dts/bcm270x.dtsi
-+++ b/arch/arm/boot/dts/bcm270x.dtsi
-@@ -19,6 +19,13 @@
- 
- 		gpio@7e200000 { /* gpio */
- 			interrupts = <2 17>, <2 18>;
-+
-+			dpi_18bit_gpio0: dpi_18bit_gpio0 {
-+				brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
-+					     12 13 14 15 16 17 18 19
-+					     20 21>;
-+				brcm,function = <BCM2835_FSEL_ALT2>;
-+			};
- 		};
- 
- 		serial@7e201000 { /* uart0 */
diff --git a/target/linux/brcm2708/patches-4.14/950-0352-overlays-Add-an-overlay-for-the-Adafruit-Kippah-with.patch b/target/linux/brcm2708/patches-4.14/950-0352-overlays-Add-an-overlay-for-the-Adafruit-Kippah-with.patch
deleted file mode 100644
index d6273bb8e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0352-overlays-Add-an-overlay-for-the-Adafruit-Kippah-with.patch
+++ /dev/null
@@ -1,85 +0,0 @@
-From 62da6ec26e4e73c553dfadcd962b583af9975a39 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Fri, 9 Mar 2018 13:20:21 -0800
-Subject: [PATCH 352/454] overlays: Add an overlay for the Adafruit Kippah with
- their 7" panel
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  6 +++
- .../overlays/vc4-kms-kippah-7inch-overlay.dts | 43 +++++++++++++++++++
- 3 files changed, 50 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -137,6 +137,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	upstream.dtbo \
- 	upstream-aux-interrupt.dtbo \
- 	vc4-fkms-v3d.dtbo \
-+	vc4-kms-kippah-7inch.dtbo \
- 	vc4-kms-v3d.dtbo \
- 	vga666.dtbo \
- 	w1-gpio.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1977,6 +1977,12 @@ Params: cma-256                 CMA is 2
-         cma-64                  CMA is 64MB, 64MB-aligned
- 
- 
-+Name:   vc4-kms-kippah-7inch
-+Info:   Enable the Adafruit DPI Kippah with the 7" Ontat panel attached.
-+        Requires vc4-kms-v3d to be loaded.
-+Load:   dtoverlay=vc4-kms-kippah-7inch
-+
-+
- Name:   vga666
- Info:   Overlay for the Fen Logic VGA666 board
-         This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts
-@@ -0,0 +1,43 @@
-+/*
-+ * vc4-kms-v3d-overlay.dts
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+#include <dt-bindings/pinctrl/bcm2835.h>
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			panel: panel {
-+				compatible = "ontat,yx700wv03", "simple-panel";
-+
-+				port {
-+					panel_in: endpoint {
-+						remote-endpoint = <&dpi_out>;
-+					};
-+				};
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&dpi>;
-+		__overlay__  {
-+			status = "okay";
-+
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&dpi_18bit_gpio0>;
-+
-+			port {
-+				dpi_out: endpoint@0 {
-+					remote-endpoint = <&panel_in>;
-+				};
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0353-overlays-Remove-stale-notes-about-vc4-s-CMA-alignmen.patch b/target/linux/brcm2708/patches-4.14/950-0353-overlays-Remove-stale-notes-about-vc4-s-CMA-alignmen.patch
deleted file mode 100644
index 20e407814..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0353-overlays-Remove-stale-notes-about-vc4-s-CMA-alignmen.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 1ee09b8c520f7e3cab8c417f18e89e89774662ea Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Fri, 9 Mar 2018 13:26:33 -0800
-Subject: [PATCH 353/454] overlays: Remove stale notes about vc4's CMA
- alignment in the README.
-
-We haven't needed alignment since
-553c942f8b2cbc7394b4d4fa2f848b23a8f07451, and the current overlays
-don't specify any.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
- arch/arm/boot/dts/overlays/README | 20 ++++++++++----------
- 1 file changed, 10 insertions(+), 10 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1958,11 +1958,11 @@ Name:   vc4-fkms-v3d
- Info:   Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx
-         display stack.
- Load:   dtoverlay=vc4-fkms-v3d,<param>
--Params: cma-256                 CMA is 256MB, 256MB-aligned (needs 1GB)
--        cma-192                 CMA is 192MB, 256MB-aligned (needs 1GB)
--        cma-128                 CMA is 128MB, 128MB-aligned
--        cma-96                  CMA is 96MB, 128MB-aligned
--        cma-64                  CMA is 64MB, 64MB-aligned
-+Params: cma-256                 CMA is 256MB (needs 1GB)
-+        cma-192                 CMA is 192MB (needs 1GB)
-+        cma-128                 CMA is 128MB
-+        cma-96                  CMA is 96MB
-+        cma-64                  CMA is 64MB
- 
- 
- Name:   vc4-kms-v3d
-@@ -1970,11 +1970,11 @@ Info:   Enable Eric Anholt's DRM VC4 HDM
-         booting to GUI while this overlay is in use will cause interesting
-         lockups.
- Load:   dtoverlay=vc4-kms-v3d,<param>
--Params: cma-256                 CMA is 256MB, 256MB-aligned (needs 1GB)
--        cma-192                 CMA is 192MB, 256MB-aligned (needs 1GB)
--        cma-128                 CMA is 128MB, 128MB-aligned
--        cma-96                  CMA is 96MB, 128MB-aligned
--        cma-64                  CMA is 64MB, 64MB-aligned
-+Params: cma-256                 CMA is 256MB (needs 1GB)
-+        cma-192                 CMA is 192MB (needs 1GB)
-+        cma-128                 CMA is 128MB
-+        cma-96                  CMA is 96MB
-+        cma-64                  CMA is 64MB
- 
- 
- Name:   vc4-kms-kippah-7inch
diff --git a/target/linux/brcm2708/patches-4.14/950-0354-drm-vc4-Advertise-supported-modifiers-for-planes.patch b/target/linux/brcm2708/patches-4.14/950-0354-drm-vc4-Advertise-supported-modifiers-for-planes.patch
deleted file mode 100644
index 5bbb0576e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0354-drm-vc4-Advertise-supported-modifiers-for-planes.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From cc6f4a74861a987e8d95aa36f2d141c777e30425 Mon Sep 17 00:00:00 2001
-From: Daniel Stone <daniels@collabora.com>
-Date: Tue, 8 Aug 2017 17:44:48 +0100
-Subject: [PATCH 354/454] drm/vc4: Advertise supported modifiers for planes
-
-The IN_FORMATS blob allows the kernel to advertise to userspace which
-format/modifier combinations are supported, per plane. Use this to
-advertise that we support both T_TILED and linear.
-
-v2:
-  - Only advertise T_TILED for RGB (Eric)
-  - Actually turn on allow_fb_modifiers (Eric)
-
-Signed-off-by: Daniel Stone <daniels@collabora.com>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Link: https://patchwork.freedesktop.org/patch/170828/
-(cherry picked from commit 423ad7b3cbd1158d080e20119a7a5f93a085a486)
----
- drivers/gpu/drm/vc4/vc4_kms.c   |  1 +
- drivers/gpu/drm/vc4/vc4_plane.c | 34 ++++++++++++++++++++++++++++++++-
- 2 files changed, 34 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/vc4/vc4_kms.c
-+++ b/drivers/gpu/drm/vc4/vc4_kms.c
-@@ -222,6 +222,7 @@ int vc4_kms_load(struct drm_device *dev)
- 	dev->mode_config.funcs = &vc4_mode_funcs;
- 	dev->mode_config.preferred_depth = 24;
- 	dev->mode_config.async_page_flip = true;
-+	dev->mode_config.allow_fb_modifiers = true;
- 
- 	drm_mode_config_reset(dev);
- 
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -867,6 +867,32 @@ out:
- 					      ctx);
- }
- 
-+static bool vc4_format_mod_supported(struct drm_plane *plane,
-+				     uint32_t format,
-+				     uint64_t modifier)
-+{
-+	/* Support T_TILING for RGB formats only. */
-+	switch (format) {
-+	case DRM_FORMAT_XRGB8888:
-+	case DRM_FORMAT_ARGB8888:
-+	case DRM_FORMAT_ABGR8888:
-+	case DRM_FORMAT_XBGR8888:
-+	case DRM_FORMAT_RGB565:
-+	case DRM_FORMAT_BGR565:
-+	case DRM_FORMAT_ARGB1555:
-+	case DRM_FORMAT_XRGB1555:
-+		return true;
-+	case DRM_FORMAT_YUV422:
-+	case DRM_FORMAT_YVU422:
-+	case DRM_FORMAT_YUV420:
-+	case DRM_FORMAT_YVU420:
-+	case DRM_FORMAT_NV12:
-+	case DRM_FORMAT_NV16:
-+	default:
-+		return (modifier == DRM_FORMAT_MOD_LINEAR);
-+	}
-+}
-+
- static const struct drm_plane_funcs vc4_plane_funcs = {
- 	.update_plane = vc4_update_plane,
- 	.disable_plane = drm_atomic_helper_disable_plane,
-@@ -875,6 +901,7 @@ static const struct drm_plane_funcs vc4_
- 	.reset = vc4_plane_reset,
- 	.atomic_duplicate_state = vc4_plane_duplicate_state,
- 	.atomic_destroy_state = vc4_plane_destroy_state,
-+	.format_mod_supported = vc4_format_mod_supported,
- };
- 
- struct drm_plane *vc4_plane_init(struct drm_device *dev,
-@@ -886,6 +913,11 @@ struct drm_plane *vc4_plane_init(struct
- 	u32 num_formats = 0;
- 	int ret = 0;
- 	unsigned i;
-+	static const uint64_t modifiers[] = {
-+		DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
-+		DRM_FORMAT_MOD_LINEAR,
-+		DRM_FORMAT_MOD_INVALID
-+	};
- 
- 	vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
- 				 GFP_KERNEL);
-@@ -906,7 +938,7 @@ struct drm_plane *vc4_plane_init(struct
- 	ret = drm_universal_plane_init(dev, plane, 0,
- 				       &vc4_plane_funcs,
- 				       formats, num_formats,
--				       NULL, type, NULL);
-+				       modifiers, type, NULL);
- 
- 	drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0355-drm-vc4-Add-some-missing-HVS-register-definitions.patch b/target/linux/brcm2708/patches-4.14/950-0355-drm-vc4-Add-some-missing-HVS-register-definitions.patch
deleted file mode 100644
index d86b23e86..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0355-drm-vc4-Add-some-missing-HVS-register-definitions.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-From a40aa2492372d46688fc6952c13f38e57ae51a6b Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Wed, 11 Apr 2018 22:49:12 +0200
-Subject: [PATCH 355/454] drm/vc4: Add some missing HVS register definitions.
-
-At least the RGBA expand field we should have been setting, because we
-aren't expanding correctly for 565 -> 8888.  Other registers are ones
-that may be interesting for various projects that have been discussed.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Acked-by: Stefan Schake <stschake@gmail.com>
-Link: https://patchwork.freedesktop.org/patch/msgid/1523479755-20812-2-git-send-email-stschake@gmail.com
-(cherry picked from commit aa808440426f6d163a4f51076132628fee6e1e7d)
----
- drivers/gpu/drm/vc4/vc4_regs.h | 96 ++++++++++++++++++++++++++++++++++
- 1 file changed, 96 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_regs.h
-+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -359,6 +359,21 @@
- #define SCALER_DISPCTRL0                        0x00000040
- # define SCALER_DISPCTRLX_ENABLE		BIT(31)
- # define SCALER_DISPCTRLX_RESET			BIT(30)
-+/* Generates a single frame when VSTART is seen and stops at the last
-+ * pixel read from the FIFO.
-+ */
-+# define SCALER_DISPCTRLX_ONESHOT		BIT(29)
-+/* Processes a single context in the dlist and then task switch,
-+ * instead of an entire line.
-+ */
-+# define SCALER_DISPCTRLX_ONECTX		BIT(28)
-+/* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
-+# define SCALER_DISPCTRLX_FIFO32		BIT(27)
-+/* Turns on output to the DISPSLAVE register instead of the normal
-+ * FIFO.
-+ */
-+# define SCALER_DISPCTRLX_FIFOREG		BIT(26)
-+
- # define SCALER_DISPCTRLX_WIDTH_MASK		VC4_MASK(23, 12)
- # define SCALER_DISPCTRLX_WIDTH_SHIFT		12
- # define SCALER_DISPCTRLX_HEIGHT_MASK		VC4_MASK(11, 0)
-@@ -431,6 +446,68 @@
-  */
- # define SCALER_GAMADDR_SRAMENB			BIT(30)
- 
-+#define SCALER_OLEDOFFS                         0x00000080
-+/* Clamps R to [16,235] and G/B to [16,240]. */
-+# define SCALER_OLEDOFFS_YUVCLAMP               BIT(31)
-+
-+/* Chooses which display FIFO the matrix applies to. */
-+# define SCALER_OLEDOFFS_DISPFIFO_MASK          VC4_MASK(25, 24)
-+# define SCALER_OLEDOFFS_DISPFIFO_SHIFT         24
-+# define SCALER_OLEDOFFS_DISPFIFO_DISABLED      0
-+# define SCALER_OLEDOFFS_DISPFIFO_0             1
-+# define SCALER_OLEDOFFS_DISPFIFO_1             2
-+# define SCALER_OLEDOFFS_DISPFIFO_2             3
-+
-+/* Offsets are 8-bit 2s-complement. */
-+# define SCALER_OLEDOFFS_RED_MASK               VC4_MASK(23, 16)
-+# define SCALER_OLEDOFFS_RED_SHIFT              16
-+# define SCALER_OLEDOFFS_GREEN_MASK             VC4_MASK(15, 8)
-+# define SCALER_OLEDOFFS_GREEN_SHIFT            8
-+# define SCALER_OLEDOFFS_BLUE_MASK              VC4_MASK(7, 0)
-+# define SCALER_OLEDOFFS_BLUE_SHIFT             0
-+
-+/* The coefficients are S0.9 fractions. */
-+#define SCALER_OLEDCOEF0                        0x00000084
-+# define SCALER_OLEDCOEF0_B_TO_R_MASK           VC4_MASK(29, 20)
-+# define SCALER_OLEDCOEF0_B_TO_R_SHIFT          20
-+# define SCALER_OLEDCOEF0_B_TO_G_MASK           VC4_MASK(19, 10)
-+# define SCALER_OLEDCOEF0_B_TO_G_SHIFT          10
-+# define SCALER_OLEDCOEF0_B_TO_B_MASK           VC4_MASK(9, 0)
-+# define SCALER_OLEDCOEF0_B_TO_B_SHIFT          0
-+
-+#define SCALER_OLEDCOEF1                        0x00000088
-+# define SCALER_OLEDCOEF1_G_TO_R_MASK           VC4_MASK(29, 20)
-+# define SCALER_OLEDCOEF1_G_TO_R_SHIFT          20
-+# define SCALER_OLEDCOEF1_G_TO_G_MASK           VC4_MASK(19, 10)
-+# define SCALER_OLEDCOEF1_G_TO_G_SHIFT          10
-+# define SCALER_OLEDCOEF1_G_TO_B_MASK           VC4_MASK(9, 0)
-+# define SCALER_OLEDCOEF1_G_TO_B_SHIFT          0
-+
-+#define SCALER_OLEDCOEF2                        0x0000008c
-+# define SCALER_OLEDCOEF2_R_TO_R_MASK           VC4_MASK(29, 20)
-+# define SCALER_OLEDCOEF2_R_TO_R_SHIFT          20
-+# define SCALER_OLEDCOEF2_R_TO_G_MASK           VC4_MASK(19, 10)
-+# define SCALER_OLEDCOEF2_R_TO_G_SHIFT          10
-+# define SCALER_OLEDCOEF2_R_TO_B_MASK           VC4_MASK(9, 0)
-+# define SCALER_OLEDCOEF2_R_TO_B_SHIFT          0
-+
-+/* Slave addresses for DMAing from HVS composition output to other
-+ * devices.  The top bits are valid only in !FIFO32 mode.
-+ */
-+#define SCALER_DISPSLAVE0                       0x000000c0
-+#define SCALER_DISPSLAVE1                       0x000000c9
-+#define SCALER_DISPSLAVE2                       0x000000d0
-+# define SCALER_DISPSLAVE_ISSUE_VSTART          BIT(31)
-+# define SCALER_DISPSLAVE_ISSUE_HSTART          BIT(30)
-+/* Set when the current line has been read and an HSTART is required. */
-+# define SCALER_DISPSLAVE_EOL                   BIT(26)
-+/* Set when the display FIFO is empty. */
-+# define SCALER_DISPSLAVE_EMPTY                 BIT(25)
-+/* Set when there is RGB data ready to read. */
-+# define SCALER_DISPSLAVE_VALID                 BIT(24)
-+# define SCALER_DISPSLAVE_RGB_MASK              VC4_MASK(23, 0)
-+# define SCALER_DISPSLAVE_RGB_SHIFT             0
-+
- #define SCALER_GAMDATA                          0x000000e0
- #define SCALER_DLIST_START                      0x00002000
- #define SCALER_DLIST_SIZE                       0x00004000
-@@ -796,6 +873,10 @@ enum hvs_pixel_format {
- 	HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
- 	HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
- 	HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
-+	HVS_PIXEL_FORMAT_H264 = 12,
-+	HVS_PIXEL_FORMAT_PALETTE = 13,
-+	HVS_PIXEL_FORMAT_YUV444_RGB = 14,
-+	HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
- };
- 
- /* Note: the LSB is the rightmost character shown.  Only valid for
-@@ -829,12 +910,27 @@ enum hvs_pixel_format {
- #define SCALER_CTL0_TILING_128B			2
- #define SCALER_CTL0_TILING_256B_OR_T		3
- 
-+#define SCALER_CTL0_ALPHA_MASK                  BIT(19)
- #define SCALER_CTL0_HFLIP                       BIT(16)
- #define SCALER_CTL0_VFLIP                       BIT(15)
- 
-+#define SCALER_CTL0_KEY_MODE_MASK		VC4_MASK(18, 17)
-+#define SCALER_CTL0_KEY_MODE_SHIFT		17
-+#define SCALER_CTL0_KEY_DISABLED		0
-+#define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB	1
-+#define SCALER_CTL0_KEY_MATCH			2 /* turn transparent */
-+#define SCALER_CTL0_KEY_REPLACE			3 /* replace with value from key mask word 2 */
-+
- #define SCALER_CTL0_ORDER_MASK			VC4_MASK(14, 13)
- #define SCALER_CTL0_ORDER_SHIFT			13
- 
-+#define SCALER_CTL0_RGBA_EXPAND_MASK		VC4_MASK(12, 11)
-+#define SCALER_CTL0_RGBA_EXPAND_SHIFT		11
-+#define SCALER_CTL0_RGBA_EXPAND_ZERO		0
-+#define SCALER_CTL0_RGBA_EXPAND_LSB		1
-+#define SCALER_CTL0_RGBA_EXPAND_MSB		2
-+#define SCALER_CTL0_RGBA_EXPAND_ROUND		3
-+
- #define SCALER_CTL0_SCL1_MASK			VC4_MASK(10, 8)
- #define SCALER_CTL0_SCL1_SHIFT			8
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0356-drm-vc4-Add-missing-formats-to-vc4_format_mod_suppor.patch b/target/linux/brcm2708/patches-4.14/950-0356-drm-vc4-Add-missing-formats-to-vc4_format_mod_suppor.patch
deleted file mode 100644
index bf9f9e265..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0356-drm-vc4-Add-missing-formats-to-vc4_format_mod_suppor.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 0360325765bee2f76e11d42abf8e601320054230 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Fri, 16 Mar 2018 15:04:34 -0700
-Subject: [PATCH 356/454] drm/vc4: Add missing formats to
- vc4_format_mod_supported().
-
-Daniel's format_mod_supported() patch predated Dave's for NV21/61, and
-I didn't catch that when rebasing.  This is a problem since the
-formats are now getting validated before being passed to the driver's
-atomic hooks.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Acked-by: Daniel Stone <daniels@collabora.com>
-Cc: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Fixes: 423ad7b3cbd1 ("drm/vc4: Advertise supported modifiers for planes")
-Link: https://patchwork.freedesktop.org/patch/msgid/20180316220435.31416-2-eric@anholt.net
-(cherry picked from commit 1e871d65e375280757833d9fce91dda71980bdf5)
----
- drivers/gpu/drm/vc4/vc4_plane.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -887,7 +887,9 @@ static bool vc4_format_mod_supported(str
- 	case DRM_FORMAT_YUV420:
- 	case DRM_FORMAT_YVU420:
- 	case DRM_FORMAT_NV12:
-+	case DRM_FORMAT_NV21:
- 	case DRM_FORMAT_NV16:
-+	case DRM_FORMAT_NV61:
- 	default:
- 		return (modifier == DRM_FORMAT_MOD_LINEAR);
- 	}
diff --git a/target/linux/brcm2708/patches-4.14/950-0357-drm-vc4-Add-support-for-SAND-modifier.patch b/target/linux/brcm2708/patches-4.14/950-0357-drm-vc4-Add-support-for-SAND-modifier.patch
deleted file mode 100644
index 3b94f268b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0357-drm-vc4-Add-support-for-SAND-modifier.patch
+++ /dev/null
@@ -1,266 +0,0 @@
-From 7d83a48b50ac24af7763e7ba5304e9a82f37f014 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Fri, 16 Mar 2018 15:04:35 -0700
-Subject: [PATCH 357/454] drm/vc4: Add support for SAND modifier.
-
-This is the format generated by VC4's H.264 engine, and preferred by
-the ISP as well.  By displaying SAND buffers directly, we can avoid
-needing to use the ISP to rewrite the SAND H.264 output to linear
-before display.
-
-This is a joint effort by Dave Stevenson (who wrote the initial patch
-and DRM demo) and Eric Anholt (drm_fourcc.h generalization, safety
-checks, RGBA support).
-
-v2: Make the parameter macro give all of the middle 48 bits (suggested
-    by Daniels).  Fix fourcc_mod_broadcom_mod()'s bits/shift being
-    swapped.  Mark NV12/21 as supported, not YUV420.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Cc: Daniel Vetter <daniel@ffwll.ch>
-Acked-by: Daniel Stone <daniels@collabora.com> (v1)
-Cc: Boris Brezillon <boris.brezillon@bootlin.com>
-Cc: Maxime Ripard <maxime.ripard@bootlin.com>
-Link: https://patchwork.freedesktop.org/patch/msgid/20180316220435.31416-3-eric@anholt.net
-(cherry picked from commit e065a8dd30af703b4794dc740c0825ee12b92efd)
----
- drivers/gpu/drm/vc4/vc4_plane.c | 84 ++++++++++++++++++++++++++++++---
- drivers/gpu/drm/vc4/vc4_regs.h  |  6 +++
- include/uapi/drm/drm_fourcc.h   | 59 +++++++++++++++++++++++
- 3 files changed, 142 insertions(+), 7 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -466,11 +466,13 @@ static int vc4_plane_mode_set(struct drm
- 	struct drm_framebuffer *fb = state->fb;
- 	u32 ctl0_offset = vc4_state->dlist_count;
- 	const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
-+	u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
- 	int num_planes = drm_format_num_planes(format->drm);
- 	bool covers_screen;
- 	u32 scl0, scl1, pitch0;
- 	u32 lbm_size, tiling;
- 	unsigned long irqflags;
-+	u32 hvs_format = format->hvs;
- 	int ret, i;
- 
- 	ret = vc4_plane_setup_clipping_and_scaling(state);
-@@ -510,7 +512,7 @@ static int vc4_plane_mode_set(struct drm
- 		scl1 = vc4_get_scl_field(state, 0);
- 	}
- 
--	switch (fb->modifier) {
-+	switch (base_format_mod) {
- 	case DRM_FORMAT_MOD_LINEAR:
- 		tiling = SCALER_CTL0_TILING_LINEAR;
- 		pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
-@@ -533,6 +535,49 @@ static int vc4_plane_mode_set(struct drm
- 		break;
- 	}
- 
-+	case DRM_FORMAT_MOD_BROADCOM_SAND64:
-+	case DRM_FORMAT_MOD_BROADCOM_SAND128:
-+	case DRM_FORMAT_MOD_BROADCOM_SAND256: {
-+		uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
-+
-+		/* Column-based NV12 or RGBA.
-+		 */
-+		if (fb->format->num_planes > 1) {
-+			if (hvs_format != HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE) {
-+				DRM_DEBUG_KMS("SAND format only valid for NV12/21");
-+				return -EINVAL;
-+			}
-+			hvs_format = HVS_PIXEL_FORMAT_H264;
-+		} else {
-+			if (base_format_mod == DRM_FORMAT_MOD_BROADCOM_SAND256) {
-+				DRM_DEBUG_KMS("SAND256 format only valid for H.264");
-+				return -EINVAL;
-+			}
-+		}
-+
-+		switch (base_format_mod) {
-+		case DRM_FORMAT_MOD_BROADCOM_SAND64:
-+			tiling = SCALER_CTL0_TILING_64B;
-+			break;
-+		case DRM_FORMAT_MOD_BROADCOM_SAND128:
-+			tiling = SCALER_CTL0_TILING_128B;
-+			break;
-+		case DRM_FORMAT_MOD_BROADCOM_SAND256:
-+			tiling = SCALER_CTL0_TILING_256B_OR_T;
-+			break;
-+		default:
-+			break;
-+		}
-+
-+		if (param > SCALER_TILE_HEIGHT_MASK) {
-+			DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
-+			return -EINVAL;
-+		}
-+
-+		pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
-+		break;
-+	}
-+
- 	default:
- 		DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
- 			      (long long)fb->modifier);
-@@ -543,7 +588,7 @@ static int vc4_plane_mode_set(struct drm
- 	vc4_dlist_write(vc4_state,
- 			SCALER_CTL0_VALID |
- 			(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
--			(format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
-+			(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
- 			VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
- 			(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
- 			VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
-@@ -597,8 +642,13 @@ static int vc4_plane_mode_set(struct drm
- 
- 	/* Pitch word 1/2 */
- 	for (i = 1; i < num_planes; i++) {
--		vc4_dlist_write(vc4_state,
--				VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));
-+		if (hvs_format != HVS_PIXEL_FORMAT_H264) {
-+			vc4_dlist_write(vc4_state,
-+					VC4_SET_FIELD(fb->pitches[i],
-+						      SCALER_SRC_PITCH));
-+		} else {
-+			vc4_dlist_write(vc4_state, pitch0);
-+		}
- 	}
- 
- 	/* Colorspace conversion words */
-@@ -881,13 +931,30 @@ static bool vc4_format_mod_supported(str
- 	case DRM_FORMAT_BGR565:
- 	case DRM_FORMAT_ARGB1555:
- 	case DRM_FORMAT_XRGB1555:
--		return true;
-+		switch (fourcc_mod_broadcom_mod(modifier)) {
-+		case DRM_FORMAT_MOD_LINEAR:
-+		case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
-+		case DRM_FORMAT_MOD_BROADCOM_SAND64:
-+		case DRM_FORMAT_MOD_BROADCOM_SAND128:
-+			return true;
-+		default:
-+			return false;
-+		}
-+	case DRM_FORMAT_NV12:
-+	case DRM_FORMAT_NV21:
-+		switch (fourcc_mod_broadcom_mod(modifier)) {
-+		case DRM_FORMAT_MOD_LINEAR:
-+		case DRM_FORMAT_MOD_BROADCOM_SAND64:
-+		case DRM_FORMAT_MOD_BROADCOM_SAND128:
-+		case DRM_FORMAT_MOD_BROADCOM_SAND256:
-+			return true;
-+		default:
-+			return false;
-+		}
- 	case DRM_FORMAT_YUV422:
- 	case DRM_FORMAT_YVU422:
- 	case DRM_FORMAT_YUV420:
- 	case DRM_FORMAT_YVU420:
--	case DRM_FORMAT_NV12:
--	case DRM_FORMAT_NV21:
- 	case DRM_FORMAT_NV16:
- 	case DRM_FORMAT_NV61:
- 	default:
-@@ -917,6 +984,9 @@ struct drm_plane *vc4_plane_init(struct
- 	unsigned i;
- 	static const uint64_t modifiers[] = {
- 		DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
-+		DRM_FORMAT_MOD_BROADCOM_SAND128,
-+		DRM_FORMAT_MOD_BROADCOM_SAND64,
-+		DRM_FORMAT_MOD_BROADCOM_SAND256,
- 		DRM_FORMAT_MOD_LINEAR,
- 		DRM_FORMAT_MOD_INVALID
- 	};
---- a/drivers/gpu/drm/vc4/vc4_regs.h
-+++ b/drivers/gpu/drm/vc4/vc4_regs.h
-@@ -1059,6 +1059,12 @@ enum hvs_pixel_format {
- #define SCALER_SRC_PITCH_MASK			VC4_MASK(15, 0)
- #define SCALER_SRC_PITCH_SHIFT			0
- 
-+/* PITCH0/1/2 fields for tiled (SAND). */
-+#define SCALER_TILE_SKIP_0_MASK			VC4_MASK(18, 16)
-+#define SCALER_TILE_SKIP_0_SHIFT		16
-+#define SCALER_TILE_HEIGHT_MASK			VC4_MASK(15, 0)
-+#define SCALER_TILE_HEIGHT_SHIFT		0
-+
- /* PITCH0 fields for T-tiled. */
- #define SCALER_PITCH0_TILE_WIDTH_L_MASK		VC4_MASK(22, 16)
- #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT	16
---- a/include/uapi/drm/drm_fourcc.h
-+++ b/include/uapi/drm/drm_fourcc.h
-@@ -383,6 +383,23 @@ extern "C" {
- #define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
- 
- /*
-+ * Some Broadcom modifiers take parameters, for example the number of
-+ * vertical lines in the image. Reserve the lower 32 bits for modifier
-+ * type, and the next 24 bits for parameters. Top 8 bits are the
-+ * vendor code.
-+ */
-+#define __fourcc_mod_broadcom_param_shift 8
-+#define __fourcc_mod_broadcom_param_bits 48
-+#define fourcc_mod_broadcom_code(val, params) \
-+	fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
-+#define fourcc_mod_broadcom_param(m) \
-+	((int)(((m) >> __fourcc_mod_broadcom_param_shift) &	\
-+	       ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
-+#define fourcc_mod_broadcom_mod(m) \
-+	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<	\
-+		 __fourcc_mod_broadcom_param_shift))
-+
-+/*
-  * Broadcom VC4 "T" format
-  *
-  * This is the primary layout that the V3D GPU can texture from (it
-@@ -403,6 +420,48 @@ extern "C" {
-  */
- #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
- 
-+/*
-+ * Broadcom SAND format
-+ *
-+ * This is the native format that the H.264 codec block uses.  For VC4
-+ * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
-+ *
-+ * The image can be considered to be split into columns, and the
-+ * columns are placed consecutively into memory.  The width of those
-+ * columns can be either 32, 64, 128, or 256 pixels, but in practice
-+ * only 128 pixel columns are used.
-+ *
-+ * The pitch between the start of each column is set to optimally
-+ * switch between SDRAM banks. This is passed as the number of lines
-+ * of column width in the modifier (we can't use the stride value due
-+ * to various core checks that look at it , so you should set the
-+ * stride to width*cpp).
-+ *
-+ * Note that the column height for this format modifier is the same
-+ * for all of the planes, assuming that each column contains both Y
-+ * and UV.  Some SAND-using hardware stores UV in a separate tiled
-+ * image from Y to reduce the column height, which is not supported
-+ * with these modifiers.
-+ */
-+
-+#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
-+	fourcc_mod_broadcom_code(2, v)
-+#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
-+	fourcc_mod_broadcom_code(3, v)
-+#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
-+	fourcc_mod_broadcom_code(4, v)
-+#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
-+	fourcc_mod_broadcom_code(5, v)
-+
-+#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
-+	DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
-+#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
-+	DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
-+#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
-+	DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
-+#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
-+	DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
-+
- #if defined(__cplusplus)
- }
- #endif
diff --git a/target/linux/brcm2708/patches-4.14/950-0358-spi-Make-GPIO-CSs-honour-the-SPI_NO_CS-flag.patch b/target/linux/brcm2708/patches-4.14/950-0358-spi-Make-GPIO-CSs-honour-the-SPI_NO_CS-flag.patch
deleted file mode 100644
index 717c05b67..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0358-spi-Make-GPIO-CSs-honour-the-SPI_NO_CS-flag.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 02554ec274e6b76eb827f384c38f9c67fe93cb8a Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 3 Jul 2018 14:23:47 +0100
-Subject: [PATCH 358/454] spi: Make GPIO CSs honour the SPI_NO_CS flag
-
-The SPI configuration state includes an SPI_NO_CS flag that disables
-all CS line manipulation, for applications that want to manage their
-own chip selects. However, this flag is ignored by the GPIO CS code
-in the SPI framework.
-
-Correct this omission with a trivial patch.
-
-See: https://github.com/raspberrypi/linux/issues/2169
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/spi/spi.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/spi/spi.c
-+++ b/drivers/spi/spi.c
-@@ -729,7 +729,9 @@ static void spi_set_cs(struct spi_device
- 		enable = !enable;
- 
- 	if (gpio_is_valid(spi->cs_gpio)) {
--		gpio_set_value_cansleep(spi->cs_gpio, !enable);
-+		/* Honour the SPI_NO_CS flag */
-+		if (!(spi->mode & SPI_NO_CS))
-+			gpio_set_value(spi->cs_gpio, !enable);
- 		/* Some SPI masters need both GPIO CS & slave_select */
- 		if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
- 		    spi->controller->set_cs)
diff --git a/target/linux/brcm2708/patches-4.14/950-0359-net-lan78xx-fix-rx-handling-before-first-packet-is-s.patch b/target/linux/brcm2708/patches-4.14/950-0359-net-lan78xx-fix-rx-handling-before-first-packet-is-s.patch
deleted file mode 100644
index 1acda73f3..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0359-net-lan78xx-fix-rx-handling-before-first-packet-is-s.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 213fa517424f4d1c83e7cf486c0f113bd874c32c Mon Sep 17 00:00:00 2001
-From: Stefan Wahren <stefan.wahren@i2se.com>
-Date: Mon, 16 Jul 2018 21:33:40 +0200
-Subject: [PATCH 359/454] net: lan78xx: fix rx handling before first packet is
- send
-
-As long the bh tasklet isn't scheduled once, no packet from the rx path
-will be handled. Since the tx path also schedule the same tasklet
-this situation only persits until the first packet transmission.
-So fix this issue by scheduling the tasklet during ndo_open like in usbnet.
-
-Link: https://github.com/raspberrypi/linux/issues/2617
-Fixes: 55d7de9de6c3 ("Microchip's LAN7800 family USB 2/3 to 10/100/1000 Ethernet")
-Suggested-by: Floris Bos <bos@je-eigen-domein.nl>
-Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
----
- drivers/net/usb/lan78xx.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2585,6 +2585,8 @@ static int lan78xx_open(struct net_devic
- 
- 	dev->link_on = false;
- 
-+	tasklet_schedule(&dev->bh);
-+
- 	lan78xx_defer_kevent(dev, EVENT_LINK_RESET);
- done:
- 	usb_autopm_put_interface(dev->intf);
diff --git a/target/linux/brcm2708/patches-4.14/950-0360-lan78xx-Fix-link-status-notifications.patch b/target/linux/brcm2708/patches-4.14/950-0360-lan78xx-Fix-link-status-notifications.patch
deleted file mode 100644
index c7b1c3e5e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0360-lan78xx-Fix-link-status-notifications.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 033e0f05b592bc315c8278fce37f100d90bc64b4 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 18 Jul 2018 09:31:17 +0100
-Subject: [PATCH 360/454] lan78xx: Fix link status notifications
-
-The patch to allow packet reception before the first transmission broke
-the notification and handling of link status changes. Move the new call
-to tasklet_schedule into lan78xx_link_reset to fix it.
-
-See: https://github.com/raspberrypi/linux/issues/2617
-
-Fixes: d407fc229cdc ("net: lan78xx: fix rx handling before first packet is send")
-Suggested-by: Stefan Wahren <stefan.wahren@i2se.com>
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/net/usb/lan78xx.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2585,8 +2585,6 @@ static int lan78xx_open(struct net_devic
- 
- 	dev->link_on = false;
- 
--	tasklet_schedule(&dev->bh);
--
- 	lan78xx_defer_kevent(dev, EVENT_LINK_RESET);
- done:
- 	usb_autopm_put_interface(dev->intf);
diff --git a/target/linux/brcm2708/patches-4.14/950-0361-overlays-Fix-vc4-kms-kippah-7inch.patch b/target/linux/brcm2708/patches-4.14/950-0361-overlays-Fix-vc4-kms-kippah-7inch.patch
deleted file mode 100644
index d448e23e6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0361-overlays-Fix-vc4-kms-kippah-7inch.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 38c886fdba43a119c7a28655e30c11fc77cdf814 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Thu, 19 Jul 2018 13:07:39 +0100
-Subject: [PATCH 361/454] overlays: Fix vc4-kms-kippah-7inch
-
-Add a Params: to the README entry and move it into alphabetical order.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README | 13 +++++++------
- 1 file changed, 7 insertions(+), 6 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1965,6 +1965,13 @@ Params: cma-256                 CMA is 2
-         cma-64                  CMA is 64MB
- 
- 
-+Name:   vc4-kms-kippah-7inch
-+Info:   Enable the Adafruit DPI Kippah with the 7" Ontat panel attached.
-+        Requires vc4-kms-v3d to be loaded.
-+Load:   dtoverlay=vc4-kms-kippah-7inch
-+Params: <None>
-+
-+
- Name:   vc4-kms-v3d
- Info:   Enable Eric Anholt's DRM VC4 HDMI/HVS/V3D driver. Running startx or
-         booting to GUI while this overlay is in use will cause interesting
-@@ -1977,12 +1984,6 @@ Params: cma-256                 CMA is 2
-         cma-64                  CMA is 64MB
- 
- 
--Name:   vc4-kms-kippah-7inch
--Info:   Enable the Adafruit DPI Kippah with the 7" Ontat panel attached.
--        Requires vc4-kms-v3d to be loaded.
--Load:   dtoverlay=vc4-kms-kippah-7inch
--
--
- Name:   vga666
- Info:   Overlay for the Fen Logic VGA666 board
-         This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds
diff --git a/target/linux/brcm2708/patches-4.14/950-0362-dwc-otg-FIQ-Fix-bad-mode-in-data-abort-handler.patch b/target/linux/brcm2708/patches-4.14/950-0362-dwc-otg-FIQ-Fix-bad-mode-in-data-abort-handler.patch
deleted file mode 100644
index 1627494e2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0362-dwc-otg-FIQ-Fix-bad-mode-in-data-abort-handler.patch
+++ /dev/null
@@ -1,128 +0,0 @@
-From 8edeb93cec4b7ca6771348fafbf4676920b052c9 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 16 Jul 2018 14:40:13 +0100
-Subject: [PATCH 362/454] dwc-otg: FIQ: Fix "bad mode in data abort handler"
-
-Create a semi-static mapping for the USB registers early in the boot
-process, before additional kernel threads are started, so all threads
-will have the mappings from the start. This avoids the need for
-data aborts to lazily update them.
-
-See: https://github.com/raspberrypi/linux/issues/2450
-
-Signed-off-by: Floris Bos <bos@je-eigen-domein.nl>
----
- arch/arm/mach-bcm/board_bcm2835.c         | 69 +++++++++++++++++++++++
- drivers/usb/host/dwc_otg/dwc_otg_driver.c |  2 +-
- 2 files changed, 70 insertions(+), 1 deletion(-)
-
---- a/arch/arm/mach-bcm/board_bcm2835.c
-+++ b/arch/arm/mach-bcm/board_bcm2835.c
-@@ -15,6 +15,7 @@
- #include <linux/init.h>
- #include <linux/irqchip.h>
- #include <linux/of_address.h>
-+#include <linux/of_fdt.h>
- #include <linux/clk/bcm2835.h>
- #include <asm/system_info.h>
- 
-@@ -24,6 +25,9 @@
- #include "platsmp.h"
- #include <linux/dma-mapping.h>
- 
-+#define BCM2835_USB_VIRT_BASE   0xf0980000
-+#define BCM2835_USB_VIRT_MPHI   0xf0006000
-+
- static void __init bcm2835_init(void)
- {
- 	struct device_node *np = of_find_node_by_path("/system");
-@@ -44,6 +48,70 @@ static void __init bcm2835_init_early(vo
- 	init_dma_coherent_pool_size(SZ_1M);
- }
- 
-+/*
-+ * We need to map registers that are going to be accessed by the FIQ
-+ * very early, before any kernel threads are spawned. Because if done
-+ * later, the mapping tables are not updated instantly but lazily upon
-+ * first access through a data abort handler. While that is fine
-+ * when executing regular kernel code, if the first access in a specific
-+ * thread happens while running FIQ code this will result in a panic.
-+ *
-+ * For more background see the following old mailing list thread:
-+ * https://www.spinics.net/lists/arm-kernel/msg325250.html
-+ */
-+static int __init bcm2835_map_usb(unsigned long node, const char *uname,
-+					int depth, void *data)
-+{
-+	struct map_desc map[2];
-+	const __be32 *reg;
-+	int len;
-+	unsigned long p2b_offset = *((unsigned long *) data);
-+
-+	if (!of_flat_dt_is_compatible(node, "brcm,bcm2708-usb"))
-+		return 0;
-+	reg = of_get_flat_dt_prop(node, "reg", &len);
-+	if (!reg || len != (sizeof(unsigned long) * 4))
-+		return 0;
-+
-+	/* Use information about the physical addresses of the
-+	 * registers from the device tree, but use legacy
-+	 * iotable_init() static mapping function to map them,
-+	 * as ioremap() is not functional at this stage in boot.
-+	 */
-+	map[0].virtual = (unsigned long) BCM2835_USB_VIRT_BASE;
-+	map[0].pfn = __phys_to_pfn(be32_to_cpu(reg[0]) - p2b_offset);
-+	map[0].length = be32_to_cpu(reg[1]);
-+	map[0].type = MT_DEVICE;
-+	map[1].virtual = (unsigned long) BCM2835_USB_VIRT_MPHI;
-+	map[1].pfn = __phys_to_pfn(be32_to_cpu(reg[2]) - p2b_offset);
-+	map[1].length = be32_to_cpu(reg[3]);
-+	map[1].type = MT_DEVICE;
-+	iotable_init(map, 2);
-+
-+	return 1;
-+}
-+
-+static void __init bcm2835_map_io(void)
-+{
-+	const __be32 *ranges;
-+	int soc, len;
-+	unsigned long p2b_offset;
-+
-+	debug_ll_io_init();
-+
-+	/* Find out how to map bus to physical address first from soc/ranges */
-+	soc = of_get_flat_dt_subnode_by_name(of_get_flat_dt_root(), "soc");
-+	if (soc < 0)
-+		return;
-+	ranges = of_get_flat_dt_prop(soc, "ranges", &len);
-+	if (!ranges || len < (sizeof(unsigned long) * 3))
-+		return;
-+	p2b_offset = be32_to_cpu(ranges[0]) - be32_to_cpu(ranges[1]);
-+
-+	/* Now search for bcm2708-usb node in device tree */
-+	of_scan_flat_dt(bcm2835_map_usb, &p2b_offset);
-+}
-+
- static const char * const bcm2835_compat[] = {
- #ifdef CONFIG_ARCH_MULTI_V6
- 	"brcm,bcm2835",
-@@ -56,6 +124,7 @@ static const char * const bcm2835_compat
- };
- 
- DT_MACHINE_START(BCM2835, "BCM2835")
-+	.map_io = bcm2835_map_io,
- 	.init_machine = bcm2835_init,
- 	.init_early = bcm2835_init_early,
- 	.dt_compat = bcm2835_compat,
---- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
-@@ -837,7 +837,7 @@ static int dwc_otg_driver_probe(
- 		retval = -ENOMEM;
- 		goto fail;
- 	}
--	dev_dbg(&_dev->dev, "base=0x%08x\n",
-+	dev_info(&_dev->dev, "base=0x%08x\n",
-                 (unsigned)dwc_otg_device->os_dep.base);
- #endif
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0363-End-log-messages-in-one-newline-not-two.patch b/target/linux/brcm2708/patches-4.14/950-0363-End-log-messages-in-one-newline-not-two.patch
deleted file mode 100644
index 38fea57f1..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0363-End-log-messages-in-one-newline-not-two.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 0c3fac1d19848029b6e76cdf3585358f313d5117 Mon Sep 17 00:00:00 2001
-From: Andreas Gustafsson <gson@gson.org>
-Date: Tue, 7 Aug 2018 20:19:07 +0300
-Subject: [PATCH 363/454] End log messages in one newline, not two.
-
-Signed-off-by: Andreas Gustafsson <gson@gson.org>
----
- .../staging/vc04_services/interface/vchiq_arm/vchiq_arm.c   | 4 ++--
- .../vc04_services/interface/vchiq_arm/vchiq_kern_lib.c      | 6 +++---
- 2 files changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
-@@ -2084,7 +2084,7 @@ dump_phys_mem(void *virt_addr, u32 num_b
- 	pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL);
- 	if (!pages) {
- 		vchiq_log_error(vchiq_arm_log_level,
--			"Unable to allocation memory for %d pages\n",
-+			"Unable to allocation memory for %d pages",
- 			num_pages);
- 		return;
- 	}
-@@ -2103,7 +2103,7 @@ dump_phys_mem(void *virt_addr, u32 num_b
- 
- 	if (rc < 0) {
- 		vchiq_log_error(vchiq_arm_log_level,
--				"Failed to get user pages: %d\n", rc);
-+				"Failed to get user pages: %d", rc);
- 		goto out;
- 	}
- 
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
-@@ -89,17 +89,17 @@ VCHIQ_STATUS_T vchiq_initialise(VCHIQ_IN
- 	}
- 	if (i == VCHIQ_INIT_RETRIES) {
- 		vchiq_log_error(vchiq_core_log_level,
--			"%s: videocore not initialized\n", __func__);
-+			"%s: videocore not initialized", __func__);
- 		goto failed;
- 	} else if (i > 0) {
- 		vchiq_log_warning(vchiq_core_log_level,
--			"%s: videocore initialized after %d retries\n", __func__, i);
-+			"%s: videocore initialized after %d retries", __func__, i);
- 	}
- 
- 	instance = kzalloc(sizeof(*instance), GFP_KERNEL);
- 	if (!instance) {
- 		vchiq_log_error(vchiq_core_log_level,
--			"%s: error allocating vchiq instance\n", __func__);
-+			"%s: error allocating vchiq instance", __func__);
- 		goto failed;
- 	}
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0364-Fix-one-more-log-message-ending-in-two-newlines.patch b/target/linux/brcm2708/patches-4.14/950-0364-Fix-one-more-log-message-ending-in-two-newlines.patch
deleted file mode 100644
index 55a93ca4a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0364-Fix-one-more-log-message-ending-in-two-newlines.patch
+++ /dev/null
@@ -1,21 +0,0 @@
-From 2caa88a2dd1b282bf71a54a7e00df3e7df502d94 Mon Sep 17 00:00:00 2001
-From: Andreas Gustafsson <gson@gson.org>
-Date: Wed, 8 Aug 2018 22:23:40 +0300
-Subject: [PATCH 364/454] Fix one more log message ending in two newlines.
-
-Signed-off-by: Andreas Gustafsson <gson@gson.org>
----
- drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c
-@@ -3153,7 +3153,7 @@ vchiq_pause_internal(VCHIQ_STATE_T *stat
- 		break;
- 	default:
- 		vchiq_log_error(vchiq_core_log_level,
--			"vchiq_pause_internal in state %s\n",
-+			"vchiq_pause_internal in state %s",
- 			conn_state_names[state->conn_state]);
- 		status = VCHIQ_ERROR;
- 		VCHIQ_STATS_INC(state, error_count);
diff --git a/target/linux/brcm2708/patches-4.14/950-0365-Add-rpi-poe-fan-driver.patch b/target/linux/brcm2708/patches-4.14/950-0365-Add-rpi-poe-fan-driver.patch
deleted file mode 100644
index ccf014b45..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0365-Add-rpi-poe-fan-driver.patch
+++ /dev/null
@@ -1,615 +0,0 @@
-From 1f8ba449fabb0eda1d835138d2324f8bc251e8c5 Mon Sep 17 00:00:00 2001
-From: Serge Schneider <serge@raspberrypi.org>
-Date: Mon, 9 Jul 2018 12:54:25 +0100
-Subject: [PATCH 365/454] Add rpi-poe-fan driver
-
-Signed-off-by: Serge Schneider <serge@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |   1 +
- arch/arm/boot/dts/overlays/README             |   6 +
- .../arm/boot/dts/overlays/rpi-poe-overlay.dts |  61 +++
- arch/arm/configs/bcm2709_defconfig            |   1 +
- arch/arm/configs/bcmrpi_defconfig             |   1 +
- drivers/hwmon/Kconfig                         |  10 +
- drivers/hwmon/Makefile                        |   1 +
- drivers/hwmon/rpi-poe-fan.c                   | 443 ++++++++++++++++++
- include/soc/bcm2835/raspberrypi-firmware.h    |   2 +
- 9 files changed, 526 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/rpi-poe-overlay.dts
- create mode 100644 drivers/hwmon/rpi-poe-fan.c
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -103,6 +103,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	rpi-dac.dtbo \
- 	rpi-display.dtbo \
- 	rpi-ft5406.dtbo \
-+	rpi-poe.dtbo \
- 	rpi-proto.dtbo \
- 	rpi-sense.dtbo \
- 	rpi-tv.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1576,6 +1576,12 @@ Params: touchscreen-size-x      Touchscr
-         touchscreen-swapped-x-y Swap X and Y cordinates (default 0);
- 
- 
-+Name:   rpi-poe
-+Info:   Raspberry Pi POE HAT
-+Load:   dtoverlay=rpi-poe
-+Params: <None>
-+
-+
- Name:   rpi-proto
- Info:   Configures the RPi Proto audio card
- Load:   dtoverlay=rpi-proto
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts
-@@ -0,0 +1,61 @@
-+/*
-+ * Overlay for the Raspberry Pi POE HAT.
-+ */
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			fan0: rpi-poe-fan@0 {
-+				compatible = "rpi-poe-fan";
-+				firmware = <&firmware>;
-+				cooling-min-state = <0>;
-+				cooling-max-state = <3>;
-+				#cooling-cells = <2>;
-+				cooling-levels = <0 50 150 255>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&cpu_thermal>;
-+		__overlay__ {
-+			trips {
-+				threshold: trip-point@0 {
-+					temperature = <45000>;
-+					hysteresis = <5000>;
-+					type = "active";
-+				};
-+				target: trip-point@1 {
-+					temperature = <50000>;
-+					hysteresis = <2000>;
-+					type = "active";
-+				};
-+				cpu_hot: cpu_hot@0 {
-+					temperature = <55000>;
-+					hysteresis = <2000>;
-+					type = "active";
-+				};
-+			};
-+			cooling-maps {
-+				map0 {
-+					trip = <&threshold>;
-+					cooling-device = <&fan0 0 1>;
-+				};
-+				map1 {
-+					trip = <&target>;
-+					cooling-device = <&fan0 1 2>;
-+				};
-+				map2 {
-+					trip = <&cpu_hot>;
-+					cooling-device = <&fan0 2 3>;
-+				};
-+			};
-+		};
-+	};
-+};
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -658,6 +658,7 @@ CONFIG_HWMON=m
- CONFIG_SENSORS_DS1621=m
- CONFIG_SENSORS_JC42=m
- CONFIG_SENSORS_LM75=m
-+CONFIG_SENSORS_RPI_POE_FAN=m
- CONFIG_SENSORS_SHT21=m
- CONFIG_SENSORS_SHT3x=m
- CONFIG_SENSORS_SHTC1=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -651,6 +651,7 @@ CONFIG_HWMON=m
- CONFIG_SENSORS_DS1621=m
- CONFIG_SENSORS_JC42=m
- CONFIG_SENSORS_LM75=m
-+CONFIG_SENSORS_RPI_POE_FAN=m
- CONFIG_SENSORS_SHT21=m
- CONFIG_SENSORS_SHT3x=m
- CONFIG_SENSORS_SHTC1=m
---- a/drivers/hwmon/Kconfig
-+++ b/drivers/hwmon/Kconfig
-@@ -1286,6 +1286,16 @@ config SENSORS_PWM_FAN
- 	  This driver can also be built as a module.  If so, the module
- 	  will be called pwm-fan.
- 
-+config SENSORS_RPI_POE_FAN
-+	tristate "Raspberry Pi POE HAT fan"
-+	depends on RASPBERRYPI_FIRMWARE
-+	depends on THERMAL || THERMAL=n
-+	help
-+	  If you say yes here you get support for Raspberry Pi POE HAT fan.
-+
-+	  This driver can also be built as a module.  If so, the module
-+	  will be called rpi-poe-fan.
-+
- config SENSORS_SHT15
- 	tristate "Sensiron humidity and temperature sensors. SHT15 and compat."
- 	depends on GPIOLIB || COMPILE_TEST
---- a/drivers/hwmon/Makefile
-+++ b/drivers/hwmon/Makefile
-@@ -138,6 +138,7 @@ obj-$(CONFIG_SENSORS_PC87427)	+= pc87427
- obj-$(CONFIG_SENSORS_PCF8591)	+= pcf8591.o
- obj-$(CONFIG_SENSORS_POWR1220)  += powr1220.o
- obj-$(CONFIG_SENSORS_PWM_FAN)	+= pwm-fan.o
-+obj-$(CONFIG_SENSORS_RPI_POE_FAN)	+= rpi-poe-fan.o
- obj-$(CONFIG_SENSORS_S3C)	+= s3c-hwmon.o
- obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o
- obj-$(CONFIG_SENSORS_SCH5627)	+= sch5627.o
---- /dev/null
-+++ b/drivers/hwmon/rpi-poe-fan.c
-@@ -0,0 +1,443 @@
-+/*
-+ * rpi-poe-fan.c - Hwmon driver for Raspberry Pi POE HAT fan.
-+ *
-+ * Copyright (C) 2018 Raspberry Pi (Trading) Ltd.
-+ * Based on pwm-fan.c by Kamil Debski <k.debski@samsung.com>
-+ *
-+ * Author: Serge Schneider <serge@raspberrypi.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/hwmon.h>
-+#include <linux/hwmon-sysfs.h>
-+#include <linux/module.h>
-+#include <linux/mutex.h>
-+#include <linux/notifier.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/reboot.h>
-+#include <linux/sysfs.h>
-+#include <linux/thermal.h>
-+#include <soc/bcm2835/raspberrypi-firmware.h>
-+
-+#define MAX_PWM 255
-+
-+#define POE_CUR_PWM 0x0
-+#define POE_DEF_PWM 0x1
-+
-+struct rpi_poe_fan_ctx {
-+	struct mutex lock;
-+	struct rpi_firmware *fw;
-+	unsigned int pwm_value;
-+	unsigned int def_pwm_value;
-+	unsigned int rpi_poe_fan_state;
-+	unsigned int rpi_poe_fan_max_state;
-+	unsigned int *rpi_poe_fan_cooling_levels;
-+	struct thermal_cooling_device *cdev;
-+	struct notifier_block nb;
-+};
-+
-+struct m_data_s{
-+	u32 reg;
-+	u32 val;
-+	u32 ret;
-+};
-+
-+static int write_reg(struct rpi_firmware *fw, u32 reg, u32 *val){
-+	struct m_data_s m_data = {
-+		.reg = reg,
-+		.val = *val
-+	};
-+	int ret;
-+	ret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POE_HAT_VAL,
-+				    &m_data, sizeof(m_data));
-+	if (ret) {
-+		return ret;
-+	} else if (m_data.ret) {
-+		return -EIO;
-+	}
-+	return 0;
-+}
-+
-+static int read_reg(struct rpi_firmware *fw, u32 reg, u32 *val){
-+	struct m_data_s m_data = {
-+		.reg = reg,
-+	};
-+	int ret;
-+	ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_POE_HAT_VAL,
-+				    &m_data, sizeof(m_data));
-+	if (ret) {
-+		return ret;
-+	} else if (m_data.ret) {
-+		return -EIO;
-+	}
-+	*val = m_data.val;
-+	return 0;
-+}
-+
-+static int rpi_poe_reboot(struct notifier_block *nb, unsigned long code,
-+			  void *unused)
-+{
-+	struct rpi_poe_fan_ctx *ctx = container_of(nb, struct rpi_poe_fan_ctx,
-+						   nb);
-+
-+	if (ctx->pwm_value != ctx->def_pwm_value)
-+		write_reg(ctx->fw, POE_CUR_PWM, &ctx->def_pwm_value);
-+
-+	return NOTIFY_DONE;
-+}
-+
-+static int  __set_pwm(struct rpi_poe_fan_ctx *ctx, u32 pwm)
-+{
-+	int ret = 0;
-+
-+	mutex_lock(&ctx->lock);
-+	if (ctx->pwm_value == pwm)
-+		goto exit_set_pwm_err;
-+
-+	ret = write_reg(ctx->fw, POE_CUR_PWM, &pwm);
-+	if (!ret)
-+		ctx->pwm_value = pwm;
-+exit_set_pwm_err:
-+	mutex_unlock(&ctx->lock);
-+	return ret;
-+}
-+
-+static int  __set_def_pwm(struct rpi_poe_fan_ctx *ctx, u32 def_pwm)
-+{
-+	int ret = 0;
-+	mutex_lock(&ctx->lock);
-+	if (ctx->def_pwm_value == def_pwm)
-+		goto exit_set_def_pwm_err;
-+
-+	ret = write_reg(ctx->fw, POE_CUR_PWM, &def_pwm);
-+	if (!ret)
-+		ctx->def_pwm_value = def_pwm;
-+exit_set_def_pwm_err:
-+	mutex_unlock(&ctx->lock);
-+	return ret;
-+}
-+
-+static void rpi_poe_fan_update_state(struct rpi_poe_fan_ctx *ctx,
-+				     unsigned long pwm)
-+{
-+	int i;
-+
-+	for (i = 0; i < ctx->rpi_poe_fan_max_state; ++i)
-+		if (pwm < ctx->rpi_poe_fan_cooling_levels[i + 1])
-+			break;
-+
-+	ctx->rpi_poe_fan_state = i;
-+}
-+
-+static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
-+		       const char *buf, size_t count)
-+{
-+	struct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);
-+	unsigned long pwm;
-+	int ret;
-+
-+	if (kstrtoul(buf, 10, &pwm) || pwm > MAX_PWM)
-+		return -EINVAL;
-+
-+	ret = __set_pwm(ctx, pwm);
-+	if (ret)
-+		return ret;
-+
-+	rpi_poe_fan_update_state(ctx, pwm);
-+	return count;
-+}
-+
-+static ssize_t set_def_pwm(struct device *dev, struct device_attribute *attr,
-+			   const char *buf, size_t count)
-+{
-+	struct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);
-+	unsigned long def_pwm;
-+	int ret;
-+
-+	if (kstrtoul(buf, 10, &def_pwm) || def_pwm > MAX_PWM)
-+		return -EINVAL;
-+
-+	ret = __set_def_pwm(ctx, def_pwm);
-+	if (ret)
-+		return ret;
-+	return count;
-+}
-+
-+static ssize_t show_pwm(struct device *dev,
-+			struct device_attribute *attr, char *buf)
-+{
-+	struct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);
-+
-+	return sprintf(buf, "%u\n", ctx->pwm_value);
-+}
-+
-+static ssize_t show_def_pwm(struct device *dev,
-+			struct device_attribute *attr, char *buf)
-+{
-+	struct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);
-+
-+	return sprintf(buf, "%u\n", ctx->def_pwm_value);
-+}
-+
-+
-+static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);
-+static SENSOR_DEVICE_ATTR(def_pwm1, 0644, show_def_pwm, set_def_pwm, 1);
-+
-+static struct attribute *rpi_poe_fan_attrs[] = {
-+	&sensor_dev_attr_pwm1.dev_attr.attr,
-+	&sensor_dev_attr_def_pwm1.dev_attr.attr,
-+	NULL,
-+};
-+
-+ATTRIBUTE_GROUPS(rpi_poe_fan);
-+
-+/* thermal cooling device callbacks */
-+static int rpi_poe_fan_get_max_state(struct thermal_cooling_device *cdev,
-+				     unsigned long *state)
-+{
-+	struct rpi_poe_fan_ctx *ctx = cdev->devdata;
-+
-+	if (!ctx)
-+		return -EINVAL;
-+
-+	*state = ctx->rpi_poe_fan_max_state;
-+
-+	return 0;
-+}
-+
-+static int rpi_poe_fan_get_cur_state(struct thermal_cooling_device *cdev,
-+				     unsigned long *state)
-+{
-+	struct rpi_poe_fan_ctx *ctx = cdev->devdata;
-+
-+	if (!ctx)
-+		return -EINVAL;
-+
-+	*state = ctx->rpi_poe_fan_state;
-+
-+	return 0;
-+}
-+
-+static int rpi_poe_fan_set_cur_state(struct thermal_cooling_device *cdev,
-+				     unsigned long state)
-+{
-+	struct rpi_poe_fan_ctx *ctx = cdev->devdata;
-+	int ret;
-+
-+	if (!ctx || (state > ctx->rpi_poe_fan_max_state))
-+		return -EINVAL;
-+
-+	if (state == ctx->rpi_poe_fan_state)
-+		return 0;
-+
-+	ret = __set_pwm(ctx, ctx->rpi_poe_fan_cooling_levels[state]);
-+	if (ret) {
-+		dev_err(&cdev->device, "Cannot set pwm!\n");
-+		return ret;
-+	}
-+
-+	ctx->rpi_poe_fan_state = state;
-+
-+	return ret;
-+}
-+
-+static const struct thermal_cooling_device_ops rpi_poe_fan_cooling_ops = {
-+	.get_max_state = rpi_poe_fan_get_max_state,
-+	.get_cur_state = rpi_poe_fan_get_cur_state,
-+	.set_cur_state = rpi_poe_fan_set_cur_state,
-+};
-+
-+static int rpi_poe_fan_of_get_cooling_data(struct device *dev,
-+				       struct rpi_poe_fan_ctx *ctx)
-+{
-+	struct device_node *np = dev->of_node;
-+	int num, i, ret;
-+
-+	if (!of_find_property(np, "cooling-levels", NULL))
-+		return 0;
-+
-+	ret = of_property_count_u32_elems(np, "cooling-levels");
-+	if (ret <= 0) {
-+		dev_err(dev, "Wrong data!\n");
-+		return ret ? : -EINVAL;
-+	}
-+
-+	num = ret;
-+	ctx->rpi_poe_fan_cooling_levels = devm_kzalloc(dev, num * sizeof(u32),
-+						   GFP_KERNEL);
-+	if (!ctx->rpi_poe_fan_cooling_levels)
-+		return -ENOMEM;
-+
-+	ret = of_property_read_u32_array(np, "cooling-levels",
-+					 ctx->rpi_poe_fan_cooling_levels, num);
-+	if (ret) {
-+		dev_err(dev, "Property 'cooling-levels' cannot be read!\n");
-+		return ret;
-+	}
-+
-+	for (i = 0; i < num; i++) {
-+		if (ctx->rpi_poe_fan_cooling_levels[i] > MAX_PWM) {
-+			dev_err(dev, "PWM fan state[%d]:%d > %d\n", i,
-+				ctx->rpi_poe_fan_cooling_levels[i], MAX_PWM);
-+			return -EINVAL;
-+		}
-+	}
-+
-+	ctx->rpi_poe_fan_max_state = num - 1;
-+
-+	return 0;
-+}
-+
-+static int rpi_poe_fan_probe(struct platform_device *pdev)
-+{
-+	struct thermal_cooling_device *cdev;
-+	struct rpi_poe_fan_ctx *ctx;
-+	struct device *hwmon;
-+	struct device_node *np = pdev->dev.of_node;
-+	struct device_node *fw_node;
-+	int ret;
-+
-+	fw_node = of_parse_phandle(np, "firmware", 0);
-+	if (!fw_node) {
-+		dev_err(&pdev->dev, "Missing firmware node\n");
-+		return -ENOENT;
-+	}
-+
-+	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
-+	if (!ctx)
-+		return -ENOMEM;
-+
-+	mutex_init(&ctx->lock);
-+
-+	ctx->fw = rpi_firmware_get(fw_node);
-+	if (!ctx->fw)
-+		return -EPROBE_DEFER;
-+
-+	platform_set_drvdata(pdev, ctx);
-+
-+	ctx->nb.notifier_call = rpi_poe_reboot;
-+	ret = register_reboot_notifier(&ctx->nb);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to register reboot notifier: %i\n",
-+			ret);
-+		return ret;
-+	}
-+	ret = read_reg(ctx->fw, POE_DEF_PWM, &ctx->def_pwm_value);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to get default PWM value: %i\n",
-+			ret);
-+		goto err;
-+	}
-+	ret = read_reg(ctx->fw, POE_CUR_PWM, &ctx->pwm_value);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to get current PWM value: %i\n",
-+			ret);
-+		goto err;
-+	}
-+
-+	hwmon = devm_hwmon_device_register_with_groups(&pdev->dev, "rpipoefan",
-+						       ctx, rpi_poe_fan_groups);
-+	if (IS_ERR(hwmon)) {
-+		dev_err(&pdev->dev, "Failed to register hwmon device\n");
-+		ret = PTR_ERR(hwmon);
-+		goto err;
-+	}
-+
-+	ret = rpi_poe_fan_of_get_cooling_data(&pdev->dev, ctx);
-+	if (ret)
-+		return ret;
-+
-+	rpi_poe_fan_update_state(ctx, ctx->pwm_value);
-+	if (!IS_ENABLED(CONFIG_THERMAL))
-+		return 0;
-+
-+	cdev = thermal_of_cooling_device_register(np,
-+						  "rpi-poe-fan", ctx,
-+						  &rpi_poe_fan_cooling_ops);
-+	if (IS_ERR(cdev)) {
-+		dev_err(&pdev->dev,
-+			"Failed to register rpi-poe-fan as cooling device");
-+		ret = PTR_ERR(cdev);
-+		goto err;
-+	}
-+	ctx->cdev = cdev;
-+	thermal_cdev_update(cdev);
-+
-+	return 0;
-+err:
-+	unregister_reboot_notifier(&ctx->nb);
-+	return ret;
-+}
-+
-+static int rpi_poe_fan_remove(struct platform_device *pdev)
-+{
-+	struct rpi_poe_fan_ctx *ctx = platform_get_drvdata(pdev);
-+	u32 value = ctx->def_pwm_value;
-+
-+	unregister_reboot_notifier(&ctx->nb);
-+	thermal_cooling_device_unregister(ctx->cdev);
-+	if (ctx->pwm_value != value) {
-+		write_reg(ctx->fw, POE_CUR_PWM, &value);
-+	}
-+	return 0;
-+}
-+
-+#ifdef CONFIG_PM_SLEEP
-+static int rpi_poe_fan_suspend(struct device *dev)
-+{
-+	struct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);
-+	u32 value = 0;
-+
-+	if (ctx->pwm_value != value)
-+		ret = write_reg(ctx->fw, POE_CUR_PWM, &value);
-+	return 0;
-+}
-+
-+static int rpi_poe_fan_resume(struct device *dev)
-+{
-+	struct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);
-+	u32 value = ctx->pwm_value;
-+	int ret = 0;
-+
-+	if (value != 0)
-+		ret = write_reg(ctx->fw, POE_CUR_PWM, &value);
-+
-+	return ret;
-+}
-+#endif
-+
-+static SIMPLE_DEV_PM_OPS(rpi_poe_fan_pm, rpi_poe_fan_suspend,
-+			 rpi_poe_fan_resume);
-+
-+static const struct of_device_id of_rpi_poe_fan_match[] = {
-+	{ .compatible = "rpi-poe-fan", },
-+	{},
-+};
-+MODULE_DEVICE_TABLE(of, of_rpi_poe_fan_match);
-+
-+static struct platform_driver rpi_poe_fan_driver = {
-+	.probe		= rpi_poe_fan_probe,
-+	.remove		= rpi_poe_fan_remove,
-+	.driver	= {
-+		.name		= "rpi-poe-fan",
-+		.pm		= &rpi_poe_fan_pm,
-+		.of_match_table	= of_rpi_poe_fan_match,
-+	},
-+};
-+
-+module_platform_driver(rpi_poe_fan_driver);
-+
-+MODULE_AUTHOR("Serge Schneider <serge@raspberrypi.org>");
-+MODULE_ALIAS("platform:rpi-poe-fan");
-+MODULE_DESCRIPTION("Raspberry Pi POE HAT fan driver");
-+MODULE_LICENSE("GPL");
---- a/include/soc/bcm2835/raspberrypi-firmware.h
-+++ b/include/soc/bcm2835/raspberrypi-firmware.h
-@@ -93,6 +93,8 @@ enum rpi_firmware_property_tag {
- 	RPI_FIRMWARE_SET_GPIO_CONFIG =                        0x00038043,
- 	RPI_FIRMWARE_GET_PERIPH_REG =                         0x00030045,
- 	RPI_FIRMWARE_SET_PERIPH_REG =                         0x00038045,
-+	RPI_FIRMWARE_GET_POE_HAT_VAL =                        0x00030049,
-+	RPI_FIRMWARE_SET_POE_HAT_VAL =                        0x00030050,
- 
- 
- 	/* Dispmanx TAGS */
diff --git a/target/linux/brcm2708/patches-4.14/950-0366-devicetree-add-RPi-CM3-dts-to-arm64-mimic-the-RPi-3B.patch b/target/linux/brcm2708/patches-4.14/950-0366-devicetree-add-RPi-CM3-dts-to-arm64-mimic-the-RPi-3B.patch
deleted file mode 100644
index b0a2ac1af..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0366-devicetree-add-RPi-CM3-dts-to-arm64-mimic-the-RPi-3B.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 1767590e5da1817e0f9ea0521af9096acb2590c6 Mon Sep 17 00:00:00 2001
-From: Steve Pavao <stevep@korgrd.com>
-Date: Fri, 10 Aug 2018 17:09:50 -0400
-Subject: [PATCH 366/454] devicetree: add RPi CM3 dts to arm64; mimic the RPi
- 3B arm64 dts implementation, by referring to the actual dts file in the arm
- directory
-
----
- arch/arm64/boot/dts/broadcom/Makefile            | 2 ++
- arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts | 3 +++
- 2 files changed, 5 insertions(+)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts
-
---- a/arch/arm64/boot/dts/broadcom/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/Makefile
-@@ -9,6 +9,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rp
- dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-3-b.dtb
- dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb
- dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb
-+dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-cm3.dtb
-+dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb
- 
- dts-dirs += ../overlays
- 
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts
-@@ -0,0 +1,3 @@
-+#define RPI364
-+
-+#include "../../../../arm/boot/dts/bcm2710-rpi-cm3.dts"
diff --git a/target/linux/brcm2708/patches-4.14/950-0367-staging-bcm2835-camera-Skip-ISP-pass-to-eliminate-pa.patch b/target/linux/brcm2708/patches-4.14/950-0367-staging-bcm2835-camera-Skip-ISP-pass-to-eliminate-pa.patch
deleted file mode 100644
index 610a9bc9f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0367-staging-bcm2835-camera-Skip-ISP-pass-to-eliminate-pa.patch
+++ /dev/null
@@ -1,231 +0,0 @@
-From 7efa934859d354d8c331d2c99a6126020ce0310d Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <6by9@users.noreply.github.com>
-Date: Thu, 10 May 2018 12:42:07 -0700
-Subject: [PATCH 367/454] staging: bcm2835-camera: Skip ISP pass to eliminate
- padding.
-
-commit dd9bb50522733befceac9cbe0b68f5ad4e5106ff upstream.
-
-Interleaved RGB and single plane YUV formats can be delivered by the
-GPU without the secondary step of removing padding, as the
-bytesperline field can be set appropriately.
-
-Planar YUV needs the GPU to still remove padding, as there is no way
-to report that there is padding between the planes (ie on the height).
-The multi-planar formats are NOT applicable, as there is no easy way
-to make them contiguous in memory (ie one large allocation that gets
-broken up). The whole task is passed across to videobuf2 which has no
-notion of that requirement.
-
-v2: Changes by anholt from the downstream driver: Flag two more planar
-    formats as needing padding removal, and remove broken userspace
-    workaround.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 44 ++++++++++++++-----
- .../bcm2835-camera/mmal-common.h              |  3 ++
- 2 files changed, 35 insertions(+), 12 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -88,6 +88,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 12,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 1,
-+	 .remove_padding = 1,
- 	 },
- 	{
- 	 .name = "4:2:2, packed, YUYV",
-@@ -97,6 +98,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 16,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 2,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "RGB24 (LE)",
-@@ -106,6 +108,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 24,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 3,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "JPEG",
-@@ -115,6 +118,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 8,
- 	 .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE,
- 	 .ybbp = 0,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "H264",
-@@ -124,6 +128,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 8,
- 	 .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
- 	 .ybbp = 0,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "MJPEG",
-@@ -133,6 +138,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 8,
- 	 .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
- 	 .ybbp = 0,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "4:2:2, packed, YVYU",
-@@ -142,6 +148,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 16,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 2,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "4:2:2, packed, VYUY",
-@@ -151,6 +158,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 16,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 2,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "4:2:2, packed, UYVY",
-@@ -160,6 +168,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 16,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 2,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "4:2:0, planar, NV12",
-@@ -169,6 +178,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 12,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 1,
-+	 .remove_padding = 1,
- 	 },
- 	{
- 	 .name = "RGB24 (BE)",
-@@ -178,6 +188,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 24,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 3,
-+	 .remove_padding = 0,
- 	 },
- 	{
- 	 .name = "4:2:0, planar, YVU",
-@@ -187,6 +198,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 12,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 1,
-+	 .remove_padding = 1,
- 	 },
- 	{
- 	 .name = "4:2:0, planar, NV21",
-@@ -196,6 +208,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 12,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 1,
-+	 .remove_padding = 1,
- 	 },
- 	{
- 	 .name = "RGB32 (BE)",
-@@ -205,6 +218,7 @@ static struct mmal_fmt formats[] = {
- 	 .depth = 32,
- 	 .mmal_component = MMAL_COMPONENT_CAMERA,
- 	 .ybbp = 4,
-+	 .remove_padding = 0,
- 	 },
- };
- 
-@@ -962,9 +976,19 @@ static int vidioc_try_fmt_vid_cap(struct
- 			      &f->fmt.pix.height, MIN_HEIGHT, dev->max_height,
- 			      1, 0);
- 	f->fmt.pix.bytesperline = f->fmt.pix.width * mfmt->ybbp;
-+	if (!mfmt->remove_padding) {
-+		int align_mask = ((32 * mfmt->depth) >> 3) - 1;
-+		/* GPU isn't removing padding, so stride is aligned to 32 */
-+		f->fmt.pix.bytesperline =
-+			(f->fmt.pix.bytesperline + align_mask) & ~align_mask;
-+		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+			 "Not removing padding, so bytes/line = %d, "
-+			 "(align_mask %d)\n",
-+			 f->fmt.pix.bytesperline, align_mask);
-+	}
- 
- 	/* Image buffer has to be padded to allow for alignment, even though
--	 * we then remove that padding before delivering the buffer.
-+	 * we sometimes then remove that padding before delivering the buffer.
- 	 */
- 	f->fmt.pix.sizeimage = ((f->fmt.pix.height + 15) & ~15) *
- 			(((f->fmt.pix.width + 31) & ~31) * mfmt->depth) >> 3;
-@@ -997,6 +1021,7 @@ static int mmal_setup_components(struct
- 	struct vchiq_mmal_port *port = NULL, *camera_port = NULL;
- 	struct vchiq_mmal_component *encode_component = NULL;
- 	struct mmal_fmt *mfmt = get_format(f);
-+	u32 remove_padding;
- 
- 	BUG_ON(!mfmt);
- 
-@@ -1065,6 +1090,12 @@ static int mmal_setup_components(struct
- 			camera_port->format.encoding = MMAL_ENCODING_RGB24;
- 	}
- 
-+	remove_padding = mfmt->remove_padding;
-+	vchiq_mmal_port_parameter_set(dev->instance,
-+				      camera_port,
-+				      MMAL_PARAMETER_NO_IMAGE_PADDING,
-+				      &remove_padding, sizeof(remove_padding));
-+
- 	camera_port->format.encoding_variant = 0;
- 	camera_port->es.video.width = f->fmt.pix.width;
- 	camera_port->es.video.height = f->fmt.pix.height;
-@@ -1542,7 +1573,6 @@ static int __init mmal_init(struct bm283
- {
- 	int ret;
- 	struct mmal_es_format_local *format;
--	u32 bool_true = 1;
- 	u32 supported_encodings[MAX_SUPPORTED_ENCODINGS];
- 	int param_size;
- 	struct vchiq_mmal_component  *camera;
-@@ -1626,11 +1656,6 @@ static int __init mmal_init(struct bm283
- 	format->es->video.frame_rate.num = 0; /* Rely on fps_range */
- 	format->es->video.frame_rate.den = 1;
- 
--	vchiq_mmal_port_parameter_set(dev->instance,
--				      &camera->output[MMAL_CAMERA_PORT_VIDEO],
--				      MMAL_PARAMETER_NO_IMAGE_PADDING,
--				      &bool_true, sizeof(bool_true));
--
- 	format = &camera->output[MMAL_CAMERA_PORT_CAPTURE].format;
- 
- 	format->encoding = MMAL_ENCODING_OPAQUE;
-@@ -1652,11 +1677,6 @@ static int __init mmal_init(struct bm283
- 	dev->capture.enc_profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;
- 	dev->capture.enc_level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
- 
--	vchiq_mmal_port_parameter_set(dev->instance,
--				      &camera->output[MMAL_CAMERA_PORT_CAPTURE],
--				      MMAL_PARAMETER_NO_IMAGE_PADDING,
--				      &bool_true, sizeof(bool_true));
--
- 	/* get the preview component ready */
- 	ret = vchiq_mmal_component_init(
- 			dev->instance, "ril.video_render",
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h
-@@ -31,6 +31,9 @@ struct mmal_fmt {
- 	int   depth;
- 	u32   mmal_component;  /* MMAL component index to be used to encode */
- 	u32   ybbp;            /* depth of first Y plane for planar formats */
-+	bool  remove_padding;  /* Does the GPU have to remove padding,
-+				* or can we do hide padding via bytesperline.
-+				*/
- };
- 
- /* buffer for one video frame */
diff --git a/target/linux/brcm2708/patches-4.14/950-0368-staging-bcm2835-camera-Allocate-context-once-per-buf.patch b/target/linux/brcm2708/patches-4.14/950-0368-staging-bcm2835-camera-Allocate-context-once-per-buf.patch
deleted file mode 100644
index c933bcc7a..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0368-staging-bcm2835-camera-Allocate-context-once-per-buf.patch
+++ /dev/null
@@ -1,192 +0,0 @@
-From f36097b9766ff3f61c21d1fd29e75ddd3844a533 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:08 -0700
-Subject: [PATCH 368/454] staging: bcm2835-camera: Allocate context once per
- buffer
-
-commit 96b7e81ab6b74e7cefdac0d7a90b746ef7f8597d upstream.
-
-The struct mmal_msg_context was being allocated for every message
-being sent to the VPU, and freed when it came back.  Whilst that is
-required behaviour for some messages (mainly the synchronous ones), it
-is wasteful for the video buffers that make up the majority of the
-traffic.
-
-Add to the buffer_init/cleanup hooks that it allocates/frees the
-msg_context required.
-
-v2: changes by anholt from the downstream tree: clean up indentation,
-    pass an error value through, forward-declare the struct so we have
-    less void *
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 30 +++++++++++++--
- .../bcm2835-camera/mmal-common.h              |  4 ++
- .../vc04_services/bcm2835-camera/mmal-vchiq.c | 38 ++++++++++++++-----
- .../vc04_services/bcm2835-camera/mmal-vchiq.h |  3 ++
- 4 files changed, 62 insertions(+), 13 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -280,6 +280,20 @@ static int queue_setup(struct vb2_queue
- 	return 0;
- }
- 
-+static int buffer_init(struct vb2_buffer *vb)
-+{
-+	struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
-+	struct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb);
-+	struct mmal_buffer *buf = container_of(vb2, struct mmal_buffer, vb);
-+
-+	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p, vb %p\n",
-+		 __func__, dev, vb);
-+	buf->buffer = vb2_plane_vaddr(&buf->vb.vb2_buf, 0);
-+	buf->buffer_size = vb2_plane_size(&buf->vb.vb2_buf, 0);
-+
-+	return mmal_vchi_buffer_init(dev->instance, buf);
-+}
-+
- static int buffer_prepare(struct vb2_buffer *vb)
- {
- 	struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
-@@ -302,6 +316,17 @@ static int buffer_prepare(struct vb2_buf
- 	return 0;
- }
- 
-+static void buffer_cleanup(struct vb2_buffer *vb)
-+{
-+	struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
-+	struct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb);
-+	struct mmal_buffer *buf = container_of(vb2, struct mmal_buffer, vb);
-+
-+	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p, vb %p\n",
-+		 __func__, dev, vb);
-+	mmal_vchi_buffer_cleanup(buf);
-+}
-+
- static inline bool is_capturing(struct bm2835_mmal_dev *dev)
- {
- 	return dev->capture.camera_port ==
-@@ -497,9 +522,6 @@ static void buffer_queue(struct vb2_buff
- 	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
- 		 "%s: dev:%p buf:%p\n", __func__, dev, buf);
- 
--	buf->buffer = vb2_plane_vaddr(&buf->vb.vb2_buf, 0);
--	buf->buffer_size = vb2_plane_size(&buf->vb.vb2_buf, 0);
--
- 	ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf);
- 	if (ret < 0)
- 		v4l2_err(&dev->v4l2_dev, "%s: error submitting buffer\n",
-@@ -665,7 +687,9 @@ static void bm2835_mmal_unlock(struct vb
- 
- static const struct vb2_ops bm2835_mmal_video_qops = {
- 	.queue_setup = queue_setup,
-+	.buf_init = buffer_init,
- 	.buf_prepare = buffer_prepare,
-+	.buf_cleanup = buffer_cleanup,
- 	.buf_queue = buffer_queue,
- 	.start_streaming = start_streaming,
- 	.stop_streaming = stop_streaming,
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h
-@@ -22,6 +22,8 @@
- /** Special value signalling that time is not known */
- #define MMAL_TIME_UNKNOWN (1LL<<63)
- 
-+struct mmal_msg_context;
-+
- /* mapping between v4l and mmal video modes */
- struct mmal_fmt {
- 	char  *name;
-@@ -46,6 +48,8 @@ struct mmal_buffer {
- 
- 	void *buffer; /* buffer pointer */
- 	unsigned long buffer_size; /* size of allocated buffer */
-+
-+	struct mmal_msg_context *msg_context;
- };
- 
- /* */
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -324,8 +324,6 @@ static void buffer_work_cb(struct work_s
- 					    msg_context->u.bulk.dts,
- 					    msg_context->u.bulk.pts);
- 
--	/* release message context */
--	release_msg_context(msg_context);
- }
- 
- /* enqueue a bulk receive for a given message context */
-@@ -506,11 +504,13 @@ buffer_from_host(struct vchiq_mmal_insta
- 		return -EINTR;
- 
- 	/* get context */
--	msg_context = get_msg_context(instance);
--	if (IS_ERR(msg_context)) {
--		ret = PTR_ERR(msg_context);
-+	if (!buf->msg_context) {
-+		pr_err("%s: msg_context not allocated, buf %p\n", __func__,
-+		       buf);
-+		ret = -EINVAL;
- 		goto unlock;
- 	}
-+	msg_context = buf->msg_context;
- 
- 	/* store bulk message context for when data arrives */
- 	msg_context->u.bulk.instance = instance;
-@@ -560,11 +560,6 @@ buffer_from_host(struct vchiq_mmal_insta
- 					sizeof(struct mmal_msg_header) +
- 					sizeof(m.u.buffer_from_host));
- 
--	if (ret != 0) {
--		release_msg_context(msg_context);
--		/* todo: is this correct error value? */
--	}
--
- 	vchi_service_release(instance->handle);
- 
- unlock:
-@@ -1779,6 +1774,29 @@ int vchiq_mmal_submit_buffer(struct vchi
- 
- 	return 0;
- }
-+
-+int mmal_vchi_buffer_init(struct vchiq_mmal_instance *instance,
-+			  struct mmal_buffer *buf)
-+{
-+	struct mmal_msg_context *msg_context = get_msg_context(instance);
-+
-+	if (IS_ERR(msg_context))
-+		return (PTR_ERR(msg_context));
-+
-+	buf->msg_context = msg_context;
-+	return 0;
-+}
-+
-+int mmal_vchi_buffer_cleanup(struct mmal_buffer *buf)
-+{
-+	struct mmal_msg_context *msg_context = buf->msg_context;
-+
-+	if (msg_context)
-+		release_msg_context(msg_context);
-+	buf->msg_context = NULL;
-+
-+	return 0;
-+}
- 
- /* Initialise a mmal component and its ports
-  *
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-@@ -171,4 +171,7 @@ int vchiq_mmal_submit_buffer(struct vchi
- 			     struct vchiq_mmal_port *port,
- 			     struct mmal_buffer *buf);
- 
-+int mmal_vchi_buffer_init(struct vchiq_mmal_instance *instance,
-+			  struct mmal_buffer *buf);
-+int mmal_vchi_buffer_cleanup(struct mmal_buffer *buf);
- #endif /* MMAL_VCHIQ_H */
diff --git a/target/linux/brcm2708/patches-4.14/950-0369-staging-bcm2835-camera-Remove-bulk_mutex-as-it-is-no.patch b/target/linux/brcm2708/patches-4.14/950-0369-staging-bcm2835-camera-Remove-bulk_mutex-as-it-is-no.patch
deleted file mode 100644
index 7cae80689..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0369-staging-bcm2835-camera-Remove-bulk_mutex-as-it-is-no.patch
+++ /dev/null
@@ -1,154 +0,0 @@
-From 5d8eefe0b0b10b346c76cda1c99bceca33d66aac Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:09 -0700
-Subject: [PATCH 369/454] staging: bcm2835-camera: Remove bulk_mutex as it is
- not required
-
-commit 71fcbc4740ab24c5208a24cf48a8190dc8f5d9ae upstream.
-
-There is no requirement to serialise bulk transfers as that is all
-done in VCHI, and if a second MMAL_MSG_TYPE_BUFFER_TO_HOST happened
-before the VCHI_CALLBACK_BULK_RECEIVED, then the service_callback
-thread is deadlocked.
-
-Remove the bulk_mutex so that multiple receives can be scheduled at a
-time.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../vc04_services/bcm2835-camera/mmal-vchiq.c | 48 +------------------
- 1 file changed, 1 insertion(+), 47 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -165,9 +165,6 @@ struct vchiq_mmal_instance {
- 	/* ensure serialised access to service */
- 	struct mutex vchiq_mutex;
- 
--	/* ensure serialised access to bulk operations */
--	struct mutex bulk_mutex;
--
- 	/* vmalloc page to receive scratch bulk xfers into */
- 	void *bulk_scratch;
- 
-@@ -335,13 +332,6 @@ static int bulk_receive(struct vchiq_mma
- 	unsigned long flags = 0;
- 	int ret;
- 
--	/* bulk mutex stops other bulk operations while we have a
--	 * receive in progress - released in callback
--	 */
--	ret = mutex_lock_interruptible(&instance->bulk_mutex);
--	if (ret != 0)
--		return ret;
--
- 	rd_len = msg->u.buffer_from_host.buffer_header.length;
- 
- 	/* take buffer from queue */
-@@ -360,8 +350,6 @@ static int bulk_receive(struct vchiq_mma
- 		 * waiting bulk receive?
- 		 */
- 
--		mutex_unlock(&instance->bulk_mutex);
--
- 		return -EINVAL;
- 	}
- 
-@@ -402,11 +390,6 @@ static int bulk_receive(struct vchiq_mma
- 
- 	vchi_service_release(instance->handle);
- 
--	if (ret != 0) {
--		/* callback will not be clearing the mutex */
--		mutex_unlock(&instance->bulk_mutex);
--	}
--
- 	return ret;
- }
- 
-@@ -416,13 +399,6 @@ static int dummy_bulk_receive(struct vch
- {
- 	int ret;
- 
--	/* bulk mutex stops other bulk operations while we have a
--	 * receive in progress - released in callback
--	 */
--	ret = mutex_lock_interruptible(&instance->bulk_mutex);
--	if (ret != 0)
--		return ret;
--
- 	/* zero length indicates this was a dummy transfer */
- 	msg_context->u.bulk.buffer_used = 0;
- 
-@@ -438,11 +414,6 @@ static int dummy_bulk_receive(struct vch
- 
- 	vchi_service_release(instance->handle);
- 
--	if (ret != 0) {
--		/* callback will not be clearing the mutex */
--		mutex_unlock(&instance->bulk_mutex);
--	}
--
- 	return ret;
- }
- 
-@@ -497,18 +468,11 @@ buffer_from_host(struct vchiq_mmal_insta
- 
- 	pr_debug("instance:%p buffer:%p\n", instance->handle, buf);
- 
--	/* bulk mutex stops other bulk operations while we
--	 * have a receive in progress
--	 */
--	if (mutex_lock_interruptible(&instance->bulk_mutex))
--		return -EINTR;
--
- 	/* get context */
- 	if (!buf->msg_context) {
- 		pr_err("%s: msg_context not allocated, buf %p\n", __func__,
- 		       buf);
--		ret = -EINVAL;
--		goto unlock;
-+		return -EINVAL;
- 	}
- 	msg_context = buf->msg_context;
- 
-@@ -562,9 +526,6 @@ buffer_from_host(struct vchiq_mmal_insta
- 
- 	vchi_service_release(instance->handle);
- 
--unlock:
--	mutex_unlock(&instance->bulk_mutex);
--
- 	return ret;
- }
- 
-@@ -688,9 +649,6 @@ static void buffer_to_host_cb(struct vch
- static void bulk_receive_cb(struct vchiq_mmal_instance *instance,
- 			    struct mmal_msg_context *msg_context)
- {
--	/* bulk receive operation complete */
--	mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex);
--
- 	/* replace the buffer header */
- 	port_buffer_from_host(msg_context->u.bulk.instance,
- 			      msg_context->u.bulk.port);
-@@ -706,9 +664,6 @@ static void bulk_abort_cb(struct vchiq_m
- {
- 	pr_err("%s: bulk ABORTED msg_context:%p\n", __func__, msg_context);
- 
--	/* bulk receive operation complete */
--	mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex);
--
- 	/* replace the buffer header */
- 	port_buffer_from_host(msg_context->u.bulk.instance,
- 			      msg_context->u.bulk.port);
-@@ -2047,7 +2002,6 @@ int vchiq_mmal_init(struct vchiq_mmal_in
- 		return -ENOMEM;
- 
- 	mutex_init(&instance->vchiq_mutex);
--	mutex_init(&instance->bulk_mutex);
- 
- 	instance->bulk_scratch = vmalloc(PAGE_SIZE);
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0370-staging-bcm2835-camera-Match-MMAL-buffer-count-to-V4.patch b/target/linux/brcm2708/patches-4.14/950-0370-staging-bcm2835-camera-Match-MMAL-buffer-count-to-V4.patch
deleted file mode 100644
index 2e07fa136..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0370-staging-bcm2835-camera-Match-MMAL-buffer-count-to-V4.patch
+++ /dev/null
@@ -1,115 +0,0 @@
-From 84ab2b48fc6834e44ef2d6cec5b2d21285090f88 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:10 -0700
-Subject: [PATCH 370/454] staging: bcm2835-camera: Match MMAL buffer count to
- V4L2.
-
-commit 7cc31d57f399b00f96ce295d5b86426b95d9076f upstream.
-
-For historical reasons, the number of buffers passed to the VPU over
-MMAL did not match that passed from V4L2.  That is a silly situation
-as the driver has to duplicate serialisation and other functions that
-have already been implemented in V4L2/videobuf2.
-
-As we had more V4L2 buffers than MMAL ones, the MMAL buffer headers
-were returned to the VPU immediately on being filled, which is now
-invalid.
-
-Match the number of buffers notified in queue_setup with that used in
-MMAL.  Return buffers only when we get them from V4L2.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../bcm2835-camera/bcm2835-camera.c           |  6 ++++--
- .../vc04_services/bcm2835-camera/mmal-vchiq.c | 21 +------------------
- .../vc04_services/bcm2835-camera/mmal-vchiq.h |  4 ----
- 3 files changed, 5 insertions(+), 26 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -262,8 +262,10 @@ static int queue_setup(struct vb2_queue
- 		return -EINVAL;
- 	}
- 
--	if (*nbuffers < (dev->capture.port->current_buffer.num + 2))
--		*nbuffers = (dev->capture.port->current_buffer.num + 2);
-+	if (*nbuffers < dev->capture.port->minimum_buffer.num)
-+		*nbuffers = dev->capture.port->minimum_buffer.num;
-+
-+	dev->capture.port->current_buffer.num = *nbuffers;
- 
- 	*nplanes = 1;
- 
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -548,7 +548,6 @@ static int port_buffer_from_host(struct
- 	/* peek buffer from queue */
- 	spin_lock_irqsave(&port->slock, flags);
- 	if (list_empty(&port->buffers)) {
--		port->buffer_underflow++;
- 		spin_unlock_irqrestore(&port->slock, flags);
- 		return -ENOSPC;
- 	}
-@@ -639,9 +638,6 @@ static void buffer_to_host_cb(struct vch
- 		    msg->u.buffer_from_host.payload_in_message;
- 	}
- 
--	/* replace the buffer header */
--	port_buffer_from_host(instance, msg_context->u.bulk.port);
--
- 	/* schedule the port callback */
- 	schedule_work(&msg_context->u.bulk.work);
- }
-@@ -649,10 +645,6 @@ static void buffer_to_host_cb(struct vch
- static void bulk_receive_cb(struct vchiq_mmal_instance *instance,
- 			    struct mmal_msg_context *msg_context)
- {
--	/* replace the buffer header */
--	port_buffer_from_host(msg_context->u.bulk.instance,
--			      msg_context->u.bulk.port);
--
- 	msg_context->u.bulk.status = 0;
- 
- 	/* schedule the port callback */
-@@ -664,10 +656,6 @@ static void bulk_abort_cb(struct vchiq_m
- {
- 	pr_err("%s: bulk ABORTED msg_context:%p\n", __func__, msg_context);
- 
--	/* replace the buffer header */
--	port_buffer_from_host(msg_context->u.bulk.instance,
--			      msg_context->u.bulk.port);
--
- 	msg_context->u.bulk.status = -EINTR;
- 
- 	schedule_work(&msg_context->u.bulk.work);
-@@ -1718,14 +1706,7 @@ int vchiq_mmal_submit_buffer(struct vchi
- 	list_add_tail(&buffer->list, &port->buffers);
- 	spin_unlock_irqrestore(&port->slock, flags);
- 
--	/* the port previously underflowed because it was missing a
--	 * mmal_buffer which has just been added, submit that buffer
--	 * to the mmal service.
--	 */
--	if (port->buffer_underflow) {
--		port_buffer_from_host(instance, port);
--		port->buffer_underflow--;
--	}
-+	port_buffer_from_host(instance, port);
- 
- 	return 0;
- }
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-@@ -82,10 +82,6 @@ struct vchiq_mmal_port {
- 	struct list_head buffers;
- 	/* lock to serialise adding and removing buffers from list */
- 	spinlock_t slock;
--	/* count of how many buffer header refils have failed because
--	 * there was no buffer to satisfy them
--	 */
--	int buffer_underflow;
- 	/* callback on buffer completion */
- 	vchiq_mmal_buffer_cb buffer_cb;
- 	/* callback context */
diff --git a/target/linux/brcm2708/patches-4.14/950-0371-staging-bcm2835-camera-Remove-V4L2-MMAL-buffer-remap.patch b/target/linux/brcm2708/patches-4.14/950-0371-staging-bcm2835-camera-Remove-V4L2-MMAL-buffer-remap.patch
deleted file mode 100644
index c3d5ea729..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0371-staging-bcm2835-camera-Remove-V4L2-MMAL-buffer-remap.patch
+++ /dev/null
@@ -1,239 +0,0 @@
-From 0d3b557ef5494adf6458fe4e6f4a9b41e6e0d12a Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:11 -0700
-Subject: [PATCH 371/454] staging: bcm2835-camera: Remove V4L2/MMAL buffer
- remapping
-
-commit 9384167070713570a25f854d641979e94163c425 upstream
-
-The MMAL and V4L2 buffers had been disassociated, and linked on
-demand.  Seeing as both are finite and low in number, and we now have
-the same number of each, link them for the duration.  This removes the
-complexity of maintaining lists as the struct mmal_buffer context
-comes back from the VPU, so we can directly link back to the relevant
-V4L2 buffer.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../bcm2835-camera/bcm2835-camera.c           |   7 +-
- .../vc04_services/bcm2835-camera/mmal-vchiq.c | 109 ++++--------------
- 2 files changed, 29 insertions(+), 87 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -301,8 +301,8 @@ static int buffer_prepare(struct vb2_buf
- 	struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue);
- 	unsigned long size;
- 
--	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
--		 __func__, dev);
-+	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p, vb %p\n",
-+		 __func__, dev, vb);
- 
- 	BUG_ON(!dev->capture.port);
- 	BUG_ON(!dev->capture.fmt);
-@@ -522,7 +522,8 @@ static void buffer_queue(struct vb2_buff
- 	int ret;
- 
- 	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--		 "%s: dev:%p buf:%p\n", __func__, dev, buf);
-+		 "%s: dev:%p buf:%p, idx %u\n",
-+		 __func__, dev, buf, vb2->vb2_buf.index);
- 
- 	ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf);
- 	if (ret < 0)
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -329,16 +329,12 @@ static int bulk_receive(struct vchiq_mma
- 			struct mmal_msg_context *msg_context)
- {
- 	unsigned long rd_len;
--	unsigned long flags = 0;
- 	int ret;
- 
- 	rd_len = msg->u.buffer_from_host.buffer_header.length;
- 
--	/* take buffer from queue */
--	spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags);
--	if (list_empty(&msg_context->u.bulk.port->buffers)) {
--		spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
--		pr_err("buffer list empty trying to submit bulk receive\n");
-+	if (!msg_context->u.bulk.buffer) {
-+		pr_err("bulk.buffer not configured - error in buffer_from_host\n");
- 
- 		/* todo: this is a serious error, we should never have
- 		 * committed a buffer_to_host operation to the mmal
-@@ -353,13 +349,6 @@ static int bulk_receive(struct vchiq_mma
- 		return -EINVAL;
- 	}
- 
--	msg_context->u.bulk.buffer =
--	    list_entry(msg_context->u.bulk.port->buffers.next,
--		       struct mmal_buffer, list);
--	list_del(&msg_context->u.bulk.buffer->list);
--
--	spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
--
- 	/* ensure we do not overrun the available buffer */
- 	if (rd_len > msg_context->u.bulk.buffer->buffer_size) {
- 		rd_len = msg_context->u.bulk.buffer->buffer_size;
-@@ -422,31 +411,6 @@ static int inline_receive(struct vchiq_m
- 			  struct mmal_msg *msg,
- 			  struct mmal_msg_context *msg_context)
- {
--	unsigned long flags = 0;
--
--	/* take buffer from queue */
--	spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags);
--	if (list_empty(&msg_context->u.bulk.port->buffers)) {
--		spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
--		pr_err("buffer list empty trying to receive inline\n");
--
--		/* todo: this is a serious error, we should never have
--		 * committed a buffer_to_host operation to the mmal
--		 * port without the buffer to back it up (with
--		 * underflow handling) and there is no obvious way to
--		 * deal with this. Less bad than the bulk case as we
--		 * can just drop this on the floor but...unhelpful
--		 */
--		return -EINVAL;
--	}
--
--	msg_context->u.bulk.buffer =
--	    list_entry(msg_context->u.bulk.port->buffers.next,
--		       struct mmal_buffer, list);
--	list_del(&msg_context->u.bulk.buffer->list);
--
--	spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags);
--
- 	memcpy(msg_context->u.bulk.buffer->buffer,
- 	       msg->u.buffer_from_host.short_data,
- 	       msg->u.buffer_from_host.payload_in_message);
-@@ -466,6 +430,9 @@ buffer_from_host(struct vchiq_mmal_insta
- 	struct mmal_msg m;
- 	int ret;
- 
-+	if (!port->enabled)
-+		return -EINVAL;
-+
- 	pr_debug("instance:%p buffer:%p\n", instance->handle, buf);
- 
- 	/* get context */
-@@ -479,7 +446,7 @@ buffer_from_host(struct vchiq_mmal_insta
- 	/* store bulk message context for when data arrives */
- 	msg_context->u.bulk.instance = instance;
- 	msg_context->u.bulk.port = port;
--	msg_context->u.bulk.buffer = NULL;	/* not valid until bulk xfer */
-+	msg_context->u.bulk.buffer = buf;
- 	msg_context->u.bulk.buffer_used = 0;
- 
- 	/* initialise work structure ready to schedule callback */
-@@ -529,43 +496,6 @@ buffer_from_host(struct vchiq_mmal_insta
- 	return ret;
- }
- 
--/* submit a buffer to the mmal sevice
-- *
-- * the buffer_from_host uses size data from the ports next available
-- * mmal_buffer and deals with there being no buffer available by
-- * incrementing the underflow for later
-- */
--static int port_buffer_from_host(struct vchiq_mmal_instance *instance,
--				 struct vchiq_mmal_port *port)
--{
--	int ret;
--	struct mmal_buffer *buf;
--	unsigned long flags = 0;
--
--	if (!port->enabled)
--		return -EINVAL;
--
--	/* peek buffer from queue */
--	spin_lock_irqsave(&port->slock, flags);
--	if (list_empty(&port->buffers)) {
--		spin_unlock_irqrestore(&port->slock, flags);
--		return -ENOSPC;
--	}
--
--	buf = list_entry(port->buffers.next, struct mmal_buffer, list);
--
--	spin_unlock_irqrestore(&port->slock, flags);
--
--	/* issue buffer to mmal service */
--	ret = buffer_from_host(instance, port, buf);
--	if (ret) {
--		pr_err("adding buffer header failed\n");
--		/* todo: how should this be dealt with */
--	}
--
--	return ret;
--}
--
- /* deals with receipt of buffer to host message */
- static void buffer_to_host_cb(struct vchiq_mmal_instance *instance,
- 			      struct mmal_msg *msg, u32 msg_len)
-@@ -1425,7 +1355,14 @@ static int port_disable(struct vchiq_mma
- 	ret = port_action_port(instance, port,
- 			       MMAL_MSG_PORT_ACTION_TYPE_DISABLE);
- 	if (ret == 0) {
--		/* drain all queued buffers on port */
-+		/*
-+		 * Drain all queued buffers on port. This should only
-+		 * apply to buffers that have been queued before the port
-+		 * has been enabled. If the port has been enabled and buffers
-+		 * passed, then the buffers should have been removed from this
-+		 * list, and we should get the relevant callbacks via VCHIQ
-+		 * to release the buffers.
-+		 */
- 		spin_lock_irqsave(&port->slock, flags);
- 
- 		list_for_each_safe(buf_head, q, &port->buffers) {
-@@ -1454,7 +1391,7 @@ static int port_enable(struct vchiq_mmal
- 		       struct vchiq_mmal_port *port)
- {
- 	unsigned int hdr_count;
--	struct list_head *buf_head;
-+	struct list_head *q, *buf_head;
- 	int ret;
- 
- 	if (port->enabled)
-@@ -1480,7 +1417,7 @@ static int port_enable(struct vchiq_mmal
- 	if (port->buffer_cb) {
- 		/* send buffer headers to videocore */
- 		hdr_count = 1;
--		list_for_each(buf_head, &port->buffers) {
-+		list_for_each_safe(buf_head, q, &port->buffers) {
- 			struct mmal_buffer *mmalbuf;
- 
- 			mmalbuf = list_entry(buf_head, struct mmal_buffer,
-@@ -1489,6 +1426,7 @@ static int port_enable(struct vchiq_mmal
- 			if (ret)
- 				goto done;
- 
-+			list_del(buf_head);
- 			hdr_count++;
- 			if (hdr_count > port->current_buffer.num)
- 				break;
-@@ -1701,12 +1639,15 @@ int vchiq_mmal_submit_buffer(struct vchi
- 			     struct mmal_buffer *buffer)
- {
- 	unsigned long flags = 0;
-+	int ret;
- 
--	spin_lock_irqsave(&port->slock, flags);
--	list_add_tail(&buffer->list, &port->buffers);
--	spin_unlock_irqrestore(&port->slock, flags);
--
--	port_buffer_from_host(instance, port);
-+	ret = buffer_from_host(instance, port, buffer);
-+	if (ret == -EINVAL) {
-+		/* Port is disabled. Queue for when it is enabled. */
-+		spin_lock_irqsave(&port->slock, flags);
-+		list_add_tail(&buffer->list, &port->buffers);
-+		spin_unlock_irqrestore(&port->slock, flags);
-+	}
- 
- 	return 0;
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0372-staging-bcm2835-camera-Add-multiple-include-protecti.patch b/target/linux/brcm2708/patches-4.14/950-0372-staging-bcm2835-camera-Add-multiple-include-protecti.patch
deleted file mode 100644
index b6d7667c8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0372-staging-bcm2835-camera-Add-multiple-include-protecti.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 1ae2f10aaf05db61db9e58fa035c13eea2d5f0b6 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:12 -0700
-Subject: [PATCH 372/454] staging: bcm2835-camera: Add multiple include
- protection
-
-commit 514a6ab198c6b8bc78e681288a582972641e713a upstream.
-
-mmal-parameters.h didn't have the normal
-
-...
-
-protection to stop it being included multiple times.  Add it.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../staging/vc04_services/bcm2835-camera/mmal-parameters.h   | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h
-@@ -21,6 +21,9 @@
-  * @{
-  */
- 
-+#ifndef __MMAL_PARAMETERS_H
-+#define __MMAL_PARAMETERS_H
-+
- /** Common parameter ID group, used with many types of component. */
- #define MMAL_PARAMETER_GROUP_COMMON            (0<<16)
- /** Camera-specific parameter ID group. */
-@@ -685,3 +688,5 @@ struct mmal_parameter_camera_info_t {
- 	struct mmal_parameter_camera_info_flash_t
- 				flashes[MMAL_PARAMETER_CAMERA_INFO_MAX_FLASHES];
- };
-+
-+#endif
diff --git a/target/linux/brcm2708/patches-4.14/950-0373-staging-bcm2835-camera-Move-struct-vchiq_mmal_rect.patch b/target/linux/brcm2708/patches-4.14/950-0373-staging-bcm2835-camera-Move-struct-vchiq_mmal_rect.patch
deleted file mode 100644
index d5b8593af..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0373-staging-bcm2835-camera-Move-struct-vchiq_mmal_rect.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 7df25059f84e7dab7fc8d733b83f016b62a33372 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:13 -0700
-Subject: [PATCH 373/454] staging: bcm2835-camera: Move struct vchiq_mmal_rect
-
-commit 84adcb14133ed2412d54355539a8ab4d6a3fcabc upstream.
-
-struct vchiq_mmal_rect is only referenced from mmal-parameters.h, yet
-was defined in mmal-vchiq.h.
-
-Move it to avoid having to include multiple headers for no reason.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../vc04_services/bcm2835-camera/mmal-parameters.h        | 8 ++++++++
- drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h | 8 --------
- 2 files changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h
-@@ -567,6 +567,14 @@ enum mmal_parameter_displayset {
- 	MMAL_DISPLAY_SET_ALPHA = 0x400,
- };
- 
-+/* rectangle, used lots so it gets its own struct */
-+struct vchiq_mmal_rect {
-+	s32 x;
-+	s32 y;
-+	s32 width;
-+	s32 height;
-+};
-+
- struct mmal_parameter_displayregion {
- 	/** Bitfield that indicates which fields are set and should be
- 	 * used. All other fields will maintain their current value.
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-@@ -35,14 +35,6 @@ enum vchiq_mmal_es_type {
- 	MMAL_ES_TYPE_SUBPICTURE   /**< Sub-picture elementary stream */
- };
- 
--/* rectangle, used lots so it gets its own struct */
--struct vchiq_mmal_rect {
--	s32 x;
--	s32 y;
--	s32 width;
--	s32 height;
--};
--
- struct vchiq_mmal_port_buffer {
- 	unsigned int num; /* number of buffers */
- 	u32 size; /* size of buffers */
diff --git a/target/linux/brcm2708/patches-4.14/950-0374-staging-bcm2835-camera-Replace-BUG_ON-with-return-er.patch b/target/linux/brcm2708/patches-4.14/950-0374-staging-bcm2835-camera-Replace-BUG_ON-with-return-er.patch
deleted file mode 100644
index 009891c40..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0374-staging-bcm2835-camera-Replace-BUG_ON-with-return-er.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 4beea0c16ceaefc78e2fb6b5a2a0548bd6d04ee6 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:14 -0700
-Subject: [PATCH 374/454] staging: bcm2835-camera: Replace BUG_ON with return
- error
-
-commit 84db34cd720964adf0c9019d6d1b4de1cb26d1de upstream.
-
-The error conditions don't warrant taking the kernel down, so remove
-BUG_ON.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../staging/vc04_services/bcm2835-camera/bcm2835-camera.c  | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -304,8 +304,8 @@ static int buffer_prepare(struct vb2_buf
- 	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p, vb %p\n",
- 		 __func__, dev, vb);
- 
--	BUG_ON(!dev->capture.port);
--	BUG_ON(!dev->capture.fmt);
-+	if (!dev->capture.port || !dev->capture.fmt)
-+		return -ENODEV;
- 
- 	size = dev->capture.stride * dev->capture.height;
- 	if (vb2_plane_size(vb, 0) < size) {
-@@ -1050,7 +1050,8 @@ static int mmal_setup_components(struct
- 	struct mmal_fmt *mfmt = get_format(f);
- 	u32 remove_padding;
- 
--	BUG_ON(!mfmt);
-+	if (!mfmt)
-+		return -EINVAL;
- 
- 	if (dev->capture.encode_component) {
- 		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
diff --git a/target/linux/brcm2708/patches-4.14/950-0375-staging-bcm2835-camera-Fix-comment-typos.patch b/target/linux/brcm2708/patches-4.14/950-0375-staging-bcm2835-camera-Fix-comment-typos.patch
deleted file mode 100644
index 3da7e12c2..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0375-staging-bcm2835-camera-Fix-comment-typos.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 7d5ca722a638236b7a7651d66aff2a99a0f20755 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:15 -0700
-Subject: [PATCH 375/454] staging: bcm2835-camera: Fix comment typos.
-
-commit a9e14815aaf7f620945950cb5490b8610f9a5700 upstream.
-
-Fix a typo flagged by checkpatch, and another in the same line.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/staging/vc04_services/bcm2835-camera/mmal-msg-port.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-port.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-port.h
-@@ -40,7 +40,7 @@ enum mmal_port_type {
-  *
-  * most elements are informational only, the pointer values for
-  * interogation messages are generally provided as additional
-- * strucures within the message. When used to set values only teh
-+ * structures within the message. When used to set values only the
-  * buffer_num, buffer_size and userdata parameters are writable.
-  */
- struct mmal_port {
diff --git a/target/linux/brcm2708/patches-4.14/950-0376-staging-bcm2835-camera-Fix-indentation-of-tables.patch b/target/linux/brcm2708/patches-4.14/950-0376-staging-bcm2835-camera-Fix-indentation-of-tables.patch
deleted file mode 100644
index f002ecd53..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0376-staging-bcm2835-camera-Fix-indentation-of-tables.patch
+++ /dev/null
@@ -1,321 +0,0 @@
-From 212b50d76ee63b58a59ccb687719583f72ea5e23 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 10 May 2018 12:42:17 -0700
-Subject: [PATCH 376/454] staging: bcm2835-camera: Fix indentation of tables
-
-commit 6166045e7964067dba0da43a122de27ceb49be7b upstream
-
-As requested by Mauro Carvalho Chehab in review.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 289 +++++++++---------
- 1 file changed, 139 insertions(+), 150 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -81,145 +81,132 @@ static const struct v4l2_fract
- /* video formats */
- static struct mmal_fmt formats[] = {
- 	{
--	 .name = "4:2:0, planar, YUV",
--	 .fourcc = V4L2_PIX_FMT_YUV420,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_I420,
--	 .depth = 12,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 1,
--	 .remove_padding = 1,
--	 },
--	{
--	 .name = "4:2:2, packed, YUYV",
--	 .fourcc = V4L2_PIX_FMT_YUYV,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_YUYV,
--	 .depth = 16,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 2,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "RGB24 (LE)",
--	 .fourcc = V4L2_PIX_FMT_RGB24,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_RGB24,
--	 .depth = 24,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 3,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "JPEG",
--	 .fourcc = V4L2_PIX_FMT_JPEG,
--	 .flags = V4L2_FMT_FLAG_COMPRESSED,
--	 .mmal = MMAL_ENCODING_JPEG,
--	 .depth = 8,
--	 .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE,
--	 .ybbp = 0,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "H264",
--	 .fourcc = V4L2_PIX_FMT_H264,
--	 .flags = V4L2_FMT_FLAG_COMPRESSED,
--	 .mmal = MMAL_ENCODING_H264,
--	 .depth = 8,
--	 .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
--	 .ybbp = 0,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "MJPEG",
--	 .fourcc = V4L2_PIX_FMT_MJPEG,
--	 .flags = V4L2_FMT_FLAG_COMPRESSED,
--	 .mmal = MMAL_ENCODING_MJPEG,
--	 .depth = 8,
--	 .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
--	 .ybbp = 0,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "4:2:2, packed, YVYU",
--	 .fourcc = V4L2_PIX_FMT_YVYU,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_YVYU,
--	 .depth = 16,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 2,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "4:2:2, packed, VYUY",
--	 .fourcc = V4L2_PIX_FMT_VYUY,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_VYUY,
--	 .depth = 16,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 2,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "4:2:2, packed, UYVY",
--	 .fourcc = V4L2_PIX_FMT_UYVY,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_UYVY,
--	 .depth = 16,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 2,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "4:2:0, planar, NV12",
--	 .fourcc = V4L2_PIX_FMT_NV12,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_NV12,
--	 .depth = 12,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 1,
--	 .remove_padding = 1,
--	 },
--	{
--	 .name = "RGB24 (BE)",
--	 .fourcc = V4L2_PIX_FMT_BGR24,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_BGR24,
--	 .depth = 24,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 3,
--	 .remove_padding = 0,
--	 },
--	{
--	 .name = "4:2:0, planar, YVU",
--	 .fourcc = V4L2_PIX_FMT_YVU420,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_YV12,
--	 .depth = 12,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 1,
--	 .remove_padding = 1,
--	 },
--	{
--	 .name = "4:2:0, planar, NV21",
--	 .fourcc = V4L2_PIX_FMT_NV21,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_NV21,
--	 .depth = 12,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 1,
--	 .remove_padding = 1,
--	 },
--	{
--	 .name = "RGB32 (BE)",
--	 .fourcc = V4L2_PIX_FMT_BGR32,
--	 .flags = 0,
--	 .mmal = MMAL_ENCODING_BGRA,
--	 .depth = 32,
--	 .mmal_component = MMAL_COMPONENT_CAMERA,
--	 .ybbp = 4,
--	 .remove_padding = 0,
--	 },
-+		.name = "4:2:0, planar, YUV",
-+		.fourcc = V4L2_PIX_FMT_YUV420,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_I420,
-+		.depth = 12,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 1,
-+		.remove_padding = 1,
-+	}, {
-+		.name = "4:2:2, packed, YUYV",
-+		.fourcc = V4L2_PIX_FMT_YUYV,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_YUYV,
-+		.depth = 16,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 2,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "RGB24 (LE)",
-+		.fourcc = V4L2_PIX_FMT_RGB24,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_RGB24,
-+		.depth = 24,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 3,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "JPEG",
-+		.fourcc = V4L2_PIX_FMT_JPEG,
-+		.flags = V4L2_FMT_FLAG_COMPRESSED,
-+		.mmal = MMAL_ENCODING_JPEG,
-+		.depth = 8,
-+		.mmal_component = MMAL_COMPONENT_IMAGE_ENCODE,
-+		.ybbp = 0,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "H264",
-+		.fourcc = V4L2_PIX_FMT_H264,
-+		.flags = V4L2_FMT_FLAG_COMPRESSED,
-+		.mmal = MMAL_ENCODING_H264,
-+		.depth = 8,
-+		.mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
-+		.ybbp = 0,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "MJPEG",
-+		.fourcc = V4L2_PIX_FMT_MJPEG,
-+		.flags = V4L2_FMT_FLAG_COMPRESSED,
-+		.mmal = MMAL_ENCODING_MJPEG,
-+		.depth = 8,
-+		.mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
-+		.ybbp = 0,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "4:2:2, packed, YVYU",
-+		.fourcc = V4L2_PIX_FMT_YVYU,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_YVYU,
-+		.depth = 16,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 2,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "4:2:2, packed, VYUY",
-+		.fourcc = V4L2_PIX_FMT_VYUY,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_VYUY,
-+		.depth = 16,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 2,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "4:2:2, packed, UYVY",
-+		.fourcc = V4L2_PIX_FMT_UYVY,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_UYVY,
-+		.depth = 16,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 2,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "4:2:0, planar, NV12",
-+		.fourcc = V4L2_PIX_FMT_NV12,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_NV12,
-+		.depth = 12,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 1,
-+		.remove_padding = 1,
-+	}, {
-+		.name = "RGB24 (BE)",
-+		.fourcc = V4L2_PIX_FMT_BGR24,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_BGR24,
-+		.depth = 24,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 3,
-+		.remove_padding = 0,
-+	}, {
-+		.name = "4:2:0, planar, YVU",
-+		.fourcc = V4L2_PIX_FMT_YVU420,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_YV12,
-+		.depth = 12,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 1,
-+		.remove_padding = 1,
-+	}, {
-+		.name = "4:2:0, planar, NV21",
-+		.fourcc = V4L2_PIX_FMT_NV21,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_NV21,
-+		.depth = 12,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 1,
-+		.remove_padding = 1,
-+	}, {
-+		.name = "RGB32 (BE)",
-+		.fourcc = V4L2_PIX_FMT_BGR32,
-+		.flags = 0,
-+		.mmal = MMAL_ENCODING_BGRA,
-+		.depth = 32,
-+		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.ybbp = 4,
-+		.remove_padding = 0,
-+	},
- };
- 
- static struct mmal_fmt *get_format(struct v4l2_format *f)
-@@ -709,17 +696,19 @@ static int set_overlay_params(struct bm2
- 			      struct vchiq_mmal_port *port)
- {
- 	struct mmal_parameter_displayregion prev_config = {
--	.set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA |
--	    MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN,
--	.layer = PREVIEW_LAYER,
--	.alpha = dev->overlay.global_alpha,
--	.fullscreen = 0,
--	.dest_rect = {
--		      .x = dev->overlay.w.left,
--		      .y = dev->overlay.w.top,
--		      .width = dev->overlay.w.width,
--		      .height = dev->overlay.w.height,
--		      },
-+		.set =	MMAL_DISPLAY_SET_LAYER |
-+			MMAL_DISPLAY_SET_ALPHA |
-+			MMAL_DISPLAY_SET_DEST_RECT |
-+			MMAL_DISPLAY_SET_FULLSCREEN,
-+		.layer = PREVIEW_LAYER,
-+		.alpha = dev->overlay.global_alpha,
-+		.fullscreen = 0,
-+		.dest_rect = {
-+			.x = dev->overlay.w.left,
-+			.y = dev->overlay.w.top,
-+			.width = dev->overlay.w.width,
-+			.height = dev->overlay.w.height,
-+		},
- 	};
- 	return vchiq_mmal_port_parameter_set(dev->instance, port,
- 					     MMAL_PARAMETER_DISPLAYREGION,
diff --git a/target/linux/brcm2708/patches-4.14/950-0377-staging-bcm2835-camera-Fix-warnings-about-string-ops.patch b/target/linux/brcm2708/patches-4.14/950-0377-staging-bcm2835-camera-Fix-warnings-about-string-ops.patch
deleted file mode 100644
index 4cdef53f9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0377-staging-bcm2835-camera-Fix-warnings-about-string-ops.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 2c6ce48e18a2a95743de7a84faefd52d090c2a56 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Thu, 10 May 2018 12:42:18 -0700
-Subject: [PATCH 377/454] staging: bcm2835-camera: Fix warnings about string
- ops on v4l2 uapi.
-
-commit 40b73e16675ee2e77358ed1cfc3364c8bf000e4f upstream.
-
-The v4l2 uapi uses u8[] for strings, so cast those to char * to avoid
-compiler warnings about unsigned vs signed with sprintf() and friends.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../vc04_services/bcm2835-camera/bcm2835-camera.c    | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -726,7 +726,7 @@ static int vidioc_enum_fmt_vid_overlay(s
- 
- 	fmt = &formats[f->index];
- 
--	strlcpy(f->description, fmt->name, sizeof(f->description));
-+	strlcpy((char *)f->description, fmt->name, sizeof(f->description));
- 	f->pixelformat = fmt->fourcc;
- 	f->flags = fmt->flags;
- 
-@@ -884,7 +884,7 @@ static int vidioc_enum_input(struct file
- 		return -EINVAL;
- 
- 	inp->type = V4L2_INPUT_TYPE_CAMERA;
--	sprintf(inp->name, "Camera %u", inp->index);
-+	sprintf((char *)inp->name, "Camera %u", inp->index);
- 	return 0;
- }
- 
-@@ -912,11 +912,11 @@ static int vidioc_querycap(struct file *
- 
- 	vchiq_mmal_version(dev->instance, &major, &minor);
- 
--	strcpy(cap->driver, "bm2835 mmal");
--	snprintf(cap->card, sizeof(cap->card), "mmal service %d.%d",
-+	strcpy((char *)cap->driver, "bm2835 mmal");
-+	snprintf((char *)cap->card, sizeof(cap->card), "mmal service %d.%d",
- 		 major, minor);
- 
--	snprintf(cap->bus_info, sizeof(cap->bus_info),
-+	snprintf((char *)cap->bus_info, sizeof(cap->bus_info),
- 		 "platform:%s", dev->v4l2_dev.name);
- 	cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY |
- 	    V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
-@@ -935,7 +935,7 @@ static int vidioc_enum_fmt_vid_cap(struc
- 
- 	fmt = &formats[f->index];
- 
--	strlcpy(f->description, fmt->name, sizeof(f->description));
-+	strlcpy((char *)f->description, fmt->name, sizeof(f->description));
- 	f->pixelformat = fmt->fourcc;
- 	f->flags = fmt->flags;
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0378-staging-bcm2835-Remove-dead-code-related-to-framerat.patch b/target/linux/brcm2708/patches-4.14/950-0378-staging-bcm2835-Remove-dead-code-related-to-framerat.patch
deleted file mode 100644
index 7fcfdc866..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0378-staging-bcm2835-Remove-dead-code-related-to-framerat.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 6ad3bd1cb169213a3dfab84e2221ff40bb7a08f8 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Thu, 10 May 2018 12:42:19 -0700
-Subject: [PATCH 378/454] staging: bcm2835: Remove dead code related to
- framerate.
-
-commit aa4f227112dc8d6caf73f494deb4bbd5ecc6eec4 upstream.
-
-Fixes a compiler warning about a set-but-not-used variable. I think
-this was just leftover dead code from before set_framerate_params(),
-since that also sets up some mmal_parameter_rational structs for fps.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../staging/vc04_services/bcm2835-camera/bcm2835-camera.c    | 5 -----
- 1 file changed, 5 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -1430,7 +1430,6 @@ static int vidioc_s_parm(struct file *fi
- {
- 	struct bm2835_mmal_dev *dev = video_drvdata(file);
- 	struct v4l2_fract tpf;
--	struct mmal_parameter_rational fps_param;
- 
- 	if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
- 		return -EINVAL;
-@@ -1447,10 +1446,6 @@ static int vidioc_s_parm(struct file *fi
- 	parm->parm.capture.readbuffers  = 1;
- 	parm->parm.capture.capability   = V4L2_CAP_TIMEPERFRAME;
- 
--	fps_param.num = 0;	/* Select variable fps, and then use
--				 * FPS_RANGE to select the actual limits.
--				 */
--	fps_param.den = 1;
- 	set_framerate_params(dev);
- 
- 	return 0;
diff --git a/target/linux/brcm2708/patches-4.14/950-0379-staging-bcm2835-Fix-mmal_port_parameter_get-signed-u.patch b/target/linux/brcm2708/patches-4.14/950-0379-staging-bcm2835-Fix-mmal_port_parameter_get-signed-u.patch
deleted file mode 100644
index d8d8fb623..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0379-staging-bcm2835-Fix-mmal_port_parameter_get-signed-u.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 48d22b014512b2dac7e625748509c4360b79f085 Mon Sep 17 00:00:00 2001
-From: Eric Anholt <eric@anholt.net>
-Date: Thu, 10 May 2018 12:42:20 -0700
-Subject: [PATCH 379/454] staging: bcm2835: Fix mmal_port_parameter_get()
- signed/unsigned warnings.
-
-commit 9dabe666d33d00849b05c5c46cc31dec39004ba7 upstream
-
-The arg is a u32 *, so switch over to that in our declarations.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../staging/vc04_services/bcm2835-camera/bcm2835-camera.c   | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -522,7 +522,7 @@ static int start_streaming(struct vb2_qu
- {
- 	struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
- 	int ret;
--	int parameter_size;
-+	u32 parameter_size;
- 
- 	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
- 		 __func__, dev);
-@@ -1522,7 +1522,7 @@ static int get_num_cameras(struct vchiq_
- 	int ret;
- 	struct vchiq_mmal_component  *cam_info_component;
- 	struct mmal_parameter_camera_info_t cam_info = {0};
--	int param_size = sizeof(cam_info);
-+	u32 param_size = sizeof(cam_info);
- 	int i;
- 
- 	/* create a camera_info component */
-@@ -1586,7 +1586,7 @@ static int __init mmal_init(struct bm283
- 	int ret;
- 	struct mmal_es_format_local *format;
- 	u32 supported_encodings[MAX_SUPPORTED_ENCODINGS];
--	int param_size;
-+	u32 param_size;
- 	struct vchiq_mmal_component  *camera;
- 
- 	ret = vchiq_mmal_init(&dev->instance);
diff --git a/target/linux/brcm2708/patches-4.14/950-0380-staging-bcm2835-Use-BIT_ULL-macro.patch b/target/linux/brcm2708/patches-4.14/950-0380-staging-bcm2835-Use-BIT_ULL-macro.patch
deleted file mode 100644
index 8adf5e510..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0380-staging-bcm2835-Use-BIT_ULL-macro.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 773fe10cd3c4cfc266e7fab793fa8e1c0cda8db3 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Kilian=20K=C3=B6ppchen?= <kiliankoeppchen@googlemail.com>
-Date: Sun, 13 May 2018 18:21:34 +0200
-Subject: [PATCH 380/454] staging: bcm2835: Use BIT_ULL macro
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-commit 1e85394462d631e72d975556b2514038822fe840 upstream.
-
-This patch fixes the checkpatch.pl check hint:
-
-CHECK: Prefer using the BIT_ULL macro
-
-Signed-off-by: Kilian Köppchen <kiliankoeppchen@googlemail.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/staging/vc04_services/bcm2835-camera/mmal-common.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h
-@@ -20,7 +20,7 @@
- #define MMAL_MAGIC MMAL_FOURCC('m', 'm', 'a', 'l')
- 
- /** Special value signalling that time is not known */
--#define MMAL_TIME_UNKNOWN (1LL<<63)
-+#define MMAL_TIME_UNKNOWN BIT_ULL(63)
- 
- struct mmal_msg_context;
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0381-staging-vc04_services-no-need-to-check-debugfs-retur.patch b/target/linux/brcm2708/patches-4.14/950-0381-staging-vc04_services-no-need-to-check-debugfs-retur.patch
deleted file mode 100644
index 1a8cfd124..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0381-staging-vc04_services-no-need-to-check-debugfs-retur.patch
+++ /dev/null
@@ -1,217 +0,0 @@
-From 5e4d56448e08a7f4bf39e1b3f4c43916ff74d337 Mon Sep 17 00:00:00 2001
-From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Date: Fri, 1 Jun 2018 13:09:59 +0200
-Subject: [PATCH 381/454] staging: vc04_services: no need to check debugfs
- return values
-
-commit 0723103f8ba15a019bbcaf6f130d73d05337332f upstream
-
-When calling debugfs functions, there is no need to ever check the
-return value.  The function can work or not, but the code logic should
-never do something different based on this.
-
-Clean up the vchiq_arm code by not caring about the value of debugfs
-calls.  This ends up removing a number of lines of code that are not
-needed.
-
-Cc: Stefan Wahren <stefan.wahren@i2se.com>
-Cc: Kees Cook <keescook@chromium.org>
-Cc: Dan Carpenter <dan.carpenter@oracle.com>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Keerthi Reddy <keerthigd4990@gmail.com>
-Cc: linux-rpi-kernel@lists.infradead.org
-Cc: linux-arm-kernel@lists.infradead.org
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../interface/vchiq_arm/vchiq_arm.c           |  8 +-
- .../interface/vchiq_arm/vchiq_debugfs.c       | 73 +++----------------
- .../interface/vchiq_arm/vchiq_debugfs.h       |  4 +-
- 3 files changed, 15 insertions(+), 70 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
-@@ -1753,7 +1753,7 @@ vchiq_open(struct inode *inode, struct f
- 		instance->state = state;
- 		instance->pid = current->tgid;
- 
--		(void)vchiq_debugfs_add_instance(instance);
-+		vchiq_debugfs_add_instance(instance);
- 
- 		sema_init(&instance->insert_event, 0);
- 		sema_init(&instance->remove_event, 0);
-@@ -3437,9 +3437,7 @@ static int vchiq_probe(struct platform_d
- 		goto failed_device_create;
- 
- 	/* create debugfs entries */
--	err = vchiq_debugfs_init();
--	if (err != 0)
--		goto failed_debugfs_init;
-+	vchiq_debugfs_init();
- 
- 	vchiq_log_info(vchiq_arm_log_level,
- 		"vchiq: initialised - version %d (min %d), device %d.%d",
-@@ -3448,8 +3446,6 @@ static int vchiq_probe(struct platform_d
- 
- 	return 0;
- 
--failed_debugfs_init:
--	device_destroy(vchiq_class, vchiq_devid);
- failed_device_create:
- 	class_destroy(vchiq_class);
- failed_class_create:
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-@@ -160,15 +160,12 @@ static const struct file_operations debu
- };
- 
- /* create an entry under <debugfs>/vchiq/log for each log category */
--static int vchiq_debugfs_create_log_entries(struct dentry *top)
-+static void vchiq_debugfs_create_log_entries(struct dentry *top)
- {
- 	struct dentry *dir;
- 	size_t i;
--	int ret = 0;
- 
- 	dir = debugfs_create_dir("log", vchiq_debugfs_top());
--	if (!dir)
--		return -ENOMEM;
- 	debugfs_info.log_categories = dir;
- 
- 	for (i = 0; i < n_log_entries; i++) {
-@@ -179,14 +176,8 @@ static int vchiq_debugfs_create_log_entr
- 					  debugfs_info.log_categories,
- 					  levp,
- 					  &debugfs_log_fops);
--		if (!dir) {
--			ret = -ENOMEM;
--			break;
--		}
--
- 		vchiq_debugfs_log_entries[i].dir = dir;
- 	}
--	return ret;
- }
- 
- static int debugfs_usecount_show(struct seq_file *f, void *offset)
-@@ -270,43 +261,22 @@ static const struct file_operations debu
- };
- 
- /* add an instance (process) to the debugfs entries */
--int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
-+void vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
- {
- 	char pidstr[16];
--	struct dentry *top, *use_count, *trace;
-+	struct dentry *top;
- 	struct dentry *clients = vchiq_clients_top();
- 
- 	snprintf(pidstr, sizeof(pidstr), "%d",
- 		 vchiq_instance_get_pid(instance));
- 
- 	top = debugfs_create_dir(pidstr, clients);
--	if (!top)
--		goto fail_top;
- 
--	use_count = debugfs_create_file("use_count",
--					0444, top,
--					instance,
--					&debugfs_usecount_fops);
--	if (!use_count)
--		goto fail_use_count;
--
--	trace = debugfs_create_file("trace",
--				    0644, top,
--				    instance,
--				    &debugfs_trace_fops);
--	if (!trace)
--		goto fail_trace;
-+	debugfs_create_file("use_count", 0444, top, instance,
-+			    &debugfs_usecount_fops);
-+	debugfs_create_file("trace", 0644, top, instance, &debugfs_trace_fops);
- 
- 	vchiq_instance_get_debugfs_node(instance)->dentry = top;
--
--	return 0;
--
--fail_trace:
--	debugfs_remove(use_count);
--fail_use_count:
--	debugfs_remove(top);
--fail_top:
--	return -ENOMEM;
- }
- 
- void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance)
-@@ -316,32 +286,13 @@ void vchiq_debugfs_remove_instance(VCHIQ
- 	debugfs_remove_recursive(node->dentry);
- }
- 
--
--int vchiq_debugfs_init(void)
-+void vchiq_debugfs_init(void)
- {
--	BUG_ON(debugfs_info.vchiq_cfg_dir != NULL);
--
- 	debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL);
--	if (debugfs_info.vchiq_cfg_dir == NULL)
--		goto fail;
--
- 	debugfs_info.clients = debugfs_create_dir("clients",
- 				vchiq_debugfs_top());
--	if (!debugfs_info.clients)
--		goto fail;
- 
--	if (vchiq_debugfs_create_log_entries(vchiq_debugfs_top()) != 0)
--		goto fail;
--
--	return 0;
--
--fail:
--	vchiq_debugfs_deinit();
--	vchiq_log_error(vchiq_arm_log_level,
--		"%s: failed to create debugfs directory",
--		__func__);
--
--	return -ENOMEM;
-+	vchiq_debugfs_create_log_entries(vchiq_debugfs_top());
- }
- 
- /* remove all the debugfs entries */
-@@ -363,18 +314,16 @@ static struct dentry *vchiq_debugfs_top(
- 
- #else /* CONFIG_DEBUG_FS */
- 
--int vchiq_debugfs_init(void)
-+void vchiq_debugfs_init(void)
- {
--	return 0;
- }
- 
- void vchiq_debugfs_deinit(void)
- {
- }
- 
--int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
-+void vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance)
- {
--	return 0;
- }
- 
- void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance)
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.h
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.h
-@@ -40,11 +40,11 @@ typedef struct vchiq_debugfs_node_struct
-     struct dentry *dentry;
- } VCHIQ_DEBUGFS_NODE_T;
- 
--int vchiq_debugfs_init(void);
-+void vchiq_debugfs_init(void);
- 
- void vchiq_debugfs_deinit(void);
- 
--int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance);
-+void vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance);
- 
- void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance);
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0382-staging-vc04_services-remove-odd-vchiq_debugfs_top-w.patch b/target/linux/brcm2708/patches-4.14/950-0382-staging-vc04_services-remove-odd-vchiq_debugfs_top-w.patch
deleted file mode 100644
index f9b7c3bad..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0382-staging-vc04_services-remove-odd-vchiq_debugfs_top-w.patch
+++ /dev/null
@@ -1,104 +0,0 @@
-From a283da4533745e3552b889dce7e31ada9d99c5d2 Mon Sep 17 00:00:00 2001
-From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Date: Fri, 1 Jun 2018 13:10:00 +0200
-Subject: [PATCH 382/454] staging: vc04_services: remove odd
- vchiq_debugfs_top() wrapper
-
-commit 2739deaece4bc25fba5df0566423f4a11c3f4e84 upstream
-
-vchiq_debugfs_top() is only a wrapper around a pointer to a dentry, so
-just use the dentry directly instead, making it a static variable
-instead of part of a static structure.
-
-This also removes the pointless BUG_ON() when checking that dentry as no
-one should ever care if debugfs is working or not, and the kernel should
-really not panic over something as trivial as that.
-
-Suggested-by: Eric Anholt <eric@anholt.net>
-Cc: Stefan Wahren <stefan.wahren@i2se.com>
-Cc: Kees Cook <keescook@chromium.org>
-Cc: Dan Carpenter <dan.carpenter@oracle.com>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Keerthi Reddy <keerthigd4990@gmail.com>
-Cc: linux-rpi-kernel@lists.infradead.org
-Cc: linux-arm-kernel@lists.infradead.org
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../interface/vchiq_arm/vchiq_debugfs.c       | 24 +++++++------------
- 1 file changed, 8 insertions(+), 16 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-@@ -55,9 +55,6 @@
- 
- /* Top-level debug info */
- struct vchiq_debugfs_info {
--	/* Global 'vchiq' debugfs entry used by all instances */
--	struct dentry *vchiq_cfg_dir;
--
- 	/* one entry per client process */
- 	struct dentry *clients;
- 
-@@ -67,6 +64,9 @@ struct vchiq_debugfs_info {
- 
- static struct vchiq_debugfs_info debugfs_info;
- 
-+/* Global 'vchiq' debugfs entry used by all instances */
-+struct dentry *vchiq_dbg_dir;
-+
- /* Log category debugfs entries */
- struct vchiq_debugfs_log_entry {
- 	const char *name;
-@@ -84,7 +84,6 @@ static struct vchiq_debugfs_log_entry vc
- static int n_log_entries = ARRAY_SIZE(vchiq_debugfs_log_entries);
- 
- static struct dentry *vchiq_clients_top(void);
--static struct dentry *vchiq_debugfs_top(void);
- 
- static int debugfs_log_show(struct seq_file *f, void *offset)
- {
-@@ -165,7 +164,7 @@ static void vchiq_debugfs_create_log_ent
- 	struct dentry *dir;
- 	size_t i;
- 
--	dir = debugfs_create_dir("log", vchiq_debugfs_top());
-+	dir = debugfs_create_dir("log", vchiq_dbg_dir);
- 	debugfs_info.log_categories = dir;
- 
- 	for (i = 0; i < n_log_entries; i++) {
-@@ -288,17 +287,16 @@ void vchiq_debugfs_remove_instance(VCHIQ
- 
- void vchiq_debugfs_init(void)
- {
--	debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL);
--	debugfs_info.clients = debugfs_create_dir("clients",
--				vchiq_debugfs_top());
-+	vchiq_dbg_dir = debugfs_create_dir("vchiq", NULL);
-+	debugfs_info.clients = debugfs_create_dir("clients", vchiq_dbg_dir);
- 
--	vchiq_debugfs_create_log_entries(vchiq_debugfs_top());
-+	vchiq_debugfs_create_log_entries(vchiq_dbg_dir);
- }
- 
- /* remove all the debugfs entries */
- void vchiq_debugfs_deinit(void)
- {
--	debugfs_remove_recursive(vchiq_debugfs_top());
-+	debugfs_remove_recursive(vchiq_dbg_dir);
- }
- 
- static struct dentry *vchiq_clients_top(void)
-@@ -306,12 +304,6 @@ static struct dentry *vchiq_clients_top(
- 	return debugfs_info.clients;
- }
- 
--static struct dentry *vchiq_debugfs_top(void)
--{
--	BUG_ON(debugfs_info.vchiq_cfg_dir == NULL);
--	return debugfs_info.vchiq_cfg_dir;
--}
--
- #else /* CONFIG_DEBUG_FS */
- 
- void vchiq_debugfs_init(void)
diff --git a/target/linux/brcm2708/patches-4.14/950-0383-staging-vc04_services-move-client-dbg-directory-into.patch b/target/linux/brcm2708/patches-4.14/950-0383-staging-vc04_services-move-client-dbg-directory-into.patch
deleted file mode 100644
index 14abfcad3..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0383-staging-vc04_services-move-client-dbg-directory-into.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From 217f7a22c049f2ccc24d2080cf7369f39fe3b6c5 Mon Sep 17 00:00:00 2001
-From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Date: Fri, 1 Jun 2018 13:10:01 +0200
-Subject: [PATCH 383/454] staging: vc04_services: move client dbg directory
- into static variable
-
-commit 24e8d3fc42f25936ff270e404847a3a462c38468 upstream
-
-This does not need to be part of a wrapper function, or in a structure,
-just properly reference it directly as a single variable.
-
-The whole variable will be going away soon anyway, this is just a step
-toward that direction.
-
-Suggested-by: Eric Anholt <eric@anholt.net>
-Cc: Stefan Wahren <stefan.wahren@i2se.com>
-Cc: Kees Cook <keescook@chromium.org>
-Cc: Dan Carpenter <dan.carpenter@oracle.com>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Keerthi Reddy <keerthigd4990@gmail.com>
-Cc: linux-rpi-kernel@lists.infradead.org
-Cc: linux-arm-kernel@lists.infradead.org
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../interface/vchiq_arm/vchiq_debugfs.c        | 18 ++++--------------
- 1 file changed, 4 insertions(+), 14 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-@@ -55,17 +55,15 @@
- 
- /* Top-level debug info */
- struct vchiq_debugfs_info {
--	/* one entry per client process */
--	struct dentry *clients;
--
- 	/* log categories */
- 	struct dentry *log_categories;
- };
- 
- static struct vchiq_debugfs_info debugfs_info;
- 
--/* Global 'vchiq' debugfs entry used by all instances */
-+/* Global 'vchiq' debugfs and clients entry used by all instances */
- struct dentry *vchiq_dbg_dir;
-+struct dentry *vchiq_dbg_clients;
- 
- /* Log category debugfs entries */
- struct vchiq_debugfs_log_entry {
-@@ -83,8 +81,6 @@ static struct vchiq_debugfs_log_entry vc
- };
- static int n_log_entries = ARRAY_SIZE(vchiq_debugfs_log_entries);
- 
--static struct dentry *vchiq_clients_top(void);
--
- static int debugfs_log_show(struct seq_file *f, void *offset)
- {
- 	int *levp = f->private;
-@@ -264,12 +260,11 @@ void vchiq_debugfs_add_instance(VCHIQ_IN
- {
- 	char pidstr[16];
- 	struct dentry *top;
--	struct dentry *clients = vchiq_clients_top();
- 
- 	snprintf(pidstr, sizeof(pidstr), "%d",
- 		 vchiq_instance_get_pid(instance));
- 
--	top = debugfs_create_dir(pidstr, clients);
-+	top = debugfs_create_dir(pidstr, vchiq_dbg_clients);
- 
- 	debugfs_create_file("use_count", 0444, top, instance,
- 			    &debugfs_usecount_fops);
-@@ -288,7 +283,7 @@ void vchiq_debugfs_remove_instance(VCHIQ
- void vchiq_debugfs_init(void)
- {
- 	vchiq_dbg_dir = debugfs_create_dir("vchiq", NULL);
--	debugfs_info.clients = debugfs_create_dir("clients", vchiq_dbg_dir);
-+	vchiq_dbg_clients = debugfs_create_dir("clients", vchiq_dbg_dir);
- 
- 	vchiq_debugfs_create_log_entries(vchiq_dbg_dir);
- }
-@@ -299,11 +294,6 @@ void vchiq_debugfs_deinit(void)
- 	debugfs_remove_recursive(vchiq_dbg_dir);
- }
- 
--static struct dentry *vchiq_clients_top(void)
--{
--	return debugfs_info.clients;
--}
--
- #else /* CONFIG_DEBUG_FS */
- 
- void vchiq_debugfs_init(void)
diff --git a/target/linux/brcm2708/patches-4.14/950-0384-staging-vc04_services-remove-struct-vchiq_debugfs_in.patch b/target/linux/brcm2708/patches-4.14/950-0384-staging-vc04_services-remove-struct-vchiq_debugfs_in.patch
deleted file mode 100644
index 36f5584dd..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0384-staging-vc04_services-remove-struct-vchiq_debugfs_in.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From d661bf1a882cc7123f84fcf3ccf210b19929a47b Mon Sep 17 00:00:00 2001
-From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Date: Fri, 1 Jun 2018 13:10:02 +0200
-Subject: [PATCH 384/454] staging: vc04_services: remove struct
- vchiq_debugfs_info
-
-commit 127892febb2d5d6612756da2d7d0bab526db3b51 upstream
-
-This structure, and the one static variable that was declared with it,
-were not being used for anything.  The log_categories field was being
-set, but never used again.  So just remove it entirely as it is not
-needed at all.
-
-Suggested-by: Eric Anholt <eric@anholt.net>
-Cc: Stefan Wahren <stefan.wahren@i2se.com>
-Cc: Kees Cook <keescook@chromium.org>
-Cc: Dan Carpenter <dan.carpenter@oracle.com>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Keerthi Reddy <keerthigd4990@gmail.com>
-Cc: linux-rpi-kernel@lists.infradead.org
-Cc: linux-arm-kernel@lists.infradead.org
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../interface/vchiq_arm/vchiq_debugfs.c           | 15 +--------------
- 1 file changed, 1 insertion(+), 14 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-@@ -52,15 +52,6 @@
- #define VCHIQ_LOG_INFO_STR    "info"
- #define VCHIQ_LOG_TRACE_STR   "trace"
- 
--
--/* Top-level debug info */
--struct vchiq_debugfs_info {
--	/* log categories */
--	struct dentry *log_categories;
--};
--
--static struct vchiq_debugfs_info debugfs_info;
--
- /* Global 'vchiq' debugfs and clients entry used by all instances */
- struct dentry *vchiq_dbg_dir;
- struct dentry *vchiq_dbg_clients;
-@@ -161,16 +152,12 @@ static void vchiq_debugfs_create_log_ent
- 	size_t i;
- 
- 	dir = debugfs_create_dir("log", vchiq_dbg_dir);
--	debugfs_info.log_categories = dir;
- 
- 	for (i = 0; i < n_log_entries; i++) {
- 		void *levp = (void *)vchiq_debugfs_log_entries[i].plevel;
- 
- 		dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name,
--					  0644,
--					  debugfs_info.log_categories,
--					  levp,
--					  &debugfs_log_fops);
-+					  0644, dir, levp, &debugfs_log_fops);
- 		vchiq_debugfs_log_entries[i].dir = dir;
- 	}
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0385-staging-vc04_services-vchiq_debugfs_log_entry-can-be.patch b/target/linux/brcm2708/patches-4.14/950-0385-staging-vc04_services-vchiq_debugfs_log_entry-can-be.patch
deleted file mode 100644
index 89249ed65..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0385-staging-vc04_services-vchiq_debugfs_log_entry-can-be.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 866caf8f5ea6d9b5b47d8e4bfad9359a278dc5e7 Mon Sep 17 00:00:00 2001
-From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Date: Fri, 1 Jun 2018 13:10:03 +0200
-Subject: [PATCH 385/454] staging: vc04_services: vchiq_debugfs_log_entry can
- be a void *
-
-commit 54f156968a1ca1655a53b4975e91b767552d8008 upstream
-
-There's no need to set this to be int * when it is only used as a void *.
-This lets us remove the unneeded cast, and unneeded temporary variable
-the one place it is referenced in the code.
-
-Suggested-by: Eric Anholt <eric@anholt.net>
-Cc: Stefan Wahren <stefan.wahren@i2se.com>
-Cc: Kees Cook <keescook@chromium.org>
-Cc: Dan Carpenter <dan.carpenter@oracle.com>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Keerthi Reddy <keerthigd4990@gmail.com>
-Cc: linux-rpi-kernel@lists.infradead.org
-Cc: linux-arm-kernel@lists.infradead.org
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../vc04_services/interface/vchiq_arm/vchiq_debugfs.c     | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-@@ -59,7 +59,7 @@ struct dentry *vchiq_dbg_clients;
- /* Log category debugfs entries */
- struct vchiq_debugfs_log_entry {
- 	const char *name;
--	int *plevel;
-+	void *plevel;
- 	struct dentry *dir;
- };
- 
-@@ -154,10 +154,10 @@ static void vchiq_debugfs_create_log_ent
- 	dir = debugfs_create_dir("log", vchiq_dbg_dir);
- 
- 	for (i = 0; i < n_log_entries; i++) {
--		void *levp = (void *)vchiq_debugfs_log_entries[i].plevel;
--
- 		dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name,
--					  0644, dir, levp, &debugfs_log_fops);
-+					  0644, dir,
-+					  vchiq_debugfs_log_entries[i].plevel,
-+					  &debugfs_log_fops);
- 		vchiq_debugfs_log_entries[i].dir = dir;
- 	}
- }
diff --git a/target/linux/brcm2708/patches-4.14/950-0386-staging-vc04_services-no-need-to-save-the-log-debufs.patch b/target/linux/brcm2708/patches-4.14/950-0386-staging-vc04_services-no-need-to-save-the-log-debufs.patch
deleted file mode 100644
index 11e2e000d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0386-staging-vc04_services-no-need-to-save-the-log-debufs.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 4940fd338dc53324603c0bd2642b0a3864baa5fe Mon Sep 17 00:00:00 2001
-From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Date: Fri, 1 Jun 2018 13:10:04 +0200
-Subject: [PATCH 386/454] staging: vc04_services: no need to save the log
- debufs dentries
-
-commit 3b93c0f4b6accb8105152900d7e414593a8b0c79 upstream
-
-The log entry dentries are only set, never referenced, so no need to
-keep them around.  Remove the pointer from struct
-vchiq_debugfs_log_entry as it is not needed anymore and get rid of the
-separate vchiq_debugfs_create_log_entries() function as it is only used
-in one place.
-
-Suggested-by: Eric Anholt <eric@anholt.net>
-Cc: Stefan Wahren <stefan.wahren@i2se.com>
-Cc: Kees Cook <keescook@chromium.org>
-Cc: Dan Carpenter <dan.carpenter@oracle.com>
-Cc: Arnd Bergmann <arnd@arndb.de>
-Cc: Keerthi Reddy <keerthigd4990@gmail.com>
-Cc: linux-rpi-kernel@lists.infradead.org
-Cc: linux-arm-kernel@lists.infradead.org
-Reviewed-by: Eric Anholt <eric@anholt.net>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../interface/vchiq_arm/vchiq_debugfs.c       | 29 +++++++------------
- 1 file changed, 10 insertions(+), 19 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_debugfs.c
-@@ -60,7 +60,6 @@ struct dentry *vchiq_dbg_clients;
- struct vchiq_debugfs_log_entry {
- 	const char *name;
- 	void *plevel;
--	struct dentry *dir;
- };
- 
- static struct vchiq_debugfs_log_entry vchiq_debugfs_log_entries[] = {
-@@ -145,23 +144,6 @@ static const struct file_operations debu
- 	.release	= single_release,
- };
- 
--/* create an entry under <debugfs>/vchiq/log for each log category */
--static void vchiq_debugfs_create_log_entries(struct dentry *top)
--{
--	struct dentry *dir;
--	size_t i;
--
--	dir = debugfs_create_dir("log", vchiq_dbg_dir);
--
--	for (i = 0; i < n_log_entries; i++) {
--		dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name,
--					  0644, dir,
--					  vchiq_debugfs_log_entries[i].plevel,
--					  &debugfs_log_fops);
--		vchiq_debugfs_log_entries[i].dir = dir;
--	}
--}
--
- static int debugfs_usecount_show(struct seq_file *f, void *offset)
- {
- 	VCHIQ_INSTANCE_T instance = f->private;
-@@ -269,10 +251,19 @@ void vchiq_debugfs_remove_instance(VCHIQ
- 
- void vchiq_debugfs_init(void)
- {
-+	struct dentry *dir;
-+	int i;
-+
- 	vchiq_dbg_dir = debugfs_create_dir("vchiq", NULL);
- 	vchiq_dbg_clients = debugfs_create_dir("clients", vchiq_dbg_dir);
- 
--	vchiq_debugfs_create_log_entries(vchiq_dbg_dir);
-+	/* create an entry under <debugfs>/vchiq/log for each log category */
-+	dir = debugfs_create_dir("log", vchiq_dbg_dir);
-+
-+	for (i = 0; i < n_log_entries; i++)
-+		debugfs_create_file(vchiq_debugfs_log_entries[i].name, 0644,
-+				    dir, vchiq_debugfs_log_entries[i].plevel,
-+				    &debugfs_log_fops);
- }
- 
- /* remove all the debugfs entries */
diff --git a/target/linux/brcm2708/patches-4.14/950-0387-staging-vc04_services-Join-multiline-dereferences.patch b/target/linux/brcm2708/patches-4.14/950-0387-staging-vc04_services-Join-multiline-dereferences.patch
deleted file mode 100644
index 4dc8bae6b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0387-staging-vc04_services-Join-multiline-dereferences.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 1ff6cbebfb5ce6a9509eb29d5f98d6b8710c021d Mon Sep 17 00:00:00 2001
-From: Genki Sky <sky@genki.is>
-Date: Tue, 5 Dec 2017 19:09:54 -0500
-Subject: [PATCH 387/454] staging: vc04_services: Join multiline dereferences
-
-commit 7260ea5fc327344974716e5109180f96f0483a85 upstream
-
-This was found using checkpatch.pl's MULTILINE_DEREFERENCE warning.
-Putting the dereference onto one line makes them easier to read,
-especially when part of a larger expression (in this case, function
-arguments and ternary operator), and when the dereferences are short
-(as they are here).
-
-Signed-off-by: Genki Sky <sky@genki.is>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../bcm2835-camera/bcm2835-camera.c              | 16 ++++++----------
- 1 file changed, 6 insertions(+), 10 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -356,11 +356,9 @@ static void buffer_cb(struct vchiq_mmal_
- 				pr_debug("Grab another frame");
- 				vchiq_mmal_port_parameter_set(
- 					instance,
--					dev->capture.
--					camera_port,
-+					dev->capture.camera_port,
- 					MMAL_PARAMETER_CAPTURE,
--					&dev->capture.
--					frame_count,
-+					&dev->capture.frame_count,
- 					sizeof(dev->capture.frame_count));
- 			}
- 		} else {
-@@ -419,11 +417,9 @@ static void buffer_cb(struct vchiq_mmal_
- 					 "Grab another frame as buffer has EOS");
- 				vchiq_mmal_port_parameter_set(
- 					instance,
--					dev->capture.
--					camera_port,
-+					dev->capture.camera_port,
- 					MMAL_PARAMETER_CAPTURE,
--					&dev->capture.
--					frame_count,
-+					&dev->capture.frame_count,
- 					sizeof(dev->capture.frame_count));
- 			}
- 		} else {
-@@ -1268,8 +1264,8 @@ static int mmal_setup_components(struct
- 					port->current_buffer.size =
- 					    (f->fmt.pix.sizeimage <
- 					     (100 << 10))
--					    ? (100 << 10) : f->fmt.pix.
--					    sizeimage;
-+					    ? (100 << 10)
-+					    : f->fmt.pix.sizeimage;
- 				}
- 				v4l2_dbg(1, bcm2835_v4l2_debug,
- 					 &dev->v4l2_dev,
diff --git a/target/linux/brcm2708/patches-4.14/950-0388-Revert-bcm2835-camera-Fix-timestamp-calculation-prob.patch b/target/linux/brcm2708/patches-4.14/950-0388-Revert-bcm2835-camera-Fix-timestamp-calculation-prob.patch
deleted file mode 100644
index 2bb3a4714..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0388-Revert-bcm2835-camera-Fix-timestamp-calculation-prob.patch
+++ /dev/null
@@ -1,93 +0,0 @@
-From a740e59bf8099d1f5b5b29be3e9993fbd51e729a Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Fri, 6 Jul 2018 17:43:03 +0100
-Subject: [PATCH 388/454] Revert "bcm2835-camera: Fix timestamp calculation
- problem (#2214)"
-
-This reverts commit 90ac037dbeecbb514b677e43b53bc5b1a452ea22.
-This has been fixed in an alternate format upstream, so adopt that.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 41 ++++++++++++++-----
- .../bcm2835-camera/bcm2835-camera.h           |  2 +-
- 2 files changed, 32 insertions(+), 11 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -374,17 +374,37 @@ static void buffer_cb(struct vchiq_mmal_
- 				 buf->vb.vb2_buf.timestamp);
- 
- 			} else if(pts != 0) {
-+				struct timeval timestamp;
- 				s64 runtime_us = pts -
- 				    dev->capture.vc_start_timestamp;
--				buf->vb.vb2_buf.timestamp = (runtime_us * NSEC_PER_USEC) +
--				    dev->capture.kernel_start_timestamp;
-+				u32 div = 0;
-+				u32 rem = 0;
-+
-+				div =
-+				    div_u64_rem(runtime_us, USEC_PER_SEC, &rem);
-+				timestamp.tv_sec =
-+				    dev->capture.kernel_start_ts.tv_sec + div;
-+				timestamp.tv_usec =
-+				    dev->capture.kernel_start_ts.tv_usec + rem;
-+
-+				if (timestamp.tv_usec >=
-+				    USEC_PER_SEC) {
-+					timestamp.tv_sec++;
-+					timestamp.tv_usec -=
-+					    USEC_PER_SEC;
-+				}
- 				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--					 "Buffer time set as converted timestamp - %llu "
--					 "= (pts [%lld usec] - vc start time [%llu usec]) "
--					 "+ kernel start time [%llu nsec]\n",
--					 buf->vb.vb2_buf.timestamp,
--					 pts, dev->capture.vc_start_timestamp,
--					 dev->capture.kernel_start_timestamp);
-+					 "Convert start time %d.%06d and %llu "
-+					 "with offset %llu to %d.%06d\n",
-+					 (int)dev->capture.kernel_start_ts.
-+					 tv_sec,
-+					 (int)dev->capture.kernel_start_ts.
-+					 tv_usec,
-+					 dev->capture.vc_start_timestamp, pts,
-+					 (int)timestamp.tv_sec,
-+					 (int)timestamp.tv_usec);
-+				buf->vb.vb2_buf.timestamp = timestamp.tv_sec * 1000000000ULL +
-+					timestamp.tv_usec * 1000ULL;
- 			} else {
- 				if (dev->capture.last_timestamp) {
- 					buf->vb.vb2_buf.timestamp = dev->capture.last_timestamp;
-@@ -394,7 +414,8 @@ static void buffer_cb(struct vchiq_mmal_
- 				}
- 				else {
- 					buf->vb.vb2_buf.timestamp =
--					dev->capture.kernel_start_timestamp;
-+					dev->capture.kernel_start_ts.tv_sec  * 1000000000ULL +
-+					dev->capture.kernel_start_ts.tv_usec * 1000ULL;
- 					v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
- 					 "Buffer time set as start timestamp - %lld",
- 					 buf->vb.vb2_buf.timestamp);
-@@ -575,7 +596,7 @@ static int start_streaming(struct vb2_qu
- 
- 	dev->capture.last_timestamp = 0;
- 
--	dev->capture.kernel_start_timestamp = ktime_get_ns();
-+	v4l2_get_timestamp(&dev->capture.kernel_start_ts);
- 
- 	/* enable the camera port */
- 	dev->capture.port->cb_ctx = dev;
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-@@ -92,7 +92,7 @@ struct bm2835_mmal_dev {
- 		/* VC start timestamp for streaming */
- 		s64         vc_start_timestamp;
- 		/* Kernel start timestamp for streaming */
--		u64         kernel_start_timestamp;
-+		struct timeval kernel_start_ts;
- 		/* Timestamp of last frame */
- 		u64 		last_timestamp;
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0389-staging-bcm2835-camera-use-ktime_t-for-timestamps.patch b/target/linux/brcm2708/patches-4.14/950-0389-staging-bcm2835-camera-use-ktime_t-for-timestamps.patch
deleted file mode 100644
index 5801afea5..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0389-staging-bcm2835-camera-use-ktime_t-for-timestamps.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From fab723d6ce6dd2052b4febd65ae62425288d79d3 Mon Sep 17 00:00:00 2001
-From: Arnd Bergmann <arnd@arndb.de>
-Date: Mon, 27 Nov 2017 14:19:56 +0100
-Subject: [PATCH 389/454] staging: bcm2835-camera use ktime_t for timestamps
-
-commit 6cf83f2a9e81c500819938fad3555081471212c6 upstream with
-minor mods
-
-struct timeval is deprecated for in-kernel use, and converting
-this function to use ktime_t makes it simpler as well.
-
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 37 +++++--------------
- .../bcm2835-camera/bcm2835-camera.h           |  2 +-
- 2 files changed, 10 insertions(+), 29 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -374,37 +374,18 @@ static void buffer_cb(struct vchiq_mmal_
- 				 buf->vb.vb2_buf.timestamp);
- 
- 			} else if(pts != 0) {
--				struct timeval timestamp;
-+				ktime_t timestamp;
- 				s64 runtime_us = pts -
- 				    dev->capture.vc_start_timestamp;
--				u32 div = 0;
--				u32 rem = 0;
--
--				div =
--				    div_u64_rem(runtime_us, USEC_PER_SEC, &rem);
--				timestamp.tv_sec =
--				    dev->capture.kernel_start_ts.tv_sec + div;
--				timestamp.tv_usec =
--				    dev->capture.kernel_start_ts.tv_usec + rem;
--
--				if (timestamp.tv_usec >=
--				    USEC_PER_SEC) {
--					timestamp.tv_sec++;
--					timestamp.tv_usec -=
--					    USEC_PER_SEC;
--				}
-+				timestamp = ktime_add_us(dev->capture.kernel_start_ts,
-+							 runtime_us);
- 				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--					 "Convert start time %d.%06d and %llu "
--					 "with offset %llu to %d.%06d\n",
--					 (int)dev->capture.kernel_start_ts.
--					 tv_sec,
--					 (int)dev->capture.kernel_start_ts.
--					 tv_usec,
-+					 "Convert start time %llu and %llu "
-+					 "with offset %llu to %llu\n",
-+					 ktime_to_ns(dev->capture.kernel_start_ts),
- 					 dev->capture.vc_start_timestamp, pts,
--					 (int)timestamp.tv_sec,
--					 (int)timestamp.tv_usec);
--				buf->vb.vb2_buf.timestamp = timestamp.tv_sec * 1000000000ULL +
--					timestamp.tv_usec * 1000ULL;
-+					 ktime_to_ns(timestamp));
-+				buf->vb.vb2_buf.timestamp = ktime_to_ns(timestamp);
- 			} else {
- 				if (dev->capture.last_timestamp) {
- 					buf->vb.vb2_buf.timestamp = dev->capture.last_timestamp;
-@@ -596,7 +577,7 @@ static int start_streaming(struct vb2_qu
- 
- 	dev->capture.last_timestamp = 0;
- 
--	v4l2_get_timestamp(&dev->capture.kernel_start_ts);
-+	dev->capture.kernel_start_ts = ktime_get();
- 
- 	/* enable the camera port */
- 	dev->capture.port->cb_ctx = dev;
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-@@ -92,7 +92,7 @@ struct bm2835_mmal_dev {
- 		/* VC start timestamp for streaming */
- 		s64         vc_start_timestamp;
- 		/* Kernel start timestamp for streaming */
--		struct timeval kernel_start_ts;
-+		ktime_t kernel_start_ts;
- 		/* Timestamp of last frame */
- 		u64 		last_timestamp;
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0390-staging-vc04_services-Unsplit-user-visible-strings.patch b/target/linux/brcm2708/patches-4.14/950-0390-staging-vc04_services-Unsplit-user-visible-strings.patch
deleted file mode 100644
index 667a13f2c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0390-staging-vc04_services-Unsplit-user-visible-strings.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 59f1fbe55d6e5b878fd422cd969fbee7d5d9b78c Mon Sep 17 00:00:00 2001
-From: Genki Sky <sky@genki.is>
-Date: Tue, 5 Dec 2017 19:09:54 -0500
-Subject: [PATCH 390/454] staging: vc04_services: Unsplit user-visible strings
-
-Commit 5ced5a899b405e09cc681b8a1a449815b66744c7 upstream.
-
-This was found using checkpatch.pl's SPLIT_STRING warning. While joining
-these strings makes for long lines, the kernel codebase consistently
-does it this way to make user-visible strings easier to grep for.
-
-Signed-off-by: Genki Sky <sky@genki.is>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../staging/vc04_services/bcm2835-camera/bcm2835-camera.c  | 7 +++----
- drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c  | 3 +--
- 2 files changed, 4 insertions(+), 6 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -380,8 +380,7 @@ static void buffer_cb(struct vchiq_mmal_
- 				timestamp = ktime_add_us(dev->capture.kernel_start_ts,
- 							 runtime_us);
- 				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--					 "Convert start time %llu and %llu "
--					 "with offset %llu to %llu\n",
-+					 "Convert start time %llu and %llu with offset %llu to %llu\n",
- 					 ktime_to_ns(dev->capture.kernel_start_ts),
- 					 dev->capture.vc_start_timestamp, pts,
- 					 ktime_to_ns(timestamp));
-@@ -585,8 +584,8 @@ static int start_streaming(struct vb2_qu
- 	    vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb);
- 	if (ret) {
- 		v4l2_err(&dev->v4l2_dev,
--			"Failed to enable capture port - error %d. "
--			"Disabling camera port again\n", ret);
-+			"Failed to enable capture port - error %d. Disabling camera port again\n",
-+			ret);
- 
- 		vchiq_mmal_port_disable(dev->instance,
- 					dev->capture.camera_port);
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -1229,8 +1229,7 @@ static int port_action_handle(struct vch
- 
- 	ret = -rmsg->u.port_action_reply.status;
- 
--	pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)" \
--		 " connect component:0x%x connect port:%d\n",
-+	pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d) connect component:0x%x connect port:%d\n",
- 		 __func__,
- 		 ret, port->component->handle, port->handle,
- 		 port_action_type_names[action_type],
diff --git a/target/linux/brcm2708/patches-4.14/950-0391-staging-vc04_services-Use-__func__.patch b/target/linux/brcm2708/patches-4.14/950-0391-staging-vc04_services-Use-__func__.patch
deleted file mode 100644
index 15f524a09..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0391-staging-vc04_services-Use-__func__.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 192196a624b8bb2eb9dea805066ff9698d3c67d3 Mon Sep 17 00:00:00 2001
-From: Genki Sky <sky@genki.is>
-Date: Tue, 5 Dec 2017 19:09:55 -0500
-Subject: [PATCH 391/454] staging: vc04_services: Use __func__
-
-Commit b891f25d80d16e314dc191f019c4e346e41bfb36 upstream.
-
-This was found using checkpatch.pl's EMBEDDED_FUNCTION_NAME warning.
-It is easier to be consistent and always use __func__ instead of having
-to remember to update any hardcoded references to the original name.
-
-Signed-off-by: Genki Sky <sky@genki.is>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -503,8 +503,8 @@ static void buffer_to_host_cb(struct vch
- 	struct mmal_msg_context *msg_context;
- 	u32 handle;
- 
--	pr_debug("buffer_to_host_cb: instance:%p msg:%p msg_len:%d\n",
--		 instance, msg, msg_len);
-+	pr_debug("%s: instance:%p msg:%p msg_len:%d\n",
-+		 __func__, instance, msg, msg_len);
- 
- 	if (msg->u.buffer_from_host.drvbuf.magic == MMAL_MAGIC) {
- 		handle = msg->u.buffer_from_host.drvbuf.client_context;
diff --git a/target/linux/brcm2708/patches-4.14/950-0392-staging-bcm2835-camera-Do-not-bulk-receive-from-serv.patch b/target/linux/brcm2708/patches-4.14/950-0392-staging-bcm2835-camera-Do-not-bulk-receive-from-serv.patch
deleted file mode 100644
index 12cce81ea..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0392-staging-bcm2835-camera-Do-not-bulk-receive-from-serv.patch
+++ /dev/null
@@ -1,197 +0,0 @@
-From 2324b6fff518bebf6ec6363afe932c227f9d0b09 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 14 Feb 2018 17:04:26 +0000
-Subject: [PATCH 392/454] staging: bcm2835-camera: Do not bulk receive from
- service thread
-
-vchi_bulk_queue_receive will queue up to a default of 4
-bulk receives on a connection before blocking.
-If called from the VCHI service_callback thread, then
-that thread is unable to service the VCHI_CALLBACK_BULK_RECEIVED
-events that would enable the queue call to succeed.
-
-Add a workqueue to schedule the call vchi_bulk_queue_receive
-in an alternate context to avoid the lock up.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../vc04_services/bcm2835-camera/mmal-vchiq.c | 101 ++++++++++--------
- 1 file changed, 59 insertions(+), 42 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -118,8 +118,10 @@ struct mmal_msg_context {
- 
- 	union {
- 		struct {
--			/* work struct for defered callback - must come first */
-+			/* work struct for buffer_cb callback */
- 			struct work_struct work;
-+			/* work struct for deferred callback */
-+			struct work_struct buffer_to_host_work;
- 			/* mmal instance */
- 			struct vchiq_mmal_instance *instance;
- 			/* mmal port */
-@@ -174,6 +176,9 @@ struct vchiq_mmal_instance {
- 	/* component to use next */
- 	int component_idx;
- 	struct vchiq_mmal_component component[VCHIQ_MMAL_MAX_COMPONENTS];
-+
-+	/* ordered workqueue to process all bulk operations */
-+	struct workqueue_struct *bulk_wq;
- };
- 
- static int __must_check
-@@ -320,7 +325,44 @@ static void buffer_work_cb(struct work_s
- 					    msg_context->u.bulk.mmal_flags,
- 					    msg_context->u.bulk.dts,
- 					    msg_context->u.bulk.pts);
-+}
-+
-+/* workqueue scheduled callback to handle receiving buffers
-+ *
-+ * VCHI will allow up to 4 bulk receives to be scheduled before blocking.
-+ * If we block in the service_callback context then we can't process the
-+ * VCHI_CALLBACK_BULK_RECEIVED message that would otherwise allow the blocked
-+ * vchi_bulk_queue_receive() call to complete.
-+ */
-+static void buffer_to_host_work_cb(struct work_struct *work)
-+{
-+	struct mmal_msg_context *msg_context =
-+		container_of(work, struct mmal_msg_context,
-+			     u.bulk.buffer_to_host_work);
-+	struct vchiq_mmal_instance *instance = msg_context->instance;
-+	unsigned long len = msg_context->u.bulk.buffer_used;
-+	int ret;
- 
-+	if (!len)
-+		/* Dummy receive to ensure the buffers remain in order */
-+		len = 8;
-+	/* queue the bulk submission */
-+	vchi_service_use(instance->handle);
-+	ret = vchi_bulk_queue_receive(instance->handle,
-+				      msg_context->u.bulk.buffer->buffer,
-+				      /* Actual receive needs to be a multiple
-+				       * of 4 bytes
-+				       */
-+				      (len + 3) & ~3,
-+				      VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
-+				      VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
-+				      msg_context);
-+
-+	vchi_service_release(instance->handle);
-+
-+	if (ret != 0)
-+		pr_err("%s: ctx: %p, vchi_bulk_queue_receive failed %d\n",
-+		       __func__, msg_context, ret);
- }
- 
- /* enqueue a bulk receive for a given message context */
-@@ -329,7 +371,6 @@ static int bulk_receive(struct vchiq_mma
- 			struct mmal_msg_context *msg_context)
- {
- 	unsigned long rd_len;
--	int ret;
- 
- 	rd_len = msg->u.buffer_from_host.buffer_header.length;
- 
-@@ -365,45 +406,10 @@ static int bulk_receive(struct vchiq_mma
- 	msg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts;
- 	msg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts;
- 
--	/* queue the bulk submission */
--	vchi_service_use(instance->handle);
--	ret = vchi_bulk_queue_receive(instance->handle,
--				      msg_context->u.bulk.buffer->buffer,
--				      /* Actual receive needs to be a multiple
--				       * of 4 bytes
--				       */
--				      (rd_len + 3) & ~3,
--				      VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
--				      VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
--				      msg_context);
--
--	vchi_service_release(instance->handle);
--
--	return ret;
--}
--
--/* enque a dummy bulk receive for a given message context */
--static int dummy_bulk_receive(struct vchiq_mmal_instance *instance,
--			      struct mmal_msg_context *msg_context)
--{
--	int ret;
--
--	/* zero length indicates this was a dummy transfer */
--	msg_context->u.bulk.buffer_used = 0;
--
--	/* queue the bulk submission */
--	vchi_service_use(instance->handle);
--
--	ret = vchi_bulk_queue_receive(instance->handle,
--				      instance->bulk_scratch,
--				      8,
--				      VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE |
--				      VCHI_FLAGS_BLOCK_UNTIL_QUEUED,
--				      msg_context);
-+	queue_work(msg_context->instance->bulk_wq,
-+		   &msg_context->u.bulk.buffer_to_host_work);
- 
--	vchi_service_release(instance->handle);
--
--	return ret;
-+	return 0;
- }
- 
- /* data in message, memcpy from packet into output buffer */
-@@ -451,6 +457,8 @@ buffer_from_host(struct vchiq_mmal_insta
- 
- 	/* initialise work structure ready to schedule callback */
- 	INIT_WORK(&msg_context->u.bulk.work, buffer_work_cb);
-+	INIT_WORK(&msg_context->u.bulk.buffer_to_host_work,
-+		  buffer_to_host_work_cb);
- 
- 	/* prep the buffer from host message */
- 	memset(&m, 0xbc, sizeof(m));	/* just to make debug clearer */
-@@ -531,7 +539,7 @@ static void buffer_to_host_cb(struct vch
- 		if (msg->u.buffer_from_host.buffer_header.flags &
- 		    MMAL_BUFFER_HEADER_FLAG_EOS) {
- 			msg_context->u.bulk.status =
--			    dummy_bulk_receive(instance, msg_context);
-+			    bulk_receive(instance, msg, msg_context);
- 			if (msg_context->u.bulk.status == 0)
- 				return;	/* successful bulk submission, bulk
- 					 * completion will trigger callback
-@@ -1862,6 +1870,9 @@ int vchiq_mmal_finalise(struct vchiq_mma
- 
- 	mutex_unlock(&instance->vchiq_mutex);
- 
-+	flush_workqueue(instance->bulk_wq);
-+	destroy_workqueue(instance->bulk_wq);
-+
- 	vfree(instance->bulk_scratch);
- 
- 	mmal_context_map_destroy(&instance->context_map);
-@@ -1935,6 +1946,11 @@ int vchiq_mmal_init(struct vchiq_mmal_in
- 
- 	params.callback_param = instance;
- 
-+	instance->bulk_wq = alloc_ordered_workqueue("mmal-vchiq",
-+						    WQ_MEM_RECLAIM);
-+	if (!instance->bulk_wq)
-+		goto err_free;
-+
- 	status = vchi_service_open(vchi_instance, &params, &instance->handle);
- 	if (status) {
- 		pr_err("Failed to open VCHI service connection (status=%d)\n",
-@@ -1949,8 +1965,9 @@ int vchiq_mmal_init(struct vchiq_mmal_in
- 	return 0;
- 
- err_close_services:
--
- 	vchi_service_close(instance->handle);
-+	destroy_workqueue(instance->bulk_wq);
-+err_free:
- 	vfree(instance->bulk_scratch);
- 	kfree(instance);
- 	return -ENODEV;
diff --git a/target/linux/brcm2708/patches-4.14/950-0393-staging-bcm2835-camera-Return-early-on-errors.patch b/target/linux/brcm2708/patches-4.14/950-0393-staging-bcm2835-camera-Return-early-on-errors.patch
deleted file mode 100644
index 6ea463899..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0393-staging-bcm2835-camera-Return-early-on-errors.patch
+++ /dev/null
@@ -1,192 +0,0 @@
-From d4154a99430bf73bc501bafc26de80cb1498626c Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Fri, 10 Mar 2017 17:27:56 +0000
-Subject: [PATCH 393/454] staging: bcm2835-camera: Return early on errors
-
-Fix several instances where it is easier to return
-early on error conditions than handle it as an else
-clause.
-As requested by Mauro.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 132 +++++++++---------
- 1 file changed, 68 insertions(+), 64 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -342,7 +342,9 @@ static void buffer_cb(struct vchiq_mmal_
- 			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
- 		}
- 		return;
--	} else if (length == 0) {
-+	}
-+
-+	if (length == 0) {
- 		/* stream ended */
- 		if (buf) {
- 			/* this should only ever happen if the port is
-@@ -365,70 +367,72 @@ static void buffer_cb(struct vchiq_mmal_
- 			/* signal frame completion */
- 			complete(&dev->capture.frame_cmplt);
- 		}
--	} else {
--		if (dev->capture.frame_count) {
--			if (dev->capture.vc_start_timestamp == -1) {
--				buf->vb.vb2_buf.timestamp = ktime_get_ns();
--				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--				 "Buffer time set as current time - %lld",
--				 buf->vb.vb2_buf.timestamp);
--
--			} else if(pts != 0) {
--				ktime_t timestamp;
--				s64 runtime_us = pts -
--				    dev->capture.vc_start_timestamp;
--				timestamp = ktime_add_us(dev->capture.kernel_start_ts,
--							 runtime_us);
--				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--					 "Convert start time %llu and %llu with offset %llu to %llu\n",
--					 ktime_to_ns(dev->capture.kernel_start_ts),
--					 dev->capture.vc_start_timestamp, pts,
--					 ktime_to_ns(timestamp));
--				buf->vb.vb2_buf.timestamp = ktime_to_ns(timestamp);
--			} else {
--				if (dev->capture.last_timestamp) {
--					buf->vb.vb2_buf.timestamp = dev->capture.last_timestamp;
--					v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--					 "Buffer time set as last timestamp - %lld",
--					 buf->vb.vb2_buf.timestamp);
--				}
--				else {
--					buf->vb.vb2_buf.timestamp =
--					dev->capture.kernel_start_ts.tv_sec  * 1000000000ULL +
--					dev->capture.kernel_start_ts.tv_usec * 1000ULL;
--					v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--					 "Buffer time set as start timestamp - %lld",
--					 buf->vb.vb2_buf.timestamp);
--				}
--			}
--			dev->capture.last_timestamp = buf->vb.vb2_buf.timestamp;
-+		return;
-+	}
- 
--			vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length);
--			if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_KEYFRAME)
--				buf->vb.flags |= V4L2_BUF_FLAG_KEYFRAME;
-+	if (!dev->capture.frame_count) {
-+		/* signal frame completion */
-+		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
-+		complete(&dev->capture.frame_cmplt);
-+		return;
-+	}
- 
-+	if (dev->capture.vc_start_timestamp == -1) {
-+		/*
-+		 * VPU doesn't support MMAL_PARAMETER_SYSTEM_TIME, rely on
-+		 * kernel time, and have no latency compensation.
-+		 */
-+		buf->vb.vb2_buf.timestamp = ktime_get_ns();
-+		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+			 "Buffer time set as current time - %lld",
-+			 buf->vb.vb2_buf.timestamp);
-+	} else if (pts != 0) {
-+		ktime_t timestamp;
-+		s64 runtime_us = pts -
-+		    dev->capture.vc_start_timestamp;
-+		timestamp = ktime_add_us(dev->capture.kernel_start_ts,
-+					 runtime_us);
-+		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+			 "Convert start time %llu and %llu with offset %llu to %llu\n",
-+			 ktime_to_ns(dev->capture.kernel_start_ts),
-+			 dev->capture.vc_start_timestamp, pts,
-+			 ktime_to_ns(timestamp));
-+		buf->vb.vb2_buf.timestamp = ktime_to_ns(timestamp);
-+	} else {
-+		if (dev->capture.last_timestamp) {
-+			buf->vb.vb2_buf.timestamp = dev->capture.last_timestamp;
- 			v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--				"Buffer has ts %llu",
--				dev->capture.last_timestamp);
--			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
--
--			if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS &&
--			    is_capturing(dev)) {
--				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--					 "Grab another frame as buffer has EOS");
--				vchiq_mmal_port_parameter_set(
--					instance,
--					dev->capture.camera_port,
--					MMAL_PARAMETER_CAPTURE,
--					&dev->capture.frame_count,
--					sizeof(dev->capture.frame_count));
--			}
-+				 "Buffer time set as last timestamp - %lld",
-+				 buf->vb.vb2_buf.timestamp);
- 		} else {
--			/* signal frame completion */
--			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
--			complete(&dev->capture.frame_cmplt);
-+			buf->vb.vb2_buf.timestamp =
-+				ktime_to_ns(dev->capture.kernel_start_ts);
-+			v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+				 "Buffer time set as start timestamp - %lld",
-+				 buf->vb.vb2_buf.timestamp);
- 		}
- 	}
-+	dev->capture.last_timestamp = buf->vb.vb2_buf.timestamp;
-+
-+	vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length);
-+	if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_KEYFRAME)
-+		buf->vb.flags |= V4L2_BUF_FLAG_KEYFRAME;
-+
-+	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+		 "Buffer has ts %llu",
-+		 dev->capture.last_timestamp);
-+	vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
-+
-+	if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS &&
-+	    is_capturing(dev)) {
-+		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+			 "Grab another frame as buffer has EOS");
-+		vchiq_mmal_port_parameter_set(instance,
-+					      dev->capture.camera_port,
-+					      MMAL_PARAMETER_CAPTURE,
-+					      &dev->capture.frame_count,
-+					      sizeof(dev->capture.frame_count));
-+	}
- }
- 
- static int enable_camera(struct bm2835_mmal_dev *dev)
-@@ -823,27 +827,27 @@ static int vidioc_overlay(struct file *f
- 
- 	ret = vchiq_mmal_port_set_format(dev->instance, src);
- 	if (ret < 0)
--		goto error;
-+		return ret;
- 
- 	ret = set_overlay_params(dev, dst);
- 	if (ret < 0)
--		goto error;
-+		return ret;
- 
- 	if (enable_camera(dev) < 0)
--		goto error;
-+		return ret;
- 
- 	ret = vchiq_mmal_component_enable(
- 			dev->instance,
- 			dev->component[MMAL_COMPONENT_PREVIEW]);
- 	if (ret < 0)
--		goto error;
-+		return ret;
- 
- 	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "connecting %p to %p\n",
- 		 src, dst);
- 	ret = vchiq_mmal_port_connect_tunnel(dev->instance, src, dst);
- 	if (!ret)
- 		ret = vchiq_mmal_port_enable(dev->instance, src, NULL);
--error:
-+
- 	return ret;
- }
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0394-staging-bcm2835-camera-Remove-dead-email-addresses.patch b/target/linux/brcm2708/patches-4.14/950-0394-staging-bcm2835-camera-Remove-dead-email-addresses.patch
deleted file mode 100644
index 0a6ebf8d5..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0394-staging-bcm2835-camera-Remove-dead-email-addresses.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From 1e2e9ad8d312dc4931e572489043ccd86745f3ee Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Fri, 10 Mar 2017 17:35:38 +0000
-Subject: [PATCH 394/454] staging: bcm2835-camera: Remove dead email addresses
-
-None of the listed author email addresses were valid.
-Keep list of authors and the companies they represented.
-Update my email address.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../vc04_services/bcm2835-camera/bcm2835-camera.c        | 9 +++++----
- .../vc04_services/bcm2835-camera/bcm2835-camera.h        | 9 +++++----
- drivers/staging/vc04_services/bcm2835-camera/controls.c  | 9 +++++----
- .../staging/vc04_services/bcm2835-camera/mmal-common.h   | 9 +++++----
- .../vc04_services/bcm2835-camera/mmal-encodings.h        | 9 +++++----
- .../vc04_services/bcm2835-camera/mmal-msg-common.h       | 9 +++++----
- .../vc04_services/bcm2835-camera/mmal-msg-format.h       | 9 +++++----
- .../staging/vc04_services/bcm2835-camera/mmal-msg-port.h | 9 +++++----
- drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h  | 9 +++++----
- .../vc04_services/bcm2835-camera/mmal-parameters.h       | 9 +++++----
- .../staging/vc04_services/bcm2835-camera/mmal-vchiq.c    | 9 +++++----
- .../staging/vc04_services/bcm2835-camera/mmal-vchiq.h    | 9 +++++----
- 12 files changed, 60 insertions(+), 48 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  */
- 
- #include <linux/errno.h>
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  *
-  * core driver device
-  */
---- a/drivers/staging/vc04_services/bcm2835-camera/controls.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  */
- 
- #include <linux/errno.h>
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-common.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  *
-  * MMAL structures
-  *
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-encodings.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-encodings.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  */
- #ifndef MMAL_ENCODINGS_H
- #define MMAL_ENCODINGS_H
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-common.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-common.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  */
- 
- #ifndef MMAL_MSG_COMMON_H
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-format.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-format.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  */
- 
- #ifndef MMAL_MSG_FORMAT_H
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-port.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-port.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  */
- 
- /* MMAL_PORT_TYPE_T */
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  */
- 
- /* all the data structures which serialise the MMAL protocol. note
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  */
- 
- /* common parameters */
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  *
-  * V4L2 driver MMAL vchiq interface code
-  */
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-@@ -7,10 +7,11 @@
-  * License.  See the file COPYING in the main directory of this archive
-  * for more details.
-  *
-- * Authors: Vincent Sanders <vincent.sanders@collabora.co.uk>
-- *          Dave Stevenson <dsteve@broadcom.com>
-- *          Simon Mellor <simellor@broadcom.com>
-- *          Luke Diamand <luked@broadcom.com>
-+ * Authors: Vincent Sanders @ Collabora
-+ *          Dave Stevenson @ Broadcom
-+ *		(now dave.stevenson@raspberrypi.org)
-+ *          Simon Mellor @ Broadcom
-+ *          Luke Diamand @ Broadcom
-  *
-  * MMAL interface to VCHIQ message passing
-  */
diff --git a/target/linux/brcm2708/patches-4.14/950-0395-staging-bcm2835-camera-Fix-comment-style-violations.patch b/target/linux/brcm2708/patches-4.14/950-0395-staging-bcm2835-camera-Fix-comment-style-violations.patch
deleted file mode 100644
index 10afc8390..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0395-staging-bcm2835-camera-Fix-comment-style-violations.patch
+++ /dev/null
@@ -1,617 +0,0 @@
-From 7fff5af1dafbcc5d21d22ea35249ca4dc26999d9 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 13:49:32 +0000
-Subject: [PATCH 395/454] staging: bcm2835-camera: Fix comment style
- violations.
-
-Fix comment style violations in the header files.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/mmal-msg-format.h          |  95 ++++++------
- .../bcm2835-camera/mmal-msg-port.h            | 124 ++++++++--------
- .../vc04_services/bcm2835-camera/mmal-msg.h   | 135 +++++++++---------
- 3 files changed, 185 insertions(+), 169 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-format.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-format.h
-@@ -22,22 +22,23 @@
- /* MMAL_ES_FORMAT_T */
- 
- struct mmal_audio_format {
--	u32 channels;           /**< Number of audio channels */
--	u32 sample_rate;        /**< Sample rate */
-+	u32 channels;		/* Number of audio channels */
-+	u32 sample_rate;	/* Sample rate */
- 
--	u32 bits_per_sample;    /**< Bits per sample */
--	u32 block_align;        /**< Size of a block of data */
-+	u32 bits_per_sample;	/* Bits per sample */
-+	u32 block_align;	/* Size of a block of data */
- };
- 
- struct mmal_video_format {
--	u32 width;        /**< Width of frame in pixels */
--	u32 height;       /**< Height of frame in rows of pixels */
--	struct mmal_rect crop;         /**< Visible region of the frame */
--	struct mmal_rational frame_rate;   /**< Frame rate */
--	struct mmal_rational par;          /**< Pixel aspect ratio */
--
--	/* FourCC specifying the color space of the video stream. See the
--	 * \ref MmalColorSpace "pre-defined color spaces" for some examples.
-+	u32 width;		/* Width of frame in pixels */
-+	u32 height;		/* Height of frame in rows of pixels */
-+	struct mmal_rect crop;	/* Visible region of the frame */
-+	struct mmal_rational frame_rate;	/* Frame rate */
-+	struct mmal_rational par;		/* Pixel aspect ratio */
-+
-+	/*
-+	 * FourCC specifying the color space of the video stream. See the
-+	 * MmalColorSpace "pre-defined color spaces" for some examples.
- 	 */
- 	u32 color_space;
- };
-@@ -53,48 +54,56 @@ union mmal_es_specific_format {
- 	struct mmal_subpicture_format subpicture;
- };
- 
--/** Definition of an elementary stream format (MMAL_ES_FORMAT_T) */
-+/* Definition of an elementary stream format (MMAL_ES_FORMAT_T) */
- struct mmal_es_format_local {
--	u32 type;      /* enum mmal_es_type */
--
--	u32 encoding;  /* FourCC specifying encoding of the elementary stream.*/
--	u32 encoding_variant; /* FourCC specifying the specific
--			       * encoding variant of the elementary
--			       * stream.
--			       */
--
--	union mmal_es_specific_format *es;  /* Type specific
--					     * information for the
--					     * elementary stream
--					     */
-+	u32 type;	/* enum mmal_es_type */
- 
--	u32 bitrate;        /**< Bitrate in bits per second */
--	u32 flags; /**< Flags describing properties of the elementary stream. */
-+	u32 encoding;	/* FourCC specifying encoding of the elementary
-+			 * stream.
-+			 */
-+	u32 encoding_variant;	/* FourCC specifying the specific
-+				 * encoding variant of the elementary
-+				 * stream.
-+				 */
-+
-+	union mmal_es_specific_format *es;	/* Type specific
-+						 * information for the
-+						 * elementary stream
-+						 */
-+
-+	u32 bitrate;	/* Bitrate in bits per second */
-+	u32 flags;	/* Flags describing properties of the elementary
-+			 * stream.
-+			 */
- 
--	u32 extradata_size;       /**< Size of the codec specific data */
--	u8  *extradata;           /**< Codec specific data */
-+	u32 extradata_size;	/* Size of the codec specific data */
-+	u8  *extradata;		/* Codec specific data */
- };
- 
--/** Remote definition of an elementary stream format (MMAL_ES_FORMAT_T) */
-+/* Remote definition of an elementary stream format (MMAL_ES_FORMAT_T) */
- struct mmal_es_format {
--	u32 type;      /* enum mmal_es_type */
-+	u32 type;	/* enum mmal_es_type */
- 
--	u32 encoding;  /* FourCC specifying encoding of the elementary stream.*/
--	u32 encoding_variant; /* FourCC specifying the specific
--			       * encoding variant of the elementary
--			       * stream.
--			       */
-+	u32 encoding;	/* FourCC specifying encoding of the elementary
-+			 * stream.
-+			 */
-+	u32 encoding_variant;	/* FourCC specifying the specific
-+				 * encoding variant of the elementary
-+				 * stream.
-+				 */
- 
--	u32 es; /* Type specific
-+	u32 es;	/* Type specific
- 		 * information for the
- 		 * elementary stream
- 		 */
- 
--	u32 bitrate;        /**< Bitrate in bits per second */
--	u32 flags; /**< Flags describing properties of the elementary stream. */
-+	u32 bitrate;	/* Bitrate in bits per second */
-+	u32 flags;	/* Flags describing properties of the elementary
-+			 * stream.
-+			 */
- 
--	u32 extradata_size;       /**< Size of the codec specific data */
--	u32 extradata;           /**< Codec specific data */
-+	u32 extradata_size;	/* Size of the codec specific data */
-+	u32 extradata;		/* Codec specific data */
- };
- 
- #endif /* MMAL_MSG_FORMAT_H */
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-port.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg-port.h
-@@ -16,28 +16,31 @@
- 
- /* MMAL_PORT_TYPE_T */
- enum mmal_port_type {
--	MMAL_PORT_TYPE_UNKNOWN = 0,  /**< Unknown port type */
--	MMAL_PORT_TYPE_CONTROL,      /**< Control port */
--	MMAL_PORT_TYPE_INPUT,        /**< Input port */
--	MMAL_PORT_TYPE_OUTPUT,       /**< Output port */
--	MMAL_PORT_TYPE_CLOCK,        /**< Clock port */
-+	MMAL_PORT_TYPE_UNKNOWN = 0,	/* Unknown port type */
-+	MMAL_PORT_TYPE_CONTROL,		/* Control port */
-+	MMAL_PORT_TYPE_INPUT,		/* Input port */
-+	MMAL_PORT_TYPE_OUTPUT,		/* Output port */
-+	MMAL_PORT_TYPE_CLOCK,		/* Clock port */
- };
- 
--/** The port is pass-through and doesn't need buffer headers allocated */
-+/* The port is pass-through and doesn't need buffer headers allocated */
- #define MMAL_PORT_CAPABILITY_PASSTHROUGH                       0x01
--/** The port wants to allocate the buffer payloads.
-+/*
-+ *The port wants to allocate the buffer payloads.
-  * This signals a preference that payload allocation should be done
-  * on this port for efficiency reasons.
-  */
- #define MMAL_PORT_CAPABILITY_ALLOCATION                        0x02
--/** The port supports format change events.
-+/*
-+ * The port supports format change events.
-  * This applies to input ports and is used to let the client know
-  * whether the port supports being reconfigured via a format
-  * change event (i.e. without having to disable the port).
-  */
- #define MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE      0x04
- 
--/* mmal port structure (MMAL_PORT_T)
-+/*
-+ * mmal port structure (MMAL_PORT_T)
-  *
-  * most elements are informational only, the pointer values for
-  * interogation messages are generally provided as additional
-@@ -45,50 +48,50 @@ enum mmal_port_type {
-  * buffer_num, buffer_size and userdata parameters are writable.
-  */
- struct mmal_port {
--	u32 priv; /* Private member used by the framework */
--	u32 name; /* Port name. Used for debugging purposes (RO) */
-+	u32 priv;	/* Private member used by the framework */
-+	u32 name;	/* Port name. Used for debugging purposes (RO) */
- 
--	u32 type;      /* Type of the port (RO) enum mmal_port_type */
--	u16 index;     /* Index of the port in its type list (RO) */
--	u16 index_all; /* Index of the port in the list of all ports (RO) */
--
--	u32 is_enabled; /* Indicates whether the port is enabled or not (RO) */
--	u32 format; /* Format of the elementary stream */
--
--	u32 buffer_num_min; /* Minimum number of buffers the port
--			     *   requires (RO).  This is set by the
--			     *   component.
--			     */
--
--	u32 buffer_size_min; /* Minimum size of buffers the port
--			      * requires (RO).  This is set by the
--			      * component.
--			      */
--
--	u32 buffer_alignment_min; /* Minimum alignment requirement for
--				   * the buffers (RO).  A value of
--				   * zero means no special alignment
--				   * requirements.  This is set by the
--				   * component.
--				   */
--
--	u32 buffer_num_recommended;  /* Number of buffers the port
--				      * recommends for optimal
--				      * performance (RO).  A value of
--				      * zero means no special
--				      * recommendation.  This is set
--				      * by the component.
--				      */
--
--	u32 buffer_size_recommended; /* Size of buffers the port
--				      * recommends for optimal
--				      * performance (RO).  A value of
--				      * zero means no special
--				      * recommendation.  This is set
--				      * by the component.
--				      */
-+	u32 type;	/* Type of the port (RO) enum mmal_port_type */
-+	u16 index;	/* Index of the port in its type list (RO) */
-+	u16 index_all;	/* Index of the port in the list of all ports (RO) */
-+
-+	u32 is_enabled;	/* Indicates whether the port is enabled or not (RO) */
-+	u32 format;	/* Format of the elementary stream */
-+
-+	u32 buffer_num_min;	/* Minimum number of buffers the port
-+				 *   requires (RO).  This is set by the
-+				 *   component.
-+				 */
-+
-+	u32 buffer_size_min;	/* Minimum size of buffers the port
-+				 * requires (RO).  This is set by the
-+				 * component.
-+				 */
-+
-+	u32 buffer_alignment_min;/* Minimum alignment requirement for
-+				  * the buffers (RO).  A value of
-+				  * zero means no special alignment
-+				  * requirements.  This is set by the
-+				  * component.
-+				  */
-+
-+	u32 buffer_num_recommended;	/* Number of buffers the port
-+					 * recommends for optimal
-+					 * performance (RO).  A value of
-+					 * zero means no special
-+					 * recommendation.  This is set
-+					 * by the component.
-+					 */
-+
-+	u32 buffer_size_recommended;	/* Size of buffers the port
-+					 * recommends for optimal
-+					 * performance (RO).  A value of
-+					 * zero means no special
-+					 * recommendation.  This is set
-+					 * by the component.
-+					 */
- 
--	u32 buffer_num; /* Actual number of buffers the port will use.
-+	u32 buffer_num;	/* Actual number of buffers the port will use.
- 			 * This is set by the client.
- 			 */
- 
-@@ -97,14 +100,13 @@ struct mmal_port {
- 			  * the client.
- 			  */
- 
--	u32 component; /* Component this port belongs to (Read Only) */
-+	u32 component;	/* Component this port belongs to (Read Only) */
- 
--	u32 userdata; /* Field reserved for use by the client */
--
--	u32 capabilities; /* Flags describing the capabilities of a
--			   * port (RO).  Bitwise combination of \ref
--			   * portcapabilities "Port capabilities"
--			   * values.
--			   */
-+	u32 userdata;	/* Field reserved for use by the client */
- 
-+	u32 capabilities;	/* Flags describing the capabilities of a
-+				 * port (RO).  Bitwise combination of \ref
-+				 * portcapabilities "Port capabilities"
-+				 * values.
-+				 */
- };
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h
-@@ -14,7 +14,8 @@
-  *          Luke Diamand @ Broadcom
-  */
- 
--/* all the data structures which serialise the MMAL protocol. note
-+/*
-+ * all the data structures which serialise the MMAL protocol. note
-  * these are directly mapped onto the recived message data.
-  *
-  * BEWARE: They seem to *assume* pointers are u32 and that there is no
-@@ -44,51 +45,51 @@ enum mmal_msg_type {
- 	MMAL_MSG_TYPE_SERVICE_CLOSED,
- 	MMAL_MSG_TYPE_GET_VERSION,
- 	MMAL_MSG_TYPE_COMPONENT_CREATE,
--	MMAL_MSG_TYPE_COMPONENT_DESTROY, /* 5 */
-+	MMAL_MSG_TYPE_COMPONENT_DESTROY,	/* 5 */
- 	MMAL_MSG_TYPE_COMPONENT_ENABLE,
- 	MMAL_MSG_TYPE_COMPONENT_DISABLE,
- 	MMAL_MSG_TYPE_PORT_INFO_GET,
- 	MMAL_MSG_TYPE_PORT_INFO_SET,
--	MMAL_MSG_TYPE_PORT_ACTION, /* 10 */
-+	MMAL_MSG_TYPE_PORT_ACTION,		/* 10 */
- 	MMAL_MSG_TYPE_BUFFER_FROM_HOST,
- 	MMAL_MSG_TYPE_BUFFER_TO_HOST,
- 	MMAL_MSG_TYPE_GET_STATS,
- 	MMAL_MSG_TYPE_PORT_PARAMETER_SET,
--	MMAL_MSG_TYPE_PORT_PARAMETER_GET, /* 15 */
-+	MMAL_MSG_TYPE_PORT_PARAMETER_GET,	/* 15 */
- 	MMAL_MSG_TYPE_EVENT_TO_HOST,
- 	MMAL_MSG_TYPE_GET_CORE_STATS_FOR_PORT,
- 	MMAL_MSG_TYPE_OPAQUE_ALLOCATOR,
- 	MMAL_MSG_TYPE_CONSUME_MEM,
--	MMAL_MSG_TYPE_LMK, /* 20 */
-+	MMAL_MSG_TYPE_LMK,			/* 20 */
- 	MMAL_MSG_TYPE_OPAQUE_ALLOCATOR_DESC,
- 	MMAL_MSG_TYPE_DRM_GET_LHS32,
- 	MMAL_MSG_TYPE_DRM_GET_TIME,
- 	MMAL_MSG_TYPE_BUFFER_FROM_HOST_ZEROLEN,
--	MMAL_MSG_TYPE_PORT_FLUSH, /* 25 */
-+	MMAL_MSG_TYPE_PORT_FLUSH,		/* 25 */
- 	MMAL_MSG_TYPE_HOST_LOG,
- 	MMAL_MSG_TYPE_MSG_LAST
- };
- 
- /* port action request messages differ depending on the action type */
- enum mmal_msg_port_action_type {
--	MMAL_MSG_PORT_ACTION_TYPE_UNKNOWN = 0,      /* Unkown action */
--	MMAL_MSG_PORT_ACTION_TYPE_ENABLE,           /* Enable a port */
--	MMAL_MSG_PORT_ACTION_TYPE_DISABLE,          /* Disable a port */
--	MMAL_MSG_PORT_ACTION_TYPE_FLUSH,            /* Flush a port */
--	MMAL_MSG_PORT_ACTION_TYPE_CONNECT,          /* Connect ports */
--	MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT,       /* Disconnect ports */
-+	MMAL_MSG_PORT_ACTION_TYPE_UNKNOWN = 0,	/* Unknown action */
-+	MMAL_MSG_PORT_ACTION_TYPE_ENABLE,	/* Enable a port */
-+	MMAL_MSG_PORT_ACTION_TYPE_DISABLE,	/* Disable a port */
-+	MMAL_MSG_PORT_ACTION_TYPE_FLUSH,	/* Flush a port */
-+	MMAL_MSG_PORT_ACTION_TYPE_CONNECT,	/* Connect ports */
-+	MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT,	/* Disconnect ports */
- 	MMAL_MSG_PORT_ACTION_TYPE_SET_REQUIREMENTS, /* Set buffer requirements*/
- };
- 
- struct mmal_msg_header {
- 	u32 magic;
--	u32 type; /** enum mmal_msg_type */
-+	u32 type;	/* enum mmal_msg_type */
- 
- 	/* Opaque handle to the control service */
- 	u32 control_service;
- 
--	u32 context; /** a u32 per message context */
--	u32 status; /** The status of the vchiq operation */
-+	u32 context;	/* a u32 per message context */
-+	u32 status;	/* The status of the vchiq operation */
- 	u32 padding;
- };
- 
-@@ -102,9 +103,9 @@ struct mmal_msg_version {
- 
- /* request to VC to create component */
- struct mmal_msg_component_create {
--	u32 client_component; /* component context */
-+	u32 client_component;	/* component context */
- 	char name[128];
--	u32 pid;                /* For debug */
-+	u32 pid;		/* For debug */
- };
- 
- /* reply from VC to component creation request */
-@@ -124,7 +125,7 @@ struct mmal_msg_component_destroy {
- };
- 
- struct mmal_msg_component_destroy_reply {
--	u32 status; /** The component destruction status */
-+	u32 status; /* The component destruction status */
- };
- 
- /* request and reply to VC to enable a component */
-@@ -133,7 +134,7 @@ struct mmal_msg_component_enable {
- };
- 
- struct mmal_msg_component_enable_reply {
--	u32 status; /** The component enable status */
-+	u32 status; /* The component enable status */
- };
- 
- /* request and reply to VC to disable a component */
-@@ -142,7 +143,7 @@ struct mmal_msg_component_disable {
- };
- 
- struct mmal_msg_component_disable_reply {
--	u32 status; /** The component disable status */
-+	u32 status; /* The component disable status */
- };
- 
- /* request to VC to get port information */
-@@ -154,12 +155,12 @@ struct mmal_msg_port_info_get {
- 
- /* reply from VC to get port info request */
- struct mmal_msg_port_info_get_reply {
--	u32 status; /** enum mmal_msg_status */
--	u32 component_handle;  /* component handle port is associated with */
--	u32 port_type;         /* enum mmal_msg_port_type */
--	u32 port_index;        /* port indexed in query */
--	s32 found;             /* unused */
--	u32 port_handle;               /**< Handle to use for this port */
-+	u32 status;		/* enum mmal_msg_status */
-+	u32 component_handle;	/* component handle port is associated with */
-+	u32 port_type;		/* enum mmal_msg_port_type */
-+	u32 port_index;		/* port indexed in query */
-+	s32 found;		/* unused */
-+	u32 port_handle;	/* Handle to use for this port */
- 	struct mmal_port port;
- 	struct mmal_es_format format; /* elementary stream format */
- 	union mmal_es_specific_format es; /* es type specific data */
-@@ -169,8 +170,8 @@ struct mmal_msg_port_info_get_reply {
- /* request to VC to set port information */
- struct mmal_msg_port_info_set {
- 	u32 component_handle;
--	u32 port_type;         /* enum mmal_msg_port_type */
--	u32 port_index;           /* port indexed in query */
-+	u32 port_type;		/* enum mmal_msg_port_type */
-+	u32 port_index;		/* port indexed in query */
- 	struct mmal_port port;
- 	struct mmal_es_format format;
- 	union mmal_es_specific_format es;
-@@ -180,11 +181,11 @@ struct mmal_msg_port_info_set {
- /* reply from VC to port info set request */
- struct mmal_msg_port_info_set_reply {
- 	u32 status;
--	u32 component_handle;  /* component handle port is associated with */
--	u32 port_type;         /* enum mmal_msg_port_type */
--	u32 index;             /* port indexed in query */
--	s32 found;             /* unused */
--	u32 port_handle;               /**< Handle to use for this port */
-+	u32 component_handle;	/* component handle port is associated with */
-+	u32 port_type;		/* enum mmal_msg_port_type */
-+	u32 index;		/* port indexed in query */
-+	s32 found;		/* unused */
-+	u32 port_handle;	/* Handle to use for this port */
- 	struct mmal_port port;
- 	struct mmal_es_format format;
- 	union mmal_es_specific_format es;
-@@ -195,7 +196,7 @@ struct mmal_msg_port_info_set_reply {
- struct mmal_msg_port_action_port {
- 	u32 component_handle;
- 	u32 port_handle;
--	u32 action; /* enum mmal_msg_port_action_type */
-+	u32 action;		/* enum mmal_msg_port_action_type */
- 	struct mmal_port port;
- };
- 
-@@ -203,50 +204,53 @@ struct mmal_msg_port_action_port {
- struct mmal_msg_port_action_handle {
- 	u32 component_handle;
- 	u32 port_handle;
--	u32 action; /* enum mmal_msg_port_action_type */
-+	u32 action;		/* enum mmal_msg_port_action_type */
- 	u32 connect_component_handle;
- 	u32 connect_port_handle;
- };
- 
- struct mmal_msg_port_action_reply {
--	u32 status; /** The port action operation status */
-+	u32 status;	/* The port action operation status */
- };
- 
- /* MMAL buffer transfer */
- 
--/** Size of space reserved in a buffer message for short messages. */
-+/* Size of space reserved in a buffer message for short messages. */
- #define MMAL_VC_SHORT_DATA 128
- 
--/** Signals that the current payload is the end of the stream of data */
-+/* Signals that the current payload is the end of the stream of data */
- #define MMAL_BUFFER_HEADER_FLAG_EOS                    (1<<0)
--/** Signals that the start of the current payload starts a frame */
-+/* Signals that the start of the current payload starts a frame */
- #define MMAL_BUFFER_HEADER_FLAG_FRAME_START            (1<<1)
--/** Signals that the end of the current payload ends a frame */
-+/* Signals that the end of the current payload ends a frame */
- #define MMAL_BUFFER_HEADER_FLAG_FRAME_END              (1<<2)
--/** Signals that the current payload contains only complete frames (>1) */
-+/* Signals that the current payload contains only complete frames (>1) */
- #define MMAL_BUFFER_HEADER_FLAG_FRAME                  \
- 	(MMAL_BUFFER_HEADER_FLAG_FRAME_START|MMAL_BUFFER_HEADER_FLAG_FRAME_END)
--/** Signals that the current payload is a keyframe (i.e. self decodable) */
-+/* Signals that the current payload is a keyframe (i.e. self decodable) */
- #define MMAL_BUFFER_HEADER_FLAG_KEYFRAME               (1<<3)
--/** Signals a discontinuity in the stream of data (e.g. after a seek).
-+/*
-+ * Signals a discontinuity in the stream of data (e.g. after a seek).
-  * Can be used for instance by a decoder to reset its state
-  */
- #define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY          (1<<4)
--/** Signals a buffer containing some kind of config data for the component
-+/*
-+ * Signals a buffer containing some kind of config data for the component
-  * (e.g. codec config data)
-  */
- #define MMAL_BUFFER_HEADER_FLAG_CONFIG                 (1<<5)
--/** Signals an encrypted payload */
-+/* Signals an encrypted payload */
- #define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED              (1<<6)
--/** Signals a buffer containing side information */
-+/* Signals a buffer containing side information */
- #define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO          (1<<7)
--/** Signals a buffer which is the snapshot/postview image from a stills
-+/*
-+ * Signals a buffer which is the snapshot/postview image from a stills
-  * capture
-  */
- #define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT              (1<<8)
--/** Signals a buffer which contains data known to be corrupted */
-+/* Signals a buffer which contains data known to be corrupted */
- #define MMAL_BUFFER_HEADER_FLAG_CORRUPTED              (1<<9)
--/** Signals that a buffer failed to be transmitted */
-+/* Signals that a buffer failed to be transmitted */
- #define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED    (1<<10)
- 
- struct mmal_driver_buffer {
-@@ -258,8 +262,8 @@ struct mmal_driver_buffer {
- 
- /* buffer header */
- struct mmal_buffer_header {
--	u32 next; /* next header */
--	u32 priv; /* framework private data */
-+	u32 next;	/* next header */
-+	u32 priv;	/* framework private data */
- 	u32 cmd;
- 	u32 data;
- 	u32 alloc_size;
-@@ -284,7 +288,8 @@ struct mmal_buffer_header_type_specific
- };
- 
- struct mmal_msg_buffer_from_host {
--	/* The front 32 bytes of the buffer header are copied
-+	/*
-+	 *The front 32 bytes of the buffer header are copied
- 	 * back to us in the reply to allow for context. This
- 	 * area is used to store two mmal_driver_buffer structures to
- 	 * allow for multiple concurrent service users.
-@@ -299,7 +304,7 @@ struct mmal_msg_buffer_from_host {
- 	s32 is_zero_copy;
- 	s32 has_reference;
- 
--	/** allows short data to be xfered in control message */
-+	/* allows short data to be xfered in control message */
- 	u32 payload_in_message;
- 	u8 short_data[MMAL_VC_SHORT_DATA];
- };
-@@ -309,10 +314,10 @@ struct mmal_msg_buffer_from_host {
- #define MMAL_WORKER_PORT_PARAMETER_SPACE      96
- 
- struct mmal_msg_port_parameter_set {
--	u32 component_handle; /* component */
--	u32 port_handle;      /* port */
--	u32 id;     /* Parameter ID  */
--	u32 size;      /* Parameter size */
-+	u32 component_handle;	/* component */
-+	u32 port_handle;	/* port */
-+	u32 id;			/* Parameter ID  */
-+	u32 size;		/* Parameter size */
- 	uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE];
- };
- 
-@@ -325,16 +330,16 @@ struct mmal_msg_port_parameter_set_reply
- /* port parameter getting */
- 
- struct mmal_msg_port_parameter_get {
--	u32 component_handle; /* component */
--	u32 port_handle;      /* port */
--	u32 id;     /* Parameter ID  */
--	u32 size;      /* Parameter size */
-+	u32 component_handle;	/* component */
-+	u32 port_handle;	/* port */
-+	u32 id;			/* Parameter ID  */
-+	u32 size;		/* Parameter size */
- };
- 
- struct mmal_msg_port_parameter_get_reply {
--	u32 status;           /* Status of mmal_port_parameter_get call */
--	u32 id;     /* Parameter ID  */
--	u32 size;      /* Parameter size */
-+	u32 status;		/* Status of mmal_port_parameter_get call */
-+	u32 id;			/* Parameter ID  */
-+	u32 size;		/* Parameter size */
- 	uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE];
- };
- 
-@@ -342,7 +347,7 @@ struct mmal_msg_port_parameter_get_reply
- #define MMAL_WORKER_EVENT_SPACE 256
- 
- struct mmal_msg_event_to_host {
--	u32 client_component; /* component context */
-+	u32 client_component;	/* component context */
- 
- 	u32 port_type;
- 	u32 port_num;
diff --git a/target/linux/brcm2708/patches-4.14/950-0396-staging-bcm2835-camera-Fix-spacing-around-operators.patch b/target/linux/brcm2708/patches-4.14/950-0396-staging-bcm2835-camera-Fix-spacing-around-operators.patch
deleted file mode 100644
index 022c12eec..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0396-staging-bcm2835-camera-Fix-spacing-around-operators.patch
+++ /dev/null
@@ -1,145 +0,0 @@
-From 4310db07054697c7c1750cafa57b843f76fd7df0 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 14:13:03 +0000
-Subject: [PATCH 396/454] staging: bcm2835-camera: Fix spacing around operators
-
-Fix checkpatch warnings over spaces around operators.
-Many were around operations that can be replaced with the
-BIT(x) macro, so replace with that where appropriate.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../vc04_services/bcm2835-camera/controls.c   | 32 +++++++++----------
- .../vc04_services/bcm2835-camera/mmal-msg.h   | 25 ++++++++-------
- .../bcm2835-camera/mmal-parameters.h          | 12 +++----
- 3 files changed, 35 insertions(+), 34 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/controls.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c
-@@ -1126,10 +1126,10 @@ static const struct bm2835_mmal_v4l2_ctr
- 	{
- 		V4L2_CID_MPEG_VIDEO_H264_PROFILE,
- 		MMAL_CONTROL_TYPE_STD_MENU,
--		~((1<<V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
--			(1<<V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
--			(1<<V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
--			(1<<V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)),
-+		~(BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)),
- 		V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
- 		V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 1, NULL,
- 		MMAL_PARAMETER_PROFILE,
-@@ -1138,18 +1138,18 @@ static const struct bm2835_mmal_v4l2_ctr
- 	},
- 	{
- 		V4L2_CID_MPEG_VIDEO_H264_LEVEL, MMAL_CONTROL_TYPE_STD_MENU,
--		~((1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
--			(1<<V4L2_MPEG_VIDEO_H264_LEVEL_4_0)),
-+		~(BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
-+		  BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0)),
- 		V4L2_MPEG_VIDEO_H264_LEVEL_4_0,
- 		V4L2_MPEG_VIDEO_H264_LEVEL_4_0, 1, NULL,
- 		MMAL_PARAMETER_PROFILE,
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-msg.h
-@@ -219,39 +219,40 @@ struct mmal_msg_port_action_reply {
- #define MMAL_VC_SHORT_DATA 128
- 
- /* Signals that the current payload is the end of the stream of data */
--#define MMAL_BUFFER_HEADER_FLAG_EOS                    (1<<0)
-+#define MMAL_BUFFER_HEADER_FLAG_EOS                    BIT(0)
- /* Signals that the start of the current payload starts a frame */
--#define MMAL_BUFFER_HEADER_FLAG_FRAME_START            (1<<1)
-+#define MMAL_BUFFER_HEADER_FLAG_FRAME_START            BIT(1)
- /* Signals that the end of the current payload ends a frame */
--#define MMAL_BUFFER_HEADER_FLAG_FRAME_END              (1<<2)
-+#define MMAL_BUFFER_HEADER_FLAG_FRAME_END              BIT(2)
- /* Signals that the current payload contains only complete frames (>1) */
- #define MMAL_BUFFER_HEADER_FLAG_FRAME                  \
--	(MMAL_BUFFER_HEADER_FLAG_FRAME_START|MMAL_BUFFER_HEADER_FLAG_FRAME_END)
-+	(MMAL_BUFFER_HEADER_FLAG_FRAME_START | \
-+	 MMAL_BUFFER_HEADER_FLAG_FRAME_END)
- /* Signals that the current payload is a keyframe (i.e. self decodable) */
--#define MMAL_BUFFER_HEADER_FLAG_KEYFRAME               (1<<3)
-+#define MMAL_BUFFER_HEADER_FLAG_KEYFRAME               BIT(3)
- /*
-  * Signals a discontinuity in the stream of data (e.g. after a seek).
-  * Can be used for instance by a decoder to reset its state
-  */
--#define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY          (1<<4)
-+#define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY          BIT(4)
- /*
-  * Signals a buffer containing some kind of config data for the component
-  * (e.g. codec config data)
-  */
--#define MMAL_BUFFER_HEADER_FLAG_CONFIG                 (1<<5)
-+#define MMAL_BUFFER_HEADER_FLAG_CONFIG                 BIT(5)
- /* Signals an encrypted payload */
--#define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED              (1<<6)
-+#define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED              BIT(6)
- /* Signals a buffer containing side information */
--#define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO          (1<<7)
-+#define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO          BIT(7)
- /*
-  * Signals a buffer which is the snapshot/postview image from a stills
-  * capture
-  */
--#define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT              (1<<8)
-+#define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT              BIT(8)
- /* Signals a buffer which contains data known to be corrupted */
--#define MMAL_BUFFER_HEADER_FLAG_CORRUPTED              (1<<9)
-+#define MMAL_BUFFER_HEADER_FLAG_CORRUPTED              BIT(9)
- /* Signals that a buffer failed to be transmitted */
--#define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED    (1<<10)
-+#define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED    BIT(10)
- 
- struct mmal_driver_buffer {
- 	u32 magic;
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-parameters.h
-@@ -26,17 +26,17 @@
- #define __MMAL_PARAMETERS_H
- 
- /** Common parameter ID group, used with many types of component. */
--#define MMAL_PARAMETER_GROUP_COMMON            (0<<16)
-+#define MMAL_PARAMETER_GROUP_COMMON            (0 << 16)
- /** Camera-specific parameter ID group. */
--#define MMAL_PARAMETER_GROUP_CAMERA            (1<<16)
-+#define MMAL_PARAMETER_GROUP_CAMERA            (1 << 16)
- /** Video-specific parameter ID group. */
--#define MMAL_PARAMETER_GROUP_VIDEO             (2<<16)
-+#define MMAL_PARAMETER_GROUP_VIDEO             (2 << 16)
- /** Audio-specific parameter ID group. */
--#define MMAL_PARAMETER_GROUP_AUDIO             (3<<16)
-+#define MMAL_PARAMETER_GROUP_AUDIO             (3 << 16)
- /** Clock-specific parameter ID group. */
--#define MMAL_PARAMETER_GROUP_CLOCK             (4<<16)
-+#define MMAL_PARAMETER_GROUP_CLOCK             (4 << 16)
- /** Miracast-specific parameter ID group. */
--#define MMAL_PARAMETER_GROUP_MIRACAST       (5<<16)
-+#define MMAL_PARAMETER_GROUP_MIRACAST       (5 << 16)
- 
- /* Common parameters */
- enum mmal_parameter_common_type {
diff --git a/target/linux/brcm2708/patches-4.14/950-0397-staging-bcm2835-camera-Reduce-length-of-enum-names.patch b/target/linux/brcm2708/patches-4.14/950-0397-staging-bcm2835-camera-Reduce-length-of-enum-names.patch
deleted file mode 100644
index bb57d135e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0397-staging-bcm2835-camera-Reduce-length-of-enum-names.patch
+++ /dev/null
@@ -1,771 +0,0 @@
-From 2a5b35b90041f190656984ee9299e0edf8e272e2 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 15:23:35 +0000
-Subject: [PATCH 397/454] staging: bcm2835-camera: Reduce length of enum names
-
-We have numerous lines over 80 chars, or oddly split. Many
-of these are due to using long enum names such as
-MMAL_COMPONENT_CAMERA.
-Reduce the length of these enum names.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 163 +++++++++---------
- .../bcm2835-camera/bcm2835-camera.h           |  20 +--
- .../vc04_services/bcm2835-camera/controls.c   |  47 +++--
- 3 files changed, 113 insertions(+), 117 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -87,7 +87,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_I420,
- 		.depth = 12,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 1,
- 		.remove_padding = 1,
- 	}, {
-@@ -96,7 +96,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_YUYV,
- 		.depth = 16,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 2,
- 		.remove_padding = 0,
- 	}, {
-@@ -105,7 +105,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_RGB24,
- 		.depth = 24,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 3,
- 		.remove_padding = 0,
- 	}, {
-@@ -114,7 +114,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = V4L2_FMT_FLAG_COMPRESSED,
- 		.mmal = MMAL_ENCODING_JPEG,
- 		.depth = 8,
--		.mmal_component = MMAL_COMPONENT_IMAGE_ENCODE,
-+		.mmal_component = COMP_IMAGE_ENCODE,
- 		.ybbp = 0,
- 		.remove_padding = 0,
- 	}, {
-@@ -123,7 +123,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = V4L2_FMT_FLAG_COMPRESSED,
- 		.mmal = MMAL_ENCODING_H264,
- 		.depth = 8,
--		.mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
-+		.mmal_component = COMP_VIDEO_ENCODE,
- 		.ybbp = 0,
- 		.remove_padding = 0,
- 	}, {
-@@ -132,7 +132,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = V4L2_FMT_FLAG_COMPRESSED,
- 		.mmal = MMAL_ENCODING_MJPEG,
- 		.depth = 8,
--		.mmal_component = MMAL_COMPONENT_VIDEO_ENCODE,
-+		.mmal_component = COMP_VIDEO_ENCODE,
- 		.ybbp = 0,
- 		.remove_padding = 0,
- 	}, {
-@@ -141,7 +141,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_YVYU,
- 		.depth = 16,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 2,
- 		.remove_padding = 0,
- 	}, {
-@@ -150,7 +150,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_VYUY,
- 		.depth = 16,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 2,
- 		.remove_padding = 0,
- 	}, {
-@@ -159,7 +159,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_UYVY,
- 		.depth = 16,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 2,
- 		.remove_padding = 0,
- 	}, {
-@@ -168,7 +168,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_NV12,
- 		.depth = 12,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 1,
- 		.remove_padding = 1,
- 	}, {
-@@ -177,7 +177,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_BGR24,
- 		.depth = 24,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 3,
- 		.remove_padding = 0,
- 	}, {
-@@ -186,7 +186,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_YV12,
- 		.depth = 12,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 1,
- 		.remove_padding = 1,
- 	}, {
-@@ -195,7 +195,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_NV21,
- 		.depth = 12,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 1,
- 		.remove_padding = 1,
- 	}, {
-@@ -204,7 +204,7 @@ static struct mmal_fmt formats[] = {
- 		.flags = 0,
- 		.mmal = MMAL_ENCODING_BGRA,
- 		.depth = 32,
--		.mmal_component = MMAL_COMPONENT_CAMERA,
-+		.mmal_component = COMP_CAMERA,
- 		.ybbp = 4,
- 		.remove_padding = 0,
- 	},
-@@ -321,7 +321,7 @@ static inline bool is_capturing(struct b
- {
- 	return dev->capture.camera_port ==
- 	    &dev->
--	    component[MMAL_COMPONENT_CAMERA]->output[MMAL_CAMERA_PORT_CAPTURE];
-+	    component[COMP_CAMERA]->output[CAM_PORT_CAPTURE];
- }
- 
- static void buffer_cb(struct vchiq_mmal_instance *instance,
-@@ -443,7 +443,7 @@ static int enable_camera(struct bm2835_m
- 	if (!dev->camera_use_count) {
- 		ret = vchiq_mmal_port_parameter_set(
- 			dev->instance,
--			&dev->component[MMAL_COMPONENT_CAMERA]->control,
-+			&dev->component[COMP_CAMERA]->control,
- 			MMAL_PARAMETER_CAMERA_NUM, &dev->camera_num,
- 			sizeof(dev->camera_num));
- 		if (ret < 0) {
-@@ -454,7 +454,7 @@ static int enable_camera(struct bm2835_m
- 
- 		ret = vchiq_mmal_component_enable(
- 				dev->instance,
--				dev->component[MMAL_COMPONENT_CAMERA]);
-+				dev->component[COMP_CAMERA]);
- 		if (ret < 0) {
- 			v4l2_err(&dev->v4l2_dev,
- 				 "Failed enabling camera, ret %d\n", ret);
-@@ -486,7 +486,7 @@ static int disable_camera(struct bm2835_
- 		ret =
- 		    vchiq_mmal_component_disable(
- 				dev->instance,
--				dev->component[MMAL_COMPONENT_CAMERA]);
-+				dev->component[COMP_CAMERA]);
- 		if (ret < 0) {
- 			v4l2_err(&dev->v4l2_dev,
- 				 "Failed disabling camera, ret %d\n", ret);
-@@ -494,7 +494,7 @@ static int disable_camera(struct bm2835_
- 		}
- 		vchiq_mmal_port_parameter_set(
- 			dev->instance,
--			&dev->component[MMAL_COMPONENT_CAMERA]->control,
-+			&dev->component[COMP_CAMERA]->control,
- 			MMAL_PARAMETER_CAMERA_NUM, &i,
- 			sizeof(i));
- 	}
-@@ -546,7 +546,7 @@ static int start_streaming(struct vb2_qu
- 	/* if the preview is not already running, wait for a few frames for AGC
- 	 * to settle down.
- 	 */
--	if (!dev->component[MMAL_COMPONENT_PREVIEW]->enabled)
-+	if (!dev->component[COMP_PREVIEW]->enabled)
- 		msleep(300);
- 
- 	/* enable the connection from camera to encoder (if applicable) */
-@@ -784,9 +784,9 @@ static int vidioc_s_fmt_vid_overlay(stru
- 	vidioc_try_fmt_vid_overlay(file, priv, f);
- 
- 	dev->overlay = f->fmt.win;
--	if (dev->component[MMAL_COMPONENT_PREVIEW]->enabled) {
-+	if (dev->component[COMP_PREVIEW]->enabled) {
- 		set_overlay_params(dev,
--				   &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]);
-+				   &dev->component[COMP_PREVIEW]->input[0]);
- 	}
- 
- 	return 0;
-@@ -799,13 +799,13 @@ static int vidioc_overlay(struct file *f
- 	struct vchiq_mmal_port *src;
- 	struct vchiq_mmal_port *dst;
- 
--	if ((on && dev->component[MMAL_COMPONENT_PREVIEW]->enabled) ||
--	    (!on && !dev->component[MMAL_COMPONENT_PREVIEW]->enabled))
-+	if ((on && dev->component[COMP_PREVIEW]->enabled) ||
-+	    (!on && !dev->component[COMP_PREVIEW]->enabled))
- 		return 0;	/* already in requested state */
- 
- 	src =
--	    &dev->component[MMAL_COMPONENT_CAMERA]->
--	    output[MMAL_CAMERA_PORT_PREVIEW];
-+	    &dev->component[COMP_CAMERA]->
-+	    output[CAM_PORT_PREVIEW];
- 
- 	if (!on) {
- 		/* disconnect preview ports and disable component */
-@@ -817,14 +817,14 @@ static int vidioc_overlay(struct file *f
- 		if (ret >= 0)
- 			ret = vchiq_mmal_component_disable(
- 					dev->instance,
--					dev->component[MMAL_COMPONENT_PREVIEW]);
-+					dev->component[COMP_PREVIEW]);
- 
- 		disable_camera(dev);
- 		return ret;
- 	}
- 
- 	/* set preview port format and connect it to output */
--	dst = &dev->component[MMAL_COMPONENT_PREVIEW]->input[0];
-+	dst = &dev->component[COMP_PREVIEW]->input[0];
- 
- 	ret = vchiq_mmal_port_set_format(dev->instance, src);
- 	if (ret < 0)
-@@ -839,7 +839,7 @@ static int vidioc_overlay(struct file *f
- 
- 	ret = vchiq_mmal_component_enable(
- 			dev->instance,
--			dev->component[MMAL_COMPONENT_PREVIEW]);
-+			dev->component[COMP_PREVIEW]);
- 	if (ret < 0)
- 		return ret;
- 
-@@ -860,8 +860,8 @@ static int vidioc_g_fbuf(struct file *fi
- 	 */
- 	struct bm2835_mmal_dev *dev = video_drvdata(file);
- 	struct vchiq_mmal_port *preview_port =
--		    &dev->component[MMAL_COMPONENT_CAMERA]->
--		    output[MMAL_CAMERA_PORT_PREVIEW];
-+		&dev->component[COMP_CAMERA]->
-+		output[CAM_PORT_PREVIEW];
- 
- 	a->capability = V4L2_FBUF_CAP_EXTERNOVERLAY |
- 			V4L2_FBUF_CAP_GLOBAL_ALPHA;
-@@ -1064,31 +1064,31 @@ static int mmal_setup_components(struct
- 	}
- 	/* format dependent port setup */
- 	switch (mfmt->mmal_component) {
--	case MMAL_COMPONENT_CAMERA:
-+	case COMP_CAMERA:
- 		/* Make a further decision on port based on resolution */
- 		if (f->fmt.pix.width <= max_video_width
- 		    && f->fmt.pix.height <= max_video_height)
- 			camera_port = port =
--			    &dev->component[MMAL_COMPONENT_CAMERA]->
--			    output[MMAL_CAMERA_PORT_VIDEO];
-+			    &dev->component[COMP_CAMERA]->
-+			    output[CAM_PORT_VIDEO];
- 		else
- 			camera_port = port =
--			    &dev->component[MMAL_COMPONENT_CAMERA]->
--			    output[MMAL_CAMERA_PORT_CAPTURE];
-+			    &dev->component[COMP_CAMERA]->
-+			    output[CAM_PORT_CAPTURE];
- 		break;
--	case MMAL_COMPONENT_IMAGE_ENCODE:
--		encode_component = dev->component[MMAL_COMPONENT_IMAGE_ENCODE];
--		port = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0];
-+	case COMP_IMAGE_ENCODE:
-+		encode_component = dev->component[COMP_IMAGE_ENCODE];
-+		port = &dev->component[COMP_IMAGE_ENCODE]->output[0];
- 		camera_port =
--		    &dev->component[MMAL_COMPONENT_CAMERA]->
--		    output[MMAL_CAMERA_PORT_CAPTURE];
-+		    &dev->component[COMP_CAMERA]->
-+		    output[CAM_PORT_CAPTURE];
- 		break;
--	case MMAL_COMPONENT_VIDEO_ENCODE:
--		encode_component = dev->component[MMAL_COMPONENT_VIDEO_ENCODE];
--		port = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+	case COMP_VIDEO_ENCODE:
-+		encode_component = dev->component[COMP_VIDEO_ENCODE];
-+		port = &dev->component[COMP_VIDEO_ENCODE]->output[0];
- 		camera_port =
--		    &dev->component[MMAL_COMPONENT_CAMERA]->
--		    output[MMAL_CAMERA_PORT_VIDEO];
-+		    &dev->component[COMP_CAMERA]->
-+		    output[CAM_PORT_VIDEO];
- 		break;
- 	default:
- 		break;
-@@ -1130,13 +1130,12 @@ static int mmal_setup_components(struct
- 
- 	if (!ret
- 	    && camera_port ==
--	    &dev->component[MMAL_COMPONENT_CAMERA]->
--	    output[MMAL_CAMERA_PORT_VIDEO]) {
-+	    &dev->component[COMP_CAMERA]->
-+	    output[CAM_PORT_VIDEO]) {
- 		bool overlay_enabled =
--		    !!dev->component[MMAL_COMPONENT_PREVIEW]->enabled;
-+		    !!dev->component[COMP_PREVIEW]->enabled;
- 		struct vchiq_mmal_port *preview_port =
--		    &dev->component[MMAL_COMPONENT_CAMERA]->
--		    output[MMAL_CAMERA_PORT_PREVIEW];
-+		    &dev->component[COMP_CAMERA]->output[CAM_PORT_PREVIEW];
- 		/* Preview and encode ports need to match on resolution */
- 		if (overlay_enabled) {
- 			/* Need to disable the overlay before we can update
-@@ -1167,7 +1166,7 @@ static int mmal_setup_components(struct
- 			ret = vchiq_mmal_port_connect_tunnel(
- 				dev->instance,
- 				preview_port,
--				&dev->component[MMAL_COMPONENT_PREVIEW]->input[0]);
-+				&dev->component[COMP_PREVIEW]->input[0]);
- 			if (!ret)
- 				ret = vchiq_mmal_port_enable(dev->instance,
- 							     preview_port,
-@@ -1221,11 +1220,11 @@ static int mmal_setup_components(struct
- 				port->format.encoding_variant = 0;
- 				/* Set any encoding specific parameters */
- 				switch (mfmt->mmal_component) {
--				case MMAL_COMPONENT_VIDEO_ENCODE:
-+				case COMP_VIDEO_ENCODE:
- 					port->format.bitrate =
- 					    dev->capture.encode_bitrate;
- 					break;
--				case MMAL_COMPONENT_IMAGE_ENCODE:
-+				case COMP_IMAGE_ENCODE:
- 					/* Could set EXIF parameters here */
- 					break;
- 				default:
-@@ -1597,12 +1596,12 @@ static int __init mmal_init(struct bm283
- 
- 	/* get the camera component ready */
- 	ret = vchiq_mmal_component_init(dev->instance, "ril.camera",
--					&dev->component[MMAL_COMPONENT_CAMERA]);
-+					&dev->component[COMP_CAMERA]);
- 	if (ret < 0)
- 		goto unreg_mmal;
- 
--	camera = dev->component[MMAL_COMPONENT_CAMERA];
--	if (camera->outputs <  MMAL_CAMERA_PORT_COUNT) {
-+	camera = dev->component[COMP_CAMERA];
-+	if (camera->outputs <  CAM_PORT_COUNT) {
- 		ret = -EINVAL;
- 		goto unreg_camera;
- 	}
-@@ -1621,7 +1620,7 @@ static int __init mmal_init(struct bm283
- 	dev->rgb_bgr_swapped = true;
- 	param_size = sizeof(supported_encodings);
- 	ret = vchiq_mmal_port_parameter_get(dev->instance,
--					    &camera->output[MMAL_CAMERA_PORT_CAPTURE],
-+					    &camera->output[CAM_PORT_CAPTURE],
- 					    MMAL_PARAMETER_SUPPORTED_ENCODINGS,
- 					    &supported_encodings,
- 					    &param_size);
-@@ -1642,7 +1641,7 @@ static int __init mmal_init(struct bm283
- 			}
- 		}
- 	}
--	format = &camera->output[MMAL_CAMERA_PORT_PREVIEW].format;
-+	format = &camera->output[CAM_PORT_PREVIEW].format;
- 
- 	format->encoding = MMAL_ENCODING_OPAQUE;
- 	format->encoding_variant = MMAL_ENCODING_I420;
-@@ -1656,7 +1655,7 @@ static int __init mmal_init(struct bm283
- 	format->es->video.frame_rate.num = 0; /* Rely on fps_range */
- 	format->es->video.frame_rate.den = 1;
- 
--	format = &camera->output[MMAL_CAMERA_PORT_VIDEO].format;
-+	format = &camera->output[CAM_PORT_VIDEO].format;
- 
- 	format->encoding = MMAL_ENCODING_OPAQUE;
- 	format->encoding_variant = MMAL_ENCODING_I420;
-@@ -1670,7 +1669,7 @@ static int __init mmal_init(struct bm283
- 	format->es->video.frame_rate.num = 0; /* Rely on fps_range */
- 	format->es->video.frame_rate.den = 1;
- 
--	format = &camera->output[MMAL_CAMERA_PORT_CAPTURE].format;
-+	format = &camera->output[CAM_PORT_CAPTURE].format;
- 
- 	format->encoding = MMAL_ENCODING_OPAQUE;
- 
-@@ -1694,28 +1693,28 @@ static int __init mmal_init(struct bm283
- 	/* get the preview component ready */
- 	ret = vchiq_mmal_component_init(
- 			dev->instance, "ril.video_render",
--			&dev->component[MMAL_COMPONENT_PREVIEW]);
-+			&dev->component[COMP_PREVIEW]);
- 	if (ret < 0)
- 		goto unreg_camera;
- 
--	if (dev->component[MMAL_COMPONENT_PREVIEW]->inputs < 1) {
-+	if (dev->component[COMP_PREVIEW]->inputs < 1) {
- 		ret = -EINVAL;
- 		pr_debug("too few input ports %d needed %d\n",
--			 dev->component[MMAL_COMPONENT_PREVIEW]->inputs, 1);
-+			 dev->component[COMP_PREVIEW]->inputs, 1);
- 		goto unreg_preview;
- 	}
- 
- 	/* get the image encoder component ready */
- 	ret = vchiq_mmal_component_init(
- 		dev->instance, "ril.image_encode",
--		&dev->component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+		&dev->component[COMP_IMAGE_ENCODE]);
- 	if (ret < 0)
- 		goto unreg_preview;
- 
--	if (dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs < 1) {
-+	if (dev->component[COMP_IMAGE_ENCODE]->inputs < 1) {
- 		ret = -EINVAL;
- 		v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n",
--			 dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs,
-+			 dev->component[COMP_IMAGE_ENCODE]->inputs,
- 			 1);
- 		goto unreg_image_encoder;
- 	}
-@@ -1723,21 +1722,21 @@ static int __init mmal_init(struct bm283
- 	/* get the video encoder component ready */
- 	ret = vchiq_mmal_component_init(dev->instance, "ril.video_encode",
- 					&dev->
--					component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+					component[COMP_VIDEO_ENCODE]);
- 	if (ret < 0)
- 		goto unreg_image_encoder;
- 
--	if (dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs < 1) {
-+	if (dev->component[COMP_VIDEO_ENCODE]->inputs < 1) {
- 		ret = -EINVAL;
- 		v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n",
--			 dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs,
-+			 dev->component[COMP_VIDEO_ENCODE]->inputs,
- 			 1);
- 		goto unreg_vid_encoder;
- 	}
- 
- 	{
- 		struct vchiq_mmal_port *encoder_port =
--			&dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+			&dev->component[COMP_VIDEO_ENCODE]->output[0];
- 		encoder_port->format.encoding = MMAL_ENCODING_H264;
- 		ret = vchiq_mmal_port_set_format(dev->instance,
- 						 encoder_port);
-@@ -1748,12 +1747,12 @@ static int __init mmal_init(struct bm283
- 
- 		vchiq_mmal_port_parameter_set(
- 			dev->instance,
--			&dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control,
-+			&dev->component[COMP_VIDEO_ENCODE]->control,
- 			MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT,
- 			&enable, sizeof(enable));
- 
- 		vchiq_mmal_port_parameter_set(dev->instance,
--					      &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control,
-+					      &dev->component[COMP_VIDEO_ENCODE]->control,
- 					      MMAL_PARAMETER_MINIMISE_FRAGMENTATION,
- 					      &enable,
- 					      sizeof(enable));
-@@ -1768,23 +1767,23 @@ unreg_vid_encoder:
- 	pr_err("Cleanup: Destroy video encoder\n");
- 	vchiq_mmal_component_finalise(
- 		dev->instance,
--		dev->component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+		dev->component[COMP_VIDEO_ENCODE]);
- 
- unreg_image_encoder:
- 	pr_err("Cleanup: Destroy image encoder\n");
- 	vchiq_mmal_component_finalise(
- 		dev->instance,
--		dev->component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+		dev->component[COMP_IMAGE_ENCODE]);
- 
- unreg_preview:
- 	pr_err("Cleanup: Destroy video render\n");
- 	vchiq_mmal_component_finalise(dev->instance,
--				      dev->component[MMAL_COMPONENT_PREVIEW]);
-+				      dev->component[COMP_PREVIEW]);
- 
- unreg_camera:
- 	pr_err("Cleanup: Destroy camera\n");
- 	vchiq_mmal_component_finalise(dev->instance,
--				      dev->component[MMAL_COMPONENT_CAMERA]);
-+				      dev->component[COMP_CAMERA]);
- 
- unreg_mmal:
- 	vchiq_mmal_finalise(dev->instance);
-@@ -1840,21 +1839,21 @@ static void bcm2835_cleanup_instance(str
- 					     dev->capture.encode_component);
- 	}
- 	vchiq_mmal_component_disable(dev->instance,
--				     dev->component[MMAL_COMPONENT_CAMERA]);
-+				     dev->component[COMP_CAMERA]);
- 
- 	vchiq_mmal_component_finalise(dev->instance,
- 				      dev->
--				      component[MMAL_COMPONENT_VIDEO_ENCODE]);
-+				      component[COMP_VIDEO_ENCODE]);
- 
- 	vchiq_mmal_component_finalise(dev->instance,
- 				      dev->
--				      component[MMAL_COMPONENT_IMAGE_ENCODE]);
-+				      component[COMP_IMAGE_ENCODE]);
- 
- 	vchiq_mmal_component_finalise(dev->instance,
--				      dev->component[MMAL_COMPONENT_PREVIEW]);
-+				      dev->component[COMP_PREVIEW]);
- 
- 	vchiq_mmal_component_finalise(dev->instance,
--				      dev->component[MMAL_COMPONENT_CAMERA]);
-+				      dev->component[COMP_CAMERA]);
- 
- 	v4l2_ctrl_handler_free(&dev->ctrl_handler);
- 
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-@@ -19,18 +19,18 @@
- #define V4L2_CTRL_COUNT 29 /* number of v4l controls */
- 
- enum {
--	MMAL_COMPONENT_CAMERA = 0,
--	MMAL_COMPONENT_PREVIEW,
--	MMAL_COMPONENT_IMAGE_ENCODE,
--	MMAL_COMPONENT_VIDEO_ENCODE,
--	MMAL_COMPONENT_COUNT
-+	COMP_CAMERA = 0,
-+	COMP_PREVIEW,
-+	COMP_IMAGE_ENCODE,
-+	COMP_VIDEO_ENCODE,
-+	COMP_COUNT
- };
- 
- enum {
--	MMAL_CAMERA_PORT_PREVIEW = 0,
--	MMAL_CAMERA_PORT_VIDEO,
--	MMAL_CAMERA_PORT_CAPTURE,
--	MMAL_CAMERA_PORT_COUNT
-+	CAM_PORT_PREVIEW = 0,
-+	CAM_PORT_VIDEO,
-+	CAM_PORT_CAPTURE,
-+	CAM_PORT_COUNT
- };
- 
- #define PREVIEW_LAYER      2
-@@ -64,7 +64,7 @@ struct bm2835_mmal_dev {
- 
- 	/* allocated mmal instance and components */
- 	struct vchiq_mmal_instance   *instance;
--	struct vchiq_mmal_component  *component[MMAL_COMPONENT_COUNT];
-+	struct vchiq_mmal_component  *component[COMP_COUNT];
- 	int camera_use_count;
- 
- 	struct v4l2_window overlay;
---- a/drivers/staging/vc04_services/bcm2835-camera/controls.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c
-@@ -179,7 +179,7 @@ static int ctrl_set_rational(struct bm28
- 	struct mmal_parameter_rational rational_value;
- 	struct vchiq_mmal_port *control;
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	rational_value.num = ctrl->val;
- 	rational_value.den = 100;
-@@ -197,7 +197,7 @@ static int ctrl_set_value(struct bm2835_
- 	u32 u32_value;
- 	struct vchiq_mmal_port *control;
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	u32_value = ctrl->val;
- 
-@@ -222,7 +222,7 @@ static int ctrl_set_iso(struct bm2835_mm
- 		dev->manual_iso_enabled =
- 				(ctrl->val == V4L2_ISO_SENSITIVITY_MANUAL);
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	if (dev->manual_iso_enabled)
- 		u32_value = dev->iso;
-@@ -241,7 +241,7 @@ static int ctrl_set_value_ev(struct bm28
- 	s32 s32_value;
- 	struct vchiq_mmal_port *control;
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	s32_value = (ctrl->val - 12) * 2;	/* Convert from index to 1/6ths */
- 
-@@ -258,7 +258,7 @@ static int ctrl_set_rotate(struct bm2835
- 	u32 u32_value;
- 	struct vchiq_mmal_component *camera;
- 
--	camera = dev->component[MMAL_COMPONENT_CAMERA];
-+	camera = dev->component[COMP_CAMERA];
- 
- 	u32_value = ((ctrl->val % 360) / 90) * 90;
- 
-@@ -294,7 +294,7 @@ static int ctrl_set_flip(struct bm2835_m
- 	else
- 		dev->vflip = ctrl->val;
- 
--	camera = dev->component[MMAL_COMPONENT_CAMERA];
-+	camera = dev->component[COMP_CAMERA];
- 
- 	if (dev->hflip && dev->vflip)
- 		u32_value = MMAL_PARAM_MIRROR_BOTH;
-@@ -333,7 +333,7 @@ static int ctrl_set_exposure(struct bm28
- 	struct vchiq_mmal_port *control;
- 	int ret = 0;
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	if (mmal_ctrl->mmal_id == MMAL_PARAMETER_SHUTTER_SPEED)	{
- 		/* V4L2 is in 100usec increments.
-@@ -408,7 +408,7 @@ static int ctrl_set_metering_mode(struct
- 		struct vchiq_mmal_port *control;
- 		u32 u32_value = dev->metering_mode;
- 
--		control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+		control = &dev->component[COMP_CAMERA]->control;
- 
- 		return vchiq_mmal_port_parameter_set(dev->instance, control,
- 					     mmal_ctrl->mmal_id,
-@@ -424,7 +424,7 @@ static int ctrl_set_flicker_avoidance(st
- 	u32 u32_value;
- 	struct vchiq_mmal_port *control;
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	switch (ctrl->val) {
- 	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
-@@ -453,7 +453,7 @@ static int ctrl_set_awb_mode(struct bm28
- 	u32 u32_value;
- 	struct vchiq_mmal_port *control;
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	switch (ctrl->val) {
- 	case V4L2_WHITE_BALANCE_MANUAL:
-@@ -509,7 +509,7 @@ static int ctrl_set_awb_gains(struct bm2
- 	struct vchiq_mmal_port *control;
- 	struct mmal_parameter_awbgains gains;
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	if (ctrl->id == V4L2_CID_RED_BALANCE)
- 		dev->red_gain = ctrl->val;
-@@ -557,7 +557,7 @@ static int ctrl_set_image_effect(struct
- 					v4l2_to_mmal_effects_values[i].v;
- 			}
- 
--			control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+			control = &dev->component[COMP_CAMERA]->control;
- 
- 			ret = vchiq_mmal_port_parameter_set(
- 					dev->instance, control,
-@@ -590,7 +590,7 @@ static int ctrl_set_colfx(struct bm2835_
- 	int ret = -EINVAL;
- 	struct vchiq_mmal_port *control;
- 
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	dev->colourfx.enable = (ctrl->val & 0xff00) >> 8;
- 	dev->colourfx.enable = ctrl->val & 0xff;
-@@ -616,7 +616,7 @@ static int ctrl_set_bitrate(struct bm283
- 
- 	dev->capture.encode_bitrate = ctrl->val;
- 
--	encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+	encoder_out = &dev->component[COMP_VIDEO_ENCODE]->output[0];
- 
- 	ret = vchiq_mmal_port_parameter_set(dev->instance, encoder_out,
- 					    mmal_ctrl->mmal_id,
-@@ -632,7 +632,7 @@ static int ctrl_set_bitrate_mode(struct
- 	u32 bitrate_mode;
- 	struct vchiq_mmal_port *encoder_out;
- 
--	encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+	encoder_out = &dev->component[COMP_VIDEO_ENCODE]->output[0];
- 
- 	dev->capture.encode_bitrate_mode = ctrl->val;
- 	switch (ctrl->val) {
-@@ -659,7 +659,7 @@ static int ctrl_set_image_encode_output(
- 	u32 u32_value;
- 	struct vchiq_mmal_port *jpeg_out;
- 
--	jpeg_out = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0];
-+	jpeg_out = &dev->component[COMP_IMAGE_ENCODE]->output[0];
- 
- 	u32_value = ctrl->val;
- 
-@@ -675,7 +675,7 @@ static int ctrl_set_video_encode_param_o
- 	u32 u32_value;
- 	struct vchiq_mmal_port *vid_enc_ctl;
- 
--	vid_enc_ctl = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0];
-+	vid_enc_ctl = &dev->component[COMP_VIDEO_ENCODE]->output[0];
- 
- 	u32_value = ctrl->val;
- 
-@@ -788,7 +788,7 @@ static int ctrl_set_video_encode_profile
- 		}
- 
- 		ret = vchiq_mmal_port_parameter_set(dev->instance,
--						    &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0],
-+						    &dev->component[COMP_VIDEO_ENCODE]->output[0],
- 			mmal_ctrl->mmal_id,
- 			&param, sizeof(param));
- 	}
-@@ -806,7 +806,7 @@ static int ctrl_set_scene_mode(struct bm
- 	v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev,
- 		 "scene mode selected %d, was %d\n", ctrl->val,
- 		 dev->scene_mode);
--	control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
-+	control = &dev->component[COMP_CAMERA]->control;
- 
- 	if (ctrl->val == dev->scene_mode)
- 		return 0;
-@@ -1224,18 +1224,15 @@ int set_framerate_params(struct bm2835_m
- 		 fps_range.fps_high.den);
- 
- 	ret = vchiq_mmal_port_parameter_set(dev->instance,
--					    &dev->component[MMAL_COMPONENT_CAMERA]->
--					    output[MMAL_CAMERA_PORT_PREVIEW],
-+					    &dev->component[COMP_CAMERA]->output[CAM_PORT_PREVIEW],
- 					    MMAL_PARAMETER_FPS_RANGE,
- 					    &fps_range, sizeof(fps_range));
- 	ret += vchiq_mmal_port_parameter_set(dev->instance,
--					     &dev->component[MMAL_COMPONENT_CAMERA]->
--					     output[MMAL_CAMERA_PORT_VIDEO],
-+					     &dev->component[COMP_CAMERA]->output[CAM_PORT_VIDEO],
- 					     MMAL_PARAMETER_FPS_RANGE,
- 					     &fps_range, sizeof(fps_range));
- 	ret += vchiq_mmal_port_parameter_set(dev->instance,
--					     &dev->component[MMAL_COMPONENT_CAMERA]->
--					     output[MMAL_CAMERA_PORT_CAPTURE],
-+					     &dev->component[COMP_CAMERA]->output[CAM_PORT_CAPTURE],
- 					     MMAL_PARAMETER_FPS_RANGE,
- 					     &fps_range, sizeof(fps_range));
- 	if (ret)
diff --git a/target/linux/brcm2708/patches-4.14/950-0398-staging-bcm2835-camera-Fix-multiple-line-dereference.patch b/target/linux/brcm2708/patches-4.14/950-0398-staging-bcm2835-camera-Fix-multiple-line-dereference.patch
deleted file mode 100644
index 196d8581f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0398-staging-bcm2835-camera-Fix-multiple-line-dereference.patch
+++ /dev/null
@@ -1,133 +0,0 @@
-From 792e9e31a64c32d70b79afaa24d9ad3e96a39ff6 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 15:28:07 +0000
-Subject: [PATCH 398/454] staging: bcm2835-camera: Fix multiple line
- dereference errors
-
-Fix checkpatch errors "Avoid multiple line dereference"
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 41 +++++++------------
- 1 file changed, 14 insertions(+), 27 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -320,8 +320,7 @@ static void buffer_cleanup(struct vb2_bu
- static inline bool is_capturing(struct bm2835_mmal_dev *dev)
- {
- 	return dev->capture.camera_port ==
--	    &dev->
--	    component[COMP_CAMERA]->output[CAM_PORT_CAPTURE];
-+	    &dev->component[COMP_CAMERA]->output[CAM_PORT_CAPTURE];
- }
- 
- static void buffer_cb(struct vchiq_mmal_instance *instance,
-@@ -804,8 +803,7 @@ static int vidioc_overlay(struct file *f
- 		return 0;	/* already in requested state */
- 
- 	src =
--	    &dev->component[COMP_CAMERA]->
--	    output[CAM_PORT_PREVIEW];
-+	    &dev->component[COMP_CAMERA]->output[CAM_PORT_PREVIEW];
- 
- 	if (!on) {
- 		/* disconnect preview ports and disable component */
-@@ -860,8 +858,7 @@ static int vidioc_g_fbuf(struct file *fi
- 	 */
- 	struct bm2835_mmal_dev *dev = video_drvdata(file);
- 	struct vchiq_mmal_port *preview_port =
--		&dev->component[COMP_CAMERA]->
--		output[CAM_PORT_PREVIEW];
-+		&dev->component[COMP_CAMERA]->output[CAM_PORT_PREVIEW];
- 
- 	a->capability = V4L2_FBUF_CAP_EXTERNOVERLAY |
- 			V4L2_FBUF_CAP_GLOBAL_ALPHA;
-@@ -1053,8 +1050,7 @@ static int mmal_setup_components(struct
- 					       dev->capture.camera_port, NULL);
- 		dev->capture.camera_port = NULL;
- 		ret = vchiq_mmal_component_disable(dev->instance,
--						   dev->capture.
--						   encode_component);
-+						   dev->capture.encode_component);
- 		if (ret)
- 			v4l2_err(&dev->v4l2_dev,
- 				 "Failed to disable encode component %d\n",
-@@ -1069,26 +1065,22 @@ static int mmal_setup_components(struct
- 		if (f->fmt.pix.width <= max_video_width
- 		    && f->fmt.pix.height <= max_video_height)
- 			camera_port = port =
--			    &dev->component[COMP_CAMERA]->
--			    output[CAM_PORT_VIDEO];
-+			    &dev->component[COMP_CAMERA]->output[CAM_PORT_VIDEO];
- 		else
- 			camera_port = port =
--			    &dev->component[COMP_CAMERA]->
--			    output[CAM_PORT_CAPTURE];
-+			    &dev->component[COMP_CAMERA]->output[CAM_PORT_CAPTURE];
- 		break;
- 	case COMP_IMAGE_ENCODE:
- 		encode_component = dev->component[COMP_IMAGE_ENCODE];
- 		port = &dev->component[COMP_IMAGE_ENCODE]->output[0];
- 		camera_port =
--		    &dev->component[COMP_CAMERA]->
--		    output[CAM_PORT_CAPTURE];
-+		    &dev->component[COMP_CAMERA]->output[CAM_PORT_CAPTURE];
- 		break;
- 	case COMP_VIDEO_ENCODE:
- 		encode_component = dev->component[COMP_VIDEO_ENCODE];
- 		port = &dev->component[COMP_VIDEO_ENCODE]->output[0];
- 		camera_port =
--		    &dev->component[COMP_CAMERA]->
--		    output[CAM_PORT_VIDEO];
-+		    &dev->component[COMP_CAMERA]->output[CAM_PORT_VIDEO];
- 		break;
- 	default:
- 		break;
-@@ -1130,8 +1122,7 @@ static int mmal_setup_components(struct
- 
- 	if (!ret
- 	    && camera_port ==
--	    &dev->component[COMP_CAMERA]->
--	    output[CAM_PORT_VIDEO]) {
-+	    &dev->component[COMP_CAMERA]->output[CAM_PORT_VIDEO]) {
- 		bool overlay_enabled =
- 		    !!dev->component[COMP_PREVIEW]->enabled;
- 		struct vchiq_mmal_port *preview_port =
-@@ -1268,9 +1259,8 @@ static int mmal_setup_components(struct
- 						 port->current_buffer.size);
- 					port->current_buffer.size =
- 					    (f->fmt.pix.sizeimage <
--					     (100 << 10))
--					    ? (100 << 10)
--					    : f->fmt.pix.sizeimage;
-+					     (100 << 10)) ?
-+					    (100 << 10) : f->fmt.pix.sizeimage;
- 				}
- 				v4l2_dbg(1, bcm2835_v4l2_debug,
- 					 &dev->v4l2_dev,
-@@ -1721,8 +1711,7 @@ static int __init mmal_init(struct bm283
- 
- 	/* get the video encoder component ready */
- 	ret = vchiq_mmal_component_init(dev->instance, "ril.video_encode",
--					&dev->
--					component[COMP_VIDEO_ENCODE]);
-+					&dev->component[COMP_VIDEO_ENCODE]);
- 	if (ret < 0)
- 		goto unreg_image_encoder;
- 
-@@ -1842,12 +1831,10 @@ static void bcm2835_cleanup_instance(str
- 				     dev->component[COMP_CAMERA]);
- 
- 	vchiq_mmal_component_finalise(dev->instance,
--				      dev->
--				      component[COMP_VIDEO_ENCODE]);
-+				      dev->component[COMP_VIDEO_ENCODE]);
- 
- 	vchiq_mmal_component_finalise(dev->instance,
--				      dev->
--				      component[COMP_IMAGE_ENCODE]);
-+				      dev->component[COMP_IMAGE_ENCODE]);
- 
- 	vchiq_mmal_component_finalise(dev->instance,
- 				      dev->component[COMP_PREVIEW]);
diff --git a/target/linux/brcm2708/patches-4.14/950-0399-staging-bcm2835-camera-Fix-brace-style-issues.patch b/target/linux/brcm2708/patches-4.14/950-0399-staging-bcm2835-camera-Fix-brace-style-issues.patch
deleted file mode 100644
index bca154cbf..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0399-staging-bcm2835-camera-Fix-brace-style-issues.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From 6e545dce9e62d137d6d63eeed0ec35f865dcb823 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 15:37:11 +0000
-Subject: [PATCH 399/454] staging: bcm2835-camera: Fix brace style issues.
-
-Fix mismatched or missing brace issues flagged by checkpatch.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c | 3 ++-
- drivers/staging/vc04_services/bcm2835-camera/controls.c       | 3 ++-
- drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c     | 3 ++-
- 3 files changed, 6 insertions(+), 3 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -573,10 +573,11 @@ static int start_streaming(struct vb2_qu
- 
- 		/* Flag to indicate just to rely on kernel timestamps */
- 		dev->capture.vc_start_timestamp = -1;
--	} else
-+	} else {
- 		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
- 			 "Start time %lld size %d\n",
- 			 dev->capture.vc_start_timestamp, parameter_size);
-+	}
- 
- 	dev->capture.last_timestamp = 0;
- 
---- a/drivers/staging/vc04_services/bcm2835-camera/controls.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c
-@@ -413,8 +413,9 @@ static int ctrl_set_metering_mode(struct
- 		return vchiq_mmal_port_parameter_set(dev->instance, control,
- 					     mmal_ctrl->mmal_id,
- 					     &u32_value, sizeof(u32_value));
--	} else
-+	} else {
- 		return 0;
-+	}
- }
- 
- static int ctrl_set_flicker_avoidance(struct bm2835_mmal_dev *dev,
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -1334,9 +1334,10 @@ static int port_parameter_get(struct vch
- 		memcpy(value, &rmsg->u.port_parameter_get_reply.value,
- 		       *value_size);
- 		*value_size = rmsg->u.port_parameter_get_reply.size;
--	} else
-+	} else {
- 		memcpy(value, &rmsg->u.port_parameter_get_reply.value,
- 		       rmsg->u.port_parameter_get_reply.size);
-+	}
- 
- 	pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", __func__,
- 		 ret, port->component->handle, port->handle, parameter_id);
diff --git a/target/linux/brcm2708/patches-4.14/950-0400-staging-bcm2835-camera-Fix-missing-lines-between-ite.patch b/target/linux/brcm2708/patches-4.14/950-0400-staging-bcm2835-camera-Fix-missing-lines-between-ite.patch
deleted file mode 100644
index 55b301ee6..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0400-staging-bcm2835-camera-Fix-missing-lines-between-ite.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 52499594ce8b48c434bed29062c8bbc15b96cc96 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 15:39:26 +0000
-Subject: [PATCH 400/454] staging: bcm2835-camera: Fix missing lines between
- items
-
-Fix checkpatch errors for missing blank lines after variable
-or structure declarations.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../staging/vc04_services/bcm2835-camera/bcm2835-camera.h   | 1 +
- drivers/staging/vc04_services/bcm2835-camera/controls.c     | 2 ++
- drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c   | 6 ++++--
- 3 files changed, 7 insertions(+), 2 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-@@ -133,6 +133,7 @@ int set_framerate_params(struct bm2835_m
- 		(pix_fmt)->pixelformat, (pix_fmt)->bytesperline,	\
- 		(pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \
- }
-+
- #define v4l2_dump_win_format(level, debug, dev, win_fmt, desc)	\
- {	\
- 	v4l2_dbg(level, debug, dev,	\
---- a/drivers/staging/vc04_services/bcm2835-camera/controls.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c
-@@ -56,6 +56,7 @@ static const s64 ev_bias_qmenu[] = {
- static const s64 iso_qmenu[] = {
- 	0, 100000, 200000, 400000, 800000,
- };
-+
- static const uint32_t iso_values[] = {
- 	0, 100, 200, 400, 800,
- };
-@@ -1272,6 +1273,7 @@ int bm2835_mmal_init_controls(struct bm2
- 				 * mismatches.
- 				 */
- 				int i;
-+
- 				mask = 1 << V4L2_SCENE_MODE_NONE;
- 				for (i = 0;
- 				     i < ARRAY_SIZE(scene_configs);
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -1886,10 +1886,12 @@ int vchiq_mmal_finalise(struct vchiq_mma
- 
- int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance)
- {
--	int status;
--	struct vchiq_mmal_instance *instance;
- 	static VCHI_CONNECTION_T *vchi_connection;
-+
- 	static VCHI_INSTANCE_T vchi_instance;
-+
-+	struct vchiq_mmal_instance *instance;
-+	int status;
- 	SERVICE_CREATION_T params = {
- 		.version		= VCHI_VERSION_EX(VC_MMAL_VER, VC_MMAL_MIN_VER),
- 		.service_id		= VC_MMAL_SERVER_NAME,
diff --git a/target/linux/brcm2708/patches-4.14/950-0401-staging-bcm2835-camera-Fix-logical-continuation-spli.patch b/target/linux/brcm2708/patches-4.14/950-0401-staging-bcm2835-camera-Fix-logical-continuation-spli.patch
deleted file mode 100644
index 4f329bf4f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0401-staging-bcm2835-camera-Fix-logical-continuation-spli.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 7038689f4826a41b25f30ec416ab0b7ba0a4758c Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 15:48:54 +0000
-Subject: [PATCH 401/454] staging: bcm2835-camera: Fix logical continuation
- splits
-
-Fix checkpatch errors for "Logical continuations should be
-on the previous line".
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../vc04_services/bcm2835-camera/bcm2835-camera.c    | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -549,8 +549,8 @@ static int start_streaming(struct vb2_qu
- 		msleep(300);
- 
- 	/* enable the connection from camera to encoder (if applicable) */
--	if (dev->capture.camera_port != dev->capture.port
--	    && dev->capture.camera_port) {
-+	if (dev->capture.camera_port != dev->capture.port &&
-+	    dev->capture.camera_port) {
- 		ret = vchiq_mmal_port_enable(dev->instance,
- 					     dev->capture.camera_port, NULL);
- 		if (ret) {
-@@ -1063,8 +1063,8 @@ static int mmal_setup_components(struct
- 	switch (mfmt->mmal_component) {
- 	case COMP_CAMERA:
- 		/* Make a further decision on port based on resolution */
--		if (f->fmt.pix.width <= max_video_width
--		    && f->fmt.pix.height <= max_video_height)
-+		if (f->fmt.pix.width <= max_video_width &&
-+		    f->fmt.pix.height <= max_video_height)
- 			camera_port = port =
- 			    &dev->component[COMP_CAMERA]->output[CAM_PORT_VIDEO];
- 		else
-@@ -1121,8 +1121,8 @@ static int mmal_setup_components(struct
- 
- 	ret = vchiq_mmal_port_set_format(dev->instance, camera_port);
- 
--	if (!ret
--	    && camera_port ==
-+	if (!ret &&
-+	    camera_port ==
- 	    &dev->component[COMP_CAMERA]->output[CAM_PORT_VIDEO]) {
- 		bool overlay_enabled =
- 		    !!dev->component[COMP_PREVIEW]->enabled;
diff --git a/target/linux/brcm2708/patches-4.14/950-0402-staging-bcm2835-camera-Fix-open-parenthesis-alignmen.patch b/target/linux/brcm2708/patches-4.14/950-0402-staging-bcm2835-camera-Fix-open-parenthesis-alignmen.patch
deleted file mode 100644
index 3e5fc2b40..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0402-staging-bcm2835-camera-Fix-open-parenthesis-alignmen.patch
+++ /dev/null
@@ -1,137 +0,0 @@
-From ebbe1b1aad0b52d27beed714cb075e1c83af651f Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 15:53:59 +0000
-Subject: [PATCH 402/454] staging: bcm2835-camera: Fix open parenthesis
- alignment
-
-Fix checkpatch "Alignment should match open parenthesis"
-errors.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 12 ++++-----
- .../vc04_services/bcm2835-camera/controls.c   | 25 ++++++++++++-------
- .../vc04_services/bcm2835-camera/mmal-vchiq.c |  2 +-
- .../vc04_services/bcm2835-camera/mmal-vchiq.h |  6 ++---
- 4 files changed, 25 insertions(+), 20 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -419,8 +419,7 @@ static void buffer_cb(struct vchiq_mmal_
- 		buf->vb.flags |= V4L2_BUF_FLAG_KEYFRAME;
- 
- 	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--		 "Buffer has ts %llu",
--		 dev->capture.last_timestamp);
-+		 "Buffer has ts %llu", dev->capture.last_timestamp);
- 	vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
- 
- 	if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS &&
-@@ -589,8 +588,8 @@ static int start_streaming(struct vb2_qu
- 	    vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb);
- 	if (ret) {
- 		v4l2_err(&dev->v4l2_dev,
--			"Failed to enable capture port - error %d. Disabling camera port again\n",
--			ret);
-+			 "Failed to enable capture port - error %d. Disabling camera port again\n",
-+			 ret);
- 
- 		vchiq_mmal_port_disable(dev->instance,
- 					dev->capture.camera_port);
-@@ -998,8 +997,7 @@ static int vidioc_try_fmt_vid_cap(struct
- 		f->fmt.pix.bytesperline =
- 			(f->fmt.pix.bytesperline + align_mask) & ~align_mask;
- 		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--			 "Not removing padding, so bytes/line = %d, "
--			 "(align_mask %d)\n",
-+			 "Not removing padding, so bytes/line = %d, (align_mask %d)\n",
- 			 f->fmt.pix.bytesperline, align_mask);
- 	}
- 
-@@ -1345,7 +1343,7 @@ static int vidioc_s_fmt_vid_cap(struct f
- }
- 
- static int vidioc_enum_framesizes(struct file *file, void *fh,
--			   struct v4l2_frmsizeenum *fsize)
-+				  struct v4l2_frmsizeenum *fsize)
- {
- 	struct bm2835_mmal_dev *dev = video_drvdata(file);
- 	static const struct v4l2_frmsize_stepwise sizes = {
---- a/drivers/staging/vc04_services/bcm2835-camera/controls.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c
-@@ -1257,9 +1257,12 @@ int bm2835_mmal_init_controls(struct bm2
- 
- 		switch (ctrl->type) {
- 		case MMAL_CONTROL_TYPE_STD:
--			dev->ctrls[c] = v4l2_ctrl_new_std(hdl,
--				&bm2835_mmal_ctrl_ops, ctrl->id,
--				ctrl->min, ctrl->max, ctrl->step, ctrl->def);
-+			dev->ctrls[c] =
-+				v4l2_ctrl_new_std(hdl,
-+						  &bm2835_mmal_ctrl_ops,
-+						  ctrl->id, ctrl->min,
-+						  ctrl->max, ctrl->step,
-+						  ctrl->def);
- 			break;
- 
- 		case MMAL_CONTROL_TYPE_STD_MENU:
-@@ -1283,16 +1286,20 @@ int bm2835_mmal_init_controls(struct bm2
- 				mask = ~mask;
- 			}
- 
--			dev->ctrls[c] = v4l2_ctrl_new_std_menu(hdl,
--			&bm2835_mmal_ctrl_ops, ctrl->id,
--			ctrl->max, mask, ctrl->def);
-+			dev->ctrls[c] =
-+				v4l2_ctrl_new_std_menu(hdl,
-+						       &bm2835_mmal_ctrl_ops,
-+						       ctrl->id, ctrl->max,
-+						       mask, ctrl->def);
- 			break;
- 		}
- 
- 		case MMAL_CONTROL_TYPE_INT_MENU:
--			dev->ctrls[c] = v4l2_ctrl_new_int_menu(hdl,
--				&bm2835_mmal_ctrl_ops, ctrl->id,
--				ctrl->max, ctrl->def, ctrl->imenu);
-+			dev->ctrls[c] =
-+				v4l2_ctrl_new_int_menu(hdl,
-+						       &bm2835_mmal_ctrl_ops,
-+						       ctrl->id, ctrl->max,
-+						       ctrl->def, ctrl->imenu);
- 			break;
- 
- 		case MMAL_CONTROL_TYPE_CLUSTER:
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -717,7 +717,7 @@ static int send_synchronous_mmal_msg(str
- 	if (payload_len >
- 	    (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))) {
- 		pr_err("payload length %d exceeds max:%d\n", payload_len,
--		      (int)(MMAL_MSG_MAX_SIZE -
-+		       (int)(MMAL_MSG_MAX_SIZE -
- 			    sizeof(struct mmal_msg_header)));
- 		return -EINVAL;
- 	}
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-@@ -131,7 +131,7 @@ int vchiq_mmal_port_enable(
-  * disable a port will dequeue any pending buffers
-  */
- int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance,
--			   struct vchiq_mmal_port *port);
-+			    struct vchiq_mmal_port *port);
- 
- int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance,
- 				  struct vchiq_mmal_port *port,
-@@ -149,8 +149,8 @@ int vchiq_mmal_port_set_format(struct vc
- 			       struct vchiq_mmal_port *port);
- 
- int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance,
--			    struct vchiq_mmal_port *src,
--			    struct vchiq_mmal_port *dst);
-+				   struct vchiq_mmal_port *src,
-+				   struct vchiq_mmal_port *dst);
- 
- int vchiq_mmal_version(struct vchiq_mmal_instance *instance,
- 		       u32 *major_out,
diff --git a/target/linux/brcm2708/patches-4.14/950-0403-staging-bcm2835-camera-Fix-typo.patch b/target/linux/brcm2708/patches-4.14/950-0403-staging-bcm2835-camera-Fix-typo.patch
deleted file mode 100644
index 2cb79b6fa..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0403-staging-bcm2835-camera-Fix-typo.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 75989383a7aca3fd571739c24f36f301ce40a1eb Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 21 Feb 2018 15:58:38 +0000
-Subject: [PATCH 403/454] staging: bcm2835-camera: Fix typo.
-
-Fix a typo flagged up by checkpatch.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-@@ -119,7 +119,7 @@ int vchiq_mmal_component_disable(
- /* enable a mmal port
-  *
-  * enables a port and if a buffer callback provided enque buffer
-- * headers as apropriate for the port.
-+ * headers as appropriate for the port.
-  */
- int vchiq_mmal_port_enable(
- 		struct vchiq_mmal_instance *instance,
diff --git a/target/linux/brcm2708/patches-4.14/950-0404-staging-bcm2835_camera-Ensure-all-buffers-are-return.patch b/target/linux/brcm2708/patches-4.14/950-0404-staging-bcm2835_camera-Ensure-all-buffers-are-return.patch
deleted file mode 100644
index b2d7b8608..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0404-staging-bcm2835_camera-Ensure-all-buffers-are-return.patch
+++ /dev/null
@@ -1,82 +0,0 @@
-From 13e015450812772f21c874dd310abe3379b87bb5 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 28 Jun 2018 15:57:25 +0100
-Subject: [PATCH 404/454] staging: bcm2835_camera: Ensure all buffers are
- returned on disable
-
-With the recent change to match MMAL and V4L2 buffers there
-is a need to wait for all MMAL buffers to be returned during
-stop_streaming.
-
-Fixes: 9384167 "staging: bcm2835-camera: Remove V4L2/MMAL buffer remapping"
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c              | 16 ++++++++++++++++
- .../vc04_services/bcm2835-camera/mmal-vchiq.c    |  4 ++++
- .../vc04_services/bcm2835-camera/mmal-vchiq.h    |  3 +++
- 3 files changed, 23 insertions(+)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -615,6 +615,7 @@ static void stop_streaming(struct vb2_qu
- 	int ret;
- 	unsigned long timeout;
- 	struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq);
-+	struct vchiq_mmal_port *port = dev->capture.port;
- 
- 	v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n",
- 		 __func__, dev);
-@@ -658,6 +659,21 @@ static void stop_streaming(struct vb2_qu
- 			 ret);
- 	}
- 
-+	/* wait for all buffers to be returned */
-+	while (atomic_read(&port->buffers_with_vpu)) {
-+		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+			 "%s: Waiting for buffers to be returned - %d outstanding\n",
-+			 __func__, atomic_read(&port->buffers_with_vpu));
-+		ret = wait_for_completion_timeout(&dev->capture.frame_cmplt,
-+						  HZ);
-+		if (ret <= 0) {
-+			v4l2_err(&dev->v4l2_dev, "%s: Timeout waiting for buffers to be returned - %d outstanding\n",
-+				 __func__,
-+				 atomic_read(&port->buffers_with_vpu));
-+			break;
-+		}
-+	}
-+
- 	if (disable_camera(dev) < 0)
- 		v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n");
- }
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -318,6 +318,8 @@ static void buffer_work_cb(struct work_s
- 	struct mmal_msg_context *msg_context =
- 		container_of(work, struct mmal_msg_context, u.bulk.work);
- 
-+	atomic_dec(&msg_context->u.bulk.port->buffers_with_vpu);
-+
- 	msg_context->u.bulk.port->buffer_cb(msg_context->u.bulk.instance,
- 					    msg_context->u.bulk.port,
- 					    msg_context->u.bulk.status,
-@@ -461,6 +463,8 @@ buffer_from_host(struct vchiq_mmal_insta
- 	INIT_WORK(&msg_context->u.bulk.buffer_to_host_work,
- 		  buffer_to_host_work_cb);
- 
-+	atomic_inc(&port->buffers_with_vpu);
-+
- 	/* prep the buffer from host message */
- 	memset(&m, 0xbc, sizeof(m));	/* just to make debug clearer */
- 
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.h
-@@ -75,6 +75,9 @@ struct vchiq_mmal_port {
- 	struct list_head buffers;
- 	/* lock to serialise adding and removing buffers from list */
- 	spinlock_t slock;
-+
-+	/* Count of buffers the VPU has yet to return */
-+	atomic_t buffers_with_vpu;
- 	/* callback on buffer completion */
- 	vchiq_mmal_buffer_cb buffer_cb;
- 	/* callback context */
diff --git a/target/linux/brcm2708/patches-4.14/950-0405-staging-mmal-vchiq-Remove-check-of-the-number-of-buf.patch b/target/linux/brcm2708/patches-4.14/950-0405-staging-mmal-vchiq-Remove-check-of-the-number-of-buf.patch
deleted file mode 100644
index e51626e08..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0405-staging-mmal-vchiq-Remove-check-of-the-number-of-buf.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 338d4e95632213c910335b0283ce52ce0643881d Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 4 Jul 2018 17:01:15 +0100
-Subject: [PATCH 405/454] staging: mmal-vchiq: Remove check of the number of
- buffers supplied
-
-Before 9384167 there was a need to ensure that there were sufficient
-buffers supplied from the user to cover those being sent to the VPU
-(always 1).
-With 9384167 the buffers are linked 1:1 between MMAL and V4L2,
-therefore there is no need for that check, and indeed it is wrong
-as there is no need to submit all the buffers before starting streaming.
-
-Fixes: 9384167 "staging: bcm2835-camera: Remove V4L2/MMAL buffer remapping"
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../staging/vc04_services/bcm2835-camera/mmal-vchiq.c  | 10 ----------
- 1 file changed, 10 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -1410,16 +1410,6 @@ static int port_enable(struct vchiq_mmal
- 	if (port->enabled)
- 		return 0;
- 
--	/* ensure there are enough buffers queued to cover the buffer headers */
--	if (port->buffer_cb) {
--		hdr_count = 0;
--		list_for_each(buf_head, &port->buffers) {
--			hdr_count++;
--		}
--		if (hdr_count < port->current_buffer.num)
--			return -ENOSPC;
--	}
--
- 	ret = port_action_port(instance, port,
- 			       MMAL_MSG_PORT_ACTION_TYPE_ENABLE);
- 	if (ret)
diff --git a/target/linux/brcm2708/patches-4.14/950-0406-staging-bcm2835-camera-Handle-empty-EOS-buffers-whil.patch b/target/linux/brcm2708/patches-4.14/950-0406-staging-bcm2835-camera-Handle-empty-EOS-buffers-whil.patch
deleted file mode 100644
index 72ce5e690..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0406-staging-bcm2835-camera-Handle-empty-EOS-buffers-whil.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 3905de52a7c815b6e2cf1915697ac5baaab34b85 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 5 Jul 2018 16:17:03 +0100
-Subject: [PATCH 406/454] staging: bcm2835-camera: Handle empty EOS buffers
- whilst streaming
-
-The change to mapping V4L2 to MMAL buffers 1:1 didn't handle
-the condition we get with raw pixel buffers (eg YUV and RGB)
-direct from the camera's stills port. That sends the pixel buffer
-and then an empty buffer with the EOS flag set. The EOS buffer
-wasn't handled and returned an error up the stack.
-
-Handle the condition correctly by returning it to the component
-if streaming, or returning with an error if stopping streaming.
-
-Fixes: 9384167 "staging: bcm2835-camera: Remove V4L2/MMAL buffer remapping"
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 21 +++++++++++--------
- .../vc04_services/bcm2835-camera/mmal-vchiq.c |  5 +++--
- 2 files changed, 15 insertions(+), 11 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -346,16 +346,13 @@ static void buffer_cb(struct vchiq_mmal_
- 
- 	if (length == 0) {
- 		/* stream ended */
--		if (buf) {
--			/* this should only ever happen if the port is
--			 * disabled and there are buffers still queued
-+		if (dev->capture.frame_count) {
-+			/* empty buffer whilst capturing - expected to be an
-+			 * EOS, so grab another frame
- 			 */
--			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
--			pr_debug("Empty buffer");
--		} else if (dev->capture.frame_count) {
--			/* grab another frame */
- 			if (is_capturing(dev)) {
--				pr_debug("Grab another frame");
-+				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+					 "Grab another frame");
- 				vchiq_mmal_port_parameter_set(
- 					instance,
- 					dev->capture.camera_port,
-@@ -363,8 +360,14 @@ static void buffer_cb(struct vchiq_mmal_
- 					&dev->capture.frame_count,
- 					sizeof(dev->capture.frame_count));
- 			}
-+			if (vchiq_mmal_submit_buffer(instance, port, buf))
-+				v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+					 "Failed to return EOS buffer");
- 		} else {
--			/* signal frame completion */
-+			/* stopping streaming.
-+			 * return buffer, and signal frame completion
-+			 */
-+			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
- 			complete(&dev->capture.frame_cmplt);
- 		}
- 		return;
---- a/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/mmal-vchiq.c
-@@ -404,8 +404,6 @@ static int bulk_receive(struct vchiq_mma
- 
- 	/* store length */
- 	msg_context->u.bulk.buffer_used = rd_len;
--	msg_context->u.bulk.mmal_flags =
--	    msg->u.buffer_from_host.buffer_header.flags;
- 	msg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts;
- 	msg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts;
- 
-@@ -533,6 +531,9 @@ static void buffer_to_host_cb(struct vch
- 		return;
- 	}
- 
-+	msg_context->u.bulk.mmal_flags =
-+				msg->u.buffer_from_host.buffer_header.flags;
-+
- 	if (msg->h.status != MMAL_MSG_STATUS_SUCCESS) {
- 		/* message reception had an error */
- 		pr_warn("error %d in reply\n", msg->h.status);
diff --git a/target/linux/brcm2708/patches-4.14/950-0407-staging-bcm2835-camera-Set-sequence-number-correctly.patch b/target/linux/brcm2708/patches-4.14/950-0407-staging-bcm2835-camera-Set-sequence-number-correctly.patch
deleted file mode 100644
index edce12ef1..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0407-staging-bcm2835-camera-Set-sequence-number-correctly.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From 8e15cefda972657178522ceb72c834ecd6ed9380 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 21 Jun 2018 17:02:14 +0100
-Subject: [PATCH 407/454] staging: bcm2835-camera: Set sequence number
- correctly
-
-Set the sequence number in vb2_v4l2_buffer mainly so the
-latest v4l2-ctl reports the frame rate correctly.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c | 4 ++++
- drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h | 2 ++
- 2 files changed, 6 insertions(+)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -416,6 +416,7 @@ static void buffer_cb(struct vchiq_mmal_
- 		}
- 	}
- 	dev->capture.last_timestamp = buf->vb.vb2_buf.timestamp;
-+	buf->vb.sequence = dev->capture.sequence++;
- 
- 	vb2_set_plane_payload(&buf->vb.vb2_buf, 0, length);
- 	if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_KEYFRAME)
-@@ -544,6 +545,9 @@ static int start_streaming(struct vb2_qu
- 	/* enable frame capture */
- 	dev->capture.frame_count = 1;
- 
-+	/* reset sequence number */
-+	dev->capture.sequence = 0;
-+
- 	/* if the preview is not already running, wait for a few frames for AGC
- 	 * to settle down.
- 	 */
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.h
-@@ -96,6 +96,8 @@ struct bm2835_mmal_dev {
- 		ktime_t kernel_start_ts;
- 		/* Timestamp of last frame */
- 		u64 		last_timestamp;
-+		/* Sequence number of last buffer */
-+		u32		sequence;
- 
- 		struct vchiq_mmal_port  *port; /* port being used for capture */
- 		/* camera port being used for capture */
diff --git a/target/linux/brcm2708/patches-4.14/950-0408-staging-bcm2835-camera-Ensure-timestamps-never-go-ba.patch b/target/linux/brcm2708/patches-4.14/950-0408-staging-bcm2835-camera-Ensure-timestamps-never-go-ba.patch
deleted file mode 100644
index 8b387ba24..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0408-staging-bcm2835-camera-Ensure-timestamps-never-go-ba.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From d93df875705016c8b767b679ad6d16bf26b2d132 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Tue, 24 Jul 2018 12:08:29 +0100
-Subject: [PATCH 408/454] staging: bcm2835-camera: Ensure timestamps never go
- backwards.
-
-There is an awkward situation with H264 header bytes. Currently
-they are returned with a PTS of 0 because they aren't associated
-with a timestamped frame to encode. These are handled by either
-returning the timestamp of the last buffer to have been received,
-or in the case of the first buffer the timestamp taken at
-start_streaming.
-This results in a race where the current frame may have started
-before we take the start time, which results in the first encoded
-frame having an earlier timestamp than the header bytes.
-
-Ensure that we never return a negative delta to the user by checking
-against the previous timestamp.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../staging/vc04_services/bcm2835-camera/bcm2835-camera.c    | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -400,6 +400,11 @@ static void buffer_cb(struct vchiq_mmal_
- 			 ktime_to_ns(dev->capture.kernel_start_ts),
- 			 dev->capture.vc_start_timestamp, pts,
- 			 ktime_to_ns(timestamp));
-+		if (timestamp < dev->capture.last_timestamp) {
-+			v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
-+				 "Negative delta - using last time\n");
-+			timestamp = dev->capture.last_timestamp;
-+		}
- 		buf->vb.vb2_buf.timestamp = ktime_to_ns(timestamp);
- 	} else {
- 		if (dev->capture.last_timestamp) {
diff --git a/target/linux/brcm2708/patches-4.14/950-0409-dtoverlays-Add-support-for-ADV7280-M-ADV7281-M-and-A.patch b/target/linux/brcm2708/patches-4.14/950-0409-dtoverlays-Add-support-for-ADV7280-M-ADV7281-M-and-A.patch
deleted file mode 100644
index 6b6bacca8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0409-dtoverlays-Add-support-for-ADV7280-M-ADV7281-M-and-A.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From c325695bc45f687cb2b206d02c8d8e7f3c1ad0a1 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Thu, 23 Aug 2018 10:42:41 +0100
-Subject: [PATCH 409/454] dtoverlays: Add support for ADV7280-M, ADV7281-M and
- ADV7281-MA chips.
-
-The driver that supports the ADV7282-M also supports the ADV7280-M,
-ADV7281-M, and ADV7281-MA.
-The 7280-M exposes 8 analogue inputs. The 7281-M doesn't have the
-I2P deinterlacing block. The 7281-MA has 8 inputs but no I2P.
-Otherwise they are the same as ADV7282-M.
-
-Adds a new overlay "adv728x" that includes the existing adv7282
-overlay but adds several parameters to modify the behaviour.
-
-Adds a new addr parameter to allow the I2C address to be changed.
-(the chip has an address select pin to change between 0x20 and 0x21).
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             | 13 +++++++
- .../boot/dts/overlays/adv7282m-overlay.dts    |  9 ++---
- .../boot/dts/overlays/adv728x-m-overlay.dts   | 36 +++++++++++++++++++
- 4 files changed, 55 insertions(+), 4 deletions(-)
- create mode 100644 arch/arm/boot/dts/overlays/adv728x-m-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -7,6 +7,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	ads1115.dtbo \
- 	ads7846.dtbo \
- 	adv7282m.dtbo \
-+	adv728x-m.dtbo \
- 	akkordion-iqdacplus.dtbo \
- 	allo-boss-dac-pcm512x-audio.dtbo \
- 	allo-digione.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -274,6 +274,19 @@ Info:   Analog Devices ADV7282M analogue
- Load:   dtoverlay=adv7282m,<param>=<val>
- Params: i2c_pins_28_29          Use pins 28&29 for the I2C instead of 44&45.
-                                 This is required for Pi B+, 2, 0, and 0W.
-+        addr                    Overrides the I2C address (default 0x21)
-+
-+
-+Name:   adv728x-m
-+Info:   Analog Devices ADV728[0|1|2]-M analogue video to CSI2 bridges.
-+        This is a wrapper for adv7282m, and defaults to ADV7282M.
-+Load:   dtoverlay=adv728x-m,<param>=<val>
-+Params: i2c_pins_28_29          Use pins 28&29 for the I2C instead of 44&45.
-+                                This is required for Pi B+, 2, 0, and 0W.
-+        addr                    Overrides the I2C address (default 0x21)
-+        adv7280m                Select ADV7280-M.
-+        adv7281m                Select ADV7281-M.
-+        adv7281ma               Select ADV7281-MA.
- 
- 
- Name:   akkordion-iqdacplus
---- a/arch/arm/boot/dts/overlays/adv7282m-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/adv7282m-overlay.dts
-@@ -12,13 +12,13 @@
- 			#size-cells = <0>;
- 			status = "okay";
- 
--			adv7282: adv7282@21 {
-+			adv728x: adv728x@21 {
- 				compatible = "adi,adv7282-m";
- 				reg = <0x21>;
- 				status = "okay";
- 				clock-frequency = <24000000>;
- 				port {
--					adv7282_0: endpoint {
-+					adv728x_0: endpoint {
- 						remote-endpoint = <&csi1_ep>;
- 						clock-lanes = <0>;
- 						data-lanes = <1>;
-@@ -42,7 +42,7 @@
- 				#address-cells = <1>;
- 				#size-cells = <0>;
- 				csi1_ep: endpoint {
--					remote-endpoint = <&adv7282_0>;
-+					remote-endpoint = <&adv728x_0>;
- 				};
- 			};
- 		};
-@@ -70,6 +70,7 @@
- 	};
- 
- 	__overrides__ {
--		i2c_pins_28_29 = <0>,"+2-3";
-+		i2c_pins_28_29 =	<0>,"+2-3";
-+		addr =			<&adv728x>,"reg:0";
- 	};
- };
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/adv728x-m-overlay.dts
-@@ -0,0 +1,36 @@
-+// Definitions for Analog Devices ADV728[0|1|2]-M video to CSI2 bridges on VC
-+// I2C bus
-+
-+#include "adv7282m-overlay.dts"
-+
-+/{
-+	compatible = "brcm,bcm2708";
-+
-+	// Fragment numbers deliberately high to avoid conflicts with the
-+	// included adv7282m overlay file.
-+
-+	fragment@101 {
-+		target = <&adv728x>;
-+		__dormant__ {
-+			compatible = "adi,adv7280-m";
-+		};
-+	};
-+	fragment@102 {
-+		target = <&adv728x>;
-+		__dormant__ {
-+			compatible = "adi,adv7281-m";
-+		};
-+	};
-+	fragment@103 {
-+		target = <&adv728x>;
-+		__dormant__ {
-+			compatible = "adi,adv7281-ma";
-+		};
-+	};
-+
-+	__overrides__ {
-+		adv7280m = <0>, "+101";
-+		adv7281m = <0>, "+102";
-+		adv7281ma = <0>, "+103";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0410-bcm2835-interpolate-audio-delay.patch b/target/linux/brcm2708/patches-4.14/950-0410-bcm2835-interpolate-audio-delay.patch
deleted file mode 100644
index 2be6117ef..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0410-bcm2835-interpolate-audio-delay.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From 84ad00eb76af34f8a6c6941dc6da80a3f735b207 Mon Sep 17 00:00:00 2001
-From: wm4 <wm4@nowhere>
-Date: Wed, 13 Jan 2016 19:44:47 +0100
-Subject: [PATCH 410/454] bcm2835: interpolate audio delay
-
-It appears the GPU only sends us a message all 10ms to update
-the playback progress. Other than this, the playback position
-(what SNDRV_PCM_IOCTL_DELAY will return) is not updated at all.
-Userspace will see jitter up to 10ms in the audio position.
-
-Make this a bit nicer for userspace by interpolating the
-position using the CPU clock.
-
-I'm not sure if setting snd_pcm_runtime.delay is the right
-approach for this. Or if there is maybe an already existing
-mechanism for position interpolation in the ALSA core.
-
-I only set SNDRV_PCM_INFO_BATCH because this appears to remove
-at least one situation snd_pcm_runtime.delay is used, so I have
-to worry less in which place I have to update this field, or
-how it interacts with the rest of ALSA.
-
-In the future, it might be nice to use VC_AUDIO_MSG_TYPE_LATENCY.
-One problem is that it requires sending a videocore message, and
-waiting for a reply, which could make the implementation much
-harder due to locking and synchronization requirements.
----
- .../vc04_services/bcm2835-audio/bcm2835-pcm.c       | 13 +++++++++++--
- .../staging/vc04_services/bcm2835-audio/bcm2835.h   |  1 +
- 2 files changed, 12 insertions(+), 2 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c
-+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c
-@@ -22,7 +22,7 @@
- /* hardware definition */
- static const struct snd_pcm_hardware snd_bcm2835_playback_hw = {
- 	.info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
--	SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
-+	SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH),
- 	.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
- 	.rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
- 	.rate_min = 8000,
-@@ -93,6 +93,8 @@ void bcm2835_playback_fifo(struct bcm283
- 		alsa_stream->pos %= alsa_stream->buffer_size;
- 	}
- 
-+	alsa_stream->interpolate_start = ktime_get_ns();
-+
- 	if (alsa_stream->substream) {
- 		if (new_period)
- 			snd_pcm_period_elapsed(alsa_stream->substream);
-@@ -323,6 +325,7 @@ static int snd_bcm2835_pcm_prepare(struc
- 	alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream);
- 	alsa_stream->period_size = snd_pcm_lib_period_bytes(substream);
- 	alsa_stream->pos = 0;
-+	alsa_stream->interpolate_start = ktime_get_ns();
- 
- 	audio_debug("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n",
- 		alsa_stream->buffer_size, alsa_stream->period_size,
-@@ -415,13 +418,19 @@ snd_bcm2835_pcm_pointer(struct snd_pcm_s
- {
- 	struct snd_pcm_runtime *runtime = substream->runtime;
- 	struct bcm2835_alsa_stream *alsa_stream = runtime->private_data;
--
-+	u64 now = ktime_get_ns();
- 
- 	audio_debug("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0,
- 		frames_to_bytes(runtime, runtime->status->hw_ptr),
- 		frames_to_bytes(runtime, runtime->control->appl_ptr),
- 		alsa_stream->pos);
- 
-+	/* Give userspace better delay reporting by interpolating between GPU
-+	 * notifications, assuming audio speed is close enough to the clock
-+	 * used for ktime */
-+	if (alsa_stream->interpolate_start && alsa_stream->interpolate_start < now)
-+		runtime->delay = -(int)div_u64((now - alsa_stream->interpolate_start) * runtime->rate,  1000000000);
-+
- 	return snd_pcm_indirect_playback_pointer(substream,
- 		&alsa_stream->pcm_indirect,
- 		alsa_stream->pos);
---- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.h
-+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.h
-@@ -137,6 +137,7 @@ struct bcm2835_alsa_stream {
- 	unsigned int pos;
- 	unsigned int buffer_size;
- 	unsigned int period_size;
-+	u64 interpolate_start;
- 
- 	atomic_t retrieved;
- 	struct bcm2835_audio_instance *instance;
diff --git a/target/linux/brcm2708/patches-4.14/950-0411-Add-support-for-audioinjector.net-ultra-soundcard.-2.patch b/target/linux/brcm2708/patches-4.14/950-0411-Add-support-for-audioinjector.net-ultra-soundcard.-2.patch
deleted file mode 100644
index 584b9afd1..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0411-Add-support-for-audioinjector.net-ultra-soundcard.-2.patch
+++ /dev/null
@@ -1,141 +0,0 @@
-From e4981de3c02a5d73085ba036be4e104a6b034791 Mon Sep 17 00:00:00 2001
-From: Matt Flax <flatmax@flatmax.org>
-Date: Tue, 28 Aug 2018 18:42:13 +1000
-Subject: [PATCH 411/454] Add support for audioinjector.net ultra soundcard.
- (#2664)
-
-Uses the simple-audio-card ALSA machine driver. Sets up the machine
-driver in the device tree overlay file. The overlays/Makefile is
-altered to add the audioinjector-ultra.dtbo dtb overlay.
-
-Adds CONFIG_SND_SOC_CS4265 to the defconfig files.
-
-Signed-off-by: Matt Flax <flatmax@flatmax.org>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  6 ++
- .../overlays/audioinjector-ultra-overlay.dts  | 71 +++++++++++++++++++
- arch/arm/configs/bcm2709_defconfig            |  1 +
- arch/arm/configs/bcmrpi_defconfig             |  1 +
- 5 files changed, 80 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -17,6 +17,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	applepi-dac.dtbo \
- 	at86rf233.dtbo \
- 	audioinjector-addons.dtbo \
-+	audioinjector-ultra.dtbo \
- 	audioinjector-wm8731-audio.dtbo \
- 	audremap.dtbo \
- 	balena-fin.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -411,6 +411,12 @@ Params: non-stop-clocks         Keeps th
-                                 is paused or stopped (default off)
- 
- 
-+Name:   audioinjector-ultra
-+Info:   Configures the audioinjector.net ultra soundcard
-+Load:   dtoverlay=audioinjector-ultra
-+Params: <None>
-+
-+
- Name:   audioinjector-wm8731-audio
- Info:   Configures the audioinjector.net audio add on soundcard
- Load:   dtoverlay=audioinjector-wm8731-audio
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts
-@@ -0,0 +1,71 @@
-+// Definitions for audioinjector.net audio add on soundcard
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c1>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			cs4265: cs4265@4e {
-+				#sound-dai-cells = <0>;
-+				compatible = "cirrus,cs4265";
-+				reg = <0x4e>;
-+				reset-gpios = <&gpio 5 0>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&sound>;
-+		__overlay__ {
-+			compatible = "simple-audio-card";
-+			i2s-controller = <&i2s>;
-+			status = "okay";
-+
-+			simple-audio-card,name = "audioinjector-ultra";
-+
-+			simple-audio-card,widgets =
-+				"Line", "OUTPUTS",
-+				"Line", "INPUTS";
-+
-+			simple-audio-card,routing =
-+				"OUTPUTS","LINEOUTL",
-+				"OUTPUTS","LINEOUTR",
-+				"OUTPUTS","SPDIFOUT",
-+				"LINEINL","INPUTS",
-+				"LINEINR","INPUTS",
-+				"MICL","INPUTS",
-+				"MICR","INPUTS";
-+
-+			simple-audio-card,format = "i2s";
-+
-+			simple-audio-card,bitclock-master = <&sound_master>;
-+			simple-audio-card,frame-master = <&sound_master>;
-+
-+			simple-audio-card,cpu {
-+				sound-dai = <&i2s>;
-+				dai-tdm-slot-num = <2>;
-+				dai-tdm-slot-width = <32>;
-+			};
-+
-+			sound_master: simple-audio-card,codec {
-+				sound-dai = <&cs4265>;
-+				system-clock-frequency = <12288000>;
-+			};
-+		};
-+	};
-+};
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -917,6 +917,7 @@ CONFIG_SND_SOC_AK4554=m
- CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
-+CONFIG_SND_SOC_CS4265=m
- CONFIG_SND_SIMPLE_CARD=m
- CONFIG_HID_BATTERY_STRENGTH=y
- CONFIG_HIDRAW=y
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -910,6 +910,7 @@ CONFIG_SND_SOC_AK4554=m
- CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
-+CONFIG_SND_SOC_CS4265=m
- CONFIG_SND_SIMPLE_CARD=m
- CONFIG_HID_BATTERY_STRENGTH=y
- CONFIG_HIDRAW=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0412-PoE-HAT-driver-cleanup.patch b/target/linux/brcm2708/patches-4.14/950-0412-PoE-HAT-driver-cleanup.patch
deleted file mode 100644
index 58aa53955..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0412-PoE-HAT-driver-cleanup.patch
+++ /dev/null
@@ -1,245 +0,0 @@
-From 97a6a1f61eb949892457a739435fd5280fc800f8 Mon Sep 17 00:00:00 2001
-From: XECDesign <XECDesign@users.noreply.github.com>
-Date: Wed, 29 Aug 2018 15:08:30 +0100
-Subject: [PATCH 412/454] PoE HAT driver cleanup
-
-* Fix undeclared variable in rpi_poe_fan_suspend
-* Add SPDX-License-Identifier
-* Expand PoE acronym in Kconfig help
-* Give clearer error message on of_property_count_u32_elems fail
-* Add documentation
-* Add vendor to of_device_id compatible string.
-* Rename m_data_s struct to fw_data_s
-* Fix typos
-
-Fixes: #2665
-
-Signed-off-by: Serge Schneider <serge@raspberrypi.org>
----
- .../devicetree/bindings/hwmon/rpi-poe-fan.txt | 55 +++++++++++++++++++
- Documentation/hwmon/rpi-poe-fan               | 15 +++++
- .../arm/boot/dts/overlays/rpi-poe-overlay.dts |  2 +-
- drivers/hwmon/Kconfig                         |  5 +-
- drivers/hwmon/rpi-poe-fan.c                   | 39 ++++++-------
- 5 files changed, 90 insertions(+), 26 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/hwmon/rpi-poe-fan.txt
- create mode 100644 Documentation/hwmon/rpi-poe-fan
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/hwmon/rpi-poe-fan.txt
-@@ -0,0 +1,55 @@
-+Bindings for the Raspberry Pi PoE HAT fan
-+
-+Required properties:
-+- compatible	: "raspberrypi,rpi-poe-fan"
-+- firmware	: Reference to the RPi firmware device node
-+- pwms		: the PWM that is used to control the PWM fan
-+- cooling-levels      : PWM duty cycle values in a range from 0 to 255
-+			which correspond to thermal cooling states
-+
-+Example:
-+	fan0: rpi-poe-fan@0 {
-+		compatible = "raspberrypi,rpi-poe-fan";
-+		firmware = <&firmware>;
-+		cooling-min-state = <0>;
-+		cooling-max-state = <3>;
-+		#cooling-cells = <2>;
-+		cooling-levels = <0 50 150 255>;
-+		status = "okay";
-+	};
-+
-+	thermal-zones {
-+		cpu_thermal: cpu-thermal {
-+			trips {
-+				threshold: trip-point@0 {
-+					temperature = <45000>;
-+					hysteresis = <5000>;
-+					type = "active";
-+				};
-+				target: trip-point@1 {
-+					temperature = <50000>;
-+					hysteresis = <2000>;
-+					type = "active";
-+				};
-+				cpu_hot: cpu_hot@0 {
-+					temperature = <55000>;
-+					hysteresis = <2000>;
-+					type = "active";
-+				};
-+			};
-+			cooling-maps {
-+				map0 {
-+					trip = <&threshold>;
-+					cooling-device = <&fan0 0 1>;
-+				};
-+				map1 {
-+					trip = <&target>;
-+					cooling-device = <&fan0 1 2>;
-+				};
-+				map2 {
-+					trip = <&cpu_hot>;
-+					cooling-device = <&fan0 2 3>;
-+				};
-+			};
-+		};
-+	};
---- /dev/null
-+++ b/Documentation/hwmon/rpi-poe-fan
-@@ -0,0 +1,15 @@
-+Kernel driver rpi-poe-fan
-+=====================
-+
-+This driver enables the use of the Raspberry Pi PoE HAT fan.
-+
-+Author: Serge Schneider <serge@raspberrypi.org>
-+
-+Description
-+-----------
-+
-+The driver implements a simple interface for driving the Raspberry Pi PoE
-+(Power over Ethernet) HAT fan. The driver passes commands to the Raspberry Pi
-+firmware through the mailbox property interface. The firmware then forwards
-+the commands to the board over I2C on the ID_EEPROM pins. The driver exposes
-+the fan to the user space through the hwmon sysfs interface.
---- a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts
-@@ -11,7 +11,7 @@
- 		target-path = "/";
- 		__overlay__ {
- 			fan0: rpi-poe-fan@0 {
--				compatible = "rpi-poe-fan";
-+				compatible = "raspberrypi,rpi-poe-fan";
- 				firmware = <&firmware>;
- 				cooling-min-state = <0>;
- 				cooling-max-state = <3>;
---- a/drivers/hwmon/Kconfig
-+++ b/drivers/hwmon/Kconfig
-@@ -1287,11 +1287,12 @@ config SENSORS_PWM_FAN
- 	  will be called pwm-fan.
- 
- config SENSORS_RPI_POE_FAN
--	tristate "Raspberry Pi POE HAT fan"
-+	tristate "Raspberry Pi PoE HAT fan"
- 	depends on RASPBERRYPI_FIRMWARE
- 	depends on THERMAL || THERMAL=n
- 	help
--	  If you say yes here you get support for Raspberry Pi POE HAT fan.
-+	  If you say yes here you get support for Raspberry Pi PoE (Power over
-+	  Ethernet) HAT fan.
- 
- 	  This driver can also be built as a module.  If so, the module
- 	  will be called rpi-poe-fan.
---- a/drivers/hwmon/rpi-poe-fan.c
-+++ b/drivers/hwmon/rpi-poe-fan.c
-@@ -1,20 +1,11 @@
-+// SPDX-License-Identifier: GPL-2.0
- /*
-- * rpi-poe-fan.c - Hwmon driver for Raspberry Pi POE HAT fan.
-+ * rpi-poe-fan.c - Hwmon driver for Raspberry Pi PoE HAT fan.
-  *
-  * Copyright (C) 2018 Raspberry Pi (Trading) Ltd.
-  * Based on pwm-fan.c by Kamil Debski <k.debski@samsung.com>
-  *
-  * Author: Serge Schneider <serge@raspberrypi.org>
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-  */
- 
- #include <linux/hwmon.h>
-@@ -46,41 +37,41 @@ struct rpi_poe_fan_ctx {
- 	struct notifier_block nb;
- };
- 
--struct m_data_s{
-+struct fw_tag_data_s{
- 	u32 reg;
- 	u32 val;
- 	u32 ret;
- };
- 
- static int write_reg(struct rpi_firmware *fw, u32 reg, u32 *val){
--	struct m_data_s m_data = {
-+	struct fw_tag_data_s fw_tag_data = {
- 		.reg = reg,
- 		.val = *val
- 	};
- 	int ret;
- 	ret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POE_HAT_VAL,
--				    &m_data, sizeof(m_data));
-+				    &fw_tag_data, sizeof(fw_tag_data));
- 	if (ret) {
- 		return ret;
--	} else if (m_data.ret) {
-+	} else if (fw_tag_data.ret) {
- 		return -EIO;
- 	}
- 	return 0;
- }
- 
- static int read_reg(struct rpi_firmware *fw, u32 reg, u32 *val){
--	struct m_data_s m_data = {
-+	struct fw_tag_data_s fw_tag_data = {
- 		.reg = reg,
- 	};
- 	int ret;
- 	ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_POE_HAT_VAL,
--				    &m_data, sizeof(m_data));
-+				    &fw_tag_data, sizeof(fw_tag_data));
- 	if (ret) {
- 		return ret;
--	} else if (m_data.ret) {
-+	} else if (fw_tag_data.ret) {
- 		return -EIO;
- 	}
--	*val = m_data.val;
-+	*val = fw_tag_data.val;
- 	return 0;
- }
- 
-@@ -268,7 +259,8 @@ static int rpi_poe_fan_of_get_cooling_da
- 
- 	ret = of_property_count_u32_elems(np, "cooling-levels");
- 	if (ret <= 0) {
--		dev_err(dev, "Wrong data!\n");
-+		dev_err(dev, "cooling-levels property missing or invalid: %d\n",
-+			ret);
- 		return ret ? : -EINVAL;
- 	}
- 
-@@ -397,10 +389,11 @@ static int rpi_poe_fan_suspend(struct de
- {
- 	struct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);
- 	u32 value = 0;
-+	int ret = 0;
- 
- 	if (ctx->pwm_value != value)
- 		ret = write_reg(ctx->fw, POE_CUR_PWM, &value);
--	return 0;
-+	return ret;
- }
- 
- static int rpi_poe_fan_resume(struct device *dev)
-@@ -420,7 +413,7 @@ static SIMPLE_DEV_PM_OPS(rpi_poe_fan_pm,
- 			 rpi_poe_fan_resume);
- 
- static const struct of_device_id of_rpi_poe_fan_match[] = {
--	{ .compatible = "rpi-poe-fan", },
-+	{ .compatible = "raspberrypi,rpi-poe-fan", },
- 	{},
- };
- MODULE_DEVICE_TABLE(of, of_rpi_poe_fan_match);
-@@ -439,5 +432,5 @@ module_platform_driver(rpi_poe_fan_drive
- 
- MODULE_AUTHOR("Serge Schneider <serge@raspberrypi.org>");
- MODULE_ALIAS("platform:rpi-poe-fan");
--MODULE_DESCRIPTION("Raspberry Pi POE HAT fan driver");
-+MODULE_DESCRIPTION("Raspberry Pi PoE HAT fan driver");
- MODULE_LICENSE("GPL");
diff --git a/target/linux/brcm2708/patches-4.14/950-0413-ASoC-cs4265-Add-a-S-PDIF-enable-switch.patch b/target/linux/brcm2708/patches-4.14/950-0413-ASoC-cs4265-Add-a-S-PDIF-enable-switch.patch
deleted file mode 100644
index 37b3f38b8..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0413-ASoC-cs4265-Add-a-S-PDIF-enable-switch.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 7e9389e69bb200a1a988072d357e248166846c8f Mon Sep 17 00:00:00 2001
-From: Matt Flax <flatmax@flatmax.org>
-Date: Thu, 30 Aug 2018 09:38:02 +1000
-Subject: [PATCH 413/454] ASoC: cs4265: Add a S/PDIF enable switch
-
-commit f853d6b3ba345297974d877d8ed0f4a91eaca739 upstream.
-
-This patch adds a S/PDIF enable switch as a SOC_SINGLE.
-
-Signed-off-by: Matt Flax <flatmax@flatmax.org>
-Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/codecs/cs4265.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/sound/soc/codecs/cs4265.c
-+++ b/sound/soc/codecs/cs4265.c
-@@ -154,6 +154,7 @@ static const struct snd_kcontrol_new cs4
- 	SOC_SINGLE("E to F Buffer Disable Switch", CS4265_SPDIF_CTL1,
- 				6, 1, 0),
- 	SOC_ENUM("C Data Access", cam_mode_enum),
-+	SOC_SINGLE("SPDIF Switch", CS4265_SPDIF_CTL2, 5, 1, 1),
- 	SOC_SINGLE("Validity Bit Control Switch", CS4265_SPDIF_CTL2,
- 				3, 1, 0),
- 	SOC_ENUM("SPDIF Mono/Stereo", spdif_mono_stereo_enum),
diff --git a/target/linux/brcm2708/patches-4.14/950-0414-ASoC-cs4265-Add-native-32bit-I2S-transport.patch b/target/linux/brcm2708/patches-4.14/950-0414-ASoC-cs4265-Add-native-32bit-I2S-transport.patch
deleted file mode 100644
index 51f239379..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0414-ASoC-cs4265-Add-native-32bit-I2S-transport.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 0bd446083b4690dfadd835fab60f6eac4c308da1 Mon Sep 17 00:00:00 2001
-From: Matt Flax <flatmax@flatmax.org>
-Date: Thu, 30 Aug 2018 09:38:01 +1000
-Subject: [PATCH 414/454] ASoC: cs4265: Add native 32bit I2S transport
-
-commit be47e75eb1419ffc1d9c26230963fd5fa3055097 upstream.
-
-The cs4265 uses 32 bit transport on the I2S bus. This patch enables native
-32 bit mode for machine drivers which use this sound card driver.
-
-Signed-off-by: Matt Flax <flatmax@flatmax.org>
-Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/codecs/cs4265.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/sound/soc/codecs/cs4265.c
-+++ b/sound/soc/codecs/cs4265.c
-@@ -497,7 +497,8 @@ static int cs4265_set_bias_level(struct
- 			SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
- 
- #define CS4265_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
--			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
-+			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE | \
-+			SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
- 
- static const struct snd_soc_dai_ops cs4265_ops = {
- 	.hw_params	= cs4265_pcm_hw_params,
diff --git a/target/linux/brcm2708/patches-4.14/950-0415-qmi_wwan-apply-SET_DTR-quirk-to-the-SIMCOM-shared-de.patch b/target/linux/brcm2708/patches-4.14/950-0415-qmi_wwan-apply-SET_DTR-quirk-to-the-SIMCOM-shared-de.patch
deleted file mode 100644
index f4c433978..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0415-qmi_wwan-apply-SET_DTR-quirk-to-the-SIMCOM-shared-de.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From d0b55a012bbf2ffe4307f2632165dc1f8cdc351f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= <bjorn@mork.no>
-Date: Fri, 25 May 2018 15:00:20 +0200
-Subject: [PATCH 415/454] qmi_wwan: apply SET_DTR quirk to the SIMCOM shared
- device ID
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-commit 102cd909635612c0be784a519651954a7924c786 upstream.
-
-SIMCOM are reusing a single device ID for many (all of their?)
-different modems, based on different chipsets and firmwares. Newer
-Qualcomm chipset generations require setting DTR to wake the QMI
-function.  The SIM7600E modem is using such a chipset, making it
-fail to work with this driver despite the device ID match.
-
-Fix by unconditionally enabling the SET_DTR quirk for all SIMCOM
-modems using this specific device ID.  This is similar to what
-we already have done for another case of device IDs recycled over
-multiple chipset generations: 14cf4a771b30 ("drivers: net: usb:
-qmi_wwan: add QMI_QUIRK_SET_DTR for Telit PID 0x1201")
-
-Initial testing on an older SIM7100 modem shows no immediate side
-effects.
-
-Reported-by: Sebastian Sjoholm <sebastian.sjoholm@gmail.com>
-Cc: Reinhard Speyerer <rspmn@arcor.de>
-Signed-off-by: Bjørn Mork <bjorn@mork.no>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/usb/qmi_wwan.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/usb/qmi_wwan.c
-+++ b/drivers/net/usb/qmi_wwan.c
-@@ -1250,7 +1250,7 @@ static const struct usb_device_id produc
- 	{QMI_FIXED_INTF(0x03f0, 0x4e1d, 8)},	/* HP lt4111 LTE/EV-DO/HSPA+ Gobi 4G Module */
- 	{QMI_FIXED_INTF(0x03f0, 0x9d1d, 1)},	/* HP lt4120 Snapdragon X5 LTE */
- 	{QMI_FIXED_INTF(0x22de, 0x9061, 3)},	/* WeTelecom WPD-600N */
--	{QMI_FIXED_INTF(0x1e0e, 0x9001, 5)},	/* SIMCom 7230E */
-+	{QMI_QUIRK_SET_DTR(0x1e0e, 0x9001, 5)},	/* SIMCom 7100E, 7230E, 7600E ++ */
- 	{QMI_QUIRK_SET_DTR(0x2c7c, 0x0125, 4)},	/* Quectel EC25, EC20 R2.0  Mini PCIe */
- 	{QMI_QUIRK_SET_DTR(0x2c7c, 0x0121, 4)},	/* Quectel EC21 Mini PCIe */
- 	{QMI_QUIRK_SET_DTR(0x2c7c, 0x0191, 4)},	/* Quectel EG91 */
diff --git a/target/linux/brcm2708/patches-4.14/950-0416-configs-Add-SENSOR_GPIO_FAN-m.patch b/target/linux/brcm2708/patches-4.14/950-0416-configs-Add-SENSOR_GPIO_FAN-m.patch
deleted file mode 100644
index 60ae03c9b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0416-configs-Add-SENSOR_GPIO_FAN-m.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From de95673d68e09e69cc7c6039136dd2fa0002c42b Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 18 Sep 2018 11:03:20 +0100
-Subject: [PATCH 416/454] configs: Add SENSOR_GPIO_FAN=m
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 3 ++-
- arch/arm/configs/bcmrpi_defconfig  | 3 ++-
- 2 files changed, 4 insertions(+), 2 deletions(-)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -656,6 +656,7 @@ CONFIG_BATTERY_DS2760=m
- CONFIG_BATTERY_GAUGE_LTC2941=m
- CONFIG_HWMON=m
- CONFIG_SENSORS_DS1621=m
-+CONFIG_SENSORS_GPIO_FAN=m
- CONFIG_SENSORS_JC42=m
- CONFIG_SENSORS_LM75=m
- CONFIG_SENSORS_RPI_POE_FAN=m
-@@ -914,10 +915,10 @@ CONFIG_SND_PISOUND=m
- CONFIG_SND_SOC_ADAU1701=m
- CONFIG_SND_SOC_ADAU7002=m
- CONFIG_SND_SOC_AK4554=m
-+CONFIG_SND_SOC_CS4265=m
- CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
--CONFIG_SND_SOC_CS4265=m
- CONFIG_SND_SIMPLE_CARD=m
- CONFIG_HID_BATTERY_STRENGTH=y
- CONFIG_HIDRAW=y
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -649,6 +649,7 @@ CONFIG_BATTERY_DS2760=m
- CONFIG_BATTERY_GAUGE_LTC2941=m
- CONFIG_HWMON=m
- CONFIG_SENSORS_DS1621=m
-+CONFIG_SENSORS_GPIO_FAN=m
- CONFIG_SENSORS_JC42=m
- CONFIG_SENSORS_LM75=m
- CONFIG_SENSORS_RPI_POE_FAN=m
-@@ -907,10 +908,10 @@ CONFIG_SND_PISOUND=m
- CONFIG_SND_SOC_ADAU1701=m
- CONFIG_SND_SOC_ADAU7002=m
- CONFIG_SND_SOC_AK4554=m
-+CONFIG_SND_SOC_CS4265=m
- CONFIG_SND_SOC_CS4271_I2C=m
- CONFIG_SND_SOC_SPDIF=m
- CONFIG_SND_SOC_WM8804_I2C=m
--CONFIG_SND_SOC_CS4265=m
- CONFIG_SND_SIMPLE_CARD=m
- CONFIG_HID_BATTERY_STRENGTH=y
- CONFIG_HIDRAW=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0417-BCM270X_DT-Add-gpio-fan-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0417-BCM270X_DT-Add-gpio-fan-overlay.patch
deleted file mode 100644
index 4e7f3641b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0417-BCM270X_DT-Add-gpio-fan-overlay.patch
+++ /dev/null
@@ -1,114 +0,0 @@
-From 498dfe7d12a047e4a3b466683b0b8138ea74ed9b Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 18 Sep 2018 11:08:07 +0100
-Subject: [PATCH 417/454] BCM270X_DT: Add gpio-fan overlay
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  8 +++
- .../boot/dts/overlays/gpio-fan-overlay.dts    | 71 +++++++++++++++++++
- 3 files changed, 80 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/gpio-fan-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -35,6 +35,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	fe-pi-audio.dtbo \
- 	goodix.dtbo \
- 	googlevoicehat-soundcard.dtbo \
-+	gpio-fan.dtbo \
- 	gpio-ir.dtbo \
- 	gpio-ir-tx.dtbo \
- 	gpio-key.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -563,6 +563,14 @@ Load:   dtoverlay=googlevoicehat-soundca
- Params: <None>
- 
- 
-+Name:   gpio-fan
-+Info:   Configure a GPIO pin to control a cooling fan.
-+Load:   dtoverlay=gpio-fan,<param>=<val>
-+Params: gpiopin                 GPIO used to control the fan (default 12)
-+        temp                    Temperature at which the fan switches on, in
-+                                millicelcius (default 55000)
-+
-+
- Name:   gpio-ir
- Info:   Use GPIO pin as rc-core style infrared receiver input. The rc-core-
-         based gpio_ir_recv driver maps received keys directly to a
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts
-@@ -0,0 +1,71 @@
-+/*
-+ * Overlay for the Raspberry Pi GPIO Fan @ BCM GPIO12.
-+ * Optional parameters:
-+ *	- "gpiopin"	- default GPIO12
-+ * 	- "temp"	- default 55000
-+ * Requires:
-+ *	- kernel configurations: CONFIG_SENSORS_GPIO_FAN=m and CONFIG_SENSORS_PWM_FAN=m;
-+ *	- kernel rebuid;
-+ *	- DC Fan connected to GPIO via a N-MOSFET (2N7002)
-+ *
-+ *                   ┌─────────────────────┐
-+ *                   │Fan negative terminal│
-+ *                   └┬────────────────────┘
-+ *                    │
-+ *                 │──┘
-+ * [GPIO12]──────┤ │<─┐  2N7002
-+ *                 │──┤
-+ *                    │
-+ *                   ─┴─
-+ *                   GND
-+ *
-+ * sudo dtc -W no-unit_address_vs_reg -@ -I dts -O dtb -o /boot/overlays/gpio-fan.dtbo gpio-fan.dts
-+ * sudo nano /boot/config.txt add "dtoverlay=gpio-fan" or "dtoverlay=gpio-fan,gpiopin=12,temp=45000"
-+ * or
-+ * sudo sh -c "echo '\n# Enable PI GPIO-Fan\ndtoverlay=gpio-fan\n' >> /boot/config.txt"
-+ * sudo sh -c "echo '\n# Enable PI GPIO-Fan\ndtoverlay=gpio-fan,gpiopin=12\n' >> /boot/config.txt"
-+ *
-+ */
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target-path = "/";
-+		__overlay__ {
-+			fan0: gpio-fan@0 {
-+				compatible = "gpio-fan";
-+				gpios = <&gpio 12 1>;
-+				gpio-fan,speed-map = <0    0>,
-+									 <5000 1>;
-+				#cooling-cells = <2>;
-+			};
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&cpu_thermal>;
-+		polling-delay = <2000>;	/* milliseconds */
-+		__overlay__ {
-+			trips {
-+				cpu_hot: trip-point@0 {
-+					temperature = <55000>;	/* (millicelsius) Fan started at 55°C */
-+					hysteresis = <5000>;	/* (millicelsius) Fan stopped at 50°C */
-+					type = "active";
-+				};
-+			};
-+			cooling-maps {
-+				map0 {
-+					trip = <&cpu_hot>;
-+					cooling-device = <&fan0 1 1>;
-+				};
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		gpiopin = <&fan0>,"gpios:4", <&fan0>,"brcm,pins:0";
-+		temp = <&cpu_hot>,"temperature:0";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0418-dtoverlays-Correct-DT-handling-camera-GPIOs.patch b/target/linux/brcm2708/patches-4.14/950-0418-dtoverlays-Correct-DT-handling-camera-GPIOs.patch
deleted file mode 100644
index 7f7769488..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0418-dtoverlays-Correct-DT-handling-camera-GPIOs.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From ea59741f2679e30d765b6a9e0d45265e3033a38c Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Tue, 18 Sep 2018 10:47:38 +0100
-Subject: [PATCH 418/454] dtoverlays: Correct DT handling camera GPIOs
-
-The firmware has support for updating overrides with the correct
-GPIO settings for the camera GPIOs, but the wrong device tree
-setup ended up being merged.
-Correct the DT configuration so that the firmware does set it
-up correctly.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- arch/arm/boot/dts/bcm270x.dtsi                |  7 +++++++
- arch/arm/boot/dts/overlays/README             | 10 +---------
- arch/arm/boot/dts/overlays/ov5647-overlay.dts | 12 ++++++++++--
- 3 files changed, 18 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/bcm270x.dtsi
-+++ b/arch/arm/boot/dts/bcm270x.dtsi
-@@ -152,6 +152,13 @@
- 		regulator-max-microvolt = <3300000>;
- 		regulator-always-on;
- 	};
-+
-+	__overrides__ {
-+		cam0-pwdn-ctrl;
-+		cam0-pwdn;
-+		cam0-led-ctrl;
-+		cam0-led;
-+	};
- };
- 
- /* Configure and use the auxilliary interrupt controller */
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1283,15 +1283,7 @@ Info:   Omnivision OV5647 camera module.
-         Uses Unicam 1, which is the standard camera connector on most Pi
-         variants.
- Load:   dtoverlay=ov5647,<param>=<val>
--Params: cam0-pwdn               GPIO used to control the sensor powerdown line.
--
--        cam0-led                GPIO used to control the sensor led
--                                Both these fields should be automatically filled
--                                in by the firmware to reflect the default GPIO
--                                configuration of the particular Pi variant in
--                                use.
--
--        i2c_pins_28_29          Use pins 28&29 for the I2C instead of 44&45.
-+Params: i2c_pins_28_29          Use pins 28&29 for the I2C instead of 44&45.
-                                 This is required for Pi B+, 2, 0, and 0W.
- 
- 
---- a/arch/arm/boot/dts/overlays/ov5647-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/ov5647-overlay.dts
-@@ -78,9 +78,17 @@
- 		};
- 	};
- 
-+	fragment@5 {
-+		target-path="/__overrides__";
-+		__overlay__ {
-+			cam0-pwdn-ctrl = <&ov5647>,"pwdn-gpios:0";
-+			cam0-pwdn      = <&ov5647>,"pwdn-gpios:4";
-+			cam0-led-ctrl  = <&ov5647>,"pwdn-gpios:12";
-+			cam0-led       = <&ov5647>,"pwdn-gpios:16";
-+		};
-+	};
-+
- 	__overrides__ {
- 		i2c_pins_28_29 = <0>,"+4-5";
--		cam0-pwdn = <&ov5647>,"pwdn-gpios:4";
--		cam0-led = <&ov5647>,"pwdn-gpios:16";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0419-media-ov5647-Use-gpiod_set_value_cansleep.patch b/target/linux/brcm2708/patches-4.14/950-0419-media-ov5647-Use-gpiod_set_value_cansleep.patch
deleted file mode 100644
index 5517d1f61..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0419-media-ov5647-Use-gpiod_set_value_cansleep.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 185076ab6bc5dd83f2da62552fbb79a53d36314d Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Tue, 18 Sep 2018 11:08:51 +0100
-Subject: [PATCH 419/454] media: ov5647: Use gpiod_set_value_cansleep
-
-All calls to the gpio library are in contexts that can sleep,
-therefore there is no issue with having those GPIOs controlled
-by controllers which require sleeping (eg I2C GPIO expanders).
-
-Switch to using gpiod_set_value_cansleep instead of gpiod_set_value
-to avoid triggering the warning in gpiolib should the GPIO
-controller need to sleep.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/media/i2c/ov5647.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/media/i2c/ov5647.c
-+++ b/drivers/media/i2c/ov5647.c
-@@ -348,7 +348,7 @@ static int ov5647_sensor_power(struct v4
- 		dev_dbg(&client->dev, "OV5647 power on\n");
- 
- 		if (ov5647->pwdn) {
--			gpiod_set_value(ov5647->pwdn, 0);
-+			gpiod_set_value_cansleep(ov5647->pwdn, 0);
- 			msleep(PWDN_ACTIVE_DELAY_MS);
- 		}
- 
-@@ -390,7 +390,7 @@ static int ov5647_sensor_power(struct v4
- 
- 		clk_disable_unprepare(ov5647->xclk);
- 
--		gpiod_set_value(ov5647->pwdn, 1);
-+		gpiod_set_value_cansleep(ov5647->pwdn, 1);
- 	}
- 
- 	/* Update the power count. */
-@@ -624,13 +624,13 @@ static int ov5647_probe(struct i2c_clien
- 		goto mutex_remove;
- 
- 	if (sensor->pwdn) {
--		gpiod_set_value(sensor->pwdn, 0);
-+		gpiod_set_value_cansleep(sensor->pwdn, 0);
- 		msleep(PWDN_ACTIVE_DELAY_MS);
- 	}
- 
- 	ret = ov5647_detect(sd);
- 
--	gpiod_set_value(sensor->pwdn, 1);
-+	gpiod_set_value_cansleep(sensor->pwdn, 1);
- 
- 	if (ret < 0)
- 		goto error;
diff --git a/target/linux/brcm2708/patches-4.14/950-0420-dwc_otg-fiq_fsm-fix-incorrect-DMA-register-offset-ca.patch b/target/linux/brcm2708/patches-4.14/950-0420-dwc_otg-fiq_fsm-fix-incorrect-DMA-register-offset-ca.patch
deleted file mode 100644
index fa05b1970..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0420-dwc_otg-fiq_fsm-fix-incorrect-DMA-register-offset-ca.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 502af2ba683831fb4c05bd887374053d17376c87 Mon Sep 17 00:00:00 2001
-From: P33M <p33m@github.com>
-Date: Fri, 21 Sep 2018 14:05:09 +0100
-Subject: [PATCH 420/454] dwc_otg: fiq_fsm: fix incorrect DMA register offset
- calculation
-
-Rationalise the offset and update all call sites.
-
-Fixes https://github.com/raspberrypi/linux/issues/2408
----
- drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 8 ++++----
- drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 2 +-
- 2 files changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
-@@ -250,7 +250,7 @@ static int notrace fiq_increment_dma_buf
- 		BUG();
- 
- 	hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
--	FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
- 	st->channel[n].dma_info.index = i;
- 	return 0;
- }
-@@ -302,7 +302,7 @@ static int notrace fiq_iso_out_advance(s
- 
- 	/* New DMA address - address of bounce buffer referred to in index */
- 	hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
--	//hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
-+	//hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);
- 	//hcdma.d32 += st->channel[n].dma_info.slot_len[i];
- 	fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
- 	fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
-@@ -317,7 +317,7 @@ static int notrace fiq_iso_out_advance(s
- 	st->channel[n].dma_info.index++;
- 	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
- 	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
--	FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+	FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
- 	return last;
- }
- 
-@@ -564,7 +564,7 @@ static int notrace noinline fiq_fsm_upda
- 
- 	/* grab the next DMA address offset from the array */
- 	hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
--	FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
-+	FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
- 
- 	/* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
- 	 * the core needs to be told to send the correct number. Caution: for IN transfers,
---- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
-+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
-@@ -94,7 +94,7 @@ do {							\
- #define HC_START	0x500
- #define HC_OFFSET	0x020
- 
--#define HC_DMA		0x514
-+#define HC_DMA		0x14
- 
- #define HCCHAR		0x00
- #define HCSPLT		0x04
diff --git a/target/linux/brcm2708/patches-4.14/950-0422-configs-Add-CONFIG_HID_BIGBEN_FF-m.patch b/target/linux/brcm2708/patches-4.14/950-0422-configs-Add-CONFIG_HID_BIGBEN_FF-m.patch
deleted file mode 100644
index 9c70996e0..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0422-configs-Add-CONFIG_HID_BIGBEN_FF-m.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From c036841a3e40473596002b866ef422af33e07962 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 24 Sep 2018 14:56:58 +0100
-Subject: [PATCH 422/454] configs: Add CONFIG_HID_BIGBEN_FF=m
-
-See: https://github.com/raspberrypi/linux/issues/2690
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -929,6 +929,7 @@ CONFIG_HID_APPLE=m
- CONFIG_HID_ASUS=m
- CONFIG_HID_BELKIN=m
- CONFIG_HID_BETOP_FF=m
-+CONFIG_HID_BIGBEN_FF=m
- CONFIG_HID_CHERRY=m
- CONFIG_HID_CHICONY=m
- CONFIG_HID_CYPRESS=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -922,6 +922,7 @@ CONFIG_HID_APPLE=m
- CONFIG_HID_ASUS=m
- CONFIG_HID_BELKIN=m
- CONFIG_HID_BETOP_FF=m
-+CONFIG_HID_BIGBEN_FF=m
- CONFIG_HID_CHERRY=m
- CONFIG_HID_CHICONY=m
- CONFIG_HID_CYPRESS=m
diff --git a/target/linux/brcm2708/patches-4.14/950-0423-ASoC-cs4265-Add-a-MIC-pre.-route-2696.patch b/target/linux/brcm2708/patches-4.14/950-0423-ASoC-cs4265-Add-a-MIC-pre.-route-2696.patch
deleted file mode 100644
index aa99f322d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0423-ASoC-cs4265-Add-a-MIC-pre.-route-2696.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 2c85d648b750a406eee62a2647173e2b99915ab7 Mon Sep 17 00:00:00 2001
-From: Matt Flax <flatmax@flatmax.org>
-Date: Fri, 28 Sep 2018 15:13:28 +1000
-Subject: [PATCH 423/454] ASoC: cs4265: Add a MIC pre. route (#2696)
-
-Commit 	b0ef5011b981ece1fde8063243a56d3038b87adb upstream.
-
-The cs4265 driver is missing a microphone preamp enable.
-This patch enables/disables the microphone preamp when mic
-selection is made using the kcontrol.
-
-Signed-off-by: Matt Flax <flatmax@flatmax.org>
-Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/codecs/cs4265.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/sound/soc/codecs/cs4265.c
-+++ b/sound/soc/codecs/cs4265.c
-@@ -222,10 +222,11 @@ static const struct snd_soc_dapm_route c
- 	{"LINEOUTR", NULL, "DAC"},
- 	{"SPDIFOUT", NULL, "SPDIF"},
- 
-+	{"Pre-amp MIC", NULL, "MICL"},
-+	{"Pre-amp MIC", NULL, "MICR"},
-+	{"ADC Mux", "MIC", "Pre-amp MIC"},
- 	{"ADC Mux", "LINEIN", "LINEINL"},
- 	{"ADC Mux", "LINEIN", "LINEINR"},
--	{"ADC Mux", "MIC", "MICL"},
--	{"ADC Mux", "MIC", "MICR"},
- 	{"ADC", NULL, "ADC Mux"},
- 	{"DOUT", NULL, "ADC"},
- 	{"DAI1 Capture", NULL, "DOUT"},
diff --git a/target/linux/brcm2708/patches-4.14/950-0424-vchiq_2835_arm-Implement-a-DMA-pool-for-small-bulk-t.patch b/target/linux/brcm2708/patches-4.14/950-0424-vchiq_2835_arm-Implement-a-DMA-pool-for-small-bulk-t.patch
deleted file mode 100644
index 0c93a14dc..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0424-vchiq_2835_arm-Implement-a-DMA-pool-for-small-bulk-t.patch
+++ /dev/null
@@ -1,126 +0,0 @@
-From 88acd92a7cbcb8a6ae299b88554abbc9bedbae0a Mon Sep 17 00:00:00 2001
-From: detule <ogjoneski@gmail.com>
-Date: Tue, 2 Oct 2018 04:10:08 -0400
-Subject: [PATCH 424/454] vchiq_2835_arm: Implement a DMA pool for small bulk
- transfers (#2699)
-
-During a bulk transfer we request a DMA allocation to hold the
-scatter-gather list.  Most of the time, this allocation is small
-(<< PAGE_SIZE), however it can be requested at a high enough frequency
-to cause fragmentation and/or stress the CMA allocator (think time
-spent in compaction here, or during allocations elsewhere).
-
-Implement a pool to serve up small DMA allocations, falling back
-to a coherent allocation if the request is greater than
-VCHIQ_DMA_POOL_SIZE.
-
-Signed-off-by: Oliver Gjoneski <ogjoneski@gmail.com>
----
- .../interface/vchiq_arm/vchiq_2835_arm.c      | 40 +++++++++++++++----
- 1 file changed, 33 insertions(+), 7 deletions(-)
-
---- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
-+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
-@@ -37,6 +37,7 @@
- #include <linux/interrupt.h>
- #include <linux/pagemap.h>
- #include <linux/dma-mapping.h>
-+#include <linux/dmapool.h>
- #include <linux/io.h>
- #include <linux/platform_device.h>
- #include <linux/uaccess.h>
-@@ -59,6 +60,8 @@
- #define BELL0	0x00
- #define BELL2	0x08
- 
-+#define VCHIQ_DMA_POOL_SIZE PAGE_SIZE
-+
- typedef struct vchiq_2835_state_struct {
- 	int inited;
- 	VCHIQ_ARM_STATE_T arm_state;
-@@ -68,6 +71,7 @@ struct vchiq_pagelist_info {
- 	PAGELIST_T *pagelist;
- 	size_t pagelist_buffer_size;
- 	dma_addr_t dma_addr;
-+	bool is_from_pool;
- 	enum dma_data_direction dma_dir;
- 	unsigned int num_pages;
- 	unsigned int pages_need_release;
-@@ -78,6 +82,7 @@ struct vchiq_pagelist_info {
- 
- static void __iomem *g_regs;
- static unsigned int g_cache_line_size = sizeof(CACHE_LINE_SIZE);
-+static struct dma_pool *g_dma_pool;
- static unsigned int g_fragments_size;
- static char *g_fragments_base;
- static char *g_free_fragments;
-@@ -193,6 +198,14 @@ int vchiq_platform_init(struct platform_
- 	}
- 
- 	g_dev = dev;
-+	g_dma_pool = dmam_pool_create("vchiq_scatter_pool", dev,
-+				      VCHIQ_DMA_POOL_SIZE, g_cache_line_size,
-+				      0);
-+	if (!g_dma_pool) {
-+		dev_err(dev, "failed to create dma pool");
-+		return -ENOMEM;
-+	}
-+
- 	vchiq_log_info(vchiq_arm_log_level,
- 		"vchiq_init - done (slots %pK, phys %pad)",
- 		vchiq_slot_zero, &slot_phys);
-@@ -377,9 +390,14 @@ cleanup_pagelistinfo(struct vchiq_pageli
- 		for (i = 0; i < pagelistinfo->num_pages; i++)
- 			put_page(pagelistinfo->pages[i]);
- 	}
--
--	dma_free_coherent(g_dev, pagelistinfo->pagelist_buffer_size,
--			  pagelistinfo->pagelist, pagelistinfo->dma_addr);
-+	if (pagelistinfo->is_from_pool) {
-+		dma_pool_free(g_dma_pool, pagelistinfo->pagelist,
-+			      pagelistinfo->dma_addr);
-+	} else {
-+		dma_free_coherent(g_dev, pagelistinfo->pagelist_buffer_size,
-+				  pagelistinfo->pagelist,
-+				  pagelistinfo->dma_addr);
-+	}
- }
- 
- /* There is a potential problem with partial cache lines (pages?)
-@@ -400,6 +418,7 @@ create_pagelist(char __user *buf, size_t
- 	u32 *addrs;
- 	unsigned int num_pages, offset, i, k;
- 	int actual_pages;
-+	bool is_from_pool;
- 	size_t pagelist_size;
- 	struct scatterlist *scatterlist, *sg;
- 	int dma_buffers;
-@@ -417,10 +436,16 @@ create_pagelist(char __user *buf, size_t
- 	/* Allocate enough storage to hold the page pointers and the page
- 	** list
- 	*/
--	pagelist = dma_zalloc_coherent(g_dev,
--				       pagelist_size,
--				       &dma_addr,
--				       GFP_KERNEL);
-+	if (pagelist_size > VCHIQ_DMA_POOL_SIZE) {
-+		pagelist = dma_zalloc_coherent(g_dev,
-+					       pagelist_size,
-+					       &dma_addr,
-+					       GFP_KERNEL);
-+		is_from_pool = false;
-+	} else {
-+		pagelist = dma_pool_zalloc(g_dma_pool, GFP_KERNEL, &dma_addr);
-+		is_from_pool = true;
-+	}
- 
- 	vchiq_log_trace(vchiq_arm_log_level, "create_pagelist - %pK",
- 			pagelist);
-@@ -441,6 +466,7 @@ create_pagelist(char __user *buf, size_t
- 	pagelistinfo->pagelist = pagelist;
- 	pagelistinfo->pagelist_buffer_size = pagelist_size;
- 	pagelistinfo->dma_addr = dma_addr;
-+	pagelistinfo->is_from_pool = is_from_pool;
- 	pagelistinfo->dma_dir =  (type == PAGELIST_WRITE) ?
- 				  DMA_TO_DEVICE : DMA_FROM_DEVICE;
- 	pagelistinfo->num_pages = num_pages;
diff --git a/target/linux/brcm2708/patches-4.14/950-0425-Update-gpio-fan-overlay.dts-2711.patch b/target/linux/brcm2708/patches-4.14/950-0425-Update-gpio-fan-overlay.dts-2711.patch
deleted file mode 100644
index cbeea060b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0425-Update-gpio-fan-overlay.dts-2711.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 4f420b1d3606ec5652dc8fe8092756158f652755 Mon Sep 17 00:00:00 2001
-From: Paul <paulenuta@users.noreply.github.com>
-Date: Thu, 11 Oct 2018 12:17:20 +0300
-Subject: [PATCH 425/454] Update gpio-fan-overlay.dts (#2711)
-
-Add references, links, clear details, some typo correction.
----
- .../boot/dts/overlays/gpio-fan-overlay.dts    | 36 +++++++++++--------
- 1 file changed, 22 insertions(+), 14 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts
-@@ -1,29 +1,37 @@
- /*
-  * Overlay for the Raspberry Pi GPIO Fan @ BCM GPIO12.
-+ * References: 
-+ *	- https://www.raspberrypi.org/forums/viewtopic.php?f=107&p=1367135#p1365084
-+ *
-  * Optional parameters:
-- *	- "gpiopin"	- default GPIO12
-- * 	- "temp"	- default 55000
-+ *	- "gpiopin"	- BCM number of the pin driving the fan, default 12 (GPIO12);
-+ * 	- "temp"	- CPU temperature at which fan is started in millicelsius, default 55000;
-+ *
-  * Requires:
-- *	- kernel configurations: CONFIG_SENSORS_GPIO_FAN=m and CONFIG_SENSORS_PWM_FAN=m;
-- *	- kernel rebuid;
-- *	- DC Fan connected to GPIO via a N-MOSFET (2N7002)
-+ *	- kernel configurations: CONFIG_SENSORS_GPIO_FAN=m;
-+ *	- kernel rebuild;
-+ *	- N-MOSFET connected to gpiopin, 2N7002-[https://en.wikipedia.org/wiki/2N7000];
-+ *	- DC Fan connected to N-MOSFET Drain terminal, a 12V fan is working fine and quite silently;
-+ *	  [https://www.tme.eu/en/details/ee40101s1-999-a/dc12v-fans/sunon/ee40101s1-1000u-999/]
-  *
-  *                   ┌─────────────────────┐
-  *                   │Fan negative terminal│
-  *                   └┬────────────────────┘
-- *                    │
-- *                 │──┘
-+ *                    │D
-+ *             G   │──┘
-  * [GPIO12]──────┤ │<─┐  2N7002
-  *                 │──┤
-- *                    │
-+ *                    │S
-  *                   ─┴─
-  *                   GND
-  *
-- * sudo dtc -W no-unit_address_vs_reg -@ -I dts -O dtb -o /boot/overlays/gpio-fan.dtbo gpio-fan.dts
-- * sudo nano /boot/config.txt add "dtoverlay=gpio-fan" or "dtoverlay=gpio-fan,gpiopin=12,temp=45000"
-- * or
-- * sudo sh -c "echo '\n# Enable PI GPIO-Fan\ndtoverlay=gpio-fan\n' >> /boot/config.txt"
-- * sudo sh -c "echo '\n# Enable PI GPIO-Fan\ndtoverlay=gpio-fan,gpiopin=12\n' >> /boot/config.txt"
-+ * Build:
-+ * 	- `sudo dtc -W no-unit_address_vs_reg -@ -I dts -O dtb -o /boot/overlays/gpio-fan.dtbo gpio-fan-overlay.dts`
-+ * Activate:
-+ *	- sudo nano /boot/config.txt add "dtoverlay=gpio-fan" or "dtoverlay=gpio-fan,gpiopin=12,temp=45000"
-+ *	 or
-+ *	- sudo sh -c 'printf "\n# Enable PI GPIO-Fan Default\ndtoverlay=gpio-fan\n" >> /boot/config.txt'
-+ *	- sudo sh -c 'printf "\n# Enable PI GPIO-Fan Custom\ntoverlay=gpio-fan,gpiopin=12,temp=45000\n" >> /boot/config.txt'
-  *
-  */
- /dts-v1/;
-@@ -52,7 +60,7 @@
- 			trips {
- 				cpu_hot: trip-point@0 {
- 					temperature = <55000>;	/* (millicelsius) Fan started at 55°C */
--					hysteresis = <5000>;	/* (millicelsius) Fan stopped at 50°C */
-+					hysteresis = <10000>;	/* (millicelsius) Fan stopped at 45°C */
- 					type = "active";
- 				};
- 			};
diff --git a/target/linux/brcm2708/patches-4.14/950-0426-drivers-thermal-step_wise-add-support-for-hysteresis.patch b/target/linux/brcm2708/patches-4.14/950-0426-drivers-thermal-step_wise-add-support-for-hysteresis.patch
deleted file mode 100644
index e715e4e21..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0426-drivers-thermal-step_wise-add-support-for-hysteresis.patch
+++ /dev/null
@@ -1,96 +0,0 @@
-From bcf41a406eb1c0e2a7f3e5ac0baef5455933afd7 Mon Sep 17 00:00:00 2001
-From: Ram Chandrasekar <rkumbako@codeaurora.org>
-Date: Mon, 7 May 2018 11:54:08 -0600
-Subject: [PATCH 426/454] drivers: thermal: step_wise: add support for
- hysteresis
-
-From: Ram Chandrasekar <rkumbako@codeaurora.org>
-
-Step wise governor increases the mitigation level when the temperature
-goes above a threshold and will decrease the mitigation when the
-temperature falls below the threshold. If it were a case, where the
-temperature hovers around a threshold, the mitigation will be applied
-and removed at every iteration. This reaction to the temperature is
-inefficient for performance.
-
-The use of hysteresis temperature could avoid this ping-pong of
-mitigation by relaxing the mitigation to happen only when the
-temperature goes below this lower hysteresis value.
-
-Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
-Signed-off-by: Lina Iyer <ilina@codeaurora.org>
----
- drivers/thermal/step_wise.c | 33 +++++++++++++++++++++++----------
- 1 file changed, 23 insertions(+), 10 deletions(-)
-
---- a/drivers/thermal/step_wise.c
-+++ b/drivers/thermal/step_wise.c
-@@ -36,7 +36,7 @@
-  *       for this trip point
-  *    d. if the trend is THERMAL_TREND_DROP_FULL, use lower limit
-  *       for this trip point
-- * If the temperature is lower than a trip point,
-+ * If the temperature is lower than a hysteresis temperature,
-  *    a. if the trend is THERMAL_TREND_RAISING, do nothing
-  *    b. if the trend is THERMAL_TREND_DROPPING, use lower cooling
-  *       state for this trip point, if the cooling state already
-@@ -127,7 +127,7 @@ static void update_passive_instance(stru
- 
- static void thermal_zone_trip_update(struct thermal_zone_device *tz, int trip)
- {
--	int trip_temp;
-+	int trip_temp, hyst_temp;
- 	enum thermal_trip_type trip_type;
- 	enum thermal_trend trend;
- 	struct thermal_instance *instance;
-@@ -135,22 +135,23 @@ static void thermal_zone_trip_update(str
- 	int old_target;
- 
- 	if (trip == THERMAL_TRIPS_NONE) {
--		trip_temp = tz->forced_passive;
-+		hyst_temp = trip_temp = tz->forced_passive;
- 		trip_type = THERMAL_TRIPS_NONE;
- 	} else {
- 		tz->ops->get_trip_temp(tz, trip, &trip_temp);
-+		hyst_temp = trip_temp;
-+		if (tz->ops->get_trip_hyst) {
-+			tz->ops->get_trip_hyst(tz, trip, &hyst_temp);
-+			hyst_temp = trip_temp - hyst_temp;
-+		}
- 		tz->ops->get_trip_type(tz, trip, &trip_type);
- 	}
- 
- 	trend = get_tz_trend(tz, trip);
- 
--	if (tz->temperature >= trip_temp) {
--		throttle = true;
--		trace_thermal_zone_trip(tz, trip, trip_type);
--	}
--
--	dev_dbg(&tz->device, "Trip%d[type=%d,temp=%d]:trend=%d,throttle=%d\n",
--				trip, trip_type, trip_temp, trend, throttle);
-+	dev_dbg(&tz->device,
-+		"Trip%d[type=%d,temp=%d,hyst=%d]:trend=%d,throttle=%d\n",
-+		trip, trip_type, trip_temp, hyst_temp, trend, throttle);
- 
- 	mutex_lock(&tz->lock);
- 
-@@ -159,6 +160,18 @@ static void thermal_zone_trip_update(str
- 			continue;
- 
- 		old_target = instance->target;
-+		throttle = false;
-+		/*
-+		 * Lower the mitigation only if the temperature
-+		 * goes below the hysteresis temperature.
-+		 */
-+		if (tz->temperature >= trip_temp ||
-+		   (tz->temperature >= hyst_temp &&
-+		   old_target != THERMAL_NO_TARGET)) {
-+			throttle = true;
-+			trace_thermal_zone_trip(tz, trip, trip_type);
-+		}
-+
- 		instance->target = get_target_state(instance, trend, throttle);
- 		dev_dbg(&instance->cdev->device, "old_target=%d, target=%d\n",
- 					old_target, (int)instance->target);
diff --git a/target/linux/brcm2708/patches-4.14/950-0427-drivers-thermal-step_wise-avoid-throttling-at-hyster.patch b/target/linux/brcm2708/patches-4.14/950-0427-drivers-thermal-step_wise-avoid-throttling-at-hyster.patch
deleted file mode 100644
index f0fa93365..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0427-drivers-thermal-step_wise-avoid-throttling-at-hyster.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From a06f6477429a37eee70347349040166f81395041 Mon Sep 17 00:00:00 2001
-From: Serge Schneider <serge@raspberrypi.org>
-Date: Tue, 2 Oct 2018 11:14:15 +0100
-Subject: [PATCH 427/454] drivers: thermal: step_wise: avoid throttling at
- hysteresis temperature after dropping below it
-
-Signed-off-by: Serge Schneider <serge@raspberrypi.org>
----
- drivers/thermal/step_wise.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/step_wise.c
-+++ b/drivers/thermal/step_wise.c
-@@ -167,7 +167,7 @@ static void thermal_zone_trip_update(str
- 		 */
- 		if (tz->temperature >= trip_temp ||
- 		   (tz->temperature >= hyst_temp &&
--		   old_target != THERMAL_NO_TARGET)) {
-+		   old_target == instance->upper)) {
- 			throttle = true;
- 			trace_thermal_zone_trip(tz, trip, trip_type);
- 		}
diff --git a/target/linux/brcm2708/patches-4.14/950-0428-hwmon-adjust-rpi-poe-fan-overlay-trip-points.patch b/target/linux/brcm2708/patches-4.14/950-0428-hwmon-adjust-rpi-poe-fan-overlay-trip-points.patch
deleted file mode 100644
index 52e54ec7c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0428-hwmon-adjust-rpi-poe-fan-overlay-trip-points.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From 9ec0b2a0a3a74c4740ccb312955b7ebc262197e5 Mon Sep 17 00:00:00 2001
-From: Serge Schneider <serge@raspberrypi.org>
-Date: Wed, 26 Sep 2018 19:44:59 +0100
-Subject: [PATCH 428/454] hwmon: adjust rpi-poe-fan overlay trip points
-
-Signed-off-by: Serge Schneider <serge@raspberrypi.org>
----
- .../arm/boot/dts/overlays/rpi-poe-overlay.dts | 26 +++++++------------
- 1 file changed, 9 insertions(+), 17 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts
-@@ -14,9 +14,9 @@
- 				compatible = "raspberrypi,rpi-poe-fan";
- 				firmware = <&firmware>;
- 				cooling-min-state = <0>;
--				cooling-max-state = <3>;
-+				cooling-max-state = <2>;
- 				#cooling-cells = <2>;
--				cooling-levels = <0 50 150 255>;
-+				cooling-levels = <0 150 255>;
- 				status = "okay";
- 			};
- 		};
-@@ -26,35 +26,27 @@
- 		target = <&cpu_thermal>;
- 		__overlay__ {
- 			trips {
--				threshold: trip-point@0 {
--					temperature = <45000>;
--					hysteresis = <5000>;
--					type = "active";
--				};
--				target: trip-point@1 {
-+				trip0: trip0 {
- 					temperature = <50000>;
--					hysteresis = <2000>;
-+					hysteresis = <5000>;
- 					type = "active";
- 				};
--				cpu_hot: cpu_hot@0 {
-+				trip1: trip1 {
-+
- 					temperature = <55000>;
--					hysteresis = <2000>;
-+					hysteresis = <5000>;
- 					type = "active";
- 				};
- 			};
- 			cooling-maps {
- 				map0 {
--					trip = <&threshold>;
-+					trip = <&trip0>;
- 					cooling-device = <&fan0 0 1>;
- 				};
- 				map1 {
--					trip = <&target>;
-+					trip = <&trip1>;
- 					cooling-device = <&fan0 1 2>;
- 				};
--				map2 {
--					trip = <&cpu_hot>;
--					cooling-device = <&fan0 2 3>;
--				};
- 			};
- 		};
- 	};
diff --git a/target/linux/brcm2708/patches-4.14/950-0429-overlays-add-overrides-for-PoE-HAT-fan-control.patch b/target/linux/brcm2708/patches-4.14/950-0429-overlays-add-overrides-for-PoE-HAT-fan-control.patch
deleted file mode 100644
index c0d93511f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0429-overlays-add-overrides-for-PoE-HAT-fan-control.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From f7469d4973136acff2537c323a5377c217333bc8 Mon Sep 17 00:00:00 2001
-From: Serge Schneider <serge@raspberrypi.org>
-Date: Tue, 2 Oct 2018 17:13:48 +0100
-Subject: [PATCH 429/454] overlays: add overrides for PoE HAT fan control
-
-Signed-off-by: Serge Schneider <serge@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README              | 13 ++++++++++---
- arch/arm/boot/dts/overlays/rpi-poe-overlay.dts | 10 ++++++++++
- 2 files changed, 20 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1596,9 +1596,16 @@ Params: touchscreen-size-x      Touchscr
- 
- 
- Name:   rpi-poe
--Info:   Raspberry Pi POE HAT
--Load:   dtoverlay=rpi-poe
--Params: <None>
-+Info:   Raspberry Pi PoE HAT fan
-+Load:   dtoverlay=rpi-poe,<param>[=<val>]
-+Params: poe_fan_temp0           Temperature (in millicelcius) at which the fan
-+                                turns on (default 50000)
-+        poe_fan_temp0_hyst      Temperature delta (in millicelcius) at which
-+                                the fan turns off (default 5000)
-+        poe_fan_temp1           Temperature (in millicelcius) at which the fan
-+                                speeds up (default 55000)
-+        poe_fan_temp1_hyst      Temperature delta (in millicelcius) at which
-+                                the fan slows down (default 5000)
- 
- 
- Name:   rpi-proto
---- a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts
-@@ -50,4 +50,14 @@
- 			};
- 		};
- 	};
-+
-+	fragment@2 {
-+		target-path = "/__overrides__";
-+		__overlay__ {
-+			poe_fan_temp0 =		<&trip0>,"temperature:0";
-+			poe_fan_temp0_hyst =	<&trip0>,"hysteresis:0";
-+			poe_fan_temp1 =		<&trip1>,"temperature:0";
-+			poe_fan_temp1_hyst =	<&trip1>,"hysteresis:0";
-+		};
-+	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0430-overlays-Add-gpio-no-bank0-irq-overlay.patch b/target/linux/brcm2708/patches-4.14/950-0430-overlays-Add-gpio-no-bank0-irq-overlay.patch
deleted file mode 100644
index fc30b601f..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0430-overlays-Add-gpio-no-bank0-irq-overlay.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 01f0d0d45d28e7505e6f57bf09df3cf2ff079d5e Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 18 Jul 2018 17:25:00 +0100
-Subject: [PATCH 430/454] overlays: Add gpio-no-bank0-irq overlay
-
-See: https://github.com/raspberrypi/linux/issues/2590
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/Makefile                |  1 +
- arch/arm/boot/dts/overlays/README                  |  9 +++++++++
- .../dts/overlays/gpio-no-bank0-irq-overlay.dts     | 14 ++++++++++++++
- 3 files changed, 24 insertions(+)
- create mode 100755 arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -39,6 +39,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	gpio-ir.dtbo \
- 	gpio-ir-tx.dtbo \
- 	gpio-key.dtbo \
-+	gpio-no-bank0-irq.dtbo \
- 	gpio-no-irq.dtbo \
- 	gpio-poweroff.dtbo \
- 	gpio-shutdown.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -619,6 +619,15 @@ Params: gpio                    GPIO pin
-         keycode                 Set the key code for the button
- 
- 
-+Name:   gpio-no-bank0-irq
-+Info:   Use this overlay to disable GPIO interrupts for GPIOs in bank 0 (0-27),
-+        which can be useful for UIO drivers.
-+        N.B. Using this overlay will trigger a kernel WARN during booting, but
-+        this can safely be ignored - the system should work as expected.
-+Load:   dtoverlay=gpio-no-bank0-irq
-+Params: <None>
-+
-+
- Name:   gpio-no-irq
- Info:   Use this overlay to disable all GPIO interrupts, which can be useful
-         for user-space GPIO edge detection systems.
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts
-@@ -0,0 +1,14 @@
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835";
-+
-+	fragment@0 {
-+		// Configure the gpio pin controller
-+		target = <&gpio>;
-+		__overlay__ {
-+			    interrupts = <255 255>, <2 18>;
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0431-Add-hy28b-2017-model-device-tree-overlay-2721.patch b/target/linux/brcm2708/patches-4.14/950-0431-Add-hy28b-2017-model-device-tree-overlay-2721.patch
deleted file mode 100644
index 8b795562b..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0431-Add-hy28b-2017-model-device-tree-overlay-2721.patch
+++ /dev/null
@@ -1,209 +0,0 @@
-From a3d3b80d8a028e7cec393c02c1a96c5e632e7b30 Mon Sep 17 00:00:00 2001
-From: Hans-Wilhelm Warlo <5417271+hanswilw@users.noreply.github.com>
-Date: Tue, 16 Oct 2018 18:20:48 +0200
-Subject: [PATCH 431/454] Add hy28b 2017 model device tree overlay (#2721)
-
-The 2017 version of the hy28b display requires a different
-initialisation sequence.
-
-Signed-off-by: Hans-Wilhelm Warlo <hw@warlo.no>
----
- arch/arm/boot/dts/overlays/Makefile           |   1 +
- arch/arm/boot/dts/overlays/README             |  19 +++
- .../boot/dts/overlays/hy28b-2017-overlay.dts  | 152 ++++++++++++++++++
- 3 files changed, 172 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -51,6 +51,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	hifiberry-digi-pro.dtbo \
- 	hy28a.dtbo \
- 	hy28b.dtbo \
-+	hy28b-2017.dtbo \
- 	i2c-bcm2708.dtbo \
- 	i2c-gpio.dtbo \
- 	i2c-mux.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -792,6 +792,25 @@ Params: speed                   Display
-         ledgpio                 GPIO used to control backlight
- 
- 
-+Name:   hy28b-2017
-+Info:   HY28B 2017 version - 2.8" TFT LCD Display Module by HAOYU Electronics
-+        Default values match Texy's display shield
-+Load:   dtoverlay=hy28b-2017,<param>=<val>
-+Params: speed                   Display SPI bus speed
-+
-+        rotate                  Display rotation {0,90,180,270}
-+
-+        fps                     Delay between frame updates
-+
-+        debug                   Debug output level {0-7}
-+
-+        xohms                   Touchpanel sensitivity (X-plate resistance)
-+
-+        resetgpio               GPIO used to reset controller
-+
-+        ledgpio                 GPIO used to control backlight
-+
-+
- Name:   i2c-bcm2708
- Info:   Fall back to the i2c_bcm2708 driver for the i2c_arm bus.
- Load:   dtoverlay=i2c-bcm2708
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts
-@@ -0,0 +1,152 @@
-+/*
-+ * Device Tree overlay for HY28b display shield by Texy.
-+ * Modified for 2017 version with ILI9325 D chip
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev0>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@3 {
-+		target = <&gpio>;
-+		__overlay__ {
-+			hy28b_pins: hy28b_pins {
-+				brcm,pins = <17 25 18>;
-+				brcm,function = <0 1 1>; /* in out out */
-+			};
-+		};
-+	};
-+
-+	fragment@4 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			hy28b: hy28b@0{
-+				compatible = "ilitek,ili9325";
-+				reg = <0>;
-+				pinctrl-names = "default";
-+				pinctrl-0 = <&hy28b_pins>;
-+
-+				spi-max-frequency = <48000000>;
-+				spi-cpol;
-+				spi-cpha;
-+				rotate = <270>;
-+				bgr;
-+				fps = <50>;
-+				buswidth = <8>;
-+				startbyte = <0x70>;
-+				reset-gpios = <&gpio 25 0>;
-+				led-gpios = <&gpio 18 1>;
-+
-+				init = <0x10000e5 0x78F0
-+					0x1000001 0x0100
-+					0x1000002 0x0700
-+				        0x1000003 0x1030
-+					0x1000004 0x0000
-+					0x1000008 0x0207
-+					0x1000009 0x0000
-+				        0x100000a 0x0000
-+					0x100000c 0x0000
-+					0x100000d 0x0000
-+					0x100000f 0x0000
-+				        0x1000010 0x0000
-+					0x1000011 0x0007
-+					0x1000012 0x0000
-+					0x1000013 0x0000
-+					0x1000007 0x0001
-+				        0x2000032
-+				        0x2000032
-+				        0x2000032
-+				        0x2000032
-+					0x1000010 0x1090
-+					0x1000011 0x0227
-+				        0x2000032
-+					0x1000012 0x001f
-+				        0x2000032
-+				        0x1000013 0x1500
-+					0x1000029 0x0027
-+					0x100002b 0x000d
-+				        0x2000032
-+				        0x1000020 0x0000
-+					0x1000021 0x0000
-+				        0x2000032
-+					0x1000030 0x0000
-+					0x1000031 0x0707
-+					0x1000032 0x0307
-+					0x1000035 0x0200
-+					0x1000036 0x0008
-+					0x1000037 0x0004
-+					0x1000038 0x0000
-+					0x1000039 0x0707
-+					0x100003c 0x0002
-+					0x100003d 0x1d04
-+					0x1000050 0x0000
-+				        0x1000051 0x00ef
-+					0x1000052 0x0000
-+					0x1000053 0x013f
-+					0x1000060 0xa700
-+				        0x1000061 0x0001
-+					0x100006a 0x0000
-+					0x1000080 0x0000
-+					0x1000081 0x0000
-+				        0x1000082 0x0000
-+					0x1000083 0x0000
-+					0x1000084 0x0000
-+					0x1000085 0x0000
-+				        0x1000090 0x0010
-+					0x1000092 0x0600
-+					0x1000007 0x0133>;
-+				debug = <0>;
-+			};
-+
-+			hy28b_ts: hy28b-ts@1 {
-+				compatible = "ti,ads7846";
-+				reg = <1>;
-+
-+				spi-max-frequency = <2000000>;
-+				interrupts = <17 2>; /* high-to-low edge triggered */
-+				interrupt-parent = <&gpio>;
-+				pendown-gpio = <&gpio 17 0>;
-+				ti,x-plate-ohms = /bits/ 16 <100>;
-+				ti,pressure-max = /bits/ 16 <255>;
-+			};
-+		};
-+	};
-+	__overrides__ {
-+		speed = 	<&hy28b>,"spi-max-frequency:0";
-+		rotate = 	<&hy28b>,"rotate:0";
-+		fps = 		<&hy28b>,"fps:0";
-+		debug = 	<&hy28b>,"debug:0";
-+		xohms =		<&hy28b_ts>,"ti,x-plate-ohms;0";
-+		resetgpio =	<&hy28b>,"reset-gpios:4",
-+				<&hy28b_pins>, "brcm,pins:4";
-+		ledgpio =	<&hy28b>,"led-gpios:4",
-+				<&hy28b_pins>, "brcm,pins:8";
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0432-config-Add-CONFIG_USBIP_VUDC.patch b/target/linux/brcm2708/patches-4.14/950-0432-config-Add-CONFIG_USBIP_VUDC.patch
deleted file mode 100644
index 03acaf4d7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0432-config-Add-CONFIG_USBIP_VUDC.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From e93796935edc915e6c3578cb1f2f3014ae3b69a8 Mon Sep 17 00:00:00 2001
-From: popcornmix <popcornmix@gmail.com>
-Date: Thu, 25 Oct 2018 14:08:43 +0100
-Subject: [PATCH 432/454] config: Add CONFIG_USBIP_VUDC
-
-See: https://github.com/raspberrypi/firmware/issues/353
----
- arch/arm/configs/bcm2709_defconfig | 1 +
- arch/arm/configs/bcmrpi_defconfig  | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -1004,6 +1004,7 @@ CONFIG_USB_MICROTEK=m
- CONFIG_USBIP_CORE=m
- CONFIG_USBIP_VHCI_HCD=m
- CONFIG_USBIP_HOST=m
-+CONFIG_USBIP_VUDC=m
- CONFIG_USB_DWC2=m
- CONFIG_USB_SERIAL=m
- CONFIG_USB_SERIAL_GENERIC=y
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -997,6 +997,7 @@ CONFIG_USB_MICROTEK=m
- CONFIG_USBIP_CORE=m
- CONFIG_USBIP_VHCI_HCD=m
- CONFIG_USBIP_HOST=m
-+CONFIG_USBIP_VUDC=m
- CONFIG_USB_DWC2=m
- CONFIG_USB_SERIAL=m
- CONFIG_USB_SERIAL_GENERIC=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0433-mmc-bcm2835-sdhost-Recover-from-MMC_SEND_EXT_CSD.patch b/target/linux/brcm2708/patches-4.14/950-0433-mmc-bcm2835-sdhost-Recover-from-MMC_SEND_EXT_CSD.patch
deleted file mode 100644
index 8e9d036fa..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0433-mmc-bcm2835-sdhost-Recover-from-MMC_SEND_EXT_CSD.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 6191e47f23fe4fa13dfbb38dfdda12e567028963 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 26 Oct 2018 17:29:51 +0100
-Subject: [PATCH 433/454] mmc/bcm2835-sdhost: Recover from MMC_SEND_EXT_CSD
-
-If the user issues an "mmc extcsd read", the SD controller receives
-what it thinks is a SEND_IF_COND command with an unexpected data block.
-The resulting operations leave the FSM stuck in READWAIT, a state which
-persists until the MMC framework resets the controller, by which point
-the root filesystem is likely to have been unmounted.
-
-A less heavyweight solution is to detect the condition and nudge the
-FSM by asserting the (self-clearing) FORCE_DATA_MODE bit.
-
-N.B. This workaround was essentially discovered by accident and without
-a full understanding the inner workings of the controller, so it is
-fortunate that the "fix" only modifies error paths.
-
-See: https://github.com/raspberrypi/linux/issues/2728
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/mmc/host/bcm2835-sdhost.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/drivers/mmc/host/bcm2835-sdhost.c
-+++ b/drivers/mmc/host/bcm2835-sdhost.c
-@@ -1244,6 +1244,8 @@ static void bcm2835_sdhost_finish_comman
- 				pr_info("%s: ignoring CRC7 error for CMD1\n",
- 					mmc_hostname(host->mmc));
- 		} else {
-+			u32 edm, fsm;
-+
- 			if (sdhsts & SDHSTS_CMD_TIME_OUT) {
- 				if (host->debug)
- 					pr_warn("%s: command %d timeout\n",
-@@ -1256,6 +1258,13 @@ static void bcm2835_sdhost_finish_comman
- 				       host->cmd->opcode);
- 				host->cmd->error = -EILSEQ;
- 			}
-+
-+			edm = readl(host->ioaddr + SDEDM);
-+			fsm = edm & SDEDM_FSM_MASK;
-+			if (fsm == SDEDM_FSM_READWAIT ||
-+			    fsm == SDEDM_FSM_WRITESTART1)
-+				writel(edm | SDEDM_FORCE_DATA_MODE,
-+				       host->ioaddr + SDEDM);
- 			tasklet_schedule(&host->finish_tasklet);
- 			return;
- 		}
diff --git a/target/linux/brcm2708/patches-4.14/950-0434-mmc-bcm2835-Recover-from-MMC_SEND_EXT_CSD.patch b/target/linux/brcm2708/patches-4.14/950-0434-mmc-bcm2835-Recover-from-MMC_SEND_EXT_CSD.patch
deleted file mode 100644
index 9a9e81103..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0434-mmc-bcm2835-Recover-from-MMC_SEND_EXT_CSD.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From c2eae29f6503cf29ac6a204c51132cfed33d203e Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Fri, 26 Oct 2018 17:40:44 +0100
-Subject: [PATCH 434/454] mmc/bcm2835: Recover from MMC_SEND_EXT_CSD
-
-If the user issues an "mmc extcsd read", the SD controller receives
-what it thinks is a SEND_IF_COND command with an unexpected data block.
-The resulting operations leave the FSM stuck in READWAIT, a state which
-persists until the MMC framework resets the controller, by which point
-the root filesystem is likely to have been unmounted.
-
-A less heavyweight solution is to detect the condition and nudge the
-FSM by asserting the (self-clearing) FORCE_DATA_MODE bit.
-
-N.B. This workaround was essentially discovered by accident and without
-a full understanding the inner workings of the controller, so it is
-fortunate that the "fix" only modifies error paths.
-
-See: https://github.com/raspberrypi/linux/issues/2728
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/mmc/host/bcm2835.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/drivers/mmc/host/bcm2835.c
-+++ b/drivers/mmc/host/bcm2835.c
-@@ -772,6 +772,8 @@ static void bcm2835_finish_command(struc
- 
- 		if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
- 		    (host->cmd->opcode != MMC_SEND_OP_COND)) {
-+			u32 edm, fsm;
-+
- 			if (sdhsts & SDHSTS_CMD_TIME_OUT) {
- 				host->cmd->error = -ETIMEDOUT;
- 			} else {
-@@ -780,6 +782,13 @@ static void bcm2835_finish_command(struc
- 				bcm2835_dumpregs(host);
- 				host->cmd->error = -EILSEQ;
- 			}
-+			edm = readl(host->ioaddr + SDEDM);
-+			fsm = edm & SDEDM_FSM_MASK;
-+			if (fsm == SDEDM_FSM_READWAIT ||
-+			    fsm == SDEDM_FSM_WRITESTART1)
-+				/* Kick the FSM out of its wait */
-+				writel(edm | SDEDM_FORCE_DATA_MODE,
-+				       host->ioaddr + SDEDM);
- 			bcm2835_finish_request(host);
- 			return;
- 		}
diff --git a/target/linux/brcm2708/patches-4.14/950-0435-overlays-pi3-disable-bt-Clear-out-bt_pins-node.patch b/target/linux/brcm2708/patches-4.14/950-0435-overlays-pi3-disable-bt-Clear-out-bt_pins-node.patch
deleted file mode 100644
index 63131d61d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0435-overlays-pi3-disable-bt-Clear-out-bt_pins-node.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From ce45639ffb45059500a07261ea4099e955de4dd4 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 29 Oct 2018 10:38:31 +0000
-Subject: [PATCH 435/454] overlays: pi3-disable-bt: Clear out bt_pins node
-
-The pi3-disable-bt overlay does not (and cannot) delete the bt_pins
-node, but emptying its properties (including brcm,pins) is a way of
-signalling to the hciuart systemd service that Bluetooth has been
-disabled.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/pi3-disable-bt-overlay.dts | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm/boot/dts/overlays/pi3-disable-bt-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/pi3-disable-bt-overlay.dts
-@@ -37,6 +37,15 @@
- 	};
- 
- 	fragment@3 {
-+		target = <&bt_pins>;
-+		__overlay__ {
-+			brcm,pins;
-+			brcm,function;
-+			brcm,pull;
-+		};
-+	};
-+
-+	fragment@4 {
- 		target-path = "/aliases";
- 		__overlay__ {
- 			serial0 = "/soc/serial@7e201000";
diff --git a/target/linux/brcm2708/patches-4.14/950-0436-Revert-rtc-pcf8523-properly-handle-oscillator-stop-b.patch b/target/linux/brcm2708/patches-4.14/950-0436-Revert-rtc-pcf8523-properly-handle-oscillator-stop-b.patch
deleted file mode 100644
index b68cef69d..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0436-Revert-rtc-pcf8523-properly-handle-oscillator-stop-b.patch
+++ /dev/null
@@ -1,56 +0,0 @@
-From e37bc7714591ac7a94200ee254a116904e19b784 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 29 Oct 2018 14:45:45 +0000
-Subject: [PATCH 436/454] Revert "rtc: pcf8523: properly handle oscillator stop
- bit"
-
-This reverts commit ede44c908d44b166a5b6bd7caacd105c2ff5a70f.
-
-See: https://github.com/raspberrypi/firmware/issues/1065
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/rtc/rtc-pcf8523.c | 25 ++++++++++++++++++++++---
- 1 file changed, 22 insertions(+), 3 deletions(-)
-
---- a/drivers/rtc/rtc-pcf8523.c
-+++ b/drivers/rtc/rtc-pcf8523.c
-@@ -178,8 +178,28 @@ static int pcf8523_rtc_read_time(struct
- 	if (err < 0)
- 		return err;
- 
--	if (regs[0] & REG_SECONDS_OS)
--		return -EINVAL;
-+	if (regs[0] & REG_SECONDS_OS) {
-+		/*
-+		 * If the oscillator was stopped, try to clear the flag. Upon
-+		 * power-up the flag is always set, but if we cannot clear it
-+		 * the oscillator isn't running properly for some reason. The
-+		 * sensible thing therefore is to return an error, signalling
-+		 * that the clock cannot be assumed to be correct.
-+		 */
-+
-+		regs[0] &= ~REG_SECONDS_OS;
-+
-+		err = pcf8523_write(client, REG_SECONDS, regs[0]);
-+		if (err < 0)
-+			return err;
-+
-+		err = pcf8523_read(client, REG_SECONDS, &regs[0]);
-+		if (err < 0)
-+			return err;
-+
-+		if (regs[0] & REG_SECONDS_OS)
-+			return -EAGAIN;
-+	}
- 
- 	tm->tm_sec = bcd2bin(regs[0] & 0x7f);
- 	tm->tm_min = bcd2bin(regs[1] & 0x7f);
-@@ -215,7 +235,6 @@ static int pcf8523_rtc_set_time(struct d
- 		return err;
- 
- 	regs[0] = REG_SECONDS;
--	/* This will purposely overwrite REG_SECONDS_OS */
- 	regs[1] = bin2bcd(tm->tm_sec);
- 	regs[2] = bin2bcd(tm->tm_min);
- 	regs[3] = bin2bcd(tm->tm_hour);
diff --git a/target/linux/brcm2708/patches-4.14/950-0437-Update-issue-templates-2736.patch b/target/linux/brcm2708/patches-4.14/950-0437-Update-issue-templates-2736.patch
deleted file mode 100644
index b6df9a5bc..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0437-Update-issue-templates-2736.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 6bfc60a2c2b49067adc254c19045800621a34b4c Mon Sep 17 00:00:00 2001
-From: James Hughes <JamesH65@users.noreply.github.com>
-Date: Fri, 2 Nov 2018 11:55:49 +0000
-Subject: [PATCH 437/454] Update issue templates (#2736)
-
----
- .github/ISSUE_TEMPLATE/bug_report.md | 34 ++++++++++++++++++++++++++++
- 1 file changed, 34 insertions(+)
- create mode 100644 .github/ISSUE_TEMPLATE/bug_report.md
-
---- /dev/null
-+++ b/.github/ISSUE_TEMPLATE/bug_report.md
-@@ -0,0 +1,34 @@
-+---
-+name: Bug report
-+about: Create a report to help us fix your issue
-+
-+---
-+
-+**Is this the right place for my bug report?**
-+This repository contains the Linux kernel used on the Raspberry Pi. If you believe that the issue you are seeing is kernel-related, this is the right place. If not, we have other repositories for the GPU firmware at [github.com/raspberrypi/firmware](https://github.com/raspberrypi/firmware) and Raspberry Pi userland applications at [github.com/raspberrypi/userland](https://github.com/raspberrypi/userland). If you have problems with the Raspbian distribution packages, report them in the [github.com/RPi-Distro/repo](https://github.com/RPi-Distro/repo). If you simply have a question, then [the Raspberry Pi forums](https://www.raspberrypi.org/forums) are the best place to ask it.
-+
-+**Describe the bug**
-+Add a clear and concise description of what you think the bug is.
-+
-+**To reproduce**
-+List the steps required to reproduce the issue.
-+
-+**Expected behaviour**
-+Add a clear and concise description of what you expected to happen.
-+
-+**Actual behaviour**
-+Add a clear and concise description of what actually happened.
-+
-+**System**
-+ Copy and paste the results of the raspinfo command in to this section. Alternatively, copy and paste a pastebin link, or add answers to the following questions:
-+
-+* Which model of Raspberry Pi? e.g. Pi3B+, PiZeroW
-+* Which OS and version (`cat /etc/rpi-issue`)?
-+* Which firmware version (`vcgencmd version`)?
-+* Which kernel version (`uname -a`)?
-+
-+**Logs**
-+If applicable, add the relevant output from `dmesg` or similar.
-+
-+**Additional context**
-+Add any other relevant context for the problem.
diff --git a/target/linux/brcm2708/patches-4.14/950-0438-sc16is7xx-Don-t-spin-if-no-data-received.patch b/target/linux/brcm2708/patches-4.14/950-0438-sc16is7xx-Don-t-spin-if-no-data-received.patch
deleted file mode 100644
index dd7fd236c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0438-sc16is7xx-Don-t-spin-if-no-data-received.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 15cbb4515b766b5efc48bc53b1f83c4211c671a4 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 6 Nov 2018 12:57:48 +0000
-Subject: [PATCH 438/454] sc16is7xx: Don't spin if no data received
-
-See: https://github.com/raspberrypi/linux/issues/2676
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/tty/serial/sc16is7xx.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/tty/serial/sc16is7xx.c
-+++ b/drivers/tty/serial/sc16is7xx.c
-@@ -701,6 +701,8 @@ static bool sc16is7xx_port_irq(struct sc
- 			rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
- 			if (rxlen)
- 				sc16is7xx_handle_rx(port, rxlen, iir);
-+			else
-+				return false;
- 			break;
- 		case SC16IS7XX_IIR_THRI_SRC:
- 			sc16is7xx_handle_tx(port);
diff --git a/target/linux/brcm2708/patches-4.14/950-0439-overlays-uart0-return-GPIOs-14-and-15-to-inputs.patch b/target/linux/brcm2708/patches-4.14/950-0439-overlays-uart0-return-GPIOs-14-and-15-to-inputs.patch
deleted file mode 100644
index d5907d9b7..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0439-overlays-uart0-return-GPIOs-14-and-15-to-inputs.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 1edeed0e3a0961e9c15e66f8cc5764d043b45b03 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 7 Nov 2018 17:43:10 +0000
-Subject: [PATCH 439/454] overlays: uart0 - return GPIOs 14 and 15 to inputs
-
-In the event that alternate pins are used (only useful on Compute
-Modules), return the standard pins to inputs to avoid double-mapping
-them.
-
-See: https://www.raspberrypi.org/forums/viewtopic.php?p=1388713#p1316977
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/uart0-overlay.dts | 13 +++++++------
- 1 file changed, 7 insertions(+), 6 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/uart0-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/uart0-overlay.dts
-@@ -17,16 +17,17 @@
- 		target = <&gpio>;
- 		__overlay__ {
- 			uart0_pins: uart0_pins {
--				brcm,pins = <14 15>;
--				brcm,function = <4>; /* alt0 */
--				brcm,pull = <0 2>;
-+				brcm,pins = <14 15 14 15>;
-+				brcm,function = <0 0 4 4>; /* alt0 */
-+				brcm,pull = <0 0 0 2>;
- 			};
- 		};
- 	};
- 
- 	__overrides__ {
--		txd0_pin = <&uart0_pins>,"brcm,pins:0";
--		rxd0_pin = <&uart0_pins>,"brcm,pins:4";
--		pin_func = <&uart0_pins>,"brcm,function:0";
-+		txd0_pin = <&uart0_pins>,"brcm,pins:8";
-+		rxd0_pin = <&uart0_pins>,"brcm,pins:12";
-+		pin_func = <&uart0_pins>,"brcm,function:8",
-+			   <&uart0_pins>,"brcm,function:12";
- 	};
- };
diff --git a/target/linux/brcm2708/patches-4.14/950-0440-Update-README-2750.patch b/target/linux/brcm2708/patches-4.14/950-0440-Update-README-2750.patch
deleted file mode 100644
index 9ad349760..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0440-Update-README-2750.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 1338e5cc4b23a2215a881eccca6ca9009b29efdf Mon Sep 17 00:00:00 2001
-From: James Hughes <JamesH65@users.noreply.github.com>
-Date: Tue, 13 Nov 2018 16:51:21 +0000
-Subject: [PATCH 440/454] Update README (#2750)
-
-Small update to the DT blob docs to include the axiperf option.
-
-Signed-off-by: James Hughes <james.hughes@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/README | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -89,6 +89,11 @@ Params:
-         audio                   Set to "on" to enable the onboard ALSA audio
-                                 interface (default "off")
- 
-+        axiperf                 Set to "on" to enable the AXI bus performance
-+                                monitors.
-+                                See /sys/kernel/debug/raspberrypi_axi_monitor
-+                                for the results.
-+
-         eee                     Enable Energy Efficient Ethernet support for
-                                 compatible devices (default "on"). See also
-                                 "tx_lpi_timer".
diff --git a/target/linux/brcm2708/patches-4.14/950-0441-overlays-Remove-superfluous-address-size-cells.patch b/target/linux/brcm2708/patches-4.14/950-0441-overlays-Remove-superfluous-address-size-cells.patch
deleted file mode 100644
index a36143a33..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0441-overlays-Remove-superfluous-address-size-cells.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From 0d988407afff02574ed649ff6776a77d322bbe72 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Wed, 14 Nov 2018 09:53:25 +0000
-Subject: [PATCH 441/454] overlays: Remove superfluous #address/size-cells
-
-Newer versions of dtc warn about unnecessary usage of #address-cells
-and #size-cells, so remove them.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/overlays/adv7282m-overlay.dts | 4 ----
- arch/arm/boot/dts/overlays/ov5647-overlay.dts   | 4 ----
- arch/arm/boot/dts/overlays/tc358743-overlay.dts | 4 ----
- 3 files changed, 12 deletions(-)
-
---- a/arch/arm/boot/dts/overlays/adv7282m-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/adv7282m-overlay.dts
-@@ -34,13 +34,9 @@
- 	fragment@1 {
- 		target = <&csi1>;
- 		__overlay__ {
--			#address-cells = <1>;
--			#size-cells = <0>;
- 			status = "okay";
- 
- 			port {
--				#address-cells = <1>;
--				#size-cells = <0>;
- 				csi1_ep: endpoint {
- 					remote-endpoint = <&adv728x_0>;
- 				};
---- a/arch/arm/boot/dts/overlays/ov5647-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/ov5647-overlay.dts
-@@ -43,13 +43,9 @@
- 	fragment@1 {
- 		target = <&csi1>;
- 		__overlay__ {
--			#address-cells = <1>;
--			#size-cells = <0>;
- 			status = "okay";
- 
- 			port {
--				#address-cells = <1>;
--				#size-cells = <0>;
- 				csi1_ep: endpoint {
- 					remote-endpoint = <&ov5647_0>;
- 				};
---- a/arch/arm/boot/dts/overlays/tc358743-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/tc358743-overlay.dts
-@@ -42,13 +42,9 @@
- 	fragment@1 {
- 		target = <&csi1>;
- 		__overlay__ {
--			#address-cells = <1>;
--			#size-cells = <0>;
- 			status = "okay";
- 
- 			port {
--				#address-cells = <1>;
--				#size-cells = <0>;
- 				csi1_ep: endpoint {
- 					remote-endpoint = <&tc358743>;
- 				};
diff --git a/target/linux/brcm2708/patches-4.14/950-0442-vcsm-Fix-an-NULL-dereference-in-the-import_dmabuf-er.patch b/target/linux/brcm2708/patches-4.14/950-0442-vcsm-Fix-an-NULL-dereference-in-the-import_dmabuf-er.patch
deleted file mode 100644
index 9baa09c72..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0442-vcsm-Fix-an-NULL-dereference-in-the-import_dmabuf-er.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From dffde3390eb21fe0dc748a06894641a81d009b4e Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Wed, 14 Nov 2018 11:54:46 +0000
-Subject: [PATCH 442/454] vcsm: Fix an NULL dereference in the import_dmabuf
- error path
-
-resource was dereferenced even though it was NULL.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- drivers/char/broadcom/vc_sm/vmcs_sm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
-+++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
-@@ -2315,8 +2315,8 @@ int vc_sm_ioctl_import_dmabuf(struct sm_
- 	return 0;
- 
- error:
--	resource->res_stats[IMPORT_FAIL]++;
- 	if (resource) {
-+		resource->res_stats[IMPORT_FAIL]++;
- 		vc_sm_resource_deceased(resource, 1);
- 		kfree(resource);
- 	}
diff --git a/target/linux/brcm2708/patches-4.14/950-0443-net-lan78xx-Support-auto-downshift-to-100Mb-s.patch b/target/linux/brcm2708/patches-4.14/950-0443-net-lan78xx-Support-auto-downshift-to-100Mb-s.patch
deleted file mode 100644
index 4bdbd6eea..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0443-net-lan78xx-Support-auto-downshift-to-100Mb-s.patch
+++ /dev/null
@@ -1,126 +0,0 @@
-From 68502f802a66b68a6b5fefb52e709807a702a94b Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Mon, 26 Nov 2018 19:46:58 +0000
-Subject: [PATCH 443/454] net: lan78xx: Support auto-downshift to 100Mb/s
-
-Ethernet cables with faulty or missing pairs (specifically pairs C and
-D) allow auto-negotiation to 1000Mbs, but do not support the successful
-establishment of a link. Add a DT property, "microchip,downshift-after",
-to configure the number of auto-negotiation failures after which it
-falls back to 100Mbs. Valid values are 2, 3, 4, 5 and 0, where 0 means
-never downshift.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- drivers/net/phy/microchip.c  | 33 +++++++++++++++++++++++++++++++++
- drivers/net/usb/lan78xx.c    |  8 ++++++--
- include/linux/microchipphy.h | 11 +++++++++++
- 3 files changed, 50 insertions(+), 2 deletions(-)
-
---- a/drivers/net/phy/microchip.c
-+++ b/drivers/net/phy/microchip.c
-@@ -21,6 +21,7 @@
- #include <linux/phy.h>
- #include <linux/microchipphy.h>
- #include <linux/delay.h>
-+#include <linux/of.h>
- 
- #define DRIVER_AUTHOR	"WOOJUNG HUH <woojung.huh@microchip.com>"
- #define DRIVER_DESC	"Microchip LAN88XX PHY driver"
-@@ -225,6 +226,7 @@ static int lan88xx_probe(struct phy_devi
- {
- 	struct device *dev = &phydev->mdio.dev;
- 	struct lan88xx_priv *priv;
-+	u32 downshift_after = 0;
- 
- 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- 	if (!priv)
-@@ -232,6 +234,37 @@ static int lan88xx_probe(struct phy_devi
- 
- 	priv->wolopts = 0;
- 
-+	if (!of_property_read_u32(dev->of_node,
-+				  "microchip,downshift-after",
-+				  &downshift_after)) {
-+		u32 mask = LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK;
-+		u32 val = LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
-+
-+		switch (downshift_after) {
-+		case 2:
-+			val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2;
-+			break;
-+		case 3:
-+			val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3;
-+			break;
-+		case 4:
-+			val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4;
-+			break;
-+		case 5:
-+			val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5;
-+			break;
-+		case 0:
-+			/* Disable completely */
-+			mask = LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
-+			val = 0;
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		(void)phy_modify_paged(phydev, 1, LAN78XX_PHY_CTRL3,
-+				       mask, val);
-+	}
-+
- 	/* these values can be used to identify internal PHY */
- 	priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
- 	priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -36,7 +36,8 @@
- #include <linux/irq.h>
- #include <linux/irqchip/chained_irq.h>
- #include <linux/microchipphy.h>
--#include <linux/phy.h>
-+#include <linux/phy_fixed.h>
-+#include <linux/of_mdio.h>
- #include <linux/of_net.h>
- #include "lan78xx.h"
- 
-@@ -1763,6 +1764,7 @@ done:
- 
- static int lan78xx_mdio_init(struct lan78xx_net *dev)
- {
-+	struct device_node *node;
- 	int ret;
- 
- 	dev->mdiobus = mdiobus_alloc();
-@@ -1791,7 +1793,9 @@ static int lan78xx_mdio_init(struct lan7
- 		break;
- 	}
- 
--	ret = mdiobus_register(dev->mdiobus);
-+	node = of_get_child_by_name(dev->udev->dev.of_node, "mdio");
-+	ret = of_mdiobus_register(dev->mdiobus, node);
-+	of_node_put(node);
- 	if (ret) {
- 		netdev_err(dev->net, "can't register MDIO bus\n");
- 		goto exit1;
---- a/include/linux/microchipphy.h
-+++ b/include/linux/microchipphy.h
-@@ -70,6 +70,17 @@
- #define	LAN88XX_MMD3_CHIP_ID			(32877)
- #define	LAN88XX_MMD3_CHIP_REV			(32878)
- 
-+/* Registers specific to the LAN7800/LAN7850 embedded phy */
-+#define LAN78XX_PHY_LED_MODE_SELECT		(0x1D)
-+
-+#define LAN78XX_PHY_CTRL3			(0x14)
-+#define LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT	(0x0010)
-+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK	(0x000c)
-+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2	(0x0000)
-+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3	(0x0004)
-+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4	(0x0008)
-+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5	(0x000c)
-+
- /* DSP registers */
- #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG		(0x806A)
- #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_	(0x2000)
diff --git a/target/linux/brcm2708/patches-4.14/950-0444-ARM-dts-bcm283x-Set-downshift-after-for-Pi-3B.patch b/target/linux/brcm2708/patches-4.14/950-0444-ARM-dts-bcm283x-Set-downshift-after-for-Pi-3B.patch
deleted file mode 100644
index baa533f9e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0444-ARM-dts-bcm283x-Set-downshift-after-for-Pi-3B.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 671286dda990f9ca489f6dfac760b3468ad00f55 Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 27 Nov 2018 16:55:14 +0000
-Subject: [PATCH 444/454] ARM: dts: bcm283x: Set downshift-after for Pi 3B+
-
-Enable the auto-downshift feature on Raspberry Pi 3B+ so that a link
-can eventually be established using a cable with pairs C and/or D
-missing or broken in a 1000Mbps-capable port.
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
-+++ b/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
-@@ -27,6 +27,15 @@
- 				 * led1 = 6:link10/100/activity
- 				 */
- 				microchip,led-modes = <1 6>;
-+
-+				mdio {
-+					#address-cells = <0x1>;
-+					#size-cells = <0x0>;
-+					eth_phy: ethernet-phy@1 {
-+						reg = <1>;
-+						microchip,downshift-after = <2>;
-+					};
-+				};
- 			};
- 		};
- 	};
diff --git a/target/linux/brcm2708/patches-4.14/950-0445-BCM270X_DT-Add-new-Ethernet-DT-parameters.patch b/target/linux/brcm2708/patches-4.14/950-0445-BCM270X_DT-Add-new-Ethernet-DT-parameters.patch
deleted file mode 100644
index 94d8e09b1..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0445-BCM270X_DT-Add-new-Ethernet-DT-parameters.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From d4539512edd83737f51377e3e87512040133628a Mon Sep 17 00:00:00 2001
-From: Phil Elwell <phil@raspberrypi.org>
-Date: Tue, 27 Nov 2018 16:56:50 +0000
-Subject: [PATCH 445/454] BCM270X_DT: Add new Ethernet DT parameters
-
-Add "eth_downshift_after" DT parameter to allow the delay before the
-downshift to be specified. The default is 2 auto-negotiation cycles,
-and legal values are 2, 3, 4, 5 and 0 (disabled).
-
-Add "eth_max_speed" DT parameter as a way of prohibiting 1000Mbps
-links. This can be used to avoid the delay until the downshift mechanism
-activates. Legal values are 10, 100 and 1000, where the default is
-unlimited (effectively 1000Mbps).
-
-Signed-off-by: Phil Elwell <phil@raspberrypi.org>
----
- arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi | 2 ++
- arch/arm/boot/dts/overlays/README          | 9 +++++++++
- 2 files changed, 11 insertions(+)
-
---- a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
-+++ b/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
-@@ -48,5 +48,7 @@
- 		tx_lpi_timer = <&ethernet>,"microchip,tx-lpi-timer:0";
- 		eth_led0 = <&ethernet>,"microchip,led-modes:0";
- 		eth_led1 = <&ethernet>,"microchip,led-modes:4";
-+		eth_downshift_after = <&eth_phy>,"microchip,downshift-after:0";
-+		eth_max_speed = <&eth_phy>,"max-speed:0";
- 	};
- };
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -98,6 +98,11 @@ Params:
-                                 compatible devices (default "on"). See also
-                                 "tx_lpi_timer".
- 
-+        eth_downshift_after     Set the number of auto-negotiation failures
-+                                after which the 1000Mbps modes are disabled.
-+                                Legal values are 2, 3, 4, 5 and 0, where
-+                                0 means never downshift (default 2).
-+
-         eth_led0                Set mode of LED0 (usually orange) (default
-                                 "1"). The legal values are:
-                                 0=link/activity          1=link1000/activity
-@@ -108,6 +113,10 @@ Params:
-         eth_led1                Set mode of LED1 (usually green) (default
-                                 "6"). See eth_led0 for legal values.
- 
-+        eth_max_speed           Set the maximum speed a link is allowed
-+                                to negotiate. Legal values are 10, 100 and
-+                                1000 (default 1000).
-+
-         i2c_arm                 Set to "on" to enable the ARM's i2c interface
-                                 (default "off")
- 
diff --git a/target/linux/brcm2708/patches-4.14/950-0446-staging-bcm2835-camera-Fix-stride-on-RGB3-BGR3-forma.patch b/target/linux/brcm2708/patches-4.14/950-0446-staging-bcm2835-camera-Fix-stride-on-RGB3-BGR3-forma.patch
deleted file mode 100644
index 0e3442713..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0446-staging-bcm2835-camera-Fix-stride-on-RGB3-BGR3-forma.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 4660f99fbaa2836cd5f041c42c49c7d883cf5497 Mon Sep 17 00:00:00 2001
-From: Dave Stevenson <dave.stevenson@raspberrypi.org>
-Date: Fri, 30 Nov 2018 16:00:54 +0000
-Subject: [PATCH 446/454] staging: bcm2835-camera: Fix stride on RGB3/BGR3
- formats
-
-RGB3/BGR3 end up being 3 bytes per pixel, which meant that
-the alignment code ended up trying to align using bitmasking
-with a mask of 96.
-That doesn't work, so switch to an arithmetic alignment for
-those formats.
-
-Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
----
- .../bcm2835-camera/bcm2835-camera.c           | 26 ++++++++++++++-----
- 1 file changed, 20 insertions(+), 6 deletions(-)
-
---- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c
-@@ -1020,13 +1020,27 @@ static int vidioc_try_fmt_vid_cap(struct
- 			      1, 0);
- 	f->fmt.pix.bytesperline = f->fmt.pix.width * mfmt->ybbp;
- 	if (!mfmt->remove_padding) {
--		int align_mask = ((32 * mfmt->depth) >> 3) - 1;
--		/* GPU isn't removing padding, so stride is aligned to 32 */
--		f->fmt.pix.bytesperline =
--			(f->fmt.pix.bytesperline + align_mask) & ~align_mask;
-+		if (mfmt->depth == 24) {
-+			/*
-+			 * 24bpp is a pain as we can't use simple masking.
-+			 * Min stride is width aligned to 16, times 24bpp.
-+			 */
-+			f->fmt.pix.bytesperline =
-+				((f->fmt.pix.width + 15) & ~15) * 3;
-+		} else {
-+			/*
-+			 * GPU isn't removing padding, so stride is aligned to
-+			 * 32
-+			 */
-+			int align_mask = ((32 * mfmt->depth) >> 3) - 1;
-+
-+			f->fmt.pix.bytesperline =
-+				(f->fmt.pix.bytesperline + align_mask) &
-+							~align_mask;
-+		}
- 		v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
--			 "Not removing padding, so bytes/line = %d, (align_mask %d)\n",
--			 f->fmt.pix.bytesperline, align_mask);
-+			 "Not removing padding, so bytes/line = %d\n",
-+			 f->fmt.pix.bytesperline);
- 	}
- 
- 	/* Image buffer has to be padded to allow for alignment, even though
diff --git a/target/linux/brcm2708/patches-4.14/950-0447-tpm-Make-SECURITYFS-a-weak-dependency.patch b/target/linux/brcm2708/patches-4.14/950-0447-tpm-Make-SECURITYFS-a-weak-dependency.patch
deleted file mode 100644
index 3265cf99e..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0447-tpm-Make-SECURITYFS-a-weak-dependency.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From dc9be9a67256c7bafe4aa75d2033ce344e3f0409 Mon Sep 17 00:00:00 2001
-From: Peter Huewe <peterhuewe@gmx.de>
-Date: Mon, 3 Sep 2018 21:51:51 +0200
-Subject: [PATCH 447/454] tpm: Make SECURITYFS a weak dependency
-
-commit 2f7d8dbb11287cbe9da6380ca14ed5d38c9ed91f upstream.
-
-While having SECURITYFS enabled for the tpm subsystem is beneficial in
-most cases, it is not strictly necessary to have it enabled at all.
-Especially on platforms without any boot firmware integration of the TPM
-(e.g. raspberry pi) it does not add any value for the tpm subsystem,
-as there is no eventlog present.
-
-By turning it from 'select' to 'imply' it still gets selected per
-default, but enables users who want to save some kb of ram by turning
-SECURITYFS off.
-
-Signed-off-by: Peter Huewe <peterhuewe@gmx.de>
-Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
-Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
----
- drivers/char/tpm/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/char/tpm/Kconfig
-+++ b/drivers/char/tpm/Kconfig
-@@ -5,7 +5,7 @@
- menuconfig TCG_TPM
- 	tristate "TPM Hardware Support"
- 	depends on HAS_IOMEM
--	select SECURITYFS
-+	imply SECURITYFS
- 	select CRYPTO
- 	select CRYPTO_HASH_INFO
- 	---help---
diff --git a/target/linux/brcm2708/patches-4.14/950-0448-Enable-TPM-TIS-SPI-support-for-TPM1.2-and-TPM2.0-chi.patch b/target/linux/brcm2708/patches-4.14/950-0448-Enable-TPM-TIS-SPI-support-for-TPM1.2-and-TPM2.0-chi.patch
deleted file mode 100644
index 15915f27c..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0448-Enable-TPM-TIS-SPI-support-for-TPM1.2-and-TPM2.0-chi.patch
+++ /dev/null
@@ -1,106 +0,0 @@
-From 9bd7df848d7e683eb78637286a00af1c86dee361 Mon Sep 17 00:00:00 2001
-From: Peter Huewe <peterhuewe@gmx.de>
-Date: Thu, 14 Jun 2018 22:42:18 +0200
-Subject: [PATCH 448/454] Enable TPM TIS SPI support for TPM1.2 and TPM2.0
- chips
-
-This patch enables the support for SPI TPMs which follow the TCG TIS
-FIFO/PTP specification like the SLB9670.
-In order to decrease ram usage the weak dependency on CONFIG_SECURITFS
-is explictly set to 'n'.
-
-Signed-off-by: Peter Huewe <peterhuewe@gmx.de>
----
- arch/arm/configs/bcm2709_defconfig   |  3 +++
- arch/arm/configs/bcmrpi_defconfig    |  3 +++
- arch/arm64/configs/bcmrpi3_defconfig | 11 ++++++-----
- 3 files changed, 12 insertions(+), 5 deletions(-)
-
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -607,6 +607,8 @@ CONFIG_SERIAL_DEV_BUS=m
- CONFIG_TTY_PRINTK=y
- CONFIG_HW_RANDOM=y
- CONFIG_RAW_DRIVER=y
-+CONFIG_TCG_TPM=m
-+CONFIG_TCG_TIS_SPI=m
- CONFIG_I2C=y
- CONFIG_I2C_CHARDEV=m
- CONFIG_I2C_MUX_GPMUX=m
-@@ -1361,6 +1363,7 @@ CONFIG_FUNCTION_PROFILER=y
- CONFIG_KGDB=y
- CONFIG_KGDB_KDB=y
- CONFIG_KDB_KEYBOARD=y
-+# CONFIG_SECURITYFS is not set
- CONFIG_CRYPTO_USER=m
- CONFIG_CRYPTO_CBC=y
- CONFIG_CRYPTO_CTS=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -602,6 +602,8 @@ CONFIG_SERIAL_DEV_BUS=m
- CONFIG_TTY_PRINTK=y
- CONFIG_HW_RANDOM=y
- CONFIG_RAW_DRIVER=y
-+CONFIG_TCG_TPM=m
-+CONFIG_TCG_TIS_SPI=m
- CONFIG_I2C=y
- CONFIG_I2C_CHARDEV=m
- CONFIG_I2C_MUX_GPMUX=m
-@@ -1353,6 +1355,7 @@ CONFIG_FUNCTION_PROFILER=y
- CONFIG_KGDB=y
- CONFIG_KGDB_KDB=y
- CONFIG_KDB_KEYBOARD=y
-+# CONFIG_SECURITYFS is not set
- CONFIG_CRYPTO_USER=m
- CONFIG_CRYPTO_CRYPTD=m
- CONFIG_CRYPTO_CBC=y
---- a/arch/arm64/configs/bcmrpi3_defconfig
-+++ b/arch/arm64/configs/bcmrpi3_defconfig
-@@ -98,6 +98,8 @@ CONFIG_INET_XFRM_MODE_TRANSPORT=m
- CONFIG_INET_XFRM_MODE_TUNNEL=m
- CONFIG_INET_XFRM_MODE_BEET=m
- CONFIG_INET_DIAG=m
-+CONFIG_TCP_CONG_ADVANCED=y
-+CONFIG_TCP_CONG_BBR=m
- CONFIG_IPV6=m
- CONFIG_IPV6_ROUTER_PREF=y
- CONFIG_INET6_AH=m
-@@ -306,11 +308,9 @@ CONFIG_NET_SCH_CHOKE=m
- CONFIG_NET_SCH_QFQ=m
- CONFIG_NET_SCH_CODEL=m
- CONFIG_NET_SCH_FQ_CODEL=m
-+CONFIG_NET_SCH_FQ=m
- CONFIG_NET_SCH_INGRESS=m
- CONFIG_NET_SCH_PLUG=m
--CONFIG_NET_SCH_FQ=m
--CONFIG_TCP_CONG_ADVANCED=y
--CONFIG_TCP_CONG_BBR=m
- CONFIG_NET_CLS_BASIC=m
- CONFIG_NET_CLS_TCINDEX=m
- CONFIG_NET_CLS_ROUTE4=m
-@@ -586,6 +586,8 @@ CONFIG_SERIAL_DEV_BUS=m
- CONFIG_TTY_PRINTK=y
- CONFIG_HW_RANDOM=y
- CONFIG_RAW_DRIVER=y
-+CONFIG_TCG_TPM=m
-+CONFIG_TCG_TIS_SPI=m
- CONFIG_I2C=y
- CONFIG_I2C_CHARDEV=m
- CONFIG_I2C_MUX_PCA954x=m
-@@ -1265,6 +1267,7 @@ CONFIG_FUNCTION_PROFILER=y
- CONFIG_KGDB=y
- CONFIG_KGDB_KDB=y
- CONFIG_KDB_KEYBOARD=y
-+# CONFIG_SECURITYFS is not set
- CONFIG_CRYPTO_USER=m
- CONFIG_CRYPTO_CBC=y
- CONFIG_CRYPTO_CTS=m
-@@ -1277,8 +1280,6 @@ CONFIG_CRYPTO_DES=y
- CONFIG_CRYPTO_LZ4=m
- CONFIG_CRYPTO_USER_API_SKCIPHER=m
- CONFIG_ARM64_CRYPTO=y
--CONFIG_CRYPTO_AES_ARM64=m
- CONFIG_CRYPTO_AES_ARM64_BS=m
--CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m
- CONFIG_CRC_ITU_T=y
- CONFIG_LIBCRC32C=y
diff --git a/target/linux/brcm2708/patches-4.14/950-0449-Add-overlay-for-SLB9760-Iridium-LetsTrust-TPM.patch b/target/linux/brcm2708/patches-4.14/950-0449-Add-overlay-for-SLB9760-Iridium-LetsTrust-TPM.patch
deleted file mode 100644
index 70341f629..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0449-Add-overlay-for-SLB9760-Iridium-LetsTrust-TPM.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From 0e9dac6a2530f94fd8f3d195d929523536bc7ab2 Mon Sep 17 00:00:00 2001
-From: Peter Huewe <peterhuewe@gmx.de>
-Date: Thu, 14 Jun 2018 22:51:24 +0200
-Subject: [PATCH 449/454] Add overlay for SLB9760 Iridium /LetsTrust TPM
-
-Device Tree overlay for the Infineon SLB9670 Trusted Platform Module add-on
-boards, which can be used as a secure key storage and hwrng.
-available as "Iridium SLB9670" by Infineon and "LetsTrust TPM" by
-pi3g.
-
-Signed-off-by: Peter Huewe <peterhuewe@gmx.de>
----
- arch/arm/boot/dts/overlays/Makefile           |  1 +
- arch/arm/boot/dts/overlays/README             |  8 ++++
- .../boot/dts/overlays/tpm-slb9670-overlay.dts | 44 +++++++++++++++++++
- 3 files changed, 53 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts
-
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -138,6 +138,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
- 	tc358743.dtbo \
- 	tc358743-audio.dtbo \
- 	tinylcd35.dtbo \
-+	tpm-slb9670.dtbo \
- 	uart0.dtbo \
- 	uart1.dtbo \
- 	upstream.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -1994,6 +1994,14 @@ Params: speed                   Display
-                 dtoverlay=tinylcd35,touch,touchgpio=3
- 
- 
-+Name:   tpm-slb9670
-+Info:   Enables support for Infineon SLB9670 Trusted Platform Module add-on
-+        boards, which can be used as a secure key storage and hwrng,
-+        available as "Iridium SLB9670" by Infineon and "LetsTrust TPM" by pi3g.
-+Load:   dtoverlay=tpm-slb9670
-+Params: <None>
-+
-+
- Name:   uart0
- Info:   Change the pin usage of uart0
- Load:   dtoverlay=uart0,<param>=<val>
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts
-@@ -0,0 +1,44 @@
-+/*
-+ * Device Tree overlay for the Infineon SLB9670 Trusted Platform Module add-on
-+ * boards, which can be used as a secure key storage and hwrng.
-+ * available as "Iridium SLB9670" by Infineon and "LetsTrust TPM" by pi3g.
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
-+
-+	fragment@0 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&spidev1>;
-+		__overlay__ {
-+			status = "disabled";
-+		};
-+	};
-+
-+	fragment@2 {
-+		target = <&spi0>;
-+		__overlay__ {
-+			/* needed to avoid dtc warning */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			slb9670: slb9670@1 {
-+				compatible = "infineon,slb9670";
-+				reg = <1>;	/* CE1 */
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				spi-max-frequency = <32000000>;
-+				status = "okay";
-+			};
-+
-+		};
-+	};
-+};
diff --git a/target/linux/brcm2708/patches-4.14/950-0450-ASoC-add-driver-for-3Dlab-Nano-soundcard-2758.patch b/target/linux/brcm2708/patches-4.14/950-0450-ASoC-add-driver-for-3Dlab-Nano-soundcard-2758.patch
deleted file mode 100644
index 8e138f3cc..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0450-ASoC-add-driver-for-3Dlab-Nano-soundcard-2758.patch
+++ /dev/null
@@ -1,505 +0,0 @@
-From 09a4e02366e56076b344dd1fa14eea7618a11d5a Mon Sep 17 00:00:00 2001
-From: dev-3Dlab <45081440+dev-3Dlab@users.noreply.github.com>
-Date: Wed, 5 Dec 2018 10:59:11 +0100
-Subject: [PATCH 450/454] ASoC: add driver for 3Dlab Nano soundcard (#2758)
-
-Signed-off-by: GT <dev@3d-lab-av.com>
----
- .../overlays/3dlab-nano-player-overlay.dts    |  32 ++
- arch/arm/boot/dts/overlays/Makefile           |   1 +
- arch/arm/boot/dts/overlays/README             |   6 +
- arch/arm/configs/bcm2709_defconfig            |   1 +
- arch/arm/configs/bcmrpi_defconfig             |   1 +
- sound/soc/bcm/3dlab-nano-player.c             | 370 ++++++++++++++++++
- sound/soc/bcm/Kconfig                         |   6 +
- sound/soc/bcm/Makefile                        |   2 +
- 8 files changed, 419 insertions(+)
- create mode 100644 arch/arm/boot/dts/overlays/3dlab-nano-player-overlay.dts
- create mode 100644 sound/soc/bcm/3dlab-nano-player.c
-
---- /dev/null
-+++ b/arch/arm/boot/dts/overlays/3dlab-nano-player-overlay.dts
-@@ -0,0 +1,32 @@
-+// Definitions for 3Dlab Nano Player
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+	compatible = "brcm,bcm2708";
-+
-+	fragment@0 {
-+		target = <&i2s>;
-+		__overlay__ {
-+			status = "okay";
-+		};
-+	};
-+
-+	fragment@1 {
-+		target = <&i2c>;
-+		__overlay__ {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "okay";
-+
-+			nano-player@41 {
-+				compatible = "3dlab,nano-player";
-+				reg = <0x41>;
-+				i2s-controller = <&i2s>;
-+				status = "okay";
-+			};
-+		};
-+	};
-+};
-+
-+// EOF
---- a/arch/arm/boot/dts/overlays/Makefile
-+++ b/arch/arm/boot/dts/overlays/Makefile
-@@ -1,6 +1,7 @@
- # Overlays for the Raspberry Pi platform
- 
- dtbo-$(CONFIG_ARCH_BCM2835) += \
-+	3dlab-nano-player.dtbo \
- 	adau1977-adc.dtbo \
- 	adau7002-simple.dtbo \
- 	ads1015.dtbo \
---- a/arch/arm/boot/dts/overlays/README
-+++ b/arch/arm/boot/dts/overlays/README
-@@ -199,6 +199,12 @@ Params:
-         and the other i2c baudrate parameters.
- 
- 
-+Name:   3dlab-nano-player
-+Info:   Configures the 3Dlab Nano Player
-+Load:   dtoverlay=3dlab-nano-player
-+Params: <None>
-+
-+
- Name:   adau1977-adc
- Info:   Overlay for activation of ADAU1977 ADC codec over I2C for control
-         and I2S for data.
---- a/arch/arm/configs/bcm2709_defconfig
-+++ b/arch/arm/configs/bcm2709_defconfig
-@@ -889,6 +889,7 @@ CONFIG_SND_USB_6FIRE=m
- CONFIG_SND_USB_HIFACE=m
- CONFIG_SND_SOC=m
- CONFIG_SND_BCM2835_SOC_I2S=m
-+CONFIG_SND_BCM2708_SOC_3DLAB_NANO_PLAYER=m
- CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m
- CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
- CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
---- a/arch/arm/configs/bcmrpi_defconfig
-+++ b/arch/arm/configs/bcmrpi_defconfig
-@@ -882,6 +882,7 @@ CONFIG_SND_USB_6FIRE=m
- CONFIG_SND_USB_HIFACE=m
- CONFIG_SND_SOC=m
- CONFIG_SND_BCM2835_SOC_I2S=m
-+CONFIG_SND_BCM2708_SOC_3DLAB_NANO_PLAYER=m
- CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m
- CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
- CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
---- /dev/null
-+++ b/sound/soc/bcm/3dlab-nano-player.c
-@@ -0,0 +1,370 @@
-+/*
-+ * 3Dlab Nano Player ALSA SoC Audio driver.
-+ *
-+ * Copyright (C) 2018 3Dlab.
-+ *
-+ * Author: GT <dev@3d-lab-av.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * General Public License for more details.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/i2c.h>
-+#include <sound/soc.h>
-+#include <sound/pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/control.h>
-+
-+#define NANO_ID		0x00
-+#define NANO_VER	0x01
-+#define NANO_CFG	0x02
-+#define NANO_STATUS	0x03
-+#define NANO_SPI_ADDR	0x04
-+#define NANO_SPI_DATA	0x05
-+
-+#define NANO_ID_VAL	0x3D
-+#define NANO_CFG_OFF	0x00
-+#define NANO_CFG_MULT1	0
-+#define NANO_CFG_MULT2	1
-+#define NANO_CFG_MULT4	2
-+#define NANO_CFG_MULT8	3
-+#define NANO_CFG_MULT16	4
-+#define NANO_CFG_CLK22	0
-+#define NANO_CFG_CLK24	BIT(3)
-+#define NANO_CFG_DSD	BIT(4)
-+#define NANO_CFG_ENA	BIT(5)
-+#define NANO_CFG_BLINK	BIT(6)
-+#define NANO_STATUS_P1  BIT(0)
-+#define NANO_STATUS_P2  BIT(1)
-+#define NANO_STATUS_FLG BIT(2)
-+#define NANO_STATUS_CLK BIT(3)
-+#define NANO_SPI_READ	0
-+#define NANO_SPI_WRITE	BIT(5)
-+
-+#define NANO_DAC_CTRL1	0x00
-+#define NANO_DAC_CTRL2	0x01
-+#define NANO_DAC_CTRL3	0x02
-+#define NANO_DAC_LATT	0x03
-+#define NANO_DAC_RATT	0x04
-+
-+#define NANO_CTRL2_VAL	0x22
-+
-+static int nano_player_spi_write(struct regmap *map,
-+				 unsigned int reg, unsigned int val)
-+{
-+	/* indirect register access */
-+	regmap_write(map, NANO_SPI_DATA, val);
-+	regmap_write(map, NANO_SPI_ADDR, reg | NANO_SPI_WRITE);
-+	return 0;
-+}
-+
-+static int nano_player_ctrl_info(struct snd_kcontrol *kcontrol,
-+				 struct snd_ctl_elem_info *uinfo)
-+{
-+	/* describe control element */
-+	if (strstr(kcontrol->id.name, "Volume")) {
-+		uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
-+		uinfo->count = 1;
-+		uinfo->value.integer.min = 0;
-+		uinfo->value.integer.max = 100;
-+	} else {
-+		uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
-+		uinfo->count = 1;
-+		uinfo->value.integer.min = 0;
-+		uinfo->value.integer.max = 1;
-+	}
-+
-+	return 0;
-+}
-+
-+static int nano_player_ctrl_put(struct snd_kcontrol *kcontrol,
-+				struct snd_ctl_elem_value *ucontrol)
-+{
-+	/* program control value to hardware */
-+	struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
-+	struct regmap *regmap = snd_soc_card_get_drvdata(card);
-+
-+	if (strstr(kcontrol->id.name, "Volume")) {
-+		unsigned int vol = ucontrol->value.integer.value[0];
-+		unsigned int att = 255 - (2 * (100 - vol));
-+
-+		nano_player_spi_write(regmap, NANO_DAC_LATT, att);
-+		nano_player_spi_write(regmap, NANO_DAC_RATT, att);
-+		kcontrol->private_value = vol;
-+	} else {
-+		unsigned int mute = ucontrol->value.integer.value[0];
-+		unsigned int reg = NANO_CTRL2_VAL | mute;
-+
-+		nano_player_spi_write(regmap, NANO_DAC_CTRL2, reg);
-+		kcontrol->private_value = mute;
-+	}
-+	return 0;
-+}
-+
-+static int nano_player_ctrl_get(struct snd_kcontrol *kcontrol,
-+				struct snd_ctl_elem_value *ucontrol)
-+{
-+	/* return last programmed value */
-+	ucontrol->value.integer.value[0] = kcontrol->private_value;
-+	return 0;
-+}
-+
-+#define SOC_NANO_PLAYER_CTRL(xname) \
-+{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
-+	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
-+	.info = nano_player_ctrl_info, \
-+	.put = nano_player_ctrl_put, \
-+	.get = nano_player_ctrl_get }
-+
-+static const struct snd_kcontrol_new nano_player_controls[] = {
-+	SOC_NANO_PLAYER_CTRL("Master Playback Volume"),
-+	SOC_NANO_PLAYER_CTRL("Master Playback Switch"),
-+};
-+
-+static const unsigned int nano_player_rates[] = {
-+	44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000,
-+	705600, 768000 /* only possible with fast clocks */
-+};
-+
-+static struct snd_pcm_hw_constraint_list nano_player_constraint_rates = {
-+	.list	= nano_player_rates,
-+	.count	= ARRAY_SIZE(nano_player_rates),
-+};
-+
-+static int nano_player_init(struct snd_soc_pcm_runtime *rtd)
-+{
-+	struct snd_soc_card *card = rtd->card;
-+	struct regmap *regmap = snd_soc_card_get_drvdata(card);
-+	struct snd_soc_pcm_stream *cpu = &rtd->cpu_dai->driver->playback;
-+	struct snd_soc_pcm_stream *codec = &rtd->codec_dai->driver->playback;
-+	unsigned int sample_bits = 32;
-+	unsigned int val;
-+
-+	/* configure cpu dai */
-+	cpu->formats |= SNDRV_PCM_FMTBIT_DSD_U32_LE;
-+	cpu->rate_max = 768000;
-+
-+	/* configure dummy codec dai */
-+	codec->rate_min = 44100;
-+	codec->rates = SNDRV_PCM_RATE_KNOT;
-+	codec->formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_DSD_U32_LE;
-+
-+	/* configure max supported rate */
-+	regmap_read(regmap, NANO_STATUS, &val);
-+	if (val & NANO_STATUS_CLK) {
-+		dev_notice(card->dev, "Board with fast clocks installed\n");
-+		codec->rate_max = 768000;
-+	} else {
-+		dev_notice(card->dev, "Board with normal clocks installed\n");
-+		codec->rate_max = 384000;
-+	}
-+
-+	/* frame length enforced by hardware */
-+	return snd_soc_dai_set_bclk_ratio(rtd->cpu_dai, sample_bits * 2);
-+}
-+
-+static int nano_player_startup(struct snd_pcm_substream *substream)
-+{
-+	return snd_pcm_hw_constraint_list(substream->runtime, 0,
-+					  SNDRV_PCM_HW_PARAM_RATE,
-+					  &nano_player_constraint_rates);
-+}
-+
-+static int nano_player_hw_params(struct snd_pcm_substream *substream,
-+				 struct snd_pcm_hw_params *params)
-+{
-+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+	struct snd_soc_card *card = rtd->card;
-+	struct regmap *regmap = snd_soc_card_get_drvdata(card);
-+	unsigned int config = NANO_CFG_ENA;
-+	struct snd_mask *fmt;
-+
-+	/* configure PCM or DSD */
-+	fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
-+	if (snd_mask_test(fmt, SNDRV_PCM_FORMAT_DSD_U32_LE)) {
-+		/* embed DSD in PCM data */
-+		snd_mask_none(fmt);
-+		snd_mask_set(fmt, SNDRV_PCM_FORMAT_S32_LE);
-+		/* enable DSD mode */
-+		config |= NANO_CFG_DSD;
-+	}
-+
-+	/* configure clocks */
-+	switch (params_rate(params)) {
-+	case 44100:
-+		config |= NANO_CFG_MULT1 | NANO_CFG_CLK22;
-+		break;
-+	case 88200:
-+		config |= NANO_CFG_MULT2 | NANO_CFG_CLK22;
-+		break;
-+	case 176400:
-+		config |= NANO_CFG_MULT4 | NANO_CFG_CLK22;
-+		break;
-+	case 352800:
-+		config |= NANO_CFG_MULT8 | NANO_CFG_CLK22;
-+		break;
-+	case 705600:
-+		config |= NANO_CFG_MULT16 | NANO_CFG_CLK22;
-+		break;
-+	case 48000:
-+		config |= NANO_CFG_MULT1 | NANO_CFG_CLK24;
-+		break;
-+	case 96000:
-+		config |= NANO_CFG_MULT2 | NANO_CFG_CLK24;
-+		break;
-+	case 192000:
-+		config |= NANO_CFG_MULT4 | NANO_CFG_CLK24;
-+		break;
-+	case 384000:
-+		config |= NANO_CFG_MULT8 | NANO_CFG_CLK24;
-+		break;
-+	case 768000:
-+		config |= NANO_CFG_MULT16 | NANO_CFG_CLK24;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	dev_dbg(card->dev, "Send CFG register 0x%02X\n", config);
-+	return regmap_write(regmap, NANO_CFG, config);
-+}
-+
-+static struct snd_soc_ops nano_player_ops = {
-+	.startup	= nano_player_startup,
-+	.hw_params	= nano_player_hw_params,
-+};
-+
-+static struct snd_soc_dai_link nano_player_link = {
-+	.name		= "3Dlab Nano Player",
-+	.stream_name	= "3Dlab Nano Player HiFi",
-+	.platform_name	= "bcm2708-i2s.0",
-+	.cpu_dai_name	= "bcm2708-i2s.0",
-+	.codec_name	= "snd-soc-dummy",
-+	.codec_dai_name	= "snd-soc-dummy-dai",
-+	.dai_fmt	= SND_SOC_DAIFMT_I2S |
-+			  SND_SOC_DAIFMT_CONT |
-+			  SND_SOC_DAIFMT_NB_NF |
-+			  SND_SOC_DAIFMT_CBM_CFM,
-+	.init		= nano_player_init,
-+	.ops		= &nano_player_ops,
-+};
-+
-+static const struct regmap_config nano_player_regmap = {
-+	.reg_bits	= 8,
-+	.val_bits	= 8,
-+	.max_register	= 128,
-+	.cache_type	= REGCACHE_RBTREE,
-+};
-+
-+static int nano_player_card_probe(struct snd_soc_card *card)
-+{
-+	struct regmap *regmap = snd_soc_card_get_drvdata(card);
-+	unsigned int val;
-+
-+	/* check hardware integrity */
-+	regmap_read(regmap, NANO_ID, &val);
-+	if (val != NANO_ID_VAL) {
-+		dev_err(card->dev, "Invalid ID register 0x%02X\n", val);
-+		return -ENODEV;
-+	}
-+
-+	/* report version to the user */
-+	regmap_read(regmap, NANO_VER, &val);
-+	dev_notice(card->dev, "Started 3Dlab Nano Player driver (v%d)\n", val);
-+
-+	/* enable internal audio bus and blink status LED */
-+	return regmap_write(regmap, NANO_CFG, NANO_CFG_ENA | NANO_CFG_BLINK);
-+}
-+
-+static int nano_player_card_remove(struct snd_soc_card *card)
-+{
-+	/* disable internal audio bus */
-+	struct regmap *regmap = snd_soc_card_get_drvdata(card);
-+
-+	return regmap_write(regmap, NANO_CFG, NANO_CFG_OFF);
-+}
-+
-+static struct snd_soc_card nano_player_card = {
-+	.name		= "3Dlab_Nano_Player",
-+	.owner		= THIS_MODULE,
-+	.dai_link	= &nano_player_link,
-+	.num_links	= 1,
-+	.controls	= nano_player_controls,
-+	.num_controls	= ARRAY_SIZE(nano_player_controls),
-+	.probe		= nano_player_card_probe,
-+	.remove		= nano_player_card_remove,
-+};
-+
-+static int nano_player_i2c_probe(struct i2c_client *i2c,
-+				 const struct i2c_device_id *id)
-+{
-+	struct regmap *regmap;
-+	int ret;
-+
-+	regmap = devm_regmap_init_i2c(i2c, &nano_player_regmap);
-+	if (IS_ERR(regmap)) {
-+		ret = PTR_ERR(regmap);
-+		dev_err(&i2c->dev, "Failed to init regmap %d\n", ret);
-+		return ret;
-+	}
-+
-+	if (i2c->dev.of_node) {
-+		struct snd_soc_dai_link *dai = &nano_player_link;
-+		struct device_node *node;
-+
-+		/* cpu handle configured by device tree */
-+		node = of_parse_phandle(i2c->dev.of_node, "i2s-controller", 0);
-+		if (node) {
-+			dai->platform_name = NULL;
-+			dai->platform_of_node = node;
-+			dai->cpu_dai_name = NULL;
-+			dai->cpu_of_node = node;
-+		}
-+	}
-+
-+	nano_player_card.dev = &i2c->dev;
-+	snd_soc_card_set_drvdata(&nano_player_card, regmap);
-+	ret = devm_snd_soc_register_card(&i2c->dev, &nano_player_card);
-+
-+	if (ret && ret != -EPROBE_DEFER)
-+		dev_err(&i2c->dev, "Failed to register card %d\n", ret);
-+
-+	return ret;
-+}
-+
-+static const struct of_device_id nano_player_of_match[] = {
-+	{ .compatible = "3dlab,nano-player", },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, nano_player_of_match);
-+
-+static const struct i2c_device_id nano_player_i2c_id[] = {
-+	{ "nano-player", 0 },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(i2c, nano_player_i2c_id);
-+
-+static struct i2c_driver nano_player_i2c_driver = {
-+	.probe		= nano_player_i2c_probe,
-+	.id_table	= nano_player_i2c_id,
-+	.driver		= {
-+		.name		= "nano-player",
-+		.owner		= THIS_MODULE,
-+		.of_match_table	= nano_player_of_match,
-+	},
-+};
-+
-+module_i2c_driver(nano_player_i2c_driver);
-+
-+MODULE_DESCRIPTION("ASoC 3Dlab Nano Player driver");
-+MODULE_AUTHOR("GT <dev@3d-lab-av.com>");
-+MODULE_LICENSE("GPL v2");
-+
-+/* EOF */
---- a/sound/soc/bcm/Kconfig
-+++ b/sound/soc/bcm/Kconfig
-@@ -18,6 +18,12 @@ config SND_SOC_CYGNUS
- 
- 	  If you don't know what to do here, say N.
- 
-+config SND_BCM2708_SOC_3DLAB_NANO_PLAYER
-+	tristate "Support for 3Dlab Nano Player"
-+	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
-+	help
-+	  Say Y or M if you want to add support for 3Dlab Nano Player.
-+
- config SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD
- 	tristate "Support for Google voiceHAT soundcard"
- 	depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
---- a/sound/soc/bcm/Makefile
-+++ b/sound/soc/bcm/Makefile
-@@ -12,6 +12,7 @@ obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-
- snd-soc-googlevoicehat-codec-objs := googlevoicehat-codec.o
- 
- # BCM2708 Machine Support
-+snd-soc-3dlab-nano-player-objs := 3dlab-nano-player.o
- snd-soc-adau1977-adc-objs := adau1977-adc.o
- snd-soc-googlevoicehat-soundcard-objs := googlevoicehat-soundcard.o
- snd-soc-hifiberry-amp-objs := hifiberry_amp.o
-@@ -38,6 +39,7 @@ snd-soc-allo-katana-codec-objs := allo-k
- snd-soc-pisound-objs := pisound.o
- snd-soc-fe-pi-audio-objs := fe-pi-audio.o
- 
-+obj-$(CONFIG_SND_BCM2708_SOC_3DLAB_NANO_PLAYER) += snd-soc-3dlab-nano-player.o
- obj-$(CONFIG_SND_BCM2708_SOC_ADAU1977_ADC) += snd-soc-adau1977-adc.o
- obj-$(CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD) += snd-soc-googlevoicehat-soundcard.o
- obj-$(CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD)  += snd-soc-googlevoicehat-codec.o
diff --git a/target/linux/brcm2708/patches-4.14/950-0451-dtoverlays-fe-pi-audio-fix-sgtl5000-compatible-strin.patch b/target/linux/brcm2708/patches-4.14/950-0451-dtoverlays-fe-pi-audio-fix-sgtl5000-compatible-strin.patch
deleted file mode 100644
index e9b0d9cb0..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0451-dtoverlays-fe-pi-audio-fix-sgtl5000-compatible-strin.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 717b9761b68bf9e63e9041079bfd77a090af4bdd Mon Sep 17 00:00:00 2001
-From: Ben Wolsieffer <benwolsieffer@gmail.com>
-Date: Sun, 9 Dec 2018 16:46:00 -0500
-Subject: [PATCH 451/454] dtoverlays: fe-pi-audio: fix sgtl5000 compatible
- string
-
-The compatible string was set to "fepi,sgtl5000", which worked for some
-reason in 4.14, but does not work in 4.19, presumably due to some
-change in the kernel matching logic. The correct string is
-"fsl,sgtl5000".
-
-Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com>
----
- arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts
-+++ b/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts
-@@ -39,7 +39,7 @@
- 
- 			sgtl5000@0a {
- 				#sound-dai-cells = <0>;
--				compatible = "fepi,sgtl5000";
-+				compatible = "fsl,sgtl5000";
- 				reg = <0x0a>;
- 				clocks = <&sgtl5000_mclk>;
- 				micbias-resistor-k-ohms = <2>;
diff --git a/target/linux/brcm2708/patches-4.14/950-0452-bcm2835_smi-re-add-dereference-to-fix-DMA-transfers.patch b/target/linux/brcm2708/patches-4.14/950-0452-bcm2835_smi-re-add-dereference-to-fix-DMA-transfers.patch
deleted file mode 100644
index 2573ed530..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0452-bcm2835_smi-re-add-dereference-to-fix-DMA-transfers.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-From 1d967ce855045c54c5019419345a060365e02198 Mon Sep 17 00:00:00 2001
-From: Ezekiel Bethel <zek@9net.org>
-Date: Wed, 12 Dec 2018 19:11:13 +0000
-Subject: [PATCH 452/454] bcm2835_smi: re-add dereference to fix DMA transfers
-
----
- drivers/misc/bcm2835_smi.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/misc/bcm2835_smi.c
-+++ b/drivers/misc/bcm2835_smi.c
-@@ -879,7 +879,7 @@ static int bcm2835_smi_probe(struct plat
- 		goto err;
- 	}
- 	addr = of_get_address(node, 0, NULL, NULL);
--	inst->smi_regs_busaddr = be32_to_cpu(addr);
-+	inst->smi_regs_busaddr = be32_to_cpu(*addr);
- 
- 	err = bcm2835_smi_dma_setup(inst);
- 	if (err)
diff --git a/target/linux/brcm2708/patches-4.14/950-0454-lan78xx-Debounce-link-events-to-minimize-poll-storm.patch b/target/linux/brcm2708/patches-4.14/950-0454-lan78xx-Debounce-link-events-to-minimize-poll-storm.patch
deleted file mode 100644
index 1821616b9..000000000
--- a/target/linux/brcm2708/patches-4.14/950-0454-lan78xx-Debounce-link-events-to-minimize-poll-storm.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 44c28420145101c846b445b8ae6159400909f69f Mon Sep 17 00:00:00 2001
-From: Joshua Emele <jemele@acm.org>
-Date: Wed, 7 Nov 2018 16:07:40 -0800
-Subject: [PATCH 454/454] lan78xx: Debounce link events to minimize poll storm
-
-The bInterval is set to 4 (i.e. 8 microframes => 1ms) and the only bit
-that the driver pays attention to is "link was reset". If there's a
-flapping status bit in that endpoint data, (such as if PHY negotiation
-needs a few tries to get a stable link) then polling at a slower rate
-would act as a de-bounce.
-
-See: https://github.com/raspberrypi/linux/issues/2447
----
- drivers/net/usb/lan78xx.c | 12 +++++++++++-
- 1 file changed, 11 insertions(+), 1 deletion(-)
-
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -425,6 +425,11 @@ static bool enable_tso;
- module_param(enable_tso, bool, 0644);
- MODULE_PARM_DESC(enable_tso, "Enables TCP segmentation offload");
- 
-+#define INT_URB_MICROFRAMES_PER_MS	8
-+static int int_urb_interval_ms = 8;
-+module_param(int_urb_interval_ms, int, 0);
-+MODULE_PARM_DESC(int_urb_interval_ms, "Override usb interrupt urb interval");
-+
- static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)
- {
- 	u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
-@@ -3707,7 +3712,12 @@ static int lan78xx_probe(struct usb_inte
- 	dev->pipe_intr = usb_rcvintpipe(dev->udev,
- 					dev->ep_intr->desc.bEndpointAddress &
- 					USB_ENDPOINT_NUMBER_MASK);
--	period = dev->ep_intr->desc.bInterval;
-+	if (int_urb_interval_ms <= 0)
-+		period = dev->ep_intr->desc.bInterval;
-+	else
-+		period = int_urb_interval_ms * INT_URB_MICROFRAMES_PER_MS;
-+
-+	netif_notice(dev, probe, netdev, "int urb period %d\n", period);
- 
- 	maxp = usb_maxpacket(dev->udev, dev->pipe_intr, 0);
- 	buf = kmalloc(maxp, GFP_KERNEL);
diff --git a/target/linux/brcm2708/patches-4.14/960-add-rasbperrypi-compatible.patch b/target/linux/brcm2708/patches-4.14/960-add-rasbperrypi-compatible.patch
deleted file mode 100644
index 8a95eb11b..000000000
--- a/target/linux/brcm2708/patches-4.14/960-add-rasbperrypi-compatible.patch
+++ /dev/null
@@ -1,51 +0,0 @@
---- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
-+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts
-@@ -5,6 +5,7 @@
- #include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
-+	compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
- 	model = "Raspberry Pi Model B+";
- };
- 
---- a/arch/arm/boot/dts/bcm2708-rpi-b.dts
-+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts
-@@ -5,6 +5,7 @@
- #include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
-+	compatible = "raspberrypi,model-b", "brcm,bcm2835";
- 	model = "Raspberry Pi Model B";
- };
- 
---- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts
-+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts
-@@ -5,6 +5,7 @@
- #include "bcm283x-rpi-csi1-4lane.dtsi"
- 
- / {
-+	compatible = "raspberrypi,compute-module", "brcm,bcm2835";
- 	model = "Raspberry Pi Compute Module";
- };
- 
---- a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts
-@@ -5,7 +5,7 @@
- #include "bcm283x-rpi-csi1-2lane.dtsi"
- 
- / {
--	compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
-+	compatible = "raspberrypi,3-model-b", "brcm,bcm2837", "brcm,bcm2836";
- 	model = "Raspberry Pi 3 Model B";
- 
- 	chosen {
---- a/arch/arm/boot/dts/bcm2710-rpi-cm3.dts
-+++ b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts
-@@ -5,6 +5,7 @@
- #include "bcm283x-rpi-csi1-4lane.dtsi"
- 
- / {
-+	compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
- 	model = "Raspberry Pi Compute Module 3";
- };
- 
diff --git a/target/linux/brcm2708/patches-4.14/961-lan78xx-enable-LED.patch b/target/linux/brcm2708/patches-4.14/961-lan78xx-enable-LED.patch
deleted file mode 100644
index ae09e0833..000000000
--- a/target/linux/brcm2708/patches-4.14/961-lan78xx-enable-LED.patch
+++ /dev/null
@@ -1,18 +0,0 @@
---- a/drivers/net/usb/lan78xx.c
-+++ b/drivers/net/usb/lan78xx.c
-@@ -2458,6 +2458,15 @@ static int lan78xx_reset(struct lan78xx_
- 
- 	ret = lan78xx_read_reg(dev, HW_CFG, &buf);
- 	buf |= HW_CFG_MEF_;
-+	if (dev->chipid == ID_REV_CHIP_ID_7800_) {
-+		ret = lan78xx_read_raw_eeprom(dev, 0, 1, &sig);
-+		if (!ret && sig != EEPROM_INDICATOR) {
-+			/* Implies there is no external eeprom. Enable LEDS */
-+			netdev_info(dev->net,
-+				    "No External EEPROM. Enabling LEDS\n");
-+			buf |= HW_CFG_LED0_EN_ | HW_CFG_LED1_EN_;
-+		}
-+	}
- 	ret = lan78xx_write_reg(dev, HW_CFG, buf);
- 
- 	ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
diff --git a/target/linux/cns3xxx/patches-4.14/060-pcie_abort.patch b/target/linux/cns3xxx/patches-4.14/060-pcie_abort.patch
index b5f035057..7a3a8e4c2 100644
--- a/target/linux/cns3xxx/patches-4.14/060-pcie_abort.patch
+++ b/target/linux/cns3xxx/patches-4.14/060-pcie_abort.patch
@@ -1,7 +1,7 @@
 --- a/arch/arm/mach-cns3xxx/pcie.c
 +++ b/arch/arm/mach-cns3xxx/pcie.c
 @@ -86,6 +86,79 @@ static void __iomem *cns3xxx_pci_map_bus
- 	return base + where + (devfn << 12);
+ 	return base + (where & 0xffc) + (devfn << 12);
  }
  
 +static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where)
diff --git a/target/linux/generic/backport-4.14/047-v4.21-mtd-keep-original-flags-for-every-struct-mtd_info.patch b/target/linux/generic/backport-4.14/047-v4.21-mtd-keep-original-flags-for-every-struct-mtd_info.patch
deleted file mode 100644
index 7f90cf946..000000000
--- a/target/linux/generic/backport-4.14/047-v4.21-mtd-keep-original-flags-for-every-struct-mtd_info.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From 1186af457cc186c5ed01708da71b1ffbdf0a2638 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 20 Nov 2018 09:55:45 +0100
-Subject: [PATCH] mtd: keep original flags for every struct mtd_info
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-When allocating a new partition mtd subsystem runs internal tests in the
-allocate_partition(). They may result in modifying specified flags (e.g.
-dropping some /features/ like write access).
-
-Those constraints don't have to be necessary true for subpartitions. It
-may happen parent partition isn't block aligned (effectively disabling
-write access) while subpartition may fit blocks nicely. In such case all
-checks should be run again (starting with original flags value).
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
----
- drivers/mtd/mtdcore.c   | 2 ++
- drivers/mtd/mtdpart.c   | 3 ++-
- include/linux/mtd/mtd.h | 1 +
- 3 files changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/mtdcore.c
-+++ b/drivers/mtd/mtdcore.c
-@@ -650,6 +650,8 @@ static void mtd_set_dev_defaults(struct
- 	} else {
- 		pr_debug("mtd device won't show a device symlink in sysfs\n");
- 	}
-+
-+	mtd->orig_flags = mtd->flags;
- }
- 
- /**
---- a/drivers/mtd/mtdpart.c
-+++ b/drivers/mtd/mtdpart.c
-@@ -394,7 +394,8 @@ static struct mtd_part *allocate_partiti
- 
- 	/* set up the MTD object for this partition */
- 	slave->mtd.type = parent->type;
--	slave->mtd.flags = parent->flags & ~part->mask_flags;
-+	slave->mtd.flags = parent->orig_flags & ~part->mask_flags;
-+	slave->mtd.orig_flags = slave->mtd.flags;
- 	slave->mtd.size = part->size;
- 	slave->mtd.writesize = parent->writesize;
- 	slave->mtd.writebufsize = parent->writebufsize;
---- a/include/linux/mtd/mtd.h
-+++ b/include/linux/mtd/mtd.h
-@@ -218,6 +218,7 @@ struct mtd_debug_info {
- struct mtd_info {
- 	u_char type;
- 	uint32_t flags;
-+	uint32_t orig_flags; /* Flags as before running mtd checks */
- 	uint64_t size;	 // Total size of the MTD
- 
- 	/* "Major" erase size for the device. Naïve users may take this
diff --git a/target/linux/generic/backport-4.14/048-v4.21-mtd-improve-calculating-partition-boundaries-when-ch.patch b/target/linux/generic/backport-4.14/048-v4.21-mtd-improve-calculating-partition-boundaries-when-ch.patch
deleted file mode 100644
index 58163e693..000000000
--- a/target/linux/generic/backport-4.14/048-v4.21-mtd-improve-calculating-partition-boundaries-when-ch.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 6750f61a13a0197c40e4a40739117493b15f19e8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 20 Nov 2018 10:24:09 +0100
-Subject: [PATCH] mtd: improve calculating partition boundaries when checking
- for alignment
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-When checking for alignment mtd should check absolute offsets. It's
-important for subpartitions as it doesn't make sense to check their
-relative addresses.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
----
- drivers/mtd/mtdpart.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/mtdpart.c
-+++ b/drivers/mtd/mtdpart.c
-@@ -61,6 +61,15 @@ static inline struct mtd_part *mtd_to_pa
- 	return container_of(mtd, struct mtd_part, mtd);
- }
- 
-+static u64 part_absolute_offset(struct mtd_info *mtd)
-+{
-+	struct mtd_part *part = mtd_to_part(mtd);
-+
-+	if (!mtd_is_partition(mtd))
-+		return 0;
-+
-+	return part_absolute_offset(part->parent) + part->offset;
-+}
- 
- /*
-  * MTD methods which simply translate the effective address and pass through
-@@ -562,7 +571,7 @@ static struct mtd_part *allocate_partiti
- 	if (!(slave->mtd.flags & MTD_NO_ERASE))
- 		wr_alignment = slave->mtd.erasesize;
- 
--	tmp = slave->offset;
-+	tmp = part_absolute_offset(parent) + slave->offset;
- 	remainder = do_div(tmp, wr_alignment);
- 	if ((slave->mtd.flags & MTD_WRITEABLE) && remainder) {
- 		/* Doesn't start on a boundary of major erase size */
-@@ -573,7 +582,7 @@ static struct mtd_part *allocate_partiti
- 			part->name);
- 	}
- 
--	tmp = slave->mtd.size;
-+	tmp = part_absolute_offset(parent) + slave->mtd.size;
- 	remainder = do_div(tmp, wr_alignment);
- 	if ((slave->mtd.flags & MTD_WRITEABLE) && remainder) {
- 		slave->mtd.flags &= ~MTD_WRITEABLE;
diff --git a/target/linux/generic/backport-4.14/095-Allow-class-e-address-assignment-via-ifconfig-ioctl.patch b/target/linux/generic/backport-4.14/095-Allow-class-e-address-assignment-via-ifconfig-ioctl.patch
deleted file mode 100644
index fec083dad..000000000
--- a/target/linux/generic/backport-4.14/095-Allow-class-e-address-assignment-via-ifconfig-ioctl.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 46bf067870156abd61fe24d14c2486d15b8b502c Mon Sep 17 00:00:00 2001
-From: Dave Taht <dave@taht.net>
-Date: Fri, 14 Dec 2018 18:38:40 +0000
-Subject: [PATCH 1/1] Allow class-e address assignment in ifconfig and early
- boot
-
-While the linux kernel became mostly "class-e clean" a decade ago,
-and most distributions long ago switched to the iproute2 suite
-of utilities, which allow class-e (240.0.0.0/4) address assignment,
-distributions relying on busybox, toybox and other forms of
-ifconfig cannot assign class-e addresses without this kernel patch.
-
-With this patch, also, a boot command line on these addresses is feasible:
-(ip=248.0.1.2::248.0.1.1:255.255.255.0).
-
-While CIDR has been obsolete for 2 decades, and a survey of all the
-userspace open source code in the world shows most IN_whatever macros
-are also obsolete... rather than obsolete CIDR from this ioctl entirely,
-this patch merely enables class-e assignment, sanely.
-
-H/T to Vince Fuller and his original patch here:
-    https://lkml.org/lkml/2008/1/7/370
-
-Signed-off-by: Dave Taht <dave.taht@gmail.com>
-Reviewed-by: John Gilmore <gnu@toad.com>
----
- include/uapi/linux/in.h | 8 ++++++--
- net/ipv4/devinet.c      | 4 +++-
- net/ipv4/ipconfig.c     | 2 ++
- 3 files changed, 11 insertions(+), 3 deletions(-)
-
---- a/include/uapi/linux/in.h
-+++ b/include/uapi/linux/in.h
-@@ -268,8 +268,12 @@ struct sockaddr_in {
- #define	IN_MULTICAST(a)		IN_CLASSD(a)
- #define IN_MULTICAST_NET	0xF0000000
- 
--#define	IN_EXPERIMENTAL(a)	((((long int) (a)) & 0xf0000000) == 0xf0000000)
--#define	IN_BADCLASS(a)		IN_EXPERIMENTAL((a))
-+#define	IN_BADCLASS(a)		((((long int) (a) ) == 0xffffffff)
-+#define	IN_EXPERIMENTAL(a)	IN_BADCLASS((a))
-+
-+#define	IN_CLASSE(a)		((((long int) (a)) & 0xf0000000) == 0xf0000000)
-+#define	IN_CLASSE_NET		0xffffffff
-+#define	IN_CLASSE_NSHIFT	0
- 
- /* Address to accept any incoming messages. */
- #define	INADDR_ANY		((unsigned long int) 0x00000000)
---- a/net/ipv4/devinet.c
-+++ b/net/ipv4/devinet.c
-@@ -921,7 +921,7 @@ static int inet_abc_len(__be32 addr)
- {
- 	int rc = -1;	/* Something else, probably a multicast. */
- 
--	if (ipv4_is_zeronet(addr))
-+	if (ipv4_is_zeronet(addr) || ipv4_is_lbcast(addr))
- 		rc = 0;
- 	else {
- 		__u32 haddr = ntohl(addr);
-@@ -932,6 +932,8 @@ static int inet_abc_len(__be32 addr)
- 			rc = 16;
- 		else if (IN_CLASSC(haddr))
- 			rc = 24;
-+		else if (IN_CLASSE(haddr))
-+			rc = 32;
- 	}
- 
- 	return rc;
---- a/net/ipv4/ipconfig.c
-+++ b/net/ipv4/ipconfig.c
-@@ -457,6 +457,8 @@ static int __init ic_defaults(void)
- 			ic_netmask = htonl(IN_CLASSB_NET);
- 		else if (IN_CLASSC(ntohl(ic_myaddr)))
- 			ic_netmask = htonl(IN_CLASSC_NET);
-+		else if (IN_CLASSE(ntohl(ic_myaddr)))
-+			ic_netmask = htonl(IN_CLASSE_NET);
- 		else {
- 			pr_err("IP-Config: Unable to guess netmask for address %pI4\n",
- 			       &ic_myaddr);
diff --git a/target/linux/generic/backport-4.14/100-arm-cns3xxx-fix-writing-to-wrong-PCI-registers-after.patch b/target/linux/generic/backport-4.14/100-arm-cns3xxx-fix-writing-to-wrong-PCI-registers-after.patch
deleted file mode 100644
index faeb3e417..000000000
--- a/target/linux/generic/backport-4.14/100-arm-cns3xxx-fix-writing-to-wrong-PCI-registers-after.patch
+++ /dev/null
@@ -1,74 +0,0 @@
-From 03556dab1cb02d85b50d7be3ee3a3bac001f5991 Mon Sep 17 00:00:00 2001
-From: Koen Vandeputte <koen.vandeputte@ncentric.com>
-Date: Tue, 18 Dec 2018 12:14:06 +0100
-Subject: [PATCH] arm: cns3xxx: fix writing to wrong PCI registers after
- alignment
-
-Originally, cns3xxx used it's own functions for mapping, reading and writing registers.
-
-Commit 802b7c06adc7 ("ARM: cns3xxx: Convert PCI to use generic config accessors")
-removed the internal PCI config write function in favor of the generic one:
-
-cns3xxx_pci_write_config() --> pci_generic_config_write()
-
-cns3xxx_pci_write_config() expected aligned addresses, being produced by cns3xxx_pci_map_bus()
-while the generic one pci_generic_config_write() actually expects the real address
-as both the function and hardware are capable of byte-aligned writes.
-
-This currently leads to pci_generic_config_write() writing
-to the wrong registers on some ocasions.
-
-First issue seen due to this:
-
-- driver ath9k gets loaded
-- The driver wants to write value 0xA8 to register PCI_LATENCY_TIMER, located at 0x0D
-- cns3xxx_pci_map_bus() aligns the address to 0x0C
-- pci_generic_config_write() effectively writes 0xA8 into register 0x0C (CACHE_LINE_SIZE)
-
-This seems to cause some slight instability when certain PCI devices are used.
-
-Another issue example caused by this this is the PCI bus numbering,
-where the primary bus is higher than the secondary, which is impossible.
-
-Before:
-
-00:00.0 PCI bridge: Cavium, Inc. Device 3400 (rev 01) (prog-if 00 [Normal decode])
-    Flags: bus master, fast devsel, latency 0, IRQ 255
-    Bus: primary=02, secondary=01, subordinate=ff, sec-latency=0
-
-After fix:
-
-00:00.0 PCI bridge: Cavium, Inc. Device 3400 (rev 01) (prog-if 00 [Normal decode])
-    Flags: bus master, fast devsel, latency 0, IRQ 255
-    Bus: primary=00, secondary=01, subordinate=02, sec-latency=0
-
-And very likely some more ..
-
-Fix all by omitting the alignment being done in the mapping function.
-
-Fixes: 802b7c06adc7 ("ARM: cns3xxx: Convert PCI to use generic config accessors")
-Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
-CC: Arnd Bergmann <arnd@arndb.de>
-CC: Bjorn Helgaas <bhelgaas@google.com>
-CC: Krzysztof Halasa <khalasa@piap.pl>
-CC: Olof Johansson <olof@lixom.net>
-CC: Robin Leblon <robin.leblon@ncentric.com>
-CC: Rob Herring <robh@kernel.org>
-CC: Russell King <linux@armlinux.org.uk>
-CC: Tim Harvey <tharvey@gateworks.com>
-CC: stable@vger.kernel.org # v4.0+
----
- arch/arm/mach-cns3xxx/pcie.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -83,7 +83,7 @@ static void __iomem *cns3xxx_pci_map_bus
- 	} else /* remote PCI bus */
- 		base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
- 
--	return base + (where & 0xffc) + (devfn << 12);
-+	return base + where + (devfn << 12);
- }
- 
- static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
diff --git a/target/linux/generic/backport-4.14/304-v4.16-netfilter-move-checksum-indirection-to-struct-nf_ipv.patch b/target/linux/generic/backport-4.14/304-v4.16-netfilter-move-checksum-indirection-to-struct-nf_ipv.patch
index a73256a2c..458ddd417 100644
--- a/target/linux/generic/backport-4.14/304-v4.16-netfilter-move-checksum-indirection-to-struct-nf_ipv.patch
+++ b/target/linux/generic/backport-4.14/304-v4.16-netfilter-move-checksum-indirection-to-struct-nf_ipv.patch
@@ -116,7 +116,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  	.saveroute		= nf_ip_saveroute,
 --- a/net/ipv6/netfilter.c
 +++ b/net/ipv6/netfilter.c
-@@ -194,12 +194,12 @@ static __sum16 nf_ip6_checksum_partial(s
+@@ -193,12 +193,12 @@ static __sum16 nf_ip6_checksum_partial(s
  static const struct nf_ipv6_ops ipv6ops = {
  	.chk_addr	= ipv6_chk_addr,
  	.route_input    = ip6_route_input,
diff --git a/target/linux/generic/backport-4.14/305-v4.16-netfilter-move-checksum_partial-indirection-to-struc.patch b/target/linux/generic/backport-4.14/305-v4.16-netfilter-move-checksum_partial-indirection-to-struc.patch
index 6ef092825..19a0aacb4 100644
--- a/target/linux/generic/backport-4.14/305-v4.16-netfilter-move-checksum_partial-indirection-to-struc.patch
+++ b/target/linux/generic/backport-4.14/305-v4.16-netfilter-move-checksum_partial-indirection-to-struc.patch
@@ -151,7 +151,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  	.reroute		= nf_ip_reroute,
 --- a/net/ipv6/netfilter.c
 +++ b/net/ipv6/netfilter.c
-@@ -192,15 +192,15 @@ static __sum16 nf_ip6_checksum_partial(s
+@@ -191,15 +191,15 @@ static __sum16 nf_ip6_checksum_partial(s
  };
  
  static const struct nf_ipv6_ops ipv6ops = {
diff --git a/target/linux/generic/backport-4.14/306-v4.16-netfilter-remove-saveroute-indirection-in-struct-nf_.patch b/target/linux/generic/backport-4.14/306-v4.16-netfilter-remove-saveroute-indirection-in-struct-nf_.patch
index 2b44066f1..75de3c84f 100644
--- a/target/linux/generic/backport-4.14/306-v4.16-netfilter-remove-saveroute-indirection-in-struct-nf_.patch
+++ b/target/linux/generic/backport-4.14/306-v4.16-netfilter-remove-saveroute-indirection-in-struct-nf_.patch
@@ -125,7 +125,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  };
 --- a/net/ipv6/netfilter.c
 +++ b/net/ipv6/netfilter.c
-@@ -70,31 +70,6 @@ int ip6_route_me_harder(struct net *net,
+@@ -69,31 +69,6 @@ int ip6_route_me_harder(struct net *net,
  }
  EXPORT_SYMBOL(ip6_route_me_harder);
  
@@ -157,7 +157,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  static int nf_ip6_reroute(struct net *net, struct sk_buff *skb,
  			  const struct nf_queue_entry *entry)
  {
-@@ -202,7 +177,6 @@ static const struct nf_ipv6_ops ipv6ops
+@@ -201,7 +176,6 @@ static const struct nf_ipv6_ops ipv6ops
  static const struct nf_afinfo nf_ip6_afinfo = {
  	.family			= AF_INET6,
  	.route			= nf_ip6_route,
diff --git a/target/linux/generic/backport-4.14/307-v4.16-netfilter-move-route-indirection-to-struct-nf_ipv6_o.patch b/target/linux/generic/backport-4.14/307-v4.16-netfilter-move-route-indirection-to-struct-nf_ipv6_o.patch
index eb3e29349..b98aac0ff 100644
--- a/target/linux/generic/backport-4.14/307-v4.16-netfilter-move-route-indirection-to-struct-nf_ipv6_o.patch
+++ b/target/linux/generic/backport-4.14/307-v4.16-netfilter-move-route-indirection-to-struct-nf_ipv6_o.patch
@@ -114,7 +114,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  };
 --- a/net/ipv6/netfilter.c
 +++ b/net/ipv6/netfilter.c
-@@ -172,11 +172,11 @@ static const struct nf_ipv6_ops ipv6ops
+@@ -171,11 +171,11 @@ static const struct nf_ipv6_ops ipv6ops
  	.fragment		= ip6_fragment,
  	.checksum		= nf_ip6_checksum,
  	.checksum_partial	= nf_ip6_checksum_partial,
diff --git a/target/linux/generic/backport-4.14/308-v4.16-netfilter-move-reroute-indirection-to-struct-nf_ipv6.patch b/target/linux/generic/backport-4.14/308-v4.16-netfilter-move-reroute-indirection-to-struct-nf_ipv6.patch
index d45c4ef85..5dbd1a4ce 100644
--- a/target/linux/generic/backport-4.14/308-v4.16-netfilter-move-reroute-indirection-to-struct-nf_ipv6.patch
+++ b/target/linux/generic/backport-4.14/308-v4.16-netfilter-move-reroute-indirection-to-struct-nf_ipv6.patch
@@ -138,7 +138,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  
 --- a/net/ipv6/netfilter.c
 +++ b/net/ipv6/netfilter.c
-@@ -70,7 +70,7 @@ int ip6_route_me_harder(struct net *net,
+@@ -69,7 +69,7 @@ int ip6_route_me_harder(struct net *net,
  }
  EXPORT_SYMBOL(ip6_route_me_harder);
  
@@ -147,7 +147,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  			  const struct nf_queue_entry *entry)
  {
  	struct ip6_rt_info *rt_info = nf_queue_entry_reroute(entry);
-@@ -80,7 +80,7 @@ static int nf_ip6_reroute(struct net *ne
+@@ -79,7 +79,7 @@ static int nf_ip6_reroute(struct net *ne
  		if (!ipv6_addr_equal(&iph->daddr, &rt_info->daddr) ||
  		    !ipv6_addr_equal(&iph->saddr, &rt_info->saddr) ||
  		    skb->mark != rt_info->mark)
@@ -156,7 +156,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  	}
  	return 0;
  }
-@@ -173,11 +173,11 @@ static const struct nf_ipv6_ops ipv6ops
+@@ -172,11 +172,11 @@ static const struct nf_ipv6_ops ipv6ops
  	.checksum		= nf_ip6_checksum,
  	.checksum_partial	= nf_ip6_checksum_partial,
  	.route			= nf_ip6_route,
diff --git a/target/linux/generic/backport-4.14/309-v4.16-netfilter-remove-route_key_size-field-in-struct-nf_a.patch b/target/linux/generic/backport-4.14/309-v4.16-netfilter-remove-route_key_size-field-in-struct-nf_a.patch
index 270379346..21381b7e6 100644
--- a/target/linux/generic/backport-4.14/309-v4.16-netfilter-remove-route_key_size-field-in-struct-nf_a.patch
+++ b/target/linux/generic/backport-4.14/309-v4.16-netfilter-remove-route_key_size-field-in-struct-nf_a.patch
@@ -29,7 +29,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  static int __init ipv4_netfilter_init(void)
 --- a/net/ipv6/netfilter.c
 +++ b/net/ipv6/netfilter.c
-@@ -178,7 +178,6 @@ static const struct nf_ipv6_ops ipv6ops
+@@ -177,7 +177,6 @@ static const struct nf_ipv6_ops ipv6ops
  
  static const struct nf_afinfo nf_ip6_afinfo = {
  	.family			= AF_INET6,
diff --git a/target/linux/generic/backport-4.14/310-v4.16-netfilter-remove-struct-nf_afinfo-and-its-helper-fun.patch b/target/linux/generic/backport-4.14/310-v4.16-netfilter-remove-struct-nf_afinfo-and-its-helper-fun.patch
index 381b99721..0ca58f998 100644
--- a/target/linux/generic/backport-4.14/310-v4.16-netfilter-remove-struct-nf_afinfo-and-its-helper-fun.patch
+++ b/target/linux/generic/backport-4.14/310-v4.16-netfilter-remove-struct-nf_afinfo-and-its-helper-fun.patch
@@ -102,7 +102,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
 -subsys_initcall(ipv4_netfilter_init);
 --- a/net/ipv6/netfilter.c
 +++ b/net/ipv6/netfilter.c
-@@ -176,14 +176,10 @@ static const struct nf_ipv6_ops ipv6ops
+@@ -175,14 +175,10 @@ static const struct nf_ipv6_ops ipv6ops
  	.reroute		= nf_ip6_reroute,
  };
  
@@ -118,7 +118,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  }
  
  /* This can be called from inet6_init() on errors, so it cannot
-@@ -192,5 +188,4 @@ int __init ipv6_netfilter_init(void)
+@@ -191,5 +187,4 @@ int __init ipv6_netfilter_init(void)
  void ipv6_netfilter_fini(void)
  {
  	RCU_INIT_POINTER(nf_ipv6_ops, NULL);
diff --git a/target/linux/generic/backport-4.14/400-v4.16-leds-trigger-Introduce-a-NETDEV-trigger.patch b/target/linux/generic/backport-4.14/400-v4.16-leds-trigger-Introduce-a-NETDEV-trigger.patch
deleted file mode 100644
index b7d680a11..000000000
--- a/target/linux/generic/backport-4.14/400-v4.16-leds-trigger-Introduce-a-NETDEV-trigger.patch
+++ /dev/null
@@ -1,588 +0,0 @@
-From 06f502f57d0d7728f9fa0f157ec5e4111ddb98f6 Mon Sep 17 00:00:00 2001
-From: Ben Whitten <ben.whitten@gmail.com>
-Date: Sun, 10 Dec 2017 21:17:55 +0000
-Subject: [PATCH] leds: trigger: Introduce a NETDEV trigger
-
-This commit introduces a NETDEV trigger for named device
-activity. Available triggers are link, rx, and tx.
-
-Signed-off-by: Ben Whitten <ben.whitten@gmail.com>
-Acked-by: Pavel Machek <pavel@ucw.cz>
-Signed-off-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
----
- .../ABI/testing/sysfs-class-led-trigger-netdev     |  45 ++
- drivers/leds/trigger/Kconfig                       |   7 +
- drivers/leds/trigger/Makefile                      |   1 +
- drivers/leds/trigger/ledtrig-netdev.c              | 496 +++++++++++++++++++++
- 4 files changed, 549 insertions(+)
- create mode 100644 Documentation/ABI/testing/sysfs-class-led-trigger-netdev
- create mode 100644 drivers/leds/trigger/ledtrig-netdev.c
-
---- /dev/null
-+++ b/Documentation/ABI/testing/sysfs-class-led-trigger-netdev
-@@ -0,0 +1,45 @@
-+What:		/sys/class/leds/<led>/device_name
-+Date:		Dec 2017
-+KernelVersion:	4.16
-+Contact:	linux-leds@vger.kernel.org
-+Description:
-+		Specifies the network device name to monitor.
-+
-+What:		/sys/class/leds/<led>/interval
-+Date:		Dec 2017
-+KernelVersion:	4.16
-+Contact:	linux-leds@vger.kernel.org
-+Description:
-+		Specifies the duration of the LED blink in milliseconds.
-+		Defaults to 50 ms.
-+
-+What:		/sys/class/leds/<led>/link
-+Date:		Dec 2017
-+KernelVersion:	4.16
-+Contact:	linux-leds@vger.kernel.org
-+Description:
-+		Signal the link state of the named network device.
-+		If set to 0 (default), the LED's normal state is off.
-+		If set to 1, the LED's normal state reflects the link state
-+		of the named network device.
-+		Setting this value also immediately changes the LED state.
-+
-+What:		/sys/class/leds/<led>/tx
-+Date:		Dec 2017
-+KernelVersion:	4.16
-+Contact:	linux-leds@vger.kernel.org
-+Description:
-+		Signal transmission of data on the named network device.
-+		If set to 0 (default), the LED will not blink on transmission.
-+		If set to 1, the LED will blink for the milliseconds specified
-+		in interval to signal transmission.
-+
-+What:		/sys/class/leds/<led>/rx
-+Date:		Dec 2017
-+KernelVersion:	4.16
-+Contact:	linux-leds@vger.kernel.org
-+Description:
-+		Signal reception of data on the named network device.
-+		If set to 0 (default), the LED will not blink on reception.
-+		If set to 1, the LED will blink for the milliseconds specified
-+		in interval to signal reception.
---- a/drivers/leds/trigger/Kconfig
-+++ b/drivers/leds/trigger/Kconfig
-@@ -126,4 +126,11 @@ config LEDS_TRIGGER_PANIC
- 	  a different trigger.
- 	  If unsure, say Y.
- 
-+config LEDS_TRIGGER_NETDEV
-+	tristate "LED Netdev Trigger"
-+	depends on NET && LEDS_TRIGGERS
-+	help
-+	  This allows LEDs to be controlled by network device activity.
-+	  If unsure, say Y.
-+
- endif # LEDS_TRIGGERS
---- a/drivers/leds/trigger/Makefile
-+++ b/drivers/leds/trigger/Makefile
-@@ -11,3 +11,4 @@ obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON)	+=
- obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT)	+= ledtrig-transient.o
- obj-$(CONFIG_LEDS_TRIGGER_CAMERA)	+= ledtrig-camera.o
- obj-$(CONFIG_LEDS_TRIGGER_PANIC)	+= ledtrig-panic.o
-+obj-$(CONFIG_LEDS_TRIGGER_NETDEV)	+= ledtrig-netdev.o
---- /dev/null
-+++ b/drivers/leds/trigger/ledtrig-netdev.c
-@@ -0,0 +1,496 @@
-+// SPDX-License-Identifier: GPL-2.0
-+// Copyright 2017 Ben Whitten <ben.whitten@gmail.com>
-+// Copyright 2007 Oliver Jowett <oliver@opencloud.com>
-+//
-+// LED Kernel Netdev Trigger
-+//
-+// Toggles the LED to reflect the link and traffic state of a named net device
-+//
-+// Derived from ledtrig-timer.c which is:
-+//  Copyright 2005-2006 Openedhand Ltd.
-+//  Author: Richard Purdie <rpurdie@openedhand.com>
-+
-+#include <linux/atomic.h>
-+#include <linux/ctype.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/jiffies.h>
-+#include <linux/kernel.h>
-+#include <linux/leds.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/netdevice.h>
-+#include <linux/spinlock.h>
-+#include <linux/timer.h>
-+#include "../leds.h"
-+
-+/*
-+ * Configurable sysfs attributes:
-+ *
-+ * device_name - network device name to monitor
-+ * interval - duration of LED blink, in milliseconds
-+ * link -  LED's normal state reflects whether the link is up
-+ *         (has carrier) or not
-+ * tx -  LED blinks on transmitted data
-+ * rx -  LED blinks on receive data
-+ *
-+ */
-+
-+struct led_netdev_data {
-+	spinlock_t lock;
-+
-+	struct delayed_work work;
-+	struct notifier_block notifier;
-+
-+	struct led_classdev *led_cdev;
-+	struct net_device *net_dev;
-+
-+	char device_name[IFNAMSIZ];
-+	atomic_t interval;
-+	unsigned int last_activity;
-+
-+	unsigned long mode;
-+#define NETDEV_LED_LINK	0
-+#define NETDEV_LED_TX	1
-+#define NETDEV_LED_RX	2
-+#define NETDEV_LED_MODE_LINKUP	3
-+};
-+
-+enum netdev_led_attr {
-+	NETDEV_ATTR_LINK,
-+	NETDEV_ATTR_TX,
-+	NETDEV_ATTR_RX
-+};
-+
-+static void set_baseline_state(struct led_netdev_data *trigger_data)
-+{
-+	int current_brightness;
-+	struct led_classdev *led_cdev = trigger_data->led_cdev;
-+
-+	current_brightness = led_cdev->brightness;
-+	if (current_brightness)
-+		led_cdev->blink_brightness = current_brightness;
-+	if (!led_cdev->blink_brightness)
-+		led_cdev->blink_brightness = led_cdev->max_brightness;
-+
-+	if (!test_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode))
-+		led_set_brightness(led_cdev, LED_OFF);
-+	else {
-+		if (test_bit(NETDEV_LED_LINK, &trigger_data->mode))
-+			led_set_brightness(led_cdev,
-+					   led_cdev->blink_brightness);
-+		else
-+			led_set_brightness(led_cdev, LED_OFF);
-+
-+		/* If we are looking for RX/TX start periodically
-+		 * checking stats
-+		 */
-+		if (test_bit(NETDEV_LED_TX, &trigger_data->mode) ||
-+		    test_bit(NETDEV_LED_RX, &trigger_data->mode))
-+			schedule_delayed_work(&trigger_data->work, 0);
-+	}
-+}
-+
-+static ssize_t device_name_show(struct device *dev,
-+				struct device_attribute *attr, char *buf)
-+{
-+	struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
-+	ssize_t len;
-+
-+	spin_lock_bh(&trigger_data->lock);
-+	len = sprintf(buf, "%s\n", trigger_data->device_name);
-+	spin_unlock_bh(&trigger_data->lock);
-+
-+	return len;
-+}
-+
-+static ssize_t device_name_store(struct device *dev,
-+				 struct device_attribute *attr, const char *buf,
-+				 size_t size)
-+{
-+	struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
-+
-+	if (size >= IFNAMSIZ)
-+		return -EINVAL;
-+
-+	cancel_delayed_work_sync(&trigger_data->work);
-+
-+	spin_lock_bh(&trigger_data->lock);
-+
-+	if (trigger_data->net_dev) {
-+		dev_put(trigger_data->net_dev);
-+		trigger_data->net_dev = NULL;
-+	}
-+
-+	strncpy(trigger_data->device_name, buf, size);
-+	if (size > 0 && trigger_data->device_name[size - 1] == '\n')
-+		trigger_data->device_name[size - 1] = 0;
-+
-+	if (trigger_data->device_name[0] != 0)
-+		trigger_data->net_dev =
-+		    dev_get_by_name(&init_net, trigger_data->device_name);
-+
-+	clear_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode);
-+	if (trigger_data->net_dev != NULL)
-+		if (netif_carrier_ok(trigger_data->net_dev))
-+			set_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode);
-+
-+	trigger_data->last_activity = 0;
-+
-+	set_baseline_state(trigger_data);
-+	spin_unlock_bh(&trigger_data->lock);
-+
-+	return size;
-+}
-+
-+static DEVICE_ATTR_RW(device_name);
-+
-+static ssize_t netdev_led_attr_show(struct device *dev, char *buf,
-+	enum netdev_led_attr attr)
-+{
-+	struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
-+	int bit;
-+
-+	switch (attr) {
-+	case NETDEV_ATTR_LINK:
-+		bit = NETDEV_LED_LINK;
-+		break;
-+	case NETDEV_ATTR_TX:
-+		bit = NETDEV_LED_TX;
-+		break;
-+	case NETDEV_ATTR_RX:
-+		bit = NETDEV_LED_RX;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return sprintf(buf, "%u\n", test_bit(bit, &trigger_data->mode));
-+}
-+
-+static ssize_t netdev_led_attr_store(struct device *dev, const char *buf,
-+	size_t size, enum netdev_led_attr attr)
-+{
-+	struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
-+	unsigned long state;
-+	int ret;
-+	int bit;
-+
-+	ret = kstrtoul(buf, 0, &state);
-+	if (ret)
-+		return ret;
-+
-+	switch (attr) {
-+	case NETDEV_ATTR_LINK:
-+		bit = NETDEV_LED_LINK;
-+		break;
-+	case NETDEV_ATTR_TX:
-+		bit = NETDEV_LED_TX;
-+		break;
-+	case NETDEV_ATTR_RX:
-+		bit = NETDEV_LED_RX;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	cancel_delayed_work_sync(&trigger_data->work);
-+
-+	if (state)
-+		set_bit(bit, &trigger_data->mode);
-+	else
-+		clear_bit(bit, &trigger_data->mode);
-+
-+	set_baseline_state(trigger_data);
-+
-+	return size;
-+}
-+
-+static ssize_t link_show(struct device *dev,
-+	struct device_attribute *attr, char *buf)
-+{
-+	return netdev_led_attr_show(dev, buf, NETDEV_ATTR_LINK);
-+}
-+
-+static ssize_t link_store(struct device *dev,
-+	struct device_attribute *attr, const char *buf, size_t size)
-+{
-+	return netdev_led_attr_store(dev, buf, size, NETDEV_ATTR_LINK);
-+}
-+
-+static DEVICE_ATTR_RW(link);
-+
-+static ssize_t tx_show(struct device *dev,
-+	struct device_attribute *attr, char *buf)
-+{
-+	return netdev_led_attr_show(dev, buf, NETDEV_ATTR_TX);
-+}
-+
-+static ssize_t tx_store(struct device *dev,
-+	struct device_attribute *attr, const char *buf, size_t size)
-+{
-+	return netdev_led_attr_store(dev, buf, size, NETDEV_ATTR_TX);
-+}
-+
-+static DEVICE_ATTR_RW(tx);
-+
-+static ssize_t rx_show(struct device *dev,
-+	struct device_attribute *attr, char *buf)
-+{
-+	return netdev_led_attr_show(dev, buf, NETDEV_ATTR_RX);
-+}
-+
-+static ssize_t rx_store(struct device *dev,
-+	struct device_attribute *attr, const char *buf, size_t size)
-+{
-+	return netdev_led_attr_store(dev, buf, size, NETDEV_ATTR_RX);
-+}
-+
-+static DEVICE_ATTR_RW(rx);
-+
-+static ssize_t interval_show(struct device *dev,
-+			     struct device_attribute *attr, char *buf)
-+{
-+	struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
-+
-+	return sprintf(buf, "%u\n",
-+		       jiffies_to_msecs(atomic_read(&trigger_data->interval)));
-+}
-+
-+static ssize_t interval_store(struct device *dev,
-+			      struct device_attribute *attr, const char *buf,
-+			      size_t size)
-+{
-+	struct led_classdev *led_cdev = dev_get_drvdata(dev);
-+	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
-+	unsigned long value;
-+	int ret;
-+
-+	ret = kstrtoul(buf, 0, &value);
-+	if (ret)
-+		return ret;
-+
-+	/* impose some basic bounds on the timer interval */
-+	if (value >= 5 && value <= 10000) {
-+		cancel_delayed_work_sync(&trigger_data->work);
-+
-+		atomic_set(&trigger_data->interval, msecs_to_jiffies(value));
-+		set_baseline_state(trigger_data);	/* resets timer */
-+	}
-+
-+	return size;
-+}
-+
-+static DEVICE_ATTR_RW(interval);
-+
-+static int netdev_trig_notify(struct notifier_block *nb,
-+			      unsigned long evt, void *dv)
-+{
-+	struct net_device *dev =
-+		netdev_notifier_info_to_dev((struct netdev_notifier_info *)dv);
-+	struct led_netdev_data *trigger_data = container_of(nb,
-+							    struct
-+							    led_netdev_data,
-+							    notifier);
-+
-+	if (evt != NETDEV_UP && evt != NETDEV_DOWN && evt != NETDEV_CHANGE
-+	    && evt != NETDEV_REGISTER && evt != NETDEV_UNREGISTER
-+	    && evt != NETDEV_CHANGENAME)
-+		return NOTIFY_DONE;
-+
-+	if (strcmp(dev->name, trigger_data->device_name))
-+		return NOTIFY_DONE;
-+
-+	cancel_delayed_work_sync(&trigger_data->work);
-+
-+	spin_lock_bh(&trigger_data->lock);
-+
-+	clear_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode);
-+	switch (evt) {
-+	case NETDEV_REGISTER:
-+		if (trigger_data->net_dev)
-+			dev_put(trigger_data->net_dev);
-+		dev_hold(dev);
-+		trigger_data->net_dev = dev;
-+		break;
-+	case NETDEV_CHANGENAME:
-+	case NETDEV_UNREGISTER:
-+		if (trigger_data->net_dev) {
-+			dev_put(trigger_data->net_dev);
-+			trigger_data->net_dev = NULL;
-+		}
-+		break;
-+	case NETDEV_UP:
-+	case NETDEV_CHANGE:
-+		if (netif_carrier_ok(dev))
-+			set_bit(NETDEV_LED_MODE_LINKUP, &trigger_data->mode);
-+		break;
-+	}
-+
-+	set_baseline_state(trigger_data);
-+
-+	spin_unlock_bh(&trigger_data->lock);
-+
-+	return NOTIFY_DONE;
-+}
-+
-+/* here's the real work! */
-+static void netdev_trig_work(struct work_struct *work)
-+{
-+	struct led_netdev_data *trigger_data = container_of(work,
-+							    struct
-+							    led_netdev_data,
-+							    work.work);
-+	struct rtnl_link_stats64 *dev_stats;
-+	unsigned int new_activity;
-+	struct rtnl_link_stats64 temp;
-+	unsigned long interval;
-+	int invert;
-+
-+	/* If we dont have a device, insure we are off */
-+	if (!trigger_data->net_dev) {
-+		led_set_brightness(trigger_data->led_cdev, LED_OFF);
-+		return;
-+	}
-+
-+	/* If we are not looking for RX/TX then return  */
-+	if (!test_bit(NETDEV_LED_TX, &trigger_data->mode) &&
-+	    !test_bit(NETDEV_LED_RX, &trigger_data->mode))
-+		return;
-+
-+	dev_stats = dev_get_stats(trigger_data->net_dev, &temp);
-+	new_activity =
-+	    (test_bit(NETDEV_LED_TX, &trigger_data->mode) ?
-+		dev_stats->tx_packets : 0) +
-+	    (test_bit(NETDEV_LED_RX, &trigger_data->mode) ?
-+		dev_stats->rx_packets : 0);
-+
-+	if (trigger_data->last_activity != new_activity) {
-+		led_stop_software_blink(trigger_data->led_cdev);
-+
-+		invert = test_bit(NETDEV_LED_LINK, &trigger_data->mode);
-+		interval = jiffies_to_msecs(
-+				atomic_read(&trigger_data->interval));
-+		/* base state is ON (link present) */
-+		led_blink_set_oneshot(trigger_data->led_cdev,
-+				      &interval,
-+				      &interval,
-+				      invert);
-+		trigger_data->last_activity = new_activity;
-+	}
-+
-+	schedule_delayed_work(&trigger_data->work,
-+			(atomic_read(&trigger_data->interval)*2));
-+}
-+
-+static void netdev_trig_activate(struct led_classdev *led_cdev)
-+{
-+	struct led_netdev_data *trigger_data;
-+	int rc;
-+
-+	trigger_data = kzalloc(sizeof(struct led_netdev_data), GFP_KERNEL);
-+	if (!trigger_data)
-+		return;
-+
-+	spin_lock_init(&trigger_data->lock);
-+
-+	trigger_data->notifier.notifier_call = netdev_trig_notify;
-+	trigger_data->notifier.priority = 10;
-+
-+	INIT_DELAYED_WORK(&trigger_data->work, netdev_trig_work);
-+
-+	trigger_data->led_cdev = led_cdev;
-+	trigger_data->net_dev = NULL;
-+	trigger_data->device_name[0] = 0;
-+
-+	trigger_data->mode = 0;
-+	atomic_set(&trigger_data->interval, msecs_to_jiffies(50));
-+	trigger_data->last_activity = 0;
-+
-+	led_cdev->trigger_data = trigger_data;
-+
-+	rc = device_create_file(led_cdev->dev, &dev_attr_device_name);
-+	if (rc)
-+		goto err_out;
-+	rc = device_create_file(led_cdev->dev, &dev_attr_link);
-+	if (rc)
-+		goto err_out_device_name;
-+	rc = device_create_file(led_cdev->dev, &dev_attr_rx);
-+	if (rc)
-+		goto err_out_link;
-+	rc = device_create_file(led_cdev->dev, &dev_attr_tx);
-+	if (rc)
-+		goto err_out_rx;
-+	rc = device_create_file(led_cdev->dev, &dev_attr_interval);
-+	if (rc)
-+		goto err_out_tx;
-+	rc = register_netdevice_notifier(&trigger_data->notifier);
-+	if (rc)
-+		goto err_out_interval;
-+	return;
-+
-+err_out_interval:
-+	device_remove_file(led_cdev->dev, &dev_attr_interval);
-+err_out_tx:
-+	device_remove_file(led_cdev->dev, &dev_attr_tx);
-+err_out_rx:
-+	device_remove_file(led_cdev->dev, &dev_attr_rx);
-+err_out_link:
-+	device_remove_file(led_cdev->dev, &dev_attr_link);
-+err_out_device_name:
-+	device_remove_file(led_cdev->dev, &dev_attr_device_name);
-+err_out:
-+	led_cdev->trigger_data = NULL;
-+	kfree(trigger_data);
-+}
-+
-+static void netdev_trig_deactivate(struct led_classdev *led_cdev)
-+{
-+	struct led_netdev_data *trigger_data = led_cdev->trigger_data;
-+
-+	if (trigger_data) {
-+		unregister_netdevice_notifier(&trigger_data->notifier);
-+
-+		device_remove_file(led_cdev->dev, &dev_attr_device_name);
-+		device_remove_file(led_cdev->dev, &dev_attr_link);
-+		device_remove_file(led_cdev->dev, &dev_attr_rx);
-+		device_remove_file(led_cdev->dev, &dev_attr_tx);
-+		device_remove_file(led_cdev->dev, &dev_attr_interval);
-+
-+		cancel_delayed_work_sync(&trigger_data->work);
-+
-+		if (trigger_data->net_dev)
-+			dev_put(trigger_data->net_dev);
-+
-+		kfree(trigger_data);
-+	}
-+}
-+
-+static struct led_trigger netdev_led_trigger = {
-+	.name = "netdev",
-+	.activate = netdev_trig_activate,
-+	.deactivate = netdev_trig_deactivate,
-+};
-+
-+static int __init netdev_trig_init(void)
-+{
-+	return led_trigger_register(&netdev_led_trigger);
-+}
-+
-+static void __exit netdev_trig_exit(void)
-+{
-+	led_trigger_unregister(&netdev_led_trigger);
-+}
-+
-+module_init(netdev_trig_init);
-+module_exit(netdev_trig_exit);
-+
-+MODULE_AUTHOR("Ben Whitten <ben.whitten@gmail.com>");
-+MODULE_AUTHOR("Oliver Jowett <oliver@opencloud.com>");
-+MODULE_DESCRIPTION("Netdev LED trigger");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/generic/backport-4.14/500-ubifs-Handle-re-linking-of-inodes-correctly-while-re.patch b/target/linux/generic/backport-4.14/500-ubifs-Handle-re-linking-of-inodes-correctly-while-re.patch
deleted file mode 100644
index 71e036c92..000000000
--- a/target/linux/generic/backport-4.14/500-ubifs-Handle-re-linking-of-inodes-correctly-while-re.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From: Richard Weinberger <richard@nod.at>
-Date: Wed, 7 Nov 2018 23:04:43 +0100
-Subject: [PATCH] ubifs: Handle re-linking of inodes correctly while recovery
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-UBIFS's recovery code strictly assumes that a deleted inode will never
-come back, therefore it removes all data which belongs to that inode
-as soon it faces an inode with link count 0 in the replay list.
-Before O_TMPFILE this assumption was perfectly fine. With O_TMPFILE
-it can lead to data loss upon a power-cut.
-
-Consider a journal with entries like:
-0: inode X (nlink = 0) /* O_TMPFILE was created */
-1: data for inode X /* Someone writes to the temp file */
-2: inode X (nlink = 0) /* inode was changed, xattr, chmod, … */
-3: inode X (nlink = 1) /* inode was re-linked via linkat() */
-
-Upon replay of entry #2 UBIFS will drop all data that belongs to inode X,
-this will lead to an empty file after mounting.
-
-As solution for this problem, scan the replay list for a re-link entry
-before dropping data.
-
-Fixes: 474b93704f32 ("ubifs: Implement O_TMPFILE")
-Cc: stable@vger.kernel.org
-Cc: Russell Senior <russell@personaltelco.net>
-Cc: Rafał Miłecki <zajec5@gmail.com>
-Reported-by: Russell Senior <russell@personaltelco.net>
-Reported-by: Rafał Miłecki <zajec5@gmail.com>
-Signed-off-by: Richard Weinberger <richard@nod.at>
----
- fs/ubifs/replay.c | 37 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 37 insertions(+)
-
---- a/fs/ubifs/replay.c
-+++ b/fs/ubifs/replay.c
-@@ -210,6 +210,38 @@ static int trun_remove_range(struct ubif
- }
- 
- /**
-+ * inode_still_linked - check whether inode in question will be re-linked.
-+ * @c: UBIFS file-system description object
-+ * @rino: replay entry to test
-+ *
-+ * O_TMPFILE files can be re-linked, this means link count goes from 0 to 1.
-+ * This case needs special care, otherwise all references to the inode will
-+ * be removed upon the first replay entry of an inode with link count 0
-+ * is found.
-+ */
-+static bool inode_still_linked(struct ubifs_info *c, struct replay_entry *rino)
-+{
-+	struct replay_entry *r;
-+
-+	ubifs_assert(rino->deletion);
-+	ubifs_assert(key_type(c, &rino->key) == UBIFS_INO_KEY);
-+
-+	/*
-+	 * Find the most recent entry for the inode behind @rino and check
-+	 * whether it is a deletion.
-+	 */
-+	list_for_each_entry_reverse(r, &c->replay_list, list) {
-+		ubifs_assert(r->sqnum >= rino->sqnum);
-+		if (key_inum(c, &r->key) == key_inum(c, &rino->key))
-+			return r->deletion == 0;
-+
-+	}
-+
-+	ubifs_assert(0);
-+	return false;
-+}
-+
-+/**
-  * apply_replay_entry - apply a replay entry to the TNC.
-  * @c: UBIFS file-system description object
-  * @r: replay entry to apply
-@@ -239,6 +271,11 @@ static int apply_replay_entry(struct ubi
- 			{
- 				ino_t inum = key_inum(c, &r->key);
- 
-+				if (inode_still_linked(c, r)) {
-+					err = 0;
-+					break;
-+				}
-+
- 				err = ubifs_tnc_remove_ino(c, inum);
- 				break;
- 			}
diff --git a/target/linux/generic/hack-4.14/902-debloat_proc.patch b/target/linux/generic/hack-4.14/902-debloat_proc.patch
index 98788cd26..cae6d66e7 100644
--- a/target/linux/generic/hack-4.14/902-debloat_proc.patch
+++ b/target/linux/generic/hack-4.14/902-debloat_proc.patch
@@ -227,7 +227,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 +	if (IS_ENABLED(CONFIG_PROC_STRIPPED))
 +		return 0;
- 	pe = proc_create("timer_list", 0400, NULL, &timer_list_fops);
+ 	pe = proc_create("timer_list", 0444, NULL, &timer_list_fops);
  	if (!pe)
  		return -ENOMEM;
 --- a/mm/vmalloc.c
diff --git a/target/linux/generic/pending-4.14/834-ledtrig-libata.patch b/target/linux/generic/pending-4.14/834-ledtrig-libata.patch
index 392d41c94..2eec024b7 100644
--- a/target/linux/generic/pending-4.14/834-ledtrig-libata.patch
+++ b/target/linux/generic/pending-4.14/834-ledtrig-libata.patch
@@ -65,7 +65,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /**
   *	ata_build_rw_tf - Build ATA taskfile for given read/write request
   *	@tf: Target ATA taskfile
-@@ -5121,6 +5134,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
+@@ -5120,6 +5133,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
  		if (tag < 0)
  			return NULL;
  	}
@@ -75,7 +75,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  	qc = __ata_qc_from_tag(ap, tag);
  	qc->tag = tag;
-@@ -6022,6 +6038,9 @@ struct ata_port *ata_port_alloc(struct a
+@@ -6021,6 +6037,9 @@ struct ata_port *ata_port_alloc(struct a
  	ap->stats.unhandled_irq = 1;
  	ap->stats.idle_irq = 1;
  #endif
@@ -85,7 +85,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	ata_sff_port_init(ap);
  
  	return ap;
-@@ -6043,6 +6062,12 @@ static void ata_host_release(struct devi
+@@ -6042,6 +6061,12 @@ static void ata_host_release(struct devi
  
  		kfree(ap->pmp_link);
  		kfree(ap->slave_link);
@@ -98,7 +98,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		kfree(ap);
  		host->ports[i] = NULL;
  	}
-@@ -6489,7 +6514,23 @@ int ata_host_register(struct ata_host *h
+@@ -6488,7 +6513,23 @@ int ata_host_register(struct ata_host *h
  		host->ports[i]->print_id = atomic_inc_return(&ata_print_id);
  		host->ports[i]->local_port_no = i + 1;
  	}
diff --git a/target/linux/layerscape/Makefile b/target/linux/layerscape/Makefile
index 7bb12b85e..9b8ae4082 100644
--- a/target/linux/layerscape/Makefile
+++ b/target/linux/layerscape/Makefile
@@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
 
 BOARD:=layerscape
 BOARDNAME:=NXP Layerscape
-KERNEL_PATCHVER:=4.14
+KERNEL_PATCHVER:=4.9
 FEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4
 SUBTARGETS:=armv8_64b armv8_32b armv7
 MAINTAINER:=Yangbo Lu <yangbo.lu@nxp.com>
diff --git a/target/linux/layerscape/README b/target/linux/layerscape/README
index 5af20e191..1aecf30ac 100644
--- a/target/linux/layerscape/README
+++ b/target/linux/layerscape/README
@@ -11,8 +11,8 @@ Layerscape Quick Start
   LS1012ARDB LS1012AFRWY LS1043ARDB LS1046ARDB
 
 * ARMv7
-  LS1021ATWR LS1021AIOT
-  (SD card boot support on LS1021ATWR/LS1021AIOT)
+  LS1021ATWR
+  (SD card boot support on LS1021ATWR)
 
 
 2. Build
diff --git a/target/linux/layerscape/armv7/config-4.14 b/target/linux/layerscape/armv7/config-4.9
old mode 100755
new mode 100644
similarity index 74%
rename from target/linux/layerscape/armv7/config-4.14
rename to target/linux/layerscape/armv7/config-4.9
index b70d4705d..9eae0fabc
--- a/target/linux/layerscape/armv7/config-4.14
+++ b/target/linux/layerscape/armv7/config-4.9
@@ -1,19 +1,20 @@
+CONFIG_ABX500_CORE=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
 # CONFIG_AD525X_DPOT_SPI is not set
+CONFIG_AHCI_IMX=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_AK8975=y
 CONFIG_ALIGNMENT_TRAP=y
 CONFIG_APDS9802ALS=y
 CONFIG_AQUANTIA_PHY=y
 # CONFIG_ARCH_AXXIA is not set
 CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
 CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
 CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
 CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
 CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
 CONFIG_ARCH_HAS_TICK_BROADCAST=y
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
@@ -24,8 +25,6 @@ CONFIG_ARCH_MULTI_V6_V7=y
 CONFIG_ARCH_MULTI_V7=y
 CONFIG_ARCH_MXC=y
 CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
 CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
@@ -46,6 +45,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
 CONFIG_ARM_CPUIDLE=y
 CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CRYPTO=y
 CONFIG_ARM_ERRATA_430973=y
 CONFIG_ARM_ERRATA_643719=y
 CONFIG_ARM_ERRATA_720789=y
@@ -58,6 +58,7 @@ CONFIG_ARM_GIC=y
 CONFIG_ARM_HAS_SG_CHAIN=y
 CONFIG_ARM_HEAVY_MB=y
 # CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_IMX6Q_CPUFREQ=y
 CONFIG_ARM_L1_CACHE_SHIFT=6
 CONFIG_ARM_L1_CACHE_SHIFT_6=y
 CONFIG_ARM_LPAE=y
@@ -72,13 +73,18 @@ CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_TIMER_SP804=y
 CONFIG_ARM_UNWIND=y
 CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASSOCIATIVE_ARRAY=y
 CONFIG_AT803X_PHY=y
+CONFIG_ATA=y
 CONFIG_ATAGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AXP20X_POWER is not set
+CONFIG_BATTERY_ACT8945A=y
 CONFIG_BATTERY_SBS=y
 CONFIG_BCM_NET_PHYLIB=y
-CONFIG_BINARY_PRINTF=y
+# CONFIG_BLK_CGROUP is not set
 CONFIG_BLK_CMDLINE_PARSER=y
 CONFIG_BLK_DEV_BSG=y
 CONFIG_BLK_DEV_LOOP=y
@@ -89,10 +95,10 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
 # CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_SCSI_REQUEST=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_BOUNCE=y
 # CONFIG_BPF_SYSCALL is not set
 CONFIG_BRCMSTB_GISB_ARB=y
@@ -100,11 +106,28 @@ CONFIG_BROADCOM_PHY=y
 CONFIG_BUILD_BIN2C=y
 CONFIG_CACHE_L2X0=y
 # CONFIG_CACHE_L2X0_PMU is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_SCHED=y
+# CONFIG_CHARGER_MAX14577 is not set
+CONFIG_CHARGER_TPS65090=y
+# CONFIG_CHARGER_TPS65217 is not set
 CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHROME_PLATFORMS=y
 CONFIG_CHR_DEV_SG=y
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLKSRC_IMX_GPT=y
 CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_VERSATILE=y
 CONFIG_CLK_QORIQ=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_CMA=y
@@ -119,14 +142,20 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
 # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
 CONFIG_CMDLINE_PARTITION=y
 CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MAX77686=y
+# CONFIG_COMMON_CLK_PALMAS is not set
+# CONFIG_COMMON_CLK_RK808 is not set
+# CONFIG_COMMON_CLK_S2MPS11 is not set
+CONFIG_COMPACTION=y
 CONFIG_COMPAT_BRK=y
 CONFIG_CONFIGFS_FS=y
 CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
 CONFIG_COREDUMP=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_CORTINA_PHY is not set
 CONFIG_CPUFREQ_DT=y
 CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUSETS=y
 CONFIG_CPU_32v6K=y
 CONFIG_CPU_32v7=y
 CONFIG_CPU_ABRT_EV7=y
@@ -155,32 +184,35 @@ CONFIG_CPU_HAS_ASID=y
 CONFIG_CPU_IDLE=y
 # CONFIG_CPU_IDLE_GOV_LADDER is not set
 CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
 CONFIG_CPU_PABRT_V7=y
 CONFIG_CPU_PM=y
 CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
 CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
 CONFIG_CPU_TLB_V7=y
 CONFIG_CPU_V7=y
-CONFIG_CRASH_CORE=y
 CONFIG_CRC16=y
 # CONFIG_CRC32_SARWATE is not set
 CONFIG_CRC32_SLICEBY8=y
 CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_ACOMP2=y
 CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
+# CONFIG_CRYPTO_AES_ARM_CE is not set
 CONFIG_CRYPTO_CRC32C=y
 CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_GHASH_ARM_CE is not set
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
 CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
 CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_SHA1_ARM_CE is not set
+# CONFIG_CRYPTO_SHA1_ARM_NEON is not set
+# CONFIG_CRYPTO_SHA256_ARM is not set
+# CONFIG_CRYPTO_SHA2_ARM_CE is not set
+# CONFIG_CRYPTO_SHA512_ARM is not set
 # CONFIG_CRYPTO_TLS is not set
 CONFIG_CRYPTO_WORKQUEUE=y
 CONFIG_DCACHE_WORD_ACCESS=y
@@ -188,6 +220,7 @@ CONFIG_DEBUG_ALIGN_RODATA=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_IMX_UART_PORT=1
 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_RODATA=y
 # CONFIG_DEBUG_UART_8250 is not set
 # CONFIG_DEBUG_USER is not set
 CONFIG_DECOMPRESS_BZIP2=y
@@ -216,17 +249,19 @@ CONFIG_DMA_ENGINE=y
 CONFIG_DMA_OF=y
 CONFIG_DMA_SHARED_BUFFER=y
 CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMI=y
-CONFIG_DMIID=y
-# CONFIG_DMI_SYSFS is not set
 CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
 CONFIG_DTC=y
 CONFIG_DT_IDLE_STATES=y
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_DW_DMAC=y
 CONFIG_DW_DMAC_CORE=y
 CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC=y
 CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+# CONFIG_EDAC_MM_EDAC is not set
 CONFIG_EDAC_SUPPORT=y
 CONFIG_EEPROM_93CX6=y
 CONFIG_EEPROM_AT24=y
@@ -243,10 +278,15 @@ CONFIG_EFI_STUB=y
 CONFIG_ELF_CORE=y
 # CONFIG_ENABLE_DEFAULT_TRACERS is not set
 CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_EVENT_TRACING=y
+CONFIG_EXPORTFS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+# CONFIG_EXTCON_MAX14577 is not set
+# CONFIG_EXTCON_MAX8997 is not set
+# CONFIG_EXTCON_PALMAS is not set
+CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_FAT_FS=y
 # CONFIG_FEC is not set
 CONFIG_FHANDLE=y
@@ -255,7 +295,6 @@ CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_FORCE_MAX_ZONEORDER=12
 CONFIG_FREEZER=y
-# CONFIG_FSL_DPAA2_ETH_CEETM is not set
 CONFIG_FSL_EDMA=y
 CONFIG_FSL_GUTS=y
 CONFIG_FSL_IFC=y
@@ -272,16 +311,14 @@ CONFIG_FTRACE=y
 CONFIG_FUSE_FS=y
 # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_EARLY_IOREMAP=y
 CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IO=y
 CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 CONFIG_GENERIC_MSI_IRQ=y
@@ -289,8 +326,6 @@ CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_GENERIC_PHY=y
 CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
@@ -299,11 +334,24 @@ CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GIANFAR=y
 CONFIG_GLOB=y
 CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_GPIO_AXP209 is not set
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_EM=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MPC8XXX=y
 CONFIG_GPIO_MXC=y
-# CONFIG_GRO_CELLS is not set
+CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCF857X=y
+# CONFIG_GPIO_STMPE is not set
+CONFIG_GPIO_SYSCON=y
+# CONFIG_GPIO_TPS65218 is not set
+CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TWL4030=y
+CONFIG_GPIO_XILINX=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HARDEN_BRANCH_PREDICTOR=y
 CONFIG_HARDIRQS_SW_RESEND=y
@@ -322,6 +370,7 @@ CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
 CONFIG_HAVE_ARM_ARCH_TIMER=y
 CONFIG_HAVE_ARM_SMCCC=y
 # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
 CONFIG_HAVE_CC_STACKPROTECTOR=y
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_CLK_PREPARE=y
@@ -331,18 +380,22 @@ CONFIG_HAVE_DEBUG_KMEMLEAK=y
 CONFIG_HAVE_DMA_API_DEBUG=y
 CONFIG_HAVE_DMA_CONTIGUOUS=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_GUP=y
+CONFIG_HAVE_GENERIC_RCU_GUP=y
 CONFIG_HAVE_HW_BREAKPOINT=y
 CONFIG_HAVE_IDE=y
 CONFIG_HAVE_IMX_SRC=y
 CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
 CONFIG_HAVE_MEMBLOCK=y
 CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
 CONFIG_HAVE_NET_DSA=y
@@ -365,9 +418,9 @@ CONFIG_HIGHPTE=y
 CONFIG_HOTPLUG_CPU=y
 # CONFIG_HUGETLBFS is not set
 CONFIG_HVC_DRIVER=y
+CONFIG_HWMON=y
 CONFIG_HW_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_IMX_RNGC=y
 CONFIG_HZ_FIXED=0
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
@@ -376,10 +429,8 @@ CONFIG_I2C_COMPAT=y
 CONFIG_I2C_DEMUX_PINCTRL=y
 CONFIG_I2C_DESIGNWARE_CORE=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
 CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_IMX=y
-# CONFIG_I2C_IMX_LPI2C is not set
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_MUX_PINCTRL=y
@@ -389,6 +440,15 @@ CONFIG_I2C_SLAVE_EEPROM=y
 CONFIG_I2C_XILINX=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_ICS932S401=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONFIGFS=y
+CONFIG_IIO_HRTIMER_TRIGGER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_SW_TRIGGER=y
+# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_IMX2_WDT=y
@@ -418,28 +478,73 @@ CONFIG_KERNEL_GZIP=y
 # CONFIG_KERNEL_XZ is not set
 CONFIG_KEXEC=y
 CONFIG_KEXEC_CORE=y
+CONFIG_KEYS=y
+CONFIG_KVM=y
+CONFIG_KVM_ARM_HOST=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_MAX8997 is not set
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_LIBFDT=y
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCKUP_DETECTOR=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
 CONFIG_LS_SCFG_MSI=y
 CONFIG_LS_SOC_DRIVERS=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACVLAN=y
+CONFIG_MACVTAP=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
 CONFIG_MANDATORY_FILE_LOCKING=y
 CONFIG_MARVELL_PHY=y
 CONFIG_MCPM=y
 CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BOARDINFO=y
 # CONFIG_MDIO_FSL_BACKPLANE is not set
 # CONFIG_MDIO_GPIO is not set
+CONFIG_MEMCG=y
+# CONFIG_MEMCG_SWAP is not set
 CONFIG_MEMORY=y
 CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_ACT8945A=y
+CONFIG_MFD_AS3711=y
+CONFIG_MFD_AS3722=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_BCM590XX=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MAX14577=y
+CONFIG_MFD_MAX77686=y
+CONFIG_MFD_MAX8907=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_MAX8998=y
+CONFIG_MFD_PALMAS=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_STMPE=y
 CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_VEXPRESS_SYSREG is not set
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS65217=y
+CONFIG_MFD_TPS65218=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+# CONFIG_MFD_TWL4030_AUDIO is not set
+CONFIG_MFD_VEXPRESS_SYSREG=y
 CONFIG_MICREL_PHY=y
 CONFIG_MIGHT_HAVE_CACHE_L2X0=y
 CONFIG_MIGHT_HAVE_PCI=y
@@ -455,6 +560,7 @@ CONFIG_MMC_SDHCI_OF_ESDHC=y
 # CONFIG_MMC_SDHCI_PCI is not set
 CONFIG_MMC_SDHCI_PLTFM=y
 # CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMU_NOTIFIER=y
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MSDOS_FS=y
@@ -468,6 +574,9 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_DENALI=y
+CONFIG_MTD_NAND_DENALI_DT=y
 CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND_FSL_IFC=y
 CONFIG_MTD_SPI_NOR=y
@@ -483,12 +592,11 @@ CONFIG_MULTI_IRQ_HANDLER=y
 CONFIG_MUTEX_SPIN_ON_OWNER=y
 CONFIG_MX3_IPU=y
 CONFIG_MX3_IPU_IRQS=4
-# CONFIG_MXS_DMA is not set
 CONFIG_NAMESPACES=y
 CONFIG_NATIONAL_PHY=y
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEON=y
-# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_CLS_CGROUP is not set
 CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NET_NS=y
 CONFIG_NET_PTP_CLASSIFY=y
@@ -497,7 +605,6 @@ CONFIG_NLS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
-CONFIG_NOP_TRACER=y
 CONFIG_NO_BOOTMEM=y
 CONFIG_NO_HZ=y
 CONFIG_NO_HZ_COMMON=y
@@ -505,7 +612,6 @@ CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=16
 CONFIG_NTFS_FS=y
 CONFIG_NVMEM=y
-# CONFIG_NVMEM_IMX_IIM is not set
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_ADDRESS_PCI=y
@@ -524,7 +630,7 @@ CONFIG_OLD_SIGSUSPEND3=y
 CONFIG_OUTER_CACHE=y
 CONFIG_OUTER_CACHE_SYNC=y
 CONFIG_PACKET_DIAG=y
-CONFIG_PADATA=y
+CONFIG_PAGE_COUNTER=y
 CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PANIC_ON_OOPS is not set
 CONFIG_PANIC_ON_OOPS_VALUE=0
@@ -536,17 +642,15 @@ CONFIG_PCIEASPM=y
 CONFIG_PCIEASPM_DEFAULT=y
 # CONFIG_PCIEASPM_PERFORMANCE is not set
 # CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
 CONFIG_PCIE_PME=y
+CONFIG_PCI_BUS_ADDR_T_64BIT=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_DOMAINS_GENERIC=y
 CONFIG_PCI_ECAM=y
 CONFIG_PCI_HOST_COMMON=y
 CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_LABEL=y
 CONFIG_PCI_LAYERSCAPE=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
@@ -557,6 +661,8 @@ CONFIG_PHYLIB=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_PID_NS=y
 CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_PALMAS=y
 CONFIG_PL310_ERRATA_588369=y
 CONFIG_PL310_ERRATA_727915=y
 CONFIG_PL310_ERRATA_753970=y
@@ -572,6 +678,7 @@ CONFIG_PM_SLEEP_SMP=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_POSIX_MQUEUE_SYSCTL=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_BRCMKONA=y
 CONFIG_POWER_RESET_BRCMSTB=y
 CONFIG_POWER_RESET_GPIO=y
@@ -581,10 +688,12 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y
 CONFIG_POWER_RESET_VEXPRESS=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_PPS=y
+CONFIG_PREEMPT_NOTIFIERS=y
 CONFIG_PRINTK_TIME=y
-CONFIG_PROBE_EVENTS=y
+# CONFIG_PROBE_EVENTS is not set
 CONFIG_PROC_CHILDREN=y
 CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
 CONFIG_PSTORE=y
 CONFIG_PSTORE_CONSOLE=y
 # CONFIG_PSTORE_LZ4_COMPRESS is not set
@@ -594,13 +703,18 @@ CONFIG_PSTORE_RAM=y
 CONFIG_PSTORE_ZLIB_COMPRESS=y
 CONFIG_PTP_1588_CLOCK=y
 CONFIG_PTP_1588_CLOCK_GIANFAR=y
+CONFIG_PWM=y
+# CONFIG_PWM_IMX is not set
+# CONFIG_PWM_STMPE is not set
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_TWL is not set
+# CONFIG_PWM_TWL_LED is not set
 CONFIG_QORIQ_CPUFREQ=y
 # CONFIG_QUICC_ENGINE is not set
 CONFIG_RAS=y
 CONFIG_RATIONAL=y
 CONFIG_RCU_CPU_STALL_TIMEOUT=21
 # CONFIG_RCU_EXPERT is not set
-CONFIG_RCU_NEED_SEGCBLIST=y
 CONFIG_RCU_STALL_COMMON=y
 CONFIG_RD_BZIP2=y
 CONFIG_RD_GZIP=y
@@ -613,32 +727,89 @@ CONFIG_REED_SOLOMON_DEC8=y
 CONFIG_REED_SOLOMON_ENC8=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_REGMAP_SPI=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ACT8865=y
+CONFIG_REGULATOR_ACT8945A=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_AS3711=y
+CONFIG_REGULATOR_AS3722=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BCM590XX=y
+CONFIG_REGULATOR_DA9210=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_LP872X=y
+# CONFIG_REGULATOR_MAX14577 is not set
+CONFIG_REGULATOR_MAX77686=y
+# CONFIG_REGULATOR_MAX77802 is not set
+CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_MAX8973=y
+# CONFIG_REGULATOR_MAX8997 is not set
+# CONFIG_REGULATOR_MAX8998 is not set
+CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_PWM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_S2MPA01 is not set
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_REGULATOR_TPS51632=y
+CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_REGULATOR_TPS65217=y
+CONFIG_REGULATOR_TPS65218=y
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_REGULATOR_TWL4030=y
+CONFIG_REGULATOR_VEXPRESS=y
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RFS_ACCEL=y
-CONFIG_RING_BUFFER=y
 CONFIG_RPS=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AS3722=y
 # CONFIG_RTC_DRV_CMOS is not set
 CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1307_HWMON=y
 CONFIG_RTC_DRV_DS3232=y
 # CONFIG_RTC_DRV_EFI is not set
 CONFIG_RTC_DRV_EM3027=y
 # CONFIG_RTC_DRV_IMXDI is not set
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_MAX8907=y
+# CONFIG_RTC_DRV_MAX8997 is not set
+# CONFIG_RTC_DRV_MAX8998 is not set
 # CONFIG_RTC_DRV_MXC is not set
+CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_PCF2127=y
 CONFIG_RTC_DRV_PCF85263=y
+# CONFIG_RTC_DRV_RK808 is not set
+# CONFIG_RTC_DRV_S5M is not set
+CONFIG_RTC_DRV_TPS6586X=y
+CONFIG_RTC_DRV_TPS65910=y
+CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
 CONFIG_RWSEM_SPIN_ON_OWNER=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_PMP=y
+CONFIG_SATA_SIL24=y
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHED_INFO is not set
 CONFIG_SCSI=y
 CONFIG_SECCOMP=y
 CONFIG_SECCOMP_FILTER=y
 # CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_SENSORS_ISL29018=y
+CONFIG_SENSORS_ISL29028=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_LM95245=y
 CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_EM=y
@@ -682,7 +853,6 @@ CONFIG_SPARSE_IRQ=y
 CONFIG_SPI=y
 CONFIG_SPI_BITBANG=y
 CONFIG_SPI_CADENCE=y
-# CONFIG_SPI_FSL_LPSPI is not set
 # CONFIG_SPI_FSL_QUADSPI is not set
 # CONFIG_SPI_IMX is not set
 CONFIG_SPI_MASTER=y
@@ -696,16 +866,17 @@ CONFIG_SQUASHFS_FILE_CACHE=y
 CONFIG_SQUASHFS_LZO=y
 CONFIG_SQUASHFS_ZLIB=y
 CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
 CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
 CONFIG_STAGING_BOARD=y
+CONFIG_STMPE_I2C=y
+# CONFIG_STMPE_SPI is not set
 # CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
 CONFIG_SWIOTLB=y
 CONFIG_SWPHY=y
 CONFIG_SWP_EMULATE=y
+# CONFIG_SW_SYNC is not set
 CONFIG_SYNC_FILE=y
 # CONFIG_SYN_COOKIES is not set
 CONFIG_SYSFS_SYSCALL=y
@@ -714,20 +885,18 @@ CONFIG_SYS_SUPPORTS_HUGETLBFS=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_THERMAL=y
 CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
 CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
 CONFIG_THERMAL_OF=y
 # CONFIG_THUMB2_KERNEL is not set
 CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
 CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TRACEPOINTS=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TRACING=y
 CONFIG_TRACING_EVENTS_GPIO=y
 CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
+CONFIG_TUN=y
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_TWL4030_WATCHDOG is not set
 CONFIG_UBIFS_FS=y
 # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
 CONFIG_UBIFS_FS_LZO=y
@@ -736,19 +905,19 @@ CONFIG_UCS2_STRING=y
 CONFIG_UEVENT_HELPER_PATH=""
 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 CONFIG_UNIX_DIAG=y
-CONFIG_UPROBES=y
-CONFIG_UPROBE_EVENTS=y
-CONFIG_USB_SUPPORT=y
 CONFIG_USER_NS=y
 CONFIG_USE_OF=y
 CONFIG_UTS_NS=y
 CONFIG_VDSO=y
 CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VETH=y
 CONFIG_VEXPRESS_CONFIG=y
 CONFIG_VEXPRESS_SYSCFG=y
 CONFIG_VFAT_FS=y
 CONFIG_VFP=y
 CONFIG_VFPv3=y
+CONFIG_VHOST=y
+CONFIG_VHOST_NET=y
 CONFIG_VIRTIO=y
 CONFIG_VIRTIO_BLK=y
 CONFIG_VIRTIO_CONSOLE=y
@@ -757,6 +926,7 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_NET=y
 CONFIG_VIRTIO_PCI=y
 CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTUALIZATION=y
 CONFIG_VITESSE_PHY=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_VT=y
@@ -765,6 +935,8 @@ CONFIG_VT_CONSOLE_SLEEP=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_WATCHDOG_CORE=y
 # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
 CONFIG_XILINX_WATCHDOG=y
 CONFIG_XPS=y
 CONFIG_XZ_DEC_ARM=y
diff --git a/target/linux/layerscape/armv8_32b/config-4.14 b/target/linux/layerscape/armv8_32b/config-4.9
similarity index 71%
rename from target/linux/layerscape/armv8_32b/config-4.14
rename to target/linux/layerscape/armv8_32b/config-4.9
index 89cb55bb8..d5bedb4ee 100644
--- a/target/linux/layerscape/armv8_32b/config-4.14
+++ b/target/linux/layerscape/armv8_32b/config-4.9
@@ -1,19 +1,20 @@
+CONFIG_ABX500_CORE=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
 # CONFIG_AD525X_DPOT_SPI is not set
+CONFIG_AHCI_IMX=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_AK8975=y
 CONFIG_ALIGNMENT_TRAP=y
 CONFIG_APDS9802ALS=y
 CONFIG_AQUANTIA_PHY=y
 # CONFIG_ARCH_AXXIA is not set
 CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
 CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
 CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
 CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
 CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
 CONFIG_ARCH_HAS_TICK_BROADCAST=y
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
@@ -24,8 +25,6 @@ CONFIG_ARCH_MULTI_V6_V7=y
 CONFIG_ARCH_MULTI_V7=y
 CONFIG_ARCH_MXC=y
 CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
 CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
@@ -35,9 +34,11 @@ CONFIG_ARCH_SUPPORTS_UPROBES=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_ARCH_USE_BUILTIN_BSWAP=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
 CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
 CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ARCH_TIMER=y
 CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
@@ -46,6 +47,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
 CONFIG_ARM_CPUIDLE=y
 CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CRYPTO=y
 CONFIG_ARM_ERRATA_430973=y
 CONFIG_ARM_ERRATA_643719=y
 CONFIG_ARM_ERRATA_720789=y
@@ -55,18 +57,23 @@ CONFIG_ARM_ERRATA_764369=y
 CONFIG_ARM_ERRATA_775420=y
 CONFIG_ARM_ERRATA_798181=y
 CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
 CONFIG_ARM_HAS_SG_CHAIN=y
 CONFIG_ARM_HEAVY_MB=y
 # CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_IMX6Q_CPUFREQ=y
 CONFIG_ARM_L1_CACHE_SHIFT=6
 CONFIG_ARM_L1_CACHE_SHIFT_6=y
 CONFIG_ARM_LPAE=y
 CONFIG_ARM_PATCH_IDIV=y
 CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_PL172_MPMC is not set
 CONFIG_ARM_PMU=y
 CONFIG_ARM_PSCI=y
 CONFIG_ARM_PSCI_FW=y
 # CONFIG_ARM_SMMU is not set
+CONFIG_ARM_SP805_WATCHDOG=y
 CONFIG_ARM_THUMB=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_TIMER_SP804=y
@@ -74,18 +81,37 @@ CONFIG_ARM_UNWIND=y
 CONFIG_ARM_VIRT_EXT=y
 CONFIG_ASSOCIATIVE_ARRAY=y
 CONFIG_AT803X_PHY=y
+CONFIG_ATA=y
 CONFIG_ATAGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AXP20X_POWER is not set
+CONFIG_BACKLIGHT_AS3711=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_GENERIC=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_TPS65217 is not set
+CONFIG_BATTERY_ACT8945A=y
 CONFIG_BATTERY_SBS=y
+CONFIG_BCMA=y
+CONFIG_BCMA_BLOCKIO=y
+# CONFIG_BCMA_DEBUG is not set
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_SFLASH=y
 CONFIG_BCM_NET_PHYLIB=y
-CONFIG_BINARY_PRINTF=y
+# CONFIG_BLK_CGROUP is not set
 CONFIG_BLK_CMDLINE_PARSER=y
 CONFIG_BLK_DEV_BSG=y
 CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+# CONFIG_BLK_DEV_NVME_SCSI is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=262144
@@ -93,10 +119,10 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
 # CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_SCSI_REQUEST=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_BOUNCE=y
 # CONFIG_BPF_SYSCALL is not set
 CONFIG_BRCMSTB_GISB_ARB=y
@@ -119,11 +145,28 @@ CONFIG_CAN_RAW=y
 # CONFIG_CAN_SJA1000 is not set
 # CONFIG_CAN_SOFTING is not set
 # CONFIG_CAN_TI_HECC is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_SCHED=y
+# CONFIG_CHARGER_MAX14577 is not set
+CONFIG_CHARGER_TPS65090=y
+# CONFIG_CHARGER_TPS65217 is not set
 CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHROME_PLATFORMS=y
 CONFIG_CHR_DEV_SG=y
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLKSRC_IMX_GPT=y
 CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_VERSATILE=y
 CONFIG_CLK_QORIQ=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_CMA=y
@@ -138,14 +181,20 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
 # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
 CONFIG_CMDLINE_PARTITION=y
 CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MAX77686=y
+# CONFIG_COMMON_CLK_PALMAS is not set
+# CONFIG_COMMON_CLK_RK808 is not set
+# CONFIG_COMMON_CLK_S2MPS11 is not set
+CONFIG_COMPACTION=y
 CONFIG_COMPAT_BRK=y
 CONFIG_CONFIGFS_FS=y
 CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
 CONFIG_COREDUMP=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_CORTINA_PHY is not set
 CONFIG_CPUFREQ_DT=y
 CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUSETS=y
 CONFIG_CPU_32v6K=y
 CONFIG_CPU_32v7=y
 CONFIG_CPU_ABRT_EV7=y
@@ -174,32 +223,54 @@ CONFIG_CPU_HAS_ASID=y
 CONFIG_CPU_IDLE=y
 # CONFIG_CPU_IDLE_GOV_LADDER is not set
 CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
 CONFIG_CPU_PABRT_V7=y
 CONFIG_CPU_PM=y
 CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
 CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
 CONFIG_CPU_TLB_V7=y
 CONFIG_CPU_V7=y
-CONFIG_CRASH_CORE=y
 CONFIG_CRC16=y
 # CONFIG_CRC32_SARWATE is not set
 CONFIG_CRC32_SLICEBY8=y
 CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_ACOMP2=y
 CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
+# CONFIG_CRYPTO_AES_ARM_CE is not set
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
 CONFIG_CRYPTO_CRC32C=y
 CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
+# CONFIG_CRYPTO_DEV_MXC_SCC is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECHAINIV=y
+# CONFIG_CRYPTO_GHASH_ARM_CE is not set
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
 CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA1_ARM_CE is not set
+# CONFIG_CRYPTO_SHA1_ARM_NEON is not set
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_SHA256_ARM is not set
+# CONFIG_CRYPTO_SHA2_ARM_CE is not set
+# CONFIG_CRYPTO_SHA512_ARM is not set
 # CONFIG_CRYPTO_TLS is not set
 CONFIG_CRYPTO_WORKQUEUE=y
 CONFIG_DCACHE_WORD_ACCESS=y
@@ -207,6 +278,7 @@ CONFIG_DEBUG_ALIGN_RODATA=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_IMX_UART_PORT=1
 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_RODATA=y
 # CONFIG_DEBUG_UART_8250 is not set
 # CONFIG_DEBUG_USER is not set
 CONFIG_DECOMPRESS_BZIP2=y
@@ -219,8 +291,12 @@ CONFIG_DEFAULT_CFQ=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
 CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEVKMEM=y
-CONFIG_DEVMEM=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+# CONFIG_DEVFREQ_THERMAL is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_DMADEVICES=y
@@ -229,31 +305,34 @@ CONFIG_DMA_ENGINE=y
 CONFIG_DMA_OF=y
 CONFIG_DMA_SHARED_BUFFER=y
 CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DMI=y
-CONFIG_DMIID=y
-# CONFIG_DMI_SYSFS is not set
 CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
 CONFIG_DRM=y
 CONFIG_DRM_BRIDGE=y
 CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
 CONFIG_DRM_FSL_DCU=y
 CONFIG_DRM_GEM_CMA_HELPER=y
 CONFIG_DRM_KMS_CMA_HELPER=y
 CONFIG_DRM_KMS_FB_HELPER=y
 CONFIG_DRM_KMS_HELPER=y
 CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_DRM_SII902X=y
 # CONFIG_DRM_VIRTIO_GPU is not set
+CONFIG_DST_CACHE=y
 CONFIG_DTC=y
 CONFIG_DT_IDLE_STATES=y
 CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_GENERIC=y
 CONFIG_DW_DMAC=y
 CONFIG_DW_DMAC_CORE=y
 CONFIG_DW_WATCHDOG=y
+CONFIG_E1000E=y
+CONFIG_EDAC=y
 CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+# CONFIG_EDAC_MM_EDAC is not set
 CONFIG_EDAC_SUPPORT=y
 CONFIG_EEPROM_93CX6=y
 CONFIG_EEPROM_AT24=y
@@ -270,12 +349,18 @@ CONFIG_EFI_STUB=y
 CONFIG_ELF_CORE=y
 # CONFIG_ENABLE_DEFAULT_TRACERS is not set
 CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_EVENT_TRACING=y
+CONFIG_EXPORTFS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+# CONFIG_EXTCON_MAX14577 is not set
+# CONFIG_EXTCON_MAX8997 is not set
+# CONFIG_EXTCON_PALMAS is not set
+CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_FAT_FS=y
 CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -284,7 +369,6 @@ CONFIG_FB_DEFERRED_IO=y
 CONFIG_FB_EFI=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_MX3=y
-# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
 CONFIG_FB_SIMPLE=y
 CONFIG_FB_SYS_COPYAREA=y
 CONFIG_FB_SYS_FILLRECT=y
@@ -314,7 +398,6 @@ CONFIG_FREEZER=y
 CONFIG_FSL_BMAN_CONFIG=y
 CONFIG_FSL_BMAN_DEBUGFS=y
 # CONFIG_FSL_BMAN_TEST is not set
-# CONFIG_FSL_DPAA2_ETH_CEETM is not set
 # CONFIG_FSL_DPAA_1588 is not set
 CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y
 # CONFIG_FSL_DPAA_CEETM is not set
@@ -376,16 +459,14 @@ CONFIG_FTRACE=y
 CONFIG_FUSE_FS=y
 # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_EARLY_IOREMAP=y
 CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IO=y
 CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 CONFIG_GENERIC_MSI_IRQ=y
@@ -393,8 +474,6 @@ CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_GENERIC_PHY=y
 CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
@@ -403,11 +482,25 @@ CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GIANFAR=y
 CONFIG_GLOB=y
 CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_GPIO_AXP209 is not set
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_EM=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MPC8XXX=y
 CONFIG_GPIO_MXC=y
-# CONFIG_GRO_CELLS is not set
+CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_PL061=y
+# CONFIG_GPIO_STMPE is not set
+CONFIG_GPIO_SYSCON=y
+# CONFIG_GPIO_TPS65218 is not set
+CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TWL4030=y
+CONFIG_GPIO_XILINX=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HARDEN_BRANCH_PREDICTOR=y
 CONFIG_HARDIRQS_SW_RESEND=y
@@ -426,6 +519,7 @@ CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
 CONFIG_HAVE_ARM_ARCH_TIMER=y
 CONFIG_HAVE_ARM_SMCCC=y
 # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
 CONFIG_HAVE_CC_STACKPROTECTOR=y
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_CLK_PREPARE=y
@@ -435,18 +529,22 @@ CONFIG_HAVE_DEBUG_KMEMLEAK=y
 CONFIG_HAVE_DMA_API_DEBUG=y
 CONFIG_HAVE_DMA_CONTIGUOUS=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_HAVE_EBPF_JIT=y
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_GUP=y
+CONFIG_HAVE_GENERIC_RCU_GUP=y
 CONFIG_HAVE_HW_BREAKPOINT=y
 CONFIG_HAVE_IDE=y
 CONFIG_HAVE_IMX_SRC=y
 CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
 CONFIG_HAVE_MEMBLOCK=y
 CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
 CONFIG_HAVE_NET_DSA=y
@@ -467,12 +565,13 @@ CONFIG_HID=y
 CONFIG_HID_GENERIC=y
 CONFIG_HIGHMEM=y
 CONFIG_HIGHPTE=y
+CONFIG_HIX5HD2_GMAC=y
 CONFIG_HOTPLUG_CPU=y
 # CONFIG_HUGETLBFS is not set
 CONFIG_HVC_DRIVER=y
+CONFIG_HWMON=y
 CONFIG_HW_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_IMX_RNGC=y
 CONFIG_HZ_FIXED=0
 CONFIG_I2C=y
 CONFIG_I2C_ALGOBIT=y
@@ -482,35 +581,55 @@ CONFIG_I2C_COMPAT=y
 CONFIG_I2C_DEMUX_PINCTRL=y
 CONFIG_I2C_DESIGNWARE_CORE=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
 CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_IMX=y
-# CONFIG_I2C_IMX_LPI2C is not set
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_MUX_PINCTRL=y
+CONFIG_I2C_NOMADIK=y
 CONFIG_I2C_RK3X=y
 CONFIG_I2C_SLAVE=y
 CONFIG_I2C_SLAVE_EEPROM=y
 CONFIG_I2C_XILINX=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_ICS932S401=y
+CONFIG_IGB=y
+CONFIG_IGB_HWMON=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONFIGFS=y
+CONFIG_IIO_HRTIMER_TRIGGER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_SW_TRIGGER=y
+# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_IMX2_WDT=y
 CONFIG_IMX_DMA=y
 CONFIG_IMX_SDMA=y
 # CONFIG_IMX_WEIM is not set
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
 CONFIG_INET_DIAG=y
 # CONFIG_INET_DIAG_DESTROY is not set
-# CONFIG_INET_RAW_DIAG is not set
+CONFIG_INET_ESP=y
 CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_INPUT=y
+# CONFIG_INPUT_AXP20X_PEK is not set
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
 CONFIG_INPUT_MATRIXKMAP=y
+# CONFIG_INPUT_MAX8997_HAPTIC is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_PSAUX=y
@@ -523,7 +642,17 @@ CONFIG_IOMMU_HELPER=y
 CONFIG_IOMMU_SUPPORT=y
 CONFIG_IOSCHED_CFQ=y
 CONFIG_IPC_NS=y
+CONFIG_IPV6=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SUBTREES is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
@@ -542,12 +671,30 @@ CONFIG_KEYBOARD_ATKBD=y
 CONFIG_KEYBOARD_BCM=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_KEYBOARD_IMX is not set
+# CONFIG_KEYBOARD_STMPE is not set
 CONFIG_KEYS=y
+CONFIG_KS8851=y
+CONFIG_KVM=y
+CONFIG_KVM_ARM_HOST=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
 # CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_MAX8997 is not set
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_LIBFDT=y
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCKUP_DETECTOR=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
 CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_CLUT224=y
@@ -557,36 +704,74 @@ CONFIG_LS_SCFG_MSI=y
 # CONFIG_LS_SOC_DRIVERS is not set
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACVLAN=y
+CONFIG_MACVTAP=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
 CONFIG_MANDATORY_FILE_LOCKING=y
 CONFIG_MARVELL_PHY=y
 CONFIG_MCPM=y
 CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BOARDINFO=y
 CONFIG_MDIO_BUS_MUX=y
 CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_DEVICE=y
 # CONFIG_MDIO_FSL_BACKPLANE is not set
 # CONFIG_MDIO_GPIO is not set
+CONFIG_MEMCG=y
+# CONFIG_MEMCG_SWAP is not set
 CONFIG_MEMORY=y
 CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_ACT8945A=y
+CONFIG_MFD_AS3711=y
+CONFIG_MFD_AS3722=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_BCM590XX=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MAX14577=y
+CONFIG_MFD_MAX77686=y
+CONFIG_MFD_MAX8907=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_MAX8998=y
+CONFIG_MFD_PALMAS=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_STMPE=y
 CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_VEXPRESS_SYSREG is not set
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS65217=y
+CONFIG_MFD_TPS65218=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+# CONFIG_MFD_TWL4030_AUDIO is not set
+CONFIG_MFD_VEXPRESS_SYSREG=y
 CONFIG_MICREL_PHY=y
 CONFIG_MIGHT_HAVE_CACHE_L2X0=y
 CONFIG_MIGHT_HAVE_PCI=y
 CONFIG_MIGRATION=y
 CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
 # CONFIG_MMC_MXC is not set
 CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_AT91=y
 CONFIG_MMC_SDHCI_OF_ESDHC=y
 # CONFIG_MMC_SDHCI_PCI is not set
 CONFIG_MMC_SDHCI_PLTFM=y
 # CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMU_NOTIFIER=y
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_MODULES_USE_ELF_REL=y
 # CONFIG_MOUSE_BCM5974 is not set
@@ -601,14 +786,13 @@ CONFIG_MOUSE_PS2_CYPRESS=y
 CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_MOUSE_PS2_FOCALTECH=y
 CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
 CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 CONFIG_MSDOS_FS=y
+# CONFIG_MTD_BCM47XXSFLASH is not set
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 CONFIG_MTD_CFI_STAA=y
@@ -619,6 +803,9 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_DENALI=y
+CONFIG_MTD_NAND_DENALI_DT=y
 CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND_FSL_IFC=y
 CONFIG_MTD_SPI_NOR=y
@@ -633,22 +820,22 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
 CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_MULTI_IRQ_HANDLER=y
 CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MVMDIO=y
 CONFIG_MX3_IPU=y
 CONFIG_MX3_IPU_IRQS=4
-# CONFIG_MXS_DMA is not set
 CONFIG_NAMESPACES=y
 CONFIG_NATIONAL_PHY=y
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEON=y
-# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_CLS_CGROUP is not set
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_IP_TUNNEL=y
 CONFIG_NET_NS=y
 CONFIG_NET_PTP_CLASSIFY=y
 CONFIG_NLS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=y
-CONFIG_NOP_TRACER=y
 CONFIG_NO_BOOTMEM=y
 CONFIG_NO_HZ=y
 CONFIG_NO_HZ_COMMON=y
@@ -656,7 +843,7 @@ CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=16
 CONFIG_NTFS_FS=y
 CONFIG_NVMEM=y
-# CONFIG_NVMEM_IMX_IIM is not set
+CONFIG_NVME_CORE=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_ADDRESS_PCI=y
@@ -675,11 +862,12 @@ CONFIG_OLD_SIGSUSPEND3=y
 CONFIG_OUTER_CACHE=y
 CONFIG_OUTER_CACHE_SYNC=y
 CONFIG_PACKET_DIAG=y
-CONFIG_PADATA=y
+CONFIG_PAGE_COUNTER=y
 CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PANIC_ON_OOPS is not set
 CONFIG_PANIC_ON_OOPS_VALUE=0
 CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARTITION_PERCPU=y
 CONFIG_PCI=y
 CONFIG_PCIEAER=y
 CONFIG_PCIEASPM=y
@@ -687,17 +875,15 @@ CONFIG_PCIEASPM=y
 CONFIG_PCIEASPM_DEFAULT=y
 # CONFIG_PCIEASPM_PERFORMANCE is not set
 # CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
 CONFIG_PCIE_PME=y
+CONFIG_PCI_BUS_ADDR_T_64BIT=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_DOMAINS_GENERIC=y
 CONFIG_PCI_ECAM=y
 CONFIG_PCI_HOST_COMMON=y
 CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_LABEL=y
 CONFIG_PCI_LAYERSCAPE=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
@@ -708,19 +894,28 @@ CONFIG_PHYLIB=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_PID_NS=y
 CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_PALMAS=y
 CONFIG_PL310_ERRATA_588369=y
 CONFIG_PL310_ERRATA_727915=y
 CONFIG_PL310_ERRATA_753970=y
 CONFIG_PL310_ERRATA_769419=y
+CONFIG_PL320_MBOX=y
+CONFIG_PL330_DMA=y
+# CONFIG_PLAT_VERSATILE_CLCD is not set
 CONFIG_PM=y
 CONFIG_PM_CLK=y
 # CONFIG_PM_DEBUG is not set
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
 CONFIG_PM_OPP=y
 CONFIG_PM_SLEEP=y
 CONFIG_PM_SLEEP_SMP=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_AVS=y
 CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_BRCMKONA=y
 CONFIG_POWER_RESET_BRCMSTB=y
 CONFIG_POWER_RESET_GPIO=y
@@ -730,9 +925,11 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y
 CONFIG_POWER_RESET_VEXPRESS=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_PPS=y
+CONFIG_PREEMPT_NOTIFIERS=y
 CONFIG_PRINTK_TIME=y
-CONFIG_PROBE_EVENTS=y
+# CONFIG_PROBE_EVENTS is not set
 CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_PID_CPUSET=y
 CONFIG_PSTORE=y
 CONFIG_PSTORE_CONSOLE=y
 # CONFIG_PSTORE_LZ4_COMPRESS is not set
@@ -743,14 +940,20 @@ CONFIG_PSTORE_ZLIB_COMPRESS=y
 CONFIG_PTP_1588_CLOCK=y
 # CONFIG_PTP_1588_CLOCK_DPAA is not set
 CONFIG_PTP_1588_CLOCK_GIANFAR=y
+CONFIG_PWM=y
+# CONFIG_PWM_IMX is not set
+# CONFIG_PWM_STMPE is not set
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_TWL is not set
+# CONFIG_PWM_TWL_LED is not set
 CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
 CONFIG_QORIQ_CPUFREQ=y
 # CONFIG_QUICC_ENGINE is not set
+CONFIG_R8169=y
 CONFIG_RAS=y
 CONFIG_RATIONAL=y
 CONFIG_RCU_CPU_STALL_TIMEOUT=21
 # CONFIG_RCU_EXPERT is not set
-CONFIG_RCU_NEED_SEGCBLIST=y
 CONFIG_RCU_STALL_COMMON=y
 CONFIG_RD_BZIP2=y
 CONFIG_RD_GZIP=y
@@ -763,31 +966,90 @@ CONFIG_REED_SOLOMON_DEC8=y
 CONFIG_REED_SOLOMON_ENC8=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_REGMAP_SPI=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ACT8865=y
+CONFIG_REGULATOR_ACT8945A=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_AS3711=y
+CONFIG_REGULATOR_AS3722=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BCM590XX=y
+CONFIG_REGULATOR_DA9210=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_LP872X=y
+# CONFIG_REGULATOR_MAX14577 is not set
+CONFIG_REGULATOR_MAX77686=y
+# CONFIG_REGULATOR_MAX77802 is not set
+CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_MAX8973=y
+# CONFIG_REGULATOR_MAX8997 is not set
+# CONFIG_REGULATOR_MAX8998 is not set
+CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_PWM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_S2MPA01 is not set
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_REGULATOR_TPS51632=y
+CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_REGULATOR_TPS65217=y
+CONFIG_REGULATOR_TPS65218=y
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_REGULATOR_TWL4030=y
+CONFIG_REGULATOR_VEXPRESS=y
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RFS_ACCEL=y
-CONFIG_RING_BUFFER=y
 CONFIG_RPS=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AS3722=y
 # CONFIG_RTC_DRV_CMOS is not set
 CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1307_HWMON=y
 CONFIG_RTC_DRV_DS3232=y
 # CONFIG_RTC_DRV_EFI is not set
 CONFIG_RTC_DRV_EM3027=y
 # CONFIG_RTC_DRV_IMXDI is not set
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_MAX8907=y
+# CONFIG_RTC_DRV_MAX8997 is not set
+# CONFIG_RTC_DRV_MAX8998 is not set
 # CONFIG_RTC_DRV_MXC is not set
+CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_PCF2127=y
 CONFIG_RTC_DRV_PCF85263=y
+CONFIG_RTC_DRV_PL031=y
+# CONFIG_RTC_DRV_RK808 is not set
+# CONFIG_RTC_DRV_S5M is not set
+CONFIG_RTC_DRV_TPS6586X=y
+CONFIG_RTC_DRV_TPS65910=y
+CONFIG_RTC_DRV_TWL4030=y
 CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
 CONFIG_RWSEM_SPIN_ON_OWNER=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_MV=y
+CONFIG_SATA_PMP=y
+CONFIG_SATA_SIL24=y
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHED_INFO is not set
 CONFIG_SCSI=y
 CONFIG_SECCOMP=y
 CONFIG_SECCOMP_FILTER=y
+CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_SENSORS_ISL29018=y
+CONFIG_SENSORS_ISL29028=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_LM95245=y
 CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_EM=y
@@ -795,6 +1057,8 @@ CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_PCI=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_BCM63XX=y
 CONFIG_SERIAL_BCM63XX_CONSOLE=y
 CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
@@ -810,12 +1074,15 @@ CONFIG_SERIAL_ST_ASC_CONSOLE=y
 CONFIG_SERIAL_XILINX_PS_UART=y
 CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
 CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIO_SERPORT=y
 CONFIG_SG_POOL=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_SMP=y
 CONFIG_SMP_ON_UP=y
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
 CONFIG_SMSC_PHY=y
 CONFIG_SOCK_DIAG=y
 CONFIG_SOC_BRCMSTB=y
@@ -834,10 +1101,10 @@ CONFIG_SPARSE_IRQ=y
 CONFIG_SPI=y
 CONFIG_SPI_BITBANG=y
 CONFIG_SPI_CADENCE=y
-# CONFIG_SPI_FSL_LPSPI is not set
 CONFIG_SPI_FSL_QUADSPI=y
 # CONFIG_SPI_IMX is not set
 CONFIG_SPI_MASTER=y
+CONFIG_SPI_PL022=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPI_XILINX=y
 CONFIG_SPMI=y
@@ -848,16 +1115,19 @@ CONFIG_SQUASHFS_FILE_CACHE=y
 CONFIG_SQUASHFS_LZO=y
 CONFIG_SQUASHFS_ZLIB=y
 CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
 CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
 CONFIG_STAGING_BOARD=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STMPE_I2C=y
+# CONFIG_STMPE_SPI is not set
 # CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
 CONFIG_SWIOTLB=y
 CONFIG_SWPHY=y
 CONFIG_SWP_EMULATE=y
+# CONFIG_SW_SYNC is not set
 CONFIG_SYNC_FILE=y
 # CONFIG_SYN_COOKIES is not set
 CONFIG_SYSFS_SYSCALL=y
@@ -866,21 +1136,21 @@ CONFIG_SYS_SUPPORTS_HUGETLBFS=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_THERMAL=y
 CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
 CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
 CONFIG_THERMAL_OF=y
 # CONFIG_THUMB2_KERNEL is not set
 CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
+CONFIG_TI_CPSW_ALE=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_TOUCHSCREEN_PROPERTIES=y
-CONFIG_TRACEPOINTS=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TRACING=y
+CONFIG_TOUCHSCREEN_STMPE=y
 CONFIG_TRACING_EVENTS_GPIO=y
 CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
+CONFIG_TUN=y
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_TWL4030_WATCHDOG is not set
 CONFIG_UBIFS_FS=y
 # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
 CONFIG_UBIFS_FS_LZO=y
@@ -889,8 +1159,7 @@ CONFIG_UCS2_STRING=y
 CONFIG_UEVENT_HELPER_PATH=""
 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 CONFIG_UNIX_DIAG=y
-CONFIG_UPROBES=y
-CONFIG_UPROBE_EVENTS=y
+# CONFIG_USB_IMX21_HCD is not set
 CONFIG_USB_SUPPORT=y
 # CONFIG_USERIO is not set
 CONFIG_USER_NS=y
@@ -898,6 +1167,7 @@ CONFIG_USE_OF=y
 CONFIG_UTS_NS=y
 CONFIG_VDSO=y
 CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VETH=y
 CONFIG_VEXPRESS_CONFIG=y
 CONFIG_VEXPRESS_SYSCFG=y
 CONFIG_VFAT_FS=y
@@ -905,6 +1175,8 @@ CONFIG_VFP=y
 CONFIG_VFPv3=y
 CONFIG_VGA_ARB=y
 CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VHOST=y
+CONFIG_VHOST_NET=y
 CONFIG_VIDEOMODE_HELPERS=y
 CONFIG_VIRTIO=y
 CONFIG_VIRTIO_BLK=y
@@ -914,6 +1186,7 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_NET=y
 CONFIG_VIRTIO_PCI=y
 CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTUALIZATION=y
 CONFIG_VITESSE_PHY=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_VT=y
@@ -922,6 +1195,8 @@ CONFIG_VT_CONSOLE_SLEEP=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_WATCHDOG_CORE=y
 # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
 CONFIG_XILINX_WATCHDOG=y
 CONFIG_XPS=y
 CONFIG_XZ_DEC_ARM=y
diff --git a/target/linux/layerscape/armv8_64b/config-4.14 b/target/linux/layerscape/armv8_64b/config-4.9
similarity index 74%
rename from target/linux/layerscape/armv8_64b/config-4.14
rename to target/linux/layerscape/armv8_64b/config-4.9
index 782da4e3f..c59cf6199 100644
--- a/target/linux/layerscape/armv8_64b/config-4.14
+++ b/target/linux/layerscape/armv8_64b/config-4.9
@@ -1,21 +1,43 @@
 CONFIG_64BIT=y
-# CONFIG_ACPI is not set
-# CONFIG_AHCI_XGENE is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CCA_REQUIRED=y
+CONFIG_ACPI_CONTAINER=y
+# CONFIG_ACPI_CPPC_CPUFREQ is not set
+# CONFIG_ACPI_CUSTOM_DSDT is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_IORT=y
+CONFIG_ACPI_MCFG=y
+CONFIG_ACPI_NUMA=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_AHCI_XGENE=y
+CONFIG_AMD_XGBE=y
 CONFIG_AQUANTIA_PHY=y
 CONFIG_ARCH_CLOCKSOURCE_DATA=y
 CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
 CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
-CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
 CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
 CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
 CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
 CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
 CONFIG_ARCH_HAS_KCOV=y
-CONFIG_ARCH_HAS_SET_MEMORY=y
 CONFIG_ARCH_HAS_SG_CHAIN=y
-CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
-CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
 CONFIG_ARCH_HAS_TICK_BROADCAST=y
 CONFIG_ARCH_HIBERNATION_HEADER=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
@@ -25,18 +47,13 @@ CONFIG_ARCH_MMAP_RND_BITS_MAX=33
 CONFIG_ARCH_MMAP_RND_BITS_MIN=18
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
-# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
 CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_ARCH_SPARSEMEM_DEFAULT=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
 CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
-CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
 CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
-CONFIG_ARCH_SUPPORTS_UPROBES=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
@@ -46,13 +63,15 @@ CONFIG_ARM64=y
 # CONFIG_ARM64_16K_PAGES is not set
 CONFIG_ARM64_4K_PAGES=y
 # CONFIG_ARM64_64K_PAGES is not set
+# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set
 CONFIG_ARM64_CONT_SHIFT=4
-# CONFIG_ARM64_CRYPTO is not set
+CONFIG_ARM64_CRYPTO=y
 CONFIG_ARM64_ERRATUM_819472=y
 CONFIG_ARM64_ERRATUM_824069=y
 CONFIG_ARM64_ERRATUM_826319=y
 CONFIG_ARM64_ERRATUM_827319=y
 CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_834220=y
 CONFIG_ARM64_ERRATUM_843419=y
 CONFIG_ARM64_ERRATUM_845719=y
 CONFIG_ARM64_HW_AFDBM=y
@@ -60,12 +79,9 @@ CONFIG_ARM64_HW_AFDBM=y
 CONFIG_ARM64_MODULE_CMODEL_LARGE=y
 CONFIG_ARM64_PAGE_SHIFT=12
 CONFIG_ARM64_PAN=y
-# CONFIG_ARM64_PMEM is not set
-# CONFIG_ARM64_PTDUMP_CORE is not set
-# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
+# CONFIG_ARM64_PTDUMP is not set
 # CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
 CONFIG_ARM64_SSBD=y
-# CONFIG_ARM64_SW_TTBR0_PAN is not set
 CONFIG_ARM64_UAO=y
 CONFIG_ARM64_VA_BITS=48
 # CONFIG_ARM64_VA_BITS_39 is not set
@@ -75,7 +91,6 @@ CONFIG_ARM64_VHE=y
 CONFIG_ARM_AMBA=y
 CONFIG_ARM_ARCH_TIMER=y
 CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
 CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
 CONFIG_ARM_CPUIDLE=y
 # CONFIG_ARM_DT_BL_CPUFREQ is not set
@@ -91,8 +106,13 @@ CONFIG_ARM_SMMU=y
 CONFIG_ARM_SMMU_V3=y
 CONFIG_ARM_SP805_WATCHDOG=y
 CONFIG_ARM_TIMER_SP804=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ASYNC_CORE=y
 CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
 CONFIG_ATA=y
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_VERBOSE_ERROR=y
 CONFIG_AUDIT=y
 CONFIG_AUDITSYSCALL=y
 CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
@@ -103,27 +123,31 @@ CONFIG_AUDIT_WATCH=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKLIGHT_PWM is not set
 CONFIG_BALLOON_COMPACTION=y
 CONFIG_BATTERY_BQ27XXX=y
-# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
 CONFIG_BATTERY_BQ27XXX_I2C=y
+CONFIG_BLK_CGROUP=y
 CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
 CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+# CONFIG_BLK_DEV_NVME_SCSI is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=262144
 CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_THROTTLING=y
 CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_SCSI_REQUEST=y
 CONFIG_BLOCK_COMPAT=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_BOUNCE=y
 CONFIG_BPF_JIT=y
 # CONFIG_BPF_SYSCALL is not set
+CONFIG_BRIDGE_VLAN_FILTERING=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 CONFIG_BTRFS_FS=y
@@ -134,14 +158,35 @@ CONFIG_CAVIUM_ERRATUM_22375=y
 CONFIG_CAVIUM_ERRATUM_23144=y
 CONFIG_CAVIUM_ERRATUM_23154=y
 CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_CEPH_LIB=y
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+CONFIG_CFQ_GROUP_IOSCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_WRITEBACK=y
 CONFIG_CHECKPOINT_RESTORE=y
 CONFIG_CHROME_PLATFORMS=y
 CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_ACPI=y
 CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_VERSATILE=y
 CONFIG_CLK_QORIQ=y
 CONFIG_CLK_SP810=y
 CONFIG_CLK_VEXPRESS_OSC=y
 CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
 CONFIG_CMA=y
 CONFIG_CMA_ALIGNMENT=8
 CONFIG_CMA_AREAS=7
@@ -154,8 +199,13 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
 # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
 CONFIG_COMMON_CLK=y
 CONFIG_COMMON_CLK_CS2000_CP=y
+# CONFIG_COMMON_CLK_MAX77686 is not set
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_S2MPS11=y
 CONFIG_COMMON_CLK_VERSATILE=y
 CONFIG_COMMON_CLK_XGENE=y
+CONFIG_COMPACTION=y
 CONFIG_COMPAT=y
 CONFIG_COMPAT_BINFMT_ELF=y
 CONFIG_COMPAT_NETLINK_MESSAGES=y
@@ -163,8 +213,10 @@ CONFIG_COMPAT_OLD_SIGACTION=y
 CONFIG_CONFIGFS_FS=y
 CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_COREDUMP=y
+# CONFIG_CORTINA_PHY is not set
 CONFIG_CPUFREQ_DT=y
 CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUSETS=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
@@ -180,11 +232,9 @@ CONFIG_CPU_FREQ_STAT=y
 CONFIG_CPU_IDLE=y
 # CONFIG_CPU_IDLE_GOV_LADDER is not set
 CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
 CONFIG_CPU_PM=y
 CONFIG_CPU_RMAP=y
 CONFIG_CPU_THERMAL=y
-CONFIG_CRASH_CORE=y
 CONFIG_CRC16=y
 # CONFIG_CRC32_SARWATE is not set
 CONFIG_CRC32_SLICEBY8=y
@@ -192,30 +242,79 @@ CONFIG_CRC7=y
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC_T10DIF=y
 CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_ACOMP2=y
+# CONFIG_CROS_EC_CHARDEV is not set
+CONFIG_CROS_EC_PROTO=y
+# CONFIG_CROS_KBD_LED_BACKLIGHT is not set
+CONFIG_CRYPTO_ABLK_HELPER=y
 CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
 CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32_ARM64 is not set
 CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=y
 CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC is not set
-# CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_DMA=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
 CONFIG_CRYPTO_LZO=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512=y
 # CONFIG_CRYPTO_TLS is not set
 CONFIG_CRYPTO_WORKQUEUE=y
 CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_DEBUG_ALIGN_RODATA is not set
+# CONFIG_DEBUG_BLK_CGROUP is not set
 CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_EFI is not set
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_INFO_REDUCED is not set
 CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_RODATA=y
+CONFIG_DEBUG_SET_MODULE_RONX=y
 CONFIG_DECOMPRESS_BZIP2=y
 CONFIG_DECOMPRESS_GZIP=y
 CONFIG_DECOMPRESS_LZMA=y
@@ -225,11 +324,12 @@ CONFIG_DEFAULT_CFQ=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
 CONFIG_DEFAULT_IOSCHED="cfq"
 CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEVMEM=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEV_DAX is not set
 CONFIG_DMADEVICES=y
 CONFIG_DMATEST=y
+CONFIG_DMA_ACPI=y
 CONFIG_DMA_CMA=y
 CONFIG_DMA_ENGINE=y
 CONFIG_DMA_ENGINE_RAID=y
@@ -240,9 +340,13 @@ CONFIG_DMI=y
 CONFIG_DMIID=y
 # CONFIG_DMI_SYSFS is not set
 CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_DST_CACHE=y
 CONFIG_DTC=y
 CONFIG_DT_IDLE_STATES=y
 CONFIG_DUMMY_CONSOLE=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
 CONFIG_EDAC_SUPPORT=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EFI=y
@@ -258,6 +362,8 @@ CONFIG_EFI_STUB=y
 CONFIG_ELF_CORE=y
 # CONFIG_EMBEDDED is not set
 CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_EVM is not set
+CONFIG_EXPORTFS=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 # CONFIG_EXT2_FS_SECURITY is not set
@@ -270,7 +376,9 @@ CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
 CONFIG_EXTCON=y
 CONFIG_EXTCON_USB_GPIO=y
+CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
 CONFIG_FAT_FS=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
@@ -281,7 +389,6 @@ CONFIG_FB_CMDLINE=y
 CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_EFI is not set
 CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
 CONFIG_FB_SYS_COPYAREA=y
 CONFIG_FB_SYS_FILLRECT=y
 CONFIG_FB_SYS_FOPS=y
@@ -310,7 +417,6 @@ CONFIG_FREEZER=y
 CONFIG_FSL_BMAN_CONFIG=y
 CONFIG_FSL_BMAN_DEBUGFS=y
 # CONFIG_FSL_BMAN_TEST is not set
-# CONFIG_FSL_DPAA is not set
 CONFIG_FSL_DPAA2=y
 CONFIG_FSL_DPAA2_ETH=y
 CONFIG_FSL_DPAA2_ETHSW=y
@@ -345,7 +451,6 @@ CONFIG_FSL_DPA_PIRQ_SLOW=y
 CONFIG_FSL_DPA_PORTAL_SHARE=y
 CONFIG_FSL_EDMA=y
 CONFIG_FSL_ERRATUM_A008585=y
-# CONFIG_FSL_FMAN is not set
 CONFIG_FSL_FM_MAX_FRAME_SIZE=1522
 CONFIG_FSL_FM_RX_EXTRA_HEADROOM=64
 CONFIG_FSL_GUTS=y
@@ -389,7 +494,6 @@ CONFIG_FUSE_FS=y
 # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
 CONFIG_GARP=y
 CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
 CONFIG_GENERIC_CLOCKEVENTS=y
@@ -399,7 +503,8 @@ CONFIG_GENERIC_CSUM=y
 CONFIG_GENERIC_EARLY_IOREMAP=y
 CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_CHIP=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
 CONFIG_GENERIC_IRQ_MIGRATION=y
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
@@ -415,11 +520,18 @@ CONFIG_GENERIC_TIME_VSYSCALL=y
 # CONFIG_GIANFAR is not set
 CONFIG_GLOB=y
 CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MAX77620=y
 CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PL061=y
 CONFIG_GPIO_SYSFS=y
-# CONFIG_GRO_CELLS is not set
+CONFIG_GPIO_XGENE=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HARDEN_BRANCH_PREDICTOR=y
 CONFIG_HARDIRQS_SW_RESEND=y
@@ -438,7 +550,6 @@ CONFIG_HAVE_ARCH_PFN_VALID=y
 CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
 CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
-CONFIG_HAVE_ARCH_VMAP_STACK=y
 CONFIG_HAVE_ARM_SMCCC=y
 # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
 CONFIG_HAVE_CC_STACKPROTECTOR=y
@@ -459,9 +570,16 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_GUP=y
+CONFIG_HAVE_GENERIC_RCU_GUP=y
 CONFIG_HAVE_HW_BREAKPOINT=y
 CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_KVM_MSI=y
 CONFIG_HAVE_MEMBLOCK=y
 CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
 CONFIG_HAVE_MEMORY_PRESENT=y
@@ -491,26 +609,33 @@ CONFIG_HID_KENSINGTON=y
 CONFIG_HID_LOGITECH=y
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MONTEREY=y
-CONFIG_HOLES_IN_ZONE=y
+CONFIG_HNS=y
+CONFIG_HNS_DSAF=y
+CONFIG_HNS_ENET=y
+CONFIG_HNS_MDIO=y
 CONFIG_HOTPLUG_CPU=y
+# CONFIG_HPET is not set
 CONFIG_HUGETLBFS=y
 CONFIG_HUGETLB_PAGE=y
 CONFIG_HVC_DRIVER=y
 CONFIG_HVC_IRQ=y
 CONFIG_HVC_XEN=y
 CONFIG_HVC_XEN_FRONTEND=y
+CONFIG_HWMON=y
 CONFIG_HW_CONSOLE=y
 CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_CAVIUM is not set
 CONFIG_HZ=250
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
 CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_DESIGNWARE_CORE=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
-# CONFIG_I2C_DESIGNWARE_SLAVE is not set
 CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_IMX=y
 CONFIG_I2C_MUX=y
@@ -518,24 +643,39 @@ CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_RK3X=y
 CONFIG_I2C_SLAVE=y
 # CONFIG_I2C_SLAVE_EEPROM is not set
+CONFIG_IGB=y
+CONFIG_IGBVF=y
+CONFIG_IGB_HWMON=y
+CONFIG_IIO=y
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_IMA is not set
 CONFIG_IMX2_WDT=y
 CONFIG_INET_DIAG=y
 # CONFIG_INET_DIAG_DESTROY is not set
-# CONFIG_INET_RAW_DIAG is not set
+CONFIG_INET_ESP=y
 CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_INPUT=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
 CONFIG_INPUT_MOUSE=y
 CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+CONFIG_INTEGRITY=y
+CONFIG_INTEGRITY_AUDIT=y
+# CONFIG_INTEGRITY_SIGNATURE is not set
 CONFIG_IOMMU_API=y
 CONFIG_IOMMU_DMA=y
 CONFIG_IOMMU_HELPER=y
@@ -548,7 +688,13 @@ CONFIG_IOMMU_SUPPORT=y
 CONFIG_IOSCHED_CFQ=y
 # CONFIG_IOSCHED_DEADLINE is not set
 CONFIG_IPC_NS=y
+CONFIG_IPV6=y
+CONFIG_IPV6_SIT=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_RARP is not set
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_BYPASS_MANAGER=y
 CONFIG_IRQ_DOMAIN=y
@@ -563,14 +709,32 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_KEXEC=y
 CONFIG_KEXEC_CORE=y
 CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_CROS_EC is not set
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYS=y
+CONFIG_KEYS_COMPAT=y
 CONFIG_KSM=y
+CONFIG_KVM=y
+CONFIG_KVM_ARM_HOST=y
+CONFIG_KVM_ARM_PMU=y
+CONFIG_KVM_ARM_VGIC_V3_ITS=y
+CONFIG_KVM_COMPAT=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
 # CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=16
 CONFIG_LIBCRC32C=y
 CONFIG_LIBFDT=y
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCKUP_DETECTOR=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
 CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_CLUT224=y
@@ -580,31 +744,54 @@ CONFIG_LS_SCFG_MSI=y
 CONFIG_LS_SOC_DRIVERS=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACVLAN=y
+CONFIG_MACVTAP=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_MAX77620_THERMAL is not set
+# CONFIG_MAX77620_WATCHDOG is not set
 CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BOARDINFO=y
 CONFIG_MDIO_BUS_MUX=y
 CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_DEVICE=y
 # CONFIG_MDIO_FSL_BACKPLANE is not set
 # CONFIG_MDIO_GPIO is not set
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_SWAP_ENABLED=y
 CONFIG_MEMORY=y
 CONFIG_MEMORY_BALLOON=y
 CONFIG_MEMORY_ISOLATION=y
 CONFIG_MEMTEST=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_I2C=y
+# CONFIG_MFD_CROS_EC_SPI is not set
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
 CONFIG_MFD_SYSCON=y
-# CONFIG_MFD_VEXPRESS_SYSREG is not set
+CONFIG_MFD_VEXPRESS_SYSREG=y
 CONFIG_MICREL_PHY=y
 CONFIG_MIGRATION=y
 CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_K3=y
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
 CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
 CONFIG_MMC_SDHCI_OF_ESDHC=y
 # CONFIG_MMC_SDHCI_PCI is not set
 CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SPI=y
 # CONFIG_MMC_TIFM_SD is not set
 CONFIG_MMU_NOTIFIER=y
 CONFIG_MODULES_TREE_LOOKUP=y
@@ -620,13 +807,12 @@ CONFIG_MOUSE_PS2_CYPRESS=y
 # CONFIG_MOUSE_PS2_ELANTECH is not set
 CONFIG_MOUSE_PS2_FOCALTECH=y
 CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
 CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MPILIB=y
 CONFIG_MRP=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 # CONFIG_MTD_CFI_GEOMETRY is not set
@@ -638,6 +824,8 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_DENALI=y
+CONFIG_MTD_NAND_DENALI_DT=y
 CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND_FSL_IFC=y
 CONFIG_MTD_SPI_NOR=y
@@ -657,8 +845,10 @@ CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEED_MULTIPLE_NODES=y
 CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
 CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NET_CADENCE is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NET_CLS_CGROUP is not set
 CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_IP_TUNNEL=y
 CONFIG_NET_NS=y
 CONFIG_NET_PTP_CLASSIFY=y
 CONFIG_NET_SWITCHDEV=y
@@ -674,6 +864,7 @@ CONFIG_NUMA=y
 CONFIG_NUMA_BALANCING=y
 CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
 CONFIG_NVMEM=y
+CONFIG_NVME_CORE=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_ADDRESS_PCI=y
@@ -690,13 +881,16 @@ CONFIG_OF_PCI_IRQ=y
 CONFIG_OF_RESERVED_MEM=y
 CONFIG_OLD_SIGSUSPEND3=y
 CONFIG_PACKET_DIAG=y
-CONFIG_PADATA=y
+CONFIG_PAGE_COUNTER=y
 # CONFIG_PANIC_ON_OOPS is not set
 CONFIG_PANIC_ON_OOPS_VALUE=0
 CONFIG_PANIC_TIMEOUT=0
 CONFIG_PARAVIRT=y
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_PARTITION_PERCPU=y
+# CONFIG_PATA_ACPI is not set
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_PATA_PLATFORM=y
 CONFIG_PCI=y
 CONFIG_PCIEAER=y
 CONFIG_PCIEASPM=y
@@ -704,10 +898,8 @@ CONFIG_PCIEASPM=y
 CONFIG_PCIEASPM_DEFAULT=y
 # CONFIG_PCIEASPM_PERFORMANCE is not set
 # CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
 CONFIG_PCIE_PME=y
 CONFIG_PCI_ATS=y
 CONFIG_PCI_BUS_ADDR_T_64BIT=y
@@ -731,12 +923,16 @@ CONFIG_PID_IN_CONTEXTIDR=y
 CONFIG_PID_NS=y
 CONFIG_PL330_DMA=y
 CONFIG_PM=y
+# CONFIG_PMIC_OPREGION is not set
 CONFIG_PM_CLK=y
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_OPP=y
 CONFIG_PM_SLEEP=y
 CONFIG_PM_SLEEP_SMP=y
 CONFIG_PM_STD_PARTITION=""
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_POSIX_MQUEUE_SYSCTL=y
 CONFIG_POWER_RESET=y
@@ -748,14 +944,19 @@ CONFIG_PPS=y
 CONFIG_PREEMPT=y
 CONFIG_PREEMPT_COUNT=y
 # CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_NOTIFIERS=y
 CONFIG_PREEMPT_RCU=y
 CONFIG_PRINTK_TIME=y
 CONFIG_PRINT_QUOTA_WARNING=y
 CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_PID_CPUSET=y
 CONFIG_PROFILING=y
 CONFIG_PTP_1588_CLOCK=y
 # CONFIG_PTP_1588_CLOCK_DPAA is not set
 CONFIG_PTP_1588_CLOCK_DPAA2=y
+CONFIG_PWM=y
+# CONFIG_PWM_CROS_EC is not set
+CONFIG_PWM_SYSFS=y
 CONFIG_QCOM_HIDMA=y
 CONFIG_QCOM_HIDMA_MGMT=y
 CONFIG_QCOM_QDF2400_ERRATUM_0065=y
@@ -763,6 +964,7 @@ CONFIG_QCOM_QDF2400_ERRATUM_0065=y
 # CONFIG_QFMT_V2 is not set
 CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
 CONFIG_QORIQ_CPUFREQ=y
+CONFIG_QORIQ_THERMAL=y
 # CONFIG_QUICC_ENGINE is not set
 CONFIG_QUOTA=y
 CONFIG_QUOTACTL=y
@@ -774,7 +976,6 @@ CONFIG_RAS=y
 CONFIG_RATIONAL=y
 CONFIG_RCU_CPU_STALL_TIMEOUT=21
 # CONFIG_RCU_EXPERT is not set
-CONFIG_RCU_NEED_SEGCBLIST=y
 CONFIG_RCU_STALL_COMMON=y
 CONFIG_RD_BZIP2=y
 CONFIG_RD_GZIP=y
@@ -784,38 +985,70 @@ CONFIG_RD_XZ=y
 CONFIG_REALTEK_PHY=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_REGMAP_SPI=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_S2MPA01 is not set
+CONFIG_REGULATOR_S2MPS11=y
+# CONFIG_REGULATOR_S5M8767 is not set
+# CONFIG_REGULATOR_VEXPRESS is not set
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RFS_ACCEL=y
 CONFIG_RPS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1307_HWMON=y
 CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_MAX77686=y
 CONFIG_RTC_DRV_PCF2127=y
 CONFIG_RTC_DRV_PCF85263=y
 CONFIG_RTC_DRV_PL031=y
+# CONFIG_RTC_DRV_RK808 is not set
+CONFIG_RTC_DRV_S5M=y
 CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
 CONFIG_RWSEM_SPIN_ON_OWNER=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_PMP=y
+CONFIG_SATA_SIL24=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SCHED_AUTOGROUP=y
 CONFIG_SCHED_INFO=y
 CONFIG_SCHED_MC=y
 CONFIG_SCSI=y
+CONFIG_SCSI_HISI_SAS=y
 # CONFIG_SCSI_PROC_FS is not set
-# CONFIG_SCSI_SAS_ATA is not set
+CONFIG_SCSI_SAS_ATA=y
 CONFIG_SCSI_SAS_ATTRS=y
 CONFIG_SCSI_SAS_HOST_SMP=y
 CONFIG_SCSI_SAS_LIBSAS=y
 CONFIG_SECCOMP=y
 CONFIG_SECCOMP_FILTER=y
+CONFIG_SECURITY=y
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_SECURITY_LOADPIN is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_SMACK is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_YAMA is not set
 CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PNP=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 CONFIG_SERIAL_8250_SHARE_IRQ=y
 CONFIG_SERIAL_AMBA_PL011=y
@@ -829,11 +1062,34 @@ CONFIG_SERIO=y
 CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SG_POOL=y
+CONFIG_SKY2=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
+CONFIG_SMC91X=y
 CONFIG_SMP=y
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+CONFIG_SND=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AK4613=y
+CONFIG_SND_SOC_FSL_SAI=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_TIMER=y
 CONFIG_SOCK_DIAG=y
 CONFIG_SOC_BUS=y
+CONFIG_SOUND=y
 CONFIG_SPARSEMEM=y
 CONFIG_SPARSEMEM_EXTREME=y
 CONFIG_SPARSEMEM_MANUAL=y
@@ -860,6 +1116,7 @@ CONFIG_SUSPEND_FREEZER=y
 CONFIG_SWIOTLB=y
 CONFIG_SWIOTLB_XEN=y
 CONFIG_SWPHY=y
+# CONFIG_SW_SYNC is not set
 CONFIG_SYNC_FILE=y
 # CONFIG_SYN_COOKIES is not set
 CONFIG_SYSCTL_EXCEPTION_TRACE=y
@@ -868,28 +1125,24 @@ CONFIG_SYSVIPC_COMPAT=y
 CONFIG_SYS_HYPERVISOR=y
 CONFIG_SYS_SUPPORTS_HUGETLBFS=y
 CONFIG_TASKSTATS=y
-CONFIG_TASKS_RCU=y
 CONFIG_TASK_DELAY_ACCT=y
 CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_TASK_XACCT=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_THERMAL=y
 CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
 CONFIG_THERMAL_EMULATION=y
 CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
 CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
 CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
 CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
 # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
 CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
-CONFIG_TREE_SRCU=y
+CONFIG_TUN=y
 CONFIG_UBIFS_FS=y
 # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
 CONFIG_UBIFS_FS_LZO=y
@@ -919,7 +1172,6 @@ CONFIG_VFAT_FS=y
 CONFIG_VFIO=y
 CONFIG_VFIO_FSL_MC=y
 CONFIG_VFIO_IOMMU_TYPE1=y
-# CONFIG_VFIO_MDEV is not set
 # CONFIG_VFIO_NOIOMMU is not set
 CONFIG_VFIO_PCI=y
 CONFIG_VFIO_PCI_INTX=y
@@ -928,6 +1180,8 @@ CONFIG_VFIO_PCI_MMAP=y
 CONFIG_VFIO_VIRQFD=y
 CONFIG_VGA_ARB=y
 CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VHOST=y
+CONFIG_VHOST_NET=y
 CONFIG_VIDEOMODE_HELPERS=y
 CONFIG_VIRTIO=y
 CONFIG_VIRTIO_BALLOON=y
@@ -938,10 +1192,10 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_NET=y
 CONFIG_VIRTIO_PCI=y
 CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTUALIZATION=y
 CONFIG_VITESSE_PHY=y
 CONFIG_VLAN_8021Q_GVRP=y
 CONFIG_VLAN_8021Q_MVRP=y
-CONFIG_VMAP_STACK=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
@@ -966,18 +1220,18 @@ CONFIG_XEN_GRANT_DEV_ALLOC=y
 # CONFIG_XEN_NETDEV_BACKEND is not set
 CONFIG_XEN_NETDEV_FRONTEND=y
 CONFIG_XEN_PRIVCMD=y
-# CONFIG_XEN_PVCALLS_BACKEND is not set
 CONFIG_XEN_SCRUB_PAGES=y
 # CONFIG_XEN_SCSI_FRONTEND is not set
 CONFIG_XEN_SYS_HYPERVISOR=y
 # CONFIG_XEN_WDT is not set
 CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
 CONFIG_XFS_FS=y
 CONFIG_XFS_POSIX_ACL=y
 CONFIG_XFS_RT=y
 CONFIG_XOR_BLOCKS=y
 CONFIG_XPS=y
-CONFIG_XXHASH=y
 CONFIG_XZ_DEC_ARM=y
 CONFIG_XZ_DEC_ARMTHUMB=y
 CONFIG_XZ_DEC_BCJ=y
@@ -987,5 +1241,3 @@ CONFIG_XZ_DEC_SPARC=y
 CONFIG_XZ_DEC_X86=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/layerscape/image/armv7.mk b/target/linux/layerscape/image/armv7.mk
index 04937a908..7a582d79b 100644
--- a/target/linux/layerscape/image/armv7.mk
+++ b/target/linux/layerscape/image/armv7.mk
@@ -45,19 +45,3 @@ define Device/ls1021atwr-sdboot
     append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
 endef
 TARGET_DEVICES += ls1021atwr-sdboot
-
-define Device/ls1021aiot-sdboot
-  DEVICE_TITLE := LS1021AIOT (SD Card Boot)
-  DEVICE_DTS := ls1021a-iot
-  FILESYSTEMS := ext4
-  IMAGES := sdcard.img
-  IMAGE/sdcard.img := \
-    ls-clean | \
-    ls-append-sdhead $(1) | pad-to 4K | \
-    ls-append $(1)-uboot.bin | pad-to 1M | \
-    ls-append $(1)-uboot-env.bin | pad-to 15M | \
-    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \
-    append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \
-    append-rootfs | check-size $(LS_SD_IMAGE_SIZE)
-endef
-TARGET_DEVICES += ls1021aiot-sdboot
diff --git a/target/linux/layerscape/image/armv8_32b.mk b/target/linux/layerscape/image/armv8_32b.mk
index 8410c3b4d..95418926f 100644
--- a/target/linux/layerscape/image/armv8_32b.mk
+++ b/target/linux/layerscape/image/armv8_32b.mk
@@ -9,7 +9,6 @@ define Device/Default
   PROFILES := Default
   IMAGES := firmware.bin
   FILESYSTEMS := ubifs
-  MKUBIFS_OPTS := -m 1 -e 262016 -c 128
   KERNEL := kernel-bin | uImage none
   KERNEL_NAME := zImage
   KERNEL_LOADADDR := 0x80008000
@@ -25,6 +24,7 @@ define Device/ls1012ardb
     u-boot-ls1012ardb-image \
     kmod-ppfe
   DEVICE_DTS := ../../../arm64/boot/dts/freescale/fsl-ls1012a-rdb
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 256KiB
   PAGESIZE := 1
@@ -99,6 +99,7 @@ define Device/ls1046ardb
     layerscape-ppa-ls1046ardb \
     u-boot-ls1046ardb-image
   DEVICE_DTS := ../../../arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 256KiB
   PAGESIZE := 1
diff --git a/target/linux/layerscape/image/armv8_64b.mk b/target/linux/layerscape/image/armv8_64b.mk
index 6d783a58d..79e05efc1 100644
--- a/target/linux/layerscape/image/armv8_64b.mk
+++ b/target/linux/layerscape/image/armv8_64b.mk
@@ -9,7 +9,6 @@ define Device/Default
   PROFILES := Default
   IMAGES := firmware.bin
   FILESYSTEMS := ubifs
-  MKUBIFS_OPTS := -m 1 -e 262016 -c 128
   KERNEL := kernel-bin | gzip | uImage gzip
   KERNEL_LOADADDR := 0x80080000
   KERNEL_ENTRY_POINT := 0x80080000
@@ -23,6 +22,7 @@ define Device/ls1012ardb
     layerscape-ppa-ls1012ardb \
     kmod-ppfe
   DEVICE_DTS := freescale/fsl-ls1012a-rdb
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 256KiB
   PAGESIZE := 1
@@ -115,6 +115,7 @@ define Device/ls1046ardb
     layerscape-fman-ls1046ardb \
     layerscape-ppa-ls1046ardb
   DEVICE_DTS := freescale/fsl-ls1046a-rdb-sdk
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 256KiB
   PAGESIZE := 1
@@ -161,6 +162,7 @@ define Device/ls1088ardb
     layerscape-ppa-ls1088ardb \
     restool
   DEVICE_DTS := freescale/fsl-ls1088a-rdb
+  UBIFS_OPTS := -m 1 -e 262016 -c 128
   UBINIZE_OPTS := -E 5
   BLOCKSIZE := 256KiB
   PAGESIZE := 1
@@ -256,6 +258,6 @@ define Device/traverse-five64
   IMAGES = root sysupgrade.tar
   IMAGE/root = append-rootfs
   IMAGE/sysupgrade.tar = sysupgrade-tar
-  MKUBIFS_OPTS := -m 2048 -e 124KiB -c 4096
+  UBIFS_OPTS := -m 2048 -e 124KiB -c 4096
 endef
 TARGET_DEVICES += traverse-five64
diff --git a/target/linux/layerscape/modules.mk b/target/linux/layerscape/modules.mk
index 5f2d472c9..7a368a0d2 100644
--- a/target/linux/layerscape/modules.mk
+++ b/target/linux/layerscape/modules.mk
@@ -9,8 +9,7 @@ define KernelPackage/ppfe
   SUBMENU:=$(NETWORK_DEVICES_MENU)
   TITLE:=Freescale PPFE Driver support
   DEPENDS:=@TARGET_layerscape
-  KCONFIG:=CONFIG_FSL_PPFE=y \
-  	CONFIG_FSL_PPFE_UTIL_DISABLED=y
+  KCONFIG:=CONFIG_FSL_PPFE CONFIG_FSL_PPFE_UTIL_DISABLED
   FILES:=$(LINUX_DIR)/drivers/staging/fsl_ppfe/pfe.ko
   AUTOLOAD:=$(call AutoLoad,35,pfe)
 endef
diff --git a/target/linux/layerscape/patches-4.14/201-config-support-layerscape.patch b/target/linux/layerscape/patches-4.14/201-config-support-layerscape.patch
deleted file mode 100644
index 7ab88b5e9..000000000
--- a/target/linux/layerscape/patches-4.14/201-config-support-layerscape.patch
+++ /dev/null
@@ -1,301 +0,0 @@
-From 0bafdb711c1a61fbe5bb5b4d4bb5e32425d95a72 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 16 Nov 2018 15:36:03 +0800
-Subject: [PATCH] config: support layerscape
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is an integrated patch of config for layerscape
-
-Signed-off-by: Alison Wang <alison.wang@nxp.com>
-Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
-Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
-Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
-Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
-Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-Signed-off-by: Li Yang <leoyang.li@nxp.com>
-Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
-Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
-Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
-Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Signed-off-by: Zhao Qiang  <qiang.zhao@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/irqchip/Makefile                |  1 +
- drivers/net/ethernet/freescale/Kconfig  | 14 ++++----
- drivers/net/ethernet/freescale/Makefile |  3 ++
- drivers/ptp/Kconfig                     | 29 +++++++++++++++++
- drivers/soc/Kconfig                     |  1 +
- drivers/soc/fsl/Kconfig                 | 11 +++++++
- drivers/soc/fsl/Kconfig.arm             | 16 +++++++++
- drivers/soc/fsl/Makefile                |  3 ++
- drivers/soc/fsl/layerscape/Kconfig      | 10 ++++++
- drivers/soc/fsl/layerscape/Makefile     |  1 +
- drivers/staging/Kconfig                 |  4 +++
- drivers/staging/Makefile                |  2 ++
- drivers/staging/fsl-dpaa2/Kconfig       | 43 ++++++++++++++++++++++++-
- drivers/staging/fsl-dpaa2/Makefile      |  4 +++
- 14 files changed, 135 insertions(+), 7 deletions(-)
- create mode 100644 drivers/soc/fsl/Kconfig.arm
- create mode 100644 drivers/soc/fsl/layerscape/Kconfig
- create mode 100644 drivers/soc/fsl/layerscape/Makefile
-
---- a/drivers/irqchip/Makefile
-+++ b/drivers/irqchip/Makefile
-@@ -80,3 +80,4 @@ obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed
- obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
- obj-$(CONFIG_QCOM_IRQ_COMBINER)		+= qcom-irq-combiner.o
- obj-$(CONFIG_IRQ_UNIPHIER_AIDET)	+= irq-uniphier-aidet.o
-+obj-$(CONFIG_QUICC_ENGINE)		+= irq-qeic.o
---- a/drivers/net/ethernet/freescale/Kconfig
-+++ b/drivers/net/ethernet/freescale/Kconfig
-@@ -5,10 +5,11 @@
- config NET_VENDOR_FREESCALE
- 	bool "Freescale devices"
- 	default y
--	depends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \
--		   M523x || M527x || M5272 || M528x || M520x || M532x || \
--		   ARCH_MXC || ARCH_MXS || (PPC_MPC52xx && PPC_BESTCOMM) || \
--		   ARCH_LAYERSCAPE || COMPILE_TEST
-+	depends on FSL_SOC || (QUICC_ENGINE && PPC32) || CPM1 || CPM2 || \
-+		   PPC_MPC512x || M523x || M527x || M5272 || M528x || M520x || \
-+		   M532x || ARCH_MXC || ARCH_MXS || \
-+		   (PPC_MPC52xx && PPC_BESTCOMM) || ARCH_LAYERSCAPE || \
-+		   COMPILE_TEST
- 	---help---
- 	  If you have a network (Ethernet) card belonging to this class, say Y.
- 
-@@ -73,7 +74,7 @@ config FSL_XGMAC_MDIO
- 
- config UCC_GETH
- 	tristate "Freescale QE Gigabit Ethernet"
--	depends on QUICC_ENGINE
-+	depends on QUICC_ENGINE && FSL_SOC && PPC32
- 	select FSL_PQ_MDIO
- 	select PHYLIB
- 	---help---
-@@ -94,7 +95,8 @@ config GIANFAR
- 	  This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx,
- 	  and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
- 	  on the 8540.
--
-+source "drivers/net/ethernet/freescale/sdk_fman/Kconfig"
-+source "drivers/net/ethernet/freescale/sdk_dpaa/Kconfig"
- source "drivers/net/ethernet/freescale/dpaa/Kconfig"
- 
- endif # NET_VENDOR_FREESCALE
---- a/drivers/net/ethernet/freescale/Makefile
-+++ b/drivers/net/ethernet/freescale/Makefile
-@@ -20,5 +20,8 @@ gianfar_driver-objs := gianfar.o \
- obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
- ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
- 
-+obj-$(if $(CONFIG_FSL_SDK_FMAN),y) += sdk_fman/
-+obj-$(if $(CONFIG_FSL_SDK_DPAA_ETH),y) += sdk_dpaa/
-+
- obj-$(CONFIG_FSL_FMAN) += fman/
- obj-$(CONFIG_FSL_DPAA_ETH) += dpaa/
---- a/drivers/ptp/Kconfig
-+++ b/drivers/ptp/Kconfig
-@@ -55,6 +55,35 @@ config PTP_1588_CLOCK_GIANFAR
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called gianfar_ptp.
- 
-+config PTP_1588_CLOCK_DPAA
-+	tristate "Freescale DPAA as PTP clock"
-+	depends on FSL_SDK_DPAA_ETH
-+	select PTP_1588_CLOCK
-+        select FSL_DPAA_TS
-+        default n
-+	help
-+	  This driver adds support for using the DPAA 1588 timer module
-+	  as a PTP clock. This clock is only useful if your PTP programs are
-+	  getting hardware time stamps on the PTP Ethernet packets
-+	  using the SO_TIMESTAMPING API.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called dpaa_ptp.
-+
-+config PTP_1588_CLOCK_DPAA2
-+	tristate "Freescale DPAA2 as PTP clock"
-+	depends on FSL_DPAA2_ETH
-+	select PTP_1588_CLOCK
-+	default y
-+	help
-+	  This driver adds support for using the DPAA2 1588 timer module
-+	  as a PTP clock. This clock is only useful if your PTP programs are
-+	  getting hardware time stamps on the PTP Ethernet packets
-+	  using the SO_TIMESTAMPING API.
-+
-+	  To compile this driver as a module, choose M here: the module
-+	  will be called dpaa2-rtc.
-+
- config PTP_1588_CLOCK_IXP46X
- 	tristate "Intel IXP46x as PTP clock"
- 	depends on IXP4XX_ETH
---- a/drivers/soc/Kconfig
-+++ b/drivers/soc/Kconfig
-@@ -5,6 +5,7 @@ source "drivers/soc/amlogic/Kconfig"
- source "drivers/soc/atmel/Kconfig"
- source "drivers/soc/bcm/Kconfig"
- source "drivers/soc/fsl/Kconfig"
-+source "drivers/soc/fsl/ls2-console/Kconfig"
- source "drivers/soc/imx/Kconfig"
- source "drivers/soc/mediatek/Kconfig"
- source "drivers/soc/qcom/Kconfig"
---- a/drivers/soc/fsl/Kconfig
-+++ b/drivers/soc/fsl/Kconfig
-@@ -16,3 +16,14 @@ config FSL_GUTS
- 	  Initially only reading SVR and registering soc device are supported.
- 	  Other guts accesses, such as reading RCW, should eventually be moved
- 	  into this driver as well.
-+
-+config FSL_SLEEP_FSM
-+	bool
-+	help
-+	  This driver configures a hardware FSM (Finite State Machine) for deep sleep.
-+	  The FSM is used to finish clean-ups at the last stage of system entering deep
-+	  sleep, and also wakes up system when a wake up event happens.
-+
-+if ARM || ARM64
-+source "drivers/soc/fsl/Kconfig.arm"
-+endif
---- /dev/null
-+++ b/drivers/soc/fsl/Kconfig.arm
-@@ -0,0 +1,16 @@
-+#
-+# Freescale ARM SOC Drivers
-+#
-+
-+config LS_SOC_DRIVERS
-+	bool "Layerscape Soc Drivers"
-+	depends on ARCH_LAYERSCAPE || SOC_LS1021A
-+	default n
-+	help
-+	Say y here to enable Freescale Layerscape Soc Device Drivers support.
-+	The Soc Drivers provides the device driver that is a specific block
-+	or feature on Layerscape platform.
-+
-+if LS_SOC_DRIVERS
-+	source "drivers/soc/fsl/layerscape/Kconfig"
-+endif
---- a/drivers/soc/fsl/Makefile
-+++ b/drivers/soc/fsl/Makefile
-@@ -6,3 +6,6 @@ obj-$(CONFIG_FSL_DPAA)                 +
- obj-$(CONFIG_QUICC_ENGINE)		+= qe/
- obj-$(CONFIG_CPM)			+= qe/
- obj-$(CONFIG_FSL_GUTS)			+= guts.o
-+obj-$(CONFIG_FSL_LS2_CONSOLE)		+= ls2-console/
-+obj-$(CONFIG_LS_SOC_DRIVERS)		+= layerscape/
-+obj-$(CONFIG_FSL_SLEEP_FSM)	+= sleep_fsm.o
---- /dev/null
-+++ b/drivers/soc/fsl/layerscape/Kconfig
-@@ -0,0 +1,10 @@
-+#
-+# Layerscape Soc drivers
-+#
-+config  FTM_ALARM
-+	bool "FTM alarm driver"
-+	default n
-+	help
-+	Say y here to enable FTM alarm support.  The FTM alarm provides
-+	alarm functions for wakeup system from deep sleep.  There is only
-+	one FTM can be used in ALARM(FTM 0).
---- /dev/null
-+++ b/drivers/soc/fsl/layerscape/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_FTM_ALARM) += ftm_alarm.o
---- a/drivers/staging/Kconfig
-+++ b/drivers/staging/Kconfig
-@@ -118,4 +118,8 @@ source "drivers/staging/vboxvideo/Kconfi
- 
- source "drivers/staging/pi433/Kconfig"
- 
-+source "drivers/staging/fsl_qbman/Kconfig"
-+
-+source "drivers/staging/fsl_ppfe/Kconfig"
-+
- endif # STAGING
---- a/drivers/staging/Makefile
-+++ b/drivers/staging/Makefile
-@@ -50,3 +50,5 @@ obj-$(CONFIG_BCM2835_VCHIQ)	+= vc04_serv
- obj-$(CONFIG_CRYPTO_DEV_CCREE)	+= ccree/
- obj-$(CONFIG_DRM_VBOXVIDEO)	+= vboxvideo/
- obj-$(CONFIG_PI433)		+= pi433/
-+obj-$(CONFIG_FSL_SDK_DPA)      += fsl_qbman/
-+obj-$(CONFIG_FSL_PPFE)		+= fsl_ppfe/
---- a/drivers/staging/fsl-dpaa2/Kconfig
-+++ b/drivers/staging/fsl-dpaa2/Kconfig
-@@ -4,7 +4,7 @@
- 
- config FSL_DPAA2
- 	bool "Freescale DPAA2 devices"
--	depends on FSL_MC_BUS && ARCH_LAYERSCAPE
-+	depends on FSL_MC_BUS
- 	---help---
- 	  Build drivers for Freescale DataPath Acceleration
- 	  Architecture (DPAA2) family of SoCs.
-@@ -16,3 +16,44 @@ config FSL_DPAA2_ETH
- 	---help---
- 	  Ethernet driver for Freescale DPAA2 SoCs, using the
- 	  Freescale MC bus driver
-+
-+if FSL_DPAA2_ETH
-+config FSL_DPAA2_ETH_USE_ERR_QUEUE
-+	bool "Enable Rx error queue"
-+	default n
-+	---help---
-+	  Allow Rx error frames to be enqueued on an error queue
-+	  and processed by the driver (by default they are dropped
-+	  in hardware).
-+	  This may impact performance, recommended for debugging
-+	  purposes only.
-+
-+# QBMAN_DEBUG requires some additional DPIO APIs
-+config FSL_DPAA2_ETH_DEBUGFS
-+	depends on DEBUG_FS
-+	bool "Enable debugfs support"
-+	default y
-+	---help---
-+	  Enable advanced statistics through debugfs interface.
-+
-+config FSL_DPAA2_ETH_DCB
-+        bool "Data Center Bridging (DCB) Support"
-+        default n
-+        depends on DCB
-+        ---help---
-+          Say Y here if you want to use Data Center Bridging (DCB) features
-+          (PFC) in the driver.
-+
-+          If unsure, say N.
-+endif
-+
-+source "drivers/staging/fsl-dpaa2/mac/Kconfig"
-+source "drivers/staging/fsl-dpaa2/evb/Kconfig"
-+
-+config FSL_DPAA2_ETHSW
-+	tristate "Freescale DPAA2 Ethernet Switch"
-+	depends on FSL_DPAA2
-+	depends on NET_SWITCHDEV
-+	---help---
-+	Driver for Freescale DPAA2 Ethernet Switch. Select
-+	BRIDGE to have support for bridge tools.
---- a/drivers/staging/fsl-dpaa2/Makefile
-+++ b/drivers/staging/fsl-dpaa2/Makefile
-@@ -3,3 +3,7 @@
- #
- 
- obj-$(CONFIG_FSL_DPAA2_ETH)	+= ethernet/
-+obj-$(CONFIG_FSL_DPAA2_MAC)	+= mac/
-+obj-$(CONFIG_FSL_DPAA2_EVB)	+= evb/
-+obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += rtc/
-+obj-$(CONFIG_FSL_DPAA2_ETHSW)	+= ethsw/
diff --git a/target/linux/layerscape/patches-4.14/202-core-linux-support-layerscape.patch b/target/linux/layerscape/patches-4.14/202-core-linux-support-layerscape.patch
deleted file mode 100644
index 14e8d7315..000000000
--- a/target/linux/layerscape/patches-4.14/202-core-linux-support-layerscape.patch
+++ /dev/null
@@ -1,741 +0,0 @@
-From 74243154052af635ee9ce9d07aab273ce219c855 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Thu, 13 Dec 2018 13:23:52 +0800
-Subject: [PATCH] core-linux: support layerscape
-
-This is an integrated patch of core-linux for layerscape.
-
-Signed-off-by: Abhijit Ayarekar <abhijit.ayarekar@caviumnetworks.com>
-Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
-Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
-Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
-Signed-off-by: Christoph Hellwig <hch@lst.de>
-Signed-off-by: David Ahern <dsahern@gmail.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
-Signed-off-by: Jiri Pirko <jiri@mellanox.com>
-Signed-off-by: Joel Fernandes <joelaf@google.com>
-Signed-off-by: Li Yang <leoyang.li@nxp.com>
-Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
-Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
-Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
-Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
-Signed-off-by: Robin Murphy <robin.murphy@arm.com>
-Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/base/dma-mapping.c                |  7 ++
- drivers/net/bonding/bond_main.c           |  5 +-
- drivers/net/bonding/bond_options.c        |  2 +-
- drivers/net/team/team.c                   |  3 +-
- drivers/net/vrf.c                         |  3 +-
- drivers/of/device.c                       | 13 +++-
- drivers/soc/fsl/guts.c                    |  3 +
- include/linux/fsl_devices.h               |  2 +
- include/linux/netdevice.h                 | 13 +++-
- include/linux/skbuff.h                    |  2 +
- include/net/bonding.h                     |  3 +-
- net/batman-adv/soft-interface.c           |  3 +-
- net/bridge/br_device.c                    |  3 +-
- net/core/dev.c                            | 81 ++++++++++++++---------
- net/core/rtnetlink.c                      | 10 +--
- net/core/skbuff.c                         | 29 +++++++-
- samples/bpf/Makefile                      | 12 +++-
- samples/bpf/map_perf_test_kern.c          |  2 +-
- samples/bpf/map_perf_test_user.c          |  2 +-
- tools/testing/selftests/bpf/bpf_helpers.h | 56 ++++++++++++++--
- 20 files changed, 193 insertions(+), 61 deletions(-)
-
---- a/drivers/base/dma-mapping.c
-+++ b/drivers/base/dma-mapping.c
-@@ -335,6 +335,7 @@ void dma_common_free_remap(void *cpu_add
-  * Common configuration to enable DMA API use for a device
-  */
- #include <linux/pci.h>
-+#include <linux/fsl/mc.h>
- 
- int dma_configure(struct device *dev)
- {
-@@ -350,6 +351,12 @@ int dma_configure(struct device *dev)
- 			dma_dev = dma_dev->parent;
- 	}
- 
-+	if (dev_is_fsl_mc(dev)) {
-+		dma_dev = dev;
-+		while (dev_is_fsl_mc(dma_dev))
-+			dma_dev = dma_dev->parent;
-+	}
-+
- 	if (dma_dev->of_node) {
- 		ret = of_dma_configure(dev, dma_dev->of_node);
- 	} else if (has_acpi_companion(dma_dev)) {
---- a/drivers/net/bonding/bond_main.c
-+++ b/drivers/net/bonding/bond_main.c
-@@ -1337,7 +1337,8 @@ void bond_lower_state_changed(struct sla
- }
- 
- /* enslave device <slave> to bond device <master> */
--int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
-+int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev,
-+		 struct netlink_ext_ack *extack)
- {
- 	struct bonding *bond = netdev_priv(bond_dev);
- 	const struct net_device_ops *slave_ops = slave_dev->netdev_ops;
-@@ -3506,7 +3507,7 @@ static int bond_do_ioctl(struct net_devi
- 	switch (cmd) {
- 	case BOND_ENSLAVE_OLD:
- 	case SIOCBONDENSLAVE:
--		res = bond_enslave(bond_dev, slave_dev);
-+		res = bond_enslave(bond_dev, slave_dev, NULL);
- 		break;
- 	case BOND_RELEASE_OLD:
- 	case SIOCBONDRELEASE:
---- a/drivers/net/bonding/bond_options.c
-+++ b/drivers/net/bonding/bond_options.c
-@@ -1389,7 +1389,7 @@ static int bond_option_slaves_set(struct
- 	switch (command[0]) {
- 	case '+':
- 		netdev_dbg(bond->dev, "Adding slave %s\n", dev->name);
--		ret = bond_enslave(bond->dev, dev);
-+		ret = bond_enslave(bond->dev, dev, NULL);
- 		break;
- 
- 	case '-':
---- a/drivers/net/team/team.c
-+++ b/drivers/net/team/team.c
-@@ -1932,7 +1932,8 @@ static int team_netpoll_setup(struct net
- }
- #endif
- 
--static int team_add_slave(struct net_device *dev, struct net_device *port_dev)
-+static int team_add_slave(struct net_device *dev, struct net_device *port_dev,
-+			  struct netlink_ext_ack *extack)
- {
- 	struct team *team = netdev_priv(dev);
- 	int err;
---- a/drivers/net/vrf.c
-+++ b/drivers/net/vrf.c
-@@ -791,7 +791,8 @@ err:
- 	return ret;
- }
- 
--static int vrf_add_slave(struct net_device *dev, struct net_device *port_dev)
-+static int vrf_add_slave(struct net_device *dev, struct net_device *port_dev,
-+			 struct netlink_ext_ack *extack)
- {
- 	if (netif_is_l3_master(port_dev) || netif_is_l3_slave(port_dev))
- 		return -EINVAL;
---- a/drivers/of/device.c
-+++ b/drivers/of/device.c
-@@ -15,6 +15,9 @@
- 
- #include <asm/errno.h>
- #include "of_private.h"
-+#ifdef CONFIG_FSL_MC_BUS
-+#include <linux/fsl/mc.h>
-+#endif
- 
- /**
-  * of_match_device - Tell if a struct device matches an of_device_id list
-@@ -105,6 +108,9 @@ int of_dma_configure(struct device *dev,
- #ifdef CONFIG_ARM_AMBA
- 		    dev->bus != &amba_bustype &&
- #endif
-+#ifdef CONFIG_FSL_MC_BUS
-+		    dev->bus != &fsl_mc_bus_type &&
-+#endif
- 		    dev->bus != &platform_bus_type)
- 			return ret == -ENODEV ? 0 : ret;
- 
-@@ -155,7 +161,12 @@ int of_dma_configure(struct device *dev,
- 	dev->coherent_dma_mask &= mask;
- 	*dev->dma_mask &= mask;
- 
--	coherent = of_dma_is_coherent(np);
-+#ifdef CONFIG_FSL_MC_BUS
-+	if (dev_is_fsl_mc(dev))
-+		coherent = fsl_mc_is_dev_coherent(dev);
-+	else
-+#endif
-+		coherent = of_dma_is_coherent(np);
- 	dev_dbg(dev, "device is%sdma coherent\n",
- 		coherent ? " " : " not ");
- 
---- a/drivers/soc/fsl/guts.c
-+++ b/drivers/soc/fsl/guts.c
-@@ -213,6 +213,9 @@ static const struct of_device_id fsl_gut
- 	{ .compatible = "fsl,ls1021a-dcfg", },
- 	{ .compatible = "fsl,ls1043a-dcfg", },
- 	{ .compatible = "fsl,ls2080a-dcfg", },
-+	{ .compatible = "fsl,ls1088a-dcfg", },
-+	{ .compatible = "fsl,ls1012a-dcfg", },
-+	{ .compatible = "fsl,ls1046a-dcfg", },
- 	{}
- };
- MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
---- a/include/linux/fsl_devices.h
-+++ b/include/linux/fsl_devices.h
-@@ -99,7 +99,9 @@ struct fsl_usb2_platform_data {
- 	unsigned	suspended:1;
- 	unsigned	already_suspended:1;
- 	unsigned        has_fsl_erratum_a007792:1;
-+	unsigned        has_fsl_erratum_14:1;
- 	unsigned        has_fsl_erratum_a005275:1;
-+	unsigned        has_fsl_erratum_a006918:1;
- 	unsigned	has_fsl_erratum_a005697:1;
- 	unsigned        check_phy_clk_valid:1;
- 
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -1260,7 +1260,8 @@ struct net_device_ops {
- 						     u32 flow_id);
- #endif
- 	int			(*ndo_add_slave)(struct net_device *dev,
--						 struct net_device *slave_dev);
-+						 struct net_device *slave_dev,
-+						 struct netlink_ext_ack *extack);
- 	int			(*ndo_del_slave)(struct net_device *dev,
- 						 struct net_device *slave_dev);
- 	netdev_features_t	(*ndo_fix_features)(struct net_device *dev,
-@@ -2341,7 +2342,8 @@ int register_netdevice_notifier(struct n
- int unregister_netdevice_notifier(struct notifier_block *nb);
- 
- struct netdev_notifier_info {
--	struct net_device *dev;
-+	struct net_device	*dev;
-+	struct netlink_ext_ack	*extack;
- };
- 
- struct netdev_notifier_info_ext {
-@@ -2373,6 +2375,7 @@ static inline void netdev_notifier_info_
- 					     struct net_device *dev)
- {
- 	info->dev = dev;
-+	info->extack = NULL;
- }
- 
- static inline struct net_device *
-@@ -2381,6 +2384,12 @@ netdev_notifier_info_to_dev(const struct
- 	return info->dev;
- }
- 
-+static inline struct netlink_ext_ack *
-+netdev_notifier_info_to_extack(const struct netdev_notifier_info *info)
-+{
-+	return info->extack;
-+}
-+
- int call_netdevice_notifiers(unsigned long val, struct net_device *dev);
- 
- 
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -964,6 +964,7 @@ void kfree_skb_list(struct sk_buff *segs
- void skb_tx_error(struct sk_buff *skb);
- void consume_skb(struct sk_buff *skb);
- void __consume_stateless_skb(struct sk_buff *skb);
-+void skb_recycle(struct sk_buff *skb);
- void  __kfree_skb(struct sk_buff *skb);
- extern struct kmem_cache *skbuff_head_cache;
- 
-@@ -3293,6 +3294,7 @@ static inline void skb_free_datagram_loc
- }
- int skb_kill_datagram(struct sock *sk, struct sk_buff *skb, unsigned int flags);
- int skb_copy_bits(const struct sk_buff *skb, int offset, void *to, int len);
-+void copy_skb_header(struct sk_buff *new, const struct sk_buff *old);
- int skb_store_bits(struct sk_buff *skb, int offset, const void *from, int len);
- __wsum skb_copy_and_csum_bits(const struct sk_buff *skb, int offset, u8 *to,
- 			      int len, __wsum csum);
---- a/include/net/bonding.h
-+++ b/include/net/bonding.h
-@@ -592,7 +592,8 @@ void bond_destroy_sysfs(struct bond_net
- void bond_prepare_sysfs_group(struct bonding *bond);
- int bond_sysfs_slave_add(struct slave *slave);
- void bond_sysfs_slave_del(struct slave *slave);
--int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev);
-+int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev,
-+		 struct netlink_ext_ack *extack);
- int bond_release(struct net_device *bond_dev, struct net_device *slave_dev);
- u32 bond_xmit_hash(struct bonding *bond, struct sk_buff *skb);
- int bond_set_carrier(struct bonding *bond);
---- a/net/batman-adv/soft-interface.c
-+++ b/net/batman-adv/soft-interface.c
-@@ -872,7 +872,8 @@ free_bat_counters:
-  * Return: 0 if successful or error otherwise.
-  */
- static int batadv_softif_slave_add(struct net_device *dev,
--				   struct net_device *slave_dev)
-+				   struct net_device *slave_dev,
-+				   struct netlink_ext_ack *extack)
- {
- 	struct batadv_hard_iface *hard_iface;
- 	struct net *net = dev_net(dev);
---- a/net/bridge/br_device.c
-+++ b/net/bridge/br_device.c
-@@ -324,7 +324,8 @@ void br_netpoll_disable(struct net_bridg
- 
- #endif
- 
--static int br_add_slave(struct net_device *dev, struct net_device *slave_dev)
-+static int br_add_slave(struct net_device *dev, struct net_device *slave_dev,
-+			struct netlink_ext_ack *extack)
- 
- {
- 	struct net_bridge *br = netdev_priv(dev);
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -162,7 +162,6 @@ static struct list_head offload_base __r
- 
- static int netif_rx_internal(struct sk_buff *skb);
- static int call_netdevice_notifiers_info(unsigned long val,
--					 struct net_device *dev,
- 					 struct netdev_notifier_info *info);
- static struct napi_struct *napi_by_id(unsigned int napi_id);
- 
-@@ -1312,10 +1311,11 @@ EXPORT_SYMBOL(netdev_features_change);
- void netdev_state_change(struct net_device *dev)
- {
- 	if (dev->flags & IFF_UP) {
--		struct netdev_notifier_change_info change_info;
-+		struct netdev_notifier_change_info change_info = {
-+			.info.dev = dev,
-+		};
- 
--		change_info.flags_changed = 0;
--		call_netdevice_notifiers_info(NETDEV_CHANGE, dev,
-+		call_netdevice_notifiers_info(NETDEV_CHANGE,
- 					      &change_info.info);
- 		rtmsg_ifinfo(RTM_NEWLINK, dev, 0, GFP_KERNEL);
- 	}
-@@ -1536,9 +1536,10 @@ EXPORT_SYMBOL(dev_disable_lro);
- static int call_netdevice_notifier(struct notifier_block *nb, unsigned long val,
- 				   struct net_device *dev)
- {
--	struct netdev_notifier_info info;
-+	struct netdev_notifier_info info = {
-+		.dev = dev,
-+	};
- 
--	netdev_notifier_info_init(&info, dev);
- 	return nb->notifier_call(nb, val, &info);
- }
- 
-@@ -1663,11 +1664,9 @@ EXPORT_SYMBOL(unregister_netdevice_notif
-  */
- 
- static int call_netdevice_notifiers_info(unsigned long val,
--					 struct net_device *dev,
- 					 struct netdev_notifier_info *info)
- {
- 	ASSERT_RTNL();
--	netdev_notifier_info_init(info, dev);
- 	return raw_notifier_call_chain(&netdev_chain, val, info);
- }
- 
-@@ -1682,9 +1681,11 @@ static int call_netdevice_notifiers_info
- 
- int call_netdevice_notifiers(unsigned long val, struct net_device *dev)
- {
--	struct netdev_notifier_info info;
-+	struct netdev_notifier_info info = {
-+		.dev = dev,
-+	};
- 
--	return call_netdevice_notifiers_info(val, dev, &info);
-+	return call_netdevice_notifiers_info(val, &info);
- }
- EXPORT_SYMBOL(call_netdevice_notifiers);
- 
-@@ -1707,7 +1708,7 @@ static int call_netdevice_notifiers_mtu(
- 
- 	BUILD_BUG_ON(offsetof(struct netdev_notifier_info_ext, info) != 0);
- 
--	return call_netdevice_notifiers_info(val, dev, &info.info);
-+	return call_netdevice_notifiers_info(val, &info.info);
- }
- 
- #ifdef CONFIG_NET_INGRESS
-@@ -6338,7 +6339,15 @@ static int __netdev_upper_dev_link(struc
- 				   struct net_device *upper_dev, bool master,
- 				   void *upper_priv, void *upper_info)
- {
--	struct netdev_notifier_changeupper_info changeupper_info;
-+	struct netdev_notifier_changeupper_info changeupper_info = {
-+		.info = {
-+			.dev = dev,
-+		},
-+		.upper_dev = upper_dev,
-+		.master = master,
-+		.linking = true,
-+		.upper_info = upper_info,
-+	};
- 	int ret = 0;
- 
- 	ASSERT_RTNL();
-@@ -6356,12 +6365,7 @@ static int __netdev_upper_dev_link(struc
- 	if (master && netdev_master_upper_dev_get(dev))
- 		return -EBUSY;
- 
--	changeupper_info.upper_dev = upper_dev;
--	changeupper_info.master = master;
--	changeupper_info.linking = true;
--	changeupper_info.upper_info = upper_info;
--
--	ret = call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER, dev,
-+	ret = call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER,
- 					    &changeupper_info.info);
- 	ret = notifier_to_errno(ret);
- 	if (ret)
-@@ -6373,7 +6377,7 @@ static int __netdev_upper_dev_link(struc
- 		return ret;
- 
- 	netdev_update_addr_mask(dev);
--	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, dev,
-+	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- 					    &changeupper_info.info);
- 	ret = notifier_to_errno(ret);
- 	if (ret)
-@@ -6437,21 +6441,25 @@ EXPORT_SYMBOL(netdev_master_upper_dev_li
- void netdev_upper_dev_unlink(struct net_device *dev,
- 			     struct net_device *upper_dev)
- {
--	struct netdev_notifier_changeupper_info changeupper_info;
-+	struct netdev_notifier_changeupper_info changeupper_info = {
-+		.info = {
-+			.dev = dev,
-+		},
-+		.upper_dev = upper_dev,
-+		.linking = false,
-+	};
- 
- 	ASSERT_RTNL();
- 
--	changeupper_info.upper_dev = upper_dev;
- 	changeupper_info.master = netdev_master_upper_dev_get(dev) == upper_dev;
--	changeupper_info.linking = false;
- 
--	call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER, dev,
-+	call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER,
- 				      &changeupper_info.info);
- 
- 	__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
- 
- 	netdev_update_addr_mask(dev);
--	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, dev,
-+	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- 				      &changeupper_info.info);
- }
- EXPORT_SYMBOL(netdev_upper_dev_unlink);
-@@ -6467,11 +6475,13 @@ EXPORT_SYMBOL(netdev_upper_dev_unlink);
- void netdev_bonding_info_change(struct net_device *dev,
- 				struct netdev_bonding_info *bonding_info)
- {
--	struct netdev_notifier_bonding_info	info;
-+	struct netdev_notifier_bonding_info info = {
-+		.info.dev = dev,
-+	};
- 
- 	memcpy(&info.bonding_info, bonding_info,
- 	       sizeof(struct netdev_bonding_info));
--	call_netdevice_notifiers_info(NETDEV_BONDING_INFO, dev,
-+	call_netdevice_notifiers_info(NETDEV_BONDING_INFO,
- 				      &info.info);
- }
- EXPORT_SYMBOL(netdev_bonding_info_change);
-@@ -6597,11 +6607,13 @@ EXPORT_SYMBOL(dev_get_nest_level);
- void netdev_lower_state_changed(struct net_device *lower_dev,
- 				void *lower_state_info)
- {
--	struct netdev_notifier_changelowerstate_info changelowerstate_info;
-+	struct netdev_notifier_changelowerstate_info changelowerstate_info = {
-+		.info.dev = lower_dev,
-+	};
- 
- 	ASSERT_RTNL();
- 	changelowerstate_info.lower_state_info = lower_state_info;
--	call_netdevice_notifiers_info(NETDEV_CHANGELOWERSTATE, lower_dev,
-+	call_netdevice_notifiers_info(NETDEV_CHANGELOWERSTATE,
- 				      &changelowerstate_info.info);
- }
- EXPORT_SYMBOL(netdev_lower_state_changed);
-@@ -6892,11 +6904,14 @@ void __dev_notify_flags(struct net_devic
- 
- 	if (dev->flags & IFF_UP &&
- 	    (changes & ~(IFF_UP | IFF_PROMISC | IFF_ALLMULTI | IFF_VOLATILE))) {
--		struct netdev_notifier_change_info change_info;
-+		struct netdev_notifier_change_info change_info = {
-+			.info = {
-+				.dev = dev,
-+			},
-+			.flags_changed = changes,
-+		};
- 
--		change_info.flags_changed = changes;
--		call_netdevice_notifiers_info(NETDEV_CHANGE, dev,
--					      &change_info.info);
-+		call_netdevice_notifiers_info(NETDEV_CHANGE, &change_info.info);
- 	}
- }
- 
---- a/net/core/rtnetlink.c
-+++ b/net/core/rtnetlink.c
-@@ -1912,7 +1912,8 @@ static int do_setvfinfo(struct net_devic
- 	return err;
- }
- 
--static int do_set_master(struct net_device *dev, int ifindex)
-+static int do_set_master(struct net_device *dev, int ifindex,
-+			 struct netlink_ext_ack *extack)
- {
- 	struct net_device *upper_dev = netdev_master_upper_dev_get(dev);
- 	const struct net_device_ops *ops;
-@@ -1937,7 +1938,7 @@ static int do_set_master(struct net_devi
- 			return -EINVAL;
- 		ops = upper_dev->netdev_ops;
- 		if (ops->ndo_add_slave) {
--			err = ops->ndo_add_slave(upper_dev, dev);
-+			err = ops->ndo_add_slave(upper_dev, dev, extack);
- 			if (err)
- 				return err;
- 		} else {
-@@ -2074,7 +2075,7 @@ static int do_setlink(const struct sk_bu
- 	}
- 
- 	if (tb[IFLA_MASTER]) {
--		err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]));
-+		err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]), extack);
- 		if (err)
- 			goto errout;
- 		status |= DO_SETLINK_MODIFIED;
-@@ -2723,7 +2724,8 @@ replay:
- 				goto out_unregister;
- 		}
- 		if (tb[IFLA_MASTER]) {
--			err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]));
-+			err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]),
-+					    extack);
- 			if (err)
- 				goto out_unregister;
- 		}
---- a/net/core/skbuff.c
-+++ b/net/core/skbuff.c
-@@ -799,6 +799,32 @@ void napi_consume_skb(struct sk_buff *sk
- }
- EXPORT_SYMBOL(napi_consume_skb);
- 
-+/**
-+ * 	skb_recycle - clean up an skb for reuse
-+ * 	@skb: buffer
-+ *
-+ * 	Recycles the skb to be reused as a receive buffer. This
-+ * 	function does any necessary reference count dropping, and
-+ * 	cleans up the skbuff as if it just came from __alloc_skb().
-+ */
-+void skb_recycle(struct sk_buff *skb)
-+{
-+	struct skb_shared_info *shinfo;
-+	u8 head_frag = skb->head_frag;
-+
-+	skb_release_head_state(skb);
-+
-+	shinfo = skb_shinfo(skb);
-+	memset(shinfo, 0, offsetof(struct skb_shared_info, dataref));
-+	atomic_set(&shinfo->dataref, 1);
-+
-+	memset(skb, 0, offsetof(struct sk_buff, tail));
-+	skb->data = skb->head + NET_SKB_PAD;
-+	skb->head_frag = head_frag;
-+	skb_reset_tail_pointer(skb);
-+}
-+EXPORT_SYMBOL(skb_recycle);
-+
- /* Make sure a field is enclosed inside headers_start/headers_end section */
- #define CHECK_SKB_FIELD(field) \
- 	BUILD_BUG_ON(offsetof(struct sk_buff, field) <		\
-@@ -1318,7 +1344,7 @@ static void skb_headers_offset_update(st
- 	skb->inner_mac_header += off;
- }
- 
--static void copy_skb_header(struct sk_buff *new, const struct sk_buff *old)
-+void copy_skb_header(struct sk_buff *new, const struct sk_buff *old)
- {
- 	__copy_skb_header(new, old);
- 
-@@ -1326,6 +1352,7 @@ static void copy_skb_header(struct sk_bu
- 	skb_shinfo(new)->gso_segs = skb_shinfo(old)->gso_segs;
- 	skb_shinfo(new)->gso_type = skb_shinfo(old)->gso_type;
- }
-+EXPORT_SYMBOL(copy_skb_header);
- 
- static inline int skb_alloc_rx_flag(const struct sk_buff *skb)
- {
---- a/samples/bpf/Makefile
-+++ b/samples/bpf/Makefile
-@@ -178,6 +178,12 @@ HOSTLOADLIBES_syscall_tp += -lelf
- LLC ?= llc
- CLANG ?= clang
- 
-+# Detect that we're cross compiling and use the cross compiler
-+ifdef CROSS_COMPILE
-+HOSTCC = $(CROSS_COMPILE)gcc
-+CLANG_ARCH_ARGS = -target $(ARCH)
-+endif
-+
- # Trick to allow make to be run from this directory
- all: $(LIBBPF)
- 	$(MAKE) -C ../../ $(CURDIR)/
-@@ -228,9 +234,9 @@ $(obj)/tracex5_kern.o: $(obj)/syscall_nr
- $(obj)/%.o: $(src)/%.c
- 	$(CLANG) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) $(EXTRA_CFLAGS) -I$(obj) \
- 		-I$(srctree)/tools/testing/selftests/bpf/ \
--		-D__KERNEL__ -D__ASM_SYSREG_H -Wno-unused-value -Wno-pointer-sign \
--		-Wno-compare-distinct-pointer-types \
-+		-D__KERNEL__ -Wno-unused-value -Wno-pointer-sign \
-+		-D__TARGET_ARCH_$(ARCH) -Wno-compare-distinct-pointer-types \
- 		-Wno-gnu-variable-sized-type-not-at-end \
- 		-Wno-address-of-packed-member -Wno-tautological-compare \
--		-Wno-unknown-warning-option \
-+		-Wno-unknown-warning-option $(CLANG_ARCH_ARGS) \
- 		-O2 -emit-llvm -c $< -o -| $(LLC) -march=bpf -filetype=obj -o $@
---- a/samples/bpf/map_perf_test_kern.c
-+++ b/samples/bpf/map_perf_test_kern.c
-@@ -266,7 +266,7 @@ int stress_hash_map_lookup(struct pt_reg
- 	return 0;
- }
- 
--SEC("kprobe/sys_getpgrp")
-+SEC("kprobe/sys_getppid")
- int stress_array_map_lookup(struct pt_regs *ctx)
- {
- 	u32 key = 1, i;
---- a/samples/bpf/map_perf_test_user.c
-+++ b/samples/bpf/map_perf_test_user.c
-@@ -282,7 +282,7 @@ static void test_array_lookup(int cpu)
- 
- 	start_time = time_get_ns();
- 	for (i = 0; i < max_cnt; i++)
--		syscall(__NR_getpgrp, 0);
-+		syscall(__NR_getppid, 0);
- 	printf("%d:array_lookup %lld lookups per sec\n",
- 	       cpu, max_cnt * 1000000000ll * 64 / (time_get_ns() - start_time));
- }
---- a/tools/testing/selftests/bpf/bpf_helpers.h
-+++ b/tools/testing/selftests/bpf/bpf_helpers.h
-@@ -110,7 +110,47 @@ static int (*bpf_skb_under_cgroup)(void
- static int (*bpf_skb_change_head)(void *, int len, int flags) =
- 	(void *) BPF_FUNC_skb_change_head;
- 
-+/* Scan the ARCH passed in from ARCH env variable (see Makefile) */
-+#if defined(__TARGET_ARCH_x86)
-+	#define bpf_target_x86
-+	#define bpf_target_defined
-+#elif defined(__TARGET_ARCH_s930x)
-+	#define bpf_target_s930x
-+	#define bpf_target_defined
-+#elif defined(__TARGET_ARCH_arm64)
-+	#define bpf_target_arm64
-+	#define bpf_target_defined
-+#elif defined(__TARGET_ARCH_mips)
-+	#define bpf_target_mips
-+	#define bpf_target_defined
-+#elif defined(__TARGET_ARCH_powerpc)
-+	#define bpf_target_powerpc
-+	#define bpf_target_defined
-+#elif defined(__TARGET_ARCH_sparc)
-+	#define bpf_target_sparc
-+	#define bpf_target_defined
-+#else
-+	#undef bpf_target_defined
-+#endif
-+
-+/* Fall back to what the compiler says */
-+#ifndef bpf_target_defined
- #if defined(__x86_64__)
-+	#define bpf_target_x86
-+#elif defined(__s390x__)
-+	#define bpf_target_s930x
-+#elif defined(__aarch64__)
-+	#define bpf_target_arm64
-+#elif defined(__mips__)
-+	#define bpf_target_mips
-+#elif defined(__powerpc__)
-+	#define bpf_target_powerpc
-+#elif defined(__sparc__)
-+	#define bpf_target_sparc
-+#endif
-+#endif
-+
-+#if defined(bpf_target_x86)
- 
- #define PT_REGS_PARM1(x) ((x)->di)
- #define PT_REGS_PARM2(x) ((x)->si)
-@@ -123,7 +163,7 @@ static int (*bpf_skb_change_head)(void *
- #define PT_REGS_SP(x) ((x)->sp)
- #define PT_REGS_IP(x) ((x)->ip)
- 
--#elif defined(__s390x__)
-+#elif defined(bpf_target_s390x)
- 
- #define PT_REGS_PARM1(x) ((x)->gprs[2])
- #define PT_REGS_PARM2(x) ((x)->gprs[3])
-@@ -136,7 +176,7 @@ static int (*bpf_skb_change_head)(void *
- #define PT_REGS_SP(x) ((x)->gprs[15])
- #define PT_REGS_IP(x) ((x)->psw.addr)
- 
--#elif defined(__aarch64__)
-+#elif defined(bpf_target_arm64)
- 
- #define PT_REGS_PARM1(x) ((x)->regs[0])
- #define PT_REGS_PARM2(x) ((x)->regs[1])
-@@ -149,7 +189,7 @@ static int (*bpf_skb_change_head)(void *
- #define PT_REGS_SP(x) ((x)->sp)
- #define PT_REGS_IP(x) ((x)->pc)
- 
--#elif defined(__mips__)
-+#elif defined(bpf_target_mips)
- 
- #define PT_REGS_PARM1(x) ((x)->regs[4])
- #define PT_REGS_PARM2(x) ((x)->regs[5])
-@@ -162,7 +202,7 @@ static int (*bpf_skb_change_head)(void *
- #define PT_REGS_SP(x) ((x)->regs[29])
- #define PT_REGS_IP(x) ((x)->cp0_epc)
- 
--#elif defined(__powerpc__)
-+#elif defined(bpf_target_powerpc)
- 
- #define PT_REGS_PARM1(x) ((x)->gpr[3])
- #define PT_REGS_PARM2(x) ((x)->gpr[4])
-@@ -173,7 +213,7 @@ static int (*bpf_skb_change_head)(void *
- #define PT_REGS_SP(x) ((x)->sp)
- #define PT_REGS_IP(x) ((x)->nip)
- 
--#elif defined(__sparc__)
-+#elif defined(bpf_target_sparc)
- 
- #define PT_REGS_PARM1(x) ((x)->u_regs[UREG_I0])
- #define PT_REGS_PARM2(x) ((x)->u_regs[UREG_I1])
-@@ -183,6 +223,8 @@ static int (*bpf_skb_change_head)(void *
- #define PT_REGS_RET(x) ((x)->u_regs[UREG_I7])
- #define PT_REGS_RC(x) ((x)->u_regs[UREG_I0])
- #define PT_REGS_SP(x) ((x)->u_regs[UREG_FP])
-+
-+/* Should this also be a bpf_target check for the sparc case? */
- #if defined(__arch64__)
- #define PT_REGS_IP(x) ((x)->tpc)
- #else
-@@ -191,10 +233,10 @@ static int (*bpf_skb_change_head)(void *
- 
- #endif
- 
--#ifdef __powerpc__
-+#ifdef bpf_target_powerpc
- #define BPF_KPROBE_READ_RET_IP(ip, ctx)		({ (ip) = (ctx)->link; })
- #define BPF_KRETPROBE_READ_RET_IP		BPF_KPROBE_READ_RET_IP
--#elif defined(__sparc__)
-+#elif bpf_target_sparc
- #define BPF_KPROBE_READ_RET_IP(ip, ctx)		({ (ip) = PT_REGS_RET(ctx); })
- #define BPF_KRETPROBE_READ_RET_IP		BPF_KPROBE_READ_RET_IP
- #else
diff --git a/target/linux/layerscape/patches-4.14/301-arch-support-layerscape.patch b/target/linux/layerscape/patches-4.14/301-arch-support-layerscape.patch
deleted file mode 100644
index faa02bffa..000000000
--- a/target/linux/layerscape/patches-4.14/301-arch-support-layerscape.patch
+++ /dev/null
@@ -1,325 +0,0 @@
-From 6eeff55fd4756f271ad09a914078c9aa45f8359d Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 16 Nov 2018 14:23:40 +0800
-Subject: [PATCH 04/39] arch: support layerscape
-This is an integrated patch of arch for layerscape
-
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
-Signed-off-by: Alison Wang <alison.wang@freescale.com>
-Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
-Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
-Signed-off-by: Dave Liu <daveliu@freescale.com>
-Signed-off-by: Guanhua <guanhua.gao@nxp.com>
-Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
-Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
-Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
-Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
-Signed-off-by: Jin Qing <b24347@freescale.com>
-Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
-Signed-off-by: Li Yang <leoli@freescale.com>
-Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
-Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
-Signed-off-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
-Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
-Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
-Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
-Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
-Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
-Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
-Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
-Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- arch/arm/include/asm/delay.h          | 16 ++++++++++++++
- arch/arm/include/asm/io.h             | 31 +++++++++++++++++++++++++++
- arch/arm/include/asm/mach/map.h       |  4 ++--
- arch/arm/include/asm/pgtable.h        |  7 ++++++
- arch/arm/kernel/time.c                |  3 +++
- arch/arm/mm/dma-mapping.c             |  1 +
- arch/arm/mm/ioremap.c                 |  7 ++++++
- arch/arm/mm/mmu.c                     |  9 ++++++++
- arch/arm64/include/asm/cache.h        |  2 +-
- arch/arm64/include/asm/io.h           |  1 +
- arch/arm64/include/asm/pgtable-prot.h |  3 +++
- arch/arm64/include/asm/pgtable.h      |  5 +++++
- arch/arm64/mm/dma-mapping.c           |  1 +
- arch/arm64/mm/init.c                  | 12 +++++++----
- 14 files changed, 95 insertions(+), 7 deletions(-)
-
---- a/arch/arm/include/asm/delay.h
-+++ b/arch/arm/include/asm/delay.h
-@@ -85,6 +85,22 @@ extern void __bad_udelay(void);
- 			__const_udelay((n) * UDELAY_MULT)) :		\
- 	  __udelay(n))
- 
-+#define spin_event_timeout(condition, timeout, delay)                          \
-+({                                                                             \
-+	typeof(condition) __ret;                                               \
-+	int i = 0;							       \
-+	while (!(__ret = (condition)) && (i++ < timeout)) {		       \
-+		if (delay)                                                     \
-+			udelay(delay);                                         \
-+		else                                                           \
-+			cpu_relax();					       \
-+		udelay(1);						       \
-+	}								       \
-+	if (!__ret)                                                            \
-+		__ret = (condition);                                           \
-+	__ret;		                                                       \
-+})
-+
- /* Loop-based definitions for assembly code. */
- extern void __loop_delay(unsigned long loops);
- extern void __loop_udelay(unsigned long usecs);
---- a/arch/arm/include/asm/io.h
-+++ b/arch/arm/include/asm/io.h
-@@ -128,6 +128,7 @@ static inline u32 __raw_readl(const vola
- #define MT_DEVICE_NONSHARED	1
- #define MT_DEVICE_CACHED	2
- #define MT_DEVICE_WC		3
-+#define MT_MEMORY_RW_NS		4
- /*
-  * types 4 onwards can be found in asm/mach/map.h and are undefined
-  * for ioremap
-@@ -229,6 +230,34 @@ void __iomem *pci_remap_cfgspace(resourc
- #endif
- #endif
- 
-+/* access ports */
-+#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
-+#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
-+
-+#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
-+#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
-+
-+#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
-+#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
-+
-+/* Clear and set bits in one shot.  These macros can be used to clear and
-+ * set multiple bits in a register using a single read-modify-write.  These
-+ * macros can also be used to set a multiple-bit bit pattern using a mask,
-+ * by specifying the mask in the 'clear' parameter and the new bit pattern
-+ * in the 'set' parameter.
-+ */
-+
-+#define clrsetbits_be32(addr, clear, set) \
-+	iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
-+#define clrsetbits_le32(addr, clear, set) \
-+	iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
-+#define clrsetbits_be16(addr, clear, set) \
-+	iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
-+#define clrsetbits_le16(addr, clear, set) \
-+	iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
-+#define clrsetbits_8(addr, clear, set) \
-+	iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
-+
- /*
-  *  IO port access primitives
-  *  -------------------------
-@@ -417,6 +446,8 @@ void __iomem *ioremap_wc(resource_size_t
- #define ioremap_wc ioremap_wc
- #define ioremap_wt ioremap_wc
- 
-+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size);
-+
- void iounmap(volatile void __iomem *iomem_cookie);
- #define iounmap iounmap
- 
---- a/arch/arm/include/asm/mach/map.h
-+++ b/arch/arm/include/asm/mach/map.h
-@@ -21,9 +21,9 @@ struct map_desc {
- 	unsigned int type;
- };
- 
--/* types 0-3 are defined in asm/io.h */
-+/* types 0-4 are defined in asm/io.h */
- enum {
--	MT_UNCACHED = 4,
-+	MT_UNCACHED = 5,
- 	MT_CACHECLEAN,
- 	MT_MINICLEAN,
- 	MT_LOW_VECTORS,
---- a/arch/arm/include/asm/pgtable.h
-+++ b/arch/arm/include/asm/pgtable.h
-@@ -119,6 +119,13 @@ extern pgprot_t		pgprot_s2_device;
- #define pgprot_noncached(prot) \
- 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
- 
-+#define pgprot_cached(prot) \
-+	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
-+
-+#define pgprot_cached_ns(prot) \
-+	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
-+			L_PTE_MT_DEV_NONSHARED)
-+
- #define pgprot_writecombine(prot) \
- 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
- 
---- a/arch/arm/kernel/time.c
-+++ b/arch/arm/kernel/time.c
-@@ -12,6 +12,7 @@
-  *  reading the RTC at bootup, etc...
-  */
- #include <linux/clk-provider.h>
-+#include <linux/clockchips.h>
- #include <linux/clocksource.h>
- #include <linux/errno.h>
- #include <linux/export.h>
-@@ -121,5 +122,7 @@ void __init time_init(void)
- 		of_clk_init(NULL);
- #endif
- 		timer_probe();
-+
-+		tick_setup_hrtimer_broadcast();
- 	}
- }
---- a/arch/arm/mm/dma-mapping.c
-+++ b/arch/arm/mm/dma-mapping.c
-@@ -2416,6 +2416,7 @@ void arch_setup_dma_ops(struct device *d
- #endif
- 	dev->archdata.dma_ops_setup = true;
- }
-+EXPORT_SYMBOL(arch_setup_dma_ops);
- 
- void arch_teardown_dma_ops(struct device *dev)
- {
---- a/arch/arm/mm/ioremap.c
-+++ b/arch/arm/mm/ioremap.c
-@@ -398,6 +398,13 @@ void __iomem *ioremap_wc(resource_size_t
- }
- EXPORT_SYMBOL(ioremap_wc);
- 
-+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size)
-+{
-+	return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS,
-+				   __builtin_return_address(0));
-+}
-+EXPORT_SYMBOL(ioremap_cache_ns);
-+
- /*
-  * Remap an arbitrary physical address space into the kernel virtual
-  * address space as memory. Needed when the kernel wants to execute
---- a/arch/arm/mm/mmu.c
-+++ b/arch/arm/mm/mmu.c
-@@ -315,6 +315,13 @@ static struct mem_type mem_types[] __ro_
- 		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
- 		.domain    = DOMAIN_KERNEL,
- 	},
-+	[MT_MEMORY_RW_NS] = {
-+		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-+			     L_PTE_XN,
-+		.prot_l1   = PMD_TYPE_TABLE,
-+		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN,
-+		.domain    = DOMAIN_KERNEL,
-+	},
- 	[MT_ROM] = {
- 		.prot_sect = PMD_TYPE_SECT,
- 		.domain    = DOMAIN_KERNEL,
-@@ -651,6 +658,7 @@ static void __init build_mem_type_table(
- 	}
- 	kern_pgprot |= PTE_EXT_AF;
- 	vecs_pgprot |= PTE_EXT_AF;
-+	mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte;
- 
- 	/*
- 	 * Set PXN for user mappings
-@@ -679,6 +687,7 @@ static void __init build_mem_type_table(
- 	mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
- 	mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
- 	mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
-+	mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd;
- 	mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
- 	mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
- 	mem_types[MT_ROM].prot_sect |= cp->pmd;
---- a/arch/arm64/include/asm/cache.h
-+++ b/arch/arm64/include/asm/cache.h
-@@ -34,7 +34,7 @@
- #define ICACHE_POLICY_VIPT	2
- #define ICACHE_POLICY_PIPT	3
- 
--#define L1_CACHE_SHIFT		7
-+#define L1_CACHE_SHIFT		6
- #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
- 
- /*
---- a/arch/arm64/include/asm/io.h
-+++ b/arch/arm64/include/asm/io.h
-@@ -170,6 +170,7 @@ extern void __iomem *ioremap_cache(phys_
- #define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
- #define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
- #define ioremap_wt(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
-+#define ioremap_cache_ns(addr, size)	__ioremap((addr), (size), __pgprot(PROT_NORMAL_NS))
- #define iounmap				__iounmap
- 
- /*
---- a/arch/arm64/include/asm/pgtable-prot.h
-+++ b/arch/arm64/include/asm/pgtable-prot.h
-@@ -48,6 +48,8 @@
- #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
- #define PROT_NORMAL_WT		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
- #define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
-+#define PROT_NORMAL_NS		(PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
-+
- 
- #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
- #define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
-@@ -68,6 +70,7 @@
- #define PAGE_HYP_DEVICE		__pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
- 
- #define PAGE_S2			__pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
-+#define PAGE_S2_NS		__pgprot(PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF)
- #define PAGE_S2_DEVICE		__pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
- 
- #define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
---- a/arch/arm64/include/asm/pgtable.h
-+++ b/arch/arm64/include/asm/pgtable.h
-@@ -377,6 +377,11 @@ static inline int pmd_protnone(pmd_t pmd
- 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
- #define pgprot_writecombine(prot) \
- 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
-+#define pgprot_cached(prot) \
-+	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
-+			PTE_PXN | PTE_UXN)
-+#define pgprot_cached_ns(prot) \
-+	__pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
- #define pgprot_device(prot) \
- 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
- #define __HAVE_PHYS_MEM_ACCESS_PROT
---- a/arch/arm64/mm/dma-mapping.c
-+++ b/arch/arm64/mm/dma-mapping.c
-@@ -937,3 +937,4 @@ void arch_setup_dma_ops(struct device *d
- 	}
- #endif
- }
-+EXPORT_SYMBOL(arch_setup_dma_ops);
---- a/arch/arm64/mm/init.c
-+++ b/arch/arm64/mm/init.c
-@@ -457,6 +457,14 @@ void __init arm64_memblock_init(void)
- 	 * Register the kernel text, kernel data, initrd, and initial
- 	 * pagetables with memblock.
- 	 */
-+
-+	/* make this the first reservation so that there are no chances of
-+	 * overlap
-+	 */
-+	reserve_elfcorehdr();
-+
-+	reserve_crashkernel();
-+
- 	memblock_reserve(__pa_symbol(_text), _end - _text);
- #ifdef CONFIG_BLK_DEV_INITRD
- 	if (initrd_start) {
-@@ -476,10 +484,6 @@ void __init arm64_memblock_init(void)
- 	else
- 		arm64_dma_phys_limit = PHYS_MASK + 1;
- 
--	reserve_crashkernel();
--
--	reserve_elfcorehdr();
--
- 	high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
- 
- 	dma_contiguous_reserve(arm64_dma_phys_limit);
diff --git a/target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch b/target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch
deleted file mode 100644
index afe8d450d..000000000
--- a/target/linux/layerscape/patches-4.14/302-dts-support-layerscape.patch
+++ /dev/null
@@ -1,6848 +0,0 @@
-From caecd8632a257759735ed6dd9354091cae8a5746 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 16 Nov 2018 17:11:32 +0800
-Subject: [PATCH] dts: support layerscape This is an integrated patch of dts
- for layerscape
-
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
-Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
-Signed-off-by: Alan Wang <alan.wang@nxp.com>
-Signed-off-by: Alison Wang <alison.wang@nxp.com>
-Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
-Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
-Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
-Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
-Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
-Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
-Signed-off-by: Changming Huang <jerry.huang@nxp.com>
-Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
-Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
-Signed-off-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
-Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- arch/arm/boot/dts/ls1021a-qds.dts             |  28 +
- arch/arm/boot/dts/ls1021a-twr.dts             |  27 +
- arch/arm/boot/dts/ls1021a.dtsi                | 105 +++-
- arch/arm64/boot/dts/freescale/Makefile        |   9 +
- .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 123 +++++
- .../boot/dts/freescale/fsl-ls1012a-frdm.dts   |  96 ++--
- .../boot/dts/freescale/fsl-ls1012a-frwy.dts   | 177 +++++++
- .../boot/dts/freescale/fsl-ls1012a-qds.dts    | 133 +++--
- .../boot/dts/freescale/fsl-ls1012a-rdb.dts    | 100 ++--
- .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 179 +++++--
- .../boot/dts/freescale/fsl-ls1043-post.dtsi   |   3 +-
- .../dts/freescale/fsl-ls1043a-qds-sdk.dts     |  71 +++
- .../boot/dts/freescale/fsl-ls1043a-qds.dts    | 201 ++++++--
- .../dts/freescale/fsl-ls1043a-rdb-sdk.dts     |  71 +++
- .../dts/freescale/fsl-ls1043a-rdb-usdpaa.dts  | 117 +++++
- .../boot/dts/freescale/fsl-ls1043a-rdb.dts    |  75 ++-
- .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 196 +++++--
- .../boot/dts/freescale/fsl-ls1046-post.dtsi   |   2 +-
- .../dts/freescale/fsl-ls1046a-qds-sdk.dts     |  79 +++
- .../boot/dts/freescale/fsl-ls1046a-qds.dts    | 189 +++++--
- .../dts/freescale/fsl-ls1046a-rdb-sdk.dts     | 115 +++++
- .../dts/freescale/fsl-ls1046a-rdb-usdpaa.dts  | 110 ++++
- .../boot/dts/freescale/fsl-ls1046a-rdb.dts    |  44 +-
- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 182 +++++--
- .../boot/dts/freescale/fsl-ls1088a-qds.dts    |  88 ++--
- .../boot/dts/freescale/fsl-ls1088a-rdb.dts    | 150 ++++--
- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 486 ++++++++++++++++--
- .../boot/dts/freescale/fsl-ls2080a-qds.dts    | 100 ++--
- .../boot/dts/freescale/fsl-ls2080a-rdb.dts    | 118 +++--
- .../boot/dts/freescale/fsl-ls2080a-simu.dts   |  38 +-
- .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi |  42 +-
- .../boot/dts/freescale/fsl-ls2081a-rdb.dts    | 163 ++++++
- .../boot/dts/freescale/fsl-ls2088a-qds.dts    | 158 ++++--
- .../boot/dts/freescale/fsl-ls2088a-rdb.dts    | 118 +++--
- .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi |  44 +-
- .../boot/dts/freescale/fsl-ls208xa-qds.dtsi   |  43 +-
- .../boot/dts/freescale/fsl-ls208xa-rdb.dtsi   |  60 +--
- .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 210 ++++++--
- .../dts/freescale/qoriq-bman-portals-sdk.dtsi |  55 ++
- .../dts/freescale/qoriq-bman-portals.dtsi     |   8 +-
- .../boot/dts/freescale/qoriq-dpaa-eth.dtsi    |  97 ++++
- .../dts/freescale/qoriq-fman3-0-10g-0.dtsi    |  11 +-
- .../dts/freescale/qoriq-fman3-0-10g-1.dtsi    |  11 +-
- .../dts/freescale/qoriq-fman3-0-1g-0.dtsi     |   7 +-
- .../dts/freescale/qoriq-fman3-0-1g-1.dtsi     |   7 +-
- .../dts/freescale/qoriq-fman3-0-1g-2.dtsi     |   7 +-
- .../dts/freescale/qoriq-fman3-0-1g-3.dtsi     |   7 +-
- .../dts/freescale/qoriq-fman3-0-1g-4.dtsi     |   7 +-
- .../dts/freescale/qoriq-fman3-0-1g-5.dtsi     |   7 +-
- .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi |  47 ++
- .../boot/dts/freescale/qoriq-fman3-0.dtsi     |  54 +-
- .../dts/freescale/qoriq-qman-portals-sdk.dtsi |  38 ++
- .../dts/freescale/qoriq-qman-portals.dtsi     |   9 +-
- .../boot/dts/fsl/qoriq-fman-0-10g-0.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman-0-1g-0.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-0-1g-1.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-0-1g-2.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-0-1g-3.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-0-1g-4.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-1-10g-0.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman-1-1g-0.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-1-1g-1.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-1-1g-2.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-1-1g-3.dtsi       |   4 +-
- .../boot/dts/fsl/qoriq-fman-1-1g-4.dtsi       |   4 +-
- .../fsl/qoriq-fman3-0-10g-0-best-effort.dtsi  |   4 +-
- .../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi     |   4 +-
- .../fsl/qoriq-fman3-0-10g-1-best-effort.dtsi  |   4 +-
- .../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi     |   4 +-
- .../boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi     |   4 +-
- .../boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi     |   4 +-
- .../boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi      |   4 +-
- .../boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi      |   4 +-
- 83 files changed, 3742 insertions(+), 1000 deletions(-)
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
- create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
- create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
- create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
-
---- a/arch/arm/boot/dts/ls1021a-qds.dts
-+++ b/arch/arm/boot/dts/ls1021a-qds.dts
-@@ -124,6 +124,21 @@
- 	};
- };
- 
-+&qspi {
-+	num-cs = <2>;
-+	status = "okay";
-+
-+	qflash0: s25fl128s@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+};
-+
- &enet0 {
- 	tbi-handle = <&tbi0>;
- 	phy-handle = <&sgmii_phy1c>;
-@@ -239,6 +254,11 @@
- 		device-width = <1>;
- 	};
- 
-+	nand@2,0 {
-+		compatible = "fsl,ifc-nand";
-+		reg = <0x2 0x0 0x10000>;
-+	};
-+
- 	fpga: board-control@3,0 {
- 		#address-cells = <1>;
- 		#size-cells = <1>;
-@@ -331,3 +351,11 @@
- &uart1 {
- 	status = "okay";
- };
-+
-+&can0 {
-+	status = "okay";
-+};
-+
-+&can1 {
-+	status = "okay";
-+};
---- a/arch/arm/boot/dts/ls1021a-twr.dts
-+++ b/arch/arm/boot/dts/ls1021a-twr.dts
-@@ -142,6 +142,21 @@
- 	};
- };
- 
-+&qspi {
-+	num-cs = <2>;
-+	status = "okay";
-+
-+	qflash0: n25q128a13@0 {
-+		compatible = "n25q128a13", "jedec,spi-nor";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+};
-+
- &enet0 {
- 	tbi-handle = <&tbi1>;
- 	phy-handle = <&sgmii_phy2>;
-@@ -228,6 +243,10 @@
- 	};
- };
- 
-+&esdhc {
-+	status = "okay";
-+};
-+
- &sai1 {
- 	status = "okay";
- };
-@@ -243,3 +262,11 @@
- &uart1 {
- 	status = "okay";
- };
-+
-+&can0 {
-+	status = "okay";
-+};
-+
-+&can1 {
-+	status = "okay";
-+};
---- a/arch/arm/boot/dts/ls1021a.dtsi
-+++ b/arch/arm/boot/dts/ls1021a.dtsi
-@@ -146,12 +146,13 @@
- 		ifc: ifc@1530000 {
- 			compatible = "fsl,ifc", "simple-bus";
- 			reg = <0x0 0x1530000 0x0 0x10000>;
-+			big-endian;
- 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
- 		dcfg: dcfg@1ee0000 {
- 			compatible = "fsl,ls1021a-dcfg", "syscon";
--			reg = <0x0 0x1ee0000 0x0 0x10000>;
-+			reg = <0x0 0x1ee0000 0x0 0x1000>;
- 			big-endian;
- 		};
- 
-@@ -334,25 +335,41 @@
- 			status = "disabled";
- 		};
- 
-+		qspi: quadspi@1550000 {
-+			compatible = "fsl,ls1021a-qspi";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x0 0x1550000 0x0 0x10000>,
-+				<0x0 0x40000000 0x0 0x4000000>;
-+			reg-names = "QuadSPI", "QuadSPI-memory";
-+			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-names = "qspi_en", "qspi";
-+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+			big-endian;
-+			status = "disabled";
-+		};
-+
- 		i2c0: i2c@2180000 {
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x2180000 0x0 0x10000>;
- 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- 			clock-names = "i2c";
- 			clocks = <&clockgen 4 1>;
-+			fsl-scl-gpio = <&gpio3 23 0>;
- 			status = "disabled";
- 		};
- 
- 		i2c1: i2c@2190000 {
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x2190000 0x0 0x10000>;
- 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- 			clock-names = "i2c";
- 			clocks = <&clockgen 4 1>;
-+			fsl-scl-gpio = <&gpio3 23 0>;
- 			status = "disabled";
- 		};
- 
-@@ -497,6 +514,17 @@
- 			status = "disabled";
- 		};
- 
-+		ftm0: ftm0@29d0000 {
-+			compatible = "fsl,ls1021a-ftm-alarm";
-+			reg = <0x0 0x29d0000 0x0 0x10000>,
-+			      <0x0 0x1ee2144 0x0 0x4>,
-+			      <0x0 0x0157051c 0x0 0x4>;
-+			reg-names = "ftm", "pmctrl", "scrachpad";
-+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-+			big-endian;
-+			status = "okay";
-+		};
-+
- 		wdog0: watchdog@2ad0000 {
- 			compatible = "fsl,imx21-wdt";
- 			reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -550,6 +578,25 @@
- 				 <&clockgen 4 1>;
- 		};
- 
-+		qdma: qdma@8390000 {
-+			compatible = "fsl,ls1021a-qdma";
-+			reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
-+			      <0x0 0x8389000 0x0 0x1000>, /* Status regs */
-+			      <0x0 0x838a000 0x0 0x2000>; /* Block regs */
-+			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "qdma-error",
-+				"qdma-queue0", "qdma-queue1";
-+			channels = <8>;
-+			block-number = <2>;
-+			block-offset = <0x1000>;
-+			queues = <2>;
-+			status-sizes = <64>;
-+			queue-sizes = <64 64>;
-+			big-endian;
-+		};
-+
- 		dcu: dcu@2ce0000 {
- 			compatible = "fsl,ls1021a-dcu";
- 			reg = <0x0 0x2ce0000 0x0 0x10000>;
-@@ -684,6 +731,10 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			configure-gfladj;
-+			usb3-lpm-capable;
-+			snps,dis-u1u2-when-u3-quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		pcie@3400000 {
-@@ -691,7 +742,9 @@
- 			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
- 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
- 			reg-names = "regs", "config";
--			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-+			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
-+					   <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+			interrupt-names = "pme", "aer";
- 			fsl,pcie-scfg = <&scfg 0>;
- 			#address-cells = <3>;
- 			#size-cells = <2>;
-@@ -714,7 +767,9 @@
- 			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
- 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
- 			reg-names = "regs", "config";
--			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
-+					   <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+			interrupt-names = "pme", "aer";
- 			fsl,pcie-scfg = <&scfg 1>;
- 			#address-cells = <3>;
- 			#size-cells = <2>;
-@@ -731,5 +786,45 @@
- 					<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
- 					<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
- 		};
-+
-+		can0: can@2a70000 {
-+			compatible = "fsl,ls1021ar2-flexcan";
-+			reg = <0x0 0x2a70000 0x0 0x1000>;
-+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+			clock-names = "ipg", "per";
-+			big-endian;
-+			status = "disabled";
-+		};
-+
-+		can1: can@2a80000 {
-+			compatible = "fsl,ls1021ar2-flexcan";
-+			reg = <0x0 0x2a80000 0x0 0x1000>;
-+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+			clock-names = "ipg", "per";
-+			big-endian;
-+			status = "disabled";
-+		};
-+
-+		can2: can@2a90000 {
-+			compatible = "fsl,ls1021ar2-flexcan";
-+			reg = <0x0 0x2a90000 0x0 0x1000>;
-+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+			clock-names = "ipg", "per";
-+			big-endian;
-+			status = "disabled";
-+		};
-+
-+		can3: can@2aa0000 {
-+			compatible = "fsl,ls1021ar2-flexcan";
-+			reg = <0x0 0x2aa0000 0x0 0x1000>;
-+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
-+			clock-names = "ipg", "per";
-+			big-endian;
-+			status = "disabled";
-+		};
- 	};
- };
---- a/arch/arm64/boot/dts/freescale/Makefile
-+++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -1,15 +1,24 @@
- # SPDX-License-Identifier: GPL-2.0
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
-+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
- dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
-@@ -0,0 +1,123 @@
-+/*
-+ * Device Tree file for NXP LS1012A 2G5RDB Board.
-+ *
-+ * Copyright 2017 NXP
-+ *
-+ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+/dts-v1/;
-+
-+#include "fsl-ls1012a.dtsi"
-+
-+/ {
-+	model = "LS1012A 2G5RDB Board";
-+	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
-+
-+	aliases {
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
-+	};
-+};
-+
-+&duart0 {
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+};
-+
-+&qspi {
-+	num-cs = <2>;
-+	bus-num = <0>;
-+	status = "okay";
-+
-+	qflash0: s25fs512s@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		m25p,fast-read;
-+		reg = <0>;
-+	};
-+};
-+
-+&sata {
-+	status = "okay";
-+};
-+
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii-2500";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = < 0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = < 0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii-2500";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
-@@ -1,45 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS1012A Freedom Board.
-  *
-  * Copyright 2016 Freescale Semiconductor, Inc.
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- /dts-v1/;
- 
-@@ -49,6 +13,11 @@
- 	model = "LS1012A Freedom Board";
- 	compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
- 
-+	aliases {
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
-+	};
-+
- 	sys_mclk: clock-mclk {
- 		compatible = "fixed-clock";
- 		#clock-cells = <0>;
-@@ -110,6 +79,44 @@
- 	};
- };
- 
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
-+
- &sai2 {
- 	status = "okay";
- };
-@@ -117,3 +124,18 @@
- &sata {
- 	status = "okay";
- };
-+
-+&qspi {
-+	status = "okay";
-+	qflash0: s25fs512s@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		m25p,fast-read;
-+		reg = <0>;
-+		spi-rx-bus-width = <2>;
-+		spi-tx-bus-width = <2>;
-+	};
-+
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
-@@ -0,0 +1,177 @@
-+/*
-+ * Device Tree file for NXP LS1012A FRWY Board.
-+ *
-+ * Copyright 2018 NXP
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+/dts-v1/;
-+
-+#include "fsl-ls1012a.dtsi"
-+
-+/ {
-+	model = "LS1012A FRWY Board";
-+	compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
-+
-+	aliases {
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
-+	};
-+
-+	sys_mclk: clock-mclk {
-+		compatible = "fixed-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <25000000>;
-+	};
-+
-+	reg_1p8v: regulator-1p8v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "1P8V";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-always-on;
-+	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,format = "i2s";
-+		simple-audio-card,widgets =
-+			"Microphone", "Microphone Jack",
-+			"Headphone", "Headphone Jack",
-+			"Speaker", "Speaker Ext",
-+			"Line", "Line In Jack";
-+		simple-audio-card,routing =
-+			"MIC_IN", "Microphone Jack",
-+			"Microphone Jack", "Mic Bias",
-+			"LINE_IN", "Line In Jack",
-+			"Headphone Jack", "HP_OUT",
-+			"Speaker Ext", "LINE_OUT";
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&sai2>;
-+			frame-master;
-+			bitclock-master;
-+		};
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&codec>;
-+			frame-master;
-+			bitclock-master;
-+			system-clock-frequency = <25000000>;
-+		};
-+	};
-+};
-+
-+&pcie {
-+	status = "okay";
-+};
-+
-+&duart0 {
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	codec: sgtl5000@a {
-+		compatible = "fsl,sgtl5000";
-+		#sound-dai-cells = <0>;
-+		reg = <0xa>;
-+		VDDA-supply = <&reg_1p8v>;
-+		VDDIO-supply = <&reg_1p8v>;
-+		clocks = <&sys_mclk>;
-+	};
-+};
-+
-+&qspi {
-+	num-cs = <1>;
-+	bus-num = <0>;
-+	status = "okay";
-+
-+	qflash0: w25q16dw@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		m25p,fast-read;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
-+};
-+
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
-+
-+&sai2 {
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
-@@ -1,45 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS1012A QDS Board.
-  *
-  * Copyright 2016 Freescale Semiconductor, Inc.
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- /dts-v1/;
- 
-@@ -49,6 +13,11 @@
- 	model = "LS1012A QDS Board";
- 	compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
- 
-+	aliases {
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
-+	};
-+
- 	sys_mclk: clock-mclk {
- 		compatible = "fixed-clock";
- 		#clock-cells = <0>;
-@@ -93,6 +62,43 @@
- 	};
- };
- 
-+&pcie {
-+	status = "okay";
-+};
-+
-+&dspi {
-+	bus-num = <0>;
-+	status = "okay";
-+
-+	flash@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "n25q128a11", "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <10000000>;
-+	};
-+
-+	flash@1 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "sst25wf040b", "jedec,spi-nor";
-+		spi-cpol;
-+		spi-cpha;
-+		reg = <1>;
-+		spi-max-frequency = <10000000>;
-+	};
-+
-+	flash@2 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "en25s64", "jedec,spi-nor";
-+		spi-cpol;
-+		spi-cpha;
-+		reg = <2>;
-+		spi-max-frequency = <10000000>;
-+	};
-+};
-+
- &duart0 {
- 	status = "okay";
- };
-@@ -131,6 +137,44 @@
- 	};
- };
- 
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x2>;
-+		phy-mode = "sgmii-2500";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x3>;
-+		phy-mode = "sgmii-2500";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
-+
- &sai2 {
- 	status = "okay";
- };
-@@ -138,3 +182,18 @@
- &sata {
- 	status = "okay";
- };
-+
-+&qspi {
-+	status = "okay";
-+	qflash0: s25fs512s@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		m25p,fast-read;
-+		reg = <0>;
-+		spi-rx-bus-width = <2>;
-+		spi-tx-bus-width = <2>;
-+	};
-+
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
-@@ -1,45 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS1012A RDB Board.
-  *
-  * Copyright 2016 Freescale Semiconductor, Inc.
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- /dts-v1/;
- 
-@@ -48,6 +12,15 @@
- / {
- 	model = "LS1012A RDB Board";
- 	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
-+
-+	aliases {
-+		ethernet0 = &pfe_mac0;
-+		ethernet1 = &pfe_mac1;
-+	};
-+};
-+
-+&pcie {
-+	status = "okay";
- };
- 
- &duart0 {
-@@ -74,3 +47,56 @@
- &sata {
- 	status = "okay";
- };
-+
-+&pfe {
-+	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	ethernet@0 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x0>;	/* GEM_ID */
-+		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "sgmii";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x1>; /* enabled/disabled */
-+		};
-+	};
-+
-+	ethernet@1 {
-+		compatible = "fsl,pfe-gemac-port";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x1>;	/* GEM_ID */
-+		fsl,gemac-bus-id = < 0x1 >;	/* BUS_ID */
-+		fsl,gemac-phy-id = < 0x1 >;	/* PHY_ID */
-+		fsl,mdio-mux-val = <0x0>;
-+		phy-mode = "rgmii-txid";
-+		fsl,pfe-phy-if-flags = <0x0>;
-+
-+		mdio@0 {
-+			reg = <0x0>; /* enabled/disabled */
-+		};
-+	};
-+};
-+
-+&qspi {
-+	status = "okay";
-+	qflash0: s25fs512s@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		m25p,fast-read;
-+		reg = <0>;
-+		spi-rx-bus-width = <2>;
-+		spi-tx-bus-width = <2>;
-+	};
-+
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
-@@ -1,45 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-1012A family SoC.
-  *
-  * Copyright 2016 Freescale Semiconductor, Inc.
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-@@ -70,6 +34,24 @@
- 			reg = <0x0>;
- 			clocks = <&clockgen 1 0>;
- 			#cooling-cells = <2>;
-+			cpu-idle-states = <&CPU_PH20>;
-+		};
-+	};
-+
-+	idle-states {
-+		/*
-+		 * PSCI node is not added default, U-boot will add missing
-+		 * parts if it determines to use PSCI.
-+		 */
-+		entry-method = "arm,psci";
-+
-+		CPU_PH20: cpu-ph20 {
-+			compatible = "arm,idle-state";
-+			idle-state-name = "PH20";
-+			arm,psci-suspend-param = <0x0>;
-+			entry-latency-us = <1000>;
-+			exit-latency-us = <1000>;
-+			min-residency-us = <3000>;
- 		};
- 	};
- 
-@@ -247,7 +229,7 @@
- 		dcfg: dcfg@1ee0000 {
- 			compatible = "fsl,ls1012a-dcfg",
- 				     "syscon";
--			reg = <0x0 0x1ee0000 0x0 0x10000>;
-+			reg = <0x0 0x1ee0000 0x0 0x1000>;
- 			big-endian;
- 		};
- 
-@@ -335,13 +317,23 @@
- 			};
- 		};
- 
-+		ftm0: ftm0@29d0000 {
-+			compatible = "fsl,ls1012a-ftm-alarm";
-+			reg = <0x0 0x29d0000 0x0 0x10000>,
-+			      <0x0 0x1ee2140 0x0 0x4>;
-+			reg-names = "ftm", "pmctrl";
-+			interrupts = <0 86 0x4>;
-+			big-endian;
-+		};
-+
- 		i2c0: i2c@2180000 {
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x2180000 0x0 0x10000>;
- 			interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&clockgen 4 0>;
-+			clocks = <&clockgen 4 3>;
-+			fsl-scl-gpio = <&gpio0 13 0>;
- 			status = "disabled";
- 		};
- 
-@@ -351,7 +343,20 @@
- 			#size-cells = <0>;
- 			reg = <0x0 0x2190000 0x0 0x10000>;
- 			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&clockgen 4 3>;
-+			status = "disabled";
-+		};
-+
-+		dspi: dspi@2100000 {
-+			compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x0 0x2100000 0x0 0x10000>;
-+			interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-names = "dspi";
- 			clocks = <&clockgen 4 0>;
-+			spi-num-chipselects = <5>;
-+			big-endian;
- 			status = "disabled";
- 		};
- 
-@@ -400,6 +405,20 @@
- 			big-endian;
- 		};
- 
-+		qspi: quadspi@1550000 {
-+			compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x0 0x1550000 0x0 0x10000>,
-+				<0x0 0x40000000 0x0 0x10000000>;
-+			reg-names = "QuadSPI", "QuadSPI-memory";
-+			interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-names = "qspi_en", "qspi";
-+			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
-+			big-endian;
-+			status = "disabled";
-+		};
-+
- 		sai1: sai@2b50000 {
- 			#sound-dai-cells = <0>;
- 			compatible = "fsl,vf610-sai";
-@@ -451,6 +470,7 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		sata: sata@3200000 {
-@@ -471,5 +491,84 @@
- 			dr_mode = "host";
- 			phy_type = "ulpi";
- 		};
-+
-+		msi: msi-controller1@1572000 {
-+			compatible = "fsl,ls1012a-msi";
-+			reg = <0x0 0x1572000 0x0 0x8>;
-+			msi-controller;
-+			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
-+		pcie: pcie@3400000 {
-+			compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
-+			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
-+			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
-+			reg-names = "regs", "config";
-+			interrupts = <0 118 0x4>, /* AER interrupt */
-+				     <0 117 0x4>; /* PME interrupt */
-+			interrupt-names = "aer", "pme";
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+			device_type = "pci";
-+			num-lanes = <4>;
-+			bus-range = <0x0 0xff>;
-+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
-+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+			msi-parent = <&msi>;
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
-+			status = "disabled";
-+		};
-+
-+		rcpm: rcpm@1ee2000 {
-+			compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
-+			reg = <0x0 0x1ee2000 0x0 0x1000>;
-+			fsl,#rcpm-wakeup-cells = <1>;
-+		};
-+	};
-+
-+	reserved-memory {
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		pfe_reserved: packetbuffer@83400000 {
-+			reg = <0 0x83400000 0 0xc00000>;
-+		};
-+	};
-+
-+	pfe: pfe@04000000 {
-+		compatible = "fsl,pfe";
-+		reg =   <0x0 0x04000000 0x0 0xc00000>,	/* AXI 16M */
-+			<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */
-+		reg-names = "pfe", "pfe-ddr";
-+		fsl,pfe-num-interfaces = <0x2>;
-+		interrupts = <0 172 0x4>,    /* HIF interrupt */
-+			     <0 173 0x4>,    /*HIF_NOCPY interrupt */
-+			     <0 174 0x4>;    /* WoL interrupt */
-+		interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
-+		memory-region = <&pfe_reserved>;
-+		fsl,pfe-scfg = <&scfg 0>;
-+		fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
-+		clocks = <&clockgen 4 0>;
-+		clock-names = "pfe";
-+
-+		status = "okay";
-+		pfe_mac0: ethernet@0 {
-+		};
-+
-+		pfe_mac1: ethernet@1 {
-+		};
-+	};
-+
-+	firmware {
-+		optee {
-+			compatible = "linaro,optee-tz";
-+			method = "smc";
-+		};
- 	};
- };
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
-@@ -1,9 +1,8 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 device tree nodes for ls1043
-  *
-  * Copyright 2015-2016 Freescale Semiconductor Inc.
-- *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- &soc {
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
-@@ -0,0 +1,71 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-+ *
-+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
-+ *
-+ * Mingkai Hu <Mingkai.hu@freescale.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "fsl-ls1043a-qds.dts"
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+	compatible = "fsl,bman-fbpr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+	compatible = "fsl,qman-fqd";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+	compatible = "fsl,qman-pfdr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+};
-+
-+&fman0 {
-+	compatible = "fsl,fman", "simple-bus";
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-  *
-  * Copyright 2014-2015 Freescale Semiconductor, Inc.
-  *
-  * Mingkai Hu <Mingkai.hu@freescale.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -60,6 +23,22 @@
- 		serial1 = &duart1;
- 		serial2 = &duart2;
- 		serial3 = &duart3;
-+		sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
-+		sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
-+		sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
-+		sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
-+		qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
-+		qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
-+		qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
-+		qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
-+		qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
-+		qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
-+		qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
-+		qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
-+		emi1_slot1 = &ls1043mdio_s1;
-+		emi1_slot2 = &ls1043mdio_s2;
-+		emi1_slot3 = &ls1043mdio_s3;
-+		emi1_slot4 = &ls1043mdio_s4;
- 	};
- 
- 	chosen {
-@@ -179,7 +158,153 @@
- 		#size-cells = <1>;
- 		spi-max-frequency = <20000000>;
- 		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
- 	};
- };
- 
- #include "fsl-ls1043-post.dtsi"
-+
-+&fman0 {
-+	ethernet@e0000 {
-+		phy-handle = <&qsgmii_phy_s2_p1>;
-+		phy-connection-type = "sgmii";
-+	};
-+
-+	ethernet@e2000 {
-+		phy-handle = <&qsgmii_phy_s2_p2>;
-+		phy-connection-type = "sgmii";
-+	};
-+
-+	ethernet@e4000 {
-+		phy-handle = <&rgmii_phy1>;
-+		phy-connection-type = "rgmii";
-+	};
-+
-+	ethernet@e6000 {
-+		phy-handle = <&rgmii_phy2>;
-+		phy-connection-type = "rgmii";
-+	};
-+
-+	ethernet@e8000 {
-+		phy-handle = <&qsgmii_phy_s2_p3>;
-+		phy-connection-type = "sgmii";
-+	};
-+
-+	ethernet@ea000 {
-+		phy-handle = <&qsgmii_phy_s2_p4>;
-+		phy-connection-type = "sgmii";
-+	};
-+
-+	ethernet@f0000 { /* DTSEC9/10GEC1 */
-+		fixed-link = <1 1 10000 0 0>;
-+		phy-connection-type = "xgmii";
-+	};
-+};
-+
-+&fpga {
-+	mdio-mux-emi1 {
-+		compatible = "mdio-mux-mmioreg", "mdio-mux";
-+		mdio-parent-bus = <&mdio0>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x54 1>;    /* BRDCFG4 */
-+		mux-mask = <0xe0>; /* EMI1 */
-+
-+		/* On-board RGMII1 PHY */
-+		ls1043mdio0: mdio@0 {
-+			reg = <0>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
-+				reg = <0x1>;
-+			};
-+		};
-+
-+		/* On-board RGMII2 PHY */
-+		ls1043mdio1: mdio@1 {
-+			reg = <0x20>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
-+				reg = <0x2>;
-+			};
-+		};
-+
-+		/* Slot 1 */
-+		ls1043mdio_s1: mdio@2 {
-+			reg = <0x40>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+
-+			qsgmii_phy_s1_p1: ethernet-phy@4 {
-+				reg = <0x4>;
-+			};
-+			qsgmii_phy_s1_p2: ethernet-phy@5 {
-+				reg = <0x5>;
-+			};
-+			qsgmii_phy_s1_p3: ethernet-phy@6 {
-+				reg = <0x6>;
-+			};
-+			qsgmii_phy_s1_p4: ethernet-phy@7 {
-+				reg = <0x7>;
-+			};
-+
-+			sgmii_phy_s1_p1: ethernet-phy@1c {
-+				reg = <0x1c>;
-+			};
-+		};
-+
-+		/* Slot 2 */
-+		ls1043mdio_s2: mdio@3 {
-+			reg = <0x60>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+
-+			qsgmii_phy_s2_p1: ethernet-phy@8 {
-+				reg = <0x8>;
-+			};
-+			qsgmii_phy_s2_p2: ethernet-phy@9 {
-+				reg = <0x9>;
-+			};
-+			qsgmii_phy_s2_p3: ethernet-phy@a {
-+				reg = <0xa>;
-+			};
-+			qsgmii_phy_s2_p4: ethernet-phy@b {
-+				reg = <0xb>;
-+			};
-+
-+			sgmii_phy_s2_p1: ethernet-phy@1c {
-+				reg = <0x1c>;
-+			};
-+		};
-+
-+		/* Slot 3 */
-+		ls1043mdio_s3: mdio@4 {
-+			reg = <0x80>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+
-+			sgmii_phy_s3_p1: ethernet-phy@1c {
-+				reg = <0x1c>;
-+			};
-+		};
-+
-+		/* Slot 4 */
-+		ls1043mdio_s4: mdio@5 {
-+			reg = <0xa0>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+
-+			sgmii_phy_s4_p1: ethernet-phy@1c {
-+				reg = <0x1c>;
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
-@@ -0,0 +1,71 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-+ *
-+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
-+ *
-+ * Mingkai Hu <Mingkai.hu@freescale.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "fsl-ls1043a-rdb.dts"
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+	compatible = "fsl,bman-fbpr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+	compatible = "fsl,qman-fqd";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+	compatible = "fsl,qman-pfdr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+};
-+
-+&fman0 {
-+	compatible = "fsl,fman", "simple-bus";
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
-@@ -0,0 +1,117 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-+ *
-+ * Copyright (C) 2014-2015, Freescale Semiconductor
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2.  This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include "fsl-ls1043a-rdb-sdk.dts"
-+
-+&soc {
-+	bp7: buffer-pool@7 {
-+		compatible = "fsl,p4080-bpool", "fsl,bpool";
-+		fsl,bpid = <7>;
-+		fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
-+		fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
-+	};
-+
-+	bp8: buffer-pool@8 {
-+		compatible = "fsl,p4080-bpool", "fsl,bpool";
-+		fsl,bpid = <8>;
-+		fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
-+		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
-+	};
-+
-+	bp9: buffer-pool@9 {
-+		compatible = "fsl,p4080-bpool", "fsl,bpool";
-+		fsl,bpid = <9>;
-+		fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
-+		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
-+	};
-+
-+	fsl,dpaa {
-+		compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
-+
-+		ethernet@0 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
-+			fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
-+		};
-+
-+		ethernet@1 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
-+			fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
-+		};
-+
-+		ethernet@2 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
-+			fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
-+		};
-+
-+		ethernet@3 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
-+			fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
-+		};
-+
-+		ethernet@4 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
-+			fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
-+		};
-+
-+		ethernet@5 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
-+			fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
-+		};
-+
-+		ethernet@8 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
-+			fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
-+
-+		};
-+		dpa-fman0-oh@2 {
-+			compatible = "fsl,dpa-oh";
-+			/* Define frame queues for the OH port*/
-+			/* <OH Rx error, OH Rx default> */
-+			fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
-+			fsl,fman-oh-port = <&fman0_oh2>;
-+		};
-+	};
-+};
-+/ {
-+	reserved-memory {
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		usdpaa_mem: usdpaa_mem {
-+			compatible = "fsl,usdpaa-mem";
-+			alloc-ranges = <0 0 0x10000 0>;
-+			size = <0 0x10000000>;
-+			alignment = <0 0x10000000>;
-+		};
-+	};
-+};
-+
-+&fman0 {
-+	fman0_oh2: port@83000 {
-+		cell-index = <1>;
-+		compatible = "fsl,fman-port-oh";
-+		reg = <0x83000 0x1000>;
-+	};
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-  *
-  * Copyright 2014-2015 Freescale Semiconductor, Inc.
-  *
-  * Mingkai Hu <Mingkai.hu@freescale.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -86,6 +49,10 @@
- 		compatible = "pericom,pt7c4338";
- 		reg = <0x68>;
- 	};
-+	rtc@51 {
-+		compatible = "nxp,pcf85263";
-+		reg = <0x51>;
-+	};
- };
- 
- &ifc {
-@@ -130,6 +97,38 @@
- 		reg = <0>;
- 		spi-max-frequency = <1000000>; /* input clock */
- 	};
-+
-+	slic@2 {
-+		compatible = "maxim,ds26522";
-+		reg = <2>;
-+		spi-max-frequency = <2000000>;
-+		fsl,spi-cs-sck-delay = <100>;
-+		fsl,spi-sck-cs-delay = <50>;
-+	};
-+
-+	slic@3 {
-+		compatible = "maxim,ds26522";
-+		reg = <3>;
-+		spi-max-frequency = <2000000>;
-+		fsl,spi-cs-sck-delay = <100>;
-+		fsl,spi-sck-cs-delay = <50>;
-+	};
-+};
-+
-+&uqe {
-+	ucc_hdlc: ucc@2000 {
-+		compatible = "fsl,ucc-hdlc";
-+		rx-clock-name = "clk8";
-+		tx-clock-name = "clk9";
-+		fsl,rx-sync-clock = "rsync_pin";
-+		fsl,tx-sync-clock = "tsync_pin";
-+		fsl,tx-timeslot-mask = <0xfffffffe>;
-+		fsl,rx-timeslot-mask = <0xfffffffe>;
-+		fsl,tdm-framer-type = "e1";
-+		fsl,tdm-id = <0>;
-+		fsl,siram-entry-id = <0>;
-+		fsl,tdm-interface;
-+	};
- };
- 
- &duart0 {
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
-  *
-  * Copyright 2014-2015 Freescale Semiconductor, Inc.
-  *
-  * Mingkai Hu <Mingkai.hu@freescale.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- #include <dt-bindings/thermal/thermal.h>
-@@ -81,6 +44,7 @@
- 			clocks = <&clockgen 1 0>;
- 			next-level-cache = <&l2>;
- 			#cooling-cells = <2>;
-+			cpu-idle-states = <&CPU_PH20>;
- 		};
- 
- 		cpu1: cpu@1 {
-@@ -89,6 +53,7 @@
- 			reg = <0x1>;
- 			clocks = <&clockgen 1 0>;
- 			next-level-cache = <&l2>;
-+			cpu-idle-states = <&CPU_PH20>;
- 		};
- 
- 		cpu2: cpu@2 {
-@@ -97,6 +62,7 @@
- 			reg = <0x2>;
- 			clocks = <&clockgen 1 0>;
- 			next-level-cache = <&l2>;
-+			cpu-idle-states = <&CPU_PH20>;
- 		};
- 
- 		cpu3: cpu@3 {
-@@ -105,6 +71,7 @@
- 			reg = <0x3>;
- 			clocks = <&clockgen 1 0>;
- 			next-level-cache = <&l2>;
-+			cpu-idle-states = <&CPU_PH20>;
- 		};
- 
- 		l2: l2-cache {
-@@ -112,6 +79,23 @@
- 		};
- 	};
- 
-+	idle-states {
-+		/*
-+		 * PSCI node is not added default, U-boot will add missing
-+		 * parts if it determines to use PSCI.
-+		 */
-+		entry-method = "arm,psci";
-+
-+		CPU_PH20: cpu-ph20 {
-+			compatible = "arm,idle-state";
-+			idle-state-name = "PH20";
-+			arm,psci-suspend-param = <0x0>;
-+			entry-latency-us = <1000>;
-+			exit-latency-us = <1000>;
-+			min-residency-us = <3000>;
-+		};
-+	};
-+
- 	memory@80000000 {
- 		device_type = "memory";
- 		reg = <0x0 0x80000000 0 0x80000000>;
-@@ -255,7 +239,7 @@
- 
- 		dcfg: dcfg@1ee0000 {
- 			compatible = "fsl,ls1043a-dcfg", "syscon";
--			reg = <0x0 0x1ee0000 0x0 0x10000>;
-+			reg = <0x0 0x1ee0000 0x0 0x1000>;
- 			big-endian;
- 		};
- 
-@@ -422,7 +406,7 @@
- 		};
- 
- 		i2c0: i2c@2180000 {
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x2180000 0x0 0x10000>;
-@@ -432,6 +416,7 @@
- 			dmas = <&edma0 1 39>,
- 			       <&edma0 1 38>;
- 			dma-names = "tx", "rx";
-+			fsl-scl-gpio = <&gpio4 12 0>;
- 			status = "disabled";
- 		};
- 
-@@ -536,6 +521,72 @@
- 			#interrupt-cells = <2>;
- 		};
- 
-+		uqe: uqe@2400000 {
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			device_type = "qe";
-+			compatible = "fsl,qe", "simple-bus";
-+			ranges = <0x0 0x0 0x2400000 0x40000>;
-+			reg = <0x0 0x2400000 0x0 0x480>;
-+			brg-frequency = <100000000>;
-+			bus-frequency = <200000000>;
-+
-+			fsl,qe-num-riscs = <1>;
-+			fsl,qe-num-snums = <28>;
-+
-+			qeic: qeic@80 {
-+				compatible = "fsl,qe-ic";
-+				reg = <0x80 0x80>;
-+				#address-cells = <0>;
-+				interrupt-controller;
-+				#interrupt-cells = <1>;
-+				interrupts = <0 77 0x04 0 77 0x04>;
-+			};
-+
-+			si1: si@700 {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+				compatible = "fsl,ls1043-qe-si",
-+						"fsl,t1040-qe-si";
-+				reg = <0x700 0x80>;
-+			};
-+
-+			siram1: siram@1000 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "fsl,ls1043-qe-siram",
-+						"fsl,t1040-qe-siram";
-+				reg = <0x1000 0x800>;
-+			};
-+
-+			ucc@2000 {
-+				cell-index = <1>;
-+				reg = <0x2000 0x200>;
-+				interrupts = <32>;
-+				interrupt-parent = <&qeic>;
-+			};
-+
-+			ucc@2200 {
-+				cell-index = <3>;
-+				reg = <0x2200 0x200>;
-+				interrupts = <34>;
-+				interrupt-parent = <&qeic>;
-+			};
-+
-+			muram@10000 {
-+				#address-cells = <1>;
-+				#size-cells = <1>;
-+				compatible = "fsl,qe-muram", "fsl,cpm-muram";
-+				ranges = <0x0 0x10000 0x6000>;
-+
-+				data-only@0 {
-+					compatible = "fsl,qe-muram-data",
-+					"fsl,cpm-muram-data";
-+					reg = <0x0 0x6000>;
-+				};
-+			};
-+		};
-+
- 		lpuart0: serial@2950000 {
- 			compatible = "fsl,ls1021a-lpuart";
- 			reg = <0x0 0x2950000 0x0 0x1000>;
-@@ -590,6 +641,16 @@
- 			status = "disabled";
- 		};
- 
-+		ftm0: ftm0@29d0000 {
-+			compatible = "fsl,ls1043a-ftm-alarm";
-+			reg = <0x0 0x29d0000 0x0 0x10000>,
-+			      <0x0 0x1ee2140 0x0 0x4>;
-+			reg-names = "ftm", "pmctrl";
-+			interrupts = <0 86 0x4>;
-+			big-endian;
-+			status = "okay";
-+		};
-+
- 		wdog0: wdog@2ad0000 {
- 			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
- 			reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -622,6 +683,9 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			usb3-lpm-capable;
-+			snps,dis-u1u2-when-u3-quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		usb1: usb3@3000000 {
-@@ -631,6 +695,9 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			usb3-lpm-capable;
-+			snps,dis-u1u2-when-u3-quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		usb2: usb3@3100000 {
-@@ -640,6 +707,9 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			usb3-lpm-capable;
-+			snps,dis-u1u2-when-u3-quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		sata: sata@3200000 {
-@@ -652,6 +722,27 @@
- 			dma-coherent;
- 		};
- 
-+		qdma: qdma@8380000 {
-+			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
-+			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
-+			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
-+			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
-+			interrupts = <0 152 0x4>,
-+				     <0 39 0x4>,
-+				     <0 40 0x4>,
-+				     <0 41 0x4>,
-+				     <0 42 0x4>;
-+			interrupt-names = "qdma-error", "qdma-queue0",
-+				"qdma-queue1", "qdma-queue2", "qdma-queue3";
-+			channels = <8>;
-+			block-number = <1>;
-+			block-offset = <0x10000>;
-+			queues = <2>;
-+			status-sizes = <64>;
-+			queue-sizes = <64 64>;
-+			big-endian;
-+		};
-+
- 		msi1: msi-controller1@1571000 {
- 			compatible = "fsl,ls1043a-msi";
- 			reg = <0x0 0x1571000 0x0 0x8>;
-@@ -678,9 +769,9 @@
- 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
- 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
- 			reg-names = "regs", "config";
--			interrupts = <0 118 0x4>, /* controller interrupt */
--				     <0 117 0x4>; /* PME interrupt */
--			interrupt-names = "intr", "pme";
-+			interrupts = <0 117 0x4>, /* PME interrupt */
-+				     <0 118 0x4>; /* aer interrupt */
-+			interrupt-names = "pme", "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -703,9 +794,9 @@
- 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
- 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
- 			reg-names = "regs", "config";
--			interrupts = <0 128 0x4>,
--				     <0 127 0x4>;
--			interrupt-names = "intr", "pme";
-+			interrupts = <0 127 0x4>,
-+				     <0 128 0x4>;
-+			interrupt-names = "pme", "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -728,9 +819,9 @@
- 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
- 			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
- 			reg-names = "regs", "config";
--			interrupts = <0 162 0x4>,
--				     <0 161 0x4>;
--			interrupt-names = "intr", "pme";
-+			interrupts = <0 161 0x4>,
-+				     <0 162 0x4>;
-+			interrupt-names = "pme", "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -749,6 +840,13 @@
- 		};
- 	};
- 
-+	firmware {
-+		optee {
-+			compatible = "linaro,optee-tz";
-+			method = "smc";
-+		};
-+	};
-+
- };
- 
- #include "qoriq-qman-portals.dtsi"
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
-@@ -1,9 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 device tree nodes for ls1046
-  *
-  * Copyright 2015-2016 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- &soc {
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
-@@ -0,0 +1,79 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-+ *
-+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
-+ *
-+ * Mingkai Hu <Mingkai.hu@freescale.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "fsl-ls1046a-qds.dts"
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+	compatible = "fsl,bman-fbpr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+	compatible = "fsl,qman-fqd";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+	compatible = "fsl,qman-pfdr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+};
-+
-+&fsldpaa {
-+	ethernet@9 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet7>;
-+		dma-coherent;
-+	};
-+};
-+
-+&fman0 {
-+	compatible = "fsl,fman", "simple-bus";
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-  *
-  * Copyright 2016 Freescale Semiconductor, Inc.
-  *
-  * Shaohui Xie <Shaohui.Xie@nxp.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -61,6 +24,20 @@
- 		serial1 = &duart1;
- 		serial2 = &duart2;
- 		serial3 = &duart3;
-+
-+		emi1_slot1 = &ls1046mdio_s1;
-+		emi1_slot2 = &ls1046mdio_s2;
-+		emi1_slot4 = &ls1046mdio_s4;
-+
-+		sgmii_s1_p1 = &sgmii_phy_s1_p1;
-+		sgmii_s1_p2 = &sgmii_phy_s1_p2;
-+		sgmii_s1_p3 = &sgmii_phy_s1_p3;
-+		sgmii_s1_p4 = &sgmii_phy_s1_p4;
-+		sgmii_s4_p1 = &sgmii_phy_s4_p1;
-+		qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
-+		qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
-+		qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
-+		qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
- 	};
- 
- 	chosen {
-@@ -208,7 +185,143 @@
- 		#size-cells = <1>;
- 		spi-max-frequency = <20000000>;
- 		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
- 	};
- };
- 
- #include "fsl-ls1046-post.dtsi"
-+
-+&fman0 {
-+	ethernet@e0000 {
-+		phy-handle = <&qsgmii_phy_s2_p1>;
-+		phy-connection-type = "sgmii";
-+	};
-+
-+	ethernet@e2000 {
-+		phy-handle = <&sgmii_phy_s4_p1>;
-+		phy-connection-type = "sgmii";
-+	};
-+
-+	ethernet@e4000 {
-+		phy-handle = <&rgmii_phy1>;
-+		phy-connection-type = "rgmii";
-+	};
-+
-+	ethernet@e6000 {
-+		phy-handle = <&rgmii_phy2>;
-+		phy-connection-type = "rgmii";
-+	};
-+
-+	ethernet@e8000 {
-+		phy-handle = <&sgmii_phy_s1_p3>;
-+		phy-connection-type = "sgmii";
-+	};
-+
-+	ethernet@ea000 {
-+		phy-handle = <&sgmii_phy_s1_p4>;
-+		phy-connection-type = "sgmii";
-+	};
-+
-+	ethernet@f0000 { /* DTSEC9/10GEC1 */
-+		phy-handle = <&sgmii_phy_s1_p1>;
-+		phy-connection-type = "xgmii";
-+	};
-+
-+	ethernet@f2000 { /* DTSEC10/10GEC2 */
-+		phy-handle = <&sgmii_phy_s1_p2>;
-+		phy-connection-type = "xgmii";
-+	};
-+};
-+
-+&fpga {
-+	#address-cells = <1>;
-+	#size-cells = <1>;
-+	mdio-mux-emi1 {
-+		compatible = "mdio-mux-mmioreg", "mdio-mux";
-+		mdio-parent-bus = <&mdio0>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		reg = <0x54 1>;    /* BRDCFG4 */
-+		mux-mask = <0xe0>; /* EMI1 */
-+
-+		/* On-board RGMII1 PHY */
-+		ls1046mdio0: mdio@0 {
-+			reg = <0>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
-+				reg = <0x1>;
-+			};
-+		};
-+
-+		/* On-board RGMII2 PHY */
-+		ls1046mdio1: mdio@1 {
-+			reg = <0x20>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
-+				reg = <0x2>;
-+			};
-+		};
-+
-+		/* Slot 1 */
-+		ls1046mdio_s1: mdio@2 {
-+			reg = <0x40>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+
-+			sgmii_phy_s1_p1: ethernet-phy@1c {
-+				reg = <0x1c>;
-+			};
-+
-+			sgmii_phy_s1_p2: ethernet-phy@1d {
-+				reg = <0x1d>;
-+			};
-+
-+			sgmii_phy_s1_p3: ethernet-phy@1e {
-+				reg = <0x1e>;
-+			};
-+
-+			sgmii_phy_s1_p4: ethernet-phy@1f {
-+				reg = <0x1f>;
-+			};
-+		};
-+
-+		/* Slot 2 */
-+		ls1046mdio_s2: mdio@3 {
-+			reg = <0x60>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+
-+			qsgmii_phy_s2_p1: ethernet-phy@8 {
-+				reg = <0x8>;
-+			};
-+			qsgmii_phy_s2_p2: ethernet-phy@9 {
-+				reg = <0x9>;
-+			};
-+			qsgmii_phy_s2_p3: ethernet-phy@a {
-+				reg = <0xa>;
-+			};
-+			qsgmii_phy_s2_p4: ethernet-phy@b {
-+				reg = <0xb>;
-+			};
-+		};
-+
-+		/* Slot 4 */
-+		ls1046mdio_s4: mdio@5 {
-+			reg = <0x80>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			status = "disabled";
-+
-+			sgmii_phy_s4_p1: ethernet-phy@1c {
-+				reg = <0x1c>;
-+			};
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
-@@ -0,0 +1,115 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-+ *
-+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
-+ *
-+ * Mingkai Hu <Mingkai.hu@freescale.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+#include "fsl-ls1046a-rdb.dts"
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
-+&bman_fbpr {
-+	compatible = "fsl,bman-fbpr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_fqd {
-+	compatible = "fsl,qman-fqd";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+&qman_pfdr {
-+	compatible = "fsl,qman-pfdr";
-+	alloc-ranges = <0 0 0x10000 0>;
-+};
-+
-+&soc {
-+#include "qoriq-dpaa-eth.dtsi"
-+#include "qoriq-fman3-0-6oh.dtsi"
-+};
-+
-+&fsldpaa {
-+	ethernet@0 {
-+		status = "disabled";
-+	};
-+	ethernet@1 {
-+		status = "disabled";
-+	};
-+	ethernet@9 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet7>;
-+		dma-coherent;
-+	};
-+};
-+
-+&fman0 {
-+	compatible = "fsl,fman", "simple-bus";
-+};
-+
-+&mdio9 {
-+	pcsphy6: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x8C0 0x40>;   /* lane D */
-+	};
-+};
-+
-+&mdio10 {
-+	pcsphy7: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x880 0x40>;   /* lane C */
-+	};
-+};
-+
-+/* Update MAC connections to backplane PHYs
-+ * &mac9 {
-+ *	phy-handle = <&pcsphy6>;
-+ *};
-+ *
-+ *&mac10 {
-+ *	phy-handle = <&pcsphy7>;
-+ *};
-+*/
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
-@@ -0,0 +1,110 @@
-+/*
-+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-+ *
-+ * Copyright (C) 2016, Freescale Semiconductor
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2.  This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include "fsl-ls1046a-rdb-sdk.dts"
-+
-+&soc {
-+	bp7: buffer-pool@7 {
-+		compatible = "fsl,ls1046a-bpool", "fsl,bpool";
-+		fsl,bpid = <7>;
-+		fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
-+		fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
-+	};
-+
-+	bp8: buffer-pool@8 {
-+		compatible = "fsl,ls1046a-bpool", "fsl,bpool";
-+		fsl,bpid = <8>;
-+		fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
-+		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
-+	};
-+
-+	bp9: buffer-pool@9 {
-+		compatible = "fsl,ls1046a-bpool", "fsl,bpool";
-+		fsl,bpid = <9>;
-+		fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
-+		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
-+	};
-+
-+	fsl,dpaa {
-+		compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
-+
-+		ethernet@2 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
-+			fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
-+		};
-+
-+		ethernet@3 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
-+			fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
-+		};
-+
-+		ethernet@4 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
-+			fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
-+		};
-+
-+		ethernet@5 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
-+			fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
-+		};
-+
-+		ethernet@8 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
-+			fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
-+		};
-+
-+		ethernet@9 {
-+			compatible = "fsl,dpa-ethernet-init";
-+			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
-+			fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
-+			fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
-+		};
-+
-+		dpa-fman0-oh@2 {
-+			compatible = "fsl,dpa-oh";
-+			/* Define frame queues for the OH port*/
-+			/* <OH Rx error, OH Rx default> */
-+			fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
-+			fsl,fman-oh-port = <&fman0_oh2>;
-+		};
-+	};
-+};
-+/ {
-+	reserved-memory {
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		usdpaa_mem: usdpaa_mem {
-+			compatible = "fsl,usdpaa-mem";
-+			alloc-ranges = <0 0 0x10000 0>;
-+			size = <0 0x10000000>;
-+			alignment = <0 0x10000000>;
-+		};
-+	};
-+};
-+
-+&fman0 {
-+	fman0_oh2: port@83000 {
-+		cell-index = <1>;
-+		compatible = "fsl,fman-port-oh";
-+		reg = <0x83000 0x1000>;
-+	};
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-  *
-  * Copyright 2016 Freescale Semiconductor, Inc.
-  *
-  * Mingkai Hu <mingkai.hu@nxp.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -139,6 +102,7 @@
- 	num-cs = <2>;
- 	bus-num = <0>;
- 	status = "okay";
-+	fsl,qspi-has-second-chip;
- 
- 	qflash0: s25fs512s@0 {
- 		compatible = "spansion,m25p80";
-@@ -146,6 +110,8 @@
- 		#size-cells = <1>;
- 		spi-max-frequency = <20000000>;
- 		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
- 	};
- 
- 	qflash1: s25fs512s@1 {
-@@ -154,6 +120,8 @@
- 		#size-cells = <1>;
- 		spi-max-frequency = <20000000>;
- 		reg = <1>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
- 	};
- };
- 
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -1,47 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
-  *
-  * Copyright 2016 Freescale Semiconductor, Inc.
-  *
-  * Mingkai Hu <mingkai.hu@nxp.com>
-- *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-@@ -122,7 +85,7 @@
- 		CPU_PH20: cpu-ph20 {
- 			compatible = "arm,idle-state";
- 			idle-state-name = "PH20";
--			arm,psci-suspend-param = <0x00010000>;
-+			arm,psci-suspend-param = <0x0>;
- 			entry-latency-us = <1000>;
- 			exit-latency-us = <1000>;
- 			min-residency-us = <3000>;
-@@ -214,7 +177,6 @@
- 			clock-names = "qspi_en", "qspi";
- 			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
- 			big-endian;
--			fsl,qspi-has-second-chip;
- 			status = "disabled";
- 		};
- 
-@@ -304,7 +266,7 @@
- 
- 		dcfg: dcfg@1ee0000 {
- 			compatible = "fsl,ls1046a-dcfg", "syscon";
--			reg = <0x0 0x1ee0000 0x0 0x10000>;
-+			reg = <0x0 0x1ee0000 0x0 0x1000>;
- 			big-endian;
- 		};
- 
-@@ -407,7 +369,7 @@
- 		};
- 
- 		i2c0: i2c@2180000 {
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x2180000 0x0 0x10000>;
-@@ -416,6 +378,7 @@
- 			dmas = <&edma0 1 39>,
- 			       <&edma0 1 38>;
- 			dma-names = "tx", "rx";
-+			fsl-scl-gpio = <&gpio3 12 0>;
- 			status = "disabled";
- 		};
- 
-@@ -440,12 +403,13 @@
- 		};
- 
- 		i2c3: i2c@21b0000 {
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x21b0000 0x0 0x10000>;
- 			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- 			clocks = <&clockgen 4 1>;
-+			fsl-scl-gpio = <&gpio3 12 0>;
- 			status = "disabled";
- 		};
- 
-@@ -571,6 +535,15 @@
- 			status = "disabled";
- 		};
- 
-+		ftm0: ftm0@29d0000 {
-+			compatible = "fsl,ls1046a-ftm-alarm";
-+			reg = <0x0 0x29d0000 0x0 0x10000>,
-+			      <0x0 0x1ee2140 0x0 0x4>;
-+			reg-names = "ftm", "pmctrl";
-+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-+			big-endian;
-+		};
-+
- 		wdog0: watchdog@2ad0000 {
- 			compatible = "fsl,imx21-wdt";
- 			reg = <0x0 0x2ad0000 0x0 0x10000>;
-@@ -602,6 +575,9 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			usb3-lpm-capable;
-+			snps,dis-u1u2-when-u3-quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		usb1: usb@3000000 {
-@@ -611,6 +587,9 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			usb3-lpm-capable;
-+			snps,dis-u1u2-when-u3-quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		usb2: usb@3100000 {
-@@ -620,6 +599,9 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			usb3-lpm-capable;
-+			snps,dis-u1u2-when-u3-quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		sata: sata@3200000 {
-@@ -631,6 +613,27 @@
- 			clocks = <&clockgen 4 1>;
- 		};
- 
-+		qdma: qdma@8380000 {
-+			compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
-+			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
-+			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
-+			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
-+			interrupts = <0 153 0x4>,
-+				     <0 39 0x4>,
-+				     <0 40 0x4>,
-+				     <0 41 0x4>,
-+				     <0 42 0x4>;
-+			interrupt-names = "qdma-error", "qdma-queue0",
-+				"qdma-queue1", "qdma-queue2", "qdma-queue3";
-+			channels = <8>;
-+			block-number = <1>;
-+			block-offset = <0x10000>;
-+			queues = <2>;
-+			status-sizes = <64>;
-+			queue-sizes = <64 64>;
-+			big-endian;
-+		};
-+
- 		msi1: msi-controller@1580000 {
- 			compatible = "fsl,ls1046a-msi";
- 			msi-controller;
-@@ -661,6 +664,92 @@
- 				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- 		};
- 
-+		pcie@3400000 {
-+			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
-+			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
-+			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
-+			reg-names = "regs", "config";
-+			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+			interrupt-names = "pme", "aer";
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+			device_type = "pci";
-+			dma-coherent;
-+			num-lanes = <4>;
-+			num-ib-windows = <6>;
-+			num-ob-windows = <6>;
-+			bus-range = <0x0 0xff>;
-+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
-+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+			msi-parent = <&msi1>, <&msi2>, <&msi3>;
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
-+		pcie@3500000 {
-+			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
-+			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
-+			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
-+			reg-names = "regs", "config";
-+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "pme", "aer";
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+			device_type = "pci";
-+			dma-coherent;
-+			num-lanes = <2>;
-+			num-ib-windows = <6>;
-+			num-ob-windows = <6>;
-+			bus-range = <0x0 0xff>;
-+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
-+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+			msi-parent = <&msi1>, <&msi2>, <&msi3>;
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
-+		pcie@3600000 {
-+			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
-+			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
-+			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
-+			reg-names = "regs", "config";
-+			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
-+				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
-+			interrupt-names = "pme", "aer";
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+			device_type = "pci";
-+			dma-coherent;
-+			num-lanes = <2>;
-+			num-ib-windows = <6>;
-+			num-ob-windows = <6>;
-+			bus-range = <0x0 0xff>;
-+			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
-+				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+			msi-parent = <&msi1>, <&msi2>, <&msi3>;
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
-+		serdes1: serdes@1ea0000 {
-+			reg = <0x0 0x1ea0000 0 0x00002000>;
-+			compatible = "fsl,serdes-10g";
-+		};
-+
- 	};
- 
- 	reserved-memory {
-@@ -689,6 +778,13 @@
- 			no-map;
- 		};
- 	};
-+
-+	firmware {
-+		optee {
-+			compatible = "linaro,optee-tz";
-+			method = "smc";
-+		};
-+	};
- };
- 
- #include "qoriq-qman-portals.dtsi"
---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for NXP LS1088A QDS Board.
-  *
-@@ -5,43 +6,6 @@
-  *
-  * Harninder Rai <harninder.rai@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -134,6 +98,30 @@
- 	};
- };
- 
-+&qspi {
-+	status = "okay";
-+	fsl,qspi-has-second-chip;
-+	qflash0: s25fs512s@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+
-+	qflash1: s25fs512s@1 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <1>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+};
-+
- &duart0 {
- 	status = "okay";
- };
-@@ -149,3 +137,29 @@
- &sata {
- 	status = "okay";
- };
-+
-+&pcs_mdio1 {
-+		pcs_phy1: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x840 0x40>;/* lane B */
-+	};
-+};
-+
-+&pcs_mdio2 {
-+		pcs_phy2: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x800 0x40>;/* lane A */
-+	};
-+};
-+
-+/* Update DPMAC connections to backplane PHYs, under SerDes 0x1D_0xXX.
-+ * &dpmac1 {
-+ *	phy-handle = <&pcs_phy1>;
-+ * };
-+ */
---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for NXP LS1088A RDB Board.
-  *
-@@ -5,43 +6,6 @@
-  *
-  * Harninder Rai <harninder.rai@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -110,6 +74,31 @@
- 	};
- };
- 
-+&qspi {
-+	status = "okay";
-+	fsl,qspi-has-second-chip;
-+	qflash0: s25fs512s@0 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+
-+	qflash1: s25fs512s@1 {
-+		compatible = "spansion,m25p80";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <1>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+
-+};
-+
- &duart0 {
- 	status = "okay";
- };
-@@ -118,6 +107,14 @@
- 	status = "okay";
- };
- 
-+&usb0 {
-+	status = "okay";
-+};
-+
-+&usb1 {
-+	status = "okay";
-+};
-+
- &esdhc {
- 	status = "okay";
- };
-@@ -125,3 +122,82 @@
- &sata {
- 	status = "okay";
- };
-+
-+&emdio1 {
-+	/* Freescale F104 PHY1 */
-+	mdio1_phy1: emdio1_phy@1 {
-+		reg = <0x1c>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy2: emdio1_phy@2 {
-+		reg = <0x1d>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy3: emdio1_phy@3 {
-+		reg = <0x1e>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy4: emdio1_phy@4 {
-+		reg = <0x1f>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	/* F104 PHY2 */
-+	mdio1_phy5: emdio1_phy@5 {
-+		reg = <0x0c>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy6: emdio1_phy@6 {
-+		reg = <0x0d>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy7: emdio1_phy@7 {
-+		reg = <0x0e>;
-+		phy-connection-type = "qsgmii";
-+	};
-+	mdio1_phy8: emdio1_phy@8 {
-+		reg = <0x0f>;
-+		phy-connection-type = "qsgmii";
-+	};
-+};
-+
-+&emdio2 {
-+	/* Aquantia AQR105 10G PHY */
-+	mdio2_phy1: emdio2_phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 2 0x4>;
-+		reg = <0x0>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+/* DPMAC connections to external PHYs
-+ * based on LS1088A RM RevC - $24.1.2 SerDes Options
-+ */
-+/* DPMAC1 is 10G SFP+, fixed link */
-+&dpmac2 {
-+	phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac3 {
-+	phy-handle = <&mdio1_phy5>;
-+};
-+&dpmac4 {
-+	phy-handle = <&mdio1_phy6>;
-+};
-+&dpmac5 {
-+	phy-handle = <&mdio1_phy7>;
-+};
-+&dpmac6 {
-+	phy-handle = <&mdio1_phy8>;
-+};
-+&dpmac7 {
-+	phy-handle = <&mdio1_phy1>;
-+};
-+&dpmac8 {
-+	phy-handle = <&mdio1_phy2>;
-+};
-+&dpmac9 {
-+	phy-handle = <&mdio1_phy3>;
-+};
-+&dpmac10 {
-+	phy-handle = <&mdio1_phy4>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for NXP Layerscape-1088A family SoC.
-  *
-@@ -5,43 +6,6 @@
-  *
-  * Harninder Rai <harninder.rai@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/thermal/thermal.h>
-@@ -130,7 +94,7 @@
- 		CPU_PH20: cpu-ph20 {
- 			compatible = "arm,idle-state";
- 			idle-state-name = "PH20";
--			arm,psci-suspend-param = <0x00010000>;
-+			arm,psci-suspend-param = <0x0>;
- 			entry-latency-us = <1000>;
- 			exit-latency-us = <1000>;
- 			min-residency-us = <3000>;
-@@ -147,6 +111,15 @@
- 		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
- 		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
- 		interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		its: gic-its@6020000 {
-+			compatible = "arm,gic-v3-its";
-+			msi-controller;
-+			reg = <0x0 0x6020000 0 0x20000>;
-+		};
- 	};
- 
- 	timer {
-@@ -169,11 +142,31 @@
- 		clock-output-names = "sysclk";
- 	};
- 
-+	dcfg: dcfg@1e00000 {
-+		compatible = "fsl,ls1088a-dcfg", "syscon";
-+		reg = <0x0 0x1e00000 0x0 0x10000>;
-+		little-endian;
-+	};
-+
-+	rstcr: syscon@1e60000 {
-+		compatible = "fsl,ls1088a-rstcr", "syscon";
-+		reg = <0x0 0x1e60000 0x0 0x4>;
-+	};
-+
-+	reboot {
-+		compatible = "syscon-reboot";
-+		regmap = <&rstcr>;
-+		offset = <0x0>;
-+		mask = <0x02>;
-+	};
-+
-+
- 	soc {
- 		compatible = "simple-bus";
- 		#address-cells = <2>;
- 		#size-cells = <2>;
- 		ranges;
-+		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
- 
- 		clockgen: clocking@1300000 {
- 			compatible = "fsl,ls1088a-clockgen";
-@@ -283,6 +276,62 @@
- 			status = "disabled";
- 		};
- 
-+		cluster1_core0_watchdog: wdt@c000000 {
-+			compatible = "arm,sp805-wdt", "arm,primecell";
-+			reg = <0x0 0xc000000 0x0 0x1000>;
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "apb_pclk", "wdog_clk";
-+		};
-+
-+		cluster1_core1_watchdog: wdt@c010000 {
-+			compatible = "arm,sp805-wdt", "arm,primecell";
-+			reg = <0x0 0xc010000 0x0 0x1000>;
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "apb_pclk", "wdog_clk";
-+		};
-+
-+		cluster1_core2_watchdog: wdt@c020000 {
-+			compatible = "arm,sp805-wdt", "arm,primecell";
-+			reg = <0x0 0xc020000 0x0 0x1000>;
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "apb_pclk", "wdog_clk";
-+		};
-+
-+		cluster1_core3_watchdog: wdt@c030000 {
-+			compatible = "arm,sp805-wdt", "arm,primecell";
-+			reg = <0x0 0xc030000 0x0 0x1000>;
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "apb_pclk", "wdog_clk";
-+		};
-+
-+		cluster2_core0_watchdog: wdt@c100000 {
-+			compatible = "arm,sp805-wdt", "arm,primecell";
-+			reg = <0x0 0xc100000 0x0 0x1000>;
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "apb_pclk", "wdog_clk";
-+		};
-+
-+		cluster2_core1_watchdog: wdt@c110000 {
-+			compatible = "arm,sp805-wdt", "arm,primecell";
-+			reg = <0x0 0xc110000 0x0 0x1000>;
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "apb_pclk", "wdog_clk";
-+		};
-+
-+		cluster2_core2_watchdog: wdt@c120000 {
-+			compatible = "arm,sp805-wdt", "arm,primecell";
-+			reg = <0x0 0xc120000 0x0 0x1000>;
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "apb_pclk", "wdog_clk";
-+		};
-+
-+		cluster2_core3_watchdog: wdt@c130000 {
-+			compatible = "arm,sp805-wdt", "arm,primecell";
-+			reg = <0x0 0xc130000 0x0 0x1000>;
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "apb_pclk", "wdog_clk";
-+		};
-+
- 		gpio0: gpio@2300000 {
- 			compatible = "fsl,qoriq-gpio";
- 			reg = <0x0 0x2300000 0x0 0x10000>;
-@@ -323,6 +372,72 @@
- 			#interrupt-cells = <2>;
- 		};
- 
-+		/* TODO: WRIOP (CCSR?) */
-+		emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
-+					  * E-MDIO1: 0x1_6000
-+					  */
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8B96000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;	/* force the driver in LE mode */
-+
-+			/* Not necessary on the QDS, but needed on the RDB */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
-+					  * E-MDIO2: 0x1_7000
-+					  */
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8B97000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;	/* force the driver in LE mode */
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio1: mdio@0x8c07000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c07000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio2: mdio@0x8c0b000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c0b000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio3: mdio@0x8c0f000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c0f000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio4: mdio@0x8c13000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c13000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
- 		ifc: ifc@2240000 {
- 			compatible = "fsl,ifc", "simple-bus";
- 			reg = <0x0 0x2240000 0x0 0x20000>;
-@@ -333,13 +448,22 @@
- 			status = "disabled";
- 		};
- 
-+		ftm0: ftm0@2800000 {
-+			compatible = "fsl,ls1088a-ftm-alarm";
-+			reg = <0x0 0x2800000 0x0 0x10000>,
-+			      <0x0 0x1e34050 0x0 0x4>;
-+			reg-names = "ftm", "pmctrl";
-+			interrupts = <0 44 4>;
-+		};
-+
- 		i2c0: i2c@2000000 {
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x2000000 0x0 0x10000>;
- 			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 7>;
-+			fsl-scl-gpio = <&gpio3 30 0>;
- 			status = "disabled";
- 		};
- 
-@@ -349,7 +473,7 @@
- 			#size-cells = <0>;
- 			reg = <0x0 0x2010000 0x0 0x10000>;
- 			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 7>;
- 			status = "disabled";
- 		};
- 
-@@ -359,7 +483,7 @@
- 			#size-cells = <0>;
- 			reg = <0x0 0x2020000 0x0 0x10000>;
- 			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 7>;
- 			status = "disabled";
- 		};
- 
-@@ -369,7 +493,7 @@
- 			#size-cells = <0>;
- 			reg = <0x0 0x2030000 0x0 0x10000>;
- 			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 7>;
- 			status = "disabled";
- 		};
- 
-@@ -385,6 +509,26 @@
- 			status = "disabled";
- 		};
- 
-+		usb0: usb3@3100000 {
-+			compatible = "snps,dwc3";
-+			reg = <0x0 0x3100000 0x0 0x10000>;
-+			interrupts = <0 80 0x4>; /* Level high type */
-+			dr_mode = "host";
-+			configure-gfladj;
-+			snps,dis_rxdet_inp3_quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+		};
-+
-+		usb1: usb3@3110000 {
-+			compatible = "snps,dwc3";
-+			reg = <0x0 0x3110000 0x0 0x10000>;
-+			interrupts = <0 81 0x4>; /* Level high type */
-+			dr_mode = "host";
-+			configure-gfladj;
-+			snps,dis_rxdet_inp3_quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+		};
-+
- 		sata: sata@3200000 {
- 			compatible = "fsl,ls1088a-ahci";
- 			reg = <0x0 0x3200000 0x0 0x10000>,
-@@ -395,6 +539,17 @@
- 			dma-coherent;
- 			status = "disabled";
- 		};
-+		qspi: quadspi@20c0000 {
-+			compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x0 0x20c0000 0x0 0x10000>,
-+				<0x0 0x20000000 0x0 0x10000000>;
-+			reg-names = "QuadSPI", "QuadSPI-memory";
-+			interrupts = <0 25 0x4>; /* Level high type */
-+			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+			clock-names = "qspi_en", "qspi";
-+		};
- 
- 		crypto: crypto@8000000 {
- 			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
-@@ -434,6 +589,251 @@
- 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- 			};
- 		};
-+
-+		pcie@3400000 {
-+			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
-+			       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
-+			reg-names = "regs", "config";
-+			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+			interrupt-names = "aer";
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+			device_type = "pci";
-+			dma-coherent;
-+			num-lanes = <4>;
-+			bus-range = <0x0 0xff>;
-+			ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
-+				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
-+		pcie@3500000 {
-+			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
-+			       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
-+			reg-names = "regs", "config";
-+			interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+			interrupt-names = "aer";
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+			device_type = "pci";
-+			dma-coherent;
-+			num-lanes = <4>;
-+			bus-range = <0x0 0xff>;
-+			ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
-+				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
-+		pcie@3600000 {
-+			compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
-+			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
-+			       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
-+			reg-names = "regs", "config";
-+			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
-+			interrupt-names = "aer";
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+			device_type = "pci";
-+			dma-coherent;
-+			num-lanes = <8>;
-+			bus-range = <0x0 0xff>;
-+			ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
-+				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-+			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
-+					<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
-+		};
-+
-+		fsl_mc: fsl-mc@80c000000 {
-+			compatible = "fsl,qoriq-mc";
-+			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
-+			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-+			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
-+			dma-coherent;
-+			#address-cells = <3>;
-+			#size-cells = <1>;
-+
-+			/*
-+			 * Region type 0x0 - MC portals
-+			 * Region type 0x1 - QBMAN portals
-+			 */
-+			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
-+				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
-+
-+			dpmacs {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				dpmac1: dpmac@1 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <1>;
-+				};
-+
-+				dpmac2: dpmac@2 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <2>;
-+				};
-+
-+				dpmac3: dpmac@3 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <3>;
-+				};
-+
-+				dpmac4: dpmac@4 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <4>;
-+				};
-+
-+				dpmac5: dpmac@5 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <5>;
-+				};
-+
-+				dpmac6: dpmac@6 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <6>;
-+				};
-+
-+				dpmac7: dpmac@7 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <7>;
-+				};
-+
-+				dpmac8: dpmac@8 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <8>;
-+				};
-+
-+				dpmac9: dpmac@9 {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <9>;
-+				};
-+
-+				dpmac10: dpmac@a {
-+					compatible = "fsl,qoriq-mc-dpmac";
-+					reg = <0xa>;
-+				};
-+			};
-+		};
-+
-+		smmu: iommu@5000000 {
-+			compatible = "arm,mmu-500";
-+			reg = <0 0x5000000 0 0x800000>;
-+			#global-interrupts = <12>;
-+			#iommu-cells = <1>;
-+			stream-match-mask = <0x7C00>;
-+			interrupts = <0 13 4>, /* global secure fault */
-+				     <0 14 4>, /* combined secure interrupt */
-+				     <0 15 4>, /* global non-secure fault */
-+				     <0 16 4>, /* combined non-secure interrupt */
-+				/* performance counter interrupts 0-7 */
-+				     <0 211 4>,
-+				     <0 212 4>,
-+				     <0 213 4>,
-+				     <0 214 4>,
-+				     <0 215 4>,
-+				     <0 216 4>,
-+				     <0 217 4>,
-+				     <0 218 4>,
-+				/* per context interrupt, 64 interrupts */
-+				     <0 146 4>,
-+				     <0 147 4>,
-+				     <0 148 4>,
-+				     <0 149 4>,
-+				     <0 150 4>,
-+				     <0 151 4>,
-+				     <0 152 4>,
-+				     <0 153 4>,
-+				     <0 154 4>,
-+				     <0 155 4>,
-+				     <0 156 4>,
-+				     <0 157 4>,
-+				     <0 158 4>,
-+				     <0 159 4>,
-+				     <0 160 4>,
-+				     <0 161 4>,
-+				     <0 162 4>,
-+				     <0 163 4>,
-+				     <0 164 4>,
-+				     <0 165 4>,
-+				     <0 166 4>,
-+				     <0 167 4>,
-+				     <0 168 4>,
-+				     <0 169 4>,
-+				     <0 170 4>,
-+				     <0 171 4>,
-+				     <0 172 4>,
-+				     <0 173 4>,
-+				     <0 174 4>,
-+				     <0 175 4>,
-+				     <0 176 4>,
-+				     <0 177 4>,
-+				     <0 178 4>,
-+				     <0 179 4>,
-+				     <0 180 4>,
-+				     <0 181 4>,
-+				     <0 182 4>,
-+				     <0 183 4>,
-+				     <0 184 4>,
-+				     <0 185 4>,
-+				     <0 186 4>,
-+				     <0 187 4>,
-+				     <0 188 4>,
-+				     <0 189 4>,
-+				     <0 190 4>,
-+				     <0 191 4>,
-+				     <0 192 4>,
-+				     <0 193 4>,
-+				     <0 194 4>,
-+				     <0 195 4>,
-+				     <0 196 4>,
-+				     <0 197 4>,
-+				     <0 198 4>,
-+				     <0 199 4>,
-+				     <0 200 4>,
-+				     <0 201 4>,
-+				     <0 202 4>,
-+				     <0 203 4>,
-+				     <0 204 4>,
-+				     <0 205 4>,
-+				     <0 206 4>,
-+				     <0 207 4>,
-+				     <0 208 4>,
-+				     <0 209 4>;
-+		};
-+
-+		serdes1: serdes@1ea0000 {
-+				reg = <0x0 0x1ea0000 0 0x00002000>;
-+				compatible = "fsl,serdes-10g";
-+		};
- 	};
- 
-+	firmware {
-+		optee {
-+			compatible = "linaro,optee-tz";
-+			method = "smc";
-+		};
-+	};
- };
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS2080a QDS Board.
-  *
-@@ -7,43 +8,6 @@
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -59,3 +23,65 @@
- 		stdout-path = "serial0:115200n8";
- 	};
- };
-+
-+&ifc {
-+	boardctrl: board-control@3,0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
-+		reg = <3 0 0x300>;		/* TODO check address */
-+		ranges = <0 3 0 0x300>;
-+
-+		mdio_mux_emi1 {
-+			compatible = "mdio-mux-mmioreg", "mdio-mux";
-+			mdio-parent-bus = <&emdio1>;
-+			reg = <0x54 1>;		/* BRDCFG4 */
-+			mux-mask = <0xe0>;	/* EMI1_MDIO */
-+
-+			#address-cells=<1>;
-+			#size-cells = <0>;
-+
-+			/* Child MDIO buses, one for each riser card:
-+			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
-+			 * VSC8234 PHYs on the riser cards.
-+			 */
-+
-+			mdio_mux3: mdio@60 {
-+				reg = <0x60>;
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				mdio0_phy12: mdio_phy0@1c {
-+					reg = <0x1c>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy13: mdio_phy1@1d {
-+					reg = <0x1d>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy14: mdio_phy2@1e {
-+					reg = <0x1e>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy15: mdio_phy3@1f {
-+					reg = <0x1f>;
-+					phy-connection-type = "sgmii";
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
-+&dpmac9 {
-+	phy-handle = <&mdio0_phy12>;
-+};
-+&dpmac10 {
-+	phy-handle = <&mdio0_phy13>;
-+};
-+&dpmac11 {
-+	phy-handle = <&mdio0_phy14>;
-+};
-+&dpmac12 {
-+	phy-handle = <&mdio0_phy15>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS2080a RDB Board.
-  *
-@@ -7,43 +8,6 @@
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -59,3 +23,83 @@
- 		stdout-path = "serial1:115200n8";
- 	};
- };
-+
-+&emdio1 {
-+	status = "disabled";
-+	/* CS4340 PHYs */
-+	mdio1_phy1: emdio1_phy@1 {
-+		reg = <0x10>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy2: emdio1_phy@2 {
-+		reg = <0x11>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy3: emdio1_phy@3 {
-+		reg = <0x12>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy4: emdio1_phy@4 {
-+		reg = <0x13>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+&emdio2 {
-+	/* AQR405 PHYs */
-+	mdio2_phy1: emdio2_phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 1 0x4>; /* Level high type */
-+		reg = <0x0>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy2: emdio2_phy@2 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 2 0x4>; /* Level high type */
-+		reg = <0x1>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy3: emdio2_phy@3 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 4 0x4>; /* Level high type */
-+		reg = <0x2>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy4: emdio2_phy@4 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 5 0x4>; /* Level high type */
-+		reg = <0x3>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+/* Update DPMAC connections to external PHYs, under the assumption of
-+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
-+ */
-+/* Leave Cortina nodes commented out until driver is integrated
-+ *&dpmac1 {
-+ *	phy-handle = <&mdio1_phy1>;
-+ *};
-+ *&dpmac2 {
-+ *	phy-handle = <&mdio1_phy2>;
-+ *};
-+ *&dpmac3 {
-+ *	phy-handle = <&mdio1_phy3>;
-+ *};
-+ *&dpmac4 {
-+ *	phy-handle = <&mdio1_phy4>;
-+ *};
-+ */
-+
-+&dpmac5 {
-+	phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac6 {
-+	phy-handle = <&mdio2_phy2>;
-+};
-+&dpmac7 {
-+	phy-handle = <&mdio2_phy3>;
-+};
-+&dpmac8 {
-+	phy-handle = <&mdio2_phy4>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS2080a software Simulator model
-  *
-@@ -5,43 +6,6 @@
-  *
-  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPL or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-2080A family SoC.
-  *
-@@ -6,43 +7,6 @@
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- #include "fsl-ls208xa.dtsi"
-@@ -150,6 +114,10 @@
- 	};
- };
- 
-+&timer {
-+	fsl,erratum-a008585;
-+};
-+
- &pcie1 {
- 	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
- 	       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
-@@ -0,0 +1,163 @@
-+/*
-+ * Device Tree file for NXP LS2081A RDB Board.
-+ *
-+ * Copyright 2017 NXP
-+ *
-+ * Priyanka Jain <priyanka.jain@nxp.com>
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPLv2 or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ *  a) This library is free software; you can redistribute it and/or
-+ *     modify it under the terms of the GNU General Public License as
-+ *     published by the Free Software Foundation; either version 2 of the
-+ *     License, or (at your option) any later version.
-+ *
-+ *     This library is distributed in the hope that it will be useful,
-+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *     GNU General Public License for more details.
-+ *
-+ * Or, alternatively,
-+ *
-+ *  b) Permission is hereby granted, free of charge, to any person
-+ *     obtaining a copy of this software and associated documentation
-+ *     files (the "Software"), to deal in the Software without
-+ *     restriction, including without limitation the rights to use,
-+ *     copy, modify, merge, publish, distribute, sublicense, and/or
-+ *     sell copies of the Software, and to permit persons to whom the
-+ *     Software is furnished to do so, subject to the following
-+ *     conditions:
-+ *
-+ *     The above copyright notice and this permission notice shall be
-+ *     included in all copies or substantial portions of the Software.
-+ *
-+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ *     OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+
-+/dts-v1/;
-+
-+#include "fsl-ls2088a.dtsi"
-+
-+/ {
-+	model = "NXP Layerscape 2081A RDB Board";
-+	compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
-+
-+	aliases {
-+		serial0 = &serial0;
-+		serial1 = &serial1;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial1:115200n8";
-+	};
-+};
-+
-+&esdhc {
-+	status = "okay";
-+};
-+
-+&ifc {
-+	status = "disabled";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+	pca9547@75 {
-+		compatible = "nxp,pca9547";
-+		reg = <0x75>;
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+		i2c@1 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x01>;
-+			rtc@51 {
-+				compatible = "nxp,pcf2129";
-+				reg = <0x51>;
-+			};
-+		};
-+
-+		i2c@2 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x02>;
-+
-+			ina220@40 {
-+				compatible = "ti,ina220";
-+				reg = <0x40>;
-+				shunt-resistor = <500>;
-+			};
-+		};
-+
-+		i2c@3 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x3>;
-+
-+			adt7481@4c {
-+				compatible = "adi,adt7461";
-+				reg = <0x4c>;
-+			};
-+		};
-+	};
-+};
-+
-+&dspi {
-+	status = "okay";
-+	dflash0: n25q512a {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "st,m25p80";
-+		spi-max-frequency = <3000000>;
-+		reg = <0>;
-+	};
-+};
-+
-+&qspi {
-+	status = "okay";
-+	fsl,qspi-has-second-chip;
-+	flash0: s25fs512s@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "spansion,m25p80";
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
-+	flash1: s25fs512s@1 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+		compatible = "spansion,m25p80";
-+		spi-max-frequency = <20000000>;
-+		reg = <1>;
-+	};
-+};
-+
-+&sata0 {
-+	status = "okay";
-+};
-+
-+&sata1 {
-+	status = "okay";
-+};
-+
-+&usb0 {
-+	status = "okay";
-+};
-+
-+&usb1 {
-+	status = "okay";
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS2088A QDS Board.
-  *
-@@ -6,43 +7,6 @@
-  *
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -58,3 +22,123 @@
- 		stdout-path = "serial0:115200n8";
- 	};
- };
-+
-+&ifc {
-+	boardctrl: board-control@3,0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
-+		reg = <3 0 0x300>;		/* TODO check address */
-+		ranges = <0 3 0 0x300>;
-+
-+		mdio_mux_emi1 {
-+			compatible = "mdio-mux-mmioreg", "mdio-mux";
-+			mdio-parent-bus = <&emdio1>;
-+			reg = <0x54 1>;		/* BRDCFG4 */
-+			mux-mask = <0xe0>;	/* EMI1_MDIO */
-+
-+			#address-cells=<1>;
-+			#size-cells = <0>;
-+
-+			/* Child MDIO buses, one for each riser card:
-+			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
-+			 * VSC8234 PHYs on the riser cards.
-+			 */
-+
-+			mdio_mux3: mdio@60 {
-+				reg = <0x60>;
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+
-+				mdio0_phy12: mdio_phy0@1c {
-+					reg = <0x1c>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy13: mdio_phy1@1d {
-+					reg = <0x1d>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy14: mdio_phy2@1e {
-+					reg = <0x1e>;
-+					phy-connection-type = "sgmii";
-+				};
-+				mdio0_phy15: mdio_phy3@1f {
-+					reg = <0x1f>;
-+					phy-connection-type = "sgmii";
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&pcs_mdio1 {
-+		pcs_phy1: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x9C0 0x40>;/* lane H */
-+	};
-+};
-+
-+&pcs_mdio2 {
-+		pcs_phy2: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x980 0x40>;/* lane G */
-+	};
-+};
-+
-+&pcs_mdio3 {
-+		pcs_phy3: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x940 0x40>;/* lane F */
-+	};
-+};
-+
-+&pcs_mdio4 {
-+		pcs_phy4: ethernet-phy@0 {
-+		backplane-mode = "10gbase-kr";
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		reg = <0x0>;
-+		fsl,lane-handle = <&serdes1>;
-+		fsl,lane-reg = <0x900 0x40>;/* lane E */
-+	};
-+};
-+
-+/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
-+ * &dpmac1 {
-+ *	phy-handle = <&pcs_phy1>;
-+ * };
-+ *
-+ * &dpmac2 {
-+ *	phy-handle = <&pcs_phy2>;
-+ * };
-+ *
-+ * &dpmac3 {
-+ *	phy-handle = <&pcs_phy3>;
-+ * };
-+ *
-+ * &dpmac4 {
-+ *	phy-handle = <&pcs_phy4>;
-+ * };
-+ */
-+
-+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
-+&dpmac9 {
-+	phy-handle = <&mdio0_phy12>;
-+};
-+&dpmac10 {
-+	phy-handle = <&mdio0_phy13>;
-+};
-+&dpmac11 {
-+	phy-handle = <&mdio0_phy14>;
-+};
-+&dpmac12 {
-+	phy-handle = <&mdio0_phy15>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS2088A RDB Board.
-  *
-@@ -6,43 +7,6 @@
-  *
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- /dts-v1/;
-@@ -58,3 +22,83 @@
- 		stdout-path = "serial1:115200n8";
- 	};
- };
-+
-+&emdio1 {
-+	status = "disabled";
-+	/* CS4340 PHYs */
-+	mdio1_phy1: emdio1_phy@1 {
-+		reg = <0x10>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy2: emdio1_phy@2 {
-+		reg = <0x11>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy3: emdio1_phy@3 {
-+		reg = <0x12>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio1_phy4: emdio1_phy@4 {
-+		reg = <0x13>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+&emdio2 {
-+	/* AQR405 PHYs */
-+	mdio2_phy1: emdio2_phy@1 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 1 0x4>; /* Level high type */
-+		reg = <0x0>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy2: emdio2_phy@2 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 2 0x4>; /* Level high type */
-+		reg = <0x1>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy3: emdio2_phy@3 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 4 0x4>; /* Level high type */
-+		reg = <0x2>;
-+		phy-connection-type = "xfi";
-+	};
-+	mdio2_phy4: emdio2_phy@4 {
-+		compatible = "ethernet-phy-ieee802.3-c45";
-+		interrupts = <0 5 0x4>; /* Level high type */
-+		reg = <0x3>;
-+		phy-connection-type = "xfi";
-+	};
-+};
-+
-+/* Update DPMAC connections to external PHYs, under the assumption of
-+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
-+ */
-+/* Leave Cortina PHYs commented out until proper driver is integrated
-+ *&dpmac1 {
-+ *	phy-handle = <&mdio1_phy1>;
-+ *};
-+ *&dpmac2 {
-+ *	phy-handle = <&mdio1_phy2>;
-+ *};
-+ *&dpmac3 {
-+ *	phy-handle = <&mdio1_phy3>;
-+ *};
-+ *&dpmac4 {
-+ *	phy-handle = <&mdio1_phy4>;
-+ *};
-+ */
-+
-+&dpmac5 {
-+	phy-handle = <&mdio2_phy1>;
-+};
-+&dpmac6 {
-+	phy-handle = <&mdio2_phy2>;
-+};
-+&dpmac7 {
-+	phy-handle = <&mdio2_phy3>;
-+};
-+&dpmac8 {
-+	phy-handle = <&mdio2_phy4>;
-+};
---- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-2088A family SoC.
-  *
-@@ -6,43 +7,6 @@
-  *
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- #include "fsl-ls208xa.dtsi"
-@@ -143,7 +107,7 @@
- 	CPU_PW20: cpu-pw20 {
- 		compatible = "arm,idle-state";
- 		idle-state-name = "PW20";
--		arm,psci-suspend-param = <0x00010000>;
-+		arm,psci-suspend-param = <0x0>;
- 		entry-latency-us = <2000>;
- 		exit-latency-us = <2000>;
- 		min-residency-us = <6000>;
-@@ -151,6 +115,7 @@
- };
- 
- &pcie1 {
-+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
- 	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
- 	       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
- 
-@@ -159,6 +124,7 @@
- };
- 
- &pcie2 {
-+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
- 	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
- 	       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
- 
-@@ -167,6 +133,7 @@
- };
- 
- &pcie3 {
-+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
- 	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
- 	       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
- 
-@@ -175,6 +142,7 @@
- };
- 
- &pcie4 {
-+	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
- 	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
- 	       0x38 0x00000000 0x0 0x00002000>; /* configuration space */
- 
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS2080A QDS Board.
-  *
-@@ -6,43 +7,6 @@
-  *
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- &esdhc {
-@@ -165,16 +129,21 @@
- 
- &qspi {
- 	status = "okay";
-+	fsl,qspi-has-second-chip;
- 	flash0: s25fl256s1@0 {
- 		#address-cells = <1>;
- 		#size-cells = <1>;
- 		compatible = "st,m25p80";
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
- 		spi-max-frequency = <20000000>;
- 		reg = <0>;
- 	};
- 	flash2: s25fl256s1@2 {
- 		#address-cells = <1>;
- 		#size-cells = <1>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
- 		compatible = "st,m25p80";
- 		spi-max-frequency = <20000000>;
- 		reg = <0>;
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree file for Freescale LS2080A RDB Board.
-  *
-@@ -6,43 +7,6 @@
-  *
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- &esdhc {
-@@ -85,6 +49,7 @@
- 		reg = <0x75>;
- 		#address-cells = <1>;
- 		#size-cells = <0>;
-+		i2c-mux-never-disable;
- 		i2c@1 {
- 			#address-cells = <1>;
- 			#size-cells = <0>;
-@@ -95,6 +60,17 @@
- 			};
- 		};
- 
-+		i2c@2 {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+			reg = <0x02>;
-+			ina220@40 {
-+				compatible = "ti,ina220";
-+				reg = <0x40>;
-+				shunt-resistor = <500>;
-+			};
-+		};
-+
- 		i2c@3 {
- 			#address-cells = <1>;
- 			#size-cells = <0>;
-@@ -132,7 +108,15 @@
- };
- 
- &qspi {
--	status = "disabled";
-+	status = "okay";
-+	flash0: s25fs512s@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		compatible = "spansion,m25p80";
-+		m25p,fast-read;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
- };
- 
- &sata0 {
---- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
-@@ -1,3 +1,4 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- /*
-  * Device Tree Include file for Freescale Layerscape-2080A family SoC.
-  *
-@@ -6,43 +7,6 @@
-  *
-  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
-  *
-- * This file is dual-licensed: you can use it either under the terms
-- * of the GPLv2 or the X11 license, at your option. Note that this dual
-- * licensing only applies to this file, and not this project as a
-- * whole.
-- *
-- *  a) This library is free software; you can redistribute it and/or
-- *     modify it under the terms of the GNU General Public License as
-- *     published by the Free Software Foundation; either version 2 of the
-- *     License, or (at your option) any later version.
-- *
-- *     This library is distributed in the hope that it will be useful,
-- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
-- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- *     GNU General Public License for more details.
-- *
-- * Or, alternatively,
-- *
-- *  b) Permission is hereby granted, free of charge, to any person
-- *     obtaining a copy of this software and associated documentation
-- *     files (the "Software"), to deal in the Software without
-- *     restriction, including without limitation the rights to use,
-- *     copy, modify, merge, publish, distribute, sublicense, and/or
-- *     sell copies of the Software, and to permit persons to whom the
-- *     Software is furnished to do so, subject to the following
-- *     conditions:
-- *
-- *     The above copyright notice and this permission notice shall be
-- *     included in all copies or substantial portions of the Software.
-- *
-- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-- *     OTHER DEALINGS IN THE SOFTWARE.
-  */
- 
- #include <dt-bindings/thermal/thermal.h>
-@@ -111,13 +75,12 @@
- 		mask = <0x2>;
- 	};
- 
--	timer {
-+	timer: timer {
- 		compatible = "arm,armv8-timer";
- 		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
- 			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
- 			     <1 11 4>, /* Virtual PPI, active-low */
- 			     <1 10 4>; /* Hypervisor PPI, active-low */
--		fsl,erratum-a008585;
- 	};
- 
- 	pmu {
-@@ -135,6 +98,7 @@
- 		#address-cells = <2>;
- 		#size-cells = <2>;
- 		ranges;
-+		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
- 
- 		clockgen: clocking@1300000 {
- 			compatible = "fsl,ls2080a-clockgen";
-@@ -357,6 +321,8 @@
- 			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
- 			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
-+			dma-coherent;
- 			#address-cells = <3>;
- 			#size-cells = <1>;
- 
-@@ -460,6 +426,8 @@
- 			compatible = "arm,mmu-500";
- 			reg = <0 0x5000000 0 0x800000>;
- 			#global-interrupts = <12>;
-+			#iommu-cells = <1>;
-+			stream-match-mask = <0x7C00>;
- 			interrupts = <0 13 4>, /* global secure fault */
- 				     <0 14 4>, /* combined secure interrupt */
- 				     <0 15 4>, /* global non-secure fault */
-@@ -502,7 +470,6 @@
- 				     <0 204 4>, <0 205 4>,
- 				     <0 206 4>, <0 207 4>,
- 				     <0 208 4>, <0 209 4>;
--			mmu-masters = <&fsl_mc 0x300 0>;
- 		};
- 
- 		dspi: dspi@2100000 {
-@@ -574,15 +541,126 @@
- 			#interrupt-cells = <2>;
- 		};
- 
-+		/* TODO: WRIOP (CCSR?) */
-+		emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
-+					  * E-MDIO1: 0x1_6000
-+					  */
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8B96000 0x0 0x1000>;
-+			device_type = "mdio";	/* TODO: is this necessary? */
-+			little-endian;	/* force the driver in LE mode */
-+
-+			/* Not necessary on the QDS, but needed on the RDB */
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
-+					  * E-MDIO2: 0x1_7000
-+					  */
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8B97000 0x0 0x1000>;
-+			device_type = "mdio";	/* TODO: is this necessary? */
-+			little-endian;	/* force the driver in LE mode */
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio1: mdio@0x8c07000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c07000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio2: mdio@0x8c0b000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c0b000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio3: mdio@0x8c0f000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c0f000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio4: mdio@0x8c13000 {
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c13000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio5: mdio@0x8c17000 {
-+			status = "disabled";
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c17000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio6: mdio@0x8c1b000 {
-+			status = "disabled";
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c1b000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio7: mdio@0x8c1f000 {
-+			status = "disabled";
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c1f000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
-+		pcs_mdio8: mdio@0x8c23000 {
-+			status = "disabled";
-+			compatible = "fsl,fman-memac-mdio";
-+			reg = <0x0 0x8c23000 0x0 0x1000>;
-+			device_type = "mdio";
-+			little-endian;
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
-+
- 		i2c0: i2c@2000000 {
- 			status = "disabled";
--			compatible = "fsl,vf610-i2c";
-+			compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
- 			#address-cells = <1>;
- 			#size-cells = <0>;
- 			reg = <0x0 0x2000000 0x0 0x10000>;
- 			interrupts = <0 34 0x4>; /* Level high type */
- 			clock-names = "i2c";
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 1>;
-+			fsl-scl-gpio = <&gpio3 10 0>;
- 		};
- 
- 		i2c1: i2c@2010000 {
-@@ -593,7 +671,7 @@
- 			reg = <0x0 0x2010000 0x0 0x10000>;
- 			interrupts = <0 34 0x4>; /* Level high type */
- 			clock-names = "i2c";
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 1>;
- 		};
- 
- 		i2c2: i2c@2020000 {
-@@ -604,7 +682,7 @@
- 			reg = <0x0 0x2020000 0x0 0x10000>;
- 			interrupts = <0 35 0x4>; /* Level high type */
- 			clock-names = "i2c";
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 1>;
- 		};
- 
- 		i2c3: i2c@2030000 {
-@@ -615,7 +693,7 @@
- 			reg = <0x0 0x2030000 0x0 0x10000>;
- 			interrupts = <0 35 0x4>; /* Level high type */
- 			clock-names = "i2c";
--			clocks = <&clockgen 4 3>;
-+			clocks = <&clockgen 4 1>;
- 		};
- 
- 		ifc: ifc@2240000 {
-@@ -648,8 +726,8 @@
- 			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
- 				     "snps,dw-pcie";
- 			reg-names = "regs", "config";
--			interrupts = <0 108 0x4>; /* Level high type */
--			interrupt-names = "intr";
-+			interrupts = <0 108 0x4>; /* aer interrupt */
-+			interrupt-names = "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -657,6 +735,7 @@
- 			num-lanes = <4>;
- 			bus-range = <0x0 0xff>;
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 7>;
- 			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
-@@ -669,8 +748,8 @@
- 			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
- 				     "snps,dw-pcie";
- 			reg-names = "regs", "config";
--			interrupts = <0 113 0x4>; /* Level high type */
--			interrupt-names = "intr";
-+			interrupts = <0 113 0x4>; /* aer interrupt */
-+			interrupt-names = "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -678,6 +757,7 @@
- 			num-lanes = <4>;
- 			bus-range = <0x0 0xff>;
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 7>;
- 			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
-@@ -690,8 +770,8 @@
- 			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
- 				     "snps,dw-pcie";
- 			reg-names = "regs", "config";
--			interrupts = <0 118 0x4>; /* Level high type */
--			interrupt-names = "intr";
-+			interrupts = <0 118 0x4>; /* aer interrupt */
-+			interrupt-names = "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -699,6 +779,7 @@
- 			num-lanes = <8>;
- 			bus-range = <0x0 0xff>;
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 7>;
- 			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
-@@ -711,8 +792,8 @@
- 			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
- 				     "snps,dw-pcie";
- 			reg-names = "regs", "config";
--			interrupts = <0 123 0x4>; /* Level high type */
--			interrupt-names = "intr";
-+			interrupts = <0 123 0x4>; /* aer interrupt */
-+			interrupt-names = "aer";
- 			#address-cells = <3>;
- 			#size-cells = <2>;
- 			device_type = "pci";
-@@ -720,6 +801,7 @@
- 			num-lanes = <4>;
- 			bus-range = <0x0 0xff>;
- 			msi-parent = <&its>;
-+			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
- 			#interrupt-cells = <1>;
- 			interrupt-map-mask = <0 0 0 7>;
- 			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
-@@ -754,6 +836,7 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
- 		};
- 
- 		usb1: usb3@3110000 {
-@@ -764,6 +847,12 @@
- 			dr_mode = "host";
- 			snps,quirk-frame-length-adjustment = <0x20>;
- 			snps,dis_rxdet_inp3_quirk;
-+			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
-+		};
-+
-+		serdes1: serdes@1ea0000 {
-+				reg = <0x0 0x1ea0000 0 0x00002000>;
-+				compatible = "fsl,serdes-10g";
- 		};
- 
- 		ccn@4000000 {
-@@ -771,6 +860,14 @@
- 			reg = <0x0 0x04000000 0x0 0x01000000>;
- 			interrupts = <0 12 4>;
- 		};
-+
-+		ftm0: ftm0@2800000 {
-+			compatible = "fsl,ls208xa-ftm-alarm";
-+			reg = <0x0 0x2800000 0x0 0x10000>,
-+			      <0x0 0x1e34050 0x0 0x4>;
-+			reg-names = "ftm", "pmctrl";
-+			interrupts = <0 44 4>;
-+		};
- 	};
- 
- 	ddr1: memory-controller@1080000 {
-@@ -786,4 +883,11 @@
- 		interrupts = <0 18 0x4>;
- 		little-endian;
- 	};
-+
-+	firmware {
-+		optee {
-+			compatible = "linaro,optee-tz";
-+			method = "smc";
-+		};
-+	};
- };
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
-@@ -0,0 +1,55 @@
-+/*
-+ * QorIQ BMan SDK Portals device tree nodes
-+ *
-+ * Copyright 2011-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+ */
-+
-+&bportals {
-+	bman-portal@0 {
-+		cell-index = <0>;
-+	};
-+
-+	bman-portal@10000 {
-+		cell-index = <1>;
-+	};
-+
-+	bman-portal@20000 {
-+		cell-index = <2>;
-+	};
-+
-+	bman-portal@30000 {
-+		cell-index = <3>;
-+	};
-+
-+	bman-portal@40000 {
-+		cell-index = <4>;
-+	};
-+
-+	bman-portal@50000 {
-+		cell-index = <5>;
-+	};
-+
-+	bman-portal@60000 {
-+		cell-index = <6>;
-+	};
-+
-+	bman-portal@70000 {
-+		cell-index = <7>;
-+	};
-+
-+	bman-portal@80000 {
-+		cell-index = <8>;
-+	};
-+
-+	bman-portal@90000 {
-+		cell-index = <9>;
-+	};
-+
-+	 bman-bpids@0 {
-+		compatible = "fsl,bpid-range";
-+		fsl,bpid-range = <32 32>;
-+	};
-+};
---- a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
-@@ -1,9 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ BMan Portals device tree
-  *
-  * Copyright 2011-2016 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- &bportals {
-@@ -68,4 +68,10 @@
- 		reg = <0x80000 0x4000>, <0x4080000 0x4000>;
- 		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
- 	};
-+
-+	bman-portal@90000 {
-+		compatible = "fsl,bman-portal";
-+		reg = <0x90000 0x4000>, <0x4090000 0x4000>;
-+		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
-+	};
- };
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
-@@ -0,0 +1,97 @@
-+/*
-+ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
-+ *
-+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *       notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *       notice, this list of conditions and the following disclaimer in the
-+ *       documentation and/or other materials provided with the distribution.
-+ *     * Neither the name of Freescale Semiconductor nor the
-+ *       names of its contributors may be used to endorse or promote products
-+ *       derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+fsldpaa: fsl,dpaa {
-+	compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
-+	ethernet@0 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet0>;
-+		dma-coherent;
-+	};
-+	ethernet@1 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet1>;
-+		dma-coherent;
-+	};
-+	ethernet@2 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet2>;
-+		dma-coherent;
-+	};
-+	ethernet@3 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet3>;
-+		dma-coherent;
-+	};
-+	ethernet@4 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet4>;
-+		dma-coherent;
-+	};
-+	ethernet@5 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet5>;
-+		dma-coherent;
-+	};
-+	ethernet@8 {
-+		compatible = "fsl,dpa-ethernet";
-+		fsl,fman-mac = <&enet6>;
-+		dma-coherent;
-+	};
-+	ethernet@6 {
-+		compatible = "fsl,im-ethernet";
-+		fsl,fman-mac = <&enet2>;
-+		dma-coherent;
-+		fpmevt-sel = <0>;
-+	};
-+	ethernet@7 {
-+		compatible = "fsl,im-ethernet";
-+		fsl,fman-mac = <&enet3>;
-+		dma-coherent;
-+		fpmevt-sel = <1>;
-+	};
-+	ethernet@10 {
-+		compatible = "fsl,im-ethernet";
-+		fsl,fman-mac = <&enet4>;
-+		dma-coherent;
-+		fpmevt-sel = <2>;
-+	};
-+	ethernet@11 {
-+		compatible = "fsl,im-ethernet";
-+		fsl,fman-mac = <&enet5>;
-+		dma-coherent;
-+		fpmevt-sel = <3>;
-+	};
-+};
-+
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
-@@ -1,27 +1,28 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 10g port #0 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman@1a00000 {
- 	fman0_rx_0x10: port@90000 {
- 		cell-index = <0x10>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
- 		reg = <0x90000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
- 
- 	fman0_tx_0x30: port@b0000 {
- 		cell-index = <0x30>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
- 		reg = <0xb0000 0x1000>;
- 		fsl,fman-10g-port;
-+		fsl,qman-channel-id = <0x800>;
- 	};
- 
--	ethernet@f0000 {
-+	mac9: ethernet@f0000 {
- 		cell-index = <0x8>;
- 		compatible = "fsl,fman-memac";
- 		reg = <0xf0000 0x1000>;
-@@ -29,7 +30,7 @@ fman@1a00000 {
- 		pcsphy-handle = <&pcsphy6>;
- 	};
- 
--	mdio@f1000 {
-+	mdio9: mdio@f1000 {
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
-@@ -1,27 +1,28 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 10g port #1 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman@1a00000 {
- 	fman0_rx_0x11: port@91000 {
- 		cell-index = <0x11>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
- 		reg = <0x91000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
- 
- 	fman0_tx_0x31: port@b1000 {
- 		cell-index = <0x31>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
- 		reg = <0xb1000 0x1000>;
- 		fsl,fman-10g-port;
-+		fsl,qman-channel-id = <0x801>;
- 	};
- 
--	ethernet@f2000 {
-+	mac10: ethernet@f2000 {
- 		cell-index = <0x9>;
- 		compatible = "fsl,fman-memac";
- 		reg = <0xf2000 0x1000>;
-@@ -29,7 +30,7 @@ fman@1a00000 {
- 		pcsphy-handle = <&pcsphy7>;
- 	};
- 
--	mdio@f3000 {
-+	mdio10: mdio@f3000 {
- 		#address-cells = <1>;
- 		#size-cells = <0>;
- 		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 1g port #0 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman@1a00000 {
- 	fman0_rx_0x08: port@88000 {
- 		cell-index = <0x8>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- 		reg = <0x88000 0x1000>;
- 	};
- 
- 	fman0_tx_0x28: port@a8000 {
- 		cell-index = <0x28>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- 		reg = <0xa8000 0x1000>;
-+		fsl,qman-channel-id = <0x802>;
- 	};
- 
- 	ethernet@e0000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 1g port #1 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman@1a00000 {
- 	fman0_rx_0x09: port@89000 {
- 		cell-index = <0x9>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- 		reg = <0x89000 0x1000>;
- 	};
- 
- 	fman0_tx_0x29: port@a9000 {
- 		cell-index = <0x29>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- 		reg = <0xa9000 0x1000>;
-+		fsl,qman-channel-id = <0x803>;
- 	};
- 
- 	ethernet@e2000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 1g port #2 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman@1a00000 {
- 	fman0_rx_0x0a: port@8a000 {
- 		cell-index = <0xa>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- 		reg = <0x8a000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2a: port@aa000 {
- 		cell-index = <0x2a>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- 		reg = <0xaa000 0x1000>;
-+		fsl,qman-channel-id = <0x804>;
- 	};
- 
- 	ethernet@e4000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 1g port #3 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman@1a00000 {
- 	fman0_rx_0x0b: port@8b000 {
- 		cell-index = <0xb>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- 		reg = <0x8b000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2b: port@ab000 {
- 		cell-index = <0x2b>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- 		reg = <0xab000 0x1000>;
-+		fsl,qman-channel-id = <0x805>;
- 	};
- 
- 	ethernet@e6000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 1g port #4 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman@1a00000 {
- 	fman0_rx_0x0c: port@8c000 {
- 		cell-index = <0xc>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- 		reg = <0x8c000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2c: port@ac000 {
- 		cell-index = <0x2c>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- 		reg = <0xac000 0x1000>;
-+		fsl,qman-channel-id = <0x806>;
- 	};
- 
- 	ethernet@e8000 {
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
-@@ -1,22 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 1g port #5 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman@1a00000 {
- 	fman0_rx_0x0d: port@8d000 {
- 		cell-index = <0xd>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
- 		reg = <0x8d000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2d: port@ad000 {
- 		cell-index = <0x2d>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
- 		reg = <0xad000 0x1000>;
-+		fsl,qman-channel-id = <0x807>;
- 	};
- 
- 	ethernet@ea000 {
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
-@@ -0,0 +1,47 @@
-+/*
-+ * QorIQ FMan v3 OH ports device tree
-+ *
-+ * Copyright 2012-2015 Freescale Semiconductor Inc.
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+ */
-+
-+fman@1a00000 {
-+
-+	fman0_oh1: port@82000 {
-+		cell-index = <0>;
-+		compatible = "fsl,fman-port-oh";
-+		reg = <0x82000 0x1000>;
-+	};
-+
-+	fman0_oh2: port@83000 {
-+		cell-index = <1>;
-+		compatible = "fsl,fman-port-oh";
-+		reg = <0x83000 0x1000>;
-+	};
-+
-+	fman0_oh3: port@84000 {
-+		cell-index = <2>;
-+		compatible = "fsl,fman-port-oh";
-+		reg = <0x84000 0x1000>;
-+	};
-+
-+	fman0_oh4: port@85000 {
-+		cell-index = <3>;
-+		compatible = "fsl,fman-port-oh";
-+		reg = <0x85000 0x1000>;
-+	};
-+
-+	fman0_oh5: port@86000 {
-+		cell-index = <4>;
-+		compatible = "fsl,fman-port-oh";
-+		reg = <0x86000 0x1000>;
-+	};
-+
-+	fman0_oh6: port@87000 {
-+		cell-index = <5>;
-+		compatible = "fsl,fman-port-oh";
-+		reg = <0x87000 0x1000>;
-+	};
-+
-+};
---- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
-@@ -1,9 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ FMan v3 device tree
-  *
-  * Copyright 2012-2015 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- fman0: fman@1a00000 {
-@@ -19,45 +19,95 @@ fman0: fman@1a00000 {
- 	clock-names = "fmanclk";
- 	fsl,qman-channel-range = <0x800 0x10>;
- 
-+	cc {
-+		compatible = "fsl,fman-cc";
-+	};
-+
- 	muram@0 {
- 		compatible = "fsl,fman-muram";
- 		reg = <0x0 0x60000>;
- 	};
- 
-+	bmi@80000 {
-+		compatible = "fsl,fman-bmi";
-+		reg = <0x80000 0x400>;
-+	};
-+
-+	qmi@80400 {
-+		compatible = "fsl,fman-qmi";
-+		reg = <0x80400 0x400>;
-+	};
-+
- 	fman0_oh_0x2: port@82000 {
- 		cell-index = <0x2>;
- 		compatible = "fsl,fman-v3-port-oh";
- 		reg = <0x82000 0x1000>;
-+		fsl,qman-channel-id = <0x809>;
- 	};
- 
- 	fman0_oh_0x3: port@83000 {
- 		cell-index = <0x3>;
- 		compatible = "fsl,fman-v3-port-oh";
- 		reg = <0x83000 0x1000>;
-+		fsl,qman-channel-id = <0x80a>;
- 	};
- 
- 	fman0_oh_0x4: port@84000 {
- 		cell-index = <0x4>;
- 		compatible = "fsl,fman-v3-port-oh";
- 		reg = <0x84000 0x1000>;
-+		fsl,qman-channel-id = <0x80b>;
- 	};
- 
- 	fman0_oh_0x5: port@85000 {
- 		cell-index = <0x5>;
- 		compatible = "fsl,fman-v3-port-oh";
- 		reg = <0x85000 0x1000>;
-+		fsl,qman-channel-id = <0x80c>;
- 	};
- 
- 	fman0_oh_0x6: port@86000 {
- 		cell-index = <0x6>;
- 		compatible = "fsl,fman-v3-port-oh";
- 		reg = <0x86000 0x1000>;
-+		fsl,qman-channel-id = <0x80d>;
- 	};
- 
- 	fman0_oh_0x7: port@87000 {
- 		cell-index = <0x7>;
- 		compatible = "fsl,fman-v3-port-oh";
- 		reg = <0x87000 0x1000>;
-+		fsl,qman-channel-id = <0x80e>;
-+	};
-+
-+	policer@c0000 {
-+		compatible = "fsl,fman-policer";
-+		reg = <0xc0000 0x1000>;
-+	};
-+
-+	keygen@c1000 {
-+		compatible = "fsl,fman-keygen";
-+		reg = <0xc1000 0x1000>;
-+	};
-+
-+	dma@c2000 {
-+		compatible = "fsl,fman-dma";
-+		reg = <0xc2000 0x1000>;
-+	};
-+
-+	fpm@c3000 {
-+		compatible = "fsl,fman-fpm";
-+		reg = <0xc3000 0x1000>;
-+	};
-+
-+	parser@c7000 {
-+		compatible = "fsl,fman-parser";
-+		reg = <0xc7000 0x1000>;
-+	};
-+
-+	vsps@dc000 {
-+		compatible = "fsl,fman-vsps";
-+		reg = <0xdc000 0x1000>;
- 	};
- 
- 	mdio0: mdio@fc000 {
-@@ -75,7 +125,7 @@ fman0: fman@1a00000 {
- 	};
- 
- 	ptp_timer0: ptp-timer@fe000 {
--		compatible = "fsl,fman-ptp-timer";
-+		compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
- 		reg = <0xfe000 0x1000>;
- 	};
- };
---- /dev/null
-+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
-@@ -0,0 +1,38 @@
-+/*
-+ * QorIQ QMan SDK Portals device tree nodes
-+ *
-+ * Copyright 2011-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+ */
-+
-+&qportals {
-+	qman-fqids@0 {
-+		compatible = "fsl,fqid-range";
-+		fsl,fqid-range = <256 256>;
-+	};
-+
-+	qman-fqids@1 {
-+		compatible = "fsl,fqid-range";
-+		fsl,fqid-range = <32768 32768>;
-+	};
-+
-+	qman-pools@0 {
-+		compatible = "fsl,pool-channel-range";
-+		fsl,pool-channel-range = <0x401 0xf>;
-+	};
-+
-+	qman-cgrids@0 {
-+		compatible = "fsl,cgrid-range";
-+		fsl,cgrid-range = <0 256>;
-+	};
-+
-+	qman-ceetm@0 {
-+		compatible = "fsl,qman-ceetm";
-+		fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
-+		fsl,ceetm-sp-range = <0 16>;
-+		fsl,ceetm-lni-range = <0 8>;
-+		fsl,ceetm-channel-range = <0 32>;
-+	};
-+};
---- a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
-+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
-@@ -1,9 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * QorIQ QMan Portals device tree
-  *
-  * Copyright 2011-2016 Freescale Semiconductor Inc.
-  *
-- * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-  */
- 
- &qportals {
-@@ -77,4 +77,11 @@
- 		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- 		cell-index = <8>;
- 	};
-+
-+	qportal9: qman-portal@90000 {
-+		compatible = "fsl,qman-portal";
-+		reg = <0x90000 0x4000>, <0x4090000 0x4000>;
-+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
-+		cell-index = <9>;
-+	};
- };
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-10g-0.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x10: port@90000 {
- 		cell-index = <0x10>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx";
- 		reg = <0x90000 0x1000>;
- 	};
- 
- 	fman0_tx_0x30: port@b0000 {
- 		cell-index = <0x30>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx";
- 		reg = <0xb0000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-0.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x08: port@88000 {
- 		cell-index = <0x8>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x88000 0x1000>;
- 	};
- 
- 	fman0_tx_0x28: port@a8000 {
- 		cell-index = <0x28>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xa8000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-1.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x09: port@89000 {
- 		cell-index = <0x9>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x89000 0x1000>;
- 	};
- 
- 	fman0_tx_0x29: port@a9000 {
- 		cell-index = <0x29>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xa9000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-2.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x0a: port@8a000 {
- 		cell-index = <0xa>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8a000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2a: port@aa000 {
- 		cell-index = <0x2a>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xaa000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-3.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x0b: port@8b000 {
- 		cell-index = <0xb>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8b000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2b: port@ab000 {
- 		cell-index = <0x2b>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xab000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-0-1g-4.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x0c: port@8c000 {
- 		cell-index = <0xc>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8c000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2c: port@ac000 {
- 		cell-index = <0x2c>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xac000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-10g-0.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x10: port@90000 {
- 		cell-index = <0x10>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-10g-rx";
- 		reg = <0x90000 0x1000>;
- 	};
- 
- 	fman1_tx_0x30: port@b0000 {
- 		cell-index = <0x30>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-10g-tx";
- 		reg = <0xb0000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-0.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x08: port@88000 {
- 		cell-index = <0x8>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x88000 0x1000>;
- 	};
- 
- 	fman1_tx_0x28: port@a8000 {
- 		cell-index = <0x28>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xa8000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-1.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x09: port@89000 {
- 		cell-index = <0x9>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x89000 0x1000>;
- 	};
- 
- 	fman1_tx_0x29: port@a9000 {
- 		cell-index = <0x29>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xa9000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-2.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x0a: port@8a000 {
- 		cell-index = <0xa>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8a000 0x1000>;
- 	};
- 
- 	fman1_tx_0x2a: port@aa000 {
- 		cell-index = <0x2a>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xaa000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-3.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x0b: port@8b000 {
- 		cell-index = <0xb>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8b000 0x1000>;
- 	};
- 
- 	fman1_tx_0x2b: port@ab000 {
- 		cell-index = <0x2b>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xab000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman-1-1g-4.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x0c: port@8c000 {
- 		cell-index = <0xc>;
--		compatible = "fsl,fman-v2-port-rx";
-+		compatible = "fsl,fman-v2-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8c000 0x1000>;
- 	};
- 
- 	fman1_tx_0x2c: port@ac000 {
- 		cell-index = <0x2c>;
--		compatible = "fsl,fman-v2-port-tx";
-+		compatible = "fsl,fman-v2-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xac000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
-@@ -35,7 +35,7 @@
- fman@400000 {
- 	fman0_rx_0x08: port@88000 {
- 		cell-index = <0x8>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx";
- 		reg = <0x88000 0x1000>;
- 		fsl,fman-10g-port;
- 		fsl,fman-best-effort-port;
-@@ -43,7 +43,7 @@ fman@400000 {
- 
- 	fman0_tx_0x28: port@a8000 {
- 		cell-index = <0x28>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx";
- 		reg = <0xa8000 0x1000>;
- 		fsl,fman-10g-port;
- 		fsl,fman-best-effort-port;
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
-@@ -35,14 +35,14 @@
- fman@400000 {
- 	fman0_rx_0x10: port@90000 {
- 		cell-index = <0x10>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
- 		reg = <0x90000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
- 
- 	fman0_tx_0x30: port@b0000 {
- 		cell-index = <0x30>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
- 		reg = <0xb0000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
-@@ -35,7 +35,7 @@
- fman@400000 {
- 	fman0_rx_0x09: port@89000 {
- 		cell-index = <0x9>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx";
- 		reg = <0x89000 0x1000>;
- 		fsl,fman-10g-port;
- 		fsl,fman-best-effort-port;
-@@ -43,7 +43,7 @@ fman@400000 {
- 
- 	fman0_tx_0x29: port@a9000 {
- 		cell-index = <0x29>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx";
- 		reg = <0xa9000 0x1000>;
- 		fsl,fman-10g-port;
- 		fsl,fman-best-effort-port;
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
-@@ -35,14 +35,14 @@
- fman@400000 {
- 	fman0_rx_0x11: port@91000 {
- 		cell-index = <0x11>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
- 		reg = <0x91000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
- 
- 	fman0_tx_0x31: port@b1000 {
- 		cell-index = <0x31>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
- 		reg = <0xb1000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x08: port@88000 {
- 		cell-index = <0x8>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x88000 0x1000>;
- 	};
- 
- 	fman0_tx_0x28: port@a8000 {
- 		cell-index = <0x28>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xa8000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x09: port@89000 {
- 		cell-index = <0x9>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x89000 0x1000>;
- 	};
- 
- 	fman0_tx_0x29: port@a9000 {
- 		cell-index = <0x29>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xa9000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x0a: port@8a000 {
- 		cell-index = <0xa>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8a000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2a: port@aa000 {
- 		cell-index = <0x2a>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xaa000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x0b: port@8b000 {
- 		cell-index = <0xb>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8b000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2b: port@ab000 {
- 		cell-index = <0x2b>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xab000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x0c: port@8c000 {
- 		cell-index = <0xc>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8c000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2c: port@ac000 {
- 		cell-index = <0x2c>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xac000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
-@@ -35,13 +35,13 @@
- fman@400000 {
- 	fman0_rx_0x0d: port@8d000 {
- 		cell-index = <0xd>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8d000 0x1000>;
- 	};
- 
- 	fman0_tx_0x2d: port@ad000 {
- 		cell-index = <0x2d>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xad000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
-@@ -35,14 +35,14 @@
- fman@500000 {
- 	fman1_rx_0x10: port@90000 {
- 		cell-index = <0x10>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx";
- 		reg = <0x90000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
- 
- 	fman1_tx_0x30: port@b0000 {
- 		cell-index = <0x30>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx";
- 		reg = <0xb0000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
-@@ -35,14 +35,14 @@
- fman@500000 {
- 	fman1_rx_0x11: port@91000 {
- 		cell-index = <0x11>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-10g-rx";
- 		reg = <0x91000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
- 
- 	fman1_tx_0x31: port@b1000 {
- 		cell-index = <0x31>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-10g-tx";
- 		reg = <0xb1000 0x1000>;
- 		fsl,fman-10g-port;
- 	};
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x08: port@88000 {
- 		cell-index = <0x8>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x88000 0x1000>;
- 	};
- 
- 	fman1_tx_0x28: port@a8000 {
- 		cell-index = <0x28>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xa8000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x09: port@89000 {
- 		cell-index = <0x9>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x89000 0x1000>;
- 	};
- 
- 	fman1_tx_0x29: port@a9000 {
- 		cell-index = <0x29>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xa9000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x0a: port@8a000 {
- 		cell-index = <0xa>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8a000 0x1000>;
- 	};
- 
- 	fman1_tx_0x2a: port@aa000 {
- 		cell-index = <0x2a>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xaa000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x0b: port@8b000 {
- 		cell-index = <0xb>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8b000 0x1000>;
- 	};
- 
- 	fman1_tx_0x2b: port@ab000 {
- 		cell-index = <0x2b>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xab000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x0c: port@8c000 {
- 		cell-index = <0xc>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8c000 0x1000>;
- 	};
- 
- 	fman1_tx_0x2c: port@ac000 {
- 		cell-index = <0x2c>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xac000 0x1000>;
- 	};
- 
---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
-+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
-@@ -35,13 +35,13 @@
- fman@500000 {
- 	fman1_rx_0x0d: port@8d000 {
- 		cell-index = <0xd>;
--		compatible = "fsl,fman-v3-port-rx";
-+		compatible = "fsl,fman-v3-port-rx","fsl,fman-port-1g-rx";
- 		reg = <0x8d000 0x1000>;
- 	};
- 
- 	fman1_tx_0x2d: port@ad000 {
- 		cell-index = <0x2d>;
--		compatible = "fsl,fman-v3-port-tx";
-+		compatible = "fsl,fman-v3-port-tx","fsl,fman-port-1g-tx";
- 		reg = <0xad000 0x1000>;
- 	};
- 
diff --git a/target/linux/layerscape/patches-4.14/304-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch b/target/linux/layerscape/patches-4.14/304-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch
deleted file mode 100644
index 37ddf88e5..000000000
--- a/target/linux/layerscape/patches-4.14/304-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch
+++ /dev/null
@@ -1,289 +0,0 @@
-From bb1a53f1bcb3f4c5983955a1d419c0e4e2531043 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 26 Oct 2018 16:00:37 +0800
-Subject: [PATCH 06/40] arm: dts: ls1021a: Add LS1021A-IOT board support
-
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- arch/arm/boot/dts/Makefile        |   3 +-
- arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++
- 2 files changed, 264 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -496,7 +496,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
- 	imx7s-warp.dtb
- dtb-$(CONFIG_SOC_LS1021A) += \
- 	ls1021a-qds.dtb \
--	ls1021a-twr.dtb
-+	ls1021a-twr.dtb \
-+	ls1021a-iot.dtb
- dtb-$(CONFIG_SOC_VF610) += \
- 	vf500-colibri-eval-v3.dtb \
- 	vf610-colibri-eval-v3.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/ls1021a-iot.dts
-@@ -0,0 +1,262 @@
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+/dts-v1/;
-+#include "ls1021a.dtsi"
-+
-+/ {
-+	model = "LS1021A IOT Board";
-+
-+	sys_mclk: clock-mclk {
-+		compatible = "fixed-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <24576000>;
-+	};
-+
-+	regulators {
-+		compatible = "simple-bus";
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		reg_3p3v: regulator@0 {
-+			compatible = "regulator-fixed";
-+			reg = <0>;
-+			regulator-name = "3P3V";
-+			regulator-min-microvolt = <3300000>;
-+			regulator-max-microvolt = <3300000>;
-+			regulator-always-on;
-+		};
-+
-+		reg_2p5v: regulator@1 {
-+			compatible = "regulator-fixed";
-+			reg = <1>;
-+			regulator-name = "2P5V";
-+			regulator-min-microvolt = <2500000>;
-+			regulator-max-microvolt = <2500000>;
-+			regulator-always-on;
-+		};
-+	};
-+
-+	sound {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,format = "i2s";
-+		simple-audio-card,widgets =
-+			"Microphone", "Microphone Jack",
-+			"Headphone", "Headphone Jack",
-+			"Speaker", "Speaker Ext",
-+			"Line", "Line In Jack";
-+		simple-audio-card,routing =
-+			"MIC_IN", "Microphone Jack",
-+			"Microphone Jack", "Mic Bias",
-+			"LINE_IN", "Line In Jack",
-+			"Headphone Jack", "HP_OUT",
-+			"Speaker Ext", "LINE_OUT";
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&sai2>;
-+			frame-master;
-+			bitclock-master;
-+		};
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&codec>;
-+			frame-master;
-+			bitclock-master;
-+		};
-+	};
-+
-+	firmware {
-+		optee {
-+			compatible = "linaro,optee-tz";
-+			method = "smc";
-+			};
-+		};
-+};
-+
-+&enet0 {
-+	tbi-handle = <&tbi1>;
-+	phy-handle = <&phy1>;
-+	phy-connection-type = "sgmii";
-+	status = "okay";
-+};
-+
-+&enet1 {
-+	tbi-handle = <&tbi1>;
-+	phy-handle = <&phy3>;
-+	phy-connection-type = "sgmii";
-+	status = "okay";
-+};
-+
-+&enet2 {
-+	fixed-link = <0 1 1000 0 0>;
-+	phy-connection-type = "rgmii-id";
-+	status = "okay";
-+};
-+
-+&can0{
-+	status = "disabled";
-+};
-+
-+&can1{
-+	status = "disabled";
-+};
-+
-+&can2{
-+	status = "disabled";
-+};
-+
-+&can3{
-+	status = "okay";
-+};
-+
-+&esdhc{
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	max1239@35 {
-+		compatible = "maxim,max1239";
-+		reg = <0x35>;
-+		#io-channel-cells = <1>;
-+	};
-+
-+	codec: sgtl5000@2a {
-+               #sound-dai-cells=<0x0>;
-+		compatible = "fsl,sgtl5000";
-+		reg = <0x2a>;
-+		VDDA-supply = <&reg_3p3v>;
-+		VDDIO-supply = <&reg_2p5v>;
-+		clocks = <&sys_mclk 1>;
-+	};
-+
-+	pca9555: pca9555@23 {
-+		compatible = "nxp,pca9555";
-+		/*pinctrl-names = "default";*/
-+		/*interrupt-parent = <&gpio2>;
-+		interrupts = <19 0x2>;*/
-+		gpio-controller;
-+		#gpio-cells = <2>;
-+		interrupt-controller;
-+		#interrupt-cells = <2>;
-+		reg = <0x23>;
-+	};
-+
-+	ina220@44 {
-+		compatible = "ti,ina220";
-+		reg = <0x44>;
-+		shunt-resistor = <1000>;
-+	};
-+
-+	ina220@45 {
-+		compatible = "ti,ina220";
-+		reg = <0x45>;
-+		shunt-resistor = <1000>;
-+	};
-+
-+	lm75b@48 {
-+                compatible = "nxp,lm75a";
-+                reg = <0x48>;
-+        };
-+
-+	adt7461a@4c {
-+		compatible = "adt7461a";
-+		reg = <0x4c>;
-+	};
-+
-+	hdmi: sii9022a@39 {
-+		compatible = "fsl,sii902x";
-+		reg = <0x39>;
-+		interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
-+	};
-+};
-+
-+&i2c1 {
-+	status = "disabled";
-+};
-+
-+&ifc {
-+	status = "disabled";
-+};
-+
-+&lpuart0 {
-+	status = "okay";
-+};
-+
-+&mdio0 {
-+	phy0: ethernet-phy@0 {
-+		reg = <0x0>;
-+	};
-+	phy1: ethernet-phy@1 {
-+		reg = <0x1>;
-+	};
-+	phy2: ethernet-phy@2 {
-+		reg = <0x2>;
-+	};
-+	phy3: ethernet-phy@3 {
-+		reg = <0x3>;
-+	};
-+	tbi1: tbi-phy@1f {
-+		reg = <0x1f>;
-+		device_type = "tbi-phy";
-+	};
-+};
-+
-+&qspi {
-+	num-cs = <2>;
-+	status = "okay";
-+
-+	qflash0: s25fl128s@0 {
-+		compatible = "spansion,s25fl129p1";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
-+};
-+
-+&sai2 {
-+	status = "okay";
-+};
-+
-+&uart0 {
-+	status = "okay";
-+};
-+
-+&uart1 {
-+	status = "okay";
-+};
-+
-+&dcu {
-+	display = <&display>;
-+	status = "okay";
-+
-+	display: display@0 {
-+		bits-per-pixel = <24>;
-+
-+		display-timings {
-+			native-mode = <&timing0>;
-+
-+			timing0: mode0 {
-+				clock-frequency = <25000000>;
-+				hactive = <640>;
-+				vactive = <480>;
-+				hback-porch = <80>;
-+				hfront-porch = <80>;
-+				vback-porch = <16>;
-+				vfront-porch = <16>;
-+				hsync-len = <12>;
-+				vsync-len = <2>;
-+				hsync-active = <1>;
-+				vsync-active = <1>;
-+			};
-+		};
-+	};
-+};
diff --git a/target/linux/layerscape/patches-4.14/701-dpaa2-dpio-support-layerscape.patch b/target/linux/layerscape/patches-4.14/701-dpaa2-dpio-support-layerscape.patch
deleted file mode 100644
index 34514caa0..000000000
--- a/target/linux/layerscape/patches-4.14/701-dpaa2-dpio-support-layerscape.patch
+++ /dev/null
@@ -1,2415 +0,0 @@
-From ede8d823f0e1b2c5e14cbac13839b818ed1c18cf Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:10 +0800
-Subject: [PATCH 07/40] apaa2-dpio:support layerscape
-This is an integrated patch of dpaa2-dpio for layerscape
-
-Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
-Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
-Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com>
-Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
-Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
-Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
-Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/staging/fsl-mc/Kconfig                |   1 +
- drivers/staging/fsl-mc/Makefile               |   1 +
- drivers/staging/fsl-mc/bus/Kconfig            |   5 +-
- drivers/staging/fsl-mc/bus/Makefile           |   3 +-
- drivers/staging/fsl-mc/bus/dpbp-cmd.h         |  28 +-
- drivers/staging/fsl-mc/bus/dpbp.c             |  28 +-
- drivers/staging/fsl-mc/bus/dpcon-cmd.h        |  28 +-
- drivers/staging/fsl-mc/bus/dpcon.c            |  32 +-
- drivers/staging/fsl-mc/bus/dpio/Makefile      |   3 +-
- drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h    |  29 +-
- drivers/staging/fsl-mc/bus/dpio/dpio-driver.c |  53 ++--
- .../staging/fsl-mc/bus/dpio/dpio-service.c    | 258 +++++++++++++---
- drivers/staging/fsl-mc/bus/dpio/dpio.c        |  51 ++--
- drivers/staging/fsl-mc/bus/dpio/dpio.h        |  32 +-
- .../staging/fsl-mc/bus/dpio/qbman-portal.c    | 217 ++++++++++---
- .../staging/fsl-mc/bus/dpio/qbman-portal.h    | 112 ++++---
- drivers/staging/fsl-mc/bus/dpmcp.c            |  28 +-
- drivers/staging/fsl-mc/bus/dprc-driver.c      |   4 +-
- drivers/staging/fsl-mc/bus/dprc.c             |  28 +-
- drivers/staging/fsl-mc/bus/fsl-mc-allocator.c |   4 +-
- drivers/staging/fsl-mc/bus/fsl-mc-bus.c       |   4 +-
- drivers/staging/fsl-mc/bus/fsl-mc-msi.c       |   4 +-
- drivers/staging/fsl-mc/bus/fsl-mc-private.h   |   4 +-
- .../fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c    |   4 +-
- drivers/staging/fsl-mc/bus/mc-io.c            |  28 +-
- drivers/staging/fsl-mc/bus/mc-sys.c           |  28 +-
- drivers/staging/fsl-mc/include/dpaa2-fd.h     | 288 ++++++++++++++++--
- drivers/staging/fsl-mc/include/dpaa2-global.h |  27 +-
- drivers/staging/fsl-mc/include/dpaa2-io.h     |  97 ++++--
- drivers/staging/fsl-mc/include/dpbp.h         |  29 +-
- drivers/staging/fsl-mc/include/dpcon.h        |  32 +-
- drivers/staging/fsl-mc/include/dpopr.h        | 110 +++++++
- drivers/staging/fsl-mc/include/mc.h           |   4 +-
- 33 files changed, 970 insertions(+), 634 deletions(-)
- create mode 100644 drivers/staging/fsl-mc/include/dpopr.h
-
---- a/drivers/staging/fsl-mc/Kconfig
-+++ b/drivers/staging/fsl-mc/Kconfig
-@@ -1 +1,2 @@
-+# SPDX-License-Identifier: GPL-2.0
- source "drivers/staging/fsl-mc/bus/Kconfig"
---- a/drivers/staging/fsl-mc/Makefile
-+++ b/drivers/staging/fsl-mc/Makefile
-@@ -1,2 +1,3 @@
-+# SPDX-License-Identifier: GPL-2.0
- # Freescale Management Complex (MC) bus drivers
- obj-$(CONFIG_FSL_MC_BUS)	+= bus/
---- a/drivers/staging/fsl-mc/bus/Kconfig
-+++ b/drivers/staging/fsl-mc/bus/Kconfig
-@@ -1,10 +1,9 @@
-+# SPDX-License-Identifier: GPL-2.0
- #
- # DPAA2 fsl-mc bus
- #
- # Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
- #
--# This file is released under the GPLv2
--#
- 
- config FSL_MC_BUS
- 	bool "QorIQ DPAA2 fsl-mc bus driver"
-@@ -18,7 +17,7 @@ config FSL_MC_BUS
- 
- config FSL_MC_DPIO
-         tristate "QorIQ DPAA2 DPIO driver"
--        depends on FSL_MC_BUS && ARCH_LAYERSCAPE
-+        depends on FSL_MC_BUS
-         help
- 	  Driver for the DPAA2 DPIO object.  A DPIO provides queue and
- 	  buffer management facilities for software to interact with
---- a/drivers/staging/fsl-mc/bus/Makefile
-+++ b/drivers/staging/fsl-mc/bus/Makefile
-@@ -1,10 +1,9 @@
-+# SPDX-License-Identifier: GPL-2.0
- #
- # Freescale Management Complex (MC) bus drivers
- #
- # Copyright (C) 2014 Freescale Semiconductor, Inc.
- #
--# This file is released under the GPLv2
--#
- obj-$(CONFIG_FSL_MC_BUS) += mc-bus-driver.o
- 
- mc-bus-driver-objs := fsl-mc-bus.o \
---- a/drivers/staging/fsl-mc/bus/dpbp-cmd.h
-+++ b/drivers/staging/fsl-mc/bus/dpbp-cmd.h
-@@ -1,33 +1,7 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef _FSL_DPBP_CMD_H
- #define _FSL_DPBP_CMD_H
---- a/drivers/staging/fsl-mc/bus/dpbp.c
-+++ b/drivers/staging/fsl-mc/bus/dpbp.c
-@@ -1,33 +1,7 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #include <linux/kernel.h>
- #include "../include/mc.h"
---- a/drivers/staging/fsl-mc/bus/dpcon-cmd.h
-+++ b/drivers/staging/fsl-mc/bus/dpcon-cmd.h
-@@ -1,33 +1,7 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef _FSL_DPCON_CMD_H
- #define _FSL_DPCON_CMD_H
---- a/drivers/staging/fsl-mc/bus/dpcon.c
-+++ b/drivers/staging/fsl-mc/bus/dpcon.c
-@@ -1,33 +1,7 @@
--/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #include <linux/kernel.h>
- #include "../include/mc.h"
---- a/drivers/staging/fsl-mc/bus/dpio/Makefile
-+++ b/drivers/staging/fsl-mc/bus/dpio/Makefile
-@@ -1,9 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0
- #
- # QorIQ DPAA2 DPIO driver
- #
- 
--subdir-ccflags-y := -Werror
--
- obj-$(CONFIG_FSL_MC_DPIO) += fsl-mc-dpio.o
- 
- fsl-mc-dpio-objs := dpio.o qbman-portal.o dpio-service.o dpio-driver.o
---- a/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
-+++ b/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
-@@ -1,34 +1,8 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef _FSL_DPIO_CMD_H
- #define _FSL_DPIO_CMD_H
-@@ -51,6 +25,7 @@
- #define DPIO_CMDID_ENABLE				DPIO_CMD(0x002)
- #define DPIO_CMDID_DISABLE				DPIO_CMD(0x003)
- #define DPIO_CMDID_GET_ATTR				DPIO_CMD(0x004)
-+#define DPIO_CMDID_RESET				DPIO_CMD(0x005)
- 
- struct dpio_cmd_open {
- 	__le32 dpio_id;
---- a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
-+++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
-@@ -1,33 +1,8 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright 2014-2016 Freescale Semiconductor Inc.
-- * Copyright NXP 2016
-+ * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *	 notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *	 notice, this list of conditions and the following disclaimer in the
-- *	 documentation and/or other materials provided with the distribution.
-- *     * Neither the name of Freescale Semiconductor nor the
-- *	 names of its contributors may be used to endorse or promote products
-- *	 derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- 
- #include <linux/types.h>
-@@ -114,6 +89,7 @@ static int dpaa2_dpio_probe(struct fsl_m
- 	int err = -ENOMEM;
- 	struct device *dev = &dpio_dev->dev;
- 	static int next_cpu = -1;
-+	int possible_next_cpu;
- 
- 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- 	if (!priv)
-@@ -135,6 +111,12 @@ static int dpaa2_dpio_probe(struct fsl_m
- 		goto err_open;
- 	}
- 
-+	err = dpio_reset(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
-+	if (err) {
-+		dev_err(dev, "dpio_reset() failed\n");
-+		goto err_reset;
-+	}
-+
- 	err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
- 				  &dpio_attrs);
- 	if (err) {
-@@ -156,23 +138,23 @@ static int dpaa2_dpio_probe(struct fsl_m
- 
- 	/* get the cpu to use for the affinity hint */
- 	if (next_cpu == -1)
--		next_cpu = cpumask_first(cpu_online_mask);
-+		possible_next_cpu = cpumask_first(cpu_online_mask);
- 	else
--		next_cpu = cpumask_next(next_cpu, cpu_online_mask);
-+		possible_next_cpu = cpumask_next(next_cpu, cpu_online_mask);
- 
--	if (!cpu_possible(next_cpu)) {
-+	if (possible_next_cpu >= nr_cpu_ids) {
- 		dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
- 		err = -ERANGE;
- 		goto err_allocate_irqs;
- 	}
--	desc.cpu = next_cpu;
-+	desc.cpu = next_cpu = possible_next_cpu;
- 
- 	/*
--	 * Set the CENA regs to be the cache inhibited area of the portal to
--	 * avoid coherency issues if a user migrates to another core.
-+	 * Set the CENA regs to be the cache enabled area of the portal to
-+	 * achieve the best performance.
- 	 */
--	desc.regs_cena = ioremap_wc(dpio_dev->regions[1].start,
--		resource_size(&dpio_dev->regions[1]));
-+	desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start,
-+		resource_size(&dpio_dev->regions[0]));
- 	desc.regs_cinh = ioremap(dpio_dev->regions[1].start,
- 		resource_size(&dpio_dev->regions[1]));
- 
-@@ -207,6 +189,7 @@ err_register_dpio_irq:
- err_allocate_irqs:
- 	dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
- err_get_attr:
-+err_reset:
- 	dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
- err_open:
- 	fsl_mc_portal_free(dpio_dev->mc_io);
---- a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
-+++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
-@@ -1,33 +1,8 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright 2014-2016 Freescale Semiconductor Inc.
-  * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *	 notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *	 notice, this list of conditions and the following disclaimer in the
-- *	 documentation and/or other materials provided with the distribution.
-- *     * Neither the name of Freescale Semiconductor nor the
-- *	 names of its contributors may be used to endorse or promote products
-- *	 derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- #include <linux/types.h>
- #include "../../include/mc.h"
-@@ -43,7 +18,6 @@
- #include "qbman-portal.h"
- 
- struct dpaa2_io {
--	atomic_t refs;
- 	struct dpaa2_io_desc dpio_desc;
- 	struct qbman_swp_desc swp_desc;
- 	struct qbman_swp *swp;
-@@ -83,7 +57,7 @@ static inline struct dpaa2_io *service_s
- 	 * If cpu == -1, choose the current cpu, with no guarantees about
- 	 * potentially being migrated away.
- 	 */
--	if (unlikely(cpu < 0))
-+	if (cpu < 0)
- 		cpu = smp_processor_id();
- 
- 	/* If a specific cpu was requested, pick it up immediately */
-@@ -95,6 +69,10 @@ static inline struct dpaa2_io *service_s
- 	if (d)
- 		return d;
- 
-+	d = service_select_by_cpu(d, -1);
-+	if (d)
-+		return d;
-+
- 	spin_lock(&dpio_list_lock);
- 	d = list_entry(dpio_list.next, struct dpaa2_io, node);
- 	list_del(&d->node);
-@@ -105,6 +83,23 @@ static inline struct dpaa2_io *service_s
- }
- 
- /**
-+ * dpaa2_io_service_select() - return a dpaa2_io service affined to this cpu
-+ * @cpu: the cpu id
-+ *
-+ * Return the affine dpaa2_io service, or NULL if there is no service affined
-+ * to the specified cpu. If DPAA2_IO_ANY_CPU is used, return the next available
-+ * service.
-+ */
-+struct dpaa2_io *dpaa2_io_service_select(int cpu)
-+{
-+	if (cpu == DPAA2_IO_ANY_CPU)
-+		return service_select(NULL);
-+
-+	return service_select_by_cpu(NULL, cpu);
-+}
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_select);
-+
-+/**
-  * dpaa2_io_create() - create a dpaa2_io object.
-  * @desc: the dpaa2_io descriptor
-  *
-@@ -126,7 +121,6 @@ struct dpaa2_io *dpaa2_io_create(const s
- 		return NULL;
- 	}
- 
--	atomic_set(&obj->refs, 1);
- 	obj->dpio_desc = *desc;
- 	obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena;
- 	obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh;
-@@ -158,7 +152,6 @@ struct dpaa2_io *dpaa2_io_create(const s
- 
- 	return obj;
- }
--EXPORT_SYMBOL(dpaa2_io_create);
- 
- /**
-  * dpaa2_io_down() - release the dpaa2_io object.
-@@ -171,11 +164,8 @@ EXPORT_SYMBOL(dpaa2_io_create);
-  */
- void dpaa2_io_down(struct dpaa2_io *d)
- {
--	if (!atomic_dec_and_test(&d->refs))
--		return;
- 	kfree(d);
- }
--EXPORT_SYMBOL(dpaa2_io_down);
- 
- #define DPAA_POLL_MAX 32
- 
-@@ -206,7 +196,7 @@ irqreturn_t dpaa2_io_irq(struct dpaa2_io
- 			u64 q64;
- 
- 			q64 = qbman_result_SCN_ctx(dq);
--			ctx = (void *)q64;
-+			ctx = (void *)(uintptr_t)q64;
- 			ctx->cb(ctx);
- 		} else {
- 			pr_crit("fsl-mc-dpio: Unrecognised/ignored DQRR entry\n");
-@@ -222,7 +212,6 @@ done:
- 	qbman_swp_interrupt_set_inhibit(swp, 0);
- 	return IRQ_HANDLED;
- }
--EXPORT_SYMBOL(dpaa2_io_irq);
- 
- /**
-  * dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN
-@@ -252,7 +241,7 @@ int dpaa2_io_service_register(struct dpa
- 		return -ENODEV;
- 
- 	ctx->dpio_id = d->dpio_desc.dpio_id;
--	ctx->qman64 = (u64)ctx;
-+	ctx->qman64 = (u64)(uintptr_t)ctx;
- 	ctx->dpio_private = d;
- 	spin_lock_irqsave(&d->lock_notifications, irqflags);
- 	list_add(&ctx->node, &d->notifications);
-@@ -265,7 +254,7 @@ int dpaa2_io_service_register(struct dpa
- 							 ctx->qman64);
- 	return 0;
- }
--EXPORT_SYMBOL(dpaa2_io_service_register);
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_register);
- 
- /**
-  * dpaa2_io_service_deregister - The opposite of 'register'.
-@@ -288,7 +277,7 @@ void dpaa2_io_service_deregister(struct
- 	list_del(&ctx->node);
- 	spin_unlock_irqrestore(&d->lock_notifications, irqflags);
- }
--EXPORT_SYMBOL(dpaa2_io_service_deregister);
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_deregister);
- 
- /**
-  * dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service.
-@@ -322,7 +311,7 @@ int dpaa2_io_service_rearm(struct dpaa2_
- 
- 	return err;
- }
--EXPORT_SYMBOL(dpaa2_io_service_rearm);
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_rearm);
- 
- /**
-  * dpaa2_io_service_pull_fq() - pull dequeue functions from a fq.
-@@ -385,7 +374,7 @@ int dpaa2_io_service_pull_channel(struct
- 
- 	return err;
- }
--EXPORT_SYMBOL(dpaa2_io_service_pull_channel);
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_pull_channel);
- 
- /**
-  * dpaa2_io_service_enqueue_fq() - Enqueue a frame to a frame queue.
-@@ -441,7 +430,7 @@ int dpaa2_io_service_enqueue_qd(struct d
- 
- 	return qbman_swp_enqueue(d->swp, &ed, fd);
- }
--EXPORT_SYMBOL(dpaa2_io_service_enqueue_qd);
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_enqueue_qd);
- 
- /**
-  * dpaa2_io_service_release() - Release buffers to a buffer pool.
-@@ -453,7 +442,7 @@ EXPORT_SYMBOL(dpaa2_io_service_enqueue_q
-  * Return 0 for success, and negative error code for failure.
-  */
- int dpaa2_io_service_release(struct dpaa2_io *d,
--			     u32 bpid,
-+			     u16 bpid,
- 			     const u64 *buffers,
- 			     unsigned int num_buffers)
- {
-@@ -468,7 +457,7 @@ int dpaa2_io_service_release(struct dpaa
- 
- 	return qbman_swp_release(d->swp, &rd, buffers, num_buffers);
- }
--EXPORT_SYMBOL(dpaa2_io_service_release);
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_release);
- 
- /**
-  * dpaa2_io_service_acquire() - Acquire buffers from a buffer pool.
-@@ -482,7 +471,7 @@ EXPORT_SYMBOL(dpaa2_io_service_release);
-  * Eg. if the buffer pool is empty, this will return zero.
-  */
- int dpaa2_io_service_acquire(struct dpaa2_io *d,
--			     u32 bpid,
-+			     u16 bpid,
- 			     u64 *buffers,
- 			     unsigned int num_buffers)
- {
-@@ -499,7 +488,7 @@ int dpaa2_io_service_acquire(struct dpaa
- 
- 	return err;
- }
--EXPORT_SYMBOL(dpaa2_io_service_acquire);
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_acquire);
- 
- /*
-  * 'Stores' are reusable memory blocks for holding dequeue results, and to
-@@ -553,7 +542,7 @@ struct dpaa2_io_store *dpaa2_io_store_cr
- 
- 	return ret;
- }
--EXPORT_SYMBOL(dpaa2_io_store_create);
-+EXPORT_SYMBOL_GPL(dpaa2_io_store_create);
- 
- /**
-  * dpaa2_io_store_destroy() - Frees the dma memory storage for dequeue
-@@ -567,7 +556,7 @@ void dpaa2_io_store_destroy(struct dpaa2
- 	kfree(s->alloced_addr);
- 	kfree(s);
- }
--EXPORT_SYMBOL(dpaa2_io_store_destroy);
-+EXPORT_SYMBOL_GPL(dpaa2_io_store_destroy);
- 
- /**
-  * dpaa2_io_store_next() - Determine when the next dequeue result is available.
-@@ -615,4 +604,177 @@ struct dpaa2_dq *dpaa2_io_store_next(str
- 
- 	return ret;
- }
--EXPORT_SYMBOL(dpaa2_io_store_next);
-+EXPORT_SYMBOL_GPL(dpaa2_io_store_next);
-+
-+/**
-+ * dpaa2_io_query_fq_count() - Get the frame and byte count for a given fq.
-+ * @d: the given DPIO object.
-+ * @fqid: the id of frame queue to be queried.
-+ * @fcnt: the queried frame count.
-+ * @bcnt: the queried byte count.
-+ *
-+ * Knowing the FQ count at run-time can be useful in debugging situations.
-+ * The instantaneous frame- and byte-count are hereby returned.
-+ *
-+ * Return 0 for a successful query, and negative error code if query fails.
-+ */
-+int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid,
-+			    u32 *fcnt, u32 *bcnt)
-+{
-+	struct qbman_fq_query_np_rslt state;
-+	struct qbman_swp *swp;
-+	unsigned long irqflags;
-+	int ret;
-+
-+	d = service_select(d);
-+	if (!d)
-+		return -ENODEV;
-+
-+	swp = d->swp;
-+	spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
-+	ret = qbman_fq_query_state(swp, fqid, &state);
-+	spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
-+	if (ret)
-+		return ret;
-+	*fcnt = qbman_fq_state_frame_count(&state);
-+	*bcnt = qbman_fq_state_byte_count(&state);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(dpaa2_io_query_fq_count);
-+
-+/**
-+ * dpaa2_io_query_bp_count() - Query the number of buffers currently in a
-+ * buffer pool.
-+ * @d: the given DPIO object.
-+ * @bpid: the index of buffer pool to be queried.
-+ * @num: the queried number of buffers in the buffer pool.
-+ *
-+ * Return 0 for a successful query, and negative error code if query fails.
-+ */
-+int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid, u32 *num)
-+{
-+	struct qbman_bp_query_rslt state;
-+	struct qbman_swp *swp;
-+	unsigned long irqflags;
-+	int ret;
-+
-+	d = service_select(d);
-+	if (!d)
-+		return -ENODEV;
-+
-+	swp = d->swp;
-+	spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
-+	ret = qbman_bp_query(swp, bpid, &state);
-+	spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
-+	if (ret)
-+		return ret;
-+	*num = qbman_bp_info_num_free_bufs(&state);
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(dpaa2_io_query_bp_count);
-+
-+/**
-+ * dpaa2_io_service_enqueue_orp_fq() - Enqueue a frame to a frame queue with
-+ * order restoration
-+ * @d: the given DPIO service.
-+ * @fqid: the given frame queue id.
-+ * @fd: the frame descriptor which is enqueued.
-+ * @orpid: the order restoration point ID
-+ * @seqnum: the order sequence number
-+ * @last: must be set for the final frame if seqnum is shared (spilt frame)
-+ *
-+ * Performs an enqueue to a frame queue using the specified order restoration
-+ * point. The QMan device will ensure the order of frames placed on the
-+ * queue will be ordered as per the sequence number.
-+ *
-+ * In the case a frame is split it is possible to enqueue using the same
-+ * sequence number more than once. The final frame in a shared sequence number
-+ * most be indicated by setting last = 1. For non shared sequence numbers
-+ * last = 1 must always be set.
-+ *
-+ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
-+ * or -ENODEV if there is no dpio service.
-+ */
-+int dpaa2_io_service_enqueue_orp_fq(struct dpaa2_io *d, u32 fqid,
-+				    const struct dpaa2_fd *fd, u16 orpid,
-+				    u16 seqnum, int last)
-+{
-+	struct qbman_eq_desc ed;
-+
-+	d = service_select(d);
-+	if (!d)
-+		return -ENODEV;
-+	qbman_eq_desc_clear(&ed);
-+	qbman_eq_desc_set_orp(&ed, 0, orpid, seqnum, !last);
-+	qbman_eq_desc_set_fq(&ed, fqid);
-+	return qbman_swp_enqueue(d->swp, &ed, fd);
-+}
-+EXPORT_SYMBOL(dpaa2_io_service_enqueue_orp_fq);
-+
-+/**
-+ * dpaa2_io_service_enqueue_orp_qd() - Enqueue a frame to a queueing destination
-+ * with order restoration
-+ * @d: the given DPIO service.
-+ * @qdid: the given queuing destination id.
-+ * @fd: the frame descriptor which is enqueued.
-+ * @orpid: the order restoration point ID
-+ * @seqnum: the order sequence number
-+ * @last: must be set for the final frame if seqnum is shared (spilt frame)
-+ *
-+ * Performs an enqueue to a frame queue using the specified order restoration
-+ * point. The QMan device will ensure the order of frames placed on the
-+ * queue will be ordered as per the sequence number.
-+ *
-+ * In the case a frame is split it is possible to enqueue using the same
-+ * sequence number more than once. The final frame in a shared sequence number
-+ * most be indicated by setting last = 1. For non shared sequence numbers
-+ * last = 1 must always be set.
-+ *
-+ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
-+ * or -ENODEV if there is no dpio service.
-+ */
-+int dpaa2_io_service_enqueue_orp_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
-+				    u16 qdbin, const struct dpaa2_fd *fd,
-+				    u16 orpid, u16 seqnum, int last)
-+{
-+	struct qbman_eq_desc ed;
-+
-+	d = service_select(d);
-+	if (!d)
-+		return -ENODEV;
-+	qbman_eq_desc_clear(&ed);
-+	qbman_eq_desc_set_orp(&ed, 0, orpid, seqnum, !last);
-+	qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
-+	return qbman_swp_enqueue(d->swp, &ed, fd);
-+}
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_enqueue_orp_qd);
-+
-+/**
-+ * dpaa2_io_service_orp_seqnum_drop() - Remove a sequence number from
-+ * an order restoration list
-+ * @d: the given DPIO service.
-+ * @orpid: Order restoration point to remove a sequence number from
-+ * @seqnum: Sequence number to remove
-+ *
-+ * Removes a frames sequence number from an order restoration point without
-+ * enqueing the frame. Used to indicate that the order restoration hardware
-+ * should not expect to see this sequence number. Typically used to indicate
-+ * a frame was terminated or dropped from a flow.
-+ *
-+ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
-+ * or -ENODEV if there is no dpio service.
-+ */
-+int dpaa2_io_service_orp_seqnum_drop(struct dpaa2_io *d, u16 orpid, u16 seqnum)
-+{
-+	struct qbman_eq_desc ed;
-+	struct dpaa2_fd fd;
-+
-+	d = service_select(d);
-+	if (!d)
-+		return -ENODEV;
-+	qbman_eq_desc_clear(&ed);
-+	qbman_eq_desc_set_orp_hole(&ed, orpid, seqnum);
-+	return qbman_swp_enqueue(d->swp, &ed, &fd);
-+}
-+EXPORT_SYMBOL_GPL(dpaa2_io_service_orp_seqnum_drop);
---- a/drivers/staging/fsl-mc/bus/dpio/dpio.c
-+++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c
-@@ -1,34 +1,8 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #include <linux/kernel.h>
- #include "../../include/mc.h"
-@@ -222,3 +196,26 @@ int dpio_get_api_version(struct fsl_mc_i
- 
- 	return 0;
- }
-+
-+/**
-+ * dpio_reset() - Reset the DPIO, returns the object to initial state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPIO object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpio_reset(struct fsl_mc_io *mc_io,
-+	       u32 cmd_flags,
-+	       u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
---- a/drivers/staging/fsl-mc/bus/dpio/dpio.h
-+++ b/drivers/staging/fsl-mc/bus/dpio/dpio.h
-@@ -1,34 +1,8 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef __FSL_DPIO_H
- #define __FSL_DPIO_H
-@@ -106,4 +80,8 @@ int dpio_get_api_version(struct fsl_mc_i
- 			 u16 *major_ver,
- 			 u16 *minor_ver);
- 
-+int dpio_reset(struct fsl_mc_io	*mc_io,
-+	       u32 cmd_flags,
-+	       u16 token);
-+
- #endif /* __FSL_DPIO_H */
---- a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
-+++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
-@@ -1,33 +1,8 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
-  * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *       notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *       notice, this list of conditions and the following disclaimer in the
-- *       documentation and/or other materials provided with the distribution.
-- *     * Neither the name of Freescale Semiconductor nor the
-- *       names of its contributors may be used to endorse or promote products
-- *       derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- 
- #include <asm/cacheflush.h>
-@@ -99,6 +74,14 @@ enum qbman_sdqcr_fc {
- 	qbman_sdqcr_fc_up_to_3 = 1
- };
- 
-+#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
-+#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
-+static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
-+{
-+	dcivac(p->addr_cena + offset);
-+	prefetch(p->addr_cena + offset);
-+}
-+
- /* Portal Access */
- 
- static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
-@@ -189,7 +172,7 @@ struct qbman_swp *qbman_swp_init(const s
- 	p->addr_cinh = d->cinh_bar;
- 
- 	reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
--				1, /* Writes Non-cacheable */
-+				0, /* Writes cacheable */
- 				0, /* EQCR_CI stashing threshold */
- 				3, /* RPM: Valid bit mode, RCR in array mode */
- 				2, /* DCM: Discrete consumption ack mode */
-@@ -315,6 +298,7 @@ void qbman_swp_mc_submit(struct qbman_sw
- 
- 	dma_wmb();
- 	*v = cmd_verb | p->mc.valid_bit;
-+	dccvac(cmd);
- }
- 
- /*
-@@ -325,6 +309,7 @@ void *qbman_swp_mc_result(struct qbman_s
- {
- 	u32 *ret, verb;
- 
-+	qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
- 	ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
- 
- 	/* Remove the valid-bit - command completed if the rest is non-zero */
-@@ -370,6 +355,43 @@ void qbman_eq_desc_set_no_orp(struct qbm
- 		d->verb |= enqueue_rejects_to_fq;
- }
- 
-+/**
-+ * qbman_eq_desc_set_orp() - Set order-restoration in the enqueue descriptor
-+ * @d: the enqueue descriptor.
-+ * @response_success: 1 = enqueue with response always; 0 = enqueue with
-+ * rejections returned on a FQ.
-+ * @oprid: the order point record id.
-+ * @seqnum: the order restoration sequence number.
-+ * @incomplete: indicates whether this is the last fragments using the same
-+ * sequence number.
-+ */
-+void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
-+			   u16 oprid, u16 seqnum, int incomplete)
-+{
-+	d->verb |= (1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
-+	if (respond_success)
-+		d->verb |= enqueue_response_always;
-+	else
-+		d->verb |= enqueue_rejects_to_fq;
-+	d->orpid = cpu_to_le16(oprid);
-+	d->seqnum = cpu_to_le16((!!incomplete << 14) | seqnum);
-+}
-+
-+/**
-+ * qbman_eq_desc_set_orp_hole() - fill a hole in the order-restoration sequence
-+ * without any enqueue
-+ * @d: the enqueue descriptor.
-+ * @oprid: the order point record id.
-+ * @seqnum: the order restoration sequence number.
-+ */
-+void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, u16 oprid,
-+				u16 seqnum)
-+{
-+	d->verb |= (1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT) | enqueue_empty;
-+	d->orpid = cpu_to_le16(oprid);
-+	d->seqnum = cpu_to_le16(seqnum);
-+}
-+
- /*
-  * Exactly one of the following descriptor "targets" should be set. (Calling any
-  * one of these will replace the effect of any prior call to one of these.)
-@@ -429,12 +451,23 @@ int qbman_swp_enqueue(struct qbman_swp *
- 		return -EBUSY;
- 
- 	p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
--	memcpy(&p->dca, &d->dca, 31);
-+	/* This is mapped as DEVICE type memory, writes are
-+	 * with address alignment:
-+	 * desc.dca address alignment = 1
-+	 * desc.seqnum address alignment = 2
-+	 * desc.orpid address alignment = 4
-+	 * desc.tgtid address alignment = 8
-+	 */
-+	p->dca = d->dca;
-+	p->seqnum = d->seqnum;
-+	p->orpid = d->orpid;
-+	memcpy(&p->tgtid, &d->tgtid, 24);
- 	memcpy(&p->fd, fd, sizeof(*fd));
- 
- 	/* Set the verb byte, have to substitute in the valid-bit */
- 	dma_wmb();
- 	p->verb = d->verb | EQAR_VB(eqar);
-+	dccvac(p);
- 
- 	return 0;
- }
-@@ -522,7 +555,7 @@ void qbman_pull_desc_set_storage(struct
- 				 int stash)
- {
- 	/* save the virtual address */
--	d->rsp_addr_virt = (u64)storage;
-+	d->rsp_addr_virt = (u64)(uintptr_t)storage;
- 
- 	if (!storage) {
- 		d->verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
-@@ -615,7 +648,7 @@ int qbman_swp_pull(struct qbman_swp *s,
- 		atomic_inc(&s->vdq.available);
- 		return -EBUSY;
- 	}
--	s->vdq.storage = (void *)d->rsp_addr_virt;
-+	s->vdq.storage = (void *)(uintptr_t)d->rsp_addr_virt;
- 	p = qbman_get_cmd(s, QBMAN_CENA_SWP_VDQCR);
- 	p->numf = d->numf;
- 	p->tok = QMAN_DQ_TOKEN_VALID;
-@@ -627,6 +660,7 @@ int qbman_swp_pull(struct qbman_swp *s,
- 	/* Set the verb byte, have to substitute in the valid-bit */
- 	p->verb = d->verb | s->vdq.valid_bit;
- 	s->vdq.valid_bit ^= QB_VALID_BIT;
-+	dccvac(p);
- 
- 	return 0;
- }
-@@ -680,8 +714,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
- 				 s->dqrr.next_idx, pi);
- 			s->dqrr.reset_bug = 0;
- 		}
--		prefetch(qbman_get_cmd(s,
--				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
-+		qbman_inval_prefetch(s,	QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
- 	}
- 
- 	p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
-@@ -696,8 +729,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
- 	 * knew from reading PI.
- 	 */
- 	if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
--		prefetch(qbman_get_cmd(s,
--				       QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
-+		qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
- 		return NULL;
- 	}
- 	/*
-@@ -720,7 +752,7 @@ const struct dpaa2_dq *qbman_swp_dqrr_ne
- 	    (flags & DPAA2_DQ_STAT_EXPIRED))
- 		atomic_inc(&s->vdq.available);
- 
--	prefetch(qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx)));
-+	qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
- 
- 	return p;
- }
-@@ -848,6 +880,7 @@ int qbman_swp_release(struct qbman_swp *
- 	 */
- 	dma_wmb();
- 	p->verb = d->verb | RAR_VB(rar) | num_buffers;
-+	dccvac(p);
- 
- 	return 0;
- }
-@@ -855,7 +888,7 @@ int qbman_swp_release(struct qbman_swp *
- struct qbman_acquire_desc {
- 	u8 verb;
- 	u8 reserved;
--	u16 bpid;
-+	__le16 bpid;
- 	u8 num;
- 	u8 reserved2[59];
- };
-@@ -863,10 +896,10 @@ struct qbman_acquire_desc {
- struct qbman_acquire_rslt {
- 	u8 verb;
- 	u8 rslt;
--	u16 reserved;
-+	__le16 reserved;
- 	u8 num;
- 	u8 reserved2[3];
--	u64 buf[7];
-+	__le64 buf[7];
- };
- 
- /**
-@@ -929,7 +962,7 @@ int qbman_swp_acquire(struct qbman_swp *
- struct qbman_alt_fq_state_desc {
- 	u8 verb;
- 	u8 reserved[3];
--	u32 fqid;
-+	__le32 fqid;
- 	u8 reserved2[56];
- };
- 
-@@ -952,7 +985,7 @@ int qbman_swp_alt_fq_state(struct qbman_
- 	if (!p)
- 		return -EBUSY;
- 
--	p->fqid = cpu_to_le32(fqid) & ALT_FQ_FQID_MASK;
-+	p->fqid = cpu_to_le32(fqid & ALT_FQ_FQID_MASK);
- 
- 	/* Complete the management command */
- 	r = qbman_swp_mc_complete(s, p, alt_fq_verb);
-@@ -978,11 +1011,11 @@ int qbman_swp_alt_fq_state(struct qbman_
- struct qbman_cdan_ctrl_desc {
- 	u8 verb;
- 	u8 reserved;
--	u16 ch;
-+	__le16 ch;
- 	u8 we;
- 	u8 ctrl;
--	u16 reserved2;
--	u64 cdan_ctx;
-+	__le16 reserved2;
-+	__le64 cdan_ctx;
- 	u8 reserved3[48];
- 
- };
-@@ -990,7 +1023,7 @@ struct qbman_cdan_ctrl_desc {
- struct qbman_cdan_ctrl_rslt {
- 	u8 verb;
- 	u8 rslt;
--	u16 ch;
-+	__le16 ch;
- 	u8 reserved[60];
- };
- 
-@@ -1033,3 +1066,99 @@ int qbman_swp_CDAN_set(struct qbman_swp
- 
- 	return 0;
- }
-+
-+#define QBMAN_RESPONSE_VERB_MASK	0x7f
-+#define QBMAN_FQ_QUERY_NP		0x45
-+#define QBMAN_BP_QUERY			0x32
-+
-+struct qbman_fq_query_desc {
-+	u8 verb;
-+	u8 reserved[3];
-+	__le32 fqid;
-+	u8 reserved2[56];
-+};
-+
-+int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
-+			 struct qbman_fq_query_np_rslt *r)
-+{
-+	struct qbman_fq_query_desc *p;
-+	void *resp;
-+
-+	p = (struct qbman_fq_query_desc *)qbman_swp_mc_start(s);
-+	if (!p)
-+		return -EBUSY;
-+
-+	/* FQID is a 24 bit value */
-+	p->fqid = cpu_to_le32(fqid & 0x00FFFFFF);
-+	resp = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP);
-+	if (!resp) {
-+		pr_err("qbman: Query FQID %d NP fields failed, no response\n",
-+		       fqid);
-+		return -EIO;
-+	}
-+	*r = *(struct qbman_fq_query_np_rslt *)resp;
-+	/* Decode the outcome */
-+	WARN_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_FQ_QUERY_NP);
-+
-+	/* Determine success or failure */
-+	if (r->rslt != QBMAN_MC_RSLT_OK) {
-+		pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n",
-+		       p->fqid, r->rslt);
-+		return -EIO;
-+	}
-+
-+	return 0;
-+}
-+
-+u32 qbman_fq_state_frame_count(const struct qbman_fq_query_np_rslt *r)
-+{
-+	return (le32_to_cpu(r->frm_cnt) & 0x00FFFFFF);
-+}
-+
-+u32 qbman_fq_state_byte_count(const struct qbman_fq_query_np_rslt *r)
-+{
-+	return le32_to_cpu(r->byte_cnt);
-+}
-+
-+struct qbman_bp_query_desc {
-+	u8 verb;
-+	u8 reserved;
-+	__le16 bpid;
-+	u8 reserved2[60];
-+};
-+
-+int qbman_bp_query(struct qbman_swp *s, u16 bpid,
-+		   struct qbman_bp_query_rslt *r)
-+{
-+	struct qbman_bp_query_desc *p;
-+	void *resp;
-+
-+	p = (struct qbman_bp_query_desc *)qbman_swp_mc_start(s);
-+	if (!p)
-+		return -EBUSY;
-+
-+	p->bpid = cpu_to_le16(bpid);
-+	resp = qbman_swp_mc_complete(s, p, QBMAN_BP_QUERY);
-+	if (!resp) {
-+		pr_err("qbman: Query BPID %d fields failed, no response\n",
-+		       bpid);
-+		return -EIO;
-+	}
-+	*r = *(struct qbman_bp_query_rslt *)resp;
-+	/* Decode the outcome */
-+	WARN_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_BP_QUERY);
-+
-+	/* Determine success or failure */
-+	if (r->rslt != QBMAN_MC_RSLT_OK) {
-+		pr_err("Query fields of BPID 0x%x failed, code=0x%02x\n",
-+		       bpid, r->rslt);
-+		return -EIO;
-+	}
-+
-+	return 0;
-+}
-+
-+u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a)
-+{
-+	return le32_to_cpu(a->fill);
-+}
---- a/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
-+++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
-@@ -1,33 +1,8 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
-  * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *       notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *       notice, this list of conditions and the following disclaimer in the
-- *       documentation and/or other materials provided with the distribution.
-- *     * Neither the name of Freescale Semiconductor nor the
-- *       names of its contributors may be used to endorse or promote products
-- *       derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef __FSL_QBMAN_PORTAL_H
- #define __FSL_QBMAN_PORTAL_H
-@@ -57,8 +32,8 @@ struct qbman_pull_desc {
- 	u8 numf;
- 	u8 tok;
- 	u8 reserved;
--	u32 dq_src;
--	u64 rsp_addr;
-+	__le32 dq_src;
-+	__le64 rsp_addr;
- 	u64 rsp_addr_virt;
- 	u8 padding[40];
- };
-@@ -95,17 +70,17 @@ enum qbman_pull_type_e {
- struct qbman_eq_desc {
- 	u8 verb;
- 	u8 dca;
--	u16 seqnum;
--	u16 orpid;
--	u16 reserved1;
--	u32 tgtid;
--	u32 tag;
--	u16 qdbin;
-+	__le16 seqnum;
-+	__le16 orpid;
-+	__le16 reserved1;
-+	__le32 tgtid;
-+	__le32 tag;
-+	__le16 qdbin;
- 	u8 qpri;
- 	u8 reserved[3];
- 	u8 wae;
- 	u8 rspid;
--	u64 rsp_addr;
-+	__le64 rsp_addr;
- 	u8 fd[32];
- };
- 
-@@ -113,9 +88,9 @@ struct qbman_eq_desc {
- struct qbman_release_desc {
- 	u8 verb;
- 	u8 reserved;
--	u16 bpid;
--	u32 reserved2;
--	u64 buf[7];
-+	__le16 bpid;
-+	__le32 reserved2;
-+	__le64 buf[7];
- };
- 
- /* Management command result codes */
-@@ -187,6 +162,9 @@ int qbman_result_has_new_result(struct q
- 
- void qbman_eq_desc_clear(struct qbman_eq_desc *d);
- void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
-+void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
-+			   u16 oprid, u16 seqnum, int incomplete);
-+void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, u16 oprid, u16 seqnum);
- void qbman_eq_desc_set_token(struct qbman_eq_desc *d, u8 token);
- void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
- void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
-@@ -466,4 +444,62 @@ static inline void *qbman_swp_mc_complet
- 	return cmd;
- }
- 
-+/* Query APIs */
-+struct qbman_fq_query_np_rslt {
-+	u8 verb;
-+	u8 rslt;
-+	u8 st1;
-+	u8 st2;
-+	u8 reserved[2];
-+	__le16 od1_sfdr;
-+	__le16 od2_sfdr;
-+	__le16 od3_sfdr;
-+	__le16 ra1_sfdr;
-+	__le16 ra2_sfdr;
-+	__le32 pfdr_hptr;
-+	__le32 pfdr_tptr;
-+	__le32 frm_cnt;
-+	__le32 byte_cnt;
-+	__le16 ics_surp;
-+	u8 is;
-+	u8 reserved2[29];
-+};
-+
-+int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
-+			 struct qbman_fq_query_np_rslt *r);
-+u32 qbman_fq_state_frame_count(const struct qbman_fq_query_np_rslt *r);
-+u32 qbman_fq_state_byte_count(const struct qbman_fq_query_np_rslt *r);
-+
-+struct qbman_bp_query_rslt {
-+	u8 verb;
-+	u8 rslt;
-+	u8 reserved[4];
-+	u8 bdi;
-+	u8 state;
-+	__le32 fill;
-+	__le32 hdotr;
-+	__le16 swdet;
-+	__le16 swdxt;
-+	__le16 hwdet;
-+	__le16 hwdxt;
-+	__le16 swset;
-+	__le16 swsxt;
-+	__le16 vbpid;
-+	__le16 icid;
-+	__le64 bpscn_addr;
-+	__le64 bpscn_ctx;
-+	__le16 hw_targ;
-+	u8 dbe;
-+	u8 reserved2;
-+	u8 sdcnt;
-+	u8 hdcnt;
-+	u8 sscnt;
-+	u8 reserved3[9];
-+};
-+
-+int qbman_bp_query(struct qbman_swp *s, u16 bpid,
-+		   struct qbman_bp_query_rslt *r);
-+
-+u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a);
-+
- #endif /* __FSL_QBMAN_PORTAL_H */
---- a/drivers/staging/fsl-mc/bus/dpmcp.c
-+++ b/drivers/staging/fsl-mc/bus/dpmcp.c
-@@ -1,33 +1,7 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #include <linux/kernel.h>
- #include "../include/mc.h"
---- a/drivers/staging/fsl-mc/bus/dprc-driver.c
-+++ b/drivers/staging/fsl-mc/bus/dprc-driver.c
-@@ -1,12 +1,10 @@
-+// SPDX-License-Identifier: GPL-2.0
- /*
-  * Freescale data path resource container (DPRC) driver
-  *
-  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
-  * Author: German Rivera <German.Rivera@freescale.com>
-  *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-  */
- 
- #include <linux/module.h>
---- a/drivers/staging/fsl-mc/bus/dprc.c
-+++ b/drivers/staging/fsl-mc/bus/dprc.c
-@@ -1,33 +1,7 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #include <linux/kernel.h>
- #include "../include/mc.h"
---- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
-+++ b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
-@@ -1,11 +1,9 @@
-+// SPDX-License-Identifier: GPL-2.0
- /*
-  * fsl-mc object allocator driver
-  *
-  * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
-  *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-  */
- 
- #include <linux/module.h>
---- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
-+++ b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
-@@ -1,12 +1,10 @@
-+// SPDX-License-Identifier: GPL-2.0
- /*
-  * Freescale Management Complex (MC) bus driver
-  *
-  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
-  * Author: German Rivera <German.Rivera@freescale.com>
-  *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-  */
- 
- #define pr_fmt(fmt) "fsl-mc: " fmt
---- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
-+++ b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
-@@ -1,12 +1,10 @@
-+// SPDX-License-Identifier: GPL-2.0
- /*
-  * Freescale Management Complex (MC) bus driver MSI support
-  *
-  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
-  * Author: German Rivera <German.Rivera@freescale.com>
-  *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-  */
- 
- #include <linux/of_device.h>
---- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h
-+++ b/drivers/staging/fsl-mc/bus/fsl-mc-private.h
-@@ -1,11 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
- /*
-  * Freescale Management Complex (MC) bus private declarations
-  *
-  * Copyright (C) 2016 Freescale Semiconductor, Inc.
-  *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-  */
- #ifndef _FSL_MC_PRIVATE_H_
- #define _FSL_MC_PRIVATE_H_
---- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
-+++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
-@@ -1,12 +1,10 @@
-+// SPDX-License-Identifier: GPL-2.0
- /*
-  * Freescale Management Complex (MC) bus driver MSI support
-  *
-  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
-  * Author: German Rivera <German.Rivera@freescale.com>
-  *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-  */
- 
- #include <linux/of_device.h>
---- a/drivers/staging/fsl-mc/bus/mc-io.c
-+++ b/drivers/staging/fsl-mc/bus/mc-io.c
-@@ -1,33 +1,7 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *       notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *       notice, this list of conditions and the following disclaimer in the
-- *       documentation and/or other materials provided with the distribution.
-- *     * Neither the name of the above-listed copyright holders nor the
-- *       names of any contributors may be used to endorse or promote products
-- *       derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- 
- #include <linux/io.h>
---- a/drivers/staging/fsl-mc/bus/mc-sys.c
-+++ b/drivers/staging/fsl-mc/bus/mc-sys.c
-@@ -1,35 +1,9 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-  * I/O services to send MC commands to the MC hardware
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *       notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *       notice, this list of conditions and the following disclaimer in the
-- *       documentation and/or other materials provided with the distribution.
-- *     * Neither the name of the above-listed copyright holders nor the
-- *       names of any contributors may be used to endorse or promote products
-- *       derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- 
- #include <linux/delay.h>
---- a/drivers/staging/fsl-mc/include/dpaa2-fd.h
-+++ b/drivers/staging/fsl-mc/include/dpaa2-fd.h
-@@ -1,33 +1,8 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright 2014-2016 Freescale Semiconductor Inc.
-  * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *       notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *       notice, this list of conditions and the following disclaimer in the
-- *       documentation and/or other materials provided with the distribution.
-- *     * Neither the name of Freescale Semiconductor nor the
-- *       names of its contributors may be used to endorse or promote products
-- *       derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef __FSL_DPAA2_FD_H
- #define __FSL_DPAA2_FD_H
-@@ -91,6 +66,27 @@ struct dpaa2_fd {
- #define SG_BPID_MASK		0x3FFF
- #define SG_FINAL_FLAG_MASK	0x1
- #define SG_FINAL_FLAG_SHIFT	15
-+#define FL_SHORT_LEN_FLAG_MASK	0x1
-+#define FL_SHORT_LEN_FLAG_SHIFT	14
-+#define FL_SHORT_LEN_MASK	0x3FFFF
-+#define FL_OFFSET_MASK		0x0FFF
-+#define FL_FORMAT_MASK		0x3
-+#define FL_FORMAT_SHIFT		12
-+#define FL_BPID_MASK		0x3FFF
-+#define FL_FINAL_FLAG_MASK	0x1
-+#define FL_FINAL_FLAG_SHIFT	15
-+
-+/* Error bits in FD CTRL */
-+#define FD_CTRL_ERR_MASK	0x000000FF
-+#define FD_CTRL_UFD		0x00000004
-+#define FD_CTRL_SBE		0x00000008
-+#define FD_CTRL_FLC		0x00000010
-+#define FD_CTRL_FSE		0x00000020
-+#define FD_CTRL_FAERR		0x00000040
-+
-+/* Annotation bits in FD CTRL */
-+#define FD_CTRL_PTA		0x00800000
-+#define FD_CTRL_PTV1		0x00400000
- 
- enum dpaa2_fd_format {
- 	dpaa2_fd_single = 0,
-@@ -312,7 +308,7 @@ enum dpaa2_sg_format {
-  */
- static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
- {
--	return le64_to_cpu((dma_addr_t)sg->addr);
-+	return (dma_addr_t)le64_to_cpu(sg->addr);
- }
- 
- /**
-@@ -443,9 +439,243 @@ static inline bool dpaa2_sg_is_final(con
-  */
- static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
- {
--	sg->format_offset &= cpu_to_le16(~(SG_FINAL_FLAG_MASK
--					 << SG_FINAL_FLAG_SHIFT));
-+	sg->format_offset &= cpu_to_le16((~(SG_FINAL_FLAG_MASK
-+					 << SG_FINAL_FLAG_SHIFT)) & 0xFFFF);
- 	sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
- }
- 
-+/**
-+ * struct dpaa2_fl_entry - structure for frame list entry.
-+ * @addr:          address in the FLE
-+ * @len:           length in the FLE
-+ * @bpid:          buffer pool ID
-+ * @format_offset: format, offset, and short-length fields
-+ * @frc:           frame context
-+ * @ctrl:          control bits...including pta, pvt1, pvt2, err, etc
-+ * @flc:           flow context address
-+ */
-+struct dpaa2_fl_entry {
-+	__le64 addr;
-+	__le32 len;
-+	__le16 bpid;
-+	__le16 format_offset;
-+	__le32 frc;
-+	__le32 ctrl;
-+	__le64 flc;
-+};
-+
-+enum dpaa2_fl_format {
-+	dpaa2_fl_single = 0,
-+	dpaa2_fl_res,
-+	dpaa2_fl_sg
-+};
-+
-+/**
-+ * dpaa2_fl_get_addr() - get the addr field of FLE
-+ * @fle: the given frame list entry
-+ *
-+ * Return the address in the frame list entry.
-+ */
-+static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
-+{
-+	return (dma_addr_t)le64_to_cpu(fle->addr);
-+}
-+
-+/**
-+ * dpaa2_fl_set_addr() - Set the addr field of FLE
-+ * @fle: the given frame list entry
-+ * @addr: the address needs to be set in frame list entry
-+ */
-+static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
-+				     dma_addr_t addr)
-+{
-+	fle->addr = cpu_to_le64(addr);
-+}
-+
-+/**
-+ * dpaa2_fl_get_frc() - Get the frame context in the FLE
-+ * @fle: the given frame list entry
-+ *
-+ * Return the frame context field in the frame lsit entry.
-+ */
-+static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
-+{
-+	return le32_to_cpu(fle->frc);
-+}
-+
-+/**
-+ * dpaa2_fl_set_frc() - Set the frame context in the FLE
-+ * @fle: the given frame list entry
-+ * @frc: the frame context needs to be set in frame list entry
-+ */
-+static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
-+{
-+	fle->frc = cpu_to_le32(frc);
-+}
-+
-+/**
-+ * dpaa2_fl_get_ctrl() - Get the control bits in the FLE
-+ * @fle: the given frame list entry
-+ *
-+ * Return the control bits field in the frame list entry.
-+ */
-+static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
-+{
-+	return le32_to_cpu(fle->ctrl);
-+}
-+
-+/**
-+ * dpaa2_fl_set_ctrl() - Set the control bits in the FLE
-+ * @fle: the given frame list entry
-+ * @ctrl: the control bits to be set in the frame list entry
-+ */
-+static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
-+{
-+	fle->ctrl = cpu_to_le32(ctrl);
-+}
-+
-+/**
-+ * dpaa2_fl_get_flc() - Get the flow context in the FLE
-+ * @fle: the given frame list entry
-+ *
-+ * Return the flow context in the frame list entry.
-+ */
-+static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
-+{
-+	return (dma_addr_t)le64_to_cpu(fle->flc);
-+}
-+
-+/**
-+ * dpaa2_fl_set_flc() - Set the flow context field of FLE
-+ * @fle: the given frame list entry
-+ * @flc_addr: the flow context needs to be set in frame list entry
-+ */
-+static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
-+				    dma_addr_t flc_addr)
-+{
-+	fle->flc = cpu_to_le64(flc_addr);
-+}
-+
-+static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
-+{
-+	return !!((le16_to_cpu(fle->format_offset) >>
-+		  FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
-+}
-+
-+/**
-+ * dpaa2_fl_get_len() - Get the length in the FLE
-+ * @fle: the given frame list entry
-+ *
-+ * Return the length field in the frame list entry.
-+ */
-+static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
-+{
-+	if (dpaa2_fl_short_len(fle))
-+		return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
-+
-+	return le32_to_cpu(fle->len);
-+}
-+
-+/**
-+ * dpaa2_fl_set_len() - Set the length field of FLE
-+ * @fle: the given frame list entry
-+ * @len: the length needs to be set in frame list entry
-+ */
-+static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
-+{
-+	fle->len = cpu_to_le32(len);
-+}
-+
-+/**
-+ * dpaa2_fl_get_offset() - Get the offset field in the frame list entry
-+ * @fle: the given frame list entry
-+ *
-+ * Return the offset.
-+ */
-+static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
-+{
-+	return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
-+}
-+
-+/**
-+ * dpaa2_fl_set_offset() - Set the offset field of FLE
-+ * @fle: the given frame list entry
-+ * @offset: the offset needs to be set in frame list entry
-+ */
-+static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
-+{
-+	fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
-+	fle->format_offset |= cpu_to_le16(offset);
-+}
-+
-+/**
-+ * dpaa2_fl_get_format() - Get the format field in the FLE
-+ * @fle: the given frame list entry
-+ *
-+ * Return the format.
-+ */
-+static inline enum dpaa2_fl_format dpaa2_fl_get_format(
-+					const struct dpaa2_fl_entry *fle)
-+{
-+	return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
-+				       FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
-+}
-+
-+/**
-+ * dpaa2_fl_set_format() - Set the format field of FLE
-+ * @fle: the given frame list entry
-+ * @format: the format needs to be set in frame list entry
-+ */
-+static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
-+				       enum dpaa2_fl_format format)
-+{
-+	fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
-+	fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
-+}
-+
-+/**
-+ * dpaa2_fl_get_bpid() - Get the bpid field in the FLE
-+ * @fle: the given frame list entry
-+ *
-+ * Return the buffer pool id.
-+ */
-+static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
-+{
-+	return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
-+}
-+
-+/**
-+ * dpaa2_fl_set_bpid() - Set the bpid field of FLE
-+ * @fle: the given frame list entry
-+ * @bpid: buffer pool id to be set
-+ */
-+static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
-+{
-+	fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
-+	fle->bpid |= cpu_to_le16(bpid);
-+}
-+
-+/**
-+ * dpaa2_fl_is_final() - Check final bit in FLE
-+ * @fle: the given frame list entry
-+ *
-+ * Return bool.
-+ */
-+static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
-+{
-+	return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
-+}
-+
-+/**
-+ * dpaa2_fl_set_final() - Set the final bit in FLE
-+ * @fle: the given frame list entry
-+ * @final: the final boolean to be set
-+ */
-+static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
-+{
-+	fle->format_offset &= cpu_to_le16(~(FL_FINAL_FLAG_MASK <<
-+					    FL_FINAL_FLAG_SHIFT));
-+	fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
-+}
-+
- #endif /* __FSL_DPAA2_FD_H */
---- a/drivers/staging/fsl-mc/include/dpaa2-global.h
-+++ b/drivers/staging/fsl-mc/include/dpaa2-global.h
-@@ -1,33 +1,8 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright 2014-2016 Freescale Semiconductor Inc.
-  * Copyright 2016 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *       notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *       notice, this list of conditions and the following disclaimer in the
-- *       documentation and/or other materials provided with the distribution.
-- *     * Neither the name of Freescale Semiconductor nor the
-- *       names of its contributors may be used to endorse or promote products
-- *       derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef __FSL_DPAA2_GLOBAL_H
- #define __FSL_DPAA2_GLOBAL_H
---- a/drivers/staging/fsl-mc/include/dpaa2-io.h
-+++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
-@@ -1,33 +1,8 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright 2014-2016 Freescale Semiconductor Inc.
-- * Copyright NXP
-+ * Copyright 2017 NXP
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- *     * Redistributions of source code must retain the above copyright
-- *       notice, this list of conditions and the following disclaimer.
-- *     * Redistributions in binary form must reproduce the above copyright
-- *       notice, this list of conditions and the following disclaimer in the
-- *       documentation and/or other materials provided with the distribution.
-- *     * Neither the name of Freescale Semiconductor nor the
-- *       names of its contributors may be used to endorse or promote products
-- *       derived from this software without specific prior written permission.
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef __FSL_DPAA2_IO_H
- #define __FSL_DPAA2_IO_H
-@@ -88,6 +63,8 @@ void dpaa2_io_down(struct dpaa2_io *d);
- 
- irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
- 
-+struct dpaa2_io *dpaa2_io_service_select(int cpu);
-+
- /**
-  * struct dpaa2_io_notification_ctx - The DPIO notification context structure
-  * @cb:           The callback to be invoked when the notification arrives
-@@ -103,7 +80,7 @@ irqreturn_t dpaa2_io_irq(struct dpaa2_io
-  * Used when a FQDAN/CDAN registration is made by drivers.
-  */
- struct dpaa2_io_notification_ctx {
--	void (*cb)(struct dpaa2_io_notification_ctx *);
-+	void (*cb)(struct dpaa2_io_notification_ctx *ctx);
- 	int is_cdan;
- 	u32 id;
- 	int desired_cpu;
-@@ -129,9 +106,9 @@ int dpaa2_io_service_enqueue_fq(struct d
- 				const struct dpaa2_fd *fd);
- int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
- 				u16 qdbin, const struct dpaa2_fd *fd);
--int dpaa2_io_service_release(struct dpaa2_io *d, u32 bpid,
-+int dpaa2_io_service_release(struct dpaa2_io *d, u16 bpid,
- 			     const u64 *buffers, unsigned int num_buffers);
--int dpaa2_io_service_acquire(struct dpaa2_io *d, u32 bpid,
-+int dpaa2_io_service_acquire(struct dpaa2_io *d, u16 bpid,
- 			     u64 *buffers, unsigned int num_buffers);
- 
- struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
-@@ -139,4 +116,64 @@ struct dpaa2_io_store *dpaa2_io_store_cr
- void dpaa2_io_store_destroy(struct dpaa2_io_store *s);
- struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last);
- 
-+/* Order Restoration Support */
-+int dpaa2_io_service_enqueue_orp_fq(struct dpaa2_io *d, u32 fqid,
-+				    const struct dpaa2_fd *fd, u16 orpid,
-+				    u16 seqnum, int last);
-+
-+int dpaa2_io_service_enqueue_orp_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
-+				    u16 qdbin, const struct dpaa2_fd *fd,
-+				    u16 orpid, u16 seqnum, int last);
-+
-+int dpaa2_io_service_orp_seqnum_drop(struct dpaa2_io *d, u16 orpid,
-+				     u16 seqnum);
-+
-+/***************/
-+/* CSCN        */
-+/***************/
-+
-+/**
-+ * struct dpaa2_cscn - The CSCN message format
-+ * @verb: identifies the type of message (should be 0x27).
-+ * @stat: status bits related to dequeuing response (not used)
-+ * @state: bit 0 = 0/1 if CG is no/is congested
-+ * @reserved: reserved byte
-+ * @cgid: congest grp ID - the first 16 bits
-+ * @ctx: context data
-+ *
-+ * Congestion management can be implemented in software through
-+ * the use of Congestion State Change Notifications (CSCN). These
-+ * are messages written by DPAA2 hardware to memory whenever the
-+ * instantaneous count (I_CNT field in the CG) exceeds the
-+ * Congestion State (CS) entrance threshold, signifying congestion
-+ * entrance, or when the instantaneous count returns below exit
-+ * threshold, signifying congestion exit. The format of the message
-+ * is given by the dpaa2_cscn structure. Bit 0 of the state field
-+ * represents congestion state written by the hardware.
-+ */
-+struct dpaa2_cscn {
-+	u8 verb;
-+	u8 stat;
-+	u8 state;
-+	u8 reserved;
-+	__le32 cgid;
-+	__le64 ctx;
-+};
-+
-+#define DPAA2_CSCN_SIZE                        64
-+#define DPAA2_CSCN_ALIGN               16
-+
-+#define DPAA2_CSCN_STATE_MASK          0x1
-+#define DPAA2_CSCN_CONGESTED           1
-+
-+static inline bool dpaa2_cscn_state_congested(struct dpaa2_cscn *cscn)
-+{
-+	return ((cscn->state & DPAA2_CSCN_STATE_MASK) == DPAA2_CSCN_CONGESTED);
-+}
-+
-+int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid,
-+			    u32 *fcnt, u32 *bcnt);
-+int dpaa2_io_query_bp_count(struct dpaa2_io *d, u16 bpid,
-+			    u32 *num);
-+
- #endif /* __FSL_DPAA2_IO_H */
---- a/drivers/staging/fsl-mc/include/dpbp.h
-+++ b/drivers/staging/fsl-mc/include/dpbp.h
-@@ -1,34 +1,7 @@
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
- /*
-  * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef __FSL_DPBP_H
- #define __FSL_DPBP_H
---- a/drivers/staging/fsl-mc/include/dpcon.h
-+++ b/drivers/staging/fsl-mc/include/dpcon.h
-@@ -1,33 +1,7 @@
--/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor Inc.
-  *
-- * Redistribution and use in source and binary forms, with or without
-- * modification, are permitted provided that the following conditions are met:
-- * * Redistributions of source code must retain the above copyright
-- * notice, this list of conditions and the following disclaimer.
-- * * Redistributions in binary form must reproduce the above copyright
-- * notice, this list of conditions and the following disclaimer in the
-- * documentation and/or other materials provided with the distribution.
-- * * Neither the name of the above-listed copyright holders nor the
-- * names of any contributors may be used to endorse or promote products
-- * derived from this software without specific prior written permission.
-- *
-- *
-- * ALTERNATIVELY, this software may be distributed under the terms of the
-- * GNU General Public License ("GPL") as published by the Free Software
-- * Foundation, either version 2 of that License or (at your option) any
-- * later version.
-- *
-- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- * POSSIBILITY OF SUCH DAMAGE.
-  */
- #ifndef __FSL_DPCON_H
- #define __FSL_DPCON_H
---- /dev/null
-+++ b/drivers/staging/fsl-mc/include/dpopr.h
-@@ -0,0 +1,110 @@
-+/*
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#ifndef __FSL_DPOPR_H_
-+#define __FSL_DPOPR_H_
-+
-+/* Data Path Order Restoration API
-+ * Contains initialization APIs and runtime APIs for the Order Restoration
-+ */
-+
-+/** Order Restoration properties */
-+
-+/**
-+ * Create a new Order Point Record option
-+ */
-+#define OPR_OPT_CREATE 0x1
-+/**
-+ * Retire an existing Order Point Record option
-+ */
-+#define OPR_OPT_RETIRE 0x2
-+
-+/**
-+ * struct opr_cfg - Structure representing OPR configuration
-+ * @oprrws: Order point record (OPR) restoration window size (0 to 5)
-+ *			0 - Window size is 32 frames.
-+ *			1 - Window size is 64 frames.
-+ *			2 - Window size is 128 frames.
-+ *			3 - Window size is 256 frames.
-+ *			4 - Window size is 512 frames.
-+ *			5 - Window size is 1024 frames.
-+ * @oa: OPR auto advance NESN window size (0 disabled, 1 enabled)
-+ * @olws: OPR acceptable late arrival window size (0 to 3)
-+ *			0 - Disabled. Late arrivals are always rejected.
-+ *			1 - Window size is 32 frames.
-+ *			2 - Window size is the same as the OPR restoration
-+ *				window size configured in the OPRRWS field.
-+ *			3 - Window size is 8192 frames. Late arrivals are
-+ *				always accepted.
-+ * @oeane: Order restoration list (ORL) resource exhaustion
-+ *			advance NESN enable (0 disabled, 1 enabled)
-+ * @oloe: OPR loose ordering enable (0 disabled, 1 enabled)
-+ */
-+struct opr_cfg {
-+	u8 oprrws;
-+	u8 oa;
-+	u8 olws;
-+	u8 oeane;
-+	u8 oloe;
-+};
-+
-+/**
-+ * struct opr_qry - Structure representing OPR configuration
-+ * @enable: Enabled state
-+ * @rip: Retirement In Progress
-+ * @ndsn: Next dispensed sequence number
-+ * @nesn: Next expected sequence number
-+ * @ea_hseq: Early arrival head sequence number
-+ * @hseq_nlis: HSEQ not last in sequence
-+ * @ea_tseq: Early arrival tail sequence number
-+ * @tseq_nlis: TSEQ not last in sequence
-+ * @ea_tptr: Early arrival tail pointer
-+ * @ea_hptr: Early arrival head pointer
-+ * @opr_id: Order Point Record ID
-+ * @opr_vid: Order Point Record Virtual ID
-+ */
-+struct opr_qry {
-+	char enable;
-+	char rip;
-+	u16 ndsn;
-+	u16 nesn;
-+	u16 ea_hseq;
-+	char hseq_nlis;
-+	u16 ea_tseq;
-+	char tseq_nlis;
-+	u16 ea_tptr;
-+	u16 ea_hptr;
-+	u16 opr_id;
-+	u16 opr_vid;
-+};
-+
-+#endif /* __FSL_DPOPR_H_ */
---- a/drivers/staging/fsl-mc/include/mc.h
-+++ b/drivers/staging/fsl-mc/include/mc.h
-@@ -1,12 +1,10 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
- /*
-  * Freescale Management Complex (MC) bus public interface
-  *
-  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
-  * Author: German Rivera <German.Rivera@freescale.com>
-  *
-- * This file is licensed under the terms of the GNU General Public
-- * License version 2. This program is licensed "as is" without any
-- * warranty of any kind, whether express or implied.
-  */
- #ifndef _FSL_MC_H_
- #define _FSL_MC_H_
diff --git a/target/linux/layerscape/patches-4.14/702-dpaa2-ethernet-support-layerscape.patch b/target/linux/layerscape/patches-4.14/702-dpaa2-ethernet-support-layerscape.patch
deleted file mode 100644
index 44cedd123..000000000
--- a/target/linux/layerscape/patches-4.14/702-dpaa2-ethernet-support-layerscape.patch
+++ /dev/null
@@ -1,8094 +0,0 @@
-From 6ec4d0cf0b0e5e41abc91012db4ebff7d415a92b Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:13 +0800
-Subject: [PATCH 08/40] dpaa2-ethernet: support layerscape
-This is an integrated patch of dpaa2-ethernet for
- layerscape
-
-Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
-Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
-Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/staging/fsl-dpaa2/Kconfig             |    7 +
- drivers/staging/fsl-dpaa2/ethernet/Makefile   |    2 +
- .../fsl-dpaa2/ethernet/dpaa2-eth-ceetm.c      | 1240 +++++++++
- .../fsl-dpaa2/ethernet/dpaa2-eth-ceetm.h      |  183 ++
- .../fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c    |  357 +++
- .../fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h    |   60 +
- .../staging/fsl-dpaa2/ethernet/dpaa2-eth.c    | 2335 +++++++++++++----
- .../staging/fsl-dpaa2/ethernet/dpaa2-eth.h    |  388 ++-
- .../fsl-dpaa2/ethernet/dpaa2-ethtool.c        |  625 ++++-
- drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h |  192 +-
- drivers/staging/fsl-dpaa2/ethernet/dpni.c     |  604 ++++-
- drivers/staging/fsl-dpaa2/ethernet/dpni.h     |  344 ++-
- 12 files changed, 5723 insertions(+), 614 deletions(-)
- create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-ceetm.c
- create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-ceetm.h
- create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c
- create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h
-
---- a/drivers/staging/fsl-dpaa2/Kconfig
-+++ b/drivers/staging/fsl-dpaa2/Kconfig
-@@ -17,6 +17,13 @@ config FSL_DPAA2_ETH
- 	  Ethernet driver for Freescale DPAA2 SoCs, using the
- 	  Freescale MC bus driver
- 
-+config FSL_DPAA2_ETH_CEETM
-+	depends on NET_SCHED
-+	bool "DPAA2 Ethernet CEETM QoS"
-+	default n
-+	---help---
-+	  Enable QoS offloading support through the CEETM hardware block.
-+
- if FSL_DPAA2_ETH
- config FSL_DPAA2_ETH_USE_ERR_QUEUE
- 	bool "Enable Rx error queue"
---- a/drivers/staging/fsl-dpaa2/ethernet/Makefile
-+++ b/drivers/staging/fsl-dpaa2/ethernet/Makefile
-@@ -5,6 +5,8 @@
- obj-$(CONFIG_FSL_DPAA2_ETH) += fsl-dpaa2-eth.o
- 
- fsl-dpaa2-eth-objs    := dpaa2-eth.o dpaa2-ethtool.o dpni.o
-+fsl-dpaa2-eth-${CONFIG_FSL_DPAA2_ETH_DEBUGFS} += dpaa2-eth-debugfs.o
-+fsl-dpaa2-eth-${CONFIG_FSL_DPAA2_ETH_CEETM} += dpaa2-eth-ceetm.o
- 
- # Needed by the tracing framework
- CFLAGS_dpaa2-eth.o := -I$(src)
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-ceetm.c
-@@ -0,0 +1,1240 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+/*
-+ * Copyright 2017 NXP
-+ *
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+
-+#include "dpaa2-eth-ceetm.h"
-+#include "dpaa2-eth.h"
-+
-+#define DPAA2_CEETM_DESCRIPTION "FSL DPAA2 CEETM qdisc"
-+/* Conversion formula from userspace passed Bps to expected Mbit */
-+#define dpaa2_eth_bps_to_mbit(rate) (rate >> 17)
-+
-+static const struct nla_policy dpaa2_ceetm_policy[DPAA2_CEETM_TCA_MAX] = {
-+	[DPAA2_CEETM_TCA_COPT] = { .len = sizeof(struct dpaa2_ceetm_tc_copt) },
-+	[DPAA2_CEETM_TCA_QOPS] = { .len = sizeof(struct dpaa2_ceetm_tc_qopt) },
-+};
-+
-+struct Qdisc_ops dpaa2_ceetm_qdisc_ops;
-+
-+static inline int dpaa2_eth_set_ch_shaping(struct dpaa2_eth_priv *priv,
-+					   struct dpni_tx_shaping_cfg *scfg,
-+					   struct dpni_tx_shaping_cfg *ecfg,
-+					   int coupled, int ch_id)
-+{
-+	int err = 0;
-+
-+	netdev_dbg(priv->net_dev, "%s: ch_id %d rate %d mbps\n", __func__,
-+		   ch_id, scfg->rate_limit);
-+	err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, scfg,
-+				  ecfg, coupled);
-+	if (err)
-+		netdev_err(priv->net_dev, "dpni_set_tx_shaping err\n");
-+
-+	return err;
-+}
-+
-+static inline int dpaa2_eth_reset_ch_shaping(struct dpaa2_eth_priv *priv,
-+					     int ch_id)
-+{
-+	struct dpni_tx_shaping_cfg cfg = { 0 };
-+
-+	return dpaa2_eth_set_ch_shaping(priv, &cfg, &cfg, 0, ch_id);
-+}
-+
-+static inline int
-+dpaa2_eth_update_shaping_cfg(struct net_device *dev,
-+			     struct dpaa2_ceetm_shaping_cfg cfg,
-+			     struct dpni_tx_shaping_cfg *scfg,
-+			     struct dpni_tx_shaping_cfg *ecfg)
-+{
-+	scfg->rate_limit = dpaa2_eth_bps_to_mbit(cfg.cir);
-+	ecfg->rate_limit = dpaa2_eth_bps_to_mbit(cfg.eir);
-+
-+	if (cfg.cbs > DPAA2_ETH_MAX_BURST_SIZE) {
-+		netdev_err(dev, "Committed burst size must be under %d\n",
-+			   DPAA2_ETH_MAX_BURST_SIZE);
-+		return -EINVAL;
-+	}
-+
-+	scfg->max_burst_size = cfg.cbs;
-+
-+	if (cfg.ebs > DPAA2_ETH_MAX_BURST_SIZE) {
-+		netdev_err(dev, "Excess burst size must be under %d\n",
-+			   DPAA2_ETH_MAX_BURST_SIZE);
-+		return -EINVAL;
-+	}
-+
-+	ecfg->max_burst_size = cfg.ebs;
-+
-+	if ((!cfg.cir || !cfg.eir) && cfg.coupled) {
-+		netdev_err(dev, "Coupling can be set when both CIR and EIR are finite\n");
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+enum update_tx_prio {
-+	DPAA2_ETH_ADD_CQ,
-+	DPAA2_ETH_DEL_CQ,
-+};
-+
-+/* Normalize weights based on max passed value */
-+static inline int dpaa2_eth_normalize_tx_prio(struct dpaa2_ceetm_qdisc *priv)
-+{
-+	struct dpni_tx_schedule_cfg *sched_cfg;
-+	struct dpaa2_ceetm_class *cl;
-+	u32 qpri;
-+	u16 weight_max = 0, increment;
-+	int i;
-+
-+	/* Check the boundaries of the provided values */
-+	for (i = 0; i < priv->clhash.hashsize; i++)
-+		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode)
-+			weight_max = (weight_max == 0 ? cl->prio.weight :
-+				     (weight_max < cl->prio.weight ?
-+				      cl->prio.weight : weight_max));
-+
-+	/* If there are no elements, there's nothing to do */
-+	if (weight_max == 0)
-+		return 0;
-+
-+	increment = (DPAA2_CEETM_MAX_WEIGHT - DPAA2_CEETM_MIN_WEIGHT) /
-+		    weight_max;
-+
-+	for (i = 0; i < priv->clhash.hashsize; i++) {
-+		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode) {
-+			if (cl->prio.mode == STRICT_PRIORITY)
-+				continue;
-+
-+			qpri = cl->prio.qpri;
-+			sched_cfg = &priv->prio.tx_prio_cfg.tc_sched[qpri];
-+
-+			sched_cfg->delta_bandwidth =
-+				DPAA2_CEETM_MIN_WEIGHT +
-+				(cl->prio.weight * increment);
-+
-+			pr_debug("%s: Normalized CQ qpri %d weight to %d\n",
-+				 __func__, qpri, sched_cfg->delta_bandwidth);
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static inline int dpaa2_eth_update_tx_prio(struct dpaa2_eth_priv *priv,
-+					   struct dpaa2_ceetm_class *cl,
-+					   enum update_tx_prio type)
-+{
-+	struct dpaa2_ceetm_qdisc *sch = qdisc_priv(cl->parent);
-+	struct dpni_congestion_notification_cfg notif_cfg = {0};
-+	struct dpni_tx_schedule_cfg *sched_cfg;
-+	struct dpni_taildrop td = {0};
-+	u8 ch_id = 0, tc_id = 0;
-+	u32 qpri = 0;
-+	int err = 0;
-+
-+	qpri = cl->prio.qpri;
-+	tc_id = DPNI_BUILD_CH_TC(ch_id, qpri);
-+
-+	switch (type) {
-+	case DPAA2_ETH_ADD_CQ:
-+		/* Disable congestion notifications */
-+		notif_cfg.threshold_entry = 0;
-+		notif_cfg.threshold_exit = 0;
-+		err = dpni_set_congestion_notification(priv->mc_io, 0,
-+						       priv->mc_token,
-+						       DPNI_QUEUE_TX, tc_id,
-+						       &notif_cfg);
-+		if (err) {
-+			netdev_err(priv->net_dev, "Error disabling congestion notifications %d\n",
-+				   err);
-+			return err;
-+		}
-+		/* Enable taildrop */
-+		td.enable = 1;
-+		td.units = DPNI_CONGESTION_UNIT_FRAMES;
-+		td.threshold = DPAA2_CEETM_TD_THRESHOLD;
-+		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
-+					DPNI_CP_GROUP, DPNI_QUEUE_TX, tc_id,
-+					0, &td);
-+		if (err) {
-+			netdev_err(priv->net_dev, "Error enabling Tx taildrop %d\n",
-+				   err);
-+			return err;
-+		}
-+		break;
-+	case DPAA2_ETH_DEL_CQ:
-+		/* Disable taildrop */
-+		td.enable = 0;
-+		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
-+					DPNI_CP_GROUP, DPNI_QUEUE_TX, tc_id,
-+					0, &td);
-+		if (err) {
-+			netdev_err(priv->net_dev, "Error disabling Tx taildrop %d\n",
-+				   err);
-+			return err;
-+		}
-+		/* Enable congestion notifications */
-+		notif_cfg.units = DPNI_CONGESTION_UNIT_BYTES;
-+		notif_cfg.threshold_entry = DPAA2_ETH_TX_CONG_ENTRY_THRESH;
-+		notif_cfg.threshold_exit = DPAA2_ETH_TX_CONG_EXIT_THRESH;
-+		notif_cfg.message_ctx = (u64)priv;
-+		notif_cfg.message_iova = priv->cscn_dma;
-+		notif_cfg.notification_mode = DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
-+					      DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
-+					      DPNI_CONG_OPT_COHERENT_WRITE;
-+		err = dpni_set_congestion_notification(priv->mc_io, 0,
-+						       priv->mc_token,
-+						       DPNI_QUEUE_TX, tc_id,
-+						       &notif_cfg);
-+		if (err) {
-+			netdev_err(priv->net_dev, "Error enabling congestion notifications %d\n",
-+				   err);
-+			return err;
-+		}
-+		break;
-+	}
-+
-+	/* We can zero out the structure in the tx_prio_conf array */
-+	if (type == DPAA2_ETH_DEL_CQ) {
-+		sched_cfg = &sch->prio.tx_prio_cfg.tc_sched[qpri];
-+		memset(sched_cfg, 0, sizeof(*sched_cfg));
-+	}
-+
-+	/* Normalize priorities */
-+	err = dpaa2_eth_normalize_tx_prio(sch);
-+
-+	/* Debug print goes here */
-+	print_hex_dump_debug("tx_prio: ", DUMP_PREFIX_OFFSET, 16, 1,
-+			     &sch->prio.tx_prio_cfg,
-+			     sizeof(sch->prio.tx_prio_cfg), 0);
-+
-+	/* Call dpni_set_tx_priorities for the entire prio qdisc */
-+	err = dpni_set_tx_priorities(priv->mc_io, 0, priv->mc_token,
-+				     &sch->prio.tx_prio_cfg);
-+	if (err)
-+		netdev_err(priv->net_dev, "dpni_set_tx_priorities err %d\n",
-+			   err);
-+
-+	return err;
-+}
-+
-+static void dpaa2_eth_ceetm_enable(struct dpaa2_eth_priv *priv)
-+{
-+	priv->ceetm_en = true;
-+}
-+
-+static void dpaa2_eth_ceetm_disable(struct dpaa2_eth_priv *priv)
-+{
-+	priv->ceetm_en = false;
-+}
-+
-+/* Find class in qdisc hash table using given handle */
-+static inline struct dpaa2_ceetm_class *dpaa2_ceetm_find(u32 handle,
-+							 struct Qdisc *sch)
-+{
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct Qdisc_class_common *clc;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : find class %X in qdisc %X\n",
-+		 __func__, handle, sch->handle);
-+
-+	clc = qdisc_class_find(&priv->clhash, handle);
-+	return clc ? container_of(clc, struct dpaa2_ceetm_class, common) : NULL;
-+}
-+
-+/* Insert a class in the qdisc's class hash */
-+static void dpaa2_ceetm_link_class(struct Qdisc *sch,
-+				   struct Qdisc_class_hash *clhash,
-+				   struct Qdisc_class_common *common)
-+{
-+	sch_tree_lock(sch);
-+	qdisc_class_hash_insert(clhash, common);
-+	sch_tree_unlock(sch);
-+	qdisc_class_hash_grow(sch, clhash);
-+}
-+
-+/* Destroy a ceetm class */
-+static void dpaa2_ceetm_cls_destroy(struct Qdisc *sch,
-+				    struct dpaa2_ceetm_class *cl)
-+{
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct dpaa2_eth_priv *priv = netdev_priv(dev);
-+
-+	if (!cl)
-+		return;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : destroy class %X from under %X\n",
-+		 __func__, cl->common.classid, sch->handle);
-+
-+	/* Recurse into child first */
-+	if (cl->child) {
-+		qdisc_destroy(cl->child);
-+		cl->child = NULL;
-+	}
-+
-+	switch (cl->type) {
-+	case CEETM_ROOT:
-+		if (dpaa2_eth_reset_ch_shaping(priv, cl->root.ch_id))
-+			netdev_err(dev, "Error resetting channel shaping\n");
-+
-+		break;
-+
-+	case CEETM_PRIO:
-+		if (dpaa2_eth_update_tx_prio(priv, cl, DPAA2_ETH_DEL_CQ))
-+			netdev_err(dev, "Error resetting tx_priorities\n");
-+
-+		if (cl->prio.cstats)
-+			free_percpu(cl->prio.cstats);
-+
-+		break;
-+	}
-+
-+	tcf_block_put(cl->block);
-+	kfree(cl);
-+}
-+
-+/* Destroy a ceetm qdisc */
-+static void dpaa2_ceetm_destroy(struct Qdisc *sch)
-+{
-+	unsigned int i;
-+	struct hlist_node *next;
-+	struct dpaa2_ceetm_class *cl;
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct dpaa2_eth_priv *priv_eth = netdev_priv(dev);
-+
-+	pr_debug(KBUILD_BASENAME " : %s : destroy qdisc %X\n",
-+		 __func__, sch->handle);
-+
-+	/* All filters need to be removed before destroying the classes */
-+	tcf_block_put(priv->block);
-+
-+	for (i = 0; i < priv->clhash.hashsize; i++) {
-+		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode)
-+			tcf_block_put(cl->block);
-+	}
-+
-+	for (i = 0; i < priv->clhash.hashsize; i++) {
-+		hlist_for_each_entry_safe(cl, next, &priv->clhash.hash[i],
-+					  common.hnode)
-+			dpaa2_ceetm_cls_destroy(sch, cl);
-+	}
-+
-+	qdisc_class_hash_destroy(&priv->clhash);
-+
-+	switch (priv->type) {
-+	case CEETM_ROOT:
-+		dpaa2_eth_ceetm_disable(priv_eth);
-+
-+		if (priv->root.qstats)
-+			free_percpu(priv->root.qstats);
-+
-+		if (!priv->root.qdiscs)
-+			break;
-+
-+		/* Destroy the pfifo qdiscs in case they haven't been attached
-+		 * to the netdev queues yet.
-+		 */
-+		for (i = 0; i < dev->num_tx_queues; i++)
-+			if (priv->root.qdiscs[i])
-+				qdisc_destroy(priv->root.qdiscs[i]);
-+
-+		kfree(priv->root.qdiscs);
-+		break;
-+
-+	case CEETM_PRIO:
-+		if (priv->prio.parent)
-+			priv->prio.parent->child = NULL;
-+		break;
-+	}
-+}
-+
-+static int dpaa2_ceetm_dump(struct Qdisc *sch, struct sk_buff *skb)
-+{
-+	struct Qdisc *qdisc;
-+	unsigned int ntx, i;
-+	struct nlattr *nest;
-+	struct dpaa2_ceetm_tc_qopt qopt;
-+	struct dpaa2_ceetm_qdisc_stats *qstats;
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+
-+	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
-+
-+	sch_tree_lock(sch);
-+	memset(&qopt, 0, sizeof(qopt));
-+	qopt.type = priv->type;
-+	qopt.shaped = priv->shaped;
-+
-+	switch (priv->type) {
-+	case CEETM_ROOT:
-+		/* Gather statistics from the underlying pfifo qdiscs */
-+		sch->q.qlen = 0;
-+		memset(&sch->bstats, 0, sizeof(sch->bstats));
-+		memset(&sch->qstats, 0, sizeof(sch->qstats));
-+
-+		for (ntx = 0; ntx < dev->num_tx_queues; ntx++) {
-+			qdisc = netdev_get_tx_queue(dev, ntx)->qdisc_sleeping;
-+			sch->q.qlen		+= qdisc->q.qlen;
-+			sch->bstats.bytes	+= qdisc->bstats.bytes;
-+			sch->bstats.packets	+= qdisc->bstats.packets;
-+			sch->qstats.qlen	+= qdisc->qstats.qlen;
-+			sch->qstats.backlog	+= qdisc->qstats.backlog;
-+			sch->qstats.drops	+= qdisc->qstats.drops;
-+			sch->qstats.requeues	+= qdisc->qstats.requeues;
-+			sch->qstats.overlimits	+= qdisc->qstats.overlimits;
-+		}
-+
-+		for_each_online_cpu(i) {
-+			qstats = per_cpu_ptr(priv->root.qstats, i);
-+			sch->qstats.drops += qstats->drops;
-+		}
-+
-+		break;
-+
-+	case CEETM_PRIO:
-+		qopt.prio_group_A = priv->prio.tx_prio_cfg.prio_group_A;
-+		qopt.prio_group_B = priv->prio.tx_prio_cfg.prio_group_B;
-+		qopt.separate_groups = priv->prio.tx_prio_cfg.separate_groups;
-+		break;
-+
-+	default:
-+		pr_err(KBUILD_BASENAME " : %s : invalid qdisc\n", __func__);
-+		sch_tree_unlock(sch);
-+		return -EINVAL;
-+	}
-+
-+	nest = nla_nest_start(skb, TCA_OPTIONS);
-+	if (!nest)
-+		goto nla_put_failure;
-+	if (nla_put(skb, DPAA2_CEETM_TCA_QOPS, sizeof(qopt), &qopt))
-+		goto nla_put_failure;
-+	nla_nest_end(skb, nest);
-+
-+	sch_tree_unlock(sch);
-+	return skb->len;
-+
-+nla_put_failure:
-+	sch_tree_unlock(sch);
-+	nla_nest_cancel(skb, nest);
-+	return -EMSGSIZE;
-+}
-+
-+static int dpaa2_ceetm_change_prio(struct Qdisc *sch,
-+				   struct dpaa2_ceetm_qdisc *priv,
-+				   struct dpaa2_ceetm_tc_qopt *qopt)
-+{
-+	/* TODO: Once LX2 support is added */
-+	/* priv->shaped = parent_cl->shaped; */
-+	priv->prio.tx_prio_cfg.prio_group_A = qopt->prio_group_A;
-+	priv->prio.tx_prio_cfg.prio_group_B = qopt->prio_group_B;
-+	priv->prio.tx_prio_cfg.separate_groups = qopt->separate_groups;
-+
-+	return 0;
-+}
-+
-+/* Edit a ceetm qdisc */
-+static int dpaa2_ceetm_change(struct Qdisc *sch, struct nlattr *opt)
-+{
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct nlattr *tb[DPAA2_CEETM_TCA_QOPS + 1];
-+	struct dpaa2_ceetm_tc_qopt *qopt;
-+	int err;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
-+
-+	err = nla_parse_nested(tb, DPAA2_CEETM_TCA_QOPS, opt,
-+			       dpaa2_ceetm_policy, NULL);
-+	if (err < 0) {
-+		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
-+		       "nla_parse_nested");
-+		return err;
-+	}
-+
-+	if (!tb[DPAA2_CEETM_TCA_QOPS]) {
-+		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
-+		       "tb");
-+		return -EINVAL;
-+	}
-+
-+	if (TC_H_MIN(sch->handle)) {
-+		pr_err("CEETM: a qdisc should not have a minor\n");
-+		return -EINVAL;
-+	}
-+
-+	qopt = nla_data(tb[DPAA2_CEETM_TCA_QOPS]);
-+
-+	if (priv->type != qopt->type) {
-+		pr_err("CEETM: qdisc %X is not of the provided type\n",
-+		       sch->handle);
-+		return -EINVAL;
-+	}
-+
-+	switch (priv->type) {
-+	case CEETM_PRIO:
-+		err = dpaa2_ceetm_change_prio(sch, priv, qopt);
-+		break;
-+	default:
-+		pr_err(KBUILD_BASENAME " : %s : invalid qdisc\n", __func__);
-+		err = -EINVAL;
-+	}
-+
-+	return err;
-+}
-+
-+/* Configure a root ceetm qdisc */
-+static int dpaa2_ceetm_init_root(struct Qdisc *sch,
-+				 struct dpaa2_ceetm_qdisc *priv,
-+				 struct dpaa2_ceetm_tc_qopt *qopt)
-+{
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct dpaa2_eth_priv *priv_eth = netdev_priv(dev);
-+	struct netdev_queue *dev_queue;
-+	unsigned int i, parent_id;
-+	struct Qdisc *qdisc;
-+	int err;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
-+
-+	/* Validate inputs */
-+	if (sch->parent != TC_H_ROOT) {
-+		pr_err("CEETM: a root ceetm qdisc can not be attached to a class\n");
-+		tcf_block_put(priv->block);
-+		qdisc_class_hash_destroy(&priv->clhash);
-+		return -EINVAL;
-+	}
-+
-+	/* Pre-allocate underlying pfifo qdiscs.
-+	 *
-+	 * We want to offload shaping and scheduling decisions to the hardware.
-+	 * The pfifo qdiscs will be attached to the netdev queues and will
-+	 * guide the traffic from the IP stack down to the driver with minimum
-+	 * interference.
-+	 *
-+	 * The CEETM qdiscs and classes will be crossed when the traffic
-+	 * reaches the driver.
-+	 */
-+	priv->root.qdiscs = kcalloc(dev->num_tx_queues,
-+				    sizeof(priv->root.qdiscs[0]),
-+				    GFP_KERNEL);
-+	if (!priv->root.qdiscs) {
-+		err = -ENOMEM;
-+		goto err_init_root;
-+	}
-+
-+	for (i = 0; i < dev->num_tx_queues; i++) {
-+		dev_queue = netdev_get_tx_queue(dev, i);
-+		parent_id = TC_H_MAKE(TC_H_MAJ(sch->handle),
-+				      TC_H_MIN(i + PFIFO_MIN_OFFSET));
-+
-+		qdisc = qdisc_create_dflt(dev_queue, &pfifo_qdisc_ops,
-+					  parent_id);
-+		if (!qdisc) {
-+			err = -ENOMEM;
-+			goto err_init_root;
-+		}
-+
-+		priv->root.qdiscs[i] = qdisc;
-+		qdisc->flags |= TCQ_F_ONETXQUEUE;
-+	}
-+
-+	sch->flags |= TCQ_F_MQROOT;
-+
-+	priv->root.qstats = alloc_percpu(struct dpaa2_ceetm_qdisc_stats);
-+	if (!priv->root.qstats) {
-+		pr_err(KBUILD_BASENAME " : %s : alloc_percpu() failed\n",
-+		       __func__);
-+		err = -ENOMEM;
-+		goto err_init_root;
-+	}
-+
-+	dpaa2_eth_ceetm_enable(priv_eth);
-+	return 0;
-+
-+err_init_root:
-+	dpaa2_ceetm_destroy(sch);
-+	return err;
-+}
-+
-+/* Configure a prio ceetm qdisc */
-+static int dpaa2_ceetm_init_prio(struct Qdisc *sch,
-+				 struct dpaa2_ceetm_qdisc *priv,
-+				 struct dpaa2_ceetm_tc_qopt *qopt)
-+{
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct dpaa2_ceetm_class *parent_cl;
-+	struct Qdisc *parent_qdisc;
-+	int err;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
-+
-+	if (sch->parent == TC_H_ROOT) {
-+		pr_err("CEETM: a prio ceetm qdisc can not be root\n");
-+		err = -EINVAL;
-+		goto err_init_prio;
-+	}
-+
-+	parent_qdisc = qdisc_lookup(dev, TC_H_MAJ(sch->parent));
-+	if (strcmp(parent_qdisc->ops->id, dpaa2_ceetm_qdisc_ops.id)) {
-+		pr_err("CEETM: a ceetm qdisc can not be attached to other qdisc/class types\n");
-+		err = -EINVAL;
-+		goto err_init_prio;
-+	}
-+
-+	/* Obtain the parent root ceetm_class */
-+	parent_cl = dpaa2_ceetm_find(sch->parent, parent_qdisc);
-+
-+	if (!parent_cl || parent_cl->type != CEETM_ROOT) {
-+		pr_err("CEETM: a prio ceetm qdiscs can be added only under a root ceetm class\n");
-+		err = -EINVAL;
-+		goto err_init_prio;
-+	}
-+
-+	priv->prio.parent = parent_cl;
-+	parent_cl->child = sch;
-+
-+	err = dpaa2_ceetm_change_prio(sch, priv, qopt);
-+
-+	return 0;
-+
-+err_init_prio:
-+	dpaa2_ceetm_destroy(sch);
-+	return err;
-+}
-+
-+/* Configure a generic ceetm qdisc */
-+static int dpaa2_ceetm_init(struct Qdisc *sch, struct nlattr *opt)
-+{
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct nlattr *tb[DPAA2_CEETM_TCA_QOPS + 1];
-+	struct dpaa2_ceetm_tc_qopt *qopt;
-+	int err;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
-+
-+	if (!netif_is_multiqueue(dev))
-+		return -EOPNOTSUPP;
-+
-+	err = tcf_block_get(&priv->block, &priv->filter_list);
-+	if (err) {
-+		pr_err("CEETM: unable to get tcf_block\n");
-+		return err;
-+	}
-+
-+	if (!opt) {
-+		pr_err(KBUILD_BASENAME " : %s : tc error - opt = NULL\n",
-+		       __func__);
-+		return -EINVAL;
-+	}
-+
-+	err = nla_parse_nested(tb, DPAA2_CEETM_TCA_QOPS, opt,
-+			       dpaa2_ceetm_policy, NULL);
-+	if (err < 0) {
-+		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
-+		       "nla_parse_nested");
-+		return err;
-+	}
-+
-+	if (!tb[DPAA2_CEETM_TCA_QOPS]) {
-+		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
-+		       "tb");
-+		return -EINVAL;
-+	}
-+
-+	if (TC_H_MIN(sch->handle)) {
-+		pr_err("CEETM: a qdisc should not have a minor\n");
-+		return -EINVAL;
-+	}
-+
-+	qopt = nla_data(tb[DPAA2_CEETM_TCA_QOPS]);
-+
-+	/* Initialize the class hash list. Each qdisc has its own class hash */
-+	err = qdisc_class_hash_init(&priv->clhash);
-+	if (err < 0) {
-+		pr_err(KBUILD_BASENAME " : %s : qdisc_class_hash_init failed\n",
-+		       __func__);
-+		return err;
-+	}
-+
-+	priv->type = qopt->type;
-+	priv->shaped = qopt->shaped;
-+
-+	switch (priv->type) {
-+	case CEETM_ROOT:
-+		err = dpaa2_ceetm_init_root(sch, priv, qopt);
-+		break;
-+	case CEETM_PRIO:
-+		err = dpaa2_ceetm_init_prio(sch, priv, qopt);
-+		break;
-+	default:
-+		pr_err(KBUILD_BASENAME " : %s : invalid qdisc\n", __func__);
-+		dpaa2_ceetm_destroy(sch);
-+		err = -EINVAL;
-+	}
-+
-+	return err;
-+}
-+
-+/* Attach the underlying pfifo qdiscs */
-+static void dpaa2_ceetm_attach(struct Qdisc *sch)
-+{
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct Qdisc *qdisc, *old_qdisc;
-+	unsigned int i;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
-+
-+	for (i = 0; i < dev->num_tx_queues; i++) {
-+		qdisc = priv->root.qdiscs[i];
-+		old_qdisc = dev_graft_qdisc(qdisc->dev_queue, qdisc);
-+		if (old_qdisc)
-+			qdisc_destroy(old_qdisc);
-+	}
-+
-+	/* Remove the references to the pfifo qdiscs since the kernel will
-+	 * destroy them when needed. No cleanup from our part is required from
-+	 * this point on.
-+	 */
-+	kfree(priv->root.qdiscs);
-+	priv->root.qdiscs = NULL;
-+}
-+
-+static unsigned long dpaa2_ceetm_cls_find(struct Qdisc *sch, u32 classid)
-+{
-+	struct dpaa2_ceetm_class *cl;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : classid %X from qdisc %X\n",
-+		 __func__, classid, sch->handle);
-+	cl = dpaa2_ceetm_find(classid, sch);
-+
-+	return (unsigned long)cl;
-+}
-+
-+static int dpaa2_ceetm_cls_change_root(struct dpaa2_ceetm_class *cl,
-+				       struct dpaa2_ceetm_tc_copt *copt,
-+				       struct net_device *dev)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(dev);
-+	struct dpni_tx_shaping_cfg scfg = { 0 }, ecfg = { 0 };
-+	int err = 0;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : class %X\n", __func__,
-+		 cl->common.classid);
-+
-+	if (!cl->shaped)
-+		return 0;
-+
-+	if (dpaa2_eth_update_shaping_cfg(dev, copt->shaping_cfg,
-+					 &scfg, &ecfg))
-+		return -EINVAL;
-+
-+	err = dpaa2_eth_set_ch_shaping(priv, &scfg, &ecfg,
-+				       copt->shaping_cfg.coupled,
-+				       cl->root.ch_id);
-+	if (err)
-+		return err;
-+
-+	memcpy(&cl->root.shaping_cfg, &copt->shaping_cfg,
-+	       sizeof(struct dpaa2_ceetm_shaping_cfg));
-+
-+	return err;
-+}
-+
-+static int dpaa2_ceetm_cls_change_prio(struct dpaa2_ceetm_class *cl,
-+				       struct dpaa2_ceetm_tc_copt *copt,
-+				       struct net_device *dev)
-+{
-+	struct dpaa2_ceetm_qdisc *sch = qdisc_priv(cl->parent);
-+	struct dpni_tx_schedule_cfg *sched_cfg;
-+	struct dpaa2_eth_priv *priv = netdev_priv(dev);
-+	int err;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : class %X mode %d weight %d\n",
-+		 __func__, cl->common.classid, copt->mode, copt->weight);
-+
-+	if (!cl->prio.cstats) {
-+		cl->prio.cstats = alloc_percpu(struct dpaa2_ceetm_class_stats);
-+		if (!cl->prio.cstats) {
-+			pr_err(KBUILD_BASENAME " : %s : alloc_percpu() failed\n",
-+			       __func__);
-+			return -ENOMEM;
-+		}
-+	}
-+
-+	cl->prio.mode = copt->mode;
-+	cl->prio.weight = copt->weight;
-+
-+	sched_cfg = &sch->prio.tx_prio_cfg.tc_sched[cl->prio.qpri];
-+
-+	switch (copt->mode) {
-+	case STRICT_PRIORITY:
-+		sched_cfg->mode = DPNI_TX_SCHED_STRICT_PRIORITY;
-+		break;
-+	case WEIGHTED_A:
-+		sched_cfg->mode = DPNI_TX_SCHED_WEIGHTED_A;
-+		break;
-+	case WEIGHTED_B:
-+		sched_cfg->mode = DPNI_TX_SCHED_WEIGHTED_B;
-+		break;
-+	}
-+
-+	err = dpaa2_eth_update_tx_prio(priv, cl, DPAA2_ETH_ADD_CQ);
-+
-+	return err;
-+}
-+
-+/* Add a new ceetm class */
-+static int dpaa2_ceetm_cls_add(struct Qdisc *sch, u32 classid,
-+			       struct dpaa2_ceetm_tc_copt *copt,
-+			       unsigned long *arg)
-+{
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct dpaa2_eth_priv *priv_eth = netdev_priv(dev);
-+	struct dpaa2_ceetm_class *cl;
-+	int err;
-+
-+	if (copt->type == CEETM_ROOT &&
-+	    priv->clhash.hashelems == dpaa2_eth_ch_count(priv_eth)) {
-+		pr_err("CEETM: only %d channel%s per DPNI allowed, sorry\n",
-+		       dpaa2_eth_ch_count(priv_eth),
-+		       dpaa2_eth_ch_count(priv_eth) == 1 ? "" : "s");
-+		return -EINVAL;
-+	}
-+
-+	if (copt->type == CEETM_PRIO &&
-+	    priv->clhash.hashelems == dpaa2_eth_tc_count(priv_eth)) {
-+		pr_err("CEETM: only %d queue%s per channel allowed, sorry\n",
-+		       dpaa2_eth_tc_count(priv_eth),
-+		       dpaa2_eth_tc_count(priv_eth) == 1 ? "" : "s");
-+		return -EINVAL;
-+	}
-+
-+	cl = kzalloc(sizeof(*cl), GFP_KERNEL);
-+	if (!cl)
-+		return -ENOMEM;
-+
-+	err = tcf_block_get(&cl->block, &cl->filter_list);
-+	if (err) {
-+		pr_err("%s: Unable to set new root class\n", __func__);
-+		goto out_free;
-+	}
-+
-+	cl->common.classid = classid;
-+	cl->parent = sch;
-+	cl->child = NULL;
-+
-+	/* Add class handle in Qdisc */
-+	dpaa2_ceetm_link_class(sch, &priv->clhash, &cl->common);
-+
-+	cl->shaped = copt->shaped;
-+	cl->type = copt->type;
-+
-+	/* Claim a CEETM channel / tc - DPAA2. will assume transition from
-+	 * classid to qdid/qpri, starting from qdid / qpri 0
-+	 */
-+	switch (copt->type) {
-+	case CEETM_ROOT:
-+		cl->root.ch_id = classid - sch->handle - 1;
-+		err = dpaa2_ceetm_cls_change_root(cl, copt, dev);
-+		break;
-+	case CEETM_PRIO:
-+		cl->prio.qpri = classid - sch->handle - 1;
-+		err = dpaa2_ceetm_cls_change_prio(cl, copt, dev);
-+		break;
-+	}
-+
-+	if (err) {
-+		pr_err("%s: Unable to set new %s class\n", __func__,
-+		       (copt->type == CEETM_ROOT ? "root" : "prio"));
-+		goto out_free;
-+	}
-+
-+	switch (copt->type) {
-+	case CEETM_ROOT:
-+		pr_debug(KBUILD_BASENAME " : %s : configured root class %X associated with channel qdid %d\n",
-+			 __func__, classid, cl->root.ch_id);
-+		break;
-+	case CEETM_PRIO:
-+		pr_debug(KBUILD_BASENAME " : %s : configured prio class %X associated with queue qpri %d\n",
-+			 __func__, classid, cl->prio.qpri);
-+		break;
-+	}
-+
-+	*arg = (unsigned long)cl;
-+	return 0;
-+
-+out_free:
-+	kfree(cl);
-+	return err;
-+}
-+
-+/* Add or configure a ceetm class */
-+static int dpaa2_ceetm_cls_change(struct Qdisc *sch, u32 classid, u32 parentid,
-+				  struct nlattr **tca, unsigned long *arg)
-+{
-+	struct dpaa2_ceetm_qdisc *priv;
-+	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)*arg;
-+	struct nlattr *opt = tca[TCA_OPTIONS];
-+	struct nlattr *tb[DPAA2_CEETM_TCA_MAX];
-+	struct dpaa2_ceetm_tc_copt *copt;
-+	struct net_device *dev = qdisc_dev(sch);
-+	int err;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : classid %X under qdisc %X\n",
-+		 __func__, classid, sch->handle);
-+
-+	if (strcmp(sch->ops->id, dpaa2_ceetm_qdisc_ops.id)) {
-+		pr_err("CEETM: a ceetm class can not be attached to other qdisc/class types\n");
-+		return -EINVAL;
-+	}
-+
-+	priv = qdisc_priv(sch);
-+
-+	if (!opt) {
-+		pr_err(KBUILD_BASENAME " : %s : tc error NULL opt\n", __func__);
-+		return -EINVAL;
-+	}
-+
-+	err = nla_parse_nested(tb, DPAA2_CEETM_TCA_COPT, opt,
-+			       dpaa2_ceetm_policy, NULL);
-+	if (err < 0) {
-+		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
-+		       "nla_parse_nested");
-+		return -EINVAL;
-+	}
-+
-+	if (!tb[DPAA2_CEETM_TCA_COPT]) {
-+		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
-+		       "tb");
-+		return -EINVAL;
-+	}
-+
-+	copt = nla_data(tb[DPAA2_CEETM_TCA_COPT]);
-+
-+	/* Configure an existing ceetm class */
-+	if (cl) {
-+		if (copt->type != cl->type) {
-+			pr_err("CEETM: class %X is not of the provided type\n",
-+			       cl->common.classid);
-+			return -EINVAL;
-+		}
-+
-+		switch (copt->type) {
-+		case CEETM_ROOT:
-+			return dpaa2_ceetm_cls_change_root(cl, copt, dev);
-+		case CEETM_PRIO:
-+			return dpaa2_ceetm_cls_change_prio(cl, copt, dev);
-+
-+		default:
-+			pr_err(KBUILD_BASENAME " : %s : invalid class\n",
-+			       __func__);
-+			return -EINVAL;
-+		}
-+	}
-+
-+	return dpaa2_ceetm_cls_add(sch, classid, copt, arg);
-+}
-+
-+static void dpaa2_ceetm_cls_walk(struct Qdisc *sch, struct qdisc_walker *arg)
-+{
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct dpaa2_ceetm_class *cl;
-+	unsigned int i;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
-+
-+	if (arg->stop)
-+		return;
-+
-+	for (i = 0; i < priv->clhash.hashsize; i++) {
-+		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode) {
-+			if (arg->count < arg->skip) {
-+				arg->count++;
-+				continue;
-+			}
-+			if (arg->fn(sch, (unsigned long)cl, arg) < 0) {
-+				arg->stop = 1;
-+				return;
-+			}
-+			arg->count++;
-+		}
-+	}
-+}
-+
-+static int dpaa2_ceetm_cls_dump(struct Qdisc *sch, unsigned long arg,
-+				struct sk_buff *skb, struct tcmsg *tcm)
-+{
-+	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
-+	struct nlattr *nest;
-+	struct dpaa2_ceetm_tc_copt copt;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n",
-+		 __func__, cl->common.classid, sch->handle);
-+
-+	sch_tree_lock(sch);
-+
-+	tcm->tcm_parent = ((struct Qdisc *)cl->parent)->handle;
-+	tcm->tcm_handle = cl->common.classid;
-+
-+	memset(&copt, 0, sizeof(copt));
-+
-+	copt.shaped = cl->shaped;
-+	copt.type = cl->type;
-+
-+	switch (cl->type) {
-+	case CEETM_ROOT:
-+		if (cl->child)
-+			tcm->tcm_info = cl->child->handle;
-+
-+		memcpy(&copt.shaping_cfg, &cl->root.shaping_cfg,
-+		       sizeof(struct dpaa2_ceetm_shaping_cfg));
-+
-+		break;
-+
-+	case CEETM_PRIO:
-+		if (cl->child)
-+			tcm->tcm_info = cl->child->handle;
-+
-+		copt.mode = cl->prio.mode;
-+		copt.weight = cl->prio.weight;
-+
-+		break;
-+	}
-+
-+	nest = nla_nest_start(skb, TCA_OPTIONS);
-+	if (!nest)
-+		goto nla_put_failure;
-+	if (nla_put(skb, DPAA2_CEETM_TCA_COPT, sizeof(copt), &copt))
-+		goto nla_put_failure;
-+	nla_nest_end(skb, nest);
-+	sch_tree_unlock(sch);
-+	return skb->len;
-+
-+nla_put_failure:
-+	sch_tree_unlock(sch);
-+	nla_nest_cancel(skb, nest);
-+	return -EMSGSIZE;
-+}
-+
-+static int dpaa2_ceetm_cls_delete(struct Qdisc *sch, unsigned long arg)
-+{
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n",
-+		 __func__, cl->common.classid, sch->handle);
-+
-+	sch_tree_lock(sch);
-+	qdisc_class_hash_remove(&priv->clhash, &cl->common);
-+	sch_tree_unlock(sch);
-+	return 0;
-+}
-+
-+/* Get the class' child qdisc, if any */
-+static struct Qdisc *dpaa2_ceetm_cls_leaf(struct Qdisc *sch, unsigned long arg)
-+{
-+	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n",
-+		 __func__, cl->common.classid, sch->handle);
-+
-+	switch (cl->type) {
-+	case CEETM_ROOT:
-+	case CEETM_PRIO:
-+		return cl->child;
-+	}
-+
-+	return NULL;
-+}
-+
-+static int dpaa2_ceetm_cls_graft(struct Qdisc *sch, unsigned long arg,
-+				 struct Qdisc *new, struct Qdisc **old)
-+{
-+	if (new && strcmp(new->ops->id, dpaa2_ceetm_qdisc_ops.id)) {
-+		pr_err("CEETM: only ceetm qdiscs can be attached to ceetm classes\n");
-+		return -EOPNOTSUPP;
-+	}
-+
-+	return 0;
-+}
-+
-+static int dpaa2_ceetm_cls_dump_stats(struct Qdisc *sch, unsigned long arg,
-+				      struct gnet_dump *d)
-+{
-+	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
-+	struct gnet_stats_basic_packed tmp_bstats;
-+	struct dpaa2_ceetm_tc_xstats xstats;
-+	union dpni_statistics dpni_stats;
-+	struct net_device *dev = qdisc_dev(sch);
-+	struct dpaa2_eth_priv *priv_eth = netdev_priv(dev);
-+	u8 ch_id = 0;
-+	int err;
-+
-+	memset(&xstats, 0, sizeof(xstats));
-+	memset(&tmp_bstats, 0, sizeof(tmp_bstats));
-+
-+	if (cl->type == CEETM_ROOT)
-+		return 0;
-+
-+	err = dpni_get_statistics(priv_eth->mc_io, 0, priv_eth->mc_token, 3,
-+				  DPNI_BUILD_CH_TC(ch_id, cl->prio.qpri),
-+				  &dpni_stats);
-+	if (err)
-+		netdev_warn(dev, "dpni_get_stats(%d) failed - %d\n", 3, err);
-+
-+	xstats.ceetm_dequeue_bytes = dpni_stats.page_3.ceetm_dequeue_bytes;
-+	xstats.ceetm_dequeue_frames = dpni_stats.page_3.ceetm_dequeue_frames;
-+	xstats.ceetm_reject_bytes = dpni_stats.page_3.ceetm_reject_bytes;
-+	xstats.ceetm_reject_frames = dpni_stats.page_3.ceetm_reject_frames;
-+
-+	return gnet_stats_copy_app(d, &xstats, sizeof(xstats));
-+}
-+
-+static struct tcf_block *dpaa2_ceetm_tcf_block(struct Qdisc *sch,
-+					       unsigned long arg)
-+{
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__,
-+		 cl ? cl->common.classid : 0, sch->handle);
-+	return cl ? cl->block : priv->block;
-+}
-+
-+static unsigned long dpaa2_ceetm_tcf_bind(struct Qdisc *sch,
-+					  unsigned long parent,
-+					  u32 classid)
-+{
-+	struct dpaa2_ceetm_class *cl = dpaa2_ceetm_find(classid, sch);
-+
-+	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__,
-+		 cl ? cl->common.classid : 0, sch->handle);
-+	return (unsigned long)cl;
-+}
-+
-+static void dpaa2_ceetm_tcf_unbind(struct Qdisc *sch, unsigned long arg)
-+{
-+	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
-+
-+	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__,
-+		 cl ? cl->common.classid : 0, sch->handle);
-+}
-+
-+const struct Qdisc_class_ops dpaa2_ceetm_cls_ops = {
-+	.graft		=	dpaa2_ceetm_cls_graft,
-+	.leaf		=	dpaa2_ceetm_cls_leaf,
-+	.find		=	dpaa2_ceetm_cls_find,
-+	.change		=	dpaa2_ceetm_cls_change,
-+	.delete		=	dpaa2_ceetm_cls_delete,
-+	.walk		=	dpaa2_ceetm_cls_walk,
-+	.tcf_block	=	dpaa2_ceetm_tcf_block,
-+	.bind_tcf	=	dpaa2_ceetm_tcf_bind,
-+	.unbind_tcf	=	dpaa2_ceetm_tcf_unbind,
-+	.dump		=	dpaa2_ceetm_cls_dump,
-+	.dump_stats	=	dpaa2_ceetm_cls_dump_stats,
-+};
-+
-+struct Qdisc_ops dpaa2_ceetm_qdisc_ops __read_mostly = {
-+	.id		=	"ceetm",
-+	.priv_size	=	sizeof(struct dpaa2_ceetm_qdisc),
-+	.cl_ops		=	&dpaa2_ceetm_cls_ops,
-+	.init		=	dpaa2_ceetm_init,
-+	.destroy	=	dpaa2_ceetm_destroy,
-+	.change		=	dpaa2_ceetm_change,
-+	.dump		=	dpaa2_ceetm_dump,
-+	.attach		=	dpaa2_ceetm_attach,
-+	.owner		=	THIS_MODULE,
-+};
-+
-+/* Run the filters and classifiers attached to the qdisc on the provided skb */
-+int dpaa2_ceetm_classify(struct sk_buff *skb, struct Qdisc *sch,
-+			 int *qdid, u8 *qpri)
-+{
-+	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
-+	struct dpaa2_ceetm_class *cl = NULL;
-+	struct tcf_result res;
-+	struct tcf_proto *tcf;
-+	int result;
-+
-+	tcf = rcu_dereference_bh(priv->filter_list);
-+	while (tcf && (result = tcf_classify(skb, tcf, &res, false)) >= 0) {
-+#ifdef CONFIG_NET_CLS_ACT
-+		switch (result) {
-+		case TC_ACT_QUEUED:
-+		case TC_ACT_STOLEN:
-+		case TC_ACT_SHOT:
-+			/* No valid class found due to action */
-+			return -1;
-+		}
-+#endif
-+		cl = (void *)res.class;
-+		if (!cl) {
-+			/* The filter leads to the qdisc */
-+			if (res.classid == sch->handle)
-+				return 0;
-+
-+			cl = dpaa2_ceetm_find(res.classid, sch);
-+			/* The filter leads to an invalid class */
-+			if (!cl)
-+				break;
-+		}
-+
-+		/* The class might have its own filters attached */
-+		tcf = rcu_dereference_bh(cl->filter_list);
-+	}
-+
-+	/* No valid class found */
-+	if (!cl)
-+		return 0;
-+
-+	switch (cl->type) {
-+	case CEETM_ROOT:
-+		*qdid = cl->root.ch_id;
-+
-+		/* The root class does not have a child prio qdisc */
-+		if (!cl->child)
-+			return 0;
-+
-+		/* Run the prio qdisc classifiers */
-+		return dpaa2_ceetm_classify(skb, cl->child, qdid, qpri);
-+
-+	case CEETM_PRIO:
-+		*qpri = cl->prio.qpri;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+int __init dpaa2_ceetm_register(void)
-+{
-+	int err = 0;
-+
-+	pr_debug(KBUILD_MODNAME ": " DPAA2_CEETM_DESCRIPTION "\n");
-+
-+	err = register_qdisc(&dpaa2_ceetm_qdisc_ops);
-+	if (unlikely(err))
-+		pr_err(KBUILD_MODNAME
-+		       ": %s:%hu:%s(): register_qdisc() = %d\n",
-+		       KBUILD_BASENAME ".c", __LINE__, __func__, err);
-+
-+	return err;
-+}
-+
-+void __exit dpaa2_ceetm_unregister(void)
-+{
-+	pr_debug(KBUILD_MODNAME ": %s:%s() ->\n",
-+		 KBUILD_BASENAME ".c", __func__);
-+
-+	unregister_qdisc(&dpaa2_ceetm_qdisc_ops);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-ceetm.h
-@@ -0,0 +1,183 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+/*
-+ * Copyright 2017 NXP
-+ *
-+ */
-+
-+#ifndef __DPAA2_ETH_CEETM_H
-+#define __DPAA2_ETH_CEETM_H
-+
-+#include <net/pkt_sched.h>
-+#include <net/pkt_cls.h>
-+#include <net/netlink.h>
-+
-+#include "dpaa2-eth.h"
-+
-+/* For functional purposes, there are num_tx_queues pfifo qdiscs through which
-+ * frames reach the driver. Their handles start from 1:21. Handles 1:1 to 1:20
-+ * are reserved for the maximum 32 CEETM channels (majors and minors are in
-+ * hex).
-+ */
-+#define PFIFO_MIN_OFFSET		0x21
-+
-+#define DPAA2_CEETM_MIN_WEIGHT		100
-+#define DPAA2_CEETM_MAX_WEIGHT		24800
-+
-+#define DPAA2_CEETM_TD_THRESHOLD	1000
-+
-+enum wbfs_group_type {
-+	WBFS_GRP_A,
-+	WBFS_GRP_B,
-+	WBFS_GRP_LARGE
-+};
-+
-+enum {
-+	DPAA2_CEETM_TCA_UNSPEC,
-+	DPAA2_CEETM_TCA_COPT,
-+	DPAA2_CEETM_TCA_QOPS,
-+	DPAA2_CEETM_TCA_MAX,
-+};
-+
-+/* CEETM configuration types */
-+enum dpaa2_ceetm_type {
-+	CEETM_ROOT = 1,
-+	CEETM_PRIO,
-+};
-+
-+enum {
-+	STRICT_PRIORITY = 0,
-+	WEIGHTED_A,
-+	WEIGHTED_B,
-+};
-+
-+struct dpaa2_ceetm_shaping_cfg {
-+	__u64 cir; /* committed information rate */
-+	__u64 eir; /* excess information rate */
-+	__u16 cbs; /* committed burst size */
-+	__u16 ebs; /* excess burst size */
-+	__u8 coupled; /* shaper coupling */
-+};
-+
-+extern const struct nla_policy ceetm_policy[DPAA2_CEETM_TCA_MAX];
-+
-+struct dpaa2_ceetm_class;
-+struct dpaa2_ceetm_qdisc_stats;
-+struct dpaa2_ceetm_class_stats;
-+
-+/* corresponds to CEETM shaping at LNI level */
-+struct dpaa2_root_q {
-+	struct Qdisc **qdiscs;
-+	struct dpaa2_ceetm_qdisc_stats __percpu *qstats;
-+};
-+
-+/* corresponds to the number of priorities a channel serves */
-+struct dpaa2_prio_q {
-+	struct dpaa2_ceetm_class *parent;
-+	struct dpni_tx_priorities_cfg tx_prio_cfg;
-+};
-+
-+struct dpaa2_ceetm_qdisc {
-+	struct Qdisc_class_hash clhash;
-+	struct tcf_proto *filter_list; /* qdisc attached filters */
-+	struct tcf_block *block;
-+
-+	enum dpaa2_ceetm_type type; /* ROOT/PRIO */
-+	bool shaped;
-+	union {
-+		struct dpaa2_root_q root;
-+		struct dpaa2_prio_q prio;
-+	};
-+};
-+
-+/* CEETM Qdisc configuration parameters */
-+struct dpaa2_ceetm_tc_qopt {
-+	enum dpaa2_ceetm_type type;
-+	__u16 shaped;
-+	__u8 prio_group_A;
-+	__u8 prio_group_B;
-+	__u8 separate_groups;
-+};
-+
-+/* root class - corresponds to a channel */
-+struct dpaa2_root_c {
-+	struct dpaa2_ceetm_shaping_cfg shaping_cfg;
-+	u32 ch_id;
-+};
-+
-+/* prio class - corresponds to a strict priority queue (group) */
-+struct dpaa2_prio_c {
-+	struct dpaa2_ceetm_class_stats __percpu *cstats;
-+	u32 qpri;
-+	u8 mode;
-+	u16 weight;
-+};
-+
-+struct dpaa2_ceetm_class {
-+	struct Qdisc_class_common common;
-+	struct tcf_proto *filter_list; /* class attached filters */
-+	struct tcf_block *block;
-+	struct Qdisc *parent;
-+	struct Qdisc *child;
-+
-+	enum dpaa2_ceetm_type type; /* ROOT/PRIO */
-+	bool shaped;
-+	union {
-+		struct dpaa2_root_c root;
-+		struct dpaa2_prio_c prio;
-+	};
-+};
-+
-+/* CEETM Class configuration parameters */
-+struct dpaa2_ceetm_tc_copt {
-+	enum dpaa2_ceetm_type type;
-+	struct dpaa2_ceetm_shaping_cfg shaping_cfg;
-+	__u16 shaped;
-+	__u8 mode;
-+	__u16 weight;
-+};
-+
-+/* CEETM stats */
-+struct dpaa2_ceetm_qdisc_stats {
-+	__u32 drops;
-+};
-+
-+struct dpaa2_ceetm_class_stats {
-+	/* Software counters */
-+	struct gnet_stats_basic_packed bstats;
-+	__u32 ern_drop_count;
-+	__u32 congested_count;
-+};
-+
-+struct dpaa2_ceetm_tc_xstats {
-+	__u64 ceetm_dequeue_bytes;
-+	__u64 ceetm_dequeue_frames;
-+	__u64 ceetm_reject_bytes;
-+	__u64 ceetm_reject_frames;
-+};
-+
-+#ifdef CONFIG_FSL_DPAA2_ETH_CEETM
-+int __init dpaa2_ceetm_register(void);
-+void __exit dpaa2_ceetm_unregister(void);
-+int dpaa2_ceetm_classify(struct sk_buff *skb, struct Qdisc *sch,
-+			 int *qdid, u8 *qpri);
-+#else
-+static inline int dpaa2_ceetm_register(void)
-+{
-+	return 0;
-+}
-+
-+static inline void dpaa2_ceetm_unregister(void) {}
-+
-+static inline int dpaa2_ceetm_classify(struct sk_buff *skb, struct Qdisc *sch,
-+				       int *qdid, u8 *qpri)
-+{
-+	return 0;
-+}
-+#endif
-+
-+static inline bool dpaa2_eth_ceetm_is_enabled(struct dpaa2_eth_priv *priv)
-+{
-+	return priv->ceetm_en;
-+}
-+
-+#endif
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c
-@@ -0,0 +1,357 @@
-+
-+/* Copyright 2015 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the name of Freescale Semiconductor nor the
-+ *	 names of its contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/debugfs.h>
-+#include "dpaa2-eth.h"
-+#include "dpaa2-eth-debugfs.h"
-+
-+#define DPAA2_ETH_DBG_ROOT "dpaa2-eth"
-+
-+static struct dentry *dpaa2_dbg_root;
-+
-+static int dpaa2_dbg_cpu_show(struct seq_file *file, void *offset)
-+{
-+	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
-+	struct rtnl_link_stats64 *stats;
-+	struct dpaa2_eth_drv_stats *extras;
-+	int i;
-+
-+	seq_printf(file, "Per-CPU stats for %s\n", priv->net_dev->name);
-+	seq_printf(file, "%s%16s%16s%16s%16s%16s%16s%16s%16s%16s\n",
-+		   "CPU", "Rx", "Rx Err", "Rx SG", "Tx", "Tx Err", "Tx conf",
-+		   "Tx SG", "Tx realloc", "Enq busy");
-+
-+	for_each_online_cpu(i) {
-+		stats = per_cpu_ptr(priv->percpu_stats, i);
-+		extras = per_cpu_ptr(priv->percpu_extras, i);
-+		seq_printf(file, "%3d%16llu%16llu%16llu%16llu%16llu%16llu%16llu%16llu%16llu\n",
-+			   i,
-+			   stats->rx_packets,
-+			   stats->rx_errors,
-+			   extras->rx_sg_frames,
-+			   stats->tx_packets,
-+			   stats->tx_errors,
-+			   extras->tx_conf_frames,
-+			   extras->tx_sg_frames,
-+			   extras->tx_reallocs,
-+			   extras->tx_portal_busy);
-+	}
-+
-+	return 0;
-+}
-+
-+static int dpaa2_dbg_cpu_open(struct inode *inode, struct file *file)
-+{
-+	int err;
-+	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private;
-+
-+	err = single_open(file, dpaa2_dbg_cpu_show, priv);
-+	if (err < 0)
-+		netdev_err(priv->net_dev, "single_open() failed\n");
-+
-+	return err;
-+}
-+
-+static const struct file_operations dpaa2_dbg_cpu_ops = {
-+	.open = dpaa2_dbg_cpu_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+};
-+
-+static char *fq_type_to_str(struct dpaa2_eth_fq *fq)
-+{
-+	switch (fq->type) {
-+	case DPAA2_RX_FQ:
-+		return "Rx";
-+	case DPAA2_TX_CONF_FQ:
-+		return "Tx conf";
-+	case DPAA2_RX_ERR_FQ:
-+		return "Rx err";
-+	default:
-+		return "N/A";
-+	}
-+}
-+
-+static int dpaa2_dbg_fqs_show(struct seq_file *file, void *offset)
-+{
-+	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
-+	struct dpaa2_eth_fq *fq;
-+	u32 fcnt, bcnt;
-+	int i, err;
-+
-+	seq_printf(file, "non-zero FQ stats for %s:\n", priv->net_dev->name);
-+	seq_printf(file, "%s%16s%16s%16s%16s%16s%16s\n",
-+		   "VFQID", "CPU", "Traffic Class", "Type", "Frames",
-+		   "Pending frames", "Congestion");
-+
-+	for (i = 0; i <  priv->num_fqs; i++) {
-+		fq = &priv->fq[i];
-+		err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt);
-+		if (err)
-+			fcnt = 0;
-+
-+		/* A lot of queues, no use displaying zero traffic ones */
-+		if (!fq->stats.frames && !fcnt)
-+			continue;
-+
-+		seq_printf(file, "%5d%16d%16d%16s%16llu%16u%16llu\n",
-+			   fq->fqid,
-+			   fq->target_cpu,
-+			   fq->tc,
-+			   fq_type_to_str(fq),
-+			   fq->stats.frames,
-+			   fcnt,
-+			   fq->stats.congestion_entry);
-+	}
-+
-+	return 0;
-+}
-+
-+static int dpaa2_dbg_fqs_open(struct inode *inode, struct file *file)
-+{
-+	int err;
-+	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private;
-+
-+	err = single_open(file, dpaa2_dbg_fqs_show, priv);
-+	if (err < 0)
-+		netdev_err(priv->net_dev, "single_open() failed\n");
-+
-+	return err;
-+}
-+
-+static const struct file_operations dpaa2_dbg_fq_ops = {
-+	.open = dpaa2_dbg_fqs_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+};
-+
-+static int dpaa2_dbg_ch_show(struct seq_file *file, void *offset)
-+{
-+	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
-+	struct dpaa2_eth_channel *ch;
-+	int i;
-+
-+	seq_printf(file, "Channel stats for %s:\n", priv->net_dev->name);
-+	seq_printf(file, "%s%16s%16s%16s%16s%16s%16s\n",
-+		   "CHID", "CPU", "Deq busy", "Frames", "CDANs",
-+		   "Avg frm/CDAN", "Buf count");
-+
-+	for (i = 0; i < priv->num_channels; i++) {
-+		ch = priv->channel[i];
-+		seq_printf(file, "%4d%16d%16llu%16llu%16llu%16llu%16d\n",
-+			   ch->ch_id,
-+			   ch->nctx.desired_cpu,
-+			   ch->stats.dequeue_portal_busy,
-+			   ch->stats.frames,
-+			   ch->stats.cdan,
-+			   ch->stats.frames / ch->stats.cdan,
-+			   ch->buf_count);
-+	}
-+
-+	return 0;
-+}
-+
-+static int dpaa2_dbg_ch_open(struct inode *inode, struct file *file)
-+{
-+	int err;
-+	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private;
-+
-+	err = single_open(file, dpaa2_dbg_ch_show, priv);
-+	if (err < 0)
-+		netdev_err(priv->net_dev, "single_open() failed\n");
-+
-+	return err;
-+}
-+
-+static const struct file_operations dpaa2_dbg_ch_ops = {
-+	.open = dpaa2_dbg_ch_open,
-+	.read = seq_read,
-+	.llseek = seq_lseek,
-+	.release = single_release,
-+};
-+
-+static ssize_t dpaa2_dbg_reset_write(struct file *file, const char __user *buf,
-+				     size_t count, loff_t *offset)
-+{
-+	struct dpaa2_eth_priv *priv = file->private_data;
-+	struct rtnl_link_stats64 *percpu_stats;
-+	struct dpaa2_eth_drv_stats *percpu_extras;
-+	struct dpaa2_eth_fq *fq;
-+	struct dpaa2_eth_channel *ch;
-+	int i;
-+
-+	for_each_online_cpu(i) {
-+		percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
-+		memset(percpu_stats, 0, sizeof(*percpu_stats));
-+
-+		percpu_extras = per_cpu_ptr(priv->percpu_extras, i);
-+		memset(percpu_extras, 0, sizeof(*percpu_extras));
-+	}
-+
-+	for (i = 0; i < priv->num_fqs; i++) {
-+		fq = &priv->fq[i];
-+		memset(&fq->stats, 0, sizeof(fq->stats));
-+	}
-+
-+	for (i = 0; i < priv->num_channels; i++) {
-+		ch = priv->channel[i];
-+		memset(&ch->stats, 0, sizeof(ch->stats));
-+	}
-+
-+	return count;
-+}
-+
-+static const struct file_operations dpaa2_dbg_reset_ops = {
-+	.open = simple_open,
-+	.write = dpaa2_dbg_reset_write,
-+};
-+
-+static ssize_t dpaa2_dbg_reset_mc_write(struct file *file,
-+					const char __user *buf,
-+					size_t count, loff_t *offset)
-+{
-+	struct dpaa2_eth_priv *priv = file->private_data;
-+	int err;
-+
-+	err = dpni_reset_statistics(priv->mc_io, 0, priv->mc_token);
-+	if (err)
-+		netdev_err(priv->net_dev,
-+			   "dpni_reset_statistics() failed %d\n", err);
-+
-+	return count;
-+}
-+
-+static const struct file_operations dpaa2_dbg_reset_mc_ops = {
-+	.open = simple_open,
-+	.write = dpaa2_dbg_reset_mc_write,
-+};
-+
-+void dpaa2_dbg_add(struct dpaa2_eth_priv *priv)
-+{
-+	if (!dpaa2_dbg_root)
-+		return;
-+
-+	/* Create a directory for the interface */
-+	priv->dbg.dir = debugfs_create_dir(priv->net_dev->name,
-+					   dpaa2_dbg_root);
-+	if (!priv->dbg.dir) {
-+		netdev_err(priv->net_dev, "debugfs_create_dir() failed\n");
-+		return;
-+	}
-+
-+	/* per-cpu stats file */
-+	priv->dbg.cpu_stats = debugfs_create_file("cpu_stats", 0444,
-+						  priv->dbg.dir, priv,
-+						  &dpaa2_dbg_cpu_ops);
-+	if (!priv->dbg.cpu_stats) {
-+		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
-+		goto err_cpu_stats;
-+	}
-+
-+	/* per-fq stats file */
-+	priv->dbg.fq_stats = debugfs_create_file("fq_stats", 0444,
-+						 priv->dbg.dir, priv,
-+						 &dpaa2_dbg_fq_ops);
-+	if (!priv->dbg.fq_stats) {
-+		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
-+		goto err_fq_stats;
-+	}
-+
-+	/* per-fq stats file */
-+	priv->dbg.ch_stats = debugfs_create_file("ch_stats", 0444,
-+						 priv->dbg.dir, priv,
-+						 &dpaa2_dbg_ch_ops);
-+	if (!priv->dbg.fq_stats) {
-+		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
-+		goto err_ch_stats;
-+	}
-+
-+	/* reset stats */
-+	priv->dbg.reset_stats = debugfs_create_file("reset_stats", 0200,
-+						    priv->dbg.dir, priv,
-+						    &dpaa2_dbg_reset_ops);
-+	if (!priv->dbg.reset_stats) {
-+		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
-+		goto err_reset_stats;
-+	}
-+
-+	/* reset MC stats */
-+	priv->dbg.reset_mc_stats = debugfs_create_file("reset_mc_stats",
-+						0222, priv->dbg.dir, priv,
-+						&dpaa2_dbg_reset_mc_ops);
-+	if (!priv->dbg.reset_mc_stats) {
-+		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
-+		goto err_reset_mc_stats;
-+	}
-+
-+	return;
-+
-+err_reset_mc_stats:
-+	debugfs_remove(priv->dbg.reset_stats);
-+err_reset_stats:
-+	debugfs_remove(priv->dbg.ch_stats);
-+err_ch_stats:
-+	debugfs_remove(priv->dbg.fq_stats);
-+err_fq_stats:
-+	debugfs_remove(priv->dbg.cpu_stats);
-+err_cpu_stats:
-+	debugfs_remove(priv->dbg.dir);
-+}
-+
-+void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv)
-+{
-+	debugfs_remove(priv->dbg.reset_mc_stats);
-+	debugfs_remove(priv->dbg.reset_stats);
-+	debugfs_remove(priv->dbg.fq_stats);
-+	debugfs_remove(priv->dbg.ch_stats);
-+	debugfs_remove(priv->dbg.cpu_stats);
-+	debugfs_remove(priv->dbg.dir);
-+}
-+
-+void dpaa2_eth_dbg_init(void)
-+{
-+	dpaa2_dbg_root = debugfs_create_dir(DPAA2_ETH_DBG_ROOT, NULL);
-+	if (!dpaa2_dbg_root) {
-+		pr_err("DPAA2-ETH: debugfs create failed\n");
-+		return;
-+	}
-+
-+	pr_info("DPAA2-ETH: debugfs created\n");
-+}
-+
-+void __exit dpaa2_eth_dbg_exit(void)
-+{
-+	debugfs_remove(dpaa2_dbg_root);
-+}
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h
-@@ -0,0 +1,60 @@
-+/* Copyright 2015 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the name of Freescale Semiconductor nor the
-+ *	 names of its contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef DPAA2_ETH_DEBUGFS_H
-+#define DPAA2_ETH_DEBUGFS_H
-+
-+#include <linux/dcache.h>
-+
-+struct dpaa2_eth_priv;
-+
-+struct dpaa2_debugfs {
-+	struct dentry *dir;
-+	struct dentry *fq_stats;
-+	struct dentry *ch_stats;
-+	struct dentry *cpu_stats;
-+	struct dentry *reset_stats;
-+	struct dentry *reset_mc_stats;
-+};
-+
-+#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS
-+void dpaa2_eth_dbg_init(void);
-+void dpaa2_eth_dbg_exit(void);
-+void dpaa2_dbg_add(struct dpaa2_eth_priv *priv);
-+void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv);
-+#else
-+static inline void dpaa2_eth_dbg_init(void) {}
-+static inline void dpaa2_eth_dbg_exit(void) {}
-+static inline void dpaa2_dbg_add(struct dpaa2_eth_priv *priv) {}
-+static inline void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv) {}
-+#endif /* CONFIG_FSL_DPAA2_ETH_DEBUGFS */
-+
-+#endif /* DPAA2_ETH_DEBUGFS_H */
---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
-@@ -38,9 +38,14 @@
- #include <linux/msi.h>
- #include <linux/kthread.h>
- #include <linux/iommu.h>
--
-+#include <linux/net_tstamp.h>
-+#include <linux/bpf.h>
-+#include <linux/filter.h>
-+#include <linux/atomic.h>
-+#include <net/sock.h>
- #include "../../fsl-mc/include/mc.h"
- #include "dpaa2-eth.h"
-+#include "dpaa2-eth-ceetm.h"
- 
- /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
-  * using trace events only need to #include <trace/events/sched.h>
-@@ -104,13 +109,15 @@ static void free_rx_fd(struct dpaa2_eth_
- 		/* We don't support any other format */
- 		return;
- 
--	/* For S/G frames, we first need to free all SG entries */
-+	/* For S/G frames, we first need to free all SG entries
-+	 * except the first one, which was taken care of already
-+	 */
- 	sgt = vaddr + dpaa2_fd_get_offset(fd);
--	for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
-+	for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
- 		addr = dpaa2_sg_get_addr(&sgt[i]);
- 		sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
- 		dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
--				 DMA_FROM_DEVICE);
-+				 DMA_BIDIRECTIONAL);
- 
- 		skb_free_frag(sg_vaddr);
- 		if (dpaa2_sg_is_final(&sgt[i]))
-@@ -133,8 +140,7 @@ static struct sk_buff *build_linear_skb(
- 
- 	ch->buf_count--;
- 
--	skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_SIZE +
--			SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
-+	skb = build_skb(fd_vaddr, DPAA2_ETH_SKB_SIZE);
- 	if (unlikely(!skb))
- 		return NULL;
- 
-@@ -170,15 +176,19 @@ static struct sk_buff *build_frag_skb(st
- 		sg_addr = dpaa2_sg_get_addr(sge);
- 		sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
- 		dma_unmap_single(dev, sg_addr, DPAA2_ETH_RX_BUF_SIZE,
--				 DMA_FROM_DEVICE);
-+				 DMA_BIDIRECTIONAL);
- 
- 		sg_length = dpaa2_sg_get_len(sge);
- 
- 		if (i == 0) {
- 			/* We build the skb around the first data buffer */
--			skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_SIZE +
--				SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
-+			skb = build_skb(sg_vaddr, DPAA2_ETH_SKB_SIZE);
- 			if (unlikely(!skb)) {
-+				/* Free the first SG entry now, since we already
-+				 * unmapped it and obtained the virtual address
-+				 */
-+				skb_free_frag(sg_vaddr);
-+
- 				/* We still need to subtract the buffers used
- 				 * by this FD from our software counter
- 				 */
-@@ -213,17 +223,173 @@ static struct sk_buff *build_frag_skb(st
- 			break;
- 	}
- 
-+	WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
-+
- 	/* Count all data buffers + SG table buffer */
- 	ch->buf_count -= i + 2;
- 
- 	return skb;
- }
- 
-+static int dpaa2_eth_xdp_tx(struct dpaa2_eth_priv *priv,
-+			    struct dpaa2_fd *fd,
-+			    void *buf_start,
-+			    u16 queue_id)
-+{
-+	struct dpaa2_eth_fq *fq;
-+	struct rtnl_link_stats64 *percpu_stats;
-+	struct dpaa2_eth_drv_stats *percpu_extras;
-+	struct dpaa2_faead *faead;
-+	u32 ctrl, frc;
-+	int i, err;
-+
-+	/* Mark the egress frame annotation area as valid */
-+	frc = dpaa2_fd_get_frc(fd);
-+	dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
-+	dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL);
-+
-+	ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV;
-+	faead = dpaa2_get_faead(buf_start, false);
-+	faead->ctrl = cpu_to_le32(ctrl);
-+	faead->conf_fqid = 0;
-+
-+	percpu_stats = this_cpu_ptr(priv->percpu_stats);
-+	percpu_extras = this_cpu_ptr(priv->percpu_extras);
-+
-+	fq = &priv->fq[queue_id];
-+	for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
-+		err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
-+						  priv->tx_qdid, 0,
-+						  fq->tx_qdbin, fd);
-+		if (err != -EBUSY)
-+			break;
-+	}
-+
-+	percpu_extras->tx_portal_busy += i;
-+	if (unlikely(err)) {
-+		percpu_stats->tx_errors++;
-+	} else {
-+		percpu_stats->tx_packets++;
-+		percpu_stats->tx_bytes += dpaa2_fd_get_len(fd);
-+	}
-+
-+	return err;
-+}
-+
-+static void free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array, int count)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	void *vaddr;
-+	int i;
-+
-+	for (i = 0; i < count; i++) {
-+		/* Same logic as on regular Rx path */
-+		vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
-+		dma_unmap_single(dev, buf_array[i], DPAA2_ETH_RX_BUF_SIZE,
-+				 DMA_BIDIRECTIONAL);
-+		skb_free_frag(vaddr);
-+	}
-+}
-+
-+static void release_fd_buf(struct dpaa2_eth_priv *priv,
-+			   struct dpaa2_eth_channel *ch,
-+			   dma_addr_t addr)
-+{
-+	int err;
-+
-+	ch->rel_buf_array[ch->rel_buf_cnt++] = addr;
-+	if (likely(ch->rel_buf_cnt < DPAA2_ETH_BUFS_PER_CMD))
-+		return;
-+
-+	while ((err = dpaa2_io_service_release(ch->dpio, priv->bpid,
-+					       ch->rel_buf_array,
-+					       ch->rel_buf_cnt)) == -EBUSY)
-+		cpu_relax();
-+
-+	if (err)
-+		free_bufs(priv, ch->rel_buf_array, ch->rel_buf_cnt);
-+
-+	ch->rel_buf_cnt = 0;
-+}
-+
-+static u32 dpaa2_eth_run_xdp(struct dpaa2_eth_priv *priv,
-+			     struct dpaa2_eth_channel *ch,
-+			     struct dpaa2_fd *fd,
-+			     u16 queue_id,
-+			     void *vaddr)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	dma_addr_t addr = dpaa2_fd_get_addr(fd);
-+	struct rtnl_link_stats64 *percpu_stats;
-+	struct bpf_prog *xdp_prog;
-+	struct xdp_buff xdp;
-+	u32 xdp_act = XDP_PASS;
-+
-+	xdp_prog = READ_ONCE(ch->xdp_prog);
-+	if (!xdp_prog)
-+		return xdp_act;
-+
-+	percpu_stats = this_cpu_ptr(priv->percpu_stats);
-+
-+	xdp.data = vaddr + dpaa2_fd_get_offset(fd);
-+	xdp.data_end = xdp.data + dpaa2_fd_get_len(fd);
-+	/* Allow the XDP program to use the specially reserved headroom */
-+	xdp.data_hard_start = xdp.data - XDP_PACKET_HEADROOM;
-+
-+	rcu_read_lock();
-+	xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
-+
-+	/* xdp.data pointer may have changed */
-+	dpaa2_fd_set_offset(fd, xdp.data - vaddr);
-+	dpaa2_fd_set_len(fd, xdp.data_end - xdp.data);
-+
-+	switch (xdp_act) {
-+	case XDP_PASS:
-+		break;
-+	default:
-+		bpf_warn_invalid_xdp_action(xdp_act);
-+	case XDP_ABORTED:
-+	case XDP_DROP:
-+		/* This is our buffer, so we can release it back to hardware */
-+		release_fd_buf(priv, ch, addr);
-+		percpu_stats->rx_dropped++;
-+		break;
-+	case XDP_TX:
-+		if (dpaa2_eth_xdp_tx(priv, fd, vaddr, queue_id)) {
-+			dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
-+					 DMA_BIDIRECTIONAL);
-+			free_rx_fd(priv, fd, vaddr);
-+			ch->buf_count--;
-+		}
-+		break;
-+	case XDP_REDIRECT:
-+		dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
-+				 DMA_BIDIRECTIONAL);
-+		ch->buf_count--;
-+		ch->flush = true;
-+		/* Mark the actual start of the data buffer */
-+		xdp.data_hard_start = vaddr;
-+		if (xdp_do_redirect(priv->net_dev, &xdp, xdp_prog))
-+			free_rx_fd(priv, fd, vaddr);
-+		break;
-+	}
-+
-+	if (xdp_act == XDP_TX || xdp_act == XDP_REDIRECT) {
-+		percpu_stats->rx_packets++;
-+		percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
-+	}
-+
-+	rcu_read_unlock();
-+
-+	return xdp_act;
-+}
-+
- /* Main Rx frame processing routine */
- static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
- 			 struct dpaa2_eth_channel *ch,
- 			 const struct dpaa2_fd *fd,
--			 struct napi_struct *napi)
-+			 struct napi_struct *napi,
-+			 u16 queue_id)
- {
- 	dma_addr_t addr = dpaa2_fd_get_addr(fd);
- 	u8 fd_format = dpaa2_fd_get_format(fd);
-@@ -235,14 +401,16 @@ static void dpaa2_eth_rx(struct dpaa2_et
- 	struct dpaa2_fas *fas;
- 	void *buf_data;
- 	u32 status = 0;
-+	u32 xdp_act;
- 
- 	/* Tracing point */
- 	trace_dpaa2_rx_fd(priv->net_dev, fd);
- 
- 	vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
--	dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE);
-+	dma_sync_single_for_cpu(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
-+				DMA_BIDIRECTIONAL);
- 
--	fas = dpaa2_get_fas(vaddr);
-+	fas = dpaa2_get_fas(vaddr, false);
- 	prefetch(fas);
- 	buf_data = vaddr + dpaa2_fd_get_offset(fd);
- 	prefetch(buf_data);
-@@ -251,22 +419,41 @@ static void dpaa2_eth_rx(struct dpaa2_et
- 	percpu_extras = this_cpu_ptr(priv->percpu_extras);
- 
- 	if (fd_format == dpaa2_fd_single) {
-+		xdp_act = dpaa2_eth_run_xdp(priv, ch, (struct dpaa2_fd *)fd,
-+					    queue_id, vaddr);
-+		if (xdp_act != XDP_PASS)
-+			return;
-+
-+		dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
-+				 DMA_BIDIRECTIONAL);
- 		skb = build_linear_skb(priv, ch, fd, vaddr);
- 	} else if (fd_format == dpaa2_fd_sg) {
-+		dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
-+				 DMA_BIDIRECTIONAL);
- 		skb = build_frag_skb(priv, ch, buf_data);
- 		skb_free_frag(vaddr);
- 		percpu_extras->rx_sg_frames++;
- 		percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
- 	} else {
- 		/* We don't support any other format */
--		goto err_frame_format;
-+		goto drop_cnt;
- 	}
- 
- 	if (unlikely(!skb))
--		goto err_build_skb;
-+		goto drop_fd;
- 
- 	prefetch(skb->data);
- 
-+	/* Get the timestamp value */
-+	if (priv->ts_rx_en) {
-+		struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
-+		u64 *ns = dpaa2_get_ts(vaddr, false);
-+
-+		*ns = DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS * le64_to_cpup(ns);
-+		memset(shhwtstamps, 0, sizeof(*shhwtstamps));
-+		shhwtstamps->hwtstamp = ns_to_ktime(*ns);
-+	}
-+
- 	/* Check if we need to validate the L4 csum */
- 	if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
- 		status = le32_to_cpu(fas->status);
-@@ -275,6 +462,12 @@ static void dpaa2_eth_rx(struct dpaa2_et
- 
- 	skb->protocol = eth_type_trans(skb, priv->net_dev);
- 
-+	/* Record Rx queue - this will be used when picking a Tx queue to
-+	 * forward the frames. We're keeping flow affinity through the
-+	 * network stack.
-+	 */
-+	skb_record_rx_queue(skb, queue_id);
-+
- 	percpu_stats->rx_packets++;
- 	percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
- 
-@@ -282,22 +475,74 @@ static void dpaa2_eth_rx(struct dpaa2_et
- 
- 	return;
- 
--err_build_skb:
-+drop_fd:
- 	free_rx_fd(priv, fd, vaddr);
--err_frame_format:
-+drop_cnt:
- 	percpu_stats->rx_dropped++;
- }
- 
-+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
-+/* Processing of Rx frames received on the error FQ
-+ * We check and print the error bits and then free the frame
-+ */
-+static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv,
-+			     struct dpaa2_eth_channel *ch,
-+			     const struct dpaa2_fd *fd,
-+			     struct napi_struct *napi __always_unused,
-+			     u16 queue_id __always_unused)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	dma_addr_t addr = dpaa2_fd_get_addr(fd);
-+	void *vaddr;
-+	struct rtnl_link_stats64 *percpu_stats;
-+	struct dpaa2_fas *fas;
-+	u32 status = 0;
-+	u32 fd_errors;
-+	bool has_fas_errors = false;
-+
-+	vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
-+	dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_BIDIRECTIONAL);
-+
-+	/* check frame errors in the FD field */
-+	fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_RX_ERR_MASK;
-+	if (likely(fd_errors)) {
-+		has_fas_errors = (fd_errors & FD_CTRL_FAERR) &&
-+				 !!(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV);
-+		if (net_ratelimit())
-+			netdev_dbg(priv->net_dev, "RX frame FD err: %08x\n",
-+				   fd_errors);
-+	}
-+
-+	/* check frame errors in the FAS field */
-+	if (has_fas_errors) {
-+		fas = dpaa2_get_fas(vaddr, false);
-+		status = le32_to_cpu(fas->status);
-+		if (net_ratelimit())
-+			netdev_dbg(priv->net_dev, "Rx frame FAS err: 0x%08x\n",
-+				   status & DPAA2_FAS_RX_ERR_MASK);
-+	}
-+	free_rx_fd(priv, fd, vaddr);
-+
-+	percpu_stats = this_cpu_ptr(priv->percpu_stats);
-+	percpu_stats->rx_errors++;
-+	ch->buf_count--;
-+}
-+#endif
-+
- /* Consume all frames pull-dequeued into the store. This is the simplest way to
-  * make sure we don't accidentally issue another volatile dequeue which would
-  * overwrite (leak) frames already in the store.
-  *
-+ * The number of frames is returned using the last 2 output arguments,
-+ * separately for Rx and Tx confirmations.
-+ *
-  * Observance of NAPI budget is not our concern, leaving that to the caller.
-  */
--static int consume_frames(struct dpaa2_eth_channel *ch)
-+static bool consume_frames(struct dpaa2_eth_channel *ch, int *rx_cleaned,
-+			   int *tx_conf_cleaned)
- {
- 	struct dpaa2_eth_priv *priv = ch->priv;
--	struct dpaa2_eth_fq *fq;
-+	struct dpaa2_eth_fq *fq = NULL;
- 	struct dpaa2_dq *dq;
- 	const struct dpaa2_fd *fd;
- 	int cleaned = 0;
-@@ -315,14 +560,60 @@ static int consume_frames(struct dpaa2_e
- 		}
- 
- 		fd = dpaa2_dq_fd(dq);
--		fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
--		fq->stats.frames++;
-+		prefetch(fd);
- 
--		fq->consume(priv, ch, fd, &ch->napi);
-+		fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
-+		fq->consume(priv, ch, fd, &ch->napi, fq->flowid);
- 		cleaned++;
- 	} while (!is_last);
- 
--	return cleaned;
-+	if (!cleaned)
-+		return false;
-+
-+	/* All frames brought in store by a volatile dequeue
-+	 * come from the same queue
-+	 */
-+	if (fq->type == DPAA2_TX_CONF_FQ) {
-+		*tx_conf_cleaned += cleaned;
-+	} else {
-+		*rx_cleaned += cleaned;
-+		/* If we processed XDP_REDIRECT frames, flush them now */
-+		/* FIXME: Since we don't actually do anything inside
-+		 * ndo_xdp_flush, we call it here simply for compliance
-+		 * reasons
-+		 */
-+		if (ch->flush) {
-+			xdp_do_flush_map();
-+			ch->flush = false;
-+		}
-+	}
-+
-+	fq->stats.frames += cleaned;
-+	ch->stats.frames += cleaned;
-+
-+	return true;
-+}
-+
-+/* Configure the egress frame annotation for timestamp update */
-+static void enable_tx_tstamp(struct dpaa2_fd *fd, void *buf_start)
-+{
-+	struct dpaa2_faead *faead;
-+	u32 ctrl, frc;
-+
-+	/* Mark the egress frame annotation area as valid */
-+	frc = dpaa2_fd_get_frc(fd);
-+	dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
-+
-+	/* Set hardware annotation size */
-+	ctrl = dpaa2_fd_get_ctrl(fd);
-+	dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
-+
-+	/* enable UPD (update prepanded data) bit in FAEAD field of
-+	 * hardware frame annotation area
-+	 */
-+	ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
-+	faead = dpaa2_get_faead(buf_start, true);
-+	faead->ctrl = cpu_to_le32(ctrl);
- }
- 
- /* Create a frame descriptor based on a fragmented skb */
-@@ -341,7 +632,6 @@ static int build_sg_fd(struct dpaa2_eth_
- 	int num_sg;
- 	int num_dma_bufs;
- 	struct dpaa2_eth_swa *swa;
--	struct dpaa2_fas *fas;
- 
- 	/* Create and map scatterlist.
- 	 * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
-@@ -365,21 +655,14 @@ static int build_sg_fd(struct dpaa2_eth_
- 
- 	/* Prepare the HW SGT structure */
- 	sgt_buf_size = priv->tx_data_offset +
--		       sizeof(struct dpaa2_sg_entry) * (1 + num_dma_bufs);
--	sgt_buf = kzalloc(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN, GFP_ATOMIC);
-+		       sizeof(struct dpaa2_sg_entry) *  num_dma_bufs;
-+	sgt_buf = netdev_alloc_frag(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN);
- 	if (unlikely(!sgt_buf)) {
- 		err = -ENOMEM;
- 		goto sgt_buf_alloc_failed;
- 	}
- 	sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
--
--	/* PTA from egress side is passed as is to the confirmation side so
--	 * we need to clear some fields here in order to find consistent values
--	 * on TX confirmation. We are clearing FAS (Frame Annotation Status)
--	 * field from the hardware annotation area
--	 */
--	fas = dpaa2_get_fas(sgt_buf);
--	memset(fas, 0, DPAA2_FAS_SIZE);
-+	memset(sgt_buf, 0, sgt_buf_size);
- 
- 	sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
- 
-@@ -402,10 +685,11 @@ static int build_sg_fd(struct dpaa2_eth_
- 	 * all of them on Tx Conf.
- 	 */
- 	swa = (struct dpaa2_eth_swa *)sgt_buf;
--	swa->skb = skb;
--	swa->scl = scl;
--	swa->num_sg = num_sg;
--	swa->num_dma_bufs = num_dma_bufs;
-+	swa->type = DPAA2_ETH_SWA_SG;
-+	swa->sg.skb = skb;
-+	swa->sg.scl = scl;
-+	swa->sg.num_sg = num_sg;
-+	swa->sg.sgt_size = sgt_buf_size;
- 
- 	/* Separately map the SGT buffer */
- 	addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
-@@ -417,13 +701,15 @@ static int build_sg_fd(struct dpaa2_eth_
- 	dpaa2_fd_set_format(fd, dpaa2_fd_sg);
- 	dpaa2_fd_set_addr(fd, addr);
- 	dpaa2_fd_set_len(fd, skb->len);
--	dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL | DPAA2_FD_CTRL_PTA |
--			  DPAA2_FD_CTRL_PTV1);
-+	dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
-+
-+	if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
-+		enable_tx_tstamp(fd, sgt_buf);
- 
- 	return 0;
- 
- dma_map_single_failed:
--	kfree(sgt_buf);
-+	skb_free_frag(sgt_buf);
- sgt_buf_alloc_failed:
- 	dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
- dma_map_sg_failed:
-@@ -437,29 +723,27 @@ static int build_single_fd(struct dpaa2_
- 			   struct dpaa2_fd *fd)
- {
- 	struct device *dev = priv->net_dev->dev.parent;
--	u8 *buffer_start;
--	struct dpaa2_fas *fas;
--	struct sk_buff **skbh;
-+	u8 *buffer_start, *aligned_start;
-+	struct dpaa2_eth_swa *swa;
- 	dma_addr_t addr;
- 
--	buffer_start = PTR_ALIGN(skb->data - priv->tx_data_offset -
--				 DPAA2_ETH_TX_BUF_ALIGN,
--				 DPAA2_ETH_TX_BUF_ALIGN);
--
--	/* PTA from egress side is passed as is to the confirmation side so
--	 * we need to clear some fields here in order to find consistent values
--	 * on TX confirmation. We are clearing FAS (Frame Annotation Status)
--	 * field from the hardware annotation area
-+	buffer_start = skb->data - dpaa2_eth_needed_headroom(priv, skb);
-+
-+	/* If there's enough room to align the FD address, do it.
-+	 * It will help hardware optimize accesses.
- 	 */
--	fas = dpaa2_get_fas(buffer_start);
--	memset(fas, 0, DPAA2_FAS_SIZE);
-+	aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
-+				  DPAA2_ETH_TX_BUF_ALIGN);
-+	if (aligned_start >= skb->head)
-+		buffer_start = aligned_start;
- 
- 	/* Store a backpointer to the skb at the beginning of the buffer
- 	 * (in the private data area) such that we can release it
- 	 * on Tx confirm
- 	 */
--	skbh = (struct sk_buff **)buffer_start;
--	*skbh = skb;
-+	swa = (struct dpaa2_eth_swa *)buffer_start;
-+	swa->type = DPAA2_ETH_SWA_SINGLE;
-+	swa->single.skb = skb;
- 
- 	addr = dma_map_single(dev, buffer_start,
- 			      skb_tail_pointer(skb) - buffer_start,
-@@ -471,8 +755,10 @@ static int build_single_fd(struct dpaa2_
- 	dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
- 	dpaa2_fd_set_len(fd, skb->len);
- 	dpaa2_fd_set_format(fd, dpaa2_fd_single);
--	dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL | DPAA2_FD_CTRL_PTA |
--			  DPAA2_FD_CTRL_PTV1);
-+	dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
-+
-+	if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
-+		enable_tx_tstamp(fd, buffer_start);
- 
- 	return 0;
- }
-@@ -486,92 +772,128 @@ static int build_single_fd(struct dpaa2_
-  * Optionally, return the frame annotation status word (FAS), which needs
-  * to be checked if we're on the confirmation path.
-  */
--static void free_tx_fd(const struct dpaa2_eth_priv *priv,
-+static void free_tx_fd(struct dpaa2_eth_priv *priv,
- 		       const struct dpaa2_fd *fd,
--		       u32 *status)
-+		       bool in_napi)
- {
- 	struct device *dev = priv->net_dev->dev.parent;
- 	dma_addr_t fd_addr;
--	struct sk_buff **skbh, *skb;
-+	struct sk_buff *skb = NULL;
- 	unsigned char *buffer_start;
--	int unmap_size;
--	struct scatterlist *scl;
--	int num_sg, num_dma_bufs;
- 	struct dpaa2_eth_swa *swa;
- 	u8 fd_format = dpaa2_fd_get_format(fd);
--	struct dpaa2_fas *fas;
- 
- 	fd_addr = dpaa2_fd_get_addr(fd);
--	skbh = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
--	fas = dpaa2_get_fas(skbh);
-+	buffer_start = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
-+	swa = (struct dpaa2_eth_swa *)buffer_start;
- 
- 	if (fd_format == dpaa2_fd_single) {
--		skb = *skbh;
--		buffer_start = (unsigned char *)skbh;
--		/* Accessing the skb buffer is safe before dma unmap, because
--		 * we didn't map the actual skb shell.
--		 */
--		dma_unmap_single(dev, fd_addr,
--				 skb_tail_pointer(skb) - buffer_start,
--				 DMA_BIDIRECTIONAL);
-+		if (swa->type == DPAA2_ETH_SWA_SINGLE) {
-+			skb = swa->single.skb;
-+			/* Accessing the skb buffer is safe before dma unmap,
-+			 * because we didn't map the actual skb shell.
-+			 */
-+			dma_unmap_single(dev, fd_addr,
-+					 skb_tail_pointer(skb) - buffer_start,
-+					 DMA_BIDIRECTIONAL);
-+		} else {
-+			WARN_ONCE(swa->type != DPAA2_ETH_SWA_XDP,
-+				  "Wrong SWA type");
-+			dma_unmap_single(dev, fd_addr, swa->xdp.dma_size,
-+					 DMA_BIDIRECTIONAL);
-+		}
- 	} else if (fd_format == dpaa2_fd_sg) {
--		swa = (struct dpaa2_eth_swa *)skbh;
--		skb = swa->skb;
--		scl = swa->scl;
--		num_sg = swa->num_sg;
--		num_dma_bufs = swa->num_dma_bufs;
-+		skb = swa->sg.skb;
- 
- 		/* Unmap the scatterlist */
--		dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
--		kfree(scl);
-+		dma_unmap_sg(dev, swa->sg.scl, swa->sg.num_sg, DMA_BIDIRECTIONAL);
-+		kfree(swa->sg.scl);
- 
- 		/* Unmap the SGT buffer */
--		unmap_size = priv->tx_data_offset +
--		       sizeof(struct dpaa2_sg_entry) * (1 + num_dma_bufs);
--		dma_unmap_single(dev, fd_addr, unmap_size, DMA_BIDIRECTIONAL);
-+		dma_unmap_single(dev, fd_addr, swa->sg.sgt_size,
-+				 DMA_BIDIRECTIONAL);
- 	} else {
--		/* Unsupported format, mark it as errored and give up */
--		if (status)
--			*status = ~0;
-+		netdev_dbg(priv->net_dev, "Invalid FD format\n");
- 		return;
- 	}
- 
--	/* Read the status from the Frame Annotation after we unmap the first
--	 * buffer but before we free it. The caller function is responsible
--	 * for checking the status value.
--	 */
--	if (status)
--		*status = le32_to_cpu(fas->status);
-+	if (swa->type == DPAA2_ETH_SWA_XDP) {
-+		page_frag_free(buffer_start);
-+		return;
-+	}
-+
-+	/* Get the timestamp value */
-+	if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
-+		struct skb_shared_hwtstamps shhwtstamps;
-+		u64 *ns;
-+
-+		memset(&shhwtstamps, 0, sizeof(shhwtstamps));
-+
-+		ns = dpaa2_get_ts(buffer_start, true);
-+		*ns = DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS * le64_to_cpup(ns);
-+		shhwtstamps.hwtstamp = ns_to_ktime(*ns);
-+		skb_tstamp_tx(skb, &shhwtstamps);
-+	}
- 
--	/* Free SGT buffer kmalloc'ed on tx */
-+	/* Free SGT buffer allocated on tx */
- 	if (fd_format != dpaa2_fd_single)
--		kfree(skbh);
-+		skb_free_frag(buffer_start);
- 
- 	/* Move on with skb release */
--	dev_kfree_skb(skb);
-+	napi_consume_skb(skb, in_napi);
- }
- 
- static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
- {
- 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct device *dev = net_dev->dev.parent;
- 	struct dpaa2_fd fd;
- 	struct rtnl_link_stats64 *percpu_stats;
- 	struct dpaa2_eth_drv_stats *percpu_extras;
- 	struct dpaa2_eth_fq *fq;
- 	u16 queue_mapping;
--	int err, i;
-+	unsigned int needed_headroom;
-+	u8 prio;
-+	int err, i, ch_id = 0;
-+
-+	queue_mapping = skb_get_queue_mapping(skb);
-+	prio = netdev_txq_to_tc(net_dev, queue_mapping);
-+
-+	/* Hardware interprets priority level 0 as being the highest,
-+	 * so we need to do a reverse mapping to the netdev tc index
-+	 */
-+	if (net_dev->num_tc)
-+		prio = net_dev->num_tc - prio - 1;
-+ 
-+	queue_mapping %= dpaa2_eth_queue_count(priv);
-+	fq = &priv->fq[queue_mapping];
-+
-+	/* If we're congested, stop this tx queue; transmission of
-+	 * the current skb happens regardless of congestion state
-+	 */
-+	dma_sync_single_for_cpu(dev, priv->cscn_dma,
-+				DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
-+	if (unlikely(dpaa2_cscn_state_congested(priv->cscn_mem))) {
-+		netif_stop_subqueue(net_dev, queue_mapping);
-+		fq->stats.congestion_entry++;
-+	}
- 
- 	percpu_stats = this_cpu_ptr(priv->percpu_stats);
- 	percpu_extras = this_cpu_ptr(priv->percpu_extras);
- 
--	if (unlikely(skb_headroom(skb) < DPAA2_ETH_NEEDED_HEADROOM(priv))) {
-+	/* For non-linear skb we don't need a minimum headroom */
-+	needed_headroom = dpaa2_eth_needed_headroom(priv, skb);
-+	if (skb_headroom(skb) < needed_headroom) {
- 		struct sk_buff *ns;
- 
--		ns = skb_realloc_headroom(skb, DPAA2_ETH_NEEDED_HEADROOM(priv));
-+		ns = skb_realloc_headroom(skb, needed_headroom);
- 		if (unlikely(!ns)) {
- 			percpu_stats->tx_dropped++;
- 			goto err_alloc_headroom;
- 		}
-+		percpu_extras->tx_reallocs++;
-+		if (skb->sk)
-+			skb_set_owner_w(ns, skb->sk);
- 		dev_kfree_skb(skb);
- 		skb = ns;
- 	}
-@@ -605,13 +927,15 @@ static netdev_tx_t dpaa2_eth_tx(struct s
- 	/* Tracing point */
- 	trace_dpaa2_tx_fd(net_dev, &fd);
- 
--	/* TxConf FQ selection primarily based on cpu affinity; this is
--	 * non-migratable context, so it's safe to call smp_processor_id().
--	 */
--	queue_mapping = smp_processor_id() % dpaa2_eth_queue_count(priv);
--	fq = &priv->fq[queue_mapping];
-+	if (dpaa2_eth_ceetm_is_enabled(priv)) {
-+		err = dpaa2_ceetm_classify(skb, net_dev->qdisc, &ch_id, &prio);
-+		if (err)
-+			goto err_ceetm_classify;
-+	}
-+
- 	for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
--		err = dpaa2_io_service_enqueue_qd(NULL, priv->tx_qdid, 0,
-+		err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
-+						  priv->tx_qdid, prio,
- 						  fq->tx_qdbin, &fd);
- 		if (err != -EBUSY)
- 			break;
-@@ -620,7 +944,7 @@ static netdev_tx_t dpaa2_eth_tx(struct s
- 	if (unlikely(err < 0)) {
- 		percpu_stats->tx_errors++;
- 		/* Clean up everything, including freeing the skb */
--		free_tx_fd(priv, &fd, NULL);
-+		free_tx_fd(priv, &fd, false);
- 	} else {
- 		percpu_stats->tx_packets++;
- 		percpu_stats->tx_bytes += dpaa2_fd_get_len(&fd);
-@@ -628,6 +952,8 @@ static netdev_tx_t dpaa2_eth_tx(struct s
- 
- 	return NETDEV_TX_OK;
- 
-+err_ceetm_classify:
-+	free_tx_fd(priv, &fd, false);
- err_build_fd:
- err_alloc_headroom:
- 	dev_kfree_skb(skb);
-@@ -639,13 +965,13 @@ err_alloc_headroom:
- static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
- 			      struct dpaa2_eth_channel *ch,
- 			      const struct dpaa2_fd *fd,
--			      struct napi_struct *napi __always_unused)
-+			      struct napi_struct *napi __always_unused,
-+			      u16 queue_id)
- {
-+	struct device *dev = priv->net_dev->dev.parent;
- 	struct rtnl_link_stats64 *percpu_stats;
- 	struct dpaa2_eth_drv_stats *percpu_extras;
--	u32 status = 0;
- 	u32 fd_errors;
--	bool has_fas_errors = false;
- 
- 	/* Tracing point */
- 	trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
-@@ -654,31 +980,28 @@ static void dpaa2_eth_tx_conf(struct dpa
- 	percpu_extras->tx_conf_frames++;
- 	percpu_extras->tx_conf_bytes += dpaa2_fd_get_len(fd);
- 
--	/* Check frame errors in the FD field */
--	fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
--	if (unlikely(fd_errors)) {
--		/* We only check error bits in the FAS field if corresponding
--		 * FAERR bit is set in FD and the FAS field is marked as valid
--		 */
--		has_fas_errors = (fd_errors & DPAA2_FD_CTRL_FAERR) &&
--				 !!(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV);
--		if (net_ratelimit())
--			netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
--				   fd_errors);
-+	/* Check congestion state and wake all queues if necessary */
-+	if (unlikely(__netif_subqueue_stopped(priv->net_dev, queue_id))) {
-+		dma_sync_single_for_cpu(dev, priv->cscn_dma,
-+					DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
-+		if (!dpaa2_cscn_state_congested(priv->cscn_mem))
-+			netif_tx_wake_all_queues(priv->net_dev);
- 	}
- 
--	free_tx_fd(priv, fd, has_fas_errors ? &status : NULL);
-+	/* Check frame errors in the FD field */
-+	fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
-+	free_tx_fd(priv, fd, true);
- 
- 	if (likely(!fd_errors))
- 		return;
- 
-+	if (net_ratelimit())
-+		netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
-+			   fd_errors);
-+
- 	percpu_stats = this_cpu_ptr(priv->percpu_stats);
- 	/* Tx-conf logically pertains to the egress path. */
- 	percpu_stats->tx_errors++;
--
--	if (has_fas_errors && net_ratelimit())
--		netdev_dbg(priv->net_dev, "TX frame FAS error: 0x%08x\n",
--			   status & DPAA2_FAS_TX_ERR_MASK);
- }
- 
- static int set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
-@@ -728,26 +1051,27 @@ static int set_tx_csum(struct dpaa2_eth_
- /* Perform a single release command to add buffers
-  * to the specified buffer pool
-  */
--static int add_bufs(struct dpaa2_eth_priv *priv, u16 bpid)
-+static int add_bufs(struct dpaa2_eth_priv *priv,
-+		    struct dpaa2_eth_channel *ch, u16 bpid)
- {
- 	struct device *dev = priv->net_dev->dev.parent;
- 	u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
- 	void *buf;
- 	dma_addr_t addr;
--	int i;
-+	int i, err;
- 
- 	for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
- 		/* Allocate buffer visible to WRIOP + skb shared info +
- 		 * alignment padding
- 		 */
--		buf = napi_alloc_frag(DPAA2_ETH_BUF_RAW_SIZE);
-+		buf = napi_alloc_frag(dpaa2_eth_buf_raw_size(priv));
- 		if (unlikely(!buf))
- 			goto err_alloc;
- 
--		buf = PTR_ALIGN(buf, DPAA2_ETH_RX_BUF_ALIGN);
-+		buf = PTR_ALIGN(buf, priv->rx_buf_align);
- 
- 		addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUF_SIZE,
--				      DMA_FROM_DEVICE);
-+				      DMA_BIDIRECTIONAL);
- 		if (unlikely(dma_mapping_error(dev, addr)))
- 			goto err_map;
- 
-@@ -755,28 +1079,31 @@ static int add_bufs(struct dpaa2_eth_pri
- 
- 		/* tracing point */
- 		trace_dpaa2_eth_buf_seed(priv->net_dev,
--					 buf, DPAA2_ETH_BUF_RAW_SIZE,
-+					 buf, dpaa2_eth_buf_raw_size(priv),
- 					 addr, DPAA2_ETH_RX_BUF_SIZE,
- 					 bpid);
- 	}
- 
- release_bufs:
--	/* In case the portal is busy, retry until successful.
--	 * The buffer release function would only fail if the QBMan portal
--	 * was busy, which implies portal contention (i.e. more CPUs than
--	 * portals, i.e. GPPs w/o affine DPIOs). For all practical purposes,
--	 * there is little we can realistically do, short of giving up -
--	 * in which case we'd risk depleting the buffer pool and never again
--	 * receiving the Rx interrupt which would kick-start the refill logic.
--	 * So just keep retrying, at the risk of being moved to ksoftirqd.
--	 */
--	while (dpaa2_io_service_release(NULL, bpid, buf_array, i))
-+	/* In case the portal is busy, retry until successful */
-+	while ((err = dpaa2_io_service_release(ch->dpio, bpid,
-+					       buf_array, i)) == -EBUSY)
- 		cpu_relax();
-+
-+	/* If release command failed, clean up and bail out; not much
-+	 * else we can do about it
-+	 */
-+	if (err) {
-+		free_bufs(priv, buf_array, i);
-+		return 0;
-+	}
-+
- 	return i;
- 
- err_map:
- 	skb_free_frag(buf);
- err_alloc:
-+	/* If we managed to allocate at least some buffers, release them */
- 	if (i)
- 		goto release_bufs;
- 
-@@ -796,9 +1123,10 @@ static int seed_pool(struct dpaa2_eth_pr
- 	 */
- 	preempt_disable();
- 	for (j = 0; j < priv->num_channels; j++) {
--		for (i = 0; i < DPAA2_ETH_NUM_BUFS;
-+		priv->channel[j]->buf_count = 0;
-+		for (i = 0; i < priv->max_bufs_per_ch;
- 		     i += DPAA2_ETH_BUFS_PER_CMD) {
--			new_count = add_bufs(priv, bpid);
-+			new_count = add_bufs(priv, priv->channel[j], bpid);
- 			priv->channel[j]->buf_count += new_count;
- 
- 			if (new_count < DPAA2_ETH_BUFS_PER_CMD) {
-@@ -818,10 +1146,8 @@ static int seed_pool(struct dpaa2_eth_pr
-  */
- static void drain_bufs(struct dpaa2_eth_priv *priv, int count)
- {
--	struct device *dev = priv->net_dev->dev.parent;
- 	u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
--	void *vaddr;
--	int ret, i;
-+	int ret;
- 
- 	do {
- 		ret = dpaa2_io_service_acquire(NULL, priv->bpid,
-@@ -830,27 +1156,16 @@ static void drain_bufs(struct dpaa2_eth_
- 			netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
- 			return;
- 		}
--		for (i = 0; i < ret; i++) {
--			/* Same logic as on regular Rx path */
--			vaddr = dpaa2_iova_to_virt(priv->iommu_domain,
--						   buf_array[i]);
--			dma_unmap_single(dev, buf_array[i],
--					 DPAA2_ETH_RX_BUF_SIZE,
--					 DMA_FROM_DEVICE);
--			skb_free_frag(vaddr);
--		}
-+		free_bufs(priv, buf_array, ret);
- 	} while (ret);
- }
- 
- static void drain_pool(struct dpaa2_eth_priv *priv)
- {
--	int i;
--
-+	preempt_disable();
- 	drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD);
- 	drain_bufs(priv, 1);
--
--	for (i = 0; i < priv->num_channels; i++)
--		priv->channel[i]->buf_count = 0;
-+	preempt_enable();
- }
- 
- /* Function is called from softirq context only, so we don't need to guard
-@@ -862,19 +1177,19 @@ static int refill_pool(struct dpaa2_eth_
- {
- 	int new_count;
- 
--	if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH))
-+	if (likely(ch->buf_count >= priv->refill_thresh))
- 		return 0;
- 
- 	do {
--		new_count = add_bufs(priv, bpid);
-+		new_count = add_bufs(priv, ch, bpid);
- 		if (unlikely(!new_count)) {
- 			/* Out of memory; abort for now, we'll try later on */
- 			break;
- 		}
- 		ch->buf_count += new_count;
--	} while (ch->buf_count < DPAA2_ETH_NUM_BUFS);
-+	} while (ch->buf_count < priv->max_bufs_per_ch);
- 
--	if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS))
-+	if (unlikely(ch->buf_count < priv->max_bufs_per_ch))
- 		return -ENOMEM;
- 
- 	return 0;
-@@ -887,7 +1202,8 @@ static int pull_channel(struct dpaa2_eth
- 
- 	/* Retry while portal is busy */
- 	do {
--		err = dpaa2_io_service_pull_channel(NULL, ch->ch_id, ch->store);
-+		err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id,
-+						    ch->store);
- 		dequeues++;
- 		cpu_relax();
- 	} while (err == -EBUSY);
-@@ -902,20 +1218,21 @@ static int pull_channel(struct dpaa2_eth
- /* NAPI poll routine
-  *
-  * Frames are dequeued from the QMan channel associated with this NAPI context.
-- * Rx, Tx confirmation and (if configured) Rx error frames all count
-- * towards the NAPI budget.
-+ * Rx and (if configured) Rx error frames count towards the NAPI budget. Tx
-+ * confirmation frames are limited by a threshold per NAPI poll cycle.
-  */
- static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
- {
- 	struct dpaa2_eth_channel *ch;
--	int cleaned = 0, store_cleaned;
-+	int rx_cleaned = 0, tx_conf_cleaned = 0;
-+	bool store_cleaned;
- 	struct dpaa2_eth_priv *priv;
- 	int err;
- 
- 	ch = container_of(napi, struct dpaa2_eth_channel, napi);
- 	priv = ch->priv;
- 
--	while (cleaned < budget) {
-+	do {
- 		err = pull_channel(ch);
- 		if (unlikely(err))
- 			break;
-@@ -923,29 +1240,29 @@ static int dpaa2_eth_poll(struct napi_st
- 		/* Refill pool if appropriate */
- 		refill_pool(priv, ch, priv->bpid);
- 
--		store_cleaned = consume_frames(ch);
--		cleaned += store_cleaned;
-+		store_cleaned = consume_frames(ch, &rx_cleaned,
-+					       &tx_conf_cleaned);
- 
--		/* If we have enough budget left for a full store,
--		 * try a new pull dequeue, otherwise we're done here
-+		/* If we've either consumed the budget with Rx frames,
-+		 * or reached the Tx conf threshold, we're done.
- 		 */
--		if (store_cleaned == 0 ||
--		    cleaned > budget - DPAA2_ETH_STORE_SIZE)
--			break;
--	}
--
--	if (cleaned < budget) {
--		napi_complete_done(napi, cleaned);
--		/* Re-enable data available notifications */
--		do {
--			err = dpaa2_io_service_rearm(NULL, &ch->nctx);
--			cpu_relax();
--		} while (err == -EBUSY);
--	}
-+		if (rx_cleaned >= budget ||
-+		    tx_conf_cleaned >= TX_CONF_PER_NAPI_POLL)
-+			return budget;
-+	} while (store_cleaned);
- 
--	ch->stats.frames += cleaned;
-+	/* We didn't consume the entire budget, finish napi and
-+	 * re-enable data availability notifications
-+	 */
-+	napi_complete(napi);
-+	do {
-+		err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx);
-+		cpu_relax();
-+	} while (err == -EBUSY);
-+		WARN_ONCE(err, "CDAN notifications rearm failed on core %d",
-+			  ch->nctx.desired_cpu);
- 
--	return cleaned;
-+	return max(rx_cleaned, 1);
- }
- 
- static void enable_ch_napi(struct dpaa2_eth_priv *priv)
-@@ -1006,28 +1323,30 @@ static int dpaa2_eth_open(struct net_dev
- 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
- 	int err;
- 
--	err = seed_pool(priv, priv->bpid);
--	if (err) {
--		/* Not much to do; the buffer pool, though not filled up,
--		 * may still contain some buffers which would enable us
--		 * to limp on.
--		 */
--		netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
--			   priv->dpbp_dev->obj_desc.id, priv->bpid);
--	}
--
- 	/* We'll only start the txqs when the link is actually ready; make sure
- 	 * we don't race against the link up notification, which may come
- 	 * immediately after dpni_enable();
- 	 */
- 	netif_tx_stop_all_queues(net_dev);
--	enable_ch_napi(priv);
-+
- 	/* Also, explicitly set carrier off, otherwise netif_carrier_ok() will
- 	 * return true and cause 'ip link show' to report the LOWER_UP flag,
- 	 * even though the link notification wasn't even received.
- 	 */
- 	netif_carrier_off(net_dev);
- 
-+	err = seed_pool(priv, priv->bpid);
-+	if (err) {
-+		/* Not much to do; the buffer pool, though not filled up,
-+		 * may still contain some buffers which would enable us
-+		 * to limp on.
-+		 */
-+		netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
-+			   priv->dpbp_dev->obj_desc.id, priv->bpid);
-+	}
-+
-+	priv->refill_thresh = DPAA2_ETH_REFILL_THRESH(priv);
-+
- 	err = dpni_enable(priv->mc_io, 0, priv->mc_token);
- 	if (err < 0) {
- 		netdev_err(net_dev, "dpni_enable() failed\n");
-@@ -1047,48 +1366,17 @@ static int dpaa2_eth_open(struct net_dev
- 
- link_state_err:
- enable_err:
--	disable_ch_napi(priv);
-+	priv->refill_thresh = 0;
- 	drain_pool(priv);
- 	return err;
- }
- 
--/* The DPIO store must be empty when we call this,
-- * at the end of every NAPI cycle.
-- */
--static u32 drain_channel(struct dpaa2_eth_priv *priv,
--			 struct dpaa2_eth_channel *ch)
--{
--	u32 drained = 0, total = 0;
--
--	do {
--		pull_channel(ch);
--		drained = consume_frames(ch);
--		total += drained;
--	} while (drained);
--
--	return total;
--}
--
--static u32 drain_ingress_frames(struct dpaa2_eth_priv *priv)
--{
--	struct dpaa2_eth_channel *ch;
--	int i;
--	u32 drained = 0;
--
--	for (i = 0; i < priv->num_channels; i++) {
--		ch = priv->channel[i];
--		drained += drain_channel(priv, ch);
--	}
--
--	return drained;
--}
--
- static int dpaa2_eth_stop(struct net_device *net_dev)
- {
- 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
- 	int dpni_enabled;
--	int retries = 10;
--	u32 drained;
-+	int retries = 10, i;
-+	int err = 0;
- 
- 	netif_tx_stop_all_queues(net_dev);
- 	netif_carrier_off(net_dev);
-@@ -1105,56 +1393,24 @@ static int dpaa2_eth_stop(struct net_dev
- 	} while (dpni_enabled && --retries);
- 	if (!retries) {
- 		netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
--		/* Must go on and disable NAPI nonetheless, so we don't crash at
--		 * the next "ifconfig up"
-+		/* Must go on and finish processing pending frames, so we don't
-+		 * crash at the next "ifconfig up"
- 		 */
-+		err = -ETIMEDOUT;
- 	}
- 
--	/* Wait for NAPI to complete on every core and disable it.
--	 * In particular, this will also prevent NAPI from being rescheduled if
--	 * a new CDAN is serviced, effectively discarding the CDAN. We therefore
--	 * don't even need to disarm the channels, except perhaps for the case
--	 * of a huge coalescing value.
--	 */
--	disable_ch_napi(priv);
-+	priv->refill_thresh = 0;
- 
--	 /* Manually drain the Rx and TxConf queues */
--	drained = drain_ingress_frames(priv);
--	if (drained)
--		netdev_dbg(net_dev, "Drained %d frames.\n", drained);
-+	/* Wait for all running napi poll routines to finish, so that no
-+	 * new refill operations are started
-+	 */
-+	for (i = 0; i < priv->num_channels; i++)
-+		napi_synchronize(&priv->channel[i]->napi);
- 
- 	/* Empty the buffer pool */
- 	drain_pool(priv);
- 
--	return 0;
--}
--
--static int dpaa2_eth_init(struct net_device *net_dev)
--{
--	u64 supported = 0;
--	u64 not_supported = 0;
--	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
--	u32 options = priv->dpni_attrs.options;
--
--	/* Capabilities listing */
--	supported |= IFF_LIVE_ADDR_CHANGE;
--
--	if (options & DPNI_OPT_NO_MAC_FILTER)
--		not_supported |= IFF_UNICAST_FLT;
--	else
--		supported |= IFF_UNICAST_FLT;
--
--	net_dev->priv_flags |= supported;
--	net_dev->priv_flags &= ~not_supported;
--
--	/* Features */
--	net_dev->features = NETIF_F_RXCSUM |
--			    NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
--			    NETIF_F_SG | NETIF_F_HIGHDMA |
--			    NETIF_F_LLTX;
--	net_dev->hw_features = net_dev->features;
--
--	return 0;
-+	return err;
- }
- 
- static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
-@@ -1200,25 +1456,6 @@ static void dpaa2_eth_get_stats(struct n
- 	}
- }
- 
--static int dpaa2_eth_change_mtu(struct net_device *net_dev, int mtu)
--{
--	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
--	int err;
--
--	/* Set the maximum Rx frame length to match the transmit side;
--	 * account for L2 headers when computing the MFL
--	 */
--	err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
--					(u16)DPAA2_ETH_L2_MAX_FRM(mtu));
--	if (err) {
--		netdev_err(net_dev, "dpni_set_max_frame_length() failed\n");
--		return err;
--	}
--
--	net_dev->mtu = mtu;
--	return 0;
--}
--
- /* Copy mac unicast addresses from @net_dev to @priv.
-  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
-  */
-@@ -1380,16 +1617,363 @@ static int dpaa2_eth_set_features(struct
- 	return 0;
- }
- 
-+static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(dev);
-+	struct hwtstamp_config config;
-+
-+	if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
-+		return -EFAULT;
-+
-+	switch (config.tx_type) {
-+	case HWTSTAMP_TX_OFF:
-+		priv->ts_tx_en = false;
-+		break;
-+	case HWTSTAMP_TX_ON:
-+		priv->ts_tx_en = true;
-+		break;
-+	default:
-+		return -ERANGE;
-+	}
-+
-+	if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
-+		priv->ts_rx_en = false;
-+	} else {
-+		priv->ts_rx_en = true;
-+		/* TS is set for all frame types, not only those requested */
-+		config.rx_filter = HWTSTAMP_FILTER_ALL;
-+	}
-+
-+	return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
-+			-EFAULT : 0;
-+}
-+
-+static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-+{
-+	if (cmd == SIOCSHWTSTAMP)
-+		return dpaa2_eth_ts_ioctl(dev, rq, cmd);
-+
-+	return -EINVAL;
-+}
-+
-+static int set_buffer_layout(struct dpaa2_eth_priv *priv)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	struct dpni_buffer_layout buf_layout = {0};
-+	int err;
-+
-+	/* We need to check for WRIOP version 1.0.0, but depending on the MC
-+	 * version, this number is not always provided correctly on rev1.
-+	 * We need to check for both alternatives in this situation.
-+	 */
-+	if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) ||
-+	    priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0))
-+		priv->rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1;
-+	else
-+		priv->rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN;
-+
-+	/* tx buffer */
-+	buf_layout.pass_timestamp = true;
-+	buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
-+	buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP |
-+			     DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
-+	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
-+				     DPNI_QUEUE_TX, &buf_layout);
-+	if (err) {
-+		dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
-+		return err;
-+	}
-+
-+	/* tx-confirm buffer */
-+	buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
-+	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
-+				     DPNI_QUEUE_TX_CONFIRM, &buf_layout);
-+	if (err) {
-+		dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
-+		return err;
-+	}
-+
-+	/* Now that we've set our tx buffer layout, retrieve the minimum
-+	 * required tx data offset.
-+	 */
-+	err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
-+				      &priv->tx_data_offset);
-+	if (err) {
-+		dev_err(dev, "dpni_get_tx_data_offset() failed\n");
-+		return err;
-+	}
-+
-+	if ((priv->tx_data_offset % 64) != 0)
-+		dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
-+			 priv->tx_data_offset);
-+
-+	/* rx buffer */
-+	buf_layout.pass_frame_status = true;
-+	buf_layout.pass_parser_result = true;
-+	buf_layout.data_align = priv->rx_buf_align;
-+	buf_layout.private_data_size = 0;
-+	buf_layout.data_head_room = dpaa2_eth_rx_headroom(priv);
-+	/* If XDP program is attached, reserve extra space for
-+	 * potential header expansions
-+	 */
-+	if (priv->has_xdp_prog)
-+		buf_layout.data_head_room += XDP_PACKET_HEADROOM;
-+	buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
-+			     DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
-+			     DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
-+			     DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
-+			     DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
-+	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
-+				     DPNI_QUEUE_RX, &buf_layout);
-+	if (err) {
-+		dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static int dpaa2_eth_set_xdp(struct net_device *net_dev, struct bpf_prog *prog)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct dpaa2_eth_channel *ch;
-+	struct bpf_prog *old_prog = NULL;
-+	int i, err;
-+
-+	/* No support for SG frames */
-+	if (DPAA2_ETH_L2_MAX_FRM(net_dev->mtu) > DPAA2_ETH_RX_BUF_SIZE)
-+		return -EINVAL;
-+
-+	if (netif_running(net_dev)) {
-+		err = dpaa2_eth_stop(net_dev);
-+		if (err)
-+			return err;
-+	}
-+
-+	if (prog) {
-+		prog = bpf_prog_add(prog, priv->num_channels - 1);
-+		if (IS_ERR(prog))
-+			return PTR_ERR(prog);
-+	}
-+
-+	priv->has_xdp_prog = !!prog;
-+
-+	for (i = 0; i < priv->num_channels; i++) {
-+		ch = priv->channel[i];
-+		old_prog = xchg(&ch->xdp_prog, prog);
-+		if (old_prog)
-+			bpf_prog_put(old_prog);
-+	}
-+
-+	/* When turning XDP on/off we need to do some reconfiguring
-+	 * of the Rx buffer layout. Buffer pool was drained on dpaa2_eth_stop,
-+	 * so we are sure no old format buffers will be used from now on
-+	 */
-+	if (priv->has_xdp_prog != !!old_prog)
-+		set_buffer_layout(priv);
-+
-+	if (netif_running(net_dev)) {
-+		err = dpaa2_eth_open(net_dev);
-+		if (err)
-+			return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static int dpaa2_eth_xdp(struct net_device *dev, struct netdev_xdp *xdp)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(dev);
-+
-+	switch (xdp->command) {
-+	case XDP_SETUP_PROG:
-+		return dpaa2_eth_set_xdp(dev, xdp->prog);
-+	case XDP_QUERY_PROG:
-+		xdp->prog_attached = priv->has_xdp_prog;
-+		return 0;
-+	default:
-+		return -EINVAL;
-+	}
-+}
-+
-+static int dpaa2_eth_xdp_xmit(struct net_device *net_dev, struct xdp_buff *xdp)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct device *dev = net_dev->dev.parent;
-+	struct rtnl_link_stats64 *percpu_stats;
-+	struct dpaa2_eth_drv_stats *percpu_extras;
-+	unsigned int needed_headroom;
-+	struct dpaa2_eth_swa *swa;
-+	struct dpaa2_eth_fq *fq;
-+	struct dpaa2_fd fd;
-+	void *buffer_start, *aligned_start;
-+	dma_addr_t addr;
-+	int err, i;
-+
-+	if (!netif_running(net_dev))
-+		return -ENETDOWN;
-+
-+	/* We require a minimum headroom to be able to transmit the frame.
-+	 * Otherwise return an error and let the original net_device handle it
-+	 */
-+	/* TODO: Do we update i/f counters here or just on the Rx device? */
-+	needed_headroom = dpaa2_eth_needed_headroom(priv, NULL);
-+	if (xdp->data < xdp->data_hard_start ||
-+	    xdp->data - xdp->data_hard_start < needed_headroom) {
-+		percpu_stats->tx_dropped++;
-+		return -EINVAL;
-+	}
-+
-+	percpu_stats = this_cpu_ptr(priv->percpu_stats);
-+	percpu_extras = this_cpu_ptr(priv->percpu_extras);
-+
-+	/* Setup the FD fields */
-+	memset(&fd, 0, sizeof(fd));
-+
-+	/* Align FD address, if possible */
-+	buffer_start = xdp->data - needed_headroom;
-+	aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
-+				  DPAA2_ETH_TX_BUF_ALIGN);
-+	if (aligned_start >= xdp->data_hard_start)
-+		buffer_start = aligned_start;
-+
-+	swa = (struct dpaa2_eth_swa *)buffer_start;
-+	/* fill in necessary fields here */
-+	swa->type = DPAA2_ETH_SWA_XDP;
-+	swa->xdp.dma_size = xdp->data_end - buffer_start;
-+
-+	addr = dma_map_single(dev, buffer_start,
-+			      xdp->data_end - buffer_start,
-+			      DMA_BIDIRECTIONAL);
-+	if (unlikely(dma_mapping_error(dev, addr))) {
-+		percpu_stats->tx_dropped++;
-+		return -ENOMEM;
-+	}
-+
-+	dpaa2_fd_set_addr(&fd, addr);
-+	dpaa2_fd_set_offset(&fd, xdp->data - buffer_start);
-+	dpaa2_fd_set_len(&fd, xdp->data_end - xdp->data);
-+	dpaa2_fd_set_format(&fd, dpaa2_fd_single);
-+	dpaa2_fd_set_ctrl(&fd, FD_CTRL_PTA);
-+
-+	fq = &priv->fq[smp_processor_id()];
-+	for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
-+		err = dpaa2_io_service_enqueue_qd(NULL, priv->tx_qdid, 0,
-+						  fq->tx_qdbin, &fd);
-+		if (err != -EBUSY)
-+			break;
-+	}
-+	percpu_extras->tx_portal_busy += i;
-+	if (unlikely(err < 0)) {
-+		percpu_stats->tx_errors++;
-+		/* let the Rx device handle the cleanup */
-+		return err;
-+	}
-+
-+	percpu_stats->tx_packets++;
-+	percpu_stats->tx_bytes += dpaa2_fd_get_len(&fd);
-+
-+	return 0;
-+}
-+
-+static void dpaa2_eth_xdp_flush(struct net_device *net_dev)
-+{
-+	/* We don't have hardware support for Tx batching,
-+	 * so we do the actual frame enqueue in ndo_xdp_xmit
-+	 */
-+}
-+
-+static int dpaa2_eth_update_xps(struct dpaa2_eth_priv *priv)
-+{
-+	struct net_device *net_dev = priv->net_dev;
-+	unsigned int i, num_queues;
-+	struct cpumask xps_mask;
-+	struct dpaa2_eth_fq *fq;
-+	int err = 0;
-+
-+	num_queues = (net_dev->num_tc ? : 1) * dpaa2_eth_queue_count(priv);
-+	for (i = 0; i < num_queues; i++) {
-+		fq = &priv->fq[i % dpaa2_eth_queue_count(priv)];
-+		cpumask_clear(&xps_mask);
-+		cpumask_set_cpu(fq->target_cpu, &xps_mask);
-+		err = netif_set_xps_queue(net_dev, &xps_mask, i);
-+		if (err) {
-+			dev_info_once(net_dev->dev.parent,
-+				      "Error setting XPS queue\n");
-+			break;
-+		}
-+	}
-+
-+	return err;
-+}
-+
-+static int dpaa2_eth_setup_tc(struct net_device *net_dev,
-+			      enum tc_setup_type type,
-+			      void *type_data)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct tc_mqprio_qopt *mqprio = (struct tc_mqprio_qopt *)type_data;
-+	int i, err = 0;
-+
-+	if (type != TC_SETUP_MQPRIO)
-+		return -EINVAL;
-+
-+	if (mqprio->num_tc > dpaa2_eth_tc_count(priv)) {
-+		netdev_err(net_dev, "Max %d traffic classes supported\n",
-+			   dpaa2_eth_tc_count(priv));
-+		return -EINVAL;
-+	}
-+
-+	if (mqprio->num_tc == net_dev->num_tc)
-+		return 0;
-+
-+	mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
-+
-+	if (!mqprio->num_tc) {
-+		netdev_reset_tc(net_dev);
-+		err = netif_set_real_num_tx_queues(net_dev,
-+						   dpaa2_eth_queue_count(priv));
-+		if (err)
-+			return err;
-+
-+		goto update_xps;
-+	}
-+
-+	err = netdev_set_num_tc(net_dev, mqprio->num_tc);
-+	if (err)
-+		return err;
-+
-+	err = netif_set_real_num_tx_queues(net_dev, mqprio->num_tc *
-+					   dpaa2_eth_queue_count(priv));
-+	if (err)
-+		return err;
-+
-+	for (i = 0; i < mqprio->num_tc; i++) {
-+		err = netdev_set_tc_queue(net_dev, i,
-+					  dpaa2_eth_queue_count(priv),
-+					  i * dpaa2_eth_queue_count(priv));
-+		if (err)
-+			return err;
-+	}
-+
-+update_xps:
-+	err = dpaa2_eth_update_xps(priv);
-+	return err;
-+}
-+
- static const struct net_device_ops dpaa2_eth_ops = {
- 	.ndo_open = dpaa2_eth_open,
- 	.ndo_start_xmit = dpaa2_eth_tx,
- 	.ndo_stop = dpaa2_eth_stop,
--	.ndo_init = dpaa2_eth_init,
- 	.ndo_set_mac_address = dpaa2_eth_set_addr,
- 	.ndo_get_stats64 = dpaa2_eth_get_stats,
--	.ndo_change_mtu = dpaa2_eth_change_mtu,
- 	.ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
- 	.ndo_set_features = dpaa2_eth_set_features,
-+	.ndo_do_ioctl = dpaa2_eth_ioctl,
-+	.ndo_xdp = dpaa2_eth_xdp,
-+	.ndo_xdp_xmit = dpaa2_eth_xdp_xmit,
-+	.ndo_xdp_flush = dpaa2_eth_xdp_flush,
-+	.ndo_setup_tc = dpaa2_eth_setup_tc,
- };
- 
- static void cdan_cb(struct dpaa2_io_notification_ctx *ctx)
-@@ -1422,34 +2006,32 @@ static struct fsl_mc_device *setup_dpcon
- 	err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
- 	if (err) {
- 		dev_err(dev, "dpcon_open() failed\n");
--		goto err_open;
-+		goto free;
- 	}
- 
- 	err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
- 	if (err) {
- 		dev_err(dev, "dpcon_reset() failed\n");
--		goto err_reset;
-+		goto close;
- 	}
- 
- 	err = dpcon_get_attributes(priv->mc_io, 0, dpcon->mc_handle, &attrs);
- 	if (err) {
- 		dev_err(dev, "dpcon_get_attributes() failed\n");
--		goto err_get_attr;
-+		goto close;
- 	}
- 
- 	err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
- 	if (err) {
- 		dev_err(dev, "dpcon_enable() failed\n");
--		goto err_enable;
-+		goto close;
- 	}
- 
- 	return dpcon;
- 
--err_enable:
--err_get_attr:
--err_reset:
-+close:
- 	dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
--err_open:
-+free:
- 	fsl_mc_object_free(dpcon);
- 
- 	return NULL;
-@@ -1502,7 +2084,14 @@ err_setup:
- static void free_channel(struct dpaa2_eth_priv *priv,
- 			 struct dpaa2_eth_channel *channel)
- {
-+	struct bpf_prog *prog;
-+
- 	free_dpcon(priv, channel->dpcon);
-+
-+	prog = READ_ONCE(channel->xdp_prog);
-+	if (prog)
-+		bpf_prog_put(prog);
-+
- 	kfree(channel);
- }
- 
-@@ -1546,7 +2135,8 @@ static int setup_dpio(struct dpaa2_eth_p
- 		nctx->desired_cpu = i;
- 
- 		/* Register the new context */
--		err = dpaa2_io_service_register(NULL, nctx);
-+		channel->dpio = dpaa2_io_service_select(i);
-+		err = dpaa2_io_service_register(channel->dpio, nctx);
- 		if (err) {
- 			dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
- 			/* If no affine DPIO for this core, there's probably
-@@ -1586,7 +2176,7 @@ static int setup_dpio(struct dpaa2_eth_p
- 	return 0;
- 
- err_set_cdan:
--	dpaa2_io_service_deregister(NULL, nctx);
-+	dpaa2_io_service_deregister(channel->dpio, nctx);
- err_service_reg:
- 	free_channel(priv, channel);
- err_alloc_ch:
-@@ -1609,7 +2199,7 @@ static void free_dpio(struct dpaa2_eth_p
- 	/* deregister CDAN notifications and free channels */
- 	for (i = 0; i < priv->num_channels; i++) {
- 		ch = priv->channel[i];
--		dpaa2_io_service_deregister(NULL, &ch->nctx);
-+		dpaa2_io_service_deregister(ch->dpio, &ch->nctx);
- 		free_channel(priv, ch);
- 	}
- }
-@@ -1636,8 +2226,7 @@ static void set_fq_affinity(struct dpaa2
- {
- 	struct device *dev = priv->net_dev->dev.parent;
- 	struct dpaa2_eth_fq *fq;
--	int rx_cpu, txc_cpu;
--	int i;
-+	int rx_cpu, txc_cpu, i;
- 
- 	/* For each FQ, pick one channel/CPU to deliver frames to.
- 	 * This may well change at runtime, either through irqbalance or
-@@ -1649,6 +2238,7 @@ static void set_fq_affinity(struct dpaa2
- 		fq = &priv->fq[i];
- 		switch (fq->type) {
- 		case DPAA2_RX_FQ:
-+		case DPAA2_RX_ERR_FQ:
- 			fq->target_cpu = rx_cpu;
- 			rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
- 			if (rx_cpu >= nr_cpu_ids)
-@@ -1656,6 +2246,7 @@ static void set_fq_affinity(struct dpaa2
- 			break;
- 		case DPAA2_TX_CONF_FQ:
- 			fq->target_cpu = txc_cpu;
-+
- 			txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
- 			if (txc_cpu >= nr_cpu_ids)
- 				txc_cpu = cpumask_first(&priv->dpio_cpumask);
-@@ -1665,11 +2256,13 @@ static void set_fq_affinity(struct dpaa2
- 		}
- 		fq->channel = get_affine_channel(priv, fq->target_cpu);
- 	}
-+
-+	dpaa2_eth_update_xps(priv);
- }
- 
- static void setup_fqs(struct dpaa2_eth_priv *priv)
- {
--	int i;
-+	int i, j;
- 
- 	/* We have one TxConf FQ per Tx flow.
- 	 * The number of Tx and Rx queues is the same.
-@@ -1681,11 +2274,19 @@ static void setup_fqs(struct dpaa2_eth_p
- 		priv->fq[priv->num_fqs++].flowid = (u16)i;
- 	}
- 
--	for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
--		priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
--		priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
--		priv->fq[priv->num_fqs++].flowid = (u16)i;
--	}
-+	for (i = 0; i < dpaa2_eth_tc_count(priv); i++)
-+		for (j = 0; j < dpaa2_eth_queue_count(priv); j++) {
-+			priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
-+			priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
-+			priv->fq[priv->num_fqs].tc = (u8)i;
-+			priv->fq[priv->num_fqs++].flowid = (u16)j;
-+		}
-+
-+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
-+	/* We have exactly one Rx error queue per DPNI */
-+	priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ;
-+	priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err;
-+#endif
- 
- 	/* For each FQ, decide on which core to process incoming frames */
- 	set_fq_affinity(priv);
-@@ -1735,6 +2336,9 @@ static int setup_dpbp(struct dpaa2_eth_p
- 	}
- 	priv->bpid = dpbp_attrs.bpid;
- 
-+	/* By default we start with flow control enabled */
-+	priv->max_bufs_per_ch = DPAA2_ETH_NUM_BUFS_FC / priv->num_channels;
-+
- 	return 0;
- 
- err_get_attr:
-@@ -1756,13 +2360,59 @@ static void free_dpbp(struct dpaa2_eth_p
- 	fsl_mc_object_free(priv->dpbp_dev);
- }
- 
-+static int setup_tx_congestion(struct dpaa2_eth_priv *priv)
-+{
-+	struct dpni_congestion_notification_cfg notif_cfg = {0};
-+	struct device *dev = priv->net_dev->dev.parent;
-+	int err;
-+
-+	priv->cscn_unaligned = kzalloc(DPAA2_CSCN_SIZE + DPAA2_CSCN_ALIGN,
-+				       GFP_KERNEL);
-+
-+	if (!priv->cscn_unaligned)
-+		return -ENOMEM;
-+
-+	priv->cscn_mem = PTR_ALIGN(priv->cscn_unaligned, DPAA2_CSCN_ALIGN);
-+	priv->cscn_dma = dma_map_single(dev, priv->cscn_mem, DPAA2_CSCN_SIZE,
-+					DMA_FROM_DEVICE);
-+	if (dma_mapping_error(dev, priv->cscn_dma)) {
-+		dev_err(dev, "Error mapping CSCN memory area\n");
-+		err = -ENOMEM;
-+		goto err_dma_map;
-+	}
-+
-+	notif_cfg.units = DPNI_CONGESTION_UNIT_BYTES;
-+	notif_cfg.threshold_entry = DPAA2_ETH_TX_CONG_ENTRY_THRESH;
-+	notif_cfg.threshold_exit = DPAA2_ETH_TX_CONG_EXIT_THRESH;
-+	notif_cfg.message_ctx = (u64)priv;
-+	notif_cfg.message_iova = priv->cscn_dma;
-+	notif_cfg.notification_mode = DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
-+				      DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
-+				      DPNI_CONG_OPT_COHERENT_WRITE;
-+	err = dpni_set_congestion_notification(priv->mc_io, 0, priv->mc_token,
-+					       DPNI_QUEUE_TX, 0, &notif_cfg);
-+	if (err) {
-+		dev_err(dev, "dpni_set_congestion_notification failed\n");
-+		goto err_set_cong;
-+	}
-+
-+	return 0;
-+
-+err_set_cong:
-+	dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
-+err_dma_map:
-+	kfree(priv->cscn_unaligned);
-+
-+	return err;
-+}
-+
- /* Configure the DPNI object this interface is associated with */
- static int setup_dpni(struct fsl_mc_device *ls_dev)
- {
- 	struct device *dev = &ls_dev->dev;
- 	struct dpaa2_eth_priv *priv;
- 	struct net_device *net_dev;
--	struct dpni_buffer_layout buf_layout = {0};
-+	struct dpni_link_cfg cfg = {0};
- 	int err;
- 
- 	net_dev = dev_get_drvdata(dev);
-@@ -1772,7 +2422,22 @@ static int setup_dpni(struct fsl_mc_devi
- 	err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
- 	if (err) {
- 		dev_err(dev, "dpni_open() failed\n");
--		goto err_open;
-+		return err;
-+	}
-+
-+	/* Check if we can work with this DPNI object */
-+	err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major,
-+				   &priv->dpni_ver_minor);
-+	if (err) {
-+		dev_err(dev, "dpni_get_api_version() failed\n");
-+		goto close;
-+	}
-+	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) {
-+		dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n",
-+			priv->dpni_ver_major, priv->dpni_ver_minor,
-+			DPNI_VER_MAJOR, DPNI_VER_MINOR);
-+		err = -ENOTSUPP;
-+		goto close;
- 	}
- 
- 	ls_dev->mc_io = priv->mc_io;
-@@ -1781,82 +2446,53 @@ static int setup_dpni(struct fsl_mc_devi
- 	err = dpni_reset(priv->mc_io, 0, priv->mc_token);
- 	if (err) {
- 		dev_err(dev, "dpni_reset() failed\n");
--		goto err_reset;
-+		goto close;
- 	}
- 
- 	err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
- 				  &priv->dpni_attrs);
- 	if (err) {
- 		dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
--		goto err_get_attr;
-+		goto close;
- 	}
- 
--	/* Configure buffer layouts */
--	/* rx buffer */
--	buf_layout.pass_parser_result = true;
--	buf_layout.pass_frame_status = true;
--	buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
--	buf_layout.data_align = DPAA2_ETH_RX_BUF_ALIGN;
--	buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
--			     DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
--			     DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
--			     DPNI_BUF_LAYOUT_OPT_DATA_ALIGN;
--	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
--				     DPNI_QUEUE_RX, &buf_layout);
--	if (err) {
--		dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
--		goto err_buf_layout;
--	}
-+	err = set_buffer_layout(priv);
-+	if (err)
-+		goto close;
- 
--	/* tx buffer */
--	buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
--			     DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
--	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
--				     DPNI_QUEUE_TX, &buf_layout);
--	if (err) {
--		dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
--		goto err_buf_layout;
--	}
-+	/* Enable congestion notifications for Tx queues */
-+	err = setup_tx_congestion(priv);
-+	if (err)
-+		goto close;
- 
--	/* tx-confirm buffer */
--	buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
--	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
--				     DPNI_QUEUE_TX_CONFIRM, &buf_layout);
--	if (err) {
--		dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
--		goto err_buf_layout;
--	}
-+	/* allocate classification rule space */
-+	priv->cls_rule = kzalloc(sizeof(*priv->cls_rule) *
-+				 dpaa2_eth_fs_count(priv), GFP_KERNEL);
-+	if (!priv->cls_rule)
-+		goto close;
- 
--	/* Now that we've set our tx buffer layout, retrieve the minimum
--	 * required tx data offset.
--	 */
--	err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
--				      &priv->tx_data_offset);
-+	/* Enable flow control */
-+	cfg.options = DPNI_LINK_OPT_AUTONEG | DPNI_LINK_OPT_PAUSE;
-+	priv->tx_pause_frames = true;
-+	err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &cfg);
- 	if (err) {
--		dev_err(dev, "dpni_get_tx_data_offset() failed\n");
--		goto err_data_offset;
-+		dev_err(dev, "dpni_set_link_cfg() failed\n");
-+		goto cls_free;
- 	}
- 
--	if ((priv->tx_data_offset % 64) != 0)
--		dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
--			 priv->tx_data_offset);
--
--	/* Accommodate software annotation space (SWA) */
--	priv->tx_data_offset += DPAA2_ETH_SWA_SIZE;
--
- 	return 0;
- 
--err_data_offset:
--err_buf_layout:
--err_get_attr:
--err_reset:
-+cls_free:
-+	kfree(priv->cls_rule);
-+close:
- 	dpni_close(priv->mc_io, 0, priv->mc_token);
--err_open:
-+
- 	return err;
- }
- 
- static void free_dpni(struct dpaa2_eth_priv *priv)
- {
-+	struct device *dev = priv->net_dev->dev.parent;
- 	int err;
- 
- 	err = dpni_reset(priv->mc_io, 0, priv->mc_token);
-@@ -1865,6 +2501,11 @@ static void free_dpni(struct dpaa2_eth_p
- 			    err);
- 
- 	dpni_close(priv->mc_io, 0, priv->mc_token);
-+
-+	kfree(priv->cls_rule);
-+
-+	dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
-+	kfree(priv->cscn_unaligned);
- }
- 
- static int setup_rx_flow(struct dpaa2_eth_priv *priv,
-@@ -1873,11 +2514,10 @@ static int setup_rx_flow(struct dpaa2_et
- 	struct device *dev = priv->net_dev->dev.parent;
- 	struct dpni_queue queue;
- 	struct dpni_queue_id qid;
--	struct dpni_taildrop td;
- 	int err;
- 
- 	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
--			     DPNI_QUEUE_RX, 0, fq->flowid, &queue, &qid);
-+			     DPNI_QUEUE_RX, fq->tc, fq->flowid, &queue, &qid);
- 	if (err) {
- 		dev_err(dev, "dpni_get_queue(RX) failed\n");
- 		return err;
-@@ -1890,7 +2530,7 @@ static int setup_rx_flow(struct dpaa2_et
- 	queue.destination.priority = 1;
- 	queue.user_context = (u64)(uintptr_t)fq;
- 	err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
--			     DPNI_QUEUE_RX, 0, fq->flowid,
-+			     DPNI_QUEUE_RX, fq->tc, fq->flowid,
- 			     DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
- 			     &queue);
- 	if (err) {
-@@ -1898,15 +2538,121 @@ static int setup_rx_flow(struct dpaa2_et
- 		return err;
- 	}
- 
--	td.enable = 1;
--	td.threshold = DPAA2_ETH_TAILDROP_THRESH;
--	err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token, DPNI_CP_QUEUE,
--				DPNI_QUEUE_RX, 0, fq->flowid, &td);
--	if (err) {
--		dev_err(dev, "dpni_set_threshold() failed\n");
--		return err;
-+	return 0;
-+}
-+
-+static int set_queue_taildrop(struct dpaa2_eth_priv *priv,
-+			      struct dpni_taildrop *td)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	int i, err;
-+
-+	for (i = 0; i < priv->num_fqs; i++) {
-+		if (priv->fq[i].type != DPAA2_RX_FQ)
-+			continue;
-+
-+		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
-+					DPNI_CP_QUEUE, DPNI_QUEUE_RX,
-+					priv->fq[i].tc, priv->fq[i].flowid,
-+					td);
-+		if (err) {
-+			dev_err(dev, "dpni_set_taildrop() failed (%d)\n", err);
-+			return err;
-+		}
-+
-+		dev_dbg(dev, "%s taildrop for Rx queue id %d tc %d\n",
-+			(td->enable ? "Enabled" : "Disabled"),
-+			priv->fq[i].flowid, priv->fq[i].tc);
-+	}
-+
-+	return 0;
-+}
-+
-+static int set_group_taildrop(struct dpaa2_eth_priv *priv,
-+			      struct dpni_taildrop *td)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	struct dpni_taildrop disable_td, *tc_td;
-+	int i, err;
-+
-+	memset(&disable_td, 0, sizeof(struct dpni_taildrop));
-+	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
-+		if (td->enable && dpaa2_eth_is_pfc_enabled(priv, i))
-+			/* Do not set taildrop thresholds for PFC-enabled
-+			 * traffic classes. We will enable congestion
-+			 * notifications for them.
-+			 */
-+			tc_td = &disable_td;
-+		else
-+			tc_td = td;
-+
-+		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
-+					DPNI_CP_GROUP, DPNI_QUEUE_RX,
-+					i, 0, tc_td);
-+		if (err) {
-+			dev_err(dev, "dpni_set_taildrop() failed (%d)\n", err);
-+			return err;
-+		}
-+
-+		dev_dbg(dev, "%s taildrop for Rx group tc %d\n",
-+			(tc_td->enable ? "Enabled" : "Disabled"),
-+			i);
-+	}
-+
-+	return 0;
-+}
-+
-+/* Enable/disable Rx FQ taildrop
-+ *
-+ * Rx FQ taildrop is mutually exclusive with flow control and it only gets
-+ * disabled when FC is active. Depending on FC status, we need to compute
-+ * the maximum number of buffers in the pool differently, so use the
-+ * opportunity to update max number of buffers as well.
-+ */
-+int set_rx_taildrop(struct dpaa2_eth_priv *priv)
-+{
-+	enum dpaa2_eth_td_cfg cfg = dpaa2_eth_get_td_type(priv);
-+	struct dpni_taildrop td_queue, td_group;
-+	int err = 0;
-+
-+	switch (cfg) {
-+	case DPAA2_ETH_TD_NONE:
-+		memset(&td_queue, 0, sizeof(struct dpni_taildrop));
-+		memset(&td_group, 0, sizeof(struct dpni_taildrop));
-+		priv->max_bufs_per_ch = DPAA2_ETH_NUM_BUFS_FC /
-+					priv->num_channels;
-+		break;
-+	case DPAA2_ETH_TD_QUEUE:
-+		memset(&td_group, 0, sizeof(struct dpni_taildrop));
-+		td_queue.enable = 1;
-+		td_queue.units = DPNI_CONGESTION_UNIT_BYTES;
-+		td_queue.threshold = DPAA2_ETH_TAILDROP_THRESH /
-+				     dpaa2_eth_tc_count(priv);
-+		priv->max_bufs_per_ch = DPAA2_ETH_NUM_BUFS_PER_CH;
-+		break;
-+	case DPAA2_ETH_TD_GROUP:
-+		memset(&td_queue, 0, sizeof(struct dpni_taildrop));
-+		td_group.enable = 1;
-+		td_group.units = DPNI_CONGESTION_UNIT_FRAMES;
-+		td_group.threshold = NAPI_POLL_WEIGHT *
-+				     dpaa2_eth_queue_count(priv);
-+		priv->max_bufs_per_ch = NAPI_POLL_WEIGHT *
-+					dpaa2_eth_tc_count(priv);
-+		break;
-+	default:
-+		break;
- 	}
- 
-+	err = set_queue_taildrop(priv, &td_queue);
-+	if (err)
-+		return err;
-+
-+	err = set_group_taildrop(priv, &td_group);
-+	if (err)
-+		return err;
-+
-+	priv->refill_thresh = DPAA2_ETH_REFILL_THRESH(priv);
-+
- 	return 0;
- }
- 
-@@ -1953,23 +2699,88 @@ static int setup_tx_flow(struct dpaa2_et
- 	return 0;
- }
- 
--/* Hash key is a 5-tuple: IPsrc, IPdst, IPnextproto, L4src, L4dst */
--static const struct dpaa2_eth_hash_fields hash_fields[] = {
-+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
-+static int setup_rx_err_flow(struct dpaa2_eth_priv *priv,
-+			     struct dpaa2_eth_fq *fq)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	struct dpni_queue q = { { 0 } };
-+	struct dpni_queue_id qid;
-+	u8 q_opt = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST;
-+	int err;
-+
-+	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
-+			     DPNI_QUEUE_RX_ERR, 0, 0, &q, &qid);
-+	if (err) {
-+		dev_err(dev, "dpni_get_queue() failed (%d)\n", err);
-+		return err;
-+	}
-+
-+	fq->fqid = qid.fqid;
-+
-+	q.destination.id = fq->channel->dpcon_id;
-+	q.destination.type = DPNI_DEST_DPCON;
-+	q.destination.priority = 1;
-+	q.user_context = (u64)fq;
-+	err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
-+			     DPNI_QUEUE_RX_ERR, 0, 0, q_opt, &q);
-+	if (err) {
-+		dev_err(dev, "dpni_set_queue() failed (%d)\n", err);
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+#endif
-+
-+/* default hash key fields */
-+static struct dpaa2_eth_dist_fields default_dist_fields[] = {
- 	{
-+		/* L2 header */
-+		.rxnfc_field = RXH_L2DA,
-+		.cls_prot = NET_PROT_ETH,
-+		.cls_field = NH_FLD_ETH_DA,
-+		.id = DPAA2_ETH_DIST_ETHDST,
-+		.size = 6,
-+	}, {
-+		.cls_prot = NET_PROT_ETH,
-+		.cls_field = NH_FLD_ETH_SA,
-+		.id = DPAA2_ETH_DIST_ETHSRC,
-+		.size = 6,
-+	}, {
-+		/* This is the last ethertype field parsed:
-+		 * depending on frame format, it can be the MAC ethertype
-+		 * or the VLAN etype.
-+		 */
-+		.cls_prot = NET_PROT_ETH,
-+		.cls_field = NH_FLD_ETH_TYPE,
-+		.id = DPAA2_ETH_DIST_ETHTYPE,
-+		.size = 2,
-+	}, {
-+		/* VLAN header */
-+		.rxnfc_field = RXH_VLAN,
-+		.cls_prot = NET_PROT_VLAN,
-+		.cls_field = NH_FLD_VLAN_TCI,
-+		.id = DPAA2_ETH_DIST_VLAN,
-+		.size = 2,
-+	}, {
- 		/* IP header */
- 		.rxnfc_field = RXH_IP_SRC,
- 		.cls_prot = NET_PROT_IP,
- 		.cls_field = NH_FLD_IP_SRC,
-+		.id = DPAA2_ETH_DIST_IPSRC,
- 		.size = 4,
- 	}, {
- 		.rxnfc_field = RXH_IP_DST,
- 		.cls_prot = NET_PROT_IP,
- 		.cls_field = NH_FLD_IP_DST,
-+		.id = DPAA2_ETH_DIST_IPDST,
- 		.size = 4,
- 	}, {
- 		.rxnfc_field = RXH_L3_PROTO,
- 		.cls_prot = NET_PROT_IP,
- 		.cls_field = NH_FLD_IP_PROTO,
-+		.id = DPAA2_ETH_DIST_IPPROTO,
- 		.size = 1,
- 	}, {
- 		/* Using UDP ports, this is functionally equivalent to raw
-@@ -1978,90 +2789,182 @@ static const struct dpaa2_eth_hash_field
- 		.rxnfc_field = RXH_L4_B_0_1,
- 		.cls_prot = NET_PROT_UDP,
- 		.cls_field = NH_FLD_UDP_PORT_SRC,
-+		.id = DPAA2_ETH_DIST_L4SRC,
- 		.size = 2,
- 	}, {
- 		.rxnfc_field = RXH_L4_B_2_3,
- 		.cls_prot = NET_PROT_UDP,
- 		.cls_field = NH_FLD_UDP_PORT_DST,
-+		.id = DPAA2_ETH_DIST_L4DST,
- 		.size = 2,
- 	},
- };
- 
--/* Set RX hash options
-- * flags is a combination of RXH_ bits
-- */
--static int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags)
-+static int legacy_config_dist_key(struct dpaa2_eth_priv *priv,
-+				  dma_addr_t key_iova)
- {
--	struct device *dev = net_dev->dev.parent;
--	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
--	struct dpkg_profile_cfg cls_cfg;
-+	struct device *dev = priv->net_dev->dev.parent;
- 	struct dpni_rx_tc_dist_cfg dist_cfg;
--	u8 *dma_mem;
--	int i;
--	int err = 0;
-+	int i, err;
- 
--	if (!dpaa2_eth_hash_enabled(priv)) {
--		dev_dbg(dev, "Hashing support is not enabled\n");
--		return 0;
-+	/* In legacy mode, we can't configure flow steering independently */
-+	if (!dpaa2_eth_hash_enabled(priv))
-+		return -EOPNOTSUPP;
-+
-+	memset(&dist_cfg, 0, sizeof(dist_cfg));
-+
-+	dist_cfg.key_cfg_iova = key_iova;
-+	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
-+	if (dpaa2_eth_fs_enabled(priv)) {
-+		dist_cfg.dist_mode = DPNI_DIST_MODE_FS;
-+		dist_cfg.fs_cfg.miss_action = DPNI_FS_MISS_HASH;
-+	} else {
-+		dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
- 	}
- 
--	memset(&cls_cfg, 0, sizeof(cls_cfg));
-+	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
-+		err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token, i,
-+					  &dist_cfg);
-+		if (err) {
-+			dev_err(dev, "dpni_set_rx_tc_dist failed\n");
-+			return err;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int config_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key_iova)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	struct dpni_rx_dist_cfg dist_cfg;
-+	int i, err;
- 
--	for (i = 0; i < ARRAY_SIZE(hash_fields); i++) {
--		struct dpkg_extract *key =
--			&cls_cfg.extracts[cls_cfg.num_extracts];
-+	if (!dpaa2_eth_hash_enabled(priv))
-+		return -EOPNOTSUPP;
- 
--		if (!(flags & hash_fields[i].rxnfc_field))
--			continue;
-+	memset(&dist_cfg, 0, sizeof(dist_cfg));
-+
-+	dist_cfg.key_cfg_iova = key_iova;
-+	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
-+	dist_cfg.enable = true;
-+
-+	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
-+		dist_cfg.tc = i;
-+
-+		err = dpni_set_rx_hash_dist(priv->mc_io, 0,
-+					    priv->mc_token, &dist_cfg);
-+		if (err) {
-+			dev_err(dev, "dpni_set_rx_hash_dist failed\n");
-+			return err;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int config_fs_key(struct dpaa2_eth_priv *priv, dma_addr_t key_iova)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	struct dpni_rx_dist_cfg dist_cfg;
-+	int i, err;
- 
--		if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) {
--			dev_err(dev, "error adding key extraction rule, too many rules?\n");
--			return -E2BIG;
-+	if (!dpaa2_eth_fs_enabled(priv))
-+		return -EOPNOTSUPP;
-+
-+	memset(&dist_cfg, 0, sizeof(dist_cfg));
-+
-+	dist_cfg.key_cfg_iova = key_iova;
-+	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
-+	dist_cfg.enable = true;
-+
-+	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
-+		dist_cfg.tc = i;
-+
-+		err = dpni_set_rx_fs_dist(priv->mc_io, 0,
-+					  priv->mc_token, &dist_cfg);
-+		if (err) {
-+			dev_err(dev, "dpni_set_rx_fs_dist failed\n");
-+			return err;
- 		}
-+	}
-+
-+	return 0;
-+}
- 
-+int dpaa2_eth_set_dist_key(struct dpaa2_eth_priv *priv,
-+			   enum dpaa2_eth_rx_dist type, u32 key_fields)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	struct dpkg_profile_cfg cls_cfg;
-+	struct dpkg_extract *key;
-+	u32 hash_fields = 0;
-+	dma_addr_t key_iova;
-+	u8 *key_mem;
-+	int i, err;
-+
-+	memset(&cls_cfg, 0, sizeof(cls_cfg));
-+
-+	for (i = 0; i < priv->num_dist_fields; i++) {
-+		if (!(key_fields & priv->dist_fields[i].id))
-+			continue;
-+
-+		key = &cls_cfg.extracts[cls_cfg.num_extracts];
- 		key->type = DPKG_EXTRACT_FROM_HDR;
--		key->extract.from_hdr.prot = hash_fields[i].cls_prot;
-+		key->extract.from_hdr.prot = priv->dist_fields[i].cls_prot;
- 		key->extract.from_hdr.type = DPKG_FULL_FIELD;
--		key->extract.from_hdr.field = hash_fields[i].cls_field;
-+		key->extract.from_hdr.field = priv->dist_fields[i].cls_field;
- 		cls_cfg.num_extracts++;
- 
--		priv->rx_hash_fields |= hash_fields[i].rxnfc_field;
-+		hash_fields |= priv->dist_fields[i].rxnfc_field;
- 	}
- 
--	dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
--	if (!dma_mem)
-+	key_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
-+	if (!key_mem)
- 		return -ENOMEM;
- 
--	err = dpni_prepare_key_cfg(&cls_cfg, dma_mem);
-+	err = dpni_prepare_key_cfg(&cls_cfg, key_mem);
- 	if (err) {
- 		dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
--		goto err_prep_key;
-+		goto free_key;
- 	}
- 
--	memset(&dist_cfg, 0, sizeof(dist_cfg));
--
--	/* Prepare for setting the rx dist */
--	dist_cfg.key_cfg_iova = dma_map_single(dev, dma_mem,
--					       DPAA2_CLASSIFIER_DMA_SIZE,
--					       DMA_TO_DEVICE);
--	if (dma_mapping_error(dev, dist_cfg.key_cfg_iova)) {
-+	key_iova = dma_map_single(dev, key_mem, DPAA2_CLASSIFIER_DMA_SIZE,
-+				  DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, key_iova)) {
- 		dev_err(dev, "DMA mapping failed\n");
- 		err = -ENOMEM;
--		goto err_dma_map;
-+		goto free_key;
- 	}
- 
--	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
--	dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
-+	switch (type) {
-+	case DPAA2_ETH_RX_DIST_LEGACY:
-+		err = legacy_config_dist_key(priv, key_iova);
-+		break;
-+	case DPAA2_ETH_RX_DIST_HASH:
-+		err = config_hash_key(priv, key_iova);
-+		break;
-+	case DPAA2_ETH_RX_DIST_FS:
-+		err = config_fs_key(priv, key_iova);
-+		break;
-+	default:
-+		err = -EINVAL;
-+		break;
-+	}
- 
--	err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token, 0, &dist_cfg);
--	dma_unmap_single(dev, dist_cfg.key_cfg_iova,
--			 DPAA2_CLASSIFIER_DMA_SIZE, DMA_TO_DEVICE);
--	if (err)
--		dev_err(dev, "dpni_set_rx_tc_dist() error %d\n", err);
-+	dma_unmap_single(dev, key_iova, DPAA2_CLASSIFIER_DMA_SIZE,
-+			 DMA_TO_DEVICE);
-+	if (err) {
-+		if (err != -EOPNOTSUPP)
-+			dev_err(dev, "Distribution key config failed\n");
-+		goto free_key;
-+	}
- 
--err_dma_map:
--err_prep_key:
--	kfree(dma_mem);
-+	if (type != DPAA2_ETH_RX_DIST_FS)
-+		priv->rx_hash_fields = hash_fields;
-+
-+free_key:
-+	kfree(key_mem);
- 	return err;
- }
- 
-@@ -2080,6 +2983,7 @@ static int bind_dpni(struct dpaa2_eth_pr
- 	pools_params.num_dpbp = 1;
- 	pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id;
- 	pools_params.pools[0].backup_pool = 0;
-+	pools_params.pools[0].priority_mask = 0xff;
- 	pools_params.pools[0].buffer_size = DPAA2_ETH_RX_BUF_SIZE;
- 	err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
- 	if (err) {
-@@ -2087,17 +2991,36 @@ static int bind_dpni(struct dpaa2_eth_pr
- 		return err;
- 	}
- 
--	/* have the interface implicitly distribute traffic based on supported
--	 * header fields
-+	/* Verify classification options and disable hashing and/or
-+	 * flow steering support in case of invalid configuration values
- 	 */
--	err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_SUPPORTED);
--	if (err)
--		netdev_err(net_dev, "Failed to configure hashing\n");
-+	priv->dist_fields = default_dist_fields;
-+	priv->num_dist_fields = ARRAY_SIZE(default_dist_fields);
-+	check_cls_support(priv);
-+
-+	/* have the interface implicitly distribute traffic based on
-+	 * a static hash key. Also configure flow steering key, if supported.
-+	 * Errors here are not blocking, so just let the called function
-+	 * print its error message and move along.
-+	 */
-+	if (dpaa2_eth_has_legacy_dist(priv)) {
-+		dpaa2_eth_set_dist_key(priv, DPAA2_ETH_RX_DIST_LEGACY,
-+				       DPAA2_ETH_DIST_ALL);
-+	} else {
-+		dpaa2_eth_set_dist_key(priv, DPAA2_ETH_RX_DIST_HASH,
-+				       DPAA2_ETH_DIST_DEFAULT_HASH);
-+		dpaa2_eth_set_dist_key(priv, DPAA2_ETH_RX_DIST_FS,
-+				       DPAA2_ETH_DIST_ALL);
-+	}
- 
- 	/* Configure handling of error frames */
- 	err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
- 	err_cfg.set_frame_annotation = 1;
-+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
-+	err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
-+#else
- 	err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
-+#endif
- 	err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
- 				       &err_cfg);
- 	if (err) {
-@@ -2114,6 +3037,11 @@ static int bind_dpni(struct dpaa2_eth_pr
- 		case DPAA2_TX_CONF_FQ:
- 			err = setup_tx_flow(priv, &priv->fq[i]);
- 			break;
-+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
-+		case DPAA2_RX_ERR_FQ:
-+			err = setup_rx_err_flow(priv, &priv->fq[i]);
-+			break;
-+#endif
- 		default:
- 			dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
- 			return -EINVAL;
-@@ -2237,11 +3165,14 @@ static int netdev_init(struct net_device
- {
- 	struct device *dev = net_dev->dev.parent;
- 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	u32 options = priv->dpni_attrs.options;
-+	u64 supported = 0, not_supported = 0;
- 	u8 bcast_addr[ETH_ALEN];
- 	u8 num_queues;
- 	int err;
- 
- 	net_dev->netdev_ops = &dpaa2_eth_ops;
-+	net_dev->ethtool_ops = &dpaa2_ethtool_ops;
- 
- 	err = set_mac_addr(priv);
- 	if (err)
-@@ -2255,14 +3186,14 @@ static int netdev_init(struct net_device
- 		return err;
- 	}
- 
--	/* Reserve enough space to align buffer as per hardware requirement;
--	 * NOTE: priv->tx_data_offset MUST be initialized at this point.
--	 */
--	net_dev->needed_headroom = DPAA2_ETH_NEEDED_HEADROOM(priv);
--
--	/* Set MTU limits */
--	net_dev->min_mtu = 68;
-+	/* Set MTU upper limit; lower limit is default (68B) */
- 	net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
-+	err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
-+					(u16)DPAA2_ETH_MFL);
-+	if (err) {
-+		dev_err(dev, "dpni_set_max_frame_length() failed\n");
-+		return err;
-+	}
- 
- 	/* Set actual number of queues in the net device */
- 	num_queues = dpaa2_eth_queue_count(priv);
-@@ -2277,12 +3208,23 @@ static int netdev_init(struct net_device
- 		return err;
- 	}
- 
--	/* Our .ndo_init will be called herein */
--	err = register_netdev(net_dev);
--	if (err < 0) {
--		dev_err(dev, "register_netdev() failed\n");
--		return err;
--	}
-+	/* Capabilities listing */
-+	supported |= IFF_LIVE_ADDR_CHANGE;
-+
-+	if (options & DPNI_OPT_NO_MAC_FILTER)
-+		not_supported |= IFF_UNICAST_FLT;
-+	else
-+		supported |= IFF_UNICAST_FLT;
-+
-+	net_dev->priv_flags |= supported;
-+	net_dev->priv_flags &= ~not_supported;
-+
-+	/* Features */
-+	net_dev->features = NETIF_F_RXCSUM |
-+			    NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
-+			    NETIF_F_SG | NETIF_F_HIGHDMA |
-+			    NETIF_F_LLTX;
-+	net_dev->hw_features = net_dev->features;
- 
- 	return 0;
- }
-@@ -2303,14 +3245,9 @@ static int poll_link_state(void *arg)
- 	return 0;
- }
- 
--static irqreturn_t dpni_irq0_handler(int irq_num, void *arg)
--{
--	return IRQ_WAKE_THREAD;
--}
--
- static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
- {
--	u32 status = 0, clear = 0;
-+	u32 status = ~0;
- 	struct device *dev = (struct device *)arg;
- 	struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
- 	struct net_device *net_dev = dev_get_drvdata(dev);
-@@ -2320,18 +3257,12 @@ static irqreturn_t dpni_irq0_handler_thr
- 				  DPNI_IRQ_INDEX, &status);
- 	if (unlikely(err)) {
- 		netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
--		clear = 0xffffffff;
--		goto out;
-+		return IRQ_HANDLED;
- 	}
- 
--	if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
--		clear |= DPNI_IRQ_EVENT_LINK_CHANGED;
-+	if (status & DPNI_IRQ_EVENT_LINK_CHANGED)
- 		link_state_update(netdev_priv(net_dev));
--	}
- 
--out:
--	dpni_clear_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
--			      DPNI_IRQ_INDEX, clear);
- 	return IRQ_HANDLED;
- }
- 
-@@ -2348,8 +3279,7 @@ static int setup_irqs(struct fsl_mc_devi
- 
- 	irq = ls_dev->irqs[0];
- 	err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq,
--					dpni_irq0_handler,
--					dpni_irq0_handler_thread,
-+					NULL, dpni_irq0_handler_thread,
- 					IRQF_NO_SUSPEND | IRQF_ONESHOT,
- 					dev_name(&ls_dev->dev), &ls_dev->dev);
- 	if (err < 0) {
-@@ -2405,6 +3335,393 @@ static void del_ch_napi(struct dpaa2_eth
- 	}
- }
- 
-+/* SysFS support */
-+static ssize_t dpaa2_eth_show_tx_shaping(struct device *dev,
-+					 struct device_attribute *attr,
-+					 char *buf)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(to_net_dev(dev));
-+	/* No MC API for getting the shaping config. We're stateful. */
-+	struct dpni_tx_shaping_cfg *scfg = &priv->shaping_cfg;
-+
-+	return sprintf(buf, "%u %hu\n", scfg->rate_limit, scfg->max_burst_size);
-+}
-+
-+static ssize_t dpaa2_eth_write_tx_shaping(struct device *dev,
-+					  struct device_attribute *attr,
-+					  const char *buf,
-+					  size_t count)
-+{
-+	int err, items;
-+	struct dpaa2_eth_priv *priv = netdev_priv(to_net_dev(dev));
-+	struct dpni_tx_shaping_cfg scfg, ercfg = { 0 };
-+
-+	items = sscanf(buf, "%u %hu", &scfg.rate_limit, &scfg.max_burst_size);
-+	if (items != 2) {
-+		pr_err("Expected format: \"rate_limit(Mbps) max_burst_size(bytes)\"\n");
-+		return -EINVAL;
-+	}
-+	/* Size restriction as per MC API documentation */
-+	if (scfg.max_burst_size > DPAA2_ETH_MAX_BURST_SIZE) {
-+		pr_err("max_burst_size must be <= %d\n",
-+		       DPAA2_ETH_MAX_BURST_SIZE);
-+		return -EINVAL;
-+	}
-+
-+	err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, &scfg,
-+				  &ercfg, 0);
-+	if (err) {
-+		dev_err(dev, "dpni_set_tx_shaping() failed\n");
-+		return -EPERM;
-+	}
-+	/* If successful, save the current configuration for future inquiries */
-+	priv->shaping_cfg = scfg;
-+
-+	return count;
-+}
-+
-+static struct device_attribute dpaa2_eth_attrs[] = {
-+	__ATTR(tx_shaping,
-+	       0600,
-+	       dpaa2_eth_show_tx_shaping,
-+	       dpaa2_eth_write_tx_shaping),
-+};
-+
-+static void dpaa2_eth_sysfs_init(struct device *dev)
-+{
-+	int i, err;
-+
-+	for (i = 0; i < ARRAY_SIZE(dpaa2_eth_attrs); i++) {
-+		err = device_create_file(dev, &dpaa2_eth_attrs[i]);
-+		if (err) {
-+			dev_err(dev, "ERROR creating sysfs file\n");
-+			goto undo;
-+		}
-+	}
-+	return;
-+
-+undo:
-+	while (i > 0)
-+		device_remove_file(dev, &dpaa2_eth_attrs[--i]);
-+}
-+
-+static void dpaa2_eth_sysfs_remove(struct device *dev)
-+{
-+	int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(dpaa2_eth_attrs); i++)
-+		device_remove_file(dev, &dpaa2_eth_attrs[i]);
-+}
-+
-+#ifdef CONFIG_FSL_DPAA2_ETH_DCB
-+static int dpaa2_eth_dcbnl_ieee_getpfc(struct net_device *net_dev,
-+				       struct ieee_pfc *pfc)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct dpni_congestion_notification_cfg notification_cfg;
-+	struct dpni_link_state state;
-+	int err, i;
-+
-+	priv->pfc.pfc_cap = dpaa2_eth_tc_count(priv);
-+
-+	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
-+	if (err) {
-+		netdev_err(net_dev, "ERROR %d getting link state", err);
-+		return err;
-+	}
-+
-+	if (!(state.options & DPNI_LINK_OPT_PFC_PAUSE))
-+		return 0;
-+
-+	priv->pfc.pfc_en = 0;
-+	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
-+		err = dpni_get_congestion_notification(priv->mc_io, 0,
-+						       priv->mc_token,
-+						       DPNI_QUEUE_RX,
-+						       i, &notification_cfg);
-+		if (err) {
-+			netdev_err(net_dev, "Error %d getting congestion notif",
-+				   err);
-+			return err;
-+		}
-+
-+		if (notification_cfg.threshold_entry)
-+			priv->pfc.pfc_en |= 1 << i;
-+	}
-+
-+	memcpy(pfc, &priv->pfc, sizeof(priv->pfc));
-+
-+	return 0;
-+}
-+
-+/* Configure ingress classification based on VLAN PCP */
-+static int set_vlan_qos(struct dpaa2_eth_priv *priv)
-+{
-+	struct device *dev = priv->net_dev->dev.parent;
-+	struct dpkg_profile_cfg kg_cfg = {0};
-+	struct dpni_qos_tbl_cfg qos_cfg = {0};
-+	struct dpni_rule_cfg key_params;
-+	u8 *params_iova, *key, *mask = NULL;
-+	/* We only need the trailing 16 bits, without the TPID */
-+	u8 key_size = VLAN_HLEN / 2;
-+	int err = 0, i, j = 0;
-+
-+	if (priv->vlan_clsf_set)
-+		return 0;
-+
-+	params_iova = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
-+	if (!params_iova)
-+		return -ENOMEM;
-+
-+	kg_cfg.num_extracts = 1;
-+	kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_HDR;
-+	kg_cfg.extracts[0].extract.from_hdr.prot = NET_PROT_VLAN;
-+	kg_cfg.extracts[0].extract.from_hdr.type = DPKG_FULL_FIELD;
-+	kg_cfg.extracts[0].extract.from_hdr.field = NH_FLD_VLAN_TCI;
-+
-+	err = dpni_prepare_key_cfg(&kg_cfg, params_iova);
-+	if (err) {
-+		dev_err(dev, "dpkg_prepare_key_cfg failed: %d\n", err);
-+		goto out_free;
-+	}
-+
-+	/* Set QoS table */
-+	qos_cfg.default_tc = 0;
-+	qos_cfg.discard_on_miss = 0;
-+	qos_cfg.key_cfg_iova = dma_map_single(dev, params_iova,
-+					      DPAA2_CLASSIFIER_DMA_SIZE,
-+					      DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, qos_cfg.key_cfg_iova)) {
-+		dev_err(dev, "%s: DMA mapping failed\n", __func__);
-+		err = -ENOMEM;
-+		goto out_free;
-+	}
-+	err = dpni_set_qos_table(priv->mc_io, 0, priv->mc_token, &qos_cfg);
-+	dma_unmap_single(dev, qos_cfg.key_cfg_iova,
-+			 DPAA2_CLASSIFIER_DMA_SIZE, DMA_TO_DEVICE);
-+
-+	if (err) {
-+		dev_err(dev, "dpni_set_qos_table failed: %d\n", err);
-+		goto out_free;
-+	}
-+
-+	key_params.key_size = key_size;
-+
-+	if (dpaa2_eth_fs_mask_enabled(priv)) {
-+		mask = kzalloc(key_size, GFP_KERNEL);
-+		if (!mask)
-+			goto out_free;
-+
-+		*mask = cpu_to_be16(VLAN_PRIO_MASK);
-+
-+		key_params.mask_iova = dma_map_single(dev, mask, key_size,
-+						      DMA_TO_DEVICE);
-+		if (dma_mapping_error(dev, key_params.mask_iova)) {
-+			dev_err(dev, "DMA mapping failed %s\n", __func__);
-+			err = -ENOMEM;
-+			goto out_free_mask;
-+		}
-+	} else {
-+		key_params.mask_iova = 0;
-+	}
-+
-+	key = kzalloc(key_size, GFP_KERNEL);
-+	if (!key)
-+		goto out_cleanup_mask;
-+
-+	key_params.key_iova = dma_map_single(dev, key, key_size,
-+					     DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, key_params.key_iova)) {
-+		dev_err(dev, "%s: DMA mapping failed\n", __func__);
-+		err = -ENOMEM;
-+		goto out_free_key;
-+	}
-+
-+	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
-+		*key = cpu_to_be16(i << VLAN_PRIO_SHIFT);
-+
-+		dma_sync_single_for_device(dev, key_params.key_iova,
-+					   key_size, DMA_TO_DEVICE);
-+
-+		err = dpni_add_qos_entry(priv->mc_io, 0, priv->mc_token,
-+					 &key_params, i, j++);
-+		if (err) {
-+			dev_err(dev, "dpni_add_qos_entry failed: %d\n", err);
-+			goto out_remove;
-+		}
-+	}
-+
-+	priv->vlan_clsf_set = true;
-+	dev_dbg(dev, "Vlan PCP QoS classification set\n");
-+	goto out_cleanup;
-+
-+out_remove:
-+	for (j = 0; j < i; j++) {
-+		*key = cpu_to_be16(j << VLAN_PRIO_SHIFT);
-+
-+		dma_sync_single_for_device(dev, key_params.key_iova, key_size,
-+					   DMA_TO_DEVICE);
-+
-+		err = dpni_remove_qos_entry(priv->mc_io, 0, priv->mc_token,
-+					    &key_params);
-+		if (err)
-+			dev_err(dev, "dpni_remove_qos_entry failed: %d\n", err);
-+	}
-+
-+out_cleanup:
-+	dma_unmap_single(dev, key_params.key_iova, key_size, DMA_TO_DEVICE);
-+out_free_key:
-+	kfree(key);
-+out_cleanup_mask:
-+	if (key_params.mask_iova)
-+		dma_unmap_single(dev, key_params.mask_iova, key_size,
-+				 DMA_TO_DEVICE);
-+out_free_mask:
-+	kfree(mask);
-+out_free:
-+	kfree(params_iova);
-+	return err;
-+}
-+
-+static int dpaa2_eth_dcbnl_ieee_setpfc(struct net_device *net_dev,
-+				       struct ieee_pfc *pfc)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct dpni_congestion_notification_cfg notification_cfg = {0};
-+	struct dpni_link_state state = {0};
-+	struct dpni_link_cfg cfg = {0};
-+	struct ieee_pfc old_pfc;
-+	int err = 0, i;
-+
-+	if (dpaa2_eth_tc_count(priv) == 1) {
-+		netdev_dbg(net_dev, "DPNI has 1 TC, PFC configuration N/A\n");
-+		return 0;
-+	}
-+
-+	/* Zero out pfc_enabled prios greater than tc_count */
-+	pfc->pfc_en &= (1 << dpaa2_eth_tc_count(priv)) - 1;
-+
-+	if (priv->pfc.pfc_en == pfc->pfc_en)
-+		/* Same enabled mask, nothing to be done */
-+		return 0;
-+
-+	err = set_vlan_qos(priv);
-+	if (err)
-+		return err;
-+
-+	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
-+	if (err) {
-+		netdev_err(net_dev, "ERROR %d getting link state", err);
-+		return err;
-+	}
-+
-+	cfg.rate = state.rate;
-+	cfg.options = state.options;
-+	if (pfc->pfc_en)
-+		cfg.options |= DPNI_LINK_OPT_PFC_PAUSE;
-+	else
-+		cfg.options &= ~DPNI_LINK_OPT_PFC_PAUSE;
-+
-+	err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &cfg);
-+	if (err) {
-+		netdev_err(net_dev, "ERROR %d setting link cfg", err);
-+		return err;
-+	}
-+
-+	memcpy(&old_pfc, &priv->pfc, sizeof(priv->pfc));
-+	memcpy(&priv->pfc, pfc, sizeof(priv->pfc));
-+
-+	err = set_rx_taildrop(priv);
-+	if (err)
-+		goto out_restore_config;
-+
-+	/* configure congestion notifications */
-+	notification_cfg.notification_mode = DPNI_CONG_OPT_FLOW_CONTROL;
-+	notification_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
-+	notification_cfg.message_iova = 0ULL;
-+	notification_cfg.message_ctx = 0ULL;
-+
-+	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
-+		if (dpaa2_eth_is_pfc_enabled(priv, i)) {
-+			notification_cfg.threshold_entry = NAPI_POLL_WEIGHT;
-+			notification_cfg.threshold_exit = NAPI_POLL_WEIGHT / 2;
-+		} else {
-+			notification_cfg.threshold_entry = 0;
-+			notification_cfg.threshold_exit = 0;
-+		}
-+
-+		err = dpni_set_congestion_notification(priv->mc_io, 0,
-+						       priv->mc_token,
-+						       DPNI_QUEUE_RX,
-+						       i, &notification_cfg);
-+		if (err) {
-+			netdev_err(net_dev, "Error %d setting congestion notif",
-+				   err);
-+			goto out_restore_config;
-+		}
-+
-+		netdev_dbg(net_dev, "%s congestion notifications for tc %d\n",
-+			   (notification_cfg.threshold_entry ?
-+			    "Enabled" : "Disabled"), i);
-+	}
-+
-+	return 0;
-+
-+out_restore_config:
-+	memcpy(&priv->pfc, &old_pfc, sizeof(priv->pfc));
-+	return err;
-+}
-+
-+static u8 dpaa2_eth_dcbnl_getdcbx(struct net_device *net_dev)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+
-+	return priv->dcbx_mode;
-+}
-+
-+static u8 dpaa2_eth_dcbnl_setdcbx(struct net_device *net_dev, u8 mode)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+
-+	priv->dcbx_mode = mode;
-+	return 0;
-+}
-+
-+static u8 dpaa2_eth_dcbnl_getcap(struct net_device *net_dev, int capid, u8 *cap)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+
-+	switch (capid) {
-+	case DCB_CAP_ATTR_PFC:
-+		*cap = true;
-+		break;
-+	case DCB_CAP_ATTR_PFC_TCS:
-+		/* bitmap where each bit represents a number of traffic
-+		 * classes the device can be configured to use for Priority
-+		 * Flow Control
-+		 */
-+		*cap = 1 << (dpaa2_eth_tc_count(priv) - 1);
-+		break;
-+	case DCB_CAP_ATTR_DCBX:
-+		*cap = priv->dcbx_mode;
-+		break;
-+	default:
-+		*cap = false;
-+		break;
-+	}
-+
-+	return 0;
-+}
-+
-+const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops = {
-+	.ieee_getpfc	= dpaa2_eth_dcbnl_ieee_getpfc,
-+	.ieee_setpfc	= dpaa2_eth_dcbnl_ieee_setpfc,
-+	.getdcbx	= dpaa2_eth_dcbnl_getdcbx,
-+	.setdcbx	= dpaa2_eth_dcbnl_setdcbx,
-+	.getcap		= dpaa2_eth_dcbnl_getcap,
-+};
-+#endif
-+
- static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
- {
- 	struct device *dev;
-@@ -2415,7 +3732,7 @@ static int dpaa2_eth_probe(struct fsl_mc
- 	dev = &dpni_dev->dev;
- 
- 	/* Net device */
--	net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_TX_QUEUES);
-+	net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_NETDEV_QUEUES);
- 	if (!net_dev) {
- 		dev_err(dev, "alloc_etherdev_mq() failed\n");
- 		return -ENOMEM;
-@@ -2433,7 +3750,10 @@ static int dpaa2_eth_probe(struct fsl_mc
- 	err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
- 				     &priv->mc_io);
- 	if (err) {
--		dev_err(dev, "MC portal allocation failed\n");
-+		if (err == -ENXIO)
-+			err = -EPROBE_DEFER;
-+		else
-+			dev_err(dev, "MC portal allocation failed\n");
- 		goto err_portal_alloc;
- 	}
- 
-@@ -2456,9 +3776,6 @@ static int dpaa2_eth_probe(struct fsl_mc
- 	if (err)
- 		goto err_bind;
- 
--	/* Add a NAPI context for each channel */
--	add_ch_napi(priv);
--
- 	/* Percpu statistics */
- 	priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
- 	if (!priv->percpu_stats) {
-@@ -2491,7 +3808,14 @@ static int dpaa2_eth_probe(struct fsl_mc
- 	if (err)
- 		goto err_alloc_rings;
- 
--	net_dev->ethtool_ops = &dpaa2_ethtool_ops;
-+#ifdef CONFIG_FSL_DPAA2_ETH_DCB
-+	net_dev->dcbnl_ops = &dpaa2_eth_dcbnl_ops;
-+	priv->dcbx_mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
-+#endif
-+
-+	/* Add a NAPI context for each channel */
-+	add_ch_napi(priv);
-+	enable_ch_napi(priv);
- 
- 	err = setup_irqs(dpni_dev);
- 	if (err) {
-@@ -2499,25 +3823,41 @@ static int dpaa2_eth_probe(struct fsl_mc
- 		priv->poll_thread = kthread_run(poll_link_state, priv,
- 						"%s_poll_link", net_dev->name);
- 		if (IS_ERR(priv->poll_thread)) {
--			netdev_err(net_dev, "Error starting polling thread\n");
-+			dev_err(dev, "Error starting polling thread\n");
- 			goto err_poll_thread;
- 		}
- 		priv->do_link_poll = true;
- 	}
- 
-+	err = register_netdev(net_dev);
-+	if (err < 0) {
-+		dev_err(dev, "register_netdev() failed\n");
-+		goto err_netdev_reg;
-+	}
-+
-+	dpaa2_eth_sysfs_init(&net_dev->dev);
-+#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS
-+	dpaa2_dbg_add(priv);
-+#endif
-+
- 	dev_info(dev, "Probed interface %s\n", net_dev->name);
- 	return 0;
- 
-+err_netdev_reg:
-+	if (priv->do_link_poll)
-+		kthread_stop(priv->poll_thread);
-+	else
-+		fsl_mc_free_irqs(dpni_dev);
- err_poll_thread:
- 	free_rings(priv);
- err_alloc_rings:
- err_csum:
--	unregister_netdev(net_dev);
- err_netdev_init:
- 	free_percpu(priv->percpu_extras);
- err_alloc_percpu_extras:
- 	free_percpu(priv->percpu_stats);
- err_alloc_percpu_stats:
-+	disable_ch_napi(priv);
- 	del_ch_napi(priv);
- err_bind:
- 	free_dpbp(priv);
-@@ -2544,8 +3884,15 @@ static int dpaa2_eth_remove(struct fsl_m
- 	net_dev = dev_get_drvdata(dev);
- 	priv = netdev_priv(net_dev);
- 
-+#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS
-+	dpaa2_dbg_remove(priv);
-+#endif
-+	dpaa2_eth_sysfs_remove(&net_dev->dev);
-+
- 	unregister_netdev(net_dev);
--	dev_info(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
-+
-+	disable_ch_napi(priv);
-+	del_ch_napi(priv);
- 
- 	if (priv->do_link_poll)
- 		kthread_stop(priv->poll_thread);
-@@ -2555,8 +3902,6 @@ static int dpaa2_eth_remove(struct fsl_m
- 	free_rings(priv);
- 	free_percpu(priv->percpu_stats);
- 	free_percpu(priv->percpu_extras);
--
--	del_ch_napi(priv);
- 	free_dpbp(priv);
- 	free_dpio(priv);
- 	free_dpni(priv);
-@@ -2566,6 +3911,8 @@ static int dpaa2_eth_remove(struct fsl_m
- 	dev_set_drvdata(dev, NULL);
- 	free_netdev(net_dev);
- 
-+	dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
-+
- 	return 0;
- }
- 
-@@ -2588,4 +3935,34 @@ static struct fsl_mc_driver dpaa2_eth_dr
- 	.match_id_table = dpaa2_eth_match_id_table
- };
- 
--module_fsl_mc_driver(dpaa2_eth_driver);
-+static int __init dpaa2_eth_driver_init(void)
-+{
-+	int err;
-+
-+	dpaa2_eth_dbg_init();
-+	err = fsl_mc_driver_register(&dpaa2_eth_driver);
-+	if (err)
-+		goto out_debugfs_err;
-+
-+	err = dpaa2_ceetm_register();
-+	if (err)
-+		goto out_ceetm_err;
-+
-+	return 0;
-+
-+out_ceetm_err:
-+	fsl_mc_driver_unregister(&dpaa2_eth_driver);
-+out_debugfs_err:
-+	dpaa2_eth_dbg_exit();
-+	return err;
-+}
-+
-+static void __exit dpaa2_eth_driver_exit(void)
-+{
-+	dpaa2_ceetm_unregister();
-+	fsl_mc_driver_unregister(&dpaa2_eth_driver);
-+	dpaa2_eth_dbg_exit();
-+}
-+
-+module_init(dpaa2_eth_driver_init);
-+module_exit(dpaa2_eth_driver_exit);
---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
-@@ -33,6 +33,7 @@
- #ifndef __DPAA2_ETH_H
- #define __DPAA2_ETH_H
- 
-+#include <linux/dcbnl.h>
- #include <linux/netdevice.h>
- #include <linux/if_vlan.h>
- 
-@@ -44,9 +45,17 @@
- #include "dpni-cmd.h"
- 
- #include "dpaa2-eth-trace.h"
-+#include "dpaa2-eth-debugfs.h"
-+
-+#define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
- 
- #define DPAA2_ETH_STORE_SIZE		16
- 
-+/* We set a max threshold for how many Tx confirmations we should process
-+ * on a NAPI poll call, they take less processing time.
-+ */
-+#define TX_CONF_PER_NAPI_POLL		256
-+
- /* Maximum number of scatter-gather entries in an ingress frame,
-  * considering the maximum receive frame size is 64K
-  */
-@@ -60,6 +69,14 @@
- /* Convert L3 MTU to L2 MFL */
- #define DPAA2_ETH_L2_MAX_FRM(mtu)	((mtu) + VLAN_ETH_HLEN)
- 
-+/* Maximum burst size value for Tx shaping */
-+#define DPAA2_ETH_MAX_BURST_SIZE	0xF7FF
-+
-+/* Maximum number of buffers that can be acquired/released through a single
-+ * QBMan command
-+ */
-+#define DPAA2_ETH_BUFS_PER_CMD		7
-+
- /* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo
-  * frames in the Rx queues (length of the current frame is not
-  * taken into account when making the taildrop decision)
-@@ -72,31 +89,32 @@
-  * to accommodate the buffer refill delay.
-  */
- #define DPAA2_ETH_MAX_FRAMES_PER_QUEUE	(DPAA2_ETH_TAILDROP_THRESH / 64)
--#define DPAA2_ETH_NUM_BUFS		(DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
--#define DPAA2_ETH_REFILL_THRESH		DPAA2_ETH_MAX_FRAMES_PER_QUEUE
-+#define DPAA2_ETH_NUM_BUFS_PER_CH	(DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
-+#define DPAA2_ETH_REFILL_THRESH(priv)	\
-+	((priv)->max_bufs_per_ch - DPAA2_ETH_BUFS_PER_CMD)
- 
--/* Maximum number of buffers that can be acquired/released through a single
-- * QBMan command
-- */
--#define DPAA2_ETH_BUFS_PER_CMD		7
-+/* Global buffer quota in case flow control is enabled */
-+#define DPAA2_ETH_NUM_BUFS_FC		256
-+
-+/* Hardware requires alignment for ingress/egress buffer addresses */
-+#define DPAA2_ETH_TX_BUF_ALIGN		64
- 
--/* Hardware requires alignment for ingress/egress buffer addresses
-- * and ingress buffer lengths.
-+/* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
-+ * to 256B. For newer revisions, the requirement is only for 64B alignment
-  */
-+#define DPAA2_ETH_RX_BUF_ALIGN_REV1	256
-+#define DPAA2_ETH_RX_BUF_ALIGN		64
-+
- #define DPAA2_ETH_RX_BUF_SIZE		2048
--#define DPAA2_ETH_TX_BUF_ALIGN		64
--#define DPAA2_ETH_RX_BUF_ALIGN		256
--#define DPAA2_ETH_NEEDED_HEADROOM(p_priv) \
--	((p_priv)->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN)
--
--/* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but we need to allocate ingress
-- * buffers large enough to allow building an skb around them and also account
-- * for alignment restrictions
-- */
--#define DPAA2_ETH_BUF_RAW_SIZE \
--	(DPAA2_ETH_RX_BUF_SIZE + \
--	SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + \
--	DPAA2_ETH_RX_BUF_ALIGN)
-+#define DPAA2_ETH_SKB_SIZE \
-+	(DPAA2_ETH_RX_BUF_SIZE + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
-+
-+/* PTP nominal frequency 1GHz */
-+#define DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS 1
-+
-+/* Hardware annotation area in RX/TX buffers */
-+#define DPAA2_ETH_RX_HWA_SIZE		64
-+#define DPAA2_ETH_TX_HWA_SIZE		128
- 
- /* We are accommodating a skb backpointer and some S/G info
-  * in the frame's software annotation. The hardware
-@@ -104,12 +122,32 @@
-  */
- #define DPAA2_ETH_SWA_SIZE		64
- 
-+/* We store different information in the software annotation area of a Tx frame
-+ * based on what type of frame it is
-+ */
-+enum dpaa2_eth_swa_type {
-+	DPAA2_ETH_SWA_SINGLE,
-+	DPAA2_ETH_SWA_SG,
-+	DPAA2_ETH_SWA_XDP,
-+};
-+
- /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
- struct dpaa2_eth_swa {
--	struct sk_buff *skb;
--	struct scatterlist *scl;
--	int num_sg;
--	int num_dma_bufs;
-+	enum dpaa2_eth_swa_type type;
-+	union {
-+		struct {
-+			struct sk_buff *skb;
-+		} single;
-+		struct {
-+			struct sk_buff *skb;
-+			struct scatterlist *scl;
-+			int num_sg;
-+			int sgt_size;
-+		} sg;
-+		struct {
-+			int dma_size;
-+		} xdp;
-+	};
- };
- 
- /* Annotation valid bits in FD FRC */
-@@ -120,23 +158,14 @@ struct dpaa2_eth_swa {
- #define DPAA2_FD_FRC_FASWOV		0x0800
- #define DPAA2_FD_FRC_FAICFDV		0x0400
- 
--/* Error bits in FD CTRL */
--#define DPAA2_FD_CTRL_UFD		0x00000004
--#define DPAA2_FD_CTRL_SBE		0x00000008
--#define DPAA2_FD_CTRL_FSE		0x00000020
--#define DPAA2_FD_CTRL_FAERR		0x00000040
--
--#define DPAA2_FD_RX_ERR_MASK		(DPAA2_FD_CTRL_SBE	| \
--					 DPAA2_FD_CTRL_FAERR)
--#define DPAA2_FD_TX_ERR_MASK		(DPAA2_FD_CTRL_UFD	| \
--					 DPAA2_FD_CTRL_SBE	| \
--					 DPAA2_FD_CTRL_FSE	| \
--					 DPAA2_FD_CTRL_FAERR)
-+#define DPAA2_FD_RX_ERR_MASK		(FD_CTRL_SBE | FD_CTRL_FAERR)
-+#define DPAA2_FD_TX_ERR_MASK		(FD_CTRL_UFD	| \
-+					 FD_CTRL_SBE	| \
-+					 FD_CTRL_FSE	| \
-+					 FD_CTRL_FAERR)
- 
- /* Annotation bits in FD CTRL */
- #define DPAA2_FD_CTRL_ASAL		0x00020000	/* ASAL = 128 */
--#define DPAA2_FD_CTRL_PTA		0x00800000
--#define DPAA2_FD_CTRL_PTV1		0x00400000
- 
- /* Frame annotation status */
- struct dpaa2_fas {
-@@ -144,7 +173,7 @@ struct dpaa2_fas {
- 	u8 ppid;
- 	__le16 ifpid;
- 	__le32 status;
--} __packed;
-+};
- 
- /* Frame annotation status word is located in the first 8 bytes
-  * of the buffer's hardware annoatation area
-@@ -152,11 +181,45 @@ struct dpaa2_fas {
- #define DPAA2_FAS_OFFSET		0
- #define DPAA2_FAS_SIZE			(sizeof(struct dpaa2_fas))
- 
-+/* Timestamp is located in the next 8 bytes of the buffer's
-+ * hardware annotation area
-+ */
-+#define DPAA2_TS_OFFSET			0x8
-+
-+/* Frame annotation egress action descriptor */
-+#define DPAA2_FAEAD_OFFSET		0x58
-+
-+struct dpaa2_faead {
-+	__le32 conf_fqid;
-+	__le32 ctrl;
-+};
-+
-+#define DPAA2_FAEAD_A2V			0x20000000
-+#define DPAA2_FAEAD_A4V			0x08000000
-+#define DPAA2_FAEAD_UPDV		0x00001000
-+#define DPAA2_FAEAD_EBDDV		0x00002000
-+#define DPAA2_FAEAD_UPD			0x00000010
-+
- /* Accessors for the hardware annotation fields that we use */
--#define dpaa2_get_hwa(buf_addr) \
--	((void *)(buf_addr) + DPAA2_ETH_SWA_SIZE)
--#define dpaa2_get_fas(buf_addr) \
--	(struct dpaa2_fas *)(dpaa2_get_hwa(buf_addr) + DPAA2_FAS_OFFSET)
-+static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
-+{
-+	return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
-+}
-+
-+static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
-+{
-+	return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
-+}
-+
-+static inline u64 *dpaa2_get_ts(void *buf_addr, bool swa)
-+{
-+	return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
-+}
-+
-+static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
-+{
-+	return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
-+}
- 
- /* Error and status bits in the frame annotation status word */
- /* Debug frame, otherwise supposed to be discarded */
-@@ -203,11 +266,6 @@ struct dpaa2_fas {
- 					 DPAA2_FAS_BLE		| \
- 					 DPAA2_FAS_L3CE		| \
- 					 DPAA2_FAS_L4CE)
--/* Tx errors */
--#define DPAA2_FAS_TX_ERR_MASK		(DPAA2_FAS_KSE		| \
--					 DPAA2_FAS_EOFHE	| \
--					 DPAA2_FAS_MNLE		| \
--					 DPAA2_FAS_TIDE)
- 
- /* Time in milliseconds between link state updates */
- #define DPAA2_ETH_LINK_STATE_REFRESH	1000
-@@ -218,6 +276,14 @@ struct dpaa2_fas {
-  */
- #define DPAA2_ETH_ENQUEUE_RETRIES	10
- 
-+/* Tx congestion entry & exit thresholds, in number of bytes.
-+ * We allow a maximum of 512KB worth of frames pending processing on the Tx
-+ * queues of an interface
-+ */
-+#define DPAA2_ETH_TX_CONG_ENTRY_THRESH  (512 * 1024)
-+#define DPAA2_ETH_TX_CONG_EXIT_THRESH	\
-+	(DPAA2_ETH_TX_CONG_ENTRY_THRESH * 9 / 10)
-+
- /* Driver statistics, other than those in struct rtnl_link_stats64.
-  * These are usually collected per-CPU and aggregated by ethtool.
-  */
-@@ -226,6 +292,7 @@ struct dpaa2_eth_drv_stats {
- 	__u64	tx_conf_bytes;
- 	__u64	tx_sg_frames;
- 	__u64	tx_sg_bytes;
-+	__u64	tx_reallocs;
- 	__u64	rx_sg_frames;
- 	__u64	rx_sg_bytes;
- 	/* Enqueues retried due to portal busy */
-@@ -236,6 +303,8 @@ struct dpaa2_eth_drv_stats {
- struct dpaa2_eth_fq_stats {
- 	/* Number of frames received on this queue */
- 	__u64 frames;
-+	/* Number of times this queue entered congestion */
-+	__u64 congestion_entry;
- };
- 
- /* Per-channel statistics */
-@@ -250,17 +319,23 @@ struct dpaa2_eth_ch_stats {
- 	__u64 pull_err;
- };
- 
-+#define DPAA2_ETH_MAX_TCS		8
-+
- /* Maximum number of queues associated with a DPNI */
--#define DPAA2_ETH_MAX_RX_QUEUES		16
--#define DPAA2_ETH_MAX_TX_QUEUES		NR_CPUS
-+#define DPAA2_ETH_MAX_RX_QUEUES		(DPNI_MAX_DIST_SIZE * DPAA2_ETH_MAX_TCS)
-+#define DPAA2_ETH_MAX_TX_QUEUES		DPNI_MAX_SENDERS
-+#define DPAA2_ETH_MAX_RX_ERR_QUEUES	1
- #define DPAA2_ETH_MAX_QUEUES		(DPAA2_ETH_MAX_RX_QUEUES + \
--					DPAA2_ETH_MAX_TX_QUEUES)
-+					DPAA2_ETH_MAX_TX_QUEUES + \
-+					DPAA2_ETH_MAX_RX_ERR_QUEUES)
-+#define DPAA2_ETH_MAX_NETDEV_QUEUES	(DPNI_MAX_DIST_SIZE * DPAA2_ETH_MAX_TCS)
- 
--#define DPAA2_ETH_MAX_DPCONS		NR_CPUS
-+#define DPAA2_ETH_MAX_DPCONS		16
- 
- enum dpaa2_eth_fq_type {
- 	DPAA2_RX_FQ = 0,
- 	DPAA2_TX_CONF_FQ,
-+	DPAA2_RX_ERR_FQ
- };
- 
- struct dpaa2_eth_priv;
-@@ -269,6 +344,7 @@ struct dpaa2_eth_fq {
- 	u32 fqid;
- 	u32 tx_qdbin;
- 	u16 flowid;
-+	u8 tc;
- 	int target_cpu;
- 	struct dpaa2_eth_channel *channel;
- 	enum dpaa2_eth_fq_type type;
-@@ -276,7 +352,8 @@ struct dpaa2_eth_fq {
- 	void (*consume)(struct dpaa2_eth_priv *,
- 			struct dpaa2_eth_channel *,
- 			const struct dpaa2_fd *,
--			struct napi_struct *);
-+			struct napi_struct *,
-+			u16 queue_id);
- 	struct dpaa2_eth_fq_stats stats;
- };
- 
-@@ -285,24 +362,53 @@ struct dpaa2_eth_channel {
- 	struct fsl_mc_device *dpcon;
- 	int dpcon_id;
- 	int ch_id;
--	int dpio_id;
- 	struct napi_struct napi;
-+	struct dpaa2_io *dpio;
- 	struct dpaa2_io_store *store;
- 	struct dpaa2_eth_priv *priv;
- 	int buf_count;
- 	struct dpaa2_eth_ch_stats stats;
-+	struct bpf_prog *xdp_prog;
-+	u64 rel_buf_array[DPAA2_ETH_BUFS_PER_CMD];
-+	u8 rel_buf_cnt;
-+	bool flush;
-+};
-+
-+struct dpaa2_eth_cls_rule {
-+	struct ethtool_rx_flow_spec fs;
-+	bool in_use;
- };
- 
--struct dpaa2_eth_hash_fields {
-+struct dpaa2_eth_dist_fields {
- 	u64 rxnfc_field;
- 	enum net_prot cls_prot;
- 	int cls_field;
-+	int offset;
- 	int size;
-+	u32 id;
- };
- 
- /* Driver private data */
- struct dpaa2_eth_priv {
- 	struct net_device *net_dev;
-+	/* Standard statistics */
-+	struct rtnl_link_stats64 __percpu *percpu_stats;
-+	/* Extra stats, in addition to the ones known by the kernel */
-+	struct dpaa2_eth_drv_stats __percpu *percpu_extras;
-+	bool ts_tx_en; /* Tx timestamping enabled */
-+	bool ts_rx_en; /* Rx timestamping enabled */
-+	u16 tx_data_offset;
-+	u16 bpid;
-+	u16 tx_qdid;
-+	u16 rx_buf_align;
-+	struct iommu_domain *iommu_domain;
-+	int max_bufs_per_ch;
-+	int refill_thresh;
-+	bool has_xdp_prog;
-+
-+	void *cscn_mem;	/* Tx congestion notifications are written here */
-+	void *cscn_unaligned;
-+	dma_addr_t cscn_dma;
- 
- 	u8 num_fqs;
- 	struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
-@@ -311,51 +417,193 @@ struct dpaa2_eth_priv {
- 	struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
- 
- 	struct dpni_attr dpni_attrs;
--	u16 tx_data_offset;
--
-+	u16 dpni_ver_major;
-+	u16 dpni_ver_minor;
- 	struct fsl_mc_device *dpbp_dev;
--	u16 bpid;
--	struct iommu_domain *iommu_domain;
- 
--	u16 tx_qdid;
- 	struct fsl_mc_io *mc_io;
- 	/* Cores which have an affine DPIO/DPCON.
- 	 * This is the cpu set on which Rx and Tx conf frames are processed
- 	 */
- 	struct cpumask dpio_cpumask;
- 
--	/* Standard statistics */
--	struct rtnl_link_stats64 __percpu *percpu_stats;
--	/* Extra stats, in addition to the ones known by the kernel */
--	struct dpaa2_eth_drv_stats __percpu *percpu_extras;
--
- 	u16 mc_token;
- 
- 	struct dpni_link_state link_state;
- 	bool do_link_poll;
- 	struct task_struct *poll_thread;
- 
-+	/* Rx distribution (hash and flow steering) header fields
-+	 * supported by the driver
-+	 */
-+	struct dpaa2_eth_dist_fields *dist_fields;
-+	u8 num_dist_fields;
- 	/* enabled ethtool hashing bits */
- 	u64 rx_hash_fields;
-+#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS
-+	struct dpaa2_debugfs dbg;
-+#endif
-+	/* array of classification rules */
-+	struct dpaa2_eth_cls_rule *cls_rule;
-+	struct dpni_tx_shaping_cfg shaping_cfg;
-+
-+	u8 dcbx_mode;
-+	struct ieee_pfc pfc;
-+	bool vlan_clsf_set;
-+	bool tx_pause_frames;
-+
-+	bool ceetm_en;
-+};
-+
-+enum dpaa2_eth_rx_dist {
-+	DPAA2_ETH_RX_DIST_HASH,
-+	DPAA2_ETH_RX_DIST_FS,
-+	DPAA2_ETH_RX_DIST_LEGACY
- };
- 
--/* default Rx hash options, set during probing */
--#define DPAA2_RXH_SUPPORTED	(RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
--				| RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
--				| RXH_L4_B_2_3)
-+/* Supported Rx distribution field ids */
-+#define DPAA2_ETH_DIST_ETHSRC		BIT(0)
-+#define DPAA2_ETH_DIST_ETHDST		BIT(1)
-+#define DPAA2_ETH_DIST_ETHTYPE		BIT(2)
-+#define DPAA2_ETH_DIST_VLAN		BIT(3)
-+#define DPAA2_ETH_DIST_IPSRC		BIT(4)
-+#define DPAA2_ETH_DIST_IPDST		BIT(5)
-+#define DPAA2_ETH_DIST_IPPROTO		BIT(6)
-+#define DPAA2_ETH_DIST_L4SRC		BIT(7)
-+#define DPAA2_ETH_DIST_L4DST		BIT(8)
-+#define DPAA2_ETH_DIST_ALL		(~0U)
-+
-+/* Default Rx hash key */
-+#define DPAA2_ETH_DIST_DEFAULT_HASH \
-+	(DPAA2_ETH_DIST_IPPROTO | \
-+	 DPAA2_ETH_DIST_IPSRC | DPAA2_ETH_DIST_IPDST | \
-+	 DPAA2_ETH_DIST_L4SRC | DPAA2_ETH_DIST_L4DST)
- 
- #define dpaa2_eth_hash_enabled(priv)	\
- 	((priv)->dpni_attrs.num_queues > 1)
- 
-+#define dpaa2_eth_fs_enabled(priv)	\
-+	(!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
-+
-+#define dpaa2_eth_fs_mask_enabled(priv)	\
-+	((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
-+
-+#define dpaa2_eth_fs_count(priv)	\
-+	((priv)->dpni_attrs.fs_entries)
-+
- /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
- #define DPAA2_CLASSIFIER_DMA_SIZE 256
- 
- extern const struct ethtool_ops dpaa2_ethtool_ops;
- extern const char dpaa2_eth_drv_version[];
- 
--static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv)
-+static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
-+					 u16 ver_major, u16 ver_minor)
-+{
-+	if (priv->dpni_ver_major == ver_major)
-+		return priv->dpni_ver_minor - ver_minor;
-+	return priv->dpni_ver_major - ver_major;
-+}
-+
-+#define DPNI_DIST_KEY_VER_MAJOR			7
-+#define DPNI_DIST_KEY_VER_MINOR			5
-+
-+static inline bool dpaa2_eth_has_legacy_dist(struct dpaa2_eth_priv *priv)
-+{
-+	return (dpaa2_eth_cmp_dpni_ver(priv, DPNI_DIST_KEY_VER_MAJOR,
-+				       DPNI_DIST_KEY_VER_MINOR) < 0);
-+}
-+
-+/* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but the skb built around
-+ * the buffer also needs space for its shared info struct, and we need
-+ * to allocate enough to accommodate hardware alignment restrictions
-+ */
-+static inline unsigned int dpaa2_eth_buf_raw_size(struct dpaa2_eth_priv *priv)
-+{
-+	return DPAA2_ETH_SKB_SIZE + priv->rx_buf_align;
-+}
-+
-+/* Total headroom needed by the hardware in Tx frame buffers */
-+static inline unsigned int
-+dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, struct sk_buff *skb)
-+{
-+	unsigned int headroom = DPAA2_ETH_SWA_SIZE;
-+
-+	/* If we don't have an skb (e.g. XDP buffer), we only need space for
-+	 * the software annotation area
-+	 */
-+	if (!skb)
-+		return headroom;
-+
-+	/* For non-linear skbs we have no headroom requirement, as we build a
-+	 * SG frame with a newly allocated SGT buffer
-+	 */
-+	if (skb_is_nonlinear(skb))
-+		return 0;
-+
-+	/* If we have Tx timestamping, need 128B hardware annotation */
-+	if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
-+		headroom += DPAA2_ETH_TX_HWA_SIZE;
-+
-+	return headroom;
-+}
-+
-+/* Extra headroom space requested to hardware, in order to make sure there's
-+ * no realloc'ing in forwarding scenarios. We need to reserve enough space
-+ * such that we can accommodate the maximum required Tx offset and alignment
-+ * in the ingress frame buffer
-+ */
-+static inline unsigned int dpaa2_eth_rx_headroom(struct dpaa2_eth_priv *priv)
-+{
-+	return priv->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN -
-+	       DPAA2_ETH_RX_HWA_SIZE;
-+}
-+
-+static inline int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv)
- {
- 	return priv->dpni_attrs.num_queues;
- }
- 
-+static inline int dpaa2_eth_tc_count(struct dpaa2_eth_priv *priv)
-+{
-+	return priv->dpni_attrs.num_tcs;
-+}
-+
-+static inline bool dpaa2_eth_is_pfc_enabled(struct dpaa2_eth_priv *priv,
-+					    int traffic_class)
-+{
-+	return priv->pfc.pfc_en & (1 << traffic_class);
-+}
-+
-+enum dpaa2_eth_td_cfg {
-+	DPAA2_ETH_TD_NONE,
-+	DPAA2_ETH_TD_QUEUE,
-+	DPAA2_ETH_TD_GROUP
-+};
-+
-+static inline enum dpaa2_eth_td_cfg
-+dpaa2_eth_get_td_type(struct dpaa2_eth_priv *priv)
-+{
-+	bool pfc_enabled = !!(priv->pfc.pfc_en);
-+
-+	if (pfc_enabled)
-+		return DPAA2_ETH_TD_GROUP;
-+	else if (priv->tx_pause_frames)
-+		return DPAA2_ETH_TD_NONE;
-+	else
-+		return DPAA2_ETH_TD_QUEUE;
-+}
-+
-+static inline int dpaa2_eth_ch_count(struct dpaa2_eth_priv *priv)
-+{
-+	return 1;
-+}
-+
-+void check_cls_support(struct dpaa2_eth_priv *priv);
-+
-+int set_rx_taildrop(struct dpaa2_eth_priv *priv);
-+
-+int dpaa2_eth_set_dist_key(struct dpaa2_eth_priv *priv,
-+			   enum dpaa2_eth_rx_dist type, u32 key_fields);
-+
- #endif	/* __DPAA2_H */
---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c
-@@ -1,5 +1,5 @@
- /* Copyright 2014-2016 Freescale Semiconductor Inc.
-- * Copyright 2016 NXP
-+ * Copyright 2016-2017 NXP
-  *
-  * Redistribution and use in source and binary forms, with or without
-  * modification, are permitted provided that the following conditions are met:
-@@ -62,6 +62,7 @@ static char dpaa2_ethtool_extras[][ETH_G
- 	"[drv] tx conf bytes",
- 	"[drv] tx sg frames",
- 	"[drv] tx sg bytes",
-+	"[drv] tx realloc frames",
- 	"[drv] rx sg frames",
- 	"[drv] rx sg bytes",
- 	"[drv] enqueue portal busy",
-@@ -69,6 +70,15 @@ static char dpaa2_ethtool_extras[][ETH_G
- 	"[drv] dequeue portal busy",
- 	"[drv] channel pull errors",
- 	"[drv] cdan",
-+	"[drv] tx congestion state",
-+#ifdef CONFIG_FSL_QBMAN_DEBUG
-+	/* FQ stats */
-+	"rx pending frames",
-+	"rx pending bytes",
-+	"tx conf pending frames",
-+	"tx conf pending bytes",
-+	"buffer count"
-+#endif
- };
- 
- #define DPAA2_ETH_NUM_EXTRA_STATS	ARRAY_SIZE(dpaa2_ethtool_extras)
-@@ -76,10 +86,15 @@ static char dpaa2_ethtool_extras[][ETH_G
- static void dpaa2_eth_get_drvinfo(struct net_device *net_dev,
- 				  struct ethtool_drvinfo *drvinfo)
- {
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+
- 	strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
- 	strlcpy(drvinfo->version, dpaa2_eth_drv_version,
- 		sizeof(drvinfo->version));
--	strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
-+
-+	snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
-+		 "%u.%u", priv->dpni_ver_major, priv->dpni_ver_minor);
-+
- 	strlcpy(drvinfo->bus_info, dev_name(net_dev->dev.parent->parent),
- 		sizeof(drvinfo->bus_info));
- }
-@@ -113,25 +128,37 @@ out:
- 	return err;
- }
- 
-+#define DPNI_DYNAMIC_LINK_SET_VER_MAJOR		7
-+#define DPNI_DYNAMIC_LINK_SET_VER_MINOR		1
- static int
- dpaa2_eth_set_link_ksettings(struct net_device *net_dev,
- 			     const struct ethtool_link_ksettings *link_settings)
- {
--	struct dpni_link_cfg cfg = {0};
- 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct dpni_link_state state = {0};
-+	struct dpni_link_cfg cfg = {0};
- 	int err = 0;
- 
--	netdev_dbg(net_dev, "Setting link parameters...");
-+	/* If using an older MC version, the DPNI must be down
-+ 	 * in order to be able to change link settings. Taking steps to let
-+ 	 * the user know that.
-+ 	 */
-+	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_DYNAMIC_LINK_SET_VER_MAJOR,
-+				   DPNI_DYNAMIC_LINK_SET_VER_MINOR) < 0) {
-+		if (netif_running(net_dev)) {
-+			netdev_info(net_dev, "Interface must be brought down first.\n");
-+			return -EACCES;
-+		}
-+	}
- 
--	/* Due to a temporary MC limitation, the DPNI must be down
--	 * in order to be able to change link settings. Taking steps to let
--	 * the user know that.
--	 */
--	if (netif_running(net_dev)) {
--		netdev_info(net_dev, "Sorry, interface must be brought down first.\n");
--		return -EACCES;
-+	/* Need to interrogate link state to get flow control params */
-+	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
-+	if (err) {
-+		netdev_err(net_dev, "Error getting link state\n");
-+		goto out;
- 	}
- 
-+	cfg.options = state.options;
- 	cfg.rate = link_settings->base.speed;
- 	if (link_settings->base.autoneg == AUTONEG_ENABLE)
- 		cfg.options |= DPNI_LINK_OPT_AUTONEG;
-@@ -149,6 +176,81 @@ dpaa2_eth_set_link_ksettings(struct net_
- 		 */
- 		netdev_dbg(net_dev, "ERROR %d setting link cfg\n", err);
- 
-+out:
-+	return err;
-+}
-+
-+static void dpaa2_eth_get_pauseparam(struct net_device *net_dev,
-+				     struct ethtool_pauseparam *pause)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct dpni_link_state state = {0};
-+	int err;
-+
-+	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
-+	if (err)
-+		netdev_dbg(net_dev, "Error getting link state\n");
-+
-+	/* Report general port autonegotiation status */
-+	pause->autoneg = !!(state.options & DPNI_LINK_OPT_AUTONEG);
-+	pause->rx_pause = !!(state.options & DPNI_LINK_OPT_PAUSE);
-+	pause->tx_pause = pause->rx_pause ^
-+			  !!(state.options & DPNI_LINK_OPT_ASYM_PAUSE);
-+}
-+
-+static int dpaa2_eth_set_pauseparam(struct net_device *net_dev,
-+				    struct ethtool_pauseparam *pause)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct dpni_link_state state = {0};
-+	struct dpni_link_cfg cfg = {0};
-+	u32 current_tx_pause;
-+	int err = 0;
-+
-+	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
-+	if (err) {
-+		netdev_dbg(net_dev, "Error getting link state\n");
-+		goto out;
-+	}
-+
-+	cfg.rate = state.rate;
-+	cfg.options = state.options;
-+	current_tx_pause = !!(cfg.options & DPNI_LINK_OPT_PAUSE) ^
-+			   !!(cfg.options & DPNI_LINK_OPT_ASYM_PAUSE);
-+
-+	/* We don't support changing pause frame autonegotiation separately
-+	 * from general port autoneg
-+	 */
-+	if (pause->autoneg != !!(state.options & DPNI_LINK_OPT_AUTONEG))
-+		netdev_warn(net_dev,
-+			    "Cannot change pause frame autoneg separately\n");
-+
-+	if (pause->rx_pause)
-+		cfg.options |= DPNI_LINK_OPT_PAUSE;
-+	else
-+		cfg.options &= ~DPNI_LINK_OPT_PAUSE;
-+
-+	if (pause->rx_pause ^ pause->tx_pause)
-+		cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
-+	else
-+		cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
-+
-+	err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &cfg);
-+	if (err) {
-+		netdev_dbg(net_dev, "Error setting link\n");
-+		goto out;
-+	}
-+
-+	/* Enable/disable Rx FQ taildrop if Tx pause frames have changed */
-+	if (current_tx_pause == pause->tx_pause)
-+		goto out;
-+
-+	priv->tx_pause_frames = pause->tx_pause;
-+	err = set_rx_taildrop(priv);
-+	if (err)
-+		netdev_dbg(net_dev, "Error configuring taildrop\n");
-+
-+out:
- 	return err;
- }
- 
-@@ -192,6 +294,13 @@ static void dpaa2_eth_get_ethtool_stats(
- 	int j, k, err;
- 	int num_cnt;
- 	union dpni_statistics dpni_stats;
-+
-+#ifdef CONFIG_FSL_QBMAN_DEBUG
-+	u32 fcnt, bcnt;
-+	u32 fcnt_rx_total = 0, fcnt_tx_total = 0;
-+	u32 bcnt_rx_total = 0, bcnt_tx_total = 0;
-+	u32 buf_cnt;
-+#endif
- 	u64 cdan = 0;
- 	u64 portal_busy = 0, pull_err = 0;
- 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-@@ -204,7 +313,7 @@ static void dpaa2_eth_get_ethtool_stats(
- 	/* Print standard counters, from DPNI statistics */
- 	for (j = 0; j <= 2; j++) {
- 		err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token,
--					  j, &dpni_stats);
-+					  j, 0, &dpni_stats);
- 		if (err != 0)
- 			netdev_warn(net_dev, "dpni_get_stats(%d) failed\n", j);
- 		switch (j) {
-@@ -240,12 +349,474 @@ static void dpaa2_eth_get_ethtool_stats(
- 	*(data + i++) = portal_busy;
- 	*(data + i++) = pull_err;
- 	*(data + i++) = cdan;
-+
-+	*(data + i++) = dpaa2_cscn_state_congested(priv->cscn_mem);
-+
-+#ifdef CONFIG_FSL_QBMAN_DEBUG
-+	for (j = 0; j < priv->num_fqs; j++) {
-+		/* Print FQ instantaneous counts */
-+		err = dpaa2_io_query_fq_count(NULL, priv->fq[j].fqid,
-+					      &fcnt, &bcnt);
-+		if (err) {
-+			netdev_warn(net_dev, "FQ query error %d", err);
-+			return;
-+		}
-+
-+		if (priv->fq[j].type == DPAA2_TX_CONF_FQ) {
-+			fcnt_tx_total += fcnt;
-+			bcnt_tx_total += bcnt;
-+		} else {
-+			fcnt_rx_total += fcnt;
-+			bcnt_rx_total += bcnt;
-+		}
-+	}
-+
-+	*(data + i++) = fcnt_rx_total;
-+	*(data + i++) = bcnt_rx_total;
-+	*(data + i++) = fcnt_tx_total;
-+	*(data + i++) = bcnt_tx_total;
-+
-+	err = dpaa2_io_query_bp_count(NULL, priv->bpid, &buf_cnt);
-+	if (err) {
-+		netdev_warn(net_dev, "Buffer count query error %d\n", err);
-+		return;
-+	}
-+	*(data + i++) = buf_cnt;
-+#endif
-+}
-+
-+static int cls_key_off(struct dpaa2_eth_priv *priv, int prot, int field)
-+{
-+	int i, off = 0;
-+
-+	for (i = 0; i < priv->num_dist_fields; i++) {
-+		if (priv->dist_fields[i].cls_prot == prot &&
-+		    priv->dist_fields[i].cls_field == field)
-+			return off;
-+		off += priv->dist_fields[i].size;
-+	}
-+
-+	return -1;
-+}
-+
-+static u8 cls_key_size(struct dpaa2_eth_priv *priv)
-+{
-+	u8 i, size = 0;
-+
-+	for (i = 0; i < priv->num_dist_fields; i++)
-+		size += priv->dist_fields[i].size;
-+
-+	return size;
-+}
-+
-+void check_cls_support(struct dpaa2_eth_priv *priv)
-+{
-+	u8 key_size = cls_key_size(priv);
-+	struct device *dev = priv->net_dev->dev.parent;
-+
-+	if (dpaa2_eth_hash_enabled(priv)) {
-+		if (priv->dpni_attrs.fs_key_size < key_size) {
-+			dev_info(dev, "max_dist_key_size = %d, expected %d. Hashing and steering are disabled\n",
-+				 priv->dpni_attrs.fs_key_size,
-+				 key_size);
-+			goto disable_fs;
-+		}
-+		if (priv->num_dist_fields > DPKG_MAX_NUM_OF_EXTRACTS) {
-+			dev_info(dev, "Too many key fields (max = %d). Hashing and steering are disabled\n",
-+				 DPKG_MAX_NUM_OF_EXTRACTS);
-+			goto disable_fs;
-+		}
-+	}
-+
-+	if (dpaa2_eth_fs_enabled(priv)) {
-+		if (!dpaa2_eth_hash_enabled(priv)) {
-+			dev_info(dev, "Insufficient queues. Steering is disabled\n");
-+			goto disable_fs;
-+		}
-+
-+		if (!dpaa2_eth_fs_mask_enabled(priv)) {
-+			dev_info(dev, "Key masks not supported. Steering is disabled\n");
-+			goto disable_fs;
-+		}
-+	}
-+
-+	return;
-+
-+disable_fs:
-+	priv->dpni_attrs.options |= DPNI_OPT_NO_FS;
-+	priv->dpni_attrs.options &= ~DPNI_OPT_HAS_KEY_MASKING;
-+}
-+
-+static int prep_l4_rule(struct dpaa2_eth_priv *priv,
-+			struct ethtool_tcpip4_spec *l4_value,
-+			struct ethtool_tcpip4_spec *l4_mask,
-+			void *key, void *mask, u8 l4_proto)
-+{
-+	int offset;
-+
-+	if (l4_mask->tos) {
-+		netdev_err(priv->net_dev, "ToS is not supported for IPv4 L4\n");
-+		return -EOPNOTSUPP;
-+	}
-+
-+	if (l4_mask->ip4src) {
-+		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_SRC);
-+		*(u32 *)(key + offset) = l4_value->ip4src;
-+		*(u32 *)(mask + offset) = l4_mask->ip4src;
-+	}
-+
-+	if (l4_mask->ip4dst) {
-+		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_DST);
-+		*(u32 *)(key + offset) = l4_value->ip4dst;
-+		*(u32 *)(mask + offset) = l4_mask->ip4dst;
-+	}
-+
-+	if (l4_mask->psrc) {
-+		offset = cls_key_off(priv, NET_PROT_UDP, NH_FLD_UDP_PORT_SRC);
-+		*(u32 *)(key + offset) = l4_value->psrc;
-+		*(u32 *)(mask + offset) = l4_mask->psrc;
-+	}
-+
-+	if (l4_mask->pdst) {
-+		offset = cls_key_off(priv, NET_PROT_UDP, NH_FLD_UDP_PORT_DST);
-+		*(u32 *)(key + offset) = l4_value->pdst;
-+		*(u32 *)(mask + offset) = l4_mask->pdst;
-+	}
-+
-+	/* Only apply the rule for the user-specified L4 protocol
-+	 * and if ethertype matches IPv4
-+	 */
-+	offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_TYPE);
-+	*(u16 *)(key + offset) = htons(ETH_P_IP);
-+	*(u16 *)(mask + offset) = 0xFFFF;
-+
-+	offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_PROTO);
-+	*(u8 *)(key + offset) = l4_proto;
-+	*(u8 *)(mask + offset) = 0xFF;
-+
-+	/* TODO: check IP version */
-+
-+	return 0;
-+}
-+
-+static int prep_eth_rule(struct dpaa2_eth_priv *priv,
-+			 struct ethhdr *eth_value, struct ethhdr *eth_mask,
-+			 void *key, void *mask)
-+{
-+	int offset;
-+
-+	if (eth_mask->h_proto) {
-+		netdev_err(priv->net_dev, "Ethertype is not supported!\n");
-+		return -EOPNOTSUPP;
-+	}
-+
-+	if (!is_zero_ether_addr(eth_mask->h_source)) {
-+		offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_SA);
-+		ether_addr_copy(key + offset, eth_value->h_source);
-+		ether_addr_copy(mask + offset, eth_mask->h_source);
-+	}
-+
-+	if (!is_zero_ether_addr(eth_mask->h_dest)) {
-+		offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_DA);
-+		ether_addr_copy(key + offset, eth_value->h_dest);
-+		ether_addr_copy(mask + offset, eth_mask->h_dest);
-+	}
-+
-+	return 0;
-+}
-+
-+static int prep_user_ip_rule(struct dpaa2_eth_priv *priv,
-+			     struct ethtool_usrip4_spec *uip_value,
-+			     struct ethtool_usrip4_spec *uip_mask,
-+			     void *key, void *mask)
-+{
-+	int offset;
-+
-+	if (uip_mask->tos)
-+		return -EOPNOTSUPP;
-+
-+	if (uip_mask->ip4src) {
-+		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_SRC);
-+		*(u32 *)(key + offset) = uip_value->ip4src;
-+		*(u32 *)(mask + offset) = uip_mask->ip4src;
-+	}
-+
-+	if (uip_mask->ip4dst) {
-+		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_DST);
-+		*(u32 *)(key + offset) = uip_value->ip4dst;
-+		*(u32 *)(mask + offset) = uip_mask->ip4dst;
-+	}
-+
-+	if (uip_mask->proto) {
-+		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_PROTO);
-+		*(u32 *)(key + offset) = uip_value->proto;
-+		*(u32 *)(mask + offset) = uip_mask->proto;
-+	}
-+	if (uip_mask->l4_4_bytes) {
-+		offset = cls_key_off(priv, NET_PROT_UDP, NH_FLD_UDP_PORT_SRC);
-+		*(u16 *)(key + offset) = uip_value->l4_4_bytes << 16;
-+		*(u16 *)(mask + offset) = uip_mask->l4_4_bytes << 16;
-+
-+		offset = cls_key_off(priv, NET_PROT_UDP, NH_FLD_UDP_PORT_DST);
-+		*(u16 *)(key + offset) = uip_value->l4_4_bytes & 0xFFFF;
-+		*(u16 *)(mask + offset) = uip_mask->l4_4_bytes & 0xFFFF;
-+	}
-+
-+	/* Ethertype must be IP */
-+	offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_TYPE);
-+	*(u16 *)(key + offset) = htons(ETH_P_IP);
-+	*(u16 *)(mask + offset) = 0xFFFF;
-+
-+	return 0;
-+}
-+
-+static int prep_ext_rule(struct dpaa2_eth_priv *priv,
-+			 struct ethtool_flow_ext *ext_value,
-+			 struct ethtool_flow_ext *ext_mask,
-+			 void *key, void *mask)
-+{
-+	int offset;
-+
-+	if (ext_mask->vlan_etype)
-+		return -EOPNOTSUPP;
-+
-+	if (ext_mask->vlan_tci) {
-+		offset = cls_key_off(priv, NET_PROT_VLAN, NH_FLD_VLAN_TCI);
-+		*(u16 *)(key + offset) = ext_value->vlan_tci;
-+		*(u16 *)(mask + offset) = ext_mask->vlan_tci;
-+	}
-+
-+	return 0;
-+}
-+
-+static int prep_mac_ext_rule(struct dpaa2_eth_priv *priv,
-+			     struct ethtool_flow_ext *ext_value,
-+			     struct ethtool_flow_ext *ext_mask,
-+			     void *key, void *mask)
-+{
-+	int offset;
-+
-+	if (!is_zero_ether_addr(ext_mask->h_dest)) {
-+		offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_DA);
-+		ether_addr_copy(key + offset, ext_value->h_dest);
-+		ether_addr_copy(mask + offset, ext_mask->h_dest);
-+	}
-+
-+	return 0;
-+}
-+
-+static int prep_cls_rule(struct net_device *net_dev,
-+			 struct ethtool_rx_flow_spec *fs,
-+			 void *key)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	const u8 key_size = cls_key_size(priv);
-+	void *msk = key + key_size;
-+	int err;
-+
-+	memset(key, 0, key_size * 2);
-+
-+	switch (fs->flow_type & 0xff) {
-+	case TCP_V4_FLOW:
-+		err = prep_l4_rule(priv, &fs->h_u.tcp_ip4_spec,
-+				   &fs->m_u.tcp_ip4_spec, key, msk,
-+				   IPPROTO_TCP);
-+		break;
-+	case UDP_V4_FLOW:
-+		err = prep_l4_rule(priv, &fs->h_u.udp_ip4_spec,
-+				   &fs->m_u.udp_ip4_spec, key, msk,
-+				   IPPROTO_UDP);
-+		break;
-+	case SCTP_V4_FLOW:
-+		err = prep_l4_rule(priv, &fs->h_u.sctp_ip4_spec,
-+				   &fs->m_u.sctp_ip4_spec, key, msk,
-+				   IPPROTO_SCTP);
-+		break;
-+	case ETHER_FLOW:
-+		err = prep_eth_rule(priv, &fs->h_u.ether_spec,
-+				    &fs->m_u.ether_spec, key, msk);
-+		break;
-+	case IP_USER_FLOW:
-+		err = prep_user_ip_rule(priv, &fs->h_u.usr_ip4_spec,
-+					&fs->m_u.usr_ip4_spec, key, msk);
-+		break;
-+	default:
-+		/* TODO: AH, ESP */
-+		return -EOPNOTSUPP;
-+	}
-+	if (err)
-+		return err;
-+
-+	if (fs->flow_type & FLOW_EXT) {
-+		err = prep_ext_rule(priv, &fs->h_ext, &fs->m_ext, key, msk);
-+		if (err)
-+			return err;
-+	}
-+
-+	if (fs->flow_type & FLOW_MAC_EXT) {
-+		err = prep_mac_ext_rule(priv, &fs->h_ext, &fs->m_ext, key, msk);
-+		if (err)
-+			return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static int del_cls(struct net_device *net_dev, int location);
-+
-+static int do_cls(struct net_device *net_dev,
-+		  struct ethtool_rx_flow_spec *fs,
-+		  bool add)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	struct device *dev = net_dev->dev.parent;
-+	const int rule_cnt = dpaa2_eth_fs_count(priv);
-+	struct dpni_rule_cfg rule_cfg;
-+	struct dpni_fs_action_cfg fs_act = { 0 };
-+	void *dma_mem;
-+	int err = 0, tc;
-+
-+	if (!dpaa2_eth_fs_enabled(priv)) {
-+		netdev_err(net_dev, "dev does not support steering!\n");
-+		/* dev doesn't support steering */
-+		return -EOPNOTSUPP;
-+	}
-+
-+	if ((fs->ring_cookie != RX_CLS_FLOW_DISC &&
-+	     fs->ring_cookie >= dpaa2_eth_queue_count(priv)) ||
-+	     fs->location >= rule_cnt)
-+		return -EINVAL;
-+
-+	/* When adding a new rule, check if location if available
-+	 * and if not, free the existing table entry before inserting
-+	 * the new one
-+	 */
-+	if (add && (priv->cls_rule[fs->location].in_use == true))
-+		del_cls(net_dev, fs->location);
-+
-+	memset(&rule_cfg, 0, sizeof(rule_cfg));
-+	rule_cfg.key_size = cls_key_size(priv);
-+
-+	/* allocate twice the key size, for the actual key and for mask */
-+	dma_mem = kzalloc(rule_cfg.key_size * 2, GFP_DMA | GFP_KERNEL);
-+	if (!dma_mem)
-+		return -ENOMEM;
-+
-+	err = prep_cls_rule(net_dev, fs, dma_mem);
-+	if (err)
-+		goto err_free_mem;
-+
-+	rule_cfg.key_iova = dma_map_single(dev, dma_mem,
-+					   rule_cfg.key_size * 2,
-+					   DMA_TO_DEVICE);
-+
-+	rule_cfg.mask_iova = rule_cfg.key_iova + rule_cfg.key_size;
-+
-+	if (fs->ring_cookie == RX_CLS_FLOW_DISC)
-+		fs_act.options |= DPNI_FS_OPT_DISCARD;
-+	else
-+		fs_act.flow_id = fs->ring_cookie;
-+
-+	for (tc = 0; tc < dpaa2_eth_tc_count(priv); tc++) {
-+		if (add)
-+			err = dpni_add_fs_entry(priv->mc_io, 0, priv->mc_token,
-+						tc, fs->location, &rule_cfg,
-+						&fs_act);
-+		else
-+			err = dpni_remove_fs_entry(priv->mc_io, 0,
-+						   priv->mc_token, tc,
-+						   &rule_cfg);
-+
-+		if (err)
-+			break;
-+	}
-+
-+	dma_unmap_single(dev, rule_cfg.key_iova,
-+			 rule_cfg.key_size * 2, DMA_TO_DEVICE);
-+
-+	if (err)
-+		netdev_err(net_dev, "dpaa2_add/remove_cls() error %d\n", err);
-+
-+err_free_mem:
-+	kfree(dma_mem);
-+
-+	return err;
-+}
-+
-+static int add_cls(struct net_device *net_dev,
-+		   struct ethtool_rx_flow_spec *fs)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	int err;
-+
-+	err = do_cls(net_dev, fs, true);
-+	if (err)
-+		return err;
-+
-+	priv->cls_rule[fs->location].in_use = true;
-+	priv->cls_rule[fs->location].fs = *fs;
-+
-+	return 0;
-+}
-+
-+static int del_cls(struct net_device *net_dev, int location)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	int err;
-+
-+	err = do_cls(net_dev, &priv->cls_rule[location].fs, false);
-+	if (err)
-+		return err;
-+
-+	priv->cls_rule[location].in_use = false;
-+
-+	return 0;
-+}
-+
-+static int set_hash(struct net_device *net_dev, u64 data)
-+{
-+	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	u32 key = 0;
-+	int i;
-+
-+	if (data & RXH_DISCARD)
-+		return -EOPNOTSUPP;
-+
-+	for (i = 0; i < priv->num_dist_fields; i++)
-+		if (priv->dist_fields[i].rxnfc_field & data)
-+			key |= priv->dist_fields[i].id;
-+
-+	return dpaa2_eth_set_dist_key(priv, DPAA2_ETH_RX_DIST_HASH, key);
-+}
-+
-+static int dpaa2_eth_set_rxnfc(struct net_device *net_dev,
-+			       struct ethtool_rxnfc *rxnfc)
-+{
-+	int err = 0;
-+
-+	switch (rxnfc->cmd) {
-+	case ETHTOOL_SRXCLSRLINS:
-+		err = add_cls(net_dev, &rxnfc->fs);
-+		break;
-+	case ETHTOOL_SRXCLSRLDEL:
-+		err = del_cls(net_dev, rxnfc->fs.location);
-+		break;
-+	case ETHTOOL_SRXFH:
-+		err = set_hash(net_dev, rxnfc->data);
-+		break;
-+	default:
-+		err = -EOPNOTSUPP;
-+	}
-+
-+	return err;
- }
- 
- static int dpaa2_eth_get_rxnfc(struct net_device *net_dev,
- 			       struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
- {
- 	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
-+	const int rule_cnt = dpaa2_eth_fs_count(priv);
-+	int i, j;
- 
- 	switch (rxnfc->cmd) {
- 	case ETHTOOL_GRXFH:
-@@ -258,6 +829,33 @@ static int dpaa2_eth_get_rxnfc(struct ne
- 	case ETHTOOL_GRXRINGS:
- 		rxnfc->data = dpaa2_eth_queue_count(priv);
- 		break;
-+
-+	case ETHTOOL_GRXCLSRLCNT:
-+		for (i = 0, rxnfc->rule_cnt = 0; i < rule_cnt; i++)
-+			if (priv->cls_rule[i].in_use)
-+				rxnfc->rule_cnt++;
-+		rxnfc->data = rule_cnt;
-+		break;
-+
-+	case ETHTOOL_GRXCLSRULE:
-+		if (!priv->cls_rule[rxnfc->fs.location].in_use)
-+			return -EINVAL;
-+
-+		rxnfc->fs = priv->cls_rule[rxnfc->fs.location].fs;
-+		break;
-+
-+	case ETHTOOL_GRXCLSRLALL:
-+		for (i = 0, j = 0; i < rule_cnt; i++) {
-+			if (!priv->cls_rule[i].in_use)
-+				continue;
-+			if (j == rxnfc->rule_cnt)
-+				return -EMSGSIZE;
-+			rule_locs[j++] = i;
-+		}
-+		rxnfc->rule_cnt = j;
-+		rxnfc->data = rule_cnt;
-+		break;
-+
- 	default:
- 		return -EOPNOTSUPP;
- 	}
-@@ -270,8 +868,11 @@ const struct ethtool_ops dpaa2_ethtool_o
- 	.get_link = ethtool_op_get_link,
- 	.get_link_ksettings = dpaa2_eth_get_link_ksettings,
- 	.set_link_ksettings = dpaa2_eth_set_link_ksettings,
-+	.get_pauseparam = dpaa2_eth_get_pauseparam,
-+	.set_pauseparam = dpaa2_eth_set_pauseparam,
- 	.get_sset_count = dpaa2_eth_get_sset_count,
- 	.get_ethtool_stats = dpaa2_eth_get_ethtool_stats,
- 	.get_strings = dpaa2_eth_get_strings,
- 	.get_rxnfc = dpaa2_eth_get_rxnfc,
-+	.set_rxnfc = dpaa2_eth_set_rxnfc,
- };
---- a/drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h
-@@ -39,9 +39,11 @@
- #define DPNI_VER_MAJOR				7
- #define DPNI_VER_MINOR				0
- #define DPNI_CMD_BASE_VERSION			1
-+#define DPNI_CMD_2ND_VERSION			2
- #define DPNI_CMD_ID_OFFSET			4
- 
- #define DPNI_CMD(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION)
-+#define DPNI_CMD_V2(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_2ND_VERSION)
- 
- #define DPNI_CMDID_OPEN					DPNI_CMD(0x801)
- #define DPNI_CMDID_CLOSE				DPNI_CMD(0x800)
-@@ -64,7 +66,7 @@
- #define DPNI_CMDID_GET_IRQ_STATUS			DPNI_CMD(0x016)
- #define DPNI_CMDID_CLEAR_IRQ_STATUS			DPNI_CMD(0x017)
- 
--#define DPNI_CMDID_SET_POOLS				DPNI_CMD(0x200)
-+#define DPNI_CMDID_SET_POOLS				DPNI_CMD_V2(0x200)
- #define DPNI_CMDID_SET_ERRORS_BEHAVIOR			DPNI_CMD(0x20B)
- 
- #define DPNI_CMDID_GET_QDID				DPNI_CMD(0x210)
-@@ -73,7 +75,7 @@
- #define DPNI_CMDID_SET_MAX_FRAME_LENGTH			DPNI_CMD(0x216)
- #define DPNI_CMDID_GET_MAX_FRAME_LENGTH			DPNI_CMD(0x217)
- #define DPNI_CMDID_SET_LINK_CFG				DPNI_CMD(0x21A)
--#define DPNI_CMDID_SET_TX_SHAPING			DPNI_CMD(0x21B)
-+#define DPNI_CMDID_SET_TX_SHAPING			DPNI_CMD_V2(0x21B)
- 
- #define DPNI_CMDID_SET_MCAST_PROMISC			DPNI_CMD(0x220)
- #define DPNI_CMDID_GET_MCAST_PROMISC			DPNI_CMD(0x221)
-@@ -87,11 +89,16 @@
- 
- #define DPNI_CMDID_SET_RX_TC_DIST			DPNI_CMD(0x235)
- 
-+#define DPNI_CMDID_SET_QOS_TBL				DPNI_CMD(0x240)
-+#define DPNI_CMDID_ADD_QOS_ENT				DPNI_CMD(0x241)
-+#define DPNI_CMDID_REMOVE_QOS_ENT			DPNI_CMD(0x242)
- #define DPNI_CMDID_ADD_FS_ENT				DPNI_CMD(0x244)
- #define DPNI_CMDID_REMOVE_FS_ENT			DPNI_CMD(0x245)
- #define DPNI_CMDID_CLR_FS_ENT				DPNI_CMD(0x246)
- 
--#define DPNI_CMDID_GET_STATISTICS			DPNI_CMD(0x25D)
-+#define DPNI_CMDID_SET_TX_PRIORITIES			DPNI_CMD_V2(0x250)
-+#define DPNI_CMDID_GET_STATISTICS			DPNI_CMD_V2(0x25D)
-+#define DPNI_CMDID_RESET_STATISTICS			DPNI_CMD(0x25E)
- #define DPNI_CMDID_GET_QUEUE				DPNI_CMD(0x25F)
- #define DPNI_CMDID_SET_QUEUE				DPNI_CMD(0x260)
- #define DPNI_CMDID_GET_TAILDROP				DPNI_CMD(0x261)
-@@ -110,6 +117,9 @@
- #define DPNI_CMDID_GET_OFFLOAD				DPNI_CMD(0x26B)
- #define DPNI_CMDID_SET_OFFLOAD				DPNI_CMD(0x26C)
- 
-+#define DPNI_CMDID_SET_RX_FS_DIST			DPNI_CMD(0x273)
-+#define DPNI_CMDID_SET_RX_HASH_DIST			DPNI_CMD(0x274)
-+
- /* Macros for accessing command fields smaller than 1byte */
- #define DPNI_MASK(field)	\
- 	GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \
-@@ -126,13 +136,14 @@ struct dpni_cmd_open {
- 
- #define DPNI_BACKUP_POOL(val, order)	(((val) & 0x1) << (order))
- struct dpni_cmd_set_pools {
--	/* cmd word 0 */
- 	u8 num_dpbp;
- 	u8 backup_pool_mask;
- 	__le16 pad;
--	/* cmd word 0..4 */
--	__le32 dpbp_id[DPNI_MAX_DPBP];
--	/* cmd word 4..6 */
-+	struct {
-+		__le16 dpbp_id;
-+		u8 priority_mask;
-+		u8 pad;
-+	} pool[DPNI_MAX_DPBP];
- 	__le16 buffer_size[DPNI_MAX_DPBP];
- };
- 
-@@ -303,6 +314,7 @@ struct dpni_rsp_get_tx_data_offset {
- 
- struct dpni_cmd_get_statistics {
- 	u8 page_number;
-+	u8 param;
- };
- 
- struct dpni_rsp_get_statistics {
-@@ -335,6 +347,22 @@ struct dpni_rsp_get_link_state {
- 	__le64 options;
- };
- 
-+#define DPNI_COUPLED_SHIFT	0
-+#define DPNI_COUPLED_SIZE	1
-+
-+struct dpni_cmd_set_tx_shaping {
-+	/* cmd word 0 */
-+	__le16 tx_cr_max_burst_size;
-+	__le16 tx_er_max_burst_size;
-+	__le32 pad;
-+	/* cmd word 1 */
-+	__le32 tx_cr_rate_limit;
-+	__le32 tx_er_rate_limit;
-+	/* cmd word 2 */
-+	/* from LSB: coupled:1 */
-+	u8 coupled;
-+};
-+
- struct dpni_cmd_set_max_frame_length {
- 	__le16 max_frame_length;
- };
-@@ -394,6 +422,24 @@ struct dpni_cmd_clear_mac_filters {
- 	u8 flags;
- };
- 
-+#define DPNI_SEPARATE_GRP_SHIFT 0
-+#define DPNI_SEPARATE_GRP_SIZE  1
-+#define DPNI_MODE_1_SHIFT		0
-+#define DPNI_MODE_1_SIZE		4
-+#define DPNI_MODE_2_SHIFT		4
-+#define DPNI_MODE_2_SIZE		4
-+
-+struct dpni_cmd_set_tx_priorities {
-+	__le16 flags;
-+	u8 prio_group_A;
-+	u8 prio_group_B;
-+	__le32 pad0;
-+	u8 modes[4];
-+	__le32 pad1;
-+	__le64 pad2;
-+	__le16 delta_bandwidth[8];
-+};
-+
- #define DPNI_DIST_MODE_SHIFT		0
- #define DPNI_DIST_MODE_SIZE		4
- #define DPNI_MISS_ACTION_SHIFT		4
-@@ -503,6 +549,63 @@ struct dpni_cmd_set_queue {
- 	__le64 user_context;
- };
- 
-+#define DPNI_DISCARD_ON_MISS_SHIFT	0
-+#define DPNI_DISCARD_ON_MISS_SIZE	1
-+
-+struct dpni_cmd_set_qos_table {
-+	__le32 pad;
-+	u8 default_tc;
-+	/* only the LSB */
-+	u8 discard_on_miss;
-+	__le16 pad1[21];
-+	__le64 key_cfg_iova;
-+};
-+
-+struct dpni_cmd_add_qos_entry {
-+	__le16 pad;
-+	u8 tc_id;
-+	u8 key_size;
-+	__le16 index;
-+	__le16 pad2;
-+	__le64 key_iova;
-+	__le64 mask_iova;
-+};
-+
-+struct dpni_cmd_remove_qos_entry {
-+	u8 pad1[3];
-+	u8 key_size;
-+	__le32 pad2;
-+	__le64 key_iova;
-+	__le64 mask_iova;
-+};
-+
-+struct dpni_cmd_add_fs_entry {
-+	/* cmd word 0 */
-+	__le16 options;
-+	u8 tc_id;
-+	u8 key_size;
-+	__le16 index;
-+	__le16 flow_id;
-+	/* cmd word 1 */
-+	__le64 key_iova;
-+	/* cmd word 2 */
-+	__le64 mask_iova;
-+	/* cmd word 3 */
-+	__le64 flc;
-+};
-+
-+struct dpni_cmd_remove_fs_entry {
-+	/* cmd word 0 */
-+	__le16 pad0;
-+	u8 tc_id;
-+	u8 key_size;
-+	__le32 pad1;
-+	/* cmd word 1 */
-+	__le64 key_iova;
-+	/* cmd word 2 */
-+	__le64 mask_iova;
-+};
-+
- struct dpni_cmd_set_taildrop {
- 	/* cmd word 0 */
- 	u8 congestion_point;
-@@ -538,4 +641,79 @@ struct dpni_rsp_get_taildrop {
- 	__le32 threshold;
- };
- 
-+struct dpni_rsp_get_api_version {
-+	u16 major;
-+	u16 minor;
-+};
-+
-+#define DPNI_DEST_TYPE_SHIFT		0
-+#define DPNI_DEST_TYPE_SIZE		4
-+#define DPNI_CONG_UNITS_SHIFT		4
-+#define DPNI_CONG_UNITS_SIZE		2
-+
-+struct dpni_cmd_set_congestion_notification {
-+	/* cmd word 0 */
-+	u8 qtype;
-+	u8 tc;
-+	u8 pad[6];
-+	/* cmd word 1 */
-+	__le32 dest_id;
-+	__le16 notification_mode;
-+	u8 dest_priority;
-+	/* from LSB: dest_type: 4 units:2 */
-+	u8 type_units;
-+	/* cmd word 2 */
-+	__le64 message_iova;
-+	/* cmd word 3 */
-+	__le64 message_ctx;
-+	/* cmd word 4 */
-+	__le32 threshold_entry;
-+	__le32 threshold_exit;
-+};
-+
-+struct dpni_cmd_get_congestion_notification {
-+	/* cmd word 0 */
-+	u8 qtype;
-+	u8 tc;
-+};
-+
-+struct dpni_rsp_get_congestion_notification {
-+	/* cmd word 0 */
-+	__le64 pad;
-+	/* cmd word 1 */
-+	__le32 dest_id;
-+	__le16 notification_mode;
-+	u8 dest_priority;
-+	/* from LSB: dest_type: 4 units:2 */
-+	u8 type_units;
-+	/* cmd word 2 */
-+	__le64 message_iova;
-+	/* cmd word 3 */
-+	__le64 message_ctx;
-+	/* cmd word 4 */
-+	__le32 threshold_entry;
-+	__le32 threshold_exit;
-+};
-+
-+#define DPNI_RX_FS_DIST_ENABLE_SHIFT	0
-+#define DPNI_RX_FS_DIST_ENABLE_SIZE	1
-+struct dpni_cmd_set_rx_fs_dist {
-+	__le16 dist_size;
-+	u8 enable;
-+	u8 tc;
-+	__le16 miss_flow_id;
-+	__le16 pad;
-+	__le64 key_cfg_iova;
-+};
-+
-+#define DPNI_RX_HASH_DIST_ENABLE_SHIFT	0
-+#define DPNI_RX_HASH_DIST_ENABLE_SIZE	1
-+struct dpni_cmd_set_rx_hash_dist {
-+	__le16 dist_size;
-+	u8 enable;
-+	u8 tc;
-+	__le32 pad;
-+	__le64 key_cfg_iova;
-+};
-+
- #endif /* _FSL_DPNI_CMD_H */
---- a/drivers/staging/fsl-dpaa2/ethernet/dpni.c
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c
-@@ -122,7 +122,7 @@ int dpni_open(struct fsl_mc_io *mc_io,
- 	      int dpni_id,
- 	      u16 *token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_open *cmd_params;
- 
- 	int err;
-@@ -160,7 +160,7 @@ int dpni_close(struct fsl_mc_io *mc_io,
- 	       u32 cmd_flags,
- 	       u16 token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 
- 	/* prepare command */
- 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLOSE,
-@@ -188,7 +188,7 @@ int dpni_set_pools(struct fsl_mc_io *mc_
- 		   u16 token,
- 		   const struct dpni_pools_cfg *cfg)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_pools *cmd_params;
- 	int i;
- 
-@@ -199,7 +199,10 @@ int dpni_set_pools(struct fsl_mc_io *mc_
- 	cmd_params = (struct dpni_cmd_set_pools *)cmd.params;
- 	cmd_params->num_dpbp = cfg->num_dpbp;
- 	for (i = 0; i < DPNI_MAX_DPBP; i++) {
--		cmd_params->dpbp_id[i] = cpu_to_le32(cfg->pools[i].dpbp_id);
-+		cmd_params->pool[i].dpbp_id =
-+			cpu_to_le16(cfg->pools[i].dpbp_id);
-+		cmd_params->pool[i].priority_mask =
-+			cfg->pools[i].priority_mask;
- 		cmd_params->buffer_size[i] =
- 			cpu_to_le16(cfg->pools[i].buffer_size);
- 		cmd_params->backup_pool_mask |=
-@@ -222,7 +225,7 @@ int dpni_enable(struct fsl_mc_io *mc_io,
- 		u32 cmd_flags,
- 		u16 token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 
- 	/* prepare command */
- 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE,
-@@ -245,7 +248,7 @@ int dpni_disable(struct fsl_mc_io *mc_io
- 		 u32 cmd_flags,
- 		 u16 token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 
- 	/* prepare command */
- 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_DISABLE,
-@@ -270,7 +273,7 @@ int dpni_is_enabled(struct fsl_mc_io *mc
- 		    u16 token,
- 		    int *en)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_is_enabled *rsp_params;
- 	int err;
- 
-@@ -303,7 +306,7 @@ int dpni_reset(struct fsl_mc_io *mc_io,
- 	       u32 cmd_flags,
- 	       u16 token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 
- 	/* prepare command */
- 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET,
-@@ -335,7 +338,7 @@ int dpni_set_irq_enable(struct fsl_mc_io
- 			u8 irq_index,
- 			u8 en)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_irq_enable *cmd_params;
- 
- 	/* prepare command */
-@@ -366,7 +369,7 @@ int dpni_get_irq_enable(struct fsl_mc_io
- 			u8 irq_index,
- 			u8 *en)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_irq_enable *cmd_params;
- 	struct dpni_rsp_get_irq_enable *rsp_params;
- 
-@@ -413,7 +416,7 @@ int dpni_set_irq_mask(struct fsl_mc_io *
- 		      u8 irq_index,
- 		      u32 mask)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_irq_mask *cmd_params;
- 
- 	/* prepare command */
-@@ -447,7 +450,7 @@ int dpni_get_irq_mask(struct fsl_mc_io *
- 		      u8 irq_index,
- 		      u32 *mask)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_irq_mask *cmd_params;
- 	struct dpni_rsp_get_irq_mask *rsp_params;
- 	int err;
-@@ -489,7 +492,7 @@ int dpni_get_irq_status(struct fsl_mc_io
- 			u8 irq_index,
- 			u32 *status)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_irq_status *cmd_params;
- 	struct dpni_rsp_get_irq_status *rsp_params;
- 	int err;
-@@ -532,7 +535,7 @@ int dpni_clear_irq_status(struct fsl_mc_
- 			  u8 irq_index,
- 			  u32 status)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_clear_irq_status *cmd_params;
- 
- 	/* prepare command */
-@@ -561,7 +564,7 @@ int dpni_get_attributes(struct fsl_mc_io
- 			u16 token,
- 			struct dpni_attr *attr)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_get_attr *rsp_params;
- 
- 	int err;
-@@ -609,7 +612,7 @@ int dpni_set_errors_behavior(struct fsl_
- 			     u16 token,
- 			     struct dpni_error_cfg *cfg)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_errors_behavior *cmd_params;
- 
- 	/* prepare command */
-@@ -641,7 +644,7 @@ int dpni_get_buffer_layout(struct fsl_mc
- 			   enum dpni_queue_type qtype,
- 			   struct dpni_buffer_layout *layout)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_buffer_layout *cmd_params;
- 	struct dpni_rsp_get_buffer_layout *rsp_params;
- 	int err;
-@@ -689,7 +692,7 @@ int dpni_set_buffer_layout(struct fsl_mc
- 			   enum dpni_queue_type qtype,
- 			   const struct dpni_buffer_layout *layout)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_buffer_layout *cmd_params;
- 
- 	/* prepare command */
-@@ -731,7 +734,7 @@ int dpni_set_offload(struct fsl_mc_io *m
- 		     enum dpni_offload type,
- 		     u32 config)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_offload *cmd_params;
- 
- 	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_OFFLOAD,
-@@ -750,7 +753,7 @@ int dpni_get_offload(struct fsl_mc_io *m
- 		     enum dpni_offload type,
- 		     u32 *config)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_offload *cmd_params;
- 	struct dpni_rsp_get_offload *rsp_params;
- 	int err;
-@@ -792,7 +795,7 @@ int dpni_get_qdid(struct fsl_mc_io *mc_i
- 		  enum dpni_queue_type qtype,
- 		  u16 *qdid)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_qdid *cmd_params;
- 	struct dpni_rsp_get_qdid *rsp_params;
- 	int err;
-@@ -830,7 +833,7 @@ int dpni_get_tx_data_offset(struct fsl_m
- 			    u16 token,
- 			    u16 *data_offset)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_get_tx_data_offset *rsp_params;
- 	int err;
- 
-@@ -865,7 +868,7 @@ int dpni_set_link_cfg(struct fsl_mc_io *
- 		      u16 token,
- 		      const struct dpni_link_cfg *cfg)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_link_cfg *cmd_params;
- 
- 	/* prepare command */
-@@ -894,7 +897,7 @@ int dpni_get_link_state(struct fsl_mc_io
- 			u16 token,
- 			struct dpni_link_state *state)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_get_link_state *rsp_params;
- 	int err;
- 
-@@ -918,6 +921,44 @@ int dpni_get_link_state(struct fsl_mc_io
- }
- 
- /**
-+ * dpni_set_tx_shaping() - Set the transmit shaping
-+ * @mc_io:		Pointer to MC portal's I/O object
-+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:		Token of DPNI object
-+ * @tx_cr_shaper:	TX committed rate shaping configuration
-+ * @tx_er_shaper:	TX excess rate shaping configuration
-+ * @coupled:		Committed and excess rate shapers are coupled
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpni_set_tx_shaping(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			const struct dpni_tx_shaping_cfg *tx_cr_shaper,
-+			const struct dpni_tx_shaping_cfg *tx_er_shaper,
-+			int coupled)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpni_cmd_set_tx_shaping *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_SHAPING,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_set_tx_shaping *)cmd.params;
-+	cmd_params->tx_cr_max_burst_size =
-+				cpu_to_le16(tx_cr_shaper->max_burst_size);
-+	cmd_params->tx_er_max_burst_size =
-+				cpu_to_le16(tx_er_shaper->max_burst_size);
-+	cmd_params->tx_cr_rate_limit = cpu_to_le32(tx_cr_shaper->rate_limit);
-+	cmd_params->tx_er_rate_limit = cpu_to_le32(tx_er_shaper->rate_limit);
-+	dpni_set_field(cmd_params->coupled, COUPLED, coupled);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-  * dpni_set_max_frame_length() - Set the maximum received frame length.
-  * @mc_io:	Pointer to MC portal's I/O object
-  * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-@@ -933,7 +974,7 @@ int dpni_set_max_frame_length(struct fsl
- 			      u16 token,
- 			      u16 max_frame_length)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_max_frame_length *cmd_params;
- 
- 	/* prepare command */
-@@ -963,7 +1004,7 @@ int dpni_get_max_frame_length(struct fsl
- 			      u16 token,
- 			      u16 *max_frame_length)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_get_max_frame_length *rsp_params;
- 	int err;
- 
-@@ -998,7 +1039,7 @@ int dpni_set_multicast_promisc(struct fs
- 			       u16 token,
- 			       int en)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_multicast_promisc *cmd_params;
- 
- 	/* prepare command */
-@@ -1026,7 +1067,7 @@ int dpni_get_multicast_promisc(struct fs
- 			       u16 token,
- 			       int *en)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_get_multicast_promisc *rsp_params;
- 	int err;
- 
-@@ -1061,7 +1102,7 @@ int dpni_set_unicast_promisc(struct fsl_
- 			     u16 token,
- 			     int en)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_unicast_promisc *cmd_params;
- 
- 	/* prepare command */
-@@ -1089,7 +1130,7 @@ int dpni_get_unicast_promisc(struct fsl_
- 			     u16 token,
- 			     int *en)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_get_unicast_promisc *rsp_params;
- 	int err;
- 
-@@ -1124,7 +1165,7 @@ int dpni_set_primary_mac_addr(struct fsl
- 			      u16 token,
- 			      const u8 mac_addr[6])
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_primary_mac_addr *cmd_params;
- 	int i;
- 
-@@ -1154,7 +1195,7 @@ int dpni_get_primary_mac_addr(struct fsl
- 			      u16 token,
- 			      u8 mac_addr[6])
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_get_primary_mac_addr *rsp_params;
- 	int i, err;
- 
-@@ -1193,7 +1234,7 @@ int dpni_get_port_mac_addr(struct fsl_mc
- 			   u16 token,
- 			   u8 mac_addr[6])
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_rsp_get_port_mac_addr *rsp_params;
- 	int i, err;
- 
-@@ -1229,7 +1270,7 @@ int dpni_add_mac_addr(struct fsl_mc_io *
- 		      u16 token,
- 		      const u8 mac_addr[6])
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_add_mac_addr *cmd_params;
- 	int i;
- 
-@@ -1259,7 +1300,7 @@ int dpni_remove_mac_addr(struct fsl_mc_i
- 			 u16 token,
- 			 const u8 mac_addr[6])
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_remove_mac_addr *cmd_params;
- 	int i;
- 
-@@ -1293,7 +1334,7 @@ int dpni_clear_mac_filters(struct fsl_mc
- 			   int unicast,
- 			   int multicast)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_clear_mac_filters *cmd_params;
- 
- 	/* prepare command */
-@@ -1309,6 +1350,55 @@ int dpni_clear_mac_filters(struct fsl_mc
- }
- 
- /**
-+ * dpni_set_tx_priorities() - Set transmission TC priority configuration
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @cfg:	Transmission selection configuration
-+ *
-+ * warning:	Allowed only when DPNI is disabled
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpni_set_tx_priorities(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   const struct dpni_tx_priorities_cfg *cfg)
-+{
-+	struct dpni_cmd_set_tx_priorities *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int i;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_PRIORITIES,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_set_tx_priorities *)cmd.params;
-+	dpni_set_field(cmd_params->flags,
-+		       SEPARATE_GRP,
-+		       cfg->separate_groups);
-+	cmd_params->prio_group_A = cfg->prio_group_A;
-+	cmd_params->prio_group_B = cfg->prio_group_B;
-+
-+	for (i = 0; i + 1 < DPNI_MAX_TC; i += 2) {
-+		dpni_set_field(cmd_params->modes[i / 2],
-+			       MODE_1,
-+			       cfg->tc_sched[i].mode);
-+		dpni_set_field(cmd_params->modes[i / 2],
-+			       MODE_2,
-+			       cfg->tc_sched[i + 1].mode);
-+	}
-+
-+	for (i = 0; i < DPNI_MAX_TC; i++) {
-+		cmd_params->delta_bandwidth[i] =
-+				cpu_to_le16(cfg->tc_sched[i].delta_bandwidth);
-+	}
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-  * dpni_set_rx_tc_dist() - Set Rx traffic class distribution configuration
-  * @mc_io:	Pointer to MC portal's I/O object
-  * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-@@ -1327,7 +1417,7 @@ int dpni_set_rx_tc_dist(struct fsl_mc_io
- 			u8 tc_id,
- 			const struct dpni_rx_tc_dist_cfg *cfg)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_rx_tc_dist *cmd_params;
- 
- 	/* prepare command */
-@@ -1346,6 +1436,293 @@ int dpni_set_rx_tc_dist(struct fsl_mc_io
- 	return mc_send_command(mc_io, &cmd);
- }
- 
-+/*
-+ * dpni_set_qos_table() - Set QoS mapping table
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @cfg:	QoS table configuration
-+ *
-+ * This function and all QoS-related functions require that
-+ *'max_tcs > 1' was set at DPNI creation.
-+ *
-+ * warning: Before calling this function, call dpkg_prepare_key_cfg() to
-+ *			prepare the key_cfg_iova parameter
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpni_set_qos_table(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       const struct dpni_qos_tbl_cfg *cfg)
-+{
-+	struct dpni_cmd_set_qos_table *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QOS_TBL,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_set_qos_table *)cmd.params;
-+	cmd_params->default_tc = cfg->default_tc;
-+	cmd_params->key_cfg_iova = cpu_to_le64(cfg->key_cfg_iova);
-+	dpni_set_field(cmd_params->discard_on_miss,
-+		       ENABLE,
-+		       cfg->discard_on_miss);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpni_add_qos_entry() - Add QoS mapping entry (to select a traffic class)
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @cfg:	QoS rule to add
-+ * @tc_id:	Traffic class selection (0-7)
-+ * @index:	Location in the QoS table where to insert the entry.
-+ *		Only relevant if MASKING is enabled for QoS classification on
-+ *		this DPNI, it is ignored for exact match.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpni_add_qos_entry(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       const struct dpni_rule_cfg *cfg,
-+		       u8 tc_id,
-+		       u16 index)
-+{
-+	struct dpni_cmd_add_qos_entry *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_QOS_ENT,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_add_qos_entry *)cmd.params;
-+	cmd_params->tc_id = tc_id;
-+	cmd_params->key_size = cfg->key_size;
-+	cmd_params->index = cpu_to_le16(index);
-+	cmd_params->key_iova = cpu_to_le64(cfg->key_iova);
-+	cmd_params->mask_iova = cpu_to_le64(cfg->mask_iova);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpni_remove_qos_entry() - Remove QoS mapping entry
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @cfg:	QoS rule to remove
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpni_remove_qos_entry(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  const struct dpni_rule_cfg *cfg)
-+{
-+	struct dpni_cmd_remove_qos_entry *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_QOS_ENT,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_remove_qos_entry *)cmd.params;
-+	cmd_params->key_size = cfg->key_size;
-+	cmd_params->key_iova = cpu_to_le64(cfg->key_iova);
-+	cmd_params->mask_iova = cpu_to_le64(cfg->mask_iova);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpni_add_fs_entry() - Add Flow Steering entry for a specific traffic class
-+ *			(to select a flow ID)
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @tc_id:	Traffic class selection (0-7)
-+ * @index:	Location in the QoS table where to insert the entry.
-+ *		Only relevant if MASKING is enabled for QoS
-+ *		classification on this DPNI, it is ignored for exact match.
-+ * @cfg:	Flow steering rule to add
-+ * @action:	Action to be taken as result of a classification hit
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpni_add_fs_entry(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      u8 tc_id,
-+		      u16 index,
-+		      const struct dpni_rule_cfg *cfg,
-+		      const struct dpni_fs_action_cfg *action)
-+{
-+	struct dpni_cmd_add_fs_entry *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_FS_ENT,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_add_fs_entry *)cmd.params;
-+	cmd_params->tc_id = tc_id;
-+	cmd_params->key_size = cfg->key_size;
-+	cmd_params->index = cpu_to_le16(index);
-+	cmd_params->key_iova = cpu_to_le64(cfg->key_iova);
-+	cmd_params->mask_iova = cpu_to_le64(cfg->mask_iova);
-+	cmd_params->options = cpu_to_le16(action->options);
-+	cmd_params->flow_id = cpu_to_le16(action->flow_id);
-+	cmd_params->flc = cpu_to_le64(action->flc);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpni_remove_fs_entry() - Remove Flow Steering entry from a specific
-+ *			    traffic class
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @tc_id:	Traffic class selection (0-7)
-+ * @cfg:	Flow steering rule to remove
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpni_remove_fs_entry(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u8 tc_id,
-+			 const struct dpni_rule_cfg *cfg)
-+{
-+	struct dpni_cmd_remove_fs_entry *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_FS_ENT,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_remove_fs_entry *)cmd.params;
-+	cmd_params->tc_id = tc_id;
-+	cmd_params->key_size = cfg->key_size;
-+	cmd_params->key_iova = cpu_to_le64(cfg->key_iova);
-+	cmd_params->mask_iova = cpu_to_le64(cfg->mask_iova);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpni_set_congestion_notification() - Set traffic class congestion
-+ *					notification configuration
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @qtype:	Type of queue - Rx, Tx and Tx confirm types are supported
-+ * @tc_id:	Traffic class selection (0-7)
-+ * @cfg:	Congestion notification configuration
-+ *
-+ * Return:	'0' on Success; error code otherwise.
-+ */
-+int dpni_set_congestion_notification(
-+			struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			enum dpni_queue_type qtype,
-+			u8 tc_id,
-+			const struct dpni_congestion_notification_cfg *cfg)
-+{
-+	struct dpni_cmd_set_congestion_notification *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(
-+			DPNI_CMDID_SET_CONGESTION_NOTIFICATION,
-+			cmd_flags,
-+			token);
-+	cmd_params = (struct dpni_cmd_set_congestion_notification *)cmd.params;
-+	cmd_params->qtype = qtype;
-+	cmd_params->tc = tc_id;
-+	cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
-+	cmd_params->notification_mode = cpu_to_le16(cfg->notification_mode);
-+	cmd_params->dest_priority = cfg->dest_cfg.priority;
-+	dpni_set_field(cmd_params->type_units, DEST_TYPE,
-+		       cfg->dest_cfg.dest_type);
-+	dpni_set_field(cmd_params->type_units, CONG_UNITS, cfg->units);
-+	cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
-+	cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
-+	cmd_params->threshold_entry = cpu_to_le32(cfg->threshold_entry);
-+	cmd_params->threshold_exit = cpu_to_le32(cfg->threshold_exit);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpni_get_congestion_notification() - Get traffic class congestion
-+ *	notification configuration
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @qtype:	Type of queue - Rx, Tx and Tx confirm types are supported
-+ * @tc_id:	bits 7-4 contain ceetm channel index (valid only for TX);
-+ *		bits 3-0 contain traffic class.
-+ *		Use macro DPNI_BUILD_CH_TC() to build correct value for
-+ *		tc_id parameter.
-+ * @cfg:	congestion notification configuration
-+ *
-+ * Return:	'0' on Success; error code otherwise.
-+ */
-+int dpni_get_congestion_notification(
-+			struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			enum dpni_queue_type qtype,
-+			u8 tc_id,
-+			struct dpni_congestion_notification_cfg *cfg)
-+{
-+	struct dpni_rsp_get_congestion_notification *rsp_params;
-+	struct dpni_cmd_get_congestion_notification *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(
-+				DPNI_CMDID_GET_CONGESTION_NOTIFICATION,
-+				cmd_flags,
-+				token);
-+	cmd_params = (struct dpni_cmd_get_congestion_notification *)cmd.params;
-+	cmd_params->qtype = qtype;
-+	cmd_params->tc = tc_id;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpni_rsp_get_congestion_notification *)cmd.params;
-+	cfg->units = dpni_get_field(rsp_params->type_units, CONG_UNITS);
-+	cfg->threshold_entry = le32_to_cpu(rsp_params->threshold_entry);
-+	cfg->threshold_exit = le32_to_cpu(rsp_params->threshold_exit);
-+	cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
-+	cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
-+	cfg->notification_mode = le16_to_cpu(rsp_params->notification_mode);
-+	cfg->dest_cfg.dest_id = le32_to_cpu(rsp_params->dest_id);
-+	cfg->dest_cfg.priority = rsp_params->dest_priority;
-+	cfg->dest_cfg.dest_type = dpni_get_field(rsp_params->type_units,
-+						 DEST_TYPE);
-+
-+	return 0;
-+}
-+
- /**
-  * dpni_set_queue() - Set queue parameters
-  * @mc_io:	Pointer to MC portal's I/O object
-@@ -1371,7 +1748,7 @@ int dpni_set_queue(struct fsl_mc_io *mc_
- 		   u8 options,
- 		   const struct dpni_queue *queue)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_queue *cmd_params;
- 
- 	/* prepare command */
-@@ -1419,7 +1796,7 @@ int dpni_get_queue(struct fsl_mc_io *mc_
- 		   struct dpni_queue *queue,
- 		   struct dpni_queue_id *qid)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_queue *cmd_params;
- 	struct dpni_rsp_get_queue *rsp_params;
- 	int err;
-@@ -1463,6 +1840,8 @@ int dpni_get_queue(struct fsl_mc_io *mc_
-  * @token:	Token of DPNI object
-  * @page:	Selects the statistics page to retrieve, see
-  *		DPNI_GET_STATISTICS output. Pages are numbered 0 to 2.
-+ * @param:	Custom parameter for some pages used to select a certain
-+ *		statistic source, for example the TC.
-  * @stat:	Structure containing the statistics
-  *
-  * Return:	'0' on Success; Error code otherwise.
-@@ -1471,9 +1850,10 @@ int dpni_get_statistics(struct fsl_mc_io
- 			u32 cmd_flags,
- 			u16 token,
- 			u8 page,
-+			u8 param,
- 			union dpni_statistics *stat)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_statistics *cmd_params;
- 	struct dpni_rsp_get_statistics *rsp_params;
- 	int i, err;
-@@ -1484,6 +1864,7 @@ int dpni_get_statistics(struct fsl_mc_io
- 					  token);
- 	cmd_params = (struct dpni_cmd_get_statistics *)cmd.params;
- 	cmd_params->page_number = page;
-+	cmd_params->param = param;
- 
- 	/* send command to mc */
- 	err = mc_send_command(mc_io, &cmd);
-@@ -1499,6 +1880,29 @@ int dpni_get_statistics(struct fsl_mc_io
- }
- 
- /**
-+ * dpni_reset_statistics() - Clears DPNI statistics
-+ * @mc_io:		Pointer to MC portal's I/O object
-+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:		Token of DPNI object
-+ *
-+ * Return:  '0' on Success; Error code otherwise.
-+ */
-+int dpni_reset_statistics(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET_STATISTICS,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-  * dpni_set_taildrop() - Set taildrop per queue or TC
-  * @mc_io:	Pointer to MC portal's I/O object
-  * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-@@ -1506,7 +1910,10 @@ int dpni_get_statistics(struct fsl_mc_io
-  * @cg_point:	Congestion point
-  * @q_type:	Queue type on which the taildrop is configured.
-  *		Only Rx queues are supported for now
-- * @tc:		Traffic class to apply this taildrop to
-+ * @tc:		bits 7-4 contain ceetm channel index (valid only for TX);
-+ *		bits 3-0 contain traffic class.
-+ *		Use macro DPNI_BUILD_CH_TC() to build correct value for
-+ *		tc parameter.
-  * @q_index:	Index of the queue if the DPNI supports multiple queues for
-  *		traffic distribution. Ignored if CONGESTION_POINT is not 0.
-  * @taildrop:	Taildrop structure
-@@ -1522,7 +1929,7 @@ int dpni_set_taildrop(struct fsl_mc_io *
- 		      u8 index,
- 		      struct dpni_taildrop *taildrop)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_set_taildrop *cmd_params;
- 
- 	/* prepare command */
-@@ -1550,7 +1957,10 @@ int dpni_set_taildrop(struct fsl_mc_io *
-  * @cg_point:	Congestion point
-  * @q_type:	Queue type on which the taildrop is configured.
-  *		Only Rx queues are supported for now
-- * @tc:		Traffic class to apply this taildrop to
-+ * @tc:		bits 7-4 contain ceetm channel index (valid only for TX);
-+ *		bits 3-0 contain traffic class.
-+ *		Use macro DPNI_BUILD_CH_TC() to build correct value for
-+ *		tc parameter.
-  * @q_index:	Index of the queue if the DPNI supports multiple queues for
-  *		traffic distribution. Ignored if CONGESTION_POINT is not 0.
-  * @taildrop:	Taildrop structure
-@@ -1566,7 +1976,7 @@ int dpni_get_taildrop(struct fsl_mc_io *
- 		      u8 index,
- 		      struct dpni_taildrop *taildrop)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpni_cmd_get_taildrop *cmd_params;
- 	struct dpni_rsp_get_taildrop *rsp_params;
- 	int err;
-@@ -1594,3 +2004,109 @@ int dpni_get_taildrop(struct fsl_mc_io *
- 
- 	return 0;
- }
-+
-+/**
-+ * dpni_get_api_version() - Get Data Path Network Interface API version
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @major_ver:	Major version of data path network interface API
-+ * @minor_ver:	Minor version of data path network interface API
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpni_get_api_version(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 *major_ver,
-+			 u16 *minor_ver)
-+{
-+	struct dpni_rsp_get_api_version *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION,
-+					  cmd_flags, 0);
-+
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpni_rsp_get_api_version *)cmd.params;
-+	*major_ver = le16_to_cpu(rsp_params->major);
-+	*minor_ver = le16_to_cpu(rsp_params->minor);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpni_set_rx_fs_dist() - Set Rx traffic class FS distribution
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @cfg: Distribution configuration
-+ * If the FS is already enabled with a previous call the classification
-+ * key will be changed but all the table rules are kept. If the
-+ * existing rules do not match the key the results will not be
-+ * predictable. It is the user responsibility to keep key integrity.
-+ * If cfg.enable is set to 1 the command will create a flow steering table
-+ * and will classify packets according to this table. The packets that
-+ * miss all the table rules will be classified according to settings
-+ * made in dpni_set_rx_hash_dist()
-+ * If cfg.enable is set to 0 the command will clear flow steering table.
-+ * The packets will be classified according to settings made in
-+ * dpni_set_rx_hash_dist()
-+ */
-+int dpni_set_rx_fs_dist(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			const struct dpni_rx_dist_cfg *cfg)
-+{
-+	struct dpni_cmd_set_rx_fs_dist *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_FS_DIST,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_set_rx_fs_dist *)cmd.params;
-+	cmd_params->dist_size = le16_to_cpu(cfg->dist_size);
-+	dpni_set_field(cmd_params->enable, RX_FS_DIST_ENABLE, cfg->enable);
-+	cmd_params->tc = cfg->tc;
-+	cmd_params->miss_flow_id = le16_to_cpu(cfg->fs_miss_flow_id);
-+	cmd_params->key_cfg_iova = le64_to_cpu(cfg->key_cfg_iova);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpni_set_rx_hash_dist() - Set Rx traffic class HASH distribution
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPNI object
-+ * @cfg: Distribution configuration
-+ * If cfg.enable is set to 1 the packets will be classified using a hash
-+ * function based on the key received in cfg.key_cfg_iova parameter.
-+ * If cfg.enable is set to 0 the packets will be sent to the queue configured
-+ * in dpni_set_rx_dist_default_queue() call
-+ */
-+int dpni_set_rx_hash_dist(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  const struct dpni_rx_dist_cfg *cfg)
-+{
-+	struct dpni_cmd_set_rx_hash_dist *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_HASH_DIST,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpni_cmd_set_rx_hash_dist *)cmd.params;
-+	cmd_params->dist_size = le16_to_cpu(cfg->dist_size);
-+	dpni_set_field(cmd_params->enable, RX_FS_DIST_ENABLE, cfg->enable);
-+	cmd_params->tc = cfg->tc;
-+	cmd_params->key_cfg_iova = le64_to_cpu(cfg->key_cfg_iova);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
---- a/drivers/staging/fsl-dpaa2/ethernet/dpni.h
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.h
-@@ -52,6 +52,14 @@ struct fsl_mc_io;
-  * Maximum number of buffer pools per DPNI
-  */
- #define DPNI_MAX_DPBP				8
-+/**
-+ * Maximum number of senders
-+ */
-+#define DPNI_MAX_SENDERS			16
-+/**
-+ * Maximum distribution size
-+ */
-+#define DPNI_MAX_DIST_SIZE			16
- 
- /**
-  * All traffic classes considered; see dpni_set_queue()
-@@ -123,13 +131,15 @@ struct dpni_pools_cfg {
- 	/**
- 	 * struct pools - Buffer pools parameters
- 	 * @dpbp_id: DPBP object ID
-+	 * @priority_mask: priorities served by DPBP
- 	 * @buffer_size: Buffer size
- 	 * @backup_pool: Backup pool
- 	 */
- 	struct {
--		int	dpbp_id;
-+		u16	dpbp_id;
-+		u8	priority_mask;
- 		u16	buffer_size;
--		int	backup_pool;
-+		u8	backup_pool;
- 	} pools[DPNI_MAX_DPBP];
- };
- 
-@@ -476,6 +486,24 @@ union dpni_statistics {
- 		u64 egress_confirmed_frames;
- 	} page_2;
- 	/**
-+	 * struct page_3 - Page_3 statistics structure with values for the
-+	 *		   selected TC
-+	 * @ceetm_dequeue_bytes: Cumulative count of the number of bytes
-+	 *			 dequeued
-+	 * @ceetm_dequeue_frames: Cumulative count of the number of frames
-+	 *			  dequeued
-+	 * @ceetm_reject_bytes: Cumulative count of the number of bytes in all
-+	 *			frames whose enqueue was rejected
-+	 * @ceetm_reject_frames: Cumulative count of all frame enqueues
-+	 *			 rejected
-+	 */
-+	struct {
-+		u64 ceetm_dequeue_bytes;
-+		u64 ceetm_dequeue_frames;
-+		u64 ceetm_reject_bytes;
-+		u64 ceetm_reject_frames;
-+	} page_3;
-+	/**
- 	 * struct raw - raw statistics structure
- 	 */
- 	struct {
-@@ -487,8 +515,13 @@ int dpni_get_statistics(struct fsl_mc_io
- 			u32			cmd_flags,
- 			u16			token,
- 			u8			page,
-+			u8			param,
- 			union dpni_statistics	*stat);
- 
-+int dpni_reset_statistics(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token);
-+
- /**
-  * Enable auto-negotiation
-  */
-@@ -505,6 +538,10 @@ int dpni_get_statistics(struct fsl_mc_io
-  * Enable a-symmetric pause frames
-  */
- #define DPNI_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
-+/**
-+ * Enable priority flow control pause frames
-+ */
-+#define DPNI_LINK_OPT_PFC_PAUSE		0x0000000000000010ULL
- 
- /**
-  * struct - Structure representing DPNI link configuration
-@@ -538,6 +575,23 @@ int dpni_get_link_state(struct fsl_mc_io
- 			u16			token,
- 			struct dpni_link_state	*state);
- 
-+/**
-+ * struct dpni_tx_shaping - Structure representing DPNI tx shaping configuration
-+ * @rate_limit: rate in Mbps
-+ * @max_burst_size: burst size in bytes (up to 64KB)
-+ */
-+struct dpni_tx_shaping_cfg {
-+	u32	rate_limit;
-+	u16	max_burst_size;
-+};
-+
-+int dpni_set_tx_shaping(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			const struct dpni_tx_shaping_cfg *tx_cr_shaper,
-+			const struct dpni_tx_shaping_cfg *tx_er_shaper,
-+			int coupled);
-+
- int dpni_set_max_frame_length(struct fsl_mc_io	*mc_io,
- 			      u32		cmd_flags,
- 			      u16		token,
-@@ -639,6 +693,70 @@ int dpni_prepare_key_cfg(const struct dp
- 			 u8 *key_cfg_buf);
- 
- /**
-+ * struct dpni_qos_tbl_cfg - Structure representing QOS table configuration
-+ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with
-+ *		key extractions to be used as the QoS criteria by calling
-+ *		dpkg_prepare_key_cfg()
-+ * @discard_on_miss: Set to '1' to discard frames in case of no match (miss);
-+ *		'0' to use the 'default_tc' in such cases
-+ * @default_tc: Used in case of no-match and 'discard_on_miss'= 0
-+ */
-+struct dpni_qos_tbl_cfg {
-+	u64 key_cfg_iova;
-+	int discard_on_miss;
-+	u8 default_tc;
-+};
-+
-+int dpni_set_qos_table(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       const struct dpni_qos_tbl_cfg *cfg);
-+
-+/**
-+ * enum dpni_tx_schedule_mode - DPNI Tx scheduling mode
-+ * @DPNI_TX_SCHED_STRICT_PRIORITY: strict priority
-+ * @DPNI_TX_SCHED_WEIGHTED_A: weighted based scheduling in group A
-+ * @DPNI_TX_SCHED_WEIGHTED_B: weighted based scheduling in group B
-+ */
-+enum dpni_tx_schedule_mode {
-+	DPNI_TX_SCHED_STRICT_PRIORITY = 0,
-+	DPNI_TX_SCHED_WEIGHTED_A,
-+	DPNI_TX_SCHED_WEIGHTED_B,
-+};
-+
-+/**
-+ * struct dpni_tx_schedule_cfg - Structure representing Tx scheduling conf
-+ * @mode:		Scheduling mode
-+ * @delta_bandwidth:	Bandwidth represented in weights from 100 to 10000;
-+ *	not applicable for 'strict-priority' mode;
-+ */
-+struct dpni_tx_schedule_cfg {
-+	enum dpni_tx_schedule_mode mode;
-+	u16 delta_bandwidth;
-+};
-+
-+/**
-+ * struct dpni_tx_priorities_cfg - Structure representing transmission
-+ *					priorities for DPNI TCs
-+ * @tc_sched:	An array of traffic-classes
-+ * @prio_group_A: Priority of group A
-+ * @prio_group_B: Priority of group B
-+ * @separate_groups: Treat A and B groups as separate
-+ * @ceetm_ch_idx: ceetm channel index to apply the changes
-+ */
-+struct dpni_tx_priorities_cfg {
-+	struct dpni_tx_schedule_cfg tc_sched[DPNI_MAX_TC];
-+	u8 prio_group_A;
-+	u8 prio_group_B;
-+	u8 separate_groups;
-+};
-+
-+int dpni_set_tx_priorities(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   const struct dpni_tx_priorities_cfg *cfg);
-+
-+/**
-  * struct dpni_rx_tc_dist_cfg - Rx traffic class distribution configuration
-  * @dist_size: Set the distribution size;
-  *	supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,
-@@ -784,6 +902,108 @@ enum dpni_congestion_point {
- };
- 
- /**
-+ * struct dpni_dest_cfg - Structure representing DPNI destination parameters
-+ * @dest_type:	Destination type
-+ * @dest_id:	Either DPIO ID or DPCON ID, depending on the destination type
-+ * @priority:	Priority selection within the DPIO or DPCON channel; valid
-+ *		values are 0-1 or 0-7, depending on the number of priorities
-+ *		in that channel; not relevant for 'DPNI_DEST_NONE' option
-+ */
-+struct dpni_dest_cfg {
-+	enum dpni_dest dest_type;
-+	int dest_id;
-+	u8 priority;
-+};
-+
-+/* DPNI congestion options */
-+
-+/**
-+ * CSCN message is written to message_iova once entering a
-+ * congestion state (see 'threshold_entry')
-+ */
-+#define DPNI_CONG_OPT_WRITE_MEM_ON_ENTER        0x00000001
-+/**
-+ * CSCN message is written to message_iova once exiting a
-+ * congestion state (see 'threshold_exit')
-+ */
-+#define DPNI_CONG_OPT_WRITE_MEM_ON_EXIT         0x00000002
-+/**
-+ * CSCN write will attempt to allocate into a cache (coherent write);
-+ * valid only if 'DPNI_CONG_OPT_WRITE_MEM_<X>' is selected
-+ */
-+#define DPNI_CONG_OPT_COHERENT_WRITE            0x00000004
-+/**
-+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' CSCN message is sent to
-+ * DPIO/DPCON's WQ channel once entering a congestion state
-+ * (see 'threshold_entry')
-+ */
-+#define DPNI_CONG_OPT_NOTIFY_DEST_ON_ENTER      0x00000008
-+/**
-+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' CSCN message is sent to
-+ * DPIO/DPCON's WQ channel once exiting a congestion state
-+ * (see 'threshold_exit')
-+ */
-+#define DPNI_CONG_OPT_NOTIFY_DEST_ON_EXIT       0x00000010
-+/**
-+ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' when the CSCN is written to the
-+ * sw-portal's DQRR, the DQRI interrupt is asserted immediately (if enabled)
-+ */
-+#define DPNI_CONG_OPT_INTR_COALESCING_DISABLED  0x00000020
-+/**
-+ * This congestion will trigger flow control or priority flow control.
-+ * This will have effect only if flow control is enabled with
-+ * dpni_set_link_cfg().
-+ */
-+#define DPNI_CONG_OPT_FLOW_CONTROL	0x00000040
-+
-+/**
-+ * struct dpni_congestion_notification_cfg - congestion notification
-+ *					configuration
-+ * @units: Units type
-+ * @threshold_entry: Above this threshold we enter a congestion state.
-+ *		set it to '0' to disable it
-+ * @threshold_exit: Below this threshold we exit the congestion state.
-+ * @message_ctx: The context that will be part of the CSCN message
-+ * @message_iova: I/O virtual address (must be in DMA-able memory),
-+ *		must be 16B aligned; valid only if 'DPNI_CONG_OPT_WRITE_MEM_<X>'
-+ *		is contained in 'options'
-+ * @dest_cfg: CSCN can be send to either DPIO or DPCON WQ channel
-+ * @notification_mode: Mask of available options; use 'DPNI_CONG_OPT_<X>' values
-+ */
-+
-+struct dpni_congestion_notification_cfg {
-+	enum dpni_congestion_unit units;
-+	u32 threshold_entry;
-+	u32 threshold_exit;
-+	u64 message_ctx;
-+	u64 message_iova;
-+	struct dpni_dest_cfg dest_cfg;
-+	u16 notification_mode;
-+};
-+
-+/** Compose TC parameter for function dpni_set_congestion_notification()
-+ * and dpni_get_congestion_notification().
-+ */
-+#define DPNI_BUILD_CH_TC(ceetm_ch_idx, tc) \
-+	((((ceetm_ch_idx) & 0x0F) << 4) | ((tc) & 0x0F))
-+
-+int dpni_set_congestion_notification(
-+			struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			enum dpni_queue_type qtype,
-+			u8 tc_id,
-+			const struct dpni_congestion_notification_cfg *cfg);
-+
-+int dpni_get_congestion_notification(
-+			struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			enum dpni_queue_type qtype,
-+			u8 tc_id,
-+			struct dpni_congestion_notification_cfg *cfg);
-+
-+/**
-  * struct dpni_taildrop - Structure representing the taildrop
-  * @enable:	Indicates whether the taildrop is active or not.
-  * @units:	Indicates the unit of THRESHOLD. Queue taildrop only supports
-@@ -829,4 +1049,124 @@ struct dpni_rule_cfg {
- 	u8	key_size;
- };
- 
-+int dpni_get_api_version(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 *major_ver,
-+			 u16 *minor_ver);
-+
-+int dpni_add_qos_entry(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       const struct dpni_rule_cfg *cfg,
-+		       u8 tc_id,
-+		       u16 index);
-+
-+int dpni_remove_qos_entry(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  const struct dpni_rule_cfg *cfg);
-+
-+int dpni_clear_qos_table(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token);
-+
-+/**
-+ * Discard matching traffic. If set, this takes precedence over any other
-+ * configuration and matching traffic is always discarded.
-+ */
-+ #define DPNI_FS_OPT_DISCARD            0x1
-+
-+/**
-+ * Set FLC value. If set, flc member of struct dpni_fs_action_cfg is used to
-+ * override the FLC value set per queue.
-+ * For more details check the Frame Descriptor section in the hardware
-+ * documentation.
-+ */
-+#define DPNI_FS_OPT_SET_FLC            0x2
-+
-+/*
-+ * Indicates whether the 6 lowest significant bits of FLC are used for stash
-+ * control. If set, the 6 least significant bits in value are interpreted as
-+ * follows:
-+ *     - bits 0-1: indicates the number of 64 byte units of context that are
-+ *     stashed. FLC value is interpreted as a memory address in this case,
-+ *     excluding the 6 LS bits.
-+ *     - bits 2-3: indicates the number of 64 byte units of frame annotation
-+ *     to be stashed. Annotation is placed at FD[ADDR].
-+ *     - bits 4-5: indicates the number of 64 byte units of frame data to be
-+ *     stashed. Frame data is placed at FD[ADDR] + FD[OFFSET].
-+ * This flag is ignored if DPNI_FS_OPT_SET_FLC is not specified.
-+ */
-+#define DPNI_FS_OPT_SET_STASH_CONTROL  0x4
-+
-+/**
-+ * struct dpni_fs_action_cfg - Action configuration for table look-up
-+ * @flc:	FLC value for traffic matching this rule. Please check the
-+ *		Frame Descriptor section in the hardware documentation for
-+ *		more information.
-+ * @flow_id:	Identifies the Rx queue used for matching traffic. Supported
-+ *		values are in range 0 to num_queue-1.
-+ * @options:	Any combination of DPNI_FS_OPT_ values.
-+ */
-+struct dpni_fs_action_cfg {
-+	u64 flc;
-+	u16 flow_id;
-+	u16 options;
-+};
-+
-+int dpni_add_fs_entry(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      u8 tc_id,
-+		      u16 index,
-+		      const struct dpni_rule_cfg *cfg,
-+		      const struct dpni_fs_action_cfg *action);
-+
-+int dpni_remove_fs_entry(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u8 tc_id,
-+			 const struct dpni_rule_cfg *cfg);
-+
-+/**
-+ * When used for queue_idx in function dpni_set_rx_dist_default_queue
-+ * will signal to dpni to drop all unclassified frames
-+ */
-+#define DPNI_FS_MISS_DROP		((uint16_t)-1)
-+
-+/**
-+ * struct dpni_rx_dist_cfg - distribution configuration
-+ * @dist_size:	distribution size; supported values: 1,2,3,4,6,7,8,
-+ *		12,14,16,24,28,32,48,56,64,96,112,128,192,224,256,384,448,
-+ *		512,768,896,1024
-+ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with
-+ *		the extractions to be used for the distribution key by calling
-+ *		dpkg_prepare_key_cfg() relevant only when enable!=0 otherwise
-+ *		it can be '0'
-+ * @enable: enable/disable the distribution.
-+ * @tc: TC id for which distribution is set
-+ * @fs_miss_flow_id: when packet misses all rules from flow steering table and
-+ *		hash is disabled it will be put into this queue id; use
-+ *		DPNI_FS_MISS_DROP to drop frames. The value of this field is
-+ *		used only when flow steering distribution is enabled and hash
-+ *		distribution is disabled
-+ */
-+struct dpni_rx_dist_cfg {
-+	u16 dist_size;
-+	u64 key_cfg_iova;
-+	u8 enable;
-+	u8 tc;
-+	u16 fs_miss_flow_id;
-+};
-+
-+int dpni_set_rx_fs_dist(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			const struct dpni_rx_dist_cfg *cfg);
-+
-+int dpni_set_rx_hash_dist(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  const struct dpni_rx_dist_cfg *cfg);
-+
- #endif /* __FSL_DPNI_H */
diff --git a/target/linux/layerscape/patches-4.14/703-dpaa2-l2switch-support-layerscape.patch b/target/linux/layerscape/patches-4.14/703-dpaa2-l2switch-support-layerscape.patch
deleted file mode 100644
index ae91fc363..000000000
--- a/target/linux/layerscape/patches-4.14/703-dpaa2-l2switch-support-layerscape.patch
+++ /dev/null
@@ -1,4040 +0,0 @@
-From bdb1d42c9398eb14e997e026bd46602543a7ed03 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:16 +0800
-Subject: [PATCH 09/40] dpaa2-l2switch: support layerscape
-This is an integrated patch of dpaa2-l2switch for
- layerscape
-
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
-Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
-Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/staging/fsl-dpaa2/ethsw/Makefile      |   10 +
- drivers/staging/fsl-dpaa2/ethsw/README        |  106 ++
- drivers/staging/fsl-dpaa2/ethsw/TODO          |   14 +
- drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h    |  359 ++++
- drivers/staging/fsl-dpaa2/ethsw/dpsw.c        | 1165 +++++++++++++
- drivers/staging/fsl-dpaa2/ethsw/dpsw.h        |  592 +++++++
- .../staging/fsl-dpaa2/ethsw/ethsw-ethtool.c   |  206 +++
- drivers/staging/fsl-dpaa2/ethsw/ethsw.c       | 1438 +++++++++++++++++
- drivers/staging/fsl-dpaa2/ethsw/ethsw.h       |   90 ++
- 9 files changed, 3980 insertions(+)
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/Makefile
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/README
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/TODO
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw.c
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw.h
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/ethsw.c
- create mode 100644 drivers/staging/fsl-dpaa2/ethsw/ethsw.h
-
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/Makefile
-@@ -0,0 +1,10 @@
-+# SPDX-License-Identifier: GPL-2.0
-+#
-+# Makefile for the Freescale DPAA2 Ethernet Switch
-+#
-+# Copyright 2014-2017 Freescale Semiconductor, Inc.
-+# Copyright 2017-2018 NXP
-+
-+obj-$(CONFIG_FSL_DPAA2_ETHSW) += dpaa2-ethsw.o
-+
-+dpaa2-ethsw-objs := ethsw.o ethsw-ethtool.o dpsw.o
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/README
-@@ -0,0 +1,106 @@
-+DPAA2 Ethernet Switch driver
-+============================
-+
-+This file provides documentation for the DPAA2 Ethernet Switch driver
-+
-+
-+Contents
-+========
-+	Supported Platforms
-+	Architecture Overview
-+	Creating an Ethernet Switch
-+	Features
-+
-+
-+	Supported Platforms
-+===================
-+This driver provides networking support for Freescale LS2085A, LS2088A
-+DPAA2 SoCs.
-+
-+
-+Architecture Overview
-+=====================
-+The Ethernet Switch in the DPAA2 architecture consists of several hardware
-+resources that provide the functionality. These are allocated and
-+configured via the Management Complex (MC) portals. MC abstracts most of
-+these resources as DPAA2 objects and exposes ABIs through which they can
-+be configured and controlled.
-+
-+For a more detailed description of the DPAA2 architecture and its object
-+abstractions see:
-+	drivers/staging/fsl-mc/README.txt
-+
-+The Ethernet Switch is built on top of a Datapath Switch (DPSW) object.
-+
-+Configuration interface:
-+
-+          ---------------------
-+         | DPAA2 Switch driver |
-+          ---------------------
-+                   .
-+                   .
-+              ----------
-+             | DPSW API |
-+              ----------
-+                   .           software
-+ ================= . ==============
-+                   .           hardware
-+          ---------------------
-+         | MC hardware portals |
-+          ---------------------
-+                   .
-+                   .
-+                 ------
-+                | DPSW |
-+                 ------
-+
-+Driver uses the switch device driver model and exposes each switch port as
-+a network interface, which can be included in a bridge. Traffic switched
-+between ports is offloaded into the hardware. Exposed network interfaces
-+are not used for I/O, they are used just for configuration. This
-+limitation is going to be addressed in the future.
-+
-+The DPSW can have ports connected to DPNIs or to PHYs via DPMACs.
-+
-+
-+ [ethA]     [ethB]     [ethC]     [ethD]     [ethE]     [ethF]
-+    :          :          :          :          :          :
-+    :          :          :          :          :          :
-+[eth drv]  [eth drv]  [                ethsw drv              ]
-+    :          :          :          :          :          :        kernel
-+========================================================================
-+    :          :          :          :          :          :        hardware
-+ [DPNI]      [DPNI]     [============= DPSW =================]
-+    |          |          |          |          |          |
-+    |           ----------           |       [DPMAC]    [DPMAC]
-+     -------------------------------            |          |
-+                                                |          |
-+                                              [PHY]      [PHY]
-+
-+For a more detailed description of the Ethernet switch device driver model
-+see:
-+	Documentation/networking/switchdev.txt
-+
-+Creating an Ethernet Switch
-+===========================
-+A device is created for the switch objects probed on the MC bus. Each DPSW
-+has a number of properties which determine the configuration options and
-+associated hardware resources.
-+
-+A DPSW object (and the other DPAA2 objects needed for a DPAA2 switch) can
-+be added to a container on the MC bus in one of two ways: statically,
-+through a Datapath Layout Binary file (DPL) that is parsed by MC at boot
-+time; or created dynamically at runtime, via the DPAA2 objects APIs.
-+
-+Features
-+========
-+Driver configures DPSW to perform hardware switching offload of
-+unicast/multicast/broadcast (VLAN tagged or untagged) traffic between its
-+ports.
-+
-+It allows configuration of hardware learning, flooding, multicast groups,
-+port VLAN configuration and STP state.
-+
-+Static entries can be added/removed from the FDB.
-+
-+Hardware statistics for each port are provided through ethtool -S option.
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/TODO
-@@ -0,0 +1,14 @@
-+* Add I/O capabilities on switch port netdevices. This will allow control
-+traffic to reach the CPU.
-+* Add ACL to redirect control traffic to CPU.
-+* Add support for displaying learned FDB entries
-+* MC firmware uprev; the DPAA2 objects used by the Ethernet Switch driver
-+need to   be kept in sync with binary interface changes in MC
-+* refine README file
-+* cleanup
-+
-+NOTE: At least first three of the above are required before getting the
-+DPAA2 Ethernet Switch driver out of staging. Another requirement is that
-+the fsl-mc bus driver is moved to drivers/bus and dpio driver is moved to
-+drivers/soc (this is required for I/O).
-+
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h
-@@ -0,0 +1,359 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017-2018 NXP
-+ *
-+ */
-+
-+#ifndef __FSL_DPSW_CMD_H
-+#define __FSL_DPSW_CMD_H
-+
-+/* DPSW Version */
-+#define DPSW_VER_MAJOR		8
-+#define DPSW_VER_MINOR		0
-+
-+#define DPSW_CMD_BASE_VERSION	1
-+#define DPSW_CMD_ID_OFFSET	4
-+
-+#define DPSW_CMD_ID(id)	(((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_BASE_VERSION)
-+
-+/* Command IDs */
-+#define DPSW_CMDID_CLOSE                    DPSW_CMD_ID(0x800)
-+#define DPSW_CMDID_OPEN                     DPSW_CMD_ID(0x802)
-+
-+#define DPSW_CMDID_GET_API_VERSION          DPSW_CMD_ID(0xa02)
-+
-+#define DPSW_CMDID_ENABLE                   DPSW_CMD_ID(0x002)
-+#define DPSW_CMDID_DISABLE                  DPSW_CMD_ID(0x003)
-+#define DPSW_CMDID_GET_ATTR                 DPSW_CMD_ID(0x004)
-+#define DPSW_CMDID_RESET                    DPSW_CMD_ID(0x005)
-+
-+#define DPSW_CMDID_SET_IRQ_ENABLE           DPSW_CMD_ID(0x012)
-+
-+#define DPSW_CMDID_SET_IRQ_MASK             DPSW_CMD_ID(0x014)
-+
-+#define DPSW_CMDID_GET_IRQ_STATUS           DPSW_CMD_ID(0x016)
-+#define DPSW_CMDID_CLEAR_IRQ_STATUS         DPSW_CMD_ID(0x017)
-+
-+#define DPSW_CMDID_IF_SET_TCI               DPSW_CMD_ID(0x030)
-+#define DPSW_CMDID_IF_SET_STP               DPSW_CMD_ID(0x031)
-+
-+#define DPSW_CMDID_IF_GET_COUNTER           DPSW_CMD_ID(0x034)
-+
-+#define DPSW_CMDID_IF_ENABLE                DPSW_CMD_ID(0x03D)
-+#define DPSW_CMDID_IF_DISABLE               DPSW_CMD_ID(0x03E)
-+
-+#define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH  DPSW_CMD_ID(0x044)
-+
-+#define DPSW_CMDID_IF_GET_LINK_STATE        DPSW_CMD_ID(0x046)
-+#define DPSW_CMDID_IF_SET_FLOODING          DPSW_CMD_ID(0x047)
-+#define DPSW_CMDID_IF_SET_BROADCAST         DPSW_CMD_ID(0x048)
-+
-+#define DPSW_CMDID_IF_GET_TCI               DPSW_CMD_ID(0x04A)
-+
-+#define DPSW_CMDID_IF_SET_LINK_CFG          DPSW_CMD_ID(0x04C)
-+
-+#define DPSW_CMDID_VLAN_ADD                 DPSW_CMD_ID(0x060)
-+#define DPSW_CMDID_VLAN_ADD_IF              DPSW_CMD_ID(0x061)
-+#define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED     DPSW_CMD_ID(0x062)
-+
-+#define DPSW_CMDID_VLAN_REMOVE_IF           DPSW_CMD_ID(0x064)
-+#define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED  DPSW_CMD_ID(0x065)
-+#define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING  DPSW_CMD_ID(0x066)
-+#define DPSW_CMDID_VLAN_REMOVE              DPSW_CMD_ID(0x067)
-+
-+#define DPSW_CMDID_FDB_ADD_UNICAST          DPSW_CMD_ID(0x084)
-+#define DPSW_CMDID_FDB_REMOVE_UNICAST       DPSW_CMD_ID(0x085)
-+#define DPSW_CMDID_FDB_ADD_MULTICAST        DPSW_CMD_ID(0x086)
-+#define DPSW_CMDID_FDB_REMOVE_MULTICAST     DPSW_CMD_ID(0x087)
-+#define DPSW_CMDID_FDB_SET_LEARNING_MODE    DPSW_CMD_ID(0x088)
-+
-+/* Macros for accessing command fields smaller than 1byte */
-+#define DPSW_MASK(field)        \
-+	GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \
-+		DPSW_##field##_SHIFT)
-+#define dpsw_set_field(var, field, val) \
-+	((var) |= (((val) << DPSW_##field##_SHIFT) & DPSW_MASK(field)))
-+#define dpsw_get_field(var, field)      \
-+	(((var) & DPSW_MASK(field)) >> DPSW_##field##_SHIFT)
-+#define dpsw_get_bit(var, bit) \
-+	(((var)  >> (bit)) & GENMASK(0, 0))
-+
-+struct dpsw_cmd_open {
-+	__le32 dpsw_id;
-+};
-+
-+#define DPSW_COMPONENT_TYPE_SHIFT	0
-+#define DPSW_COMPONENT_TYPE_SIZE	4
-+
-+struct dpsw_cmd_create {
-+	/* cmd word 0 */
-+	__le16 num_ifs;
-+	u8 max_fdbs;
-+	u8 max_meters_per_if;
-+	/* from LSB: only the first 4 bits */
-+	u8 component_type;
-+	u8 pad[3];
-+	/* cmd word 1 */
-+	__le16 max_vlans;
-+	__le16 max_fdb_entries;
-+	__le16 fdb_aging_time;
-+	__le16 max_fdb_mc_groups;
-+	/* cmd word 2 */
-+	__le64 options;
-+};
-+
-+struct dpsw_cmd_destroy {
-+	__le32 dpsw_id;
-+};
-+
-+#define DPSW_ENABLE_SHIFT 0
-+#define DPSW_ENABLE_SIZE  1
-+
-+struct dpsw_rsp_is_enabled {
-+	/* from LSB: enable:1 */
-+	u8 enabled;
-+};
-+
-+struct dpsw_cmd_set_irq_enable {
-+	u8 enable_state;
-+	u8 pad[3];
-+	u8 irq_index;
-+};
-+
-+struct dpsw_cmd_get_irq_enable {
-+	__le32 pad;
-+	u8 irq_index;
-+};
-+
-+struct dpsw_rsp_get_irq_enable {
-+	u8 enable_state;
-+};
-+
-+struct dpsw_cmd_set_irq_mask {
-+	__le32 mask;
-+	u8 irq_index;
-+};
-+
-+struct dpsw_cmd_get_irq_mask {
-+	__le32 pad;
-+	u8 irq_index;
-+};
-+
-+struct dpsw_rsp_get_irq_mask {
-+	__le32 mask;
-+};
-+
-+struct dpsw_cmd_get_irq_status {
-+	__le32 status;
-+	u8 irq_index;
-+};
-+
-+struct dpsw_rsp_get_irq_status {
-+	__le32 status;
-+};
-+
-+struct dpsw_cmd_clear_irq_status {
-+	__le32 status;
-+	u8 irq_index;
-+};
-+
-+#define DPSW_COMPONENT_TYPE_SHIFT	0
-+#define DPSW_COMPONENT_TYPE_SIZE	4
-+
-+struct dpsw_rsp_get_attr {
-+	/* cmd word 0 */
-+	__le16 num_ifs;
-+	u8 max_fdbs;
-+	u8 num_fdbs;
-+	__le16 max_vlans;
-+	__le16 num_vlans;
-+	/* cmd word 1 */
-+	__le16 max_fdb_entries;
-+	__le16 fdb_aging_time;
-+	__le32 dpsw_id;
-+	/* cmd word 2 */
-+	__le16 mem_size;
-+	__le16 max_fdb_mc_groups;
-+	u8 max_meters_per_if;
-+	/* from LSB only the first 4 bits */
-+	u8 component_type;
-+	__le16 pad;
-+	/* cmd word 3 */
-+	__le64 options;
-+};
-+
-+struct dpsw_cmd_if_set_flooding {
-+	__le16 if_id;
-+	/* from LSB: enable:1 */
-+	u8 enable;
-+};
-+
-+struct dpsw_cmd_if_set_broadcast {
-+	__le16 if_id;
-+	/* from LSB: enable:1 */
-+	u8 enable;
-+};
-+
-+#define DPSW_VLAN_ID_SHIFT	0
-+#define DPSW_VLAN_ID_SIZE	12
-+#define DPSW_DEI_SHIFT		12
-+#define DPSW_DEI_SIZE		1
-+#define DPSW_PCP_SHIFT		13
-+#define DPSW_PCP_SIZE		3
-+
-+struct dpsw_cmd_if_set_tci {
-+	__le16 if_id;
-+	/* from LSB: VLAN_ID:12 DEI:1 PCP:3 */
-+	__le16 conf;
-+};
-+
-+struct dpsw_cmd_if_get_tci {
-+	__le16 if_id;
-+};
-+
-+struct dpsw_rsp_if_get_tci {
-+	__le16 pad;
-+	__le16 vlan_id;
-+	u8 dei;
-+	u8 pcp;
-+};
-+
-+#define DPSW_STATE_SHIFT	0
-+#define DPSW_STATE_SIZE		4
-+
-+struct dpsw_cmd_if_set_stp {
-+	__le16 if_id;
-+	__le16 vlan_id;
-+	/* only the first LSB 4 bits */
-+	u8 state;
-+};
-+
-+#define DPSW_COUNTER_TYPE_SHIFT		0
-+#define DPSW_COUNTER_TYPE_SIZE		5
-+
-+struct dpsw_cmd_if_get_counter {
-+	__le16 if_id;
-+	/* from LSB: type:5 */
-+	u8 type;
-+};
-+
-+struct dpsw_rsp_if_get_counter {
-+	__le64 pad;
-+	__le64 counter;
-+};
-+
-+struct dpsw_cmd_if {
-+	__le16 if_id;
-+};
-+
-+struct dpsw_cmd_if_set_max_frame_length {
-+	__le16 if_id;
-+	__le16 frame_length;
-+};
-+
-+struct dpsw_cmd_if_set_link_cfg {
-+	/* cmd word 0 */
-+	__le16 if_id;
-+	u8 pad[6];
-+	/* cmd word 1 */
-+	__le32 rate;
-+	__le32 pad1;
-+	/* cmd word 2 */
-+	__le64 options;
-+};
-+
-+struct dpsw_cmd_if_get_link_state {
-+	__le16 if_id;
-+};
-+
-+#define DPSW_UP_SHIFT	0
-+#define DPSW_UP_SIZE	1
-+
-+struct dpsw_rsp_if_get_link_state {
-+	/* cmd word 0 */
-+	__le32 pad0;
-+	u8 up;
-+	u8 pad1[3];
-+	/* cmd word 1 */
-+	__le32 rate;
-+	__le32 pad2;
-+	/* cmd word 2 */
-+	__le64 options;
-+};
-+
-+struct dpsw_vlan_add {
-+	__le16 fdb_id;
-+	__le16 vlan_id;
-+};
-+
-+struct dpsw_cmd_vlan_manage_if {
-+	/* cmd word 0 */
-+	__le16 pad0;
-+	__le16 vlan_id;
-+	__le32 pad1;
-+	/* cmd word 1-4 */
-+	__le64 if_id[4];
-+};
-+
-+struct dpsw_cmd_vlan_remove {
-+	__le16 pad;
-+	__le16 vlan_id;
-+};
-+
-+struct dpsw_cmd_fdb_add {
-+	__le32 pad;
-+	__le16 fdb_aging_time;
-+	__le16 num_fdb_entries;
-+};
-+
-+struct dpsw_rsp_fdb_add {
-+	__le16 fdb_id;
-+};
-+
-+struct dpsw_cmd_fdb_remove {
-+	__le16 fdb_id;
-+};
-+
-+#define DPSW_ENTRY_TYPE_SHIFT	0
-+#define DPSW_ENTRY_TYPE_SIZE	4
-+
-+struct dpsw_cmd_fdb_unicast_op {
-+	/* cmd word 0 */
-+	__le16 fdb_id;
-+	u8 mac_addr[6];
-+	/* cmd word 1 */
-+	__le16 if_egress;
-+	/* only the first 4 bits from LSB */
-+	u8 type;
-+};
-+
-+struct dpsw_cmd_fdb_multicast_op {
-+	/* cmd word 0 */
-+	__le16 fdb_id;
-+	__le16 num_ifs;
-+	/* only the first 4 bits from LSB */
-+	u8 type;
-+	u8 pad[3];
-+	/* cmd word 1 */
-+	u8 mac_addr[6];
-+	__le16 pad2;
-+	/* cmd word 2-5 */
-+	__le64 if_id[4];
-+};
-+
-+#define DPSW_LEARNING_MODE_SHIFT	0
-+#define DPSW_LEARNING_MODE_SIZE		4
-+
-+struct dpsw_cmd_fdb_set_learning_mode {
-+	__le16 fdb_id;
-+	/* only the first 4 bits from LSB */
-+	u8 mode;
-+};
-+
-+struct dpsw_rsp_get_api_version {
-+	__le16 version_major;
-+	__le16 version_minor;
-+};
-+
-+#endif /* __FSL_DPSW_CMD_H */
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw.c
-@@ -0,0 +1,1165 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017-2018 NXP
-+ *
-+ */
-+
-+#include <linux/fsl/mc.h>
-+#include "dpsw.h"
-+#include "dpsw-cmd.h"
-+
-+static void build_if_id_bitmap(__le64 *bmap,
-+			       const u16 *id,
-+			       const u16 num_ifs)
-+{
-+	int i;
-+
-+	for (i = 0; (i < num_ifs) && (i < DPSW_MAX_IF); i++) {
-+		if (id[i] < DPSW_MAX_IF)
-+			bmap[id[i] / 64] |= cpu_to_le64(BIT_MASK(id[i] % 64));
-+	}
-+}
-+
-+/**
-+ * dpsw_open() - Open a control session for the specified object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @dpsw_id:	DPSW unique ID
-+ * @token:	Returned token; use in subsequent API calls
-+ *
-+ * This function can be used to open a control session for an
-+ * already created object; an object may have been declared in
-+ * the DPL or by calling the dpsw_create() function.
-+ * This function returns a unique authentication token,
-+ * associated with the specific object ID and the specific MC
-+ * portal; this token must be used in all subsequent commands for
-+ * this specific object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_open(struct fsl_mc_io *mc_io,
-+	      u32 cmd_flags,
-+	      int dpsw_id,
-+	      u16 *token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_open *cmd_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_OPEN,
-+					  cmd_flags,
-+					  0);
-+	cmd_params = (struct dpsw_cmd_open *)cmd.params;
-+	cmd_params->dpsw_id = cpu_to_le32(dpsw_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	*token = mc_cmd_hdr_read_token(&cmd);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpsw_close() - Close the control session of the object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ *
-+ * After this function is called, no further operations are
-+ * allowed on the object without opening a new control session.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_close(struct fsl_mc_io *mc_io,
-+	       u32 cmd_flags,
-+	       u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLOSE,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_enable() - Enable DPSW functionality
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_enable(struct fsl_mc_io *mc_io,
-+		u32 cmd_flags,
-+		u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_ENABLE,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_disable() - Disable DPSW functionality
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_disable(struct fsl_mc_io *mc_io,
-+		 u32 cmd_flags,
-+		 u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_DISABLE,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_reset() - Reset the DPSW, returns the object to initial state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_reset(struct fsl_mc_io *mc_io,
-+	       u32 cmd_flags,
-+	       u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_RESET,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_set_irq_enable() - Set overall interrupt state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPCI object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Interrupt state - enable = 1, disable = 0
-+ *
-+ * Allows GPP software to control when interrupts are generated.
-+ * Each interrupt can have up to 32 causes.  The enable/disable control's the
-+ * overall interrupt state. if the interrupt is disabled no causes will cause
-+ * an interrupt
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_set_irq_enable(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u8 irq_index,
-+			u8 en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_set_irq_enable *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_set_irq_enable *)cmd.params;
-+	dpsw_set_field(cmd_params->enable_state, ENABLE, en);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_set_irq_mask() - Set interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPCI object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	Event mask to trigger interrupt;
-+ *		each bit:
-+ *			0 = ignore event
-+ *			1 = consider event for asserting IRQ
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_set_irq_mask(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      u8 irq_index,
-+		      u32 mask)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_set_irq_mask *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_set_irq_mask *)cmd.params;
-+	cmd_params->mask = cpu_to_le32(mask);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_get_irq_status() - Get the current status of any pending interrupts
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	Returned interrupts status - one bit per cause:
-+ *			0 = no interrupt pending
-+ *			1 = interrupt pending
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_get_irq_status(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u8 irq_index,
-+			u32 *status)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_get_irq_status *cmd_params;
-+	struct dpsw_rsp_get_irq_status *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_get_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(*status);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpsw_rsp_get_irq_status *)cmd.params;
-+	*status = le32_to_cpu(rsp_params->status);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpsw_clear_irq_status() - Clear a pending interrupt's status
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPCI object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	bits to clear (W1C) - one bit per cause:
-+ *			0 = don't change
-+ *			1 = clear status bit
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_clear_irq_status(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u8 irq_index,
-+			  u32 status)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_clear_irq_status *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLEAR_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_clear_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(status);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_get_attributes() - Retrieve DPSW attributes
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @attr:	Returned DPSW attributes
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_get_attributes(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			struct dpsw_attr *attr)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_rsp_get_attr *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_ATTR,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpsw_rsp_get_attr *)cmd.params;
-+	attr->num_ifs = le16_to_cpu(rsp_params->num_ifs);
-+	attr->max_fdbs = rsp_params->max_fdbs;
-+	attr->num_fdbs = rsp_params->num_fdbs;
-+	attr->max_vlans = le16_to_cpu(rsp_params->max_vlans);
-+	attr->num_vlans = le16_to_cpu(rsp_params->num_vlans);
-+	attr->max_fdb_entries = le16_to_cpu(rsp_params->max_fdb_entries);
-+	attr->fdb_aging_time = le16_to_cpu(rsp_params->fdb_aging_time);
-+	attr->id = le32_to_cpu(rsp_params->dpsw_id);
-+	attr->mem_size = le16_to_cpu(rsp_params->mem_size);
-+	attr->max_fdb_mc_groups = le16_to_cpu(rsp_params->max_fdb_mc_groups);
-+	attr->max_meters_per_if = rsp_params->max_meters_per_if;
-+	attr->options = le64_to_cpu(rsp_params->options);
-+	attr->component_type = dpsw_get_field(rsp_params->component_type,
-+					      COMPONENT_TYPE);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpsw_if_set_link_cfg() - Set the link configuration.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface id
-+ * @cfg:	Link configuration
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u16 if_id,
-+			 struct dpsw_link_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_set_link_cfg *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_LINK_CFG,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_set_link_cfg *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	cmd_params->rate = cpu_to_le32(cfg->rate);
-+	cmd_params->options = cpu_to_le64(cfg->options);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_if_get_link_state - Return the link state
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface id
-+ * @state:	Link state	1 - linkup, 0 - link down or disconnected
-+ *
-+ * @Return	'0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_get_link_state(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   u16 if_id,
-+			   struct dpsw_link_state *state)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_get_link_state *cmd_params;
-+	struct dpsw_rsp_if_get_link_state *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_LINK_STATE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_get_link_state *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpsw_rsp_if_get_link_state *)cmd.params;
-+	state->rate = le32_to_cpu(rsp_params->rate);
-+	state->options = le64_to_cpu(rsp_params->options);
-+	state->up = dpsw_get_field(rsp_params->up, UP);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpsw_if_set_flooding() - Enable Disable flooding for particular interface
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface Identifier
-+ * @en:		1 - enable, 0 - disable
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_set_flooding(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u16 if_id,
-+			 u8 en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_set_flooding *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_FLOODING,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_set_flooding *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	dpsw_set_field(cmd_params->enable, ENABLE, en);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_if_set_broadcast() - Enable/disable broadcast for particular interface
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface Identifier
-+ * @en:		1 - enable, 0 - disable
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u16 if_id,
-+			  u8 en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_set_broadcast *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_BROADCAST,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_set_broadcast *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	dpsw_set_field(cmd_params->enable, ENABLE, en);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_if_set_tci() - Set default VLAN Tag Control Information (TCI)
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface Identifier
-+ * @cfg:	Tag Control Information Configuration
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_set_tci(struct fsl_mc_io *mc_io,
-+		    u32 cmd_flags,
-+		    u16 token,
-+		    u16 if_id,
-+		    const struct dpsw_tci_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_set_tci *cmd_params;
-+	u16 tmp_conf = 0;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_TCI,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_set_tci *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	dpsw_set_field(tmp_conf, VLAN_ID, cfg->vlan_id);
-+	dpsw_set_field(tmp_conf, DEI, cfg->dei);
-+	dpsw_set_field(tmp_conf, PCP, cfg->pcp);
-+	cmd_params->conf = cpu_to_le16(tmp_conf);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_if_get_tci() - Get default VLAN Tag Control Information (TCI)
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface Identifier
-+ * @cfg:	Tag Control Information Configuration
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_get_tci(struct fsl_mc_io *mc_io,
-+		    u32 cmd_flags,
-+		    u16 token,
-+		    u16 if_id,
-+		    struct dpsw_tci_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_get_tci *cmd_params;
-+	struct dpsw_rsp_if_get_tci *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_TCI,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_get_tci *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpsw_rsp_if_get_tci *)cmd.params;
-+	cfg->pcp = rsp_params->pcp;
-+	cfg->dei = rsp_params->dei;
-+	cfg->vlan_id = le16_to_cpu(rsp_params->vlan_id);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpsw_if_set_stp() - Function sets Spanning Tree Protocol (STP) state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface Identifier
-+ * @cfg:	STP State configuration parameters
-+ *
-+ * The following STP states are supported -
-+ * blocking, listening, learning, forwarding and disabled.
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_set_stp(struct fsl_mc_io *mc_io,
-+		    u32 cmd_flags,
-+		    u16 token,
-+		    u16 if_id,
-+		    const struct dpsw_stp_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_set_stp *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_STP,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_set_stp *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	cmd_params->vlan_id = cpu_to_le16(cfg->vlan_id);
-+	dpsw_set_field(cmd_params->state, STATE, cfg->state);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_if_get_counter() - Get specific counter of particular interface
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface Identifier
-+ * @type:	Counter type
-+ * @counter:	return value
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_get_counter(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u16 if_id,
-+			enum dpsw_counter type,
-+			u64 *counter)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_get_counter *cmd_params;
-+	struct dpsw_rsp_if_get_counter *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_COUNTER,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_get_counter *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	dpsw_set_field(cmd_params->type, COUNTER_TYPE, type);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpsw_rsp_if_get_counter *)cmd.params;
-+	*counter = le64_to_cpu(rsp_params->counter);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpsw_if_enable() - Enable Interface
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface Identifier
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_enable(struct fsl_mc_io *mc_io,
-+		   u32 cmd_flags,
-+		   u16 token,
-+		   u16 if_id)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_if_disable() - Disable Interface
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @if_id:	Interface Identifier
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_disable(struct fsl_mc_io *mc_io,
-+		    u32 cmd_flags,
-+		    u16 token,
-+		    u16 if_id)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_DISABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_if_set_max_frame_length() - Set Maximum Receive frame length.
-+ * @mc_io:		Pointer to MC portal's I/O object
-+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:		Token of DPSW object
-+ * @if_id:		Interface Identifier
-+ * @frame_length:	Maximum Frame Length
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io,
-+				 u32 cmd_flags,
-+				 u16 token,
-+				 u16 if_id,
-+				 u16 frame_length)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_if_set_max_frame_length *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_if_set_max_frame_length *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	cmd_params->frame_length = cpu_to_le16(frame_length);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_vlan_add() - Adding new VLAN to DPSW.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @vlan_id:	VLAN Identifier
-+ * @cfg:	VLAN configuration
-+ *
-+ * Only VLAN ID and FDB ID are required parameters here.
-+ * 12 bit VLAN ID is defined in IEEE802.1Q.
-+ * Adding a duplicate VLAN ID is not allowed.
-+ * FDB ID can be shared across multiple VLANs. Shared learning
-+ * is obtained by calling dpsw_vlan_add for multiple VLAN IDs
-+ * with same fdb_id
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_vlan_add(struct fsl_mc_io *mc_io,
-+		  u32 cmd_flags,
-+		  u16 token,
-+		  u16 vlan_id,
-+		  const struct dpsw_vlan_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_vlan_add *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_vlan_add *)cmd.params;
-+	cmd_params->fdb_id = cpu_to_le16(cfg->fdb_id);
-+	cmd_params->vlan_id = cpu_to_le16(vlan_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_vlan_add_if() - Adding a set of interfaces to an existing VLAN.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @vlan_id:	VLAN Identifier
-+ * @cfg:	Set of interfaces to add
-+ *
-+ * It adds only interfaces not belonging to this VLAN yet,
-+ * otherwise an error is generated and an entire command is
-+ * ignored. This function can be called numerous times always
-+ * providing required interfaces delta.
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_vlan_add_if(struct fsl_mc_io *mc_io,
-+		     u32 cmd_flags,
-+		     u16 token,
-+		     u16 vlan_id,
-+		     const struct dpsw_vlan_if_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_vlan_manage_if *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_vlan_manage_if *)cmd.params;
-+	cmd_params->vlan_id = cpu_to_le16(vlan_id);
-+	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_vlan_add_if_untagged() - Defining a set of interfaces that should be
-+ *				transmitted as untagged.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @vlan_id:	VLAN Identifier
-+ * @cfg:	Set of interfaces that should be transmitted as untagged
-+ *
-+ * These interfaces should already belong to this VLAN.
-+ * By default all interfaces are transmitted as tagged.
-+ * Providing un-existing interface or untagged interface that is
-+ * configured untagged already generates an error and the entire
-+ * command is ignored.
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io,
-+			      u32 cmd_flags,
-+			      u16 token,
-+			      u16 vlan_id,
-+			      const struct dpsw_vlan_if_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_vlan_manage_if *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF_UNTAGGED,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_vlan_manage_if *)cmd.params;
-+	cmd_params->vlan_id = cpu_to_le16(vlan_id);
-+	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_vlan_remove_if() - Remove interfaces from an existing VLAN.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @vlan_id:	VLAN Identifier
-+ * @cfg:	Set of interfaces that should be removed
-+ *
-+ * Interfaces must belong to this VLAN, otherwise an error
-+ * is returned and an the command is ignored
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u16 vlan_id,
-+			const struct dpsw_vlan_if_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_vlan_manage_if *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_vlan_manage_if *)cmd.params;
-+	cmd_params->vlan_id = cpu_to_le16(vlan_id);
-+	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_vlan_remove_if_untagged() - Define a set of interfaces that should be
-+ *		converted from transmitted as untagged to transmit as tagged.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @vlan_id:	VLAN Identifier
-+ * @cfg:	Set of interfaces that should be removed
-+ *
-+ * Interfaces provided by API have to belong to this VLAN and
-+ * configured untagged, otherwise an error is returned and the
-+ * command is ignored
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io,
-+				 u32 cmd_flags,
-+				 u16 token,
-+				 u16 vlan_id,
-+				 const struct dpsw_vlan_if_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_vlan_manage_if *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_vlan_manage_if *)cmd.params;
-+	cmd_params->vlan_id = cpu_to_le16(vlan_id);
-+	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_vlan_remove() - Remove an entire VLAN
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @vlan_id:	VLAN Identifier
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_vlan_remove(struct fsl_mc_io *mc_io,
-+		     u32 cmd_flags,
-+		     u16 token,
-+		     u16 vlan_id)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_vlan_remove *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_vlan_remove *)cmd.params;
-+	cmd_params->vlan_id = cpu_to_le16(vlan_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_fdb_add_unicast() - Function adds an unicast entry into MAC lookup table
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @fdb_id:	Forwarding Database Identifier
-+ * @cfg:	Unicast entry configuration
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u16 fdb_id,
-+			 const struct dpsw_fdb_unicast_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_fdb_unicast_op *cmd_params;
-+	int i;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD_UNICAST,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_fdb_unicast_op *)cmd.params;
-+	cmd_params->fdb_id = cpu_to_le16(fdb_id);
-+	cmd_params->if_egress = cpu_to_le16(cfg->if_egress);
-+	for (i = 0; i < 6; i++)
-+		cmd_params->mac_addr[i] = cfg->mac_addr[5 - i];
-+	dpsw_set_field(cmd_params->type, ENTRY_TYPE, cfg->type);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_fdb_remove_unicast() - removes an entry from MAC lookup table
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @fdb_id:	Forwarding Database Identifier
-+ * @cfg:	Unicast entry configuration
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io,
-+			    u32 cmd_flags,
-+			    u16 token,
-+			    u16 fdb_id,
-+			    const struct dpsw_fdb_unicast_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_fdb_unicast_op *cmd_params;
-+	int i;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE_UNICAST,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_fdb_unicast_op *)cmd.params;
-+	cmd_params->fdb_id = cpu_to_le16(fdb_id);
-+	for (i = 0; i < 6; i++)
-+		cmd_params->mac_addr[i] = cfg->mac_addr[5 - i];
-+	cmd_params->if_egress = cpu_to_le16(cfg->if_egress);
-+	dpsw_set_field(cmd_params->type, ENTRY_TYPE, cfg->type);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_fdb_add_multicast() - Add a set of egress interfaces to multi-cast group
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @fdb_id:	Forwarding Database Identifier
-+ * @cfg:	Multicast entry configuration
-+ *
-+ * If group doesn't exist, it will be created.
-+ * It adds only interfaces not belonging to this multicast group
-+ * yet, otherwise error will be generated and the command is
-+ * ignored.
-+ * This function may be called numerous times always providing
-+ * required interfaces delta.
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   u16 fdb_id,
-+			   const struct dpsw_fdb_multicast_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_fdb_multicast_op *cmd_params;
-+	int i;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD_MULTICAST,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_fdb_multicast_op *)cmd.params;
-+	cmd_params->fdb_id = cpu_to_le16(fdb_id);
-+	cmd_params->num_ifs = cpu_to_le16(cfg->num_ifs);
-+	dpsw_set_field(cmd_params->type, ENTRY_TYPE, cfg->type);
-+	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
-+	for (i = 0; i < 6; i++)
-+		cmd_params->mac_addr[i] = cfg->mac_addr[5 - i];
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_fdb_remove_multicast() - Removing interfaces from an existing multicast
-+ *				group.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @fdb_id:	Forwarding Database Identifier
-+ * @cfg:	Multicast entry configuration
-+ *
-+ * Interfaces provided by this API have to exist in the group,
-+ * otherwise an error will be returned and an entire command
-+ * ignored. If there is no interface left in the group,
-+ * an entire group is deleted
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io,
-+			      u32 cmd_flags,
-+			      u16 token,
-+			      u16 fdb_id,
-+			      const struct dpsw_fdb_multicast_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_fdb_multicast_op *cmd_params;
-+	int i;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE_MULTICAST,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_fdb_multicast_op *)cmd.params;
-+	cmd_params->fdb_id = cpu_to_le16(fdb_id);
-+	cmd_params->num_ifs = cpu_to_le16(cfg->num_ifs);
-+	dpsw_set_field(cmd_params->type, ENTRY_TYPE, cfg->type);
-+	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
-+	for (i = 0; i < 6; i++)
-+		cmd_params->mac_addr[i] = cfg->mac_addr[5 - i];
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_fdb_set_learning_mode() - Define FDB learning mode
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSW object
-+ * @fdb_id:	Forwarding Database Identifier
-+ * @mode:	Learning mode
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io,
-+			       u32 cmd_flags,
-+			       u16 token,
-+			       u16 fdb_id,
-+			       enum dpsw_fdb_learning_mode mode)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_cmd_fdb_set_learning_mode *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_SET_LEARNING_MODE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpsw_cmd_fdb_set_learning_mode *)cmd.params;
-+	cmd_params->fdb_id = cpu_to_le16(fdb_id);
-+	dpsw_set_field(cmd_params->mode, LEARNING_MODE, mode);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpsw_get_api_version() - Get Data Path Switch API version
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @major_ver:	Major version of data path switch API
-+ * @minor_ver:	Minor version of data path switch API
-+ *
-+ * Return:  '0' on Success; Error code otherwise.
-+ */
-+int dpsw_get_api_version(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 *major_ver,
-+			 u16 *minor_ver)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpsw_rsp_get_api_version *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_API_VERSION,
-+					  cmd_flags,
-+					  0);
-+
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpsw_rsp_get_api_version *)cmd.params;
-+	*major_ver = le16_to_cpu(rsp_params->version_major);
-+	*minor_ver = le16_to_cpu(rsp_params->version_minor);
-+
-+	return 0;
-+}
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw.h
-@@ -0,0 +1,592 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
-+ * Copyright 2017-2018 NXP
-+ *
-+ */
-+
-+#ifndef __FSL_DPSW_H
-+#define __FSL_DPSW_H
-+
-+/* Data Path L2-Switch API
-+ * Contains API for handling DPSW topology and functionality
-+ */
-+
-+struct fsl_mc_io;
-+
-+/**
-+ * DPSW general definitions
-+ */
-+
-+/**
-+ * Maximum number of traffic class priorities
-+ */
-+#define DPSW_MAX_PRIORITIES	8
-+/**
-+ * Maximum number of interfaces
-+ */
-+#define DPSW_MAX_IF		64
-+
-+int dpsw_open(struct fsl_mc_io *mc_io,
-+	      u32 cmd_flags,
-+	      int dpsw_id,
-+	      u16 *token);
-+
-+int dpsw_close(struct fsl_mc_io *mc_io,
-+	       u32 cmd_flags,
-+	       u16 token);
-+
-+/**
-+ * DPSW options
-+ */
-+
-+/**
-+ * Disable flooding
-+ */
-+#define DPSW_OPT_FLOODING_DIS		0x0000000000000001ULL
-+/**
-+ * Disable Multicast
-+ */
-+#define DPSW_OPT_MULTICAST_DIS		0x0000000000000004ULL
-+/**
-+ * Support control interface
-+ */
-+#define DPSW_OPT_CTRL_IF_DIS		0x0000000000000010ULL
-+/**
-+ * Disable flooding metering
-+ */
-+#define DPSW_OPT_FLOODING_METERING_DIS  0x0000000000000020ULL
-+/**
-+ * Enable metering
-+ */
-+#define DPSW_OPT_METERING_EN            0x0000000000000040ULL
-+
-+/**
-+ * enum dpsw_component_type - component type of a bridge
-+ * @DPSW_COMPONENT_TYPE_C_VLAN: A C-VLAN component of an
-+ *   enterprise VLAN bridge or of a Provider Bridge used
-+ *   to process C-tagged frames
-+ * @DPSW_COMPONENT_TYPE_S_VLAN: An S-VLAN component of a
-+ *   Provider Bridge
-+ *
-+ */
-+enum dpsw_component_type {
-+	DPSW_COMPONENT_TYPE_C_VLAN = 0,
-+	DPSW_COMPONENT_TYPE_S_VLAN
-+};
-+
-+/**
-+ * struct dpsw_cfg - DPSW configuration
-+ * @num_ifs: Number of external and internal interfaces
-+ * @adv: Advanced parameters; default is all zeros;
-+ *		 use this structure to change default settings
-+ */
-+struct dpsw_cfg {
-+	u16 num_ifs;
-+	/**
-+	 * struct adv - Advanced parameters
-+	 * @options: Enable/Disable DPSW features (bitmap)
-+	 * @max_vlans: Maximum Number of VLAN's; 0 - indicates default 16
-+	 * @max_meters_per_if: Number of meters per interface
-+	 * @max_fdbs: Maximum Number of FDB's; 0 - indicates default 16
-+	 * @max_fdb_entries: Number of FDB entries for default FDB table;
-+	 *			0 - indicates default 1024 entries.
-+	 * @fdb_aging_time: Default FDB aging time for default FDB table;
-+	 *			0 - indicates default 300 seconds
-+	 * @max_fdb_mc_groups: Number of multicast groups in each FDB table;
-+	 *			0 - indicates default 32
-+	 * @component_type: Indicates the component type of this bridge
-+	 */
-+	struct {
-+		u64 options;
-+		u16 max_vlans;
-+		u8 max_meters_per_if;
-+		u8 max_fdbs;
-+		u16 max_fdb_entries;
-+		u16 fdb_aging_time;
-+		u16 max_fdb_mc_groups;
-+		enum dpsw_component_type component_type;
-+	} adv;
-+};
-+
-+int dpsw_enable(struct fsl_mc_io *mc_io,
-+		u32 cmd_flags,
-+		u16 token);
-+
-+int dpsw_disable(struct fsl_mc_io *mc_io,
-+		 u32 cmd_flags,
-+		 u16 token);
-+
-+int dpsw_reset(struct fsl_mc_io *mc_io,
-+	       u32 cmd_flags,
-+	       u16 token);
-+
-+/**
-+ * DPSW IRQ Index and Events
-+ */
-+
-+#define DPSW_IRQ_INDEX_IF		0x0000
-+#define DPSW_IRQ_INDEX_L2SW		0x0001
-+
-+/**
-+ * IRQ event - Indicates that the link state changed
-+ */
-+#define DPSW_IRQ_EVENT_LINK_CHANGED	0x0001
-+
-+/**
-+ * struct dpsw_irq_cfg - IRQ configuration
-+ * @addr:	Address that must be written to signal a message-based interrupt
-+ * @val:	Value to write into irq_addr address
-+ * @irq_num: A user defined number associated with this IRQ
-+ */
-+struct dpsw_irq_cfg {
-+	     u64 addr;
-+	     u32 val;
-+	     int irq_num;
-+};
-+
-+int dpsw_set_irq_enable(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u8 irq_index,
-+			u8 en);
-+
-+int dpsw_set_irq_mask(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      u8 irq_index,
-+		      u32 mask);
-+
-+int dpsw_get_irq_status(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u8 irq_index,
-+			u32 *status);
-+
-+int dpsw_clear_irq_status(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u8 irq_index,
-+			  u32 status);
-+
-+/**
-+ * struct dpsw_attr - Structure representing DPSW attributes
-+ * @id: DPSW object ID
-+ * @options: Enable/Disable DPSW features
-+ * @max_vlans: Maximum Number of VLANs
-+ * @max_meters_per_if:  Number of meters per interface
-+ * @max_fdbs: Maximum Number of FDBs
-+ * @max_fdb_entries: Number of FDB entries for default FDB table;
-+ *			0 - indicates default 1024 entries.
-+ * @fdb_aging_time: Default FDB aging time for default FDB table;
-+ *			0 - indicates default 300 seconds
-+ * @max_fdb_mc_groups: Number of multicast groups in each FDB table;
-+ *			0 - indicates default 32
-+ * @mem_size: DPSW frame storage memory size
-+ * @num_ifs: Number of interfaces
-+ * @num_vlans: Current number of VLANs
-+ * @num_fdbs: Current number of FDBs
-+ * @component_type: Component type of this bridge
-+ */
-+struct dpsw_attr {
-+	int id;
-+	u64 options;
-+	u16 max_vlans;
-+	u8 max_meters_per_if;
-+	u8 max_fdbs;
-+	u16 max_fdb_entries;
-+	u16 fdb_aging_time;
-+	u16 max_fdb_mc_groups;
-+	u16 num_ifs;
-+	u16 mem_size;
-+	u16 num_vlans;
-+	u8 num_fdbs;
-+	enum dpsw_component_type component_type;
-+};
-+
-+int dpsw_get_attributes(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			struct dpsw_attr *attr);
-+
-+/**
-+ * enum dpsw_action - Action selection for special/control frames
-+ * @DPSW_ACTION_DROP: Drop frame
-+ * @DPSW_ACTION_REDIRECT: Redirect frame to control port
-+ */
-+enum dpsw_action {
-+	DPSW_ACTION_DROP = 0,
-+	DPSW_ACTION_REDIRECT = 1
-+};
-+
-+/**
-+ * Enable auto-negotiation
-+ */
-+#define DPSW_LINK_OPT_AUTONEG		0x0000000000000001ULL
-+/**
-+ * Enable half-duplex mode
-+ */
-+#define DPSW_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
-+/**
-+ * Enable pause frames
-+ */
-+#define DPSW_LINK_OPT_PAUSE		0x0000000000000004ULL
-+/**
-+ * Enable a-symmetric pause frames
-+ */
-+#define DPSW_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
-+
-+/**
-+ * struct dpsw_link_cfg - Structure representing DPSW link configuration
-+ * @rate: Rate
-+ * @options: Mask of available options; use 'DPSW_LINK_OPT_<X>' values
-+ */
-+struct dpsw_link_cfg {
-+	u32 rate;
-+	u64 options;
-+};
-+
-+int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u16 if_id,
-+			 struct dpsw_link_cfg *cfg);
-+/**
-+ * struct dpsw_link_state - Structure representing DPSW link state
-+ * @rate: Rate
-+ * @options: Mask of available options; use 'DPSW_LINK_OPT_<X>' values
-+ * @up: 0 - covers two cases: down and disconnected, 1 - up
-+ */
-+struct dpsw_link_state {
-+	u32 rate;
-+	u64 options;
-+	u8 up;
-+};
-+
-+int dpsw_if_get_link_state(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   u16 if_id,
-+			   struct dpsw_link_state *state);
-+
-+int dpsw_if_set_flooding(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u16 if_id,
-+			 u8 en);
-+
-+int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u16 if_id,
-+			  u8 en);
-+
-+/**
-+ * struct dpsw_tci_cfg - Tag Control Information (TCI) configuration
-+ * @pcp: Priority Code Point (PCP): a 3-bit field which refers
-+ *		 to the IEEE 802.1p priority
-+ * @dei: Drop Eligible Indicator (DEI): a 1-bit field. May be used
-+ *		 separately or in conjunction with PCP to indicate frames
-+ *		 eligible to be dropped in the presence of congestion
-+ * @vlan_id: VLAN Identifier (VID): a 12-bit field specifying the VLAN
-+ *			to which the frame belongs. The hexadecimal values
-+ *			of 0x000 and 0xFFF are reserved;
-+ *			all other values may be used as VLAN identifiers,
-+ *			allowing up to 4,094 VLANs
-+ */
-+struct dpsw_tci_cfg {
-+	u8 pcp;
-+	u8 dei;
-+	u16 vlan_id;
-+};
-+
-+int dpsw_if_set_tci(struct fsl_mc_io *mc_io,
-+		    u32 cmd_flags,
-+		    u16 token,
-+		    u16 if_id,
-+		    const struct dpsw_tci_cfg *cfg);
-+
-+int dpsw_if_get_tci(struct fsl_mc_io *mc_io,
-+		    u32 cmd_flags,
-+		    u16 token,
-+		    u16 if_id,
-+		    struct dpsw_tci_cfg *cfg);
-+
-+/**
-+ * enum dpsw_stp_state - Spanning Tree Protocol (STP) states
-+ * @DPSW_STP_STATE_BLOCKING: Blocking state
-+ * @DPSW_STP_STATE_LISTENING: Listening state
-+ * @DPSW_STP_STATE_LEARNING: Learning state
-+ * @DPSW_STP_STATE_FORWARDING: Forwarding state
-+ *
-+ */
-+enum dpsw_stp_state {
-+	DPSW_STP_STATE_DISABLED = 0,
-+	DPSW_STP_STATE_LISTENING = 1,
-+	DPSW_STP_STATE_LEARNING = 2,
-+	DPSW_STP_STATE_FORWARDING = 3,
-+	DPSW_STP_STATE_BLOCKING = 0
-+};
-+
-+/**
-+ * struct dpsw_stp_cfg - Spanning Tree Protocol (STP) Configuration
-+ * @vlan_id: VLAN ID STP state
-+ * @state: STP state
-+ */
-+struct dpsw_stp_cfg {
-+	u16 vlan_id;
-+	enum dpsw_stp_state state;
-+};
-+
-+int dpsw_if_set_stp(struct fsl_mc_io *mc_io,
-+		    u32 cmd_flags,
-+		    u16 token,
-+		    u16 if_id,
-+		    const struct dpsw_stp_cfg *cfg);
-+
-+/**
-+ * enum dpsw_accepted_frames - Types of frames to accept
-+ * @DPSW_ADMIT_ALL: The device accepts VLAN tagged, untagged and
-+ *			priority tagged frames
-+ * @DPSW_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or
-+ *			Priority-Tagged frames received on this interface.
-+ *
-+ */
-+enum dpsw_accepted_frames {
-+	DPSW_ADMIT_ALL = 1,
-+	DPSW_ADMIT_ONLY_VLAN_TAGGED = 3
-+};
-+
-+/**
-+ * enum dpsw_counter  - Counters types
-+ * @DPSW_CNT_ING_FRAME: Counts ingress frames
-+ * @DPSW_CNT_ING_BYTE: Counts ingress bytes
-+ * @DPSW_CNT_ING_FLTR_FRAME: Counts filtered ingress frames
-+ * @DPSW_CNT_ING_FRAME_DISCARD: Counts discarded ingress frame
-+ * @DPSW_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
-+ * @DPSW_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
-+ * @DPSW_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
-+ * @DPSW_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
-+ * @DPSW_CNT_EGR_FRAME: Counts egress frames
-+ * @DPSW_CNT_EGR_BYTE: Counts eEgress bytes
-+ * @DPSW_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames
-+ * @DPSW_CNT_EGR_STP_FRAME_DISCARD: Counts egress STP discarded frames
-+ */
-+enum dpsw_counter {
-+	DPSW_CNT_ING_FRAME = 0x0,
-+	DPSW_CNT_ING_BYTE = 0x1,
-+	DPSW_CNT_ING_FLTR_FRAME = 0x2,
-+	DPSW_CNT_ING_FRAME_DISCARD = 0x3,
-+	DPSW_CNT_ING_MCAST_FRAME = 0x4,
-+	DPSW_CNT_ING_MCAST_BYTE = 0x5,
-+	DPSW_CNT_ING_BCAST_FRAME = 0x6,
-+	DPSW_CNT_ING_BCAST_BYTES = 0x7,
-+	DPSW_CNT_EGR_FRAME = 0x8,
-+	DPSW_CNT_EGR_BYTE = 0x9,
-+	DPSW_CNT_EGR_FRAME_DISCARD = 0xa,
-+	DPSW_CNT_EGR_STP_FRAME_DISCARD = 0xb
-+};
-+
-+int dpsw_if_get_counter(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u16 if_id,
-+			enum dpsw_counter type,
-+			u64 *counter);
-+
-+int dpsw_if_enable(struct fsl_mc_io *mc_io,
-+		   u32 cmd_flags,
-+		   u16 token,
-+		   u16 if_id);
-+
-+int dpsw_if_disable(struct fsl_mc_io *mc_io,
-+		    u32 cmd_flags,
-+		    u16 token,
-+		    u16 if_id);
-+
-+int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io,
-+				 u32 cmd_flags,
-+				 u16 token,
-+				 u16 if_id,
-+				 u16 frame_length);
-+
-+/**
-+ * struct dpsw_vlan_cfg - VLAN Configuration
-+ * @fdb_id: Forwarding Data Base
-+ */
-+struct dpsw_vlan_cfg {
-+	u16 fdb_id;
-+};
-+
-+int dpsw_vlan_add(struct fsl_mc_io *mc_io,
-+		  u32 cmd_flags,
-+		  u16 token,
-+		  u16 vlan_id,
-+		  const struct dpsw_vlan_cfg *cfg);
-+
-+/**
-+ * struct dpsw_vlan_if_cfg - Set of VLAN Interfaces
-+ * @num_ifs: The number of interfaces that are assigned to the egress
-+ *		list for this VLAN
-+ * @if_id: The set of interfaces that are
-+ *		assigned to the egress list for this VLAN
-+ */
-+struct dpsw_vlan_if_cfg {
-+	u16 num_ifs;
-+	u16 if_id[DPSW_MAX_IF];
-+};
-+
-+int dpsw_vlan_add_if(struct fsl_mc_io *mc_io,
-+		     u32 cmd_flags,
-+		     u16 token,
-+		     u16 vlan_id,
-+		     const struct dpsw_vlan_if_cfg *cfg);
-+
-+int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io,
-+			      u32 cmd_flags,
-+			      u16 token,
-+			      u16 vlan_id,
-+			      const struct dpsw_vlan_if_cfg *cfg);
-+
-+int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u16 vlan_id,
-+			const struct dpsw_vlan_if_cfg *cfg);
-+
-+int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io,
-+				 u32 cmd_flags,
-+				 u16 token,
-+				 u16 vlan_id,
-+				 const struct dpsw_vlan_if_cfg *cfg);
-+
-+int dpsw_vlan_remove(struct fsl_mc_io *mc_io,
-+		     u32 cmd_flags,
-+		     u16 token,
-+		     u16 vlan_id);
-+
-+/**
-+ * enum dpsw_fdb_entry_type - FDB Entry type - Static/Dynamic
-+ * @DPSW_FDB_ENTRY_STATIC: Static entry
-+ * @DPSW_FDB_ENTRY_DINAMIC: Dynamic entry
-+ */
-+enum dpsw_fdb_entry_type {
-+	DPSW_FDB_ENTRY_STATIC = 0,
-+	DPSW_FDB_ENTRY_DINAMIC = 1
-+};
-+
-+/**
-+ * struct dpsw_fdb_unicast_cfg - Unicast entry configuration
-+ * @type: Select static or dynamic entry
-+ * @mac_addr: MAC address
-+ * @if_egress: Egress interface ID
-+ */
-+struct dpsw_fdb_unicast_cfg {
-+	enum dpsw_fdb_entry_type type;
-+	u8 mac_addr[6];
-+	u16 if_egress;
-+};
-+
-+int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u16 fdb_id,
-+			 const struct dpsw_fdb_unicast_cfg *cfg);
-+
-+int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io,
-+			    u32 cmd_flags,
-+			    u16 token,
-+			    u16 fdb_id,
-+			    const struct dpsw_fdb_unicast_cfg *cfg);
-+
-+/**
-+ * struct dpsw_fdb_multicast_cfg - Multi-cast entry configuration
-+ * @type: Select static or dynamic entry
-+ * @mac_addr: MAC address
-+ * @num_ifs: Number of external and internal interfaces
-+ * @if_id: Egress interface IDs
-+ */
-+struct dpsw_fdb_multicast_cfg {
-+	enum dpsw_fdb_entry_type type;
-+	u8 mac_addr[6];
-+	u16 num_ifs;
-+	u16 if_id[DPSW_MAX_IF];
-+};
-+
-+int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   u16 fdb_id,
-+			   const struct dpsw_fdb_multicast_cfg *cfg);
-+
-+int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io,
-+			      u32 cmd_flags,
-+			      u16 token,
-+			      u16 fdb_id,
-+			      const struct dpsw_fdb_multicast_cfg *cfg);
-+
-+/**
-+ * enum dpsw_fdb_learning_mode - Auto-learning modes
-+ * @DPSW_FDB_LEARNING_MODE_DIS: Disable Auto-learning
-+ * @DPSW_FDB_LEARNING_MODE_HW: Enable HW auto-Learning
-+ * @DPSW_FDB_LEARNING_MODE_NON_SECURE: Enable None secure learning by CPU
-+ * @DPSW_FDB_LEARNING_MODE_SECURE: Enable secure learning by CPU
-+ *
-+ *	NONE - SECURE LEARNING
-+ *	SMAC found	DMAC found	CTLU Action
-+ *	v		v	Forward frame to
-+ *						1.  DMAC destination
-+ *	-		v	Forward frame to
-+ *						1.  DMAC destination
-+ *						2.  Control interface
-+ *	v		-	Forward frame to
-+ *						1.  Flooding list of interfaces
-+ *	-		-	Forward frame to
-+ *						1.  Flooding list of interfaces
-+ *						2.  Control interface
-+ *	SECURE LEARING
-+ *	SMAC found	DMAC found	CTLU Action
-+ *	v		v		Forward frame to
-+ *						1.  DMAC destination
-+ *	-		v		Forward frame to
-+ *						1.  Control interface
-+ *	v		-		Forward frame to
-+ *						1.  Flooding list of interfaces
-+ *	-		-		Forward frame to
-+ *						1.  Control interface
-+ */
-+enum dpsw_fdb_learning_mode {
-+	DPSW_FDB_LEARNING_MODE_DIS = 0,
-+	DPSW_FDB_LEARNING_MODE_HW = 1,
-+	DPSW_FDB_LEARNING_MODE_NON_SECURE = 2,
-+	DPSW_FDB_LEARNING_MODE_SECURE = 3
-+};
-+
-+int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io,
-+			       u32 cmd_flags,
-+			       u16 token,
-+			       u16 fdb_id,
-+			       enum dpsw_fdb_learning_mode mode);
-+
-+/**
-+ * struct dpsw_fdb_attr - FDB Attributes
-+ * @max_fdb_entries: Number of FDB entries
-+ * @fdb_aging_time: Aging time in seconds
-+ * @learning_mode: Learning mode
-+ * @num_fdb_mc_groups: Current number of multicast groups
-+ * @max_fdb_mc_groups: Maximum number of multicast groups
-+ */
-+struct dpsw_fdb_attr {
-+	u16 max_fdb_entries;
-+	u16 fdb_aging_time;
-+	enum dpsw_fdb_learning_mode learning_mode;
-+	u16 num_fdb_mc_groups;
-+	u16 max_fdb_mc_groups;
-+};
-+
-+int dpsw_get_api_version(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 *major_ver,
-+			 u16 *minor_ver);
-+
-+#endif /* __FSL_DPSW_H */
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c
-@@ -0,0 +1,206 @@
-+/* Copyright 2014-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the name of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include "ethsw.h"
-+
-+static struct {
-+	enum dpsw_counter id;
-+	char name[ETH_GSTRING_LEN];
-+} ethsw_ethtool_counters[] =  {
-+	{DPSW_CNT_ING_FRAME,		"rx frames"},
-+	{DPSW_CNT_ING_BYTE,		"rx bytes"},
-+	{DPSW_CNT_ING_FLTR_FRAME,	"rx filtered frames"},
-+	{DPSW_CNT_ING_FRAME_DISCARD,	"rx discarded frames"},
-+	{DPSW_CNT_ING_BCAST_FRAME,	"rx b-cast frames"},
-+	{DPSW_CNT_ING_BCAST_BYTES,	"rx b-cast bytes"},
-+	{DPSW_CNT_ING_MCAST_FRAME,	"rx m-cast frames"},
-+	{DPSW_CNT_ING_MCAST_BYTE,	"rx m-cast bytes"},
-+	{DPSW_CNT_EGR_FRAME,		"tx frames"},
-+	{DPSW_CNT_EGR_BYTE,		"tx bytes"},
-+	{DPSW_CNT_EGR_FRAME_DISCARD,	"tx discarded frames"},
-+
-+};
-+
-+#define ETHSW_NUM_COUNTERS	ARRAY_SIZE(ethsw_ethtool_counters)
-+
-+static void ethsw_get_drvinfo(struct net_device *netdev,
-+			      struct ethtool_drvinfo *drvinfo)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	u16 version_major, version_minor;
-+	int err;
-+
-+	strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
-+
-+	err = dpsw_get_api_version(port_priv->ethsw_data->mc_io, 0,
-+				   &version_major,
-+				   &version_minor);
-+	if (err)
-+		strlcpy(drvinfo->fw_version, "N/A",
-+			sizeof(drvinfo->fw_version));
-+	else
-+		snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
-+			 "%u.%u", version_major, version_minor);
-+
-+	strlcpy(drvinfo->bus_info, dev_name(netdev->dev.parent->parent),
-+		sizeof(drvinfo->bus_info));
-+}
-+
-+static int
-+ethsw_get_link_ksettings(struct net_device *netdev,
-+			 struct ethtool_link_ksettings *link_ksettings)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	struct dpsw_link_state state = {0};
-+	int err = 0;
-+
-+	err = dpsw_if_get_link_state(port_priv->ethsw_data->mc_io, 0,
-+				     port_priv->ethsw_data->dpsw_handle,
-+				     port_priv->idx,
-+				     &state);
-+	if (err) {
-+		netdev_err(netdev, "ERROR %d getting link state", err);
-+		goto out;
-+	}
-+
-+	/* At the moment, we have no way of interrogating the DPMAC
-+	 * from the DPSW side or there may not exist a DPMAC at all.
-+	 * Report only autoneg state, duplexity and speed.
-+	 */
-+	if (state.options & DPSW_LINK_OPT_AUTONEG)
-+		link_ksettings->base.autoneg = AUTONEG_ENABLE;
-+	if (!(state.options & DPSW_LINK_OPT_HALF_DUPLEX))
-+		link_ksettings->base.duplex = DUPLEX_FULL;
-+	link_ksettings->base.speed = state.rate;
-+
-+out:
-+	return err;
-+}
-+
-+static int
-+ethsw_set_link_ksettings(struct net_device *netdev,
-+			 const struct ethtool_link_ksettings *link_ksettings)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	struct dpsw_link_cfg cfg = {0};
-+	int err = 0;
-+
-+	netdev_dbg(netdev, "Setting link parameters...");
-+
-+	/* Due to a temporary MC limitation, the DPSW port must be down
-+	 * in order to be able to change link settings. Taking steps to let
-+	 * the user know that.
-+	 */
-+	if (netif_running(netdev)) {
-+		netdev_info(netdev, "Sorry, interface must be brought down first.\n");
-+		return -EACCES;
-+	}
-+
-+	cfg.rate = link_ksettings->base.speed;
-+	if (link_ksettings->base.autoneg == AUTONEG_ENABLE)
-+		cfg.options |= DPSW_LINK_OPT_AUTONEG;
-+	else
-+		cfg.options &= ~DPSW_LINK_OPT_AUTONEG;
-+	if (link_ksettings->base.duplex  == DUPLEX_HALF)
-+		cfg.options |= DPSW_LINK_OPT_HALF_DUPLEX;
-+	else
-+		cfg.options &= ~DPSW_LINK_OPT_HALF_DUPLEX;
-+
-+	err = dpsw_if_set_link_cfg(port_priv->ethsw_data->mc_io, 0,
-+				   port_priv->ethsw_data->dpsw_handle,
-+				   port_priv->idx,
-+				   &cfg);
-+	if (err)
-+		/* ethtool will be loud enough if we return an error; no point
-+		 * in putting our own error message on the console by default
-+		 */
-+		netdev_dbg(netdev, "ERROR %d setting link cfg", err);
-+
-+	return err;
-+}
-+
-+static int ethsw_ethtool_get_sset_count(struct net_device *dev, int sset)
-+{
-+	switch (sset) {
-+	case ETH_SS_STATS:
-+		return ETHSW_NUM_COUNTERS;
-+	default:
-+		return -EOPNOTSUPP;
-+	}
-+}
-+
-+static void ethsw_ethtool_get_strings(struct net_device *netdev,
-+				      u32 stringset, u8 *data)
-+{
-+	int i;
-+
-+	switch (stringset) {
-+	case ETH_SS_STATS:
-+		for (i = 0; i < ETHSW_NUM_COUNTERS; i++)
-+			memcpy(data + i * ETH_GSTRING_LEN,
-+			       ethsw_ethtool_counters[i].name, ETH_GSTRING_LEN);
-+		break;
-+	}
-+}
-+
-+static void ethsw_ethtool_get_stats(struct net_device *netdev,
-+				    struct ethtool_stats *stats,
-+				    u64 *data)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	int i, err;
-+
-+	memset(data, 0,
-+	       sizeof(u64) * ETHSW_NUM_COUNTERS);
-+
-+	for (i = 0; i < ETHSW_NUM_COUNTERS; i++) {
-+		err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
-+					  port_priv->ethsw_data->dpsw_handle,
-+					  port_priv->idx,
-+					  ethsw_ethtool_counters[i].id,
-+					  &data[i]);
-+		if (err)
-+			netdev_err(netdev, "dpsw_if_get_counter[%s] err %d\n",
-+				   ethsw_ethtool_counters[i].name, err);
-+	}
-+}
-+
-+const struct ethtool_ops ethsw_port_ethtool_ops = {
-+	.get_drvinfo		= ethsw_get_drvinfo,
-+	.get_link		= ethtool_op_get_link,
-+	.get_link_ksettings	= ethsw_get_link_ksettings,
-+	.set_link_ksettings	= ethsw_set_link_ksettings,
-+	.get_strings		= ethsw_ethtool_get_strings,
-+	.get_ethtool_stats	= ethsw_ethtool_get_stats,
-+	.get_sset_count		= ethsw_ethtool_get_sset_count,
-+};
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
-@@ -0,0 +1,1438 @@
-+/* Copyright 2014-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the name of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/module.h>
-+
-+#include <linux/interrupt.h>
-+#include <linux/msi.h>
-+#include <linux/kthread.h>
-+#include <linux/workqueue.h>
-+
-+#include <linux/fsl/mc.h>
-+
-+#include "ethsw.h"
-+
-+static struct workqueue_struct *ethsw_owq;
-+
-+/* Minimal supported DPSW version */
-+#define DPSW_MIN_VER_MAJOR		8
-+#define DPSW_MIN_VER_MINOR		0
-+
-+#define DEFAULT_VLAN_ID			1
-+
-+static int ethsw_add_vlan(struct ethsw_core *ethsw, u16 vid)
-+{
-+	int err;
-+
-+	struct dpsw_vlan_cfg	vcfg = {
-+		.fdb_id = 0,
-+	};
-+
-+	if (ethsw->vlans[vid]) {
-+		dev_err(ethsw->dev, "VLAN already configured\n");
-+		return -EEXIST;
-+	}
-+
-+	err = dpsw_vlan_add(ethsw->mc_io, 0,
-+			    ethsw->dpsw_handle, vid, &vcfg);
-+	if (err) {
-+		dev_err(ethsw->dev, "dpsw_vlan_add err %d\n", err);
-+		return err;
-+	}
-+	ethsw->vlans[vid] = ETHSW_VLAN_MEMBER;
-+
-+	return 0;
-+}
-+
-+static int ethsw_port_set_pvid(struct ethsw_port_priv *port_priv, u16 pvid)
-+{
-+	struct ethsw_core *ethsw = port_priv->ethsw_data;
-+	struct net_device *netdev = port_priv->netdev;
-+	struct dpsw_tci_cfg tci_cfg = { 0 };
-+	bool is_oper;
-+	int err, ret;
-+
-+	err = dpsw_if_get_tci(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+			      port_priv->idx, &tci_cfg);
-+	if (err) {
-+		netdev_err(netdev, "dpsw_if_get_tci err %d\n", err);
-+		return err;
-+	}
-+
-+	tci_cfg.vlan_id = pvid;
-+
-+	/* Interface needs to be down to change PVID */
-+	is_oper = netif_oper_up(netdev);
-+	if (is_oper) {
-+		err = dpsw_if_disable(ethsw->mc_io, 0,
-+				      ethsw->dpsw_handle,
-+				      port_priv->idx);
-+		if (err) {
-+			netdev_err(netdev, "dpsw_if_disable err %d\n", err);
-+			return err;
-+		}
-+	}
-+
-+	err = dpsw_if_set_tci(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+			      port_priv->idx, &tci_cfg);
-+	if (err) {
-+		netdev_err(netdev, "dpsw_if_set_tci err %d\n", err);
-+		goto set_tci_error;
-+	}
-+
-+	/* Delete previous PVID info and mark the new one */
-+	port_priv->vlans[port_priv->pvid] &= ~ETHSW_VLAN_PVID;
-+	port_priv->vlans[pvid] |= ETHSW_VLAN_PVID;
-+	port_priv->pvid = pvid;
-+
-+set_tci_error:
-+	if (is_oper) {
-+		ret = dpsw_if_enable(ethsw->mc_io, 0,
-+				     ethsw->dpsw_handle,
-+				     port_priv->idx);
-+		if (ret) {
-+			netdev_err(netdev, "dpsw_if_enable err %d\n", ret);
-+			return ret;
-+		}
-+	}
-+
-+	return err;
-+}
-+
-+static int ethsw_port_add_vlan(struct ethsw_port_priv *port_priv,
-+			       u16 vid, u16 flags)
-+{
-+	struct ethsw_core *ethsw = port_priv->ethsw_data;
-+	struct net_device *netdev = port_priv->netdev;
-+	struct dpsw_vlan_if_cfg vcfg;
-+	int err;
-+
-+	if (port_priv->vlans[vid]) {
-+		netdev_warn(netdev, "VLAN %d already configured\n", vid);
-+		return -EEXIST;
-+	}
-+
-+	vcfg.num_ifs = 1;
-+	vcfg.if_id[0] = port_priv->idx;
-+	err = dpsw_vlan_add_if(ethsw->mc_io, 0, ethsw->dpsw_handle, vid, &vcfg);
-+	if (err) {
-+		netdev_err(netdev, "dpsw_vlan_add_if err %d\n", err);
-+		return err;
-+	}
-+
-+	port_priv->vlans[vid] = ETHSW_VLAN_MEMBER;
-+
-+	if (flags & BRIDGE_VLAN_INFO_UNTAGGED) {
-+		err = dpsw_vlan_add_if_untagged(ethsw->mc_io, 0,
-+						ethsw->dpsw_handle,
-+						vid, &vcfg);
-+		if (err) {
-+			netdev_err(netdev,
-+				   "dpsw_vlan_add_if_untagged err %d\n", err);
-+			return err;
-+		}
-+		port_priv->vlans[vid] |= ETHSW_VLAN_UNTAGGED;
-+	}
-+
-+	if (flags & BRIDGE_VLAN_INFO_PVID) {
-+		err = ethsw_port_set_pvid(port_priv, vid);
-+		if (err)
-+			return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ethsw_set_learning(struct ethsw_core *ethsw, u8 flag)
-+{
-+	enum dpsw_fdb_learning_mode learn_mode;
-+	int err;
-+
-+	if (flag)
-+		learn_mode = DPSW_FDB_LEARNING_MODE_HW;
-+	else
-+		learn_mode = DPSW_FDB_LEARNING_MODE_DIS;
-+
-+	err = dpsw_fdb_set_learning_mode(ethsw->mc_io, 0, ethsw->dpsw_handle, 0,
-+					 learn_mode);
-+	if (err) {
-+		dev_err(ethsw->dev, "dpsw_fdb_set_learning_mode err %d\n", err);
-+		return err;
-+	}
-+	ethsw->learning = !!flag;
-+
-+	return 0;
-+}
-+
-+static int ethsw_port_set_flood(struct ethsw_port_priv *port_priv, u8 flag)
-+{
-+	int err;
-+
-+	err = dpsw_if_set_flooding(port_priv->ethsw_data->mc_io, 0,
-+				   port_priv->ethsw_data->dpsw_handle,
-+				   port_priv->idx, flag);
-+	if (err) {
-+		netdev_err(port_priv->netdev,
-+			   "dpsw_fdb_set_learning_mode err %d\n", err);
-+		return err;
-+	}
-+	port_priv->flood = !!flag;
-+
-+	return 0;
-+}
-+
-+static int ethsw_port_set_stp_state(struct ethsw_port_priv *port_priv, u8 state)
-+{
-+	struct dpsw_stp_cfg stp_cfg = {
-+		.vlan_id = DEFAULT_VLAN_ID,
-+		.state = state,
-+	};
-+	int err;
-+
-+	if (!netif_oper_up(port_priv->netdev) || state == port_priv->stp_state)
-+		return 0;	/* Nothing to do */
-+
-+	err = dpsw_if_set_stp(port_priv->ethsw_data->mc_io, 0,
-+			      port_priv->ethsw_data->dpsw_handle,
-+			      port_priv->idx, &stp_cfg);
-+	if (err) {
-+		netdev_err(port_priv->netdev,
-+			   "dpsw_if_set_stp err %d\n", err);
-+		return err;
-+	}
-+
-+	port_priv->stp_state = state;
-+
-+	return 0;
-+}
-+
-+static int ethsw_dellink_switch(struct ethsw_core *ethsw, u16 vid)
-+{
-+	struct ethsw_port_priv *ppriv_local = NULL;
-+	int i, err;
-+
-+	if (!ethsw->vlans[vid])
-+		return -ENOENT;
-+
-+	err = dpsw_vlan_remove(ethsw->mc_io, 0, ethsw->dpsw_handle, vid);
-+	if (err) {
-+		dev_err(ethsw->dev, "dpsw_vlan_remove err %d\n", err);
-+		return err;
-+	}
-+	ethsw->vlans[vid] = 0;
-+
-+	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
-+		ppriv_local = ethsw->ports[i];
-+		ppriv_local->vlans[vid] = 0;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ethsw_port_fdb_add_uc(struct ethsw_port_priv *port_priv,
-+				 const unsigned char *addr)
-+{
-+	struct dpsw_fdb_unicast_cfg entry = {0};
-+	int err;
-+
-+	entry.if_egress = port_priv->idx;
-+	entry.type = DPSW_FDB_ENTRY_STATIC;
-+	ether_addr_copy(entry.mac_addr, addr);
-+
-+	err = dpsw_fdb_add_unicast(port_priv->ethsw_data->mc_io, 0,
-+				   port_priv->ethsw_data->dpsw_handle,
-+				   0, &entry);
-+	if (err)
-+		netdev_err(port_priv->netdev,
-+			   "dpsw_fdb_add_unicast err %d\n", err);
-+	return err;
-+}
-+
-+static int ethsw_port_fdb_del_uc(struct ethsw_port_priv *port_priv,
-+				 const unsigned char *addr)
-+{
-+	struct dpsw_fdb_unicast_cfg entry = {0};
-+	int err;
-+
-+	entry.if_egress = port_priv->idx;
-+	entry.type = DPSW_FDB_ENTRY_STATIC;
-+	ether_addr_copy(entry.mac_addr, addr);
-+
-+	err = dpsw_fdb_remove_unicast(port_priv->ethsw_data->mc_io, 0,
-+				      port_priv->ethsw_data->dpsw_handle,
-+				      0, &entry);
-+	/* Silently discard calling multiple times the del command */
-+	if (err && err != -ENXIO)
-+		netdev_err(port_priv->netdev,
-+			   "dpsw_fdb_remove_unicast err %d\n", err);
-+	return err;
-+}
-+
-+static int ethsw_port_fdb_add_mc(struct ethsw_port_priv *port_priv,
-+				 const unsigned char *addr)
-+{
-+	struct dpsw_fdb_multicast_cfg entry = {0};
-+	int err;
-+
-+	ether_addr_copy(entry.mac_addr, addr);
-+	entry.type = DPSW_FDB_ENTRY_STATIC;
-+	entry.num_ifs = 1;
-+	entry.if_id[0] = port_priv->idx;
-+
-+	err = dpsw_fdb_add_multicast(port_priv->ethsw_data->mc_io, 0,
-+				     port_priv->ethsw_data->dpsw_handle,
-+				     0, &entry);
-+	/* Silently discard calling multiple times the add command */
-+	if (err && err != -ENXIO)
-+		netdev_err(port_priv->netdev, "dpsw_fdb_add_multicast err %d\n",
-+			   err);
-+	return err;
-+}
-+
-+static int ethsw_port_fdb_del_mc(struct ethsw_port_priv *port_priv,
-+				 const unsigned char *addr)
-+{
-+	struct dpsw_fdb_multicast_cfg entry = {0};
-+	int err;
-+
-+	ether_addr_copy(entry.mac_addr, addr);
-+	entry.type = DPSW_FDB_ENTRY_STATIC;
-+	entry.num_ifs = 1;
-+	entry.if_id[0] = port_priv->idx;
-+
-+	err = dpsw_fdb_remove_multicast(port_priv->ethsw_data->mc_io, 0,
-+					port_priv->ethsw_data->dpsw_handle,
-+					0, &entry);
-+	/* Silently discard calling multiple times the del command */
-+	if (err && err != -ENAVAIL)
-+		netdev_err(port_priv->netdev,
-+			   "dpsw_fdb_remove_multicast err %d\n", err);
-+	return err;
-+}
-+
-+static void port_get_stats(struct net_device *netdev,
-+			   struct rtnl_link_stats64 *stats)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	u64 tmp;
-+	int err;
-+
-+	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
-+				  port_priv->ethsw_data->dpsw_handle,
-+				  port_priv->idx,
-+				  DPSW_CNT_ING_FRAME, &stats->rx_packets);
-+	if (err)
-+		goto error;
-+
-+	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
-+				  port_priv->ethsw_data->dpsw_handle,
-+				  port_priv->idx,
-+				  DPSW_CNT_EGR_FRAME, &stats->tx_packets);
-+	if (err)
-+		goto error;
-+
-+	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
-+				  port_priv->ethsw_data->dpsw_handle,
-+				  port_priv->idx,
-+				  DPSW_CNT_ING_BYTE, &stats->rx_bytes);
-+	if (err)
-+		goto error;
-+
-+	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
-+				  port_priv->ethsw_data->dpsw_handle,
-+				  port_priv->idx,
-+				  DPSW_CNT_EGR_BYTE, &stats->tx_bytes);
-+	if (err)
-+		goto error;
-+
-+	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
-+				  port_priv->ethsw_data->dpsw_handle,
-+				  port_priv->idx,
-+				  DPSW_CNT_ING_FRAME_DISCARD,
-+				  &stats->rx_dropped);
-+	if (err)
-+		goto error;
-+
-+	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
-+				  port_priv->ethsw_data->dpsw_handle,
-+				  port_priv->idx,
-+				  DPSW_CNT_ING_FLTR_FRAME,
-+				  &tmp);
-+	if (err)
-+		goto error;
-+	stats->rx_dropped += tmp;
-+
-+	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
-+				  port_priv->ethsw_data->dpsw_handle,
-+				  port_priv->idx,
-+				  DPSW_CNT_EGR_FRAME_DISCARD,
-+				  &stats->tx_dropped);
-+	if (err)
-+		goto error;
-+
-+	return;
-+
-+error:
-+	netdev_err(netdev, "dpsw_if_get_counter err %d\n", err);
-+}
-+
-+static bool port_has_offload_stats(const struct net_device *netdev,
-+				   int attr_id)
-+{
-+	return (attr_id == IFLA_OFFLOAD_XSTATS_CPU_HIT);
-+}
-+
-+static int port_get_offload_stats(int attr_id,
-+				  const struct net_device *netdev,
-+				  void *sp)
-+{
-+	switch (attr_id) {
-+	case IFLA_OFFLOAD_XSTATS_CPU_HIT:
-+		port_get_stats((struct net_device *)netdev, sp);
-+		return 0;
-+	}
-+
-+	return -EINVAL;
-+}
-+
-+static int port_change_mtu(struct net_device *netdev, int mtu)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	int err;
-+
-+	err = dpsw_if_set_max_frame_length(port_priv->ethsw_data->mc_io,
-+					   0,
-+					   port_priv->ethsw_data->dpsw_handle,
-+					   port_priv->idx,
-+					   (u16)ETHSW_L2_MAX_FRM(mtu));
-+	if (err) {
-+		netdev_err(netdev,
-+			   "dpsw_if_set_max_frame_length() err %d\n", err);
-+		return err;
-+	}
-+
-+	netdev->mtu = mtu;
-+	return 0;
-+}
-+
-+static int port_carrier_state_sync(struct net_device *netdev)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	struct dpsw_link_state state;
-+	int err;
-+
-+	err = dpsw_if_get_link_state(port_priv->ethsw_data->mc_io, 0,
-+				     port_priv->ethsw_data->dpsw_handle,
-+				     port_priv->idx, &state);
-+	if (err) {
-+		netdev_err(netdev, "dpsw_if_get_link_state() err %d\n", err);
-+		return err;
-+	}
-+
-+	WARN_ONCE(state.up > 1, "Garbage read into link_state");
-+
-+	if (state.up != port_priv->link_state) {
-+		if (state.up)
-+			netif_carrier_on(netdev);
-+		else
-+			netif_carrier_off(netdev);
-+		port_priv->link_state = state.up;
-+	}
-+	return 0;
-+}
-+
-+static int port_open(struct net_device *netdev)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	int err;
-+
-+	/* No need to allow Tx as control interface is disabled */
-+	netif_tx_stop_all_queues(netdev);
-+
-+	err = dpsw_if_enable(port_priv->ethsw_data->mc_io, 0,
-+			     port_priv->ethsw_data->dpsw_handle,
-+			     port_priv->idx);
-+	if (err) {
-+		netdev_err(netdev, "dpsw_if_enable err %d\n", err);
-+		return err;
-+	}
-+
-+	/* sync carrier state */
-+	err = port_carrier_state_sync(netdev);
-+	if (err) {
-+		netdev_err(netdev,
-+			   "port_carrier_state_sync err %d\n", err);
-+		goto err_carrier_sync;
-+	}
-+
-+	return 0;
-+
-+err_carrier_sync:
-+	dpsw_if_disable(port_priv->ethsw_data->mc_io, 0,
-+			port_priv->ethsw_data->dpsw_handle,
-+			port_priv->idx);
-+	return err;
-+}
-+
-+static int port_stop(struct net_device *netdev)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	int err;
-+
-+	err = dpsw_if_disable(port_priv->ethsw_data->mc_io, 0,
-+			      port_priv->ethsw_data->dpsw_handle,
-+			      port_priv->idx);
-+	if (err) {
-+		netdev_err(netdev, "dpsw_if_disable err %d\n", err);
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static netdev_tx_t port_dropframe(struct sk_buff *skb,
-+				  struct net_device *netdev)
-+{
-+	/* we don't support I/O for now, drop the frame */
-+	dev_kfree_skb_any(skb);
-+
-+	return NETDEV_TX_OK;
-+}
-+
-+static const struct net_device_ops ethsw_port_ops = {
-+	.ndo_open		= port_open,
-+	.ndo_stop		= port_stop,
-+
-+	.ndo_set_mac_address	= eth_mac_addr,
-+	.ndo_change_mtu		= port_change_mtu,
-+	.ndo_has_offload_stats	= port_has_offload_stats,
-+	.ndo_get_offload_stats	= port_get_offload_stats,
-+
-+	.ndo_start_xmit		= port_dropframe,
-+};
-+
-+static void ethsw_links_state_update(struct ethsw_core *ethsw)
-+{
-+	int i;
-+
-+	for (i = 0; i < ethsw->sw_attr.num_ifs; i++)
-+		port_carrier_state_sync(ethsw->ports[i]->netdev);
-+}
-+
-+static irqreturn_t ethsw_irq0_handler(int irq_num, void *arg)
-+{
-+	return IRQ_WAKE_THREAD;
-+}
-+
-+static irqreturn_t ethsw_irq0_handler_thread(int irq_num, void *arg)
-+{
-+	struct device *dev = (struct device *)arg;
-+	struct ethsw_core *ethsw = dev_get_drvdata(dev);
-+
-+	/* Mask the events and the if_id reserved bits to be cleared on read */
-+	u32 status = DPSW_IRQ_EVENT_LINK_CHANGED | 0xFFFF0000;
-+	int err;
-+
-+	err = dpsw_get_irq_status(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+				  DPSW_IRQ_INDEX_IF, &status);
-+	if (err) {
-+		dev_err(dev, "Can't get irq status (err %d)", err);
-+
-+		err = dpsw_clear_irq_status(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+					    DPSW_IRQ_INDEX_IF, 0xFFFFFFFF);
-+		if (err)
-+			dev_err(dev, "Can't clear irq status (err %d)", err);
-+		goto out;
-+	}
-+
-+	if (status & DPSW_IRQ_EVENT_LINK_CHANGED)
-+		ethsw_links_state_update(ethsw);
-+
-+out:
-+	return IRQ_HANDLED;
-+}
-+
-+static int ethsw_setup_irqs(struct fsl_mc_device *sw_dev)
-+{
-+	struct device *dev = &sw_dev->dev;
-+	struct ethsw_core *ethsw = dev_get_drvdata(dev);
-+	u32 mask = DPSW_IRQ_EVENT_LINK_CHANGED;
-+	struct fsl_mc_device_irq *irq;
-+	int err;
-+
-+	err = fsl_mc_allocate_irqs(sw_dev);
-+	if (err) {
-+		dev_err(dev, "MC irqs allocation failed\n");
-+		return err;
-+	}
-+
-+	if (WARN_ON(sw_dev->obj_desc.irq_count != DPSW_IRQ_NUM)) {
-+		err = -EINVAL;
-+		goto free_irq;
-+	}
-+
-+	err = dpsw_set_irq_enable(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+				  DPSW_IRQ_INDEX_IF, 0);
-+	if (err) {
-+		dev_err(dev, "dpsw_set_irq_enable err %d\n", err);
-+		goto free_irq;
-+	}
-+
-+	irq = sw_dev->irqs[DPSW_IRQ_INDEX_IF];
-+
-+	err = devm_request_threaded_irq(dev, irq->msi_desc->irq,
-+					ethsw_irq0_handler,
-+					ethsw_irq0_handler_thread,
-+					IRQF_NO_SUSPEND | IRQF_ONESHOT,
-+					dev_name(dev), dev);
-+	if (err) {
-+		dev_err(dev, "devm_request_threaded_irq(): %d", err);
-+		goto free_irq;
-+	}
-+
-+	err = dpsw_set_irq_mask(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+				DPSW_IRQ_INDEX_IF, mask);
-+	if (err) {
-+		dev_err(dev, "dpsw_set_irq_mask(): %d", err);
-+		goto free_devm_irq;
-+	}
-+
-+	err = dpsw_set_irq_enable(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+				  DPSW_IRQ_INDEX_IF, 1);
-+	if (err) {
-+		dev_err(dev, "dpsw_set_irq_enable(): %d", err);
-+		goto free_devm_irq;
-+	}
-+
-+	return 0;
-+
-+free_devm_irq:
-+	devm_free_irq(dev, irq->msi_desc->irq, dev);
-+free_irq:
-+	fsl_mc_free_irqs(sw_dev);
-+	return err;
-+}
-+
-+static void ethsw_teardown_irqs(struct fsl_mc_device *sw_dev)
-+{
-+	struct device *dev = &sw_dev->dev;
-+	struct ethsw_core *ethsw = dev_get_drvdata(dev);
-+	struct fsl_mc_device_irq *irq;
-+	int err;
-+
-+	irq = sw_dev->irqs[DPSW_IRQ_INDEX_IF];
-+	err = dpsw_set_irq_enable(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+				  DPSW_IRQ_INDEX_IF, 0);
-+	if (err)
-+		dev_err(dev, "dpsw_set_irq_enable err %d\n", err);
-+
-+	fsl_mc_free_irqs(sw_dev);
-+}
-+
-+static int swdev_port_attr_get(struct net_device *netdev,
-+			       struct switchdev_attr *attr)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+
-+	switch (attr->id) {
-+	case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
-+		attr->u.ppid.id_len = 1;
-+		attr->u.ppid.id[0] = port_priv->ethsw_data->dev_id;
-+		break;
-+	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
-+		attr->u.brport_flags =
-+			(port_priv->ethsw_data->learning ? BR_LEARNING : 0) |
-+			(port_priv->flood ? BR_FLOOD : 0);
-+		break;
-+	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS_SUPPORT:
-+		attr->u.brport_flags_support = BR_LEARNING | BR_FLOOD;
-+		break;
-+	default:
-+		return -EOPNOTSUPP;
-+	}
-+
-+	return 0;
-+}
-+
-+static int port_attr_stp_state_set(struct net_device *netdev,
-+				   struct switchdev_trans *trans,
-+				   u8 state)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+
-+	if (switchdev_trans_ph_prepare(trans))
-+		return 0;
-+
-+	return ethsw_port_set_stp_state(port_priv, state);
-+}
-+
-+static int port_attr_br_flags_set(struct net_device *netdev,
-+				  struct switchdev_trans *trans,
-+				  unsigned long flags)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	int err = 0;
-+
-+	if (switchdev_trans_ph_prepare(trans))
-+		return 0;
-+
-+	/* Learning is enabled per switch */
-+	err = ethsw_set_learning(port_priv->ethsw_data, !!(flags & BR_LEARNING));
-+	if (err)
-+		goto exit;
-+
-+	err = ethsw_port_set_flood(port_priv, !!(flags & BR_FLOOD));
-+
-+exit:
-+	return err;
-+}
-+
-+static int swdev_port_attr_set(struct net_device *netdev,
-+			       const struct switchdev_attr *attr,
-+			       struct switchdev_trans *trans)
-+{
-+	int err = 0;
-+
-+	switch (attr->id) {
-+	case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
-+		err = port_attr_stp_state_set(netdev, trans,
-+					      attr->u.stp_state);
-+		break;
-+	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
-+		err = port_attr_br_flags_set(netdev, trans,
-+					     attr->u.brport_flags);
-+		break;
-+	case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
-+		/* VLANs are supported by default  */
-+		break;
-+	default:
-+		err = -EOPNOTSUPP;
-+		break;
-+	}
-+
-+	return err;
-+}
-+
-+static int port_vlans_add(struct net_device *netdev,
-+			  const struct switchdev_obj_port_vlan *vlan,
-+			  struct switchdev_trans *trans)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	int vid, err;
-+
-+	if (switchdev_trans_ph_prepare(trans))
-+		return 0;
-+
-+	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
-+		if (!port_priv->ethsw_data->vlans[vid]) {
-+			/* this is a new VLAN */
-+			err = ethsw_add_vlan(port_priv->ethsw_data, vid);
-+			if (err)
-+				return err;
-+
-+			port_priv->ethsw_data->vlans[vid] |= ETHSW_VLAN_GLOBAL;
-+		}
-+		err = ethsw_port_add_vlan(port_priv, vid, vlan->flags);
-+		if (err)
-+			break;
-+	}
-+
-+	return err;
-+}
-+
-+static int swdev_port_obj_add(struct net_device *netdev,
-+			      const struct switchdev_obj *obj,
-+			      struct switchdev_trans *trans)
-+{
-+	int err;
-+
-+	switch (obj->id) {
-+	case SWITCHDEV_OBJ_ID_PORT_VLAN:
-+		err = port_vlans_add(netdev,
-+				     SWITCHDEV_OBJ_PORT_VLAN(obj),
-+				     trans);
-+		break;
-+	default:
-+		err = -EOPNOTSUPP;
-+		break;
-+	}
-+
-+	return err;
-+}
-+
-+static int ethsw_port_del_vlan(struct ethsw_port_priv *port_priv, u16 vid)
-+{
-+	struct ethsw_core *ethsw = port_priv->ethsw_data;
-+	struct net_device *netdev = port_priv->netdev;
-+	struct dpsw_vlan_if_cfg vcfg;
-+	int i, err;
-+
-+	if (!port_priv->vlans[vid])
-+		return -ENOENT;
-+
-+	if (port_priv->vlans[vid] & ETHSW_VLAN_PVID) {
-+		err = ethsw_port_set_pvid(port_priv, 0);
-+		if (err)
-+			return err;
-+	}
-+
-+	vcfg.num_ifs = 1;
-+	vcfg.if_id[0] = port_priv->idx;
-+	if (port_priv->vlans[vid] & ETHSW_VLAN_UNTAGGED) {
-+		err = dpsw_vlan_remove_if_untagged(ethsw->mc_io, 0,
-+						   ethsw->dpsw_handle,
-+						   vid, &vcfg);
-+		if (err) {
-+			netdev_err(netdev,
-+				   "dpsw_vlan_remove_if_untagged err %d\n",
-+				   err);
-+		}
-+		port_priv->vlans[vid] &= ~ETHSW_VLAN_UNTAGGED;
-+	}
-+
-+	if (port_priv->vlans[vid] & ETHSW_VLAN_MEMBER) {
-+		err = dpsw_vlan_remove_if(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+					  vid, &vcfg);
-+		if (err) {
-+			netdev_err(netdev,
-+				   "dpsw_vlan_remove_if err %d\n", err);
-+			return err;
-+		}
-+		port_priv->vlans[vid] &= ~ETHSW_VLAN_MEMBER;
-+
-+		/* Delete VLAN from switch if it is no longer configured on
-+		 * any port
-+		 */
-+		for (i = 0; i < ethsw->sw_attr.num_ifs; i++)
-+			if (ethsw->ports[i]->vlans[vid] & ETHSW_VLAN_MEMBER)
-+				return 0; /* Found a port member in VID */
-+
-+		ethsw->vlans[vid] &= ~ETHSW_VLAN_GLOBAL;
-+
-+		err = ethsw_dellink_switch(ethsw, vid);
-+		if (err)
-+			return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static int port_vlans_del(struct net_device *netdev,
-+			  const struct switchdev_obj_port_vlan *vlan)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+	int vid, err;
-+
-+	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
-+		err = ethsw_port_del_vlan(port_priv, vid);
-+		if (err)
-+			break;
-+	}
-+
-+	return err;
-+}
-+
-+static int swdev_port_obj_del(struct net_device *netdev,
-+			      const struct switchdev_obj *obj)
-+{
-+	int err;
-+
-+	switch (obj->id) {
-+	case SWITCHDEV_OBJ_ID_PORT_VLAN:
-+		err = port_vlans_del(netdev, SWITCHDEV_OBJ_PORT_VLAN(obj));
-+		break;
-+	default:
-+		err = -EOPNOTSUPP;
-+		break;
-+	}
-+	return err;
-+}
-+
-+static const struct switchdev_ops ethsw_port_switchdev_ops = {
-+	.switchdev_port_attr_get	= swdev_port_attr_get,
-+	.switchdev_port_attr_set	= swdev_port_attr_set,
-+	.switchdev_port_obj_add		= swdev_port_obj_add,
-+	.switchdev_port_obj_del		= swdev_port_obj_del,
-+};
-+
-+/* For the moment, only flood setting needs to be updated */
-+static int port_bridge_join(struct net_device *netdev)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+
-+	/* Enable flooding */
-+	return ethsw_port_set_flood(port_priv, 1);
-+}
-+
-+static int port_bridge_leave(struct net_device *netdev)
-+{
-+	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
-+
-+	/* Disable flooding */
-+	return ethsw_port_set_flood(port_priv, 0);
-+}
-+
-+static int port_netdevice_event(struct notifier_block *unused,
-+				unsigned long event, void *ptr)
-+{
-+	struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
-+	struct netdev_notifier_changeupper_info *info = ptr;
-+	struct net_device *upper_dev;
-+	int err = 0;
-+
-+	if (netdev->netdev_ops != &ethsw_port_ops)
-+		return NOTIFY_DONE;
-+
-+	/* Handle just upper dev link/unlink for the moment */
-+	if (event == NETDEV_CHANGEUPPER) {
-+		upper_dev = info->upper_dev;
-+		if (netif_is_bridge_master(upper_dev)) {
-+			if (info->linking)
-+				err = port_bridge_join(netdev);
-+			else
-+				err = port_bridge_leave(netdev);
-+		}
-+	}
-+
-+	return notifier_from_errno(err);
-+}
-+
-+static struct notifier_block port_nb __read_mostly = {
-+	.notifier_call = port_netdevice_event,
-+};
-+
-+struct ethsw_switchdev_event_work {
-+	struct work_struct work;
-+	struct switchdev_notifier_fdb_info fdb_info;
-+	struct net_device *dev;
-+	unsigned long event;
-+};
-+
-+static void ethsw_switchdev_event_work(struct work_struct *work)
-+{
-+	struct ethsw_switchdev_event_work *switchdev_work =
-+		container_of(work, struct ethsw_switchdev_event_work, work);
-+	struct net_device *dev = switchdev_work->dev;
-+	struct switchdev_notifier_fdb_info *fdb_info;
-+	struct ethsw_port_priv *port_priv;
-+
-+	rtnl_lock();
-+	port_priv = netdev_priv(dev);
-+	fdb_info = &switchdev_work->fdb_info;
-+
-+	switch (switchdev_work->event) {
-+	case SWITCHDEV_FDB_ADD_TO_DEVICE:
-+		if (is_unicast_ether_addr(fdb_info->addr))
-+			ethsw_port_fdb_add_uc(netdev_priv(dev), fdb_info->addr);
-+		else
-+			ethsw_port_fdb_add_mc(netdev_priv(dev), fdb_info->addr);
-+		break;
-+	case SWITCHDEV_FDB_DEL_TO_DEVICE:
-+		if (is_unicast_ether_addr(fdb_info->addr))
-+			ethsw_port_fdb_del_uc(netdev_priv(dev), fdb_info->addr);
-+		else
-+			ethsw_port_fdb_del_mc(netdev_priv(dev), fdb_info->addr);
-+		break;
-+	}
-+
-+	rtnl_unlock();
-+	kfree(switchdev_work->fdb_info.addr);
-+	kfree(switchdev_work);
-+	dev_put(dev);
-+}
-+
-+/* Called under rcu_read_lock() */
-+static int port_switchdev_event(struct notifier_block *unused,
-+				unsigned long event, void *ptr)
-+{
-+	struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
-+	struct ethsw_switchdev_event_work *switchdev_work;
-+	struct switchdev_notifier_fdb_info *fdb_info = ptr;
-+
-+	switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);
-+	if (!switchdev_work)
-+		return NOTIFY_BAD;
-+
-+	INIT_WORK(&switchdev_work->work, ethsw_switchdev_event_work);
-+	switchdev_work->dev = dev;
-+	switchdev_work->event = event;
-+
-+	switch (event) {
-+	case SWITCHDEV_FDB_ADD_TO_DEVICE:
-+	case SWITCHDEV_FDB_DEL_TO_DEVICE:
-+		memcpy(&switchdev_work->fdb_info, ptr,
-+		       sizeof(switchdev_work->fdb_info));
-+		switchdev_work->fdb_info.addr = kzalloc(ETH_ALEN, GFP_ATOMIC);
-+		if (!switchdev_work->fdb_info.addr)
-+			goto err_addr_alloc;
-+
-+		ether_addr_copy((u8 *)switchdev_work->fdb_info.addr,
-+				fdb_info->addr);
-+
-+		/* Take a reference on the device to avoid being freed. */
-+		dev_hold(dev);
-+		break;
-+	default:
-+		return NOTIFY_DONE;
-+	}
-+
-+	queue_work(ethsw_owq, &switchdev_work->work);
-+
-+	return NOTIFY_DONE;
-+
-+err_addr_alloc:
-+	kfree(switchdev_work);
-+	return NOTIFY_BAD;
-+}
-+
-+static struct notifier_block port_switchdev_nb = {
-+	.notifier_call = port_switchdev_event,
-+};
-+
-+static int ethsw_register_notifier(struct device *dev)
-+{
-+	int err;
-+
-+	err = register_netdevice_notifier(&port_nb);
-+	if (err) {
-+		dev_err(dev, "Failed to register netdev notifier\n");
-+		return err;
-+	}
-+
-+	err = register_switchdev_notifier(&port_switchdev_nb);
-+	if (err) {
-+		dev_err(dev, "Failed to register switchdev notifier\n");
-+		goto err_switchdev_nb;
-+	}
-+
-+	return 0;
-+
-+err_switchdev_nb:
-+	unregister_netdevice_notifier(&port_nb);
-+	return err;
-+}
-+
-+static int ethsw_open(struct ethsw_core *ethsw)
-+{
-+	struct ethsw_port_priv *port_priv = NULL;
-+	int i, err;
-+
-+	err = dpsw_enable(ethsw->mc_io, 0, ethsw->dpsw_handle);
-+	if (err) {
-+		dev_err(ethsw->dev, "dpsw_enable err %d\n", err);
-+		return err;
-+	}
-+
-+	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
-+		port_priv = ethsw->ports[i];
-+		err = dev_open(port_priv->netdev);
-+		if (err) {
-+			netdev_err(port_priv->netdev, "dev_open err %d\n", err);
-+			return err;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int ethsw_stop(struct ethsw_core *ethsw)
-+{
-+	struct ethsw_port_priv *port_priv = NULL;
-+	int i, err;
-+
-+	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
-+		port_priv = ethsw->ports[i];
-+		dev_close(port_priv->netdev);
-+	}
-+
-+	err = dpsw_disable(ethsw->mc_io, 0, ethsw->dpsw_handle);
-+	if (err) {
-+		dev_err(ethsw->dev, "dpsw_disable err %d\n", err);
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static int ethsw_init(struct fsl_mc_device *sw_dev)
-+{
-+	struct device *dev = &sw_dev->dev;
-+	struct ethsw_core *ethsw = dev_get_drvdata(dev);
-+	u16 version_major, version_minor, i;
-+	struct dpsw_stp_cfg stp_cfg;
-+	int err;
-+
-+	ethsw->dev_id = sw_dev->obj_desc.id;
-+
-+	err = dpsw_open(ethsw->mc_io, 0, ethsw->dev_id, &ethsw->dpsw_handle);
-+	if (err) {
-+		dev_err(dev, "dpsw_open err %d\n", err);
-+		return err;
-+	}
-+
-+	err = dpsw_get_attributes(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+				  &ethsw->sw_attr);
-+	if (err) {
-+		dev_err(dev, "dpsw_get_attributes err %d\n", err);
-+		goto err_close;
-+	}
-+
-+	err = dpsw_get_api_version(ethsw->mc_io, 0,
-+				   &version_major,
-+				   &version_minor);
-+	if (err) {
-+		dev_err(dev, "dpsw_get_api_version err %d\n", err);
-+		goto err_close;
-+	}
-+
-+	/* Minimum supported DPSW version check */
-+	if (version_major < DPSW_MIN_VER_MAJOR ||
-+	    (version_major == DPSW_MIN_VER_MAJOR &&
-+	     version_minor < DPSW_MIN_VER_MINOR)) {
-+		dev_err(dev, "DPSW version %d:%d not supported. Use %d.%d or greater.\n",
-+			version_major,
-+			version_minor,
-+			DPSW_MIN_VER_MAJOR, DPSW_MIN_VER_MINOR);
-+		err = -ENOTSUPP;
-+		goto err_close;
-+	}
-+
-+	err = dpsw_reset(ethsw->mc_io, 0, ethsw->dpsw_handle);
-+	if (err) {
-+		dev_err(dev, "dpsw_reset err %d\n", err);
-+		goto err_close;
-+	}
-+
-+	err = dpsw_fdb_set_learning_mode(ethsw->mc_io, 0, ethsw->dpsw_handle, 0,
-+					 DPSW_FDB_LEARNING_MODE_HW);
-+	if (err) {
-+		dev_err(dev, "dpsw_fdb_set_learning_mode err %d\n", err);
-+		goto err_close;
-+	}
-+
-+	stp_cfg.vlan_id = DEFAULT_VLAN_ID;
-+	stp_cfg.state = DPSW_STP_STATE_FORWARDING;
-+
-+	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
-+		err = dpsw_if_set_stp(ethsw->mc_io, 0, ethsw->dpsw_handle, i,
-+				      &stp_cfg);
-+		if (err) {
-+			dev_err(dev, "dpsw_if_set_stp err %d for port %d\n",
-+				err, i);
-+			goto err_close;
-+		}
-+
-+		err = dpsw_if_set_broadcast(ethsw->mc_io, 0,
-+					    ethsw->dpsw_handle, i, 1);
-+		if (err) {
-+			dev_err(dev,
-+				"dpsw_if_set_broadcast err %d for port %d\n",
-+				err, i);
-+			goto err_close;
-+		}
-+	}
-+
-+	ethsw_owq = alloc_ordered_workqueue("%s_ordered", WQ_MEM_RECLAIM,
-+					    "ethsw");
-+	if (!ethsw_owq) {
-+		err = -ENOMEM;
-+		goto err_close;
-+	}
-+
-+	err = ethsw_register_notifier(dev);
-+	if (err)
-+		goto err_destroy_ordered_workqueue;
-+
-+	return 0;
-+
-+err_destroy_ordered_workqueue:
-+	destroy_workqueue(ethsw_owq);
-+
-+err_close:
-+	dpsw_close(ethsw->mc_io, 0, ethsw->dpsw_handle);
-+	return err;
-+}
-+
-+static int ethsw_port_init(struct ethsw_port_priv *port_priv, u16 port)
-+{
-+	const char def_mcast[ETH_ALEN] = {0x01, 0x00, 0x5e, 0x00, 0x00, 0x01};
-+	struct net_device *netdev = port_priv->netdev;
-+	struct ethsw_core *ethsw = port_priv->ethsw_data;
-+	struct dpsw_vlan_if_cfg vcfg;
-+	int err;
-+
-+	/* Switch starts with all ports configured to VLAN 1. Need to
-+	 * remove this setting to allow configuration at bridge join
-+	 */
-+	vcfg.num_ifs = 1;
-+	vcfg.if_id[0] = port_priv->idx;
-+
-+	err = dpsw_vlan_remove_if_untagged(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+					   DEFAULT_VLAN_ID, &vcfg);
-+	if (err) {
-+		netdev_err(netdev, "dpsw_vlan_remove_if_untagged err %d\n",
-+			   err);
-+		return err;
-+	}
-+
-+	err = ethsw_port_set_pvid(port_priv, 0);
-+	if (err)
-+		return err;
-+
-+	err = dpsw_vlan_remove_if(ethsw->mc_io, 0, ethsw->dpsw_handle,
-+				  DEFAULT_VLAN_ID, &vcfg);
-+	if (err) {
-+		netdev_err(netdev, "dpsw_vlan_remove_if err %d\n", err);
-+		return err;
-+	}
-+
-+	err = ethsw_port_fdb_add_mc(port_priv, def_mcast);
-+
-+	return err;
-+}
-+
-+static void ethsw_unregister_notifier(struct device *dev)
-+{
-+	int err;
-+
-+	err = unregister_switchdev_notifier(&port_switchdev_nb);
-+	if (err)
-+		dev_err(dev,
-+			"Failed to unregister switchdev notifier (%d)\n", err);
-+
-+	err = unregister_netdevice_notifier(&port_nb);
-+	if (err)
-+		dev_err(dev,
-+			"Failed to unregister netdev notifier (%d)\n", err);
-+}
-+
-+static void ethsw_takedown(struct fsl_mc_device *sw_dev)
-+{
-+	struct device *dev = &sw_dev->dev;
-+	struct ethsw_core *ethsw = dev_get_drvdata(dev);
-+	int err;
-+
-+	ethsw_unregister_notifier(dev);
-+
-+	err = dpsw_close(ethsw->mc_io, 0, ethsw->dpsw_handle);
-+	if (err)
-+		dev_warn(dev, "dpsw_close err %d\n", err);
-+}
-+
-+static int ethsw_remove(struct fsl_mc_device *sw_dev)
-+{
-+	struct ethsw_port_priv *port_priv;
-+	struct ethsw_core *ethsw;
-+	struct device *dev;
-+	int i;
-+
-+	dev = &sw_dev->dev;
-+	ethsw = dev_get_drvdata(dev);
-+
-+	ethsw_teardown_irqs(sw_dev);
-+
-+	destroy_workqueue(ethsw_owq);
-+
-+	rtnl_lock();
-+	ethsw_stop(ethsw);
-+	rtnl_unlock();
-+
-+	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
-+		port_priv = ethsw->ports[i];
-+		unregister_netdev(port_priv->netdev);
-+		free_netdev(port_priv->netdev);
-+	}
-+	kfree(ethsw->ports);
-+
-+	ethsw_takedown(sw_dev);
-+	fsl_mc_portal_free(ethsw->mc_io);
-+
-+	kfree(ethsw);
-+
-+	dev_set_drvdata(dev, NULL);
-+
-+	return 0;
-+}
-+
-+static int ethsw_probe_port(struct ethsw_core *ethsw, u16 port_idx)
-+{
-+	struct ethsw_port_priv *port_priv;
-+	struct device *dev = ethsw->dev;
-+	struct net_device *port_netdev;
-+	int err;
-+
-+	port_netdev = alloc_etherdev(sizeof(struct ethsw_port_priv));
-+	if (!port_netdev) {
-+		dev_err(dev, "alloc_etherdev error\n");
-+		return -ENOMEM;
-+	}
-+
-+	port_priv = netdev_priv(port_netdev);
-+	port_priv->netdev = port_netdev;
-+	port_priv->ethsw_data = ethsw;
-+
-+	port_priv->idx = port_idx;
-+	port_priv->stp_state = BR_STATE_FORWARDING;
-+
-+	/* Flooding is implicitly enabled */
-+	port_priv->flood = true;
-+
-+	SET_NETDEV_DEV(port_netdev, dev);
-+	port_netdev->netdev_ops = &ethsw_port_ops;
-+	port_netdev->ethtool_ops = &ethsw_port_ethtool_ops;
-+	port_netdev->switchdev_ops = &ethsw_port_switchdev_ops;
-+
-+	/* Set MTU limits */
-+	port_netdev->min_mtu = ETH_MIN_MTU;
-+	port_netdev->max_mtu = ETHSW_MAX_FRAME_LENGTH;
-+
-+	err = register_netdev(port_netdev);
-+	if (err < 0) {
-+		dev_err(dev, "register_netdev error %d\n", err);
-+			free_netdev(port_netdev);
-+			return err;
-+		}
-+
-+	ethsw->ports[port_idx] = port_priv;
-+
-+	return ethsw_port_init(port_priv, port_idx);
-+}
-+
-+static int ethsw_probe(struct fsl_mc_device *sw_dev)
-+{
-+	struct device *dev = &sw_dev->dev;
-+	struct ethsw_core *ethsw;
-+	int i, err;
-+
-+	/* Allocate switch core*/
-+	ethsw = kzalloc(sizeof(*ethsw), GFP_KERNEL);
-+
-+	if (!ethsw)
-+		return -ENOMEM;
-+
-+	ethsw->dev = dev;
-+	dev_set_drvdata(dev, ethsw);
-+
-+	err = fsl_mc_portal_allocate(sw_dev, 0, &ethsw->mc_io);
-+	if (err) {
-+		dev_err(dev, "fsl_mc_portal_allocate err %d\n", err);
-+		goto err_free_drvdata;
-+	}
-+
-+	err = ethsw_init(sw_dev);
-+	if (err)
-+		goto err_free_cmdport;
-+
-+	/* DEFAULT_VLAN_ID is implicitly configured on the switch */
-+	ethsw->vlans[DEFAULT_VLAN_ID] = ETHSW_VLAN_MEMBER;
-+
-+	/* Learning is implicitly enabled */
-+	ethsw->learning = true;
-+
-+	ethsw->ports = kcalloc(ethsw->sw_attr.num_ifs, sizeof(*ethsw->ports),
-+			       GFP_KERNEL);
-+	if (!(ethsw->ports)) {
-+		err = -ENOMEM;
-+		goto err_takedown;
-+	}
-+
-+	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
-+		err = ethsw_probe_port(ethsw, i);
-+		if (err)
-+			goto err_free_ports;
-+	}
-+
-+	/* Switch starts up enabled */
-+	rtnl_lock();
-+	err = ethsw_open(ethsw);
-+	rtnl_unlock();
-+	if (err)
-+		goto err_free_ports;
-+
-+	/* Setup IRQs */
-+	err = ethsw_setup_irqs(sw_dev);
-+	if (err)
-+		goto err_stop;
-+
-+	dev_info(dev, "probed %d port switch\n", ethsw->sw_attr.num_ifs);
-+	return 0;
-+
-+err_stop:
-+	rtnl_lock();
-+	ethsw_stop(ethsw);
-+	rtnl_unlock();
-+
-+err_free_ports:
-+	/* Cleanup registered ports only */
-+	for (i--; i >= 0; i--) {
-+		unregister_netdev(ethsw->ports[i]->netdev);
-+		free_netdev(ethsw->ports[i]->netdev);
-+	}
-+	kfree(ethsw->ports);
-+
-+err_takedown:
-+	ethsw_takedown(sw_dev);
-+
-+err_free_cmdport:
-+	fsl_mc_portal_free(ethsw->mc_io);
-+
-+err_free_drvdata:
-+	kfree(ethsw);
-+	dev_set_drvdata(dev, NULL);
-+
-+	return err;
-+}
-+
-+static const struct fsl_mc_device_id ethsw_match_id_table[] = {
-+	{
-+		.vendor = FSL_MC_VENDOR_FREESCALE,
-+		.obj_type = "dpsw",
-+	},
-+	{ .vendor = 0x0 }
-+};
-+MODULE_DEVICE_TABLE(fslmc, ethsw_match_id_table);
-+
-+static struct fsl_mc_driver eth_sw_drv = {
-+	.driver = {
-+		.name = KBUILD_MODNAME,
-+		.owner = THIS_MODULE,
-+	},
-+	.probe = ethsw_probe,
-+	.remove = ethsw_remove,
-+	.match_id_table = ethsw_match_id_table
-+};
-+
-+module_fsl_mc_driver(eth_sw_drv);
-+
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("DPAA2 Ethernet Switch Driver");
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/ethsw/ethsw.h
-@@ -0,0 +1,90 @@
-+/* Copyright 2014-2017 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the name of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef __ETHSW_H
-+#define __ETHSW_H
-+
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/rtnetlink.h>
-+#include <linux/if_vlan.h>
-+#include <uapi/linux/if_bridge.h>
-+#include <net/switchdev.h>
-+#include <linux/if_bridge.h>
-+
-+#include "dpsw.h"
-+
-+/* Number of IRQs supported */
-+#define DPSW_IRQ_NUM	2
-+
-+#define ETHSW_VLAN_MEMBER	1
-+#define ETHSW_VLAN_UNTAGGED	2
-+#define ETHSW_VLAN_PVID		4
-+#define ETHSW_VLAN_GLOBAL	8
-+
-+/* Maximum Frame Length supported by HW (currently 10k) */
-+#define DPAA2_MFL		(10 * 1024)
-+#define ETHSW_MAX_FRAME_LENGTH	(DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN)
-+#define ETHSW_L2_MAX_FRM(mtu)	((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN)
-+
-+extern const struct ethtool_ops ethsw_port_ethtool_ops;
-+
-+struct ethsw_core;
-+
-+/* Per port private data */
-+struct ethsw_port_priv {
-+	struct net_device	*netdev;
-+	u16			idx;
-+	struct ethsw_core	*ethsw_data;
-+	u8			link_state;
-+	u8			stp_state;
-+	bool			flood;
-+
-+	u8			vlans[VLAN_VID_MASK + 1];
-+	u16			pvid;
-+};
-+
-+/* Switch data */
-+struct ethsw_core {
-+	struct device			*dev;
-+	struct fsl_mc_io		*mc_io;
-+	u16				dpsw_handle;
-+	struct dpsw_attr		sw_attr;
-+	int				dev_id;
-+	struct ethsw_port_priv		**ports;
-+
-+	u8				vlans[VLAN_VID_MASK + 1];
-+	bool				learning;
-+};
-+
-+#endif	/* __ETHSW_H */
diff --git a/target/linux/layerscape/patches-4.14/704-dpaa2-mac-phy-support-layerscape.patch b/target/linux/layerscape/patches-4.14/704-dpaa2-mac-phy-support-layerscape.patch
deleted file mode 100644
index d76c5abe5..000000000
--- a/target/linux/layerscape/patches-4.14/704-dpaa2-mac-phy-support-layerscape.patch
+++ /dev/null
@@ -1,1888 +0,0 @@
-From 92cf25fe454dd42136e717ba679a9dba740db0e7 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:18 +0800
-Subject: [PATCH 10/40] dpaa2-mac-phy: support layerscape
-This is an integrated patch of dpaa2-mac-phy for
- layerscape
-
-Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
-Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
-Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
-Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-Signed-off-by: Itai Katz <itai.katz@freescale.com>
-Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
-Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
-Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/staging/fsl-dpaa2/mac/Kconfig     |  23 +
- drivers/staging/fsl-dpaa2/mac/Makefile    |  10 +
- drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h | 172 ++++++
- drivers/staging/fsl-dpaa2/mac/dpmac.c     | 619 ++++++++++++++++++++
- drivers/staging/fsl-dpaa2/mac/dpmac.h     | 342 +++++++++++
- drivers/staging/fsl-dpaa2/mac/mac.c       | 672 ++++++++++++++++++++++
- 6 files changed, 1838 insertions(+)
- create mode 100644 drivers/staging/fsl-dpaa2/mac/Kconfig
- create mode 100644 drivers/staging/fsl-dpaa2/mac/Makefile
- create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h
- create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac.c
- create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac.h
- create mode 100644 drivers/staging/fsl-dpaa2/mac/mac.c
-
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/mac/Kconfig
-@@ -0,0 +1,23 @@
-+config FSL_DPAA2_MAC
-+	tristate "DPAA2 MAC / PHY interface"
-+	depends on FSL_MC_BUS && FSL_DPAA2
-+	select MDIO_BUS_MUX_MMIOREG
-+	select FSL_XGMAC_MDIO
-+	select FIXED_PHY
-+	---help---
-+	Prototype driver for DPAA2 MAC / PHY interface object.
-+	This driver works as a proxy between phylib including phy drivers and
-+	the MC firmware.  It receives updates on link state changes from PHY
-+	lib and forwards them to MC and receives interrupt from MC whenever
-+	a request is made to change the link state.
-+
-+
-+config FSL_DPAA2_MAC_NETDEVS
-+	bool "Expose net interfaces for PHYs"
-+	default n
-+	depends on FSL_DPAA2_MAC
-+	---help---
-+	Exposes macX net interfaces which allow direct control over MACs and
-+	PHYs.
-+	.
-+	Leave disabled if unsure.
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/mac/Makefile
-@@ -0,0 +1,10 @@
-+
-+obj-$(CONFIG_FSL_DPAA2_MAC) += dpaa2-mac.o
-+
-+dpaa2-mac-objs := mac.o dpmac.o
-+
-+all:
-+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
-+
-+clean:
-+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h
-@@ -0,0 +1,172 @@
-+/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#ifndef _FSL_DPMAC_CMD_H
-+#define _FSL_DPMAC_CMD_H
-+
-+/* DPMAC Version */
-+#define DPMAC_VER_MAJOR				4
-+#define DPMAC_VER_MINOR				2
-+#define DPMAC_CMD_BASE_VERSION			1
-+#define DPMAC_CMD_ID_OFFSET			4
-+
-+#define DPMAC_CMD(id)	(((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_BASE_VERSION)
-+
-+/* Command IDs */
-+#define DPMAC_CMDID_CLOSE		DPMAC_CMD(0x800)
-+#define DPMAC_CMDID_OPEN		DPMAC_CMD(0x80c)
-+#define DPMAC_CMDID_CREATE		DPMAC_CMD(0x90c)
-+#define DPMAC_CMDID_DESTROY		DPMAC_CMD(0x98c)
-+#define DPMAC_CMDID_GET_API_VERSION	DPMAC_CMD(0xa0c)
-+
-+#define DPMAC_CMDID_GET_ATTR		DPMAC_CMD(0x004)
-+#define DPMAC_CMDID_RESET		DPMAC_CMD(0x005)
-+
-+#define DPMAC_CMDID_SET_IRQ_ENABLE	DPMAC_CMD(0x012)
-+#define DPMAC_CMDID_GET_IRQ_ENABLE	DPMAC_CMD(0x013)
-+#define DPMAC_CMDID_SET_IRQ_MASK	DPMAC_CMD(0x014)
-+#define DPMAC_CMDID_GET_IRQ_MASK	DPMAC_CMD(0x015)
-+#define DPMAC_CMDID_GET_IRQ_STATUS	DPMAC_CMD(0x016)
-+#define DPMAC_CMDID_CLEAR_IRQ_STATUS	DPMAC_CMD(0x017)
-+
-+#define DPMAC_CMDID_GET_LINK_CFG	DPMAC_CMD(0x0c2)
-+#define DPMAC_CMDID_SET_LINK_STATE	DPMAC_CMD(0x0c3)
-+#define DPMAC_CMDID_GET_COUNTER		DPMAC_CMD(0x0c4)
-+
-+#define DPMAC_CMDID_SET_PORT_MAC_ADDR	DPMAC_CMD(0x0c5)
-+
-+/* Macros for accessing command fields smaller than 1byte */
-+#define DPMAC_MASK(field)        \
-+	GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \
-+		DPMAC_##field##_SHIFT)
-+#define dpmac_set_field(var, field, val) \
-+	((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field)))
-+#define dpmac_get_field(var, field)      \
-+	(((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT)
-+
-+struct dpmac_cmd_open {
-+	u32 dpmac_id;
-+};
-+
-+struct dpmac_cmd_create {
-+	u32 mac_id;
-+};
-+
-+struct dpmac_cmd_destroy {
-+	u32 dpmac_id;
-+};
-+
-+struct dpmac_cmd_set_irq_enable {
-+	u8 enable;
-+	u8 pad[3];
-+	u8 irq_index;
-+};
-+
-+struct dpmac_cmd_get_irq_enable {
-+	u32 pad;
-+	u8 irq_index;
-+};
-+
-+struct dpmac_rsp_get_irq_enable {
-+	u8 enabled;
-+};
-+
-+struct dpmac_cmd_set_irq_mask {
-+	u32 mask;
-+	u8 irq_index;
-+};
-+
-+struct dpmac_cmd_get_irq_mask {
-+	u32 pad;
-+	u8 irq_index;
-+};
-+
-+struct dpmac_rsp_get_irq_mask {
-+	u32 mask;
-+};
-+
-+struct dpmac_cmd_get_irq_status {
-+	u32 status;
-+	u8 irq_index;
-+};
-+
-+struct dpmac_rsp_get_irq_status {
-+	u32 status;
-+};
-+
-+struct dpmac_cmd_clear_irq_status {
-+	u32 status;
-+	u8 irq_index;
-+};
-+
-+struct dpmac_rsp_get_attributes {
-+	u8 eth_if;
-+	u8 link_type;
-+	u16 id;
-+	u32 max_rate;
-+};
-+
-+struct dpmac_rsp_get_link_cfg {
-+	u64 options;
-+	u32 rate;
-+};
-+
-+#define DPMAC_STATE_SIZE	1
-+#define DPMAC_STATE_SHIFT	0
-+
-+struct dpmac_cmd_set_link_state {
-+	u64 options;
-+	u32 rate;
-+	u32 pad;
-+	/* only least significant bit is valid */
-+	u8 up;
-+};
-+
-+struct dpmac_cmd_get_counter {
-+	u8 type;
-+};
-+
-+struct dpmac_rsp_get_counter {
-+	u64 pad;
-+	u64 counter;
-+};
-+
-+struct dpmac_rsp_get_api_version {
-+	u16 major;
-+	u16 minor;
-+};
-+
-+struct dpmac_cmd_set_port_mac_addr {
-+	u8 pad[2];
-+	u8 addr[6];
-+};
-+
-+#endif /* _FSL_DPMAC_CMD_H */
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/mac/dpmac.c
-@@ -0,0 +1,619 @@
-+/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#include <linux/fsl/mc.h>
-+#include "dpmac.h"
-+#include "dpmac-cmd.h"
-+
-+/**
-+ * dpmac_open() - Open a control session for the specified object.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @dpmac_id:	DPMAC unique ID
-+ * @token:	Returned token; use in subsequent API calls
-+ *
-+ * This function can be used to open a control session for an
-+ * already created object; an object may have been declared in
-+ * the DPL or by calling the dpmac_create function.
-+ * This function returns a unique authentication token,
-+ * associated with the specific object ID and the specific MC
-+ * portal; this token must be used in all subsequent commands for
-+ * this specific object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_open(struct fsl_mc_io *mc_io,
-+	       u32 cmd_flags,
-+	       int dpmac_id,
-+	       u16 *token)
-+{
-+	struct dpmac_cmd_open *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN,
-+					  cmd_flags,
-+					  0);
-+	cmd_params = (struct dpmac_cmd_open *)cmd.params;
-+	cmd_params->dpmac_id = cpu_to_le32(dpmac_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	*token = mc_cmd_hdr_read_token(&cmd);
-+
-+	return err;
-+}
-+
-+/**
-+ * dpmac_close() - Close the control session of the object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ *
-+ * After this function is called, no further operations are
-+ * allowed on the object without opening a new control session.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_close(struct fsl_mc_io *mc_io,
-+		u32 cmd_flags,
-+		u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpmac_create() - Create the DPMAC object.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @dprc_token: Parent container token; '0' for default container
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @cfg:	Configuration structure
-+ * @obj_id:	Returned object id
-+ *
-+ * Create the DPMAC object, allocate required resources and
-+ * perform required initialization.
-+ *
-+ * The function accepts an authentication token of a parent
-+ * container that this object should be assigned to. The token
-+ * can be '0' so the object will be assigned to the default container.
-+ * The newly created object can be opened with the returned
-+ * object id and using the container's associated tokens and MC portals.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_create(struct fsl_mc_io *mc_io,
-+		 u16 dprc_token,
-+		 u32 cmd_flags,
-+		 const struct dpmac_cfg *cfg,
-+		 u32 *obj_id)
-+{
-+	struct dpmac_cmd_create *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE,
-+					  cmd_flags,
-+					  dprc_token);
-+	cmd_params = (struct dpmac_cmd_create *)cmd.params;
-+	cmd_params->mac_id = cpu_to_le32(cfg->mac_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	*obj_id = mc_cmd_read_object_id(&cmd);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpmac_destroy() - Destroy the DPMAC object and release all its resources.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @dprc_token: Parent container token; '0' for default container
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @object_id:	The object id; it must be a valid id within the container that
-+ * created this object;
-+ *
-+ * The function accepts the authentication token of the parent container that
-+ * created the object (not the one that currently owns the object). The object
-+ * is searched within parent using the provided 'object_id'.
-+ * All tokens to the object must be closed before calling destroy.
-+ *
-+ * Return:	'0' on Success; error code otherwise.
-+ */
-+int dpmac_destroy(struct fsl_mc_io *mc_io,
-+		  u16 dprc_token,
-+		  u32 cmd_flags,
-+		  u32 object_id)
-+{
-+	struct dpmac_cmd_destroy *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY,
-+					  cmd_flags,
-+					  dprc_token);
-+	cmd_params = (struct dpmac_cmd_destroy *)cmd.params;
-+	cmd_params->dpmac_id = cpu_to_le32(object_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpmac_set_irq_enable() - Set overall interrupt state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Interrupt state - enable = 1, disable = 0
-+ *
-+ * Allows GPP software to control when interrupts are generated.
-+ * Each interrupt can have up to 32 causes.  The enable/disable control's the
-+ * overall interrupt state. if the interrupt is disabled no causes will cause
-+ * an interrupt.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_set_irq_enable(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u8 irq_index,
-+			 u8 en)
-+{
-+	struct dpmac_cmd_set_irq_enable *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpmac_cmd_set_irq_enable *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+	cmd_params->enable = en;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpmac_get_irq_enable() - Get overall interrupt state
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Returned interrupt state - enable = 1, disable = 0
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_get_irq_enable(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u8 irq_index,
-+			 u8 *en)
-+{
-+	struct dpmac_cmd_get_irq_enable *cmd_params;
-+	struct dpmac_rsp_get_irq_enable *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpmac_cmd_get_irq_enable *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpmac_rsp_get_irq_enable *)cmd.params;
-+	*en = rsp_params->enabled;
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpmac_set_irq_mask() - Set interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	Event mask to trigger interrupt;
-+ *		each bit:
-+ *			0 = ignore event
-+ *			1 = consider event for asserting IRQ
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_set_irq_mask(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       u8 irq_index,
-+		       u32 mask)
-+{
-+	struct dpmac_cmd_set_irq_mask *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpmac_cmd_set_irq_mask *)cmd.params;
-+	cmd_params->mask = cpu_to_le32(mask);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpmac_get_irq_mask() - Get interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	Returned event mask to trigger interrupt
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_get_irq_mask(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       u8 irq_index,
-+		       u32 *mask)
-+{
-+	struct dpmac_cmd_get_irq_mask *cmd_params;
-+	struct dpmac_rsp_get_irq_mask *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpmac_cmd_get_irq_mask *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpmac_rsp_get_irq_mask *)cmd.params;
-+	*mask = le32_to_cpu(rsp_params->mask);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpmac_get_irq_status() - Get the current status of any pending interrupts.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	Returned interrupts status - one bit per cause:
-+ *			0 = no interrupt pending
-+ *			1 = interrupt pending
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_get_irq_status(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u8 irq_index,
-+			 u32 *status)
-+{
-+	struct dpmac_cmd_get_irq_status *cmd_params;
-+	struct dpmac_rsp_get_irq_status *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpmac_cmd_get_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(*status);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpmac_rsp_get_irq_status *)cmd.params;
-+	*status = le32_to_cpu(rsp_params->status);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpmac_clear_irq_status() - Clear a pending interrupt's status
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	Bits to clear (W1C) - one bit per cause:
-+ *			0 = don't change
-+ *			1 = clear status bit
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   u8 irq_index,
-+			   u32 status)
-+{
-+	struct dpmac_cmd_clear_irq_status *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLEAR_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpmac_cmd_clear_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(status);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpmac_get_attributes - Retrieve DPMAC attributes.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @attr:	Returned object's attributes
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 struct dpmac_attr *attr)
-+{
-+	struct dpmac_rsp_get_attributes *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpmac_rsp_get_attributes *)cmd.params;
-+	attr->eth_if = rsp_params->eth_if;
-+	attr->link_type = rsp_params->link_type;
-+	attr->id = le16_to_cpu(rsp_params->id);
-+	attr->max_rate = le32_to_cpu(rsp_params->max_rate);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpmac_get_link_cfg() - Get Ethernet link configuration
-+ * @mc_io:	Pointer to opaque I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @cfg:	Returned structure with the link configuration
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       struct dpmac_link_cfg *cfg)
-+{
-+	struct dpmac_rsp_get_link_cfg *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err = 0;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpmac_rsp_get_link_cfg *)cmd.params;
-+	cfg->options = le64_to_cpu(rsp_params->options);
-+	cfg->rate = le32_to_cpu(rsp_params->rate);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpmac_set_link_state() - Set the Ethernet link status
-+ * @mc_io:	Pointer to opaque I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @link_state:	Link state configuration
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 struct dpmac_link_state *link_state)
-+{
-+	struct dpmac_cmd_set_link_state *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpmac_cmd_set_link_state *)cmd.params;
-+	cmd_params->options = cpu_to_le64(link_state->options);
-+	cmd_params->rate = cpu_to_le32(link_state->rate);
-+	cmd_params->up = dpmac_get_field(link_state->up, STATE);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpmac_get_counter() - Read a specific DPMAC counter
-+ * @mc_io:	Pointer to opaque I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @type:	The requested counter
-+ * @counter:	Returned counter value
-+ *
-+ * Return:	The requested counter; '0' otherwise.
-+ */
-+int dpmac_get_counter(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      enum dpmac_counter type,
-+		      u64 *counter)
-+{
-+	struct dpmac_cmd_get_counter *dpmac_cmd;
-+	struct dpmac_rsp_get_counter *dpmac_rsp;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err = 0;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER,
-+					  cmd_flags,
-+					  token);
-+	dpmac_cmd = (struct dpmac_cmd_get_counter *)cmd.params;
-+	dpmac_cmd->type = type;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	dpmac_rsp = (struct dpmac_rsp_get_counter *)cmd.params;
-+	*counter = le64_to_cpu(dpmac_rsp->counter);
-+
-+	return 0;
-+}
-+
-+/* untested */
-+int dpmac_set_port_mac_addr(struct fsl_mc_io *mc_io,
-+			    u32 cmd_flags,
-+			    u16 token,
-+			    const u8 addr[6])
-+{
-+	struct dpmac_cmd_set_port_mac_addr *dpmac_cmd;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_PORT_MAC_ADDR,
-+					  cmd_flags,
-+					  token);
-+	dpmac_cmd = (struct dpmac_cmd_set_port_mac_addr *)cmd.params;
-+	dpmac_cmd->addr[0] = addr[5];
-+	dpmac_cmd->addr[1] = addr[4];
-+	dpmac_cmd->addr[2] = addr[3];
-+	dpmac_cmd->addr[3] = addr[2];
-+	dpmac_cmd->addr[4] = addr[1];
-+	dpmac_cmd->addr[5] = addr[0];
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpmac_get_api_version() - Get Data Path MAC version
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @major_ver:	Major version of data path mac API
-+ * @minor_ver:	Minor version of data path mac API
-+ *
-+ * Return:  '0' on Success; Error code otherwise.
-+ */
-+int dpmac_get_api_version(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 *major_ver,
-+			  u16 *minor_ver)
-+{
-+	struct dpmac_rsp_get_api_version *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION,
-+					cmd_flags,
-+					0);
-+
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpmac_rsp_get_api_version *)cmd.params;
-+	*major_ver = le16_to_cpu(rsp_params->major);
-+	*minor_ver = le16_to_cpu(rsp_params->minor);
-+
-+	return 0;
-+}
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/mac/dpmac.h
-@@ -0,0 +1,342 @@
-+/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#ifndef __FSL_DPMAC_H
-+#define __FSL_DPMAC_H
-+
-+/* Data Path MAC API
-+ * Contains initialization APIs and runtime control APIs for DPMAC
-+ */
-+
-+struct fsl_mc_io;
-+
-+int dpmac_open(struct fsl_mc_io *mc_io,
-+	       u32 cmd_flags,
-+	       int dpmac_id,
-+	       u16 *token);
-+
-+int dpmac_close(struct fsl_mc_io *mc_io,
-+		u32 cmd_flags,
-+		u16 token);
-+
-+/**
-+ * enum dpmac_link_type -  DPMAC link type
-+ * @DPMAC_LINK_TYPE_NONE: No link
-+ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
-+ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
-+ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
-+ */
-+enum dpmac_link_type {
-+	DPMAC_LINK_TYPE_NONE,
-+	DPMAC_LINK_TYPE_FIXED,
-+	DPMAC_LINK_TYPE_PHY,
-+	DPMAC_LINK_TYPE_BACKPLANE
-+};
-+
-+/**
-+ * enum dpmac_eth_if - DPMAC Ethrnet interface
-+ * @DPMAC_ETH_IF_MII: MII interface
-+ * @DPMAC_ETH_IF_RMII: RMII interface
-+ * @DPMAC_ETH_IF_SMII: SMII interface
-+ * @DPMAC_ETH_IF_GMII: GMII interface
-+ * @DPMAC_ETH_IF_RGMII: RGMII interface
-+ * @DPMAC_ETH_IF_SGMII: SGMII interface
-+ * @DPMAC_ETH_IF_QSGMII: QSGMII interface
-+ * @DPMAC_ETH_IF_XAUI: XAUI interface
-+ * @DPMAC_ETH_IF_XFI: XFI interface
-+ */
-+enum dpmac_eth_if {
-+	DPMAC_ETH_IF_MII,
-+	DPMAC_ETH_IF_RMII,
-+	DPMAC_ETH_IF_SMII,
-+	DPMAC_ETH_IF_GMII,
-+	DPMAC_ETH_IF_RGMII,
-+	DPMAC_ETH_IF_SGMII,
-+	DPMAC_ETH_IF_QSGMII,
-+	DPMAC_ETH_IF_XAUI,
-+	DPMAC_ETH_IF_XFI
-+};
-+
-+/**
-+ * struct dpmac_cfg - Structure representing DPMAC configuration
-+ * @mac_id:	Represents the Hardware MAC ID; in case of multiple WRIOP,
-+ *		the MAC IDs are continuous.
-+ *		For example:  2 WRIOPs, 16 MACs in each:
-+ *				MAC IDs for the 1st WRIOP: 1-16,
-+ *				MAC IDs for the 2nd WRIOP: 17-32.
-+ */
-+struct dpmac_cfg {
-+	u16 mac_id;
-+};
-+
-+int dpmac_create(struct fsl_mc_io *mc_io,
-+		 u16 dprc_token,
-+		 u32 cmd_flags,
-+		 const struct dpmac_cfg *cfg,
-+		 u32 *obj_id);
-+
-+int dpmac_destroy(struct fsl_mc_io *mc_io,
-+		  u16 dprc_token,
-+		  u32 cmd_flags,
-+		  u32 object_id);
-+
-+/**
-+ * DPMAC IRQ Index and Events
-+ */
-+
-+/**
-+ * IRQ index
-+ */
-+#define DPMAC_IRQ_INDEX				0
-+/**
-+ * IRQ event - indicates a change in link state
-+ */
-+#define DPMAC_IRQ_EVENT_LINK_CFG_REQ		0x00000001
-+/**
-+ * IRQ event - Indicates that the link state changed
-+ */
-+#define DPMAC_IRQ_EVENT_LINK_CHANGED		0x00000002
-+
-+int dpmac_set_irq_enable(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u8 irq_index,
-+			 u8 en);
-+
-+int dpmac_get_irq_enable(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u8 irq_index,
-+			 u8 *en);
-+
-+int dpmac_set_irq_mask(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       u8 irq_index,
-+		       u32 mask);
-+
-+int dpmac_get_irq_mask(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       u8 irq_index,
-+		       u32 *mask);
-+
-+int dpmac_get_irq_status(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 u8 irq_index,
-+			 u32 *status);
-+
-+int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   u8 irq_index,
-+			   u32 status);
-+
-+/**
-+ * struct dpmac_attr - Structure representing DPMAC attributes
-+ * @id:		DPMAC object ID
-+ * @max_rate:	Maximum supported rate - in Mbps
-+ * @eth_if:	Ethernet interface
-+ * @link_type:	link type
-+ */
-+struct dpmac_attr {
-+	u16 id;
-+	u32 max_rate;
-+	enum dpmac_eth_if eth_if;
-+	enum dpmac_link_type link_type;
-+};
-+
-+int dpmac_get_attributes(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 struct dpmac_attr *attr);
-+
-+/**
-+ * DPMAC link configuration/state options
-+ */
-+
-+/**
-+ * Enable auto-negotiation
-+ */
-+#define DPMAC_LINK_OPT_AUTONEG		0x0000000000000001ULL
-+/**
-+ * Enable half-duplex mode
-+ */
-+#define DPMAC_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
-+/**
-+ * Enable pause frames
-+ */
-+#define DPMAC_LINK_OPT_PAUSE		0x0000000000000004ULL
-+/**
-+ * Enable a-symmetric pause frames
-+ */
-+#define DPMAC_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
-+
-+/**
-+ * struct dpmac_link_cfg - Structure representing DPMAC link configuration
-+ * @rate: Link's rate - in Mbps
-+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
-+ */
-+struct dpmac_link_cfg {
-+	u32 rate;
-+	u64 options;
-+};
-+
-+int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
-+		       u32 cmd_flags,
-+		       u16 token,
-+		       struct dpmac_link_cfg *cfg);
-+
-+/**
-+ * struct dpmac_link_state - DPMAC link configuration request
-+ * @rate: Rate in Mbps
-+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
-+ * @up: Link state
-+ */
-+struct dpmac_link_state {
-+	u32 rate;
-+	u64 options;
-+	int up;
-+};
-+
-+int dpmac_set_link_state(struct fsl_mc_io *mc_io,
-+			 u32 cmd_flags,
-+			 u16 token,
-+			 struct dpmac_link_state *link_state);
-+
-+/**
-+ * enum dpmac_counter - DPMAC counter types
-+ * @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad.
-+ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-bytes frames, good or bad.
-+ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-bytes frames, good or bad.
-+ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-bytes frames, good or bad.
-+ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-bytes frames, good or bad.
-+ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-bytes frames, good or bad.
-+ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-bytes frames and larger
-+ *				  (up to max frame length specified),
-+ *				  good or bad.
-+ * @DPMAC_CNT_ING_FRAG: counts frames which are shorter than 64 bytes received
-+ *			with a wrong CRC
-+ * @DPMAC_CNT_ING_JABBER: counts frames longer than the maximum frame length
-+ *			  specified, with a bad frame check sequence.
-+ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped frames due to internal errors.
-+ *				 Occurs when a receive FIFO overflows.
-+ *				 Includes also frames truncated as a result of
-+ *				 the receive FIFO overflow.
-+ * @DPMAC_CNT_ING_ALIGN_ERR: counts frames with an alignment error
-+ *			     (optional used for wrong SFD).
-+ * @DPMAC_CNT_EGR_UNDERSIZED: counts frames transmitted that was less than 64
-+ *			      bytes long with a good CRC.
-+ * @DPMAC_CNT_ING_OVERSIZED: counts frames longer than the maximum frame length
-+ *			     specified, with a good frame check sequence.
-+ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frames (regular and PFC)
-+ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frames transmitted
-+ *				     (regular and PFC).
-+ * @DPMAC_CNT_ING_BYTE: counts bytes received except preamble for all valid
-+ *			frames and valid pause frames.
-+ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frames.
-+ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frames.
-+ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad frames received.
-+ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frames.
-+ * @DPMAC_CNT_ING_ERR_FRAME: counts frames received with an error
-+ *			     (except for undersized/fragment frame).
-+ * @DPMAC_CNT_EGR_BYTE: counts bytes transmitted except preamble for all valid
-+ *			frames and valid pause frames transmitted.
-+ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frames.
-+ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frames.
-+ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frames.
-+ * @DPMAC_CNT_EGR_ERR_FRAME: counts frames transmitted with an error.
-+ * @DPMAC_CNT_ING_GOOD_FRAME: counts frames received without error, including
-+ *			      pause frames.
-+ * @DPMAC_CNT_ENG_GOOD_FRAME: counts frames transmitted without error, including
-+ *			      pause frames.
-+ */
-+enum dpmac_counter {
-+	DPMAC_CNT_ING_FRAME_64,
-+	DPMAC_CNT_ING_FRAME_127,
-+	DPMAC_CNT_ING_FRAME_255,
-+	DPMAC_CNT_ING_FRAME_511,
-+	DPMAC_CNT_ING_FRAME_1023,
-+	DPMAC_CNT_ING_FRAME_1518,
-+	DPMAC_CNT_ING_FRAME_1519_MAX,
-+	DPMAC_CNT_ING_FRAG,
-+	DPMAC_CNT_ING_JABBER,
-+	DPMAC_CNT_ING_FRAME_DISCARD,
-+	DPMAC_CNT_ING_ALIGN_ERR,
-+	DPMAC_CNT_EGR_UNDERSIZED,
-+	DPMAC_CNT_ING_OVERSIZED,
-+	DPMAC_CNT_ING_VALID_PAUSE_FRAME,
-+	DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
-+	DPMAC_CNT_ING_BYTE,
-+	DPMAC_CNT_ING_MCAST_FRAME,
-+	DPMAC_CNT_ING_BCAST_FRAME,
-+	DPMAC_CNT_ING_ALL_FRAME,
-+	DPMAC_CNT_ING_UCAST_FRAME,
-+	DPMAC_CNT_ING_ERR_FRAME,
-+	DPMAC_CNT_EGR_BYTE,
-+	DPMAC_CNT_EGR_MCAST_FRAME,
-+	DPMAC_CNT_EGR_BCAST_FRAME,
-+	DPMAC_CNT_EGR_UCAST_FRAME,
-+	DPMAC_CNT_EGR_ERR_FRAME,
-+	DPMAC_CNT_ING_GOOD_FRAME,
-+	DPMAC_CNT_ENG_GOOD_FRAME
-+};
-+
-+int dpmac_get_counter(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      enum dpmac_counter type,
-+		      u64 *counter);
-+
-+/**
-+ * dpmac_set_port_mac_addr() - Set a MAC address associated with the physical
-+ *              port.  This is not used for filtering, MAC is always in
-+ *              promiscuous mode, it is passed to DPNIs through DPNI API for
-+ *              application used.
-+ * @mc_io:	Pointer to opaque I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPMAC object
-+ * @addr:	MAC address to set
-+ *
-+ * Return:	The requested counter; '0' otherwise.
-+ */
-+int dpmac_set_port_mac_addr(struct fsl_mc_io *mc_io,
-+			    u32 cmd_flags,
-+			    u16 token,
-+			    const u8 addr[6]);
-+
-+int dpmac_get_api_version(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 *major_ver,
-+			  u16 *minor_ver);
-+
-+#endif /* __FSL_DPMAC_H */
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/mac/mac.c
-@@ -0,0 +1,672 @@
-+/* Copyright 2015 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the name of Freescale Semiconductor nor the
-+ *	 names of its contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/module.h>
-+
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/msi.h>
-+#include <linux/rtnetlink.h>
-+#include <linux/if_vlan.h>
-+
-+#include <uapi/linux/if_bridge.h>
-+#include <net/netlink.h>
-+
-+#include <linux/of.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_net.h>
-+#include <linux/phy.h>
-+#include <linux/phy_fixed.h>
-+
-+#include <linux/fsl/mc.h>
-+
-+#include "dpmac.h"
-+#include "dpmac-cmd.h"
-+
-+struct dpaa2_mac_priv {
-+	struct net_device		*netdev;
-+	struct fsl_mc_device		*mc_dev;
-+	struct dpmac_attr		attr;
-+	struct dpmac_link_state		old_state;
-+};
-+
-+/* TODO: fix the 10G modes, mapping can't be right:
-+ *  XGMII is paralel
-+ *  XAUI is serial, using 8b/10b encoding
-+ *  XFI is also serial but using 64b/66b encoding
-+ * they can't all map to XGMII...
-+ *
-+ * This must be kept in sync with enum dpmac_eth_if.
-+ */
-+static phy_interface_t dpaa2_mac_iface_mode[] =  {
-+	PHY_INTERFACE_MODE_MII,		/* DPMAC_ETH_IF_MII */
-+	PHY_INTERFACE_MODE_RMII,	/* DPMAC_ETH_IF_RMII */
-+	PHY_INTERFACE_MODE_SMII,	/* DPMAC_ETH_IF_SMII */
-+	PHY_INTERFACE_MODE_GMII,	/* DPMAC_ETH_IF_GMII */
-+	PHY_INTERFACE_MODE_RGMII,	/* DPMAC_ETH_IF_RGMII */
-+	PHY_INTERFACE_MODE_SGMII,	/* DPMAC_ETH_IF_SGMII */
-+	PHY_INTERFACE_MODE_QSGMII,	/* DPMAC_ETH_IF_QSGMII */
-+	PHY_INTERFACE_MODE_XGMII,	/* DPMAC_ETH_IF_XAUI */
-+	PHY_INTERFACE_MODE_XGMII,	/* DPMAC_ETH_IF_XFI */
-+};
-+
-+static void dpaa2_mac_link_changed(struct net_device *netdev)
-+{
-+	struct phy_device	*phydev;
-+	struct dpmac_link_state	state = { 0 };
-+	struct dpaa2_mac_priv	*priv = netdev_priv(netdev);
-+	int			err;
-+
-+	/* the PHY just notified us of link state change */
-+	phydev = netdev->phydev;
-+
-+	state.up = !!phydev->link;
-+	if (phydev->link) {
-+		state.rate = phydev->speed;
-+
-+		if (!phydev->duplex)
-+			state.options |= DPMAC_LINK_OPT_HALF_DUPLEX;
-+		if (phydev->autoneg)
-+			state.options |= DPMAC_LINK_OPT_AUTONEG;
-+
-+		netif_carrier_on(netdev);
-+	} else {
-+		netif_carrier_off(netdev);
-+	}
-+
-+	if (priv->old_state.up != state.up ||
-+	    priv->old_state.rate != state.rate ||
-+	    priv->old_state.options != state.options) {
-+		priv->old_state = state;
-+		phy_print_status(phydev);
-+	}
-+
-+	/* We must interrogate MC at all times, because we don't know
-+	 * when and whether a potential DPNI may have read the link state.
-+	 */
-+	err = dpmac_set_link_state(priv->mc_dev->mc_io, 0,
-+				   priv->mc_dev->mc_handle, &state);
-+	if (unlikely(err))
-+		dev_err(&priv->mc_dev->dev, "dpmac_set_link_state: %d\n", err);
-+}
-+
-+static int dpaa2_mac_open(struct net_device *netdev)
-+{
-+	/* start PHY state machine */
-+	phy_start(netdev->phydev);
-+
-+	return 0;
-+}
-+
-+static int dpaa2_mac_stop(struct net_device *netdev)
-+{
-+	if (!netdev->phydev)
-+		goto done;
-+
-+	/* stop PHY state machine */
-+	phy_stop(netdev->phydev);
-+
-+	/* signal link down to firmware */
-+	netdev->phydev->link = 0;
-+	dpaa2_mac_link_changed(netdev);
-+
-+done:
-+	return 0;
-+}
-+
-+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
-+static netdev_tx_t dpaa2_mac_drop_frame(struct sk_buff *skb,
-+					struct net_device *dev)
-+{
-+	/* we don't support I/O for now, drop the frame */
-+	dev_kfree_skb_any(skb);
-+	return NETDEV_TX_OK;
-+}
-+
-+static int dpaa2_mac_get_link_ksettings(struct net_device *netdev,
-+					struct ethtool_link_ksettings *ks)
-+{
-+	phy_ethtool_ksettings_get(netdev->phydev, ks);
-+
-+	return 0;
-+}
-+
-+static int dpaa2_mac_set_link_ksettings(struct net_device *netdev,
-+					const struct ethtool_link_ksettings *ks)
-+{
-+	return phy_ethtool_ksettings_set(netdev->phydev, ks);
-+}
-+
-+static void dpaa2_mac_get_stats(struct net_device *netdev,
-+				struct rtnl_link_stats64 *storage)
-+{
-+	struct dpaa2_mac_priv	*priv = netdev_priv(netdev);
-+	u64			tmp;
-+	int			err;
-+
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_EGR_MCAST_FRAME,
-+				&storage->tx_packets);
-+	if (err)
-+		goto error;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_EGR_BCAST_FRAME, &tmp);
-+	if (err)
-+		goto error;
-+	storage->tx_packets += tmp;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_EGR_UCAST_FRAME, &tmp);
-+	if (err)
-+		goto error;
-+	storage->tx_packets += tmp;
-+
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_EGR_UNDERSIZED, &storage->tx_dropped);
-+	if (err)
-+		goto error;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_EGR_BYTE, &storage->tx_bytes);
-+	if (err)
-+		goto error;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_EGR_ERR_FRAME, &storage->tx_errors);
-+	if (err)
-+		goto error;
-+
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_ING_ALL_FRAME, &storage->rx_packets);
-+	if (err)
-+		goto error;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_ING_MCAST_FRAME, &storage->multicast);
-+	if (err)
-+		goto error;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_ING_FRAME_DISCARD,
-+				&storage->rx_dropped);
-+	if (err)
-+		goto error;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_ING_ALIGN_ERR, &storage->rx_errors);
-+	if (err)
-+		goto error;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_ING_OVERSIZED, &tmp);
-+	if (err)
-+		goto error;
-+	storage->rx_errors += tmp;
-+	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
-+				DPMAC_CNT_ING_BYTE, &storage->rx_bytes);
-+	if (err)
-+		goto error;
-+
-+	return;
-+error:
-+	netdev_err(netdev, "dpmac_get_counter err %d\n", err);
-+}
-+
-+static struct {
-+	enum dpmac_counter id;
-+	char name[ETH_GSTRING_LEN];
-+} dpaa2_mac_counters[] =  {
-+	{DPMAC_CNT_ING_ALL_FRAME,		"rx all frames"},
-+	{DPMAC_CNT_ING_GOOD_FRAME,		"rx frames ok"},
-+	{DPMAC_CNT_ING_ERR_FRAME,		"rx frame errors"},
-+	{DPMAC_CNT_ING_FRAME_DISCARD,		"rx frame discards"},
-+	{DPMAC_CNT_ING_UCAST_FRAME,		"rx u-cast"},
-+	{DPMAC_CNT_ING_BCAST_FRAME,		"rx b-cast"},
-+	{DPMAC_CNT_ING_MCAST_FRAME,		"rx m-cast"},
-+	{DPMAC_CNT_ING_FRAME_64,		"rx 64 bytes"},
-+	{DPMAC_CNT_ING_FRAME_127,		"rx 65-127 bytes"},
-+	{DPMAC_CNT_ING_FRAME_255,		"rx 128-255 bytes"},
-+	{DPMAC_CNT_ING_FRAME_511,		"rx 256-511 bytes"},
-+	{DPMAC_CNT_ING_FRAME_1023,		"rx 512-1023 bytes"},
-+	{DPMAC_CNT_ING_FRAME_1518,		"rx 1024-1518 bytes"},
-+	{DPMAC_CNT_ING_FRAME_1519_MAX,		"rx 1519-max bytes"},
-+	{DPMAC_CNT_ING_FRAG,			"rx frags"},
-+	{DPMAC_CNT_ING_JABBER,			"rx jabber"},
-+	{DPMAC_CNT_ING_ALIGN_ERR,		"rx align errors"},
-+	{DPMAC_CNT_ING_OVERSIZED,		"rx oversized"},
-+	{DPMAC_CNT_ING_VALID_PAUSE_FRAME,	"rx pause"},
-+	{DPMAC_CNT_ING_BYTE,			"rx bytes"},
-+	{DPMAC_CNT_ENG_GOOD_FRAME,		"tx frames ok"},
-+	{DPMAC_CNT_EGR_UCAST_FRAME,		"tx u-cast"},
-+	{DPMAC_CNT_EGR_MCAST_FRAME,		"tx m-cast"},
-+	{DPMAC_CNT_EGR_BCAST_FRAME,		"tx b-cast"},
-+	{DPMAC_CNT_EGR_ERR_FRAME,		"tx frame errors"},
-+	{DPMAC_CNT_EGR_UNDERSIZED,		"tx undersized"},
-+	{DPMAC_CNT_EGR_VALID_PAUSE_FRAME,	"tx b-pause"},
-+	{DPMAC_CNT_EGR_BYTE,			"tx bytes"},
-+
-+};
-+
-+static void dpaa2_mac_get_strings(struct net_device *netdev,
-+				  u32 stringset, u8 *data)
-+{
-+	int i;
-+
-+	switch (stringset) {
-+	case ETH_SS_STATS:
-+		for (i = 0; i < ARRAY_SIZE(dpaa2_mac_counters); i++)
-+			memcpy(data + i * ETH_GSTRING_LEN,
-+			       dpaa2_mac_counters[i].name,
-+			       ETH_GSTRING_LEN);
-+		break;
-+	}
-+}
-+
-+static void dpaa2_mac_get_ethtool_stats(struct net_device *netdev,
-+					struct ethtool_stats *stats,
-+					u64 *data)
-+{
-+	struct dpaa2_mac_priv	*priv = netdev_priv(netdev);
-+	int			i;
-+	int			err;
-+
-+	for (i = 0; i < ARRAY_SIZE(dpaa2_mac_counters); i++) {
-+		err = dpmac_get_counter(priv->mc_dev->mc_io,
-+					0,
-+					priv->mc_dev->mc_handle,
-+					dpaa2_mac_counters[i].id, &data[i]);
-+		if (err)
-+			netdev_err(netdev, "dpmac_get_counter[%s] err %d\n",
-+				   dpaa2_mac_counters[i].name, err);
-+	}
-+}
-+
-+static int dpaa2_mac_get_sset_count(struct net_device *dev, int sset)
-+{
-+	switch (sset) {
-+	case ETH_SS_STATS:
-+		return ARRAY_SIZE(dpaa2_mac_counters);
-+	default:
-+		return -EOPNOTSUPP;
-+	}
-+}
-+
-+static const struct net_device_ops dpaa2_mac_ndo_ops = {
-+	.ndo_open		= &dpaa2_mac_open,
-+	.ndo_stop		= &dpaa2_mac_stop,
-+	.ndo_start_xmit		= &dpaa2_mac_drop_frame,
-+	.ndo_get_stats64	= &dpaa2_mac_get_stats,
-+};
-+
-+static const struct ethtool_ops dpaa2_mac_ethtool_ops = {
-+	.get_link_ksettings	= &dpaa2_mac_get_link_ksettings,
-+	.set_link_ksettings	= &dpaa2_mac_set_link_ksettings,
-+	.get_strings		= &dpaa2_mac_get_strings,
-+	.get_ethtool_stats	= &dpaa2_mac_get_ethtool_stats,
-+	.get_sset_count		= &dpaa2_mac_get_sset_count,
-+};
-+#endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */
-+
-+static void configure_link(struct dpaa2_mac_priv *priv,
-+			   struct dpmac_link_cfg *cfg)
-+{
-+	struct phy_device *phydev = priv->netdev->phydev;
-+
-+	if (unlikely(!phydev))
-+		return;
-+
-+	phydev->speed = cfg->rate;
-+	phydev->duplex  = !!(cfg->options & DPMAC_LINK_OPT_HALF_DUPLEX);
-+
-+	if (cfg->options & DPMAC_LINK_OPT_AUTONEG) {
-+		phydev->autoneg = 1;
-+		phydev->advertising |= ADVERTISED_Autoneg;
-+	} else {
-+		phydev->autoneg = 0;
-+		phydev->advertising &= ~ADVERTISED_Autoneg;
-+	}
-+
-+	phy_start_aneg(phydev);
-+}
-+
-+static irqreturn_t dpaa2_mac_irq_handler(int irq_num, void *arg)
-+{
-+	struct device *dev = (struct device *)arg;
-+	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
-+	struct dpaa2_mac_priv *priv = dev_get_drvdata(dev);
-+	struct dpmac_link_cfg link_cfg;
-+	u32 status;
-+	int err;
-+
-+	err = dpmac_get_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle,
-+				   DPMAC_IRQ_INDEX, &status);
-+	if (unlikely(err || !status))
-+		return IRQ_NONE;
-+
-+	/* DPNI-initiated link configuration; 'ifconfig up' also calls this */
-+	if (status & DPMAC_IRQ_EVENT_LINK_CFG_REQ) {
-+		err = dpmac_get_link_cfg(mc_dev->mc_io, 0, mc_dev->mc_handle,
-+					 &link_cfg);
-+		if (unlikely(err))
-+			goto out;
-+
-+		configure_link(priv, &link_cfg);
-+	}
-+
-+out:
-+	dpmac_clear_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle,
-+			       DPMAC_IRQ_INDEX, status);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int setup_irqs(struct fsl_mc_device *mc_dev)
-+{
-+	int err = 0;
-+	struct fsl_mc_device_irq *irq;
-+
-+	err = fsl_mc_allocate_irqs(mc_dev);
-+	if (err) {
-+		dev_err(&mc_dev->dev, "fsl_mc_allocate_irqs err %d\n", err);
-+		return err;
-+	}
-+
-+	irq = mc_dev->irqs[0];
-+	err = devm_request_threaded_irq(&mc_dev->dev, irq->msi_desc->irq,
-+					NULL, &dpaa2_mac_irq_handler,
-+					IRQF_NO_SUSPEND | IRQF_ONESHOT,
-+					dev_name(&mc_dev->dev), &mc_dev->dev);
-+	if (err) {
-+		dev_err(&mc_dev->dev, "devm_request_threaded_irq err %d\n",
-+			err);
-+		goto free_irq;
-+	}
-+
-+	err = dpmac_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle,
-+				 DPMAC_IRQ_INDEX, DPMAC_IRQ_EVENT_LINK_CFG_REQ);
-+	if (err) {
-+		dev_err(&mc_dev->dev, "dpmac_set_irq_mask err %d\n", err);
-+		goto free_irq;
-+	}
-+	err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle,
-+				   DPMAC_IRQ_INDEX, 1);
-+	if (err) {
-+		dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err);
-+		goto free_irq;
-+	}
-+
-+	return 0;
-+
-+free_irq:
-+	fsl_mc_free_irqs(mc_dev);
-+
-+	return err;
-+}
-+
-+static void teardown_irqs(struct fsl_mc_device *mc_dev)
-+{
-+	int err;
-+
-+	err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle,
-+				   DPMAC_IRQ_INDEX, 0);
-+	if (err)
-+		dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err);
-+
-+	fsl_mc_free_irqs(mc_dev);
-+}
-+
-+static struct device_node *find_dpmac_node(struct device *dev, u16 dpmac_id)
-+{
-+	struct device_node *dpmacs, *dpmac = NULL;
-+	struct device_node *mc_node = dev->of_node;
-+	u32 id;
-+	int err;
-+
-+	dpmacs = of_find_node_by_name(mc_node, "dpmacs");
-+	if (!dpmacs) {
-+		dev_err(dev, "No dpmacs subnode in device-tree\n");
-+		return NULL;
-+	}
-+
-+	while ((dpmac = of_get_next_child(dpmacs, dpmac))) {
-+		err = of_property_read_u32(dpmac, "reg", &id);
-+		if (err)
-+			continue;
-+		if (id == dpmac_id)
-+			return dpmac;
-+	}
-+
-+	return NULL;
-+}
-+
-+static int dpaa2_mac_probe(struct fsl_mc_device *mc_dev)
-+{
-+	struct device		*dev;
-+	struct dpaa2_mac_priv	*priv = NULL;
-+	struct device_node	*phy_node, *dpmac_node;
-+	struct net_device	*netdev;
-+	phy_interface_t		if_mode;
-+	int			err = 0;
-+
-+	dev = &mc_dev->dev;
-+
-+	/* prepare a net_dev structure to make the phy lib API happy */
-+	netdev = alloc_etherdev(sizeof(*priv));
-+	if (!netdev) {
-+		dev_err(dev, "alloc_etherdev error\n");
-+		err = -ENOMEM;
-+		goto err_exit;
-+	}
-+	priv = netdev_priv(netdev);
-+	priv->mc_dev = mc_dev;
-+	priv->netdev = netdev;
-+
-+	SET_NETDEV_DEV(netdev, dev);
-+
-+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
-+	snprintf(netdev->name, IFNAMSIZ, "mac%d", mc_dev->obj_desc.id);
-+#endif
-+
-+	dev_set_drvdata(dev, priv);
-+
-+	/* We may need to issue MC commands while in atomic context */
-+	err = fsl_mc_portal_allocate(mc_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
-+				     &mc_dev->mc_io);
-+	if (err || !mc_dev->mc_io) {
-+		dev_dbg(dev, "fsl_mc_portal_allocate error: %d\n", err);
-+		err = -EPROBE_DEFER;
-+		goto err_free_netdev;
-+	}
-+
-+	err = dpmac_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id,
-+			 &mc_dev->mc_handle);
-+	if (err || !mc_dev->mc_handle) {
-+		dev_err(dev, "dpmac_open error: %d\n", err);
-+		err = -ENODEV;
-+		goto err_free_mcp;
-+	}
-+
-+	err = dpmac_get_attributes(mc_dev->mc_io, 0,
-+				   mc_dev->mc_handle, &priv->attr);
-+	if (err) {
-+		dev_err(dev, "dpmac_get_attributes err %d\n", err);
-+		err = -EINVAL;
-+		goto err_close;
-+	}
-+
-+	/* Look up the DPMAC node in the device-tree. */
-+	dpmac_node = find_dpmac_node(dev, priv->attr.id);
-+	if (!dpmac_node) {
-+		dev_err(dev, "No dpmac@%d subnode found.\n", priv->attr.id);
-+		err = -ENODEV;
-+		goto err_close;
-+	}
-+
-+	err = setup_irqs(mc_dev);
-+	if (err) {
-+		err = -EFAULT;
-+		goto err_close;
-+	}
-+
-+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
-+	/* OPTIONAL, register netdev just to make it visible to the user */
-+	netdev->netdev_ops = &dpaa2_mac_ndo_ops;
-+	netdev->ethtool_ops = &dpaa2_mac_ethtool_ops;
-+
-+	/* phy starts up enabled so netdev should be up too */
-+	netdev->flags |= IFF_UP;
-+
-+	err = register_netdev(priv->netdev);
-+	if (err < 0) {
-+		dev_err(dev, "register_netdev error %d\n", err);
-+		err = -ENODEV;
-+		goto err_free_irq;
-+	}
-+#endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */
-+
-+	/* probe the PHY as a fixed-link if there's a phy-handle defined
-+	 * in the device tree
-+	 */
-+	phy_node = of_parse_phandle(dpmac_node, "phy-handle", 0);
-+	if (!phy_node) {
-+		goto probe_fixed_link;
-+	}
-+
-+	if (priv->attr.eth_if < ARRAY_SIZE(dpaa2_mac_iface_mode)) {
-+		if_mode = dpaa2_mac_iface_mode[priv->attr.eth_if];
-+		dev_dbg(dev, "\tusing if mode %s for eth_if %d\n",
-+			phy_modes(if_mode), priv->attr.eth_if);
-+	} else {
-+		dev_warn(dev, "Unexpected interface mode %d, will probe as fixed link\n",
-+			 priv->attr.eth_if);
-+		goto probe_fixed_link;
-+	}
-+
-+	/* try to connect to the PHY */
-+	netdev->phydev = of_phy_connect(netdev, phy_node,
-+					&dpaa2_mac_link_changed, 0, if_mode);
-+	if (!netdev->phydev) {
-+		/* No need for dev_err(); the kernel's loud enough as it is. */
-+		dev_dbg(dev, "Can't of_phy_connect() now.\n");
-+		/* We might be waiting for the MDIO MUX to probe, so defer
-+		 * our own probing.
-+		 */
-+		err = -EPROBE_DEFER;
-+		goto err_defer;
-+	}
-+	dev_info(dev, "Connected to %s PHY.\n", phy_modes(if_mode));
-+
-+probe_fixed_link:
-+	if (!netdev->phydev) {
-+		struct fixed_phy_status status = {
-+			.link = 1,
-+			/* fixed-phys don't support 10Gbps speed for now */
-+			.speed = 1000,
-+			.duplex = 1,
-+		};
-+
-+		/* try to register a fixed link phy */
-+		netdev->phydev = fixed_phy_register(PHY_POLL, &status, -1,
-+						    NULL);
-+		if (!netdev->phydev || IS_ERR(netdev->phydev)) {
-+			dev_err(dev, "error trying to register fixed PHY\n");
-+			/* So we don't crash unregister_netdev() later on */
-+			netdev->phydev = NULL;
-+			err = -EFAULT;
-+			goto err_no_phy;
-+		}
-+		dev_info(dev, "Registered fixed PHY.\n");
-+	}
-+
-+	dpaa2_mac_open(netdev);
-+
-+	return 0;
-+
-+err_defer:
-+err_no_phy:
-+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
-+	unregister_netdev(netdev);
-+err_free_irq:
-+#endif
-+	teardown_irqs(mc_dev);
-+err_close:
-+	dpmac_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
-+err_free_mcp:
-+	fsl_mc_portal_free(mc_dev->mc_io);
-+err_free_netdev:
-+	free_netdev(netdev);
-+err_exit:
-+	return err;
-+}
-+
-+static int dpaa2_mac_remove(struct fsl_mc_device *mc_dev)
-+{
-+	struct device		*dev = &mc_dev->dev;
-+	struct dpaa2_mac_priv	*priv = dev_get_drvdata(dev);
-+	struct net_device	*netdev = priv->netdev;
-+
-+	dpaa2_mac_stop(netdev);
-+
-+	if (phy_is_pseudo_fixed_link(netdev->phydev))
-+		fixed_phy_unregister(netdev->phydev);
-+	else
-+		phy_disconnect(netdev->phydev);
-+	netdev->phydev = NULL;
-+
-+#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
-+	unregister_netdev(priv->netdev);
-+#endif
-+	teardown_irqs(priv->mc_dev);
-+	dpmac_close(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle);
-+	fsl_mc_portal_free(priv->mc_dev->mc_io);
-+	free_netdev(priv->netdev);
-+
-+	dev_set_drvdata(dev, NULL);
-+
-+	return 0;
-+}
-+
-+static const struct fsl_mc_device_id dpaa2_mac_match_id_table[] = {
-+	{
-+		.vendor = FSL_MC_VENDOR_FREESCALE,
-+		.obj_type = "dpmac",
-+	},
-+	{ .vendor = 0x0 }
-+};
-+MODULE_DEVICE_TABLE(fslmc, dpaa2_mac_match_id_table);
-+
-+static struct fsl_mc_driver dpaa2_mac_drv = {
-+	.driver = {
-+		.name		= KBUILD_MODNAME,
-+		.owner		= THIS_MODULE,
-+	},
-+	.probe		= dpaa2_mac_probe,
-+	.remove		= dpaa2_mac_remove,
-+	.match_id_table = dpaa2_mac_match_id_table,
-+};
-+
-+module_fsl_mc_driver(dpaa2_mac_drv);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("DPAA2 PHY proxy interface driver");
diff --git a/target/linux/layerscape/patches-4.14/705-dpaa2-rtc-support-layerscape.patch b/target/linux/layerscape/patches-4.14/705-dpaa2-rtc-support-layerscape.patch
deleted file mode 100644
index de6816b58..000000000
--- a/target/linux/layerscape/patches-4.14/705-dpaa2-rtc-support-layerscape.patch
+++ /dev/null
@@ -1,1367 +0,0 @@
-From 579f1f6767b1008c6e5ccc2b029acbb56002ed8b Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:20 +0800
-Subject: [PATCH 11/40] dpaa2-rtc: support layerscape
-This is an integrated patch of dpaa2-rtc for layerscape
-
-Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/staging/fsl-dpaa2/rtc/Makefile    |  10 +
- drivers/staging/fsl-dpaa2/rtc/dprtc-cmd.h | 160 +++++
- drivers/staging/fsl-dpaa2/rtc/dprtc.c     | 746 ++++++++++++++++++++++
- drivers/staging/fsl-dpaa2/rtc/dprtc.h     | 172 +++++
- drivers/staging/fsl-dpaa2/rtc/rtc.c       | 242 +++++++
- 5 files changed, 1330 insertions(+)
- create mode 100644 drivers/staging/fsl-dpaa2/rtc/Makefile
- create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc-cmd.h
- create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc.c
- create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc.h
- create mode 100644 drivers/staging/fsl-dpaa2/rtc/rtc.c
-
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/rtc/Makefile
-@@ -0,0 +1,10 @@
-+
-+obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += dpaa2-rtc.o
-+
-+dpaa2-rtc-objs := rtc.o dprtc.o
-+
-+all:
-+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
-+
-+clean:
-+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/rtc/dprtc-cmd.h
-@@ -0,0 +1,160 @@
-+/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#ifndef _FSL_DPRTC_CMD_H
-+#define _FSL_DPRTC_CMD_H
-+
-+/* DPRTC Version */
-+#define DPRTC_VER_MAJOR			2
-+#define DPRTC_VER_MINOR			0
-+
-+/* Command versioning */
-+#define DPRTC_CMD_BASE_VERSION		1
-+#define DPRTC_CMD_ID_OFFSET		4
-+
-+#define DPRTC_CMD(id)	(((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_BASE_VERSION)
-+
-+/* Command IDs */
-+#define DPRTC_CMDID_CLOSE			DPRTC_CMD(0x800)
-+#define DPRTC_CMDID_OPEN			DPRTC_CMD(0x810)
-+#define DPRTC_CMDID_CREATE			DPRTC_CMD(0x910)
-+#define DPRTC_CMDID_DESTROY			DPRTC_CMD(0x990)
-+#define DPRTC_CMDID_GET_API_VERSION		DPRTC_CMD(0xa10)
-+
-+#define DPRTC_CMDID_ENABLE			DPRTC_CMD(0x002)
-+#define DPRTC_CMDID_DISABLE			DPRTC_CMD(0x003)
-+#define DPRTC_CMDID_GET_ATTR			DPRTC_CMD(0x004)
-+#define DPRTC_CMDID_RESET			DPRTC_CMD(0x005)
-+#define DPRTC_CMDID_IS_ENABLED			DPRTC_CMD(0x006)
-+
-+#define DPRTC_CMDID_SET_IRQ_ENABLE		DPRTC_CMD(0x012)
-+#define DPRTC_CMDID_GET_IRQ_ENABLE		DPRTC_CMD(0x013)
-+#define DPRTC_CMDID_SET_IRQ_MASK		DPRTC_CMD(0x014)
-+#define DPRTC_CMDID_GET_IRQ_MASK		DPRTC_CMD(0x015)
-+#define DPRTC_CMDID_GET_IRQ_STATUS		DPRTC_CMD(0x016)
-+#define DPRTC_CMDID_CLEAR_IRQ_STATUS		DPRTC_CMD(0x017)
-+
-+#define DPRTC_CMDID_SET_CLOCK_OFFSET		DPRTC_CMD(0x1d0)
-+#define DPRTC_CMDID_SET_FREQ_COMPENSATION	DPRTC_CMD(0x1d1)
-+#define DPRTC_CMDID_GET_FREQ_COMPENSATION	DPRTC_CMD(0x1d2)
-+#define DPRTC_CMDID_GET_TIME			DPRTC_CMD(0x1d3)
-+#define DPRTC_CMDID_SET_TIME			DPRTC_CMD(0x1d4)
-+#define DPRTC_CMDID_SET_ALARM			DPRTC_CMD(0x1d5)
-+#define DPRTC_CMDID_SET_PERIODIC_PULSE		DPRTC_CMD(0x1d6)
-+#define DPRTC_CMDID_CLEAR_PERIODIC_PULSE	DPRTC_CMD(0x1d7)
-+#define DPRTC_CMDID_SET_EXT_TRIGGER		DPRTC_CMD(0x1d8)
-+#define DPRTC_CMDID_CLEAR_EXT_TRIGGER		DPRTC_CMD(0x1d9)
-+#define DPRTC_CMDID_GET_EXT_TRIGGER_TIMESTAMP	DPRTC_CMD(0x1dA)
-+
-+/* Macros for accessing command fields smaller than 1byte */
-+#define DPRTC_MASK(field)        \
-+	GENMASK(DPRTC_##field##_SHIFT + DPRTC_##field##_SIZE - 1, \
-+		DPRTC_##field##_SHIFT)
-+#define dprtc_get_field(var, field)      \
-+	(((var) & DPRTC_MASK(field)) >> DPRTC_##field##_SHIFT)
-+
-+#pragma pack(push, 1)
-+struct dprtc_cmd_open {
-+	uint32_t dprtc_id;
-+};
-+
-+struct dprtc_cmd_destroy {
-+	uint32_t object_id;
-+};
-+
-+#define DPRTC_ENABLE_SHIFT	0
-+#define DPRTC_ENABLE_SIZE	1
-+
-+struct dprtc_rsp_is_enabled {
-+	uint8_t en;
-+};
-+
-+struct dprtc_cmd_get_irq {
-+	uint32_t pad;
-+	uint8_t irq_index;
-+};
-+
-+struct dprtc_cmd_set_irq_enable {
-+	uint8_t en;
-+	uint8_t pad[3];
-+	uint8_t irq_index;
-+};
-+
-+struct dprtc_rsp_get_irq_enable {
-+	uint8_t en;
-+};
-+
-+struct dprtc_cmd_set_irq_mask {
-+	uint32_t mask;
-+	uint8_t irq_index;
-+};
-+
-+struct dprtc_rsp_get_irq_mask {
-+	uint32_t mask;
-+};
-+
-+struct dprtc_cmd_get_irq_status {
-+	uint32_t status;
-+	uint8_t irq_index;
-+};
-+
-+struct dprtc_rsp_get_irq_status {
-+	uint32_t status;
-+};
-+
-+struct dprtc_cmd_clear_irq_status {
-+	uint32_t status;
-+	uint8_t irq_index;
-+};
-+
-+struct dprtc_rsp_get_attributes {
-+	uint32_t pad;
-+	uint32_t id;
-+};
-+
-+struct dprtc_cmd_set_clock_offset {
-+	uint64_t offset;
-+};
-+
-+struct dprtc_get_freq_compensation {
-+	uint32_t freq_compensation;
-+};
-+
-+struct dprtc_time {
-+	uint64_t time;
-+};
-+
-+struct dprtc_rsp_get_api_version {
-+	uint16_t major;
-+	uint16_t minor;
-+};
-+#pragma pack(pop)
-+#endif /* _FSL_DPRTC_CMD_H */
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/rtc/dprtc.c
-@@ -0,0 +1,746 @@
-+/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#include <linux/fsl/mc.h>
-+
-+#include "dprtc.h"
-+#include "dprtc-cmd.h"
-+
-+/**
-+ * dprtc_open() - Open a control session for the specified object.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @dprtc_id:	DPRTC unique ID
-+ * @token:	Returned token; use in subsequent API calls
-+ *
-+ * This function can be used to open a control session for an
-+ * already created object; an object may have been declared in
-+ * the DPL or by calling the dprtc_create function.
-+ * This function returns a unique authentication token,
-+ * associated with the specific object ID and the specific MC
-+ * portal; this token must be used in all subsequent commands for
-+ * this specific object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_open(struct fsl_mc_io *mc_io,
-+	       uint32_t cmd_flags,
-+	       int dprtc_id,
-+	       uint16_t *token)
-+{
-+	struct dprtc_cmd_open *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_OPEN,
-+					  cmd_flags,
-+					  0);
-+	cmd_params = (struct dprtc_cmd_open *)cmd.params;
-+	cmd_params->dprtc_id = cpu_to_le32(dprtc_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	*token = mc_cmd_hdr_read_token(&cmd);
-+
-+	return err;
-+}
-+
-+/**
-+ * dprtc_close() - Close the control session of the object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ *
-+ * After this function is called, no further operations are
-+ * allowed on the object without opening a new control session.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_close(struct fsl_mc_io *mc_io,
-+		uint32_t cmd_flags,
-+		uint16_t token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLOSE, cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_create() - Create the DPRTC object.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @dprc_token:	Parent container token; '0' for default container
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @cfg:	Configuration structure
-+ * @obj_id:	Returned object id
-+ *
-+ * Create the DPRTC object, allocate required resources and
-+ * perform required initialization.
-+ *
-+ * The function accepts an authentication token of a parent
-+ * container that this object should be assigned to. The token
-+ * can be '0' so the object will be assigned to the default container.
-+ * The newly created object can be opened with the returned
-+ * object id and using the container's associated tokens and MC portals.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_create(struct fsl_mc_io *mc_io,
-+		 uint16_t dprc_token,
-+		 uint32_t cmd_flags,
-+		 const struct dprtc_cfg *cfg,
-+		 uint32_t *obj_id)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	(void)(cfg); /* unused */
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CREATE,
-+					  cmd_flags,
-+					  dprc_token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	*obj_id = mc_cmd_read_object_id(&cmd);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dprtc_destroy() - Destroy the DPRTC object and release all its resources.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @dprc_token: Parent container token; '0' for default container
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @object_id:	The object id; it must be a valid id within the container that
-+ * created this object;
-+ *
-+ * The function accepts the authentication token of the parent container that
-+ * created the object (not the one that currently owns the object). The object
-+ * is searched within parent using the provided 'object_id'.
-+ * All tokens to the object must be closed before calling destroy.
-+ *
-+ * Return:	'0' on Success; error code otherwise.
-+ */
-+int dprtc_destroy(struct fsl_mc_io *mc_io,
-+		  uint16_t dprc_token,
-+		  uint32_t cmd_flags,
-+		  uint32_t object_id)
-+{
-+	struct dprtc_cmd_destroy *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_DESTROY,
-+					  cmd_flags,
-+					  dprc_token);
-+	cmd_params = (struct dprtc_cmd_destroy *)cmd.params;
-+	cmd_params->object_id = cpu_to_le32(object_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+int dprtc_enable(struct fsl_mc_io *mc_io,
-+		 uint32_t cmd_flags,
-+		 uint16_t token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_ENABLE, cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+int dprtc_disable(struct fsl_mc_io *mc_io,
-+		  uint32_t cmd_flags,
-+		  uint16_t token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_DISABLE,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+int dprtc_is_enabled(struct fsl_mc_io *mc_io,
-+		     uint32_t cmd_flags,
-+		     uint16_t token,
-+		     int *en)
-+{
-+	struct dprtc_rsp_is_enabled *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_IS_ENABLED, cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dprtc_rsp_is_enabled *)cmd.params;
-+	*en = dprtc_get_field(rsp_params->en, ENABLE);
-+
-+	return 0;
-+}
-+
-+int dprtc_reset(struct fsl_mc_io *mc_io,
-+		uint32_t cmd_flags,
-+		uint16_t token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_RESET,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_set_irq_enable() - Set overall interrupt state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Interrupt state - enable = 1, disable = 0
-+ *
-+ * Allows GPP software to control when interrupts are generated.
-+ * Each interrupt can have up to 32 causes.  The enable/disable control's the
-+ * overall interrupt state. if the interrupt is disabled no causes will cause
-+ * an interrupt.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
-+			 uint32_t cmd_flags,
-+			 uint16_t token,
-+			 uint8_t irq_index,
-+			 uint8_t en)
-+{
-+	struct dprtc_cmd_set_irq_enable *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_cmd_set_irq_enable *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+	cmd_params->en = en;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_get_irq_enable() - Get overall interrupt state
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Returned interrupt state - enable = 1, disable = 0
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
-+			 uint32_t cmd_flags,
-+			 uint16_t token,
-+			 uint8_t irq_index,
-+			 uint8_t *en)
-+{
-+	struct dprtc_rsp_get_irq_enable *rsp_params;
-+	struct dprtc_cmd_get_irq *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_cmd_get_irq *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dprtc_rsp_get_irq_enable *)cmd.params;
-+	*en = rsp_params->en;
-+
-+	return 0;
-+}
-+
-+/**
-+ * dprtc_set_irq_mask() - Set interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	Event mask to trigger interrupt;
-+ *		each bit:
-+ *			0 = ignore event
-+ *			1 = consider event for asserting IRQ
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
-+		       uint32_t cmd_flags,
-+		       uint16_t token,
-+		       uint8_t irq_index,
-+		       uint32_t mask)
-+{
-+	struct dprtc_cmd_set_irq_mask *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_cmd_set_irq_mask *)cmd.params;
-+	cmd_params->mask = cpu_to_le32(mask);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_get_irq_mask() - Get interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	Returned event mask to trigger interrupt
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
-+		       uint32_t cmd_flags,
-+		       uint16_t token,
-+		       uint8_t irq_index,
-+		       uint32_t *mask)
-+{
-+	struct dprtc_rsp_get_irq_mask *rsp_params;
-+	struct dprtc_cmd_get_irq *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_cmd_get_irq *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dprtc_rsp_get_irq_mask *)cmd.params;
-+	*mask = le32_to_cpu(rsp_params->mask);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dprtc_get_irq_status() - Get the current status of any pending interrupts.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	Returned interrupts status - one bit per cause:
-+ *			0 = no interrupt pending
-+ *			1 = interrupt pending
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
-+			 uint32_t cmd_flags,
-+			 uint16_t token,
-+			 uint8_t irq_index,
-+			 uint32_t *status)
-+{
-+	struct dprtc_cmd_get_irq_status *cmd_params;
-+	struct dprtc_rsp_get_irq_status *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_cmd_get_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(*status);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dprtc_rsp_get_irq_status *)cmd.params;
-+	*status = rsp_params->status;
-+
-+	return 0;
-+}
-+
-+/**
-+ * dprtc_clear_irq_status() - Clear a pending interrupt's status
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	Bits to clear (W1C) - one bit per cause:
-+ *			0 = don't change
-+ *			1 = clear status bit
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
-+			   uint32_t cmd_flags,
-+			   uint16_t token,
-+			   uint8_t irq_index,
-+			   uint32_t status)
-+{
-+	struct dprtc_cmd_clear_irq_status *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLEAR_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_cmd_clear_irq_status *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+	cmd_params->status = cpu_to_le32(status);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_get_attributes - Retrieve DPRTC attributes.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @attr:	Returned object's attributes
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_get_attributes(struct fsl_mc_io *mc_io,
-+			 uint32_t cmd_flags,
-+			 uint16_t token,
-+			 struct dprtc_attr *attr)
-+{
-+	struct dprtc_rsp_get_attributes *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_ATTR,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dprtc_rsp_get_attributes *)cmd.params;
-+	attr->id = le32_to_cpu(rsp_params->id);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dprtc_set_clock_offset() - Sets the clock's offset
-+ * (usually relative to another clock).
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @offset:	New clock offset (in nanoseconds).
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_set_clock_offset(struct fsl_mc_io *mc_io,
-+			   uint32_t cmd_flags,
-+			   uint16_t token,
-+			   int64_t offset)
-+{
-+	struct dprtc_cmd_set_clock_offset *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_CLOCK_OFFSET,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_cmd_set_clock_offset *)cmd.params;
-+	cmd_params->offset = cpu_to_le64(offset);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_set_freq_compensation() - Sets a new frequency compensation value.
-+ *
-+ * @mc_io:		Pointer to MC portal's I/O object
-+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:		Token of DPRTC object
-+ * @freq_compensation:	The new frequency compensation value to set.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
-+				uint32_t cmd_flags,
-+				uint16_t token,
-+				uint32_t freq_compensation)
-+{
-+	struct dprtc_get_freq_compensation *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_FREQ_COMPENSATION,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_get_freq_compensation *)cmd.params;
-+	cmd_params->freq_compensation = cpu_to_le32(freq_compensation);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_get_freq_compensation() - Retrieves the frequency compensation value
-+ *
-+ * @mc_io:		Pointer to MC portal's I/O object
-+ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:		Token of DPRTC object
-+ * @freq_compensation:	Frequency compensation value
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io,
-+				uint32_t cmd_flags,
-+				uint16_t token,
-+				uint32_t *freq_compensation)
-+{
-+	struct dprtc_get_freq_compensation *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_FREQ_COMPENSATION,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dprtc_get_freq_compensation *)cmd.params;
-+	*freq_compensation = le32_to_cpu(rsp_params->freq_compensation);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dprtc_get_time() - Returns the current RTC time.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @time:	Current RTC time.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_get_time(struct fsl_mc_io *mc_io,
-+		   uint32_t cmd_flags,
-+		   uint16_t token,
-+		   uint64_t *time)
-+{
-+	struct dprtc_time *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_TIME,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dprtc_time *)cmd.params;
-+	*time = le64_to_cpu(rsp_params->time);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dprtc_set_time() - Updates current RTC time.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @time:	New RTC time.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_set_time(struct fsl_mc_io *mc_io,
-+		   uint32_t cmd_flags,
-+		   uint16_t token,
-+		   uint64_t time)
-+{
-+	struct dprtc_time *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_TIME,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_time *)cmd.params;
-+	cmd_params->time = cpu_to_le64(time);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_set_alarm() - Defines and sets alarm.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPRTC object
-+ * @time:	In nanoseconds, the time when the alarm
-+ *			should go off - must be a multiple of
-+ *			1 microsecond
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dprtc_set_alarm(struct fsl_mc_io *mc_io,
-+		    uint32_t cmd_flags,
-+		    uint16_t token, uint64_t time)
-+{
-+	struct dprtc_time *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_ALARM,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dprtc_time *)cmd.params;
-+	cmd_params->time = cpu_to_le64(time);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dprtc_get_api_version() - Get Data Path Real Time Counter API version
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @major_ver:	Major version of data path real time counter API
-+ * @minor_ver:	Minor version of data path real time counter API
-+ *
-+ * Return:  '0' on Success; Error code otherwise.
-+ */
-+int dprtc_get_api_version(struct fsl_mc_io *mc_io,
-+			  uint32_t cmd_flags,
-+			  uint16_t *major_ver,
-+			  uint16_t *minor_ver)
-+{
-+	struct dprtc_rsp_get_api_version *rsp_params;
-+	struct fsl_mc_command cmd = { 0 };
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_API_VERSION,
-+					cmd_flags,
-+					0);
-+
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dprtc_rsp_get_api_version *)cmd.params;
-+	*major_ver = le16_to_cpu(rsp_params->major);
-+	*minor_ver = le16_to_cpu(rsp_params->minor);
-+
-+	return 0;
-+}
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/rtc/dprtc.h
-@@ -0,0 +1,172 @@
-+/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#ifndef __FSL_DPRTC_H
-+#define __FSL_DPRTC_H
-+
-+/* Data Path Real Time Counter API
-+ * Contains initialization APIs and runtime control APIs for RTC
-+ */
-+
-+struct fsl_mc_io;
-+
-+/**
-+ * Number of irq's
-+ */
-+#define DPRTC_MAX_IRQ_NUM			1
-+#define DPRTC_IRQ_INDEX				0
-+
-+/**
-+ * Interrupt event masks:
-+ */
-+
-+/**
-+ * Interrupt event mask indicating alarm event had occurred
-+ */
-+#define DPRTC_EVENT_ALARM			0x40000000
-+/**
-+ * Interrupt event mask indicating periodic pulse event had occurred
-+ */
-+#define DPRTC_EVENT_PPS				0x08000000
-+
-+int dprtc_open(struct fsl_mc_io *mc_io,
-+	       uint32_t cmd_flags,
-+	       int dprtc_id,
-+	       uint16_t *token);
-+
-+int dprtc_close(struct fsl_mc_io *mc_io,
-+		uint32_t cmd_flags,
-+		uint16_t token);
-+
-+/**
-+ * struct dprtc_cfg - Structure representing DPRTC configuration
-+ * @options:	place holder
-+ */
-+struct dprtc_cfg {
-+	uint32_t options;
-+};
-+
-+int dprtc_create(struct fsl_mc_io *mc_io,
-+		 uint16_t dprc_token,
-+		 uint32_t cmd_flags,
-+		 const struct dprtc_cfg *cfg,
-+		 uint32_t *obj_id);
-+
-+int dprtc_destroy(struct fsl_mc_io *mc_io,
-+		  uint16_t dprc_token,
-+		  uint32_t cmd_flags,
-+		  uint32_t object_id);
-+
-+int dprtc_set_clock_offset(struct fsl_mc_io *mc_io,
-+			   uint32_t cmd_flags,
-+			   uint16_t token,
-+			   int64_t offset);
-+
-+int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
-+		  uint32_t cmd_flags,
-+		  uint16_t token,
-+		  uint32_t freq_compensation);
-+
-+int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io,
-+		  uint32_t cmd_flags,
-+		  uint16_t token,
-+		  uint32_t *freq_compensation);
-+
-+int dprtc_get_time(struct fsl_mc_io *mc_io,
-+		   uint32_t cmd_flags,
-+		   uint16_t token,
-+		   uint64_t *time);
-+
-+int dprtc_set_time(struct fsl_mc_io *mc_io,
-+		   uint32_t cmd_flags,
-+		   uint16_t token,
-+		   uint64_t time);
-+
-+int dprtc_set_alarm(struct fsl_mc_io *mc_io,
-+		    uint32_t cmd_flags,
-+		    uint16_t token,
-+		    uint64_t time);
-+
-+int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
-+			 uint32_t cmd_flags,
-+			 uint16_t token,
-+			 uint8_t irq_index,
-+			 uint8_t en);
-+
-+int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
-+			 uint32_t cmd_flags,
-+			 uint16_t token,
-+			 uint8_t irq_index,
-+			 uint8_t *en);
-+
-+int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
-+		       uint32_t cmd_flags,
-+		       uint16_t token,
-+		       uint8_t irq_index,
-+		       uint32_t mask);
-+
-+int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
-+		       uint32_t cmd_flags,
-+		       uint16_t token,
-+		       uint8_t irq_index,
-+		       uint32_t *mask);
-+
-+int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
-+			 uint32_t cmd_flags,
-+			 uint16_t token,
-+			 uint8_t irq_index,
-+			 uint32_t *status);
-+
-+int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
-+			   uint32_t cmd_flags,
-+			   uint16_t token,
-+			   uint8_t irq_index,
-+			   uint32_t status);
-+
-+/**
-+ * struct dprtc_attr - Structure representing DPRTC attributes
-+ * @id:		DPRTC object ID
-+ */
-+struct dprtc_attr {
-+	int id;
-+};
-+
-+int dprtc_get_attributes(struct fsl_mc_io *mc_io,
-+			 uint32_t cmd_flags,
-+			 uint16_t token,
-+			 struct dprtc_attr *attr);
-+
-+int dprtc_get_api_version(struct fsl_mc_io *mc_io,
-+			  uint32_t cmd_flags,
-+			  uint16_t *major_ver,
-+			  uint16_t *minor_ver);
-+
-+#endif /* __FSL_DPRTC_H */
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/rtc/rtc.c
-@@ -0,0 +1,242 @@
-+/* Copyright 2013-2015 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/ptp_clock_kernel.h>
-+
-+#include <linux/fsl/mc.h>
-+
-+#include "dprtc.h"
-+#include "dprtc-cmd.h"
-+
-+#define N_EXT_TS	2
-+
-+struct ptp_clock *clock;
-+struct fsl_mc_device *rtc_mc_dev;
-+u32 freqCompensation;
-+
-+/* PTP clock operations */
-+static int ptp_dpaa2_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
-+{
-+	u64 adj;
-+	u32 diff, tmr_add;
-+	int neg_adj = 0;
-+	int err = 0;
-+	struct fsl_mc_device *mc_dev = rtc_mc_dev;
-+	struct device *dev = &mc_dev->dev;
-+
-+	if (ppb < 0) {
-+		neg_adj = 1;
-+		ppb = -ppb;
-+	}
-+
-+	tmr_add = freqCompensation;
-+	adj = tmr_add;
-+	adj *= ppb;
-+	diff = div_u64(adj, 1000000000ULL);
-+
-+	tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
-+
-+	err = dprtc_set_freq_compensation(mc_dev->mc_io, 0,
-+					  mc_dev->mc_handle, tmr_add);
-+	if (err)
-+		dev_err(dev, "dprtc_set_freq_compensation err %d\n", err);
-+	return 0;
-+}
-+
-+static int ptp_dpaa2_adjtime(struct ptp_clock_info *ptp, s64 delta)
-+{
-+	s64 now;
-+	int err = 0;
-+	struct fsl_mc_device *mc_dev = rtc_mc_dev;
-+	struct device *dev = &mc_dev->dev;
-+
-+	err = dprtc_get_time(mc_dev->mc_io, 0, mc_dev->mc_handle, &now);
-+	if (err) {
-+		dev_err(dev, "dprtc_get_time err %d\n", err);
-+		return 0;
-+	}
-+
-+	now += delta;
-+
-+	err = dprtc_set_time(mc_dev->mc_io, 0, mc_dev->mc_handle, now);
-+	if (err) {
-+		dev_err(dev, "dprtc_set_time err %d\n", err);
-+		return 0;
-+	}
-+	return 0;
-+}
-+
-+static int ptp_dpaa2_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
-+{
-+	u64 ns;
-+	u32 remainder;
-+	int err = 0;
-+	struct fsl_mc_device *mc_dev = rtc_mc_dev;
-+	struct device *dev = &mc_dev->dev;
-+
-+	err = dprtc_get_time(mc_dev->mc_io, 0, mc_dev->mc_handle, &ns);
-+	if (err) {
-+		dev_err(dev, "dprtc_get_time err %d\n", err);
-+		return 0;
-+	}
-+
-+	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
-+	ts->tv_nsec = remainder;
-+	return 0;
-+}
-+
-+static int ptp_dpaa2_settime(struct ptp_clock_info *ptp,
-+			       const struct timespec *ts)
-+{
-+	u64 ns;
-+	int err = 0;
-+	struct fsl_mc_device *mc_dev = rtc_mc_dev;
-+	struct device *dev = &mc_dev->dev;
-+
-+	ns = ts->tv_sec * 1000000000ULL;
-+	ns += ts->tv_nsec;
-+
-+	err = dprtc_set_time(mc_dev->mc_io, 0, mc_dev->mc_handle, ns);
-+	if (err)
-+		dev_err(dev, "dprtc_set_time err %d\n", err);
-+	return 0;
-+}
-+
-+static struct ptp_clock_info ptp_dpaa2_caps = {
-+	.owner		= THIS_MODULE,
-+	.name		= "dpaa2 clock",
-+	.max_adj	= 512000,
-+	.n_alarm	= 0,
-+	.n_ext_ts	= N_EXT_TS,
-+	.n_per_out	= 0,
-+	.n_pins		= 0,
-+	.pps		= 1,
-+	.adjfreq	= ptp_dpaa2_adjfreq,
-+	.adjtime	= ptp_dpaa2_adjtime,
-+	.gettime64	= ptp_dpaa2_gettime,
-+	.settime64	= ptp_dpaa2_settime,
-+};
-+
-+static int rtc_probe(struct fsl_mc_device *mc_dev)
-+{
-+	struct device		*dev;
-+	int			err = 0;
-+	int			dpaa2_phc_index;
-+	u32			tmr_add = 0;
-+
-+	if (!mc_dev)
-+		return -EFAULT;
-+
-+	dev = &mc_dev->dev;
-+
-+	err = fsl_mc_portal_allocate(mc_dev, 0, &mc_dev->mc_io);
-+	if (unlikely(err)) {
-+		dev_err(dev, "fsl_mc_portal_allocate err %d\n", err);
-+		goto err_exit;
-+	}
-+	if (!mc_dev->mc_io) {
-+		dev_err(dev,
-+			"fsl_mc_portal_allocate returned null handle but no error\n");
-+		err = -EFAULT;
-+		goto err_exit;
-+	}
-+
-+	err = dprtc_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id,
-+			 &mc_dev->mc_handle);
-+	if (err) {
-+		dev_err(dev, "dprtc_open err %d\n", err);
-+		goto err_free_mcp;
-+	}
-+	if (!mc_dev->mc_handle) {
-+		dev_err(dev, "dprtc_open returned null handle but no error\n");
-+		err = -EFAULT;
-+		goto err_free_mcp;
-+	}
-+
-+	rtc_mc_dev = mc_dev;
-+
-+	err = dprtc_get_freq_compensation(mc_dev->mc_io, 0,
-+					  mc_dev->mc_handle, &tmr_add);
-+	if (err) {
-+		dev_err(dev, "dprtc_get_freq_compensation err %d\n", err);
-+		goto err_close;
-+	}
-+	freqCompensation = tmr_add;
-+
-+	clock = ptp_clock_register(&ptp_dpaa2_caps, dev);
-+	if (IS_ERR(clock)) {
-+		err = PTR_ERR(clock);
-+		goto err_close;
-+	}
-+	dpaa2_phc_index = ptp_clock_index(clock);
-+
-+	return 0;
-+err_close:
-+	dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
-+err_free_mcp:
-+	fsl_mc_portal_free(mc_dev->mc_io);
-+err_exit:
-+	return err;
-+}
-+
-+static int rtc_remove(struct fsl_mc_device *mc_dev)
-+{
-+	ptp_clock_unregister(clock);
-+	dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
-+	fsl_mc_portal_free(mc_dev->mc_io);
-+
-+	return 0;
-+}
-+
-+static const struct fsl_mc_device_id rtc_match_id_table[] = {
-+	{
-+		.vendor = FSL_MC_VENDOR_FREESCALE,
-+		.obj_type = "dprtc",
-+	},
-+	{}
-+};
-+
-+static struct fsl_mc_driver rtc_drv = {
-+	.driver = {
-+		.name		= KBUILD_MODNAME,
-+		.owner		= THIS_MODULE,
-+	},
-+	.probe		= rtc_probe,
-+	.remove		= rtc_remove,
-+	.match_id_table = rtc_match_id_table,
-+};
-+
-+module_fsl_mc_driver(rtc_drv);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("DPAA2 RTC (PTP 1588 clock) driver (prototype)");
diff --git a/target/linux/layerscape/patches-4.14/706-dpaa2-virtualbridge-support-layerscape.patch b/target/linux/layerscape/patches-4.14/706-dpaa2-virtualbridge-support-layerscape.patch
deleted file mode 100644
index 6c89bb1fe..000000000
--- a/target/linux/layerscape/patches-4.14/706-dpaa2-virtualbridge-support-layerscape.patch
+++ /dev/null
@@ -1,3256 +0,0 @@
-From 278c2ebd8f04e2b05c87187a3e8b6af552abd57f Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Thu, 13 Dec 2018 13:27:22 +0800
-Subject: [PATCH] dpaa2-virtualbridge: support layerscape
-
-This is an integrated patch of dpaa2-virtualbridge for layerscape
-
-Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
----
- drivers/staging/fsl-dpaa2/evb/Kconfig      |    7 +
- drivers/staging/fsl-dpaa2/evb/Makefile     |   10 +
- drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h |  279 ++++
- drivers/staging/fsl-dpaa2/evb/dpdmux.c     | 1111 ++++++++++++++++
- drivers/staging/fsl-dpaa2/evb/dpdmux.h     |  453 +++++++
- drivers/staging/fsl-dpaa2/evb/evb.c        | 1353 ++++++++++++++++++++
- 6 files changed, 3213 insertions(+)
- create mode 100644 drivers/staging/fsl-dpaa2/evb/Kconfig
- create mode 100644 drivers/staging/fsl-dpaa2/evb/Makefile
- create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h
- create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux.c
- create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux.h
- create mode 100644 drivers/staging/fsl-dpaa2/evb/evb.c
-
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/evb/Kconfig
-@@ -0,0 +1,7 @@
-+config FSL_DPAA2_EVB
-+	tristate "DPAA2 Edge Virtual Bridge"
-+	depends on FSL_MC_BUS && FSL_DPAA2
-+	select VLAN_8021Q
-+	default y
-+	---help---
-+	Prototype driver for DPAA2 Edge Virtual Bridge.
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/evb/Makefile
-@@ -0,0 +1,10 @@
-+
-+obj-$(CONFIG_FSL_DPAA2_EVB) += dpaa2-evb.o
-+
-+dpaa2-evb-objs := evb.o dpdmux.o
-+
-+all:
-+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
-+
-+clean:
-+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h
-@@ -0,0 +1,279 @@
-+/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#ifndef _FSL_DPDMUX_CMD_H
-+#define _FSL_DPDMUX_CMD_H
-+
-+/* DPDMUX Version */
-+#define DPDMUX_VER_MAJOR		6
-+#define DPDMUX_VER_MINOR		1
-+
-+#define DPDMUX_CMD_BASE_VER		1
-+#define DPDMUX_CMD_ID_OFFSET		4
-+
-+#define DPDMUX_CMD(id)	(((id) << DPDMUX_CMD_ID_OFFSET) | DPDMUX_CMD_BASE_VER)
-+
-+/* Command IDs */
-+#define DPDMUX_CMDID_CLOSE			DPDMUX_CMD(0x800)
-+#define DPDMUX_CMDID_OPEN			DPDMUX_CMD(0x806)
-+#define DPDMUX_CMDID_CREATE			DPDMUX_CMD(0x906)
-+#define DPDMUX_CMDID_DESTROY			DPDMUX_CMD(0x986)
-+#define DPDMUX_CMDID_GET_API_VERSION		DPDMUX_CMD(0xa06)
-+
-+#define DPDMUX_CMDID_ENABLE			DPDMUX_CMD(0x002)
-+#define DPDMUX_CMDID_DISABLE			DPDMUX_CMD(0x003)
-+#define DPDMUX_CMDID_GET_ATTR			DPDMUX_CMD(0x004)
-+#define DPDMUX_CMDID_RESET			DPDMUX_CMD(0x005)
-+#define DPDMUX_CMDID_IS_ENABLED			DPDMUX_CMD(0x006)
-+
-+#define DPDMUX_CMDID_SET_IRQ_ENABLE		DPDMUX_CMD(0x012)
-+#define DPDMUX_CMDID_GET_IRQ_ENABLE		DPDMUX_CMD(0x013)
-+#define DPDMUX_CMDID_SET_IRQ_MASK		DPDMUX_CMD(0x014)
-+#define DPDMUX_CMDID_GET_IRQ_MASK		DPDMUX_CMD(0x015)
-+#define DPDMUX_CMDID_GET_IRQ_STATUS		DPDMUX_CMD(0x016)
-+#define DPDMUX_CMDID_CLEAR_IRQ_STATUS		DPDMUX_CMD(0x017)
-+
-+#define DPDMUX_CMDID_SET_MAX_FRAME_LENGTH	DPDMUX_CMD(0x0a1)
-+
-+#define DPDMUX_CMDID_UL_RESET_COUNTERS		DPDMUX_CMD(0x0a3)
-+
-+#define DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES	DPDMUX_CMD(0x0a7)
-+#define DPDMUX_CMDID_IF_GET_ATTR		DPDMUX_CMD(0x0a8)
-+#define DPDMUX_CMDID_IF_ENABLE			DPDMUX_CMD(0x0a9)
-+#define DPDMUX_CMDID_IF_DISABLE			DPDMUX_CMD(0x0aa)
-+
-+#define DPDMUX_CMDID_IF_ADD_L2_RULE		DPDMUX_CMD(0x0b0)
-+#define DPDMUX_CMDID_IF_REMOVE_L2_RULE		DPDMUX_CMD(0x0b1)
-+#define DPDMUX_CMDID_IF_GET_COUNTER		DPDMUX_CMD(0x0b2)
-+#define DPDMUX_CMDID_IF_SET_LINK_CFG		DPDMUX_CMD(0x0b3)
-+#define DPDMUX_CMDID_IF_GET_LINK_STATE		DPDMUX_CMD(0x0b4)
-+
-+#define DPDMUX_CMDID_SET_CUSTOM_KEY		DPDMUX_CMD(0x0b5)
-+#define DPDMUX_CMDID_ADD_CUSTOM_CLS_ENTRY	DPDMUX_CMD(0x0b6)
-+#define DPDMUX_CMDID_REMOVE_CUSTOM_CLS_ENTRY	DPDMUX_CMD(0x0b7)
-+
-+#define DPDMUX_MASK(field)        \
-+	GENMASK(DPDMUX_##field##_SHIFT + DPDMUX_##field##_SIZE - 1, \
-+		DPDMUX_##field##_SHIFT)
-+#define dpdmux_set_field(var, field, val) \
-+	((var) |= (((val) << DPDMUX_##field##_SHIFT) & DPDMUX_MASK(field)))
-+#define dpdmux_get_field(var, field)      \
-+	(((var) & DPDMUX_MASK(field)) >> DPDMUX_##field##_SHIFT)
-+
-+struct dpdmux_cmd_open {
-+	u32 dpdmux_id;
-+};
-+
-+struct dpdmux_cmd_create {
-+	u8 method;
-+	u8 manip;
-+	u16 num_ifs;
-+	u32 pad;
-+
-+	u16 adv_max_dmat_entries;
-+	u16 adv_max_mc_groups;
-+	u16 adv_max_vlan_ids;
-+	u16 pad1;
-+
-+	u64 options;
-+};
-+
-+struct dpdmux_cmd_destroy {
-+	u32 dpdmux_id;
-+};
-+
-+#define DPDMUX_ENABLE_SHIFT	0
-+#define DPDMUX_ENABLE_SIZE	1
-+
-+struct dpdmux_rsp_is_enabled {
-+	u8 en;
-+};
-+
-+struct dpdmux_cmd_set_irq_enable {
-+	u8 enable;
-+	u8 pad[3];
-+	u8 irq_index;
-+};
-+
-+struct dpdmux_cmd_get_irq_enable {
-+	u32 pad;
-+	u8 irq_index;
-+};
-+
-+struct dpdmux_rsp_get_irq_enable {
-+	u8 enable;
-+};
-+
-+struct dpdmux_cmd_set_irq_mask {
-+	u32 mask;
-+	u8 irq_index;
-+};
-+
-+struct dpdmux_cmd_get_irq_mask {
-+	u32 pad;
-+	u8 irq_index;
-+};
-+
-+struct dpdmux_rsp_get_irq_mask {
-+	u32 mask;
-+};
-+
-+struct dpdmux_cmd_get_irq_status {
-+	u32 status;
-+	u8 irq_index;
-+};
-+
-+struct dpdmux_rsp_get_irq_status {
-+	u32 status;
-+};
-+
-+struct dpdmux_cmd_clear_irq_status {
-+	u32 status;
-+	u8 irq_index;
-+};
-+
-+struct dpdmux_rsp_get_attr {
-+	u8 method;
-+	u8 manip;
-+	u16 num_ifs;
-+	u16 mem_size;
-+	u16 pad;
-+
-+	u64 pad1;
-+
-+	u32 id;
-+	u32 pad2;
-+
-+	u64 options;
-+};
-+
-+struct dpdmux_cmd_set_max_frame_length {
-+	u16 max_frame_length;
-+};
-+
-+#define DPDMUX_ACCEPTED_FRAMES_TYPE_SHIFT	0
-+#define DPDMUX_ACCEPTED_FRAMES_TYPE_SIZE	4
-+#define DPDMUX_UNACCEPTED_FRAMES_ACTION_SHIFT	4
-+#define DPDMUX_UNACCEPTED_FRAMES_ACTION_SIZE	4
-+
-+struct dpdmux_cmd_if_set_accepted_frames {
-+	u16 if_id;
-+	u8 frames_options;
-+};
-+
-+struct dpdmux_cmd_if {
-+	u16 if_id;
-+};
-+
-+struct dpdmux_rsp_if_get_attr {
-+	u8 pad[3];
-+	u8 enabled;
-+	u8 pad1[3];
-+	u8 accepted_frames_type;
-+	u32 rate;
-+};
-+
-+struct dpdmux_cmd_if_l2_rule {
-+	u16 if_id;
-+	u8 mac_addr5;
-+	u8 mac_addr4;
-+	u8 mac_addr3;
-+	u8 mac_addr2;
-+	u8 mac_addr1;
-+	u8 mac_addr0;
-+
-+	u32 pad;
-+	u16 vlan_id;
-+};
-+
-+struct dpdmux_cmd_if_get_counter {
-+	u16 if_id;
-+	u8 counter_type;
-+};
-+
-+struct dpdmux_rsp_if_get_counter {
-+	u64 pad;
-+	u64 counter;
-+};
-+
-+struct dpdmux_cmd_if_set_link_cfg {
-+	u16 if_id;
-+	u16 pad[3];
-+
-+	u32 rate;
-+	u32 pad1;
-+
-+	u64 options;
-+};
-+
-+struct dpdmux_cmd_if_get_link_state {
-+	u16 if_id;
-+};
-+
-+struct dpdmux_rsp_if_get_link_state {
-+	u32 pad;
-+	u8 up;
-+	u8 pad1[3];
-+
-+	u32 rate;
-+	u32 pad2;
-+
-+	u64 options;
-+};
-+
-+struct dpdmux_rsp_get_api_version {
-+	u16 major;
-+	u16 minor;
-+};
-+
-+struct dpdmux_set_custom_key {
-+	u64 pad[6];
-+	u64 key_cfg_iova;
-+};
-+
-+struct dpdmux_cmd_add_custom_cls_entry {
-+	u8 pad[3];
-+	u8 key_size;
-+	u16 pad1;
-+	u16 dest_if;
-+	u64 key_iova;
-+	u64 mask_iova;
-+};
-+
-+struct dpdmux_cmd_remove_custom_cls_entry {
-+	u8 pad[3];
-+	u8 key_size;
-+	u32 pad1;
-+	u64 key_iova;
-+	u64 mask_iova;
-+};
-+
-+#endif /* _FSL_DPDMUX_CMD_H */
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/evb/dpdmux.c
-@@ -0,0 +1,1111 @@
-+/* Copyright 2013-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#include <linux/fsl/mc.h>
-+#include "dpdmux.h"
-+#include "dpdmux-cmd.h"
-+
-+/**
-+ * dpdmux_open() - Open a control session for the specified object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @dpdmux_id:		DPDMUX unique ID
-+ * @token:		Returned token; use in subsequent API calls
-+ *
-+ * This function can be used to open a control session for an
-+ * already created object; an object may have been declared in
-+ * the DPL or by calling the dpdmux_create() function.
-+ * This function returns a unique authentication token,
-+ * associated with the specific object ID and the specific MC
-+ * portal; this token must be used in all subsequent commands for
-+ * this specific object.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_open(struct fsl_mc_io *mc_io,
-+		u32 cmd_flags,
-+		int dpdmux_id,
-+		u16 *token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_open *cmd_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_OPEN,
-+					  cmd_flags,
-+					  0);
-+	cmd_params = (struct dpdmux_cmd_open *)cmd.params;
-+	cmd_params->dpdmux_id = cpu_to_le32(dpdmux_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	*token = mc_cmd_hdr_read_token(&cmd);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_close() - Close the control session of the object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:		Token of DPDMUX object
-+ *
-+ * After this function is called, no further operations are
-+ * allowed on the object without opening a new control session.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_close(struct fsl_mc_io *mc_io,
-+		 u32 cmd_flags,
-+		 u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CLOSE,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_create() - Create the DPDMUX object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @dprc_token:	Parent container token; '0' for default container
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @cfg:	Configuration structure
-+ * @obj_id: returned object id
-+ *
-+ * Create the DPDMUX object, allocate required resources and
-+ * perform required initialization.
-+ *
-+ * The object can be created either by declaring it in the
-+ * DPL file, or by calling this function.
-+ *
-+ * The function accepts an authentication token of a parent
-+ * container that this object should be assigned to. The token
-+ * can be '0' so the object will be assigned to the default container.
-+ * The newly created object can be opened with the returned
-+ * object id and using the container's associated tokens and MC portals.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_create(struct fsl_mc_io *mc_io,
-+		  u16 dprc_token,
-+		  u32 cmd_flags,
-+		  const struct dpdmux_cfg *cfg,
-+		  u32 *obj_id)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_create *cmd_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CREATE,
-+					  cmd_flags,
-+					  dprc_token);
-+	cmd_params = (struct dpdmux_cmd_create *)cmd.params;
-+	cmd_params->method = cfg->method;
-+	cmd_params->manip = cfg->manip;
-+	cmd_params->num_ifs = cpu_to_le16(cfg->num_ifs);
-+	cmd_params->adv_max_dmat_entries =
-+			cpu_to_le16(cfg->adv.max_dmat_entries);
-+	cmd_params->adv_max_mc_groups = cpu_to_le16(cfg->adv.max_mc_groups);
-+	cmd_params->adv_max_vlan_ids = cpu_to_le16(cfg->adv.max_vlan_ids);
-+	cmd_params->options = cpu_to_le64(cfg->adv.options);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	*obj_id = mc_cmd_hdr_read_token(&cmd);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_destroy() - Destroy the DPDMUX object and release all its resources.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @dprc_token: Parent container token; '0' for default container
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @object_id:	The object id; it must be a valid id within the container that
-+ * created this object;
-+ *
-+ * The function accepts the authentication token of the parent container that
-+ * created the object (not the one that currently owns the object). The object
-+ * is searched within parent using the provided 'object_id'.
-+ * All tokens to the object must be closed before calling destroy.
-+ *
-+ * Return:	'0' on Success; error code otherwise.
-+ */
-+int dpdmux_destroy(struct fsl_mc_io *mc_io,
-+		   u16 dprc_token,
-+		   u32 cmd_flags,
-+		   u32 object_id)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_destroy *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_DESTROY,
-+					  cmd_flags,
-+					  dprc_token);
-+	cmd_params = (struct dpdmux_cmd_destroy *)cmd.params;
-+	cmd_params->dpdmux_id = cpu_to_le32(object_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_enable() - Enable DPDMUX functionality
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_enable(struct fsl_mc_io *mc_io,
-+		  u32 cmd_flags,
-+		  u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_ENABLE,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_disable() - Disable DPDMUX functionality
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_disable(struct fsl_mc_io *mc_io,
-+		   u32 cmd_flags,
-+		   u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_DISABLE,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_is_enabled() - Check if the DPDMUX is enabled.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @en:		Returns '1' if object is enabled; '0' otherwise
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_is_enabled(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      int *en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_rsp_is_enabled *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IS_ENABLED,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpdmux_rsp_is_enabled *)cmd.params;
-+	*en = dpdmux_get_field(rsp_params->en, ENABLE);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_reset() - Reset the DPDMUX, returns the object to initial state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_reset(struct fsl_mc_io *mc_io,
-+		 u32 cmd_flags,
-+		 u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_RESET,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_set_irq_enable() - Set overall interrupt state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Interrupt state - enable = 1, disable = 0
-+ *
-+ * Allows GPP software to control when interrupts are generated.
-+ * Each interrupt can have up to 32 causes.  The enable/disable control's the
-+ * overall interrupt state. if the interrupt is disabled no causes will cause
-+ * an interrupt.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_set_irq_enable(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u8 irq_index,
-+			  u8 en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_set_irq_enable *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_set_irq_enable *)cmd.params;
-+	cmd_params->enable = en;
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_get_irq_enable() - Get overall interrupt state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Returned interrupt state - enable = 1, disable = 0
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_get_irq_enable(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u8 irq_index,
-+			  u8 *en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_get_irq_enable *cmd_params;
-+	struct dpdmux_rsp_get_irq_enable *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_get_irq_enable *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpdmux_rsp_get_irq_enable *)cmd.params;
-+	*en = rsp_params->enable;
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_set_irq_mask() - Set interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	event mask to trigger interrupt;
-+ *		each bit:
-+ *			0 = ignore event
-+ *			1 = consider event for asserting IRQ
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_set_irq_mask(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u8 irq_index,
-+			u32 mask)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_set_irq_mask *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_set_irq_mask *)cmd.params;
-+	cmd_params->mask = cpu_to_le32(mask);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_get_irq_mask() - Get interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	Returned event mask to trigger interrupt
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_get_irq_mask(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u8 irq_index,
-+			u32 *mask)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_get_irq_mask *cmd_params;
-+	struct dpdmux_rsp_get_irq_mask *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_get_irq_mask *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpdmux_rsp_get_irq_mask *)cmd.params;
-+	*mask = le32_to_cpu(rsp_params->mask);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_get_irq_status() - Get the current status of any pending interrupts.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	Returned interrupts status - one bit per cause:
-+ *			0 = no interrupt pending
-+ *			1 = interrupt pending
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_get_irq_status(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u8 irq_index,
-+			  u32 *status)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_get_irq_status *cmd_params;
-+	struct dpdmux_rsp_get_irq_status *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_get_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(*status);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpdmux_rsp_get_irq_status *)cmd.params;
-+	*status = le32_to_cpu(rsp_params->status);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_clear_irq_status() - Clear a pending interrupt's status
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	bits to clear (W1C) - one bit per cause:
-+ *			0 = don't change
-+ *			1 = clear status bit
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_clear_irq_status(struct fsl_mc_io *mc_io,
-+			    u32 cmd_flags,
-+			    u16 token,
-+			    u8 irq_index,
-+			    u32 status)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_clear_irq_status *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CLEAR_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_clear_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(status);
-+	cmd_params->irq_index = irq_index;
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_get_attributes() - Retrieve DPDMUX attributes
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @attr:	Returned object's attributes
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_get_attributes(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  struct dpdmux_attr *attr)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_rsp_get_attr *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_ATTR,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpdmux_rsp_get_attr *)cmd.params;
-+	attr->id = le32_to_cpu(rsp_params->id);
-+	attr->options = le64_to_cpu(rsp_params->options);
-+	attr->method = rsp_params->method;
-+	attr->manip = rsp_params->manip;
-+	attr->num_ifs = le16_to_cpu(rsp_params->num_ifs);
-+	attr->mem_size = le16_to_cpu(rsp_params->mem_size);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_if_enable() - Enable Interface
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @if_id:	Interface Identifier
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_enable(struct fsl_mc_io *mc_io,
-+		     u32 cmd_flags,
-+		     u16 token,
-+		     u16 if_id)
-+{
-+	struct dpdmux_cmd_if *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_if_disable() - Disable Interface
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @if_id:	Interface Identifier
-+ *
-+ * Return:	Completion status. '0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_disable(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      u16 if_id)
-+{
-+	struct dpdmux_cmd_if *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_DISABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_set_max_frame_length() - Set the maximum frame length in DPDMUX
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:		Token of DPDMUX object
-+ * @max_frame_length:	The required maximum frame length
-+ *
-+ * Update the maximum frame length on all DMUX interfaces.
-+ * In case of VEPA, the maximum frame length on all dmux interfaces
-+ * will be updated with the minimum value of the mfls of the connected
-+ * dpnis and the actual value of dmux mfl.
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_set_max_frame_length(struct fsl_mc_io *mc_io,
-+				u32 cmd_flags,
-+				u16 token,
-+				u16 max_frame_length)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_set_max_frame_length *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_MAX_FRAME_LENGTH,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_set_max_frame_length *)cmd.params;
-+	cmd_params->max_frame_length = cpu_to_le16(max_frame_length);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_ul_reset_counters() - Function resets the uplink counter
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_ul_reset_counters(struct fsl_mc_io *mc_io,
-+			     u32 cmd_flags,
-+			     u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_UL_RESET_COUNTERS,
-+					  cmd_flags,
-+					  token);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_if_set_accepted_frames() - Set the accepted frame types
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @if_id:	Interface ID (0 for uplink, or 1-num_ifs);
-+ * @cfg:	Frame types configuration
-+ *
-+ * if 'DPDMUX_ADMIT_ONLY_VLAN_TAGGED' is set - untagged frames or
-+ * priority-tagged frames are discarded.
-+ * if 'DPDMUX_ADMIT_ONLY_UNTAGGED' is set - untagged frames or
-+ * priority-tagged frames are accepted.
-+ * if 'DPDMUX_ADMIT_ALL' is set (default mode) - all VLAN tagged,
-+ * untagged and priority-tagged frame are accepted;
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_set_accepted_frames(struct fsl_mc_io *mc_io,
-+				  u32 cmd_flags,
-+				  u16 token,
-+				  u16 if_id,
-+				  const struct dpdmux_accepted_frames *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_if_set_accepted_frames *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if_set_accepted_frames *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	dpdmux_set_field(cmd_params->frames_options, ACCEPTED_FRAMES_TYPE,
-+			 cfg->type);
-+	dpdmux_set_field(cmd_params->frames_options, UNACCEPTED_FRAMES_ACTION,
-+			 cfg->unaccept_act);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_if_get_attributes() - Obtain DPDMUX interface attributes
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @if_id:	Interface ID (0 for uplink, or 1-num_ifs);
-+ * @attr:	Interface attributes
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_get_attributes(struct fsl_mc_io *mc_io,
-+			     u32 cmd_flags,
-+			     u16 token,
-+			     u16 if_id,
-+			     struct dpdmux_if_attr *attr)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_if *cmd_params;
-+	struct dpdmux_rsp_if_get_attr *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_ATTR,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpdmux_rsp_if_get_attr *)cmd.params;
-+	attr->rate = le32_to_cpu(rsp_params->rate);
-+	attr->enabled = dpdmux_get_field(rsp_params->enabled, ENABLE);
-+	attr->accept_frame_type =
-+			dpdmux_get_field(rsp_params->accepted_frames_type,
-+					 ACCEPTED_FRAMES_TYPE);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_if_remove_l2_rule() - Remove L2 rule from DPDMUX table
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @if_id:	Destination interface ID
-+ * @rule:	L2 rule
-+ *
-+ * Function removes a L2 rule from DPDMUX table
-+ * or adds an interface to an existing multicast address
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_remove_l2_rule(struct fsl_mc_io *mc_io,
-+			     u32 cmd_flags,
-+			     u16 token,
-+			     u16 if_id,
-+			     const struct dpdmux_l2_rule *rule)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_if_l2_rule *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_REMOVE_L2_RULE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if_l2_rule *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	cmd_params->vlan_id = cpu_to_le16(rule->vlan_id);
-+	cmd_params->mac_addr5 = rule->mac_addr[5];
-+	cmd_params->mac_addr4 = rule->mac_addr[4];
-+	cmd_params->mac_addr3 = rule->mac_addr[3];
-+	cmd_params->mac_addr2 = rule->mac_addr[2];
-+	cmd_params->mac_addr1 = rule->mac_addr[1];
-+	cmd_params->mac_addr0 = rule->mac_addr[0];
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_if_add_l2_rule() - Add L2 rule into DPDMUX table
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPDMUX object
-+ * @if_id:	Destination interface ID
-+ * @rule:	L2 rule
-+ *
-+ * Function adds a L2 rule into DPDMUX table
-+ * or adds an interface to an existing multicast address
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_add_l2_rule(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u16 if_id,
-+			  const struct dpdmux_l2_rule *rule)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_if_l2_rule *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_ADD_L2_RULE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if_l2_rule *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	cmd_params->vlan_id = cpu_to_le16(rule->vlan_id);
-+	cmd_params->mac_addr5 = rule->mac_addr[5];
-+	cmd_params->mac_addr4 = rule->mac_addr[4];
-+	cmd_params->mac_addr3 = rule->mac_addr[3];
-+	cmd_params->mac_addr2 = rule->mac_addr[2];
-+	cmd_params->mac_addr1 = rule->mac_addr[1];
-+	cmd_params->mac_addr0 = rule->mac_addr[0];
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_if_get_counter() - Functions obtains specific counter of an interface
-+ * @mc_io: Pointer to MC portal's I/O object
-+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token: Token of DPDMUX object
-+ * @if_id:  Interface Id
-+ * @counter_type: counter type
-+ * @counter: Returned specific counter information
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_get_counter(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u16 if_id,
-+			  enum dpdmux_counter_type counter_type,
-+			  u64 *counter)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_if_get_counter *cmd_params;
-+	struct dpdmux_rsp_if_get_counter *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_COUNTER,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if_get_counter *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	cmd_params->counter_type = counter_type;
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpdmux_rsp_if_get_counter *)cmd.params;
-+	*counter = le64_to_cpu(rsp_params->counter);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_if_set_link_cfg() - set the link configuration.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token: Token of DPSW object
-+ * @if_id: interface id
-+ * @cfg: Link configuration
-+ *
-+ * Return:	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_set_link_cfg(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   u16 if_id,
-+			   struct dpdmux_link_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_if_set_link_cfg *cmd_params;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_SET_LINK_CFG,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if_set_link_cfg *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+	cmd_params->rate = cpu_to_le32(cfg->rate);
-+	cmd_params->options = cpu_to_le64(cfg->options);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_if_get_link_state - Return the link state
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token: Token of DPSW object
-+ * @if_id: interface id
-+ * @state: link state
-+ *
-+ * @returns	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_if_get_link_state(struct fsl_mc_io *mc_io,
-+			     u32 cmd_flags,
-+			     u16 token,
-+			     u16 if_id,
-+			     struct dpdmux_link_state *state)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_cmd_if_get_link_state *cmd_params;
-+	struct dpdmux_rsp_if_get_link_state *rsp_params;
-+	int err;
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_LINK_STATE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_if_get_link_state *)cmd.params;
-+	cmd_params->if_id = cpu_to_le16(if_id);
-+
-+	/* send command to mc*/
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	/* retrieve response parameters */
-+	rsp_params = (struct dpdmux_rsp_if_get_link_state *)cmd.params;
-+	state->rate = le32_to_cpu(rsp_params->rate);
-+	state->options = le64_to_cpu(rsp_params->options);
-+	state->up = dpdmux_get_field(rsp_params->up, ENABLE);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpdmux_set_custom_key - Set a custom classification key.
-+ *
-+ * This API is only available for DPDMUX instance created with
-+ * DPDMUX_METHOD_CUSTOM.  This API must be called before populating the
-+ * classification table using dpdmux_add_custom_cls_entry.
-+ *
-+ * Calls to dpdmux_set_custom_key remove all existing classification entries
-+ * that may have been added previously using dpdmux_add_custom_cls_entry.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token: Token of DPSW object
-+ * @if_id: interface id
-+ * @key_cfg_iova: DMA address of a configuration structure set up using
-+ *		  dpkg_prepare_key_cfg. Maximum key size is 24 bytes.
-+ *
-+ * @returns	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_set_custom_key(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u64 key_cfg_iova)
-+{
-+	struct dpdmux_set_custom_key *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_CUSTOM_KEY,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_set_custom_key *)cmd.params;
-+	cmd_params->key_cfg_iova = cpu_to_le64(key_cfg_iova);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_add_custom_cls_entry - Adds a custom classification entry.
-+ *
-+ * This API is only available for DPDMUX instances created with
-+ * DPDMUX_METHOD_CUSTOM.  Before calling this function a classification key
-+ * composition rule must be set up using dpdmux_set_custom_key.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token: Token of DPSW object
-+ * @rule: Classification rule to insert.  Rules cannot be duplicated, if a
-+ *	matching rule already exists, the action will be replaced.
-+ * @action: Action to perform for matching traffic.
-+ *
-+ * @returns	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_add_custom_cls_entry(struct fsl_mc_io *mc_io,
-+				u32 cmd_flags,
-+				u16 token,
-+				struct dpdmux_rule_cfg *rule,
-+				struct dpdmux_cls_action *action)
-+{
-+	struct dpdmux_cmd_add_custom_cls_entry *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_ADD_CUSTOM_CLS_ENTRY,
-+					  cmd_flags,
-+					  token);
-+
-+	cmd_params = (struct dpdmux_cmd_add_custom_cls_entry *)cmd.params;
-+	cmd_params->key_size = rule->key_size;
-+	cmd_params->dest_if = cpu_to_le16(action->dest_if);
-+	cmd_params->key_iova = cpu_to_le64(rule->key_iova);
-+	cmd_params->mask_iova = cpu_to_le64(rule->mask_iova);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_remove_custom_cls_entry - Removes a custom classification entry.
-+ *
-+ * This API is only available for DPDMUX instances created with
-+ * DPDMUX_METHOD_CUSTOM.  The API can be used to remove classification
-+ * entries previously inserted using dpdmux_add_custom_cls_entry.
-+ *
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token: Token of DPSW object
-+ * @rule: Classification rule to remove
-+ *
-+ * @returns	'0' on Success; Error code otherwise.
-+ */
-+int dpdmux_remove_custom_cls_entry(struct fsl_mc_io *mc_io,
-+				   u32 cmd_flags,
-+				   u16 token,
-+				   struct dpdmux_rule_cfg *rule)
-+{
-+	struct dpdmux_cmd_remove_custom_cls_entry *cmd_params;
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	/* prepare command */
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_REMOVE_CUSTOM_CLS_ENTRY,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpdmux_cmd_remove_custom_cls_entry *)cmd.params;
-+	cmd_params->key_size = rule->key_size;
-+	cmd_params->key_iova = cpu_to_le64(rule->key_iova);
-+	cmd_params->mask_iova = cpu_to_le64(rule->mask_iova);
-+
-+	/* send command to mc*/
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpdmux_get_api_version() - Get Data Path Demux API version
-+ * @mc_io:  Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @major_ver:	Major version of data path demux API
-+ * @minor_ver:	Minor version of data path demux API
-+ *
-+ * Return:  '0' on Success; Error code otherwise.
-+ */
-+int dpdmux_get_api_version(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 *major_ver,
-+			   u16 *minor_ver)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpdmux_rsp_get_api_version *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_API_VERSION,
-+					cmd_flags,
-+					0);
-+
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpdmux_rsp_get_api_version *)cmd.params;
-+	*major_ver = le16_to_cpu(rsp_params->major);
-+	*minor_ver = le16_to_cpu(rsp_params->minor);
-+
-+	return 0;
-+}
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/evb/dpdmux.h
-@@ -0,0 +1,453 @@
-+/* Copyright 2013-2015 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#ifndef __FSL_DPDMUX_H
-+#define __FSL_DPDMUX_H
-+
-+struct fsl_mc_io;
-+
-+/* Data Path Demux API
-+ * Contains API for handling DPDMUX topology and functionality
-+ */
-+
-+int dpdmux_open(struct fsl_mc_io *mc_io,
-+		u32 cmd_flags,
-+		int dpdmux_id,
-+		u16 *token);
-+
-+int dpdmux_close(struct fsl_mc_io *mc_io,
-+		 u32 cmd_flags,
-+		 u16 token);
-+
-+/**
-+ * DPDMUX general options
-+ */
-+
-+/**
-+ * Enable bridging between internal interfaces
-+ */
-+#define DPDMUX_OPT_BRIDGE_EN	0x0000000000000002ULL
-+
-+/**
-+ * Mask support for classification
-+ */
-+#define DPDMUX_OPT_CLS_MASK_SUPPORT		0x0000000000000020ULL
-+
-+#define DPDMUX_IRQ_INDEX_IF	0x0000
-+#define DPDMUX_IRQ_INDEX	0x0001
-+
-+/**
-+ * IRQ event - Indicates that the link state changed
-+ */
-+#define DPDMUX_IRQ_EVENT_LINK_CHANGED	0x0001
-+
-+/**
-+ * enum dpdmux_manip - DPDMUX manipulation operations
-+ * @DPDMUX_MANIP_NONE:	No manipulation on frames
-+ * @DPDMUX_MANIP_ADD_REMOVE_S_VLAN: Add S-VLAN on egress, remove it on ingress
-+ */
-+enum dpdmux_manip {
-+	DPDMUX_MANIP_NONE = 0x0,
-+	DPDMUX_MANIP_ADD_REMOVE_S_VLAN = 0x1
-+};
-+
-+/**
-+ * enum dpdmux_method - DPDMUX method options
-+ * @DPDMUX_METHOD_NONE: no DPDMUX method
-+ * @DPDMUX_METHOD_C_VLAN_MAC: DPDMUX based on C-VLAN and MAC address
-+ * @DPDMUX_METHOD_MAC: DPDMUX based on MAC address
-+ * @DPDMUX_METHOD_C_VLAN: DPDMUX based on C-VLAN
-+ * @DPDMUX_METHOD_S_VLAN: DPDMUX based on S-VLAN
-+ */
-+enum dpdmux_method {
-+	DPDMUX_METHOD_NONE = 0x0,
-+	DPDMUX_METHOD_C_VLAN_MAC = 0x1,
-+	DPDMUX_METHOD_MAC = 0x2,
-+	DPDMUX_METHOD_C_VLAN = 0x3,
-+	DPDMUX_METHOD_S_VLAN = 0x4,
-+	DPDMUX_METHOD_CUSTOM = 0x5
-+};
-+
-+/**
-+ * struct dpdmux_cfg - DPDMUX configuration parameters
-+ * @method: Defines the operation method for the DPDMUX address table
-+ * @manip: Required manipulation operation
-+ * @num_ifs: Number of interfaces (excluding the uplink interface)
-+ * @adv: Advanced parameters; default is all zeros;
-+ *	 use this structure to change default settings
-+ */
-+struct dpdmux_cfg {
-+	enum dpdmux_method method;
-+	enum dpdmux_manip manip;
-+	u16 num_ifs;
-+	/**
-+	 * struct adv - Advanced parameters
-+	 * @options: DPDMUX options - combination of 'DPDMUX_OPT_<X>' flags
-+	 * @max_dmat_entries: Maximum entries in DPDMUX address table
-+	 *		0 - indicates default: 64 entries per interface.
-+	 * @max_mc_groups: Number of multicast groups in DPDMUX table
-+	 *		0 - indicates default: 32 multicast groups
-+	 * @max_vlan_ids: max vlan ids allowed in the system -
-+	 *		relevant only case of working in mac+vlan method.
-+	 *		0 - indicates default 16 vlan ids.
-+	 */
-+	struct {
-+		u64 options;
-+		u16 max_dmat_entries;
-+		u16 max_mc_groups;
-+		u16 max_vlan_ids;
-+	} adv;
-+};
-+
-+int dpdmux_create(struct fsl_mc_io *mc_io,
-+		  u16 dprc_token,
-+		  u32 cmd_flags,
-+		  const struct dpdmux_cfg *cfg,
-+		  u32 *obj_id);
-+
-+int dpdmux_destroy(struct fsl_mc_io *mc_io,
-+		   u16 dprc_token,
-+		   u32 cmd_flags,
-+		   u32 object_id);
-+
-+int dpdmux_enable(struct fsl_mc_io *mc_io,
-+		  u32 cmd_flags,
-+		  u16 token);
-+
-+int dpdmux_disable(struct fsl_mc_io *mc_io,
-+		   u32 cmd_flags,
-+		   u16 token);
-+
-+int dpdmux_is_enabled(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      int *en);
-+
-+int dpdmux_reset(struct fsl_mc_io *mc_io,
-+		 u32 cmd_flags,
-+		 u16 token);
-+
-+int dpdmux_set_irq_enable(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u8 irq_index,
-+			  u8 en);
-+
-+int dpdmux_get_irq_enable(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u8 irq_index,
-+			  u8 *en);
-+
-+int dpdmux_set_irq_mask(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u8 irq_index,
-+			u32 mask);
-+
-+int dpdmux_get_irq_mask(struct fsl_mc_io *mc_io,
-+			u32 cmd_flags,
-+			u16 token,
-+			u8 irq_index,
-+			u32 *mask);
-+
-+int dpdmux_get_irq_status(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u8 irq_index,
-+			  u32 *status);
-+
-+int dpdmux_clear_irq_status(struct fsl_mc_io *mc_io,
-+			    u32 cmd_flags,
-+			    u16 token,
-+			    u8 irq_index,
-+			    u32 status);
-+
-+/**
-+ * struct dpdmux_attr - Structure representing DPDMUX attributes
-+ * @id: DPDMUX object ID
-+ * @options: Configuration options (bitmap)
-+ * @method: DPDMUX address table method
-+ * @manip: DPDMUX manipulation type
-+ * @num_ifs: Number of interfaces (excluding the uplink interface)
-+ * @mem_size: DPDMUX frame storage memory size
-+ */
-+struct dpdmux_attr {
-+	int id;
-+	u64 options;
-+	enum dpdmux_method method;
-+	enum dpdmux_manip manip;
-+	u16 num_ifs;
-+	u16 mem_size;
-+};
-+
-+int dpdmux_get_attributes(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  struct dpdmux_attr *attr);
-+
-+int dpdmux_set_max_frame_length(struct fsl_mc_io *mc_io,
-+				u32 cmd_flags,
-+				u16 token,
-+				u16 max_frame_length);
-+
-+/**
-+ * enum dpdmux_counter_type - Counter types
-+ * @DPDMUX_CNT_ING_FRAME: Counts ingress frames
-+ * @DPDMUX_CNT_ING_BYTE: Counts ingress bytes
-+ * @DPDMUX_CNT_ING_FLTR_FRAME: Counts filtered ingress frames
-+ * @DPDMUX_CNT_ING_FRAME_DISCARD: Counts discarded ingress frames
-+ * @DPDMUX_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
-+ * @DPDMUX_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
-+ * @DPDMUX_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
-+ * @DPDMUX_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
-+ * @DPDMUX_CNT_EGR_FRAME: Counts egress frames
-+ * @DPDMUX_CNT_EGR_BYTE: Counts egress bytes
-+ * @DPDMUX_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames
-+ */
-+enum dpdmux_counter_type {
-+	DPDMUX_CNT_ING_FRAME = 0x0,
-+	DPDMUX_CNT_ING_BYTE = 0x1,
-+	DPDMUX_CNT_ING_FLTR_FRAME = 0x2,
-+	DPDMUX_CNT_ING_FRAME_DISCARD = 0x3,
-+	DPDMUX_CNT_ING_MCAST_FRAME = 0x4,
-+	DPDMUX_CNT_ING_MCAST_BYTE = 0x5,
-+	DPDMUX_CNT_ING_BCAST_FRAME = 0x6,
-+	DPDMUX_CNT_ING_BCAST_BYTES = 0x7,
-+	DPDMUX_CNT_EGR_FRAME = 0x8,
-+	DPDMUX_CNT_EGR_BYTE = 0x9,
-+	DPDMUX_CNT_EGR_FRAME_DISCARD = 0xa
-+};
-+
-+/**
-+ * enum dpdmux_accepted_frames_type - DPDMUX frame types
-+ * @DPDMUX_ADMIT_ALL: The device accepts VLAN tagged, untagged and
-+ *			priority-tagged frames
-+ * @DPDMUX_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or
-+ *				priority-tagged frames that are received on this
-+ *				interface
-+ * @DPDMUX_ADMIT_ONLY_UNTAGGED: Untagged frames or priority-tagged frames
-+ *				received on this interface are accepted
-+ */
-+enum dpdmux_accepted_frames_type {
-+	DPDMUX_ADMIT_ALL = 0,
-+	DPDMUX_ADMIT_ONLY_VLAN_TAGGED = 1,
-+	DPDMUX_ADMIT_ONLY_UNTAGGED = 2
-+};
-+
-+/**
-+ * enum dpdmux_action - DPDMUX action for un-accepted frames
-+ * @DPDMUX_ACTION_DROP: Drop un-accepted frames
-+ * @DPDMUX_ACTION_REDIRECT_TO_CTRL: Redirect un-accepted frames to the
-+ *					control interface
-+ */
-+enum dpdmux_action {
-+	DPDMUX_ACTION_DROP = 0,
-+	DPDMUX_ACTION_REDIRECT_TO_CTRL = 1
-+};
-+
-+/**
-+ * struct dpdmux_accepted_frames - Frame types configuration
-+ * @type: Defines ingress accepted frames
-+ * @unaccept_act: Defines action on frames not accepted
-+ */
-+struct dpdmux_accepted_frames {
-+	enum dpdmux_accepted_frames_type type;
-+	enum dpdmux_action unaccept_act;
-+};
-+
-+int dpdmux_if_set_accepted_frames(struct fsl_mc_io *mc_io,
-+				  u32 cmd_flags,
-+				  u16 token,
-+				  u16 if_id,
-+				  const struct dpdmux_accepted_frames *cfg);
-+
-+/**
-+ * struct dpdmux_if_attr - Structure representing frame types configuration
-+ * @rate: Configured interface rate (in bits per second)
-+ * @enabled: Indicates if interface is enabled
-+ * @accept_frame_type: Indicates type of accepted frames for the interface
-+ */
-+struct dpdmux_if_attr {
-+	u32 rate;
-+	int enabled;
-+	enum dpdmux_accepted_frames_type accept_frame_type;
-+};
-+
-+int dpdmux_if_get_attributes(struct fsl_mc_io *mc_io,
-+			     u32 cmd_flags,
-+			     u16 token,
-+			     u16 if_id,
-+			     struct dpdmux_if_attr *attr);
-+
-+int dpdmux_if_enable(struct fsl_mc_io *mc_io,
-+		     u32 cmd_flags,
-+		     u16 token,
-+		     u16 if_id);
-+
-+int dpdmux_if_disable(struct fsl_mc_io *mc_io,
-+		      u32 cmd_flags,
-+		      u16 token,
-+		      u16 if_id);
-+
-+/**
-+ * struct dpdmux_l2_rule - Structure representing L2 rule
-+ * @mac_addr: MAC address
-+ * @vlan_id: VLAN ID
-+ */
-+struct dpdmux_l2_rule {
-+	u8 mac_addr[6];
-+	u16 vlan_id;
-+};
-+
-+int dpdmux_if_remove_l2_rule(struct fsl_mc_io *mc_io,
-+			     u32 cmd_flags,
-+			     u16 token,
-+			     u16 if_id,
-+			     const struct dpdmux_l2_rule *rule);
-+
-+int dpdmux_if_add_l2_rule(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u16 if_id,
-+			  const struct dpdmux_l2_rule *rule);
-+
-+int dpdmux_if_get_counter(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u16 if_id,
-+			  enum dpdmux_counter_type counter_type,
-+			  u64 *counter);
-+
-+int dpdmux_ul_reset_counters(struct fsl_mc_io *mc_io,
-+			     u32 cmd_flags,
-+			     u16 token);
-+
-+/**
-+ * Enable auto-negotiation
-+ */
-+#define DPDMUX_LINK_OPT_AUTONEG		0x0000000000000001ULL
-+/**
-+ * Enable half-duplex mode
-+ */
-+#define DPDMUX_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
-+/**
-+ * Enable pause frames
-+ */
-+#define DPDMUX_LINK_OPT_PAUSE		0x0000000000000004ULL
-+/**
-+ * Enable a-symmetric pause frames
-+ */
-+#define DPDMUX_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
-+
-+/**
-+ * struct dpdmux_link_cfg - Structure representing DPDMUX link configuration
-+ * @rate: Rate
-+ * @options: Mask of available options; use 'DPDMUX_LINK_OPT_<X>' values
-+ */
-+struct dpdmux_link_cfg {
-+	u32 rate;
-+	u64 options;
-+};
-+
-+int dpdmux_if_set_link_cfg(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 token,
-+			   u16 if_id,
-+			   struct dpdmux_link_cfg *cfg);
-+/**
-+ * struct dpdmux_link_state - Structure representing DPDMUX link state
-+ * @rate: Rate
-+ * @options: Mask of available options; use 'DPDMUX_LINK_OPT_<X>' values
-+ * @up: 0 - down, 1 - up
-+ */
-+struct dpdmux_link_state {
-+	u32 rate;
-+	u64 options;
-+	int      up;
-+};
-+
-+int dpdmux_if_get_link_state(struct fsl_mc_io *mc_io,
-+			     u32 cmd_flags,
-+			     u16 token,
-+			     u16 if_id,
-+			     struct dpdmux_link_state *state);
-+
-+int dpdmux_set_custom_key(struct fsl_mc_io *mc_io,
-+			  u32 cmd_flags,
-+			  u16 token,
-+			  u64 key_cfg_iova);
-+
-+/**
-+ * struct dpdmux_rule_cfg - Custom classification rule.
-+ *
-+ * @key_iova: DMA address of buffer storing the look-up value
-+ * @mask_iova: DMA address of the mask used for TCAM classification
-+ * @key_size: size, in bytes, of the look-up value. This must match the size
-+ *	of the look-up key defined using dpdmux_set_custom_key, otherwise the
-+ *	entry will never be hit
-+ */
-+struct dpdmux_rule_cfg {
-+	u64 key_iova;
-+	u64 mask_iova;
-+	u8 key_size;
-+};
-+
-+/**
-+ * struct dpdmux_cls_action - Action to execute for frames matching the
-+ *	classification entry
-+ *
-+ * @dest_if: Interface to forward the frames to. Port numbering is similar to
-+ *	the one used to connect interfaces:
-+ *	- 0 is the uplink port,
-+ *	- all others are downlink ports.
-+ */
-+struct dpdmux_cls_action {
-+	u16 dest_if;
-+};
-+
-+int dpdmux_add_custom_cls_entry(struct fsl_mc_io *mc_io,
-+				u32 cmd_flags,
-+				u16 token,
-+				struct dpdmux_rule_cfg *rule,
-+				struct dpdmux_cls_action *action);
-+
-+int dpdmux_remove_custom_cls_entry(struct fsl_mc_io *mc_io,
-+				   u32 cmd_flags,
-+				   u16 token,
-+				   struct dpdmux_rule_cfg *rule);
-+
-+int dpdmux_get_api_version(struct fsl_mc_io *mc_io,
-+			   u32 cmd_flags,
-+			   u16 *major_ver,
-+			   u16 *minor_ver);
-+
-+#endif /* __FSL_DPDMUX_H */
---- /dev/null
-+++ b/drivers/staging/fsl-dpaa2/evb/evb.c
-@@ -0,0 +1,1353 @@
-+/* Copyright 2015 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the name of Freescale Semiconductor nor the
-+ *	 names of its contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
-+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
-+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#include <linux/module.h>
-+#include <linux/msi.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/rtnetlink.h>
-+#include <linux/if_vlan.h>
-+
-+#include <uapi/linux/if_bridge.h>
-+#include <net/netlink.h>
-+
-+#include <linux/fsl/mc.h>
-+
-+#include "dpdmux.h"
-+#include "dpdmux-cmd.h"
-+
-+static const char evb_drv_version[] = "0.1";
-+
-+/* Minimal supported DPDMUX version */
-+#define DPDMUX_MIN_VER_MAJOR			6
-+#define DPDMUX_MIN_VER_MINOR			0
-+
-+/* IRQ index */
-+#define DPDMUX_MAX_IRQ_NUM			2
-+
-+/* MAX FRAME LENGTH (currently 10k) */
-+#define EVB_MAX_FRAME_LENGTH		(10 * 1024)
-+#define EVB_MAX_MTU			(EVB_MAX_FRAME_LENGTH - VLAN_ETH_HLEN)
-+#define EVB_MIN_MTU			68
-+
-+struct evb_port_priv {
-+	struct net_device	*netdev;
-+	struct list_head	list;
-+	u16			port_index;
-+	struct evb_priv		*evb_priv;
-+	u8			vlans[VLAN_VID_MASK + 1];
-+};
-+
-+struct evb_priv {
-+	/* keep first */
-+	struct evb_port_priv	uplink;
-+
-+	struct fsl_mc_io	*mc_io;
-+	struct list_head	port_list;
-+	struct dpdmux_attr	attr;
-+	u16			mux_handle;
-+	int			dev_id;
-+};
-+
-+static int _evb_port_carrier_state_sync(struct net_device *netdev)
-+{
-+	struct evb_port_priv		*port_priv = netdev_priv(netdev);
-+	struct dpdmux_link_state	state;
-+	int err;
-+
-+	err = dpdmux_if_get_link_state(port_priv->evb_priv->mc_io, 0,
-+				       port_priv->evb_priv->mux_handle,
-+				       port_priv->port_index, &state);
-+	if (unlikely(err)) {
-+		netdev_err(netdev, "dpdmux_if_get_link_state() err %d\n", err);
-+		return err;
-+	}
-+
-+	WARN_ONCE(state.up > 1, "Garbage read into link_state");
-+
-+	if (state.up)
-+		netif_carrier_on(port_priv->netdev);
-+	else
-+		netif_carrier_off(port_priv->netdev);
-+
-+	return 0;
-+}
-+
-+static int evb_port_open(struct net_device *netdev)
-+{
-+	int			err;
-+
-+	/* FIXME: enable port when support added */
-+
-+	err = _evb_port_carrier_state_sync(netdev);
-+	if (err) {
-+		netdev_err(netdev, "ethsw_port_carrier_state_sync err %d\n",
-+			   err);
-+		return err;
-+	}
-+
-+	return 0;
-+}
-+
-+static netdev_tx_t evb_dropframe(struct sk_buff *skb, struct net_device *dev)
-+{
-+	/* we don't support I/O for now, drop the frame */
-+	dev_kfree_skb_any(skb);
-+	return NETDEV_TX_OK;
-+}
-+
-+static int evb_links_state_update(struct evb_priv *priv)
-+{
-+	struct evb_port_priv	*port_priv;
-+	struct list_head	*pos;
-+	int err;
-+
-+	list_for_each(pos, &priv->port_list) {
-+		port_priv = list_entry(pos, struct evb_port_priv, list);
-+
-+		err = _evb_port_carrier_state_sync(port_priv->netdev);
-+		if (err)
-+			netdev_err(port_priv->netdev,
-+				   "_evb_port_carrier_state_sync err %d\n",
-+				   err);
-+	}
-+
-+	return 0;
-+}
-+
-+static irqreturn_t evb_irq0_handler(int irq_num, void *arg)
-+{
-+	return IRQ_WAKE_THREAD;
-+}
-+
-+static irqreturn_t _evb_irq0_handler_thread(int irq_num, void *arg)
-+{
-+	struct device		*dev = (struct device *)arg;
-+	struct fsl_mc_device	*evb_dev = to_fsl_mc_device(dev);
-+	struct net_device	*netdev = dev_get_drvdata(dev);
-+	struct evb_priv		*priv = netdev_priv(netdev);
-+	struct fsl_mc_io	*io = priv->mc_io;
-+	u16 token = priv->mux_handle;
-+	int irq_index = DPDMUX_IRQ_INDEX_IF;
-+
-+	/* Mask the events and the if_id reserved bits to be cleared on read */
-+	u32 status = DPDMUX_IRQ_EVENT_LINK_CHANGED | 0xFFFF0000;
-+	int err;
-+
-+	/* Sanity check */
-+	if (WARN_ON(!evb_dev || !evb_dev->irqs || !evb_dev->irqs[irq_index]))
-+		goto out;
-+	if (WARN_ON(evb_dev->irqs[irq_index]->msi_desc->irq != (u32)irq_num))
-+		goto out;
-+
-+	err = dpdmux_get_irq_status(io, 0, token, irq_index, &status);
-+	if (unlikely(err)) {
-+		netdev_err(netdev, "Can't get irq status (err %d)", err);
-+		err = dpdmux_clear_irq_status(io, 0, token, irq_index,
-+					      0xFFFFFFFF);
-+		if (unlikely(err))
-+			netdev_err(netdev, "Can't clear irq status (err %d)",
-+				   err);
-+		goto out;
-+	}
-+
-+	if (status & DPDMUX_IRQ_EVENT_LINK_CHANGED) {
-+		err = evb_links_state_update(priv);
-+		if (unlikely(err))
-+			goto out;
-+	}
-+
-+out:
-+	return IRQ_HANDLED;
-+}
-+
-+static int evb_setup_irqs(struct fsl_mc_device *evb_dev)
-+{
-+	struct device		*dev = &evb_dev->dev;
-+	struct net_device	*netdev = dev_get_drvdata(dev);
-+	struct evb_priv		*priv = netdev_priv(netdev);
-+	int err = 0;
-+	struct fsl_mc_device_irq *irq;
-+	const int irq_index = DPDMUX_IRQ_INDEX_IF;
-+	u32 mask = DPDMUX_IRQ_EVENT_LINK_CHANGED;
-+
-+	err = fsl_mc_allocate_irqs(evb_dev);
-+	if (unlikely(err)) {
-+		dev_err(dev, "MC irqs allocation failed\n");
-+		return err;
-+	}
-+
-+	if (WARN_ON(evb_dev->obj_desc.irq_count != DPDMUX_MAX_IRQ_NUM)) {
-+		err = -EINVAL;
-+		goto free_irq;
-+	}
-+
-+	err = dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle,
-+				    irq_index, 0);
-+	if (unlikely(err)) {
-+		dev_err(dev, "dpdmux_set_irq_enable err %d\n", err);
-+		goto free_irq;
-+	}
-+
-+	irq = evb_dev->irqs[irq_index];
-+
-+	err = devm_request_threaded_irq(dev, irq->msi_desc->irq,
-+					evb_irq0_handler,
-+					_evb_irq0_handler_thread,
-+					IRQF_NO_SUSPEND | IRQF_ONESHOT,
-+					dev_name(dev), dev);
-+	if (unlikely(err)) {
-+		dev_err(dev, "devm_request_threaded_irq(): %d", err);
-+		goto free_irq;
-+	}
-+
-+	err = dpdmux_set_irq_mask(priv->mc_io, 0, priv->mux_handle,
-+				  irq_index, mask);
-+	if (unlikely(err)) {
-+		dev_err(dev, "dpdmux_set_irq_mask(): %d", err);
-+		goto free_devm_irq;
-+	}
-+
-+	err = dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle,
-+				    irq_index, 1);
-+	if (unlikely(err)) {
-+		dev_err(dev, "dpdmux_set_irq_enable(): %d", err);
-+		goto free_devm_irq;
-+	}
-+
-+	return 0;
-+
-+free_devm_irq:
-+	devm_free_irq(dev, irq->msi_desc->irq, dev);
-+free_irq:
-+	fsl_mc_free_irqs(evb_dev);
-+	return err;
-+}
-+
-+static void evb_teardown_irqs(struct fsl_mc_device *evb_dev)
-+{
-+	struct device		*dev = &evb_dev->dev;
-+	struct net_device	*netdev = dev_get_drvdata(dev);
-+	struct evb_priv		*priv = netdev_priv(netdev);
-+
-+	dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle,
-+			      DPDMUX_IRQ_INDEX_IF, 0);
-+
-+	devm_free_irq(dev,
-+		      evb_dev->irqs[DPDMUX_IRQ_INDEX_IF]->msi_desc->irq,
-+		      dev);
-+	fsl_mc_free_irqs(evb_dev);
-+}
-+
-+static int evb_port_add_rule(struct net_device *netdev,
-+			     const unsigned char *addr, u16 vid)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	struct dpdmux_l2_rule	rule = { .vlan_id = vid };
-+	int			err;
-+
-+	if (addr)
-+		ether_addr_copy(rule.mac_addr, addr);
-+
-+	err = dpdmux_if_add_l2_rule(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index, &rule);
-+	if (unlikely(err))
-+		netdev_err(netdev, "dpdmux_if_add_l2_rule err %d\n", err);
-+	return err;
-+}
-+
-+static int evb_port_del_rule(struct net_device *netdev,
-+			     const unsigned char *addr, u16 vid)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	struct dpdmux_l2_rule	rule = { .vlan_id = vid };
-+	int err;
-+
-+	if (addr)
-+		ether_addr_copy(rule.mac_addr, addr);
-+
-+	err = dpdmux_if_remove_l2_rule(port_priv->evb_priv->mc_io,
-+				       0,
-+				       port_priv->evb_priv->mux_handle,
-+				       port_priv->port_index, &rule);
-+	if (unlikely(err))
-+		netdev_err(netdev, "dpdmux_if_remove_l2_rule err %d\n", err);
-+	return err;
-+}
-+
-+static bool _lookup_address(struct net_device *netdev,
-+			    const unsigned char *addr)
-+{
-+	struct netdev_hw_addr	   *ha;
-+	struct netdev_hw_addr_list *list = (is_unicast_ether_addr(addr)) ?
-+					   &netdev->uc : &netdev->mc;
-+
-+	netif_addr_lock_bh(netdev);
-+	list_for_each_entry(ha, &list->list, list) {
-+		if (ether_addr_equal(ha->addr, addr)) {
-+			netif_addr_unlock_bh(netdev);
-+			return true;
-+		}
-+	}
-+	netif_addr_unlock_bh(netdev);
-+	return false;
-+}
-+
-+static inline int evb_port_fdb_prep(struct nlattr *tb[],
-+				    struct net_device *netdev,
-+				    const unsigned char *addr, u16 *vid,
-+				    bool del)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	struct evb_priv		*evb_priv = port_priv->evb_priv;
-+
-+	*vid = 0;
-+
-+	if (evb_priv->attr.method != DPDMUX_METHOD_MAC &&
-+	    evb_priv->attr.method != DPDMUX_METHOD_C_VLAN_MAC) {
-+		netdev_err(netdev,
-+			   "EVB mode does not support MAC classification\n");
-+		return -EOPNOTSUPP;
-+	}
-+
-+	/* check if the address is configured on this port */
-+	if (_lookup_address(netdev, addr)) {
-+		if (!del)
-+			return -EEXIST;
-+	} else {
-+		if (del)
-+			return -ENOENT;
-+	}
-+
-+	if (tb[NDA_VLAN] && evb_priv->attr.method == DPDMUX_METHOD_C_VLAN_MAC) {
-+		if (nla_len(tb[NDA_VLAN]) != sizeof(unsigned short)) {
-+			netdev_err(netdev, "invalid vlan size %d\n",
-+				   nla_len(tb[NDA_VLAN]));
-+			return -EINVAL;
-+		}
-+
-+		*vid = nla_get_u16(tb[NDA_VLAN]);
-+
-+		if (!*vid || *vid >= VLAN_VID_MASK) {
-+			netdev_err(netdev, "invalid vid value 0x%04x\n", *vid);
-+			return -EINVAL;
-+		}
-+	} else if (evb_priv->attr.method == DPDMUX_METHOD_C_VLAN_MAC) {
-+		netdev_err(netdev,
-+			   "EVB mode requires explicit VLAN configuration\n");
-+		return -EINVAL;
-+	} else if (tb[NDA_VLAN]) {
-+		netdev_warn(netdev, "VLAN not supported, argument ignored\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static int evb_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
-+			    struct net_device *netdev,
-+			    const unsigned char *addr, u16 vid, u16 flags)
-+{
-+	u16 _vid;
-+	int err;
-+
-+	/* TODO: add replace support when added to iproute bridge */
-+	if (!(flags & NLM_F_REQUEST)) {
-+		netdev_err(netdev,
-+			   "evb_port_fdb_add unexpected flags value %08x\n",
-+			   flags);
-+		return -EINVAL;
-+	}
-+
-+	err = evb_port_fdb_prep(tb, netdev, addr, &_vid, 0);
-+	if (unlikely(err))
-+		return err;
-+
-+	err = evb_port_add_rule(netdev, addr, _vid);
-+	if (unlikely(err))
-+		return err;
-+
-+	if (is_unicast_ether_addr(addr)) {
-+		err = dev_uc_add(netdev, addr);
-+		if (unlikely(err)) {
-+			netdev_err(netdev, "dev_uc_add err %d\n", err);
-+			return err;
-+		}
-+	} else {
-+		err = dev_mc_add(netdev, addr);
-+		if (unlikely(err)) {
-+			netdev_err(netdev, "dev_mc_add err %d\n", err);
-+			return err;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int evb_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
-+			    struct net_device *netdev,
-+			    const unsigned char *addr, u16 vid)
-+{
-+	u16 _vid;
-+	int err;
-+
-+	err = evb_port_fdb_prep(tb, netdev, addr, &_vid, 1);
-+	if (unlikely(err))
-+		return err;
-+
-+	err = evb_port_del_rule(netdev, addr, _vid);
-+	if (unlikely(err))
-+		return err;
-+
-+	if (is_unicast_ether_addr(addr)) {
-+		err = dev_uc_del(netdev, addr);
-+		if (unlikely(err)) {
-+			netdev_err(netdev, "dev_uc_del err %d\n", err);
-+			return err;
-+		}
-+	} else {
-+		err = dev_mc_del(netdev, addr);
-+		if (unlikely(err)) {
-+			netdev_err(netdev, "dev_mc_del err %d\n", err);
-+			return err;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int evb_change_mtu(struct net_device *netdev,
-+			  int mtu)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	struct evb_priv		*evb_priv = port_priv->evb_priv;
-+	struct list_head	*pos;
-+	int			err = 0;
-+
-+	/* This operation is not permitted on downlinks */
-+	if (port_priv->port_index > 0)
-+		return -EPERM;
-+
-+	err = dpdmux_set_max_frame_length(evb_priv->mc_io,
-+					  0,
-+					  evb_priv->mux_handle,
-+					  (uint16_t)(mtu + VLAN_ETH_HLEN));
-+
-+	if (unlikely(err)) {
-+		netdev_err(netdev, "dpdmux_ul_set_max_frame_length err %d\n",
-+			   err);
-+		return err;
-+	}
-+
-+	/* Update the max frame length for downlinks */
-+	list_for_each(pos, &evb_priv->port_list) {
-+		port_priv = list_entry(pos, struct evb_port_priv, list);
-+		port_priv->netdev->mtu = mtu;
-+	}
-+
-+	netdev->mtu = mtu;
-+	return 0;
-+}
-+
-+static const struct nla_policy ifla_br_policy[IFLA_MAX + 1] = {
-+	[IFLA_BRIDGE_FLAGS]	= { .type = NLA_U16 },
-+	[IFLA_BRIDGE_MODE]	= { .type = NLA_U16 },
-+	[IFLA_BRIDGE_VLAN_INFO]	= { .type = NLA_BINARY,
-+				.len = sizeof(struct bridge_vlan_info), },
-+};
-+
-+static int evb_setlink_af_spec(struct net_device *netdev,
-+			       struct nlattr **tb)
-+{
-+	struct bridge_vlan_info	*vinfo;
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	int			err = 0;
-+
-+	if (!tb[IFLA_BRIDGE_VLAN_INFO]) {
-+		netdev_err(netdev, "no VLAN INFO in nlmsg\n");
-+		return -EOPNOTSUPP;
-+	}
-+
-+	vinfo = nla_data(tb[IFLA_BRIDGE_VLAN_INFO]);
-+
-+	if (!vinfo->vid || vinfo->vid > VLAN_VID_MASK)
-+		return -EINVAL;
-+
-+	err = evb_port_add_rule(netdev, NULL, vinfo->vid);
-+	if (unlikely(err))
-+		return err;
-+
-+	port_priv->vlans[vinfo->vid] = 1;
-+
-+	return 0;
-+}
-+
-+static int evb_setlink(struct net_device *netdev,
-+		       struct nlmsghdr *nlh,
-+		       u16 flags)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	struct evb_priv		*evb_priv = port_priv->evb_priv;
-+	struct nlattr		*attr;
-+	struct nlattr		*tb[(IFLA_BRIDGE_MAX > IFLA_BRPORT_MAX) ?
-+					IFLA_BRIDGE_MAX : IFLA_BRPORT_MAX + 1];
-+	int			err = 0;
-+
-+	if (evb_priv->attr.method != DPDMUX_METHOD_C_VLAN &&
-+	    evb_priv->attr.method != DPDMUX_METHOD_S_VLAN) {
-+		netdev_err(netdev,
-+			   "EVB mode does not support VLAN only classification\n");
-+		return -EOPNOTSUPP;
-+	}
-+
-+	attr = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
-+	if (attr) {
-+		err = nla_parse_nested(tb, IFLA_BRIDGE_MAX, attr,
-+				       ifla_br_policy, NULL);
-+		if (unlikely(err)) {
-+			netdev_err(netdev,
-+				   "nla_parse_nested for br_policy err %d\n",
-+				   err);
-+			return err;
-+		}
-+
-+		err = evb_setlink_af_spec(netdev, tb);
-+		return err;
-+	}
-+
-+	netdev_err(netdev, "nlmsg_find_attr found no AF_SPEC\n");
-+	return -EOPNOTSUPP;
-+}
-+
-+static int __nla_put_netdev(struct sk_buff *skb, struct net_device *netdev)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	struct evb_priv		*evb_priv = port_priv->evb_priv;
-+	u8			operstate = netif_running(netdev) ?
-+				netdev->operstate : IF_OPER_DOWN;
-+	int			iflink;
-+	int			err;
-+
-+	err = nla_put_string(skb, IFLA_IFNAME, netdev->name);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u32(skb, IFLA_MASTER, evb_priv->uplink.netdev->ifindex);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u32(skb, IFLA_MTU, netdev->mtu);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u8(skb, IFLA_OPERSTATE, operstate);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	if (netdev->addr_len) {
-+		err = nla_put(skb, IFLA_ADDRESS, netdev->addr_len,
-+			      netdev->dev_addr);
-+		if (unlikely(err))
-+			goto nla_put_err;
-+	}
-+
-+	iflink = dev_get_iflink(netdev);
-+	if (netdev->ifindex != iflink) {
-+		err = nla_put_u32(skb, IFLA_LINK, iflink);
-+		if (unlikely(err))
-+			goto nla_put_err;
-+	}
-+
-+	return 0;
-+
-+nla_put_err:
-+	netdev_err(netdev, "nla_put_ err %d\n", err);
-+	return err;
-+}
-+
-+static int __nla_put_port(struct sk_buff *skb, struct net_device *netdev)
-+{
-+	struct nlattr	*nest;
-+	int		err;
-+
-+	nest = nla_nest_start(skb, IFLA_PROTINFO | NLA_F_NESTED);
-+	if (!nest) {
-+		netdev_err(netdev, "nla_nest_start failed\n");
-+		return -ENOMEM;
-+	}
-+
-+	err = nla_put_u8(skb, IFLA_BRPORT_STATE, BR_STATE_FORWARDING);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u16(skb, IFLA_BRPORT_PRIORITY, 0);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u32(skb, IFLA_BRPORT_COST, 0);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u8(skb, IFLA_BRPORT_MODE, 0);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u8(skb, IFLA_BRPORT_GUARD, 0);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u8(skb, IFLA_BRPORT_PROTECT, 0);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u8(skb, IFLA_BRPORT_FAST_LEAVE, 0);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u8(skb, IFLA_BRPORT_LEARNING, 0);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	err = nla_put_u8(skb, IFLA_BRPORT_UNICAST_FLOOD, 1);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+	nla_nest_end(skb, nest);
-+
-+	return 0;
-+
-+nla_put_err:
-+	netdev_err(netdev, "nla_put_ err %d\n", err);
-+	nla_nest_cancel(skb, nest);
-+	return err;
-+}
-+
-+static int __nla_put_vlan(struct sk_buff *skb,  struct net_device *netdev)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	struct nlattr		*nest;
-+	struct bridge_vlan_info	vinfo;
-+	const u8		*vlans = port_priv->vlans;
-+	u16			i;
-+	int			err;
-+
-+	nest = nla_nest_start(skb, IFLA_AF_SPEC);
-+	if (!nest) {
-+		netdev_err(netdev, "nla_nest_start failed");
-+		return -ENOMEM;
-+	}
-+
-+	for (i = 0; i < VLAN_VID_MASK + 1; i++) {
-+		if (!vlans[i])
-+			continue;
-+
-+		vinfo.flags = 0;
-+		vinfo.vid = i;
-+
-+		err = nla_put(skb, IFLA_BRIDGE_VLAN_INFO,
-+			      sizeof(vinfo), &vinfo);
-+		if (unlikely(err))
-+			goto nla_put_err;
-+	}
-+
-+	nla_nest_end(skb, nest);
-+
-+	return 0;
-+
-+nla_put_err:
-+	netdev_err(netdev, "nla_put_ err %d\n", err);
-+	nla_nest_cancel(skb, nest);
-+	return err;
-+}
-+
-+static int evb_getlink(struct sk_buff *skb, u32 pid, u32 seq,
-+		       struct net_device *netdev, u32 filter_mask, int nlflags)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	struct evb_priv		*evb_priv = port_priv->evb_priv;
-+	struct ifinfomsg	*hdr;
-+	struct nlmsghdr		*nlh;
-+	int			err;
-+
-+	if (evb_priv->attr.method != DPDMUX_METHOD_C_VLAN &&
-+	    evb_priv->attr.method != DPDMUX_METHOD_S_VLAN) {
-+		return 0;
-+	}
-+
-+	nlh = nlmsg_put(skb, pid, seq, RTM_NEWLINK, sizeof(*hdr), NLM_F_MULTI);
-+	if (!nlh)
-+		return -EMSGSIZE;
-+
-+	hdr = nlmsg_data(nlh);
-+	memset(hdr, 0, sizeof(*hdr));
-+	hdr->ifi_family = AF_BRIDGE;
-+	hdr->ifi_type = netdev->type;
-+	hdr->ifi_index = netdev->ifindex;
-+	hdr->ifi_flags = dev_get_flags(netdev);
-+
-+	err = __nla_put_netdev(skb, netdev);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+
-+	err = __nla_put_port(skb, netdev);
-+	if (unlikely(err))
-+		goto nla_put_err;
-+
-+	/* Check if the VID information is requested */
-+	if (filter_mask & RTEXT_FILTER_BRVLAN) {
-+		err = __nla_put_vlan(skb, netdev);
-+		if (unlikely(err))
-+			goto nla_put_err;
-+	}
-+
-+	nlmsg_end(skb, nlh);
-+	return skb->len;
-+
-+nla_put_err:
-+	nlmsg_cancel(skb, nlh);
-+	return -EMSGSIZE;
-+}
-+
-+static int evb_dellink(struct net_device *netdev,
-+		       struct nlmsghdr *nlh,
-+		       u16 flags)
-+{
-+	struct nlattr		*tb[IFLA_BRIDGE_MAX + 1];
-+	struct nlattr		*spec;
-+	struct bridge_vlan_info	*vinfo;
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	int			err = 0;
-+
-+	spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
-+	if (!spec)
-+		return 0;
-+
-+	err = nla_parse_nested(tb, IFLA_BRIDGE_MAX, spec, ifla_br_policy, NULL);
-+	if (unlikely(err))
-+		return err;
-+
-+	if (!tb[IFLA_BRIDGE_VLAN_INFO])
-+		return -EOPNOTSUPP;
-+
-+	vinfo = nla_data(tb[IFLA_BRIDGE_VLAN_INFO]);
-+
-+	if (!vinfo->vid || vinfo->vid > VLAN_VID_MASK)
-+		return -EINVAL;
-+
-+	err = evb_port_del_rule(netdev, NULL, vinfo->vid);
-+	if (unlikely(err)) {
-+		netdev_err(netdev, "evb_port_del_rule err %d\n", err);
-+		return err;
-+	}
-+	port_priv->vlans[vinfo->vid] = 0;
-+
-+	return 0;
-+}
-+
-+void evb_port_get_stats(struct net_device *netdev,
-+			struct rtnl_link_stats64 *storage)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	u64			tmp;
-+	int			err;
-+
-+	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index,
-+				    DPDMUX_CNT_ING_FRAME, &storage->rx_packets);
-+	if (unlikely(err))
-+		goto error;
-+
-+	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index,
-+				    DPDMUX_CNT_ING_BYTE, &storage->rx_bytes);
-+	if (unlikely(err))
-+		goto error;
-+
-+	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index,
-+				    DPDMUX_CNT_ING_FLTR_FRAME, &tmp);
-+	if (unlikely(err))
-+		goto error;
-+
-+	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index,
-+				    DPDMUX_CNT_ING_FRAME_DISCARD,
-+				    &storage->rx_dropped);
-+	if (unlikely(err)) {
-+		storage->rx_dropped = tmp;
-+		goto error;
-+	}
-+	storage->rx_dropped += tmp;
-+
-+	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index,
-+				    DPDMUX_CNT_ING_MCAST_FRAME,
-+				    &storage->multicast);
-+	if (unlikely(err))
-+		goto error;
-+
-+	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index,
-+				    DPDMUX_CNT_EGR_FRAME, &storage->tx_packets);
-+	if (unlikely(err))
-+		goto error;
-+
-+	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index,
-+				    DPDMUX_CNT_EGR_BYTE, &storage->tx_bytes);
-+	if (unlikely(err))
-+		goto error;
-+
-+	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+				    0,
-+				    port_priv->evb_priv->mux_handle,
-+				    port_priv->port_index,
-+				    DPDMUX_CNT_EGR_FRAME_DISCARD,
-+				    &storage->tx_dropped);
-+	if (unlikely(err))
-+		goto error;
-+
-+	return;
-+
-+error:
-+	netdev_err(netdev, "dpdmux_if_get_counter err %d\n", err);
-+}
-+
-+static const struct net_device_ops evb_port_ops = {
-+	.ndo_open		= &evb_port_open,
-+
-+	.ndo_start_xmit		= &evb_dropframe,
-+
-+	.ndo_fdb_add		= &evb_port_fdb_add,
-+	.ndo_fdb_del		= &evb_port_fdb_del,
-+
-+	.ndo_get_stats64	= &evb_port_get_stats,
-+	.ndo_change_mtu		= &evb_change_mtu,
-+};
-+
-+static void evb_get_drvinfo(struct net_device *netdev,
-+			    struct ethtool_drvinfo *drvinfo)
-+{
-+	struct evb_port_priv *port_priv = netdev_priv(netdev);
-+	u16 version_major, version_minor;
-+	int err;
-+
-+	strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
-+	strlcpy(drvinfo->version, evb_drv_version, sizeof(drvinfo->version));
-+
-+	err = dpdmux_get_api_version(port_priv->evb_priv->mc_io, 0,
-+				     &version_major,
-+				     &version_minor);
-+	if (err)
-+		strlcpy(drvinfo->fw_version, "N/A",
-+			sizeof(drvinfo->fw_version));
-+	else
-+		snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
-+			 "%u.%u", version_major, version_minor);
-+
-+	strlcpy(drvinfo->bus_info, dev_name(netdev->dev.parent->parent),
-+		sizeof(drvinfo->bus_info));
-+}
-+
-+static int evb_get_settings(struct net_device *netdev,
-+			    struct ethtool_cmd *cmd)
-+{
-+	struct evb_port_priv *port_priv = netdev_priv(netdev);
-+	struct dpdmux_link_state state = {0};
-+	int err = 0;
-+
-+	err = dpdmux_if_get_link_state(port_priv->evb_priv->mc_io, 0,
-+				       port_priv->evb_priv->mux_handle,
-+				       port_priv->port_index,
-+				       &state);
-+	if (err) {
-+		netdev_err(netdev, "ERROR %d getting link state", err);
-+		goto out;
-+	}
-+
-+	/* At the moment, we have no way of interrogating the DPMAC
-+	 * from the DPDMUX side or there may not exist a DPMAC at all.
-+	 * Report only autoneg state, duplexity and speed.
-+	 */
-+	if (state.options & DPDMUX_LINK_OPT_AUTONEG)
-+		cmd->autoneg = AUTONEG_ENABLE;
-+	if (!(state.options & DPDMUX_LINK_OPT_HALF_DUPLEX))
-+		cmd->duplex = DUPLEX_FULL;
-+	ethtool_cmd_speed_set(cmd, state.rate);
-+
-+out:
-+	return err;
-+}
-+
-+static int evb_set_settings(struct net_device *netdev,
-+			    struct ethtool_cmd *cmd)
-+{
-+	struct evb_port_priv *port_priv = netdev_priv(netdev);
-+	struct dpdmux_link_state state = {0};
-+	struct dpdmux_link_cfg cfg = {0};
-+	int err = 0;
-+
-+	netdev_dbg(netdev, "Setting link parameters...");
-+
-+	err = dpdmux_if_get_link_state(port_priv->evb_priv->mc_io, 0,
-+				       port_priv->evb_priv->mux_handle,
-+				       port_priv->port_index,
-+				       &state);
-+	if (err) {
-+		netdev_err(netdev, "ERROR %d getting link state", err);
-+		goto out;
-+	}
-+
-+	/* Due to a temporary MC limitation, the DPDMUX port must be down
-+	 * in order to be able to change link settings. Taking steps to let
-+	 * the user know that.
-+	 */
-+	if (netif_running(netdev)) {
-+		netdev_info(netdev,
-+			    "Sorry, interface must be brought down first.\n");
-+		return -EACCES;
-+	}
-+
-+	cfg.options = state.options;
-+	cfg.rate = ethtool_cmd_speed(cmd);
-+	if (cmd->autoneg == AUTONEG_ENABLE)
-+		cfg.options |= DPDMUX_LINK_OPT_AUTONEG;
-+	else
-+		cfg.options &= ~DPDMUX_LINK_OPT_AUTONEG;
-+	if (cmd->duplex == DUPLEX_HALF)
-+		cfg.options |= DPDMUX_LINK_OPT_HALF_DUPLEX;
-+	else
-+		cfg.options &= ~DPDMUX_LINK_OPT_HALF_DUPLEX;
-+
-+	err = dpdmux_if_set_link_cfg(port_priv->evb_priv->mc_io, 0,
-+				     port_priv->evb_priv->mux_handle,
-+				     port_priv->port_index,
-+				     &cfg);
-+	if (err)
-+		/* ethtool will be loud enough if we return an error; no point
-+		 * in putting our own error message on the console by default
-+		 */
-+		netdev_dbg(netdev, "ERROR %d setting link cfg", err);
-+
-+out:
-+	return err;
-+}
-+
-+static struct {
-+	enum dpdmux_counter_type id;
-+	char name[ETH_GSTRING_LEN];
-+} evb_ethtool_counters[] =  {
-+	{DPDMUX_CNT_ING_FRAME,		"rx frames"},
-+	{DPDMUX_CNT_ING_BYTE,		"rx bytes"},
-+	{DPDMUX_CNT_ING_FLTR_FRAME,	"rx filtered frames"},
-+	{DPDMUX_CNT_ING_FRAME_DISCARD,	"rx discarded frames"},
-+	{DPDMUX_CNT_ING_BCAST_FRAME,	"rx b-cast frames"},
-+	{DPDMUX_CNT_ING_BCAST_BYTES,	"rx b-cast bytes"},
-+	{DPDMUX_CNT_ING_MCAST_FRAME,	"rx m-cast frames"},
-+	{DPDMUX_CNT_ING_MCAST_BYTE,	"rx m-cast bytes"},
-+	{DPDMUX_CNT_EGR_FRAME,		"tx frames"},
-+	{DPDMUX_CNT_EGR_BYTE,		"tx bytes"},
-+	{DPDMUX_CNT_EGR_FRAME_DISCARD,	"tx discarded frames"},
-+};
-+
-+static int evb_ethtool_get_sset_count(struct net_device *dev, int sset)
-+{
-+	switch (sset) {
-+	case ETH_SS_STATS:
-+		return ARRAY_SIZE(evb_ethtool_counters);
-+	default:
-+		return -EOPNOTSUPP;
-+	}
-+}
-+
-+static void evb_ethtool_get_strings(struct net_device *netdev,
-+				    u32 stringset, u8 *data)
-+{
-+	u32 i;
-+
-+	switch (stringset) {
-+	case ETH_SS_STATS:
-+		for (i = 0; i < ARRAY_SIZE(evb_ethtool_counters); i++)
-+			memcpy(data + i * ETH_GSTRING_LEN,
-+			       evb_ethtool_counters[i].name, ETH_GSTRING_LEN);
-+		break;
-+	}
-+}
-+
-+static void evb_ethtool_get_stats(struct net_device *netdev,
-+				  struct ethtool_stats *stats,
-+				  u64 *data)
-+{
-+	struct evb_port_priv	*port_priv = netdev_priv(netdev);
-+	u32			i;
-+	int			err;
-+
-+	for (i = 0; i < ARRAY_SIZE(evb_ethtool_counters); i++) {
-+		err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
-+					    0,
-+					    port_priv->evb_priv->mux_handle,
-+					    port_priv->port_index,
-+					    evb_ethtool_counters[i].id,
-+					    &data[i]);
-+		if (err)
-+			netdev_err(netdev, "dpdmux_if_get_counter[%s] err %d\n",
-+				   evb_ethtool_counters[i].name, err);
-+	}
-+}
-+
-+static const struct ethtool_ops evb_port_ethtool_ops = {
-+	.get_drvinfo		= &evb_get_drvinfo,
-+	.get_link		= &ethtool_op_get_link,
-+	.get_settings		= &evb_get_settings,
-+	.set_settings		= &evb_set_settings,
-+	.get_strings		= &evb_ethtool_get_strings,
-+	.get_ethtool_stats	= &evb_ethtool_get_stats,
-+	.get_sset_count		= &evb_ethtool_get_sset_count,
-+};
-+
-+static int evb_open(struct net_device *netdev)
-+{
-+	struct evb_priv	*priv = netdev_priv(netdev);
-+	int		err = 0;
-+
-+	err = dpdmux_enable(priv->mc_io, 0, priv->mux_handle);
-+	if (unlikely(err))
-+		netdev_err(netdev, "dpdmux_enable err %d\n", err);
-+
-+	return err;
-+}
-+
-+static int evb_close(struct net_device *netdev)
-+{
-+	struct evb_priv	*priv = netdev_priv(netdev);
-+	int		err = 0;
-+
-+	err = dpdmux_disable(priv->mc_io, 0, priv->mux_handle);
-+	if (unlikely(err))
-+		netdev_err(netdev, "dpdmux_disable err %d\n", err);
-+
-+	return err;
-+}
-+
-+static const struct net_device_ops evb_ops = {
-+	.ndo_start_xmit		= &evb_dropframe,
-+	.ndo_open		= &evb_open,
-+	.ndo_stop		= &evb_close,
-+
-+	.ndo_bridge_setlink	= &evb_setlink,
-+	.ndo_bridge_getlink	= &evb_getlink,
-+	.ndo_bridge_dellink	= &evb_dellink,
-+
-+	.ndo_get_stats64	= &evb_port_get_stats,
-+	.ndo_change_mtu		= &evb_change_mtu,
-+};
-+
-+static int evb_takedown(struct fsl_mc_device *evb_dev)
-+{
-+	struct device		*dev = &evb_dev->dev;
-+	struct net_device	*netdev = dev_get_drvdata(dev);
-+	struct evb_priv		*priv = netdev_priv(netdev);
-+	int			err;
-+
-+	err = dpdmux_close(priv->mc_io, 0, priv->mux_handle);
-+	if (unlikely(err))
-+		dev_warn(dev, "dpdmux_close err %d\n", err);
-+
-+	return 0;
-+}
-+
-+static int evb_init(struct fsl_mc_device *evb_dev)
-+{
-+	struct device		*dev = &evb_dev->dev;
-+	struct net_device	*netdev = dev_get_drvdata(dev);
-+	struct evb_priv		*priv = netdev_priv(netdev);
-+	u16			version_major;
-+	u16			version_minor;
-+	int			err = 0;
-+
-+	priv->dev_id = evb_dev->obj_desc.id;
-+
-+	err = dpdmux_open(priv->mc_io, 0, priv->dev_id, &priv->mux_handle);
-+	if (unlikely(err)) {
-+		dev_err(dev, "dpdmux_open err %d\n", err);
-+		goto err_exit;
-+	}
-+	if (!priv->mux_handle) {
-+		dev_err(dev, "dpdmux_open returned null handle but no error\n");
-+		err = -EFAULT;
-+		goto err_exit;
-+	}
-+
-+	err = dpdmux_get_attributes(priv->mc_io, 0, priv->mux_handle,
-+				    &priv->attr);
-+	if (unlikely(err)) {
-+		dev_err(dev, "dpdmux_get_attributes err %d\n", err);
-+		goto err_close;
-+	}
-+
-+	err = dpdmux_get_api_version(priv->mc_io, 0,
-+				     &version_major,
-+				     &version_minor);
-+	if (unlikely(err)) {
-+		dev_err(dev, "dpdmux_get_api_version err %d\n", err);
-+		goto err_close;
-+	}
-+
-+	/* Minimum supported DPDMUX version check */
-+	if (version_major < DPDMUX_MIN_VER_MAJOR ||
-+	    (version_major == DPDMUX_MIN_VER_MAJOR &&
-+	     version_minor < DPDMUX_MIN_VER_MINOR)) {
-+		dev_err(dev, "DPDMUX version %d.%d not supported. Use %d.%d or greater.\n",
-+			version_major, version_minor,
-+			DPDMUX_MIN_VER_MAJOR, DPDMUX_MIN_VER_MAJOR);
-+		err = -ENOTSUPP;
-+		goto err_close;
-+	}
-+
-+	err = dpdmux_reset(priv->mc_io, 0, priv->mux_handle);
-+	if (unlikely(err)) {
-+		dev_err(dev, "dpdmux_reset err %d\n", err);
-+		goto err_close;
-+	}
-+
-+	return 0;
-+
-+err_close:
-+	dpdmux_close(priv->mc_io, 0, priv->mux_handle);
-+err_exit:
-+	return err;
-+}
-+
-+static int evb_remove(struct fsl_mc_device *evb_dev)
-+{
-+	struct device		*dev = &evb_dev->dev;
-+	struct net_device	*netdev = dev_get_drvdata(dev);
-+	struct evb_priv		*priv = netdev_priv(netdev);
-+	struct evb_port_priv	*port_priv;
-+	struct list_head	*pos;
-+
-+	list_for_each(pos, &priv->port_list) {
-+		port_priv = list_entry(pos, struct evb_port_priv, list);
-+
-+		rtnl_lock();
-+		netdev_upper_dev_unlink(port_priv->netdev, netdev);
-+		rtnl_unlock();
-+
-+		unregister_netdev(port_priv->netdev);
-+		free_netdev(port_priv->netdev);
-+	}
-+
-+	evb_teardown_irqs(evb_dev);
-+
-+	unregister_netdev(netdev);
-+
-+	evb_takedown(evb_dev);
-+	fsl_mc_portal_free(priv->mc_io);
-+
-+	dev_set_drvdata(dev, NULL);
-+	free_netdev(netdev);
-+
-+	return 0;
-+}
-+
-+static int evb_probe(struct fsl_mc_device *evb_dev)
-+{
-+	struct device		*dev;
-+	struct evb_priv		*priv = NULL;
-+	struct net_device	*netdev = NULL;
-+	char			port_name[IFNAMSIZ];
-+	int			i;
-+	int			err = 0;
-+
-+	dev = &evb_dev->dev;
-+
-+	/* register switch device, it's for management only - no I/O */
-+	netdev = alloc_etherdev(sizeof(*priv));
-+	if (!netdev) {
-+		dev_err(dev, "alloc_etherdev error\n");
-+		return -ENOMEM;
-+	}
-+	netdev->netdev_ops = &evb_ops;
-+
-+	dev_set_drvdata(dev, netdev);
-+
-+	priv = netdev_priv(netdev);
-+
-+	err = fsl_mc_portal_allocate(evb_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
-+				     &priv->mc_io);
-+	if (err) {
-+		if (err == -ENXIO)
-+			err = -EPROBE_DEFER;
-+		else
-+			dev_err(dev, "fsl_mc_portal_allocate err %d\n", err);
-+		goto err_free_netdev;
-+	}
-+
-+	if (!priv->mc_io) {
-+		dev_err(dev, "fsl_mc_portal_allocate returned null handle but no error\n");
-+		err = -EFAULT;
-+		goto err_free_netdev;
-+	}
-+
-+	err = evb_init(evb_dev);
-+	if (unlikely(err)) {
-+		dev_err(dev, "evb init err %d\n", err);
-+		goto err_free_cmdport;
-+	}
-+
-+	INIT_LIST_HEAD(&priv->port_list);
-+	netdev->flags |= IFF_PROMISC | IFF_MASTER;
-+
-+	dev_alloc_name(netdev, "evb%d");
-+
-+	/* register switch ports */
-+	snprintf(port_name, IFNAMSIZ, "%sp%%d", netdev->name);
-+
-+	/* only register downlinks? */
-+	for (i = 0; i < priv->attr.num_ifs + 1; i++) {
-+		struct net_device *port_netdev;
-+		struct evb_port_priv *port_priv;
-+
-+		if (i) {
-+			port_netdev =
-+				alloc_etherdev(sizeof(struct evb_port_priv));
-+			if (!port_netdev) {
-+				dev_err(dev, "alloc_etherdev error\n");
-+				goto err_takedown;
-+			}
-+
-+			port_priv = netdev_priv(port_netdev);
-+
-+			port_netdev->flags |= IFF_PROMISC | IFF_SLAVE;
-+
-+			dev_alloc_name(port_netdev, port_name);
-+		} else {
-+			port_netdev = netdev;
-+			port_priv = &priv->uplink;
-+		}
-+
-+		port_priv->netdev = port_netdev;
-+		port_priv->evb_priv = priv;
-+		port_priv->port_index = i;
-+
-+		SET_NETDEV_DEV(port_netdev, dev);
-+
-+		if (i) {
-+			port_netdev->netdev_ops = &evb_port_ops;
-+
-+			err = register_netdev(port_netdev);
-+			if (err < 0) {
-+				dev_err(dev, "register_netdev err %d\n", err);
-+				free_netdev(port_netdev);
-+				goto err_takedown;
-+			}
-+
-+			rtnl_lock();
-+			err = netdev_master_upper_dev_link(port_netdev, netdev,
-+							   NULL, NULL);
-+			if (unlikely(err)) {
-+				dev_err(dev, "netdev_master_upper_dev_link err %d\n",
-+					err);
-+				unregister_netdev(port_netdev);
-+				free_netdev(port_netdev);
-+				rtnl_unlock();
-+				goto err_takedown;
-+			}
-+			rtmsg_ifinfo(RTM_NEWLINK, port_netdev,
-+				     IFF_SLAVE, GFP_KERNEL);
-+			rtnl_unlock();
-+
-+			list_add(&port_priv->list, &priv->port_list);
-+		} else {
-+			/* Set MTU limits only on uplink */
-+			port_netdev->min_mtu = EVB_MIN_MTU;
-+			port_netdev->max_mtu = EVB_MAX_MTU;
-+
-+			err = register_netdev(netdev);
-+
-+			if (err < 0) {
-+				dev_err(dev, "register_netdev error %d\n", err);
-+				goto err_takedown;
-+			}
-+		}
-+
-+		port_netdev->ethtool_ops = &evb_port_ethtool_ops;
-+
-+		/* ports are up from init */
-+		rtnl_lock();
-+		err = dev_open(port_netdev);
-+		rtnl_unlock();
-+		if (unlikely(err))
-+			dev_warn(dev, "dev_open err %d\n", err);
-+	}
-+
-+	/* setup irqs */
-+	err = evb_setup_irqs(evb_dev);
-+	if (unlikely(err)) {
-+		dev_warn(dev, "evb_setup_irqs err %d\n", err);
-+		goto err_takedown;
-+	}
-+
-+	dev_info(dev, "probed evb device with %d ports\n",
-+		 priv->attr.num_ifs);
-+	return 0;
-+
-+err_takedown:
-+	evb_remove(evb_dev);
-+err_free_cmdport:
-+	fsl_mc_portal_free(priv->mc_io);
-+err_free_netdev:
-+	return err;
-+}
-+
-+static const struct fsl_mc_device_id evb_match_id_table[] = {
-+	{
-+		.vendor = FSL_MC_VENDOR_FREESCALE,
-+		.obj_type = "dpdmux",
-+	},
-+	{}
-+};
-+
-+static struct fsl_mc_driver evb_drv = {
-+	.driver = {
-+		.name		= KBUILD_MODNAME,
-+		.owner		= THIS_MODULE,
-+	},
-+	.probe		= evb_probe,
-+	.remove		= evb_remove,
-+	.match_id_table = evb_match_id_table,
-+};
-+
-+module_fsl_mc_driver(evb_drv);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("Layerscape DPAA Edge Virtual Bridge driver (prototype)");
diff --git a/target/linux/layerscape/patches-4.14/711-dpaa-bqman-support-layerscape.patch b/target/linux/layerscape/patches-4.14/711-dpaa-bqman-support-layerscape.patch
deleted file mode 100644
index 89ace283b..000000000
--- a/target/linux/layerscape/patches-4.14/711-dpaa-bqman-support-layerscape.patch
+++ /dev/null
@@ -1,550 +0,0 @@
-From 48dbe4b3a31795b8efdfff82f69eccd086052eed Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 16 Nov 2018 10:27:30 +0800
-Subject: [PATCH 16/39] dpaa-bqman: support layerscape 
-This is an integrated patch of dpaa-bqman for layerscape
-
-Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
-Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
-Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
-Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
-Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/soc/fsl/qbman/Kconfig       |   2 +-
- drivers/soc/fsl/qbman/bman.c        |  24 ++++-
- drivers/soc/fsl/qbman/bman_ccsr.c   |  35 ++++++-
- drivers/soc/fsl/qbman/bman_portal.c |  12 ++-
- drivers/soc/fsl/qbman/bman_priv.h   |   3 +
- drivers/soc/fsl/qbman/dpaa_sys.h    |   8 +-
- drivers/soc/fsl/qbman/qman.c        |  46 ++++++++-
- drivers/soc/fsl/qbman/qman_ccsr.c   | 140 ++++++++++++++++++++++------
- drivers/soc/fsl/qbman/qman_portal.c |  12 ++-
- drivers/soc/fsl/qbman/qman_priv.h   |   5 +-
- drivers/soc/fsl/qbman/qman_test.h   |   2 -
- 11 files changed, 236 insertions(+), 53 deletions(-)
-
---- a/drivers/soc/fsl/qbman/Kconfig
-+++ b/drivers/soc/fsl/qbman/Kconfig
-@@ -1,6 +1,6 @@
- menuconfig FSL_DPAA
- 	bool "Freescale DPAA 1.x support"
--	depends on FSL_SOC_BOOKE
-+	depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
- 	select GENERIC_ALLOCATOR
- 	help
- 	  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
---- a/drivers/soc/fsl/qbman/bman.c
-+++ b/drivers/soc/fsl/qbman/bman.c
-@@ -35,6 +35,27 @@
- 
- /* Portal register assists */
- 
-+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
-+/* Cache-inhibited register offsets */
-+#define BM_REG_RCR_PI_CINH	0x3000
-+#define BM_REG_RCR_CI_CINH	0x3100
-+#define BM_REG_RCR_ITR		0x3200
-+#define BM_REG_CFG		0x3300
-+#define BM_REG_SCN(n)		(0x3400 + ((n) << 6))
-+#define BM_REG_ISR		0x3e00
-+#define BM_REG_IER		0x3e40
-+#define BM_REG_ISDR		0x3e80
-+#define BM_REG_IIR		0x3ec0
-+
-+/* Cache-enabled register offsets */
-+#define BM_CL_CR		0x0000
-+#define BM_CL_RR0		0x0100
-+#define BM_CL_RR1		0x0140
-+#define BM_CL_RCR		0x1000
-+#define BM_CL_RCR_PI_CENA	0x3000
-+#define BM_CL_RCR_CI_CENA	0x3100
-+
-+#else
- /* Cache-inhibited register offsets */
- #define BM_REG_RCR_PI_CINH	0x0000
- #define BM_REG_RCR_CI_CINH	0x0004
-@@ -53,6 +74,7 @@
- #define BM_CL_RCR		0x1000
- #define BM_CL_RCR_PI_CENA	0x3000
- #define BM_CL_RCR_CI_CENA	0x3100
-+#endif
- 
- /*
-  * Portal modes.
-@@ -607,7 +629,7 @@ int bman_p_irqsource_add(struct bman_por
- 	unsigned long irqflags;
- 
- 	local_irq_save(irqflags);
--	set_bits(bits & BM_PIRQ_VISIBLE, &p->irq_sources);
-+	p->irq_sources |= bits & BM_PIRQ_VISIBLE;
- 	bm_out(&p->p, BM_REG_IER, p->irq_sources);
- 	local_irq_restore(irqflags);
- 	return 0;
---- a/drivers/soc/fsl/qbman/bman_ccsr.c
-+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
-@@ -170,10 +170,11 @@ static int fsl_bman_probe(struct platfor
- {
- 	int ret, err_irq;
- 	struct device *dev = &pdev->dev;
--	struct device_node *node = dev->of_node;
-+	struct device_node *mem_node, *node = dev->of_node;
- 	struct resource *res;
- 	u16 id, bm_pool_cnt;
- 	u8 major, minor;
-+	u64 size;
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	if (!res) {
-@@ -201,6 +202,38 @@ static int fsl_bman_probe(struct platfor
- 		return -ENODEV;
- 	}
- 
-+	/*
-+	 * If FBPR memory wasn't defined using the qbman compatiable string
-+	 * try using the of_reserved_mem_device method
-+	 */
-+	if (!fbpr_a) {
-+		ret = of_reserved_mem_device_init(dev);
-+		if (ret) {
-+			dev_err(dev, "of_reserved_mem_device_init() failed 0x%x\n",
-+				ret);
-+			return -ENODEV;
-+		}
-+		mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
-+		if (mem_node) {
-+			ret = of_property_read_u64(mem_node, "size", &size);
-+			if (ret) {
-+				dev_err(dev, "FBPR: of_address_to_resource fails 0x%x\n",
-+					ret);
-+				return -ENODEV;
-+			}
-+			fbpr_sz = size;
-+		} else {
-+			dev_err(dev, "No memory-region found for FBPR\n");
-+			return -ENODEV;
-+		}
-+		if (!dma_zalloc_coherent(dev, fbpr_sz, &fbpr_a, 0)) {
-+			dev_err(dev, "Alloc FBPR memory failed\n");
-+			return -ENODEV;
-+		}
-+	}
-+
-+	dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
-+
- 	bm_set_memory(fbpr_a, fbpr_sz);
- 
- 	err_irq = platform_get_irq(pdev, 0);
---- a/drivers/soc/fsl/qbman/bman_portal.c
-+++ b/drivers/soc/fsl/qbman/bman_portal.c
-@@ -123,7 +123,14 @@ static int bman_portal_probe(struct plat
- 	}
- 	pcfg->irq = irq;
- 
--	va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
-+#ifdef CONFIG_PPC
-+	/* PPC requires a cacheable/non-coherent mapping of the portal */
-+	va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
-+			  (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
-+#else
-+	/* For ARM we can use write combine mapping. */
-+	va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
-+#endif
- 	if (!va) {
- 		dev_err(dev, "ioremap::CE failed\n");
- 		goto err_ioremap1;
-@@ -131,8 +138,7 @@ static int bman_portal_probe(struct plat
- 
- 	pcfg->addr_virt[DPAA_PORTAL_CE] = va;
- 
--	va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
--			  _PAGE_GUARDED | _PAGE_NO_CACHE);
-+	va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
- 	if (!va) {
- 		dev_err(dev, "ioremap::CI failed\n");
- 		goto err_ioremap2;
---- a/drivers/soc/fsl/qbman/bman_priv.h
-+++ b/drivers/soc/fsl/qbman/bman_priv.h
-@@ -33,6 +33,9 @@
- #include "dpaa_sys.h"
- 
- #include <soc/fsl/bman.h>
-+#include <linux/dma-contiguous.h>
-+#include <linux/of_address.h>
-+#include <linux/dma-mapping.h>
- 
- /* Portal processing (interrupt) sources */
- #define BM_PIRQ_RCRI	0x00000002	/* RCR Ring (below threshold) */
---- a/drivers/soc/fsl/qbman/dpaa_sys.h
-+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
-@@ -44,20 +44,18 @@
- #include <linux/prefetch.h>
- #include <linux/genalloc.h>
- #include <asm/cacheflush.h>
-+#include <linux/io.h>
-+#include <linux/delay.h>
- 
- /* For 2-element tables related to cache-inhibited and cache-enabled mappings */
- #define DPAA_PORTAL_CE 0
- #define DPAA_PORTAL_CI 1
- 
--#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
--#error "Unsupported Cacheline Size"
--#endif
--
- static inline void dpaa_flush(void *p)
- {
- #ifdef CONFIG_PPC
- 	flush_dcache_range((unsigned long)p, (unsigned long)p+64);
--#elif defined(CONFIG_ARM32)
-+#elif defined(CONFIG_ARM)
- 	__cpuc_flush_dcache_area(p, 64);
- #elif defined(CONFIG_ARM64)
- 	__flush_dcache_area(p, 64);
---- a/drivers/soc/fsl/qbman/qman.c
-+++ b/drivers/soc/fsl/qbman/qman.c
-@@ -41,6 +41,43 @@
- 
- /* Portal register assists */
- 
-+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
-+/* Cache-inhibited register offsets */
-+#define QM_REG_EQCR_PI_CINH	0x3000
-+#define QM_REG_EQCR_CI_CINH	0x3040
-+#define QM_REG_EQCR_ITR		0x3080
-+#define QM_REG_DQRR_PI_CINH	0x3100
-+#define QM_REG_DQRR_CI_CINH	0x3140
-+#define QM_REG_DQRR_ITR		0x3180
-+#define QM_REG_DQRR_DCAP	0x31C0
-+#define QM_REG_DQRR_SDQCR	0x3200
-+#define QM_REG_DQRR_VDQCR	0x3240
-+#define QM_REG_DQRR_PDQCR	0x3280
-+#define QM_REG_MR_PI_CINH	0x3300
-+#define QM_REG_MR_CI_CINH	0x3340
-+#define QM_REG_MR_ITR		0x3380
-+#define QM_REG_CFG		0x3500
-+#define QM_REG_ISR		0x3600
-+#define QM_REG_IER		0x3640
-+#define QM_REG_ISDR		0x3680
-+#define QM_REG_IIR		0x36C0
-+#define QM_REG_ITPR		0x3740
-+
-+/* Cache-enabled register offsets */
-+#define QM_CL_EQCR		0x0000
-+#define QM_CL_DQRR		0x1000
-+#define QM_CL_MR		0x2000
-+#define QM_CL_EQCR_PI_CENA	0x3000
-+#define QM_CL_EQCR_CI_CENA	0x3040
-+#define QM_CL_DQRR_PI_CENA	0x3100
-+#define QM_CL_DQRR_CI_CENA	0x3140
-+#define QM_CL_MR_PI_CENA	0x3300
-+#define QM_CL_MR_CI_CENA	0x3340
-+#define QM_CL_CR		0x3800
-+#define QM_CL_RR0		0x3900
-+#define QM_CL_RR1		0x3940
-+
-+#else
- /* Cache-inhibited register offsets */
- #define QM_REG_EQCR_PI_CINH	0x0000
- #define QM_REG_EQCR_CI_CINH	0x0004
-@@ -75,6 +112,7 @@
- #define QM_CL_CR		0x3800
- #define QM_CL_RR0		0x3900
- #define QM_CL_RR1		0x3940
-+#endif
- 
- /*
-  * BTW, the drivers (and h/w programming model) already obtain the required
-@@ -909,12 +947,12 @@ static inline int qm_mc_result_timeout(s
- 
- static inline void fq_set(struct qman_fq *fq, u32 mask)
- {
--	set_bits(mask, &fq->flags);
-+	fq->flags |= mask;
- }
- 
- static inline void fq_clear(struct qman_fq *fq, u32 mask)
- {
--	clear_bits(mask, &fq->flags);
-+	fq->flags &= ~mask;
- }
- 
- static inline int fq_isset(struct qman_fq *fq, u32 mask)
-@@ -1566,7 +1604,7 @@ void qman_p_irqsource_add(struct qman_po
- 	unsigned long irqflags;
- 
- 	local_irq_save(irqflags);
--	set_bits(bits & QM_PIRQ_VISIBLE, &p->irq_sources);
-+	p->irq_sources |= bits & QM_PIRQ_VISIBLE;
- 	qm_out(&p->p, QM_REG_IER, p->irq_sources);
- 	local_irq_restore(irqflags);
- }
-@@ -1589,7 +1627,7 @@ void qman_p_irqsource_remove(struct qman
- 	 */
- 	local_irq_save(irqflags);
- 	bits &= QM_PIRQ_VISIBLE;
--	clear_bits(bits, &p->irq_sources);
-+	p->irq_sources &= ~bits;
- 	qm_out(&p->p, QM_REG_IER, p->irq_sources);
- 	ier = qm_in(&p->p, QM_REG_IER);
- 	/*
---- a/drivers/soc/fsl/qbman/qman_ccsr.c
-+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
-@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *d
- }
- 
- /*
-- * Ideally we would use the DMA API to turn rmem->base into a DMA address
-- * (especially if iommu translations ever get involved).  Unfortunately, the
-- * DMA API currently does not allow mapping anything that is not backed with
-- * a struct page.
-+ * QMan needs two global memory areas initialized at boot time:
-+ *  1) FQD: Frame Queue Descriptors used to manage frame queues
-+ *  2) PFDR: Packed Frame Queue Descriptor Records used to store frames
-+ * Both areas are reserved using the device tree reserved memory framework
-+ * and the addresses and sizes are initialized when the QMan device is probed
-  */
- static dma_addr_t fqd_a, pfdr_a;
- static size_t fqd_sz, pfdr_sz;
- 
-+#ifdef CONFIG_PPC
-+/*
-+ * Support for PPC Device Tree backward compatibility when compatiable
-+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
-+ */
-+static int zero_priv_mem(phys_addr_t addr, size_t sz)
-+{
-+	/* map as cacheable, non-guarded */
-+	void __iomem *tmpp = ioremap_prot(addr, sz, 0);
-+
-+	if (!tmpp)
-+		return -ENOMEM;
-+
-+	memset_io(tmpp, 0, sz);
-+	flush_dcache_range((unsigned long)tmpp,
-+			   (unsigned long)tmpp + sz);
-+	iounmap(tmpp);
-+
-+	return 0;
-+}
-+
- static int qman_fqd(struct reserved_mem *rmem)
- {
- 	fqd_a = rmem->base;
- 	fqd_sz = rmem->size;
- 
- 	WARN_ON(!(fqd_a && fqd_sz));
--
- 	return 0;
- }
- RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
-@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem
- }
- RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
- 
-+#endif
-+
- static unsigned int qm_get_fqid_maxcnt(void)
- {
- 	return fqd_sz / 64;
- }
- 
--/*
-- * Flush this memory range from data cache so that QMAN originated
-- * transactions for this memory region could be marked non-coherent.
-- */
--static int zero_priv_mem(struct device *dev, struct device_node *node,
--			 phys_addr_t addr, size_t sz)
--{
--	/* map as cacheable, non-guarded */
--	void __iomem *tmpp = ioremap_prot(addr, sz, 0);
--
--	if (!tmpp)
--		return -ENOMEM;
--
--	memset_io(tmpp, 0, sz);
--	flush_dcache_range((unsigned long)tmpp,
--			   (unsigned long)tmpp + sz);
--	iounmap(tmpp);
--
--	return 0;
--}
--
- static void log_edata_bits(struct device *dev, u32 bit_count)
- {
- 	u32 i, j, mask = 0xffffffff;
-@@ -687,11 +689,12 @@ static int qman_resource_init(struct dev
- static int fsl_qman_probe(struct platform_device *pdev)
- {
- 	struct device *dev = &pdev->dev;
--	struct device_node *node = dev->of_node;
-+	struct device_node *mem_node, *node = dev->of_node;
- 	struct resource *res;
- 	int ret, err_irq;
- 	u16 id;
- 	u8 major, minor;
-+	u64 size;
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	if (!res) {
-@@ -717,6 +720,8 @@ static int fsl_qman_probe(struct platfor
- 		qman_ip_rev = QMAN_REV30;
- 	else if (major == 3 && minor == 1)
- 		qman_ip_rev = QMAN_REV31;
-+	else if (major == 3 && minor == 2)
-+		qman_ip_rev = QMAN_REV32;
- 	else {
- 		dev_err(dev, "Unknown QMan version\n");
- 		return -ENODEV;
-@@ -727,10 +732,83 @@ static int fsl_qman_probe(struct platfor
- 		qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
- 	}
- 
--	ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
--	WARN_ON(ret);
--	if (ret)
--		return -ENODEV;
-+	if (fqd_a) {
-+#ifdef CONFIG_PPC
-+		/*
-+		 * For PPC backward DT compatibility
-+		 * FQD memory MUST be zero'd by software
-+		 */
-+		zero_priv_mem(fqd_a, fqd_sz);
-+#else
-+		WARN(1, "Unexpected archiceture using non shared-dma-mem reservations");
-+#endif
-+	} else {
-+		/*
-+		 * Order of memory regions is assumed as FQD followed by PFDR
-+		 * in order to ensure allocations from the correct regions the
-+		 * driver initializes then allocates each piece in order
-+		 */
-+		ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 0);
-+		if (ret) {
-+			dev_err(dev, "of_reserved_mem_device_init_by_idx(0) failed 0x%x\n",
-+				ret);
-+			return -ENODEV;
-+		}
-+		mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
-+		if (mem_node) {
-+			ret = of_property_read_u64(mem_node, "size", &size);
-+			if (ret) {
-+				dev_err(dev, "FQD: of_address_to_resource fails 0x%x\n",
-+					ret);
-+				return -ENODEV;
-+			}
-+			fqd_sz = size;
-+		} else {
-+			dev_err(dev, "No memory-region found for FQD\n");
-+			return -ENODEV;
-+		}
-+		if (!dma_zalloc_coherent(dev, fqd_sz, &fqd_a, 0)) {
-+			dev_err(dev, "Alloc FQD memory failed\n");
-+			return -ENODEV;
-+		}
-+
-+		/*
-+		 * Disassociate the FQD reserved memory area from the device
-+		 * because a device can only have one DMA memory area. This
-+		 * should be fine since the memory is allocated and initialized
-+		 * and only ever accessed by the QMan device from now on
-+		 */
-+		of_reserved_mem_device_release(dev);
-+	}
-+	dev_dbg(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz);
-+
-+	if (!pfdr_a) {
-+		/* Setup PFDR memory */
-+		ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 1);
-+		if (ret) {
-+			dev_err(dev, "of_reserved_mem_device_init(1) failed 0x%x\n",
-+			ret);
-+			return -ENODEV;
-+		}
-+		mem_node = of_parse_phandle(dev->of_node, "memory-region", 1);
-+		if (mem_node) {
-+			ret = of_property_read_u64(mem_node, "size", &size);
-+			if (ret) {
-+				dev_err(dev, "PFDR: of_address_to_resource fails 0x%x\n",
-+					ret);
-+				return -ENODEV;
-+			}
-+			pfdr_sz = size;
-+		} else {
-+			dev_err(dev, "No memory-region found for PFDR\n");
-+			return -ENODEV;
-+		}
-+		if (!dma_zalloc_coherent(dev, pfdr_sz, &pfdr_a, 0)) {
-+			dev_err(dev, "Alloc PFDR Failed size 0x%zx\n", pfdr_sz);
-+			return -ENODEV;
-+		}
-+	}
-+	dev_info(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz);
- 
- 	ret = qman_init_ccsr(dev);
- 	if (ret) {
---- a/drivers/soc/fsl/qbman/qman_portal.c
-+++ b/drivers/soc/fsl/qbman/qman_portal.c
-@@ -262,7 +262,14 @@ static int qman_portal_probe(struct plat
- 	}
- 	pcfg->irq = irq;
- 
--	va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
-+#ifdef CONFIG_PPC
-+	/* PPC requires a cacheable/non-coherent mapping of the portal */
-+	va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
-+			  (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
-+#else
-+	/* For ARM we can use write combine mapping. */
-+	va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
-+#endif
- 	if (!va) {
- 		dev_err(dev, "ioremap::CE failed\n");
- 		goto err_ioremap1;
-@@ -270,8 +277,7 @@ static int qman_portal_probe(struct plat
- 
- 	pcfg->addr_virt[DPAA_PORTAL_CE] = va;
- 
--	va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
--			  _PAGE_GUARDED | _PAGE_NO_CACHE);
-+	va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
- 	if (!va) {
- 		dev_err(dev, "ioremap::CI failed\n");
- 		goto err_ioremap2;
---- a/drivers/soc/fsl/qbman/qman_priv.h
-+++ b/drivers/soc/fsl/qbman/qman_priv.h
-@@ -28,13 +28,13 @@
-  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  */
- 
--#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
--
- #include "dpaa_sys.h"
- 
- #include <soc/fsl/qman.h>
- #include <linux/dma-mapping.h>
- #include <linux/iommu.h>
-+#include <linux/dma-contiguous.h>
-+#include <linux/of_address.h>
- 
- #if defined(CONFIG_FSL_PAMU)
- #include <asm/fsl_pamu_stash.h>
-@@ -187,6 +187,7 @@ struct qm_portal_config {
- #define QMAN_REV20 0x0200
- #define QMAN_REV30 0x0300
- #define QMAN_REV31 0x0301
-+#define QMAN_REV32 0x0302
- extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
- 
- #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
---- a/drivers/soc/fsl/qbman/qman_test.h
-+++ b/drivers/soc/fsl/qbman/qman_test.h
-@@ -30,7 +30,5 @@
- 
- #include "qman_priv.h"
- 
--#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
--
- int qman_test_stash(void);
- int qman_test_api(void);
diff --git a/target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch b/target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch
deleted file mode 100644
index aaf677b56..000000000
--- a/target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 918f966af1f0e42ff8ac298e1d7d02e67afcfab4 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:27:42 +0800
-Subject: [PATCH 18/40] sata: support layerscape
-This is an integrated patch of sata for layerscape
-
-Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/ata/ahci_qoriq.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/drivers/ata/ahci_qoriq.c
-+++ b/drivers/ata/ahci_qoriq.c
-@@ -35,6 +35,8 @@
- 
- /* port register default value */
- #define AHCI_PORT_PHY_1_CFG	0xa003fffe
-+#define AHCI_PORT_PHY2_CFG	0x28184d1f
-+#define AHCI_PORT_PHY3_CFG	0x0e081509
- #define AHCI_PORT_TRANS_CFG	0x08000029
- #define AHCI_PORT_AXICC_CFG	0x3fffffff
- 
-@@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ah
- 		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- 				qpriv->ecc_addr);
- 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-+		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-+		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- 		if (qpriv->is_dmacoherent)
- 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-@@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ah
- 
- 	case AHCI_LS2080A:
- 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-+		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-+		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- 		if (qpriv->is_dmacoherent)
- 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-@@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ah
- 		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
- 				qpriv->ecc_addr);
- 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-+		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-+		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- 		if (qpriv->is_dmacoherent)
- 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-@@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ah
- 		writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
- 		       qpriv->ecc_addr);
- 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-+		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-+		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- 		if (qpriv->is_dmacoherent)
- 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
-@@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ah
- 
- 	case AHCI_LS2088A:
- 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
-+		writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
-+		writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
- 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- 		if (qpriv->is_dmacoherent)
- 			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
diff --git a/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch b/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch
deleted file mode 100644
index dcd153560..000000000
--- a/target/linux/layerscape/patches-4.14/811-clock-support-layerscape.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From d94f8863307c0f7fb7aeb2084cc666c47991d78b Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Mon, 19 Nov 2018 10:26:57 +0800
-Subject: [PATCH] clock: support layerscape
-This is an integrated patch of clock for layerscape
-
-Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/clk/clk-qoriq.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/clk-qoriq.c
-+++ b/drivers/clk/clk-qoriq.c
-@@ -41,7 +41,7 @@ struct clockgen_pll_div {
- };
- 
- struct clockgen_pll {
--	struct clockgen_pll_div div[4];
-+	struct clockgen_pll_div div[8];
- };
- 
- #define CLKSEL_VALID	1
-@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct
- 		struct clk *clk;
- 		int ret;
- 
-+		/*
-+		 * For platform PLL, there are 8 divider clocks.
-+		 * For core PLL, there are 4 divider clocks at most.
-+		 */
-+		if (idx != 0 && i >= 4)
-+			break;
-+
- 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
- 			 "cg-pll%d-div%d", idx, i + 1);
- 
diff --git a/target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch b/target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch
deleted file mode 100644
index 1c8ae2578..000000000
--- a/target/linux/layerscape/patches-4.14/812-flexspi-support-layerscape.patch
+++ /dev/null
@@ -1,182 +0,0 @@
-From 31d0f8f19246c9a2fbecb5ca0a03ef6bb70eee2d Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 9 Nov 2018 19:32:53 +0800
-Subject: [PATCH] flexspi: support layerscape
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This is an integrated patch of flexspi for layerscape
-
-Signed-off-by: Alistair Strachan <astrachan@google.com>
-Signed-off-by: Ariel Elior <Ariel.Elior@cavium.com>
-Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Joe Thornber <ejt@redhat.com>
-Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
-Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
-Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-Signed-off-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Mike Snitzer <snitzer@redhat.com>
-Signed-off-by: Peng Li <lipeng321@huawei.com>
-Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
-Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
-Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
-Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/md/dm-thin.c                      | 13 +++++++++++++
- drivers/net/ethernet/qlogic/qed/qed_mcp.c |  7 +++++++
- drivers/net/phy/xilinx_gmii2rgmii.c       |  5 +++++
- drivers/spi/spi-tegra20-slink.c           | 18 ++++++++++++++++++
- drivers/staging/android/ashmem.c          |  6 ++++++
- drivers/tty/serial/imx.c                  |  8 ++++++++
- kernel/events/core.c                      |  6 ++++++
- sound/soc/soc-dapm.c                      |  7 +++++++
- 8 files changed, 70 insertions(+)
-
---- a/drivers/md/dm-thin.c
-+++ b/drivers/md/dm-thin.c
-@@ -3645,6 +3645,19 @@ static int process_create_thin_mesg(unsi
- 		return r;
- 	}
- 
-+	r = dm_pool_get_free_metadata_block_count(pool->pmd, &free_blocks);
-+	if (r) {
-+		metadata_operation_failed(pool, "dm_pool_get_free_metadata_block_count", r);
-+		return r;
-+	}
-+
-+	if (!free_blocks) {
-+		/* Let's commit before we use up the metadata reserve. */
-+		r = commit(pool);
-+		if (r)
-+			return r;
-+	}
-+
- 	return 0;
- }
- 
---- a/drivers/net/ethernet/qlogic/qed/qed_mcp.c
-+++ b/drivers/net/ethernet/qlogic/qed/qed_mcp.c
-@@ -616,6 +616,13 @@ static int qed_mcp_cmd_and_union(struct
- 		return -EBUSY;
- 	}
- 
-+	if (p_hwfn->mcp_info->b_block_cmd) {
-+		DP_NOTICE(p_hwfn,
-+			  "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
-+			  p_mb_params->cmd, p_mb_params->param);
-+		return -EBUSY;
-+	}
-+
- 	if (p_mb_params->data_src_size > union_data_size ||
- 	    p_mb_params->data_dst_size > union_data_size) {
- 		DP_ERR(p_hwfn,
---- a/drivers/net/phy/xilinx_gmii2rgmii.c
-+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
-@@ -89,6 +89,11 @@ static int xgmiitorgmii_probe(struct mdi
- 		return -EPROBE_DEFER;
- 	}
- 
-+	if (!priv->phy_dev->drv) {
-+		dev_info(dev, "Attached phy not ready\n");
-+		return -EPROBE_DEFER;
-+	}
-+
- 	priv->addr = mdiodev->addr;
- 	priv->phy_drv = priv->phy_dev->drv;
- 	memcpy(&priv->conv_phy_drv, priv->phy_dev->drv,
---- a/drivers/spi/spi-tegra20-slink.c
-+++ b/drivers/spi/spi-tegra20-slink.c
-@@ -1081,6 +1081,24 @@ static int tegra_slink_probe(struct plat
- 		goto exit_free_master;
- 	}
- 
-+	/* disabled clock may cause interrupt storm upon request */
-+	tspi->clk = devm_clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(tspi->clk)) {
-+		ret = PTR_ERR(tspi->clk);
-+		dev_err(&pdev->dev, "Can not get clock %d\n", ret);
-+		goto exit_free_master;
-+	}
-+	ret = clk_prepare(tspi->clk);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
-+		goto exit_free_master;
-+	}
-+	ret = clk_enable(tspi->clk);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
-+		goto exit_free_master;
-+	}
-+
- 	spi_irq = platform_get_irq(pdev, 0);
- 	tspi->irq = spi_irq;
- 	ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
---- a/drivers/staging/android/ashmem.c
-+++ b/drivers/staging/android/ashmem.c
-@@ -380,6 +380,12 @@ static int ashmem_mmap(struct file *file
- 		goto out;
- 	}
- 
-+	/* requested mapping size larger than object size */
-+	if (vma->vm_end - vma->vm_start > PAGE_ALIGN(asma->size)) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
- 	/* requested protection bits must match our allowed protection mask */
- 	if (unlikely((vma->vm_flags & ~calc_vm_prot_bits(asma->prot_mask, 0)) &
- 		     calc_vm_prot_bits(PROT_MASK, 0))) {
---- a/drivers/tty/serial/imx.c
-+++ b/drivers/tty/serial/imx.c
-@@ -2221,6 +2221,14 @@ static int serial_imx_probe(struct platf
- 				ret);
- 			return ret;
- 		}
-+
-+		ret = devm_request_irq(&pdev->dev, rtsirq, imx_rtsint, 0,
-+				       dev_name(&pdev->dev), sport);
-+		if (ret) {
-+			dev_err(&pdev->dev, "failed to request rts irq: %d\n",
-+				ret);
-+			return ret;
-+		}
- 	} else {
- 		ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
- 				       dev_name(&pdev->dev), sport);
---- a/kernel/events/core.c
-+++ b/kernel/events/core.c
-@@ -3763,6 +3763,12 @@ int perf_event_read_local(struct perf_ev
- 		goto out;
- 	}
- 
-+	/* If this is a pinned event it must be running on this CPU */
-+	if (event->attr.pinned && event->oncpu != smp_processor_id()) {
-+		ret = -EBUSY;
-+		goto out;
-+	}
-+
- 	/*
- 	 * If the event is currently on this CPU, its either a per-task event,
- 	 * or local to this CPU. Furthermore it means its ACTIVE (otherwise
---- a/sound/soc/soc-dapm.c
-+++ b/sound/soc/soc-dapm.c
-@@ -4012,6 +4012,13 @@ int snd_soc_dapm_link_dai_widgets(struct
- 			continue;
- 		}
- 
-+		/* let users know there is no DAI to link */
-+		if (!dai_w->priv) {
-+			dev_dbg(card->dev, "dai widget %s has no DAI\n",
-+				dai_w->name);
-+			continue;
-+		}
-+
- 		dai = dai_w->priv;
- 
- 		/* ...find all widgets with the same stream and link them */
diff --git a/target/linux/layerscape/patches-4.14/814-ls2-console-support-layerscape.patch b/target/linux/layerscape/patches-4.14/814-ls2-console-support-layerscape.patch
deleted file mode 100644
index 090986bd8..000000000
--- a/target/linux/layerscape/patches-4.14/814-ls2-console-support-layerscape.patch
+++ /dev/null
@@ -1,316 +0,0 @@
-From c64d8ab6260330fa2fe9a2d676256697e4e2a83c Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:44 +0800
-Subject: [PATCH 31/40] ls2-console: support layerscape
-This is an integrated patch of ls2-console for
- layerscape
-
-Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/soc/fsl/ls2-console/Kconfig       |   4 +
- drivers/soc/fsl/ls2-console/Makefile      |   1 +
- drivers/soc/fsl/ls2-console/ls2-console.c | 284 ++++++++++++++++++++++
- 3 files changed, 289 insertions(+)
- create mode 100644 drivers/soc/fsl/ls2-console/Kconfig
- create mode 100644 drivers/soc/fsl/ls2-console/Makefile
- create mode 100644 drivers/soc/fsl/ls2-console/ls2-console.c
-
---- /dev/null
-+++ b/drivers/soc/fsl/ls2-console/Kconfig
-@@ -0,0 +1,4 @@
-+config FSL_LS2_CONSOLE
-+        tristate "Layerscape MC and AIOP console support"
-+	depends on ARCH_LAYERSCAPE
-+        default y
---- /dev/null
-+++ b/drivers/soc/fsl/ls2-console/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_FSL_LS2_CONSOLE) += ls2-console.o
---- /dev/null
-+++ b/drivers/soc/fsl/ls2-console/ls2-console.c
-@@ -0,0 +1,284 @@
-+/* Copyright 2015-2016 Freescale Semiconductor Inc.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ * * Redistributions of source code must retain the above copyright
-+ * notice, this list of conditions and the following disclaimer.
-+ * * Redistributions in binary form must reproduce the above copyright
-+ * notice, this list of conditions and the following disclaimer in the
-+ * documentation and/or other materials provided with the distribution.
-+ * * Neither the name of the above-listed copyright holders nor the
-+ * names of any contributors may be used to endorse or promote products
-+ * derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/miscdevice.h>
-+#include <linux/uaccess.h>
-+#include <linux/poll.h>
-+#include <linux/compat.h>
-+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+
-+/* SoC address for the MC firmware base low/high registers */
-+#define SOC_CCSR_MC_FW_BASE_ADDR_REGS 0x8340020
-+#define SOC_CCSR_MC_FW_BASE_ADDR_REGS_SIZE 2
-+/* MC firmware base low/high registers indexes */
-+#define MCFBALR_OFFSET 0
-+#define MCFBAHR_OFFSET 1
-+
-+/* Bit mask used to obtain the most significant part of the MC base address */
-+#define MC_FW_HIGH_ADDR_MASK 0x1FFFF
-+/* Bit mask used to obtain the least significant part of the MC base address */
-+#define MC_FW_LOW_ADDR_MASK 0xE0000000
-+
-+#define MC_BUFFER_OFFSET 0x01000000
-+#define MC_BUFFER_SIZE (1024*1024*16)
-+#define MC_OFFSET_DELTA (MC_BUFFER_OFFSET)
-+
-+#define AIOP_BUFFER_OFFSET 0x06000000
-+#define AIOP_BUFFER_SIZE (1024*1024*16)
-+#define AIOP_OFFSET_DELTA (0)
-+
-+struct log_header {
-+	char magic_word[8]; /* magic word */
-+	uint32_t buf_start; /* holds the 32-bit little-endian
-+			     * offset of the start of the buffer
-+			     */
-+	uint32_t buf_length; /* holds the 32-bit little-endian
-+			      * length of the buffer
-+			      */
-+	uint32_t last_byte; /* holds the 32-bit little-endian offset
-+			     * of the byte after the last byte that
-+			     * was written
-+			     */
-+	char reserved[44];
-+};
-+
-+#define LOG_HEADER_FLAG_BUFFER_WRAPAROUND 0x80000000
-+#define LOG_VERSION_MAJOR 1
-+#define LOG_VERSION_MINOR 0
-+
-+
-+#define invalidate(p) { asm volatile("dc ivac, %0" : : "r" (p) : "memory"); }
-+
-+struct console_data {
-+	char *map_addr;
-+	struct log_header *hdr;
-+	char *start_addr; /* Start of buffer */
-+	char *end_addr; /* End of buffer */
-+	char *end_of_data; /* Current end of data */
-+	char *cur_ptr; /* Last data sent to console */
-+};
-+
-+#define LAST_BYTE(a) ((a) & ~(LOG_HEADER_FLAG_BUFFER_WRAPAROUND))
-+
-+static inline void __adjust_end(struct console_data *cd)
-+{
-+	cd->end_of_data = cd->start_addr
-+				+ LAST_BYTE(le32_to_cpu(cd->hdr->last_byte));
-+}
-+
-+static inline void adjust_end(struct console_data *cd)
-+{
-+	invalidate(cd->hdr);
-+	__adjust_end(cd);
-+}
-+
-+static inline uint64_t get_mc_fw_base_address(void)
-+{
-+	u32 *mcfbaregs = (u32 *) ioremap(SOC_CCSR_MC_FW_BASE_ADDR_REGS,
-+					 SOC_CCSR_MC_FW_BASE_ADDR_REGS_SIZE);
-+	u64 mcfwbase = 0ULL;
-+
-+	mcfwbase  = readl(mcfbaregs + MCFBAHR_OFFSET) & MC_FW_HIGH_ADDR_MASK;
-+	mcfwbase <<= 32;
-+	mcfwbase |= readl(mcfbaregs + MCFBALR_OFFSET) & MC_FW_LOW_ADDR_MASK;
-+	iounmap(mcfbaregs);
-+	pr_info("fsl-ls2-console: MC base address at 0x%016llx\n", mcfwbase);
-+	return mcfwbase;
-+}
-+
-+static int fsl_ls2_generic_console_open(struct inode *node, struct file *fp,
-+				u64 offset, u64 size,
-+				uint8_t *emagic, uint8_t magic_len,
-+				u32 offset_delta)
-+{
-+	struct console_data *cd;
-+	uint8_t *magic;
-+	uint32_t wrapped;
-+
-+	cd = kmalloc(sizeof(*cd), GFP_KERNEL);
-+	if (cd == NULL)
-+		return -ENOMEM;
-+	fp->private_data = cd;
-+	cd->map_addr = ioremap(get_mc_fw_base_address() + offset, size);
-+
-+	cd->hdr = (struct log_header *) cd->map_addr;
-+	invalidate(cd->hdr);
-+
-+	magic = cd->hdr->magic_word;
-+	if (memcmp(magic, emagic, magic_len)) {
-+		pr_info("magic didn't match!\n");
-+		pr_info("expected: %02x %02x %02x %02x %02x %02x %02x %02x\n",
-+				emagic[0], emagic[1], emagic[2], emagic[3],
-+				emagic[4], emagic[5], emagic[6], emagic[7]);
-+		pr_info("    seen: %02x %02x %02x %02x %02x %02x %02x %02x\n",
-+				magic[0], magic[1], magic[2], magic[3],
-+				magic[4], magic[5], magic[6], magic[7]);
-+		kfree(cd);
-+		iounmap(cd->map_addr);
-+		return -EIO;
-+	}
-+
-+	cd->start_addr = cd->map_addr
-+			 + le32_to_cpu(cd->hdr->buf_start) - offset_delta;
-+	cd->end_addr = cd->start_addr + le32_to_cpu(cd->hdr->buf_length);
-+
-+	wrapped = le32_to_cpu(cd->hdr->last_byte)
-+			 & LOG_HEADER_FLAG_BUFFER_WRAPAROUND;
-+
-+	__adjust_end(cd);
-+	if (wrapped && (cd->end_of_data != cd->end_addr))
-+		cd->cur_ptr = cd->end_of_data+1;
-+	else
-+		cd->cur_ptr = cd->start_addr;
-+
-+	return 0;
-+}
-+
-+static int fsl_ls2_mc_console_open(struct inode *node, struct file *fp)
-+{
-+	uint8_t magic_word[] = { 0, 1, 'C', 'M' };
-+
-+	return fsl_ls2_generic_console_open(node, fp,
-+			MC_BUFFER_OFFSET, MC_BUFFER_SIZE,
-+			magic_word, sizeof(magic_word),
-+			MC_OFFSET_DELTA);
-+}
-+
-+static int fsl_ls2_aiop_console_open(struct inode *node, struct file *fp)
-+{
-+	uint8_t magic_word[] = { 'P', 'O', 'I', 'A' };
-+
-+	return fsl_ls2_generic_console_open(node, fp,
-+			AIOP_BUFFER_OFFSET, AIOP_BUFFER_SIZE,
-+			magic_word, sizeof(magic_word),
-+			AIOP_OFFSET_DELTA);
-+}
-+
-+static int fsl_ls2_console_close(struct inode *node, struct file *fp)
-+{
-+	struct console_data *cd = fp->private_data;
-+
-+	iounmap(cd->map_addr);
-+	kfree(cd);
-+	return 0;
-+}
-+
-+ssize_t fsl_ls2_console_read(struct file *fp, char __user *buf, size_t count,
-+			     loff_t *f_pos)
-+{
-+	struct console_data *cd = fp->private_data;
-+	size_t bytes = 0;
-+	char data;
-+
-+	/* Check if we need to adjust the end of data addr */
-+	adjust_end(cd);
-+
-+	while ((count != bytes) && (cd->end_of_data != cd->cur_ptr)) {
-+		if (((u64)cd->cur_ptr) % 64 == 0)
-+			invalidate(cd->cur_ptr);
-+
-+		data = *(cd->cur_ptr);
-+		if (copy_to_user(&buf[bytes], &data, 1))
-+			return -EFAULT;
-+		cd->cur_ptr++;
-+		if (cd->cur_ptr >= cd->end_addr)
-+			cd->cur_ptr = cd->start_addr;
-+		++bytes;
-+	}
-+	return bytes;
-+}
-+
-+static const struct file_operations fsl_ls2_mc_console_fops = {
-+	.owner          = THIS_MODULE,
-+	.open           = fsl_ls2_mc_console_open,
-+	.release        = fsl_ls2_console_close,
-+	.read           = fsl_ls2_console_read,
-+};
-+
-+static struct miscdevice fsl_ls2_mc_console_dev = {
-+	.minor = MISC_DYNAMIC_MINOR,
-+	.name = "fsl_mc_console",
-+	.fops = &fsl_ls2_mc_console_fops
-+};
-+
-+static const struct file_operations fsl_ls2_aiop_console_fops = {
-+	.owner          = THIS_MODULE,
-+	.open           = fsl_ls2_aiop_console_open,
-+	.release        = fsl_ls2_console_close,
-+	.read           = fsl_ls2_console_read,
-+};
-+
-+static struct miscdevice fsl_ls2_aiop_console_dev = {
-+	.minor = MISC_DYNAMIC_MINOR,
-+	.name = "fsl_aiop_console",
-+	.fops = &fsl_ls2_aiop_console_fops
-+};
-+
-+static int __init fsl_ls2_console_init(void)
-+{
-+	int err = 0;
-+
-+	pr_info("Freescale LS2 console driver\n");
-+	err = misc_register(&fsl_ls2_mc_console_dev);
-+	if (err) {
-+		pr_err("fsl_mc_console: cannot register device\n");
-+		return err;
-+	}
-+	pr_info("fsl-ls2-console: device %s registered\n",
-+		fsl_ls2_mc_console_dev.name);
-+
-+	err = misc_register(&fsl_ls2_aiop_console_dev);
-+	if (err) {
-+		pr_err("fsl_aiop_console: cannot register device\n");
-+		return err;
-+	}
-+	pr_info("fsl-ls2-console: device %s registered\n",
-+		fsl_ls2_aiop_console_dev.name);
-+
-+	return 0;
-+}
-+
-+static void __exit fsl_ls2_console_exit(void)
-+{
-+	misc_deregister(&fsl_ls2_mc_console_dev);
-+
-+	misc_deregister(&fsl_ls2_aiop_console_dev);
-+}
-+
-+module_init(fsl_ls2_console_init);
-+module_exit(fsl_ls2_console_exit);
-+
-+MODULE_AUTHOR("Roy Pledge <roy.pledge@freescale.com>");
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("Freescale LS2 console driver");
diff --git a/target/linux/layerscape/patches-4.14/815-msi-support-layerscape.patch b/target/linux/layerscape/patches-4.14/815-msi-support-layerscape.patch
deleted file mode 100644
index dd2a84e79..000000000
--- a/target/linux/layerscape/patches-4.14/815-msi-support-layerscape.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 56d12979923250799d651b75029ff281928635a4 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:53 +0800
-Subject: [PATCH 32/40] msi: support layerscape
-This is an integrated patch of msi for layerscape
-
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- .../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
- drivers/irqchip/irq-ls-scfg-msi.c                                | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
-+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
-@@ -8,6 +8,7 @@ Required properties:
-               "fsl,ls1043a-msi"
-               "fsl,ls1046a-msi"
-               "fsl,ls1043a-v1.1-msi"
-+              "fsl,ls1012a-msi"
- - msi-controller: indicates that this is a PCIe MSI controller node
- - reg: physical base address of the controller and length of memory mapped.
- - interrupts: an interrupt to the parent interrupt controller.
---- a/drivers/irqchip/irq-ls-scfg-msi.c
-+++ b/drivers/irqchip/irq-ls-scfg-msi.c
-@@ -319,6 +319,7 @@ static const struct of_device_id ls_scfg
- 	{ .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
- 	{ .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
- 
-+	{ .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },
- 	{ .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
- 	{ .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
- 	{ .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
diff --git a/target/linux/layerscape/patches-4.14/816-pcie-support-layerscape.patch b/target/linux/layerscape/patches-4.14/816-pcie-support-layerscape.patch
deleted file mode 100644
index 68d6a31a5..000000000
--- a/target/linux/layerscape/patches-4.14/816-pcie-support-layerscape.patch
+++ /dev/null
@@ -1,596 +0,0 @@
-From c503e92983f2e18c1e18e21b15d5bedd6d0be8ac Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:56 +0800
-Subject: [PATCH 33/40] pcie: support layerscape
-This is an integrated patch of pcie for layerscape
-
-Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
-Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
-Signed-off-by: Po Liu <po.liu@nxp.com>
-Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- .../bindings/pci/layerscape-pci.txt           |  14 +-
- arch/arm/kernel/bios32.c                      |  43 ++++++
- arch/arm64/kernel/pci.c                       |  43 ++++++
- drivers/misc/pci_endpoint_test.c              |  20 +--
- drivers/pci/dwc/Kconfig                       |   8 ++
- drivers/pci/dwc/pci-layerscape.c              | 132 +++++++++++++++++-
- drivers/pci/endpoint/functions/pci-epf-test.c |   2 +-
- drivers/pci/endpoint/pci-epf-core.c           |   8 +-
- drivers/pci/pcie/portdrv_core.c               |  29 ++++
- drivers/pci/quirks.c                          |  15 ++
- include/linux/pci.h                           |   1 +
- 11 files changed, 292 insertions(+), 23 deletions(-)
-
---- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
-+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
-@@ -18,11 +18,16 @@ Required properties:
-         "fsl,ls2088a-pcie"
-         "fsl,ls1088a-pcie"
-         "fsl,ls1046a-pcie"
-+        "fsl,ls1012a-pcie"
- - reg: base addresses and lengths of the PCIe controller register blocks.
- - interrupts: A list of interrupt outputs of the controller. Must contain an
-   entry for each entry in the interrupt-names property.
--- interrupt-names: Must include the following entries:
--  "intr": The interrupt that is asserted for controller interrupts
-+- interrupt-names: It could include the following entries:
-+  "aer": Asserted for aer interrupt when chip support the aer interrupt with
-+		 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
-+  "pme": Asserted for pme interrupt when chip support the pme interrupt with
-+		 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
-+  ......
- - fsl,pcie-scfg: Must include two entries.
-   The first entry must be a link to the SCFG device node
-   The second entry must be '0' or '1' based on physical PCIe controller index.
-@@ -38,8 +43,9 @@ Example:
- 		reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
- 		       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
- 		reg-names = "regs", "config";
--		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
--		interrupt-names = "intr";
-+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
-+			<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
-+		interrupt-names = "aer", "pme";
- 		fsl,pcie-scfg = <&scfg 0>;
- 		#address-cells = <3>;
- 		#size-cells = <2>;
---- a/arch/arm/kernel/bios32.c
-+++ b/arch/arm/kernel/bios32.c
-@@ -12,6 +12,8 @@
- #include <linux/slab.h>
- #include <linux/init.h>
- #include <linux/io.h>
-+#include <linux/of_irq.h>
-+#include <linux/pcieport_if.h>
- 
- #include <asm/mach-types.h>
- #include <asm/mach/map.h>
-@@ -65,6 +67,47 @@ void pcibios_report_status(u_int status_
- }
- 
- /*
-+ * Check device tree if the service interrupts are there
-+ */
-+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
-+{
-+	int ret, count = 0;
-+	struct device_node *np = NULL;
-+
-+	if (dev->bus->dev.of_node)
-+		np = dev->bus->dev.of_node;
-+
-+	if (np == NULL)
-+		return 0;
-+
-+	if (!IS_ENABLED(CONFIG_OF_IRQ))
-+		return 0;
-+
-+	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
-+	 * request irq for aer
-+	 */
-+	if (mask & PCIE_PORT_SERVICE_AER) {
-+		ret = of_irq_get_byname(np, "aer");
-+		if (ret > 0) {
-+			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
-+			count++;
-+		}
-+	}
-+
-+	if (mask & PCIE_PORT_SERVICE_PME) {
-+		ret = of_irq_get_byname(np, "pme");
-+		if (ret > 0) {
-+			irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
-+			count++;
-+		}
-+	}
-+
-+	/* TODO: add more service interrupts if there it is in the device tree*/
-+
-+	return count;
-+}
-+
-+/*
-  * We don't use this to fix the device, but initialisation of it.
-  * It's not the correct use for this, but it works.
-  * Note that the arbiter/ISA bridge appears to be buggy, specifically in
---- a/arch/arm64/kernel/pci.c
-+++ b/arch/arm64/kernel/pci.c
-@@ -17,6 +17,8 @@
- #include <linux/mm.h>
- #include <linux/of_pci.h>
- #include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+#include <linux/pcieport_if.h>
- #include <linux/pci.h>
- #include <linux/pci-acpi.h>
- #include <linux/pci-ecam.h>
-@@ -36,6 +38,47 @@ int pcibios_alloc_irq(struct pci_dev *de
- #endif
- 
- /*
-+ * Check device tree if the service interrupts are there
-+ */
-+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
-+{
-+	int ret, count = 0;
-+	struct device_node *np = NULL;
-+
-+	if (dev->bus->dev.of_node)
-+		np = dev->bus->dev.of_node;
-+
-+	if (np == NULL)
-+		return 0;
-+
-+	if (!IS_ENABLED(CONFIG_OF_IRQ))
-+		return 0;
-+
-+	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
-+	 * request irq for aer
-+	 */
-+	if (mask & PCIE_PORT_SERVICE_AER) {
-+		ret = of_irq_get_byname(np, "aer");
-+		if (ret > 0) {
-+			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
-+			count++;
-+		}
-+	}
-+
-+	if (mask & PCIE_PORT_SERVICE_PME) {
-+		ret = of_irq_get_byname(np, "pme");
-+		if (ret > 0) {
-+			irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
-+			count++;
-+		}
-+	}
-+
-+	/* TODO: add more service interrupts if there it is in the device tree*/
-+
-+	return count;
-+}
-+
-+/*
-  * raw_pci_read/write - Platform-specific PCI config space access.
-  */
- int raw_pci_read(unsigned int domain, unsigned int bus,
---- a/drivers/misc/pci_endpoint_test.c
-+++ b/drivers/misc/pci_endpoint_test.c
-@@ -97,6 +97,8 @@ struct pci_endpoint_test {
- 	struct miscdevice miscdev;
- 	enum pci_barno test_reg_bar;
- 	size_t alignment;
-+	char name[20];
-+	int irq_num;
- };
- 
- struct pci_endpoint_test_data {
-@@ -454,9 +456,7 @@ static int pci_endpoint_test_probe(struc
- {
- 	int i;
- 	int err;
--	int irq = 0;
- 	int id;
--	char name[20];
- 	enum pci_barno bar;
- 	void __iomem *base;
- 	struct device *dev = &pdev->dev;
-@@ -501,19 +501,19 @@ static int pci_endpoint_test_probe(struc
- 	pci_set_master(pdev);
- 
- 	if (!no_msi) {
--		irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
--		if (irq < 0)
-+		test->irq_num = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
-+		if (test->irq_num < 0)
- 			dev_err(dev, "failed to get MSI interrupts\n");
- 	}
- 
--	err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
-+	err = request_irq(pdev->irq, pci_endpoint_test_irqhandler,
- 			       IRQF_SHARED, DRV_MODULE_NAME, test);
- 	if (err) {
- 		dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
- 		goto err_disable_msi;
- 	}
- 
--	for (i = 1; i < irq; i++) {
-+	for (i = 1; i < test->irq_num; i++) {
- 		err = devm_request_irq(dev, pdev->irq + i,
- 				       pci_endpoint_test_irqhandler,
- 				       IRQF_SHARED, DRV_MODULE_NAME, test);
-@@ -548,10 +548,10 @@ static int pci_endpoint_test_probe(struc
- 		goto err_iounmap;
- 	}
- 
--	snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
-+	snprintf(test->name, sizeof(test->name), DRV_MODULE_NAME ".%d", id);
- 	misc_device = &test->miscdev;
- 	misc_device->minor = MISC_DYNAMIC_MINOR;
--	misc_device->name = name;
-+	misc_device->name = test->name;
- 	misc_device->fops = &pci_endpoint_test_fops,
- 
- 	err = misc_register(misc_device);
-@@ -584,6 +584,7 @@ err_disable_pdev:
- static void pci_endpoint_test_remove(struct pci_dev *pdev)
- {
- 	int id;
-+	int i;
- 	enum pci_barno bar;
- 	struct pci_endpoint_test *test = pci_get_drvdata(pdev);
- 	struct miscdevice *misc_device = &test->miscdev;
-@@ -599,6 +600,8 @@ static void pci_endpoint_test_remove(str
- 		if (test->bar[bar])
- 			pci_iounmap(pdev, test->bar[bar]);
- 	}
-+	for (i = 0; i < test->irq_num; i++)
-+		free_irq(pdev->irq + i, test);
- 	pci_disable_msi(pdev);
- 	pci_release_regions(pdev);
- 	pci_disable_device(pdev);
-@@ -607,6 +610,7 @@ static void pci_endpoint_test_remove(str
- static const struct pci_device_id pci_endpoint_test_tbl[] = {
- 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
- 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
-+	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID) },
- 	{ }
- };
- MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
---- a/drivers/pci/dwc/Kconfig
-+++ b/drivers/pci/dwc/Kconfig
-@@ -111,6 +111,14 @@ config PCI_LAYERSCAPE
- 	help
- 	  Say Y here if you want PCIe controller support on Layerscape SoCs.
- 
-+config PCI_LAYERSCAPE_EP
-+	bool "PCI layerscape Endpoint Mode"
-+	depends on PCI_ENDPOINT
-+	select PCIE_DW_EP
-+	help
-+	 Enables support for the PCIe controller in the layerscape SoC to work in
-+	 endpoint mode.
-+
- config PCI_HISI
- 	depends on OF && ARM64
- 	bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
---- a/drivers/pci/dwc/pci-layerscape.c
-+++ b/drivers/pci/dwc/pci-layerscape.c
-@@ -33,8 +33,15 @@
- 
- /* PEX Internal Configuration Registers */
- #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
-+#define PCIE_ABSERR		0x8d0 /* Bridge Slave Error Response Register */
-+#define PCIE_ABSERR_SETTING	0x9401 /* Forward error of non-posted request */
- 
-+#define PCIE_DBI2_BASE		0x1000	/* DBI2 base address*/
-+#define PCIE_MSI_MSG_DATA_OFF	0x5c	/* MSI Data register address*/
-+#define PCIE_MSI_OB_SIZE	4096
-+#define PCIE_MSI_ADDR_OFFSET	(1024 * 1024)
- #define PCIE_IATU_NUM		6
-+#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
- 
- struct ls_pcie_drvdata {
- 	u32 lut_offset;
-@@ -44,12 +51,20 @@ struct ls_pcie_drvdata {
- 	const struct dw_pcie_ops *dw_pcie_ops;
- };
- 
-+struct ls_pcie_ep {
-+	dma_addr_t msi_phys_addr;
-+	void __iomem *msi_virt_addr;
-+	u64 msi_msg_addr;
-+	u16 msi_msg_data;
-+};
-+
- struct ls_pcie {
- 	struct dw_pcie *pci;
- 	void __iomem *lut;
- 	struct regmap *scfg;
- 	const struct ls_pcie_drvdata *drvdata;
- 	int index;
-+	struct ls_pcie_ep *pcie_ep;
- };
- 
- #define to_ls_pcie(x)	dev_get_drvdata((x)->dev)
-@@ -124,6 +139,14 @@ static int ls_pcie_link_up(struct dw_pci
- 	return 1;
- }
- 
-+/* Forward error response of outbound non-posted requests */
-+static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
-+{
-+	struct dw_pcie *pci = pcie->pci;
-+
-+	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
-+}
-+
- static int ls_pcie_host_init(struct pcie_port *pp)
- {
- 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-@@ -135,6 +158,7 @@ static int ls_pcie_host_init(struct pcie
- 	 * dw_pcie_setup_rc() will reconfigure the outbound windows.
- 	 */
- 	ls_pcie_disable_outbound_atus(pcie);
-+	ls_pcie_fix_error_response(pcie);
- 
- 	dw_pcie_dbi_ro_wr_en(pci);
- 	ls_pcie_clear_multifunction(pcie);
-@@ -253,6 +277,7 @@ static struct ls_pcie_drvdata ls2088_drv
- };
- 
- static const struct of_device_id ls_pcie_of_match[] = {
-+	{ .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
- 	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
- 	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
- 	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
-@@ -263,6 +288,99 @@ static const struct of_device_id ls_pcie
- 	{ },
- };
- 
-+static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep)
-+{
-+	iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr);
-+}
-+
-+static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
-+		enum pci_epc_irq_type type, u8 interrupt_num)
-+{
-+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-+	struct ls_pcie *pcie = to_ls_pcie(pci);
-+	struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
-+	u32 free_win;
-+
-+	/* get the msi message address and msi message data */
-+	pcie_ep->msi_msg_addr = ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_L32) |
-+		(((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) << 32);
-+	pcie_ep->msi_msg_data = ioread16(pci->dbi_base + PCIE_MSI_MSG_DATA_OFF);
-+
-+	/* request and config the outband window for msi */
-+	free_win = find_first_zero_bit(&ep->ob_window_map,
-+					sizeof(ep->ob_window_map));
-+	if (free_win >= ep->num_ob_windows) {
-+		dev_err(pci->dev, "no free outbound window\n");
-+		return -ENOMEM;
-+	}
-+
-+	dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
-+					pcie_ep->msi_phys_addr,
-+					pcie_ep->msi_msg_addr,
-+					PCIE_MSI_OB_SIZE);
-+
-+	set_bit(free_win, &ep->ob_window_map);
-+
-+	/* generate the msi interrupt */
-+	ls_pcie_raise_msi_irq(pcie_ep);
-+
-+	/* release the outband window of msi */
-+	dw_pcie_disable_atu(pci, free_win, DW_PCIE_REGION_OUTBOUND);
-+	clear_bit(free_win, &ep->ob_window_map);
-+
-+	return 0;
-+}
-+
-+static struct dw_pcie_ep_ops pcie_ep_ops = {
-+	.raise_irq = ls_pcie_raise_irq,
-+};
-+
-+static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
-+					struct platform_device *pdev)
-+{
-+	struct dw_pcie *pci = pcie->pci;
-+	struct device *dev = pci->dev;
-+	struct dw_pcie_ep *ep;
-+	struct ls_pcie_ep *pcie_ep;
-+	struct resource *cfg_res;
-+	int ret;
-+
-+	ep = &pci->ep;
-+	ep->ops = &pcie_ep_ops;
-+
-+	pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
-+	if (!pcie_ep)
-+		return -ENOMEM;
-+
-+	pcie->pcie_ep = pcie_ep;
-+
-+	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
-+	if (cfg_res) {
-+		ep->phys_base = cfg_res->start;
-+		ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE;
-+	} else {
-+		dev_err(dev, "missing *config* space\n");
-+		return -ENODEV;
-+	}
-+
-+	pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET;
-+
-+	pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr,
-+						PCIE_MSI_OB_SIZE);
-+	if (!pcie_ep->msi_virt_addr) {
-+		dev_err(dev, "failed to map MSI outbound region\n");
-+		return -ENOMEM;
-+	}
-+
-+	ret = dw_pcie_ep_init(ep);
-+	if (ret) {
-+		dev_err(dev, "failed to initialize endpoint\n");
-+		return ret;
-+	}
-+
-+	return 0;
-+}
-+
- static int __init ls_add_pcie_port(struct ls_pcie *pcie)
- {
- 	struct dw_pcie *pci = pcie->pci;
-@@ -309,18 +427,18 @@ static int __init ls_pcie_probe(struct p
- 	if (IS_ERR(pci->dbi_base))
- 		return PTR_ERR(pci->dbi_base);
- 
--	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
-+	pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
- 
--	if (!ls_pcie_is_bridge(pcie))
--		return -ENODEV;
-+	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
- 
- 	platform_set_drvdata(pdev, pcie);
- 
--	ret = ls_add_pcie_port(pcie);
--	if (ret < 0)
--		return ret;
-+	if (!ls_pcie_is_bridge(pcie))
-+		ret = ls_add_pcie_ep(pcie, pdev);
-+	else
-+		ret = ls_add_pcie_port(pcie);
- 
--	return 0;
-+	return ret;
- }
- 
- static struct platform_driver ls_pcie_driver = {
---- a/drivers/pci/endpoint/functions/pci-epf-test.c
-+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
-@@ -471,7 +471,7 @@ static int pci_epf_test_probe(struct pci
- 	const struct pci_epf_device_id *match;
- 	struct pci_epf_test_data *data;
- 	enum pci_barno test_reg_bar = BAR_0;
--	bool linkup_notifier = true;
-+	bool linkup_notifier = false;
- 
- 	match = pci_epf_match_device(pci_epf_test_ids, epf);
- 	data = (struct pci_epf_test_data *)match->driver_data;
---- a/drivers/pci/endpoint/pci-epf-core.c
-+++ b/drivers/pci/endpoint/pci-epf-core.c
-@@ -104,8 +104,8 @@ void pci_epf_free_space(struct pci_epf *
- 	if (!addr)
- 		return;
- 
--	dma_free_coherent(dev, epf->bar[bar].size, addr,
--			  epf->bar[bar].phys_addr);
-+	free_pages((unsigned long)addr,
-+		get_order(epf->bar[bar].size));
- 
- 	epf->bar[bar].phys_addr = 0;
- 	epf->bar[bar].size = 0;
-@@ -129,7 +129,9 @@ void *pci_epf_alloc_space(struct pci_epf
- 		size = 128;
- 	size = roundup_pow_of_two(size);
- 
--	space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
-+	space = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
-+						get_order(size));
-+	phys_addr = virt_to_phys(space);
- 	if (!space) {
- 		dev_err(dev, "failed to allocate mem space\n");
- 		return NULL;
---- a/drivers/pci/pcie/portdrv_core.c
-+++ b/drivers/pci/pcie/portdrv_core.c
-@@ -45,6 +45,20 @@ static void release_pcie_device(struct d
- }
- 
- /**
-+ * pcibios_check_service_irqs - check irqs in the device tree
-+ * @dev: PCI Express port to handle
-+ * @irqs: Array of irqs to populate
-+ * @mask: Bitmask of port capabilities returned by get_port_device_capability()
-+ *
-+ * Return value: 0 means no service irqs in the device tree
-+ *
-+ */
-+int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
-+{
-+	return 0;
-+}
-+
-+/**
-  * pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode
-  * for given port
-  * @dev: PCI Express port to handle
-@@ -185,10 +199,25 @@ out_free_irqs:
- static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
- {
- 	int ret, i;
-+	int irq = -1;
- 
- 	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
- 		irqs[i] = -1;
- 
-+	/* Check if some platforms owns independent irq pins for AER/PME etc.
-+	 * Some platforms may own independent AER/PME interrupts and set
-+	 * them in the device tree file.
-+	 */
-+	ret = pcibios_check_service_irqs(dev, irqs, mask);
-+	if (ret) {
-+		if (dev->irq)
-+			irq = dev->irq;
-+		for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
-+			if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
-+				irqs[i] = irq;
-+		return 0;
-+	}
-+
- 	/*
- 	 * If we support PME or hotplug, but we can't use MSI/MSI-X for
- 	 * them, we have to fall back to INTx or other interrupts, e.g., a
---- a/drivers/pci/quirks.c
-+++ b/drivers/pci/quirks.c
-@@ -3376,6 +3376,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
- DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
- DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
- 
-+/*
-+ * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
-+ * bus reset. Link state of device does not comes UP and so config space
-+ * never accessible again.
-+ */
-+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
-+
- static void quirk_no_pm_reset(struct pci_dev *dev)
- {
- 	/*
-@@ -4857,3 +4864,11 @@ static void quirk_no_ats(struct pci_dev
- /* AMD Stoney platform GPU */
- DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
- #endif /* CONFIG_PCI_ATS */
-+
-+/* Freescale PCIe doesn't support MSI in RC mode */
-+static void quirk_fsl_no_msi(struct pci_dev *pdev)
-+{
-+	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
-+		pdev->no_msi = 1;
-+}
-+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
---- a/include/linux/pci.h
-+++ b/include/linux/pci.h
-@@ -1944,6 +1944,7 @@ void pcibios_release_device(struct pci_d
- void pcibios_penalize_isa_irq(int irq, int active);
- int pcibios_alloc_irq(struct pci_dev *dev);
- void pcibios_free_irq(struct pci_dev *dev);
-+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
- 
- #ifdef CONFIG_HIBERNATE_CALLBACKS
- extern struct dev_pm_ops pcibios_pm_ops;
diff --git a/target/linux/layerscape/patches-4.14/817-platform-security-support-layerscape.patch b/target/linux/layerscape/patches-4.14/817-platform-security-support-layerscape.patch
deleted file mode 100644
index 8f378d40c..000000000
--- a/target/linux/layerscape/patches-4.14/817-platform-security-support-layerscape.patch
+++ /dev/null
@@ -1,1443 +0,0 @@
-From d2e808b0dcca1b5e850274f770775c355ae36c48 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:27:03 +0800
-Subject: [PATCH 34/40] platfrom-security: support layerscape
-This is an integrated patch of platform-security for
- layerscape
-
-Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
-Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- Documentation/security/keys/secure-key.rst    |  67 ++
- MAINTAINERS                                   |  12 +
- drivers/tee/optee/Kconfig                     |   8 +
- drivers/tee/optee/core.c                      |   2 +-
- include/keys/secure-type.h                    |  33 +
- security/keys/Kconfig                         |  11 +
- security/keys/Makefile                        |   5 +
- security/keys/encrypted-keys/Makefile         |   2 +
- security/keys/encrypted-keys/encrypted.c      |  13 +-
- security/keys/encrypted-keys/encrypted.h      |  13 +
- .../keys/encrypted-keys/masterkey_secure.c    |  37 ++
- security/keys/secure_key.c                    | 339 ++++++++++
- security/keys/securekey_desc.c                | 608 ++++++++++++++++++
- security/keys/securekey_desc.h                | 141 ++++
- 14 files changed, 1288 insertions(+), 3 deletions(-)
- create mode 100644 Documentation/security/keys/secure-key.rst
- create mode 100644 include/keys/secure-type.h
- create mode 100644 security/keys/encrypted-keys/masterkey_secure.c
- create mode 100644 security/keys/secure_key.c
- create mode 100644 security/keys/securekey_desc.c
- create mode 100644 security/keys/securekey_desc.h
-
---- /dev/null
-+++ b/Documentation/security/keys/secure-key.rst
-@@ -0,0 +1,67 @@
-+==========
-+Secure Key
-+==========
-+
-+Secure key is the new type added to kernel key ring service.
-+Secure key is a symmetric type key of minimum length 32 bytes
-+and with maximum possible length to be 128 bytes. It is produced
-+in kernel using the CAAM crypto engine. Userspace can only see
-+the blob for the corresponding key. All the blobs are displayed
-+or loaded in hex ascii.
-+
-+Secure key can be created on platforms which supports CAAM
-+hardware block. Secure key can also be used as a master key to
-+create the encrypted keys along with the existing key types in
-+kernel.
-+
-+Secure key uses CAAM hardware to generate the key and blobify its
-+content for userspace. Generated blobs are tied up with the hardware
-+secret key stored in CAAM, hence the same blob will not be able to
-+de-blobify with the different secret key on another machine.
-+
-+Usage::
-+
-+	keyctl add secure <name> "new <keylen>" <ring>
-+	keyctl load secure <name> "load <hex_blob>" <ring>
-+	keyctl print <key_id>
-+
-+"keyctl add secure" option will create the random data of the
-+specified key len using CAAM and store it as a key in kernel.
-+Key contents will be displayed as blobs to the user in hex ascii.
-+User can input key len from 32 bytes to 128 bytes.
-+
-+"keyctl load secure" option will load the blob contents. In kernel,
-+key will be deirved using input blob and CAAM, along with the secret
-+key stored in CAAM.
-+
-+"keyctl print" will return the hex string of the blob corresponding to
-+key_id. Returned blob will be of key_len + 48 bytes. Extra 48 bytes are
-+the header bytes added by the CAAM.
-+
-+Example of secure key usage::
-+
-+1. Create the secure key with name kmk-master of length 32 bytes::
-+
-+	$ keyctl add secure kmk-master "new 32" @u
-+	46001928
-+
-+	$keyctl show
-+	Session Keyring
-+	1030783626 --alswrv      0 65534  keyring: _uid_ses.0
-+	 695927745 --alswrv      0 65534   \_ keyring: _uid.0
-+	  46001928 --als-rv      0     0       \_ secure: kmk-master
-+
-+2. Print the blob contents for the kmk-master key::
-+
-+	$ keyctl print 46001928
-+	d9743445b640f3d59c1670dddc0bc9c2
-+	34fc9aab7dd05c965e6120025012f029b
-+	07faa4776c4f6ed02899e35a135531e9a
-+	6e5c2b51132f9d5aef28f68738e658296
-+	3fe583177cfe50d2542b659a13039
-+
-+	$ keyctl pipe 46001928 > secure_key.blob
-+
-+3. Load the blob in the user key ring::
-+
-+	$ keyctl load secure kmk-master "load 'cat secure_key.blob'" @u
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -7645,6 +7645,18 @@ F:	include/keys/trusted-type.h
- F:	security/keys/trusted.c
- F:	security/keys/trusted.h
- 
-+KEYS-SECURE
-+M:	Udit Agarwal <udit.agarwal@nxp.com>
-+R:	Sahil Malhotra <sahil.malhotra@nxp.com>
-+L:	linux-security-module@vger.kernel.org
-+L:	keyrings@vger.kernel.org
-+S:	Supported
-+F:	include/keys/secure-type.h
-+F:	security/keys/secure_key.c
-+F:	security/keys/securekey_desc.c
-+F:	security/keys/securekey_desc.h
-+F:	security/keys/encrypted-keys/masterkey_secure.c
-+
- KEYS/KEYRINGS:
- M:	David Howells <dhowells@redhat.com>
- L:	keyrings@vger.kernel.org
---- a/drivers/tee/optee/Kconfig
-+++ b/drivers/tee/optee/Kconfig
-@@ -5,3 +5,11 @@ config OPTEE
- 	help
- 	  This implements the OP-TEE Trusted Execution Environment (TEE)
- 	  driver.
-+
-+config OPTEE_SHM_NUM_PRIV_PAGES
-+	int "Private Shared Memory Pages"
-+	default 1
-+	depends on OPTEE
-+	help
-+	  This sets the number of private shared memory pages to be
-+	  used by OP-TEE TEE driver.
---- a/drivers/tee/optee/core.c
-+++ b/drivers/tee/optee/core.c
-@@ -31,7 +31,7 @@
- 
- #define DRIVER_NAME "optee"
- 
--#define OPTEE_SHM_NUM_PRIV_PAGES	1
-+#define OPTEE_SHM_NUM_PRIV_PAGES	CONFIG_OPTEE_SHM_NUM_PRIV_PAGES
- 
- /**
-  * optee_from_msg_param() - convert from OPTEE_MSG parameters to
---- /dev/null
-+++ b/include/keys/secure-type.h
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2018 NXP.
-+ *
-+ */
-+
-+#ifndef _KEYS_SECURE_TYPE_H
-+#define _KEYS_SECURE_TYPE_H
-+
-+#include <linux/key.h>
-+#include <linux/rcupdate.h>
-+
-+/* Minimum key size to be used is 32 bytes and maximum key size fixed
-+ * is 128 bytes.
-+ * Blob size to be kept is Maximum key size + blob header added by CAAM.
-+ */
-+
-+#define MIN_KEY_SIZE                    32
-+#define MAX_KEY_SIZE                    128
-+#define BLOB_HEADER_SIZE		48
-+
-+#define MAX_BLOB_SIZE                   (MAX_KEY_SIZE + BLOB_HEADER_SIZE)
-+
-+struct secure_key_payload {
-+	struct rcu_head rcu;
-+	unsigned int key_len;
-+	unsigned int blob_len;
-+	unsigned char key[MAX_KEY_SIZE + 1];
-+	unsigned char blob[MAX_BLOB_SIZE];
-+};
-+
-+extern struct key_type key_type_secure;
-+#endif
---- a/security/keys/Kconfig
-+++ b/security/keys/Kconfig
-@@ -71,6 +71,17 @@ config TRUSTED_KEYS
- 
- 	  If you are unsure as to whether this is required, answer N.
- 
-+config SECURE_KEYS
-+	tristate "SECURE_KEYS"
-+	depends on KEYS && CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
-+	help
-+	  This option provide support for creating secure-type key and blobs
-+	  in kernel. Secure keys are random number symmetric keys generated
-+	  from CAAM. The CAAM creates the blobs for the random key.
-+	  Userspace will only be able to see the blob.
-+
-+	  If you are unsure as to whether this is required, answer N.
-+
- config ENCRYPTED_KEYS
- 	tristate "ENCRYPTED KEYS"
- 	depends on KEYS
---- a/security/keys/Makefile
-+++ b/security/keys/Makefile
-@@ -28,4 +28,9 @@ obj-$(CONFIG_KEY_DH_OPERATIONS) += dh.o
- #
- obj-$(CONFIG_BIG_KEYS) += big_key.o
- obj-$(CONFIG_TRUSTED_KEYS) += trusted.o
-+CFLAGS_secure_key.o += -I$(obj)/../../drivers/crypto/caam/
-+CFLAGS_securekey_desc.o += -I$(obj)/../../drivers/crypto/caam/
-+obj-$(CONFIG_SECURE_KEYS) += securekey.o
-+securekey-y := securekey_desc.o \
-+	       secure_key.o
- obj-$(CONFIG_ENCRYPTED_KEYS) += encrypted-keys/
---- a/security/keys/encrypted-keys/Makefile
-+++ b/security/keys/encrypted-keys/Makefile
-@@ -7,5 +7,7 @@ obj-$(CONFIG_ENCRYPTED_KEYS) += encrypte
- 
- encrypted-keys-y := encrypted.o ecryptfs_format.o
- masterkey-$(CONFIG_TRUSTED_KEYS) := masterkey_trusted.o
-+masterkey-$(CONFIG_SECURE_KEYS) := masterkey_secure.o
- masterkey-$(CONFIG_TRUSTED_KEYS)-$(CONFIG_ENCRYPTED_KEYS) := masterkey_trusted.o
-+masterkey-$(CONFIG_SECURE_KEYS)-$(CONFIG_ENCRYPTED_KEYS) := masterkey_secure.o
- encrypted-keys-y += $(masterkey-y) $(masterkey-m-m)
---- a/security/keys/encrypted-keys/encrypted.c
-+++ b/security/keys/encrypted-keys/encrypted.c
-@@ -39,6 +39,7 @@
- #include "ecryptfs_format.h"
- 
- static const char KEY_TRUSTED_PREFIX[] = "trusted:";
-+static const char KEY_SECURE_PREFIX[] = "secure:";
- static const char KEY_USER_PREFIX[] = "user:";
- static const char hash_alg[] = "sha256";
- static const char hmac_alg[] = "hmac(sha256)";
-@@ -49,6 +50,7 @@ static unsigned int ivsize;
- static int blksize;
- 
- #define KEY_TRUSTED_PREFIX_LEN (sizeof (KEY_TRUSTED_PREFIX) - 1)
-+#define KEY_SECURE_PREFIX_LEN (sizeof(KEY_SECURE_PREFIX) - 1)
- #define KEY_USER_PREFIX_LEN (sizeof (KEY_USER_PREFIX) - 1)
- #define KEY_ECRYPTFS_DESC_LEN 16
- #define HASH_SIZE SHA256_DIGEST_SIZE
-@@ -125,7 +127,7 @@ static int valid_ecryptfs_desc(const cha
- /*
-  * valid_master_desc - verify the 'key-type:desc' of a new/updated master-key
-  *
-- * key-type:= "trusted:" | "user:"
-+ * key-type:= "trusted:" | "user:" | "secure:"
-  * desc:= master-key description
-  *
-  * Verify that 'key-type' is valid and that 'desc' exists. On key update,
-@@ -140,6 +142,8 @@ static int valid_master_desc(const char
- 
- 	if (!strncmp(new_desc, KEY_TRUSTED_PREFIX, KEY_TRUSTED_PREFIX_LEN))
- 		prefix_len = KEY_TRUSTED_PREFIX_LEN;
-+	else if (!strncmp(new_desc, KEY_SECURE_PREFIX, KEY_SECURE_PREFIX_LEN))
-+		prefix_len = KEY_SECURE_PREFIX_LEN;
- 	else if (!strncmp(new_desc, KEY_USER_PREFIX, KEY_USER_PREFIX_LEN))
- 		prefix_len = KEY_USER_PREFIX_LEN;
- 	else
-@@ -358,7 +362,7 @@ static int calc_hmac(u8 *digest, const u
- 
- enum derived_key_type { ENC_KEY, AUTH_KEY };
- 
--/* Derive authentication/encryption key from trusted key */
-+/* Derive authentication/encryption key from trusted/secure key */
- static int get_derived_key(u8 *derived_key, enum derived_key_type key_type,
- 			   const u8 *master_key, size_t master_keylen)
- {
-@@ -429,6 +433,11 @@ static struct key *request_master_key(st
- 		mkey = request_trusted_key(epayload->master_desc +
- 					   KEY_TRUSTED_PREFIX_LEN,
- 					   master_key, master_keylen);
-+	} else if (!strncmp(epayload->master_desc, KEY_SECURE_PREFIX,
-+			    KEY_SECURE_PREFIX_LEN)) {
-+		mkey = request_secure_key(epayload->master_desc +
-+					  KEY_SECURE_PREFIX_LEN,
-+					  master_key, master_keylen);
- 	} else if (!strncmp(epayload->master_desc, KEY_USER_PREFIX,
- 			    KEY_USER_PREFIX_LEN)) {
- 		mkey = request_user_key(epayload->master_desc +
---- a/security/keys/encrypted-keys/encrypted.h
-+++ b/security/keys/encrypted-keys/encrypted.h
-@@ -16,6 +16,19 @@ static inline struct key *request_truste
- }
- #endif
- 
-+#if defined(CONFIG_SECURE_KEYS)
-+extern struct key *request_secure_key(const char *secure_desc,
-+				      const u8 **master_key,
-+				      size_t *master_keylen);
-+#else
-+static inline struct key *request_secure_key(const char *secure_desc,
-+					     const u8 **master_key,
-+					     size_t *master_keylen)
-+{
-+	return ERR_PTR(-EOPNOTSUPP);
-+}
-+#endif
-+
- #if ENCRYPTED_DEBUG
- static inline void dump_master_key(const u8 *master_key, size_t master_keylen)
- {
---- /dev/null
-+++ b/security/keys/encrypted-keys/masterkey_secure.c
-@@ -0,0 +1,37 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2018 NXP.
-+ *
-+ */
-+
-+#include <linux/uaccess.h>
-+#include <linux/module.h>
-+#include <linux/err.h>
-+#include <keys/secure-type.h>
-+#include <keys/encrypted-type.h>
-+#include "encrypted.h"
-+
-+/*
-+ * request_secure_key - request the secure key
-+ *
-+ * Secure keys and their blobs are derived from CAAM hardware.
-+ * Userspace manages secure  key-type data, but key data is not
-+ * visible in plain form. It is presented as blobs.
-+ */
-+struct key *request_secure_key(const char *secure_desc,
-+				const u8 **master_key, size_t *master_keylen)
-+{
-+	struct secure_key_payload *spayload;
-+	struct key *skey;
-+
-+	skey = request_key(&key_type_secure, secure_desc, NULL);
-+	if (IS_ERR(skey))
-+		goto error;
-+
-+	down_read(&skey->sem);
-+	spayload = skey->payload.data[0];
-+	*master_key = spayload->key;
-+	*master_keylen = spayload->key_len;
-+error:
-+	return skey;
-+}
---- /dev/null
-+++ b/security/keys/secure_key.c
-@@ -0,0 +1,339 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/* Copyright (C) 2018 NXP
-+ * Secure key is generated using NXP CAAM hardware block. CAAM generates the
-+ * random number (used as a key) and creates its blob for the user.
-+ */
-+
-+#include <linux/slab.h>
-+#include <linux/parser.h>
-+#include <linux/string.h>
-+#include <linux/key-type.h>
-+#include <linux/rcupdate.h>
-+#include <keys/secure-type.h>
-+#include <linux/completion.h>
-+
-+#include "securekey_desc.h"
-+
-+static const char hmac_alg[] = "hmac(sha1)";
-+static const char hash_alg[] = "sha1";
-+
-+static struct crypto_shash *hashalg;
-+static struct crypto_shash *hmacalg;
-+
-+enum {
-+	error = -1,
-+	new_key,
-+	load_blob,
-+};
-+
-+static const match_table_t key_tokens = {
-+	{new_key, "new"},
-+	{load_blob, "load"},
-+	{error, NULL}
-+};
-+
-+static struct secure_key_payload *secure_payload_alloc(struct key *key)
-+{
-+	struct secure_key_payload *sec_key = NULL;
-+	int ret = 0;
-+
-+	ret = key_payload_reserve(key, sizeof(*sec_key));
-+	if (ret < 0)
-+		goto out;
-+
-+	sec_key = kzalloc(sizeof(*sec_key), GFP_KERNEL);
-+	if (!sec_key)
-+		goto out;
-+
-+out:
-+	return sec_key;
-+}
-+
-+/*
-+ * parse_inputdata - parse the keyctl input data and fill in the
-+ *		     payload structure for key or its blob.
-+ * param[in]: data pointer to the data to be parsed for creating key.
-+ * param[in]: p pointer to secure key payload structure to fill parsed data
-+ * On success returns 0, otherwise -EINVAL.
-+ */
-+static int parse_inputdata(char *data, struct secure_key_payload *p)
-+{
-+	substring_t args[MAX_OPT_ARGS];
-+	long keylen = 0;
-+	int ret = -EINVAL;
-+	int key_cmd = -EINVAL;
-+	char *c = NULL;
-+
-+	c = strsep(&data, " \t");
-+	if (!c) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	/* Get the keyctl command i.e. new_key or load_blob etc */
-+	key_cmd = match_token(c, key_tokens, args);
-+
-+	switch (key_cmd) {
-+	case new_key:
-+		/* first argument is key size */
-+		c = strsep(&data, " \t");
-+		if (!c) {
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+
-+		ret = kstrtol(c, 10, &keylen);
-+		if (ret < 0 || keylen < MIN_KEY_SIZE ||
-+						keylen > MAX_KEY_SIZE) {
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+
-+		p->key_len = keylen;
-+		ret = new_key;
-+
-+		break;
-+	case load_blob:
-+		/* first argument is blob data for CAAM*/
-+		c = strsep(&data, " \t");
-+		if (!c) {
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+
-+		/* Blob_len = No of characters in blob/2 */
-+		p->blob_len = strlen(c) / 2;
-+		if (p->blob_len > MAX_BLOB_SIZE) {
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+
-+		ret = hex2bin(p->blob, c, p->blob_len);
-+		if (ret < 0) {
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+		ret = load_blob;
-+
-+		break;
-+	case error:
-+		ret = -EINVAL;
-+		break;
-+	}
-+
-+out:
-+	return ret;
-+}
-+
-+/*
-+ * secure_instantiate - create a new secure type key.
-+ * Supports the operation to generate a new key. A random number
-+ * is generated from CAAM as key data and the corresponding red blob
-+ * is formed and stored as key_blob.
-+ * Also supports the operation to load the blob and key is derived using
-+ * that blob from CAAM.
-+ * On success, return 0. Otherwise return errno.
-+ */
-+static int secure_instantiate(struct key *key,
-+		struct key_preparsed_payload *prep)
-+{
-+	struct secure_key_payload *payload = NULL;
-+	size_t datalen = prep->datalen;
-+	char *data = NULL;
-+	int key_cmd = 0;
-+	int ret = 0;
-+	enum sk_req_type sk_op_type;
-+	struct device *dev = NULL;
-+
-+	if (datalen <= 0 || datalen > 32767 || !prep->data) {
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	data = kmalloc(datalen + 1, GFP_KERNEL);
-+	if (!data) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	memcpy(data, prep->data, datalen);
-+	data[datalen] = '\0';
-+
-+	payload = secure_payload_alloc(key);
-+	if (!payload) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	/* Allocate caam job ring for operation to be performed from CAAM */
-+	dev = caam_jr_alloc();
-+	if (!dev) {
-+		pr_info("caam_jr_alloc failed\n");
-+		ret = -ENODEV;
-+		goto out;
-+	}
-+
-+	key_cmd = parse_inputdata(data, payload);
-+	if (key_cmd < 0) {
-+		ret = key_cmd;
-+		goto out;
-+	}
-+
-+	switch (key_cmd) {
-+	case load_blob:
-+		/*
-+		 * Red blob decryption to be done for load operation
-+		 * to derive the key.
-+		 */
-+		sk_op_type = sk_red_blob_dec;
-+		ret = key_deblob(payload, sk_op_type, dev);
-+		if (ret != 0) {
-+			pr_info("secure_key: key_blob decap fail (%d)\n", ret);
-+			goto out;
-+		}
-+		break;
-+	case new_key:
-+		/* Get Random number from caam of the specified length */
-+		sk_op_type = sk_get_random;
-+		ret = caam_get_random(payload, sk_op_type, dev);
-+		if (ret != 0) {
-+			pr_info("secure_key: get_random fail (%d)\n", ret);
-+			goto out;
-+		}
-+
-+		/* Generate red blob of key random bytes with CAAM */
-+		sk_op_type = sk_red_blob_enc;
-+		ret = key_blob(payload, sk_op_type, dev);
-+		if (ret != 0) {
-+			pr_info("secure_key: key_blob encap fail (%d)\n", ret);
-+			goto out;
-+		}
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+out:
-+	if (data)
-+		kzfree(data);
-+	if (dev)
-+		caam_jr_free(dev);
-+
-+	if (!ret)
-+		rcu_assign_keypointer(key, payload);
-+	else
-+		kzfree(payload);
-+
-+	return ret;
-+}
-+
-+/*
-+ * secure_read - copy the  blob data to userspace in hex.
-+ * param[in]: key pointer to key struct
-+ * param[in]: buffer pointer to user data for creating key
-+ * param[in]: buflen is the length of the buffer
-+ * On success, return to userspace the secure key data size.
-+ */
-+static long secure_read(const struct key *key, char __user *buffer,
-+			 size_t buflen)
-+{
-+	const struct secure_key_payload *p = NULL;
-+	char *ascii_buf;
-+	char *bufp;
-+	int i;
-+
-+	p = dereference_key_locked(key);
-+	if (!p)
-+		return -EINVAL;
-+
-+	if (buffer && buflen >= 2 * p->blob_len) {
-+		ascii_buf = kmalloc(2 * p->blob_len, GFP_KERNEL);
-+		if (!ascii_buf)
-+			return -ENOMEM;
-+
-+		bufp = ascii_buf;
-+		for (i = 0; i < p->blob_len; i++)
-+			bufp = hex_byte_pack(bufp, p->blob[i]);
-+		if (copy_to_user(buffer, ascii_buf, 2 * p->blob_len) != 0) {
-+			kzfree(ascii_buf);
-+			return -EFAULT;
-+		}
-+		kzfree(ascii_buf);
-+	}
-+	return 2 * p->blob_len;
-+}
-+
-+/*
-+ * secure_destroy - clear and free the key's payload
-+ */
-+static void secure_destroy(struct key *key)
-+{
-+	kzfree(key->payload.data[0]);
-+}
-+
-+struct key_type key_type_secure = {
-+	.name = "secure",
-+	.instantiate = secure_instantiate,
-+	.destroy = secure_destroy,
-+	.read = secure_read,
-+};
-+EXPORT_SYMBOL_GPL(key_type_secure);
-+
-+static void secure_shash_release(void)
-+{
-+	if (hashalg)
-+		crypto_free_shash(hashalg);
-+	if (hmacalg)
-+		crypto_free_shash(hmacalg);
-+}
-+
-+static int __init secure_shash_alloc(void)
-+{
-+	int ret;
-+
-+	hmacalg = crypto_alloc_shash(hmac_alg, 0, CRYPTO_ALG_ASYNC);
-+	if (IS_ERR(hmacalg)) {
-+		pr_info("secure_key: could not allocate crypto %s\n",
-+				hmac_alg);
-+		return PTR_ERR(hmacalg);
-+	}
-+
-+	hashalg = crypto_alloc_shash(hash_alg, 0, CRYPTO_ALG_ASYNC);
-+	if (IS_ERR(hashalg)) {
-+		pr_info("secure_key: could not allocate crypto %s\n",
-+				hash_alg);
-+		ret = PTR_ERR(hashalg);
-+		goto hashalg_fail;
-+	}
-+
-+	return 0;
-+
-+hashalg_fail:
-+	crypto_free_shash(hmacalg);
-+	return ret;
-+}
-+
-+static int __init init_secure_key(void)
-+{
-+	int ret;
-+
-+	ret = secure_shash_alloc();
-+	if (ret < 0)
-+		return ret;
-+
-+	ret = register_key_type(&key_type_secure);
-+	if (ret < 0)
-+		secure_shash_release();
-+	return ret;
-+}
-+
-+static void __exit cleanup_secure_key(void)
-+{
-+	secure_shash_release();
-+	unregister_key_type(&key_type_secure);
-+}
-+
-+late_initcall(init_secure_key);
-+module_exit(cleanup_secure_key);
-+
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/security/keys/securekey_desc.c
-@@ -0,0 +1,608 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2018 NXP
-+ *
-+ */
-+
-+#include <keys/secure-type.h>
-+#include "securekey_desc.h"
-+
-+/* key modifier for blob encapsulation & decapsulation descriptor */
-+u8 key_modifier[] = "SECURE_KEY";
-+u32 key_modifier_len = 10;
-+
-+void caam_sk_rng_desc(struct sk_req *skreq, struct sk_desc *skdesc)
-+{
-+	struct sk_fetch_rnd_data *fetch_rnd_data = NULL;
-+	struct random_desc *rnd_desc = NULL;
-+	size_t len = 0;
-+	u32 *desc = skreq->hwdesc;
-+
-+	init_job_desc(desc, 0);
-+
-+	fetch_rnd_data = &skreq->req_u.sk_fetch_rnd_data;
-+	rnd_desc = &skdesc->dma_u.random_descp;
-+	len = fetch_rnd_data->key_len;
-+
-+	/* command 0x82500000 */
-+	append_cmd(desc, CMD_OPERATION | OP_TYPE_CLASS1_ALG |
-+			OP_ALG_ALGSEL_RNG);
-+	/* command 0x60340000 | len */
-+	append_cmd(desc, CMD_FIFO_STORE | FIFOST_TYPE_RNGSTORE | len);
-+	append_ptr(desc, rnd_desc->rnd_data);
-+}
-+
-+void caam_sk_redblob_encap_desc(struct sk_req *skreq, struct sk_desc *skdesc)
-+{
-+	struct redblob_encap_desc *red_blob_desc =
-+					&skdesc->dma_u.redblob_encapdesc;
-+	struct sk_red_blob_encap *red_blob_req =
-+					&skreq->req_u.sk_red_blob_encap;
-+	u32 *desc = skreq->hwdesc;
-+
-+	init_job_desc(desc, 0);
-+
-+	/* Load class 2 key with key modifier. */
-+	append_key_as_imm(desc, key_modifier, key_modifier_len,
-+			  key_modifier_len, CLASS_2 | KEY_DEST_CLASS_REG);
-+
-+	/* SEQ IN PTR Command. */
-+	append_seq_in_ptr(desc, red_blob_desc->in_data, red_blob_req->data_sz,
-+			  0);
-+
-+	/* SEQ OUT PTR Command. */
-+	append_seq_out_ptr(desc, red_blob_desc->redblob,
-+			   red_blob_req->redblob_sz, 0);
-+
-+	/* RedBlob encapsulation PROTOCOL Command. */
-+	append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB);
-+}
-+
-+/* void caam_sk_redblob_decap_desc(struct sk_req *skreq, struct sk_desc *skdesc)
-+ * brief CAAM Descriptor creator from redblob to plaindata.
-+ * param[in] skreq Pointer to secure key request structure
-+ * param[in] skdesc Pointer to secure key descriptor structure
-+ */
-+void caam_sk_redblob_decap_desc(struct sk_req *skreq, struct sk_desc *skdesc)
-+{
-+	struct redblob_decap_desc *red_blob_desc =
-+					&skdesc->dma_u.redblob_decapdesc;
-+	struct sk_red_blob_decap *red_blob_req =
-+					&skreq->req_u.sk_red_blob_decap;
-+	u32 *desc = skreq->hwdesc;
-+
-+	init_job_desc(desc, 0);
-+
-+	/* Load class 2 key with key modifier. */
-+	append_key_as_imm(desc, key_modifier, key_modifier_len,
-+			  key_modifier_len, CLASS_2 | KEY_DEST_CLASS_REG);
-+
-+	/* SEQ IN PTR Command. */
-+	append_seq_in_ptr(desc, red_blob_desc->redblob,
-+			  red_blob_req->redblob_sz, 0);
-+
-+	/* SEQ OUT PTR Command. */
-+	append_seq_out_ptr(desc, red_blob_desc->out_data,
-+			   red_blob_req->data_sz, 0);
-+
-+	/* RedBlob decapsulation PROTOCOL Command. */
-+	append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB);
-+}
-+
-+/* int caam_sk_get_random_map(struct device *dev, struct sk_req *req,
-+ *			      struct sk_desc *skdesc)
-+ * brief DMA map the buffer virtual pointers to physical address.
-+ * param[in] dev Pointer to job ring device structure
-+ * param[in] req Pointer to secure key request structure
-+ * param[in] skdesc Pointer to secure key descriptor structure
-+ * return 0 on success, error value otherwise.
-+ */
-+int caam_sk_get_random_map(struct device *dev, struct sk_req *req,
-+			   struct sk_desc *skdesc)
-+{
-+	struct sk_fetch_rnd_data *fetch_rnd_data;
-+	struct random_desc *rnd_desc;
-+
-+	fetch_rnd_data = &req->req_u.sk_fetch_rnd_data;
-+	rnd_desc = &skdesc->dma_u.random_descp;
-+
-+	rnd_desc->rnd_data = dma_map_single(dev, fetch_rnd_data->data,
-+				fetch_rnd_data->key_len, DMA_FROM_DEVICE);
-+
-+	if (dma_mapping_error(dev, rnd_desc->rnd_data)) {
-+		dev_err(dev, "Unable to map memory\n");
-+		goto sk_random_map_fail;
-+	}
-+	return 0;
-+
-+sk_random_map_fail:
-+	return -ENOMEM;
-+}
-+
-+/* int caam_sk_redblob_encap_map(struct device *dev, struct sk_req *req,
-+ *					struct sk_desc *skdesc)
-+ * brief DMA map the buffer virtual pointers to physical address.
-+ * param[in] dev Pointer to job ring device structure
-+ * param[in] req Pointer to secure key request structure
-+ * param[in] skdesc Pointer to secure key descriptor structure
-+ * return 0 on success, error value otherwise.
-+ */
-+int caam_sk_redblob_encap_map(struct device *dev, struct sk_req *req,
-+			      struct sk_desc *skdesc)
-+{
-+	struct sk_red_blob_encap *red_blob_encap;
-+	struct redblob_encap_desc *red_blob_desc;
-+
-+	red_blob_encap = &req->req_u.sk_red_blob_encap;
-+	red_blob_desc = &skdesc->dma_u.redblob_encapdesc;
-+
-+	red_blob_desc->in_data = dma_map_single(dev, red_blob_encap->data,
-+					red_blob_encap->data_sz, DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, red_blob_desc->in_data)) {
-+		dev_err(dev, "Unable to map memory\n");
-+		goto sk_data_fail;
-+	}
-+
-+	red_blob_desc->redblob = dma_map_single(dev, red_blob_encap->redblob,
-+				red_blob_encap->redblob_sz, DMA_FROM_DEVICE);
-+	if (dma_mapping_error(dev, red_blob_desc->redblob)) {
-+		dev_err(dev, "Unable to map memory\n");
-+		goto sk_redblob_fail;
-+	}
-+
-+	return 0;
-+
-+sk_redblob_fail:
-+	dma_unmap_single(dev, red_blob_desc->in_data, red_blob_encap->data_sz,
-+			 DMA_TO_DEVICE);
-+sk_data_fail:
-+	return -ENOMEM;
-+}
-+
-+/* static int caam_sk_redblob_decap_map(struct device *dev,
-+ *					    struct sk_req *req,
-+ *					    struct sk_desc *skdesc)
-+ * brief DMA map the buffer virtual pointers to physical address.
-+ * param[in] dev Pointer to job ring device structure
-+ * param[in] req Pointer to secure key request structure
-+ * param[in] skdesc Pointer to secure key descriptor structure
-+ * return 0 on success, error value otherwise.
-+ */
-+int caam_sk_redblob_decap_map(struct device *dev, struct sk_req *req,
-+			      struct sk_desc *skdesc)
-+{
-+	struct sk_red_blob_decap *red_blob_decap;
-+	struct redblob_decap_desc *red_blob_desc;
-+
-+	red_blob_decap = &req->req_u.sk_red_blob_decap;
-+	red_blob_desc = &skdesc->dma_u.redblob_decapdesc;
-+
-+	red_blob_desc->redblob = dma_map_single(dev, red_blob_decap->redblob,
-+				red_blob_decap->redblob_sz, DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, red_blob_desc->redblob)) {
-+		dev_err(dev, "Unable to map memory\n");
-+		goto sk_redblob_fail;
-+	}
-+
-+	red_blob_desc->out_data = dma_map_single(dev, red_blob_decap->data,
-+				red_blob_decap->data_sz, DMA_FROM_DEVICE);
-+	if (dma_mapping_error(dev, red_blob_desc->out_data)) {
-+		dev_err(dev, "Unable to map memory\n");
-+		goto sk_data_fail;
-+	}
-+
-+	return 0;
-+
-+sk_data_fail:
-+	dma_unmap_single(dev, red_blob_desc->redblob,
-+			 red_blob_decap->redblob_sz, DMA_TO_DEVICE);
-+sk_redblob_fail:
-+	return -ENOMEM;
-+}
-+
-+/* @fn void securekey_unmap(struct device *dev,
-+ *			    struct sk_desc *skdesc, struct sk_req *req)
-+ * @brief DMA unmap the buffer pointers.
-+ * @param[in] dev Pointer to job ring device structure
-+ * @param[in] skdesc Pointer to secure key descriptor structure
-+ * @param[in] req Pointer to secure key request structure
-+ */
-+void securekey_unmap(struct device *dev,
-+		     struct sk_desc *skdesc, struct sk_req *req)
-+{
-+
-+	switch (req->type) {
-+	case sk_get_random:
-+		{
-+			struct sk_fetch_rnd_data *fetch_rnd_data;
-+			struct random_desc *rnd_desc;
-+
-+			fetch_rnd_data = &req->req_u.sk_fetch_rnd_data;
-+			rnd_desc = &skdesc->dma_u.random_descp;
-+
-+			/* Unmap Descriptor buffer pointers. */
-+			dma_unmap_single(dev, rnd_desc->rnd_data,
-+					 fetch_rnd_data->key_len,
-+					 DMA_FROM_DEVICE);
-+			break;
-+		}
-+	case sk_red_blob_enc:
-+		{
-+			struct sk_red_blob_encap *red_blob_encap;
-+			struct redblob_encap_desc *red_blob_desc;
-+
-+			red_blob_encap = &req->req_u.sk_red_blob_encap;
-+			red_blob_desc = &skdesc->dma_u.redblob_encapdesc;
-+
-+			/* Unmap Descriptor buffer pointers. */
-+			dma_unmap_single(dev, red_blob_desc->in_data,
-+					 red_blob_encap->data_sz,
-+					 DMA_TO_DEVICE);
-+
-+			dma_unmap_single(dev, red_blob_desc->redblob,
-+					 red_blob_encap->redblob_sz,
-+					 DMA_FROM_DEVICE);
-+
-+			break;
-+		}
-+	case sk_red_blob_dec:
-+		{
-+			struct sk_red_blob_decap *red_blob_decap;
-+			struct redblob_decap_desc *red_blob_desc;
-+
-+			red_blob_decap = &req->req_u.sk_red_blob_decap;
-+			red_blob_desc = &skdesc->dma_u.redblob_decapdesc;
-+
-+			/* Unmap Descriptor buffer pointers. */
-+			dma_unmap_single(dev, red_blob_desc->redblob,
-+					 red_blob_decap->redblob_sz,
-+					 DMA_TO_DEVICE);
-+
-+			dma_unmap_single(dev, red_blob_desc->out_data,
-+					 red_blob_decap->data_sz,
-+					 DMA_FROM_DEVICE);
-+
-+			break;
-+		}
-+	default:
-+		dev_err(dev, "Unable to find request type\n");
-+		break;
-+	}
-+	kfree(skdesc);
-+}
-+
-+/*  int caam_securekey_desc_init(struct device *dev, struct sk_req *req)
-+ *  brief CAAM Descriptor creator for secure key operations.
-+ *  param[in] dev Pointer to job ring device structure
-+ *  param[in] req Pointer to secure key request structure
-+ *  return 0 on success, error value otherwise.
-+ */
-+int caam_securekey_desc_init(struct device *dev, struct sk_req *req)
-+{
-+	struct sk_desc *skdesc = NULL;
-+	int ret = 0;
-+
-+	switch (req->type) {
-+	case sk_get_random:
-+		{
-+			skdesc = kmalloc(sizeof(*skdesc), GFP_DMA);
-+			if (!skdesc) {
-+				ret = -ENOMEM;
-+				goto out;
-+			}
-+			skdesc->req_type = req->type;
-+
-+			if (caam_sk_get_random_map(dev, req, skdesc)) {
-+				dev_err(dev, "caam get_random map fail\n");
-+				ret = -ENOMEM;
-+				goto out;
-+			}
-+			caam_sk_rng_desc(req, skdesc);
-+			break;
-+		}
-+	case sk_red_blob_enc:
-+		{
-+			skdesc = kmalloc(sizeof(*skdesc), GFP_DMA);
-+			if (!skdesc) {
-+				ret = -ENOMEM;
-+				goto out;
-+			}
-+
-+			skdesc->req_type = req->type;
-+
-+			if (caam_sk_redblob_encap_map(dev, req, skdesc)) {
-+				dev_err(dev, "caam redblob_encap map fail\n");
-+				ret = -ENOMEM;
-+				goto out;
-+			}
-+
-+			/* Descriptor function to create redblob from data. */
-+			caam_sk_redblob_encap_desc(req, skdesc);
-+			break;
-+		}
-+
-+	case sk_red_blob_dec:
-+		{
-+			skdesc = kmalloc(sizeof(*skdesc), GFP_DMA);
-+			if (!skdesc) {
-+				ret = -ENOMEM;
-+				goto out;
-+			}
-+
-+			skdesc->req_type = req->type;
-+
-+			if (caam_sk_redblob_decap_map(dev, req, skdesc)) {
-+				dev_err(dev, "caam redblob_decap map fail\n");
-+				ret = -ENOMEM;
-+				goto out;
-+			}
-+
-+			/* Descriptor function to decap data from redblob. */
-+			caam_sk_redblob_decap_desc(req, skdesc);
-+			break;
-+		}
-+	default:
-+		pr_debug("Unknown request type\n");
-+		ret = -EINVAL;
-+		goto out;
-+	}
-+
-+	req->desc_pointer = (void *)skdesc;
-+
-+out:
-+	return ret;
-+}
-+
-+/* static void caam_op_done (struct device *dev, u32 *desc, u32 ret,
-+ *			     void *context)
-+ * brief callback function to be called when descriptor executed.
-+ * param[in] dev Pointer to device structure
-+ * param[in] desc descriptor pointer
-+ * param[in] ret return status of Job submitted
-+ * param[in] context void pointer
-+ */
-+static void caam_op_done(struct device *dev, u32 *desc, u32 ret,
-+			 void *context)
-+{
-+	struct sk_req *req = context;
-+
-+	if (ret) {
-+		dev_err(dev, "caam op done err: %x\n", ret);
-+		/* print the error source name. */
-+		caam_jr_strstatus(dev, ret);
-+	}
-+	/* Call securekey_unmap function for unmapping the buffer pointers. */
-+	securekey_unmap(dev, req->desc_pointer, req);
-+
-+	req->ret = ret;
-+	complete(&req->comp);
-+}
-+
-+
-+/*  static int sk_job_submit(struct device *jrdev, struct sk_req *req)
-+ *  brief Enqueue a Job descriptor to Job ring and wait until SEC returns.
-+ *  param[in] jrdev Pointer to job ring device structure
-+ *  param[in] req Pointer to secure key request structure
-+ *  return 0 on success, error value otherwise.
-+ */
-+static int sk_job_submit(struct device *jrdev, struct sk_req *req)
-+{
-+	int ret;
-+
-+	init_completion(&req->comp);
-+
-+	/* caam_jr_enqueue function for Enqueue a job descriptor */
-+	ret = caam_jr_enqueue(jrdev, req->hwdesc, caam_op_done, req);
-+	if (!ret)
-+		wait_for_completion_interruptible(&req->comp);
-+
-+	ret = req->ret;
-+	return ret;
-+}
-+
-+/* caam_get_random(struct secure_key_payload *p,  enum sk_req_type fetch_rnd,
-+ *		   struct device *dev)
-+ * Create the random number of the specified length using CAAM block
-+ * param[in]: out pointer to place the random bytes
-+ * param[in]: length for the random data bytes.
-+ * param[in]: dev Pointer to job ring device structure
-+ * If operation is successful return 0, otherwise error.
-+ */
-+int caam_get_random(struct secure_key_payload *p,  enum sk_req_type fetch_rnd,
-+		    struct device *dev)
-+{
-+	struct sk_fetch_rnd_data *fetch_rnd_data = NULL;
-+	struct sk_req *req = NULL;
-+	int ret = 0;
-+	void *temp = NULL;
-+
-+	req = kmalloc(sizeof(struct sk_req), GFP_DMA);
-+	if (!req) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	req->type = fetch_rnd;
-+	fetch_rnd_data = &(req->req_u.sk_fetch_rnd_data);
-+
-+	/* initialise with key length */
-+	fetch_rnd_data->key_len = p->key_len;
-+
-+	temp = kmalloc(fetch_rnd_data->key_len, GFP_DMA);
-+	if (!temp) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+	fetch_rnd_data->data = temp;
-+
-+	ret = caam_securekey_desc_init(dev, req);
-+
-+	if (ret) {
-+		pr_info("caam_securekey_desc_init failed\n");
-+		goto out;
-+	}
-+
-+	ret = sk_job_submit(dev, req);
-+	if (!ret) {
-+		/*Copy output to key buffer. */
-+		memcpy(p->key, fetch_rnd_data->data, p->key_len);
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+out:
-+	if (req)
-+		kfree(req);
-+
-+	if (temp)
-+		kfree(temp);
-+
-+	return ret;
-+}
-+EXPORT_SYMBOL(caam_get_random);
-+
-+/* key_deblob(struct secure_key_payload *p, enum sk_req_type decap_type
-+ *		struct device *dev)
-+ * Deblobify the blob to get the key data and fill in secure key payload struct
-+ * param[in] p pointer to the secure key payload
-+ * param[in] decap_type operation to be done.
-+ * param[in] dev dev Pointer to job ring device structure
-+ * If operation is successful return 0, otherwise error.
-+ */
-+int key_deblob(struct secure_key_payload *p, enum sk_req_type decap_type,
-+	       struct device *dev)
-+{
-+	unsigned int blob_len;
-+	struct sk_red_blob_decap *d_blob;
-+	struct sk_req *req = NULL;
-+	int total_sz = 0, *temp = NULL, ret = 0;
-+
-+	req = kmalloc(sizeof(struct sk_req), GFP_DMA);
-+	if (!req) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	d_blob = &(req->req_u.sk_red_blob_decap);
-+	blob_len = p->blob_len;
-+	req->type = decap_type;
-+
-+	/*
-+	 * Red blob size is the blob_len filled in payload struct
-+	 * Data_sz i.e. key is the blob_len - blob header size
-+	 */
-+
-+	d_blob->redblob_sz = blob_len;
-+	d_blob->data_sz = blob_len - (SK_BLOB_KEY_SZ + SK_BLOB_MAC_SZ);
-+	total_sz = d_blob->data_sz + d_blob->redblob_sz;
-+
-+	temp = kmalloc(total_sz, GFP_DMA);
-+	if (!temp) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	req->mem_pointer = temp;
-+	d_blob->redblob = temp;
-+	d_blob->data = d_blob->redblob + d_blob->redblob_sz;
-+	memcpy(d_blob->redblob, p->blob, blob_len);
-+
-+	ret = caam_securekey_desc_init(dev, req);
-+
-+	if (ret) {
-+		pr_info("caam_securekey_desc_init: Failed\n");
-+		goto out;
-+	}
-+
-+	ret = sk_job_submit(dev, req);
-+	if (!ret) {
-+		/*Copy output to key buffer. */
-+		p->key_len = d_blob->data_sz;
-+		memcpy(p->key, d_blob->data, p->key_len);
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+out:
-+	if (temp)
-+		kfree(temp);
-+	if (req)
-+		kfree(req);
-+	return ret;
-+}
-+EXPORT_SYMBOL(key_deblob);
-+
-+/* key_blob(struct secure_key_payload *p, enum sk_req_type encap_type,
-+ *		struct device *dev)
-+ * To blobify the key data to get the blob. This blob can only be seen by
-+ * userspace.
-+ * param[in] p pointer to the secure key payload
-+ * param[in] decap_type operation to be done.
-+ * param[in] dev dev Pointer to job ring device structure
-+ * If operation is successful return 0, otherwise error.
-+ */
-+int key_blob(struct secure_key_payload *p, enum sk_req_type encap_type,
-+	     struct device *dev)
-+{
-+	unsigned int key_len;
-+	struct sk_red_blob_encap *k_blob;
-+	struct sk_req *req = NULL;
-+	int total_sz = 0, *temp = NULL, ret = 0;
-+
-+	req = kmalloc(sizeof(struct sk_req), GFP_DMA);
-+	if (!req) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	key_len = p->key_len;
-+
-+	req->type = encap_type;
-+	k_blob = &(req->req_u.sk_red_blob_encap);
-+
-+	/*
-+	 * Data_sz i.e. key len and the corresponding blob_len is
-+	 * key_len + BLOB header size.
-+	 */
-+
-+	k_blob->data_sz = key_len;
-+	k_blob->redblob_sz = key_len + SK_BLOB_KEY_SZ + SK_BLOB_MAC_SZ;
-+	total_sz = k_blob->data_sz + k_blob->redblob_sz;
-+
-+	temp = kmalloc(total_sz, GFP_DMA);
-+	if (!temp) {
-+		ret = -ENOMEM;
-+		goto out;
-+	}
-+
-+	req->mem_pointer = temp;
-+	k_blob->data = temp;
-+
-+	k_blob->redblob = k_blob->data + k_blob->data_sz;
-+	memcpy(k_blob->data, p->key, key_len);
-+
-+	ret = caam_securekey_desc_init(dev, req);
-+
-+	if (ret) {
-+		pr_info("caam_securekey_desc_init failed\n");
-+		goto out;
-+	}
-+
-+	ret = sk_job_submit(dev, req);
-+	if (!ret) {
-+		/*Copy output to key buffer. */
-+		p->blob_len = k_blob->redblob_sz;
-+		memcpy(p->blob, k_blob->redblob, p->blob_len);
-+	} else {
-+		ret = -EINVAL;
-+	}
-+
-+out:
-+	if (temp)
-+		kfree(req->mem_pointer);
-+	if (req)
-+		kfree(req);
-+	return ret;
-+
-+}
-+EXPORT_SYMBOL(key_blob);
---- /dev/null
-+++ b/security/keys/securekey_desc.h
-@@ -0,0 +1,141 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright 2018 NXP
-+ *
-+ */
-+#ifndef _SECUREKEY_DESC_H_
-+#define _SECUREKEY_DESC_H_
-+
-+#include "compat.h"
-+#include "regs.h"
-+#include "intern.h"
-+#include "desc.h"
-+#include "desc_constr.h"
-+#include "jr.h"
-+#include "error.h"
-+#include "pdb.h"
-+
-+#define SK_BLOB_KEY_SZ		32	/* Blob key size. */
-+#define SK_BLOB_MAC_SZ		16	/* Blob MAC size. */
-+
-+/*
-+ * brief defines different kinds of operations supported by this module.
-+ */
-+enum sk_req_type {
-+	sk_get_random,
-+	sk_red_blob_enc,
-+	sk_red_blob_dec,
-+};
-+
-+
-+/*
-+ * struct random_des
-+ * param[out] rnd_data output buffer for random data.
-+ */
-+struct random_desc {
-+	dma_addr_t rnd_data;
-+};
-+
-+/* struct redblob_encap_desc
-+ * details Structure containing dma address for redblob encapsulation.
-+ * param[in] in_data input data to redblob encap descriptor.
-+ * param[out] redblob output buffer for redblob.
-+ */
-+struct redblob_encap_desc {
-+	dma_addr_t in_data;
-+	dma_addr_t redblob;
-+};
-+
-+/* struct redblob_decap_desc
-+ * details Structure containing dma address for redblob decapsulation.
-+ * param[in] redblob input buffer to redblob decap descriptor.
-+ * param[out] out_data output data from redblob decap descriptor.
-+ */
-+struct redblob_decap_desc {
-+	dma_addr_t redblob;
-+	dma_addr_t out_data;
-+};
-+
-+/* struct sk_desc
-+ * details Structure for securekey descriptor creation.
-+ * param[in] req_type operation supported.
-+ * param[in] dma_u union of struct for supported operation.
-+ */
-+struct sk_desc {
-+	u32 req_type;
-+	union {
-+		struct redblob_encap_desc redblob_encapdesc;
-+		struct redblob_decap_desc redblob_decapdesc;
-+		struct random_desc random_descp;
-+	} dma_u;
-+};
-+
-+/* struct sk_fetch_rnd_data
-+ * decriptor structure containing key length.
-+ */
-+struct sk_fetch_rnd_data {
-+	void *data;
-+	size_t key_len;
-+};
-+
-+/* struct sk_red_blob_encap
-+ * details Structure containing buffer pointers for redblob encapsulation.
-+ * param[in] data Input data.
-+ * param[in] data_sz size of Input data.
-+ * param[out] redblob output buffer for redblob.
-+ * param[in] redblob_sz size of redblob.
-+ */
-+struct sk_red_blob_encap {
-+	void *data;
-+	uint32_t data_sz;
-+	void *redblob;
-+	uint32_t redblob_sz;
-+};
-+
-+/* struct sk_red_blob_decap
-+ * details Structure containing buffer pointers for redblob decapsulation.
-+ * param[in] redblob Input redblob.
-+ * param[in] redblob_sz size of redblob.
-+ * param[out] data output buffer for data.
-+ * param[in] data_sz size of output data.
-+ */
-+struct sk_red_blob_decap {
-+	void *redblob;
-+	uint32_t redblob_sz;
-+	void *data;
-+	uint32_t data_sz;
-+};
-+
-+/* struct sk_req
-+ * details Structure for securekey request creation.
-+ * param[in] type operation supported.
-+ * param[in] req_u union of struct for supported operation.
-+ * param[out] ret return status of CAAM operation.
-+ * param[in] mem_pointer memory pointer for allocated kernel memory.
-+ * param[in] desc_pointer Pointer to securekey descriptor creation structure.
-+ * param[in] comp struct completion object.
-+ * param[in] hwdesc contains descriptor instructions.
-+ */
-+struct sk_req {
-+	enum sk_req_type type;
-+	void *arg;
-+	union {
-+		struct sk_red_blob_encap sk_red_blob_encap;
-+		struct sk_red_blob_decap sk_red_blob_decap;
-+		struct sk_fetch_rnd_data sk_fetch_rnd_data;
-+	} req_u;
-+	int ret;
-+	void *mem_pointer;
-+	void *desc_pointer;
-+	struct completion comp;
-+	u32 hwdesc[MAX_CAAM_DESCSIZE];
-+};
-+
-+int caam_get_random(struct secure_key_payload *p,  enum sk_req_type fetch_rnd,
-+		    struct device *dev);
-+int key_blob(struct secure_key_payload *p, enum sk_req_type encap_type,
-+	     struct device *dev);
-+int key_deblob(struct secure_key_payload *p, enum sk_req_type decap_type,
-+	       struct device *dev);
-+
-+#endif /*_SECUREKEY_DESC_H_*/
diff --git a/target/linux/layerscape/patches-4.14/818-qspi-support-layerscape.patch b/target/linux/layerscape/patches-4.14/818-qspi-support-layerscape.patch
deleted file mode 100644
index 945f7b244..000000000
--- a/target/linux/layerscape/patches-4.14/818-qspi-support-layerscape.patch
+++ /dev/null
@@ -1,774 +0,0 @@
-From 60eee49f37b77bc2d5f46c5db5a5c24d0c31bd02 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 20 Nov 2018 15:36:57 +0800
-Subject: [PATCH] qspi: support layerscape
-
-This is an integrated patch of qspi for layerscape
-
-Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
-Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
-Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
-Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
-Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
----
- .../devicetree/bindings/mtd/fsl-quadspi.txt   |  31 ++
- drivers/mtd/spi-nor/fsl-quadspi.c             | 444 +++++++++++-------
- drivers/mtd/spi-nor/spi-nor.c                 |   5 +
- 3 files changed, 320 insertions(+), 160 deletions(-)
-
---- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
-+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
-@@ -7,6 +7,7 @@ Required properties:
- 		 or
- 		 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
- 		 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
-+		 "fsl,ls2080a-qspi" followed by "fsl,ls1088a-qspi",
-   - reg : the first contains the register location and length,
-           the second contains the memory mapping address and length
-   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-@@ -39,3 +40,33 @@ qspi0: quadspi@40044000 {
- 		....
- 	};
- };
-+
-+qspi1: quadspi@20c0000 {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	reg = <0x0 0x20c0000 0x0 0x10000>,
-+		<0x0 0x20000000 0x0 0x10000000>;
-+	reg-names = "QuadSPI", "QuadSPI-memory";
-+	interrupts = <0 25 0x4>; /* Level high type */
-+	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-+	clock-names = "qspi_en", "qspi";
-+	status = "okay";
-+
-+	qflash0: s25fs512s@0 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+
-+	qflash1: s25fs512s@1 {
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+		spi-max-frequency = <20000000>;
-+		reg = <1>;
-+		spi-rx-bus-width = <4>;
-+		spi-tx-bus-width = <4>;
-+	};
-+};
---- a/drivers/mtd/spi-nor/fsl-quadspi.c
-+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
-@@ -41,6 +41,7 @@
- #define QUADSPI_QUIRK_TKT253890		(1 << 2)
- /* Controller cannot wake up from wait mode, TKT245618 */
- #define QUADSPI_QUIRK_TKT245618         (1 << 3)
-+#define QUADSPI_ADDR_REMAP		(1 << 4)
- 
- /* The registers */
- #define QUADSPI_MCR			0x00
-@@ -183,7 +184,7 @@
- 
- /* Macros for constructing the LUT register. */
- #define LUT0(ins, pad, opr)						\
--		(((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
-+		(((opr) << OPRND0_SHIFT) | ((pad) << PAD0_SHIFT) | \
- 		((LUT_##ins) << INSTR0_SHIFT))
- 
- #define LUT1(ins, pad, opr)	(LUT0(ins, pad, opr) << OPRND1_SHIFT)
-@@ -193,27 +194,29 @@
- #define QUADSPI_LUT_NUM		64
- 
- /* SEQID -- we can have 16 seqids at most. */
--#define SEQID_READ		0
--#define SEQID_WREN		1
--#define SEQID_WRDI		2
--#define SEQID_RDSR		3
--#define SEQID_SE		4
--#define SEQID_CHIP_ERASE	5
--#define SEQID_PP		6
--#define SEQID_RDID		7
--#define SEQID_WRSR		8
--#define SEQID_RDCR		9
--#define SEQID_EN4B		10
--#define SEQID_BRWR		11
-+/* LUT0 programmed by bootloader, for run-time create entry for LUT seqid 1 */
-+#define SEQID_LUT0_BOOTLOADER	0
-+#define SEQID_LUT1_RUNTIME	1
-+#define SEQID_LUT2_AHBREAD	2
- 
- #define QUADSPI_MIN_IOMAP SZ_4M
- 
-+enum fsl_qspi_ops {
-+	FSL_QSPI_OPS_READ = 0,
-+	FSL_QSPI_OPS_WRITE,
-+	FSL_QSPI_OPS_ERASE,
-+	FSL_QSPI_OPS_READ_REG,
-+	FSL_QSPI_OPS_WRITE_REG,
-+	FSL_QSPI_OPS_WRITE_BUF_REG,
-+};
-+
- enum fsl_qspi_devtype {
- 	FSL_QUADSPI_VYBRID,
- 	FSL_QUADSPI_IMX6SX,
- 	FSL_QUADSPI_IMX7D,
- 	FSL_QUADSPI_IMX6UL,
- 	FSL_QUADSPI_LS1021A,
-+	FSL_QUADSPI_LS2080A,
- };
- 
- struct fsl_qspi_devtype_data {
-@@ -267,6 +270,15 @@ static struct fsl_qspi_devtype_data ls10
- 	.driver_data = 0,
- };
- 
-+static const struct fsl_qspi_devtype_data ls2080a_data = {
-+	.devtype = FSL_QUADSPI_LS2080A,
-+	.rxfifo = 128,
-+	.txfifo = 64,
-+	.ahb_buf_size = 1024,
-+	.driver_data = QUADSPI_QUIRK_TKT253890 | QUADSPI_ADDR_REMAP,
-+};
-+
-+
- #define FSL_QSPI_MAX_CHIP	4
- struct fsl_qspi {
- 	struct spi_nor nor[FSL_QSPI_MAX_CHIP];
-@@ -310,6 +322,22 @@ static inline int needs_wakeup_wait_mode
- }
- 
- /*
-+ * QSPI memory regions split into two parts: a 256MB region that is located
-+ * in the least significant 4GB of the SoC address space and a 3.75GB region
-+ * that is located above the least significant 4GB of the SoC address space.
-+ *
-+ * The 4GB QSPI address space map is shown below.
-+ *
-+ * SoC Address			   QSPI Address
-+ * 0x00_2000_0000-0x00_2FFF_FFFF   0x00_0000_0000-0x00_0FFF_FFFF	First 256MB
-+ * 0x04_1000_0000-0x04_FFFF_FFFF   0x00_1000_0000-0x00_FFFF_FFFF	Last 3.75GB
-+ */
-+static inline int need_address_remap(struct fsl_qspi *q)
-+{
-+	return q->devtype_data->driver_data & QUADSPI_ADDR_REMAP;
-+}
-+
-+/*
-  * R/W functions for big- or little-endian registers:
-  * The qSPI controller's endian is independent of the CPU core's endian.
-  * So far, although the CPU core is little-endian but the qSPI have two
-@@ -368,137 +396,160 @@ static irqreturn_t fsl_qspi_irq_handler(
- 	return IRQ_HANDLED;
- }
- 
--static void fsl_qspi_init_lut(struct fsl_qspi *q)
-+static inline s8 pad_count(s8 pad_val)
- {
-+	s8 count = -1;
-+
-+	if (!pad_val)
-+		return 0;
-+
-+	while (pad_val) {
-+		pad_val >>= 1;
-+		count++;
-+	}
-+	return count;
-+}
-+
-+/*
-+ * Prepare LUT entry for the input cmd.
-+ * Protocol info is present in instance of struct spi_nor, using which fields
-+ * like cmd, data, addrlen along with pad info etc can be parsed.
-+ */
-+static void fsl_qspi_prepare_lut(struct spi_nor *nor,
-+				 enum fsl_qspi_ops ops, u8 cmd)
-+{
-+	struct fsl_qspi *q = nor->priv;
- 	void __iomem *base = q->iobase;
- 	int rxfifo = q->devtype_data->rxfifo;
-+	int txfifo = q->devtype_data->txfifo;
- 	u32 lut_base;
--	int i;
-+	u8 cmd_pad, addr_pad, data_pad, dummy_pad;
-+	enum spi_nor_protocol protocol = 0;
-+	u8 addrlen = 0;
-+	u8 read_dm, opcode;
-+	int stop_lut;
-+
-+	read_dm = opcode = cmd_pad = addr_pad = data_pad = dummy_pad = 0;
-+
-+	switch (ops) {
-+	case FSL_QSPI_OPS_READ_REG:
-+	case FSL_QSPI_OPS_WRITE_REG:
-+	case FSL_QSPI_OPS_WRITE_BUF_REG:
-+		opcode = cmd;
-+		protocol = nor->reg_proto;
-+		break;
-+	case FSL_QSPI_OPS_READ:
-+		opcode = cmd;
-+		read_dm = nor->read_dummy;
-+		protocol = nor->read_proto;
-+		break;
-+	case FSL_QSPI_OPS_WRITE:
-+		opcode = cmd;
-+		protocol = nor->write_proto;
-+		break;
-+	case FSL_QSPI_OPS_ERASE:
-+		opcode = cmd;
-+		break;
-+	default:
-+		dev_err(q->dev, "Unsupported operation 0x%.2x\n", ops);
-+		return;
-+	}
-+
-+	if (protocol) {
-+		cmd_pad = spi_nor_get_protocol_inst_nbits(protocol);
-+		addr_pad = spi_nor_get_protocol_addr_nbits(protocol);
-+		data_pad = spi_nor_get_protocol_data_nbits(protocol);
-+	}
-+
-+	dummy_pad = data_pad;
- 
--	struct spi_nor *nor = &q->nor[0];
--	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
--	u8 read_op = nor->read_opcode;
--	u8 read_dm = nor->read_dummy;
-+	dev_dbg(q->dev, "ops:%x opcode:%x pad[cmd:%d, addr:%d, data:%d]\n",
-+			ops, opcode, cmd_pad, addr_pad, data_pad);
- 
- 	fsl_qspi_unlock_lut(q);
- 
--	/* Clear all the LUT table */
--	for (i = 0; i < QUADSPI_LUT_NUM; i++)
--		qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
--
--	/* Read */
--	lut_base = SEQID_READ * 4;
--
--	qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
--			base + QUADSPI_LUT(lut_base));
--	qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
--		    LUT1(FSL_READ, PAD4, rxfifo),
--			base + QUADSPI_LUT(lut_base + 1));
--
--	/* Write enable */
--	lut_base = SEQID_WREN * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
--			base + QUADSPI_LUT(lut_base));
--
--	/* Page Program */
--	lut_base = SEQID_PP * 4;
--
--	qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
--		    LUT1(ADDR, PAD1, addrlen),
--			base + QUADSPI_LUT(lut_base));
--	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
--			base + QUADSPI_LUT(lut_base + 1));
--
--	/* Read Status */
--	lut_base = SEQID_RDSR * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
--			LUT1(FSL_READ, PAD1, 0x1),
--			base + QUADSPI_LUT(lut_base));
--
--	/* Erase a sector */
--	lut_base = SEQID_SE * 4;
--
--	qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
--		    LUT1(ADDR, PAD1, addrlen),
--			base + QUADSPI_LUT(lut_base));
--
--	/* Erase the whole chip */
--	lut_base = SEQID_CHIP_ERASE * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
--			base + QUADSPI_LUT(lut_base));
--
--	/* READ ID */
--	lut_base = SEQID_RDID * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
--			LUT1(FSL_READ, PAD1, 0x8),
--			base + QUADSPI_LUT(lut_base));
--
--	/* Write Register */
--	lut_base = SEQID_WRSR * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
--			LUT1(FSL_WRITE, PAD1, 0x2),
--			base + QUADSPI_LUT(lut_base));
--
--	/* Read Configuration Register */
--	lut_base = SEQID_RDCR * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
--			LUT1(FSL_READ, PAD1, 0x1),
--			base + QUADSPI_LUT(lut_base));
--
--	/* Write disable */
--	lut_base = SEQID_WRDI * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
--			base + QUADSPI_LUT(lut_base));
--
--	/* Enter 4 Byte Mode (Micron) */
--	lut_base = SEQID_EN4B * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
--			base + QUADSPI_LUT(lut_base));
--
--	/* Enter 4 Byte Mode (Spansion) */
--	lut_base = SEQID_BRWR * 4;
--	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
--			base + QUADSPI_LUT(lut_base));
-+	/* Dynamic LUT */
-+	lut_base = SEQID_LUT1_RUNTIME * 4;
-+	if (ops == FSL_QSPI_OPS_READ)
-+		lut_base = SEQID_LUT2_AHBREAD * 4;
-+
-+	/* default, STOP instruction to be programmed in (lut_base + 1) reg */
-+	stop_lut = 1;
-+	switch (ops) {
-+	case FSL_QSPI_OPS_READ_REG:
-+		qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
-+			  LUT1(FSL_READ, pad_count(data_pad), rxfifo),
-+			  base + QUADSPI_LUT(lut_base));
-+		break;
-+	case FSL_QSPI_OPS_WRITE_REG:
-+		qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode),
-+			  base + QUADSPI_LUT(lut_base));
-+		break;
-+	case FSL_QSPI_OPS_WRITE_BUF_REG:
-+		qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
-+			  LUT1(FSL_WRITE, pad_count(data_pad), txfifo),
-+			  base + QUADSPI_LUT(lut_base));
-+		break;
-+	case FSL_QSPI_OPS_READ:
-+	case FSL_QSPI_OPS_WRITE:
-+	case FSL_QSPI_OPS_ERASE:
-+		/* Common for Read, Write and Erase ops. */
-+
-+		addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
-+
-+		qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
-+				LUT1(ADDR, pad_count(addr_pad), addrlen),
-+				base + QUADSPI_LUT(lut_base));
-+		/*
-+		 * For Erase ops - Data and Dummy not required.
-+		 * For Write ops - Dummy not required.
-+		 */
- 
--	fsl_qspi_lock_lut(q);
--}
-+		if (ops == FSL_QSPI_OPS_READ) {
- 
--/* Get the SEQID for the command */
--static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
--{
--	switch (cmd) {
--	case SPINOR_OP_READ_1_1_4:
--	case SPINOR_OP_READ_1_1_4_4B:
--		return SEQID_READ;
--	case SPINOR_OP_WREN:
--		return SEQID_WREN;
--	case SPINOR_OP_WRDI:
--		return SEQID_WRDI;
--	case SPINOR_OP_RDSR:
--		return SEQID_RDSR;
--	case SPINOR_OP_SE:
--		return SEQID_SE;
--	case SPINOR_OP_CHIP_ERASE:
--		return SEQID_CHIP_ERASE;
--	case SPINOR_OP_PP:
--		return SEQID_PP;
--	case SPINOR_OP_RDID:
--		return SEQID_RDID;
--	case SPINOR_OP_WRSR:
--		return SEQID_WRSR;
--	case SPINOR_OP_RDCR:
--		return SEQID_RDCR;
--	case SPINOR_OP_EN4B:
--		return SEQID_EN4B;
--	case SPINOR_OP_BRWR:
--		return SEQID_BRWR;
-+			/*
-+			 * For cmds SPINOR_OP_READ and SPINOR_OP_READ_4B value
-+			 * of dummy cycles are 0.
-+			 */
-+			if (read_dm)
-+				qspi_writel(q,
-+					    LUT0(DUMMY, pad_count(dummy_pad),
-+					    read_dm) |
-+					    LUT1(FSL_READ, pad_count(data_pad),
-+					    rxfifo),
-+					    base + QUADSPI_LUT(lut_base + 1));
-+			else
-+				qspi_writel(q,
-+					    LUT0(FSL_READ, pad_count(data_pad),
-+					    rxfifo),
-+					    base + QUADSPI_LUT(lut_base + 1));
-+
-+			stop_lut = 2;
-+
-+			/* TODO Add condition to check if READ is IP/AHB. */
-+
-+			/* For AHB read, add seqid in BFGENCR register. */
-+			qspi_writel(q,
-+				    SEQID_LUT2_AHBREAD <<
-+				    QUADSPI_BFGENCR_SEQID_SHIFT,
-+				    q->iobase + QUADSPI_BFGENCR);
-+		}
-+
-+		if (ops == FSL_QSPI_OPS_WRITE) {
-+			qspi_writel(q, LUT0(FSL_WRITE, pad_count(data_pad), 0),
-+					base + QUADSPI_LUT(lut_base + 1));
-+			stop_lut = 2;
-+		}
-+		break;
- 	default:
--		if (cmd == q->nor[0].erase_opcode)
--			return SEQID_SE;
--		dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
-+		dev_err(q->dev, "Unsupported operation 0x%.2x\n", ops);
- 		break;
- 	}
--	return -EINVAL;
-+
-+	/* prepare LUT for STOP instruction. */
-+	qspi_writel(q, 0, base +  QUADSPI_LUT(lut_base + stop_lut));
-+
-+	fsl_qspi_lock_lut(q);
- }
- 
- static int
-@@ -508,6 +559,10 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
- 	int seqid;
- 	u32 reg, reg2;
- 	int err;
-+	u32 memmap_phyadd = q->memmap_phy;
-+
-+	if (need_address_remap(q))
-+		memmap_phyadd = 0;
- 
- 	init_completion(&q->c);
- 	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
-@@ -516,7 +571,7 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
- 	/* save the reg */
- 	reg = qspi_readl(q, base + QUADSPI_MCR);
- 
--	qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
-+	qspi_writel(q, memmap_phyadd + q->chip_base_addr + addr,
- 			base + QUADSPI_SFAR);
- 	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
- 			base + QUADSPI_RBCT);
-@@ -533,7 +588,7 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
- 	} while (1);
- 
- 	/* trigger the LUT now */
--	seqid = fsl_qspi_get_seqid(q, cmd);
-+	seqid = SEQID_LUT1_RUNTIME;
- 	qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
- 			base + QUADSPI_IPCR);
- 
-@@ -609,6 +664,7 @@ static ssize_t fsl_qspi_nor_write(struct
- {
- 	int ret, i, j;
- 	u32 tmp;
-+	u8 byts;
- 
- 	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
- 		q->chip_base_addr, to, count);
-@@ -618,10 +674,18 @@ static ssize_t fsl_qspi_nor_write(struct
- 	qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
- 
- 	/* fill the TX data to the FIFO */
-+	byts = count;
- 	for (j = 0, i = ((count + 3) / 4); j < i; j++) {
--		tmp = fsl_qspi_endian_xchg(q, *txbuf);
-+		if(byts >= 4)
-+			tmp = fsl_qspi_endian_xchg(q, *txbuf);
-+		else {
-+			memcpy(&tmp, txbuf, byts);
-+			tmp = fsl_qspi_endian_xchg(q, tmp);
-+		}
-+
- 		qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
- 		txbuf++;
-+		byts -= 4;
- 	}
- 
- 	/* fill the TXFIFO upto 16 bytes for i.MX7d */
-@@ -642,11 +706,15 @@ static void fsl_qspi_set_map_addr(struct
- {
- 	int nor_size = q->nor_size;
- 	void __iomem *base = q->iobase;
-+	u32 memmap_phyadd = q->memmap_phy;
-+
-+	if (need_address_remap(q))
-+		memmap_phyadd = 0;
- 
--	qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
--	qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
--	qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
--	qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
-+	qspi_writel(q, nor_size + memmap_phyadd, base + QUADSPI_SFA1AD);
-+	qspi_writel(q, nor_size * 2 + memmap_phyadd, base + QUADSPI_SFA2AD);
-+	qspi_writel(q, nor_size * 3 + memmap_phyadd, base + QUADSPI_SFB1AD);
-+	qspi_writel(q, nor_size * 4 + memmap_phyadd, base + QUADSPI_SFB2AD);
- }
- 
- /*
-@@ -662,7 +730,7 @@ static void fsl_qspi_set_map_addr(struct
-  * causes the controller to clear the buffer, and use the sequence pointed
-  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
-  */
--static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
-+static void fsl_qspi_init_ahb_read(struct fsl_qspi *q)
- {
- 	void __iomem *base = q->iobase;
- 	int seqid;
-@@ -685,8 +753,8 @@ static void fsl_qspi_init_abh_read(struc
- 	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
- 	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
- 
--	/* Set the default lut sequence for AHB Read. */
--	seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
-+	/* Set dynamic LUT entry as lut sequence for AHB Read . */
-+	seqid = SEQID_LUT2_AHBREAD;
- 	qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
- 		q->iobase + QUADSPI_BFGENCR);
- }
-@@ -729,7 +797,6 @@ static int fsl_qspi_nor_setup(struct fsl
- 	void __iomem *base = q->iobase;
- 	u32 reg;
- 	int ret;
--
- 	/* disable and unprepare clock to avoid glitch pass to controller */
- 	fsl_qspi_clk_disable_unprep(q);
- 
-@@ -747,9 +814,6 @@ static int fsl_qspi_nor_setup(struct fsl
- 		base + QUADSPI_MCR);
- 	udelay(1);
- 
--	/* Init the LUT table. */
--	fsl_qspi_init_lut(q);
--
- 	/* Disable the module */
- 	qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
- 			base + QUADSPI_MCR);
-@@ -770,6 +834,9 @@ static int fsl_qspi_nor_setup(struct fsl
- 	/* enable the interrupt */
- 	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
- 
-+	/* Init for AHB read */
-+	fsl_qspi_init_ahb_read(q);
-+
- 	return 0;
- }
- 
-@@ -792,12 +859,6 @@ static int fsl_qspi_nor_setup_last(struc
- 	if (ret)
- 		return ret;
- 
--	/* Init the LUT table again. */
--	fsl_qspi_init_lut(q);
--
--	/* Init for AHB read */
--	fsl_qspi_init_abh_read(q);
--
- 	return 0;
- }
- 
-@@ -807,6 +868,7 @@ static const struct of_device_id fsl_qsp
- 	{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
- 	{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
- 	{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
-+	{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
- 	{ /* sentinel */ }
- };
- MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-@@ -821,6 +883,7 @@ static int fsl_qspi_read_reg(struct spi_
- 	int ret;
- 	struct fsl_qspi *q = nor->priv;
- 
-+	fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ_REG, opcode);
- 	ret = fsl_qspi_runcmd(q, opcode, 0, len);
- 	if (ret)
- 		return ret;
-@@ -835,6 +898,8 @@ static int fsl_qspi_write_reg(struct spi
- 	int ret;
- 
- 	if (!buf) {
-+		/* Prepare LUT for WRITE_REG cmd with input BUF as NULL. */
-+		fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE_REG, opcode);
- 		ret = fsl_qspi_runcmd(q, opcode, 0, 1);
- 		if (ret)
- 			return ret;
-@@ -843,6 +908,8 @@ static int fsl_qspi_write_reg(struct spi
- 			fsl_qspi_invalid(q);
- 
- 	} else if (len > 0) {
-+		/* Prepare LUT for WRITE_REG cmd with input BUF non-NULL. */
-+		fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE_BUF_REG, opcode);
- 		ret = fsl_qspi_nor_write(q, nor, opcode, 0,
- 					(u32 *)buf, len);
- 		if (ret > 0)
-@@ -859,8 +926,11 @@ static ssize_t fsl_qspi_write(struct spi
- 			      size_t len, const u_char *buf)
- {
- 	struct fsl_qspi *q = nor->priv;
--	ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
--					 (u32 *)buf, len);
-+	ssize_t ret;
-+
-+	fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE, nor->program_opcode);
-+	ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
-+				 (u32 *)buf, len);
- 
- 	/* invalid the data in the AHB buffer. */
- 	fsl_qspi_invalid(q);
-@@ -873,6 +943,8 @@ static ssize_t fsl_qspi_read(struct spi_
- 	struct fsl_qspi *q = nor->priv;
- 	u8 cmd = nor->read_opcode;
- 
-+	fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ, nor->read_opcode);
-+
- 	/* if necessary,ioremap buffer before AHB read, */
- 	if (!q->ahb_addr) {
- 		q->memmap_offs = q->chip_base_addr + from;
-@@ -907,8 +979,9 @@ static ssize_t fsl_qspi_read(struct spi_
- 		len);
- 
- 	/* Read out the data directly from the AHB buffer.*/
--	memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
--		len);
-+	memcpy_fromio(buf,
-+		      q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
-+		      len);
- 
- 	return len;
- }
-@@ -921,6 +994,7 @@ static int fsl_qspi_erase(struct spi_nor
- 	dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
- 		nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
- 
-+	fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_ERASE, nor->erase_opcode);
- 	ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
- 	if (ret)
- 		return ret;
-@@ -958,17 +1032,14 @@ static void fsl_qspi_unprep(struct spi_n
- 
- static int fsl_qspi_probe(struct platform_device *pdev)
- {
--	const struct spi_nor_hwcaps hwcaps = {
--		.mask = SNOR_HWCAPS_READ_1_1_4 |
--			SNOR_HWCAPS_PP,
--	};
-+	struct spi_nor_hwcaps hwcaps;
- 	struct device_node *np = pdev->dev.of_node;
- 	struct device *dev = &pdev->dev;
- 	struct fsl_qspi *q;
- 	struct resource *res;
- 	struct spi_nor *nor;
- 	struct mtd_info *mtd;
--	int ret, i = 0;
-+	int ret, i = 0, value;
- 
- 	q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
- 	if (!q)
-@@ -1041,6 +1112,10 @@ static int fsl_qspi_probe(struct platfor
- 
- 	/* iterate the subnodes. */
- 	for_each_available_child_of_node(dev->of_node, np) {
-+		/* Reset hwcaps mask to minimal caps for the slave node. */
-+		hwcaps.mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP;
-+		value = 0;
-+
- 		/* skip the holes */
- 		if (!q->has_second_chip)
- 			i *= 2;
-@@ -1070,6 +1145,51 @@ static int fsl_qspi_probe(struct platfor
- 		/* set the chip address for READID */
- 		fsl_qspi_set_base_addr(q, nor);
- 
-+		/*
-+		 * If spi-rx-bus-width and spi-tx-bus-width not defined assign
-+		 * default hardware capabilities SNOR_HWCAPS_READ_1_1_4 and
-+		 * SNOR_HWCAPS_PP supported by the Quad-SPI controller.
-+		 */
-+		if (!of_property_read_u32(np, "spi-rx-bus-width", &value)) {
-+			switch (value) {
-+			case 1:
-+				hwcaps.mask |= SNOR_HWCAPS_READ |
-+					       SNOR_HWCAPS_READ_FAST;
-+				break;
-+			case 2:
-+				hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2 |
-+					       SNOR_HWCAPS_READ_1_2_2;
-+				break;
-+			case 4:
-+				hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4 |
-+					       SNOR_HWCAPS_READ_1_4_4;
-+				break;
-+			default:
-+				dev_err(dev,
-+					"spi-rx-bus-width %d not supported\n",
-+					value);
-+				break;
-+			}
-+		} else
-+			hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
-+
-+		if (!of_property_read_u32(np, "spi-tx-bus-width", &value)) {
-+			switch (value) {
-+			case 1:
-+				hwcaps.mask |= SNOR_HWCAPS_PP;
-+				break;
-+			case 4:
-+				hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4 |
-+					       SNOR_HWCAPS_PP_1_4_4;
-+				break;
-+			default:
-+				dev_err(dev,
-+					"spi-tx-bus-width %d not supported\n",
-+					value);
-+				break;
-+			}
-+		}
-+
- 		ret = spi_nor_scan(nor, NULL, &hwcaps);
- 		if (ret)
- 			goto mutex_failed;
-@@ -1098,6 +1218,8 @@ static int fsl_qspi_probe(struct platfor
- 		if (nor->page_size > q->devtype_data->txfifo)
- 			nor->page_size = q->devtype_data->txfifo;
- 
-+		/*required for memory mapped AHB read*/
-+		fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ, nor->read_opcode);
- 		i++;
- 	}
- 
-@@ -1106,6 +1228,8 @@ static int fsl_qspi_probe(struct platfor
- 	if (ret)
- 		goto last_init_failed;
- 
-+
-+
- 	fsl_qspi_clk_disable_unprep(q);
- 	return 0;
- 
---- a/drivers/mtd/spi-nor/spi-nor.c
-+++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -1146,6 +1146,11 @@ static const struct flash_info spi_nor_i
- 	{ "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
- 	{ "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
- 	{ "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
-+	{
-+		"w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
-+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
-+	},
- 	{ "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
- 	{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
- 	{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
diff --git a/target/linux/layerscape/patches-4.14/819-sdhc-support-layerscape.patch b/target/linux/layerscape/patches-4.14/819-sdhc-support-layerscape.patch
deleted file mode 100644
index 986db4c22..000000000
--- a/target/linux/layerscape/patches-4.14/819-sdhc-support-layerscape.patch
+++ /dev/null
@@ -1,147 +0,0 @@
-From f901f791d07deaeba6310ac070769575a0bb790a Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:27:54 +0800
-Subject: [PATCH 36/40] sdhc: support layerscape
-This is an integrated patch of sdhc for layerscape
-
-Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/mmc/host/sdhci-of-esdhc.c | 85 +++++++++++++++++++++----------
- 1 file changed, 57 insertions(+), 28 deletions(-)
-
---- a/drivers/mmc/host/sdhci-of-esdhc.c
-+++ b/drivers/mmc/host/sdhci-of-esdhc.c
-@@ -30,11 +30,56 @@
- #define VENDOR_V_22	0x12
- #define VENDOR_V_23	0x13
- 
-+#define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)
-+
-+struct esdhc_clk_fixup {
-+	const unsigned int sd_dflt_max_clk;
-+	const unsigned int max_clk[MMC_TIMING_NUM];
-+};
-+
-+static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
-+	.sd_dflt_max_clk = 25000000,
-+	.max_clk[MMC_TIMING_MMC_HS] = 46500000,
-+	.max_clk[MMC_TIMING_SD_HS] = 46500000,
-+};
-+
-+static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
-+	.sd_dflt_max_clk = 25000000,
-+	.max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
-+	.max_clk[MMC_TIMING_MMC_HS200] = 167000000,
-+};
-+
-+static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
-+	.sd_dflt_max_clk = 25000000,
-+	.max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
-+	.max_clk[MMC_TIMING_MMC_HS200] = 125000000,
-+};
-+
-+static const struct esdhc_clk_fixup p1010_esdhc_clk = {
-+	.sd_dflt_max_clk = 20000000,
-+	.max_clk[MMC_TIMING_LEGACY] = 20000000,
-+	.max_clk[MMC_TIMING_MMC_HS] = 42000000,
-+	.max_clk[MMC_TIMING_SD_HS] = 40000000,
-+};
-+
-+static const struct of_device_id sdhci_esdhc_of_match[] = {
-+	{ .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
-+	{ .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
-+	{ .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
-+	{ .compatible = "fsl,p1010-esdhc",   .data = &p1010_esdhc_clk},
-+	{ .compatible = "fsl,mpc8379-esdhc" },
-+	{ .compatible = "fsl,mpc8536-esdhc" },
-+	{ .compatible = "fsl,esdhc" },
-+	{ }
-+};
-+MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
-+
- struct sdhci_esdhc {
- 	u8 vendor_ver;
- 	u8 spec_ver;
- 	bool quirk_incorrect_hostver;
- 	unsigned int peripheral_clock;
-+	const struct esdhc_clk_fixup *clk_fixup;
- };
- 
- /**
-@@ -498,6 +543,7 @@ static void esdhc_of_set_clock(struct sd
- 	int pre_div = 1;
- 	int div = 1;
- 	ktime_t timeout;
-+	long fixup = 0;
- 	u32 temp;
- 
- 	host->mmc->actual_clock = 0;
-@@ -511,27 +557,14 @@ static void esdhc_of_set_clock(struct sd
- 	if (esdhc->vendor_ver < VENDOR_V_23)
- 		pre_div = 2;
- 
--	/*
--	 * Limit SD clock to 167MHz for ls1046a according to its datasheet
--	 */
--	if (clock > 167000000 &&
--	    of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc"))
--		clock = 167000000;
-+	if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
-+		esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
-+		fixup = esdhc->clk_fixup->sd_dflt_max_clk;
-+	else if (esdhc->clk_fixup)
-+		fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
- 
--	/*
--	 * Limit SD clock to 125MHz for ls1012a according to its datasheet
--	 */
--	if (clock > 125000000 &&
--	    of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc"))
--		clock = 125000000;
--
--	/* Workaround to reduce the clock frequency for p1010 esdhc */
--	if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
--		if (clock > 20000000)
--			clock -= 5000000;
--		if (clock > 40000000)
--			clock -= 5000000;
--	}
-+	if (fixup && clock > fixup)
-+		clock = fixup;
- 
- 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
- 	temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
-@@ -789,6 +822,7 @@ static struct soc_device_attribute soc_i
- 
- static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
- {
-+	const struct of_device_id *match;
- 	struct sdhci_pltfm_host *pltfm_host;
- 	struct sdhci_esdhc *esdhc;
- 	struct device_node *np;
-@@ -808,6 +842,9 @@ static void esdhc_init(struct platform_d
- 	else
- 		esdhc->quirk_incorrect_hostver = false;
- 
-+	match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
-+	if (match)
-+		esdhc->clk_fixup = match->data;
- 	np = pdev->dev.of_node;
- 	clk = of_clk_get(np, 0);
- 	if (!IS_ERR(clk)) {
-@@ -907,14 +944,6 @@ static int sdhci_esdhc_probe(struct plat
- 	return ret;
- }
- 
--static const struct of_device_id sdhci_esdhc_of_match[] = {
--	{ .compatible = "fsl,mpc8379-esdhc" },
--	{ .compatible = "fsl,mpc8536-esdhc" },
--	{ .compatible = "fsl,esdhc" },
--	{ }
--};
--MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
--
- static struct platform_driver sdhci_esdhc_driver = {
- 	.driver = {
- 		.name = "sdhci-esdhc",
diff --git a/target/linux/layerscape/patches-4.14/820-sec-support-layerscape.patch b/target/linux/layerscape/patches-4.14/820-sec-support-layerscape.patch
deleted file mode 100644
index 9cec9dc70..000000000
--- a/target/linux/layerscape/patches-4.14/820-sec-support-layerscape.patch
+++ /dev/null
@@ -1,13093 +0,0 @@
-From 936d5f485f2ff837cdd7d49839771bd3367e8b92 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:28:03 +0800
-Subject: [PATCH 37/40] sec: support layerscape
-This is an integrated patch of sec for layerscape
-
-Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
-Signed-off-by: Cristian Stoica <cristian.stoica@nxp.com>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
-Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
-Signed-off-by: Horia Geantă horia.geanta@nxp.com
-Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
-Signed-off-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- crypto/Kconfig                      |   20 +
- crypto/Makefile                     |    1 +
- crypto/tcrypt.c                     |   27 +-
- crypto/testmgr.c                    |  244 ++
- crypto/testmgr.h                    |  219 ++
- crypto/tls.c                        |  607 +++
- drivers/crypto/Makefile             |    2 +-
- drivers/crypto/caam/Kconfig         |   57 +-
- drivers/crypto/caam/Makefile        |   10 +-
- drivers/crypto/caam/caamalg.c       |  131 +-
- drivers/crypto/caam/caamalg_desc.c  |  761 +++-
- drivers/crypto/caam/caamalg_desc.h  |   47 +-
- drivers/crypto/caam/caamalg_qi.c    |  927 ++++-
- drivers/crypto/caam/caamalg_qi2.c   | 5691 +++++++++++++++++++++++++++
- drivers/crypto/caam/caamalg_qi2.h   |  274 ++
- drivers/crypto/caam/caamhash.c      |  132 +-
- drivers/crypto/caam/caamhash_desc.c |  108 +
- drivers/crypto/caam/caamhash_desc.h |   49 +
- drivers/crypto/caam/compat.h        |    2 +
- drivers/crypto/caam/ctrl.c          |   23 +-
- drivers/crypto/caam/desc.h          |   62 +-
- drivers/crypto/caam/desc_constr.h   |   52 +-
- drivers/crypto/caam/dpseci.c        |  865 ++++
- drivers/crypto/caam/dpseci.h        |  433 ++
- drivers/crypto/caam/dpseci_cmd.h    |  287 ++
- drivers/crypto/caam/error.c         |   75 +-
- drivers/crypto/caam/error.h         |    6 +-
- drivers/crypto/caam/intern.h        |    1 +
- drivers/crypto/caam/jr.c            |   42 +
- drivers/crypto/caam/jr.h            |    2 +
- drivers/crypto/caam/key_gen.c       |   30 -
- drivers/crypto/caam/key_gen.h       |   30 +
- drivers/crypto/caam/qi.c            |   85 +-
- drivers/crypto/caam/qi.h            |    2 +-
- drivers/crypto/caam/regs.h          |    2 +
- drivers/crypto/caam/sg_sw_qm.h      |   46 +-
- drivers/crypto/talitos.c            |    8 +
- 37 files changed, 11006 insertions(+), 354 deletions(-)
- create mode 100644 crypto/tls.c
- create mode 100644 drivers/crypto/caam/caamalg_qi2.c
- create mode 100644 drivers/crypto/caam/caamalg_qi2.h
- create mode 100644 drivers/crypto/caam/caamhash_desc.c
- create mode 100644 drivers/crypto/caam/caamhash_desc.h
- create mode 100644 drivers/crypto/caam/dpseci.c
- create mode 100644 drivers/crypto/caam/dpseci.h
- create mode 100644 drivers/crypto/caam/dpseci_cmd.h
-
---- a/crypto/Kconfig
-+++ b/crypto/Kconfig
-@@ -312,6 +312,26 @@ config CRYPTO_ECHAINIV
- 	  a sequence number xored with a salt.  This is the default
- 	  algorithm for CBC.
- 
-+config CRYPTO_TLS
-+	tristate "TLS support"
-+	select CRYPTO_AEAD
-+	select CRYPTO_BLKCIPHER
-+	select CRYPTO_MANAGER
-+	select CRYPTO_HASH
-+	select CRYPTO_NULL
-+	select CRYPTO_AUTHENC
-+	help
-+	  Support for TLS 1.0 record encryption and decryption
-+
-+	  This module adds support for encryption/decryption of TLS 1.0 frames
-+	  using blockcipher algorithms. The name of the resulting algorithm is
-+	  "tls10(hmac(<digest>),cbc(<cipher>))". By default, the generic base
-+	  algorithms are used (e.g. aes-generic, sha1-generic), but hardware
-+	  accelerated versions will be used automatically if available.
-+
-+	  User-space applications (OpenSSL, GnuTLS) can offload TLS 1.0
-+	  operations through AF_ALG or cryptodev interfaces
-+
- comment "Block modes"
- 
- config CRYPTO_CBC
---- a/crypto/Makefile
-+++ b/crypto/Makefile
-@@ -118,6 +118,7 @@ obj-$(CONFIG_CRYPTO_CRC32C) += crc32c_ge
- obj-$(CONFIG_CRYPTO_CRC32) += crc32_generic.o
- obj-$(CONFIG_CRYPTO_CRCT10DIF) += crct10dif_common.o crct10dif_generic.o
- obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o
-+obj-$(CONFIG_CRYPTO_TLS) += tls.o
- obj-$(CONFIG_CRYPTO_LZO) += lzo.o
- obj-$(CONFIG_CRYPTO_LZ4) += lz4.o
- obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o
---- a/crypto/tcrypt.c
-+++ b/crypto/tcrypt.c
-@@ -76,7 +76,7 @@ static char *check[] = {
- 	"khazad", "wp512", "wp384", "wp256", "tnepres", "xeta",  "fcrypt",
- 	"camellia", "seed", "salsa20", "rmd128", "rmd160", "rmd256", "rmd320",
- 	"lzo", "cts", "zlib", "sha3-224", "sha3-256", "sha3-384", "sha3-512",
--	NULL
-+	"rsa", NULL
- };
- 
- struct tcrypt_result {
-@@ -355,11 +355,13 @@ static void test_aead_speed(const char *
- 					       iv);
- 			aead_request_set_ad(req, aad_size);
- 
--			if (secs)
-+			if (secs) {
- 				ret = test_aead_jiffies(req, enc, *b_size,
- 							secs);
--			else
-+				cond_resched();
-+			} else {
- 				ret = test_aead_cycles(req, enc, *b_size);
-+			}
- 
- 			if (ret) {
- 				pr_err("%s() failed return code=%d\n", e, ret);
-@@ -736,12 +738,14 @@ static void test_ahash_speed_common(cons
- 
- 		ahash_request_set_crypt(req, sg, output, speed[i].plen);
- 
--		if (secs)
-+		if (secs) {
- 			ret = test_ahash_jiffies(req, speed[i].blen,
- 						 speed[i].plen, output, secs);
--		else
-+			cond_resched();
-+		} else {
- 			ret = test_ahash_cycles(req, speed[i].blen,
- 						speed[i].plen, output);
-+		}
- 
- 		if (ret) {
- 			pr_err("hashing failed ret=%d\n", ret);
-@@ -959,12 +963,14 @@ static void test_skcipher_speed(const ch
- 
- 			skcipher_request_set_crypt(req, sg, sg, *b_size, iv);
- 
--			if (secs)
-+			if (secs) {
- 				ret = test_acipher_jiffies(req, enc,
- 							   *b_size, secs);
--			else
-+				cond_resched();
-+			} else {
- 				ret = test_acipher_cycles(req, enc,
- 							  *b_size);
-+			}
- 
- 			if (ret) {
- 				pr_err("%s() failed flags=%x\n", e,
-@@ -1336,6 +1342,10 @@ static int do_test(const char *alg, u32
- 		ret += tcrypt_test("hmac(sha3-512)");
- 		break;
- 
-+	case 115:
-+		ret += tcrypt_test("rsa");
-+		break;
-+
- 	case 150:
- 		ret += tcrypt_test("ansi_cprng");
- 		break;
-@@ -1397,6 +1407,9 @@ static int do_test(const char *alg, u32
- 	case 190:
- 		ret += tcrypt_test("authenc(hmac(sha512),cbc(des3_ede))");
- 		break;
-+	case 191:
-+		ret += tcrypt_test("tls10(hmac(sha1),cbc(aes))");
-+		break;
- 	case 200:
- 		test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0,
- 				speed_template_16_24_32);
---- a/crypto/testmgr.c
-+++ b/crypto/testmgr.c
-@@ -117,6 +117,13 @@ struct drbg_test_suite {
- 	unsigned int count;
- };
- 
-+struct tls_test_suite {
-+	struct {
-+		struct tls_testvec *vecs;
-+		unsigned int count;
-+	} enc, dec;
-+};
-+
- struct akcipher_test_suite {
- 	const struct akcipher_testvec *vecs;
- 	unsigned int count;
-@@ -140,6 +147,7 @@ struct alg_test_desc {
- 		struct hash_test_suite hash;
- 		struct cprng_test_suite cprng;
- 		struct drbg_test_suite drbg;
-+		struct tls_test_suite tls;
- 		struct akcipher_test_suite akcipher;
- 		struct kpp_test_suite kpp;
- 	} suite;
-@@ -991,6 +999,233 @@ static int test_aead(struct crypto_aead
- 	return 0;
- }
- 
-+static int __test_tls(struct crypto_aead *tfm, int enc,
-+		      struct tls_testvec *template, unsigned int tcount,
-+		      const bool diff_dst)
-+{
-+	const char *algo = crypto_tfm_alg_driver_name(crypto_aead_tfm(tfm));
-+	unsigned int i, k, authsize;
-+	char *q;
-+	struct aead_request *req;
-+	struct scatterlist *sg;
-+	struct scatterlist *sgout;
-+	const char *e, *d;
-+	struct tcrypt_result result;
-+	void *input;
-+	void *output;
-+	void *assoc;
-+	char *iv;
-+	char *key;
-+	char *xbuf[XBUFSIZE];
-+	char *xoutbuf[XBUFSIZE];
-+	char *axbuf[XBUFSIZE];
-+	int ret = -ENOMEM;
-+
-+	if (testmgr_alloc_buf(xbuf))
-+		goto out_noxbuf;
-+
-+	if (diff_dst && testmgr_alloc_buf(xoutbuf))
-+		goto out_nooutbuf;
-+
-+	if (testmgr_alloc_buf(axbuf))
-+		goto out_noaxbuf;
-+
-+	iv = kzalloc(MAX_IVLEN, GFP_KERNEL);
-+	if (!iv)
-+		goto out_noiv;
-+
-+	key = kzalloc(MAX_KEYLEN, GFP_KERNEL);
-+	if (!key)
-+		goto out_nokey;
-+
-+	sg = kmalloc(sizeof(*sg) * 8 * (diff_dst ? 2 : 1), GFP_KERNEL);
-+	if (!sg)
-+		goto out_nosg;
-+
-+	sgout = sg + 8;
-+
-+	d = diff_dst ? "-ddst" : "";
-+	e = enc ? "encryption" : "decryption";
-+
-+	init_completion(&result.completion);
-+
-+	req = aead_request_alloc(tfm, GFP_KERNEL);
-+	if (!req) {
-+		pr_err("alg: tls%s: Failed to allocate request for %s\n",
-+		       d, algo);
-+		goto out;
-+	}
-+
-+	aead_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
-+				  tcrypt_complete, &result);
-+
-+	for (i = 0; i < tcount; i++) {
-+		input = xbuf[0];
-+		assoc = axbuf[0];
-+
-+		ret = -EINVAL;
-+		if (WARN_ON(template[i].ilen > PAGE_SIZE ||
-+			    template[i].alen > PAGE_SIZE))
-+			goto out;
-+
-+		memcpy(assoc, template[i].assoc, template[i].alen);
-+		memcpy(input, template[i].input, template[i].ilen);
-+
-+		if (template[i].iv)
-+			memcpy(iv, template[i].iv, MAX_IVLEN);
-+		else
-+			memset(iv, 0, MAX_IVLEN);
-+
-+		crypto_aead_clear_flags(tfm, ~0);
-+
-+		if (template[i].klen > MAX_KEYLEN) {
-+			pr_err("alg: aead%s: setkey failed on test %d for %s: key size %d > %d\n",
-+			       d, i, algo, template[i].klen, MAX_KEYLEN);
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+		memcpy(key, template[i].key, template[i].klen);
-+
-+		ret = crypto_aead_setkey(tfm, key, template[i].klen);
-+		if (!ret == template[i].fail) {
-+			pr_err("alg: tls%s: setkey failed on test %d for %s: flags=%x\n",
-+			       d, i, algo, crypto_aead_get_flags(tfm));
-+			goto out;
-+		} else if (ret)
-+			continue;
-+
-+		authsize = 20;
-+		ret = crypto_aead_setauthsize(tfm, authsize);
-+		if (ret) {
-+			pr_err("alg: aead%s: Failed to set authsize to %u on test %d for %s\n",
-+			       d, authsize, i, algo);
-+			goto out;
-+		}
-+
-+		k = !!template[i].alen;
-+		sg_init_table(sg, k + 1);
-+		sg_set_buf(&sg[0], assoc, template[i].alen);
-+		sg_set_buf(&sg[k], input, (enc ? template[i].rlen :
-+					   template[i].ilen));
-+		output = input;
-+
-+		if (diff_dst) {
-+			sg_init_table(sgout, k + 1);
-+			sg_set_buf(&sgout[0], assoc, template[i].alen);
-+
-+			output = xoutbuf[0];
-+			sg_set_buf(&sgout[k], output,
-+				   (enc ? template[i].rlen : template[i].ilen));
-+		}
-+
-+		aead_request_set_crypt(req, sg, (diff_dst) ? sgout : sg,
-+				       template[i].ilen, iv);
-+
-+		aead_request_set_ad(req, template[i].alen);
-+
-+		ret = enc ? crypto_aead_encrypt(req) : crypto_aead_decrypt(req);
-+
-+		switch (ret) {
-+		case 0:
-+			if (template[i].novrfy) {
-+				/* verification was supposed to fail */
-+				pr_err("alg: tls%s: %s failed on test %d for %s: ret was 0, expected -EBADMSG\n",
-+				       d, e, i, algo);
-+				/* so really, we got a bad message */
-+				ret = -EBADMSG;
-+				goto out;
-+			}
-+			break;
-+		case -EINPROGRESS:
-+		case -EBUSY:
-+			wait_for_completion(&result.completion);
-+			reinit_completion(&result.completion);
-+			ret = result.err;
-+			if (!ret)
-+				break;
-+		case -EBADMSG:
-+			/* verification failure was expected */
-+			if (template[i].novrfy)
-+				continue;
-+			/* fall through */
-+		default:
-+			pr_err("alg: tls%s: %s failed on test %d for %s: ret=%d\n",
-+			       d, e, i, algo, -ret);
-+			goto out;
-+		}
-+
-+		q = output;
-+		if (memcmp(q, template[i].result, template[i].rlen)) {
-+			pr_err("alg: tls%s: Test %d failed on %s for %s\n",
-+			       d, i, e, algo);
-+			hexdump(q, template[i].rlen);
-+			pr_err("should be:\n");
-+			hexdump(template[i].result, template[i].rlen);
-+			ret = -EINVAL;
-+			goto out;
-+		}
-+	}
-+
-+out:
-+	aead_request_free(req);
-+
-+	kfree(sg);
-+out_nosg:
-+	kfree(key);
-+out_nokey:
-+	kfree(iv);
-+out_noiv:
-+	testmgr_free_buf(axbuf);
-+out_noaxbuf:
-+	if (diff_dst)
-+		testmgr_free_buf(xoutbuf);
-+out_nooutbuf:
-+	testmgr_free_buf(xbuf);
-+out_noxbuf:
-+	return ret;
-+}
-+
-+static int test_tls(struct crypto_aead *tfm, int enc,
-+		    struct tls_testvec *template, unsigned int tcount)
-+{
-+	int ret;
-+	/* test 'dst == src' case */
-+	ret = __test_tls(tfm, enc, template, tcount, false);
-+	if (ret)
-+		return ret;
-+	/* test 'dst != src' case */
-+	return __test_tls(tfm, enc, template, tcount, true);
-+}
-+
-+static int alg_test_tls(const struct alg_test_desc *desc, const char *driver,
-+			u32 type, u32 mask)
-+{
-+	struct crypto_aead *tfm;
-+	int err = 0;
-+
-+	tfm = crypto_alloc_aead(driver, type, mask);
-+	if (IS_ERR(tfm)) {
-+		pr_err("alg: aead: Failed to load transform for %s: %ld\n",
-+		       driver, PTR_ERR(tfm));
-+		return PTR_ERR(tfm);
-+	}
-+
-+	if (desc->suite.tls.enc.vecs) {
-+		err = test_tls(tfm, ENCRYPT, desc->suite.tls.enc.vecs,
-+			       desc->suite.tls.enc.count);
-+		if (err)
-+			goto out;
-+	}
-+
-+	if (!err && desc->suite.tls.dec.vecs)
-+		err = test_tls(tfm, DECRYPT, desc->suite.tls.dec.vecs,
-+			       desc->suite.tls.dec.count);
-+
-+out:
-+	crypto_free_aead(tfm);
-+	return err;
-+}
-+
- static int test_cipher(struct crypto_cipher *tfm, int enc,
- 		       const struct cipher_testvec *template,
- 		       unsigned int tcount)
-@@ -3518,6 +3753,15 @@ static const struct alg_test_desc alg_te
- 			.hash = __VECS(tgr192_tv_template)
- 		}
- 	}, {
-+		.alg = "tls10(hmac(sha1),cbc(aes))",
-+		.test = alg_test_tls,
-+		.suite = {
-+			.tls = {
-+				.enc = __VECS(tls_enc_tv_template),
-+				.dec = __VECS(tls_dec_tv_template)
-+			}
-+		}
-+	}, {
- 		.alg = "vmac(aes)",
- 		.test = alg_test_hash,
- 		.suite = {
---- a/crypto/testmgr.h
-+++ b/crypto/testmgr.h
-@@ -125,6 +125,20 @@ struct drbg_testvec {
- 	size_t expectedlen;
- };
- 
-+struct tls_testvec {
-+	char *key;	/* wrapped keys for encryption and authentication */
-+	char *iv;	/* initialization vector */
-+	char *input;	/* input data */
-+	char *assoc;	/* associated data: seq num, type, version, input len */
-+	char *result;	/* result data */
-+	unsigned char fail;	/* the test failure is expected */
-+	unsigned char novrfy;	/* dec verification failure expected */
-+	unsigned char klen;	/* key length */
-+	unsigned short ilen;	/* input data length */
-+	unsigned short alen;	/* associated data length */
-+	unsigned short rlen;	/* result length */
-+};
-+
- struct akcipher_testvec {
- 	const unsigned char *key;
- 	const unsigned char *m;
-@@ -153,6 +167,211 @@ struct kpp_testvec {
- static const char zeroed_string[48];
- 
- /*
-+ * TLS1.0 synthetic test vectors
-+ */
-+static struct tls_testvec tls_enc_tv_template[] = {
-+	{
-+#ifdef __LITTLE_ENDIAN
-+		.key	= "\x08\x00"		/* rta length */
-+			"\x01\x00"		/* rta type */
-+#else
-+		.key	= "\x00\x08"		/* rta length */
-+			"\x00\x01"		/* rta type */
-+#endif
-+			"\x00\x00\x00\x10"	/* enc key length */
-+			"authenticationkey20benckeyis16_bytes",
-+		.klen	= 8 + 20 + 16,
-+		.iv	= "iv0123456789abcd",
-+		.input	= "Single block msg",
-+		.ilen	= 16,
-+		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
-+			"\x00\x03\x01\x00\x10",
-+		.alen	= 13,
-+		.result	= "\xd5\xac\xb\xd2\xac\xad\x3f\xb1"
-+			"\x59\x79\x1e\x91\x5f\x52\x14\x9c"
-+			"\xc0\x75\xd8\x4c\x97\x0f\x07\x73"
-+			"\xdc\x89\x47\x49\x49\xcb\x30\x6b"
-+			"\x1b\x45\x23\xa1\xd0\x51\xcf\x02"
-+			"\x2e\xa8\x5d\xa0\xfe\xca\x82\x61",
-+		.rlen	= 16 + 20 + 12,
-+	}, {
-+#ifdef __LITTLE_ENDIAN
-+		.key	= "\x08\x00"		/* rta length */
-+			"\x01\x00"		/* rta type */
-+#else
-+		.key	= "\x00\x08"		/* rta length */
-+			"\x00\x01"		/* rta type */
-+#endif
-+			"\x00\x00\x00\x10"	/* enc key length */
-+			"authenticationkey20benckeyis16_bytes",
-+		.klen	= 8 + 20 + 16,
-+		.iv	= "iv0123456789abcd",
-+		.input	= "",
-+		.ilen	= 0,
-+		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
-+			"\x00\x03\x01\x00\x00",
-+		.alen	= 13,
-+		.result = "\x58\x2a\x11\xc\x86\x8e\x4b\x67"
-+			"\x2d\x16\x26\x1a\xac\x4b\xe2\x1a"
-+			"\xe9\x6a\xcc\x4d\x6f\x79\x8a\x45"
-+			"\x1f\x4e\x27\xf2\xa7\x59\xb4\x5a",
-+		.rlen	= 20 + 12,
-+	}, {
-+#ifdef __LITTLE_ENDIAN
-+		.key	= "\x08\x00"		/* rta length */
-+			"\x01\x00"		/* rta type */
-+#else
-+		.key	= "\x00\x08"		/* rta length */
-+			"\x00\x01"		/* rta type */
-+#endif
-+			"\x00\x00\x00\x10"	/* enc key length */
-+			"authenticationkey20benckeyis16_bytes",
-+		.klen	= 8 + 20 + 16,
-+		.iv	= "iv0123456789abcd",
-+		.input	= "285 bytes plaintext285 bytes plaintext285 bytes"
-+			" plaintext285 bytes plaintext285 bytes plaintext285"
-+			" bytes plaintext285 bytes plaintext285 bytes"
-+			" plaintext285 bytes plaintext285 bytes plaintext285"
-+			" bytes plaintext285 bytes plaintext285 bytes"
-+			" plaintext285 bytes plaintext285 bytes plaintext285"
-+			" bytes plaintext285 bytes plaintext",
-+		.ilen	= 285,
-+		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
-+			"\x00\x03\x01\x01\x1d",
-+		.alen	= 13,
-+		.result = "\x80\x23\x82\x44\x14\x2a\x1d\x94\xc\xc2\x1d\xd"
-+			"\x3a\x32\x89\x4c\x57\x30\xa8\x89\x76\x46\xcc\x90"
-+			"\x1d\x88\xb8\xa6\x1a\x58\xe\x2d\xeb\x2c\xc7\x3a"
-+			"\x52\x4e\xdb\xb3\x1e\x83\x11\xf5\x3c\xce\x6e\x94"
-+			"\xd3\x26\x6a\x9a\xd\xbd\xc7\x98\xb9\xb3\x3a\x51"
-+			"\x1e\x4\x84\x8a\x8f\x54\x9a\x51\x69\x9c\xce\x31"
-+			"\x8d\x5d\x8b\xee\x5f\x70\xc\xc9\xb8\x50\x54\xf8"
-+			"\xb2\x4a\x7a\xcd\xeb\x7a\x82\x81\xc6\x41\xc8\x50"
-+			"\x91\x8d\xc8\xed\xcd\x40\x8f\x55\xd1\xec\xc9\xac"
-+			"\x15\x18\xf9\x20\xa0\xed\x18\xa1\xe3\x56\xe3\x14"
-+			"\xe5\xe8\x66\x63\x20\xed\xe4\x62\x9d\xa3\xa4\x1d"
-+			"\x81\x89\x18\xf2\x36\xae\xc8\x8a\x2b\xbc\xc3\xb8"
-+			"\x80\xf\x97\x21\x36\x39\x8\x84\x23\x18\x9e\x9c"
-+			"\x72\x32\x75\x2d\x2e\xf9\x60\xb\xe8\xcc\xd9\x74"
-+			"\x4\x1b\x8e\x99\xc1\x94\xee\xd0\xac\x4e\xfc\x7e"
-+			"\xf1\x96\xb3\xe7\x14\xb8\xf2\xc\x25\x97\x82\x6b"
-+			"\xbd\x0\x65\xab\x5c\xe3\x16\xfb\x68\xef\xea\x9d"
-+			"\xff\x44\x1d\x2a\x44\xf5\xc8\x56\x77\xb7\xbf\x13"
-+			"\xc8\x54\xdb\x92\xfe\x16\x4c\xbe\x18\xe9\xb\x8d"
-+			"\xb\xd4\x43\x58\x43\xaa\xf4\x3\x80\x97\x62\xd5"
-+			"\xdf\x3c\x28\xaa\xee\x48\x4b\x55\x41\x1b\x31\x2"
-+			"\xbe\xa0\x1c\xbd\xb7\x22\x2a\xe5\x53\x72\x73\x20"
-+			"\x44\x4f\xe6\x1\x2b\x34\x33\x11\x7d\xfb\x10\xc1"
-+			"\x66\x7c\xa6\xf4\x48\x36\x5e\x2\xda\x41\x4b\x3e"
-+			"\xe7\x80\x17\x17\xce\xf1\x3e\x6a\x8e\x26\xf3\xb7"
-+			"\x2b\x85\xd\x31\x8d\xba\x6c\x22\xb4\x28\x55\x7e"
-+			"\x2a\x9e\x26\xf1\x3d\x21\xac\x65",
-+		.rlen	= 285 + 20 + 15,
-+	}
-+};
-+
-+static struct tls_testvec tls_dec_tv_template[] = {
-+	{
-+#ifdef __LITTLE_ENDIAN
-+		.key	= "\x08\x00"		/* rta length */
-+			"\x01\x00"		/* rta type */
-+#else
-+		.key	= "\x00\x08"		/* rta length */
-+			"\x00\x01"		/* rta type */
-+#endif
-+			"\x00\x00\x00\x10"	/* enc key length */
-+			"authenticationkey20benckeyis16_bytes",
-+		.klen	= 8 + 20 + 16,
-+		.iv	= "iv0123456789abcd",
-+		.input	= "\xd5\xac\xb\xd2\xac\xad\x3f\xb1"
-+			"\x59\x79\x1e\x91\x5f\x52\x14\x9c"
-+			"\xc0\x75\xd8\x4c\x97\x0f\x07\x73"
-+			"\xdc\x89\x47\x49\x49\xcb\x30\x6b"
-+			"\x1b\x45\x23\xa1\xd0\x51\xcf\x02"
-+			"\x2e\xa8\x5d\xa0\xfe\xca\x82\x61",
-+		.ilen	= 16 + 20 + 12,
-+		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
-+			"\x00\x03\x01\x00\x30",
-+		.alen	= 13,
-+		.result	= "Single block msg",
-+		.rlen	= 16,
-+	}, {
-+#ifdef __LITTLE_ENDIAN
-+		.key	= "\x08\x00"		/* rta length */
-+			"\x01\x00"		/* rta type */
-+#else
-+		.key	= "\x00\x08"		/* rta length */
-+			"\x00\x01"		/* rta type */
-+#endif
-+			"\x00\x00\x00\x10"	/* enc key length */
-+			"authenticationkey20benckeyis16_bytes",
-+		.klen	= 8 + 20 + 16,
-+		.iv	= "iv0123456789abcd",
-+		.input = "\x58\x2a\x11\xc\x86\x8e\x4b\x67"
-+			"\x2d\x16\x26\x1a\xac\x4b\xe2\x1a"
-+			"\xe9\x6a\xcc\x4d\x6f\x79\x8a\x45"
-+			"\x1f\x4e\x27\xf2\xa7\x59\xb4\x5a",
-+		.ilen	= 20 + 12,
-+		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
-+			"\x00\x03\x01\x00\x20",
-+		.alen	= 13,
-+		.result	= "",
-+		.rlen	= 0,
-+	}, {
-+#ifdef __LITTLE_ENDIAN
-+		.key	= "\x08\x00"		/* rta length */
-+			"\x01\x00"		/* rta type */
-+#else
-+		.key	= "\x00\x08"		/* rta length */
-+			"\x00\x01"		/* rta type */
-+#endif
-+			"\x00\x00\x00\x10"	/* enc key length */
-+			"authenticationkey20benckeyis16_bytes",
-+		.klen	= 8 + 20 + 16,
-+		.iv	= "iv0123456789abcd",
-+		.input = "\x80\x23\x82\x44\x14\x2a\x1d\x94\xc\xc2\x1d\xd"
-+			"\x3a\x32\x89\x4c\x57\x30\xa8\x89\x76\x46\xcc\x90"
-+			"\x1d\x88\xb8\xa6\x1a\x58\xe\x2d\xeb\x2c\xc7\x3a"
-+			"\x52\x4e\xdb\xb3\x1e\x83\x11\xf5\x3c\xce\x6e\x94"
-+			"\xd3\x26\x6a\x9a\xd\xbd\xc7\x98\xb9\xb3\x3a\x51"
-+			"\x1e\x4\x84\x8a\x8f\x54\x9a\x51\x69\x9c\xce\x31"
-+			"\x8d\x5d\x8b\xee\x5f\x70\xc\xc9\xb8\x50\x54\xf8"
-+			"\xb2\x4a\x7a\xcd\xeb\x7a\x82\x81\xc6\x41\xc8\x50"
-+			"\x91\x8d\xc8\xed\xcd\x40\x8f\x55\xd1\xec\xc9\xac"
-+			"\x15\x18\xf9\x20\xa0\xed\x18\xa1\xe3\x56\xe3\x14"
-+			"\xe5\xe8\x66\x63\x20\xed\xe4\x62\x9d\xa3\xa4\x1d"
-+			"\x81\x89\x18\xf2\x36\xae\xc8\x8a\x2b\xbc\xc3\xb8"
-+			"\x80\xf\x97\x21\x36\x39\x8\x84\x23\x18\x9e\x9c"
-+			"\x72\x32\x75\x2d\x2e\xf9\x60\xb\xe8\xcc\xd9\x74"
-+			"\x4\x1b\x8e\x99\xc1\x94\xee\xd0\xac\x4e\xfc\x7e"
-+			"\xf1\x96\xb3\xe7\x14\xb8\xf2\xc\x25\x97\x82\x6b"
-+			"\xbd\x0\x65\xab\x5c\xe3\x16\xfb\x68\xef\xea\x9d"
-+			"\xff\x44\x1d\x2a\x44\xf5\xc8\x56\x77\xb7\xbf\x13"
-+			"\xc8\x54\xdb\x92\xfe\x16\x4c\xbe\x18\xe9\xb\x8d"
-+			"\xb\xd4\x43\x58\x43\xaa\xf4\x3\x80\x97\x62\xd5"
-+			"\xdf\x3c\x28\xaa\xee\x48\x4b\x55\x41\x1b\x31\x2"
-+			"\xbe\xa0\x1c\xbd\xb7\x22\x2a\xe5\x53\x72\x73\x20"
-+			"\x44\x4f\xe6\x1\x2b\x34\x33\x11\x7d\xfb\x10\xc1"
-+			"\x66\x7c\xa6\xf4\x48\x36\x5e\x2\xda\x41\x4b\x3e"
-+			"\xe7\x80\x17\x17\xce\xf1\x3e\x6a\x8e\x26\xf3\xb7"
-+			"\x2b\x85\xd\x31\x8d\xba\x6c\x22\xb4\x28\x55\x7e"
-+			"\x2a\x9e\x26\xf1\x3d\x21\xac\x65",
-+
-+		.ilen	= 285 + 20 + 15,
-+		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
-+			"\x00\x03\x01\x01\x40",
-+		.alen	= 13,
-+		.result	= "285 bytes plaintext285 bytes plaintext285 bytes"
-+			" plaintext285 bytes plaintext285 bytes plaintext285"
-+			" bytes plaintext285 bytes plaintext285 bytes"
-+			" plaintext285 bytes plaintext285 bytes plaintext285"
-+			" bytes plaintext285 bytes plaintext285 bytes"
-+			" plaintext285 bytes plaintext285 bytes plaintext",
-+		.rlen	= 285,
-+	}
-+};
-+
-+/*
-  * RSA test vectors. Borrowed from openSSL.
-  */
- static const struct akcipher_testvec rsa_tv_template[] = {
---- /dev/null
-+++ b/crypto/tls.c
-@@ -0,0 +1,607 @@
-+/*
-+ * Copyright 2013 Freescale Semiconductor, Inc.
-+ * Copyright 2017 NXP Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the Free
-+ * Software Foundation; either version 2 of the License, or (at your option)
-+ * any later version.
-+ *
-+ */
-+
-+#include <crypto/internal/aead.h>
-+#include <crypto/internal/hash.h>
-+#include <crypto/internal/skcipher.h>
-+#include <crypto/authenc.h>
-+#include <crypto/null.h>
-+#include <crypto/scatterwalk.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/rtnetlink.h>
-+
-+struct tls_instance_ctx {
-+	struct crypto_ahash_spawn auth;
-+	struct crypto_skcipher_spawn enc;
-+};
-+
-+struct crypto_tls_ctx {
-+	unsigned int reqoff;
-+	struct crypto_ahash *auth;
-+	struct crypto_skcipher *enc;
-+	struct crypto_skcipher *null;
-+};
-+
-+struct tls_request_ctx {
-+	/*
-+	 * cryptlen holds the payload length in the case of encryption or
-+	 * payload_len + icv_len + padding_len in case of decryption
-+	 */
-+	unsigned int cryptlen;
-+	/* working space for partial results */
-+	struct scatterlist tmp[2];
-+	struct scatterlist cipher[2];
-+	struct scatterlist dst[2];
-+	char tail[];
-+};
-+
-+struct async_op {
-+	struct completion completion;
-+	int err;
-+};
-+
-+static void tls_async_op_done(struct crypto_async_request *req, int err)
-+{
-+	struct async_op *areq = req->data;
-+
-+	if (err == -EINPROGRESS)
-+		return;
-+
-+	areq->err = err;
-+	complete(&areq->completion);
-+}
-+
-+static int crypto_tls_setkey(struct crypto_aead *tls, const u8 *key,
-+			     unsigned int keylen)
-+{
-+	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
-+	struct crypto_ahash *auth = ctx->auth;
-+	struct crypto_skcipher *enc = ctx->enc;
-+	struct crypto_authenc_keys keys;
-+	int err = -EINVAL;
-+
-+	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
-+		goto badkey;
-+
-+	crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK);
-+	crypto_ahash_set_flags(auth, crypto_aead_get_flags(tls) &
-+				    CRYPTO_TFM_REQ_MASK);
-+	err = crypto_ahash_setkey(auth, keys.authkey, keys.authkeylen);
-+	crypto_aead_set_flags(tls, crypto_ahash_get_flags(auth) &
-+				       CRYPTO_TFM_RES_MASK);
-+
-+	if (err)
-+		goto out;
-+
-+	crypto_skcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK);
-+	crypto_skcipher_set_flags(enc, crypto_aead_get_flags(tls) &
-+					 CRYPTO_TFM_REQ_MASK);
-+	err = crypto_skcipher_setkey(enc, keys.enckey, keys.enckeylen);
-+	crypto_aead_set_flags(tls, crypto_skcipher_get_flags(enc) &
-+				       CRYPTO_TFM_RES_MASK);
-+
-+out:
-+	return err;
-+
-+badkey:
-+	crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+	goto out;
-+}
-+
-+/**
-+ * crypto_tls_genicv - Calculate hmac digest for a TLS record
-+ * @hash:	(output) buffer to save the digest into
-+ * @src:	(input) scatterlist with the assoc and payload data
-+ * @srclen:	(input) size of the source buffer (assoclen + cryptlen)
-+ * @req:	(input) aead request
-+ **/
-+static int crypto_tls_genicv(u8 *hash, struct scatterlist *src,
-+			     unsigned int srclen, struct aead_request *req)
-+{
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
-+	struct tls_request_ctx *treq_ctx = aead_request_ctx(req);
-+	struct async_op ahash_op;
-+	struct ahash_request *ahreq = (void *)(treq_ctx->tail + ctx->reqoff);
-+	unsigned int flags = CRYPTO_TFM_REQ_MAY_SLEEP;
-+	int err = -EBADMSG;
-+
-+	 /* Bail out if the request assoc len is 0 */
-+	if (!req->assoclen)
-+		return err;
-+
-+	init_completion(&ahash_op.completion);
-+
-+	/* the hash transform to be executed comes from the original request */
-+	ahash_request_set_tfm(ahreq, ctx->auth);
-+	/* prepare the hash request with input data and result pointer */
-+	ahash_request_set_crypt(ahreq, src, hash, srclen);
-+	/* set the notifier for when the async hash function returns */
-+	ahash_request_set_callback(ahreq, aead_request_flags(req) & flags,
-+				   tls_async_op_done, &ahash_op);
-+
-+	/* Calculate the digest on the given data. The result is put in hash */
-+	err = crypto_ahash_digest(ahreq);
-+	if (err == -EINPROGRESS) {
-+		err = wait_for_completion_interruptible(&ahash_op.completion);
-+		if (!err)
-+			err = ahash_op.err;
-+	}
-+
-+	return err;
-+}
-+
-+/**
-+ * crypto_tls_gen_padicv - Calculate and pad hmac digest for a TLS record
-+ * @hash:	(output) buffer to save the digest and padding into
-+ * @phashlen:	(output) the size of digest + padding
-+ * @req:	(input) aead request
-+ **/
-+static int crypto_tls_gen_padicv(u8 *hash, unsigned int *phashlen,
-+				 struct aead_request *req)
-+{
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	unsigned int hash_size = crypto_aead_authsize(tls);
-+	unsigned int block_size = crypto_aead_blocksize(tls);
-+	unsigned int srclen = req->cryptlen + hash_size;
-+	unsigned int icvlen = req->cryptlen + req->assoclen;
-+	unsigned int padlen;
-+	int err;
-+
-+	err = crypto_tls_genicv(hash, req->src, icvlen, req);
-+	if (err)
-+		goto out;
-+
-+	/* add padding after digest */
-+	padlen = block_size - (srclen % block_size);
-+	memset(hash + hash_size, padlen - 1, padlen);
-+
-+	*phashlen = hash_size + padlen;
-+out:
-+	return err;
-+}
-+
-+static int crypto_tls_copy_data(struct aead_request *req,
-+				struct scatterlist *src,
-+				struct scatterlist *dst,
-+				unsigned int len)
-+{
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
-+	SKCIPHER_REQUEST_ON_STACK(skreq, ctx->null);
-+
-+	skcipher_request_set_tfm(skreq, ctx->null);
-+	skcipher_request_set_callback(skreq, aead_request_flags(req),
-+				      NULL, NULL);
-+	skcipher_request_set_crypt(skreq, src, dst, len, NULL);
-+
-+	return crypto_skcipher_encrypt(skreq);
-+}
-+
-+static int crypto_tls_encrypt(struct aead_request *req)
-+{
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
-+	struct tls_request_ctx *treq_ctx = aead_request_ctx(req);
-+	struct skcipher_request *skreq;
-+	struct scatterlist *cipher = treq_ctx->cipher;
-+	struct scatterlist *tmp = treq_ctx->tmp;
-+	struct scatterlist *sg, *src, *dst;
-+	unsigned int cryptlen, phashlen;
-+	u8 *hash = treq_ctx->tail;
-+	int err;
-+
-+	/*
-+	 * The hash result is saved at the beginning of the tls request ctx
-+	 * and is aligned as required by the hash transform. Enough space was
-+	 * allocated in crypto_tls_init_tfm to accommodate the difference. The
-+	 * requests themselves start later at treq_ctx->tail + ctx->reqoff so
-+	 * the result is not overwritten by the second (cipher) request.
-+	 */
-+	hash = (u8 *)ALIGN((unsigned long)hash +
-+			   crypto_ahash_alignmask(ctx->auth),
-+			   crypto_ahash_alignmask(ctx->auth) + 1);
-+
-+	/*
-+	 * STEP 1: create ICV together with necessary padding
-+	 */
-+	err = crypto_tls_gen_padicv(hash, &phashlen, req);
-+	if (err)
-+		return err;
-+
-+	/*
-+	 * STEP 2: Hash and padding are combined with the payload
-+	 * depending on the form it arrives. Scatter tables must have at least
-+	 * one page of data before chaining with another table and can't have
-+	 * an empty data page. The following code addresses these requirements.
-+	 *
-+	 * If the payload is empty, only the hash is encrypted, otherwise the
-+	 * payload scatterlist is merged with the hash. A special merging case
-+	 * is when the payload has only one page of data. In that case the
-+	 * payload page is moved to another scatterlist and prepared there for
-+	 * encryption.
-+	 */
-+	if (req->cryptlen) {
-+		src = scatterwalk_ffwd(tmp, req->src, req->assoclen);
-+
-+		sg_init_table(cipher, 2);
-+		sg_set_buf(cipher + 1, hash, phashlen);
-+
-+		if (sg_is_last(src)) {
-+			sg_set_page(cipher, sg_page(src), req->cryptlen,
-+				    src->offset);
-+			src = cipher;
-+		} else {
-+			unsigned int rem_len = req->cryptlen;
-+
-+			for (sg = src; rem_len > sg->length; sg = sg_next(sg))
-+				rem_len -= min(rem_len, sg->length);
-+
-+			sg_set_page(cipher, sg_page(sg), rem_len, sg->offset);
-+			sg_chain(sg, 1, cipher);
-+		}
-+	} else {
-+		sg_init_one(cipher, hash, phashlen);
-+		src = cipher;
-+	}
-+
-+	/**
-+	 * If src != dst copy the associated data from source to destination.
-+	 * In both cases fast-forward passed the associated data in the dest.
-+	 */
-+	if (req->src != req->dst) {
-+		err = crypto_tls_copy_data(req, req->src, req->dst,
-+					   req->assoclen);
-+		if (err)
-+			return err;
-+	}
-+	dst = scatterwalk_ffwd(treq_ctx->dst, req->dst, req->assoclen);
-+
-+	/*
-+	 * STEP 3: encrypt the frame and return the result
-+	 */
-+	cryptlen = req->cryptlen + phashlen;
-+
-+	/*
-+	 * The hash and the cipher are applied at different times and their
-+	 * requests can use the same memory space without interference
-+	 */
-+	skreq = (void *)(treq_ctx->tail + ctx->reqoff);
-+	skcipher_request_set_tfm(skreq, ctx->enc);
-+	skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv);
-+	skcipher_request_set_callback(skreq, aead_request_flags(req),
-+				      req->base.complete, req->base.data);
-+	/*
-+	 * Apply the cipher transform. The result will be in req->dst when the
-+	 * asynchronuous call terminates
-+	 */
-+	err = crypto_skcipher_encrypt(skreq);
-+
-+	return err;
-+}
-+
-+static int crypto_tls_decrypt(struct aead_request *req)
-+{
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
-+	struct tls_request_ctx *treq_ctx = aead_request_ctx(req);
-+	unsigned int cryptlen = req->cryptlen;
-+	unsigned int hash_size = crypto_aead_authsize(tls);
-+	unsigned int block_size = crypto_aead_blocksize(tls);
-+	struct skcipher_request *skreq = (void *)(treq_ctx->tail + ctx->reqoff);
-+	struct scatterlist *tmp = treq_ctx->tmp;
-+	struct scatterlist *src, *dst;
-+
-+	u8 padding[255]; /* padding can be 0-255 bytes */
-+	u8 pad_size;
-+	u16 *len_field;
-+	u8 *ihash, *hash = treq_ctx->tail;
-+
-+	int paderr = 0;
-+	int err = -EINVAL;
-+	int i;
-+	struct async_op ciph_op;
-+
-+	/*
-+	 * Rule out bad packets. The input packet length must be at least one
-+	 * byte more than the hash_size
-+	 */
-+	if (cryptlen <= hash_size || cryptlen % block_size)
-+		goto out;
-+
-+	/*
-+	 * Step 1 - Decrypt the source. Fast-forward past the associated data
-+	 * to the encrypted data. The result will be overwritten in place so
-+	 * that the decrypted data will be adjacent to the associated data. The
-+	 * last step (computing the hash) will have it's input data already
-+	 * prepared and ready to be accessed at req->src.
-+	 */
-+	src = scatterwalk_ffwd(tmp, req->src, req->assoclen);
-+	dst = src;
-+
-+	init_completion(&ciph_op.completion);
-+	skcipher_request_set_tfm(skreq, ctx->enc);
-+	skcipher_request_set_callback(skreq, aead_request_flags(req),
-+				      tls_async_op_done, &ciph_op);
-+	skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv);
-+	err = crypto_skcipher_decrypt(skreq);
-+	if (err == -EINPROGRESS) {
-+		err = wait_for_completion_interruptible(&ciph_op.completion);
-+		if (!err)
-+			err = ciph_op.err;
-+	}
-+	if (err)
-+		goto out;
-+
-+	/*
-+	 * Step 2 - Verify padding
-+	 * Retrieve the last byte of the payload; this is the padding size.
-+	 */
-+	cryptlen -= 1;
-+	scatterwalk_map_and_copy(&pad_size, dst, cryptlen, 1, 0);
-+
-+	/* RFC recommendation for invalid padding size. */
-+	if (cryptlen < pad_size + hash_size) {
-+		pad_size = 0;
-+		paderr = -EBADMSG;
-+	}
-+	cryptlen -= pad_size;
-+	scatterwalk_map_and_copy(padding, dst, cryptlen, pad_size, 0);
-+
-+	/* Padding content must be equal with pad_size. We verify it all */
-+	for (i = 0; i < pad_size; i++)
-+		if (padding[i] != pad_size)
-+			paderr = -EBADMSG;
-+
-+	/*
-+	 * Step 3 - Verify hash
-+	 * Align the digest result as required by the hash transform. Enough
-+	 * space was allocated in crypto_tls_init_tfm
-+	 */
-+	hash = (u8 *)ALIGN((unsigned long)hash +
-+			   crypto_ahash_alignmask(ctx->auth),
-+			   crypto_ahash_alignmask(ctx->auth) + 1);
-+	/*
-+	 * Two bytes at the end of the associated data make the length field.
-+	 * It must be updated with the length of the cleartext message before
-+	 * the hash is calculated.
-+	 */
-+	len_field = sg_virt(req->src) + req->assoclen - 2;
-+	cryptlen -= hash_size;
-+	*len_field = htons(cryptlen);
-+
-+	/* This is the hash from the decrypted packet. Save it for later */
-+	ihash = hash + hash_size;
-+	scatterwalk_map_and_copy(ihash, dst, cryptlen, hash_size, 0);
-+
-+	/* Now compute and compare our ICV with the one from the packet */
-+	err = crypto_tls_genicv(hash, req->src, cryptlen + req->assoclen, req);
-+	if (!err)
-+		err = memcmp(hash, ihash, hash_size) ? -EBADMSG : 0;
-+
-+	if (req->src != req->dst) {
-+		err = crypto_tls_copy_data(req, req->src, req->dst, cryptlen +
-+					   req->assoclen);
-+		if (err)
-+			goto out;
-+	}
-+
-+	/* return the first found error */
-+	if (paderr)
-+		err = paderr;
-+
-+out:
-+	aead_request_complete(req, err);
-+	return err;
-+}
-+
-+static int crypto_tls_init_tfm(struct crypto_aead *tfm)
-+{
-+	struct aead_instance *inst = aead_alg_instance(tfm);
-+	struct tls_instance_ctx *ictx = aead_instance_ctx(inst);
-+	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm);
-+	struct crypto_ahash *auth;
-+	struct crypto_skcipher *enc;
-+	struct crypto_skcipher *null;
-+	int err;
-+
-+	auth = crypto_spawn_ahash(&ictx->auth);
-+	if (IS_ERR(auth))
-+		return PTR_ERR(auth);
-+
-+	enc = crypto_spawn_skcipher(&ictx->enc);
-+	err = PTR_ERR(enc);
-+	if (IS_ERR(enc))
-+		goto err_free_ahash;
-+
-+	null = crypto_get_default_null_skcipher2();
-+	err = PTR_ERR(null);
-+	if (IS_ERR(null))
-+		goto err_free_skcipher;
-+
-+	ctx->auth = auth;
-+	ctx->enc = enc;
-+	ctx->null = null;
-+
-+	/*
-+	 * Allow enough space for two digests. The two digests will be compared
-+	 * during the decryption phase. One will come from the decrypted packet
-+	 * and the other will be calculated. For encryption, one digest is
-+	 * padded (up to a cipher blocksize) and chained with the payload
-+	 */
-+	ctx->reqoff = ALIGN(crypto_ahash_digestsize(auth) +
-+			    crypto_ahash_alignmask(auth),
-+			    crypto_ahash_alignmask(auth) + 1) +
-+			    max(crypto_ahash_digestsize(auth),
-+				crypto_skcipher_blocksize(enc));
-+
-+	crypto_aead_set_reqsize(tfm,
-+				sizeof(struct tls_request_ctx) +
-+				ctx->reqoff +
-+				max_t(unsigned int,
-+				      crypto_ahash_reqsize(auth) +
-+				      sizeof(struct ahash_request),
-+				      crypto_skcipher_reqsize(enc) +
-+				      sizeof(struct skcipher_request)));
-+
-+	return 0;
-+
-+err_free_skcipher:
-+	crypto_free_skcipher(enc);
-+err_free_ahash:
-+	crypto_free_ahash(auth);
-+	return err;
-+}
-+
-+static void crypto_tls_exit_tfm(struct crypto_aead *tfm)
-+{
-+	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm);
-+
-+	crypto_free_ahash(ctx->auth);
-+	crypto_free_skcipher(ctx->enc);
-+	crypto_put_default_null_skcipher2();
-+}
-+
-+static void crypto_tls_free(struct aead_instance *inst)
-+{
-+	struct tls_instance_ctx *ctx = aead_instance_ctx(inst);
-+
-+	crypto_drop_skcipher(&ctx->enc);
-+	crypto_drop_ahash(&ctx->auth);
-+	kfree(inst);
-+}
-+
-+static int crypto_tls_create(struct crypto_template *tmpl, struct rtattr **tb)
-+{
-+	struct crypto_attr_type *algt;
-+	struct aead_instance *inst;
-+	struct hash_alg_common *auth;
-+	struct crypto_alg *auth_base;
-+	struct skcipher_alg *enc;
-+	struct tls_instance_ctx *ctx;
-+	const char *enc_name;
-+	int err;
-+
-+	algt = crypto_get_attr_type(tb);
-+	if (IS_ERR(algt))
-+		return PTR_ERR(algt);
-+
-+	if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask)
-+		return -EINVAL;
-+
-+	auth = ahash_attr_alg(tb[1], CRYPTO_ALG_TYPE_HASH,
-+			      CRYPTO_ALG_TYPE_AHASH_MASK |
-+			      crypto_requires_sync(algt->type, algt->mask));
-+	if (IS_ERR(auth))
-+		return PTR_ERR(auth);
-+
-+	auth_base = &auth->base;
-+
-+	enc_name = crypto_attr_alg_name(tb[2]);
-+	err = PTR_ERR(enc_name);
-+	if (IS_ERR(enc_name))
-+		goto out_put_auth;
-+
-+	inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
-+	err = -ENOMEM;
-+	if (!inst)
-+		goto out_put_auth;
-+
-+	ctx = aead_instance_ctx(inst);
-+
-+	err = crypto_init_ahash_spawn(&ctx->auth, auth,
-+				      aead_crypto_instance(inst));
-+	if (err)
-+		goto err_free_inst;
-+
-+	crypto_set_skcipher_spawn(&ctx->enc, aead_crypto_instance(inst));
-+	err = crypto_grab_skcipher(&ctx->enc, enc_name, 0,
-+				   crypto_requires_sync(algt->type,
-+							algt->mask));
-+	if (err)
-+		goto err_drop_auth;
-+
-+	enc = crypto_spawn_skcipher_alg(&ctx->enc);
-+
-+	err = -ENAMETOOLONG;
-+	if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
-+		     "tls10(%s,%s)", auth_base->cra_name,
-+		     enc->base.cra_name) >= CRYPTO_MAX_ALG_NAME)
-+		goto err_drop_enc;
-+
-+	if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
-+		     "tls10(%s,%s)", auth_base->cra_driver_name,
-+		     enc->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME)
-+		goto err_drop_enc;
-+
-+	inst->alg.base.cra_flags = (auth_base->cra_flags |
-+					enc->base.cra_flags) & CRYPTO_ALG_ASYNC;
-+	inst->alg.base.cra_priority = enc->base.cra_priority * 10 +
-+					auth_base->cra_priority;
-+	inst->alg.base.cra_blocksize = enc->base.cra_blocksize;
-+	inst->alg.base.cra_alignmask = auth_base->cra_alignmask |
-+					enc->base.cra_alignmask;
-+	inst->alg.base.cra_ctxsize = sizeof(struct crypto_tls_ctx);
-+
-+	inst->alg.ivsize = crypto_skcipher_alg_ivsize(enc);
-+	inst->alg.chunksize = crypto_skcipher_alg_chunksize(enc);
-+	inst->alg.maxauthsize = auth->digestsize;
-+
-+	inst->alg.init = crypto_tls_init_tfm;
-+	inst->alg.exit = crypto_tls_exit_tfm;
-+
-+	inst->alg.setkey = crypto_tls_setkey;
-+	inst->alg.encrypt = crypto_tls_encrypt;
-+	inst->alg.decrypt = crypto_tls_decrypt;
-+
-+	inst->free = crypto_tls_free;
-+
-+	err = aead_register_instance(tmpl, inst);
-+	if (err)
-+		goto err_drop_enc;
-+
-+out:
-+	crypto_mod_put(auth_base);
-+	return err;
-+
-+err_drop_enc:
-+	crypto_drop_skcipher(&ctx->enc);
-+err_drop_auth:
-+	crypto_drop_ahash(&ctx->auth);
-+err_free_inst:
-+	kfree(inst);
-+out_put_auth:
-+	goto out;
-+}
-+
-+static struct crypto_template crypto_tls_tmpl = {
-+	.name = "tls10",
-+	.create = crypto_tls_create,
-+	.module = THIS_MODULE,
-+};
-+
-+static int __init crypto_tls_module_init(void)
-+{
-+	return crypto_register_template(&crypto_tls_tmpl);
-+}
-+
-+static void __exit crypto_tls_module_exit(void)
-+{
-+	crypto_unregister_template(&crypto_tls_tmpl);
-+}
-+
-+module_init(crypto_tls_module_init);
-+module_exit(crypto_tls_module_exit);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("TLS 1.0 record encryption");
---- a/drivers/crypto/Makefile
-+++ b/drivers/crypto/Makefile
-@@ -10,7 +10,7 @@ obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chel
- obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/
- obj-$(CONFIG_CRYPTO_DEV_NITROX) += cavium/nitrox/
- obj-$(CONFIG_CRYPTO_DEV_EXYNOS_RNG) += exynos-rng.o
--obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/
-+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON) += caam/
- obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
- obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
- obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
---- a/drivers/crypto/caam/Kconfig
-+++ b/drivers/crypto/caam/Kconfig
-@@ -1,7 +1,11 @@
-+config CRYPTO_DEV_FSL_CAAM_COMMON
-+	tristate
-+
- config CRYPTO_DEV_FSL_CAAM
--	tristate "Freescale CAAM-Multicore driver backend"
-+	tristate "Freescale CAAM-Multicore platform driver backend"
- 	depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE
- 	select SOC_BUS
-+	select CRYPTO_DEV_FSL_CAAM_COMMON
- 	help
- 	  Enables the driver module for Freescale's Cryptographic Accelerator
- 	  and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
-@@ -12,9 +16,16 @@ config CRYPTO_DEV_FSL_CAAM
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called caam.
- 
-+if CRYPTO_DEV_FSL_CAAM
-+
-+config CRYPTO_DEV_FSL_CAAM_DEBUG
-+	bool "Enable debug output in CAAM driver"
-+	help
-+	  Selecting this will enable printing of various debug
-+	  information in the CAAM driver.
-+
- config CRYPTO_DEV_FSL_CAAM_JR
- 	tristate "Freescale CAAM Job Ring driver backend"
--	depends on CRYPTO_DEV_FSL_CAAM
- 	default y
- 	help
- 	  Enables the driver module for Job Rings which are part of
-@@ -25,9 +36,10 @@ config CRYPTO_DEV_FSL_CAAM_JR
- 	  To compile this driver as a module, choose M here: the module
- 	  will be called caam_jr.
- 
-+if CRYPTO_DEV_FSL_CAAM_JR
-+
- config CRYPTO_DEV_FSL_CAAM_RINGSIZE
- 	int "Job Ring size"
--	depends on CRYPTO_DEV_FSL_CAAM_JR
- 	range 2 9
- 	default "9"
- 	help
-@@ -45,7 +57,6 @@ config CRYPTO_DEV_FSL_CAAM_RINGSIZE
- 
- config CRYPTO_DEV_FSL_CAAM_INTC
- 	bool "Job Ring interrupt coalescing"
--	depends on CRYPTO_DEV_FSL_CAAM_JR
- 	help
- 	  Enable the Job Ring's interrupt coalescing feature.
- 
-@@ -75,7 +86,6 @@ config CRYPTO_DEV_FSL_CAAM_INTC_TIME_THL
- 
- config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
- 	tristate "Register algorithm implementations with the Crypto API"
--	depends on CRYPTO_DEV_FSL_CAAM_JR
- 	default y
- 	select CRYPTO_AEAD
- 	select CRYPTO_AUTHENC
-@@ -90,7 +100,7 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
- 
- config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
- 	tristate "Queue Interface as Crypto API backend"
--	depends on CRYPTO_DEV_FSL_CAAM_JR && FSL_DPAA && NET
-+	depends on FSL_SDK_DPA && NET
- 	default y
- 	select CRYPTO_AUTHENC
- 	select CRYPTO_BLKCIPHER
-@@ -107,7 +117,6 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
- 
- config CRYPTO_DEV_FSL_CAAM_AHASH_API
- 	tristate "Register hash algorithm implementations with Crypto API"
--	depends on CRYPTO_DEV_FSL_CAAM_JR
- 	default y
- 	select CRYPTO_HASH
- 	help
-@@ -119,7 +128,6 @@ config CRYPTO_DEV_FSL_CAAM_AHASH_API
- 
- config CRYPTO_DEV_FSL_CAAM_PKC_API
-         tristate "Register public key cryptography implementations with Crypto API"
--        depends on CRYPTO_DEV_FSL_CAAM_JR
-         default y
-         select CRYPTO_RSA
-         help
-@@ -131,7 +139,6 @@ config CRYPTO_DEV_FSL_CAAM_PKC_API
- 
- config CRYPTO_DEV_FSL_CAAM_RNG_API
- 	tristate "Register caam device for hwrng API"
--	depends on CRYPTO_DEV_FSL_CAAM_JR
- 	default y
- 	select CRYPTO_RNG
- 	select HW_RANDOM
-@@ -142,13 +149,31 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API
- 	  To compile this as a module, choose M here: the module
- 	  will be called caamrng.
- 
--config CRYPTO_DEV_FSL_CAAM_DEBUG
--	bool "Enable debug output in CAAM driver"
--	depends on CRYPTO_DEV_FSL_CAAM
--	help
--	  Selecting this will enable printing of various debug
--	  information in the CAAM driver.
-+endif # CRYPTO_DEV_FSL_CAAM_JR
-+
-+endif # CRYPTO_DEV_FSL_CAAM
-+
-+config CRYPTO_DEV_FSL_DPAA2_CAAM
-+	tristate "QorIQ DPAA2 CAAM (DPSECI) driver"
-+	depends on FSL_MC_DPIO
-+	select CRYPTO_DEV_FSL_CAAM_COMMON
-+	select CRYPTO_BLKCIPHER
-+	select CRYPTO_AUTHENC
-+	select CRYPTO_AEAD
-+	select CRYPTO_HASH
-+	---help---
-+	  CAAM driver for QorIQ Data Path Acceleration Architecture 2.
-+	  It handles DPSECI DPAA2 objects that sit on the Management Complex
-+	  (MC) fsl-mc bus.
-+
-+	  To compile this as a module, choose M here: the module
-+	  will be called dpaa2_caam.
- 
- config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC
- 	def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \
--		      CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI)
-+		      CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI || \
-+		      CRYPTO_DEV_FSL_DPAA2_CAAM)
-+
-+config CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC
-+	def_tristate (CRYPTO_DEV_FSL_CAAM_AHASH_API || \
-+		      CRYPTO_DEV_FSL_DPAA2_CAAM)
---- a/drivers/crypto/caam/Makefile
-+++ b/drivers/crypto/caam/Makefile
-@@ -6,19 +6,27 @@ ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG
- 	ccflags-y := -DDEBUG
- endif
- 
-+ccflags-y += -DVERSION=\"\"
-+
-+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON) += error.o
- obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o
- obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o
- obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
- obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o
- obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o
- obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
-+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC) += caamhash_desc.o
- obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
- obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caam_pkc.o
- 
- caam-objs := ctrl.o
--caam_jr-objs := jr.o key_gen.o error.o
-+caam_jr-objs := jr.o key_gen.o
- caam_pkc-y := caampkc.o pkc_desc.o
- ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),)
- 	ccflags-y += -DCONFIG_CAAM_QI
- 	caam-objs += qi.o
- endif
-+
-+obj-$(CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM) += dpaa2_caam.o
-+
-+dpaa2_caam-y    := caamalg_qi2.o dpseci.o
---- a/drivers/crypto/caam/caamalg.c
-+++ b/drivers/crypto/caam/caamalg.c
-@@ -108,6 +108,7 @@ struct caam_ctx {
- 	dma_addr_t sh_desc_dec_dma;
- 	dma_addr_t sh_desc_givenc_dma;
- 	dma_addr_t key_dma;
-+	enum dma_data_direction dir;
- 	struct device *jrdev;
- 	struct alginfo adata;
- 	struct alginfo cdata;
-@@ -118,6 +119,7 @@ static int aead_null_set_sh_desc(struct
- {
- 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
- 	struct device *jrdev = ctx->jrdev;
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
- 	u32 *desc;
- 	int rem_bytes = CAAM_DESC_BYTES_MAX - AEAD_DESC_JOB_IO_LEN -
- 			ctx->adata.keylen_pad;
-@@ -136,9 +138,10 @@ static int aead_null_set_sh_desc(struct
- 
- 	/* aead_encrypt shared descriptor */
- 	desc = ctx->sh_desc_enc;
--	cnstr_shdsc_aead_null_encap(desc, &ctx->adata, ctx->authsize);
-+	cnstr_shdsc_aead_null_encap(desc, &ctx->adata, ctx->authsize,
-+				    ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	/*
- 	 * Job Descriptor and Shared Descriptors
-@@ -154,9 +157,10 @@ static int aead_null_set_sh_desc(struct
- 
- 	/* aead_decrypt shared descriptor */
- 	desc = ctx->sh_desc_dec;
--	cnstr_shdsc_aead_null_decap(desc, &ctx->adata, ctx->authsize);
-+	cnstr_shdsc_aead_null_decap(desc, &ctx->adata, ctx->authsize,
-+				    ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	return 0;
- }
-@@ -168,6 +172,7 @@ static int aead_set_sh_desc(struct crypt
- 	unsigned int ivsize = crypto_aead_ivsize(aead);
- 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
- 	struct device *jrdev = ctx->jrdev;
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
- 	u32 ctx1_iv_off = 0;
- 	u32 *desc, *nonce = NULL;
- 	u32 inl_mask;
-@@ -234,9 +239,9 @@ static int aead_set_sh_desc(struct crypt
- 	desc = ctx->sh_desc_enc;
- 	cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,
- 			       ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,
--			       false);
-+			       false, ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- skip_enc:
- 	/*
-@@ -266,9 +271,9 @@ skip_enc:
- 	desc = ctx->sh_desc_dec;
- 	cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
- 			       ctx->authsize, alg->caam.geniv, is_rfc3686,
--			       nonce, ctx1_iv_off, false);
-+			       nonce, ctx1_iv_off, false, ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	if (!alg->caam.geniv)
- 		goto skip_givenc;
-@@ -300,9 +305,9 @@ skip_enc:
- 	desc = ctx->sh_desc_enc;
- 	cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
- 				  ctx->authsize, is_rfc3686, nonce,
--				  ctx1_iv_off, false);
-+				  ctx1_iv_off, false, ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- skip_givenc:
- 	return 0;
-@@ -323,6 +328,7 @@ static int gcm_set_sh_desc(struct crypto
- {
- 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
- 	struct device *jrdev = ctx->jrdev;
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
- 	u32 *desc;
- 	int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
- 			ctx->cdata.keylen;
-@@ -344,9 +350,9 @@ static int gcm_set_sh_desc(struct crypto
- 	}
- 
- 	desc = ctx->sh_desc_enc;
--	cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ctx->authsize);
-+	cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ivsize, ctx->authsize, false);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	/*
- 	 * Job Descriptor and Shared Descriptors
-@@ -361,9 +367,9 @@ static int gcm_set_sh_desc(struct crypto
- 	}
- 
- 	desc = ctx->sh_desc_dec;
--	cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ctx->authsize);
-+	cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ivsize, ctx->authsize, false);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	return 0;
- }
-@@ -382,6 +388,7 @@ static int rfc4106_set_sh_desc(struct cr
- {
- 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
- 	struct device *jrdev = ctx->jrdev;
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
- 	u32 *desc;
- 	int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
- 			ctx->cdata.keylen;
-@@ -403,9 +410,10 @@ static int rfc4106_set_sh_desc(struct cr
- 	}
- 
- 	desc = ctx->sh_desc_enc;
--	cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ctx->authsize);
-+	cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
-+				  false);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	/*
- 	 * Job Descriptor and Shared Descriptors
-@@ -420,9 +428,10 @@ static int rfc4106_set_sh_desc(struct cr
- 	}
- 
- 	desc = ctx->sh_desc_dec;
--	cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ctx->authsize);
-+	cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
-+				  false);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	return 0;
- }
-@@ -442,6 +451,7 @@ static int rfc4543_set_sh_desc(struct cr
- {
- 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
- 	struct device *jrdev = ctx->jrdev;
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
- 	u32 *desc;
- 	int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
- 			ctx->cdata.keylen;
-@@ -463,9 +473,10 @@ static int rfc4543_set_sh_desc(struct cr
- 	}
- 
- 	desc = ctx->sh_desc_enc;
--	cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ctx->authsize);
-+	cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
-+				  false);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	/*
- 	 * Job Descriptor and Shared Descriptors
-@@ -480,9 +491,10 @@ static int rfc4543_set_sh_desc(struct cr
- 	}
- 
- 	desc = ctx->sh_desc_dec;
--	cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ctx->authsize);
-+	cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
-+				  false);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	return 0;
- }
-@@ -503,6 +515,7 @@ static int aead_setkey(struct crypto_aea
- {
- 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
- 	struct device *jrdev = ctx->jrdev;
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
- 	struct crypto_authenc_keys keys;
- 	int ret = 0;
- 
-@@ -517,6 +530,27 @@ static int aead_setkey(struct crypto_aea
- 		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
- #endif
- 
-+	/*
-+	 * If DKP is supported, use it in the shared descriptor to generate
-+	 * the split key.
-+	 */
-+	if (ctrlpriv->era >= 6) {
-+		ctx->adata.keylen = keys.authkeylen;
-+		ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
-+						      OP_ALG_ALGSEL_MASK);
-+
-+		if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
-+			goto badkey;
-+
-+		memcpy(ctx->key, keys.authkey, keys.authkeylen);
-+		memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
-+		       keys.enckeylen);
-+		dma_sync_single_for_device(jrdev, ctx->key_dma,
-+					   ctx->adata.keylen_pad +
-+					   keys.enckeylen, ctx->dir);
-+		goto skip_split_key;
-+	}
-+
- 	ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, keys.authkey,
- 			    keys.authkeylen, CAAM_MAX_KEY_SIZE -
- 			    keys.enckeylen);
-@@ -527,12 +561,14 @@ static int aead_setkey(struct crypto_aea
- 	/* postpend encryption key to auth split key */
- 	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
- 	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
--				   keys.enckeylen, DMA_TO_DEVICE);
-+				   keys.enckeylen, ctx->dir);
- #ifdef DEBUG
- 	print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
- 		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
- 		       ctx->adata.keylen_pad + keys.enckeylen, 1);
- #endif
-+
-+skip_split_key:
- 	ctx->cdata.keylen = keys.enckeylen;
- 	return aead_set_sh_desc(aead);
- badkey:
-@@ -552,7 +588,7 @@ static int gcm_setkey(struct crypto_aead
- #endif
- 
- 	memcpy(ctx->key, key, keylen);
--	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE);
-+	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, ctx->dir);
- 	ctx->cdata.keylen = keylen;
- 
- 	return gcm_set_sh_desc(aead);
-@@ -580,7 +616,7 @@ static int rfc4106_setkey(struct crypto_
- 	 */
- 	ctx->cdata.keylen = keylen - 4;
- 	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
--				   DMA_TO_DEVICE);
-+				   ctx->dir);
- 	return rfc4106_set_sh_desc(aead);
- }
- 
-@@ -606,7 +642,7 @@ static int rfc4543_setkey(struct crypto_
- 	 */
- 	ctx->cdata.keylen = keylen - 4;
- 	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
--				   DMA_TO_DEVICE);
-+				   ctx->dir);
- 	return rfc4543_set_sh_desc(aead);
- }
- 
-@@ -658,21 +694,21 @@ static int ablkcipher_setkey(struct cryp
- 	cnstr_shdsc_ablkcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686,
- 				     ctx1_iv_off);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	/* ablkcipher_decrypt shared descriptor */
- 	desc = ctx->sh_desc_dec;
- 	cnstr_shdsc_ablkcipher_decap(desc, &ctx->cdata, ivsize, is_rfc3686,
- 				     ctx1_iv_off);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	/* ablkcipher_givencrypt shared descriptor */
- 	desc = ctx->sh_desc_givenc;
- 	cnstr_shdsc_ablkcipher_givencap(desc, &ctx->cdata, ivsize, is_rfc3686,
- 					ctx1_iv_off);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_givenc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	return 0;
- }
-@@ -701,13 +737,13 @@ static int xts_ablkcipher_setkey(struct
- 	desc = ctx->sh_desc_enc;
- 	cnstr_shdsc_xts_ablkcipher_encap(desc, &ctx->cdata);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	/* xts_ablkcipher_decrypt shared descriptor */
- 	desc = ctx->sh_desc_dec;
- 	cnstr_shdsc_xts_ablkcipher_decap(desc, &ctx->cdata);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- 
- 	return 0;
- }
-@@ -987,9 +1023,6 @@ static void init_aead_job(struct aead_re
- 		append_seq_out_ptr(desc, dst_dma,
- 				   req->assoclen + req->cryptlen - authsize,
- 				   out_options);
--
--	/* REG3 = assoclen */
--	append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
- }
- 
- static void init_gcm_job(struct aead_request *req,
-@@ -1004,6 +1037,7 @@ static void init_gcm_job(struct aead_req
- 	unsigned int last;
- 
- 	init_aead_job(req, edesc, all_contig, encrypt);
-+	append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
- 
- 	/* BUG This should not be specific to generic GCM. */
- 	last = 0;
-@@ -1030,6 +1064,7 @@ static void init_authenc_job(struct aead
- 						 struct caam_aead_alg, aead);
- 	unsigned int ivsize = crypto_aead_ivsize(aead);
- 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
- 	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
- 			       OP_ALG_AAI_CTR_MOD128);
- 	const bool is_rfc3686 = alg->caam.rfc3686;
-@@ -1053,6 +1088,15 @@ static void init_authenc_job(struct aead
- 
- 	init_aead_job(req, edesc, all_contig, encrypt);
- 
-+	/*
-+	 * {REG3, DPOVRD} = assoclen, depending on whether MATH command supports
-+	 * having DPOVRD as destination.
-+	 */
-+	if (ctrlpriv->era < 3)
-+		append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
-+	else
-+		append_math_add_imm_u32(desc, DPOVRD, ZERO, IMM, req->assoclen);
-+
- 	if (ivsize && ((is_rfc3686 && encrypt) || !alg->caam.geniv))
- 		append_load_as_imm(desc, req->iv, ivsize,
- 				   LDST_CLASS_1_CCB |
-@@ -3203,9 +3247,11 @@ struct caam_crypto_alg {
- 	struct caam_alg_entry caam;
- };
- 
--static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam)
-+static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam,
-+			   bool uses_dkp)
- {
- 	dma_addr_t dma_addr;
-+	struct caam_drv_private *priv;
- 
- 	ctx->jrdev = caam_jr_alloc();
- 	if (IS_ERR(ctx->jrdev)) {
-@@ -3213,10 +3259,16 @@ static int caam_init_common(struct caam_
- 		return PTR_ERR(ctx->jrdev);
- 	}
- 
-+	priv = dev_get_drvdata(ctx->jrdev->parent);
-+	if (priv->era >= 6 && uses_dkp)
-+		ctx->dir = DMA_BIDIRECTIONAL;
-+	else
-+		ctx->dir = DMA_TO_DEVICE;
-+
- 	dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_enc,
- 					offsetof(struct caam_ctx,
- 						 sh_desc_enc_dma),
--					DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
-+					ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
- 	if (dma_mapping_error(ctx->jrdev, dma_addr)) {
- 		dev_err(ctx->jrdev, "unable to map key, shared descriptors\n");
- 		caam_jr_free(ctx->jrdev);
-@@ -3244,7 +3296,7 @@ static int caam_cra_init(struct crypto_t
- 		 container_of(alg, struct caam_crypto_alg, crypto_alg);
- 	struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
- 
--	return caam_init_common(ctx, &caam_alg->caam);
-+	return caam_init_common(ctx, &caam_alg->caam, false);
- }
- 
- static int caam_aead_init(struct crypto_aead *tfm)
-@@ -3254,14 +3306,15 @@ static int caam_aead_init(struct crypto_
- 		 container_of(alg, struct caam_aead_alg, aead);
- 	struct caam_ctx *ctx = crypto_aead_ctx(tfm);
- 
--	return caam_init_common(ctx, &caam_alg->caam);
-+	return caam_init_common(ctx, &caam_alg->caam,
-+				alg->setkey == aead_setkey);
- }
- 
- static void caam_exit_common(struct caam_ctx *ctx)
- {
- 	dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_enc_dma,
- 			       offsetof(struct caam_ctx, sh_desc_enc_dma),
--			       DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
-+			       ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
- 	caam_jr_free(ctx->jrdev);
- }
- 
---- a/drivers/crypto/caam/caamalg_desc.c
-+++ b/drivers/crypto/caam/caamalg_desc.c
-@@ -45,16 +45,16 @@ static inline void append_dec_op1(u32 *d
-  * cnstr_shdsc_aead_null_encap - IPSec ESP encapsulation shared descriptor
-  *                               (non-protocol) with no (null) encryption.
-  * @desc: pointer to buffer used for descriptor construction
-- * @adata: pointer to authentication transform definitions. Note that since a
-- *         split key is to be used, the size of the split key itself is
-- *         specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1,
-- *         SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP.
-+ * @adata: pointer to authentication transform definitions.
-+ *         A split key is required for SEC Era < 6; the size of the split key
-+ *         is specified in this case. Valid algorithm values - one of
-+ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
-+ *         with OP_ALG_AAI_HMAC_PRECOMP.
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-- *
-- * Note: Requires an MDHA split key.
-+ * @era: SEC Era
-  */
- void cnstr_shdsc_aead_null_encap(u32 * const desc, struct alginfo *adata,
--				 unsigned int icvsize)
-+				 unsigned int icvsize, int era)
- {
- 	u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd;
- 
-@@ -63,13 +63,18 @@ void cnstr_shdsc_aead_null_encap(u32 * c
- 	/* Skip if already shared */
- 	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
- 				   JUMP_COND_SHRD);
--	if (adata->key_inline)
--		append_key_as_imm(desc, adata->key_virt, adata->keylen_pad,
--				  adata->keylen, CLASS_2 | KEY_DEST_MDHA_SPLIT |
--				  KEY_ENC);
--	else
--		append_key(desc, adata->key_dma, adata->keylen, CLASS_2 |
--			   KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+	if (era < 6) {
-+		if (adata->key_inline)
-+			append_key_as_imm(desc, adata->key_virt,
-+					  adata->keylen_pad, adata->keylen,
-+					  CLASS_2 | KEY_DEST_MDHA_SPLIT |
-+					  KEY_ENC);
-+		else
-+			append_key(desc, adata->key_dma, adata->keylen,
-+				   CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+	} else {
-+		append_proto_dkp(desc, adata);
-+	}
- 	set_jump_tgt_here(desc, key_jump_cmd);
- 
- 	/* assoclen + cryptlen = seqinlen */
-@@ -121,16 +126,16 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_null_enca
-  * cnstr_shdsc_aead_null_decap - IPSec ESP decapsulation shared descriptor
-  *                               (non-protocol) with no (null) decryption.
-  * @desc: pointer to buffer used for descriptor construction
-- * @adata: pointer to authentication transform definitions. Note that since a
-- *         split key is to be used, the size of the split key itself is
-- *         specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1,
-- *         SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP.
-+ * @adata: pointer to authentication transform definitions.
-+ *         A split key is required for SEC Era < 6; the size of the split key
-+ *         is specified in this case. Valid algorithm values - one of
-+ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
-+ *         with OP_ALG_AAI_HMAC_PRECOMP.
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-- *
-- * Note: Requires an MDHA split key.
-+ * @era: SEC Era
-  */
- void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
--				 unsigned int icvsize)
-+				 unsigned int icvsize, int era)
- {
- 	u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd, *jump_cmd;
- 
-@@ -139,13 +144,18 @@ void cnstr_shdsc_aead_null_decap(u32 * c
- 	/* Skip if already shared */
- 	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
- 				   JUMP_COND_SHRD);
--	if (adata->key_inline)
--		append_key_as_imm(desc, adata->key_virt, adata->keylen_pad,
--				  adata->keylen, CLASS_2 |
--				  KEY_DEST_MDHA_SPLIT | KEY_ENC);
--	else
--		append_key(desc, adata->key_dma, adata->keylen, CLASS_2 |
--			   KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+	if (era < 6) {
-+		if (adata->key_inline)
-+			append_key_as_imm(desc, adata->key_virt,
-+					  adata->keylen_pad, adata->keylen,
-+					  CLASS_2 | KEY_DEST_MDHA_SPLIT |
-+					  KEY_ENC);
-+		else
-+			append_key(desc, adata->key_dma, adata->keylen,
-+				   CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+	} else {
-+		append_proto_dkp(desc, adata);
-+	}
- 	set_jump_tgt_here(desc, key_jump_cmd);
- 
- 	/* Class 2 operation */
-@@ -204,7 +214,7 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_null_deca
- static void init_sh_desc_key_aead(u32 * const desc,
- 				  struct alginfo * const cdata,
- 				  struct alginfo * const adata,
--				  const bool is_rfc3686, u32 *nonce)
-+				  const bool is_rfc3686, u32 *nonce, int era)
- {
- 	u32 *key_jump_cmd;
- 	unsigned int enckeylen = cdata->keylen;
-@@ -224,13 +234,18 @@ static void init_sh_desc_key_aead(u32 *
- 	if (is_rfc3686)
- 		enckeylen -= CTR_RFC3686_NONCE_SIZE;
- 
--	if (adata->key_inline)
--		append_key_as_imm(desc, adata->key_virt, adata->keylen_pad,
--				  adata->keylen, CLASS_2 |
--				  KEY_DEST_MDHA_SPLIT | KEY_ENC);
--	else
--		append_key(desc, adata->key_dma, adata->keylen, CLASS_2 |
--			   KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+	if (era < 6) {
-+		if (adata->key_inline)
-+			append_key_as_imm(desc, adata->key_virt,
-+					  adata->keylen_pad, adata->keylen,
-+					  CLASS_2 | KEY_DEST_MDHA_SPLIT |
-+					  KEY_ENC);
-+		else
-+			append_key(desc, adata->key_dma, adata->keylen,
-+				   CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+	} else {
-+		append_proto_dkp(desc, adata);
-+	}
- 
- 	if (cdata->key_inline)
- 		append_key_as_imm(desc, cdata->key_virt, enckeylen,
-@@ -261,26 +276,27 @@ static void init_sh_desc_key_aead(u32 *
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
-  *         with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128.
-- * @adata: pointer to authentication transform definitions. Note that since a
-- *         split key is to be used, the size of the split key itself is
-- *         specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1,
-- *         SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP.
-+ * @adata: pointer to authentication transform definitions.
-+ *         A split key is required for SEC Era < 6; the size of the split key
-+ *         is specified in this case. Valid algorithm values - one of
-+ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
-+ *         with OP_ALG_AAI_HMAC_PRECOMP.
-  * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-  * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
-  * @nonce: pointer to rfc3686 nonce
-  * @ctx1_iv_off: IV offset in CONTEXT1 register
-  * @is_qi: true when called from caam/qi
-- *
-- * Note: Requires an MDHA split key.
-+ * @era: SEC Era
-  */
- void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
- 			    struct alginfo *adata, unsigned int ivsize,
- 			    unsigned int icvsize, const bool is_rfc3686,
--			    u32 *nonce, const u32 ctx1_iv_off, const bool is_qi)
-+			    u32 *nonce, const u32 ctx1_iv_off, const bool is_qi,
-+			    int era)
- {
- 	/* Note: Context registers are saved. */
--	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
-+	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era);
- 
- 	/* Class 2 operation */
- 	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
-@@ -306,8 +322,13 @@ void cnstr_shdsc_aead_encap(u32 * const
- 	}
- 
- 	/* Read and write assoclen bytes */
--	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
--	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
-+	if (is_qi || era < 3) {
-+		append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
-+		append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
-+	} else {
-+		append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
-+		append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
-+	}
- 
- 	/* Skip assoc data */
- 	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
-@@ -350,27 +371,27 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_encap);
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
-  *         with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128.
-- * @adata: pointer to authentication transform definitions. Note that since a
-- *         split key is to be used, the size of the split key itself is
-- *         specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1,
-- *         SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP.
-+ * @adata: pointer to authentication transform definitions.
-+ *         A split key is required for SEC Era < 6; the size of the split key
-+ *         is specified in this case. Valid algorithm values - one of
-+ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
-+ *         with OP_ALG_AAI_HMAC_PRECOMP.
-  * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-  * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
-  * @nonce: pointer to rfc3686 nonce
-  * @ctx1_iv_off: IV offset in CONTEXT1 register
-  * @is_qi: true when called from caam/qi
-- *
-- * Note: Requires an MDHA split key.
-+ * @era: SEC Era
-  */
- void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
- 			    struct alginfo *adata, unsigned int ivsize,
- 			    unsigned int icvsize, const bool geniv,
- 			    const bool is_rfc3686, u32 *nonce,
--			    const u32 ctx1_iv_off, const bool is_qi)
-+			    const u32 ctx1_iv_off, const bool is_qi, int era)
- {
- 	/* Note: Context registers are saved. */
--	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
-+	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era);
- 
- 	/* Class 2 operation */
- 	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
-@@ -397,11 +418,23 @@ void cnstr_shdsc_aead_decap(u32 * const
- 	}
- 
- 	/* Read and write assoclen bytes */
--	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
--	if (geniv)
--		append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM, ivsize);
--	else
--		append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
-+	if (is_qi || era < 3) {
-+		append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
-+		if (geniv)
-+			append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM,
-+						ivsize);
-+		else
-+			append_math_add(desc, VARSEQOUTLEN, ZERO, REG3,
-+					CAAM_CMD_SZ);
-+	} else {
-+		append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
-+		if (geniv)
-+			append_math_add_imm_u32(desc, VARSEQOUTLEN, DPOVRD, IMM,
-+						ivsize);
-+		else
-+			append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD,
-+					CAAM_CMD_SZ);
-+	}
- 
- 	/* Skip assoc data */
- 	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
-@@ -456,29 +489,29 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_decap);
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
-  *         with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128.
-- * @adata: pointer to authentication transform definitions. Note that since a
-- *         split key is to be used, the size of the split key itself is
-- *         specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1,
-- *         SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP.
-+ * @adata: pointer to authentication transform definitions.
-+ *         A split key is required for SEC Era < 6; the size of the split key
-+ *         is specified in this case. Valid algorithm values - one of
-+ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
-+ *         with OP_ALG_AAI_HMAC_PRECOMP.
-  * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-  * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
-  * @nonce: pointer to rfc3686 nonce
-  * @ctx1_iv_off: IV offset in CONTEXT1 register
-  * @is_qi: true when called from caam/qi
-- *
-- * Note: Requires an MDHA split key.
-+ * @era: SEC Era
-  */
- void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
- 			       struct alginfo *adata, unsigned int ivsize,
- 			       unsigned int icvsize, const bool is_rfc3686,
- 			       u32 *nonce, const u32 ctx1_iv_off,
--			       const bool is_qi)
-+			       const bool is_qi, int era)
- {
- 	u32 geniv, moveiv;
- 
- 	/* Note: Context registers are saved. */
--	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
-+	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era);
- 
- 	if (is_qi) {
- 		u32 *wait_load_cmd;
-@@ -528,8 +561,13 @@ copy_iv:
- 			 OP_ALG_ENCRYPT);
- 
- 	/* Read and write assoclen bytes */
--	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
--	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
-+	if (is_qi || era < 3) {
-+		append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
-+		append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
-+	} else {
-+		append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
-+		append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
-+	}
- 
- 	/* Skip assoc data */
- 	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
-@@ -583,14 +621,431 @@ copy_iv:
- EXPORT_SYMBOL(cnstr_shdsc_aead_givencap);
- 
- /**
-+ * cnstr_shdsc_tls_encap - tls encapsulation shared descriptor
-+ * @desc: pointer to buffer used for descriptor construction
-+ * @cdata: pointer to block cipher transform definitions
-+ *         Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed
-+ *         with OP_ALG_AAI_CBC
-+ * @adata: pointer to authentication transform definitions.
-+ *         A split key is required for SEC Era < 6; the size of the split key
-+ *         is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1
-+ *         ANDed with OP_ALG_AAI_HMAC_PRECOMP.
-+ * @assoclen: associated data length
-+ * @ivsize: initialization vector size
-+ * @authsize: authentication data size
-+ * @blocksize: block cipher size
-+ * @era: SEC Era
-+ */
-+void cnstr_shdsc_tls_encap(u32 * const desc, struct alginfo *cdata,
-+			   struct alginfo *adata, unsigned int assoclen,
-+			   unsigned int ivsize, unsigned int authsize,
-+			   unsigned int blocksize, int era)
-+{
-+	u32 *key_jump_cmd, *zero_payload_jump_cmd;
-+	u32 genpad, idx_ld_datasz, idx_ld_pad, stidx;
-+
-+	/*
-+	 * Compute the index (in bytes) for the LOAD with destination of
-+	 * Class 1 Data Size Register and for the LOAD that generates padding
-+	 */
-+	if (adata->key_inline) {
-+		idx_ld_datasz = DESC_TLS10_ENC_LEN + adata->keylen_pad +
-+				cdata->keylen - 4 * CAAM_CMD_SZ;
-+		idx_ld_pad = DESC_TLS10_ENC_LEN + adata->keylen_pad +
-+			     cdata->keylen - 2 * CAAM_CMD_SZ;
-+	} else {
-+		idx_ld_datasz = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ -
-+				4 * CAAM_CMD_SZ;
-+		idx_ld_pad = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ -
-+			     2 * CAAM_CMD_SZ;
-+	}
-+
-+	stidx = 1 << HDR_START_IDX_SHIFT;
-+	init_sh_desc(desc, HDR_SHARE_SERIAL | stidx);
-+
-+	/* skip key loading if they are loaded due to sharing */
-+	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
-+				   JUMP_COND_SHRD);
-+
-+	if (era < 6) {
-+		if (adata->key_inline)
-+			append_key_as_imm(desc, adata->key_virt,
-+					  adata->keylen_pad, adata->keylen,
-+					  CLASS_2 | KEY_DEST_MDHA_SPLIT |
-+					  KEY_ENC);
-+		else
-+			append_key(desc, adata->key_dma, adata->keylen,
-+				   CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+	} else {
-+		append_proto_dkp(desc, adata);
-+	}
-+
-+	if (cdata->key_inline)
-+		append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
-+				  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
-+	else
-+		append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
-+			   KEY_DEST_CLASS_REG);
-+
-+	set_jump_tgt_here(desc, key_jump_cmd);
-+
-+	/* class 2 operation */
-+	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
-+			 OP_ALG_ENCRYPT);
-+	/* class 1 operation */
-+	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
-+			 OP_ALG_ENCRYPT);
-+
-+	/* payloadlen = input data length - (assoclen + ivlen) */
-+	append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, assoclen + ivsize);
-+
-+	/* math1 = payloadlen + icvlen */
-+	append_math_add_imm_u32(desc, REG1, REG0, IMM, authsize);
-+
-+	/* padlen = block_size - math1 % block_size */
-+	append_math_and_imm_u32(desc, REG3, REG1, IMM, blocksize - 1);
-+	append_math_sub_imm_u32(desc, REG2, IMM, REG3, blocksize);
-+
-+	/* cryptlen = payloadlen + icvlen + padlen */
-+	append_math_add(desc, VARSEQOUTLEN, REG1, REG2, 4);
-+
-+	/*
-+	 * update immediate data with the padding length value
-+	 * for the LOAD in the class 1 data size register.
-+	 */
-+	append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 |
-+			(idx_ld_datasz << MOVE_OFFSET_SHIFT) | 7);
-+	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF |
-+			(idx_ld_datasz << MOVE_OFFSET_SHIFT) | 8);
-+
-+	/* overwrite PL field for the padding iNFO FIFO entry  */
-+	append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 |
-+			(idx_ld_pad << MOVE_OFFSET_SHIFT) | 7);
-+	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF |
-+			(idx_ld_pad << MOVE_OFFSET_SHIFT) | 8);
-+
-+	/* store encrypted payload, icv and padding */
-+	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF);
-+
-+	/* if payload length is zero, jump to zero-payload commands */
-+	append_math_add(desc, VARSEQINLEN, ZERO, REG0, 4);
-+	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
-+					    JUMP_COND_MATH_Z);
-+
-+	/* load iv in context1 */
-+	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX |
-+		   LDST_CLASS_1_CCB | ivsize);
-+
-+	/* read assoc for authentication */
-+	append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 |
-+			     FIFOLD_TYPE_MSG);
-+	/* insnoop payload */
-+	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLD_TYPE_MSG |
-+			     FIFOLD_TYPE_LAST2 | FIFOLDST_VLF);
-+
-+	/* jump the zero-payload commands */
-+	append_jump(desc, JUMP_TEST_ALL | 3);
-+
-+	/* zero-payload commands */
-+	set_jump_tgt_here(desc, zero_payload_jump_cmd);
-+
-+	/* load iv in context1 */
-+	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX |
-+		   LDST_CLASS_1_CCB | ivsize);
-+
-+	/* assoc data is the only data for authentication */
-+	append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 |
-+			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2);
-+
-+	/* send icv to encryption */
-+	append_move(desc, MOVE_SRC_CLASS2CTX | MOVE_DEST_CLASS1INFIFO |
-+		    authsize);
-+
-+	/* update class 1 data size register with padding length */
-+	append_load_imm_u32(desc, 0, LDST_CLASS_1_CCB |
-+			    LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
-+
-+	/* generate padding and send it to encryption */
-+	genpad = NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_LC1 | NFIFOENTRY_FC1 |
-+	      NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_PTYPE_N;
-+	append_load_imm_u32(desc, genpad, LDST_CLASS_IND_CCB |
-+			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "tls enc shdesc@" __stringify(__LINE__) ": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
-+		       desc_bytes(desc), 1);
-+#endif
-+}
-+EXPORT_SYMBOL(cnstr_shdsc_tls_encap);
-+
-+/**
-+ * cnstr_shdsc_tls_decap - tls decapsulation shared descriptor
-+ * @desc: pointer to buffer used for descriptor construction
-+ * @cdata: pointer to block cipher transform definitions
-+ *         Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed
-+ *         with OP_ALG_AAI_CBC
-+ * @adata: pointer to authentication transform definitions.
-+ *         A split key is required for SEC Era < 6; the size of the split key
-+ *         is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1
-+ *         ANDed with OP_ALG_AAI_HMAC_PRECOMP.
-+ * @assoclen: associated data length
-+ * @ivsize: initialization vector size
-+ * @authsize: authentication data size
-+ * @blocksize: block cipher size
-+ * @era: SEC Era
-+ */
-+void cnstr_shdsc_tls_decap(u32 * const desc, struct alginfo *cdata,
-+			   struct alginfo *adata, unsigned int assoclen,
-+			   unsigned int ivsize, unsigned int authsize,
-+			   unsigned int blocksize, int era)
-+{
-+	u32 stidx, jumpback;
-+	u32 *key_jump_cmd, *zero_payload_jump_cmd, *skip_zero_jump_cmd;
-+	/*
-+	 * Pointer Size bool determines the size of address pointers.
-+	 * false - Pointers fit in one 32-bit word.
-+	 * true - Pointers fit in two 32-bit words.
-+	 */
-+	static const bool ps = (CAAM_PTR_SZ != CAAM_CMD_SZ);
-+
-+	stidx = 1 << HDR_START_IDX_SHIFT;
-+	init_sh_desc(desc, HDR_SHARE_SERIAL | stidx);
-+
-+	/* skip key loading if they are loaded due to sharing */
-+	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
-+				   JUMP_COND_SHRD);
-+
-+	if (era < 6)
-+		append_key(desc, adata->key_dma, adata->keylen, CLASS_2 |
-+			   KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+	else
-+		append_proto_dkp(desc, adata);
-+
-+	append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
-+		   KEY_DEST_CLASS_REG);
-+
-+	set_jump_tgt_here(desc, key_jump_cmd);
-+
-+	/* class 2 operation */
-+	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
-+			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
-+	/* class 1 operation */
-+	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
-+			 OP_ALG_DECRYPT);
-+
-+	/* VSIL = input data length - 2 * block_size */
-+	append_math_sub_imm_u32(desc, VARSEQINLEN, SEQINLEN, IMM, 2 *
-+				blocksize);
-+
-+	/*
-+	 * payloadlen + icvlen + padlen = input data length - (assoclen +
-+	 * ivsize)
-+	 */
-+	append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, assoclen + ivsize);
-+
-+	/* skip data to the last but one cipher block */
-+	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | LDST_VLF);
-+
-+	/* load iv for the last cipher block */
-+	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX |
-+		   LDST_CLASS_1_CCB | ivsize);
-+
-+	/* read last cipher block */
-+	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG |
-+			     FIFOLD_TYPE_LAST1 | blocksize);
-+
-+	/* move decrypted block into math0 and math1 */
-+	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO | MOVE_DEST_MATH0 |
-+		    blocksize);
-+
-+	/* reset AES CHA */
-+	append_load_imm_u32(desc, CCTRL_RESET_CHA_AESA, LDST_CLASS_IND_CCB |
-+			    LDST_SRCDST_WORD_CHACTRL | LDST_IMM);
-+
-+	/* rewind input sequence */
-+	append_seq_in_ptr_intlen(desc, 0, 65535, SQIN_RTO);
-+
-+	/* key1 is in decryption form */
-+	append_operation(desc, cdata->algtype | OP_ALG_AAI_DK |
-+			 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
-+
-+	/* load iv in context1 */
-+	append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_1_CCB |
-+		   LDST_SRCDST_WORD_CLASS_CTX | ivsize);
-+
-+	/* read sequence number */
-+	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG);
-+	/* load Type, Version and Len fields in math0 */
-+	append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_DECO |
-+		   LDST_SRCDST_WORD_DECO_MATH0 | (3 << LDST_OFFSET_SHIFT) | 5);
-+
-+	/* compute (padlen - 1) */
-+	append_math_and_imm_u64(desc, REG1, REG1, IMM, 255);
-+
-+	/* math2 = icvlen + (padlen - 1) + 1 */
-+	append_math_add_imm_u32(desc, REG2, REG1, IMM, authsize + 1);
-+
-+	append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1);
-+
-+	/* VSOL = payloadlen + icvlen + padlen */
-+	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, 4);
-+
-+	if (caam_little_end)
-+		append_moveb(desc, MOVE_WAITCOMP |
-+			     MOVE_SRC_MATH0 | MOVE_DEST_MATH0 | 8);
-+
-+	/* update Len field */
-+	append_math_sub(desc, REG0, REG0, REG2, 8);
-+
-+	/* store decrypted payload, icv and padding */
-+	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF);
-+
-+	/* VSIL = (payloadlen + icvlen + padlen) - (icvlen + padlen)*/
-+	append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4);
-+
-+	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
-+					    JUMP_COND_MATH_Z);
-+
-+	/* send Type, Version and Len(pre ICV) fields to authentication */
-+	append_move(desc, MOVE_WAITCOMP |
-+		    MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO |
-+		    (3 << MOVE_OFFSET_SHIFT) | 5);
-+
-+	/* outsnooping payload */
-+	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
-+			     FIFOLD_TYPE_MSG1OUT2 | FIFOLD_TYPE_LAST2 |
-+			     FIFOLDST_VLF);
-+	skip_zero_jump_cmd = append_jump(desc, JUMP_TEST_ALL | 2);
-+
-+	set_jump_tgt_here(desc, zero_payload_jump_cmd);
-+	/* send Type, Version and Len(pre ICV) fields to authentication */
-+	append_move(desc, MOVE_WAITCOMP | MOVE_AUX_LS |
-+		    MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO |
-+		    (3 << MOVE_OFFSET_SHIFT) | 5);
-+
-+	set_jump_tgt_here(desc, skip_zero_jump_cmd);
-+	append_math_add(desc, VARSEQINLEN, ZERO, REG2, 4);
-+
-+	/* load icvlen and padlen */
-+	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG |
-+			     FIFOLD_TYPE_LAST1 | FIFOLDST_VLF);
-+
-+	/* VSIL = (payloadlen + icvlen + padlen) - icvlen + padlen */
-+	append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4);
-+
-+	/*
-+	 * Start a new input sequence using the SEQ OUT PTR command options,
-+	 * pointer and length used when the current output sequence was defined.
-+	 */
-+	if (ps) {
-+		/*
-+		 * Move the lower 32 bits of Shared Descriptor address, the
-+		 * SEQ OUT PTR command, Output Pointer (2 words) and
-+		 * Output Length into math registers.
-+		 */
-+		if (caam_little_end)
-+			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF |
-+				    MOVE_DEST_MATH0 |
-+				    (55 * 4 << MOVE_OFFSET_SHIFT) | 20);
-+		else
-+			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF |
-+				    MOVE_DEST_MATH0 |
-+				    (54 * 4 << MOVE_OFFSET_SHIFT) | 20);
-+
-+		/* Transform SEQ OUT PTR command in SEQ IN PTR command */
-+		append_math_and_imm_u32(desc, REG0, REG0, IMM,
-+					~(CMD_SEQ_IN_PTR ^ CMD_SEQ_OUT_PTR));
-+		/* Append a JUMP command after the copied fields */
-+		jumpback = CMD_JUMP | (char)-9;
-+		append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM |
-+				    LDST_SRCDST_WORD_DECO_MATH2 |
-+				    (4 << LDST_OFFSET_SHIFT));
-+		append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1);
-+		/* Move the updated fields back to the Job Descriptor */
-+		if (caam_little_end)
-+			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 |
-+				    MOVE_DEST_DESCBUF |
-+				    (55 * 4 << MOVE_OFFSET_SHIFT) | 24);
-+		else
-+			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 |
-+				    MOVE_DEST_DESCBUF |
-+				    (54 * 4 << MOVE_OFFSET_SHIFT) | 24);
-+
-+		/*
-+		 * Read the new SEQ IN PTR command, Input Pointer, Input Length
-+		 * and then jump back to the next command from the
-+		 * Shared Descriptor.
-+		 */
-+		append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 6);
-+	} else {
-+		/*
-+		 * Move the SEQ OUT PTR command, Output Pointer (1 word) and
-+		 * Output Length into math registers.
-+		 */
-+		if (caam_little_end)
-+			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF |
-+				    MOVE_DEST_MATH0 |
-+				    (54 * 4 << MOVE_OFFSET_SHIFT) | 12);
-+		else
-+			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF |
-+				    MOVE_DEST_MATH0 |
-+				    (53 * 4 << MOVE_OFFSET_SHIFT) | 12);
-+
-+		/* Transform SEQ OUT PTR command in SEQ IN PTR command */
-+		append_math_and_imm_u64(desc, REG0, REG0, IMM,
-+					~(((u64)(CMD_SEQ_IN_PTR ^
-+						 CMD_SEQ_OUT_PTR)) << 32));
-+		/* Append a JUMP command after the copied fields */
-+		jumpback = CMD_JUMP | (char)-7;
-+		append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM |
-+				    LDST_SRCDST_WORD_DECO_MATH1 |
-+				    (4 << LDST_OFFSET_SHIFT));
-+		append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1);
-+		/* Move the updated fields back to the Job Descriptor */
-+		if (caam_little_end)
-+			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 |
-+				    MOVE_DEST_DESCBUF |
-+				    (54 * 4 << MOVE_OFFSET_SHIFT) | 16);
-+		else
-+			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 |
-+				    MOVE_DEST_DESCBUF |
-+				    (53 * 4 << MOVE_OFFSET_SHIFT) | 16);
-+
-+		/*
-+		 * Read the new SEQ IN PTR command, Input Pointer, Input Length
-+		 * and then jump back to the next command from the
-+		 * Shared Descriptor.
-+		 */
-+		 append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 5);
-+	}
-+
-+	/* skip payload */
-+	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | FIFOLDST_VLF);
-+	/* check icv */
-+	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_ICV |
-+			     FIFOLD_TYPE_LAST2 | authsize);
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "tls dec shdesc@" __stringify(__LINE__) ": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
-+		       desc_bytes(desc), 1);
-+#endif
-+}
-+EXPORT_SYMBOL(cnstr_shdsc_tls_decap);
-+
-+/**
-  * cnstr_shdsc_gcm_encap - gcm encapsulation shared descriptor
-  * @desc: pointer to buffer used for descriptor construction
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
-+ * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-+ * @is_qi: true when called from caam/qi
-  */
- void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
--			   unsigned int icvsize)
-+			   unsigned int ivsize, unsigned int icvsize,
-+			   const bool is_qi)
- {
- 	u32 *key_jump_cmd, *zero_payload_jump_cmd, *zero_assoc_jump_cmd1,
- 	    *zero_assoc_jump_cmd2;
-@@ -612,11 +1067,35 @@ void cnstr_shdsc_gcm_encap(u32 * const d
- 	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
- 			 OP_ALG_ENCRYPT);
- 
-+	if (is_qi) {
-+		u32 *wait_load_cmd;
-+
-+		/* REG3 = assoclen */
-+		append_seq_load(desc, 4, LDST_CLASS_DECO |
-+				LDST_SRCDST_WORD_DECO_MATH3 |
-+				(4 << LDST_OFFSET_SHIFT));
-+
-+		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
-+					    JUMP_COND_CALM | JUMP_COND_NCP |
-+					    JUMP_COND_NOP | JUMP_COND_NIP |
-+					    JUMP_COND_NIFP);
-+		set_jump_tgt_here(desc, wait_load_cmd);
-+
-+		append_math_sub_imm_u32(desc, VARSEQOUTLEN, SEQINLEN, IMM,
-+					ivsize);
-+	} else {
-+		append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG0,
-+				CAAM_CMD_SZ);
-+	}
-+
- 	/* if assoclen + cryptlen is ZERO, skip to ICV write */
--	append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
- 	zero_assoc_jump_cmd2 = append_jump(desc, JUMP_TEST_ALL |
- 						 JUMP_COND_MATH_Z);
- 
-+	if (is_qi)
-+		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
-+				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
-+
- 	/* if assoclen is ZERO, skip reading the assoc data */
- 	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
- 	zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL |
-@@ -648,8 +1127,11 @@ void cnstr_shdsc_gcm_encap(u32 * const d
- 	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
- 			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
- 
--	/* jump the zero-payload commands */
--	append_jump(desc, JUMP_TEST_ALL | 2);
-+	/* jump to ICV writing */
-+	if (is_qi)
-+		append_jump(desc, JUMP_TEST_ALL | 4);
-+	else
-+		append_jump(desc, JUMP_TEST_ALL | 2);
- 
- 	/* zero-payload commands */
- 	set_jump_tgt_here(desc, zero_payload_jump_cmd);
-@@ -657,10 +1139,18 @@ void cnstr_shdsc_gcm_encap(u32 * const d
- 	/* read assoc data */
- 	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
- 			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST1);
-+	if (is_qi)
-+		/* jump to ICV writing */
-+		append_jump(desc, JUMP_TEST_ALL | 2);
- 
- 	/* There is no input data */
- 	set_jump_tgt_here(desc, zero_assoc_jump_cmd2);
- 
-+	if (is_qi)
-+		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
-+				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 |
-+				     FIFOLD_TYPE_LAST1);
-+
- 	/* write ICV */
- 	append_seq_store(desc, icvsize, LDST_CLASS_1_CCB |
- 			 LDST_SRCDST_BYTE_CONTEXT);
-@@ -677,10 +1167,13 @@ EXPORT_SYMBOL(cnstr_shdsc_gcm_encap);
-  * @desc: pointer to buffer used for descriptor construction
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
-+ * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-+ * @is_qi: true when called from caam/qi
-  */
- void cnstr_shdsc_gcm_decap(u32 * const desc, struct alginfo *cdata,
--			   unsigned int icvsize)
-+			   unsigned int ivsize, unsigned int icvsize,
-+			   const bool is_qi)
- {
- 	u32 *key_jump_cmd, *zero_payload_jump_cmd, *zero_assoc_jump_cmd1;
- 
-@@ -701,6 +1194,24 @@ void cnstr_shdsc_gcm_decap(u32 * const d
- 	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
- 			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
- 
-+	if (is_qi) {
-+		u32 *wait_load_cmd;
-+
-+		/* REG3 = assoclen */
-+		append_seq_load(desc, 4, LDST_CLASS_DECO |
-+				LDST_SRCDST_WORD_DECO_MATH3 |
-+				(4 << LDST_OFFSET_SHIFT));
-+
-+		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
-+					    JUMP_COND_CALM | JUMP_COND_NCP |
-+					    JUMP_COND_NOP | JUMP_COND_NIP |
-+					    JUMP_COND_NIFP);
-+		set_jump_tgt_here(desc, wait_load_cmd);
-+
-+		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
-+				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
-+	}
-+
- 	/* if assoclen is ZERO, skip reading the assoc data */
- 	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
- 	zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL |
-@@ -753,10 +1264,13 @@ EXPORT_SYMBOL(cnstr_shdsc_gcm_decap);
-  * @desc: pointer to buffer used for descriptor construction
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
-+ * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-+ * @is_qi: true when called from caam/qi
-  */
- void cnstr_shdsc_rfc4106_encap(u32 * const desc, struct alginfo *cdata,
--			       unsigned int icvsize)
-+			       unsigned int ivsize, unsigned int icvsize,
-+			       const bool is_qi)
- {
- 	u32 *key_jump_cmd;
- 
-@@ -777,7 +1291,29 @@ void cnstr_shdsc_rfc4106_encap(u32 * con
- 	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
- 			 OP_ALG_ENCRYPT);
- 
--	append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, 8);
-+	if (is_qi) {
-+		u32 *wait_load_cmd;
-+
-+		/* REG3 = assoclen */
-+		append_seq_load(desc, 4, LDST_CLASS_DECO |
-+				LDST_SRCDST_WORD_DECO_MATH3 |
-+				(4 << LDST_OFFSET_SHIFT));
-+
-+		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
-+					    JUMP_COND_CALM | JUMP_COND_NCP |
-+					    JUMP_COND_NOP | JUMP_COND_NIP |
-+					    JUMP_COND_NIFP);
-+		set_jump_tgt_here(desc, wait_load_cmd);
-+
-+		/* Read salt and IV */
-+		append_fifo_load_as_imm(desc, (void *)(cdata->key_virt +
-+					cdata->keylen), 4, FIFOLD_CLASS_CLASS1 |
-+					FIFOLD_TYPE_IV);
-+		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
-+				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
-+	}
-+
-+	append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, ivsize);
- 	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
- 
- 	/* Read assoc data */
-@@ -785,7 +1321,7 @@ void cnstr_shdsc_rfc4106_encap(u32 * con
- 			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
- 
- 	/* Skip IV */
--	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_SKIP);
-+	append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_SKIP);
- 
- 	/* Will read cryptlen bytes */
- 	append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
-@@ -824,10 +1360,13 @@ EXPORT_SYMBOL(cnstr_shdsc_rfc4106_encap)
-  * @desc: pointer to buffer used for descriptor construction
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
-+ * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-+ * @is_qi: true when called from caam/qi
-  */
- void cnstr_shdsc_rfc4106_decap(u32 * const desc, struct alginfo *cdata,
--			       unsigned int icvsize)
-+			       unsigned int ivsize, unsigned int icvsize,
-+			       const bool is_qi)
- {
- 	u32 *key_jump_cmd;
- 
-@@ -849,7 +1388,29 @@ void cnstr_shdsc_rfc4106_decap(u32 * con
- 	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
- 			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
- 
--	append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, 8);
-+	if (is_qi) {
-+		u32 *wait_load_cmd;
-+
-+		/* REG3 = assoclen */
-+		append_seq_load(desc, 4, LDST_CLASS_DECO |
-+				LDST_SRCDST_WORD_DECO_MATH3 |
-+				(4 << LDST_OFFSET_SHIFT));
-+
-+		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
-+					    JUMP_COND_CALM | JUMP_COND_NCP |
-+					    JUMP_COND_NOP | JUMP_COND_NIP |
-+					    JUMP_COND_NIFP);
-+		set_jump_tgt_here(desc, wait_load_cmd);
-+
-+		/* Read salt and IV */
-+		append_fifo_load_as_imm(desc, (void *)(cdata->key_virt +
-+					cdata->keylen), 4, FIFOLD_CLASS_CLASS1 |
-+					FIFOLD_TYPE_IV);
-+		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
-+				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
-+	}
-+
-+	append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, ivsize);
- 	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
- 
- 	/* Read assoc data */
-@@ -857,7 +1418,7 @@ void cnstr_shdsc_rfc4106_decap(u32 * con
- 			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
- 
- 	/* Skip IV */
--	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_SKIP);
-+	append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_SKIP);
- 
- 	/* Will read cryptlen bytes */
- 	append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG3, CAAM_CMD_SZ);
-@@ -896,10 +1457,13 @@ EXPORT_SYMBOL(cnstr_shdsc_rfc4106_decap)
-  * @desc: pointer to buffer used for descriptor construction
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
-+ * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-+ * @is_qi: true when called from caam/qi
-  */
- void cnstr_shdsc_rfc4543_encap(u32 * const desc, struct alginfo *cdata,
--			       unsigned int icvsize)
-+			       unsigned int ivsize, unsigned int icvsize,
-+			       const bool is_qi)
- {
- 	u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd;
- 
-@@ -920,6 +1484,18 @@ void cnstr_shdsc_rfc4543_encap(u32 * con
- 	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
- 			 OP_ALG_ENCRYPT);
- 
-+	if (is_qi) {
-+		/* assoclen is not needed, skip it */
-+		append_seq_fifo_load(desc, 4, FIFOLD_CLASS_SKIP);
-+
-+		/* Read salt and IV */
-+		append_fifo_load_as_imm(desc, (void *)(cdata->key_virt +
-+					cdata->keylen), 4, FIFOLD_CLASS_CLASS1 |
-+					FIFOLD_TYPE_IV);
-+		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
-+				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
-+	}
-+
- 	/* assoclen + cryptlen = seqinlen */
- 	append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
- 
-@@ -966,10 +1542,13 @@ EXPORT_SYMBOL(cnstr_shdsc_rfc4543_encap)
-  * @desc: pointer to buffer used for descriptor construction
-  * @cdata: pointer to block cipher transform definitions
-  *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
-+ * @ivsize: initialization vector size
-  * @icvsize: integrity check value (ICV) size (truncated or full)
-+ * @is_qi: true when called from caam/qi
-  */
- void cnstr_shdsc_rfc4543_decap(u32 * const desc, struct alginfo *cdata,
--			       unsigned int icvsize)
-+			       unsigned int ivsize, unsigned int icvsize,
-+			       const bool is_qi)
- {
- 	u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd;
- 
-@@ -990,6 +1569,18 @@ void cnstr_shdsc_rfc4543_decap(u32 * con
- 	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
- 			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
- 
-+	if (is_qi) {
-+		/* assoclen is not needed, skip it */
-+		append_seq_fifo_load(desc, 4, FIFOLD_CLASS_SKIP);
-+
-+		/* Read salt and IV */
-+		append_fifo_load_as_imm(desc, (void *)(cdata->key_virt +
-+					cdata->keylen), 4, FIFOLD_CLASS_CLASS1 |
-+					FIFOLD_TYPE_IV);
-+		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
-+				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
-+	}
-+
- 	/* assoclen + cryptlen = seqoutlen */
- 	append_math_sub(desc, REG3, SEQOUTLEN, REG0, CAAM_CMD_SZ);
- 
-@@ -1075,7 +1666,7 @@ void cnstr_shdsc_ablkcipher_encap(u32 *
- 
- 	/* Load nonce into CONTEXT1 reg */
- 	if (is_rfc3686) {
--		u8 *nonce = cdata->key_virt + cdata->keylen;
-+		const u8 *nonce = cdata->key_virt + cdata->keylen;
- 
- 		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
- 				   LDST_CLASS_IND_CCB |
-@@ -1140,7 +1731,7 @@ void cnstr_shdsc_ablkcipher_decap(u32 *
- 
- 	/* Load nonce into CONTEXT1 reg */
- 	if (is_rfc3686) {
--		u8 *nonce = cdata->key_virt + cdata->keylen;
-+		const u8 *nonce = cdata->key_virt + cdata->keylen;
- 
- 		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
- 				   LDST_CLASS_IND_CCB |
-@@ -1209,7 +1800,7 @@ void cnstr_shdsc_ablkcipher_givencap(u32
- 
- 	/* Load Nonce into CONTEXT1 reg */
- 	if (is_rfc3686) {
--		u8 *nonce = cdata->key_virt + cdata->keylen;
-+		const u8 *nonce = cdata->key_virt + cdata->keylen;
- 
- 		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
- 				   LDST_CLASS_IND_CCB |
---- a/drivers/crypto/caam/caamalg_desc.h
-+++ b/drivers/crypto/caam/caamalg_desc.h
-@@ -17,6 +17,9 @@
- #define DESC_QI_AEAD_DEC_LEN		(DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ)
- #define DESC_QI_AEAD_GIVENC_LEN		(DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ)
- 
-+#define DESC_TLS_BASE			(4 * CAAM_CMD_SZ)
-+#define DESC_TLS10_ENC_LEN		(DESC_TLS_BASE + 29 * CAAM_CMD_SZ)
-+
- /* Note: Nonce is counted in cdata.keylen */
- #define DESC_AEAD_CTR_RFC3686_LEN	(4 * CAAM_CMD_SZ)
- 
-@@ -27,14 +30,20 @@
- #define DESC_GCM_BASE			(3 * CAAM_CMD_SZ)
- #define DESC_GCM_ENC_LEN		(DESC_GCM_BASE + 16 * CAAM_CMD_SZ)
- #define DESC_GCM_DEC_LEN		(DESC_GCM_BASE + 12 * CAAM_CMD_SZ)
-+#define DESC_QI_GCM_ENC_LEN		(DESC_GCM_ENC_LEN + 6 * CAAM_CMD_SZ)
-+#define DESC_QI_GCM_DEC_LEN		(DESC_GCM_DEC_LEN + 3 * CAAM_CMD_SZ)
- 
- #define DESC_RFC4106_BASE		(3 * CAAM_CMD_SZ)
- #define DESC_RFC4106_ENC_LEN		(DESC_RFC4106_BASE + 13 * CAAM_CMD_SZ)
- #define DESC_RFC4106_DEC_LEN		(DESC_RFC4106_BASE + 13 * CAAM_CMD_SZ)
-+#define DESC_QI_RFC4106_ENC_LEN		(DESC_RFC4106_ENC_LEN + 5 * CAAM_CMD_SZ)
-+#define DESC_QI_RFC4106_DEC_LEN		(DESC_RFC4106_DEC_LEN + 5 * CAAM_CMD_SZ)
- 
- #define DESC_RFC4543_BASE		(3 * CAAM_CMD_SZ)
- #define DESC_RFC4543_ENC_LEN		(DESC_RFC4543_BASE + 11 * CAAM_CMD_SZ)
- #define DESC_RFC4543_DEC_LEN		(DESC_RFC4543_BASE + 12 * CAAM_CMD_SZ)
-+#define DESC_QI_RFC4543_ENC_LEN		(DESC_RFC4543_ENC_LEN + 4 * CAAM_CMD_SZ)
-+#define DESC_QI_RFC4543_DEC_LEN		(DESC_RFC4543_DEC_LEN + 4 * CAAM_CMD_SZ)
- 
- #define DESC_ABLKCIPHER_BASE		(3 * CAAM_CMD_SZ)
- #define DESC_ABLKCIPHER_ENC_LEN		(DESC_ABLKCIPHER_BASE + \
-@@ -43,46 +52,62 @@
- 					 15 * CAAM_CMD_SZ)
- 
- void cnstr_shdsc_aead_null_encap(u32 * const desc, struct alginfo *adata,
--				 unsigned int icvsize);
-+				 unsigned int icvsize, int era);
- 
- void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
--				 unsigned int icvsize);
-+				 unsigned int icvsize, int era);
- 
- void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
- 			    struct alginfo *adata, unsigned int ivsize,
- 			    unsigned int icvsize, const bool is_rfc3686,
- 			    u32 *nonce, const u32 ctx1_iv_off,
--			    const bool is_qi);
-+			    const bool is_qi, int era);
- 
- void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
- 			    struct alginfo *adata, unsigned int ivsize,
- 			    unsigned int icvsize, const bool geniv,
- 			    const bool is_rfc3686, u32 *nonce,
--			    const u32 ctx1_iv_off, const bool is_qi);
-+			    const u32 ctx1_iv_off, const bool is_qi, int era);
- 
- void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
- 			       struct alginfo *adata, unsigned int ivsize,
- 			       unsigned int icvsize, const bool is_rfc3686,
- 			       u32 *nonce, const u32 ctx1_iv_off,
--			       const bool is_qi);
-+			       const bool is_qi, int era);
-+
-+void cnstr_shdsc_tls_encap(u32 *const desc, struct alginfo *cdata,
-+			   struct alginfo *adata, unsigned int assoclen,
-+			   unsigned int ivsize, unsigned int authsize,
-+			   unsigned int blocksize, int era);
-+
-+void cnstr_shdsc_tls_decap(u32 *const desc, struct alginfo *cdata,
-+			   struct alginfo *adata, unsigned int assoclen,
-+			   unsigned int ivsize, unsigned int authsize,
-+			   unsigned int blocksize, int era);
- 
- void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
--			   unsigned int icvsize);
-+			   unsigned int ivsize, unsigned int icvsize,
-+			   const bool is_qi);
- 
- void cnstr_shdsc_gcm_decap(u32 * const desc, struct alginfo *cdata,
--			   unsigned int icvsize);
-+			   unsigned int ivsize, unsigned int icvsize,
-+			   const bool is_qi);
- 
- void cnstr_shdsc_rfc4106_encap(u32 * const desc, struct alginfo *cdata,
--			       unsigned int icvsize);
-+			       unsigned int ivsize, unsigned int icvsize,
-+			       const bool is_qi);
- 
- void cnstr_shdsc_rfc4106_decap(u32 * const desc, struct alginfo *cdata,
--			       unsigned int icvsize);
-+			       unsigned int ivsize, unsigned int icvsize,
-+			       const bool is_qi);
- 
- void cnstr_shdsc_rfc4543_encap(u32 * const desc, struct alginfo *cdata,
--			       unsigned int icvsize);
-+			       unsigned int ivsize, unsigned int icvsize,
-+			       const bool is_qi);
- 
- void cnstr_shdsc_rfc4543_decap(u32 * const desc, struct alginfo *cdata,
--			       unsigned int icvsize);
-+			       unsigned int ivsize, unsigned int icvsize,
-+			       const bool is_qi);
- 
- void cnstr_shdsc_ablkcipher_encap(u32 * const desc, struct alginfo *cdata,
- 				  unsigned int ivsize, const bool is_rfc3686,
---- a/drivers/crypto/caam/caamalg_qi.c
-+++ b/drivers/crypto/caam/caamalg_qi.c
-@@ -7,7 +7,7 @@
-  */
- 
- #include "compat.h"
--
-+#include "ctrl.h"
- #include "regs.h"
- #include "intern.h"
- #include "desc_constr.h"
-@@ -53,6 +53,7 @@ struct caam_ctx {
- 	u32 sh_desc_givenc[DESC_MAX_USED_LEN];
- 	u8 key[CAAM_MAX_KEY_SIZE];
- 	dma_addr_t key_dma;
-+	enum dma_data_direction dir;
- 	struct alginfo adata;
- 	struct alginfo cdata;
- 	unsigned int authsize;
-@@ -74,6 +75,7 @@ static int aead_set_sh_desc(struct crypt
- 	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
- 			       OP_ALG_AAI_CTR_MOD128);
- 	const bool is_rfc3686 = alg->caam.rfc3686;
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
- 
- 	if (!ctx->cdata.keylen || !ctx->authsize)
- 		return 0;
-@@ -124,7 +126,7 @@ static int aead_set_sh_desc(struct crypt
- 
- 	cnstr_shdsc_aead_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata,
- 			       ivsize, ctx->authsize, is_rfc3686, nonce,
--			       ctx1_iv_off, true);
-+			       ctx1_iv_off, true, ctrlpriv->era);
- 
- skip_enc:
- 	/* aead_decrypt shared descriptor */
-@@ -149,7 +151,8 @@ skip_enc:
- 
- 	cnstr_shdsc_aead_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata,
- 			       ivsize, ctx->authsize, alg->caam.geniv,
--			       is_rfc3686, nonce, ctx1_iv_off, true);
-+			       is_rfc3686, nonce, ctx1_iv_off, true,
-+			       ctrlpriv->era);
- 
- 	if (!alg->caam.geniv)
- 		goto skip_givenc;
-@@ -176,7 +179,7 @@ skip_enc:
- 
- 	cnstr_shdsc_aead_givencap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata,
- 				  ivsize, ctx->authsize, is_rfc3686, nonce,
--				  ctx1_iv_off, true);
-+				  ctx1_iv_off, true, ctrlpriv->era);
- 
- skip_givenc:
- 	return 0;
-@@ -197,6 +200,7 @@ static int aead_setkey(struct crypto_aea
- {
- 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
- 	struct device *jrdev = ctx->jrdev;
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
- 	struct crypto_authenc_keys keys;
- 	int ret = 0;
- 
-@@ -211,6 +215,27 @@ static int aead_setkey(struct crypto_aea
- 		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
- #endif
- 
-+	/*
-+	 * If DKP is supported, use it in the shared descriptor to generate
-+	 * the split key.
-+	 */
-+	if (ctrlpriv->era >= 6) {
-+		ctx->adata.keylen = keys.authkeylen;
-+		ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
-+						      OP_ALG_ALGSEL_MASK);
-+
-+		if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
-+			goto badkey;
-+
-+		memcpy(ctx->key, keys.authkey, keys.authkeylen);
-+		memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
-+		       keys.enckeylen);
-+		dma_sync_single_for_device(jrdev, ctx->key_dma,
-+					   ctx->adata.keylen_pad +
-+					   keys.enckeylen, ctx->dir);
-+		goto skip_split_key;
-+	}
-+
- 	ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey,
- 			    keys.authkeylen, CAAM_MAX_KEY_SIZE -
- 			    keys.enckeylen);
-@@ -220,13 +245,14 @@ static int aead_setkey(struct crypto_aea
- 	/* postpend encryption key to auth split key */
- 	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
- 	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
--				   keys.enckeylen, DMA_TO_DEVICE);
-+				   keys.enckeylen, ctx->dir);
- #ifdef DEBUG
- 	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
- 		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
- 		       ctx->adata.keylen_pad + keys.enckeylen, 1);
- #endif
- 
-+skip_split_key:
- 	ctx->cdata.keylen = keys.enckeylen;
- 
- 	ret = aead_set_sh_desc(aead);
-@@ -258,6 +284,468 @@ badkey:
- 	return -EINVAL;
- }
- 
-+static int tls_set_sh_desc(struct crypto_aead *tls)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	unsigned int ivsize = crypto_aead_ivsize(tls);
-+	unsigned int blocksize = crypto_aead_blocksize(tls);
-+	unsigned int assoclen = 13; /* always 13 bytes for TLS */
-+	unsigned int data_len[2];
-+	u32 inl_mask;
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	/*
-+	 * TLS 1.0 encrypt shared descriptor
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	data_len[0] = ctx->adata.keylen_pad;
-+	data_len[1] = ctx->cdata.keylen;
-+
-+	if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len,
-+			      &inl_mask, ARRAY_SIZE(data_len)) < 0)
-+		return -EINVAL;
-+
-+	if (inl_mask & 1)
-+		ctx->adata.key_virt = ctx->key;
-+	else
-+		ctx->adata.key_dma = ctx->key_dma;
-+
-+	if (inl_mask & 2)
-+		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
-+	else
-+		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
-+
-+	ctx->adata.key_inline = !!(inl_mask & 1);
-+	ctx->cdata.key_inline = !!(inl_mask & 2);
-+
-+	cnstr_shdsc_tls_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata,
-+			      assoclen, ivsize, ctx->authsize, blocksize,
-+			      ctrlpriv->era);
-+
-+	/*
-+	 * TLS 1.0 decrypt shared descriptor
-+	 * Keys do not fit inline, regardless of algorithms used
-+	 */
-+	ctx->adata.key_inline = false;
-+	ctx->adata.key_dma = ctx->key_dma;
-+	ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
-+
-+	cnstr_shdsc_tls_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata,
-+			      assoclen, ivsize, ctx->authsize, blocksize,
-+			      ctrlpriv->era);
-+
-+	return 0;
-+}
-+
-+static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+
-+	ctx->authsize = authsize;
-+	tls_set_sh_desc(tls);
-+
-+	return 0;
-+}
-+
-+static int tls_setkey(struct crypto_aead *tls, const u8 *key,
-+		      unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	struct device *jrdev = ctx->jrdev;
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
-+	struct crypto_authenc_keys keys;
-+	int ret = 0;
-+
-+	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
-+		goto badkey;
-+
-+#ifdef DEBUG
-+	dev_err(jrdev, "keylen %d enckeylen %d authkeylen %d\n",
-+		keys.authkeylen + keys.enckeylen, keys.enckeylen,
-+		keys.authkeylen);
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	/*
-+	 * If DKP is supported, use it in the shared descriptor to generate
-+	 * the split key.
-+	 */
-+	if (ctrlpriv->era >= 6) {
-+		ctx->adata.keylen = keys.authkeylen;
-+		ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
-+						      OP_ALG_ALGSEL_MASK);
-+
-+		if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
-+			goto badkey;
-+
-+		memcpy(ctx->key, keys.authkey, keys.authkeylen);
-+		memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
-+		       keys.enckeylen);
-+		dma_sync_single_for_device(jrdev, ctx->key_dma,
-+					   ctx->adata.keylen_pad +
-+					   keys.enckeylen, ctx->dir);
-+		goto skip_split_key;
-+	}
-+
-+	ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey,
-+			    keys.authkeylen, CAAM_MAX_KEY_SIZE -
-+			    keys.enckeylen);
-+	if (ret)
-+		goto badkey;
-+
-+	/* postpend encryption key to auth split key */
-+	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
-+	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
-+				   keys.enckeylen, ctx->dir);
-+
-+#ifdef DEBUG
-+	dev_err(jrdev, "split keylen %d split keylen padded %d\n",
-+		ctx->adata.keylen, ctx->adata.keylen_pad);
-+	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
-+		       ctx->adata.keylen_pad + keys.enckeylen, 1);
-+#endif
-+
-+skip_split_key:
-+	ctx->cdata.keylen = keys.enckeylen;
-+
-+	ret = tls_set_sh_desc(tls);
-+	if (ret)
-+		goto badkey;
-+
-+	/* Now update the driver contexts with the new shared descriptor */
-+	if (ctx->drv_ctx[ENCRYPT]) {
-+		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
-+					  ctx->sh_desc_enc);
-+		if (ret) {
-+			dev_err(jrdev, "driver enc context update failed\n");
-+			goto badkey;
-+		}
-+	}
-+
-+	if (ctx->drv_ctx[DECRYPT]) {
-+		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
-+					  ctx->sh_desc_dec);
-+		if (ret) {
-+			dev_err(jrdev, "driver dec context update failed\n");
-+			goto badkey;
-+		}
-+	}
-+
-+	return ret;
-+badkey:
-+	crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+	return -EINVAL;
-+}
-+
-+static int gcm_set_sh_desc(struct crypto_aead *aead)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
-+	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
-+			ctx->cdata.keylen;
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_GCM_ENC_LEN) {
-+		ctx->cdata.key_inline = true;
-+		ctx->cdata.key_virt = ctx->key;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	cnstr_shdsc_gcm_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
-+			      ctx->authsize, true);
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_GCM_DEC_LEN) {
-+		ctx->cdata.key_inline = true;
-+		ctx->cdata.key_virt = ctx->key;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	cnstr_shdsc_gcm_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
-+			      ctx->authsize, true);
-+
-+	return 0;
-+}
-+
-+static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
-+
-+	ctx->authsize = authsize;
-+	gcm_set_sh_desc(authenc);
-+
-+	return 0;
-+}
-+
-+static int gcm_setkey(struct crypto_aead *aead,
-+		      const u8 *key, unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *jrdev = ctx->jrdev;
-+	int ret;
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	memcpy(ctx->key, key, keylen);
-+	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, ctx->dir);
-+	ctx->cdata.keylen = keylen;
-+
-+	ret = gcm_set_sh_desc(aead);
-+	if (ret)
-+		return ret;
-+
-+	/* Now update the driver contexts with the new shared descriptor */
-+	if (ctx->drv_ctx[ENCRYPT]) {
-+		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
-+					  ctx->sh_desc_enc);
-+		if (ret) {
-+			dev_err(jrdev, "driver enc context update failed\n");
-+			return ret;
-+		}
-+	}
-+
-+	if (ctx->drv_ctx[DECRYPT]) {
-+		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
-+					  ctx->sh_desc_dec);
-+		if (ret) {
-+			dev_err(jrdev, "driver dec context update failed\n");
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int rfc4106_set_sh_desc(struct crypto_aead *aead)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
-+	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
-+			ctx->cdata.keylen;
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	ctx->cdata.key_virt = ctx->key;
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_RFC4106_ENC_LEN) {
-+		ctx->cdata.key_inline = true;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	cnstr_shdsc_rfc4106_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
-+				  ctx->authsize, true);
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_RFC4106_DEC_LEN) {
-+		ctx->cdata.key_inline = true;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	cnstr_shdsc_rfc4106_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
-+				  ctx->authsize, true);
-+
-+	return 0;
-+}
-+
-+static int rfc4106_setauthsize(struct crypto_aead *authenc,
-+			       unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
-+
-+	ctx->authsize = authsize;
-+	rfc4106_set_sh_desc(authenc);
-+
-+	return 0;
-+}
-+
-+static int rfc4106_setkey(struct crypto_aead *aead,
-+			  const u8 *key, unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *jrdev = ctx->jrdev;
-+	int ret;
-+
-+	if (keylen < 4)
-+		return -EINVAL;
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	memcpy(ctx->key, key, keylen);
-+	/*
-+	 * The last four bytes of the key material are used as the salt value
-+	 * in the nonce. Update the AES key length.
-+	 */
-+	ctx->cdata.keylen = keylen - 4;
-+	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
-+				   ctx->dir);
-+
-+	ret = rfc4106_set_sh_desc(aead);
-+	if (ret)
-+		return ret;
-+
-+	/* Now update the driver contexts with the new shared descriptor */
-+	if (ctx->drv_ctx[ENCRYPT]) {
-+		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
-+					  ctx->sh_desc_enc);
-+		if (ret) {
-+			dev_err(jrdev, "driver enc context update failed\n");
-+			return ret;
-+		}
-+	}
-+
-+	if (ctx->drv_ctx[DECRYPT]) {
-+		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
-+					  ctx->sh_desc_dec);
-+		if (ret) {
-+			dev_err(jrdev, "driver dec context update failed\n");
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
-+static int rfc4543_set_sh_desc(struct crypto_aead *aead)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
-+	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
-+			ctx->cdata.keylen;
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	ctx->cdata.key_virt = ctx->key;
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_RFC4543_ENC_LEN) {
-+		ctx->cdata.key_inline = true;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	cnstr_shdsc_rfc4543_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
-+				  ctx->authsize, true);
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_RFC4543_DEC_LEN) {
-+		ctx->cdata.key_inline = true;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	cnstr_shdsc_rfc4543_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
-+				  ctx->authsize, true);
-+
-+	return 0;
-+}
-+
-+static int rfc4543_setauthsize(struct crypto_aead *authenc,
-+			       unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
-+
-+	ctx->authsize = authsize;
-+	rfc4543_set_sh_desc(authenc);
-+
-+	return 0;
-+}
-+
-+static int rfc4543_setkey(struct crypto_aead *aead,
-+			  const u8 *key, unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *jrdev = ctx->jrdev;
-+	int ret;
-+
-+	if (keylen < 4)
-+		return -EINVAL;
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	memcpy(ctx->key, key, keylen);
-+	/*
-+	 * The last four bytes of the key material are used as the salt value
-+	 * in the nonce. Update the AES key length.
-+	 */
-+	ctx->cdata.keylen = keylen - 4;
-+	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
-+				   ctx->dir);
-+
-+	ret = rfc4543_set_sh_desc(aead);
-+	if (ret)
-+		return ret;
-+
-+	/* Now update the driver contexts with the new shared descriptor */
-+	if (ctx->drv_ctx[ENCRYPT]) {
-+		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
-+					  ctx->sh_desc_enc);
-+		if (ret) {
-+			dev_err(jrdev, "driver enc context update failed\n");
-+			return ret;
-+		}
-+	}
-+
-+	if (ctx->drv_ctx[DECRYPT]) {
-+		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
-+					  ctx->sh_desc_dec);
-+		if (ret) {
-+			dev_err(jrdev, "driver dec context update failed\n");
-+			return ret;
-+		}
-+	}
-+
-+	return 0;
-+}
-+
- static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
- 			     const u8 *key, unsigned int keylen)
- {
-@@ -414,6 +902,29 @@ struct aead_edesc {
- };
- 
- /*
-+ * tls_edesc - s/w-extended tls descriptor
-+ * @src_nents: number of segments in input scatterlist
-+ * @dst_nents: number of segments in output scatterlist
-+ * @iv_dma: dma address of iv for checking continuity and link table
-+ * @qm_sg_bytes: length of dma mapped h/w link table
-+ * @tmp: array of scatterlists used by 'scatterwalk_ffwd'
-+ * @qm_sg_dma: bus physical mapped address of h/w link table
-+ * @drv_req: driver-specific request structure
-+ * @sgt: the h/w link table, followed by IV
-+ */
-+struct tls_edesc {
-+	int src_nents;
-+	int dst_nents;
-+	dma_addr_t iv_dma;
-+	int qm_sg_bytes;
-+	dma_addr_t qm_sg_dma;
-+	struct scatterlist tmp[2];
-+	struct scatterlist *dst;
-+	struct caam_drv_req drv_req;
-+	struct qm_sg_entry sgt[0];
-+};
-+
-+/*
-  * ablkcipher_edesc - s/w-extended ablkcipher descriptor
-  * @src_nents: number of segments in input scatterlist
-  * @dst_nents: number of segments in output scatterlist
-@@ -508,6 +1019,19 @@ static void aead_unmap(struct device *de
- 	dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
- }
- 
-+static void tls_unmap(struct device *dev,
-+		      struct tls_edesc *edesc,
-+		      struct aead_request *req)
-+{
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	int ivsize = crypto_aead_ivsize(aead);
-+
-+	caam_unmap(dev, req->src, edesc->dst, edesc->src_nents,
-+		   edesc->dst_nents, edesc->iv_dma, ivsize,
-+		   edesc->drv_req.drv_ctx->op_type, edesc->qm_sg_dma,
-+		   edesc->qm_sg_bytes);
-+}
-+
- static void ablkcipher_unmap(struct device *dev,
- 			     struct ablkcipher_edesc *edesc,
- 			     struct ablkcipher_request *req)
-@@ -532,8 +1056,18 @@ static void aead_done(struct caam_drv_re
- 	qidev = caam_ctx->qidev;
- 
- 	if (unlikely(status)) {
-+		u32 ssrc = status & JRSTA_SSRC_MASK;
-+		u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
-+
- 		caam_jr_strstatus(qidev, status);
--		ecode = -EIO;
-+		/*
-+		 * verify hw auth check passed else return -EBADMSG
-+		 */
-+		if (ssrc == JRSTA_SSRC_CCB_ERROR &&
-+		    err_id == JRSTA_CCBERR_ERRID_ICVCHK)
-+			ecode = -EBADMSG;
-+		else
-+			ecode = -EIO;
- 	}
- 
- 	edesc = container_of(drv_req, typeof(*edesc), drv_req);
-@@ -785,6 +1319,260 @@ static int aead_decrypt(struct aead_requ
- 	return aead_crypt(req, false);
- }
- 
-+static int ipsec_gcm_encrypt(struct aead_request *req)
-+{
-+	if (req->assoclen < 8)
-+		return -EINVAL;
-+
-+	return aead_crypt(req, true);
-+}
-+
-+static int ipsec_gcm_decrypt(struct aead_request *req)
-+{
-+	if (req->assoclen < 8)
-+		return -EINVAL;
-+
-+	return aead_crypt(req, false);
-+}
-+
-+static void tls_done(struct caam_drv_req *drv_req, u32 status)
-+{
-+	struct device *qidev;
-+	struct tls_edesc *edesc;
-+	struct aead_request *aead_req = drv_req->app_ctx;
-+	struct crypto_aead *aead = crypto_aead_reqtfm(aead_req);
-+	struct caam_ctx *caam_ctx = crypto_aead_ctx(aead);
-+	int ecode = 0;
-+
-+	qidev = caam_ctx->qidev;
-+
-+	if (unlikely(status)) {
-+		caam_jr_strstatus(qidev, status);
-+		ecode = -EIO;
-+	}
-+
-+	edesc = container_of(drv_req, typeof(*edesc), drv_req);
-+	tls_unmap(qidev, edesc, aead_req);
-+
-+	aead_request_complete(aead_req, ecode);
-+	qi_cache_free(edesc);
-+}
-+
-+/*
-+ * allocate and map the tls extended descriptor
-+ */
-+static struct tls_edesc *tls_edesc_alloc(struct aead_request *req, bool encrypt)
-+{
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	unsigned int blocksize = crypto_aead_blocksize(aead);
-+	unsigned int padsize, authsize;
-+	struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
-+						 typeof(*alg), aead);
-+	struct device *qidev = ctx->qidev;
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
-+	struct tls_edesc *edesc;
-+	dma_addr_t qm_sg_dma, iv_dma = 0;
-+	int ivsize = 0;
-+	u8 *iv;
-+	int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes;
-+	int in_len, out_len;
-+	struct qm_sg_entry *sg_table, *fd_sgt;
-+	struct caam_drv_ctx *drv_ctx;
-+	enum optype op_type = encrypt ? ENCRYPT : DECRYPT;
-+	struct scatterlist *dst;
-+
-+	if (encrypt) {
-+		padsize = blocksize - ((req->cryptlen + ctx->authsize) %
-+					blocksize);
-+		authsize = ctx->authsize + padsize;
-+	} else {
-+		authsize = ctx->authsize;
-+	}
-+
-+	drv_ctx = get_drv_ctx(ctx, op_type);
-+	if (unlikely(IS_ERR_OR_NULL(drv_ctx)))
-+		return (struct tls_edesc *)drv_ctx;
-+
-+	/* allocate space for base edesc, link tables and IV */
-+	edesc = qi_cache_alloc(GFP_DMA | flags);
-+	if (unlikely(!edesc)) {
-+		dev_err(qidev, "could not allocate extended descriptor\n");
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	if (likely(req->src == req->dst)) {
-+		src_nents = sg_nents_for_len(req->src, req->assoclen +
-+					     req->cryptlen +
-+					     (encrypt ? authsize : 0));
-+		if (unlikely(src_nents < 0)) {
-+			dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
-+				req->assoclen + req->cryptlen +
-+				(encrypt ? authsize : 0));
-+			qi_cache_free(edesc);
-+			return ERR_PTR(src_nents);
-+		}
-+
-+		mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
-+					      DMA_BIDIRECTIONAL);
-+		if (unlikely(!mapped_src_nents)) {
-+			dev_err(qidev, "unable to map source\n");
-+			qi_cache_free(edesc);
-+			return ERR_PTR(-ENOMEM);
-+		}
-+		dst = req->dst;
-+	} else {
-+		src_nents = sg_nents_for_len(req->src, req->assoclen +
-+					     req->cryptlen);
-+		if (unlikely(src_nents < 0)) {
-+			dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
-+				req->assoclen + req->cryptlen);
-+			qi_cache_free(edesc);
-+			return ERR_PTR(src_nents);
-+		}
-+
-+		dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen);
-+		dst_nents = sg_nents_for_len(dst, req->cryptlen +
-+					     (encrypt ? authsize : 0));
-+		if (unlikely(dst_nents < 0)) {
-+			dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n",
-+				req->cryptlen +
-+				(encrypt ? authsize : 0));
-+			qi_cache_free(edesc);
-+			return ERR_PTR(dst_nents);
-+		}
-+
-+		if (src_nents) {
-+			mapped_src_nents = dma_map_sg(qidev, req->src,
-+						      src_nents, DMA_TO_DEVICE);
-+			if (unlikely(!mapped_src_nents)) {
-+				dev_err(qidev, "unable to map source\n");
-+				qi_cache_free(edesc);
-+				return ERR_PTR(-ENOMEM);
-+			}
-+		} else {
-+			mapped_src_nents = 0;
-+		}
-+
-+		mapped_dst_nents = dma_map_sg(qidev, dst, dst_nents,
-+					      DMA_FROM_DEVICE);
-+		if (unlikely(!mapped_dst_nents)) {
-+			dev_err(qidev, "unable to map destination\n");
-+			dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE);
-+			qi_cache_free(edesc);
-+			return ERR_PTR(-ENOMEM);
-+		}
-+	}
-+
-+	/*
-+	 * Create S/G table: IV, src, dst.
-+	 * Input is not contiguous.
-+	 */
-+	qm_sg_ents = 1 + mapped_src_nents +
-+		     (mapped_dst_nents > 1 ? mapped_dst_nents : 0);
-+	sg_table = &edesc->sgt[0];
-+	qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
-+
-+	ivsize = crypto_aead_ivsize(aead);
-+	iv = (u8 *)(sg_table + qm_sg_ents);
-+	/* Make sure IV is located in a DMAable area */
-+	memcpy(iv, req->iv, ivsize);
-+	iv_dma = dma_map_single(qidev, iv, ivsize, DMA_TO_DEVICE);
-+	if (dma_mapping_error(qidev, iv_dma)) {
-+		dev_err(qidev, "unable to map IV\n");
-+		caam_unmap(qidev, req->src, dst, src_nents, dst_nents, 0, 0, 0,
-+			   0, 0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	edesc->src_nents = src_nents;
-+	edesc->dst_nents = dst_nents;
-+	edesc->dst = dst;
-+	edesc->iv_dma = iv_dma;
-+	edesc->drv_req.app_ctx = req;
-+	edesc->drv_req.cbk = tls_done;
-+	edesc->drv_req.drv_ctx = drv_ctx;
-+
-+	dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
-+	qm_sg_index = 1;
-+
-+	sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0);
-+	qm_sg_index += mapped_src_nents;
-+
-+	if (mapped_dst_nents > 1)
-+		sg_to_qm_sg_last(dst, mapped_dst_nents, sg_table +
-+				 qm_sg_index, 0);
-+
-+	qm_sg_dma = dma_map_single(qidev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
-+	if (dma_mapping_error(qidev, qm_sg_dma)) {
-+		dev_err(qidev, "unable to map S/G table\n");
-+		caam_unmap(qidev, req->src, dst, src_nents, dst_nents, iv_dma,
-+			   ivsize, op_type, 0, 0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	edesc->qm_sg_dma = qm_sg_dma;
-+	edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+	out_len = req->cryptlen + (encrypt ? authsize : 0);
-+	in_len = ivsize + req->assoclen + req->cryptlen;
-+
-+	fd_sgt = &edesc->drv_req.fd_sgt[0];
-+
-+	dma_to_qm_sg_one_last_ext(&fd_sgt[1], qm_sg_dma, in_len, 0);
-+
-+	if (req->dst == req->src)
-+		dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma +
-+				    (sg_nents_for_len(req->src, req->assoclen) +
-+				     1) * sizeof(*sg_table), out_len, 0);
-+	else if (mapped_dst_nents == 1)
-+		dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(dst), out_len, 0);
-+	else
-+		dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + sizeof(*sg_table) *
-+				     qm_sg_index, out_len, 0);
-+
-+	return edesc;
-+}
-+
-+static int tls_crypt(struct aead_request *req, bool encrypt)
-+{
-+	struct tls_edesc *edesc;
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	int ret;
-+
-+	if (unlikely(caam_congested))
-+		return -EAGAIN;
-+
-+	edesc = tls_edesc_alloc(req, encrypt);
-+	if (IS_ERR_OR_NULL(edesc))
-+		return PTR_ERR(edesc);
-+
-+	ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req);
-+	if (!ret) {
-+		ret = -EINPROGRESS;
-+	} else {
-+		tls_unmap(ctx->qidev, edesc, req);
-+		qi_cache_free(edesc);
-+	}
-+
-+	return ret;
-+}
-+
-+static int tls_encrypt(struct aead_request *req)
-+{
-+	return tls_crypt(req, true);
-+}
-+
-+static int tls_decrypt(struct aead_request *req)
-+{
-+	return tls_crypt(req, false);
-+}
-+
- static void ablkcipher_done(struct caam_drv_req *drv_req, u32 status)
- {
- 	struct ablkcipher_edesc *edesc;
-@@ -1308,6 +2096,61 @@ static struct caam_alg_template driver_a
- };
- 
- static struct caam_aead_alg driver_aeads[] = {
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "rfc4106(gcm(aes))",
-+				.cra_driver_name = "rfc4106-gcm-aes-caam-qi",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = rfc4106_setkey,
-+			.setauthsize = rfc4106_setauthsize,
-+			.encrypt = ipsec_gcm_encrypt,
-+			.decrypt = ipsec_gcm_decrypt,
-+			.ivsize = 8,
-+			.maxauthsize = AES_BLOCK_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "rfc4543(gcm(aes))",
-+				.cra_driver_name = "rfc4543-gcm-aes-caam-qi",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = rfc4543_setkey,
-+			.setauthsize = rfc4543_setauthsize,
-+			.encrypt = ipsec_gcm_encrypt,
-+			.decrypt = ipsec_gcm_decrypt,
-+			.ivsize = 8,
-+			.maxauthsize = AES_BLOCK_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
-+		},
-+	},
-+	/* Galois Counter Mode */
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "gcm(aes)",
-+				.cra_driver_name = "gcm-aes-caam-qi",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = gcm_setkey,
-+			.setauthsize = gcm_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = 12,
-+			.maxauthsize = AES_BLOCK_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
-+		}
-+	},
- 	/* single-pass ipsec_esp descriptor */
- 	{
- 		.aead = {
-@@ -2118,6 +2961,26 @@ static struct caam_aead_alg driver_aeads
- 			.geniv = true,
- 		}
- 	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "tls10(hmac(sha1),cbc(aes))",
-+				.cra_driver_name = "tls10-hmac-sha1-cbc-aes-caam-qi",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = tls_setkey,
-+			.setauthsize = tls_setauthsize,
-+			.encrypt = tls_encrypt,
-+			.decrypt = tls_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	}
- };
- 
- struct caam_crypto_alg {
-@@ -2126,9 +2989,20 @@ struct caam_crypto_alg {
- 	struct caam_alg_entry caam;
- };
- 
--static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam)
-+static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam,
-+			   bool uses_dkp)
- {
- 	struct caam_drv_private *priv;
-+	/* Digest sizes for MD5, SHA1, SHA-224, SHA-256, SHA-384, SHA-512 */
-+	static const u8 digest_size[] = {
-+		MD5_DIGEST_SIZE,
-+		SHA1_DIGEST_SIZE,
-+		SHA224_DIGEST_SIZE,
-+		SHA256_DIGEST_SIZE,
-+		SHA384_DIGEST_SIZE,
-+		SHA512_DIGEST_SIZE
-+	};
-+	u8 op_id;
- 
- 	/*
- 	 * distribute tfms across job rings to ensure in-order
-@@ -2140,8 +3014,14 @@ static int caam_init_common(struct caam_
- 		return PTR_ERR(ctx->jrdev);
- 	}
- 
-+	priv = dev_get_drvdata(ctx->jrdev->parent);
-+	if (priv->era >= 6 && uses_dkp)
-+		ctx->dir = DMA_BIDIRECTIONAL;
-+	else
-+		ctx->dir = DMA_TO_DEVICE;
-+
- 	ctx->key_dma = dma_map_single(ctx->jrdev, ctx->key, sizeof(ctx->key),
--				      DMA_TO_DEVICE);
-+				      ctx->dir);
- 	if (dma_mapping_error(ctx->jrdev, ctx->key_dma)) {
- 		dev_err(ctx->jrdev, "unable to map key\n");
- 		caam_jr_free(ctx->jrdev);
-@@ -2152,7 +3032,22 @@ static int caam_init_common(struct caam_
- 	ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
- 	ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
- 
--	priv = dev_get_drvdata(ctx->jrdev->parent);
-+	if (ctx->adata.algtype) {
-+		op_id = (ctx->adata.algtype & OP_ALG_ALGSEL_SUBMASK)
-+				>> OP_ALG_ALGSEL_SHIFT;
-+		if (op_id < ARRAY_SIZE(digest_size)) {
-+			ctx->authsize = digest_size[op_id];
-+		} else {
-+			dev_err(ctx->jrdev,
-+				"incorrect op_id %d; must be less than %zu\n",
-+				op_id, ARRAY_SIZE(digest_size));
-+			caam_jr_free(ctx->jrdev);
-+			return -EINVAL;
-+		}
-+	} else {
-+		ctx->authsize = 0;
-+	}
-+
- 	ctx->qidev = priv->qidev;
- 
- 	spin_lock_init(&ctx->lock);
-@@ -2170,7 +3065,7 @@ static int caam_cra_init(struct crypto_t
- 							crypto_alg);
- 	struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
- 
--	return caam_init_common(ctx, &caam_alg->caam);
-+	return caam_init_common(ctx, &caam_alg->caam, false);
- }
- 
- static int caam_aead_init(struct crypto_aead *tfm)
-@@ -2180,7 +3075,9 @@ static int caam_aead_init(struct crypto_
- 						      aead);
- 	struct caam_ctx *ctx = crypto_aead_ctx(tfm);
- 
--	return caam_init_common(ctx, &caam_alg->caam);
-+	return caam_init_common(ctx, &caam_alg->caam,
-+				(alg->setkey == aead_setkey) ||
-+				(alg->setkey == tls_setkey));
- }
- 
- static void caam_exit_common(struct caam_ctx *ctx)
-@@ -2189,8 +3086,7 @@ static void caam_exit_common(struct caam
- 	caam_drv_ctx_rel(ctx->drv_ctx[DECRYPT]);
- 	caam_drv_ctx_rel(ctx->drv_ctx[GIVENCRYPT]);
- 
--	dma_unmap_single(ctx->jrdev, ctx->key_dma, sizeof(ctx->key),
--			 DMA_TO_DEVICE);
-+	dma_unmap_single(ctx->jrdev, ctx->key_dma, sizeof(ctx->key), ctx->dir);
- 
- 	caam_jr_free(ctx->jrdev);
- }
-@@ -2315,6 +3211,11 @@ static int __init caam_qi_algapi_init(vo
- 	if (!priv || !priv->qi_present)
- 		return -ENODEV;
- 
-+	if (caam_dpaa2) {
-+		dev_info(ctrldev, "caam/qi frontend driver not suitable for DPAA 2.x, aborting...\n");
-+		return -ENODEV;
-+	}
-+
- 	INIT_LIST_HEAD(&alg_list);
- 
- 	/*
---- /dev/null
-+++ b/drivers/crypto/caam/caamalg_qi2.c
-@@ -0,0 +1,5691 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017-2018 NXP
-+ */
-+
-+#include <linux/fsl/mc.h>
-+#include "compat.h"
-+#include "regs.h"
-+#include "caamalg_qi2.h"
-+#include "dpseci_cmd.h"
-+#include "desc_constr.h"
-+#include "error.h"
-+#include "sg_sw_sec4.h"
-+#include "sg_sw_qm2.h"
-+#include "key_gen.h"
-+#include "caamalg_desc.h"
-+#include "caamhash_desc.h"
-+#include "../../../drivers/staging/fsl-mc/include/dpaa2-io.h"
-+#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
-+
-+#define CAAM_CRA_PRIORITY	2000
-+
-+/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
-+#define CAAM_MAX_KEY_SIZE	(AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE + \
-+				 SHA512_DIGEST_SIZE * 2)
-+
-+#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM
-+bool caam_little_end;
-+EXPORT_SYMBOL(caam_little_end);
-+bool caam_imx;
-+EXPORT_SYMBOL(caam_imx);
-+#endif
-+
-+/*
-+ * This is a a cache of buffers, from which the users of CAAM QI driver
-+ * can allocate short buffers. It's speedier than doing kmalloc on the hotpath.
-+ * NOTE: A more elegant solution would be to have some headroom in the frames
-+ *       being processed. This can be added by the dpaa2-eth driver. This would
-+ *       pose a problem for userspace application processing which cannot
-+ *       know of this limitation. So for now, this will work.
-+ * NOTE: The memcache is SMP-safe. No need to handle spinlocks in-here
-+ */
-+static struct kmem_cache *qi_cache;
-+
-+struct caam_alg_entry {
-+	struct device *dev;
-+	int class1_alg_type;
-+	int class2_alg_type;
-+	bool rfc3686;
-+	bool geniv;
-+};
-+
-+struct caam_aead_alg {
-+	struct aead_alg aead;
-+	struct caam_alg_entry caam;
-+	bool registered;
-+};
-+
-+struct caam_skcipher_alg {
-+	struct skcipher_alg skcipher;
-+	struct caam_alg_entry caam;
-+	bool registered;
-+};
-+
-+/**
-+ * caam_ctx - per-session context
-+ * @flc: Flow Contexts array
-+ * @key:  virtual address of the key(s): [authentication key], encryption key
-+ * @flc_dma: I/O virtual addresses of the Flow Contexts
-+ * @key_dma: I/O virtual address of the key
-+ * @dir: DMA direction for mapping key and Flow Contexts
-+ * @dev: dpseci device
-+ * @adata: authentication algorithm details
-+ * @cdata: encryption algorithm details
-+ * @authsize: authentication tag (a.k.a. ICV / MAC) size
-+ */
-+struct caam_ctx {
-+	struct caam_flc flc[NUM_OP];
-+	u8 key[CAAM_MAX_KEY_SIZE];
-+	dma_addr_t flc_dma[NUM_OP];
-+	dma_addr_t key_dma;
-+	enum dma_data_direction dir;
-+	struct device *dev;
-+	struct alginfo adata;
-+	struct alginfo cdata;
-+	unsigned int authsize;
-+};
-+
-+void *dpaa2_caam_iova_to_virt(struct dpaa2_caam_priv *priv,
-+			      dma_addr_t iova_addr)
-+{
-+	phys_addr_t phys_addr;
-+
-+	phys_addr = priv->domain ? iommu_iova_to_phys(priv->domain, iova_addr) :
-+				   iova_addr;
-+
-+	return phys_to_virt(phys_addr);
-+}
-+
-+/*
-+ * qi_cache_zalloc - Allocate buffers from CAAM-QI cache
-+ *
-+ * Allocate data on the hotpath. Instead of using kzalloc, one can use the
-+ * services of the CAAM QI memory cache (backed by kmem_cache). The buffers
-+ * will have a size of CAAM_QI_MEMCACHE_SIZE, which should be sufficient for
-+ * hosting 16 SG entries.
-+ *
-+ * @flags - flags that would be used for the equivalent kmalloc(..) call
-+ *
-+ * Returns a pointer to a retrieved buffer on success or NULL on failure.
-+ */
-+static inline void *qi_cache_zalloc(gfp_t flags)
-+{
-+	return kmem_cache_zalloc(qi_cache, flags);
-+}
-+
-+/*
-+ * qi_cache_free - Frees buffers allocated from CAAM-QI cache
-+ *
-+ * @obj - buffer previously allocated by qi_cache_zalloc
-+ *
-+ * No checking is being done, the call is a passthrough call to
-+ * kmem_cache_free(...)
-+ */
-+static inline void qi_cache_free(void *obj)
-+{
-+	kmem_cache_free(qi_cache, obj);
-+}
-+
-+static struct caam_request *to_caam_req(struct crypto_async_request *areq)
-+{
-+	switch (crypto_tfm_alg_type(areq->tfm)) {
-+	case CRYPTO_ALG_TYPE_SKCIPHER:
-+		return skcipher_request_ctx(skcipher_request_cast(areq));
-+	case CRYPTO_ALG_TYPE_AEAD:
-+		return aead_request_ctx(container_of(areq, struct aead_request,
-+						     base));
-+	case CRYPTO_ALG_TYPE_AHASH:
-+		return ahash_request_ctx(ahash_request_cast(areq));
-+	default:
-+		return ERR_PTR(-EINVAL);
-+	}
-+}
-+
-+static void caam_unmap(struct device *dev, struct scatterlist *src,
-+		       struct scatterlist *dst, int src_nents,
-+		       int dst_nents, dma_addr_t iv_dma, int ivsize,
-+		       dma_addr_t qm_sg_dma, int qm_sg_bytes)
-+{
-+	if (dst != src) {
-+		if (src_nents)
-+			dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
-+		dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
-+	} else {
-+		dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
-+	}
-+
-+	if (iv_dma)
-+		dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
-+
-+	if (qm_sg_bytes)
-+		dma_unmap_single(dev, qm_sg_dma, qm_sg_bytes, DMA_TO_DEVICE);
-+}
-+
-+static int aead_set_sh_desc(struct crypto_aead *aead)
-+{
-+	struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
-+						 typeof(*alg), aead);
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
-+	struct device *dev = ctx->dev;
-+	struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
-+	struct caam_flc *flc;
-+	u32 *desc;
-+	u32 ctx1_iv_off = 0;
-+	u32 *nonce = NULL;
-+	unsigned int data_len[2];
-+	u32 inl_mask;
-+	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
-+			       OP_ALG_AAI_CTR_MOD128);
-+	const bool is_rfc3686 = alg->caam.rfc3686;
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	/*
-+	 * AES-CTR needs to load IV in CONTEXT1 reg
-+	 * at an offset of 128bits (16bytes)
-+	 * CONTEXT1[255:128] = IV
-+	 */
-+	if (ctr_mode)
-+		ctx1_iv_off = 16;
-+
-+	/*
-+	 * RFC3686 specific:
-+	 *	CONTEXT1[255:128] = {NONCE, IV, COUNTER}
-+	 */
-+	if (is_rfc3686) {
-+		ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
-+		nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
-+				ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
-+	}
-+
-+	data_len[0] = ctx->adata.keylen_pad;
-+	data_len[1] = ctx->cdata.keylen;
-+
-+	/* aead_encrypt shared descriptor */
-+	if (desc_inline_query((alg->caam.geniv ? DESC_QI_AEAD_GIVENC_LEN :
-+						 DESC_QI_AEAD_ENC_LEN) +
-+			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
-+			      DESC_JOB_IO_LEN, data_len, &inl_mask,
-+			      ARRAY_SIZE(data_len)) < 0)
-+		return -EINVAL;
-+
-+	if (inl_mask & 1)
-+		ctx->adata.key_virt = ctx->key;
-+	else
-+		ctx->adata.key_dma = ctx->key_dma;
-+
-+	if (inl_mask & 2)
-+		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
-+	else
-+		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
-+
-+	ctx->adata.key_inline = !!(inl_mask & 1);
-+	ctx->cdata.key_inline = !!(inl_mask & 2);
-+
-+	flc = &ctx->flc[ENCRYPT];
-+	desc = flc->sh_desc;
-+
-+	if (alg->caam.geniv)
-+		cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata,
-+					  ivsize, ctx->authsize, is_rfc3686,
-+					  nonce, ctx1_iv_off, true,
-+					  priv->sec_attr.era);
-+	else
-+		cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata,
-+				       ivsize, ctx->authsize, is_rfc3686, nonce,
-+				       ctx1_iv_off, true, priv->sec_attr.era);
-+
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	/* aead_decrypt shared descriptor */
-+	if (desc_inline_query(DESC_QI_AEAD_DEC_LEN +
-+			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
-+			      DESC_JOB_IO_LEN, data_len, &inl_mask,
-+			      ARRAY_SIZE(data_len)) < 0)
-+		return -EINVAL;
-+
-+	if (inl_mask & 1)
-+		ctx->adata.key_virt = ctx->key;
-+	else
-+		ctx->adata.key_dma = ctx->key_dma;
-+
-+	if (inl_mask & 2)
-+		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
-+	else
-+		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
-+
-+	ctx->adata.key_inline = !!(inl_mask & 1);
-+	ctx->cdata.key_inline = !!(inl_mask & 2);
-+
-+	flc = &ctx->flc[DECRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata,
-+			       ivsize, ctx->authsize, alg->caam.geniv,
-+			       is_rfc3686, nonce, ctx1_iv_off, true,
-+			       priv->sec_attr.era);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	return 0;
-+}
-+
-+static int aead_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
-+
-+	ctx->authsize = authsize;
-+	aead_set_sh_desc(authenc);
-+
-+	return 0;
-+}
-+
-+struct split_key_sh_result {
-+	struct completion completion;
-+	int err;
-+	struct device *dev;
-+};
-+
-+static void split_key_sh_done(void *cbk_ctx, u32 err)
-+{
-+	struct split_key_sh_result *res = cbk_ctx;
-+
-+#ifdef DEBUG
-+	dev_err(res->dev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
-+#endif
-+
-+	if (err)
-+		caam_qi2_strstatus(res->dev, err);
-+
-+	res->err = err;
-+	complete(&res->completion);
-+}
-+
-+static int aead_setkey(struct crypto_aead *aead, const u8 *key,
-+		       unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *dev = ctx->dev;
-+	struct crypto_authenc_keys keys;
-+
-+	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
-+		goto badkey;
-+
-+#ifdef DEBUG
-+	dev_err(dev, "keylen %d enckeylen %d authkeylen %d\n",
-+		keys.authkeylen + keys.enckeylen, keys.enckeylen,
-+		keys.authkeylen);
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	ctx->adata.keylen = keys.authkeylen;
-+	ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
-+					      OP_ALG_ALGSEL_MASK);
-+
-+	if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
-+		goto badkey;
-+
-+	memcpy(ctx->key, keys.authkey, keys.authkeylen);
-+	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
-+	dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad +
-+				   keys.enckeylen, ctx->dir);
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
-+		       ctx->adata.keylen_pad + keys.enckeylen, 1);
-+#endif
-+
-+	ctx->cdata.keylen = keys.enckeylen;
-+
-+	return aead_set_sh_desc(aead);
-+badkey:
-+	crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+	return -EINVAL;
-+}
-+
-+static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
-+					   bool encrypt)
-+{
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	struct caam_request *req_ctx = aead_request_ctx(req);
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
-+						 typeof(*alg), aead);
-+	struct device *dev = ctx->dev;
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
-+	struct aead_edesc *edesc;
-+	dma_addr_t qm_sg_dma, iv_dma = 0;
-+	int ivsize = 0;
-+	unsigned int authsize = ctx->authsize;
-+	int qm_sg_index = 0, qm_sg_nents = 0, qm_sg_bytes;
-+	int in_len, out_len;
-+	struct dpaa2_sg_entry *sg_table;
-+
-+	/* allocate space for base edesc, link tables and IV */
-+	edesc = qi_cache_zalloc(GFP_DMA | flags);
-+	if (unlikely(!edesc)) {
-+		dev_err(dev, "could not allocate extended descriptor\n");
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	if (unlikely(req->dst != req->src)) {
-+		src_nents = sg_nents_for_len(req->src, req->assoclen +
-+					     req->cryptlen);
-+		if (unlikely(src_nents < 0)) {
-+			dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
-+				req->assoclen + req->cryptlen);
-+			qi_cache_free(edesc);
-+			return ERR_PTR(src_nents);
-+		}
-+
-+		dst_nents = sg_nents_for_len(req->dst, req->assoclen +
-+					     req->cryptlen +
-+					     (encrypt ? authsize :
-+							(-authsize)));
-+		if (unlikely(dst_nents < 0)) {
-+			dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
-+				req->assoclen + req->cryptlen +
-+				(encrypt ? authsize : (-authsize)));
-+			qi_cache_free(edesc);
-+			return ERR_PTR(dst_nents);
-+		}
-+
-+		if (src_nents) {
-+			mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
-+						      DMA_TO_DEVICE);
-+			if (unlikely(!mapped_src_nents)) {
-+				dev_err(dev, "unable to map source\n");
-+				qi_cache_free(edesc);
-+				return ERR_PTR(-ENOMEM);
-+			}
-+		} else {
-+			mapped_src_nents = 0;
-+		}
-+
-+		mapped_dst_nents = dma_map_sg(dev, req->dst, dst_nents,
-+					      DMA_FROM_DEVICE);
-+		if (unlikely(!mapped_dst_nents)) {
-+			dev_err(dev, "unable to map destination\n");
-+			dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE);
-+			qi_cache_free(edesc);
-+			return ERR_PTR(-ENOMEM);
-+		}
-+	} else {
-+		src_nents = sg_nents_for_len(req->src, req->assoclen +
-+					     req->cryptlen +
-+						(encrypt ? authsize : 0));
-+		if (unlikely(src_nents < 0)) {
-+			dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
-+				req->assoclen + req->cryptlen +
-+				(encrypt ? authsize : 0));
-+			qi_cache_free(edesc);
-+			return ERR_PTR(src_nents);
-+		}
-+
-+		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
-+					      DMA_BIDIRECTIONAL);
-+		if (unlikely(!mapped_src_nents)) {
-+			dev_err(dev, "unable to map source\n");
-+			qi_cache_free(edesc);
-+			return ERR_PTR(-ENOMEM);
-+		}
-+	}
-+
-+	if ((alg->caam.rfc3686 && encrypt) || !alg->caam.geniv)
-+		ivsize = crypto_aead_ivsize(aead);
-+
-+	/*
-+	 * Create S/G table: req->assoclen, [IV,] req->src [, req->dst].
-+	 * Input is not contiguous.
-+	 */
-+	qm_sg_nents = 1 + !!ivsize + mapped_src_nents +
-+		      (mapped_dst_nents > 1 ? mapped_dst_nents : 0);
-+	sg_table = &edesc->sgt[0];
-+	qm_sg_bytes = qm_sg_nents * sizeof(*sg_table);
-+	if (unlikely(offsetof(struct aead_edesc, sgt) + qm_sg_bytes + ivsize >
-+		     CAAM_QI_MEMCACHE_SIZE)) {
-+		dev_err(dev, "No space for %d S/G entries and/or %dB IV\n",
-+			qm_sg_nents, ivsize);
-+		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
-+			   0, 0, 0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	if (ivsize) {
-+		u8 *iv = (u8 *)(sg_table + qm_sg_nents);
-+
-+		/* Make sure IV is located in a DMAable area */
-+		memcpy(iv, req->iv, ivsize);
-+
-+		iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
-+		if (dma_mapping_error(dev, iv_dma)) {
-+			dev_err(dev, "unable to map IV\n");
-+			caam_unmap(dev, req->src, req->dst, src_nents,
-+				   dst_nents, 0, 0, 0, 0);
-+			qi_cache_free(edesc);
-+			return ERR_PTR(-ENOMEM);
-+		}
-+	}
-+
-+	edesc->src_nents = src_nents;
-+	edesc->dst_nents = dst_nents;
-+	edesc->iv_dma = iv_dma;
-+
-+	edesc->assoclen = cpu_to_caam32(req->assoclen);
-+	edesc->assoclen_dma = dma_map_single(dev, &edesc->assoclen, 4,
-+					     DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, edesc->assoclen_dma)) {
-+		dev_err(dev, "unable to map assoclen\n");
-+		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
-+			   iv_dma, ivsize, 0, 0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	dma_to_qm_sg_one(sg_table, edesc->assoclen_dma, 4, 0);
-+	qm_sg_index++;
-+	if (ivsize) {
-+		dma_to_qm_sg_one(sg_table + qm_sg_index, iv_dma, ivsize, 0);
-+		qm_sg_index++;
-+	}
-+	sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0);
-+	qm_sg_index += mapped_src_nents;
-+
-+	if (mapped_dst_nents > 1)
-+		sg_to_qm_sg_last(req->dst, mapped_dst_nents, sg_table +
-+				 qm_sg_index, 0);
-+
-+	qm_sg_dma = dma_map_single(dev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, qm_sg_dma)) {
-+		dev_err(dev, "unable to map S/G table\n");
-+		dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
-+		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
-+			   iv_dma, ivsize, 0, 0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	edesc->qm_sg_dma = qm_sg_dma;
-+	edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+	out_len = req->assoclen + req->cryptlen +
-+		  (encrypt ? ctx->authsize : (-ctx->authsize));
-+	in_len = 4 + ivsize + req->assoclen + req->cryptlen;
-+
-+	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+	dpaa2_fl_set_addr(in_fle, qm_sg_dma);
-+	dpaa2_fl_set_len(in_fle, in_len);
-+
-+	if (req->dst == req->src) {
-+		if (mapped_src_nents == 1) {
-+			dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+			dpaa2_fl_set_addr(out_fle, sg_dma_address(req->src));
-+		} else {
-+			dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
-+			dpaa2_fl_set_addr(out_fle, qm_sg_dma +
-+					  (1 + !!ivsize) * sizeof(*sg_table));
-+		}
-+	} else if (mapped_dst_nents == 1) {
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+		dpaa2_fl_set_addr(out_fle, sg_dma_address(req->dst));
-+	} else {
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
-+		dpaa2_fl_set_addr(out_fle, qm_sg_dma + qm_sg_index *
-+				  sizeof(*sg_table));
-+	}
-+
-+	dpaa2_fl_set_len(out_fle, out_len);
-+
-+	return edesc;
-+}
-+
-+static struct tls_edesc *tls_edesc_alloc(struct aead_request *req,
-+					 bool encrypt)
-+{
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	unsigned int blocksize = crypto_aead_blocksize(tls);
-+	unsigned int padsize, authsize;
-+	struct caam_request *req_ctx = aead_request_ctx(req);
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	struct caam_aead_alg *alg = container_of(crypto_aead_alg(tls),
-+						 typeof(*alg), aead);
-+	struct device *dev = ctx->dev;
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
-+	struct tls_edesc *edesc;
-+	dma_addr_t qm_sg_dma, iv_dma = 0;
-+	int ivsize = 0;
-+	u8 *iv;
-+	int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes;
-+	int in_len, out_len;
-+	struct dpaa2_sg_entry *sg_table;
-+	struct scatterlist *dst;
-+
-+	if (encrypt) {
-+		padsize = blocksize - ((req->cryptlen + ctx->authsize) %
-+					blocksize);
-+		authsize = ctx->authsize + padsize;
-+	} else {
-+		authsize = ctx->authsize;
-+	}
-+
-+	/* allocate space for base edesc, link tables and IV */
-+	edesc = qi_cache_zalloc(GFP_DMA | flags);
-+	if (unlikely(!edesc)) {
-+		dev_err(dev, "could not allocate extended descriptor\n");
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	if (likely(req->src == req->dst)) {
-+		src_nents = sg_nents_for_len(req->src, req->assoclen +
-+					     req->cryptlen +
-+					     (encrypt ? authsize : 0));
-+		if (unlikely(src_nents < 0)) {
-+			dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
-+				req->assoclen + req->cryptlen +
-+				(encrypt ? authsize : 0));
-+			qi_cache_free(edesc);
-+			return ERR_PTR(src_nents);
-+		}
-+
-+		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
-+					      DMA_BIDIRECTIONAL);
-+		if (unlikely(!mapped_src_nents)) {
-+			dev_err(dev, "unable to map source\n");
-+			qi_cache_free(edesc);
-+			return ERR_PTR(-ENOMEM);
-+		}
-+		dst = req->dst;
-+	} else {
-+		src_nents = sg_nents_for_len(req->src, req->assoclen +
-+					     req->cryptlen);
-+		if (unlikely(src_nents < 0)) {
-+			dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
-+				req->assoclen + req->cryptlen);
-+			qi_cache_free(edesc);
-+			return ERR_PTR(src_nents);
-+		}
-+
-+		dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen);
-+		dst_nents = sg_nents_for_len(dst, req->cryptlen +
-+					     (encrypt ? authsize : 0));
-+		if (unlikely(dst_nents < 0)) {
-+			dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
-+				req->cryptlen +
-+				(encrypt ? authsize : 0));
-+			qi_cache_free(edesc);
-+			return ERR_PTR(dst_nents);
-+		}
-+
-+		if (src_nents) {
-+			mapped_src_nents = dma_map_sg(dev, req->src,
-+						      src_nents, DMA_TO_DEVICE);
-+			if (unlikely(!mapped_src_nents)) {
-+				dev_err(dev, "unable to map source\n");
-+				qi_cache_free(edesc);
-+				return ERR_PTR(-ENOMEM);
-+			}
-+		} else {
-+			mapped_src_nents = 0;
-+		}
-+
-+		mapped_dst_nents = dma_map_sg(dev, dst, dst_nents,
-+					      DMA_FROM_DEVICE);
-+		if (unlikely(!mapped_dst_nents)) {
-+			dev_err(dev, "unable to map destination\n");
-+			dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE);
-+			qi_cache_free(edesc);
-+			return ERR_PTR(-ENOMEM);
-+		}
-+	}
-+
-+	/*
-+	 * Create S/G table: IV, src, dst.
-+	 * Input is not contiguous.
-+	 */
-+	qm_sg_ents = 1 + mapped_src_nents +
-+		     (mapped_dst_nents > 1 ? mapped_dst_nents : 0);
-+	sg_table = &edesc->sgt[0];
-+	qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
-+
-+	ivsize = crypto_aead_ivsize(tls);
-+	iv = (u8 *)(sg_table + qm_sg_ents);
-+	/* Make sure IV is located in a DMAable area */
-+	memcpy(iv, req->iv, ivsize);
-+	iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, iv_dma)) {
-+		dev_err(dev, "unable to map IV\n");
-+		caam_unmap(dev, req->src, dst, src_nents, dst_nents, 0, 0, 0,
-+			   0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	edesc->src_nents = src_nents;
-+	edesc->dst_nents = dst_nents;
-+	edesc->dst = dst;
-+	edesc->iv_dma = iv_dma;
-+
-+	dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
-+	qm_sg_index = 1;
-+
-+	sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0);
-+	qm_sg_index += mapped_src_nents;
-+
-+	if (mapped_dst_nents > 1)
-+		sg_to_qm_sg_last(dst, mapped_dst_nents, sg_table +
-+				 qm_sg_index, 0);
-+
-+	qm_sg_dma = dma_map_single(dev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, qm_sg_dma)) {
-+		dev_err(dev, "unable to map S/G table\n");
-+		caam_unmap(dev, req->src, dst, src_nents, dst_nents, iv_dma,
-+			   ivsize, 0, 0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	edesc->qm_sg_dma = qm_sg_dma;
-+	edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+	out_len = req->cryptlen + (encrypt ? authsize : 0);
-+	in_len = ivsize + req->assoclen + req->cryptlen;
-+
-+	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+	dpaa2_fl_set_addr(in_fle, qm_sg_dma);
-+	dpaa2_fl_set_len(in_fle, in_len);
-+
-+	if (req->dst == req->src) {
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
-+		dpaa2_fl_set_addr(out_fle, qm_sg_dma +
-+				  (sg_nents_for_len(req->src, req->assoclen) +
-+				   1) * sizeof(*sg_table));
-+	} else if (mapped_dst_nents == 1) {
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+		dpaa2_fl_set_addr(out_fle, sg_dma_address(dst));
-+	} else {
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
-+		dpaa2_fl_set_addr(out_fle, qm_sg_dma + qm_sg_index *
-+				  sizeof(*sg_table));
-+	}
-+
-+	dpaa2_fl_set_len(out_fle, out_len);
-+
-+	return edesc;
-+}
-+
-+static int tls_set_sh_desc(struct crypto_aead *tls)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	unsigned int ivsize = crypto_aead_ivsize(tls);
-+	unsigned int blocksize = crypto_aead_blocksize(tls);
-+	struct device *dev = ctx->dev;
-+	struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
-+	struct caam_flc *flc;
-+	u32 *desc;
-+	unsigned int assoclen = 13; /* always 13 bytes for TLS */
-+	unsigned int data_len[2];
-+	u32 inl_mask;
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	/*
-+	 * TLS 1.0 encrypt shared descriptor
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	data_len[0] = ctx->adata.keylen_pad;
-+	data_len[1] = ctx->cdata.keylen;
-+
-+	if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len,
-+			      &inl_mask, ARRAY_SIZE(data_len)) < 0)
-+		return -EINVAL;
-+
-+	if (inl_mask & 1)
-+		ctx->adata.key_virt = ctx->key;
-+	else
-+		ctx->adata.key_dma = ctx->key_dma;
-+
-+	if (inl_mask & 2)
-+		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
-+	else
-+		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
-+
-+	ctx->adata.key_inline = !!(inl_mask & 1);
-+	ctx->cdata.key_inline = !!(inl_mask & 2);
-+
-+	flc = &ctx->flc[ENCRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_tls_encap(desc, &ctx->cdata, &ctx->adata,
-+			      assoclen, ivsize, ctx->authsize, blocksize,
-+			      priv->sec_attr.era);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc));
-+	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	/*
-+	 * TLS 1.0 decrypt shared descriptor
-+	 * Keys do not fit inline, regardless of algorithms used
-+	 */
-+	ctx->adata.key_inline = false;
-+	ctx->adata.key_dma = ctx->key_dma;
-+	ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
-+
-+	flc = &ctx->flc[DECRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_tls_decap(desc, &ctx->cdata, &ctx->adata, assoclen, ivsize,
-+			      ctx->authsize, blocksize, priv->sec_attr.era);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	return 0;
-+}
-+
-+static int tls_setkey(struct crypto_aead *tls, const u8 *key,
-+		      unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	struct device *dev = ctx->dev;
-+	struct crypto_authenc_keys keys;
-+
-+	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
-+		goto badkey;
-+
-+#ifdef DEBUG
-+	dev_err(dev, "keylen %d enckeylen %d authkeylen %d\n",
-+		keys.authkeylen + keys.enckeylen, keys.enckeylen,
-+		keys.authkeylen);
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	ctx->adata.keylen = keys.authkeylen;
-+	ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
-+					      OP_ALG_ALGSEL_MASK);
-+
-+	if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
-+		goto badkey;
-+
-+	memcpy(ctx->key, keys.authkey, keys.authkeylen);
-+	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
-+	dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad +
-+				   keys.enckeylen, ctx->dir);
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
-+		       ctx->adata.keylen_pad + keys.enckeylen, 1);
-+#endif
-+
-+	ctx->cdata.keylen = keys.enckeylen;
-+
-+	return tls_set_sh_desc(tls);
-+badkey:
-+	crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+	return -EINVAL;
-+}
-+
-+static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+
-+	ctx->authsize = authsize;
-+	tls_set_sh_desc(tls);
-+
-+	return 0;
-+}
-+
-+static int gcm_set_sh_desc(struct crypto_aead *aead)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *dev = ctx->dev;
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
-+	struct caam_flc *flc;
-+	u32 *desc;
-+	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
-+			ctx->cdata.keylen;
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	/*
-+	 * AES GCM encrypt shared descriptor
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_GCM_ENC_LEN) {
-+		ctx->cdata.key_inline = true;
-+		ctx->cdata.key_virt = ctx->key;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	flc = &ctx->flc[ENCRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ivsize, ctx->authsize, true);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptors
-+	 * must all fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_GCM_DEC_LEN) {
-+		ctx->cdata.key_inline = true;
-+		ctx->cdata.key_virt = ctx->key;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	flc = &ctx->flc[DECRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ivsize, ctx->authsize, true);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	return 0;
-+}
-+
-+static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
-+
-+	ctx->authsize = authsize;
-+	gcm_set_sh_desc(authenc);
-+
-+	return 0;
-+}
-+
-+static int gcm_setkey(struct crypto_aead *aead,
-+		      const u8 *key, unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *dev = ctx->dev;
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	memcpy(ctx->key, key, keylen);
-+	dma_sync_single_for_device(dev, ctx->key_dma, keylen, ctx->dir);
-+	ctx->cdata.keylen = keylen;
-+
-+	return gcm_set_sh_desc(aead);
-+}
-+
-+static int rfc4106_set_sh_desc(struct crypto_aead *aead)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *dev = ctx->dev;
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
-+	struct caam_flc *flc;
-+	u32 *desc;
-+	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
-+			ctx->cdata.keylen;
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	ctx->cdata.key_virt = ctx->key;
-+
-+	/*
-+	 * RFC4106 encrypt shared descriptor
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_RFC4106_ENC_LEN) {
-+		ctx->cdata.key_inline = true;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	flc = &ctx->flc[ENCRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
-+				  true);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptors
-+	 * must all fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_RFC4106_DEC_LEN) {
-+		ctx->cdata.key_inline = true;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	flc = &ctx->flc[DECRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
-+				  true);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	return 0;
-+}
-+
-+static int rfc4106_setauthsize(struct crypto_aead *authenc,
-+			       unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
-+
-+	ctx->authsize = authsize;
-+	rfc4106_set_sh_desc(authenc);
-+
-+	return 0;
-+}
-+
-+static int rfc4106_setkey(struct crypto_aead *aead,
-+			  const u8 *key, unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *dev = ctx->dev;
-+
-+	if (keylen < 4)
-+		return -EINVAL;
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	memcpy(ctx->key, key, keylen);
-+	/*
-+	 * The last four bytes of the key material are used as the salt value
-+	 * in the nonce. Update the AES key length.
-+	 */
-+	ctx->cdata.keylen = keylen - 4;
-+	dma_sync_single_for_device(dev, ctx->key_dma, ctx->cdata.keylen,
-+				   ctx->dir);
-+
-+	return rfc4106_set_sh_desc(aead);
-+}
-+
-+static int rfc4543_set_sh_desc(struct crypto_aead *aead)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *dev = ctx->dev;
-+	unsigned int ivsize = crypto_aead_ivsize(aead);
-+	struct caam_flc *flc;
-+	u32 *desc;
-+	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
-+			ctx->cdata.keylen;
-+
-+	if (!ctx->cdata.keylen || !ctx->authsize)
-+		return 0;
-+
-+	ctx->cdata.key_virt = ctx->key;
-+
-+	/*
-+	 * RFC4543 encrypt shared descriptor
-+	 * Job Descriptor and Shared Descriptor
-+	 * must fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_RFC4543_ENC_LEN) {
-+		ctx->cdata.key_inline = true;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	flc = &ctx->flc[ENCRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
-+				  true);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	/*
-+	 * Job Descriptor and Shared Descriptors
-+	 * must all fit into the 64-word Descriptor h/w Buffer
-+	 */
-+	if (rem_bytes >= DESC_QI_RFC4543_DEC_LEN) {
-+		ctx->cdata.key_inline = true;
-+	} else {
-+		ctx->cdata.key_inline = false;
-+		ctx->cdata.key_dma = ctx->key_dma;
-+	}
-+
-+	flc = &ctx->flc[DECRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
-+				  true);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	return 0;
-+}
-+
-+static int rfc4543_setauthsize(struct crypto_aead *authenc,
-+			       unsigned int authsize)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
-+
-+	ctx->authsize = authsize;
-+	rfc4543_set_sh_desc(authenc);
-+
-+	return 0;
-+}
-+
-+static int rfc4543_setkey(struct crypto_aead *aead,
-+			  const u8 *key, unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct device *dev = ctx->dev;
-+
-+	if (keylen < 4)
-+		return -EINVAL;
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+
-+	memcpy(ctx->key, key, keylen);
-+	/*
-+	 * The last four bytes of the key material are used as the salt value
-+	 * in the nonce. Update the AES key length.
-+	 */
-+	ctx->cdata.keylen = keylen - 4;
-+	dma_sync_single_for_device(dev, ctx->key_dma, ctx->cdata.keylen,
-+				   ctx->dir);
-+
-+	return rfc4543_set_sh_desc(aead);
-+}
-+
-+static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
-+			   unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
-+	struct caam_skcipher_alg *alg =
-+		container_of(crypto_skcipher_alg(skcipher),
-+			     struct caam_skcipher_alg, skcipher);
-+	struct device *dev = ctx->dev;
-+	struct caam_flc *flc;
-+	unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
-+	u32 *desc;
-+	u32 ctx1_iv_off = 0;
-+	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
-+			       OP_ALG_AAI_CTR_MOD128);
-+	const bool is_rfc3686 = alg->caam.rfc3686;
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
-+#endif
-+	/*
-+	 * AES-CTR needs to load IV in CONTEXT1 reg
-+	 * at an offset of 128bits (16bytes)
-+	 * CONTEXT1[255:128] = IV
-+	 */
-+	if (ctr_mode)
-+		ctx1_iv_off = 16;
-+
-+	/*
-+	 * RFC3686 specific:
-+	 *	| CONTEXT1[255:128] = {NONCE, IV, COUNTER}
-+	 *	| *key = {KEY, NONCE}
-+	 */
-+	if (is_rfc3686) {
-+		ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
-+		keylen -= CTR_RFC3686_NONCE_SIZE;
-+	}
-+
-+	ctx->cdata.keylen = keylen;
-+	ctx->cdata.key_virt = key;
-+	ctx->cdata.key_inline = true;
-+
-+	/* skcipher_encrypt shared descriptor */
-+	flc = &ctx->flc[ENCRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_ablkcipher_encap(desc, &ctx->cdata, ivsize,
-+				     is_rfc3686, ctx1_iv_off);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	/* skcipher_decrypt shared descriptor */
-+	flc = &ctx->flc[DECRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_ablkcipher_decap(desc, &ctx->cdata, ivsize,
-+				     is_rfc3686, ctx1_iv_off);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	return 0;
-+}
-+
-+static int xts_skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
-+			       unsigned int keylen)
-+{
-+	struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
-+	struct device *dev = ctx->dev;
-+	struct caam_flc *flc;
-+	u32 *desc;
-+
-+	if (keylen != 2 * AES_MIN_KEY_SIZE  && keylen != 2 * AES_MAX_KEY_SIZE) {
-+		dev_err(dev, "key size mismatch\n");
-+		crypto_skcipher_set_flags(skcipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+		return -EINVAL;
-+	}
-+
-+	ctx->cdata.keylen = keylen;
-+	ctx->cdata.key_virt = key;
-+	ctx->cdata.key_inline = true;
-+
-+	/* xts_skcipher_encrypt shared descriptor */
-+	flc = &ctx->flc[ENCRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_xts_ablkcipher_encap(desc, &ctx->cdata);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	/* xts_skcipher_decrypt shared descriptor */
-+	flc = &ctx->flc[DECRYPT];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_xts_ablkcipher_decap(desc, &ctx->cdata);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
-+				   sizeof(flc->flc) + desc_bytes(desc),
-+				   ctx->dir);
-+
-+	return 0;
-+}
-+
-+static struct skcipher_edesc *skcipher_edesc_alloc(struct skcipher_request *req)
-+{
-+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
-+	struct caam_request *req_ctx = skcipher_request_ctx(req);
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
-+	struct device *dev = ctx->dev;
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		       GFP_KERNEL : GFP_ATOMIC;
-+	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
-+	struct skcipher_edesc *edesc;
-+	dma_addr_t iv_dma;
-+	u8 *iv;
-+	int ivsize = crypto_skcipher_ivsize(skcipher);
-+	int dst_sg_idx, qm_sg_ents, qm_sg_bytes;
-+	struct dpaa2_sg_entry *sg_table;
-+
-+	src_nents = sg_nents_for_len(req->src, req->cryptlen);
-+	if (unlikely(src_nents < 0)) {
-+		dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
-+			req->cryptlen);
-+		return ERR_PTR(src_nents);
-+	}
-+
-+	if (unlikely(req->dst != req->src)) {
-+		dst_nents = sg_nents_for_len(req->dst, req->cryptlen);
-+		if (unlikely(dst_nents < 0)) {
-+			dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
-+				req->cryptlen);
-+			return ERR_PTR(dst_nents);
-+		}
-+
-+		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
-+					      DMA_TO_DEVICE);
-+		if (unlikely(!mapped_src_nents)) {
-+			dev_err(dev, "unable to map source\n");
-+			return ERR_PTR(-ENOMEM);
-+		}
-+
-+		mapped_dst_nents = dma_map_sg(dev, req->dst, dst_nents,
-+					      DMA_FROM_DEVICE);
-+		if (unlikely(!mapped_dst_nents)) {
-+			dev_err(dev, "unable to map destination\n");
-+			dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE);
-+			return ERR_PTR(-ENOMEM);
-+		}
-+	} else {
-+		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
-+					      DMA_BIDIRECTIONAL);
-+		if (unlikely(!mapped_src_nents)) {
-+			dev_err(dev, "unable to map source\n");
-+			return ERR_PTR(-ENOMEM);
-+		}
-+	}
-+
-+	qm_sg_ents = 1 + mapped_src_nents;
-+	dst_sg_idx = qm_sg_ents;
-+
-+	qm_sg_ents += mapped_dst_nents > 1 ? mapped_dst_nents : 0;
-+	qm_sg_bytes = qm_sg_ents * sizeof(struct dpaa2_sg_entry);
-+	if (unlikely(offsetof(struct skcipher_edesc, sgt) + qm_sg_bytes +
-+		     ivsize > CAAM_QI_MEMCACHE_SIZE)) {
-+		dev_err(dev, "No space for %d S/G entries and/or %dB IV\n",
-+			qm_sg_ents, ivsize);
-+		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
-+			   0, 0, 0);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	/* allocate space for base edesc, link tables and IV */
-+	edesc = qi_cache_zalloc(GFP_DMA | flags);
-+	if (unlikely(!edesc)) {
-+		dev_err(dev, "could not allocate extended descriptor\n");
-+		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
-+			   0, 0, 0);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	/* Make sure IV is located in a DMAable area */
-+	sg_table = &edesc->sgt[0];
-+	iv = (u8 *)(sg_table + qm_sg_ents);
-+	memcpy(iv, req->iv, ivsize);
-+
-+	iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, iv_dma)) {
-+		dev_err(dev, "unable to map IV\n");
-+		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
-+			   0, 0, 0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	edesc->src_nents = src_nents;
-+	edesc->dst_nents = dst_nents;
-+	edesc->iv_dma = iv_dma;
-+	edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+	dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
-+	sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + 1, 0);
-+
-+	if (mapped_dst_nents > 1)
-+		sg_to_qm_sg_last(req->dst, mapped_dst_nents, sg_table +
-+				 dst_sg_idx, 0);
-+
-+	edesc->qm_sg_dma = dma_map_single(dev, sg_table, edesc->qm_sg_bytes,
-+					  DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, edesc->qm_sg_dma)) {
-+		dev_err(dev, "unable to map S/G table\n");
-+		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
-+			   iv_dma, ivsize, 0, 0);
-+		qi_cache_free(edesc);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+
-+	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_len(in_fle, req->cryptlen + ivsize);
-+	dpaa2_fl_set_len(out_fle, req->cryptlen);
-+
-+	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+	dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
-+
-+	if (req->src == req->dst) {
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
-+		dpaa2_fl_set_addr(out_fle, edesc->qm_sg_dma +
-+				  sizeof(*sg_table));
-+	} else if (mapped_dst_nents > 1) {
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
-+		dpaa2_fl_set_addr(out_fle, edesc->qm_sg_dma + dst_sg_idx *
-+				  sizeof(*sg_table));
-+	} else {
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+		dpaa2_fl_set_addr(out_fle, sg_dma_address(req->dst));
-+	}
-+
-+	return edesc;
-+}
-+
-+static void aead_unmap(struct device *dev, struct aead_edesc *edesc,
-+		       struct aead_request *req)
-+{
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	int ivsize = crypto_aead_ivsize(aead);
-+
-+	caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
-+		   edesc->iv_dma, ivsize, edesc->qm_sg_dma, edesc->qm_sg_bytes);
-+	dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
-+}
-+
-+static void tls_unmap(struct device *dev, struct tls_edesc *edesc,
-+		      struct aead_request *req)
-+{
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	int ivsize = crypto_aead_ivsize(tls);
-+
-+	caam_unmap(dev, req->src, edesc->dst, edesc->src_nents,
-+		   edesc->dst_nents, edesc->iv_dma, ivsize, edesc->qm_sg_dma,
-+		   edesc->qm_sg_bytes);
-+}
-+
-+static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc,
-+			   struct skcipher_request *req)
-+{
-+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
-+	int ivsize = crypto_skcipher_ivsize(skcipher);
-+
-+	caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
-+		   edesc->iv_dma, ivsize, edesc->qm_sg_dma, edesc->qm_sg_bytes);
-+}
-+
-+static void aead_encrypt_done(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct aead_request *req = container_of(areq, struct aead_request,
-+						base);
-+	struct caam_request *req_ctx = to_caam_req(areq);
-+	struct aead_edesc *edesc = req_ctx->edesc;
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	int ecode = 0;
-+
-+#ifdef DEBUG
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		ecode = -EIO;
-+	}
-+
-+	aead_unmap(ctx->dev, edesc, req);
-+	qi_cache_free(edesc);
-+	aead_request_complete(req, ecode);
-+}
-+
-+static void aead_decrypt_done(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct aead_request *req = container_of(areq, struct aead_request,
-+						base);
-+	struct caam_request *req_ctx = to_caam_req(areq);
-+	struct aead_edesc *edesc = req_ctx->edesc;
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	int ecode = 0;
-+
-+#ifdef DEBUG
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		/*
-+		 * verify hw auth check passed else return -EBADMSG
-+		 */
-+		if ((status & JRSTA_CCBERR_ERRID_MASK) ==
-+		     JRSTA_CCBERR_ERRID_ICVCHK)
-+			ecode = -EBADMSG;
-+		else
-+			ecode = -EIO;
-+	}
-+
-+	aead_unmap(ctx->dev, edesc, req);
-+	qi_cache_free(edesc);
-+	aead_request_complete(req, ecode);
-+}
-+
-+static int aead_encrypt(struct aead_request *req)
-+{
-+	struct aead_edesc *edesc;
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct caam_request *caam_req = aead_request_ctx(req);
-+	int ret;
-+
-+	/* allocate extended descriptor */
-+	edesc = aead_edesc_alloc(req, true);
-+	if (IS_ERR(edesc))
-+		return PTR_ERR(edesc);
-+
-+	caam_req->flc = &ctx->flc[ENCRYPT];
-+	caam_req->flc_dma = ctx->flc_dma[ENCRYPT];
-+	caam_req->cbk = aead_encrypt_done;
-+	caam_req->ctx = &req->base;
-+	caam_req->edesc = edesc;
-+	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
-+	if (ret != -EINPROGRESS &&
-+	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
-+		aead_unmap(ctx->dev, edesc, req);
-+		qi_cache_free(edesc);
-+	}
-+
-+	return ret;
-+}
-+
-+static int aead_decrypt(struct aead_request *req)
-+{
-+	struct aead_edesc *edesc;
-+	struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(aead);
-+	struct caam_request *caam_req = aead_request_ctx(req);
-+	int ret;
-+
-+	/* allocate extended descriptor */
-+	edesc = aead_edesc_alloc(req, false);
-+	if (IS_ERR(edesc))
-+		return PTR_ERR(edesc);
-+
-+	caam_req->flc = &ctx->flc[DECRYPT];
-+	caam_req->flc_dma = ctx->flc_dma[DECRYPT];
-+	caam_req->cbk = aead_decrypt_done;
-+	caam_req->ctx = &req->base;
-+	caam_req->edesc = edesc;
-+	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
-+	if (ret != -EINPROGRESS &&
-+	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
-+		aead_unmap(ctx->dev, edesc, req);
-+		qi_cache_free(edesc);
-+	}
-+
-+	return ret;
-+}
-+
-+static void tls_encrypt_done(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct aead_request *req = container_of(areq, struct aead_request,
-+						base);
-+	struct caam_request *req_ctx = to_caam_req(areq);
-+	struct tls_edesc *edesc = req_ctx->edesc;
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	int ecode = 0;
-+
-+#ifdef DEBUG
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		ecode = -EIO;
-+	}
-+
-+	tls_unmap(ctx->dev, edesc, req);
-+	qi_cache_free(edesc);
-+	aead_request_complete(req, ecode);
-+}
-+
-+static void tls_decrypt_done(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct aead_request *req = container_of(areq, struct aead_request,
-+						base);
-+	struct caam_request *req_ctx = to_caam_req(areq);
-+	struct tls_edesc *edesc = req_ctx->edesc;
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	int ecode = 0;
-+
-+#ifdef DEBUG
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		/*
-+		 * verify hw auth check passed else return -EBADMSG
-+		 */
-+		if ((status & JRSTA_CCBERR_ERRID_MASK) ==
-+		     JRSTA_CCBERR_ERRID_ICVCHK)
-+			ecode = -EBADMSG;
-+		else
-+			ecode = -EIO;
-+	}
-+
-+	tls_unmap(ctx->dev, edesc, req);
-+	qi_cache_free(edesc);
-+	aead_request_complete(req, ecode);
-+}
-+
-+static int tls_encrypt(struct aead_request *req)
-+{
-+	struct tls_edesc *edesc;
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	struct caam_request *caam_req = aead_request_ctx(req);
-+	int ret;
-+
-+	/* allocate extended descriptor */
-+	edesc = tls_edesc_alloc(req, true);
-+	if (IS_ERR(edesc))
-+		return PTR_ERR(edesc);
-+
-+	caam_req->flc = &ctx->flc[ENCRYPT];
-+	caam_req->flc_dma = ctx->flc_dma[ENCRYPT];
-+	caam_req->cbk = tls_encrypt_done;
-+	caam_req->ctx = &req->base;
-+	caam_req->edesc = edesc;
-+	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
-+	if (ret != -EINPROGRESS &&
-+	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
-+		tls_unmap(ctx->dev, edesc, req);
-+		qi_cache_free(edesc);
-+	}
-+
-+	return ret;
-+}
-+
-+static int tls_decrypt(struct aead_request *req)
-+{
-+	struct tls_edesc *edesc;
-+	struct crypto_aead *tls = crypto_aead_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_aead_ctx(tls);
-+	struct caam_request *caam_req = aead_request_ctx(req);
-+	int ret;
-+
-+	/* allocate extended descriptor */
-+	edesc = tls_edesc_alloc(req, false);
-+	if (IS_ERR(edesc))
-+		return PTR_ERR(edesc);
-+
-+	caam_req->flc = &ctx->flc[DECRYPT];
-+	caam_req->flc_dma = ctx->flc_dma[DECRYPT];
-+	caam_req->cbk = tls_decrypt_done;
-+	caam_req->ctx = &req->base;
-+	caam_req->edesc = edesc;
-+	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
-+	if (ret != -EINPROGRESS &&
-+	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
-+		tls_unmap(ctx->dev, edesc, req);
-+		qi_cache_free(edesc);
-+	}
-+
-+	return ret;
-+}
-+
-+static int ipsec_gcm_encrypt(struct aead_request *req)
-+{
-+	if (req->assoclen < 8)
-+		return -EINVAL;
-+
-+	return aead_encrypt(req);
-+}
-+
-+static int ipsec_gcm_decrypt(struct aead_request *req)
-+{
-+	if (req->assoclen < 8)
-+		return -EINVAL;
-+
-+	return aead_decrypt(req);
-+}
-+
-+static void skcipher_encrypt_done(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct skcipher_request *req = skcipher_request_cast(areq);
-+	struct caam_request *req_ctx = to_caam_req(areq);
-+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
-+	struct skcipher_edesc *edesc = req_ctx->edesc;
-+	int ecode = 0;
-+	int ivsize = crypto_skcipher_ivsize(skcipher);
-+
-+#ifdef DEBUG
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		ecode = -EIO;
-+	}
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "dstiv  @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
-+		       edesc->src_nents > 1 ? 100 : ivsize, 1);
-+	caam_dump_sg(KERN_ERR, "dst    @" __stringify(__LINE__)": ",
-+		     DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
-+		     edesc->dst_nents > 1 ? 100 : req->cryptlen, 1);
-+#endif
-+
-+	skcipher_unmap(ctx->dev, edesc, req);
-+
-+	/*
-+	 * The crypto API expects us to set the IV (req->iv) to the last
-+	 * ciphertext block. This is used e.g. by the CTS mode.
-+	 */
-+	scatterwalk_map_and_copy(req->iv, req->dst, req->cryptlen - ivsize,
-+				 ivsize, 0);
-+
-+	qi_cache_free(edesc);
-+	skcipher_request_complete(req, ecode);
-+}
-+
-+static void skcipher_decrypt_done(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct skcipher_request *req = skcipher_request_cast(areq);
-+	struct caam_request *req_ctx = to_caam_req(areq);
-+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
-+	struct skcipher_edesc *edesc = req_ctx->edesc;
-+	int ecode = 0;
-+#ifdef DEBUG
-+	int ivsize = crypto_skcipher_ivsize(skcipher);
-+
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		ecode = -EIO;
-+	}
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "dstiv  @" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
-+		       edesc->src_nents > 1 ? 100 : ivsize, 1);
-+	caam_dump_sg(KERN_ERR, "dst    @" __stringify(__LINE__)": ",
-+		     DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
-+		     edesc->dst_nents > 1 ? 100 : req->cryptlen, 1);
-+#endif
-+
-+	skcipher_unmap(ctx->dev, edesc, req);
-+	qi_cache_free(edesc);
-+	skcipher_request_complete(req, ecode);
-+}
-+
-+static int skcipher_encrypt(struct skcipher_request *req)
-+{
-+	struct skcipher_edesc *edesc;
-+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
-+	struct caam_request *caam_req = skcipher_request_ctx(req);
-+	int ret;
-+
-+	/* allocate extended descriptor */
-+	edesc = skcipher_edesc_alloc(req);
-+	if (IS_ERR(edesc))
-+		return PTR_ERR(edesc);
-+
-+	caam_req->flc = &ctx->flc[ENCRYPT];
-+	caam_req->flc_dma = ctx->flc_dma[ENCRYPT];
-+	caam_req->cbk = skcipher_encrypt_done;
-+	caam_req->ctx = &req->base;
-+	caam_req->edesc = edesc;
-+	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
-+	if (ret != -EINPROGRESS &&
-+	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
-+		skcipher_unmap(ctx->dev, edesc, req);
-+		qi_cache_free(edesc);
-+	}
-+
-+	return ret;
-+}
-+
-+static int skcipher_decrypt(struct skcipher_request *req)
-+{
-+	struct skcipher_edesc *edesc;
-+	struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
-+	struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
-+	struct caam_request *caam_req = skcipher_request_ctx(req);
-+	int ivsize = crypto_skcipher_ivsize(skcipher);
-+	int ret;
-+
-+	/* allocate extended descriptor */
-+	edesc = skcipher_edesc_alloc(req);
-+	if (IS_ERR(edesc))
-+		return PTR_ERR(edesc);
-+
-+	/*
-+	 * The crypto API expects us to set the IV (req->iv) to the last
-+	 * ciphertext block.
-+	 */
-+	scatterwalk_map_and_copy(req->iv, req->src, req->cryptlen - ivsize,
-+				 ivsize, 0);
-+
-+	caam_req->flc = &ctx->flc[DECRYPT];
-+	caam_req->flc_dma = ctx->flc_dma[DECRYPT];
-+	caam_req->cbk = skcipher_decrypt_done;
-+	caam_req->ctx = &req->base;
-+	caam_req->edesc = edesc;
-+	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
-+	if (ret != -EINPROGRESS &&
-+	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
-+		skcipher_unmap(ctx->dev, edesc, req);
-+		qi_cache_free(edesc);
-+	}
-+
-+	return ret;
-+}
-+
-+static int caam_cra_init(struct caam_ctx *ctx, struct caam_alg_entry *caam,
-+			 bool uses_dkp)
-+{
-+	dma_addr_t dma_addr;
-+	int i;
-+
-+	/* copy descriptor header template value */
-+	ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
-+	ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
-+
-+	ctx->dev = caam->dev;
-+	ctx->dir = uses_dkp ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
-+
-+	dma_addr = dma_map_single_attrs(ctx->dev, ctx->flc,
-+					offsetof(struct caam_ctx, flc_dma),
-+					ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
-+	if (dma_mapping_error(ctx->dev, dma_addr)) {
-+		dev_err(ctx->dev, "unable to map key, shared descriptors\n");
-+		return -ENOMEM;
-+	}
-+
-+	for (i = 0; i < NUM_OP; i++)
-+		ctx->flc_dma[i] = dma_addr + i * sizeof(ctx->flc[i]);
-+	ctx->key_dma = dma_addr + NUM_OP * sizeof(ctx->flc[0]);
-+
-+	return 0;
-+}
-+
-+static int caam_cra_init_skcipher(struct crypto_skcipher *tfm)
-+{
-+	struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
-+	struct caam_skcipher_alg *caam_alg =
-+		container_of(alg, typeof(*caam_alg), skcipher);
-+
-+	crypto_skcipher_set_reqsize(tfm, sizeof(struct caam_request));
-+	return caam_cra_init(crypto_skcipher_ctx(tfm), &caam_alg->caam, false);
-+}
-+
-+static int caam_cra_init_aead(struct crypto_aead *tfm)
-+{
-+	struct aead_alg *alg = crypto_aead_alg(tfm);
-+	struct caam_aead_alg *caam_alg = container_of(alg, typeof(*caam_alg),
-+						      aead);
-+
-+	crypto_aead_set_reqsize(tfm, sizeof(struct caam_request));
-+	return caam_cra_init(crypto_aead_ctx(tfm), &caam_alg->caam,
-+			     (alg->setkey == aead_setkey) ||
-+			     (alg->setkey == tls_setkey));
-+}
-+
-+static void caam_exit_common(struct caam_ctx *ctx)
-+{
-+	dma_unmap_single_attrs(ctx->dev, ctx->flc_dma[0],
-+			       offsetof(struct caam_ctx, flc_dma), ctx->dir,
-+			       DMA_ATTR_SKIP_CPU_SYNC);
-+}
-+
-+static void caam_cra_exit(struct crypto_skcipher *tfm)
-+{
-+	caam_exit_common(crypto_skcipher_ctx(tfm));
-+}
-+
-+static void caam_cra_exit_aead(struct crypto_aead *tfm)
-+{
-+	caam_exit_common(crypto_aead_ctx(tfm));
-+}
-+
-+static struct caam_skcipher_alg driver_algs[] = {
-+	{
-+		.skcipher = {
-+			.base = {
-+				.cra_name = "cbc(aes)",
-+				.cra_driver_name = "cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = skcipher_setkey,
-+			.encrypt = skcipher_encrypt,
-+			.decrypt = skcipher_decrypt,
-+			.min_keysize = AES_MIN_KEY_SIZE,
-+			.max_keysize = AES_MAX_KEY_SIZE,
-+			.ivsize = AES_BLOCK_SIZE,
-+		},
-+		.caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+	},
-+	{
-+		.skcipher = {
-+			.base = {
-+				.cra_name = "cbc(des3_ede)",
-+				.cra_driver_name = "cbc-3des-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = skcipher_setkey,
-+			.encrypt = skcipher_encrypt,
-+			.decrypt = skcipher_decrypt,
-+			.min_keysize = DES3_EDE_KEY_SIZE,
-+			.max_keysize = DES3_EDE_KEY_SIZE,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+		},
-+		.caam.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+	},
-+	{
-+		.skcipher = {
-+			.base = {
-+				.cra_name = "cbc(des)",
-+				.cra_driver_name = "cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = skcipher_setkey,
-+			.encrypt = skcipher_encrypt,
-+			.decrypt = skcipher_decrypt,
-+			.min_keysize = DES_KEY_SIZE,
-+			.max_keysize = DES_KEY_SIZE,
-+			.ivsize = DES_BLOCK_SIZE,
-+		},
-+		.caam.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+	},
-+	{
-+		.skcipher = {
-+			.base = {
-+				.cra_name = "ctr(aes)",
-+				.cra_driver_name = "ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = skcipher_setkey,
-+			.encrypt = skcipher_encrypt,
-+			.decrypt = skcipher_decrypt,
-+			.min_keysize = AES_MIN_KEY_SIZE,
-+			.max_keysize = AES_MAX_KEY_SIZE,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.chunksize = AES_BLOCK_SIZE,
-+		},
-+		.caam.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					OP_ALG_AAI_CTR_MOD128,
-+	},
-+	{
-+		.skcipher = {
-+			.base = {
-+				.cra_name = "rfc3686(ctr(aes))",
-+				.cra_driver_name = "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = skcipher_setkey,
-+			.encrypt = skcipher_encrypt,
-+			.decrypt = skcipher_decrypt,
-+			.min_keysize = AES_MIN_KEY_SIZE +
-+				       CTR_RFC3686_NONCE_SIZE,
-+			.max_keysize = AES_MAX_KEY_SIZE +
-+				       CTR_RFC3686_NONCE_SIZE,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.chunksize = AES_BLOCK_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.rfc3686 = true,
-+		},
-+	},
-+	{
-+		.skcipher = {
-+			.base = {
-+				.cra_name = "xts(aes)",
-+				.cra_driver_name = "xts-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = xts_skcipher_setkey,
-+			.encrypt = skcipher_encrypt,
-+			.decrypt = skcipher_decrypt,
-+			.min_keysize = 2 * AES_MIN_KEY_SIZE,
-+			.max_keysize = 2 * AES_MAX_KEY_SIZE,
-+			.ivsize = AES_BLOCK_SIZE,
-+		},
-+		.caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS,
-+	}
-+};
-+
-+static struct caam_aead_alg driver_aeads[] = {
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "rfc4106(gcm(aes))",
-+				.cra_driver_name = "rfc4106-gcm-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = rfc4106_setkey,
-+			.setauthsize = rfc4106_setauthsize,
-+			.encrypt = ipsec_gcm_encrypt,
-+			.decrypt = ipsec_gcm_decrypt,
-+			.ivsize = 8,
-+			.maxauthsize = AES_BLOCK_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "rfc4543(gcm(aes))",
-+				.cra_driver_name = "rfc4543-gcm-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = rfc4543_setkey,
-+			.setauthsize = rfc4543_setauthsize,
-+			.encrypt = ipsec_gcm_encrypt,
-+			.decrypt = ipsec_gcm_decrypt,
-+			.ivsize = 8,
-+			.maxauthsize = AES_BLOCK_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
-+		},
-+	},
-+	/* Galois Counter Mode */
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "gcm(aes)",
-+				.cra_driver_name = "gcm-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = gcm_setkey,
-+			.setauthsize = gcm_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = 12,
-+			.maxauthsize = AES_BLOCK_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
-+		}
-+	},
-+	/* single-pass ipsec_esp descriptor */
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(md5),cbc(aes))",
-+				.cra_driver_name = "authenc-hmac-md5-"
-+						   "cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = MD5_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(md5),"
-+					    "cbc(aes)))",
-+				.cra_driver_name = "echainiv-authenc-hmac-md5-"
-+						   "cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = MD5_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha1),cbc(aes))",
-+				.cra_driver_name = "authenc-hmac-sha1-"
-+						   "cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha1),"
-+					    "cbc(aes)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha1-cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha224),cbc(aes))",
-+				.cra_driver_name = "authenc-hmac-sha224-"
-+						   "cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA224_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha224),"
-+					    "cbc(aes)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha224-cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA224_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha256),cbc(aes))",
-+				.cra_driver_name = "authenc-hmac-sha256-"
-+						   "cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA256_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha256),"
-+					    "cbc(aes)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha256-cbc-aes-"
-+						   "caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA256_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha384),cbc(aes))",
-+				.cra_driver_name = "authenc-hmac-sha384-"
-+						   "cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA384_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha384),"
-+					    "cbc(aes)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha384-cbc-aes-"
-+						   "caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA384_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha512),cbc(aes))",
-+				.cra_driver_name = "authenc-hmac-sha512-"
-+						   "cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA512_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha512),"
-+					    "cbc(aes)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha512-cbc-aes-"
-+						   "caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA512_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
-+				.cra_driver_name = "authenc-hmac-md5-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = MD5_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(md5),"
-+					    "cbc(des3_ede)))",
-+				.cra_driver_name = "echainiv-authenc-hmac-md5-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = MD5_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha1),"
-+					    "cbc(des3_ede))",
-+				.cra_driver_name = "authenc-hmac-sha1-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha1),"
-+					    "cbc(des3_ede)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha1-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha224),"
-+					    "cbc(des3_ede))",
-+				.cra_driver_name = "authenc-hmac-sha224-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA224_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha224),"
-+					    "cbc(des3_ede)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha224-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA224_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha256),"
-+					    "cbc(des3_ede))",
-+				.cra_driver_name = "authenc-hmac-sha256-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA256_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha256),"
-+					    "cbc(des3_ede)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha256-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA256_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha384),"
-+					    "cbc(des3_ede))",
-+				.cra_driver_name = "authenc-hmac-sha384-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA384_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha384),"
-+					    "cbc(des3_ede)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha384-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA384_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha512),"
-+					    "cbc(des3_ede))",
-+				.cra_driver_name = "authenc-hmac-sha512-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA512_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha512),"
-+					    "cbc(des3_ede)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha512-"
-+						   "cbc-des3_ede-caam-qi2",
-+				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES3_EDE_BLOCK_SIZE,
-+			.maxauthsize = SHA512_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(md5),cbc(des))",
-+				.cra_driver_name = "authenc-hmac-md5-"
-+						   "cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = MD5_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(md5),"
-+					    "cbc(des)))",
-+				.cra_driver_name = "echainiv-authenc-hmac-md5-"
-+						   "cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = MD5_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha1),cbc(des))",
-+				.cra_driver_name = "authenc-hmac-sha1-"
-+						   "cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha1),"
-+					    "cbc(des)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha1-cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha224),cbc(des))",
-+				.cra_driver_name = "authenc-hmac-sha224-"
-+						   "cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA224_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha224),"
-+					    "cbc(des)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha224-cbc-des-"
-+						   "caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA224_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha256),cbc(des))",
-+				.cra_driver_name = "authenc-hmac-sha256-"
-+						   "cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA256_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha256),"
-+					    "cbc(des)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha256-cbc-desi-"
-+						   "caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA256_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha384),cbc(des))",
-+				.cra_driver_name = "authenc-hmac-sha384-"
-+						   "cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA384_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha384),"
-+					    "cbc(des)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha384-cbc-des-"
-+						   "caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA384_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha512),cbc(des))",
-+				.cra_driver_name = "authenc-hmac-sha512-"
-+						   "cbc-des-caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA512_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "echainiv(authenc(hmac(sha512),"
-+					    "cbc(des)))",
-+				.cra_driver_name = "echainiv-authenc-"
-+						   "hmac-sha512-cbc-des-"
-+						   "caam-qi2",
-+				.cra_blocksize = DES_BLOCK_SIZE,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = DES_BLOCK_SIZE,
-+			.maxauthsize = SHA512_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.geniv = true,
-+		}
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(md5),"
-+					    "rfc3686(ctr(aes)))",
-+				.cra_driver_name = "authenc-hmac-md5-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = MD5_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "seqiv(authenc("
-+					    "hmac(md5),rfc3686(ctr(aes))))",
-+				.cra_driver_name = "seqiv-authenc-hmac-md5-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = MD5_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+			.geniv = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha1),"
-+					    "rfc3686(ctr(aes)))",
-+				.cra_driver_name = "authenc-hmac-sha1-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "seqiv(authenc("
-+					    "hmac(sha1),rfc3686(ctr(aes))))",
-+				.cra_driver_name = "seqiv-authenc-hmac-sha1-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+			.geniv = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha224),"
-+					    "rfc3686(ctr(aes)))",
-+				.cra_driver_name = "authenc-hmac-sha224-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA224_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "seqiv(authenc("
-+					    "hmac(sha224),rfc3686(ctr(aes))))",
-+				.cra_driver_name = "seqiv-authenc-hmac-sha224-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA224_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+			.geniv = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha256),"
-+					    "rfc3686(ctr(aes)))",
-+				.cra_driver_name = "authenc-hmac-sha256-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA256_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "seqiv(authenc(hmac(sha256),"
-+					    "rfc3686(ctr(aes))))",
-+				.cra_driver_name = "seqiv-authenc-hmac-sha256-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA256_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+			.geniv = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha384),"
-+					    "rfc3686(ctr(aes)))",
-+				.cra_driver_name = "authenc-hmac-sha384-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA384_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "seqiv(authenc(hmac(sha384),"
-+					    "rfc3686(ctr(aes))))",
-+				.cra_driver_name = "seqiv-authenc-hmac-sha384-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA384_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+			.geniv = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "authenc(hmac(sha512),"
-+					    "rfc3686(ctr(aes)))",
-+				.cra_driver_name = "authenc-hmac-sha512-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA512_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "seqiv(authenc(hmac(sha512),"
-+					    "rfc3686(ctr(aes))))",
-+				.cra_driver_name = "seqiv-authenc-hmac-sha512-"
-+						   "rfc3686-ctr-aes-caam-qi2",
-+				.cra_blocksize = 1,
-+			},
-+			.setkey = aead_setkey,
-+			.setauthsize = aead_setauthsize,
-+			.encrypt = aead_encrypt,
-+			.decrypt = aead_decrypt,
-+			.ivsize = CTR_RFC3686_IV_SIZE,
-+			.maxauthsize = SHA512_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES |
-+					   OP_ALG_AAI_CTR_MOD128,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+			.rfc3686 = true,
-+			.geniv = true,
-+		},
-+	},
-+	{
-+		.aead = {
-+			.base = {
-+				.cra_name = "tls10(hmac(sha1),cbc(aes))",
-+				.cra_driver_name = "tls10-hmac-sha1-cbc-aes-caam-qi2",
-+				.cra_blocksize = AES_BLOCK_SIZE,
-+			},
-+			.setkey = tls_setkey,
-+			.setauthsize = tls_setauthsize,
-+			.encrypt = tls_encrypt,
-+			.decrypt = tls_decrypt,
-+			.ivsize = AES_BLOCK_SIZE,
-+			.maxauthsize = SHA1_DIGEST_SIZE,
-+		},
-+		.caam = {
-+			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
-+			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
-+					   OP_ALG_AAI_HMAC_PRECOMP,
-+		},
-+	},
-+};
-+
-+static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg)
-+{
-+	struct skcipher_alg *alg = &t_alg->skcipher;
-+
-+	alg->base.cra_module = THIS_MODULE;
-+	alg->base.cra_priority = CAAM_CRA_PRIORITY;
-+	alg->base.cra_ctxsize = sizeof(struct caam_ctx);
-+	alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
-+
-+	alg->init = caam_cra_init_skcipher;
-+	alg->exit = caam_cra_exit;
-+}
-+
-+static void caam_aead_alg_init(struct caam_aead_alg *t_alg)
-+{
-+	struct aead_alg *alg = &t_alg->aead;
-+
-+	alg->base.cra_module = THIS_MODULE;
-+	alg->base.cra_priority = CAAM_CRA_PRIORITY;
-+	alg->base.cra_ctxsize = sizeof(struct caam_ctx);
-+	alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
-+
-+	alg->init = caam_cra_init_aead;
-+	alg->exit = caam_cra_exit_aead;
-+}
-+
-+/* max hash key is max split key size */
-+#define CAAM_MAX_HASH_KEY_SIZE		(SHA512_DIGEST_SIZE * 2)
-+
-+#define CAAM_MAX_HASH_BLOCK_SIZE	SHA512_BLOCK_SIZE
-+#define CAAM_MAX_HASH_DIGEST_SIZE	SHA512_DIGEST_SIZE
-+
-+#define DESC_HASH_MAX_USED_BYTES	(DESC_AHASH_FINAL_LEN + \
-+					 CAAM_MAX_HASH_KEY_SIZE)
-+#define DESC_HASH_MAX_USED_LEN		(DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ)
-+
-+/* caam context sizes for hashes: running digest + 8 */
-+#define HASH_MSG_LEN			8
-+#define MAX_CTX_LEN			(HASH_MSG_LEN + SHA512_DIGEST_SIZE)
-+
-+enum hash_optype {
-+	UPDATE = 0,
-+	UPDATE_FIRST,
-+	FINALIZE,
-+	DIGEST,
-+	HASH_NUM_OP
-+};
-+
-+/**
-+ * caam_hash_ctx - ahash per-session context
-+ * @flc: Flow Contexts array
-+ * @flc_dma: I/O virtual addresses of the Flow Contexts
-+ * @key:  virtual address of the authentication key
-+ * @dev: dpseci device
-+ * @ctx_len: size of Context Register
-+ * @adata: hashing algorithm details
-+ */
-+struct caam_hash_ctx {
-+	struct caam_flc flc[HASH_NUM_OP];
-+	dma_addr_t flc_dma[HASH_NUM_OP];
-+	u8 key[CAAM_MAX_HASH_KEY_SIZE];
-+	struct device *dev;
-+	int ctx_len;
-+	struct alginfo adata;
-+};
-+
-+/* ahash state */
-+struct caam_hash_state {
-+	struct caam_request caam_req;
-+	dma_addr_t buf_dma;
-+	dma_addr_t ctx_dma;
-+	u8 buf_0[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
-+	int buflen_0;
-+	u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
-+	int buflen_1;
-+	u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
-+	int (*update)(struct ahash_request *req);
-+	int (*final)(struct ahash_request *req);
-+	int (*finup)(struct ahash_request *req);
-+	int current_buf;
-+};
-+
-+struct caam_export_state {
-+	u8 buf[CAAM_MAX_HASH_BLOCK_SIZE];
-+	u8 caam_ctx[MAX_CTX_LEN];
-+	int buflen;
-+	int (*update)(struct ahash_request *req);
-+	int (*final)(struct ahash_request *req);
-+	int (*finup)(struct ahash_request *req);
-+};
-+
-+static inline void switch_buf(struct caam_hash_state *state)
-+{
-+	state->current_buf ^= 1;
-+}
-+
-+static inline u8 *current_buf(struct caam_hash_state *state)
-+{
-+	return state->current_buf ? state->buf_1 : state->buf_0;
-+}
-+
-+static inline u8 *alt_buf(struct caam_hash_state *state)
-+{
-+	return state->current_buf ? state->buf_0 : state->buf_1;
-+}
-+
-+static inline int *current_buflen(struct caam_hash_state *state)
-+{
-+	return state->current_buf ? &state->buflen_1 : &state->buflen_0;
-+}
-+
-+static inline int *alt_buflen(struct caam_hash_state *state)
-+{
-+	return state->current_buf ? &state->buflen_0 : &state->buflen_1;
-+}
-+
-+/* Map current buffer in state (if length > 0) and put it in link table */
-+static inline int buf_map_to_qm_sg(struct device *dev,
-+				   struct dpaa2_sg_entry *qm_sg,
-+				   struct caam_hash_state *state)
-+{
-+	int buflen = *current_buflen(state);
-+
-+	if (!buflen)
-+		return 0;
-+
-+	state->buf_dma = dma_map_single(dev, current_buf(state), buflen,
-+					DMA_TO_DEVICE);
-+	if (dma_mapping_error(dev, state->buf_dma)) {
-+		dev_err(dev, "unable to map buf\n");
-+		state->buf_dma = 0;
-+		return -ENOMEM;
-+	}
-+
-+	dma_to_qm_sg_one(qm_sg, state->buf_dma, buflen, 0);
-+
-+	return 0;
-+}
-+
-+/* Map state->caam_ctx, and add it to link table */
-+static inline int ctx_map_to_qm_sg(struct device *dev,
-+				   struct caam_hash_state *state, int ctx_len,
-+				   struct dpaa2_sg_entry *qm_sg, u32 flag)
-+{
-+	state->ctx_dma = dma_map_single(dev, state->caam_ctx, ctx_len, flag);
-+	if (dma_mapping_error(dev, state->ctx_dma)) {
-+		dev_err(dev, "unable to map ctx\n");
-+		state->ctx_dma = 0;
-+		return -ENOMEM;
-+	}
-+
-+	dma_to_qm_sg_one(qm_sg, state->ctx_dma, ctx_len, 0);
-+
-+	return 0;
-+}
-+
-+static int ahash_set_sh_desc(struct crypto_ahash *ahash)
-+{
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+	struct dpaa2_caam_priv *priv = dev_get_drvdata(ctx->dev);
-+	struct caam_flc *flc;
-+	u32 *desc;
-+
-+	ctx->adata.key_virt = ctx->key;
-+	ctx->adata.key_inline = true;
-+
-+	/* ahash_update shared descriptor */
-+	flc = &ctx->flc[UPDATE];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_UPDATE, ctx->ctx_len,
-+			  ctx->ctx_len, true, priv->sec_attr.era);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE],
-+				   desc_bytes(desc), DMA_BIDIRECTIONAL);
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR,
-+		       "ahash update shdesc@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
-+#endif
-+
-+	/* ahash_update_first shared descriptor */
-+	flc = &ctx->flc[UPDATE_FIRST];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len,
-+			  ctx->ctx_len, false, priv->sec_attr.era);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE_FIRST],
-+				   desc_bytes(desc), DMA_BIDIRECTIONAL);
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR,
-+		       "ahash update first shdesc@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
-+#endif
-+
-+	/* ahash_final shared descriptor */
-+	flc = &ctx->flc[FINALIZE];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, digestsize,
-+			  ctx->ctx_len, true, priv->sec_attr.era);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[FINALIZE],
-+				   desc_bytes(desc), DMA_BIDIRECTIONAL);
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR,
-+		       "ahash final shdesc@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
-+#endif
-+
-+	/* ahash_digest shared descriptor */
-+	flc = &ctx->flc[DIGEST];
-+	desc = flc->sh_desc;
-+	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, digestsize,
-+			  ctx->ctx_len, false, priv->sec_attr.era);
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[DIGEST],
-+				   desc_bytes(desc), DMA_BIDIRECTIONAL);
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR,
-+		       "ahash digest shdesc@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
-+#endif
-+
-+	return 0;
-+}
-+
-+/* Digest hash size if it is too large */
-+static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
-+			   u32 *keylen, u8 *key_out, u32 digestsize)
-+{
-+	struct caam_request *req_ctx;
-+	u32 *desc;
-+	struct split_key_sh_result result;
-+	dma_addr_t src_dma, dst_dma;
-+	struct caam_flc *flc;
-+	dma_addr_t flc_dma;
-+	int ret = -ENOMEM;
-+	struct dpaa2_fl_entry *in_fle, *out_fle;
-+
-+	req_ctx = kzalloc(sizeof(*req_ctx), GFP_KERNEL | GFP_DMA);
-+	if (!req_ctx)
-+		return -ENOMEM;
-+
-+	in_fle = &req_ctx->fd_flt[1];
-+	out_fle = &req_ctx->fd_flt[0];
-+
-+	flc = kzalloc(sizeof(*flc), GFP_KERNEL | GFP_DMA);
-+	if (!flc)
-+		goto err_flc;
-+
-+	src_dma = dma_map_single(ctx->dev, (void *)key_in, *keylen,
-+				 DMA_TO_DEVICE);
-+	if (dma_mapping_error(ctx->dev, src_dma)) {
-+		dev_err(ctx->dev, "unable to map key input memory\n");
-+		goto err_src_dma;
-+	}
-+	dst_dma = dma_map_single(ctx->dev, (void *)key_out, digestsize,
-+				 DMA_FROM_DEVICE);
-+	if (dma_mapping_error(ctx->dev, dst_dma)) {
-+		dev_err(ctx->dev, "unable to map key output memory\n");
-+		goto err_dst_dma;
-+	}
-+
-+	desc = flc->sh_desc;
-+
-+	init_sh_desc(desc, 0);
-+
-+	/* descriptor to perform unkeyed hash on key_in */
-+	append_operation(desc, ctx->adata.algtype | OP_ALG_ENCRYPT |
-+			 OP_ALG_AS_INITFINAL);
-+	append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 |
-+			     FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_MSG);
-+	append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
-+			 LDST_SRCDST_BYTE_CONTEXT);
-+
-+	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
-+	flc_dma = dma_map_single(ctx->dev, flc, sizeof(flc->flc) +
-+				 desc_bytes(desc), DMA_TO_DEVICE);
-+	if (dma_mapping_error(ctx->dev, flc_dma)) {
-+		dev_err(ctx->dev, "unable to map shared descriptor\n");
-+		goto err_flc_dma;
-+	}
-+
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
-+	dpaa2_fl_set_addr(in_fle, src_dma);
-+	dpaa2_fl_set_len(in_fle, *keylen);
-+	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+	dpaa2_fl_set_addr(out_fle, dst_dma);
-+	dpaa2_fl_set_len(out_fle, digestsize);
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "key_in@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, key_in, *keylen, 1);
-+	print_hex_dump(KERN_ERR, "shdesc@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
-+#endif
-+
-+	result.err = 0;
-+	init_completion(&result.completion);
-+	result.dev = ctx->dev;
-+
-+	req_ctx->flc = flc;
-+	req_ctx->flc_dma = flc_dma;
-+	req_ctx->cbk = split_key_sh_done;
-+	req_ctx->ctx = &result;
-+
-+	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+	if (ret == -EINPROGRESS) {
-+		/* in progress */
-+		wait_for_completion(&result.completion);
-+		ret = result.err;
-+#ifdef DEBUG
-+		print_hex_dump(KERN_ERR,
-+			       "digested key@" __stringify(__LINE__)": ",
-+			       DUMP_PREFIX_ADDRESS, 16, 4, key_in, digestsize,
-+			       1);
-+#endif
-+	}
-+
-+	dma_unmap_single(ctx->dev, flc_dma, sizeof(flc->flc) + desc_bytes(desc),
-+			 DMA_TO_DEVICE);
-+err_flc_dma:
-+	dma_unmap_single(ctx->dev, dst_dma, digestsize, DMA_FROM_DEVICE);
-+err_dst_dma:
-+	dma_unmap_single(ctx->dev, src_dma, *keylen, DMA_TO_DEVICE);
-+err_src_dma:
-+	kfree(flc);
-+err_flc:
-+	kfree(req_ctx);
-+
-+	*keylen = digestsize;
-+
-+	return ret;
-+}
-+
-+static int ahash_setkey(struct crypto_ahash *ahash, const u8 *key,
-+			unsigned int keylen)
-+{
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	unsigned int blocksize = crypto_tfm_alg_blocksize(&ahash->base);
-+	unsigned int digestsize = crypto_ahash_digestsize(ahash);
-+	int ret;
-+	u8 *hashed_key = NULL;
-+
-+#ifdef DEBUG
-+	dev_err(ctx->dev, "keylen %d blocksize %d\n", keylen, blocksize);
-+#endif
-+
-+	if (keylen > blocksize) {
-+		hashed_key = kmalloc_array(digestsize, sizeof(*hashed_key),
-+					   GFP_KERNEL | GFP_DMA);
-+		if (!hashed_key)
-+			return -ENOMEM;
-+		ret = hash_digest_key(ctx, key, &keylen, hashed_key,
-+				      digestsize);
-+		if (ret)
-+			goto bad_free_key;
-+		key = hashed_key;
-+	}
-+
-+	ctx->adata.keylen = keylen;
-+	ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
-+					      OP_ALG_ALGSEL_MASK);
-+	if (ctx->adata.keylen_pad > CAAM_MAX_HASH_KEY_SIZE)
-+		goto bad_free_key;
-+
-+	memcpy(ctx->key, key, keylen);
-+
-+	kfree(hashed_key);
-+	return ahash_set_sh_desc(ahash);
-+bad_free_key:
-+	kfree(hashed_key);
-+	crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
-+	return -EINVAL;
-+}
-+
-+static inline void ahash_unmap(struct device *dev, struct ahash_edesc *edesc,
-+			       struct ahash_request *req, int dst_len)
-+{
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+
-+	if (edesc->src_nents)
-+		dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE);
-+	if (edesc->dst_dma)
-+		dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE);
-+
-+	if (edesc->qm_sg_bytes)
-+		dma_unmap_single(dev, edesc->qm_sg_dma, edesc->qm_sg_bytes,
-+				 DMA_TO_DEVICE);
-+
-+	if (state->buf_dma) {
-+		dma_unmap_single(dev, state->buf_dma, *current_buflen(state),
-+				 DMA_TO_DEVICE);
-+		state->buf_dma = 0;
-+	}
-+}
-+
-+static inline void ahash_unmap_ctx(struct device *dev,
-+				   struct ahash_edesc *edesc,
-+				   struct ahash_request *req, int dst_len,
-+				   u32 flag)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+
-+	if (state->ctx_dma) {
-+		dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag);
-+		state->ctx_dma = 0;
-+	}
-+	ahash_unmap(dev, edesc, req, dst_len);
-+}
-+
-+static void ahash_done(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct ahash_request *req = ahash_request_cast(areq);
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct ahash_edesc *edesc = state->caam_req.edesc;
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+	int ecode = 0;
-+
-+#ifdef DEBUG
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		ecode = -EIO;
-+	}
-+
-+	ahash_unmap(ctx->dev, edesc, req, digestsize);
-+	qi_cache_free(edesc);
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
-+		       ctx->ctx_len, 1);
-+	if (req->result)
-+		print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ",
-+			       DUMP_PREFIX_ADDRESS, 16, 4, req->result,
-+			       digestsize, 1);
-+#endif
-+
-+	req->base.complete(&req->base, ecode);
-+}
-+
-+static void ahash_done_bi(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct ahash_request *req = ahash_request_cast(areq);
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct ahash_edesc *edesc = state->caam_req.edesc;
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	int ecode = 0;
-+#ifdef DEBUG
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		ecode = -EIO;
-+	}
-+
-+	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
-+	switch_buf(state);
-+	qi_cache_free(edesc);
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
-+		       ctx->ctx_len, 1);
-+	if (req->result)
-+		print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ",
-+			       DUMP_PREFIX_ADDRESS, 16, 4, req->result,
-+			       digestsize, 1);
-+#endif
-+
-+	req->base.complete(&req->base, ecode);
-+}
-+
-+static void ahash_done_ctx_src(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct ahash_request *req = ahash_request_cast(areq);
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct ahash_edesc *edesc = state->caam_req.edesc;
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+	int ecode = 0;
-+
-+#ifdef DEBUG
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		ecode = -EIO;
-+	}
-+
-+	ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_TO_DEVICE);
-+	qi_cache_free(edesc);
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
-+		       ctx->ctx_len, 1);
-+	if (req->result)
-+		print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ",
-+			       DUMP_PREFIX_ADDRESS, 16, 4, req->result,
-+			       digestsize, 1);
-+#endif
-+
-+	req->base.complete(&req->base, ecode);
-+}
-+
-+static void ahash_done_ctx_dst(void *cbk_ctx, u32 status)
-+{
-+	struct crypto_async_request *areq = cbk_ctx;
-+	struct ahash_request *req = ahash_request_cast(areq);
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct ahash_edesc *edesc = state->caam_req.edesc;
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	int ecode = 0;
-+#ifdef DEBUG
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+
-+	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
-+#endif
-+
-+	if (unlikely(status)) {
-+		caam_qi2_strstatus(ctx->dev, status);
-+		ecode = -EIO;
-+	}
-+
-+	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE);
-+	switch_buf(state);
-+	qi_cache_free(edesc);
-+
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
-+		       ctx->ctx_len, 1);
-+	if (req->result)
-+		print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ",
-+			       DUMP_PREFIX_ADDRESS, 16, 4, req->result,
-+			       digestsize, 1);
-+#endif
-+
-+	req->base.complete(&req->base, ecode);
-+}
-+
-+static int ahash_update_ctx(struct ahash_request *req)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_request *req_ctx = &state->caam_req;
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	u8 *buf = current_buf(state);
-+	int *buflen = current_buflen(state);
-+	u8 *next_buf = alt_buf(state);
-+	int *next_buflen = alt_buflen(state), last_buflen;
-+	int in_len = *buflen + req->nbytes, to_hash;
-+	int src_nents, mapped_nents, qm_sg_bytes, qm_sg_src_index;
-+	struct ahash_edesc *edesc;
-+	int ret = 0;
-+
-+	last_buflen = *next_buflen;
-+	*next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
-+	to_hash = in_len - *next_buflen;
-+
-+	if (to_hash) {
-+		struct dpaa2_sg_entry *sg_table;
-+
-+		src_nents = sg_nents_for_len(req->src,
-+					     req->nbytes - (*next_buflen));
-+		if (src_nents < 0) {
-+			dev_err(ctx->dev, "Invalid number of src SG.\n");
-+			return src_nents;
-+		}
-+
-+		if (src_nents) {
-+			mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
-+						  DMA_TO_DEVICE);
-+			if (!mapped_nents) {
-+				dev_err(ctx->dev, "unable to DMA map source\n");
-+				return -ENOMEM;
-+			}
-+		} else {
-+			mapped_nents = 0;
-+		}
-+
-+		/* allocate space for base edesc and link tables */
-+		edesc = qi_cache_zalloc(GFP_DMA | flags);
-+		if (!edesc) {
-+			dma_unmap_sg(ctx->dev, req->src, src_nents,
-+				     DMA_TO_DEVICE);
-+			return -ENOMEM;
-+		}
-+
-+		edesc->src_nents = src_nents;
-+		qm_sg_src_index = 1 + (*buflen ? 1 : 0);
-+		qm_sg_bytes = (qm_sg_src_index + mapped_nents) *
-+			      sizeof(*sg_table);
-+		sg_table = &edesc->sgt[0];
-+
-+		ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
-+				       DMA_BIDIRECTIONAL);
-+		if (ret)
-+			goto unmap_ctx;
-+
-+		ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
-+		if (ret)
-+			goto unmap_ctx;
-+
-+		if (mapped_nents) {
-+			sg_to_qm_sg_last(req->src, mapped_nents,
-+					 sg_table + qm_sg_src_index, 0);
-+			if (*next_buflen)
-+				scatterwalk_map_and_copy(next_buf, req->src,
-+							 to_hash - *buflen,
-+							 *next_buflen, 0);
-+		} else {
-+			dpaa2_sg_set_final(sg_table + qm_sg_src_index - 1,
-+					   true);
-+		}
-+
-+		edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
-+						  qm_sg_bytes, DMA_TO_DEVICE);
-+		if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
-+			dev_err(ctx->dev, "unable to map S/G table\n");
-+			ret = -ENOMEM;
-+			goto unmap_ctx;
-+		}
-+		edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+		memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+		dpaa2_fl_set_final(in_fle, true);
-+		dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+		dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
-+		dpaa2_fl_set_len(in_fle, ctx->ctx_len + to_hash);
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+		dpaa2_fl_set_addr(out_fle, state->ctx_dma);
-+		dpaa2_fl_set_len(out_fle, ctx->ctx_len);
-+
-+		req_ctx->flc = &ctx->flc[UPDATE];
-+		req_ctx->flc_dma = ctx->flc_dma[UPDATE];
-+		req_ctx->cbk = ahash_done_bi;
-+		req_ctx->ctx = &req->base;
-+		req_ctx->edesc = edesc;
-+
-+		ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+		if (ret != -EINPROGRESS &&
-+		    !(ret == -EBUSY &&
-+		      req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
-+			goto unmap_ctx;
-+	} else if (*next_buflen) {
-+		scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
-+					 req->nbytes, 0);
-+		*buflen = *next_buflen;
-+		*next_buflen = last_buflen;
-+	}
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "buf@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
-+	print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
-+		       *next_buflen, 1);
-+#endif
-+
-+	return ret;
-+unmap_ctx:
-+	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
-+	qi_cache_free(edesc);
-+	return ret;
-+}
-+
-+static int ahash_final_ctx(struct ahash_request *req)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_request *req_ctx = &state->caam_req;
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	int buflen = *current_buflen(state);
-+	int qm_sg_bytes, qm_sg_src_index;
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+	struct ahash_edesc *edesc;
-+	struct dpaa2_sg_entry *sg_table;
-+	int ret;
-+
-+	/* allocate space for base edesc and link tables */
-+	edesc = qi_cache_zalloc(GFP_DMA | flags);
-+	if (!edesc)
-+		return -ENOMEM;
-+
-+	qm_sg_src_index = 1 + (buflen ? 1 : 0);
-+	qm_sg_bytes = qm_sg_src_index * sizeof(*sg_table);
-+	sg_table = &edesc->sgt[0];
-+
-+	ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
-+			       DMA_TO_DEVICE);
-+	if (ret)
-+		goto unmap_ctx;
-+
-+	ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
-+	if (ret)
-+		goto unmap_ctx;
-+
-+	dpaa2_sg_set_final(sg_table + qm_sg_src_index - 1, true);
-+
-+	edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
-+					  DMA_TO_DEVICE);
-+	if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
-+		dev_err(ctx->dev, "unable to map S/G table\n");
-+		ret = -ENOMEM;
-+		goto unmap_ctx;
-+	}
-+	edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
-+					DMA_FROM_DEVICE);
-+	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
-+		dev_err(ctx->dev, "unable to map dst\n");
-+		edesc->dst_dma = 0;
-+		ret = -ENOMEM;
-+		goto unmap_ctx;
-+	}
-+
-+	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+	dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
-+	dpaa2_fl_set_len(in_fle, ctx->ctx_len + buflen);
-+	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
-+	dpaa2_fl_set_len(out_fle, digestsize);
-+
-+	req_ctx->flc = &ctx->flc[FINALIZE];
-+	req_ctx->flc_dma = ctx->flc_dma[FINALIZE];
-+	req_ctx->cbk = ahash_done_ctx_src;
-+	req_ctx->ctx = &req->base;
-+	req_ctx->edesc = edesc;
-+
-+	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+	if (ret == -EINPROGRESS ||
-+	    (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
-+		return ret;
-+
-+unmap_ctx:
-+	ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_FROM_DEVICE);
-+	qi_cache_free(edesc);
-+	return ret;
-+}
-+
-+static int ahash_finup_ctx(struct ahash_request *req)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_request *req_ctx = &state->caam_req;
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	int buflen = *current_buflen(state);
-+	int qm_sg_bytes, qm_sg_src_index;
-+	int src_nents, mapped_nents;
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+	struct ahash_edesc *edesc;
-+	struct dpaa2_sg_entry *sg_table;
-+	int ret;
-+
-+	src_nents = sg_nents_for_len(req->src, req->nbytes);
-+	if (src_nents < 0) {
-+		dev_err(ctx->dev, "Invalid number of src SG.\n");
-+		return src_nents;
-+	}
-+
-+	if (src_nents) {
-+		mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
-+					  DMA_TO_DEVICE);
-+		if (!mapped_nents) {
-+			dev_err(ctx->dev, "unable to DMA map source\n");
-+			return -ENOMEM;
-+		}
-+	} else {
-+		mapped_nents = 0;
-+	}
-+
-+	/* allocate space for base edesc and link tables */
-+	edesc = qi_cache_zalloc(GFP_DMA | flags);
-+	if (!edesc) {
-+		dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
-+		return -ENOMEM;
-+	}
-+
-+	edesc->src_nents = src_nents;
-+	qm_sg_src_index = 1 + (buflen ? 1 : 0);
-+	qm_sg_bytes = (qm_sg_src_index + mapped_nents) * sizeof(*sg_table);
-+	sg_table = &edesc->sgt[0];
-+
-+	ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
-+			       DMA_TO_DEVICE);
-+	if (ret)
-+		goto unmap_ctx;
-+
-+	ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
-+	if (ret)
-+		goto unmap_ctx;
-+
-+	sg_to_qm_sg_last(req->src, mapped_nents, sg_table + qm_sg_src_index, 0);
-+
-+	edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
-+					  DMA_TO_DEVICE);
-+	if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
-+		dev_err(ctx->dev, "unable to map S/G table\n");
-+		ret = -ENOMEM;
-+		goto unmap_ctx;
-+	}
-+	edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
-+					DMA_FROM_DEVICE);
-+	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
-+		dev_err(ctx->dev, "unable to map dst\n");
-+		edesc->dst_dma = 0;
-+		ret = -ENOMEM;
-+		goto unmap_ctx;
-+	}
-+
-+	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+	dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
-+	dpaa2_fl_set_len(in_fle, ctx->ctx_len + buflen + req->nbytes);
-+	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
-+	dpaa2_fl_set_len(out_fle, digestsize);
-+
-+	req_ctx->flc = &ctx->flc[FINALIZE];
-+	req_ctx->flc_dma = ctx->flc_dma[FINALIZE];
-+	req_ctx->cbk = ahash_done_ctx_src;
-+	req_ctx->ctx = &req->base;
-+	req_ctx->edesc = edesc;
-+
-+	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+	if (ret == -EINPROGRESS ||
-+	    (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
-+		return ret;
-+
-+unmap_ctx:
-+	ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_FROM_DEVICE);
-+	qi_cache_free(edesc);
-+	return ret;
-+}
-+
-+static int ahash_digest(struct ahash_request *req)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_request *req_ctx = &state->caam_req;
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+	int src_nents, mapped_nents;
-+	struct ahash_edesc *edesc;
-+	int ret = -ENOMEM;
-+
-+	state->buf_dma = 0;
-+
-+	src_nents = sg_nents_for_len(req->src, req->nbytes);
-+	if (src_nents < 0) {
-+		dev_err(ctx->dev, "Invalid number of src SG.\n");
-+		return src_nents;
-+	}
-+
-+	if (src_nents) {
-+		mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
-+					  DMA_TO_DEVICE);
-+		if (!mapped_nents) {
-+			dev_err(ctx->dev, "unable to map source for DMA\n");
-+			return ret;
-+		}
-+	} else {
-+		mapped_nents = 0;
-+	}
-+
-+	/* allocate space for base edesc and link tables */
-+	edesc = qi_cache_zalloc(GFP_DMA | flags);
-+	if (!edesc) {
-+		dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
-+		return ret;
-+	}
-+
-+	edesc->src_nents = src_nents;
-+	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+
-+	if (mapped_nents > 1) {
-+		int qm_sg_bytes;
-+		struct dpaa2_sg_entry *sg_table = &edesc->sgt[0];
-+
-+		qm_sg_bytes = mapped_nents * sizeof(*sg_table);
-+		sg_to_qm_sg_last(req->src, mapped_nents, sg_table, 0);
-+		edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
-+						  qm_sg_bytes, DMA_TO_DEVICE);
-+		if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
-+			dev_err(ctx->dev, "unable to map S/G table\n");
-+			goto unmap;
-+		}
-+		edesc->qm_sg_bytes = qm_sg_bytes;
-+		dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+		dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
-+	} else {
-+		dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
-+		dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src));
-+	}
-+
-+	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
-+					DMA_FROM_DEVICE);
-+	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
-+		dev_err(ctx->dev, "unable to map dst\n");
-+		edesc->dst_dma = 0;
-+		goto unmap;
-+	}
-+
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_len(in_fle, req->nbytes);
-+	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
-+	dpaa2_fl_set_len(out_fle, digestsize);
-+
-+	req_ctx->flc = &ctx->flc[DIGEST];
-+	req_ctx->flc_dma = ctx->flc_dma[DIGEST];
-+	req_ctx->cbk = ahash_done;
-+	req_ctx->ctx = &req->base;
-+	req_ctx->edesc = edesc;
-+	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+	if (ret == -EINPROGRESS ||
-+	    (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
-+		return ret;
-+
-+unmap:
-+	ahash_unmap(ctx->dev, edesc, req, digestsize);
-+	qi_cache_free(edesc);
-+	return ret;
-+}
-+
-+static int ahash_final_no_ctx(struct ahash_request *req)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_request *req_ctx = &state->caam_req;
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	u8 *buf = current_buf(state);
-+	int buflen = *current_buflen(state);
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+	struct ahash_edesc *edesc;
-+	int ret = -ENOMEM;
-+
-+	/* allocate space for base edesc and link tables */
-+	edesc = qi_cache_zalloc(GFP_DMA | flags);
-+	if (!edesc)
-+		return ret;
-+
-+	state->buf_dma = dma_map_single(ctx->dev, buf, buflen, DMA_TO_DEVICE);
-+	if (dma_mapping_error(ctx->dev, state->buf_dma)) {
-+		dev_err(ctx->dev, "unable to map src\n");
-+		goto unmap;
-+	}
-+
-+	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
-+					DMA_FROM_DEVICE);
-+	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
-+		dev_err(ctx->dev, "unable to map dst\n");
-+		edesc->dst_dma = 0;
-+		goto unmap;
-+	}
-+
-+	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
-+	dpaa2_fl_set_addr(in_fle, state->buf_dma);
-+	dpaa2_fl_set_len(in_fle, buflen);
-+	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
-+	dpaa2_fl_set_len(out_fle, digestsize);
-+
-+	req_ctx->flc = &ctx->flc[DIGEST];
-+	req_ctx->flc_dma = ctx->flc_dma[DIGEST];
-+	req_ctx->cbk = ahash_done;
-+	req_ctx->ctx = &req->base;
-+	req_ctx->edesc = edesc;
-+
-+	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+	if (ret == -EINPROGRESS ||
-+	    (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
-+		return ret;
-+
-+unmap:
-+	ahash_unmap(ctx->dev, edesc, req, digestsize);
-+	qi_cache_free(edesc);
-+	return ret;
-+}
-+
-+static int ahash_update_no_ctx(struct ahash_request *req)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_request *req_ctx = &state->caam_req;
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	u8 *buf = current_buf(state);
-+	int *buflen = current_buflen(state);
-+	u8 *next_buf = alt_buf(state);
-+	int *next_buflen = alt_buflen(state);
-+	int in_len = *buflen + req->nbytes, to_hash;
-+	int qm_sg_bytes, src_nents, mapped_nents;
-+	struct ahash_edesc *edesc;
-+	int ret = 0;
-+
-+	*next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
-+	to_hash = in_len - *next_buflen;
-+
-+	if (to_hash) {
-+		struct dpaa2_sg_entry *sg_table;
-+
-+		src_nents = sg_nents_for_len(req->src,
-+					     req->nbytes - *next_buflen);
-+		if (src_nents < 0) {
-+			dev_err(ctx->dev, "Invalid number of src SG.\n");
-+			return src_nents;
-+		}
-+
-+		if (src_nents) {
-+			mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
-+						  DMA_TO_DEVICE);
-+			if (!mapped_nents) {
-+				dev_err(ctx->dev, "unable to DMA map source\n");
-+				return -ENOMEM;
-+			}
-+		} else {
-+			mapped_nents = 0;
-+		}
-+
-+		/* allocate space for base edesc and link tables */
-+		edesc = qi_cache_zalloc(GFP_DMA | flags);
-+		if (!edesc) {
-+			dma_unmap_sg(ctx->dev, req->src, src_nents,
-+				     DMA_TO_DEVICE);
-+			return -ENOMEM;
-+		}
-+
-+		edesc->src_nents = src_nents;
-+		qm_sg_bytes = (1 + mapped_nents) * sizeof(*sg_table);
-+		sg_table = &edesc->sgt[0];
-+
-+		ret = buf_map_to_qm_sg(ctx->dev, sg_table, state);
-+		if (ret)
-+			goto unmap_ctx;
-+
-+		sg_to_qm_sg_last(req->src, mapped_nents, sg_table + 1, 0);
-+
-+		if (*next_buflen)
-+			scatterwalk_map_and_copy(next_buf, req->src,
-+						 to_hash - *buflen,
-+						 *next_buflen, 0);
-+
-+		edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
-+						  qm_sg_bytes, DMA_TO_DEVICE);
-+		if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
-+			dev_err(ctx->dev, "unable to map S/G table\n");
-+			ret = -ENOMEM;
-+			goto unmap_ctx;
-+		}
-+		edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+		state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx,
-+						ctx->ctx_len, DMA_FROM_DEVICE);
-+		if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
-+			dev_err(ctx->dev, "unable to map ctx\n");
-+			state->ctx_dma = 0;
-+			ret = -ENOMEM;
-+			goto unmap_ctx;
-+		}
-+
-+		memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+		dpaa2_fl_set_final(in_fle, true);
-+		dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+		dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
-+		dpaa2_fl_set_len(in_fle, to_hash);
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+		dpaa2_fl_set_addr(out_fle, state->ctx_dma);
-+		dpaa2_fl_set_len(out_fle, ctx->ctx_len);
-+
-+		req_ctx->flc = &ctx->flc[UPDATE_FIRST];
-+		req_ctx->flc_dma = ctx->flc_dma[UPDATE_FIRST];
-+		req_ctx->cbk = ahash_done_ctx_dst;
-+		req_ctx->ctx = &req->base;
-+		req_ctx->edesc = edesc;
-+
-+		ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+		if (ret != -EINPROGRESS &&
-+		    !(ret == -EBUSY &&
-+		      req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
-+			goto unmap_ctx;
-+
-+		state->update = ahash_update_ctx;
-+		state->finup = ahash_finup_ctx;
-+		state->final = ahash_final_ctx;
-+	} else if (*next_buflen) {
-+		scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
-+					 req->nbytes, 0);
-+		*buflen = *next_buflen;
-+		*next_buflen = 0;
-+	}
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "buf@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
-+	print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
-+		       *next_buflen, 1);
-+#endif
-+
-+	return ret;
-+unmap_ctx:
-+	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE);
-+	qi_cache_free(edesc);
-+	return ret;
-+}
-+
-+static int ahash_finup_no_ctx(struct ahash_request *req)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_request *req_ctx = &state->caam_req;
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	int buflen = *current_buflen(state);
-+	int qm_sg_bytes, src_nents, mapped_nents;
-+	int digestsize = crypto_ahash_digestsize(ahash);
-+	struct ahash_edesc *edesc;
-+	struct dpaa2_sg_entry *sg_table;
-+	int ret;
-+
-+	src_nents = sg_nents_for_len(req->src, req->nbytes);
-+	if (src_nents < 0) {
-+		dev_err(ctx->dev, "Invalid number of src SG.\n");
-+		return src_nents;
-+	}
-+
-+	if (src_nents) {
-+		mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
-+					  DMA_TO_DEVICE);
-+		if (!mapped_nents) {
-+			dev_err(ctx->dev, "unable to DMA map source\n");
-+			return -ENOMEM;
-+		}
-+	} else {
-+		mapped_nents = 0;
-+	}
-+
-+	/* allocate space for base edesc and link tables */
-+	edesc = qi_cache_zalloc(GFP_DMA | flags);
-+	if (!edesc) {
-+		dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
-+		return -ENOMEM;
-+	}
-+
-+	edesc->src_nents = src_nents;
-+	qm_sg_bytes = (2 + mapped_nents) * sizeof(*sg_table);
-+	sg_table = &edesc->sgt[0];
-+
-+	ret = buf_map_to_qm_sg(ctx->dev, sg_table, state);
-+	if (ret)
-+		goto unmap;
-+
-+	sg_to_qm_sg_last(req->src, mapped_nents, sg_table + 1, 0);
-+
-+	edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
-+					  DMA_TO_DEVICE);
-+	if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
-+		dev_err(ctx->dev, "unable to map S/G table\n");
-+		ret = -ENOMEM;
-+		goto unmap;
-+	}
-+	edesc->qm_sg_bytes = qm_sg_bytes;
-+
-+	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
-+					DMA_FROM_DEVICE);
-+	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
-+		dev_err(ctx->dev, "unable to map dst\n");
-+		edesc->dst_dma = 0;
-+		ret = -ENOMEM;
-+		goto unmap;
-+	}
-+
-+	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+	dpaa2_fl_set_final(in_fle, true);
-+	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+	dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
-+	dpaa2_fl_set_len(in_fle, buflen + req->nbytes);
-+	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
-+	dpaa2_fl_set_len(out_fle, digestsize);
-+
-+	req_ctx->flc = &ctx->flc[DIGEST];
-+	req_ctx->flc_dma = ctx->flc_dma[DIGEST];
-+	req_ctx->cbk = ahash_done;
-+	req_ctx->ctx = &req->base;
-+	req_ctx->edesc = edesc;
-+	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+	if (ret != -EINPROGRESS &&
-+	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
-+		goto unmap;
-+
-+	return ret;
-+unmap:
-+	ahash_unmap(ctx->dev, edesc, req, digestsize);
-+	qi_cache_free(edesc);
-+	return -ENOMEM;
-+}
-+
-+static int ahash_update_first(struct ahash_request *req)
-+{
-+	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
-+	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_request *req_ctx = &state->caam_req;
-+	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
-+	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
-+	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
-+		      GFP_KERNEL : GFP_ATOMIC;
-+	u8 *next_buf = alt_buf(state);
-+	int *next_buflen = alt_buflen(state);
-+	int to_hash;
-+	int src_nents, mapped_nents;
-+	struct ahash_edesc *edesc;
-+	int ret = 0;
-+
-+	*next_buflen = req->nbytes & (crypto_tfm_alg_blocksize(&ahash->base) -
-+				      1);
-+	to_hash = req->nbytes - *next_buflen;
-+
-+	if (to_hash) {
-+		struct dpaa2_sg_entry *sg_table;
-+
-+		src_nents = sg_nents_for_len(req->src,
-+					     req->nbytes - (*next_buflen));
-+		if (src_nents < 0) {
-+			dev_err(ctx->dev, "Invalid number of src SG.\n");
-+			return src_nents;
-+		}
-+
-+		if (src_nents) {
-+			mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
-+						  DMA_TO_DEVICE);
-+			if (!mapped_nents) {
-+				dev_err(ctx->dev, "unable to map source for DMA\n");
-+				return -ENOMEM;
-+			}
-+		} else {
-+			mapped_nents = 0;
-+		}
-+
-+		/* allocate space for base edesc and link tables */
-+		edesc = qi_cache_zalloc(GFP_DMA | flags);
-+		if (!edesc) {
-+			dma_unmap_sg(ctx->dev, req->src, src_nents,
-+				     DMA_TO_DEVICE);
-+			return -ENOMEM;
-+		}
-+
-+		edesc->src_nents = src_nents;
-+		sg_table = &edesc->sgt[0];
-+
-+		memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
-+		dpaa2_fl_set_final(in_fle, true);
-+		dpaa2_fl_set_len(in_fle, to_hash);
-+
-+		if (mapped_nents > 1) {
-+			int qm_sg_bytes;
-+
-+			sg_to_qm_sg_last(req->src, mapped_nents, sg_table, 0);
-+			qm_sg_bytes = mapped_nents * sizeof(*sg_table);
-+			edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
-+							  qm_sg_bytes,
-+							  DMA_TO_DEVICE);
-+			if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
-+				dev_err(ctx->dev, "unable to map S/G table\n");
-+				ret = -ENOMEM;
-+				goto unmap_ctx;
-+			}
-+			edesc->qm_sg_bytes = qm_sg_bytes;
-+			dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
-+			dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
-+		} else {
-+			dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
-+			dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src));
-+		}
-+
-+		if (*next_buflen)
-+			scatterwalk_map_and_copy(next_buf, req->src, to_hash,
-+						 *next_buflen, 0);
-+
-+		state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx,
-+						ctx->ctx_len, DMA_FROM_DEVICE);
-+		if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
-+			dev_err(ctx->dev, "unable to map ctx\n");
-+			state->ctx_dma = 0;
-+			ret = -ENOMEM;
-+			goto unmap_ctx;
-+		}
-+
-+		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
-+		dpaa2_fl_set_addr(out_fle, state->ctx_dma);
-+		dpaa2_fl_set_len(out_fle, ctx->ctx_len);
-+
-+		req_ctx->flc = &ctx->flc[UPDATE_FIRST];
-+		req_ctx->flc_dma = ctx->flc_dma[UPDATE_FIRST];
-+		req_ctx->cbk = ahash_done_ctx_dst;
-+		req_ctx->ctx = &req->base;
-+		req_ctx->edesc = edesc;
-+
-+		ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
-+		if (ret != -EINPROGRESS &&
-+		    !(ret == -EBUSY && req->base.flags &
-+		      CRYPTO_TFM_REQ_MAY_BACKLOG))
-+			goto unmap_ctx;
-+
-+		state->update = ahash_update_ctx;
-+		state->finup = ahash_finup_ctx;
-+		state->final = ahash_final_ctx;
-+	} else if (*next_buflen) {
-+		state->update = ahash_update_no_ctx;
-+		state->finup = ahash_finup_no_ctx;
-+		state->final = ahash_final_no_ctx;
-+		scatterwalk_map_and_copy(next_buf, req->src, 0,
-+					 req->nbytes, 0);
-+		switch_buf(state);
-+	}
-+#ifdef DEBUG
-+	print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ",
-+		       DUMP_PREFIX_ADDRESS, 16, 4, next_buf, *next_buflen, 1);
-+#endif
-+
-+	return ret;
-+unmap_ctx:
-+	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE);
-+	qi_cache_free(edesc);
-+	return ret;
-+}
-+
-+static int ahash_finup_first(struct ahash_request *req)
-+{
-+	return ahash_digest(req);
-+}
-+
-+static int ahash_init(struct ahash_request *req)
-+{
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+
-+	state->update = ahash_update_first;
-+	state->finup = ahash_finup_first;
-+	state->final = ahash_final_no_ctx;
-+
-+	state->ctx_dma = 0;
-+	state->current_buf = 0;
-+	state->buf_dma = 0;
-+	state->buflen_0 = 0;
-+	state->buflen_1 = 0;
-+
-+	return 0;
-+}
-+
-+static int ahash_update(struct ahash_request *req)
-+{
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+
-+	return state->update(req);
-+}
-+
-+static int ahash_finup(struct ahash_request *req)
-+{
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+
-+	return state->finup(req);
-+}
-+
-+static int ahash_final(struct ahash_request *req)
-+{
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+
-+	return state->final(req);
-+}
-+
-+static int ahash_export(struct ahash_request *req, void *out)
-+{
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	struct caam_export_state *export = out;
-+	int len;
-+	u8 *buf;
-+
-+	if (state->current_buf) {
-+		buf = state->buf_1;
-+		len = state->buflen_1;
-+	} else {
-+		buf = state->buf_0;
-+		len = state->buflen_0;
-+	}
-+
-+	memcpy(export->buf, buf, len);
-+	memcpy(export->caam_ctx, state->caam_ctx, sizeof(export->caam_ctx));
-+	export->buflen = len;
-+	export->update = state->update;
-+	export->final = state->final;
-+	export->finup = state->finup;
-+
-+	return 0;
-+}
-+
-+static int ahash_import(struct ahash_request *req, const void *in)
-+{
-+	struct caam_hash_state *state = ahash_request_ctx(req);
-+	const struct caam_export_state *export = in;
-+
-+	memset(state, 0, sizeof(*state));
-+	memcpy(state->buf_0, export->buf, export->buflen);
-+	memcpy(state->caam_ctx, export->caam_ctx, sizeof(state->caam_ctx));
-+	state->buflen_0 = export->buflen;
-+	state->update = export->update;
-+	state->final = export->final;
-+	state->finup = export->finup;
-+
-+	return 0;
-+}
-+
-+struct caam_hash_template {
-+	char name[CRYPTO_MAX_ALG_NAME];
-+	char driver_name[CRYPTO_MAX_ALG_NAME];
-+	char hmac_name[CRYPTO_MAX_ALG_NAME];
-+	char hmac_driver_name[CRYPTO_MAX_ALG_NAME];
-+	unsigned int blocksize;
-+	struct ahash_alg template_ahash;
-+	u32 alg_type;
-+};
-+
-+/* ahash descriptors */
-+static struct caam_hash_template driver_hash[] = {
-+	{
-+		.name = "sha1",
-+		.driver_name = "sha1-caam-qi2",
-+		.hmac_name = "hmac(sha1)",
-+		.hmac_driver_name = "hmac-sha1-caam-qi2",
-+		.blocksize = SHA1_BLOCK_SIZE,
-+		.template_ahash = {
-+			.init = ahash_init,
-+			.update = ahash_update,
-+			.final = ahash_final,
-+			.finup = ahash_finup,
-+			.digest = ahash_digest,
-+			.export = ahash_export,
-+			.import = ahash_import,
-+			.setkey = ahash_setkey,
-+			.halg = {
-+				.digestsize = SHA1_DIGEST_SIZE,
-+				.statesize = sizeof(struct caam_export_state),
-+			},
-+		},
-+		.alg_type = OP_ALG_ALGSEL_SHA1,
-+	}, {
-+		.name = "sha224",
-+		.driver_name = "sha224-caam-qi2",
-+		.hmac_name = "hmac(sha224)",
-+		.hmac_driver_name = "hmac-sha224-caam-qi2",
-+		.blocksize = SHA224_BLOCK_SIZE,
-+		.template_ahash = {
-+			.init = ahash_init,
-+			.update = ahash_update,
-+			.final = ahash_final,
-+			.finup = ahash_finup,
-+			.digest = ahash_digest,
-+			.export = ahash_export,
-+			.import = ahash_import,
-+			.setkey = ahash_setkey,
-+			.halg = {
-+				.digestsize = SHA224_DIGEST_SIZE,
-+				.statesize = sizeof(struct caam_export_state),
-+			},
-+		},
-+		.alg_type = OP_ALG_ALGSEL_SHA224,
-+	}, {
-+		.name = "sha256",
-+		.driver_name = "sha256-caam-qi2",
-+		.hmac_name = "hmac(sha256)",
-+		.hmac_driver_name = "hmac-sha256-caam-qi2",
-+		.blocksize = SHA256_BLOCK_SIZE,
-+		.template_ahash = {
-+			.init = ahash_init,
-+			.update = ahash_update,
-+			.final = ahash_final,
-+			.finup = ahash_finup,
-+			.digest = ahash_digest,
-+			.export = ahash_export,
-+			.import = ahash_import,
-+			.setkey = ahash_setkey,
-+			.halg = {
-+				.digestsize = SHA256_DIGEST_SIZE,
-+				.statesize = sizeof(struct caam_export_state),
-+			},
-+		},
-+		.alg_type = OP_ALG_ALGSEL_SHA256,
-+	}, {
-+		.name = "sha384",
-+		.driver_name = "sha384-caam-qi2",
-+		.hmac_name = "hmac(sha384)",
-+		.hmac_driver_name = "hmac-sha384-caam-qi2",
-+		.blocksize = SHA384_BLOCK_SIZE,
-+		.template_ahash = {
-+			.init = ahash_init,
-+			.update = ahash_update,
-+			.final = ahash_final,
-+			.finup = ahash_finup,
-+			.digest = ahash_digest,
-+			.export = ahash_export,
-+			.import = ahash_import,
-+			.setkey = ahash_setkey,
-+			.halg = {
-+				.digestsize = SHA384_DIGEST_SIZE,
-+				.statesize = sizeof(struct caam_export_state),
-+			},
-+		},
-+		.alg_type = OP_ALG_ALGSEL_SHA384,
-+	}, {
-+		.name = "sha512",
-+		.driver_name = "sha512-caam-qi2",
-+		.hmac_name = "hmac(sha512)",
-+		.hmac_driver_name = "hmac-sha512-caam-qi2",
-+		.blocksize = SHA512_BLOCK_SIZE,
-+		.template_ahash = {
-+			.init = ahash_init,
-+			.update = ahash_update,
-+			.final = ahash_final,
-+			.finup = ahash_finup,
-+			.digest = ahash_digest,
-+			.export = ahash_export,
-+			.import = ahash_import,
-+			.setkey = ahash_setkey,
-+			.halg = {
-+				.digestsize = SHA512_DIGEST_SIZE,
-+				.statesize = sizeof(struct caam_export_state),
-+			},
-+		},
-+		.alg_type = OP_ALG_ALGSEL_SHA512,
-+	}, {
-+		.name = "md5",
-+		.driver_name = "md5-caam-qi2",
-+		.hmac_name = "hmac(md5)",
-+		.hmac_driver_name = "hmac-md5-caam-qi2",
-+		.blocksize = MD5_BLOCK_WORDS * 4,
-+		.template_ahash = {
-+			.init = ahash_init,
-+			.update = ahash_update,
-+			.final = ahash_final,
-+			.finup = ahash_finup,
-+			.digest = ahash_digest,
-+			.export = ahash_export,
-+			.import = ahash_import,
-+			.setkey = ahash_setkey,
-+			.halg = {
-+				.digestsize = MD5_DIGEST_SIZE,
-+				.statesize = sizeof(struct caam_export_state),
-+			},
-+		},
-+		.alg_type = OP_ALG_ALGSEL_MD5,
-+	}
-+};
-+
-+struct caam_hash_alg {
-+	struct list_head entry;
-+	struct device *dev;
-+	int alg_type;
-+	struct ahash_alg ahash_alg;
-+};
-+
-+static int caam_hash_cra_init(struct crypto_tfm *tfm)
-+{
-+	struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
-+	struct crypto_alg *base = tfm->__crt_alg;
-+	struct hash_alg_common *halg =
-+		 container_of(base, struct hash_alg_common, base);
-+	struct ahash_alg *alg =
-+		 container_of(halg, struct ahash_alg, halg);
-+	struct caam_hash_alg *caam_hash =
-+		 container_of(alg, struct caam_hash_alg, ahash_alg);
-+	struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
-+	/* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
-+	static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
-+					 HASH_MSG_LEN + SHA1_DIGEST_SIZE,
-+					 HASH_MSG_LEN + 32,
-+					 HASH_MSG_LEN + SHA256_DIGEST_SIZE,
-+					 HASH_MSG_LEN + 64,
-+					 HASH_MSG_LEN + SHA512_DIGEST_SIZE };
-+	dma_addr_t dma_addr;
-+	int i;
-+
-+	ctx->dev = caam_hash->dev;
-+
-+	dma_addr = dma_map_single_attrs(ctx->dev, ctx->flc, sizeof(ctx->flc),
-+					DMA_BIDIRECTIONAL,
-+					DMA_ATTR_SKIP_CPU_SYNC);
-+	if (dma_mapping_error(ctx->dev, dma_addr)) {
-+		dev_err(ctx->dev, "unable to map shared descriptors\n");
-+		return -ENOMEM;
-+	}
-+
-+	for (i = 0; i < HASH_NUM_OP; i++)
-+		ctx->flc_dma[i] = dma_addr + i * sizeof(ctx->flc[i]);
-+
-+	/* copy descriptor header template value */
-+	ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
-+
-+	ctx->ctx_len = runninglen[(ctx->adata.algtype &
-+				   OP_ALG_ALGSEL_SUBMASK) >>
-+				  OP_ALG_ALGSEL_SHIFT];
-+
-+	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
-+				 sizeof(struct caam_hash_state));
-+
-+	return ahash_set_sh_desc(ahash);
-+}
-+
-+static void caam_hash_cra_exit(struct crypto_tfm *tfm)
-+{
-+	struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
-+
-+	dma_unmap_single_attrs(ctx->dev, ctx->flc_dma[0], sizeof(ctx->flc),
-+			       DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC);
-+}
-+
-+static struct caam_hash_alg *caam_hash_alloc(struct device *dev,
-+	struct caam_hash_template *template, bool keyed)
-+{
-+	struct caam_hash_alg *t_alg;
-+	struct ahash_alg *halg;
-+	struct crypto_alg *alg;
-+
-+	t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
-+	if (!t_alg)
-+		return ERR_PTR(-ENOMEM);
-+
-+	t_alg->ahash_alg = template->template_ahash;
-+	halg = &t_alg->ahash_alg;
-+	alg = &halg->halg.base;
-+
-+	if (keyed) {
-+		snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
-+			 template->hmac_name);
-+		snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
-+			 template->hmac_driver_name);
-+	} else {
-+		snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
-+			 template->name);
-+		snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
-+			 template->driver_name);
-+		t_alg->ahash_alg.setkey = NULL;
-+	}
-+	alg->cra_module = THIS_MODULE;
-+	alg->cra_init = caam_hash_cra_init;
-+	alg->cra_exit = caam_hash_cra_exit;
-+	alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
-+	alg->cra_priority = CAAM_CRA_PRIORITY;
-+	alg->cra_blocksize = template->blocksize;
-+	alg->cra_alignmask = 0;
-+	alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH;
-+	alg->cra_type = &crypto_ahash_type;
-+
-+	t_alg->alg_type = template->alg_type;
-+	t_alg->dev = dev;
-+
-+	return t_alg;
-+}
-+
-+static void dpaa2_caam_fqdan_cb(struct dpaa2_io_notification_ctx *nctx)
-+{
-+	struct dpaa2_caam_priv_per_cpu *ppriv;
-+
-+	ppriv = container_of(nctx, struct dpaa2_caam_priv_per_cpu, nctx);
-+	napi_schedule_irqoff(&ppriv->napi);
-+}
-+
-+static int __cold dpaa2_dpseci_dpio_setup(struct dpaa2_caam_priv *priv)
-+{
-+	struct device *dev = priv->dev;
-+	struct dpaa2_io_notification_ctx *nctx;
-+	struct dpaa2_caam_priv_per_cpu *ppriv;
-+	int err, i = 0, cpu;
-+
-+	for_each_online_cpu(cpu) {
-+		ppriv = per_cpu_ptr(priv->ppriv, cpu);
-+		ppriv->priv = priv;
-+		nctx = &ppriv->nctx;
-+		nctx->is_cdan = 0;
-+		nctx->id = ppriv->rsp_fqid;
-+		nctx->desired_cpu = cpu;
-+		nctx->cb = dpaa2_caam_fqdan_cb;
-+
-+		/* Register notification callbacks */
-+		err = dpaa2_io_service_register(NULL, nctx);
-+		if (unlikely(err)) {
-+			dev_dbg(dev, "No affine DPIO for cpu %d\n", cpu);
-+			nctx->cb = NULL;
-+			/*
-+			 * If no affine DPIO for this core, there's probably
-+			 * none available for next cores either. Signal we want
-+			 * to retry later, in case the DPIO devices weren't
-+			 * probed yet.
-+			 */
-+			err = -EPROBE_DEFER;
-+			goto err;
-+		}
-+
-+		ppriv->store = dpaa2_io_store_create(DPAA2_CAAM_STORE_SIZE,
-+						     dev);
-+		if (unlikely(!ppriv->store)) {
-+			dev_err(dev, "dpaa2_io_store_create() failed\n");
-+			goto err;
-+		}
-+
-+		if (++i == priv->num_pairs)
-+			break;
-+	}
-+
-+	return 0;
-+
-+err:
-+	for_each_online_cpu(cpu) {
-+		ppriv = per_cpu_ptr(priv->ppriv, cpu);
-+		if (!ppriv->nctx.cb)
-+			break;
-+		dpaa2_io_service_deregister(NULL, &ppriv->nctx);
-+	}
-+
-+	for_each_online_cpu(cpu) {
-+		ppriv = per_cpu_ptr(priv->ppriv, cpu);
-+		if (!ppriv->store)
-+			break;
-+		dpaa2_io_store_destroy(ppriv->store);
-+	}
-+
-+	return err;
-+}
-+
-+static void __cold dpaa2_dpseci_dpio_free(struct dpaa2_caam_priv *priv)
-+{
-+	struct dpaa2_caam_priv_per_cpu *ppriv;
-+	int i = 0, cpu;
-+
-+	for_each_online_cpu(cpu) {
-+		ppriv = per_cpu_ptr(priv->ppriv, cpu);
-+		dpaa2_io_service_deregister(NULL, &ppriv->nctx);
-+		dpaa2_io_store_destroy(ppriv->store);
-+
-+		if (++i == priv->num_pairs)
-+			return;
-+	}
-+}
-+
-+static int dpaa2_dpseci_bind(struct dpaa2_caam_priv *priv)
-+{
-+	struct dpseci_rx_queue_cfg rx_queue_cfg;
-+	struct device *dev = priv->dev;
-+	struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
-+	struct dpaa2_caam_priv_per_cpu *ppriv;
-+	int err = 0, i = 0, cpu;
-+
-+	/* Configure Rx queues */
-+	for_each_online_cpu(cpu) {
-+		ppriv = per_cpu_ptr(priv->ppriv, cpu);
-+
-+		rx_queue_cfg.options = DPSECI_QUEUE_OPT_DEST |
-+				       DPSECI_QUEUE_OPT_USER_CTX;
-+		rx_queue_cfg.order_preservation_en = 0;
-+		rx_queue_cfg.dest_cfg.dest_type = DPSECI_DEST_DPIO;
-+		rx_queue_cfg.dest_cfg.dest_id = ppriv->nctx.dpio_id;
-+		/*
-+		 * Rx priority (WQ) doesn't really matter, since we use
-+		 * pull mode, i.e. volatile dequeues from specific FQs
-+		 */
-+		rx_queue_cfg.dest_cfg.priority = 0;
-+		rx_queue_cfg.user_ctx = ppriv->nctx.qman64;
-+
-+		err = dpseci_set_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
-+					  &rx_queue_cfg);
-+		if (err) {
-+			dev_err(dev, "dpseci_set_rx_queue() failed with err %d\n",
-+				err);
-+			return err;
-+		}
-+
-+		if (++i == priv->num_pairs)
-+			break;
-+	}
-+
-+	return err;
-+}
-+
-+static void dpaa2_dpseci_congestion_free(struct dpaa2_caam_priv *priv)
-+{
-+	struct device *dev = priv->dev;
-+
-+	if (!priv->cscn_mem)
-+		return;
-+
-+	dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
-+	kfree(priv->cscn_mem);
-+}
-+
-+static void dpaa2_dpseci_free(struct dpaa2_caam_priv *priv)
-+{
-+	struct device *dev = priv->dev;
-+	struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
-+
-+	dpaa2_dpseci_congestion_free(priv);
-+	dpseci_close(priv->mc_io, 0, ls_dev->mc_handle);
-+}
-+
-+static void dpaa2_caam_process_fd(struct dpaa2_caam_priv *priv,
-+				  const struct dpaa2_fd *fd)
-+{
-+	struct caam_request *req;
-+	u32 fd_err;
-+
-+	if (dpaa2_fd_get_format(fd) != dpaa2_fd_list) {
-+		dev_err(priv->dev, "Only Frame List FD format is supported!\n");
-+		return;
-+	}
-+
-+	fd_err = dpaa2_fd_get_ctrl(fd) & FD_CTRL_ERR_MASK;
-+	if (unlikely(fd_err))
-+		dev_err(priv->dev, "FD error: %08x\n", fd_err);
-+
-+	/*
-+	 * FD[ADDR] is guaranteed to be valid, irrespective of errors reported
-+	 * in FD[ERR] or FD[FRC].
-+	 */
-+	req = dpaa2_caam_iova_to_virt(priv, dpaa2_fd_get_addr(fd));
-+	dma_unmap_single(priv->dev, req->fd_flt_dma, sizeof(req->fd_flt),
-+			 DMA_BIDIRECTIONAL);
-+	req->cbk(req->ctx, dpaa2_fd_get_frc(fd));
-+}
-+
-+static int dpaa2_caam_pull_fq(struct dpaa2_caam_priv_per_cpu *ppriv)
-+{
-+	int err;
-+
-+	/* Retry while portal is busy */
-+	do {
-+		err = dpaa2_io_service_pull_fq(NULL, ppriv->rsp_fqid,
-+					       ppriv->store);
-+	} while (err == -EBUSY);
-+
-+	if (unlikely(err))
-+		dev_err(ppriv->priv->dev, "dpaa2_io_service_pull err %d", err);
-+
-+	return err;
-+}
-+
-+static int dpaa2_caam_store_consume(struct dpaa2_caam_priv_per_cpu *ppriv)
-+{
-+	struct dpaa2_dq *dq;
-+	int cleaned = 0, is_last;
-+
-+	do {
-+		dq = dpaa2_io_store_next(ppriv->store, &is_last);
-+		if (unlikely(!dq)) {
-+			if (unlikely(!is_last)) {
-+				dev_dbg(ppriv->priv->dev,
-+					"FQ %d returned no valid frames\n",
-+					ppriv->rsp_fqid);
-+				/*
-+				 * MUST retry until we get some sort of
-+				 * valid response token (be it "empty dequeue"
-+				 * or a valid frame).
-+				 */
-+				continue;
-+			}
-+			break;
-+		}
-+
-+		/* Process FD */
-+		dpaa2_caam_process_fd(ppriv->priv, dpaa2_dq_fd(dq));
-+		cleaned++;
-+	} while (!is_last);
-+
-+	return cleaned;
-+}
-+
-+static int dpaa2_dpseci_poll(struct napi_struct *napi, int budget)
-+{
-+	struct dpaa2_caam_priv_per_cpu *ppriv;
-+	struct dpaa2_caam_priv *priv;
-+	int err, cleaned = 0, store_cleaned;
-+
-+	ppriv = container_of(napi, struct dpaa2_caam_priv_per_cpu, napi);
-+	priv = ppriv->priv;
-+
-+	if (unlikely(dpaa2_caam_pull_fq(ppriv)))
-+		return 0;
-+
-+	do {
-+		store_cleaned = dpaa2_caam_store_consume(ppriv);
-+		cleaned += store_cleaned;
-+
-+		if (store_cleaned == 0 ||
-+		    cleaned > budget - DPAA2_CAAM_STORE_SIZE)
-+			break;
-+
-+		/* Try to dequeue some more */
-+		err = dpaa2_caam_pull_fq(ppriv);
-+		if (unlikely(err))
-+			break;
-+	} while (1);
-+
-+	if (cleaned < budget) {
-+		napi_complete_done(napi, cleaned);
-+		err = dpaa2_io_service_rearm(NULL, &ppriv->nctx);
-+		if (unlikely(err))
-+			dev_err(priv->dev, "Notification rearm failed: %d\n",
-+				err);
-+	}
-+
-+	return cleaned;
-+}
-+
-+static int dpaa2_dpseci_congestion_setup(struct dpaa2_caam_priv *priv,
-+					 u16 token)
-+{
-+	struct dpseci_congestion_notification_cfg cong_notif_cfg = { 0 };
-+	struct device *dev = priv->dev;
-+	int err;
-+
-+	/*
-+	 * Congestion group feature supported starting with DPSECI API v5.1
-+	 * and only when object has been created with this capability.
-+	 */
-+	if ((DPSECI_VER(priv->major_ver, priv->minor_ver) < DPSECI_VER(5, 1)) ||
-+	    !(priv->dpseci_attr.options & DPSECI_OPT_HAS_CG))
-+		return 0;
-+
-+	priv->cscn_mem = kzalloc(DPAA2_CSCN_SIZE + DPAA2_CSCN_ALIGN,
-+				 GFP_KERNEL | GFP_DMA);
-+	if (!priv->cscn_mem)
-+		return -ENOMEM;
-+
-+	priv->cscn_mem_aligned = PTR_ALIGN(priv->cscn_mem, DPAA2_CSCN_ALIGN);
-+	priv->cscn_dma = dma_map_single(dev, priv->cscn_mem_aligned,
-+					DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
-+	if (dma_mapping_error(dev, priv->cscn_dma)) {
-+		dev_err(dev, "Error mapping CSCN memory area\n");
-+		err = -ENOMEM;
-+		goto err_dma_map;
-+	}
-+
-+	cong_notif_cfg.units = DPSECI_CONGESTION_UNIT_BYTES;
-+	cong_notif_cfg.threshold_entry = DPAA2_SEC_CONG_ENTRY_THRESH;
-+	cong_notif_cfg.threshold_exit = DPAA2_SEC_CONG_EXIT_THRESH;
-+	cong_notif_cfg.message_ctx = (u64)priv;
-+	cong_notif_cfg.message_iova = priv->cscn_dma;
-+	cong_notif_cfg.notification_mode = DPSECI_CGN_MODE_WRITE_MEM_ON_ENTER |
-+					DPSECI_CGN_MODE_WRITE_MEM_ON_EXIT |
-+					DPSECI_CGN_MODE_COHERENT_WRITE;
-+
-+	err = dpseci_set_congestion_notification(priv->mc_io, 0, token,
-+						 &cong_notif_cfg);
-+	if (err) {
-+		dev_err(dev, "dpseci_set_congestion_notification failed\n");
-+		goto err_set_cong;
-+	}
-+
-+	return 0;
-+
-+err_set_cong:
-+	dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
-+err_dma_map:
-+	kfree(priv->cscn_mem);
-+
-+	return err;
-+}
-+
-+static int __cold dpaa2_dpseci_setup(struct fsl_mc_device *ls_dev)
-+{
-+	struct device *dev = &ls_dev->dev;
-+	struct dpaa2_caam_priv *priv;
-+	struct dpaa2_caam_priv_per_cpu *ppriv;
-+	int err, cpu;
-+	u8 i;
-+
-+	priv = dev_get_drvdata(dev);
-+
-+	priv->dev = dev;
-+	priv->dpsec_id = ls_dev->obj_desc.id;
-+
-+	/* Get a handle for the DPSECI this interface is associate with */
-+	err = dpseci_open(priv->mc_io, 0, priv->dpsec_id, &ls_dev->mc_handle);
-+	if (err) {
-+		dev_err(dev, "dpsec_open() failed: %d\n", err);
-+		goto err_open;
-+	}
-+
-+	dev_info(dev, "Opened dpseci object successfully\n");
-+
-+	err = dpseci_get_api_version(priv->mc_io, 0, &priv->major_ver,
-+				     &priv->minor_ver);
-+	if (err) {
-+		dev_err(dev, "dpseci_get_api_version() failed\n");
-+		goto err_get_vers;
-+	}
-+
-+	err = dpseci_get_attributes(priv->mc_io, 0, ls_dev->mc_handle,
-+				    &priv->dpseci_attr);
-+	if (err) {
-+		dev_err(dev, "dpseci_get_attributes() failed\n");
-+		goto err_get_vers;
-+	}
-+
-+	err = dpseci_get_sec_attr(priv->mc_io, 0, ls_dev->mc_handle,
-+				  &priv->sec_attr);
-+	if (err) {
-+		dev_err(dev, "dpseci_get_sec_attr() failed\n");
-+		goto err_get_vers;
-+	}
-+
-+	err = dpaa2_dpseci_congestion_setup(priv, ls_dev->mc_handle);
-+	if (err) {
-+		dev_err(dev, "setup_congestion() failed\n");
-+		goto err_get_vers;
-+	}
-+
-+	priv->num_pairs = min(priv->dpseci_attr.num_rx_queues,
-+			      priv->dpseci_attr.num_tx_queues);
-+	if (priv->num_pairs > num_online_cpus()) {
-+		dev_warn(dev, "%d queues won't be used\n",
-+			 priv->num_pairs - num_online_cpus());
-+		priv->num_pairs = num_online_cpus();
-+	}
-+
-+	for (i = 0; i < priv->dpseci_attr.num_rx_queues; i++) {
-+		err = dpseci_get_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
-+					  &priv->rx_queue_attr[i]);
-+		if (err) {
-+			dev_err(dev, "dpseci_get_rx_queue() failed\n");
-+			goto err_get_rx_queue;
-+		}
-+	}
-+
-+	for (i = 0; i < priv->dpseci_attr.num_tx_queues; i++) {
-+		err = dpseci_get_tx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
-+					  &priv->tx_queue_attr[i]);
-+		if (err) {
-+			dev_err(dev, "dpseci_get_tx_queue() failed\n");
-+			goto err_get_rx_queue;
-+		}
-+	}
-+
-+	i = 0;
-+	for_each_online_cpu(cpu) {
-+		dev_info(dev, "pair %d: rx queue %d, tx queue %d\n", i,
-+			 priv->rx_queue_attr[i].fqid,
-+			 priv->tx_queue_attr[i].fqid);
-+
-+		ppriv = per_cpu_ptr(priv->ppriv, cpu);
-+		ppriv->req_fqid = priv->tx_queue_attr[i].fqid;
-+		ppriv->rsp_fqid = priv->rx_queue_attr[i].fqid;
-+		ppriv->prio = i;
-+
-+		ppriv->net_dev.dev = *dev;
-+		INIT_LIST_HEAD(&ppriv->net_dev.napi_list);
-+		netif_napi_add(&ppriv->net_dev, &ppriv->napi, dpaa2_dpseci_poll,
-+			       DPAA2_CAAM_NAPI_WEIGHT);
-+		if (++i == priv->num_pairs)
-+			break;
-+	}
-+
-+	return 0;
-+
-+err_get_rx_queue:
-+	dpaa2_dpseci_congestion_free(priv);
-+err_get_vers:
-+	dpseci_close(priv->mc_io, 0, ls_dev->mc_handle);
-+err_open:
-+	return err;
-+}
-+
-+static int dpaa2_dpseci_enable(struct dpaa2_caam_priv *priv)
-+{
-+	struct device *dev = priv->dev;
-+	struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
-+	struct dpaa2_caam_priv_per_cpu *ppriv;
-+	int err, i;
-+
-+	for (i = 0; i < priv->num_pairs; i++) {
-+		ppriv = per_cpu_ptr(priv->ppriv, i);
-+		napi_enable(&ppriv->napi);
-+	}
-+
-+	err = dpseci_enable(priv->mc_io, 0, ls_dev->mc_handle);
-+	if (err) {
-+		dev_err(dev, "dpseci_enable() failed\n");
-+		return err;
-+	}
-+
-+	dev_info(dev, "DPSECI version %d.%d\n",
-+		 priv->major_ver,
-+		 priv->minor_ver);
-+
-+	return 0;
-+}
-+
-+static int __cold dpaa2_dpseci_disable(struct dpaa2_caam_priv *priv)
-+{
-+	struct device *dev = priv->dev;
-+	struct dpaa2_caam_priv_per_cpu *ppriv;
-+	struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
-+	int i, err = 0, enabled;
-+
-+	err = dpseci_disable(priv->mc_io, 0, ls_dev->mc_handle);
-+	if (err) {
-+		dev_err(dev, "dpseci_disable() failed\n");
-+		return err;
-+	}
-+
-+	err = dpseci_is_enabled(priv->mc_io, 0, ls_dev->mc_handle, &enabled);
-+	if (err) {
-+		dev_err(dev, "dpseci_is_enabled() failed\n");
-+		return err;
-+	}
-+
-+	dev_dbg(dev, "disable: %s\n", enabled ? "false" : "true");
-+
-+	for (i = 0; i < priv->num_pairs; i++) {
-+		ppriv = per_cpu_ptr(priv->ppriv, i);
-+		napi_disable(&ppriv->napi);
-+		netif_napi_del(&ppriv->napi);
-+	}
-+
-+	return 0;
-+}
-+
-+static struct list_head hash_list;
-+
-+static int dpaa2_caam_probe(struct fsl_mc_device *dpseci_dev)
-+{
-+	struct device *dev;
-+	struct dpaa2_caam_priv *priv;
-+	int i, err = 0;
-+	bool registered = false;
-+
-+	/*
-+	 * There is no way to get CAAM endianness - there is no direct register
-+	 * space access and MC f/w does not provide this attribute.
-+	 * All DPAA2-based SoCs have little endian CAAM, thus hard-code this
-+	 * property.
-+	 */
-+	caam_little_end = true;
-+
-+	caam_imx = false;
-+
-+	dev = &dpseci_dev->dev;
-+
-+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-+	if (!priv)
-+		return -ENOMEM;
-+
-+	dev_set_drvdata(dev, priv);
-+
-+	priv->domain = iommu_get_domain_for_dev(dev);
-+
-+	qi_cache = kmem_cache_create("dpaa2_caamqicache", CAAM_QI_MEMCACHE_SIZE,
-+				     0, SLAB_CACHE_DMA, NULL);
-+	if (!qi_cache) {
-+		dev_err(dev, "Can't allocate SEC cache\n");
-+		err = -ENOMEM;
-+		goto err_qicache;
-+	}
-+
-+	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
-+	if (err) {
-+		dev_err(dev, "dma_set_mask_and_coherent() failed\n");
-+		goto err_dma_mask;
-+	}
-+
-+	/* Obtain a MC portal */
-+	err = fsl_mc_portal_allocate(dpseci_dev, 0, &priv->mc_io);
-+	if (err) {
-+		if (err == -ENXIO)
-+			err = -EPROBE_DEFER;
-+		else
-+			dev_err(dev, "MC portal allocation failed\n");
-+
-+		goto err_dma_mask;
-+	}
-+
-+	priv->ppriv = alloc_percpu(*priv->ppriv);
-+	if (!priv->ppriv) {
-+		dev_err(dev, "alloc_percpu() failed\n");
-+		goto err_alloc_ppriv;
-+	}
-+
-+	/* DPSECI initialization */
-+	err = dpaa2_dpseci_setup(dpseci_dev);
-+	if (err < 0) {
-+		dev_err(dev, "dpaa2_dpseci_setup() failed\n");
-+		goto err_dpseci_setup;
-+	}
-+
-+	/* DPIO */
-+	err = dpaa2_dpseci_dpio_setup(priv);
-+	if (err) {
-+		dev_err(dev, "dpaa2_dpseci_dpio_setup() failed\n");
-+		goto err_dpio_setup;
-+	}
-+
-+	/* DPSECI binding to DPIO */
-+	err = dpaa2_dpseci_bind(priv);
-+	if (err) {
-+		dev_err(dev, "dpaa2_dpseci_bind() failed\n");
-+		goto err_bind;
-+	}
-+
-+	/* DPSECI enable */
-+	err = dpaa2_dpseci_enable(priv);
-+	if (err) {
-+		dev_err(dev, "dpaa2_dpseci_enable() failed");
-+		goto err_bind;
-+	}
-+
-+	/* register crypto algorithms the device supports */
-+	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
-+		struct caam_skcipher_alg *t_alg = driver_algs + i;
-+		u32 alg_sel = t_alg->caam.class1_alg_type & OP_ALG_ALGSEL_MASK;
-+
-+		/* Skip DES algorithms if not supported by device */
-+		if (!priv->sec_attr.des_acc_num &&
-+		    ((alg_sel == OP_ALG_ALGSEL_3DES) ||
-+		     (alg_sel == OP_ALG_ALGSEL_DES)))
-+			continue;
-+
-+		/* Skip AES algorithms if not supported by device */
-+		if (!priv->sec_attr.aes_acc_num &&
-+		    (alg_sel == OP_ALG_ALGSEL_AES))
-+			continue;
-+
-+		t_alg->caam.dev = dev;
-+		caam_skcipher_alg_init(t_alg);
-+
-+		err = crypto_register_skcipher(&t_alg->skcipher);
-+		if (err) {
-+			dev_warn(dev, "%s alg registration failed: %d\n",
-+				 t_alg->skcipher.base.cra_driver_name, err);
-+			continue;
-+		}
-+
-+		t_alg->registered = true;
-+		registered = true;
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
-+		struct caam_aead_alg *t_alg = driver_aeads + i;
-+		u32 c1_alg_sel = t_alg->caam.class1_alg_type &
-+				 OP_ALG_ALGSEL_MASK;
-+		u32 c2_alg_sel = t_alg->caam.class2_alg_type &
-+				 OP_ALG_ALGSEL_MASK;
-+
-+		/* Skip DES algorithms if not supported by device */
-+		if (!priv->sec_attr.des_acc_num &&
-+		    ((c1_alg_sel == OP_ALG_ALGSEL_3DES) ||
-+		     (c1_alg_sel == OP_ALG_ALGSEL_DES)))
-+			continue;
-+
-+		/* Skip AES algorithms if not supported by device */
-+		if (!priv->sec_attr.aes_acc_num &&
-+		    (c1_alg_sel == OP_ALG_ALGSEL_AES))
-+			continue;
-+
-+		/*
-+		 * Skip algorithms requiring message digests
-+		 * if MD not supported by device.
-+		 */
-+		if (!priv->sec_attr.md_acc_num && c2_alg_sel)
-+			continue;
-+
-+		t_alg->caam.dev = dev;
-+		caam_aead_alg_init(t_alg);
-+
-+		err = crypto_register_aead(&t_alg->aead);
-+		if (err) {
-+			dev_warn(dev, "%s alg registration failed: %d\n",
-+				 t_alg->aead.base.cra_driver_name, err);
-+			continue;
-+		}
-+
-+		t_alg->registered = true;
-+		registered = true;
-+	}
-+	if (registered)
-+		dev_info(dev, "algorithms registered in /proc/crypto\n");
-+
-+	/* register hash algorithms the device supports */
-+	INIT_LIST_HEAD(&hash_list);
-+
-+	/*
-+	 * Skip registration of any hashing algorithms if MD block
-+	 * is not present.
-+	 */
-+	if (!priv->sec_attr.md_acc_num)
-+		return 0;
-+
-+	for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
-+		struct caam_hash_alg *t_alg;
-+		struct caam_hash_template *alg = driver_hash + i;
-+
-+		/* register hmac version */
-+		t_alg = caam_hash_alloc(dev, alg, true);
-+		if (IS_ERR(t_alg)) {
-+			err = PTR_ERR(t_alg);
-+			dev_warn(dev, "%s hash alg allocation failed: %d\n",
-+				 alg->driver_name, err);
-+			continue;
-+		}
-+
-+		err = crypto_register_ahash(&t_alg->ahash_alg);
-+		if (err) {
-+			dev_warn(dev, "%s alg registration failed: %d\n",
-+				 t_alg->ahash_alg.halg.base.cra_driver_name,
-+				 err);
-+			kfree(t_alg);
-+		} else {
-+			list_add_tail(&t_alg->entry, &hash_list);
-+		}
-+
-+		/* register unkeyed version */
-+		t_alg = caam_hash_alloc(dev, alg, false);
-+		if (IS_ERR(t_alg)) {
-+			err = PTR_ERR(t_alg);
-+			dev_warn(dev, "%s alg allocation failed: %d\n",
-+				 alg->driver_name, err);
-+			continue;
-+		}
-+
-+		err = crypto_register_ahash(&t_alg->ahash_alg);
-+		if (err) {
-+			dev_warn(dev, "%s alg registration failed: %d\n",
-+				 t_alg->ahash_alg.halg.base.cra_driver_name,
-+				 err);
-+			kfree(t_alg);
-+		} else {
-+			list_add_tail(&t_alg->entry, &hash_list);
-+		}
-+	}
-+	if (!list_empty(&hash_list))
-+		dev_info(dev, "hash algorithms registered in /proc/crypto\n");
-+
-+	return err;
-+
-+err_bind:
-+	dpaa2_dpseci_dpio_free(priv);
-+err_dpio_setup:
-+	dpaa2_dpseci_free(priv);
-+err_dpseci_setup:
-+	free_percpu(priv->ppriv);
-+err_alloc_ppriv:
-+	fsl_mc_portal_free(priv->mc_io);
-+err_dma_mask:
-+	kmem_cache_destroy(qi_cache);
-+err_qicache:
-+	dev_set_drvdata(dev, NULL);
-+
-+	return err;
-+}
-+
-+static int __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev)
-+{
-+	struct device *dev;
-+	struct dpaa2_caam_priv *priv;
-+	int i;
-+
-+	dev = &ls_dev->dev;
-+	priv = dev_get_drvdata(dev);
-+
-+	for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
-+		struct caam_aead_alg *t_alg = driver_aeads + i;
-+
-+		if (t_alg->registered)
-+			crypto_unregister_aead(&t_alg->aead);
-+	}
-+
-+	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
-+		struct caam_skcipher_alg *t_alg = driver_algs + i;
-+
-+		if (t_alg->registered)
-+			crypto_unregister_skcipher(&t_alg->skcipher);
-+	}
-+
-+	if (hash_list.next) {
-+		struct caam_hash_alg *t_hash_alg, *p;
-+
-+		list_for_each_entry_safe(t_hash_alg, p, &hash_list, entry) {
-+			crypto_unregister_ahash(&t_hash_alg->ahash_alg);
-+			list_del(&t_hash_alg->entry);
-+			kfree(t_hash_alg);
-+		}
-+	}
-+
-+	dpaa2_dpseci_disable(priv);
-+	dpaa2_dpseci_dpio_free(priv);
-+	dpaa2_dpseci_free(priv);
-+	free_percpu(priv->ppriv);
-+	fsl_mc_portal_free(priv->mc_io);
-+	dev_set_drvdata(dev, NULL);
-+	kmem_cache_destroy(qi_cache);
-+
-+	return 0;
-+}
-+
-+int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req)
-+{
-+	struct dpaa2_fd fd;
-+	struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
-+	int err = 0, i, id;
-+
-+	if (IS_ERR(req))
-+		return PTR_ERR(req);
-+
-+	if (priv->cscn_mem) {
-+		dma_sync_single_for_cpu(priv->dev, priv->cscn_dma,
-+					DPAA2_CSCN_SIZE,
-+					DMA_FROM_DEVICE);
-+		if (unlikely(dpaa2_cscn_state_congested(priv->cscn_mem_aligned))) {
-+			dev_dbg_ratelimited(dev, "Dropping request\n");
-+			return -EBUSY;
-+		}
-+	}
-+
-+	dpaa2_fl_set_flc(&req->fd_flt[1], req->flc_dma);
-+
-+	req->fd_flt_dma = dma_map_single(dev, req->fd_flt, sizeof(req->fd_flt),
-+					 DMA_BIDIRECTIONAL);
-+	if (dma_mapping_error(dev, req->fd_flt_dma)) {
-+		dev_err(dev, "DMA mapping error for QI enqueue request\n");
-+		goto err_out;
-+	}
-+
-+	memset(&fd, 0, sizeof(fd));
-+	dpaa2_fd_set_format(&fd, dpaa2_fd_list);
-+	dpaa2_fd_set_addr(&fd, req->fd_flt_dma);
-+	dpaa2_fd_set_len(&fd, dpaa2_fl_get_len(&req->fd_flt[1]));
-+	dpaa2_fd_set_flc(&fd, req->flc_dma);
-+
-+	/*
-+	 * There is no guarantee that preemption is disabled here,
-+	 * thus take action.
-+	 */
-+	preempt_disable();
-+	id = smp_processor_id() % priv->dpseci_attr.num_tx_queues;
-+	for (i = 0; i < (priv->dpseci_attr.num_tx_queues << 1); i++) {
-+		err = dpaa2_io_service_enqueue_fq(NULL,
-+						  priv->tx_queue_attr[id].fqid,
-+						  &fd);
-+		if (err != -EBUSY)
-+			break;
-+	}
-+	preempt_enable();
-+
-+	if (unlikely(err < 0)) {
-+		dev_err(dev, "Error enqueuing frame: %d\n", err);
-+		goto err_out;
-+	}
-+
-+	return -EINPROGRESS;
-+
-+err_out:
-+	dma_unmap_single(dev, req->fd_flt_dma, sizeof(req->fd_flt),
-+			 DMA_BIDIRECTIONAL);
-+	return -EIO;
-+}
-+EXPORT_SYMBOL(dpaa2_caam_enqueue);
-+
-+const struct fsl_mc_device_id dpaa2_caam_match_id_table[] = {
-+	{
-+		.vendor = FSL_MC_VENDOR_FREESCALE,
-+		.obj_type = "dpseci",
-+	},
-+	{ .vendor = 0x0 }
-+};
-+
-+static struct fsl_mc_driver dpaa2_caam_driver = {
-+	.driver = {
-+		.name		= KBUILD_MODNAME,
-+		.owner		= THIS_MODULE,
-+	},
-+	.probe		= dpaa2_caam_probe,
-+	.remove		= dpaa2_caam_remove,
-+	.match_id_table = dpaa2_caam_match_id_table
-+};
-+
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_AUTHOR("Freescale Semiconductor, Inc");
-+MODULE_DESCRIPTION("Freescale DPAA2 CAAM Driver");
-+
-+module_fsl_mc_driver(dpaa2_caam_driver);
---- /dev/null
-+++ b/drivers/crypto/caam/caamalg_qi2.h
-@@ -0,0 +1,274 @@
-+/*
-+ * Copyright 2015-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the names of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef _CAAMALG_QI2_H_
-+#define _CAAMALG_QI2_H_
-+
-+#include "../../../drivers/staging/fsl-mc/include/dpaa2-io.h"
-+#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
-+#include <linux/threads.h>
-+#include "dpseci.h"
-+#include "desc_constr.h"
-+
-+#define DPAA2_CAAM_STORE_SIZE	16
-+/* NAPI weight *must* be a multiple of the store size. */
-+#define DPAA2_CAAM_NAPI_WEIGHT	64
-+
-+/* The congestion entrance threshold was chosen so that on LS2088
-+ * we support the maximum throughput for the available memory
-+ */
-+#define DPAA2_SEC_CONG_ENTRY_THRESH	(128 * 1024 * 1024)
-+#define DPAA2_SEC_CONG_EXIT_THRESH	(DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
-+
-+/**
-+ * dpaa2_caam_priv - driver private data
-+ * @dpseci_id: DPSECI object unique ID
-+ * @major_ver: DPSECI major version
-+ * @minor_ver: DPSECI minor version
-+ * @dpseci_attr: DPSECI attributes
-+ * @sec_attr: SEC engine attributes
-+ * @rx_queue_attr: array of Rx queue attributes
-+ * @tx_queue_attr: array of Tx queue attributes
-+ * @cscn_mem: pointer to memory region containing the
-+ *	dpaa2_cscn struct; it's size is larger than
-+ *	sizeof(struct dpaa2_cscn) to accommodate alignment
-+ * @cscn_mem_aligned: pointer to struct dpaa2_cscn; it is computed
-+ *	as PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
-+ * @cscn_dma: dma address used by the QMAN to write CSCN messages
-+ * @dev: device associated with the DPSECI object
-+ * @mc_io: pointer to MC portal's I/O object
-+ * @domain: IOMMU domain
-+ * @ppriv: per CPU pointers to privata data
-+ */
-+struct dpaa2_caam_priv {
-+	int dpsec_id;
-+
-+	u16 major_ver;
-+	u16 minor_ver;
-+
-+	struct dpseci_attr dpseci_attr;
-+	struct dpseci_sec_attr sec_attr;
-+	struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];
-+	struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];
-+	int num_pairs;
-+
-+	/* congestion */
-+	void *cscn_mem;
-+	void *cscn_mem_aligned;
-+	dma_addr_t cscn_dma;
-+
-+	struct device *dev;
-+	struct fsl_mc_io *mc_io;
-+	struct iommu_domain *domain;
-+
-+	struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
-+};
-+
-+/**
-+ * dpaa2_caam_priv_per_cpu - per CPU private data
-+ * @napi: napi structure
-+ * @net_dev: netdev used by napi
-+ * @req_fqid: (virtual) request (Tx / enqueue) FQID
-+ * @rsp_fqid: (virtual) response (Rx / dequeue) FQID
-+ * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
-+ * @nctx: notification context of response FQ
-+ * @store: where dequeued frames are stored
-+ * @priv: backpointer to dpaa2_caam_priv
-+ */
-+struct dpaa2_caam_priv_per_cpu {
-+	struct napi_struct napi;
-+	struct net_device net_dev;
-+	int req_fqid;
-+	int rsp_fqid;
-+	int prio;
-+	struct dpaa2_io_notification_ctx nctx;
-+	struct dpaa2_io_store *store;
-+	struct dpaa2_caam_priv *priv;
-+};
-+
-+/*
-+ * The CAAM QI hardware constructs a job descriptor which points
-+ * to shared descriptor (as pointed by context_a of FQ to CAAM).
-+ * When the job descriptor is executed by deco, the whole job
-+ * descriptor together with shared descriptor gets loaded in
-+ * deco buffer which is 64 words long (each 32-bit).
-+ *
-+ * The job descriptor constructed by QI hardware has layout:
-+ *
-+ *	HEADER		(1 word)
-+ *	Shdesc ptr	(1 or 2 words)
-+ *	SEQ_OUT_PTR	(1 word)
-+ *	Out ptr		(1 or 2 words)
-+ *	Out length	(1 word)
-+ *	SEQ_IN_PTR	(1 word)
-+ *	In ptr		(1 or 2 words)
-+ *	In length	(1 word)
-+ *
-+ * The shdesc ptr is used to fetch shared descriptor contents
-+ * into deco buffer.
-+ *
-+ * Apart from shdesc contents, the total number of words that
-+ * get loaded in deco buffer are '8' or '11'. The remaining words
-+ * in deco buffer can be used for storing shared descriptor.
-+ */
-+#define MAX_SDLEN	((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
-+
-+/* Length of a single buffer in the QI driver memory cache */
-+#define CAAM_QI_MEMCACHE_SIZE	512
-+
-+/*
-+ * aead_edesc - s/w-extended aead descriptor
-+ * @src_nents: number of segments in input scatterlist
-+ * @dst_nents: number of segments in output scatterlist
-+ * @iv_dma: dma address of iv for checking continuity and link table
-+ * @qm_sg_bytes: length of dma mapped h/w link table
-+ * @qm_sg_dma: bus physical mapped address of h/w link table
-+ * @assoclen: associated data length, in CAAM endianness
-+ * @assoclen_dma: bus physical mapped address of req->assoclen
-+ * @sgt: the h/w link table, followed by IV
-+ */
-+struct aead_edesc {
-+	int src_nents;
-+	int dst_nents;
-+	dma_addr_t iv_dma;
-+	int qm_sg_bytes;
-+	dma_addr_t qm_sg_dma;
-+	unsigned int assoclen;
-+	dma_addr_t assoclen_dma;
-+	struct dpaa2_sg_entry sgt[0];
-+};
-+
-+/*
-+ * tls_edesc - s/w-extended tls descriptor
-+ * @src_nents: number of segments in input scatterlist
-+ * @dst_nents: number of segments in output scatterlist
-+ * @iv_dma: dma address of iv for checking continuity and link table
-+ * @qm_sg_bytes: length of dma mapped h/w link table
-+ * @qm_sg_dma: bus physical mapped address of h/w link table
-+ * @tmp: array of scatterlists used by 'scatterwalk_ffwd'
-+ * @dst: pointer to output scatterlist, usefull for unmapping
-+ * @sgt: the h/w link table, followed by IV
-+ */
-+struct tls_edesc {
-+	int src_nents;
-+	int dst_nents;
-+	dma_addr_t iv_dma;
-+	int qm_sg_bytes;
-+	dma_addr_t qm_sg_dma;
-+	struct scatterlist tmp[2];
-+	struct scatterlist *dst;
-+	struct dpaa2_sg_entry sgt[0];
-+};
-+
-+/*
-+ * skcipher_edesc - s/w-extended skcipher descriptor
-+ * @src_nents: number of segments in input scatterlist
-+ * @dst_nents: number of segments in output scatterlist
-+ * @iv_dma: dma address of iv for checking continuity and link table
-+ * @qm_sg_bytes: length of dma mapped qm_sg space
-+ * @qm_sg_dma: I/O virtual address of h/w link table
-+ * @sgt: the h/w link table, followed by IV
-+ */
-+struct skcipher_edesc {
-+	int src_nents;
-+	int dst_nents;
-+	dma_addr_t iv_dma;
-+	int qm_sg_bytes;
-+	dma_addr_t qm_sg_dma;
-+	struct dpaa2_sg_entry sgt[0];
-+};
-+
-+/*
-+ * ahash_edesc - s/w-extended ahash descriptor
-+ * @dst_dma: I/O virtual address of req->result
-+ * @qm_sg_dma: I/O virtual address of h/w link table
-+ * @src_nents: number of segments in input scatterlist
-+ * @qm_sg_bytes: length of dma mapped qm_sg space
-+ * @sgt: pointer to h/w link table
-+ */
-+struct ahash_edesc {
-+	dma_addr_t dst_dma;
-+	dma_addr_t qm_sg_dma;
-+	int src_nents;
-+	int qm_sg_bytes;
-+	struct dpaa2_sg_entry sgt[0];
-+};
-+
-+/**
-+ * caam_flc - Flow Context (FLC)
-+ * @flc: Flow Context options
-+ * @sh_desc: Shared Descriptor
-+ */
-+struct caam_flc {
-+	u32 flc[16];
-+	u32 sh_desc[MAX_SDLEN];
-+} ____cacheline_aligned;
-+
-+enum optype {
-+	ENCRYPT = 0,
-+	DECRYPT,
-+	NUM_OP
-+};
-+
-+/**
-+ * caam_request - the request structure the driver application should fill while
-+ *                submitting a job to driver.
-+ * @fd_flt: Frame list table defining input and output
-+ *          fd_flt[0] - FLE pointing to output buffer
-+ *          fd_flt[1] - FLE pointing to input buffer
-+ * @fd_flt_dma: DMA address for the frame list table
-+ * @flc: Flow Context
-+ * @flc_dma: I/O virtual address of Flow Context
-+ * @cbk: Callback function to invoke when job is completed
-+ * @ctx: arbit context attached with request by the application
-+ * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
-+ */
-+struct caam_request {
-+	struct dpaa2_fl_entry fd_flt[2];
-+	dma_addr_t fd_flt_dma;
-+	struct caam_flc *flc;
-+	dma_addr_t flc_dma;
-+	void (*cbk)(void *ctx, u32 err);
-+	void *ctx;
-+	void *edesc;
-+};
-+
-+/**
-+ * dpaa2_caam_enqueue() - enqueue a crypto request
-+ * @dev: device associated with the DPSECI object
-+ * @req: pointer to caam_request
-+ */
-+int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
-+
-+#endif	/* _CAAMALG_QI2_H_ */
---- a/drivers/crypto/caam/caamhash.c
-+++ b/drivers/crypto/caam/caamhash.c
-@@ -62,6 +62,7 @@
- #include "error.h"
- #include "sg_sw_sec4.h"
- #include "key_gen.h"
-+#include "caamhash_desc.h"
- 
- #define CAAM_CRA_PRIORITY		3000
- 
-@@ -71,14 +72,6 @@
- #define CAAM_MAX_HASH_BLOCK_SIZE	SHA512_BLOCK_SIZE
- #define CAAM_MAX_HASH_DIGEST_SIZE	SHA512_DIGEST_SIZE
- 
--/* length of descriptors text */
--#define DESC_AHASH_BASE			(3 * CAAM_CMD_SZ)
--#define DESC_AHASH_UPDATE_LEN		(6 * CAAM_CMD_SZ)
--#define DESC_AHASH_UPDATE_FIRST_LEN	(DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
--#define DESC_AHASH_FINAL_LEN		(DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
--#define DESC_AHASH_FINUP_LEN		(DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
--#define DESC_AHASH_DIGEST_LEN		(DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
--
- #define DESC_HASH_MAX_USED_BYTES	(DESC_AHASH_FINAL_LEN + \
- 					 CAAM_MAX_HASH_KEY_SIZE)
- #define DESC_HASH_MAX_USED_LEN		(DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ)
-@@ -107,6 +100,7 @@ struct caam_hash_ctx {
- 	dma_addr_t sh_desc_update_first_dma;
- 	dma_addr_t sh_desc_fin_dma;
- 	dma_addr_t sh_desc_digest_dma;
-+	enum dma_data_direction dir;
- 	struct device *jrdev;
- 	u8 key[CAAM_MAX_HASH_KEY_SIZE];
- 	int ctx_len;
-@@ -218,7 +212,7 @@ static inline int buf_map_to_sec4_sg(str
- }
- 
- /* Map state->caam_ctx, and add it to link table */
--static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
-+static inline int ctx_map_to_sec4_sg(struct device *jrdev,
- 				     struct caam_hash_state *state, int ctx_len,
- 				     struct sec4_sg_entry *sec4_sg, u32 flag)
- {
-@@ -234,68 +228,22 @@ static inline int ctx_map_to_sec4_sg(u32
- 	return 0;
- }
- 
--/*
-- * For ahash update, final and finup (import_ctx = true)
-- *     import context, read and write to seqout
-- * For ahash firsts and digest (import_ctx = false)
-- *     read and write to seqout
-- */
--static inline void ahash_gen_sh_desc(u32 *desc, u32 state, int digestsize,
--				     struct caam_hash_ctx *ctx, bool import_ctx)
--{
--	u32 op = ctx->adata.algtype;
--	u32 *skip_key_load;
--
--	init_sh_desc(desc, HDR_SHARE_SERIAL);
--
--	/* Append key if it has been set; ahash update excluded */
--	if ((state != OP_ALG_AS_UPDATE) && (ctx->adata.keylen)) {
--		/* Skip key loading if already shared */
--		skip_key_load = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
--					    JUMP_COND_SHRD);
--
--		append_key_as_imm(desc, ctx->key, ctx->adata.keylen_pad,
--				  ctx->adata.keylen, CLASS_2 |
--				  KEY_DEST_MDHA_SPLIT | KEY_ENC);
--
--		set_jump_tgt_here(desc, skip_key_load);
--
--		op |= OP_ALG_AAI_HMAC_PRECOMP;
--	}
--
--	/* If needed, import context from software */
--	if (import_ctx)
--		append_seq_load(desc, ctx->ctx_len, LDST_CLASS_2_CCB |
--				LDST_SRCDST_BYTE_CONTEXT);
--
--	/* Class 2 operation */
--	append_operation(desc, op | state | OP_ALG_ENCRYPT);
--
--	/*
--	 * Load from buf and/or src and write to req->result or state->context
--	 * Calculate remaining bytes to read
--	 */
--	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
--	/* Read remaining bytes */
--	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 |
--			     FIFOLD_TYPE_MSG | KEY_VLF);
--	/* Store class2 context bytes */
--	append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
--			 LDST_SRCDST_BYTE_CONTEXT);
--}
--
- static int ahash_set_sh_desc(struct crypto_ahash *ahash)
- {
- 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
- 	int digestsize = crypto_ahash_digestsize(ahash);
- 	struct device *jrdev = ctx->jrdev;
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
- 	u32 *desc;
- 
-+	ctx->adata.key_virt = ctx->key;
-+
- 	/* ahash_update shared descriptor */
- 	desc = ctx->sh_desc_update;
--	ahash_gen_sh_desc(desc, OP_ALG_AS_UPDATE, ctx->ctx_len, ctx, true);
-+	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_UPDATE, ctx->ctx_len,
-+			  ctx->ctx_len, true, ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_update_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- #ifdef DEBUG
- 	print_hex_dump(KERN_ERR,
- 		       "ahash update shdesc@"__stringify(__LINE__)": ",
-@@ -304,9 +252,10 @@ static int ahash_set_sh_desc(struct cryp
- 
- 	/* ahash_update_first shared descriptor */
- 	desc = ctx->sh_desc_update_first;
--	ahash_gen_sh_desc(desc, OP_ALG_AS_INIT, ctx->ctx_len, ctx, false);
-+	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len,
-+			  ctx->ctx_len, false, ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- #ifdef DEBUG
- 	print_hex_dump(KERN_ERR,
- 		       "ahash update first shdesc@"__stringify(__LINE__)": ",
-@@ -315,9 +264,10 @@ static int ahash_set_sh_desc(struct cryp
- 
- 	/* ahash_final shared descriptor */
- 	desc = ctx->sh_desc_fin;
--	ahash_gen_sh_desc(desc, OP_ALG_AS_FINALIZE, digestsize, ctx, true);
-+	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, digestsize,
-+			  ctx->ctx_len, true, ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- #ifdef DEBUG
- 	print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ",
- 		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
-@@ -326,9 +276,10 @@ static int ahash_set_sh_desc(struct cryp
- 
- 	/* ahash_digest shared descriptor */
- 	desc = ctx->sh_desc_digest;
--	ahash_gen_sh_desc(desc, OP_ALG_AS_INITFINAL, digestsize, ctx, false);
-+	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, digestsize,
-+			  ctx->ctx_len, false, ctrlpriv->era);
- 	dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
--				   desc_bytes(desc), DMA_TO_DEVICE);
-+				   desc_bytes(desc), ctx->dir);
- #ifdef DEBUG
- 	print_hex_dump(KERN_ERR,
- 		       "ahash digest shdesc@"__stringify(__LINE__)": ",
-@@ -421,6 +372,7 @@ static int ahash_setkey(struct crypto_ah
- 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
- 	int blocksize = crypto_tfm_alg_blocksize(&ahash->base);
- 	int digestsize = crypto_ahash_digestsize(ahash);
-+	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
- 	int ret;
- 	u8 *hashed_key = NULL;
- 
-@@ -441,16 +393,26 @@ static int ahash_setkey(struct crypto_ah
- 		key = hashed_key;
- 	}
- 
--	ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, key, keylen,
--			    CAAM_MAX_HASH_KEY_SIZE);
--	if (ret)
--		goto bad_free_key;
-+	/*
-+	 * If DKP is supported, use it in the shared descriptor to generate
-+	 * the split key.
-+	 */
-+	if (ctrlpriv->era >= 6) {
-+		ctx->adata.key_inline = true;
-+		ctx->adata.keylen = keylen;
-+		ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
-+						      OP_ALG_ALGSEL_MASK);
- 
--#ifdef DEBUG
--	print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
--		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
--		       ctx->adata.keylen_pad, 1);
--#endif
-+		if (ctx->adata.keylen_pad > CAAM_MAX_HASH_KEY_SIZE)
-+			goto bad_free_key;
-+
-+		memcpy(ctx->key, key, keylen);
-+	} else {
-+		ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, key,
-+				    keylen, CAAM_MAX_HASH_KEY_SIZE);
-+		if (ret)
-+			goto bad_free_key;
-+	}
- 
- 	kfree(hashed_key);
- 	return ahash_set_sh_desc(ahash);
-@@ -773,7 +735,7 @@ static int ahash_update_ctx(struct ahash
- 		edesc->src_nents = src_nents;
- 		edesc->sec4_sg_bytes = sec4_sg_bytes;
- 
--		ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
-+		ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
- 					 edesc->sec4_sg, DMA_BIDIRECTIONAL);
- 		if (ret)
- 			goto unmap_ctx;
-@@ -871,9 +833,8 @@ static int ahash_final_ctx(struct ahash_
- 	desc = edesc->hw_desc;
- 
- 	edesc->sec4_sg_bytes = sec4_sg_bytes;
--	edesc->src_nents = 0;
- 
--	ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
-+	ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
- 				 edesc->sec4_sg, DMA_TO_DEVICE);
- 	if (ret)
- 		goto unmap_ctx;
-@@ -967,7 +928,7 @@ static int ahash_finup_ctx(struct ahash_
- 
- 	edesc->src_nents = src_nents;
- 
--	ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
-+	ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
- 				 edesc->sec4_sg, DMA_TO_DEVICE);
- 	if (ret)
- 		goto unmap_ctx;
-@@ -1123,7 +1084,6 @@ static int ahash_final_no_ctx(struct aha
- 		dev_err(jrdev, "unable to map dst\n");
- 		goto unmap;
- 	}
--	edesc->src_nents = 0;
- 
- #ifdef DEBUG
- 	print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
-@@ -1205,7 +1165,6 @@ static int ahash_update_no_ctx(struct ah
- 
- 		edesc->src_nents = src_nents;
- 		edesc->sec4_sg_bytes = sec4_sg_bytes;
--		edesc->dst_dma = 0;
- 
- 		ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, state);
- 		if (ret)
-@@ -1417,7 +1376,6 @@ static int ahash_update_first(struct aha
- 		}
- 
- 		edesc->src_nents = src_nents;
--		edesc->dst_dma = 0;
- 
- 		ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 0, 0,
- 					  to_hash);
-@@ -1719,6 +1677,7 @@ static int caam_hash_cra_init(struct cry
- 					 HASH_MSG_LEN + 64,
- 					 HASH_MSG_LEN + SHA512_DIGEST_SIZE };
- 	dma_addr_t dma_addr;
-+	struct caam_drv_private *priv;
- 
- 	/*
- 	 * Get a Job ring from Job Ring driver to ensure in-order
-@@ -1730,10 +1689,13 @@ static int caam_hash_cra_init(struct cry
- 		return PTR_ERR(ctx->jrdev);
- 	}
- 
-+	priv = dev_get_drvdata(ctx->jrdev->parent);
-+	ctx->dir = priv->era >= 6 ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
-+
- 	dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_update,
- 					offsetof(struct caam_hash_ctx,
- 						 sh_desc_update_dma),
--					DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
-+					ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
- 	if (dma_mapping_error(ctx->jrdev, dma_addr)) {
- 		dev_err(ctx->jrdev, "unable to map shared descriptors\n");
- 		caam_jr_free(ctx->jrdev);
-@@ -1768,7 +1730,7 @@ static void caam_hash_cra_exit(struct cr
- 	dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_update_dma,
- 			       offsetof(struct caam_hash_ctx,
- 					sh_desc_update_dma),
--			       DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
-+			       ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
- 	caam_jr_free(ctx->jrdev);
- }
- 
---- /dev/null
-+++ b/drivers/crypto/caam/caamhash_desc.c
-@@ -0,0 +1,108 @@
-+/*
-+ * Shared descriptors for ahash algorithms
-+ *
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the names of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include "compat.h"
-+#include "desc_constr.h"
-+#include "caamhash_desc.h"
-+
-+/**
-+ * cnstr_shdsc_ahash - ahash shared descriptor
-+ * @desc: pointer to buffer used for descriptor construction
-+ * @adata: pointer to authentication transform definitions.
-+ *         A split key is required for SEC Era < 6; the size of the split key
-+ *         is specified in this case.
-+ *         Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224,
-+ *         SHA256, SHA384, SHA512}.
-+ * @state: algorithm state OP_ALG_AS_{INIT, FINALIZE, INITFINALIZE, UPDATE}
-+ * @digestsize: algorithm's digest size
-+ * @ctx_len: size of Context Register
-+ * @import_ctx: true if previous Context Register needs to be restored
-+ *              must be true for ahash update and final
-+ *              must be false for for ahash first and digest
-+ * @era: SEC Era
-+ */
-+void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state,
-+		       int digestsize, int ctx_len, bool import_ctx, int era)
-+{
-+	u32 op = adata->algtype;
-+
-+	init_sh_desc(desc, HDR_SHARE_SERIAL);
-+
-+	/* Append key if it has been set; ahash update excluded */
-+	if (state != OP_ALG_AS_UPDATE && adata->keylen) {
-+		u32 *skip_key_load;
-+
-+		/* Skip key loading if already shared */
-+		skip_key_load = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
-+					    JUMP_COND_SHRD);
-+
-+		if (era < 6)
-+			append_key_as_imm(desc, adata->key_virt,
-+					  adata->keylen_pad,
-+					  adata->keylen, CLASS_2 |
-+					  KEY_DEST_MDHA_SPLIT | KEY_ENC);
-+		else
-+			append_proto_dkp(desc, adata);
-+
-+		set_jump_tgt_here(desc, skip_key_load);
-+
-+		op |= OP_ALG_AAI_HMAC_PRECOMP;
-+	}
-+
-+	/* If needed, import context from software */
-+	if (import_ctx)
-+		append_seq_load(desc, ctx_len, LDST_CLASS_2_CCB |
-+				LDST_SRCDST_BYTE_CONTEXT);
-+
-+	/* Class 2 operation */
-+	append_operation(desc, op | state | OP_ALG_ENCRYPT);
-+
-+	/*
-+	 * Load from buf and/or src and write to req->result or state->context
-+	 * Calculate remaining bytes to read
-+	 */
-+	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
-+	/* Read remaining bytes */
-+	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 |
-+			     FIFOLD_TYPE_MSG | KEY_VLF);
-+	/* Store class2 context bytes */
-+	append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
-+			 LDST_SRCDST_BYTE_CONTEXT);
-+}
-+EXPORT_SYMBOL(cnstr_shdsc_ahash);
-+
-+MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("FSL CAAM ahash descriptors support");
-+MODULE_AUTHOR("NXP Semiconductors");
---- /dev/null
-+++ b/drivers/crypto/caam/caamhash_desc.h
-@@ -0,0 +1,49 @@
-+/*
-+ * Shared descriptors for ahash algorithms
-+ *
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the names of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef _CAAMHASH_DESC_H_
-+#define _CAAMHASH_DESC_H_
-+
-+/* length of descriptors text */
-+#define DESC_AHASH_BASE			(3 * CAAM_CMD_SZ)
-+#define DESC_AHASH_UPDATE_LEN		(6 * CAAM_CMD_SZ)
-+#define DESC_AHASH_UPDATE_FIRST_LEN	(DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
-+#define DESC_AHASH_FINAL_LEN		(DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
-+#define DESC_AHASH_DIGEST_LEN		(DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
-+
-+void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state,
-+		       int digestsize, int ctx_len, bool import_ctx, int era);
-+
-+#endif /* _CAAMHASH_DESC_H_ */
---- a/drivers/crypto/caam/compat.h
-+++ b/drivers/crypto/caam/compat.h
-@@ -17,6 +17,7 @@
- #include <linux/of_platform.h>
- #include <linux/dma-mapping.h>
- #include <linux/io.h>
-+#include <linux/iommu.h>
- #include <linux/spinlock.h>
- #include <linux/rtnetlink.h>
- #include <linux/in.h>
-@@ -38,6 +39,7 @@
- #include <crypto/authenc.h>
- #include <crypto/akcipher.h>
- #include <crypto/scatterwalk.h>
-+#include <crypto/skcipher.h>
- #include <crypto/internal/skcipher.h>
- #include <crypto/internal/hash.h>
- #include <crypto/internal/rsa.h>
---- a/drivers/crypto/caam/ctrl.c
-+++ b/drivers/crypto/caam/ctrl.c
-@@ -27,6 +27,8 @@ EXPORT_SYMBOL(caam_imx);
- #include "qi.h"
- #endif
- 
-+static struct platform_device *caam_dma_dev;
-+
- /*
-  * i.MX targets tend to have clock control subsystems that can
-  * enable/disable clocking to our device.
-@@ -332,6 +334,9 @@ static int caam_remove(struct platform_d
- 	debugfs_remove_recursive(ctrlpriv->dfs_root);
- #endif
- 
-+	if (caam_dma_dev)
-+		platform_device_unregister(caam_dma_dev);
-+
- 	/* Unmap controller region */
- 	iounmap(ctrl);
- 
-@@ -433,6 +438,10 @@ static int caam_probe(struct platform_de
- 		{.family = "Freescale i.MX"},
- 		{},
- 	};
-+	static struct platform_device_info caam_dma_pdev_info = {
-+		.name = "caam-dma",
-+		.id = PLATFORM_DEVID_NONE
-+	};
- 	struct device *dev;
- 	struct device_node *nprop, *np;
- 	struct caam_ctrl __iomem *ctrl;
-@@ -615,6 +624,8 @@ static int caam_probe(struct platform_de
- 		goto iounmap_ctrl;
- 	}
- 
-+	ctrlpriv->era = caam_get_era();
-+
- 	ret = of_platform_populate(nprop, caam_match, NULL, dev);
- 	if (ret) {
- 		dev_err(dev, "JR platform devices creation error\n");
-@@ -671,6 +682,16 @@ static int caam_probe(struct platform_de
- 		goto caam_remove;
- 	}
- 
-+	caam_dma_pdev_info.parent = dev;
-+	caam_dma_pdev_info.dma_mask = dma_get_mask(dev);
-+	caam_dma_dev = platform_device_register_full(&caam_dma_pdev_info);
-+	if (IS_ERR(caam_dma_dev)) {
-+		dev_err(dev, "Unable to create and register caam-dma dev\n");
-+		caam_dma_dev = 0;
-+	} else {
-+		set_dma_ops(&caam_dma_dev->dev, get_dma_ops(dev));
-+	}
-+
- 	cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
- 
- 	/*
-@@ -746,7 +767,7 @@ static int caam_probe(struct platform_de
- 
- 	/* Report "alive" for developer to see */
- 	dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
--		 caam_get_era());
-+		 ctrlpriv->era);
- 	dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n",
- 		 ctrlpriv->total_jobrs, ctrlpriv->qi_present,
- 		 caam_dpaa2 ? "yes" : "no");
---- a/drivers/crypto/caam/desc.h
-+++ b/drivers/crypto/caam/desc.h
-@@ -42,6 +42,7 @@
- #define CMD_SEQ_LOAD		(0x03 << CMD_SHIFT)
- #define CMD_FIFO_LOAD		(0x04 << CMD_SHIFT)
- #define CMD_SEQ_FIFO_LOAD	(0x05 << CMD_SHIFT)
-+#define CMD_MOVEB		(0x07 << CMD_SHIFT)
- #define CMD_STORE		(0x0a << CMD_SHIFT)
- #define CMD_SEQ_STORE		(0x0b << CMD_SHIFT)
- #define CMD_FIFO_STORE		(0x0c << CMD_SHIFT)
-@@ -355,6 +356,7 @@
- #define FIFOLD_TYPE_PK_N	(0x08 << FIFOLD_TYPE_SHIFT)
- #define FIFOLD_TYPE_PK_A	(0x0c << FIFOLD_TYPE_SHIFT)
- #define FIFOLD_TYPE_PK_B	(0x0d << FIFOLD_TYPE_SHIFT)
-+#define FIFOLD_TYPE_IFIFO	(0x0f << FIFOLD_TYPE_SHIFT)
- 
- /* Other types. Need to OR in last/flush bits as desired */
- #define FIFOLD_TYPE_MSG_MASK	(0x38 << FIFOLD_TYPE_SHIFT)
-@@ -408,6 +410,7 @@
- #define FIFOST_TYPE_MESSAGE_DATA (0x30 << FIFOST_TYPE_SHIFT)
- #define FIFOST_TYPE_RNGSTORE	 (0x34 << FIFOST_TYPE_SHIFT)
- #define FIFOST_TYPE_RNGFIFO	 (0x35 << FIFOST_TYPE_SHIFT)
-+#define FIFOST_TYPE_METADATA	 (0x3e << FIFOST_TYPE_SHIFT)
- #define FIFOST_TYPE_SKIP	 (0x3f << FIFOST_TYPE_SHIFT)
- 
- /*
-@@ -444,6 +447,18 @@
- #define OP_PCLID_DSAVERIFY	(0x16 << OP_PCLID_SHIFT)
- #define OP_PCLID_RSAENC_PUBKEY  (0x18 << OP_PCLID_SHIFT)
- #define OP_PCLID_RSADEC_PRVKEY  (0x19 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_MD5	(0x20 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_SHA1	(0x21 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_SHA224	(0x22 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_SHA256	(0x23 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_SHA384	(0x24 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_SHA512	(0x25 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_RIF_MD5	(0x60 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_RIF_SHA1	(0x61 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_RIF_SHA224	(0x62 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_RIF_SHA256	(0x63 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_RIF_SHA384	(0x64 << OP_PCLID_SHIFT)
-+#define OP_PCLID_DKP_RIF_SHA512	(0x65 << OP_PCLID_SHIFT)
- 
- /* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL/ENCAP_PROTOCOL */
- #define OP_PCLID_IPSEC		(0x01 << OP_PCLID_SHIFT)
-@@ -1093,6 +1108,22 @@
- /* MacSec protinfos */
- #define OP_PCL_MACSEC				 0x0001
- 
-+/* Derived Key Protocol (DKP) Protinfo */
-+#define OP_PCL_DKP_SRC_SHIFT	14
-+#define OP_PCL_DKP_SRC_MASK	(3 << OP_PCL_DKP_SRC_SHIFT)
-+#define OP_PCL_DKP_SRC_IMM	(0 << OP_PCL_DKP_SRC_SHIFT)
-+#define OP_PCL_DKP_SRC_SEQ	(1 << OP_PCL_DKP_SRC_SHIFT)
-+#define OP_PCL_DKP_SRC_PTR	(2 << OP_PCL_DKP_SRC_SHIFT)
-+#define OP_PCL_DKP_SRC_SGF	(3 << OP_PCL_DKP_SRC_SHIFT)
-+#define OP_PCL_DKP_DST_SHIFT	12
-+#define OP_PCL_DKP_DST_MASK	(3 << OP_PCL_DKP_DST_SHIFT)
-+#define OP_PCL_DKP_DST_IMM	(0 << OP_PCL_DKP_DST_SHIFT)
-+#define OP_PCL_DKP_DST_SEQ	(1 << OP_PCL_DKP_DST_SHIFT)
-+#define OP_PCL_DKP_DST_PTR	(2 << OP_PCL_DKP_DST_SHIFT)
-+#define OP_PCL_DKP_DST_SGF	(3 << OP_PCL_DKP_DST_SHIFT)
-+#define OP_PCL_DKP_KEY_SHIFT	0
-+#define OP_PCL_DKP_KEY_MASK	(0xfff << OP_PCL_DKP_KEY_SHIFT)
-+
- /* PKI unidirectional protocol protinfo bits */
- #define OP_PCL_PKPROT_TEST			 0x0008
- #define OP_PCL_PKPROT_DECRYPT			 0x0004
-@@ -1440,10 +1471,11 @@
- #define MATH_SRC1_REG2		(0x02 << MATH_SRC1_SHIFT)
- #define MATH_SRC1_REG3		(0x03 << MATH_SRC1_SHIFT)
- #define MATH_SRC1_IMM		(0x04 << MATH_SRC1_SHIFT)
--#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC0_SHIFT)
-+#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC1_SHIFT)
- #define MATH_SRC1_INFIFO	(0x0a << MATH_SRC1_SHIFT)
- #define MATH_SRC1_OUTFIFO	(0x0b << MATH_SRC1_SHIFT)
- #define MATH_SRC1_ONE		(0x0c << MATH_SRC1_SHIFT)
-+#define MATH_SRC1_ZERO		(0x0f << MATH_SRC1_SHIFT)
- 
- /* Destination selectors */
- #define MATH_DEST_SHIFT		8
-@@ -1452,6 +1484,7 @@
- #define MATH_DEST_REG1		(0x01 << MATH_DEST_SHIFT)
- #define MATH_DEST_REG2		(0x02 << MATH_DEST_SHIFT)
- #define MATH_DEST_REG3		(0x03 << MATH_DEST_SHIFT)
-+#define MATH_DEST_DPOVRD	(0x07 << MATH_DEST_SHIFT)
- #define MATH_DEST_SEQINLEN	(0x08 << MATH_DEST_SHIFT)
- #define MATH_DEST_SEQOUTLEN	(0x09 << MATH_DEST_SHIFT)
- #define MATH_DEST_VARSEQINLEN	(0x0a << MATH_DEST_SHIFT)
-@@ -1624,4 +1657,31 @@
- /* Frame Descriptor Command for Replacement Job Descriptor */
- #define FD_CMD_REPLACE_JOB_DESC				0x20000000
- 
-+/* CHA Control Register bits */
-+#define CCTRL_RESET_CHA_ALL          0x1
-+#define CCTRL_RESET_CHA_AESA         0x2
-+#define CCTRL_RESET_CHA_DESA         0x4
-+#define CCTRL_RESET_CHA_AFHA         0x8
-+#define CCTRL_RESET_CHA_KFHA         0x10
-+#define CCTRL_RESET_CHA_SF8A         0x20
-+#define CCTRL_RESET_CHA_PKHA         0x40
-+#define CCTRL_RESET_CHA_MDHA         0x80
-+#define CCTRL_RESET_CHA_CRCA         0x100
-+#define CCTRL_RESET_CHA_RNG          0x200
-+#define CCTRL_RESET_CHA_SF9A         0x400
-+#define CCTRL_RESET_CHA_ZUCE         0x800
-+#define CCTRL_RESET_CHA_ZUCA         0x1000
-+#define CCTRL_UNLOAD_PK_A0           0x10000
-+#define CCTRL_UNLOAD_PK_A1           0x20000
-+#define CCTRL_UNLOAD_PK_A2           0x40000
-+#define CCTRL_UNLOAD_PK_A3           0x80000
-+#define CCTRL_UNLOAD_PK_B0           0x100000
-+#define CCTRL_UNLOAD_PK_B1           0x200000
-+#define CCTRL_UNLOAD_PK_B2           0x400000
-+#define CCTRL_UNLOAD_PK_B3           0x800000
-+#define CCTRL_UNLOAD_PK_N            0x1000000
-+#define CCTRL_UNLOAD_PK_A            0x4000000
-+#define CCTRL_UNLOAD_PK_B            0x8000000
-+#define CCTRL_UNLOAD_SBOX            0x10000000
-+
- #endif /* DESC_H */
---- a/drivers/crypto/caam/desc_constr.h
-+++ b/drivers/crypto/caam/desc_constr.h
-@@ -109,7 +109,7 @@ static inline void init_job_desc_shared(
- 	append_ptr(desc, ptr);
- }
- 
--static inline void append_data(u32 * const desc, void *data, int len)
-+static inline void append_data(u32 * const desc, const void *data, int len)
- {
- 	u32 *offset = desc_end(desc);
- 
-@@ -172,7 +172,7 @@ static inline void append_cmd_ptr_extlen
- 	append_cmd(desc, len);
- }
- 
--static inline void append_cmd_data(u32 * const desc, void *data, int len,
-+static inline void append_cmd_data(u32 * const desc, const void *data, int len,
- 				   u32 command)
- {
- 	append_cmd(desc, command | IMMEDIATE | len);
-@@ -189,6 +189,7 @@ static inline u32 *append_##cmd(u32 * co
- }
- APPEND_CMD_RET(jump, JUMP)
- APPEND_CMD_RET(move, MOVE)
-+APPEND_CMD_RET(moveb, MOVEB)
- 
- static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd)
- {
-@@ -271,7 +272,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
- APPEND_SEQ_PTR_INTLEN(out, OUT)
- 
- #define APPEND_CMD_PTR_TO_IMM(cmd, op) \
--static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
-+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
- 					 unsigned int len, u32 options) \
- { \
- 	PRINT_POS; \
-@@ -312,7 +313,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_
-  * from length of immediate data provided, e.g., split keys
-  */
- #define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
--static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
-+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
- 					 unsigned int data_len, \
- 					 unsigned int len, u32 options) \
- { \
-@@ -452,7 +453,7 @@ struct alginfo {
- 	unsigned int keylen_pad;
- 	union {
- 		dma_addr_t key_dma;
--		void *key_virt;
-+		const void *key_virt;
- 	};
- 	bool key_inline;
- };
-@@ -496,4 +497,45 @@ static inline int desc_inline_query(unsi
- 	return (rem_bytes >= 0) ? 0 : -1;
- }
- 
-+/**
-+ * append_proto_dkp - Derived Key Protocol (DKP): key -> split key
-+ * @desc: pointer to buffer used for descriptor construction
-+ * @adata: pointer to authentication transform definitions.
-+ *         keylen should be the length of initial key, while keylen_pad
-+ *         the length of the derived (split) key.
-+ *         Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224,
-+ *         SHA256, SHA384, SHA512}.
-+ */
-+static inline void append_proto_dkp(u32 * const desc, struct alginfo *adata)
-+{
-+	u32 protid;
-+
-+	/*
-+	 * Quick & dirty translation from OP_ALG_ALGSEL_{MD5, SHA*}
-+	 * to OP_PCLID_DKP_{MD5, SHA*}
-+	 */
-+	protid = (adata->algtype & OP_ALG_ALGSEL_SUBMASK) |
-+		 (0x20 << OP_ALG_ALGSEL_SHIFT);
-+
-+	if (adata->key_inline) {
-+		int words;
-+
-+		append_operation(desc, OP_TYPE_UNI_PROTOCOL | protid |
-+				 OP_PCL_DKP_SRC_IMM | OP_PCL_DKP_DST_IMM |
-+				 adata->keylen);
-+		append_data(desc, adata->key_virt, adata->keylen);
-+
-+		/* Reserve space in descriptor buffer for the derived key */
-+		words = (ALIGN(adata->keylen_pad, CAAM_CMD_SZ) -
-+			 ALIGN(adata->keylen, CAAM_CMD_SZ)) / CAAM_CMD_SZ;
-+		if (words)
-+			(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + words);
-+	} else {
-+		append_operation(desc, OP_TYPE_UNI_PROTOCOL | protid |
-+				 OP_PCL_DKP_SRC_PTR | OP_PCL_DKP_DST_PTR |
-+				 adata->keylen);
-+		append_ptr(desc, adata->key_dma);
-+	}
-+}
-+
- #endif /* DESC_CONSTR_H */
---- /dev/null
-+++ b/drivers/crypto/caam/dpseci.c
-@@ -0,0 +1,865 @@
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the names of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/fsl/mc.h>
-+#include "../../../drivers/staging/fsl-mc/include/dpopr.h"
-+#include "dpseci.h"
-+#include "dpseci_cmd.h"
-+
-+/**
-+ * dpseci_open() - Open a control session for the specified object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @dpseci_id:	DPSECI unique ID
-+ * @token:	Returned token; use in subsequent API calls
-+ *
-+ * This function can be used to open a control session for an already created
-+ * object; an object may have been declared in the DPL or by calling the
-+ * dpseci_create() function.
-+ * This function returns a unique authentication token, associated with the
-+ * specific object ID and the specific MC portal; this token must be used in all
-+ * subsequent commands for this specific object.
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpseci_id,
-+		u16 *token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_open *cmd_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_OPEN,
-+					  cmd_flags,
-+					  0);
-+	cmd_params = (struct dpseci_cmd_open *)cmd.params;
-+	cmd_params->dpseci_id = cpu_to_le32(dpseci_id);
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	*token = mc_cmd_hdr_read_token(&cmd);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_close() - Close the control session of the object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ *
-+ * After this function is called, no further operations are allowed on the
-+ * object without opening a new control session.
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLOSE,
-+					  cmd_flags,
-+					  token);
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_create() - Create the DPSECI object
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @dprc_token:	Parent container token; '0' for default container
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @cfg:	Configuration structure
-+ * @obj_id:	returned object id
-+ *
-+ * Create the DPSECI object, allocate required resources and perform required
-+ * initialization.
-+ *
-+ * The object can be created either by declaring it in the DPL file, or by
-+ * calling this function.
-+ *
-+ * The function accepts an authentication token of a parent container that this
-+ * object should be assigned to. The token can be '0' so the object will be
-+ * assigned to the default container.
-+ * The newly created object can be opened with the returned object id and using
-+ * the container's associated tokens and MC portals.
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
-+		  const struct dpseci_cfg *cfg, u32 *obj_id)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_create *cmd_params;
-+	int i, err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CREATE,
-+					  cmd_flags,
-+					  dprc_token);
-+	cmd_params = (struct dpseci_cmd_create *)cmd.params;
-+	for (i = 0; i < 8; i++)
-+		cmd_params->priorities[i] = cfg->priorities[i];
-+	for (i = 0; i < 8; i++)
-+		cmd_params->priorities2[i] = cfg->priorities[8 + i];
-+	cmd_params->num_tx_queues = cfg->num_tx_queues;
-+	cmd_params->num_rx_queues = cfg->num_rx_queues;
-+	cmd_params->options = cpu_to_le32(cfg->options);
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	*obj_id = mc_cmd_read_object_id(&cmd);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_destroy() - Destroy the DPSECI object and release all its resources
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @dprc_token: Parent container token; '0' for default container
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @object_id:	The object id; it must be a valid id within the container that
-+ *		created this object
-+ *
-+ * The function accepts the authentication token of the parent container that
-+ * created the object (not the one that currently owns the object). The object
-+ * is searched within parent using the provided 'object_id'.
-+ * All tokens to the object must be closed before calling destroy.
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
-+		   u32 object_id)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_destroy *cmd_params;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DESTROY,
-+					  cmd_flags,
-+					  dprc_token);
-+	cmd_params = (struct dpseci_cmd_destroy *)cmd.params;
-+	cmd_params->object_id = cpu_to_le32(object_id);
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_enable() - Enable the DPSECI, allow sending and receiving frames
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_disable() - Disable the DPSECI, stop sending and receiving frames
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DISABLE,
-+					  cmd_flags,
-+					  token);
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_is_enabled() - Check if the DPSECI is enabled.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @en:		Returns '1' if object is enabled; '0' otherwise
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+		      int *en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_rsp_is_enabled *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_IS_ENABLED,
-+					  cmd_flags,
-+					  token);
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_rsp_is_enabled *)cmd.params;
-+	*en = dpseci_get_field(rsp_params->is_enabled, ENABLE);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_reset() - Reset the DPSECI, returns the object to initial state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_RESET,
-+					  cmd_flags,
-+					  token);
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_get_irq_enable() - Get overall interrupt state
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Returned Interrupt state - enable = 1, disable = 0
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			  u8 irq_index, u8 *en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_irq_enable *cmd_params;
-+	struct dpseci_rsp_get_irq_enable *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_rsp_get_irq_enable *)cmd.params;
-+	*en = rsp_params->enable_state;
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_set_irq_enable() - Set overall interrupt state.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @irq_index:	The interrupt index to configure
-+ * @en:		Interrupt state - enable = 1, disable = 0
-+ *
-+ * Allows GPP software to control when interrupts are generated.
-+ * Each interrupt can have up to 32 causes. The enable/disable control's the
-+ * overall interrupt state. If the interrupt is disabled no causes will cause
-+ * an interrupt.
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			  u8 irq_index, u8 en)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_irq_enable *cmd_params;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_ENABLE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+	cmd_params->enable_state = en;
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_get_irq_mask() - Get interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	Returned event mask to trigger interrupt
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently.
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 irq_index, u32 *mask)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_irq_mask *cmd_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params;
-+	cmd_params->irq_index = irq_index;
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	*mask = le32_to_cpu(cmd_params->mask);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_set_irq_mask() - Set interrupt mask.
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @irq_index:	The interrupt index to configure
-+ * @mask:	event mask to trigger interrupt;
-+ *		each bit:
-+ *			0 = ignore event
-+ *			1 = consider event for asserting IRQ
-+ *
-+ * Every interrupt can have up to 32 causes and the interrupt model supports
-+ * masking/unmasking each cause independently
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 irq_index, u32 mask)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_irq_mask *cmd_params;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_MASK,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params;
-+	cmd_params->mask = cpu_to_le32(mask);
-+	cmd_params->irq_index = irq_index;
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_get_irq_status() - Get the current status of any pending interrupts
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	Returned interrupts status - one bit per cause:
-+ *			0 = no interrupt pending
-+ *			1 = interrupt pending
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			  u8 irq_index, u32 *status)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_irq_status *cmd_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(*status);
-+	cmd_params->irq_index = irq_index;
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	*status = le32_to_cpu(cmd_params->status);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_clear_irq_status() - Clear a pending interrupt's status
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @irq_index:	The interrupt index to configure
-+ * @status:	bits to clear (W1C) - one bit per cause:
-+ *			0 = don't change
-+ *			1 = clear status bit
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			    u8 irq_index, u32 status)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_irq_status *cmd_params;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLEAR_IRQ_STATUS,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_irq_status *)cmd.params;
-+	cmd_params->status = cpu_to_le32(status);
-+	cmd_params->irq_index = irq_index;
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_get_attributes() - Retrieve DPSECI attributes
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @attr:	Returned object's attributes
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			  struct dpseci_attr *attr)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_rsp_get_attributes *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_ATTR,
-+					  cmd_flags,
-+					  token);
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_rsp_get_attributes *)cmd.params;
-+	attr->id = le32_to_cpu(rsp_params->id);
-+	attr->num_tx_queues = rsp_params->num_tx_queues;
-+	attr->num_rx_queues = rsp_params->num_rx_queues;
-+	attr->options = le32_to_cpu(rsp_params->options);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_set_rx_queue() - Set Rx queue configuration
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @queue:	Select the queue relative to number of priorities configured at
-+ *		DPSECI creation; use DPSECI_ALL_QUEUES to configure all
-+ *		Rx queues identically.
-+ * @cfg:	Rx queue configuration
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 queue, const struct dpseci_rx_queue_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_queue *cmd_params;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_RX_QUEUE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_queue *)cmd.params;
-+	cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
-+	cmd_params->priority = cfg->dest_cfg.priority;
-+	cmd_params->queue = queue;
-+	dpseci_set_field(cmd_params->dest_type, DEST_TYPE,
-+			 cfg->dest_cfg.dest_type);
-+	cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx);
-+	cmd_params->options = cpu_to_le32(cfg->options);
-+	dpseci_set_field(cmd_params->order_preservation_en, ORDER_PRESERVATION,
-+			 cfg->order_preservation_en);
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_get_rx_queue() - Retrieve Rx queue attributes
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @queue:	Select the queue relative to number of priorities configured at
-+ *		DPSECI creation
-+ * @attr:	Returned Rx queue attributes
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 queue, struct dpseci_rx_queue_attr *attr)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_queue *cmd_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_RX_QUEUE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_queue *)cmd.params;
-+	cmd_params->queue = queue;
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	attr->dest_cfg.dest_id = le32_to_cpu(cmd_params->dest_id);
-+	attr->dest_cfg.priority = cmd_params->priority;
-+	attr->dest_cfg.dest_type = dpseci_get_field(cmd_params->dest_type,
-+						    DEST_TYPE);
-+	attr->user_ctx = le64_to_cpu(cmd_params->user_ctx);
-+	attr->fqid = le32_to_cpu(cmd_params->fqid);
-+	attr->order_preservation_en =
-+		dpseci_get_field(cmd_params->order_preservation_en,
-+				 ORDER_PRESERVATION);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_get_tx_queue() - Retrieve Tx queue attributes
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @queue:	Select the queue relative to number of priorities configured at
-+ *		DPSECI creation
-+ * @attr:	Returned Tx queue attributes
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 queue, struct dpseci_tx_queue_attr *attr)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_queue *cmd_params;
-+	struct dpseci_rsp_get_tx_queue *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_TX_QUEUE,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_queue *)cmd.params;
-+	cmd_params->queue = queue;
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_rsp_get_tx_queue *)cmd.params;
-+	attr->fqid = le32_to_cpu(rsp_params->fqid);
-+	attr->priority = rsp_params->priority;
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_get_sec_attr() - Retrieve SEC accelerator attributes
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @attr:	Returned SEC attributes
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			struct dpseci_sec_attr *attr)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_rsp_get_sec_attr *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_ATTR,
-+					  cmd_flags,
-+					  token);
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_rsp_get_sec_attr *)cmd.params;
-+	attr->ip_id = le16_to_cpu(rsp_params->ip_id);
-+	attr->major_rev = rsp_params->major_rev;
-+	attr->minor_rev = rsp_params->minor_rev;
-+	attr->era = rsp_params->era;
-+	attr->deco_num = rsp_params->deco_num;
-+	attr->zuc_auth_acc_num = rsp_params->zuc_auth_acc_num;
-+	attr->zuc_enc_acc_num = rsp_params->zuc_enc_acc_num;
-+	attr->snow_f8_acc_num = rsp_params->snow_f8_acc_num;
-+	attr->snow_f9_acc_num = rsp_params->snow_f9_acc_num;
-+	attr->crc_acc_num = rsp_params->crc_acc_num;
-+	attr->pk_acc_num = rsp_params->pk_acc_num;
-+	attr->kasumi_acc_num = rsp_params->kasumi_acc_num;
-+	attr->rng_acc_num = rsp_params->rng_acc_num;
-+	attr->md_acc_num = rsp_params->md_acc_num;
-+	attr->arc4_acc_num = rsp_params->arc4_acc_num;
-+	attr->des_acc_num = rsp_params->des_acc_num;
-+	attr->aes_acc_num = rsp_params->aes_acc_num;
-+	attr->ccha_acc_num = rsp_params->ccha_acc_num;
-+	attr->ptha_acc_num = rsp_params->ptha_acc_num;
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_get_sec_counters() - Retrieve SEC accelerator counters
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @counters:	Returned SEC counters
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			    struct dpseci_sec_counters *counters)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_rsp_get_sec_counters *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_COUNTERS,
-+					  cmd_flags,
-+					  token);
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_rsp_get_sec_counters *)cmd.params;
-+	counters->dequeued_requests =
-+		le64_to_cpu(rsp_params->dequeued_requests);
-+	counters->ob_enc_requests = le64_to_cpu(rsp_params->ob_enc_requests);
-+	counters->ib_dec_requests = le64_to_cpu(rsp_params->ib_dec_requests);
-+	counters->ob_enc_bytes = le64_to_cpu(rsp_params->ob_enc_bytes);
-+	counters->ob_prot_bytes = le64_to_cpu(rsp_params->ob_prot_bytes);
-+	counters->ib_dec_bytes = le64_to_cpu(rsp_params->ib_dec_bytes);
-+	counters->ib_valid_bytes = le64_to_cpu(rsp_params->ib_valid_bytes);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_get_api_version() - Get Data Path SEC Interface API version
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @major_ver:	Major version of data path sec API
-+ * @minor_ver:	Minor version of data path sec API
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
-+			   u16 *major_ver, u16 *minor_ver)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_rsp_get_api_version *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_API_VERSION,
-+					  cmd_flags, 0);
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_rsp_get_api_version *)cmd.params;
-+	*major_ver = le16_to_cpu(rsp_params->major);
-+	*minor_ver = le16_to_cpu(rsp_params->minor);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_set_opr() - Set Order Restoration configuration
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @index:	The queue index
-+ * @options:	Configuration mode options; can be OPR_OPT_CREATE or
-+ *		OPR_OPT_RETIRE
-+ * @cfg:	Configuration options for the OPR
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
-+		   u8 options, struct opr_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_opr *cmd_params;
-+
-+	cmd.header = mc_encode_cmd_header(
-+			DPSECI_CMDID_SET_OPR,
-+			cmd_flags,
-+			token);
-+	cmd_params = (struct dpseci_cmd_opr *)cmd.params;
-+	cmd_params->index = index;
-+	cmd_params->options = options;
-+	cmd_params->oloe = cfg->oloe;
-+	cmd_params->oeane = cfg->oeane;
-+	cmd_params->olws = cfg->olws;
-+	cmd_params->oa = cfg->oa;
-+	cmd_params->oprrws = cfg->oprrws;
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_get_opr() - Retrieve Order Restoration config and query
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @index:	The queue index
-+ * @cfg:	Returned OPR configuration
-+ * @qry:	Returned OPR query
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
-+		   struct opr_cfg *cfg, struct opr_qry *qry)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_opr *cmd_params;
-+	struct dpseci_rsp_get_opr *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_OPR,
-+					  cmd_flags,
-+					  token);
-+	cmd_params = (struct dpseci_cmd_opr *)cmd.params;
-+	cmd_params->index = index;
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_rsp_get_opr *)cmd.params;
-+	qry->rip = dpseci_get_field(rsp_params->flags, OPR_RIP);
-+	qry->enable = dpseci_get_field(rsp_params->flags, OPR_ENABLE);
-+	cfg->oloe = rsp_params->oloe;
-+	cfg->oeane = rsp_params->oeane;
-+	cfg->olws = rsp_params->olws;
-+	cfg->oa = rsp_params->oa;
-+	cfg->oprrws = rsp_params->oprrws;
-+	qry->nesn = le16_to_cpu(rsp_params->nesn);
-+	qry->ndsn = le16_to_cpu(rsp_params->ndsn);
-+	qry->ea_tseq = le16_to_cpu(rsp_params->ea_tseq);
-+	qry->tseq_nlis = dpseci_get_field(rsp_params->tseq_nlis, OPR_TSEQ_NLIS);
-+	qry->ea_hseq = le16_to_cpu(rsp_params->ea_hseq);
-+	qry->hseq_nlis = dpseci_get_field(rsp_params->hseq_nlis, OPR_HSEQ_NLIS);
-+	qry->ea_hptr = le16_to_cpu(rsp_params->ea_hptr);
-+	qry->ea_tptr = le16_to_cpu(rsp_params->ea_tptr);
-+	qry->opr_vid = le16_to_cpu(rsp_params->opr_vid);
-+	qry->opr_id = le16_to_cpu(rsp_params->opr_id);
-+
-+	return 0;
-+}
-+
-+/**
-+ * dpseci_set_congestion_notification() - Set congestion group
-+ *	notification configuration
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @cfg:	congestion notification configuration
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_set_congestion_notification(struct fsl_mc_io *mc_io, u32 cmd_flags,
-+	u16 token, const struct dpseci_congestion_notification_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_congestion_notification *cmd_params;
-+
-+	cmd.header = mc_encode_cmd_header(
-+			DPSECI_CMDID_SET_CONGESTION_NOTIFICATION,
-+			cmd_flags,
-+			token);
-+	cmd_params = (struct dpseci_cmd_congestion_notification *)cmd.params;
-+	cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
-+	cmd_params->notification_mode = cpu_to_le16(cfg->notification_mode);
-+	cmd_params->priority = cfg->dest_cfg.priority;
-+	dpseci_set_field(cmd_params->options, CGN_DEST_TYPE,
-+			 cfg->dest_cfg.dest_type);
-+	dpseci_set_field(cmd_params->options, CGN_UNITS, cfg->units);
-+	cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
-+	cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
-+	cmd_params->threshold_entry = cpu_to_le32(cfg->threshold_entry);
-+	cmd_params->threshold_exit = cpu_to_le32(cfg->threshold_exit);
-+
-+	return mc_send_command(mc_io, &cmd);
-+}
-+
-+/**
-+ * dpseci_get_congestion_notification() - Get congestion group notification
-+ *	configuration
-+ * @mc_io:	Pointer to MC portal's I/O object
-+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-+ * @token:	Token of DPSECI object
-+ * @cfg:	congestion notification configuration
-+ *
-+ * Return:	'0' on success, error code otherwise
-+ */
-+int dpseci_get_congestion_notification(struct fsl_mc_io *mc_io, u32 cmd_flags,
-+	u16 token, struct dpseci_congestion_notification_cfg *cfg)
-+{
-+	struct fsl_mc_command cmd = { 0 };
-+	struct dpseci_cmd_congestion_notification *rsp_params;
-+	int err;
-+
-+	cmd.header = mc_encode_cmd_header(
-+			DPSECI_CMDID_GET_CONGESTION_NOTIFICATION,
-+			cmd_flags,
-+			token);
-+	err = mc_send_command(mc_io, &cmd);
-+	if (err)
-+		return err;
-+
-+	rsp_params = (struct dpseci_cmd_congestion_notification *)cmd.params;
-+	cfg->dest_cfg.dest_id = le32_to_cpu(rsp_params->dest_id);
-+	cfg->notification_mode = le16_to_cpu(rsp_params->notification_mode);
-+	cfg->dest_cfg.priority = rsp_params->priority;
-+	cfg->dest_cfg.dest_type = dpseci_get_field(rsp_params->options,
-+						   CGN_DEST_TYPE);
-+	cfg->units = dpseci_get_field(rsp_params->options, CGN_UNITS);
-+	cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
-+	cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
-+	cfg->threshold_entry = le32_to_cpu(rsp_params->threshold_entry);
-+	cfg->threshold_exit = le32_to_cpu(rsp_params->threshold_exit);
-+
-+	return 0;
-+}
---- /dev/null
-+++ b/drivers/crypto/caam/dpseci.h
-@@ -0,0 +1,433 @@
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the names of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+#ifndef _DPSECI_H_
-+#define _DPSECI_H_
-+
-+/*
-+ * Data Path SEC Interface API
-+ * Contains initialization APIs and runtime control APIs for DPSECI
-+ */
-+
-+struct fsl_mc_io;
-+struct opr_cfg;
-+struct opr_qry;
-+
-+/**
-+ * General DPSECI macros
-+ */
-+
-+/**
-+ * Maximum number of Tx/Rx queues per DPSECI object
-+ */
-+#define DPSECI_MAX_QUEUE_NUM		16
-+
-+/**
-+ * All queues considered; see dpseci_set_rx_queue()
-+ */
-+#define DPSECI_ALL_QUEUES	(u8)(-1)
-+
-+int dpseci_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpseci_id,
-+		u16 *token);
-+
-+int dpseci_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
-+
-+/**
-+ * Enable the Congestion Group support
-+ */
-+#define DPSECI_OPT_HAS_CG		0x000020
-+
-+/**
-+ * Enable the Order Restoration support
-+ */
-+#define DPSECI_OPT_HAS_OPR		0x000040
-+
-+/**
-+ * Order Point Records are shared for the entire DPSECI
-+ */
-+#define DPSECI_OPT_OPR_SHARED		0x000080
-+
-+/**
-+ * struct dpseci_cfg - Structure representing DPSECI configuration
-+ * @options: Any combination of the following options:
-+ *		DPSECI_OPT_HAS_CG
-+ *		DPSECI_OPT_HAS_OPR
-+ *		DPSECI_OPT_OPR_SHARED
-+ * @num_tx_queues: num of queues towards the SEC
-+ * @num_rx_queues: num of queues back from the SEC
-+ * @priorities: Priorities for the SEC hardware processing;
-+ *		each place in the array is the priority of the tx queue
-+ *		towards the SEC;
-+ *		valid priorities are configured with values 1-8;
-+ */
-+struct dpseci_cfg {
-+	u32 options;
-+	u8 num_tx_queues;
-+	u8 num_rx_queues;
-+	u8 priorities[DPSECI_MAX_QUEUE_NUM];
-+};
-+
-+int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
-+		  const struct dpseci_cfg *cfg, u32 *obj_id);
-+
-+int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
-+		   u32 object_id);
-+
-+int dpseci_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
-+
-+int dpseci_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
-+
-+int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+		      int *en);
-+
-+int dpseci_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
-+
-+int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			  u8 irq_index, u8 *en);
-+
-+int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			  u8 irq_index, u8 en);
-+
-+int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 irq_index, u32 *mask);
-+
-+int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 irq_index, u32 mask);
-+
-+int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			  u8 irq_index, u32 *status);
-+
-+int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			    u8 irq_index, u32 status);
-+
-+/**
-+ * struct dpseci_attr - Structure representing DPSECI attributes
-+ * @id: DPSECI object ID
-+ * @num_tx_queues: number of queues towards the SEC
-+ * @num_rx_queues: number of queues back from the SEC
-+ * @options: any combination of the following options:
-+ *		DPSECI_OPT_HAS_CG
-+ *		DPSECI_OPT_HAS_OPR
-+ *		DPSECI_OPT_OPR_SHARED
-+ */
-+struct dpseci_attr {
-+	int id;
-+	u8 num_tx_queues;
-+	u8 num_rx_queues;
-+	u32 options;
-+};
-+
-+int dpseci_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			  struct dpseci_attr *attr);
-+
-+/**
-+ * enum dpseci_dest - DPSECI destination types
-+ * @DPSECI_DEST_NONE: Unassigned destination; The queue is set in parked mode
-+ *	and does not generate FQDAN notifications; user is expected to dequeue
-+ *	from the queue based on polling or other user-defined method
-+ * @DPSECI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
-+ *	notifications to the specified DPIO; user is expected to dequeue from
-+ *	the queue only after notification is received
-+ * @DPSECI_DEST_DPCON: The queue is set in schedule mode and does not generate
-+ *	FQDAN notifications, but is connected to the specified DPCON object;
-+ *	user is expected to dequeue from the DPCON channel
-+ */
-+enum dpseci_dest {
-+	DPSECI_DEST_NONE = 0,
-+	DPSECI_DEST_DPIO,
-+	DPSECI_DEST_DPCON
-+};
-+
-+/**
-+ * struct dpseci_dest_cfg - Structure representing DPSECI destination parameters
-+ * @dest_type: Destination type
-+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
-+ * @priority: Priority selection within the DPIO or DPCON channel; valid values
-+ *	are 0-1 or 0-7, depending on the number of priorities in that channel;
-+ *	not relevant for 'DPSECI_DEST_NONE' option
-+ */
-+struct dpseci_dest_cfg {
-+	enum dpseci_dest dest_type;
-+	int dest_id;
-+	u8 priority;
-+};
-+
-+/**
-+ * DPSECI queue modification options
-+ */
-+
-+/**
-+ * Select to modify the user's context associated with the queue
-+ */
-+#define DPSECI_QUEUE_OPT_USER_CTX		0x00000001
-+
-+/**
-+ * Select to modify the queue's destination
-+ */
-+#define DPSECI_QUEUE_OPT_DEST			0x00000002
-+
-+/**
-+ * Select to modify the queue's order preservation
-+ */
-+#define DPSECI_QUEUE_OPT_ORDER_PRESERVATION	0x00000004
-+
-+/**
-+ * struct dpseci_rx_queue_cfg - DPSECI RX queue configuration
-+ * @options: Flags representing the suggested modifications to the queue;
-+ *	Use any combination of 'DPSECI_QUEUE_OPT_<X>' flags
-+ * @order_preservation_en: order preservation configuration for the rx queue
-+ * valid only if 'DPSECI_QUEUE_OPT_ORDER_PRESERVATION' is contained in 'options'
-+ * @user_ctx: User context value provided in the frame descriptor of each
-+ *	dequeued frame;	valid only if 'DPSECI_QUEUE_OPT_USER_CTX' is contained
-+ *	in 'options'
-+ * @dest_cfg: Queue destination parameters; valid only if
-+ *	'DPSECI_QUEUE_OPT_DEST' is contained in 'options'
-+ */
-+struct dpseci_rx_queue_cfg {
-+	u32 options;
-+	int order_preservation_en;
-+	u64 user_ctx;
-+	struct dpseci_dest_cfg dest_cfg;
-+};
-+
-+int dpseci_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 queue, const struct dpseci_rx_queue_cfg *cfg);
-+
-+/**
-+ * struct dpseci_rx_queue_attr - Structure representing attributes of Rx queues
-+ * @user_ctx: User context value provided in the frame descriptor of each
-+ *	dequeued frame
-+ * @order_preservation_en: Status of the order preservation configuration on the
-+ *	queue
-+ * @dest_cfg: Queue destination configuration
-+ * @fqid: Virtual FQID value to be used for dequeue operations
-+ */
-+struct dpseci_rx_queue_attr {
-+	u64 user_ctx;
-+	int order_preservation_en;
-+	struct dpseci_dest_cfg dest_cfg;
-+	u32 fqid;
-+};
-+
-+int dpseci_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 queue, struct dpseci_rx_queue_attr *attr);
-+
-+/**
-+ * struct dpseci_tx_queue_attr - Structure representing attributes of Tx queues
-+ * @fqid: Virtual FQID to be used for sending frames to SEC hardware
-+ * @priority: SEC hardware processing priority for the queue
-+ */
-+struct dpseci_tx_queue_attr {
-+	u32 fqid;
-+	u8 priority;
-+};
-+
-+int dpseci_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			u8 queue, struct dpseci_tx_queue_attr *attr);
-+
-+/**
-+ * struct dpseci_sec_attr - Structure representing attributes of the SEC
-+ *	hardware accelerator
-+ * @ip_id: ID for SEC
-+ * @major_rev: Major revision number for SEC
-+ * @minor_rev: Minor revision number for SEC
-+ * @era: SEC Era
-+ * @deco_num: The number of copies of the DECO that are implemented in this
-+ *	version of SEC
-+ * @zuc_auth_acc_num: The number of copies of ZUCA that are implemented in this
-+ *	version of SEC
-+ * @zuc_enc_acc_num: The number of copies of ZUCE that are implemented in this
-+ *	version of SEC
-+ * @snow_f8_acc_num: The number of copies of the SNOW-f8 module that are
-+ *	implemented in this version of SEC
-+ * @snow_f9_acc_num: The number of copies of the SNOW-f9 module that are
-+ *	implemented in this version of SEC
-+ * @crc_acc_num: The number of copies of the CRC module that are implemented in
-+ *	this version of SEC
-+ * @pk_acc_num:  The number of copies of the Public Key module that are
-+ *	implemented in this version of SEC
-+ * @kasumi_acc_num: The number of copies of the Kasumi module that are
-+ *	implemented in this version of SEC
-+ * @rng_acc_num: The number of copies of the Random Number Generator that are
-+ *	implemented in this version of SEC
-+ * @md_acc_num: The number of copies of the MDHA (Hashing module) that are
-+ *	implemented in this version of SEC
-+ * @arc4_acc_num: The number of copies of the ARC4 module that are implemented
-+ *	in this version of SEC
-+ * @des_acc_num: The number of copies of the DES module that are implemented in
-+ *	this version of SEC
-+ * @aes_acc_num: The number of copies of the AES module that are implemented in
-+ *	this version of SEC
-+ * @ccha_acc_num: The number of copies of the ChaCha20 module that are
-+ *	implemented in this version of SEC.
-+ * @ptha_acc_num: The number of copies of the Poly1305 module that are
-+ *	implemented in this version of SEC.
-+ **/
-+struct dpseci_sec_attr {
-+	u16 ip_id;
-+	u8 major_rev;
-+	u8 minor_rev;
-+	u8 era;
-+	u8 deco_num;
-+	u8 zuc_auth_acc_num;
-+	u8 zuc_enc_acc_num;
-+	u8 snow_f8_acc_num;
-+	u8 snow_f9_acc_num;
-+	u8 crc_acc_num;
-+	u8 pk_acc_num;
-+	u8 kasumi_acc_num;
-+	u8 rng_acc_num;
-+	u8 md_acc_num;
-+	u8 arc4_acc_num;
-+	u8 des_acc_num;
-+	u8 aes_acc_num;
-+	u8 ccha_acc_num;
-+	u8 ptha_acc_num;
-+};
-+
-+int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			struct dpseci_sec_attr *attr);
-+
-+/**
-+ * struct dpseci_sec_counters - Structure representing global SEC counters and
-+ *				not per dpseci counters
-+ * @dequeued_requests:	Number of Requests Dequeued
-+ * @ob_enc_requests:	Number of Outbound Encrypt Requests
-+ * @ib_dec_requests:	Number of Inbound Decrypt Requests
-+ * @ob_enc_bytes:	Number of Outbound Bytes Encrypted
-+ * @ob_prot_bytes:	Number of Outbound Bytes Protected
-+ * @ib_dec_bytes:	Number of Inbound Bytes Decrypted
-+ * @ib_valid_bytes:	Number of Inbound Bytes Validated
-+ */
-+struct dpseci_sec_counters {
-+	u64 dequeued_requests;
-+	u64 ob_enc_requests;
-+	u64 ib_dec_requests;
-+	u64 ob_enc_bytes;
-+	u64 ob_prot_bytes;
-+	u64 ib_dec_bytes;
-+	u64 ib_valid_bytes;
-+};
-+
-+int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
-+			    struct dpseci_sec_counters *counters);
-+
-+int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
-+			   u16 *major_ver, u16 *minor_ver);
-+
-+int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
-+		   u8 options, struct opr_cfg *cfg);
-+
-+int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
-+		   struct opr_cfg *cfg, struct opr_qry *qry);
-+
-+/**
-+ * enum dpseci_congestion_unit - DPSECI congestion units
-+ * @DPSECI_CONGESTION_UNIT_BYTES: bytes units
-+ * @DPSECI_CONGESTION_UNIT_FRAMES: frames units
-+ */
-+enum dpseci_congestion_unit {
-+	DPSECI_CONGESTION_UNIT_BYTES = 0,
-+	DPSECI_CONGESTION_UNIT_FRAMES
-+};
-+
-+/**
-+ * CSCN message is written to message_iova once entering a
-+ * congestion state (see 'threshold_entry')
-+ */
-+#define DPSECI_CGN_MODE_WRITE_MEM_ON_ENTER		0x00000001
-+
-+/**
-+ * CSCN message is written to message_iova once exiting a
-+ * congestion state (see 'threshold_exit')
-+ */
-+#define DPSECI_CGN_MODE_WRITE_MEM_ON_EXIT		0x00000002
-+
-+/**
-+ * CSCN write will attempt to allocate into a cache (coherent write);
-+ * valid only if 'DPSECI_CGN_MODE_WRITE_MEM_<X>' is selected
-+ */
-+#define DPSECI_CGN_MODE_COHERENT_WRITE			0x00000004
-+
-+/**
-+ * if 'dpseci_dest_cfg.dest_type != DPSECI_DEST_NONE' CSCN message is sent to
-+ * DPIO/DPCON's WQ channel once entering a congestion state
-+ * (see 'threshold_entry')
-+ */
-+#define DPSECI_CGN_MODE_NOTIFY_DEST_ON_ENTER		0x00000008
-+
-+/**
-+ * if 'dpseci_dest_cfg.dest_type != DPSECI_DEST_NONE' CSCN message is sent to
-+ * DPIO/DPCON's WQ channel once exiting a congestion state
-+ * (see 'threshold_exit')
-+ */
-+#define DPSECI_CGN_MODE_NOTIFY_DEST_ON_EXIT		0x00000010
-+
-+/**
-+ * if 'dpseci_dest_cfg.dest_type != DPSECI_DEST_NONE' when the CSCN is written
-+ * to the sw-portal's DQRR, the DQRI interrupt is asserted immediately
-+ * (if enabled)
-+ */
-+#define DPSECI_CGN_MODE_INTR_COALESCING_DISABLED	0x00000020
-+
-+/**
-+ * struct dpseci_congestion_notification_cfg - congestion notification
-+ *	configuration
-+ * @units: units type
-+ * @threshold_entry: above this threshold we enter a congestion state.
-+ *	set it to '0' to disable it
-+ * @threshold_exit: below this threshold we exit the congestion state.
-+ * @message_ctx: The context that will be part of the CSCN message
-+ * @message_iova: I/O virtual address (must be in DMA-able memory),
-+ *	must be 16B aligned;
-+ * @dest_cfg: CSCN can be send to either DPIO or DPCON WQ channel
-+ * @notification_mode: Mask of available options; use 'DPSECI_CGN_MODE_<X>'
-+ *	values
-+ */
-+struct dpseci_congestion_notification_cfg {
-+	enum dpseci_congestion_unit units;
-+	u32 threshold_entry;
-+	u32 threshold_exit;
-+	u64 message_ctx;
-+	u64 message_iova;
-+	struct dpseci_dest_cfg dest_cfg;
-+	u16 notification_mode;
-+};
-+
-+int dpseci_set_congestion_notification(struct fsl_mc_io *mc_io, u32 cmd_flags,
-+	u16 token, const struct dpseci_congestion_notification_cfg *cfg);
-+
-+int dpseci_get_congestion_notification(struct fsl_mc_io *mc_io, u32 cmd_flags,
-+	u16 token, struct dpseci_congestion_notification_cfg *cfg);
-+
-+#endif /* _DPSECI_H_ */
---- /dev/null
-+++ b/drivers/crypto/caam/dpseci_cmd.h
-@@ -0,0 +1,287 @@
-+/*
-+ * Copyright 2013-2016 Freescale Semiconductor Inc.
-+ * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *	 notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *	 notice, this list of conditions and the following disclaimer in the
-+ *	 documentation and/or other materials provided with the distribution.
-+ *     * Neither the names of the above-listed copyright holders nor the
-+ *	 names of any contributors may be used to endorse or promote products
-+ *	 derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef _DPSECI_CMD_H_
-+#define _DPSECI_CMD_H_
-+
-+/* DPSECI Version */
-+#define DPSECI_VER_MAJOR				5
-+#define DPSECI_VER_MINOR				3
-+
-+#define DPSECI_VER(maj, min)	(((maj) << 16) | (min))
-+#define DPSECI_VERSION		DPSECI_VER(DPSECI_VER_MAJOR, DPSECI_VER_MINOR)
-+
-+/* Command versioning */
-+#define DPSECI_CMD_BASE_VERSION		1
-+#define DPSECI_CMD_BASE_VERSION_V2	2
-+#define DPSECI_CMD_BASE_VERSION_V3	3
-+#define DPSECI_CMD_ID_OFFSET		4
-+
-+#define DPSECI_CMD_V1(id)	(((id) << DPSECI_CMD_ID_OFFSET) | \
-+				 DPSECI_CMD_BASE_VERSION)
-+
-+#define DPSECI_CMD_V2(id)	(((id) << DPSECI_CMD_ID_OFFSET) | \
-+				 DPSECI_CMD_BASE_VERSION_V2)
-+
-+#define DPSECI_CMD_V3(id)	(((id) << DPSECI_CMD_ID_OFFSET) | \
-+				 DPSECI_CMD_BASE_VERSION_V3)
-+
-+/* Command IDs */
-+#define DPSECI_CMDID_CLOSE				DPSECI_CMD_V1(0x800)
-+#define DPSECI_CMDID_OPEN				DPSECI_CMD_V1(0x809)
-+#define DPSECI_CMDID_CREATE				DPSECI_CMD_V3(0x909)
-+#define DPSECI_CMDID_DESTROY				DPSECI_CMD_V1(0x989)
-+#define DPSECI_CMDID_GET_API_VERSION			DPSECI_CMD_V1(0xa09)
-+
-+#define DPSECI_CMDID_ENABLE				DPSECI_CMD_V1(0x002)
-+#define DPSECI_CMDID_DISABLE				DPSECI_CMD_V1(0x003)
-+#define DPSECI_CMDID_GET_ATTR				DPSECI_CMD_V1(0x004)
-+#define DPSECI_CMDID_RESET				DPSECI_CMD_V1(0x005)
-+#define DPSECI_CMDID_IS_ENABLED				DPSECI_CMD_V1(0x006)
-+
-+#define DPSECI_CMDID_SET_IRQ_ENABLE			DPSECI_CMD_V1(0x012)
-+#define DPSECI_CMDID_GET_IRQ_ENABLE			DPSECI_CMD_V1(0x013)
-+#define DPSECI_CMDID_SET_IRQ_MASK			DPSECI_CMD_V1(0x014)
-+#define DPSECI_CMDID_GET_IRQ_MASK			DPSECI_CMD_V1(0x015)
-+#define DPSECI_CMDID_GET_IRQ_STATUS			DPSECI_CMD_V1(0x016)
-+#define DPSECI_CMDID_CLEAR_IRQ_STATUS			DPSECI_CMD_V1(0x017)
-+
-+#define DPSECI_CMDID_SET_RX_QUEUE			DPSECI_CMD_V1(0x194)
-+#define DPSECI_CMDID_GET_RX_QUEUE			DPSECI_CMD_V1(0x196)
-+#define DPSECI_CMDID_GET_TX_QUEUE			DPSECI_CMD_V1(0x197)
-+#define DPSECI_CMDID_GET_SEC_ATTR			DPSECI_CMD_V2(0x198)
-+#define DPSECI_CMDID_GET_SEC_COUNTERS			DPSECI_CMD_V1(0x199)
-+#define DPSECI_CMDID_SET_OPR				DPSECI_CMD_V1(0x19A)
-+#define DPSECI_CMDID_GET_OPR				DPSECI_CMD_V1(0x19B)
-+#define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION	DPSECI_CMD_V1(0x170)
-+#define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION	DPSECI_CMD_V1(0x171)
-+
-+/* Macros for accessing command fields smaller than 1 byte */
-+#define DPSECI_MASK(field)	\
-+	GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1,	\
-+		DPSECI_##field##_SHIFT)
-+
-+#define dpseci_set_field(var, field, val)	\
-+	((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field)))
-+
-+#define dpseci_get_field(var, field)	\
-+	(((var) & DPSECI_MASK(field)) >> DPSECI_##field##_SHIFT)
-+
-+struct dpseci_cmd_open {
-+	__le32 dpseci_id;
-+};
-+
-+struct dpseci_cmd_create {
-+	u8 priorities[8];
-+	u8 num_tx_queues;
-+	u8 num_rx_queues;
-+	u8 pad0[6];
-+	__le32 options;
-+	__le32 pad1;
-+	u8 priorities2[8];
-+};
-+
-+struct dpseci_cmd_destroy {
-+	__le32 object_id;
-+};
-+
-+#define DPSECI_ENABLE_SHIFT	0
-+#define DPSECI_ENABLE_SIZE	1
-+
-+struct dpseci_rsp_is_enabled {
-+	u8 is_enabled;
-+};
-+
-+struct dpseci_cmd_irq_enable {
-+	u8 enable_state;
-+	u8 pad[3];
-+	u8 irq_index;
-+};
-+
-+struct dpseci_rsp_get_irq_enable {
-+	u8 enable_state;
-+};
-+
-+struct dpseci_cmd_irq_mask {
-+	__le32 mask;
-+	u8 irq_index;
-+};
-+
-+struct dpseci_cmd_irq_status {
-+	__le32 status;
-+	u8 irq_index;
-+};
-+
-+struct dpseci_rsp_get_attributes {
-+	__le32 id;
-+	__le32 pad0;
-+	u8 num_tx_queues;
-+	u8 num_rx_queues;
-+	u8 pad1[6];
-+	__le32 options;
-+};
-+
-+#define DPSECI_DEST_TYPE_SHIFT	0
-+#define DPSECI_DEST_TYPE_SIZE	4
-+
-+#define DPSECI_ORDER_PRESERVATION_SHIFT	0
-+#define DPSECI_ORDER_PRESERVATION_SIZE	1
-+
-+struct dpseci_cmd_queue {
-+	__le32 dest_id;
-+	u8 priority;
-+	u8 queue;
-+	u8 dest_type;
-+	u8 pad;
-+	__le64 user_ctx;
-+	union {
-+		__le32 options;
-+		__le32 fqid;
-+	};
-+	u8 order_preservation_en;
-+};
-+
-+struct dpseci_rsp_get_tx_queue {
-+	__le32 pad;
-+	__le32 fqid;
-+	u8 priority;
-+};
-+
-+struct dpseci_rsp_get_sec_attr {
-+	__le16 ip_id;
-+	u8 major_rev;
-+	u8 minor_rev;
-+	u8 era;
-+	u8 pad0[3];
-+	u8 deco_num;
-+	u8 zuc_auth_acc_num;
-+	u8 zuc_enc_acc_num;
-+	u8 pad1;
-+	u8 snow_f8_acc_num;
-+	u8 snow_f9_acc_num;
-+	u8 crc_acc_num;
-+	u8 pad2;
-+	u8 pk_acc_num;
-+	u8 kasumi_acc_num;
-+	u8 rng_acc_num;
-+	u8 pad3;
-+	u8 md_acc_num;
-+	u8 arc4_acc_num;
-+	u8 des_acc_num;
-+	u8 aes_acc_num;
-+	u8 ccha_acc_num;
-+	u8 ptha_acc_num;
-+};
-+
-+struct dpseci_rsp_get_sec_counters {
-+	__le64 dequeued_requests;
-+	__le64 ob_enc_requests;
-+	__le64 ib_dec_requests;
-+	__le64 ob_enc_bytes;
-+	__le64 ob_prot_bytes;
-+	__le64 ib_dec_bytes;
-+	__le64 ib_valid_bytes;
-+};
-+
-+struct dpseci_rsp_get_api_version {
-+	__le16 major;
-+	__le16 minor;
-+};
-+
-+struct dpseci_cmd_opr {
-+	__le16 pad;
-+	u8 index;
-+	u8 options;
-+	u8 pad1[7];
-+	u8 oloe;
-+	u8 oeane;
-+	u8 olws;
-+	u8 oa;
-+	u8 oprrws;
-+};
-+
-+#define DPSECI_OPR_RIP_SHIFT		0
-+#define DPSECI_OPR_RIP_SIZE		1
-+#define DPSECI_OPR_ENABLE_SHIFT		1
-+#define DPSECI_OPR_ENABLE_SIZE		1
-+#define DPSECI_OPR_TSEQ_NLIS_SHIFT	0
-+#define DPSECI_OPR_TSEQ_NLIS_SIZE	1
-+#define DPSECI_OPR_HSEQ_NLIS_SHIFT	0
-+#define DPSECI_OPR_HSEQ_NLIS_SIZE	1
-+
-+struct dpseci_rsp_get_opr {
-+	__le64 pad;
-+	u8 flags;
-+	u8 pad0[2];
-+	u8 oloe;
-+	u8 oeane;
-+	u8 olws;
-+	u8 oa;
-+	u8 oprrws;
-+	__le16 nesn;
-+	__le16 pad1;
-+	__le16 ndsn;
-+	__le16 pad2;
-+	__le16 ea_tseq;
-+	u8 tseq_nlis;
-+	u8 pad3;
-+	__le16 ea_hseq;
-+	u8 hseq_nlis;
-+	u8 pad4;
-+	__le16 ea_hptr;
-+	__le16 pad5;
-+	__le16 ea_tptr;
-+	__le16 pad6;
-+	__le16 opr_vid;
-+	__le16 pad7;
-+	__le16 opr_id;
-+};
-+
-+#define DPSECI_CGN_DEST_TYPE_SHIFT	0
-+#define DPSECI_CGN_DEST_TYPE_SIZE	4
-+#define DPSECI_CGN_UNITS_SHIFT		4
-+#define DPSECI_CGN_UNITS_SIZE		2
-+
-+struct dpseci_cmd_congestion_notification {
-+	__le32 dest_id;
-+	__le16 notification_mode;
-+	u8 priority;
-+	u8 options;
-+	__le64 message_iova;
-+	__le64 message_ctx;
-+	__le32 threshold_entry;
-+	__le32 threshold_exit;
-+};
-+
-+#endif /* _DPSECI_CMD_H_ */
---- a/drivers/crypto/caam/error.c
-+++ b/drivers/crypto/caam/error.c
-@@ -108,6 +108,54 @@ static const struct {
- 	{ 0xF1, "3GPP HFN matches or exceeds the Threshold" },
- };
- 
-+static const struct {
-+	u8 value;
-+	const char *error_text;
-+} qi_error_list[] = {
-+	{ 0x1F, "Job terminated by FQ or ICID flush" },
-+	{ 0x20, "FD format error"},
-+	{ 0x21, "FD command format error"},
-+	{ 0x23, "FL format error"},
-+	{ 0x25, "CRJD specified in FD, but not enabled in FLC"},
-+	{ 0x30, "Max. buffer size too small"},
-+	{ 0x31, "DHR exceeds max. buffer size (allocate mode, S/G format)"},
-+	{ 0x32, "SGT exceeds max. buffer size (allocate mode, S/G format"},
-+	{ 0x33, "Size over/underflow (allocate mode)"},
-+	{ 0x34, "Size over/underflow (reuse mode)"},
-+	{ 0x35, "Length exceeds max. short length (allocate mode, S/G/ format)"},
-+	{ 0x36, "Memory footprint exceeds max. value (allocate mode, S/G/ format)"},
-+	{ 0x41, "SBC frame format not supported (allocate mode)"},
-+	{ 0x42, "Pool 0 invalid / pool 1 size < pool 0 size (allocate mode)"},
-+	{ 0x43, "Annotation output enabled but ASAR = 0 (allocate mode)"},
-+	{ 0x44, "Unsupported or reserved frame format or SGHR = 1 (reuse mode)"},
-+	{ 0x45, "DHR correction underflow (reuse mode, single buffer format)"},
-+	{ 0x46, "Annotation length exceeds offset (reuse mode)"},
-+	{ 0x48, "Annotation output enabled but ASA limited by ASAR (reuse mode)"},
-+	{ 0x49, "Data offset correction exceeds input frame data length (reuse mode)"},
-+	{ 0x4B, "Annotation output enabled but ASA cannote be expanded (frame list)"},
-+	{ 0x51, "Unsupported IF reuse mode"},
-+	{ 0x52, "Unsupported FL use mode"},
-+	{ 0x53, "Unsupported RJD use mode"},
-+	{ 0x54, "Unsupported inline descriptor use mode"},
-+	{ 0xC0, "Table buffer pool 0 depletion"},
-+	{ 0xC1, "Table buffer pool 1 depletion"},
-+	{ 0xC2, "Data buffer pool 0 depletion, no OF allocated"},
-+	{ 0xC3, "Data buffer pool 1 depletion, no OF allocated"},
-+	{ 0xC4, "Data buffer pool 0 depletion, partial OF allocated"},
-+	{ 0xC5, "Data buffer pool 1 depletion, partial OF allocated"},
-+	{ 0xD0, "FLC read error"},
-+	{ 0xD1, "FL read error"},
-+	{ 0xD2, "FL write error"},
-+	{ 0xD3, "OF SGT write error"},
-+	{ 0xD4, "PTA read error"},
-+	{ 0xD5, "PTA write error"},
-+	{ 0xD6, "OF SGT F-bit write error"},
-+	{ 0xD7, "ASA write error"},
-+	{ 0xE1, "FLC[ICR]=0 ICID error"},
-+	{ 0xE2, "FLC[ICR]=1 ICID error"},
-+	{ 0xE4, "source of ICID flush not trusted (BDI = 0)"},
-+};
-+
- static const char * const cha_id_list[] = {
- 	"",
- 	"AES",
-@@ -236,6 +284,27 @@ static void report_deco_status(struct de
- 		status, error, idx_str, idx, err_str, err_err_code);
- }
- 
-+static void report_qi_status(struct device *qidev, const u32 status,
-+			     const char *error)
-+{
-+	u8 err_id = status & JRSTA_QIERR_ERROR_MASK;
-+	const char *err_str = "unidentified error value 0x";
-+	char err_err_code[3] = { 0 };
-+	int i;
-+
-+	for (i = 0; i < ARRAY_SIZE(qi_error_list); i++)
-+		if (qi_error_list[i].value == err_id)
-+			break;
-+
-+	if (i != ARRAY_SIZE(qi_error_list) && qi_error_list[i].error_text)
-+		err_str = qi_error_list[i].error_text;
-+	else
-+		snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
-+
-+	dev_err(qidev, "%08x: %s: %s%s\n",
-+		status, error, err_str, err_err_code);
-+}
-+
- static void report_jr_status(struct device *jrdev, const u32 status,
- 			     const char *error)
- {
-@@ -250,7 +319,7 @@ static void report_cond_code_status(stru
- 		status, error, __func__);
- }
- 
--void caam_jr_strstatus(struct device *jrdev, u32 status)
-+void caam_strstatus(struct device *jrdev, u32 status, bool qi_v2)
- {
- 	static const struct stat_src {
- 		void (*report_ssed)(struct device *jrdev, const u32 status,
-@@ -262,7 +331,7 @@ void caam_jr_strstatus(struct device *jr
- 		{ report_ccb_status, "CCB" },
- 		{ report_jump_status, "Jump" },
- 		{ report_deco_status, "DECO" },
--		{ NULL, "Queue Manager Interface" },
-+		{ report_qi_status, "Queue Manager Interface" },
- 		{ report_jr_status, "Job Ring" },
- 		{ report_cond_code_status, "Condition Code" },
- 		{ NULL, NULL },
-@@ -288,4 +357,4 @@ void caam_jr_strstatus(struct device *jr
- 	else
- 		dev_err(jrdev, "%d: unknown error source\n", ssrc);
- }
--EXPORT_SYMBOL(caam_jr_strstatus);
-+EXPORT_SYMBOL(caam_strstatus);
---- a/drivers/crypto/caam/error.h
-+++ b/drivers/crypto/caam/error.h
-@@ -8,7 +8,11 @@
- #ifndef CAAM_ERROR_H
- #define CAAM_ERROR_H
- #define CAAM_ERROR_STR_MAX 302
--void caam_jr_strstatus(struct device *jrdev, u32 status);
-+
-+void caam_strstatus(struct device *dev, u32 status, bool qi_v2);
-+
-+#define caam_jr_strstatus(jrdev, status) caam_strstatus(jrdev, status, false)
-+#define caam_qi2_strstatus(qidev, status) caam_strstatus(qidev, status, true)
- 
- void caam_dump_sg(const char *level, const char *prefix_str, int prefix_type,
- 		  int rowsize, int groupsize, struct scatterlist *sg,
---- a/drivers/crypto/caam/intern.h
-+++ b/drivers/crypto/caam/intern.h
-@@ -84,6 +84,7 @@ struct caam_drv_private {
- 	u8 qi_present;		/* Nonzero if QI present in device */
- 	int secvio_irq;		/* Security violation interrupt number */
- 	int virt_en;		/* Virtualization enabled in CAAM */
-+	int era;		/* CAAM Era (internal HW revision) */
- 
- #define	RNG4_MAX_HANDLES 2
- 	/* RNG4 block */
---- a/drivers/crypto/caam/jr.c
-+++ b/drivers/crypto/caam/jr.c
-@@ -23,6 +23,14 @@ struct jr_driver_data {
- 
- static struct jr_driver_data driver_data;
- 
-+static int jr_driver_probed;
-+
-+int caam_jr_driver_probed(void)
-+{
-+	return jr_driver_probed;
-+}
-+EXPORT_SYMBOL(caam_jr_driver_probed);
-+
- static int caam_reset_hw_jr(struct device *dev)
- {
- 	struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
-@@ -119,6 +127,8 @@ static int caam_jr_remove(struct platfor
- 		dev_err(jrdev, "Failed to shut down job ring\n");
- 	irq_dispose_mapping(jrpriv->irq);
- 
-+	jr_driver_probed--;
-+
- 	return ret;
- }
- 
-@@ -282,6 +292,36 @@ struct device *caam_jr_alloc(void)
- EXPORT_SYMBOL(caam_jr_alloc);
- 
- /**
-+ * caam_jridx_alloc() - Alloc a specific job ring based on its index.
-+ *
-+ * returns :  pointer to the newly allocated physical
-+ *	      JobR dev can be written to if successful.
-+ **/
-+struct device *caam_jridx_alloc(int idx)
-+{
-+	struct caam_drv_private_jr *jrpriv;
-+	struct device *dev = ERR_PTR(-ENODEV);
-+
-+	spin_lock(&driver_data.jr_alloc_lock);
-+
-+	if (list_empty(&driver_data.jr_list))
-+		goto end;
-+
-+	list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) {
-+		if (jrpriv->ridx == idx) {
-+			atomic_inc(&jrpriv->tfm_count);
-+			dev = jrpriv->dev;
-+			break;
-+		}
-+	}
-+
-+end:
-+	spin_unlock(&driver_data.jr_alloc_lock);
-+	return dev;
-+}
-+EXPORT_SYMBOL(caam_jridx_alloc);
-+
-+/**
-  * caam_jr_free() - Free the Job Ring
-  * @rdev     - points to the dev that identifies the Job ring to
-  *             be released.
-@@ -539,6 +579,8 @@ static int caam_jr_probe(struct platform
- 
- 	atomic_set(&jrpriv->tfm_count, 0);
- 
-+	jr_driver_probed++;
-+
- 	return 0;
- }
- 
---- a/drivers/crypto/caam/jr.h
-+++ b/drivers/crypto/caam/jr.h
-@@ -9,7 +9,9 @@
- #define JR_H
- 
- /* Prototypes for backend-level services exposed to APIs */
-+int caam_jr_driver_probed(void);
- struct device *caam_jr_alloc(void);
-+struct device *caam_jridx_alloc(int idx);
- void caam_jr_free(struct device *rdev);
- int caam_jr_enqueue(struct device *dev, u32 *desc,
- 		    void (*cbk)(struct device *dev, u32 *desc, u32 status,
---- a/drivers/crypto/caam/key_gen.c
-+++ b/drivers/crypto/caam/key_gen.c
-@@ -11,36 +11,6 @@
- #include "desc_constr.h"
- #include "key_gen.h"
- 
--/**
-- * split_key_len - Compute MDHA split key length for a given algorithm
-- * @hash: Hashing algorithm selection, one of OP_ALG_ALGSEL_* - MD5, SHA1,
-- *        SHA224, SHA384, SHA512.
-- *
-- * Return: MDHA split key length
-- */
--static inline u32 split_key_len(u32 hash)
--{
--	/* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
--	static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
--	u32 idx;
--
--	idx = (hash & OP_ALG_ALGSEL_SUBMASK) >> OP_ALG_ALGSEL_SHIFT;
--
--	return (u32)(mdpadlen[idx] * 2);
--}
--
--/**
-- * split_key_pad_len - Compute MDHA split key pad length for a given algorithm
-- * @hash: Hashing algorithm selection, one of OP_ALG_ALGSEL_* - MD5, SHA1,
-- *        SHA224, SHA384, SHA512.
-- *
-- * Return: MDHA split key pad length
-- */
--static inline u32 split_key_pad_len(u32 hash)
--{
--	return ALIGN(split_key_len(hash), 16);
--}
--
- void split_key_done(struct device *dev, u32 *desc, u32 err,
- 			   void *context)
- {
---- a/drivers/crypto/caam/key_gen.h
-+++ b/drivers/crypto/caam/key_gen.h
-@@ -6,6 +6,36 @@
-  *
-  */
- 
-+/**
-+ * split_key_len - Compute MDHA split key length for a given algorithm
-+ * @hash: Hashing algorithm selection, one of OP_ALG_ALGSEL_* - MD5, SHA1,
-+ *        SHA224, SHA384, SHA512.
-+ *
-+ * Return: MDHA split key length
-+ */
-+static inline u32 split_key_len(u32 hash)
-+{
-+	/* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
-+	static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
-+	u32 idx;
-+
-+	idx = (hash & OP_ALG_ALGSEL_SUBMASK) >> OP_ALG_ALGSEL_SHIFT;
-+
-+	return (u32)(mdpadlen[idx] * 2);
-+}
-+
-+/**
-+ * split_key_pad_len - Compute MDHA split key pad length for a given algorithm
-+ * @hash: Hashing algorithm selection, one of OP_ALG_ALGSEL_* - MD5, SHA1,
-+ *        SHA224, SHA384, SHA512.
-+ *
-+ * Return: MDHA split key pad length
-+ */
-+static inline u32 split_key_pad_len(u32 hash)
-+{
-+	return ALIGN(split_key_len(hash), 16);
-+}
-+
- struct split_key_result {
- 	struct completion completion;
- 	int err;
---- a/drivers/crypto/caam/qi.c
-+++ b/drivers/crypto/caam/qi.c
-@@ -9,7 +9,7 @@
- 
- #include <linux/cpumask.h>
- #include <linux/kthread.h>
--#include <soc/fsl/qman.h>
-+#include <linux/fsl_qman.h>
- 
- #include "regs.h"
- #include "qi.h"
-@@ -105,23 +105,21 @@ static struct kmem_cache *qi_cache;
- int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req)
- {
- 	struct qm_fd fd;
--	dma_addr_t addr;
- 	int ret;
- 	int num_retries = 0;
- 
--	qm_fd_clear_fd(&fd);
--	qm_fd_set_compound(&fd, qm_sg_entry_get_len(&req->fd_sgt[1]));
--
--	addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt),
-+	fd.cmd = 0;
-+	fd.format = qm_fd_compound;
-+	fd.cong_weight = caam32_to_cpu(req->fd_sgt[1].length);
-+	fd.addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt),
- 			      DMA_BIDIRECTIONAL);
--	if (dma_mapping_error(qidev, addr)) {
-+	if (dma_mapping_error(qidev, fd.addr)) {
- 		dev_err(qidev, "DMA mapping error for QI enqueue request\n");
- 		return -EIO;
- 	}
--	qm_fd_addr_set64(&fd, addr);
- 
- 	do {
--		ret = qman_enqueue(req->drv_ctx->req_fq, &fd);
-+		ret = qman_enqueue(req->drv_ctx->req_fq, &fd, 0);
- 		if (likely(!ret))
- 			return 0;
- 
-@@ -137,7 +135,7 @@ int caam_qi_enqueue(struct device *qidev
- EXPORT_SYMBOL(caam_qi_enqueue);
- 
- static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq,
--			   const union qm_mr_entry *msg)
-+			   const struct qm_mr_entry *msg)
- {
- 	const struct qm_fd *fd;
- 	struct caam_drv_req *drv_req;
-@@ -145,7 +143,7 @@ static void caam_fq_ern_cb(struct qman_p
- 
- 	fd = &msg->ern.fd;
- 
--	if (qm_fd_get_format(fd) != qm_fd_compound) {
-+	if (fd->format != qm_fd_compound) {
- 		dev_err(qidev, "Non-compound FD from CAAM\n");
- 		return;
- 	}
-@@ -180,20 +178,22 @@ static struct qman_fq *create_caam_req_f
- 	req_fq->cb.fqs = NULL;
- 
- 	ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
--				QMAN_FQ_FLAG_TO_DCPORTAL, req_fq);
-+				QMAN_FQ_FLAG_TO_DCPORTAL | QMAN_FQ_FLAG_LOCKED,
-+			     req_fq);
- 	if (ret) {
- 		dev_err(qidev, "Failed to create session req FQ\n");
- 		goto create_req_fq_fail;
- 	}
- 
--	memset(&opts, 0, sizeof(opts));
--	opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
--				   QM_INITFQ_WE_CONTEXTB |
--				   QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID);
--	opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE);
--	qm_fqd_set_destwq(&opts.fqd, qm_channel_caam, 2);
--	opts.fqd.context_b = cpu_to_be32(qman_fq_fqid(rsp_fq));
--	qm_fqd_context_a_set64(&opts.fqd, hwdesc);
-+	opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
-+		       QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA |
-+		       QM_INITFQ_WE_CGID;
-+	opts.fqd.fq_ctrl = QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE;
-+	opts.fqd.dest.channel = qm_channel_caam;
-+	opts.fqd.dest.wq = 2;
-+	opts.fqd.context_b = qman_fq_fqid(rsp_fq);
-+	opts.fqd.context_a.hi = upper_32_bits(hwdesc);
-+	opts.fqd.context_a.lo = lower_32_bits(hwdesc);
- 	opts.fqd.cgid = qipriv.cgr.cgrid;
- 
- 	ret = qman_init_fq(req_fq, fq_sched_flag, &opts);
-@@ -207,7 +207,7 @@ static struct qman_fq *create_caam_req_f
- 	return req_fq;
- 
- init_req_fq_fail:
--	qman_destroy_fq(req_fq);
-+	qman_destroy_fq(req_fq, 0);
- create_req_fq_fail:
- 	kfree(req_fq);
- 	return ERR_PTR(ret);
-@@ -275,7 +275,7 @@ empty_fq:
- 	if (ret)
- 		dev_err(qidev, "OOS of FQID: %u failed\n", fq->fqid);
- 
--	qman_destroy_fq(fq);
-+	qman_destroy_fq(fq, 0);
- 	kfree(fq);
- 
- 	return ret;
-@@ -292,7 +292,7 @@ static int empty_caam_fq(struct qman_fq
- 		if (ret)
- 			return ret;
- 
--		if (!qm_mcr_np_get(&np, frm_cnt))
-+		if (!np.frm_cnt)
- 			break;
- 
- 		msleep(20);
-@@ -572,22 +572,27 @@ static enum qman_cb_dqrr_result caam_rsp
- 	struct caam_drv_req *drv_req;
- 	const struct qm_fd *fd;
- 	struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
--	u32 status;
- 
- 	if (caam_qi_napi_schedule(p, caam_napi))
- 		return qman_cb_dqrr_stop;
- 
- 	fd = &dqrr->fd;
--	status = be32_to_cpu(fd->status);
--	if (unlikely(status))
--		dev_err(qidev, "Error: %#x in CAAM response FD\n", status);
-+	if (unlikely(fd->status)) {
-+		u32 ssrc = fd->status & JRSTA_SSRC_MASK;
-+		u8 err_id = fd->status & JRSTA_CCBERR_ERRID_MASK;
-+
-+		if (ssrc != JRSTA_SSRC_CCB_ERROR ||
-+		    err_id != JRSTA_CCBERR_ERRID_ICVCHK)
-+			dev_err(qidev, "Error: %#x in CAAM response FD\n",
-+				fd->status);
-+	}
- 
--	if (unlikely(qm_fd_get_format(fd) != qm_fd_compound)) {
-+	if (unlikely(fd->format != qm_fd_compound)) {
- 		dev_err(qidev, "Non-compound FD from CAAM\n");
- 		return qman_cb_dqrr_consume;
- 	}
- 
--	drv_req = (struct caam_drv_req *)phys_to_virt(qm_fd_addr_get64(fd));
-+	drv_req = (struct caam_drv_req *)phys_to_virt(fd->addr);
- 	if (unlikely(!drv_req)) {
- 		dev_err(qidev,
- 			"Can't find original request for caam response\n");
-@@ -597,7 +602,7 @@ static enum qman_cb_dqrr_result caam_rsp
- 	dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
- 			 sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
- 
--	drv_req->cbk(drv_req, status);
-+	drv_req->cbk(drv_req, fd->status);
- 	return qman_cb_dqrr_consume;
- }
- 
-@@ -621,17 +626,18 @@ static int alloc_rsp_fq_cpu(struct devic
- 		return -ENODEV;
- 	}
- 
--	memset(&opts, 0, sizeof(opts));
--	opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
--				   QM_INITFQ_WE_CONTEXTB |
--				   QM_INITFQ_WE_CONTEXTA | QM_INITFQ_WE_CGID);
--	opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING |
--				       QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE);
--	qm_fqd_set_destwq(&opts.fqd, qman_affine_channel(cpu), 3);
-+	opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
-+		QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA |
-+		QM_INITFQ_WE_CGID;
-+	opts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING | QM_FQCTRL_CPCSTASH |
-+			   QM_FQCTRL_CGE;
-+	opts.fqd.dest.channel = qman_affine_channel(cpu);
-+	opts.fqd.dest.wq = 3;
- 	opts.fqd.cgid = qipriv.cgr.cgrid;
- 	opts.fqd.context_a.stashing.exclusive =	QM_STASHING_EXCL_CTX |
- 						QM_STASHING_EXCL_DATA;
--	qm_fqd_set_stashing(&opts.fqd, 0, 1, 1);
-+	opts.fqd.context_a.stashing.data_cl = 1;
-+	opts.fqd.context_a.stashing.context_cl = 1;
- 
- 	ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
- 	if (ret) {
-@@ -662,8 +668,7 @@ static int init_cgr(struct device *qidev
- 
- 	qipriv.cgr.cb = cgr_cb;
- 	memset(&opts, 0, sizeof(opts));
--	opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES |
--				   QM_CGR_WE_MODE);
-+	opts.we_mask = QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | QM_CGR_WE_MODE;
- 	opts.cgr.cscn_en = QM_CGR_EN;
- 	opts.cgr.mode = QMAN_CGR_MODE_FRAME;
- 	qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1);
---- a/drivers/crypto/caam/qi.h
-+++ b/drivers/crypto/caam/qi.h
-@@ -9,7 +9,7 @@
- #ifndef __QI_H__
- #define __QI_H__
- 
--#include <soc/fsl/qman.h>
-+#include <linux/fsl_qman.h>
- #include "compat.h"
- #include "desc.h"
- #include "desc_constr.h"
---- a/drivers/crypto/caam/regs.h
-+++ b/drivers/crypto/caam/regs.h
-@@ -627,6 +627,8 @@ struct caam_job_ring {
- #define JRSTA_DECOERR_INVSIGN       0x86
- #define JRSTA_DECOERR_DSASIGN       0x87
- 
-+#define JRSTA_QIERR_ERROR_MASK      0x00ff
-+
- #define JRSTA_CCBERR_JUMP           0x08000000
- #define JRSTA_CCBERR_INDEX_MASK     0xff00
- #define JRSTA_CCBERR_INDEX_SHIFT    8
---- a/drivers/crypto/caam/sg_sw_qm.h
-+++ b/drivers/crypto/caam/sg_sw_qm.h
-@@ -34,46 +34,61 @@
- #ifndef __SG_SW_QM_H
- #define __SG_SW_QM_H
- 
--#include <soc/fsl/qman.h>
-+#include <linux/fsl_qman.h>
- #include "regs.h"
- 
-+static inline void cpu_to_hw_sg(struct qm_sg_entry *qm_sg_ptr)
-+{
-+	dma_addr_t addr = qm_sg_ptr->opaque;
-+
-+	qm_sg_ptr->opaque = cpu_to_caam64(addr);
-+	qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl);
-+}
-+
- static inline void __dma_to_qm_sg(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma,
--				  u16 offset)
-+				  u32 len, u16 offset)
- {
--	qm_sg_entry_set64(qm_sg_ptr, dma);
-+	qm_sg_ptr->addr = dma;
-+	qm_sg_ptr->length = len;
- 	qm_sg_ptr->__reserved2 = 0;
- 	qm_sg_ptr->bpid = 0;
--	qm_sg_ptr->offset = cpu_to_be16(offset & QM_SG_OFF_MASK);
-+	qm_sg_ptr->__reserved3 = 0;
-+	qm_sg_ptr->offset = offset & QM_SG_OFFSET_MASK;
-+
-+	cpu_to_hw_sg(qm_sg_ptr);
- }
- 
- static inline void dma_to_qm_sg_one(struct qm_sg_entry *qm_sg_ptr,
- 				    dma_addr_t dma, u32 len, u16 offset)
- {
--	__dma_to_qm_sg(qm_sg_ptr, dma, offset);
--	qm_sg_entry_set_len(qm_sg_ptr, len);
-+	qm_sg_ptr->extension = 0;
-+	qm_sg_ptr->final = 0;
-+	__dma_to_qm_sg(qm_sg_ptr, dma, len, offset);
- }
- 
- static inline void dma_to_qm_sg_one_last(struct qm_sg_entry *qm_sg_ptr,
- 					 dma_addr_t dma, u32 len, u16 offset)
- {
--	__dma_to_qm_sg(qm_sg_ptr, dma, offset);
--	qm_sg_entry_set_f(qm_sg_ptr, len);
-+	qm_sg_ptr->extension = 0;
-+	qm_sg_ptr->final = 1;
-+	__dma_to_qm_sg(qm_sg_ptr, dma, len, offset);
- }
- 
- static inline void dma_to_qm_sg_one_ext(struct qm_sg_entry *qm_sg_ptr,
- 					dma_addr_t dma, u32 len, u16 offset)
- {
--	__dma_to_qm_sg(qm_sg_ptr, dma, offset);
--	qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | (len & QM_SG_LEN_MASK));
-+	qm_sg_ptr->extension = 1;
-+	qm_sg_ptr->final = 0;
-+	__dma_to_qm_sg(qm_sg_ptr, dma, len, offset);
- }
- 
- static inline void dma_to_qm_sg_one_last_ext(struct qm_sg_entry *qm_sg_ptr,
- 					     dma_addr_t dma, u32 len,
- 					     u16 offset)
- {
--	__dma_to_qm_sg(qm_sg_ptr, dma, offset);
--	qm_sg_ptr->cfg = cpu_to_be32(QM_SG_EXT | QM_SG_FIN |
--				     (len & QM_SG_LEN_MASK));
-+	qm_sg_ptr->extension = 1;
-+	qm_sg_ptr->final = 1;
-+	__dma_to_qm_sg(qm_sg_ptr, dma, len, offset);
- }
- 
- /*
-@@ -102,7 +117,10 @@ static inline void sg_to_qm_sg_last(stru
- 				    struct qm_sg_entry *qm_sg_ptr, u16 offset)
- {
- 	qm_sg_ptr = sg_to_qm_sg(sg, sg_count, qm_sg_ptr, offset);
--	qm_sg_entry_set_f(qm_sg_ptr, qm_sg_entry_get_len(qm_sg_ptr));
-+
-+	qm_sg_ptr->sgt_efl = caam32_to_cpu(qm_sg_ptr->sgt_efl);
-+	qm_sg_ptr->final = 1;
-+	qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl);
- }
- 
- #endif /* __SG_SW_QM_H */
---- a/drivers/crypto/talitos.c
-+++ b/drivers/crypto/talitos.c
-@@ -1241,6 +1241,14 @@ static int ipsec_esp(struct talitos_edes
- 	ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
- 				 sg_count, areq->assoclen, tbl_off, elen);
- 
-+	/*
-+	 * In case of SEC 2.x+, cipher in len must include only the ciphertext,
-+	 * while extent is used for ICV len.
-+	 */
-+	if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
-+	    (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
-+		desc->ptr[4].len = cpu_to_be16(cryptlen);
-+
- 	if (ret > 1) {
- 		tbl_off += ret;
- 		sync_needed = true;
diff --git a/target/linux/layerscape/patches-4.14/821-smmu-support-layerscape.patch b/target/linux/layerscape/patches-4.14/821-smmu-support-layerscape.patch
deleted file mode 100644
index e0daa4334..000000000
--- a/target/linux/layerscape/patches-4.14/821-smmu-support-layerscape.patch
+++ /dev/null
@@ -1,506 +0,0 @@
-From 05375244c8e74f90239db92646a771905fdfc0db Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:28:22 +0800
-Subject: [PATCH 38/40] smmu: support layerscape
-This is an integrated patch of smmu for layerscape
-
-Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
-Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- .../devicetree/bindings/misc/fsl,qoriq-mc.txt |  39 ++++++
- drivers/iommu/arm-smmu.c                      |   7 +
- drivers/iommu/iommu.c                         |  21 +++
- drivers/iommu/of_iommu.c                      | 126 +++++++++++++++++-
- drivers/of/irq.c                              |   6 +-
- drivers/of/of_pci.c                           | 101 --------------
- include/linux/iommu.h                         |   2 +
- include/linux/of_iommu.h                      |  10 ++
- include/linux/of_pci.h                        |  10 --
- 9 files changed, 205 insertions(+), 117 deletions(-)
-
---- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
-+++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
-@@ -9,6 +9,25 @@ blocks that can be used to create functi
- such as network interfaces, crypto accelerator instances, L2 switches,
- etc.
- 
-+For an overview of the DPAA2 architecture and fsl-mc bus see:
-+drivers/staging/fsl-mc/README.txt
-+
-+As described in the above overview, all DPAA2 objects in a DPRC share the
-+same hardware "isolation context" and a 10-bit value called an ICID
-+(isolation context id) is expressed by the hardware to identify
-+the requester.
-+
-+The generic 'iommus' property is insufficient to describe the relationship
-+between ICIDs and IOMMUs, so an iommu-map property is used to define
-+the set of possible ICIDs under a root DPRC and how they map to
-+an IOMMU.
-+
-+For generic IOMMU bindings, see
-+Documentation/devicetree/bindings/iommu/iommu.txt.
-+
-+For arm-smmu binding, see:
-+Documentation/devicetree/bindings/iommu/arm,smmu.txt.
-+
- Required properties:
- 
-     - compatible
-@@ -88,14 +107,34 @@ Sub-nodes:
-               Value type: <phandle>
-               Definition: Specifies the phandle to the PHY device node associated
-                           with the this dpmac.
-+Optional properties:
-+
-+- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier
-+  data.
-+
-+  The property is an arbitrary number of tuples of
-+  (icid-base,iommu,iommu-base,length).
-+
-+  Any ICID i in the interval [icid-base, icid-base + length) is
-+  associated with the listed IOMMU, with the iommu-specifier
-+  (i - icid-base + iommu-base).
- 
- Example:
- 
-+        smmu: iommu@5000000 {
-+               compatible = "arm,mmu-500";
-+               #iommu-cells = <2>;
-+               stream-match-mask = <0x7C00>;
-+               ...
-+        };
-+
-         fsl_mc: fsl-mc@80c000000 {
-                 compatible = "fsl,qoriq-mc";
-                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
-                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
-                 msi-parent = <&its>;
-+                /* define map for ICIDs 23-64 */
-+                iommu-map = <23 &smmu 23 41>;
-                 #address-cells = <3>;
-                 #size-cells = <1>;
- 
---- a/drivers/iommu/arm-smmu.c
-+++ b/drivers/iommu/arm-smmu.c
-@@ -52,6 +52,7 @@
- #include <linux/spinlock.h>
- 
- #include <linux/amba/bus.h>
-+#include <linux/fsl/mc.h>
- 
- #include "io-pgtable.h"
- #include "arm-smmu-regs.h"
-@@ -1464,6 +1465,8 @@ static struct iommu_group *arm_smmu_devi
- 
- 	if (dev_is_pci(dev))
- 		group = pci_device_group(dev);
-+	else if (dev_is_fsl_mc(dev))
-+		group = fsl_mc_device_group(dev);
- 	else
- 		group = generic_device_group(dev);
- 
-@@ -2040,6 +2043,10 @@ static void arm_smmu_bus_init(void)
- 		bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
- 	}
- #endif
-+#ifdef CONFIG_FSL_MC_BUS
-+	if (!iommu_present(&fsl_mc_bus_type))
-+		bus_set_iommu(&fsl_mc_bus_type, &arm_smmu_ops);
-+#endif
- }
- 
- static int arm_smmu_device_probe(struct platform_device *pdev)
---- a/drivers/iommu/iommu.c
-+++ b/drivers/iommu/iommu.c
-@@ -33,6 +33,7 @@
- #include <linux/bitops.h>
- #include <linux/property.h>
- #include <trace/events/iommu.h>
-+#include <linux/fsl/mc.h>
- 
- static struct kset *iommu_group_kset;
- static DEFINE_IDA(iommu_group_ida);
-@@ -987,6 +988,26 @@ struct iommu_group *pci_device_group(str
- 	return iommu_group_alloc();
- }
- 
-+/* Get the IOMMU group for device on fsl-mc bus */
-+struct iommu_group *fsl_mc_device_group(struct device *dev)
-+{
-+	struct device *cont_dev = fsl_mc_cont_dev(dev);
-+	struct iommu_group *group;
-+
-+	/* Container device is responsible for creating the iommu group */
-+	if (fsl_mc_is_cont_dev(dev)) {
-+		group = iommu_group_alloc();
-+		if (IS_ERR(group))
-+			return NULL;
-+	} else {
-+		get_device(cont_dev);
-+		group = iommu_group_get(cont_dev);
-+		put_device(cont_dev);
-+	}
-+
-+	return group;
-+}
-+
- /**
-  * iommu_group_get_for_dev - Find or create the IOMMU group for a device
-  * @dev: target device
---- a/drivers/iommu/of_iommu.c
-+++ b/drivers/iommu/of_iommu.c
-@@ -24,6 +24,7 @@
- #include <linux/of_iommu.h>
- #include <linux/of_pci.h>
- #include <linux/slab.h>
-+#include <linux/fsl/mc.h>
- 
- #define NO_IOMMU	1
- 
-@@ -143,15 +144,115 @@ struct of_pci_iommu_alias_info {
- 	struct device_node *np;
- };
- 
-+/**
-+ * of_map_rid - Translate a requester ID through a downstream mapping.
-+ * @np: root complex device node.
-+ * @rid: Requester ID to map.
-+ * @map_name: property name of the map to use.
-+ * @map_mask_name: optional property name of the mask to use.
-+ * @target: optional pointer to a target device node.
-+ * @id_out: optional pointer to receive the translated ID.
-+ *
-+ * Given PCI/MC requester ID, look up the appropriate implementation-defined
-+ * platform ID and/or the target device which receives transactions on that
-+ * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or
-+ * @id_out may be NULL if only the other is required. If @target points to
-+ * a non-NULL device node pointer, only entries targeting that node will be
-+ * matched; if it points to a NULL value, it will receive the device node of
-+ * the first matching target phandle, with a reference held.
-+ *
-+ * Return: 0 on success or a standard error code on failure.
-+ */
-+int of_map_rid(struct device_node *np, u32 rid,
-+	       const char *map_name, const char *map_mask_name,
-+	       struct device_node **target, u32 *id_out)
-+{
-+	u32 map_mask, masked_rid;
-+	int map_len;
-+	const __be32 *map = NULL;
-+
-+	if (!np || !map_name || (!target && !id_out))
-+		return -EINVAL;
-+
-+	map = of_get_property(np, map_name, &map_len);
-+	if (!map) {
-+		if (target)
-+			return -ENODEV;
-+		/* Otherwise, no map implies no translation */
-+		*id_out = rid;
-+		return 0;
-+	}
-+
-+	if (!map_len || map_len % (4 * sizeof(*map))) {
-+		pr_err("%pOF: Error: Bad %s length: %d\n", np,
-+			map_name, map_len);
-+		return -EINVAL;
-+	}
-+
-+	/* The default is to select all bits. */
-+	map_mask = 0xffffffff;
-+
-+	/*
-+	 * Can be overridden by "{iommu,msi}-map-mask" property.
-+	 * If of_property_read_u32() fails, the default is used.
-+	 */
-+	if (map_mask_name)
-+		of_property_read_u32(np, map_mask_name, &map_mask);
-+
-+	masked_rid = map_mask & rid;
-+	for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) {
-+		struct device_node *phandle_node;
-+		u32 rid_base = be32_to_cpup(map + 0);
-+		u32 phandle = be32_to_cpup(map + 1);
-+		u32 out_base = be32_to_cpup(map + 2);
-+		u32 rid_len = be32_to_cpup(map + 3);
-+
-+		if (rid_base & ~map_mask) {
-+			pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores rid-base (0x%x)\n",
-+				np, map_name, map_name,
-+				map_mask, rid_base);
-+			return -EFAULT;
-+		}
-+
-+		if (masked_rid < rid_base || masked_rid >= rid_base + rid_len)
-+			continue;
-+
-+		phandle_node = of_find_node_by_phandle(phandle);
-+		if (!phandle_node)
-+			return -ENODEV;
-+
-+		if (target) {
-+			if (*target)
-+				of_node_put(phandle_node);
-+			else
-+				*target = phandle_node;
-+
-+			if (*target != phandle_node)
-+				continue;
-+		}
-+
-+		if (id_out)
-+			*id_out = masked_rid - rid_base + out_base;
-+
-+		pr_debug("%pOF: %s, using mask %08x, rid-base: %08x, out-base: %08x, length: %08x, rid: %08x -> %08x\n",
-+			np, map_name, map_mask, rid_base, out_base,
-+			rid_len, rid, *id_out);
-+		return 0;
-+	}
-+
-+	pr_err("%pOF: Invalid %s translation - no match for rid 0x%x on %pOF\n",
-+		np, map_name, rid, target && *target ? *target : NULL);
-+	return -EFAULT;
-+}
- static int of_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data)
- {
- 	struct of_pci_iommu_alias_info *info = data;
- 	struct of_phandle_args iommu_spec = { .args_count = 1 };
- 	int err;
- 
--	err = of_pci_map_rid(info->np, alias, "iommu-map",
--			     "iommu-map-mask", &iommu_spec.np,
--			     iommu_spec.args);
-+	err = of_map_rid(info->np, alias, "iommu-map",
-+			 "iommu-map-mask", &iommu_spec.np,
-+			 iommu_spec.args);
- 	if (err)
- 		return err == -ENODEV ? NO_IOMMU : err;
- 
-@@ -160,6 +261,23 @@ static int of_pci_iommu_init(struct pci_
- 	return err;
- }
- 
-+static int of_fsl_mc_iommu_init(struct fsl_mc_device *mc_dev,
-+				struct device_node *master_np)
-+{
-+	struct of_phandle_args iommu_spec = { .args_count = 1 };
-+	int err;
-+
-+	err = of_map_rid(master_np, mc_dev->icid, "iommu-map",
-+			 "iommu-map-mask", &iommu_spec.np,
-+			 iommu_spec.args);
-+	if (err)
-+		return err == -ENODEV ? NO_IOMMU : err;
-+
-+	err = of_iommu_xlate(&mc_dev->dev, &iommu_spec);
-+	of_node_put(iommu_spec.np);
-+	return err;
-+}
-+
- const struct iommu_ops *of_iommu_configure(struct device *dev,
- 					   struct device_node *master_np)
- {
-@@ -191,6 +309,8 @@ const struct iommu_ops *of_iommu_configu
- 
- 		err = pci_for_each_dma_alias(to_pci_dev(dev),
- 					     of_pci_iommu_init, &info);
-+	} else if (dev_is_fsl_mc(dev)) {
-+		err = of_fsl_mc_iommu_init(to_fsl_mc_device(dev), master_np);
- 	} else {
- 		struct of_phandle_args iommu_spec;
- 		int idx = 0;
---- a/drivers/of/irq.c
-+++ b/drivers/of/irq.c
-@@ -26,7 +26,7 @@
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/of_irq.h>
--#include <linux/of_pci.h>
-+#include <linux/of_iommu.h>
- #include <linux/string.h>
- #include <linux/slab.h>
- 
-@@ -593,8 +593,8 @@ static u32 __of_msi_map_rid(struct devic
- 	 * "msi-map" property.
- 	 */
- 	for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent)
--		if (!of_pci_map_rid(parent_dev->of_node, rid_in, "msi-map",
--				    "msi-map-mask", np, &rid_out))
-+		if (!of_map_rid(parent_dev->of_node, rid_in, "msi-map",
-+				"msi-map-mask", np, &rid_out))
- 			break;
- 	return rid_out;
- }
---- a/drivers/of/of_pci.c
-+++ b/drivers/of/of_pci.c
-@@ -281,104 +281,3 @@ parse_failed:
- }
- EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
- #endif /* CONFIG_OF_ADDRESS */
--
--/**
-- * of_pci_map_rid - Translate a requester ID through a downstream mapping.
-- * @np: root complex device node.
-- * @rid: PCI requester ID to map.
-- * @map_name: property name of the map to use.
-- * @map_mask_name: optional property name of the mask to use.
-- * @target: optional pointer to a target device node.
-- * @id_out: optional pointer to receive the translated ID.
-- *
-- * Given a PCI requester ID, look up the appropriate implementation-defined
-- * platform ID and/or the target device which receives transactions on that
-- * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or
-- * @id_out may be NULL if only the other is required. If @target points to
-- * a non-NULL device node pointer, only entries targeting that node will be
-- * matched; if it points to a NULL value, it will receive the device node of
-- * the first matching target phandle, with a reference held.
-- *
-- * Return: 0 on success or a standard error code on failure.
-- */
--int of_pci_map_rid(struct device_node *np, u32 rid,
--		   const char *map_name, const char *map_mask_name,
--		   struct device_node **target, u32 *id_out)
--{
--	u32 map_mask, masked_rid;
--	int map_len;
--	const __be32 *map = NULL;
--
--	if (!np || !map_name || (!target && !id_out))
--		return -EINVAL;
--
--	map = of_get_property(np, map_name, &map_len);
--	if (!map) {
--		if (target)
--			return -ENODEV;
--		/* Otherwise, no map implies no translation */
--		*id_out = rid;
--		return 0;
--	}
--
--	if (!map_len || map_len % (4 * sizeof(*map))) {
--		pr_err("%pOF: Error: Bad %s length: %d\n", np,
--			map_name, map_len);
--		return -EINVAL;
--	}
--
--	/* The default is to select all bits. */
--	map_mask = 0xffffffff;
--
--	/*
--	 * Can be overridden by "{iommu,msi}-map-mask" property.
--	 * If of_property_read_u32() fails, the default is used.
--	 */
--	if (map_mask_name)
--		of_property_read_u32(np, map_mask_name, &map_mask);
--
--	masked_rid = map_mask & rid;
--	for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) {
--		struct device_node *phandle_node;
--		u32 rid_base = be32_to_cpup(map + 0);
--		u32 phandle = be32_to_cpup(map + 1);
--		u32 out_base = be32_to_cpup(map + 2);
--		u32 rid_len = be32_to_cpup(map + 3);
--
--		if (rid_base & ~map_mask) {
--			pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores rid-base (0x%x)\n",
--				np, map_name, map_name,
--				map_mask, rid_base);
--			return -EFAULT;
--		}
--
--		if (masked_rid < rid_base || masked_rid >= rid_base + rid_len)
--			continue;
--
--		phandle_node = of_find_node_by_phandle(phandle);
--		if (!phandle_node)
--			return -ENODEV;
--
--		if (target) {
--			if (*target)
--				of_node_put(phandle_node);
--			else
--				*target = phandle_node;
--
--			if (*target != phandle_node)
--				continue;
--		}
--
--		if (id_out)
--			*id_out = masked_rid - rid_base + out_base;
--
--		pr_debug("%pOF: %s, using mask %08x, rid-base: %08x, out-base: %08x, length: %08x, rid: %08x -> %08x\n",
--			np, map_name, map_mask, rid_base, out_base,
--			rid_len, rid, *id_out);
--		return 0;
--	}
--
--	pr_err("%pOF: Invalid %s translation - no match for rid 0x%x on %pOF\n",
--		np, map_name, rid, target && *target ? *target : NULL);
--	return -EFAULT;
--}
---- a/include/linux/iommu.h
-+++ b/include/linux/iommu.h
-@@ -389,6 +389,8 @@ static inline size_t iommu_map_sg(struct
- extern struct iommu_group *pci_device_group(struct device *dev);
- /* Generic device grouping function */
- extern struct iommu_group *generic_device_group(struct device *dev);
-+/* FSL-MC device grouping function */
-+struct iommu_group *fsl_mc_device_group(struct device *dev);
- 
- /**
-  * struct iommu_fwspec - per-device IOMMU instance data
---- a/include/linux/of_iommu.h
-+++ b/include/linux/of_iommu.h
-@@ -15,6 +15,9 @@ extern int of_get_dma_window(struct devi
- extern const struct iommu_ops *of_iommu_configure(struct device *dev,
- 					struct device_node *master_np);
- 
-+int of_map_rid(struct device_node *np, u32 rid,
-+	       const char *map_name, const char *map_mask_name,
-+	       struct device_node **target, u32 *id_out);
- #else
- 
- static inline int of_get_dma_window(struct device_node *dn, const char *prefix,
-@@ -30,6 +33,13 @@ static inline const struct iommu_ops *of
- 	return NULL;
- }
- 
-+static inline int of_map_rid(struct device_node *np, u32 rid,
-+			const char *map_name, const char *map_mask_name,
-+			struct device_node **target, u32 *id_out)
-+{
-+	return -EINVAL;
-+}
-+
- #endif	/* CONFIG_OF_IOMMU */
- 
- extern struct of_device_id __iommu_of_table;
---- a/include/linux/of_pci.h
-+++ b/include/linux/of_pci.h
-@@ -19,9 +19,6 @@ int of_pci_parse_bus_range(struct device
- int of_get_pci_domain_nr(struct device_node *node);
- int of_pci_get_max_link_speed(struct device_node *node);
- void of_pci_check_probe_only(void);
--int of_pci_map_rid(struct device_node *np, u32 rid,
--		   const char *map_name, const char *map_mask_name,
--		   struct device_node **target, u32 *id_out);
- #else
- static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
- {
-@@ -57,13 +54,6 @@ of_get_pci_domain_nr(struct device_node
- 	return -1;
- }
- 
--static inline int of_pci_map_rid(struct device_node *np, u32 rid,
--			const char *map_name, const char *map_mask_name,
--			struct device_node **target, u32 *id_out)
--{
--	return -EINVAL;
--}
--
- static inline int
- of_pci_get_max_link_speed(struct device_node *node)
- {
diff --git a/target/linux/layerscape/patches-4.14/822-uart-support-layerscape.patch b/target/linux/layerscape/patches-4.14/822-uart-support-layerscape.patch
deleted file mode 100644
index fa6779caa..000000000
--- a/target/linux/layerscape/patches-4.14/822-uart-support-layerscape.patch
+++ /dev/null
@@ -1,52 +0,0 @@
-From 558ca1294aa2bf7f29d55361d2f18c6dc534e1d6 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:28:33 +0800
-Subject: [PATCH 39/40] uart: support layerscape
-This is an integrated patch of uart for layerscape
-
-Signed-off-by: Sriram Dash <Sriram.dash@nxp.com>
-Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
----
- drivers/tty/serial/fsl_lpuart.c | 15 +++++++++------
- 1 file changed, 9 insertions(+), 6 deletions(-)
-
---- a/drivers/tty/serial/fsl_lpuart.c
-+++ b/drivers/tty/serial/fsl_lpuart.c
-@@ -236,6 +236,8 @@
- /* IMX lpuart has four extra unused regs located at the beginning */
- #define IMX_REG_OFF	0x10
- 
-+static DECLARE_BITMAP(linemap, UART_NR);
-+
- struct lpuart_port {
- 	struct uart_port	port;
- 	struct clk		*clk;
-@@ -2149,13 +2151,13 @@ static int lpuart_probe(struct platform_
- 
- 	ret = of_alias_get_id(np, "serial");
- 	if (ret < 0) {
--		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
--		return ret;
--	}
--	if (ret >= ARRAY_SIZE(lpuart_ports)) {
--		dev_err(&pdev->dev, "serial%d out of range\n", ret);
--		return -EINVAL;
-+		ret = find_first_zero_bit(linemap, UART_NR);
-+		if (ret >= UART_NR) {
-+			dev_err(&pdev->dev, "port line is full, add device failed\n");
-+			return ret;
-+		}
- 	}
-+	set_bit(ret, linemap);
- 	sport->port.line = ret;
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
-@@ -2246,6 +2248,7 @@ static int lpuart_remove(struct platform
- 	struct lpuart_port *sport = platform_get_drvdata(pdev);
- 
- 	uart_remove_one_port(&lpuart_reg, &sport->port);
-+	clear_bit(sport->port.line, linemap);
- 
- 	clk_disable_unprepare(sport->clk);
- 
diff --git a/target/linux/layerscape/patches-4.14/824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch b/target/linux/layerscape/patches-4.14/824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch
deleted file mode 100644
index 944488221..000000000
--- a/target/linux/layerscape/patches-4.14/824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From bb7412794db9b48dc4cc041c75d380e512dfff2a Mon Sep 17 00:00:00 2001
-From: Mathew McBride <matt@traverse.com.au>
-Date: Tue, 20 Nov 2018 14:36:54 +0800
-Subject: [PATCH] mmc: sdhci-of-esdhc: add voltage switch support for ls1043a
-
-Added voltage switch support for ls1043a.
-
-Signed-off-by: Mathew McBride <matt@traverse.com.au>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
----
- drivers/mmc/host/sdhci-of-esdhc.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mmc/host/sdhci-of-esdhc.c
-+++ b/drivers/mmc/host/sdhci-of-esdhc.c
-@@ -650,6 +650,7 @@ static void esdhc_reset(struct sdhci_hos
- static const struct of_device_id scfg_device_ids[] = {
- 	{ .compatible = "fsl,t1040-scfg", },
- 	{ .compatible = "fsl,ls1012a-scfg", },
-+	{ .compatible = "fsl,ls1043a-scfg", },
- 	{ .compatible = "fsl,ls1046a-scfg", },
- 	{}
- };
diff --git a/target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch b/target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch
new file mode 100644
index 000000000..ea3cc702d
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch
@@ -0,0 +1,374 @@
+From 0774b97305507af18f8c43efb69aa00e6c57ae90 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Fri, 6 Jul 2018 15:31:14 +0800
+Subject: [PATCH] config: support layerscape
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is an integrated patch for layerscape config/makefile support.
+
+Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
+Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ arch/arm/mach-imx/Kconfig               |  1 +
+ drivers/base/Kconfig                    |  1 +
+ drivers/crypto/Makefile                 |  2 +-
+ drivers/net/ethernet/freescale/Kconfig  |  4 +-
+ drivers/net/ethernet/freescale/Makefile |  2 +
+ drivers/ptp/Kconfig                     | 29 +++++++++++
+ drivers/rtc/Kconfig                     |  8 +++
+ drivers/rtc/Makefile                    |  1 +
+ drivers/soc/Kconfig                     |  3 +-
+ drivers/soc/fsl/Kconfig                 | 30 ++++++++++++
+ drivers/soc/fsl/Kconfig.arm             | 16 ++++++
+ drivers/soc/fsl/Makefile                |  5 ++
+ drivers/soc/fsl/layerscape/Kconfig      | 10 ++++
+ drivers/soc/fsl/layerscape/Makefile     |  1 +
+ drivers/staging/Kconfig                 |  6 +++
+ drivers/staging/Makefile                |  3 ++
+ drivers/staging/fsl-dpaa2/Kconfig       | 65 +++++++++++++++++++++++++
+ drivers/staging/fsl-dpaa2/Makefile      |  9 ++++
+ 18 files changed, 192 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/soc/fsl/Kconfig
+ create mode 100644 drivers/soc/fsl/Kconfig.arm
+ create mode 100644 drivers/soc/fsl/layerscape/Kconfig
+ create mode 100644 drivers/soc/fsl/layerscape/Makefile
+ create mode 100644 drivers/staging/fsl-dpaa2/Kconfig
+ create mode 100644 drivers/staging/fsl-dpaa2/Makefile
+
+--- a/arch/arm/mach-imx/Kconfig
++++ b/arch/arm/mach-imx/Kconfig
+@@ -1,6 +1,7 @@
+ menuconfig ARCH_MXC
+ 	bool "Freescale i.MX family"
+ 	depends on ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
++	select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+ 	select ARCH_SUPPORTS_BIG_ENDIAN
+ 	select CLKSRC_IMX_GPT
+ 	select GENERIC_IRQ_CHIP
+--- a/drivers/base/Kconfig
++++ b/drivers/base/Kconfig
+@@ -240,6 +240,7 @@ config GENERIC_CPU_VULNERABILITIES
+ 
+ config SOC_BUS
+ 	bool
++	select GLOB
+ 
+ source "drivers/base/regmap/Kconfig"
+ 
+--- a/drivers/crypto/Makefile
++++ b/drivers/crypto/Makefile
+@@ -3,7 +3,7 @@ obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += at
+ obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
+ obj-$(CONFIG_CRYPTO_DEV_BFIN_CRC) += bfin_crc.o
+ obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/
+-obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON) += caam/
+ obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
+ obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
+ obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
+--- a/drivers/net/ethernet/freescale/Kconfig
++++ b/drivers/net/ethernet/freescale/Kconfig
+@@ -5,7 +5,7 @@
+ config NET_VENDOR_FREESCALE
+ 	bool "Freescale devices"
+ 	default y
+-	depends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \
++	depends on FSL_SOC || (QUICC_ENGINE && PPC32) || CPM1 || CPM2 || PPC_MPC512x || \
+ 		   M523x || M527x || M5272 || M528x || M520x || M532x || \
+ 		   ARCH_MXC || ARCH_MXS || (PPC_MPC52xx && PPC_BESTCOMM) || \
+ 		   ARCH_LAYERSCAPE
+@@ -93,4 +93,6 @@ config GIANFAR
+ 	  and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
+ 	  on the 8540.
+ 
++source "drivers/net/ethernet/freescale/sdk_fman/Kconfig"
++source "drivers/net/ethernet/freescale/sdk_dpaa/Kconfig"
+ endif # NET_VENDOR_FREESCALE
+--- a/drivers/net/ethernet/freescale/Makefile
++++ b/drivers/net/ethernet/freescale/Makefile
+@@ -21,4 +21,6 @@ gianfar_driver-objs := gianfar.o \
+ obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
+ ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
+ 
++obj-$(if $(CONFIG_FSL_SDK_FMAN),y) += sdk_fman/
++obj-$(if $(CONFIG_FSL_SDK_DPAA_ETH),y) += sdk_dpaa/
+ obj-$(CONFIG_FSL_FMAN) += fman/
+--- a/drivers/ptp/Kconfig
++++ b/drivers/ptp/Kconfig
+@@ -39,6 +39,35 @@ config PTP_1588_CLOCK_GIANFAR
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called gianfar_ptp.
+ 
++config PTP_1588_CLOCK_DPAA
++	tristate "Freescale DPAA as PTP clock"
++	depends on FSL_SDK_DPAA_ETH
++	select PTP_1588_CLOCK
++        select FSL_DPAA_TS
++        default n
++	help
++	  This driver adds support for using the DPAA 1588 timer module
++	  as a PTP clock. This clock is only useful if your PTP programs are
++	  getting hardware time stamps on the PTP Ethernet packets
++	  using the SO_TIMESTAMPING API.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called dpaa_ptp.
++
++config PTP_1588_CLOCK_DPAA2
++	tristate "Freescale DPAA2 as PTP clock"
++	depends on FSL_DPAA2_ETH
++	select PTP_1588_CLOCK
++	default y
++	help
++	  This driver adds support for using the DPAA2 1588 timer module
++	  as a PTP clock. This clock is only useful if your PTP programs are
++	  getting hardware time stamps on the PTP Ethernet packets
++	  using the SO_TIMESTAMPING API.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called dpaa2-rtc.
++
+ config PTP_1588_CLOCK_IXP46X
+ 	tristate "Intel IXP46x as PTP clock"
+ 	depends on IXP4XX_ETH
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -414,6 +414,14 @@ config RTC_DRV_PCF85063
+ 	  This driver can also be built as a module. If so, the module
+ 	  will be called rtc-pcf85063.
+ 
++config RTC_DRV_PCF85263
++	tristate "NXP PCF85263"
++	help
++	  If you say yes here you get support for the PCF85263 RTC chip
++
++	  This driver can also be built as a module. If so, the module
++	  will be called rtc-pcf85263.
++
+ config RTC_DRV_PCF8563
+ 	tristate "Philips PCF8563/Epson RTC8564"
+ 	help
+--- a/drivers/rtc/Makefile
++++ b/drivers/rtc/Makefile
+@@ -111,6 +111,7 @@ obj-$(CONFIG_RTC_DRV_PCF2127)	+= rtc-pcf
+ obj-$(CONFIG_RTC_DRV_PCF50633)	+= rtc-pcf50633.o
+ obj-$(CONFIG_RTC_DRV_PCF85063)	+= rtc-pcf85063.o
+ obj-$(CONFIG_RTC_DRV_PCF8523)	+= rtc-pcf8523.o
++obj-$(CONFIG_RTC_DRV_PCF85263)	+= rtc-pcf85263.o
+ obj-$(CONFIG_RTC_DRV_PCF8563)	+= rtc-pcf8563.o
+ obj-$(CONFIG_RTC_DRV_PCF8583)	+= rtc-pcf8583.o
+ obj-$(CONFIG_RTC_DRV_PIC32)	+= rtc-pic32.o
+--- a/drivers/soc/Kconfig
++++ b/drivers/soc/Kconfig
+@@ -1,8 +1,7 @@
+ menu "SOC (System On Chip) specific Drivers"
+ 
+ source "drivers/soc/bcm/Kconfig"
+-source "drivers/soc/fsl/qbman/Kconfig"
+-source "drivers/soc/fsl/qe/Kconfig"
++source "drivers/soc/fsl/Kconfig"
+ source "drivers/soc/mediatek/Kconfig"
+ source "drivers/soc/qcom/Kconfig"
+ source "drivers/soc/rockchip/Kconfig"
+--- /dev/null
++++ b/drivers/soc/fsl/Kconfig
+@@ -0,0 +1,30 @@
++#
++# Freescale SOC drivers
++#
++
++source "drivers/soc/fsl/qbman/Kconfig"
++source "drivers/soc/fsl/qe/Kconfig"
++source "drivers/soc/fsl/ls2-console/Kconfig"
++
++config FSL_GUTS
++	bool
++	select SOC_BUS
++	help
++	  The global utilities block controls power management, I/O device
++	  enabling, power-onreset(POR) configuration monitoring, alternate
++	  function selection for multiplexed signals,and clock control.
++	  This driver is to manage and access global utilities block.
++	  Initially only reading SVR and registering soc device are supported.
++	  Other guts accesses, such as reading RCW, should eventually be moved
++	  into this driver as well.
++
++config FSL_SLEEP_FSM
++	bool
++	help
++	  This driver configures a hardware FSM (Finite State Machine) for deep sleep.
++	  The FSM is used to finish clean-ups at the last stage of system entering deep
++	  sleep, and also wakes up system when a wake up event happens.
++
++if ARM || ARM64
++source "drivers/soc/fsl/Kconfig.arm"
++endif
+--- /dev/null
++++ b/drivers/soc/fsl/Kconfig.arm
+@@ -0,0 +1,16 @@
++#
++# Freescale ARM SOC Drivers
++#
++
++config LS_SOC_DRIVERS
++	bool "Layerscape Soc Drivers"
++	depends on ARCH_LAYERSCAPE || SOC_LS1021A
++	default n
++	help
++	Say y here to enable Freescale Layerscape Soc Device Drivers support.
++	The Soc Drivers provides the device driver that is a specific block
++	or feature on Layerscape platform.
++
++if LS_SOC_DRIVERS
++	source "drivers/soc/fsl/layerscape/Kconfig"
++endif
+--- a/drivers/soc/fsl/Makefile
++++ b/drivers/soc/fsl/Makefile
+@@ -5,3 +5,8 @@
+ obj-$(CONFIG_FSL_DPAA)                 += qbman/
+ obj-$(CONFIG_QUICC_ENGINE)		+= qe/
+ obj-$(CONFIG_CPM)			+= qe/
++obj-$(CONFIG_FSL_GUTS)			+= guts.o
++obj-$(CONFIG_FSL_LS2_CONSOLE)		+= ls2-console/
++obj-$(CONFIG_SUSPEND)			+= rcpm.o
++obj-$(CONFIG_LS_SOC_DRIVERS)		+= layerscape/
++obj-$(CONFIG_FSL_SLEEP_FSM)	+= sleep_fsm.o
+--- /dev/null
++++ b/drivers/soc/fsl/layerscape/Kconfig
+@@ -0,0 +1,10 @@
++#
++# Layerscape Soc drivers
++#
++config  FTM_ALARM
++	bool "FTM alarm driver"
++	default n
++	help
++	Say y here to enable FTM alarm support.  The FTM alarm provides
++	alarm functions for wakeup system from deep sleep.  There is only
++	one FTM can be used in ALARM(FTM 0).
+--- /dev/null
++++ b/drivers/soc/fsl/layerscape/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_FTM_ALARM) += ftm_alarm.o
+--- a/drivers/staging/Kconfig
++++ b/drivers/staging/Kconfig
+@@ -94,6 +94,8 @@ source "drivers/staging/fbtft/Kconfig"
+ 
+ source "drivers/staging/fsl-mc/Kconfig"
+ 
++source "drivers/staging/fsl-dpaa2/Kconfig"
++
+ source "drivers/staging/wilc1000/Kconfig"
+ 
+ source "drivers/staging/most/Kconfig"
+@@ -106,4 +108,8 @@ source "drivers/staging/greybus/Kconfig"
+ 
+ source "drivers/staging/vc04_services/Kconfig"
+ 
++source "drivers/staging/fsl_qbman/Kconfig"
++
++source "drivers/staging/fsl_ppfe/Kconfig"
++
+ endif # STAGING
+--- a/drivers/staging/Makefile
++++ b/drivers/staging/Makefile
+@@ -36,9 +36,12 @@ obj-$(CONFIG_UNISYSSPAR)	+= unisys/
+ obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD)	+= clocking-wizard/
+ obj-$(CONFIG_FB_TFT)		+= fbtft/
+ obj-$(CONFIG_FSL_MC_BUS)	+= fsl-mc/
++obj-$(CONFIG_FSL_DPAA2)		+= fsl-dpaa2/
+ obj-$(CONFIG_WILC1000)		+= wilc1000/
+ obj-$(CONFIG_MOST)		+= most/
+ obj-$(CONFIG_ISDN_I4L)		+= i4l/
+ obj-$(CONFIG_KS7010)		+= ks7010/
+ obj-$(CONFIG_GREYBUS)		+= greybus/
+ obj-$(CONFIG_BCM2708_VCHIQ)	+= vc04_services/
++obj-$(CONFIG_FSL_SDK_DPA)	+= fsl_qbman/
++obj-$(CONFIG_FSL_PPFE)		+= fsl_ppfe/
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/Kconfig
+@@ -0,0 +1,65 @@
++#
++# Freescale DataPath Acceleration Architecture Gen2 (DPAA2) drivers
++#
++
++config FSL_DPAA2
++	bool "Freescale DPAA2 devices"
++	depends on FSL_MC_BUS
++	---help---
++	  Build drivers for Freescale DataPath Acceleration
++	  Architecture (DPAA2) family of SoCs.
++
++config FSL_DPAA2_ETH
++	tristate "Freescale DPAA2 Ethernet"
++	depends on FSL_DPAA2 && FSL_MC_DPIO
++	---help---
++	  Ethernet driver for Freescale DPAA2 SoCs, using the
++	  Freescale MC bus driver
++
++if FSL_DPAA2_ETH
++config FSL_DPAA2_ETH_USE_ERR_QUEUE
++	bool "Enable Rx error queue"
++	default n
++	---help---
++	  Allow Rx error frames to be enqueued on an error queue
++	  and processed by the driver (by default they are dropped
++	  in hardware).
++	  This may impact performance, recommended for debugging
++	  purposes only.
++
++# QBMAN_DEBUG requires some additional DPIO APIs
++config FSL_DPAA2_ETH_DEBUGFS
++	depends on DEBUG_FS
++	bool "Enable debugfs support"
++	default n
++	---help---
++	  Enable advanced statistics through debugfs interface.
++
++config FSL_DPAA2_ETH_DCB
++        bool "Data Center Bridging (DCB) Support"
++        default n
++        depends on DCB
++        ---help---
++          Say Y here if you want to use Data Center Bridging (DCB) features
++          (PFC) in the driver.
++
++          If unsure, say N.
++
++config FSL_DPAA2_ETH_CEETM
++	depends on NET_SCHED
++	bool "DPAA2 Ethernet CEETM QoS"
++	default n
++	---help---
++	  Enable QoS offloading support through the CEETM hardware block.
++endif
++
++source "drivers/staging/fsl-dpaa2/mac/Kconfig"
++source "drivers/staging/fsl-dpaa2/evb/Kconfig"
++
++config FSL_DPAA2_ETHSW
++	tristate "Freescale DPAA2 Ethernet Switch"
++	depends on FSL_DPAA2
++	depends on NET_SWITCHDEV
++	---help---
++	Driver for Freescale DPAA2 Ethernet Switch. Select
++	BRIDGE to have support for bridge tools.
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/Makefile
+@@ -0,0 +1,9 @@
++#
++# Freescale DataPath Acceleration Architecture Gen2 (DPAA2) drivers
++#
++
++obj-$(CONFIG_FSL_DPAA2_ETH)	+= ethernet/
++obj-$(CONFIG_FSL_DPAA2_MAC)	+= mac/
++obj-$(CONFIG_FSL_DPAA2_EVB)	+= evb/
++obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += rtc/
++obj-$(CONFIG_FSL_DPAA2_ETHSW)	+= ethsw/
diff --git a/target/linux/layerscape/patches-4.9/202-core-linux-support-layerscape.patch b/target/linux/layerscape/patches-4.9/202-core-linux-support-layerscape.patch
new file mode 100644
index 000000000..1e33604f6
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/202-core-linux-support-layerscape.patch
@@ -0,0 +1,1458 @@
+From f339945a8e81fff22df95284e142b79c37fd2333 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 16:07:09 +0800
+Subject: [PATCH 02/32] core-linux: support layerscape
+
+This is an integrated patch for layerscape core-linux support.
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
+Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
+Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
+Signed-off-by: Jarod Wilson <jarod@redhat.com>
+Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
+Signed-off-by: stephen hemminger <stephen@networkplumber.org>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/base/devres.c                         |  66 ++++++
+ drivers/base/soc.c                            |  70 ++++++
+ .../net/ethernet/mellanox/mlxsw/spectrum.c    |   2 +-
+ .../mellanox/mlxsw/spectrum_switchdev.c       |   2 +-
+ drivers/net/ethernet/rocker/rocker_ofdpa.c    |   4 +-
+ include/linux/device.h                        |  19 ++
+ include/linux/dma-mapping.h                   |   5 +
+ include/linux/fsl/svr.h                       |  97 ++++++++
+ include/linux/fsl_devices.h                   |   3 +
+ include/linux/irqdesc.h                       |   4 +
+ include/linux/irqdomain.h                     |  13 +-
+ include/linux/netdev_features.h               |   2 +
+ include/linux/netdevice.h                     |  10 +-
+ include/linux/skbuff.h                        |   2 +
+ include/linux/sys_soc.h                       |   3 +
+ include/net/switchdev.h                       |   8 +-
+ include/uapi/linux/if_ether.h                 |   1 +
+ kernel/irq/Kconfig                            |  11 +
+ kernel/irq/Makefile                           |   1 +
+ kernel/irq/debugfs.c                          | 215 ++++++++++++++++++
+ kernel/irq/internals.h                        |  22 ++
+ kernel/irq/irqdesc.c                          |   1 +
+ kernel/irq/irqdomain.c                        | 171 ++++++++++----
+ kernel/irq/manage.c                           |   1 +
+ kernel/irq/msi.c                              |   2 +-
+ net/bridge/br.c                               |   4 +-
+ net/bridge/br_fdb.c                           |   2 +
+ net/bridge/br_private.h                       |   7 +
+ net/bridge/br_switchdev.c                     |  33 +++
+ net/core/dev.c                                |  30 ++-
+ net/core/net-sysfs.c                          |  20 +-
+ net/core/rtnetlink.c                          |   4 +-
+ net/core/skbuff.c                             |  29 ++-
+ net/sched/sch_generic.c                       |   7 +
+ 34 files changed, 809 insertions(+), 62 deletions(-)
+ create mode 100644 include/linux/fsl/svr.h
+ create mode 100644 kernel/irq/debugfs.c
+
+--- a/drivers/base/devres.c
++++ b/drivers/base/devres.c
+@@ -10,6 +10,7 @@
+ #include <linux/device.h>
+ #include <linux/module.h>
+ #include <linux/slab.h>
++#include <linux/percpu.h>
+ 
+ #include "base.h"
+ 
+@@ -985,3 +986,68 @@ void devm_free_pages(struct device *dev,
+ 			       &devres));
+ }
+ EXPORT_SYMBOL_GPL(devm_free_pages);
++
++static void devm_percpu_release(struct device *dev, void *pdata)
++{
++	void __percpu *p;
++
++	p = *(void __percpu **)pdata;
++	free_percpu(p);
++}
++
++static int devm_percpu_match(struct device *dev, void *data, void *p)
++{
++	struct devres *devr = container_of(data, struct devres, data);
++
++	return *(void **)devr->data == p;
++}
++
++/**
++ * __devm_alloc_percpu - Resource-managed alloc_percpu
++ * @dev: Device to allocate per-cpu memory for
++ * @size: Size of per-cpu memory to allocate
++ * @align: Alignment of per-cpu memory to allocate
++ *
++ * Managed alloc_percpu. Per-cpu memory allocated with this function is
++ * automatically freed on driver detach.
++ *
++ * RETURNS:
++ * Pointer to allocated memory on success, NULL on failure.
++ */
++void __percpu *__devm_alloc_percpu(struct device *dev, size_t size,
++		size_t align)
++{
++	void *p;
++	void __percpu *pcpu;
++
++	pcpu = __alloc_percpu(size, align);
++	if (!pcpu)
++		return NULL;
++
++	p = devres_alloc(devm_percpu_release, sizeof(void *), GFP_KERNEL);
++	if (!p) {
++		free_percpu(pcpu);
++		return NULL;
++	}
++
++	*(void __percpu **)p = pcpu;
++
++	devres_add(dev, p);
++
++	return pcpu;
++}
++EXPORT_SYMBOL_GPL(__devm_alloc_percpu);
++
++/**
++ * devm_free_percpu - Resource-managed free_percpu
++ * @dev: Device this memory belongs to
++ * @pdata: Per-cpu memory to free
++ *
++ * Free memory allocated with devm_alloc_percpu().
++ */
++void devm_free_percpu(struct device *dev, void __percpu *pdata)
++{
++	WARN_ON(devres_destroy(dev, devm_percpu_release, devm_percpu_match,
++			       (void *)pdata));
++}
++EXPORT_SYMBOL_GPL(devm_free_percpu);
+--- a/drivers/base/soc.c
++++ b/drivers/base/soc.c
+@@ -13,6 +13,7 @@
+ #include <linux/spinlock.h>
+ #include <linux/sys_soc.h>
+ #include <linux/err.h>
++#include <linux/glob.h>
+ 
+ static DEFINE_IDA(soc_ida);
+ 
+@@ -159,3 +160,72 @@ static int __init soc_bus_register(void)
+ 	return bus_register(&soc_bus_type);
+ }
+ core_initcall(soc_bus_register);
++
++static int soc_device_match_one(struct device *dev, void *arg)
++{
++	struct soc_device *soc_dev = container_of(dev, struct soc_device, dev);
++	const struct soc_device_attribute *match = arg;
++
++	if (match->machine &&
++	    (!soc_dev->attr->machine ||
++	     !glob_match(match->machine, soc_dev->attr->machine)))
++		return 0;
++
++	if (match->family &&
++	    (!soc_dev->attr->family ||
++	     !glob_match(match->family, soc_dev->attr->family)))
++		return 0;
++
++	if (match->revision &&
++	    (!soc_dev->attr->revision ||
++	     !glob_match(match->revision, soc_dev->attr->revision)))
++		return 0;
++
++	if (match->soc_id &&
++	    (!soc_dev->attr->soc_id ||
++	     !glob_match(match->soc_id, soc_dev->attr->soc_id)))
++		return 0;
++
++	return 1;
++}
++
++/*
++ * soc_device_match - identify the SoC in the machine
++ * @matches: zero-terminated array of possible matches
++ *
++ * returns the first matching entry of the argument array, or NULL
++ * if none of them match.
++ *
++ * This function is meant as a helper in place of of_match_node()
++ * in cases where either no device tree is available or the information
++ * in a device node is insufficient to identify a particular variant
++ * by its compatible strings or other properties. For new devices,
++ * the DT binding should always provide unique compatible strings
++ * that allow the use of of_match_node() instead.
++ *
++ * The calling function can use the .data entry of the
++ * soc_device_attribute to pass a structure or function pointer for
++ * each entry.
++ */
++const struct soc_device_attribute *soc_device_match(
++	const struct soc_device_attribute *matches)
++{
++	int ret = 0;
++
++	if (!matches)
++		return NULL;
++
++	while (!ret) {
++		if (!(matches->machine || matches->family ||
++		      matches->revision || matches->soc_id))
++			break;
++		ret = bus_for_each_dev(&soc_bus_type, NULL, (void *)matches,
++				       soc_device_match_one);
++		if (!ret)
++			matches++;
++		else
++			return matches;
++	}
++	return NULL;
++}
++EXPORT_SYMBOL_GPL(soc_device_match);
+--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
++++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c
+@@ -859,7 +859,7 @@ mlxsw_sp_port_get_sw_stats64(const struc
+ 	return 0;
+ }
+ 
+-static bool mlxsw_sp_port_has_offload_stats(int attr_id)
++static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
+ {
+ 	switch (attr_id) {
+ 	case IFLA_OFFLOAD_XSTATS_CPU_HIT:
+--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c
++++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c
+@@ -1405,7 +1405,7 @@ static void mlxsw_sp_fdb_call_notifiers(
+ 	if (learning_sync) {
+ 		info.addr = mac;
+ 		info.vid = vid;
+-		notifier_type = adding ? SWITCHDEV_FDB_ADD : SWITCHDEV_FDB_DEL;
++		notifier_type = adding ? SWITCHDEV_FDB_ADD_TO_BRIDGE : SWITCHDEV_FDB_DEL_TO_BRIDGE;
+ 		call_switchdev_notifiers(notifier_type, dev, &info.info);
+ 	}
+ }
+--- a/drivers/net/ethernet/rocker/rocker_ofdpa.c
++++ b/drivers/net/ethernet/rocker/rocker_ofdpa.c
+@@ -1939,10 +1939,10 @@ static void ofdpa_port_fdb_learn_work(st
+ 
+ 	rtnl_lock();
+ 	if (learned && removing)
+-		call_switchdev_notifiers(SWITCHDEV_FDB_DEL,
++		call_switchdev_notifiers(SWITCHDEV_FDB_DEL_TO_BRIDGE,
+ 					 lw->ofdpa_port->dev, &info.info);
+ 	else if (learned && !removing)
+-		call_switchdev_notifiers(SWITCHDEV_FDB_ADD,
++		call_switchdev_notifiers(SWITCHDEV_FDB_ADD_TO_BRIDGE,
+ 					 lw->ofdpa_port->dev, &info.info);
+ 	rtnl_unlock();
+ 
+--- a/include/linux/device.h
++++ b/include/linux/device.h
+@@ -688,6 +688,25 @@ void __iomem *devm_ioremap_resource(stru
+ int devm_add_action(struct device *dev, void (*action)(void *), void *data);
+ void devm_remove_action(struct device *dev, void (*action)(void *), void *data);
+ 
++/**
++ * devm_alloc_percpu - Resource-managed alloc_percpu
++ * @dev: Device to allocate per-cpu memory for
++ * @type: Type to allocate per-cpu memory for
++ *
++ * Managed alloc_percpu. Per-cpu memory allocated with this function is
++ * automatically freed on driver detach.
++ *
++ * RETURNS:
++ * Pointer to allocated memory on success, NULL on failure.
++ */
++#define devm_alloc_percpu(dev, type)      \
++	((typeof(type) __percpu *)__devm_alloc_percpu((dev), sizeof(type), \
++						      __alignof__(type)))
++
++void __percpu *__devm_alloc_percpu(struct device *dev, size_t size,
++				   size_t align);
++void devm_free_percpu(struct device *dev, void __percpu *pdata);
++
+ static inline int devm_add_action_or_reset(struct device *dev,
+ 					   void (*action)(void *), void *data)
+ {
+--- a/include/linux/dma-mapping.h
++++ b/include/linux/dma-mapping.h
+@@ -164,6 +164,11 @@ int dma_mmap_from_coherent(struct device
+ 
+ #ifdef CONFIG_HAS_DMA
+ #include <asm/dma-mapping.h>
++static inline void set_dma_ops(struct device *dev,
++			       struct dma_map_ops *dma_ops)
++{
++	dev->archdata.dma_ops = dma_ops;
++}
+ #else
+ /*
+  * Define the dma api to allow compilation but not linking of
+--- /dev/null
++++ b/include/linux/fsl/svr.h
+@@ -0,0 +1,97 @@
++/*
++ * MPC85xx cpu type detection
++ *
++ * Copyright 2011-2012 Freescale Semiconductor, Inc.
++ *
++ * This is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef FSL_SVR_H
++#define FSL_SVR_H
++
++#define SVR_REV(svr)	((svr) & 0xFF)		/* SOC design resision */
++#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
++#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
++
++/* Some parts define SVR[0:23] as the SOC version */
++#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF)	/* SOC Version fields */
++
++#define SVR_8533	0x803400
++#define SVR_8535	0x803701
++#define SVR_8536	0x803700
++#define SVR_8540	0x803000
++#define SVR_8541	0x807200
++#define SVR_8543	0x803200
++#define SVR_8544	0x803401
++#define SVR_8545	0x803102
++#define SVR_8547	0x803101
++#define SVR_8548	0x803100
++#define SVR_8555	0x807100
++#define SVR_8560	0x807000
++#define SVR_8567	0x807501
++#define SVR_8568	0x807500
++#define SVR_8569	0x808000
++#define SVR_8572	0x80E000
++#define SVR_P1010	0x80F100
++#define SVR_P1011	0x80E500
++#define SVR_P1012	0x80E501
++#define SVR_P1013	0x80E700
++#define SVR_P1014	0x80F101
++#define SVR_P1017	0x80F700
++#define SVR_P1020	0x80E400
++#define SVR_P1021	0x80E401
++#define SVR_P1022	0x80E600
++#define SVR_P1023	0x80F600
++#define SVR_P1024	0x80E402
++#define SVR_P1025	0x80E403
++#define SVR_P2010	0x80E300
++#define SVR_P2020	0x80E200
++#define SVR_P2040	0x821000
++#define SVR_P2041	0x821001
++#define SVR_P3041	0x821103
++#define SVR_P4040	0x820100
++#define SVR_P4080	0x820000
++#define SVR_P5010	0x822100
++#define SVR_P5020	0x822000
++#define SVR_P5021	0X820500
++#define SVR_P5040	0x820400
++#define SVR_T4240	0x824000
++#define SVR_T4120	0x824001
++#define SVR_T4160	0x824100
++#define SVR_T4080	0x824102
++#define SVR_C291	0x850000
++#define SVR_C292	0x850020
++#define SVR_C293	0x850030
++#define SVR_B4860	0X868000
++#define SVR_G4860	0x868001
++#define SVR_G4060	0x868003
++#define SVR_B4440	0x868100
++#define SVR_G4440	0x868101
++#define SVR_B4420	0x868102
++#define SVR_B4220	0x868103
++#define SVR_T1040	0x852000
++#define SVR_T1041	0x852001
++#define SVR_T1042	0x852002
++#define SVR_T1020	0x852100
++#define SVR_T1021	0x852101
++#define SVR_T1022	0x852102
++#define SVR_T1023	0x854100
++#define SVR_T1024	0x854000
++#define SVR_T2080	0x853000
++#define SVR_T2081	0x853100
++
++#define SVR_8610	0x80A000
++#define SVR_8641	0x809000
++#define SVR_8641D	0x809001
++
++#define SVR_9130	0x860001
++#define SVR_9131	0x860000
++#define SVR_9132	0x861000
++#define SVR_9232	0x861400
++
++#define SVR_Unknown	0xFFFFFF
++
++#endif
+--- a/include/linux/fsl_devices.h
++++ b/include/linux/fsl_devices.h
+@@ -99,7 +99,10 @@ struct fsl_usb2_platform_data {
+ 	unsigned	suspended:1;
+ 	unsigned	already_suspended:1;
+ 	unsigned        has_fsl_erratum_a007792:1;
++	unsigned        has_fsl_erratum_14:1;
+ 	unsigned        has_fsl_erratum_a005275:1;
++	unsigned        has_fsl_erratum_a006918:1;
++	unsigned        has_fsl_erratum_a005697:1;
+ 	unsigned        check_phy_clk_valid:1;
+ 
+ 	/* register save area for suspend/resume */
+--- a/include/linux/irqdesc.h
++++ b/include/linux/irqdesc.h
+@@ -46,6 +46,7 @@ struct pt_regs;
+  * @rcu:		rcu head for delayed free
+  * @kobj:		kobject used to represent this struct in sysfs
+  * @dir:		/proc/irq/ procfs entry
++ * @debugfs_file:	dentry for the debugfs file
+  * @name:		flow handler name for /proc/interrupts output
+  */
+ struct irq_desc {
+@@ -88,6 +89,9 @@ struct irq_desc {
+ #ifdef CONFIG_PROC_FS
+ 	struct proc_dir_entry	*dir;
+ #endif
++#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
++	struct dentry		*debugfs_file;
++#endif
+ #ifdef CONFIG_SPARSE_IRQ
+ 	struct rcu_head		rcu;
+ 	struct kobject		kobj;
+--- a/include/linux/irqdomain.h
++++ b/include/linux/irqdomain.h
+@@ -138,6 +138,7 @@ struct irq_domain_chip_generic;
+  *      setting up one or more generic chips for interrupt controllers
+  *      drivers using the generic chip library which uses this pointer.
+  * @parent: Pointer to parent irq_domain to support hierarchy irq_domains
++ * @debugfs_file: dentry for the domain debugfs file
+  *
+  * Revmap data, used internally by irq_domain
+  * @revmap_direct_max_irq: The largest hwirq that can be set for controllers that
+@@ -160,6 +161,9 @@ struct irq_domain {
+ #ifdef	CONFIG_IRQ_DOMAIN_HIERARCHY
+ 	struct irq_domain *parent;
+ #endif
++#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
++	struct dentry		*debugfs_file;
++#endif
+ 
+ 	/* reverse map data. The linear map gets appended to the irq_domain */
+ 	irq_hw_number_t hwirq_max;
+@@ -174,8 +178,8 @@ enum {
+ 	/* Irq domain is hierarchical */
+ 	IRQ_DOMAIN_FLAG_HIERARCHY	= (1 << 0),
+ 
+-	/* Core calls alloc/free recursive through the domain hierarchy. */
+-	IRQ_DOMAIN_FLAG_AUTO_RECURSIVE	= (1 << 1),
++	/* Irq domain name was allocated in __irq_domain_add() */
++	IRQ_DOMAIN_NAME_ALLOCATED	= (1 << 6),
+ 
+ 	/* Irq domain is an IPI domain with virq per cpu */
+ 	IRQ_DOMAIN_FLAG_IPI_PER_CPU	= (1 << 2),
+@@ -231,6 +235,9 @@ static inline bool is_fwnode_irqchip(str
+ 	return fwnode && fwnode->type == FWNODE_IRQCHIP;
+ }
+ 
++extern void irq_domain_update_bus_token(struct irq_domain *domain,
++					enum irq_domain_bus_token bus_token);
++
+ static inline
+ struct irq_domain *irq_find_matching_fwnode(struct fwnode_handle *fwnode,
+ 					    enum irq_domain_bus_token bus_token)
+@@ -403,7 +410,7 @@ static inline int irq_domain_alloc_irqs(
+ 				       NULL);
+ }
+ 
+-extern int irq_domain_alloc_irqs_recursive(struct irq_domain *domain,
++extern int irq_domain_alloc_irqs_hierarchy(struct irq_domain *domain,
+ 					   unsigned int irq_base,
+ 					   unsigned int nr_irqs, void *arg);
+ extern int irq_domain_set_hwirq_and_chip(struct irq_domain *domain,
+--- a/include/linux/netdev_features.h
++++ b/include/linux/netdev_features.h
+@@ -74,6 +74,7 @@ enum {
+ 	NETIF_F_BUSY_POLL_BIT,		/* Busy poll */
+ 
+ 	NETIF_F_HW_TC_BIT,		/* Offload TC infrastructure */
++	NETIF_F_HW_ACCEL_MQ_BIT,	/* Hardware-accelerated multiqueue */
+ 
+ 	/*
+ 	 * Add your fresh new feature above and remember to update
+@@ -136,6 +137,7 @@ enum {
+ #define NETIF_F_HW_L2FW_DOFFLOAD	__NETIF_F(HW_L2FW_DOFFLOAD)
+ #define NETIF_F_BUSY_POLL	__NETIF_F(BUSY_POLL)
+ #define NETIF_F_HW_TC		__NETIF_F(HW_TC)
++#define NETIF_F_HW_ACCEL_MQ	__NETIF_F(HW_ACCEL_MQ)
+ 
+ #define for_each_netdev_feature(mask_addr, bit)	\
+ 	for_each_set_bit(bit, (unsigned long *)mask_addr, NETDEV_FEATURE_COUNT)
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -930,7 +930,7 @@ struct netdev_xdp {
+  *	3. Update dev->stats asynchronously and atomically, and define
+  *	   neither operation.
+  *
+- * bool (*ndo_has_offload_stats)(int attr_id)
++ * bool (*ndo_has_offload_stats)(const struct net_device *dev, int attr_id)
+  *	Return true if this device supports offload stats of this attr_id.
+  *
+  * int (*ndo_get_offload_stats)(int attr_id, const struct net_device *dev,
+@@ -1167,7 +1167,7 @@ struct net_device_ops {
+ 
+ 	struct rtnl_link_stats64* (*ndo_get_stats64)(struct net_device *dev,
+ 						     struct rtnl_link_stats64 *storage);
+-	bool			(*ndo_has_offload_stats)(int attr_id);
++	bool			(*ndo_has_offload_stats)(const struct net_device *dev, int attr_id);
+ 	int			(*ndo_get_offload_stats)(int attr_id,
+ 							 const struct net_device *dev,
+ 							 void *attr_data);
+@@ -1509,6 +1509,8 @@ enum netdev_priv_flags {
+  *	@if_port:	Selectable AUI, TP, ...
+  *	@dma:		DMA channel
+  *	@mtu:		Interface MTU value
++ *	@min_mtu:	Interface Minimum MTU value
++ *	@max_mtu:	Interface Maximum MTU value
+  *	@type:		Interface hardware type
+  *	@hard_header_len: Maximum hardware header length.
+  *	@min_header_len:  Minimum hardware header length
+@@ -1735,6 +1737,8 @@ struct net_device {
+ 	unsigned char		dma;
+ 
+ 	unsigned int		mtu;
++	unsigned int		min_mtu;
++	unsigned int		max_mtu;
+ 	unsigned short		type;
+ 	unsigned short		hard_header_len;
+ 	unsigned short		min_header_len;
+@@ -1938,6 +1942,8 @@ int netdev_set_prio_tc_map(struct net_de
+ 	return 0;
+ }
+ 
++int netdev_txq_to_tc(struct net_device *dev, unsigned int txq);
++
+ static inline
+ void netdev_reset_tc(struct net_device *dev)
+ {
+--- a/include/linux/skbuff.h
++++ b/include/linux/skbuff.h
+@@ -908,6 +908,7 @@ void kfree_skb(struct sk_buff *skb);
+ void kfree_skb_list(struct sk_buff *segs);
+ void skb_tx_error(struct sk_buff *skb);
+ void consume_skb(struct sk_buff *skb);
++void skb_recycle(struct sk_buff *skb);
+ void  __kfree_skb(struct sk_buff *skb);
+ extern struct kmem_cache *skbuff_head_cache;
+ 
+@@ -3081,6 +3082,7 @@ static inline void skb_free_datagram_loc
+ }
+ int skb_kill_datagram(struct sock *sk, struct sk_buff *skb, unsigned int flags);
+ int skb_copy_bits(const struct sk_buff *skb, int offset, void *to, int len);
++void copy_skb_header(struct sk_buff *new, const struct sk_buff *old);
+ int skb_store_bits(struct sk_buff *skb, int offset, const void *from, int len);
+ __wsum skb_copy_and_csum_bits(const struct sk_buff *skb, int offset, u8 *to,
+ 			      int len, __wsum csum);
+--- a/include/linux/sys_soc.h
++++ b/include/linux/sys_soc.h
+@@ -13,6 +13,7 @@ struct soc_device_attribute {
+ 	const char *family;
+ 	const char *revision;
+ 	const char *soc_id;
++	const void *data;
+ };
+ 
+ /**
+@@ -34,4 +35,6 @@ void soc_device_unregister(struct soc_de
+  */
+ struct device *soc_device_to_device(struct soc_device *soc);
+ 
++const struct soc_device_attribute *soc_device_match(
++	const struct soc_device_attribute *matches);
+ #endif /* __SOC_BUS_H */
+--- a/include/net/switchdev.h
++++ b/include/net/switchdev.h
+@@ -46,6 +46,7 @@ enum switchdev_attr_id {
+ 	SWITCHDEV_ATTR_ID_PORT_PARENT_ID,
+ 	SWITCHDEV_ATTR_ID_PORT_STP_STATE,
+ 	SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS,
++	SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS_SUPPORT,
+ 	SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME,
+ 	SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING,
+ };
+@@ -60,6 +61,7 @@ struct switchdev_attr {
+ 		struct netdev_phys_item_id ppid;	/* PORT_PARENT_ID */
+ 		u8 stp_state;				/* PORT_STP_STATE */
+ 		unsigned long brport_flags;		/* PORT_BRIDGE_FLAGS */
++		unsigned long brport_flags_support;	/* PORT_BRIDGE_FLAGS_SUPPORT */
+ 		clock_t ageing_time;			/* BRIDGE_AGEING_TIME */
+ 		bool vlan_filtering;			/* BRIDGE_VLAN_FILTERING */
+ 	} u;
+@@ -149,8 +151,10 @@ struct switchdev_ops {
+ };
+ 
+ enum switchdev_notifier_type {
+-	SWITCHDEV_FDB_ADD = 1,
+-	SWITCHDEV_FDB_DEL,
++	SWITCHDEV_FDB_ADD_TO_BRIDGE = 1,
++	SWITCHDEV_FDB_DEL_TO_BRIDGE,
++	SWITCHDEV_FDB_ADD_TO_DEVICE,
++	SWITCHDEV_FDB_DEL_TO_DEVICE,
+ };
+ 
+ struct switchdev_notifier_info {
+--- a/include/uapi/linux/if_ether.h
++++ b/include/uapi/linux/if_ether.h
+@@ -36,6 +36,7 @@
+ #define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
+ #define ETH_FRAME_LEN	1514		/* Max. octets in frame sans FCS */
+ #define ETH_FCS_LEN	4		/* Octets in the FCS		 */
++#define ETH_MIN_MTU	68		/* Min IPv4 MTU per RFC791      */
+ 
+ /*
+  *	These are the defined Ethernet Protocol ID's.
+--- a/kernel/irq/Kconfig
++++ b/kernel/irq/Kconfig
+@@ -108,4 +108,15 @@ config SPARSE_IRQ
+ 
+ 	  If you don't know what to do here, say N.
+ 
++config GENERIC_IRQ_DEBUGFS
++	bool "Expose irq internals in debugfs"
++	depends on DEBUG_FS
++	default n
++	---help---
++
++	  Exposes internal state information through debugfs. Mostly for
++	  developers and debugging of hard to diagnose interrupt problems.
++
++	  If you don't know what to do here, say N.
++
+ endmenu
+--- a/kernel/irq/Makefile
++++ b/kernel/irq/Makefile
+@@ -10,3 +10,4 @@ obj-$(CONFIG_PM_SLEEP) += pm.o
+ obj-$(CONFIG_GENERIC_MSI_IRQ) += msi.o
+ obj-$(CONFIG_GENERIC_IRQ_IPI) += ipi.o
+ obj-$(CONFIG_SMP) += affinity.o
++obj-$(CONFIG_GENERIC_IRQ_DEBUGFS) += debugfs.o
+--- /dev/null
++++ b/kernel/irq/debugfs.c
+@@ -0,0 +1,215 @@
++/*
++ * Copyright 2017 Thomas Gleixner <tglx@linutronix.de>
++ *
++ * This file is licensed under the GPL V2.
++ */
++#include <linux/debugfs.h>
++#include <linux/irqdomain.h>
++#include <linux/irq.h>
++
++#include "internals.h"
++
++static struct dentry *irq_dir;
++
++struct irq_bit_descr {
++	unsigned int	mask;
++	char		*name;
++};
++#define BIT_MASK_DESCR(m)	{ .mask = m, .name = #m }
++
++static void irq_debug_show_bits(struct seq_file *m, int ind, unsigned int state,
++				const struct irq_bit_descr *sd, int size)
++{
++	int i;
++
++	for (i = 0; i < size; i++, sd++) {
++		if (state & sd->mask)
++			seq_printf(m, "%*s%s\n", ind + 12, "", sd->name);
++	}
++}
++
++#ifdef CONFIG_SMP
++static void irq_debug_show_masks(struct seq_file *m, struct irq_desc *desc)
++{
++	struct irq_data *data = irq_desc_get_irq_data(desc);
++	struct cpumask *msk;
++
++	msk = irq_data_get_affinity_mask(data);
++	seq_printf(m, "affinity: %*pbl\n", cpumask_pr_args(msk));
++#ifdef CONFIG_GENERIC_PENDING_IRQ
++	msk = desc->pending_mask;
++	seq_printf(m, "pending:  %*pbl\n", cpumask_pr_args(msk));
++#endif
++}
++#else
++static void irq_debug_show_masks(struct seq_file *m, struct irq_desc *desc) { }
++#endif
++
++static const struct irq_bit_descr irqchip_flags[] = {
++	BIT_MASK_DESCR(IRQCHIP_SET_TYPE_MASKED),
++	BIT_MASK_DESCR(IRQCHIP_EOI_IF_HANDLED),
++	BIT_MASK_DESCR(IRQCHIP_MASK_ON_SUSPEND),
++	BIT_MASK_DESCR(IRQCHIP_ONOFFLINE_ENABLED),
++	BIT_MASK_DESCR(IRQCHIP_SKIP_SET_WAKE),
++	BIT_MASK_DESCR(IRQCHIP_ONESHOT_SAFE),
++	BIT_MASK_DESCR(IRQCHIP_EOI_THREADED),
++};
++
++static void
++irq_debug_show_chip(struct seq_file *m, struct irq_data *data, int ind)
++{
++	struct irq_chip *chip = data->chip;
++
++	if (!chip) {
++		seq_printf(m, "chip: None\n");
++		return;
++	}
++	seq_printf(m, "%*schip:    %s\n", ind, "", chip->name);
++	seq_printf(m, "%*sflags:   0x%lx\n", ind + 1, "", chip->flags);
++	irq_debug_show_bits(m, ind, chip->flags, irqchip_flags,
++			    ARRAY_SIZE(irqchip_flags));
++}
++
++static void
++irq_debug_show_data(struct seq_file *m, struct irq_data *data, int ind)
++{
++	seq_printf(m, "%*sdomain:  %s\n", ind, "",
++		   data->domain ? data->domain->name : "");
++	seq_printf(m, "%*shwirq:   0x%lx\n", ind + 1, "", data->hwirq);
++	irq_debug_show_chip(m, data, ind + 1);
++#ifdef	CONFIG_IRQ_DOMAIN_HIERARCHY
++	if (!data->parent_data)
++		return;
++	seq_printf(m, "%*sparent:\n", ind + 1, "");
++	irq_debug_show_data(m, data->parent_data, ind + 4);
++#endif
++}
++
++static const struct irq_bit_descr irqdata_states[] = {
++	BIT_MASK_DESCR(IRQ_TYPE_EDGE_RISING),
++	BIT_MASK_DESCR(IRQ_TYPE_EDGE_FALLING),
++	BIT_MASK_DESCR(IRQ_TYPE_LEVEL_HIGH),
++	BIT_MASK_DESCR(IRQ_TYPE_LEVEL_LOW),
++	BIT_MASK_DESCR(IRQD_LEVEL),
++
++	BIT_MASK_DESCR(IRQD_ACTIVATED),
++	BIT_MASK_DESCR(IRQD_IRQ_STARTED),
++	BIT_MASK_DESCR(IRQD_IRQ_DISABLED),
++	BIT_MASK_DESCR(IRQD_IRQ_MASKED),
++	BIT_MASK_DESCR(IRQD_IRQ_INPROGRESS),
++
++	BIT_MASK_DESCR(IRQD_PER_CPU),
++	BIT_MASK_DESCR(IRQD_NO_BALANCING),
++
++	BIT_MASK_DESCR(IRQD_MOVE_PCNTXT),
++	BIT_MASK_DESCR(IRQD_AFFINITY_SET),
++	BIT_MASK_DESCR(IRQD_SETAFFINITY_PENDING),
++	BIT_MASK_DESCR(IRQD_AFFINITY_MANAGED),
++	BIT_MASK_DESCR(IRQD_MANAGED_SHUTDOWN),
++
++	BIT_MASK_DESCR(IRQD_FORWARDED_TO_VCPU),
++
++	BIT_MASK_DESCR(IRQD_WAKEUP_STATE),
++	BIT_MASK_DESCR(IRQD_WAKEUP_ARMED),
++};
++
++static const struct irq_bit_descr irqdesc_states[] = {
++	BIT_MASK_DESCR(_IRQ_NOPROBE),
++	BIT_MASK_DESCR(_IRQ_NOREQUEST),
++	BIT_MASK_DESCR(_IRQ_NOTHREAD),
++	BIT_MASK_DESCR(_IRQ_NOAUTOEN),
++	BIT_MASK_DESCR(_IRQ_NESTED_THREAD),
++	BIT_MASK_DESCR(_IRQ_PER_CPU_DEVID),
++	BIT_MASK_DESCR(_IRQ_IS_POLLED),
++	BIT_MASK_DESCR(_IRQ_DISABLE_UNLAZY),
++};
++
++static const struct irq_bit_descr irqdesc_istates[] = {
++	BIT_MASK_DESCR(IRQS_AUTODETECT),
++	BIT_MASK_DESCR(IRQS_SPURIOUS_DISABLED),
++	BIT_MASK_DESCR(IRQS_POLL_INPROGRESS),
++	BIT_MASK_DESCR(IRQS_ONESHOT),
++	BIT_MASK_DESCR(IRQS_REPLAY),
++	BIT_MASK_DESCR(IRQS_WAITING),
++	BIT_MASK_DESCR(IRQS_PENDING),
++	BIT_MASK_DESCR(IRQS_SUSPENDED),
++};
++
++
++static int irq_debug_show(struct seq_file *m, void *p)
++{
++	struct irq_desc *desc = m->private;
++	struct irq_data *data;
++
++	raw_spin_lock_irq(&desc->lock);
++	data = irq_desc_get_irq_data(desc);
++	seq_printf(m, "handler:  %pf\n", desc->handle_irq);
++	seq_printf(m, "status:   0x%08x\n", desc->status_use_accessors);
++	irq_debug_show_bits(m, 0, desc->status_use_accessors, irqdesc_states,
++			    ARRAY_SIZE(irqdesc_states));
++	seq_printf(m, "istate:   0x%08x\n", desc->istate);
++	irq_debug_show_bits(m, 0, desc->istate, irqdesc_istates,
++			    ARRAY_SIZE(irqdesc_istates));
++	seq_printf(m, "ddepth:   %u\n", desc->depth);
++	seq_printf(m, "wdepth:   %u\n", desc->wake_depth);
++	seq_printf(m, "dstate:   0x%08x\n", irqd_get(data));
++	irq_debug_show_bits(m, 0, irqd_get(data), irqdata_states,
++			    ARRAY_SIZE(irqdata_states));
++	seq_printf(m, "node:     %d\n", irq_data_get_node(data));
++	irq_debug_show_masks(m, desc);
++	irq_debug_show_data(m, data, 0);
++	raw_spin_unlock_irq(&desc->lock);
++	return 0;
++}
++
++static int irq_debug_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, irq_debug_show, inode->i_private);
++}
++
++static const struct file_operations dfs_irq_ops = {
++	.open		= irq_debug_open,
++	.read		= seq_read,
++	.llseek		= seq_lseek,
++	.release	= single_release,
++};
++
++void irq_add_debugfs_entry(unsigned int irq, struct irq_desc *desc)
++{
++	char name [10];
++
++	if (!irq_dir || !desc || desc->debugfs_file)
++		return;
++
++	sprintf(name, "%d", irq);
++	desc->debugfs_file = debugfs_create_file(name, 0444, irq_dir, desc,
++						 &dfs_irq_ops);
++}
++
++void irq_remove_debugfs_entry(struct irq_desc *desc)
++{
++	if (desc->debugfs_file)
++		debugfs_remove(desc->debugfs_file);
++}
++
++static int __init irq_debugfs_init(void)
++{
++	struct dentry *root_dir;
++	int irq;
++
++	root_dir = debugfs_create_dir("irq", NULL);
++	if (!root_dir)
++		return -ENOMEM;
++
++	irq_domain_debugfs_init(root_dir);
++
++	irq_dir = debugfs_create_dir("irqs", root_dir);
++
++	irq_lock_sparse();
++	for_each_active_irq(irq)
++		irq_add_debugfs_entry(irq, irq_to_desc(irq));
++	irq_unlock_sparse();
++
++	return 0;
++}
++__initcall(irq_debugfs_init);
+--- a/kernel/irq/internals.h
++++ b/kernel/irq/internals.h
+@@ -169,6 +169,11 @@ irq_put_desc_unlock(struct irq_desc *des
+ 
+ #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
+ 
++static inline unsigned int irqd_get(struct irq_data *d)
++{
++	return __irqd_to_state(d);
++}
++
+ /*
+  * Manipulation functions for irq_data.state
+  */
+@@ -226,3 +231,20 @@ irq_pm_install_action(struct irq_desc *d
+ static inline void
+ irq_pm_remove_action(struct irq_desc *desc, struct irqaction *action) { }
+ #endif
++
++#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
++void irq_add_debugfs_entry(unsigned int irq, struct irq_desc *desc);
++void irq_remove_debugfs_entry(struct irq_desc *desc);
++# ifdef CONFIG_IRQ_DOMAIN
++void irq_domain_debugfs_init(struct dentry *root);
++# else
++static inline void irq_domain_debugfs_init(struct dentry *root);
++# endif
++#else /* CONFIG_GENERIC_IRQ_DEBUGFS */
++static inline void irq_add_debugfs_entry(unsigned int irq, struct irq_desc *d)
++{
++}
++static inline void irq_remove_debugfs_entry(struct irq_desc *d)
++{
++}
++#endif /* CONFIG_GENERIC_IRQ_DEBUGFS */
+--- a/kernel/irq/irqdesc.c
++++ b/kernel/irq/irqdesc.c
+@@ -394,6 +394,7 @@ static void free_desc(unsigned int irq)
+ {
+ 	struct irq_desc *desc = irq_to_desc(irq);
+ 
++	irq_remove_debugfs_entry(desc);
+ 	unregister_irq_proc(irq, desc);
+ 
+ 	/*
+--- a/kernel/irq/irqdomain.c
++++ b/kernel/irq/irqdomain.c
+@@ -31,6 +31,14 @@ struct irqchip_fwid {
+ 	void *data;
+ };
+ 
++#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
++static void debugfs_add_domain_dir(struct irq_domain *d);
++static void debugfs_remove_domain_dir(struct irq_domain *d);
++#else
++static inline void debugfs_add_domain_dir(struct irq_domain *d) { }
++static inline void debugfs_remove_domain_dir(struct irq_domain *d) { }
++#endif
++
+ /**
+  * irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for
+  *                           identifying an irq domain
+@@ -117,6 +125,7 @@ struct irq_domain *__irq_domain_add(stru
+ 	irq_domain_check_hierarchy(domain);
+ 
+ 	mutex_lock(&irq_domain_mutex);
++	debugfs_add_domain_dir(domain);
+ 	list_add(&domain->link, &irq_domain_list);
+ 	mutex_unlock(&irq_domain_mutex);
+ 
+@@ -136,6 +145,7 @@ EXPORT_SYMBOL_GPL(__irq_domain_add);
+ void irq_domain_remove(struct irq_domain *domain)
+ {
+ 	mutex_lock(&irq_domain_mutex);
++	debugfs_remove_domain_dir(domain);
+ 
+ 	WARN_ON(!radix_tree_empty(&domain->revmap_tree));
+ 
+@@ -156,6 +166,37 @@ void irq_domain_remove(struct irq_domain
+ }
+ EXPORT_SYMBOL_GPL(irq_domain_remove);
+ 
++void irq_domain_update_bus_token(struct irq_domain *domain,
++				 enum irq_domain_bus_token bus_token)
++{
++	char *name;
++
++	if (domain->bus_token == bus_token)
++		return;
++
++	mutex_lock(&irq_domain_mutex);
++
++	domain->bus_token = bus_token;
++
++	name = kasprintf(GFP_KERNEL, "%s-%d", domain->name, bus_token);
++	if (!name) {
++		mutex_unlock(&irq_domain_mutex);
++		return;
++	}
++
++	debugfs_remove_domain_dir(domain);
++
++	if (domain->flags & IRQ_DOMAIN_NAME_ALLOCATED)
++		kfree(domain->name);
++	else
++		domain->flags |= IRQ_DOMAIN_NAME_ALLOCATED;
++
++	domain->name = name;
++	debugfs_add_domain_dir(domain);
++
++	mutex_unlock(&irq_domain_mutex);
++}
++
+ /**
+  * irq_domain_add_simple() - Register an irq_domain and optionally map a range of irqs
+  * @of_node: pointer to interrupt controller's device tree node.
+@@ -1164,43 +1205,18 @@ void irq_domain_free_irqs_top(struct irq
+ 	irq_domain_free_irqs_common(domain, virq, nr_irqs);
+ }
+ 
+-static bool irq_domain_is_auto_recursive(struct irq_domain *domain)
+-{
+-	return domain->flags & IRQ_DOMAIN_FLAG_AUTO_RECURSIVE;
+-}
+-
+-static void irq_domain_free_irqs_recursive(struct irq_domain *domain,
++static void irq_domain_free_irqs_hierarchy(struct irq_domain *domain,
+ 					   unsigned int irq_base,
+ 					   unsigned int nr_irqs)
+ {
+ 	domain->ops->free(domain, irq_base, nr_irqs);
+-	if (irq_domain_is_auto_recursive(domain)) {
+-		BUG_ON(!domain->parent);
+-		irq_domain_free_irqs_recursive(domain->parent, irq_base,
+-					       nr_irqs);
+-	}
+ }
+ 
+-int irq_domain_alloc_irqs_recursive(struct irq_domain *domain,
++int irq_domain_alloc_irqs_hierarchy(struct irq_domain *domain,
+ 				    unsigned int irq_base,
+ 				    unsigned int nr_irqs, void *arg)
+ {
+-	int ret = 0;
+-	struct irq_domain *parent = domain->parent;
+-	bool recursive = irq_domain_is_auto_recursive(domain);
+-
+-	BUG_ON(recursive && !parent);
+-	if (recursive)
+-		ret = irq_domain_alloc_irqs_recursive(parent, irq_base,
+-						      nr_irqs, arg);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = domain->ops->alloc(domain, irq_base, nr_irqs, arg);
+-	if (ret < 0 && recursive)
+-		irq_domain_free_irqs_recursive(parent, irq_base, nr_irqs);
+-
+-	return ret;
++	return domain->ops->alloc(domain, irq_base, nr_irqs, arg);
+ }
+ 
+ /**
+@@ -1261,7 +1277,7 @@ int __irq_domain_alloc_irqs(struct irq_d
+ 	}
+ 
+ 	mutex_lock(&irq_domain_mutex);
+-	ret = irq_domain_alloc_irqs_recursive(domain, virq, nr_irqs, arg);
++	ret = irq_domain_alloc_irqs_hierarchy(domain, virq, nr_irqs, arg);
+ 	if (ret < 0) {
+ 		mutex_unlock(&irq_domain_mutex);
+ 		goto out_free_irq_data;
+@@ -1296,7 +1312,7 @@ void irq_domain_free_irqs(unsigned int v
+ 	mutex_lock(&irq_domain_mutex);
+ 	for (i = 0; i < nr_irqs; i++)
+ 		irq_domain_remove_irq(virq + i);
+-	irq_domain_free_irqs_recursive(data->domain, virq, nr_irqs);
++	irq_domain_free_irqs_hierarchy(data->domain, virq, nr_irqs);
+ 	mutex_unlock(&irq_domain_mutex);
+ 
+ 	irq_domain_free_irq_data(virq, nr_irqs);
+@@ -1316,15 +1332,11 @@ int irq_domain_alloc_irqs_parent(struct
+ 				 unsigned int irq_base, unsigned int nr_irqs,
+ 				 void *arg)
+ {
+-	/* irq_domain_alloc_irqs_recursive() has called parent's alloc() */
+-	if (irq_domain_is_auto_recursive(domain))
+-		return 0;
++	if (!domain->parent)
++		return -ENOSYS;
+ 
+-	domain = domain->parent;
+-	if (domain)
+-		return irq_domain_alloc_irqs_recursive(domain, irq_base,
+-						       nr_irqs, arg);
+-	return -ENOSYS;
++	return irq_domain_alloc_irqs_hierarchy(domain->parent, irq_base,
++					       nr_irqs, arg);
+ }
+ EXPORT_SYMBOL_GPL(irq_domain_alloc_irqs_parent);
+ 
+@@ -1339,10 +1351,10 @@ EXPORT_SYMBOL_GPL(irq_domain_alloc_irqs_
+ void irq_domain_free_irqs_parent(struct irq_domain *domain,
+ 				 unsigned int irq_base, unsigned int nr_irqs)
+ {
+-	/* irq_domain_free_irqs_recursive() will call parent's free */
+-	if (!irq_domain_is_auto_recursive(domain) && domain->parent)
+-		irq_domain_free_irqs_recursive(domain->parent, irq_base,
+-					       nr_irqs);
++	if (!domain->parent)
++		return;
++
++	irq_domain_free_irqs_hierarchy(domain->parent, irq_base, nr_irqs);
+ }
+ EXPORT_SYMBOL_GPL(irq_domain_free_irqs_parent);
+ 
+@@ -1448,3 +1460,78 @@ static void irq_domain_check_hierarchy(s
+ {
+ }
+ #endif	/* CONFIG_IRQ_DOMAIN_HIERARCHY */
++
++#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
++static struct dentry *domain_dir;
++
++static void
++irq_domain_debug_show_one(struct seq_file *m, struct irq_domain *d, int ind)
++{
++	seq_printf(m, "%*sname:   %s\n", ind, "", d->name);
++	seq_printf(m, "%*ssize:   %u\n", ind + 1, "",
++		   d->revmap_size + d->revmap_direct_max_irq);
++	seq_printf(m, "%*smapped: %u\n", ind + 1, "", d->mapcount);
++	seq_printf(m, "%*sflags:  0x%08x\n", ind +1 , "", d->flags);
++#ifdef	CONFIG_IRQ_DOMAIN_HIERARCHY
++	if (!d->parent)
++		return;
++	seq_printf(m, "%*sparent: %s\n", ind + 1, "", d->parent->name);
++	irq_domain_debug_show_one(m, d->parent, ind + 4);
++#endif
++}
++
++static int irq_domain_debug_show(struct seq_file *m, void *p)
++{
++	struct irq_domain *d = m->private;
++
++	/* Default domain? Might be NULL */
++	if (!d) {
++		if (!irq_default_domain)
++			return 0;
++		d = irq_default_domain;
++	}
++	irq_domain_debug_show_one(m, d, 0);
++	return 0;
++}
++
++static int irq_domain_debug_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, irq_domain_debug_show, inode->i_private);
++}
++
++static const struct file_operations dfs_domain_ops = {
++	.open		= irq_domain_debug_open,
++	.read		= seq_read,
++	.llseek		= seq_lseek,
++	.release	= single_release,
++};
++
++static void debugfs_add_domain_dir(struct irq_domain *d)
++{
++	if (!d->name || !domain_dir || d->debugfs_file)
++		return;
++	d->debugfs_file = debugfs_create_file(d->name, 0444, domain_dir, d,
++					      &dfs_domain_ops);
++}
++
++static void debugfs_remove_domain_dir(struct irq_domain *d)
++{
++	if (d->debugfs_file)
++		debugfs_remove(d->debugfs_file);
++}
++
++void __init irq_domain_debugfs_init(struct dentry *root)
++{
++	struct irq_domain *d;
++
++	domain_dir = debugfs_create_dir("domains", root);
++	if (!domain_dir)
++		return;
++
++	debugfs_create_file("default", 0444, domain_dir, NULL, &dfs_domain_ops);
++	mutex_lock(&irq_domain_mutex);
++	list_for_each_entry(d, &irq_domain_list, link)
++		debugfs_add_domain_dir(d);
++	mutex_unlock(&irq_domain_mutex);
++}
++#endif
+--- a/kernel/irq/manage.c
++++ b/kernel/irq/manage.c
+@@ -1391,6 +1391,7 @@ __setup_irq(unsigned int irq, struct irq
+ 		wake_up_process(new->secondary->thread);
+ 
+ 	register_irq_proc(irq, desc);
++	irq_add_debugfs_entry(irq, desc);
+ 	new->dir = NULL;
+ 	register_handler_proc(irq, new);
+ 	free_cpumask_var(mask);
+--- a/kernel/irq/msi.c
++++ b/kernel/irq/msi.c
+@@ -310,7 +310,7 @@ int msi_domain_populate_irqs(struct irq_
+ 
+ 		ops->set_desc(arg, desc);
+ 		/* Assumes the domain mutex is held! */
+-		ret = irq_domain_alloc_irqs_recursive(domain, virq, 1, arg);
++		ret = irq_domain_alloc_irqs_hierarchy(domain, virq, 1, arg);
+ 		if (ret)
+ 			break;
+ 
+--- a/net/bridge/br.c
++++ b/net/bridge/br.c
+@@ -138,14 +138,14 @@ static int br_switchdev_event(struct not
+ 	br = p->br;
+ 
+ 	switch (event) {
+-	case SWITCHDEV_FDB_ADD:
++	case SWITCHDEV_FDB_ADD_TO_BRIDGE:
+ 		fdb_info = ptr;
+ 		err = br_fdb_external_learn_add(br, p, fdb_info->addr,
+ 						fdb_info->vid);
+ 		if (err)
+ 			err = notifier_from_errno(err);
+ 		break;
+-	case SWITCHDEV_FDB_DEL:
++	case SWITCHDEV_FDB_DEL_TO_BRIDGE:
+ 		fdb_info = ptr;
+ 		err = br_fdb_external_learn_del(br, p, fdb_info->addr,
+ 						fdb_info->vid);
+--- a/net/bridge/br_fdb.c
++++ b/net/bridge/br_fdb.c
+@@ -688,6 +688,8 @@ static void fdb_notify(struct net_bridge
+ 	struct sk_buff *skb;
+ 	int err = -ENOBUFS;
+ 
++	br_switchdev_fdb_notify(fdb, type);
++
+ 	skb = nlmsg_new(fdb_nlmsg_size(), GFP_ATOMIC);
+ 	if (skb == NULL)
+ 		goto errout;
+--- a/net/bridge/br_private.h
++++ b/net/bridge/br_private.h
+@@ -1060,6 +1060,8 @@ void nbp_switchdev_frame_mark(const stru
+ 			      struct sk_buff *skb);
+ bool nbp_switchdev_allowed_egress(const struct net_bridge_port *p,
+ 				  const struct sk_buff *skb);
++void br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb,
++			     int type);
+ #else
+ static inline int nbp_switchdev_mark_set(struct net_bridge_port *p)
+ {
+@@ -1076,6 +1078,11 @@ static inline bool nbp_switchdev_allowed
+ {
+ 	return true;
+ }
++
++static inline void
++br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, int type)
++{
++}
+ #endif /* CONFIG_NET_SWITCHDEV */
+ 
+ #endif
+--- a/net/bridge/br_switchdev.c
++++ b/net/bridge/br_switchdev.c
+@@ -55,3 +55,36 @@ bool nbp_switchdev_allowed_egress(const
+ 	return !skb->offload_fwd_mark ||
+ 	       BR_INPUT_SKB_CB(skb)->offload_fwd_mark != p->offload_fwd_mark;
+ }
++
++static void
++br_switchdev_fdb_call_notifiers(bool adding, const unsigned char *mac,
++				u16 vid, struct net_device *dev)
++{
++	struct switchdev_notifier_fdb_info info;
++	unsigned long notifier_type;
++
++	info.addr = mac;
++	info.vid = vid;
++	notifier_type = adding ? SWITCHDEV_FDB_ADD_TO_DEVICE : SWITCHDEV_FDB_DEL_TO_DEVICE;
++	call_switchdev_notifiers(notifier_type, dev, &info.info);
++}
++
++void
++br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, int type)
++{
++	if (!fdb->added_by_user)
++		return;
++
++	switch (type) {
++	case RTM_DELNEIGH:
++		br_switchdev_fdb_call_notifiers(false, fdb->addr.addr,
++						fdb->vlan_id,
++						fdb->dst->dev);
++		break;
++	case RTM_NEWNEIGH:
++		br_switchdev_fdb_call_notifiers(true, fdb->addr.addr,
++						fdb->vlan_id,
++						fdb->dst->dev);
++		break;
++	}
++}
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -1990,6 +1990,23 @@ static void netif_setup_tc(struct net_de
+ 	}
+ }
+ 
++int netdev_txq_to_tc(struct net_device *dev, unsigned int txq)
++{
++	if (dev->num_tc) {
++		struct netdev_tc_txq *tc = &dev->tc_to_txq[0];
++		int i;
++
++		for (i = 0; i < TC_MAX_QUEUE; i++, tc++) {
++			if ((txq - tc->offset) < tc->count)
++				return i;
++		}
++
++		return -1;
++	}
++
++	return 0;
++}
++
+ #ifdef CONFIG_XPS
+ static DEFINE_MUTEX(xps_map_mutex);
+ #define xmap_dereference(P)		\
+@@ -6656,9 +6673,18 @@ int dev_set_mtu(struct net_device *dev,
+ 	if (new_mtu == dev->mtu)
+ 		return 0;
+ 
+-	/*	MTU must be positive.	 */
+-	if (new_mtu < 0)
++	/* MTU must be positive, and in range */
++	if (new_mtu < 0 || new_mtu < dev->min_mtu) {
++		net_err_ratelimited("%s: Invalid MTU %d requested, hw min %d\n",
++				    dev->name, new_mtu, dev->min_mtu);
+ 		return -EINVAL;
++	}
++
++	if (dev->max_mtu > 0 && new_mtu > dev->max_mtu) {
++		net_err_ratelimited("%s: Invalid MTU %d requested, hw max %d\n",
++				    dev->name, new_mtu, dev->min_mtu);
++		return -EINVAL;
++	}
+ 
+ 	if (!netif_device_present(dev))
+ 		return -ENODEV;
+--- a/net/core/net-sysfs.c
++++ b/net/core/net-sysfs.c
+@@ -1021,7 +1021,6 @@ static ssize_t show_trans_timeout(struct
+ 	return sprintf(buf, "%lu", trans_timeout);
+ }
+ 
+-#ifdef CONFIG_XPS
+ static unsigned int get_netdev_queue_index(struct netdev_queue *queue)
+ {
+ 	struct net_device *dev = queue->dev;
+@@ -1033,6 +1032,21 @@ static unsigned int get_netdev_queue_ind
+ 	return i;
+ }
+ 
++static ssize_t show_traffic_class(struct netdev_queue *queue,
++				  struct netdev_queue_attribute *attribute,
++				  char *buf)
++{
++	struct net_device *dev = queue->dev;
++	int index = get_netdev_queue_index(queue);
++	int tc = netdev_txq_to_tc(dev, index);
++
++	if (tc < 0)
++		return -EINVAL;
++
++	return sprintf(buf, "%u\n", tc);
++}
++
++#ifdef CONFIG_XPS
+ static ssize_t show_tx_maxrate(struct netdev_queue *queue,
+ 			       struct netdev_queue_attribute *attribute,
+ 			       char *buf)
+@@ -1075,6 +1089,9 @@ static struct netdev_queue_attribute que
+ static struct netdev_queue_attribute queue_trans_timeout =
+ 	__ATTR(tx_timeout, S_IRUGO, show_trans_timeout, NULL);
+ 
++static struct netdev_queue_attribute queue_traffic_class =
++	__ATTR(traffic_class, S_IRUGO, show_traffic_class, NULL);
++
+ #ifdef CONFIG_BQL
+ /*
+  * Byte queue limits sysfs structures and functions.
+@@ -1260,6 +1277,7 @@ static struct netdev_queue_attribute xps
+ 
+ static struct attribute *netdev_queue_default_attrs[] = {
+ 	&queue_trans_timeout.attr,
++	&queue_traffic_class.attr,
+ #ifdef CONFIG_XPS
+ 	&xps_cpus_attribute.attr,
+ 	&queue_tx_maxrate.attr,
+--- a/net/core/rtnetlink.c
++++ b/net/core/rtnetlink.c
+@@ -3709,7 +3709,7 @@ static int rtnl_get_offload_stats(struct
+ 		if (!size)
+ 			continue;
+ 
+-		if (!dev->netdev_ops->ndo_has_offload_stats(attr_id))
++		if (!dev->netdev_ops->ndo_has_offload_stats(dev, attr_id))
+ 			continue;
+ 
+ 		attr = nla_reserve_64bit(skb, attr_id, size,
+@@ -3750,7 +3750,7 @@ static int rtnl_get_offload_stats_size(c
+ 
+ 	for (attr_id = IFLA_OFFLOAD_XSTATS_FIRST;
+ 	     attr_id <= IFLA_OFFLOAD_XSTATS_MAX; attr_id++) {
+-		if (!dev->netdev_ops->ndo_has_offload_stats(attr_id))
++		if (!dev->netdev_ops->ndo_has_offload_stats(dev, attr_id))
+ 			continue;
+ 		size = rtnl_get_offload_stats_attr_size(attr_id);
+ 		nla_size += nla_total_size_64bit(size);
+--- a/net/core/skbuff.c
++++ b/net/core/skbuff.c
+@@ -842,6 +842,32 @@ void napi_consume_skb(struct sk_buff *sk
+ }
+ EXPORT_SYMBOL(napi_consume_skb);
+ 
++/**
++ * 	skb_recycle - clean up an skb for reuse
++ * 	@skb: buffer
++ *
++ * 	Recycles the skb to be reused as a receive buffer. This
++ * 	function does any necessary reference count dropping, and
++ * 	cleans up the skbuff as if it just came from __alloc_skb().
++ */
++void skb_recycle(struct sk_buff *skb)
++{
++	struct skb_shared_info *shinfo;
++	u8 head_frag = skb->head_frag;
++
++	skb_release_head_state(skb);
++
++	shinfo = skb_shinfo(skb);
++	memset(shinfo, 0, offsetof(struct skb_shared_info, dataref));
++	atomic_set(&shinfo->dataref, 1);
++
++	memset(skb, 0, offsetof(struct sk_buff, tail));
++	skb->data = skb->head + NET_SKB_PAD;
++	skb->head_frag = head_frag;
++	skb_reset_tail_pointer(skb);
++}
++EXPORT_SYMBOL(skb_recycle);
++
+ /* Make sure a field is enclosed inside headers_start/headers_end section */
+ #define CHECK_SKB_FIELD(field) \
+ 	BUILD_BUG_ON(offsetof(struct sk_buff, field) <		\
+@@ -1075,7 +1101,7 @@ static void skb_headers_offset_update(st
+ 	skb->inner_mac_header += off;
+ }
+ 
+-static void copy_skb_header(struct sk_buff *new, const struct sk_buff *old)
++void copy_skb_header(struct sk_buff *new, const struct sk_buff *old)
+ {
+ 	__copy_skb_header(new, old);
+ 
+@@ -1083,6 +1109,7 @@ static void copy_skb_header(struct sk_bu
+ 	skb_shinfo(new)->gso_segs = skb_shinfo(old)->gso_segs;
+ 	skb_shinfo(new)->gso_type = skb_shinfo(old)->gso_type;
+ }
++EXPORT_SYMBOL(copy_skb_header);
+ 
+ static inline int skb_alloc_rx_flag(const struct sk_buff *skb)
+ {
+--- a/net/sched/sch_generic.c
++++ b/net/sched/sch_generic.c
+@@ -309,6 +309,13 @@ static void dev_watchdog(unsigned long a
+ 					txq->trans_timeout++;
+ 					break;
+ 				}
++
++				/* Devices with HW_ACCEL_MQ have multiple txqs
++				 * but update only the first one's transmission
++				 * timestamp so avoid checking the rest.
++				 */
++				if (dev->features & NETIF_F_HW_ACCEL_MQ)
++					break;
+ 			}
+ 
+ 			if (some_queue_timedout) {
diff --git a/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch b/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch
new file mode 100644
index 000000000..2985cff0b
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch
@@ -0,0 +1,517 @@
+From 2f2a0ab9e4b3186be981f7151a4f4f794d4b6caa Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 16:18:37 +0800
+Subject: [PATCH 03/32] arch: support layerscape
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is an integrated patch for layerscape arch support.
+
+Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
+Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
+Signed-off-by: Zhao Qiang <B45475@freescale.com>
+Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
+Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
+Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
+Signed-off-by: Po Liu <po.liu@nxp.com>
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
+Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ arch/arm/include/asm/delay.h           | 16 +++++++
+ arch/arm/include/asm/dma-mapping.h     |  6 ---
+ arch/arm/include/asm/io.h              | 31 +++++++++++++
+ arch/arm/include/asm/mach/map.h        |  4 +-
+ arch/arm/include/asm/pgtable.h         |  7 +++
+ arch/arm/kernel/bios32.c               | 43 ++++++++++++++++++
+ arch/arm/mm/dma-mapping.c              |  1 +
+ arch/arm/mm/ioremap.c                  |  7 +++
+ arch/arm/mm/mmu.c                      |  9 ++++
+ arch/arm64/include/asm/cache.h         |  2 +-
+ arch/arm64/include/asm/io.h            | 30 +++++++++++++
+ arch/arm64/include/asm/pci.h           |  4 ++
+ arch/arm64/include/asm/pgtable-prot.h  |  2 +
+ arch/arm64/include/asm/pgtable.h       |  5 +++
+ arch/arm64/kernel/pci.c                | 62 ++++++++++++++++++++++++++
+ arch/arm64/mm/dma-mapping.c            |  6 +++
+ arch/powerpc/include/asm/dma-mapping.h |  5 ---
+ arch/tile/include/asm/dma-mapping.h    |  5 ---
+ 18 files changed, 226 insertions(+), 19 deletions(-)
+
+--- a/arch/arm/include/asm/delay.h
++++ b/arch/arm/include/asm/delay.h
+@@ -57,6 +57,22 @@ extern void __bad_udelay(void);
+ 			__const_udelay((n) * UDELAY_MULT)) :		\
+ 	  __udelay(n))
+ 
++#define spin_event_timeout(condition, timeout, delay)                          \
++({                                                                             \
++	typeof(condition) __ret;                                               \
++	int i = 0;							       \
++	while (!(__ret = (condition)) && (i++ < timeout)) {		       \
++		if (delay)                                                     \
++			udelay(delay);                                         \
++		else                                                           \
++			cpu_relax();					       \
++		udelay(1);						       \
++	}								       \
++	if (!__ret)                                                            \
++		__ret = (condition);                                           \
++	__ret;		                                                       \
++})
++
+ /* Loop-based definitions for assembly code. */
+ extern void __loop_delay(unsigned long loops);
+ extern void __loop_udelay(unsigned long usecs);
+--- a/arch/arm/include/asm/dma-mapping.h
++++ b/arch/arm/include/asm/dma-mapping.h
+@@ -31,12 +31,6 @@ static inline struct dma_map_ops *get_dm
+ 		return __generic_dma_ops(dev);
+ }
+ 
+-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
+-{
+-	BUG_ON(!dev);
+-	dev->archdata.dma_ops = ops;
+-}
+-
+ #define HAVE_ARCH_DMA_SUPPORTED 1
+ extern int dma_supported(struct device *dev, u64 mask);
+ 
+--- a/arch/arm/include/asm/io.h
++++ b/arch/arm/include/asm/io.h
+@@ -129,6 +129,7 @@ static inline u32 __raw_readl(const vola
+ #define MT_DEVICE_NONSHARED	1
+ #define MT_DEVICE_CACHED	2
+ #define MT_DEVICE_WC		3
++#define MT_MEMORY_RW_NS		4
+ /*
+  * types 4 onwards can be found in asm/mach/map.h and are undefined
+  * for ioremap
+@@ -220,6 +221,34 @@ extern int pci_ioremap_io(unsigned int o
+ #endif
+ #endif
+ 
++/* access ports */
++#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
++#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
++
++#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
++#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
++
++#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
++#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
++
++/* Clear and set bits in one shot.  These macros can be used to clear and
++ * set multiple bits in a register using a single read-modify-write.  These
++ * macros can also be used to set a multiple-bit bit pattern using a mask,
++ * by specifying the mask in the 'clear' parameter and the new bit pattern
++ * in the 'set' parameter.
++ */
++
++#define clrsetbits_be32(addr, clear, set) \
++	iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_le32(addr, clear, set) \
++	iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_be16(addr, clear, set) \
++	iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_le16(addr, clear, set) \
++	iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_8(addr, clear, set) \
++	iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
++
+ /*
+  *  IO port access primitives
+  *  -------------------------
+@@ -408,6 +437,8 @@ void __iomem *ioremap_wc(resource_size_t
+ #define ioremap_wc ioremap_wc
+ #define ioremap_wt ioremap_wc
+ 
++void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size);
++
+ void iounmap(volatile void __iomem *iomem_cookie);
+ #define iounmap iounmap
+ 
+--- a/arch/arm/include/asm/mach/map.h
++++ b/arch/arm/include/asm/mach/map.h
+@@ -21,9 +21,9 @@ struct map_desc {
+ 	unsigned int type;
+ };
+ 
+-/* types 0-3 are defined in asm/io.h */
++/* types 0-4 are defined in asm/io.h */
+ enum {
+-	MT_UNCACHED = 4,
++	MT_UNCACHED = 5,
+ 	MT_CACHECLEAN,
+ 	MT_MINICLEAN,
+ 	MT_LOW_VECTORS,
+--- a/arch/arm/include/asm/pgtable.h
++++ b/arch/arm/include/asm/pgtable.h
+@@ -118,6 +118,13 @@ extern pgprot_t		pgprot_s2_device;
+ #define pgprot_noncached(prot) \
+ 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
+ 
++#define pgprot_cached(prot) \
++	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
++
++#define pgprot_cached_ns(prot) \
++	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
++			L_PTE_MT_DEV_NONSHARED)
++
+ #define pgprot_writecombine(prot) \
+ 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
+ 
+--- a/arch/arm/kernel/bios32.c
++++ b/arch/arm/kernel/bios32.c
+@@ -11,6 +11,8 @@
+ #include <linux/slab.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
++#include <linux/of_irq.h>
++#include <linux/pcieport_if.h>
+ 
+ #include <asm/mach-types.h>
+ #include <asm/mach/map.h>
+@@ -64,6 +66,47 @@ void pcibios_report_status(u_int status_
+ }
+ 
+ /*
++ * Check device tree if the service interrupts are there
++ */
++int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
++{
++	int ret, count = 0;
++	struct device_node *np = NULL;
++
++	if (dev->bus->dev.of_node)
++		np = dev->bus->dev.of_node;
++
++	if (np == NULL)
++		return 0;
++
++	if (!IS_ENABLED(CONFIG_OF_IRQ))
++		return 0;
++
++	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
++	 * request irq for aer
++	 */
++	if (mask & PCIE_PORT_SERVICE_AER) {
++		ret = of_irq_get_byname(np, "aer");
++		if (ret > 0) {
++			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
++			count++;
++		}
++	}
++
++	if (mask & PCIE_PORT_SERVICE_PME) {
++		ret = of_irq_get_byname(np, "pme");
++		if (ret > 0) {
++			irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
++			count++;
++		}
++	}
++
++	/* TODO: add more service interrupts if there it is in the device tree*/
++
++	return count;
++}
++
++/*
+  * We don't use this to fix the device, but initialisation of it.
+  * It's not the correct use for this, but it works.
+  * Note that the arbiter/ISA bridge appears to be buggy, specifically in
+--- a/arch/arm/mm/dma-mapping.c
++++ b/arch/arm/mm/dma-mapping.c
+@@ -2410,6 +2410,7 @@ void arch_setup_dma_ops(struct device *d
+ 
+ 	set_dma_ops(dev, dma_ops);
+ }
++EXPORT_SYMBOL(arch_setup_dma_ops);
+ 
+ void arch_teardown_dma_ops(struct device *dev)
+ {
+--- a/arch/arm/mm/ioremap.c
++++ b/arch/arm/mm/ioremap.c
+@@ -398,6 +398,13 @@ void __iomem *ioremap_wc(resource_size_t
+ }
+ EXPORT_SYMBOL(ioremap_wc);
+ 
++void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size)
++{
++	return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS,
++				   __builtin_return_address(0));
++}
++EXPORT_SYMBOL(ioremap_cache_ns);
++
+ /*
+  * Remap an arbitrary physical address space into the kernel virtual
+  * address space as memory. Needed when the kernel wants to execute
+--- a/arch/arm/mm/mmu.c
++++ b/arch/arm/mm/mmu.c
+@@ -313,6 +313,13 @@ static struct mem_type mem_types[] __ro_
+ 		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
+ 		.domain    = DOMAIN_KERNEL,
+ 	},
++	[MT_MEMORY_RW_NS] = {
++		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
++			     L_PTE_XN,
++		.prot_l1   = PMD_TYPE_TABLE,
++		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN,
++		.domain    = DOMAIN_KERNEL,
++	},
+ 	[MT_ROM] = {
+ 		.prot_sect = PMD_TYPE_SECT,
+ 		.domain    = DOMAIN_KERNEL,
+@@ -644,6 +651,7 @@ static void __init build_mem_type_table(
+ 	}
+ 	kern_pgprot |= PTE_EXT_AF;
+ 	vecs_pgprot |= PTE_EXT_AF;
++	mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte;
+ 
+ 	/*
+ 	 * Set PXN for user mappings
+@@ -672,6 +680,7 @@ static void __init build_mem_type_table(
+ 	mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
+ 	mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
+ 	mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
++	mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd;
+ 	mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
+ 	mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
+ 	mem_types[MT_ROM].prot_sect |= cp->pmd;
+--- a/arch/arm64/include/asm/cache.h
++++ b/arch/arm64/include/asm/cache.h
+@@ -18,7 +18,7 @@
+ 
+ #include <asm/cachetype.h>
+ 
+-#define L1_CACHE_SHIFT		7
++#define L1_CACHE_SHIFT		6
+ #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
+ 
+ /*
+--- a/arch/arm64/include/asm/io.h
++++ b/arch/arm64/include/asm/io.h
+@@ -171,6 +171,8 @@ extern void __iomem *ioremap_cache(phys_
+ #define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
+ #define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
+ #define ioremap_wt(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
++#define ioremap_cache_ns(addr, size)   __ioremap((addr), (size), \
++                                                __pgprot(PROT_NORMAL_NS))
+ #define iounmap				__iounmap
+ 
+ /*
+@@ -184,6 +186,34 @@ extern void __iomem *ioremap_cache(phys_
+ #define iowrite32be(v,p)	({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
+ #define iowrite64be(v,p)	({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
+ 
++/* access ports */
++#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
++#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
++
++#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
++#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
++
++#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
++#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
++
++/* Clear and set bits in one shot.  These macros can be used to clear and
++ * set multiple bits in a register using a single read-modify-write.  These
++ * macros can also be used to set a multiple-bit bit pattern using a mask,
++ * by specifying the mask in the 'clear' parameter and the new bit pattern
++ * in the 'set' parameter.
++ */
++
++#define clrsetbits_be32(addr, clear, set) \
++	iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_le32(addr, clear, set) \
++	iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_be16(addr, clear, set) \
++	iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_le16(addr, clear, set) \
++	iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_8(addr, clear, set) \
++	iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
++
+ #include <asm-generic/io.h>
+ 
+ /*
+--- a/arch/arm64/include/asm/pci.h
++++ b/arch/arm64/include/asm/pci.h
+@@ -31,6 +31,10 @@ static inline int pci_get_legacy_ide_irq
+ 	return -ENODEV;
+ }
+ 
++#define HAVE_PCI_MMAP
++extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
++			       enum pci_mmap_state mmap_state,
++			       int write_combine);
+ static inline int pci_proc_domain(struct pci_bus *bus)
+ {
+ 	return 1;
+--- a/arch/arm64/include/asm/pgtable-prot.h
++++ b/arch/arm64/include/asm/pgtable-prot.h
+@@ -48,6 +48,7 @@
+ #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
+ #define PROT_NORMAL_WT		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
+ #define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
++#define PROT_NORMAL_NS         (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
+ 
+ #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
+ #define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
+@@ -68,6 +69,7 @@
+ #define PAGE_HYP_DEVICE		__pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
+ 
+ #define PAGE_S2			__pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
++#define PAGE_S2_NS		__pgprot(PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF)
+ #define PAGE_S2_DEVICE		__pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
+ 
+ #define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_NG | PTE_PXN | PTE_UXN)
+--- a/arch/arm64/include/asm/pgtable.h
++++ b/arch/arm64/include/asm/pgtable.h
+@@ -370,6 +370,11 @@ static inline int pmd_protnone(pmd_t pmd
+ 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
+ #define pgprot_writecombine(prot) \
+ 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
++#define pgprot_cached(prot) \
++	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
++			PTE_PXN | PTE_UXN)
++#define pgprot_cached_ns(prot) \
++	__pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
+ #define pgprot_device(prot) \
+ 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
+ #define __HAVE_PHYS_MEM_ACCESS_PROT
+--- a/arch/arm64/kernel/pci.c
++++ b/arch/arm64/kernel/pci.c
+@@ -17,6 +17,8 @@
+ #include <linux/mm.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
++#include <linux/of_irq.h>
++#include <linux/pcieport_if.h>
+ #include <linux/pci.h>
+ #include <linux/pci-acpi.h>
+ #include <linux/pci-ecam.h>
+@@ -53,6 +55,66 @@ int pcibios_alloc_irq(struct pci_dev *de
+ 
+ 	return 0;
+ }
++
++/*
++ * Check device tree if the service interrupts are there
++ */
++int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
++{
++	int ret, count = 0;
++	struct device_node *np = NULL;
++
++	if (dev->bus->dev.of_node)
++		np = dev->bus->dev.of_node;
++
++	if (np == NULL)
++		return 0;
++
++	if (!IS_ENABLED(CONFIG_OF_IRQ))
++		return 0;
++
++	/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
++	 * request irq for aer
++	 */
++	if (mask & PCIE_PORT_SERVICE_AER) {
++		ret = of_irq_get_byname(np, "aer");
++		if (ret > 0) {
++			irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
++			count++;
++		}
++	}
++
++	if (mask & PCIE_PORT_SERVICE_PME) {
++		ret = of_irq_get_byname(np, "pme");
++		if (ret > 0) {
++			irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
++			count++;
++		}
++	}
++
++	/* TODO: add more service interrupts if there it is in the device tree*/
++
++	return count;
++}
++
++int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
++			enum pci_mmap_state mmap_state, int write_combine)
++{
++	if (mmap_state == pci_mmap_io)
++		return -EINVAL;
++
++	/*
++	 * Mark this as IO
++	 */
++	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++
++	if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++			     vma->vm_end - vma->vm_start,
++			     vma->vm_page_prot))
++		return -EAGAIN;
++
++	return 0;
++}
+ 
+ /*
+  * raw_pci_read/write - Platform-specific PCI config space access.
+--- a/arch/arm64/mm/dma-mapping.c
++++ b/arch/arm64/mm/dma-mapping.c
+@@ -30,6 +30,7 @@
+ #include <linux/swiotlb.h>
+ 
+ #include <asm/cacheflush.h>
++#include <linux/fsl/mc.h>
+ 
+ static int swiotlb __ro_after_init;
+ 
+@@ -925,6 +926,10 @@ static int __init __iommu_dma_init(void)
+ 	if (!ret)
+ 		ret = register_iommu_dma_ops_notifier(&pci_bus_type);
+ #endif
++#ifdef CONFIG_FSL_MC_BUS
++	if (!ret)
++		ret = register_iommu_dma_ops_notifier(&fsl_mc_bus_type);
++#endif
+ 	return ret;
+ }
+ arch_initcall(__iommu_dma_init);
+@@ -978,3 +983,4 @@ void arch_setup_dma_ops(struct device *d
+ 	dev->archdata.dma_coherent = coherent;
+ 	__iommu_setup_dma_ops(dev, dma_base, size, iommu);
+ }
++EXPORT_SYMBOL(arch_setup_dma_ops);
+--- a/arch/powerpc/include/asm/dma-mapping.h
++++ b/arch/powerpc/include/asm/dma-mapping.h
+@@ -91,11 +91,6 @@ static inline struct dma_map_ops *get_dm
+ 	return dev->archdata.dma_ops;
+ }
+ 
+-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
+-{
+-	dev->archdata.dma_ops = ops;
+-}
+-
+ /*
+  * get_dma_offset()
+  *
+--- a/arch/tile/include/asm/dma-mapping.h
++++ b/arch/tile/include/asm/dma-mapping.h
+@@ -59,11 +59,6 @@ static inline phys_addr_t dma_to_phys(st
+ 
+ static inline void dma_mark_clean(void *addr, size_t size) {}
+ 
+-static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
+-{
+-	dev->archdata.dma_ops = ops;
+-}
+-
+ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+ {
+ 	if (!dev->dma_mask)
diff --git a/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch b/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch
new file mode 100644
index 000000000..36854f193
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch
@@ -0,0 +1,10549 @@
+From 2ba4c76bc645b7b4ff04364f294f3022d369108a Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 16:20:56 +0800
+Subject: [PATCH 04/32] dts: support layercape
+
+This is an integrated patch for layerscape dts support.
+
+Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
+Signed-off-by: Alison Wang <b18965@freescale.com>
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
+Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
+Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
+Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
+Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
+Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Changming Huang <jerry.huang@nxp.com>
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Meng Yi <meng.yi@nxp.com>
+Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ arch/arm/boot/dts/alpine.dtsi                 |   2 +-
+ arch/arm/boot/dts/axm55xx.dtsi                |   2 +-
+ arch/arm/boot/dts/ecx-2000.dts                |   2 +-
+ arch/arm/boot/dts/imx6ul.dtsi                 |   4 +-
+ arch/arm/boot/dts/keystone.dtsi               |   4 +-
+ arch/arm/boot/dts/ls1021a-qds.dts             |  26 +
+ arch/arm/boot/dts/ls1021a-twr.dts             |  25 +
+ arch/arm/boot/dts/ls1021a.dtsi                | 284 ++++--
+ arch/arm/boot/dts/mt6580.dtsi                 |   2 +-
+ arch/arm/boot/dts/mt6589.dtsi                 |   2 +-
+ arch/arm/boot/dts/mt8127.dtsi                 |   2 +-
+ arch/arm/boot/dts/mt8135.dtsi                 |   2 +-
+ arch/arm/boot/dts/rk3288.dtsi                 |   2 +-
+ arch/arm/boot/dts/sun6i-a31.dtsi              |   2 +-
+ arch/arm/boot/dts/sun7i-a20.dtsi              |   4 +-
+ arch/arm/boot/dts/sun8i-a23-a33.dtsi          |   2 +-
+ arch/arm/boot/dts/sun9i-a80.dtsi              |   2 +-
+ arch/arm64/boot/dts/freescale/Makefile        |  18 +
+ .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 123 +++
+ .../boot/dts/freescale/fsl-ls1012a-frdm.dts   | 141 +++
+ .../boot/dts/freescale/fsl-ls1012a-frwy.dts   | 177 ++++
+ .../boot/dts/freescale/fsl-ls1012a-qds.dts    | 166 ++++
+ .../boot/dts/freescale/fsl-ls1012a-rdb.dts    | 102 ++
+ .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 567 +++++++++++
+ .../boot/dts/freescale/fsl-ls1043-post.dtsi   |  44 +
+ .../dts/freescale/fsl-ls1043a-qds-sdk.dts     |  71 ++
+ .../boot/dts/freescale/fsl-ls1043a-qds.dts    | 210 ++++-
+ .../dts/freescale/fsl-ls1043a-rdb-sdk.dts     |  71 ++
+ .../dts/freescale/fsl-ls1043a-rdb-usdpaa.dts  | 117 +++
+ .../boot/dts/freescale/fsl-ls1043a-rdb.dts    | 152 ++-
+ .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 357 +++++--
+ .../boot/dts/freescale/fsl-ls1046-post.dtsi   |  48 +
+ .../dts/freescale/fsl-ls1046a-qds-sdk.dts     | 112 +++
+ .../boot/dts/freescale/fsl-ls1046a-qds.dts    | 326 +++++++
+ .../dts/freescale/fsl-ls1046a-rdb-sdk.dts     |  85 ++
+ .../dts/freescale/fsl-ls1046a-rdb-usdpaa.dts  | 110 +++
+ .../boot/dts/freescale/fsl-ls1046a-rdb.dts    | 181 ++++
+ .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 771 +++++++++++++++
+ .../boot/dts/freescale/fsl-ls1088a-qds.dts    | 137 +++
+ .../boot/dts/freescale/fsl-ls1088a-rdb.dts    | 200 ++++
+ .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 800 ++++++++++++++++
+ .../boot/dts/freescale/fsl-ls2080a-qds.dts    | 229 +----
+ .../boot/dts/freescale/fsl-ls2080a-rdb.dts    | 207 ++--
+ .../boot/dts/freescale/fsl-ls2080a-simu.dts   |  47 +-
+ .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 803 ++--------------
+ .../boot/dts/freescale/fsl-ls2081a-rdb.dts    | 161 ++++
+ .../boot/dts/freescale/fsl-ls2088a-qds.dts    | 126 +++
+ .../boot/dts/freescale/fsl-ls2088a-rdb.dts    | 104 ++
+ .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 159 ++++
+ .../boot/dts/freescale/fsl-ls208xa-qds.dtsi   | 162 ++++
+ .../boot/dts/freescale/fsl-ls208xa-rdb.dtsi   | 136 +++
+ .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 885 ++++++++++++++++++
+ .../dts/freescale/qoriq-bman-portals-sdk.dtsi |  55 ++
+ .../dts/freescale/qoriq-bman-portals.dtsi     |  77 ++
+ .../boot/dts/freescale/qoriq-dpaa-eth.dtsi    |  73 ++
+ .../dts/freescale/qoriq-fman3-0-10g-0.dtsi    |  43 +
+ .../dts/freescale/qoriq-fman3-0-10g-1.dtsi    |  43 +
+ .../dts/freescale/qoriq-fman3-0-1g-0.dtsi     |  42 +
+ .../dts/freescale/qoriq-fman3-0-1g-1.dtsi     |  42 +
+ .../dts/freescale/qoriq-fman3-0-1g-2.dtsi     |  42 +
+ .../dts/freescale/qoriq-fman3-0-1g-3.dtsi     |  42 +
+ .../dts/freescale/qoriq-fman3-0-1g-4.dtsi     |  42 +
+ .../dts/freescale/qoriq-fman3-0-1g-5.dtsi     |  42 +
+ .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi |  47 +
+ .../boot/dts/freescale/qoriq-fman3-0.dtsi     | 130 +++
+ .../dts/freescale/qoriq-qman-portals-sdk.dtsi |  38 +
+ .../dts/freescale/qoriq-qman-portals.dtsi     |  87 ++
+ .../boot/dts/fsl/qoriq-bman1-portals.dtsi     |  10 +
+ .../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi     |   4 +-
+ .../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi     |   4 +-
+ 70 files changed, 8051 insertions(+), 1286 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
+
+--- a/arch/arm/boot/dts/alpine.dtsi
++++ b/arch/arm/boot/dts/alpine.dtsi
+@@ -93,7 +93,7 @@
+ 			interrupt-controller;
+ 			reg = <0x0 0xfb001000 0x0 0x1000>,
+ 			      <0x0 0xfb002000 0x0 0x2000>,
+-			      <0x0 0xfb004000 0x0 0x1000>,
++			      <0x0 0xfb004000 0x0 0x2000>,
+ 			      <0x0 0xfb006000 0x0 0x2000>;
+ 			interrupts =
+ 				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+--- a/arch/arm/boot/dts/axm55xx.dtsi
++++ b/arch/arm/boot/dts/axm55xx.dtsi
+@@ -62,7 +62,7 @@
+ 		#address-cells = <0>;
+ 		interrupt-controller;
+ 		reg = <0x20 0x01001000 0 0x1000>,
+-		      <0x20 0x01002000 0 0x1000>,
++		      <0x20 0x01002000 0 0x2000>,
+ 		      <0x20 0x01004000 0 0x2000>,
+ 		      <0x20 0x01006000 0 0x2000>;
+ 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+--- a/arch/arm/boot/dts/ecx-2000.dts
++++ b/arch/arm/boot/dts/ecx-2000.dts
+@@ -99,7 +99,7 @@
+ 			interrupt-controller;
+ 			interrupts = <1 9 0xf04>;
+ 			reg = <0xfff11000 0x1000>,
+-			      <0xfff12000 0x1000>,
++			      <0xfff12000 0x2000>,
+ 			      <0xfff14000 0x2000>,
+ 			      <0xfff16000 0x2000>;
+ 		};
+--- a/arch/arm/boot/dts/imx6ul.dtsi
++++ b/arch/arm/boot/dts/imx6ul.dtsi
+@@ -89,11 +89,11 @@
+ 	};
+ 
+ 	intc: interrupt-controller@00a01000 {
+-		compatible = "arm,cortex-a7-gic";
++		compatible = "arm,gic-400", "arm,cortex-a7-gic";
+ 		#interrupt-cells = <3>;
+ 		interrupt-controller;
+ 		reg = <0x00a01000 0x1000>,
+-		      <0x00a02000 0x1000>,
++		      <0x00a02000 0x2000>,
+ 		      <0x00a04000 0x2000>,
+ 		      <0x00a06000 0x2000>;
+ 	};
+--- a/arch/arm/boot/dts/keystone.dtsi
++++ b/arch/arm/boot/dts/keystone.dtsi
+@@ -30,12 +30,12 @@
+ 	};
+ 
+ 	gic: interrupt-controller {
+-		compatible = "arm,cortex-a15-gic";
++		compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ 		#interrupt-cells = <3>;
+ 		interrupt-controller;
+ 		reg = <0x0 0x02561000 0x0 0x1000>,
+ 		      <0x0 0x02562000 0x0 0x2000>,
+-		      <0x0 0x02564000 0x0 0x1000>,
++		      <0x0 0x02564000 0x0 0x2000>,
+ 		      <0x0 0x02566000 0x0 0x2000>;
+ 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ 				IRQ_TYPE_LEVEL_HIGH)>;
+--- a/arch/arm/boot/dts/ls1021a-qds.dts
++++ b/arch/arm/boot/dts/ls1021a-qds.dts
+@@ -124,6 +124,19 @@
+ 	};
+ };
+ 
++&qspi {
++	num-cs = <2>;
++	status = "okay";
++
++	qflash0: s25fl128s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++};
++
+ &enet0 {
+ 	tbi-handle = <&tbi0>;
+ 	phy-handle = <&sgmii_phy1c>;
+@@ -239,6 +252,11 @@
+ 		device-width = <1>;
+ 	};
+ 
++	nand@2,0 {
++		compatible = "fsl,ifc-nand";
++		reg = <0x2 0x0 0x10000>;
++	};
++
+ 	fpga: board-control@3,0 {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+@@ -331,3 +349,11 @@
+ &uart1 {
+ 	status = "okay";
+ };
++
++&can0 {
++	status = "okay";
++};
++
++&can1 {
++	status = "okay";
++};
+--- a/arch/arm/boot/dts/ls1021a-twr.dts
++++ b/arch/arm/boot/dts/ls1021a-twr.dts
+@@ -142,6 +142,19 @@
+ 	};
+ };
+ 
++&qspi {
++	num-cs = <2>;
++	status = "okay";
++
++	qflash0: n25q128a13@0 {
++		compatible = "n25q128a13", "jedec,spi-nor";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++};
++
+ &enet0 {
+ 	tbi-handle = <&tbi1>;
+ 	phy-handle = <&sgmii_phy2>;
+@@ -228,6 +241,10 @@
+ 	};
+ };
+ 
++&esdhc {
++        status = "okay";
++};
++
+ &sai1 {
+ 	status = "okay";
+ };
+@@ -243,3 +260,11 @@
+ &uart1 {
+ 	status = "okay";
+ };
++
++&can0 {
++	status = "okay";
++};
++
++&can1 {
++	status = "okay";
++};
+--- a/arch/arm/boot/dts/ls1021a.dtsi
++++ b/arch/arm/boot/dts/ls1021a.dtsi
+@@ -47,6 +47,7 @@
+ 
+ #include "skeleton64.dtsi"
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+ 	compatible = "fsl,ls1021a";
+@@ -70,21 +71,29 @@
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
+-		cpu@f00 {
++		cpu0: @f00 {
+ 			compatible = "arm,cortex-a7";
+ 			device_type = "cpu";
+ 			reg = <0xf00>;
+-			clocks = <&cluster1_clk>;
++			clocks = <&clockgen 1 0>;
++			#cooling-cells = <2>;
+ 		};
+ 
+-		cpu@f01 {
++		cpu1: @f01 {
+ 			compatible = "arm,cortex-a7";
+ 			device_type = "cpu";
+ 			reg = <0xf01>;
+-			clocks = <&cluster1_clk>;
++			clocks = <&clockgen 1 0>;
+ 		};
+ 	};
+ 
++	sysclk: sysclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <100000000>;
++		clock-output-names = "sysclk";
++	};
++
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+ 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -108,11 +117,11 @@
+ 		ranges;
+ 
+ 		gic: interrupt-controller@1400000 {
+-			compatible = "arm,cortex-a7-gic";
++			compatible = "arm,gic-400", "arm,cortex-a7-gic";
+ 			#interrupt-cells = <3>;
+ 			interrupt-controller;
+ 			reg = <0x0 0x1401000 0x0 0x1000>,
+-			      <0x0 0x1402000 0x0 0x1000>,
++			      <0x0 0x1402000 0x0 0x2000>,
+ 			      <0x0 0x1404000 0x0 0x2000>,
+ 			      <0x0 0x1406000 0x0 0x2000>;
+ 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+@@ -120,14 +129,14 @@
+ 		};
+ 
+ 		msi1: msi-controller@1570e00 {
+-			compatible = "fsl,1s1021a-msi";
++			compatible = "fsl,ls1021a-msi";
+ 			reg = <0x0 0x1570e00 0x0 0x8>;
+ 			msi-controller;
+ 			interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
+ 
+ 		msi2: msi-controller@1570e08 {
+-			compatible = "fsl,1s1021a-msi";
++			compatible = "fsl,ls1021a-msi";
+ 			reg = <0x0 0x1570e08 0x0 0x8>;
+ 			msi-controller;
+ 			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+@@ -137,11 +146,12 @@
+ 			compatible = "fsl,ifc", "simple-bus";
+ 			reg = <0x0 0x1530000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++			big-endian;
+ 		};
+ 
+ 		dcfg: dcfg@1ee0000 {
+ 			compatible = "fsl,ls1021a-dcfg", "syscon";
+-			reg = <0x0 0x1ee0000 0x0 0x10000>;
++			reg = <0x0 0x1ee0000 0x0 0x1000>;
+ 			big-endian;
+ 		};
+ 
+@@ -163,7 +173,7 @@
+ 			      <0x0 0x20220520 0x0 0x4>;
+ 			reg-names = "ahci", "sata-ecc";
+ 			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			dma-coherent;
+ 			status = "disabled";
+ 		};
+@@ -214,43 +224,89 @@
+ 		};
+ 
+ 		clockgen: clocking@1ee1000 {
+-			#address-cells = <1>;
+-			#size-cells = <1>;
+-			ranges = <0x0 0x0 0x1ee1000 0x10000>;
++			compatible = "fsl,ls1021a-clockgen";
++			reg = <0x0 0x1ee1000 0x0 0x1000>;
++			#clock-cells = <2>;
++			clocks = <&sysclk>;
++		};
+ 
+-			sysclk: sysclk {
+-				compatible = "fixed-clock";
+-				#clock-cells = <0>;
+-				clock-output-names = "sysclk";
+-			};
+-
+-			cga_pll1: pll@800 {
+-				compatible = "fsl,qoriq-core-pll-2.0";
+-				#clock-cells = <1>;
+-				reg = <0x800 0x10>;
+-				clocks = <&sysclk>;
+-				clock-output-names = "cga-pll1", "cga-pll1-div2",
+-						     "cga-pll1-div4";
+-			};
+-
+-			platform_clk: pll@c00 {
+-				compatible = "fsl,qoriq-core-pll-2.0";
+-				#clock-cells = <1>;
+-				reg = <0xc00 0x10>;
+-				clocks = <&sysclk>;
+-				clock-output-names = "platform-clk", "platform-clk-div2";
+-			};
+-
+-			cluster1_clk: clk0c0@0 {
+-				compatible = "fsl,qoriq-core-mux-2.0";
+-				#clock-cells = <0>;
+-				reg = <0x0 0x10>;
+-				clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
+-				clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
+-				clock-output-names = "cluster1-clk";
++		tmu: tmu@1f00000 {
++			compatible = "fsl,qoriq-tmu";
++			reg = <0x0 0x1f00000 0x0 0x10000>;
++			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++			fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
++			fsl,tmu-calibration = <0x00000000 0x0000000f
++					       0x00000001 0x00000017
++					       0x00000002 0x0000001e
++					       0x00000003 0x00000026
++					       0x00000004 0x0000002e
++					       0x00000005 0x00000035
++					       0x00000006 0x0000003d
++					       0x00000007 0x00000044
++					       0x00000008 0x0000004c
++					       0x00000009 0x00000053
++					       0x0000000a 0x0000005b
++					       0x0000000b 0x00000064
++
++					       0x00010000 0x00000011
++					       0x00010001 0x0000001c
++					       0x00010002 0x00000024
++					       0x00010003 0x0000002b
++					       0x00010004 0x00000034
++					       0x00010005 0x00000039
++					       0x00010006 0x00000042
++					       0x00010007 0x0000004c
++					       0x00010008 0x00000051
++					       0x00010009 0x0000005a
++					       0x0001000a 0x00000063
++
++					       0x00020000 0x00000013
++					       0x00020001 0x00000019
++					       0x00020002 0x00000024
++					       0x00020003 0x0000002c
++					       0x00020004 0x00000035
++					       0x00020005 0x0000003d
++					       0x00020006 0x00000046
++					       0x00020007 0x00000050
++					       0x00020008 0x00000059
++
++					       0x00030000 0x00000002
++					       0x00030001 0x0000000d
++					       0x00030002 0x00000019
++					       0x00030003 0x00000024>;
++			#thermal-sensor-cells = <1>;
++		};
++
++		thermal-zones {
++			cpu_thermal: cpu-thermal {
++				polling-delay-passive = <1000>;
++				polling-delay = <5000>;
++
++				thermal-sensors = <&tmu 0>;
++
++				trips {
++					cpu_alert: cpu-alert {
++						temperature = <85000>;
++						hysteresis = <2000>;
++						type = "passive";
++					};
++					cpu_crit: cpu-crit {
++						temperature = <95000>;
++						hysteresis = <2000>;
++						type = "critical";
++					};
++				};
++
++				cooling-maps {
++					map0 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu0 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++				};
+ 			};
+ 		};
+-
+ 		dspi0: dspi@2100000 {
+ 			compatible = "fsl,ls1021a-v1.0-dspi";
+ 			#address-cells = <1>;
+@@ -258,7 +314,7 @@
+ 			reg = <0x0 0x2100000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ 			clock-names = "dspi";
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			spi-num-chipselects = <6>;
+ 			big-endian;
+ 			status = "disabled";
+@@ -271,31 +327,48 @@
+ 			reg = <0x0 0x2110000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ 			clock-names = "dspi";
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			spi-num-chipselects = <6>;
+ 			big-endian;
+ 			status = "disabled";
+ 		};
+ 
++		qspi: quadspi@1550000 {
++			compatible = "fsl,ls1021a-qspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x1550000 0x0 0x10000>,
++				<0x0 0x40000000 0x0 0x4000000>;
++			reg-names = "QuadSPI", "QuadSPI-memory";
++			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
++			clock-names = "qspi_en", "qspi";
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++			big-endian;
++			amba-base = <0x40000000>;
++			status = "disabled";
++		};
++
+ 		i2c0: i2c@2180000 {
+-			compatible = "fsl,vf610-i2c";
++			compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			reg = <0x0 0x2180000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ 			clock-names = "i2c";
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
++			fsl-scl-gpio = <&gpio3 23 0>;
+ 			status = "disabled";
+ 		};
+ 
+ 		i2c1: i2c@2190000 {
+-			compatible = "fsl,vf610-i2c";
++			compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			reg = <0x0 0x2190000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ 			clock-names = "i2c";
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
++			fsl-scl-gpio = <&gpio3 23 0>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -306,7 +379,7 @@
+ 			reg = <0x0 0x21a0000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ 			clock-names = "i2c";
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -399,7 +472,7 @@
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x2960000 0x0 0x1000>;
+ 			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			clock-names = "ipg";
+ 			status = "disabled";
+ 		};
+@@ -408,7 +481,7 @@
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x2970000 0x0 0x1000>;
+ 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			clock-names = "ipg";
+ 			status = "disabled";
+ 		};
+@@ -417,7 +490,7 @@
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x2980000 0x0 0x1000>;
+ 			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			clock-names = "ipg";
+ 			status = "disabled";
+ 		};
+@@ -426,7 +499,7 @@
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x2990000 0x0 0x1000>;
+ 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			clock-names = "ipg";
+ 			status = "disabled";
+ 		};
+@@ -435,16 +508,26 @@
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x29a0000 0x0 0x1000>;
+ 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			clock-names = "ipg";
+ 			status = "disabled";
+ 		};
+ 
++		ftm0: ftm0@29d0000 {
++			compatible = "fsl,ls1021a-ftm";
++			reg = <0x0 0x29d0000 0x0 0x10000>,
++			      <0x0 0x1ee2140 0x0 0x4>;
++			reg-names = "ftm", "FlexTimer1";
++			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++			big-endian;
++			status = "okay";
++		};
++
+ 		wdog0: watchdog@2ad0000 {
+ 			compatible = "fsl,imx21-wdt";
+ 			reg = <0x0 0x2ad0000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>;
++			clocks = <&clockgen 4 1>;
+ 			clock-names = "wdog-en";
+ 			big-endian;
+ 		};
+@@ -454,8 +537,8 @@
+ 			compatible = "fsl,vf610-sai";
+ 			reg = <0x0 0x2b50000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>, <&platform_clk 1>,
+-				 <&platform_clk 1>, <&platform_clk 1>;
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
++				 <&clockgen 4 1>, <&clockgen 4 1>;
+ 			clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ 			dma-names = "tx", "rx";
+ 			dmas = <&edma0 1 47>,
+@@ -468,8 +551,8 @@
+ 			compatible = "fsl,vf610-sai";
+ 			reg = <0x0 0x2b60000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 1>, <&platform_clk 1>,
+-				 <&platform_clk 1>, <&platform_clk 1>;
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
++				 <&clockgen 4 1>, <&clockgen 4 1>;
+ 			clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ 			dma-names = "tx", "rx";
+ 			dmas = <&edma0 1 45>,
+@@ -489,16 +572,31 @@
+ 			dma-channels = <32>;
+ 			big-endian;
+ 			clock-names = "dmamux0", "dmamux1";
+-			clocks = <&platform_clk 1>,
+-				 <&platform_clk 1>;
++			clocks = <&clockgen 4 1>,
++				 <&clockgen 4 1>;
++		};
++
++		qdma: qdma@8390000 {
++			compatible = "fsl,ls1021a-qdma";
++			reg = <0x0 0x8398000 0x0 0x1000>, /* Controller regs */
++			      <0x0 0x8399000 0x0 0x1000>, /* Status regs */
++			      <0x0 0x839a000 0x0 0x2000>; /* Block regs */
++			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "qdma-error", "qdma-queue";
++			channels = <8>;
++			queues = <2>;
++			status-sizes = <64>;
++			queue-sizes = <64 64>;
++			big-endian;
+ 		};
+ 
+ 		dcu: dcu@2ce0000 {
+ 			compatible = "fsl,ls1021a-dcu";
+ 			reg = <0x0 0x2ce0000 0x0 0x10000>;
+ 			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+-			clocks = <&platform_clk 0>,
+-				<&platform_clk 0>;
++			clocks = <&clockgen 4 0>,
++				<&clockgen 4 0>;
+ 			clock-names = "dcu", "pix";
+ 			big-endian;
+ 			status = "disabled";
+@@ -626,7 +724,11 @@
+ 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ 			dr_mode = "host";
+ 			snps,quirk-frame-length-adjustment = <0x20>;
++			configure-gfladj;
++			dma-coherent;
+ 			snps,dis_rxdet_inp3_quirk;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
+ 		};
+ 
+ 		pcie@3400000 {
+@@ -634,7 +736,9 @@
+ 			reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
+ 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names = "regs", "config";
+-			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
++			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
++					   <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++			interrupt-names = "pme", "aer";
+ 			fsl,pcie-scfg = <&scfg 0>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+@@ -643,7 +747,7 @@
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&msi1>;
++			msi-parent = <&msi1>, <&msi2>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
+@@ -657,7 +761,9 @@
+ 			reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
+ 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names = "regs", "config";
+-			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
++					   <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++			interrupt-names = "pme", "aer";
+ 			fsl,pcie-scfg = <&scfg 1>;
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+@@ -666,7 +772,7 @@
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&msi2>;
++			msi-parent = <&msi1>, <&msi2>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
+@@ -674,5 +780,45 @@
+ 					<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ 					<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ 		};
++
++		can0: can@2a70000 {
++			compatible = "fsl,ls1021ar2-flexcan";
++			reg = <0x0 0x2a70000 0x0 0x1000>;
++			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++			clock-names = "ipg", "per";
++			big-endian;
++			status = "disabled";
++		};
++
++		can1: can@2a80000 {
++			compatible = "fsl,ls1021ar2-flexcan";
++			reg = <0x0 0x2a80000 0x0 0x1000>;
++			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++			clock-names = "ipg", "per";
++			big-endian;
++			status = "disabled";
++		};
++
++		can2: can@2a90000 {
++			compatible = "fsl,ls1021ar2-flexcan";
++			reg = <0x0 0x2a90000 0x0 0x1000>;
++			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++			clock-names = "ipg", "per";
++			big-endian;
++			status = "disabled";
++		};
++
++		can3: can@2aa0000 {
++			compatible = "fsl,ls1021ar2-flexcan";
++			reg = <0x0 0x2aa0000 0x0 0x1000>;
++			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++			clock-names = "ipg", "per";
++			big-endian;
++			status = "disabled";
++		};
+ 	};
+ };
+--- a/arch/arm/boot/dts/mt6580.dtsi
++++ b/arch/arm/boot/dts/mt6580.dtsi
+@@ -91,7 +91,7 @@
+ 		#interrupt-cells = <3>;
+ 		interrupt-parent = <&gic>;
+ 		reg = <0x10211000 0x1000>,
+-		      <0x10212000 0x1000>,
++		      <0x10212000 0x2000>,
+ 		      <0x10214000 0x2000>,
+ 		      <0x10216000 0x2000>;
+ 	};
+--- a/arch/arm/boot/dts/mt6589.dtsi
++++ b/arch/arm/boot/dts/mt6589.dtsi
+@@ -102,7 +102,7 @@
+ 			#interrupt-cells = <3>;
+ 			interrupt-parent = <&gic>;
+ 			reg = <0x10211000 0x1000>,
+-			      <0x10212000 0x1000>,
++			      <0x10212000 0x2000>,
+ 			      <0x10214000 0x2000>,
+ 			      <0x10216000 0x2000>;
+ 		};
+--- a/arch/arm/boot/dts/mt8127.dtsi
++++ b/arch/arm/boot/dts/mt8127.dtsi
+@@ -129,7 +129,7 @@
+ 			#interrupt-cells = <3>;
+ 			interrupt-parent = <&gic>;
+ 			reg = <0 0x10211000 0 0x1000>,
+-			      <0 0x10212000 0 0x1000>,
++			      <0 0x10212000 0 0x2000>,
+ 			      <0 0x10214000 0 0x2000>,
+ 			      <0 0x10216000 0 0x2000>;
+ 		};
+--- a/arch/arm/boot/dts/mt8135.dtsi
++++ b/arch/arm/boot/dts/mt8135.dtsi
+@@ -221,7 +221,7 @@
+ 			#interrupt-cells = <3>;
+ 			interrupt-parent = <&gic>;
+ 			reg = <0 0x10211000 0 0x1000>,
+-			      <0 0x10212000 0 0x1000>,
++			      <0 0x10212000 0 0x2000>,
+ 			      <0 0x10214000 0 0x2000>,
+ 			      <0 0x10216000 0 0x2000>;
+ 		};
+--- a/arch/arm/boot/dts/rk3288.dtsi
++++ b/arch/arm/boot/dts/rk3288.dtsi
+@@ -1109,7 +1109,7 @@
+ 		#address-cells = <0>;
+ 
+ 		reg = <0xffc01000 0x1000>,
+-		      <0xffc02000 0x1000>,
++		      <0xffc02000 0x2000>,
+ 		      <0xffc04000 0x2000>,
+ 		      <0xffc06000 0x2000>;
+ 		interrupts = <GIC_PPI 9 0xf04>;
+--- a/arch/arm/boot/dts/sun6i-a31.dtsi
++++ b/arch/arm/boot/dts/sun6i-a31.dtsi
+@@ -791,7 +791,7 @@
+ 		gic: interrupt-controller@01c81000 {
+ 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ 			reg = <0x01c81000 0x1000>,
+-			      <0x01c82000 0x1000>,
++			      <0x01c82000 0x2000>,
+ 			      <0x01c84000 0x2000>,
+ 			      <0x01c86000 0x2000>;
+ 			interrupt-controller;
+--- a/arch/arm/boot/dts/sun7i-a20.dtsi
++++ b/arch/arm/boot/dts/sun7i-a20.dtsi
+@@ -1685,9 +1685,9 @@
+ 		};
+ 
+ 		gic: interrupt-controller@01c81000 {
+-			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
++			compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ 			reg = <0x01c81000 0x1000>,
+-			      <0x01c82000 0x1000>,
++			      <0x01c82000 0x2000>,
+ 			      <0x01c84000 0x2000>,
+ 			      <0x01c86000 0x2000>;
+ 			interrupt-controller;
+--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
++++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+@@ -488,7 +488,7 @@
+ 		gic: interrupt-controller@01c81000 {
+ 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ 			reg = <0x01c81000 0x1000>,
+-			      <0x01c82000 0x1000>,
++			      <0x01c82000 0x2000>,
+ 			      <0x01c84000 0x2000>,
+ 			      <0x01c86000 0x2000>;
+ 			interrupt-controller;
+--- a/arch/arm/boot/dts/sun9i-a80.dtsi
++++ b/arch/arm/boot/dts/sun9i-a80.dtsi
+@@ -613,7 +613,7 @@
+ 		gic: interrupt-controller@01c41000 {
+ 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ 			reg = <0x01c41000 0x1000>,
+-			      <0x01c42000 0x1000>,
++			      <0x01c42000 0x2000>,
+ 			      <0x01c44000 0x2000>,
+ 			      <0x01c46000 0x2000>;
+ 			interrupt-controller;
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -1,8 +1,26 @@
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+  
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts
+@@ -0,0 +1,123 @@
++/*
++ * Device Tree file for NXP LS1012A 2G5RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++	model = "LS1012A 2G5RDB Board";
++	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++
++	aliases {
++		ethernet0 = &pfe_mac0;
++		ethernet1 = &pfe_mac1;
++	};
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++};
++
++&qspi {
++	num-cs = <2>;
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: s25fs512s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		m25p,fast-read;
++		reg = <0>;
++	};
++};
++
++&sata {
++	status = "okay";
++};
++
++&pfe {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	ethernet@0 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x0>;	/* GEM_ID */
++		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
++		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii-2500";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x1>; /* enabled/disabled */
++		};
++	};
++
++	ethernet@1 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x1>;	/* GEM_ID */
++		fsl,gemac-bus-id = < 0x0>;	/* BUS_ID */
++		fsl,gemac-phy-id = < 0x2>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii-2500";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x0>; /* enabled/disabled */
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+@@ -0,0 +1,141 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Freescale LS1012A Freedom Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++	model = "LS1012A Freedom Board";
++	compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
++
++	aliases {
++		ethernet0 = &pfe_mac0;
++		ethernet1 = &pfe_mac1;
++	};
++
++	sys_mclk: clock-mclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <25000000>;
++	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "1P8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,widgets =
++			"Microphone", "Microphone Jack",
++			"Headphone", "Headphone Jack",
++			"Speaker", "Speaker Ext",
++			"Line", "Line In Jack";
++		simple-audio-card,routing =
++			"MIC_IN", "Microphone Jack",
++			"Microphone Jack", "Mic Bias",
++			"LINE_IN", "Line In Jack",
++			"Headphone Jack", "HP_OUT",
++			"Speaker Ext", "LINE_OUT";
++
++		simple-audio-card,cpu {
++			sound-dai = <&sai2>;
++			frame-master;
++			bitclock-master;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&codec>;
++			frame-master;
++			bitclock-master;
++			system-clock-frequency = <25000000>;
++		};
++	};
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	codec: sgtl5000@a {
++		#sound-dai-cells = <0>;
++		compatible = "fsl,sgtl5000";
++		reg = <0xa>;
++		VDDA-supply = <&reg_1p8v>;
++		VDDIO-supply = <&reg_1p8v>;
++		clocks = <&sys_mclk>;
++	};
++};
++
++&qspi {
++	num-cs = <1>;
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: s25fs512s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		m25p,fast-read;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++};
++
++&pfe {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	ethernet@0 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x0>;	/* GEM_ID */
++		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
++		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x1>; /* enabled/disabled */
++		};
++	};
++
++	ethernet@1 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x1>;	/* GEM_ID */
++		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
++		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x0>; /* enabled/disabled */
++		};
++	};
++};
++
++&sai2 {
++	status = "okay";
++};
++
++&sata {
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
+@@ -0,0 +1,177 @@
++/*
++ * Device Tree file for NXP LS1012A FRWY Board.
++ *
++ * Copyright 2018 NXP
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++	model = "LS1012A FRWY Board";
++	compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
++
++	aliases {
++		ethernet0 = &pfe_mac0;
++		ethernet1 = &pfe_mac1;
++	};
++
++	sys_mclk: clock-mclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <25000000>;
++	};
++
++	reg_1p8v: regulator-1p8v {
++		compatible = "regulator-fixed";
++		regulator-name = "1P8V";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,widgets =
++			"Microphone", "Microphone Jack",
++			"Headphone", "Headphone Jack",
++			"Speaker", "Speaker Ext",
++			"Line", "Line In Jack";
++		simple-audio-card,routing =
++			"MIC_IN", "Microphone Jack",
++			"Microphone Jack", "Mic Bias",
++			"LINE_IN", "Line In Jack",
++			"Headphone Jack", "HP_OUT",
++			"Speaker Ext", "LINE_OUT";
++
++		simple-audio-card,cpu {
++			sound-dai = <&sai2>;
++			frame-master;
++			bitclock-master;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&codec>;
++			frame-master;
++			bitclock-master;
++			system-clock-frequency = <25000000>;
++		};
++	};
++};
++
++&pcie {
++	status = "okay";
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	codec: sgtl5000@a {
++		compatible = "fsl,sgtl5000";
++		#sound-dai-cells = <0>;
++		reg = <0xa>;
++		VDDA-supply = <&reg_1p8v>;
++		VDDIO-supply = <&reg_1p8v>;
++		clocks = <&sys_mclk>;
++	};
++};
++
++&qspi {
++	num-cs = <1>;
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: w25q16dw@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		m25p,fast-read;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++};
++
++&pfe {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	ethernet@0 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x0>;	/* GEM_ID */
++		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
++		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x1>; /* enabled/disabled */
++		};
++	};
++
++	ethernet@1 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x1>;	/* GEM_ID */
++		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
++		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x0>; /* enabled/disabled */
++		};
++	};
++};
++
++&sai2 {
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+@@ -0,0 +1,166 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Freescale LS1012A QDS Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++	model = "LS1012A QDS Board";
++	compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
++
++	aliases {
++		ethernet0 = &pfe_mac0;
++		ethernet1 = &pfe_mac1;
++	};
++
++	sys_mclk: clock-mclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <24576000>;
++	};
++
++	reg_3p3v: regulator-3p3v {
++		compatible = "regulator-fixed";
++		regulator-name = "3P3V";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,widgets =
++			"Microphone", "Microphone Jack",
++			"Headphone", "Headphone Jack",
++			"Speaker", "Speaker Ext",
++			"Line", "Line In Jack";
++		simple-audio-card,routing =
++			"MIC_IN", "Microphone Jack",
++			"Microphone Jack", "Mic Bias",
++			"LINE_IN", "Line In Jack",
++			"Headphone Jack", "HP_OUT",
++			"Speaker Ext", "LINE_OUT";
++
++		simple-audio-card,cpu {
++			sound-dai = <&sai2>;
++			frame-master;
++			bitclock-master;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&codec>;
++			frame-master;
++			bitclock-master;
++			system-clock-frequency = <24576000>;
++		};
++	};
++};
++
++&pcie {
++	status = "okay";
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	pca9547@77 {
++		compatible = "nxp,pca9547";
++		reg = <0x77>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		i2c@4 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x4>;
++
++			codec: sgtl5000@a {
++				#sound-dai-cells = <0>;
++				compatible = "fsl,sgtl5000";
++				reg = <0xa>;
++				VDDA-supply = <&reg_3p3v>;
++				VDDIO-supply = <&reg_3p3v>;
++				clocks = <&sys_mclk>;
++			};
++		};
++	};
++};
++
++&qspi {
++	num-cs = <2>;
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: s25fs512s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		m25p,fast-read;
++		reg = <0>;
++	};
++};
++
++&pfe {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	ethernet@0 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x0>;	/* GEM_ID */
++		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
++		fsl,gemac-phy-id = <0x1>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x2>;
++		phy-mode = "sgmii-2500";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x1>; /* enabled/disabled */
++		};
++	};
++
++	ethernet@1 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x1>;	/* GEM_ID */
++		fsl,gemac-bus-id = <0x1>;	/* BUS_ID */
++		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x3>;
++		phy-mode = "sgmii-2500";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x0>; /* enabled/disabled */
++		};
++	};
++};
++
++&sai2 {
++	status = "okay";
++};
++
++&sata {
++	status = "okay";
++};
++
++&esdhc0 {
++	status = "okay";
++};
++
++&esdhc1 {
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+@@ -0,0 +1,102 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Freescale LS1012A RDB Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++	model = "LS1012A RDB Board";
++	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++
++	aliases {
++		ethernet0 = &pfe_mac0;
++		ethernet1 = &pfe_mac1;
++	};
++};
++
++&pcie {
++	status = "okay";
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++};
++
++&qspi {
++	num-cs = <2>;
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: s25fs512s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		m25p,fast-read;
++		reg = <0>;
++	};
++};
++
++&sata {
++	status = "okay";
++};
++
++&esdhc0 {
++	sd-uhs-sdr104;
++	sd-uhs-sdr50;
++	sd-uhs-sdr25;
++	sd-uhs-sdr12;
++	status = "okay";
++};
++
++&esdhc1 {
++	mmc-hs200-1_8v;
++	status = "okay";
++};
++
++&pfe {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	ethernet@0 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x0>;	/* GEM_ID */
++		fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
++		fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "sgmii";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x1>; /* enabled/disabled */
++		};
++	};
++
++	ethernet@1 {
++		compatible = "fsl,pfe-gemac-port";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x1>;	/* GEM_ID */
++		fsl,gemac-bus-id = < 0x1 >;	/* BUS_ID */
++		fsl,gemac-phy-id = < 0x1 >;	/* PHY_ID */
++		fsl,mdio-mux-val = <0x0>;
++		phy-mode = "rgmii-txid";
++		fsl,pfe-phy-if-flags = <0x0>;
++
++		mdio@0 {
++			reg = <0x0>; /* enabled/disabled */
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+@@ -0,0 +1,567 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ */
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++	compatible = "fsl,ls1012a";
++	interrupt-parent = <&gic>;
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	aliases {
++		crypto = &crypto;
++		rtic_a = &rtic_a;
++		rtic_b = &rtic_b;
++		rtic_c = &rtic_c;
++		rtic_d = &rtic_d;
++		sec_mon = &sec_mon;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x0>;
++			clocks = <&clockgen 1 0>;
++			#cooling-cells = <2>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++	};
++
++	idle-states {
++		/*
++		 * PSCI node is not added default, U-boot will add missing
++		 * parts if it determines to use PSCI.
++		 */
++		entry-method = "arm,psci";
++
++		CPU_PH20: cpu-ph20 {
++			compatible = "arm,idle-state";
++			idle-state-name = "PH20";
++			arm,psci-suspend-param = <0x0>;
++			entry-latency-us = <1000>;
++			exit-latency-us = <1000>;
++			min-residency-us = <3000>;
++		};
++	};
++
++	sysclk: sysclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <125000000>;
++		clock-output-names = "sysclk";
++	};
++
++	coreclk: coreclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <100000000>;
++		clock-output-names = "coreclk";
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
++			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
++			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
++			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
++	};
++
++	pmu {
++		compatible = "arm,armv8-pmuv3";
++		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	gic: interrupt-controller@1400000 {
++		compatible = "arm,gic-400";
++		#interrupt-cells = <3>;
++		interrupt-controller;
++		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
++		      <0x0 0x1402000 0 0x2000>, /* GICC */
++		      <0x0 0x1404000 0 0x2000>, /* GICH */
++		      <0x0 0x1406000 0 0x2000>; /* GICV */
++		interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
++	};
++
++	reboot {
++		compatible = "syscon-reboot";
++		regmap = <&dcfg>;
++		offset = <0xb0>;
++		mask = <0x02>;
++	};
++
++	soc {
++		compatible = "simple-bus";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		scfg: scfg@1570000 {
++			compatible = "fsl,ls1012a-scfg", "syscon";
++			reg = <0x0 0x1570000 0x0 0x10000>;
++			big-endian;
++		};
++
++		crypto: crypto@1700000 {
++			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
++				     "fsl,sec-v4.0";
++			fsl,sec-era = <8>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0x0 0x00 0x1700000 0x100000>;
++			reg = <0x00 0x1700000 0x0 0x100000>;
++			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++
++			sec_jr0: jr@10000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x10000 0x10000>;
++				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr1: jr@20000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x20000 0x10000>;
++				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr2: jr@30000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x30000 0x10000>;
++				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr3: jr@40000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x40000 0x10000>;
++				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			caam-dma {
++				compatible = "fsl,sec-v5.4-dma",
++					     "fsl,sec-v5.0-dma",
++					     "fsl,sec-v4.0-dma";
++			};
++
++			rtic@60000 {
++				compatible = "fsl,sec-v5.4-rtic",
++					     "fsl,sec-v5.0-rtic",
++					     "fsl,sec-v4.0-rtic";
++				#address-cells = <1>;
++				#size-cells = <1>;
++				reg = <0x60000 0x100 0x60e00 0x18>;
++				ranges = <0x0 0x60100 0x500>;
++
++				rtic_a: rtic-a@0 {
++					compatible = "fsl,sec-v5.4-rtic-memory",
++						     "fsl,sec-v5.0-rtic-memory",
++						     "fsl,sec-v4.0-rtic-memory";
++					reg = <0x00 0x20 0x100 0x100>;
++				};
++
++				rtic_b: rtic-b@20 {
++					compatible = "fsl,sec-v5.4-rtic-memory",
++						     "fsl,sec-v5.0-rtic-memory",
++						     "fsl,sec-v4.0-rtic-memory";
++					reg = <0x20 0x20 0x200 0x100>;
++				};
++
++				rtic_c: rtic-c@40 {
++					compatible = "fsl,sec-v5.4-rtic-memory",
++						     "fsl,sec-v5.0-rtic-memory",
++						     "fsl,sec-v4.0-rtic-memory";
++					reg = <0x40 0x20 0x300 0x100>;
++				};
++
++				rtic_d: rtic-d@60 {
++					compatible = "fsl,sec-v5.4-rtic-memory",
++						     "fsl,sec-v5.0-rtic-memory",
++						     "fsl,sec-v4.0-rtic-memory";
++					reg = <0x60 0x20 0x400 0x100>;
++				};
++			};
++		};
++
++		sec_mon: sec_mon@1e90000 {
++			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
++				     "fsl,sec-v4.0-mon";
++			reg = <0x0 0x1e90000 0x0 0x10000>;
++			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		dcfg: dcfg@1ee0000 {
++			compatible = "fsl,ls1012a-dcfg",
++				     "syscon";
++			reg = <0x0 0x1ee0000 0x0 0x10000>;
++			big-endian;
++		};
++
++		clockgen: clocking@1ee1000 {
++			compatible = "fsl,ls1012a-clockgen";
++			reg = <0x0 0x1ee1000 0x0 0x1000>;
++			#clock-cells = <2>;
++			clocks = <&sysclk &coreclk>;
++			clock-names = "sysclk", "coreclk";
++		};
++
++		tmu: tmu@1f00000 {
++			compatible = "fsl,qoriq-tmu";
++			reg = <0x0 0x1f00000 0x0 0x10000>;
++			interrupts = <0 33 0x4>;
++			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++			fsl,tmu-calibration = <0x00000000 0x00000026
++					       0x00000001 0x0000002d
++					       0x00000002 0x00000032
++					       0x00000003 0x00000039
++					       0x00000004 0x0000003f
++					       0x00000005 0x00000046
++					       0x00000006 0x0000004d
++					       0x00000007 0x00000054
++					       0x00000008 0x0000005a
++					       0x00000009 0x00000061
++					       0x0000000a 0x0000006a
++					       0x0000000b 0x00000071
++
++					       0x00010000 0x00000025
++					       0x00010001 0x0000002c
++					       0x00010002 0x00000035
++					       0x00010003 0x0000003d
++					       0x00010004 0x00000045
++					       0x00010005 0x0000004e
++					       0x00010006 0x00000057
++					       0x00010007 0x00000061
++					       0x00010008 0x0000006b
++					       0x00010009 0x00000076
++
++					       0x00020000 0x00000029
++					       0x00020001 0x00000033
++					       0x00020002 0x0000003d
++					       0x00020003 0x00000049
++					       0x00020004 0x00000056
++					       0x00020005 0x00000061
++					       0x00020006 0x0000006d
++
++					       0x00030000 0x00000021
++					       0x00030001 0x0000002a
++					       0x00030002 0x0000003c
++					       0x00030003 0x0000004e>;
++			big-endian;
++			#thermal-sensor-cells = <1>;
++		};
++
++		thermal-zones {
++			cpu_thermal: cpu-thermal {
++				polling-delay-passive = <1000>;
++				polling-delay = <5000>;
++				thermal-sensors = <&tmu 0>;
++
++				trips {
++					cpu_alert: cpu-alert {
++						temperature = <85000>;
++						hysteresis = <2000>;
++						type = "passive";
++					};
++
++					cpu_crit: cpu-crit {
++						temperature = <95000>;
++						hysteresis = <2000>;
++						type = "critical";
++					};
++				};
++
++				cooling-maps {
++					map0 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu0 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++				};
++			};
++		};
++
++		esdhc0: esdhc@1560000 {
++			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
++			reg = <0x0 0x1560000 0x0 0x10000>;
++			interrupts = <0 62 0x4>;
++			clocks = <&clockgen 4 0>;
++			voltage-ranges = <1800 1800 3300 3300>;
++			sdhci,auto-cmd12;
++			big-endian;
++			bus-width = <4>;
++			status = "disabled";
++		};
++
++		esdhc1: esdhc@1580000 {
++			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
++			reg = <0x0 0x1580000 0x0 0x10000>;
++			interrupts = <0 65 0x4>;
++			clocks = <&clockgen 4 0>;
++			voltage-ranges = <1800 1800 3300 3300>;
++			sdhci,auto-cmd12;
++			big-endian;
++			broken-cd;
++			bus-width = <4>;
++			status = "disabled";
++		};
++
++		rcpm: rcpm@1ee2000 {
++			compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
++			reg = <0x0 0x1ee2000 0x0 0x1000>;
++			fsl,#rcpm-wakeup-cells = <1>;
++		};
++
++		ftm0: ftm0@29d0000 {
++			compatible = "fsl,ls1012a-ftm";
++			reg = <0x0 0x29d0000 0x0 0x10000>,
++			      <0x0 0x1ee2140 0x0 0x4>;
++			reg-names = "ftm", "FlexTimer1";
++			interrupts = <0 86 0x4>;
++			big-endian;
++		};
++
++		i2c0: i2c@2180000 {
++			compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2180000 0x0 0x10000>;
++			interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 3>;
++			fsl-scl-gpio = <&gpio0 13 0>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@2190000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2190000 0x0 0x10000>;
++			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 3>;
++			status = "disabled";
++		};
++
++		duart0: serial@21c0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x00 0x21c0500 0x0 0x100>;
++			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 0>;
++			status = "disabled";
++		};
++
++		duart1: serial@21c0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x00 0x21c0600 0x0 0x100>;
++			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 0>;
++			status = "disabled";
++		};
++
++		gpio0: gpio@2300000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2300000 0x0 0x10000>;
++			interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio1: gpio@2310000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2310000 0x0 0x10000>;
++			interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		qspi: quadspi@1550000 {
++			compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x1550000 0x0 0x10000>,
++				<0x0 0x40000000 0x0 0x10000000>;
++			reg-names = "QuadSPI", "QuadSPI-memory";
++			interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
++			clock-names = "qspi_en", "qspi";
++			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
++			big-endian;
++			fsl,qspi-has-second-chip;
++			status = "disabled";
++		};
++
++		wdog0: wdog@2ad0000 {
++			compatible = "fsl,ls1012a-wdt",
++				     "fsl,imx21-wdt";
++			reg = <0x0 0x2ad0000 0x0 0x10000>;
++			interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 0>;
++			big-endian;
++		};
++
++		sai1: sai@2b50000 {
++			#sound-dai-cells = <0>;
++			compatible = "fsl,vf610-sai";
++			reg = <0x0 0x2b50000 0x0 0x10000>;
++			interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>,
++				 <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "bus", "mclk1", "mclk2", "mclk3";
++			dma-names = "tx", "rx";
++			dmas = <&edma0 1 47>,
++			       <&edma0 1 46>;
++			status = "disabled";
++		};
++
++		sai2: sai@2b60000 {
++			#sound-dai-cells = <0>;
++			compatible = "fsl,vf610-sai";
++			reg = <0x0 0x2b60000 0x0 0x10000>;
++			interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>,
++				 <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "bus", "mclk1", "mclk2", "mclk3";
++			dma-names = "tx", "rx";
++			dmas = <&edma0 1 45>,
++			       <&edma0 1 44>;
++			status = "disabled";
++		};
++
++		edma0: edma@2c00000 {
++			#dma-cells = <2>;
++			compatible = "fsl,vf610-edma";
++			reg = <0x0 0x2c00000 0x0 0x10000>,
++			      <0x0 0x2c10000 0x0 0x10000>,
++			      <0x0 0x2c20000 0x0 0x10000>;
++			interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
++				     <0 103 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "edma-tx", "edma-err";
++			dma-channels = <32>;
++			big-endian;
++			clock-names = "dmamux0", "dmamux1";
++			clocks = <&clockgen 4 3>,
++				 <&clockgen 4 3>;
++		};
++
++		usb0: usb3@2f00000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x2f00000 0x0 0x10000>;
++			interrupts = <0 60 0x4>;
++			dr_mode = "host";
++			snps,quirk-frame-length-adjustment = <0x20>;
++			snps,dis_rxdet_inp3_quirk;
++		};
++
++		usb1: usb2@8600000 {
++			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
++			reg = <0x0 0x8600000 0x0 0x1000>;
++			interrupts = <0 139 0x4>;
++			dr_mode = "host";
++			phy_type = "ulpi";
++		};
++
++		sata: sata@3200000 {
++			compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
++			reg = <0x0 0x3200000 0x0 0x10000>,
++				<0x0 0x20140520 0x0 0x4>;
++			reg-names = "ahci", "sata-ecc";
++			interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 0>;
++			dma-coherent;
++			status = "disabled";
++		};
++
++		msi: msi-controller1@1572000 {
++			compatible = "fsl,ls1012a-msi";
++			reg = <0x0 0x1572000 0x0 0x8>;
++			msi-controller;
++			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pcie: pcie@3400000 {
++			compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
++			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 118 0x4>, /* AER interrupt */
++				     <0 117 0x4>; /* PME interrupt */
++			interrupt-names = "aer", "pme";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
++			status = "disabled";
++		};
++	};
++
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		pfe_reserved: packetbuffer@83400000 {
++			reg = <0 0x83400000 0 0xc00000>;
++		};
++	};
++
++	pfe: pfe@04000000 {
++		compatible = "fsl,pfe";
++		reg =   <0x0 0x04000000 0x0 0xc00000>,	/* AXI 16M */
++			<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */
++		reg-names = "pfe", "pfe-ddr";
++		fsl,pfe-num-interfaces = <0x2>;
++		interrupts = <0 172 0x4>,    /* HIF interrupt */
++			     <0 173 0x4>,    /*HIF_NOCPY interrupt */
++			     <0 174 0x4>;    /* WoL interrupt */
++		interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
++		memory-region = <&pfe_reserved>;
++		fsl,pfe-scfg = <&scfg 0>;
++		fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
++		clocks = <&clockgen 4 0>;
++		clock-names = "pfe";
++
++		status = "okay";
++		pfe_mac0: ethernet@0 {
++		};
++
++		pfe_mac1: ethernet@1 {
++		};
++	};
++
++	firmware {
++		optee {
++			compatible = "linaro,optee-tz";
++			method = "smc";
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
+@@ -0,0 +1,44 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 device tree nodes for ls1043
++ *
++ * Copyright 2015-2016 Freescale Semiconductor Inc.
++ */
++
++&soc {
++
++/* include used FMan blocks */
++#include "qoriq-fman3-0.dtsi"
++#include "qoriq-fman3-0-1g-0.dtsi"
++#include "qoriq-fman3-0-1g-1.dtsi"
++#include "qoriq-fman3-0-1g-2.dtsi"
++#include "qoriq-fman3-0-1g-3.dtsi"
++#include "qoriq-fman3-0-1g-4.dtsi"
++#include "qoriq-fman3-0-1g-5.dtsi"
++#include "qoriq-fman3-0-10g-0.dtsi"
++
++};
++
++&fman0 {
++	/* these aliases provide the FMan ports mapping */
++	enet0: ethernet@e0000 {
++	};
++
++	enet1: ethernet@e2000 {
++	};
++
++	enet2: ethernet@e4000 {
++	};
++
++	enet3: ethernet@e6000 {
++	};
++
++	enet4: ethernet@e8000 {
++	};
++
++	enet5: ethernet@ea000 {
++	};
++
++	enet6: ethernet@f0000 {
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+@@ -0,0 +1,71 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1043a-qds.dts"
++#include "qoriq-qman-portals-sdk.dtsi"
++#include "qoriq-bman-portals-sdk.dtsi"
++
++&bman_fbpr {
++	compatible = "fsl,bman-fbpr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++	compatible = "fsl,qman-fqd";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++	compatible = "fsl,qman-pfdr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fman0 {
++	compatible = "fsl,fman", "simple-bus";
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+@@ -1,51 +1,14 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+  *
+- * Copyright 2014-2015, Freescale Semiconductor
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+  *
+  * Mingkai Hu <Mingkai.hu@freescale.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- *  a) This library is free software; you can redistribute it and/or
+- *     modify it under the terms of the GNU General Public License as
+- *     published by the Free Software Foundation; either version 2 of the
+- *     License, or (at your option) any later version.
+- *
+- *     This library is distributed in the hope that it will be useful,
+- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *     GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- *  b) Permission is hereby granted, free of charge, to any person
+- *     obtaining a copy of this software and associated documentation
+- *     files (the "Software"), to deal in the Software without
+- *     restriction, including without limitation the rights to use,
+- *     copy, modify, merge, publish, distribute, sublicense, and/or
+- *     sell copies of the Software, and to permit persons to whom the
+- *     Software is furnished to do so, subject to the following
+- *     conditions:
+- *
+- *     The above copyright notice and this permission notice shall be
+- *     included in all copies or substantial portions of the Software.
+- *
+- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+ /dts-v1/;
+-/include/ "fsl-ls1043a.dtsi"
++#include "fsl-ls1043a.dtsi"
+ 
+ / {
+ 	model = "LS1043A QDS Board";
+@@ -60,6 +23,22 @@
+ 		serial1 = &duart1;
+ 		serial2 = &duart2;
+ 		serial3 = &duart3;
++		sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
++		sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
++		sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
++		sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
++		qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
++		qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
++		qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
++		qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
++		qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
++		qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
++		qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
++		qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
++		emi1_slot1 = &ls1043mdio_s1;
++		emi1_slot2 = &ls1043mdio_s2;
++		emi1_slot3 = &ls1043mdio_s3;
++		emi1_slot4 = &ls1043mdio_s4;
+ 	};
+ 
+ 	chosen {
+@@ -97,8 +76,11 @@
+ 	};
+ 
+ 	fpga: board-control@2,0 {
+-		compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
+ 		reg = <0x2 0x0 0x0000100>;
++		ranges = <0 2 0 0x100>;
+ 	};
+ };
+ 
+@@ -181,3 +163,149 @@
+ 		reg = <0>;
+ 	};
+ };
++
++#include "fsl-ls1043-post.dtsi"
++
++&fman0 {
++	ethernet@e0000 {
++		phy-handle = <&qsgmii_phy_s2_p1>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@e2000 {
++		phy-handle = <&qsgmii_phy_s2_p2>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@e4000 {
++		phy-handle = <&rgmii_phy1>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e6000 {
++		phy-handle = <&rgmii_phy2>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e8000 {
++		phy-handle = <&qsgmii_phy_s2_p3>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@ea000 {
++		phy-handle = <&qsgmii_phy_s2_p4>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@f0000 { /* DTSEC9/10GEC1 */
++		fixed-link = <1 1 10000 0 0>;
++		phy-connection-type = "xgmii";
++	};
++};
++
++&fpga {
++	mdio-mux-emi1 {
++		compatible = "mdio-mux-mmioreg", "mdio-mux";
++		mdio-parent-bus = <&mdio0>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x54 1>;    /* BRDCFG4 */
++		mux-mask = <0xe0>; /* EMI1 */
++
++		/* On-board RGMII1 PHY */
++		ls1043mdio0: mdio@0 {
++			reg = <0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
++				reg = <0x1>;
++			};
++		};
++
++		/* On-board RGMII2 PHY */
++		ls1043mdio1: mdio@1 {
++			reg = <0x20>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
++				reg = <0x2>;
++			};
++		};
++
++		/* Slot 1 */
++		ls1043mdio_s1: mdio@2 {
++			reg = <0x40>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			qsgmii_phy_s1_p1: ethernet-phy@4 {
++				reg = <0x4>;
++			};
++			qsgmii_phy_s1_p2: ethernet-phy@5 {
++				reg = <0x5>;
++			};
++			qsgmii_phy_s1_p3: ethernet-phy@6 {
++				reg = <0x6>;
++			};
++			qsgmii_phy_s1_p4: ethernet-phy@7 {
++				reg = <0x7>;
++			};
++
++			sgmii_phy_s1_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++
++		/* Slot 2 */
++		ls1043mdio_s2: mdio@3 {
++			reg = <0x60>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			qsgmii_phy_s2_p1: ethernet-phy@8 {
++				reg = <0x8>;
++			};
++			qsgmii_phy_s2_p2: ethernet-phy@9 {
++				reg = <0x9>;
++			};
++			qsgmii_phy_s2_p3: ethernet-phy@a {
++				reg = <0xa>;
++			};
++			qsgmii_phy_s2_p4: ethernet-phy@b {
++				reg = <0xb>;
++			};
++
++			sgmii_phy_s2_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++
++		/* Slot 3 */
++		ls1043mdio_s3: mdio@4 {
++			reg = <0x80>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			sgmii_phy_s3_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++
++		/* Slot 4 */
++		ls1043mdio_s4: mdio@5 {
++			reg = <0xa0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			sgmii_phy_s4_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+@@ -0,0 +1,71 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1043a-rdb.dts"
++#include "qoriq-qman-portals-sdk.dtsi"
++#include "qoriq-bman-portals-sdk.dtsi"
++
++&bman_fbpr {
++	compatible = "fsl,bman-fbpr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++	compatible = "fsl,qman-fqd";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++	compatible = "fsl,qman-pfdr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fman0 {
++	compatible = "fsl,fman", "simple-bus";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+@@ -0,0 +1,117 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include "fsl-ls1043a-rdb-sdk.dts"
++
++&soc {
++	bp7: buffer-pool@7 {
++		compatible = "fsl,p4080-bpool", "fsl,bpool";
++		fsl,bpid = <7>;
++		fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
++		fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
++	};
++
++	bp8: buffer-pool@8 {
++		compatible = "fsl,p4080-bpool", "fsl,bpool";
++		fsl,bpid = <8>;
++		fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
++		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++	};
++
++	bp9: buffer-pool@9 {
++		compatible = "fsl,p4080-bpool", "fsl,bpool";
++		fsl,bpid = <9>;
++		fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
++		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++	};
++
++	fsl,dpaa {
++		compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
++
++		ethernet@0 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
++			fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
++		};
++
++		ethernet@1 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
++			fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
++		};
++
++		ethernet@2 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
++			fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
++		};
++
++		ethernet@3 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
++			fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
++		};
++
++		ethernet@4 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
++			fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
++		};
++
++		ethernet@5 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
++			fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
++		};
++
++		ethernet@8 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
++			fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
++
++		};
++		dpa-fman0-oh@2 {
++			compatible = "fsl,dpa-oh";
++			/* Define frame queues for the OH port*/
++			/* <OH Rx error, OH Rx default> */
++			fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
++			fsl,fman-oh-port = <&fman0_oh2>;
++		};
++	};
++};
++/ {
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		usdpaa_mem: usdpaa_mem {
++			compatible = "fsl,usdpaa-mem";
++			alloc-ranges = <0 0 0x10000 0>;
++			size = <0 0x10000000>;
++			alignment = <0 0x10000000>;
++		};
++	};
++};
++
++&fman0 {
++	fman0_oh2: port@83000 {
++		cell-index = <1>;
++		compatible = "fsl,fman-port-oh";
++		reg = <0x83000 0x1000>;
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -1,51 +1,14 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+  *
+- * Copyright 2014-2015, Freescale Semiconductor
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+  *
+  * Mingkai Hu <Mingkai.hu@freescale.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- *  a) This library is free software; you can redistribute it and/or
+- *     modify it under the terms of the GNU General Public License as
+- *     published by the Free Software Foundation; either version 2 of the
+- *     License, or (at your option) any later version.
+- *
+- *     This library is distributed in the hope that it will be useful,
+- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *     GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- *  b) Permission is hereby granted, free of charge, to any person
+- *     obtaining a copy of this software and associated documentation
+- *     files (the "Software"), to deal in the Software without
+- *     restriction, including without limitation the rights to use,
+- *     copy, modify, merge, publish, distribute, sublicense, and/or
+- *     sell copies of the Software, and to permit persons to whom the
+- *     Software is furnished to do so, subject to the following
+- *     conditions:
+- *
+- *     The above copyright notice and this permission notice shall be
+- *     included in all copies or substantial portions of the Software.
+- *
+- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+ /dts-v1/;
+-/include/ "fsl-ls1043a.dtsi"
++#include "fsl-ls1043a.dtsi"
+ 
+ / {
+ 	model = "LS1043A RDB Board";
+@@ -86,6 +49,10 @@
+ 		compatible = "pericom,pt7c4338";
+ 		reg = <0x68>;
+ 	};
++	rtc@51 {
++		compatible = "nxp,pcf85263";
++		reg = <0x51>;
++	};
+ };
+ 
+ &ifc {
+@@ -130,6 +97,38 @@
+ 		reg = <0>;
+ 		spi-max-frequency = <1000000>; /* input clock */
+ 	};
++
++	slic@2 {
++		compatible = "maxim,ds26522";
++		reg = <2>;
++		spi-max-frequency = <2000000>;
++		fsl,spi-cs-sck-delay = <100>;
++		fsl,spi-sck-cs-delay = <50>;
++	};
++
++	slic@3 {
++		compatible = "maxim,ds26522";
++		reg = <3>;
++		spi-max-frequency = <2000000>;
++		fsl,spi-cs-sck-delay = <100>;
++		fsl,spi-sck-cs-delay = <50>;
++	};
++};
++
++&uqe {
++	ucc_hdlc: ucc@2000 {
++		compatible = "fsl,ucc-hdlc";
++		rx-clock-name = "clk8";
++		tx-clock-name = "clk9";
++		fsl,rx-sync-clock = "rsync_pin";
++		fsl,tx-sync-clock = "tsync_pin";
++		fsl,tx-timeslot-mask = <0xfffffffe>;
++		fsl,rx-timeslot-mask = <0xfffffffe>;
++		fsl,tdm-framer-type = "e1";
++		fsl,tdm-id = <0>;
++		fsl,siram-entry-id = <0>;
++		fsl,tdm-interface;
++	};
+ };
+ 
+ &duart0 {
+@@ -139,3 +138,76 @@
+ &duart1 {
+ 	status = "okay";
+ };
++
++#include "fsl-ls1043-post.dtsi"
++
++&fman0 {
++	ethernet@e0000 {
++		phy-handle = <&qsgmii_phy1>;
++		phy-connection-type = "qsgmii";
++	};
++
++	ethernet@e2000 {
++		phy-handle = <&qsgmii_phy2>;
++		phy-connection-type = "qsgmii";
++	};
++
++	ethernet@e4000 {
++		phy-handle = <&rgmii_phy1>;
++		phy-connection-type = "rgmii-txid";
++	};
++
++	ethernet@e6000 {
++		phy-handle = <&rgmii_phy2>;
++		phy-connection-type = "rgmii-txid";
++	};
++
++	ethernet@e8000 {
++		phy-handle = <&qsgmii_phy3>;
++		phy-connection-type = "qsgmii";
++	};
++
++	ethernet@ea000 {
++		phy-handle = <&qsgmii_phy4>;
++		phy-connection-type = "qsgmii";
++	};
++
++	ethernet@f0000 { /* 10GEC1 */
++		phy-handle = <&aqr105_phy>;
++		phy-connection-type = "xgmii";
++	};
++
++	mdio@fc000 {
++		rgmii_phy1: ethernet-phy@1 {
++			reg = <0x1>;
++		};
++
++		rgmii_phy2: ethernet-phy@2 {
++			reg = <0x2>;
++		};
++
++		qsgmii_phy1: ethernet-phy@4 {
++			reg = <0x4>;
++		};
++
++		qsgmii_phy2: ethernet-phy@5 {
++			reg = <0x5>;
++		};
++
++		qsgmii_phy3: ethernet-phy@6 {
++			reg = <0x6>;
++		};
++
++		qsgmii_phy4: ethernet-phy@7 {
++			reg = <0x7>;
++		};
++	};
++
++	mdio@fd000 {
++		aqr105_phy: ethernet-phy@1 {
++			compatible = "ethernet-phy-ieee802.3-c45";
++			interrupts = <0 132 4>;
++			reg = <0x1>;
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -1,55 +1,32 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+  *
+- * Copyright 2014-2015, Freescale Semiconductor
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+  *
+  * Mingkai Hu <Mingkai.hu@freescale.com>
+- *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- *  a) This library is free software; you can redistribute it and/or
+- *     modify it under the terms of the GNU General Public License as
+- *     published by the Free Software Foundation; either version 2 of the
+- *     License, or (at your option) any later version.
+- *
+- *     This library is distributed in the hope that it will be useful,
+- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *     GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- *  b) Permission is hereby granted, free of charge, to any person
+- *     obtaining a copy of this software and associated documentation
+- *     files (the "Software"), to deal in the Software without
+- *     restriction, including without limitation the rights to use,
+- *     copy, modify, merge, publish, distribute, sublicense, and/or
+- *     sell copies of the Software, and to permit persons to whom the
+- *     Software is furnished to do so, subject to the following
+- *     conditions:
+- *
+- *     The above copyright notice and this permission notice shall be
+- *     included in all copies or substantial portions of the Software.
+- *
+- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
++#include <dt-bindings/thermal/thermal.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
+ / {
+ 	compatible = "fsl,ls1043a";
+ 	interrupt-parent = <&gic>;
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
++	aliases {
++		fman0 = &fman0;
++		ethernet0 = &enet0;
++		ethernet1 = &enet1;
++		ethernet2 = &enet2;
++		ethernet3 = &enet3;
++		ethernet4 = &enet4;
++		ethernet5 = &enet5;
++		ethernet6 = &enet6;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -66,6 +43,8 @@
+ 			reg = <0x0>;
+ 			clocks = <&clockgen 1 0>;
+ 			next-level-cache = <&l2>;
++			#cooling-cells = <2>;
++			cpu-idle-states = <&CPU_PH20>;
+ 		};
+ 
+ 		cpu1: cpu@1 {
+@@ -74,6 +53,7 @@
+ 			reg = <0x1>;
+ 			clocks = <&clockgen 1 0>;
+ 			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
+ 		};
+ 
+ 		cpu2: cpu@2 {
+@@ -82,6 +62,7 @@
+ 			reg = <0x2>;
+ 			clocks = <&clockgen 1 0>;
+ 			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
+ 		};
+ 
+ 		cpu3: cpu@3 {
+@@ -90,6 +71,7 @@
+ 			reg = <0x3>;
+ 			clocks = <&clockgen 1 0>;
+ 			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
+ 		};
+ 
+ 		l2: l2-cache {
+@@ -97,12 +79,56 @@
+ 		};
+ 	};
+ 
++	idle-states {
++		/*
++		 * PSCI node is not added default, U-boot will add missing
++		 * parts if it determines to use PSCI.
++		 */
++		entry-method = "arm,psci";
++
++		CPU_PH20: cpu-ph20 {
++			compatible = "arm,idle-state";
++			idle-state-name = "PH20";
++			arm,psci-suspend-param = <0x0>;
++			entry-latency-us = <1000>;
++			exit-latency-us = <1000>;
++			min-residency-us = <3000>;
++		};
++	};
++
+ 	memory@80000000 {
+ 		device_type = "memory";
+ 		reg = <0x0 0x80000000 0 0x80000000>;
+ 		      /* DRAM space 1, size: 2GiB DRAM */
+ 	};
+ 
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		bman_fbpr: bman-fbpr {
++			compatible = "shared-dma-pool";
++			size = <0 0x1000000>;
++			alignment = <0 0x1000000>;
++			no-map;
++		};
++
++		qman_fqd: qman-fqd {
++			compatible = "shared-dma-pool";
++			size = <0 0x400000>;
++			alignment = <0 0x400000>;
++			no-map;
++		};
++
++		qman_pfdr: qman-pfdr {
++			compatible = "shared-dma-pool";
++			size = <0 0x2000000>;
++			alignment = <0 0x2000000>;
++			no-map;
++		};
++	};
++
+ 	sysclk: sysclk {
+ 		compatible = "fixed-clock";
+ 		#clock-cells = <0>;
+@@ -149,7 +175,7 @@
+ 		interrupts = <1 9 0xf08>;
+ 	};
+ 
+-	soc {
++	soc: soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+@@ -213,13 +239,14 @@
+ 
+ 		dcfg: dcfg@1ee0000 {
+ 			compatible = "fsl,ls1043a-dcfg", "syscon";
+-			reg = <0x0 0x1ee0000 0x0 0x10000>;
++			reg = <0x0 0x1ee0000 0x0 0x1000>;
+ 			big-endian;
+ 		};
+ 
+ 		ifc: ifc@1530000 {
+ 			compatible = "fsl,ifc", "simple-bus";
+ 			reg = <0x0 0x1530000 0x0 0x10000>;
++			big-endian;
+ 			interrupts = <0 43 0x4>;
+ 		};
+ 
+@@ -255,6 +282,103 @@
+ 			big-endian;
+ 		};
+ 
++		tmu: tmu@1f00000 {
++			compatible = "fsl,qoriq-tmu";
++			reg = <0x0 0x1f00000 0x0 0x10000>;
++			interrupts = <0 33 0x4>;
++			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++			fsl,tmu-calibration = <0x00000000 0x00000026
++					       0x00000001 0x0000002d
++					       0x00000002 0x00000032
++					       0x00000003 0x00000039
++					       0x00000004 0x0000003f
++					       0x00000005 0x00000046
++					       0x00000006 0x0000004d
++					       0x00000007 0x00000054
++					       0x00000008 0x0000005a
++					       0x00000009 0x00000061
++					       0x0000000a 0x0000006a
++					       0x0000000b 0x00000071
++
++					       0x00010000 0x00000025
++					       0x00010001 0x0000002c
++					       0x00010002 0x00000035
++					       0x00010003 0x0000003d
++					       0x00010004 0x00000045
++					       0x00010005 0x0000004e
++					       0x00010006 0x00000057
++					       0x00010007 0x00000061
++					       0x00010008 0x0000006b
++					       0x00010009 0x00000076
++
++					       0x00020000 0x00000029
++					       0x00020001 0x00000033
++					       0x00020002 0x0000003d
++					       0x00020003 0x00000049
++					       0x00020004 0x00000056
++					       0x00020005 0x00000061
++					       0x00020006 0x0000006d
++
++					       0x00030000 0x00000021
++					       0x00030001 0x0000002a
++					       0x00030002 0x0000003c
++					       0x00030003 0x0000004e>;
++			#thermal-sensor-cells = <1>;
++		};
++
++		thermal-zones {
++			cpu_thermal: cpu-thermal {
++				polling-delay-passive = <1000>;
++				polling-delay = <5000>;
++
++				thermal-sensors = <&tmu 3>;
++
++				trips {
++					cpu_alert: cpu-alert {
++						temperature = <85000>;
++						hysteresis = <2000>;
++						type = "passive";
++					};
++					cpu_crit: cpu-crit {
++						temperature = <95000>;
++						hysteresis = <2000>;
++						type = "critical";
++					};
++				};
++
++				cooling-maps {
++					map0 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu0 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++				};
++			};
++		};
++
++		qman: qman@1880000 {
++			compatible = "fsl,qman";
++			reg = <0x00 0x1880000 0x0 0x10000>;
++			interrupts = <0 45 0x4>;
++			memory-region = <&qman_fqd &qman_pfdr>;
++		};
++
++		bman: bman@1890000 {
++			compatible = "fsl,bman";
++			reg = <0x00 0x1890000 0x0 0x10000>;
++			interrupts = <0 45 0x4>;
++			memory-region = <&bman_fbpr>;
++		};
++
++		bportals: bman-portals@508000000 {
++			ranges = <0x0 0x5 0x08000000 0x8000000>;
++		};
++
++		qportals: qman-portals@500000000 {
++			ranges = <0x0 0x5 0x00000000 0x8000000>;
++		};
++
+ 		dspi0: dspi@2100000 {
+ 			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ 			#address-cells = <1>;
+@@ -282,7 +406,7 @@
+ 		};
+ 
+ 		i2c0: i2c@2180000 {
+-			compatible = "fsl,vf610-i2c";
++			compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 			reg = <0x0 0x2180000 0x0 0x10000>;
+@@ -292,6 +416,7 @@
+ 			dmas = <&edma0 1 39>,
+ 			       <&edma0 1 38>;
+ 			dma-names = "tx", "rx";
++			fsl-scl-gpio = <&gpio4 12 0>;
+ 			status = "disabled";
+ 		};
+ 
+@@ -396,6 +521,72 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 
++		uqe: uqe@2400000 {
++			#address-cells = <1>;
++			#size-cells = <1>;
++			device_type = "qe";
++			compatible = "fsl,qe", "simple-bus";
++			ranges = <0x0 0x0 0x2400000 0x40000>;
++			reg = <0x0 0x2400000 0x0 0x480>;
++			brg-frequency = <100000000>;
++			bus-frequency = <200000000>;
++
++			fsl,qe-num-riscs = <1>;
++			fsl,qe-num-snums = <28>;
++
++			qeic: qeic@80 {
++				compatible = "fsl,qe-ic";
++				reg = <0x80 0x80>;
++				#address-cells = <0>;
++				interrupt-controller;
++				#interrupt-cells = <1>;
++				interrupts = <0 77 0x04 0 77 0x04>;
++			};
++
++			si1: si@700 {
++				#address-cells = <1>;
++				#size-cells = <0>;
++				compatible = "fsl,ls1043-qe-si",
++						"fsl,t1040-qe-si";
++				reg = <0x700 0x80>;
++			};
++
++			siram1: siram@1000 {
++				#address-cells = <1>;
++				#size-cells = <1>;
++				compatible = "fsl,ls1043-qe-siram",
++						"fsl,t1040-qe-siram";
++				reg = <0x1000 0x800>;
++			};
++
++			ucc@2000 {
++				cell-index = <1>;
++				reg = <0x2000 0x200>;
++				interrupts = <32>;
++				interrupt-parent = <&qeic>;
++			};
++
++			ucc@2200 {
++				cell-index = <3>;
++				reg = <0x2200 0x200>;
++				interrupts = <34>;
++				interrupt-parent = <&qeic>;
++			};
++
++			muram@10000 {
++				#address-cells = <1>;
++				#size-cells = <1>;
++				compatible = "fsl,qe-muram", "fsl,cpm-muram";
++				ranges = <0x0 0x10000 0x6000>;
++
++				data-only@0 {
++					compatible = "fsl,qe-muram-data",
++					"fsl,cpm-muram-data";
++					reg = <0x0 0x6000>;
++				};
++			};
++		};
++
+ 		lpuart0: serial@2950000 {
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x2950000 0x0 0x1000>;
+@@ -450,6 +641,16 @@
+ 			status = "disabled";
+ 		};
+ 
++		ftm0: ftm0@29d0000 {
++			compatible = "fsl,ls1043a-ftm";
++			reg = <0x0 0x29d0000 0x0 0x10000>,
++			      <0x0 0x1ee2140 0x0 0x4>;
++			reg-names = "ftm", "FlexTimer1";
++			interrupts = <0 86 0x4>;
++			big-endian;
++			status = "okay";
++		};
++
+ 		wdog0: wdog@2ad0000 {
+ 			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+ 			reg = <0x0 0x2ad0000 0x0 0x10000>;
+@@ -482,6 +683,10 @@
+ 			dr_mode = "host";
+ 			snps,quirk-frame-length-adjustment = <0x20>;
+ 			snps,dis_rxdet_inp3_quirk;
++			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++			snps,dma-snooping;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
+ 		};
+ 
+ 		usb1: usb3@3000000 {
+@@ -491,6 +696,11 @@
+ 			dr_mode = "host";
+ 			snps,quirk-frame-length-adjustment = <0x20>;
+ 			snps,dis_rxdet_inp3_quirk;
++			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++			snps,dma-snooping;
++			configure-gfladj;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
+ 		};
+ 
+ 		usb2: usb3@3100000 {
+@@ -500,32 +710,54 @@
+ 			dr_mode = "host";
+ 			snps,quirk-frame-length-adjustment = <0x20>;
+ 			snps,dis_rxdet_inp3_quirk;
++			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++			snps,dma-snooping;
++			configure-gfladj;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
+ 		};
+ 
+ 		sata: sata@3200000 {
+ 			compatible = "fsl,ls1043a-ahci";
+-			reg = <0x0 0x3200000 0x0 0x10000>;
++			reg = <0x0 0x3200000 0x0 0x10000>,
++				<0x0 0x20140520 0x0 0x4>;
++			reg-names = "ahci", "sata-ecc";
+ 			interrupts = <0 69 0x4>;
+ 			clocks = <&clockgen 4 0>;
+ 			dma-coherent;
+ 		};
+ 
++		qdma: qdma@8380000 {
++			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
++			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
++			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
++			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
++			interrupts = <0 152 0x4>,
++				     <0 39 0x4>;
++			interrupt-names = "qdma-error", "qdma-queue";
++			channels = <8>;
++			queues = <2>;
++			status-sizes = <64>;
++			queue-sizes = <64 64>;
++			big-endian;
++		};
++
+ 		msi1: msi-controller1@1571000 {
+-			compatible = "fsl,1s1043a-msi";
++			compatible = "fsl,ls1043a-msi";
+ 			reg = <0x0 0x1571000 0x0 0x8>;
+ 			msi-controller;
+ 			interrupts = <0 116 0x4>;
+ 		};
+ 
+ 		msi2: msi-controller2@1572000 {
+-			compatible = "fsl,1s1043a-msi";
++			compatible = "fsl,ls1043a-msi";
+ 			reg = <0x0 0x1572000 0x0 0x8>;
+ 			msi-controller;
+ 			interrupts = <0 126 0x4>;
+ 		};
+ 
+ 		msi3: msi-controller3@1573000 {
+-			compatible = "fsl,1s1043a-msi";
++			compatible = "fsl,ls1043a-msi";
+ 			reg = <0x0 0x1573000 0x0 0x8>;
+ 			msi-controller;
+ 			interrupts = <0 160 0x4>;
+@@ -536,9 +768,9 @@
+ 			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+ 			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names = "regs", "config";
+-			interrupts = <0 118 0x4>, /* controller interrupt */
+-				     <0 117 0x4>; /* PME interrupt */
+-			interrupt-names = "intr", "pme";
++			interrupts = <0 117 0x4>, /* PME interrupt */
++				     <0 118 0x4>; /* aer interrupt */
++			interrupt-names = "pme", "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
+@@ -547,7 +779,7 @@
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&msi1>;
++			msi-parent = <&msi1>, <&msi2>, <&msi3>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+@@ -561,9 +793,9 @@
+ 			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+ 			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names = "regs", "config";
+-			interrupts = <0 128 0x4>,
+-				     <0 127 0x4>;
+-			interrupt-names = "intr", "pme";
++			interrupts = <0 127 0x4>,
++				     <0 128 0x4>;
++			interrupt-names = "pme", "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
+@@ -572,7 +804,7 @@
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&msi2>;
++			msi-parent = <&msi1>, <&msi2>, <&msi3>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
+@@ -586,9 +818,9 @@
+ 			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+ 			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ 			reg-names = "regs", "config";
+-			interrupts = <0 162 0x4>,
+-				     <0 161 0x4>;
+-			interrupt-names = "intr", "pme";
++			interrupts = <0 161 0x4>,
++				     <0 162 0x4>;
++			interrupt-names = "pme", "aer";
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
+@@ -597,7 +829,7 @@
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
+ 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&msi3>;
++			msi-parent = <&msi1>, <&msi2>, <&msi3>;
+ 			#interrupt-cells = <1>;
+ 			interrupt-map-mask = <0 0 0 7>;
+ 			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+@@ -607,4 +839,13 @@
+ 		};
+ 	};
+ 
++	firmware {
++		optee {
++			compatible = "linaro,optee-tz";
++			method = "smc";
++		};
++	};
+ };
++
++#include "qoriq-qman-portals.dtsi"
++#include "qoriq-bman-portals.dtsi"
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
+@@ -0,0 +1,48 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 device tree nodes for ls1046
++ *
++ * Copyright 2015-2016 Freescale Semiconductor Inc.
++ *
++ */
++
++&soc {
++
++/* include used FMan blocks */
++#include "qoriq-fman3-0.dtsi"
++#include "qoriq-fman3-0-1g-0.dtsi"
++#include "qoriq-fman3-0-1g-1.dtsi"
++#include "qoriq-fman3-0-1g-2.dtsi"
++#include "qoriq-fman3-0-1g-3.dtsi"
++#include "qoriq-fman3-0-1g-4.dtsi"
++#include "qoriq-fman3-0-1g-5.dtsi"
++#include "qoriq-fman3-0-10g-0.dtsi"
++#include "qoriq-fman3-0-10g-1.dtsi"
++};
++
++&fman0 {
++	/* these aliases provide the FMan ports mapping */
++	enet0: ethernet@e0000 {
++	};
++
++	enet1: ethernet@e2000 {
++	};
++
++	enet2: ethernet@e4000 {
++	};
++
++	enet3: ethernet@e6000 {
++	};
++
++	enet4: ethernet@e8000 {
++	};
++
++	enet5: ethernet@ea000 {
++	};
++
++	enet6: ethernet@f0000 {
++	};
++
++	enet7: ethernet@f2000 {
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+@@ -0,0 +1,112 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1046a-qds.dts"
++#include "qoriq-qman-portals-sdk.dtsi"
++#include "qoriq-bman-portals-sdk.dtsi"
++
++&bman_fbpr {
++	compatible = "fsl,bman-fbpr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++	compatible = "fsl,qman-fqd";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++	compatible = "fsl,qman-pfdr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fsldpaa {
++	ethernet@9 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet7>;
++		dma-coherent;
++	};
++};
++
++&fman0 {
++	compatible = "fsl,fman", "simple-bus";
++};
++
++&dspi {
++	bus-num = <0>;
++	status = "okay";
++
++	flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "n25q128a11", "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++
++	flash@1 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "sst25wf040b", "jedec,spi-nor";
++		spi-cpol;
++		spi-cpha;
++		reg = <1>;
++		spi-max-frequency = <10000000>;
++	};
++
++	flash@2 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "en25s64", "jedec,spi-nor";
++		spi-cpol;
++		spi-cpha;
++		reg = <2>;
++		spi-max-frequency = <10000000>;
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+@@ -0,0 +1,326 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * Shaohui Xie <Shaohui.Xie@nxp.com>
++ */
++
++/dts-v1/;
++
++#include "fsl-ls1046a.dtsi"
++
++/ {
++	model = "LS1046A QDS Board";
++	compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
++
++	aliases {
++		gpio0 = &gpio0;
++		gpio1 = &gpio1;
++		gpio2 = &gpio2;
++		gpio3 = &gpio3;
++		serial0 = &duart0;
++		serial1 = &duart1;
++		serial2 = &duart2;
++		serial3 = &duart3;
++
++		emi1_slot1 = &ls1046mdio_s1;
++		emi1_slot2 = &ls1046mdio_s2;
++		emi1_slot4 = &ls1046mdio_s4;
++
++		sgmii_s1_p1 = &sgmii_phy_s1_p1;
++		sgmii_s1_p2 = &sgmii_phy_s1_p2;
++		sgmii_s1_p3 = &sgmii_phy_s1_p3;
++		sgmii_s1_p4 = &sgmii_phy_s1_p4;
++		sgmii_s4_p1 = &sgmii_phy_s4_p1;
++		qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
++		qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
++		qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
++		qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++};
++
++&dspi {
++	bus-num = <0>;
++	status = "okay";
++
++	flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "n25q128a11", "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++	};
++
++	flash@1 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "sst25wf040b", "jedec,spi-nor";
++		spi-cpol;
++		spi-cpha;
++		reg = <1>;
++		spi-max-frequency = <10000000>;
++	};
++
++	flash@2 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "en25s64", "jedec,spi-nor";
++		spi-cpol;
++		spi-cpha;
++		reg = <2>;
++		spi-max-frequency = <10000000>;
++	};
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&duart1 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	pca9547@77 {
++		compatible = "nxp,pca9547";
++		reg = <0x77>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x2>;
++
++			ina220@40 {
++				compatible = "ti,ina220";
++				reg = <0x40>;
++				shunt-resistor = <1000>;
++			};
++
++			ina220@41 {
++				compatible = "ti,ina220";
++				reg = <0x41>;
++				shunt-resistor = <1000>;
++			};
++		};
++
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			rtc@51 {
++				compatible = "nxp,pcf2129";
++				reg = <0x51>;
++				/* IRQ10_B */
++				interrupts = <0 150 0x4>;
++			};
++
++			eeprom@56 {
++				compatible = "atmel,24c512";
++				reg = <0x56>;
++			};
++
++			eeprom@57 {
++				compatible = "atmel,24c512";
++				reg = <0x57>;
++			};
++
++			temp-sensor@4c {
++				compatible = "adi,adt7461a";
++				reg = <0x4c>;
++			};
++		};
++	};
++};
++
++&ifc {
++	#address-cells = <2>;
++	#size-cells = <1>;
++	/* NOR, NAND Flashes and FPGA on board */
++	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
++		  0x1 0x0 0x0 0x7e800000 0x00010000
++		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
++	status = "okay";
++
++	nor@0,0 {
++		compatible = "cfi-flash";
++		reg = <0x0 0x0 0x8000000>;
++		bank-width = <2>;
++		device-width = <1>;
++	};
++
++	nand@1,0 {
++		compatible = "fsl,ifc-nand";
++		reg = <0x1 0x0 0x10000>;
++	};
++
++	fpga: board-control@2,0 {
++		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
++		reg = <0x2 0x0 0x0000100>;
++		ranges = <0 2 0 0x100>;
++	};
++};
++
++&lpuart0 {
++	status = "okay";
++};
++
++&qspi {
++	num-cs = <2>;
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: s25fl128s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++};
++
++#include "fsl-ls1046-post.dtsi"
++
++&fman0 {
++	ethernet@e0000 {
++		phy-handle = <&qsgmii_phy_s2_p1>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@e2000 {
++		phy-handle = <&sgmii_phy_s4_p1>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@e4000 {
++		phy-handle = <&rgmii_phy1>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e6000 {
++		phy-handle = <&rgmii_phy2>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e8000 {
++		phy-handle = <&sgmii_phy_s1_p3>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@ea000 {
++		phy-handle = <&sgmii_phy_s1_p4>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@f0000 { /* DTSEC9/10GEC1 */
++		phy-handle = <&sgmii_phy_s1_p1>;
++		phy-connection-type = "xgmii";
++	};
++
++	ethernet@f2000 { /* DTSEC10/10GEC2 */
++		phy-handle = <&sgmii_phy_s1_p2>;
++		phy-connection-type = "xgmii";
++	};
++};
++
++&fpga {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	mdio-mux-emi1 {
++		compatible = "mdio-mux-mmioreg", "mdio-mux";
++		mdio-parent-bus = <&mdio0>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		reg = <0x54 1>;    /* BRDCFG4 */
++		mux-mask = <0xe0>; /* EMI1 */
++
++		/* On-board RGMII1 PHY */
++		ls1046mdio0: mdio@0 {
++			reg = <0>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
++				reg = <0x1>;
++			};
++		};
++
++		/* On-board RGMII2 PHY */
++		ls1046mdio1: mdio@1 {
++			reg = <0x20>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
++				reg = <0x2>;
++			};
++		};
++
++		/* Slot 1 */
++		ls1046mdio_s1: mdio@2 {
++			reg = <0x40>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			sgmii_phy_s1_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++
++			sgmii_phy_s1_p2: ethernet-phy@1d {
++				reg = <0x1d>;
++			};
++
++			sgmii_phy_s1_p3: ethernet-phy@1e {
++				reg = <0x1e>;
++			};
++
++			sgmii_phy_s1_p4: ethernet-phy@1f {
++				reg = <0x1f>;
++			};
++		};
++
++		/* Slot 2 */
++		ls1046mdio_s2: mdio@3 {
++			reg = <0x60>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			qsgmii_phy_s2_p1: ethernet-phy@8 {
++				reg = <0x8>;
++			};
++			qsgmii_phy_s2_p2: ethernet-phy@9 {
++				reg = <0x9>;
++			};
++			qsgmii_phy_s2_p3: ethernet-phy@a {
++				reg = <0xa>;
++			};
++			qsgmii_phy_s2_p4: ethernet-phy@b {
++				reg = <0xb>;
++			};
++		};
++
++		/* Slot 4 */
++		ls1046mdio_s4: mdio@5 {
++			reg = <0x80>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++			status = "disabled";
++
++			sgmii_phy_s4_p1: ethernet-phy@1c {
++				reg = <0x1c>;
++			};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+@@ -0,0 +1,85 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1046a-rdb.dts"
++#include "qoriq-qman-portals-sdk.dtsi"
++#include "qoriq-bman-portals-sdk.dtsi"
++
++&bman_fbpr {
++	compatible = "fsl,bman-fbpr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++	compatible = "fsl,qman-fqd";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++	compatible = "fsl,qman-pfdr";
++	alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fsldpaa {
++	ethernet@0 {
++		status = "disabled";
++	};
++	ethernet@1 {
++		status = "disabled";
++	};
++	ethernet@9 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet7>;
++		dma-coherent;
++	};
++};
++
++&fman0 {
++	compatible = "fsl,fman", "simple-bus";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+@@ -0,0 +1,110 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include "fsl-ls1046a-rdb-sdk.dts"
++
++&soc {
++	bp7: buffer-pool@7 {
++		compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++		fsl,bpid = <7>;
++		fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
++		fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
++	};
++
++	bp8: buffer-pool@8 {
++		compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++		fsl,bpid = <8>;
++		fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
++		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++	};
++
++	bp9: buffer-pool@9 {
++		compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++		fsl,bpid = <9>;
++		fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
++		fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++	};
++
++	fsl,dpaa {
++		compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
++
++		ethernet@2 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
++			fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
++		};
++
++		ethernet@3 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
++			fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
++		};
++
++		ethernet@4 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
++			fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
++		};
++
++		ethernet@5 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
++			fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
++		};
++
++		ethernet@8 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
++			fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
++		};
++
++		ethernet@9 {
++			compatible = "fsl,dpa-ethernet-init";
++			fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++			fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
++			fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
++		};
++
++		dpa-fman0-oh@2 {
++			compatible = "fsl,dpa-oh";
++			/* Define frame queues for the OH port*/
++			/* <OH Rx error, OH Rx default> */
++			fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
++			fsl,fman-oh-port = <&fman0_oh2>;
++		};
++	};
++};
++/ {
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		usdpaa_mem: usdpaa_mem {
++			compatible = "fsl,usdpaa-mem";
++			alloc-ranges = <0 0 0x10000 0>;
++			size = <0 0x10000000>;
++			alignment = <0 0x10000000>;
++		};
++	};
++};
++
++&fman0 {
++	fman0_oh2: port@83000 {
++		cell-index = <1>;
++		compatible = "fsl,fman-port-oh";
++		reg = <0x83000 0x1000>;
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+@@ -0,0 +1,181 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <mingkai.hu@nxp.com>
++ */
++
++/dts-v1/;
++
++#include "fsl-ls1046a.dtsi"
++
++/ {
++	model = "LS1046A RDB Board";
++	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
++
++	aliases {
++		serial0 = &duart0;
++		serial1 = &duart1;
++		serial2 = &duart2;
++		serial3 = &duart3;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++};
++
++&esdhc {
++	mmc-hs200-1_8v;
++	sd-uhs-sdr104;
++	sd-uhs-sdr50;
++	sd-uhs-sdr25;
++	sd-uhs-sdr12;
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&duart1 {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	ina220@40 {
++		compatible = "ti,ina220";
++		reg = <0x40>;
++		shunt-resistor = <1000>;
++	};
++
++	temp-sensor@4c {
++		compatible = "adi,adt7461";
++		reg = <0x4c>;
++	};
++
++	eeprom@56 {
++		compatible = "atmel,24c512";
++		reg = <0x52>;
++	};
++
++	eeprom@57 {
++		compatible = "atmel,24c512";
++		reg = <0x53>;
++	};
++};
++
++&i2c3 {
++	status = "okay";
++
++	rtc@51 {
++		compatible = "nxp,pcf2129";
++		reg = <0x51>;
++	};
++};
++
++&ifc {
++	#address-cells = <2>;
++	#size-cells = <1>;
++	/* NAND Flashe and CPLD on board */
++	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
++		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
++	status = "okay";
++
++	nand@0,0 {
++		compatible = "fsl,ifc-nand";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		reg = <0x0 0x0 0x10000>;
++	};
++
++	cpld: board-control@2,0 {
++		compatible = "fsl,ls1046ardb-cpld";
++		reg = <0x2 0x0 0x0000100>;
++	};
++};
++
++&qspi {
++	num-cs = <2>;
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: s25fs512s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++
++	qflash1: s25fs512s@1 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		reg = <1>;
++	};
++};
++
++#include "fsl-ls1046-post.dtsi"
++
++&fman0 {
++	ethernet@e4000 {
++		phy-handle = <&rgmii_phy1>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e6000 {
++		phy-handle = <&rgmii_phy2>;
++		phy-connection-type = "rgmii";
++	};
++
++	ethernet@e8000 {
++		phy-handle = <&sgmii_phy1>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@ea000 {
++		phy-handle = <&sgmii_phy2>;
++		phy-connection-type = "sgmii";
++	};
++
++	ethernet@f0000 { /* 10GEC1 */
++		phy-handle = <&aqr106_phy>;
++		phy-connection-type = "xgmii";
++	};
++
++	ethernet@f2000 { /* 10GEC2 */
++		fixed-link = <0 1 1000 0 0>;
++		phy-connection-type = "xgmii";
++	};
++
++	mdio@fc000 {
++		rgmii_phy1: ethernet-phy@1 {
++			reg = <0x1>;
++		};
++
++		rgmii_phy2: ethernet-phy@2 {
++			reg = <0x2>;
++		};
++
++		sgmii_phy1: ethernet-phy@3 {
++			reg = <0x3>;
++		};
++
++		sgmii_phy2: ethernet-phy@4 {
++			reg = <0x4>;
++		};
++	};
++
++	mdio@fd000 {
++		aqr106_phy: ethernet-phy@0 {
++			compatible = "ethernet-phy-ieee802.3-c45";
++			interrupts = <0 131 4>;
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+@@ -0,0 +1,771 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <mingkai.hu@nxp.com>
++ */
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++	compatible = "fsl,ls1046a";
++	interrupt-parent = <&gic>;
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	aliases {
++		crypto = &crypto;
++		fman0 = &fman0;
++		ethernet0 = &enet0;
++		ethernet1 = &enet1;
++		ethernet2 = &enet2;
++		ethernet3 = &enet3;
++		ethernet4 = &enet4;
++		ethernet5 = &enet5;
++		ethernet6 = &enet6;
++		ethernet7 = &enet7;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a72";
++			reg = <0x0>;
++			clocks = <&clockgen 1 0>;
++			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
++			#cooling-cells = <2>;
++		};
++
++		cpu1: cpu@1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a72";
++			reg = <0x1>;
++			clocks = <&clockgen 1 0>;
++			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu2: cpu@2 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a72";
++			reg = <0x2>;
++			clocks = <&clockgen 1 0>;
++			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu3: cpu@3 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a72";
++			reg = <0x3>;
++			clocks = <&clockgen 1 0>;
++			next-level-cache = <&l2>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		l2: l2-cache {
++			compatible = "cache";
++		};
++	};
++
++	idle-states {
++		/*
++		 * PSCI node is not added default, U-boot will add missing
++		 * parts if it determines to use PSCI.
++		 */
++		entry-method = "arm,psci";
++
++		CPU_PH20: cpu-ph20 {
++			compatible = "arm,idle-state";
++			idle-state-name = "PH20";
++			arm,psci-suspend-param = <0x0>;
++			entry-latency-us = <1000>;
++			exit-latency-us = <1000>;
++			min-residency-us = <3000>;
++		};
++	};
++
++	memory@80000000 {
++		device_type = "memory";
++	};
++
++	sysclk: sysclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <100000000>;
++		clock-output-names = "sysclk";
++	};
++
++	reboot {
++		compatible ="syscon-reboot";
++		regmap = <&dcfg>;
++		offset = <0xb0>;
++		mask = <0x02>;
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
++					  IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
++					  IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
++					  IRQ_TYPE_LEVEL_LOW)>,
++			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
++					  IRQ_TYPE_LEVEL_LOW)>;
++	};
++
++	pmu {
++		compatible = "arm,cortex-a72-pmu";
++		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
++			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-affinity = <&cpu0>,
++				     <&cpu1>,
++				     <&cpu2>,
++				     <&cpu3>;
++	};
++
++	gic: interrupt-controller@1400000 {
++		compatible = "arm,gic-400";
++		#interrupt-cells = <3>;
++		interrupt-controller;
++		reg = <0x0 0x1410000 0 0x10000>, /* GICD */
++		      <0x0 0x1420000 0 0x20000>, /* GICC */
++		      <0x0 0x1440000 0 0x20000>, /* GICH */
++		      <0x0 0x1460000 0 0x20000>; /* GICV */
++		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
++					 IRQ_TYPE_LEVEL_LOW)>;
++	};
++
++	soc: soc {
++		compatible = "simple-bus";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		ddr: memory-controller@1080000 {
++			compatible = "fsl,qoriq-memory-controller";
++			reg = <0x0 0x1080000 0x0 0x1000>;
++			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++			big-endian;
++		};
++
++		ifc: ifc@1530000 {
++			compatible = "fsl,ifc", "simple-bus";
++			reg = <0x0 0x1530000 0x0 0x10000>;
++			big-endian;
++			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		qspi: quadspi@1550000 {
++			compatible = "fsl,ls1021a-qspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x1550000 0x0 0x10000>,
++				<0x0 0x40000000 0x0 0x10000000>;
++			reg-names = "QuadSPI", "QuadSPI-memory";
++			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
++			clock-names = "qspi_en", "qspi";
++			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++			big-endian;
++			fsl,qspi-has-second-chip;
++			status = "disabled";
++		};
++
++		esdhc: esdhc@1560000 {
++			compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
++			reg = <0x0 0x1560000 0x0 0x10000>;
++			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 2 1>;
++			voltage-ranges = <1800 1800 3300 3300>;
++			sdhci,auto-cmd12;
++			big-endian;
++			bus-width = <4>;
++		};
++
++		scfg: scfg@1570000 {
++			compatible = "fsl,ls1046a-scfg", "syscon";
++			reg = <0x0 0x1570000 0x0 0x10000>;
++			big-endian;
++		};
++
++		crypto: crypto@1700000 {
++			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
++				     "fsl,sec-v4.0";
++			fsl,sec-era = <8>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0x0 0x00 0x1700000 0x100000>;
++			reg = <0x00 0x1700000 0x0 0x100000>;
++			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++
++			sec_jr0: jr@10000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x10000 0x10000>;
++				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr1: jr@20000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x20000 0x10000>;
++				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr2: jr@30000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x30000 0x10000>;
++				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr3: jr@40000 {
++				compatible = "fsl,sec-v5.4-job-ring",
++					     "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x40000 0x10000>;
++				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++			};
++		};
++
++		qman: qman@1880000 {
++			compatible = "fsl,qman";
++			reg = <0x00 0x1880000 0x0 0x10000>;
++			interrupts = <0 45 0x4>;
++			memory-region = <&qman_fqd &qman_pfdr>;
++
++		};
++
++		bman: bman@1890000 {
++			compatible = "fsl,bman";
++			reg = <0x00 0x1890000 0x0 0x10000>;
++			interrupts = <0 45 0x4>;
++			memory-region = <&bman_fbpr>;
++
++		};
++
++		qportals: qman-portals@500000000 {
++			ranges = <0x0 0x5 0x00000000 0x8000000>;
++		};
++
++		bportals: bman-portals@508000000 {
++			ranges = <0x0 0x5 0x08000000 0x8000000>;
++		};
++
++		dcfg: dcfg@1ee0000 {
++			compatible = "fsl,ls1046a-dcfg", "syscon";
++			reg = <0x0 0x1ee0000 0x0 0x1000>;
++			big-endian;
++		};
++
++		clockgen: clocking@1ee1000 {
++			compatible = "fsl,ls1046a-clockgen";
++			reg = <0x0 0x1ee1000 0x0 0x1000>;
++			#clock-cells = <2>;
++			clocks = <&sysclk>;
++		};
++
++		tmu: tmu@1f00000 {
++			compatible = "fsl,qoriq-tmu";
++			reg = <0x0 0x1f00000 0x0 0x10000>;
++			interrupts = <0 33 0x4>;
++			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++			fsl,tmu-calibration =
++				/* Calibration data group 1 */
++				<0x00000000 0x00000026
++				0x00000001 0x0000002d
++				0x00000002 0x00000032
++				0x00000003 0x00000039
++				0x00000004 0x0000003f
++				0x00000005 0x00000046
++				0x00000006 0x0000004d
++				0x00000007 0x00000054
++				0x00000008 0x0000005a
++				0x00000009 0x00000061
++				0x0000000a 0x0000006a
++				0x0000000b 0x00000071
++				/* Calibration data group 2 */
++				0x00010000 0x00000025
++				0x00010001 0x0000002c
++				0x00010002 0x00000035
++				0x00010003 0x0000003d
++				0x00010004 0x00000045
++				0x00010005 0x0000004e
++				0x00010006 0x00000057
++				0x00010007 0x00000061
++				0x00010008 0x0000006b
++				0x00010009 0x00000076
++				/* Calibration data group 3 */
++				0x00020000 0x00000029
++				0x00020001 0x00000033
++				0x00020002 0x0000003d
++				0x00020003 0x00000049
++				0x00020004 0x00000056
++				0x00020005 0x00000061
++				0x00020006 0x0000006d
++				/* Calibration data group 4 */
++				0x00030000 0x00000021
++				0x00030001 0x0000002a
++				0x00030002 0x0000003c
++				0x00030003 0x0000004e>;
++			big-endian;
++			#thermal-sensor-cells = <1>;
++		};
++
++		thermal-zones {
++			cpu_thermal: cpu-thermal {
++				polling-delay-passive = <1000>;
++				polling-delay = <5000>;
++				thermal-sensors = <&tmu 3>;
++
++				trips {
++					cpu_alert: cpu-alert {
++						temperature = <85000>;
++						hysteresis = <2000>;
++						type = "passive";
++					};
++
++					cpu_crit: cpu-crit {
++						temperature = <95000>;
++						hysteresis = <2000>;
++						type = "critical";
++					};
++				};
++
++				cooling-maps {
++					map0 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu0 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++				};
++			};
++		};
++
++		dspi: dspi@2100000 {
++			compatible = "fsl,ls1021a-v1.0-dspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2100000 0x0 0x10000>;
++			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
++			clock-names = "dspi";
++			clocks = <&clockgen 4 1>;
++			spi-num-chipselects = <5>;
++			big-endian;
++			status = "disabled";
++		};
++
++		i2c0: i2c@2180000 {
++			compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2180000 0x0 0x10000>;
++			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			dmas = <&edma0 1 39>,
++			       <&edma0 1 38>;
++			dma-names = "tx", "rx";
++			fsl-scl-gpio = <&gpio3 12 0>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@2190000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2190000 0x0 0x10000>;
++			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@21a0000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x21a0000 0x0 0x10000>;
++			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@21b0000 {
++			compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x21b0000 0x0 0x10000>;
++			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			fsl-scl-gpio = <&gpio3 12 0>;
++			status = "disabled";
++		};
++
++		duart0: serial@21c0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x00 0x21c0500 0x0 0x100>;
++			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		duart1: serial@21c0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x00 0x21c0600 0x0 0x100>;
++			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		duart2: serial@21d0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21d0500 0x0 0x100>;
++			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		duart3: serial@21d0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21d0600 0x0 0x100>;
++			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++		};
++
++		gpio0: gpio@2300000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2300000 0x0 0x10000>;
++			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio1: gpio@2310000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2310000 0x0 0x10000>;
++			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio2: gpio@2320000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2320000 0x0 0x10000>;
++			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio3: gpio@2330000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2330000 0x0 0x10000>;
++			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		lpuart0: serial@2950000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2950000 0x0 0x1000>;
++			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 0>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart1: serial@2960000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2960000 0x0 0x1000>;
++			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart2: serial@2970000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2970000 0x0 0x1000>;
++			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart3: serial@2980000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2980000 0x0 0x1000>;
++			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart4: serial@2990000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x2990000 0x0 0x1000>;
++			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		lpuart5: serial@29a0000 {
++			compatible = "fsl,ls1021a-lpuart";
++			reg = <0x0 0x29a0000 0x0 0x1000>;
++			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			clock-names = "ipg";
++			status = "disabled";
++		};
++
++		ftm0: ftm0@29d0000 {
++			compatible = "fsl,ls1046a-ftm";
++			reg = <0x0 0x29d0000 0x0 0x10000>,
++			      <0x0 0x1ee2140 0x0 0x4>;
++			reg-names = "ftm", "FlexTimer1";
++			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++			big-endian;
++		};
++
++		wdog0: watchdog@2ad0000 {
++			compatible = "fsl,imx21-wdt";
++			reg = <0x0 0x2ad0000 0x0 0x10000>;
++			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			big-endian;
++		};
++
++		edma0: edma@2c00000 {
++			#dma-cells = <2>;
++			compatible = "fsl,vf610-edma";
++			reg = <0x0 0x2c00000 0x0 0x10000>,
++			      <0x0 0x2c10000 0x0 0x10000>,
++			      <0x0 0x2c20000 0x0 0x10000>;
++			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "edma-tx", "edma-err";
++			dma-channels = <32>;
++			big-endian;
++			clock-names = "dmamux0", "dmamux1";
++			clocks = <&clockgen 4 1>,
++				 <&clockgen 4 1>;
++		};
++
++		usb0: usb@2f00000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x2f00000 0x0 0x10000>;
++			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
++			dr_mode = "host";
++			snps,quirk-frame-length-adjustment = <0x20>;
++			snps,dis_rxdet_inp3_quirk;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
++		};
++
++		usb1: usb@3000000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3000000 0x0 0x10000>;
++			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++			dr_mode = "host";
++			snps,quirk-frame-length-adjustment = <0x20>;
++			snps,dis_rxdet_inp3_quirk;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
++		};
++
++		usb2: usb@3100000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3100000 0x0 0x10000>;
++			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			dr_mode = "host";
++			snps,quirk-frame-length-adjustment = <0x20>;
++			snps,dis_rxdet_inp3_quirk;
++			usb3-lpm-capable;
++			snps,dis-u1u2-when-u3-quirk;
++		};
++
++		sata: sata@3200000 {
++			compatible = "fsl,ls1046a-ahci";
++			reg = <0x0 0x3200000 0x0 0x10000>,
++				<0x0 0x20140520 0x0 0x4>;
++			reg-names = "ahci", "sata-ecc";
++			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 1>;
++			dma-coherent;
++		};
++
++		qdma: qdma@8380000 {
++			compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
++			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
++			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
++			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
++			interrupts = <0 153 0x4>,
++				     <0 39 0x4>;
++			interrupt-names = "qdma-error", "qdma-queue";
++			channels = <8>;
++			queues = <2>;
++			status-sizes = <64>;
++			queue-sizes = <64 64>;
++			big-endian;
++		};
++
++		msi1: msi-controller@1580000 {
++			compatible = "fsl,ls1046a-msi";
++			msi-controller;
++			reg = <0x0 0x1580000 0x0 0x10000>;
++			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		msi2: msi-controller@1590000 {
++			compatible = "fsl,ls1046a-msi";
++			msi-controller;
++			reg = <0x0 0x1590000 0x0 0x10000>;
++			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		msi3: msi-controller@15a0000 {
++			compatible = "fsl,ls1046a-msi";
++			msi-controller;
++			reg = <0x0 0x15a0000 0x0 0x10000>;
++			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pcie@3400000 {
++			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
++			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
++				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++			interrupt-names = "pme", "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi1>, <&msi2>, <&msi3>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pcie@3500000 {
++			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
++			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "pme", "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <2>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi1>, <&msi2>, <&msi3>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pcie@3600000 {
++			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
++			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "pme", "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <2>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&msi1>, <&msi2>, <&msi3>;
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++	};
++
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		bman_fbpr: bman-fbpr {
++			compatible = "shared-dma-pool";
++			size = <0 0x1000000>;
++			alignment = <0 0x1000000>;
++			no-map;
++		};
++		qman_fqd: qman-fqd {
++			compatible = "shared-dma-pool";
++			size = <0 0x800000>;
++			alignment = <0 0x800000>;
++			no-map;
++		};
++		qman_pfdr: qman-pfdr {
++			compatible = "shared-dma-pool";
++			size = <0 0x2000000>;
++			alignment = <0 0x2000000>;
++			no-map;
++		};
++	};
++
++	firmware {
++		optee {
++			compatible = "linaro,optee-tz";
++			method = "smc";
++		};
++	};
++};
++
++#include "qoriq-qman-portals.dtsi"
++#include "qoriq-bman-portals.dtsi"
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+@@ -0,0 +1,137 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for NXP LS1088A QDS Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Harninder Rai <harninder.rai@nxp.com>
++ *
++ */
++
++/dts-v1/;
++
++#include "fsl-ls1088a.dtsi"
++
++/ {
++	model = "LS1088A QDS Board";
++	compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
++};
++
++&i2c0 {
++	status = "okay";
++
++	i2c-switch@77 {
++		compatible = "nxp,pca9547";
++		reg = <0x77>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x2>;
++
++			ina220@40 {
++				compatible = "ti,ina220";
++				reg = <0x40>;
++				shunt-resistor = <1000>;
++			};
++
++			ina220@41 {
++				compatible = "ti,ina220";
++				reg = <0x41>;
++				shunt-resistor = <1000>;
++			};
++		};
++
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			temp-sensor@4c {
++				compatible = "adi,adt7461a";
++				reg = <0x4c>;
++			};
++
++			rtc@51 {
++				compatible = "nxp,pcf2129";
++				reg = <0x51>;
++				/* IRQ10_B */
++				interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			eeprom@56 {
++				compatible = "atmel,24c512";
++				reg = <0x56>;
++			};
++
++			eeprom@57 {
++				compatible = "atmel,24c512";
++				reg = <0x57>;
++			};
++		};
++	};
++};
++
++&qspi {
++	status = "okay";
++	qflash0: s25fs512s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		m25p,fast-read;
++		reg = <0>;
++	};
++
++	qflash1: s25fs512s@1 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		spi-max-frequency = <20000000>;
++		m25p,fast-read;
++		reg = <1>;
++	};
++};
++
++&ifc {
++	status = "okay";
++
++	ranges = <0 0 0x5 0x80000000 0x08000000
++		  2 0 0x5 0x30000000 0x00010000
++		  3 0 0x5 0x20000000 0x00010000>;
++
++	nor@0,0 {
++		compatible = "cfi-flash";
++		reg = <0x0 0x0 0x8000000>;
++		bank-width = <2>;
++		device-width = <1>;
++	};
++
++	nand@2,0 {
++		compatible = "fsl,ifc-nand";
++		reg = <0x2 0x0 0x10000>;
++	};
++
++	fpga: board-control@3,0 {
++		compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
++		reg = <0x3 0x0 0x0000100>;
++	};
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&duart1 {
++	status = "okay";
++};
++
++&esdhc {
++	status = "okay";
++};
++
++&sata {
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+@@ -0,0 +1,200 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for NXP LS1088A RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Harninder Rai <harninder.rai@nxp.com>
++ *
++ */
++
++/dts-v1/;
++
++#include "fsl-ls1088a.dtsi"
++
++/ {
++	model = "L1088A RDB Board";
++	compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
++};
++
++&i2c0 {
++	status = "okay";
++
++	i2c-switch@77 {
++		compatible = "nxp,pca9547";
++		reg = <0x77>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x2>;
++
++			ina220@40 {
++				compatible = "ti,ina220";
++				reg = <0x40>;
++				shunt-resistor = <1000>;
++			};
++		};
++
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			temp-sensor@4c {
++				compatible = "adi,adt7461a";
++				reg = <0x4c>;
++			};
++
++			rtc@51 {
++				compatible = "nxp,pcf2129";
++				reg = <0x51>;
++				/* IRQ10_B */
++				interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
++			};
++		};
++	};
++};
++
++&qspi {
++	status = "okay";
++	qflash0: s25fs512s@0 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		m25p,fast-read;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++
++	qflash1: s25fs512s@1 {
++		compatible = "spansion,m25p80";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		m25p,fast-read;
++		spi-max-frequency = <20000000>;
++		reg = <1>;
++	};
++};
++
++&ifc {
++	status = "okay";
++
++	ranges = <0 0 0x5 0x30000000 0x00010000
++		  2 0 0x5 0x20000000 0x00010000>;
++
++	nand@0,0 {
++		compatible = "fsl,ifc-nand";
++		reg = <0x0 0x0 0x10000>;
++	};
++
++	fpga: board-control@2,0 {
++		compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
++		reg = <0x2 0x0 0x0000100>;
++	};
++};
++
++&duart0 {
++	status = "okay";
++};
++
++&duart1 {
++	status = "okay";
++};
++
++&usb0 {
++	status = "okay";
++};
++
++&usb1 {
++	status = "okay";
++};
++
++&esdhc {
++	status = "okay";
++};
++
++&sata {
++	status = "okay";
++};
++
++&emdio1 {
++	/* Freescale F104 PHY1 */
++	mdio1_phy1: emdio1_phy@1 {
++		reg = <0x1c>;
++		phy-connection-type = "qsgmii";
++	};
++	mdio1_phy2: emdio1_phy@2 {
++		reg = <0x1d>;
++		phy-connection-type = "qsgmii";
++	};
++	mdio1_phy3: emdio1_phy@3 {
++		reg = <0x1e>;
++		phy-connection-type = "qsgmii";
++	};
++	mdio1_phy4: emdio1_phy@4 {
++		reg = <0x1f>;
++		phy-connection-type = "qsgmii";
++	};
++	/* F104 PHY2 */
++	mdio1_phy5: emdio1_phy@5 {
++		reg = <0x0c>;
++		phy-connection-type = "qsgmii";
++	};
++	mdio1_phy6: emdio1_phy@6 {
++		reg = <0x0d>;
++		phy-connection-type = "qsgmii";
++	};
++	mdio1_phy7: emdio1_phy@7 {
++		reg = <0x0e>;
++		phy-connection-type = "qsgmii";
++	};
++	mdio1_phy8: emdio1_phy@8 {
++		reg = <0x0f>;
++		phy-connection-type = "qsgmii";
++	};
++};
++
++&emdio2 {
++	/* Aquantia AQR105 10G PHY */
++	mdio2_phy1: emdio2_phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 2 0x4>;
++		reg = <0x0>;
++		phy-connection-type = "xfi";
++	};
++};
++
++/* DPMAC connections to external PHYs
++ * based on LS1088A RM RevC - $24.1.2 SerDes Options
++ */
++/* DPMAC1 is 10G SFP+, fixed link */
++&dpmac2 {
++	phy-handle = <&mdio2_phy1>;
++};
++&dpmac3 {
++	phy-handle = <&mdio1_phy5>;
++};
++&dpmac4 {
++	phy-handle = <&mdio1_phy6>;
++};
++&dpmac5 {
++	phy-handle = <&mdio1_phy7>;
++};
++&dpmac6 {
++	phy-handle = <&mdio1_phy8>;
++};
++&dpmac7 {
++	phy-handle = <&mdio1_phy1>;
++};
++&dpmac8 {
++	phy-handle = <&mdio1_phy2>;
++};
++&dpmac9 {
++	phy-handle = <&mdio1_phy3>;
++};
++&dpmac10 {
++	phy-handle = <&mdio1_phy4>;
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+@@ -0,0 +1,800 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for NXP Layerscape-1088A family SoC.
++ *
++ * Copyright 2017 NXP
++ *
++ * Harninder Rai <harninder.rai@nxp.com>
++ *
++ */
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++	compatible = "fsl,ls1088a";
++	interrupt-parent = <&gic>;
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	aliases {
++		crypto = &crypto;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		/* We have 2 clusters having 4 Cortex-A53 cores each */
++		cpu0: cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x0>;
++			clocks = <&clockgen 1 0>;
++			#cooling-cells = <2>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu1: cpu@1 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x1>;
++			clocks = <&clockgen 1 0>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu2: cpu@2 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x2>;
++			clocks = <&clockgen 1 0>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu3: cpu@3 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x3>;
++			clocks = <&clockgen 1 0>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu4: cpu@100 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x100>;
++			clocks = <&clockgen 1 1>;
++			#cooling-cells = <2>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu5: cpu@101 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x101>;
++			clocks = <&clockgen 1 1>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu6: cpu@102 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x102>;
++			clocks = <&clockgen 1 1>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++
++		cpu7: cpu@103 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a53";
++			reg = <0x103>;
++			clocks = <&clockgen 1 1>;
++			cpu-idle-states = <&CPU_PH20>;
++		};
++	};
++
++	idle-states {
++		/*
++		 * PSCI node is not added default, U-boot will add missing
++		 * parts if it determines to use PSCI.
++		 */
++		entry-method = "arm,psci";
++
++		CPU_PH20: cpu-ph20 {
++			compatible = "arm,idle-state";
++			idle-state-name = "PH20";
++			arm,psci-suspend-param = <0x0>;
++			entry-latency-us = <1000>;
++			exit-latency-us = <1000>;
++			min-residency-us = <3000>;
++		};
++	};
++
++	gic: interrupt-controller@6000000 {
++		compatible = "arm,gic-v3";
++		#interrupt-cells = <3>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		interrupt-controller;
++		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
++		      <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
++		      <0x0 0x0c0c0000 0 0x2000>, /* GICC */
++		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
++		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
++		interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
++
++		its: gic-its@6020000 {
++			compatible = "arm,gic-v3-its";
++			msi-controller;
++			reg = <0x0 0x6020000 0 0x20000>;
++		};
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
++			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
++			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
++			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
++	};
++
++	sysclk: sysclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <100000000>;
++		clock-output-names = "sysclk";
++	};
++
++	dcfg: dcfg@1e00000 {
++		compatible = "fsl,ls1088a-dcfg", "syscon";
++		reg = <0x0 0x1e00000 0x0 0x10000>;
++		little-endian;
++	};
++
++	rstcr: syscon@1e60000 {
++		compatible = "fsl,ls1088a-rstcr", "syscon";
++		reg = <0x0 0x1e60000 0x0 0x4>;
++	};
++
++	reboot {
++		compatible = "syscon-reboot";
++		regmap = <&rstcr>;
++		offset = <0x0>;
++		mask = <0x02>;
++	};
++
++
++	soc {
++		compatible = "simple-bus";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
++
++		clockgen: clocking@1300000 {
++			compatible = "fsl,ls1088a-clockgen";
++			reg = <0 0x1300000 0 0xa0000>;
++			#clock-cells = <2>;
++			clocks = <&sysclk>;
++		};
++
++		tmu: tmu@1f80000 {
++			compatible = "fsl,qoriq-tmu";
++			reg = <0x0 0x1f80000 0x0 0x10000>;
++			interrupts = <0 23 0x4>;
++			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++			fsl,tmu-calibration =
++				/* Calibration data group 1 */
++				<0x00000000 0x00000026
++				0x00000001 0x0000002d
++				0x00000002 0x00000032
++				0x00000003 0x00000039
++				0x00000004 0x0000003f
++				0x00000005 0x00000046
++				0x00000006 0x0000004d
++				0x00000007 0x00000054
++				0x00000008 0x0000005a
++				0x00000009 0x00000061
++				0x0000000a 0x0000006a
++				0x0000000b 0x00000071
++				/* Calibration data group 2 */
++				0x00010000 0x00000025
++				0x00010001 0x0000002c
++				0x00010002 0x00000035
++				0x00010003 0x0000003d
++				0x00010004 0x00000045
++				0x00010005 0x0000004e
++				0x00010006 0x00000057
++				0x00010007 0x00000061
++				0x00010008 0x0000006b
++				0x00010009 0x00000076
++				/* Calibration data group 3 */
++				0x00020000 0x00000029
++				0x00020001 0x00000033
++				0x00020002 0x0000003d
++				0x00020003 0x00000049
++				0x00020004 0x00000056
++				0x00020005 0x00000061
++				0x00020006 0x0000006d
++				/* Calibration data group 4 */
++				0x00030000 0x00000021
++				0x00030001 0x0000002a
++				0x00030002 0x0000003c
++				0x00030003 0x0000004e>;
++			little-endian;
++			#thermal-sensor-cells = <1>;
++		};
++
++		thermal-zones {
++			cpu_thermal: cpu-thermal {
++				polling-delay-passive = <1000>;
++				polling-delay = <5000>;
++				thermal-sensors = <&tmu 0>;
++
++				trips {
++					cpu_alert: cpu-alert {
++						temperature = <85000>;
++						hysteresis = <2000>;
++						type = "passive";
++					};
++
++					cpu_crit: cpu-crit {
++						temperature = <95000>;
++						hysteresis = <2000>;
++						type = "critical";
++					};
++				};
++
++				cooling-maps {
++					map0 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu0 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++					map1 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu4 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++				};
++			};
++		};
++
++		duart0: serial@21c0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21c0500 0x0 0x100>;
++			clocks = <&clockgen 4 3>;
++			interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
++			status = "disabled";
++		};
++
++		duart1: serial@21c0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21c0600 0x0 0x100>;
++			clocks = <&clockgen 4 3>;
++			interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
++			status = "disabled";
++		};
++
++		cluster1_core0_watchdog: wdt@c000000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc000000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster1_core1_watchdog: wdt@c010000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc010000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster1_core2_watchdog: wdt@c020000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc020000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster1_core3_watchdog: wdt@c030000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc030000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster2_core0_watchdog: wdt@c100000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc100000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster2_core1_watchdog: wdt@c110000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc110000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster2_core2_watchdog: wdt@c120000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc120000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster2_core3_watchdog: wdt@c130000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc130000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		gpio0: gpio@2300000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2300000 0x0 0x10000>;
++			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio1: gpio@2310000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2310000 0x0 0x10000>;
++			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio2: gpio@2320000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2320000 0x0 0x10000>;
++			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio3: gpio@2330000 {
++			compatible = "fsl,qoriq-gpio";
++			reg = <0x0 0x2330000 0x0 0x10000>;
++			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
++			gpio-controller;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		/* TODO: WRIOP (CCSR?) */
++		emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
++					  * E-MDIO1: 0x1_6000
++					  */
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8B96000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;	/* force the driver in LE mode */
++
++			/* Not necessary on the QDS, but needed on the RDB */
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
++					  * E-MDIO2: 0x1_7000
++					  */
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8B97000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;	/* force the driver in LE mode */
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		ifc: ifc@2240000 {
++			compatible = "fsl,ifc", "simple-bus";
++			reg = <0x0 0x2240000 0x0 0x20000>;
++			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
++			little-endian;
++			#address-cells = <2>;
++			#size-cells = <1>;
++
++		};
++
++		ftm0: ftm0@2800000 {
++			compatible = "fsl,ls1088a-ftm";
++			reg = <0x0 0x2800000 0x0 0x10000>,
++			      <0x0 0x1e34050 0x0 0x4>;
++			interrupts = <0 44 4>;
++			reg-names = "ftm", "FlexTimer1";
++		};
++
++		i2c0: i2c@2000000 {
++			compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2000000 0x0 0x10000>;
++			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 7>;
++			fsl-scl-gpio = <&gpio3 30 0>;
++			status = "disabled";
++		};
++
++		i2c1: i2c@2010000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2010000 0x0 0x10000>;
++			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 7>;
++			status = "disabled";
++		};
++
++		i2c2: i2c@2020000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2020000 0x0 0x10000>;
++			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 7>;
++			status = "disabled";
++		};
++
++		i2c3: i2c@2030000 {
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2030000 0x0 0x10000>;
++			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 7>;
++			status = "disabled";
++		};
++
++		qspi: quadspi@20c0000 {
++			compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x20c0000 0x0 0x10000>,
++				<0x0 0x20000000 0x0 0x10000000>;
++			reg-names = "QuadSPI", "QuadSPI-memory";
++			interrupts = <0 25 0x4>; /* Level high type */
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "qspi_en", "qspi";
++			fsl,qspi-has-second-chip;
++		};
++
++		esdhc: esdhc@2140000 {
++			compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
++			reg = <0x0 0x2140000 0x0 0x10000>;
++			interrupts = <0 28 0x4>; /* Level high type */
++			clock-frequency = <0>;
++			voltage-ranges = <1800 1800 3300 3300>;
++			sdhci,auto-cmd12;
++			little-endian;
++			bus-width = <4>;
++			status = "disabled";
++		};
++
++		usb0: usb3@3100000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3100000 0x0 0x10000>;
++			interrupts = <0 80 0x4>; /* Level high type */
++			dr_mode = "host";
++			configure-gfladj;
++			snps,dis_rxdet_inp3_quirk;
++		};
++
++		usb1: usb3@3110000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3110000 0x0 0x10000>;
++			interrupts = <0 81 0x4>; /* Level high type */
++			dr_mode = "host";
++			configure-gfladj;
++			snps,dis_rxdet_inp3_quirk;
++		};
++
++		sata: sata@3200000 {
++			compatible = "fsl,ls1088a-ahci";
++			reg = <0x0 0x3200000 0x0 0x10000>,
++				<0x7 0x100520 0x0 0x4>;
++			reg-names = "ahci", "sata-ecc";
++			interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&clockgen 4 3>;
++			dma-coherent;
++			status = "disabled";
++		};
++
++		pcie@3400000 {
++			compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
++				     "snps,dw-pcie";
++			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
++			       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++			interrupt-names = "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pcie@3500000 {
++			compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
++				     "snps,dw-pcie";
++			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
++			       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++			interrupt-names = "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		pcie@3600000 {
++			compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
++				     "snps,dw-pcie";
++			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
++			       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
++			reg-names = "regs", "config";
++			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++			interrupt-names = "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <8>;
++			bus-range = <0x0 0xff>;
++			ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
++				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
++					<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
++		fsl_mc: fsl-mc@80c000000 {
++			compatible = "fsl,qoriq-mc";
++			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
++			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
++			dma-coherent;
++			#address-cells = <3>;
++			#size-cells = <1>;
++
++			/*
++			 * Region type 0x0 - MC portals
++			 * Region type 0x1 - QBMAN portals
++			 */
++			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
++				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
++
++			dpmacs {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				dpmac1: dpmac@1 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <1>;
++				};
++
++				dpmac2: dpmac@2 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <2>;
++				};
++
++				dpmac3: dpmac@3 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <3>;
++				};
++
++				dpmac4: dpmac@4 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <4>;
++				};
++
++				dpmac5: dpmac@5 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <5>;
++				};
++
++				dpmac6: dpmac@6 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <6>;
++				};
++
++				dpmac7: dpmac@7 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <7>;
++				};
++
++				dpmac8: dpmac@8 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <8>;
++				};
++
++				dpmac9: dpmac@9 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <9>;
++				};
++
++				dpmac10: dpmac@a {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0xa>;
++				};
++			};
++		};
++
++		smmu: iommu@5000000 {
++			compatible = "arm,mmu-500";
++			reg = <0 0x5000000 0 0x800000>;
++			#global-interrupts = <12>;
++			#iommu-cells = <1>;
++			stream-match-mask = <0x7C00>;
++			interrupts = <0 13 4>, /* global secure fault */
++				     <0 14 4>, /* combined secure interrupt */
++				     <0 15 4>, /* global non-secure fault */
++				     <0 16 4>, /* combined non-secure interrupt */
++				/* performance counter interrupts 0-7 */
++				     <0 211 4>,
++				     <0 212 4>,
++				     <0 213 4>,
++				     <0 214 4>,
++				     <0 215 4>,
++				     <0 216 4>,
++				     <0 217 4>,
++				     <0 218 4>,
++				/* per context interrupt, 64 interrupts */
++				     <0 146 4>,
++				     <0 147 4>,
++				     <0 148 4>,
++				     <0 149 4>,
++				     <0 150 4>,
++				     <0 151 4>,
++				     <0 152 4>,
++				     <0 153 4>,
++				     <0 154 4>,
++				     <0 155 4>,
++				     <0 156 4>,
++				     <0 157 4>,
++				     <0 158 4>,
++				     <0 159 4>,
++				     <0 160 4>,
++				     <0 161 4>,
++				     <0 162 4>,
++				     <0 163 4>,
++				     <0 164 4>,
++				     <0 165 4>,
++				     <0 166 4>,
++				     <0 167 4>,
++				     <0 168 4>,
++				     <0 169 4>,
++				     <0 170 4>,
++				     <0 171 4>,
++				     <0 172 4>,
++				     <0 173 4>,
++				     <0 174 4>,
++				     <0 175 4>,
++				     <0 176 4>,
++				     <0 177 4>,
++				     <0 178 4>,
++				     <0 179 4>,
++				     <0 180 4>,
++				     <0 181 4>,
++				     <0 182 4>,
++				     <0 183 4>,
++				     <0 184 4>,
++				     <0 185 4>,
++				     <0 186 4>,
++				     <0 187 4>,
++				     <0 188 4>,
++				     <0 189 4>,
++				     <0 190 4>,
++				     <0 191 4>,
++				     <0 192 4>,
++				     <0 193 4>,
++				     <0 194 4>,
++				     <0 195 4>,
++				     <0 196 4>,
++				     <0 197 4>,
++				     <0 198 4>,
++				     <0 199 4>,
++				     <0 200 4>,
++				     <0 201 4>,
++				     <0 202 4>,
++				     <0 203 4>,
++				     <0 204 4>,
++				     <0 205 4>,
++				     <0 206 4>,
++				     <0 207 4>,
++				     <0 208 4>,
++				     <0 209 4>;
++		};
++
++		crypto: crypto@8000000 {
++			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
++			fsl,sec-era = <8>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0x0 0x00 0x8000000 0x100000>;
++			reg = <0x00 0x8000000 0x0 0x100000>;
++			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
++			dma-coherent;
++
++			sec_jr0: jr@10000 {
++				compatible = "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x10000 0x10000>;
++				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr1: jr@20000 {
++				compatible = "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x20000 0x10000>;
++				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr2: jr@30000 {
++				compatible = "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x30000 0x10000>;
++				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr3: jr@40000 {
++				compatible = "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x40000 0x10000>;
++				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			};
++		};
++	};
++
++	firmware {
++		optee {
++			compatible = "linaro,optee-tz";
++			method = "smc";
++		};
++	};
++
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+@@ -1,214 +1,87 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+  * Device Tree file for Freescale LS2080a QDS Board.
+  *
+- * Copyright (C) 2015, Freescale Semiconductor
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
+  *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+  *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- *  a) This library is free software; you can redistribute it and/or
+- *     modify it under the terms of the GNU General Public License as
+- *     published by the Free Software Foundation; either version 2 of the
+- *     License, or (at your option) any later version.
+- *
+- *     This library is distributed in the hope that it will be useful,
+- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *     GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- *  b) Permission is hereby granted, free of charge, to any person
+- *     obtaining a copy of this software and associated documentation
+- *     files (the "Software"), to deal in the Software without
+- *     restriction, including without limitation the rights to use,
+- *     copy, modify, merge, publish, distribute, sublicense, and/or
+- *     sell copies of the Software, and to permit persons to whom the
+- *     Software is furnished to do so, subject to the following
+- *     conditions:
+- *
+- *     The above copyright notice and this permission notice shall be
+- *     included in all copies or substantial portions of the Software.
+- *
+- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+ /dts-v1/;
+ 
+-/include/ "fsl-ls2080a.dtsi"
++#include "fsl-ls2080a.dtsi"
++#include "fsl-ls208xa-qds.dtsi"
+ 
+ / {
+ 	model = "Freescale Layerscape 2080a QDS Board";
+ 	compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
+ 
+-	aliases {
+-		serial0 = &serial0;
+-		serial1 = &serial1;
+-	};
+-
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ };
+ 
+-&esdhc {
+-	status = "okay";
+-};
+-
+ &ifc {
+-	status = "okay";
+-	#address-cells = <2>;
+-	#size-cells = <1>;
+-	ranges = <0x0 0x0 0x5 0x80000000 0x08000000
+-		  0x2 0x0 0x5 0x30000000 0x00010000
+-		  0x3 0x0 0x5 0x20000000 0x00010000>;
+-
+-	nor@0,0 {
++	boardctrl: board-control@3,0 {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+-		compatible = "cfi-flash";
+-		reg = <0x0 0x0 0x8000000>;
+-		bank-width = <2>;
+-		device-width = <1>;
+-	};
+-
+-	nand@2,0 {
+-	     compatible = "fsl,ifc-nand";
+-	     reg = <0x2 0x0 0x10000>;
+-	};
++		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
++		reg = <3 0 0x300>;		/* TODO check address */
++		ranges = <0 3 0 0x300>;
+ 
+-	cpld@3,0 {
+-	     reg = <0x3 0x0 0x10000>;
+-	     compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
+-	};
+-};
+-
+-&i2c0 {
+-	status = "okay";
+-	pca9547@77 {
+-		compatible = "nxp,pca9547";
+-		reg = <0x77>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		i2c@0 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x00>;
+-			rtc@68 {
+-				compatible = "dallas,ds3232";
+-				reg = <0x68>;
+-			};
+-		};
+-
+-		i2c@2 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x02>;
+-
+-			ina220@40 {
+-				compatible = "ti,ina220";
+-				reg = <0x40>;
+-				shunt-resistor = <500>;
+-			};
+-
+-			ina220@41 {
+-				compatible = "ti,ina220";
+-				reg = <0x41>;
+-				shunt-resistor = <1000>;
+-			};
+-		};
++		mdio_mux_emi1 {
++			compatible = "mdio-mux-mmioreg", "mdio-mux";
++			mdio-parent-bus = <&emdio1>;
++			reg = <0x54 1>;		/* BRDCFG4 */
++			mux-mask = <0xe0>;	/* EMI1_MDIO */
+ 
+-		i2c@3 {
+-			#address-cells = <1>;
++			#address-cells=<1>;
+ 			#size-cells = <0>;
+-			reg = <0x3>;
+ 
+-			adt7481@4c {
+-				compatible = "adi,adt7461";
+-				reg = <0x4c>;
++			/* Child MDIO buses, one for each riser card:
++			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
++			 * VSC8234 PHYs on the riser cards.
++			 */
++
++			mdio_mux3: mdio@60 {
++				reg = <0x60>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mdio0_phy12: mdio_phy0@1c {
++					reg = <0x1c>;
++					phy-connection-type = "sgmii";
++				};
++				mdio0_phy13: mdio_phy1@1d {
++					reg = <0x1d>;
++					phy-connection-type = "sgmii";
++				};
++				mdio0_phy14: mdio_phy2@1e {
++					reg = <0x1e>;
++					phy-connection-type = "sgmii";
++				};
++				mdio0_phy15: mdio_phy3@1f {
++					reg = <0x1f>;
++					phy-connection-type = "sgmii";
++				};
+ 			};
+ 		};
+ 	};
+ };
+ 
+-&i2c1 {
+-	status = "disabled";
++/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
++&dpmac9 {
++	phy-handle = <&mdio0_phy12>;
+ };
+-
+-&i2c2 {
+-	status = "disabled";
+-};
+-
+-&i2c3 {
+-	status = "disabled";
+-};
+-
+-&dspi {
+-	status = "okay";
+-	dflash0: n25q128a {
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		compatible = "st,m25p80";
+-		spi-max-frequency = <3000000>;
+-		reg = <0>;
+-	};
+-	dflash1: sst25wf040b {
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		compatible = "st,m25p80";
+-		spi-max-frequency = <3000000>;
+-		reg = <1>;
+-	};
+-	dflash2: en25s64 {
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		compatible = "st,m25p80";
+-		spi-max-frequency = <3000000>;
+-		reg = <2>;
+-	};
++&dpmac10 {
++	phy-handle = <&mdio0_phy13>;
+ };
+-
+-&qspi {
+-	status = "okay";
+-	flash0: s25fl256s1@0 {
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		compatible = "st,m25p80";
+-		spi-max-frequency = <20000000>;
+-		reg = <0>;
+-	};
+-	flash2: s25fl256s1@2 {
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		compatible = "st,m25p80";
+-		spi-max-frequency = <20000000>;
+-		reg = <0>;
+-	};
++&dpmac11 {
++	phy-handle = <&mdio0_phy14>;
+ };
+-
+-&sata0 {
+-	status = "okay";
+-};
+-
+-&sata1 {
+-	status = "okay";
+-};
+-
+-&usb0 {
+-	status = "okay";
+-};
+-
+-&usb1 {
+-	status = "okay";
++&dpmac12 {
++	phy-handle = <&mdio0_phy15>;
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+@@ -1,170 +1,105 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+  * Device Tree file for Freescale LS2080a RDB Board.
+  *
+- * Copyright (C) 2015, Freescale Semiconductor
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
+  *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+  *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- *  a) This library is free software; you can redistribute it and/or
+- *     modify it under the terms of the GNU General Public License as
+- *     published by the Free Software Foundation; either version 2 of the
+- *     License, or (at your option) any later version.
+- *
+- *     This library is distributed in the hope that it will be useful,
+- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *     GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- *  b) Permission is hereby granted, free of charge, to any person
+- *     obtaining a copy of this software and associated documentation
+- *     files (the "Software"), to deal in the Software without
+- *     restriction, including without limitation the rights to use,
+- *     copy, modify, merge, publish, distribute, sublicense, and/or
+- *     sell copies of the Software, and to permit persons to whom the
+- *     Software is furnished to do so, subject to the following
+- *     conditions:
+- *
+- *     The above copyright notice and this permission notice shall be
+- *     included in all copies or substantial portions of the Software.
+- *
+- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+ /dts-v1/;
+ 
+-/include/ "fsl-ls2080a.dtsi"
++#include "fsl-ls2080a.dtsi"
++#include "fsl-ls208xa-rdb.dtsi"
+ 
+ / {
+ 	model = "Freescale Layerscape 2080a RDB Board";
+ 	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
+ 
+-	aliases {
+-		serial0 = &serial0;
+-		serial1 = &serial1;
+-	};
+-
+ 	chosen {
+ 		stdout-path = "serial1:115200n8";
+ 	};
+ };
+ 
+-&esdhc {
+-	status = "okay";
+-};
+-
+-&ifc {
+-	status = "okay";
+-	#address-cells = <2>;
+-	#size-cells = <1>;
+-	ranges = <0x0 0x0 0x5 0x80000000 0x08000000
+-		  0x2 0x0 0x5 0x30000000 0x00010000
+-		  0x3 0x0 0x5 0x20000000 0x00010000>;
+-
+-	nor@0,0 {
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		compatible = "cfi-flash";
+-		reg = <0x0 0x0 0x8000000>;
+-		bank-width = <2>;
+-		device-width = <1>;
+-	};
+-
+-	nand@2,0 {
+-	     compatible = "fsl,ifc-nand";
+-	     reg = <0x2 0x0 0x10000>;
+-	};
+-
+-	cpld@3,0 {
+-	     reg = <0x3 0x0 0x10000>;
+-	     compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
+-	};
+-
+-};
+-
+-&i2c0 {
+-	status = "okay";
+-	pca9547@75 {
+-		compatible = "nxp,pca9547";
+-		reg = <0x75>;
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		status = "disabled";
+-		i2c@1 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x01>;
+-			rtc@68 {
+-				compatible = "dallas,ds3232";
+-				reg = <0x68>;
+-			};
+-		};
+-
+-		i2c@3 {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x3>;
+-
+-			adt7481@4c {
+-				compatible = "adi,adt7461";
+-				reg = <0x4c>;
+-			};
+-		};
+-	};
+-};
+-
+-&i2c1 {
+-	status = "disabled";
+-};
+-
+-&i2c2 {
+-	status = "disabled";
+-};
+-
+-&i2c3 {
++&emdio1 {
+ 	status = "disabled";
++	/* CS4340 PHYs */
++	mdio1_phy1: emdio1_phy@1 {
++		reg = <0x10>;
++		phy-connection-type = "xfi";
++	};
++	mdio1_phy2: emdio1_phy@2 {
++		reg = <0x11>;
++		phy-connection-type = "xfi";
++	};
++	mdio1_phy3: emdio1_phy@3 {
++		reg = <0x12>;
++		phy-connection-type = "xfi";
++	};
++	mdio1_phy4: emdio1_phy@4 {
++		reg = <0x13>;
++		phy-connection-type = "xfi";
++	};
+ };
+ 
+-&dspi {
+-	status = "okay";
+-	dflash0: n25q512a {
+-		#address-cells = <1>;
+-		#size-cells = <1>;
+-		compatible = "st,m25p80";
+-		spi-max-frequency = <3000000>;
+-		reg = <0>;
++&emdio2 {
++	/* AQR405 PHYs */
++	mdio2_phy1: emdio2_phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 1 0x4>; /* Level high type */
++		reg = <0x0>;
++		phy-connection-type = "xfi";
++	};
++	mdio2_phy2: emdio2_phy@2 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 2 0x4>; /* Level high type */
++		reg = <0x1>;
++		phy-connection-type = "xfi";
++	};
++	mdio2_phy3: emdio2_phy@3 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 4 0x4>; /* Level high type */
++		reg = <0x2>;
++		phy-connection-type = "xfi";
++	};
++	mdio2_phy4: emdio2_phy@4 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 5 0x4>; /* Level high type */
++		reg = <0x3>;
++		phy-connection-type = "xfi";
+ 	};
+ };
+ 
+-&qspi {
+-	status = "disabled";
+-};
++/* Update DPMAC connections to external PHYs, under the assumption of
++ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
++ */
++/* Leave Cortina nodes commented out until driver is integrated
++ *&dpmac1 {
++ *	phy-handle = <&mdio1_phy1>;
++ *};
++ *&dpmac2 {
++ *	phy-handle = <&mdio1_phy2>;
++ *};
++ *&dpmac3 {
++ *	phy-handle = <&mdio1_phy3>;
++ *};
++ *&dpmac4 {
++ *	phy-handle = <&mdio1_phy4>;
++ *};
++ */
+ 
+-&sata0 {
+-	status = "okay";
++&dpmac5 {
++	phy-handle = <&mdio2_phy1>;
+ };
+-
+-&sata1 {
+-	status = "okay";
++&dpmac6 {
++	phy-handle = <&mdio2_phy2>;
+ };
+-
+-&usb0 {
+-	status = "okay";
++&dpmac7 {
++	phy-handle = <&mdio2_phy3>;
+ };
+-
+-&usb1 {
+-	status = "okay";
++&dpmac8 {
++	phy-handle = <&mdio2_phy4>;
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+@@ -1,62 +1,21 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+  * Device Tree file for Freescale LS2080a software Simulator model
+  *
+- * Copyright (C) 2014-2015, Freescale Semiconductor
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+  *
+  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+  *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPL or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- *  a) This library is free software; you can redistribute it and/or
+- *     modify it under the terms of the GNU General Public License as
+- *     published by the Free Software Foundation; either version 2 of the
+- *     License, or (at your option) any later version.
+- *
+- *     This library is distributed in the hope that it will be useful,
+- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *     GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- *  b) Permission is hereby granted, free of charge, to any person
+- *     obtaining a copy of this software and associated documentation
+- *     files (the "Software"), to deal in the Software without
+- *     restriction, including without limitation the rights to use,
+- *     copy, modify, merge, publish, distribute, sublicense, and/or
+- *     sell copies of the Software, and to permit persons to whom the
+- *     Software is furnished to do so, subject to the following
+- *     conditions:
+- *
+- *     The above copyright notice and this permission notice shall be
+- *     included in all copies or substantial portions of the Software.
+- *
+- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+ /dts-v1/;
+ 
+-/include/ "fsl-ls2080a.dtsi"
++#include "fsl-ls2080a.dtsi"
+ 
+ / {
+ 	model = "Freescale Layerscape 2080a software Simulator model";
+ 	compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
+ 
+-	aliases {
+-		serial0 = &serial0;
+-		serial1 = &serial1;
+-	};
+-
+ 	ethernet@2210000 {
+ 		compatible = "smsc,lan91c111";
+ 		reg = <0x0 0x2210000 0x0 0x100>;
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+@@ -1,739 +1,144 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+  * Device Tree Include file for Freescale Layerscape-2080A family SoC.
+  *
+- * Copyright (C) 2014-2015, Freescale Semiconductor
++ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+  *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
+  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+  *
+- * This file is dual-licensed: you can use it either under the terms
+- * of the GPLv2 or the X11 license, at your option. Note that this dual
+- * licensing only applies to this file, and not this project as a
+- * whole.
+- *
+- *  a) This library is free software; you can redistribute it and/or
+- *     modify it under the terms of the GNU General Public License as
+- *     published by the Free Software Foundation; either version 2 of the
+- *     License, or (at your option) any later version.
+- *
+- *     This library is distributed in the hope that it will be useful,
+- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+- *     GNU General Public License for more details.
+- *
+- * Or, alternatively,
+- *
+- *  b) Permission is hereby granted, free of charge, to any person
+- *     obtaining a copy of this software and associated documentation
+- *     files (the "Software"), to deal in the Software without
+- *     restriction, including without limitation the rights to use,
+- *     copy, modify, merge, publish, distribute, sublicense, and/or
+- *     sell copies of the Software, and to permit persons to whom the
+- *     Software is furnished to do so, subject to the following
+- *     conditions:
+- *
+- *     The above copyright notice and this permission notice shall be
+- *     included in all copies or substantial portions of the Software.
+- *
+- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+- *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+-/ {
+-	compatible = "fsl,ls2080a";
+-	interrupt-parent = <&gic>;
+-	#address-cells = <2>;
+-	#size-cells = <2>;
+-
+-	cpus {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-
+-		/*
+-		 * We expect the enable-method for cpu's to be "psci", but this
+-		 * is dependent on the SoC FW, which will fill this in.
+-		 *
+-		 * Currently supported enable-method is psci v0.2
+-		 */
+-
+-		/* We have 4 clusters having 2 Cortex-A57 cores each */
+-		cpu@0 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a57";
+-			reg = <0x0>;
+-			clocks = <&clockgen 1 0>;
+-			next-level-cache = <&cluster0_l2>;
+-		};
+-
+-		cpu@1 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a57";
+-			reg = <0x1>;
+-			clocks = <&clockgen 1 0>;
+-			next-level-cache = <&cluster0_l2>;
+-		};
+-
+-		cpu@100 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a57";
+-			reg = <0x100>;
+-			clocks = <&clockgen 1 1>;
+-			next-level-cache = <&cluster1_l2>;
+-		};
+-
+-		cpu@101 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a57";
+-			reg = <0x101>;
+-			clocks = <&clockgen 1 1>;
+-			next-level-cache = <&cluster1_l2>;
+-		};
+-
+-		cpu@200 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a57";
+-			reg = <0x200>;
+-			clocks = <&clockgen 1 2>;
+-			next-level-cache = <&cluster2_l2>;
+-		};
+-
+-		cpu@201 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a57";
+-			reg = <0x201>;
+-			clocks = <&clockgen 1 2>;
+-			next-level-cache = <&cluster2_l2>;
+-		};
+-
+-		cpu@300 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a57";
+-			reg = <0x300>;
+-			clocks = <&clockgen 1 3>;
+-			next-level-cache = <&cluster3_l2>;
+-		};
+-
+-		cpu@301 {
+-			device_type = "cpu";
+-			compatible = "arm,cortex-a57";
+-			reg = <0x301>;
+-			clocks = <&clockgen 1 3>;
+-			next-level-cache = <&cluster3_l2>;
+-		};
+-
+-		cluster0_l2: l2-cache0 {
+-			compatible = "cache";
+-		};
+-
+-		cluster1_l2: l2-cache1 {
+-			compatible = "cache";
+-		};
+-
+-		cluster2_l2: l2-cache2 {
+-			compatible = "cache";
+-		};
+-
+-		cluster3_l2: l2-cache3 {
+-			compatible = "cache";
+-		};
+-	};
+-
+-	memory@80000000 {
+-		device_type = "memory";
+-		reg = <0x00000000 0x80000000 0 0x80000000>;
+-		      /* DRAM space - 1, size : 2 GB DRAM */
+-	};
+-
+-	sysclk: sysclk {
+-		compatible = "fixed-clock";
+-		#clock-cells = <0>;
+-		clock-frequency = <100000000>;
+-		clock-output-names = "sysclk";
+-	};
+-
+-	gic: interrupt-controller@6000000 {
+-		compatible = "arm,gic-v3";
+-		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+-			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
+-			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
+-			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
+-			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
+-		#interrupt-cells = <3>;
+-		#address-cells = <2>;
+-		#size-cells = <2>;
+-		ranges;
+-		interrupt-controller;
+-		interrupts = <1 9 0x4>;
+-
+-		its: gic-its@6020000 {
+-			compatible = "arm,gic-v3-its";
+-			msi-controller;
+-			reg = <0x0 0x6020000 0 0x20000>;
+-		};
+-	};
+-
+-	rstcr: syscon@1e60000 {
+-		compatible = "fsl,ls2080a-rstcr", "syscon";
+-		reg = <0x0 0x1e60000 0x0 0x4>;
+-	};
+-
+-	reboot {
+-		compatible ="syscon-reboot";
+-		regmap = <&rstcr>;
+-		offset = <0x0>;
+-		mask = <0x2>;
+-	};
+-
+-	timer {
+-		compatible = "arm,armv8-timer";
+-		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
+-			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
+-			     <1 11 4>, /* Virtual PPI, active-low */
+-			     <1 10 4>; /* Hypervisor PPI, active-low */
+-		fsl,erratum-a008585;
+-	};
+-
+-	pmu {
+-		compatible = "arm,armv8-pmuv3";
+-		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
+-	};
+-
+-	soc {
+-		compatible = "simple-bus";
+-		#address-cells = <2>;
+-		#size-cells = <2>;
+-		ranges;
+-
+-		clockgen: clocking@1300000 {
+-			compatible = "fsl,ls2080a-clockgen";
+-			reg = <0 0x1300000 0 0xa0000>;
+-			#clock-cells = <2>;
+-			clocks = <&sysclk>;
+-		};
+-
+-		serial0: serial@21c0500 {
+-			compatible = "fsl,ns16550", "ns16550a";
+-			reg = <0x0 0x21c0500 0x0 0x100>;
+-			clocks = <&clockgen 4 3>;
+-			interrupts = <0 32 0x4>; /* Level high type */
+-		};
+-
+-		serial1: serial@21c0600 {
+-			compatible = "fsl,ns16550", "ns16550a";
+-			reg = <0x0 0x21c0600 0x0 0x100>;
+-			clocks = <&clockgen 4 3>;
+-			interrupts = <0 32 0x4>; /* Level high type */
+-		};
+-
+-		cluster1_core0_watchdog: wdt@c000000 {
+-			compatible = "arm,sp805-wdt", "arm,primecell";
+-			reg = <0x0 0xc000000 0x0 0x1000>;
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "apb_pclk", "wdog_clk";
+-		};
+-
+-		cluster1_core1_watchdog: wdt@c010000 {
+-			compatible = "arm,sp805-wdt", "arm,primecell";
+-			reg = <0x0 0xc010000 0x0 0x1000>;
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "apb_pclk", "wdog_clk";
+-		};
+-
+-		cluster2_core0_watchdog: wdt@c100000 {
+-			compatible = "arm,sp805-wdt", "arm,primecell";
+-			reg = <0x0 0xc100000 0x0 0x1000>;
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "apb_pclk", "wdog_clk";
+-		};
+-
+-		cluster2_core1_watchdog: wdt@c110000 {
+-			compatible = "arm,sp805-wdt", "arm,primecell";
+-			reg = <0x0 0xc110000 0x0 0x1000>;
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "apb_pclk", "wdog_clk";
+-		};
+-
+-		cluster3_core0_watchdog: wdt@c200000 {
+-			compatible = "arm,sp805-wdt", "arm,primecell";
+-			reg = <0x0 0xc200000 0x0 0x1000>;
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "apb_pclk", "wdog_clk";
+-		};
+-
+-		cluster3_core1_watchdog: wdt@c210000 {
+-			compatible = "arm,sp805-wdt", "arm,primecell";
+-			reg = <0x0 0xc210000 0x0 0x1000>;
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "apb_pclk", "wdog_clk";
+-		};
+-
+-		cluster4_core0_watchdog: wdt@c300000 {
+-			compatible = "arm,sp805-wdt", "arm,primecell";
+-			reg = <0x0 0xc300000 0x0 0x1000>;
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "apb_pclk", "wdog_clk";
+-		};
+-
+-		cluster4_core1_watchdog: wdt@c310000 {
+-			compatible = "arm,sp805-wdt", "arm,primecell";
+-			reg = <0x0 0xc310000 0x0 0x1000>;
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "apb_pclk", "wdog_clk";
+-		};
+-
+-		fsl_mc: fsl-mc@80c000000 {
+-			compatible = "fsl,qoriq-mc";
+-			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
+-			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+-			msi-parent = <&its>;
+-			#address-cells = <3>;
+-			#size-cells = <1>;
+-
+-			/*
+-			 * Region type 0x0 - MC portals
+-			 * Region type 0x1 - QBMAN portals
+-			 */
+-			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+-				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+-
+-			/*
+-			 * Define the maximum number of MACs present on the SoC.
+-			 */
+-			dpmacs {
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				dpmac1: dpmac@1 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x1>;
+-				};
+-
+-				dpmac2: dpmac@2 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x2>;
+-				};
+-
+-				dpmac3: dpmac@3 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x3>;
+-				};
+-
+-				dpmac4: dpmac@4 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x4>;
+-				};
+-
+-				dpmac5: dpmac@5 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x5>;
+-				};
+-
+-				dpmac6: dpmac@6 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x6>;
+-				};
+-
+-				dpmac7: dpmac@7 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x7>;
+-				};
+-
+-				dpmac8: dpmac@8 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x8>;
+-				};
+-
+-				dpmac9: dpmac@9 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x9>;
+-				};
+-
+-				dpmac10: dpmac@a {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0xa>;
+-				};
+-
+-				dpmac11: dpmac@b {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0xb>;
+-				};
+-
+-				dpmac12: dpmac@c {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0xc>;
+-				};
+-
+-				dpmac13: dpmac@d {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0xd>;
+-				};
+-
+-				dpmac14: dpmac@e {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0xe>;
+-				};
+-
+-				dpmac15: dpmac@f {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0xf>;
+-				};
+-
+-				dpmac16: dpmac@10 {
+-					compatible = "fsl,qoriq-mc-dpmac";
+-					reg = <0x10>;
+-				};
+-			};
+-		};
+-
+-		smmu: iommu@5000000 {
+-			compatible = "arm,mmu-500";
+-			reg = <0 0x5000000 0 0x800000>;
+-			#global-interrupts = <12>;
+-			interrupts = <0 13 4>, /* global secure fault */
+-				     <0 14 4>, /* combined secure interrupt */
+-				     <0 15 4>, /* global non-secure fault */
+-				     <0 16 4>, /* combined non-secure interrupt */
+-				/* performance counter interrupts 0-7 */
+-				     <0 211 4>, <0 212 4>,
+-				     <0 213 4>, <0 214 4>,
+-				     <0 215 4>, <0 216 4>,
+-				     <0 217 4>, <0 218 4>,
+-				/* per context interrupt, 64 interrupts */
+-				     <0 146 4>, <0 147 4>,
+-				     <0 148 4>, <0 149 4>,
+-				     <0 150 4>, <0 151 4>,
+-				     <0 152 4>, <0 153 4>,
+-				     <0 154 4>, <0 155 4>,
+-				     <0 156 4>, <0 157 4>,
+-				     <0 158 4>, <0 159 4>,
+-				     <0 160 4>, <0 161 4>,
+-				     <0 162 4>, <0 163 4>,
+-				     <0 164 4>, <0 165 4>,
+-				     <0 166 4>, <0 167 4>,
+-				     <0 168 4>, <0 169 4>,
+-				     <0 170 4>, <0 171 4>,
+-				     <0 172 4>, <0 173 4>,
+-				     <0 174 4>, <0 175 4>,
+-				     <0 176 4>, <0 177 4>,
+-				     <0 178 4>, <0 179 4>,
+-				     <0 180 4>, <0 181 4>,
+-				     <0 182 4>, <0 183 4>,
+-				     <0 184 4>, <0 185 4>,
+-				     <0 186 4>, <0 187 4>,
+-				     <0 188 4>, <0 189 4>,
+-				     <0 190 4>, <0 191 4>,
+-				     <0 192 4>, <0 193 4>,
+-				     <0 194 4>, <0 195 4>,
+-				     <0 196 4>, <0 197 4>,
+-				     <0 198 4>, <0 199 4>,
+-				     <0 200 4>, <0 201 4>,
+-				     <0 202 4>, <0 203 4>,
+-				     <0 204 4>, <0 205 4>,
+-				     <0 206 4>, <0 207 4>,
+-				     <0 208 4>, <0 209 4>;
+-			mmu-masters = <&fsl_mc 0x300 0>;
+-		};
+-
+-		dspi: dspi@2100000 {
+-			status = "disabled";
+-			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x0 0x2100000 0x0 0x10000>;
+-			interrupts = <0 26 0x4>; /* Level high type */
+-			clocks = <&clockgen 4 3>;
+-			clock-names = "dspi";
+-			spi-num-chipselects = <5>;
+-			bus-num = <0>;
+-		};
+-
+-		esdhc: esdhc@2140000 {
+-			status = "disabled";
+-			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
+-			reg = <0x0 0x2140000 0x0 0x10000>;
+-			interrupts = <0 28 0x4>; /* Level high type */
+-			clock-frequency = <0>;	/* Updated by bootloader */
+-			voltage-ranges = <1800 1800 3300 3300>;
+-			sdhci,auto-cmd12;
+-			little-endian;
+-			bus-width = <4>;
+-		};
+-
+-		gpio0: gpio@2300000 {
+-			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+-			reg = <0x0 0x2300000 0x0 0x10000>;
+-			interrupts = <0 36 0x4>; /* Level high type */
+-			gpio-controller;
+-			little-endian;
+-			#gpio-cells = <2>;
+-			interrupt-controller;
+-			#interrupt-cells = <2>;
+-		};
+-
+-		gpio1: gpio@2310000 {
+-			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+-			reg = <0x0 0x2310000 0x0 0x10000>;
+-			interrupts = <0 36 0x4>; /* Level high type */
+-			gpio-controller;
+-			little-endian;
+-			#gpio-cells = <2>;
+-			interrupt-controller;
+-			#interrupt-cells = <2>;
+-		};
+-
+-		gpio2: gpio@2320000 {
+-			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+-			reg = <0x0 0x2320000 0x0 0x10000>;
+-			interrupts = <0 37 0x4>; /* Level high type */
+-			gpio-controller;
+-			little-endian;
+-			#gpio-cells = <2>;
+-			interrupt-controller;
+-			#interrupt-cells = <2>;
+-		};
+-
+-		gpio3: gpio@2330000 {
+-			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+-			reg = <0x0 0x2330000 0x0 0x10000>;
+-			interrupts = <0 37 0x4>; /* Level high type */
+-			gpio-controller;
+-			little-endian;
+-			#gpio-cells = <2>;
+-			interrupt-controller;
+-			#interrupt-cells = <2>;
+-		};
+-
+-		i2c0: i2c@2000000 {
+-			status = "disabled";
+-			compatible = "fsl,vf610-i2c";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x0 0x2000000 0x0 0x10000>;
+-			interrupts = <0 34 0x4>; /* Level high type */
+-			clock-names = "i2c";
+-			clocks = <&clockgen 4 3>;
+-		};
+-
+-		i2c1: i2c@2010000 {
+-			status = "disabled";
+-			compatible = "fsl,vf610-i2c";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x0 0x2010000 0x0 0x10000>;
+-			interrupts = <0 34 0x4>; /* Level high type */
+-			clock-names = "i2c";
+-			clocks = <&clockgen 4 3>;
+-		};
+-
+-		i2c2: i2c@2020000 {
+-			status = "disabled";
+-			compatible = "fsl,vf610-i2c";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x0 0x2020000 0x0 0x10000>;
+-			interrupts = <0 35 0x4>; /* Level high type */
+-			clock-names = "i2c";
+-			clocks = <&clockgen 4 3>;
+-		};
+-
+-		i2c3: i2c@2030000 {
+-			status = "disabled";
+-			compatible = "fsl,vf610-i2c";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x0 0x2030000 0x0 0x10000>;
+-			interrupts = <0 35 0x4>; /* Level high type */
+-			clock-names = "i2c";
+-			clocks = <&clockgen 4 3>;
+-		};
+-
+-		ifc: ifc@2240000 {
+-			compatible = "fsl,ifc", "simple-bus";
+-			reg = <0x0 0x2240000 0x0 0x20000>;
+-			interrupts = <0 21 0x4>; /* Level high type */
+-			little-endian;
+-			#address-cells = <2>;
+-			#size-cells = <1>;
+-
+-			ranges = <0 0 0x5 0x80000000 0x08000000
+-				  2 0 0x5 0x30000000 0x00010000
+-				  3 0 0x5 0x20000000 0x00010000>;
+-		};
+-
+-		qspi: quadspi@20c0000 {
+-			status = "disabled";
+-			compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			reg = <0x0 0x20c0000 0x0 0x10000>,
+-			      <0x0 0x20000000 0x0 0x10000000>;
+-			reg-names = "QuadSPI", "QuadSPI-memory";
+-			interrupts = <0 25 0x4>; /* Level high type */
+-			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+-			clock-names = "qspi_en", "qspi";
+-		};
+-
+-		pcie@3400000 {
+-			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
+-				     "snps,dw-pcie";
+-			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+-			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
+-			reg-names = "regs", "config";
+-			interrupts = <0 108 0x4>; /* Level high type */
+-			interrupt-names = "intr";
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			device_type = "pci";
+-			dma-coherent;
+-			num-lanes = <4>;
+-			bus-range = <0x0 0xff>;
+-			ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */
+-				  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&its>;
+-			#interrupt-cells = <1>;
+-			interrupt-map-mask = <0 0 0 7>;
+-			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
+-					<0000 0 0 2 &gic 0 0 0 110 4>,
+-					<0000 0 0 3 &gic 0 0 0 111 4>,
+-					<0000 0 0 4 &gic 0 0 0 112 4>;
+-		};
+-
+-		pcie@3500000 {
+-			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
+-				     "snps,dw-pcie";
+-			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+-			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
+-			reg-names = "regs", "config";
+-			interrupts = <0 113 0x4>; /* Level high type */
+-			interrupt-names = "intr";
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			device_type = "pci";
+-			dma-coherent;
+-			num-lanes = <4>;
+-			bus-range = <0x0 0xff>;
+-			ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */
+-				  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&its>;
+-			#interrupt-cells = <1>;
+-			interrupt-map-mask = <0 0 0 7>;
+-			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
+-					<0000 0 0 2 &gic 0 0 0 115 4>,
+-					<0000 0 0 3 &gic 0 0 0 116 4>,
+-					<0000 0 0 4 &gic 0 0 0 117 4>;
+-		};
+-
+-		pcie@3600000 {
+-			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
+-				     "snps,dw-pcie";
+-			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+-			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
+-			reg-names = "regs", "config";
+-			interrupts = <0 118 0x4>; /* Level high type */
+-			interrupt-names = "intr";
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			device_type = "pci";
+-			dma-coherent;
+-			num-lanes = <8>;
+-			bus-range = <0x0 0xff>;
+-			ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */
+-				  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&its>;
+-			#interrupt-cells = <1>;
+-			interrupt-map-mask = <0 0 0 7>;
+-			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
+-					<0000 0 0 2 &gic 0 0 0 120 4>,
+-					<0000 0 0 3 &gic 0 0 0 121 4>,
+-					<0000 0 0 4 &gic 0 0 0 122 4>;
+-		};
+-
+-		pcie@3700000 {
+-			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
+-				     "snps,dw-pcie";
+-			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
+-			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
+-			reg-names = "regs", "config";
+-			interrupts = <0 123 0x4>; /* Level high type */
+-			interrupt-names = "intr";
+-			#address-cells = <3>;
+-			#size-cells = <2>;
+-			device_type = "pci";
+-			dma-coherent;
+-			num-lanes = <4>;
+-			bus-range = <0x0 0xff>;
+-			ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
+-				  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-			msi-parent = <&its>;
+-			#interrupt-cells = <1>;
+-			interrupt-map-mask = <0 0 0 7>;
+-			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
+-					<0000 0 0 2 &gic 0 0 0 125 4>,
+-					<0000 0 0 3 &gic 0 0 0 126 4>,
+-					<0000 0 0 4 &gic 0 0 0 127 4>;
+-		};
+-
+-		sata0: sata@3200000 {
+-			status = "disabled";
+-			compatible = "fsl,ls2080a-ahci";
+-			reg = <0x0 0x3200000 0x0 0x10000>;
+-			interrupts = <0 133 0x4>; /* Level high type */
+-			clocks = <&clockgen 4 3>;
+-			dma-coherent;
+-		};
+-
+-		sata1: sata@3210000 {
+-			status = "disabled";
+-			compatible = "fsl,ls2080a-ahci";
+-			reg = <0x0 0x3210000 0x0 0x10000>;
+-			interrupts = <0 136 0x4>; /* Level high type */
+-			clocks = <&clockgen 4 3>;
+-			dma-coherent;
+-		};
+-
+-		usb0: usb3@3100000 {
+-			status = "disabled";
+-			compatible = "snps,dwc3";
+-			reg = <0x0 0x3100000 0x0 0x10000>;
+-			interrupts = <0 80 0x4>; /* Level high type */
+-			dr_mode = "host";
+-			snps,quirk-frame-length-adjustment = <0x20>;
+-			snps,dis_rxdet_inp3_quirk;
+-		};
+-
+-		usb1: usb3@3110000 {
+-			status = "disabled";
+-			compatible = "snps,dwc3";
+-			reg = <0x0 0x3110000 0x0 0x10000>;
+-			interrupts = <0 81 0x4>; /* Level high type */
+-			dr_mode = "host";
+-			snps,quirk-frame-length-adjustment = <0x20>;
+-			snps,dis_rxdet_inp3_quirk;
+-		};
+-
+-		ccn@4000000 {
+-			compatible = "arm,ccn-504";
+-			reg = <0x0 0x04000000 0x0 0x01000000>;
+-			interrupts = <0 12 4>;
+-		};
+-	};
+-
+-	ddr1: memory-controller@1080000 {
+-		compatible = "fsl,qoriq-memory-controller";
+-		reg = <0x0 0x1080000 0x0 0x1000>;
+-		interrupts = <0 17 0x4>;
+-		little-endian;
+-	};
+-
+-	ddr2: memory-controller@1090000 {
+-		compatible = "fsl,qoriq-memory-controller";
+-		reg = <0x0 0x1090000 0x0 0x1000>;
+-		interrupts = <0 18 0x4>;
+-		little-endian;
++#include "fsl-ls208xa.dtsi"
++
++&cpu {
++	cpu0: cpu@0 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a57";
++		reg = <0x0>;
++		clocks = <&clockgen 1 0>;
++		next-level-cache = <&cluster0_l2>;
++		#cooling-cells = <2>;
++	};
++
++	cpu1: cpu@1 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a57";
++		reg = <0x1>;
++		clocks = <&clockgen 1 0>;
++		next-level-cache = <&cluster0_l2>;
++	};
++
++	cpu2: cpu@100 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a57";
++		reg = <0x100>;
++		clocks = <&clockgen 1 1>;
++		next-level-cache = <&cluster1_l2>;
++		#cooling-cells = <2>;
++	};
++
++	cpu3: cpu@101 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a57";
++		reg = <0x101>;
++		clocks = <&clockgen 1 1>;
++		next-level-cache = <&cluster1_l2>;
++	};
++
++	cpu4: cpu@200 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a57";
++		reg = <0x200>;
++		clocks = <&clockgen 1 2>;
++		next-level-cache = <&cluster2_l2>;
++		#cooling-cells = <2>;
++	};
++
++	cpu5: cpu@201 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a57";
++		reg = <0x201>;
++		clocks = <&clockgen 1 2>;
++		next-level-cache = <&cluster2_l2>;
++	};
++
++	cpu6: cpu@300 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a57";
++		reg = <0x300>;
++		clocks = <&clockgen 1 3>;
++		next-level-cache = <&cluster3_l2>;
++		#cooling-cells = <2>;
++	};
++
++	cpu7: cpu@301 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a57";
++		reg = <0x301>;
++		clocks = <&clockgen 1 3>;
++		next-level-cache = <&cluster3_l2>;
+ 	};
++
++	cluster0_l2: l2-cache0 {
++		compatible = "cache";
++	};
++
++	cluster1_l2: l2-cache1 {
++		compatible = "cache";
++	};
++
++	cluster2_l2: l2-cache2 {
++		compatible = "cache";
++	};
++
++	cluster3_l2: l2-cache3 {
++		compatible = "cache";
++	};
++};
++
++&usb0 {
++	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++	snps,dma-snooping;
++};
++
++&usb1 {
++	snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++	snps,dma-snooping;
++};
++
++&timer {
++	fsl,erratum-a008585;
++};
++
++&pcie1 {
++	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
++	       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
++
++	ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */
++		  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++};
++
++&pcie2 {
++	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
++	       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
++
++	ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */
++		  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++};
++
++&pcie3 {
++	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
++	       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
++
++	ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */
++		  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++};
++
++&pcie4 {
++	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
++	       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
++
++	ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
++		  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
+@@ -0,0 +1,161 @@
++/*
++ * Device Tree file for NXP LS2081A RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Priyanka Jain <priyanka.jain@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "fsl-ls2088a.dtsi"
++
++/ {
++	model = "NXP Layerscape 2081A RDB Board";
++	compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
++
++	aliases {
++		serial0 = &serial0;
++		serial1 = &serial1;
++	};
++
++	chosen {
++		stdout-path = "serial1:115200n8";
++	};
++};
++
++&esdhc {
++	status = "okay";
++};
++
++&ifc {
++	status = "disabled";
++};
++
++&i2c0 {
++	status = "okay";
++	pca9547@75 {
++		compatible = "nxp,pca9547";
++		reg = <0x75>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		i2c@1 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x01>;
++			rtc@51 {
++				compatible = "nxp,pcf2129";
++				reg = <0x51>;
++			};
++		};
++
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x02>;
++
++			ina220@40 {
++				compatible = "ti,ina220";
++				reg = <0x40>;
++				shunt-resistor = <500>;
++			};
++		};
++
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			adt7481@4c {
++				compatible = "adi,adt7461";
++				reg = <0x4c>;
++			};
++		};
++	};
++};
++
++&dspi {
++	status = "okay";
++	dflash0: n25q512a {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "st,m25p80";
++		spi-max-frequency = <3000000>;
++		reg = <0>;
++	};
++};
++
++&qspi {
++	status = "okay";
++	fsl,qspi-has-second-chip;
++	flash0: s25fs512s@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "spansion,m25p80";
++		m25p,fast-read;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++	flash1: s25fs512s@1 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "spansion,m25p80";
++		m25p,fast-read;
++		spi-max-frequency = <20000000>;
++		reg = <1>;
++	};
++};
++
++&sata0 {
++	status = "okay";
++};
++
++&sata1 {
++	status = "okay";
++};
++
++&usb0 {
++	status = "okay";
++};
++
++&usb1 {
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
+@@ -0,0 +1,126 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Freescale LS2088A QDS Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
++ *
++ */
++
++/dts-v1/;
++
++#include "fsl-ls2088a.dtsi"
++#include "fsl-ls208xa-qds.dtsi"
++
++/ {
++	model = "Freescale Layerscape 2088A QDS Board";
++	compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++};
++
++&ifc {
++	boardctrl: board-control@3,0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
++		reg = <3 0 0x300>;		/* TODO check address */
++		ranges = <0 3 0 0x300>;
++
++		mdio_mux_emi1 {
++			compatible = "mdio-mux-mmioreg", "mdio-mux";
++			mdio-parent-bus = <&emdio1>;
++			reg = <0x54 1>;		/* BRDCFG4 */
++			mux-mask = <0xe0>;	/* EMI1_MDIO */
++
++			#address-cells=<1>;
++			#size-cells = <0>;
++
++			/* Child MDIO buses, one for each riser card:
++			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
++			 * VSC8234 PHYs on the riser cards.
++			 */
++
++			mdio_mux3: mdio@60 {
++				reg = <0x60>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mdio0_phy12: mdio_phy0@1c {
++					reg = <0x1c>;
++					phy-connection-type = "sgmii";
++				};
++				mdio0_phy13: mdio_phy1@1d {
++					reg = <0x1d>;
++					phy-connection-type = "sgmii";
++				};
++				mdio0_phy14: mdio_phy2@1e {
++					reg = <0x1e>;
++					phy-connection-type = "sgmii";
++				};
++				mdio0_phy15: mdio_phy3@1f {
++					reg = <0x1f>;
++					phy-connection-type = "sgmii";
++				};
++			};
++		};
++	};
++};
++
++&pcs_mdio1 {
++		pcs_phy1: ethernet-phy@0 {
++		backplane-mode = "10gbase-kr";
++		compatible = "ethernet-phy-ieee802.3-c45";
++		reg = <0x0>;
++		fsl,lane-handle = <&serdes1>;
++		fsl,lane-reg = <0x9C0 0x40>;/* lane H */
++	};
++};
++
++&pcs_mdio2 {
++		pcs_phy2: ethernet-phy@0 {
++		backplane-mode = "10gbase-kr";
++		compatible = "ethernet-phy-ieee802.3-c45";
++		reg = <0x0>;
++		fsl,lane-handle = <&serdes1>;
++		fsl,lane-reg = <0x980 0x40>;/* lane G */
++	};
++};
++
++&pcs_mdio3 {
++		pcs_phy3: ethernet-phy@0 {
++		backplane-mode = "10gbase-kr";
++		compatible = "ethernet-phy-ieee802.3-c45";
++		reg = <0x0>;
++		fsl,lane-handle = <&serdes1>;
++		fsl,lane-reg = <0x940 0x40>;/* lane F */
++	};
++};
++
++&pcs_mdio4 {
++		pcs_phy4: ethernet-phy@0 {
++		backplane-mode = "10gbase-kr";
++		compatible = "ethernet-phy-ieee802.3-c45";
++		reg = <0x0>;
++		fsl,lane-handle = <&serdes1>;
++		fsl,lane-reg = <0x900 0x40>;/* lane E */
++	};
++};
++
++/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
++&dpmac9 {
++	phy-handle = <&mdio0_phy12>;
++};
++&dpmac10 {
++	phy-handle = <&mdio0_phy13>;
++};
++&dpmac11 {
++	phy-handle = <&mdio0_phy14>;
++};
++&dpmac12 {
++	phy-handle = <&mdio0_phy15>;
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
+@@ -0,0 +1,104 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Freescale LS2088A RDB Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
++ *
++ */
++
++/dts-v1/;
++
++#include "fsl-ls2088a.dtsi"
++#include "fsl-ls208xa-rdb.dtsi"
++
++/ {
++	model = "Freescale Layerscape 2088A RDB Board";
++	compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
++
++	chosen {
++		stdout-path = "serial1:115200n8";
++	};
++};
++
++&emdio1 {
++	status = "disabled";
++	/* CS4340 PHYs */
++	mdio1_phy1: emdio1_phy@1 {
++		reg = <0x10>;
++		phy-connection-type = "xfi";
++	};
++	mdio1_phy2: emdio1_phy@2 {
++		reg = <0x11>;
++		phy-connection-type = "xfi";
++	};
++	mdio1_phy3: emdio1_phy@3 {
++		reg = <0x12>;
++		phy-connection-type = "xfi";
++	};
++	mdio1_phy4: emdio1_phy@4 {
++		reg = <0x13>;
++		phy-connection-type = "xfi";
++	};
++};
++
++&emdio2 {
++	/* AQR405 PHYs */
++	mdio2_phy1: emdio2_phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 1 0x4>; /* Level high type */
++		reg = <0x0>;
++		phy-connection-type = "xfi";
++	};
++	mdio2_phy2: emdio2_phy@2 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 2 0x4>; /* Level high type */
++		reg = <0x1>;
++		phy-connection-type = "xfi";
++	};
++	mdio2_phy3: emdio2_phy@3 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 4 0x4>; /* Level high type */
++		reg = <0x2>;
++		phy-connection-type = "xfi";
++	};
++	mdio2_phy4: emdio2_phy@4 {
++		compatible = "ethernet-phy-ieee802.3-c45";
++		interrupts = <0 5 0x4>; /* Level high type */
++		reg = <0x3>;
++		phy-connection-type = "xfi";
++	};
++};
++
++/* Update DPMAC connections to external PHYs, under the assumption of
++ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
++ */
++/* Leave Cortina PHYs commented out until proper driver is integrated
++ *&dpmac1 {
++ *	phy-handle = <&mdio1_phy1>;
++ *};
++ *&dpmac2 {
++ *	phy-handle = <&mdio1_phy2>;
++ *};
++ *&dpmac3 {
++ *	phy-handle = <&mdio1_phy3>;
++ *};
++ *&dpmac4 {
++ *	phy-handle = <&mdio1_phy4>;
++ *};
++ */
++
++&dpmac5 {
++	phy-handle = <&mdio2_phy1>;
++};
++&dpmac6 {
++	phy-handle = <&mdio2_phy2>;
++};
++&dpmac7 {
++	phy-handle = <&mdio2_phy3>;
++};
++&dpmac8 {
++	phy-handle = <&mdio2_phy4>;
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+@@ -0,0 +1,159 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for Freescale Layerscape-2088A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
++ *
++ */
++
++#include "fsl-ls208xa.dtsi"
++
++&cpu {
++	cpu0: cpu@0 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a72";
++		reg = <0x0>;
++		clocks = <&clockgen 1 0>;
++		next-level-cache = <&cluster0_l2>;
++		#cooling-cells = <2>;
++		cpu-idle-states = <&CPU_PH20>;
++	};
++
++	cpu1: cpu@1 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a72";
++		reg = <0x1>;
++		clocks = <&clockgen 1 0>;
++		next-level-cache = <&cluster0_l2>;
++		cpu-idle-states = <&CPU_PH20>;
++	};
++
++	cpu2: cpu@100 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a72";
++		reg = <0x100>;
++		clocks = <&clockgen 1 1>;
++		next-level-cache = <&cluster1_l2>;
++		#cooling-cells = <2>;
++		cpu-idle-states = <&CPU_PH20>;
++	};
++
++	cpu3: cpu@101 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a72";
++		reg = <0x101>;
++		clocks = <&clockgen 1 1>;
++		next-level-cache = <&cluster1_l2>;
++		cpu-idle-states = <&CPU_PH20>;
++	};
++
++	cpu4: cpu@200 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a72";
++		reg = <0x200>;
++		clocks = <&clockgen 1 2>;
++		next-level-cache = <&cluster2_l2>;
++		#cooling-cells = <2>;
++		cpu-idle-states = <&CPU_PH20>;
++	};
++
++	cpu5: cpu@201 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a72";
++		reg = <0x201>;
++		clocks = <&clockgen 1 2>;
++		next-level-cache = <&cluster2_l2>;
++		cpu-idle-states = <&CPU_PH20>;
++	};
++
++	cpu6: cpu@300 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a72";
++		reg = <0x300>;
++		clocks = <&clockgen 1 3>;
++		next-level-cache = <&cluster3_l2>;
++		#cooling-cells = <2>;
++		cpu-idle-states = <&CPU_PH20>;
++	};
++
++	cpu7: cpu@301 {
++		device_type = "cpu";
++		compatible = "arm,cortex-a72";
++		reg = <0x301>;
++		clocks = <&clockgen 1 3>;
++		next-level-cache = <&cluster3_l2>;
++		cpu-idle-states = <&CPU_PH20>;
++	};
++
++	idle-states {
++		/*
++		 * PSCI node is not added default, U-boot will add missing
++		 * parts if it determines to use PSCI.
++		 */
++		entry-method = "arm,psci";
++
++		CPU_PH20: cpu-ph20 {
++			compatible = "arm,idle-state";
++			idle-state-name = "PH20";
++			arm,psci-suspend-param = <0x0>;
++			entry-latency-us = <1000>;
++			exit-latency-us = <1000>;
++			min-residency-us = <3000>;
++		};
++	};
++
++	cluster0_l2: l2-cache0 {
++		compatible = "cache";
++	};
++
++	cluster1_l2: l2-cache1 {
++		compatible = "cache";
++	};
++
++	cluster2_l2: l2-cache2 {
++		compatible = "cache";
++	};
++
++	cluster3_l2: l2-cache3 {
++		compatible = "cache";
++	};
++};
++
++&pcie1 {
++	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
++	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
++	       0x20 0x00000000 0x0 0x00002000>; /* configuration space */
++
++	ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
++		  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
++};
++
++&pcie2 {
++	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
++	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
++	       0x28 0x00000000 0x0 0x00002000>; /* configuration space */
++
++	ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
++		  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
++};
++
++&pcie3 {
++	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
++	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
++	       0x30 0x00000000 0x0 0x00002000>; /* configuration space */
++
++	ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
++		  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
++};
++
++&pcie4 {
++	compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
++	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
++	       0x38 0x00000000 0x0 0x00002000>; /* configuration space */
++
++	ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
++		  0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+@@ -0,0 +1,162 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Freescale LS2080A QDS Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
++ *
++ */
++
++&esdhc {
++	mmc-hs200-1_8v;
++	status = "okay";
++};
++
++&ifc {
++	status = "okay";
++	#address-cells = <2>;
++	#size-cells = <1>;
++	ranges = <0x0 0x0 0x5 0x80000000 0x08000000
++		  0x2 0x0 0x5 0x30000000 0x00010000
++		  0x3 0x0 0x5 0x20000000 0x00010000>;
++
++	nor@0,0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "cfi-flash";
++		reg = <0x0 0x0 0x8000000>;
++		bank-width = <2>;
++		device-width = <1>;
++	};
++
++	nand@2,0 {
++	     compatible = "fsl,ifc-nand";
++	     reg = <0x2 0x0 0x10000>;
++	};
++
++	cpld@3,0 {
++	     reg = <0x3 0x0 0x10000>;
++	     compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
++	};
++};
++
++&i2c0 {
++	status = "okay";
++	pca9547@77 {
++		compatible = "nxp,pca9547";
++		reg = <0x77>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		i2c@0 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x00>;
++			rtc@68 {
++				compatible = "dallas,ds3232";
++				reg = <0x68>;
++			};
++		};
++
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x02>;
++
++			ina220@40 {
++				compatible = "ti,ina220";
++				reg = <0x40>;
++				shunt-resistor = <500>;
++			};
++
++			ina220@41 {
++				compatible = "ti,ina220";
++				reg = <0x41>;
++				shunt-resistor = <1000>;
++			};
++		};
++
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			adt7481@4c {
++				compatible = "adi,adt7461";
++				reg = <0x4c>;
++			};
++		};
++	};
++};
++
++&i2c1 {
++	status = "disabled";
++};
++
++&i2c2 {
++	status = "disabled";
++};
++
++&i2c3 {
++	status = "disabled";
++};
++
++&dspi {
++	status = "okay";
++	dflash0: n25q128a {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "st,m25p80";
++		spi-max-frequency = <3000000>;
++		reg = <0>;
++	};
++	dflash1: sst25wf040b {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "st,m25p80";
++		spi-max-frequency = <3000000>;
++		reg = <1>;
++	};
++	dflash2: en25s64 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "st,m25p80";
++		spi-max-frequency = <3000000>;
++		reg = <2>;
++	};
++};
++
++&qspi {
++	status = "okay";
++	flash0: s25fl256s1@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "st,m25p80";
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++	flash2: s25fl256s1@2 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "st,m25p80";
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++};
++
++&sata0 {
++	status = "okay";
++};
++
++&sata1 {
++	status = "okay";
++};
++
++&usb0 {
++	status = "okay";
++};
++
++&usb1 {
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+@@ -0,0 +1,136 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree file for Freescale LS2080A RDB Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
++ *
++ */
++
++&esdhc {
++	status = "okay";
++};
++
++&ifc {
++	status = "okay";
++	#address-cells = <2>;
++	#size-cells = <1>;
++	ranges = <0x0 0x0 0x5 0x80000000 0x08000000
++		  0x2 0x0 0x5 0x30000000 0x00010000
++		  0x3 0x0 0x5 0x20000000 0x00010000>;
++
++	nor@0,0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "cfi-flash";
++		reg = <0x0 0x0 0x8000000>;
++		bank-width = <2>;
++		device-width = <1>;
++	};
++
++	nand@2,0 {
++	     compatible = "fsl,ifc-nand";
++	     reg = <0x2 0x0 0x10000>;
++	};
++
++	cpld@3,0 {
++	     reg = <0x3 0x0 0x10000>;
++	     compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
++	};
++
++};
++
++&i2c0 {
++	status = "okay";
++	pca9547@75 {
++		compatible = "nxp,pca9547";
++		reg = <0x75>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		i2c-mux-never-disable;
++		i2c@1 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x01>;
++			rtc@68 {
++				compatible = "dallas,ds3232";
++				reg = <0x68>;
++			};
++		};
++
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x02>;
++			ina220@40 {
++				compatible = "ti,ina220";
++				reg = <0x40>;
++				shunt-resistor = <500>;
++			};
++		};
++
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			adt7481@4c {
++				compatible = "adi,adt7461";
++				reg = <0x4c>;
++			};
++		};
++	};
++};
++
++&i2c1 {
++	status = "disabled";
++};
++
++&i2c2 {
++	status = "disabled";
++};
++
++&i2c3 {
++	status = "disabled";
++};
++
++&dspi {
++	status = "okay";
++	dflash0: n25q512a {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "st,m25p80";
++		spi-max-frequency = <3000000>;
++		reg = <0>;
++	};
++};
++
++&qspi {
++	status = "okay";
++	flash0: s25fs512s@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "spansion,m25p80";
++		m25p,fast-read;
++		spi-max-frequency = <20000000>;
++		reg = <0>;
++	};
++};
++
++&sata0 {
++	status = "okay";
++};
++
++&sata1 {
++	status = "okay";
++};
++
++&usb0 {
++	status = "okay";
++};
++
++&usb1 {
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+@@ -0,0 +1,885 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Device Tree Include file for Freescale Layerscape-2080A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
++ *
++ */
++
++#include <dt-bindings/thermal/thermal.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++/ {
++	compatible = "fsl,ls2080a";
++	interrupt-parent = <&gic>;
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	aliases {
++		crypto = &crypto;
++		serial0 = &serial0;
++		serial1 = &serial1;
++	};
++
++	cpu: cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
++	memory@80000000 {
++		device_type = "memory";
++		reg = <0x00000000 0x80000000 0 0x80000000>;
++		      /* DRAM space - 1, size : 2 GB DRAM */
++	};
++
++	sysclk: sysclk {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <100000000>;
++		clock-output-names = "sysclk";
++	};
++
++	gic: interrupt-controller@6000000 {
++		compatible = "arm,gic-v3";
++		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
++			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
++			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
++			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
++			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
++		#interrupt-cells = <3>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		interrupt-controller;
++		interrupts = <1 9 0x4>;
++
++		its: gic-its@6020000 {
++			compatible = "arm,gic-v3-its";
++			msi-controller;
++			reg = <0x0 0x6020000 0 0x20000>;
++		};
++	};
++
++	rstcr: syscon@1e60000 {
++		compatible = "fsl,ls2080a-rstcr", "syscon";
++		reg = <0x0 0x1e60000 0x0 0x4>;
++	};
++
++	reboot {
++		compatible ="syscon-reboot";
++		regmap = <&rstcr>;
++		offset = <0x0>;
++		mask = <0x2>;
++	};
++
++	timer: timer {
++		compatible = "arm,armv8-timer";
++		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
++			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
++			     <1 11 4>, /* Virtual PPI, active-low */
++			     <1 10 4>; /* Hypervisor PPI, active-low */
++	};
++
++	pmu {
++		compatible = "arm,armv8-pmuv3";
++		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
++	};
++
++	soc {
++		compatible = "simple-bus";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
++
++		clockgen: clocking@1300000 {
++			compatible = "fsl,ls2080a-clockgen";
++			reg = <0 0x1300000 0 0xa0000>;
++			#clock-cells = <2>;
++			clocks = <&sysclk>;
++		};
++
++		dcfg: dcfg@1e00000 {
++			compatible = "fsl,ls2080a-dcfg", "syscon";
++			reg = <0x0 0x1e00000 0x0 0x10000>;
++			little-endian;
++		};
++
++		tmu: tmu@1f80000 {
++			compatible = "fsl,qoriq-tmu";
++			reg = <0x0 0x1f80000 0x0 0x10000>;
++			interrupts = <0 23 0x4>;
++			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++			fsl,tmu-calibration = <0x00000000 0x00000026
++					       0x00000001 0x0000002d
++					       0x00000002 0x00000032
++					       0x00000003 0x00000039
++					       0x00000004 0x0000003f
++					       0x00000005 0x00000046
++					       0x00000006 0x0000004d
++					       0x00000007 0x00000054
++					       0x00000008 0x0000005a
++					       0x00000009 0x00000061
++					       0x0000000a 0x0000006a
++					       0x0000000b 0x00000071
++
++					       0x00010000 0x00000025
++					       0x00010001 0x0000002c
++					       0x00010002 0x00000035
++					       0x00010003 0x0000003d
++					       0x00010004 0x00000045
++					       0x00010005 0x0000004e
++					       0x00010006 0x00000057
++					       0x00010007 0x00000061
++					       0x00010008 0x0000006b
++					       0x00010009 0x00000076
++
++					       0x00020000 0x00000029
++					       0x00020001 0x00000033
++					       0x00020002 0x0000003d
++					       0x00020003 0x00000049
++					       0x00020004 0x00000056
++					       0x00020005 0x00000061
++					       0x00020006 0x0000006d
++
++					       0x00030000 0x00000021
++					       0x00030001 0x0000002a
++					       0x00030002 0x0000003c
++					       0x00030003 0x0000004e>;
++			little-endian;
++			#thermal-sensor-cells = <1>;
++		};
++
++		thermal-zones {
++			cpu_thermal: cpu-thermal {
++				polling-delay-passive = <1000>;
++				polling-delay = <5000>;
++
++				thermal-sensors = <&tmu 4>;
++
++				trips {
++					cpu_alert: cpu-alert {
++						temperature = <75000>;
++						hysteresis = <2000>;
++						type = "passive";
++					};
++					cpu_crit: cpu-crit {
++						temperature = <85000>;
++						hysteresis = <2000>;
++						type = "critical";
++					};
++				};
++
++				cooling-maps {
++					map0 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu0 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++					map1 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu2 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++					map2 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu4 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++					map3 {
++						trip = <&cpu_alert>;
++						cooling-device =
++							<&cpu6 THERMAL_NO_LIMIT
++							THERMAL_NO_LIMIT>;
++					};
++				};
++			};
++		};
++
++		serial0: serial@21c0500 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21c0500 0x0 0x100>;
++			clocks = <&clockgen 4 3>;
++			interrupts = <0 32 0x4>; /* Level high type */
++		};
++
++		serial1: serial@21c0600 {
++			compatible = "fsl,ns16550", "ns16550a";
++			reg = <0x0 0x21c0600 0x0 0x100>;
++			clocks = <&clockgen 4 3>;
++			interrupts = <0 32 0x4>; /* Level high type */
++		};
++
++		cluster1_core0_watchdog: wdt@c000000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc000000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster1_core1_watchdog: wdt@c010000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc010000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster2_core0_watchdog: wdt@c100000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc100000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster2_core1_watchdog: wdt@c110000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc110000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster3_core0_watchdog: wdt@c200000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc200000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster3_core1_watchdog: wdt@c210000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc210000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster4_core0_watchdog: wdt@c300000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc300000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		cluster4_core1_watchdog: wdt@c310000 {
++			compatible = "arm,sp805-wdt", "arm,primecell";
++			reg = <0x0 0xc310000 0x0 0x1000>;
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "apb_pclk", "wdog_clk";
++		};
++
++		crypto: crypto@8000000 {
++			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
++			fsl,sec-era = <8>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0x0 0x00 0x8000000 0x100000>;
++			reg = <0x00 0x8000000 0x0 0x100000>;
++			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
++			dma-coherent;
++
++			sec_jr0: jr@10000 {
++				compatible = "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x10000 0x10000>;
++				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr1: jr@20000 {
++				compatible = "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x20000 0x10000>;
++				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr2: jr@30000 {
++				compatible = "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x30000 0x10000>;
++				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
++			};
++
++			sec_jr3: jr@40000 {
++				compatible = "fsl,sec-v5.0-job-ring",
++					     "fsl,sec-v4.0-job-ring";
++				reg	   = <0x40000 0x10000>;
++				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++			};
++		};
++
++		fsl_mc: fsl-mc@80c000000 {
++			compatible = "fsl,qoriq-mc";
++			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
++			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
++			dma-coherent;
++			#address-cells = <3>;
++			#size-cells = <1>;
++
++			/*
++			 * Region type 0x0 - MC portals
++			 * Region type 0x1 - QBMAN portals
++			 */
++			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
++				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
++
++			/*
++			 * Define the maximum number of MACs present on the SoC.
++			 */
++			dpmacs {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				dpmac1: dpmac@1 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x1>;
++				};
++
++				dpmac2: dpmac@2 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x2>;
++				};
++
++				dpmac3: dpmac@3 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x3>;
++				};
++
++				dpmac4: dpmac@4 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x4>;
++				};
++
++				dpmac5: dpmac@5 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x5>;
++				};
++
++				dpmac6: dpmac@6 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x6>;
++				};
++
++				dpmac7: dpmac@7 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x7>;
++				};
++
++				dpmac8: dpmac@8 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x8>;
++				};
++
++				dpmac9: dpmac@9 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x9>;
++				};
++
++				dpmac10: dpmac@a {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0xa>;
++				};
++
++				dpmac11: dpmac@b {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0xb>;
++				};
++
++				dpmac12: dpmac@c {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0xc>;
++				};
++
++				dpmac13: dpmac@d {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0xd>;
++				};
++
++				dpmac14: dpmac@e {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0xe>;
++				};
++
++				dpmac15: dpmac@f {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0xf>;
++				};
++
++				dpmac16: dpmac@10 {
++					compatible = "fsl,qoriq-mc-dpmac";
++					reg = <0x10>;
++				};
++			};
++		};
++
++		smmu: iommu@5000000 {
++			compatible = "arm,mmu-500";
++			reg = <0 0x5000000 0 0x800000>;
++			#global-interrupts = <12>;
++			#iommu-cells = <1>;
++			stream-match-mask = <0x7C00>;
++			interrupts = <0 13 4>, /* global secure fault */
++				     <0 14 4>, /* combined secure interrupt */
++				     <0 15 4>, /* global non-secure fault */
++				     <0 16 4>, /* combined non-secure interrupt */
++				/* performance counter interrupts 0-7 */
++				     <0 211 4>, <0 212 4>,
++				     <0 213 4>, <0 214 4>,
++				     <0 215 4>, <0 216 4>,
++				     <0 217 4>, <0 218 4>,
++				/* per context interrupt, 64 interrupts */
++				     <0 146 4>, <0 147 4>,
++				     <0 148 4>, <0 149 4>,
++				     <0 150 4>, <0 151 4>,
++				     <0 152 4>, <0 153 4>,
++				     <0 154 4>, <0 155 4>,
++				     <0 156 4>, <0 157 4>,
++				     <0 158 4>, <0 159 4>,
++				     <0 160 4>, <0 161 4>,
++				     <0 162 4>, <0 163 4>,
++				     <0 164 4>, <0 165 4>,
++				     <0 166 4>, <0 167 4>,
++				     <0 168 4>, <0 169 4>,
++				     <0 170 4>, <0 171 4>,
++				     <0 172 4>, <0 173 4>,
++				     <0 174 4>, <0 175 4>,
++				     <0 176 4>, <0 177 4>,
++				     <0 178 4>, <0 179 4>,
++				     <0 180 4>, <0 181 4>,
++				     <0 182 4>, <0 183 4>,
++				     <0 184 4>, <0 185 4>,
++				     <0 186 4>, <0 187 4>,
++				     <0 188 4>, <0 189 4>,
++				     <0 190 4>, <0 191 4>,
++				     <0 192 4>, <0 193 4>,
++				     <0 194 4>, <0 195 4>,
++				     <0 196 4>, <0 197 4>,
++				     <0 198 4>, <0 199 4>,
++				     <0 200 4>, <0 201 4>,
++				     <0 202 4>, <0 203 4>,
++				     <0 204 4>, <0 205 4>,
++				     <0 206 4>, <0 207 4>,
++				     <0 208 4>, <0 209 4>;
++		};
++
++		dspi: dspi@2100000 {
++			status = "disabled";
++			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2100000 0x0 0x10000>;
++			interrupts = <0 26 0x4>; /* Level high type */
++			clocks = <&clockgen 4 3>;
++			clock-names = "dspi";
++			spi-num-chipselects = <5>;
++			bus-num = <0>;
++		};
++
++		esdhc: esdhc@2140000 {
++			status = "disabled";
++			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
++			reg = <0x0 0x2140000 0x0 0x10000>;
++			interrupts = <0 28 0x4>; /* Level high type */
++			clocks = <&clockgen 4 1>;
++			voltage-ranges = <1800 1800 3300 3300>;
++			sdhci,auto-cmd12;
++			little-endian;
++			bus-width = <4>;
++		};
++
++		gpio0: gpio@2300000 {
++			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
++			reg = <0x0 0x2300000 0x0 0x10000>;
++			interrupts = <0 36 0x4>; /* Level high type */
++			gpio-controller;
++			little-endian;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio1: gpio@2310000 {
++			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
++			reg = <0x0 0x2310000 0x0 0x10000>;
++			interrupts = <0 36 0x4>; /* Level high type */
++			gpio-controller;
++			little-endian;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio2: gpio@2320000 {
++			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
++			reg = <0x0 0x2320000 0x0 0x10000>;
++			interrupts = <0 37 0x4>; /* Level high type */
++			gpio-controller;
++			little-endian;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		gpio3: gpio@2330000 {
++			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
++			reg = <0x0 0x2330000 0x0 0x10000>;
++			interrupts = <0 37 0x4>; /* Level high type */
++			gpio-controller;
++			little-endian;
++			#gpio-cells = <2>;
++			interrupt-controller;
++			#interrupt-cells = <2>;
++		};
++
++		/* TODO: WRIOP (CCSR?) */
++		emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
++					  * E-MDIO1: 0x1_6000
++					  */
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8B96000 0x0 0x1000>;
++			device_type = "mdio";	/* TODO: is this necessary? */
++			little-endian;	/* force the driver in LE mode */
++
++			/* Not necessary on the QDS, but needed on the RDB */
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
++					  * E-MDIO2: 0x1_7000
++					  */
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8B97000 0x0 0x1000>;
++			device_type = "mdio";	/* TODO: is this necessary? */
++			little-endian;	/* force the driver in LE mode */
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		pcs_mdio1: mdio@0x8c07000 {
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8c07000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		pcs_mdio2: mdio@0x8c0b000 {
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8c0b000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		pcs_mdio3: mdio@0x8c0f000 {
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8c0f000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		pcs_mdio4: mdio@0x8c13000 {
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8c13000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		pcs_mdio5: mdio@0x8c17000 {
++			status = "disabled";
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8c17000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		pcs_mdio6: mdio@0x8c1b000 {
++			status = "disabled";
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8c1b000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		pcs_mdio7: mdio@0x8c1f000 {
++			status = "disabled";
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8c1f000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		pcs_mdio8: mdio@0x8c23000 {
++			status = "disabled";
++			compatible = "fsl,fman-memac-mdio";
++			reg = <0x0 0x8c23000 0x0 0x1000>;
++			device_type = "mdio";
++			little-endian;
++
++			#address-cells = <1>;
++			#size-cells = <0>;
++		};
++
++		i2c0: i2c@2000000 {
++			status = "disabled";
++			compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2000000 0x0 0x10000>;
++			interrupts = <0 34 0x4>; /* Level high type */
++			clock-names = "i2c";
++			clocks = <&clockgen 4 1>;
++			fsl-scl-gpio = <&gpio3 10 0>;
++		};
++
++		i2c1: i2c@2010000 {
++			status = "disabled";
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2010000 0x0 0x10000>;
++			interrupts = <0 34 0x4>; /* Level high type */
++			clock-names = "i2c";
++			clocks = <&clockgen 4 1>;
++		};
++
++		i2c2: i2c@2020000 {
++			status = "disabled";
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2020000 0x0 0x10000>;
++			interrupts = <0 35 0x4>; /* Level high type */
++			clock-names = "i2c";
++			clocks = <&clockgen 4 1>;
++		};
++
++		i2c3: i2c@2030000 {
++			status = "disabled";
++			compatible = "fsl,vf610-i2c";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x2030000 0x0 0x10000>;
++			interrupts = <0 35 0x4>; /* Level high type */
++			clock-names = "i2c";
++			clocks = <&clockgen 4 1>;
++		};
++
++		ifc: ifc@2240000 {
++			compatible = "fsl,ifc", "simple-bus";
++			reg = <0x0 0x2240000 0x0 0x20000>;
++			interrupts = <0 21 0x4>; /* Level high type */
++			little-endian;
++			#address-cells = <2>;
++			#size-cells = <1>;
++
++			ranges = <0 0 0x5 0x80000000 0x08000000
++				  2 0 0x5 0x30000000 0x00010000
++				  3 0 0x5 0x20000000 0x00010000>;
++		};
++
++		qspi: quadspi@20c0000 {
++			status = "disabled";
++			compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0x20c0000 0x0 0x10000>,
++			      <0x0 0x20000000 0x0 0x10000000>;
++			reg-names = "QuadSPI", "QuadSPI-memory";
++			interrupts = <0 25 0x4>; /* Level high type */
++			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
++			clock-names = "qspi_en", "qspi";
++		};
++
++		pcie1: pcie@3400000 {
++			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
++				     "snps,dw-pcie";
++			reg-names = "regs", "config";
++			interrupts = <0 108 0x4>; /* aer interrupt */
++			interrupt-names = "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
++					<0000 0 0 2 &gic 0 0 0 110 4>,
++					<0000 0 0 3 &gic 0 0 0 111 4>,
++					<0000 0 0 4 &gic 0 0 0 112 4>;
++		};
++
++		pcie2: pcie@3500000 {
++			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
++				     "snps,dw-pcie";
++			reg-names = "regs", "config";
++			interrupts = <0 113 0x4>; /* aer interrupt */
++			interrupt-names = "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
++					<0000 0 0 2 &gic 0 0 0 115 4>,
++					<0000 0 0 3 &gic 0 0 0 116 4>,
++					<0000 0 0 4 &gic 0 0 0 117 4>;
++		};
++
++		pcie3: pcie@3600000 {
++			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
++				     "snps,dw-pcie";
++			reg-names = "regs", "config";
++			interrupts = <0 118 0x4>; /* aer interrupt */
++			interrupt-names = "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <8>;
++			bus-range = <0x0 0xff>;
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
++					<0000 0 0 2 &gic 0 0 0 120 4>,
++					<0000 0 0 3 &gic 0 0 0 121 4>,
++					<0000 0 0 4 &gic 0 0 0 122 4>;
++		};
++
++		pcie4: pcie@3700000 {
++			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
++				     "snps,dw-pcie";
++			reg-names = "regs", "config";
++			interrupts = <0 123 0x4>; /* aer interrupt */
++			interrupt-names = "aer";
++			#address-cells = <3>;
++			#size-cells = <2>;
++			device_type = "pci";
++			dma-coherent;
++			num-lanes = <4>;
++			bus-range = <0x0 0xff>;
++			msi-parent = <&its>;
++			iommu-map = <0 &smmu 0 1>;	/* This is fixed-up by u-boot */
++			#interrupt-cells = <1>;
++			interrupt-map-mask = <0 0 0 7>;
++			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
++					<0000 0 0 2 &gic 0 0 0 125 4>,
++					<0000 0 0 3 &gic 0 0 0 126 4>,
++					<0000 0 0 4 &gic 0 0 0 127 4>;
++		};
++
++		sata0: sata@3200000 {
++			status = "disabled";
++			compatible = "fsl,ls2080a-ahci";
++			reg = <0x0 0x3200000 0x0 0x10000>;
++			interrupts = <0 133 0x4>; /* Level high type */
++			clocks = <&clockgen 4 3>;
++			dma-coherent;
++		};
++
++		sata1: sata@3210000 {
++			status = "disabled";
++			compatible = "fsl,ls2080a-ahci";
++			reg = <0x0 0x3210000 0x0 0x10000>;
++			interrupts = <0 136 0x4>; /* Level high type */
++			clocks = <&clockgen 4 3>;
++			dma-coherent;
++		};
++
++		usb0: usb3@3100000 {
++			status = "disabled";
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3100000 0x0 0x10000>;
++			interrupts = <0 80 0x4>; /* Level high type */
++			dr_mode = "host";
++			snps,quirk-frame-length-adjustment = <0x20>;
++			snps,dis_rxdet_inp3_quirk;
++		};
++
++		usb1: usb3@3110000 {
++			status = "disabled";
++			compatible = "snps,dwc3";
++			reg = <0x0 0x3110000 0x0 0x10000>;
++			interrupts = <0 81 0x4>; /* Level high type */
++			dr_mode = "host";
++			snps,quirk-frame-length-adjustment = <0x20>;
++			snps,dis_rxdet_inp3_quirk;
++		};
++
++		serdes1: serdes@1ea0000 {
++				reg = <0x0 0x1ea0000 0 0x00002000>;
++		};
++
++		ccn@4000000 {
++			compatible = "arm,ccn-504";
++			reg = <0x0 0x04000000 0x0 0x01000000>;
++			interrupts = <0 12 4>;
++		};
++
++		ftm0: ftm0@2800000 {
++			compatible = "fsl,ls208xa-ftm";
++			reg = <0x0 0x2800000 0x0 0x10000>,
++			      <0x0 0x1e34050 0x0 0x4>;
++			interrupts = <0 44 4>;
++			reg-names = "ftm", "FlexTimer1";
++		};
++	};
++
++	ddr1: memory-controller@1080000 {
++		compatible = "fsl,qoriq-memory-controller";
++		reg = <0x0 0x1080000 0x0 0x1000>;
++		interrupts = <0 17 0x4>;
++		little-endian;
++	};
++
++	ddr2: memory-controller@1090000 {
++		compatible = "fsl,qoriq-memory-controller";
++		reg = <0x0 0x1090000 0x0 0x1000>;
++		interrupts = <0 18 0x4>;
++		little-endian;
++	};
++
++	firmware {
++		optee {
++			compatible = "linaro,optee-tz";
++			method = "smc";
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi
+@@ -0,0 +1,55 @@
++/*
++ * QorIQ BMan SDK Portals device tree nodes
++ *
++ * Copyright 2011-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++ */
++
++&bportals {
++	bman-portal@0 {
++		cell-index = <0>;
++	};
++
++	bman-portal@10000 {
++		cell-index = <1>;
++	};
++
++	bman-portal@20000 {
++		cell-index = <2>;
++	};
++
++	bman-portal@30000 {
++		cell-index = <3>;
++	};
++
++	bman-portal@40000 {
++		cell-index = <4>;
++	};
++
++	bman-portal@50000 {
++		cell-index = <5>;
++	};
++
++	bman-portal@60000 {
++		cell-index = <6>;
++	};
++
++	bman-portal@70000 {
++		cell-index = <7>;
++	};
++
++	bman-portal@80000 {
++		cell-index = <8>;
++	};
++
++	bman-portal@90000 {
++		cell-index = <9>;
++	};
++
++	 bman-bpids@0 {
++		compatible = "fsl,bpid-range";
++		fsl,bpid-range = <32 32>;
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
+@@ -0,0 +1,77 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ BMan Portals device tree
++ *
++ * Copyright 2011-2016 Freescale Semiconductor Inc.
++ *
++ */
++
++&bportals {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	compatible = "simple-bus";
++
++	bman-portal@0 {
++		/*
++		 * bootloader fix-ups are expected to provide the
++		 * "fsl,bman-portal-<hardware revision>" compatible
++		 */
++		compatible = "fsl,bman-portal";
++		reg = <0x0 0x4000>, <0x4000000 0x4000>;
++		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@10000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x10000 0x4000>, <0x4010000 0x4000>;
++		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@20000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x20000 0x4000>, <0x4020000 0x4000>;
++		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@30000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x30000 0x4000>, <0x4030000 0x4000>;
++		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@40000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x40000 0x4000>, <0x4040000 0x4000>;
++		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@50000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x50000 0x4000>, <0x4050000 0x4000>;
++		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@60000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x60000 0x4000>, <0x4060000 0x4000>;
++		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@70000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x70000 0x4000>, <0x4070000 0x4000>;
++		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@80000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x80000 0x4000>, <0x4080000 0x4000>;
++		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++	};
++
++	bman-portal@90000 {
++		compatible = "fsl,bman-portal";
++		reg = <0x90000 0x4000>, <0x4090000 0x4000>;
++		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
+@@ -0,0 +1,73 @@
++/*
++ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
++ *
++ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++fsldpaa: fsl,dpaa {
++	compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
++	ethernet@0 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet0>;
++		dma-coherent;
++	};
++	ethernet@1 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet1>;
++		dma-coherent;
++	};
++	ethernet@2 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet2>;
++		dma-coherent;
++	};
++	ethernet@3 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet3>;
++		dma-coherent;
++	};
++	ethernet@4 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet4>;
++		dma-coherent;
++	};
++	ethernet@5 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet5>;
++		dma-coherent;
++	};
++	ethernet@8 {
++		compatible = "fsl,dpa-ethernet";
++		fsl,fman-mac = <&enet6>;
++		dma-coherent;
++	};
++};
++
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
+@@ -0,0 +1,43 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 10g port #0 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman@1a00000 {
++	fman0_rx_0x10: port@90000 {
++		cell-index = <0x10>;
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
++		reg = <0x90000 0x1000>;
++		fsl,fman-10g-port;
++	};
++
++	fman0_tx_0x30: port@b0000 {
++		cell-index = <0x30>;
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
++		reg = <0xb0000 0x1000>;
++		fsl,fman-10g-port;
++		fsl,qman-channel-id = <0x800>;
++	};
++
++	ethernet@f0000 {
++		cell-index = <0x8>;
++		compatible = "fsl,fman-memac";
++		reg = <0xf0000 0x1000>;
++		fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
++		pcsphy-handle = <&pcsphy6>;
++	};
++
++	mdio@f1000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xf1000 0x1000>;
++
++		pcsphy6: ethernet-phy@0 {
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
+@@ -0,0 +1,43 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 10g port #1 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman@1a00000 {
++	fman0_rx_0x11: port@91000 {
++		cell-index = <0x11>;
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
++		reg = <0x91000 0x1000>;
++		fsl,fman-10g-port;
++	};
++
++	fman0_tx_0x31: port@b1000 {
++		cell-index = <0x31>;
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
++		reg = <0xb1000 0x1000>;
++		fsl,fman-10g-port;
++		fsl,qman-channel-id = <0x801>;
++	};
++
++	ethernet@f2000 {
++		cell-index = <0x9>;
++		compatible = "fsl,fman-memac";
++		reg = <0xf2000 0x1000>;
++		fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
++		pcsphy-handle = <&pcsphy7>;
++	};
++
++	mdio@f3000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xf3000 0x1000>;
++
++		pcsphy7: ethernet-phy@0 {
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
+@@ -0,0 +1,42 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 1g port #0 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman@1a00000 {
++	fman0_rx_0x08: port@88000 {
++		cell-index = <0x8>;
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
++		reg = <0x88000 0x1000>;
++	};
++
++	fman0_tx_0x28: port@a8000 {
++		cell-index = <0x28>;
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
++		reg = <0xa8000 0x1000>;
++		fsl,qman-channel-id = <0x802>;
++	};
++
++	ethernet@e0000 {
++		cell-index = <0>;
++		compatible = "fsl,fman-memac";
++		reg = <0xe0000 0x1000>;
++		fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
++		ptp-timer = <&ptp_timer0>;
++		pcsphy-handle = <&pcsphy0>;
++	};
++
++	mdio@e1000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xe1000 0x1000>;
++
++		pcsphy0: ethernet-phy@0 {
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
+@@ -0,0 +1,42 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 1g port #1 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman@1a00000 {
++	fman0_rx_0x09: port@89000 {
++		cell-index = <0x9>;
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
++		reg = <0x89000 0x1000>;
++	};
++
++	fman0_tx_0x29: port@a9000 {
++		cell-index = <0x29>;
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
++		reg = <0xa9000 0x1000>;
++		fsl,qman-channel-id = <0x803>;
++	};
++
++	ethernet@e2000 {
++		cell-index = <1>;
++		compatible = "fsl,fman-memac";
++		reg = <0xe2000 0x1000>;
++		fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
++		ptp-timer = <&ptp_timer0>;
++		pcsphy-handle = <&pcsphy1>;
++	};
++
++	mdio@e3000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xe3000 0x1000>;
++
++		pcsphy1: ethernet-phy@0 {
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
+@@ -0,0 +1,42 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 1g port #2 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman@1a00000 {
++	fman0_rx_0x0a: port@8a000 {
++		cell-index = <0xa>;
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
++		reg = <0x8a000 0x1000>;
++	};
++
++	fman0_tx_0x2a: port@aa000 {
++		cell-index = <0x2a>;
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
++		reg = <0xaa000 0x1000>;
++		fsl,qman-channel-id = <0x804>;
++	};
++
++	ethernet@e4000 {
++		cell-index = <2>;
++		compatible = "fsl,fman-memac";
++		reg = <0xe4000 0x1000>;
++		fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
++		ptp-timer = <&ptp_timer0>;
++		pcsphy-handle = <&pcsphy2>;
++	};
++
++	mdio@e5000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xe5000 0x1000>;
++
++		pcsphy2: ethernet-phy@0 {
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
+@@ -0,0 +1,42 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 1g port #3 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman@1a00000 {
++	fman0_rx_0x0b: port@8b000 {
++		cell-index = <0xb>;
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
++		reg = <0x8b000 0x1000>;
++	};
++
++	fman0_tx_0x2b: port@ab000 {
++		cell-index = <0x2b>;
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
++		reg = <0xab000 0x1000>;
++		fsl,qman-channel-id = <0x805>;
++	};
++
++	ethernet@e6000 {
++		cell-index = <3>;
++		compatible = "fsl,fman-memac";
++		reg = <0xe6000 0x1000>;
++		fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
++		ptp-timer = <&ptp_timer0>;
++		pcsphy-handle = <&pcsphy3>;
++	};
++
++	mdio@e7000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xe7000 0x1000>;
++
++		pcsphy3: ethernet-phy@0 {
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
+@@ -0,0 +1,42 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 1g port #4 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman@1a00000 {
++	fman0_rx_0x0c: port@8c000 {
++		cell-index = <0xc>;
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
++		reg = <0x8c000 0x1000>;
++	};
++
++	fman0_tx_0x2c: port@ac000 {
++		cell-index = <0x2c>;
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
++		reg = <0xac000 0x1000>;
++		fsl,qman-channel-id = <0x806>;
++	};
++
++	ethernet@e8000 {
++		cell-index = <4>;
++		compatible = "fsl,fman-memac";
++		reg = <0xe8000 0x1000>;
++		fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
++		ptp-timer = <&ptp_timer0>;
++		pcsphy-handle = <&pcsphy4>;
++	};
++
++	mdio@e9000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xe9000 0x1000>;
++
++		pcsphy4: ethernet-phy@0 {
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
+@@ -0,0 +1,42 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 1g port #5 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman@1a00000 {
++	fman0_rx_0x0d: port@8d000 {
++		cell-index = <0xd>;
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
++		reg = <0x8d000 0x1000>;
++	};
++
++	fman0_tx_0x2d: port@ad000 {
++		cell-index = <0x2d>;
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
++		reg = <0xad000 0x1000>;
++		fsl,qman-channel-id = <0x807>;
++	};
++
++	ethernet@ea000 {
++		cell-index = <5>;
++		compatible = "fsl,fman-memac";
++		reg = <0xea000 0x1000>;
++		fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
++		ptp-timer = <&ptp_timer0>;
++		pcsphy-handle = <&pcsphy5>;
++	};
++
++	mdio@eb000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xeb000 0x1000>;
++
++		pcsphy5: ethernet-phy@0 {
++			reg = <0x0>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
+@@ -0,0 +1,47 @@
++/*
++ * QorIQ FMan v3 OH ports device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++ */
++
++fman@1a00000 {
++
++	fman0_oh1: port@82000 {
++		cell-index = <0>;
++		compatible = "fsl,fman-port-oh";
++		reg = <0x82000 0x1000>;
++	};
++
++	fman0_oh2: port@83000 {
++		cell-index = <1>;
++		compatible = "fsl,fman-port-oh";
++		reg = <0x83000 0x1000>;
++	};
++
++	fman0_oh3: port@84000 {
++		cell-index = <2>;
++		compatible = "fsl,fman-port-oh";
++		reg = <0x84000 0x1000>;
++	};
++
++	fman0_oh4: port@85000 {
++		cell-index = <3>;
++		compatible = "fsl,fman-port-oh";
++		reg = <0x85000 0x1000>;
++	};
++
++	fman0_oh5: port@86000 {
++		cell-index = <4>;
++		compatible = "fsl,fman-port-oh";
++		reg = <0x86000 0x1000>;
++	};
++
++	fman0_oh6: port@87000 {
++		cell-index = <5>;
++		compatible = "fsl,fman-port-oh";
++		reg = <0x87000 0x1000>;
++	};
++
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
+@@ -0,0 +1,130 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ FMan v3 device tree
++ *
++ * Copyright 2012-2015 Freescale Semiconductor Inc.
++ *
++ */
++
++fman0: fman@1a00000 {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	cell-index = <0>;
++	compatible = "fsl,fman";
++	ranges = <0x0 0x00 0x1a00000 0x100000>;
++	reg = <0x0 0x1a00000 0x0 0x100000>;
++	interrupts = <0 44 0x4>, <0 45 0x4>;
++	clocks = <&clockgen 3 0>;
++	clock-names = "fmanclk";
++	fsl,qman-channel-range = <0x800 0x10>;
++
++	cc {
++		compatible = "fsl,fman-cc";
++	};
++
++	muram@0 {
++		compatible = "fsl,fman-muram";
++		reg = <0x0 0x60000>;
++	};
++
++	bmi@80000 {
++		compatible = "fsl,fman-bmi";
++		reg = <0x80000 0x400>;
++	};
++
++	qmi@80400 {
++		compatible = "fsl,fman-qmi";
++		reg = <0x80400 0x400>;
++	};
++
++	fman0_oh_0x2: port@82000 {
++		cell-index = <0x2>;
++		compatible = "fsl,fman-v3-port-oh";
++		reg = <0x82000 0x1000>;
++		fsl,qman-channel-id = <0x809>;
++	};
++
++	fman0_oh_0x3: port@83000 {
++		cell-index = <0x3>;
++		compatible = "fsl,fman-v3-port-oh";
++		reg = <0x83000 0x1000>;
++		fsl,qman-channel-id = <0x80a>;
++	};
++
++	fman0_oh_0x4: port@84000 {
++		cell-index = <0x4>;
++		compatible = "fsl,fman-v3-port-oh";
++		reg = <0x84000 0x1000>;
++		fsl,qman-channel-id = <0x80b>;
++	};
++
++	fman0_oh_0x5: port@85000 {
++		cell-index = <0x5>;
++		compatible = "fsl,fman-v3-port-oh";
++		reg = <0x85000 0x1000>;
++		fsl,qman-channel-id = <0x80c>;
++	};
++
++	fman0_oh_0x6: port@86000 {
++		cell-index = <0x6>;
++		compatible = "fsl,fman-v3-port-oh";
++		reg = <0x86000 0x1000>;
++		fsl,qman-channel-id = <0x80d>;
++	};
++
++	fman0_oh_0x7: port@87000 {
++		cell-index = <0x7>;
++		compatible = "fsl,fman-v3-port-oh";
++		reg = <0x87000 0x1000>;
++		fsl,qman-channel-id = <0x80e>;
++	};
++
++	policer@c0000 {
++		compatible = "fsl,fman-policer";
++		reg = <0xc0000 0x1000>;
++	};
++
++	keygen@c1000 {
++		compatible = "fsl,fman-keygen";
++		reg = <0xc1000 0x1000>;
++	};
++
++	dma@c2000 {
++		compatible = "fsl,fman-dma";
++		reg = <0xc2000 0x1000>;
++	};
++
++	fpm@c3000 {
++		compatible = "fsl,fman-fpm";
++		reg = <0xc3000 0x1000>;
++	};
++
++	parser@c7000 {
++		compatible = "fsl,fman-parser";
++		reg = <0xc7000 0x1000>;
++	};
++
++	vsps@dc000 {
++		compatible = "fsl,fman-vsps";
++		reg = <0xdc000 0x1000>;
++	};
++
++	mdio0: mdio@fc000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xfc000 0x1000>;
++	};
++
++	xmdio0: mdio@fd000 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
++		reg = <0xfd000 0x1000>;
++	};
++
++	ptp_timer0: ptp-timer@fe000 {
++		compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
++		reg = <0xfe000 0x1000>;
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi
+@@ -0,0 +1,38 @@
++/*
++ * QorIQ QMan SDK Portals device tree nodes
++ *
++ * Copyright 2011-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++ */
++
++&qportals {
++	qman-fqids@0 {
++		compatible = "fsl,fqid-range";
++		fsl,fqid-range = <256 256>;
++	};
++
++	qman-fqids@1 {
++		compatible = "fsl,fqid-range";
++		fsl,fqid-range = <32768 32768>;
++	};
++
++	qman-pools@0 {
++		compatible = "fsl,pool-channel-range";
++		fsl,pool-channel-range = <0x401 0xf>;
++	};
++
++	qman-cgrids@0 {
++		compatible = "fsl,cgrid-range";
++		fsl,cgrid-range = <0 256>;
++	};
++
++	qman-ceetm@0 {
++		compatible = "fsl,qman-ceetm";
++		fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
++		fsl,ceetm-sp-range = <0 16>;
++		fsl,ceetm-lni-range = <0 8>;
++		fsl,ceetm-channel-range = <0 32>;
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
+@@ -0,0 +1,87 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * QorIQ QMan Portals device tree
++ *
++ * Copyright 2011-2016 Freescale Semiconductor Inc.
++ *
++ */
++
++&qportals {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	compatible = "simple-bus";
++
++	qportal0: qman-portal@0 {
++		/*
++		 * bootloader fix-ups are expected to provide the
++		 * "fsl,bman-portal-<hardware revision>" compatible
++		 */
++		compatible = "fsl,qman-portal";
++		reg = <0x0 0x4000>, <0x4000000 0x4000>;
++		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <0>;
++	};
++
++	qportal1: qman-portal@10000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x10000 0x4000>, <0x4010000 0x4000>;
++		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <1>;
++	};
++
++	qportal2: qman-portal@20000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x20000 0x4000>, <0x4020000 0x4000>;
++		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <2>;
++	};
++
++	qportal3: qman-portal@30000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x30000 0x4000>, <0x4030000 0x4000>;
++		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <3>;
++	};
++
++	qportal4: qman-portal@40000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x40000 0x4000>, <0x4040000 0x4000>;
++		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <4>;
++	};
++
++	qportal5: qman-portal@50000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x50000 0x4000>, <0x4050000 0x4000>;
++		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <5>;
++	};
++
++	qportal6: qman-portal@60000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x60000 0x4000>, <0x4060000 0x4000>;
++		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <6>;
++	};
++
++	qportal7: qman-portal@70000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x70000 0x4000>, <0x4070000 0x4000>;
++		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <7>;
++	};
++
++	qportal8: qman-portal@80000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x80000 0x4000>, <0x4080000 0x4000>;
++		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <8>;
++	};
++
++	qportal9: qman-portal@90000 {
++		compatible = "fsl,qman-portal";
++		reg = <0x90000 0x4000>, <0x4090000 0x4000>;
++		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++		cell-index = <9>;
++	};
++};
+--- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
+@@ -38,51 +38,61 @@
+ 	compatible = "simple-bus";
+ 
+ 	bman-portal@0 {
++		cell-index = <0>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x0 0x4000>, <0x100000 0x1000>;
+ 		interrupts = <105 2 0 0>;
+ 	};
+ 	bman-portal@4000 {
++		cell-index = <1>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x4000 0x4000>, <0x101000 0x1000>;
+ 		interrupts = <107 2 0 0>;
+ 	};
+ 	bman-portal@8000 {
++		cell-index = <2>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x8000 0x4000>, <0x102000 0x1000>;
+ 		interrupts = <109 2 0 0>;
+ 	};
+ 	bman-portal@c000 {
++		cell-index = <3>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0xc000 0x4000>, <0x103000 0x1000>;
+ 		interrupts = <111 2 0 0>;
+ 	};
+ 	bman-portal@10000 {
++		cell-index = <4>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x10000 0x4000>, <0x104000 0x1000>;
+ 		interrupts = <113 2 0 0>;
+ 	};
+ 	bman-portal@14000 {
++		cell-index = <5>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x14000 0x4000>, <0x105000 0x1000>;
+ 		interrupts = <115 2 0 0>;
+ 	};
+ 	bman-portal@18000 {
++		cell-index = <6>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x18000 0x4000>, <0x106000 0x1000>;
+ 		interrupts = <117 2 0 0>;
+ 	};
+ 	bman-portal@1c000 {
++		cell-index = <7>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x1c000 0x4000>, <0x107000 0x1000>;
+ 		interrupts = <119 2 0 0>;
+ 	};
+ 	bman-portal@20000 {
++		cell-index = <8>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x20000 0x4000>, <0x108000 0x1000>;
+ 		interrupts = <121 2 0 0>;
+ 	};
+ 	bman-portal@24000 {
++		cell-index = <9>;
+ 		compatible = "fsl,bman-portal";
+ 		reg = <0x24000 0x4000>, <0x109000 0x1000>;
+ 		interrupts = <123 2 0 0>;
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
+@@ -35,14 +35,14 @@
+ fman@400000 {
+ 	fman0_rx_0x10: port@90000 {
+ 		cell-index = <0x10>;
+-		compatible = "fsl,fman-v3-port-rx";
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
+ 		reg = <0x90000 0x1000>;
+ 		fsl,fman-10g-port;
+ 	};
+ 
+ 	fman0_tx_0x30: port@b0000 {
+ 		cell-index = <0x30>;
+-		compatible = "fsl,fman-v3-port-tx";
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
+ 		reg = <0xb0000 0x1000>;
+ 		fsl,fman-10g-port;
+ 	};
+--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
+@@ -35,14 +35,14 @@
+ fman@400000 {
+ 	fman0_rx_0x11: port@91000 {
+ 		cell-index = <0x11>;
+-		compatible = "fsl,fman-v3-port-rx";
++		compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
+ 		reg = <0x91000 0x1000>;
+ 		fsl,fman-10g-port;
+ 	};
+ 
+ 	fman0_tx_0x31: port@b1000 {
+ 		cell-index = <0x31>;
+-		compatible = "fsl,fman-v3-port-tx";
++		compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
+ 		reg = <0xb1000 0x1000>;
+ 		fsl,fman-10g-port;
+ 	};
diff --git a/target/linux/layerscape/patches-4.14/303-add-DTS-for-Traverse-LS1043-Boards.patch b/target/linux/layerscape/patches-4.9/303-dts-layerscape-add-traverse-ls1043.patch
similarity index 75%
rename from target/linux/layerscape/patches-4.14/303-add-DTS-for-Traverse-LS1043-Boards.patch
rename to target/linux/layerscape/patches-4.9/303-dts-layerscape-add-traverse-ls1043.patch
index 68a9a3a2c..c57fb0985 100644
--- a/target/linux/layerscape/patches-4.14/303-add-DTS-for-Traverse-LS1043-Boards.patch
+++ b/target/linux/layerscape/patches-4.9/303-dts-layerscape-add-traverse-ls1043.patch
@@ -1,18 +1,17 @@
-From 263092cd68368ac6f030b847a1d5b0069bc2cef3 Mon Sep 17 00:00:00 2001
+From c0612164b379ebc8964da6bc6f6ced9736dce488 Mon Sep 17 00:00:00 2001
 From: Mathew McBride <matt@traverse.com.au>
 Date: Tue, 17 Apr 2018 10:01:03 +1000
-Subject: [PATCH 05/40] add DTS for Traverse LS1043 Boards
+Subject: [PATCH] add DTS for Traverse LS1043 Boards
 
 Signed-off-by: Mathew McBride <matt@traverse.com.au>
 ---
- arch/arm64/boot/dts/freescale/Makefile        |  5 +++-
- .../boot/dts/freescale/traverse-ls1043s.dts   | 29 +++++++++++++++++++
- .../boot/dts/freescale/traverse-ls1043v.dts   | 29 +++++++++++++++++++
- 3 files changed, 62 insertions(+), 1 deletion(-)
+ arch/arm64/boot/dts/freescale/Makefile |    5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
 
 --- a/arch/arm64/boot/dts/freescale/Makefile
 +++ b/arch/arm64/boot/dts/freescale/Makefile
-@@ -22,7 +22,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
+@@ -21,7 +21,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
@@ -26,7 +25,7 @@ Signed-off-by: Mathew McBride <matt@traverse.com.au>
  clean-files	:= *.dtb
 --- a/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts
 +++ b/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts
-@@ -330,3 +330,32 @@
+@@ -330,3 +330,29 @@
  &sata {
  	status = "disabled";
  };
@@ -35,9 +34,6 @@ Signed-off-by: Mathew McBride <matt@traverse.com.au>
 + * These kernels need additional setup for FMan/QMan DMA shared memory
 + */
 +
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
 +&bman_fbpr {
 +	compatible = "fsl,bman-fbpr";
 +	alloc-ranges = <0 0 0x10000 0>;
@@ -61,7 +57,7 @@ Signed-off-by: Mathew McBride <matt@traverse.com.au>
 +};
 --- a/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
 +++ b/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
-@@ -251,3 +251,32 @@
+@@ -251,3 +251,29 @@
  &sata {
  	status = "disabled";
  };
@@ -70,9 +66,6 @@ Signed-off-by: Mathew McBride <matt@traverse.com.au>
 + * These kernels need additional setup for FMan/QMan DMA shared memory
 + */
 +
-+#include "qoriq-qman-portals-sdk.dtsi"
-+#include "qoriq-bman-portals-sdk.dtsi"
-+
 +&bman_fbpr {
 +	compatible = "fsl,bman-fbpr";
 +	alloc-ranges = <0 0 0x10000 0>;
diff --git a/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch b/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
new file mode 100644
index 000000000..89139d93b
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch
@@ -0,0 +1,993 @@
+From c03c545e064a81515fe109ddcc4ecb3895528e58 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Fri, 6 Jul 2018 15:32:05 +0800
+Subject: [PATCH] mtd: spi-nor: support layerscape
+
+This is an integrated patch for layerscape qspi support.
+
+Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
+Signed-off-by: Yunhui Cui <B56489@freescale.com>
+Signed-off-by: mar.krzeminski <mar.krzeminski@gmail.com>
+Signed-off-by: Alison Wang <b18965@freescale.com>
+Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
+Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
+Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
+Signed-off-by: Alexander Kurz <akurz@blala.de>
+Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
+Signed-off-by: Ash Benz <ash.benz@bk.ru>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/mtd/devices/m25p80.c      |   3 +-
+ drivers/mtd/mtdchar.c             |   2 +-
+ drivers/mtd/spi-nor/fsl-quadspi.c | 327 ++++++++++++++++++++++++------
+ drivers/mtd/spi-nor/spi-nor.c     | 141 ++++++++++++-
+ include/linux/mtd/spi-nor.h       |  14 +-
+ 5 files changed, 416 insertions(+), 71 deletions(-)
+
+--- a/drivers/mtd/mtdchar.c
++++ b/drivers/mtd/mtdchar.c
+@@ -455,7 +455,7 @@ static int mtdchar_readoob(struct file *
+ 	 * data. For our userspace tools it is important to dump areas
+ 	 * with ECC errors!
+ 	 * For kernel internal usage it also might return -EUCLEAN
+-	 * to signal the caller that a bitflip has occured and has
++	 * to signal the caller that a bitflip has occurred and has
+ 	 * been corrected by the ECC algorithm.
+ 	 *
+ 	 * Note: currently the standard NAND function, nand_read_oob_std,
+--- a/drivers/mtd/spi-nor/fsl-quadspi.c
++++ b/drivers/mtd/spi-nor/fsl-quadspi.c
+@@ -41,6 +41,8 @@
+ #define QUADSPI_QUIRK_TKT253890		(1 << 2)
+ /* Controller cannot wake up from wait mode, TKT245618 */
+ #define QUADSPI_QUIRK_TKT245618         (1 << 3)
++/* QSPI_AMBA_BASE is internally added by SOC design */
++#define QUADSPI_AMBA_BASE_INTERNAL	(0x10000)
+ 
+ /* The registers */
+ #define QUADSPI_MCR			0x00
+@@ -193,7 +195,7 @@
+ #define QUADSPI_LUT_NUM		64
+ 
+ /* SEQID -- we can have 16 seqids at most. */
+-#define SEQID_QUAD_READ		0
++#define SEQID_READ		0
+ #define SEQID_WREN		1
+ #define SEQID_WRDI		2
+ #define SEQID_RDSR		3
+@@ -205,15 +207,22 @@
+ #define SEQID_RDCR		9
+ #define SEQID_EN4B		10
+ #define SEQID_BRWR		11
++#define SEQID_RDAR_OR_RD_EVCR	12
++#define SEQID_WRAR		13
++#define SEQID_WD_EVCR           14
+ 
+ #define QUADSPI_MIN_IOMAP SZ_4M
+ 
++#define FLASH_VENDOR_SPANSION_FS	"s25fs"
++#define SPANSION_S25FS_FAMILY	(1 << 1)
++
+ enum fsl_qspi_devtype {
+ 	FSL_QUADSPI_VYBRID,
+ 	FSL_QUADSPI_IMX6SX,
+ 	FSL_QUADSPI_IMX7D,
+ 	FSL_QUADSPI_IMX6UL,
+ 	FSL_QUADSPI_LS1021A,
++	FSL_QUADSPI_LS2080A,
+ };
+ 
+ struct fsl_qspi_devtype_data {
+@@ -224,7 +233,7 @@ struct fsl_qspi_devtype_data {
+ 	int driver_data;
+ };
+ 
+-static struct fsl_qspi_devtype_data vybrid_data = {
++static const struct fsl_qspi_devtype_data vybrid_data = {
+ 	.devtype = FSL_QUADSPI_VYBRID,
+ 	.rxfifo = 128,
+ 	.txfifo = 64,
+@@ -232,7 +241,7 @@ static struct fsl_qspi_devtype_data vybr
+ 	.driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
+ };
+ 
+-static struct fsl_qspi_devtype_data imx6sx_data = {
++static const struct fsl_qspi_devtype_data imx6sx_data = {
+ 	.devtype = FSL_QUADSPI_IMX6SX,
+ 	.rxfifo = 128,
+ 	.txfifo = 512,
+@@ -241,7 +250,7 @@ static struct fsl_qspi_devtype_data imx6
+ 		       | QUADSPI_QUIRK_TKT245618,
+ };
+ 
+-static struct fsl_qspi_devtype_data imx7d_data = {
++static const struct fsl_qspi_devtype_data imx7d_data = {
+ 	.devtype = FSL_QUADSPI_IMX7D,
+ 	.rxfifo = 512,
+ 	.txfifo = 512,
+@@ -250,7 +259,7 @@ static struct fsl_qspi_devtype_data imx7
+ 		       | QUADSPI_QUIRK_4X_INT_CLK,
+ };
+ 
+-static struct fsl_qspi_devtype_data imx6ul_data = {
++static const struct fsl_qspi_devtype_data imx6ul_data = {
+ 	.devtype = FSL_QUADSPI_IMX6UL,
+ 	.rxfifo = 128,
+ 	.txfifo = 512,
+@@ -267,6 +276,14 @@ static struct fsl_qspi_devtype_data ls10
+ 	.driver_data = 0,
+ };
+ 
++static struct fsl_qspi_devtype_data ls2080a_data = {
++	.devtype = FSL_QUADSPI_LS2080A,
++	.rxfifo = 128,
++	.txfifo = 64,
++	.ahb_buf_size = 1024,
++	.driver_data = QUADSPI_AMBA_BASE_INTERNAL | QUADSPI_QUIRK_TKT253890,
++};
++
+ #define FSL_QSPI_MAX_CHIP	4
+ struct fsl_qspi {
+ 	struct spi_nor nor[FSL_QSPI_MAX_CHIP];
+@@ -282,6 +299,7 @@ struct fsl_qspi {
+ 	u32 nor_size;
+ 	u32 nor_num;
+ 	u32 clk_rate;
++	u32 ddr_smp;
+ 	unsigned int chip_base_addr; /* We may support two chips. */
+ 	bool has_second_chip;
+ 	bool big_endian;
+@@ -309,6 +327,23 @@ static inline int needs_wakeup_wait_mode
+ 	return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
+ }
+ 
++static inline int has_added_amba_base_internal(struct fsl_qspi *q)
++{
++	return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
++}
++
++static u32 fsl_get_nor_vendor(struct spi_nor *nor)
++{
++	u32 vendor_id;
++
++	if (nor->vendor) {
++		if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS,
++					sizeof(FLASH_VENDOR_SPANSION_FS) - 1))
++			vendor_id = SPANSION_S25FS_FAMILY;
++	}
++	return vendor_id;
++}
++
+ /*
+  * R/W functions for big- or little-endian registers:
+  * The qSPI controller's endian is independent of the CPU core's endian.
+@@ -331,6 +366,31 @@ static u32 qspi_readl(struct fsl_qspi *q
+ 		return ioread32(addr);
+ }
+ 
++static inline u32 *u8tou32(u32 *dest, const u8 *src, size_t n)
++{
++	size_t i;
++	*dest = 0;
++
++	n = n > 4 ? 4 : n;
++	for (i = 0; i < n; i++)
++		*dest |= *src++ << i * 8;
++
++	return dest;
++
++}
++
++static inline u8 *u32tou8(u8 *dest, const u32 *src, size_t n)
++{
++	size_t i;
++	u8 *xdest = dest;
++
++	n = n > 4 ? 4 : n;
++	for (i = 0; i < n; i++)
++		*xdest++ = *src >> i * 8;
++
++	return dest;
++}
++
+ /*
+  * An IC bug makes us to re-arrange the 32-bit data.
+  * The following chips, such as IMX6SLX, have fixed this bug.
+@@ -373,8 +433,15 @@ static void fsl_qspi_init_lut(struct fsl
+ 	void __iomem *base = q->iobase;
+ 	int rxfifo = q->devtype_data->rxfifo;
+ 	u32 lut_base;
+-	u8 cmd, addrlen, dummy;
+ 	int i;
++	u32 vendor;
++
++	struct spi_nor *nor = &q->nor[0];
++	u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
++	u8 read_op = nor->read_opcode;
++	u8 read_dm = nor->read_dummy;
++
++	vendor = fsl_get_nor_vendor(nor);
+ 
+ 	fsl_qspi_unlock_lut(q);
+ 
+@@ -382,24 +449,50 @@ static void fsl_qspi_init_lut(struct fsl
+ 	for (i = 0; i < QUADSPI_LUT_NUM; i++)
+ 		qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
+ 
+-	/* Quad Read */
+-	lut_base = SEQID_QUAD_READ * 4;
++	/* Read */
++	lut_base = SEQID_READ * 4;
+ 
+-	if (q->nor_size <= SZ_16M) {
+-		cmd = SPINOR_OP_READ_1_1_4;
+-		addrlen = ADDR24BIT;
+-		dummy = 8;
+-	} else {
+-		/* use the 4-byte address */
+-		cmd = SPINOR_OP_READ_1_1_4;
+-		addrlen = ADDR32BIT;
+-		dummy = 8;
+-	}
+-
+-	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++	if (nor->flash_read == SPI_NOR_FAST) {
++		qspi_writel(q, LUT0(CMD, PAD1, read_op) |
++			    LUT1(ADDR, PAD1, addrlen),
++				base + QUADSPI_LUT(lut_base));
++		qspi_writel(q,  LUT0(DUMMY, PAD1, read_dm) |
++			    LUT1(FSL_READ, PAD1, rxfifo),
++				base + QUADSPI_LUT(lut_base + 1));
++	} else if (nor->flash_read == SPI_NOR_QUAD) {
++		if (q->nor_size == 0x4000000) {
++			read_op = 0xEC;
++		qspi_writel(q,
++			LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen),
+ 			base + QUADSPI_LUT(lut_base));
+-	qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
++		qspi_writel(q,
++			LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm),
+ 			base + QUADSPI_LUT(lut_base + 1));
++		qspi_writel(q,
++			LUT0(FSL_READ, PAD4, rxfifo),
++			base + QUADSPI_LUT(lut_base + 2));
++		} else {
++			qspi_writel(q, LUT0(CMD, PAD1, read_op) |
++				    LUT1(ADDR, PAD1, addrlen),
++				    base + QUADSPI_LUT(lut_base));
++			qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
++				    LUT1(FSL_READ, PAD4, rxfifo),
++				    base + QUADSPI_LUT(lut_base + 1));
++		}
++	} else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
++		/* read mode : 1-4-4, such as Spansion s25fl128s. */
++		qspi_writel(q, LUT0(CMD, PAD1, read_op)
++			| LUT1(ADDR_DDR, PAD4, addrlen),
++			base + QUADSPI_LUT(lut_base));
++
++		qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
++			| LUT1(DUMMY, PAD1, read_dm),
++			base + QUADSPI_LUT(lut_base + 1));
++
++		qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
++			| LUT1(JMP_ON_CS, PAD1, 0),
++			base + QUADSPI_LUT(lut_base + 2));
++	}
+ 
+ 	/* Write enable */
+ 	lut_base = SEQID_WREN * 4;
+@@ -409,16 +502,8 @@ static void fsl_qspi_init_lut(struct fsl
+ 	/* Page Program */
+ 	lut_base = SEQID_PP * 4;
+ 
+-	if (q->nor_size <= SZ_16M) {
+-		cmd = SPINOR_OP_PP;
+-		addrlen = ADDR24BIT;
+-	} else {
+-		/* use the 4-byte address */
+-		cmd = SPINOR_OP_PP;
+-		addrlen = ADDR32BIT;
+-	}
+-
+-	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++	qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
++		    LUT1(ADDR, PAD1, addrlen),
+ 			base + QUADSPI_LUT(lut_base));
+ 	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
+ 			base + QUADSPI_LUT(lut_base + 1));
+@@ -432,10 +517,8 @@ static void fsl_qspi_init_lut(struct fsl
+ 	/* Erase a sector */
+ 	lut_base = SEQID_SE * 4;
+ 
+-	cmd = q->nor[0].erase_opcode;
+-	addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
+-
+-	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
++	qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
++		    LUT1(ADDR, PAD1, addrlen),
+ 			base + QUADSPI_LUT(lut_base));
+ 
+ 	/* Erase the whole chip */
+@@ -476,6 +559,44 @@ static void fsl_qspi_init_lut(struct fsl
+ 	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
+ 			base + QUADSPI_LUT(lut_base));
+ 
++
++	/*
++	 * Flash Micron and Spansion command confilict
++	 * use the same value 0x65. But it indicates different meaning.
++	 */
++	lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
++
++	if (vendor == SPANSION_S25FS_FAMILY) {
++		/*
++		* Read any device register.
++		* Used for Spansion S25FS-S family flash only.
++		*/
++		qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
++			    LUT1(ADDR, PAD1, ADDR24BIT),
++			    base + QUADSPI_LUT(lut_base));
++		qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
++			    base + QUADSPI_LUT(lut_base + 1));
++	} else {
++		qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
++			    base + QUADSPI_LUT(lut_base));
++	}
++
++	/*
++	 * Write any device register.
++	 * Used for Spansion S25FS-S family flash only.
++	 */
++	lut_base = SEQID_WRAR * 4;
++	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
++			LUT1(ADDR, PAD1, ADDR24BIT),
++			base + QUADSPI_LUT(lut_base));
++	qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
++			base + QUADSPI_LUT(lut_base + 1));
++
++	/* Write EVCR register */
++	lut_base = SEQID_WD_EVCR * 4;
++	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
++		    base + QUADSPI_LUT(lut_base));
++
+ 	fsl_qspi_lock_lut(q);
+ }
+ 
+@@ -483,8 +604,24 @@ static void fsl_qspi_init_lut(struct fsl
+ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
+ {
+ 	switch (cmd) {
++	case SPINOR_OP_READ_1_4_4_D:
++	case SPINOR_OP_READ4_1_4_4_D:
++	case SPINOR_OP_READ4_1_1_4:
+ 	case SPINOR_OP_READ_1_1_4:
+-		return SEQID_QUAD_READ;
++	case SPINOR_OP_READ_FAST:
++	case SPINOR_OP_READ4_FAST:
++		return SEQID_READ;
++	/*
++	 * Spansion & Micron use the same command value 0x65
++	 * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
++	 * Micron: SPINOR_OP_RD_EVCR,
++	 * read enhanced volatile configuration register.
++	 * case SPINOR_OP_RD_EVCR:
++	 */
++	case SPINOR_OP_SPANSION_RDAR:
++		return SEQID_RDAR_OR_RD_EVCR;
++	case SPINOR_OP_SPANSION_WRAR:
++		return SEQID_WRAR;
+ 	case SPINOR_OP_WREN:
+ 		return SEQID_WREN;
+ 	case SPINOR_OP_WRDI:
+@@ -496,6 +633,7 @@ static int fsl_qspi_get_seqid(struct fsl
+ 	case SPINOR_OP_CHIP_ERASE:
+ 		return SEQID_CHIP_ERASE;
+ 	case SPINOR_OP_PP:
++	case SPINOR_OP_PP_4B:
+ 		return SEQID_PP;
+ 	case SPINOR_OP_RDID:
+ 		return SEQID_RDID;
+@@ -507,6 +645,8 @@ static int fsl_qspi_get_seqid(struct fsl
+ 		return SEQID_EN4B;
+ 	case SPINOR_OP_BRWR:
+ 		return SEQID_BRWR;
++	case SPINOR_OP_WD_EVCR:
++		return SEQID_WD_EVCR;
+ 	default:
+ 		if (cmd == q->nor[0].erase_opcode)
+ 			return SEQID_SE;
+@@ -531,8 +671,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
+ 	/* save the reg */
+ 	reg = qspi_readl(q, base + QUADSPI_MCR);
+ 
+-	qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
+-			base + QUADSPI_SFAR);
++	if (has_added_amba_base_internal(q))
++		qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
++	else
++		qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
++			    base + QUADSPI_SFAR);
+ 	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+ 			base + QUADSPI_RBCT);
+ 	qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
+@@ -582,10 +725,10 @@ static void fsl_qspi_read_data(struct fs
+ 				q->chip_base_addr, tmp);
+ 
+ 		if (len >= 4) {
+-			*((u32 *)rxbuf) = tmp;
++			u32tou8(rxbuf, &tmp, 4);
+ 			rxbuf += 4;
+ 		} else {
+-			memcpy(rxbuf, &tmp, len);
++			u32tou8(rxbuf, &tmp, len);
+ 			break;
+ 		}
+ 
+@@ -619,11 +762,12 @@ static inline void fsl_qspi_invalid(stru
+ }
+ 
+ static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
+-				u8 opcode, unsigned int to, u32 *txbuf,
++				u8 opcode, unsigned int to, u8 *txbuf,
+ 				unsigned count)
+ {
+ 	int ret, i, j;
+ 	u32 tmp;
++	u8 byts;
+ 
+ 	dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
+ 		q->chip_base_addr, to, count);
+@@ -633,10 +777,13 @@ static ssize_t fsl_qspi_nor_write(struct
+ 	qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
+ 
+ 	/* fill the TX data to the FIFO */
++	byts = count;
+ 	for (j = 0, i = ((count + 3) / 4); j < i; j++) {
+-		tmp = fsl_qspi_endian_xchg(q, *txbuf);
++		u8tou32(&tmp, txbuf, byts);
++		tmp = fsl_qspi_endian_xchg(q, tmp);
+ 		qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
+-		txbuf++;
++		txbuf += 4;
++		byts -= 4;
+ 	}
+ 
+ 	/* fill the TXFIFO upto 16 bytes for i.MX7d */
+@@ -657,11 +804,43 @@ static void fsl_qspi_set_map_addr(struct
+ {
+ 	int nor_size = q->nor_size;
+ 	void __iomem *base = q->iobase;
++	u32 mem_base;
++
++	if (has_added_amba_base_internal(q))
++		mem_base = 0x0;
++	else
++		mem_base = q->memmap_phy;
++
++	qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
++	qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
++	qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
++	qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
++}
++
++/*
++ * enable controller ddr quad mode to support different
++ * vender flashes ddr quad mode.
++ */
++static void set_ddr_quad_mode(struct fsl_qspi *q)
++{
++	u32 reg, reg2;
++
++	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
++
++	/* Firstly, disable the module */
++	qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
++
++	/* Set the Sampling Register for DDR */
++	reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
++	reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
++	reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
++			QUADSPI_SMPR_DDRSMP_MASK);
++	qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
++
++	/* Enable the module again (enable the DDR too) */
++	reg |= QUADSPI_MCR_DDR_EN_MASK;
++	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
+ 
+-	qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
+-	qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
+-	qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
+-	qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
+ }
+ 
+ /*
+@@ -704,6 +883,11 @@ static void fsl_qspi_init_abh_read(struc
+ 	seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
+ 	qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
+ 		q->iobase + QUADSPI_BFGENCR);
++
++	/* enable the DDR quad read */
++	if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
++		set_ddr_quad_mode(q);
++
+ }
+ 
+ /* This function was used to prepare and enable QSPI clock */
+@@ -822,6 +1006,7 @@ static const struct of_device_id fsl_qsp
+ 	{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
+ 	{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
+ 	{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
++	{ .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
+@@ -835,8 +1020,12 @@ static int fsl_qspi_read_reg(struct spi_
+ {
+ 	int ret;
+ 	struct fsl_qspi *q = nor->priv;
++	u32 to = 0;
+ 
+-	ret = fsl_qspi_runcmd(q, opcode, 0, len);
++	if (opcode == SPINOR_OP_SPANSION_RDAR)
++		u8tou32(&to, nor->cmd_buf, 4);
++
++	ret = fsl_qspi_runcmd(q, opcode, to, len);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -848,9 +1037,13 @@ static int fsl_qspi_write_reg(struct spi
+ {
+ 	struct fsl_qspi *q = nor->priv;
+ 	int ret;
++	u32 to = 0;
++
++	if (opcode == SPINOR_OP_SPANSION_WRAR)
++		u8tou32(&to, nor->cmd_buf, 4);
+ 
+ 	if (!buf) {
+-		ret = fsl_qspi_runcmd(q, opcode, 0, 1);
++		ret = fsl_qspi_runcmd(q, opcode, to, 1);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -859,7 +1052,7 @@ static int fsl_qspi_write_reg(struct spi
+ 
+ 	} else if (len > 0) {
+ 		ret = fsl_qspi_nor_write(q, nor, opcode, 0,
+-					(u32 *)buf, len);
++					buf, len);
+ 		if (ret > 0)
+ 			return 0;
+ 	} else {
+@@ -875,7 +1068,7 @@ static ssize_t fsl_qspi_write(struct spi
+ {
+ 	struct fsl_qspi *q = nor->priv;
+ 	ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
+-					 (u32 *)buf, len);
++					 (u8 *)buf, len);
+ 
+ 	/* invalid the data in the AHB buffer. */
+ 	fsl_qspi_invalid(q);
+@@ -922,7 +1115,7 @@ static ssize_t fsl_qspi_read(struct spi_
+ 		len);
+ 
+ 	/* Read out the data directly from the AHB buffer.*/
+-	memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
++	memcpy_toio(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
+ 		len);
+ 
+ 	return len;
+@@ -980,6 +1173,8 @@ static int fsl_qspi_probe(struct platfor
+ 	struct spi_nor *nor;
+ 	struct mtd_info *mtd;
+ 	int ret, i = 0;
++	int find_node;
++	enum read_mode mode = SPI_NOR_QUAD;
+ 
+ 	q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
+ 	if (!q)
+@@ -1027,6 +1222,12 @@ static int fsl_qspi_probe(struct platfor
+ 		goto clk_failed;
+ 	}
+ 
++	/* find ddrsmp value */
++	ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
++				&q->ddr_smp);
++	if (ret)
++		q->ddr_smp = 0;
++
+ 	/* find the irq */
+ 	ret = platform_get_irq(pdev, 0);
+ 	if (ret < 0) {
+@@ -1050,6 +1251,7 @@ static int fsl_qspi_probe(struct platfor
+ 
+ 	mutex_init(&q->lock);
+ 
++	find_node = 0;
+ 	/* iterate the subnodes. */
+ 	for_each_available_child_of_node(dev->of_node, np) {
+ 		/* skip the holes */
+@@ -1076,18 +1278,25 @@ static int fsl_qspi_probe(struct platfor
+ 		ret = of_property_read_u32(np, "spi-max-frequency",
+ 				&q->clk_rate);
+ 		if (ret < 0)
+-			goto mutex_failed;
++			continue;
+ 
+ 		/* set the chip address for READID */
+ 		fsl_qspi_set_base_addr(q, nor);
+ 
+-		ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
++		ret = of_property_read_bool(np, "m25p,fast-read");
++		mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
++		/* Can we enable the DDR Quad Read? */
++		ret = of_property_read_bool(np, "ddr-quad-read");
+ 		if (ret)
+-			goto mutex_failed;
++			mode = SPI_NOR_DDR_QUAD;
++
++		ret = spi_nor_scan(nor, NULL, mode);
++		if (ret)
++			continue;
+ 
+ 		ret = mtd_device_register(mtd, NULL, 0);
+ 		if (ret)
+-			goto mutex_failed;
++			continue;
+ 
+ 		/* Set the correct NOR size now. */
+ 		if (q->nor_size == 0) {
+@@ -1110,8 +1319,12 @@ static int fsl_qspi_probe(struct platfor
+ 			nor->page_size = q->devtype_data->txfifo;
+ 
+ 		i++;
++		find_node++;
+ 	}
+ 
++	if (find_node == 0)
++		goto mutex_failed;
++
+ 	/* finish the rest init. */
+ 	ret = fsl_qspi_nor_setup_last(q);
+ 	if (ret)
+--- a/drivers/mtd/spi-nor/spi-nor.c
++++ b/drivers/mtd/spi-nor/spi-nor.c
+@@ -40,6 +40,13 @@
+ #define SPI_NOR_MAX_ID_LEN	6
+ #define SPI_NOR_MAX_ADDR_WIDTH	4
+ 
++#define SPI_NOR_MICRON_WRITE_ENABLE    0x7f
++/* Added for S25FS-S family flash */
++#define SPINOR_CONFIG_REG3_OFFSET      0x800004
++#define CR3V_4KB_ERASE_UNABLE  0x8
++#define SPINOR_S25FS_FAMILY_ID 0x81
++
++
+ struct flash_info {
+ 	char		*name;
+ 
+@@ -68,7 +75,8 @@ struct flash_info {
+ #define SECT_4K_PMC		BIT(4)	/* SPINOR_OP_BE_4K_PMC works uniformly */
+ #define SPI_NOR_DUAL_READ	BIT(5)	/* Flash supports Dual Read */
+ #define SPI_NOR_QUAD_READ	BIT(6)	/* Flash supports Quad Read */
+-#define USE_FSR			BIT(7)	/* use flag status register */
++#define USE_FSR			BIT(13)	/* use flag status register */
++#define SPI_NOR_DDR_QUAD_READ	BIT(7)	/* Flash supports DDR Quad Read */
+ #define SPI_NOR_HAS_LOCK	BIT(8)	/* Flash supports lock/unlock via SR */
+ #define SPI_NOR_HAS_TB		BIT(9)	/*
+ 					 * Flash SR has Top/Bottom (TB) protect
+@@ -85,9 +93,11 @@ struct flash_info {
+ 					 * Use dedicated 4byte address op codes
+ 					 * to support memory size above 128Mib.
+ 					 */
++#define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
+ };
+ 
+ #define JEDEC_MFR(info)	((info)->id[0])
++#define EXT_ID(info)	((info)->id[5])
+ 
+ static const struct flash_info *spi_nor_match_id(const char *name);
+ 
+@@ -132,7 +142,7 @@ static int read_fsr(struct spi_nor *nor)
+ /*
+  * Read configuration register, returning its value in the
+  * location. Return the configuration register value.
+- * Returns negative if error occured.
++ * Returns negative if error occurred.
+  */
+ static int read_cr(struct spi_nor *nor)
+ {
+@@ -160,6 +170,8 @@ static inline int spi_nor_read_dummy_cyc
+ 	case SPI_NOR_DUAL:
+ 	case SPI_NOR_QUAD:
+ 		return 8;
++	case SPI_NOR_DDR_QUAD:
++		return 6;
+ 	case SPI_NOR_NORMAL:
+ 		return 0;
+ 	}
+@@ -962,6 +974,8 @@ static const struct flash_info spi_nor_i
+ 
+ 	/* ESMT */
+ 	{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
++	{ "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
++	{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
+ 
+ 	/* Everspin */
+ 	{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+@@ -1021,12 +1035,15 @@ static const struct flash_info spi_nor_i
+ 	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, SECT_4K) },
+ 	{ "mx25l3255e",  INFO(0xc29e16, 0, 64 * 1024,  64, SECT_4K) },
+ 	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
++	{ "mx25u2033e",  INFO(0xc22532, 0, 64 * 1024,   4, SECT_4K) },
++	{ "mx25u4035",   INFO(0xc22533, 0, 64 * 1024,   8, SECT_4K) },
++	{ "mx25u8035",   INFO(0xc22534, 0, 64 * 1024,  16, SECT_4K) },
+ 	{ "mx25u3235f",	 INFO(0xc22536, 0, 64 * 1024, 64, 0) },
+ 	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
+ 	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
+ 	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
+ 	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
+-	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
++	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
+ 	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
+ 	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
+ 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
+@@ -1040,10 +1057,11 @@ static const struct flash_info spi_nor_i
+ 	{ "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
+ 	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
+ 	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
++	{ "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
+ 	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ 	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+-	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+-	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
++	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
++	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+ 
+ 	/* PMC */
+ 	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
+@@ -1061,8 +1079,11 @@ static const struct flash_info spi_nor_i
+ 	{ "s70fl01gs",  INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
+ 	{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },
+ 	{ "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },
+-	{ "s25fl128s",	INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++	{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
++	{ "s25fl128s",	INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ
++			| SPI_NOR_DDR_QUAD_READ) },
+ 	{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++	{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)},
+ 	{ "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ 	{ "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },
+ 	{ "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },
+@@ -1136,7 +1157,15 @@ static const struct flash_info spi_nor_i
+ 	{ "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
+ 	{ "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
+ 	{ "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
++	{
++		"w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
++			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
++			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
++	},
+ 	{ "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
++	{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
++	{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
++	{ "w25q20ew", INFO(0xef6012, 0, 64 * 1024,  4, SECT_4K) },
+ 	{ "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
+ 	{
+ 		"w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
+@@ -1208,6 +1237,53 @@ static const struct flash_info *spi_nor_
+ 		id[0], id[1], id[2]);
+ 	return ERR_PTR(-ENODEV);
+ }
++/*
++ * The S25FS-S family physical sectors may be configured as a
++ * hybrid combination of eight 4-kB parameter sectors
++ * at the top or bottom of the address space with all
++ * but one of the remaining sectors being uniform size.
++ * The Parameter Sector Erase commands (20h or 21h) must
++ * be used to erase the 4-kB parameter sectors individually.
++ * The Sector (uniform sector) Erase commands (D8h or DCh)
++ * must be used to erase any of the remaining
++ * sectors, including the portion of highest or lowest address
++ * sector that is not overlaid by the parameter sectors.
++ * The uniform sector erase command has no effect on parameter sectors.
++ */
++static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor)
++{
++	struct fsl_qspi *q;
++	u32 cr3v_addr  = SPINOR_CONFIG_REG3_OFFSET;
++	u8 cr3v = 0x0;
++	int ret = 0x0;
++
++	q = nor->priv;
++
++	nor->cmd_buf[2] = cr3v_addr >> 16;
++	nor->cmd_buf[1] = cr3v_addr >> 8;
++	nor->cmd_buf[0] = cr3v_addr >> 0;
++
++	ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
++	if (ret)
++		return ret;
++	if (cr3v & CR3V_4KB_ERASE_UNABLE)
++		return 0;
++	ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
++	if (ret)
++		return ret;
++	cr3v = CR3V_4KB_ERASE_UNABLE;
++	nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
++	nor->write(nor, cr3v_addr, 1, &cr3v);
++
++	ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
++	if (ret)
++		return ret;
++	if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
++		return -EPERM;
++
++	return 0;
++}
++
+ 
+ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
+ 			size_t *retlen, u_char *buf)
+@@ -1427,7 +1503,7 @@ static int macronix_quad_enable(struct s
+  * Write status Register and configuration register with 2 bytes
+  * The first byte will be written to the status register, while the
+  * second byte will be written to the configuration register.
+- * Return negative if error occured.
++ * Return negative if error occurred.
+  */
+ static int write_sr_cr(struct spi_nor *nor, u16 val)
+ {
+@@ -1475,6 +1551,24 @@ static int spansion_quad_enable(struct s
+ 	return 0;
+ }
+ 
++static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
++{
++	int status;
++
++	switch (JEDEC_MFR(info)) {
++	case SNOR_MFR_SPANSION:
++		status = spansion_quad_enable(nor);
++		if (status) {
++			dev_err(nor->dev, "Spansion DDR quad-read not enabled\n");
++			return status;
++		}
++		return status;
++	default:
++		return -EINVAL;
++	}
++}
++
++
+ static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
+ {
+ 	int status;
+@@ -1621,9 +1715,25 @@ int spi_nor_scan(struct spi_nor *nor, co
+ 		write_sr(nor, 0);
+ 		spi_nor_wait_till_ready(nor);
+ 	}
++	if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
++		ret = read_sr(nor);
++		ret &= SPI_NOR_MICRON_WRITE_ENABLE;
++
++		write_enable(nor);
++		write_sr(nor, ret);
++	}
++
++	if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) {
++		ret = spansion_s25fs_disable_4kb_erase(nor);
++		if (ret)
++			return ret;
++	}
++
+ 
+ 	if (!mtd->name)
+ 		mtd->name = dev_name(dev);
++	if (info->name)
++		nor->vendor = info->name;
+ 	mtd->priv = nor;
+ 	mtd->type = MTD_NORFLASH;
+ 	mtd->writesize = 1;
+@@ -1657,6 +1767,8 @@ int spi_nor_scan(struct spi_nor *nor, co
+ 		nor->flags |= SNOR_F_USE_FSR;
+ 	if (info->flags & SPI_NOR_HAS_TB)
+ 		nor->flags |= SNOR_F_HAS_SR_TB;
++	if (info->flags & NO_CHIP_ERASE)
++		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
+ 
+ #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
+ 	/* prefer "small sector" erase if possible */
+@@ -1696,9 +1808,15 @@ int spi_nor_scan(struct spi_nor *nor, co
+ 	/* Some devices cannot do fast-read, no matter what DT tells us */
+ 	if (info->flags & SPI_NOR_NO_FR)
+ 		nor->flash_read = SPI_NOR_NORMAL;
+-
+-	/* Quad/Dual-read mode takes precedence over fast/normal */
+-	if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
++	/* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
++	if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
++		ret = set_ddr_quad_mode(nor, info);
++		if (ret) {
++			dev_err(dev, "DDR quad mode not supported\n");
++			return ret;
++		}
++		nor->flash_read = SPI_NOR_DDR_QUAD;
++	} else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
+ 		ret = set_quad_mode(nor, info);
+ 		if (ret) {
+ 			dev_err(dev, "quad mode not supported\n");
+@@ -1711,6 +1829,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+ 
+ 	/* Default commands */
+ 	switch (nor->flash_read) {
++	case SPI_NOR_DDR_QUAD:
++		nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
++		break;
+ 	case SPI_NOR_QUAD:
+ 		nor->read_opcode = SPINOR_OP_READ_1_1_4;
+ 		break;
+--- a/include/linux/mtd/spi-nor.h
++++ b/include/linux/mtd/spi-nor.h
+@@ -31,10 +31,10 @@
+ 
+ /*
+  * Note on opcode nomenclature: some opcodes have a format like
+- * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
++ * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number
+  * of I/O lines used for the opcode, address, and data (respectively). The
+  * FUNCTION has an optional suffix of '4', to represent an opcode which
+- * requires a 4-byte (32-bit) address.
++ * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
+  */
+ 
+ /* Flash opcodes. */
+@@ -46,7 +46,9 @@
+ #define SPINOR_OP_READ_1_1_2	0x3b	/* Read data bytes (Dual Output SPI) */
+ #define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
+ #define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
++#define SPINOR_OP_READ_1_4_4_D	0xed	/* Read data bytes (DDR Quad SPI) */
+ #define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
++#define SPINOR_OP_READ4_1_4_4_D	0xee	/* Read data bytes (DDR Quad SPI) */
+ #define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
+ #define SPINOR_OP_PP_1_1_4	0x32	/* Quad page program */
+ #define SPINOR_OP_PP_1_4_4	0x38	/* Quad page program */
+@@ -62,9 +64,11 @@
+ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
+ #define SPINOR_OP_READ_4B	0x13	/* Read data bytes (low frequency) */
+ #define SPINOR_OP_READ_FAST_4B	0x0c	/* Read data bytes (high frequency) */
++#define SPINOR_OP_READ4_FAST    0x0c    /* Read data bytes (high frequency) */
+ #define SPINOR_OP_READ_1_1_2_4B	0x3c	/* Read data bytes (Dual Output SPI) */
+ #define SPINOR_OP_READ_1_2_2_4B	0xbc	/* Read data bytes (Dual I/O SPI) */
+ #define SPINOR_OP_READ_1_1_4_4B	0x6c	/* Read data bytes (Quad Output SPI) */
++#define SPINOR_OP_READ4_1_1_4  0x6c    /* Read data bytes (Quad SPI) */
+ #define SPINOR_OP_READ_1_4_4_4B	0xec	/* Read data bytes (Quad I/O SPI) */
+ #define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
+ #define SPINOR_OP_PP_1_1_4_4B	0x34	/* Quad page program */
+@@ -94,6 +98,10 @@
+ /* Used for Spansion flashes only. */
+ #define SPINOR_OP_BRWR		0x17	/* Bank register write */
+ 
++/* Used for Spansion S25FS-S family flash only. */
++#define SPINOR_OP_SPANSION_RDAR	0x65	/* Read any device register */
++#define SPINOR_OP_SPANSION_WRAR	0x71	/* Write any device register */
++
+ /* Used for Micron flashes only. */
+ #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
+ #define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
+@@ -124,6 +132,7 @@ enum read_mode {
+ 	SPI_NOR_FAST,
+ 	SPI_NOR_DUAL,
+ 	SPI_NOR_QUAD,
++	SPI_NOR_DDR_QUAD,
+ };
+ 
+ #define SPI_NOR_MAX_CMD_SIZE	8
+@@ -189,6 +198,7 @@ struct spi_nor {
+ 	bool			sst_write_second;
+ 	u32			flags;
+ 	u8			cmd_buf[SPI_NOR_MAX_CMD_SIZE];
++	char			*vendor;
+ 
+ 	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+ 	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
diff --git a/target/linux/layerscape/patches-4.14/813-ifc-nor-nand-support-layerscape.patch b/target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch
similarity index 86%
rename from target/linux/layerscape/patches-4.14/813-ifc-nor-nand-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch
index dd024305c..9f44e9e72 100644
--- a/target/linux/layerscape/patches-4.14/813-ifc-nor-nand-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch
@@ -1,19 +1,33 @@
-From 780865643e5dbf41fe950924a68f7ee4fea8af3e Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:39 +0800
-Subject: [PATCH 30/40] ifc-nor-nand: support layerscape
-This is an integrated patch of ifc-nor-nand for
- layerscape
+From d9d0181f74146507026c31cccd52dda27ec3d966 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 14:57:31 +0800
+Subject: [PATCH 06/30] mtd: support layerscape
 
+This is an integrated patch for layerscape ifc-nor-nand support.
+
+Signed-off-by: Alison Wang <b18965@freescale.com>
 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
-Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/memory/fsl_ifc.c           | 263 +++++++++++++++++++++++++++++
- drivers/mtd/maps/physmap_of_core.c |   4 +
- include/linux/fsl_ifc.h            |   7 +
- 3 files changed, 274 insertions(+)
+ drivers/memory/Kconfig          |   2 +-
+ drivers/memory/fsl_ifc.c        | 263 ++++++++++++++++++++++++++++++++++++++++
+ drivers/mtd/maps/physmap_of.c   |   4 +
+ drivers/mtd/nand/Kconfig        |   2 +-
+ drivers/mtd/nand/fsl_ifc_nand.c |   5 +-
+ include/linux/fsl_ifc.h         |   7 ++
+ 6 files changed, 280 insertions(+), 3 deletions(-)
 
+--- a/drivers/memory/Kconfig
++++ b/drivers/memory/Kconfig
+@@ -115,7 +115,7 @@ config FSL_CORENET_CF
+ 
+ config FSL_IFC
+ 	bool
+-	depends on FSL_SOC || ARCH_LAYERSCAPE
++	depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
+ 
+ config JZ4780_NEMC
+ 	bool "Ingenic JZ4780 SoC NEMC driver"
 --- a/drivers/memory/fsl_ifc.c
 +++ b/drivers/memory/fsl_ifc.c
 @@ -24,6 +24,7 @@
@@ -311,8 +325,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	},
  	.probe       = fsl_ifc_ctrl_probe,
  	.remove      = fsl_ifc_ctrl_remove,
---- a/drivers/mtd/maps/physmap_of_core.c
-+++ b/drivers/mtd/maps/physmap_of_core.c
+--- a/drivers/mtd/maps/physmap_of.c
++++ b/drivers/mtd/maps/physmap_of.c
 @@ -20,6 +20,7 @@
  #include <linux/mtd/map.h>
  #include <linux/mtd/partitions.h>
@@ -321,16 +335,38 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  #include <linux/of.h>
  #include <linux/of_address.h>
  #include <linux/of_platform.h>
-@@ -205,6 +206,9 @@ static int of_flash_probe(struct platfor
- 		info->list[i].map.bankwidth = be32_to_cpup(width);
- 		info->list[i].map.device_node = dp;
+@@ -209,6 +210,9 @@ static int of_flash_probe(struct platfor
+ 			return err;
+ 		}
  
 +		if (of_property_read_bool(dp->parent, "big-endian"))
 +			info->list[i].map.swap = CFI_BIG_ENDIAN;
 +
- 		err = of_flash_probe_gemini(dev, dp, &info->list[i].map);
- 		if (err)
- 			goto err_out;
+ 		err = -ENOMEM;
+ 		info->list[i].map.virt = ioremap(info->list[i].map.phys,
+ 						 info->list[i].map.size);
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -438,7 +438,7 @@ config MTD_NAND_FSL_ELBC
+ 
+ config MTD_NAND_FSL_IFC
+ 	tristate "NAND support for Freescale IFC controller"
+-	depends on FSL_SOC || ARCH_LAYERSCAPE
++	depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
+ 	select FSL_IFC
+ 	select MEMORY
+ 	help
+--- a/drivers/mtd/nand/fsl_ifc_nand.c
++++ b/drivers/mtd/nand/fsl_ifc_nand.c
+@@ -901,7 +901,7 @@ static int fsl_ifc_chip_init(struct fsl_
+ 		chip->ecc.algo = NAND_ECC_HAMMING;
+ 	}
+ 
+-	if (ctrl->version == FSL_IFC_VERSION_1_1_0)
++	if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
+ 		fsl_ifc_sram_init(priv);
+ 
+ 	/*
 --- a/include/linux/fsl_ifc.h
 +++ b/include/linux/fsl_ifc.h
 @@ -274,6 +274,8 @@
diff --git a/target/linux/layerscape/patches-4.14/707-dpaa-ethernet-support-layerscape.patch b/target/linux/layerscape/patches-4.9/701-sdk_dpaa-support-layerscape.patch
similarity index 99%
rename from target/linux/layerscape/patches-4.14/707-dpaa-ethernet-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/701-sdk_dpaa-support-layerscape.patch
index df96aa5c6..0ea829aef 100644
--- a/target/linux/layerscape/patches-4.14/707-dpaa-ethernet-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/701-sdk_dpaa-support-layerscape.patch
@@ -1,65 +1,36 @@
-From 40b001913c4131b7532beacc13c811a9e39f3758 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:08 +0800
-Subject: [PATCH 13/40] dpaa-ethernet: support layerscape
-This is an integrated patch of dpaa-ethernet for
- layerscape
+From 6cc4cbfd0456c752f9f59d7d07fbb4b514dc6909 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 16:25:00 +0800
+Subject: [PATCH 07/32] sdk_dpaa: support layerscape
+
+This is an integrated patch for layerscape dpaa1-sdk support.
 
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
 Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
-Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Signed-off-by: David S. Miller <davem@davemloft.net>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
-Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
-Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
-Signed-off-by: Jake Moroni <mail@jakemoroni.com>
-Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
-Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com>
-Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
-Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
-Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
-Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
-Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn>
 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
+Signed-off-by: Mathew McBride <matt@traverse.com.au>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- .../net/ethernet/freescale/dpaa/dpaa_eth.c    |  399 +-
- .../ethernet/freescale/dpaa/dpaa_ethtool.c    |    2 +-
- drivers/net/ethernet/freescale/fman/Kconfig   |    1 -
- drivers/net/ethernet/freescale/fman/Makefile  |   12 +-
- .../net/ethernet/freescale/fman/fman_dtsec.c  |   19 +
- .../net/ethernet/freescale/fman/fman_dtsec.h  |    1 +
- .../net/ethernet/freescale/fman/fman_memac.c  |   32 +-
- .../net/ethernet/freescale/fman/fman_memac.h  |    1 +
- .../net/ethernet/freescale/fman/fman_port.c   |    2 +
- .../net/ethernet/freescale/fman/fman_tgec.c   |   33 +-
- .../net/ethernet/freescale/fman/fman_tgec.h   |    1 +
- drivers/net/ethernet/freescale/fman/mac.c     |  149 +-
- drivers/net/ethernet/freescale/fman/mac.h     |    8 +-
- .../net/ethernet/freescale/sdk_dpaa/Kconfig   |  195 +
+ .../net/ethernet/freescale/sdk_dpaa/Kconfig   |  196 +
  .../net/ethernet/freescale/sdk_dpaa/Makefile  |   46 +
  .../ethernet/freescale/sdk_dpaa/dpaa_1588.c   |  580 ++
  .../ethernet/freescale/sdk_dpaa/dpaa_1588.h   |  138 +
  .../freescale/sdk_dpaa/dpaa_debugfs.c         |  180 +
  .../freescale/sdk_dpaa/dpaa_debugfs.h         |   43 +
- .../ethernet/freescale/sdk_dpaa/dpaa_eth.c    | 1223 +++
- .../ethernet/freescale/sdk_dpaa/dpaa_eth.h    |  691 ++
+ .../ethernet/freescale/sdk_dpaa/dpaa_eth.c    | 1224 +++
+ .../ethernet/freescale/sdk_dpaa/dpaa_eth.h    |  687 ++
  .../freescale/sdk_dpaa/dpaa_eth_base.c        |  205 +
  .../freescale/sdk_dpaa/dpaa_eth_base.h        |   49 +
- .../freescale/sdk_dpaa/dpaa_eth_ceetm.c       | 2099 +++++
- .../freescale/sdk_dpaa/dpaa_eth_ceetm.h       |  241 +
- .../freescale/sdk_dpaa/dpaa_eth_common.c      | 1776 ++++
- .../freescale/sdk_dpaa/dpaa_eth_common.h      |  226 +
+ .../freescale/sdk_dpaa/dpaa_eth_ceetm.c       | 2115 +++++
+ .../freescale/sdk_dpaa/dpaa_eth_ceetm.h       |  240 +
+ .../freescale/sdk_dpaa/dpaa_eth_common.c      | 1802 ++++
+ .../freescale/sdk_dpaa/dpaa_eth_common.h      |  225 +
  .../freescale/sdk_dpaa/dpaa_eth_proxy.c       |  381 +
- .../ethernet/freescale/sdk_dpaa/dpaa_eth_sg.c | 1201 +++
+ .../ethernet/freescale/sdk_dpaa/dpaa_eth_sg.c | 1193 +++
  .../freescale/sdk_dpaa/dpaa_eth_sysfs.c       |  278 +
  .../freescale/sdk_dpaa/dpaa_eth_trace.h       |  144 +
- .../freescale/sdk_dpaa/dpaa_ethtool.c         |  542 ++
+ .../freescale/sdk_dpaa/dpaa_ethtool.c         |  544 ++
  .../ethernet/freescale/sdk_dpaa/dpaa_ptp.c    |  291 +
  .../net/ethernet/freescale/sdk_dpaa/mac-api.c |  931 ++
  drivers/net/ethernet/freescale/sdk_dpaa/mac.c |  489 ++
@@ -79,10 +50,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  .../sdk_fman/Peripherals/FM/MAC/fm_mac.h      |  226 +
  .../sdk_fman/Peripherals/FM/MAC/fman_crc32.c  |  119 +
  .../sdk_fman/Peripherals/FM/MAC/fman_crc32.h  |   43 +
- .../sdk_fman/Peripherals/FM/MAC/fman_dtsec.c  |  847 ++
- .../Peripherals/FM/MAC/fman_dtsec_mii_acc.c   |  165 +
+ .../sdk_fman/Peripherals/FM/MAC/fman_dtsec.c  |  845 ++
+ .../Peripherals/FM/MAC/fman_dtsec_mii_acc.c   |  163 +
  .../sdk_fman/Peripherals/FM/MAC/fman_memac.c  |  532 ++
- .../Peripherals/FM/MAC/fman_memac_mii_acc.c   |  215 +
+ .../Peripherals/FM/MAC/fman_memac_mii_acc.c   |  213 +
  .../sdk_fman/Peripherals/FM/MAC/fman_tgec.c   |  367 +
  .../sdk_fman/Peripherals/FM/MAC/memac.c       | 1153 +++
  .../sdk_fman/Peripherals/FM/MAC/memac.h       |  110 +
@@ -118,14 +89,14 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  .../sdk_fman/Peripherals/FM/Pcd/fm_prs.h      |  316 +
  .../sdk_fman/Peripherals/FM/Pcd/fm_replic.c   |  984 +++
  .../sdk_fman/Peripherals/FM/Pcd/fm_replic.h   |  101 +
- .../sdk_fman/Peripherals/FM/Pcd/fman_kg.c     |  890 ++
+ .../sdk_fman/Peripherals/FM/Pcd/fman_kg.c     |  888 ++
  .../sdk_fman/Peripherals/FM/Pcd/fman_prs.c    |  129 +
  .../sdk_fman/Peripherals/FM/Port/Makefile     |   15 +
  .../sdk_fman/Peripherals/FM/Port/fm_port.c    | 6436 ++++++++++++++
  .../sdk_fman/Peripherals/FM/Port/fm_port.h    |  999 +++
  .../Peripherals/FM/Port/fm_port_dsar.h        |  494 ++
  .../sdk_fman/Peripherals/FM/Port/fm_port_im.c |  753 ++
- .../sdk_fman/Peripherals/FM/Port/fman_port.c  | 1570 ++++
+ .../sdk_fman/Peripherals/FM/Port/fman_port.c  | 1568 ++++
  .../sdk_fman/Peripherals/FM/Rtc/Makefile      |   15 +
  .../sdk_fman/Peripherals/FM/Rtc/fm_rtc.c      |  692 ++
  .../sdk_fman/Peripherals/FM/Rtc/fm_rtc.h      |   96 +
@@ -138,7 +109,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  .../freescale/sdk_fman/Peripherals/FM/fm.h    |  648 ++
  .../sdk_fman/Peripherals/FM/fm_ipc.h          |  465 +
  .../sdk_fman/Peripherals/FM/fm_muram.c        |  174 +
- .../freescale/sdk_fman/Peripherals/FM/fman.c  | 1400 +++
+ .../freescale/sdk_fman/Peripherals/FM/fman.c  | 1398 +++
  .../sdk_fman/Peripherals/FM/inc/fm_common.h   | 1214 +++
  .../sdk_fman/Peripherals/FM/inc/fm_hc.h       |   93 +
  .../Peripherals/FM/inc/fm_sp_common.h         |  117 +
@@ -257,7 +228,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  drivers/staging/fsl_qbman/Makefile            |   28 +
  drivers/staging/fsl_qbman/bman_config.c       |  720 ++
  drivers/staging/fsl_qbman/bman_debugfs.c      |  119 +
- drivers/staging/fsl_qbman/bman_driver.c       |  559 ++
+ drivers/staging/fsl_qbman/bman_driver.c       |  575 ++
  drivers/staging/fsl_qbman/bman_high.c         | 1145 +++
  drivers/staging/fsl_qbman/bman_low.h          |  565 ++
  drivers/staging/fsl_qbman/bman_private.h      |  166 +
@@ -271,25 +242,23 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  drivers/staging/fsl_qbman/dpa_sys_arm64.h     |  102 +
  drivers/staging/fsl_qbman/dpa_sys_ppc32.h     |   70 +
  drivers/staging/fsl_qbman/dpa_sys_ppc64.h     |   79 +
- drivers/staging/fsl_qbman/fsl_usdpaa.c        | 2008 +++++
+ drivers/staging/fsl_qbman/fsl_usdpaa.c        | 2007 +++++
  drivers/staging/fsl_qbman/fsl_usdpaa_irq.c    |  289 +
  drivers/staging/fsl_qbman/qbman_driver.c      |   88 +
  drivers/staging/fsl_qbman/qman_config.c       | 1224 +++
  drivers/staging/fsl_qbman/qman_debugfs.c      | 1594 ++++
- drivers/staging/fsl_qbman/qman_driver.c       |  961 +++
+ drivers/staging/fsl_qbman/qman_driver.c       |  977 +++
  drivers/staging/fsl_qbman/qman_high.c         | 5652 ++++++++++++
- drivers/staging/fsl_qbman/qman_low.h          | 1445 ++++
+ drivers/staging/fsl_qbman/qman_low.h          | 1442 ++++
  drivers/staging/fsl_qbman/qman_private.h      |  398 +
  drivers/staging/fsl_qbman/qman_test.c         |   57 +
  drivers/staging/fsl_qbman/qman_test.h         |   45 +
  drivers/staging/fsl_qbman/qman_test_high.c    |  216 +
  .../staging/fsl_qbman/qman_test_hotpotato.c   |  502 ++
  drivers/staging/fsl_qbman/qman_utility.c      |  129 +
- include/linux/fsl/svr.h                       |   97 +
  include/linux/fsl_bman.h                      |  532 ++
  include/linux/fsl_qman.h                      | 3900 +++++++++
  include/linux/fsl_usdpaa.h                    |  372 +
- include/linux/netdev_features.h               |    2 +
  include/uapi/linux/fmd/Kbuild                 |    5 +
  include/uapi/linux/fmd/Peripherals/Kbuild     |    4 +
  .../uapi/linux/fmd/Peripherals/fm_ioctls.h    |  628 ++
@@ -300,8 +269,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  .../fmd/integrations/integration_ioctls.h     |   56 +
  include/uapi/linux/fmd/ioctls.h               |   96 +
  include/uapi/linux/fmd/net_ioctls.h           |  430 +
- net/sched/sch_generic.c                       |    7 +
- 273 files changed, 153944 insertions(+), 229 deletions(-)
+ 257 files changed, 153455 insertions(+)
  create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/Kconfig
  create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/Makefile
  create mode 100644 drivers/net/ethernet/freescale/sdk_dpaa/dpaa_1588.c
@@ -546,7 +514,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  create mode 100644 drivers/staging/fsl_qbman/qman_test_high.c
  create mode 100644 drivers/staging/fsl_qbman/qman_test_hotpotato.c
  create mode 100644 drivers/staging/fsl_qbman/qman_utility.c
- create mode 100644 include/linux/fsl/svr.h
  create mode 100644 include/linux/fsl_bman.h
  create mode 100644 include/linux/fsl_qman.h
  create mode 100644 include/linux/fsl_usdpaa.h
@@ -561,1307 +528,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  create mode 100644 include/uapi/linux/fmd/ioctls.h
  create mode 100644 include/uapi/linux/fmd/net_ioctls.h
 
---- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
-+++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
-@@ -53,6 +53,9 @@
- #include <linux/sort.h>
- #include <soc/fsl/bman.h>
- #include <soc/fsl/qman.h>
-+#if !defined(CONFIG_PPC) && defined(CONFIG_SOC_BUS)
-+#include <linux/sys_soc.h>      /* soc_device_match */
-+#endif
- 
- #include "fman.h"
- #include "fman_port.h"
-@@ -73,6 +76,10 @@ static u16 tx_timeout = 1000;
- module_param(tx_timeout, ushort, 0444);
- MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
- 
-+#ifndef CONFIG_PPC
-+bool dpaa_errata_a010022;
-+#endif
-+
- #define FM_FD_STAT_RX_ERRORS						\
- 	(FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL	| \
- 	 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
-@@ -388,34 +395,19 @@ out:
- 
- static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
- {
--	struct platform_device *of_dev;
- 	struct dpaa_eth_data *eth_data;
--	struct device *dpaa_dev, *dev;
--	struct device_node *mac_node;
-+	struct device *dpaa_dev;
- 	struct mac_device *mac_dev;
- 
- 	dpaa_dev = &pdev->dev;
- 	eth_data = dpaa_dev->platform_data;
--	if (!eth_data)
-+	if (!eth_data) {
-+		dev_err(dpaa_dev, "eth_data missing\n");
- 		return ERR_PTR(-ENODEV);
--
--	mac_node = eth_data->mac_node;
--
--	of_dev = of_find_device_by_node(mac_node);
--	if (!of_dev) {
--		dev_err(dpaa_dev, "of_find_device_by_node(%pOF) failed\n",
--			mac_node);
--		of_node_put(mac_node);
--		return ERR_PTR(-EINVAL);
- 	}
--	of_node_put(mac_node);
--
--	dev = &of_dev->dev;
--
--	mac_dev = dev_get_drvdata(dev);
-+	mac_dev = eth_data->mac_dev;
- 	if (!mac_dev) {
--		dev_err(dpaa_dev, "dev_get_drvdata(%s) failed\n",
--			dev_name(dev));
-+		dev_err(dpaa_dev, "mac_dev missing\n");
- 		return ERR_PTR(-EINVAL);
- 	}
- 
-@@ -472,6 +464,16 @@ static void dpaa_set_rx_mode(struct net_
- 				  err);
- 	}
- 
-+	if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) {
-+		priv->mac_dev->allmulti = !priv->mac_dev->allmulti;
-+		err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac,
-+						  priv->mac_dev->allmulti);
-+		if (err < 0)
-+			netif_err(priv, drv, net_dev,
-+				  "mac_dev->set_allmulti() = %d\n",
-+				  err);
-+	}
-+
- 	err = priv->mac_dev->set_multi(net_dev, priv->mac_dev);
- 	if (err < 0)
- 		netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n",
-@@ -1500,7 +1502,19 @@ static int dpaa_bp_add_8_bufs(const stru
- 	u8 i;
- 
- 	for (i = 0; i < 8; i++) {
-+#ifndef CONFIG_PPC
-+		if (dpaa_errata_a010022) {
-+			struct page *page = alloc_page(GFP_KERNEL);
-+
-+			if (unlikely(!page))
-+				goto release_previous_buffs;
-+			new_buf = page_address(page);
-+		} else {
-+			new_buf = netdev_alloc_frag(dpaa_bp->raw_size);
-+		}
-+#else
- 		new_buf = netdev_alloc_frag(dpaa_bp->raw_size);
-+#endif
- 		if (unlikely(!new_buf)) {
- 			dev_err(dev, "netdev_alloc_frag() failed, size %zu\n",
- 				dpaa_bp->raw_size);
-@@ -1645,9 +1659,13 @@ static struct sk_buff *dpaa_cleanup_tx_f
- 			dma_unmap_page(dev, qm_sg_addr(&sgt[i]),
- 				       qm_sg_entry_get_len(&sgt[i]), dma_dir);
- 		}
--
--		/* Free the page frag that we allocated on Tx */
--		skb_free_frag(phys_to_virt(addr));
-+#ifndef CONFIG_PPC
-+		if (dpaa_errata_a010022)
-+			put_page(virt_to_page(sgt));
-+		else
-+#endif
-+			/* Free the page frag that we allocated on Tx */
-+			skb_free_frag(phys_to_virt(addr));
- 	} else {
- 		dma_unmap_single(dev, addr,
- 				 skb_tail_pointer(skb) - (u8 *)skbh, dma_dir);
-@@ -1739,6 +1757,7 @@ static struct sk_buff *sg_fd_to_skb(cons
- 
- 	/* Iterate through the SGT entries and add data buffers to the skb */
- 	sgt = vaddr + fd_off;
-+	skb = NULL;
- 	for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
- 		/* Extension bit is not supported */
- 		WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
-@@ -1756,7 +1775,7 @@ static struct sk_buff *sg_fd_to_skb(cons
- 		count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
- 		dma_unmap_single(dpaa_bp->dev, sg_addr, dpaa_bp->size,
- 				 DMA_FROM_DEVICE);
--		if (i == 0) {
-+		if (!skb) {
- 			sz = dpaa_bp->size +
- 				SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
- 			skb = build_skb(sg_vaddr, sz);
-@@ -1909,16 +1928,28 @@ static int skb_to_sg_fd(struct dpaa_priv
- 	size_t frag_len;
- 	void *sgt_buf;
- 
--	/* get a page frag to store the SGTable */
--	sz = SKB_DATA_ALIGN(priv->tx_headroom + DPAA_SGT_SIZE);
--	sgt_buf = netdev_alloc_frag(sz);
--	if (unlikely(!sgt_buf)) {
--		netdev_err(net_dev, "netdev_alloc_frag() failed for size %d\n",
--			   sz);
--		return -ENOMEM;
-+#ifndef CONFIG_PPC
-+	if (unlikely(dpaa_errata_a010022)) {
-+		struct page *page = alloc_page(GFP_ATOMIC);
-+		if (unlikely(!page))
-+			return -ENOMEM;
-+		sgt_buf = page_address(page);
-+	} else {
-+#endif
-+		/* get a page frag to store the SGTable */
-+		sz = SKB_DATA_ALIGN(priv->tx_headroom + DPAA_SGT_SIZE);
-+		sgt_buf = netdev_alloc_frag(sz);
-+		if (unlikely(!sgt_buf)) {
-+			netdev_err(net_dev,
-+				   "netdev_alloc_frag() failed for size %d\n",
-+				   sz);
-+			return -ENOMEM;
-+		}
-+#ifndef CONFIG_PPC
- 	}
-+#endif
- 
--	/* Enable L3/L4 hardware checksum computation.
-+ 	/* Enable L3/L4 hardware checksum computation.
- 	 *
- 	 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
- 	 * need to write into the skb.
-@@ -2036,6 +2067,122 @@ static inline int dpaa_xmit(struct dpaa_
- 	return 0;
- }
- 
-+#ifndef CONFIG_PPC
-+/* On LS1043A SoC there is a known erratum ERR010022 that results in split DMA
-+ * transfers in the FMan under certain conditions. This, combined with a fixed
-+ * size FIFO of ongoing DMA transfers that may overflow when a split occurs,
-+ * results in the FMan stalling DMA transfers under high traffic. To avoid the
-+ * problem, one needs to prevent the DMA transfer splits to occur by preparing
-+ * the buffers
-+ */
-+
-+#define DPAA_A010022_HEADROOM	256
-+#define CROSS_4K_BOUND(start, size) \
-+	(((start) + (size)) > (((start) + 0x1000) & ~0xFFF))
-+
-+static bool dpaa_errata_a010022_has_dma_issue(struct sk_buff *skb,
-+					      struct dpaa_priv *priv)
-+{
-+	int nr_frags, i = 0;
-+	 skb_frag_t *frag;
-+
-+	/* Transfers that do not start at 16B aligned addresses will be split;
-+	 * Transfers that cross a 4K page boundary will also be split
-+	 */
-+
-+	/* Check if the frame data is aligned to 16 bytes */
-+	if ((uintptr_t)skb->data % DPAA_FD_DATA_ALIGNMENT)
-+		return true;
-+
-+	/* Check if the headroom crosses a boundary */
-+	if (CROSS_4K_BOUND((uintptr_t)skb->head, skb_headroom(skb)))
-+		return true;
-+
-+	/* Check if the non-paged data crosses a boundary */
-+	if (CROSS_4K_BOUND((uintptr_t)skb->data, skb_headlen(skb)))
-+		return true;
-+
-+	nr_frags = skb_shinfo(skb)->nr_frags;
-+
-+	while (i < nr_frags) {
-+		frag = &skb_shinfo(skb)->frags[i];
-+
-+		/* Check if a paged fragment crosses a boundary from its
-+		 * offset to its end.
-+		 */
-+		if (CROSS_4K_BOUND((uintptr_t)frag->page_offset, frag->size))
-+			return true;
-+
-+		i++;
-+	}
-+
-+	return false;
-+}
-+
-+static struct sk_buff *dpaa_errata_a010022_prevent(struct sk_buff *skb,
-+						   struct dpaa_priv *priv)
-+{
-+	int trans_offset = skb_transport_offset(skb);
-+	int net_offset = skb_network_offset(skb);
-+	int nsize, npage_order, headroom;
-+	struct sk_buff *nskb = NULL;
-+	struct page *npage;
-+	void *npage_addr;
-+
-+	if (!dpaa_errata_a010022_has_dma_issue(skb, priv))
-+		return skb;
-+
-+	/* For the new skb we only need the old one's data (both non-paged and
-+	 * paged). We can skip the old tailroom.
-+	 *
-+	 * The headroom also needs to fit our private info (64 bytes) but we
-+	 * reserve 256 bytes instead in order to guarantee that the data is
-+	 * aligned to 256.
-+	 */
-+	headroom = DPAA_A010022_HEADROOM;
-+	nsize = headroom + skb->len +
-+		SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-+
-+	/* Reserve enough memory to accommodate Jumbo frames */
-+	npage_order = (nsize - 1) / PAGE_SIZE;
-+	npage = alloc_pages(GFP_ATOMIC | __GFP_COMP, npage_order);
-+	if (unlikely(!npage)) {
-+		WARN_ONCE(1, "Memory allocation failure\n");
-+		return NULL;
-+	}
-+	npage_addr = page_address(npage);
-+
-+	nskb = build_skb(npage_addr, nsize);
-+	if (unlikely(!nskb))
-+		goto err;
-+
-+	/* Code borrowed and adapted from skb_copy() */
-+	skb_reserve(nskb, headroom);
-+	skb_put(nskb, skb->len);
-+	if (skb_copy_bits(skb, 0, nskb->data, skb->len)) {
-+		WARN_ONCE(1, "skb parsing failure\n");
-+		goto err;
-+	}
-+	copy_skb_header(nskb, skb);
-+
-+	/* We move the headroom when we align it so we have to reset the
-+	 * network and transport header offsets relative to the new data
-+	 * pointer. The checksum offload relies on these offsets.
-+	 */
-+	skb_set_network_header(nskb, net_offset);
-+	skb_set_transport_header(nskb, trans_offset);
-+
-+	dev_kfree_skb(skb);
-+	return nskb;
-+
-+err:
-+	if (nskb)
-+		dev_kfree_skb(nskb);
-+	put_page(npage);
-+	return NULL;
-+}
-+#endif
-+
- static int dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
- {
- 	const int queue_mapping = skb_get_queue_mapping(skb);
-@@ -2069,19 +2216,32 @@ static int dpaa_start_xmit(struct sk_buf
- 	/* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
- 	 * make sure we don't feed FMan with more fragments than it supports.
- 	 */
--	if (nonlinear &&
--	    likely(skb_shinfo(skb)->nr_frags < DPAA_SGT_MAX_ENTRIES)) {
--		/* Just create a S/G fd based on the skb */
--		err = skb_to_sg_fd(priv, skb, &fd);
--		percpu_priv->tx_frag_skbuffs++;
--	} else {
-+	if (unlikely(nonlinear &&
-+		     (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) {
- 		/* If the egress skb contains more fragments than we support
- 		 * we have no choice but to linearize it ourselves.
- 		 */
--		if (unlikely(nonlinear) && __skb_linearize(skb))
-+		if (__skb_linearize(skb))
-+			goto enomem;
-+
-+		nonlinear = skb_is_nonlinear(skb);
-+	}
-+
-+#ifndef CONFIG_PPC
-+	if (unlikely(dpaa_errata_a010022)) {
-+		skb = dpaa_errata_a010022_prevent(skb, priv);
-+		if (!skb)
- 			goto enomem;
-+		nonlinear = skb_is_nonlinear(skb);
-+	}
-+#endif
- 
--		/* Finally, create a contig FD from this skb */
-+	if (nonlinear) {
-+		/* Just create a S/G fd based on the skb */
-+		err = skb_to_sg_fd(priv, skb, &fd);
-+		percpu_priv->tx_frag_skbuffs++;
-+	} else {
-+		/* Create a contig FD from this skb */
- 		err = skb_to_contig_fd(priv, skb, &fd, &offset);
- 	}
- 	if (unlikely(err < 0))
-@@ -2218,14 +2378,8 @@ static enum qman_cb_dqrr_result rx_error
- 	if (dpaa_eth_napi_schedule(percpu_priv, portal))
- 		return qman_cb_dqrr_stop;
- 
--	if (dpaa_eth_refill_bpools(priv))
--		/* Unable to refill the buffer pool due to insufficient
--		 * system memory. Just release the frame back into the pool,
--		 * otherwise we'll soon end up with an empty buffer pool.
--		 */
--		dpaa_fd_release(net_dev, &dq->fd);
--	else
--		dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
-+	dpaa_eth_refill_bpools(priv);
-+	dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
- 
- 	return qman_cb_dqrr_consume;
- }
-@@ -2439,6 +2593,44 @@ static void dpaa_eth_napi_disable(struct
- 	}
- }
- 
-+static void dpaa_adjust_link(struct net_device *net_dev)
-+{
-+	struct mac_device *mac_dev;
-+	struct dpaa_priv *priv;
-+
-+	priv = netdev_priv(net_dev);
-+	mac_dev = priv->mac_dev;
-+	mac_dev->adjust_link(mac_dev);
-+}
-+
-+static int dpaa_phy_init(struct net_device *net_dev)
-+{
-+	struct mac_device *mac_dev;
-+	struct phy_device *phy_dev;
-+	struct dpaa_priv *priv;
-+
-+	priv = netdev_priv(net_dev);
-+	mac_dev = priv->mac_dev;
-+
-+	phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
-+				 &dpaa_adjust_link, 0,
-+				 mac_dev->phy_if);
-+	if (!phy_dev) {
-+		netif_err(priv, ifup, net_dev, "init_phy() failed\n");
-+		return -ENODEV;
-+	}
-+
-+	/* Remove any features not supported by the controller */
-+	phy_dev->supported &= mac_dev->if_support;
-+	phy_dev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
-+	phy_dev->advertising = phy_dev->supported;
-+
-+	mac_dev->phy_dev = phy_dev;
-+	net_dev->phydev = phy_dev;
-+
-+	return 0;
-+}
-+
- static int dpaa_open(struct net_device *net_dev)
- {
- 	struct mac_device *mac_dev;
-@@ -2449,12 +2641,9 @@ static int dpaa_open(struct net_device *
- 	mac_dev = priv->mac_dev;
- 	dpaa_eth_napi_enable(priv);
- 
--	net_dev->phydev = mac_dev->init_phy(net_dev, priv->mac_dev);
--	if (!net_dev->phydev) {
--		netif_err(priv, ifup, net_dev, "init_phy() failed\n");
--		err = -ENODEV;
-+	err = dpaa_phy_init(net_dev);
-+	if (err)
- 		goto phy_init_failed;
--	}
- 
- 	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
- 		err = fman_port_enable(mac_dev->port[i]);
-@@ -2653,7 +2842,6 @@ static inline u16 dpaa_get_headroom(stru
- static int dpaa_eth_probe(struct platform_device *pdev)
- {
- 	struct dpaa_bp *dpaa_bps[DPAA_BPS_NUM] = {NULL};
--	struct dpaa_percpu_priv *percpu_priv;
- 	struct net_device *net_dev = NULL;
- 	struct dpaa_fq *dpaa_fq, *tmp;
- 	struct dpaa_priv *priv = NULL;
-@@ -2662,7 +2850,13 @@ static int dpaa_eth_probe(struct platfor
- 	int err = 0, i, channel;
- 	struct device *dev;
- 
--	dev = &pdev->dev;
-+	/* device used for DMA mapping */
-+	dev = pdev->dev.parent;
-+	err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(40));
-+	if (err) {
-+		dev_err(dev, "dma_coerce_mask_and_coherent() failed\n");
-+		return err;
-+	}
- 
- 	/* Allocate this early, so we can store relevant information in
- 	 * the private area
-@@ -2670,7 +2864,7 @@ static int dpaa_eth_probe(struct platfor
- 	net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM);
- 	if (!net_dev) {
- 		dev_err(dev, "alloc_etherdev_mq() failed\n");
--		goto alloc_etherdev_mq_failed;
-+		return -ENOMEM;
- 	}
- 
- 	/* Do this here, so we can be verbose early */
-@@ -2686,7 +2880,7 @@ static int dpaa_eth_probe(struct platfor
- 	if (IS_ERR(mac_dev)) {
- 		dev_err(dev, "dpaa_mac_dev_get() failed\n");
- 		err = PTR_ERR(mac_dev);
--		goto mac_probe_failed;
-+		goto free_netdev;
- 	}
- 
- 	/* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
-@@ -2704,21 +2898,13 @@ static int dpaa_eth_probe(struct platfor
- 	priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
- 	priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
- 
--	/* device used for DMA mapping */
--	set_dma_ops(dev, get_dma_ops(&pdev->dev));
--	err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(40));
--	if (err) {
--		dev_err(dev, "dma_coerce_mask_and_coherent() failed\n");
--		goto dev_mask_failed;
--	}
--
- 	/* bp init */
- 	for (i = 0; i < DPAA_BPS_NUM; i++) {
--		int err;
--
- 		dpaa_bps[i] = dpaa_bp_alloc(dev);
--		if (IS_ERR(dpaa_bps[i]))
--			return PTR_ERR(dpaa_bps[i]);
-+		if (IS_ERR(dpaa_bps[i])) {
-+			err = PTR_ERR(dpaa_bps[i]);
-+			goto free_dpaa_bps;
-+		}
- 		/* the raw size of the buffers used for reception */
- 		dpaa_bps[i]->raw_size = bpool_buffer_raw_size(i, DPAA_BPS_NUM);
- 		/* avoid runtime computations by keeping the usable size here */
-@@ -2726,11 +2912,8 @@ static int dpaa_eth_probe(struct platfor
- 		dpaa_bps[i]->dev = dev;
- 
- 		err = dpaa_bp_alloc_pool(dpaa_bps[i]);
--		if (err < 0) {
--			dpaa_bps_free(priv);
--			priv->dpaa_bps[i] = NULL;
--			goto bp_create_failed;
--		}
-+		if (err < 0)
-+			goto free_dpaa_bps;
- 		priv->dpaa_bps[i] = dpaa_bps[i];
- 	}
- 
-@@ -2741,7 +2924,7 @@ static int dpaa_eth_probe(struct platfor
- 	err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
- 	if (err < 0) {
- 		dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
--		goto fq_probe_failed;
-+		goto free_dpaa_bps;
- 	}
- 
- 	priv->mac_dev = mac_dev;
-@@ -2750,12 +2933,12 @@ static int dpaa_eth_probe(struct platfor
- 	if (channel < 0) {
- 		dev_err(dev, "dpaa_get_channel() failed\n");
- 		err = channel;
--		goto get_channel_failed;
-+		goto free_dpaa_bps;
- 	}
- 
- 	priv->channel = (u16)channel;
- 
--	/* Start a thread that will walk the CPUs with affine portals
-+	/* Walk the CPUs with affine portals
- 	 * and add this pool channel to each's dequeue mask.
- 	 */
- 	dpaa_eth_add_channel(priv->channel);
-@@ -2770,20 +2953,20 @@ static int dpaa_eth_probe(struct platfor
- 	err = dpaa_eth_cgr_init(priv);
- 	if (err < 0) {
- 		dev_err(dev, "Error initializing CGR\n");
--		goto tx_cgr_init_failed;
-+		goto free_dpaa_bps;
- 	}
- 
- 	err = dpaa_ingress_cgr_init(priv);
- 	if (err < 0) {
- 		dev_err(dev, "Error initializing ingress CGR\n");
--		goto rx_cgr_init_failed;
-+		goto delete_egress_cgr;
- 	}
- 
- 	/* Add the FQs to the interface, and make them active */
- 	list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
- 		err = dpaa_fq_init(dpaa_fq, false);
- 		if (err < 0)
--			goto fq_alloc_failed;
-+			goto free_dpaa_fqs;
- 	}
- 
- 	priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]);
-@@ -2793,7 +2976,7 @@ static int dpaa_eth_probe(struct platfor
- 	err = dpaa_eth_init_ports(mac_dev, dpaa_bps, DPAA_BPS_NUM, &port_fqs,
- 				  &priv->buf_layout[0], dev);
- 	if (err)
--		goto init_ports_failed;
-+		goto free_dpaa_fqs;
- 
- 	/* Rx traffic distribution based on keygen hashing defaults to on */
- 	priv->keygen_in_use = true;
-@@ -2802,11 +2985,7 @@ static int dpaa_eth_probe(struct platfor
- 	if (!priv->percpu_priv) {
- 		dev_err(dev, "devm_alloc_percpu() failed\n");
- 		err = -ENOMEM;
--		goto alloc_percpu_failed;
--	}
--	for_each_possible_cpu(i) {
--		percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
--		memset(percpu_priv, 0, sizeof(*percpu_priv));
-+		goto free_dpaa_fqs;
- 	}
- 
- 	priv->num_tc = 1;
-@@ -2815,11 +2994,11 @@ static int dpaa_eth_probe(struct platfor
- 	/* Initialize NAPI */
- 	err = dpaa_napi_add(net_dev);
- 	if (err < 0)
--		goto napi_add_failed;
-+		goto delete_dpaa_napi;
- 
- 	err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
- 	if (err < 0)
--		goto netdev_init_failed;
-+		goto delete_dpaa_napi;
- 
- 	dpaa_eth_sysfs_init(&net_dev->dev);
- 
-@@ -2828,32 +3007,21 @@ static int dpaa_eth_probe(struct platfor
- 
- 	return 0;
- 
--netdev_init_failed:
--napi_add_failed:
-+delete_dpaa_napi:
- 	dpaa_napi_del(net_dev);
--alloc_percpu_failed:
--init_ports_failed:
-+free_dpaa_fqs:
- 	dpaa_fq_free(dev, &priv->dpaa_fq_list);
--fq_alloc_failed:
- 	qman_delete_cgr_safe(&priv->ingress_cgr);
- 	qman_release_cgrid(priv->ingress_cgr.cgrid);
--rx_cgr_init_failed:
-+delete_egress_cgr:
- 	qman_delete_cgr_safe(&priv->cgr_data.cgr);
- 	qman_release_cgrid(priv->cgr_data.cgr.cgrid);
--tx_cgr_init_failed:
--get_channel_failed:
-+free_dpaa_bps:
- 	dpaa_bps_free(priv);
--bp_create_failed:
--fq_probe_failed:
--dev_mask_failed:
--mac_probe_failed:
-+free_netdev:
- 	dev_set_drvdata(dev, NULL);
- 	free_netdev(net_dev);
--alloc_etherdev_mq_failed:
--	for (i = 0; i < DPAA_BPS_NUM && dpaa_bps[i]; i++) {
--		if (atomic_read(&dpaa_bps[i]->refs) == 0)
--			devm_kfree(dev, dpaa_bps[i]);
--	}
-+
- 	return err;
- }
- 
-@@ -2890,6 +3058,23 @@ static int dpaa_remove(struct platform_d
- 	return err;
- }
- 
-+#ifndef CONFIG_PPC
-+static bool __init soc_has_errata_a010022(void)
-+{
-+#ifdef CONFIG_SOC_BUS
-+	const struct soc_device_attribute soc_msi_matches[] = {
-+		{ .family = "QorIQ LS1043A",
-+		  .data = NULL },
-+		{ },
-+	};
-+
-+	if (!soc_device_match(soc_msi_matches))
-+		return false;
-+#endif
-+	return true; /* cannot identify SoC or errata applies */
-+}
-+#endif
-+
- static const struct platform_device_id dpaa_devtype[] = {
- 	{
- 		.name = "dpaa-ethernet",
-@@ -2914,6 +3099,10 @@ static int __init dpaa_load(void)
- 
- 	pr_debug("FSL DPAA Ethernet driver\n");
- 
-+#ifndef CONFIG_PPC
-+	/* Detect if the current SoC requires the DMA transfer alignment workaround */
-+	dpaa_errata_a010022 = soc_has_errata_a010022();
-+#endif
- 	/* initialize dpaa_eth mirror values */
- 	dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
- 	dpaa_max_frm = fman_get_max_frm();
---- a/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
-+++ b/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
-@@ -344,7 +344,7 @@ static void dpaa_get_ethtool_stats(struc
- 
- 	/* gather congestion related counters */
- 	cg_num    = 0;
--	cg_status = 0;
-+	cg_status = false;
- 	cg_time   = jiffies_to_msecs(priv->cgr_data.congested_jiffies);
- 	if (qman_query_cgr_congested(&priv->cgr_data.cgr, &cg_status) == 0) {
- 		cg_num    = priv->cgr_data.cgr_congested_count;
---- a/drivers/net/ethernet/freescale/fman/Kconfig
-+++ b/drivers/net/ethernet/freescale/fman/Kconfig
-@@ -2,7 +2,6 @@ config FSL_FMAN
- 	tristate "FMan support"
- 	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
- 	select GENERIC_ALLOCATOR
--	depends on HAS_DMA
- 	select PHYLIB
- 	default n
- 	help
---- a/drivers/net/ethernet/freescale/fman/Makefile
-+++ b/drivers/net/ethernet/freescale/fman/Makefile
-@@ -1,10 +1,10 @@
- # SPDX-License-Identifier: GPL-2.0
- subdir-ccflags-y +=  -I$(srctree)/drivers/net/ethernet/freescale/fman
- 
--obj-$(CONFIG_FSL_FMAN) += fsl_fman.o
--obj-$(CONFIG_FSL_FMAN) += fsl_fman_port.o
--obj-$(CONFIG_FSL_FMAN) += fsl_mac.o
-+obj-$(CONFIG_FSL_FMAN) += fsl_dpaa_fman.o
-+obj-$(CONFIG_FSL_FMAN) += fsl_dpaa_fman_port.o
-+obj-$(CONFIG_FSL_FMAN) += fsl_dpaa_mac.o
- 
--fsl_fman-objs	:= fman_muram.o fman.o fman_sp.o fman_keygen.o
--fsl_fman_port-objs := fman_port.o
--fsl_mac-objs:= mac.o fman_dtsec.o fman_memac.o fman_tgec.o
-+fsl_dpaa_fman-objs	:= fman_muram.o fman.o fman_sp.o fman_keygen.o
-+fsl_dpaa_fman_port-objs := fman_port.o
-+fsl_dpaa_mac-objs:= mac.o fman_dtsec.o fman_memac.o fman_tgec.o
---- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
-+++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
-@@ -1117,6 +1117,25 @@ int dtsec_add_hash_mac_address(struct fm
- 	return 0;
- }
- 
-+int dtsec_set_allmulti(struct fman_mac *dtsec, bool enable)
-+{
-+	u32 tmp;
-+	struct dtsec_regs __iomem *regs = dtsec->regs;
-+
-+	if (!is_init_done(dtsec->dtsec_drv_param))
-+		return -EINVAL;
-+
-+	tmp = ioread32be(&regs->rctrl);
-+	if (enable)
-+		tmp |= RCTRL_MPROM;
-+	else
-+		tmp &= ~RCTRL_MPROM;
-+
-+	iowrite32be(tmp, &regs->rctrl);
-+
-+	return 0;
-+}
-+
- int dtsec_del_hash_mac_address(struct fman_mac *dtsec, enet_addr_t *eth_addr)
- {
- 	struct dtsec_regs __iomem *regs = dtsec->regs;
---- a/drivers/net/ethernet/freescale/fman/fman_dtsec.h
-+++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.h
-@@ -55,5 +55,6 @@ int dtsec_set_exception(struct fman_mac
- int dtsec_add_hash_mac_address(struct fman_mac *dtsec, enet_addr_t *eth_addr);
- int dtsec_del_hash_mac_address(struct fman_mac *dtsec, enet_addr_t *eth_addr);
- int dtsec_get_version(struct fman_mac *dtsec, u32 *mac_version);
-+int dtsec_set_allmulti(struct fman_mac *dtsec, bool enable);
- 
- #endif /* __DTSEC_H */
---- a/drivers/net/ethernet/freescale/fman/fman_memac.c
-+++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
-@@ -350,6 +350,7 @@ struct fman_mac {
- 	struct fman_rev_info fm_rev_info;
- 	bool basex_if;
- 	struct phy_device *pcsphy;
-+	bool allmulti_enabled;
- };
- 
- static void add_addr_in_paddr(struct memac_regs __iomem *regs, u8 *adr,
-@@ -940,6 +941,29 @@ int memac_add_hash_mac_address(struct fm
- 	return 0;
- }
- 
-+int memac_set_allmulti(struct fman_mac *memac, bool enable)
-+{
-+	u32 entry;
-+	struct memac_regs __iomem *regs = memac->regs;
-+
-+	if (!is_init_done(memac->memac_drv_param))
-+		return -EINVAL;
-+
-+	if (enable) {
-+		for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
-+			iowrite32be(entry | HASH_CTRL_MCAST_EN,
-+				    &regs->hashtable_ctrl);
-+	} else {
-+		for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
-+			iowrite32be(entry & ~HASH_CTRL_MCAST_EN,
-+				    &regs->hashtable_ctrl);
-+	}
-+
-+	memac->allmulti_enabled = enable;
-+
-+	return 0;
-+}
-+
- int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr)
- {
- 	struct memac_regs __iomem *regs = memac->regs;
-@@ -963,8 +987,12 @@ int memac_del_hash_mac_address(struct fm
- 			break;
- 		}
- 	}
--	if (list_empty(&memac->multicast_addr_hash->lsts[hash]))
--		iowrite32be(hash & ~HASH_CTRL_MCAST_EN, &regs->hashtable_ctrl);
-+
-+	if (!memac->allmulti_enabled) {
-+		if (list_empty(&memac->multicast_addr_hash->lsts[hash]))
-+			iowrite32be(hash & ~HASH_CTRL_MCAST_EN,
-+				    &regs->hashtable_ctrl);
-+	}
- 
- 	return 0;
- }
---- a/drivers/net/ethernet/freescale/fman/fman_memac.h
-+++ b/drivers/net/ethernet/freescale/fman/fman_memac.h
-@@ -57,5 +57,6 @@ int memac_set_exception(struct fman_mac
- 			enum fman_mac_exceptions exception, bool enable);
- int memac_add_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr);
- int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr);
-+int memac_set_allmulti(struct fman_mac *memac, bool enable);
- 
- #endif /* __MEMAC_H */
---- a/drivers/net/ethernet/freescale/fman/fman_port.c
-+++ b/drivers/net/ethernet/freescale/fman/fman_port.c
-@@ -1347,8 +1347,10 @@ int fman_port_config(struct fman_port *p
- 	switch (port->port_type) {
- 	case FMAN_PORT_TYPE_RX:
- 		set_rx_dflt_cfg(port, params);
-+		/* fall through */
- 	case FMAN_PORT_TYPE_TX:
- 		set_tx_dflt_cfg(port, params, &port->dts_params);
-+		/* fall through */
- 	default:
- 		set_dflt_cfg(port, params);
- 	}
---- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
-+++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
-@@ -217,6 +217,7 @@ struct fman_mac {
- 	struct tgec_cfg *cfg;
- 	void *fm;
- 	struct fman_rev_info fm_rev_info;
-+	bool allmulti_enabled;
- };
- 
- static void set_mac_address(struct tgec_regs __iomem *regs, u8 *adr)
-@@ -564,6 +565,29 @@ int tgec_add_hash_mac_address(struct fma
- 	return 0;
- }
- 
-+int tgec_set_allmulti(struct fman_mac *tgec, bool enable)
-+{
-+	u32 entry;
-+	struct tgec_regs __iomem *regs = tgec->regs;
-+
-+	if (!is_init_done(tgec->cfg))
-+		return -EINVAL;
-+
-+	if (enable) {
-+		for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
-+			iowrite32be(entry | TGEC_HASH_MCAST_EN,
-+				    &regs->hashtable_ctrl);
-+	} else {
-+		for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
-+			iowrite32be(entry & ~TGEC_HASH_MCAST_EN,
-+				    &regs->hashtable_ctrl);
-+	}
-+
-+	tgec->allmulti_enabled = enable;
-+
-+	return 0;
-+}
-+
- int tgec_del_hash_mac_address(struct fman_mac *tgec, enet_addr_t *eth_addr)
- {
- 	struct tgec_regs __iomem *regs = tgec->regs;
-@@ -591,9 +615,12 @@ int tgec_del_hash_mac_address(struct fma
- 			break;
- 		}
- 	}
--	if (list_empty(&tgec->multicast_addr_hash->lsts[hash]))
--		iowrite32be((hash & ~TGEC_HASH_MCAST_EN),
--			    &regs->hashtable_ctrl);
-+
-+	if (!tgec->allmulti_enabled) {
-+		if (list_empty(&tgec->multicast_addr_hash->lsts[hash]))
-+			iowrite32be((hash & ~TGEC_HASH_MCAST_EN),
-+				    &regs->hashtable_ctrl);
-+	}
- 
- 	return 0;
- }
---- a/drivers/net/ethernet/freescale/fman/fman_tgec.h
-+++ b/drivers/net/ethernet/freescale/fman/fman_tgec.h
-@@ -51,5 +51,6 @@ int tgec_set_exception(struct fman_mac *
- int tgec_add_hash_mac_address(struct fman_mac *tgec, enet_addr_t *eth_addr);
- int tgec_del_hash_mac_address(struct fman_mac *tgec, enet_addr_t *eth_addr);
- int tgec_get_version(struct fman_mac *tgec, u32 *mac_version);
-+int tgec_set_allmulti(struct fman_mac *tgec, bool enable);
- 
- #endif /* __TGEC_H */
---- a/drivers/net/ethernet/freescale/fman/mac.c
-+++ b/drivers/net/ethernet/freescale/fman/mac.c
-@@ -57,9 +57,7 @@ struct mac_priv_s {
- 	struct device			*dev;
- 	void __iomem			*vaddr;
- 	u8				cell_index;
--	phy_interface_t			phy_if;
- 	struct fman			*fman;
--	struct device_node		*phy_node;
- 	struct device_node		*internal_phy_node;
- 	/* List of multicast addresses */
- 	struct list_head		mc_addr_list;
-@@ -106,7 +104,7 @@ static void set_fman_mac_params(struct m
- 			     resource_size(mac_dev->res));
- 	memcpy(&params->addr, mac_dev->addr, sizeof(mac_dev->addr));
- 	params->max_speed	= priv->max_speed;
--	params->phy_if		= priv->phy_if;
-+	params->phy_if		= mac_dev->phy_if;
- 	params->basex_if	= false;
- 	params->mac_id		= priv->cell_index;
- 	params->fm		= (void *)priv->fman;
-@@ -419,15 +417,12 @@ void fman_get_pause_cfg(struct mac_devic
- }
- EXPORT_SYMBOL(fman_get_pause_cfg);
- 
--static void adjust_link_void(struct net_device *net_dev)
-+static void adjust_link_void(struct mac_device *mac_dev)
- {
- }
- 
--static void adjust_link_dtsec(struct net_device *net_dev)
-+static void adjust_link_dtsec(struct mac_device *mac_dev)
- {
--	struct device *dev = net_dev->dev.parent;
--	struct dpaa_eth_data *eth_data = dev->platform_data;
--	struct mac_device *mac_dev = eth_data->mac_dev;
- 	struct phy_device *phy_dev = mac_dev->phy_dev;
- 	struct fman_mac *fman_mac;
- 	bool rx_pause, tx_pause;
-@@ -444,14 +439,12 @@ static void adjust_link_dtsec(struct net
- 	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
- 	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
- 	if (err < 0)
--		netdev_err(net_dev, "fman_set_mac_active_pause() = %d\n", err);
-+		dev_err(mac_dev->priv->dev, "fman_set_mac_active_pause() = %d\n",
-+			err);
- }
- 
--static void adjust_link_memac(struct net_device *net_dev)
-+static void adjust_link_memac(struct mac_device *mac_dev)
- {
--	struct device *dev = net_dev->dev.parent;
--	struct dpaa_eth_data *eth_data = dev->platform_data;
--	struct mac_device *mac_dev = eth_data->mac_dev;
- 	struct phy_device *phy_dev = mac_dev->phy_dev;
- 	struct fman_mac *fman_mac;
- 	bool rx_pause, tx_pause;
-@@ -463,60 +456,12 @@ static void adjust_link_memac(struct net
- 	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
- 	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
- 	if (err < 0)
--		netdev_err(net_dev, "fman_set_mac_active_pause() = %d\n", err);
--}
--
--/* Initializes driver's PHY state, and attaches to the PHY.
-- * Returns 0 on success.
-- */
--static struct phy_device *init_phy(struct net_device *net_dev,
--				   struct mac_device *mac_dev,
--				   void (*adj_lnk)(struct net_device *))
--{
--	struct phy_device	*phy_dev;
--	struct mac_priv_s	*priv = mac_dev->priv;
--
--	phy_dev = of_phy_connect(net_dev, priv->phy_node, adj_lnk, 0,
--				 priv->phy_if);
--	if (!phy_dev) {
--		netdev_err(net_dev, "Could not connect to PHY\n");
--		return NULL;
--	}
--
--	/* Remove any features not supported by the controller */
--	phy_dev->supported &= mac_dev->if_support;
--	/* Enable the symmetric and asymmetric PAUSE frame advertisements,
--	 * as most of the PHY drivers do not enable them by default.
--	 */
--	phy_dev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
--	phy_dev->advertising = phy_dev->supported;
--
--	mac_dev->phy_dev = phy_dev;
--
--	return phy_dev;
--}
--
--static struct phy_device *dtsec_init_phy(struct net_device *net_dev,
--					 struct mac_device *mac_dev)
--{
--	return init_phy(net_dev, mac_dev, &adjust_link_dtsec);
--}
--
--static struct phy_device *tgec_init_phy(struct net_device *net_dev,
--					struct mac_device *mac_dev)
--{
--	return init_phy(net_dev, mac_dev, adjust_link_void);
--}
--
--static struct phy_device *memac_init_phy(struct net_device *net_dev,
--					 struct mac_device *mac_dev)
--{
--	return init_phy(net_dev, mac_dev, &adjust_link_memac);
-+		dev_err(mac_dev->priv->dev, "fman_set_mac_active_pause() = %d\n",
-+			err);
- }
- 
- static void setup_dtsec(struct mac_device *mac_dev)
- {
--	mac_dev->init_phy		= dtsec_init_phy;
- 	mac_dev->init			= dtsec_initialization;
- 	mac_dev->set_promisc		= dtsec_set_promiscuous;
- 	mac_dev->change_addr		= dtsec_modify_mac_address;
-@@ -525,17 +470,17 @@ static void setup_dtsec(struct mac_devic
- 	mac_dev->set_tx_pause		= dtsec_set_tx_pause_frames;
- 	mac_dev->set_rx_pause		= dtsec_accept_rx_pause_frames;
- 	mac_dev->set_exception		= dtsec_set_exception;
-+	mac_dev->set_allmulti		= dtsec_set_allmulti;
- 	mac_dev->set_multi		= set_multi;
- 	mac_dev->start			= start;
- 	mac_dev->stop			= stop;
--
-+	mac_dev->adjust_link            = adjust_link_dtsec;
- 	mac_dev->priv->enable		= dtsec_enable;
- 	mac_dev->priv->disable		= dtsec_disable;
- }
- 
- static void setup_tgec(struct mac_device *mac_dev)
- {
--	mac_dev->init_phy		= tgec_init_phy;
- 	mac_dev->init			= tgec_initialization;
- 	mac_dev->set_promisc		= tgec_set_promiscuous;
- 	mac_dev->change_addr		= tgec_modify_mac_address;
-@@ -544,17 +489,17 @@ static void setup_tgec(struct mac_device
- 	mac_dev->set_tx_pause		= tgec_set_tx_pause_frames;
- 	mac_dev->set_rx_pause		= tgec_accept_rx_pause_frames;
- 	mac_dev->set_exception		= tgec_set_exception;
-+	mac_dev->set_allmulti		= tgec_set_allmulti;
- 	mac_dev->set_multi		= set_multi;
- 	mac_dev->start			= start;
- 	mac_dev->stop			= stop;
--
-+	mac_dev->adjust_link            = adjust_link_void;
- 	mac_dev->priv->enable		= tgec_enable;
- 	mac_dev->priv->disable		= tgec_disable;
- }
- 
- static void setup_memac(struct mac_device *mac_dev)
- {
--	mac_dev->init_phy		= memac_init_phy;
- 	mac_dev->init			= memac_initialization;
- 	mac_dev->set_promisc		= memac_set_promiscuous;
- 	mac_dev->change_addr		= memac_modify_mac_address;
-@@ -563,10 +508,11 @@ static void setup_memac(struct mac_devic
- 	mac_dev->set_tx_pause		= memac_set_tx_pause_frames;
- 	mac_dev->set_rx_pause		= memac_accept_rx_pause_frames;
- 	mac_dev->set_exception		= memac_set_exception;
-+	mac_dev->set_allmulti		= memac_set_allmulti;
- 	mac_dev->set_multi		= set_multi;
- 	mac_dev->start			= start;
- 	mac_dev->stop			= stop;
--
-+	mac_dev->adjust_link            = adjust_link_memac;
- 	mac_dev->priv->enable		= memac_enable;
- 	mac_dev->priv->disable		= memac_disable;
- }
-@@ -599,8 +545,7 @@ static const u16 phy2speed[] = {
- };
- 
- static struct platform_device *dpaa_eth_add_device(int fman_id,
--						   struct mac_device *mac_dev,
--						   struct device_node *node)
-+						   struct mac_device *mac_dev)
- {
- 	struct platform_device *pdev;
- 	struct dpaa_eth_data data;
-@@ -613,19 +558,15 @@ static struct platform_device *dpaa_eth_
- 	data.mac_dev = mac_dev;
- 	data.mac_hw_id = priv->cell_index;
- 	data.fman_hw_id = fman_id;
--	data.mac_node = node;
- 
- 	mutex_lock(&eth_lock);
--
- 	pdev = platform_device_alloc("dpaa-ethernet", dpaa_eth_dev_cnt);
- 	if (!pdev) {
- 		ret = -ENOMEM;
- 		goto no_mem;
- 	}
- 
--	pdev->dev.of_node = node;
- 	pdev->dev.parent = priv->dev;
--	set_dma_ops(&pdev->dev, get_dma_ops(priv->dev));
- 
- 	ret = platform_device_add_data(pdev, &data, sizeof(data));
- 	if (ret)
-@@ -676,7 +617,6 @@ static int mac_probe(struct platform_dev
- 	mac_dev = devm_kzalloc(dev, sizeof(*mac_dev), GFP_KERNEL);
- 	if (!mac_dev) {
- 		err = -ENOMEM;
--		dev_err(dev, "devm_kzalloc() = %d\n", err);
- 		goto _return;
- 	}
- 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-@@ -706,9 +646,6 @@ static int mac_probe(struct platform_dev
- 		goto _return;
- 	}
- 
--	/* Register mac_dev */
--	dev_set_drvdata(dev, mac_dev);
--
- 	INIT_LIST_HEAD(&priv->mc_addr_list);
- 
- 	/* Get the FM node */
-@@ -717,7 +654,7 @@ static int mac_probe(struct platform_dev
- 		dev_err(dev, "of_get_parent(%pOF) failed\n",
- 			mac_node);
- 		err = -EINVAL;
--		goto _return_dev_set_drvdata;
-+		goto _return_of_get_parent;
- 	}
- 
- 	of_dev = of_find_device_by_node(dev_node);
-@@ -751,7 +688,7 @@ static int mac_probe(struct platform_dev
- 	if (err < 0) {
- 		dev_err(dev, "of_address_to_resource(%pOF) = %d\n",
- 			mac_node, err);
--		goto _return_dev_set_drvdata;
-+		goto _return_of_get_parent;
- 	}
- 
- 	mac_dev->res = __devm_request_region(dev,
-@@ -761,7 +698,7 @@ static int mac_probe(struct platform_dev
- 	if (!mac_dev->res) {
- 		dev_err(dev, "__devm_request_mem_region(mac) failed\n");
- 		err = -EBUSY;
--		goto _return_dev_set_drvdata;
-+		goto _return_of_get_parent;
- 	}
- 
- 	priv->vaddr = devm_ioremap(dev, mac_dev->res->start,
-@@ -769,16 +706,12 @@ static int mac_probe(struct platform_dev
- 	if (!priv->vaddr) {
- 		dev_err(dev, "devm_ioremap() failed\n");
- 		err = -EIO;
--		goto _return_dev_set_drvdata;
-+		goto _return_of_get_parent;
- 	}
- 
- 	if (!of_device_is_available(mac_node)) {
--		devm_iounmap(dev, priv->vaddr);
--		__devm_release_region(dev, fman_get_mem_region(priv->fman),
--				      res.start, res.end + 1 - res.start);
--		devm_kfree(dev, mac_dev);
--		dev_set_drvdata(dev, NULL);
--		return -ENODEV;
-+		err = -ENODEV;
-+		goto _return_of_get_parent;
- 	}
- 
- 	/* Get the cell-index */
-@@ -786,7 +719,7 @@ static int mac_probe(struct platform_dev
- 	if (err) {
- 		dev_err(dev, "failed to read cell-index for %pOF\n", mac_node);
- 		err = -EINVAL;
--		goto _return_dev_set_drvdata;
-+		goto _return_of_get_parent;
- 	}
- 	priv->cell_index = (u8)val;
- 
-@@ -795,7 +728,7 @@ static int mac_probe(struct platform_dev
- 	if (!mac_addr) {
- 		dev_err(dev, "of_get_mac_address(%pOF) failed\n", mac_node);
- 		err = -EINVAL;
--		goto _return_dev_set_drvdata;
-+		goto _return_of_get_parent;
- 	}
- 	memcpy(mac_dev->addr, mac_addr, sizeof(mac_dev->addr));
- 
-@@ -805,14 +738,14 @@ static int mac_probe(struct platform_dev
- 		dev_err(dev, "of_count_phandle_with_args(%pOF, fsl,fman-ports) failed\n",
- 			mac_node);
- 		err = nph;
--		goto _return_dev_set_drvdata;
-+		goto _return_of_get_parent;
- 	}
- 
- 	if (nph != ARRAY_SIZE(mac_dev->port)) {
- 		dev_err(dev, "Not supported number of fman-ports handles of mac node %pOF from device tree\n",
- 			mac_node);
- 		err = -EINVAL;
--		goto _return_dev_set_drvdata;
-+		goto _return_of_get_parent;
- 	}
- 
- 	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
-@@ -851,13 +784,13 @@ static int mac_probe(struct platform_dev
- 			 mac_node);
- 		phy_if = PHY_INTERFACE_MODE_SGMII;
- 	}
--	priv->phy_if = phy_if;
-+	mac_dev->phy_if = phy_if;
- 
--	priv->speed		= phy2speed[priv->phy_if];
-+	priv->speed		= phy2speed[mac_dev->phy_if];
- 	priv->max_speed		= priv->speed;
- 	mac_dev->if_support	= DTSEC_SUPPORTED;
- 	/* We don't support half-duplex in SGMII mode */
--	if (priv->phy_if == PHY_INTERFACE_MODE_SGMII)
-+	if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII)
- 		mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
- 					SUPPORTED_100baseT_Half);
- 
-@@ -866,30 +799,31 @@ static int mac_probe(struct platform_dev
- 		mac_dev->if_support |= SUPPORTED_1000baseT_Full;
- 
- 	/* The 10G interface only supports one mode */
--	if (priv->phy_if == PHY_INTERFACE_MODE_XGMII)
-+	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
- 		mac_dev->if_support = SUPPORTED_10000baseT_Full;
- 
- 	/* Get the rest of the PHY information */
--	priv->phy_node = of_parse_phandle(mac_node, "phy-handle", 0);
--	if (!priv->phy_node && of_phy_is_fixed_link(mac_node)) {
-+	mac_dev->phy_node = of_parse_phandle(mac_node, "phy-handle", 0);
-+	if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
- 		struct phy_device *phy;
- 
- 		err = of_phy_register_fixed_link(mac_node);
- 		if (err)
--			goto _return_dev_set_drvdata;
-+			goto _return_of_get_parent;
- 
- 		priv->fixed_link = kzalloc(sizeof(*priv->fixed_link),
- 					   GFP_KERNEL);
- 		if (!priv->fixed_link) {
- 			err = -ENOMEM;
--			goto _return_dev_set_drvdata;
-+			goto _return_of_get_parent;
- 		}
- 
--		priv->phy_node = of_node_get(mac_node);
--		phy = of_phy_find_device(priv->phy_node);
-+		mac_dev->phy_node = of_node_get(mac_node);
-+		phy = of_phy_find_device(mac_dev->phy_node);
- 		if (!phy) {
- 			err = -EINVAL;
--			goto _return_dev_set_drvdata;
-+			of_node_put(mac_dev->phy_node);
-+			goto _return_of_get_parent;
- 		}
- 
- 		priv->fixed_link->link = phy->link;
-@@ -904,8 +838,8 @@ static int mac_probe(struct platform_dev
- 	err = mac_dev->init(mac_dev);
- 	if (err < 0) {
- 		dev_err(dev, "mac_dev->init() = %d\n", err);
--		of_node_put(priv->phy_node);
--		goto _return_dev_set_drvdata;
-+		of_node_put(mac_dev->phy_node);
-+		goto _return_of_get_parent;
- 	}
- 
- 	/* pause frame autonegotiation enabled */
-@@ -926,7 +860,7 @@ static int mac_probe(struct platform_dev
- 		 mac_dev->addr[0], mac_dev->addr[1], mac_dev->addr[2],
- 		 mac_dev->addr[3], mac_dev->addr[4], mac_dev->addr[5]);
- 
--	priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev, mac_node);
-+	priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev);
- 	if (IS_ERR(priv->eth_dev)) {
- 		dev_err(dev, "failed to add Ethernet platform device for MAC %d\n",
- 			priv->cell_index);
-@@ -937,9 +871,8 @@ static int mac_probe(struct platform_dev
- 
- _return_of_node_put:
- 	of_node_put(dev_node);
--_return_dev_set_drvdata:
-+_return_of_get_parent:
- 	kfree(priv->fixed_link);
--	dev_set_drvdata(dev, NULL);
- _return:
- 	return err;
- }
---- a/drivers/net/ethernet/freescale/fman/mac.h
-+++ b/drivers/net/ethernet/freescale/fman/mac.h
-@@ -50,6 +50,8 @@ struct mac_device {
- 	struct fman_port	*port[2];
- 	u32			 if_support;
- 	struct phy_device	*phy_dev;
-+	phy_interface_t		phy_if;
-+	struct device_node	*phy_node;
- 
- 	bool autoneg_pause;
- 	bool rx_pause_req;
-@@ -57,14 +59,15 @@ struct mac_device {
- 	bool rx_pause_active;
- 	bool tx_pause_active;
- 	bool promisc;
-+	bool allmulti;
- 
--	struct phy_device *(*init_phy)(struct net_device *net_dev,
--				       struct mac_device *mac_dev);
- 	int (*init)(struct mac_device *mac_dev);
- 	int (*start)(struct mac_device *mac_dev);
- 	int (*stop)(struct mac_device *mac_dev);
-+	void (*adjust_link)(struct mac_device *mac_dev);
- 	int (*set_promisc)(struct fman_mac *mac_dev, bool enable);
- 	int (*change_addr)(struct fman_mac *mac_dev, enet_addr_t *enet_addr);
-+	int (*set_allmulti)(struct fman_mac *mac_dev, bool enable);
- 	int (*set_multi)(struct net_device *net_dev,
- 			 struct mac_device *mac_dev);
- 	int (*set_rx_pause)(struct fman_mac *mac_dev, bool en);
-@@ -82,7 +85,6 @@ struct mac_device {
- };
- 
- struct dpaa_eth_data {
--	struct device_node *mac_node;
- 	struct mac_device *mac_dev;
- 	int mac_hw_id;
- 	int fman_hw_id;
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/Kconfig
-@@ -0,0 +1,195 @@
+@@ -0,0 +1,196 @@
 +menuconfig FSL_SDK_DPAA_ETH
 +	tristate "DPAA Ethernet"
 +	depends on (FSL_SOC || ARM64 || ARM) && FSL_SDK_BMAN && FSL_SDK_QMAN && FSL_SDK_FMAN && !FSL_DPAA_ETH
@@ -1944,6 +613,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	  significantly the driver's memory footprint and may even deplete
 +	  the system memory. Also, the skb truesize is altered and messages
 +	  from the stack that warn against this are bypassed.
++	  This option is not available on LS1043.
 +
 +config FSL_DPAA_TS
 +	bool "Linux compliant timestamping"
@@ -3061,7 +1731,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif /* DPAA_DEBUGFS_H_ */
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c
-@@ -0,0 +1,1223 @@
+@@ -0,0 +1,1224 @@
 +/* Copyright 2008-2013 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -3745,6 +2415,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#ifdef CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE
 +	.ndo_select_queue = dpa_select_queue,
 +#endif
++	.ndo_change_mtu = dpa_change_mtu,
 +	.ndo_set_rx_mode = dpa_set_rx_mode,
 +	.ndo_init = dpa_ndo_init,
 +	.ndo_set_features = dpa_set_features,
@@ -3821,10 +2492,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	net_dev->mem_start = priv->mac_dev->res->start;
 +	net_dev->mem_end = priv->mac_dev->res->end;
 +
-+	/* Configure the maximum MTU according to the FMan's MAXFRM */
-+	net_dev->min_mtu = ETH_MIN_MTU;
-+	net_dev->max_mtu = dpa_get_max_mtu();
-+
 +	net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 +		NETIF_F_LLTX);
 +
@@ -3843,8 +2510,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	net_dev->features |= NETIF_F_HW_ACCEL_MQ;
 +
 +#ifndef CONFIG_PPC
-+	/* Due to the A010022 FMan errata, we can not use S/G frames. We need
-+	 * to stop advertising S/G and GSO support.
++	/* Due to the A010022 FMan errata, we can not use contig frames larger
++	 * than 4K, nor S/G frames. We need to stop advertising S/G and GSO
++	 * support.
 +	 */
 +	if (unlikely(dpaa_errata_a010022)) {
 +		net_dev->hw_features &= ~NETIF_F_SG;
@@ -4047,6 +2715,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	/* We only want to use jumbo frame optimization if we actually have
 +	 * L2 MAX FRM set for jumbo frames as well.
 +	 */
++#ifndef CONFIG_PPC
++	if (likely(!dpaa_errata_a010022))
++#endif
 +	if(fm_get_max_frm() < 9600)
 +		dev_warn(dev,
 +			"Invalid configuration: if jumbo frames support is on, FSL_FM_MAX_FRAME_SIZE should be set to 9600\n");
@@ -4287,7 +2958,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +module_exit(dpa_unload);
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.h
-@@ -0,0 +1,691 @@
+@@ -0,0 +1,687 @@
 +/* Copyright 2008-2012 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -4962,8 +3633,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +/* LS1043A SoC has a HW issue regarding FMan DMA transactions; The issue
 + * manifests itself at high traffic rates when frames cross 4K memory
 + * boundaries or when they are not aligned to 16 bytes; For the moment, we
-+ * use a SW workaround that realigns frames to 256 bytes. Scatter/Gather
-+ * frames aren't supported on egress.
++ * use a SW workaround to avoid frames larger than 4K or that exceed 4K
++ * alignments and to realign the frames to 16 bytes.
 + */
 +
 +#ifndef CONFIG_PPC
@@ -4972,10 +3643,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#define HAS_DMA_ISSUE(start, size) \
 +	(((uintptr_t)(start) + (size)) > \
 +	 (((uintptr_t)(start) + 0x1000) & ~0xFFF))
-+/* The headroom needs to accommodate our private data (64 bytes) but
-+ * we reserve 256 bytes instead to guarantee 256 data alignment.
-+ */
-+#define DPAA_A010022_HEADROOM	256
 +#endif  /* !CONFIG_PPC */
 +
 +#endif	/* __DPA_H */
@@ -5241,7 +3908,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif /* __DPAA_ETH_BASE_H */
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_ceetm.c
-@@ -0,0 +1,2099 @@
+@@ -0,0 +1,2115 @@
 +/* Copyright 2008-2016 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -5752,7 +4419,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		netif_tx_wake_all_queues(dev);
 +	}
 +
-+	tcf_block_put(cl->block);
++	tcf_destroy_chain(&cl->filter_list);
 +	kfree(cl);
 +}
 +
@@ -5769,13 +4436,11 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		 __func__, sch->handle);
 +
 +	/* All filters need to be removed before destroying the classes */
-+	tcf_block_put(priv->block);
++	tcf_destroy_chain(&priv->filter_list);
 +
 +	for (i = 0; i < priv->clhash.hashsize; i++) {
-+		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode) {
-+			tcf_block_put(cl->block);
-+			cl->block = NULL;
-+		}
++		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode)
++			tcf_destroy_chain(&cl->filter_list);
 +	}
 +
 +	for (i = 0; i < priv->clhash.hashsize; i++) {
@@ -5931,7 +4596,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	/* Validate inputs */
 +	if (sch->parent != TC_H_ROOT) {
 +		pr_err("CEETM: a root ceetm qdisc can not be attached to a class\n");
-+		tcf_block_put(priv->block);
++		tcf_destroy_chain(&priv->filter_list);
 +		qdisc_class_hash_destroy(&priv->clhash);
 +		return -EINVAL;
 +	}
@@ -6119,6 +4784,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		}
 +
 +		child_cl->common.classid = TC_H_MAKE(sch->handle, (i + 1));
++		child_cl->refcnt = 1;
 +		child_cl->parent = sch;
 +		child_cl->type = CEETM_PRIO;
 +		child_cl->shaped = priv->shaped;
@@ -6328,6 +4994,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		}
 +
 +		child_cl->common.classid = TC_H_MAKE(sch->handle, (i + 1));
++		child_cl->refcnt = 1;
 +		child_cl->parent = sch;
 +		child_cl->type = CEETM_WBFS;
 +		child_cl->shaped = priv->shaped;
@@ -6397,11 +5064,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return -EINVAL;
 +	}
 +
-+	ret = tcf_block_get(&priv->block, &priv->filter_list);
-+	if (ret)
-+		return ret;
-+
-+	ret = nla_parse_nested(tb, TCA_CEETM_QOPS, opt, ceetm_policy, NULL);
++	ret = nla_parse_nested(tb, TCA_CEETM_QOPS, opt, ceetm_policy);
 +	if (ret < 0) {
 +		pr_err(KBUILD_BASENAME " : %s : tc error\n", __func__);
 +		return ret;
@@ -6574,7 +5237,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
 +
-+	ret = nla_parse_nested(tb, TCA_CEETM_QOPS, opt, ceetm_policy, NULL);
++	ret = nla_parse_nested(tb, TCA_CEETM_QOPS, opt, ceetm_policy);
 +	if (ret < 0) {
 +		pr_err(KBUILD_BASENAME " : %s : tc error\n", __func__);
 +		return ret;
@@ -6641,9 +5304,29 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	priv->root.qdiscs = NULL;
 +}
 +
-+static unsigned long ceetm_cls_search(struct Qdisc *sch, u32 handle)
++static unsigned long ceetm_cls_get(struct Qdisc *sch, u32 classid)
 +{
-+	return (unsigned long)ceetm_find(handle, sch);
++	struct ceetm_class *cl;
++
++	pr_debug(KBUILD_BASENAME " : %s : classid %X from qdisc %X\n",
++		 __func__, classid, sch->handle);
++	cl = ceetm_find(classid, sch);
++
++	if (cl)
++		cl->refcnt++; /* Will decrement in put() */
++	return (unsigned long)cl;
++}
++
++static void ceetm_cls_put(struct Qdisc *sch, unsigned long arg)
++{
++	struct ceetm_class *cl = (struct ceetm_class *)arg;
++
++	pr_debug(KBUILD_BASENAME " : %s : classid %X from qdisc %X\n",
++		 __func__, cl->common.classid, sch->handle);
++	cl->refcnt--;
++
++	if (cl->refcnt == 0)
++		ceetm_cls_destroy(sch, cl);
 +}
 +
 +static int ceetm_cls_change_root(struct ceetm_class *cl,
@@ -6793,7 +5476,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return -EINVAL;
 +	}
 +
-+	err = nla_parse_nested(tb, TCA_CEETM_COPT, opt, ceetm_policy, NULL);
++	err = nla_parse_nested(tb, TCA_CEETM_COPT, opt, ceetm_policy);
 +	if (err < 0) {
 +		pr_err(KBUILD_BASENAME " : %s : tc error\n", __func__);
 +		return -EINVAL;
@@ -6851,12 +5534,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	if (!cl)
 +		return -ENOMEM;
 +
-+	err = tcf_block_get(&cl->block, &cl->filter_list);
-+	if (err) {
-+		kfree(cl);
-+		return err;
-+	}
-+
 +	cl->type = copt->type;
 +	cl->shaped = copt->shaped;
 +	cl->root.rate = copt->rate;
@@ -6864,6 +5541,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	cl->root.tbl = copt->tbl;
 +
 +	cl->common.classid = classid;
++	cl->refcnt = 1;
 +	cl->parent = sch;
 +	cl->root.child = NULL;
 +	cl->root.wbfs_grp_a = false;
@@ -6920,7 +5598,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		pr_err(KBUILD_BASENAME " : %s : failed to release the channel %d\n",
 +		       __func__, channel->idx);
 +claim_err:
-+	tcf_block_put(cl->block);
 +	kfree(cl);
 +	return err;
 +}
@@ -7019,9 +5696,15 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	sch_tree_lock(sch);
 +	qdisc_class_hash_remove(&priv->clhash, &cl->common);
++	cl->refcnt--;
++
++	/* The refcnt should be at least 1 since we have incremented it in
++	 * get(). Will decrement again in put() where we will call destroy()
++	 * to actually free the memory if it reaches 0.
++	 */
++	WARN_ON(cl->refcnt == 0);
 +
 +	sch_tree_unlock(sch);
-+	ceetm_cls_destroy(sch, cl);
 +	return 0;
 +}
 +
@@ -7109,15 +5792,15 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	return gnet_stats_copy_app(d, &xstats, sizeof(xstats));
 +}
 +
-+static struct tcf_block *ceetm_tcf_block(struct Qdisc *sch, unsigned long arg)
++static struct tcf_proto **ceetm_tcf_chain(struct Qdisc *sch, unsigned long arg)
 +{
 +	struct ceetm_qdisc *priv = qdisc_priv(sch);
 +	struct ceetm_class *cl = (struct ceetm_class *)arg;
-+	struct tcf_block *block = cl ? cl->block : priv->block;
++	struct tcf_proto **fl = cl ? &cl->filter_list : &priv->filter_list;
 +
 +	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__,
 +		 cl ? cl->common.classid : 0, sch->handle);
-+	return block;
++	return fl;
 +}
 +
 +static unsigned long ceetm_tcf_bind(struct Qdisc *sch, unsigned long parent,
@@ -7141,11 +5824,12 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +const struct Qdisc_class_ops ceetm_cls_ops = {
 +	.graft		=	ceetm_cls_graft,
 +	.leaf		=	ceetm_cls_leaf,
-+	.find		=	ceetm_cls_search,
++	.get		=	ceetm_cls_get,
++	.put		=	ceetm_cls_put,
 +	.change		=	ceetm_cls_change,
 +	.delete		=	ceetm_cls_delete,
 +	.walk		=	ceetm_cls_walk,
-+	.tcf_block	=	ceetm_tcf_block,
++	.tcf_chain	=	ceetm_tcf_chain,
 +	.bind_tcf	=	ceetm_tcf_bind,
 +	.unbind_tcf	=	ceetm_tcf_unbind,
 +	.dump		=	ceetm_cls_dump,
@@ -7177,12 +5861,11 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	*qerr = NET_XMIT_SUCCESS | __NET_XMIT_BYPASS;
 +	tcf = priv->filter_list;
-+	while (tcf && (result = tcf_classify(skb, tcf, &res, false)) >= 0) {
++	while (tcf && (result = tc_classify(skb, tcf, &res, false)) >= 0) {
 +#ifdef CONFIG_NET_CLS_ACT
 +		switch (result) {
 +		case TC_ACT_QUEUED:
 +		case TC_ACT_STOLEN:
-+		case TC_ACT_TRAP:
 +			*qerr = NET_XMIT_SUCCESS | __NET_XMIT_STOLEN;
 +		case TC_ACT_SHOT:
 +			/* No valid class found due to action */
@@ -7343,7 +6026,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +module_exit(ceetm_unregister);
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_ceetm.h
-@@ -0,0 +1,241 @@
+@@ -0,0 +1,240 @@
 +/* Copyright 2008-2016 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -7489,7 +6172,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	};
 +	struct Qdisc_class_hash clhash;
 +	struct tcf_proto *filter_list; /* qdisc attached filters */
-+	struct tcf_block *block;
 +};
 +
 +/* CEETM Qdisc configuration parameters */
@@ -7538,8 +6220,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +struct ceetm_class {
 +	struct Qdisc_class_common common;
++	int refcnt; /* usage count of this class */
 +	struct tcf_proto *filter_list; /* class attached filters */
-+	struct tcf_block *block;
 +	struct Qdisc *parent;
 +	struct qm_ceetm_channel *ch;
 +	bool shaped;
@@ -7587,7 +6269,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.c
-@@ -0,0 +1,1776 @@
+@@ -0,0 +1,1802 @@
 +/* Copyright 2008-2013 Freescale Semiconductor, Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -7829,8 +6511,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + * Calculates the statistics for the given device by adding the statistics
 + * collected by each CPU.
 + */
-+void __cold
-+dpa_get_stats64(struct net_device *net_dev,
++struct rtnl_link_stats64 __cold
++*dpa_get_stats64(struct net_device *net_dev,
 +		struct rtnl_link_stats64 *stats)
 +{
 +	struct dpa_priv_s *priv = netdev_priv(net_dev);
@@ -7848,9 +6530,35 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		for (j = 0; j < numstats; j++)
 +			netstats[j] += cpustats[j];
 +	}
++	return stats;
 +}
 +EXPORT_SYMBOL(dpa_get_stats64);
 +
++int dpa_change_mtu(struct net_device *net_dev, int new_mtu)
++{
++	int max_mtu = dpa_get_max_mtu();
++
++#ifndef CONFIG_PPC
++	/* Due to the A010022 FMan errata, we can not use contig frames larger
++	 * than 4K, nor S/G frames. We need to prevent the user from setting a
++	 * large MTU.
++	 */
++	if (unlikely(dpaa_errata_a010022))
++		max_mtu = DPA_BP_RAW_SIZE;
++#endif
++
++	/* Make sure we don't exceed the Ethernet controller's MAXFRM */
++	if (new_mtu < 68 || new_mtu > max_mtu) {
++		netdev_err(net_dev, "Invalid L3 mtu %d (must be between %d and %d).\n",
++				new_mtu, 68, max_mtu);
++		return -EINVAL;
++	}
++	net_dev->mtu = new_mtu;
++
++	return 0;
++}
++EXPORT_SYMBOL(dpa_change_mtu);
++
 +/* .ndo_init callback */
 +int dpa_ndo_init(struct net_device *net_dev)
 +{
@@ -9366,7 +8074,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.h
-@@ -0,0 +1,226 @@
+@@ -0,0 +1,225 @@
 +/* Copyright 2008-2013 Freescale Semiconductor, Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -9424,12 +8132,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	fm_set_##type##_port_params(port, &param); \
 +}
 +
-+/* The SGT needs to be 256 bytes long. Even if the table has only one entry,
-+ * the FMan will read 256 bytes from its start.
-+ */
-+#define DPA_SGT_SIZE 256
 +#define DPA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
 +
++#define DPA_SGT_ENTRIES_THRESHOLD	DPA_SGT_MAX_ENTRIES
++
 +#define DPA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
 +
 +#define DPA_RX_PCD_HI_PRIO_FQ_INIT_FAIL(dpa_fq, _errno) \
@@ -9511,9 +8217,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +int __cold dpa_start(struct net_device *net_dev);
 +int __cold dpa_stop(struct net_device *net_dev);
 +void __cold dpa_timeout(struct net_device *net_dev);
-+void __cold
-+dpa_get_stats64(struct net_device *net_dev,
++struct rtnl_link_stats64 __cold
++*dpa_get_stats64(struct net_device *net_dev,
 +		struct rtnl_link_stats64 *stats);
++int dpa_change_mtu(struct net_device *net_dev, int new_mtu);
 +int dpa_ndo_init(struct net_device *net_dev);
 +int dpa_set_features(struct net_device *dev, netdev_features_t features);
 +netdev_features_t dpa_fix_features(struct net_device *dev,
@@ -9979,7 +8686,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +module_exit(dpa_proxy_unload);
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_sg.c
-@@ -0,0 +1,1201 @@
+@@ -0,0 +1,1193 @@
 +/* Copyright 2012 Freescale Semiconductor Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -10064,8 +8771,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +static int _dpa_bp_add_8_bufs(const struct dpa_bp *dpa_bp)
 +{
-+	void *new_buf, *fman_buf;
 +	struct bm_buffer bmb[8];
++	void *new_buf;
 +	dma_addr_t addr;
 +	uint8_t i;
 +	struct device *dev = dpa_bp->dev;
@@ -10095,37 +8802,21 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +		if (unlikely(!new_buf))
 +			goto netdev_alloc_failed;
-+		new_buf = PTR_ALIGN(new_buf, SMP_CACHE_BYTES);
++		new_buf = PTR_ALIGN(new_buf + SMP_CACHE_BYTES, SMP_CACHE_BYTES);
 +
-+		/* Apart from the buffer that will be used by the FMan, the
-+		 * skb also guarantees enough space to hold the backpointer
-+		 * in the headroom and the shared info at the end.
-+		 */
-+		skb = build_skb(new_buf,
-+				SMP_CACHE_BYTES + DPA_SKB_SIZE(dpa_bp->size) +
-+				SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
++		skb = build_skb(new_buf, DPA_SKB_SIZE(dpa_bp->size) +
++			SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
 +		if (unlikely(!skb)) {
 +			put_page(virt_to_head_page(new_buf));
 +			goto build_skb_failed;
 +		}
 +
-+		/* Reserve SMP_CACHE_BYTES in the skb's headroom to store the
-+		 * backpointer. This area will not be synced to, or
-+		 * overwritten by, the FMan.
++		/* Store the skb back-pointer before the start of the buffer.
++		 * Otherwise it will be overwritten by the FMan.
 +		 */
-+		skb_reserve(skb, SMP_CACHE_BYTES);
++		DPA_WRITE_SKB_PTR(skb, skbh, new_buf, -1);
 +
-+		/* We don't sync the first SMP_CACHE_BYTES of the buffer to
-+		 * the FMan. The skb backpointer is stored at the end of the
-+		 * reserved headroom. Otherwise it will be overwritten by the
-+		 * FMan.
-+		 * The buffer synced with the FMan starts right after the
-+		 * reserved headroom.
-+		 */
-+		fman_buf = new_buf + SMP_CACHE_BYTES;
-+		DPA_WRITE_SKB_PTR(skb, skbh, fman_buf, -1);
-+
-+		addr = dma_map_single(dev, fman_buf,
++		addr = dma_map_single(dev, new_buf,
 +				dpa_bp->size, DMA_BIDIRECTIONAL);
 +		if (unlikely(dma_mapping_error(dev, addr)))
 +			goto dma_map_failed;
@@ -10244,8 +8935,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	if (unlikely(fd->format == qm_fd_sg)) {
 +		nr_frags = skb_shinfo(skb)->nr_frags;
-+		dma_unmap_single(dpa_bp->dev, addr,
-+				 dpa_fd_offset(fd) + DPA_SGT_SIZE,
++		dma_unmap_single(dpa_bp->dev, addr, dpa_fd_offset(fd) +
++				 sizeof(struct qm_sg_entry) * (1 + nr_frags),
 +				 dma_dir);
 +
 +		/* The sgt buffer has been allocated with netdev_alloc_frag(),
@@ -10405,6 +9096,12 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	 * warn us that the frame length is larger than the truesize. We
 +	 * bypass the warning.
 +	 */
++#ifndef CONFIG_PPC
++	/* We do not support Jumbo frames on LS1043 and thus we edit
++	 * the skb truesize only when the 4k errata is not present.
++	 */
++	if (likely(!dpaa_errata_a010022))
++#endif
 +	skb->truesize = SKB_TRUESIZE(dpa_fd_length(fd));
 +#endif
 +
@@ -10475,6 +9172,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +				 DMA_BIDIRECTIONAL);
 +		if (i == 0) {
 +			DPA_READ_SKB_PTR(skb, skbh, sg_vaddr, -1);
++			DPA_BUG_ON(skb->head != sg_vaddr);
 +#ifdef CONFIG_FSL_DPAA_1588
 +			if (priv->tsu && priv->tsu->valid &&
 +			    priv->tsu->hwts_rx_en_ioctl)
@@ -10800,30 +9498,35 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +{
 +	int trans_offset = skb_transport_offset(skb);
 +	int net_offset = skb_network_offset(skb);
-+	int nsize, headroom, npage_order;
 +	struct sk_buff *nskb = NULL;
++	int nsize, headroom;
 +	struct page *npage;
 +	void *npage_addr;
 +
-+	headroom = DPAA_A010022_HEADROOM;
++	/* Guarantee the minimum required headroom */
++	if (skb_headroom(skb) >= priv->tx_headroom)
++		headroom = skb_headroom(skb);
++	else
++		headroom = priv->tx_headroom;
 +
-+	/* For the new skb we only need the old one's data (both non-paged and
-+	 * paged). We can skip the old tailroom.
-+	 *
-+	 * Make sure the skb_shinfo is cache-line aligned.
-+	 */
-+	nsize = SMP_CACHE_BYTES + DPA_SKB_SIZE(headroom + skb->len) +
-+		SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
-+
-+	/* Reserve enough memory to accommodate Jumbo frames */
-+	npage_order = (nsize - 1) / PAGE_SIZE;
-+	npage = alloc_pages(GFP_ATOMIC | __GFP_COMP, npage_order);
++	npage = alloc_page(GFP_ATOMIC);
 +	if (unlikely(!npage)) {
 +		WARN_ONCE(1, "Memory allocation failure\n");
 +		return NULL;
 +	}
 +	npage_addr = page_address(npage);
 +
++	/* For the new skb we only need the old one's data (both non-paged and
++	 * paged) and a headroom large enough to fit our private info. We can
++	 * skip the old tailroom.
++	 *
++	 * Make sure the new linearized buffer will not exceed a page's size.
++	 */
++	nsize = headroom + skb->len +
++		SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
++	if (unlikely(nsize > 4096))
++		goto err;
++
 +	nskb = build_skb(npage_addr, nsize);
 +	if (unlikely(!nskb))
 +		goto err;
@@ -10832,7 +9535,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	 * alignment.
 +	 * Code borrowed and adapted from skb_copy().
 +	 */
-+	skb_reserve(nskb, headroom);
++	skb_reserve(nskb, priv->tx_headroom);
 +	skb_put(nskb, skb->len);
 +	if (skb_copy_bits(skb, 0, nskb->data, skb->len)) {
 +		WARN_ONCE(1, "skb parsing failure\n");
@@ -10892,11 +9595,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	nr_frags = skb_shinfo(skb)->nr_frags;
 +	fd->format = qm_fd_sg;
 +
-+	/* The FMan reads 256 bytes from the start of the SGT regardless of
-+	 * its size. In accordance, we reserve the same amount of memory as
-+	 * well.
-+	 */
-+	sgt_size = DPA_SGT_SIZE;
++	sgt_size = sizeof(struct qm_sg_entry) * (1 + nr_frags);
 +
 +	/* Get a page frag to store the SGTable, or a full page if the errata
 +	 * is in place and we need to avoid crossing a 4k boundary.
@@ -11611,7 +10310,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#include <trace/define_trace.h>
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_ethtool.c
-@@ -0,0 +1,542 @@
+@@ -0,0 +1,544 @@
 +/* Copyright 2008-2012 Freescale Semiconductor, Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -11698,8 +10397,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#define DPA_STATS_PERCPU_LEN ARRAY_SIZE(dpa_stats_percpu)
 +#define DPA_STATS_GLOBAL_LEN ARRAY_SIZE(dpa_stats_global)
 +
-+static int __cold dpa_get_ksettings(struct net_device *net_dev,
-+		struct ethtool_link_ksettings *cmd)
++static int __cold dpa_get_settings(struct net_device *net_dev,
++		struct ethtool_cmd *et_cmd)
 +{
 +	int			 _errno;
 +	struct dpa_priv_s	*priv;
@@ -11715,13 +10414,15 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return 0;
 +	}
 +
-+	phy_ethtool_ksettings_get(priv->mac_dev->phy_dev, cmd);
++	_errno = phy_ethtool_gset(priv->mac_dev->phy_dev, et_cmd);
++	if (unlikely(_errno < 0))
++		netdev_err(net_dev, "phy_ethtool_gset() = %d\n", _errno);
 +
 +	return _errno;
 +}
 +
-+static int __cold dpa_set_ksettings(struct net_device *net_dev,
-+		const struct ethtool_link_ksettings *cmd)
++static int __cold dpa_set_settings(struct net_device *net_dev,
++		struct ethtool_cmd *et_cmd)
 +{
 +	int			 _errno;
 +	struct dpa_priv_s	*priv;
@@ -11737,9 +10438,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return -ENODEV;
 +	}
 +
-+	_errno = phy_ethtool_ksettings_set(priv->mac_dev->phy_dev, cmd);
++	_errno = phy_ethtool_sset(priv->mac_dev->phy_dev, et_cmd);
 +	if (unlikely(_errno < 0))
-+		netdev_err(net_dev, "phy_ethtool_ksettings_set() = %d\n", _errno);
++		netdev_err(net_dev, "phy_ethtool_sset() = %d\n", _errno);
 +
 +	return _errno;
 +}
@@ -12134,8 +10835,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 +
 +const struct ethtool_ops dpa_ethtool_ops = {
-+	.get_link_ksettings = dpa_get_ksettings,
-+	.set_link_ksettings = dpa_set_ksettings,
++	.get_settings = dpa_get_settings,
++	.set_settings = dpa_set_settings,
 +	.get_drvinfo = dpa_get_drvinfo,
 +	.get_msglevel = dpa_get_msglevel,
 +	.set_msglevel = dpa_set_msglevel,
@@ -19338,7 +18039,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif /* __FMAN_CRC32_H */
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec.c
-@@ -0,0 +1,847 @@
+@@ -0,0 +1,845 @@
 +/*
 + * Copyright 2008-2012 Freescale Semiconductor Inc.
 + *
@@ -19372,8 +18073,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + */
 +
 +
-+#include "std_ext.h"
-+#include "error_ext.h"
 +#include "fsl_fman_dtsec.h"
 +
 +
@@ -20188,7 +18887,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c
-@@ -0,0 +1,165 @@
+@@ -0,0 +1,163 @@
 +/*
 + * Copyright 2008-2013 Freescale Semiconductor Inc.
 + *
@@ -20222,8 +18921,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + */
 +
 +
-+#include "std_ext.h"
-+#include "error_ext.h"
 +#include "common/general.h"
 +#include "fsl_fman_dtsec_mii_acc.h"
 +
@@ -20891,7 +19588,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fman_memac_mii_acc.c
-@@ -0,0 +1,215 @@
+@@ -0,0 +1,213 @@
 +/*
 + * Copyright 2008-2013 Freescale Semiconductor Inc.
 + *
@@ -20925,8 +19622,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + */
 +
 +
-+#include "std_ext.h"
-+#include "error_ext.h"
 +#include "fsl_fman_memac_mii_acc.h"
 +
 +static void write_phy_reg_10g(struct memac_mii_access_mem_map *mii_regs,
@@ -52151,7 +50846,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif /* __FM_REPLIC_H */
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fman_kg.c
-@@ -0,0 +1,890 @@
+@@ -0,0 +1,888 @@
 +/*
 + * Copyright 2008-2012 Freescale Semiconductor Inc.
 + *
@@ -52184,8 +50879,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 + */
 +
-+#include "std_ext.h"
-+#include "error_ext.h"
 +#include "fsl_fman_kg.h"
 +
 +/****************************************/
@@ -61888,7 +60581,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Port/fman_port.c
-@@ -0,0 +1,1570 @@
+@@ -0,0 +1,1568 @@
 +/*
 + * Copyright 2008-2012 Freescale Semiconductor Inc.
 + *
@@ -61922,8 +60615,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + */
 +
 +
-+#include "std_ext.h"
-+#include "error_ext.h"
 +#include "common/general.h"
 +
 +#include "fman_common.h"
@@ -72191,7 +70882,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- /dev/null
 +++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fman.c
-@@ -0,0 +1,1400 @@
+@@ -0,0 +1,1398 @@
 +/*
 + * Copyright 2008-2012 Freescale Semiconductor Inc.
 + *
@@ -72225,8 +70916,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + */
 +
 +
-+#include "std_ext.h"
-+#include "error_ext.h"
 +#include <linux/math64.h>
 +#include "fsl_fman.h"
 +#include "dpaa_integration_ext.h"
@@ -108891,9 +107580,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +    if (WARN_ON(strlen("ptp-timer") >= sizeof(ids[0].name)))
 +        return NULL;
 +    strcpy(ids[0].name, "ptp-timer");
-+    if (WARN_ON(strlen("fsl,fman-ptp-timer") >= sizeof(ids[0].compatible)))
++    if (WARN_ON(strlen("fsl,fman-rtc") >= sizeof(ids[0].compatible)))
 +        return NULL;
-+    strcpy(ids[0].compatible, "fsl,fman-ptp-timer");
++    strcpy(ids[0].compatible, "fsl,fman-rtc");
 +    for_each_child_of_node(fm_node, dev_node) {
 +        if (likely(of_match_node(ids, dev_node) != NULL)) {
 +            _errno = of_address_to_resource(dev_node, 0, &res);
@@ -109124,7 +107813,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +    if (p_LnxWrpFmDev->fmRtcPhysBaseAddr)
 +    {
-+        dev_res = __devm_request_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, p_LnxWrpFmDev->fmRtcPhysBaseAddr, p_LnxWrpFmDev->fmRtcMemSize, "fman-ptp-timer");
++        dev_res = __devm_request_region(p_LnxWrpFmDev->dev, p_LnxWrpFmDev->res, p_LnxWrpFmDev->fmRtcPhysBaseAddr, p_LnxWrpFmDev->fmRtcMemSize, "fman-rtc");
 +        if (unlikely(dev_res == NULL))
 +            RETURN_ERROR(MAJOR, E_INVALID_STATE, ("__devm_request_region() failed"));
 +
@@ -126794,7 +125483,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +MODULE_LICENSE("Dual BSD/GPL");
 --- /dev/null
 +++ b/drivers/staging/fsl_qbman/bman_driver.c
-@@ -0,0 +1,559 @@
+@@ -0,0 +1,575 @@
 +/* Copyright 2008-2012 Freescale Semiconductor, Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -127141,6 +125830,28 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	}
 +	return 0;
 +}
++static int bman_hotplug_cpu_callback(struct notifier_block *nfb,
++				     unsigned long action, void *hcpu)
++{
++	unsigned int cpu = (unsigned long)hcpu;
++
++	switch (action) {
++	case CPU_ONLINE:
++	case CPU_ONLINE_FROZEN:
++		bman_online_cpu(cpu);
++		break;
++	case CPU_DOWN_PREPARE:
++	case CPU_DOWN_PREPARE_FROZEN:
++		bman_offline_cpu(cpu);
++	default:
++		break;
++	}
++	return NOTIFY_OK;
++}
++
++static struct notifier_block bman_hotplug_cpu_notifier = {
++	.notifier_call = bman_hotplug_cpu_callback,
++};
 +#endif /* CONFIG_HOTPLUG_CPU */
 +
 +/* Initialise the Bman driver. The meat of this function deals with portals. The
@@ -127288,13 +125999,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	for_each_cpu(cpu, &offline_cpus)
 +		bman_offline_cpu(cpu);
 +#ifdef CONFIG_HOTPLUG_CPU
-+	ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
-+					"soc/qbman_portal:online",
-+					bman_online_cpu, bman_offline_cpu);
-+	if (ret < 0) {
-+		pr_err("bman: failed to register hotplug callbacks.\n");
-+		return 0;
-+	}
++	register_hotcpu_notifier(&bman_hotplug_cpu_notifier);
 +#endif
 +	return 0;
 +}
@@ -131061,7 +129766,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif
 --- /dev/null
 +++ b/drivers/staging/fsl_qbman/fsl_usdpaa.c
-@@ -0,0 +1,2008 @@
+@@ -0,0 +1,2007 @@
 +/* Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
 + * Authors: Andy Fleming <afleming@freescale.com>
 + *	    Timur Tabi <timur@freescale.com>
@@ -132223,8 +130928,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +					 : PROT_WRITE),
 +					MAP_SHARED,
 +					start_frag->pfn_base,
-+					&populate,
-+					NULL);
++					&populate);
 +		up_write(&current->mm->mmap_sem);
 +		if (longret & ~PAGE_MASK) {
 +			ret = (int)longret;
@@ -132303,7 +131007,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	base = vma->vm_start;
 +	sz = vma->vm_end - vma->vm_start;
-+	do_munmap(current->mm, base, sz, NULL);
++	do_munmap(current->mm, base, sz);
 +	ret = 0;
 + out:
 +	up_write(&current->mm->mmap_sem);
@@ -132409,7 +131113,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return -EINVAL;
 +	longret = do_mmap_pgoff(fp, PAGE_SIZE, (unsigned long)len,
 +				PROT_READ | PROT_WRITE, MAP_SHARED,
-+				res->start >> PAGE_SHIFT, &populate, NULL);
++				res->start >> PAGE_SHIFT, &populate);
 +	up_write(&current->mm->mmap_sem);
 +
 +	if (longret & ~PAGE_MASK)
@@ -132422,7 +131126,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +static void portal_munmap(struct resource *res, void  *ptr)
 +{
 +	down_write(&current->mm->mmap_sem);
-+	do_munmap(current->mm, (unsigned long)ptr, resource_size(res), NULL);
++	do_munmap(current->mm, (unsigned long)ptr, resource_size(res));
 +	up_write(&current->mm->mmap_sem);
 +}
 +
@@ -133177,7 +131881,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	/* Set the inhibit register.  This will be reenabled
 +	   once the USDPAA code handles the IRQ */
 +	out_be32(ctx->inhibit_addr, 0x1);
-+	pr_debug("Inhibit at %p count %d", ctx->inhibit_addr, ctx->irq_count);
++	pr_info("Inhibit at %p count %d", ctx->inhibit_addr, ctx->irq_count);
 +	return IRQ_HANDLED;
 +}
 +
@@ -133712,7 +132416,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	QMAN_ERR_MDATA(0x01FF, 72, "WQ context memory"),
 +	QMAN_ERR_MDATA(0x00FF, 240, "CGR memory"),
 +	QMAN_ERR_MDATA(0x00FF, 302, "Internal Order Restoration List memory"),
-+	QMAN_ERR_MDATA(0x7FFF, 256, "SW portal ring memory"),
++	QMAN_ERR_MDATA(0x01FF, 256, "SW portal ring memory"),
 +	QMAN_ERR_MDATA(0x07FF, 181, "CEETM class queue descriptor memory"),
 +	QMAN_ERR_MDATA(0x0FFF, 140, "CEETM extended SFDR memory"),
 +	QMAN_ERR_MDATA(0x0FFF, 25, "CEETM logical FQ mapping memory"),
@@ -136279,7 +134983,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +MODULE_LICENSE("Dual BSD/GPL");
 --- /dev/null
 +++ b/drivers/staging/fsl_qbman/qman_driver.c
-@@ -0,0 +1,961 @@
+@@ -0,0 +1,977 @@
 +/* Copyright 2008-2012 Freescale Semiconductor, Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -137006,6 +135710,28 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	return 0;
 +}
 +
++static int qman_hotplug_cpu_callback(struct notifier_block *nfb,
++				unsigned long action, void *hcpu)
++{
++	unsigned int cpu = (unsigned long)hcpu;
++
++	switch (action) {
++	case CPU_ONLINE:
++	case CPU_ONLINE_FROZEN:
++		qman_online_cpu(cpu);
++		break;
++	case CPU_DOWN_PREPARE:
++	case CPU_DOWN_PREPARE_FROZEN:
++		qman_offline_cpu(cpu);
++	default:
++		break;
++	}
++	return NOTIFY_OK;
++}
++
++static struct notifier_block qman_hotplug_cpu_notifier = {
++	.notifier_call = qman_hotplug_cpu_callback,
++};
 +#endif /* CONFIG_HOTPLUG_CPU */
 +
 +__init int qman_init(void)
@@ -137155,13 +135881,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	for_each_cpu(cpu, &offline_cpus)
 +		qman_offline_cpu(cpu);
 +#ifdef CONFIG_HOTPLUG_CPU
-+	ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
-+					"soc/qman_portal:online",
-+					qman_online_cpu, qman_offline_cpu);
-+	if (ret < 0) {
-+		pr_err("qman: failed to register hotplug callbacks.\n");
-+		return ret;
-+	}
++	register_hotcpu_notifier(&qman_hotplug_cpu_notifier);
 +#endif
 +	return 0;
 +}
@@ -142898,7 +141618,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- /dev/null
 +++ b/drivers/staging/fsl_qbman/qman_low.h
-@@ -0,0 +1,1445 @@
+@@ -0,0 +1,1442 @@
 +/* Copyright 2008-2011 Freescale Semiconductor, Inc.
 + *
 + * Redistribution and use in source and binary forms, with or without
@@ -143559,7 +142279,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			qm_dqrr_cce_consume(portal, dqrr->fill);
 +			break;
 +		case qm_dqrr_cdc:
-+			qm_dqrr_cdc_consume_n(portal, (1<<QM_DQRR_SIZE) - 1);
++			qm_dqrr_cdc_consume_n(portal, (QM_DQRR_SIZE - 1));
 +			break;
 +		default:
 +			DPA_ASSERT(0);
@@ -143583,9 +142303,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		(0 ? 0x10 : 0);				/* Ignore SP */
 +	qm_out(CFG, cfg);
 +	qm_dqrr_set_maxfill(portal, max_fill);
-+
-+	/* Recalculate cursor as we may have consumed frames */
-+	dqrr->cursor = dqrr->ring + dqrr->ci;
 +	return 0;
 +}
 +
@@ -145710,106 +144427,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 +EXPORT_SYMBOL(qman_fqid_pool_used);
 --- /dev/null
-+++ b/include/linux/fsl/svr.h
-@@ -0,0 +1,97 @@
-+/*
-+ * MPC85xx cpu type detection
-+ *
-+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
-+ *
-+ * This is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
-+
-+#ifndef FSL_SVR_H
-+#define FSL_SVR_H
-+
-+#define SVR_REV(svr)	((svr) & 0xFF)		/* SOC design resision */
-+#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
-+#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
-+
-+/* Some parts define SVR[0:23] as the SOC version */
-+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF)	/* SOC Version fields */
-+
-+#define SVR_8533	0x803400
-+#define SVR_8535	0x803701
-+#define SVR_8536	0x803700
-+#define SVR_8540	0x803000
-+#define SVR_8541	0x807200
-+#define SVR_8543	0x803200
-+#define SVR_8544	0x803401
-+#define SVR_8545	0x803102
-+#define SVR_8547	0x803101
-+#define SVR_8548	0x803100
-+#define SVR_8555	0x807100
-+#define SVR_8560	0x807000
-+#define SVR_8567	0x807501
-+#define SVR_8568	0x807500
-+#define SVR_8569	0x808000
-+#define SVR_8572	0x80E000
-+#define SVR_P1010	0x80F100
-+#define SVR_P1011	0x80E500
-+#define SVR_P1012	0x80E501
-+#define SVR_P1013	0x80E700
-+#define SVR_P1014	0x80F101
-+#define SVR_P1017	0x80F700
-+#define SVR_P1020	0x80E400
-+#define SVR_P1021	0x80E401
-+#define SVR_P1022	0x80E600
-+#define SVR_P1023	0x80F600
-+#define SVR_P1024	0x80E402
-+#define SVR_P1025	0x80E403
-+#define SVR_P2010	0x80E300
-+#define SVR_P2020	0x80E200
-+#define SVR_P2040	0x821000
-+#define SVR_P2041	0x821001
-+#define SVR_P3041	0x821103
-+#define SVR_P4040	0x820100
-+#define SVR_P4080	0x820000
-+#define SVR_P5010	0x822100
-+#define SVR_P5020	0x822000
-+#define SVR_P5021	0X820500
-+#define SVR_P5040	0x820400
-+#define SVR_T4240	0x824000
-+#define SVR_T4120	0x824001
-+#define SVR_T4160	0x824100
-+#define SVR_T4080	0x824102
-+#define SVR_C291	0x850000
-+#define SVR_C292	0x850020
-+#define SVR_C293	0x850030
-+#define SVR_B4860	0X868000
-+#define SVR_G4860	0x868001
-+#define SVR_G4060	0x868003
-+#define SVR_B4440	0x868100
-+#define SVR_G4440	0x868101
-+#define SVR_B4420	0x868102
-+#define SVR_B4220	0x868103
-+#define SVR_T1040	0x852000
-+#define SVR_T1041	0x852001
-+#define SVR_T1042	0x852002
-+#define SVR_T1020	0x852100
-+#define SVR_T1021	0x852101
-+#define SVR_T1022	0x852102
-+#define SVR_T1023	0x854100
-+#define SVR_T1024	0x854000
-+#define SVR_T2080	0x853000
-+#define SVR_T2081	0x853100
-+
-+#define SVR_8610	0x80A000
-+#define SVR_8641	0x809000
-+#define SVR_8641D	0x809001
-+
-+#define SVR_9130	0x860001
-+#define SVR_9131	0x860000
-+#define SVR_9132	0x861000
-+#define SVR_9232	0x861400
-+
-+#define SVR_Unknown	0xFFFFFF
-+
-+#endif
---- /dev/null
 +++ b/include/linux/fsl_bman.h
 @@ -0,0 +1,532 @@
 +/* Copyright 2008-2012 Freescale Semiconductor, Inc.
@@ -150622,24 +149239,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif
 +
 +#endif /* FSL_USDPAA_H */
---- a/include/linux/netdev_features.h
-+++ b/include/linux/netdev_features.h
-@@ -77,6 +77,7 @@ enum {
- 	NETIF_F_HW_ESP_BIT,		/* Hardware ESP transformation offload */
- 	NETIF_F_HW_ESP_TX_CSUM_BIT,	/* ESP with TX checksum offload */
- 	NETIF_F_RX_UDP_TUNNEL_PORT_BIT, /* Offload of RX port for UDP tunnels */
-+	NETIF_F_HW_ACCEL_MQ_BIT,	/* Hardware-accelerated multiqueue */
- 
- 	/*
- 	 * Add your fresh new feature above and remember to update
-@@ -142,6 +143,7 @@ enum {
- #define NETIF_F_HW_ESP		__NETIF_F(HW_ESP)
- #define NETIF_F_HW_ESP_TX_CSUM	__NETIF_F(HW_ESP_TX_CSUM)
- #define	NETIF_F_RX_UDP_TUNNEL_PORT  __NETIF_F(RX_UDP_TUNNEL_PORT)
-+#define NETIF_F_HW_ACCEL_MQ	__NETIF_F(HW_ACCEL_MQ)
- 
- #define for_each_netdev_feature(mask_addr, bit)	\
- 	for_each_set_bit(bit, (unsigned long *)mask_addr, NETDEV_FEATURE_COUNT)
 --- /dev/null
 +++ b/include/uapi/linux/fmd/Kbuild
 @@ -0,0 +1,5 @@
@@ -156155,19 +154754,3 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +
 +#endif /* __NET_IOCTLS_H */
---- a/net/sched/sch_generic.c
-+++ b/net/sched/sch_generic.c
-@@ -313,6 +313,13 @@ static void dev_watchdog(unsigned long a
- 					txq->trans_timeout++;
- 					break;
- 				}
-+
-+				/* Devices with HW_ACCEL_MQ have multiple txqs
-+				 * but update only the first one's transmission
-+				 * timestamp so avoid checking the rest.
-+				 */
-+				if (dev->features & NETIF_F_HW_ACCEL_MQ)
-+					break;
- 			}
- 
- 			if (some_queue_timedout) {
diff --git a/target/linux/layerscape/patches-4.9/702-pci-support-layerscape.patch b/target/linux/layerscape/patches-4.9/702-pci-support-layerscape.patch
new file mode 100644
index 000000000..6f34cfe58
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/702-pci-support-layerscape.patch
@@ -0,0 +1,2098 @@
+From b2ee6e29bad31facbbf5ac1ce98235ac163d9fa9 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 16:26:47 +0800
+Subject: [PATCH 08/32] pci: support layerscape
+
+This is an integrated patch for layerscape pcie support.
+
+Signed-off-by: Po Liu <po.liu@nxp.com>
+Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
+Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
+Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
+Signed-off-by: Christoph Hellwig <hch@lst.de>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/irqchip/irq-ls-scfg-msi.c            | 257 ++++++-
+ drivers/pci/host/Makefile                    |   2 +-
+ drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++
+ drivers/pci/host/pci-layerscape-ep.c         | 309 ++++++++
+ drivers/pci/host/pci-layerscape-ep.h         | 115 +++
+ drivers/pci/host/pci-layerscape.c            |  48 +-
+ drivers/pci/host/pcie-designware.c           |   6 +
+ drivers/pci/host/pcie-designware.h           |   1 +
+ drivers/pci/pci.c                            |   2 +-
+ drivers/pci/pcie/portdrv_core.c              | 181 ++---
+ drivers/pci/quirks.c                         |  15 +
+ include/linux/pci.h                          |   1 +
+ 12 files changed, 1546 insertions(+), 149 deletions(-)
+ create mode 100644 drivers/pci/host/pci-layerscape-ep-debugfs.c
+ create mode 100644 drivers/pci/host/pci-layerscape-ep.c
+ create mode 100644 drivers/pci/host/pci-layerscape-ep.h
+
+--- a/drivers/irqchip/irq-ls-scfg-msi.c
++++ b/drivers/irqchip/irq-ls-scfg-msi.c
+@@ -17,13 +17,32 @@
+ #include <linux/irq.h>
+ #include <linux/irqchip/chained_irq.h>
+ #include <linux/irqdomain.h>
++#include <linux/of_irq.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
+ #include <linux/spinlock.h>
+ 
+-#define MSI_MAX_IRQS	32
+-#define MSI_IBS_SHIFT	3
+-#define MSIR		4
++#define MSI_IRQS_PER_MSIR	32
++#define MSI_MSIR_OFFSET		4
++
++#define MSI_LS1043V1_1_IRQS_PER_MSIR	8
++#define MSI_LS1043V1_1_MSIR_OFFSET	0x10
++
++struct ls_scfg_msi_cfg {
++	u32 ibs_shift; /* Shift of interrupt bit select */
++	u32 msir_irqs; /* The irq number per MSIR */
++	u32 msir_base; /* The base address of MSIR */
++};
++
++struct ls_scfg_msir {
++	struct ls_scfg_msi *msi_data;
++	unsigned int index;
++	unsigned int gic_irq;
++	unsigned int bit_start;
++	unsigned int bit_end;
++	unsigned int srs; /* Shared interrupt register select */
++	void __iomem *reg;
++};
+ 
+ struct ls_scfg_msi {
+ 	spinlock_t		lock;
+@@ -32,8 +51,11 @@ struct ls_scfg_msi {
+ 	struct irq_domain	*msi_domain;
+ 	void __iomem		*regs;
+ 	phys_addr_t		msiir_addr;
+-	int			irq;
+-	DECLARE_BITMAP(used, MSI_MAX_IRQS);
++	struct ls_scfg_msi_cfg	*cfg;
++	u32			msir_num;
++	struct ls_scfg_msir	*msir;
++	u32			irqs_num;
++	unsigned long		*used;
+ };
+ 
+ static struct irq_chip ls_scfg_msi_irq_chip = {
+@@ -49,19 +71,56 @@ static struct msi_domain_info ls_scfg_ms
+ 	.chip	= &ls_scfg_msi_irq_chip,
+ };
+ 
++static int msi_affinity_flag = 1;
++
++static int __init early_parse_ls_scfg_msi(char *p)
++{
++	if (p && strncmp(p, "no-affinity", 11) == 0)
++		msi_affinity_flag = 0;
++	else
++		msi_affinity_flag = 1;
++
++	return 0;
++}
++early_param("lsmsi", early_parse_ls_scfg_msi);
++
+ static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
+ {
+ 	struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
+ 
+ 	msg->address_hi = upper_32_bits(msi_data->msiir_addr);
+ 	msg->address_lo = lower_32_bits(msi_data->msiir_addr);
+-	msg->data = data->hwirq << MSI_IBS_SHIFT;
++	msg->data = data->hwirq;
++
++	if (msi_affinity_flag)
++		msg->data |= cpumask_first(data->common->affinity);
+ }
+ 
+ static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
+ 				    const struct cpumask *mask, bool force)
+ {
+-	return -EINVAL;
++	struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
++	u32 cpu;
++
++	if (!msi_affinity_flag)
++		return -EINVAL;
++
++	if (!force)
++		cpu = cpumask_any_and(mask, cpu_online_mask);
++	else
++		cpu = cpumask_first(mask);
++
++	if (cpu >= msi_data->msir_num)
++		return -EINVAL;
++
++	if (msi_data->msir[cpu].gic_irq <= 0) {
++		pr_warn("cannot bind the irq to cpu%d\n", cpu);
++		return -EINVAL;
++	}
++
++	cpumask_copy(irq_data->common->affinity, mask);
++
++	return IRQ_SET_MASK_OK;
+ }
+ 
+ static struct irq_chip ls_scfg_msi_parent_chip = {
+@@ -81,8 +140,8 @@ static int ls_scfg_msi_domain_irq_alloc(
+ 	WARN_ON(nr_irqs != 1);
+ 
+ 	spin_lock(&msi_data->lock);
+-	pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
+-	if (pos < MSI_MAX_IRQS)
++	pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
++	if (pos < msi_data->irqs_num)
+ 		__set_bit(pos, msi_data->used);
+ 	else
+ 		err = -ENOSPC;
+@@ -106,7 +165,7 @@ static void ls_scfg_msi_domain_irq_free(
+ 	int pos;
+ 
+ 	pos = d->hwirq;
+-	if (pos < 0 || pos >= MSI_MAX_IRQS) {
++	if (pos < 0 || pos >= msi_data->irqs_num) {
+ 		pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
+ 		return;
+ 	}
+@@ -123,15 +182,22 @@ static const struct irq_domain_ops ls_sc
+ 
+ static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
+ {
+-	struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
++	struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
++	struct ls_scfg_msi *msi_data = msir->msi_data;
+ 	unsigned long val;
+-	int pos, virq;
++	int pos, size, virq, hwirq;
+ 
+ 	chained_irq_enter(irq_desc_get_chip(desc), desc);
+ 
+-	val = ioread32be(msi_data->regs + MSIR);
+-	for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
+-		virq = irq_find_mapping(msi_data->parent, (31 - pos));
++	val = ioread32be(msir->reg);
++
++	pos = msir->bit_start;
++	size = msir->bit_end + 1;
++
++	for_each_set_bit_from(pos, &val, size) {
++		hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
++			msir->srs;
++		virq = irq_find_mapping(msi_data->parent, hwirq);
+ 		if (virq)
+ 			generic_handle_irq(virq);
+ 	}
+@@ -143,7 +209,7 @@ static int ls_scfg_msi_domains_init(stru
+ {
+ 	/* Initialize MSI domain parent */
+ 	msi_data->parent = irq_domain_add_linear(NULL,
+-						 MSI_MAX_IRQS,
++						 msi_data->irqs_num,
+ 						 &ls_scfg_msi_domain_ops,
+ 						 msi_data);
+ 	if (!msi_data->parent) {
+@@ -164,16 +230,118 @@ static int ls_scfg_msi_domains_init(stru
+ 	return 0;
+ }
+ 
++static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
++{
++	struct ls_scfg_msir *msir;
++	int virq, i, hwirq;
++
++	virq = platform_get_irq(msi_data->pdev, index);
++	if (virq <= 0)
++		return -ENODEV;
++
++	msir = &msi_data->msir[index];
++	msir->index = index;
++	msir->msi_data = msi_data;
++	msir->gic_irq = virq;
++	msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
++
++	if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
++		msir->bit_start = 32 - ((msir->index + 1) *
++				  MSI_LS1043V1_1_IRQS_PER_MSIR);
++		msir->bit_end = msir->bit_start +
++				MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
++	} else {
++		msir->bit_start = 0;
++		msir->bit_end = msi_data->cfg->msir_irqs - 1;
++	}
++
++	irq_set_chained_handler_and_data(msir->gic_irq,
++					 ls_scfg_msi_irq_handler,
++					 msir);
++
++	if (msi_affinity_flag) {
++		/* Associate MSIR interrupt to the cpu */
++		irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
++		msir->srs = 0; /* This value is determined by the CPU */
++	} else
++		msir->srs = index;
++
++	/* Release the hwirqs corresponding to this MSIR */
++	if (!msi_affinity_flag || msir->index == 0) {
++		for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
++			hwirq = i << msi_data->cfg->ibs_shift | msir->index;
++			bitmap_clear(msi_data->used, hwirq, 1);
++		}
++	}
++
++	return 0;
++}
++
++static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
++{
++	struct ls_scfg_msi *msi_data = msir->msi_data;
++	int i, hwirq;
++
++	if (msir->gic_irq > 0)
++		irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
++
++	for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
++		hwirq = i << msi_data->cfg->ibs_shift | msir->index;
++		bitmap_set(msi_data->used, hwirq, 1);
++	}
++
++	return 0;
++}
++
++static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
++	.ibs_shift = 3,
++	.msir_irqs = MSI_IRQS_PER_MSIR,
++	.msir_base = MSI_MSIR_OFFSET,
++};
++
++static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
++	.ibs_shift = 2,
++	.msir_irqs = MSI_IRQS_PER_MSIR,
++	.msir_base = MSI_MSIR_OFFSET,
++};
++
++static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
++	.ibs_shift = 2,
++	.msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
++	.msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
++};
++
++static const struct of_device_id ls_scfg_msi_id[] = {
++	/* The following two misspelled compatibles are obsolete */
++	{ .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
++	{ .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
++
++	{ .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },
++	{ .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
++	{ .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
++	{ .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
++	{ .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
++
+ static int ls_scfg_msi_probe(struct platform_device *pdev)
+ {
++	const struct of_device_id *match;
+ 	struct ls_scfg_msi *msi_data;
+ 	struct resource *res;
+-	int ret;
++	int i, ret;
++
++	match = of_match_device(ls_scfg_msi_id, &pdev->dev);
++	if (!match)
++		return -ENODEV;
+ 
+ 	msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
+ 	if (!msi_data)
+ 		return -ENOMEM;
+ 
++	msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
++
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
+ 	if (IS_ERR(msi_data->regs)) {
+@@ -182,23 +350,48 @@ static int ls_scfg_msi_probe(struct plat
+ 	}
+ 	msi_data->msiir_addr = res->start;
+ 
+-	msi_data->irq = platform_get_irq(pdev, 0);
+-	if (msi_data->irq <= 0) {
+-		dev_err(&pdev->dev, "failed to get MSI irq\n");
+-		return -ENODEV;
+-	}
+-
+ 	msi_data->pdev = pdev;
+ 	spin_lock_init(&msi_data->lock);
+ 
++	msi_data->irqs_num = MSI_IRQS_PER_MSIR *
++			     (1 << msi_data->cfg->ibs_shift);
++	msi_data->used = devm_kcalloc(&pdev->dev,
++				    BITS_TO_LONGS(msi_data->irqs_num),
++				    sizeof(*msi_data->used),
++				    GFP_KERNEL);
++	if (!msi_data->used)
++		return -ENOMEM;
++	/*
++	 * Reserve all the hwirqs
++	 * The available hwirqs will be released in ls1_msi_setup_hwirq()
++	 */
++	bitmap_set(msi_data->used, 0, msi_data->irqs_num);
++
++	msi_data->msir_num = of_irq_count(pdev->dev.of_node);
++
++	if (msi_affinity_flag) {
++		u32 cpu_num;
++
++		cpu_num = num_possible_cpus();
++		if (msi_data->msir_num >= cpu_num)
++			msi_data->msir_num = cpu_num;
++		else
++			msi_affinity_flag = 0;
++	}
++
++	msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
++				      sizeof(*msi_data->msir),
++				      GFP_KERNEL);
++	if (!msi_data->msir)
++		return -ENOMEM;
++
++	for (i = 0; i < msi_data->msir_num; i++)
++		ls_scfg_msi_setup_hwirq(msi_data, i);
++
+ 	ret = ls_scfg_msi_domains_init(msi_data);
+ 	if (ret)
+ 		return ret;
+ 
+-	irq_set_chained_handler_and_data(msi_data->irq,
+-					 ls_scfg_msi_irq_handler,
+-					 msi_data);
+-
+ 	platform_set_drvdata(pdev, msi_data);
+ 
+ 	return 0;
+@@ -207,8 +400,10 @@ static int ls_scfg_msi_probe(struct plat
+ static int ls_scfg_msi_remove(struct platform_device *pdev)
+ {
+ 	struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
++	int i;
+ 
+-	irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
++	for (i = 0; i < msi_data->msir_num; i++)
++		ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
+ 
+ 	irq_domain_remove(msi_data->msi_domain);
+ 	irq_domain_remove(msi_data->parent);
+@@ -218,12 +413,6 @@ static int ls_scfg_msi_remove(struct pla
+ 	return 0;
+ }
+ 
+-static const struct of_device_id ls_scfg_msi_id[] = {
+-	{ .compatible = "fsl,1s1021a-msi", },
+-	{ .compatible = "fsl,1s1043a-msi", },
+-	{},
+-};
+-
+ static struct platform_driver ls_scfg_msi_driver = {
+ 	.driver = {
+ 		.name = "ls-scfg-msi",
+--- a/drivers/pci/host/Makefile
++++ b/drivers/pci/host/Makefile
+@@ -17,7 +17,7 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx
+ obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
+ obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
+ obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
+-obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
++obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o pci-layerscape-ep-debugfs.o
+ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
+ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
+ obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
+--- /dev/null
++++ b/drivers/pci/host/pci-layerscape-ep-debugfs.c
+@@ -0,0 +1,758 @@
++/*
++ * PCIe Endpoint driver for Freescale Layerscape SoCs
++ *
++ * Copyright (C) 2015 Freescale Semiconductor.
++ *
++  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/debugfs.h>
++#include <linux/time.h>
++#include <linux/uaccess.h>
++#include <linux/kthread.h>
++#include <linux/slab.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/freezer.h>
++
++#include <linux/completion.h>
++
++#include "pci-layerscape-ep.h"
++
++#define PCIE_ATU_INDEX3		(0x3 << 0)
++#define PCIE_ATU_INDEX2		(0x2 << 0)
++#define PCIE_ATU_INDEX1		(0x1 << 0)
++#define PCIE_ATU_INDEX0		(0x0 << 0)
++
++#define PCIE_BAR0_SIZE		(4 * 1024) /* 4K */
++#define PCIE_BAR1_SIZE		(8 * 1024) /* 8K for MSIX */
++#define PCIE_BAR2_SIZE		(4 * 1024) /* 4K */
++#define PCIE_BAR4_SIZE		(1 * 1024 * 1024) /* 1M */
++#define PCIE_MSI_OB_SIZE	(4 * 1024) /* 4K */
++
++#define PCIE_MSI_MSG_ADDR_OFF	0x54
++#define PCIE_MSI_MSG_DATA_OFF	0x5c
++
++enum test_type {
++	TEST_TYPE_DMA,
++	TEST_TYPE_MEMCPY
++};
++
++enum test_dirt {
++	TEST_DIRT_READ,
++	TEST_DIRT_WRITE
++};
++
++enum test_status {
++	TEST_IDLE,
++	TEST_BUSY
++};
++
++struct ls_ep_test {
++	struct ls_ep_dev	*ep;
++	void __iomem		*cfg;
++	void __iomem		*buf;
++	void __iomem		*out;
++	void __iomem		*msi;
++	dma_addr_t		cfg_addr;
++	dma_addr_t		buf_addr;
++	dma_addr_t		out_addr;
++	dma_addr_t		bus_addr;
++	dma_addr_t		msi_addr;
++	u64			msi_msg_addr;
++	u16			msi_msg_data;
++	struct task_struct	*thread;
++	spinlock_t		lock;
++	struct completion	done;
++	u32			len;
++	int			loop;
++	char			data;
++	enum test_dirt		dirt;
++	enum test_type		type;
++	enum test_status	status;
++	u64			result; /* Mbps */
++	char			cmd[256];
++};
++
++static int ls_pcie_ep_trigger_msi(struct ls_ep_test *test)
++{
++	if (!test->msi)
++		return -EINVAL;
++
++	iowrite32(test->msi_msg_data, test->msi);
++
++	return 0;
++}
++
++static int ls_pcie_ep_test_try_run(struct ls_ep_test *test)
++{
++	int ret;
++
++	spin_lock(&test->lock);
++	if (test->status == TEST_IDLE) {
++		test->status = TEST_BUSY;
++		ret = 0;
++	} else
++		ret = -EBUSY;
++	spin_unlock(&test->lock);
++
++	return ret;
++}
++
++static void ls_pcie_ep_test_done(struct ls_ep_test *test)
++{
++	spin_lock(&test->lock);
++	test->status = TEST_IDLE;
++	spin_unlock(&test->lock);
++}
++
++static void ls_pcie_ep_test_dma_cb(void *arg)
++{
++	struct ls_ep_test *test = arg;
++
++	complete(&test->done);
++}
++
++static int ls_pcie_ep_test_dma(struct ls_ep_test *test)
++{
++	dma_cap_mask_t mask;
++	struct dma_chan *chan;
++	struct dma_device *dma_dev;
++	dma_addr_t src, dst;
++	enum dma_data_direction direction;
++	enum dma_ctrl_flags dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
++	struct timespec start, end, period;
++	int i = 0;
++
++	dma_cap_zero(mask);
++	dma_cap_set(DMA_MEMCPY, mask);
++
++	chan = dma_request_channel(mask, NULL, test);
++	if (!chan) {
++		pr_err("failed to request dma channel\n");
++		return -EINVAL;
++	}
++
++	memset(test->buf, test->data, test->len);
++
++	if (test->dirt == TEST_DIRT_WRITE) {
++		src = test->buf_addr;
++		dst = test->out_addr;
++		direction = DMA_TO_DEVICE;
++	} else {
++		src = test->out_addr;
++		dst = test->buf_addr;
++		direction = DMA_FROM_DEVICE;
++	}
++
++	dma_dev = chan->device;
++	dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
++
++	dma_sync_single_for_device(&test->ep->dev, test->buf_addr,
++				   test->len, direction);
++
++	set_freezable();
++
++	getrawmonotonic(&start);
++	while (!kthread_should_stop() && (i < test->loop)) {
++		struct dma_async_tx_descriptor *dma_desc;
++		dma_cookie_t	dma_cookie = {0};
++		unsigned long tmo;
++		int status;
++
++		init_completion(&test->done);
++
++		dma_desc = dma_dev->device_prep_dma_memcpy(chan,
++							   dst, src,
++							   test->len,
++							   dma_flags);
++		if (!dma_desc) {
++			pr_err("DMA desc constr failed...\n");
++			goto _err;
++		}
++
++		dma_desc->callback = ls_pcie_ep_test_dma_cb;
++		dma_desc->callback_param = test;
++		dma_cookie = dmaengine_submit(dma_desc);
++
++		if (dma_submit_error(dma_cookie)) {
++			pr_err("DMA submit error....\n");
++			goto _err;
++		}
++
++		/* Trigger the transaction */
++		dma_async_issue_pending(chan);
++
++		tmo = wait_for_completion_timeout(&test->done,
++					  msecs_to_jiffies(5 * test->len));
++		if (tmo == 0) {
++			pr_err("Self-test copy timed out, disabling\n");
++			goto _err;
++		}
++
++		status = dma_async_is_tx_complete(chan, dma_cookie,
++						  NULL, NULL);
++		if (status != DMA_COMPLETE) {
++			pr_err("got completion callback, but status is %s\n",
++			       status == DMA_ERROR ? "error" : "in progress");
++			goto _err;
++		}
++
++		i++;
++	}
++
++	getrawmonotonic(&end);
++	period = timespec_sub(end, start);
++	test->result = test->len * 8ULL * i * 1000;
++	do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
++	dma_release_channel(chan);
++
++	return 0;
++
++_err:
++	dma_release_channel(chan);
++	test->result = 0;
++	return -EINVAL;
++}
++
++static int ls_pcie_ep_test_cpy(struct ls_ep_test *test)
++{
++	void *dst, *src;
++	struct timespec start, end, period;
++	int i = 0;
++
++	memset(test->buf, test->data, test->len);
++
++	if (test->dirt == TEST_DIRT_WRITE) {
++		dst = test->out;
++		src = test->buf;
++	} else {
++		dst = test->buf;
++		src = test->out;
++	}
++
++	getrawmonotonic(&start);
++	while (!kthread_should_stop() && i < test->loop) {
++		memcpy(dst, src, test->len);
++		i++;
++	}
++	getrawmonotonic(&end);
++
++	period = timespec_sub(end, start);
++	test->result = test->len * 8ULL * i * 1000;
++	do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
++
++	return 0;
++}
++
++int ls_pcie_ep_test_thread(void *arg)
++{
++	int ret;
++
++	struct ls_ep_test *test = arg;
++
++	if (test->type == TEST_TYPE_DMA)
++		ret = ls_pcie_ep_test_dma(test);
++	else
++		ret = ls_pcie_ep_test_cpy(test);
++
++	if (ret) {
++		pr_err("\n%s \ttest failed\n",
++		       test->cmd);
++		test->result = 0;
++	} else
++		pr_err("\n%s \tthroughput:%lluMbps\n",
++		       test->cmd, test->result);
++
++	ls_pcie_ep_test_done(test);
++
++	ls_pcie_ep_trigger_msi(test);
++
++	do_exit(0);
++}
++
++static int ls_pcie_ep_free_test(struct ls_ep_dev *ep)
++{
++	struct ls_ep_test *test = ep->driver_data;
++
++	if (!test)
++		return 0;
++
++	if (test->status == TEST_BUSY) {
++		kthread_stop(test->thread);
++		dev_info(&ep->dev,
++			 "test is running please wait and run again\n");
++		return -EBUSY;
++	}
++
++	if (test->buf)
++		free_pages((unsigned long)test->buf,
++			   get_order(PCIE_BAR4_SIZE));
++
++	if (test->cfg)
++		free_pages((unsigned long)test->cfg,
++			   get_order(PCIE_BAR2_SIZE));
++
++	if (test->out)
++		iounmap(test->out);
++
++	kfree(test);
++	ep->driver_data = NULL;
++
++	return 0;
++}
++
++static int ls_pcie_ep_init_test(struct ls_ep_dev *ep, u64 bus_addr)
++{
++	struct ls_pcie *pcie = ep->pcie;
++	struct ls_ep_test *test = ep->driver_data;
++	int err;
++
++	if (test) {
++		dev_info(&ep->dev,
++			 "Please use 'free' to remove the exiting test\n");
++		return -EBUSY;
++	}
++
++	test = kzalloc(sizeof(*test), GFP_KERNEL);
++	if (!test)
++		return -ENOMEM;
++	ep->driver_data = test;
++	test->ep = ep;
++	spin_lock_init(&test->lock);
++	test->status = TEST_IDLE;
++
++	test->buf = dma_alloc_coherent(pcie->dev, get_order(PCIE_BAR4_SIZE),
++					&test->buf_addr,
++					GFP_KERNEL);
++	if (!test->buf) {
++		dev_info(&ep->dev, "failed to get mem for bar4\n");
++		err = -ENOMEM;
++		goto _err;
++	}
++
++	test->cfg = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
++					     get_order(PCIE_BAR2_SIZE));
++	if (!test->cfg) {
++		dev_info(&ep->dev, "failed to get mem for bar4\n");
++		err = -ENOMEM;
++		goto _err;
++	}
++	test->cfg_addr = virt_to_phys(test->cfg);
++
++	test->out_addr = pcie->out_base;
++	test->out = ioremap(test->out_addr, PCIE_BAR4_SIZE);
++	if (!test->out) {
++		dev_info(&ep->dev, "failed to map out\n");
++		err = -ENOMEM;
++		goto _err;
++	}
++
++	test->bus_addr = bus_addr;
++
++	test->msi_addr = test->out_addr + PCIE_BAR4_SIZE;
++	test->msi = ioremap(test->msi_addr, PCIE_MSI_OB_SIZE);
++	if (!test->msi)
++		dev_info(&ep->dev, "failed to map MSI outbound region\n");
++
++	test->msi_msg_addr = ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF) |
++		(((u64)ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF + 4)) << 32);
++	test->msi_msg_data = ioread16(pcie->dbi + PCIE_MSI_MSG_DATA_OFF);
++
++	ls_pcie_ep_dev_cfg_enable(ep);
++
++	/* outbound iATU for memory */
++	ls_pcie_iatu_outbound_set(pcie, 0, PCIE_ATU_TYPE_MEM,
++				  test->out_addr, bus_addr, PCIE_BAR4_SIZE);
++	/* outbound iATU for MSI */
++	ls_pcie_iatu_outbound_set(pcie, 1, PCIE_ATU_TYPE_MEM,
++				  test->msi_addr, test->msi_msg_addr,
++				  PCIE_MSI_OB_SIZE);
++
++	/* ATU 0 : INBOUND : map BAR0 */
++	ls_pcie_iatu_inbound_set(pcie, 0, 0, test->cfg_addr);
++	/* ATU 2 : INBOUND : map BAR2 */
++	ls_pcie_iatu_inbound_set(pcie, 2, 2, test->cfg_addr);
++	/* ATU 3 : INBOUND : map BAR4 */
++	ls_pcie_iatu_inbound_set(pcie, 3, 4, test->buf_addr);
++
++	return 0;
++
++_err:
++	ls_pcie_ep_free_test(ep);
++	return err;
++}
++
++static int ls_pcie_ep_start_test(struct ls_ep_dev *ep, char *cmd)
++{
++	struct ls_ep_test *test = ep->driver_data;
++	enum test_type type;
++	enum test_dirt dirt;
++	u32 cnt, len, loop;
++	unsigned int data;
++	char dirt_str[2];
++	int ret;
++
++	if (strncmp(cmd, "dma", 3) == 0)
++		type = TEST_TYPE_DMA;
++	else
++		type = TEST_TYPE_MEMCPY;
++
++	cnt = sscanf(&cmd[4], "%1s %u %u %x", dirt_str, &len, &loop, &data);
++	if (cnt != 4) {
++		dev_info(&ep->dev, "format error %s", cmd);
++		dev_info(&ep->dev, "dma/cpy <r/w> <packet_size> <loop> <data>\n");
++		return -EINVAL;
++	}
++
++	if (strncmp(dirt_str, "r", 1) == 0)
++		dirt = TEST_DIRT_READ;
++	else
++		dirt = TEST_DIRT_WRITE;
++
++	if (len > PCIE_BAR4_SIZE) {
++		dev_err(&ep->dev, "max len is %d", PCIE_BAR4_SIZE);
++		return -EINVAL;
++	}
++
++	if (!test) {
++		dev_err(&ep->dev, "Please first run init command\n");
++		return -EINVAL;
++	}
++
++	if (ls_pcie_ep_test_try_run(test)) {
++		dev_err(&ep->dev, "There is already a test running\n");
++		return -EINVAL;
++	}
++
++	test->len = len;
++	test->loop = loop;
++	test->type = type;
++	test->data = (char)data;
++	test->dirt = dirt;
++	strcpy(test->cmd, cmd);
++	test->thread = kthread_run(ls_pcie_ep_test_thread, test,
++				   "pcie ep test");
++	if (IS_ERR(test->thread)) {
++		dev_err(&ep->dev, "fork failed for pcie ep test\n");
++		ls_pcie_ep_test_done(test);
++		ret = PTR_ERR(test->thread);
++	}
++
++	return ret;
++}
++
++
++/**
++ * ls_pcie_reg_ops_read - read for regs data
++ * @filp: the opened file
++ * @buffer: where to write the data for the user to read
++ * @count: the size of the user's buffer
++ * @ppos: file position offset
++ **/
++static ssize_t ls_pcie_ep_dbg_regs_read(struct file *filp, char __user *buffer,
++				    size_t count, loff_t *ppos)
++{
++	struct ls_ep_dev *ep = filp->private_data;
++	struct ls_pcie *pcie = ep->pcie;
++	char *buf;
++	int desc = 0, i, len;
++
++	buf = kmalloc(4 * 1024, GFP_KERNEL);
++	if (!buf)
++		return -ENOMEM;
++
++	ls_pcie_ep_dev_cfg_enable(ep);
++
++	desc += sprintf(buf + desc, "%s", "reg info:");
++	for (i = 0; i < 0x200; i += 4) {
++		if (i % 16 == 0)
++			desc += sprintf(buf + desc, "\n%08x:", i);
++		desc += sprintf(buf + desc, " %08x", readl(pcie->dbi + i));
++	}
++
++	desc += sprintf(buf + desc, "\n%s", "outbound iATU info:\n");
++	for (i = 0; i < 6; i++) {
++		writel(PCIE_ATU_REGION_OUTBOUND | i,
++		       pcie->dbi + PCIE_ATU_VIEWPORT);
++		desc += sprintf(buf + desc, "iATU%d", i);
++		desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
++		desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
++		desc += sprintf(buf + desc, "\tLOWER BUS  0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
++		desc += sprintf(buf + desc, "\tUPPER BUS  0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
++		desc += sprintf(buf + desc, "\tLIMIT      0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_LIMIT));
++		desc += sprintf(buf + desc, "\tCR1        0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_CR1));
++		desc += sprintf(buf + desc, "\tCR2        0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_CR2));
++	}
++
++	desc += sprintf(buf + desc, "\n%s", "inbound iATU info:\n");
++	for (i = 0; i < 6; i++) {
++		writel(PCIE_ATU_REGION_INBOUND | i,
++		       pcie->dbi + PCIE_ATU_VIEWPORT);
++		desc += sprintf(buf + desc, "iATU%d", i);
++		desc += sprintf(buf + desc, "\tLOWER BUS  0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
++		desc += sprintf(buf + desc, "\tUPPER BUSs 0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
++		desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
++		desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
++		desc += sprintf(buf + desc, "\tLIMIT      0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_LIMIT));
++		desc += sprintf(buf + desc, "\tCR1        0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_CR1));
++		desc += sprintf(buf + desc, "\tCR2        0x%08x\n",
++		      readl(pcie->dbi + PCIE_ATU_CR2));
++	}
++
++	len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
++	kfree(buf);
++
++	return len;
++}
++
++/**
++ * ls_pcie_ep_dbg_regs_write - write into regs datum
++ * @filp: the opened file
++ * @buffer: where to find the user's data
++ * @count: the length of the user's data
++ * @ppos: file position offset
++ **/
++static ssize_t ls_pcie_ep_dbg_regs_write(struct file *filp,
++					 const char __user *buffer,
++					 size_t count, loff_t *ppos)
++{
++	struct ls_ep_dev *ep = filp->private_data;
++	struct ls_pcie *pcie = ep->pcie;
++	char buf[256];
++
++	if (count >= sizeof(buf))
++		return -ENOSPC;
++
++	memset(buf, 0, sizeof(buf));
++
++	if (copy_from_user(buf, buffer, count))
++		return -EFAULT;
++
++	ls_pcie_ep_dev_cfg_enable(ep);
++
++	if (strncmp(buf, "reg", 3) == 0) {
++		u32 reg, value;
++		int cnt;
++
++		cnt = sscanf(&buf[3], "%x %x", &reg, &value);
++		if (cnt == 2) {
++			writel(value, pcie->dbi + reg);
++			value = readl(pcie->dbi + reg);
++			dev_info(&ep->dev, "reg 0x%08x: 0x%08x\n",
++				 reg, value);
++		} else {
++			dev_info(&ep->dev, "reg <reg> <value>\n");
++		}
++	} else if (strncmp(buf, "atu", 3) == 0) {
++		/* to do */
++		dev_info(&ep->dev, " Not support atu command\n");
++	} else {
++		dev_info(&ep->dev, "Unknown command %s\n", buf);
++		dev_info(&ep->dev, "Available commands:\n");
++		dev_info(&ep->dev, "   reg <reg> <value>\n");
++	}
++
++	return count;
++}
++
++static const struct file_operations ls_pcie_ep_dbg_regs_fops = {
++	.owner = THIS_MODULE,
++	.open = simple_open,
++	.read =  ls_pcie_ep_dbg_regs_read,
++	.write = ls_pcie_ep_dbg_regs_write,
++};
++
++static ssize_t ls_pcie_ep_dbg_test_read(struct file *filp,
++				   char __user *buffer,
++				   size_t count, loff_t *ppos)
++{
++	struct ls_ep_dev *ep = filp->private_data;
++	struct ls_ep_test *test = ep->driver_data;
++	char buf[512];
++	int desc = 0, len;
++
++	if (!test) {
++		dev_info(&ep->dev, " there is NO test\n");
++		return 0;
++	}
++
++	if (test->status != TEST_IDLE) {
++		dev_info(&ep->dev, "test %s is running\n", test->cmd);
++		return 0;
++	}
++
++	desc = sprintf(buf, "MSI ADDR:0x%llx MSI DATA:0x%x\n",
++		test->msi_msg_addr, test->msi_msg_data);
++
++	desc += sprintf(buf + desc, "%s throughput:%lluMbps\n",
++			test->cmd, test->result);
++
++	len = simple_read_from_buffer(buffer, count, ppos,
++				      buf, desc);
++
++	return len;
++}
++
++static ssize_t ls_pcie_ep_dbg_test_write(struct file *filp,
++					const char __user *buffer,
++					size_t count, loff_t *ppos)
++{
++	struct ls_ep_dev *ep = filp->private_data;
++	char buf[256];
++
++	if (count >= sizeof(buf))
++		return -ENOSPC;
++
++	memset(buf, 0, sizeof(buf));
++
++	if (copy_from_user(buf, buffer, count))
++		return -EFAULT;
++
++	if (strncmp(buf, "init", 4) == 0) {
++		int i = 4;
++		u64 bus_addr;
++
++		while (buf[i] == ' ')
++			i++;
++
++		if (kstrtou64(&buf[i], 0, &bus_addr))
++			dev_info(&ep->dev, "command: init <bus_addr>\n");
++		else {
++			if (ls_pcie_ep_init_test(ep, bus_addr))
++				dev_info(&ep->dev, "failed to init test\n");
++		}
++	} else if (strncmp(buf, "free", 4) == 0)
++		ls_pcie_ep_free_test(ep);
++	else if (strncmp(buf, "dma", 3) == 0 ||
++		 strncmp(buf, "cpy", 3) == 0)
++		ls_pcie_ep_start_test(ep, buf);
++	else {
++		dev_info(&ep->dev, "Unknown command: %s\n", buf);
++		dev_info(&ep->dev, "Available commands:\n");
++		dev_info(&ep->dev, "\tinit <bus_addr>\n");
++		dev_info(&ep->dev, "\t<dma/cpy> <r/w> <packet_size> <loop>\n");
++		dev_info(&ep->dev, "\tfree\n");
++	}
++
++	return count;
++}
++
++static const struct file_operations ls_pcie_ep_dbg_test_fops = {
++	.owner = THIS_MODULE,
++	.open = simple_open,
++	.read = ls_pcie_ep_dbg_test_read,
++	.write = ls_pcie_ep_dbg_test_write,
++};
++
++static ssize_t ls_pcie_ep_dbg_dump_read(struct file *filp,
++				   char __user *buffer,
++				   size_t count, loff_t *ppos)
++{
++	struct ls_ep_dev *ep = filp->private_data;
++	struct ls_ep_test *test = ep->driver_data;
++	char *buf;
++	int desc = 0, i, len;
++
++	buf = kmalloc(4 * 1024, GFP_KERNEL);
++	if (!buf)
++		return -ENOMEM;
++
++	if (!test) {
++		dev_info(&ep->dev, " there is NO test\n");
++		kfree(buf);
++		return 0;
++	}
++
++	desc += sprintf(buf + desc, "%s", "dump info:");
++	for (i = 0; i < 256; i += 4) {
++		if (i % 16 == 0)
++			desc += sprintf(buf + desc, "\n%08x:", i);
++		desc += sprintf(buf + desc, " %08x", readl(test->buf + i));
++	}
++
++	desc += sprintf(buf + desc, "\n");
++	len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
++
++	kfree(buf);
++
++	return len;
++}
++
++static const struct file_operations ls_pcie_ep_dbg_dump_fops = {
++	.owner = THIS_MODULE,
++	.open = simple_open,
++	.read = ls_pcie_ep_dbg_dump_read,
++};
++
++static int ls_pcie_ep_dev_dbgfs_init(struct ls_ep_dev *ep)
++{
++	struct ls_pcie *pcie = ep->pcie;
++	struct dentry *pfile;
++
++	ls_pcie_ep_dev_cfg_enable(ep);
++
++	ep->dir = debugfs_create_dir(dev_name(&ep->dev), pcie->dir);
++	if (!ep->dir)
++		return -ENOMEM;
++
++	pfile = debugfs_create_file("regs", 0600, ep->dir, ep,
++				    &ls_pcie_ep_dbg_regs_fops);
++	if (!pfile)
++		dev_info(&ep->dev, "debugfs regs for failed\n");
++
++	pfile = debugfs_create_file("test", 0600, ep->dir, ep,
++				    &ls_pcie_ep_dbg_test_fops);
++	if (!pfile)
++		dev_info(&ep->dev, "debugfs test for failed\n");
++
++	pfile = debugfs_create_file("dump", 0600, ep->dir, ep,
++				    &ls_pcie_ep_dbg_dump_fops);
++	if (!pfile)
++		dev_info(&ep->dev, "debugfs dump for failed\n");
++
++	return 0;
++}
++
++int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie)
++{
++	struct ls_ep_dev *ep;
++
++	pcie->dir = debugfs_create_dir(dev_name(pcie->dev), NULL);
++	if (!pcie->dir)
++		return -ENOMEM;
++
++	list_for_each_entry(ep, &pcie->ep_list, node)
++		ls_pcie_ep_dev_dbgfs_init(ep);
++
++	return 0;
++}
++
++int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie)
++{
++	debugfs_remove_recursive(pcie->dir);
++	return 0;
++}
++
++MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
++MODULE_DESCRIPTION("Freescale Layerscape PCIe EP controller driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/pci/host/pci-layerscape-ep.c
+@@ -0,0 +1,309 @@
++/*
++ * PCIe Endpoint driver for Freescale Layerscape SoCs
++ *
++ * Copyright (C) 2015 Freescale Semiconductor.
++ *
++  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_pci.h>
++#include <linux/of_platform.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/pci.h>
++#include <linux/platform_device.h>
++#include <linux/resource.h>
++#include <linux/debugfs.h>
++#include <linux/time.h>
++#include <linux/uaccess.h>
++
++#include "pci-layerscape-ep.h"
++
++struct ls_ep_dev *
++ls_pci_ep_find(struct ls_pcie *pcie, int dev_id)
++{
++	struct ls_ep_dev *ep;
++
++	list_for_each_entry(ep, &pcie->ep_list, node) {
++		if (ep->dev_id == dev_id)
++			return ep;
++	}
++
++	return NULL;
++}
++
++static void ls_pcie_try_cfg2(struct ls_pcie *pcie, int pf, int vf)
++{
++	if (pcie->sriov)
++		writel(PCIE_LCTRL0_VAL(pf, vf),
++		       pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
++}
++
++static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
++{
++	u32 header_type = 0;
++
++	header_type = readl(pcie->dbi + (PCI_HEADER_TYPE & ~0x3));
++	header_type = (header_type >> 16) & 0x7f;
++
++	return header_type == PCI_HEADER_TYPE_BRIDGE;
++}
++
++void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
++			       u64 cpu_addr, u64 pci_addr, u32 size)
++{
++	writel(PCIE_ATU_REGION_OUTBOUND | idx,
++	       pcie->dbi + PCIE_ATU_VIEWPORT);
++	writel(lower_32_bits(cpu_addr),
++	       pcie->dbi +  PCIE_ATU_LOWER_BASE);
++	writel(upper_32_bits(cpu_addr),
++	       pcie->dbi + PCIE_ATU_UPPER_BASE);
++	writel(lower_32_bits(cpu_addr + size - 1),
++	       pcie->dbi + PCIE_ATU_LIMIT);
++	writel(lower_32_bits(pci_addr),
++	       pcie->dbi + PCIE_ATU_LOWER_TARGET);
++	writel(upper_32_bits(pci_addr),
++	       pcie->dbi + PCIE_ATU_UPPER_TARGET);
++	writel(type, pcie->dbi + PCIE_ATU_CR1);
++	writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
++}
++
++/* Use bar match mode and MEM type as default */
++void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
++				     int bar, u64 phys)
++{
++	writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
++	writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
++	writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
++	writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
++	writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
++	       PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
++}
++
++void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep)
++{
++	ls_pcie_try_cfg2(ep->pcie, ep->pf_idx, ep->vf_idx);
++}
++
++void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
++{
++	if (size < 4 * 1024)
++		return;
++
++	switch (bar) {
++	case 0:
++		writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
++		break;
++	case 1:
++		writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
++		break;
++	case 2:
++		writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
++		writel(0, bar_base + PCI_BASE_ADDRESS_3);
++		break;
++	case 4:
++		writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
++		writel(0, bar_base + PCI_BASE_ADDRESS_5);
++		break;
++	default:
++		break;
++	}
++}
++
++void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size)
++{
++	struct ls_pcie *pcie = ep->pcie;
++	void *bar_base;
++
++	if (size < 4 * 1024)
++		return;
++
++	if (pcie->sriov)
++		bar_base = pcie->dbi;
++	else
++		bar_base = pcie->dbi + PCIE_NO_SRIOV_BAR_BASE;
++
++	ls_pcie_ep_dev_cfg_enable(ep);
++	ls_pcie_ep_setup_bar(bar_base, bar, size);
++}
++
++static int ls_pcie_ep_dev_init(struct ls_pcie *pcie, int pf_idx, int vf_idx)
++{
++	struct ls_ep_dev *ep;
++
++	ep = devm_kzalloc(pcie->dev, sizeof(*ep), GFP_KERNEL);
++	if (!ep)
++		return -ENOMEM;
++
++	ep->pcie = pcie;
++	ep->pf_idx = pf_idx;
++	ep->vf_idx = vf_idx;
++	if (vf_idx)
++		ep->dev_id = pf_idx + 4 + 4 * (vf_idx - 1);
++	else
++		ep->dev_id = pf_idx;
++
++	if (ep->vf_idx)
++		dev_set_name(&ep->dev, "pf%d-vf%d",
++			     ep->pf_idx,
++			     ep->vf_idx);
++	else
++		dev_set_name(&ep->dev, "pf%d",
++			     ep->pf_idx);
++
++	list_add_tail(&ep->node, &pcie->ep_list);
++
++	return 0;
++}
++
++static int ls_pcie_ep_init(struct ls_pcie *pcie)
++{
++	u32 sriov_header;
++	int pf, vf, i, j;
++
++	sriov_header = readl(pcie->dbi + PCIE_SRIOV_POS);
++
++	if (PCI_EXT_CAP_ID(sriov_header) == PCI_EXT_CAP_ID_SRIOV) {
++		pcie->sriov = PCIE_SRIOV_POS;
++		pf = PCIE_PF_NUM;
++		vf = PCIE_VF_NUM;
++	} else {
++		pcie->sriov = 0;
++		pf = 1;
++		vf = 0;
++	}
++
++	for (i = 0; i < pf; i++) {
++		for (j = 0; j <= vf; j++)
++			ls_pcie_ep_dev_init(pcie, i, j);
++	}
++
++	return 0;
++}
++
++static struct ls_pcie_ep_drvdata ls1043_drvdata = {
++	.lut_offset = 0x10000,
++	.ltssm_shift = 24,
++	.lut_dbg = 0x7fc,
++};
++
++static struct ls_pcie_ep_drvdata ls1046_drvdata = {
++	.lut_offset = 0x80000,
++	.ltssm_shift = 24,
++	.lut_dbg = 0x407fc,
++};
++
++static struct ls_pcie_ep_drvdata ls2080_drvdata = {
++	.lut_offset = 0x80000,
++	.ltssm_shift = 0,
++	.lut_dbg = 0x7fc,
++};
++
++static const struct of_device_id ls_pcie_ep_of_match[] = {
++	{ .compatible = "fsl,ls1021a-pcie", },
++	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
++	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
++	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
++	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, ls_pcie_ep_of_match);
++
++static int ls_pcie_ep_probe(struct platform_device *pdev)
++{
++	struct ls_pcie *pcie;
++	struct resource *dbi_base, *cfg_res;
++	const struct of_device_id *match;
++	int ret;
++
++	match = of_match_device(ls_pcie_ep_of_match, &pdev->dev);
++	if (!match)
++		return -ENODEV;
++
++	pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
++	if (!pcie)
++		return -ENOMEM;
++
++	pcie->dev = &pdev->dev;
++	INIT_LIST_HEAD(&pcie->ep_list);
++
++	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
++	pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
++	if (IS_ERR(pcie->dbi)) {
++		dev_err(&pdev->dev, "missing *regs* space\n");
++		return PTR_ERR(pcie->dbi);
++	}
++
++	pcie->drvdata = match->data;
++	pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
++
++	if (ls_pcie_is_bridge(pcie))
++		return -ENODEV;
++
++	dev_info(pcie->dev, "in EP mode\n");
++
++	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
++	if (cfg_res)
++		pcie->out_base = cfg_res->start;
++	else {
++		dev_err(&pdev->dev, "missing *config* space\n");
++		return -ENODEV;
++	}
++
++	ret = ls_pcie_ep_init(pcie);
++	if (ret)
++		return ret;
++
++	ls_pcie_ep_dbgfs_init(pcie);
++
++	platform_set_drvdata(pdev, pcie);
++
++	return 0;
++}
++
++static int ls_pcie_ep_dev_remove(struct ls_ep_dev *ep)
++{
++	list_del(&ep->node);
++
++	return 0;
++}
++
++static int ls_pcie_ep_remove(struct platform_device *pdev)
++{
++	struct ls_pcie *pcie = platform_get_drvdata(pdev);
++	struct ls_ep_dev *ep, *tmp;
++
++	if (!pcie)
++		return 0;
++
++	ls_pcie_ep_dbgfs_remove(pcie);
++
++	list_for_each_entry_safe(ep, tmp, &pcie->ep_list, node)
++		ls_pcie_ep_dev_remove(ep);
++
++	return 0;
++}
++
++static struct platform_driver ls_pcie_ep_driver = {
++	.driver = {
++		.name = "ls-pcie-ep",
++		.owner = THIS_MODULE,
++		.of_match_table = ls_pcie_ep_of_match,
++	},
++	.probe = ls_pcie_ep_probe,
++	.remove = ls_pcie_ep_remove,
++};
++
++module_platform_driver(ls_pcie_ep_driver);
++
++MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
++MODULE_DESCRIPTION("Freescale Layerscape PCIe EP driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/pci/host/pci-layerscape-ep.h
+@@ -0,0 +1,115 @@
++/*
++ * PCIe Endpoint driver for Freescale Layerscape SoCs
++ *
++ * Copyright (C) 2015 Freescale Semiconductor.
++ *
++  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++#ifndef _PCIE_LAYERSCAPE_EP_H
++#define _PCIE_LAYERSCAPE_EP_H
++
++#include <linux/device.h>
++
++/* Synopsis specific PCIE configuration registers */
++#define PCIE_ATU_VIEWPORT		0x900
++#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
++#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
++#define PCIE_ATU_REGION_INDEX3		(0x3 << 0)
++#define PCIE_ATU_REGION_INDEX2		(0x2 << 0)
++#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
++#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
++#define PCIE_ATU_CR1			0x904
++#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
++#define PCIE_ATU_TYPE_IO		(0x2 << 0)
++#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
++#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
++#define PCIE_ATU_CR2			0x908
++#define PCIE_ATU_ENABLE			(0x1 << 31)
++#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
++#define PCIE_ATU_LOWER_BASE		0x90C
++#define PCIE_ATU_UPPER_BASE		0x910
++#define PCIE_ATU_LIMIT			0x914
++#define PCIE_ATU_LOWER_TARGET		0x918
++#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
++#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
++#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
++#define PCIE_ATU_UPPER_TARGET		0x91C
++
++/* PEX internal configuration registers */
++#define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */
++
++/* PEX LUT registers */
++#define PCIE_LUT_BASE		0x80000
++#define PCIE_LUT_DBG		0x7FC /* PEX LUT Debug register */
++
++#define PCIE_LUT_LCTRL0		0x7F8
++
++#define PCIE_ATU_BAR_NUM(bar)	((bar) << 8)
++#define PCIE_LCTRL0_CFG2_ENABLE	(1 << 31)
++#define PCIE_LCTRL0_VF(vf)	((vf) << 22)
++#define PCIE_LCTRL0_PF(pf)	((pf) << 16)
++#define PCIE_LCTRL0_VF_ACTIVE	(1 << 21)
++#define PCIE_LCTRL0_VAL(pf, vf)	(PCIE_LCTRL0_PF(pf) |			   \
++				 PCIE_LCTRL0_VF(vf) |			   \
++				 ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
++				 PCIE_LCTRL0_CFG2_ENABLE)
++
++#define PCIE_NO_SRIOV_BAR_BASE	0x1000
++
++#define PCIE_SRIOV_POS		0x178
++#define PCIE_PF_NUM		2
++#define PCIE_VF_NUM		64
++
++struct ls_pcie_ep_drvdata {
++	u32 lut_offset;
++	u32 ltssm_shift;
++	u32 lut_dbg;
++};
++
++struct ls_pcie {
++	struct list_head	ep_list;
++	struct device		*dev;
++	struct dentry		*dir;
++	const struct ls_pcie_ep_drvdata *drvdata;
++	void __iomem		*dbi;
++	void __iomem		*lut;
++	phys_addr_t		out_base;
++	int			sriov;
++	int			index;
++};
++
++struct ls_ep_dev {
++	struct list_head	node;
++	struct ls_pcie		*pcie;
++	struct device		dev;
++	struct dentry		*dir;
++	int			pf_idx;
++	int			vf_idx;
++	int			dev_id;
++	void			*driver_data;
++};
++
++struct ls_ep_dev *ls_pci_ep_find(struct ls_pcie *pcie, int dev_id);
++
++void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
++			      u64 cpu_addr, u64 pci_addr, u32 size);
++
++/* Use bar match mode and MEM type as default */
++void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
++				     int bar, u64 phys);
++
++void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size);
++
++
++void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep);
++
++int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie);
++int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie);
++
++#endif /* _PCIE_LAYERSCAPE_EP_H */
+--- a/drivers/pci/host/pci-layerscape.c
++++ b/drivers/pci/host/pci-layerscape.c
+@@ -33,14 +33,18 @@
+ 
+ /* PEX Internal Configuration Registers */
+ #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
++#define PCIE_ABSERR		0x8d0 /* Bridge Slave Error Response Register */
++#define PCIE_ABSERR_SETTING	0x9401 /* Forward error of non-posted request */
+ #define PCIE_DBI_RO_WR_EN	0x8bc /* DBI Read-Only Write Enable Register */
+ 
+-/* PEX LUT registers */
+-#define PCIE_LUT_DBG		0x7FC /* PEX LUT Debug Register */
++#define PCIE_IATU_NUM		6
++
++static void ls_pcie_host_init(struct pcie_port *pp);
+ 
+ struct ls_pcie_drvdata {
+ 	u32 lut_offset;
+ 	u32 ltssm_shift;
++	u32 lut_dbg;
+ 	struct pcie_host_ops *ops;
+ };
+ 
+@@ -86,6 +90,14 @@ static void ls_pcie_drop_msg_tlp(struct
+ 	iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
+ }
+ 
++static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
++{
++	int i;
++
++	for (i = 0; i < PCIE_IATU_NUM; i++)
++		dw_pcie_disable_outbound_atu(&pcie->pp, i);
++}
++
+ static int ls1021_pcie_link_up(struct pcie_port *pp)
+ {
+ 	u32 state;
+@@ -134,7 +146,7 @@ static int ls_pcie_link_up(struct pcie_p
+ 	struct ls_pcie *pcie = to_ls_pcie(pp);
+ 	u32 state;
+ 
+-	state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
++	state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
+ 		 pcie->drvdata->ltssm_shift) &
+ 		 LTSSM_STATE_MASK;
+ 
+@@ -144,6 +156,12 @@ static int ls_pcie_link_up(struct pcie_p
+ 	return 1;
+ }
+ 
++/* Forward error response of outbound non-posted requests */
++static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
++{
++	iowrite32(PCIE_ABSERR_SETTING, pcie->pp.dbi_base + PCIE_ABSERR);
++}
++
+ static void ls_pcie_host_init(struct pcie_port *pp)
+ {
+ 	struct ls_pcie *pcie = to_ls_pcie(pp);
+@@ -153,6 +171,10 @@ static void ls_pcie_host_init(struct pci
+ 	ls_pcie_clear_multifunction(pcie);
+ 	ls_pcie_drop_msg_tlp(pcie);
+ 	iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
++
++	ls_pcie_disable_outbound_atus(pcie);
++	ls_pcie_fix_error_response(pcie);
++	dw_pcie_setup_rc(pp);
+ }
+ 
+ static int ls_pcie_msi_host_init(struct pcie_port *pp,
+@@ -196,20 +218,40 @@ static struct ls_pcie_drvdata ls1021_drv
+ static struct ls_pcie_drvdata ls1043_drvdata = {
+ 	.lut_offset = 0x10000,
+ 	.ltssm_shift = 24,
++	.lut_dbg = 0x7fc,
++	.ops = &ls_pcie_host_ops,
++};
++
++static struct ls_pcie_drvdata ls1046_drvdata = {
++	.lut_offset = 0x80000,
++	.ltssm_shift = 24,
++	.lut_dbg = 0x407fc,
+ 	.ops = &ls_pcie_host_ops,
+ };
+ 
+ static struct ls_pcie_drvdata ls2080_drvdata = {
+ 	.lut_offset = 0x80000,
+ 	.ltssm_shift = 0,
++	.lut_dbg = 0x7fc,
++	.ops = &ls_pcie_host_ops,
++};
++
++static struct ls_pcie_drvdata ls2088_drvdata = {
++	.lut_offset = 0x80000,
++	.ltssm_shift = 0,
++	.lut_dbg = 0x407fc,
+ 	.ops = &ls_pcie_host_ops,
+ };
+ 
+ static const struct of_device_id ls_pcie_of_match[] = {
++	{ .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
+ 	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
+ 	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
++	{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
+ 	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
+ 	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
++	{ .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
++	{ .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata },
+ 	{ },
+ };
+ 
+--- a/drivers/pci/host/pcie-designware.c
++++ b/drivers/pci/host/pcie-designware.c
+@@ -478,6 +478,12 @@ int dw_pcie_wait_for_link(struct pcie_po
+ 	return -ETIMEDOUT;
+ }
+ 
++void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index)
++{
++	dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index);
++	dw_pcie_writel_rc(pp, PCIE_ATU_CR2, 0);
++}
++
+ int dw_pcie_link_up(struct pcie_port *pp)
+ {
+ 	u32 val;
+--- a/drivers/pci/host/pcie-designware.h
++++ b/drivers/pci/host/pcie-designware.h
+@@ -82,5 +82,6 @@ int dw_pcie_wait_for_link(struct pcie_po
+ int dw_pcie_link_up(struct pcie_port *pp);
+ void dw_pcie_setup_rc(struct pcie_port *pp);
+ int dw_pcie_host_init(struct pcie_port *pp);
++void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index);
+ 
+ #endif /* _PCIE_DESIGNWARE_H */
+--- a/drivers/pci/pci.c
++++ b/drivers/pci/pci.c
+@@ -454,7 +454,7 @@ struct resource *pci_find_parent_resourc
+ 	pci_bus_for_each_resource(bus, r, i) {
+ 		if (!r)
+ 			continue;
+-		if (res->start && resource_contains(r, res)) {
++		if (resource_contains(r, res)) {
+ 
+ 			/*
+ 			 * If the window is prefetchable but the BAR is
+--- a/drivers/pci/pcie/portdrv_core.c
++++ b/drivers/pci/pcie/portdrv_core.c
+@@ -44,52 +44,30 @@ static void release_pcie_device(struct d
+ }
+ 
+ /**
+- * pcie_port_msix_add_entry - add entry to given array of MSI-X entries
+- * @entries: Array of MSI-X entries
+- * @new_entry: Index of the entry to add to the array
+- * @nr_entries: Number of entries already in the array
++ * pcibios_check_service_irqs - check irqs in the device tree
++ * @dev: PCI Express port to handle
++ * @irqs: Array of irqs to populate
++ * @mask: Bitmask of port capabilities returned by get_port_device_capability()
++ *
++ * Return value: 0 means no service irqs in the device tree
+  *
+- * Return value: Position of the added entry in the array
+  */
+-static int pcie_port_msix_add_entry(
+-	struct msix_entry *entries, int new_entry, int nr_entries)
++int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
+ {
+-	int j;
+-
+-	for (j = 0; j < nr_entries; j++)
+-		if (entries[j].entry == new_entry)
+-			return j;
+-
+-	entries[j].entry = new_entry;
+-	return j;
++	return 0;
+ }
+ 
+ /**
+  * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port
+  * @dev: PCI Express port to handle
+- * @vectors: Array of interrupt vectors to populate
++ * @irqs: Array of interrupt vectors to populate
+  * @mask: Bitmask of port capabilities returned by get_port_device_capability()
+  *
+  * Return value: 0 on success, error code on failure
+  */
+-static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
++static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask)
+ {
+-	struct msix_entry *msix_entries;
+-	int idx[PCIE_PORT_DEVICE_MAXSERVICES];
+-	int nr_entries, status, pos, i, nvec;
+-	u16 reg16;
+-	u32 reg32;
+-
+-	nr_entries = pci_msix_vec_count(dev);
+-	if (nr_entries < 0)
+-		return nr_entries;
+-	BUG_ON(!nr_entries);
+-	if (nr_entries > PCIE_PORT_MAX_MSIX_ENTRIES)
+-		nr_entries = PCIE_PORT_MAX_MSIX_ENTRIES;
+-
+-	msix_entries = kzalloc(sizeof(*msix_entries) * nr_entries, GFP_KERNEL);
+-	if (!msix_entries)
+-		return -ENOMEM;
++	int nr_entries, entry, nvec = 0;
+ 
+ 	/*
+ 	 * Allocate as many entries as the port wants, so that we can check
+@@ -97,20 +75,13 @@ static int pcie_port_enable_msix(struct
+ 	 * equal to the number of entries this port actually uses, we'll happily
+ 	 * go through without any tricks.
+ 	 */
+-	for (i = 0; i < nr_entries; i++)
+-		msix_entries[i].entry = i;
+-
+-	status = pci_enable_msix_exact(dev, msix_entries, nr_entries);
+-	if (status)
+-		goto Exit;
+-
+-	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+-		idx[i] = -1;
+-	status = -EIO;
+-	nvec = 0;
++	nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSIX_ENTRIES,
++			PCI_IRQ_MSIX);
++	if (nr_entries < 0)
++		return nr_entries;
+ 
+ 	if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) {
+-		int entry;
++		u16 reg16;
+ 
+ 		/*
+ 		 * The code below follows the PCI Express Base Specification 2.0
+@@ -125,18 +96,16 @@ static int pcie_port_enable_msix(struct
+ 		pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16);
+ 		entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
+ 		if (entry >= nr_entries)
+-			goto Error;
++			goto out_free_irqs;
+ 
+-		i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
+-		if (i == nvec)
+-			nvec++;
++		irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pci_irq_vector(dev, entry);
++		irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pci_irq_vector(dev, entry);
+ 
+-		idx[PCIE_PORT_SERVICE_PME_SHIFT] = i;
+-		idx[PCIE_PORT_SERVICE_HP_SHIFT] = i;
++		nvec = max(nvec, entry + 1);
+ 	}
+ 
+ 	if (mask & PCIE_PORT_SERVICE_AER) {
+-		int entry;
++		u32 reg32, pos;
+ 
+ 		/*
+ 		 * The code below follows Section 7.10.10 of the PCI Express
+@@ -151,13 +120,11 @@ static int pcie_port_enable_msix(struct
+ 		pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
+ 		entry = reg32 >> 27;
+ 		if (entry >= nr_entries)
+-			goto Error;
++			goto out_free_irqs;
+ 
+-		i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
+-		if (i == nvec)
+-			nvec++;
++		irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, entry);
+ 
+-		idx[PCIE_PORT_SERVICE_AER_SHIFT] = i;
++		nvec = max(nvec, entry + 1);
+ 	}
+ 
+ 	/*
+@@ -165,41 +132,54 @@ static int pcie_port_enable_msix(struct
+ 	 * what we have.  Otherwise, the port has some extra entries not for the
+ 	 * services we know and we need to work around that.
+ 	 */
+-	if (nvec == nr_entries) {
+-		status = 0;
+-	} else {
++	if (nvec != nr_entries) {
+ 		/* Drop the temporary MSI-X setup */
+-		pci_disable_msix(dev);
++		pci_free_irq_vectors(dev);
+ 
+ 		/* Now allocate the MSI-X vectors for real */
+-		status = pci_enable_msix_exact(dev, msix_entries, nvec);
+-		if (status)
+-			goto Exit;
++		nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec,
++				PCI_IRQ_MSIX);
++		if (nr_entries < 0)
++			return nr_entries;
+ 	}
+ 
+-	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+-		vectors[i] = idx[i] >= 0 ? msix_entries[idx[i]].vector : -1;
+-
+- Exit:
+-	kfree(msix_entries);
+-	return status;
++	return 0;
+ 
+- Error:
+-	pci_disable_msix(dev);
+-	goto Exit;
++out_free_irqs:
++	pci_free_irq_vectors(dev);
++	return -EIO;
+ }
+ 
+ /**
+- * init_service_irqs - initialize irqs for PCI Express port services
++ * pcie_init_service_irqs - initialize irqs for PCI Express port services
+  * @dev: PCI Express port to handle
+  * @irqs: Array of irqs to populate
+  * @mask: Bitmask of port capabilities returned by get_port_device_capability()
+  *
+  * Return value: Interrupt mode associated with the port
+  */
+-static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
++static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
+ {
+-	int i, irq = -1;
++	unsigned flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
++	int ret, i;
++	int irq = -1;
++
++	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
++		irqs[i] = -1;
++
++	/* Check if some platforms owns independent irq pins for AER/PME etc.
++	 * Some platforms may own independent AER/PME interrupts and set
++	 * them in the device tree file.
++	 */
++	ret = pcibios_check_service_irqs(dev, irqs, mask);
++	if (ret) {
++		if (dev->irq)
++			irq = dev->irq;
++		for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
++			if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
++				irqs[i] = irq;
++		return 0;
++	}
+ 
+ 	/*
+ 	 * If MSI cannot be used for PCIe PME or hotplug, we have to use
+@@ -207,41 +187,25 @@ static int init_service_irqs(struct pci_
+ 	 */
+ 	if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) ||
+ 	    ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) {
+-		if (dev->irq)
+-			irq = dev->irq;
+-		goto no_msi;
++		flags &= ~PCI_IRQ_MSI;
++	} else {
++		/* Try to use MSI-X if supported */
++		if (!pcie_port_enable_msix(dev, irqs, mask))
++			return 0;
+ 	}
+ 
+-	/* Try to use MSI-X if supported */
+-	if (!pcie_port_enable_msix(dev, irqs, mask))
+-		return 0;
+-
+-	/*
+-	 * We're not going to use MSI-X, so try MSI and fall back to INTx.
+-	 * If neither MSI/MSI-X nor INTx available, try other interrupt.  On
+-	 * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
+-	 */
+-	if (!pci_enable_msi(dev) || dev->irq)
+-		irq = dev->irq;
++	ret = pci_alloc_irq_vectors(dev, 1, 1, flags);
++	if (ret < 0)
++		return -ENODEV;
+ 
+- no_msi:
+-	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
+-		irqs[i] = irq;
+-	irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
++	for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
++		if (i != PCIE_PORT_SERVICE_VC_SHIFT)
++			irqs[i] = pci_irq_vector(dev, 0);
++	}
+ 
+-	if (irq < 0)
+-		return -ENODEV;
+ 	return 0;
+ }
+ 
+-static void cleanup_service_irqs(struct pci_dev *dev)
+-{
+-	if (dev->msix_enabled)
+-		pci_disable_msix(dev);
+-	else if (dev->msi_enabled)
+-		pci_disable_msi(dev);
+-}
+-
+ /**
+  * get_port_device_capability - discover capabilities of a PCI Express port
+  * @dev: PCI Express port to examine
+@@ -378,7 +342,7 @@ int pcie_port_device_register(struct pci
+ 	 * that can be used in the absence of irqs.  Allow them to determine
+ 	 * if that is to be used.
+ 	 */
+-	status = init_service_irqs(dev, irqs, capabilities);
++	status = pcie_init_service_irqs(dev, irqs, capabilities);
+ 	if (status) {
+ 		capabilities &= PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_HP;
+ 		if (!capabilities)
+@@ -401,7 +365,7 @@ int pcie_port_device_register(struct pci
+ 	return 0;
+ 
+ error_cleanup_irqs:
+-	cleanup_service_irqs(dev);
++	pci_free_irq_vectors(dev);
+ error_disable:
+ 	pci_disable_device(dev);
+ 	return status;
+@@ -469,7 +433,7 @@ static int remove_iter(struct device *de
+ void pcie_port_device_remove(struct pci_dev *dev)
+ {
+ 	device_for_each_child(&dev->dev, NULL, remove_iter);
+-	cleanup_service_irqs(dev);
++	pci_free_irq_vectors(dev);
+ 	pci_disable_device(dev);
+ }
+ 
+@@ -499,7 +463,6 @@ static int pcie_port_probe_service(struc
+ 	if (status)
+ 		return status;
+ 
+-	dev_printk(KERN_DEBUG, dev, "service driver %s loaded\n", driver->name);
+ 	get_device(dev);
+ 	return 0;
+ }
+@@ -524,8 +487,6 @@ static int pcie_port_remove_service(stru
+ 	pciedev = to_pcie_device(dev);
+ 	driver = to_service_driver(dev->driver);
+ 	if (driver && driver->remove) {
+-		dev_printk(KERN_DEBUG, dev, "unloading service driver %s\n",
+-			driver->name);
+ 		driver->remove(pciedev);
+ 		put_device(dev);
+ 	}
+--- a/drivers/pci/quirks.c
++++ b/drivers/pci/quirks.c
+@@ -3333,6 +3333,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
+ 
++/*
++ * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
++ * bus reset. Link state of device does not comes UP and so config space
++ * never accessible again.
++ */
++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
++
+ static void quirk_no_pm_reset(struct pci_dev *dev)
+ {
+ 	/*
+@@ -4677,3 +4684,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
+ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
++
++/* Freescale PCIe doesn't support MSI in RC mode */
++static void quirk_fsl_no_msi(struct pci_dev *pdev)
++{
++	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
++		pdev->no_msi = 1;
++}
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -1825,6 +1825,7 @@ void pcibios_release_device(struct pci_d
+ void pcibios_penalize_isa_irq(int irq, int active);
+ int pcibios_alloc_irq(struct pci_dev *dev);
+ void pcibios_free_irq(struct pci_dev *dev);
++int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
+ 
+ #ifdef CONFIG_HIBERNATE_CALLBACKS
+ extern struct dev_pm_ops pcibios_pm_ops;
diff --git a/target/linux/layerscape/patches-4.14/709-mdio-phy-support-layerscape.patch b/target/linux/layerscape/patches-4.9/703-phy-support-layerscape.patch
similarity index 78%
rename from target/linux/layerscape/patches-4.14/709-mdio-phy-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/703-phy-support-layerscape.patch
index eeb4baaba..9c2327918 100644
--- a/target/linux/layerscape/patches-4.14/709-mdio-phy-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/703-phy-support-layerscape.patch
@@ -1,28 +1,35 @@
-From 8eb578a8c1eb55715a40f02790e43aba4a528c38 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:51 +0800
-Subject: [PATCH 15/40] mdio-phy: support layerscae
-This is an integrated patch of mdio-phy for layerscape
+From 8949ebc0c5b982eab7ca493dad7b86c30befa6ec Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:01:30 +0800
+Subject: [PATCH 09/30] phy: support layerscape
 
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
-Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
-Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
+This is an integrated patch for layerscape mdio-phy support.
+
+Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
+Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
 Signed-off-by: costi <constantin.tudor@freescale.com>
 Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
-Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/net/phy/Kconfig         |    6 +
- drivers/net/phy/Makefile        |    1 +
- drivers/net/phy/fsl_backplane.c | 1358 +++++++++++++++++++++++++++++++
+ drivers/net/phy/Kconfig         |   11 +
+ drivers/net/phy/Makefile        |    2 +
+ drivers/net/phy/aquantia.c      |   28 +
+ drivers/net/phy/cortina.c       |  118 ++++
+ drivers/net/phy/fsl_backplane.c | 1358 +++++++++++++++++++++++++++++++++++++++
+ drivers/net/phy/marvell.c       |    2 +-
+ drivers/net/phy/phy.c           |   23 +-
+ drivers/net/phy/phy_device.c    |    6 +-
  drivers/net/phy/swphy.c         |    1 +
- include/linux/phy.h             |    3 +
- 5 files changed, 1369 insertions(+)
+ include/linux/phy.h             |    6 +
+ 10 files changed, 1547 insertions(+), 8 deletions(-)
+ create mode 100644 drivers/net/phy/cortina.c
  create mode 100644 drivers/net/phy/fsl_backplane.c
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -90,6 +90,12 @@ config MDIO_BUS_MUX_MMIOREG
+@@ -89,6 +89,12 @@ config MDIO_BUS_MUX_MMIOREG
  config MDIO_CAVIUM
  	tristate
  
@@ -35,16 +42,208 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  config MDIO_GPIO
  	tristate "GPIO lib-based bitbanged MDIO buses"
  	depends on MDIO_BITBANG && GPIOLIB
+@@ -298,6 +304,11 @@ config CICADA_PHY
+ 	---help---
+ 	  Currently supports the cis8204
+ 
++config CORTINA_PHY
++	tristate "Cortina EDC CDR 10G Ethernet PHY"
++	---help---
++	  Currently supports the CS4340 phy.
++
+ config DAVICOM_PHY
+ 	tristate "Davicom PHYs"
+ 	---help---
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
-@@ -45,6 +45,7 @@ obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC)	+=
+@@ -30,6 +30,7 @@ obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC)	+=
  obj-$(CONFIG_MDIO_BUS_MUX_GPIO)	+= mdio-mux-gpio.o
  obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
  obj-$(CONFIG_MDIO_CAVIUM)	+= mdio-cavium.o
 +obj-$(CONFIG_MDIO_FSL_BACKPLANE) += fsl_backplane.o
  obj-$(CONFIG_MDIO_GPIO)		+= mdio-gpio.o
  obj-$(CONFIG_MDIO_HISI_FEMAC)	+= mdio-hisi-femac.o
- obj-$(CONFIG_MDIO_I2C)		+= mdio-i2c.o
+ obj-$(CONFIG_MDIO_MOXART)	+= mdio-moxart.o
+@@ -48,6 +49,7 @@ obj-$(CONFIG_BCM_CYGNUS_PHY)	+= bcm-cygn
+ obj-$(CONFIG_BCM_NET_PHYLIB)	+= bcm-phy-lib.o
+ obj-$(CONFIG_BROADCOM_PHY)	+= broadcom.o
+ obj-$(CONFIG_CICADA_PHY)	+= cicada.o
++obj-$(CONFIG_CORTINA_PHY)	+= cortina.o
+ obj-$(CONFIG_DAVICOM_PHY)	+= davicom.o
+ obj-$(CONFIG_DP83640_PHY)	+= dp83640.o
+ obj-$(CONFIG_DP83848_PHY)	+= dp83848.o
+--- a/drivers/net/phy/aquantia.c
++++ b/drivers/net/phy/aquantia.c
+@@ -21,6 +21,8 @@
+ #define PHY_ID_AQ1202	0x03a1b445
+ #define PHY_ID_AQ2104	0x03a1b460
+ #define PHY_ID_AQR105	0x03a1b4a2
++#define PHY_ID_AQR106	0x03a1b4d0
++#define PHY_ID_AQR107	0x03a1b4e0
+ #define PHY_ID_AQR405	0x03a1b4b0
+ 
+ #define PHY_AQUANTIA_FEATURES	(SUPPORTED_10000baseT_Full | \
+@@ -154,6 +156,30 @@ static struct phy_driver aquantia_driver
+ 	.read_status	= aquantia_read_status,
+ },
+ {
++	.phy_id		= PHY_ID_AQR106,
++	.phy_id_mask	= 0xfffffff0,
++	.name		= "Aquantia AQR106",
++	.features	= PHY_AQUANTIA_FEATURES,
++	.flags		= PHY_HAS_INTERRUPT,
++	.aneg_done	= aquantia_aneg_done,
++	.config_aneg    = aquantia_config_aneg,
++	.config_intr	= aquantia_config_intr,
++	.ack_interrupt	= aquantia_ack_interrupt,
++	.read_status	= aquantia_read_status,
++},
++{
++	.phy_id		= PHY_ID_AQR107,
++	.phy_id_mask	= 0xfffffff0,
++	.name		= "Aquantia AQR107",
++	.features	= PHY_AQUANTIA_FEATURES,
++	.flags		= PHY_HAS_INTERRUPT,
++	.aneg_done	= aquantia_aneg_done,
++	.config_aneg    = aquantia_config_aneg,
++	.config_intr	= aquantia_config_intr,
++	.ack_interrupt	= aquantia_ack_interrupt,
++	.read_status	= aquantia_read_status,
++},
++{
+ 	.phy_id		= PHY_ID_AQR405,
+ 	.phy_id_mask	= 0xfffffff0,
+ 	.name		= "Aquantia AQR405",
+@@ -173,6 +199,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_AQ1202, 0xfffffff0 },
+ 	{ PHY_ID_AQ2104, 0xfffffff0 },
+ 	{ PHY_ID_AQR105, 0xfffffff0 },
++	{ PHY_ID_AQR106, 0xfffffff0 },
++	{ PHY_ID_AQR107, 0xfffffff0 },
+ 	{ PHY_ID_AQR405, 0xfffffff0 },
+ 	{ }
+ };
+--- /dev/null
++++ b/drivers/net/phy/cortina.c
+@@ -0,0 +1,118 @@
++/*
++ *    Copyright 2017 NXP
++ *
++ *    This program is free software; you can redistribute it and/or modify
++ *    it under the terms of the GNU General Public License as published by
++ *    the Free Software Foundation; either version 2 of the License, or
++ *    (at your option) any later version.
++ *
++ *    This program is distributed in the hope that it will be useful,
++ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *    GNU General Public License for more details.
++ *
++ *    CORTINA is a registered trademark of Cortina Systems, Inc.
++ *
++ */
++#include <linux/module.h>
++#include <linux/phy.h>
++
++#define PHY_ID_CS4340	0x13e51002
++
++#define VILLA_GLOBAL_CHIP_ID_LSB			0x0
++#define VILLA_GLOBAL_CHIP_ID_MSB			0x1
++
++#define VILLA_GLOBAL_GPIO_1_INTS			0x017
++
++static int cortina_read_reg(struct phy_device *phydev, u16 regnum)
++{
++	return mdiobus_read(phydev->mdio.bus, phydev->mdio.addr,
++			    MII_ADDR_C45 | regnum);
++}
++
++static int cortina_config_aneg(struct phy_device *phydev)
++{
++	phydev->supported = SUPPORTED_10000baseT_Full;
++	phydev->advertising = SUPPORTED_10000baseT_Full;
++
++	return 0;
++}
++
++static int cortina_read_status(struct phy_device *phydev)
++{
++	int gpio_int_status, ret = 0;
++
++	gpio_int_status = cortina_read_reg(phydev, VILLA_GLOBAL_GPIO_1_INTS);
++	if (gpio_int_status < 0) {
++		ret = gpio_int_status;
++		goto err;
++	}
++
++	if (gpio_int_status & 0x8) {
++		/* up when edc_convergedS set */
++		phydev->speed = SPEED_10000;
++		phydev->duplex = DUPLEX_FULL;
++		phydev->link = 1;
++	} else {
++		phydev->link = 0;
++	}
++
++err:
++	return ret;
++}
++
++static int cortina_soft_reset(struct phy_device *phydev)
++{
++	return 0;
++}
++
++static int cortina_probe(struct phy_device *phydev)
++{
++	u32 phy_id = 0;
++	int id_lsb = 0, id_msb = 0;
++
++	/* Read device id from phy registers. */
++	id_lsb = cortina_read_reg(phydev, VILLA_GLOBAL_CHIP_ID_LSB);
++	if (id_lsb < 0)
++		return -ENXIO;
++
++	phy_id = id_lsb << 16;
++
++	id_msb = cortina_read_reg(phydev, VILLA_GLOBAL_CHIP_ID_MSB);
++	if (id_msb < 0)
++		return -ENXIO;
++
++	phy_id |= id_msb;
++
++	/* Make sure the device tree binding matched the driver with the
++	 * right device.
++	 */
++	if (phy_id != phydev->drv->phy_id) {
++		phydev_err(phydev, "Error matching phy with %s driver\n",
++			   phydev->drv->name);
++		return -ENODEV;
++	}
++
++	return 0;
++}
++
++static struct phy_driver cortina_driver[] = {
++{
++	.phy_id		= PHY_ID_CS4340,
++	.phy_id_mask	= 0xffffffff,
++	.name		= "Cortina CS4340",
++	.config_aneg	= cortina_config_aneg,
++	.read_status	= cortina_read_status,
++	.soft_reset	= cortina_soft_reset,
++	.probe		= cortina_probe,
++},
++};
++
++module_phy_driver(cortina_driver);
++
++static struct mdio_device_id __maybe_unused cortina_tbl[] = {
++	{ PHY_ID_CS4340, 0xffffffff},
++	{},
++};
++
++MODULE_DEVICE_TABLE(mdio, cortina_tbl);
 --- /dev/null
 +++ b/drivers/net/phy/fsl_backplane.c
 @@ -0,0 +1,1358 @@
@@ -1406,6 +1605,123 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +MODULE_DESCRIPTION("Freescale Backplane driver");
 +MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
 +MODULE_LICENSE("GPL v2");
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -591,7 +591,7 @@ int phy_mii_ioctl(struct phy_device *phy
+ 		return 0;
+ 
+ 	case SIOCSHWTSTAMP:
+-		if (phydev->drv->hwtstamp)
++		if (phydev->drv && phydev->drv->hwtstamp)
+ 			return phydev->drv->hwtstamp(phydev, ifr);
+ 		/* fall through */
+ 
+@@ -616,6 +616,9 @@ static int phy_start_aneg_priv(struct ph
+ 	bool trigger = 0;
+ 	int err;
+ 
++	if (!phydev->drv)
++		return -EIO;
++
+ 	mutex_lock(&phydev->lock);
+ 
+ 	if (AUTONEG_DISABLE == phydev->autoneg)
+@@ -1015,7 +1018,7 @@ void phy_state_machine(struct work_struc
+ 
+ 	old_state = phydev->state;
+ 
+-	if (phydev->drv->link_change_notify)
++	if (phydev->drv && phydev->drv->link_change_notify)
+ 		phydev->drv->link_change_notify(phydev);
+ 
+ 	switch (phydev->state) {
+@@ -1317,6 +1320,9 @@ EXPORT_SYMBOL(phy_write_mmd_indirect);
+  */
+ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
+ {
++	if (!phydev->drv)
++		return -EIO;
++
+ 	/* According to 802.3az,the EEE is supported only in full duplex-mode.
+ 	 * Also EEE feature is active when core is operating with MII, GMII
+ 	 * or RGMII (all kinds). Internal PHYs are also allowed to proceed and
+@@ -1394,6 +1400,9 @@ EXPORT_SYMBOL(phy_init_eee);
+  */
+ int phy_get_eee_err(struct phy_device *phydev)
+ {
++	if (!phydev->drv)
++		return -EIO;
++
+ 	return phy_read_mmd_indirect(phydev, MDIO_PCS_EEE_WK_ERR, MDIO_MMD_PCS);
+ }
+ EXPORT_SYMBOL(phy_get_eee_err);
+@@ -1410,6 +1419,9 @@ int phy_ethtool_get_eee(struct phy_devic
+ {
+ 	int val;
+ 
++	if (!phydev->drv)
++		return -EIO;
++
+ 	/* Get Supported EEE */
+ 	val = phy_read_mmd_indirect(phydev, MDIO_PCS_EEE_ABLE, MDIO_MMD_PCS);
+ 	if (val < 0)
+@@ -1443,6 +1455,9 @@ int phy_ethtool_set_eee(struct phy_devic
+ {
+ 	int val = ethtool_adv_to_mmd_eee_adv_t(data->advertised);
+ 
++	if (!phydev->drv)
++		return -EIO;
++
+ 	/* Mask prohibited EEE modes */
+ 	val &= ~phydev->eee_broken_modes;
+ 
+@@ -1454,7 +1469,7 @@ EXPORT_SYMBOL(phy_ethtool_set_eee);
+ 
+ int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
+ {
+-	if (phydev->drv->set_wol)
++	if (phydev->drv && phydev->drv->set_wol)
+ 		return phydev->drv->set_wol(phydev, wol);
+ 
+ 	return -EOPNOTSUPP;
+@@ -1463,7 +1478,7 @@ EXPORT_SYMBOL(phy_ethtool_set_wol);
+ 
+ void phy_ethtool_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
+ {
+-	if (phydev->drv->get_wol)
++	if (phydev->drv && phydev->drv->get_wol)
+ 		phydev->drv->get_wol(phydev, wol);
+ }
+ EXPORT_SYMBOL(phy_ethtool_get_wol);
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1046,7 +1046,7 @@ int phy_suspend(struct phy_device *phyde
+ 	if (wol.wolopts)
+ 		return -EBUSY;
+ 
+-	if (phydrv->suspend)
++	if (phydev->drv && phydrv->suspend)
+ 		ret = phydrv->suspend(phydev);
+ 
+ 	if (ret)
+@@ -1063,7 +1063,7 @@ int phy_resume(struct phy_device *phydev
+ 	struct phy_driver *phydrv = to_phy_driver(phydev->mdio.dev.driver);
+ 	int ret = 0;
+ 
+-	if (phydrv->resume)
++	if (phydev->drv && phydrv->resume)
+ 		ret = phydrv->resume(phydev);
+ 
+ 	if (ret)
+@@ -1720,7 +1720,7 @@ static int phy_remove(struct device *dev
+ 	phydev->state = PHY_DOWN;
+ 	mutex_unlock(&phydev->lock);
+ 
+-	if (phydev->drv->remove)
++	if (phydev->drv && phydev->drv->remove)
+ 		phydev->drv->remove(phydev);
+ 	phydev->drv = NULL;
+ 
 --- a/drivers/net/phy/swphy.c
 +++ b/drivers/net/phy/swphy.c
 @@ -77,6 +77,7 @@ static const struct swmii_regs duplex[]
@@ -1418,20 +1734,30 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	case 100:
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -87,6 +87,7 @@ typedef enum {
- 	PHY_INTERFACE_MODE_XAUI,
- 	/* 10GBASE-KR, XFI, SFI - single lane 10G Serdes */
- 	PHY_INTERFACE_MODE_10GKR,
+@@ -81,6 +81,7 @@ typedef enum {
+ 	PHY_INTERFACE_MODE_MOCA,
+ 	PHY_INTERFACE_MODE_QSGMII,
+ 	PHY_INTERFACE_MODE_TRGMII,
 +	PHY_INTERFACE_MODE_2500SGMII,
  	PHY_INTERFACE_MODE_MAX,
  } phy_interface_t;
  
-@@ -159,6 +160,8 @@ static inline const char *phy_modes(phy_
- 		return "xaui";
- 	case PHY_INTERFACE_MODE_10GKR:
- 		return "10gbase-kr";
+@@ -126,6 +127,8 @@ static inline const char *phy_modes(phy_
+ 		return "qsgmii";
+ 	case PHY_INTERFACE_MODE_TRGMII:
+ 		return "trgmii";
 +	case PHY_INTERFACE_MODE_2500SGMII:
 +		return "sgmii-2500";
  	default:
  		return "unknown";
  	}
+@@ -791,6 +794,9 @@ int phy_stop_interrupts(struct phy_devic
+ 
+ static inline int phy_read_status(struct phy_device *phydev)
+ {
++	if (!phydev->drv)
++		return -EIO;
++
+ 	return phydev->drv->read_status(phydev);
+ }
+ 
diff --git a/target/linux/layerscape/patches-4.14/708-mc-bus-support-layerscape.patch b/target/linux/layerscape/patches-4.9/704-fsl-mc-layerscape-support.patch
similarity index 52%
rename from target/linux/layerscape/patches-4.14/708-mc-bus-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/704-fsl-mc-layerscape-support.patch
index 8d2ba1a19..52c099203 100644
--- a/target/linux/layerscape/patches-4.14/708-mc-bus-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/704-fsl-mc-layerscape-support.patch
@@ -1,101 +1,628 @@
-From 2aaf8e8caef3ec4c2c155421f62f983892c49387 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Fri, 16 Nov 2018 12:20:04 +0800
-Subject: [PATCH 13/39] mc-bus: support layerscape
-This is an integrated patch of mc-bus for layerscape
+From ab7b47676f9334bb55f80e0ac096c7aa289810e2 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 16:44:34 +0800
+Subject: [PATCH 10/32] fsl-mc: layerscape support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is an integrated patch for layerscape mc-bus support.
 
-Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
-Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
-Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
-Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
-Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
-Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
-Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
-Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
-Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
-Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
-Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
-Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
 Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
-Signed-off-by: Stuart Yoder <stuyoder@gmail.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
+Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
+Signed-off-by: Shiva Kerdel <shiva@exdev.nl>
+Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
+Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
+Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/bus/Kconfig                           |    2 +
+ Documentation/ABI/stable/sysfs-bus-fsl-mc     |   13 +
+ Documentation/ioctl/ioctl-number.txt          |    1 +
+ Documentation/networking/dpaa2/index.rst      |    8 +
+ Documentation/networking/dpaa2/overview.rst   |  408 +++++
+ MAINTAINERS                                   |   11 +-
+ drivers/bus/Kconfig                           |    3 +
  drivers/bus/Makefile                          |    4 +
  drivers/bus/fsl-mc/Kconfig                    |   23 +
- drivers/bus/fsl-mc/Makefile                   |   21 +
- .../{staging/fsl-mc/bus => bus/fsl-mc}/dpbp.c |   97 +-
- .../fsl-mc/bus => bus/fsl-mc}/dpcon.c         |  103 +-
+ drivers/bus/fsl-mc/Makefile                   |   22 +
+ drivers/bus/fsl-mc/dpbp.c                     |  186 +++
+ drivers/bus/fsl-mc/dpcon.c                    |  222 +++
  drivers/bus/fsl-mc/dpmcp.c                    |   99 ++
- .../fsl-mc/bus => bus/fsl-mc}/dprc-driver.c   |   96 +-
- .../{staging/fsl-mc/bus => bus/fsl-mc}/dprc.c |  288 +----
- .../bus => bus/fsl-mc}/fsl-mc-allocator.c     |  112 +-
- .../fsl-mc/bus => bus/fsl-mc}/fsl-mc-bus.c    |  305 ++++-
- .../fsl-mc/bus => bus/fsl-mc}/fsl-mc-msi.c    |   16 +-
- drivers/bus/fsl-mc/fsl-mc-private.h           |  223 ++++
- drivers/bus/fsl-mc/fsl-mc-restool.c           |  219 ++++
- .../fsl-mc/bus => bus/fsl-mc}/mc-io.c         |   36 +-
- .../fsl-mc/bus => bus/fsl-mc}/mc-sys.c        |   33 +-
+ .../fsl-mc/bus => bus/fsl-mc}/dprc-driver.c   |  180 ++-
+ drivers/bus/fsl-mc/dprc.c                     |  575 +++++++
+ .../bus => bus/fsl-mc}/fsl-mc-allocator.c     |  195 ++-
+ .../fsl-mc/bus => bus/fsl-mc}/fsl-mc-bus.c    |  523 +++++--
+ drivers/bus/fsl-mc/fsl-mc-iommu.c             |   78 +
+ .../fsl-mc/bus => bus/fsl-mc}/fsl-mc-msi.c    |   34 +-
+ drivers/bus/fsl-mc/fsl-mc-private.h           |  223 +++
+ drivers/bus/fsl-mc/fsl-mc-restool.c           |  219 +++
+ .../fsl-mc/bus => bus/fsl-mc}/mc-io.c         |   80 +-
+ .../fsl-mc/bus => bus/fsl-mc}/mc-sys.c        |  105 +-
  drivers/irqchip/Kconfig                       |    6 +
  drivers/irqchip/Makefile                      |    1 +
- drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c   |   98 ++
- drivers/staging/fsl-dpaa2/ethernet/README     |    2 +-
- .../staging/fsl-dpaa2/ethernet/dpaa2-eth.c    |    2 +-
- .../staging/fsl-dpaa2/ethernet/dpaa2-eth.h    |    3 +-
- drivers/staging/fsl-dpaa2/ethernet/dpni.c     |    2 +-
+ .../irq-gic-v3-its-fsl-mc-msi.c               |   52 +-
+ drivers/staging/fsl-mc/Kconfig                |    1 +
+ drivers/staging/fsl-mc/Makefile               |    1 +
  drivers/staging/fsl-mc/TODO                   |   18 -
- drivers/staging/fsl-mc/bus/Kconfig            |   16 +-
- drivers/staging/fsl-mc/bus/Makefile           |   13 -
- drivers/staging/fsl-mc/bus/dpio/dpio-driver.c |    2 +-
- .../staging/fsl-mc/bus/dpio/dpio-service.c    |    2 +-
- drivers/staging/fsl-mc/bus/dpio/dpio.c        |   14 +-
- drivers/staging/fsl-mc/bus/dpmcp-cmd.h        |   56 -
- drivers/staging/fsl-mc/bus/dpmcp.h            |   60 -
+ drivers/staging/fsl-mc/bus/Kconfig            |   37 +-
+ drivers/staging/fsl-mc/bus/Makefile           |   17 +-
+ drivers/staging/fsl-mc/bus/dpbp.c             |  691 --------
+ drivers/staging/fsl-mc/bus/dpio/Makefile      |    8 +
+ drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h    |   50 +
+ drivers/staging/fsl-mc/bus/dpio/dpio-driver.c |  278 ++++
+ .../staging/fsl-mc/bus/dpio/dpio-service.c    |  780 +++++++++
+ drivers/staging/fsl-mc/bus/dpio/dpio.c        |  221 +++
+ drivers/staging/fsl-mc/bus/dpio/dpio.h        |   87 ++
+ .../staging/fsl-mc/bus/dpio/qbman-portal.c    | 1164 ++++++++++++++
+ .../staging/fsl-mc/bus/dpio/qbman-portal.h    |  505 ++++++
+ drivers/staging/fsl-mc/bus/dpmcp-cmd.h        |  140 --
+ drivers/staging/fsl-mc/bus/dpmcp.c            |  504 ------
+ drivers/staging/fsl-mc/bus/dpmcp.h            |  159 --
  drivers/staging/fsl-mc/bus/dpmng-cmd.h        |   58 -
- drivers/staging/fsl-mc/bus/dprc-cmd.h         |  451 --------
- drivers/staging/fsl-mc/bus/dprc.h             |  268 -----
- .../fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c    |    1 +
- include/linux/fsl/mc.h                        | 1020 +++++++++++++++++
+ drivers/staging/fsl-mc/bus/dpmng.c            |  107 --
+ drivers/staging/fsl-mc/bus/dprc-cmd.h         |  465 ------
+ drivers/staging/fsl-mc/bus/dprc.c             | 1388 -----------------
+ drivers/staging/fsl-mc/bus/fsl-mc-private.h   |   52 -
+ drivers/staging/fsl-mc/include/dpaa2-fd.h     |  681 ++++++++
+ drivers/staging/fsl-mc/include/dpaa2-global.h |  177 +++
+ drivers/staging/fsl-mc/include/dpaa2-io.h     |  178 +++
+ drivers/staging/fsl-mc/include/dpbp-cmd.h     |  185 ---
+ drivers/staging/fsl-mc/include/dpbp.h         |  220 ---
+ drivers/staging/fsl-mc/include/dpcon-cmd.h    |   62 -
+ drivers/staging/fsl-mc/include/dpmng.h        |   69 -
+ drivers/staging/fsl-mc/include/dpopr.h        |  112 ++
+ drivers/staging/fsl-mc/include/dprc.h         |  544 -------
+ drivers/staging/fsl-mc/include/mc-bus.h       |  111 --
+ drivers/staging/fsl-mc/include/mc-cmd.h       |  108 --
+ drivers/staging/fsl-mc/include/mc-sys.h       |   98 --
+ drivers/staging/fsl-mc/include/mc.h           |  201 ---
+ include/linux/fsl/mc.h                        | 1025 ++++++++++++
  include/uapi/linux/fsl_mc.h                   |   31 +
- 37 files changed, 2255 insertions(+), 1546 deletions(-)
+ 62 files changed, 8068 insertions(+), 5736 deletions(-)
+ create mode 100644 Documentation/ABI/stable/sysfs-bus-fsl-mc
+ create mode 100644 Documentation/networking/dpaa2/index.rst
+ create mode 100644 Documentation/networking/dpaa2/overview.rst
  create mode 100644 drivers/bus/fsl-mc/Kconfig
  create mode 100644 drivers/bus/fsl-mc/Makefile
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/dpbp.c (67%)
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/dpcon.c (70%)
+ create mode 100644 drivers/bus/fsl-mc/dpbp.c
+ create mode 100644 drivers/bus/fsl-mc/dpcon.c
  create mode 100644 drivers/bus/fsl-mc/dpmcp.c
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/dprc-driver.c (93%)
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/dprc.c (68%)
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-allocator.c (84%)
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-bus.c (76%)
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-msi.c (96%)
+ rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/dprc-driver.c (84%)
+ create mode 100644 drivers/bus/fsl-mc/dprc.c
+ rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-allocator.c (71%)
+ rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-bus.c (64%)
+ create mode 100644 drivers/bus/fsl-mc/fsl-mc-iommu.c
+ rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/fsl-mc-msi.c (89%)
  create mode 100644 drivers/bus/fsl-mc/fsl-mc-private.h
  create mode 100644 drivers/bus/fsl-mc/fsl-mc-restool.c
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/mc-io.c (89%)
- rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/mc-sys.c (90%)
- create mode 100644 drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
+ rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/mc-io.c (68%)
+ rename drivers/{staging/fsl-mc/bus => bus/fsl-mc}/mc-sys.c (66%)
+ rename drivers/{staging/fsl-mc/bus => irqchip}/irq-gic-v3-its-fsl-mc-msi.c (60%)
  delete mode 100644 drivers/staging/fsl-mc/TODO
+ delete mode 100644 drivers/staging/fsl-mc/bus/dpbp.c
+ create mode 100644 drivers/staging/fsl-mc/bus/dpio/Makefile
+ create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
+ create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
+ create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-service.c
+ create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.c
+ create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.h
+ create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
+ create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
  delete mode 100644 drivers/staging/fsl-mc/bus/dpmcp-cmd.h
+ delete mode 100644 drivers/staging/fsl-mc/bus/dpmcp.c
  delete mode 100644 drivers/staging/fsl-mc/bus/dpmcp.h
  delete mode 100644 drivers/staging/fsl-mc/bus/dpmng-cmd.h
+ delete mode 100644 drivers/staging/fsl-mc/bus/dpmng.c
  delete mode 100644 drivers/staging/fsl-mc/bus/dprc-cmd.h
- delete mode 100644 drivers/staging/fsl-mc/bus/dprc.h
+ delete mode 100644 drivers/staging/fsl-mc/bus/dprc.c
+ delete mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-private.h
+ create mode 100644 drivers/staging/fsl-mc/include/dpaa2-fd.h
+ create mode 100644 drivers/staging/fsl-mc/include/dpaa2-global.h
+ create mode 100644 drivers/staging/fsl-mc/include/dpaa2-io.h
+ delete mode 100644 drivers/staging/fsl-mc/include/dpbp-cmd.h
+ delete mode 100644 drivers/staging/fsl-mc/include/dpbp.h
+ delete mode 100644 drivers/staging/fsl-mc/include/dpcon-cmd.h
+ delete mode 100644 drivers/staging/fsl-mc/include/dpmng.h
+ create mode 100644 drivers/staging/fsl-mc/include/dpopr.h
+ delete mode 100644 drivers/staging/fsl-mc/include/dprc.h
+ delete mode 100644 drivers/staging/fsl-mc/include/mc-bus.h
+ delete mode 100644 drivers/staging/fsl-mc/include/mc-cmd.h
+ delete mode 100644 drivers/staging/fsl-mc/include/mc-sys.h
+ delete mode 100644 drivers/staging/fsl-mc/include/mc.h
  create mode 100644 include/linux/fsl/mc.h
  create mode 100644 include/uapi/linux/fsl_mc.h
 
+--- /dev/null
++++ b/Documentation/ABI/stable/sysfs-bus-fsl-mc
+@@ -0,0 +1,13 @@
++What:		/sys/bus/fsl-mc/devices/dprc.*/rescan
++Date:		March. 2018
++KernelVersion:	4.16
++Contact:	Ioana Ciornei <ioana.ciornei@nxp.com>
++Description:	Root dprc rescan attribute
++Users:		Userspace drivers and management tools
++
++What:		/sys/bus/fsl-mc/rescan
++Date:		March. 2018
++KernelVersion:	4.16
++Contact:	Ioana Ciornei <ioana.ciornei@nxp.com>
++Description:	Bus rescan attribute
++Users:		Userspace drivers and management tools
+--- a/Documentation/ioctl/ioctl-number.txt
++++ b/Documentation/ioctl/ioctl-number.txt
+@@ -170,6 +170,7 @@ Code  Seq#(hex)	Include File		Comments
+ 'R'	00-1F	linux/random.h		conflict!
+ 'R'	01	linux/rfkill.h		conflict!
+ 'R'	C0-DF	net/bluetooth/rfcomm.h
++'R'	E0	uapi/linux/fsl_mc.h
+ 'S'	all	linux/cdrom.h		conflict!
+ 'S'	80-81	scsi/scsi_ioctl.h	conflict!
+ 'S'	82-FF	scsi/scsi.h		conflict!
+--- /dev/null
++++ b/Documentation/networking/dpaa2/index.rst
+@@ -0,0 +1,8 @@
++===================
++DPAA2 Documentation
++===================
++
++.. toctree::
++   :maxdepth: 1
++
++   overview
+--- /dev/null
++++ b/Documentation/networking/dpaa2/overview.rst
+@@ -0,0 +1,408 @@
++.. include:: <isonum.txt>
++
++DPAA2 (Data Path Acceleration Architecture Gen2) Overview
++=========================================================
++
++:Copyright: |copy| 2015 Freescale Semiconductor Inc.
++:Copyright: |copy| 2018 NXP
++
++This document provides an overview of the Freescale DPAA2 architecture
++and how it is integrated into the Linux kernel.
++
++Introduction
++============
++
++DPAA2 is a hardware architecture designed for high-speeed network
++packet processing.  DPAA2 consists of sophisticated mechanisms for
++processing Ethernet packets, queue management, buffer management,
++autonomous L2 switching, virtual Ethernet bridging, and accelerator
++(e.g. crypto) sharing.
++
++A DPAA2 hardware component called the Management Complex (or MC) manages the
++DPAA2 hardware resources.  The MC provides an object-based abstraction for
++software drivers to use the DPAA2 hardware.
++The MC uses DPAA2 hardware resources such as queues, buffer pools, and
++network ports to create functional objects/devices such as network
++interfaces, an L2 switch, or accelerator instances.
++The MC provides memory-mapped I/O command interfaces (MC portals)
++which DPAA2 software drivers use to operate on DPAA2 objects.
++
++The diagram below shows an overview of the DPAA2 resource management
++architecture::
++
++	+--------------------------------------+
++	|                  OS                  |
++	|                        DPAA2 drivers |
++	|                             |        |
++	+-----------------------------|--------+
++	                              |
++	                              | (create,discover,connect
++	                              |  config,use,destroy)
++	                              |
++	                 DPAA2        |
++	+------------------------| mc portal |-+
++	|                             |        |
++	|   +- - - - - - - - - - - - -V- - -+  |
++	|   |                               |  |
++	|   |   Management Complex (MC)     |  |
++	|   |                               |  |
++	|   +- - - - - - - - - - - - - - - -+  |
++	|                                      |
++	| Hardware                  Hardware   |
++	| Resources                 Objects    |
++	| ---------                 -------    |
++	| -queues                   -DPRC      |
++	| -buffer pools             -DPMCP     |
++	| -Eth MACs/ports           -DPIO      |
++	| -network interface        -DPNI      |
++	|  profiles                 -DPMAC     |
++	| -queue portals            -DPBP      |
++	| -MC portals                ...       |
++	|  ...                                 |
++	|                                      |
++	+--------------------------------------+
++
++
++The MC mediates operations such as create, discover,
++connect, configuration, and destroy.  Fast-path operations
++on data, such as packet transmit/receive, are not mediated by
++the MC and are done directly using memory mapped regions in
++DPIO objects.
++
++Overview of DPAA2 Objects
++=========================
++
++The section provides a brief overview of some key DPAA2 objects.
++A simple scenario is described illustrating the objects involved
++in creating a network interfaces.
++
++DPRC (Datapath Resource Container)
++----------------------------------
++
++A DPRC is a container object that holds all the other
++types of DPAA2 objects.  In the example diagram below there
++are 8 objects of 5 types (DPMCP, DPIO, DPBP, DPNI, and DPMAC)
++in the container.
++
++::
++
++	+---------------------------------------------------------+
++	| DPRC                                                    |
++	|                                                         |
++	|  +-------+  +-------+  +-------+  +-------+  +-------+  |
++	|  | DPMCP |  | DPIO  |  | DPBP  |  | DPNI  |  | DPMAC |  |
++	|  +-------+  +-------+  +-------+  +---+---+  +---+---+  |
++	|  | DPMCP |  | DPIO  |                                   |
++	|  +-------+  +-------+                                   |
++	|  | DPMCP |                                              |
++	|  +-------+                                              |
++	|                                                         |
++	+---------------------------------------------------------+
++
++From the point of view of an OS, a DPRC behaves similar to a plug and
++play bus, like PCI.  DPRC commands can be used to enumerate the contents
++of the DPRC, discover the hardware objects present (including mappable
++regions and interrupts).
++
++::
++
++	DPRC.1 (bus)
++	   |
++	   +--+--------+-------+-------+-------+
++	      |        |       |       |       |
++	    DPMCP.1  DPIO.1  DPBP.1  DPNI.1  DPMAC.1
++	    DPMCP.2  DPIO.2
++	    DPMCP.3
++
++Hardware objects can be created and destroyed dynamically, providing
++the ability to hot plug/unplug objects in and out of the DPRC.
++
++A DPRC has a mappable MMIO region (an MC portal) that can be used
++to send MC commands.  It has an interrupt for status events (like
++hotplug).
++All objects in a container share the same hardware "isolation context".
++This means that with respect to an IOMMU the isolation granularity
++is at the DPRC (container) level, not at the individual object
++level.
++
++DPRCs can be defined statically and populated with objects
++via a config file passed to the MC when firmware starts it.
++There is also a Linux user space tool called "restool" that can be
++used to create/destroy containers and objects dynamically. The latest
++version of restool can be found at:
++        https://github.com/qoriq-open-source/restool
++
++DPAA2 Objects for an Ethernet Network Interface
++-----------------------------------------------
++
++A typical Ethernet NIC is monolithic-- the NIC device contains TX/RX
++queuing mechanisms, configuration mechanisms, buffer management,
++physical ports, and interrupts.  DPAA2 uses a more granular approach
++utilizing multiple hardware objects.  Each object provides specialized
++functions. Groups of these objects are used by software to provide
++Ethernet network interface functionality.  This approach provides
++efficient use of finite hardware resources, flexibility, and
++performance advantages.
++
++The diagram below shows the objects needed for a simple
++network interface configuration on a system with 2 CPUs.
++
++::
++
++	+---+---+ +---+---+
++	   CPU0     CPU1
++	+---+---+ +---+---+
++	    |         |
++	+---+---+ +---+---+
++	   DPIO     DPIO
++	+---+---+ +---+---+
++	    \     /
++	     \   /
++	      \ /
++	   +---+---+
++	      DPNI  --- DPBP,DPMCP
++	   +---+---+
++	       |
++	       |
++	   +---+---+
++	     DPMAC
++	   +---+---+
++	       |
++	   port/PHY
++
++Below the objects are described.  For each object a brief description
++is provided along with a summary of the kinds of operations the object
++supports and a summary of key resources of the object (MMIO regions
++and IRQs).
++
++DPMAC (Datapath Ethernet MAC)
++~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
++Represents an Ethernet MAC, a hardware device that connects to an Ethernet
++PHY and allows physical transmission and reception of Ethernet frames.
++
++- MMIO regions: none
++- IRQs: DPNI link change
++- commands: set link up/down, link config, get stats,
++  IRQ config, enable, reset
++
++DPNI (Datapath Network Interface)
++Contains TX/RX queues, network interface configuration, and RX buffer pool
++configuration mechanisms.  The TX/RX queues are in memory and are identified
++by queue number.
++
++- MMIO regions: none
++- IRQs: link state
++- commands: port config, offload config, queue config,
++  parse/classify config, IRQ config, enable, reset
++
++DPIO (Datapath I/O)
++~~~~~~~~~~~~~~~~~~~
++Provides interfaces to enqueue and dequeue
++packets and do hardware buffer pool management operations.  The DPAA2
++architecture separates the mechanism to access queues (the DPIO object)
++from the queues themselves.  The DPIO provides an MMIO interface to
++enqueue/dequeue packets.  To enqueue something a descriptor is written
++to the DPIO MMIO region, which includes the target queue number.
++There will typically be one DPIO assigned to each CPU.  This allows all
++CPUs to simultaneously perform enqueue/dequeued operations.  DPIOs are
++expected to be shared by different DPAA2 drivers.
++
++- MMIO regions: queue operations, buffer management
++- IRQs: data availability, congestion notification, buffer
++  pool depletion
++- commands: IRQ config, enable, reset
++
++DPBP (Datapath Buffer Pool)
++~~~~~~~~~~~~~~~~~~~~~~~~~~~
++Represents a hardware buffer pool.
++
++- MMIO regions: none
++- IRQs: none
++- commands: enable, reset
++
++DPMCP (Datapath MC Portal)
++~~~~~~~~~~~~~~~~~~~~~~~~~~
++Provides an MC command portal.
++Used by drivers to send commands to the MC to manage
++objects.
++
++- MMIO regions: MC command portal
++- IRQs: command completion
++- commands: IRQ config, enable, reset
++
++Object Connections
++==================
++Some objects have explicit relationships that must
++be configured:
++
++- DPNI <--> DPMAC
++- DPNI <--> DPNI
++- DPNI <--> L2-switch-port
++
++    A DPNI must be connected to something such as a DPMAC,
++    another DPNI, or L2 switch port.  The DPNI connection
++    is made via a DPRC command.
++
++::
++
++              +-------+  +-------+
++              | DPNI  |  | DPMAC |
++              +---+---+  +---+---+
++                  |          |
++                  +==========+
++
++- DPNI <--> DPBP
++
++    A network interface requires a 'buffer pool' (DPBP
++    object) which provides a list of pointers to memory
++    where received Ethernet data is to be copied.  The
++    Ethernet driver configures the DPBPs associated with
++    the network interface.
++
++Interrupts
++==========
++All interrupts generated by DPAA2 objects are message
++interrupts.  At the hardware level message interrupts
++generated by devices will normally have 3 components--
++1) a non-spoofable 'device-id' expressed on the hardware
++bus, 2) an address, 3) a data value.
++
++In the case of DPAA2 devices/objects, all objects in the
++same container/DPRC share the same 'device-id'.
++For ARM-based SoC this is the same as the stream ID.
++
++
++DPAA2 Linux Drivers Overview
++============================
++
++This section provides an overview of the Linux kernel drivers for
++DPAA2-- 1) the bus driver and associated "DPAA2 infrastructure"
++drivers and 2) functional object drivers (such as Ethernet).
++
++As described previously, a DPRC is a container that holds the other
++types of DPAA2 objects.  It is functionally similar to a plug-and-play
++bus controller.
++Each object in the DPRC is a Linux "device" and is bound to a driver.
++The diagram below shows the Linux drivers involved in a networking
++scenario and the objects bound to each driver.  A brief description
++of each driver follows.
++
++::
++
++	                                     +------------+
++	                                     | OS Network |
++	                                     |   Stack    |
++	         +------------+              +------------+
++	         | Allocator  |. . . . . . . |  Ethernet  |
++	         |(DPMCP,DPBP)|              |   (DPNI)   |
++	         +-.----------+              +---+---+----+
++	          .          .                   ^   |
++	         .            .     <data avail, |   | <enqueue,
++	        .              .     tx confirm> |   | dequeue>
++	+-------------+         .                |   |
++	| DPRC driver |          .           +---+---V----+     +---------+
++	|   (DPRC)    |           . . . . . .| DPIO driver|     |   MAC   |
++	+----------+--+                      |  (DPIO)    |     | (DPMAC) |
++	           |                         +------+-----+     +-----+---+
++	           |<dev add/remove>                |                 |
++	           |                                |                 |
++	  +--------+----------+                     |              +--+---+
++	  |   MC-bus driver   |                     |              | PHY  |
++	  |                   |                     |              |driver|
++	  |   /bus/fsl-mc     |                     |              +--+---+
++	  +-------------------+                     |                 |
++	                                            |                 |
++	========================= HARDWARE =========|=================|======
++	                                          DPIO                |
++	                                            |                 |
++	                                          DPNI---DPBP         |
++	                                            |                 |
++	                                          DPMAC               |
++	                                            |                 |
++	                                           PHY ---------------+
++	============================================|========================
++
++A brief description of each driver is provided below.
++
++MC-bus driver
++-------------
++The MC-bus driver is a platform driver and is probed from a
++node in the device tree (compatible "fsl,qoriq-mc") passed in by boot
++firmware.  It is responsible for bootstrapping the DPAA2 kernel
++infrastructure.
++Key functions include:
++
++- registering a new bus type named "fsl-mc" with the kernel,
++  and implementing bus call-backs (e.g. match/uevent/dev_groups)
++- implementing APIs for DPAA2 driver registration and for device
++  add/remove
++- creates an MSI IRQ domain
++- doing a 'device add' to expose the 'root' DPRC, in turn triggering
++  a bind of the root DPRC to the DPRC driver
++
++The binding for the MC-bus device-tree node can be consulted at
++*Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt*.
++The sysfs bind/unbind interfaces for the MC-bus can be consulted at
++*Documentation/ABI/testing/sysfs-bus-fsl-mc*.
++
++DPRC driver
++-----------
++The DPRC driver is bound to DPRC objects and does runtime management
++of a bus instance.  It performs the initial bus scan of the DPRC
++and handles interrupts for container events such as hot plug by
++re-scanning the DPRC.
++
++Allocator
++---------
++Certain objects such as DPMCP and DPBP are generic and fungible,
++and are intended to be used by other drivers.  For example,
++the DPAA2 Ethernet driver needs:
++
++- DPMCPs to send MC commands, to configure network interfaces
++- DPBPs for network buffer pools
++
++The allocator driver registers for these allocatable object types
++and those objects are bound to the allocator when the bus is probed.
++The allocator maintains a pool of objects that are available for
++allocation by other DPAA2 drivers.
++
++DPIO driver
++-----------
++The DPIO driver is bound to DPIO objects and provides services that allow
++other drivers such as the Ethernet driver to enqueue and dequeue data for
++their respective objects.
++Key services include:
++
++- data availability notifications
++- hardware queuing operations (enqueue and dequeue of data)
++- hardware buffer pool management
++
++To transmit a packet the Ethernet driver puts data on a queue and
++invokes a DPIO API.  For receive, the Ethernet driver registers
++a data availability notification callback.  To dequeue a packet
++a DPIO API is used.
++There is typically one DPIO object per physical CPU for optimum
++performance, allowing different CPUs to simultaneously enqueue
++and dequeue data.
++
++The DPIO driver operates on behalf of all DPAA2 drivers
++active in the kernel--  Ethernet, crypto, compression,
++etc.
++
++Ethernet driver
++---------------
++The Ethernet driver is bound to a DPNI and implements the kernel
++interfaces needed to connect the DPAA2 network interface to
++the network stack.
++Each DPNI corresponds to a Linux network interface.
++
++MAC driver
++----------
++An Ethernet PHY is an off-chip, board specific component and is managed
++by the appropriate PHY driver via an mdio bus.  The MAC driver
++plays a role of being a proxy between the PHY driver and the
++MC.  It does this proxy via the MC commands to a DPMAC object.
++If the PHY driver signals a link change, the MAC driver notifies
++the MC via a DPMAC command.  If a network interface is brought
++up or down, the MC notifies the DPMAC driver via an interrupt and
++the driver can take appropriate action.
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -3980,6 +3980,12 @@ S:	Maintained
+ F:	drivers/char/dtlk.c
+ F:	include/linux/dtlk.h
+ 
++DPAA2 DATAPATH I/O (DPIO) DRIVER
++M:	Roy Pledge <Roy.Pledge@nxp.com>
++L:	linux-kernel@vger.kernel.org
++S:	Maintained
++F:	drivers/staging/fsl-mc/bus/dpio
++
+ DPT_I2O SCSI RAID DRIVER
+ M:	Adaptec OEM Raid Solutions <aacraid@adaptec.com>
+ L:	linux-scsi@vger.kernel.org
+@@ -5110,7 +5116,10 @@ M:	"J. German Rivera" <German.Rivera@fre
+ M:	Stuart Yoder <stuart.yoder@nxp.com>
+ L:	linux-kernel@vger.kernel.org
+ S:	Maintained
+-F:	drivers/staging/fsl-mc/
++F:	drivers/bus/fsl-mc/
++F:	Documentation/networking/dpaa2/overview.rst
++F:	include/uapi/linux/fsl_mc.h
++F:	Documentation/ABI/stable/sysfs-bus-fsl-mc
+ 
+ FREEVXFS FILESYSTEM
+ M:	Christoph Hellwig <hch@infradead.org>
 --- a/drivers/bus/Kconfig
 +++ b/drivers/bus/Kconfig
-@@ -184,4 +184,6 @@ config DA8XX_MSTPRI
- 	  configuration. Allows to adjust the priorities of all master
- 	  peripherals.
- 
+@@ -167,4 +167,7 @@ config VEXPRESS_CONFIG
+ 	help
+ 	  Platform configuration infrastructure for the ARM Ltd.
+ 	  Versatile Express.
++
 +source "drivers/bus/fsl-mc/Kconfig"
 +
  endmenu
 --- a/drivers/bus/Makefile
 +++ b/drivers/bus/Makefile
-@@ -8,6 +8,10 @@ obj-$(CONFIG_ARM_CCI)		+= arm-cci.o
+@@ -7,6 +7,10 @@ obj-$(CONFIG_ARM_CCI)		+= arm-cci.o
  obj-$(CONFIG_ARM_CCN)		+= arm-ccn.o
  
  obj-$(CONFIG_BRCMSTB_GISB_ARB)	+= brcmstb_gisb.o
@@ -134,7 +661,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	  manager user-space tool - restool.
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/Makefile
-@@ -0,0 +1,21 @@
+@@ -0,0 +1,22 @@
 +# SPDX-License-Identifier: GPL-2.0
 +#
 +# Freescale Management Complex (MC) bus drivers
@@ -152,266 +679,11 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		      dprc-driver.o \
 +		      fsl-mc-allocator.o \
 +		      fsl-mc-msi.o \
-+		      dpmcp.o
++		      dpmcp.o \
++		      fsl-mc-iommu.o
 +
 +# MC restool kernel support
 +obj-$(CONFIG_FSL_MC_RESTOOL) += fsl-mc-restool.o
---- a/drivers/staging/fsl-mc/bus/dpbp.c
-+++ /dev/null
-@@ -1,253 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
--/*
-- * Copyright 2013-2016 Freescale Semiconductor Inc.
-- *
-- */
--#include <linux/kernel.h>
--#include "../include/mc.h"
--#include "../include/dpbp.h"
--
--#include "dpbp-cmd.h"
--
--/**
-- * dpbp_open() - Open a control session for the specified object.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @dpbp_id:	DPBP unique ID
-- * @token:	Returned token; use in subsequent API calls
-- *
-- * This function can be used to open a control session for an
-- * already created object; an object may have been declared in
-- * the DPL or by calling the dpbp_create function.
-- * This function returns a unique authentication token,
-- * associated with the specific object ID and the specific MC
-- * portal; this token must be used in all subsequent commands for
-- * this specific object
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpbp_open(struct fsl_mc_io *mc_io,
--	      u32 cmd_flags,
--	      int dpbp_id,
--	      u16 *token)
--{
--	struct mc_command cmd = { 0 };
--	struct dpbp_cmd_open *cmd_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN,
--					  cmd_flags, 0);
--	cmd_params = (struct dpbp_cmd_open *)cmd.params;
--	cmd_params->dpbp_id = cpu_to_le32(dpbp_id);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	*token = mc_cmd_hdr_read_token(&cmd);
--
--	return err;
--}
--EXPORT_SYMBOL(dpbp_open);
--
--/**
-- * dpbp_close() - Close the control session of the object
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPBP object
-- *
-- * After this function is called, no further operations are
-- * allowed on the object without opening a new control session.
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpbp_close(struct fsl_mc_io *mc_io,
--	       u32 cmd_flags,
--	       u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpbp_close);
--
--/**
-- * dpbp_enable() - Enable the DPBP.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPBP object
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpbp_enable(struct fsl_mc_io *mc_io,
--		u32 cmd_flags,
--		u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpbp_enable);
--
--/**
-- * dpbp_disable() - Disable the DPBP.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPBP object
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpbp_disable(struct fsl_mc_io *mc_io,
--		 u32 cmd_flags,
--		 u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE,
--					  cmd_flags, token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpbp_disable);
--
--/**
-- * dpbp_is_enabled() - Check if the DPBP is enabled.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPBP object
-- * @en:		Returns '1' if object is enabled; '0' otherwise
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpbp_is_enabled(struct fsl_mc_io *mc_io,
--		    u32 cmd_flags,
--		    u16 token,
--		    int *en)
--{
--	struct mc_command cmd = { 0 };
--	struct dpbp_rsp_is_enabled *rsp_params;
--	int err;
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPBP_CMDID_IS_ENABLED, cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dpbp_rsp_is_enabled *)cmd.params;
--	*en = rsp_params->enabled & DPBP_ENABLE;
--
--	return 0;
--}
--EXPORT_SYMBOL(dpbp_is_enabled);
--
--/**
-- * dpbp_reset() - Reset the DPBP, returns the object to initial state.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPBP object
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpbp_reset(struct fsl_mc_io *mc_io,
--	       u32 cmd_flags,
--	       u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET,
--					  cmd_flags, token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpbp_reset);
--
--/**
-- * dpbp_get_attributes - Retrieve DPBP attributes.
-- *
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPBP object
-- * @attr:	Returned object's attributes
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpbp_get_attributes(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			struct dpbp_attr *attr)
--{
--	struct mc_command cmd = { 0 };
--	struct dpbp_rsp_get_attributes *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR,
--					  cmd_flags, token);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params;
--	attr->bpid = le16_to_cpu(rsp_params->bpid);
--	attr->id = le32_to_cpu(rsp_params->id);
--
--	return 0;
--}
--EXPORT_SYMBOL(dpbp_get_attributes);
--
--/**
-- * dpbp_get_api_version - Get Data Path Buffer Pool API version
-- * @mc_io:	Pointer to Mc portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @major_ver:	Major version of Buffer Pool API
-- * @minor_ver:	Minor version of Buffer Pool API
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpbp_get_api_version(struct fsl_mc_io *mc_io,
--			 u32 cmd_flags,
--			 u16 *major_ver,
--			 u16 *minor_ver)
--{
--	struct mc_command cmd = { 0 };
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_API_VERSION,
--					  cmd_flags, 0);
--
--	/* send command to mc */
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
--
--	return 0;
--}
--EXPORT_SYMBOL(dpbp_get_api_version);
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/dpbp.c
 @@ -0,0 +1,186 @@
@@ -601,300 +873,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	return 0;
 +}
 +EXPORT_SYMBOL_GPL(dpbp_get_attributes);
---- a/drivers/staging/fsl-mc/bus/dpcon.c
-+++ /dev/null
-@@ -1,291 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
--/*
-- * Copyright 2013-2016 Freescale Semiconductor Inc.
-- *
-- */
--#include <linux/kernel.h>
--#include "../include/mc.h"
--#include "../include/dpcon.h"
--
--#include "dpcon-cmd.h"
--
--/**
-- * dpcon_open() - Open a control session for the specified object
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @dpcon_id:	DPCON unique ID
-- * @token:	Returned token; use in subsequent API calls
-- *
-- * This function can be used to open a control session for an
-- * already created object; an object may have been declared in
-- * the DPL or by calling the dpcon_create() function.
-- * This function returns a unique authentication token,
-- * associated with the specific object ID and the specific MC
-- * portal; this token must be used in all subsequent commands for
-- * this specific object.
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpcon_open(struct fsl_mc_io *mc_io,
--	       u32 cmd_flags,
--	       int dpcon_id,
--	       u16 *token)
--{
--	struct mc_command cmd = { 0 };
--	struct dpcon_cmd_open *dpcon_cmd;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN,
--					  cmd_flags,
--					  0);
--	dpcon_cmd = (struct dpcon_cmd_open *)cmd.params;
--	dpcon_cmd->dpcon_id = cpu_to_le32(dpcon_id);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	*token = mc_cmd_hdr_read_token(&cmd);
--
--	return 0;
--}
--EXPORT_SYMBOL(dpcon_open);
--
--/**
-- * dpcon_close() - Close the control session of the object
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPCON object
-- *
-- * After this function is called, no further operations are
-- * allowed on the object without opening a new control session.
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpcon_close(struct fsl_mc_io *mc_io,
--		u32 cmd_flags,
--		u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE,
--					  cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpcon_close);
--
--/**
-- * dpcon_enable() - Enable the DPCON
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPCON object
-- *
-- * Return:	'0' on Success; Error code otherwise
-- */
--int dpcon_enable(struct fsl_mc_io *mc_io,
--		 u32 cmd_flags,
--		 u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE,
--					  cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpcon_enable);
--
--/**
-- * dpcon_disable() - Disable the DPCON
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPCON object
-- *
-- * Return:	'0' on Success; Error code otherwise
-- */
--int dpcon_disable(struct fsl_mc_io *mc_io,
--		  u32 cmd_flags,
--		  u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE,
--					  cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpcon_disable);
--
--/**
-- * dpcon_is_enabled() -	Check if the DPCON is enabled.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPCON object
-- * @en:		Returns '1' if object is enabled; '0' otherwise
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpcon_is_enabled(struct fsl_mc_io *mc_io,
--		     u32 cmd_flags,
--		     u16 token,
--		     int *en)
--{
--	struct mc_command cmd = { 0 };
--	struct dpcon_rsp_is_enabled *dpcon_rsp;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_IS_ENABLED,
--					  cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	dpcon_rsp = (struct dpcon_rsp_is_enabled *)cmd.params;
--	*en = dpcon_rsp->enabled & DPCON_ENABLE;
--
--	return 0;
--}
--EXPORT_SYMBOL(dpcon_is_enabled);
--
--/**
-- * dpcon_reset() - Reset the DPCON, returns the object to initial state.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPCON object
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpcon_reset(struct fsl_mc_io *mc_io,
--		u32 cmd_flags,
--		u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET,
--					  cmd_flags, token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpcon_reset);
--
--/**
-- * dpcon_get_attributes() - Retrieve DPCON attributes.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPCON object
-- * @attr:	Object's attributes
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dpcon_get_attributes(struct fsl_mc_io *mc_io,
--			 u32 cmd_flags,
--			 u16 token,
--			 struct dpcon_attr *attr)
--{
--	struct mc_command cmd = { 0 };
--	struct dpcon_rsp_get_attr *dpcon_rsp;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR,
--					  cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	dpcon_rsp = (struct dpcon_rsp_get_attr *)cmd.params;
--	attr->id = le32_to_cpu(dpcon_rsp->id);
--	attr->qbman_ch_id = le16_to_cpu(dpcon_rsp->qbman_ch_id);
--	attr->num_priorities = dpcon_rsp->num_priorities;
--
--	return 0;
--}
--EXPORT_SYMBOL(dpcon_get_attributes);
--
--/**
-- * dpcon_set_notification() - Set DPCON notification destination
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPCON object
-- * @cfg:	Notification parameters
-- *
-- * Return:	'0' on Success; Error code otherwise
-- */
--int dpcon_set_notification(struct fsl_mc_io *mc_io,
--			   u32 cmd_flags,
--			   u16 token,
--			   struct dpcon_notification_cfg *cfg)
--{
--	struct mc_command cmd = { 0 };
--	struct dpcon_cmd_set_notification *dpcon_cmd;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION,
--					  cmd_flags,
--					  token);
--	dpcon_cmd = (struct dpcon_cmd_set_notification *)cmd.params;
--	dpcon_cmd->dpio_id = cpu_to_le32(cfg->dpio_id);
--	dpcon_cmd->priority = cfg->priority;
--	dpcon_cmd->user_ctx = cpu_to_le64(cfg->user_ctx);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dpcon_set_notification);
--
--/**
-- * dpcon_get_api_version - Get Data Path Concentrator API version
-- * @mc_io:	Pointer to MC portal's DPCON object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @major_ver:	Major version of DPCON API
-- * @minor_ver:	Minor version of DPCON API
-- *
-- * Return:	'0' on Success; Error code otherwise
-- */
--int dpcon_get_api_version(struct fsl_mc_io *mc_io,
--			  u32 cmd_flags,
--			  u16 *major_ver,
--			  u16 *minor_ver)
--{
--	struct mc_command cmd = { 0 };
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_API_VERSION,
--					  cmd_flags, 0);
--
--	/* send command to mc */
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
--
--	return 0;
--}
--EXPORT_SYMBOL(dpcon_get_api_version);
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/dpcon.c
 @@ -0,0 +1,222 @@
@@ -1224,44 +1202,43 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- a/drivers/staging/fsl-mc/bus/dprc-driver.c
 +++ /dev/null
-@@ -1,813 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0
+@@ -1,805 +0,0 @@
 -/*
 - * Freescale data path resource container (DPRC) driver
 - *
-- * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+- * Copyright (C) 2014 Freescale Semiconductor, Inc.
 - * Author: German Rivera <German.Rivera@freescale.com>
 - *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
 - */
 -
 -#include <linux/module.h>
 -#include <linux/slab.h>
 -#include <linux/interrupt.h>
 -#include <linux/msi.h>
--#include "../include/mc.h"
+-#include "../include/mc-bus.h"
+-#include "../include/mc-sys.h"
 -
 -#include "dprc-cmd.h"
 -#include "fsl-mc-private.h"
 -
 -#define FSL_MC_DPRC_DRIVER_NAME    "fsl_mc_dprc"
 -
--struct fsl_mc_child_objs {
+-#define FSL_MC_DEVICE_MATCH(_mc_dev, _obj_desc) \
+-	(strcmp((_mc_dev)->obj_desc.type, (_obj_desc)->type) == 0 && \
+-	 (_mc_dev)->obj_desc.id == (_obj_desc)->id)
+-
+-struct dprc_child_objs {
 -	int child_count;
--	struct fsl_mc_obj_desc *child_array;
+-	struct dprc_obj_desc *child_array;
 -};
 -
--static bool fsl_mc_device_match(struct fsl_mc_device *mc_dev,
--				struct fsl_mc_obj_desc *obj_desc)
--{
--	return mc_dev->obj_desc.id == obj_desc->id &&
--	       strcmp(mc_dev->obj_desc.type, obj_desc->type) == 0;
--
--}
--
 -static int __fsl_mc_device_remove_if_not_in_mc(struct device *dev, void *data)
 -{
 -	int i;
--	struct fsl_mc_child_objs *objs;
+-	struct dprc_child_objs *objs;
 -	struct fsl_mc_device *mc_dev;
 -
 -	WARN_ON(!dev);
@@ -1270,10 +1247,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	objs = data;
 -
 -	for (i = 0; i < objs->child_count; i++) {
--		struct fsl_mc_obj_desc *obj_desc = &objs->child_array[i];
+-		struct dprc_obj_desc *obj_desc = &objs->child_array[i];
 -
 -		if (strlen(obj_desc->type) != 0 &&
--		    fsl_mc_device_match(mc_dev, obj_desc))
+-		    FSL_MC_DEVICE_MATCH(mc_dev, obj_desc))
 -			break;
 -	}
 -
@@ -1304,7 +1281,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * been dynamically removed in the physical DPRC.
 - */
 -static void dprc_remove_devices(struct fsl_mc_device *mc_bus_dev,
--				struct fsl_mc_obj_desc *obj_desc_array,
+-				struct dprc_obj_desc *obj_desc_array,
 -				int num_child_objects_in_mc)
 -{
 -	if (num_child_objects_in_mc != 0) {
@@ -1312,7 +1289,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		 * Remove child objects that are in the DPRC in Linux,
 -		 * but not in the MC:
 -		 */
--		struct fsl_mc_child_objs objs;
+-		struct dprc_child_objs objs;
 -
 -		objs.child_count = num_child_objects_in_mc;
 -		objs.child_array = obj_desc_array;
@@ -1330,13 +1307,13 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -static int __fsl_mc_device_match(struct device *dev, void *data)
 -{
--	struct fsl_mc_obj_desc *obj_desc = data;
+-	struct dprc_obj_desc *obj_desc = data;
 -	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
 -
--	return fsl_mc_device_match(mc_dev, obj_desc);
+-	return FSL_MC_DEVICE_MATCH(mc_dev, obj_desc);
 -}
 -
--static struct fsl_mc_device *fsl_mc_device_lookup(struct fsl_mc_obj_desc
+-static struct fsl_mc_device *fsl_mc_device_lookup(struct dprc_obj_desc
 -								*obj_desc,
 -						  struct fsl_mc_device
 -								*mc_bus_dev)
@@ -1361,16 +1338,16 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * device is unbound from the corresponding device driver.
 - */
 -static void check_plugged_state_change(struct fsl_mc_device *mc_dev,
--				       struct fsl_mc_obj_desc *obj_desc)
+-				       struct dprc_obj_desc *obj_desc)
 -{
 -	int error;
 -	u32 plugged_flag_at_mc =
--			obj_desc->state & FSL_MC_OBJ_STATE_PLUGGED;
+-			obj_desc->state & DPRC_OBJ_STATE_PLUGGED;
 -
 -	if (plugged_flag_at_mc !=
--	    (mc_dev->obj_desc.state & FSL_MC_OBJ_STATE_PLUGGED)) {
+-	    (mc_dev->obj_desc.state & DPRC_OBJ_STATE_PLUGGED)) {
 -		if (plugged_flag_at_mc) {
--			mc_dev->obj_desc.state |= FSL_MC_OBJ_STATE_PLUGGED;
+-			mc_dev->obj_desc.state |= DPRC_OBJ_STATE_PLUGGED;
 -			error = device_attach(&mc_dev->dev);
 -			if (error < 0) {
 -				dev_err(&mc_dev->dev,
@@ -1378,7 +1355,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -					error);
 -			}
 -		} else {
--			mc_dev->obj_desc.state &= ~FSL_MC_OBJ_STATE_PLUGGED;
+-			mc_dev->obj_desc.state &= ~DPRC_OBJ_STATE_PLUGGED;
 -			device_release_driver(&mc_dev->dev);
 -		}
 -	}
@@ -1397,7 +1374,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * in the physical DPRC.
 - */
 -static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev,
--				 struct fsl_mc_obj_desc *obj_desc_array,
+-				 struct dprc_obj_desc *obj_desc_array,
 -				 int num_child_objects_in_mc)
 -{
 -	int error;
@@ -1405,7 +1382,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -	for (i = 0; i < num_child_objects_in_mc; i++) {
 -		struct fsl_mc_device *child_dev;
--		struct fsl_mc_obj_desc *obj_desc = &obj_desc_array[i];
+-		struct dprc_obj_desc *obj_desc = &obj_desc_array[i];
 -
 -		if (strlen(obj_desc->type) == 0)
 -			continue;
@@ -1416,7 +1393,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		child_dev = fsl_mc_device_lookup(obj_desc, mc_bus_dev);
 -		if (child_dev) {
 -			check_plugged_state_change(child_dev, obj_desc);
--			put_device(&child_dev->dev);
 -			continue;
 -		}
 -
@@ -1445,14 +1421,14 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * populated before they can get allocation requests from probe callbacks
 - * of the device drivers for the non-allocatable devices.
 - */
--static int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
--			     unsigned int *total_irq_count)
+-int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
+-		      unsigned int *total_irq_count)
 -{
 -	int num_child_objects;
 -	int dprc_get_obj_failures;
 -	int error;
 -	unsigned int irq_count = mc_bus_dev->obj_desc.irq_count;
--	struct fsl_mc_obj_desc *child_obj_desc_array = NULL;
+-	struct dprc_obj_desc *child_obj_desc_array = NULL;
 -
 -	error = dprc_get_obj_count(mc_bus_dev->mc_io,
 -				   0,
@@ -1479,7 +1455,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		 */
 -		dprc_get_obj_failures = 0;
 -		for (i = 0; i < num_child_objects; i++) {
--			struct fsl_mc_obj_desc *obj_desc =
+-			struct dprc_obj_desc *obj_desc =
 -			    &child_obj_desc_array[i];
 -
 -			error = dprc_get_obj(mc_bus_dev->mc_io,
@@ -1507,7 +1483,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -			if ((strcmp(obj_desc->type, "dpseci") == 0) &&
 -			    (obj_desc->ver_major < 4))
 -				obj_desc->flags |=
--					FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY;
+-					DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY;
 -
 -			irq_count += obj_desc->irq_count;
 -			dev_dbg(&mc_bus_dev->dev,
@@ -1534,6 +1510,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -	return 0;
 -}
+-EXPORT_SYMBOL_GPL(dprc_scan_objects);
 -
 -/**
 - * dprc_scan_container - Scans a physical DPRC and synchronizes Linux bus state
@@ -1544,7 +1521,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * bus driver with the actual state of the MC by adding and removing
 - * devices as appropriate.
 - */
--static int dprc_scan_container(struct fsl_mc_device *mc_bus_dev)
+-int dprc_scan_container(struct fsl_mc_device *mc_bus_dev)
 -{
 -	int error;
 -	unsigned int irq_count;
@@ -1580,6 +1557,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	fsl_mc_cleanup_all_resource_pools(mc_bus_dev);
 -	return error;
 -}
+-EXPORT_SYMBOL_GPL(dprc_scan_container);
 -
 -/**
 - * dprc_irq0_handler - Regular ISR for DPRC interrupt 0
@@ -1732,7 +1710,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -					  dprc_irq0_handler,
 -					  dprc_irq0_handler_thread,
 -					  IRQF_NO_SUSPEND | IRQF_ONESHOT,
--					  dev_name(&mc_dev->dev),
+-					  "FSL MC DPRC irq0",
 -					  &mc_dev->dev);
 -	if (error < 0) {
 -		dev_err(&mc_dev->dev,
@@ -1824,7 +1802,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev);
 -	bool mc_io_created = false;
 -	bool msi_domain_set = false;
--	u16 major_ver, minor_ver;
 -
 -	if (WARN_ON(strcmp(mc_dev->obj_desc.type, "dprc") != 0))
 -		return -EINVAL;
@@ -1842,7 +1819,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		if (WARN_ON(mc_dev->obj_desc.region_count == 0))
 -			return -EINVAL;
 -
--		region_size = resource_size(mc_dev->regions);
+-		region_size = mc_dev->regions[0].end -
+-			      mc_dev->regions[0].start + 1;
 -
 -		error = fsl_create_mc_io(&mc_dev->dev,
 -					 mc_dev->regions[0].start,
@@ -1896,21 +1874,13 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		goto error_cleanup_open;
 -	}
 -
--	error = dprc_get_api_version(mc_dev->mc_io, 0,
--				     &major_ver,
--				     &minor_ver);
--	if (error < 0) {
--		dev_err(&mc_dev->dev, "dprc_get_api_version() failed: %d\n",
--			error);
--		goto error_cleanup_open;
--	}
--
--	if (major_ver < DPRC_MIN_VER_MAJOR ||
--	    (major_ver == DPRC_MIN_VER_MAJOR &&
--	     minor_ver < DPRC_MIN_VER_MINOR)) {
+-	if (mc_bus->dprc_attr.version.major < DPRC_MIN_VER_MAJOR ||
+-	   (mc_bus->dprc_attr.version.major == DPRC_MIN_VER_MAJOR &&
+-	    mc_bus->dprc_attr.version.minor < DPRC_MIN_VER_MINOR)) {
 -		dev_err(&mc_dev->dev,
 -			"ERROR: DPRC version %d.%d not supported\n",
--			major_ver, minor_ver);
+-			mc_bus->dprc_attr.version.major,
+-			mc_bus->dprc_attr.version.minor);
 -		error = -ENOTSUPP;
 -		goto error_cleanup_open;
 -	}
@@ -2856,766 +2826,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +{
 +	fsl_mc_driver_unregister(&dprc_driver);
 +}
---- a/drivers/staging/fsl-mc/bus/dprc.c
-+++ /dev/null
-@@ -1,757 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
--/*
-- * Copyright 2013-2016 Freescale Semiconductor Inc.
-- *
-- */
--#include <linux/kernel.h>
--#include "../include/mc.h"
--#include "dprc.h"
--
--#include "dprc-cmd.h"
--
--/**
-- * dprc_open() - Open DPRC object for use
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @container_id: Container ID to open
-- * @token:	Returned token of DPRC object
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- *
-- * @warning	Required before any operation on the object.
-- */
--int dprc_open(struct fsl_mc_io *mc_io,
--	      u32 cmd_flags,
--	      int container_id,
--	      u16 *token)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_open *cmd_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags,
--					  0);
--	cmd_params = (struct dprc_cmd_open *)cmd.params;
--	cmd_params->container_id = cpu_to_le32(container_id);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	*token = mc_cmd_hdr_read_token(&cmd);
--
--	return 0;
--}
--EXPORT_SYMBOL(dprc_open);
--
--/**
-- * dprc_close() - Close the control session of the object
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- *
-- * After this function is called, no further operations are
-- * allowed on the object without opening a new control session.
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_close(struct fsl_mc_io *mc_io,
--	       u32 cmd_flags,
--	       u16 token)
--{
--	struct mc_command cmd = { 0 };
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dprc_close);
--
--/**
-- * dprc_get_irq() - Get IRQ information from the DPRC.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @irq_index:	The interrupt index to configure
-- * @type:	Interrupt type: 0 represents message interrupt
-- *		type (both irq_addr and irq_val are valid)
-- * @irq_cfg:	IRQ attributes
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_irq(struct fsl_mc_io *mc_io,
--		 u32 cmd_flags,
--		 u16 token,
--		 u8 irq_index,
--		 int *type,
--		 struct dprc_irq_cfg *irq_cfg)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_get_irq *cmd_params;
--	struct dprc_rsp_get_irq *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ,
--					  cmd_flags,
--					  token);
--	cmd_params = (struct dprc_cmd_get_irq *)cmd.params;
--	cmd_params->irq_index = irq_index;
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_irq *)cmd.params;
--	irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
--	irq_cfg->paddr = le64_to_cpu(rsp_params->irq_addr);
--	irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
--	*type = le32_to_cpu(rsp_params->type);
--
--	return 0;
--}
--
--/**
-- * dprc_set_irq() - Set IRQ information for the DPRC to trigger an interrupt.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @irq_index:	Identifies the interrupt index to configure
-- * @irq_cfg:	IRQ configuration
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_set_irq(struct fsl_mc_io *mc_io,
--		 u32 cmd_flags,
--		 u16 token,
--		 u8 irq_index,
--		 struct dprc_irq_cfg *irq_cfg)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_set_irq *cmd_params;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ,
--					  cmd_flags,
--					  token);
--	cmd_params = (struct dprc_cmd_set_irq *)cmd.params;
--	cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
--	cmd_params->irq_index = irq_index;
--	cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
--	cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--
--/**
-- * dprc_get_irq_enable() - Get overall interrupt state.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @irq_index:  The interrupt index to configure
-- * @en:		Returned interrupt state - enable = 1, disable = 0
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			u8 irq_index,
--			u8 *en)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_get_irq_enable *cmd_params;
--	struct dprc_rsp_get_irq_enable *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_ENABLE,
--					  cmd_flags, token);
--	cmd_params = (struct dprc_cmd_get_irq_enable *)cmd.params;
--	cmd_params->irq_index = irq_index;
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_irq_enable *)cmd.params;
--	*en = rsp_params->enabled & DPRC_ENABLE;
--
--	return 0;
--}
--
--/**
-- * dprc_set_irq_enable() - Set overall interrupt state.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @irq_index:	The interrupt index to configure
-- * @en:		Interrupt state - enable = 1, disable = 0
-- *
-- * Allows GPP software to control when interrupts are generated.
-- * Each interrupt can have up to 32 causes.  The enable/disable control's the
-- * overall interrupt state. if the interrupt is disabled no causes will cause
-- * an interrupt.
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			u8 irq_index,
--			u8 en)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_set_irq_enable *cmd_params;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_ENABLE,
--					  cmd_flags, token);
--	cmd_params = (struct dprc_cmd_set_irq_enable *)cmd.params;
--	cmd_params->enable = en & DPRC_ENABLE;
--	cmd_params->irq_index = irq_index;
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--
--/**
-- * dprc_get_irq_mask() - Get interrupt mask.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @irq_index:	The interrupt index to configure
-- * @mask:	Returned event mask to trigger interrupt
-- *
-- * Every interrupt can have up to 32 causes and the interrupt model supports
-- * masking/unmasking each cause independently
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
--		      u32 cmd_flags,
--		      u16 token,
--		      u8 irq_index,
--		      u32 *mask)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_get_irq_mask *cmd_params;
--	struct dprc_rsp_get_irq_mask *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_MASK,
--					  cmd_flags, token);
--	cmd_params = (struct dprc_cmd_get_irq_mask *)cmd.params;
--	cmd_params->irq_index = irq_index;
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_irq_mask *)cmd.params;
--	*mask = le32_to_cpu(rsp_params->mask);
--
--	return 0;
--}
--
--/**
-- * dprc_set_irq_mask() - Set interrupt mask.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @irq_index:	The interrupt index to configure
-- * @mask:	event mask to trigger interrupt;
-- *			each bit:
-- *				0 = ignore event
-- *				1 = consider event for asserting irq
-- *
-- * Every interrupt can have up to 32 causes and the interrupt model supports
-- * masking/unmasking each cause independently
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
--		      u32 cmd_flags,
--		      u16 token,
--		      u8 irq_index,
--		      u32 mask)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_set_irq_mask *cmd_params;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_MASK,
--					  cmd_flags, token);
--	cmd_params = (struct dprc_cmd_set_irq_mask *)cmd.params;
--	cmd_params->mask = cpu_to_le32(mask);
--	cmd_params->irq_index = irq_index;
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--
--/**
-- * dprc_get_irq_status() - Get the current status of any pending interrupts.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @irq_index:	The interrupt index to configure
-- * @status:	Returned interrupts status - one bit per cause:
-- *			0 = no interrupt pending
-- *			1 = interrupt pending
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_irq_status(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			u8 irq_index,
--			u32 *status)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_get_irq_status *cmd_params;
--	struct dprc_rsp_get_irq_status *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_STATUS,
--					  cmd_flags, token);
--	cmd_params = (struct dprc_cmd_get_irq_status *)cmd.params;
--	cmd_params->status = cpu_to_le32(*status);
--	cmd_params->irq_index = irq_index;
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_irq_status *)cmd.params;
--	*status = le32_to_cpu(rsp_params->status);
--
--	return 0;
--}
--
--/**
-- * dprc_clear_irq_status() - Clear a pending interrupt's status
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @irq_index:	The interrupt index to configure
-- * @status:	bits to clear (W1C) - one bit per cause:
-- *					0 = don't change
-- *					1 = clear status bit
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
--			  u32 cmd_flags,
--			  u16 token,
--			  u8 irq_index,
--			  u32 status)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_clear_irq_status *cmd_params;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLEAR_IRQ_STATUS,
--					  cmd_flags, token);
--	cmd_params = (struct dprc_cmd_clear_irq_status *)cmd.params;
--	cmd_params->status = cpu_to_le32(status);
--	cmd_params->irq_index = irq_index;
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--
--/**
-- * dprc_get_attributes() - Obtains container attributes
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @attributes	Returned container attributes
-- *
-- * Return:     '0' on Success; Error code otherwise.
-- */
--int dprc_get_attributes(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			struct dprc_attributes *attr)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_rsp_get_attributes *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR,
--					  cmd_flags,
--					  token);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_attributes *)cmd.params;
--	attr->container_id = le32_to_cpu(rsp_params->container_id);
--	attr->icid = le16_to_cpu(rsp_params->icid);
--	attr->options = le32_to_cpu(rsp_params->options);
--	attr->portal_id = le32_to_cpu(rsp_params->portal_id);
--
--	return 0;
--}
--
--/**
-- * dprc_get_obj_count() - Obtains the number of objects in the DPRC
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @obj_count:	Number of objects assigned to the DPRC
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_obj_count(struct fsl_mc_io *mc_io,
--		       u32 cmd_flags,
--		       u16 token,
--		       int *obj_count)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_rsp_get_obj_count *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT,
--					  cmd_flags, token);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_obj_count *)cmd.params;
--	*obj_count = le32_to_cpu(rsp_params->obj_count);
--
--	return 0;
--}
--EXPORT_SYMBOL(dprc_get_obj_count);
--
--/**
-- * dprc_get_obj() - Get general information on an object
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @obj_index:	Index of the object to be queried (< obj_count)
-- * @obj_desc:	Returns the requested object descriptor
-- *
-- * The object descriptors are retrieved one by one by incrementing
-- * obj_index up to (not including) the value of obj_count returned
-- * from dprc_get_obj_count(). dprc_get_obj_count() must
-- * be called prior to dprc_get_obj().
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_obj(struct fsl_mc_io *mc_io,
--		 u32 cmd_flags,
--		 u16 token,
--		 int obj_index,
--		 struct fsl_mc_obj_desc *obj_desc)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_get_obj *cmd_params;
--	struct dprc_rsp_get_obj *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ,
--					  cmd_flags,
--					  token);
--	cmd_params = (struct dprc_cmd_get_obj *)cmd.params;
--	cmd_params->obj_index = cpu_to_le32(obj_index);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_obj *)cmd.params;
--	obj_desc->id = le32_to_cpu(rsp_params->id);
--	obj_desc->vendor = le16_to_cpu(rsp_params->vendor);
--	obj_desc->irq_count = rsp_params->irq_count;
--	obj_desc->region_count = rsp_params->region_count;
--	obj_desc->state = le32_to_cpu(rsp_params->state);
--	obj_desc->ver_major = le16_to_cpu(rsp_params->version_major);
--	obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor);
--	obj_desc->flags = le16_to_cpu(rsp_params->flags);
--	strncpy(obj_desc->type, rsp_params->type, 16);
--	obj_desc->type[15] = '\0';
--	strncpy(obj_desc->label, rsp_params->label, 16);
--	obj_desc->label[15] = '\0';
--	return 0;
--}
--EXPORT_SYMBOL(dprc_get_obj);
--
--/**
-- * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @obj_type:	Type of the object to set its IRQ
-- * @obj_id:	ID of the object to set its IRQ
-- * @irq_index:	The interrupt index to configure
-- * @irq_cfg:	IRQ configuration
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
--		     u32 cmd_flags,
--		     u16 token,
--		     char *obj_type,
--		     int obj_id,
--		     u8 irq_index,
--		     struct dprc_irq_cfg *irq_cfg)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_set_obj_irq *cmd_params;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_IRQ,
--					  cmd_flags,
--					  token);
--	cmd_params = (struct dprc_cmd_set_obj_irq *)cmd.params;
--	cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
--	cmd_params->irq_index = irq_index;
--	cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
--	cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
--	cmd_params->obj_id = cpu_to_le32(obj_id);
--	strncpy(cmd_params->obj_type, obj_type, 16);
--	cmd_params->obj_type[15] = '\0';
--
--	/* send command to mc*/
--	return mc_send_command(mc_io, &cmd);
--}
--EXPORT_SYMBOL(dprc_set_obj_irq);
--
--/**
-- * dprc_get_obj_irq() - Get IRQ information from object.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @obj_type:	Type od the object to get its IRQ
-- * @obj_id:	ID of the object to get its IRQ
-- * @irq_index:	The interrupt index to configure
-- * @type:	Interrupt type: 0 represents message interrupt
-- *		type (both irq_addr and irq_val are valid)
-- * @irq_cfg:	The returned IRQ attributes
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
--		     u32 cmd_flags,
--		     u16 token,
--		     char *obj_type,
--		     int obj_id,
--		     u8 irq_index,
--		     int *type,
--		     struct dprc_irq_cfg *irq_cfg)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_get_obj_irq *cmd_params;
--	struct dprc_rsp_get_obj_irq *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_IRQ,
--					  cmd_flags,
--					  token);
--	cmd_params = (struct dprc_cmd_get_obj_irq *)cmd.params;
--	cmd_params->obj_id = cpu_to_le32(obj_id);
--	cmd_params->irq_index = irq_index;
--	strncpy(cmd_params->obj_type, obj_type, 16);
--	cmd_params->obj_type[15] = '\0';
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_obj_irq *)cmd.params;
--	irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
--	irq_cfg->paddr = le64_to_cpu(rsp_params->irq_addr);
--	irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
--	*type = le32_to_cpu(rsp_params->type);
--
--	return 0;
--}
--EXPORT_SYMBOL(dprc_get_obj_irq);
--
--/**
-- * dprc_get_res_count() - Obtains the number of free resources that are assigned
-- *		to this container, by pool type
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @type:	pool type
-- * @res_count:	Returned number of free resources of the given
-- *			resource type that are assigned to this DPRC
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_res_count(struct fsl_mc_io *mc_io,
--		       u32 cmd_flags,
--		       u16 token,
--		       char *type,
--		       int *res_count)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_get_res_count *cmd_params;
--	struct dprc_rsp_get_res_count *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_COUNT,
--					  cmd_flags, token);
--	cmd_params = (struct dprc_cmd_get_res_count *)cmd.params;
--	strncpy(cmd_params->type, type, 16);
--	cmd_params->type[15] = '\0';
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_res_count *)cmd.params;
--	*res_count = le32_to_cpu(rsp_params->res_count);
--
--	return 0;
--}
--EXPORT_SYMBOL(dprc_get_res_count);
--
--/**
-- * dprc_get_obj_region() - Get region information for a specified object.
-- * @mc_io:	Pointer to MC portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @token:	Token of DPRC object
-- * @obj_type;	Object type as returned in dprc_get_obj()
-- * @obj_id:	Unique object instance as returned in dprc_get_obj()
-- * @region_index: The specific region to query
-- * @region_desc:  Returns the requested region descriptor
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_obj_region(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			char *obj_type,
--			int obj_id,
--			u8 region_index,
--			struct dprc_region_desc *region_desc)
--{
--	struct mc_command cmd = { 0 };
--	struct dprc_cmd_get_obj_region *cmd_params;
--	struct dprc_rsp_get_obj_region *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG,
--					  cmd_flags, token);
--	cmd_params = (struct dprc_cmd_get_obj_region *)cmd.params;
--	cmd_params->obj_id = cpu_to_le32(obj_id);
--	cmd_params->region_index = region_index;
--	strncpy(cmd_params->obj_type, obj_type, 16);
--	cmd_params->obj_type[15] = '\0';
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params;
--	region_desc->base_offset = le64_to_cpu(rsp_params->base_addr);
--	region_desc->size = le32_to_cpu(rsp_params->size);
--
--	return 0;
--}
--EXPORT_SYMBOL(dprc_get_obj_region);
--
--/**
-- * dprc_get_api_version - Get Data Path Resource Container API version
-- * @mc_io:	Pointer to Mc portal's I/O object
-- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
-- * @major_ver:	Major version of Data Path Resource Container API
-- * @minor_ver:	Minor version of Data Path Resource Container API
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_api_version(struct fsl_mc_io *mc_io,
--			 u32 cmd_flags,
--			 u16 *major_ver,
--			 u16 *minor_ver)
--{
--	struct mc_command cmd = { 0 };
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION,
--					  cmd_flags, 0);
--
--	/* send command to mc */
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
--
--	return 0;
--}
--
--/**
-- * dprc_get_container_id - Get container ID associated with a given portal.
-- * @mc_io:		Pointer to Mc portal's I/O object
-- * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
-- * @container_id:	Requested container id
-- *
-- * Return:	'0' on Success; Error code otherwise.
-- */
--int dprc_get_container_id(struct fsl_mc_io *mc_io,
--			  u32 cmd_flags,
--			  int *container_id)
--{
--	struct mc_command cmd = { 0 };
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID,
--					  cmd_flags,
--					  0);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	*container_id = (int)mc_cmd_read_object_id(&cmd);
--
--	return 0;
--}
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/dprc.c
 @@ -0,0 +1,575 @@
@@ -4196,35 +3406,41 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
 +++ /dev/null
-@@ -1,663 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0
+@@ -1,668 +0,0 @@
 -/*
-- * fsl-mc object allocator driver
+- * Freescale MC object device allocator driver
 - *
-- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+- * Copyright (C) 2013 Freescale Semiconductor, Inc.
 - *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
 - */
 -
 -#include <linux/module.h>
 -#include <linux/msi.h>
--#include "../include/mc.h"
+-#include "../include/mc-bus.h"
+-#include "../include/mc-sys.h"
+-#include "../include/dpbp-cmd.h"
+-#include "../include/dpcon-cmd.h"
 -
 -#include "fsl-mc-private.h"
 -
--static bool __must_check fsl_mc_is_allocatable(const char *obj_type)
--{
--	return strcmp(obj_type, "dpbp") == 0 ||
--	       strcmp(obj_type, "dpmcp") == 0 ||
--	       strcmp(obj_type, "dpcon") == 0;
--}
+-#define FSL_MC_IS_ALLOCATABLE(_obj_type) \
+-	(strcmp(_obj_type, "dpbp") == 0 || \
+-	 strcmp(_obj_type, "dpmcp") == 0 || \
+-	 strcmp(_obj_type, "dpcon") == 0)
 -
 -/**
-- * fsl_mc_resource_pool_add_device - add allocatable object to a resource
-- * pool of a given fsl-mc bus
+- * fsl_mc_resource_pool_add_device - add allocatable device to a resource
+- * pool of a given MC bus
 - *
-- * @mc_bus: pointer to the fsl-mc bus
-- * @pool_type: pool type
-- * @mc_dev: pointer to allocatable fsl-mc device
+- * @mc_bus: pointer to the MC bus
+- * @pool_type: MC bus pool type
+- * @mc_dev: Pointer to allocatable MC object device
+- *
+- * It adds an allocatable MC object device to a container's resource pool of
+- * the given resource type
 - */
 -static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus
 -								*mc_bus,
@@ -4240,7 +3456,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -	if (WARN_ON(pool_type < 0 || pool_type >= FSL_MC_NUM_POOL_TYPES))
 -		goto out;
--	if (WARN_ON(!fsl_mc_is_allocatable(mc_dev->obj_desc.type)))
+-	if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type)))
 -		goto out;
 -	if (WARN_ON(mc_dev->resource))
 -		goto out;
@@ -4288,10 +3504,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * fsl_mc_resource_pool_remove_device - remove an allocatable device from a
 - * resource pool
 - *
-- * @mc_dev: pointer to allocatable fsl-mc device
+- * @mc_dev: Pointer to allocatable MC object device
 - *
-- * It permanently removes an allocatable fsl-mc device from the resource
-- * pool. It's an error if the device is in use.
+- * It permanently removes an allocatable MC object device from the resource
+- * pool, the device is currently in, as long as it is in the pool's free list.
 - */
 -static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device
 -								   *mc_dev)
@@ -4302,7 +3518,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	struct fsl_mc_resource *resource;
 -	int error = -EINVAL;
 -
--	if (WARN_ON(!fsl_mc_is_allocatable(mc_dev->obj_desc.type)))
+-	if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type)))
 -		goto out;
 -
 -	resource = mc_dev->resource;
@@ -4448,18 +3664,17 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -EXPORT_SYMBOL_GPL(fsl_mc_resource_free);
 -
 -/**
-- * fsl_mc_object_allocate - Allocates an fsl-mc object of the given
-- * pool type from a given fsl-mc bus instance
+- * fsl_mc_object_allocate - Allocates a MC object device of the given
+- * pool type from a given MC bus
 - *
-- * @mc_dev: fsl-mc device which is used in conjunction with the
-- * allocated object
-- * @pool_type: pool type
-- * @new_mc_dev: pointer to area where the pointer to the allocated device
-- * is to be returned
+- * @mc_dev: MC device for which the MC object device is to be allocated
+- * @pool_type: MC bus resource pool type
+- * @new_mc_dev: Pointer to area where the pointer to the allocated
+- * MC object device is to be returned
 - *
-- * Allocatable objects are always used in conjunction with some functional
-- * device.  This function allocates an object of the specified type from
-- * the DPRC containing the functional device.
+- * This function allocates a MC object device from the device's parent DPRC,
+- * from the corresponding MC bus' pool of allocatable MC object devices of
+- * the given resource type. mc_dev cannot be a DPRC itself.
 - *
 - * NOTE: pool_type must be different from FSL_MC_POOL_MCP, since MC
 - * portals are allocated using fsl_mc_portal_allocate(), instead of
@@ -4506,9 +3721,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -EXPORT_SYMBOL_GPL(fsl_mc_object_allocate);
 -
 -/**
-- * fsl_mc_object_free - Returns an fsl-mc object to the resource
-- * pool where it came from.
-- * @mc_adev: Pointer to the fsl-mc device
+- * fsl_mc_object_free - Returns an allocatable MC object device to the
+- * corresponding resource pool of a given MC bus.
+- *
+- * @mc_adev: Pointer to the MC object device
 - */
 -void fsl_mc_object_free(struct fsl_mc_device *mc_adev)
 -{
@@ -4525,14 +3741,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -EXPORT_SYMBOL_GPL(fsl_mc_object_free);
 -
 -/*
-- * A DPRC and the devices in the DPRC all share the same GIC-ITS device
-- * ID.  A block of IRQs is pre-allocated and maintained in a pool
-- * from which devices can allocate them when needed.
-- */
--
--/*
-- * Initialize the interrupt pool associated with an fsl-mc bus.
-- * It allocates a block of IRQs from the GIC-ITS.
+- * Initialize the interrupt pool associated with a MC bus.
+- * It allocates a block of IRQs from the GIC-ITS
 - */
 -int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus,
 -			     unsigned int irq_count)
@@ -4594,7 +3804,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool);
 -
 -/**
-- * Teardown the interrupt pool associated with an fsl-mc bus.
+- * Teardown the interrupt pool associated with an MC bus.
 - * It frees the IRQs that were allocated to the pool, back to the GIC-ITS.
 - */
 -void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus)
@@ -4621,7 +3831,11 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool);
 -
 -/**
-- * Allocate the IRQs required by a given fsl-mc device.
+- * It allocates the IRQs required by a given MC object device. The
+- * IRQs are allocated from the interrupt pool associated with the
+- * MC bus that contains the device, if the device is not a DPRC device.
+- * Otherwise, the IRQs are allocated from the interrupt pool associated
+- * with the MC bus that represents the DPRC device itself.
 - */
 -int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev)
 -{
@@ -4690,7 +3904,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -EXPORT_SYMBOL_GPL(fsl_mc_allocate_irqs);
 -
 -/*
-- * Frees the IRQs that were allocated for an fsl-mc device.
+- * It frees the IRQs that were allocated for a MC object device, by
+- * returning them to the corresponding interrupt pool.
 - */
 -void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev)
 -{
@@ -4782,7 +3997,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	struct fsl_mc_bus *mc_bus;
 -	int error;
 -
--	if (WARN_ON(!fsl_mc_is_allocatable(mc_dev->obj_desc.type)))
+-	if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type)))
 -		return -EINVAL;
 -
 -	mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent);
@@ -4799,7 +4014,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		return error;
 -
 -	dev_dbg(&mc_dev->dev,
--		"Allocatable fsl-mc device bound to fsl_mc_allocator driver");
+-		"Allocatable MC object device bound to fsl_mc_allocator driver");
 -	return 0;
 -}
 -
@@ -4811,7 +4026,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -{
 -	int error;
 -
--	if (WARN_ON(!fsl_mc_is_allocatable(mc_dev->obj_desc.type)))
+-	if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type)))
 -		return -EINVAL;
 -
 -	if (mc_dev->resource) {
@@ -4821,7 +4036,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	}
 -
 -	dev_dbg(&mc_dev->dev,
--		"Allocatable fsl-mc device unbound from fsl_mc_allocator driver");
+-		"Allocatable MC object device unbound from fsl_mc_allocator driver");
 -	return 0;
 -}
 -
@@ -5520,18 +4735,18 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
 +++ /dev/null
-@@ -1,900 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0
+@@ -1,920 +0,0 @@
 -/*
 - * Freescale Management Complex (MC) bus driver
 - *
-- * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+- * Copyright (C) 2014 Freescale Semiconductor, Inc.
 - * Author: German Rivera <German.Rivera@freescale.com>
 - *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
 - */
 -
--#define pr_fmt(fmt) "fsl-mc: " fmt
--
 -#include <linux/module.h>
 -#include <linux/of_device.h>
 -#include <linux/of_address.h>
@@ -5541,10 +4756,14 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -#include <linux/bitops.h>
 -#include <linux/msi.h>
 -#include <linux/dma-mapping.h>
+-#include "../include/mc-bus.h"
+-#include "../include/dpmng.h"
+-#include "../include/mc-sys.h"
 -
 -#include "fsl-mc-private.h"
 -#include "dprc-cmd.h"
--#include "dpmng-cmd.h"
+-
+-static struct kmem_cache *mc_dev_cache;
 -
 -/**
 - * Default DMA mask for devices on a fsl-mc bus
@@ -5553,7 +4772,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -/**
 - * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
-- * @root_mc_bus_dev: fsl-mc device representing the root DPRC
+- * @root_mc_bus_dev: MC object device representing the root DPRC
 - * @num_translation_ranges: number of entries in addr_translation_ranges
 - * @translation_ranges: array of bus to system address translation ranges
 - */
@@ -5580,23 +4799,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -};
 -
 -/**
-- * struct mc_version
-- * @major: Major version number: incremented on API compatibility changes
-- * @minor: Minor version number: incremented on API additions (that are
-- *		backward compatible); reset when major version is incremented
-- * @revision: Internal revision number: incremented on implementation changes
-- *		and/or bug fixes that have no impact on API
-- */
--struct mc_version {
--	u32 major;
--	u32 minor;
--	u32 revision;
--};
--
--/**
 - * fsl_mc_bus_match - device to driver matching callback
-- * @dev: the fsl-mc device to match against
-- * @drv: the device driver to search for matching fsl-mc object type
+- * @dev: the MC object device structure to match against
+- * @drv: the device driver to search for matching MC object device id
 - * structures
 - *
 - * Returns 1 on success, 0 otherwise.
@@ -5608,6 +4813,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv);
 -	bool found = false;
 -
+-	if (WARN_ON(!fsl_mc_bus_exists()))
+-		goto out;
+-
 -	if (!mc_drv->match_id_table)
 -		goto out;
 -
@@ -5615,13 +4823,13 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	 * If the object is not 'plugged' don't match.
 -	 * Only exception is the root DPRC, which is a special case.
 -	 */
--	if ((mc_dev->obj_desc.state & FSL_MC_OBJ_STATE_PLUGGED) == 0 &&
+-	if ((mc_dev->obj_desc.state & DPRC_OBJ_STATE_PLUGGED) == 0 &&
 -	    !fsl_mc_is_root_dprc(&mc_dev->dev))
 -		goto out;
 -
 -	/*
 -	 * Traverse the match_id table of the given driver, trying to find
--	 * a matching for the given device.
+-	 * a matching for the given MC object device.
 -	 */
 -	for (id = mc_drv->match_id_table; id->vendor != 0x0; id++) {
 -		if (id->vendor == mc_dev->obj_desc.vendor &&
@@ -5677,6 +4885,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -};
 -EXPORT_SYMBOL_GPL(fsl_mc_bus_type);
 -
+-static atomic_t root_dprc_count = ATOMIC_INIT(0);
+-
 -static int fsl_mc_driver_probe(struct device *dev)
 -{
 -	struct fsl_mc_driver *mc_drv;
@@ -5692,7 +4902,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -	error = mc_drv->probe(mc_dev);
 -	if (error < 0) {
--		dev_err(dev, "%s failed: %d\n", __func__, error);
+-		dev_err(dev, "MC object device probe callback failed: %d\n",
+-			error);
 -		return error;
 -	}
 -
@@ -5710,7 +4921,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -	error = mc_drv->remove(mc_dev);
 -	if (error < 0) {
--		dev_err(dev, "%s failed: %d\n", __func__, error);
+-		dev_err(dev,
+-			"MC object device remove callback failed: %d\n",
+-			error);
 -		return error;
 -	}
 -
@@ -5757,6 +4970,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		return error;
 -	}
 -
+-	pr_info("MC object device driver %s registered\n",
+-		mc_driver->driver.name);
 -	return 0;
 -}
 -EXPORT_SYMBOL_GPL(__fsl_mc_driver_register);
@@ -5772,46 +4987,19 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -EXPORT_SYMBOL_GPL(fsl_mc_driver_unregister);
 -
 -/**
-- * mc_get_version() - Retrieves the Management Complex firmware
-- *			version information
-- * @mc_io:		Pointer to opaque I/O object
-- * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
-- * @mc_ver_info:	Returned version information structure
-- *
-- * Return:	'0' on Success; Error code otherwise.
+- * fsl_mc_bus_exists - check if a root dprc exists
 - */
--static int mc_get_version(struct fsl_mc_io *mc_io,
--			  u32 cmd_flags,
--			  struct mc_version *mc_ver_info)
+-bool fsl_mc_bus_exists(void)
 -{
--	struct mc_command cmd = { 0 };
--	struct dpmng_rsp_get_version *rsp_params;
--	int err;
--
--	/* prepare command */
--	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION,
--					  cmd_flags,
--					  0);
--
--	/* send command to mc*/
--	err = mc_send_command(mc_io, &cmd);
--	if (err)
--		return err;
--
--	/* retrieve response parameters */
--	rsp_params = (struct dpmng_rsp_get_version *)cmd.params;
--	mc_ver_info->revision = le32_to_cpu(rsp_params->revision);
--	mc_ver_info->major = le32_to_cpu(rsp_params->version_major);
--	mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor);
--
--	return 0;
+-	return atomic_read(&root_dprc_count) > 0;
 -}
+-EXPORT_SYMBOL_GPL(fsl_mc_bus_exists);
 -
 -/**
 - * fsl_mc_get_root_dprc - function to traverse to the root dprc
 - */
--static void fsl_mc_get_root_dprc(struct device *dev,
--				 struct device **root_dprc_dev)
+-void fsl_mc_get_root_dprc(struct device *dev,
+-			  struct device **root_dprc_dev)
 -{
 -	if (WARN_ON(!dev)) {
 -		*root_dprc_dev = NULL;
@@ -5823,6 +5011,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -			*root_dprc_dev = (*root_dprc_dev)->parent;
 -	}
 -}
+-EXPORT_SYMBOL_GPL(fsl_mc_get_root_dprc);
 -
 -static int get_dprc_attr(struct fsl_mc_io *mc_io,
 -			 int container_id, struct dprc_attributes *attr)
@@ -5864,6 +5053,21 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	return error;
 -}
 -
+-static int get_dprc_version(struct fsl_mc_io *mc_io,
+-			    int container_id, u16 *major, u16 *minor)
+-{
+-	struct dprc_attributes attr;
+-	int error;
+-
+-	error = get_dprc_attr(mc_io, container_id, &attr);
+-	if (error == 0) {
+-		*major = attr.version.major;
+-		*minor = attr.version.minor;
+-	}
+-
+-	return error;
+-}
+-
 -static int translate_mc_addr(struct fsl_mc_device *mc_dev,
 -			     enum dprc_region_type mc_region_type,
 -			     u64 mc_offset, phys_addr_t *phys_addr)
@@ -5907,7 +5111,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	int i;
 -	int error;
 -	struct resource *regions;
--	struct fsl_mc_obj_desc *obj_desc = &mc_dev->obj_desc;
+-	struct dprc_obj_desc *obj_desc = &mc_dev->obj_desc;
 -	struct device *parent_dev = mc_dev->dev.parent;
 -	enum dprc_region_type mc_region_type;
 -
@@ -5985,22 +5189,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	return dev == root_dprc_dev;
 -}
 -
--static void fsl_mc_device_release(struct device *dev)
--{
--	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
--
--	kfree(mc_dev->regions);
--
--	if (strcmp(mc_dev->obj_desc.type, "dprc") == 0)
--		kfree(to_fsl_mc_bus(mc_dev));
--	else
--		kfree(mc_dev);
--}
--
 -/**
-- * Add a newly discovered fsl-mc device to be visible in Linux
+- * Add a newly discovered MC object device to be visible in Linux
 - */
--int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc,
+-int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
 -		      struct fsl_mc_io *mc_io,
 -		      struct device *parent_dev,
 -		      struct fsl_mc_device **new_mc_dev)
@@ -6019,7 +5211,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		/*
 -		 * Allocate an MC bus device object:
 -		 */
--		mc_bus = kzalloc(sizeof(*mc_bus), GFP_KERNEL);
+-		mc_bus = devm_kzalloc(parent_dev, sizeof(*mc_bus), GFP_KERNEL);
 -		if (!mc_bus)
 -			return -ENOMEM;
 -
@@ -6028,7 +5220,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		/*
 -		 * Allocate a regular fsl_mc_device object:
 -		 */
--		mc_dev = kzalloc(sizeof(*mc_dev), GFP_KERNEL);
+-		mc_dev = kmem_cache_zalloc(mc_dev_cache, GFP_KERNEL);
 -		if (!mc_dev)
 -			return -ENOMEM;
 -	}
@@ -6038,7 +5230,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	device_initialize(&mc_dev->dev);
 -	mc_dev->dev.parent = parent_dev;
 -	mc_dev->dev.bus = &fsl_mc_bus_type;
--	mc_dev->dev.release = fsl_mc_device_release;
 -	dev_set_name(&mc_dev->dev, "%s.%d", obj_desc->type, obj_desc->id);
 -
 -	if (strcmp(obj_desc->type, "dprc") == 0) {
@@ -6071,6 +5262,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -			}
 -
 -			mc_io2 = mc_io;
+-
+-			atomic_inc(&root_dprc_count);
 -		}
 -
 -		error = get_dprc_icid(mc_io2, obj_desc->id, &mc_dev->icid);
@@ -6078,8 +5271,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -			goto error_cleanup_dev;
 -	} else {
 -		/*
--		 * A non-DPRC object has to be a child of a DPRC, use the
--		 * parent's ICID and interrupt domain.
+-		 * A non-DPRC MC object device has to be a child of another
+-		 * MC object (specifically a DPRC object)
 -		 */
 -		mc_dev->icid = parent_mc_dev->icid;
 -		mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK;
@@ -6102,7 +5295,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	}
 -
 -	/* Objects are coherent, unless 'no shareability' flag set. */
--	if (!(obj_desc->flags & FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY))
+-	if (!(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY))
 -		arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true);
 -
 -	/*
@@ -6116,33 +5309,57 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		goto error_cleanup_dev;
 -	}
 -
--	dev_dbg(parent_dev, "added %s\n", dev_name(&mc_dev->dev));
+-	(void)get_device(&mc_dev->dev);
+-	dev_dbg(parent_dev, "Added MC object device %s\n",
+-		dev_name(&mc_dev->dev));
 -
 -	*new_mc_dev = mc_dev;
 -	return 0;
 -
 -error_cleanup_dev:
 -	kfree(mc_dev->regions);
--	kfree(mc_bus);
--	kfree(mc_dev);
+-	if (mc_bus)
+-		devm_kfree(parent_dev, mc_bus);
+-	else
+-		kmem_cache_free(mc_dev_cache, mc_dev);
 -
 -	return error;
 -}
 -EXPORT_SYMBOL_GPL(fsl_mc_device_add);
 -
 -/**
-- * fsl_mc_device_remove - Remove an fsl-mc device from being visible to
+- * fsl_mc_device_remove - Remove a MC object device from being visible to
 - * Linux
 - *
-- * @mc_dev: Pointer to an fsl-mc device
+- * @mc_dev: Pointer to a MC object device object
 - */
 -void fsl_mc_device_remove(struct fsl_mc_device *mc_dev)
 -{
+-	struct fsl_mc_bus *mc_bus = NULL;
+-
+-	kfree(mc_dev->regions);
+-
 -	/*
 -	 * The device-specific remove callback will get invoked by device_del()
 -	 */
 -	device_del(&mc_dev->dev);
 -	put_device(&mc_dev->dev);
+-
+-	if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) {
+-		mc_bus = to_fsl_mc_bus(mc_dev);
+-
+-		if (fsl_mc_is_root_dprc(&mc_dev->dev)) {
+-			if (atomic_read(&root_dprc_count) > 0)
+-				atomic_dec(&root_dprc_count);
+-			else
+-				WARN_ON(1);
+-		}
+-	}
+-
+-	if (mc_bus)
+-		devm_kfree(mc_dev->dev.parent, mc_bus);
+-	else
+-		kmem_cache_free(mc_dev_cache, mc_dev);
 -}
 -EXPORT_SYMBOL_GPL(fsl_mc_device_remove);
 -
@@ -6150,7 +5367,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -			   int *paddr_cells,
 -			   int *mc_addr_cells,
 -			   int *mc_size_cells,
--			   const __be32 **ranges_start)
+-			   const __be32 **ranges_start,
+-			   u8 *num_ranges)
 -{
 -	const __be32 *prop;
 -	int range_tuple_cell_count;
@@ -6163,6 +5381,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		dev_warn(dev,
 -			 "missing or empty ranges property for device tree node '%s'\n",
 -			 mc_node->name);
+-
+-		*num_ranges = 0;
 -		return 0;
 -	}
 -
@@ -6189,7 +5409,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		return -EINVAL;
 -	}
 -
--	return ranges_len / tuple_len;
+-	*num_ranges = ranges_len / tuple_len;
+-	return 0;
 -}
 -
 -static int get_mc_addr_translation_ranges(struct device *dev,
@@ -6197,7 +5418,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -						**ranges,
 -					  u8 *num_ranges)
 -{
--	int ret;
+-	int error;
 -	int paddr_cells;
 -	int mc_addr_cells;
 -	int mc_size_cells;
@@ -6205,16 +5426,16 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	const __be32 *ranges_start;
 -	const __be32 *cell;
 -
--	ret = parse_mc_ranges(dev,
--			      &paddr_cells,
--			      &mc_addr_cells,
--			      &mc_size_cells,
--			      &ranges_start);
--	if (ret < 0)
--		return ret;
+-	error = parse_mc_ranges(dev,
+-				&paddr_cells,
+-				&mc_addr_cells,
+-				&mc_size_cells,
+-				&ranges_start,
+-				num_ranges);
+-	if (error < 0)
+-		return error;
 -
--	*num_ranges = ret;
--	if (!ret) {
+-	if (!(*num_ranges)) {
 -		/*
 -		 * Missing or empty ranges property ("ranges;") for the
 -		 * 'fsl,qoriq-mc' node. In this case, identity mapping
@@ -6255,7 +5476,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - */
 -static int fsl_mc_bus_probe(struct platform_device *pdev)
 -{
--	struct fsl_mc_obj_desc obj_desc;
+-	struct dprc_obj_desc obj_desc;
 -	int error;
 -	struct fsl_mc *mc;
 -	struct fsl_mc_device *mc_bus_dev = NULL;
@@ -6266,6 +5487,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	struct mc_version mc_version;
 -	struct resource res;
 -
+-	dev_info(&pdev->dev, "Root MC bus device probed");
+-
 -	mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
 -	if (!mc)
 -		return -ENOMEM;
@@ -6278,8 +5501,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	error = of_address_to_resource(pdev->dev.of_node, 0, &res);
 -	if (error < 0) {
 -		dev_err(&pdev->dev,
--			"of_address_to_resource() failed for %pOF\n",
--			pdev->dev.of_node);
+-			"of_address_to_resource() failed for %s\n",
+-			pdev->dev.of_node->full_name);
 -		return error;
 -	}
 -
@@ -6298,7 +5521,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		goto error_cleanup_mc_io;
 -	}
 -
--	dev_info(&pdev->dev, "MC firmware version: %u.%u.%u\n",
+-	dev_info(&pdev->dev,
+-		 "Freescale Management Complex Firmware version: %u.%u.%u\n",
 -		 mc_version.major, mc_version.minor, mc_version.revision);
 -
 -	error = get_mc_addr_translation_ranges(&pdev->dev,
@@ -6307,17 +5531,16 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	if (error < 0)
 -		goto error_cleanup_mc_io;
 -
--	error = dprc_get_container_id(mc_io, 0, &container_id);
+-	error = dpmng_get_container_id(mc_io, 0, &container_id);
 -	if (error < 0) {
 -		dev_err(&pdev->dev,
--			"dprc_get_container_id() failed: %d\n", error);
+-			"dpmng_get_container_id() failed: %d\n", error);
 -		goto error_cleanup_mc_io;
 -	}
 -
--	memset(&obj_desc, 0, sizeof(struct fsl_mc_obj_desc));
--	error = dprc_get_api_version(mc_io, 0,
--				     &obj_desc.ver_major,
--				     &obj_desc.ver_minor);
+-	memset(&obj_desc, 0, sizeof(struct dprc_obj_desc));
+-	error = get_dprc_version(mc_io, container_id,
+-				 &obj_desc.ver_major, &obj_desc.ver_minor);
 -	if (error < 0)
 -		goto error_cleanup_mc_io;
 -
@@ -6355,6 +5578,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io);
 -	mc->root_mc_bus_dev->mc_io = NULL;
 -
+-	dev_info(&pdev->dev, "Root MC bus device removed");
 -	return 0;
 -}
 -
@@ -6379,12 +5603,22 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -{
 -	int error;
 -
+-	mc_dev_cache = kmem_cache_create("fsl_mc_device",
+-					 sizeof(struct fsl_mc_device), 0, 0,
+-					 NULL);
+-	if (!mc_dev_cache) {
+-		pr_err("Could not create fsl_mc_device cache\n");
+-		return -ENOMEM;
+-	}
+-
 -	error = bus_register(&fsl_mc_bus_type);
 -	if (error < 0) {
--		pr_err("bus type registration failed: %d\n", error);
+-		pr_err("fsl-mc bus type registration failed: %d\n", error);
 -		goto error_cleanup_cache;
 -	}
 -
+-	pr_info("fsl-mc bus type registered\n");
+-
 -	error = platform_driver_register(&fsl_mc_bus_driver);
 -	if (error < 0) {
 -		pr_err("platform_driver_register() failed: %d\n", error);
@@ -6418,12 +5652,13 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	bus_unregister(&fsl_mc_bus_type);
 -
 -error_cleanup_cache:
+-	kmem_cache_destroy(mc_dev_cache);
 -	return error;
 -}
 -postcore_initcall(fsl_mc_bus_driver_init);
 --- /dev/null
 +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c
-@@ -0,0 +1,1139 @@
+@@ -0,0 +1,1151 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Freescale Management Complex (MC) bus driver
@@ -6444,6 +5679,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#include <linux/bitops.h>
 +#include <linux/msi.h>
 +#include <linux/dma-mapping.h>
++#include <linux/fsl/mc.h>
 +
 +#include "fsl-mc-private.h"
 +
@@ -7119,6 +6355,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	struct fsl_mc_device *mc_dev = NULL;
 +	struct fsl_mc_bus *mc_bus = NULL;
 +	struct fsl_mc_device *parent_mc_dev;
++	struct device *fsl_mc_platform_dev;
++	struct device_node *fsl_mc_platform_node;
 +
 +	if (dev_is_fsl_mc(parent_dev))
 +		parent_mc_dev = to_fsl_mc_device(parent_dev);
@@ -7231,6 +6469,15 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			goto error_cleanup_dev;
 +	}
 +
++	fsl_mc_platform_dev = &mc_dev->dev;
++	while (dev_is_fsl_mc(fsl_mc_platform_dev))
++		fsl_mc_platform_dev = fsl_mc_platform_dev->parent;
++	fsl_mc_platform_node = fsl_mc_platform_dev->of_node;
++
++	/* Set up the iommu configuration for the devices. */
++	fsl_mc_dma_configure(mc_dev, fsl_mc_platform_node,
++		!(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY));
++
 +	/*
 +	 * The device-specific probe callback will get invoked by device_add()
 +	 */
@@ -7563,27 +6810,111 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	return error;
 +}
 +postcore_initcall(fsl_mc_bus_driver_init);
+--- /dev/null
++++ b/drivers/bus/fsl-mc/fsl-mc-iommu.c
+@@ -0,0 +1,78 @@
++/*
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ * Author: Nipun Gupta <nipun.gupta@nxp.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/iommu.h>
++#include <linux/of.h>
++#include <linux/of_iommu.h>
++#include <linux/fsl/mc.h>
++
++/* Setup the IOMMU for the DPRC container */
++static const struct iommu_ops
++*fsl_mc_iommu_configure(struct fsl_mc_device *mc_dev,
++	struct device_node *fsl_mc_platform_node)
++{
++	struct of_phandle_args iommu_spec;
++	const struct iommu_ops *ops;
++	u32 iommu_phandle;
++	struct device_node *iommu_node;
++	const __be32 *map = NULL;
++	int iommu_cells, map_len, ret;
++
++	map = of_get_property(fsl_mc_platform_node, "iommu-map", &map_len);
++	if (!map)
++		return NULL;
++
++	ops = mc_dev->dev.bus->iommu_ops;
++	if (!ops || !ops->of_xlate)
++		return NULL;
++
++	iommu_phandle = be32_to_cpup(map + 1);
++	iommu_node = of_find_node_by_phandle(iommu_phandle);
++
++	if (of_property_read_u32(iommu_node, "#iommu-cells", &iommu_cells)) {
++		pr_err("%s: missing #iommu-cells property\n", iommu_node->name);
++		return NULL;
++	}
++
++	/* Initialize the fwspec */
++	ret = iommu_fwspec_init(&mc_dev->dev, &iommu_node->fwnode, ops);
++	if (ret)
++		return NULL;
++
++	/*
++	 * Fill in the required stream-id before calling the iommu's
++	 * ops->xlate callback.
++	 */
++	iommu_spec.np = iommu_node;
++	iommu_spec.args[0] = mc_dev->icid;
++	iommu_spec.args_count = 1;
++
++	ret = ops->of_xlate(&mc_dev->dev, &iommu_spec);
++	if (ret)
++		return NULL;
++
++	of_node_put(iommu_spec.np);
++
++	return ops;
++}
++
++/* Set up DMA configuration for fsl-mc devices */
++void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
++	struct device_node *fsl_mc_platform_node, int coherent)
++{
++	const struct iommu_ops *ops;
++
++	ops = fsl_mc_iommu_configure(mc_dev, fsl_mc_platform_node);
++
++	mc_dev->dev.coherent_dma_mask = DMA_BIT_MASK(48);
++	mc_dev->dev.dma_mask = &mc_dev->dev.coherent_dma_mask;
++	arch_setup_dma_ops(&mc_dev->dev, 0,
++		mc_dev->dev.coherent_dma_mask + 1, ops, coherent);
++}
 --- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
 +++ /dev/null
 @@ -1,285 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0
 -/*
 - * Freescale Management Complex (MC) bus driver MSI support
 - *
-- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+- * Copyright (C) 2015 Freescale Semiconductor, Inc.
 - * Author: German Rivera <German.Rivera@freescale.com>
 - *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
 - */
 -
 -#include <linux/of_device.h>
 -#include <linux/of_address.h>
+-#include <linux/irqchip/arm-gic-v3.h>
 -#include <linux/of_irq.h>
 -#include <linux/irq.h>
 -#include <linux/irqdomain.h>
 -#include <linux/msi.h>
+-#include "../include/mc-bus.h"
 -#include "fsl-mc-private.h"
 -
--#ifdef GENERIC_MSI_DOMAIN_OPS
 -/*
 - * Generate a unique ID identifying the interrupt (only used within the MSI
 - * irqdomain.  Combine the icid with the interrupt index.
@@ -7605,9 +6936,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev),
 -					      desc);
 -}
--#else
--#define fsl_mc_msi_set_desc NULL
--#endif
 -
 -static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info)
 -{
@@ -7738,7 +7066,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -	domain = msi_create_irq_domain(fwnode, info, parent);
 -	if (domain)
--		irq_domain_update_bus_token(domain, DOMAIN_BUS_FSL_MC_MSI);
+-		domain->bus_token = DOMAIN_BUS_FSL_MC_MSI;
 -
 -	return domain;
 -}
@@ -7752,8 +7080,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	msi_domain = of_msi_get_domain(mc_platform_dev, mc_of_node,
 -				       DOMAIN_BUS_FSL_MC_MSI);
 -	if (!msi_domain) {
--		pr_err("Unable to find fsl-mc MSI domain for %pOF\n",
--		       mc_of_node);
+-		pr_err("Unable to find fsl-mc MSI domain for %s\n",
+-		       mc_of_node->full_name);
 -
 -		return -ENOENT;
 -	}
@@ -8589,15 +7917,42 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- a/drivers/staging/fsl-mc/bus/mc-io.c
 +++ /dev/null
-@@ -1,292 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
--/*
-- * Copyright 2013-2016 Freescale Semiconductor Inc.
+@@ -1,320 +0,0 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
 - *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of the above-listed copyright holders nor the
+- *       names of any contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
 - */
 -
 -#include <linux/io.h>
--#include "../include/mc.h"
+-#include "../include/mc-bus.h"
+-#include "../include/mc-sys.h"
 -
 -#include "fsl-mc-private.h"
 -#include "dpmcp.h"
@@ -8695,8 +8050,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -				      "mc_portal");
 -	if (!res) {
 -		dev_err(dev,
--			"devm_request_mem_region failed for MC portal %pa\n",
--			&mc_portal_phys_addr);
+-			"devm_request_mem_region failed for MC portal %#llx\n",
+-			mc_portal_phys_addr);
 -		return -EBUSY;
 -	}
 -
@@ -8705,8 +8060,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -						   mc_portal_size);
 -	if (!mc_portal_virt_addr) {
 -		dev_err(dev,
--			"devm_ioremap_nocache failed for MC portal %pa\n",
--			&mc_portal_phys_addr);
+-			"devm_ioremap_nocache failed for MC portal %#llx\n",
+-			mc_portal_phys_addr);
 -		return -ENXIO;
 -	}
 -
@@ -8808,7 +8163,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		goto error_cleanup_resource;
 -
 -	mc_portal_phys_addr = dpmcp_dev->regions[0].start;
--	mc_portal_size = resource_size(dpmcp_dev->regions);
+-	mc_portal_size = dpmcp_dev->regions[0].end -
+-			 dpmcp_dev->regions[0].start + 1;
 -
 -	if (WARN_ON(mc_portal_size != mc_bus_dev->mc_io->portal_size))
 -		goto error_cleanup_resource;
@@ -9155,13 +8511,39 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +EXPORT_SYMBOL_GPL(fsl_mc_portal_reset);
 --- a/drivers/staging/fsl-mc/bus/mc-sys.c
 +++ /dev/null
-@@ -1,297 +0,0 @@
--// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
--/*
-- * Copyright 2013-2016 Freescale Semiconductor Inc.
+@@ -1,317 +0,0 @@
+-/* Copyright 2013-2014 Freescale Semiconductor Inc.
 - *
 - * I/O services to send MC commands to the MC hardware
 - *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of the above-listed copyright holders nor the
+- *       names of any contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
 - */
 -
 -#include <linux/delay.h>
@@ -9169,7 +8551,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -#include <linux/ioport.h>
 -#include <linux/device.h>
 -#include <linux/io.h>
--#include <linux/io-64-nonatomic-hi-lo.h>
+-#include "../include/mc-sys.h"
+-#include "../include/mc-cmd.h"
 -#include "../include/mc.h"
 -
 -#include "dpmcp.h"
@@ -9198,7 +8581,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
 -	u16 cmd_id = le16_to_cpu(hdr->cmd_id);
 -
--	return cmd_id;
+-	return (cmd_id & MC_CMD_HDR_CMDID_MASK) >> MC_CMD_HDR_CMDID_SHIFT;
 -}
 -
 -static int mc_status_to_error(enum mc_cmd_status status)
@@ -9259,15 +8642,11 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -	/* copy command parameters into the portal */
 -	for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
--		/*
--		 * Data is already in the expected LE byte-order. Do an
--		 * extra LE -> CPU conversion so that the CPU -> LE done in
--		 * the device io write api puts it back in the right order.
--		 */
--		writeq_relaxed(le64_to_cpu(cmd->params[i]), &portal->params[i]);
+-		__raw_writeq(cmd->params[i], &portal->params[i]);
+-	__iowmb();
 -
 -	/* submit the command by writing the header */
--	writeq(le64_to_cpu(cmd->header), &portal->header);
+-	__raw_writeq(cmd->header, &portal->header);
 -}
 -
 -/**
@@ -9287,20 +8666,17 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	enum mc_cmd_status status;
 -
 -	/* Copy command response header from MC portal: */
--	resp->header = cpu_to_le64(readq_relaxed(&portal->header));
+-	__iormb();
+-	resp->header = __raw_readq(&portal->header);
+-	__iormb();
 -	status = mc_cmd_hdr_read_status(resp);
 -	if (status != MC_CMD_STATUS_OK)
 -		return status;
 -
 -	/* Copy command response data from MC portal: */
 -	for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
--		/*
--		 * Data is expected to be in LE byte-order. Do an
--		 * extra CPU -> LE to revert the LE -> CPU done in
--		 * the device io read api.
--		 */
--		resp->params[i] =
--			cpu_to_le64(readq_relaxed(&portal->params[i]));
+-		resp->params[i] = __raw_readq(&portal->params[i]);
+-	__iormb();
 -
 -	return status;
 -}
@@ -9338,8 +8714,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -		if (time_after_eq(jiffies, jiffies_until_timeout)) {
 -			dev_dbg(mc_io->dev,
--				"MC command timed out (portal: %pa, dprc handle: %#x, command: %#x)\n",
--				 &mc_io->portal_phys_addr,
+-				"MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
+-				 mc_io->portal_phys_addr,
 -				 (unsigned int)mc_cmd_hdr_read_token(cmd),
 -				 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
 -
@@ -9378,8 +8754,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS;
 -		if (timeout_usecs == 0) {
 -			dev_dbg(mc_io->dev,
--				"MC command timed out (portal: %pa, dprc handle: %#x, command: %#x)\n",
--				 &mc_io->portal_phys_addr,
+-				"MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
+-				 mc_io->portal_phys_addr,
 -				 (unsigned int)mc_cmd_hdr_read_token(cmd),
 -				 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
 -
@@ -9432,8 +8808,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -
 -	if (status != MC_CMD_STATUS_OK) {
 -		dev_dbg(mc_io->dev,
--			"MC command failed: portal: %pa, dprc handle: %#x, command: %#x, status: %s (%#x)\n",
--			 &mc_io->portal_phys_addr,
+-			"MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n",
+-			 mc_io->portal_phys_addr,
 -			 (unsigned int)mc_cmd_hdr_read_token(cmd),
 -			 (unsigned int)mc_cmd_hdr_read_cmdid(cmd),
 -			 mc_status_to_string(status),
@@ -9754,9 +9130,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +EXPORT_SYMBOL_GPL(mc_send_command);
 --- a/drivers/irqchip/Kconfig
 +++ b/drivers/irqchip/Kconfig
-@@ -42,6 +42,12 @@ config ARM_GIC_V3_ITS
- 	depends on PCI
+@@ -41,6 +41,12 @@ config ARM_GIC_V3_ITS
  	depends on PCI_MSI
+ 	select ACPI_IORT if ACPI
  
 +config ARM_GIC_V3_ITS_FSL_MC
 +	bool
@@ -9769,14 +9145,143 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	select IRQ_DOMAIN
 --- a/drivers/irqchip/Makefile
 +++ b/drivers/irqchip/Makefile
-@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_REALVIEW)		+= irq-gic-
+@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_REALVIEW)		+= irq-gic-
  obj-$(CONFIG_ARM_GIC_V2M)		+= irq-gic-v2m.o
  obj-$(CONFIG_ARM_GIC_V3)		+= irq-gic-v3.o irq-gic-common.o
- obj-$(CONFIG_ARM_GIC_V3_ITS)		+= irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o
+ obj-$(CONFIG_ARM_GIC_V3_ITS)		+= irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
 +obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC)	+= irq-gic-v3-its-fsl-mc-msi.o
  obj-$(CONFIG_PARTITION_PERCPU)		+= irq-partition-percpu.o
  obj-$(CONFIG_HISILICON_IRQ_MBIGEN)	+= irq-mbigen.o
  obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o
+--- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
++++ /dev/null
+@@ -1,126 +0,0 @@
+-/*
+- * Freescale Management Complex (MC) bus driver MSI support
+- *
+- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+- * Author: German Rivera <German.Rivera@freescale.com>
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- */
+-
+-#include <linux/of_device.h>
+-#include <linux/of_address.h>
+-#include <linux/irqchip/arm-gic-v3.h>
+-#include <linux/irq.h>
+-#include <linux/msi.h>
+-#include <linux/of.h>
+-#include <linux/of_irq.h>
+-#include "../include/mc-bus.h"
+-#include "fsl-mc-private.h"
+-
+-static struct irq_chip its_msi_irq_chip = {
+-	.name = "fsl-mc-bus-msi",
+-	.irq_mask = irq_chip_mask_parent,
+-	.irq_unmask = irq_chip_unmask_parent,
+-	.irq_eoi = irq_chip_eoi_parent,
+-	.irq_set_affinity = msi_domain_set_affinity
+-};
+-
+-static int its_fsl_mc_msi_prepare(struct irq_domain *msi_domain,
+-				  struct device *dev,
+-				  int nvec, msi_alloc_info_t *info)
+-{
+-	struct fsl_mc_device *mc_bus_dev;
+-	struct msi_domain_info *msi_info;
+-
+-	if (WARN_ON(!dev_is_fsl_mc(dev)))
+-		return -EINVAL;
+-
+-	mc_bus_dev = to_fsl_mc_device(dev);
+-	if (WARN_ON(!(mc_bus_dev->flags & FSL_MC_IS_DPRC)))
+-		return -EINVAL;
+-
+-	/*
+-	 * Set the device Id to be passed to the GIC-ITS:
+-	 *
+-	 * NOTE: This device id corresponds to the IOMMU stream ID
+-	 * associated with the DPRC object (ICID).
+-	 */
+-	info->scratchpad[0].ul = mc_bus_dev->icid;
+-	msi_info = msi_get_domain_info(msi_domain->parent);
+-	return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info);
+-}
+-
+-static struct msi_domain_ops its_fsl_mc_msi_ops = {
+-	.msi_prepare = its_fsl_mc_msi_prepare,
+-};
+-
+-static struct msi_domain_info its_fsl_mc_msi_domain_info = {
+-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
+-	.ops	= &its_fsl_mc_msi_ops,
+-	.chip	= &its_msi_irq_chip,
+-};
+-
+-static const struct of_device_id its_device_id[] = {
+-	{	.compatible	= "arm,gic-v3-its",	},
+-	{},
+-};
+-
+-int __init its_fsl_mc_msi_init(void)
+-{
+-	struct device_node *np;
+-	struct irq_domain *parent;
+-	struct irq_domain *mc_msi_domain;
+-
+-	for (np = of_find_matching_node(NULL, its_device_id); np;
+-	     np = of_find_matching_node(np, its_device_id)) {
+-		if (!of_device_is_available(np))
+-			continue;
+-		if (!of_property_read_bool(np, "msi-controller"))
+-			continue;
+-
+-		parent = irq_find_matching_host(np, DOMAIN_BUS_NEXUS);
+-		if (!parent || !msi_get_domain_info(parent)) {
+-			pr_err("%s: unable to locate ITS domain\n",
+-			       np->full_name);
+-			continue;
+-		}
+-
+-		mc_msi_domain = fsl_mc_msi_create_irq_domain(
+-						 of_node_to_fwnode(np),
+-						 &its_fsl_mc_msi_domain_info,
+-						 parent);
+-		if (!mc_msi_domain) {
+-			pr_err("%s: unable to create fsl-mc domain\n",
+-			       np->full_name);
+-			continue;
+-		}
+-
+-		WARN_ON(mc_msi_domain->
+-				host_data != &its_fsl_mc_msi_domain_info);
+-
+-		pr_info("fsl-mc MSI: %s domain created\n", np->full_name);
+-	}
+-
+-	return 0;
+-}
+-
+-void its_fsl_mc_msi_cleanup(void)
+-{
+-	struct device_node *np;
+-
+-	for (np = of_find_matching_node(NULL, its_device_id); np;
+-	     np = of_find_matching_node(np, its_device_id)) {
+-		struct irq_domain *mc_msi_domain = irq_find_matching_host(
+-							np,
+-							DOMAIN_BUS_FSL_MC_MSI);
+-
+-		if (!of_property_read_bool(np, "msi-controller"))
+-			continue;
+-
+-		if (mc_msi_domain &&
+-		    mc_msi_domain->host_data == &its_fsl_mc_msi_domain_info)
+-			irq_domain_remove(mc_msi_domain);
+-	}
+-}
 --- /dev/null
 +++ b/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
 @@ -0,0 +1,98 @@
@@ -9878,54 +9383,17 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 +
 +early_initcall(its_fsl_mc_msi_init);
---- a/drivers/staging/fsl-dpaa2/ethernet/README
-+++ b/drivers/staging/fsl-dpaa2/ethernet/README
-@@ -36,7 +36,7 @@ are treated as internal resources of oth
- 
- For a more detailed description of the DPAA2 architecture and its object
- abstractions see:
--	drivers/staging/fsl-mc/README.txt
-+	Documentation/networking/dpaa2/overview.rst
- 
- Each Linux net device is built on top of a Datapath Network Interface (DPNI)
- object and uses Buffer Pools (DPBPs), I/O Portals (DPIOs) and Concentrators
---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
-@@ -43,7 +43,7 @@
- #include <linux/filter.h>
- #include <linux/atomic.h>
- #include <net/sock.h>
--#include "../../fsl-mc/include/mc.h"
-+#include <linux/fsl/mc.h>
- #include "dpaa2-eth.h"
- #include "dpaa2-eth-ceetm.h"
- 
---- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
-@@ -36,11 +36,10 @@
- #include <linux/dcbnl.h>
- #include <linux/netdevice.h>
- #include <linux/if_vlan.h>
-+#include <linux/fsl/mc.h>
- 
- #include "../../fsl-mc/include/dpaa2-io.h"
- #include "../../fsl-mc/include/dpaa2-fd.h"
--#include "../../fsl-mc/include/dpbp.h"
--#include "../../fsl-mc/include/dpcon.h"
- #include "dpni.h"
- #include "dpni-cmd.h"
- 
---- a/drivers/staging/fsl-dpaa2/ethernet/dpni.c
-+++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c
-@@ -32,7 +32,7 @@
-  */
- #include <linux/kernel.h>
- #include <linux/errno.h>
--#include "../../fsl-mc/include/mc.h"
-+#include <linux/fsl/mc.h>
- #include "dpni.h"
- #include "dpni-cmd.h"
- 
+--- a/drivers/staging/fsl-mc/Kconfig
++++ b/drivers/staging/fsl-mc/Kconfig
+@@ -1 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
+ source "drivers/staging/fsl-mc/bus/Kconfig"
+--- a/drivers/staging/fsl-mc/Makefile
++++ b/drivers/staging/fsl-mc/Makefile
+@@ -1,2 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0
+ # Freescale Management Complex (MC) bus drivers
+ obj-$(CONFIG_FSL_MC_BUS)	+= bus/
 --- a/drivers/staging/fsl-mc/TODO
 +++ /dev/null
 @@ -1,18 +0,0 @@
@@ -9949,28 +9417,44 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -[2] https://lkml.org/lkml/2015/7/7/712
 --- a/drivers/staging/fsl-mc/bus/Kconfig
 +++ b/drivers/staging/fsl-mc/bus/Kconfig
-@@ -5,16 +5,6 @@
- # Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+@@ -1,25 +1,22 @@
++# SPDX-License-Identifier: GPL-2.0
  #
- 
+-# Freescale Management Complex (MC) bus drivers
++# DPAA2 fsl-mc bus
+ #
+-# Copyright (C) 2014 Freescale Semiconductor, Inc.
++# Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ #
+-# This file is released under the GPLv2
+-#
+-
 -config FSL_MC_BUS
--	bool "QorIQ DPAA2 fsl-mc bus driver"
--	depends on OF && (ARCH_LAYERSCAPE || (COMPILE_TEST && (ARM || ARM64 || X86_LOCAL_APIC || PPC)))
+-	bool "Freescale Management Complex (MC) bus driver"
+-	depends on OF && ARM64
 -	select GENERIC_MSI_IRQ_DOMAIN
 -	help
--	  Driver to enable the bus infrastructure for the QorIQ DPAA2
--	  architecture.  The fsl-mc bus driver handles discovery of
--	  DPAA2 objects (which are represented as Linux devices) and
--	  binding objects to drivers.
+-	  Driver to enable the bus infrastructure for the Freescale
+-          QorIQ Management Complex (fsl-mc). The fsl-mc is a hardware
+-	  module of the QorIQ LS2 SoCs, that does resource management
+-	  for hardware building-blocks in the SoC that can be used
+-	  to dynamically create networking hardware objects such as
+-	  network interfaces (NICs), crypto accelerator instances,
+-	  or L2 switches.
 -
- config FSL_MC_DPIO
-         tristate "QorIQ DPAA2 DPIO driver"
-         depends on FSL_MC_BUS
-@@ -24,3 +14,9 @@ config FSL_MC_DPIO
- 	  other DPAA2 objects. This driver does not expose the DPIO
- 	  objects individually, but groups them under a service layer
- 	  API.
-+
+-	  Only enable this option when building the kernel for
+-	  Freescale QorQIQ LS2xxxx SoCs.
+ 
++config FSL_MC_DPIO
++        tristate "QorIQ DPAA2 DPIO driver"
++	depends on FSL_MC_BUS
++        help
++	  Driver for the DPAA2 DPIO object.  A DPIO provides queue and
++	  buffer management facilities for software to interact with
++	  other DPAA2 objects. This driver does not expose the DPIO
++	  objects individually, but groups them under a service layer
++	  API.
+ 
 +config FSL_QBMAN_DEBUG
 +	tristate "Freescale QBMAN Debug APIs"
 +	depends on FSL_MC_DPIO
@@ -9978,118 +9462,34 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	  QBMan debug assistant APIs.
 --- a/drivers/staging/fsl-mc/bus/Makefile
 +++ b/drivers/staging/fsl-mc/bus/Makefile
-@@ -4,19 +4,6 @@
+@@ -1,20 +1,9 @@
++# SPDX-License-Identifier: GPL-2.0
+ #
+ # Freescale Management Complex (MC) bus drivers
  #
  # Copyright (C) 2014 Freescale Semiconductor, Inc.
  #
+-# This file is released under the GPLv2
+-#
 -obj-$(CONFIG_FSL_MC_BUS) += mc-bus-driver.o
--
+ 
 -mc-bus-driver-objs := fsl-mc-bus.o \
 -		      mc-sys.o \
 -		      mc-io.o \
 -		      dprc.o \
+-		      dpmng.o \
 -		      dprc-driver.o \
 -		      fsl-mc-allocator.o \
 -		      fsl-mc-msi.o \
 -		      irq-gic-v3-its-fsl-mc-msi.o \
 -		      dpmcp.o \
--		      dpbp.o \
--		      dpcon.o
- 
- # MC DPIO driver
- obj-$(CONFIG_FSL_MC_DPIO) += dpio/
---- a/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
-+++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
-@@ -14,7 +14,7 @@
- #include <linux/dma-mapping.h>
- #include <linux/delay.h>
- 
--#include "../../include/mc.h"
-+#include <linux/fsl/mc.h>
- #include "../../include/dpaa2-io.h"
- 
- #include "qbman-portal.h"
---- a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
-+++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
-@@ -5,7 +5,7 @@
-  *
-  */
- #include <linux/types.h>
--#include "../../include/mc.h"
-+#include <linux/fsl/mc.h>
- #include "../../include/dpaa2-io.h"
- #include <linux/init.h>
- #include <linux/module.h>
---- a/drivers/staging/fsl-mc/bus/dpio/dpio.c
-+++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c
-@@ -5,7 +5,7 @@
-  *
-  */
- #include <linux/kernel.h>
--#include "../../include/mc.h"
-+#include <linux/fsl/mc.h>
- 
- #include "dpio.h"
- #include "dpio-cmd.h"
-@@ -37,7 +37,7 @@ int dpio_open(struct fsl_mc_io *mc_io,
- 	      int dpio_id,
- 	      u16 *token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpio_cmd_open *dpio_cmd;
- 	int err;
- 
-@@ -70,7 +70,7 @@ int dpio_close(struct fsl_mc_io *mc_io,
- 	       u32 cmd_flags,
- 	       u16 token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 
- 	/* prepare command */
- 	cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
-@@ -92,7 +92,7 @@ int dpio_enable(struct fsl_mc_io *mc_io,
- 		u32 cmd_flags,
- 		u16 token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 
- 	/* prepare command */
- 	cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
-@@ -114,7 +114,7 @@ int dpio_disable(struct fsl_mc_io *mc_io
- 		 u32 cmd_flags,
- 		 u16 token)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 
- 	/* prepare command */
- 	cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
-@@ -138,7 +138,7 @@ int dpio_get_attributes(struct fsl_mc_io
- 			u16 token,
- 			struct dpio_attr *attr)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	struct dpio_rsp_get_attr *dpio_rsp;
- 	int err;
- 
-@@ -180,7 +180,7 @@ int dpio_get_api_version(struct fsl_mc_i
- 			 u16 *major_ver,
- 			 u16 *minor_ver)
- {
--	struct mc_command cmd = { 0 };
-+	struct fsl_mc_command cmd = { 0 };
- 	int err;
- 
- 	/* prepare command */
---- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
+-		      dpbp.o
++# MC DPIO driver
++obj-$(CONFIG_FSL_MC_DPIO) += dpio/
+--- a/drivers/staging/fsl-mc/bus/dpbp.c
 +++ /dev/null
-@@ -1,56 +0,0 @@
--/*
-- * Copyright 2013-2016 Freescale Semiconductor Inc.
+@@ -1,691 +0,0 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
 - *
 - * Redistribution and use in source and binary forms, with or without
 - * modification, are permitted provided that the following conditions are met:
@@ -10102,6 +9502,3818 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * names of any contributors may be used to endorse or promote products
 - * derived from this software without specific prior written permission.
 - *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#include "../include/mc-sys.h"
+-#include "../include/mc-cmd.h"
+-#include "../include/dpbp.h"
+-#include "../include/dpbp-cmd.h"
+-
+-/**
+- * dpbp_open() - Open a control session for the specified object.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @dpbp_id:	DPBP unique ID
+- * @token:	Returned token; use in subsequent API calls
+- *
+- * This function can be used to open a control session for an
+- * already created object; an object may have been declared in
+- * the DPL or by calling the dpbp_create function.
+- * This function returns a unique authentication token,
+- * associated with the specific object ID and the specific MC
+- * portal; this token must be used in all subsequent commands for
+- * this specific object
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_open(struct fsl_mc_io *mc_io,
+-	      u32 cmd_flags,
+-	      int dpbp_id,
+-	      u16 *token)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_open *cmd_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN,
+-					  cmd_flags, 0);
+-	cmd_params = (struct dpbp_cmd_open *)cmd.params;
+-	cmd_params->dpbp_id = cpu_to_le32(dpbp_id);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	*token = mc_cmd_hdr_read_token(&cmd);
+-
+-	return err;
+-}
+-EXPORT_SYMBOL(dpbp_open);
+-
+-/**
+- * dpbp_close() - Close the control session of the object
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- *
+- * After this function is called, no further operations are
+- * allowed on the object without opening a new control session.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_close(struct fsl_mc_io *mc_io,
+-	       u32 cmd_flags,
+-	       u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLOSE, cmd_flags,
+-					  token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-EXPORT_SYMBOL(dpbp_close);
+-
+-/**
+- * dpbp_create() - Create the DPBP object.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @cfg:	Configuration structure
+- * @token:	Returned token; use in subsequent API calls
+- *
+- * Create the DPBP object, allocate required resources and
+- * perform required initialization.
+- *
+- * The object can be created either by declaring it in the
+- * DPL file, or by calling this function.
+- * This function returns a unique authentication token,
+- * associated with the specific object ID and the specific MC
+- * portal; this token must be used in all subsequent calls to
+- * this specific object. For objects that are created using the
+- * DPL file, call dpbp_open function to get an authentication
+- * token first.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_create(struct fsl_mc_io *mc_io,
+-		u32 cmd_flags,
+-		const struct dpbp_cfg *cfg,
+-		u16 *token)
+-{
+-	struct mc_command cmd = { 0 };
+-	int err;
+-
+-	(void)(cfg); /* unused */
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
+-					  cmd_flags, 0);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	*token = mc_cmd_hdr_read_token(&cmd);
+-
+-	return 0;
+-}
+-
+-/**
+- * dpbp_destroy() - Destroy the DPBP object and release all its resources.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- *
+- * Return:	'0' on Success; error code otherwise.
+- */
+-int dpbp_destroy(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpbp_enable() - Enable the DPBP.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_enable(struct fsl_mc_io *mc_io,
+-		u32 cmd_flags,
+-		u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_ENABLE, cmd_flags,
+-					  token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-EXPORT_SYMBOL(dpbp_enable);
+-
+-/**
+- * dpbp_disable() - Disable the DPBP.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_disable(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-EXPORT_SYMBOL(dpbp_disable);
+-
+-/**
+- * dpbp_is_enabled() - Check if the DPBP is enabled.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @en:		Returns '1' if object is enabled; '0' otherwise
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_is_enabled(struct fsl_mc_io *mc_io,
+-		    u32 cmd_flags,
+-		    u16 token,
+-		    int *en)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_rsp_is_enabled *rsp_params;
+-	int err;
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_IS_ENABLED, cmd_flags,
+-					  token);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpbp_rsp_is_enabled *)cmd.params;
+-	*en = rsp_params->enabled & DPBP_ENABLE;
+-
+-	return 0;
+-}
+-
+-/**
+- * dpbp_reset() - Reset the DPBP, returns the object to initial state.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_reset(struct fsl_mc_io *mc_io,
+-	       u32 cmd_flags,
+-	       u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpbp_set_irq() - Set IRQ information for the DPBP to trigger an interrupt.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @irq_index:	Identifies the interrupt index to configure
+- * @irq_cfg:	IRQ configuration
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_set_irq(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token,
+-		 u8 irq_index,
+-		 struct dpbp_irq_cfg *irq_cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_set_irq *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_set_irq *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-	cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
+-	cmd_params->irq_addr = cpu_to_le64(irq_cfg->addr);
+-	cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpbp_get_irq() - Get IRQ information from the DPBP.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @irq_index:	The interrupt index to configure
+- * @type:	Interrupt type: 0 represents message interrupt
+- *		type (both irq_addr and irq_val are valid)
+- * @irq_cfg:	IRQ attributes
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_get_irq(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token,
+-		 u8 irq_index,
+-		 int *type,
+-		 struct dpbp_irq_cfg *irq_cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_get_irq *cmd_params;
+-	struct dpbp_rsp_get_irq *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_get_irq *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpbp_rsp_get_irq *)cmd.params;
+-	irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
+-	irq_cfg->addr = le64_to_cpu(rsp_params->irq_addr);
+-	irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
+-	*type = le32_to_cpu(rsp_params->type);
+-
+-	return 0;
+-}
+-
+-/**
+- * dpbp_set_irq_enable() - Set overall interrupt state.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @irq_index:	The interrupt index to configure
+- * @en:	Interrupt state - enable = 1, disable = 0
+- *
+- * Allows GPP software to control when interrupts are generated.
+- * Each interrupt can have up to 32 causes.  The enable/disable control's the
+- * overall interrupt state. if the interrupt is disabled no causes will cause
+- * an interrupt.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			u8 irq_index,
+-			u8 en)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_set_irq_enable *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_ENABLE,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_set_irq_enable *)cmd.params;
+-	cmd_params->enable = en & DPBP_ENABLE;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpbp_get_irq_enable() - Get overall interrupt state
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @irq_index:	The interrupt index to configure
+- * @en:		Returned interrupt state - enable = 1, disable = 0
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			u8 irq_index,
+-			u8 *en)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_get_irq_enable *cmd_params;
+-	struct dpbp_rsp_get_irq_enable *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_ENABLE,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_get_irq_enable *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpbp_rsp_get_irq_enable *)cmd.params;
+-	*en = rsp_params->enabled & DPBP_ENABLE;
+-	return 0;
+-}
+-
+-/**
+- * dpbp_set_irq_mask() - Set interrupt mask.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @irq_index:	The interrupt index to configure
+- * @mask:	Event mask to trigger interrupt;
+- *			each bit:
+- *				0 = ignore event
+- *				1 = consider event for asserting IRQ
+- *
+- * Every interrupt can have up to 32 causes and the interrupt model supports
+- * masking/unmasking each cause independently
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
+-		      u32 cmd_flags,
+-		      u16 token,
+-		      u8 irq_index,
+-		      u32 mask)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_set_irq_mask *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_MASK,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_set_irq_mask *)cmd.params;
+-	cmd_params->mask = cpu_to_le32(mask);
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpbp_get_irq_mask() - Get interrupt mask.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @irq_index:	The interrupt index to configure
+- * @mask:	Returned event mask to trigger interrupt
+- *
+- * Every interrupt can have up to 32 causes and the interrupt model supports
+- * masking/unmasking each cause independently
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
+-		      u32 cmd_flags,
+-		      u16 token,
+-		      u8 irq_index,
+-		      u32 *mask)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_get_irq_mask *cmd_params;
+-	struct dpbp_rsp_get_irq_mask *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_MASK,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_get_irq_mask *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpbp_rsp_get_irq_mask *)cmd.params;
+-	*mask = le32_to_cpu(rsp_params->mask);
+-
+-	return 0;
+-}
+-
+-/**
+- * dpbp_get_irq_status() - Get the current status of any pending interrupts.
+- *
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @irq_index:	The interrupt index to configure
+- * @status:	Returned interrupts status - one bit per cause:
+- *			0 = no interrupt pending
+- *			1 = interrupt pending
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			u8 irq_index,
+-			u32 *status)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_get_irq_status *cmd_params;
+-	struct dpbp_rsp_get_irq_status *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_STATUS,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_get_irq_status *)cmd.params;
+-	cmd_params->status = cpu_to_le32(*status);
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpbp_rsp_get_irq_status *)cmd.params;
+-	*status = le32_to_cpu(rsp_params->status);
+-
+-	return 0;
+-}
+-
+-/**
+- * dpbp_clear_irq_status() - Clear a pending interrupt's status
+- *
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @irq_index:	The interrupt index to configure
+- * @status:	Bits to clear (W1C) - one bit per cause:
+- *					0 = don't change
+- *					1 = clear status bit
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
+-			  u32 cmd_flags,
+-			  u16 token,
+-			  u8 irq_index,
+-			  u32 status)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_clear_irq_status *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLEAR_IRQ_STATUS,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_clear_irq_status *)cmd.params;
+-	cmd_params->status = cpu_to_le32(status);
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpbp_get_attributes - Retrieve DPBP attributes.
+- *
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @attr:	Returned object's attributes
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_get_attributes(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			struct dpbp_attr *attr)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_rsp_get_attributes *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params;
+-	attr->bpid = le16_to_cpu(rsp_params->bpid);
+-	attr->id = le32_to_cpu(rsp_params->id);
+-	attr->version.major = le16_to_cpu(rsp_params->version_major);
+-	attr->version.minor = le16_to_cpu(rsp_params->version_minor);
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(dpbp_get_attributes);
+-
+-/**
+- * dpbp_set_notifications() - Set notifications towards software
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @cfg:	notifications configuration
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_set_notifications(struct fsl_mc_io *mc_io,
+-			   u32 cmd_flags,
+-			   u16 token,
+-			   struct dpbp_notification_cfg	*cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_cmd_set_notifications *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_NOTIFICATIONS,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpbp_cmd_set_notifications *)cmd.params;
+-	cmd_params->depletion_entry = cpu_to_le32(cfg->depletion_entry);
+-	cmd_params->depletion_exit = cpu_to_le32(cfg->depletion_exit);
+-	cmd_params->surplus_entry = cpu_to_le32(cfg->surplus_entry);
+-	cmd_params->surplus_exit = cpu_to_le32(cfg->surplus_exit);
+-	cmd_params->options = cpu_to_le16(cfg->options);
+-	cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
+-	cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpbp_get_notifications() - Get the notifications configuration
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPBP object
+- * @cfg:	notifications configuration
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpbp_get_notifications(struct fsl_mc_io *mc_io,
+-			   u32 cmd_flags,
+-			   u16 token,
+-			   struct dpbp_notification_cfg	*cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpbp_rsp_get_notifications *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_NOTIFICATIONS,
+-					  cmd_flags,
+-					  token);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpbp_rsp_get_notifications *)cmd.params;
+-	cfg->depletion_entry = le32_to_cpu(rsp_params->depletion_entry);
+-	cfg->depletion_exit = le32_to_cpu(rsp_params->depletion_exit);
+-	cfg->surplus_entry = le32_to_cpu(rsp_params->surplus_entry);
+-	cfg->surplus_exit = le32_to_cpu(rsp_params->surplus_exit);
+-	cfg->options = le16_to_cpu(rsp_params->options);
+-	cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
+-	cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
+-
+-	return 0;
+-}
+--- /dev/null
++++ b/drivers/staging/fsl-mc/bus/dpio/Makefile
+@@ -0,0 +1,8 @@
++# SPDX-License-Identifier: GPL-2.0
++#
++# QorIQ DPAA2 DPIO driver
++#
++
++obj-$(CONFIG_FSL_MC_DPIO) += fsl-mc-dpio.o
++
++fsl-mc-dpio-objs := dpio.o qbman-portal.o dpio-service.o dpio-driver.o
+--- /dev/null
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
+@@ -0,0 +1,50 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
++/*
++ * Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ */
++#ifndef _FSL_DPIO_CMD_H
++#define _FSL_DPIO_CMD_H
++
++/* DPIO Version */
++#define DPIO_VER_MAJOR			4
++#define DPIO_VER_MINOR			2
++
++/* Command Versioning */
++
++#define DPIO_CMD_ID_OFFSET		4
++#define DPIO_CMD_BASE_VERSION		1
++
++#define DPIO_CMD(id)	(((id) << DPIO_CMD_ID_OFFSET) | DPIO_CMD_BASE_VERSION)
++
++/* Command IDs */
++#define DPIO_CMDID_CLOSE				DPIO_CMD(0x800)
++#define DPIO_CMDID_OPEN					DPIO_CMD(0x803)
++#define DPIO_CMDID_GET_API_VERSION			DPIO_CMD(0xa03)
++#define DPIO_CMDID_ENABLE				DPIO_CMD(0x002)
++#define DPIO_CMDID_DISABLE				DPIO_CMD(0x003)
++#define DPIO_CMDID_GET_ATTR				DPIO_CMD(0x004)
++#define DPIO_CMDID_RESET				DPIO_CMD(0x005)
++
++struct dpio_cmd_open {
++	__le32 dpio_id;
++};
++
++#define DPIO_CHANNEL_MODE_MASK		0x3
++
++struct dpio_rsp_get_attr {
++	/* cmd word 0 */
++	__le32 id;
++	__le16 qbman_portal_id;
++	u8 num_priorities;
++	u8 channel_mode;
++	/* cmd word 1 */
++	__le64 qbman_portal_ce_addr;
++	/* cmd word 2 */
++	__le64 qbman_portal_ci_addr;
++	/* cmd word 3 */
++	__le32 qbman_version;
++};
++
++#endif /* _FSL_DPIO_CMD_H */
+--- /dev/null
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
+@@ -0,0 +1,278 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/msi.h>
++#include <linux/dma-mapping.h>
++#include <linux/delay.h>
++
++#include <linux/fsl/mc.h>
++#include "../../include/dpaa2-io.h"
++
++#include "qbman-portal.h"
++#include "dpio.h"
++#include "dpio-cmd.h"
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_AUTHOR("Freescale Semiconductor, Inc");
++MODULE_DESCRIPTION("DPIO Driver");
++
++struct dpio_priv {
++	struct dpaa2_io *io;
++};
++
++static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
++{
++	struct device *dev = (struct device *)arg;
++	struct dpio_priv *priv = dev_get_drvdata(dev);
++
++	return dpaa2_io_irq(priv->io);
++}
++
++static void unregister_dpio_irq_handlers(struct fsl_mc_device *dpio_dev)
++{
++	struct fsl_mc_device_irq *irq;
++
++	irq = dpio_dev->irqs[0];
++
++	/* clear the affinity hint */
++	irq_set_affinity_hint(irq->msi_desc->irq, NULL);
++}
++
++static int register_dpio_irq_handlers(struct fsl_mc_device *dpio_dev, int cpu)
++{
++	struct dpio_priv *priv;
++	int error;
++	struct fsl_mc_device_irq *irq;
++	cpumask_t mask;
++
++	priv = dev_get_drvdata(&dpio_dev->dev);
++
++	irq = dpio_dev->irqs[0];
++	error = devm_request_irq(&dpio_dev->dev,
++				 irq->msi_desc->irq,
++				 dpio_irq_handler,
++				 0,
++				 dev_name(&dpio_dev->dev),
++				 &dpio_dev->dev);
++	if (error < 0) {
++		dev_err(&dpio_dev->dev,
++			"devm_request_irq() failed: %d\n",
++			error);
++		return error;
++	}
++
++	/* set the affinity hint */
++	cpumask_clear(&mask);
++	cpumask_set_cpu(cpu, &mask);
++	if (irq_set_affinity_hint(irq->msi_desc->irq, &mask))
++		dev_err(&dpio_dev->dev,
++			"irq_set_affinity failed irq %d cpu %d\n",
++			irq->msi_desc->irq, cpu);
++
++	return 0;
++}
++
++static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
++{
++	struct dpio_attr dpio_attrs;
++	struct dpaa2_io_desc desc;
++	struct dpio_priv *priv;
++	int err = -ENOMEM;
++	struct device *dev = &dpio_dev->dev;
++	static int next_cpu = -1;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		goto err_priv_alloc;
++
++	dev_set_drvdata(dev, priv);
++
++	err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
++	if (err) {
++		dev_dbg(dev, "MC portal allocation failed\n");
++		err = -EPROBE_DEFER;
++		goto err_mcportal;
++	}
++
++	err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
++			&dpio_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpio_open() failed\n");
++		goto err_open;
++	}
++
++	err = dpio_reset(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpio_reset() failed\n");
++		goto err_reset;
++	}
++
++	err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
++				  &dpio_attrs);
++	if (err) {
++		dev_err(dev, "dpio_get_attributes() failed %d\n", err);
++		goto err_get_attr;
++	}
++	desc.qman_version = dpio_attrs.qbman_version;
++
++	err = dpio_enable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpio_enable() failed %d\n", err);
++		goto err_get_attr;
++	}
++
++	/* initialize DPIO descriptor */
++	desc.receives_notifications = dpio_attrs.num_priorities ? 1 : 0;
++	desc.has_8prio = dpio_attrs.num_priorities == 8 ? 1 : 0;
++	desc.dpio_id = dpio_dev->obj_desc.id;
++
++	/* get the cpu to use for the affinity hint */
++	if (next_cpu == -1)
++		next_cpu = cpumask_first(cpu_online_mask);
++	else
++		next_cpu = cpumask_next(next_cpu, cpu_online_mask);
++
++	if (!cpu_possible(next_cpu)) {
++		dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
++		err = -ERANGE;
++		goto err_allocate_irqs;
++	}
++	desc.cpu = next_cpu;
++
++	/*
++	 * Set the CENA regs to be the cache enabled area of the portal to
++	 * achieve the best performance.
++	 */
++	desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start,
++		resource_size(&dpio_dev->regions[0]));
++	desc.regs_cinh = ioremap(dpio_dev->regions[1].start,
++		resource_size(&dpio_dev->regions[1]));
++
++	err = fsl_mc_allocate_irqs(dpio_dev);
++	if (err) {
++		dev_err(dev, "fsl_mc_allocate_irqs failed. err=%d\n", err);
++		goto err_allocate_irqs;
++	}
++
++	err = register_dpio_irq_handlers(dpio_dev, desc.cpu);
++	if (err)
++		goto err_register_dpio_irq;
++
++	priv->io = dpaa2_io_create(&desc);
++	if (!priv->io) {
++		dev_err(dev, "dpaa2_io_create failed\n");
++		goto err_dpaa2_io_create;
++	}
++
++	dev_info(dev, "probed\n");
++	dev_dbg(dev, "   receives_notifications = %d\n",
++		desc.receives_notifications);
++	dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
++	fsl_mc_portal_free(dpio_dev->mc_io);
++
++	return 0;
++
++err_dpaa2_io_create:
++	unregister_dpio_irq_handlers(dpio_dev);
++err_register_dpio_irq:
++	fsl_mc_free_irqs(dpio_dev);
++err_allocate_irqs:
++	dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
++err_get_attr:
++err_reset:
++	dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
++err_open:
++	fsl_mc_portal_free(dpio_dev->mc_io);
++err_mcportal:
++	dev_set_drvdata(dev, NULL);
++err_priv_alloc:
++	return err;
++}
++
++/* Tear down interrupts for a given DPIO object */
++static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev)
++{
++	unregister_dpio_irq_handlers(dpio_dev);
++	fsl_mc_free_irqs(dpio_dev);
++}
++
++static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev)
++{
++	struct device *dev;
++	struct dpio_priv *priv;
++	int err;
++
++	dev = &dpio_dev->dev;
++	priv = dev_get_drvdata(dev);
++
++	dpaa2_io_down(priv->io);
++
++	dpio_teardown_irqs(dpio_dev);
++
++	err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
++	if (err) {
++		dev_err(dev, "MC portal allocation failed\n");
++		goto err_mcportal;
++	}
++
++	err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
++			&dpio_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpio_open() failed\n");
++		goto err_open;
++	}
++
++	dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
++
++	dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
++
++	fsl_mc_portal_free(dpio_dev->mc_io);
++
++	dev_set_drvdata(dev, NULL);
++
++	return 0;
++
++err_open:
++	fsl_mc_portal_free(dpio_dev->mc_io);
++err_mcportal:
++	return err;
++}
++
++static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = {
++	{
++		.vendor = FSL_MC_VENDOR_FREESCALE,
++		.obj_type = "dpio",
++	},
++	{ .vendor = 0x0 }
++};
++
++static struct fsl_mc_driver dpaa2_dpio_driver = {
++	.driver = {
++		.name		= KBUILD_MODNAME,
++		.owner		= THIS_MODULE,
++	},
++	.probe		= dpaa2_dpio_probe,
++	.remove		= dpaa2_dpio_remove,
++	.match_id_table = dpaa2_dpio_match_id_table
++};
++
++static int dpio_driver_init(void)
++{
++	return fsl_mc_driver_register(&dpaa2_dpio_driver);
++}
++
++static void dpio_driver_exit(void)
++{
++	fsl_mc_driver_unregister(&dpaa2_dpio_driver);
++}
++module_init(dpio_driver_init);
++module_exit(dpio_driver_exit);
+--- /dev/null
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
+@@ -0,0 +1,780 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ */
++#include <linux/types.h>
++#include <linux/fsl/mc.h>
++#include "../../include/dpaa2-io.h"
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++
++#include "dpio.h"
++#include "qbman-portal.h"
++
++struct dpaa2_io {
++	struct dpaa2_io_desc dpio_desc;
++	struct qbman_swp_desc swp_desc;
++	struct qbman_swp *swp;
++	struct list_head node;
++	/* protect against multiple management commands */
++	spinlock_t lock_mgmt_cmd;
++	/* protect notifications list */
++	spinlock_t lock_notifications;
++	struct list_head notifications;
++};
++
++struct dpaa2_io_store {
++	unsigned int max;
++	dma_addr_t paddr;
++	struct dpaa2_dq *vaddr;
++	void *alloced_addr;    /* unaligned value from kmalloc() */
++	unsigned int idx;      /* position of the next-to-be-returned entry */
++	struct qbman_swp *swp; /* portal used to issue VDQCR */
++	struct device *dev;    /* device used for DMA mapping */
++};
++
++/* keep a per cpu array of DPIOs for fast access */
++static struct dpaa2_io *dpio_by_cpu[NR_CPUS];
++static struct list_head dpio_list = LIST_HEAD_INIT(dpio_list);
++static DEFINE_SPINLOCK(dpio_list_lock);
++
++static inline struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d,
++						     int cpu)
++{
++	if (d)
++		return d;
++
++	if (cpu != DPAA2_IO_ANY_CPU && cpu >= num_possible_cpus())
++		return NULL;
++
++	/*
++	 * If cpu == -1, choose the current cpu, with no guarantees about
++	 * potentially being migrated away.
++	 */
++	if (cpu < 0)
++		cpu = smp_processor_id();
++
++	/* If a specific cpu was requested, pick it up immediately */
++	return dpio_by_cpu[cpu];
++}
++
++static inline struct dpaa2_io *service_select(struct dpaa2_io *d)
++{
++	if (d)
++		return d;
++
++	d = service_select_by_cpu(d, -1);
++	if (d)
++		return d;
++
++	spin_lock(&dpio_list_lock);
++	d = list_entry(dpio_list.next, struct dpaa2_io, node);
++	list_del(&d->node);
++	list_add_tail(&d->node, &dpio_list);
++	spin_unlock(&dpio_list_lock);
++
++	return d;
++}
++
++/**
++ * dpaa2_io_service_select() - return a dpaa2_io service affined to this cpu
++ * @cpu: the cpu id
++ *
++ * Return the affine dpaa2_io service, or NULL if there is no service affined
++ * to the specified cpu. If DPAA2_IO_ANY_CPU is used, return the next available
++ * service.
++ */
++struct dpaa2_io *dpaa2_io_service_select(int cpu)
++{
++	if (cpu == DPAA2_IO_ANY_CPU)
++		return service_select(NULL);
++
++	return service_select_by_cpu(NULL, cpu);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_select);
++
++/**
++ * dpaa2_io_create() - create a dpaa2_io object.
++ * @desc: the dpaa2_io descriptor
++ *
++ * Activates a "struct dpaa2_io" corresponding to the given config of an actual
++ * DPIO object.
++ *
++ * Return a valid dpaa2_io object for success, or NULL for failure.
++ */
++struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc)
++{
++	struct dpaa2_io *obj = kmalloc(sizeof(*obj), GFP_KERNEL);
++
++	if (!obj)
++		return NULL;
++
++	/* check if CPU is out of range (-1 means any cpu) */
++	if (desc->cpu != DPAA2_IO_ANY_CPU && desc->cpu >= num_possible_cpus()) {
++		kfree(obj);
++		return NULL;
++	}
++
++	obj->dpio_desc = *desc;
++	obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena;
++	obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh;
++	obj->swp_desc.qman_version = obj->dpio_desc.qman_version;
++	obj->swp = qbman_swp_init(&obj->swp_desc);
++
++	if (!obj->swp) {
++		kfree(obj);
++		return NULL;
++	}
++
++	INIT_LIST_HEAD(&obj->node);
++	spin_lock_init(&obj->lock_mgmt_cmd);
++	spin_lock_init(&obj->lock_notifications);
++	INIT_LIST_HEAD(&obj->notifications);
++
++	/* For now only enable DQRR interrupts */
++	qbman_swp_interrupt_set_trigger(obj->swp,
++					QBMAN_SWP_INTERRUPT_DQRI);
++	qbman_swp_interrupt_clear_status(obj->swp, 0xffffffff);
++	if (obj->dpio_desc.receives_notifications)
++		qbman_swp_push_set(obj->swp, 0, 1);
++
++	spin_lock(&dpio_list_lock);
++	list_add_tail(&obj->node, &dpio_list);
++	if (desc->cpu >= 0 && !dpio_by_cpu[desc->cpu])
++		dpio_by_cpu[desc->cpu] = obj;
++	spin_unlock(&dpio_list_lock);
++
++	return obj;
++}
++
++/**
++ * dpaa2_io_down() - release the dpaa2_io object.
++ * @d: the dpaa2_io object to be released.
++ *
++ * The "struct dpaa2_io" type can represent an individual DPIO object (as
++ * described by "struct dpaa2_io_desc") or an instance of a "DPIO service",
++ * which can be used to group/encapsulate multiple DPIO objects. In all cases,
++ * each handle obtained should be released using this function.
++ */
++void dpaa2_io_down(struct dpaa2_io *d)
++{
++	kfree(d);
++}
++
++#define DPAA_POLL_MAX 32
++
++/**
++ * dpaa2_io_irq() - ISR for DPIO interrupts
++ *
++ * @obj: the given DPIO object.
++ *
++ * Return IRQ_HANDLED for success or IRQ_NONE if there
++ * were no pending interrupts.
++ */
++irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj)
++{
++	const struct dpaa2_dq *dq;
++	int max = 0;
++	struct qbman_swp *swp;
++	u32 status;
++
++	swp = obj->swp;
++	status = qbman_swp_interrupt_read_status(swp);
++	if (!status)
++		return IRQ_NONE;
++
++	dq = qbman_swp_dqrr_next(swp);
++	while (dq) {
++		if (qbman_result_is_SCN(dq)) {
++			struct dpaa2_io_notification_ctx *ctx;
++			u64 q64;
++
++			q64 = qbman_result_SCN_ctx(dq);
++			ctx = (void *)(uintptr_t)q64;
++			ctx->cb(ctx);
++		} else {
++			pr_crit("fsl-mc-dpio: Unrecognised/ignored DQRR entry\n");
++		}
++		qbman_swp_dqrr_consume(swp, dq);
++		++max;
++		if (max > DPAA_POLL_MAX)
++			goto done;
++		dq = qbman_swp_dqrr_next(swp);
++	}
++done:
++	qbman_swp_interrupt_clear_status(swp, status);
++	qbman_swp_interrupt_set_inhibit(swp, 0);
++	return IRQ_HANDLED;
++}
++
++/**
++ * dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN
++ *                               notifications on the given DPIO service.
++ * @d:   the given DPIO service.
++ * @ctx: the notification context.
++ *
++ * The caller should make the MC command to attach a DPAA2 object to
++ * a DPIO after this function completes successfully.  In that way:
++ *    (a) The DPIO service is "ready" to handle a notification arrival
++ *        (which might happen before the "attach" command to MC has
++ *        returned control of execution back to the caller)
++ *    (b) The DPIO service can provide back to the caller the 'dpio_id' and
++ *        'qman64' parameters that it should pass along in the MC command
++ *        in order for the object to be configured to produce the right
++ *        notification fields to the DPIO service.
++ *
++ * Return 0 for success, or -ENODEV for failure.
++ */
++int dpaa2_io_service_register(struct dpaa2_io *d,
++			      struct dpaa2_io_notification_ctx *ctx)
++{
++	unsigned long irqflags;
++
++	d = service_select_by_cpu(d, ctx->desired_cpu);
++	if (!d)
++		return -ENODEV;
++
++	ctx->dpio_id = d->dpio_desc.dpio_id;
++	ctx->qman64 = (u64)(uintptr_t)ctx;
++	ctx->dpio_private = d;
++	spin_lock_irqsave(&d->lock_notifications, irqflags);
++	list_add(&ctx->node, &d->notifications);
++	spin_unlock_irqrestore(&d->lock_notifications, irqflags);
++
++	/* Enable the generation of CDAN notifications */
++	if (ctx->is_cdan)
++		return qbman_swp_CDAN_set_context_enable(d->swp,
++							 (u16)ctx->id,
++							 ctx->qman64);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_register);
++
++/**
++ * dpaa2_io_service_deregister - The opposite of 'register'.
++ * @service: the given DPIO service.
++ * @ctx: the notification context.
++ *
++ * This function should be called only after sending the MC command to
++ * to detach the notification-producing device from the DPIO.
++ */
++void dpaa2_io_service_deregister(struct dpaa2_io *service,
++				 struct dpaa2_io_notification_ctx *ctx)
++{
++	struct dpaa2_io *d = ctx->dpio_private;
++	unsigned long irqflags;
++
++	if (ctx->is_cdan)
++		qbman_swp_CDAN_disable(d->swp, (u16)ctx->id);
++
++	spin_lock_irqsave(&d->lock_notifications, irqflags);
++	list_del(&ctx->node);
++	spin_unlock_irqrestore(&d->lock_notifications, irqflags);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_deregister);
++
++/**
++ * dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service.
++ * @d: the given DPIO service.
++ * @ctx: the notification context.
++ *
++ * Once a FQDAN/CDAN has been produced, the corresponding FQ/channel is
++ * considered "disarmed". Ie. the user can issue pull dequeue operations on that
++ * traffic source for as long as it likes. Eventually it may wish to "rearm"
++ * that source to allow it to produce another FQDAN/CDAN, that's what this
++ * function achieves.
++ *
++ * Return 0 for success.
++ */
++int dpaa2_io_service_rearm(struct dpaa2_io *d,
++			   struct dpaa2_io_notification_ctx *ctx)
++{
++	unsigned long irqflags;
++	int err;
++
++	d = service_select_by_cpu(d, ctx->desired_cpu);
++	if (!unlikely(d))
++		return -ENODEV;
++
++	spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
++	if (ctx->is_cdan)
++		err = qbman_swp_CDAN_enable(d->swp, (u16)ctx->id);
++	else
++		err = qbman_swp_fq_schedule(d->swp, ctx->id);
++	spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
++
++	return err;
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_rearm);
++
++/**
++ * dpaa2_io_service_pull_fq() - pull dequeue functions from a fq.
++ * @d: the given DPIO service.
++ * @fqid: the given frame queue id.
++ * @s: the dpaa2_io_store object for the result.
++ *
++ * Return 0 for success, or error code for failure.
++ */
++int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
++			     struct dpaa2_io_store *s)
++{
++	struct qbman_pull_desc pd;
++	int err;
++
++	qbman_pull_desc_clear(&pd);
++	qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
++	qbman_pull_desc_set_numframes(&pd, (u8)s->max);
++	qbman_pull_desc_set_fq(&pd, fqid);
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++	s->swp = d->swp;
++	err = qbman_swp_pull(d->swp, &pd);
++	if (err)
++		s->swp = NULL;
++
++	return err;
++}
++EXPORT_SYMBOL(dpaa2_io_service_pull_fq);
++
++/**
++ * dpaa2_io_service_pull_channel() - pull dequeue functions from a channel.
++ * @d: the given DPIO service.
++ * @channelid: the given channel id.
++ * @s: the dpaa2_io_store object for the result.
++ *
++ * Return 0 for success, or error code for failure.
++ */
++int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
++				  struct dpaa2_io_store *s)
++{
++	struct qbman_pull_desc pd;
++	int err;
++
++	qbman_pull_desc_clear(&pd);
++	qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
++	qbman_pull_desc_set_numframes(&pd, (u8)s->max);
++	qbman_pull_desc_set_channel(&pd, channelid, qbman_pull_type_prio);
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	s->swp = d->swp;
++	err = qbman_swp_pull(d->swp, &pd);
++	if (err)
++		s->swp = NULL;
++
++	return err;
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_pull_channel);
++
++/**
++ * dpaa2_io_service_enqueue_fq() - Enqueue a frame to a frame queue.
++ * @d: the given DPIO service.
++ * @fqid: the given frame queue id.
++ * @fd: the frame descriptor which is enqueued.
++ *
++ * Return 0 for successful enqueue, -EBUSY if the enqueue ring is not ready,
++ * or -ENODEV if there is no dpio service.
++ */
++int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d,
++				u32 fqid,
++				const struct dpaa2_fd *fd)
++{
++	struct qbman_eq_desc ed;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	qbman_eq_desc_clear(&ed);
++	qbman_eq_desc_set_no_orp(&ed, 0);
++	qbman_eq_desc_set_fq(&ed, fqid);
++
++	return qbman_swp_enqueue(d->swp, &ed, fd);
++}
++EXPORT_SYMBOL(dpaa2_io_service_enqueue_fq);
++
++/**
++ * dpaa2_io_service_enqueue_qd() - Enqueue a frame to a QD.
++ * @d: the given DPIO service.
++ * @qdid: the given queuing destination id.
++ * @prio: the given queuing priority.
++ * @qdbin: the given queuing destination bin.
++ * @fd: the frame descriptor which is enqueued.
++ *
++ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
++ * or -ENODEV if there is no dpio service.
++ */
++int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d,
++				u32 qdid, u8 prio, u16 qdbin,
++				const struct dpaa2_fd *fd)
++{
++	struct qbman_eq_desc ed;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	qbman_eq_desc_clear(&ed);
++	qbman_eq_desc_set_no_orp(&ed, 0);
++	qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
++
++	return qbman_swp_enqueue(d->swp, &ed, fd);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_enqueue_qd);
++
++/**
++ * dpaa2_io_service_release() - Release buffers to a buffer pool.
++ * @d: the given DPIO object.
++ * @bpid: the buffer pool id.
++ * @buffers: the buffers to be released.
++ * @num_buffers: the number of the buffers to be released.
++ *
++ * Return 0 for success, and negative error code for failure.
++ */
++int dpaa2_io_service_release(struct dpaa2_io *d,
++			     u32 bpid,
++			     const u64 *buffers,
++			     unsigned int num_buffers)
++{
++	struct qbman_release_desc rd;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	qbman_release_desc_clear(&rd);
++	qbman_release_desc_set_bpid(&rd, bpid);
++
++	return qbman_swp_release(d->swp, &rd, buffers, num_buffers);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_release);
++
++/**
++ * dpaa2_io_service_acquire() - Acquire buffers from a buffer pool.
++ * @d: the given DPIO object.
++ * @bpid: the buffer pool id.
++ * @buffers: the buffer addresses for acquired buffers.
++ * @num_buffers: the expected number of the buffers to acquire.
++ *
++ * Return a negative error code if the command failed, otherwise it returns
++ * the number of buffers acquired, which may be less than the number requested.
++ * Eg. if the buffer pool is empty, this will return zero.
++ */
++int dpaa2_io_service_acquire(struct dpaa2_io *d,
++			     u32 bpid,
++			     u64 *buffers,
++			     unsigned int num_buffers)
++{
++	unsigned long irqflags;
++	int err;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
++	err = qbman_swp_acquire(d->swp, bpid, buffers, num_buffers);
++	spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
++
++	return err;
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_acquire);
++
++/*
++ * 'Stores' are reusable memory blocks for holding dequeue results, and to
++ * assist with parsing those results.
++ */
++
++/**
++ * dpaa2_io_store_create() - Create the dma memory storage for dequeue result.
++ * @max_frames: the maximum number of dequeued result for frames, must be <= 16.
++ * @dev:        the device to allow mapping/unmapping the DMAable region.
++ *
++ * The size of the storage is "max_frames*sizeof(struct dpaa2_dq)".
++ * The 'dpaa2_io_store' returned is a DPIO service managed object.
++ *
++ * Return pointer to dpaa2_io_store struct for successfuly created storage
++ * memory, or NULL on error.
++ */
++struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
++					     struct device *dev)
++{
++	struct dpaa2_io_store *ret;
++	size_t size;
++
++	if (!max_frames || (max_frames > 16))
++		return NULL;
++
++	ret = kmalloc(sizeof(*ret), GFP_KERNEL);
++	if (!ret)
++		return NULL;
++
++	ret->max = max_frames;
++	size = max_frames * sizeof(struct dpaa2_dq) + 64;
++	ret->alloced_addr = kzalloc(size, GFP_KERNEL);
++	if (!ret->alloced_addr) {
++		kfree(ret);
++		return NULL;
++	}
++
++	ret->vaddr = PTR_ALIGN(ret->alloced_addr, 64);
++	ret->paddr = dma_map_single(dev, ret->vaddr,
++				    sizeof(struct dpaa2_dq) * max_frames,
++				    DMA_FROM_DEVICE);
++	if (dma_mapping_error(dev, ret->paddr)) {
++		kfree(ret->alloced_addr);
++		kfree(ret);
++		return NULL;
++	}
++
++	ret->idx = 0;
++	ret->dev = dev;
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_store_create);
++
++/**
++ * dpaa2_io_store_destroy() - Frees the dma memory storage for dequeue
++ *                            result.
++ * @s: the storage memory to be destroyed.
++ */
++void dpaa2_io_store_destroy(struct dpaa2_io_store *s)
++{
++	dma_unmap_single(s->dev, s->paddr, sizeof(struct dpaa2_dq) * s->max,
++			 DMA_FROM_DEVICE);
++	kfree(s->alloced_addr);
++	kfree(s);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_store_destroy);
++
++/**
++ * dpaa2_io_store_next() - Determine when the next dequeue result is available.
++ * @s: the dpaa2_io_store object.
++ * @is_last: indicate whether this is the last frame in the pull command.
++ *
++ * When an object driver performs dequeues to a dpaa2_io_store, this function
++ * can be used to determine when the next frame result is available. Once
++ * this function returns non-NULL, a subsequent call to it will try to find
++ * the next dequeue result.
++ *
++ * Note that if a pull-dequeue has a NULL result because the target FQ/channel
++ * was empty, then this function will also return NULL (rather than expecting
++ * the caller to always check for this. As such, "is_last" can be used to
++ * differentiate between "end-of-empty-dequeue" and "still-waiting".
++ *
++ * Return dequeue result for a valid dequeue result, or NULL for empty dequeue.
++ */
++struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last)
++{
++	int match;
++	struct dpaa2_dq *ret = &s->vaddr[s->idx];
++
++	match = qbman_result_has_new_result(s->swp, ret);
++	if (!match) {
++		*is_last = 0;
++		return NULL;
++	}
++
++	s->idx++;
++
++	if (dpaa2_dq_is_pull_complete(ret)) {
++		*is_last = 1;
++		s->idx = 0;
++		/*
++		 * If we get an empty dequeue result to terminate a zero-results
++		 * vdqcr, return NULL to the caller rather than expecting him to
++		 * check non-NULL results every time.
++		 */
++		if (!(dpaa2_dq_flags(ret) & DPAA2_DQ_STAT_VALIDFRAME))
++			ret = NULL;
++	} else {
++		*is_last = 0;
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_store_next);
++
++/**
++ * dpaa2_io_query_fq_count() - Get the frame and byte count for a given fq.
++ * @d: the given DPIO object.
++ * @fqid: the id of frame queue to be queried.
++ * @fcnt: the queried frame count.
++ * @bcnt: the queried byte count.
++ *
++ * Knowing the FQ count at run-time can be useful in debugging situations.
++ * The instantaneous frame- and byte-count are hereby returned.
++ *
++ * Return 0 for a successful query, and negative error code if query fails.
++ */
++int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid,
++			    u32 *fcnt, u32 *bcnt)
++{
++	struct qbman_fq_query_np_rslt state;
++	struct qbman_swp *swp;
++	unsigned long irqflags;
++	int ret;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	swp = d->swp;
++	spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
++	ret = qbman_fq_query_state(swp, fqid, &state);
++	spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
++	if (ret)
++		return ret;
++	*fcnt = qbman_fq_state_frame_count(&state);
++	*bcnt = qbman_fq_state_byte_count(&state);
++
++	return 0;
++}
++EXPORT_SYMBOL(dpaa2_io_query_fq_count);
++
++/**
++ * dpaa2_io_query_bp_count() - Query the number of buffers currently in a
++ * buffer pool.
++ * @d: the given DPIO object.
++ * @bpid: the index of buffer pool to be queried.
++ * @num: the queried number of buffers in the buffer pool.
++ *
++ * Return 0 for a successful query, and negative error code if query fails.
++ */
++int dpaa2_io_query_bp_count(struct dpaa2_io *d, u32 bpid, u32 *num)
++{
++	struct qbman_bp_query_rslt state;
++	struct qbman_swp *swp;
++	unsigned long irqflags;
++	int ret;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++
++	swp = d->swp;
++	spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
++	ret = qbman_bp_query(swp, bpid, &state);
++	spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
++	if (ret)
++		return ret;
++	*num = qbman_bp_info_num_free_bufs(&state);
++	return 0;
++}
++EXPORT_SYMBOL(dpaa2_io_query_bp_count);
++
++/**
++ * dpaa2_io_service_enqueue_orp_fq() - Enqueue a frame to a frame queue with
++ * order restoration
++ * @d: the given DPIO service.
++ * @fqid: the given frame queue id.
++ * @fd: the frame descriptor which is enqueued.
++ * @orpid: the order restoration point ID
++ * @seqnum: the order sequence number
++ * @last: must be set for the final frame if seqnum is shared (spilt frame)
++ *
++ * Performs an enqueue to a frame queue using the specified order restoration
++ * point. The QMan device will ensure the order of frames placed on the
++ * queue will be ordered as per the sequence number.
++ *
++ * In the case a frame is split it is possible to enqueue using the same
++ * sequence number more than once. The final frame in a shared sequence number
++ * most be indicated by setting last = 1. For non shared sequence numbers
++ * last = 1 must always be set.
++ *
++ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
++ * or -ENODEV if there is no dpio service.
++ */
++int dpaa2_io_service_enqueue_orp_fq(struct dpaa2_io *d, u32 fqid,
++				    const struct dpaa2_fd *fd, u16 orpid,
++				    u16 seqnum, int last)
++{
++	struct qbman_eq_desc ed;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++	qbman_eq_desc_clear(&ed);
++	qbman_eq_desc_set_orp(&ed, 0, orpid, seqnum, !last);
++	qbman_eq_desc_set_fq(&ed, fqid);
++	return qbman_swp_enqueue(d->swp, &ed, fd);
++}
++EXPORT_SYMBOL(dpaa2_io_service_enqueue_orp_fq);
++
++/**
++ * dpaa2_io_service_enqueue_orp_qd() - Enqueue a frame to a queueing destination
++ * with order restoration
++ * @d: the given DPIO service.
++ * @qdid: the given queuing destination id.
++ * @fd: the frame descriptor which is enqueued.
++ * @orpid: the order restoration point ID
++ * @seqnum: the order sequence number
++ * @last: must be set for the final frame if seqnum is shared (spilt frame)
++ *
++ * Performs an enqueue to a frame queue using the specified order restoration
++ * point. The QMan device will ensure the order of frames placed on the
++ * queue will be ordered as per the sequence number.
++ *
++ * In the case a frame is split it is possible to enqueue using the same
++ * sequence number more than once. The final frame in a shared sequence number
++ * most be indicated by setting last = 1. For non shared sequence numbers
++ * last = 1 must always be set.
++ *
++ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
++ * or -ENODEV if there is no dpio service.
++ */
++int dpaa2_io_service_enqueue_orp_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
++				    u16 qdbin, const struct dpaa2_fd *fd,
++				    u16 orpid, u16 seqnum, int last)
++{
++	struct qbman_eq_desc ed;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++	qbman_eq_desc_clear(&ed);
++	qbman_eq_desc_set_orp(&ed, 0, orpid, seqnum, !last);
++	qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
++	return qbman_swp_enqueue(d->swp, &ed, fd);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_enqueue_orp_qd);
++
++/**
++ * dpaa2_io_service_orp_seqnum_drop() - Remove a sequence number from
++ * an order restoration list
++ * @d: the given DPIO service.
++ * @orpid: Order restoration point to remove a sequence number from
++ * @seqnum: Sequence number to remove
++ *
++ * Removes a frames sequence number from an order restoration point without
++ * enqueing the frame. Used to indicate that the order restoration hardware
++ * should not expect to see this sequence number. Typically used to indicate
++ * a frame was terminated or dropped from a flow.
++ *
++ * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
++ * or -ENODEV if there is no dpio service.
++ */
++int dpaa2_io_service_orp_seqnum_drop(struct dpaa2_io *d, u16 orpid, u16 seqnum)
++{
++	struct qbman_eq_desc ed;
++	struct dpaa2_fd fd;
++
++	d = service_select(d);
++	if (!d)
++		return -ENODEV;
++	qbman_eq_desc_clear(&ed);
++	qbman_eq_desc_set_orp_hole(&ed, orpid, seqnum);
++	return qbman_swp_enqueue(d->swp, &ed, &fd);
++}
++EXPORT_SYMBOL_GPL(dpaa2_io_service_orp_seqnum_drop);
+--- /dev/null
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c
+@@ -0,0 +1,221 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/fsl/mc.h>
++
++#include "dpio.h"
++#include "dpio-cmd.h"
++
++/*
++ * Data Path I/O Portal API
++ * Contains initialization APIs and runtime control APIs for DPIO
++ */
++
++/**
++ * dpio_open() - Open a control session for the specified object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @dpio_id:	DPIO unique ID
++ * @token:	Returned token; use in subsequent API calls
++ *
++ * This function can be used to open a control session for an
++ * already created object; an object may have been declared in
++ * the DPL or by calling the dpio_create() function.
++ * This function returns a unique authentication token,
++ * associated with the specific object ID and the specific MC
++ * portal; this token must be used in all subsequent commands for
++ * this specific object.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpio_open(struct fsl_mc_io *mc_io,
++	      u32 cmd_flags,
++	      int dpio_id,
++	      u16 *token)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpio_cmd_open *dpio_cmd;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
++					  cmd_flags,
++					  0);
++	dpio_cmd = (struct dpio_cmd_open *)cmd.params;
++	dpio_cmd->dpio_id = cpu_to_le32(dpio_id);
++
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*token = mc_cmd_hdr_read_token(&cmd);
++
++	return 0;
++}
++
++/**
++ * dpio_close() - Close the control session of the object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPIO object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpio_close(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
++					  cmd_flags,
++					  token);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpio_enable() - Enable the DPIO, allow I/O portal operations.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPIO object
++ *
++ * Return:	'0' on Success; Error code otherwise
++ */
++int dpio_enable(struct fsl_mc_io *mc_io,
++		u32 cmd_flags,
++		u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
++					  cmd_flags,
++					  token);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPIO object
++ *
++ * Return:	'0' on Success; Error code otherwise
++ */
++int dpio_disable(struct fsl_mc_io *mc_io,
++		 u32 cmd_flags,
++		 u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
++					  cmd_flags,
++					  token);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpio_get_attributes() - Retrieve DPIO attributes
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPIO object
++ * @attr:	Returned object's attributes
++ *
++ * Return:	'0' on Success; Error code otherwise
++ */
++int dpio_get_attributes(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			struct dpio_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpio_rsp_get_attr *dpio_rsp;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
++					  cmd_flags,
++					  token);
++
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	dpio_rsp = (struct dpio_rsp_get_attr *)cmd.params;
++	attr->id = le32_to_cpu(dpio_rsp->id);
++	attr->qbman_portal_id = le16_to_cpu(dpio_rsp->qbman_portal_id);
++	attr->num_priorities = dpio_rsp->num_priorities;
++	attr->channel_mode = dpio_rsp->channel_mode & DPIO_CHANNEL_MODE_MASK;
++	attr->qbman_portal_ce_offset =
++		le64_to_cpu(dpio_rsp->qbman_portal_ce_addr);
++	attr->qbman_portal_ci_offset =
++		le64_to_cpu(dpio_rsp->qbman_portal_ci_addr);
++	attr->qbman_version = le32_to_cpu(dpio_rsp->qbman_version);
++
++	return 0;
++}
++
++/**
++ * dpio_get_api_version - Get Data Path I/O API version
++ * @mc_io:	Pointer to MC portal's DPIO object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @major_ver:	Major version of DPIO API
++ * @minor_ver:	Minor version of DPIO API
++ *
++ * Return:	'0' on Success; Error code otherwise
++ */
++int dpio_get_api_version(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 *major_ver,
++			 u16 *minor_ver)
++{
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
++					  cmd_flags, 0);
++
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
++
++	return 0;
++}
++
++/**
++ * dpio_reset() - Reset the DPIO, returns the object to initial state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPIO object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpio_reset(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
+--- /dev/null
++++ b/drivers/staging/fsl-mc/bus/dpio/dpio.h
+@@ -0,0 +1,87 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
++/*
++ * Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ */
++#ifndef __FSL_DPIO_H
++#define __FSL_DPIO_H
++
++struct fsl_mc_io;
++
++int dpio_open(struct fsl_mc_io	*mc_io,
++	      u32		cmd_flags,
++	      int		dpio_id,
++	      u16		*token);
++
++int dpio_close(struct fsl_mc_io	*mc_io,
++	       u32		cmd_flags,
++	       u16		token);
++
++/**
++ * enum dpio_channel_mode - DPIO notification channel mode
++ * @DPIO_NO_CHANNEL: No support for notification channel
++ * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
++ *	dedicated channel in the DPIO; user should point the queue's
++ *	destination in the relevant interface to this DPIO
++ */
++enum dpio_channel_mode {
++	DPIO_NO_CHANNEL = 0,
++	DPIO_LOCAL_CHANNEL = 1,
++};
++
++/**
++ * struct dpio_cfg - Structure representing DPIO configuration
++ * @channel_mode: Notification channel mode
++ * @num_priorities: Number of priorities for the notification channel (1-8);
++ *			relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
++ */
++struct dpio_cfg {
++	enum dpio_channel_mode	channel_mode;
++	u8		num_priorities;
++};
++
++int dpio_enable(struct fsl_mc_io	*mc_io,
++		u32		cmd_flags,
++		u16		token);
++
++int dpio_disable(struct fsl_mc_io	*mc_io,
++		 u32		cmd_flags,
++		 u16		token);
++
++/**
++ * struct dpio_attr - Structure representing DPIO attributes
++ * @id: DPIO object ID
++ * @qbman_portal_ce_offset: offset of the software portal cache-enabled area
++ * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
++ * @qbman_portal_id: Software portal ID
++ * @channel_mode: Notification channel mode
++ * @num_priorities: Number of priorities for the notification channel (1-8);
++ *			relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
++ * @qbman_version: QBMAN version
++ */
++struct dpio_attr {
++	int			id;
++	u64		qbman_portal_ce_offset;
++	u64		qbman_portal_ci_offset;
++	u16		qbman_portal_id;
++	enum dpio_channel_mode	channel_mode;
++	u8			num_priorities;
++	u32		qbman_version;
++};
++
++int dpio_get_attributes(struct fsl_mc_io	*mc_io,
++			u32		cmd_flags,
++			u16		token,
++			struct dpio_attr	*attr);
++
++int dpio_get_api_version(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 *major_ver,
++			 u16 *minor_ver);
++
++int dpio_reset(struct fsl_mc_io	*mc_io,
++	       u32 cmd_flags,
++	       u16 token);
++
++#endif /* __FSL_DPIO_H */
+--- /dev/null
++++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
+@@ -0,0 +1,1164 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
++ * Copyright 2016 NXP
++ *
++ */
++
++#include <asm/cacheflush.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include "../../include/dpaa2-global.h"
++
++#include "qbman-portal.h"
++
++#define QMAN_REV_4000   0x04000000
++#define QMAN_REV_4100   0x04010000
++#define QMAN_REV_4101   0x04010001
++#define QMAN_REV_MASK   0xffff0000
++
++/* All QBMan command and result structures use this "valid bit" encoding */
++#define QB_VALID_BIT ((u32)0x80)
++
++/* QBMan portal management command codes */
++#define QBMAN_MC_ACQUIRE       0x30
++#define QBMAN_WQCHAN_CONFIGURE 0x46
++
++/* CINH register offsets */
++#define QBMAN_CINH_SWP_EQAR    0x8c0
++#define QBMAN_CINH_SWP_DQPI    0xa00
++#define QBMAN_CINH_SWP_DCAP    0xac0
++#define QBMAN_CINH_SWP_SDQCR   0xb00
++#define QBMAN_CINH_SWP_RAR     0xcc0
++#define QBMAN_CINH_SWP_ISR     0xe00
++#define QBMAN_CINH_SWP_IER     0xe40
++#define QBMAN_CINH_SWP_ISDR    0xe80
++#define QBMAN_CINH_SWP_IIR     0xec0
++
++/* CENA register offsets */
++#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((u32)(n) << 6))
++#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((u32)(n) << 6))
++#define QBMAN_CENA_SWP_RCR(n)  (0x400 + ((u32)(n) << 6))
++#define QBMAN_CENA_SWP_CR      0x600
++#define QBMAN_CENA_SWP_RR(vb)  (0x700 + ((u32)(vb) >> 1))
++#define QBMAN_CENA_SWP_VDQCR   0x780
++
++/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
++#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)(p) & 0x1ff) >> 6)
++
++/* Define token used to determine if response written to memory is valid */
++#define QMAN_DQ_TOKEN_VALID 1
++
++/* SDQCR attribute codes */
++#define QB_SDQCR_FC_SHIFT   29
++#define QB_SDQCR_FC_MASK    0x1
++#define QB_SDQCR_DCT_SHIFT  24
++#define QB_SDQCR_DCT_MASK   0x3
++#define QB_SDQCR_TOK_SHIFT  16
++#define QB_SDQCR_TOK_MASK   0xff
++#define QB_SDQCR_SRC_SHIFT  0
++#define QB_SDQCR_SRC_MASK   0xffff
++
++/* opaque token for static dequeues */
++#define QMAN_SDQCR_TOKEN    0xbb
++
++enum qbman_sdqcr_dct {
++	qbman_sdqcr_dct_null = 0,
++	qbman_sdqcr_dct_prio_ics,
++	qbman_sdqcr_dct_active_ics,
++	qbman_sdqcr_dct_active
++};
++
++enum qbman_sdqcr_fc {
++	qbman_sdqcr_fc_one = 0,
++	qbman_sdqcr_fc_up_to_3 = 1
++};
++
++#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
++#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
++static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
++{
++	dcivac(p->addr_cena + offset);
++	prefetch(p->addr_cena + offset);
++}
++
++/* Portal Access */
++
++static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
++{
++	return readl_relaxed(p->addr_cinh + offset);
++}
++
++static inline void qbman_write_register(struct qbman_swp *p, u32 offset,
++					u32 value)
++{
++	writel_relaxed(value, p->addr_cinh + offset);
++}
++
++static inline void *qbman_get_cmd(struct qbman_swp *p, u32 offset)
++{
++	return p->addr_cena + offset;
++}
++
++#define QBMAN_CINH_SWP_CFG   0xd00
++
++#define SWP_CFG_DQRR_MF_SHIFT 20
++#define SWP_CFG_EST_SHIFT     16
++#define SWP_CFG_WN_SHIFT      14
++#define SWP_CFG_RPM_SHIFT     12
++#define SWP_CFG_DCM_SHIFT     10
++#define SWP_CFG_EPM_SHIFT     8
++#define SWP_CFG_SD_SHIFT      5
++#define SWP_CFG_SP_SHIFT      4
++#define SWP_CFG_SE_SHIFT      3
++#define SWP_CFG_DP_SHIFT      2
++#define SWP_CFG_DE_SHIFT      1
++#define SWP_CFG_EP_SHIFT      0
++
++static inline u32 qbman_set_swp_cfg(u8 max_fill, u8 wn,	u8 est, u8 rpm, u8 dcm,
++				    u8 epm, int sd, int sp, int se,
++				    int dp, int de, int ep)
++{
++	return (max_fill << SWP_CFG_DQRR_MF_SHIFT |
++		est << SWP_CFG_EST_SHIFT |
++		wn << SWP_CFG_WN_SHIFT |
++		rpm << SWP_CFG_RPM_SHIFT |
++		dcm << SWP_CFG_DCM_SHIFT |
++		epm << SWP_CFG_EPM_SHIFT |
++		sd << SWP_CFG_SD_SHIFT |
++		sp << SWP_CFG_SP_SHIFT |
++		se << SWP_CFG_SE_SHIFT |
++		dp << SWP_CFG_DP_SHIFT |
++		de << SWP_CFG_DE_SHIFT |
++		ep << SWP_CFG_EP_SHIFT);
++}
++
++/**
++ * qbman_swp_init() - Create a functional object representing the given
++ *                    QBMan portal descriptor.
++ * @d: the given qbman swp descriptor
++ *
++ * Return qbman_swp portal for success, NULL if the object cannot
++ * be created.
++ */
++struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
++{
++	struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
++	u32 reg;
++
++	if (!p)
++		return NULL;
++	p->desc = d;
++	p->mc.valid_bit = QB_VALID_BIT;
++	p->sdq = 0;
++	p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
++	p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
++	p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
++
++	atomic_set(&p->vdq.available, 1);
++	p->vdq.valid_bit = QB_VALID_BIT;
++	p->dqrr.next_idx = 0;
++	p->dqrr.valid_bit = QB_VALID_BIT;
++
++	if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_4100) {
++		p->dqrr.dqrr_size = 4;
++		p->dqrr.reset_bug = 1;
++	} else {
++		p->dqrr.dqrr_size = 8;
++		p->dqrr.reset_bug = 0;
++	}
++
++	p->addr_cena = d->cena_bar;
++	p->addr_cinh = d->cinh_bar;
++
++	reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
++				0, /* Writes cacheable */
++				0, /* EQCR_CI stashing threshold */
++				3, /* RPM: Valid bit mode, RCR in array mode */
++				2, /* DCM: Discrete consumption ack mode */
++				3, /* EPM: Valid bit mode, EQCR in array mode */
++				0, /* mem stashing drop enable == FALSE */
++				1, /* mem stashing priority == TRUE */
++				0, /* mem stashing enable == FALSE */
++				1, /* dequeue stashing priority == TRUE */
++				0, /* dequeue stashing enable == FALSE */
++				0); /* EQCR_CI stashing priority == FALSE */
++
++	qbman_write_register(p, QBMAN_CINH_SWP_CFG, reg);
++	reg = qbman_read_register(p, QBMAN_CINH_SWP_CFG);
++	if (!reg) {
++		pr_err("qbman: the portal is not enabled!\n");
++		return NULL;
++	}
++
++	/*
++	 * SDQCR needs to be initialized to 0 when no channels are
++	 * being dequeued from or else the QMan HW will indicate an
++	 * error.  The values that were calculated above will be
++	 * applied when dequeues from a specific channel are enabled.
++	 */
++	qbman_write_register(p, QBMAN_CINH_SWP_SDQCR, 0);
++	return p;
++}
++
++/**
++ * qbman_swp_finish() - Create and destroy a functional object representing
++ *                      the given QBMan portal descriptor.
++ * @p: the qbman_swp object to be destroyed
++ */
++void qbman_swp_finish(struct qbman_swp *p)
++{
++	kfree(p);
++}
++
++/**
++ * qbman_swp_interrupt_read_status()
++ * @p: the given software portal
++ *
++ * Return the value in the SWP_ISR register.
++ */
++u32 qbman_swp_interrupt_read_status(struct qbman_swp *p)
++{
++	return qbman_read_register(p, QBMAN_CINH_SWP_ISR);
++}
++
++/**
++ * qbman_swp_interrupt_clear_status()
++ * @p: the given software portal
++ * @mask: The mask to clear in SWP_ISR register
++ */
++void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask)
++{
++	qbman_write_register(p, QBMAN_CINH_SWP_ISR, mask);
++}
++
++/**
++ * qbman_swp_interrupt_get_trigger() - read interrupt enable register
++ * @p: the given software portal
++ *
++ * Return the value in the SWP_IER register.
++ */
++u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
++{
++	return qbman_read_register(p, QBMAN_CINH_SWP_IER);
++}
++
++/**
++ * qbman_swp_interrupt_set_trigger() - enable interrupts for a swp
++ * @p: the given software portal
++ * @mask: The mask of bits to enable in SWP_IER
++ */
++void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask)
++{
++	qbman_write_register(p, QBMAN_CINH_SWP_IER, mask);
++}
++
++/**
++ * qbman_swp_interrupt_get_inhibit() - read interrupt mask register
++ * @p: the given software portal object
++ *
++ * Return the value in the SWP_IIR register.
++ */
++int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
++{
++	return qbman_read_register(p, QBMAN_CINH_SWP_IIR);
++}
++
++/**
++ * qbman_swp_interrupt_set_inhibit() - write interrupt mask register
++ * @p: the given software portal object
++ * @mask: The mask to set in SWP_IIR register
++ */
++void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
++{
++	qbman_write_register(p, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
++}
++
++/*
++ * Different management commands all use this common base layer of code to issue
++ * commands and poll for results.
++ */
++
++/*
++ * Returns a pointer to where the caller should fill in their management command
++ * (caller should ignore the verb byte)
++ */
++void *qbman_swp_mc_start(struct qbman_swp *p)
++{
++	return qbman_get_cmd(p, QBMAN_CENA_SWP_CR);
++}
++
++/*
++ * Commits merges in the caller-supplied command verb (which should not include
++ * the valid-bit) and submits the command to hardware
++ */
++void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb)
++{
++	u8 *v = cmd;
++
++	dma_wmb();
++	*v = cmd_verb | p->mc.valid_bit;
++	dccvac(cmd);
++}
++
++/*
++ * Checks for a completed response (returns non-NULL if only if the response
++ * is complete).
++ */
++void *qbman_swp_mc_result(struct qbman_swp *p)
++{
++	u32 *ret, verb;
++
++	qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
++	ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
++
++	/* Remove the valid-bit - command completed if the rest is non-zero */
++	verb = ret[0] & ~QB_VALID_BIT;
++	if (!verb)
++		return NULL;
++	p->mc.valid_bit ^= QB_VALID_BIT;
++	return ret;
++}
++
++#define QB_ENQUEUE_CMD_OPTIONS_SHIFT    0
++enum qb_enqueue_commands {
++	enqueue_empty = 0,
++	enqueue_response_always = 1,
++	enqueue_rejects_to_fq = 2
++};
++
++#define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT      2
++#define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
++#define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT     4
++
++/**
++ * qbman_eq_desc_clear() - Clear the contents of a descriptor to
++ *                         default/starting state.
++ */
++void qbman_eq_desc_clear(struct qbman_eq_desc *d)
++{
++	memset(d, 0, sizeof(*d));
++}
++
++/**
++ * qbman_eq_desc_set_no_orp() - Set enqueue descriptor without orp
++ * @d:                the enqueue descriptor.
++ * @response_success: 1 = enqueue with response always; 0 = enqueue with
++ *                    rejections returned on a FQ.
++ */
++void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
++{
++	d->verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
++	if (respond_success)
++		d->verb |= enqueue_response_always;
++	else
++		d->verb |= enqueue_rejects_to_fq;
++}
++
++/**
++ * qbman_eq_desc_set_orp() - Set order-restoration in the enqueue descriptor
++ * @d: the enqueue descriptor.
++ * @response_success: 1 = enqueue with response always; 0 = enqueue with
++ * rejections returned on a FQ.
++ * @oprid: the order point record id.
++ * @seqnum: the order restoration sequence number.
++ * @incomplete: indicates whether this is the last fragments using the same
++ * sequence number.
++ */
++void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
++			   u16 oprid, u16 seqnum, int incomplete)
++{
++	d->verb |= (1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
++	if (respond_success)
++		d->verb |= enqueue_response_always;
++	else
++		d->verb |= enqueue_rejects_to_fq;
++	d->orpid = cpu_to_le16(oprid);
++	d->seqnum = cpu_to_le16((!!incomplete << 14) | seqnum);
++}
++
++/**
++ * qbman_eq_desc_set_orp_hole() - fill a hole in the order-restoration sequence
++ * without any enqueue
++ * @d: the enqueue descriptor.
++ * @oprid: the order point record id.
++ * @seqnum: the order restoration sequence number.
++ */
++void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, u16 oprid,
++				u16 seqnum)
++{
++	d->verb |= (1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT) | enqueue_empty;
++	d->orpid = cpu_to_le16(oprid);
++	d->seqnum = cpu_to_le16(seqnum);
++}
++
++/*
++ * Exactly one of the following descriptor "targets" should be set. (Calling any
++ * one of these will replace the effect of any prior call to one of these.)
++ *   -enqueue to a frame queue
++ *   -enqueue to a queuing destination
++ */
++
++/**
++ * qbman_eq_desc_set_fq() - set the FQ for the enqueue command
++ * @d:    the enqueue descriptor
++ * @fqid: the id of the frame queue to be enqueued
++ */
++void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid)
++{
++	d->verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
++	d->tgtid = cpu_to_le32(fqid);
++}
++
++/**
++ * qbman_eq_desc_set_qd() - Set Queuing Destination for the enqueue command
++ * @d:       the enqueue descriptor
++ * @qdid:    the id of the queuing destination to be enqueued
++ * @qd_bin:  the queuing destination bin
++ * @qd_prio: the queuing destination priority
++ */
++void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
++			  u32 qd_bin, u32 qd_prio)
++{
++	d->verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
++	d->tgtid = cpu_to_le32(qdid);
++	d->qdbin = cpu_to_le16(qd_bin);
++	d->qpri = qd_prio;
++}
++
++#define EQAR_IDX(eqar)     ((eqar) & 0x7)
++#define EQAR_VB(eqar)      ((eqar) & 0x80)
++#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
++
++/**
++ * qbman_swp_enqueue() - Issue an enqueue command
++ * @s:  the software portal used for enqueue
++ * @d:  the enqueue descriptor
++ * @fd: the frame descriptor to be enqueued
++ *
++ * Please note that 'fd' should only be NULL if the "action" of the
++ * descriptor is "orp_hole" or "orp_nesn".
++ *
++ * Return 0 for successful enqueue, -EBUSY if the EQCR is not ready.
++ */
++int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
++		      const struct dpaa2_fd *fd)
++{
++	struct qbman_eq_desc *p;
++	u32 eqar = qbman_read_register(s, QBMAN_CINH_SWP_EQAR);
++
++	if (!EQAR_SUCCESS(eqar))
++		return -EBUSY;
++
++	p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
++	/* This is mapped as DEVICE type memory, writes are
++	 * with address alignment:
++	 * desc.dca address alignment = 1
++	 * desc.seqnum address alignment = 2
++	 * desc.orpid address alignment = 4
++	 * desc.tgtid address alignment = 8
++	 */
++	p->dca = d->dca;
++	p->seqnum = d->seqnum;
++	p->orpid = d->orpid;
++	memcpy(&p->tgtid, &d->tgtid, 24);
++	memcpy(&p->fd, fd, sizeof(*fd));
++
++	/* Set the verb byte, have to substitute in the valid-bit */
++	dma_wmb();
++	p->verb = d->verb | EQAR_VB(eqar);
++	dccvac(p);
++
++	return 0;
++}
++
++/* Static (push) dequeue */
++
++/**
++ * qbman_swp_push_get() - Get the push dequeue setup
++ * @p:           the software portal object
++ * @channel_idx: the channel index to query
++ * @enabled:     returned boolean to show whether the push dequeue is enabled
++ *               for the given channel
++ */
++void qbman_swp_push_get(struct qbman_swp *s, u8 channel_idx, int *enabled)
++{
++	u16 src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
++
++	WARN_ON(channel_idx > 15);
++	*enabled = src | (1 << channel_idx);
++}
++
++/**
++ * qbman_swp_push_set() - Enable or disable push dequeue
++ * @p:           the software portal object
++ * @channel_idx: the channel index (0 to 15)
++ * @enable:      enable or disable push dequeue
++ */
++void qbman_swp_push_set(struct qbman_swp *s, u8 channel_idx, int enable)
++{
++	u16 dqsrc;
++
++	WARN_ON(channel_idx > 15);
++	if (enable)
++		s->sdq |= 1 << channel_idx;
++	else
++		s->sdq &= ~(1 << channel_idx);
++
++	/* Read make the complete src map.  If no channels are enabled
++	 * the SDQCR must be 0 or else QMan will assert errors
++	 */
++	dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
++	if (dqsrc != 0)
++		qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, s->sdq);
++	else
++		qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, 0);
++}
++
++#define QB_VDQCR_VERB_DCT_SHIFT    0
++#define QB_VDQCR_VERB_DT_SHIFT     2
++#define QB_VDQCR_VERB_RLS_SHIFT    4
++#define QB_VDQCR_VERB_WAE_SHIFT    5
++
++enum qb_pull_dt_e {
++	qb_pull_dt_channel,
++	qb_pull_dt_workqueue,
++	qb_pull_dt_framequeue
++};
++
++/**
++ * qbman_pull_desc_clear() - Clear the contents of a descriptor to
++ *                           default/starting state
++ * @d: the pull dequeue descriptor to be cleared
++ */
++void qbman_pull_desc_clear(struct qbman_pull_desc *d)
++{
++	memset(d, 0, sizeof(*d));
++}
++
++/**
++ * qbman_pull_desc_set_storage()- Set the pull dequeue storage
++ * @d:            the pull dequeue descriptor to be set
++ * @storage:      the pointer of the memory to store the dequeue result
++ * @storage_phys: the physical address of the storage memory
++ * @stash:        to indicate whether write allocate is enabled
++ *
++ * If not called, or if called with 'storage' as NULL, the result pull dequeues
++ * will produce results to DQRR. If 'storage' is non-NULL, then results are
++ * produced to the given memory location (using the DMA address which
++ * the caller provides in 'storage_phys'), and 'stash' controls whether or not
++ * those writes to main-memory express a cache-warming attribute.
++ */
++void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
++				 struct dpaa2_dq *storage,
++				 dma_addr_t storage_phys,
++				 int stash)
++{
++	/* save the virtual address */
++	d->rsp_addr_virt = (u64)(uintptr_t)storage;
++
++	if (!storage) {
++		d->verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
++		return;
++	}
++	d->verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
++	if (stash)
++		d->verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
++	else
++		d->verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
++
++	d->rsp_addr = cpu_to_le64(storage_phys);
++}
++
++/**
++ * qbman_pull_desc_set_numframes() - Set the number of frames to be dequeued
++ * @d:         the pull dequeue descriptor to be set
++ * @numframes: number of frames to be set, must be between 1 and 16, inclusive
++ */
++void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes)
++{
++	d->numf = numframes - 1;
++}
++
++void qbman_pull_desc_set_token(struct qbman_pull_desc *d, u8 token)
++{
++	d->tok = token;
++}
++
++/*
++ * Exactly one of the following descriptor "actions" should be set. (Calling any
++ * one of these will replace the effect of any prior call to one of these.)
++ * - pull dequeue from the given frame queue (FQ)
++ * - pull dequeue from any FQ in the given work queue (WQ)
++ * - pull dequeue from any FQ in any WQ in the given channel
++ */
++
++/**
++ * qbman_pull_desc_set_fq() - Set fqid from which the dequeue command dequeues
++ * @fqid: the frame queue index of the given FQ
++ */
++void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid)
++{
++	d->verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
++	d->verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
++	d->dq_src = cpu_to_le32(fqid);
++}
++
++/**
++ * qbman_pull_desc_set_wq() - Set wqid from which the dequeue command dequeues
++ * @wqid: composed of channel id and wqid within the channel
++ * @dct:  the dequeue command type
++ */
++void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
++			    enum qbman_pull_type_e dct)
++{
++	d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
++	d->verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
++	d->dq_src = cpu_to_le32(wqid);
++}
++
++/**
++ * qbman_pull_desc_set_channel() - Set channelid from which the dequeue command
++ *                                 dequeues
++ * @chid: the channel id to be dequeued
++ * @dct:  the dequeue command type
++ */
++void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
++				 enum qbman_pull_type_e dct)
++{
++	d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
++	d->verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
++	d->dq_src = cpu_to_le32(chid);
++}
++
++/**
++ * qbman_swp_pull() - Issue the pull dequeue command
++ * @s: the software portal object
++ * @d: the software portal descriptor which has been configured with
++ *     the set of qbman_pull_desc_set_*() calls
++ *
++ * Return 0 for success, and -EBUSY if the software portal is not ready
++ * to do pull dequeue.
++ */
++int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
++{
++	struct qbman_pull_desc *p;
++
++	if (!atomic_dec_and_test(&s->vdq.available)) {
++		atomic_inc(&s->vdq.available);
++		return -EBUSY;
++	}
++	s->vdq.storage = (void *)(uintptr_t)d->rsp_addr_virt;
++	p = qbman_get_cmd(s, QBMAN_CENA_SWP_VDQCR);
++	p->numf = d->numf;
++	p->tok = QMAN_DQ_TOKEN_VALID;
++	p->dq_src = d->dq_src;
++	p->rsp_addr = d->rsp_addr;
++	p->rsp_addr_virt = d->rsp_addr_virt;
++	dma_wmb();
++
++	/* Set the verb byte, have to substitute in the valid-bit */
++	p->verb = d->verb | s->vdq.valid_bit;
++	s->vdq.valid_bit ^= QB_VALID_BIT;
++	dccvac(p);
++
++	return 0;
++}
++
++#define QMAN_DQRR_PI_MASK   0xf
++
++/**
++ * qbman_swp_dqrr_next() - Get an valid DQRR entry
++ * @s: the software portal object
++ *
++ * Return NULL if there are no unconsumed DQRR entries. Return a DQRR entry
++ * only once, so repeated calls can return a sequence of DQRR entries, without
++ * requiring they be consumed immediately or in any particular order.
++ */
++const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
++{
++	u32 verb;
++	u32 response_verb;
++	u32 flags;
++	struct dpaa2_dq *p;
++
++	/* Before using valid-bit to detect if something is there, we have to
++	 * handle the case of the DQRR reset bug...
++	 */
++	if (unlikely(s->dqrr.reset_bug)) {
++		/*
++		 * We pick up new entries by cache-inhibited producer index,
++		 * which means that a non-coherent mapping would require us to
++		 * invalidate and read *only* once that PI has indicated that
++		 * there's an entry here. The first trip around the DQRR ring
++		 * will be much less efficient than all subsequent trips around
++		 * it...
++		 */
++		u8 pi = qbman_read_register(s, QBMAN_CINH_SWP_DQPI) &
++			QMAN_DQRR_PI_MASK;
++
++		/* there are new entries if pi != next_idx */
++		if (pi == s->dqrr.next_idx)
++			return NULL;
++
++		/*
++		 * if next_idx is/was the last ring index, and 'pi' is
++		 * different, we can disable the workaround as all the ring
++		 * entries have now been DMA'd to so valid-bit checking is
++		 * repaired. Note: this logic needs to be based on next_idx
++		 * (which increments one at a time), rather than on pi (which
++		 * can burst and wrap-around between our snapshots of it).
++		 */
++		if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) {
++			pr_debug("next_idx=%d, pi=%d, clear reset bug\n",
++				 s->dqrr.next_idx, pi);
++			s->dqrr.reset_bug = 0;
++		}
++		qbman_inval_prefetch(s,	QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
++	}
++
++	p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
++	verb = p->dq.verb;
++
++	/*
++	 * If the valid-bit isn't of the expected polarity, nothing there. Note,
++	 * in the DQRR reset bug workaround, we shouldn't need to skip these
++	 * check, because we've already determined that a new entry is available
++	 * and we've invalidated the cacheline before reading it, so the
++	 * valid-bit behaviour is repaired and should tell us what we already
++	 * knew from reading PI.
++	 */
++	if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
++		qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
++		return NULL;
++	}
++	/*
++	 * There's something there. Move "next_idx" attention to the next ring
++	 * entry (and prefetch it) before returning what we found.
++	 */
++	s->dqrr.next_idx++;
++	s->dqrr.next_idx &= s->dqrr.dqrr_size - 1; /* Wrap around */
++	if (!s->dqrr.next_idx)
++		s->dqrr.valid_bit ^= QB_VALID_BIT;
++
++	/*
++	 * If this is the final response to a volatile dequeue command
++	 * indicate that the vdq is available
++	 */
++	flags = p->dq.stat;
++	response_verb = verb & QBMAN_RESULT_MASK;
++	if ((response_verb == QBMAN_RESULT_DQ) &&
++	    (flags & DPAA2_DQ_STAT_VOLATILE) &&
++	    (flags & DPAA2_DQ_STAT_EXPIRED))
++		atomic_inc(&s->vdq.available);
++
++	qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
++
++	return p;
++}
++
++/**
++ * qbman_swp_dqrr_consume() -  Consume DQRR entries previously returned from
++ *                             qbman_swp_dqrr_next().
++ * @s: the software portal object
++ * @dq: the DQRR entry to be consumed
++ */
++void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq)
++{
++	qbman_write_register(s, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
++}
++
++/**
++ * qbman_result_has_new_result() - Check and get the dequeue response from the
++ *                                 dq storage memory set in pull dequeue command
++ * @s: the software portal object
++ * @dq: the dequeue result read from the memory
++ *
++ * Return 1 for getting a valid dequeue result, or 0 for not getting a valid
++ * dequeue result.
++ *
++ * Only used for user-provided storage of dequeue results, not DQRR. For
++ * efficiency purposes, the driver will perform any required endianness
++ * conversion to ensure that the user's dequeue result storage is in host-endian
++ * format. As such, once the user has called qbman_result_has_new_result() and
++ * been returned a valid dequeue result, they should not call it again on
++ * the same memory location (except of course if another dequeue command has
++ * been executed to produce a new result to that location).
++ */
++int qbman_result_has_new_result(struct qbman_swp *s, const struct dpaa2_dq *dq)
++{
++	if (dq->dq.tok != QMAN_DQ_TOKEN_VALID)
++		return 0;
++
++	/*
++	 * Set token to be 0 so we will detect change back to 1
++	 * next time the looping is traversed. Const is cast away here
++	 * as we want users to treat the dequeue responses as read only.
++	 */
++	((struct dpaa2_dq *)dq)->dq.tok = 0;
++
++	/*
++	 * Determine whether VDQCR is available based on whether the
++	 * current result is sitting in the first storage location of
++	 * the busy command.
++	 */
++	if (s->vdq.storage == dq) {
++		s->vdq.storage = NULL;
++		atomic_inc(&s->vdq.available);
++	}
++
++	return 1;
++}
++
++/**
++ * qbman_release_desc_clear() - Clear the contents of a descriptor to
++ *                              default/starting state.
++ */
++void qbman_release_desc_clear(struct qbman_release_desc *d)
++{
++	memset(d, 0, sizeof(*d));
++	d->verb = 1 << 5; /* Release Command Valid */
++}
++
++/**
++ * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to
++ */
++void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid)
++{
++	d->bpid = cpu_to_le16(bpid);
++}
++
++/**
++ * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI
++ * interrupt source should be asserted after the release command is completed.
++ */
++void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
++{
++	if (enable)
++		d->verb |= 1 << 6;
++	else
++		d->verb &= ~(1 << 6);
++}
++
++#define RAR_IDX(rar)     ((rar) & 0x7)
++#define RAR_VB(rar)      ((rar) & 0x80)
++#define RAR_SUCCESS(rar) ((rar) & 0x100)
++
++/**
++ * qbman_swp_release() - Issue a buffer release command
++ * @s:           the software portal object
++ * @d:           the release descriptor
++ * @buffers:     a pointer pointing to the buffer address to be released
++ * @num_buffers: number of buffers to be released,  must be less than 8
++ *
++ * Return 0 for success, -EBUSY if the release command ring is not ready.
++ */
++int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
++		      const u64 *buffers, unsigned int num_buffers)
++{
++	int i;
++	struct qbman_release_desc *p;
++	u32 rar;
++
++	if (!num_buffers || (num_buffers > 7))
++		return -EINVAL;
++
++	rar = qbman_read_register(s, QBMAN_CINH_SWP_RAR);
++	if (!RAR_SUCCESS(rar))
++		return -EBUSY;
++
++	/* Start the release command */
++	p = qbman_get_cmd(s, QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
++	/* Copy the caller's buffer pointers to the command */
++	for (i = 0; i < num_buffers; i++)
++		p->buf[i] = cpu_to_le64(buffers[i]);
++	p->bpid = d->bpid;
++
++	/*
++	 * Set the verb byte, have to substitute in the valid-bit and the number
++	 * of buffers.
++	 */
++	dma_wmb();
++	p->verb = d->verb | RAR_VB(rar) | num_buffers;
++	dccvac(p);
++
++	return 0;
++}
++
++struct qbman_acquire_desc {
++	u8 verb;
++	u8 reserved;
++	__le16 bpid;
++	u8 num;
++	u8 reserved2[59];
++};
++
++struct qbman_acquire_rslt {
++	u8 verb;
++	u8 rslt;
++	__le16 reserved;
++	u8 num;
++	u8 reserved2[3];
++	__le64 buf[7];
++};
++
++/**
++ * qbman_swp_acquire() - Issue a buffer acquire command
++ * @s:           the software portal object
++ * @bpid:        the buffer pool index
++ * @buffers:     a pointer pointing to the acquired buffer addresses
++ * @num_buffers: number of buffers to be acquired, must be less than 8
++ *
++ * Return 0 for success, or negative error code if the acquire command
++ * fails.
++ */
++int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
++		      unsigned int num_buffers)
++{
++	struct qbman_acquire_desc *p;
++	struct qbman_acquire_rslt *r;
++	int i;
++
++	if (!num_buffers || (num_buffers > 7))
++		return -EINVAL;
++
++	/* Start the management command */
++	p = qbman_swp_mc_start(s);
++
++	if (!p)
++		return -EBUSY;
++
++	/* Encode the caller-provided attributes */
++	p->bpid = cpu_to_le16(bpid);
++	p->num = num_buffers;
++
++	/* Complete the management command */
++	r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
++	if (unlikely(!r)) {
++		pr_err("qbman: acquire from BPID %d failed, no response\n",
++		       bpid);
++		return -EIO;
++	}
++
++	/* Decode the outcome */
++	WARN_ON((r->verb & 0x7f) != QBMAN_MC_ACQUIRE);
++
++	/* Determine success or failure */
++	if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
++		pr_err("qbman: acquire from BPID 0x%x failed, code=0x%02x\n",
++		       bpid, r->rslt);
++		return -EIO;
++	}
++
++	WARN_ON(r->num > num_buffers);
++
++	/* Copy the acquired buffers to the caller's array */
++	for (i = 0; i < r->num; i++)
++		buffers[i] = le64_to_cpu(r->buf[i]);
++
++	return (int)r->num;
++}
++
++struct qbman_alt_fq_state_desc {
++	u8 verb;
++	u8 reserved[3];
++	__le32 fqid;
++	u8 reserved2[56];
++};
++
++struct qbman_alt_fq_state_rslt {
++	u8 verb;
++	u8 rslt;
++	u8 reserved[62];
++};
++
++#define ALT_FQ_FQID_MASK 0x00FFFFFF
++
++int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
++			   u8 alt_fq_verb)
++{
++	struct qbman_alt_fq_state_desc *p;
++	struct qbman_alt_fq_state_rslt *r;
++
++	/* Start the management command */
++	p = qbman_swp_mc_start(s);
++	if (!p)
++		return -EBUSY;
++
++	p->fqid = cpu_to_le32(fqid & ALT_FQ_FQID_MASK);
++
++	/* Complete the management command */
++	r = qbman_swp_mc_complete(s, p, alt_fq_verb);
++	if (unlikely(!r)) {
++		pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
++		       alt_fq_verb);
++		return -EIO;
++	}
++
++	/* Decode the outcome */
++	WARN_ON((r->verb & QBMAN_RESULT_MASK) != alt_fq_verb);
++
++	/* Determine success or failure */
++	if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
++		pr_err("qbman: ALT FQID %d failed: verb = 0x%08x code = 0x%02x\n",
++		       fqid, r->verb, r->rslt);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++struct qbman_cdan_ctrl_desc {
++	u8 verb;
++	u8 reserved;
++	__le16 ch;
++	u8 we;
++	u8 ctrl;
++	__le16 reserved2;
++	__le64 cdan_ctx;
++	u8 reserved3[48];
++
++};
++
++struct qbman_cdan_ctrl_rslt {
++	u8 verb;
++	u8 rslt;
++	__le16 ch;
++	u8 reserved[60];
++};
++
++int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
++		       u8 we_mask, u8 cdan_en,
++		       u64 ctx)
++{
++	struct qbman_cdan_ctrl_desc *p = NULL;
++	struct qbman_cdan_ctrl_rslt *r = NULL;
++
++	/* Start the management command */
++	p = qbman_swp_mc_start(s);
++	if (!p)
++		return -EBUSY;
++
++	/* Encode the caller-provided attributes */
++	p->ch = cpu_to_le16(channelid);
++	p->we = we_mask;
++	if (cdan_en)
++		p->ctrl = 1;
++	else
++		p->ctrl = 0;
++	p->cdan_ctx = cpu_to_le64(ctx);
++
++	/* Complete the management command */
++	r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
++	if (unlikely(!r)) {
++		pr_err("qbman: wqchan config failed, no response\n");
++		return -EIO;
++	}
++
++	WARN_ON((r->verb & 0x7f) != QBMAN_WQCHAN_CONFIGURE);
++
++	/* Determine success or failure */
++	if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
++		pr_err("qbman: CDAN cQID %d failed: code = 0x%02x\n",
++		       channelid, r->rslt);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++#define QBMAN_RESPONSE_VERB_MASK	0x7f
++#define QBMAN_FQ_QUERY_NP		0x45
++#define QBMAN_BP_QUERY			0x32
++
++struct qbman_fq_query_desc {
++	u8 verb;
++	u8 reserved[3];
++	u32 fqid;
++	u8 reserved2[56];
++};
++
++int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
++			 struct qbman_fq_query_np_rslt *r)
++{
++	struct qbman_fq_query_desc *p;
++	void *resp;
++
++	p = (struct qbman_fq_query_desc *)qbman_swp_mc_start(s);
++	if (!p)
++		return -EBUSY;
++
++	/* FQID is a 24 bit value */
++	p->fqid = cpu_to_le32(fqid) & 0x00FFFFFF;
++	resp = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP);
++	if (!resp) {
++		pr_err("qbman: Query FQID %d NP fields failed, no response\n",
++		       fqid);
++		return -EIO;
++	}
++	*r = *(struct qbman_fq_query_np_rslt *)resp;
++	/* Decode the outcome */
++	WARN_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_FQ_QUERY_NP);
++
++	/* Determine success or failure */
++	if (r->rslt != QBMAN_MC_RSLT_OK) {
++		pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n",
++		       p->fqid, r->rslt);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++u32 qbman_fq_state_frame_count(const struct qbman_fq_query_np_rslt *r)
++{
++	return (r->frm_cnt & 0x00FFFFFF);
++}
++
++u32 qbman_fq_state_byte_count(const struct qbman_fq_query_np_rslt *r)
++{
++	return r->byte_cnt;
++}
++
++struct qbman_bp_query_desc {
++	u8 verb;
++	u8 reserved;
++	u16 bpid;
++	u8 reserved2[60];
++};
++
++int qbman_bp_query(struct qbman_swp *s, u32 bpid,
++		   struct qbman_bp_query_rslt *r)
++{
++	struct qbman_bp_query_desc *p;
++	void *resp;
++
++	p = (struct qbman_bp_query_desc *)qbman_swp_mc_start(s);
++	if (!p)
++		return -EBUSY;
++
++	p->bpid = bpid;
++	resp = qbman_swp_mc_complete(s, p, QBMAN_BP_QUERY);
++	if (!resp) {
++		pr_err("qbman: Query BPID %d fields failed, no response\n",
++		       bpid);
++		return -EIO;
++	}
++	*r = *(struct qbman_bp_query_rslt *)resp;
++	/* Decode the outcome */
++	WARN_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_BP_QUERY);
++
++	/* Determine success or failure */
++	if (r->rslt != QBMAN_MC_RSLT_OK) {
++		pr_err("Query fields of BPID 0x%x failed, code=0x%02x\n",
++		       bpid, r->rslt);
++		return -EIO;
++	}
++
++	return 0;
++}
++
++u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a)
++{
++	return a->fill;
++}
+--- /dev/null
++++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
+@@ -0,0 +1,505 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
++/*
++ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
++ * Copyright 2016 NXP
++ *
++ */
++#ifndef __FSL_QBMAN_PORTAL_H
++#define __FSL_QBMAN_PORTAL_H
++
++#include "../../include/dpaa2-fd.h"
++
++struct dpaa2_dq;
++struct qbman_swp;
++
++/* qbman software portal descriptor structure */
++struct qbman_swp_desc {
++	void *cena_bar; /* Cache-enabled portal base address */
++	void *cinh_bar; /* Cache-inhibited portal base address */
++	u32 qman_version;
++};
++
++#define QBMAN_SWP_INTERRUPT_EQRI 0x01
++#define QBMAN_SWP_INTERRUPT_EQDI 0x02
++#define QBMAN_SWP_INTERRUPT_DQRI 0x04
++#define QBMAN_SWP_INTERRUPT_RCRI 0x08
++#define QBMAN_SWP_INTERRUPT_RCDI 0x10
++#define QBMAN_SWP_INTERRUPT_VDCI 0x20
++
++/* the structure for pull dequeue descriptor */
++struct qbman_pull_desc {
++	u8 verb;
++	u8 numf;
++	u8 tok;
++	u8 reserved;
++	__le32 dq_src;
++	__le64 rsp_addr;
++	u64 rsp_addr_virt;
++	u8 padding[40];
++};
++
++enum qbman_pull_type_e {
++	/* dequeue with priority precedence, respect intra-class scheduling */
++	qbman_pull_type_prio = 1,
++	/* dequeue with active FQ precedence, respect ICS */
++	qbman_pull_type_active,
++	/* dequeue with active FQ precedence, no ICS */
++	qbman_pull_type_active_noics
++};
++
++/* Definitions for parsing dequeue entries */
++#define QBMAN_RESULT_MASK      0x7f
++#define QBMAN_RESULT_DQ        0x60
++#define QBMAN_RESULT_FQRN      0x21
++#define QBMAN_RESULT_FQRNI     0x22
++#define QBMAN_RESULT_FQPN      0x24
++#define QBMAN_RESULT_FQDAN     0x25
++#define QBMAN_RESULT_CDAN      0x26
++#define QBMAN_RESULT_CSCN_MEM  0x27
++#define QBMAN_RESULT_CGCU      0x28
++#define QBMAN_RESULT_BPSCN     0x29
++#define QBMAN_RESULT_CSCN_WQ   0x2a
++
++/* QBMan FQ management command codes */
++#define QBMAN_FQ_SCHEDULE	0x48
++#define QBMAN_FQ_FORCE		0x49
++#define QBMAN_FQ_XON		0x4d
++#define QBMAN_FQ_XOFF		0x4e
++
++/* structure of enqueue descriptor */
++struct qbman_eq_desc {
++	u8 verb;
++	u8 dca;
++	__le16 seqnum;
++	__le16 orpid;
++	__le16 reserved1;
++	__le32 tgtid;
++	__le32 tag;
++	__le16 qdbin;
++	u8 qpri;
++	u8 reserved[3];
++	u8 wae;
++	u8 rspid;
++	__le64 rsp_addr;
++	u8 fd[32];
++};
++
++/* buffer release descriptor */
++struct qbman_release_desc {
++	u8 verb;
++	u8 reserved;
++	__le16 bpid;
++	__le32 reserved2;
++	__le64 buf[7];
++};
++
++/* Management command result codes */
++#define QBMAN_MC_RSLT_OK      0xf0
++
++#define CODE_CDAN_WE_EN    0x1
++#define CODE_CDAN_WE_CTX   0x4
++
++/* portal data structure */
++struct qbman_swp {
++	const struct qbman_swp_desc *desc;
++	void __iomem *addr_cena;
++	void __iomem *addr_cinh;
++
++	/* Management commands */
++	struct {
++		u32 valid_bit; /* 0x00 or 0x80 */
++	} mc;
++
++	/* Push dequeues */
++	u32 sdq;
++
++	/* Volatile dequeues */
++	struct {
++		atomic_t available; /* indicates if a command can be sent */
++		u32 valid_bit; /* 0x00 or 0x80 */
++		struct dpaa2_dq *storage; /* NULL if DQRR */
++	} vdq;
++
++	/* DQRR */
++	struct {
++		u32 next_idx;
++		u32 valid_bit;
++		u8 dqrr_size;
++		int reset_bug; /* indicates dqrr reset workaround is needed */
++	} dqrr;
++};
++
++struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d);
++void qbman_swp_finish(struct qbman_swp *p);
++u32 qbman_swp_interrupt_read_status(struct qbman_swp *p);
++void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask);
++u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p);
++void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask);
++int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p);
++void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit);
++
++void qbman_swp_push_get(struct qbman_swp *p, u8 channel_idx, int *enabled);
++void qbman_swp_push_set(struct qbman_swp *p, u8 channel_idx, int enable);
++
++void qbman_pull_desc_clear(struct qbman_pull_desc *d);
++void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
++				 struct dpaa2_dq *storage,
++				 dma_addr_t storage_phys,
++				 int stash);
++void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes);
++void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid);
++void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
++			    enum qbman_pull_type_e dct);
++void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
++				 enum qbman_pull_type_e dct);
++
++int qbman_swp_pull(struct qbman_swp *p, struct qbman_pull_desc *d);
++
++const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s);
++void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq);
++
++int qbman_result_has_new_result(struct qbman_swp *p, const struct dpaa2_dq *dq);
++
++void qbman_eq_desc_clear(struct qbman_eq_desc *d);
++void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
++void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
++			   u16 oprid, u16 seqnum, int incomplete);
++void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, u16 oprid, u16 seqnum);
++void qbman_eq_desc_set_token(struct qbman_eq_desc *d, u8 token);
++void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
++void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
++			  u32 qd_bin, u32 qd_prio);
++
++int qbman_swp_enqueue(struct qbman_swp *p, const struct qbman_eq_desc *d,
++		      const struct dpaa2_fd *fd);
++
++void qbman_release_desc_clear(struct qbman_release_desc *d);
++void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid);
++void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable);
++
++int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
++		      const u64 *buffers, unsigned int num_buffers);
++int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
++		      unsigned int num_buffers);
++int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
++			   u8 alt_fq_verb);
++int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
++		       u8 we_mask, u8 cdan_en,
++		       u64 ctx);
++
++void *qbman_swp_mc_start(struct qbman_swp *p);
++void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb);
++void *qbman_swp_mc_result(struct qbman_swp *p);
++
++/**
++ * qbman_result_is_DQ() - check if the dequeue result is a dequeue response
++ * @dq: the dequeue result to be checked
++ *
++ * DQRR entries may contain non-dequeue results, ie. notifications
++ */
++static inline int qbman_result_is_DQ(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_DQ);
++}
++
++/**
++ * qbman_result_is_SCN() - Check the dequeue result is notification or not
++ * @dq: the dequeue result to be checked
++ *
++ */
++static inline int qbman_result_is_SCN(const struct dpaa2_dq *dq)
++{
++	return !qbman_result_is_DQ(dq);
++}
++
++/* FQ Data Availability */
++static inline int qbman_result_is_FQDAN(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQDAN);
++}
++
++/* Channel Data Availability */
++static inline int qbman_result_is_CDAN(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CDAN);
++}
++
++/* Congestion State Change */
++static inline int qbman_result_is_CSCN(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CSCN_WQ);
++}
++
++/* Buffer Pool State Change */
++static inline int qbman_result_is_BPSCN(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_BPSCN);
++}
++
++/* Congestion Group Count Update */
++static inline int qbman_result_is_CGCU(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CGCU);
++}
++
++/* Retirement */
++static inline int qbman_result_is_FQRN(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRN);
++}
++
++/* Retirement Immediate */
++static inline int qbman_result_is_FQRNI(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRNI);
++}
++
++ /* Park */
++static inline int qbman_result_is_FQPN(const struct dpaa2_dq *dq)
++{
++	return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQPN);
++}
++
++/**
++ * qbman_result_SCN_state() - Get the state field in State-change notification
++ */
++static inline u8 qbman_result_SCN_state(const struct dpaa2_dq *scn)
++{
++	return scn->scn.state;
++}
++
++#define SCN_RID_MASK 0x00FFFFFF
++
++/**
++ * qbman_result_SCN_rid() - Get the resource id in State-change notification
++ */
++static inline u32 qbman_result_SCN_rid(const struct dpaa2_dq *scn)
++{
++	return le32_to_cpu(scn->scn.rid_tok) & SCN_RID_MASK;
++}
++
++/**
++ * qbman_result_SCN_ctx() - Get the context data in State-change notification
++ */
++static inline u64 qbman_result_SCN_ctx(const struct dpaa2_dq *scn)
++{
++	return le64_to_cpu(scn->scn.ctx);
++}
++
++/**
++ * qbman_swp_fq_schedule() - Move the fq to the scheduled state
++ * @s:    the software portal object
++ * @fqid: the index of frame queue to be scheduled
++ *
++ * There are a couple of different ways that a FQ can end up parked state,
++ * This schedules it.
++ *
++ * Return 0 for success, or negative error code for failure.
++ */
++static inline int qbman_swp_fq_schedule(struct qbman_swp *s, u32 fqid)
++{
++	return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
++}
++
++/**
++ * qbman_swp_fq_force() - Force the FQ to fully scheduled state
++ * @s:    the software portal object
++ * @fqid: the index of frame queue to be forced
++ *
++ * Force eligible will force a tentatively-scheduled FQ to be fully-scheduled
++ * and thus be available for selection by any channel-dequeuing behaviour (push
++ * or pull). If the FQ is subsequently "dequeued" from the channel and is still
++ * empty at the time this happens, the resulting dq_entry will have no FD.
++ * (qbman_result_DQ_fd() will return NULL.)
++ *
++ * Return 0 for success, or negative error code for failure.
++ */
++static inline int qbman_swp_fq_force(struct qbman_swp *s, u32 fqid)
++{
++	return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
++}
++
++/**
++ * qbman_swp_fq_xon() - sets FQ flow-control to XON
++ * @s:    the software portal object
++ * @fqid: the index of frame queue
++ *
++ * This setting doesn't affect enqueues to the FQ, just dequeues.
++ *
++ * Return 0 for success, or negative error code for failure.
++ */
++static inline int qbman_swp_fq_xon(struct qbman_swp *s, u32 fqid)
++{
++	return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
++}
++
++/**
++ * qbman_swp_fq_xoff() - sets FQ flow-control to XOFF
++ * @s:    the software portal object
++ * @fqid: the index of frame queue
++ *
++ * This setting doesn't affect enqueues to the FQ, just dequeues.
++ * XOFF FQs will remain in the tenatively-scheduled state, even when
++ * non-empty, meaning they won't be selected for scheduled dequeuing.
++ * If a FQ is changed to XOFF after it had already become truly-scheduled
++ * to a channel, and a pull dequeue of that channel occurs that selects
++ * that FQ for dequeuing, then the resulting dq_entry will have no FD.
++ * (qbman_result_DQ_fd() will return NULL.)
++ *
++ * Return 0 for success, or negative error code for failure.
++ */
++static inline int qbman_swp_fq_xoff(struct qbman_swp *s, u32 fqid)
++{
++	return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
++}
++
++/* If the user has been allocated a channel object that is going to generate
++ * CDANs to another channel, then the qbman_swp_CDAN* functions will be
++ * necessary.
++ *
++ * CDAN-enabled channels only generate a single CDAN notification, after which
++ * they need to be reenabled before they'll generate another. The idea is
++ * that pull dequeuing will occur in reaction to the CDAN, followed by a
++ * reenable step. Each function generates a distinct command to hardware, so a
++ * combination function is provided if the user wishes to modify the "context"
++ * (which shows up in each CDAN message) each time they reenable, as a single
++ * command to hardware.
++ */
++
++/**
++ * qbman_swp_CDAN_set_context() - Set CDAN context
++ * @s:         the software portal object
++ * @channelid: the channel index
++ * @ctx:       the context to be set in CDAN
++ *
++ * Return 0 for success, or negative error code for failure.
++ */
++static inline int qbman_swp_CDAN_set_context(struct qbman_swp *s, u16 channelid,
++					     u64 ctx)
++{
++	return qbman_swp_CDAN_set(s, channelid,
++				  CODE_CDAN_WE_CTX,
++				  0, ctx);
++}
++
++/**
++ * qbman_swp_CDAN_enable() - Enable CDAN for the channel
++ * @s:         the software portal object
++ * @channelid: the index of the channel to generate CDAN
++ *
++ * Return 0 for success, or negative error code for failure.
++ */
++static inline int qbman_swp_CDAN_enable(struct qbman_swp *s, u16 channelid)
++{
++	return qbman_swp_CDAN_set(s, channelid,
++				  CODE_CDAN_WE_EN,
++				  1, 0);
++}
++
++/**
++ * qbman_swp_CDAN_disable() - disable CDAN for the channel
++ * @s:         the software portal object
++ * @channelid: the index of the channel to generate CDAN
++ *
++ * Return 0 for success, or negative error code for failure.
++ */
++static inline int qbman_swp_CDAN_disable(struct qbman_swp *s, u16 channelid)
++{
++	return qbman_swp_CDAN_set(s, channelid,
++				  CODE_CDAN_WE_EN,
++				  0, 0);
++}
++
++/**
++ * qbman_swp_CDAN_set_context_enable() - Set CDAN contest and enable CDAN
++ * @s:         the software portal object
++ * @channelid: the index of the channel to generate CDAN
++ * @ctx:i      the context set in CDAN
++ *
++ * Return 0 for success, or negative error code for failure.
++ */
++static inline int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s,
++						    u16 channelid,
++						    u64 ctx)
++{
++	return qbman_swp_CDAN_set(s, channelid,
++				  CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
++				  1, ctx);
++}
++
++/* Wraps up submit + poll-for-result */
++static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
++					  u8 cmd_verb)
++{
++	int loopvar = 1000;
++
++	qbman_swp_mc_submit(swp, cmd, cmd_verb);
++
++	do {
++		cmd = qbman_swp_mc_result(swp);
++	} while (!cmd && loopvar--);
++
++	WARN_ON(!loopvar);
++
++	return cmd;
++}
++
++/* Query APIs */
++struct qbman_fq_query_np_rslt {
++	u8 verb;
++	u8 rslt;
++	u8 st1;
++	u8 st2;
++	u8 reserved[2];
++	u16 od1_sfdr;
++	u16 od2_sfdr;
++	u16 od3_sfdr;
++	u16 ra1_sfdr;
++	u16 ra2_sfdr;
++	u32 pfdr_hptr;
++	u32 pfdr_tptr;
++	u32 frm_cnt;
++	u32 byte_cnt;
++	u16 ics_surp;
++	u8 is;
++	u8 reserved2[29];
++};
++
++int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
++			 struct qbman_fq_query_np_rslt *r);
++u32 qbman_fq_state_frame_count(const struct qbman_fq_query_np_rslt *r);
++u32 qbman_fq_state_byte_count(const struct qbman_fq_query_np_rslt *r);
++
++struct qbman_bp_query_rslt {
++	u8 verb;
++	u8 rslt;
++	u8 reserved[4];
++	u8 bdi;
++	u8 state;
++	u32 fill;
++	u32 hdotr;
++	u16 swdet;
++	u16 swdxt;
++	u16 hwdet;
++	u16 hwdxt;
++	u16 swset;
++	u16 swsxt;
++	u16 vbpid;
++	u16 icid;
++	u64 bpscn_addr;
++	u64 bpscn_ctx;
++	u16 hw_targ;
++	u8 dbe;
++	u8 reserved2;
++	u8 sdcnt;
++	u8 hdcnt;
++	u8 sscnt;
++	u8 reserved3[9];
++};
++
++int qbman_bp_query(struct qbman_swp *s, u32 bpid,
++		   struct qbman_bp_query_rslt *r);
++
++u32 qbman_bp_info_num_free_bufs(struct qbman_bp_query_rslt *a);
++
++#endif /* __FSL_QBMAN_PORTAL_H */
+--- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
++++ /dev/null
+@@ -1,140 +0,0 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
 - * ALTERNATIVELY, this software may be distributed under the terms of the
 - * GNU General Public License ("GPL") as published by the Free Software
 - * Foundation, either version 2 of that License or (at your option) any
@@ -10123,32 +13335,115 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -#define _FSL_DPMCP_CMD_H
 -
 -/* Minimal supported DPMCP Version */
--#define DPMCP_MIN_VER_MAJOR		3
--#define DPMCP_MIN_VER_MINOR		0
--
--/* Command versioning */
--#define DPMCP_CMD_BASE_VERSION		1
--#define DPMCP_CMD_ID_OFFSET		4
--
--#define DPMCP_CMD(id)	(((id) << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION)
+-#define DPMCP_MIN_VER_MAJOR				3
+-#define DPMCP_MIN_VER_MINOR				0
 -
 -/* Command IDs */
--#define DPMCP_CMDID_CLOSE		DPMCP_CMD(0x800)
--#define DPMCP_CMDID_OPEN		DPMCP_CMD(0x80b)
--#define DPMCP_CMDID_GET_API_VERSION	DPMCP_CMD(0xa0b)
+-#define DPMCP_CMDID_CLOSE				0x800
+-#define DPMCP_CMDID_OPEN				0x80b
+-#define DPMCP_CMDID_CREATE				0x90b
+-#define DPMCP_CMDID_DESTROY				0x900
 -
--#define DPMCP_CMDID_RESET		DPMCP_CMD(0x005)
+-#define DPMCP_CMDID_GET_ATTR				0x004
+-#define DPMCP_CMDID_RESET				0x005
+-
+-#define DPMCP_CMDID_SET_IRQ				0x010
+-#define DPMCP_CMDID_GET_IRQ				0x011
+-#define DPMCP_CMDID_SET_IRQ_ENABLE			0x012
+-#define DPMCP_CMDID_GET_IRQ_ENABLE			0x013
+-#define DPMCP_CMDID_SET_IRQ_MASK			0x014
+-#define DPMCP_CMDID_GET_IRQ_MASK			0x015
+-#define DPMCP_CMDID_GET_IRQ_STATUS			0x016
 -
 -struct dpmcp_cmd_open {
 -	__le32 dpmcp_id;
 -};
 -
+-struct dpmcp_cmd_create {
+-	__le32 portal_id;
+-};
+-
+-struct dpmcp_cmd_set_irq {
+-	/* cmd word 0 */
+-	u8 irq_index;
+-	u8 pad[3];
+-	__le32 irq_val;
+-	/* cmd word 1 */
+-	__le64 irq_addr;
+-	/* cmd word 2 */
+-	__le32 irq_num;
+-};
+-
+-struct dpmcp_cmd_get_irq {
+-	__le32 pad;
+-	u8 irq_index;
+-};
+-
+-struct dpmcp_rsp_get_irq {
+-	/* cmd word 0 */
+-	__le32 irq_val;
+-	__le32 pad;
+-	/* cmd word 1 */
+-	__le64 irq_paddr;
+-	/* cmd word 2 */
+-	__le32 irq_num;
+-	__le32 type;
+-};
+-
+-#define DPMCP_ENABLE		0x1
+-
+-struct dpmcp_cmd_set_irq_enable {
+-	u8 enable;
+-	u8 pad[3];
+-	u8 irq_index;
+-};
+-
+-struct dpmcp_cmd_get_irq_enable {
+-	__le32 pad;
+-	u8 irq_index;
+-};
+-
+-struct dpmcp_rsp_get_irq_enable {
+-	u8 enabled;
+-};
+-
+-struct dpmcp_cmd_set_irq_mask {
+-	__le32 mask;
+-	u8 irq_index;
+-};
+-
+-struct dpmcp_cmd_get_irq_mask {
+-	__le32 pad;
+-	u8 irq_index;
+-};
+-
+-struct dpmcp_rsp_get_irq_mask {
+-	__le32 mask;
+-};
+-
+-struct dpmcp_cmd_get_irq_status {
+-	__le32 status;
+-	u8 irq_index;
+-};
+-
+-struct dpmcp_rsp_get_irq_status {
+-	__le32 status;
+-};
+-
+-struct dpmcp_rsp_get_attributes {
+-	/* response word 0 */
+-	__le32 pad;
+-	__le32 id;
+-	/* response word 1 */
+-	__le16 version_major;
+-	__le16 version_minor;
+-};
+-
 -#endif /* _FSL_DPMCP_CMD_H */
---- a/drivers/staging/fsl-mc/bus/dpmcp.h
+--- a/drivers/staging/fsl-mc/bus/dpmcp.c
 +++ /dev/null
-@@ -1,60 +0,0 @@
--/*
-- * Copyright 2013-2016 Freescale Semiconductor Inc.
+@@ -1,504 +0,0 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
 - *
 - * Redistribution and use in source and binary forms, with or without
 - * modification, are permitted provided that the following conditions are met:
@@ -10161,6 +13456,514 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * names of any contributors may be used to endorse or promote products
 - * derived from this software without specific prior written permission.
 - *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#include "../include/mc-sys.h"
+-#include "../include/mc-cmd.h"
+-
+-#include "dpmcp.h"
+-#include "dpmcp-cmd.h"
+-
+-/**
+- * dpmcp_open() - Open a control session for the specified object.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @dpmcp_id:	DPMCP unique ID
+- * @token:	Returned token; use in subsequent API calls
+- *
+- * This function can be used to open a control session for an
+- * already created object; an object may have been declared in
+- * the DPL or by calling the dpmcp_create function.
+- * This function returns a unique authentication token,
+- * associated with the specific object ID and the specific MC
+- * portal; this token must be used in all subsequent commands for
+- * this specific object
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_open(struct fsl_mc_io *mc_io,
+-	       u32 cmd_flags,
+-	       int dpmcp_id,
+-	       u16 *token)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_open *cmd_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_OPEN,
+-					  cmd_flags, 0);
+-	cmd_params = (struct dpmcp_cmd_open *)cmd.params;
+-	cmd_params->dpmcp_id = cpu_to_le32(dpmcp_id);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	*token = mc_cmd_hdr_read_token(&cmd);
+-
+-	return err;
+-}
+-
+-/**
+- * dpmcp_close() - Close the control session of the object
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- *
+- * After this function is called, no further operations are
+- * allowed on the object without opening a new control session.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_close(struct fsl_mc_io *mc_io,
+-		u32 cmd_flags,
+-		u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CLOSE,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpmcp_create() - Create the DPMCP object.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @cfg:	Configuration structure
+- * @token:	Returned token; use in subsequent API calls
+- *
+- * Create the DPMCP object, allocate required resources and
+- * perform required initialization.
+- *
+- * The object can be created either by declaring it in the
+- * DPL file, or by calling this function.
+- * This function returns a unique authentication token,
+- * associated with the specific object ID and the specific MC
+- * portal; this token must be used in all subsequent calls to
+- * this specific object. For objects that are created using the
+- * DPL file, call dpmcp_open function to get an authentication
+- * token first.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_create(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 const struct dpmcp_cfg *cfg,
+-		 u16 *token)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_create *cmd_params;
+-
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CREATE,
+-					  cmd_flags, 0);
+-	cmd_params = (struct dpmcp_cmd_create *)cmd.params;
+-	cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	*token = mc_cmd_hdr_read_token(&cmd);
+-
+-	return 0;
+-}
+-
+-/**
+- * dpmcp_destroy() - Destroy the DPMCP object and release all its resources.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- *
+- * Return:	'0' on Success; error code otherwise.
+- */
+-int dpmcp_destroy(struct fsl_mc_io *mc_io,
+-		  u32 cmd_flags,
+-		  u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_DESTROY,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpmcp_reset() - Reset the DPMCP, returns the object to initial state.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_reset(struct fsl_mc_io *mc_io,
+-		u32 cmd_flags,
+-		u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_RESET,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpmcp_set_irq() - Set IRQ information for the DPMCP to trigger an interrupt.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- * @irq_index:	Identifies the interrupt index to configure
+- * @irq_cfg:	IRQ configuration
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_set_irq(struct fsl_mc_io *mc_io,
+-		  u32 cmd_flags,
+-		  u16 token,
+-		  u8 irq_index,
+-		  struct dpmcp_irq_cfg	*irq_cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_set_irq *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpmcp_cmd_set_irq *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-	cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
+-	cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
+-	cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpmcp_get_irq() - Get IRQ information from the DPMCP.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- * @irq_index:	The interrupt index to configure
+- * @type:	Interrupt type: 0 represents message interrupt
+- *		type (both irq_addr and irq_val are valid)
+- * @irq_cfg:	IRQ attributes
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_get_irq(struct fsl_mc_io *mc_io,
+-		  u32 cmd_flags,
+-		  u16 token,
+-		  u8 irq_index,
+-		  int *type,
+-		  struct dpmcp_irq_cfg	*irq_cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_get_irq *cmd_params;
+-	struct dpmcp_rsp_get_irq *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpmcp_cmd_get_irq *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpmcp_rsp_get_irq *)cmd.params;
+-	irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
+-	irq_cfg->paddr = le64_to_cpu(rsp_params->irq_paddr);
+-	irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
+-	*type = le32_to_cpu(rsp_params->type);
+-	return 0;
+-}
+-
+-/**
+- * dpmcp_set_irq_enable() - Set overall interrupt state.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- * @irq_index:	The interrupt index to configure
+- * @en:	Interrupt state - enable = 1, disable = 0
+- *
+- * Allows GPP software to control when interrupts are generated.
+- * Each interrupt can have up to 32 causes.  The enable/disable control's the
+- * overall interrupt state. if the interrupt is disabled no causes will cause
+- * an interrupt.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
+-			 u32 cmd_flags,
+-			 u16 token,
+-			 u8 irq_index,
+-			 u8 en)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_set_irq_enable *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_ENABLE,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpmcp_cmd_set_irq_enable *)cmd.params;
+-	cmd_params->enable = en & DPMCP_ENABLE;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpmcp_get_irq_enable() - Get overall interrupt state
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- * @irq_index:	The interrupt index to configure
+- * @en:		Returned interrupt state - enable = 1, disable = 0
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
+-			 u32 cmd_flags,
+-			 u16 token,
+-			 u8 irq_index,
+-			 u8 *en)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_get_irq_enable *cmd_params;
+-	struct dpmcp_rsp_get_irq_enable *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_ENABLE,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpmcp_cmd_get_irq_enable *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpmcp_rsp_get_irq_enable *)cmd.params;
+-	*en = rsp_params->enabled & DPMCP_ENABLE;
+-	return 0;
+-}
+-
+-/**
+- * dpmcp_set_irq_mask() - Set interrupt mask.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- * @irq_index:	The interrupt index to configure
+- * @mask:	Event mask to trigger interrupt;
+- *			each bit:
+- *				0 = ignore event
+- *				1 = consider event for asserting IRQ
+- *
+- * Every interrupt can have up to 32 causes and the interrupt model supports
+- * masking/unmasking each cause independently
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
+-		       u32 cmd_flags,
+-		       u16 token,
+-		       u8 irq_index,
+-		       u32 mask)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_set_irq_mask *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_MASK,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpmcp_cmd_set_irq_mask *)cmd.params;
+-	cmd_params->mask = cpu_to_le32(mask);
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dpmcp_get_irq_mask() - Get interrupt mask.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- * @irq_index:	The interrupt index to configure
+- * @mask:	Returned event mask to trigger interrupt
+- *
+- * Every interrupt can have up to 32 causes and the interrupt model supports
+- * masking/unmasking each cause independently
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
+-		       u32 cmd_flags,
+-		       u16 token,
+-		       u8 irq_index,
+-		       u32 *mask)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_get_irq_mask *cmd_params;
+-	struct dpmcp_rsp_get_irq_mask *rsp_params;
+-
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_MASK,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpmcp_cmd_get_irq_mask *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpmcp_rsp_get_irq_mask *)cmd.params;
+-	*mask = le32_to_cpu(rsp_params->mask);
+-
+-	return 0;
+-}
+-
+-/**
+- * dpmcp_get_irq_status() - Get the current status of any pending interrupts.
+- *
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- * @irq_index:	The interrupt index to configure
+- * @status:	Returned interrupts status - one bit per cause:
+- *			0 = no interrupt pending
+- *			1 = interrupt pending
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
+-			 u32 cmd_flags,
+-			 u16 token,
+-			 u8 irq_index,
+-			 u32 *status)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_cmd_get_irq_status *cmd_params;
+-	struct dpmcp_rsp_get_irq_status *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_STATUS,
+-					  cmd_flags, token);
+-	cmd_params = (struct dpmcp_cmd_get_irq_status *)cmd.params;
+-	cmd_params->status = cpu_to_le32(*status);
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpmcp_rsp_get_irq_status *)cmd.params;
+-	*status = le32_to_cpu(rsp_params->status);
+-
+-	return 0;
+-}
+-
+-/**
+- * dpmcp_get_attributes - Retrieve DPMCP attributes.
+- *
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPMCP object
+- * @attr:	Returned object's attributes
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
+-			 u32 cmd_flags,
+-			 u16 token,
+-			 struct dpmcp_attr *attr)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmcp_rsp_get_attributes *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_ATTR,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpmcp_rsp_get_attributes *)cmd.params;
+-	attr->id = le32_to_cpu(rsp_params->id);
+-	attr->version.major = le16_to_cpu(rsp_params->version_major);
+-	attr->version.minor = le16_to_cpu(rsp_params->version_minor);
+-
+-	return 0;
+-}
+--- a/drivers/staging/fsl-mc/bus/dpmcp.h
++++ /dev/null
+@@ -1,159 +0,0 @@
+-/* Copyright 2013-2015 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
 - * ALTERNATIVELY, this software may be distributed under the terms of the
 - * GNU General Public License ("GPL") as published by the Free Software
 - * Foundation, either version 2 of that License or (at your option) any
@@ -10181,30 +13984,129 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -#ifndef __FSL_DPMCP_H
 -#define __FSL_DPMCP_H
 -
--/*
-- * Data Path Management Command Portal API
+-/* Data Path Management Command Portal API
 - * Contains initialization APIs and runtime control APIs for DPMCP
 - */
 -
 -struct fsl_mc_io;
 -
 -int dpmcp_open(struct fsl_mc_io *mc_io,
--	       u32 cmd_flags,
+-	       uint32_t cmd_flags,
 -	       int dpmcp_id,
--	       u16 *token);
+-	       uint16_t *token);
+-
+-/* Get portal ID from pool */
+-#define DPMCP_GET_PORTAL_ID_FROM_POOL (-1)
 -
 -int dpmcp_close(struct fsl_mc_io *mc_io,
--		u32 cmd_flags,
--		u16 token);
+-		uint32_t cmd_flags,
+-		uint16_t token);
 -
--int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
--			  u32 cmd_flags,
--			  u16 *major_ver,
--			  u16 *minor_ver);
+-/**
+- * struct dpmcp_cfg - Structure representing DPMCP configuration
+- * @portal_id:	Portal ID; 'DPMCP_GET_PORTAL_ID_FROM_POOL' to get the portal ID
+- *		from pool
+- */
+-struct dpmcp_cfg {
+-	int portal_id;
+-};
+-
+-int dpmcp_create(struct fsl_mc_io	*mc_io,
+-		 uint32_t		cmd_flags,
+-		 const struct dpmcp_cfg	*cfg,
+-		uint16_t		*token);
+-
+-int dpmcp_destroy(struct fsl_mc_io *mc_io,
+-		  uint32_t cmd_flags,
+-		  uint16_t token);
 -
 -int dpmcp_reset(struct fsl_mc_io *mc_io,
--		u32 cmd_flags,
--		u16 token);
+-		uint32_t cmd_flags,
+-		uint16_t token);
+-
+-/* IRQ */
+-/* IRQ Index */
+-#define DPMCP_IRQ_INDEX                             0
+-/* irq event - Indicates that the link state changed */
+-#define DPMCP_IRQ_EVENT_CMD_DONE                    0x00000001
+-
+-/**
+- * struct dpmcp_irq_cfg - IRQ configuration
+- * @paddr:	Address that must be written to signal a message-based interrupt
+- * @val:	Value to write into irq_addr address
+- * @irq_num: A user defined number associated with this IRQ
+- */
+-struct dpmcp_irq_cfg {
+-	     uint64_t		paddr;
+-	     uint32_t		val;
+-	     int		irq_num;
+-};
+-
+-int dpmcp_set_irq(struct fsl_mc_io	*mc_io,
+-		  uint32_t		cmd_flags,
+-		  uint16_t		token,
+-		 uint8_t		irq_index,
+-		  struct dpmcp_irq_cfg	*irq_cfg);
+-
+-int dpmcp_get_irq(struct fsl_mc_io	*mc_io,
+-		  uint32_t		cmd_flags,
+-		  uint16_t		token,
+-		 uint8_t		irq_index,
+-		 int			*type,
+-		 struct dpmcp_irq_cfg	*irq_cfg);
+-
+-int dpmcp_set_irq_enable(struct fsl_mc_io	*mc_io,
+-			 uint32_t		cmd_flags,
+-			 uint16_t		token,
+-			uint8_t			irq_index,
+-			uint8_t			en);
+-
+-int dpmcp_get_irq_enable(struct fsl_mc_io	*mc_io,
+-			 uint32_t		cmd_flags,
+-			 uint16_t		token,
+-			uint8_t			irq_index,
+-			uint8_t			*en);
+-
+-int dpmcp_set_irq_mask(struct fsl_mc_io	*mc_io,
+-		       uint32_t	cmd_flags,
+-		       uint16_t		token,
+-		      uint8_t		irq_index,
+-		      uint32_t		mask);
+-
+-int dpmcp_get_irq_mask(struct fsl_mc_io	*mc_io,
+-		       uint32_t	cmd_flags,
+-		       uint16_t		token,
+-		      uint8_t		irq_index,
+-		      uint32_t		*mask);
+-
+-int dpmcp_get_irq_status(struct fsl_mc_io	*mc_io,
+-			 uint32_t		cmd_flags,
+-			 uint16_t		token,
+-			uint8_t			irq_index,
+-			uint32_t		*status);
+-
+-/**
+- * struct dpmcp_attr - Structure representing DPMCP attributes
+- * @id:		DPMCP object ID
+- * @version:	DPMCP version
+- */
+-struct dpmcp_attr {
+-	int id;
+-	/**
+-	 * struct version - Structure representing DPMCP version
+-	 * @major:	DPMCP major version
+-	 * @minor:	DPMCP minor version
+-	 */
+-	struct {
+-		uint16_t major;
+-		uint16_t minor;
+-	} version;
+-};
+-
+-int dpmcp_get_attributes(struct fsl_mc_io	*mc_io,
+-			 uint32_t		cmd_flags,
+-			 uint16_t		token,
+-			struct dpmcp_attr	*attr);
 -
 -#endif /* __FSL_DPMCP_H */
 --- a/drivers/staging/fsl-mc/bus/dpmng-cmd.h
@@ -10224,6 +14126,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - *       names of any contributors may be used to endorse or promote products
 - *       derived from this software without specific prior written permission.
 - *
+- *
 - * ALTERNATIVELY, this software may be distributed under the terms of the
 - * GNU General Public License ("GPL") as published by the Free Software
 - * Foundation, either version 2 of that License or (at your option) any
@@ -10252,14 +14155,13 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -#ifndef __FSL_DPMNG_CMD_H
 -#define __FSL_DPMNG_CMD_H
 -
--/* Command versioning */
--#define DPMNG_CMD_BASE_VERSION		1
--#define DPMNG_CMD_ID_OFFSET		4
--
--#define DPMNG_CMD(id)	(((id) << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION)
--
 -/* Command IDs */
--#define DPMNG_CMDID_GET_VERSION		DPMNG_CMD(0x831)
+-#define DPMNG_CMDID_GET_CONT_ID			0x830
+-#define DPMNG_CMDID_GET_VERSION			0x831
+-
+-struct dpmng_rsp_get_container_id {
+-	__le32 container_id;
+-};
 -
 -struct dpmng_rsp_get_version {
 -	__le32 revision;
@@ -10268,9 +14170,119 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -};
 -
 -#endif /* __FSL_DPMNG_CMD_H */
+--- a/drivers/staging/fsl-mc/bus/dpmng.c
++++ /dev/null
+@@ -1,107 +0,0 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#include "../include/mc-sys.h"
+-#include "../include/mc-cmd.h"
+-#include "../include/dpmng.h"
+-
+-#include "dpmng-cmd.h"
+-
+-/**
+- * mc_get_version() - Retrieves the Management Complex firmware
+- *			version information
+- * @mc_io:		Pointer to opaque I/O object
+- * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
+- * @mc_ver_info:	Returned version information structure
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int mc_get_version(struct fsl_mc_io *mc_io,
+-		   u32 cmd_flags,
+-		   struct mc_version *mc_ver_info)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmng_rsp_get_version *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION,
+-					  cmd_flags,
+-					  0);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpmng_rsp_get_version *)cmd.params;
+-	mc_ver_info->revision = le32_to_cpu(rsp_params->revision);
+-	mc_ver_info->major = le32_to_cpu(rsp_params->version_major);
+-	mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor);
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(mc_get_version);
+-
+-/**
+- * dpmng_get_container_id() - Get container ID associated with a given portal.
+- * @mc_io:		Pointer to MC portal's I/O object
+- * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
+- * @container_id:	Requested container ID
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dpmng_get_container_id(struct fsl_mc_io *mc_io,
+-			   u32 cmd_flags,
+-			   int *container_id)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dpmng_rsp_get_container_id *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_CONT_ID,
+-					  cmd_flags,
+-					  0);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dpmng_rsp_get_container_id *)cmd.params;
+-	*container_id = le32_to_cpu(rsp_params->container_id);
+-
+-	return 0;
+-}
+-
 --- a/drivers/staging/fsl-mc/bus/dprc-cmd.h
 +++ /dev/null
-@@ -1,451 +0,0 @@
+@@ -1,465 +0,0 @@
 -/*
 - * Copyright 2013-2016 Freescale Semiconductor Inc.
 - *
@@ -10285,6 +14297,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - *       names of any contributors may be used to endorse or promote products
 - *       derived from this software without specific prior written permission.
 - *
+- *
 - * ALTERNATIVELY, this software may be distributed under the terms of the
 - * GNU General Public License ("GPL") as published by the Free Software
 - * Foundation, either version 2 of that License or (at your option) any
@@ -10314,38 +14327,48 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -#define _FSL_DPRC_CMD_H
 -
 -/* Minimal supported DPRC Version */
--#define DPRC_MIN_VER_MAJOR			6
+-#define DPRC_MIN_VER_MAJOR			5
 -#define DPRC_MIN_VER_MINOR			0
 -
--/* Command versioning */
--#define DPRC_CMD_BASE_VERSION			1
--#define DPRC_CMD_ID_OFFSET			4
--
--#define DPRC_CMD(id)	(((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION)
--
 -/* Command IDs */
--#define DPRC_CMDID_CLOSE                        DPRC_CMD(0x800)
--#define DPRC_CMDID_OPEN                         DPRC_CMD(0x805)
--#define DPRC_CMDID_GET_API_VERSION              DPRC_CMD(0xa05)
+-#define DPRC_CMDID_CLOSE			0x800
+-#define DPRC_CMDID_OPEN				0x805
+-#define DPRC_CMDID_CREATE			0x905
 -
--#define DPRC_CMDID_GET_ATTR                     DPRC_CMD(0x004)
+-#define DPRC_CMDID_GET_ATTR			0x004
+-#define DPRC_CMDID_RESET_CONT			0x005
 -
--#define DPRC_CMDID_SET_IRQ                      DPRC_CMD(0x010)
--#define DPRC_CMDID_GET_IRQ                      DPRC_CMD(0x011)
--#define DPRC_CMDID_SET_IRQ_ENABLE               DPRC_CMD(0x012)
--#define DPRC_CMDID_GET_IRQ_ENABLE               DPRC_CMD(0x013)
--#define DPRC_CMDID_SET_IRQ_MASK                 DPRC_CMD(0x014)
--#define DPRC_CMDID_GET_IRQ_MASK                 DPRC_CMD(0x015)
--#define DPRC_CMDID_GET_IRQ_STATUS               DPRC_CMD(0x016)
--#define DPRC_CMDID_CLEAR_IRQ_STATUS             DPRC_CMD(0x017)
+-#define DPRC_CMDID_SET_IRQ			0x010
+-#define DPRC_CMDID_GET_IRQ			0x011
+-#define DPRC_CMDID_SET_IRQ_ENABLE		0x012
+-#define DPRC_CMDID_GET_IRQ_ENABLE		0x013
+-#define DPRC_CMDID_SET_IRQ_MASK			0x014
+-#define DPRC_CMDID_GET_IRQ_MASK			0x015
+-#define DPRC_CMDID_GET_IRQ_STATUS		0x016
+-#define DPRC_CMDID_CLEAR_IRQ_STATUS		0x017
 -
--#define DPRC_CMDID_GET_CONT_ID                  DPRC_CMD(0x830)
--#define DPRC_CMDID_GET_OBJ_COUNT                DPRC_CMD(0x159)
--#define DPRC_CMDID_GET_OBJ                      DPRC_CMD(0x15A)
--#define DPRC_CMDID_GET_RES_COUNT                DPRC_CMD(0x15B)
--#define DPRC_CMDID_GET_OBJ_REG                  DPRC_CMD(0x15E)
--#define DPRC_CMDID_SET_OBJ_IRQ                  DPRC_CMD(0x15F)
--#define DPRC_CMDID_GET_OBJ_IRQ                  DPRC_CMD(0x160)
+-#define DPRC_CMDID_CREATE_CONT			0x151
+-#define DPRC_CMDID_DESTROY_CONT			0x152
+-#define DPRC_CMDID_SET_RES_QUOTA		0x155
+-#define DPRC_CMDID_GET_RES_QUOTA		0x156
+-#define DPRC_CMDID_ASSIGN			0x157
+-#define DPRC_CMDID_UNASSIGN			0x158
+-#define DPRC_CMDID_GET_OBJ_COUNT		0x159
+-#define DPRC_CMDID_GET_OBJ			0x15A
+-#define DPRC_CMDID_GET_RES_COUNT		0x15B
+-#define DPRC_CMDID_GET_RES_IDS			0x15C
+-#define DPRC_CMDID_GET_OBJ_REG			0x15E
+-#define DPRC_CMDID_SET_OBJ_IRQ			0x15F
+-#define DPRC_CMDID_GET_OBJ_IRQ			0x160
+-#define DPRC_CMDID_SET_OBJ_LABEL		0x161
+-#define DPRC_CMDID_GET_OBJ_DESC			0x162
+-
+-#define DPRC_CMDID_CONNECT			0x167
+-#define DPRC_CMDID_DISCONNECT			0x168
+-#define DPRC_CMDID_GET_POOL			0x169
+-#define DPRC_CMDID_GET_POOL_COUNT		0x16A
+-
+-#define DPRC_CMDID_GET_CONNECTION		0x16C
 -
 -struct dprc_cmd_open {
 -	__le32 container_id;
@@ -10461,6 +14484,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	/* response word 1 */
 -	__le32 options;
 -	__le32 portal_id;
+-	/* response word 2 */
+-	__le16 version_major;
+-	__le16 version_minor;
 -};
 -
 -struct dprc_cmd_set_res_quota {
@@ -10722,11 +14748,3164 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -};
 -
 -#endif /* _FSL_DPRC_CMD_H */
---- a/drivers/staging/fsl-mc/bus/dprc.h
+--- a/drivers/staging/fsl-mc/bus/dprc.c
 +++ /dev/null
-@@ -1,268 +0,0 @@
+@@ -1,1388 +0,0 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#include "../include/mc-sys.h"
+-#include "../include/mc-cmd.h"
+-#include "../include/dprc.h"
+-
+-#include "dprc-cmd.h"
+-
+-/**
+- * dprc_open() - Open DPRC object for use
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @container_id: Container ID to open
+- * @token:	Returned token of DPRC object
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- *
+- * @warning	Required before any operation on the object.
+- */
+-int dprc_open(struct fsl_mc_io *mc_io,
+-	      u32 cmd_flags,
+-	      int container_id,
+-	      u16 *token)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_open *cmd_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags,
+-					  0);
+-	cmd_params = (struct dprc_cmd_open *)cmd.params;
+-	cmd_params->container_id = cpu_to_le32(container_id);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	*token = mc_cmd_hdr_read_token(&cmd);
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(dprc_open);
+-
+-/**
+- * dprc_close() - Close the control session of the object
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- *
+- * After this function is called, no further operations are
+- * allowed on the object without opening a new control session.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_close(struct fsl_mc_io *mc_io,
+-	       u32 cmd_flags,
+-	       u16 token)
+-{
+-	struct mc_command cmd = { 0 };
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLOSE, cmd_flags,
+-					  token);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-EXPORT_SYMBOL(dprc_close);
+-
+-/**
+- * dprc_create_container() - Create child container
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @cfg:	Child container configuration
+- * @child_container_id:	Returned child container ID
+- * @child_portal_offset: Returned child portal offset from MC portal base
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_create_container(struct fsl_mc_io *mc_io,
+-			  u32 cmd_flags,
+-			  u16 token,
+-			  struct dprc_cfg *cfg,
+-			  int *child_container_id,
+-			  u64 *child_portal_offset)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_create_container *cmd_params;
+-	struct dprc_rsp_create_container *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd_params = (struct dprc_cmd_create_container *)cmd.params;
+-	cmd_params->options = cpu_to_le32(cfg->options);
+-	cmd_params->icid = cpu_to_le16(cfg->icid);
+-	cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
+-	strncpy(cmd_params->label, cfg->label, 16);
+-	cmd_params->label[15] = '\0';
+-
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_create_container *)cmd.params;
+-	*child_container_id = le32_to_cpu(rsp_params->child_container_id);
+-	*child_portal_offset = le64_to_cpu(rsp_params->child_portal_addr);
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_destroy_container() - Destroy child container.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @child_container_id:	ID of the container to destroy
+- *
+- * This function terminates the child container, so following this call the
+- * child container ID becomes invalid.
+- *
+- * Notes:
+- * - All resources and objects of the destroyed container are returned to the
+- * parent container or destroyed if were created be the destroyed container.
+- * - This function destroy all the child containers of the specified
+- *   container prior to destroying the container itself.
+- *
+- * warning: Only the parent container is allowed to destroy a child policy
+- *		Container 0 can't be destroyed
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- *
+- */
+-int dprc_destroy_container(struct fsl_mc_io *mc_io,
+-			   u32 cmd_flags,
+-			   u16 token,
+-			   int child_container_id)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_destroy_container *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_destroy_container *)cmd.params;
+-	cmd_params->child_container_id = cpu_to_le32(child_container_id);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_reset_container - Reset child container.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @child_container_id:	ID of the container to reset
+- *
+- * In case a software context crashes or becomes non-responsive, the parent
+- * may wish to reset its resources container before the software context is
+- * restarted.
+- *
+- * This routine informs all objects assigned to the child container that the
+- * container is being reset, so they may perform any cleanup operations that are
+- * needed. All objects handles that were owned by the child container shall be
+- * closed.
+- *
+- * Note that such request may be submitted even if the child software context
+- * has not crashed, but the resulting object cleanup operations will not be
+- * aware of that.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_reset_container(struct fsl_mc_io *mc_io,
+-			 u32 cmd_flags,
+-			 u16 token,
+-			 int child_container_id)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_reset_container *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_reset_container *)cmd.params;
+-	cmd_params->child_container_id = cpu_to_le32(child_container_id);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_get_irq() - Get IRQ information from the DPRC.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @irq_index:	The interrupt index to configure
+- * @type:	Interrupt type: 0 represents message interrupt
+- *		type (both irq_addr and irq_val are valid)
+- * @irq_cfg:	IRQ attributes
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_irq(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token,
+-		 u8 irq_index,
+-		 int *type,
+-		 struct dprc_irq_cfg *irq_cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_irq *cmd_params;
+-	struct dprc_rsp_get_irq *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_get_irq *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_irq *)cmd.params;
+-	irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
+-	irq_cfg->paddr = le64_to_cpu(rsp_params->irq_addr);
+-	irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
+-	*type = le32_to_cpu(rsp_params->type);
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_set_irq() - Set IRQ information for the DPRC to trigger an interrupt.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @irq_index:	Identifies the interrupt index to configure
+- * @irq_cfg:	IRQ configuration
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_set_irq(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token,
+-		 u8 irq_index,
+-		 struct dprc_irq_cfg *irq_cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_set_irq *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_set_irq *)cmd.params;
+-	cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
+-	cmd_params->irq_index = irq_index;
+-	cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
+-	cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_get_irq_enable() - Get overall interrupt state.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @irq_index:  The interrupt index to configure
+- * @en:		Returned interrupt state - enable = 1, disable = 0
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			u8 irq_index,
+-			u8 *en)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_irq_enable *cmd_params;
+-	struct dprc_rsp_get_irq_enable *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_ENABLE,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_get_irq_enable *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_irq_enable *)cmd.params;
+-	*en = rsp_params->enabled & DPRC_ENABLE;
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_set_irq_enable() - Set overall interrupt state.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @irq_index:	The interrupt index to configure
+- * @en:		Interrupt state - enable = 1, disable = 0
+- *
+- * Allows GPP software to control when interrupts are generated.
+- * Each interrupt can have up to 32 causes.  The enable/disable control's the
+- * overall interrupt state. if the interrupt is disabled no causes will cause
+- * an interrupt.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			u8 irq_index,
+-			u8 en)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_set_irq_enable *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_ENABLE,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_set_irq_enable *)cmd.params;
+-	cmd_params->enable = en & DPRC_ENABLE;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_get_irq_mask() - Get interrupt mask.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @irq_index:	The interrupt index to configure
+- * @mask:	Returned event mask to trigger interrupt
+- *
+- * Every interrupt can have up to 32 causes and the interrupt model supports
+- * masking/unmasking each cause independently
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
+-		      u32 cmd_flags,
+-		      u16 token,
+-		      u8 irq_index,
+-		      u32 *mask)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_irq_mask *cmd_params;
+-	struct dprc_rsp_get_irq_mask *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_MASK,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_get_irq_mask *)cmd.params;
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_irq_mask *)cmd.params;
+-	*mask = le32_to_cpu(rsp_params->mask);
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_set_irq_mask() - Set interrupt mask.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @irq_index:	The interrupt index to configure
+- * @mask:	event mask to trigger interrupt;
+- *			each bit:
+- *				0 = ignore event
+- *				1 = consider event for asserting irq
+- *
+- * Every interrupt can have up to 32 causes and the interrupt model supports
+- * masking/unmasking each cause independently
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
+-		      u32 cmd_flags,
+-		      u16 token,
+-		      u8 irq_index,
+-		      u32 mask)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_set_irq_mask *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_IRQ_MASK,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_set_irq_mask *)cmd.params;
+-	cmd_params->mask = cpu_to_le32(mask);
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_get_irq_status() - Get the current status of any pending interrupts.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @irq_index:	The interrupt index to configure
+- * @status:	Returned interrupts status - one bit per cause:
+- *			0 = no interrupt pending
+- *			1 = interrupt pending
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_irq_status(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			u8 irq_index,
+-			u32 *status)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_irq_status *cmd_params;
+-	struct dprc_rsp_get_irq_status *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_IRQ_STATUS,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_get_irq_status *)cmd.params;
+-	cmd_params->status = cpu_to_le32(*status);
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_irq_status *)cmd.params;
+-	*status = le32_to_cpu(rsp_params->status);
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_clear_irq_status() - Clear a pending interrupt's status
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @irq_index:	The interrupt index to configure
+- * @status:	bits to clear (W1C) - one bit per cause:
+- *					0 = don't change
+- *					1 = clear status bit
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
+-			  u32 cmd_flags,
+-			  u16 token,
+-			  u8 irq_index,
+-			  u32 status)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_clear_irq_status *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CLEAR_IRQ_STATUS,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_clear_irq_status *)cmd.params;
+-	cmd_params->status = cpu_to_le32(status);
+-	cmd_params->irq_index = irq_index;
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_get_attributes() - Obtains container attributes
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @attributes	Returned container attributes
+- *
+- * Return:     '0' on Success; Error code otherwise.
+- */
+-int dprc_get_attributes(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			struct dprc_attributes *attr)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_rsp_get_attributes *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR,
+-					  cmd_flags,
+-					  token);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_attributes *)cmd.params;
+-	attr->container_id = le32_to_cpu(rsp_params->container_id);
+-	attr->icid = le16_to_cpu(rsp_params->icid);
+-	attr->options = le32_to_cpu(rsp_params->options);
+-	attr->portal_id = le32_to_cpu(rsp_params->portal_id);
+-	attr->version.major = le16_to_cpu(rsp_params->version_major);
+-	attr->version.minor = le16_to_cpu(rsp_params->version_minor);
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_set_res_quota() - Set allocation policy for a specific resource/object
+- *		type in a child container
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @child_container_id:	ID of the child container
+- * @type:	Resource/object type
+- * @quota:	Sets the maximum number of resources of	the selected type
+- *		that the child container is allowed to allocate from its parent;
+- *		when quota is set to -1, the policy is the same as container's
+- *		general policy.
+- *
+- * Allocation policy determines whether or not a container may allocate
+- * resources from its parent. Each container has a 'global' allocation policy
+- * that is set when the container is created.
+- *
+- * This function sets allocation policy for a specific resource type.
+- * The default policy for all resource types matches the container's 'global'
+- * allocation policy.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- *
+- * @warning	Only the parent container is allowed to change a child policy.
+- */
+-int dprc_set_res_quota(struct fsl_mc_io *mc_io,
+-		       u32 cmd_flags,
+-		       u16 token,
+-		       int child_container_id,
+-		       char *type,
+-		       u16 quota)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_set_res_quota *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_RES_QUOTA,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_set_res_quota *)cmd.params;
+-	cmd_params->child_container_id = cpu_to_le32(child_container_id);
+-	cmd_params->quota = cpu_to_le16(quota);
+-	strncpy(cmd_params->type, type, 16);
+-	cmd_params->type[15] = '\0';
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_get_res_quota() - Gets the allocation policy of a specific
+- *		resource/object type in a child container
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @child_container_id;	ID of the child container
+- * @type:	resource/object type
+- * @quota:	Returnes the maximum number of resources of the selected type
+- *		that the child container is allowed to allocate from the parent;
+- *		when quota is set to -1, the policy is the same as container's
+- *		general policy.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_res_quota(struct fsl_mc_io *mc_io,
+-		       u32 cmd_flags,
+-		       u16 token,
+-		       int child_container_id,
+-		       char *type,
+-		       u16 *quota)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_res_quota *cmd_params;
+-	struct dprc_rsp_get_res_quota *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_QUOTA,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_get_res_quota *)cmd.params;
+-	cmd_params->child_container_id = cpu_to_le32(child_container_id);
+-	strncpy(cmd_params->type, type, 16);
+-	cmd_params->type[15] = '\0';
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_res_quota *)cmd.params;
+-	*quota = le16_to_cpu(rsp_params->quota);
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_assign() - Assigns objects or resource to a child container.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @container_id: ID of the child container
+- * @res_req:	Describes the type and amount of resources to
+- *			assign to the given container
+- *
+- * Assignment is usually done by a parent (this DPRC) to one of its child
+- * containers.
+- *
+- * According to the DPRC allocation policy, the assigned resources may be taken
+- * (allocated) from the container's ancestors, if not enough resources are
+- * available in the container itself.
+- *
+- * The type of assignment depends on the dprc_res_req options, as follows:
+- * - DPRC_RES_REQ_OPT_EXPLICIT: indicates that assigned resources should have
+- *   the explicit base ID specified at the id_base_align field of res_req.
+- * - DPRC_RES_REQ_OPT_ALIGNED: indicates that the assigned resources should be
+- *   aligned to the value given at id_base_align field of res_req.
+- * - DPRC_RES_REQ_OPT_PLUGGED: Relevant only for object assignment,
+- *   and indicates that the object must be set to the plugged state.
+- *
+- * A container may use this function with its own ID in order to change a
+- * object state to plugged or unplugged.
+- *
+- * If IRQ information has been set in the child DPRC, it will signal an
+- * interrupt following every change in its object assignment.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_assign(struct fsl_mc_io *mc_io,
+-		u32 cmd_flags,
+-		u16 token,
+-		int container_id,
+-		struct dprc_res_req *res_req)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_assign *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_ASSIGN,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_assign *)cmd.params;
+-	cmd_params->container_id = cpu_to_le32(container_id);
+-	cmd_params->options = cpu_to_le32(res_req->options);
+-	cmd_params->num = cpu_to_le32(res_req->num);
+-	cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
+-	strncpy(cmd_params->type, res_req->type, 16);
+-	cmd_params->type[15] = '\0';
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_unassign() - Un-assigns objects or resources from a child container
+- *		and moves them into this (parent) DPRC.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @child_container_id:	ID of the child container
+- * @res_req:	Describes the type and amount of resources to un-assign from
+- *		the child container
+- *
+- * Un-assignment of objects can succeed only if the object is not in the
+- * plugged or opened state.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_unassign(struct fsl_mc_io *mc_io,
+-		  u32 cmd_flags,
+-		  u16 token,
+-		  int child_container_id,
+-		  struct dprc_res_req *res_req)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_unassign *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_UNASSIGN,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_unassign *)cmd.params;
+-	cmd_params->child_container_id = cpu_to_le32(child_container_id);
+-	cmd_params->options = cpu_to_le32(res_req->options);
+-	cmd_params->num = cpu_to_le32(res_req->num);
+-	cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
+-	strncpy(cmd_params->type, res_req->type, 16);
+-	cmd_params->type[15] = '\0';
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_get_pool_count() - Get the number of dprc's pools
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @token:	Token of DPRC object
+- * @pool_count:	Returned number of resource pools in the dprc
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_pool_count(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			int *pool_count)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_rsp_get_pool_count *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL_COUNT,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_pool_count *)cmd.params;
+-	*pool_count = le32_to_cpu(rsp_params->pool_count);
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_get_pool() - Get the type (string) of a certain dprc's pool
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @pool_index;	Index of the pool to be queried (< pool_count)
+- * @type:	The type of the pool
+- *
+- * The pool types retrieved one by one by incrementing
+- * pool_index up to (not including) the value of pool_count returned
+- * from dprc_get_pool_count(). dprc_get_pool_count() must
+- * be called prior to dprc_get_pool().
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_pool(struct fsl_mc_io *mc_io,
+-		  u32 cmd_flags,
+-		  u16 token,
+-		  int pool_index,
+-		  char *type)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_pool *cmd_params;
+-	struct dprc_rsp_get_pool *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_get_pool *)cmd.params;
+-	cmd_params->pool_index = cpu_to_le32(pool_index);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_pool *)cmd.params;
+-	strncpy(type, rsp_params->type, 16);
+-	type[15] = '\0';
+-
+-	return 0;
+-}
+-
+-/**
+- * dprc_get_obj_count() - Obtains the number of objects in the DPRC
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @obj_count:	Number of objects assigned to the DPRC
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_obj_count(struct fsl_mc_io *mc_io,
+-		       u32 cmd_flags,
+-		       u16 token,
+-		       int *obj_count)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_rsp_get_obj_count *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT,
+-					  cmd_flags, token);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_obj_count *)cmd.params;
+-	*obj_count = le32_to_cpu(rsp_params->obj_count);
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(dprc_get_obj_count);
+-
+-/**
+- * dprc_get_obj() - Get general information on an object
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @obj_index:	Index of the object to be queried (< obj_count)
+- * @obj_desc:	Returns the requested object descriptor
+- *
+- * The object descriptors are retrieved one by one by incrementing
+- * obj_index up to (not including) the value of obj_count returned
+- * from dprc_get_obj_count(). dprc_get_obj_count() must
+- * be called prior to dprc_get_obj().
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_obj(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token,
+-		 int obj_index,
+-		 struct dprc_obj_desc *obj_desc)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_obj *cmd_params;
+-	struct dprc_rsp_get_obj *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_get_obj *)cmd.params;
+-	cmd_params->obj_index = cpu_to_le32(obj_index);
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_obj *)cmd.params;
+-	obj_desc->id = le32_to_cpu(rsp_params->id);
+-	obj_desc->vendor = le16_to_cpu(rsp_params->vendor);
+-	obj_desc->irq_count = rsp_params->irq_count;
+-	obj_desc->region_count = rsp_params->region_count;
+-	obj_desc->state = le32_to_cpu(rsp_params->state);
+-	obj_desc->ver_major = le16_to_cpu(rsp_params->version_major);
+-	obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor);
+-	obj_desc->flags = le16_to_cpu(rsp_params->flags);
+-	strncpy(obj_desc->type, rsp_params->type, 16);
+-	obj_desc->type[15] = '\0';
+-	strncpy(obj_desc->label, rsp_params->label, 16);
+-	obj_desc->label[15] = '\0';
+-	return 0;
+-}
+-EXPORT_SYMBOL(dprc_get_obj);
+-
+-/**
+- * dprc_get_obj_desc() - Get object descriptor.
+- *
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @obj_type:	The type of the object to get its descriptor.
+- * @obj_id:	The id of the object to get its descriptor
+- * @obj_desc:	The returned descriptor to fill and return to the user
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- *
+- */
+-int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
+-		      u32 cmd_flags,
+-		      u16 token,
+-		      char *obj_type,
+-		      int obj_id,
+-		      struct dprc_obj_desc *obj_desc)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_obj_desc *cmd_params;
+-	struct dprc_rsp_get_obj_desc *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_DESC,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_get_obj_desc *)cmd.params;
+-	cmd_params->obj_id = cpu_to_le32(obj_id);
+-	strncpy(cmd_params->type, obj_type, 16);
+-	cmd_params->type[15] = '\0';
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_obj_desc *)cmd.params;
+-	obj_desc->id = le32_to_cpu(rsp_params->id);
+-	obj_desc->vendor = le16_to_cpu(rsp_params->vendor);
+-	obj_desc->irq_count = rsp_params->irq_count;
+-	obj_desc->region_count = rsp_params->region_count;
+-	obj_desc->state = le32_to_cpu(rsp_params->state);
+-	obj_desc->ver_major = le16_to_cpu(rsp_params->version_major);
+-	obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor);
+-	obj_desc->flags = le16_to_cpu(rsp_params->flags);
+-	strncpy(obj_desc->type, rsp_params->type, 16);
+-	obj_desc->type[15] = '\0';
+-	strncpy(obj_desc->label, rsp_params->label, 16);
+-	obj_desc->label[15] = '\0';
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(dprc_get_obj_desc);
+-
+-/**
+- * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @obj_type:	Type of the object to set its IRQ
+- * @obj_id:	ID of the object to set its IRQ
+- * @irq_index:	The interrupt index to configure
+- * @irq_cfg:	IRQ configuration
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
+-		     u32 cmd_flags,
+-		     u16 token,
+-		     char *obj_type,
+-		     int obj_id,
+-		     u8 irq_index,
+-		     struct dprc_irq_cfg *irq_cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_set_obj_irq *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_IRQ,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_set_obj_irq *)cmd.params;
+-	cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
+-	cmd_params->irq_index = irq_index;
+-	cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
+-	cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
+-	cmd_params->obj_id = cpu_to_le32(obj_id);
+-	strncpy(cmd_params->obj_type, obj_type, 16);
+-	cmd_params->obj_type[15] = '\0';
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-EXPORT_SYMBOL(dprc_set_obj_irq);
+-
+-/**
+- * dprc_get_obj_irq() - Get IRQ information from object.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @obj_type:	Type od the object to get its IRQ
+- * @obj_id:	ID of the object to get its IRQ
+- * @irq_index:	The interrupt index to configure
+- * @type:	Interrupt type: 0 represents message interrupt
+- *		type (both irq_addr and irq_val are valid)
+- * @irq_cfg:	The returned IRQ attributes
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
+-		     u32 cmd_flags,
+-		     u16 token,
+-		     char *obj_type,
+-		     int obj_id,
+-		     u8 irq_index,
+-		     int *type,
+-		     struct dprc_irq_cfg *irq_cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_obj_irq *cmd_params;
+-	struct dprc_rsp_get_obj_irq *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_IRQ,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_get_obj_irq *)cmd.params;
+-	cmd_params->obj_id = cpu_to_le32(obj_id);
+-	cmd_params->irq_index = irq_index;
+-	strncpy(cmd_params->obj_type, obj_type, 16);
+-	cmd_params->obj_type[15] = '\0';
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_obj_irq *)cmd.params;
+-	irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
+-	irq_cfg->paddr = le64_to_cpu(rsp_params->irq_addr);
+-	irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
+-	*type = le32_to_cpu(rsp_params->type);
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(dprc_get_obj_irq);
+-
+-/**
+- * dprc_get_res_count() - Obtains the number of free resources that are assigned
+- *		to this container, by pool type
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @type:	pool type
+- * @res_count:	Returned number of free resources of the given
+- *			resource type that are assigned to this DPRC
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_res_count(struct fsl_mc_io *mc_io,
+-		       u32 cmd_flags,
+-		       u16 token,
+-		       char *type,
+-		       int *res_count)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_res_count *cmd_params;
+-	struct dprc_rsp_get_res_count *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_COUNT,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_get_res_count *)cmd.params;
+-	strncpy(cmd_params->type, type, 16);
+-	cmd_params->type[15] = '\0';
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_res_count *)cmd.params;
+-	*res_count = le32_to_cpu(rsp_params->res_count);
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(dprc_get_res_count);
+-
+-/**
+- * dprc_get_res_ids() - Obtains IDs of free resources in the container
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @type:	pool type
+- * @range_desc:	range descriptor
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_res_ids(struct fsl_mc_io *mc_io,
+-		     u32 cmd_flags,
+-		     u16 token,
+-		     char *type,
+-		     struct dprc_res_ids_range_desc *range_desc)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_res_ids *cmd_params;
+-	struct dprc_rsp_get_res_ids *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_get_res_ids *)cmd.params;
+-	cmd_params->iter_status = range_desc->iter_status;
+-	cmd_params->base_id = cpu_to_le32(range_desc->base_id);
+-	cmd_params->last_id = cpu_to_le32(range_desc->last_id);
+-	strncpy(cmd_params->type, type, 16);
+-	cmd_params->type[15] = '\0';
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_res_ids *)cmd.params;
+-	range_desc->iter_status = rsp_params->iter_status;
+-	range_desc->base_id = le32_to_cpu(rsp_params->base_id);
+-	range_desc->last_id = le32_to_cpu(rsp_params->last_id);
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(dprc_get_res_ids);
+-
+-/**
+- * dprc_get_obj_region() - Get region information for a specified object.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @obj_type;	Object type as returned in dprc_get_obj()
+- * @obj_id:	Unique object instance as returned in dprc_get_obj()
+- * @region_index: The specific region to query
+- * @region_desc:  Returns the requested region descriptor
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_get_obj_region(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			char *obj_type,
+-			int obj_id,
+-			u8 region_index,
+-			struct dprc_region_desc *region_desc)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_obj_region *cmd_params;
+-	struct dprc_rsp_get_obj_region *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG,
+-					  cmd_flags, token);
+-	cmd_params = (struct dprc_cmd_get_obj_region *)cmd.params;
+-	cmd_params->obj_id = cpu_to_le32(obj_id);
+-	cmd_params->region_index = region_index;
+-	strncpy(cmd_params->obj_type, obj_type, 16);
+-	cmd_params->obj_type[15] = '\0';
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params;
+-	region_desc->base_offset = le64_to_cpu(rsp_params->base_addr);
+-	region_desc->size = le32_to_cpu(rsp_params->size);
+-
+-	return 0;
+-}
+-EXPORT_SYMBOL(dprc_get_obj_region);
+-
+-/**
+- * dprc_set_obj_label() - Set object label.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @obj_type:	Object's type
+- * @obj_id:	Object's ID
+- * @label:	The required label. The maximum length is 16 chars.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_set_obj_label(struct fsl_mc_io *mc_io,
+-		       u32 cmd_flags,
+-		       u16  token,
+-		       char *obj_type,
+-		       int  obj_id,
+-		       char *label)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_set_obj_label *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_LABEL,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_set_obj_label *)cmd.params;
+-	cmd_params->obj_id = cpu_to_le32(obj_id);
+-	strncpy(cmd_params->label, label, 16);
+-	cmd_params->label[15] = '\0';
+-	strncpy(cmd_params->obj_type, obj_type, 16);
+-	cmd_params->obj_type[15] = '\0';
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-EXPORT_SYMBOL(dprc_set_obj_label);
+-
+-/**
+- * dprc_connect() - Connect two endpoints to create a network link between them
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @endpoint1:	Endpoint 1 configuration parameters
+- * @endpoint2:	Endpoint 2 configuration parameters
+- * @cfg: Connection configuration. The connection configuration is ignored for
+- *	 connections made to DPMAC objects, where rate is retrieved from the
+- *	 MAC configuration.
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_connect(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token,
+-		 const struct dprc_endpoint *endpoint1,
+-		 const struct dprc_endpoint *endpoint2,
+-		 const struct dprc_connection_cfg *cfg)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_connect *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_connect *)cmd.params;
+-	cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
+-	cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
+-	cmd_params->ep2_id = cpu_to_le32(endpoint2->id);
+-	cmd_params->ep2_interface_id = cpu_to_le32(endpoint2->if_id);
+-	strncpy(cmd_params->ep1_type, endpoint1->type, 16);
+-	cmd_params->ep1_type[15] = '\0';
+-	cmd_params->max_rate = cpu_to_le32(cfg->max_rate);
+-	cmd_params->committed_rate = cpu_to_le32(cfg->committed_rate);
+-	strncpy(cmd_params->ep2_type, endpoint2->type, 16);
+-	cmd_params->ep2_type[15] = '\0';
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_disconnect() - Disconnect one endpoint to remove its network connection
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @endpoint:	Endpoint configuration parameters
+- *
+- * Return:	'0' on Success; Error code otherwise.
+- */
+-int dprc_disconnect(struct fsl_mc_io *mc_io,
+-		    u32 cmd_flags,
+-		    u16 token,
+-		    const struct dprc_endpoint *endpoint)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_disconnect *cmd_params;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_disconnect *)cmd.params;
+-	cmd_params->id = cpu_to_le32(endpoint->id);
+-	cmd_params->interface_id = cpu_to_le32(endpoint->if_id);
+-	strncpy(cmd_params->type, endpoint->type, 16);
+-	cmd_params->type[15] = '\0';
+-
+-	/* send command to mc*/
+-	return mc_send_command(mc_io, &cmd);
+-}
+-
+-/**
+- * dprc_get_connection() - Get connected endpoint and link status if connection
+- *			exists.
+- * @mc_io:	Pointer to MC portal's I/O object
+- * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+- * @token:	Token of DPRC object
+- * @endpoint1:	Endpoint 1 configuration parameters
+- * @endpoint2:	Returned endpoint 2 configuration parameters
+- * @state:	Returned link state:
+- *		1 - link is up;
+- *		0 - link is down;
+- *		-1 - no connection (endpoint2 information is irrelevant)
+- *
+- * Return:     '0' on Success; -ENAVAIL if connection does not exist.
+- */
+-int dprc_get_connection(struct fsl_mc_io *mc_io,
+-			u32 cmd_flags,
+-			u16 token,
+-			const struct dprc_endpoint *endpoint1,
+-			struct dprc_endpoint *endpoint2,
+-			int *state)
+-{
+-	struct mc_command cmd = { 0 };
+-	struct dprc_cmd_get_connection *cmd_params;
+-	struct dprc_rsp_get_connection *rsp_params;
+-	int err;
+-
+-	/* prepare command */
+-	cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION,
+-					  cmd_flags,
+-					  token);
+-	cmd_params = (struct dprc_cmd_get_connection *)cmd.params;
+-	cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
+-	cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
+-	strncpy(cmd_params->ep1_type, endpoint1->type, 16);
+-	cmd_params->ep1_type[15] = '\0';
+-
+-	/* send command to mc*/
+-	err = mc_send_command(mc_io, &cmd);
+-	if (err)
+-		return err;
+-
+-	/* retrieve response parameters */
+-	rsp_params = (struct dprc_rsp_get_connection *)cmd.params;
+-	endpoint2->id = le32_to_cpu(rsp_params->ep2_id);
+-	endpoint2->if_id = le32_to_cpu(rsp_params->ep2_interface_id);
+-	strncpy(endpoint2->type, rsp_params->ep2_type, 16);
+-	endpoint2->type[15] = '\0';
+-	*state = le32_to_cpu(rsp_params->state);
+-
+-	return 0;
+-}
+--- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h
++++ /dev/null
+@@ -1,52 +0,0 @@
 -/*
-- * Copyright 2013-2016 Freescale Semiconductor Inc.
+- * Freescale Management Complex (MC) bus private declarations
+- *
+- * Copyright (C) 2016 Freescale Semiconductor, Inc.
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- */
+-#ifndef _FSL_MC_PRIVATE_H_
+-#define _FSL_MC_PRIVATE_H_
+-
+-int __must_check fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
+-				   struct fsl_mc_io *mc_io,
+-				   struct device *parent_dev,
+-				   struct fsl_mc_device **new_mc_dev);
+-
+-void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
+-
+-int __init dprc_driver_init(void);
+-
+-void dprc_driver_exit(void);
+-
+-int __init fsl_mc_allocator_driver_init(void);
+-
+-void fsl_mc_allocator_driver_exit(void);
+-
+-int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus,
+-					  enum fsl_mc_pool_type pool_type,
+-					  struct fsl_mc_resource
+-							  **new_resource);
+-
+-void fsl_mc_resource_free(struct fsl_mc_resource *resource);
+-
+-int fsl_mc_msi_domain_alloc_irqs(struct device *dev,
+-				 unsigned int irq_count);
+-
+-void fsl_mc_msi_domain_free_irqs(struct device *dev);
+-
+-int __init its_fsl_mc_msi_init(void);
+-
+-void its_fsl_mc_msi_cleanup(void);
+-
+-int __must_check fsl_create_mc_io(struct device *dev,
+-				  phys_addr_t mc_portal_phys_addr,
+-				  u32 mc_portal_size,
+-				  struct fsl_mc_device *dpmcp_dev,
+-				  u32 flags, struct fsl_mc_io **new_mc_io);
+-
+-void fsl_destroy_mc_io(struct fsl_mc_io *mc_io);
+-
+-#endif /* _FSL_MC_PRIVATE_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl-mc/include/dpaa2-fd.h
+@@ -0,0 +1,681 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
++/*
++ * Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ */
++#ifndef __FSL_DPAA2_FD_H
++#define __FSL_DPAA2_FD_H
++
++#include <linux/kernel.h>
++
++/**
++ * DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2
++ *
++ * Frame Descriptors (FDs) are used to describe frame data in the DPAA2.
++ * Frames can be enqueued and dequeued to Frame Queues (FQs) which are consumed
++ * by the various DPAA accelerators (WRIOP, SEC, PME, DCE)
++ *
++ * There are three types of frames: single, scatter gather, and frame lists.
++ *
++ * The set of APIs in this file must be used to create, manipulate and
++ * query Frame Descriptors.
++ */
++
++/**
++ * struct dpaa2_fd - Struct describing FDs
++ * @words:         for easier/faster copying the whole FD structure
++ * @addr:          address in the FD
++ * @len:           length in the FD
++ * @bpid:          buffer pool ID
++ * @format_offset: format, offset, and short-length fields
++ * @frc:           frame context
++ * @ctrl:          control bits...including dd, sc, va, err, etc
++ * @flc:           flow context address
++ *
++ * This structure represents the basic Frame Descriptor used in the system.
++ */
++struct dpaa2_fd {
++	union {
++		u32 words[8];
++		struct dpaa2_fd_simple {
++			__le64 addr;
++			__le32 len;
++			__le16 bpid;
++			__le16 format_offset;
++			__le32 frc;
++			__le32 ctrl;
++			__le64 flc;
++		} simple;
++	};
++};
++
++#define FD_SHORT_LEN_FLAG_MASK	0x1
++#define FD_SHORT_LEN_FLAG_SHIFT	14
++#define FD_SHORT_LEN_MASK	0x3FFFF
++#define FD_OFFSET_MASK		0x0FFF
++#define FD_FORMAT_MASK		0x3
++#define FD_FORMAT_SHIFT		12
++#define FD_BPID_MASK		0x3FFF
++#define SG_SHORT_LEN_FLAG_MASK	0x1
++#define SG_SHORT_LEN_FLAG_SHIFT	14
++#define SG_SHORT_LEN_MASK	0x1FFFF
++#define SG_OFFSET_MASK		0x0FFF
++#define SG_FORMAT_MASK		0x3
++#define SG_FORMAT_SHIFT		12
++#define SG_BPID_MASK		0x3FFF
++#define SG_FINAL_FLAG_MASK	0x1
++#define SG_FINAL_FLAG_SHIFT	15
++#define FL_SHORT_LEN_FLAG_MASK	0x1
++#define FL_SHORT_LEN_FLAG_SHIFT	14
++#define FL_SHORT_LEN_MASK	0x3FFFF
++#define FL_OFFSET_MASK		0x0FFF
++#define FL_FORMAT_MASK		0x3
++#define FL_FORMAT_SHIFT		12
++#define FL_BPID_MASK		0x3FFF
++#define FL_FINAL_FLAG_MASK	0x1
++#define FL_FINAL_FLAG_SHIFT	15
++
++/* Error bits in FD CTRL */
++#define FD_CTRL_ERR_MASK	0x000000FF
++#define FD_CTRL_UFD		0x00000004
++#define FD_CTRL_SBE		0x00000008
++#define FD_CTRL_FLC		0x00000010
++#define FD_CTRL_FSE		0x00000020
++#define FD_CTRL_FAERR		0x00000040
++
++/* Annotation bits in FD CTRL */
++#define FD_CTRL_PTA		0x00800000
++#define FD_CTRL_PTV1		0x00400000
++
++enum dpaa2_fd_format {
++	dpaa2_fd_single = 0,
++	dpaa2_fd_list,
++	dpaa2_fd_sg
++};
++
++/**
++ * dpaa2_fd_get_addr() - get the addr field of frame descriptor
++ * @fd: the given frame descriptor
++ *
++ * Return the address in the frame descriptor.
++ */
++static inline dma_addr_t dpaa2_fd_get_addr(const struct dpaa2_fd *fd)
++{
++	return (dma_addr_t)le64_to_cpu(fd->simple.addr);
++}
++
++/**
++ * dpaa2_fd_set_addr() - Set the addr field of frame descriptor
++ * @fd: the given frame descriptor
++ * @addr: the address needs to be set in frame descriptor
++ */
++static inline void dpaa2_fd_set_addr(struct dpaa2_fd *fd, dma_addr_t addr)
++{
++	fd->simple.addr = cpu_to_le64(addr);
++}
++
++/**
++ * dpaa2_fd_get_frc() - Get the frame context in the frame descriptor
++ * @fd: the given frame descriptor
++ *
++ * Return the frame context field in the frame descriptor.
++ */
++static inline u32 dpaa2_fd_get_frc(const struct dpaa2_fd *fd)
++{
++	return le32_to_cpu(fd->simple.frc);
++}
++
++/**
++ * dpaa2_fd_set_frc() - Set the frame context in the frame descriptor
++ * @fd: the given frame descriptor
++ * @frc: the frame context needs to be set in frame descriptor
++ */
++static inline void dpaa2_fd_set_frc(struct dpaa2_fd *fd, u32 frc)
++{
++	fd->simple.frc = cpu_to_le32(frc);
++}
++
++/**
++ * dpaa2_fd_get_ctrl() - Get the control bits in the frame descriptor
++ * @fd: the given frame descriptor
++ *
++ * Return the control bits field in the frame descriptor.
++ */
++static inline u32 dpaa2_fd_get_ctrl(const struct dpaa2_fd *fd)
++{
++	return le32_to_cpu(fd->simple.ctrl);
++}
++
++/**
++ * dpaa2_fd_set_ctrl() - Set the control bits in the frame descriptor
++ * @fd: the given frame descriptor
++ * @ctrl: the control bits to be set in the frame descriptor
++ */
++static inline void dpaa2_fd_set_ctrl(struct dpaa2_fd *fd, u32 ctrl)
++{
++	fd->simple.ctrl = cpu_to_le32(ctrl);
++}
++
++/**
++ * dpaa2_fd_get_flc() - Get the flow context in the frame descriptor
++ * @fd: the given frame descriptor
++ *
++ * Return the flow context in the frame descriptor.
++ */
++static inline dma_addr_t dpaa2_fd_get_flc(const struct dpaa2_fd *fd)
++{
++	return (dma_addr_t)le64_to_cpu(fd->simple.flc);
++}
++
++/**
++ * dpaa2_fd_set_flc() - Set the flow context field of frame descriptor
++ * @fd: the given frame descriptor
++ * @flc_addr: the flow context needs to be set in frame descriptor
++ */
++static inline void dpaa2_fd_set_flc(struct dpaa2_fd *fd,  dma_addr_t flc_addr)
++{
++	fd->simple.flc = cpu_to_le64(flc_addr);
++}
++
++static inline bool dpaa2_fd_short_len(const struct dpaa2_fd *fd)
++{
++	return !!((le16_to_cpu(fd->simple.format_offset) >>
++		  FD_SHORT_LEN_FLAG_SHIFT) & FD_SHORT_LEN_FLAG_MASK);
++}
++
++/**
++ * dpaa2_fd_get_len() - Get the length in the frame descriptor
++ * @fd: the given frame descriptor
++ *
++ * Return the length field in the frame descriptor.
++ */
++static inline u32 dpaa2_fd_get_len(const struct dpaa2_fd *fd)
++{
++	if (dpaa2_fd_short_len(fd))
++		return le32_to_cpu(fd->simple.len) & FD_SHORT_LEN_MASK;
++
++	return le32_to_cpu(fd->simple.len);
++}
++
++/**
++ * dpaa2_fd_set_len() - Set the length field of frame descriptor
++ * @fd: the given frame descriptor
++ * @len: the length needs to be set in frame descriptor
++ */
++static inline void dpaa2_fd_set_len(struct dpaa2_fd *fd, u32 len)
++{
++	fd->simple.len = cpu_to_le32(len);
++}
++
++/**
++ * dpaa2_fd_get_offset() - Get the offset field in the frame descriptor
++ * @fd: the given frame descriptor
++ *
++ * Return the offset.
++ */
++static inline uint16_t dpaa2_fd_get_offset(const struct dpaa2_fd *fd)
++{
++	return le16_to_cpu(fd->simple.format_offset) & FD_OFFSET_MASK;
++}
++
++/**
++ * dpaa2_fd_set_offset() - Set the offset field of frame descriptor
++ * @fd: the given frame descriptor
++ * @offset: the offset needs to be set in frame descriptor
++ */
++static inline void dpaa2_fd_set_offset(struct dpaa2_fd *fd, uint16_t offset)
++{
++	fd->simple.format_offset &= cpu_to_le16(~FD_OFFSET_MASK);
++	fd->simple.format_offset |= cpu_to_le16(offset);
++}
++
++/**
++ * dpaa2_fd_get_format() - Get the format field in the frame descriptor
++ * @fd: the given frame descriptor
++ *
++ * Return the format.
++ */
++static inline enum dpaa2_fd_format dpaa2_fd_get_format(
++						const struct dpaa2_fd *fd)
++{
++	return (enum dpaa2_fd_format)((le16_to_cpu(fd->simple.format_offset)
++				      >> FD_FORMAT_SHIFT) & FD_FORMAT_MASK);
++}
++
++/**
++ * dpaa2_fd_set_format() - Set the format field of frame descriptor
++ * @fd: the given frame descriptor
++ * @format: the format needs to be set in frame descriptor
++ */
++static inline void dpaa2_fd_set_format(struct dpaa2_fd *fd,
++				       enum dpaa2_fd_format format)
++{
++	fd->simple.format_offset &=
++		cpu_to_le16(~(FD_FORMAT_MASK << FD_FORMAT_SHIFT));
++	fd->simple.format_offset |= cpu_to_le16(format << FD_FORMAT_SHIFT);
++}
++
++/**
++ * dpaa2_fd_get_bpid() - Get the bpid field in the frame descriptor
++ * @fd: the given frame descriptor
++ *
++ * Return the buffer pool id.
++ */
++static inline uint16_t dpaa2_fd_get_bpid(const struct dpaa2_fd *fd)
++{
++	return le16_to_cpu(fd->simple.bpid) & FD_BPID_MASK;
++}
++
++/**
++ * dpaa2_fd_set_bpid() - Set the bpid field of frame descriptor
++ * @fd: the given frame descriptor
++ * @bpid: buffer pool id to be set
++ */
++static inline void dpaa2_fd_set_bpid(struct dpaa2_fd *fd, uint16_t bpid)
++{
++	fd->simple.bpid &= cpu_to_le16(~(FD_BPID_MASK));
++	fd->simple.bpid |= cpu_to_le16(bpid);
++}
++
++/**
++ * struct dpaa2_sg_entry - the scatter-gathering structure
++ * @addr: address of the sg entry
++ * @len: length in this sg entry
++ * @bpid: buffer pool id
++ * @format_offset: format and offset fields
++ */
++struct dpaa2_sg_entry {
++	__le64 addr;
++	__le32 len;
++	__le16 bpid;
++	__le16 format_offset;
++};
++
++enum dpaa2_sg_format {
++	dpaa2_sg_single = 0,
++	dpaa2_sg_frame_data,
++	dpaa2_sg_sgt_ext
++};
++
++/* Accessors for SG entry fields */
++
++/**
++ * dpaa2_sg_get_addr() - Get the address from SG entry
++ * @sg: the given scatter-gathering object
++ *
++ * Return the address.
++ */
++static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
++{
++	return (dma_addr_t)le64_to_cpu(sg->addr);
++}
++
++/**
++ * dpaa2_sg_set_addr() - Set the address in SG entry
++ * @sg: the given scatter-gathering object
++ * @addr: the address to be set
++ */
++static inline void dpaa2_sg_set_addr(struct dpaa2_sg_entry *sg, dma_addr_t addr)
++{
++	sg->addr = cpu_to_le64(addr);
++}
++
++static inline bool dpaa2_sg_short_len(const struct dpaa2_sg_entry *sg)
++{
++	return !!((le16_to_cpu(sg->format_offset) >> SG_SHORT_LEN_FLAG_SHIFT)
++		& SG_SHORT_LEN_FLAG_MASK);
++}
++
++/**
++ * dpaa2_sg_get_len() - Get the length in SG entry
++ * @sg: the given scatter-gathering object
++ *
++ * Return the length.
++ */
++static inline u32 dpaa2_sg_get_len(const struct dpaa2_sg_entry *sg)
++{
++	if (dpaa2_sg_short_len(sg))
++		return le32_to_cpu(sg->len) & SG_SHORT_LEN_MASK;
++
++	return le32_to_cpu(sg->len);
++}
++
++/**
++ * dpaa2_sg_set_len() - Set the length in SG entry
++ * @sg: the given scatter-gathering object
++ * @len: the length to be set
++ */
++static inline void dpaa2_sg_set_len(struct dpaa2_sg_entry *sg, u32 len)
++{
++	sg->len = cpu_to_le32(len);
++}
++
++/**
++ * dpaa2_sg_get_offset() - Get the offset in SG entry
++ * @sg: the given scatter-gathering object
++ *
++ * Return the offset.
++ */
++static inline u16 dpaa2_sg_get_offset(const struct dpaa2_sg_entry *sg)
++{
++	return le16_to_cpu(sg->format_offset) & SG_OFFSET_MASK;
++}
++
++/**
++ * dpaa2_sg_set_offset() - Set the offset in SG entry
++ * @sg: the given scatter-gathering object
++ * @offset: the offset to be set
++ */
++static inline void dpaa2_sg_set_offset(struct dpaa2_sg_entry *sg,
++				       u16 offset)
++{
++	sg->format_offset &= cpu_to_le16(~SG_OFFSET_MASK);
++	sg->format_offset |= cpu_to_le16(offset);
++}
++
++/**
++ * dpaa2_sg_get_format() - Get the SG format in SG entry
++ * @sg: the given scatter-gathering object
++ *
++ * Return the format.
++ */
++static inline enum dpaa2_sg_format
++	dpaa2_sg_get_format(const struct dpaa2_sg_entry *sg)
++{
++	return (enum dpaa2_sg_format)((le16_to_cpu(sg->format_offset)
++				       >> SG_FORMAT_SHIFT) & SG_FORMAT_MASK);
++}
++
++/**
++ * dpaa2_sg_set_format() - Set the SG format in SG entry
++ * @sg: the given scatter-gathering object
++ * @format: the format to be set
++ */
++static inline void dpaa2_sg_set_format(struct dpaa2_sg_entry *sg,
++				       enum dpaa2_sg_format format)
++{
++	sg->format_offset &= cpu_to_le16(~(SG_FORMAT_MASK << SG_FORMAT_SHIFT));
++	sg->format_offset |= cpu_to_le16(format << SG_FORMAT_SHIFT);
++}
++
++/**
++ * dpaa2_sg_get_bpid() - Get the buffer pool id in SG entry
++ * @sg: the given scatter-gathering object
++ *
++ * Return the bpid.
++ */
++static inline u16 dpaa2_sg_get_bpid(const struct dpaa2_sg_entry *sg)
++{
++	return le16_to_cpu(sg->bpid) & SG_BPID_MASK;
++}
++
++/**
++ * dpaa2_sg_set_bpid() - Set the buffer pool id in SG entry
++ * @sg: the given scatter-gathering object
++ * @bpid: the bpid to be set
++ */
++static inline void dpaa2_sg_set_bpid(struct dpaa2_sg_entry *sg, u16 bpid)
++{
++	sg->bpid &= cpu_to_le16(~(SG_BPID_MASK));
++	sg->bpid |= cpu_to_le16(bpid);
++}
++
++/**
++ * dpaa2_sg_is_final() - Check final bit in SG entry
++ * @sg: the given scatter-gathering object
++ *
++ * Return bool.
++ */
++static inline bool dpaa2_sg_is_final(const struct dpaa2_sg_entry *sg)
++{
++	return !!(le16_to_cpu(sg->format_offset) >> SG_FINAL_FLAG_SHIFT);
++}
++
++/**
++ * dpaa2_sg_set_final() - Set the final bit in SG entry
++ * @sg: the given scatter-gathering object
++ * @final: the final boolean to be set
++ */
++static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
++{
++	sg->format_offset &= cpu_to_le16((~(SG_FINAL_FLAG_MASK
++					 << SG_FINAL_FLAG_SHIFT)) & 0xFFFF);
++	sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
++}
++
++/**
++ * struct dpaa2_fl_entry - structure for frame list entry.
++ * @addr:          address in the FLE
++ * @len:           length in the FLE
++ * @bpid:          buffer pool ID
++ * @format_offset: format, offset, and short-length fields
++ * @frc:           frame context
++ * @ctrl:          control bits...including pta, pvt1, pvt2, err, etc
++ * @flc:           flow context address
++ */
++struct dpaa2_fl_entry {
++	__le64 addr;
++	__le32 len;
++	__le16 bpid;
++	__le16 format_offset;
++	__le32 frc;
++	__le32 ctrl;
++	__le64 flc;
++};
++
++enum dpaa2_fl_format {
++	dpaa2_fl_single = 0,
++	dpaa2_fl_res,
++	dpaa2_fl_sg
++};
++
++/**
++ * dpaa2_fl_get_addr() - get the addr field of FLE
++ * @fle: the given frame list entry
++ *
++ * Return the address in the frame list entry.
++ */
++static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
++{
++	return (dma_addr_t)le64_to_cpu(fle->addr);
++}
++
++/**
++ * dpaa2_fl_set_addr() - Set the addr field of FLE
++ * @fle: the given frame list entry
++ * @addr: the address needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
++				     dma_addr_t addr)
++{
++	fle->addr = cpu_to_le64(addr);
++}
++
++/**
++ * dpaa2_fl_get_frc() - Get the frame context in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the frame context field in the frame lsit entry.
++ */
++static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
++{
++	return le32_to_cpu(fle->frc);
++}
++
++/**
++ * dpaa2_fl_set_frc() - Set the frame context in the FLE
++ * @fle: the given frame list entry
++ * @frc: the frame context needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
++{
++	fle->frc = cpu_to_le32(frc);
++}
++
++/**
++ * dpaa2_fl_get_ctrl() - Get the control bits in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the control bits field in the frame list entry.
++ */
++static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
++{
++	return le32_to_cpu(fle->ctrl);
++}
++
++/**
++ * dpaa2_fl_set_ctrl() - Set the control bits in the FLE
++ * @fle: the given frame list entry
++ * @ctrl: the control bits to be set in the frame list entry
++ */
++static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
++{
++	fle->ctrl = cpu_to_le32(ctrl);
++}
++
++/**
++ * dpaa2_fl_get_flc() - Get the flow context in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the flow context in the frame list entry.
++ */
++static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
++{
++	return (dma_addr_t)le64_to_cpu(fle->flc);
++}
++
++/**
++ * dpaa2_fl_set_flc() - Set the flow context field of FLE
++ * @fle: the given frame list entry
++ * @flc_addr: the flow context needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
++				    dma_addr_t flc_addr)
++{
++	fle->flc = cpu_to_le64(flc_addr);
++}
++
++static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
++{
++	return !!((le16_to_cpu(fle->format_offset) >>
++		  FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
++}
++
++/**
++ * dpaa2_fl_get_len() - Get the length in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the length field in the frame list entry.
++ */
++static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
++{
++	if (dpaa2_fl_short_len(fle))
++		return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
++
++	return le32_to_cpu(fle->len);
++}
++
++/**
++ * dpaa2_fl_set_len() - Set the length field of FLE
++ * @fle: the given frame list entry
++ * @len: the length needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
++{
++	fle->len = cpu_to_le32(len);
++}
++
++/**
++ * dpaa2_fl_get_offset() - Get the offset field in the frame list entry
++ * @fle: the given frame list entry
++ *
++ * Return the offset.
++ */
++static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
++{
++	return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
++}
++
++/**
++ * dpaa2_fl_set_offset() - Set the offset field of FLE
++ * @fle: the given frame list entry
++ * @offset: the offset needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
++{
++	fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
++	fle->format_offset |= cpu_to_le16(offset);
++}
++
++/**
++ * dpaa2_fl_get_format() - Get the format field in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the format.
++ */
++static inline enum dpaa2_fl_format dpaa2_fl_get_format(
++					const struct dpaa2_fl_entry *fle)
++{
++	return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
++				       FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
++}
++
++/**
++ * dpaa2_fl_set_format() - Set the format field of FLE
++ * @fle: the given frame list entry
++ * @format: the format needs to be set in frame list entry
++ */
++static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
++				       enum dpaa2_fl_format format)
++{
++	fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
++	fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
++}
++
++/**
++ * dpaa2_fl_get_bpid() - Get the bpid field in the FLE
++ * @fle: the given frame list entry
++ *
++ * Return the buffer pool id.
++ */
++static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
++{
++	return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
++}
++
++/**
++ * dpaa2_fl_set_bpid() - Set the bpid field of FLE
++ * @fle: the given frame list entry
++ * @bpid: buffer pool id to be set
++ */
++static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
++{
++	fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
++	fle->bpid |= cpu_to_le16(bpid);
++}
++
++/**
++ * dpaa2_fl_is_final() - Check final bit in FLE
++ * @fle: the given frame list entry
++ *
++ * Return bool.
++ */
++static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
++{
++	return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
++}
++
++/**
++ * dpaa2_fl_set_final() - Set the final bit in FLE
++ * @fle: the given frame list entry
++ * @final: the final boolean to be set
++ */
++static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
++{
++	fle->format_offset &= cpu_to_le16(~(FL_FINAL_FLAG_MASK <<
++					    FL_FINAL_FLAG_SHIFT));
++	fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
++}
++
++#endif /* __FSL_DPAA2_FD_H */
+--- /dev/null
++++ b/drivers/staging/fsl-mc/include/dpaa2-global.h
+@@ -0,0 +1,177 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
++/*
++ * Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ */
++#ifndef __FSL_DPAA2_GLOBAL_H
++#define __FSL_DPAA2_GLOBAL_H
++
++#include <linux/types.h>
++#include <linux/cpumask.h>
++#include "dpaa2-fd.h"
++
++struct dpaa2_dq {
++	union {
++		struct common {
++			u8 verb;
++			u8 reserved[63];
++		} common;
++		struct dq {
++			u8 verb;
++			u8 stat;
++			__le16 seqnum;
++			__le16 oprid;
++			u8 reserved;
++			u8 tok;
++			__le32 fqid;
++			u32 reserved2;
++			__le32 fq_byte_cnt;
++			__le32 fq_frm_cnt;
++			__le64 fqd_ctx;
++			u8 fd[32];
++		} dq;
++		struct scn {
++			u8 verb;
++			u8 stat;
++			u8 state;
++			u8 reserved;
++			__le32 rid_tok;
++			__le64 ctx;
++		} scn;
++	};
++};
++
++/* Parsing frame dequeue results */
++/* FQ empty */
++#define DPAA2_DQ_STAT_FQEMPTY       0x80
++/* FQ held active */
++#define DPAA2_DQ_STAT_HELDACTIVE    0x40
++/* FQ force eligible */
++#define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
++/* valid frame */
++#define DPAA2_DQ_STAT_VALIDFRAME    0x10
++/* FQ ODP enable */
++#define DPAA2_DQ_STAT_ODPVALID      0x04
++/* volatile dequeue */
++#define DPAA2_DQ_STAT_VOLATILE      0x02
++/* volatile dequeue command is expired */
++#define DPAA2_DQ_STAT_EXPIRED       0x01
++
++#define DQ_FQID_MASK		0x00FFFFFF
++#define DQ_FRAME_COUNT_MASK	0x00FFFFFF
++
++/**
++ * dpaa2_dq_flags() - Get the stat field of dequeue response
++ * @dq: the dequeue result.
++ */
++static inline u32 dpaa2_dq_flags(const struct dpaa2_dq *dq)
++{
++	return dq->dq.stat;
++}
++
++/**
++ * dpaa2_dq_is_pull() - Check whether the dq response is from a pull
++ *                      command.
++ * @dq: the dequeue result
++ *
++ * Return 1 for volatile(pull) dequeue, 0 for static dequeue.
++ */
++static inline int dpaa2_dq_is_pull(const struct dpaa2_dq *dq)
++{
++	return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_VOLATILE);
++}
++
++/**
++ * dpaa2_dq_is_pull_complete() - Check whether the pull command is completed.
++ * @dq: the dequeue result
++ *
++ * Return boolean.
++ */
++static inline bool dpaa2_dq_is_pull_complete(const struct dpaa2_dq *dq)
++{
++	return !!(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_EXPIRED);
++}
++
++/**
++ * dpaa2_dq_seqnum() - Get the seqnum field in dequeue response
++ * @dq: the dequeue result
++ *
++ * seqnum is valid only if VALIDFRAME flag is TRUE
++ *
++ * Return seqnum.
++ */
++static inline u16 dpaa2_dq_seqnum(const struct dpaa2_dq *dq)
++{
++	return le16_to_cpu(dq->dq.seqnum);
++}
++
++/**
++ * dpaa2_dq_odpid() - Get the odpid field in dequeue response
++ * @dq: the dequeue result
++ *
++ * odpid is valid only if ODPVALID flag is TRUE.
++ *
++ * Return odpid.
++ */
++static inline u16 dpaa2_dq_odpid(const struct dpaa2_dq *dq)
++{
++	return le16_to_cpu(dq->dq.oprid);
++}
++
++/**
++ * dpaa2_dq_fqid() - Get the fqid in dequeue response
++ * @dq: the dequeue result
++ *
++ * Return fqid.
++ */
++static inline u32 dpaa2_dq_fqid(const struct dpaa2_dq *dq)
++{
++	return le32_to_cpu(dq->dq.fqid) & DQ_FQID_MASK;
++}
++
++/**
++ * dpaa2_dq_byte_count() - Get the byte count in dequeue response
++ * @dq: the dequeue result
++ *
++ * Return the byte count remaining in the FQ.
++ */
++static inline u32 dpaa2_dq_byte_count(const struct dpaa2_dq *dq)
++{
++	return le32_to_cpu(dq->dq.fq_byte_cnt);
++}
++
++/**
++ * dpaa2_dq_frame_count() - Get the frame count in dequeue response
++ * @dq: the dequeue result
++ *
++ * Return the frame count remaining in the FQ.
++ */
++static inline u32 dpaa2_dq_frame_count(const struct dpaa2_dq *dq)
++{
++	return le32_to_cpu(dq->dq.fq_frm_cnt) & DQ_FRAME_COUNT_MASK;
++}
++
++/**
++ * dpaa2_dq_fd_ctx() - Get the frame queue context in dequeue response
++ * @dq: the dequeue result
++ *
++ * Return the frame queue context.
++ */
++static inline u64 dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq)
++{
++	return le64_to_cpu(dq->dq.fqd_ctx);
++}
++
++/**
++ * dpaa2_dq_fd() - Get the frame descriptor in dequeue response
++ * @dq: the dequeue result
++ *
++ * Return the frame descriptor.
++ */
++static inline const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq)
++{
++	return (const struct dpaa2_fd *)&dq->dq.fd[0];
++}
++
++#endif /* __FSL_DPAA2_GLOBAL_H */
+--- /dev/null
++++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
+@@ -0,0 +1,178 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
++/*
++ * Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ */
++#ifndef __FSL_DPAA2_IO_H
++#define __FSL_DPAA2_IO_H
++
++#include <linux/types.h>
++#include <linux/cpumask.h>
++
++#include "dpaa2-fd.h"
++#include "dpaa2-global.h"
++
++struct dpaa2_io;
++struct dpaa2_io_store;
++struct device;
++
++/**
++ * DOC: DPIO Service
++ *
++ * The DPIO service provides APIs for users to interact with the datapath
++ * by enqueueing and dequeing frame descriptors.
++ *
++ * The following set of APIs can be used to enqueue and dequeue frames
++ * as well as producing notification callbacks when data is available
++ * for dequeue.
++ */
++
++#define DPAA2_IO_ANY_CPU	-1
++
++/**
++ * struct dpaa2_io_desc - The DPIO descriptor
++ * @receives_notifications: Use notificaton mode. Non-zero if the DPIO
++ *                  has a channel.
++ * @has_8prio:      Set to non-zero for channel with 8 priority WQs.  Ignored
++ *                  unless receives_notification is TRUE.
++ * @cpu:            The cpu index that at least interrupt handlers will
++ *                  execute on.
++ * @stash_affinity: The stash affinity for this portal favour 'cpu'
++ * @regs_cena:      The cache enabled regs.
++ * @regs_cinh:      The cache inhibited regs
++ * @dpio_id:        The dpio index
++ * @qman_version:   The qman version
++ *
++ * Describes the attributes and features of the DPIO object.
++ */
++struct dpaa2_io_desc {
++	int receives_notifications;
++	int has_8prio;
++	int cpu;
++	void *regs_cena;
++	void *regs_cinh;
++	int dpio_id;
++	u32 qman_version;
++};
++
++struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc);
++
++void dpaa2_io_down(struct dpaa2_io *d);
++
++irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
++
++struct dpaa2_io *dpaa2_io_service_select(int cpu);
++
++/**
++ * struct dpaa2_io_notification_ctx - The DPIO notification context structure
++ * @cb:           The callback to be invoked when the notification arrives
++ * @is_cdan:      Zero for FQDAN, non-zero for CDAN
++ * @id:           FQID or channel ID, needed for rearm
++ * @desired_cpu:  The cpu on which the notifications will show up. Use
++ *                DPAA2_IO_ANY_CPU if don't care
++ * @dpio_id:      The dpio index
++ * @qman64:       The 64-bit context value shows up in the FQDAN/CDAN.
++ * @node:         The list node
++ * @dpio_private: The dpio object internal to dpio_service
++ *
++ * Used when a FQDAN/CDAN registration is made by drivers.
++ */
++struct dpaa2_io_notification_ctx {
++	void (*cb)(struct dpaa2_io_notification_ctx *ctx);
++	int is_cdan;
++	u32 id;
++	int desired_cpu;
++	int dpio_id;
++	u64 qman64;
++	struct list_head node;
++	void *dpio_private;
++};
++
++int dpaa2_io_service_register(struct dpaa2_io *service,
++			      struct dpaa2_io_notification_ctx *ctx);
++void dpaa2_io_service_deregister(struct dpaa2_io *service,
++				 struct dpaa2_io_notification_ctx *ctx);
++int dpaa2_io_service_rearm(struct dpaa2_io *service,
++			   struct dpaa2_io_notification_ctx *ctx);
++
++int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
++			     struct dpaa2_io_store *s);
++int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
++				  struct dpaa2_io_store *s);
++
++int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, u32 fqid,
++				const struct dpaa2_fd *fd);
++int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
++				u16 qdbin, const struct dpaa2_fd *fd);
++int dpaa2_io_service_release(struct dpaa2_io *d, u32 bpid,
++			     const u64 *buffers, unsigned int num_buffers);
++int dpaa2_io_service_acquire(struct dpaa2_io *d, u32 bpid,
++			     u64 *buffers, unsigned int num_buffers);
++
++struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
++					     struct device *dev);
++void dpaa2_io_store_destroy(struct dpaa2_io_store *s);
++struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last);
++
++/* Order Restoration Support */
++int dpaa2_io_service_enqueue_orp_fq(struct dpaa2_io *d, u32 fqid,
++				    const struct dpaa2_fd *fd, u16 orpid,
++				    u16 seqnum, int last);
++
++int dpaa2_io_service_enqueue_orp_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
++				    u16 qdbin, const struct dpaa2_fd *fd,
++				    u16 orpid, u16 seqnum, int last);
++
++int dpaa2_io_service_orp_seqnum_drop(struct dpaa2_io *d, u16 orpid,
++				     u16 seqnum);
++
++/***************/
++/* CSCN        */
++/***************/
++
++/**
++ * struct dpaa2_cscn - The CSCN message format
++ * @verb: identifies the type of message (should be 0x27).
++ * @stat: status bits related to dequeuing response (not used)
++ * @state: bit 0 = 0/1 if CG is no/is congested
++ * @reserved: reserved byte
++ * @cgid: congest grp ID - the first 16 bits
++ * @ctx: context data
++ *
++ * Congestion management can be implemented in software through
++ * the use of Congestion State Change Notifications (CSCN). These
++ * are messages written by DPAA2 hardware to memory whenever the
++ * instantaneous count (I_CNT field in the CG) exceeds the
++ * Congestion State (CS) entrance threshold, signifying congestion
++ * entrance, or when the instantaneous count returns below exit
++ * threshold, signifying congestion exit. The format of the message
++ * is given by the dpaa2_cscn structure. Bit 0 of the state field
++ * represents congestion state written by the hardware.
++ */
++struct dpaa2_cscn {
++	u8 verb;
++	u8 stat;
++	u8 state;
++	u8 reserved;
++	__le32 cgid;
++	__le64 ctx;
++};
++
++#define DPAA2_CSCN_SIZE                        64
++#define DPAA2_CSCN_ALIGN               16
++
++#define DPAA2_CSCN_STATE_MASK          0x1
++#define DPAA2_CSCN_CONGESTED           1
++
++static inline bool dpaa2_cscn_state_congested(struct dpaa2_cscn *cscn)
++{
++	return ((cscn->state & DPAA2_CSCN_STATE_MASK) == DPAA2_CSCN_CONGESTED);
++}
++
++int dpaa2_io_query_fq_count(struct dpaa2_io *d, u32 fqid,
++			    u32 *fcnt, u32 *bcnt);
++int dpaa2_io_query_bp_count(struct dpaa2_io *d, u32 bpid,
++			    u32 *num);
++
++#endif /* __FSL_DPAA2_IO_H */
+--- a/drivers/staging/fsl-mc/include/dpbp-cmd.h
++++ /dev/null
+@@ -1,185 +0,0 @@
+-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#ifndef _FSL_DPBP_CMD_H
+-#define _FSL_DPBP_CMD_H
+-
+-/* DPBP Version */
+-#define DPBP_VER_MAJOR				2
+-#define DPBP_VER_MINOR				2
+-
+-/* Command IDs */
+-#define DPBP_CMDID_CLOSE				0x800
+-#define DPBP_CMDID_OPEN					0x804
+-#define DPBP_CMDID_CREATE				0x904
+-#define DPBP_CMDID_DESTROY				0x900
+-
+-#define DPBP_CMDID_ENABLE				0x002
+-#define DPBP_CMDID_DISABLE				0x003
+-#define DPBP_CMDID_GET_ATTR				0x004
+-#define DPBP_CMDID_RESET				0x005
+-#define DPBP_CMDID_IS_ENABLED				0x006
+-
+-#define DPBP_CMDID_SET_IRQ				0x010
+-#define DPBP_CMDID_GET_IRQ				0x011
+-#define DPBP_CMDID_SET_IRQ_ENABLE			0x012
+-#define DPBP_CMDID_GET_IRQ_ENABLE			0x013
+-#define DPBP_CMDID_SET_IRQ_MASK				0x014
+-#define DPBP_CMDID_GET_IRQ_MASK				0x015
+-#define DPBP_CMDID_GET_IRQ_STATUS			0x016
+-#define DPBP_CMDID_CLEAR_IRQ_STATUS			0x017
+-
+-#define DPBP_CMDID_SET_NOTIFICATIONS		0x01b0
+-#define DPBP_CMDID_GET_NOTIFICATIONS		0x01b1
+-
+-struct dpbp_cmd_open {
+-	__le32 dpbp_id;
+-};
+-
+-#define DPBP_ENABLE			0x1
+-
+-struct dpbp_rsp_is_enabled {
+-	u8 enabled;
+-};
+-
+-struct dpbp_cmd_set_irq {
+-	/* cmd word 0 */
+-	u8 irq_index;
+-	u8 pad[3];
+-	__le32 irq_val;
+-	/* cmd word 1 */
+-	__le64 irq_addr;
+-	/* cmd word 2 */
+-	__le32 irq_num;
+-};
+-
+-struct dpbp_cmd_get_irq {
+-	__le32 pad;
+-	u8 irq_index;
+-};
+-
+-struct dpbp_rsp_get_irq {
+-	/* response word 0 */
+-	__le32 irq_val;
+-	__le32 pad;
+-	/* response word 1 */
+-	__le64 irq_addr;
+-	/* response word 2 */
+-	__le32 irq_num;
+-	__le32 type;
+-};
+-
+-struct dpbp_cmd_set_irq_enable {
+-	u8 enable;
+-	u8 pad[3];
+-	u8 irq_index;
+-};
+-
+-struct dpbp_cmd_get_irq_enable {
+-	__le32 pad;
+-	u8 irq_index;
+-};
+-
+-struct dpbp_rsp_get_irq_enable {
+-	u8 enabled;
+-};
+-
+-struct dpbp_cmd_set_irq_mask {
+-	__le32 mask;
+-	u8 irq_index;
+-};
+-
+-struct dpbp_cmd_get_irq_mask {
+-	__le32 pad;
+-	u8 irq_index;
+-};
+-
+-struct dpbp_rsp_get_irq_mask {
+-	__le32 mask;
+-};
+-
+-struct dpbp_cmd_get_irq_status {
+-	__le32 status;
+-	u8 irq_index;
+-};
+-
+-struct dpbp_rsp_get_irq_status {
+-	__le32 status;
+-};
+-
+-struct dpbp_cmd_clear_irq_status {
+-	__le32 status;
+-	u8 irq_index;
+-};
+-
+-struct dpbp_rsp_get_attributes {
+-	/* response word 0 */
+-	__le16 pad;
+-	__le16 bpid;
+-	__le32 id;
+-	/* response word 1 */
+-	__le16 version_major;
+-	__le16 version_minor;
+-};
+-
+-struct dpbp_cmd_set_notifications {
+-	/* cmd word 0 */
+-	__le32 depletion_entry;
+-	__le32 depletion_exit;
+-	/* cmd word 1 */
+-	__le32 surplus_entry;
+-	__le32 surplus_exit;
+-	/* cmd word 2 */
+-	__le16 options;
+-	__le16 pad[3];
+-	/* cmd word 3 */
+-	__le64 message_ctx;
+-	/* cmd word 4 */
+-	__le64 message_iova;
+-};
+-
+-struct dpbp_rsp_get_notifications {
+-	/* response word 0 */
+-	__le32 depletion_entry;
+-	__le32 depletion_exit;
+-	/* response word 1 */
+-	__le32 surplus_entry;
+-	__le32 surplus_exit;
+-	/* response word 2 */
+-	__le16 options;
+-	__le16 pad[3];
+-	/* response word 3 */
+-	__le64 message_ctx;
+-	/* response word 4 */
+-	__le64 message_iova;
+-};
+-
+-#endif /* _FSL_DPBP_CMD_H */
+--- a/drivers/staging/fsl-mc/include/dpbp.h
++++ /dev/null
+@@ -1,220 +0,0 @@
+-/* Copyright 2013-2015 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#ifndef __FSL_DPBP_H
+-#define __FSL_DPBP_H
+-
+-/* Data Path Buffer Pool API
+- * Contains initialization APIs and runtime control APIs for DPBP
+- */
+-
+-struct fsl_mc_io;
+-
+-int dpbp_open(struct fsl_mc_io *mc_io,
+-	      u32 cmd_flags,
+-	      int dpbp_id,
+-	      u16 *token);
+-
+-int dpbp_close(struct fsl_mc_io *mc_io,
+-	       u32		cmd_flags,
+-	       u16	token);
+-
+-/**
+- * struct dpbp_cfg - Structure representing DPBP configuration
+- * @options:	place holder
+- */
+-struct dpbp_cfg {
+-	u32 options;
+-};
+-
+-int dpbp_create(struct fsl_mc_io	*mc_io,
+-		u32		cmd_flags,
+-		const struct dpbp_cfg	*cfg,
+-		u16		*token);
+-
+-int dpbp_destroy(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token);
+-
+-int dpbp_enable(struct fsl_mc_io *mc_io,
+-		u32 cmd_flags,
+-		u16 token);
+-
+-int dpbp_disable(struct fsl_mc_io *mc_io,
+-		 u32 cmd_flags,
+-		 u16 token);
+-
+-int dpbp_is_enabled(struct fsl_mc_io *mc_io,
+-		    u32 cmd_flags,
+-		    u16 token,
+-		    int *en);
+-
+-int dpbp_reset(struct fsl_mc_io *mc_io,
+-	       u32 cmd_flags,
+-	       u16 token);
+-
+-/**
+- * struct dpbp_irq_cfg - IRQ configuration
+- * @addr:	Address that must be written to signal a message-based interrupt
+- * @val:	Value to write into irq_addr address
+- * @irq_num: A user defined number associated with this IRQ
+- */
+-struct dpbp_irq_cfg {
+-	     u64		addr;
+-	     u32		val;
+-	     int		irq_num;
+-};
+-
+-int dpbp_set_irq(struct fsl_mc_io	*mc_io,
+-		 u32		cmd_flags,
+-		 u16		token,
+-		 u8		irq_index,
+-		 struct dpbp_irq_cfg	*irq_cfg);
+-
+-int dpbp_get_irq(struct fsl_mc_io	*mc_io,
+-		 u32		cmd_flags,
+-		 u16		token,
+-		 u8		irq_index,
+-		 int			*type,
+-		 struct dpbp_irq_cfg	*irq_cfg);
+-
+-int dpbp_set_irq_enable(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			u8			irq_index,
+-			u8			en);
+-
+-int dpbp_get_irq_enable(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			u8			irq_index,
+-			u8			*en);
+-
+-int dpbp_set_irq_mask(struct fsl_mc_io	*mc_io,
+-		      u32		cmd_flags,
+-		      u16		token,
+-		      u8		irq_index,
+-		      u32		mask);
+-
+-int dpbp_get_irq_mask(struct fsl_mc_io	*mc_io,
+-		      u32		cmd_flags,
+-		      u16		token,
+-		      u8		irq_index,
+-		      u32		*mask);
+-
+-int dpbp_get_irq_status(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			u8			irq_index,
+-			u32		*status);
+-
+-int dpbp_clear_irq_status(struct fsl_mc_io	*mc_io,
+-			  u32		cmd_flags,
+-			  u16		token,
+-			  u8		irq_index,
+-			  u32		status);
+-
+-/**
+- * struct dpbp_attr - Structure representing DPBP attributes
+- * @id:		DPBP object ID
+- * @version:	DPBP version
+- * @bpid:	Hardware buffer pool ID; should be used as an argument in
+- *		acquire/release operations on buffers
+- */
+-struct dpbp_attr {
+-	int id;
+-	/**
+-	 * struct version - Structure representing DPBP version
+-	 * @major:	DPBP major version
+-	 * @minor:	DPBP minor version
+-	 */
+-	struct {
+-		u16 major;
+-		u16 minor;
+-	} version;
+-	u16 bpid;
+-};
+-
+-int dpbp_get_attributes(struct fsl_mc_io	*mc_io,
+-			u32	cmd_flags,
+-			u16		token,
+-			struct dpbp_attr	*attr);
+-
+-/**
+- *  DPBP notifications options
+- */
+-
+-/**
+- * BPSCN write will attempt to allocate into a cache (coherent write)
+- */
+-#define DPBP_NOTIF_OPT_COHERENT_WRITE	0x00000001
+-
+-/**
+- * struct dpbp_notification_cfg - Structure representing DPBP notifications
+- *	towards software
+- * @depletion_entry: below this threshold the pool is "depleted";
+- *	set it to '0' to disable it
+- * @depletion_exit: greater than or equal to this threshold the pool exit its
+- *	"depleted" state
+- * @surplus_entry: above this threshold the pool is in "surplus" state;
+- *	set it to '0' to disable it
+- * @surplus_exit: less than or equal to this threshold the pool exit its
+- *	"surplus" state
+- * @message_iova: MUST be given if either 'depletion_entry' or 'surplus_entry'
+- *	is not '0' (enable); I/O virtual address (must be in DMA-able memory),
+- *	must be 16B aligned.
+- * @message_ctx: The context that will be part of the BPSCN message and will
+- *	be written to 'message_iova'
+- * @options: Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
+- */
+-struct dpbp_notification_cfg {
+-	u32	depletion_entry;
+-	u32	depletion_exit;
+-	u32	surplus_entry;
+-	u32	surplus_exit;
+-	u64	message_iova;
+-	u64	message_ctx;
+-	u16	options;
+-};
+-
+-int dpbp_set_notifications(struct fsl_mc_io	*mc_io,
+-			   u32		cmd_flags,
+-			   u16		token,
+-			   struct dpbp_notification_cfg	*cfg);
+-
+-int dpbp_get_notifications(struct fsl_mc_io	*mc_io,
+-			   u32		cmd_flags,
+-			   u16		token,
+-			   struct dpbp_notification_cfg	*cfg);
+-
+-/** @} */
+-
+-#endif /* __FSL_DPBP_H */
+--- a/drivers/staging/fsl-mc/include/dpcon-cmd.h
++++ /dev/null
+@@ -1,62 +0,0 @@
+-/* Copyright 2013-2015 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#ifndef _FSL_DPCON_CMD_H
+-#define _FSL_DPCON_CMD_H
+-
+-/* DPCON Version */
+-#define DPCON_VER_MAJOR				2
+-#define DPCON_VER_MINOR				1
+-
+-/* Command IDs */
+-#define DPCON_CMDID_CLOSE				0x800
+-#define DPCON_CMDID_OPEN				0x808
+-#define DPCON_CMDID_CREATE				0x908
+-#define DPCON_CMDID_DESTROY				0x900
+-
+-#define DPCON_CMDID_ENABLE				0x002
+-#define DPCON_CMDID_DISABLE				0x003
+-#define DPCON_CMDID_GET_ATTR				0x004
+-#define DPCON_CMDID_RESET				0x005
+-#define DPCON_CMDID_IS_ENABLED				0x006
+-
+-#define DPCON_CMDID_SET_IRQ				0x010
+-#define DPCON_CMDID_GET_IRQ				0x011
+-#define DPCON_CMDID_SET_IRQ_ENABLE			0x012
+-#define DPCON_CMDID_GET_IRQ_ENABLE			0x013
+-#define DPCON_CMDID_SET_IRQ_MASK			0x014
+-#define DPCON_CMDID_GET_IRQ_MASK			0x015
+-#define DPCON_CMDID_GET_IRQ_STATUS			0x016
+-#define DPCON_CMDID_CLEAR_IRQ_STATUS			0x017
+-
+-#define DPCON_CMDID_SET_NOTIFICATION			0x100
+-
+-#endif /* _FSL_DPCON_CMD_H */
+--- a/drivers/staging/fsl-mc/include/dpmng.h
++++ /dev/null
+@@ -1,69 +0,0 @@
+-/* Copyright 2013-2015 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#ifndef __FSL_DPMNG_H
+-#define __FSL_DPMNG_H
+-
+-/* Management Complex General API
+- * Contains general API for the Management Complex firmware
+- */
+-
+-struct fsl_mc_io;
+-
+-/**
+- * Management Complex firmware version information
+- */
+-#define MC_VER_MAJOR 8
+-#define MC_VER_MINOR 0
+-
+-/**
+- * struct mc_version
+- * @major: Major version number: incremented on API compatibility changes
+- * @minor: Minor version number: incremented on API additions (that are
+- *		backward compatible); reset when major version is incremented
+- * @revision: Internal revision number: incremented on implementation changes
+- *		and/or bug fixes that have no impact on API
+- */
+-struct mc_version {
+-	u32 major;
+-	u32 minor;
+-	u32 revision;
+-};
+-
+-int mc_get_version(struct fsl_mc_io	*mc_io,
+-		   u32		cmd_flags,
+-		   struct mc_version	*mc_ver_info);
+-
+-int dpmng_get_container_id(struct fsl_mc_io	*mc_io,
+-			   u32		cmd_flags,
+-			   int			*container_id);
+-
+-#endif /* __FSL_DPMNG_H */
+--- /dev/null
++++ b/drivers/staging/fsl-mc/include/dpopr.h
+@@ -0,0 +1,112 @@
++/*
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef __FSL_DPOPR_H_
++#define __FSL_DPOPR_H_
++
++#include <linux/types.h>
++
++/* Data Path Order Restoration API
++ * Contains initialization APIs and runtime APIs for the Order Restoration
++ */
++
++/** Order Restoration properties */
++
++/**
++ * Create a new Order Point Record option
++ */
++#define OPR_OPT_CREATE 0x1
++/**
++ * Retire an existing Order Point Record option
++ */
++#define OPR_OPT_RETIRE 0x2
++
++/**
++ * struct opr_cfg - Structure representing OPR configuration
++ * @oprrws: Order point record (OPR) restoration window size (0 to 5)
++ *			0 - Window size is 32 frames.
++ *			1 - Window size is 64 frames.
++ *			2 - Window size is 128 frames.
++ *			3 - Window size is 256 frames.
++ *			4 - Window size is 512 frames.
++ *			5 - Window size is 1024 frames.
++ * @oa: OPR auto advance NESN window size (0 disabled, 1 enabled)
++ * @olws: OPR acceptable late arrival window size (0 to 3)
++ *			0 - Disabled. Late arrivals are always rejected.
++ *			1 - Window size is 32 frames.
++ *			2 - Window size is the same as the OPR restoration
++ *				window size configured in the OPRRWS field.
++ *			3 - Window size is 8192 frames. Late arrivals are
++ *				always accepted.
++ * @oeane: Order restoration list (ORL) resource exhaustion
++ *			advance NESN enable (0 disabled, 1 enabled)
++ * @oloe: OPR loose ordering enable (0 disabled, 1 enabled)
++ */
++struct opr_cfg {
++	u8 oprrws;
++	u8 oa;
++	u8 olws;
++	u8 oeane;
++	u8 oloe;
++};
++
++/**
++ * struct opr_qry - Structure representing OPR configuration
++ * @enable: Enabled state
++ * @rip: Retirement In Progress
++ * @ndsn: Next dispensed sequence number
++ * @nesn: Next expected sequence number
++ * @ea_hseq: Early arrival head sequence number
++ * @hseq_nlis: HSEQ not last in sequence
++ * @ea_tseq: Early arrival tail sequence number
++ * @tseq_nlis: TSEQ not last in sequence
++ * @ea_tptr: Early arrival tail pointer
++ * @ea_hptr: Early arrival head pointer
++ * @opr_id: Order Point Record ID
++ * @opr_vid: Order Point Record Virtual ID
++ */
++struct opr_qry {
++	char enable;
++	char rip;
++	u16 ndsn;
++	u16 nesn;
++	u16 ea_hseq;
++	char hseq_nlis;
++	u16 ea_tseq;
++	char tseq_nlis;
++	u16 ea_tptr;
++	u16 ea_hptr;
++	u16 opr_id;
++	u16 opr_vid;
++};
++
++#endif /* __FSL_DPOPR_H_ */
+--- a/drivers/staging/fsl-mc/include/dprc.h
++++ /dev/null
+@@ -1,544 +0,0 @@
+-/* Copyright 2013-2015 Freescale Semiconductor Inc.
 - *
 - * Redistribution and use in source and binary forms, with or without
 - * modification, are permitted provided that the following conditions are met:
@@ -10760,13 +17939,27 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -#ifndef _FSL_DPRC_H
 -#define _FSL_DPRC_H
 -
--/*
-- * Data Path Resource Container API
+-#include "mc-cmd.h"
+-
+-/* Data Path Resource Container API
 - * Contains DPRC API for managing and querying DPAA resources
 - */
 -
 -struct fsl_mc_io;
--struct fsl_mc_obj_desc;
+-
+-/**
+- * Set this value as the icid value in dprc_cfg structure when creating a
+- * container, in case the ICID is not selected by the user and should be
+- * allocated by the DPRC from the pool of ICIDs.
+- */
+-#define DPRC_GET_ICID_FROM_POOL			(u16)(~(0))
+-
+-/**
+- * Set this value as the portal_id value in dprc_cfg structure when creating a
+- * container, in case the portal ID is not specifically selected by the
+- * user and should be allocated by the DPRC from the pool of portal ids.
+- */
+-#define DPRC_GET_PORTAL_ID_FROM_POOL	(int)(~(0))
 -
 -int dprc_open(struct fsl_mc_io *mc_io,
 -	      u32 cmd_flags,
@@ -10777,13 +17970,83 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	       u32 cmd_flags,
 -	       u16 token);
 -
+-/**
+- * Container general options
+- *
+- * These options may be selected at container creation by the container creator
+- * and can be retrieved using dprc_get_attributes()
+- */
+-
+-/* Spawn Policy Option allowed - Indicates that the new container is allowed
+- * to spawn and have its own child containers.
+- */
+-#define DPRC_CFG_OPT_SPAWN_ALLOWED		0x00000001
+-
+-/* General Container allocation policy - Indicates that the new container is
+- * allowed to allocate requested resources from its parent container; if not
+- * set, the container is only allowed to use resources in its own pools; Note
+- * that this is a container's global policy, but the parent container may
+- * override it and set specific quota per resource type.
+- */
+-#define DPRC_CFG_OPT_ALLOC_ALLOWED		0x00000002
+-
+-/* Object initialization allowed - software context associated with this
+- * container is allowed to invoke object initialization operations.
+- */
+-#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED	0x00000004
+-
+-/* Topology change allowed - software context associated with this
+- * container is allowed to invoke topology operations, such as attach/detach
+- * of network objects.
+- */
+-#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED	0x00000008
+-
+-/* AIOP - Indicates that container belongs to AIOP.  */
+-#define DPRC_CFG_OPT_AIOP			0x00000020
+-
+-/* IRQ Config - Indicates that the container allowed to configure its IRQs.  */
+-#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED		0x00000040
+-
+-/**
+- * struct dprc_cfg - Container configuration options
+- * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free
+- *		ICID value is allocated by the DPRC
+- * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free
+- *		portal ID is allocated by the DPRC
+- * @options: Combination of 'DPRC_CFG_OPT_<X>' options
+- * @label: Object's label
+- */
+-struct dprc_cfg {
+-	u16 icid;
+-	int portal_id;
+-	u64 options;
+-	char label[16];
+-};
+-
+-int dprc_create_container(struct fsl_mc_io	*mc_io,
+-			  u32		cmd_flags,
+-			  u16		token,
+-			  struct dprc_cfg	*cfg,
+-			  int			*child_container_id,
+-			  u64		*child_portal_offset);
+-
+-int dprc_destroy_container(struct fsl_mc_io	*mc_io,
+-			   u32		cmd_flags,
+-			   u16		token,
+-			   int			child_container_id);
+-
+-int dprc_reset_container(struct fsl_mc_io *mc_io,
+-			 u32 cmd_flags,
+-			 u16 token,
+-			 int child_container_id);
+-
 -/* IRQ */
 -
 -/* IRQ index */
 -#define DPRC_IRQ_INDEX          0
 -
 -/* Number of dprc's IRQs */
--#define DPRC_NUM_OF_IRQS	1
+-#define DPRC_NUM_OF_IRQS		1
 -
 -/* DPRC IRQ events */
 -
@@ -10795,14 +18058,12 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -#define DPRC_IRQ_EVENT_RES_ADDED		0x00000004
 -/* IRQ event - Indicates that resources removed from the container */
 -#define DPRC_IRQ_EVENT_RES_REMOVED		0x00000008
--/*
-- * IRQ event - Indicates that one of the descendant containers that opened by
+-/* IRQ event - Indicates that one of the descendant containers that opened by
 - * this container is destroyed
 - */
 -#define DPRC_IRQ_EVENT_CONTAINER_DESTROYED	0x00000010
 -
--/*
-- * IRQ event - Indicates that on one of the container's opened object is
+-/* IRQ event - Indicates that on one of the container's opened object is
 - * destroyed
 - */
 -#define DPRC_IRQ_EVENT_OBJ_DESTROYED		0x00000020
@@ -10817,59 +18078,59 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * @irq_num:	A user defined number associated with this IRQ
 - */
 -struct dprc_irq_cfg {
--	     phys_addr_t paddr;
--	     u32 val;
--	     int irq_num;
+-	     phys_addr_t	paddr;
+-	     u32		val;
+-	     int		irq_num;
 -};
 -
--int dprc_set_irq(struct fsl_mc_io *mc_io,
--		 u32 cmd_flags,
--		 u16 token,
--		 u8 irq_index,
--		 struct dprc_irq_cfg *irq_cfg);
+-int dprc_set_irq(struct fsl_mc_io	*mc_io,
+-		 u32		cmd_flags,
+-		 u16		token,
+-		 u8		irq_index,
+-		 struct dprc_irq_cfg	*irq_cfg);
 -
--int dprc_get_irq(struct fsl_mc_io *mc_io,
--		 u32 cmd_flags,
--		 u16 token,
--		 u8 irq_index,
--		 int *type,
--		 struct dprc_irq_cfg *irq_cfg);
+-int dprc_get_irq(struct fsl_mc_io	*mc_io,
+-		 u32		cmd_flags,
+-		 u16		token,
+-		 u8		irq_index,
+-		 int			*type,
+-		 struct dprc_irq_cfg	*irq_cfg);
 -
--int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			u8 irq_index,
--			u8 en);
+-int dprc_set_irq_enable(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			u8			irq_index,
+-			u8			en);
 -
--int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			u8 irq_index,
--			u8 *en);
+-int dprc_get_irq_enable(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			u8			irq_index,
+-			u8			*en);
 -
--int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
--		      u32 cmd_flags,
--		      u16 token,
--		      u8 irq_index,
--		      u32 mask);
+-int dprc_set_irq_mask(struct fsl_mc_io	*mc_io,
+-		      u32		cmd_flags,
+-		      u16		token,
+-		      u8		irq_index,
+-		      u32		mask);
 -
--int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
--		      u32 cmd_flags,
--		      u16 token,
--		      u8 irq_index,
--		      u32 *mask);
+-int dprc_get_irq_mask(struct fsl_mc_io	*mc_io,
+-		      u32		cmd_flags,
+-		      u16		token,
+-		      u8		irq_index,
+-		      u32		*mask);
 -
--int dprc_get_irq_status(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			u8 irq_index,
--			u32 *status);
+-int dprc_get_irq_status(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			u8			irq_index,
+-			u32		*status);
 -
--int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
--			  u32 cmd_flags,
--			  u16 token,
--			  u8 irq_index,
--			  u32 status);
+-int dprc_clear_irq_status(struct fsl_mc_io	*mc_io,
+-			  u32		cmd_flags,
+-			  u16		token,
+-			  u8		irq_index,
+-			  u32		status);
 -
 -/**
 - * struct dprc_attributes - Container attributes
@@ -10877,59 +18138,191 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 - * @icid: Container's ICID
 - * @portal_id: Container's portal ID
 - * @options: Container's options as set at container's creation
+- * @version: DPRC version
 - */
 -struct dprc_attributes {
 -	int container_id;
 -	u16 icid;
 -	int portal_id;
 -	u64 options;
+-	/**
+-	 * struct version - DPRC version
+-	 * @major: DPRC major version
+-	 * @minor: DPRC minor version
+-	 */
+-	struct {
+-		u16 major;
+-		u16 minor;
+-	} version;
 -};
 -
--int dprc_get_attributes(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			struct dprc_attributes *attributes);
+-int dprc_get_attributes(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			struct dprc_attributes	*attributes);
+-
+-int dprc_set_res_quota(struct fsl_mc_io	*mc_io,
+-		       u32		cmd_flags,
+-		       u16		token,
+-		       int		child_container_id,
+-		       char		*type,
+-		       u16		quota);
+-
+-int dprc_get_res_quota(struct fsl_mc_io	*mc_io,
+-		       u32		cmd_flags,
+-		       u16		token,
+-		       int		child_container_id,
+-		       char		*type,
+-		       u16		*quota);
+-
+-/* Resource request options */
+-
+-/* Explicit resource ID request - The requested objects/resources
+- * are explicit and sequential (in case of resources).
+- * The base ID is given at res_req at base_align field
+- */
+-#define DPRC_RES_REQ_OPT_EXPLICIT		0x00000001
+-
+-/* Aligned resources request - Relevant only for resources
+- * request (and not objects). Indicates that resources base ID should be
+- * sequential and aligned to the value given at dprc_res_req base_align field
+- */
+-#define DPRC_RES_REQ_OPT_ALIGNED		0x00000002
+-
+-/* Plugged Flag - Relevant only for object assignment request.
+- * Indicates that after all objects assigned. An interrupt will be invoked at
+- * the relevant GPP. The assigned object will be marked as plugged.
+- * plugged objects can't be assigned from their container
+- */
+-#define DPRC_RES_REQ_OPT_PLUGGED		0x00000004
+-
+-/**
+- * struct dprc_res_req - Resource request descriptor, to be used in assignment
+- *			or un-assignment of resources and objects.
+- * @type: Resource/object type: Represent as a NULL terminated string.
+- *	This string may received by using dprc_get_pool() to get resource
+- *	type and dprc_get_obj() to get object type;
+- *	Note: it is not possible to assign/un-assign DPRC objects
+- * @num: Number of resources
+- * @options: Request options: combination of DPRC_RES_REQ_OPT_ options
+- * @id_base_align: In case of explicit assignment (DPRC_RES_REQ_OPT_EXPLICIT
+- *		is set at option), this field represents the required base ID
+- *		for resource allocation; In case of aligned assignment
+- *		(DPRC_RES_REQ_OPT_ALIGNED is set at option), this field
+- *		indicates the required alignment for the resource ID(s) -
+- *		use 0 if there is no alignment or explicit ID requirements
+- */
+-struct dprc_res_req {
+-	char type[16];
+-	u32 num;
+-	u32 options;
+-	int id_base_align;
+-};
+-
+-int dprc_assign(struct fsl_mc_io	*mc_io,
+-		u32		cmd_flags,
+-		u16		token,
+-		int			container_id,
+-		struct dprc_res_req	*res_req);
+-
+-int dprc_unassign(struct fsl_mc_io	*mc_io,
+-		  u32		cmd_flags,
+-		  u16		token,
+-		  int			child_container_id,
+-		  struct dprc_res_req	*res_req);
+-
+-int dprc_get_pool_count(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			int			*pool_count);
+-
+-int dprc_get_pool(struct fsl_mc_io	*mc_io,
+-		  u32		cmd_flags,
+-		  u16		token,
+-		  int			pool_index,
+-		  char			*type);
 -
 -int dprc_get_obj_count(struct fsl_mc_io *mc_io,
--		       u32 cmd_flags,
--		       u16 token,
--		       int *obj_count);
+-		       u32		cmd_flags,
+-		       u16		token,
+-		       int		*obj_count);
 -
--int dprc_get_obj(struct fsl_mc_io *mc_io,
--		 u32 cmd_flags,
--		 u16 token,
--		 int obj_index,
--		 struct fsl_mc_obj_desc *obj_desc);
+-/* Objects Attributes Flags */
 -
--int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
--		      u32 cmd_flags,
--		      u16 token,
--		      char *obj_type,
--		      int obj_id,
--		      struct fsl_mc_obj_desc *obj_desc);
+-/* Opened state - Indicates that an object is open by at least one owner */
+-#define DPRC_OBJ_STATE_OPEN		0x00000001
+-/* Plugged state - Indicates that the object is plugged */
+-#define DPRC_OBJ_STATE_PLUGGED		0x00000002
 -
--int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
--		     u32 cmd_flags,
--		     u16 token,
--		     char *obj_type,
--		     int obj_id,
--		     u8 irq_index,
--		     struct dprc_irq_cfg *irq_cfg);
+-/**
+- * Shareability flag - Object flag indicating no memory shareability.
+- * the object generates memory accesses that are non coherent with other
+- * masters;
+- * user is responsible for proper memory handling through IOMMU configuration.
+- */
+-#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY		0x0001
 -
--int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
--		     u32 cmd_flags,
--		     u16 token,
--		     char *obj_type,
--		     int obj_id,
--		     u8 irq_index,
--		     int *type,
--		     struct dprc_irq_cfg *irq_cfg);
+-/**
+- * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
+- * @type: Type of object: NULL terminated string
+- * @id: ID of logical object resource
+- * @vendor: Object vendor identifier
+- * @ver_major: Major version number
+- * @ver_minor:  Minor version number
+- * @irq_count: Number of interrupts supported by the object
+- * @region_count: Number of mappable regions supported by the object
+- * @state: Object state: combination of DPRC_OBJ_STATE_ states
+- * @label: Object label
+- * @flags: Object's flags
+- */
+-struct dprc_obj_desc {
+-	char type[16];
+-	int id;
+-	u16 vendor;
+-	u16 ver_major;
+-	u16 ver_minor;
+-	u8 irq_count;
+-	u8 region_count;
+-	u32 state;
+-	char label[16];
+-	u16 flags;
+-};
 -
--int dprc_get_res_count(struct fsl_mc_io *mc_io,
--		       u32 cmd_flags,
--		       u16 token,
--		       char *type,
--		       int *res_count);
+-int dprc_get_obj(struct fsl_mc_io	*mc_io,
+-		 u32		cmd_flags,
+-		 u16		token,
+-		 int			obj_index,
+-		 struct dprc_obj_desc	*obj_desc);
+-
+-int dprc_get_obj_desc(struct fsl_mc_io		*mc_io,
+-		      u32		cmd_flags,
+-			u16		token,
+-			char			*obj_type,
+-			int			obj_id,
+-			struct dprc_obj_desc	*obj_desc);
+-
+-int dprc_set_obj_irq(struct fsl_mc_io		*mc_io,
+-		     u32			cmd_flags,
+-		     u16			token,
+-		     char			*obj_type,
+-		     int			obj_id,
+-		     u8			irq_index,
+-		     struct dprc_irq_cfg	*irq_cfg);
+-
+-int dprc_get_obj_irq(struct fsl_mc_io		*mc_io,
+-		     u32			cmd_flags,
+-		     u16			token,
+-		     char			*obj_type,
+-		     int			obj_id,
+-		     u8			irq_index,
+-		     int			*type,
+-		     struct dprc_irq_cfg	*irq_cfg);
+-
+-int dprc_get_res_count(struct fsl_mc_io	*mc_io,
+-		       u32		cmd_flags,
+-		       u16		token,
+-		       char		*type,
+-		       int		*res_count);
 -
 -/**
 - * enum dprc_iter_status - Iteration status
@@ -10943,6 +18336,27 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	DPRC_ITER_STATUS_LAST = 2
 -};
 -
+-/**
+- * struct dprc_res_ids_range_desc - Resource ID range descriptor
+- * @base_id: Base resource ID of this range
+- * @last_id: Last resource ID of this range
+- * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at
+- *	first iteration; while the returned marker is DPRC_ITER_STATUS_MORE,
+- *	additional iterations are needed, until the returned marker is
+- *	DPRC_ITER_STATUS_LAST
+- */
+-struct dprc_res_ids_range_desc {
+-	int base_id;
+-	int last_id;
+-	enum dprc_iter_status iter_status;
+-};
+-
+-int dprc_get_res_ids(struct fsl_mc_io			*mc_io,
+-		     u32				cmd_flags,
+-		     u16				token,
+-		     char				*type,
+-		     struct dprc_res_ids_range_desc	*range_desc);
+-
 -/* Region flags */
 -/* Cacheable - Indicates that region should be mapped as cacheable */
 -#define DPRC_REGION_CACHEABLE	0x00000001
@@ -10974,38 +18388,600 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -	enum dprc_region_type type;
 -};
 -
--int dprc_get_obj_region(struct fsl_mc_io *mc_io,
--			u32 cmd_flags,
--			u16 token,
--			char *obj_type,
--			int obj_id,
--			u8 region_index,
--			struct dprc_region_desc *region_desc);
+-int dprc_get_obj_region(struct fsl_mc_io	*mc_io,
+-			u32		cmd_flags,
+-			u16		token,
+-			char			*obj_type,
+-			int			obj_id,
+-			u8			region_index,
+-			struct dprc_region_desc	*region_desc);
 -
--int dprc_get_api_version(struct fsl_mc_io *mc_io,
--			 u32 cmd_flags,
--			 u16 *major_ver,
--			 u16 *minor_ver);
+-int dprc_set_obj_label(struct fsl_mc_io	*mc_io,
+-		       u32		cmd_flags,
+-		       u16		token,
+-		       char		*obj_type,
+-		       int		obj_id,
+-		       char		*label);
 -
--int dprc_get_container_id(struct fsl_mc_io *mc_io,
--			  u32 cmd_flags,
--			  int *container_id);
+-/**
+- * struct dprc_endpoint - Endpoint description for link connect/disconnect
+- *			operations
+- * @type: Endpoint object type: NULL terminated string
+- * @id: Endpoint object ID
+- * @if_id: Interface ID; should be set for endpoints with multiple
+- *		interfaces ("dpsw", "dpdmux"); for others, always set to 0
+- */
+-struct dprc_endpoint {
+-	char type[16];
+-	int id;
+-	int if_id;
+-};
+-
+-/**
+- * struct dprc_connection_cfg - Connection configuration.
+- *				Used for virtual connections only
+- * @committed_rate: Committed rate (Mbits/s)
+- * @max_rate: Maximum rate (Mbits/s)
+- */
+-struct dprc_connection_cfg {
+-	u32 committed_rate;
+-	u32 max_rate;
+-};
+-
+-int dprc_connect(struct fsl_mc_io		*mc_io,
+-		 u32			cmd_flags,
+-		 u16			token,
+-		 const struct dprc_endpoint	*endpoint1,
+-		 const struct dprc_endpoint	*endpoint2,
+-		 const struct dprc_connection_cfg *cfg);
+-
+-int dprc_disconnect(struct fsl_mc_io		*mc_io,
+-		    u32			cmd_flags,
+-		    u16			token,
+-		    const struct dprc_endpoint	*endpoint);
+-
+-int dprc_get_connection(struct fsl_mc_io		*mc_io,
+-			u32			cmd_flags,
+-			u16			token,
+-			const struct dprc_endpoint	*endpoint1,
+-			struct dprc_endpoint		*endpoint2,
+-			int				*state);
 -
 -#endif /* _FSL_DPRC_H */
 -
---- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
-+++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
-@@ -13,6 +13,7 @@
- #include <linux/msi.h>
- #include <linux/of.h>
- #include <linux/of_irq.h>
-+#include <linux/fsl/mc.h>
- #include "fsl-mc-private.h"
- 
- static struct irq_chip its_msi_irq_chip = {
+--- a/drivers/staging/fsl-mc/include/mc-bus.h
++++ /dev/null
+@@ -1,111 +0,0 @@
+-/*
+- * Freescale Management Complex (MC) bus declarations
+- *
+- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+- * Author: German Rivera <German.Rivera@freescale.com>
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- */
+-#ifndef _FSL_MC_MCBUS_H_
+-#define _FSL_MC_MCBUS_H_
+-
+-#include "../include/mc.h"
+-#include <linux/mutex.h>
+-
+-struct irq_domain;
+-struct msi_domain_info;
+-
+-/**
+- * Maximum number of total IRQs that can be pre-allocated for an MC bus'
+- * IRQ pool
+- */
+-#define FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS	256
+-
+-#ifdef CONFIG_FSL_MC_BUS
+-#define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type)
+-#else
+-/* If fsl-mc bus is not present device cannot belong to fsl-mc bus */
+-#define dev_is_fsl_mc(_dev) (0)
+-#endif
+-
+-/**
+- * struct fsl_mc_resource_pool - Pool of MC resources of a given
+- * type
+- * @type: type of resources in the pool
+- * @max_count: maximum number of resources in the pool
+- * @free_count: number of free resources in the pool
+- * @mutex: mutex to serialize access to the pool's free list
+- * @free_list: anchor node of list of free resources in the pool
+- * @mc_bus: pointer to the MC bus that owns this resource pool
+- */
+-struct fsl_mc_resource_pool {
+-	enum fsl_mc_pool_type type;
+-	int16_t max_count;
+-	int16_t free_count;
+-	struct mutex mutex;	/* serializes access to free_list */
+-	struct list_head free_list;
+-	struct fsl_mc_bus *mc_bus;
+-};
+-
+-/**
+- * struct fsl_mc_bus - logical bus that corresponds to a physical DPRC
+- * @mc_dev: fsl-mc device for the bus device itself.
+- * @resource_pools: array of resource pools (one pool per resource type)
+- * for this MC bus. These resources represent allocatable entities
+- * from the physical DPRC.
+- * @irq_resources: Pointer to array of IRQ objects for the IRQ pool
+- * @scan_mutex: Serializes bus scanning
+- * @dprc_attr: DPRC attributes
+- */
+-struct fsl_mc_bus {
+-	struct fsl_mc_device mc_dev;
+-	struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES];
+-	struct fsl_mc_device_irq *irq_resources;
+-	struct mutex scan_mutex;    /* serializes bus scanning */
+-	struct dprc_attributes dprc_attr;
+-};
+-
+-#define to_fsl_mc_bus(_mc_dev) \
+-	container_of(_mc_dev, struct fsl_mc_bus, mc_dev)
+-
+-int dprc_scan_container(struct fsl_mc_device *mc_bus_dev);
+-
+-int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
+-		      unsigned int *total_irq_count);
+-
+-int __init dprc_driver_init(void);
+-
+-void dprc_driver_exit(void);
+-
+-int __init fsl_mc_allocator_driver_init(void);
+-
+-void fsl_mc_allocator_driver_exit(void);
+-
+-struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode,
+-						struct msi_domain_info *info,
+-						struct irq_domain *parent);
+-
+-int fsl_mc_find_msi_domain(struct device *mc_platform_dev,
+-			   struct irq_domain **mc_msi_domain);
+-
+-int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus,
+-			     unsigned int irq_count);
+-
+-void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus);
+-
+-void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev);
+-
+-void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev);
+-
+-bool fsl_mc_bus_exists(void);
+-
+-void fsl_mc_get_root_dprc(struct device *dev,
+-			  struct device **root_dprc_dev);
+-
+-bool fsl_mc_is_root_dprc(struct device *dev);
+-
+-extern struct bus_type fsl_mc_bus_type;
+-
+-#endif /* _FSL_MC_MCBUS_H_ */
+--- a/drivers/staging/fsl-mc/include/mc-cmd.h
++++ /dev/null
+@@ -1,108 +0,0 @@
+-/* Copyright 2013-2015 Freescale Semiconductor Inc.
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- * * Redistributions of source code must retain the above copyright
+- * notice, this list of conditions and the following disclaimer.
+- * * Redistributions in binary form must reproduce the above copyright
+- * notice, this list of conditions and the following disclaimer in the
+- * documentation and/or other materials provided with the distribution.
+- * * Neither the name of the above-listed copyright holders nor the
+- * names of any contributors may be used to endorse or promote products
+- * derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-#ifndef __FSL_MC_CMD_H
+-#define __FSL_MC_CMD_H
+-
+-#define MC_CMD_NUM_OF_PARAMS	7
+-
+-struct mc_cmd_header {
+-	u8 src_id;
+-	u8 flags_hw;
+-	u8 status;
+-	u8 flags_sw;
+-	__le16 token;
+-	__le16 cmd_id;
+-};
+-
+-struct mc_command {
+-	u64 header;
+-	u64 params[MC_CMD_NUM_OF_PARAMS];
+-};
+-
+-enum mc_cmd_status {
+-	MC_CMD_STATUS_OK = 0x0, /* Completed successfully */
+-	MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */
+-	MC_CMD_STATUS_AUTH_ERR = 0x3, /* Authentication error */
+-	MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /* No privilege */
+-	MC_CMD_STATUS_DMA_ERR = 0x5, /* DMA or I/O error */
+-	MC_CMD_STATUS_CONFIG_ERR = 0x6, /* Configuration error */
+-	MC_CMD_STATUS_TIMEOUT = 0x7, /* Operation timed out */
+-	MC_CMD_STATUS_NO_RESOURCE = 0x8, /* No resources */
+-	MC_CMD_STATUS_NO_MEMORY = 0x9, /* No memory available */
+-	MC_CMD_STATUS_BUSY = 0xA, /* Device is busy */
+-	MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /* Unsupported operation */
+-	MC_CMD_STATUS_INVALID_STATE = 0xC /* Invalid state */
+-};
+-
+-/*
+- * MC command flags
+- */
+-
+-/* High priority flag */
+-#define MC_CMD_FLAG_PRI		0x80
+-/* Command completion flag */
+-#define MC_CMD_FLAG_INTR_DIS	0x01
+-
+-#define MC_CMD_HDR_CMDID_MASK		0xFFF0
+-#define MC_CMD_HDR_CMDID_SHIFT		4
+-#define MC_CMD_HDR_TOKEN_MASK		0xFFC0
+-#define MC_CMD_HDR_TOKEN_SHIFT		6
+-
+-static inline u64 mc_encode_cmd_header(u16 cmd_id,
+-				       u32 cmd_flags,
+-				       u16 token)
+-{
+-	u64 header = 0;
+-	struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header;
+-
+-	hdr->cmd_id = cpu_to_le16((cmd_id << MC_CMD_HDR_CMDID_SHIFT) &
+-				  MC_CMD_HDR_CMDID_MASK);
+-	hdr->token = cpu_to_le16((token << MC_CMD_HDR_TOKEN_SHIFT) &
+-				 MC_CMD_HDR_TOKEN_MASK);
+-	hdr->status = MC_CMD_STATUS_READY;
+-	if (cmd_flags & MC_CMD_FLAG_PRI)
+-		hdr->flags_hw = MC_CMD_FLAG_PRI;
+-	if (cmd_flags & MC_CMD_FLAG_INTR_DIS)
+-		hdr->flags_sw = MC_CMD_FLAG_INTR_DIS;
+-
+-	return header;
+-}
+-
+-static inline u16 mc_cmd_hdr_read_token(struct mc_command *cmd)
+-{
+-	struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
+-	u16 token = le16_to_cpu(hdr->token);
+-
+-	return (token & MC_CMD_HDR_TOKEN_MASK) >> MC_CMD_HDR_TOKEN_SHIFT;
+-}
+-
+-#endif /* __FSL_MC_CMD_H */
+--- a/drivers/staging/fsl-mc/include/mc-sys.h
++++ /dev/null
+@@ -1,98 +0,0 @@
+-/* Copyright 2013-2014 Freescale Semiconductor Inc.
+- *
+- * Interface of the I/O services to send MC commands to the MC hardware
+- *
+- * Redistribution and use in source and binary forms, with or without
+- * modification, are permitted provided that the following conditions are met:
+- *     * Redistributions of source code must retain the above copyright
+- *       notice, this list of conditions and the following disclaimer.
+- *     * Redistributions in binary form must reproduce the above copyright
+- *       notice, this list of conditions and the following disclaimer in the
+- *       documentation and/or other materials provided with the distribution.
+- *     * Neither the name of the above-listed copyright holders nor the
+- *       names of any contributors may be used to endorse or promote products
+- *       derived from this software without specific prior written permission.
+- *
+- *
+- * ALTERNATIVELY, this software may be distributed under the terms of the
+- * GNU General Public License ("GPL") as published by the Free Software
+- * Foundation, either version 2 of that License or (at your option) any
+- * later version.
+- *
+- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+- * POSSIBILITY OF SUCH DAMAGE.
+- */
+-
+-#ifndef _FSL_MC_SYS_H
+-#define _FSL_MC_SYS_H
+-
+-#include <linux/types.h>
+-#include <linux/errno.h>
+-#include <linux/mutex.h>
+-#include <linux/spinlock.h>
+-
+-/**
+- * Bit masks for a MC I/O object (struct fsl_mc_io) flags
+- */
+-#define FSL_MC_IO_ATOMIC_CONTEXT_PORTAL	0x0001
+-
+-struct fsl_mc_resource;
+-struct mc_command;
+-
+-/**
+- * struct fsl_mc_io - MC I/O object to be passed-in to mc_send_command()
+- * @dev: device associated with this Mc I/O object
+- * @flags: flags for mc_send_command()
+- * @portal_size: MC command portal size in bytes
+- * @portal_phys_addr: MC command portal physical address
+- * @portal_virt_addr: MC command portal virtual address
+- * @dpmcp_dev: pointer to the DPMCP device associated with the MC portal.
+- *
+- * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not
+- * set:
+- * @mutex: Mutex to serialize mc_send_command() calls that use the same MC
+- * portal, if the fsl_mc_io object was created with the
+- * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag off. mc_send_command() calls for this
+- * fsl_mc_io object must be made only from non-atomic context.
+- *
+- * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is
+- * set:
+- * @spinlock: Spinlock to serialize mc_send_command() calls that use the same MC
+- * portal, if the fsl_mc_io object was created with the
+- * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag on. mc_send_command() calls for this
+- * fsl_mc_io object can be made from atomic or non-atomic context.
+- */
+-struct fsl_mc_io {
+-	struct device *dev;
+-	u16 flags;
+-	u16 portal_size;
+-	phys_addr_t portal_phys_addr;
+-	void __iomem *portal_virt_addr;
+-	struct fsl_mc_device *dpmcp_dev;
+-	union {
+-		/*
+-		 * This field is only meaningful if the
+-		 * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not set
+-		 */
+-		struct mutex mutex; /* serializes mc_send_command() */
+-
+-		/*
+-		 * This field is only meaningful if the
+-		 * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is set
+-		 */
+-		spinlock_t spinlock;	/* serializes mc_send_command() */
+-	};
+-};
+-
+-int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd);
+-
+-#endif /* _FSL_MC_SYS_H */
+--- a/drivers/staging/fsl-mc/include/mc.h
++++ /dev/null
+@@ -1,201 +0,0 @@
+-/*
+- * Freescale Management Complex (MC) bus public interface
+- *
+- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+- * Author: German Rivera <German.Rivera@freescale.com>
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- */
+-#ifndef _FSL_MC_H_
+-#define _FSL_MC_H_
+-
+-#include <linux/device.h>
+-#include <linux/mod_devicetable.h>
+-#include <linux/interrupt.h>
+-#include "../include/dprc.h"
+-
+-#define FSL_MC_VENDOR_FREESCALE	0x1957
+-
+-struct fsl_mc_device;
+-struct fsl_mc_io;
+-
+-/**
+- * struct fsl_mc_driver - MC object device driver object
+- * @driver: Generic device driver
+- * @match_id_table: table of supported device matching Ids
+- * @probe: Function called when a device is added
+- * @remove: Function called when a device is removed
+- * @shutdown: Function called at shutdown time to quiesce the device
+- * @suspend: Function called when a device is stopped
+- * @resume: Function called when a device is resumed
+- *
+- * Generic DPAA device driver object for device drivers that are registered
+- * with a DPRC bus. This structure is to be embedded in each device-specific
+- * driver structure.
+- */
+-struct fsl_mc_driver {
+-	struct device_driver driver;
+-	const struct fsl_mc_device_id *match_id_table;
+-	int (*probe)(struct fsl_mc_device *dev);
+-	int (*remove)(struct fsl_mc_device *dev);
+-	void (*shutdown)(struct fsl_mc_device *dev);
+-	int (*suspend)(struct fsl_mc_device *dev, pm_message_t state);
+-	int (*resume)(struct fsl_mc_device *dev);
+-};
+-
+-#define to_fsl_mc_driver(_drv) \
+-	container_of(_drv, struct fsl_mc_driver, driver)
+-
+-/**
+- * enum fsl_mc_pool_type - Types of allocatable MC bus resources
+- *
+- * Entries in these enum are used as indices in the array of resource
+- * pools of an fsl_mc_bus object.
+- */
+-enum fsl_mc_pool_type {
+-	FSL_MC_POOL_DPMCP = 0x0,    /* corresponds to "dpmcp" in the MC */
+-	FSL_MC_POOL_DPBP,	    /* corresponds to "dpbp" in the MC */
+-	FSL_MC_POOL_DPCON,	    /* corresponds to "dpcon" in the MC */
+-	FSL_MC_POOL_IRQ,
+-
+-	/*
+-	 * NOTE: New resource pool types must be added before this entry
+-	 */
+-	FSL_MC_NUM_POOL_TYPES
+-};
+-
+-/**
+- * struct fsl_mc_resource - MC generic resource
+- * @type: type of resource
+- * @id: unique MC resource Id within the resources of the same type
+- * @data: pointer to resource-specific data if the resource is currently
+- * allocated, or NULL if the resource is not currently allocated.
+- * @parent_pool: pointer to the parent resource pool from which this
+- * resource is allocated from.
+- * @node: Node in the free list of the corresponding resource pool
+- *
+- * NOTE: This structure is to be embedded as a field of specific
+- * MC resource structures.
+- */
+-struct fsl_mc_resource {
+-	enum fsl_mc_pool_type type;
+-	int32_t id;
+-	void *data;
+-	struct fsl_mc_resource_pool *parent_pool;
+-	struct list_head node;
+-};
+-
+-/**
+- * struct fsl_mc_device_irq - MC object device message-based interrupt
+- * @msi_desc: pointer to MSI descriptor allocated by fsl_mc_msi_alloc_descs()
+- * @mc_dev: MC object device that owns this interrupt
+- * @dev_irq_index: device-relative IRQ index
+- * @resource: MC generic resource associated with the interrupt
+- */
+-struct fsl_mc_device_irq {
+-	struct msi_desc *msi_desc;
+-	struct fsl_mc_device *mc_dev;
+-	u8 dev_irq_index;
+-	struct fsl_mc_resource resource;
+-};
+-
+-#define to_fsl_mc_irq(_mc_resource) \
+-	container_of(_mc_resource, struct fsl_mc_device_irq, resource)
+-
+-/**
+- * Bit masks for a MC object device (struct fsl_mc_device) flags
+- */
+-#define FSL_MC_IS_DPRC	0x0001
+-
+-/**
+- * struct fsl_mc_device - MC object device object
+- * @dev: Linux driver model device object
+- * @dma_mask: Default DMA mask
+- * @flags: MC object device flags
+- * @icid: Isolation context ID for the device
+- * @mc_handle: MC handle for the corresponding MC object opened
+- * @mc_io: Pointer to MC IO object assigned to this device or
+- * NULL if none.
+- * @obj_desc: MC description of the DPAA device
+- * @regions: pointer to array of MMIO region entries
+- * @irqs: pointer to array of pointers to interrupts allocated to this device
+- * @resource: generic resource associated with this MC object device, if any.
+- *
+- * Generic device object for MC object devices that are "attached" to a
+- * MC bus.
+- *
+- * NOTES:
+- * - For a non-DPRC object its icid is the same as its parent DPRC's icid.
+- * - The SMMU notifier callback gets invoked after device_add() has been
+- *   called for an MC object device, but before the device-specific probe
+- *   callback gets called.
+- * - DP_OBJ_DPRC objects are the only MC objects that have built-in MC
+- *   portals. For all other MC objects, their device drivers are responsible for
+- *   allocating MC portals for them by calling fsl_mc_portal_allocate().
+- * - Some types of MC objects (e.g., DP_OBJ_DPBP, DP_OBJ_DPCON) are
+- *   treated as resources that can be allocated/deallocated from the
+- *   corresponding resource pool in the object's parent DPRC, using the
+- *   fsl_mc_object_allocate()/fsl_mc_object_free() functions. These MC objects
+- *   are known as "allocatable" objects. For them, the corresponding
+- *   fsl_mc_device's 'resource' points to the associated resource object.
+- *   For MC objects that are not allocatable (e.g., DP_OBJ_DPRC, DP_OBJ_DPNI),
+- *   'resource' is NULL.
+- */
+-struct fsl_mc_device {
+-	struct device dev;
+-	u64 dma_mask;
+-	u16 flags;
+-	u16 icid;
+-	u16 mc_handle;
+-	struct fsl_mc_io *mc_io;
+-	struct dprc_obj_desc obj_desc;
+-	struct resource *regions;
+-	struct fsl_mc_device_irq **irqs;
+-	struct fsl_mc_resource *resource;
+-};
+-
+-#define to_fsl_mc_device(_dev) \
+-	container_of(_dev, struct fsl_mc_device, dev)
+-
+-/*
+- * module_fsl_mc_driver() - Helper macro for drivers that don't do
+- * anything special in module init/exit.  This eliminates a lot of
+- * boilerplate.  Each module may only use this macro once, and
+- * calling it replaces module_init() and module_exit()
+- */
+-#define module_fsl_mc_driver(__fsl_mc_driver) \
+-	module_driver(__fsl_mc_driver, fsl_mc_driver_register, \
+-		      fsl_mc_driver_unregister)
+-
+-/*
+- * Macro to avoid include chaining to get THIS_MODULE
+- */
+-#define fsl_mc_driver_register(drv) \
+-	__fsl_mc_driver_register(drv, THIS_MODULE)
+-
+-int __must_check __fsl_mc_driver_register(struct fsl_mc_driver *fsl_mc_driver,
+-					  struct module *owner);
+-
+-void fsl_mc_driver_unregister(struct fsl_mc_driver *driver);
+-
+-int __must_check fsl_mc_portal_allocate(struct fsl_mc_device *mc_dev,
+-					u16 mc_io_flags,
+-					struct fsl_mc_io **new_mc_io);
+-
+-void fsl_mc_portal_free(struct fsl_mc_io *mc_io);
+-
+-int fsl_mc_portal_reset(struct fsl_mc_io *mc_io);
+-
+-int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev,
+-					enum fsl_mc_pool_type pool_type,
+-					struct fsl_mc_device **new_mc_adev);
+-
+-void fsl_mc_object_free(struct fsl_mc_device *mc_adev);
+-
+-int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev);
+-
+-void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
+-
+-#endif /* _FSL_MC_H_ */
 --- /dev/null
 +++ b/include/linux/fsl/mc.h
-@@ -0,0 +1,1020 @@
+@@ -0,0 +1,1025 @@
 +/* SPDX-License-Identifier: GPL-2.0 */
 +/*
 + * Freescale Management Complex (MC) bus public interface
@@ -11416,6 +19392,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
 +
++void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
++	struct device_node *fsl_mc_platform_node, int coherent);
++
 +extern struct bus_type fsl_mc_bus_type;
 +
 +extern struct device_type fsl_mc_bus_dprc_type;
@@ -11794,6 +19773,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	DPRC_REGION_TYPE_QBMAN_PORTAL
 +};
 +
++#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY       0x0001
++
 +/**
 + * struct dprc_region_desc - Mappable region descriptor
 + * @base_offset: Region offset from region's base address.
diff --git a/target/linux/layerscape/patches-4.9/705-dpaa2-support-layerscape.patch b/target/linux/layerscape/patches-4.9/705-dpaa2-support-layerscape.patch
new file mode 100644
index 000000000..23e4ff920
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/705-dpaa2-support-layerscape.patch
@@ -0,0 +1,23038 @@
+From 77cc39e936f87463f92f7fddaaf0de51eec3972f Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Fri, 6 Jul 2018 15:30:21 +0800
+Subject: [PATCH] dpaa2: support layerscape
+
+This is an integrated patch for layerscape dpaa2 support.
+
+Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
+Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
+Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
+Signed-off-by: costi <constantin.tudor@freescale.com>
+Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
+Signed-off-by: Mathew McBride <matt@traverse.com.au>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/soc/fsl/ls2-console/Kconfig           |    4 +
+ drivers/soc/fsl/ls2-console/Makefile          |    1 +
+ drivers/soc/fsl/ls2-console/ls2-console.c     |  284 ++
+ drivers/staging/fsl-dpaa2/ethernet/Makefile   |   12 +
+ drivers/staging/fsl-dpaa2/ethernet/README     |  186 +
+ drivers/staging/fsl-dpaa2/ethernet/TODO       |   18 +
+ .../fsl-dpaa2/ethernet/dpaa2-eth-ceetm.c      | 1253 ++++++
+ .../fsl-dpaa2/ethernet/dpaa2-eth-ceetm.h      |  182 +
+ .../fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c    |  357 ++
+ .../fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h    |   60 +
+ .../fsl-dpaa2/ethernet/dpaa2-eth-trace.h      |  185 +
+ .../staging/fsl-dpaa2/ethernet/dpaa2-eth.c    | 3734 +++++++++++++++++
+ .../staging/fsl-dpaa2/ethernet/dpaa2-eth.h    |  601 +++
+ .../fsl-dpaa2/ethernet/dpaa2-ethtool.c        |  878 ++++
+ drivers/staging/fsl-dpaa2/ethernet/dpkg.h     |  176 +
+ drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h |  719 ++++
+ drivers/staging/fsl-dpaa2/ethernet/dpni.c     | 2112 ++++++++++
+ drivers/staging/fsl-dpaa2/ethernet/dpni.h     | 1172 ++++++
+ drivers/staging/fsl-dpaa2/ethernet/net.h      |  480 +++
+ drivers/staging/fsl-dpaa2/ethsw/Makefile      |   10 +
+ drivers/staging/fsl-dpaa2/ethsw/README        |  106 +
+ drivers/staging/fsl-dpaa2/ethsw/TODO          |   14 +
+ drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h    |  359 ++
+ drivers/staging/fsl-dpaa2/ethsw/dpsw.c        | 1165 +++++
+ drivers/staging/fsl-dpaa2/ethsw/dpsw.h        |  592 +++
+ .../staging/fsl-dpaa2/ethsw/ethsw-ethtool.c   |  206 +
+ drivers/staging/fsl-dpaa2/ethsw/ethsw.c       | 1438 +++++++
+ drivers/staging/fsl-dpaa2/ethsw/ethsw.h       |   90 +
+ drivers/staging/fsl-dpaa2/evb/Kconfig         |    7 +
+ drivers/staging/fsl-dpaa2/evb/Makefile        |   10 +
+ drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h    |  279 ++
+ drivers/staging/fsl-dpaa2/evb/dpdmux.c        | 1111 +++++
+ drivers/staging/fsl-dpaa2/evb/dpdmux.h        |  453 ++
+ drivers/staging/fsl-dpaa2/evb/evb.c           | 1354 ++++++
+ drivers/staging/fsl-dpaa2/mac/Kconfig         |   23 +
+ drivers/staging/fsl-dpaa2/mac/Makefile        |   10 +
+ drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h     |  172 +
+ drivers/staging/fsl-dpaa2/mac/dpmac.c         |  619 +++
+ drivers/staging/fsl-dpaa2/mac/dpmac.h         |  342 ++
+ drivers/staging/fsl-dpaa2/mac/mac.c           |  673 +++
+ drivers/staging/fsl-dpaa2/rtc/Makefile        |   10 +
+ drivers/staging/fsl-dpaa2/rtc/dprtc-cmd.h     |  160 +
+ drivers/staging/fsl-dpaa2/rtc/dprtc.c         |  746 ++++
+ drivers/staging/fsl-dpaa2/rtc/dprtc.h         |  172 +
+ drivers/staging/fsl-dpaa2/rtc/rtc.c           |  242 ++
+ include/linux/filter.h                        |    3 +
+ 46 files changed, 22780 insertions(+)
+ create mode 100644 drivers/soc/fsl/ls2-console/Kconfig
+ create mode 100644 drivers/soc/fsl/ls2-console/Makefile
+ create mode 100644 drivers/soc/fsl/ls2-console/ls2-console.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/Makefile
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/README
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/TODO
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-ceetm.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-ceetm.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-trace.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpkg.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpni.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/dpni.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethernet/net.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/Makefile
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/README
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/TODO
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/dpsw.h
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/ethsw.c
+ create mode 100644 drivers/staging/fsl-dpaa2/ethsw/ethsw.h
+ create mode 100644 drivers/staging/fsl-dpaa2/evb/Kconfig
+ create mode 100644 drivers/staging/fsl-dpaa2/evb/Makefile
+ create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h
+ create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux.c
+ create mode 100644 drivers/staging/fsl-dpaa2/evb/dpdmux.h
+ create mode 100644 drivers/staging/fsl-dpaa2/evb/evb.c
+ create mode 100644 drivers/staging/fsl-dpaa2/mac/Kconfig
+ create mode 100644 drivers/staging/fsl-dpaa2/mac/Makefile
+ create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h
+ create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac.c
+ create mode 100644 drivers/staging/fsl-dpaa2/mac/dpmac.h
+ create mode 100644 drivers/staging/fsl-dpaa2/mac/mac.c
+ create mode 100644 drivers/staging/fsl-dpaa2/rtc/Makefile
+ create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc-cmd.h
+ create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc.c
+ create mode 100644 drivers/staging/fsl-dpaa2/rtc/dprtc.h
+ create mode 100644 drivers/staging/fsl-dpaa2/rtc/rtc.c
+
+--- /dev/null
++++ b/drivers/soc/fsl/ls2-console/Kconfig
+@@ -0,0 +1,4 @@
++config FSL_LS2_CONSOLE
++        tristate "Layerscape MC and AIOP console support"
++	depends on ARCH_LAYERSCAPE
++        default y
+--- /dev/null
++++ b/drivers/soc/fsl/ls2-console/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_FSL_LS2_CONSOLE) += ls2-console.o
+--- /dev/null
++++ b/drivers/soc/fsl/ls2-console/ls2-console.c
+@@ -0,0 +1,284 @@
++/* Copyright 2015-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/miscdevice.h>
++#include <linux/uaccess.h>
++#include <linux/poll.h>
++#include <linux/compat.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++
++/* SoC address for the MC firmware base low/high registers */
++#define SOC_CCSR_MC_FW_BASE_ADDR_REGS 0x8340020
++#define SOC_CCSR_MC_FW_BASE_ADDR_REGS_SIZE 2
++/* MC firmware base low/high registers indexes */
++#define MCFBALR_OFFSET 0
++#define MCFBAHR_OFFSET 1
++
++/* Bit mask used to obtain the most significant part of the MC base address */
++#define MC_FW_HIGH_ADDR_MASK 0x1FFFF
++/* Bit mask used to obtain the least significant part of the MC base address */
++#define MC_FW_LOW_ADDR_MASK 0xE0000000
++
++#define MC_BUFFER_OFFSET 0x01000000
++#define MC_BUFFER_SIZE (1024*1024*16)
++#define MC_OFFSET_DELTA (MC_BUFFER_OFFSET)
++
++#define AIOP_BUFFER_OFFSET 0x06000000
++#define AIOP_BUFFER_SIZE (1024*1024*16)
++#define AIOP_OFFSET_DELTA (0)
++
++struct log_header {
++	char magic_word[8]; /* magic word */
++	uint32_t buf_start; /* holds the 32-bit little-endian
++			     * offset of the start of the buffer
++			     */
++	uint32_t buf_length; /* holds the 32-bit little-endian
++			      * length of the buffer
++			      */
++	uint32_t last_byte; /* holds the 32-bit little-endian offset
++			     * of the byte after the last byte that
++			     * was written
++			     */
++	char reserved[44];
++};
++
++#define LOG_HEADER_FLAG_BUFFER_WRAPAROUND 0x80000000
++#define LOG_VERSION_MAJOR 1
++#define LOG_VERSION_MINOR 0
++
++
++#define invalidate(p) { asm volatile("dc ivac, %0" : : "r" (p) : "memory"); }
++
++struct console_data {
++	char *map_addr;
++	struct log_header *hdr;
++	char *start_addr; /* Start of buffer */
++	char *end_addr; /* End of buffer */
++	char *end_of_data; /* Current end of data */
++	char *cur_ptr; /* Last data sent to console */
++};
++
++#define LAST_BYTE(a) ((a) & ~(LOG_HEADER_FLAG_BUFFER_WRAPAROUND))
++
++static inline void __adjust_end(struct console_data *cd)
++{
++	cd->end_of_data = cd->start_addr
++				+ LAST_BYTE(le32_to_cpu(cd->hdr->last_byte));
++}
++
++static inline void adjust_end(struct console_data *cd)
++{
++	invalidate(cd->hdr);
++	__adjust_end(cd);
++}
++
++static inline uint64_t get_mc_fw_base_address(void)
++{
++	u32 *mcfbaregs = (u32 *) ioremap(SOC_CCSR_MC_FW_BASE_ADDR_REGS,
++					 SOC_CCSR_MC_FW_BASE_ADDR_REGS_SIZE);
++	u64 mcfwbase = 0ULL;
++
++	mcfwbase  = readl(mcfbaregs + MCFBAHR_OFFSET) & MC_FW_HIGH_ADDR_MASK;
++	mcfwbase <<= 32;
++	mcfwbase |= readl(mcfbaregs + MCFBALR_OFFSET) & MC_FW_LOW_ADDR_MASK;
++	iounmap(mcfbaregs);
++	pr_info("fsl-ls2-console: MC base address at 0x%016llx\n", mcfwbase);
++	return mcfwbase;
++}
++
++static int fsl_ls2_generic_console_open(struct inode *node, struct file *fp,
++				u64 offset, u64 size,
++				uint8_t *emagic, uint8_t magic_len,
++				u32 offset_delta)
++{
++	struct console_data *cd;
++	uint8_t *magic;
++	uint32_t wrapped;
++
++	cd = kmalloc(sizeof(*cd), GFP_KERNEL);
++	if (cd == NULL)
++		return -ENOMEM;
++	fp->private_data = cd;
++	cd->map_addr = ioremap(get_mc_fw_base_address() + offset, size);
++
++	cd->hdr = (struct log_header *) cd->map_addr;
++	invalidate(cd->hdr);
++
++	magic = cd->hdr->magic_word;
++	if (memcmp(magic, emagic, magic_len)) {
++		pr_info("magic didn't match!\n");
++		pr_info("expected: %02x %02x %02x %02x %02x %02x %02x %02x\n",
++				emagic[0], emagic[1], emagic[2], emagic[3],
++				emagic[4], emagic[5], emagic[6], emagic[7]);
++		pr_info("    seen: %02x %02x %02x %02x %02x %02x %02x %02x\n",
++				magic[0], magic[1], magic[2], magic[3],
++				magic[4], magic[5], magic[6], magic[7]);
++		kfree(cd);
++		iounmap(cd->map_addr);
++		return -EIO;
++	}
++
++	cd->start_addr = cd->map_addr
++			 + le32_to_cpu(cd->hdr->buf_start) - offset_delta;
++	cd->end_addr = cd->start_addr + le32_to_cpu(cd->hdr->buf_length);
++
++	wrapped = le32_to_cpu(cd->hdr->last_byte)
++			 & LOG_HEADER_FLAG_BUFFER_WRAPAROUND;
++
++	__adjust_end(cd);
++	if (wrapped && (cd->end_of_data != cd->end_addr))
++		cd->cur_ptr = cd->end_of_data+1;
++	else
++		cd->cur_ptr = cd->start_addr;
++
++	return 0;
++}
++
++static int fsl_ls2_mc_console_open(struct inode *node, struct file *fp)
++{
++	uint8_t magic_word[] = { 0, 1, 'C', 'M' };
++
++	return fsl_ls2_generic_console_open(node, fp,
++			MC_BUFFER_OFFSET, MC_BUFFER_SIZE,
++			magic_word, sizeof(magic_word),
++			MC_OFFSET_DELTA);
++}
++
++static int fsl_ls2_aiop_console_open(struct inode *node, struct file *fp)
++{
++	uint8_t magic_word[] = { 'P', 'O', 'I', 'A' };
++
++	return fsl_ls2_generic_console_open(node, fp,
++			AIOP_BUFFER_OFFSET, AIOP_BUFFER_SIZE,
++			magic_word, sizeof(magic_word),
++			AIOP_OFFSET_DELTA);
++}
++
++static int fsl_ls2_console_close(struct inode *node, struct file *fp)
++{
++	struct console_data *cd = fp->private_data;
++
++	iounmap(cd->map_addr);
++	kfree(cd);
++	return 0;
++}
++
++ssize_t fsl_ls2_console_read(struct file *fp, char __user *buf, size_t count,
++			     loff_t *f_pos)
++{
++	struct console_data *cd = fp->private_data;
++	size_t bytes = 0;
++	char data;
++
++	/* Check if we need to adjust the end of data addr */
++	adjust_end(cd);
++
++	while ((count != bytes) && (cd->end_of_data != cd->cur_ptr)) {
++		if (((u64)cd->cur_ptr) % 64 == 0)
++			invalidate(cd->cur_ptr);
++
++		data = *(cd->cur_ptr);
++		if (copy_to_user(&buf[bytes], &data, 1))
++			return -EFAULT;
++		cd->cur_ptr++;
++		if (cd->cur_ptr >= cd->end_addr)
++			cd->cur_ptr = cd->start_addr;
++		++bytes;
++	}
++	return bytes;
++}
++
++static const struct file_operations fsl_ls2_mc_console_fops = {
++	.owner          = THIS_MODULE,
++	.open           = fsl_ls2_mc_console_open,
++	.release        = fsl_ls2_console_close,
++	.read           = fsl_ls2_console_read,
++};
++
++static struct miscdevice fsl_ls2_mc_console_dev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "fsl_mc_console",
++	.fops = &fsl_ls2_mc_console_fops
++};
++
++static const struct file_operations fsl_ls2_aiop_console_fops = {
++	.owner          = THIS_MODULE,
++	.open           = fsl_ls2_aiop_console_open,
++	.release        = fsl_ls2_console_close,
++	.read           = fsl_ls2_console_read,
++};
++
++static struct miscdevice fsl_ls2_aiop_console_dev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "fsl_aiop_console",
++	.fops = &fsl_ls2_aiop_console_fops
++};
++
++static int __init fsl_ls2_console_init(void)
++{
++	int err = 0;
++
++	pr_info("Freescale LS2 console driver\n");
++	err = misc_register(&fsl_ls2_mc_console_dev);
++	if (err) {
++		pr_err("fsl_mc_console: cannot register device\n");
++		return err;
++	}
++	pr_info("fsl-ls2-console: device %s registered\n",
++		fsl_ls2_mc_console_dev.name);
++
++	err = misc_register(&fsl_ls2_aiop_console_dev);
++	if (err) {
++		pr_err("fsl_aiop_console: cannot register device\n");
++		return err;
++	}
++	pr_info("fsl-ls2-console: device %s registered\n",
++		fsl_ls2_aiop_console_dev.name);
++
++	return 0;
++}
++
++static void __exit fsl_ls2_console_exit(void)
++{
++	misc_deregister(&fsl_ls2_mc_console_dev);
++
++	misc_deregister(&fsl_ls2_aiop_console_dev);
++}
++
++module_init(fsl_ls2_console_init);
++module_exit(fsl_ls2_console_exit);
++
++MODULE_AUTHOR("Roy Pledge <roy.pledge@freescale.com>");
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("Freescale LS2 console driver");
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/Makefile
+@@ -0,0 +1,12 @@
++#
++# Makefile for the Freescale DPAA2 Ethernet controller
++#
++
++obj-$(CONFIG_FSL_DPAA2_ETH) += fsl-dpaa2-eth.o
++
++fsl-dpaa2-eth-objs    := dpaa2-eth.o dpaa2-ethtool.o dpni.o
++fsl-dpaa2-eth-${CONFIG_FSL_DPAA2_ETH_DEBUGFS} += dpaa2-eth-debugfs.o
++fsl-dpaa2-eth-${CONFIG_FSL_DPAA2_ETH_CEETM} += dpaa2-eth-ceetm.o
++
++# Needed by the tracing framework
++CFLAGS_dpaa2-eth.o := -I$(src)
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/README
+@@ -0,0 +1,186 @@
++Freescale DPAA2 Ethernet driver
++===============================
++
++This file provides documentation for the Freescale DPAA2 Ethernet driver.
++
++
++Contents
++========
++	Supported Platforms
++	Architecture Overview
++	Creating a Network Interface
++	Features & Offloads
++
++
++Supported Platforms
++===================
++This driver provides networking support for Freescale DPAA2 SoCs, e.g.
++LS2080A, LS2088A, LS1088A.
++
++
++Architecture Overview
++=====================
++Unlike regular NICs, in the DPAA2 architecture there is no single hardware block
++representing network interfaces; instead, several separate hardware resources
++concur to provide the networking functionality:
++        - network interfaces
++        - queues, channels
++        - buffer pools
++        - MAC/PHY
++
++All hardware resources are allocated and configured through the Management
++Complex (MC) portals. MC abstracts most of these resources as DPAA2 objects
++and exposes ABIs through which they can be configured and controlled. A few
++hardware resources, like queues, do not have a corresponding MC object and
++are treated as internal resources of other objects.
++
++For a more detailed description of the DPAA2 architecture and its object
++abstractions see:
++	drivers/staging/fsl-mc/README.txt
++
++Each Linux net device is built on top of a Datapath Network Interface (DPNI)
++object and uses Buffer Pools (DPBPs), I/O Portals (DPIOs) and Concentrators
++(DPCONs).
++
++Configuration interface:
++
++                 -----------------------
++                | DPAA2 Ethernet Driver |
++                 -----------------------
++                     .      .      .
++                     .      .      .
++             . . . . .      .      . . . . . .
++             .              .                .
++             .              .                .
++         ----------     ----------      -----------
++        | DPBP API |   | DPNI API |    | DPCON API |
++         ----------     ----------      -----------
++             .              .                .             software
++===========  .  ==========  .  ============  .  ===================
++             .              .                .             hardware
++         ------------------------------------------
++        |            MC hardware portals           |
++         ------------------------------------------
++             .              .                .
++             .              .                .
++          ------         ------            -------
++         | DPBP |       | DPNI |          | DPCON |
++          ------         ------            -------
++
++The DPNIs are network interfaces without a direct one-on-one mapping to PHYs.
++DPBPs represent hardware buffer pools. Packet I/O is performed in the context
++of DPCON objects, using DPIO portals for managing and communicating with the
++hardware resources.
++
++Datapath (I/O) interface:
++
++         -----------------------------------------------
++        |           DPAA2 Ethernet Driver               |
++          -----------------------------------------------
++          |          ^        ^         |            |
++          |          |        |         |            |
++   enqueue|   dequeue|   data |  dequeue|       seed |
++    (Tx)  | (Rx, TxC)|  avail.|  request|     buffers|
++          |          |  notify|         |            |
++          |          |        |         |            |
++          V          |        |         V            V
++         -----------------------------------------------
++        |                 DPIO Driver                   |
++         -----------------------------------------------
++          |          |        |         |            |          software
++          |          |        |         |            |  ================
++          |          |        |         |            |          hardware
++         -----------------------------------------------
++        |               I/O hardware portals            |
++         -----------------------------------------------
++          |          ^        ^         |            |
++          |          |        |         |            |
++          |          |        |         V            |
++          V          |    ================           V
++        ----------------------           |      -------------
++ queues  ----------------------          |     | Buffer pool |
++          ----------------------         |      -------------
++                   =======================
++                                Channel
++
++Datapath I/O (DPIO) portals provide enqueue and dequeue services, data
++availability notifications and buffer pool management. DPIOs are shared between
++all DPAA2 objects (and implicitly all DPAA2 kernel drivers) that work with data
++frames, but must be affine to the CPUs for the purpose of traffic distribution.
++
++Frames are transmitted and received through hardware frame queues, which can be
++grouped in channels for the purpose of hardware scheduling. The Ethernet driver
++enqueues TX frames on egress queues and after transmission is complete a TX
++confirmation frame is sent back to the CPU.
++
++When frames are available on ingress queues, a data availability notification
++is sent to the CPU; notifications are raised per channel, so even if multiple
++queues in the same channel have available frames, only one notification is sent.
++After a channel fires a notification, is must be explicitly rearmed.
++
++Each network interface can have multiple Rx, Tx and confirmation queues affined
++to CPUs, and one channel (DPCON) for each CPU that services at least one queue.
++DPCONs are used to distribute ingress traffic to different CPUs via the cores'
++affine DPIOs.
++
++The role of hardware buffer pools is storage of ingress frame data. Each network
++interface has a privately owned buffer pool which it seeds with kernel allocated
++buffers.
++
++
++DPNIs are decoupled from PHYs; a DPNI can be connected to a PHY through a DPMAC
++object or to another DPNI through an internal link, but the connection is
++managed by MC and completely transparent to the Ethernet driver.
++
++     ---------     ---------     ---------
++    | eth if1 |   | eth if2 |   | eth ifn |
++     ---------     ---------     ---------
++          .           .          .
++          .           .          .
++          .           .          .
++         ---------------------------
++        |   DPAA2 Ethernet Driver   |
++         ---------------------------
++          .           .          .
++          .           .          .
++          .           .          .
++       ------      ------      ------            -------
++      | DPNI |    | DPNI |    | DPNI |          | DPMAC |----+
++       ------      ------      ------            -------     |
++         |           |           |                  |        |
++         |           |           |                  |      -----
++          ===========             ==================      | PHY |
++                                                           -----
++
++Creating a Network Interface
++============================
++A net device is created for each DPNI object probed on the MC bus. Each DPNI has
++a number of properties which determine the network interface configuration
++options and associated hardware resources.
++
++DPNI objects (and the other DPAA2 objects needed for a network interface) can be
++added to a container on the MC bus in one of two ways: statically, through a
++Datapath Layout Binary file (DPL) that is parsed by MC at boot time; or created
++dynamically at runtime, via the DPAA2 objects APIs.
++
++
++Features & Offloads
++===================
++Hardware checksum offloading is supported for TCP and UDP over IPv4/6 frames.
++The checksum offloads can be independently configured on RX and TX through
++ethtool.
++
++Hardware offload of unicast and multicast MAC filtering is supported on the
++ingress path and permanently enabled.
++
++Scatter-gather frames are supported on both RX and TX paths. On TX, SG support
++is configurable via ethtool; on RX it is always enabled.
++
++The DPAA2 hardware can process jumbo Ethernet frames of up to 10K bytes.
++
++The Ethernet driver defines a static flow hashing scheme that distributes
++traffic based on a 5-tuple key: src IP, dst IP, IP proto, L4 src port,
++L4 dst port. No user configuration is supported for now.
++
++Hardware specific statistics for the network interface as well as some
++non-standard driver stats can be consulted through ethtool -S option.
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/TODO
+@@ -0,0 +1,18 @@
++* Add a DPAA2 MAC kernel driver in order to allow PHY management; currently
++  the DPMAC objects and their link to DPNIs are handled by MC internally
++  and all PHYs are seen as fixed-link
++* add more debug support: decide how to expose detailed debug statistics,
++  add ingress error queue support
++* MC firmware uprev; the DPAA2 objects used by the Ethernet driver need to
++  be kept in sync with binary interface changes in MC
++* refine README file
++* cleanup
++
++NOTE: None of the above is must-have before getting the DPAA2 Ethernet driver
++out of staging. The main requirement for that is to have the drivers it
++depends on, fsl-mc bus and DPIO driver, moved to drivers/bus and drivers/soc
++respectively.
++
++ Please send any patches to Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
++ ruxandra.radulescu@nxp.com, devel@driverdev.osuosl.org,
++ linux-kernel@vger.kernel.org
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-ceetm.c
+@@ -0,0 +1,1253 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright 2017 NXP
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++
++#include "dpaa2-eth-ceetm.h"
++#include "dpaa2-eth.h"
++
++#define DPAA2_CEETM_DESCRIPTION "FSL DPAA2 CEETM qdisc"
++/* Conversion formula from userspace passed Bps to expected Mbit */
++#define dpaa2_eth_bps_to_mbit(rate) (rate >> 17)
++
++static const struct nla_policy dpaa2_ceetm_policy[DPAA2_CEETM_TCA_MAX] = {
++	[DPAA2_CEETM_TCA_COPT] = { .len = sizeof(struct dpaa2_ceetm_tc_copt) },
++	[DPAA2_CEETM_TCA_QOPS] = { .len = sizeof(struct dpaa2_ceetm_tc_qopt) },
++};
++
++struct Qdisc_ops dpaa2_ceetm_qdisc_ops;
++
++static inline int dpaa2_eth_set_ch_shaping(struct dpaa2_eth_priv *priv,
++					   struct dpni_tx_shaping_cfg *scfg,
++					   struct dpni_tx_shaping_cfg *ecfg,
++					   int coupled, int ch_id)
++{
++	int err = 0;
++
++	netdev_dbg(priv->net_dev, "%s: ch_id %d rate %d mbps\n", __func__,
++		   ch_id, scfg->rate_limit);
++	err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, scfg,
++				  ecfg, coupled);
++	if (err)
++		netdev_err(priv->net_dev, "dpni_set_tx_shaping err\n");
++
++	return err;
++}
++
++static inline int dpaa2_eth_reset_ch_shaping(struct dpaa2_eth_priv *priv,
++					     int ch_id)
++{
++	struct dpni_tx_shaping_cfg cfg = { 0 };
++
++	return dpaa2_eth_set_ch_shaping(priv, &cfg, &cfg, 0, ch_id);
++}
++
++static inline int
++dpaa2_eth_update_shaping_cfg(struct net_device *dev,
++			     struct dpaa2_ceetm_shaping_cfg cfg,
++			     struct dpni_tx_shaping_cfg *scfg,
++			     struct dpni_tx_shaping_cfg *ecfg)
++{
++	scfg->rate_limit = dpaa2_eth_bps_to_mbit(cfg.cir);
++	ecfg->rate_limit = dpaa2_eth_bps_to_mbit(cfg.eir);
++
++	if (cfg.cbs > DPAA2_ETH_MAX_BURST_SIZE) {
++		netdev_err(dev, "Committed burst size must be under %d\n",
++			   DPAA2_ETH_MAX_BURST_SIZE);
++		return -EINVAL;
++	}
++
++	scfg->max_burst_size = cfg.cbs;
++
++	if (cfg.ebs > DPAA2_ETH_MAX_BURST_SIZE) {
++		netdev_err(dev, "Excess burst size must be under %d\n",
++			   DPAA2_ETH_MAX_BURST_SIZE);
++		return -EINVAL;
++	}
++
++	ecfg->max_burst_size = cfg.ebs;
++
++	if ((!cfg.cir || !cfg.eir) && cfg.coupled) {
++		netdev_err(dev, "Coupling can be set when both CIR and EIR are finite\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++enum update_tx_prio {
++	DPAA2_ETH_ADD_CQ,
++	DPAA2_ETH_DEL_CQ,
++};
++
++/* Normalize weights based on max passed value */
++static inline int dpaa2_eth_normalize_tx_prio(struct dpaa2_ceetm_qdisc *priv)
++{
++	struct dpni_tx_schedule_cfg *sched_cfg;
++	struct dpaa2_ceetm_class *cl;
++	u32 qpri;
++	u16 weight_max = 0, increment;
++	int i;
++
++	/* Check the boundaries of the provided values */
++	for (i = 0; i < priv->clhash.hashsize; i++)
++		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode)
++			weight_max = (weight_max == 0 ? cl->prio.weight :
++				     (weight_max < cl->prio.weight ?
++				      cl->prio.weight : weight_max));
++
++	/* If there are no elements, there's nothing to do */
++	if (weight_max == 0)
++		return 0;
++
++	increment = (DPAA2_CEETM_MAX_WEIGHT - DPAA2_CEETM_MIN_WEIGHT) /
++		    weight_max;
++
++	for (i = 0; i < priv->clhash.hashsize; i++) {
++		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode) {
++			if (cl->prio.mode == STRICT_PRIORITY)
++				continue;
++
++			qpri = cl->prio.qpri;
++			sched_cfg = &priv->prio.tx_prio_cfg.tc_sched[qpri];
++
++			sched_cfg->delta_bandwidth =
++				DPAA2_CEETM_MIN_WEIGHT +
++				(cl->prio.weight * increment);
++
++			pr_debug("%s: Normalized CQ qpri %d weight to %d\n",
++				 __func__, qpri, sched_cfg->delta_bandwidth);
++		}
++	}
++
++	return 0;
++}
++
++static inline int dpaa2_eth_update_tx_prio(struct dpaa2_eth_priv *priv,
++					   struct dpaa2_ceetm_class *cl,
++					   enum update_tx_prio type)
++{
++	struct dpaa2_ceetm_qdisc *sch = qdisc_priv(cl->parent);
++	struct dpni_congestion_notification_cfg notif_cfg = {0};
++	struct dpni_tx_schedule_cfg *sched_cfg;
++	struct dpni_taildrop td = {0};
++	u8 ch_id = 0, tc_id = 0;
++	u32 qpri = 0;
++	int err = 0;
++
++	qpri = cl->prio.qpri;
++	tc_id = DPNI_BUILD_CH_TC(ch_id, qpri);
++
++	switch (type) {
++	case DPAA2_ETH_ADD_CQ:
++		/* Disable congestion notifications */
++		notif_cfg.threshold_entry = 0;
++		notif_cfg.threshold_exit = 0;
++		err = dpni_set_congestion_notification(priv->mc_io, 0,
++						       priv->mc_token,
++						       DPNI_QUEUE_TX, tc_id,
++						       &notif_cfg);
++		if (err) {
++			netdev_err(priv->net_dev, "Error disabling congestion notifications %d\n",
++				   err);
++			return err;
++		}
++		/* Enable taildrop */
++		td.enable = 1;
++		td.units = DPNI_CONGESTION_UNIT_FRAMES;
++		td.threshold = DPAA2_CEETM_TD_THRESHOLD;
++		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
++					DPNI_CP_GROUP, DPNI_QUEUE_TX, tc_id,
++					0, &td);
++		if (err) {
++			netdev_err(priv->net_dev, "Error enabling Tx taildrop %d\n",
++				   err);
++			return err;
++		}
++		break;
++	case DPAA2_ETH_DEL_CQ:
++		/* Disable taildrop */
++		td.enable = 0;
++		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
++					DPNI_CP_GROUP, DPNI_QUEUE_TX, tc_id,
++					0, &td);
++		if (err) {
++			netdev_err(priv->net_dev, "Error disabling Tx taildrop %d\n",
++				   err);
++			return err;
++		}
++		/* Enable congestion notifications */
++		notif_cfg.units = DPNI_CONGESTION_UNIT_BYTES;
++		notif_cfg.threshold_entry = DPAA2_ETH_TX_CONG_ENTRY_THRESH;
++		notif_cfg.threshold_exit = DPAA2_ETH_TX_CONG_EXIT_THRESH;
++		notif_cfg.message_ctx = (u64)priv;
++		notif_cfg.message_iova = priv->cscn_dma;
++		notif_cfg.notification_mode = DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
++					      DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
++					      DPNI_CONG_OPT_COHERENT_WRITE;
++		err = dpni_set_congestion_notification(priv->mc_io, 0,
++						       priv->mc_token,
++						       DPNI_QUEUE_TX, tc_id,
++						       &notif_cfg);
++		if (err) {
++			netdev_err(priv->net_dev, "Error enabling congestion notifications %d\n",
++				   err);
++			return err;
++		}
++		break;
++	}
++
++	/* We can zero out the structure in the tx_prio_conf array */
++	if (type == DPAA2_ETH_DEL_CQ) {
++		sched_cfg = &sch->prio.tx_prio_cfg.tc_sched[qpri];
++		memset(sched_cfg, 0, sizeof(*sched_cfg));
++	}
++
++	/* Normalize priorities */
++	err = dpaa2_eth_normalize_tx_prio(sch);
++
++	/* Debug print goes here */
++	print_hex_dump_debug("tx_prio: ", DUMP_PREFIX_OFFSET, 16, 1,
++			     &sch->prio.tx_prio_cfg,
++			     sizeof(sch->prio.tx_prio_cfg), 0);
++
++	/* Call dpni_set_tx_priorities for the entire prio qdisc */
++	err = dpni_set_tx_priorities(priv->mc_io, 0, priv->mc_token,
++				     &sch->prio.tx_prio_cfg);
++	if (err)
++		netdev_err(priv->net_dev, "dpni_set_tx_priorities err %d\n",
++			   err);
++
++	return err;
++}
++
++static void dpaa2_eth_ceetm_enable(struct dpaa2_eth_priv *priv)
++{
++	priv->ceetm_en = true;
++}
++
++static void dpaa2_eth_ceetm_disable(struct dpaa2_eth_priv *priv)
++{
++	priv->ceetm_en = false;
++}
++
++/* Find class in qdisc hash table using given handle */
++static inline struct dpaa2_ceetm_class *dpaa2_ceetm_find(u32 handle,
++							 struct Qdisc *sch)
++{
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct Qdisc_class_common *clc;
++
++	pr_debug(KBUILD_BASENAME " : %s : find class %X in qdisc %X\n",
++		 __func__, handle, sch->handle);
++
++	clc = qdisc_class_find(&priv->clhash, handle);
++	return clc ? container_of(clc, struct dpaa2_ceetm_class, common) : NULL;
++}
++
++/* Insert a class in the qdisc's class hash */
++static void dpaa2_ceetm_link_class(struct Qdisc *sch,
++				   struct Qdisc_class_hash *clhash,
++				   struct Qdisc_class_common *common)
++{
++	sch_tree_lock(sch);
++	qdisc_class_hash_insert(clhash, common);
++	sch_tree_unlock(sch);
++	qdisc_class_hash_grow(sch, clhash);
++}
++
++/* Destroy a ceetm class */
++static void dpaa2_ceetm_cls_destroy(struct Qdisc *sch,
++				    struct dpaa2_ceetm_class *cl)
++{
++	struct net_device *dev = qdisc_dev(sch);
++	struct dpaa2_eth_priv *priv = netdev_priv(dev);
++
++	if (!cl)
++		return;
++
++	pr_debug(KBUILD_BASENAME " : %s : destroy class %X from under %X\n",
++		 __func__, cl->common.classid, sch->handle);
++
++	/* Recurse into child first */
++	if (cl->child) {
++		qdisc_destroy(cl->child);
++		cl->child = NULL;
++	}
++
++	switch (cl->type) {
++	case CEETM_ROOT:
++		if (dpaa2_eth_reset_ch_shaping(priv, cl->root.ch_id))
++			netdev_err(dev, "Error resetting channel shaping\n");
++
++		break;
++
++	case CEETM_PRIO:
++		if (dpaa2_eth_update_tx_prio(priv, cl, DPAA2_ETH_DEL_CQ))
++			netdev_err(dev, "Error resetting tx_priorities\n");
++
++		if (cl->prio.cstats)
++			free_percpu(cl->prio.cstats);
++
++		break;
++	}
++
++	tcf_destroy_chain(&cl->filter_list);
++	kfree(cl);
++}
++
++/* Destroy a ceetm qdisc */
++static void dpaa2_ceetm_destroy(struct Qdisc *sch)
++{
++	unsigned int i;
++	struct hlist_node *next;
++	struct dpaa2_ceetm_class *cl;
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct net_device *dev = qdisc_dev(sch);
++	struct dpaa2_eth_priv *priv_eth = netdev_priv(dev);
++
++	pr_debug(KBUILD_BASENAME " : %s : destroy qdisc %X\n",
++		 __func__, sch->handle);
++
++	/* All filters need to be removed before destroying the classes */
++	tcf_destroy_chain(&priv->filter_list);
++
++	for (i = 0; i < priv->clhash.hashsize; i++) {
++		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode)
++			tcf_destroy_chain(&cl->filter_list);
++	}
++
++	for (i = 0; i < priv->clhash.hashsize; i++) {
++		hlist_for_each_entry_safe(cl, next, &priv->clhash.hash[i],
++					  common.hnode)
++			dpaa2_ceetm_cls_destroy(sch, cl);
++	}
++
++	qdisc_class_hash_destroy(&priv->clhash);
++
++	switch (priv->type) {
++	case CEETM_ROOT:
++		dpaa2_eth_ceetm_disable(priv_eth);
++
++		if (priv->root.qstats)
++			free_percpu(priv->root.qstats);
++
++		if (!priv->root.qdiscs)
++			break;
++
++		/* Destroy the pfifo qdiscs in case they haven't been attached
++		 * to the netdev queues yet.
++		 */
++		for (i = 0; i < dev->num_tx_queues; i++)
++			if (priv->root.qdiscs[i])
++				qdisc_destroy(priv->root.qdiscs[i]);
++
++		kfree(priv->root.qdiscs);
++		break;
++
++	case CEETM_PRIO:
++		if (priv->prio.parent)
++			priv->prio.parent->child = NULL;
++		break;
++	}
++}
++
++static int dpaa2_ceetm_dump(struct Qdisc *sch, struct sk_buff *skb)
++{
++	struct Qdisc *qdisc;
++	unsigned int ntx, i;
++	struct nlattr *nest;
++	struct dpaa2_ceetm_tc_qopt qopt;
++	struct dpaa2_ceetm_qdisc_stats *qstats;
++	struct net_device *dev = qdisc_dev(sch);
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++
++	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
++
++	sch_tree_lock(sch);
++	memset(&qopt, 0, sizeof(qopt));
++	qopt.type = priv->type;
++	qopt.shaped = priv->shaped;
++
++	switch (priv->type) {
++	case CEETM_ROOT:
++		/* Gather statistics from the underlying pfifo qdiscs */
++		sch->q.qlen = 0;
++		memset(&sch->bstats, 0, sizeof(sch->bstats));
++		memset(&sch->qstats, 0, sizeof(sch->qstats));
++
++		for (ntx = 0; ntx < dev->num_tx_queues; ntx++) {
++			qdisc = netdev_get_tx_queue(dev, ntx)->qdisc_sleeping;
++			sch->q.qlen		+= qdisc->q.qlen;
++			sch->bstats.bytes	+= qdisc->bstats.bytes;
++			sch->bstats.packets	+= qdisc->bstats.packets;
++			sch->qstats.qlen	+= qdisc->qstats.qlen;
++			sch->qstats.backlog	+= qdisc->qstats.backlog;
++			sch->qstats.drops	+= qdisc->qstats.drops;
++			sch->qstats.requeues	+= qdisc->qstats.requeues;
++			sch->qstats.overlimits	+= qdisc->qstats.overlimits;
++		}
++
++		for_each_online_cpu(i) {
++			qstats = per_cpu_ptr(priv->root.qstats, i);
++			sch->qstats.drops += qstats->drops;
++		}
++
++		break;
++
++	case CEETM_PRIO:
++		qopt.prio_group_A = priv->prio.tx_prio_cfg.prio_group_A;
++		qopt.prio_group_B = priv->prio.tx_prio_cfg.prio_group_B;
++		qopt.separate_groups = priv->prio.tx_prio_cfg.separate_groups;
++		break;
++
++	default:
++		pr_err(KBUILD_BASENAME " : %s : invalid qdisc\n", __func__);
++		sch_tree_unlock(sch);
++		return -EINVAL;
++	}
++
++	nest = nla_nest_start(skb, TCA_OPTIONS);
++	if (!nest)
++		goto nla_put_failure;
++	if (nla_put(skb, DPAA2_CEETM_TCA_QOPS, sizeof(qopt), &qopt))
++		goto nla_put_failure;
++	nla_nest_end(skb, nest);
++
++	sch_tree_unlock(sch);
++	return skb->len;
++
++nla_put_failure:
++	sch_tree_unlock(sch);
++	nla_nest_cancel(skb, nest);
++	return -EMSGSIZE;
++}
++
++static int dpaa2_ceetm_change_prio(struct Qdisc *sch,
++				   struct dpaa2_ceetm_qdisc *priv,
++				   struct dpaa2_ceetm_tc_qopt *qopt)
++{
++	/* TODO: Once LX2 support is added */
++	/* priv->shaped = parent_cl->shaped; */
++	priv->prio.tx_prio_cfg.prio_group_A = qopt->prio_group_A;
++	priv->prio.tx_prio_cfg.prio_group_B = qopt->prio_group_B;
++	priv->prio.tx_prio_cfg.separate_groups = qopt->separate_groups;
++
++	return 0;
++}
++
++/* Edit a ceetm qdisc */
++static int dpaa2_ceetm_change(struct Qdisc *sch, struct nlattr *opt)
++{
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct nlattr *tb[DPAA2_CEETM_TCA_QOPS + 1];
++	struct dpaa2_ceetm_tc_qopt *qopt;
++	int err;
++
++	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
++
++	err = nla_parse_nested(tb, DPAA2_CEETM_TCA_QOPS, opt,
++			       dpaa2_ceetm_policy);
++	if (err < 0) {
++		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
++		       "nla_parse_nested");
++		return err;
++	}
++
++	if (!tb[DPAA2_CEETM_TCA_QOPS]) {
++		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
++		       "tb");
++		return -EINVAL;
++	}
++
++	if (TC_H_MIN(sch->handle)) {
++		pr_err("CEETM: a qdisc should not have a minor\n");
++		return -EINVAL;
++	}
++
++	qopt = nla_data(tb[DPAA2_CEETM_TCA_QOPS]);
++
++	if (priv->type != qopt->type) {
++		pr_err("CEETM: qdisc %X is not of the provided type\n",
++		       sch->handle);
++		return -EINVAL;
++	}
++
++	switch (priv->type) {
++	case CEETM_PRIO:
++		err = dpaa2_ceetm_change_prio(sch, priv, qopt);
++		break;
++	default:
++		pr_err(KBUILD_BASENAME " : %s : invalid qdisc\n", __func__);
++		err = -EINVAL;
++	}
++
++	return err;
++}
++
++/* Configure a root ceetm qdisc */
++static int dpaa2_ceetm_init_root(struct Qdisc *sch,
++				 struct dpaa2_ceetm_qdisc *priv,
++				 struct dpaa2_ceetm_tc_qopt *qopt)
++{
++	struct net_device *dev = qdisc_dev(sch);
++	struct dpaa2_eth_priv *priv_eth = netdev_priv(dev);
++	struct netdev_queue *dev_queue;
++	unsigned int i, parent_id;
++	struct Qdisc *qdisc;
++	int err;
++
++	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
++
++	/* Validate inputs */
++	if (sch->parent != TC_H_ROOT) {
++		pr_err("CEETM: a root ceetm qdisc can not be attached to a class\n");
++		tcf_destroy_chain(&priv->filter_list);
++		qdisc_class_hash_destroy(&priv->clhash);
++		return -EINVAL;
++	}
++
++	/* Pre-allocate underlying pfifo qdiscs.
++	 *
++	 * We want to offload shaping and scheduling decisions to the hardware.
++	 * The pfifo qdiscs will be attached to the netdev queues and will
++	 * guide the traffic from the IP stack down to the driver with minimum
++	 * interference.
++	 *
++	 * The CEETM qdiscs and classes will be crossed when the traffic
++	 * reaches the driver.
++	 */
++	priv->root.qdiscs = kcalloc(dev->num_tx_queues,
++				    sizeof(priv->root.qdiscs[0]),
++				    GFP_KERNEL);
++	if (!priv->root.qdiscs) {
++		err = -ENOMEM;
++		goto err_init_root;
++	}
++
++	for (i = 0; i < dev->num_tx_queues; i++) {
++		dev_queue = netdev_get_tx_queue(dev, i);
++		parent_id = TC_H_MAKE(TC_H_MAJ(sch->handle),
++				      TC_H_MIN(i + PFIFO_MIN_OFFSET));
++
++		qdisc = qdisc_create_dflt(dev_queue, &pfifo_qdisc_ops,
++					  parent_id);
++		if (!qdisc) {
++			err = -ENOMEM;
++			goto err_init_root;
++		}
++
++		priv->root.qdiscs[i] = qdisc;
++		qdisc->flags |= TCQ_F_ONETXQUEUE;
++	}
++
++	sch->flags |= TCQ_F_MQROOT;
++
++	priv->root.qstats = alloc_percpu(struct dpaa2_ceetm_qdisc_stats);
++	if (!priv->root.qstats) {
++		pr_err(KBUILD_BASENAME " : %s : alloc_percpu() failed\n",
++		       __func__);
++		err = -ENOMEM;
++		goto err_init_root;
++	}
++
++	dpaa2_eth_ceetm_enable(priv_eth);
++	return 0;
++
++err_init_root:
++	dpaa2_ceetm_destroy(sch);
++	return err;
++}
++
++/* Configure a prio ceetm qdisc */
++static int dpaa2_ceetm_init_prio(struct Qdisc *sch,
++				 struct dpaa2_ceetm_qdisc *priv,
++				 struct dpaa2_ceetm_tc_qopt *qopt)
++{
++	struct net_device *dev = qdisc_dev(sch);
++	struct dpaa2_ceetm_class *parent_cl;
++	struct Qdisc *parent_qdisc;
++	int err;
++
++	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
++
++	if (sch->parent == TC_H_ROOT) {
++		pr_err("CEETM: a prio ceetm qdisc can not be root\n");
++		err = -EINVAL;
++		goto err_init_prio;
++	}
++
++	parent_qdisc = qdisc_lookup(dev, TC_H_MAJ(sch->parent));
++	if (strcmp(parent_qdisc->ops->id, dpaa2_ceetm_qdisc_ops.id)) {
++		pr_err("CEETM: a ceetm qdisc can not be attached to other qdisc/class types\n");
++		err = -EINVAL;
++		goto err_init_prio;
++	}
++
++	/* Obtain the parent root ceetm_class */
++	parent_cl = dpaa2_ceetm_find(sch->parent, parent_qdisc);
++
++	if (!parent_cl || parent_cl->type != CEETM_ROOT) {
++		pr_err("CEETM: a prio ceetm qdiscs can be added only under a root ceetm class\n");
++		err = -EINVAL;
++		goto err_init_prio;
++	}
++
++	priv->prio.parent = parent_cl;
++	parent_cl->child = sch;
++
++	err = dpaa2_ceetm_change_prio(sch, priv, qopt);
++
++	return 0;
++
++err_init_prio:
++	dpaa2_ceetm_destroy(sch);
++	return err;
++}
++
++/* Configure a generic ceetm qdisc */
++static int dpaa2_ceetm_init(struct Qdisc *sch, struct nlattr *opt)
++{
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct net_device *dev = qdisc_dev(sch);
++	struct nlattr *tb[DPAA2_CEETM_TCA_QOPS + 1];
++	struct dpaa2_ceetm_tc_qopt *qopt;
++	int err;
++
++	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
++
++	if (!netif_is_multiqueue(dev))
++		return -EOPNOTSUPP;
++
++	RCU_INIT_POINTER(priv->filter_list, NULL);
++
++	if (!opt) {
++		pr_err(KBUILD_BASENAME " : %s : tc error - opt = NULL\n",
++		       __func__);
++		return -EINVAL;
++	}
++
++	err = nla_parse_nested(tb, DPAA2_CEETM_TCA_QOPS, opt,
++			       dpaa2_ceetm_policy);
++	if (err < 0) {
++		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
++		       "nla_parse_nested");
++		return err;
++	}
++
++	if (!tb[DPAA2_CEETM_TCA_QOPS]) {
++		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
++		       "tb");
++		return -EINVAL;
++	}
++
++	if (TC_H_MIN(sch->handle)) {
++		pr_err("CEETM: a qdisc should not have a minor\n");
++		return -EINVAL;
++	}
++
++	qopt = nla_data(tb[DPAA2_CEETM_TCA_QOPS]);
++
++	/* Initialize the class hash list. Each qdisc has its own class hash */
++	err = qdisc_class_hash_init(&priv->clhash);
++	if (err < 0) {
++		pr_err(KBUILD_BASENAME " : %s : qdisc_class_hash_init failed\n",
++		       __func__);
++		return err;
++	}
++
++	priv->type = qopt->type;
++	priv->shaped = qopt->shaped;
++
++	switch (priv->type) {
++	case CEETM_ROOT:
++		err = dpaa2_ceetm_init_root(sch, priv, qopt);
++		break;
++	case CEETM_PRIO:
++		err = dpaa2_ceetm_init_prio(sch, priv, qopt);
++		break;
++	default:
++		pr_err(KBUILD_BASENAME " : %s : invalid qdisc\n", __func__);
++		dpaa2_ceetm_destroy(sch);
++		err = -EINVAL;
++	}
++
++	return err;
++}
++
++/* Attach the underlying pfifo qdiscs */
++static void dpaa2_ceetm_attach(struct Qdisc *sch)
++{
++	struct net_device *dev = qdisc_dev(sch);
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct Qdisc *qdisc, *old_qdisc;
++	unsigned int i;
++
++	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
++
++	for (i = 0; i < dev->num_tx_queues; i++) {
++		qdisc = priv->root.qdiscs[i];
++		old_qdisc = dev_graft_qdisc(qdisc->dev_queue, qdisc);
++		if (old_qdisc)
++			qdisc_destroy(old_qdisc);
++	}
++
++	/* Remove the references to the pfifo qdiscs since the kernel will
++	 * destroy them when needed. No cleanup from our part is required from
++	 * this point on.
++	 */
++	kfree(priv->root.qdiscs);
++	priv->root.qdiscs = NULL;
++}
++
++static unsigned long dpaa2_ceetm_cls_get(struct Qdisc *sch, u32 classid)
++{
++	struct dpaa2_ceetm_class *cl;
++
++	pr_debug(KBUILD_BASENAME " : %s : classid %X from qdisc %X\n",
++		 __func__, classid, sch->handle);
++	cl = dpaa2_ceetm_find(classid, sch);
++
++	if (cl)
++		cl->refcnt++;
++
++	return (unsigned long)cl;
++}
++
++static void dpaa2_ceetm_cls_put(struct Qdisc *sch, unsigned long arg)
++{
++	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
++	pr_debug(KBUILD_BASENAME " : %s : classid %X from qdisc %X\n",
++		 __func__, cl->common.classid, sch->handle);
++	cl->refcnt--;
++
++	if (cl->refcnt == 0)
++		dpaa2_ceetm_cls_destroy(sch, cl);
++}
++
++static int dpaa2_ceetm_cls_change_root(struct dpaa2_ceetm_class *cl,
++				       struct dpaa2_ceetm_tc_copt *copt,
++				       struct net_device *dev)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(dev);
++	struct dpni_tx_shaping_cfg scfg = { 0 }, ecfg = { 0 };
++	int err = 0;
++
++	pr_debug(KBUILD_BASENAME " : %s : class %X\n", __func__,
++		 cl->common.classid);
++
++	if (!cl->shaped)
++		return 0;
++
++	if (dpaa2_eth_update_shaping_cfg(dev, copt->shaping_cfg,
++					 &scfg, &ecfg))
++		return -EINVAL;
++
++	err = dpaa2_eth_set_ch_shaping(priv, &scfg, &ecfg,
++				       copt->shaping_cfg.coupled,
++				       cl->root.ch_id);
++	if (err)
++		return err;
++
++	memcpy(&cl->root.shaping_cfg, &copt->shaping_cfg,
++	       sizeof(struct dpaa2_ceetm_shaping_cfg));
++
++	return err;
++}
++
++static int dpaa2_ceetm_cls_change_prio(struct dpaa2_ceetm_class *cl,
++				       struct dpaa2_ceetm_tc_copt *copt,
++				       struct net_device *dev)
++{
++	struct dpaa2_ceetm_qdisc *sch = qdisc_priv(cl->parent);
++	struct dpni_tx_schedule_cfg *sched_cfg;
++	struct dpaa2_eth_priv *priv = netdev_priv(dev);
++	int err;
++
++	pr_debug(KBUILD_BASENAME " : %s : class %X mode %d weight %d\n",
++		 __func__, cl->common.classid, copt->mode, copt->weight);
++
++	if (!cl->prio.cstats) {
++		cl->prio.cstats = alloc_percpu(struct dpaa2_ceetm_class_stats);
++		if (!cl->prio.cstats) {
++			pr_err(KBUILD_BASENAME " : %s : alloc_percpu() failed\n",
++			       __func__);
++			return -ENOMEM;
++		}
++	}
++
++	cl->prio.mode = copt->mode;
++	cl->prio.weight = copt->weight;
++
++	sched_cfg = &sch->prio.tx_prio_cfg.tc_sched[cl->prio.qpri];
++
++	switch (copt->mode) {
++	case STRICT_PRIORITY:
++		sched_cfg->mode = DPNI_TX_SCHED_STRICT_PRIORITY;
++		break;
++	case WEIGHTED_A:
++		sched_cfg->mode = DPNI_TX_SCHED_WEIGHTED_A;
++		break;
++	case WEIGHTED_B:
++		sched_cfg->mode = DPNI_TX_SCHED_WEIGHTED_B;
++		break;
++	}
++
++	err = dpaa2_eth_update_tx_prio(priv, cl, DPAA2_ETH_ADD_CQ);
++
++	return err;
++}
++
++/* Add a new ceetm class */
++static int dpaa2_ceetm_cls_add(struct Qdisc *sch, u32 classid,
++			       struct dpaa2_ceetm_tc_copt *copt,
++			       unsigned long *arg)
++{
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct net_device *dev = qdisc_dev(sch);
++	struct dpaa2_eth_priv *priv_eth = netdev_priv(dev);
++	struct dpaa2_ceetm_class *cl;
++	int err;
++
++	if (copt->type == CEETM_ROOT &&
++	    priv->clhash.hashelems == dpaa2_eth_ch_count(priv_eth)) {
++		pr_err("CEETM: only %d channel%s per DPNI allowed, sorry\n",
++		       dpaa2_eth_ch_count(priv_eth),
++		       dpaa2_eth_ch_count(priv_eth) == 1 ? "" : "s");
++		return -EINVAL;
++	}
++
++	if (copt->type == CEETM_PRIO &&
++	    priv->clhash.hashelems == dpaa2_eth_tc_count(priv_eth)) {
++		pr_err("CEETM: only %d queue%s per channel allowed, sorry\n",
++		       dpaa2_eth_tc_count(priv_eth),
++		       dpaa2_eth_tc_count(priv_eth) == 1 ? "" : "s");
++		return -EINVAL;
++	}
++
++	cl = kzalloc(sizeof(*cl), GFP_KERNEL);
++	if (!cl)
++		return -ENOMEM;
++
++	RCU_INIT_POINTER(cl->filter_list, NULL);
++
++	cl->common.classid = classid;
++	cl->refcnt = 1;
++	cl->parent = sch;
++	cl->child = NULL;
++
++	/* Add class handle in Qdisc */
++	dpaa2_ceetm_link_class(sch, &priv->clhash, &cl->common);
++
++	cl->shaped = copt->shaped;
++	cl->type = copt->type;
++
++	/* Claim a CEETM channel / tc - DPAA2. will assume transition from
++	 * classid to qdid/qpri, starting from qdid / qpri 0
++	 */
++	switch (copt->type) {
++	case CEETM_ROOT:
++		cl->root.ch_id = classid - sch->handle - 1;
++		err = dpaa2_ceetm_cls_change_root(cl, copt, dev);
++		break;
++	case CEETM_PRIO:
++		cl->prio.qpri = classid - sch->handle - 1;
++		err = dpaa2_ceetm_cls_change_prio(cl, copt, dev);
++		break;
++	default:
++		err = -EINVAL;
++		break;
++	}
++
++	if (err) {
++		pr_err("%s: Unable to set new %s class\n", __func__,
++		       (copt->type == CEETM_ROOT ? "root" : "prio"));
++		goto out_free;
++	}
++
++	switch (copt->type) {
++	case CEETM_ROOT:
++		pr_debug(KBUILD_BASENAME " : %s : configured root class %X associated with channel qdid %d\n",
++			 __func__, classid, cl->root.ch_id);
++		break;
++	case CEETM_PRIO:
++		pr_debug(KBUILD_BASENAME " : %s : configured prio class %X associated with queue qpri %d\n",
++			 __func__, classid, cl->prio.qpri);
++		break;
++	}
++
++	*arg = (unsigned long)cl;
++	return 0;
++
++out_free:
++	kfree(cl);
++	return err;
++}
++
++/* Add or configure a ceetm class */
++static int dpaa2_ceetm_cls_change(struct Qdisc *sch, u32 classid, u32 parentid,
++				  struct nlattr **tca, unsigned long *arg)
++{
++	struct dpaa2_ceetm_qdisc *priv;
++	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)*arg;
++	struct nlattr *opt = tca[TCA_OPTIONS];
++	struct nlattr *tb[DPAA2_CEETM_TCA_MAX];
++	struct dpaa2_ceetm_tc_copt *copt;
++	struct net_device *dev = qdisc_dev(sch);
++	int err;
++
++	pr_debug(KBUILD_BASENAME " : %s : classid %X under qdisc %X\n",
++		 __func__, classid, sch->handle);
++
++	if (strcmp(sch->ops->id, dpaa2_ceetm_qdisc_ops.id)) {
++		pr_err("CEETM: a ceetm class can not be attached to other qdisc/class types\n");
++		return -EINVAL;
++	}
++
++	priv = qdisc_priv(sch);
++
++	if (!opt) {
++		pr_err(KBUILD_BASENAME " : %s : tc error NULL opt\n", __func__);
++		return -EINVAL;
++	}
++
++	err = nla_parse_nested(tb, DPAA2_CEETM_TCA_COPT, opt,
++			       dpaa2_ceetm_policy);
++	if (err < 0) {
++		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
++		       "nla_parse_nested");
++		return -EINVAL;
++	}
++
++	if (!tb[DPAA2_CEETM_TCA_COPT]) {
++		pr_err(KBUILD_BASENAME " : %s : tc error in %s\n", __func__,
++		       "tb");
++		return -EINVAL;
++	}
++
++	copt = nla_data(tb[DPAA2_CEETM_TCA_COPT]);
++
++	/* Configure an existing ceetm class */
++	if (cl) {
++		if (copt->type != cl->type) {
++			pr_err("CEETM: class %X is not of the provided type\n",
++			       cl->common.classid);
++			return -EINVAL;
++		}
++
++		switch (copt->type) {
++		case CEETM_ROOT:
++			return dpaa2_ceetm_cls_change_root(cl, copt, dev);
++		case CEETM_PRIO:
++			return dpaa2_ceetm_cls_change_prio(cl, copt, dev);
++
++		default:
++			pr_err(KBUILD_BASENAME " : %s : invalid class\n",
++			       __func__);
++			return -EINVAL;
++		}
++	}
++
++	return dpaa2_ceetm_cls_add(sch, classid, copt, arg);
++}
++
++static void dpaa2_ceetm_cls_walk(struct Qdisc *sch, struct qdisc_walker *arg)
++{
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct dpaa2_ceetm_class *cl;
++	unsigned int i;
++
++	pr_debug(KBUILD_BASENAME " : %s : qdisc %X\n", __func__, sch->handle);
++
++	if (arg->stop)
++		return;
++
++	for (i = 0; i < priv->clhash.hashsize; i++) {
++		hlist_for_each_entry(cl, &priv->clhash.hash[i], common.hnode) {
++			if (arg->count < arg->skip) {
++				arg->count++;
++				continue;
++			}
++			if (arg->fn(sch, (unsigned long)cl, arg) < 0) {
++				arg->stop = 1;
++				return;
++			}
++			arg->count++;
++		}
++	}
++}
++
++static int dpaa2_ceetm_cls_dump(struct Qdisc *sch, unsigned long arg,
++				struct sk_buff *skb, struct tcmsg *tcm)
++{
++	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
++	struct nlattr *nest;
++	struct dpaa2_ceetm_tc_copt copt;
++
++	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n",
++		 __func__, cl->common.classid, sch->handle);
++
++	sch_tree_lock(sch);
++
++	tcm->tcm_parent = ((struct Qdisc *)cl->parent)->handle;
++	tcm->tcm_handle = cl->common.classid;
++
++	memset(&copt, 0, sizeof(copt));
++
++	copt.shaped = cl->shaped;
++	copt.type = cl->type;
++
++	switch (cl->type) {
++	case CEETM_ROOT:
++		if (cl->child)
++			tcm->tcm_info = cl->child->handle;
++
++		memcpy(&copt.shaping_cfg, &cl->root.shaping_cfg,
++		       sizeof(struct dpaa2_ceetm_shaping_cfg));
++
++		break;
++
++	case CEETM_PRIO:
++		if (cl->child)
++			tcm->tcm_info = cl->child->handle;
++
++		copt.mode = cl->prio.mode;
++		copt.weight = cl->prio.weight;
++
++		break;
++	}
++
++	nest = nla_nest_start(skb, TCA_OPTIONS);
++	if (!nest)
++		goto nla_put_failure;
++	if (nla_put(skb, DPAA2_CEETM_TCA_COPT, sizeof(copt), &copt))
++		goto nla_put_failure;
++	nla_nest_end(skb, nest);
++	sch_tree_unlock(sch);
++	return skb->len;
++
++nla_put_failure:
++	sch_tree_unlock(sch);
++	nla_nest_cancel(skb, nest);
++	return -EMSGSIZE;
++}
++
++static int dpaa2_ceetm_cls_delete(struct Qdisc *sch, unsigned long arg)
++{
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
++
++	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n",
++		 __func__, cl->common.classid, sch->handle);
++
++	sch_tree_lock(sch);
++	qdisc_class_hash_remove(&priv->clhash, &cl->common);
++	cl->refcnt--;
++	WARN_ON(cl->refcnt == 0);
++	sch_tree_unlock(sch);
++	return 0;
++}
++
++/* Get the class' child qdisc, if any */
++static struct Qdisc *dpaa2_ceetm_cls_leaf(struct Qdisc *sch, unsigned long arg)
++{
++	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
++
++	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n",
++		 __func__, cl->common.classid, sch->handle);
++
++	switch (cl->type) {
++	case CEETM_ROOT:
++	case CEETM_PRIO:
++		return cl->child;
++	}
++
++	return NULL;
++}
++
++static int dpaa2_ceetm_cls_graft(struct Qdisc *sch, unsigned long arg,
++				 struct Qdisc *new, struct Qdisc **old)
++{
++	if (new && strcmp(new->ops->id, dpaa2_ceetm_qdisc_ops.id)) {
++		pr_err("CEETM: only ceetm qdiscs can be attached to ceetm classes\n");
++		return -EOPNOTSUPP;
++	}
++
++	return 0;
++}
++
++static int dpaa2_ceetm_cls_dump_stats(struct Qdisc *sch, unsigned long arg,
++				      struct gnet_dump *d)
++{
++	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
++	struct gnet_stats_basic_packed tmp_bstats;
++	struct dpaa2_ceetm_tc_xstats xstats;
++	union dpni_statistics dpni_stats;
++	struct net_device *dev = qdisc_dev(sch);
++	struct dpaa2_eth_priv *priv_eth = netdev_priv(dev);
++	u8 ch_id = 0;
++	int err;
++
++	memset(&xstats, 0, sizeof(xstats));
++	memset(&tmp_bstats, 0, sizeof(tmp_bstats));
++
++	if (cl->type == CEETM_ROOT)
++		return 0;
++
++	err = dpni_get_statistics(priv_eth->mc_io, 0, priv_eth->mc_token, 3,
++				  DPNI_BUILD_CH_TC(ch_id, cl->prio.qpri),
++				  &dpni_stats);
++	if (err)
++		netdev_warn(dev, "dpni_get_stats(%d) failed - %d\n", 3, err);
++
++	xstats.ceetm_dequeue_bytes = dpni_stats.page_3.ceetm_dequeue_bytes;
++	xstats.ceetm_dequeue_frames = dpni_stats.page_3.ceetm_dequeue_frames;
++	xstats.ceetm_reject_bytes = dpni_stats.page_3.ceetm_reject_bytes;
++	xstats.ceetm_reject_frames = dpni_stats.page_3.ceetm_reject_frames;
++
++	return gnet_stats_copy_app(d, &xstats, sizeof(xstats));
++}
++
++static struct tcf_proto __rcu **dpaa2_ceetm_tcf_chain(struct Qdisc *sch,
++						      unsigned long arg)
++{
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
++
++	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__,
++		 cl ? cl->common.classid : 0, sch->handle);
++	return cl ? &cl->filter_list : &priv->filter_list;
++}
++
++static unsigned long dpaa2_ceetm_tcf_bind(struct Qdisc *sch,
++					  unsigned long parent,
++					  u32 classid)
++{
++	struct dpaa2_ceetm_class *cl = dpaa2_ceetm_find(classid, sch);
++
++	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__,
++		 cl ? cl->common.classid : 0, sch->handle);
++	return (unsigned long)cl;
++}
++
++static void dpaa2_ceetm_tcf_unbind(struct Qdisc *sch, unsigned long arg)
++{
++	struct dpaa2_ceetm_class *cl = (struct dpaa2_ceetm_class *)arg;
++
++	pr_debug(KBUILD_BASENAME " : %s : class %X under qdisc %X\n", __func__,
++		 cl ? cl->common.classid : 0, sch->handle);
++}
++
++const struct Qdisc_class_ops dpaa2_ceetm_cls_ops = {
++	.graft		=	dpaa2_ceetm_cls_graft,
++	.leaf		=	dpaa2_ceetm_cls_leaf,
++	.get		=	dpaa2_ceetm_cls_get,
++	.put		=	dpaa2_ceetm_cls_put,
++	.change		=	dpaa2_ceetm_cls_change,
++	.delete		=	dpaa2_ceetm_cls_delete,
++	.walk		=	dpaa2_ceetm_cls_walk,
++	.tcf_chain	=	dpaa2_ceetm_tcf_chain,
++	.bind_tcf	=	dpaa2_ceetm_tcf_bind,
++	.unbind_tcf	=	dpaa2_ceetm_tcf_unbind,
++	.dump		=	dpaa2_ceetm_cls_dump,
++	.dump_stats	=	dpaa2_ceetm_cls_dump_stats,
++};
++
++struct Qdisc_ops dpaa2_ceetm_qdisc_ops __read_mostly = {
++	.id		=	"ceetm",
++	.priv_size	=	sizeof(struct dpaa2_ceetm_qdisc),
++	.cl_ops		=	&dpaa2_ceetm_cls_ops,
++	.init		=	dpaa2_ceetm_init,
++	.destroy	=	dpaa2_ceetm_destroy,
++	.change		=	dpaa2_ceetm_change,
++	.dump		=	dpaa2_ceetm_dump,
++	.attach		=	dpaa2_ceetm_attach,
++	.owner		=	THIS_MODULE,
++};
++
++/* Run the filters and classifiers attached to the qdisc on the provided skb */
++int dpaa2_ceetm_classify(struct sk_buff *skb, struct Qdisc *sch,
++			 int *qdid, int *qpri)
++{
++	struct dpaa2_ceetm_qdisc *priv = qdisc_priv(sch);
++	struct dpaa2_ceetm_class *cl = NULL;
++	struct tcf_result res;
++	struct tcf_proto *tcf;
++	int result;
++
++	tcf = rcu_dereference_bh(priv->filter_list);
++	while (tcf && (result = tc_classify(skb, tcf, &res, false)) >= 0) {
++#ifdef CONFIG_NET_CLS_ACT
++		switch (result) {
++		case TC_ACT_QUEUED:
++		case TC_ACT_STOLEN:
++		case TC_ACT_SHOT:
++			/* No valid class found due to action */
++			return -1;
++		}
++#endif
++		cl = (void *)res.class;
++		if (!cl) {
++			/* The filter leads to the qdisc */
++			if (res.classid == sch->handle)
++				return 0;
++
++			cl = dpaa2_ceetm_find(res.classid, sch);
++			/* The filter leads to an invalid class */
++			if (!cl)
++				break;
++		}
++
++		/* The class might have its own filters attached */
++		tcf = rcu_dereference_bh(cl->filter_list);
++	}
++
++	/* No valid class found */
++	if (!cl)
++		return 0;
++
++	switch (cl->type) {
++	case CEETM_ROOT:
++		*qdid = cl->root.ch_id;
++
++		/* The root class does not have a child prio qdisc */
++		if (!cl->child)
++			return 0;
++
++		/* Run the prio qdisc classifiers */
++		return dpaa2_ceetm_classify(skb, cl->child, qdid, qpri);
++
++	case CEETM_PRIO:
++		*qpri = cl->prio.qpri;
++		break;
++	}
++
++	return 0;
++}
++
++int __init dpaa2_ceetm_register(void)
++{
++	int err = 0;
++
++	pr_debug(KBUILD_MODNAME ": " DPAA2_CEETM_DESCRIPTION "\n");
++
++	err = register_qdisc(&dpaa2_ceetm_qdisc_ops);
++	if (unlikely(err))
++		pr_err(KBUILD_MODNAME
++		       ": %s:%hu:%s(): register_qdisc() = %d\n",
++		       KBUILD_BASENAME ".c", __LINE__, __func__, err);
++
++	return err;
++}
++
++void __exit dpaa2_ceetm_unregister(void)
++{
++	pr_debug(KBUILD_MODNAME ": %s:%s() ->\n",
++		 KBUILD_BASENAME ".c", __func__);
++
++	unregister_qdisc(&dpaa2_ceetm_qdisc_ops);
++}
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-ceetm.h
+@@ -0,0 +1,182 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++/*
++ * Copyright 2017 NXP
++ *
++ */
++
++#ifndef __DPAA2_ETH_CEETM_H
++#define __DPAA2_ETH_CEETM_H
++
++#include <net/pkt_sched.h>
++#include <net/pkt_cls.h>
++#include <net/netlink.h>
++
++#include "dpaa2-eth.h"
++
++/* For functional purposes, there are num_tx_queues pfifo qdiscs through which
++ * frames reach the driver. Their handles start from 1:21. Handles 1:1 to 1:20
++ * are reserved for the maximum 32 CEETM channels (majors and minors are in
++ * hex).
++ */
++#define PFIFO_MIN_OFFSET		0x21
++
++#define DPAA2_CEETM_MIN_WEIGHT		100
++#define DPAA2_CEETM_MAX_WEIGHT		24800
++
++#define DPAA2_CEETM_TD_THRESHOLD	1000
++
++enum wbfs_group_type {
++	WBFS_GRP_A,
++	WBFS_GRP_B,
++	WBFS_GRP_LARGE
++};
++
++enum {
++	DPAA2_CEETM_TCA_UNSPEC,
++	DPAA2_CEETM_TCA_COPT,
++	DPAA2_CEETM_TCA_QOPS,
++	DPAA2_CEETM_TCA_MAX,
++};
++
++/* CEETM configuration types */
++enum dpaa2_ceetm_type {
++	CEETM_ROOT = 1,
++	CEETM_PRIO,
++};
++
++enum {
++	STRICT_PRIORITY = 0,
++	WEIGHTED_A,
++	WEIGHTED_B,
++};
++
++struct dpaa2_ceetm_shaping_cfg {
++	__u64 cir; /* committed information rate */
++	__u64 eir; /* excess information rate */
++	__u16 cbs; /* committed burst size */
++	__u16 ebs; /* excess burst size */
++	__u8 coupled; /* shaper coupling */
++};
++
++extern const struct nla_policy ceetm_policy[DPAA2_CEETM_TCA_MAX];
++
++struct dpaa2_ceetm_class;
++struct dpaa2_ceetm_qdisc_stats;
++struct dpaa2_ceetm_class_stats;
++
++/* corresponds to CEETM shaping at LNI level */
++struct dpaa2_root_q {
++	struct Qdisc **qdiscs;
++	struct dpaa2_ceetm_qdisc_stats __percpu *qstats;
++};
++
++/* corresponds to the number of priorities a channel serves */
++struct dpaa2_prio_q {
++	struct dpaa2_ceetm_class *parent;
++	struct dpni_tx_priorities_cfg tx_prio_cfg;
++};
++
++struct dpaa2_ceetm_qdisc {
++	struct Qdisc_class_hash clhash;
++	struct tcf_proto *filter_list; /* qdisc attached filters */
++
++	enum dpaa2_ceetm_type type; /* ROOT/PRIO */
++	bool shaped;
++	union {
++		struct dpaa2_root_q root;
++		struct dpaa2_prio_q prio;
++	};
++};
++
++/* CEETM Qdisc configuration parameters */
++struct dpaa2_ceetm_tc_qopt {
++	enum dpaa2_ceetm_type type;
++	__u16 shaped;
++	__u8 prio_group_A;
++	__u8 prio_group_B;
++	__u8 separate_groups;
++};
++
++/* root class - corresponds to a channel */
++struct dpaa2_root_c {
++	struct dpaa2_ceetm_shaping_cfg shaping_cfg;
++	u32 ch_id;
++};
++
++/* prio class - corresponds to a strict priority queue (group) */
++struct dpaa2_prio_c {
++	struct dpaa2_ceetm_class_stats __percpu *cstats;
++	u32 qpri;
++	u8 mode;
++	u16 weight;
++};
++
++struct dpaa2_ceetm_class {
++	struct Qdisc_class_common common;
++	int refcnt;
++	struct tcf_proto *filter_list; /* class attached filters */
++	struct Qdisc *parent;
++	struct Qdisc *child;
++
++	enum dpaa2_ceetm_type type; /* ROOT/PRIO */
++	bool shaped;
++	union {
++		struct dpaa2_root_c root;
++		struct dpaa2_prio_c prio;
++	};
++};
++
++/* CEETM Class configuration parameters */
++struct dpaa2_ceetm_tc_copt {
++	enum dpaa2_ceetm_type type;
++	struct dpaa2_ceetm_shaping_cfg shaping_cfg;
++	__u16 shaped;
++	__u8 mode;
++	__u16 weight;
++};
++
++/* CEETM stats */
++struct dpaa2_ceetm_qdisc_stats {
++	__u32 drops;
++};
++
++struct dpaa2_ceetm_class_stats {
++	/* Software counters */
++	struct gnet_stats_basic_packed bstats;
++	__u32 ern_drop_count;
++	__u32 congested_count;
++};
++
++struct dpaa2_ceetm_tc_xstats {
++	__u64 ceetm_dequeue_bytes;
++	__u64 ceetm_dequeue_frames;
++	__u64 ceetm_reject_bytes;
++	__u64 ceetm_reject_frames;
++};
++
++#ifdef CONFIG_FSL_DPAA2_ETH_CEETM
++int __init dpaa2_ceetm_register(void);
++void __exit dpaa2_ceetm_unregister(void);
++int dpaa2_ceetm_classify(struct sk_buff *skb, struct Qdisc *sch,
++			 int *qdid, int *qpri);
++#else
++static inline int dpaa2_ceetm_register(void)
++{
++	return 0;
++}
++
++static inline void dpaa2_ceetm_unregister(void) {}
++
++static inline int dpaa2_ceetm_classify(struct sk_buff *skb, struct Qdisc *sch,
++				       int *qdid, int *qpri)
++{
++	return 0;
++}
++#endif
++
++static inline bool dpaa2_eth_ceetm_is_enabled(struct dpaa2_eth_priv *priv)
++{
++	return priv->ceetm_en;
++}
++
++#endif
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.c
+@@ -0,0 +1,357 @@
++
++/* Copyright 2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/module.h>
++#include <linux/debugfs.h>
++#include "dpaa2-eth.h"
++#include "dpaa2-eth-debugfs.h"
++
++#define DPAA2_ETH_DBG_ROOT "dpaa2-eth"
++
++static struct dentry *dpaa2_dbg_root;
++
++static int dpaa2_dbg_cpu_show(struct seq_file *file, void *offset)
++{
++	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
++	struct rtnl_link_stats64 *stats;
++	struct dpaa2_eth_drv_stats *extras;
++	int i;
++
++	seq_printf(file, "Per-CPU stats for %s\n", priv->net_dev->name);
++	seq_printf(file, "%s%16s%16s%16s%16s%16s%16s%16s%16s%16s\n",
++		   "CPU", "Rx", "Rx Err", "Rx SG", "Tx", "Tx Err", "Tx conf",
++		   "Tx SG", "Tx realloc", "Enq busy");
++
++	for_each_online_cpu(i) {
++		stats = per_cpu_ptr(priv->percpu_stats, i);
++		extras = per_cpu_ptr(priv->percpu_extras, i);
++		seq_printf(file, "%3d%16llu%16llu%16llu%16llu%16llu%16llu%16llu%16llu%16llu\n",
++			   i,
++			   stats->rx_packets,
++			   stats->rx_errors,
++			   extras->rx_sg_frames,
++			   stats->tx_packets,
++			   stats->tx_errors,
++			   extras->tx_conf_frames,
++			   extras->tx_sg_frames,
++			   extras->tx_reallocs,
++			   extras->tx_portal_busy);
++	}
++
++	return 0;
++}
++
++static int dpaa2_dbg_cpu_open(struct inode *inode, struct file *file)
++{
++	int err;
++	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private;
++
++	err = single_open(file, dpaa2_dbg_cpu_show, priv);
++	if (err < 0)
++		netdev_err(priv->net_dev, "single_open() failed\n");
++
++	return err;
++}
++
++static const struct file_operations dpaa2_dbg_cpu_ops = {
++	.open = dpaa2_dbg_cpu_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++};
++
++static char *fq_type_to_str(struct dpaa2_eth_fq *fq)
++{
++	switch (fq->type) {
++	case DPAA2_RX_FQ:
++		return "Rx";
++	case DPAA2_TX_CONF_FQ:
++		return "Tx conf";
++	case DPAA2_RX_ERR_FQ:
++		return "Rx err";
++	default:
++		return "N/A";
++	}
++}
++
++static int dpaa2_dbg_fqs_show(struct seq_file *file, void *offset)
++{
++	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
++	struct dpaa2_eth_fq *fq;
++	u32 fcnt, bcnt;
++	int i, err;
++
++	seq_printf(file, "non-zero FQ stats for %s:\n", priv->net_dev->name);
++	seq_printf(file, "%s%16s%16s%16s%16s%16s%16s\n",
++		   "VFQID", "CPU", "Traffic Class", "Type", "Frames",
++		   "Pending frames", "Congestion");
++
++	for (i = 0; i <  priv->num_fqs; i++) {
++		fq = &priv->fq[i];
++		err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt);
++		if (err)
++			fcnt = 0;
++
++		/* A lot of queues, no use displaying zero traffic ones */
++		if (!fq->stats.frames && !fcnt)
++			continue;
++
++		seq_printf(file, "%5d%16d%16d%16s%16llu%16u%16llu\n",
++			   fq->fqid,
++			   fq->target_cpu,
++			   fq->tc,
++			   fq_type_to_str(fq),
++			   fq->stats.frames,
++			   fcnt,
++			   fq->stats.congestion_entry);
++	}
++
++	return 0;
++}
++
++static int dpaa2_dbg_fqs_open(struct inode *inode, struct file *file)
++{
++	int err;
++	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private;
++
++	err = single_open(file, dpaa2_dbg_fqs_show, priv);
++	if (err < 0)
++		netdev_err(priv->net_dev, "single_open() failed\n");
++
++	return err;
++}
++
++static const struct file_operations dpaa2_dbg_fq_ops = {
++	.open = dpaa2_dbg_fqs_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++};
++
++static int dpaa2_dbg_ch_show(struct seq_file *file, void *offset)
++{
++	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)file->private;
++	struct dpaa2_eth_channel *ch;
++	int i;
++
++	seq_printf(file, "Channel stats for %s:\n", priv->net_dev->name);
++	seq_printf(file, "%s%16s%16s%16s%16s%16s%16s\n",
++		   "CHID", "CPU", "Deq busy", "Frames", "CDANs",
++		   "Avg frm/CDAN", "Buf count");
++
++	for (i = 0; i < priv->num_channels; i++) {
++		ch = priv->channel[i];
++		seq_printf(file, "%4d%16d%16llu%16llu%16llu%16llu%16d\n",
++			   ch->ch_id,
++			   ch->nctx.desired_cpu,
++			   ch->stats.dequeue_portal_busy,
++			   ch->stats.frames,
++			   ch->stats.cdan,
++			   ch->stats.frames / ch->stats.cdan,
++			   ch->buf_count);
++	}
++
++	return 0;
++}
++
++static int dpaa2_dbg_ch_open(struct inode *inode, struct file *file)
++{
++	int err;
++	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)inode->i_private;
++
++	err = single_open(file, dpaa2_dbg_ch_show, priv);
++	if (err < 0)
++		netdev_err(priv->net_dev, "single_open() failed\n");
++
++	return err;
++}
++
++static const struct file_operations dpaa2_dbg_ch_ops = {
++	.open = dpaa2_dbg_ch_open,
++	.read = seq_read,
++	.llseek = seq_lseek,
++	.release = single_release,
++};
++
++static ssize_t dpaa2_dbg_reset_write(struct file *file, const char __user *buf,
++				     size_t count, loff_t *offset)
++{
++	struct dpaa2_eth_priv *priv = file->private_data;
++	struct rtnl_link_stats64 *percpu_stats;
++	struct dpaa2_eth_drv_stats *percpu_extras;
++	struct dpaa2_eth_fq *fq;
++	struct dpaa2_eth_channel *ch;
++	int i;
++
++	for_each_online_cpu(i) {
++		percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
++		memset(percpu_stats, 0, sizeof(*percpu_stats));
++
++		percpu_extras = per_cpu_ptr(priv->percpu_extras, i);
++		memset(percpu_extras, 0, sizeof(*percpu_extras));
++	}
++
++	for (i = 0; i < priv->num_fqs; i++) {
++		fq = &priv->fq[i];
++		memset(&fq->stats, 0, sizeof(fq->stats));
++	}
++
++	for (i = 0; i < priv->num_channels; i++) {
++		ch = priv->channel[i];
++		memset(&ch->stats, 0, sizeof(ch->stats));
++	}
++
++	return count;
++}
++
++static const struct file_operations dpaa2_dbg_reset_ops = {
++	.open = simple_open,
++	.write = dpaa2_dbg_reset_write,
++};
++
++static ssize_t dpaa2_dbg_reset_mc_write(struct file *file,
++					const char __user *buf,
++					size_t count, loff_t *offset)
++{
++	struct dpaa2_eth_priv *priv = file->private_data;
++	int err;
++
++	err = dpni_reset_statistics(priv->mc_io, 0, priv->mc_token);
++	if (err)
++		netdev_err(priv->net_dev,
++			   "dpni_reset_statistics() failed %d\n", err);
++
++	return count;
++}
++
++static const struct file_operations dpaa2_dbg_reset_mc_ops = {
++	.open = simple_open,
++	.write = dpaa2_dbg_reset_mc_write,
++};
++
++void dpaa2_dbg_add(struct dpaa2_eth_priv *priv)
++{
++	if (!dpaa2_dbg_root)
++		return;
++
++	/* Create a directory for the interface */
++	priv->dbg.dir = debugfs_create_dir(priv->net_dev->name,
++					   dpaa2_dbg_root);
++	if (!priv->dbg.dir) {
++		netdev_err(priv->net_dev, "debugfs_create_dir() failed\n");
++		return;
++	}
++
++	/* per-cpu stats file */
++	priv->dbg.cpu_stats = debugfs_create_file("cpu_stats", 0444,
++						  priv->dbg.dir, priv,
++						  &dpaa2_dbg_cpu_ops);
++	if (!priv->dbg.cpu_stats) {
++		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
++		goto err_cpu_stats;
++	}
++
++	/* per-fq stats file */
++	priv->dbg.fq_stats = debugfs_create_file("fq_stats", 0444,
++						 priv->dbg.dir, priv,
++						 &dpaa2_dbg_fq_ops);
++	if (!priv->dbg.fq_stats) {
++		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
++		goto err_fq_stats;
++	}
++
++	/* per-fq stats file */
++	priv->dbg.ch_stats = debugfs_create_file("ch_stats", 0444,
++						 priv->dbg.dir, priv,
++						 &dpaa2_dbg_ch_ops);
++	if (!priv->dbg.fq_stats) {
++		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
++		goto err_ch_stats;
++	}
++
++	/* reset stats */
++	priv->dbg.reset_stats = debugfs_create_file("reset_stats", 0200,
++						    priv->dbg.dir, priv,
++						    &dpaa2_dbg_reset_ops);
++	if (!priv->dbg.reset_stats) {
++		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
++		goto err_reset_stats;
++	}
++
++	/* reset MC stats */
++	priv->dbg.reset_mc_stats = debugfs_create_file("reset_mc_stats",
++						0222, priv->dbg.dir, priv,
++						&dpaa2_dbg_reset_mc_ops);
++	if (!priv->dbg.reset_mc_stats) {
++		netdev_err(priv->net_dev, "debugfs_create_file() failed\n");
++		goto err_reset_mc_stats;
++	}
++
++	return;
++
++err_reset_mc_stats:
++	debugfs_remove(priv->dbg.reset_stats);
++err_reset_stats:
++	debugfs_remove(priv->dbg.ch_stats);
++err_ch_stats:
++	debugfs_remove(priv->dbg.fq_stats);
++err_fq_stats:
++	debugfs_remove(priv->dbg.cpu_stats);
++err_cpu_stats:
++	debugfs_remove(priv->dbg.dir);
++}
++
++void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv)
++{
++	debugfs_remove(priv->dbg.reset_mc_stats);
++	debugfs_remove(priv->dbg.reset_stats);
++	debugfs_remove(priv->dbg.fq_stats);
++	debugfs_remove(priv->dbg.ch_stats);
++	debugfs_remove(priv->dbg.cpu_stats);
++	debugfs_remove(priv->dbg.dir);
++}
++
++void dpaa2_eth_dbg_init(void)
++{
++	dpaa2_dbg_root = debugfs_create_dir(DPAA2_ETH_DBG_ROOT, NULL);
++	if (!dpaa2_dbg_root) {
++		pr_err("DPAA2-ETH: debugfs create failed\n");
++		return;
++	}
++
++	pr_info("DPAA2-ETH: debugfs created\n");
++}
++
++void __exit dpaa2_eth_dbg_exit(void)
++{
++	debugfs_remove(dpaa2_dbg_root);
++}
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-debugfs.h
+@@ -0,0 +1,60 @@
++/* Copyright 2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef DPAA2_ETH_DEBUGFS_H
++#define DPAA2_ETH_DEBUGFS_H
++
++#include <linux/dcache.h>
++
++struct dpaa2_eth_priv;
++
++struct dpaa2_debugfs {
++	struct dentry *dir;
++	struct dentry *fq_stats;
++	struct dentry *ch_stats;
++	struct dentry *cpu_stats;
++	struct dentry *reset_stats;
++	struct dentry *reset_mc_stats;
++};
++
++#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS
++void dpaa2_eth_dbg_init(void);
++void dpaa2_eth_dbg_exit(void);
++void dpaa2_dbg_add(struct dpaa2_eth_priv *priv);
++void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv);
++#else
++static inline void dpaa2_eth_dbg_init(void) {}
++static inline void dpaa2_eth_dbg_exit(void) {}
++static inline void dpaa2_dbg_add(struct dpaa2_eth_priv *priv) {}
++static inline void dpaa2_dbg_remove(struct dpaa2_eth_priv *priv) {}
++#endif /* CONFIG_FSL_DPAA2_ETH_DEBUGFS */
++
++#endif /* DPAA2_ETH_DEBUGFS_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth-trace.h
+@@ -0,0 +1,185 @@
++/* Copyright 2014-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM	dpaa2_eth
++
++#if !defined(_DPAA2_ETH_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _DPAA2_ETH_TRACE_H
++
++#include <linux/skbuff.h>
++#include <linux/netdevice.h>
++#include "dpaa2-eth.h"
++#include <linux/tracepoint.h>
++
++#define TR_FMT "[%s] fd: addr=0x%llx, len=%u, off=%u"
++/* trace_printk format for raw buffer event class */
++#define TR_BUF_FMT "[%s] vaddr=%p size=%zu dma_addr=%pad map_size=%zu bpid=%d"
++
++/* This is used to declare a class of events.
++ * individual events of this type will be defined below.
++ */
++
++/* Store details about a frame descriptor */
++DECLARE_EVENT_CLASS(dpaa2_eth_fd,
++		    /* Trace function prototype */
++		    TP_PROTO(struct net_device *netdev,
++			     const struct dpaa2_fd *fd),
++
++		    /* Repeat argument list here */
++		    TP_ARGS(netdev, fd),
++
++		    /* A structure containing the relevant information we want
++		     * to record. Declare name and type for each normal element,
++		     * name, type and size for arrays. Use __string for variable
++		     * length strings.
++		     */
++		    TP_STRUCT__entry(
++				     __field(u64, fd_addr)
++				     __field(u32, fd_len)
++				     __field(u16, fd_offset)
++				     __string(name, netdev->name)
++		    ),
++
++		    /* The function that assigns values to the above declared
++		     * fields
++		     */
++		    TP_fast_assign(
++				   __entry->fd_addr = dpaa2_fd_get_addr(fd);
++				   __entry->fd_len = dpaa2_fd_get_len(fd);
++				   __entry->fd_offset = dpaa2_fd_get_offset(fd);
++				   __assign_str(name, netdev->name);
++		    ),
++
++		    /* This is what gets printed when the trace event is
++		     * triggered.
++		     */
++		    TP_printk(TR_FMT,
++			      __get_str(name),
++			      __entry->fd_addr,
++			      __entry->fd_len,
++			      __entry->fd_offset)
++);
++
++/* Now declare events of the above type. Format is:
++ * DEFINE_EVENT(class, name, proto, args), with proto and args same as for class
++ */
++
++/* Tx (egress) fd */
++DEFINE_EVENT(dpaa2_eth_fd, dpaa2_tx_fd,
++	     TP_PROTO(struct net_device *netdev,
++		      const struct dpaa2_fd *fd),
++
++	     TP_ARGS(netdev, fd)
++);
++
++/* Rx fd */
++DEFINE_EVENT(dpaa2_eth_fd, dpaa2_rx_fd,
++	     TP_PROTO(struct net_device *netdev,
++		      const struct dpaa2_fd *fd),
++
++	     TP_ARGS(netdev, fd)
++);
++
++/* Tx confirmation fd */
++DEFINE_EVENT(dpaa2_eth_fd, dpaa2_tx_conf_fd,
++	     TP_PROTO(struct net_device *netdev,
++		      const struct dpaa2_fd *fd),
++
++	     TP_ARGS(netdev, fd)
++);
++
++/* Log data about raw buffers. Useful for tracing DPBP content. */
++TRACE_EVENT(dpaa2_eth_buf_seed,
++	    /* Trace function prototype */
++	    TP_PROTO(struct net_device *netdev,
++		     /* virtual address and size */
++		     void *vaddr,
++		     size_t size,
++		     /* dma map address and size */
++		     dma_addr_t dma_addr,
++		     size_t map_size,
++		     /* buffer pool id, if relevant */
++		     u16 bpid),
++
++	    /* Repeat argument list here */
++	    TP_ARGS(netdev, vaddr, size, dma_addr, map_size, bpid),
++
++	    /* A structure containing the relevant information we want
++	     * to record. Declare name and type for each normal element,
++	     * name, type and size for arrays. Use __string for variable
++	     * length strings.
++	     */
++	    TP_STRUCT__entry(
++			     __field(void *, vaddr)
++			     __field(size_t, size)
++			     __field(dma_addr_t, dma_addr)
++			     __field(size_t, map_size)
++			     __field(u16, bpid)
++			     __string(name, netdev->name)
++	    ),
++
++	    /* The function that assigns values to the above declared
++	     * fields
++	     */
++	    TP_fast_assign(
++			   __entry->vaddr = vaddr;
++			   __entry->size = size;
++			   __entry->dma_addr = dma_addr;
++			   __entry->map_size = map_size;
++			   __entry->bpid = bpid;
++			   __assign_str(name, netdev->name);
++	    ),
++
++	    /* This is what gets printed when the trace event is
++	     * triggered.
++	     */
++	    TP_printk(TR_BUF_FMT,
++		      __get_str(name),
++		      __entry->vaddr,
++		      __entry->size,
++		      &__entry->dma_addr,
++		      __entry->map_size,
++		      __entry->bpid)
++);
++
++/* If only one event of a certain type needs to be declared, use TRACE_EVENT().
++ * The syntax is the same as for DECLARE_EVENT_CLASS().
++ */
++
++#endif /* _DPAA2_ETH_TRACE_H */
++
++/* This must be outside ifdef _DPAA2_ETH_TRACE_H */
++#undef TRACE_INCLUDE_PATH
++#define TRACE_INCLUDE_PATH .
++#undef TRACE_INCLUDE_FILE
++#define TRACE_INCLUDE_FILE	dpaa2-eth-trace
++#include <trace/define_trace.h>
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c
+@@ -0,0 +1,3734 @@
++/* Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2016-2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/etherdevice.h>
++#include <linux/of_net.h>
++#include <linux/interrupt.h>
++#include <linux/msi.h>
++#include <linux/kthread.h>
++#include <linux/iommu.h>
++#include <linux/net_tstamp.h>
++#include <linux/bpf.h>
++#include <linux/filter.h>
++#include <linux/atomic.h>
++#include <net/sock.h>
++#include <linux/fsl/mc.h>
++#include "dpaa2-eth.h"
++#include "dpaa2-eth-ceetm.h"
++
++/* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
++ * using trace events only need to #include <trace/events/sched.h>
++ */
++#define CREATE_TRACE_POINTS
++#include "dpaa2-eth-trace.h"
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_AUTHOR("Freescale Semiconductor, Inc");
++MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
++
++const char dpaa2_eth_drv_version[] = "0.1";
++
++static void *dpaa2_iova_to_virt(struct iommu_domain *domain,
++				dma_addr_t iova_addr)
++{
++	phys_addr_t phys_addr;
++
++	phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
++
++	return phys_to_virt(phys_addr);
++}
++
++static void validate_rx_csum(struct dpaa2_eth_priv *priv,
++			     u32 fd_status,
++			     struct sk_buff *skb)
++{
++	skb_checksum_none_assert(skb);
++
++	/* HW checksum validation is disabled, nothing to do here */
++	if (!(priv->net_dev->features & NETIF_F_RXCSUM))
++		return;
++
++	/* Read checksum validation bits */
++	if (!((fd_status & DPAA2_FAS_L3CV) &&
++	      (fd_status & DPAA2_FAS_L4CV)))
++		return;
++
++	/* Inform the stack there's no need to compute L3/L4 csum anymore */
++	skb->ip_summed = CHECKSUM_UNNECESSARY;
++}
++
++/* Free a received FD.
++ * Not to be used for Tx conf FDs or on any other paths.
++ */
++static void free_rx_fd(struct dpaa2_eth_priv *priv,
++		       const struct dpaa2_fd *fd,
++		       void *vaddr)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	dma_addr_t addr = dpaa2_fd_get_addr(fd);
++	u8 fd_format = dpaa2_fd_get_format(fd);
++	struct dpaa2_sg_entry *sgt;
++	void *sg_vaddr;
++	int i;
++
++	/* If single buffer frame, just free the data buffer */
++	if (fd_format == dpaa2_fd_single)
++		goto free_buf;
++	else if (fd_format != dpaa2_fd_sg)
++		/* We don't support any other format */
++		return;
++
++	/* For S/G frames, we first need to free all SG entries
++	 * except the first one, which was taken care of already
++	 */
++	sgt = vaddr + dpaa2_fd_get_offset(fd);
++	for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
++		addr = dpaa2_sg_get_addr(&sgt[i]);
++		sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
++		dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
++				 DMA_BIDIRECTIONAL);
++
++		skb_free_frag(sg_vaddr);
++		if (dpaa2_sg_is_final(&sgt[i]))
++			break;
++	}
++
++free_buf:
++	skb_free_frag(vaddr);
++}
++
++/* Build a linear skb based on a single-buffer frame descriptor */
++static struct sk_buff *build_linear_skb(struct dpaa2_eth_priv *priv,
++					struct dpaa2_eth_channel *ch,
++					const struct dpaa2_fd *fd,
++					void *fd_vaddr)
++{
++	struct sk_buff *skb = NULL;
++	u16 fd_offset = dpaa2_fd_get_offset(fd);
++	u32 fd_length = dpaa2_fd_get_len(fd);
++
++	ch->buf_count--;
++
++	skb = build_skb(fd_vaddr, DPAA2_ETH_SKB_SIZE);
++	if (unlikely(!skb))
++		return NULL;
++
++	skb_reserve(skb, fd_offset);
++	skb_put(skb, fd_length);
++
++	return skb;
++}
++
++/* Build a non linear (fragmented) skb based on a S/G table */
++static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv,
++				      struct dpaa2_eth_channel *ch,
++				      struct dpaa2_sg_entry *sgt)
++{
++	struct sk_buff *skb = NULL;
++	struct device *dev = priv->net_dev->dev.parent;
++	void *sg_vaddr;
++	dma_addr_t sg_addr;
++	u16 sg_offset;
++	u32 sg_length;
++	struct page *page, *head_page;
++	int page_offset;
++	int i;
++
++	for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
++		struct dpaa2_sg_entry *sge = &sgt[i];
++
++		/* NOTE: We only support SG entries in dpaa2_sg_single format,
++		 * but this is the only format we may receive from HW anyway
++		 */
++
++		/* Get the address and length from the S/G entry */
++		sg_addr = dpaa2_sg_get_addr(sge);
++		sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
++		dma_unmap_single(dev, sg_addr, DPAA2_ETH_RX_BUF_SIZE,
++				 DMA_BIDIRECTIONAL);
++
++		sg_length = dpaa2_sg_get_len(sge);
++
++		if (i == 0) {
++			/* We build the skb around the first data buffer */
++			skb = build_skb(sg_vaddr, DPAA2_ETH_SKB_SIZE);
++			if (unlikely(!skb)) {
++				/* Free the first SG entry now, since we already
++				 * unmapped it and obtained the virtual address
++				 */
++				skb_free_frag(sg_vaddr);
++
++				/* We still need to subtract the buffers used
++				 * by this FD from our software counter
++				 */
++				while (!dpaa2_sg_is_final(&sgt[i]) &&
++				       i < DPAA2_ETH_MAX_SG_ENTRIES)
++					i++;
++				break;
++			}
++
++			sg_offset = dpaa2_sg_get_offset(sge);
++			skb_reserve(skb, sg_offset);
++			skb_put(skb, sg_length);
++		} else {
++			/* Rest of the data buffers are stored as skb frags */
++			page = virt_to_page(sg_vaddr);
++			head_page = virt_to_head_page(sg_vaddr);
++
++			/* Offset in page (which may be compound).
++			 * Data in subsequent SG entries is stored from the
++			 * beginning of the buffer, so we don't need to add the
++			 * sg_offset.
++			 */
++			page_offset = ((unsigned long)sg_vaddr &
++				(PAGE_SIZE - 1)) +
++				(page_address(page) - page_address(head_page));
++
++			skb_add_rx_frag(skb, i - 1, head_page, page_offset,
++					sg_length, DPAA2_ETH_RX_BUF_SIZE);
++		}
++
++		if (dpaa2_sg_is_final(sge))
++			break;
++	}
++
++	WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
++
++	/* Count all data buffers + SG table buffer */
++	ch->buf_count -= i + 2;
++
++	return skb;
++}
++
++static int dpaa2_eth_xdp_tx(struct dpaa2_eth_priv *priv,
++			    struct dpaa2_fd *fd,
++			    void *buf_start,
++			    u16 queue_id)
++{
++	struct dpaa2_eth_fq *fq;
++	struct rtnl_link_stats64 *percpu_stats;
++	struct dpaa2_eth_drv_stats *percpu_extras;
++	struct dpaa2_faead *faead;
++	u32 ctrl, frc;
++	int i, err;
++
++	/* Mark the egress frame annotation area as valid */
++	frc = dpaa2_fd_get_frc(fd);
++	dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
++	dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL);
++
++	ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV;
++	faead = dpaa2_get_faead(buf_start, false);
++	faead->ctrl = cpu_to_le32(ctrl);
++	faead->conf_fqid = 0;
++
++	percpu_stats = this_cpu_ptr(priv->percpu_stats);
++	percpu_extras = this_cpu_ptr(priv->percpu_extras);
++
++	fq = &priv->fq[queue_id];
++	for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
++		err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
++						  priv->tx_qdid, 0,
++						  fq->tx_qdbin, fd);
++		if (err != -EBUSY)
++			break;
++	}
++
++	percpu_extras->tx_portal_busy += i;
++	if (unlikely(err)) {
++		percpu_stats->tx_errors++;
++	} else {
++		percpu_stats->tx_packets++;
++		percpu_stats->tx_bytes += dpaa2_fd_get_len(fd);
++	}
++
++	return err;
++}
++
++static void free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array, int count)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	void *vaddr;
++	int i;
++
++	for (i = 0; i < count; i++) {
++		/* Same logic as on regular Rx path */
++		vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
++		dma_unmap_single(dev, buf_array[i], DPAA2_ETH_RX_BUF_SIZE,
++				 DMA_BIDIRECTIONAL);
++		skb_free_frag(vaddr);
++	}
++}
++
++static void release_fd_buf(struct dpaa2_eth_priv *priv,
++			   struct dpaa2_eth_channel *ch,
++			   dma_addr_t addr)
++{
++	int err;
++
++	ch->rel_buf_array[ch->rel_buf_cnt++] = addr;
++	if (likely(ch->rel_buf_cnt < DPAA2_ETH_BUFS_PER_CMD))
++		return;
++
++	while ((err = dpaa2_io_service_release(ch->dpio, priv->bpid,
++					       ch->rel_buf_array,
++					       ch->rel_buf_cnt)) == -EBUSY)
++		cpu_relax();
++
++	if (err)
++		free_bufs(priv, ch->rel_buf_array, ch->rel_buf_cnt);
++
++	ch->rel_buf_cnt = 0;
++}
++
++/* Main Rx frame processing routine */
++static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
++			 struct dpaa2_eth_channel *ch,
++			 const struct dpaa2_fd *fd,
++			 struct napi_struct *napi,
++			 u16 queue_id)
++{
++	dma_addr_t addr = dpaa2_fd_get_addr(fd);
++	u8 fd_format = dpaa2_fd_get_format(fd);
++	void *vaddr;
++	struct sk_buff *skb;
++	struct rtnl_link_stats64 *percpu_stats;
++	struct dpaa2_eth_drv_stats *percpu_extras;
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpaa2_fas *fas;
++	void *buf_data;
++	u32 status = 0;
++	struct bpf_prog *xdp_prog;
++	struct xdp_buff xdp;
++	u32 xdp_act;
++
++	/* Tracing point */
++	trace_dpaa2_rx_fd(priv->net_dev, fd);
++
++	vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
++	dma_sync_single_for_cpu(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
++				DMA_BIDIRECTIONAL);
++
++	fas = dpaa2_get_fas(vaddr, false);
++	prefetch(fas);
++	buf_data = vaddr + dpaa2_fd_get_offset(fd);
++	prefetch(buf_data);
++
++	percpu_stats = this_cpu_ptr(priv->percpu_stats);
++	percpu_extras = this_cpu_ptr(priv->percpu_extras);
++
++	xdp_prog = READ_ONCE(ch->xdp_prog);
++
++	if (fd_format == dpaa2_fd_single) {
++		if (xdp_prog) {
++			xdp.data = buf_data;
++			xdp.data_end = buf_data + dpaa2_fd_get_len(fd);
++			/* for now, we don't support changes in header size */
++			xdp.data_hard_start = buf_data;
++
++			/* update stats here, as we won't reach the code
++			 * that does that for standard frames
++			 */
++			percpu_stats->rx_packets++;
++			percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
++
++			xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
++			switch (xdp_act) {
++			case XDP_PASS:
++				break;
++			default:
++				bpf_warn_invalid_xdp_action(xdp_act);
++			case XDP_ABORTED:
++			case XDP_DROP:
++				release_fd_buf(priv, ch, addr);
++				goto drop_cnt;
++			case XDP_TX:
++				if (dpaa2_eth_xdp_tx(priv, (struct dpaa2_fd *)fd, vaddr,
++						     queue_id)) {
++					dma_unmap_single(dev, addr,
++							 DPAA2_ETH_RX_BUF_SIZE,
++							 DMA_BIDIRECTIONAL);
++					free_rx_fd(priv, fd, vaddr);
++					ch->buf_count--;
++				}
++				return;
++			}
++		}
++		dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
++				 DMA_BIDIRECTIONAL);
++		skb = build_linear_skb(priv, ch, fd, vaddr);
++	} else if (fd_format == dpaa2_fd_sg) {
++		dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE,
++				 DMA_BIDIRECTIONAL);
++		skb = build_frag_skb(priv, ch, buf_data);
++		skb_free_frag(vaddr);
++		percpu_extras->rx_sg_frames++;
++		percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
++	} else {
++		/* We don't support any other format */
++		goto drop_cnt;
++	}
++
++	if (unlikely(!skb))
++		goto drop_fd;
++
++	prefetch(skb->data);
++
++	/* Get the timestamp value */
++	if (priv->ts_rx_en) {
++		struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
++		u64 *ns = dpaa2_get_ts(vaddr, false);
++
++		*ns = DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS * le64_to_cpup(ns);
++		memset(shhwtstamps, 0, sizeof(*shhwtstamps));
++		shhwtstamps->hwtstamp = ns_to_ktime(*ns);
++	}
++
++	/* Check if we need to validate the L4 csum */
++	if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
++		status = le32_to_cpu(fas->status);
++		validate_rx_csum(priv, status, skb);
++	}
++
++	skb->protocol = eth_type_trans(skb, priv->net_dev);
++
++	/* Record Rx queue - this will be used when picking a Tx queue to
++	 * forward the frames. We're keeping flow affinity through the
++	 * network stack.
++	 */
++	skb_record_rx_queue(skb, queue_id);
++
++	percpu_stats->rx_packets++;
++	percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
++
++	napi_gro_receive(napi, skb);
++
++	return;
++
++drop_fd:
++	free_rx_fd(priv, fd, vaddr);
++drop_cnt:
++	percpu_stats->rx_dropped++;
++}
++
++#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
++/* Processing of Rx frames received on the error FQ
++ * We check and print the error bits and then free the frame
++ */
++static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv,
++			     struct dpaa2_eth_channel *ch,
++			     const struct dpaa2_fd *fd,
++			     struct napi_struct *napi __always_unused,
++			     u16 queue_id __always_unused)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	dma_addr_t addr = dpaa2_fd_get_addr(fd);
++	void *vaddr;
++	struct rtnl_link_stats64 *percpu_stats;
++	struct dpaa2_fas *fas;
++	u32 status = 0;
++	u32 fd_errors;
++	bool has_fas_errors = false;
++
++	vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
++	dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_BIDIRECTIONAL);
++
++	/* check frame errors in the FD field */
++	fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_RX_ERR_MASK;
++	if (likely(fd_errors)) {
++		has_fas_errors = (fd_errors & FD_CTRL_FAERR) &&
++				 !!(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV);
++		if (net_ratelimit())
++			netdev_dbg(priv->net_dev, "RX frame FD err: %08x\n",
++				   fd_errors);
++	}
++
++	/* check frame errors in the FAS field */
++	if (has_fas_errors) {
++		fas = dpaa2_get_fas(vaddr, false);
++		status = le32_to_cpu(fas->status);
++		if (net_ratelimit())
++			netdev_dbg(priv->net_dev, "Rx frame FAS err: 0x%08x\n",
++				   status & DPAA2_FAS_RX_ERR_MASK);
++	}
++	free_rx_fd(priv, fd, vaddr);
++
++	percpu_stats = this_cpu_ptr(priv->percpu_stats);
++	percpu_stats->rx_errors++;
++	ch->buf_count--;
++}
++#endif
++
++/* Consume all frames pull-dequeued into the store. This is the simplest way to
++ * make sure we don't accidentally issue another volatile dequeue which would
++ * overwrite (leak) frames already in the store.
++ *
++ * The number of frames is returned using the last 2 output arguments,
++ * separately for Rx and Tx confirmations.
++ *
++ * Observance of NAPI budget is not our concern, leaving that to the caller.
++ */
++static bool consume_frames(struct dpaa2_eth_channel *ch, int *rx_cleaned,
++			   int *tx_conf_cleaned)
++{
++	struct dpaa2_eth_priv *priv = ch->priv;
++	struct dpaa2_eth_fq *fq = NULL;
++	struct dpaa2_dq *dq;
++	const struct dpaa2_fd *fd;
++	int cleaned = 0;
++	int is_last;
++
++	do {
++		dq = dpaa2_io_store_next(ch->store, &is_last);
++		if (unlikely(!dq)) {
++			/* If we're here, we *must* have placed a
++			 * volatile dequeue comnmand, so keep reading through
++			 * the store until we get some sort of valid response
++			 * token (either a valid frame or an "empty dequeue")
++			 */
++			continue;
++		}
++
++		fd = dpaa2_dq_fd(dq);
++		prefetch(fd);
++
++		fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
++		fq->consume(priv, ch, fd, &ch->napi, fq->flowid);
++		cleaned++;
++	} while (!is_last);
++
++	if (!cleaned)
++		return false;
++
++	/* All frames brought in store by a volatile dequeue
++	 * come from the same queue
++	 */
++	if (fq->type == DPAA2_TX_CONF_FQ)
++		*tx_conf_cleaned += cleaned;
++	else
++		*rx_cleaned += cleaned;
++
++	fq->stats.frames += cleaned;
++	ch->stats.frames += cleaned;
++
++	return true;
++}
++
++/* Configure the egress frame annotation for timestamp update */
++static void enable_tx_tstamp(struct dpaa2_fd *fd, void *buf_start)
++{
++	struct dpaa2_faead *faead;
++	u32 ctrl, frc;
++
++	/* Mark the egress frame annotation area as valid */
++	frc = dpaa2_fd_get_frc(fd);
++	dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
++
++	/* Set hardware annotation size */
++	ctrl = dpaa2_fd_get_ctrl(fd);
++	dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
++
++	/* enable UPD (update prepanded data) bit in FAEAD field of
++	 * hardware frame annotation area
++	 */
++	ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
++	faead = dpaa2_get_faead(buf_start, true);
++	faead->ctrl = cpu_to_le32(ctrl);
++}
++
++/* Create a frame descriptor based on a fragmented skb */
++static int build_sg_fd(struct dpaa2_eth_priv *priv,
++		       struct sk_buff *skb,
++		       struct dpaa2_fd *fd)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	void *sgt_buf = NULL;
++	dma_addr_t addr;
++	int nr_frags = skb_shinfo(skb)->nr_frags;
++	struct dpaa2_sg_entry *sgt;
++	int i, err;
++	int sgt_buf_size;
++	struct scatterlist *scl, *crt_scl;
++	int num_sg;
++	int num_dma_bufs;
++	struct dpaa2_eth_swa *swa;
++
++	/* Create and map scatterlist.
++	 * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
++	 * to go beyond nr_frags+1.
++	 * Note: We don't support chained scatterlists
++	 */
++	if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
++		return -EINVAL;
++
++	scl = kcalloc(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
++	if (unlikely(!scl))
++		return -ENOMEM;
++
++	sg_init_table(scl, nr_frags + 1);
++	num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
++	num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
++	if (unlikely(!num_dma_bufs)) {
++		err = -ENOMEM;
++		goto dma_map_sg_failed;
++	}
++
++	/* Prepare the HW SGT structure */
++	sgt_buf_size = priv->tx_data_offset +
++		       sizeof(struct dpaa2_sg_entry) *  num_dma_bufs;
++	sgt_buf = netdev_alloc_frag(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN);
++	if (unlikely(!sgt_buf)) {
++		err = -ENOMEM;
++		goto sgt_buf_alloc_failed;
++	}
++	sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
++	memset(sgt_buf, 0, sgt_buf_size);
++
++	sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
++
++	/* Fill in the HW SGT structure.
++	 *
++	 * sgt_buf is zeroed out, so the following fields are implicit
++	 * in all sgt entries:
++	 *   - offset is 0
++	 *   - format is 'dpaa2_sg_single'
++	 */
++	for_each_sg(scl, crt_scl, num_dma_bufs, i) {
++		dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
++		dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
++	}
++	dpaa2_sg_set_final(&sgt[i - 1], true);
++
++	/* Store the skb backpointer in the SGT buffer.
++	 * Fit the scatterlist and the number of buffers alongside the
++	 * skb backpointer in the software annotation area. We'll need
++	 * all of them on Tx Conf.
++	 */
++	swa = (struct dpaa2_eth_swa *)sgt_buf;
++	swa->type = DPAA2_ETH_SWA_SG;
++	swa->sg.skb = skb;
++	swa->sg.scl = scl;
++	swa->sg.num_sg = num_sg;
++	swa->sg.sgt_size = sgt_buf_size;
++
++	/* Separately map the SGT buffer */
++	addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
++	if (unlikely(dma_mapping_error(dev, addr))) {
++		err = -ENOMEM;
++		goto dma_map_single_failed;
++	}
++	dpaa2_fd_set_offset(fd, priv->tx_data_offset);
++	dpaa2_fd_set_format(fd, dpaa2_fd_sg);
++	dpaa2_fd_set_addr(fd, addr);
++	dpaa2_fd_set_len(fd, skb->len);
++	dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
++
++	if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
++		enable_tx_tstamp(fd, sgt_buf);
++
++	return 0;
++
++dma_map_single_failed:
++	skb_free_frag(sgt_buf);
++sgt_buf_alloc_failed:
++	dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
++dma_map_sg_failed:
++	kfree(scl);
++	return err;
++}
++
++/* Create a frame descriptor based on a linear skb */
++static int build_single_fd(struct dpaa2_eth_priv *priv,
++			   struct sk_buff *skb,
++			   struct dpaa2_fd *fd)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	u8 *buffer_start, *aligned_start;
++	struct dpaa2_eth_swa *swa;
++	dma_addr_t addr;
++
++	buffer_start = skb->data - dpaa2_eth_needed_headroom(priv, skb);
++
++	/* If there's enough room to align the FD address, do it.
++	 * It will help hardware optimize accesses.
++	 */
++	aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
++				  DPAA2_ETH_TX_BUF_ALIGN);
++	if (aligned_start >= skb->head)
++		buffer_start = aligned_start;
++
++	/* Store a backpointer to the skb at the beginning of the buffer
++	 * (in the private data area) such that we can release it
++	 * on Tx confirm
++	 */
++	swa = (struct dpaa2_eth_swa *)buffer_start;
++	swa->type = DPAA2_ETH_SWA_SINGLE;
++	swa->single.skb = skb;
++
++	addr = dma_map_single(dev, buffer_start,
++			      skb_tail_pointer(skb) - buffer_start,
++			      DMA_BIDIRECTIONAL);
++	if (unlikely(dma_mapping_error(dev, addr)))
++		return -ENOMEM;
++
++	dpaa2_fd_set_addr(fd, addr);
++	dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
++	dpaa2_fd_set_len(fd, skb->len);
++	dpaa2_fd_set_format(fd, dpaa2_fd_single);
++	dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
++
++	if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
++		enable_tx_tstamp(fd, buffer_start);
++
++	return 0;
++}
++
++/* FD freeing routine on the Tx path
++ *
++ * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb
++ * back-pointed to is also freed.
++ * This can be called either from dpaa2_eth_tx_conf() or on the error path of
++ * dpaa2_eth_tx().
++ * Optionally, return the frame annotation status word (FAS), which needs
++ * to be checked if we're on the confirmation path.
++ */
++static void free_tx_fd(struct dpaa2_eth_priv *priv,
++		       const struct dpaa2_fd *fd,
++		       bool in_napi)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	dma_addr_t fd_addr;
++	struct sk_buff *skb = NULL;
++	unsigned char *buffer_start;
++	struct dpaa2_eth_swa *swa;
++	u8 fd_format = dpaa2_fd_get_format(fd);
++
++	fd_addr = dpaa2_fd_get_addr(fd);
++	buffer_start = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
++	swa = (struct dpaa2_eth_swa *)buffer_start;
++
++	if (fd_format == dpaa2_fd_single) {
++		skb = swa->single.skb;
++		/* Accessing the skb buffer is safe before dma unmap, because
++		 * we didn't map the actual skb shell.
++		 */
++		dma_unmap_single(dev, fd_addr,
++				 skb_tail_pointer(skb) - buffer_start,
++				 DMA_BIDIRECTIONAL);
++	} else if (fd_format == dpaa2_fd_sg) {
++		skb = swa->sg.skb;
++
++		/* Unmap the scatterlist */
++		dma_unmap_sg(dev, swa->sg.scl, swa->sg.num_sg, DMA_BIDIRECTIONAL);
++		kfree(swa->sg.scl);
++
++		/* Unmap the SGT buffer */
++		dma_unmap_single(dev, fd_addr, swa->sg.sgt_size,
++				 DMA_BIDIRECTIONAL);
++	} else {
++		netdev_dbg(priv->net_dev, "Invalid FD format\n");
++		return;
++	}
++
++	/* Get the timestamp value */
++	if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
++		struct skb_shared_hwtstamps shhwtstamps;
++		u64 *ns;
++
++		memset(&shhwtstamps, 0, sizeof(shhwtstamps));
++
++		ns = dpaa2_get_ts(buffer_start, true);
++		*ns = DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS * le64_to_cpup(ns);
++		shhwtstamps.hwtstamp = ns_to_ktime(*ns);
++		skb_tstamp_tx(skb, &shhwtstamps);
++	}
++
++	/* Free SGT buffer allocated on tx */
++	if (fd_format != dpaa2_fd_single)
++		skb_free_frag(buffer_start);
++
++	/* Move on with skb release */
++	napi_consume_skb(skb, in_napi);
++}
++
++static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct device *dev = net_dev->dev.parent;
++	struct dpaa2_fd fd;
++	struct rtnl_link_stats64 *percpu_stats;
++	struct dpaa2_eth_drv_stats *percpu_extras;
++	unsigned int needed_headroom;
++	struct dpaa2_eth_fq *fq;
++	u16 queue_mapping;
++	int err, i, ch_id = 0, qpri = 0;
++
++	queue_mapping = skb_get_queue_mapping(skb);
++	fq = &priv->fq[queue_mapping];
++
++	/* If we're congested, stop this tx queue; transmission of
++	 * the current skb happens regardless of congestion state
++	 */
++	dma_sync_single_for_cpu(dev, priv->cscn_dma,
++				DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
++	if (unlikely(dpaa2_cscn_state_congested(priv->cscn_mem))) {
++		netif_stop_subqueue(net_dev, queue_mapping);
++		fq->stats.congestion_entry++;
++	}
++
++	percpu_stats = this_cpu_ptr(priv->percpu_stats);
++	percpu_extras = this_cpu_ptr(priv->percpu_extras);
++
++	/* For non-linear skb we don't need a minimum headroom */
++	needed_headroom = dpaa2_eth_needed_headroom(priv, skb);
++	if (skb_headroom(skb) < needed_headroom) {
++		struct sk_buff *ns;
++
++		ns = skb_realloc_headroom(skb, needed_headroom);
++		if (unlikely(!ns)) {
++			percpu_stats->tx_dropped++;
++			goto err_alloc_headroom;
++		}
++		percpu_extras->tx_reallocs++;
++		if (skb->sk)
++			skb_set_owner_w(ns, skb->sk);
++		dev_kfree_skb(skb);
++		skb = ns;
++	}
++
++	/* We'll be holding a back-reference to the skb until Tx Confirmation;
++	 * we don't want that overwritten by a concurrent Tx with a cloned skb.
++	 */
++	skb = skb_unshare(skb, GFP_ATOMIC);
++	if (unlikely(!skb)) {
++		/* skb_unshare() has already freed the skb */
++		percpu_stats->tx_dropped++;
++		return NETDEV_TX_OK;
++	}
++
++	/* Setup the FD fields */
++	memset(&fd, 0, sizeof(fd));
++
++	if (skb_is_nonlinear(skb)) {
++		err = build_sg_fd(priv, skb, &fd);
++		percpu_extras->tx_sg_frames++;
++		percpu_extras->tx_sg_bytes += skb->len;
++	} else {
++		err = build_single_fd(priv, skb, &fd);
++	}
++
++	if (unlikely(err)) {
++		percpu_stats->tx_dropped++;
++		goto err_build_fd;
++	}
++
++	/* Tracing point */
++	trace_dpaa2_tx_fd(net_dev, &fd);
++
++	if (dpaa2_eth_ceetm_is_enabled(priv)) {
++		err = dpaa2_ceetm_classify(skb, net_dev->qdisc, &ch_id, &qpri);
++		if (err)
++			goto err_ceetm_classify;
++	}
++
++	for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
++		err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
++						  priv->tx_qdid, qpri,
++						  fq->tx_qdbin, &fd);
++		if (err != -EBUSY)
++			break;
++	}
++	percpu_extras->tx_portal_busy += i;
++	if (unlikely(err < 0)) {
++		percpu_stats->tx_errors++;
++		/* Clean up everything, including freeing the skb */
++		free_tx_fd(priv, &fd, false);
++	} else {
++		percpu_stats->tx_packets++;
++		percpu_stats->tx_bytes += dpaa2_fd_get_len(&fd);
++	}
++
++	return NETDEV_TX_OK;
++
++err_ceetm_classify:
++	free_tx_fd(priv, &fd, false);
++err_build_fd:
++err_alloc_headroom:
++	dev_kfree_skb(skb);
++
++	return NETDEV_TX_OK;
++}
++
++/* Tx confirmation frame processing routine */
++static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
++			      struct dpaa2_eth_channel *ch,
++			      const struct dpaa2_fd *fd,
++			      struct napi_struct *napi __always_unused,
++			      u16 queue_id)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct rtnl_link_stats64 *percpu_stats;
++	struct dpaa2_eth_drv_stats *percpu_extras;
++	u32 fd_errors;
++
++	/* Tracing point */
++	trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
++
++	percpu_extras = this_cpu_ptr(priv->percpu_extras);
++	percpu_extras->tx_conf_frames++;
++	percpu_extras->tx_conf_bytes += dpaa2_fd_get_len(fd);
++
++	/* Check congestion state and wake all queues if necessary */
++	if (unlikely(__netif_subqueue_stopped(priv->net_dev, queue_id))) {
++		dma_sync_single_for_cpu(dev, priv->cscn_dma,
++					DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
++		if (!dpaa2_cscn_state_congested(priv->cscn_mem))
++			netif_tx_wake_all_queues(priv->net_dev);
++	}
++
++	/* Check frame errors in the FD field */
++	fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
++	free_tx_fd(priv, fd, true);
++
++	if (likely(!fd_errors))
++		return;
++
++	if (net_ratelimit())
++		netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
++			   fd_errors);
++
++	percpu_stats = this_cpu_ptr(priv->percpu_stats);
++	/* Tx-conf logically pertains to the egress path. */
++	percpu_stats->tx_errors++;
++}
++
++static int set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
++{
++	int err;
++
++	err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
++			       DPNI_OFF_RX_L3_CSUM, enable);
++	if (err) {
++		netdev_err(priv->net_dev,
++			   "dpni_set_offload(RX_L3_CSUM) failed\n");
++		return err;
++	}
++
++	err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
++			       DPNI_OFF_RX_L4_CSUM, enable);
++	if (err) {
++		netdev_err(priv->net_dev,
++			   "dpni_set_offload(RX_L4_CSUM) failed\n");
++		return err;
++	}
++
++	return 0;
++}
++
++static int set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
++{
++	int err;
++
++	err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
++			       DPNI_OFF_TX_L3_CSUM, enable);
++	if (err) {
++		netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n");
++		return err;
++	}
++
++	err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
++			       DPNI_OFF_TX_L4_CSUM, enable);
++	if (err) {
++		netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n");
++		return err;
++	}
++
++	return 0;
++}
++
++/* Perform a single release command to add buffers
++ * to the specified buffer pool
++ */
++static int add_bufs(struct dpaa2_eth_priv *priv,
++		    struct dpaa2_eth_channel *ch, u16 bpid)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
++	void *buf;
++	dma_addr_t addr;
++	int i, err;
++
++	for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
++		/* Allocate buffer visible to WRIOP + skb shared info +
++		 * alignment padding
++		 */
++		buf = napi_alloc_frag(dpaa2_eth_buf_raw_size(priv));
++		if (unlikely(!buf))
++			goto err_alloc;
++
++		buf = PTR_ALIGN(buf, priv->rx_buf_align);
++
++		addr = dma_map_single(dev, buf, DPAA2_ETH_RX_BUF_SIZE,
++				      DMA_BIDIRECTIONAL);
++		if (unlikely(dma_mapping_error(dev, addr)))
++			goto err_map;
++
++		buf_array[i] = addr;
++
++		/* tracing point */
++		trace_dpaa2_eth_buf_seed(priv->net_dev,
++					 buf, dpaa2_eth_buf_raw_size(priv),
++					 addr, DPAA2_ETH_RX_BUF_SIZE,
++					 bpid);
++	}
++
++release_bufs:
++	/* In case the portal is busy, retry until successful */
++	while ((err = dpaa2_io_service_release(ch->dpio, bpid,
++					       buf_array, i)) == -EBUSY)
++		cpu_relax();
++
++	/* If release command failed, clean up and bail out; not much
++	 * else we can do about it
++	 */
++	if (err) {
++		free_bufs(priv, buf_array, i);
++		return 0;
++	}
++
++	return i;
++
++err_map:
++	skb_free_frag(buf);
++err_alloc:
++	/* If we managed to allocate at least some buffers, release them */
++	if (i)
++		goto release_bufs;
++
++	return 0;
++}
++
++static int seed_pool(struct dpaa2_eth_priv *priv, u16 bpid)
++{
++	int i, j;
++	int new_count;
++
++	/* This is the lazy seeding of Rx buffer pools.
++	 * dpaa2_add_bufs() is also used on the Rx hotpath and calls
++	 * napi_alloc_frag(). The trouble with that is that it in turn ends up
++	 * calling this_cpu_ptr(), which mandates execution in atomic context.
++	 * Rather than splitting up the code, do a one-off preempt disable.
++	 */
++	preempt_disable();
++	for (j = 0; j < priv->num_channels; j++) {
++		priv->channel[j]->buf_count = 0;
++		for (i = 0; i < priv->max_bufs_per_ch;
++		     i += DPAA2_ETH_BUFS_PER_CMD) {
++			new_count = add_bufs(priv, priv->channel[j], bpid);
++			priv->channel[j]->buf_count += new_count;
++
++			if (new_count < DPAA2_ETH_BUFS_PER_CMD) {
++				preempt_enable();
++				return -ENOMEM;
++			}
++		}
++	}
++	preempt_enable();
++
++	return 0;
++}
++
++/**
++ * Drain the specified number of buffers from the DPNI's private buffer pool.
++ * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD
++ */
++static void drain_bufs(struct dpaa2_eth_priv *priv, int count)
++{
++	u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
++	int ret;
++
++	do {
++		ret = dpaa2_io_service_acquire(NULL, priv->bpid,
++					       buf_array, count);
++		if (ret < 0) {
++			netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
++			return;
++		}
++		free_bufs(priv, buf_array, ret);
++	} while (ret);
++}
++
++static void drain_pool(struct dpaa2_eth_priv *priv)
++{
++	preempt_disable();
++	drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD);
++	drain_bufs(priv, 1);
++	preempt_enable();
++}
++
++/* Function is called from softirq context only, so we don't need to guard
++ * the access to percpu count
++ */
++static int refill_pool(struct dpaa2_eth_priv *priv,
++		       struct dpaa2_eth_channel *ch,
++		       u16 bpid)
++{
++	int new_count;
++
++	if (likely(ch->buf_count >= priv->refill_thresh))
++		return 0;
++
++	do {
++		new_count = add_bufs(priv, ch, bpid);
++		if (unlikely(!new_count)) {
++			/* Out of memory; abort for now, we'll try later on */
++			break;
++		}
++		ch->buf_count += new_count;
++	} while (ch->buf_count < priv->max_bufs_per_ch);
++
++	if (unlikely(ch->buf_count < priv->max_bufs_per_ch))
++		return -ENOMEM;
++
++	return 0;
++}
++
++static int pull_channel(struct dpaa2_eth_channel *ch)
++{
++	int err;
++	int dequeues = -1;
++
++	/* Retry while portal is busy */
++	do {
++		err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id,
++						    ch->store);
++		dequeues++;
++		cpu_relax();
++	} while (err == -EBUSY);
++
++	ch->stats.dequeue_portal_busy += dequeues;
++	if (unlikely(err))
++		ch->stats.pull_err++;
++
++	return err;
++}
++
++/* NAPI poll routine
++ *
++ * Frames are dequeued from the QMan channel associated with this NAPI context.
++ * Rx and (if configured) Rx error frames count towards the NAPI budget. Tx
++ * confirmation frames are limited by a threshold per NAPI poll cycle.
++ */
++static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
++{
++	struct dpaa2_eth_channel *ch;
++	int rx_cleaned = 0, tx_conf_cleaned = 0;
++	bool store_cleaned;
++	struct dpaa2_eth_priv *priv;
++	int err;
++
++	ch = container_of(napi, struct dpaa2_eth_channel, napi);
++	priv = ch->priv;
++
++	do {
++		err = pull_channel(ch);
++		if (unlikely(err))
++			break;
++
++		/* Refill pool if appropriate */
++		refill_pool(priv, ch, priv->bpid);
++
++		store_cleaned = consume_frames(ch, &rx_cleaned,
++					       &tx_conf_cleaned);
++
++		/* If we've either consumed the budget with Rx frames,
++		 * or reached the Tx conf threshold, we're done.
++		 */
++		if (rx_cleaned >= budget ||
++		    tx_conf_cleaned >= TX_CONF_PER_NAPI_POLL)
++			return budget;
++	} while (store_cleaned);
++
++	/* We didn't consume the entire budget, finish napi and
++	 * re-enable data availability notifications
++	 */
++	napi_complete(napi);
++	do {
++		err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx);
++		cpu_relax();
++	} while (err == -EBUSY);
++		WARN_ONCE(err, "CDAN notifications rearm failed on core %d",
++			  ch->nctx.desired_cpu);
++
++	return max(rx_cleaned, 1);
++}
++
++static void enable_ch_napi(struct dpaa2_eth_priv *priv)
++{
++	struct dpaa2_eth_channel *ch;
++	int i;
++
++	for (i = 0; i < priv->num_channels; i++) {
++		ch = priv->channel[i];
++		napi_enable(&ch->napi);
++	}
++}
++
++static void disable_ch_napi(struct dpaa2_eth_priv *priv)
++{
++	struct dpaa2_eth_channel *ch;
++	int i;
++
++	for (i = 0; i < priv->num_channels; i++) {
++		ch = priv->channel[i];
++		napi_disable(&ch->napi);
++	}
++}
++
++static int link_state_update(struct dpaa2_eth_priv *priv)
++{
++	struct dpni_link_state state;
++	int err;
++
++	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
++	if (unlikely(err)) {
++		netdev_err(priv->net_dev,
++			   "dpni_get_link_state() failed\n");
++		return err;
++	}
++
++	/* Chech link state; speed / duplex changes are not treated yet */
++	if (priv->link_state.up == state.up)
++		return 0;
++
++	priv->link_state = state;
++	if (state.up) {
++		netif_carrier_on(priv->net_dev);
++		netif_tx_start_all_queues(priv->net_dev);
++	} else {
++		netif_tx_stop_all_queues(priv->net_dev);
++		netif_carrier_off(priv->net_dev);
++	}
++
++	netdev_info(priv->net_dev, "Link Event: state %s\n",
++		    state.up ? "up" : "down");
++
++	return 0;
++}
++
++static int dpaa2_eth_open(struct net_device *net_dev)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	int err;
++
++	/* We'll only start the txqs when the link is actually ready; make sure
++	 * we don't race against the link up notification, which may come
++	 * immediately after dpni_enable();
++	 */
++	netif_tx_stop_all_queues(net_dev);
++
++	/* Also, explicitly set carrier off, otherwise netif_carrier_ok() will
++	 * return true and cause 'ip link show' to report the LOWER_UP flag,
++	 * even though the link notification wasn't even received.
++	 */
++	netif_carrier_off(net_dev);
++
++	err = seed_pool(priv, priv->bpid);
++	if (err) {
++		/* Not much to do; the buffer pool, though not filled up,
++		 * may still contain some buffers which would enable us
++		 * to limp on.
++		 */
++		netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
++			   priv->dpbp_dev->obj_desc.id, priv->bpid);
++	}
++
++	priv->refill_thresh = DPAA2_ETH_REFILL_THRESH(priv);
++
++	err = dpni_enable(priv->mc_io, 0, priv->mc_token);
++	if (err < 0) {
++		netdev_err(net_dev, "dpni_enable() failed\n");
++		goto enable_err;
++	}
++
++	/* If the DPMAC object has already processed the link up interrupt,
++	 * we have to learn the link state ourselves.
++	 */
++	err = link_state_update(priv);
++	if (err < 0) {
++		netdev_err(net_dev, "Can't update link state\n");
++		goto link_state_err;
++	}
++
++	return 0;
++
++link_state_err:
++enable_err:
++	priv->refill_thresh = 0;
++	drain_pool(priv);
++	return err;
++}
++
++static int dpaa2_eth_stop(struct net_device *net_dev)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	int dpni_enabled;
++	int retries = 10, i;
++	int err = 0;
++
++	netif_tx_stop_all_queues(net_dev);
++	netif_carrier_off(net_dev);
++
++	/* Loop while dpni_disable() attempts to drain the egress FQs
++	 * and confirm them back to us.
++	 */
++	do {
++		dpni_disable(priv->mc_io, 0, priv->mc_token);
++		dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled);
++		if (dpni_enabled)
++			/* Allow the hardware some slack */
++			msleep(100);
++	} while (dpni_enabled && --retries);
++	if (!retries) {
++		netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
++		/* Must go on and finish processing pending frames, so we don't
++		 * crash at the next "ifconfig up"
++		 */
++		err = -ETIMEDOUT;
++	}
++
++	priv->refill_thresh = 0;
++
++	/* Wait for all running napi poll routines to finish, so that no
++	 * new refill operations are started
++	 */
++	for (i = 0; i < priv->num_channels; i++)
++		napi_synchronize(&priv->channel[i]->napi);
++
++	/* Empty the buffer pool */
++	drain_pool(priv);
++
++	return err;
++}
++
++static int dpaa2_eth_init(struct net_device *net_dev)
++{
++	u64 supported = 0;
++	u64 not_supported = 0;
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	u32 options = priv->dpni_attrs.options;
++
++	/* Capabilities listing */
++	supported |= IFF_LIVE_ADDR_CHANGE;
++
++	if (options & DPNI_OPT_NO_MAC_FILTER)
++		not_supported |= IFF_UNICAST_FLT;
++	else
++		supported |= IFF_UNICAST_FLT;
++
++	net_dev->priv_flags |= supported;
++	net_dev->priv_flags &= ~not_supported;
++
++	/* Features */
++	net_dev->features = NETIF_F_RXCSUM |
++			    NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
++			    NETIF_F_SG | NETIF_F_HIGHDMA |
++			    NETIF_F_LLTX;
++	net_dev->hw_features = net_dev->features;
++
++	return 0;
++}
++
++static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct device *dev = net_dev->dev.parent;
++	int err;
++
++	err = eth_mac_addr(net_dev, addr);
++	if (err < 0) {
++		dev_err(dev, "eth_mac_addr() failed (%d)\n", err);
++		return err;
++	}
++
++	err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
++					net_dev->dev_addr);
++	if (err) {
++		dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err);
++		return err;
++	}
++
++	return 0;
++}
++
++/** Fill in counters maintained by the GPP driver. These may be different from
++ * the hardware counters obtained by ethtool.
++ */
++static struct rtnl_link_stats64 *dpaa2_eth_get_stats(struct net_device *net_dev,
++				struct rtnl_link_stats64 *stats)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct rtnl_link_stats64 *percpu_stats;
++	u64 *cpustats;
++	u64 *netstats = (u64 *)stats;
++	int i, j;
++	int num = sizeof(struct rtnl_link_stats64) / sizeof(u64);
++
++	for_each_possible_cpu(i) {
++		percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
++		cpustats = (u64 *)percpu_stats;
++		for (j = 0; j < num; j++)
++			netstats[j] += cpustats[j];
++	}
++	return stats;
++}
++
++/* Copy mac unicast addresses from @net_dev to @priv.
++ * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
++ */
++static void add_uc_hw_addr(const struct net_device *net_dev,
++			   struct dpaa2_eth_priv *priv)
++{
++	struct netdev_hw_addr *ha;
++	int err;
++
++	netdev_for_each_uc_addr(ha, net_dev) {
++		err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
++					ha->addr);
++		if (err)
++			netdev_warn(priv->net_dev,
++				    "Could not add ucast MAC %pM to the filtering table (err %d)\n",
++				    ha->addr, err);
++	}
++}
++
++/* Copy mac multicast addresses from @net_dev to @priv
++ * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
++ */
++static void add_mc_hw_addr(const struct net_device *net_dev,
++			   struct dpaa2_eth_priv *priv)
++{
++	struct netdev_hw_addr *ha;
++	int err;
++
++	netdev_for_each_mc_addr(ha, net_dev) {
++		err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
++					ha->addr);
++		if (err)
++			netdev_warn(priv->net_dev,
++				    "Could not add mcast MAC %pM to the filtering table (err %d)\n",
++				    ha->addr, err);
++	}
++}
++
++static void dpaa2_eth_set_rx_mode(struct net_device *net_dev)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	int uc_count = netdev_uc_count(net_dev);
++	int mc_count = netdev_mc_count(net_dev);
++	u8 max_mac = priv->dpni_attrs.mac_filter_entries;
++	u32 options = priv->dpni_attrs.options;
++	u16 mc_token = priv->mc_token;
++	struct fsl_mc_io *mc_io = priv->mc_io;
++	int err;
++
++	/* Basic sanity checks; these probably indicate a misconfiguration */
++	if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0)
++		netdev_info(net_dev,
++			    "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n",
++			    max_mac);
++
++	/* Force promiscuous if the uc or mc counts exceed our capabilities. */
++	if (uc_count > max_mac) {
++		netdev_info(net_dev,
++			    "Unicast addr count reached %d, max allowed is %d; forcing promisc\n",
++			    uc_count, max_mac);
++		goto force_promisc;
++	}
++	if (mc_count + uc_count > max_mac) {
++		netdev_info(net_dev,
++			    "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n",
++			    uc_count + mc_count, max_mac);
++		goto force_mc_promisc;
++	}
++
++	/* Adjust promisc settings due to flag combinations */
++	if (net_dev->flags & IFF_PROMISC)
++		goto force_promisc;
++	if (net_dev->flags & IFF_ALLMULTI) {
++		/* First, rebuild unicast filtering table. This should be done
++		 * in promisc mode, in order to avoid frame loss while we
++		 * progressively add entries to the table.
++		 * We don't know whether we had been in promisc already, and
++		 * making an MC call to find out is expensive; so set uc promisc
++		 * nonetheless.
++		 */
++		err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
++		if (err)
++			netdev_warn(net_dev, "Can't set uc promisc\n");
++
++		/* Actual uc table reconstruction. */
++		err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0);
++		if (err)
++			netdev_warn(net_dev, "Can't clear uc filters\n");
++		add_uc_hw_addr(net_dev, priv);
++
++		/* Finally, clear uc promisc and set mc promisc as requested. */
++		err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
++		if (err)
++			netdev_warn(net_dev, "Can't clear uc promisc\n");
++		goto force_mc_promisc;
++	}
++
++	/* Neither unicast, nor multicast promisc will be on... eventually.
++	 * For now, rebuild mac filtering tables while forcing both of them on.
++	 */
++	err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
++	if (err)
++		netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err);
++	err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
++	if (err)
++		netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err);
++
++	/* Actual mac filtering tables reconstruction */
++	err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1);
++	if (err)
++		netdev_warn(net_dev, "Can't clear mac filters\n");
++	add_mc_hw_addr(net_dev, priv);
++	add_uc_hw_addr(net_dev, priv);
++
++	/* Now we can clear both ucast and mcast promisc, without risking
++	 * to drop legitimate frames anymore.
++	 */
++	err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
++	if (err)
++		netdev_warn(net_dev, "Can't clear ucast promisc\n");
++	err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0);
++	if (err)
++		netdev_warn(net_dev, "Can't clear mcast promisc\n");
++
++	return;
++
++force_promisc:
++	err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
++	if (err)
++		netdev_warn(net_dev, "Can't set ucast promisc\n");
++force_mc_promisc:
++	err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
++	if (err)
++		netdev_warn(net_dev, "Can't set mcast promisc\n");
++}
++
++static int dpaa2_eth_set_features(struct net_device *net_dev,
++				  netdev_features_t features)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	netdev_features_t changed = features ^ net_dev->features;
++	bool enable;
++	int err;
++
++	if (changed & NETIF_F_RXCSUM) {
++		enable = !!(features & NETIF_F_RXCSUM);
++		err = set_rx_csum(priv, enable);
++		if (err)
++			return err;
++	}
++
++	if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
++		enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
++		err = set_tx_csum(priv, enable);
++		if (err)
++			return err;
++	}
++
++	return 0;
++}
++
++static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(dev);
++	struct hwtstamp_config config;
++
++	if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
++		return -EFAULT;
++
++	switch (config.tx_type) {
++	case HWTSTAMP_TX_OFF:
++		priv->ts_tx_en = false;
++		break;
++	case HWTSTAMP_TX_ON:
++		priv->ts_tx_en = true;
++		break;
++	default:
++		return -ERANGE;
++	}
++
++	if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
++		priv->ts_rx_en = false;
++	} else {
++		priv->ts_rx_en = true;
++		/* TS is set for all frame types, not only those requested */
++		config.rx_filter = HWTSTAMP_FILTER_ALL;
++	}
++
++	return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
++			-EFAULT : 0;
++}
++
++static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
++{
++	if (cmd == SIOCSHWTSTAMP)
++		return dpaa2_eth_ts_ioctl(dev, rq, cmd);
++
++	return -EINVAL;
++}
++
++static int set_buffer_layout(struct dpaa2_eth_priv *priv)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpni_buffer_layout buf_layout = {0};
++	int err;
++
++	/* We need to check for WRIOP version 1.0.0, but depending on the MC
++	 * version, this number is not always provided correctly on rev1.
++	 * We need to check for both alternatives in this situation.
++	 */
++	if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) ||
++	    priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0))
++		priv->rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1;
++	else
++		priv->rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN;
++
++	/* tx buffer */
++	buf_layout.pass_timestamp = true;
++	buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
++	buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP |
++			     DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE;
++	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
++				     DPNI_QUEUE_TX, &buf_layout);
++	if (err) {
++		dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
++		return err;
++	}
++
++	/* tx-confirm buffer */
++	buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
++	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
++				     DPNI_QUEUE_TX_CONFIRM, &buf_layout);
++	if (err) {
++		dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
++		return err;
++	}
++
++	/* Now that we've set our tx buffer layout, retrieve the minimum
++	 * required tx data offset.
++	 */
++	err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
++				      &priv->tx_data_offset);
++	if (err) {
++		dev_err(dev, "dpni_get_tx_data_offset() failed\n");
++		return err;
++	}
++
++	if ((priv->tx_data_offset % 64) != 0)
++		dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
++			 priv->tx_data_offset);
++
++	/* rx buffer */
++	buf_layout.pass_frame_status = true;
++	buf_layout.pass_parser_result = true;
++	buf_layout.data_align = priv->rx_buf_align;
++	buf_layout.private_data_size = 0;
++	buf_layout.data_head_room = dpaa2_eth_rx_headroom(priv);
++	buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
++			     DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
++			     DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
++			     DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
++			     DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
++	err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
++				     DPNI_QUEUE_RX, &buf_layout);
++	if (err) {
++		dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
++		return err;
++	}
++
++	return 0;
++}
++
++static int dpaa2_eth_set_xdp(struct net_device *net_dev, struct bpf_prog *prog)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct dpaa2_eth_channel *ch;
++	struct bpf_prog *old_prog;
++	int i, err;
++
++	/* No support for SG frames */
++	if (DPAA2_ETH_L2_MAX_FRM(net_dev->mtu) > DPAA2_ETH_RX_BUF_SIZE)
++		return -EINVAL;
++
++	if (netif_running(net_dev)) {
++		err = dpaa2_eth_stop(net_dev);
++		if (err)
++			return err;
++	}
++
++	if (prog) {
++		prog = bpf_prog_add(prog, priv->num_channels - 1);
++		if (IS_ERR(prog))
++			return PTR_ERR(prog);
++	}
++
++	priv->has_xdp_prog = !!prog;
++
++	for (i = 0; i < priv->num_channels; i++) {
++		ch = priv->channel[i];
++		old_prog = xchg(&ch->xdp_prog, prog);
++		if (old_prog)
++			bpf_prog_put(old_prog);
++	}
++
++	if (netif_running(net_dev)) {
++		err = dpaa2_eth_open(net_dev);
++		if (err)
++			return err;
++	}
++
++	return 0;
++}
++
++static int dpaa2_eth_xdp(struct net_device *dev, struct netdev_xdp *xdp)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(dev);
++
++	switch (xdp->command) {
++	case XDP_SETUP_PROG:
++		return dpaa2_eth_set_xdp(dev, xdp->prog);
++	case XDP_QUERY_PROG:
++		xdp->prog_attached = priv->has_xdp_prog;
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++static const struct net_device_ops dpaa2_eth_ops = {
++	.ndo_open = dpaa2_eth_open,
++	.ndo_start_xmit = dpaa2_eth_tx,
++	.ndo_stop = dpaa2_eth_stop,
++	.ndo_init = dpaa2_eth_init,
++	.ndo_set_mac_address = dpaa2_eth_set_addr,
++	.ndo_get_stats64 = dpaa2_eth_get_stats,
++	.ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
++	.ndo_set_features = dpaa2_eth_set_features,
++	.ndo_do_ioctl = dpaa2_eth_ioctl,
++	.ndo_xdp = dpaa2_eth_xdp,
++};
++
++static void cdan_cb(struct dpaa2_io_notification_ctx *ctx)
++{
++	struct dpaa2_eth_channel *ch;
++
++	ch = container_of(ctx, struct dpaa2_eth_channel, nctx);
++
++	/* Update NAPI statistics */
++	ch->stats.cdan++;
++
++	napi_schedule_irqoff(&ch->napi);
++}
++
++/* Allocate and configure a DPCON object */
++static struct fsl_mc_device *setup_dpcon(struct dpaa2_eth_priv *priv)
++{
++	struct fsl_mc_device *dpcon;
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpcon_attr attrs;
++	int err;
++
++	err = fsl_mc_object_allocate(to_fsl_mc_device(dev),
++				     FSL_MC_POOL_DPCON, &dpcon);
++	if (err) {
++		dev_info(dev, "Not enough DPCONs, will go on as-is\n");
++		return NULL;
++	}
++
++	err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
++	if (err) {
++		dev_err(dev, "dpcon_open() failed\n");
++		goto free;
++	}
++
++	err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
++	if (err) {
++		dev_err(dev, "dpcon_reset() failed\n");
++		goto close;
++	}
++
++	err = dpcon_get_attributes(priv->mc_io, 0, dpcon->mc_handle, &attrs);
++	if (err) {
++		dev_err(dev, "dpcon_get_attributes() failed\n");
++		goto close;
++	}
++
++	err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
++	if (err) {
++		dev_err(dev, "dpcon_enable() failed\n");
++		goto close;
++	}
++
++	return dpcon;
++
++close:
++	dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
++free:
++	fsl_mc_object_free(dpcon);
++
++	return NULL;
++}
++
++static void free_dpcon(struct dpaa2_eth_priv *priv,
++		       struct fsl_mc_device *dpcon)
++{
++	dpcon_disable(priv->mc_io, 0, dpcon->mc_handle);
++	dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
++	fsl_mc_object_free(dpcon);
++}
++
++static struct dpaa2_eth_channel *
++alloc_channel(struct dpaa2_eth_priv *priv)
++{
++	struct dpaa2_eth_channel *channel;
++	struct dpcon_attr attr;
++	struct device *dev = priv->net_dev->dev.parent;
++	int err;
++
++	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
++	if (!channel)
++		return NULL;
++
++	channel->dpcon = setup_dpcon(priv);
++	if (!channel->dpcon)
++		goto err_setup;
++
++	err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle,
++				   &attr);
++	if (err) {
++		dev_err(dev, "dpcon_get_attributes() failed\n");
++		goto err_get_attr;
++	}
++
++	channel->dpcon_id = attr.id;
++	channel->ch_id = attr.qbman_ch_id;
++	channel->priv = priv;
++
++	return channel;
++
++err_get_attr:
++	free_dpcon(priv, channel->dpcon);
++err_setup:
++	kfree(channel);
++	return NULL;
++}
++
++static void free_channel(struct dpaa2_eth_priv *priv,
++			 struct dpaa2_eth_channel *channel)
++{
++	struct bpf_prog *prog;
++
++	free_dpcon(priv, channel->dpcon);
++
++	prog = READ_ONCE(channel->xdp_prog);
++	if (prog)
++		bpf_prog_put(prog);
++
++	kfree(channel);
++}
++
++/* DPIO setup: allocate and configure QBMan channels, setup core affinity
++ * and register data availability notifications
++ */
++static int setup_dpio(struct dpaa2_eth_priv *priv)
++{
++	struct dpaa2_io_notification_ctx *nctx;
++	struct dpaa2_eth_channel *channel;
++	struct dpcon_notification_cfg dpcon_notif_cfg;
++	struct device *dev = priv->net_dev->dev.parent;
++	int i, err;
++
++	/* We want the ability to spread ingress traffic (RX, TX conf) to as
++	 * many cores as possible, so we need one channel for each core
++	 * (unless there's fewer queues than cores, in which case the extra
++	 * channels would be wasted).
++	 * Allocate one channel per core and register it to the core's
++	 * affine DPIO. If not enough channels are available for all cores
++	 * or if some cores don't have an affine DPIO, there will be no
++	 * ingress frame processing on those cores.
++	 */
++	cpumask_clear(&priv->dpio_cpumask);
++	for_each_online_cpu(i) {
++		/* Try to allocate a channel */
++		channel = alloc_channel(priv);
++		if (!channel) {
++			dev_info(dev,
++				 "No affine channel for cpu %d and above\n", i);
++			err = -ENODEV;
++			goto err_alloc_ch;
++		}
++
++		priv->channel[priv->num_channels] = channel;
++
++		nctx = &channel->nctx;
++		nctx->is_cdan = 1;
++		nctx->cb = cdan_cb;
++		nctx->id = channel->ch_id;
++		nctx->desired_cpu = i;
++
++		/* Register the new context */
++		channel->dpio = dpaa2_io_service_select(i);
++		err = dpaa2_io_service_register(channel->dpio, nctx);
++		if (err) {
++			dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
++			/* If no affine DPIO for this core, there's probably
++			 * none available for next cores either. Signal we want
++			 * to retry later, in case the DPIO devices weren't
++			 * probed yet.
++			 */
++			err = -EPROBE_DEFER;
++			goto err_service_reg;
++		}
++
++		/* Register DPCON notification with MC */
++		dpcon_notif_cfg.dpio_id = nctx->dpio_id;
++		dpcon_notif_cfg.priority = 0;
++		dpcon_notif_cfg.user_ctx = nctx->qman64;
++		err = dpcon_set_notification(priv->mc_io, 0,
++					     channel->dpcon->mc_handle,
++					     &dpcon_notif_cfg);
++		if (err) {
++			dev_err(dev, "dpcon_set_notification failed()\n");
++			goto err_set_cdan;
++		}
++
++		/* If we managed to allocate a channel and also found an affine
++		 * DPIO for this core, add it to the final mask
++		 */
++		cpumask_set_cpu(i, &priv->dpio_cpumask);
++		priv->num_channels++;
++
++		/* Stop if we already have enough channels to accommodate all
++		 * RX and TX conf queues
++		 */
++		if (priv->num_channels == dpaa2_eth_queue_count(priv))
++			break;
++	}
++
++	return 0;
++
++err_set_cdan:
++	dpaa2_io_service_deregister(channel->dpio, nctx);
++err_service_reg:
++	free_channel(priv, channel);
++err_alloc_ch:
++	if (cpumask_empty(&priv->dpio_cpumask)) {
++		dev_err(dev, "No cpu with an affine DPIO/DPCON\n");
++		return err;
++	}
++
++	dev_info(dev, "Cores %*pbl available for processing ingress traffic\n",
++		 cpumask_pr_args(&priv->dpio_cpumask));
++
++	return 0;
++}
++
++static void free_dpio(struct dpaa2_eth_priv *priv)
++{
++	int i;
++	struct dpaa2_eth_channel *ch;
++
++	/* deregister CDAN notifications and free channels */
++	for (i = 0; i < priv->num_channels; i++) {
++		ch = priv->channel[i];
++		dpaa2_io_service_deregister(ch->dpio, &ch->nctx);
++		free_channel(priv, ch);
++	}
++}
++
++static struct dpaa2_eth_channel *get_affine_channel(struct dpaa2_eth_priv *priv,
++						    int cpu)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	int i;
++
++	for (i = 0; i < priv->num_channels; i++)
++		if (priv->channel[i]->nctx.desired_cpu == cpu)
++			return priv->channel[i];
++
++	/* We should never get here. Issue a warning and return
++	 * the first channel, because it's still better than nothing
++	 */
++	dev_warn(dev, "No affine channel found for cpu %d\n", cpu);
++
++	return priv->channel[0];
++}
++
++static void set_fq_affinity(struct dpaa2_eth_priv *priv)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct cpumask xps_mask;
++	struct dpaa2_eth_fq *fq;
++	int rx_cpu, txc_cpu;
++	int i, err;
++
++	/* For each FQ, pick one channel/CPU to deliver frames to.
++	 * This may well change at runtime, either through irqbalance or
++	 * through direct user intervention.
++	 */
++	rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask);
++
++	for (i = 0; i < priv->num_fqs; i++) {
++		fq = &priv->fq[i];
++		switch (fq->type) {
++		case DPAA2_RX_FQ:
++		case DPAA2_RX_ERR_FQ:
++			fq->target_cpu = rx_cpu;
++			rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
++			if (rx_cpu >= nr_cpu_ids)
++				rx_cpu = cpumask_first(&priv->dpio_cpumask);
++			break;
++		case DPAA2_TX_CONF_FQ:
++			fq->target_cpu = txc_cpu;
++
++			/* Tell the stack to affine to txc_cpu the Tx queue
++			 * associated with the confirmation one
++			 */
++			cpumask_clear(&xps_mask);
++			cpumask_set_cpu(txc_cpu, &xps_mask);
++			err = netif_set_xps_queue(priv->net_dev, &xps_mask,
++						  fq->flowid);
++			if (err)
++				dev_info_once(dev, "Error setting XPS queue\n");
++
++			txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
++			if (txc_cpu >= nr_cpu_ids)
++				txc_cpu = cpumask_first(&priv->dpio_cpumask);
++			break;
++		default:
++			dev_err(dev, "Unknown FQ type: %d\n", fq->type);
++		}
++		fq->channel = get_affine_channel(priv, fq->target_cpu);
++	}
++}
++
++static void setup_fqs(struct dpaa2_eth_priv *priv)
++{
++	int i, j;
++
++	/* We have one TxConf FQ per Tx flow.
++	 * The number of Tx and Rx queues is the same.
++	 * Tx queues come first in the fq array.
++	 */
++	for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
++		priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ;
++		priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf;
++		priv->fq[priv->num_fqs++].flowid = (u16)i;
++	}
++
++	for (i = 0; i < dpaa2_eth_tc_count(priv); i++)
++		for (j = 0; j < dpaa2_eth_queue_count(priv); j++) {
++			priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
++			priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
++			priv->fq[priv->num_fqs].tc = (u8)i;
++			priv->fq[priv->num_fqs++].flowid = (u16)j;
++		}
++
++#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
++	/* We have exactly one Rx error queue per DPNI */
++	priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ;
++	priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err;
++#endif
++
++	/* For each FQ, decide on which core to process incoming frames */
++	set_fq_affinity(priv);
++}
++
++/* Allocate and configure one buffer pool for each interface */
++static int setup_dpbp(struct dpaa2_eth_priv *priv)
++{
++	int err;
++	struct fsl_mc_device *dpbp_dev;
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpbp_attr dpbp_attrs;
++
++	err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP,
++				     &dpbp_dev);
++	if (err) {
++		dev_err(dev, "DPBP device allocation failed\n");
++		return err;
++	}
++
++	priv->dpbp_dev = dpbp_dev;
++
++	err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id,
++			&dpbp_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpbp_open() failed\n");
++		goto err_open;
++	}
++
++	err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpbp_reset() failed\n");
++		goto err_reset;
++	}
++
++	err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpbp_enable() failed\n");
++		goto err_enable;
++	}
++
++	err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle,
++				  &dpbp_attrs);
++	if (err) {
++		dev_err(dev, "dpbp_get_attributes() failed\n");
++		goto err_get_attr;
++	}
++	priv->bpid = dpbp_attrs.bpid;
++
++	/* By default we start with flow control enabled */
++	priv->max_bufs_per_ch = DPAA2_ETH_NUM_BUFS_FC / priv->num_channels;
++
++	return 0;
++
++err_get_attr:
++	dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle);
++err_enable:
++err_reset:
++	dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle);
++err_open:
++	fsl_mc_object_free(dpbp_dev);
++
++	return err;
++}
++
++static void free_dpbp(struct dpaa2_eth_priv *priv)
++{
++	drain_pool(priv);
++	dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
++	dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
++	fsl_mc_object_free(priv->dpbp_dev);
++}
++
++static int setup_tx_congestion(struct dpaa2_eth_priv *priv)
++{
++	struct dpni_congestion_notification_cfg notif_cfg = {0};
++	struct device *dev = priv->net_dev->dev.parent;
++	int err;
++
++	priv->cscn_unaligned = kzalloc(DPAA2_CSCN_SIZE + DPAA2_CSCN_ALIGN,
++				       GFP_KERNEL);
++
++	if (!priv->cscn_unaligned)
++		return -ENOMEM;
++
++	priv->cscn_mem = PTR_ALIGN(priv->cscn_unaligned, DPAA2_CSCN_ALIGN);
++	priv->cscn_dma = dma_map_single(dev, priv->cscn_mem, DPAA2_CSCN_SIZE,
++					DMA_FROM_DEVICE);
++	if (dma_mapping_error(dev, priv->cscn_dma)) {
++		dev_err(dev, "Error mapping CSCN memory area\n");
++		err = -ENOMEM;
++		goto err_dma_map;
++	}
++
++	notif_cfg.units = DPNI_CONGESTION_UNIT_BYTES;
++	notif_cfg.threshold_entry = DPAA2_ETH_TX_CONG_ENTRY_THRESH;
++	notif_cfg.threshold_exit = DPAA2_ETH_TX_CONG_EXIT_THRESH;
++	notif_cfg.message_ctx = (u64)priv;
++	notif_cfg.message_iova = priv->cscn_dma;
++	notif_cfg.notification_mode = DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
++				      DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
++				      DPNI_CONG_OPT_COHERENT_WRITE;
++	err = dpni_set_congestion_notification(priv->mc_io, 0, priv->mc_token,
++					       DPNI_QUEUE_TX, 0, &notif_cfg);
++	if (err) {
++		dev_err(dev, "dpni_set_congestion_notification failed\n");
++		goto err_set_cong;
++	}
++
++	return 0;
++
++err_set_cong:
++	dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
++err_dma_map:
++	kfree(priv->cscn_unaligned);
++
++	return err;
++}
++
++/* Configure the DPNI object this interface is associated with */
++static int setup_dpni(struct fsl_mc_device *ls_dev)
++{
++	struct device *dev = &ls_dev->dev;
++	struct dpaa2_eth_priv *priv;
++	struct net_device *net_dev;
++	struct dpni_link_cfg cfg = {0};
++	int err;
++
++	net_dev = dev_get_drvdata(dev);
++	priv = netdev_priv(net_dev);
++
++	/* get a handle for the DPNI object */
++	err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
++	if (err) {
++		dev_err(dev, "dpni_open() failed\n");
++		return err;
++	}
++
++	/* Check if we can work with this DPNI object */
++	err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major,
++				   &priv->dpni_ver_minor);
++	if (err) {
++		dev_err(dev, "dpni_get_api_version() failed\n");
++		goto close;
++	}
++	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) {
++		dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n",
++			priv->dpni_ver_major, priv->dpni_ver_minor,
++			DPNI_VER_MAJOR, DPNI_VER_MINOR);
++		err = -ENOTSUPP;
++		goto close;
++	}
++
++	ls_dev->mc_io = priv->mc_io;
++	ls_dev->mc_handle = priv->mc_token;
++
++	err = dpni_reset(priv->mc_io, 0, priv->mc_token);
++	if (err) {
++		dev_err(dev, "dpni_reset() failed\n");
++		goto close;
++	}
++
++	err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
++				  &priv->dpni_attrs);
++	if (err) {
++		dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
++		goto close;
++	}
++
++	err = set_buffer_layout(priv);
++	if (err)
++		goto close;
++
++	/* Enable congestion notifications for Tx queues */
++	err = setup_tx_congestion(priv);
++	if (err)
++		goto close;
++
++	/* allocate classification rule space */
++	priv->cls_rule = kzalloc(sizeof(*priv->cls_rule) *
++				 dpaa2_eth_fs_count(priv), GFP_KERNEL);
++	if (!priv->cls_rule)
++		goto close;
++
++	/* Enable flow control */
++	cfg.options = DPNI_LINK_OPT_AUTONEG | DPNI_LINK_OPT_PAUSE;
++	priv->tx_pause_frames = true;
++	err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &cfg);
++	if (err) {
++		dev_err(dev, "dpni_set_link_cfg() failed\n");
++		goto cls_free;
++	}
++
++	return 0;
++
++cls_free:
++	kfree(priv->cls_rule);
++close:
++	dpni_close(priv->mc_io, 0, priv->mc_token);
++
++	return err;
++}
++
++static void free_dpni(struct dpaa2_eth_priv *priv)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	int err;
++
++	err = dpni_reset(priv->mc_io, 0, priv->mc_token);
++	if (err)
++		netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n",
++			    err);
++
++	dpni_close(priv->mc_io, 0, priv->mc_token);
++
++	kfree(priv->cls_rule);
++
++	dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
++	kfree(priv->cscn_unaligned);
++}
++
++static int setup_rx_flow(struct dpaa2_eth_priv *priv,
++			 struct dpaa2_eth_fq *fq)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpni_queue queue;
++	struct dpni_queue_id qid;
++	int err;
++
++	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
++			     DPNI_QUEUE_RX, fq->tc, fq->flowid, &queue, &qid);
++	if (err) {
++		dev_err(dev, "dpni_get_queue(RX) failed\n");
++		return err;
++	}
++
++	fq->fqid = qid.fqid;
++
++	queue.destination.id = fq->channel->dpcon_id;
++	queue.destination.type = DPNI_DEST_DPCON;
++	queue.destination.priority = 1;
++	queue.user_context = (u64)(uintptr_t)fq;
++	err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
++			     DPNI_QUEUE_RX, fq->tc, fq->flowid,
++			     DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
++			     &queue);
++	if (err) {
++		dev_err(dev, "dpni_set_queue(RX) failed\n");
++		return err;
++	}
++
++	return 0;
++}
++
++static int set_queue_taildrop(struct dpaa2_eth_priv *priv,
++			      struct dpni_taildrop *td)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	int i, err;
++
++	for (i = 0; i < priv->num_fqs; i++) {
++		if (priv->fq[i].type != DPAA2_RX_FQ)
++			continue;
++
++		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
++					DPNI_CP_QUEUE, DPNI_QUEUE_RX,
++					priv->fq[i].tc, priv->fq[i].flowid,
++					td);
++		if (err) {
++			dev_err(dev, "dpni_set_taildrop() failed (%d)\n", err);
++			return err;
++		}
++
++		dev_dbg(dev, "%s taildrop for Rx group tc %d\n",
++			(td->enable ? "Enabled" : "Disabled"),
++			i);
++	}
++
++	return 0;
++}
++
++static int set_group_taildrop(struct dpaa2_eth_priv *priv,
++			      struct dpni_taildrop *td)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpni_taildrop disable_td, *tc_td;
++	int i, err;
++
++	memset(&disable_td, 0, sizeof(struct dpni_taildrop));
++	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
++		if (td->enable && dpaa2_eth_is_pfc_enabled(priv, i))
++			/* Do not set taildrop thresholds for PFC-enabled
++			 * traffic classes. We will enable congestion
++			 * notifications for them.
++			 */
++			tc_td = &disable_td;
++		else
++			tc_td = td;
++
++		err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
++					DPNI_CP_GROUP, DPNI_QUEUE_RX,
++					i, 0, tc_td);
++		if (err) {
++			dev_err(dev, "dpni_set_taildrop() failed (%d)\n", err);
++			return err;
++		}
++
++		dev_dbg(dev, "%s taildrop for Rx queue id %d tc %d\n",
++			(tc_td->enable ? "Enabled" : "Disabled"),
++			priv->fq[i].flowid, priv->fq[i].tc);
++	}
++
++	return 0;
++}
++
++/* Enable/disable Rx FQ taildrop
++ *
++ * Rx FQ taildrop is mutually exclusive with flow control and it only gets
++ * disabled when FC is active. Depending on FC status, we need to compute
++ * the maximum number of buffers in the pool differently, so use the
++ * opportunity to update max number of buffers as well.
++ */
++int set_rx_taildrop(struct dpaa2_eth_priv *priv)
++{
++	enum dpaa2_eth_td_cfg cfg = dpaa2_eth_get_td_type(priv);
++	struct dpni_taildrop td_queue, td_group;
++	int err = 0;
++
++	switch (cfg) {
++	case DPAA2_ETH_TD_NONE:
++		memset(&td_queue, 0, sizeof(struct dpni_taildrop));
++		memset(&td_group, 0, sizeof(struct dpni_taildrop));
++		priv->max_bufs_per_ch = DPAA2_ETH_NUM_BUFS_FC /
++					priv->num_channels;
++		break;
++	case DPAA2_ETH_TD_QUEUE:
++		memset(&td_group, 0, sizeof(struct dpni_taildrop));
++		td_queue.enable = 1;
++		td_queue.units = DPNI_CONGESTION_UNIT_BYTES;
++		td_queue.threshold = DPAA2_ETH_TAILDROP_THRESH /
++				     dpaa2_eth_tc_count(priv);
++		priv->max_bufs_per_ch = DPAA2_ETH_NUM_BUFS_PER_CH;
++		break;
++	case DPAA2_ETH_TD_GROUP:
++		memset(&td_queue, 0, sizeof(struct dpni_taildrop));
++		td_group.enable = 1;
++		td_group.units = DPNI_CONGESTION_UNIT_FRAMES;
++		td_group.threshold = NAPI_POLL_WEIGHT *
++				     dpaa2_eth_queue_count(priv);
++		priv->max_bufs_per_ch = NAPI_POLL_WEIGHT *
++					dpaa2_eth_tc_count(priv);
++		break;
++	default:
++		break;
++	}
++
++	err = set_queue_taildrop(priv, &td_queue);
++	if (err)
++		return err;
++
++	err = set_group_taildrop(priv, &td_group);
++	if (err)
++		return err;
++
++	priv->refill_thresh = DPAA2_ETH_REFILL_THRESH(priv);
++
++	return 0;
++}
++
++static int setup_tx_flow(struct dpaa2_eth_priv *priv,
++			 struct dpaa2_eth_fq *fq)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpni_queue queue;
++	struct dpni_queue_id qid;
++	int err;
++
++	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
++			     DPNI_QUEUE_TX, 0, fq->flowid, &queue, &qid);
++	if (err) {
++		dev_err(dev, "dpni_get_queue(TX) failed\n");
++		return err;
++	}
++
++	fq->tx_qdbin = qid.qdbin;
++
++	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
++			     DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
++			     &queue, &qid);
++	if (err) {
++		dev_err(dev, "dpni_get_queue(TX_CONF) failed\n");
++		return err;
++	}
++
++	fq->fqid = qid.fqid;
++
++	queue.destination.id = fq->channel->dpcon_id;
++	queue.destination.type = DPNI_DEST_DPCON;
++	queue.destination.priority = 0;
++	queue.user_context = (u64)(uintptr_t)fq;
++	err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
++			     DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
++			     DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
++			     &queue);
++	if (err) {
++		dev_err(dev, "dpni_set_queue(TX_CONF) failed\n");
++		return err;
++	}
++
++	return 0;
++}
++
++#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
++static int setup_rx_err_flow(struct dpaa2_eth_priv *priv,
++			     struct dpaa2_eth_fq *fq)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpni_queue q = { { 0 } };
++	struct dpni_queue_id qid;
++	u8 q_opt = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST;
++	int err;
++
++	err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
++			     DPNI_QUEUE_RX_ERR, 0, 0, &q, &qid);
++	if (err) {
++		dev_err(dev, "dpni_get_queue() failed (%d)\n", err);
++		return err;
++	}
++
++	fq->fqid = qid.fqid;
++
++	q.destination.id = fq->channel->dpcon_id;
++	q.destination.type = DPNI_DEST_DPCON;
++	q.destination.priority = 1;
++	q.user_context = (u64)fq;
++	err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
++			     DPNI_QUEUE_RX_ERR, 0, 0, q_opt, &q);
++	if (err) {
++		dev_err(dev, "dpni_set_queue() failed (%d)\n", err);
++		return err;
++	}
++
++	return 0;
++}
++#endif
++
++/* default hash key fields */
++static struct dpaa2_eth_dist_fields default_dist_fields[] = {
++	{
++		/* L2 header */
++		.rxnfc_field = RXH_L2DA,
++		.cls_prot = NET_PROT_ETH,
++		.cls_field = NH_FLD_ETH_DA,
++		.id = DPAA2_ETH_DIST_ETHDST,
++		.size = 6,
++	}, {
++		.cls_prot = NET_PROT_ETH,
++		.cls_field = NH_FLD_ETH_SA,
++		.id = DPAA2_ETH_DIST_ETHSRC,
++		.size = 6,
++	}, {
++		/* This is the last ethertype field parsed:
++		 * depending on frame format, it can be the MAC ethertype
++		 * or the VLAN etype.
++		 */
++		.cls_prot = NET_PROT_ETH,
++		.cls_field = NH_FLD_ETH_TYPE,
++		.id = DPAA2_ETH_DIST_ETHTYPE,
++		.size = 2,
++	}, {
++		/* VLAN header */
++		.rxnfc_field = RXH_VLAN,
++		.cls_prot = NET_PROT_VLAN,
++		.cls_field = NH_FLD_VLAN_TCI,
++		.id = DPAA2_ETH_DIST_VLAN,
++		.size = 2,
++	}, {
++		/* IP header */
++		.rxnfc_field = RXH_IP_SRC,
++		.cls_prot = NET_PROT_IP,
++		.cls_field = NH_FLD_IP_SRC,
++		.id = DPAA2_ETH_DIST_IPSRC,
++		.size = 4,
++	}, {
++		.rxnfc_field = RXH_IP_DST,
++		.cls_prot = NET_PROT_IP,
++		.cls_field = NH_FLD_IP_DST,
++		.id = DPAA2_ETH_DIST_IPDST,
++		.size = 4,
++	}, {
++		.rxnfc_field = RXH_L3_PROTO,
++		.cls_prot = NET_PROT_IP,
++		.cls_field = NH_FLD_IP_PROTO,
++		.id = DPAA2_ETH_DIST_IPPROTO,
++		.size = 1,
++	}, {
++		/* Using UDP ports, this is functionally equivalent to raw
++		 * byte pairs from L4 header.
++		 */
++		.rxnfc_field = RXH_L4_B_0_1,
++		.cls_prot = NET_PROT_UDP,
++		.cls_field = NH_FLD_UDP_PORT_SRC,
++		.id = DPAA2_ETH_DIST_L4SRC,
++		.size = 2,
++	}, {
++		.rxnfc_field = RXH_L4_B_2_3,
++		.cls_prot = NET_PROT_UDP,
++		.cls_field = NH_FLD_UDP_PORT_DST,
++		.id = DPAA2_ETH_DIST_L4DST,
++		.size = 2,
++	},
++};
++
++static int legacy_config_dist_key(struct dpaa2_eth_priv *priv,
++				  dma_addr_t key_iova)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpni_rx_tc_dist_cfg dist_cfg;
++	int i, err;
++
++	/* In legacy mode, we can't configure flow steering independently */
++	if (!dpaa2_eth_hash_enabled(priv))
++		return -EOPNOTSUPP;
++
++	memset(&dist_cfg, 0, sizeof(dist_cfg));
++
++	dist_cfg.key_cfg_iova = key_iova;
++	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
++	if (dpaa2_eth_fs_enabled(priv)) {
++		dist_cfg.dist_mode = DPNI_DIST_MODE_FS;
++		dist_cfg.fs_cfg.miss_action = DPNI_FS_MISS_HASH;
++	} else {
++		dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
++	}
++
++	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
++		err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token, i,
++					  &dist_cfg);
++		if (err) {
++			dev_err(dev, "dpni_set_rx_tc_dist failed\n");
++			return err;
++		}
++	}
++
++	return 0;
++}
++
++static int config_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key_iova)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpni_rx_dist_cfg dist_cfg;
++	int i, err;
++
++	if (!dpaa2_eth_hash_enabled(priv))
++		return -EOPNOTSUPP;
++
++	memset(&dist_cfg, 0, sizeof(dist_cfg));
++
++	dist_cfg.key_cfg_iova = key_iova;
++	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
++	dist_cfg.enable = true;
++
++	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
++		dist_cfg.tc = i;
++
++		err = dpni_set_rx_hash_dist(priv->mc_io, 0,
++					    priv->mc_token, &dist_cfg);
++		if (err) {
++			dev_err(dev, "dpni_set_rx_hash_dist failed\n");
++			return err;
++		}
++	}
++
++	return 0;
++}
++
++static int config_fs_key(struct dpaa2_eth_priv *priv, dma_addr_t key_iova)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpni_rx_dist_cfg dist_cfg;
++	int i, err;
++
++	if (!dpaa2_eth_fs_enabled(priv))
++		return -EOPNOTSUPP;
++
++	memset(&dist_cfg, 0, sizeof(dist_cfg));
++
++	dist_cfg.key_cfg_iova = key_iova;
++	dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
++	dist_cfg.enable = true;
++
++	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
++		dist_cfg.tc = i;
++
++		err = dpni_set_rx_fs_dist(priv->mc_io, 0,
++					  priv->mc_token, &dist_cfg);
++		if (err) {
++			dev_err(dev, "dpni_set_rx_fs_dist failed\n");
++			return err;
++		}
++	}
++
++	return 0;
++}
++
++int dpaa2_eth_set_dist_key(struct dpaa2_eth_priv *priv,
++			   enum dpaa2_eth_rx_dist type, u32 key_fields)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpkg_profile_cfg cls_cfg;
++	struct dpkg_extract *key;
++	u32 hash_fields = 0;
++	dma_addr_t key_iova;
++	u8 *key_mem;
++	int i, err;
++
++	memset(&cls_cfg, 0, sizeof(cls_cfg));
++
++	for (i = 0; i < priv->num_dist_fields; i++) {
++		if (!(key_fields & priv->dist_fields[i].id))
++			continue;
++
++		key = &cls_cfg.extracts[cls_cfg.num_extracts];
++		key->type = DPKG_EXTRACT_FROM_HDR;
++		key->extract.from_hdr.prot = priv->dist_fields[i].cls_prot;
++		key->extract.from_hdr.type = DPKG_FULL_FIELD;
++		key->extract.from_hdr.field = priv->dist_fields[i].cls_field;
++		cls_cfg.num_extracts++;
++
++		hash_fields |= priv->dist_fields[i].rxnfc_field;
++	}
++
++	key_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
++	if (!key_mem)
++		return -ENOMEM;
++
++	err = dpni_prepare_key_cfg(&cls_cfg, key_mem);
++	if (err) {
++		dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
++		goto free_key;
++	}
++
++	key_iova = dma_map_single(dev, key_mem, DPAA2_CLASSIFIER_DMA_SIZE,
++				  DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, key_iova)) {
++		dev_err(dev, "DMA mapping failed\n");
++		err = -ENOMEM;
++		goto free_key;
++	}
++
++	switch (type) {
++	case DPAA2_ETH_RX_DIST_LEGACY:
++		err = legacy_config_dist_key(priv, key_iova);
++		break;
++	case DPAA2_ETH_RX_DIST_HASH:
++		err = config_hash_key(priv, key_iova);
++		break;
++	case DPAA2_ETH_RX_DIST_FS:
++		err = config_fs_key(priv, key_iova);
++		break;
++	default:
++		err = -EINVAL;
++		break;
++	}
++
++	dma_unmap_single(dev, key_iova, DPAA2_CLASSIFIER_DMA_SIZE,
++			 DMA_TO_DEVICE);
++	if (err) {
++		if (err != -EOPNOTSUPP)
++			dev_err(dev, "Distribution key config failed\n");
++		goto free_key;
++	}
++
++	if (type != DPAA2_ETH_RX_DIST_FS)
++		priv->rx_hash_fields = hash_fields;
++
++free_key:
++	kfree(key_mem);
++	return err;
++}
++
++/* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs,
++ * frame queues and channels
++ */
++static int bind_dpni(struct dpaa2_eth_priv *priv)
++{
++	struct net_device *net_dev = priv->net_dev;
++	struct device *dev = net_dev->dev.parent;
++	struct dpni_pools_cfg pools_params;
++	struct dpni_error_cfg err_cfg;
++	int err = 0;
++	int i;
++
++	pools_params.num_dpbp = 1;
++	pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id;
++	pools_params.pools[0].backup_pool = 0;
++	pools_params.pools[0].priority_mask = 0xff;
++	pools_params.pools[0].buffer_size = DPAA2_ETH_RX_BUF_SIZE;
++	err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
++	if (err) {
++		dev_err(dev, "dpni_set_pools() failed\n");
++		return err;
++	}
++
++	/* Verify classification options and disable hashing and/or
++	 * flow steering support in case of invalid configuration values
++	 */
++	priv->dist_fields = default_dist_fields;
++	priv->num_dist_fields = ARRAY_SIZE(default_dist_fields);
++	check_cls_support(priv);
++
++	/* have the interface implicitly distribute traffic based on
++	 * a static hash key. Also configure flow steering key, if supported.
++	 * Errors here are not blocking, so just let the called function
++	 * print its error message and move along.
++	 */
++	if (dpaa2_eth_has_legacy_dist(priv)) {
++		dpaa2_eth_set_dist_key(priv, DPAA2_ETH_RX_DIST_LEGACY,
++				       DPAA2_ETH_DIST_ALL);
++	} else {
++		dpaa2_eth_set_dist_key(priv, DPAA2_ETH_RX_DIST_HASH,
++				       DPAA2_ETH_DIST_DEFAULT_HASH);
++		dpaa2_eth_set_dist_key(priv, DPAA2_ETH_RX_DIST_FS,
++				       DPAA2_ETH_DIST_ALL);
++	}
++
++	/* Configure handling of error frames */
++	err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
++	err_cfg.set_frame_annotation = 1;
++#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
++	err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
++#else
++	err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
++#endif
++	err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
++				       &err_cfg);
++	if (err) {
++		dev_err(dev, "dpni_set_errors_behavior failed\n");
++		return err;
++	}
++
++	/* Configure Rx and Tx conf queues to generate CDANs */
++	for (i = 0; i < priv->num_fqs; i++) {
++		switch (priv->fq[i].type) {
++		case DPAA2_RX_FQ:
++			err = setup_rx_flow(priv, &priv->fq[i]);
++			break;
++		case DPAA2_TX_CONF_FQ:
++			err = setup_tx_flow(priv, &priv->fq[i]);
++			break;
++#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
++		case DPAA2_RX_ERR_FQ:
++			err = setup_rx_err_flow(priv, &priv->fq[i]);
++			break;
++#endif
++		default:
++			dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
++			return -EINVAL;
++		}
++		if (err)
++			return err;
++	}
++
++	err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token,
++			    DPNI_QUEUE_TX, &priv->tx_qdid);
++	if (err) {
++		dev_err(dev, "dpni_get_qdid() failed\n");
++		return err;
++	}
++
++	return 0;
++}
++
++/* Allocate rings for storing incoming frame descriptors */
++static int alloc_rings(struct dpaa2_eth_priv *priv)
++{
++	struct net_device *net_dev = priv->net_dev;
++	struct device *dev = net_dev->dev.parent;
++	int i;
++
++	for (i = 0; i < priv->num_channels; i++) {
++		priv->channel[i]->store =
++			dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev);
++		if (!priv->channel[i]->store) {
++			netdev_err(net_dev, "dpaa2_io_store_create() failed\n");
++			goto err_ring;
++		}
++	}
++
++	return 0;
++
++err_ring:
++	for (i = 0; i < priv->num_channels; i++) {
++		if (!priv->channel[i]->store)
++			break;
++		dpaa2_io_store_destroy(priv->channel[i]->store);
++	}
++
++	return -ENOMEM;
++}
++
++static void free_rings(struct dpaa2_eth_priv *priv)
++{
++	int i;
++
++	for (i = 0; i < priv->num_channels; i++)
++		dpaa2_io_store_destroy(priv->channel[i]->store);
++}
++
++static int set_mac_addr(struct dpaa2_eth_priv *priv)
++{
++	struct net_device *net_dev = priv->net_dev;
++	struct device *dev = net_dev->dev.parent;
++	u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN];
++	int err;
++
++	/* Get firmware address, if any */
++	err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr);
++	if (err) {
++		dev_err(dev, "dpni_get_port_mac_addr() failed\n");
++		return err;
++	}
++
++	/* Get DPNI attributes address, if any */
++	err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
++					dpni_mac_addr);
++	if (err) {
++		dev_err(dev, "dpni_get_primary_mac_addr() failed\n");
++		return err;
++	}
++
++	/* First check if firmware has any address configured by bootloader */
++	if (!is_zero_ether_addr(mac_addr)) {
++		/* If the DPMAC addr != DPNI addr, update it */
++		if (!ether_addr_equal(mac_addr, dpni_mac_addr)) {
++			err = dpni_set_primary_mac_addr(priv->mc_io, 0,
++							priv->mc_token,
++							mac_addr);
++			if (err) {
++				dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
++				return err;
++			}
++		}
++		memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
++	} else if (is_zero_ether_addr(dpni_mac_addr)) {
++		/* No MAC address configured, fill in net_dev->dev_addr
++		 * with a random one
++		 */
++		eth_hw_addr_random(net_dev);
++		dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n");
++
++		err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
++						net_dev->dev_addr);
++		if (err) {
++			dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
++			return err;
++		}
++
++		/* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all
++		 * practical purposes, this will be our "permanent" mac address,
++		 * at least until the next reboot. This move will also permit
++		 * register_netdevice() to properly fill up net_dev->perm_addr.
++		 */
++		net_dev->addr_assign_type = NET_ADDR_PERM;
++	} else {
++		/* NET_ADDR_PERM is default, all we have to do is
++		 * fill in the device addr.
++		 */
++		memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len);
++	}
++
++	return 0;
++}
++
++static int netdev_init(struct net_device *net_dev)
++{
++	struct device *dev = net_dev->dev.parent;
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	u8 bcast_addr[ETH_ALEN];
++	u8 num_queues;
++	int err;
++
++	net_dev->netdev_ops = &dpaa2_eth_ops;
++
++	err = set_mac_addr(priv);
++	if (err)
++		return err;
++
++	/* Explicitly add the broadcast address to the MAC filtering table */
++	eth_broadcast_addr(bcast_addr);
++	err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr);
++	if (err) {
++		dev_err(dev, "dpni_add_mac_addr() failed\n");
++		return err;
++	}
++
++	/* Set MTU upper limit; lower limit is default (68B) */
++	net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
++	err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
++					(u16)DPAA2_ETH_MFL);
++	if (err) {
++		dev_err(dev, "dpni_set_max_frame_length() failed\n");
++		return err;
++	}
++
++	/* Set actual number of queues in the net device */
++	num_queues = dpaa2_eth_queue_count(priv);
++	err = netif_set_real_num_tx_queues(net_dev, num_queues);
++	if (err) {
++		dev_err(dev, "netif_set_real_num_tx_queues() failed\n");
++		return err;
++	}
++	err = netif_set_real_num_rx_queues(net_dev, num_queues);
++	if (err) {
++		dev_err(dev, "netif_set_real_num_rx_queues() failed\n");
++		return err;
++	}
++
++	/* Our .ndo_init will be called herein */
++	err = register_netdev(net_dev);
++	if (err < 0) {
++		dev_err(dev, "register_netdev() failed\n");
++		return err;
++	}
++
++	return 0;
++}
++
++static int poll_link_state(void *arg)
++{
++	struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg;
++	int err;
++
++	while (!kthread_should_stop()) {
++		err = link_state_update(priv);
++		if (unlikely(err))
++			return err;
++
++		msleep(DPAA2_ETH_LINK_STATE_REFRESH);
++	}
++
++	return 0;
++}
++
++static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
++{
++	u32 status = ~0;
++	struct device *dev = (struct device *)arg;
++	struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
++	struct net_device *net_dev = dev_get_drvdata(dev);
++	int err;
++
++	err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
++				  DPNI_IRQ_INDEX, &status);
++	if (unlikely(err)) {
++		netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
++		return IRQ_HANDLED;
++	}
++
++	if (status & DPNI_IRQ_EVENT_LINK_CHANGED)
++		link_state_update(netdev_priv(net_dev));
++
++	return IRQ_HANDLED;
++}
++
++static int setup_irqs(struct fsl_mc_device *ls_dev)
++{
++	int err = 0;
++	struct fsl_mc_device_irq *irq;
++
++	err = fsl_mc_allocate_irqs(ls_dev);
++	if (err) {
++		dev_err(&ls_dev->dev, "MC irqs allocation failed\n");
++		return err;
++	}
++
++	irq = ls_dev->irqs[0];
++	err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq,
++					NULL, dpni_irq0_handler_thread,
++					IRQF_NO_SUSPEND | IRQF_ONESHOT,
++					dev_name(&ls_dev->dev), &ls_dev->dev);
++	if (err < 0) {
++		dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err);
++		goto free_mc_irq;
++	}
++
++	err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle,
++				DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED);
++	if (err < 0) {
++		dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err);
++		goto free_irq;
++	}
++
++	err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle,
++				  DPNI_IRQ_INDEX, 1);
++	if (err < 0) {
++		dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err);
++		goto free_irq;
++	}
++
++	return 0;
++
++free_irq:
++	devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev);
++free_mc_irq:
++	fsl_mc_free_irqs(ls_dev);
++
++	return err;
++}
++
++static void add_ch_napi(struct dpaa2_eth_priv *priv)
++{
++	int i;
++	struct dpaa2_eth_channel *ch;
++
++	for (i = 0; i < priv->num_channels; i++) {
++		ch = priv->channel[i];
++		/* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */
++		netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll,
++			       NAPI_POLL_WEIGHT);
++	}
++}
++
++static void del_ch_napi(struct dpaa2_eth_priv *priv)
++{
++	int i;
++	struct dpaa2_eth_channel *ch;
++
++	for (i = 0; i < priv->num_channels; i++) {
++		ch = priv->channel[i];
++		netif_napi_del(&ch->napi);
++	}
++}
++
++/* SysFS support */
++static ssize_t dpaa2_eth_show_tx_shaping(struct device *dev,
++					 struct device_attribute *attr,
++					 char *buf)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(to_net_dev(dev));
++	/* No MC API for getting the shaping config. We're stateful. */
++	struct dpni_tx_shaping_cfg *scfg = &priv->shaping_cfg;
++
++	return sprintf(buf, "%u %hu\n", scfg->rate_limit, scfg->max_burst_size);
++}
++
++static ssize_t dpaa2_eth_write_tx_shaping(struct device *dev,
++					  struct device_attribute *attr,
++					  const char *buf,
++					  size_t count)
++{
++	int err, items;
++	struct dpaa2_eth_priv *priv = netdev_priv(to_net_dev(dev));
++	struct dpni_tx_shaping_cfg scfg, ercfg = { 0 };
++
++	items = sscanf(buf, "%u %hu", &scfg.rate_limit, &scfg.max_burst_size);
++	if (items != 2) {
++		pr_err("Expected format: \"rate_limit(Mbps) max_burst_size(bytes)\"\n");
++		return -EINVAL;
++	}
++	/* Size restriction as per MC API documentation */
++	if (scfg.max_burst_size > DPAA2_ETH_MAX_BURST_SIZE) {
++		pr_err("max_burst_size must be <= %d\n",
++		       DPAA2_ETH_MAX_BURST_SIZE);
++		return -EINVAL;
++	}
++
++	err = dpni_set_tx_shaping(priv->mc_io, 0, priv->mc_token, &scfg,
++				  &ercfg, 0);
++	if (err) {
++		dev_err(dev, "dpni_set_tx_shaping() failed\n");
++		return -EPERM;
++	}
++	/* If successful, save the current configuration for future inquiries */
++	priv->shaping_cfg = scfg;
++
++	return count;
++}
++
++static struct device_attribute dpaa2_eth_attrs[] = {
++	__ATTR(tx_shaping,
++	       0600,
++	       dpaa2_eth_show_tx_shaping,
++	       dpaa2_eth_write_tx_shaping),
++};
++
++static void dpaa2_eth_sysfs_init(struct device *dev)
++{
++	int i, err;
++
++	for (i = 0; i < ARRAY_SIZE(dpaa2_eth_attrs); i++) {
++		err = device_create_file(dev, &dpaa2_eth_attrs[i]);
++		if (err) {
++			dev_err(dev, "ERROR creating sysfs file\n");
++			goto undo;
++		}
++	}
++	return;
++
++undo:
++	while (i > 0)
++		device_remove_file(dev, &dpaa2_eth_attrs[--i]);
++}
++
++static void dpaa2_eth_sysfs_remove(struct device *dev)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dpaa2_eth_attrs); i++)
++		device_remove_file(dev, &dpaa2_eth_attrs[i]);
++}
++
++#ifdef CONFIG_FSL_DPAA2_ETH_DCB
++static int dpaa2_eth_dcbnl_ieee_getpfc(struct net_device *net_dev,
++				       struct ieee_pfc *pfc)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct dpni_congestion_notification_cfg notification_cfg;
++	struct dpni_link_state state;
++	int err, i;
++
++	priv->pfc.pfc_cap = dpaa2_eth_tc_count(priv);
++
++	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
++	if (err) {
++		netdev_err(net_dev, "ERROR %d getting link state", err);
++		return err;
++	}
++
++	if (!(state.options & DPNI_LINK_OPT_PFC_PAUSE))
++		return 0;
++
++	priv->pfc.pfc_en = 0;
++	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
++		err = dpni_get_congestion_notification(priv->mc_io, 0,
++						       priv->mc_token,
++						       DPNI_QUEUE_RX,
++						       i, &notification_cfg);
++		if (err) {
++			netdev_err(net_dev, "Error %d getting congestion notif",
++				   err);
++			return err;
++		}
++
++		if (notification_cfg.threshold_entry)
++			priv->pfc.pfc_en |= 1 << i;
++	}
++
++	memcpy(pfc, &priv->pfc, sizeof(priv->pfc));
++
++	return 0;
++}
++
++/* Configure ingress classification based on VLAN PCP */
++static int set_vlan_qos(struct dpaa2_eth_priv *priv)
++{
++	struct device *dev = priv->net_dev->dev.parent;
++	struct dpkg_profile_cfg kg_cfg = {0};
++	struct dpni_qos_tbl_cfg qos_cfg = {0};
++	struct dpni_rule_cfg key_params;
++	u8 *params_iova, *key, *mask = NULL;
++	/* We only need the trailing 16 bits, without the TPID */
++	u8 key_size = VLAN_HLEN / 2;
++	int err = 0, i, j = 0;
++
++	if (priv->vlan_clsf_set)
++		return 0;
++
++	params_iova = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
++	if (!params_iova)
++		return -ENOMEM;
++
++	kg_cfg.num_extracts = 1;
++	kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_HDR;
++	kg_cfg.extracts[0].extract.from_hdr.prot = NET_PROT_VLAN;
++	kg_cfg.extracts[0].extract.from_hdr.type = DPKG_FULL_FIELD;
++	kg_cfg.extracts[0].extract.from_hdr.field = NH_FLD_VLAN_TCI;
++
++	err = dpni_prepare_key_cfg(&kg_cfg, params_iova);
++	if (err) {
++		dev_err(dev, "dpkg_prepare_key_cfg failed: %d\n", err);
++		goto out_free;
++	}
++
++	/* Set QoS table */
++	qos_cfg.default_tc = 0;
++	qos_cfg.discard_on_miss = 0;
++	qos_cfg.key_cfg_iova = dma_map_single(dev, params_iova,
++					      DPAA2_CLASSIFIER_DMA_SIZE,
++					      DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, qos_cfg.key_cfg_iova)) {
++		dev_err(dev, "%s: DMA mapping failed\n", __func__);
++		err = -ENOMEM;
++		goto out_free;
++	}
++	err = dpni_set_qos_table(priv->mc_io, 0, priv->mc_token, &qos_cfg);
++	dma_unmap_single(dev, qos_cfg.key_cfg_iova,
++			 DPAA2_CLASSIFIER_DMA_SIZE, DMA_TO_DEVICE);
++
++	if (err) {
++		dev_err(dev, "dpni_set_qos_table failed: %d\n", err);
++		goto out_free;
++	}
++
++	key_params.key_size = key_size;
++
++	if (dpaa2_eth_fs_mask_enabled(priv)) {
++		mask = kzalloc(key_size, GFP_KERNEL);
++		if (!mask)
++			goto out_free;
++
++		*mask = cpu_to_be16(VLAN_PRIO_MASK);
++
++		key_params.mask_iova = dma_map_single(dev, mask, key_size,
++						      DMA_TO_DEVICE);
++		if (dma_mapping_error(dev, key_params.mask_iova)) {
++			dev_err(dev, "DMA mapping failed %s\n", __func__);
++			err = -ENOMEM;
++			goto out_free_mask;
++		}
++	} else {
++		key_params.mask_iova = 0;
++	}
++
++	key = kzalloc(key_size, GFP_KERNEL);
++	if (!key)
++		goto out_cleanup_mask;
++
++	key_params.key_iova = dma_map_single(dev, key, key_size,
++					     DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, key_params.key_iova)) {
++		dev_err(dev, "%s: DMA mapping failed\n", __func__);
++		err = -ENOMEM;
++		goto out_free_key;
++	}
++
++	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
++		*key = cpu_to_be16(i << VLAN_PRIO_SHIFT);
++
++		dma_sync_single_for_device(dev, key_params.key_iova,
++					   key_size, DMA_TO_DEVICE);
++
++		err = dpni_add_qos_entry(priv->mc_io, 0, priv->mc_token,
++					 &key_params, i, j++);
++		if (err) {
++			dev_err(dev, "dpni_add_qos_entry failed: %d\n", err);
++			goto out_remove;
++		}
++	}
++
++	priv->vlan_clsf_set = true;
++	dev_dbg(dev, "Vlan PCP QoS classification set\n");
++	goto out_cleanup;
++
++out_remove:
++	for (j = 0; j < i; j++) {
++		*key = cpu_to_be16(j << VLAN_PRIO_SHIFT);
++
++		dma_sync_single_for_device(dev, key_params.key_iova, key_size,
++					   DMA_TO_DEVICE);
++
++		err = dpni_remove_qos_entry(priv->mc_io, 0, priv->mc_token,
++					    &key_params);
++		if (err)
++			dev_err(dev, "dpni_remove_qos_entry failed: %d\n", err);
++	}
++
++out_cleanup:
++	dma_unmap_single(dev, key_params.key_iova, key_size, DMA_TO_DEVICE);
++out_free_key:
++	kfree(key);
++out_cleanup_mask:
++	if (key_params.mask_iova)
++		dma_unmap_single(dev, key_params.mask_iova, key_size,
++				 DMA_TO_DEVICE);
++out_free_mask:
++	kfree(mask);
++out_free:
++	kfree(params_iova);
++	return err;
++}
++
++static int dpaa2_eth_dcbnl_ieee_setpfc(struct net_device *net_dev,
++				       struct ieee_pfc *pfc)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct dpni_congestion_notification_cfg notification_cfg = {0};
++	struct dpni_link_state state = {0};
++	struct dpni_link_cfg cfg = {0};
++	struct ieee_pfc old_pfc;
++	int err = 0, i;
++
++	if (dpaa2_eth_tc_count(priv) == 1) {
++		netdev_dbg(net_dev, "DPNI has 1 TC, PFC configuration N/A\n");
++		return 0;
++	}
++
++	/* Zero out pfc_enabled prios greater than tc_count */
++	pfc->pfc_en &= (1 << dpaa2_eth_tc_count(priv)) - 1;
++
++	if (priv->pfc.pfc_en == pfc->pfc_en)
++		/* Same enabled mask, nothing to be done */
++		return 0;
++
++	err = set_vlan_qos(priv);
++	if (err)
++		return err;
++
++	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
++	if (err) {
++		netdev_err(net_dev, "ERROR %d getting link state", err);
++		return err;
++	}
++
++	cfg.rate = state.rate;
++	cfg.options = state.options;
++	if (pfc->pfc_en)
++		cfg.options |= DPNI_LINK_OPT_PFC_PAUSE;
++	else
++		cfg.options &= ~DPNI_LINK_OPT_PFC_PAUSE;
++
++	err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &cfg);
++	if (err) {
++		netdev_err(net_dev, "ERROR %d setting link cfg", err);
++		return err;
++	}
++
++	memcpy(&old_pfc, &priv->pfc, sizeof(priv->pfc));
++	memcpy(&priv->pfc, pfc, sizeof(priv->pfc));
++
++	err = set_rx_taildrop(priv);
++	if (err)
++		goto out_restore_config;
++
++	/* configure congestion notifications */
++	notification_cfg.notification_mode = DPNI_CONG_OPT_FLOW_CONTROL;
++	notification_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
++	notification_cfg.message_iova = 0ULL;
++	notification_cfg.message_ctx = 0ULL;
++
++	for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
++		if (dpaa2_eth_is_pfc_enabled(priv, i)) {
++			notification_cfg.threshold_entry = NAPI_POLL_WEIGHT;
++			notification_cfg.threshold_exit = NAPI_POLL_WEIGHT / 2;
++		} else {
++			notification_cfg.threshold_entry = 0;
++			notification_cfg.threshold_exit = 0;
++		}
++
++		err = dpni_set_congestion_notification(priv->mc_io, 0,
++						       priv->mc_token,
++						       DPNI_QUEUE_RX,
++						       i, &notification_cfg);
++		if (err) {
++			netdev_err(net_dev, "Error %d setting congestion notif",
++				   err);
++			goto out_restore_config;
++		}
++
++		netdev_dbg(net_dev, "%s congestion notifications for tc %d\n",
++			   (notification_cfg.threshold_entry ?
++			    "Enabled" : "Disabled"), i);
++	}
++
++	return 0;
++
++out_restore_config:
++	memcpy(&priv->pfc, &old_pfc, sizeof(priv->pfc));
++	return err;
++}
++
++static u8 dpaa2_eth_dcbnl_getdcbx(struct net_device *net_dev)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++
++	return priv->dcbx_mode;
++}
++
++static u8 dpaa2_eth_dcbnl_setdcbx(struct net_device *net_dev, u8 mode)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++
++	priv->dcbx_mode = mode;
++	return 0;
++}
++
++static u8 dpaa2_eth_dcbnl_getcap(struct net_device *net_dev, int capid, u8 *cap)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++
++	switch (capid) {
++	case DCB_CAP_ATTR_PFC:
++		*cap = true;
++		break;
++	case DCB_CAP_ATTR_PFC_TCS:
++		/* bitmap where each bit represents a number of traffic
++		 * classes the device can be configured to use for Priority
++		 * Flow Control
++		 */
++		*cap = 1 << (dpaa2_eth_tc_count(priv) - 1);
++		break;
++	case DCB_CAP_ATTR_DCBX:
++		*cap = priv->dcbx_mode;
++		break;
++	default:
++		*cap = false;
++		break;
++	}
++
++	return 0;
++}
++
++const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops = {
++	.ieee_getpfc	= dpaa2_eth_dcbnl_ieee_getpfc,
++	.ieee_setpfc	= dpaa2_eth_dcbnl_ieee_setpfc,
++	.getdcbx	= dpaa2_eth_dcbnl_getdcbx,
++	.setdcbx	= dpaa2_eth_dcbnl_setdcbx,
++	.getcap		= dpaa2_eth_dcbnl_getcap,
++};
++#endif
++
++static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
++{
++	struct device *dev;
++	struct net_device *net_dev = NULL;
++	struct dpaa2_eth_priv *priv = NULL;
++	int err = 0;
++
++	dev = &dpni_dev->dev;
++
++	/* Net device */
++	net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_TX_QUEUES);
++	if (!net_dev) {
++		dev_err(dev, "alloc_etherdev_mq() failed\n");
++		return -ENOMEM;
++	}
++
++	SET_NETDEV_DEV(net_dev, dev);
++	dev_set_drvdata(dev, net_dev);
++
++	priv = netdev_priv(net_dev);
++	priv->net_dev = net_dev;
++
++	priv->iommu_domain = iommu_get_domain_for_dev(dev);
++
++	/* Obtain a MC portal */
++	err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
++				     &priv->mc_io);
++	if (err) {
++		if (err == -ENXIO)
++			err = -EPROBE_DEFER;
++		else
++			dev_err(dev, "MC portal allocation failed\n");
++		goto err_portal_alloc;
++	}
++
++	/* MC objects initialization and configuration */
++	err = setup_dpni(dpni_dev);
++	if (err)
++		goto err_dpni_setup;
++
++	err = setup_dpio(priv);
++	if (err)
++		goto err_dpio_setup;
++
++	setup_fqs(priv);
++
++	err = setup_dpbp(priv);
++	if (err)
++		goto err_dpbp_setup;
++
++	err = bind_dpni(priv);
++	if (err)
++		goto err_bind;
++
++	/* Percpu statistics */
++	priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
++	if (!priv->percpu_stats) {
++		dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
++		err = -ENOMEM;
++		goto err_alloc_percpu_stats;
++	}
++	priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
++	if (!priv->percpu_extras) {
++		dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
++		err = -ENOMEM;
++		goto err_alloc_percpu_extras;
++	}
++
++	err = netdev_init(net_dev);
++	if (err)
++		goto err_netdev_init;
++
++	/* Configure checksum offload based on current interface flags */
++	err = set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
++	if (err)
++		goto err_csum;
++
++	err = set_tx_csum(priv, !!(net_dev->features &
++				   (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
++	if (err)
++		goto err_csum;
++
++	err = alloc_rings(priv);
++	if (err)
++		goto err_alloc_rings;
++
++	net_dev->ethtool_ops = &dpaa2_ethtool_ops;
++#ifdef CONFIG_FSL_DPAA2_ETH_DCB
++	net_dev->dcbnl_ops = &dpaa2_eth_dcbnl_ops;
++	priv->dcbx_mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
++#endif
++
++	/* Add a NAPI context for each channel */
++	add_ch_napi(priv);
++	enable_ch_napi(priv);
++
++	err = setup_irqs(dpni_dev);
++	if (err) {
++		netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n");
++		priv->poll_thread = kthread_run(poll_link_state, priv,
++						"%s_poll_link", net_dev->name);
++		if (IS_ERR(priv->poll_thread)) {
++			netdev_err(net_dev, "Error starting polling thread\n");
++			goto err_poll_thread;
++		}
++		priv->do_link_poll = true;
++	}
++
++	dpaa2_eth_sysfs_init(&net_dev->dev);
++#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS
++	dpaa2_dbg_add(priv);
++#endif
++
++	dev_info(dev, "Probed interface %s\n", net_dev->name);
++	return 0;
++
++err_poll_thread:
++	free_rings(priv);
++err_alloc_rings:
++err_csum:
++	unregister_netdev(net_dev);
++err_netdev_init:
++	free_percpu(priv->percpu_extras);
++err_alloc_percpu_extras:
++	free_percpu(priv->percpu_stats);
++err_alloc_percpu_stats:
++	disable_ch_napi(priv);
++	del_ch_napi(priv);
++err_bind:
++	free_dpbp(priv);
++err_dpbp_setup:
++	free_dpio(priv);
++err_dpio_setup:
++	free_dpni(priv);
++err_dpni_setup:
++	fsl_mc_portal_free(priv->mc_io);
++err_portal_alloc:
++	dev_set_drvdata(dev, NULL);
++	free_netdev(net_dev);
++
++	return err;
++}
++
++static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
++{
++	struct device *dev;
++	struct net_device *net_dev;
++	struct dpaa2_eth_priv *priv;
++
++	dev = &ls_dev->dev;
++	net_dev = dev_get_drvdata(dev);
++	priv = netdev_priv(net_dev);
++
++#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS
++	dpaa2_dbg_remove(priv);
++#endif
++	dpaa2_eth_sysfs_remove(&net_dev->dev);
++
++	unregister_netdev(net_dev);
++
++	disable_ch_napi(priv);
++	del_ch_napi(priv);
++
++	if (priv->do_link_poll)
++		kthread_stop(priv->poll_thread);
++	else
++		fsl_mc_free_irqs(ls_dev);
++
++	free_rings(priv);
++	free_percpu(priv->percpu_stats);
++	free_percpu(priv->percpu_extras);
++	free_dpbp(priv);
++	free_dpio(priv);
++	free_dpni(priv);
++
++	fsl_mc_portal_free(priv->mc_io);
++
++	dev_set_drvdata(dev, NULL);
++	free_netdev(net_dev);
++
++	dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
++
++	return 0;
++}
++
++static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = {
++	{
++		.vendor = FSL_MC_VENDOR_FREESCALE,
++		.obj_type = "dpni",
++	},
++	{ .vendor = 0x0 }
++};
++MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table);
++
++static struct fsl_mc_driver dpaa2_eth_driver = {
++	.driver = {
++		.name = KBUILD_MODNAME,
++		.owner = THIS_MODULE,
++	},
++	.probe = dpaa2_eth_probe,
++	.remove = dpaa2_eth_remove,
++	.match_id_table = dpaa2_eth_match_id_table
++};
++
++static int __init dpaa2_eth_driver_init(void)
++{
++	int err;
++
++	dpaa2_eth_dbg_init();
++	err = fsl_mc_driver_register(&dpaa2_eth_driver);
++	if (err)
++		goto out_debugfs_err;
++
++	err = dpaa2_ceetm_register();
++	if (err)
++		goto out_ceetm_err;
++
++	return 0;
++
++out_ceetm_err:
++	fsl_mc_driver_unregister(&dpaa2_eth_driver);
++out_debugfs_err:
++	dpaa2_eth_dbg_exit();
++	return err;
++}
++
++static void __exit dpaa2_eth_driver_exit(void)
++{
++	dpaa2_ceetm_unregister();
++	fsl_mc_driver_unregister(&dpaa2_eth_driver);
++	dpaa2_eth_dbg_exit();
++}
++
++module_init(dpaa2_eth_driver_init);
++module_exit(dpaa2_eth_driver_exit);
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
+@@ -0,0 +1,601 @@
++/* Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __DPAA2_ETH_H
++#define __DPAA2_ETH_H
++
++#include <linux/dcbnl.h>
++#include <linux/netdevice.h>
++#include <linux/if_vlan.h>
++
++#include "../../fsl-mc/include/dpaa2-io.h"
++#include "../../fsl-mc/include/dpaa2-fd.h"
++#include "dpni.h"
++#include "dpni-cmd.h"
++
++#include "dpaa2-eth-trace.h"
++#include "dpaa2-eth-debugfs.h"
++
++#define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
++
++#define DPAA2_ETH_STORE_SIZE		16
++
++/* We set a max threshold for how many Tx confirmations we should process
++ * on a NAPI poll call, they take less processing time.
++ */
++#define TX_CONF_PER_NAPI_POLL		256
++
++/* Maximum number of scatter-gather entries in an ingress frame,
++ * considering the maximum receive frame size is 64K
++ */
++#define DPAA2_ETH_MAX_SG_ENTRIES	((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
++
++/* Maximum acceptable MTU value. It is in direct relation with the hardware
++ * enforced Max Frame Length (currently 10k).
++ */
++#define DPAA2_ETH_MFL			(10 * 1024)
++#define DPAA2_ETH_MAX_MTU		(DPAA2_ETH_MFL - VLAN_ETH_HLEN)
++/* Convert L3 MTU to L2 MFL */
++#define DPAA2_ETH_L2_MAX_FRM(mtu)	((mtu) + VLAN_ETH_HLEN)
++
++/* Maximum burst size value for Tx shaping */
++#define DPAA2_ETH_MAX_BURST_SIZE	0xF7FF
++
++/* Maximum number of buffers that can be acquired/released through a single
++ * QBMan command
++ */
++#define DPAA2_ETH_BUFS_PER_CMD		7
++
++/* Set the taildrop threshold (in bytes) to allow the enqueue of several jumbo
++ * frames in the Rx queues (length of the current frame is not
++ * taken into account when making the taildrop decision)
++ */
++#define DPAA2_ETH_TAILDROP_THRESH	(64 * 1024)
++
++/* Buffer quota per queue. Must be large enough such that for minimum sized
++ * frames taildrop kicks in before the bpool gets depleted, so we compute
++ * how many 64B frames fit inside the taildrop threshold and add a margin
++ * to accommodate the buffer refill delay.
++ */
++#define DPAA2_ETH_MAX_FRAMES_PER_QUEUE	(DPAA2_ETH_TAILDROP_THRESH / 64)
++#define DPAA2_ETH_NUM_BUFS_PER_CH	(DPAA2_ETH_MAX_FRAMES_PER_QUEUE + 256)
++#define DPAA2_ETH_REFILL_THRESH(priv)	\
++	((priv)->max_bufs_per_ch - DPAA2_ETH_BUFS_PER_CMD)
++
++/* Global buffer quota in case flow control is enabled */
++#define DPAA2_ETH_NUM_BUFS_FC		256
++
++/* Hardware requires alignment for ingress/egress buffer addresses */
++#define DPAA2_ETH_TX_BUF_ALIGN		64
++
++/* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
++ * to 256B. For newer revisions, the requirement is only for 64B alignment
++ */
++#define DPAA2_ETH_RX_BUF_ALIGN_REV1	256
++#define DPAA2_ETH_RX_BUF_ALIGN		64
++
++#define DPAA2_ETH_RX_BUF_SIZE		2048
++#define DPAA2_ETH_SKB_SIZE \
++	(DPAA2_ETH_RX_BUF_SIZE + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
++
++/* PTP nominal frequency 1GHz */
++#define DPAA2_PTP_NOMINAL_FREQ_PERIOD_NS 1
++
++/* Hardware annotation area in RX/TX buffers */
++#define DPAA2_ETH_RX_HWA_SIZE		64
++#define DPAA2_ETH_TX_HWA_SIZE		128
++
++/* We are accommodating a skb backpointer and some S/G info
++ * in the frame's software annotation. The hardware
++ * options are either 0 or 64, so we choose the latter.
++ */
++#define DPAA2_ETH_SWA_SIZE		64
++
++/* We store different information in the software annotation area of a Tx frame
++ * based on what type of frame it is
++ */
++enum dpaa2_eth_swa_type {
++	DPAA2_ETH_SWA_SINGLE,
++	DPAA2_ETH_SWA_SG,
++};
++
++/* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
++struct dpaa2_eth_swa {
++	enum dpaa2_eth_swa_type type;
++	union {
++		struct {
++			struct sk_buff *skb;
++		} single;
++		struct {
++			struct sk_buff *skb;
++			struct scatterlist *scl;
++			int num_sg;
++			int sgt_size;
++		} sg;
++	};
++};
++
++/* Annotation valid bits in FD FRC */
++#define DPAA2_FD_FRC_FASV		0x8000
++#define DPAA2_FD_FRC_FAEADV		0x4000
++#define DPAA2_FD_FRC_FAPRV		0x2000
++#define DPAA2_FD_FRC_FAIADV		0x1000
++#define DPAA2_FD_FRC_FASWOV		0x0800
++#define DPAA2_FD_FRC_FAICFDV		0x0400
++
++#define DPAA2_FD_RX_ERR_MASK		(FD_CTRL_SBE | FD_CTRL_FAERR)
++#define DPAA2_FD_TX_ERR_MASK		(FD_CTRL_UFD	| \
++					 FD_CTRL_SBE	| \
++					 FD_CTRL_FSE	| \
++					 FD_CTRL_FAERR)
++
++/* Annotation bits in FD CTRL */
++#define DPAA2_FD_CTRL_ASAL		0x00020000	/* ASAL = 128 */
++
++/* Frame annotation status */
++struct dpaa2_fas {
++	u8 reserved;
++	u8 ppid;
++	__le16 ifpid;
++	__le32 status;
++};
++
++/* Frame annotation status word is located in the first 8 bytes
++ * of the buffer's hardware annoatation area
++ */
++#define DPAA2_FAS_OFFSET		0
++#define DPAA2_FAS_SIZE			(sizeof(struct dpaa2_fas))
++
++/* Timestamp is located in the next 8 bytes of the buffer's
++ * hardware annotation area
++ */
++#define DPAA2_TS_OFFSET			0x8
++
++/* Frame annotation egress action descriptor */
++#define DPAA2_FAEAD_OFFSET		0x58
++
++struct dpaa2_faead {
++	__le32 conf_fqid;
++	__le32 ctrl;
++};
++
++#define DPAA2_FAEAD_A2V			0x20000000
++#define DPAA2_FAEAD_A4V			0x08000000
++#define DPAA2_FAEAD_UPDV		0x00001000
++#define DPAA2_FAEAD_EBDDV		0x00002000
++#define DPAA2_FAEAD_UPD			0x00000010
++
++/* Accessors for the hardware annotation fields that we use */
++static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
++{
++	return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
++}
++
++static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
++{
++	return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
++}
++
++static inline u64 *dpaa2_get_ts(void *buf_addr, bool swa)
++{
++	return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
++}
++
++static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
++{
++	return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
++}
++
++/* Error and status bits in the frame annotation status word */
++/* Debug frame, otherwise supposed to be discarded */
++#define DPAA2_FAS_DISC			0x80000000
++/* MACSEC frame */
++#define DPAA2_FAS_MS			0x40000000
++#define DPAA2_FAS_PTP			0x08000000
++/* Ethernet multicast frame */
++#define DPAA2_FAS_MC			0x04000000
++/* Ethernet broadcast frame */
++#define DPAA2_FAS_BC			0x02000000
++#define DPAA2_FAS_KSE			0x00040000
++#define DPAA2_FAS_EOFHE			0x00020000
++#define DPAA2_FAS_MNLE			0x00010000
++#define DPAA2_FAS_TIDE			0x00008000
++#define DPAA2_FAS_PIEE			0x00004000
++/* Frame length error */
++#define DPAA2_FAS_FLE			0x00002000
++/* Frame physical error */
++#define DPAA2_FAS_FPE			0x00001000
++#define DPAA2_FAS_PTE			0x00000080
++#define DPAA2_FAS_ISP			0x00000040
++#define DPAA2_FAS_PHE			0x00000020
++#define DPAA2_FAS_BLE			0x00000010
++/* L3 csum validation performed */
++#define DPAA2_FAS_L3CV			0x00000008
++/* L3 csum error */
++#define DPAA2_FAS_L3CE			0x00000004
++/* L4 csum validation performed */
++#define DPAA2_FAS_L4CV			0x00000002
++/* L4 csum error */
++#define DPAA2_FAS_L4CE			0x00000001
++/* Possible errors on the ingress path */
++#define DPAA2_FAS_RX_ERR_MASK		(DPAA2_FAS_KSE		| \
++					 DPAA2_FAS_EOFHE	| \
++					 DPAA2_FAS_MNLE		| \
++					 DPAA2_FAS_TIDE		| \
++					 DPAA2_FAS_PIEE		| \
++					 DPAA2_FAS_FLE		| \
++					 DPAA2_FAS_FPE		| \
++					 DPAA2_FAS_PTE		| \
++					 DPAA2_FAS_ISP		| \
++					 DPAA2_FAS_PHE		| \
++					 DPAA2_FAS_BLE		| \
++					 DPAA2_FAS_L3CE		| \
++					 DPAA2_FAS_L4CE)
++
++/* Time in milliseconds between link state updates */
++#define DPAA2_ETH_LINK_STATE_REFRESH	1000
++
++/* Number of times to retry a frame enqueue before giving up.
++ * Value determined empirically, in order to minimize the number
++ * of frames dropped on Tx
++ */
++#define DPAA2_ETH_ENQUEUE_RETRIES	10
++
++/* Tx congestion entry & exit thresholds, in number of bytes.
++ * We allow a maximum of 512KB worth of frames pending processing on the Tx
++ * queues of an interface
++ */
++#define DPAA2_ETH_TX_CONG_ENTRY_THRESH  (512 * 1024)
++#define DPAA2_ETH_TX_CONG_EXIT_THRESH	\
++	(DPAA2_ETH_TX_CONG_ENTRY_THRESH * 9 / 10)
++
++/* Driver statistics, other than those in struct rtnl_link_stats64.
++ * These are usually collected per-CPU and aggregated by ethtool.
++ */
++struct dpaa2_eth_drv_stats {
++	__u64	tx_conf_frames;
++	__u64	tx_conf_bytes;
++	__u64	tx_sg_frames;
++	__u64	tx_sg_bytes;
++	__u64	tx_reallocs;
++	__u64	rx_sg_frames;
++	__u64	rx_sg_bytes;
++	/* Enqueues retried due to portal busy */
++	__u64	tx_portal_busy;
++};
++
++/* Per-FQ statistics */
++struct dpaa2_eth_fq_stats {
++	/* Number of frames received on this queue */
++	__u64 frames;
++	/* Number of times this queue entered congestion */
++	__u64 congestion_entry;
++};
++
++/* Per-channel statistics */
++struct dpaa2_eth_ch_stats {
++	/* Volatile dequeues retried due to portal busy */
++	__u64 dequeue_portal_busy;
++	/* Number of CDANs; useful to estimate avg NAPI len */
++	__u64 cdan;
++	/* Number of frames received on queues from this channel */
++	__u64 frames;
++	/* Pull errors */
++	__u64 pull_err;
++};
++
++#define DPAA2_ETH_MAX_TCS		8
++
++/* Maximum number of queues associated with a DPNI */
++#define DPAA2_ETH_MAX_RX_QUEUES		(DPNI_MAX_DIST_SIZE * DPAA2_ETH_MAX_TCS)
++#define DPAA2_ETH_MAX_TX_QUEUES		DPNI_MAX_SENDERS
++#define DPAA2_ETH_MAX_RX_ERR_QUEUES	1
++#define DPAA2_ETH_MAX_QUEUES		(DPAA2_ETH_MAX_RX_QUEUES + \
++					DPAA2_ETH_MAX_TX_QUEUES + \
++					DPAA2_ETH_MAX_RX_ERR_QUEUES)
++
++#define DPAA2_ETH_MAX_DPCONS		16
++
++enum dpaa2_eth_fq_type {
++	DPAA2_RX_FQ = 0,
++	DPAA2_TX_CONF_FQ,
++	DPAA2_RX_ERR_FQ
++};
++
++struct dpaa2_eth_priv;
++
++struct dpaa2_eth_fq {
++	u32 fqid;
++	u32 tx_qdbin;
++	u16 flowid;
++	u8 tc;
++	int target_cpu;
++	struct dpaa2_eth_channel *channel;
++	enum dpaa2_eth_fq_type type;
++
++	void (*consume)(struct dpaa2_eth_priv *,
++			struct dpaa2_eth_channel *,
++			const struct dpaa2_fd *,
++			struct napi_struct *,
++			u16 queue_id);
++	struct dpaa2_eth_fq_stats stats;
++};
++
++struct dpaa2_eth_channel {
++	struct dpaa2_io_notification_ctx nctx;
++	struct fsl_mc_device *dpcon;
++	int dpcon_id;
++	int ch_id;
++	struct napi_struct napi;
++	struct dpaa2_io *dpio;
++	struct dpaa2_io_store *store;
++	struct dpaa2_eth_priv *priv;
++	int buf_count;
++	struct dpaa2_eth_ch_stats stats;
++	struct bpf_prog *xdp_prog;
++	u64 rel_buf_array[DPAA2_ETH_BUFS_PER_CMD];
++	u8 rel_buf_cnt;
++};
++
++struct dpaa2_eth_cls_rule {
++	struct ethtool_rx_flow_spec fs;
++	bool in_use;
++};
++
++struct dpaa2_eth_dist_fields {
++	u64 rxnfc_field;
++	enum net_prot cls_prot;
++	int cls_field;
++	int offset;
++	int size;
++	u32 id;
++};
++
++/* Driver private data */
++struct dpaa2_eth_priv {
++	struct net_device *net_dev;
++	/* Standard statistics */
++	struct rtnl_link_stats64 __percpu *percpu_stats;
++	/* Extra stats, in addition to the ones known by the kernel */
++	struct dpaa2_eth_drv_stats __percpu *percpu_extras;
++	bool ts_tx_en; /* Tx timestamping enabled */
++	bool ts_rx_en; /* Rx timestamping enabled */
++	u16 tx_data_offset;
++	u16 bpid;
++	u16 tx_qdid;
++	u16 rx_buf_align;
++	struct iommu_domain *iommu_domain;
++	int max_bufs_per_ch;
++	int refill_thresh;
++	bool has_xdp_prog;
++
++	void *cscn_mem;	/* Tx congestion notifications are written here */
++	void *cscn_unaligned;
++	dma_addr_t cscn_dma;
++
++	u8 num_fqs;
++	struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
++
++	u8 num_channels;
++	struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
++
++	struct dpni_attr dpni_attrs;
++	u16 dpni_ver_major;
++	u16 dpni_ver_minor;
++	struct fsl_mc_device *dpbp_dev;
++
++	struct fsl_mc_io *mc_io;
++	/* Cores which have an affine DPIO/DPCON.
++	 * This is the cpu set on which Rx and Tx conf frames are processed
++	 */
++	struct cpumask dpio_cpumask;
++
++	u16 mc_token;
++
++	struct dpni_link_state link_state;
++	bool do_link_poll;
++	struct task_struct *poll_thread;
++
++	/* Rx distribution (hash and flow steering) header fields
++	 * supported by the driver
++	 */
++	struct dpaa2_eth_dist_fields *dist_fields;
++	u8 num_dist_fields;
++	/* enabled ethtool hashing bits */
++	u64 rx_hash_fields;
++#ifdef CONFIG_FSL_DPAA2_ETH_DEBUGFS
++	struct dpaa2_debugfs dbg;
++#endif
++	/* array of classification rules */
++	struct dpaa2_eth_cls_rule *cls_rule;
++	struct dpni_tx_shaping_cfg shaping_cfg;
++
++	u8 dcbx_mode;
++	struct ieee_pfc pfc;
++	bool vlan_clsf_set;
++	bool tx_pause_frames;
++
++	bool ceetm_en;
++};
++
++enum dpaa2_eth_rx_dist {
++	DPAA2_ETH_RX_DIST_HASH,
++	DPAA2_ETH_RX_DIST_FS,
++	DPAA2_ETH_RX_DIST_LEGACY
++};
++
++/* Supported Rx distribution field ids */
++#define DPAA2_ETH_DIST_ETHSRC		BIT(0)
++#define DPAA2_ETH_DIST_ETHDST		BIT(1)
++#define DPAA2_ETH_DIST_ETHTYPE		BIT(2)
++#define DPAA2_ETH_DIST_VLAN		BIT(3)
++#define DPAA2_ETH_DIST_IPSRC		BIT(4)
++#define DPAA2_ETH_DIST_IPDST		BIT(5)
++#define DPAA2_ETH_DIST_IPPROTO		BIT(6)
++#define DPAA2_ETH_DIST_L4SRC		BIT(7)
++#define DPAA2_ETH_DIST_L4DST		BIT(8)
++#define DPAA2_ETH_DIST_ALL		(~0U)
++
++/* Default Rx hash key */
++#define DPAA2_ETH_DIST_DEFAULT_HASH \
++	(DPAA2_ETH_DIST_IPPROTO | \
++	 DPAA2_ETH_DIST_IPSRC | DPAA2_ETH_DIST_IPDST | \
++	 DPAA2_ETH_DIST_L4SRC | DPAA2_ETH_DIST_L4DST)
++
++#define dpaa2_eth_hash_enabled(priv)	\
++	((priv)->dpni_attrs.num_queues > 1)
++
++#define dpaa2_eth_fs_enabled(priv)	\
++	(!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
++
++#define dpaa2_eth_fs_mask_enabled(priv)	\
++	((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
++
++#define dpaa2_eth_fs_count(priv)	\
++	((priv)->dpni_attrs.fs_entries)
++
++/* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
++#define DPAA2_CLASSIFIER_DMA_SIZE 256
++
++extern const struct ethtool_ops dpaa2_ethtool_ops;
++extern const char dpaa2_eth_drv_version[];
++
++static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
++					 u16 ver_major, u16 ver_minor)
++{
++	if (priv->dpni_ver_major == ver_major)
++		return priv->dpni_ver_minor - ver_minor;
++	return priv->dpni_ver_major - ver_major;
++}
++
++#define DPNI_DIST_KEY_VER_MAJOR			7
++#define DPNI_DIST_KEY_VER_MINOR			5
++
++static inline bool dpaa2_eth_has_legacy_dist(struct dpaa2_eth_priv *priv)
++{
++	return (dpaa2_eth_cmp_dpni_ver(priv, DPNI_DIST_KEY_VER_MAJOR,
++				       DPNI_DIST_KEY_VER_MINOR) < 0);
++}
++
++/* Hardware only sees DPAA2_ETH_RX_BUF_SIZE, but the skb built around
++ * the buffer also needs space for its shared info struct, and we need
++ * to allocate enough to accommodate hardware alignment restrictions
++ */
++static inline unsigned int dpaa2_eth_buf_raw_size(struct dpaa2_eth_priv *priv)
++{
++	return DPAA2_ETH_SKB_SIZE + priv->rx_buf_align;
++}
++
++/* Total headroom needed by the hardware in Tx frame buffers */
++static inline unsigned int
++dpaa2_eth_needed_headroom(struct dpaa2_eth_priv *priv, struct sk_buff *skb)
++{
++	unsigned int headroom = DPAA2_ETH_SWA_SIZE;
++
++	/* If we don't have an skb (e.g. XDP buffer), we only need space for
++	 * the software annotation area
++	 */
++	if (!skb)
++		return headroom;
++
++	/* For non-linear skbs we have no headroom requirement, as we build a
++	 * SG frame with a newly allocated SGT buffer
++	 */
++	if (skb_is_nonlinear(skb))
++		return 0;
++
++	/* If we have Tx timestamping, need 128B hardware annotation */
++	if (priv->ts_tx_en && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
++		headroom += DPAA2_ETH_TX_HWA_SIZE;
++
++	return headroom;
++}
++
++/* Extra headroom space requested to hardware, in order to make sure there's
++ * no realloc'ing in forwarding scenarios. We need to reserve enough space
++ * such that we can accommodate the maximum required Tx offset and alignment
++ * in the ingress frame buffer
++ */
++static inline unsigned int dpaa2_eth_rx_headroom(struct dpaa2_eth_priv *priv)
++{
++	return priv->tx_data_offset + DPAA2_ETH_TX_BUF_ALIGN -
++	       DPAA2_ETH_RX_HWA_SIZE;
++}
++
++static inline int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv)
++{
++	return priv->dpni_attrs.num_queues;
++}
++
++static inline int dpaa2_eth_tc_count(struct dpaa2_eth_priv *priv)
++{
++	return priv->dpni_attrs.num_tcs;
++}
++
++static inline bool dpaa2_eth_is_pfc_enabled(struct dpaa2_eth_priv *priv,
++					    int traffic_class)
++{
++	return priv->pfc.pfc_en & (1 << traffic_class);
++}
++
++enum dpaa2_eth_td_cfg {
++	DPAA2_ETH_TD_NONE,
++	DPAA2_ETH_TD_QUEUE,
++	DPAA2_ETH_TD_GROUP
++};
++
++static inline enum dpaa2_eth_td_cfg
++dpaa2_eth_get_td_type(struct dpaa2_eth_priv *priv)
++{
++	bool pfc_enabled = !!(priv->pfc.pfc_en);
++
++	if (pfc_enabled)
++		return DPAA2_ETH_TD_GROUP;
++	else if (priv->tx_pause_frames)
++		return DPAA2_ETH_TD_NONE;
++	else
++		return DPAA2_ETH_TD_QUEUE;
++}
++
++static inline int dpaa2_eth_ch_count(struct dpaa2_eth_priv *priv)
++{
++	return 1;
++}
++
++void check_cls_support(struct dpaa2_eth_priv *priv);
++
++int set_rx_taildrop(struct dpaa2_eth_priv *priv);
++
++int dpaa2_eth_set_dist_key(struct dpaa2_eth_priv *priv,
++			   enum dpaa2_eth_rx_dist type, u32 key_fields);
++
++#endif	/* __DPAA2_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c
+@@ -0,0 +1,878 @@
++/* Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2016-2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include "dpni.h"	/* DPNI_LINK_OPT_* */
++#include "dpaa2-eth.h"
++
++/* To be kept in sync with DPNI statistics */
++static char dpaa2_ethtool_stats[][ETH_GSTRING_LEN] = {
++	"[hw] rx frames",
++	"[hw] rx bytes",
++	"[hw] rx mcast frames",
++	"[hw] rx mcast bytes",
++	"[hw] rx bcast frames",
++	"[hw] rx bcast bytes",
++	"[hw] tx frames",
++	"[hw] tx bytes",
++	"[hw] tx mcast frames",
++	"[hw] tx mcast bytes",
++	"[hw] tx bcast frames",
++	"[hw] tx bcast bytes",
++	"[hw] rx filtered frames",
++	"[hw] rx discarded frames",
++	"[hw] rx nobuffer discards",
++	"[hw] tx discarded frames",
++	"[hw] tx confirmed frames",
++};
++
++#define DPAA2_ETH_NUM_STATS	ARRAY_SIZE(dpaa2_ethtool_stats)
++
++static char dpaa2_ethtool_extras[][ETH_GSTRING_LEN] = {
++	/* per-cpu stats */
++	"[drv] tx conf frames",
++	"[drv] tx conf bytes",
++	"[drv] tx sg frames",
++	"[drv] tx sg bytes",
++	"[drv] tx realloc frames",
++	"[drv] rx sg frames",
++	"[drv] rx sg bytes",
++	"[drv] enqueue portal busy",
++	/* Channel stats */
++	"[drv] dequeue portal busy",
++	"[drv] channel pull errors",
++	"[drv] cdan",
++	"[drv] tx congestion state",
++#ifdef CONFIG_FSL_QBMAN_DEBUG
++	/* FQ stats */
++	"rx pending frames",
++	"rx pending bytes",
++	"tx conf pending frames",
++	"tx conf pending bytes",
++	"buffer count"
++#endif
++};
++
++#define DPAA2_ETH_NUM_EXTRA_STATS	ARRAY_SIZE(dpaa2_ethtool_extras)
++
++static void dpaa2_eth_get_drvinfo(struct net_device *net_dev,
++				  struct ethtool_drvinfo *drvinfo)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++
++	strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
++	strlcpy(drvinfo->version, dpaa2_eth_drv_version,
++		sizeof(drvinfo->version));
++
++	snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
++		 "%u.%u", priv->dpni_ver_major, priv->dpni_ver_minor);
++
++	strlcpy(drvinfo->bus_info, dev_name(net_dev->dev.parent->parent),
++		sizeof(drvinfo->bus_info));
++}
++
++static int
++dpaa2_eth_get_link_ksettings(struct net_device *net_dev,
++			     struct ethtool_link_ksettings *link_settings)
++{
++	struct dpni_link_state state = {0};
++	int err = 0;
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++
++	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
++	if (err) {
++		netdev_err(net_dev, "ERROR %d getting link state\n", err);
++		goto out;
++	}
++
++	/* At the moment, we have no way of interrogating the DPMAC
++	 * from the DPNI side - and for that matter there may exist
++	 * no DPMAC at all. So for now we just don't report anything
++	 * beyond the DPNI attributes.
++	 */
++	if (state.options & DPNI_LINK_OPT_AUTONEG)
++		link_settings->base.autoneg = AUTONEG_ENABLE;
++	if (!(state.options & DPNI_LINK_OPT_HALF_DUPLEX))
++		link_settings->base.duplex = DUPLEX_FULL;
++	link_settings->base.speed = state.rate;
++
++out:
++	return err;
++}
++
++#define DPNI_DYNAMIC_LINK_SET_VER_MAJOR		7
++#define DPNI_DYNAMIC_LINK_SET_VER_MINOR		1
++static int
++dpaa2_eth_set_link_ksettings(struct net_device *net_dev,
++			     const struct ethtool_link_ksettings *link_settings)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct dpni_link_state state = {0};
++	struct dpni_link_cfg cfg = {0};
++	int err = 0;
++
++	/* If using an older MC version, the DPNI must be down
++ 	 * in order to be able to change link settings. Taking steps to let
++ 	 * the user know that.
++ 	 */
++	if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_DYNAMIC_LINK_SET_VER_MAJOR,
++				   DPNI_DYNAMIC_LINK_SET_VER_MINOR) < 0) {
++		if (netif_running(net_dev)) {
++			netdev_info(net_dev, "Interface must be brought down first.\n");
++			return -EACCES;
++		}
++	}
++
++	/* Need to interrogate link state to get flow control params */
++	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
++	if (err) {
++		netdev_err(net_dev, "Error getting link state\n");
++		goto out;
++	}
++
++	cfg.options = state.options;
++	cfg.rate = link_settings->base.speed;
++	if (link_settings->base.autoneg == AUTONEG_ENABLE)
++		cfg.options |= DPNI_LINK_OPT_AUTONEG;
++	else
++		cfg.options &= ~DPNI_LINK_OPT_AUTONEG;
++	if (link_settings->base.duplex  == DUPLEX_HALF)
++		cfg.options |= DPNI_LINK_OPT_HALF_DUPLEX;
++	else
++		cfg.options &= ~DPNI_LINK_OPT_HALF_DUPLEX;
++
++	err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &cfg);
++	if (err)
++		/* ethtool will be loud enough if we return an error; no point
++		 * in putting our own error message on the console by default
++		 */
++		netdev_dbg(net_dev, "ERROR %d setting link cfg\n", err);
++
++out:
++	return err;
++}
++
++static void dpaa2_eth_get_pauseparam(struct net_device *net_dev,
++				     struct ethtool_pauseparam *pause)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct dpni_link_state state = {0};
++	int err;
++
++	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
++	if (err)
++		netdev_dbg(net_dev, "Error getting link state\n");
++
++	/* Report general port autonegotiation status */
++	pause->autoneg = !!(state.options & DPNI_LINK_OPT_AUTONEG);
++	pause->rx_pause = !!(state.options & DPNI_LINK_OPT_PAUSE);
++	pause->tx_pause = pause->rx_pause ^
++			  !!(state.options & DPNI_LINK_OPT_ASYM_PAUSE);
++}
++
++static int dpaa2_eth_set_pauseparam(struct net_device *net_dev,
++				    struct ethtool_pauseparam *pause)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct dpni_link_state state = {0};
++	struct dpni_link_cfg cfg = {0};
++	u32 current_tx_pause;
++	int err = 0;
++
++	err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
++	if (err) {
++		netdev_dbg(net_dev, "Error getting link state\n");
++		goto out;
++	}
++
++	cfg.rate = state.rate;
++	cfg.options = state.options;
++	current_tx_pause = !!(cfg.options & DPNI_LINK_OPT_PAUSE) ^
++			   !!(cfg.options & DPNI_LINK_OPT_ASYM_PAUSE);
++
++	/* We don't support changing pause frame autonegotiation separately
++	 * from general port autoneg
++	 */
++	if (pause->autoneg != !!(state.options & DPNI_LINK_OPT_AUTONEG))
++		netdev_warn(net_dev,
++			    "Cannot change pause frame autoneg separately\n");
++
++	if (pause->rx_pause)
++		cfg.options |= DPNI_LINK_OPT_PAUSE;
++	else
++		cfg.options &= ~DPNI_LINK_OPT_PAUSE;
++
++	if (pause->rx_pause ^ pause->tx_pause)
++		cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
++	else
++		cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
++
++	err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &cfg);
++	if (err) {
++		netdev_dbg(net_dev, "Error setting link\n");
++		goto out;
++	}
++
++	/* Enable/disable Rx FQ taildrop if Tx pause frames have changed */
++	if (current_tx_pause == pause->tx_pause)
++		goto out;
++
++	priv->tx_pause_frames = pause->tx_pause;
++	err = set_rx_taildrop(priv);
++	if (err)
++		netdev_dbg(net_dev, "Error configuring taildrop\n");
++
++out:
++	return err;
++}
++
++static void dpaa2_eth_get_strings(struct net_device *netdev, u32 stringset,
++				  u8 *data)
++{
++	u8 *p = data;
++	int i;
++
++	switch (stringset) {
++	case ETH_SS_STATS:
++		for (i = 0; i < DPAA2_ETH_NUM_STATS; i++) {
++			strlcpy(p, dpaa2_ethtool_stats[i], ETH_GSTRING_LEN);
++			p += ETH_GSTRING_LEN;
++		}
++		for (i = 0; i < DPAA2_ETH_NUM_EXTRA_STATS; i++) {
++			strlcpy(p, dpaa2_ethtool_extras[i], ETH_GSTRING_LEN);
++			p += ETH_GSTRING_LEN;
++		}
++		break;
++	}
++}
++
++static int dpaa2_eth_get_sset_count(struct net_device *net_dev, int sset)
++{
++	switch (sset) {
++	case ETH_SS_STATS: /* ethtool_get_stats(), ethtool_get_drvinfo() */
++		return DPAA2_ETH_NUM_STATS + DPAA2_ETH_NUM_EXTRA_STATS;
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++/** Fill in hardware counters, as returned by MC.
++ */
++static void dpaa2_eth_get_ethtool_stats(struct net_device *net_dev,
++					struct ethtool_stats *stats,
++					u64 *data)
++{
++	int i = 0;
++	int j, k, err;
++	int num_cnt;
++	union dpni_statistics dpni_stats;
++
++#ifdef CONFIG_FSL_QBMAN_DEBUG
++	u32 fcnt, bcnt;
++	u32 fcnt_rx_total = 0, fcnt_tx_total = 0;
++	u32 bcnt_rx_total = 0, bcnt_tx_total = 0;
++	u32 buf_cnt;
++#endif
++	u64 cdan = 0;
++	u64 portal_busy = 0, pull_err = 0;
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct dpaa2_eth_drv_stats *extras;
++	struct dpaa2_eth_ch_stats *ch_stats;
++
++	memset(data, 0,
++	       sizeof(u64) * (DPAA2_ETH_NUM_STATS + DPAA2_ETH_NUM_EXTRA_STATS));
++
++	/* Print standard counters, from DPNI statistics */
++	for (j = 0; j <= 2; j++) {
++		err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token,
++					  j, 0, &dpni_stats);
++		if (err != 0)
++			netdev_warn(net_dev, "dpni_get_stats(%d) failed\n", j);
++		switch (j) {
++		case 0:
++			num_cnt = sizeof(dpni_stats.page_0) / sizeof(u64);
++			break;
++		case 1:
++			num_cnt = sizeof(dpni_stats.page_1) / sizeof(u64);
++			break;
++		case 2:
++			num_cnt = sizeof(dpni_stats.page_2) / sizeof(u64);
++			break;
++		}
++		for (k = 0; k < num_cnt; k++)
++			*(data + i++) = dpni_stats.raw.counter[k];
++	}
++
++	/* Print per-cpu extra stats */
++	for_each_online_cpu(k) {
++		extras = per_cpu_ptr(priv->percpu_extras, k);
++		for (j = 0; j < sizeof(*extras) / sizeof(__u64); j++)
++			*((__u64 *)data + i + j) += *((__u64 *)extras + j);
++	}
++	i += j;
++
++	for (j = 0; j < priv->num_channels; j++) {
++		ch_stats = &priv->channel[j]->stats;
++		cdan += ch_stats->cdan;
++		portal_busy += ch_stats->dequeue_portal_busy;
++		pull_err += ch_stats->pull_err;
++	}
++
++	*(data + i++) = portal_busy;
++	*(data + i++) = pull_err;
++	*(data + i++) = cdan;
++
++	*(data + i++) = dpaa2_cscn_state_congested(priv->cscn_mem);
++
++#ifdef CONFIG_FSL_QBMAN_DEBUG
++	for (j = 0; j < priv->num_fqs; j++) {
++		/* Print FQ instantaneous counts */
++		err = dpaa2_io_query_fq_count(NULL, priv->fq[j].fqid,
++					      &fcnt, &bcnt);
++		if (err) {
++			netdev_warn(net_dev, "FQ query error %d", err);
++			return;
++		}
++
++		if (priv->fq[j].type == DPAA2_TX_CONF_FQ) {
++			fcnt_tx_total += fcnt;
++			bcnt_tx_total += bcnt;
++		} else {
++			fcnt_rx_total += fcnt;
++			bcnt_rx_total += bcnt;
++		}
++	}
++
++	*(data + i++) = fcnt_rx_total;
++	*(data + i++) = bcnt_rx_total;
++	*(data + i++) = fcnt_tx_total;
++	*(data + i++) = bcnt_tx_total;
++
++	err = dpaa2_io_query_bp_count(NULL, priv->bpid, &buf_cnt);
++	if (err) {
++		netdev_warn(net_dev, "Buffer count query error %d\n", err);
++		return;
++	}
++	*(data + i++) = buf_cnt;
++#endif
++}
++
++static int cls_key_off(struct dpaa2_eth_priv *priv, int prot, int field)
++{
++	int i, off = 0;
++
++	for (i = 0; i < priv->num_dist_fields; i++) {
++		if (priv->dist_fields[i].cls_prot == prot &&
++		    priv->dist_fields[i].cls_field == field)
++			return off;
++		off += priv->dist_fields[i].size;
++	}
++
++	return -1;
++}
++
++static u8 cls_key_size(struct dpaa2_eth_priv *priv)
++{
++	u8 i, size = 0;
++
++	for (i = 0; i < priv->num_dist_fields; i++)
++		size += priv->dist_fields[i].size;
++
++	return size;
++}
++
++void check_cls_support(struct dpaa2_eth_priv *priv)
++{
++	u8 key_size = cls_key_size(priv);
++	struct device *dev = priv->net_dev->dev.parent;
++
++	if (dpaa2_eth_hash_enabled(priv)) {
++		if (priv->dpni_attrs.fs_key_size < key_size) {
++			dev_info(dev, "max_dist_key_size = %d, expected %d. Hashing and steering are disabled\n",
++				 priv->dpni_attrs.fs_key_size,
++				 key_size);
++			goto disable_fs;
++		}
++		if (priv->num_dist_fields > DPKG_MAX_NUM_OF_EXTRACTS) {
++			dev_info(dev, "Too many key fields (max = %d). Hashing and steering are disabled\n",
++				 DPKG_MAX_NUM_OF_EXTRACTS);
++			goto disable_fs;
++		}
++	}
++
++	if (dpaa2_eth_fs_enabled(priv)) {
++		if (!dpaa2_eth_hash_enabled(priv)) {
++			dev_info(dev, "Insufficient queues. Steering is disabled\n");
++			goto disable_fs;
++		}
++
++		if (!dpaa2_eth_fs_mask_enabled(priv)) {
++			dev_info(dev, "Key masks not supported. Steering is disabled\n");
++			goto disable_fs;
++		}
++	}
++
++	return;
++
++disable_fs:
++	priv->dpni_attrs.options |= DPNI_OPT_NO_FS;
++	priv->dpni_attrs.options &= ~DPNI_OPT_HAS_KEY_MASKING;
++}
++
++static int prep_l4_rule(struct dpaa2_eth_priv *priv,
++			struct ethtool_tcpip4_spec *l4_value,
++			struct ethtool_tcpip4_spec *l4_mask,
++			void *key, void *mask, u8 l4_proto)
++{
++	int offset;
++
++	if (l4_mask->tos) {
++		netdev_err(priv->net_dev, "ToS is not supported for IPv4 L4\n");
++		return -EOPNOTSUPP;
++	}
++
++	if (l4_mask->ip4src) {
++		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_SRC);
++		*(u32 *)(key + offset) = l4_value->ip4src;
++		*(u32 *)(mask + offset) = l4_mask->ip4src;
++	}
++
++	if (l4_mask->ip4dst) {
++		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_DST);
++		*(u32 *)(key + offset) = l4_value->ip4dst;
++		*(u32 *)(mask + offset) = l4_mask->ip4dst;
++	}
++
++	if (l4_mask->psrc) {
++		offset = cls_key_off(priv, NET_PROT_UDP, NH_FLD_UDP_PORT_SRC);
++		*(u32 *)(key + offset) = l4_value->psrc;
++		*(u32 *)(mask + offset) = l4_mask->psrc;
++	}
++
++	if (l4_mask->pdst) {
++		offset = cls_key_off(priv, NET_PROT_UDP, NH_FLD_UDP_PORT_DST);
++		*(u32 *)(key + offset) = l4_value->pdst;
++		*(u32 *)(mask + offset) = l4_mask->pdst;
++	}
++
++	/* Only apply the rule for the user-specified L4 protocol
++	 * and if ethertype matches IPv4
++	 */
++	offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_TYPE);
++	*(u16 *)(key + offset) = htons(ETH_P_IP);
++	*(u16 *)(mask + offset) = 0xFFFF;
++
++	offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_PROTO);
++	*(u8 *)(key + offset) = l4_proto;
++	*(u8 *)(mask + offset) = 0xFF;
++
++	/* TODO: check IP version */
++
++	return 0;
++}
++
++static int prep_eth_rule(struct dpaa2_eth_priv *priv,
++			 struct ethhdr *eth_value, struct ethhdr *eth_mask,
++			 void *key, void *mask)
++{
++	int offset;
++
++	if (eth_mask->h_proto) {
++		netdev_err(priv->net_dev, "Ethertype is not supported!\n");
++		return -EOPNOTSUPP;
++	}
++
++	if (!is_zero_ether_addr(eth_mask->h_source)) {
++		offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_SA);
++		ether_addr_copy(key + offset, eth_value->h_source);
++		ether_addr_copy(mask + offset, eth_mask->h_source);
++	}
++
++	if (!is_zero_ether_addr(eth_mask->h_dest)) {
++		offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_DA);
++		ether_addr_copy(key + offset, eth_value->h_dest);
++		ether_addr_copy(mask + offset, eth_mask->h_dest);
++	}
++
++	return 0;
++}
++
++static int prep_user_ip_rule(struct dpaa2_eth_priv *priv,
++			     struct ethtool_usrip4_spec *uip_value,
++			     struct ethtool_usrip4_spec *uip_mask,
++			     void *key, void *mask)
++{
++	int offset;
++
++	if (uip_mask->tos)
++		return -EOPNOTSUPP;
++
++	if (uip_mask->ip4src) {
++		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_SRC);
++		*(u32 *)(key + offset) = uip_value->ip4src;
++		*(u32 *)(mask + offset) = uip_mask->ip4src;
++	}
++
++	if (uip_mask->ip4dst) {
++		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_DST);
++		*(u32 *)(key + offset) = uip_value->ip4dst;
++		*(u32 *)(mask + offset) = uip_mask->ip4dst;
++	}
++
++	if (uip_mask->proto) {
++		offset = cls_key_off(priv, NET_PROT_IP, NH_FLD_IP_PROTO);
++		*(u32 *)(key + offset) = uip_value->proto;
++		*(u32 *)(mask + offset) = uip_mask->proto;
++	}
++	if (uip_mask->l4_4_bytes) {
++		offset = cls_key_off(priv, NET_PROT_UDP, NH_FLD_UDP_PORT_SRC);
++		*(u16 *)(key + offset) = uip_value->l4_4_bytes << 16;
++		*(u16 *)(mask + offset) = uip_mask->l4_4_bytes << 16;
++
++		offset = cls_key_off(priv, NET_PROT_UDP, NH_FLD_UDP_PORT_DST);
++		*(u16 *)(key + offset) = uip_value->l4_4_bytes & 0xFFFF;
++		*(u16 *)(mask + offset) = uip_mask->l4_4_bytes & 0xFFFF;
++	}
++
++	/* Ethertype must be IP */
++	offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_TYPE);
++	*(u16 *)(key + offset) = htons(ETH_P_IP);
++	*(u16 *)(mask + offset) = 0xFFFF;
++
++	return 0;
++}
++
++static int prep_ext_rule(struct dpaa2_eth_priv *priv,
++			 struct ethtool_flow_ext *ext_value,
++			 struct ethtool_flow_ext *ext_mask,
++			 void *key, void *mask)
++{
++	int offset;
++
++	if (ext_mask->vlan_etype)
++		return -EOPNOTSUPP;
++
++	if (ext_mask->vlan_tci) {
++		offset = cls_key_off(priv, NET_PROT_VLAN, NH_FLD_VLAN_TCI);
++		*(u16 *)(key + offset) = ext_value->vlan_tci;
++		*(u16 *)(mask + offset) = ext_mask->vlan_tci;
++	}
++
++	return 0;
++}
++
++static int prep_mac_ext_rule(struct dpaa2_eth_priv *priv,
++			     struct ethtool_flow_ext *ext_value,
++			     struct ethtool_flow_ext *ext_mask,
++			     void *key, void *mask)
++{
++	int offset;
++
++	if (!is_zero_ether_addr(ext_mask->h_dest)) {
++		offset = cls_key_off(priv, NET_PROT_ETH, NH_FLD_ETH_DA);
++		ether_addr_copy(key + offset, ext_value->h_dest);
++		ether_addr_copy(mask + offset, ext_mask->h_dest);
++	}
++
++	return 0;
++}
++
++static int prep_cls_rule(struct net_device *net_dev,
++			 struct ethtool_rx_flow_spec *fs,
++			 void *key)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	const u8 key_size = cls_key_size(priv);
++	void *msk = key + key_size;
++	int err;
++
++	memset(key, 0, key_size * 2);
++
++	switch (fs->flow_type & 0xff) {
++	case TCP_V4_FLOW:
++		err = prep_l4_rule(priv, &fs->h_u.tcp_ip4_spec,
++				   &fs->m_u.tcp_ip4_spec, key, msk,
++				   IPPROTO_TCP);
++		break;
++	case UDP_V4_FLOW:
++		err = prep_l4_rule(priv, &fs->h_u.udp_ip4_spec,
++				   &fs->m_u.udp_ip4_spec, key, msk,
++				   IPPROTO_UDP);
++		break;
++	case SCTP_V4_FLOW:
++		err = prep_l4_rule(priv, &fs->h_u.sctp_ip4_spec,
++				   &fs->m_u.sctp_ip4_spec, key, msk,
++				   IPPROTO_SCTP);
++		break;
++	case ETHER_FLOW:
++		err = prep_eth_rule(priv, &fs->h_u.ether_spec,
++				    &fs->m_u.ether_spec, key, msk);
++		break;
++	case IP_USER_FLOW:
++		err = prep_user_ip_rule(priv, &fs->h_u.usr_ip4_spec,
++					&fs->m_u.usr_ip4_spec, key, msk);
++		break;
++	default:
++		/* TODO: AH, ESP */
++		return -EOPNOTSUPP;
++	}
++	if (err)
++		return err;
++
++	if (fs->flow_type & FLOW_EXT) {
++		err = prep_ext_rule(priv, &fs->h_ext, &fs->m_ext, key, msk);
++		if (err)
++			return err;
++	}
++
++	if (fs->flow_type & FLOW_MAC_EXT) {
++		err = prep_mac_ext_rule(priv, &fs->h_ext, &fs->m_ext, key, msk);
++		if (err)
++			return err;
++	}
++
++	return 0;
++}
++
++static int del_cls(struct net_device *net_dev, int location);
++
++static int do_cls(struct net_device *net_dev,
++		  struct ethtool_rx_flow_spec *fs,
++		  bool add)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	struct device *dev = net_dev->dev.parent;
++	const int rule_cnt = dpaa2_eth_fs_count(priv);
++	struct dpni_rule_cfg rule_cfg;
++	struct dpni_fs_action_cfg fs_act = { 0 };
++	void *dma_mem;
++	int err = 0, tc;
++
++	if (!dpaa2_eth_fs_enabled(priv)) {
++		netdev_err(net_dev, "dev does not support steering!\n");
++		/* dev doesn't support steering */
++		return -EOPNOTSUPP;
++	}
++
++	if ((fs->ring_cookie != RX_CLS_FLOW_DISC &&
++	     fs->ring_cookie >= dpaa2_eth_queue_count(priv)) ||
++	     fs->location >= rule_cnt)
++		return -EINVAL;
++
++	/* When adding a new rule, check if location if available
++	 * and if not, free the existing table entry before inserting
++	 * the new one
++	 */
++	if (add && (priv->cls_rule[fs->location].in_use == true))
++		del_cls(net_dev, fs->location);
++
++	memset(&rule_cfg, 0, sizeof(rule_cfg));
++	rule_cfg.key_size = cls_key_size(priv);
++
++	/* allocate twice the key size, for the actual key and for mask */
++	dma_mem = kzalloc(rule_cfg.key_size * 2, GFP_DMA | GFP_KERNEL);
++	if (!dma_mem)
++		return -ENOMEM;
++
++	err = prep_cls_rule(net_dev, fs, dma_mem);
++	if (err)
++		goto err_free_mem;
++
++	rule_cfg.key_iova = dma_map_single(dev, dma_mem,
++					   rule_cfg.key_size * 2,
++					   DMA_TO_DEVICE);
++
++	rule_cfg.mask_iova = rule_cfg.key_iova + rule_cfg.key_size;
++
++	if (fs->ring_cookie == RX_CLS_FLOW_DISC)
++		fs_act.options |= DPNI_FS_OPT_DISCARD;
++	else
++		fs_act.flow_id = fs->ring_cookie;
++
++	for (tc = 0; tc < dpaa2_eth_tc_count(priv); tc++) {
++		if (add)
++			err = dpni_add_fs_entry(priv->mc_io, 0, priv->mc_token,
++						tc, fs->location, &rule_cfg,
++						&fs_act);
++		else
++			err = dpni_remove_fs_entry(priv->mc_io, 0,
++						   priv->mc_token, tc,
++						   &rule_cfg);
++
++		if (err)
++			break;
++	}
++
++	dma_unmap_single(dev, rule_cfg.key_iova,
++			 rule_cfg.key_size * 2, DMA_TO_DEVICE);
++
++	if (err)
++		netdev_err(net_dev, "dpaa2_add/remove_cls() error %d\n", err);
++
++err_free_mem:
++	kfree(dma_mem);
++
++	return err;
++}
++
++static int add_cls(struct net_device *net_dev,
++		   struct ethtool_rx_flow_spec *fs)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	int err;
++
++	err = do_cls(net_dev, fs, true);
++	if (err)
++		return err;
++
++	priv->cls_rule[fs->location].in_use = true;
++	priv->cls_rule[fs->location].fs = *fs;
++
++	return 0;
++}
++
++static int del_cls(struct net_device *net_dev, int location)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	int err;
++
++	err = do_cls(net_dev, &priv->cls_rule[location].fs, false);
++	if (err)
++		return err;
++
++	priv->cls_rule[location].in_use = false;
++
++	return 0;
++}
++
++static int set_hash(struct net_device *net_dev, u64 data)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	u32 key = 0;
++	int i;
++
++	if (data & RXH_DISCARD)
++		return -EOPNOTSUPP;
++
++	for (i = 0; i < priv->num_dist_fields; i++)
++		if (priv->dist_fields[i].rxnfc_field & data)
++			key |= priv->dist_fields[i].id;
++
++	return dpaa2_eth_set_dist_key(priv, DPAA2_ETH_RX_DIST_HASH, key);
++}
++
++static int dpaa2_eth_set_rxnfc(struct net_device *net_dev,
++			       struct ethtool_rxnfc *rxnfc)
++{
++	int err = 0;
++
++	switch (rxnfc->cmd) {
++	case ETHTOOL_SRXCLSRLINS:
++		err = add_cls(net_dev, &rxnfc->fs);
++		break;
++	case ETHTOOL_SRXCLSRLDEL:
++		err = del_cls(net_dev, rxnfc->fs.location);
++		break;
++	case ETHTOOL_SRXFH:
++		err = set_hash(net_dev, rxnfc->data);
++		break;
++	default:
++		err = -EOPNOTSUPP;
++	}
++
++	return err;
++}
++
++static int dpaa2_eth_get_rxnfc(struct net_device *net_dev,
++			       struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
++{
++	struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
++	const int rule_cnt = dpaa2_eth_fs_count(priv);
++	int i, j;
++
++	switch (rxnfc->cmd) {
++	case ETHTOOL_GRXFH:
++		/* we purposely ignore cmd->flow_type for now, because the
++		 * classifier only supports a single set of fields for all
++		 * protocols
++		 */
++		rxnfc->data = priv->rx_hash_fields;
++		break;
++	case ETHTOOL_GRXRINGS:
++		rxnfc->data = dpaa2_eth_queue_count(priv);
++		break;
++
++	case ETHTOOL_GRXCLSRLCNT:
++		for (i = 0, rxnfc->rule_cnt = 0; i < rule_cnt; i++)
++			if (priv->cls_rule[i].in_use)
++				rxnfc->rule_cnt++;
++		rxnfc->data = rule_cnt;
++		break;
++
++	case ETHTOOL_GRXCLSRULE:
++		if (!priv->cls_rule[rxnfc->fs.location].in_use)
++			return -EINVAL;
++
++		rxnfc->fs = priv->cls_rule[rxnfc->fs.location].fs;
++		break;
++
++	case ETHTOOL_GRXCLSRLALL:
++		for (i = 0, j = 0; i < rule_cnt; i++) {
++			if (!priv->cls_rule[i].in_use)
++				continue;
++			if (j == rxnfc->rule_cnt)
++				return -EMSGSIZE;
++			rule_locs[j++] = i;
++		}
++		rxnfc->rule_cnt = j;
++		rxnfc->data = rule_cnt;
++		break;
++
++	default:
++		return -EOPNOTSUPP;
++	}
++
++	return 0;
++}
++
++const struct ethtool_ops dpaa2_ethtool_ops = {
++	.get_drvinfo = dpaa2_eth_get_drvinfo,
++	.get_link = ethtool_op_get_link,
++	.get_link_ksettings = dpaa2_eth_get_link_ksettings,
++	.set_link_ksettings = dpaa2_eth_set_link_ksettings,
++	.get_pauseparam = dpaa2_eth_get_pauseparam,
++	.set_pauseparam = dpaa2_eth_set_pauseparam,
++	.get_sset_count = dpaa2_eth_get_sset_count,
++	.get_ethtool_stats = dpaa2_eth_get_ethtool_stats,
++	.get_strings = dpaa2_eth_get_strings,
++	.get_rxnfc = dpaa2_eth_get_rxnfc,
++	.set_rxnfc = dpaa2_eth_set_rxnfc,
++};
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpkg.h
+@@ -0,0 +1,176 @@
++/* Copyright 2013-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef __FSL_DPKG_H_
++#define __FSL_DPKG_H_
++
++#include <linux/types.h>
++#include "net.h"
++
++/* Data Path Key Generator API
++ * Contains initialization APIs and runtime APIs for the Key Generator
++ */
++
++/** Key Generator properties */
++
++/**
++ * Number of masks per key extraction
++ */
++#define DPKG_NUM_OF_MASKS		4
++/**
++ * Number of extractions per key profile
++ */
++#define DPKG_MAX_NUM_OF_EXTRACTS	10
++
++/**
++ * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
++ * @DPKG_FROM_HDR: Extract selected bytes from header, by offset
++ * @DPKG_FROM_FIELD: Extract selected bytes from header, by offset from field
++ * @DPKG_FULL_FIELD: Extract a full field
++ */
++enum dpkg_extract_from_hdr_type {
++	DPKG_FROM_HDR = 0,
++	DPKG_FROM_FIELD = 1,
++	DPKG_FULL_FIELD = 2
++};
++
++/**
++ * enum dpkg_extract_type - Enumeration for selecting extraction type
++ * @DPKG_EXTRACT_FROM_HDR: Extract from the header
++ * @DPKG_EXTRACT_FROM_DATA: Extract from data not in specific header
++ * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
++ *	e.g. can be used to extract header existence;
++ *	please refer to 'Parse Result definition' section in the parser BG
++ */
++enum dpkg_extract_type {
++	DPKG_EXTRACT_FROM_HDR = 0,
++	DPKG_EXTRACT_FROM_DATA = 1,
++	DPKG_EXTRACT_FROM_PARSE = 3
++};
++
++/**
++ * struct dpkg_mask - A structure for defining a single extraction mask
++ * @mask: Byte mask for the extracted content
++ * @offset: Offset within the extracted content
++ */
++struct dpkg_mask {
++	u8 mask;
++	u8 offset;
++};
++
++/**
++ * struct dpkg_extract - A structure for defining a single extraction
++ * @type: Determines how the union below is interpreted:
++ *		DPKG_EXTRACT_FROM_HDR: selects 'from_hdr';
++ *		DPKG_EXTRACT_FROM_DATA: selects 'from_data';
++ *		DPKG_EXTRACT_FROM_PARSE: selects 'from_parse'
++ * @extract: Selects extraction method
++ * @num_of_byte_masks: Defines the number of valid entries in the array below;
++ *		This is	also the number of bytes to be used as masks
++ * @masks: Masks parameters
++ */
++struct dpkg_extract {
++	enum dpkg_extract_type type;
++	/**
++	 * union extract - Selects extraction method
++	 * @from_hdr - Used when 'type = DPKG_EXTRACT_FROM_HDR'
++	 * @from_data - Used when 'type = DPKG_EXTRACT_FROM_DATA'
++	 * @from_parse - Used when 'type = DPKG_EXTRACT_FROM_PARSE'
++	 */
++	union {
++		/**
++		 * struct from_hdr - Used when 'type = DPKG_EXTRACT_FROM_HDR'
++		 * @prot: Any of the supported headers
++		 * @type: Defines the type of header extraction:
++		 *	DPKG_FROM_HDR: use size & offset below;
++		 *	DPKG_FROM_FIELD: use field, size and offset below;
++		 *	DPKG_FULL_FIELD: use field below
++		 * @field: One of the supported fields (NH_FLD_)
++		 *
++		 * @size: Size in bytes
++		 * @offset: Byte offset
++		 * @hdr_index: Clear for cases not listed below;
++		 *	Used for protocols that may have more than a single
++		 *	header, 0 indicates an outer header;
++		 *	Supported protocols (possible values):
++		 *	NET_PROT_VLAN (0, HDR_INDEX_LAST);
++		 *	NET_PROT_MPLS (0, 1, HDR_INDEX_LAST);
++		 *	NET_PROT_IP(0, HDR_INDEX_LAST);
++		 *	NET_PROT_IPv4(0, HDR_INDEX_LAST);
++		 *	NET_PROT_IPv6(0, HDR_INDEX_LAST);
++		 */
++
++		struct {
++			enum net_prot			prot;
++			enum dpkg_extract_from_hdr_type type;
++			u32			field;
++			u8			size;
++			u8			offset;
++			u8			hdr_index;
++		} from_hdr;
++		/**
++		 * struct from_data - Used when 'type = DPKG_EXTRACT_FROM_DATA'
++		 * @size: Size in bytes
++		 * @offset: Byte offset
++		 */
++		struct {
++			u8 size;
++			u8 offset;
++		} from_data;
++
++		/**
++		 * struct from_parse - Used when
++		 *		       'type = DPKG_EXTRACT_FROM_PARSE'
++		 * @size: Size in bytes
++		 * @offset: Byte offset
++		 */
++		struct {
++			u8 size;
++			u8 offset;
++		} from_parse;
++	} extract;
++
++	u8		num_of_byte_masks;
++	struct dpkg_mask	masks[DPKG_NUM_OF_MASKS];
++};
++
++/**
++ * struct dpkg_profile_cfg - A structure for defining a full Key Generation
++ *				profile (rule)
++ * @num_extracts: Defines the number of valid entries in the array below
++ * @extracts: Array of required extractions
++ */
++struct dpkg_profile_cfg {
++	u8 num_extracts;
++	struct dpkg_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
++};
++
++#endif /* __FSL_DPKG_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpni-cmd.h
+@@ -0,0 +1,719 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef _FSL_DPNI_CMD_H
++#define _FSL_DPNI_CMD_H
++
++#include "dpni.h"
++
++/* DPNI Version */
++#define DPNI_VER_MAJOR				7
++#define DPNI_VER_MINOR				0
++#define DPNI_CMD_BASE_VERSION			1
++#define DPNI_CMD_2ND_VERSION			2
++#define DPNI_CMD_ID_OFFSET			4
++
++#define DPNI_CMD(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_BASE_VERSION)
++#define DPNI_CMD_V2(id)	(((id) << DPNI_CMD_ID_OFFSET) | DPNI_CMD_2ND_VERSION)
++
++#define DPNI_CMDID_OPEN					DPNI_CMD(0x801)
++#define DPNI_CMDID_CLOSE				DPNI_CMD(0x800)
++#define DPNI_CMDID_CREATE				DPNI_CMD(0x901)
++#define DPNI_CMDID_DESTROY				DPNI_CMD(0x900)
++#define DPNI_CMDID_GET_API_VERSION			DPNI_CMD(0xa01)
++
++#define DPNI_CMDID_ENABLE				DPNI_CMD(0x002)
++#define DPNI_CMDID_DISABLE				DPNI_CMD(0x003)
++#define DPNI_CMDID_GET_ATTR				DPNI_CMD(0x004)
++#define DPNI_CMDID_RESET				DPNI_CMD(0x005)
++#define DPNI_CMDID_IS_ENABLED				DPNI_CMD(0x006)
++
++#define DPNI_CMDID_SET_IRQ				DPNI_CMD(0x010)
++#define DPNI_CMDID_GET_IRQ				DPNI_CMD(0x011)
++#define DPNI_CMDID_SET_IRQ_ENABLE			DPNI_CMD(0x012)
++#define DPNI_CMDID_GET_IRQ_ENABLE			DPNI_CMD(0x013)
++#define DPNI_CMDID_SET_IRQ_MASK				DPNI_CMD(0x014)
++#define DPNI_CMDID_GET_IRQ_MASK				DPNI_CMD(0x015)
++#define DPNI_CMDID_GET_IRQ_STATUS			DPNI_CMD(0x016)
++#define DPNI_CMDID_CLEAR_IRQ_STATUS			DPNI_CMD(0x017)
++
++#define DPNI_CMDID_SET_POOLS				DPNI_CMD_V2(0x200)
++#define DPNI_CMDID_SET_ERRORS_BEHAVIOR			DPNI_CMD(0x20B)
++
++#define DPNI_CMDID_GET_QDID				DPNI_CMD(0x210)
++#define DPNI_CMDID_GET_TX_DATA_OFFSET			DPNI_CMD(0x212)
++#define DPNI_CMDID_GET_LINK_STATE			DPNI_CMD(0x215)
++#define DPNI_CMDID_SET_MAX_FRAME_LENGTH			DPNI_CMD(0x216)
++#define DPNI_CMDID_GET_MAX_FRAME_LENGTH			DPNI_CMD(0x217)
++#define DPNI_CMDID_SET_LINK_CFG				DPNI_CMD(0x21A)
++#define DPNI_CMDID_SET_TX_SHAPING			DPNI_CMD_V2(0x21B)
++
++#define DPNI_CMDID_SET_MCAST_PROMISC			DPNI_CMD(0x220)
++#define DPNI_CMDID_GET_MCAST_PROMISC			DPNI_CMD(0x221)
++#define DPNI_CMDID_SET_UNICAST_PROMISC			DPNI_CMD(0x222)
++#define DPNI_CMDID_GET_UNICAST_PROMISC			DPNI_CMD(0x223)
++#define DPNI_CMDID_SET_PRIM_MAC				DPNI_CMD(0x224)
++#define DPNI_CMDID_GET_PRIM_MAC				DPNI_CMD(0x225)
++#define DPNI_CMDID_ADD_MAC_ADDR				DPNI_CMD(0x226)
++#define DPNI_CMDID_REMOVE_MAC_ADDR			DPNI_CMD(0x227)
++#define DPNI_CMDID_CLR_MAC_FILTERS			DPNI_CMD(0x228)
++
++#define DPNI_CMDID_SET_RX_TC_DIST			DPNI_CMD(0x235)
++
++#define DPNI_CMDID_SET_QOS_TBL				DPNI_CMD(0x240)
++#define DPNI_CMDID_ADD_QOS_ENT				DPNI_CMD(0x241)
++#define DPNI_CMDID_REMOVE_QOS_ENT			DPNI_CMD(0x242)
++#define DPNI_CMDID_ADD_FS_ENT				DPNI_CMD(0x244)
++#define DPNI_CMDID_REMOVE_FS_ENT			DPNI_CMD(0x245)
++#define DPNI_CMDID_CLR_FS_ENT				DPNI_CMD(0x246)
++
++#define DPNI_CMDID_SET_TX_PRIORITIES			DPNI_CMD_V2(0x250)
++#define DPNI_CMDID_GET_STATISTICS			DPNI_CMD_V2(0x25D)
++#define DPNI_CMDID_RESET_STATISTICS			DPNI_CMD(0x25E)
++#define DPNI_CMDID_GET_QUEUE				DPNI_CMD(0x25F)
++#define DPNI_CMDID_SET_QUEUE				DPNI_CMD(0x260)
++#define DPNI_CMDID_GET_TAILDROP				DPNI_CMD(0x261)
++#define DPNI_CMDID_SET_TAILDROP				DPNI_CMD(0x262)
++
++#define DPNI_CMDID_GET_PORT_MAC_ADDR			DPNI_CMD(0x263)
++
++#define DPNI_CMDID_GET_BUFFER_LAYOUT			DPNI_CMD(0x264)
++#define DPNI_CMDID_SET_BUFFER_LAYOUT			DPNI_CMD(0x265)
++
++#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE		DPNI_CMD(0x266)
++#define DPNI_CMDID_SET_CONGESTION_NOTIFICATION		DPNI_CMD(0x267)
++#define DPNI_CMDID_GET_CONGESTION_NOTIFICATION		DPNI_CMD(0x268)
++#define DPNI_CMDID_SET_EARLY_DROP			DPNI_CMD(0x269)
++#define DPNI_CMDID_GET_EARLY_DROP			DPNI_CMD(0x26A)
++#define DPNI_CMDID_GET_OFFLOAD				DPNI_CMD(0x26B)
++#define DPNI_CMDID_SET_OFFLOAD				DPNI_CMD(0x26C)
++
++#define DPNI_CMDID_SET_RX_FS_DIST			DPNI_CMD(0x273)
++#define DPNI_CMDID_SET_RX_HASH_DIST			DPNI_CMD(0x274)
++
++/* Macros for accessing command fields smaller than 1byte */
++#define DPNI_MASK(field)	\
++	GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \
++		DPNI_##field##_SHIFT)
++
++#define dpni_set_field(var, field, val)	\
++	((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field)))
++#define dpni_get_field(var, field)	\
++	(((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT)
++
++struct dpni_cmd_open {
++	__le32 dpni_id;
++};
++
++#define DPNI_BACKUP_POOL(val, order)	(((val) & 0x1) << (order))
++struct dpni_cmd_set_pools {
++	u8 num_dpbp;
++	u8 backup_pool_mask;
++	__le16 pad;
++	struct {
++		__le16 dpbp_id;
++		u8 priority_mask;
++		u8 pad;
++	} pool[DPNI_MAX_DPBP];
++	__le16 buffer_size[DPNI_MAX_DPBP];
++};
++
++/* The enable indication is always the least significant bit */
++#define DPNI_ENABLE_SHIFT		0
++#define DPNI_ENABLE_SIZE		1
++
++struct dpni_rsp_is_enabled {
++	u8 enabled;
++};
++
++struct dpni_rsp_get_irq {
++	/* response word 0 */
++	__le32 irq_val;
++	__le32 pad;
++	/* response word 1 */
++	__le64 irq_addr;
++	/* response word 2 */
++	__le32 irq_num;
++	__le32 type;
++};
++
++struct dpni_cmd_set_irq_enable {
++	u8 enable;
++	u8 pad[3];
++	u8 irq_index;
++};
++
++struct dpni_cmd_get_irq_enable {
++	__le32 pad;
++	u8 irq_index;
++};
++
++struct dpni_rsp_get_irq_enable {
++	u8 enabled;
++};
++
++struct dpni_cmd_set_irq_mask {
++	__le32 mask;
++	u8 irq_index;
++};
++
++struct dpni_cmd_get_irq_mask {
++	__le32 pad;
++	u8 irq_index;
++};
++
++struct dpni_rsp_get_irq_mask {
++	__le32 mask;
++};
++
++struct dpni_cmd_get_irq_status {
++	__le32 status;
++	u8 irq_index;
++};
++
++struct dpni_rsp_get_irq_status {
++	__le32 status;
++};
++
++struct dpni_cmd_clear_irq_status {
++	__le32 status;
++	u8 irq_index;
++};
++
++struct dpni_rsp_get_attr {
++	/* response word 0 */
++	__le32 options;
++	u8 num_queues;
++	u8 num_tcs;
++	u8 mac_filter_entries;
++	u8 pad0;
++	/* response word 1 */
++	u8 vlan_filter_entries;
++	u8 pad1;
++	u8 qos_entries;
++	u8 pad2;
++	__le16 fs_entries;
++	__le16 pad3;
++	/* response word 2 */
++	u8 qos_key_size;
++	u8 fs_key_size;
++	__le16 wriop_version;
++};
++
++#define DPNI_ERROR_ACTION_SHIFT		0
++#define DPNI_ERROR_ACTION_SIZE		4
++#define DPNI_FRAME_ANN_SHIFT		4
++#define DPNI_FRAME_ANN_SIZE		1
++
++struct dpni_cmd_set_errors_behavior {
++	__le32 errors;
++	/* from least significant bit: error_action:4, set_frame_annotation:1 */
++	u8 flags;
++};
++
++/* There are 3 separate commands for configuring Rx, Tx and Tx confirmation
++ * buffer layouts, but they all share the same parameters.
++ * If one of the functions changes, below structure needs to be split.
++ */
++
++#define DPNI_PASS_TS_SHIFT		0
++#define DPNI_PASS_TS_SIZE		1
++#define DPNI_PASS_PR_SHIFT		1
++#define DPNI_PASS_PR_SIZE		1
++#define DPNI_PASS_FS_SHIFT		2
++#define DPNI_PASS_FS_SIZE		1
++
++struct dpni_cmd_get_buffer_layout {
++	u8 qtype;
++};
++
++struct dpni_rsp_get_buffer_layout {
++	/* response word 0 */
++	u8 pad0[6];
++	/* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
++	u8 flags;
++	u8 pad1;
++	/* response word 1 */
++	__le16 private_data_size;
++	__le16 data_align;
++	__le16 head_room;
++	__le16 tail_room;
++};
++
++struct dpni_cmd_set_buffer_layout {
++	/* cmd word 0 */
++	u8 qtype;
++	u8 pad0[3];
++	__le16 options;
++	/* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */
++	u8 flags;
++	u8 pad1;
++	/* cmd word 1 */
++	__le16 private_data_size;
++	__le16 data_align;
++	__le16 head_room;
++	__le16 tail_room;
++};
++
++struct dpni_cmd_set_offload {
++	u8 pad[3];
++	u8 dpni_offload;
++	__le32 config;
++};
++
++struct dpni_cmd_get_offload {
++	u8 pad[3];
++	u8 dpni_offload;
++};
++
++struct dpni_rsp_get_offload {
++	__le32 pad;
++	__le32 config;
++};
++
++struct dpni_cmd_get_qdid {
++	u8 qtype;
++};
++
++struct dpni_rsp_get_qdid {
++	__le16 qdid;
++};
++
++struct dpni_rsp_get_tx_data_offset {
++	__le16 data_offset;
++};
++
++struct dpni_cmd_get_statistics {
++	u8 page_number;
++	u8 param;
++};
++
++struct dpni_rsp_get_statistics {
++	__le64 counter[DPNI_STATISTICS_CNT];
++};
++
++struct dpni_cmd_set_link_cfg {
++	/* cmd word 0 */
++	__le64 pad0;
++	/* cmd word 1 */
++	__le32 rate;
++	__le32 pad1;
++	/* cmd word 2 */
++	__le64 options;
++};
++
++#define DPNI_LINK_STATE_SHIFT		0
++#define DPNI_LINK_STATE_SIZE		1
++
++struct dpni_rsp_get_link_state {
++	/* response word 0 */
++	__le32 pad0;
++	/* from LSB: up:1 */
++	u8 flags;
++	u8 pad1[3];
++	/* response word 1 */
++	__le32 rate;
++	__le32 pad2;
++	/* response word 2 */
++	__le64 options;
++};
++
++#define DPNI_COUPLED_SHIFT	0
++#define DPNI_COUPLED_SIZE	1
++
++struct dpni_cmd_set_tx_shaping {
++	/* cmd word 0 */
++	__le16 tx_cr_max_burst_size;
++	__le16 tx_er_max_burst_size;
++	__le32 pad;
++	/* cmd word 1 */
++	__le32 tx_cr_rate_limit;
++	__le32 tx_er_rate_limit;
++	/* cmd word 2 */
++	/* from LSB: coupled:1 */
++	u8 coupled;
++};
++
++struct dpni_cmd_set_max_frame_length {
++	__le16 max_frame_length;
++};
++
++struct dpni_rsp_get_max_frame_length {
++	__le16 max_frame_length;
++};
++
++struct dpni_cmd_set_multicast_promisc {
++	u8 enable;
++};
++
++struct dpni_rsp_get_multicast_promisc {
++	u8 enabled;
++};
++
++struct dpni_cmd_set_unicast_promisc {
++	u8 enable;
++};
++
++struct dpni_rsp_get_unicast_promisc {
++	u8 enabled;
++};
++
++struct dpni_cmd_set_primary_mac_addr {
++	__le16 pad;
++	u8 mac_addr[6];
++};
++
++struct dpni_rsp_get_primary_mac_addr {
++	__le16 pad;
++	u8 mac_addr[6];
++};
++
++struct dpni_rsp_get_port_mac_addr {
++	__le16 pad;
++	u8 mac_addr[6];
++};
++
++struct dpni_cmd_add_mac_addr {
++	__le16 pad;
++	u8 mac_addr[6];
++};
++
++struct dpni_cmd_remove_mac_addr {
++	__le16 pad;
++	u8 mac_addr[6];
++};
++
++#define DPNI_UNICAST_FILTERS_SHIFT	0
++#define DPNI_UNICAST_FILTERS_SIZE	1
++#define DPNI_MULTICAST_FILTERS_SHIFT	1
++#define DPNI_MULTICAST_FILTERS_SIZE	1
++
++struct dpni_cmd_clear_mac_filters {
++	/* from LSB: unicast:1, multicast:1 */
++	u8 flags;
++};
++
++#define DPNI_SEPARATE_GRP_SHIFT 0
++#define DPNI_SEPARATE_GRP_SIZE  1
++#define DPNI_MODE_1_SHIFT		0
++#define DPNI_MODE_1_SIZE		4
++#define DPNI_MODE_2_SHIFT		4
++#define DPNI_MODE_2_SIZE		4
++
++struct dpni_cmd_set_tx_priorities {
++	__le16 flags;
++	u8 prio_group_A;
++	u8 prio_group_B;
++	__le32 pad0;
++	u8 modes[4];
++	__le32 pad1;
++	__le64 pad2;
++	__le16 delta_bandwidth[8];
++};
++
++#define DPNI_DIST_MODE_SHIFT		0
++#define DPNI_DIST_MODE_SIZE		4
++#define DPNI_MISS_ACTION_SHIFT		4
++#define DPNI_MISS_ACTION_SIZE		4
++
++struct dpni_cmd_set_rx_tc_dist {
++	/* cmd word 0 */
++	__le16 dist_size;
++	u8 tc_id;
++	/* from LSB: dist_mode:4, miss_action:4 */
++	u8 flags;
++	__le16 pad0;
++	__le16 default_flow_id;
++	/* cmd word 1..5 */
++	__le64 pad1[5];
++	/* cmd word 6 */
++	__le64 key_cfg_iova;
++};
++
++/* dpni_set_rx_tc_dist extension (structure of the DMA-able memory at
++ * key_cfg_iova)
++ */
++struct dpni_mask_cfg {
++	u8 mask;
++	u8 offset;
++};
++
++#define DPNI_EFH_TYPE_SHIFT		0
++#define DPNI_EFH_TYPE_SIZE		4
++#define DPNI_EXTRACT_TYPE_SHIFT		0
++#define DPNI_EXTRACT_TYPE_SIZE		4
++
++struct dpni_dist_extract {
++	/* word 0 */
++	u8 prot;
++	/* EFH type stored in the 4 least significant bits */
++	u8 efh_type;
++	u8 size;
++	u8 offset;
++	__le32 field;
++	/* word 1 */
++	u8 hdr_index;
++	u8 constant;
++	u8 num_of_repeats;
++	u8 num_of_byte_masks;
++	/* Extraction type is stored in the 4 LSBs */
++	u8 extract_type;
++	u8 pad[3];
++	/* word 2 */
++	struct dpni_mask_cfg masks[4];
++};
++
++struct dpni_ext_set_rx_tc_dist {
++	/* extension word 0 */
++	u8 num_extracts;
++	u8 pad[7];
++	/* words 1..25 */
++	struct dpni_dist_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
++};
++
++struct dpni_cmd_get_queue {
++	u8 qtype;
++	u8 tc;
++	u8 index;
++};
++
++#define DPNI_DEST_TYPE_SHIFT		0
++#define DPNI_DEST_TYPE_SIZE		4
++#define DPNI_STASH_CTRL_SHIFT		6
++#define DPNI_STASH_CTRL_SIZE		1
++#define DPNI_HOLD_ACTIVE_SHIFT		7
++#define DPNI_HOLD_ACTIVE_SIZE		1
++
++struct dpni_rsp_get_queue {
++	/* response word 0 */
++	__le64 pad0;
++	/* response word 1 */
++	__le32 dest_id;
++	__le16 pad1;
++	u8 dest_prio;
++	/* From LSB: dest_type:4, pad:2, flc_stash_ctrl:1, hold_active:1 */
++	u8 flags;
++	/* response word 2 */
++	__le64 flc;
++	/* response word 3 */
++	__le64 user_context;
++	/* response word 4 */
++	__le32 fqid;
++	__le16 qdbin;
++};
++
++struct dpni_cmd_set_queue {
++	/* cmd word 0 */
++	u8 qtype;
++	u8 tc;
++	u8 index;
++	u8 options;
++	__le32 pad0;
++	/* cmd word 1 */
++	__le32 dest_id;
++	__le16 pad1;
++	u8 dest_prio;
++	u8 flags;
++	/* cmd word 2 */
++	__le64 flc;
++	/* cmd word 3 */
++	__le64 user_context;
++};
++
++#define DPNI_DISCARD_ON_MISS_SHIFT	0
++#define DPNI_DISCARD_ON_MISS_SIZE	1
++
++struct dpni_cmd_set_qos_table {
++	__le32 pad;
++	u8 default_tc;
++	/* only the LSB */
++	u8 discard_on_miss;
++	__le16 pad1[21];
++	__le64 key_cfg_iova;
++};
++
++struct dpni_cmd_add_qos_entry {
++	__le16 pad;
++	u8 tc_id;
++	u8 key_size;
++	__le16 index;
++	__le16 pad2;
++	__le64 key_iova;
++	__le64 mask_iova;
++};
++
++struct dpni_cmd_remove_qos_entry {
++	u8 pad1[3];
++	u8 key_size;
++	__le32 pad2;
++	__le64 key_iova;
++	__le64 mask_iova;
++};
++
++struct dpni_cmd_add_fs_entry {
++	/* cmd word 0 */
++	__le16 options;
++	u8 tc_id;
++	u8 key_size;
++	__le16 index;
++	__le16 flow_id;
++	/* cmd word 1 */
++	__le64 key_iova;
++	/* cmd word 2 */
++	__le64 mask_iova;
++	/* cmd word 3 */
++	__le64 flc;
++};
++
++struct dpni_cmd_remove_fs_entry {
++	/* cmd word 0 */
++	__le16 pad0;
++	u8 tc_id;
++	u8 key_size;
++	__le32 pad1;
++	/* cmd word 1 */
++	__le64 key_iova;
++	/* cmd word 2 */
++	__le64 mask_iova;
++};
++
++struct dpni_cmd_set_taildrop {
++	/* cmd word 0 */
++	u8 congestion_point;
++	u8 qtype;
++	u8 tc;
++	u8 index;
++	__le32 pad0;
++	/* cmd word 1 */
++	/* Only least significant bit is relevant */
++	u8 enable;
++	u8 pad1;
++	u8 units;
++	u8 pad2;
++	__le32 threshold;
++};
++
++struct dpni_cmd_get_taildrop {
++	u8 congestion_point;
++	u8 qtype;
++	u8 tc;
++	u8 index;
++};
++
++struct dpni_rsp_get_taildrop {
++	/* cmd word 0 */
++	__le64 pad0;
++	/* cmd word 1 */
++	/* only least significant bit is relevant */
++	u8 enable;
++	u8 pad1;
++	u8 units;
++	u8 pad2;
++	__le32 threshold;
++};
++
++struct dpni_rsp_get_api_version {
++	u16 major;
++	u16 minor;
++};
++
++#define DPNI_DEST_TYPE_SHIFT		0
++#define DPNI_DEST_TYPE_SIZE		4
++#define DPNI_CONG_UNITS_SHIFT		4
++#define DPNI_CONG_UNITS_SIZE		2
++
++struct dpni_cmd_set_congestion_notification {
++	/* cmd word 0 */
++	u8 qtype;
++	u8 tc;
++	u8 pad[6];
++	/* cmd word 1 */
++	__le32 dest_id;
++	__le16 notification_mode;
++	u8 dest_priority;
++	/* from LSB: dest_type: 4 units:2 */
++	u8 type_units;
++	/* cmd word 2 */
++	__le64 message_iova;
++	/* cmd word 3 */
++	__le64 message_ctx;
++	/* cmd word 4 */
++	__le32 threshold_entry;
++	__le32 threshold_exit;
++};
++
++struct dpni_cmd_get_congestion_notification {
++	/* cmd word 0 */
++	u8 qtype;
++	u8 tc;
++};
++
++struct dpni_rsp_get_congestion_notification {
++	/* cmd word 0 */
++	__le64 pad;
++	/* cmd word 1 */
++	__le32 dest_id;
++	__le16 notification_mode;
++	u8 dest_priority;
++	/* from LSB: dest_type: 4 units:2 */
++	u8 type_units;
++	/* cmd word 2 */
++	__le64 message_iova;
++	/* cmd word 3 */
++	__le64 message_ctx;
++	/* cmd word 4 */
++	__le32 threshold_entry;
++	__le32 threshold_exit;
++};
++
++#define DPNI_RX_FS_DIST_ENABLE_SHIFT	0
++#define DPNI_RX_FS_DIST_ENABLE_SIZE	1
++struct dpni_cmd_set_rx_fs_dist {
++	__le16 dist_size;
++	u8 enable;
++	u8 tc;
++	__le16 miss_flow_id;
++	__le16 pad;
++	__le64 key_cfg_iova;
++};
++
++#define DPNI_RX_HASH_DIST_ENABLE_SHIFT	0
++#define DPNI_RX_HASH_DIST_ENABLE_SIZE	1
++struct dpni_cmd_set_rx_hash_dist {
++	__le16 dist_size;
++	u8 enable;
++	u8 tc;
++	__le32 pad;
++	__le64 key_cfg_iova;
++};
++
++#endif /* _FSL_DPNI_CMD_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c
+@@ -0,0 +1,2112 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/fsl/mc.h>
++#include "dpni.h"
++#include "dpni-cmd.h"
++
++/**
++ * dpni_prepare_key_cfg() - function prepare extract parameters
++ * @cfg: defining a full Key Generation profile (rule)
++ * @key_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
++ *
++ * This function has to be called before the following functions:
++ *	- dpni_set_rx_tc_dist()
++ *	- dpni_set_qos_table()
++ */
++int dpni_prepare_key_cfg(const struct dpkg_profile_cfg *cfg, u8 *key_cfg_buf)
++{
++	int i, j;
++	struct dpni_ext_set_rx_tc_dist *dpni_ext;
++	struct dpni_dist_extract *extr;
++
++	if (cfg->num_extracts > DPKG_MAX_NUM_OF_EXTRACTS)
++		return -EINVAL;
++
++	dpni_ext = (struct dpni_ext_set_rx_tc_dist *)key_cfg_buf;
++	dpni_ext->num_extracts = cfg->num_extracts;
++
++	for (i = 0; i < cfg->num_extracts; i++) {
++		extr = &dpni_ext->extracts[i];
++
++		switch (cfg->extracts[i].type) {
++		case DPKG_EXTRACT_FROM_HDR:
++			extr->prot = cfg->extracts[i].extract.from_hdr.prot;
++			dpni_set_field(extr->efh_type, EFH_TYPE,
++				       cfg->extracts[i].extract.from_hdr.type);
++			extr->size = cfg->extracts[i].extract.from_hdr.size;
++			extr->offset = cfg->extracts[i].extract.from_hdr.offset;
++			extr->field = cpu_to_le32(
++				cfg->extracts[i].extract.from_hdr.field);
++			extr->hdr_index =
++				cfg->extracts[i].extract.from_hdr.hdr_index;
++			break;
++		case DPKG_EXTRACT_FROM_DATA:
++			extr->size = cfg->extracts[i].extract.from_data.size;
++			extr->offset =
++				cfg->extracts[i].extract.from_data.offset;
++			break;
++		case DPKG_EXTRACT_FROM_PARSE:
++			extr->size = cfg->extracts[i].extract.from_parse.size;
++			extr->offset =
++				cfg->extracts[i].extract.from_parse.offset;
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		extr->num_of_byte_masks = cfg->extracts[i].num_of_byte_masks;
++		dpni_set_field(extr->extract_type, EXTRACT_TYPE,
++			       cfg->extracts[i].type);
++
++		for (j = 0; j < DPKG_NUM_OF_MASKS; j++) {
++			extr->masks[j].mask = cfg->extracts[i].masks[j].mask;
++			extr->masks[j].offset =
++				cfg->extracts[i].masks[j].offset;
++		}
++	}
++
++	return 0;
++}
++
++/**
++ * dpni_open() - Open a control session for the specified object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @dpni_id:	DPNI unique ID
++ * @token:	Returned token; use in subsequent API calls
++ *
++ * This function can be used to open a control session for an
++ * already created object; an object may have been declared in
++ * the DPL or by calling the dpni_create() function.
++ * This function returns a unique authentication token,
++ * associated with the specific object ID and the specific MC
++ * portal; this token must be used in all subsequent commands for
++ * this specific object.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_open(struct fsl_mc_io *mc_io,
++	      u32 cmd_flags,
++	      int dpni_id,
++	      u16 *token)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_open *cmd_params;
++
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN,
++					  cmd_flags,
++					  0);
++	cmd_params = (struct dpni_cmd_open *)cmd.params;
++	cmd_params->dpni_id = cpu_to_le32(dpni_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*token = mc_cmd_hdr_read_token(&cmd);
++
++	return 0;
++}
++
++/**
++ * dpni_close() - Close the control session of the object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ *
++ * After this function is called, no further operations are
++ * allowed on the object without opening a new control session.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_close(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLOSE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_pools() - Set buffer pools configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg:	Buffer pools configuration
++ *
++ * mandatory for DPNI operation
++ * warning:Allowed only when DPNI is disabled
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_pools(struct fsl_mc_io *mc_io,
++		   u32 cmd_flags,
++		   u16 token,
++		   const struct dpni_pools_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_pools *cmd_params;
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_pools *)cmd.params;
++	cmd_params->num_dpbp = cfg->num_dpbp;
++	for (i = 0; i < DPNI_MAX_DPBP; i++) {
++		cmd_params->pool[i].dpbp_id =
++			cpu_to_le16(cfg->pools[i].dpbp_id);
++		cmd_params->pool[i].priority_mask =
++			cfg->pools[i].priority_mask;
++		cmd_params->buffer_size[i] =
++			cpu_to_le16(cfg->pools[i].buffer_size);
++		cmd_params->backup_pool_mask |=
++			DPNI_BACKUP_POOL(cfg->pools[i].backup_pool, i);
++	}
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_enable() - Enable the DPNI, allow sending and receiving frames.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:		Token of DPNI object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_enable(struct fsl_mc_io *mc_io,
++		u32 cmd_flags,
++		u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_disable() - Disable the DPNI, stop sending and receiving frames.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_disable(struct fsl_mc_io *mc_io,
++		 u32 cmd_flags,
++		 u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_DISABLE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_is_enabled() - Check if the DPNI is enabled.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @en:		Returns '1' if object is enabled; '0' otherwise
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_is_enabled(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    int *en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_is_enabled *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_IS_ENABLED,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_is_enabled *)cmd.params;
++	*en = dpni_get_field(rsp_params->enabled, ENABLE);
++
++	return 0;
++}
++
++/**
++ * dpni_reset() - Reset the DPNI, returns the object to initial state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_reset(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_irq_enable() - Set overall interrupt state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Interrupt state: - enable = 1, disable = 0
++ *
++ * Allows GPP software to control when interrupts are generated.
++ * Each interrupt can have up to 32 causes.  The enable/disable control's the
++ * overall interrupt state. if the interrupt is disabled no causes will cause
++ * an interrupt.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_irq_enable(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u8 en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_irq_enable *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_irq_enable *)cmd.params;
++	dpni_set_field(cmd_params->enable, ENABLE, en);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_irq_enable() - Get overall interrupt state
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Returned interrupt state - enable = 1, disable = 0
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_irq_enable(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u8 *en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_irq_enable *cmd_params;
++	struct dpni_rsp_get_irq_enable *rsp_params;
++
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_irq_enable *)cmd.params;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_irq_enable *)cmd.params;
++	*en = dpni_get_field(rsp_params->enabled, ENABLE);
++
++	return 0;
++}
++
++/**
++ * dpni_set_irq_mask() - Set interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	event mask to trigger interrupt;
++ *			each bit:
++ *				0 = ignore event
++ *				1 = consider event for asserting IRQ
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_irq_mask(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      u8 irq_index,
++		      u32 mask)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_irq_mask *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_irq_mask *)cmd.params;
++	cmd_params->mask = cpu_to_le32(mask);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_irq_mask() - Get interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	Returned event mask to trigger interrupt
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_irq_mask(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      u8 irq_index,
++		      u32 *mask)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_irq_mask *cmd_params;
++	struct dpni_rsp_get_irq_mask *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_irq_mask *)cmd.params;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_irq_mask *)cmd.params;
++	*mask = le32_to_cpu(rsp_params->mask);
++
++	return 0;
++}
++
++/**
++ * dpni_get_irq_status() - Get the current status of any pending interrupts.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @irq_index:	The interrupt index to configure
++ * @status:	Returned interrupts status - one bit per cause:
++ *			0 = no interrupt pending
++ *			1 = interrupt pending
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_irq_status(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u32 *status)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_irq_status *cmd_params;
++	struct dpni_rsp_get_irq_status *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(*status);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_irq_status *)cmd.params;
++	*status = le32_to_cpu(rsp_params->status);
++
++	return 0;
++}
++
++/**
++ * dpni_clear_irq_status() - Clear a pending interrupt's status
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @irq_index:	The interrupt index to configure
++ * @status:	bits to clear (W1C) - one bit per cause:
++ *			0 = don't change
++ *			1 = clear status bit
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_clear_irq_status(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u32 status)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_clear_irq_status *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLEAR_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_clear_irq_status *)cmd.params;
++	cmd_params->irq_index = irq_index;
++	cmd_params->status = cpu_to_le32(status);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_attributes() - Retrieve DPNI attributes.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @attr:	Object's attributes
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_attributes(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			struct dpni_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_get_attr *rsp_params;
++
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_attr *)cmd.params;
++	attr->options = le32_to_cpu(rsp_params->options);
++	attr->num_queues = rsp_params->num_queues;
++	attr->num_tcs = rsp_params->num_tcs;
++	attr->mac_filter_entries = rsp_params->mac_filter_entries;
++	attr->vlan_filter_entries = rsp_params->vlan_filter_entries;
++	attr->qos_entries = rsp_params->qos_entries;
++	attr->fs_entries = le16_to_cpu(rsp_params->fs_entries);
++	attr->qos_key_size = rsp_params->qos_key_size;
++	attr->fs_key_size = rsp_params->fs_key_size;
++	attr->wriop_version = le16_to_cpu(rsp_params->wriop_version);
++
++	return 0;
++}
++
++/**
++ * dpni_set_errors_behavior() - Set errors behavior
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg:	Errors configuration
++ *
++ * this function may be called numerous times with different
++ * error masks
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     struct dpni_error_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_errors_behavior *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_errors_behavior *)cmd.params;
++	cmd_params->errors = cpu_to_le32(cfg->errors);
++	dpni_set_field(cmd_params->flags, ERROR_ACTION, cfg->error_action);
++	dpni_set_field(cmd_params->flags, FRAME_ANN, cfg->set_frame_annotation);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_buffer_layout() - Retrieve buffer layout attributes.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @qtype:	Type of queue to retrieve configuration for
++ * @layout:	Returns buffer layout attributes
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_buffer_layout(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   enum dpni_queue_type qtype,
++			   struct dpni_buffer_layout *layout)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_buffer_layout *cmd_params;
++	struct dpni_rsp_get_buffer_layout *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_BUFFER_LAYOUT,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_buffer_layout *)cmd.params;
++	cmd_params->qtype = qtype;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_buffer_layout *)cmd.params;
++	layout->pass_timestamp = dpni_get_field(rsp_params->flags, PASS_TS);
++	layout->pass_parser_result = dpni_get_field(rsp_params->flags, PASS_PR);
++	layout->pass_frame_status = dpni_get_field(rsp_params->flags, PASS_FS);
++	layout->private_data_size = le16_to_cpu(rsp_params->private_data_size);
++	layout->data_align = le16_to_cpu(rsp_params->data_align);
++	layout->data_head_room = le16_to_cpu(rsp_params->head_room);
++	layout->data_tail_room = le16_to_cpu(rsp_params->tail_room);
++
++	return 0;
++}
++
++/**
++ * dpni_set_buffer_layout() - Set buffer layout configuration.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @qtype:	Type of queue this configuration applies to
++ * @layout:	Buffer layout configuration
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ *
++ * @warning	Allowed only when DPNI is disabled
++ */
++int dpni_set_buffer_layout(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   enum dpni_queue_type qtype,
++			   const struct dpni_buffer_layout *layout)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_buffer_layout *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_BUFFER_LAYOUT,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_buffer_layout *)cmd.params;
++	cmd_params->qtype = qtype;
++	cmd_params->options = cpu_to_le16(layout->options);
++	dpni_set_field(cmd_params->flags, PASS_TS, layout->pass_timestamp);
++	dpni_set_field(cmd_params->flags, PASS_PR, layout->pass_parser_result);
++	dpni_set_field(cmd_params->flags, PASS_FS, layout->pass_frame_status);
++	cmd_params->private_data_size = cpu_to_le16(layout->private_data_size);
++	cmd_params->data_align = cpu_to_le16(layout->data_align);
++	cmd_params->head_room = cpu_to_le16(layout->data_head_room);
++	cmd_params->tail_room = cpu_to_le16(layout->data_tail_room);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_offload() - Set DPNI offload configuration.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @type:	Type of DPNI offload
++ * @config:	Offload configuration.
++ *		For checksum offloads, non-zero value enables the offload
++ *
++ * Return:     '0' on Success; Error code otherwise.
++ *
++ * @warning    Allowed only when DPNI is disabled
++ */
++
++int dpni_set_offload(struct fsl_mc_io *mc_io,
++		     u32 cmd_flags,
++		     u16 token,
++		     enum dpni_offload type,
++		     u32 config)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_offload *cmd_params;
++
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_OFFLOAD,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_offload *)cmd.params;
++	cmd_params->dpni_offload = type;
++	cmd_params->config = cpu_to_le32(config);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++int dpni_get_offload(struct fsl_mc_io *mc_io,
++		     u32 cmd_flags,
++		     u16 token,
++		     enum dpni_offload type,
++		     u32 *config)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_offload *cmd_params;
++	struct dpni_rsp_get_offload *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_OFFLOAD,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_offload *)cmd.params;
++	cmd_params->dpni_offload = type;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_offload *)cmd.params;
++	*config = le32_to_cpu(rsp_params->config);
++
++	return 0;
++}
++
++/**
++ * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used
++ *			for enqueue operations
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @qtype:	Type of queue to receive QDID for
++ * @qdid:	Returned virtual QDID value that should be used as an argument
++ *			in all enqueue operations
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_qdid(struct fsl_mc_io *mc_io,
++		  u32 cmd_flags,
++		  u16 token,
++		  enum dpni_queue_type qtype,
++		  u16 *qdid)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_qdid *cmd_params;
++	struct dpni_rsp_get_qdid *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_qdid *)cmd.params;
++	cmd_params->qtype = qtype;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_qdid *)cmd.params;
++	*qdid = le16_to_cpu(rsp_params->qdid);
++
++	return 0;
++}
++
++/**
++ * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer)
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @data_offset: Tx data offset (from start of buffer)
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    u16 *data_offset)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_get_tx_data_offset *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TX_DATA_OFFSET,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_tx_data_offset *)cmd.params;
++	*data_offset = le16_to_cpu(rsp_params->data_offset);
++
++	return 0;
++}
++
++/**
++ * dpni_set_link_cfg() - set the link configuration.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg:	Link configuration
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_link_cfg(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      const struct dpni_link_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_link_cfg *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_LINK_CFG,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_link_cfg *)cmd.params;
++	cmd_params->rate = cpu_to_le32(cfg->rate);
++	cmd_params->options = cpu_to_le64(cfg->options);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_link_state() - Return the link state (either up or down)
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @state:	Returned link state;
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_link_state(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			struct dpni_link_state *state)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_get_link_state *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_LINK_STATE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_link_state *)cmd.params;
++	state->up = dpni_get_field(rsp_params->flags, LINK_STATE);
++	state->rate = le32_to_cpu(rsp_params->rate);
++	state->options = le64_to_cpu(rsp_params->options);
++
++	return 0;
++}
++
++/**
++ * dpni_set_tx_shaping() - Set the transmit shaping
++ * @mc_io:		Pointer to MC portal's I/O object
++ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:		Token of DPNI object
++ * @tx_cr_shaper:	TX committed rate shaping configuration
++ * @tx_er_shaper:	TX excess rate shaping configuration
++ * @coupled:		Committed and excess rate shapers are coupled
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_tx_shaping(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			const struct dpni_tx_shaping_cfg *tx_cr_shaper,
++			const struct dpni_tx_shaping_cfg *tx_er_shaper,
++			int coupled)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_tx_shaping *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_SHAPING,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_tx_shaping *)cmd.params;
++	cmd_params->tx_cr_max_burst_size =
++				cpu_to_le16(tx_cr_shaper->max_burst_size);
++	cmd_params->tx_er_max_burst_size =
++				cpu_to_le16(tx_er_shaper->max_burst_size);
++	cmd_params->tx_cr_rate_limit = cpu_to_le32(tx_cr_shaper->rate_limit);
++	cmd_params->tx_er_rate_limit = cpu_to_le32(tx_er_shaper->rate_limit);
++	dpni_set_field(cmd_params->coupled, COUPLED, coupled);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_max_frame_length() - Set the maximum received frame length.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @max_frame_length:	Maximum received frame length (in
++ *				bytes); frame is discarded if its
++ *				length exceeds this value
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_max_frame_length(struct fsl_mc_io *mc_io,
++			      u32 cmd_flags,
++			      u16 token,
++			      u16 max_frame_length)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_max_frame_length *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MAX_FRAME_LENGTH,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_max_frame_length *)cmd.params;
++	cmd_params->max_frame_length = cpu_to_le16(max_frame_length);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_max_frame_length() - Get the maximum received frame length.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @max_frame_length:	Maximum received frame length (in
++ *				bytes); frame is discarded if its
++ *				length exceeds this value
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_max_frame_length(struct fsl_mc_io *mc_io,
++			      u32 cmd_flags,
++			      u16 token,
++			      u16 *max_frame_length)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_get_max_frame_length *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MAX_FRAME_LENGTH,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_max_frame_length *)cmd.params;
++	*max_frame_length = le16_to_cpu(rsp_params->max_frame_length);
++
++	return 0;
++}
++
++/**
++ * dpni_set_multicast_promisc() - Enable/disable multicast promiscuous mode
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @en:		Set to '1' to enable; '0' to disable
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_multicast_promisc(struct fsl_mc_io *mc_io,
++			       u32 cmd_flags,
++			       u16 token,
++			       int en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_multicast_promisc *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MCAST_PROMISC,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_multicast_promisc *)cmd.params;
++	dpni_set_field(cmd_params->enable, ENABLE, en);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_multicast_promisc() - Get multicast promiscuous mode
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @en:		Returns '1' if enabled; '0' otherwise
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_multicast_promisc(struct fsl_mc_io *mc_io,
++			       u32 cmd_flags,
++			       u16 token,
++			       int *en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_get_multicast_promisc *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MCAST_PROMISC,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_multicast_promisc *)cmd.params;
++	*en = dpni_get_field(rsp_params->enabled, ENABLE);
++
++	return 0;
++}
++
++/**
++ * dpni_set_unicast_promisc() - Enable/disable unicast promiscuous mode
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @en:		Set to '1' to enable; '0' to disable
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_unicast_promisc(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     int en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_unicast_promisc *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_UNICAST_PROMISC,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_unicast_promisc *)cmd.params;
++	dpni_set_field(cmd_params->enable, ENABLE, en);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_unicast_promisc() - Get unicast promiscuous mode
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @en:		Returns '1' if enabled; '0' otherwise
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_unicast_promisc(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     int *en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_get_unicast_promisc *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_UNICAST_PROMISC,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_unicast_promisc *)cmd.params;
++	*en = dpni_get_field(rsp_params->enabled, ENABLE);
++
++	return 0;
++}
++
++/**
++ * dpni_set_primary_mac_addr() - Set the primary MAC address
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @mac_addr:	MAC address to set as primary address
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
++			      u32 cmd_flags,
++			      u16 token,
++			      const u8 mac_addr[6])
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_primary_mac_addr *cmd_params;
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_primary_mac_addr *)cmd.params;
++	for (i = 0; i < 6; i++)
++		cmd_params->mac_addr[i] = mac_addr[5 - i];
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_primary_mac_addr() - Get the primary MAC address
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @mac_addr:	Returned MAC address
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io,
++			      u32 cmd_flags,
++			      u16 token,
++			      u8 mac_addr[6])
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_get_primary_mac_addr *rsp_params;
++	int i, err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_primary_mac_addr *)cmd.params;
++	for (i = 0; i < 6; i++)
++		mac_addr[5 - i] = rsp_params->mac_addr[i];
++
++	return 0;
++}
++
++/**
++ * dpni_get_port_mac_addr() - Retrieve MAC address associated to the physical
++ *			port the DPNI is attached to
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @mac_addr:	MAC address of the physical port, if any, otherwise 0
++ *
++ * The primary MAC address is not cleared by this operation.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_port_mac_addr(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u8 mac_addr[6])
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_rsp_get_port_mac_addr *rsp_params;
++	int i, err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PORT_MAC_ADDR,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_port_mac_addr *)cmd.params;
++	for (i = 0; i < 6; i++)
++		mac_addr[5 - i] = rsp_params->mac_addr[i];
++
++	return 0;
++}
++
++/**
++ * dpni_add_mac_addr() - Add MAC address filter
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @mac_addr:	MAC address to add
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_add_mac_addr(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      const u8 mac_addr[6])
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_add_mac_addr *cmd_params;
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_MAC_ADDR,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_add_mac_addr *)cmd.params;
++	for (i = 0; i < 6; i++)
++		cmd_params->mac_addr[i] = mac_addr[5 - i];
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_remove_mac_addr() - Remove MAC address filter
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @mac_addr:	MAC address to remove
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_remove_mac_addr(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 const u8 mac_addr[6])
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_remove_mac_addr *cmd_params;
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_MAC_ADDR,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_remove_mac_addr *)cmd.params;
++	for (i = 0; i < 6; i++)
++		cmd_params->mac_addr[i] = mac_addr[5 - i];
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_clear_mac_filters() - Clear all unicast and/or multicast MAC filters
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @unicast:	Set to '1' to clear unicast addresses
++ * @multicast:	Set to '1' to clear multicast addresses
++ *
++ * The primary MAC address is not cleared by this operation.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_clear_mac_filters(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   int unicast,
++			   int multicast)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_clear_mac_filters *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLR_MAC_FILTERS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_clear_mac_filters *)cmd.params;
++	dpni_set_field(cmd_params->flags, UNICAST_FILTERS, unicast);
++	dpni_set_field(cmd_params->flags, MULTICAST_FILTERS, multicast);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_tx_priorities() - Set transmission TC priority configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg:	Transmission selection configuration
++ *
++ * warning:	Allowed only when DPNI is disabled
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_tx_priorities(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   const struct dpni_tx_priorities_cfg *cfg)
++{
++	struct dpni_cmd_set_tx_priorities *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_PRIORITIES,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_tx_priorities *)cmd.params;
++	dpni_set_field(cmd_params->flags,
++		       SEPARATE_GRP,
++		       cfg->separate_groups);
++	cmd_params->prio_group_A = cfg->prio_group_A;
++	cmd_params->prio_group_B = cfg->prio_group_B;
++
++	for (i = 0; i + 1 < DPNI_MAX_TC; i += 2) {
++		dpni_set_field(cmd_params->modes[i / 2],
++			       MODE_1,
++			       cfg->tc_sched[i].mode);
++		dpni_set_field(cmd_params->modes[i / 2],
++			       MODE_2,
++			       cfg->tc_sched[i + 1].mode);
++	}
++
++	for (i = 0; i < DPNI_MAX_TC; i++) {
++		cmd_params->delta_bandwidth[i] =
++				cpu_to_le16(cfg->tc_sched[i].delta_bandwidth);
++	}
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_rx_tc_dist() - Set Rx traffic class distribution configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @tc_id:	Traffic class selection (0-7)
++ * @cfg:	Traffic class distribution configuration
++ *
++ * warning: if 'dist_mode != DPNI_DIST_MODE_NONE', call dpni_prepare_key_cfg()
++ *			first to prepare the key_cfg_iova parameter
++ *
++ * Return:	'0' on Success; error code otherwise.
++ */
++int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 tc_id,
++			const struct dpni_rx_tc_dist_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_rx_tc_dist *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_TC_DIST,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_rx_tc_dist *)cmd.params;
++	cmd_params->dist_size = cpu_to_le16(cfg->dist_size);
++	cmd_params->tc_id = tc_id;
++	dpni_set_field(cmd_params->flags, DIST_MODE, cfg->dist_mode);
++	dpni_set_field(cmd_params->flags, MISS_ACTION, cfg->fs_cfg.miss_action);
++	cmd_params->default_flow_id = cpu_to_le16(cfg->fs_cfg.default_flow_id);
++	cmd_params->key_cfg_iova = cpu_to_le64(cfg->key_cfg_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/*
++ * dpni_set_qos_table() - Set QoS mapping table
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg:	QoS table configuration
++ *
++ * This function and all QoS-related functions require that
++ *'max_tcs > 1' was set at DPNI creation.
++ *
++ * warning: Before calling this function, call dpkg_prepare_key_cfg() to
++ *			prepare the key_cfg_iova parameter
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_qos_table(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       const struct dpni_qos_tbl_cfg *cfg)
++{
++	struct dpni_cmd_set_qos_table *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QOS_TBL,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_qos_table *)cmd.params;
++	cmd_params->default_tc = cfg->default_tc;
++	cmd_params->key_cfg_iova = cpu_to_le64(cfg->key_cfg_iova);
++	dpni_set_field(cmd_params->discard_on_miss,
++		       ENABLE,
++		       cfg->discard_on_miss);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_add_qos_entry() - Add QoS mapping entry (to select a traffic class)
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg:	QoS rule to add
++ * @tc_id:	Traffic class selection (0-7)
++ * @index:	Location in the QoS table where to insert the entry.
++ *		Only relevant if MASKING is enabled for QoS classification on
++ *		this DPNI, it is ignored for exact match.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_add_qos_entry(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       const struct dpni_rule_cfg *cfg,
++		       u8 tc_id,
++		       u16 index)
++{
++	struct dpni_cmd_add_qos_entry *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_QOS_ENT,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_add_qos_entry *)cmd.params;
++	cmd_params->tc_id = tc_id;
++	cmd_params->key_size = cfg->key_size;
++	cmd_params->index = cpu_to_le16(index);
++	cmd_params->key_iova = cpu_to_le64(cfg->key_iova);
++	cmd_params->mask_iova = cpu_to_le64(cfg->mask_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_remove_qos_entry() - Remove QoS mapping entry
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg:	QoS rule to remove
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_remove_qos_entry(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  const struct dpni_rule_cfg *cfg)
++{
++	struct dpni_cmd_remove_qos_entry *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_QOS_ENT,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_remove_qos_entry *)cmd.params;
++	cmd_params->key_size = cfg->key_size;
++	cmd_params->key_iova = cpu_to_le64(cfg->key_iova);
++	cmd_params->mask_iova = cpu_to_le64(cfg->mask_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_add_fs_entry() - Add Flow Steering entry for a specific traffic class
++ *			(to select a flow ID)
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @tc_id:	Traffic class selection (0-7)
++ * @index:	Location in the QoS table where to insert the entry.
++ *		Only relevant if MASKING is enabled for QoS
++ *		classification on this DPNI, it is ignored for exact match.
++ * @cfg:	Flow steering rule to add
++ * @action:	Action to be taken as result of a classification hit
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_add_fs_entry(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      u8 tc_id,
++		      u16 index,
++		      const struct dpni_rule_cfg *cfg,
++		      const struct dpni_fs_action_cfg *action)
++{
++	struct dpni_cmd_add_fs_entry *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_FS_ENT,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_add_fs_entry *)cmd.params;
++	cmd_params->tc_id = tc_id;
++	cmd_params->key_size = cfg->key_size;
++	cmd_params->index = cpu_to_le16(index);
++	cmd_params->key_iova = cpu_to_le64(cfg->key_iova);
++	cmd_params->mask_iova = cpu_to_le64(cfg->mask_iova);
++	cmd_params->options = cpu_to_le16(action->options);
++	cmd_params->flow_id = cpu_to_le16(action->flow_id);
++	cmd_params->flc = cpu_to_le64(action->flc);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_remove_fs_entry() - Remove Flow Steering entry from a specific
++ *			    traffic class
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @tc_id:	Traffic class selection (0-7)
++ * @cfg:	Flow steering rule to remove
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_remove_fs_entry(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u8 tc_id,
++			 const struct dpni_rule_cfg *cfg)
++{
++	struct dpni_cmd_remove_fs_entry *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_FS_ENT,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_remove_fs_entry *)cmd.params;
++	cmd_params->tc_id = tc_id;
++	cmd_params->key_size = cfg->key_size;
++	cmd_params->key_iova = cpu_to_le64(cfg->key_iova);
++	cmd_params->mask_iova = cpu_to_le64(cfg->mask_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_congestion_notification() - Set traffic class congestion
++ *					notification configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @qtype:	Type of queue - Rx, Tx and Tx confirm types are supported
++ * @tc_id:	Traffic class selection (0-7)
++ * @cfg:	Congestion notification configuration
++ *
++ * Return:	'0' on Success; error code otherwise.
++ */
++int dpni_set_congestion_notification(
++			struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			enum dpni_queue_type qtype,
++			u8 tc_id,
++			const struct dpni_congestion_notification_cfg *cfg)
++{
++	struct dpni_cmd_set_congestion_notification *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(
++			DPNI_CMDID_SET_CONGESTION_NOTIFICATION,
++			cmd_flags,
++			token);
++	cmd_params = (struct dpni_cmd_set_congestion_notification *)cmd.params;
++	cmd_params->qtype = qtype;
++	cmd_params->tc = tc_id;
++	cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
++	cmd_params->notification_mode = cpu_to_le16(cfg->notification_mode);
++	cmd_params->dest_priority = cfg->dest_cfg.priority;
++	dpni_set_field(cmd_params->type_units, DEST_TYPE,
++		       cfg->dest_cfg.dest_type);
++	dpni_set_field(cmd_params->type_units, CONG_UNITS, cfg->units);
++	cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
++	cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
++	cmd_params->threshold_entry = cpu_to_le32(cfg->threshold_entry);
++	cmd_params->threshold_exit = cpu_to_le32(cfg->threshold_exit);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_congestion_notification() - Get traffic class congestion
++ *	notification configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @qtype:	Type of queue - Rx, Tx and Tx confirm types are supported
++ * @tc_id:	bits 7-4 contain ceetm channel index (valid only for TX);
++ *		bits 3-0 contain traffic class.
++ *		Use macro DPNI_BUILD_CH_TC() to build correct value for
++ *		tc_id parameter.
++ * @cfg:	congestion notification configuration
++ *
++ * Return:	'0' on Success; error code otherwise.
++ */
++int dpni_get_congestion_notification(
++			struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			enum dpni_queue_type qtype,
++			u8 tc_id,
++			struct dpni_congestion_notification_cfg *cfg)
++{
++	struct dpni_rsp_get_congestion_notification *rsp_params;
++	struct dpni_cmd_get_congestion_notification *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(
++				DPNI_CMDID_GET_CONGESTION_NOTIFICATION,
++				cmd_flags,
++				token);
++	cmd_params = (struct dpni_cmd_get_congestion_notification *)cmd.params;
++	cmd_params->qtype = qtype;
++	cmd_params->tc = tc_id;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpni_rsp_get_congestion_notification *)cmd.params;
++	cfg->units = dpni_get_field(rsp_params->type_units, CONG_UNITS);
++	cfg->threshold_entry = le32_to_cpu(rsp_params->threshold_entry);
++	cfg->threshold_exit = le32_to_cpu(rsp_params->threshold_exit);
++	cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
++	cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
++	cfg->notification_mode = le16_to_cpu(rsp_params->notification_mode);
++	cfg->dest_cfg.dest_id = le32_to_cpu(rsp_params->dest_id);
++	cfg->dest_cfg.priority = rsp_params->dest_priority;
++	cfg->dest_cfg.dest_type = dpni_get_field(rsp_params->type_units,
++						 DEST_TYPE);
++
++	return 0;
++}
++
++/**
++ * dpni_set_queue() - Set queue parameters
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @qtype:	Type of queue - all queue types are supported, although
++ *		the command is ignored for Tx
++ * @tc:		Traffic class, in range 0 to NUM_TCS - 1
++ * @index:	Selects the specific queue out of the set allocated for the
++ *		same TC. Value must be in range 0 to NUM_QUEUES - 1
++ * @options:	A combination of DPNI_QUEUE_OPT_ values that control what
++ *		configuration options are set on the queue
++ * @queue:	Queue structure
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_queue(struct fsl_mc_io *mc_io,
++		   u32 cmd_flags,
++		   u16 token,
++		   enum dpni_queue_type qtype,
++		   u8 tc,
++		   u8 index,
++		   u8 options,
++		   const struct dpni_queue *queue)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_queue *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QUEUE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_queue *)cmd.params;
++	cmd_params->qtype = qtype;
++	cmd_params->tc = tc;
++	cmd_params->index = index;
++	cmd_params->options = options;
++	cmd_params->dest_id = cpu_to_le32(queue->destination.id);
++	cmd_params->dest_prio = queue->destination.priority;
++	dpni_set_field(cmd_params->flags, DEST_TYPE, queue->destination.type);
++	dpni_set_field(cmd_params->flags, STASH_CTRL, queue->flc.stash_control);
++	dpni_set_field(cmd_params->flags, HOLD_ACTIVE,
++		       queue->destination.hold_active);
++	cmd_params->flc = cpu_to_le64(queue->flc.value);
++	cmd_params->user_context = cpu_to_le64(queue->user_context);
++
++	/* send command to mc */
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_queue() - Get queue parameters
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @qtype:	Type of queue - all queue types are supported
++ * @tc:		Traffic class, in range 0 to NUM_TCS - 1
++ * @index:	Selects the specific queue out of the set allocated for the
++ *		same TC. Value must be in range 0 to NUM_QUEUES - 1
++ * @queue:	Queue configuration structure
++ * @qid:	Queue identification
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_queue(struct fsl_mc_io *mc_io,
++		   u32 cmd_flags,
++		   u16 token,
++		   enum dpni_queue_type qtype,
++		   u8 tc,
++		   u8 index,
++		   struct dpni_queue *queue,
++		   struct dpni_queue_id *qid)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_queue *cmd_params;
++	struct dpni_rsp_get_queue *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QUEUE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_queue *)cmd.params;
++	cmd_params->qtype = qtype;
++	cmd_params->tc = tc;
++	cmd_params->index = index;
++
++	/* send command to mc */
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_queue *)cmd.params;
++	queue->destination.id = le32_to_cpu(rsp_params->dest_id);
++	queue->destination.priority = rsp_params->dest_prio;
++	queue->destination.type = dpni_get_field(rsp_params->flags,
++						 DEST_TYPE);
++	queue->flc.stash_control = dpni_get_field(rsp_params->flags,
++						  STASH_CTRL);
++	queue->destination.hold_active = dpni_get_field(rsp_params->flags,
++							HOLD_ACTIVE);
++	queue->flc.value = le64_to_cpu(rsp_params->flc);
++	queue->user_context = le64_to_cpu(rsp_params->user_context);
++	qid->fqid = le32_to_cpu(rsp_params->fqid);
++	qid->qdbin = le16_to_cpu(rsp_params->qdbin);
++
++	return 0;
++}
++
++/**
++ * dpni_get_statistics() - Get DPNI statistics
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @page:	Selects the statistics page to retrieve, see
++ *		DPNI_GET_STATISTICS output. Pages are numbered 0 to 2.
++ * @param:	Custom parameter for some pages used to select a certain
++ *		statistic source, for example the TC.
++ * @stat:	Structure containing the statistics
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_statistics(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 page,
++			u8 param,
++			union dpni_statistics *stat)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_statistics *cmd_params;
++	struct dpni_rsp_get_statistics *rsp_params;
++	int i, err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_STATISTICS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_statistics *)cmd.params;
++	cmd_params->page_number = page;
++	cmd_params->param = param;
++
++	/* send command to mc */
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_statistics *)cmd.params;
++	for (i = 0; i < DPNI_STATISTICS_CNT; i++)
++		stat->raw.counter[i] = le64_to_cpu(rsp_params->counter[i]);
++
++	return 0;
++}
++
++/**
++ * dpni_reset_statistics() - Clears DPNI statistics
++ * @mc_io:		Pointer to MC portal's I/O object
++ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:		Token of DPNI object
++ *
++ * Return:  '0' on Success; Error code otherwise.
++ */
++int dpni_reset_statistics(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET_STATISTICS,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_taildrop() - Set taildrop per queue or TC
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cg_point:	Congestion point
++ * @q_type:	Queue type on which the taildrop is configured.
++ *		Only Rx queues are supported for now
++ * @tc:		bits 7-4 contain ceetm channel index (valid only for TX);
++ *		bits 3-0 contain traffic class.
++ *		Use macro DPNI_BUILD_CH_TC() to build correct value for
++ *		tc parameter.
++ * @q_index:	Index of the queue if the DPNI supports multiple queues for
++ *		traffic distribution. Ignored if CONGESTION_POINT is not 0.
++ * @taildrop:	Taildrop structure
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_set_taildrop(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      enum dpni_congestion_point cg_point,
++		      enum dpni_queue_type qtype,
++		      u8 tc,
++		      u8 index,
++		      struct dpni_taildrop *taildrop)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_set_taildrop *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TAILDROP,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_taildrop *)cmd.params;
++	cmd_params->congestion_point = cg_point;
++	cmd_params->qtype = qtype;
++	cmd_params->tc = tc;
++	cmd_params->index = index;
++	dpni_set_field(cmd_params->enable, ENABLE, taildrop->enable);
++	cmd_params->units = taildrop->units;
++	cmd_params->threshold = cpu_to_le32(taildrop->threshold);
++
++	/* send command to mc */
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_get_taildrop() - Get taildrop information
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cg_point:	Congestion point
++ * @q_type:	Queue type on which the taildrop is configured.
++ *		Only Rx queues are supported for now
++ * @tc:		bits 7-4 contain ceetm channel index (valid only for TX);
++ *		bits 3-0 contain traffic class.
++ *		Use macro DPNI_BUILD_CH_TC() to build correct value for
++ *		tc parameter.
++ * @q_index:	Index of the queue if the DPNI supports multiple queues for
++ *		traffic distribution. Ignored if CONGESTION_POINT is not 0.
++ * @taildrop:	Taildrop structure
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_taildrop(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      enum dpni_congestion_point cg_point,
++		      enum dpni_queue_type qtype,
++		      u8 tc,
++		      u8 index,
++		      struct dpni_taildrop *taildrop)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpni_cmd_get_taildrop *cmd_params;
++	struct dpni_rsp_get_taildrop *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_TAILDROP,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_get_taildrop *)cmd.params;
++	cmd_params->congestion_point = cg_point;
++	cmd_params->qtype = qtype;
++	cmd_params->tc = tc;
++	cmd_params->index = index;
++
++	/* send command to mc */
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpni_rsp_get_taildrop *)cmd.params;
++	taildrop->enable = dpni_get_field(rsp_params->enable, ENABLE);
++	taildrop->units = rsp_params->units;
++	taildrop->threshold = le32_to_cpu(rsp_params->threshold);
++
++	return 0;
++}
++
++/**
++ * dpni_get_api_version() - Get Data Path Network Interface API version
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @major_ver:	Major version of data path network interface API
++ * @minor_ver:	Minor version of data path network interface API
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpni_get_api_version(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 *major_ver,
++			 u16 *minor_ver)
++{
++	struct dpni_rsp_get_api_version *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION,
++					  cmd_flags, 0);
++
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpni_rsp_get_api_version *)cmd.params;
++	*major_ver = le16_to_cpu(rsp_params->major);
++	*minor_ver = le16_to_cpu(rsp_params->minor);
++
++	return 0;
++}
++
++/**
++ * dpni_set_rx_fs_dist() - Set Rx traffic class FS distribution
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg: Distribution configuration
++ * If the FS is already enabled with a previous call the classification
++ * key will be changed but all the table rules are kept. If the
++ * existing rules do not match the key the results will not be
++ * predictable. It is the user responsibility to keep key integrity.
++ * If cfg.enable is set to 1 the command will create a flow steering table
++ * and will classify packets according to this table. The packets that
++ * miss all the table rules will be classified according to settings
++ * made in dpni_set_rx_hash_dist()
++ * If cfg.enable is set to 0 the command will clear flow steering table.
++ * The packets will be classified according to settings made in
++ * dpni_set_rx_hash_dist()
++ */
++int dpni_set_rx_fs_dist(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			const struct dpni_rx_dist_cfg *cfg)
++{
++	struct dpni_cmd_set_rx_fs_dist *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_FS_DIST,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_rx_fs_dist *)cmd.params;
++	cmd_params->dist_size = le16_to_cpu(cfg->dist_size);
++	dpni_set_field(cmd_params->enable, RX_FS_DIST_ENABLE, cfg->enable);
++	cmd_params->tc = cfg->tc;
++	cmd_params->miss_flow_id = le16_to_cpu(cfg->fs_miss_flow_id);
++	cmd_params->key_cfg_iova = le64_to_cpu(cfg->key_cfg_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpni_set_rx_hash_dist() - Set Rx traffic class HASH distribution
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPNI object
++ * @cfg: Distribution configuration
++ * If cfg.enable is set to 1 the packets will be classified using a hash
++ * function based on the key received in cfg.key_cfg_iova parameter.
++ * If cfg.enable is set to 0 the packets will be sent to the queue configured
++ * in dpni_set_rx_dist_default_queue() call
++ */
++int dpni_set_rx_hash_dist(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  const struct dpni_rx_dist_cfg *cfg)
++{
++	struct dpni_cmd_set_rx_hash_dist *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_HASH_DIST,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpni_cmd_set_rx_hash_dist *)cmd.params;
++	cmd_params->dist_size = le16_to_cpu(cfg->dist_size);
++	dpni_set_field(cmd_params->enable, RX_FS_DIST_ENABLE, cfg->enable);
++	cmd_params->tc = cfg->tc;
++	cmd_params->key_cfg_iova = le64_to_cpu(cfg->key_cfg_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.h
+@@ -0,0 +1,1172 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2016 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef __FSL_DPNI_H
++#define __FSL_DPNI_H
++
++#include "dpkg.h"
++
++struct fsl_mc_io;
++
++/**
++ * Data Path Network Interface API
++ * Contains initialization APIs and runtime control APIs for DPNI
++ */
++
++/** General DPNI macros */
++
++/**
++ * Maximum number of traffic classes
++ */
++#define DPNI_MAX_TC				8
++/**
++ * Maximum number of buffer pools per DPNI
++ */
++#define DPNI_MAX_DPBP				8
++/**
++ * Maximum number of senders
++ */
++#define DPNI_MAX_SENDERS			16
++/**
++ * Maximum distribution size
++ */
++#define DPNI_MAX_DIST_SIZE			16
++
++/**
++ * All traffic classes considered; see dpni_set_queue()
++ */
++#define DPNI_ALL_TCS				(u8)(-1)
++/**
++ * All flows within traffic class considered; see dpni_set_queue()
++ */
++#define DPNI_ALL_TC_FLOWS			(u16)(-1)
++/**
++ * Generate new flow ID; see dpni_set_queue()
++ */
++#define DPNI_NEW_FLOW_ID			(u16)(-1)
++
++/**
++ * Tx traffic is always released to a buffer pool on transmit, there are no
++ * resources allocated to have the frames confirmed back to the source after
++ * transmission.
++ */
++#define DPNI_OPT_TX_FRM_RELEASE			0x000001
++/**
++ * Disables support for MAC address filtering for addresses other than primary
++ * MAC address. This affects both unicast and multicast. Promiscuous mode can
++ * still be enabled/disabled for both unicast and multicast. If promiscuous mode
++ * is disabled, only traffic matching the primary MAC address will be accepted.
++ */
++#define DPNI_OPT_NO_MAC_FILTER			0x000002
++/**
++ * Allocate policers for this DPNI. They can be used to rate-limit traffic per
++ * traffic class (TC) basis.
++ */
++#define DPNI_OPT_HAS_POLICING			0x000004
++/**
++ * Congestion can be managed in several ways, allowing the buffer pool to
++ * deplete on ingress, taildrop on each queue or use congestion groups for sets
++ * of queues. If set, it configures a single congestion groups across all TCs.
++ * If reset, a congestion group is allocated for each TC. Only relevant if the
++ * DPNI has multiple traffic classes.
++ */
++#define DPNI_OPT_SHARED_CONGESTION		0x000008
++/**
++ * Enables TCAM for Flow Steering and QoS look-ups. If not specified, all
++ * look-ups are exact match. Note that TCAM is not available on LS1088 and its
++ * variants. Setting this bit on these SoCs will trigger an error.
++ */
++#define DPNI_OPT_HAS_KEY_MASKING		0x000010
++/**
++ * Disables the flow steering table.
++ */
++#define DPNI_OPT_NO_FS				0x000020
++
++int dpni_open(struct fsl_mc_io	*mc_io,
++	      u32		cmd_flags,
++	      int		dpni_id,
++	      u16		*token);
++
++int dpni_close(struct fsl_mc_io	*mc_io,
++	       u32		cmd_flags,
++	       u16		token);
++
++/**
++ * struct dpni_pools_cfg - Structure representing buffer pools configuration
++ * @num_dpbp: Number of DPBPs
++ * @pools: Array of buffer pools parameters; The number of valid entries
++ *	must match 'num_dpbp' value
++ */
++struct dpni_pools_cfg {
++	u8		num_dpbp;
++	/**
++	 * struct pools - Buffer pools parameters
++	 * @dpbp_id: DPBP object ID
++	 * @priority_mask: priorities served by DPBP
++	 * @buffer_size: Buffer size
++	 * @backup_pool: Backup pool
++	 */
++	struct {
++		u16	dpbp_id;
++		u8	priority_mask;
++		u16	buffer_size;
++		u8	backup_pool;
++	} pools[DPNI_MAX_DPBP];
++};
++
++int dpni_set_pools(struct fsl_mc_io		*mc_io,
++		   u32				cmd_flags,
++		   u16				token,
++		   const struct dpni_pools_cfg	*cfg);
++
++int dpni_enable(struct fsl_mc_io	*mc_io,
++		u32			cmd_flags,
++		u16			token);
++
++int dpni_disable(struct fsl_mc_io	*mc_io,
++		 u32			cmd_flags,
++		 u16			token);
++
++int dpni_is_enabled(struct fsl_mc_io	*mc_io,
++		    u32			cmd_flags,
++		    u16			token,
++		    int			*en);
++
++int dpni_reset(struct fsl_mc_io	*mc_io,
++	       u32		cmd_flags,
++	       u16		token);
++
++/**
++ * DPNI IRQ Index and Events
++ */
++
++/**
++ * IRQ index
++ */
++#define DPNI_IRQ_INDEX				0
++/**
++ * IRQ event - indicates a change in link state
++ */
++#define DPNI_IRQ_EVENT_LINK_CHANGED		0x00000001
++
++int dpni_set_irq_enable(struct fsl_mc_io	*mc_io,
++			u32			cmd_flags,
++			u16			token,
++			u8			irq_index,
++			u8			en);
++
++int dpni_get_irq_enable(struct fsl_mc_io	*mc_io,
++			u32			cmd_flags,
++			u16			token,
++			u8			irq_index,
++			u8			*en);
++
++int dpni_set_irq_mask(struct fsl_mc_io	*mc_io,
++		      u32		cmd_flags,
++		      u16		token,
++		      u8		irq_index,
++		      u32		mask);
++
++int dpni_get_irq_mask(struct fsl_mc_io	*mc_io,
++		      u32		cmd_flags,
++		      u16		token,
++		      u8		irq_index,
++		      u32		*mask);
++
++int dpni_get_irq_status(struct fsl_mc_io	*mc_io,
++			u32			cmd_flags,
++			u16			token,
++			u8			irq_index,
++			u32			*status);
++
++int dpni_clear_irq_status(struct fsl_mc_io	*mc_io,
++			  u32			cmd_flags,
++			  u16			token,
++			  u8			irq_index,
++			  u32			status);
++
++/**
++ * struct dpni_attr - Structure representing DPNI attributes
++ * @options: Any combination of the following options:
++ *		DPNI_OPT_TX_FRM_RELEASE
++ *		DPNI_OPT_NO_MAC_FILTER
++ *		DPNI_OPT_HAS_POLICING
++ *		DPNI_OPT_SHARED_CONGESTION
++ *		DPNI_OPT_HAS_KEY_MASKING
++ *		DPNI_OPT_NO_FS
++ * @num_queues: Number of Tx and Rx queues used for traffic distribution.
++ * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI.
++ * @mac_filter_entries: Number of entries in the MAC address filtering table.
++ * @vlan_filter_entries: Number of entries in the VLAN address filtering table.
++ * @qos_entries: Number of entries in the QoS classification table.
++ * @fs_entries: Number of entries in the flow steering table.
++ * @qos_key_size: Size, in bytes, of the QoS look-up key. Defining a key larger
++ *		than this when adding QoS entries will result in an error.
++ * @fs_key_size: Size, in bytes, of the flow steering look-up key. Defining a
++ *		key larger than this when composing the hash + FS key will
++ *		result in an error.
++ * @wriop_version: Version of WRIOP HW block. The 3 version values are stored
++ *		on 6, 5, 5 bits respectively.
++ */
++struct dpni_attr {
++	u32 options;
++	u8 num_queues;
++	u8 num_tcs;
++	u8 mac_filter_entries;
++	u8 vlan_filter_entries;
++	u8 qos_entries;
++	u16 fs_entries;
++	u8 qos_key_size;
++	u8 fs_key_size;
++	u16 wriop_version;
++};
++
++int dpni_get_attributes(struct fsl_mc_io	*mc_io,
++			u32			cmd_flags,
++			u16			token,
++			struct dpni_attr	*attr);
++
++/**
++ * DPNI errors
++ */
++
++/**
++ * Extract out of frame header error
++ */
++#define DPNI_ERROR_EOFHE	0x00020000
++/**
++ * Frame length error
++ */
++#define DPNI_ERROR_FLE		0x00002000
++/**
++ * Frame physical error
++ */
++#define DPNI_ERROR_FPE		0x00001000
++/**
++ * Parsing header error
++ */
++#define DPNI_ERROR_PHE		0x00000020
++/**
++ * Parser L3 checksum error
++ */
++#define DPNI_ERROR_L3CE		0x00000004
++/**
++ * Parser L3 checksum error
++ */
++#define DPNI_ERROR_L4CE		0x00000001
++
++/**
++ * enum dpni_error_action - Defines DPNI behavior for errors
++ * @DPNI_ERROR_ACTION_DISCARD: Discard the frame
++ * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow
++ * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue
++ */
++enum dpni_error_action {
++	DPNI_ERROR_ACTION_DISCARD = 0,
++	DPNI_ERROR_ACTION_CONTINUE = 1,
++	DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2
++};
++
++/**
++ * struct dpni_error_cfg - Structure representing DPNI errors treatment
++ * @errors: Errors mask; use 'DPNI_ERROR__<X>
++ * @error_action: The desired action for the errors mask
++ * @set_frame_annotation: Set to '1' to mark the errors in frame annotation
++ *		status (FAS); relevant only for the non-discard action
++ */
++struct dpni_error_cfg {
++	u32			errors;
++	enum dpni_error_action	error_action;
++	int			set_frame_annotation;
++};
++
++int dpni_set_errors_behavior(struct fsl_mc_io		*mc_io,
++			     u32			cmd_flags,
++			     u16			token,
++			     struct dpni_error_cfg	*cfg);
++
++/**
++ * DPNI buffer layout modification options
++ */
++
++/**
++ * Select to modify the time-stamp setting
++ */
++#define DPNI_BUF_LAYOUT_OPT_TIMESTAMP		0x00000001
++/**
++ * Select to modify the parser-result setting; not applicable for Tx
++ */
++#define DPNI_BUF_LAYOUT_OPT_PARSER_RESULT	0x00000002
++/**
++ * Select to modify the frame-status setting
++ */
++#define DPNI_BUF_LAYOUT_OPT_FRAME_STATUS	0x00000004
++/**
++ * Select to modify the private-data-size setting
++ */
++#define DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE	0x00000008
++/**
++ * Select to modify the data-alignment setting
++ */
++#define DPNI_BUF_LAYOUT_OPT_DATA_ALIGN		0x00000010
++/**
++ * Select to modify the data-head-room setting
++ */
++#define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM	0x00000020
++/**
++ * Select to modify the data-tail-room setting
++ */
++#define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM	0x00000040
++
++/**
++ * struct dpni_buffer_layout - Structure representing DPNI buffer layout
++ * @options: Flags representing the suggested modifications to the buffer
++ *		layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags
++ * @pass_timestamp: Pass timestamp value
++ * @pass_parser_result: Pass parser results
++ * @pass_frame_status: Pass frame status
++ * @private_data_size: Size kept for private data (in bytes)
++ * @data_align: Data alignment
++ * @data_head_room: Data head room
++ * @data_tail_room: Data tail room
++ */
++struct dpni_buffer_layout {
++	u32	options;
++	int	pass_timestamp;
++	int	pass_parser_result;
++	int	pass_frame_status;
++	u16	private_data_size;
++	u16	data_align;
++	u16	data_head_room;
++	u16	data_tail_room;
++};
++
++/**
++ * enum dpni_queue_type - Identifies a type of queue targeted by the command
++ * @DPNI_QUEUE_RX: Rx queue
++ * @DPNI_QUEUE_TX: Tx queue
++ * @DPNI_QUEUE_TX_CONFIRM: Tx confirmation queue
++ * @DPNI_QUEUE_RX_ERR: Rx error queue
++ */enum dpni_queue_type {
++	DPNI_QUEUE_RX,
++	DPNI_QUEUE_TX,
++	DPNI_QUEUE_TX_CONFIRM,
++	DPNI_QUEUE_RX_ERR,
++};
++
++int dpni_get_buffer_layout(struct fsl_mc_io		*mc_io,
++			   u32				cmd_flags,
++			   u16				token,
++			   enum dpni_queue_type		qtype,
++			   struct dpni_buffer_layout	*layout);
++
++int dpni_set_buffer_layout(struct fsl_mc_io		   *mc_io,
++			   u32				   cmd_flags,
++			   u16				   token,
++			   enum dpni_queue_type		   qtype,
++			   const struct dpni_buffer_layout *layout);
++
++/**
++ * enum dpni_offload - Identifies a type of offload targeted by the command
++ * @DPNI_OFF_RX_L3_CSUM: Rx L3 checksum validation
++ * @DPNI_OFF_RX_L4_CSUM: Rx L4 checksum validation
++ * @DPNI_OFF_TX_L3_CSUM: Tx L3 checksum generation
++ * @DPNI_OFF_TX_L4_CSUM: Tx L4 checksum generation
++ */
++enum dpni_offload {
++	DPNI_OFF_RX_L3_CSUM,
++	DPNI_OFF_RX_L4_CSUM,
++	DPNI_OFF_TX_L3_CSUM,
++	DPNI_OFF_TX_L4_CSUM,
++};
++
++int dpni_set_offload(struct fsl_mc_io	*mc_io,
++		     u32		cmd_flags,
++		     u16		token,
++		     enum dpni_offload	type,
++		     u32		config);
++
++int dpni_get_offload(struct fsl_mc_io	*mc_io,
++		     u32		cmd_flags,
++		     u16		token,
++		     enum dpni_offload	type,
++		     u32		*config);
++
++int dpni_get_qdid(struct fsl_mc_io	*mc_io,
++		  u32			cmd_flags,
++		  u16			token,
++		  enum dpni_queue_type	qtype,
++		  u16			*qdid);
++
++int dpni_get_tx_data_offset(struct fsl_mc_io	*mc_io,
++			    u32			cmd_flags,
++			    u16			token,
++			    u16			*data_offset);
++
++#define DPNI_STATISTICS_CNT		7
++
++union dpni_statistics {
++	/**
++	 * struct page_0 - Page_0 statistics structure
++	 * @ingress_all_frames: Ingress frame count
++	 * @ingress_all_bytes: Ingress byte count
++	 * @ingress_multicast_frames: Ingress multicast frame count
++	 * @ingress_multicast_bytes: Ingress multicast byte count
++	 * @ingress_broadcast_frames: Ingress broadcast frame count
++	 * @ingress_broadcast_bytes: Ingress broadcast byte count
++	 */
++	struct {
++		u64 ingress_all_frames;
++		u64 ingress_all_bytes;
++		u64 ingress_multicast_frames;
++		u64 ingress_multicast_bytes;
++		u64 ingress_broadcast_frames;
++		u64 ingress_broadcast_bytes;
++	} page_0;
++	/**
++	 * struct page_1 - Page_1 statistics structure
++	 * @egress_all_frames: Egress frame count
++	 * @egress_all_bytes: Egress byte count
++	 * @egress_multicast_frames: Egress multicast frame count
++	 * @egress_multicast_bytes: Egress multicast byte count
++	 * @egress_broadcast_frames: Egress broadcast frame count
++	 * @egress_broadcast_bytes: Egress broadcast byte count
++	 */
++	struct {
++		u64 egress_all_frames;
++		u64 egress_all_bytes;
++		u64 egress_multicast_frames;
++		u64 egress_multicast_bytes;
++		u64 egress_broadcast_frames;
++		u64 egress_broadcast_bytes;
++	} page_1;
++	/**
++	 * struct page_2 - Page_2 statistics structure
++	 * @ingress_filtered_frames: Ingress filtered frame count
++	 * @ingress_discarded_frames: Ingress discarded frame count
++	 * @ingress_nobuffer_discards: Ingress discarded frame count
++	 *				due to lack of buffers
++	 * @egress_discarded_frames: Egress discarded frame count
++	 * @egress_confirmed_frames: Egress confirmed frame count
++	 */
++	struct {
++		u64 ingress_filtered_frames;
++		u64 ingress_discarded_frames;
++		u64 ingress_nobuffer_discards;
++		u64 egress_discarded_frames;
++		u64 egress_confirmed_frames;
++	} page_2;
++	/**
++	 * struct page_3 - Page_3 statistics structure with values for the
++	 *		   selected TC
++	 * @ceetm_dequeue_bytes: Cumulative count of the number of bytes
++	 *			 dequeued
++	 * @ceetm_dequeue_frames: Cumulative count of the number of frames
++	 *			  dequeued
++	 * @ceetm_reject_bytes: Cumulative count of the number of bytes in all
++	 *			frames whose enqueue was rejected
++	 * @ceetm_reject_frames: Cumulative count of all frame enqueues
++	 *			 rejected
++	 */
++	struct {
++		u64 ceetm_dequeue_bytes;
++		u64 ceetm_dequeue_frames;
++		u64 ceetm_reject_bytes;
++		u64 ceetm_reject_frames;
++	} page_3;
++	/**
++	 * struct raw - raw statistics structure
++	 */
++	struct {
++		u64 counter[DPNI_STATISTICS_CNT];
++	} raw;
++};
++
++int dpni_get_statistics(struct fsl_mc_io	*mc_io,
++			u32			cmd_flags,
++			u16			token,
++			u8			page,
++			u8			param,
++			union dpni_statistics	*stat);
++
++int dpni_reset_statistics(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token);
++
++/**
++ * Enable auto-negotiation
++ */
++#define DPNI_LINK_OPT_AUTONEG		0x0000000000000001ULL
++/**
++ * Enable half-duplex mode
++ */
++#define DPNI_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
++/**
++ * Enable pause frames
++ */
++#define DPNI_LINK_OPT_PAUSE		0x0000000000000004ULL
++/**
++ * Enable a-symmetric pause frames
++ */
++#define DPNI_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
++/**
++ * Enable priority flow control pause frames
++ */
++#define DPNI_LINK_OPT_PFC_PAUSE		0x0000000000000010ULL
++
++/**
++ * struct - Structure representing DPNI link configuration
++ * @rate: Rate
++ * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values
++ */
++struct dpni_link_cfg {
++	u32 rate;
++	u64 options;
++};
++
++int dpni_set_link_cfg(struct fsl_mc_io			*mc_io,
++		      u32				cmd_flags,
++		      u16				token,
++		      const struct dpni_link_cfg	*cfg);
++
++/**
++ * struct dpni_link_state - Structure representing DPNI link state
++ * @rate: Rate
++ * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values
++ * @up: Link state; '0' for down, '1' for up
++ */
++struct dpni_link_state {
++	u32	rate;
++	u64	options;
++	int	up;
++};
++
++int dpni_get_link_state(struct fsl_mc_io	*mc_io,
++			u32			cmd_flags,
++			u16			token,
++			struct dpni_link_state	*state);
++
++/**
++ * struct dpni_tx_shaping - Structure representing DPNI tx shaping configuration
++ * @rate_limit: rate in Mbps
++ * @max_burst_size: burst size in bytes (up to 64KB)
++ */
++struct dpni_tx_shaping_cfg {
++	u32	rate_limit;
++	u16	max_burst_size;
++};
++
++int dpni_set_tx_shaping(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			const struct dpni_tx_shaping_cfg *tx_cr_shaper,
++			const struct dpni_tx_shaping_cfg *tx_er_shaper,
++			int coupled);
++
++int dpni_set_max_frame_length(struct fsl_mc_io	*mc_io,
++			      u32		cmd_flags,
++			      u16		token,
++			      u16		max_frame_length);
++
++int dpni_get_max_frame_length(struct fsl_mc_io	*mc_io,
++			      u32		cmd_flags,
++			      u16		token,
++			      u16		*max_frame_length);
++
++int dpni_set_multicast_promisc(struct fsl_mc_io *mc_io,
++			       u32		cmd_flags,
++			       u16		token,
++			       int		en);
++
++int dpni_get_multicast_promisc(struct fsl_mc_io *mc_io,
++			       u32		cmd_flags,
++			       u16		token,
++			       int		*en);
++
++int dpni_set_unicast_promisc(struct fsl_mc_io	*mc_io,
++			     u32		cmd_flags,
++			     u16		token,
++			     int		en);
++
++int dpni_get_unicast_promisc(struct fsl_mc_io	*mc_io,
++			     u32		cmd_flags,
++			     u16		token,
++			     int		*en);
++
++int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
++			      u32		cmd_flags,
++			      u16		token,
++			      const u8		mac_addr[6]);
++
++int dpni_get_primary_mac_addr(struct fsl_mc_io	*mc_io,
++			      u32		cmd_flags,
++			      u16		token,
++			      u8		mac_addr[6]);
++
++int dpni_get_port_mac_addr(struct fsl_mc_io	*mc_io,
++			   u32			cm_flags,
++			   u16			token,
++			   u8			mac_addr[6]);
++
++int dpni_add_mac_addr(struct fsl_mc_io	*mc_io,
++		      u32		cmd_flags,
++		      u16		token,
++		      const u8		mac_addr[6]);
++
++int dpni_remove_mac_addr(struct fsl_mc_io	*mc_io,
++			 u32			cmd_flags,
++			 u16			token,
++			 const u8		mac_addr[6]);
++
++int dpni_clear_mac_filters(struct fsl_mc_io	*mc_io,
++			   u32			cmd_flags,
++			   u16			token,
++			   int			unicast,
++			   int			multicast);
++
++/**
++ * enum dpni_dist_mode - DPNI distribution mode
++ * @DPNI_DIST_MODE_NONE: No distribution
++ * @DPNI_DIST_MODE_HASH: Use hash distribution; only relevant if
++ *		the 'DPNI_OPT_DIST_HASH' option was set at DPNI creation
++ * @DPNI_DIST_MODE_FS:  Use explicit flow steering; only relevant if
++ *	 the 'DPNI_OPT_DIST_FS' option was set at DPNI creation
++ */
++enum dpni_dist_mode {
++	DPNI_DIST_MODE_NONE = 0,
++	DPNI_DIST_MODE_HASH = 1,
++	DPNI_DIST_MODE_FS = 2
++};
++
++/**
++ * enum dpni_fs_miss_action -   DPNI Flow Steering miss action
++ * @DPNI_FS_MISS_DROP: In case of no-match, drop the frame
++ * @DPNI_FS_MISS_EXPLICIT_FLOWID: In case of no-match, use explicit flow-id
++ * @DPNI_FS_MISS_HASH: In case of no-match, distribute using hash
++ */
++enum dpni_fs_miss_action {
++	DPNI_FS_MISS_DROP = 0,
++	DPNI_FS_MISS_EXPLICIT_FLOWID = 1,
++	DPNI_FS_MISS_HASH = 2
++};
++
++/**
++ * struct dpni_fs_tbl_cfg - Flow Steering table configuration
++ * @miss_action: Miss action selection
++ * @default_flow_id: Used when 'miss_action = DPNI_FS_MISS_EXPLICIT_FLOWID'
++ */
++struct dpni_fs_tbl_cfg {
++	enum dpni_fs_miss_action	miss_action;
++	u16				default_flow_id;
++};
++
++int dpni_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
++			 u8 *key_cfg_buf);
++
++/**
++ * struct dpni_qos_tbl_cfg - Structure representing QOS table configuration
++ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with
++ *		key extractions to be used as the QoS criteria by calling
++ *		dpkg_prepare_key_cfg()
++ * @discard_on_miss: Set to '1' to discard frames in case of no match (miss);
++ *		'0' to use the 'default_tc' in such cases
++ * @default_tc: Used in case of no-match and 'discard_on_miss'= 0
++ */
++struct dpni_qos_tbl_cfg {
++	u64 key_cfg_iova;
++	int discard_on_miss;
++	u8 default_tc;
++};
++
++int dpni_set_qos_table(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       const struct dpni_qos_tbl_cfg *cfg);
++
++/**
++ * enum dpni_tx_schedule_mode - DPNI Tx scheduling mode
++ * @DPNI_TX_SCHED_STRICT_PRIORITY: strict priority
++ * @DPNI_TX_SCHED_WEIGHTED_A: weighted based scheduling in group A
++ * @DPNI_TX_SCHED_WEIGHTED_B: weighted based scheduling in group B
++ */
++enum dpni_tx_schedule_mode {
++	DPNI_TX_SCHED_STRICT_PRIORITY = 0,
++	DPNI_TX_SCHED_WEIGHTED_A,
++	DPNI_TX_SCHED_WEIGHTED_B,
++};
++
++/**
++ * struct dpni_tx_schedule_cfg - Structure representing Tx scheduling conf
++ * @mode:		Scheduling mode
++ * @delta_bandwidth:	Bandwidth represented in weights from 100 to 10000;
++ *	not applicable for 'strict-priority' mode;
++ */
++struct dpni_tx_schedule_cfg {
++	enum dpni_tx_schedule_mode mode;
++	u16 delta_bandwidth;
++};
++
++/**
++ * struct dpni_tx_priorities_cfg - Structure representing transmission
++ *					priorities for DPNI TCs
++ * @tc_sched:	An array of traffic-classes
++ * @prio_group_A: Priority of group A
++ * @prio_group_B: Priority of group B
++ * @separate_groups: Treat A and B groups as separate
++ * @ceetm_ch_idx: ceetm channel index to apply the changes
++ */
++struct dpni_tx_priorities_cfg {
++	struct dpni_tx_schedule_cfg tc_sched[DPNI_MAX_TC];
++	u8 prio_group_A;
++	u8 prio_group_B;
++	u8 separate_groups;
++};
++
++int dpni_set_tx_priorities(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   const struct dpni_tx_priorities_cfg *cfg);
++
++/**
++ * struct dpni_rx_tc_dist_cfg - Rx traffic class distribution configuration
++ * @dist_size: Set the distribution size;
++ *	supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,
++ *	112,128,192,224,256,384,448,512,768,896,1024
++ * @dist_mode: Distribution mode
++ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with
++ *		the extractions to be used for the distribution key by calling
++ *		dpni_prepare_key_cfg() relevant only when
++ *		'dist_mode != DPNI_DIST_MODE_NONE', otherwise it can be '0'
++ * @fs_cfg: Flow Steering table configuration; only relevant if
++ *		'dist_mode = DPNI_DIST_MODE_FS'
++ */
++struct dpni_rx_tc_dist_cfg {
++	u16			dist_size;
++	enum dpni_dist_mode	dist_mode;
++	u64			key_cfg_iova;
++	struct dpni_fs_tbl_cfg	fs_cfg;
++};
++
++int dpni_set_rx_tc_dist(struct fsl_mc_io			*mc_io,
++			u32					cmd_flags,
++			u16					token,
++			u8					tc_id,
++			const struct dpni_rx_tc_dist_cfg	*cfg);
++
++/**
++ * enum dpni_dest - DPNI destination types
++ * @DPNI_DEST_NONE: Unassigned destination; The queue is set in parked mode and
++ *		does not generate FQDAN notifications; user is expected to
++ *		dequeue from the queue based on polling or other user-defined
++ *		method
++ * @DPNI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
++ *		notifications to the specified DPIO; user is expected to dequeue
++ *		from the queue only after notification is received
++ * @DPNI_DEST_DPCON: The queue is set in schedule mode and does not generate
++ *		FQDAN notifications, but is connected to the specified DPCON
++ *		object; user is expected to dequeue from the DPCON channel
++ */
++enum dpni_dest {
++	DPNI_DEST_NONE = 0,
++	DPNI_DEST_DPIO = 1,
++	DPNI_DEST_DPCON = 2
++};
++
++/**
++ * struct dpni_queue - Queue structure
++ * @user_context: User data, presented to the user along with any frames from
++ *		this queue. Not relevant for Tx queues.
++ */
++struct dpni_queue {
++/**
++ * struct destination - Destination structure
++ * @id: ID of the destination, only relevant if DEST_TYPE is > 0.
++ *		Identifies either a DPIO or a DPCON object. Not relevant for
++ *		Tx queues.
++ * @type: May be one of the following:
++ *	0 - No destination, queue can be manually queried, but will not
++ *		push traffic or notifications to a DPIO;
++ *	1 - The destination is a DPIO. When traffic becomes available in
++ *		the queue a FQDAN (FQ data available notification) will be
++ *		generated to selected DPIO;
++ *	2 - The destination is a DPCON. The queue is associated with a
++ *		DPCON object for the purpose of scheduling between multiple
++ *		queues. The DPCON may be independently configured to
++ *		generate notifications. Not relevant for Tx queues.
++ * @hold_active: Hold active, maintains a queue scheduled for longer
++ *		in a DPIO during dequeue to reduce spread of traffic.
++ *		Only relevant if queues are not affined to a single DPIO.
++ */
++	struct {
++		u16 id;
++		enum dpni_dest type;
++		char hold_active;
++		u8 priority;
++	} destination;
++	u64 user_context;
++	struct {
++		u64 value;
++		char stash_control;
++	} flc;
++};
++
++/**
++ * struct dpni_queue_id - Queue identification, used for enqueue commands
++ *			or queue control
++ * @fqid: FQID used for enqueueing to and/or configuration of this specific FQ
++ * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant
++ *		for Tx queues.
++ */
++struct dpni_queue_id {
++	u32 fqid;
++	u16 qdbin;
++};
++
++/**
++ * Set User Context
++ */
++#define DPNI_QUEUE_OPT_USER_CTX		0x00000001
++#define DPNI_QUEUE_OPT_DEST		0x00000002
++#define DPNI_QUEUE_OPT_FLC		0x00000004
++#define DPNI_QUEUE_OPT_HOLD_ACTIVE	0x00000008
++
++int dpni_set_queue(struct fsl_mc_io	*mc_io,
++		   u32			cmd_flags,
++		   u16			token,
++		   enum dpni_queue_type	qtype,
++		   u8			tc,
++		   u8			index,
++		   u8			options,
++		   const struct dpni_queue *queue);
++
++int dpni_get_queue(struct fsl_mc_io	*mc_io,
++		   u32			cmd_flags,
++		   u16			token,
++		   enum dpni_queue_type	qtype,
++		   u8			tc,
++		   u8			index,
++		   struct dpni_queue	*queue,
++		   struct dpni_queue_id	*qid);
++
++/**
++ * enum dpni_congestion_unit - DPNI congestion units
++ * @DPNI_CONGESTION_UNIT_BYTES: bytes units
++ * @DPNI_CONGESTION_UNIT_FRAMES: frames units
++ */
++enum dpni_congestion_unit {
++	DPNI_CONGESTION_UNIT_BYTES = 0,
++	DPNI_CONGESTION_UNIT_FRAMES
++};
++
++/**
++ * enum dpni_congestion_point - Structure representing congestion point
++ * @DPNI_CP_QUEUE: Set taildrop per queue, identified by QUEUE_TYPE, TC and
++ *		QUEUE_INDEX
++ * @DPNI_CP_GROUP: Set taildrop per queue group. Depending on options used to
++ *		define the DPNI this can be either per TC (default) or per
++ *		interface (DPNI_OPT_SHARED_CONGESTION set at DPNI create).
++ *		QUEUE_INDEX is ignored if this type is used.
++ */
++enum dpni_congestion_point {
++	DPNI_CP_QUEUE,
++	DPNI_CP_GROUP,
++};
++
++/**
++ * struct dpni_dest_cfg - Structure representing DPNI destination parameters
++ * @dest_type:	Destination type
++ * @dest_id:	Either DPIO ID or DPCON ID, depending on the destination type
++ * @priority:	Priority selection within the DPIO or DPCON channel; valid
++ *		values are 0-1 or 0-7, depending on the number of priorities
++ *		in that channel; not relevant for 'DPNI_DEST_NONE' option
++ */
++struct dpni_dest_cfg {
++	enum dpni_dest dest_type;
++	int dest_id;
++	u8 priority;
++};
++
++/* DPNI congestion options */
++
++/**
++ * CSCN message is written to message_iova once entering a
++ * congestion state (see 'threshold_entry')
++ */
++#define DPNI_CONG_OPT_WRITE_MEM_ON_ENTER        0x00000001
++/**
++ * CSCN message is written to message_iova once exiting a
++ * congestion state (see 'threshold_exit')
++ */
++#define DPNI_CONG_OPT_WRITE_MEM_ON_EXIT         0x00000002
++/**
++ * CSCN write will attempt to allocate into a cache (coherent write);
++ * valid only if 'DPNI_CONG_OPT_WRITE_MEM_<X>' is selected
++ */
++#define DPNI_CONG_OPT_COHERENT_WRITE            0x00000004
++/**
++ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' CSCN message is sent to
++ * DPIO/DPCON's WQ channel once entering a congestion state
++ * (see 'threshold_entry')
++ */
++#define DPNI_CONG_OPT_NOTIFY_DEST_ON_ENTER      0x00000008
++/**
++ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' CSCN message is sent to
++ * DPIO/DPCON's WQ channel once exiting a congestion state
++ * (see 'threshold_exit')
++ */
++#define DPNI_CONG_OPT_NOTIFY_DEST_ON_EXIT       0x00000010
++/**
++ * if 'dest_cfg.dest_type != DPNI_DEST_NONE' when the CSCN is written to the
++ * sw-portal's DQRR, the DQRI interrupt is asserted immediately (if enabled)
++ */
++#define DPNI_CONG_OPT_INTR_COALESCING_DISABLED  0x00000020
++/**
++ * This congestion will trigger flow control or priority flow control.
++ * This will have effect only if flow control is enabled with
++ * dpni_set_link_cfg().
++ */
++#define DPNI_CONG_OPT_FLOW_CONTROL	0x00000040
++
++/**
++ * struct dpni_congestion_notification_cfg - congestion notification
++ *					configuration
++ * @units: Units type
++ * @threshold_entry: Above this threshold we enter a congestion state.
++ *		set it to '0' to disable it
++ * @threshold_exit: Below this threshold we exit the congestion state.
++ * @message_ctx: The context that will be part of the CSCN message
++ * @message_iova: I/O virtual address (must be in DMA-able memory),
++ *		must be 16B aligned; valid only if 'DPNI_CONG_OPT_WRITE_MEM_<X>'
++ *		is contained in 'options'
++ * @dest_cfg: CSCN can be send to either DPIO or DPCON WQ channel
++ * @notification_mode: Mask of available options; use 'DPNI_CONG_OPT_<X>' values
++ */
++
++struct dpni_congestion_notification_cfg {
++	enum dpni_congestion_unit units;
++	u32 threshold_entry;
++	u32 threshold_exit;
++	u64 message_ctx;
++	u64 message_iova;
++	struct dpni_dest_cfg dest_cfg;
++	u16 notification_mode;
++};
++
++/** Compose TC parameter for function dpni_set_congestion_notification()
++ * and dpni_get_congestion_notification().
++ */
++#define DPNI_BUILD_CH_TC(ceetm_ch_idx, tc) \
++	((((ceetm_ch_idx) & 0x0F) << 4) | ((tc) & 0x0F))
++
++int dpni_set_congestion_notification(
++			struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			enum dpni_queue_type qtype,
++			u8 tc_id,
++			const struct dpni_congestion_notification_cfg *cfg);
++
++int dpni_get_congestion_notification(
++			struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			enum dpni_queue_type qtype,
++			u8 tc_id,
++			struct dpni_congestion_notification_cfg *cfg);
++
++/**
++ * struct dpni_taildrop - Structure representing the taildrop
++ * @enable:	Indicates whether the taildrop is active or not.
++ * @units:	Indicates the unit of THRESHOLD. Queue taildrop only supports
++ *		byte units, this field is ignored and assumed = 0 if
++ *		CONGESTION_POINT is 0.
++ * @threshold:	Threshold value, in units identified by UNITS field. Value 0
++ *		cannot be used as a valid taildrop threshold, THRESHOLD must
++ *		be > 0 if the taildrop is enabled.
++ */
++struct dpni_taildrop {
++	char enable;
++	enum dpni_congestion_unit units;
++	u32 threshold;
++};
++
++int dpni_set_taildrop(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      enum dpni_congestion_point cg_point,
++		      enum dpni_queue_type q_type,
++		      u8 tc,
++		      u8 q_index,
++		      struct dpni_taildrop *taildrop);
++
++int dpni_get_taildrop(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      enum dpni_congestion_point cg_point,
++		      enum dpni_queue_type q_type,
++		      u8 tc,
++		      u8 q_index,
++		      struct dpni_taildrop *taildrop);
++
++/**
++ * struct dpni_rule_cfg - Rule configuration for table lookup
++ * @key_iova: I/O virtual address of the key (must be in DMA-able memory)
++ * @mask_iova: I/O virtual address of the mask (must be in DMA-able memory)
++ * @key_size: key and mask size (in bytes)
++ */
++struct dpni_rule_cfg {
++	u64	key_iova;
++	u64	mask_iova;
++	u8	key_size;
++};
++
++int dpni_get_api_version(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 *major_ver,
++			 u16 *minor_ver);
++
++int dpni_add_qos_entry(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       const struct dpni_rule_cfg *cfg,
++		       u8 tc_id,
++		       u16 index);
++
++int dpni_remove_qos_entry(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  const struct dpni_rule_cfg *cfg);
++
++int dpni_clear_qos_table(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token);
++
++/**
++ * Discard matching traffic. If set, this takes precedence over any other
++ * configuration and matching traffic is always discarded.
++ */
++ #define DPNI_FS_OPT_DISCARD            0x1
++
++/**
++ * Set FLC value. If set, flc member of struct dpni_fs_action_cfg is used to
++ * override the FLC value set per queue.
++ * For more details check the Frame Descriptor section in the hardware
++ * documentation.
++ */
++#define DPNI_FS_OPT_SET_FLC            0x2
++
++/*
++ * Indicates whether the 6 lowest significant bits of FLC are used for stash
++ * control. If set, the 6 least significant bits in value are interpreted as
++ * follows:
++ *     - bits 0-1: indicates the number of 64 byte units of context that are
++ *     stashed. FLC value is interpreted as a memory address in this case,
++ *     excluding the 6 LS bits.
++ *     - bits 2-3: indicates the number of 64 byte units of frame annotation
++ *     to be stashed. Annotation is placed at FD[ADDR].
++ *     - bits 4-5: indicates the number of 64 byte units of frame data to be
++ *     stashed. Frame data is placed at FD[ADDR] + FD[OFFSET].
++ * This flag is ignored if DPNI_FS_OPT_SET_FLC is not specified.
++ */
++#define DPNI_FS_OPT_SET_STASH_CONTROL  0x4
++
++/**
++ * struct dpni_fs_action_cfg - Action configuration for table look-up
++ * @flc:	FLC value for traffic matching this rule. Please check the
++ *		Frame Descriptor section in the hardware documentation for
++ *		more information.
++ * @flow_id:	Identifies the Rx queue used for matching traffic. Supported
++ *		values are in range 0 to num_queue-1.
++ * @options:	Any combination of DPNI_FS_OPT_ values.
++ */
++struct dpni_fs_action_cfg {
++	u64 flc;
++	u16 flow_id;
++	u16 options;
++};
++
++int dpni_add_fs_entry(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      u8 tc_id,
++		      u16 index,
++		      const struct dpni_rule_cfg *cfg,
++		      const struct dpni_fs_action_cfg *action);
++
++int dpni_remove_fs_entry(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u8 tc_id,
++			 const struct dpni_rule_cfg *cfg);
++
++/**
++ * When used for queue_idx in function dpni_set_rx_dist_default_queue
++ * will signal to dpni to drop all unclassified frames
++ */
++#define DPNI_FS_MISS_DROP		((uint16_t)-1)
++
++/**
++ * struct dpni_rx_dist_cfg - distribution configuration
++ * @dist_size:	distribution size; supported values: 1,2,3,4,6,7,8,
++ *		12,14,16,24,28,32,48,56,64,96,112,128,192,224,256,384,448,
++ *		512,768,896,1024
++ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with
++ *		the extractions to be used for the distribution key by calling
++ *		dpkg_prepare_key_cfg() relevant only when enable!=0 otherwise
++ *		it can be '0'
++ * @enable: enable/disable the distribution.
++ * @tc: TC id for which distribution is set
++ * @fs_miss_flow_id: when packet misses all rules from flow steering table and
++ *		hash is disabled it will be put into this queue id; use
++ *		DPNI_FS_MISS_DROP to drop frames. The value of this field is
++ *		used only when flow steering distribution is enabled and hash
++ *		distribution is disabled
++ */
++struct dpni_rx_dist_cfg {
++	u16 dist_size;
++	u64 key_cfg_iova;
++	u8 enable;
++	u8 tc;
++	u16 fs_miss_flow_id;
++};
++
++int dpni_set_rx_fs_dist(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			const struct dpni_rx_dist_cfg *cfg);
++
++int dpni_set_rx_hash_dist(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  const struct dpni_rx_dist_cfg *cfg);
++
++#endif /* __FSL_DPNI_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethernet/net.h
+@@ -0,0 +1,480 @@
++/* Copyright 2013-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef __FSL_NET_H
++#define __FSL_NET_H
++
++#define LAST_HDR_INDEX 0xFFFFFFFF
++
++/*****************************************************************************/
++/*                Protocol fields                                            */
++/*****************************************************************************/
++
++/*************************  Ethernet fields  *********************************/
++#define NH_FLD_ETH_DA                         (1)
++#define NH_FLD_ETH_SA                         (NH_FLD_ETH_DA << 1)
++#define NH_FLD_ETH_LENGTH                     (NH_FLD_ETH_DA << 2)
++#define NH_FLD_ETH_TYPE                       (NH_FLD_ETH_DA << 3)
++#define NH_FLD_ETH_FINAL_CKSUM                (NH_FLD_ETH_DA << 4)
++#define NH_FLD_ETH_PADDING                    (NH_FLD_ETH_DA << 5)
++#define NH_FLD_ETH_ALL_FIELDS                 ((NH_FLD_ETH_DA << 6) - 1)
++
++#define NH_FLD_ETH_ADDR_SIZE                 6
++
++/***************************  VLAN fields  ***********************************/
++#define NH_FLD_VLAN_VPRI                      (1)
++#define NH_FLD_VLAN_CFI                       (NH_FLD_VLAN_VPRI << 1)
++#define NH_FLD_VLAN_VID                       (NH_FLD_VLAN_VPRI << 2)
++#define NH_FLD_VLAN_LENGTH                    (NH_FLD_VLAN_VPRI << 3)
++#define NH_FLD_VLAN_TYPE                      (NH_FLD_VLAN_VPRI << 4)
++#define NH_FLD_VLAN_ALL_FIELDS                ((NH_FLD_VLAN_VPRI << 5) - 1)
++
++#define NH_FLD_VLAN_TCI                       (NH_FLD_VLAN_VPRI | \
++					       NH_FLD_VLAN_CFI | \
++					       NH_FLD_VLAN_VID)
++
++/************************  IP (generic) fields  ******************************/
++#define NH_FLD_IP_VER                         (1)
++#define NH_FLD_IP_DSCP                        (NH_FLD_IP_VER << 2)
++#define NH_FLD_IP_ECN                         (NH_FLD_IP_VER << 3)
++#define NH_FLD_IP_PROTO                       (NH_FLD_IP_VER << 4)
++#define NH_FLD_IP_SRC                         (NH_FLD_IP_VER << 5)
++#define NH_FLD_IP_DST                         (NH_FLD_IP_VER << 6)
++#define NH_FLD_IP_TOS_TC                      (NH_FLD_IP_VER << 7)
++#define NH_FLD_IP_ID                          (NH_FLD_IP_VER << 8)
++#define NH_FLD_IP_ALL_FIELDS                  ((NH_FLD_IP_VER << 9) - 1)
++
++#define NH_FLD_IP_PROTO_SIZE                  1
++
++/*****************************  IPV4 fields  *********************************/
++#define NH_FLD_IPV4_VER                       (1)
++#define NH_FLD_IPV4_HDR_LEN                   (NH_FLD_IPV4_VER << 1)
++#define NH_FLD_IPV4_TOS                       (NH_FLD_IPV4_VER << 2)
++#define NH_FLD_IPV4_TOTAL_LEN                 (NH_FLD_IPV4_VER << 3)
++#define NH_FLD_IPV4_ID                        (NH_FLD_IPV4_VER << 4)
++#define NH_FLD_IPV4_FLAG_D                    (NH_FLD_IPV4_VER << 5)
++#define NH_FLD_IPV4_FLAG_M                    (NH_FLD_IPV4_VER << 6)
++#define NH_FLD_IPV4_OFFSET                    (NH_FLD_IPV4_VER << 7)
++#define NH_FLD_IPV4_TTL                       (NH_FLD_IPV4_VER << 8)
++#define NH_FLD_IPV4_PROTO                     (NH_FLD_IPV4_VER << 9)
++#define NH_FLD_IPV4_CKSUM                     (NH_FLD_IPV4_VER << 10)
++#define NH_FLD_IPV4_SRC_IP                    (NH_FLD_IPV4_VER << 11)
++#define NH_FLD_IPV4_DST_IP                    (NH_FLD_IPV4_VER << 12)
++#define NH_FLD_IPV4_OPTS                      (NH_FLD_IPV4_VER << 13)
++#define NH_FLD_IPV4_OPTS_COUNT                (NH_FLD_IPV4_VER << 14)
++#define NH_FLD_IPV4_ALL_FIELDS                ((NH_FLD_IPV4_VER << 15) - 1)
++
++#define NH_FLD_IPV4_ADDR_SIZE                 4
++#define NH_FLD_IPV4_PROTO_SIZE                1
++
++/*****************************  IPV6 fields  *********************************/
++#define NH_FLD_IPV6_VER                       (1)
++#define NH_FLD_IPV6_TC                        (NH_FLD_IPV6_VER << 1)
++#define NH_FLD_IPV6_SRC_IP                    (NH_FLD_IPV6_VER << 2)
++#define NH_FLD_IPV6_DST_IP                    (NH_FLD_IPV6_VER << 3)
++#define NH_FLD_IPV6_NEXT_HDR                  (NH_FLD_IPV6_VER << 4)
++#define NH_FLD_IPV6_FL                        (NH_FLD_IPV6_VER << 5)
++#define NH_FLD_IPV6_HOP_LIMIT                 (NH_FLD_IPV6_VER << 6)
++#define NH_FLD_IPV6_ID			      (NH_FLD_IPV6_VER << 7)
++#define NH_FLD_IPV6_ALL_FIELDS                ((NH_FLD_IPV6_VER << 8) - 1)
++
++#define NH_FLD_IPV6_ADDR_SIZE                 16
++#define NH_FLD_IPV6_NEXT_HDR_SIZE             1
++
++/*****************************  ICMP fields  *********************************/
++#define NH_FLD_ICMP_TYPE                      (1)
++#define NH_FLD_ICMP_CODE                      (NH_FLD_ICMP_TYPE << 1)
++#define NH_FLD_ICMP_CKSUM                     (NH_FLD_ICMP_TYPE << 2)
++#define NH_FLD_ICMP_ID                        (NH_FLD_ICMP_TYPE << 3)
++#define NH_FLD_ICMP_SQ_NUM                    (NH_FLD_ICMP_TYPE << 4)
++#define NH_FLD_ICMP_ALL_FIELDS                ((NH_FLD_ICMP_TYPE << 5) - 1)
++
++#define NH_FLD_ICMP_CODE_SIZE                 1
++#define NH_FLD_ICMP_TYPE_SIZE                 1
++
++/*****************************  IGMP fields  *********************************/
++#define NH_FLD_IGMP_VERSION                   (1)
++#define NH_FLD_IGMP_TYPE                      (NH_FLD_IGMP_VERSION << 1)
++#define NH_FLD_IGMP_CKSUM                     (NH_FLD_IGMP_VERSION << 2)
++#define NH_FLD_IGMP_DATA                      (NH_FLD_IGMP_VERSION << 3)
++#define NH_FLD_IGMP_ALL_FIELDS                ((NH_FLD_IGMP_VERSION << 4) - 1)
++
++/*****************************  TCP fields  **********************************/
++#define NH_FLD_TCP_PORT_SRC                   (1)
++#define NH_FLD_TCP_PORT_DST                   (NH_FLD_TCP_PORT_SRC << 1)
++#define NH_FLD_TCP_SEQ                        (NH_FLD_TCP_PORT_SRC << 2)
++#define NH_FLD_TCP_ACK                        (NH_FLD_TCP_PORT_SRC << 3)
++#define NH_FLD_TCP_OFFSET                     (NH_FLD_TCP_PORT_SRC << 4)
++#define NH_FLD_TCP_FLAGS                      (NH_FLD_TCP_PORT_SRC << 5)
++#define NH_FLD_TCP_WINDOW                     (NH_FLD_TCP_PORT_SRC << 6)
++#define NH_FLD_TCP_CKSUM                      (NH_FLD_TCP_PORT_SRC << 7)
++#define NH_FLD_TCP_URGPTR                     (NH_FLD_TCP_PORT_SRC << 8)
++#define NH_FLD_TCP_OPTS                       (NH_FLD_TCP_PORT_SRC << 9)
++#define NH_FLD_TCP_OPTS_COUNT                 (NH_FLD_TCP_PORT_SRC << 10)
++#define NH_FLD_TCP_ALL_FIELDS                 ((NH_FLD_TCP_PORT_SRC << 11) - 1)
++
++#define NH_FLD_TCP_PORT_SIZE                  2
++
++/*****************************  UDP fields  **********************************/
++#define NH_FLD_UDP_PORT_SRC                   (1)
++#define NH_FLD_UDP_PORT_DST                   (NH_FLD_UDP_PORT_SRC << 1)
++#define NH_FLD_UDP_LEN                        (NH_FLD_UDP_PORT_SRC << 2)
++#define NH_FLD_UDP_CKSUM                      (NH_FLD_UDP_PORT_SRC << 3)
++#define NH_FLD_UDP_ALL_FIELDS                 ((NH_FLD_UDP_PORT_SRC << 4) - 1)
++
++#define NH_FLD_UDP_PORT_SIZE                  2
++
++/***************************  UDP-lite fields  *******************************/
++#define NH_FLD_UDP_LITE_PORT_SRC              (1)
++#define NH_FLD_UDP_LITE_PORT_DST              (NH_FLD_UDP_LITE_PORT_SRC << 1)
++#define NH_FLD_UDP_LITE_ALL_FIELDS \
++	((NH_FLD_UDP_LITE_PORT_SRC << 2) - 1)
++
++#define NH_FLD_UDP_LITE_PORT_SIZE             2
++
++/***************************  UDP-encap-ESP fields  **************************/
++#define NH_FLD_UDP_ENC_ESP_PORT_SRC         (1)
++#define NH_FLD_UDP_ENC_ESP_PORT_DST         (NH_FLD_UDP_ENC_ESP_PORT_SRC << 1)
++#define NH_FLD_UDP_ENC_ESP_LEN              (NH_FLD_UDP_ENC_ESP_PORT_SRC << 2)
++#define NH_FLD_UDP_ENC_ESP_CKSUM            (NH_FLD_UDP_ENC_ESP_PORT_SRC << 3)
++#define NH_FLD_UDP_ENC_ESP_SPI              (NH_FLD_UDP_ENC_ESP_PORT_SRC << 4)
++#define NH_FLD_UDP_ENC_ESP_SEQUENCE_NUM     (NH_FLD_UDP_ENC_ESP_PORT_SRC << 5)
++#define NH_FLD_UDP_ENC_ESP_ALL_FIELDS \
++	((NH_FLD_UDP_ENC_ESP_PORT_SRC << 6) - 1)
++
++#define NH_FLD_UDP_ENC_ESP_PORT_SIZE        2
++#define NH_FLD_UDP_ENC_ESP_SPI_SIZE         4
++
++/*****************************  SCTP fields  *********************************/
++#define NH_FLD_SCTP_PORT_SRC                  (1)
++#define NH_FLD_SCTP_PORT_DST                  (NH_FLD_SCTP_PORT_SRC << 1)
++#define NH_FLD_SCTP_VER_TAG                   (NH_FLD_SCTP_PORT_SRC << 2)
++#define NH_FLD_SCTP_CKSUM                     (NH_FLD_SCTP_PORT_SRC << 3)
++#define NH_FLD_SCTP_ALL_FIELDS                ((NH_FLD_SCTP_PORT_SRC << 4) - 1)
++
++#define NH_FLD_SCTP_PORT_SIZE                 2
++
++/*****************************  DCCP fields  *********************************/
++#define NH_FLD_DCCP_PORT_SRC                  (1)
++#define NH_FLD_DCCP_PORT_DST                  (NH_FLD_DCCP_PORT_SRC << 1)
++#define NH_FLD_DCCP_ALL_FIELDS                ((NH_FLD_DCCP_PORT_SRC << 2) - 1)
++
++#define NH_FLD_DCCP_PORT_SIZE                 2
++
++/*****************************  IPHC fields  *********************************/
++#define NH_FLD_IPHC_CID                       (1)
++#define NH_FLD_IPHC_CID_TYPE                  (NH_FLD_IPHC_CID << 1)
++#define NH_FLD_IPHC_HCINDEX                   (NH_FLD_IPHC_CID << 2)
++#define NH_FLD_IPHC_GEN                       (NH_FLD_IPHC_CID << 3)
++#define NH_FLD_IPHC_D_BIT                     (NH_FLD_IPHC_CID << 4)
++#define NH_FLD_IPHC_ALL_FIELDS                ((NH_FLD_IPHC_CID << 5) - 1)
++
++/*****************************  SCTP fields  *********************************/
++#define NH_FLD_SCTP_CHUNK_DATA_TYPE           (1)
++#define NH_FLD_SCTP_CHUNK_DATA_FLAGS          (NH_FLD_SCTP_CHUNK_DATA_TYPE << 1)
++#define NH_FLD_SCTP_CHUNK_DATA_LENGTH         (NH_FLD_SCTP_CHUNK_DATA_TYPE << 2)
++#define NH_FLD_SCTP_CHUNK_DATA_TSN            (NH_FLD_SCTP_CHUNK_DATA_TYPE << 3)
++#define NH_FLD_SCTP_CHUNK_DATA_STREAM_ID      (NH_FLD_SCTP_CHUNK_DATA_TYPE << 4)
++#define NH_FLD_SCTP_CHUNK_DATA_STREAM_SQN     (NH_FLD_SCTP_CHUNK_DATA_TYPE << 5)
++#define NH_FLD_SCTP_CHUNK_DATA_PAYLOAD_PID    (NH_FLD_SCTP_CHUNK_DATA_TYPE << 6)
++#define NH_FLD_SCTP_CHUNK_DATA_UNORDERED      (NH_FLD_SCTP_CHUNK_DATA_TYPE << 7)
++#define NH_FLD_SCTP_CHUNK_DATA_BEGGINING      (NH_FLD_SCTP_CHUNK_DATA_TYPE << 8)
++#define NH_FLD_SCTP_CHUNK_DATA_END            (NH_FLD_SCTP_CHUNK_DATA_TYPE << 9)
++#define NH_FLD_SCTP_CHUNK_DATA_ALL_FIELDS \
++	((NH_FLD_SCTP_CHUNK_DATA_TYPE << 10) - 1)
++
++/***************************  L2TPV2 fields  *********************************/
++#define NH_FLD_L2TPV2_TYPE_BIT                (1)
++#define NH_FLD_L2TPV2_LENGTH_BIT              (NH_FLD_L2TPV2_TYPE_BIT << 1)
++#define NH_FLD_L2TPV2_SEQUENCE_BIT            (NH_FLD_L2TPV2_TYPE_BIT << 2)
++#define NH_FLD_L2TPV2_OFFSET_BIT              (NH_FLD_L2TPV2_TYPE_BIT << 3)
++#define NH_FLD_L2TPV2_PRIORITY_BIT            (NH_FLD_L2TPV2_TYPE_BIT << 4)
++#define NH_FLD_L2TPV2_VERSION                 (NH_FLD_L2TPV2_TYPE_BIT << 5)
++#define NH_FLD_L2TPV2_LEN                     (NH_FLD_L2TPV2_TYPE_BIT << 6)
++#define NH_FLD_L2TPV2_TUNNEL_ID               (NH_FLD_L2TPV2_TYPE_BIT << 7)
++#define NH_FLD_L2TPV2_SESSION_ID              (NH_FLD_L2TPV2_TYPE_BIT << 8)
++#define NH_FLD_L2TPV2_NS                      (NH_FLD_L2TPV2_TYPE_BIT << 9)
++#define NH_FLD_L2TPV2_NR                      (NH_FLD_L2TPV2_TYPE_BIT << 10)
++#define NH_FLD_L2TPV2_OFFSET_SIZE             (NH_FLD_L2TPV2_TYPE_BIT << 11)
++#define NH_FLD_L2TPV2_FIRST_BYTE              (NH_FLD_L2TPV2_TYPE_BIT << 12)
++#define NH_FLD_L2TPV2_ALL_FIELDS \
++	((NH_FLD_L2TPV2_TYPE_BIT << 13) - 1)
++
++/***************************  L2TPV3 fields  *********************************/
++#define NH_FLD_L2TPV3_CTRL_TYPE_BIT           (1)
++#define NH_FLD_L2TPV3_CTRL_LENGTH_BIT         (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 1)
++#define NH_FLD_L2TPV3_CTRL_SEQUENCE_BIT       (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 2)
++#define NH_FLD_L2TPV3_CTRL_VERSION            (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 3)
++#define NH_FLD_L2TPV3_CTRL_LENGTH             (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 4)
++#define NH_FLD_L2TPV3_CTRL_CONTROL            (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 5)
++#define NH_FLD_L2TPV3_CTRL_SENT               (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 6)
++#define NH_FLD_L2TPV3_CTRL_RECV               (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 7)
++#define NH_FLD_L2TPV3_CTRL_FIRST_BYTE         (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 8)
++#define NH_FLD_L2TPV3_CTRL_ALL_FIELDS \
++	((NH_FLD_L2TPV3_CTRL_TYPE_BIT << 9) - 1)
++
++#define NH_FLD_L2TPV3_SESS_TYPE_BIT           (1)
++#define NH_FLD_L2TPV3_SESS_VERSION            (NH_FLD_L2TPV3_SESS_TYPE_BIT << 1)
++#define NH_FLD_L2TPV3_SESS_ID                 (NH_FLD_L2TPV3_SESS_TYPE_BIT << 2)
++#define NH_FLD_L2TPV3_SESS_COOKIE             (NH_FLD_L2TPV3_SESS_TYPE_BIT << 3)
++#define NH_FLD_L2TPV3_SESS_ALL_FIELDS \
++	((NH_FLD_L2TPV3_SESS_TYPE_BIT << 4) - 1)
++
++/****************************  PPP fields  ***********************************/
++#define NH_FLD_PPP_PID                        (1)
++#define NH_FLD_PPP_COMPRESSED                 (NH_FLD_PPP_PID << 1)
++#define NH_FLD_PPP_ALL_FIELDS                 ((NH_FLD_PPP_PID << 2) - 1)
++
++/**************************  PPPoE fields  ***********************************/
++#define NH_FLD_PPPOE_VER                      (1)
++#define NH_FLD_PPPOE_TYPE                     (NH_FLD_PPPOE_VER << 1)
++#define NH_FLD_PPPOE_CODE                     (NH_FLD_PPPOE_VER << 2)
++#define NH_FLD_PPPOE_SID                      (NH_FLD_PPPOE_VER << 3)
++#define NH_FLD_PPPOE_LEN                      (NH_FLD_PPPOE_VER << 4)
++#define NH_FLD_PPPOE_SESSION                  (NH_FLD_PPPOE_VER << 5)
++#define NH_FLD_PPPOE_PID                      (NH_FLD_PPPOE_VER << 6)
++#define NH_FLD_PPPOE_ALL_FIELDS               ((NH_FLD_PPPOE_VER << 7) - 1)
++
++/*************************  PPP-Mux fields  **********************************/
++#define NH_FLD_PPPMUX_PID                     (1)
++#define NH_FLD_PPPMUX_CKSUM                   (NH_FLD_PPPMUX_PID << 1)
++#define NH_FLD_PPPMUX_COMPRESSED              (NH_FLD_PPPMUX_PID << 2)
++#define NH_FLD_PPPMUX_ALL_FIELDS              ((NH_FLD_PPPMUX_PID << 3) - 1)
++
++/***********************  PPP-Mux sub-frame fields  **************************/
++#define NH_FLD_PPPMUX_SUBFRM_PFF            (1)
++#define NH_FLD_PPPMUX_SUBFRM_LXT            (NH_FLD_PPPMUX_SUBFRM_PFF << 1)
++#define NH_FLD_PPPMUX_SUBFRM_LEN            (NH_FLD_PPPMUX_SUBFRM_PFF << 2)
++#define NH_FLD_PPPMUX_SUBFRM_PID            (NH_FLD_PPPMUX_SUBFRM_PFF << 3)
++#define NH_FLD_PPPMUX_SUBFRM_USE_PID        (NH_FLD_PPPMUX_SUBFRM_PFF << 4)
++#define NH_FLD_PPPMUX_SUBFRM_ALL_FIELDS \
++	((NH_FLD_PPPMUX_SUBFRM_PFF << 5) - 1)
++
++/***************************  LLC fields  ************************************/
++#define NH_FLD_LLC_DSAP                       (1)
++#define NH_FLD_LLC_SSAP                       (NH_FLD_LLC_DSAP << 1)
++#define NH_FLD_LLC_CTRL                       (NH_FLD_LLC_DSAP << 2)
++#define NH_FLD_LLC_ALL_FIELDS                 ((NH_FLD_LLC_DSAP << 3) - 1)
++
++/***************************  NLPID fields  **********************************/
++#define NH_FLD_NLPID_NLPID                    (1)
++#define NH_FLD_NLPID_ALL_FIELDS               ((NH_FLD_NLPID_NLPID << 1) - 1)
++
++/***************************  SNAP fields  ***********************************/
++#define NH_FLD_SNAP_OUI                       (1)
++#define NH_FLD_SNAP_PID                       (NH_FLD_SNAP_OUI << 1)
++#define NH_FLD_SNAP_ALL_FIELDS                ((NH_FLD_SNAP_OUI << 2) - 1)
++
++/***************************  LLC SNAP fields  *******************************/
++#define NH_FLD_LLC_SNAP_TYPE                  (1)
++#define NH_FLD_LLC_SNAP_ALL_FIELDS            ((NH_FLD_LLC_SNAP_TYPE << 1) - 1)
++
++#define NH_FLD_ARP_HTYPE                      (1)
++#define NH_FLD_ARP_PTYPE                      (NH_FLD_ARP_HTYPE << 1)
++#define NH_FLD_ARP_HLEN                       (NH_FLD_ARP_HTYPE << 2)
++#define NH_FLD_ARP_PLEN                       (NH_FLD_ARP_HTYPE << 3)
++#define NH_FLD_ARP_OPER                       (NH_FLD_ARP_HTYPE << 4)
++#define NH_FLD_ARP_SHA                        (NH_FLD_ARP_HTYPE << 5)
++#define NH_FLD_ARP_SPA                        (NH_FLD_ARP_HTYPE << 6)
++#define NH_FLD_ARP_THA                        (NH_FLD_ARP_HTYPE << 7)
++#define NH_FLD_ARP_TPA                        (NH_FLD_ARP_HTYPE << 8)
++#define NH_FLD_ARP_ALL_FIELDS                 ((NH_FLD_ARP_HTYPE << 9) - 1)
++
++/***************************  RFC2684 fields  ********************************/
++#define NH_FLD_RFC2684_LLC                    (1)
++#define NH_FLD_RFC2684_NLPID                  (NH_FLD_RFC2684_LLC << 1)
++#define NH_FLD_RFC2684_OUI                    (NH_FLD_RFC2684_LLC << 2)
++#define NH_FLD_RFC2684_PID                    (NH_FLD_RFC2684_LLC << 3)
++#define NH_FLD_RFC2684_VPN_OUI                (NH_FLD_RFC2684_LLC << 4)
++#define NH_FLD_RFC2684_VPN_IDX                (NH_FLD_RFC2684_LLC << 5)
++#define NH_FLD_RFC2684_ALL_FIELDS             ((NH_FLD_RFC2684_LLC << 6) - 1)
++
++/***************************  User defined fields  ***************************/
++#define NH_FLD_USER_DEFINED_SRCPORT           (1)
++#define NH_FLD_USER_DEFINED_PCDID             (NH_FLD_USER_DEFINED_SRCPORT << 1)
++#define NH_FLD_USER_DEFINED_ALL_FIELDS \
++	((NH_FLD_USER_DEFINED_SRCPORT << 2) - 1)
++
++/***************************  Payload fields  ********************************/
++#define NH_FLD_PAYLOAD_BUFFER                 (1)
++#define NH_FLD_PAYLOAD_SIZE                   (NH_FLD_PAYLOAD_BUFFER << 1)
++#define NH_FLD_MAX_FRM_SIZE                   (NH_FLD_PAYLOAD_BUFFER << 2)
++#define NH_FLD_MIN_FRM_SIZE                   (NH_FLD_PAYLOAD_BUFFER << 3)
++#define NH_FLD_PAYLOAD_TYPE                   (NH_FLD_PAYLOAD_BUFFER << 4)
++#define NH_FLD_FRAME_SIZE                     (NH_FLD_PAYLOAD_BUFFER << 5)
++#define NH_FLD_PAYLOAD_ALL_FIELDS             ((NH_FLD_PAYLOAD_BUFFER << 6) - 1)
++
++/***************************  GRE fields  ************************************/
++#define NH_FLD_GRE_TYPE                       (1)
++#define NH_FLD_GRE_ALL_FIELDS                 ((NH_FLD_GRE_TYPE << 1) - 1)
++
++/***************************  MINENCAP fields  *******************************/
++#define NH_FLD_MINENCAP_SRC_IP                (1)
++#define NH_FLD_MINENCAP_DST_IP                (NH_FLD_MINENCAP_SRC_IP << 1)
++#define NH_FLD_MINENCAP_TYPE                  (NH_FLD_MINENCAP_SRC_IP << 2)
++#define NH_FLD_MINENCAP_ALL_FIELDS \
++	((NH_FLD_MINENCAP_SRC_IP << 3) - 1)
++
++/***************************  IPSEC AH fields  *******************************/
++#define NH_FLD_IPSEC_AH_SPI                   (1)
++#define NH_FLD_IPSEC_AH_NH                    (NH_FLD_IPSEC_AH_SPI << 1)
++#define NH_FLD_IPSEC_AH_ALL_FIELDS            ((NH_FLD_IPSEC_AH_SPI << 2) - 1)
++
++/***************************  IPSEC ESP fields  ******************************/
++#define NH_FLD_IPSEC_ESP_SPI                  (1)
++#define NH_FLD_IPSEC_ESP_SEQUENCE_NUM         (NH_FLD_IPSEC_ESP_SPI << 1)
++#define NH_FLD_IPSEC_ESP_ALL_FIELDS           ((NH_FLD_IPSEC_ESP_SPI << 2) - 1)
++
++#define NH_FLD_IPSEC_ESP_SPI_SIZE             4
++
++/***************************  MPLS fields  ***********************************/
++#define NH_FLD_MPLS_LABEL_STACK               (1)
++#define NH_FLD_MPLS_LABEL_STACK_ALL_FIELDS \
++	((NH_FLD_MPLS_LABEL_STACK << 1) - 1)
++
++/***************************  MACSEC fields  *********************************/
++#define NH_FLD_MACSEC_SECTAG                  (1)
++#define NH_FLD_MACSEC_ALL_FIELDS              ((NH_FLD_MACSEC_SECTAG << 1) - 1)
++
++/***************************  GTP fields  ************************************/
++#define NH_FLD_GTP_TEID                       (1)
++
++/* Protocol options */
++
++/* Ethernet options */
++#define	NH_OPT_ETH_BROADCAST			1
++#define	NH_OPT_ETH_MULTICAST			2
++#define	NH_OPT_ETH_UNICAST			3
++#define	NH_OPT_ETH_BPDU				4
++
++#define NH_ETH_IS_MULTICAST_ADDR(addr) (addr[0] & 0x01)
++/* also applicable for broadcast */
++
++/* VLAN options */
++#define	NH_OPT_VLAN_CFI				1
++
++/* IPV4 options */
++#define	NH_OPT_IPV4_UNICAST			1
++#define	NH_OPT_IPV4_MULTICAST			2
++#define	NH_OPT_IPV4_BROADCAST			3
++#define	NH_OPT_IPV4_OPTION			4
++#define	NH_OPT_IPV4_FRAG			5
++#define	NH_OPT_IPV4_INITIAL_FRAG		6
++
++/* IPV6 options */
++#define	NH_OPT_IPV6_UNICAST			1
++#define	NH_OPT_IPV6_MULTICAST			2
++#define	NH_OPT_IPV6_OPTION			3
++#define	NH_OPT_IPV6_FRAG			4
++#define	NH_OPT_IPV6_INITIAL_FRAG		5
++
++/* General IP options (may be used for any version) */
++#define	NH_OPT_IP_FRAG				1
++#define	NH_OPT_IP_INITIAL_FRAG			2
++#define	NH_OPT_IP_OPTION			3
++
++/* Minenc. options */
++#define	NH_OPT_MINENCAP_SRC_ADDR_PRESENT	1
++
++/* GRE. options */
++#define	NH_OPT_GRE_ROUTING_PRESENT		1
++
++/* TCP options */
++#define	NH_OPT_TCP_OPTIONS			1
++#define	NH_OPT_TCP_CONTROL_HIGH_BITS		2
++#define	NH_OPT_TCP_CONTROL_LOW_BITS		3
++
++/* CAPWAP options */
++#define	NH_OPT_CAPWAP_DTLS			1
++
++enum net_prot {
++	NET_PROT_NONE = 0,
++	NET_PROT_PAYLOAD,
++	NET_PROT_ETH,
++	NET_PROT_VLAN,
++	NET_PROT_IPV4,
++	NET_PROT_IPV6,
++	NET_PROT_IP,
++	NET_PROT_TCP,
++	NET_PROT_UDP,
++	NET_PROT_UDP_LITE,
++	NET_PROT_IPHC,
++	NET_PROT_SCTP,
++	NET_PROT_SCTP_CHUNK_DATA,
++	NET_PROT_PPPOE,
++	NET_PROT_PPP,
++	NET_PROT_PPPMUX,
++	NET_PROT_PPPMUX_SUBFRM,
++	NET_PROT_L2TPV2,
++	NET_PROT_L2TPV3_CTRL,
++	NET_PROT_L2TPV3_SESS,
++	NET_PROT_LLC,
++	NET_PROT_LLC_SNAP,
++	NET_PROT_NLPID,
++	NET_PROT_SNAP,
++	NET_PROT_MPLS,
++	NET_PROT_IPSEC_AH,
++	NET_PROT_IPSEC_ESP,
++	NET_PROT_UDP_ENC_ESP, /* RFC 3948 */
++	NET_PROT_MACSEC,
++	NET_PROT_GRE,
++	NET_PROT_MINENCAP,
++	NET_PROT_DCCP,
++	NET_PROT_ICMP,
++	NET_PROT_IGMP,
++	NET_PROT_ARP,
++	NET_PROT_CAPWAP_DATA,
++	NET_PROT_CAPWAP_CTRL,
++	NET_PROT_RFC2684,
++	NET_PROT_ICMPV6,
++	NET_PROT_FCOE,
++	NET_PROT_FIP,
++	NET_PROT_ISCSI,
++	NET_PROT_GTP,
++	NET_PROT_USER_DEFINED_L2,
++	NET_PROT_USER_DEFINED_L3,
++	NET_PROT_USER_DEFINED_L4,
++	NET_PROT_USER_DEFINED_L5,
++	NET_PROT_USER_DEFINED_SHIM1,
++	NET_PROT_USER_DEFINED_SHIM2,
++
++	NET_PROT_DUMMY_LAST
++};
++
++/*! IEEE8021.Q */
++#define NH_IEEE8021Q_ETYPE  0x8100
++#define NH_IEEE8021Q_HDR(etype, pcp, dei, vlan_id)	\
++	    ((((u32)((etype) & 0xFFFF)) << 16) |	\
++	    (((u32)((pcp) & 0x07)) << 13) |		\
++	    (((u32)((dei) & 0x01)) << 12) |		\
++	    (((u32)((vlan_id) & 0xFFF))))
++
++#endif /* __FSL_NET_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/Makefile
+@@ -0,0 +1,10 @@
++# SPDX-License-Identifier: GPL-2.0
++#
++# Makefile for the Freescale DPAA2 Ethernet Switch
++#
++# Copyright 2014-2017 Freescale Semiconductor, Inc.
++# Copyright 2017-2018 NXP
++
++obj-$(CONFIG_FSL_DPAA2_ETHSW) += dpaa2-ethsw.o
++
++dpaa2-ethsw-objs := ethsw.o ethsw-ethtool.o dpsw.o
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/README
+@@ -0,0 +1,106 @@
++DPAA2 Ethernet Switch driver
++============================
++
++This file provides documentation for the DPAA2 Ethernet Switch driver
++
++
++Contents
++========
++	Supported Platforms
++	Architecture Overview
++	Creating an Ethernet Switch
++	Features
++
++
++	Supported Platforms
++===================
++This driver provides networking support for Freescale LS2085A, LS2088A
++DPAA2 SoCs.
++
++
++Architecture Overview
++=====================
++The Ethernet Switch in the DPAA2 architecture consists of several hardware
++resources that provide the functionality. These are allocated and
++configured via the Management Complex (MC) portals. MC abstracts most of
++these resources as DPAA2 objects and exposes ABIs through which they can
++be configured and controlled.
++
++For a more detailed description of the DPAA2 architecture and its object
++abstractions see:
++	drivers/staging/fsl-mc/README.txt
++
++The Ethernet Switch is built on top of a Datapath Switch (DPSW) object.
++
++Configuration interface:
++
++          ---------------------
++         | DPAA2 Switch driver |
++          ---------------------
++                   .
++                   .
++              ----------
++             | DPSW API |
++              ----------
++                   .           software
++ ================= . ==============
++                   .           hardware
++          ---------------------
++         | MC hardware portals |
++          ---------------------
++                   .
++                   .
++                 ------
++                | DPSW |
++                 ------
++
++Driver uses the switch device driver model and exposes each switch port as
++a network interface, which can be included in a bridge. Traffic switched
++between ports is offloaded into the hardware. Exposed network interfaces
++are not used for I/O, they are used just for configuration. This
++limitation is going to be addressed in the future.
++
++The DPSW can have ports connected to DPNIs or to PHYs via DPMACs.
++
++
++ [ethA]     [ethB]     [ethC]     [ethD]     [ethE]     [ethF]
++    :          :          :          :          :          :
++    :          :          :          :          :          :
++[eth drv]  [eth drv]  [                ethsw drv              ]
++    :          :          :          :          :          :        kernel
++========================================================================
++    :          :          :          :          :          :        hardware
++ [DPNI]      [DPNI]     [============= DPSW =================]
++    |          |          |          |          |          |
++    |           ----------           |       [DPMAC]    [DPMAC]
++     -------------------------------            |          |
++                                                |          |
++                                              [PHY]      [PHY]
++
++For a more detailed description of the Ethernet switch device driver model
++see:
++	Documentation/networking/switchdev.txt
++
++Creating an Ethernet Switch
++===========================
++A device is created for the switch objects probed on the MC bus. Each DPSW
++has a number of properties which determine the configuration options and
++associated hardware resources.
++
++A DPSW object (and the other DPAA2 objects needed for a DPAA2 switch) can
++be added to a container on the MC bus in one of two ways: statically,
++through a Datapath Layout Binary file (DPL) that is parsed by MC at boot
++time; or created dynamically at runtime, via the DPAA2 objects APIs.
++
++Features
++========
++Driver configures DPSW to perform hardware switching offload of
++unicast/multicast/broadcast (VLAN tagged or untagged) traffic between its
++ports.
++
++It allows configuration of hardware learning, flooding, multicast groups,
++port VLAN configuration and STP state.
++
++Static entries can be added/removed from the FDB.
++
++Hardware statistics for each port are provided through ethtool -S option.
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/TODO
+@@ -0,0 +1,14 @@
++* Add I/O capabilities on switch port netdevices. This will allow control
++traffic to reach the CPU.
++* Add ACL to redirect control traffic to CPU.
++* Add support for displaying learned FDB entries
++* MC firmware uprev; the DPAA2 objects used by the Ethernet Switch driver
++need to   be kept in sync with binary interface changes in MC
++* refine README file
++* cleanup
++
++NOTE: At least first three of the above are required before getting the
++DPAA2 Ethernet Switch driver out of staging. Another requirement is that
++the fsl-mc bus driver is moved to drivers/bus and dpio driver is moved to
++drivers/soc (this is required for I/O).
++
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h
+@@ -0,0 +1,359 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2013-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017-2018 NXP
++ *
++ */
++
++#ifndef __FSL_DPSW_CMD_H
++#define __FSL_DPSW_CMD_H
++
++/* DPSW Version */
++#define DPSW_VER_MAJOR		8
++#define DPSW_VER_MINOR		0
++
++#define DPSW_CMD_BASE_VERSION	1
++#define DPSW_CMD_ID_OFFSET	4
++
++#define DPSW_CMD_ID(id)	(((id) << DPSW_CMD_ID_OFFSET) | DPSW_CMD_BASE_VERSION)
++
++/* Command IDs */
++#define DPSW_CMDID_CLOSE                    DPSW_CMD_ID(0x800)
++#define DPSW_CMDID_OPEN                     DPSW_CMD_ID(0x802)
++
++#define DPSW_CMDID_GET_API_VERSION          DPSW_CMD_ID(0xa02)
++
++#define DPSW_CMDID_ENABLE                   DPSW_CMD_ID(0x002)
++#define DPSW_CMDID_DISABLE                  DPSW_CMD_ID(0x003)
++#define DPSW_CMDID_GET_ATTR                 DPSW_CMD_ID(0x004)
++#define DPSW_CMDID_RESET                    DPSW_CMD_ID(0x005)
++
++#define DPSW_CMDID_SET_IRQ_ENABLE           DPSW_CMD_ID(0x012)
++
++#define DPSW_CMDID_SET_IRQ_MASK             DPSW_CMD_ID(0x014)
++
++#define DPSW_CMDID_GET_IRQ_STATUS           DPSW_CMD_ID(0x016)
++#define DPSW_CMDID_CLEAR_IRQ_STATUS         DPSW_CMD_ID(0x017)
++
++#define DPSW_CMDID_IF_SET_TCI               DPSW_CMD_ID(0x030)
++#define DPSW_CMDID_IF_SET_STP               DPSW_CMD_ID(0x031)
++
++#define DPSW_CMDID_IF_GET_COUNTER           DPSW_CMD_ID(0x034)
++
++#define DPSW_CMDID_IF_ENABLE                DPSW_CMD_ID(0x03D)
++#define DPSW_CMDID_IF_DISABLE               DPSW_CMD_ID(0x03E)
++
++#define DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH  DPSW_CMD_ID(0x044)
++
++#define DPSW_CMDID_IF_GET_LINK_STATE        DPSW_CMD_ID(0x046)
++#define DPSW_CMDID_IF_SET_FLOODING          DPSW_CMD_ID(0x047)
++#define DPSW_CMDID_IF_SET_BROADCAST         DPSW_CMD_ID(0x048)
++
++#define DPSW_CMDID_IF_GET_TCI               DPSW_CMD_ID(0x04A)
++
++#define DPSW_CMDID_IF_SET_LINK_CFG          DPSW_CMD_ID(0x04C)
++
++#define DPSW_CMDID_VLAN_ADD                 DPSW_CMD_ID(0x060)
++#define DPSW_CMDID_VLAN_ADD_IF              DPSW_CMD_ID(0x061)
++#define DPSW_CMDID_VLAN_ADD_IF_UNTAGGED     DPSW_CMD_ID(0x062)
++
++#define DPSW_CMDID_VLAN_REMOVE_IF           DPSW_CMD_ID(0x064)
++#define DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED  DPSW_CMD_ID(0x065)
++#define DPSW_CMDID_VLAN_REMOVE_IF_FLOODING  DPSW_CMD_ID(0x066)
++#define DPSW_CMDID_VLAN_REMOVE              DPSW_CMD_ID(0x067)
++
++#define DPSW_CMDID_FDB_ADD_UNICAST          DPSW_CMD_ID(0x084)
++#define DPSW_CMDID_FDB_REMOVE_UNICAST       DPSW_CMD_ID(0x085)
++#define DPSW_CMDID_FDB_ADD_MULTICAST        DPSW_CMD_ID(0x086)
++#define DPSW_CMDID_FDB_REMOVE_MULTICAST     DPSW_CMD_ID(0x087)
++#define DPSW_CMDID_FDB_SET_LEARNING_MODE    DPSW_CMD_ID(0x088)
++
++/* Macros for accessing command fields smaller than 1byte */
++#define DPSW_MASK(field)        \
++	GENMASK(DPSW_##field##_SHIFT + DPSW_##field##_SIZE - 1, \
++		DPSW_##field##_SHIFT)
++#define dpsw_set_field(var, field, val) \
++	((var) |= (((val) << DPSW_##field##_SHIFT) & DPSW_MASK(field)))
++#define dpsw_get_field(var, field)      \
++	(((var) & DPSW_MASK(field)) >> DPSW_##field##_SHIFT)
++#define dpsw_get_bit(var, bit) \
++	(((var)  >> (bit)) & GENMASK(0, 0))
++
++struct dpsw_cmd_open {
++	__le32 dpsw_id;
++};
++
++#define DPSW_COMPONENT_TYPE_SHIFT	0
++#define DPSW_COMPONENT_TYPE_SIZE	4
++
++struct dpsw_cmd_create {
++	/* cmd word 0 */
++	__le16 num_ifs;
++	u8 max_fdbs;
++	u8 max_meters_per_if;
++	/* from LSB: only the first 4 bits */
++	u8 component_type;
++	u8 pad[3];
++	/* cmd word 1 */
++	__le16 max_vlans;
++	__le16 max_fdb_entries;
++	__le16 fdb_aging_time;
++	__le16 max_fdb_mc_groups;
++	/* cmd word 2 */
++	__le64 options;
++};
++
++struct dpsw_cmd_destroy {
++	__le32 dpsw_id;
++};
++
++#define DPSW_ENABLE_SHIFT 0
++#define DPSW_ENABLE_SIZE  1
++
++struct dpsw_rsp_is_enabled {
++	/* from LSB: enable:1 */
++	u8 enabled;
++};
++
++struct dpsw_cmd_set_irq_enable {
++	u8 enable_state;
++	u8 pad[3];
++	u8 irq_index;
++};
++
++struct dpsw_cmd_get_irq_enable {
++	__le32 pad;
++	u8 irq_index;
++};
++
++struct dpsw_rsp_get_irq_enable {
++	u8 enable_state;
++};
++
++struct dpsw_cmd_set_irq_mask {
++	__le32 mask;
++	u8 irq_index;
++};
++
++struct dpsw_cmd_get_irq_mask {
++	__le32 pad;
++	u8 irq_index;
++};
++
++struct dpsw_rsp_get_irq_mask {
++	__le32 mask;
++};
++
++struct dpsw_cmd_get_irq_status {
++	__le32 status;
++	u8 irq_index;
++};
++
++struct dpsw_rsp_get_irq_status {
++	__le32 status;
++};
++
++struct dpsw_cmd_clear_irq_status {
++	__le32 status;
++	u8 irq_index;
++};
++
++#define DPSW_COMPONENT_TYPE_SHIFT	0
++#define DPSW_COMPONENT_TYPE_SIZE	4
++
++struct dpsw_rsp_get_attr {
++	/* cmd word 0 */
++	__le16 num_ifs;
++	u8 max_fdbs;
++	u8 num_fdbs;
++	__le16 max_vlans;
++	__le16 num_vlans;
++	/* cmd word 1 */
++	__le16 max_fdb_entries;
++	__le16 fdb_aging_time;
++	__le32 dpsw_id;
++	/* cmd word 2 */
++	__le16 mem_size;
++	__le16 max_fdb_mc_groups;
++	u8 max_meters_per_if;
++	/* from LSB only the first 4 bits */
++	u8 component_type;
++	__le16 pad;
++	/* cmd word 3 */
++	__le64 options;
++};
++
++struct dpsw_cmd_if_set_flooding {
++	__le16 if_id;
++	/* from LSB: enable:1 */
++	u8 enable;
++};
++
++struct dpsw_cmd_if_set_broadcast {
++	__le16 if_id;
++	/* from LSB: enable:1 */
++	u8 enable;
++};
++
++#define DPSW_VLAN_ID_SHIFT	0
++#define DPSW_VLAN_ID_SIZE	12
++#define DPSW_DEI_SHIFT		12
++#define DPSW_DEI_SIZE		1
++#define DPSW_PCP_SHIFT		13
++#define DPSW_PCP_SIZE		3
++
++struct dpsw_cmd_if_set_tci {
++	__le16 if_id;
++	/* from LSB: VLAN_ID:12 DEI:1 PCP:3 */
++	__le16 conf;
++};
++
++struct dpsw_cmd_if_get_tci {
++	__le16 if_id;
++};
++
++struct dpsw_rsp_if_get_tci {
++	__le16 pad;
++	__le16 vlan_id;
++	u8 dei;
++	u8 pcp;
++};
++
++#define DPSW_STATE_SHIFT	0
++#define DPSW_STATE_SIZE		4
++
++struct dpsw_cmd_if_set_stp {
++	__le16 if_id;
++	__le16 vlan_id;
++	/* only the first LSB 4 bits */
++	u8 state;
++};
++
++#define DPSW_COUNTER_TYPE_SHIFT		0
++#define DPSW_COUNTER_TYPE_SIZE		5
++
++struct dpsw_cmd_if_get_counter {
++	__le16 if_id;
++	/* from LSB: type:5 */
++	u8 type;
++};
++
++struct dpsw_rsp_if_get_counter {
++	__le64 pad;
++	__le64 counter;
++};
++
++struct dpsw_cmd_if {
++	__le16 if_id;
++};
++
++struct dpsw_cmd_if_set_max_frame_length {
++	__le16 if_id;
++	__le16 frame_length;
++};
++
++struct dpsw_cmd_if_set_link_cfg {
++	/* cmd word 0 */
++	__le16 if_id;
++	u8 pad[6];
++	/* cmd word 1 */
++	__le32 rate;
++	__le32 pad1;
++	/* cmd word 2 */
++	__le64 options;
++};
++
++struct dpsw_cmd_if_get_link_state {
++	__le16 if_id;
++};
++
++#define DPSW_UP_SHIFT	0
++#define DPSW_UP_SIZE	1
++
++struct dpsw_rsp_if_get_link_state {
++	/* cmd word 0 */
++	__le32 pad0;
++	u8 up;
++	u8 pad1[3];
++	/* cmd word 1 */
++	__le32 rate;
++	__le32 pad2;
++	/* cmd word 2 */
++	__le64 options;
++};
++
++struct dpsw_vlan_add {
++	__le16 fdb_id;
++	__le16 vlan_id;
++};
++
++struct dpsw_cmd_vlan_manage_if {
++	/* cmd word 0 */
++	__le16 pad0;
++	__le16 vlan_id;
++	__le32 pad1;
++	/* cmd word 1-4 */
++	__le64 if_id[4];
++};
++
++struct dpsw_cmd_vlan_remove {
++	__le16 pad;
++	__le16 vlan_id;
++};
++
++struct dpsw_cmd_fdb_add {
++	__le32 pad;
++	__le16 fdb_aging_time;
++	__le16 num_fdb_entries;
++};
++
++struct dpsw_rsp_fdb_add {
++	__le16 fdb_id;
++};
++
++struct dpsw_cmd_fdb_remove {
++	__le16 fdb_id;
++};
++
++#define DPSW_ENTRY_TYPE_SHIFT	0
++#define DPSW_ENTRY_TYPE_SIZE	4
++
++struct dpsw_cmd_fdb_unicast_op {
++	/* cmd word 0 */
++	__le16 fdb_id;
++	u8 mac_addr[6];
++	/* cmd word 1 */
++	__le16 if_egress;
++	/* only the first 4 bits from LSB */
++	u8 type;
++};
++
++struct dpsw_cmd_fdb_multicast_op {
++	/* cmd word 0 */
++	__le16 fdb_id;
++	__le16 num_ifs;
++	/* only the first 4 bits from LSB */
++	u8 type;
++	u8 pad[3];
++	/* cmd word 1 */
++	u8 mac_addr[6];
++	__le16 pad2;
++	/* cmd word 2-5 */
++	__le64 if_id[4];
++};
++
++#define DPSW_LEARNING_MODE_SHIFT	0
++#define DPSW_LEARNING_MODE_SIZE		4
++
++struct dpsw_cmd_fdb_set_learning_mode {
++	__le16 fdb_id;
++	/* only the first 4 bits from LSB */
++	u8 mode;
++};
++
++struct dpsw_rsp_get_api_version {
++	__le16 version_major;
++	__le16 version_minor;
++};
++
++#endif /* __FSL_DPSW_CMD_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw.c
+@@ -0,0 +1,1165 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2013-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017-2018 NXP
++ *
++ */
++
++#include <linux/fsl/mc.h>
++#include "dpsw.h"
++#include "dpsw-cmd.h"
++
++static void build_if_id_bitmap(__le64 *bmap,
++			       const u16 *id,
++			       const u16 num_ifs)
++{
++	int i;
++
++	for (i = 0; (i < num_ifs) && (i < DPSW_MAX_IF); i++) {
++		if (id[i] < DPSW_MAX_IF)
++			bmap[id[i] / 64] |= cpu_to_le64(BIT_MASK(id[i] % 64));
++	}
++}
++
++/**
++ * dpsw_open() - Open a control session for the specified object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @dpsw_id:	DPSW unique ID
++ * @token:	Returned token; use in subsequent API calls
++ *
++ * This function can be used to open a control session for an
++ * already created object; an object may have been declared in
++ * the DPL or by calling the dpsw_create() function.
++ * This function returns a unique authentication token,
++ * associated with the specific object ID and the specific MC
++ * portal; this token must be used in all subsequent commands for
++ * this specific object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpsw_open(struct fsl_mc_io *mc_io,
++	      u32 cmd_flags,
++	      int dpsw_id,
++	      u16 *token)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_open *cmd_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_OPEN,
++					  cmd_flags,
++					  0);
++	cmd_params = (struct dpsw_cmd_open *)cmd.params;
++	cmd_params->dpsw_id = cpu_to_le32(dpsw_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*token = mc_cmd_hdr_read_token(&cmd);
++
++	return 0;
++}
++
++/**
++ * dpsw_close() - Close the control session of the object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ *
++ * After this function is called, no further operations are
++ * allowed on the object without opening a new control session.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpsw_close(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLOSE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_enable() - Enable DPSW functionality
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_enable(struct fsl_mc_io *mc_io,
++		u32 cmd_flags,
++		u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_ENABLE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_disable() - Disable DPSW functionality
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_disable(struct fsl_mc_io *mc_io,
++		 u32 cmd_flags,
++		 u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_DISABLE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_reset() - Reset the DPSW, returns the object to initial state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpsw_reset(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_RESET,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_set_irq_enable() - Set overall interrupt state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPCI object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Interrupt state - enable = 1, disable = 0
++ *
++ * Allows GPP software to control when interrupts are generated.
++ * Each interrupt can have up to 32 causes.  The enable/disable control's the
++ * overall interrupt state. if the interrupt is disabled no causes will cause
++ * an interrupt
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpsw_set_irq_enable(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u8 en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_set_irq_enable *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_set_irq_enable *)cmd.params;
++	dpsw_set_field(cmd_params->enable_state, ENABLE, en);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_set_irq_mask() - Set interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPCI object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	Event mask to trigger interrupt;
++ *		each bit:
++ *			0 = ignore event
++ *			1 = consider event for asserting IRQ
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpsw_set_irq_mask(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      u8 irq_index,
++		      u32 mask)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_set_irq_mask *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_SET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_set_irq_mask *)cmd.params;
++	cmd_params->mask = cpu_to_le32(mask);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_get_irq_status() - Get the current status of any pending interrupts
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @irq_index:	The interrupt index to configure
++ * @status:	Returned interrupts status - one bit per cause:
++ *			0 = no interrupt pending
++ *			1 = interrupt pending
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpsw_get_irq_status(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u32 *status)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_get_irq_status *cmd_params;
++	struct dpsw_rsp_get_irq_status *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_get_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(*status);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpsw_rsp_get_irq_status *)cmd.params;
++	*status = le32_to_cpu(rsp_params->status);
++
++	return 0;
++}
++
++/**
++ * dpsw_clear_irq_status() - Clear a pending interrupt's status
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPCI object
++ * @irq_index:	The interrupt index to configure
++ * @status:	bits to clear (W1C) - one bit per cause:
++ *			0 = don't change
++ *			1 = clear status bit
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpsw_clear_irq_status(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u32 status)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_clear_irq_status *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_CLEAR_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_clear_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(status);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_get_attributes() - Retrieve DPSW attributes
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @attr:	Returned DPSW attributes
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_get_attributes(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			struct dpsw_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_rsp_get_attr *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_ATTR,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpsw_rsp_get_attr *)cmd.params;
++	attr->num_ifs = le16_to_cpu(rsp_params->num_ifs);
++	attr->max_fdbs = rsp_params->max_fdbs;
++	attr->num_fdbs = rsp_params->num_fdbs;
++	attr->max_vlans = le16_to_cpu(rsp_params->max_vlans);
++	attr->num_vlans = le16_to_cpu(rsp_params->num_vlans);
++	attr->max_fdb_entries = le16_to_cpu(rsp_params->max_fdb_entries);
++	attr->fdb_aging_time = le16_to_cpu(rsp_params->fdb_aging_time);
++	attr->id = le32_to_cpu(rsp_params->dpsw_id);
++	attr->mem_size = le16_to_cpu(rsp_params->mem_size);
++	attr->max_fdb_mc_groups = le16_to_cpu(rsp_params->max_fdb_mc_groups);
++	attr->max_meters_per_if = rsp_params->max_meters_per_if;
++	attr->options = le64_to_cpu(rsp_params->options);
++	attr->component_type = dpsw_get_field(rsp_params->component_type,
++					      COMPONENT_TYPE);
++
++	return 0;
++}
++
++/**
++ * dpsw_if_set_link_cfg() - Set the link configuration.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface id
++ * @cfg:	Link configuration
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u16 if_id,
++			 struct dpsw_link_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_set_link_cfg *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_LINK_CFG,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_set_link_cfg *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	cmd_params->rate = cpu_to_le32(cfg->rate);
++	cmd_params->options = cpu_to_le64(cfg->options);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_if_get_link_state - Return the link state
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface id
++ * @state:	Link state	1 - linkup, 0 - link down or disconnected
++ *
++ * @Return	'0' on Success; Error code otherwise.
++ */
++int dpsw_if_get_link_state(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u16 if_id,
++			   struct dpsw_link_state *state)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_get_link_state *cmd_params;
++	struct dpsw_rsp_if_get_link_state *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_LINK_STATE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_get_link_state *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpsw_rsp_if_get_link_state *)cmd.params;
++	state->rate = le32_to_cpu(rsp_params->rate);
++	state->options = le64_to_cpu(rsp_params->options);
++	state->up = dpsw_get_field(rsp_params->up, UP);
++
++	return 0;
++}
++
++/**
++ * dpsw_if_set_flooding() - Enable Disable flooding for particular interface
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface Identifier
++ * @en:		1 - enable, 0 - disable
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_set_flooding(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u16 if_id,
++			 u8 en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_set_flooding *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_FLOODING,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_set_flooding *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	dpsw_set_field(cmd_params->enable, ENABLE, en);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_if_set_broadcast() - Enable/disable broadcast for particular interface
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface Identifier
++ * @en:		1 - enable, 0 - disable
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u16 if_id,
++			  u8 en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_set_broadcast *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_BROADCAST,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_set_broadcast *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	dpsw_set_field(cmd_params->enable, ENABLE, en);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_if_set_tci() - Set default VLAN Tag Control Information (TCI)
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface Identifier
++ * @cfg:	Tag Control Information Configuration
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_set_tci(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    u16 if_id,
++		    const struct dpsw_tci_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_set_tci *cmd_params;
++	u16 tmp_conf = 0;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_TCI,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_set_tci *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	dpsw_set_field(tmp_conf, VLAN_ID, cfg->vlan_id);
++	dpsw_set_field(tmp_conf, DEI, cfg->dei);
++	dpsw_set_field(tmp_conf, PCP, cfg->pcp);
++	cmd_params->conf = cpu_to_le16(tmp_conf);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_if_get_tci() - Get default VLAN Tag Control Information (TCI)
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface Identifier
++ * @cfg:	Tag Control Information Configuration
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_get_tci(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    u16 if_id,
++		    struct dpsw_tci_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_get_tci *cmd_params;
++	struct dpsw_rsp_if_get_tci *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_TCI,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_get_tci *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpsw_rsp_if_get_tci *)cmd.params;
++	cfg->pcp = rsp_params->pcp;
++	cfg->dei = rsp_params->dei;
++	cfg->vlan_id = le16_to_cpu(rsp_params->vlan_id);
++
++	return 0;
++}
++
++/**
++ * dpsw_if_set_stp() - Function sets Spanning Tree Protocol (STP) state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface Identifier
++ * @cfg:	STP State configuration parameters
++ *
++ * The following STP states are supported -
++ * blocking, listening, learning, forwarding and disabled.
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_set_stp(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    u16 if_id,
++		    const struct dpsw_stp_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_set_stp *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_STP,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_set_stp *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	cmd_params->vlan_id = cpu_to_le16(cfg->vlan_id);
++	dpsw_set_field(cmd_params->state, STATE, cfg->state);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_if_get_counter() - Get specific counter of particular interface
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface Identifier
++ * @type:	Counter type
++ * @counter:	return value
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_get_counter(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u16 if_id,
++			enum dpsw_counter type,
++			u64 *counter)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_get_counter *cmd_params;
++	struct dpsw_rsp_if_get_counter *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_GET_COUNTER,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_get_counter *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	dpsw_set_field(cmd_params->type, COUNTER_TYPE, type);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpsw_rsp_if_get_counter *)cmd.params;
++	*counter = le64_to_cpu(rsp_params->counter);
++
++	return 0;
++}
++
++/**
++ * dpsw_if_enable() - Enable Interface
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface Identifier
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_enable(struct fsl_mc_io *mc_io,
++		   u32 cmd_flags,
++		   u16 token,
++		   u16 if_id)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_if_disable() - Disable Interface
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @if_id:	Interface Identifier
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_disable(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    u16 if_id)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_DISABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_if_set_max_frame_length() - Set Maximum Receive frame length.
++ * @mc_io:		Pointer to MC portal's I/O object
++ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:		Token of DPSW object
++ * @if_id:		Interface Identifier
++ * @frame_length:	Maximum Frame Length
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io,
++				 u32 cmd_flags,
++				 u16 token,
++				 u16 if_id,
++				 u16 frame_length)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_if_set_max_frame_length *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_IF_SET_MAX_FRAME_LENGTH,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_if_set_max_frame_length *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	cmd_params->frame_length = cpu_to_le16(frame_length);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_vlan_add() - Adding new VLAN to DPSW.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @vlan_id:	VLAN Identifier
++ * @cfg:	VLAN configuration
++ *
++ * Only VLAN ID and FDB ID are required parameters here.
++ * 12 bit VLAN ID is defined in IEEE802.1Q.
++ * Adding a duplicate VLAN ID is not allowed.
++ * FDB ID can be shared across multiple VLANs. Shared learning
++ * is obtained by calling dpsw_vlan_add for multiple VLAN IDs
++ * with same fdb_id
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_vlan_add(struct fsl_mc_io *mc_io,
++		  u32 cmd_flags,
++		  u16 token,
++		  u16 vlan_id,
++		  const struct dpsw_vlan_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_vlan_add *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_vlan_add *)cmd.params;
++	cmd_params->fdb_id = cpu_to_le16(cfg->fdb_id);
++	cmd_params->vlan_id = cpu_to_le16(vlan_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_vlan_add_if() - Adding a set of interfaces to an existing VLAN.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @vlan_id:	VLAN Identifier
++ * @cfg:	Set of interfaces to add
++ *
++ * It adds only interfaces not belonging to this VLAN yet,
++ * otherwise an error is generated and an entire command is
++ * ignored. This function can be called numerous times always
++ * providing required interfaces delta.
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_vlan_add_if(struct fsl_mc_io *mc_io,
++		     u32 cmd_flags,
++		     u16 token,
++		     u16 vlan_id,
++		     const struct dpsw_vlan_if_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_vlan_manage_if *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_vlan_manage_if *)cmd.params;
++	cmd_params->vlan_id = cpu_to_le16(vlan_id);
++	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_vlan_add_if_untagged() - Defining a set of interfaces that should be
++ *				transmitted as untagged.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @vlan_id:	VLAN Identifier
++ * @cfg:	Set of interfaces that should be transmitted as untagged
++ *
++ * These interfaces should already belong to this VLAN.
++ * By default all interfaces are transmitted as tagged.
++ * Providing un-existing interface or untagged interface that is
++ * configured untagged already generates an error and the entire
++ * command is ignored.
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io,
++			      u32 cmd_flags,
++			      u16 token,
++			      u16 vlan_id,
++			      const struct dpsw_vlan_if_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_vlan_manage_if *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_ADD_IF_UNTAGGED,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_vlan_manage_if *)cmd.params;
++	cmd_params->vlan_id = cpu_to_le16(vlan_id);
++	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_vlan_remove_if() - Remove interfaces from an existing VLAN.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @vlan_id:	VLAN Identifier
++ * @cfg:	Set of interfaces that should be removed
++ *
++ * Interfaces must belong to this VLAN, otherwise an error
++ * is returned and an the command is ignored
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u16 vlan_id,
++			const struct dpsw_vlan_if_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_vlan_manage_if *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_vlan_manage_if *)cmd.params;
++	cmd_params->vlan_id = cpu_to_le16(vlan_id);
++	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_vlan_remove_if_untagged() - Define a set of interfaces that should be
++ *		converted from transmitted as untagged to transmit as tagged.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @vlan_id:	VLAN Identifier
++ * @cfg:	Set of interfaces that should be removed
++ *
++ * Interfaces provided by API have to belong to this VLAN and
++ * configured untagged, otherwise an error is returned and the
++ * command is ignored
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io,
++				 u32 cmd_flags,
++				 u16 token,
++				 u16 vlan_id,
++				 const struct dpsw_vlan_if_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_vlan_manage_if *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE_IF_UNTAGGED,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_vlan_manage_if *)cmd.params;
++	cmd_params->vlan_id = cpu_to_le16(vlan_id);
++	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_vlan_remove() - Remove an entire VLAN
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @vlan_id:	VLAN Identifier
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_vlan_remove(struct fsl_mc_io *mc_io,
++		     u32 cmd_flags,
++		     u16 token,
++		     u16 vlan_id)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_vlan_remove *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_VLAN_REMOVE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_vlan_remove *)cmd.params;
++	cmd_params->vlan_id = cpu_to_le16(vlan_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_fdb_add_unicast() - Function adds an unicast entry into MAC lookup table
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @fdb_id:	Forwarding Database Identifier
++ * @cfg:	Unicast entry configuration
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u16 fdb_id,
++			 const struct dpsw_fdb_unicast_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_fdb_unicast_op *cmd_params;
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD_UNICAST,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_fdb_unicast_op *)cmd.params;
++	cmd_params->fdb_id = cpu_to_le16(fdb_id);
++	cmd_params->if_egress = cpu_to_le16(cfg->if_egress);
++	for (i = 0; i < 6; i++)
++		cmd_params->mac_addr[i] = cfg->mac_addr[5 - i];
++	dpsw_set_field(cmd_params->type, ENTRY_TYPE, cfg->type);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_fdb_remove_unicast() - removes an entry from MAC lookup table
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @fdb_id:	Forwarding Database Identifier
++ * @cfg:	Unicast entry configuration
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    u16 fdb_id,
++			    const struct dpsw_fdb_unicast_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_fdb_unicast_op *cmd_params;
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE_UNICAST,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_fdb_unicast_op *)cmd.params;
++	cmd_params->fdb_id = cpu_to_le16(fdb_id);
++	for (i = 0; i < 6; i++)
++		cmd_params->mac_addr[i] = cfg->mac_addr[5 - i];
++	cmd_params->if_egress = cpu_to_le16(cfg->if_egress);
++	dpsw_set_field(cmd_params->type, ENTRY_TYPE, cfg->type);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_fdb_add_multicast() - Add a set of egress interfaces to multi-cast group
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @fdb_id:	Forwarding Database Identifier
++ * @cfg:	Multicast entry configuration
++ *
++ * If group doesn't exist, it will be created.
++ * It adds only interfaces not belonging to this multicast group
++ * yet, otherwise error will be generated and the command is
++ * ignored.
++ * This function may be called numerous times always providing
++ * required interfaces delta.
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u16 fdb_id,
++			   const struct dpsw_fdb_multicast_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_fdb_multicast_op *cmd_params;
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_ADD_MULTICAST,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_fdb_multicast_op *)cmd.params;
++	cmd_params->fdb_id = cpu_to_le16(fdb_id);
++	cmd_params->num_ifs = cpu_to_le16(cfg->num_ifs);
++	dpsw_set_field(cmd_params->type, ENTRY_TYPE, cfg->type);
++	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
++	for (i = 0; i < 6; i++)
++		cmd_params->mac_addr[i] = cfg->mac_addr[5 - i];
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_fdb_remove_multicast() - Removing interfaces from an existing multicast
++ *				group.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @fdb_id:	Forwarding Database Identifier
++ * @cfg:	Multicast entry configuration
++ *
++ * Interfaces provided by this API have to exist in the group,
++ * otherwise an error will be returned and an entire command
++ * ignored. If there is no interface left in the group,
++ * an entire group is deleted
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io,
++			      u32 cmd_flags,
++			      u16 token,
++			      u16 fdb_id,
++			      const struct dpsw_fdb_multicast_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_fdb_multicast_op *cmd_params;
++	int i;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_REMOVE_MULTICAST,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_fdb_multicast_op *)cmd.params;
++	cmd_params->fdb_id = cpu_to_le16(fdb_id);
++	cmd_params->num_ifs = cpu_to_le16(cfg->num_ifs);
++	dpsw_set_field(cmd_params->type, ENTRY_TYPE, cfg->type);
++	build_if_id_bitmap(cmd_params->if_id, cfg->if_id, cfg->num_ifs);
++	for (i = 0; i < 6; i++)
++		cmd_params->mac_addr[i] = cfg->mac_addr[5 - i];
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_fdb_set_learning_mode() - Define FDB learning mode
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSW object
++ * @fdb_id:	Forwarding Database Identifier
++ * @mode:	Learning mode
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io,
++			       u32 cmd_flags,
++			       u16 token,
++			       u16 fdb_id,
++			       enum dpsw_fdb_learning_mode mode)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_cmd_fdb_set_learning_mode *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_FDB_SET_LEARNING_MODE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpsw_cmd_fdb_set_learning_mode *)cmd.params;
++	cmd_params->fdb_id = cpu_to_le16(fdb_id);
++	dpsw_set_field(cmd_params->mode, LEARNING_MODE, mode);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpsw_get_api_version() - Get Data Path Switch API version
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @major_ver:	Major version of data path switch API
++ * @minor_ver:	Minor version of data path switch API
++ *
++ * Return:  '0' on Success; Error code otherwise.
++ */
++int dpsw_get_api_version(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 *major_ver,
++			 u16 *minor_ver)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpsw_rsp_get_api_version *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSW_CMDID_GET_API_VERSION,
++					  cmd_flags,
++					  0);
++
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpsw_rsp_get_api_version *)cmd.params;
++	*major_ver = le16_to_cpu(rsp_params->version_major);
++	*minor_ver = le16_to_cpu(rsp_params->version_minor);
++
++	return 0;
++}
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/dpsw.h
+@@ -0,0 +1,592 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2013-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017-2018 NXP
++ *
++ */
++
++#ifndef __FSL_DPSW_H
++#define __FSL_DPSW_H
++
++/* Data Path L2-Switch API
++ * Contains API for handling DPSW topology and functionality
++ */
++
++struct fsl_mc_io;
++
++/**
++ * DPSW general definitions
++ */
++
++/**
++ * Maximum number of traffic class priorities
++ */
++#define DPSW_MAX_PRIORITIES	8
++/**
++ * Maximum number of interfaces
++ */
++#define DPSW_MAX_IF		64
++
++int dpsw_open(struct fsl_mc_io *mc_io,
++	      u32 cmd_flags,
++	      int dpsw_id,
++	      u16 *token);
++
++int dpsw_close(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token);
++
++/**
++ * DPSW options
++ */
++
++/**
++ * Disable flooding
++ */
++#define DPSW_OPT_FLOODING_DIS		0x0000000000000001ULL
++/**
++ * Disable Multicast
++ */
++#define DPSW_OPT_MULTICAST_DIS		0x0000000000000004ULL
++/**
++ * Support control interface
++ */
++#define DPSW_OPT_CTRL_IF_DIS		0x0000000000000010ULL
++/**
++ * Disable flooding metering
++ */
++#define DPSW_OPT_FLOODING_METERING_DIS  0x0000000000000020ULL
++/**
++ * Enable metering
++ */
++#define DPSW_OPT_METERING_EN            0x0000000000000040ULL
++
++/**
++ * enum dpsw_component_type - component type of a bridge
++ * @DPSW_COMPONENT_TYPE_C_VLAN: A C-VLAN component of an
++ *   enterprise VLAN bridge or of a Provider Bridge used
++ *   to process C-tagged frames
++ * @DPSW_COMPONENT_TYPE_S_VLAN: An S-VLAN component of a
++ *   Provider Bridge
++ *
++ */
++enum dpsw_component_type {
++	DPSW_COMPONENT_TYPE_C_VLAN = 0,
++	DPSW_COMPONENT_TYPE_S_VLAN
++};
++
++/**
++ * struct dpsw_cfg - DPSW configuration
++ * @num_ifs: Number of external and internal interfaces
++ * @adv: Advanced parameters; default is all zeros;
++ *		 use this structure to change default settings
++ */
++struct dpsw_cfg {
++	u16 num_ifs;
++	/**
++	 * struct adv - Advanced parameters
++	 * @options: Enable/Disable DPSW features (bitmap)
++	 * @max_vlans: Maximum Number of VLAN's; 0 - indicates default 16
++	 * @max_meters_per_if: Number of meters per interface
++	 * @max_fdbs: Maximum Number of FDB's; 0 - indicates default 16
++	 * @max_fdb_entries: Number of FDB entries for default FDB table;
++	 *			0 - indicates default 1024 entries.
++	 * @fdb_aging_time: Default FDB aging time for default FDB table;
++	 *			0 - indicates default 300 seconds
++	 * @max_fdb_mc_groups: Number of multicast groups in each FDB table;
++	 *			0 - indicates default 32
++	 * @component_type: Indicates the component type of this bridge
++	 */
++	struct {
++		u64 options;
++		u16 max_vlans;
++		u8 max_meters_per_if;
++		u8 max_fdbs;
++		u16 max_fdb_entries;
++		u16 fdb_aging_time;
++		u16 max_fdb_mc_groups;
++		enum dpsw_component_type component_type;
++	} adv;
++};
++
++int dpsw_enable(struct fsl_mc_io *mc_io,
++		u32 cmd_flags,
++		u16 token);
++
++int dpsw_disable(struct fsl_mc_io *mc_io,
++		 u32 cmd_flags,
++		 u16 token);
++
++int dpsw_reset(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       u16 token);
++
++/**
++ * DPSW IRQ Index and Events
++ */
++
++#define DPSW_IRQ_INDEX_IF		0x0000
++#define DPSW_IRQ_INDEX_L2SW		0x0001
++
++/**
++ * IRQ event - Indicates that the link state changed
++ */
++#define DPSW_IRQ_EVENT_LINK_CHANGED	0x0001
++
++/**
++ * struct dpsw_irq_cfg - IRQ configuration
++ * @addr:	Address that must be written to signal a message-based interrupt
++ * @val:	Value to write into irq_addr address
++ * @irq_num: A user defined number associated with this IRQ
++ */
++struct dpsw_irq_cfg {
++	     u64 addr;
++	     u32 val;
++	     int irq_num;
++};
++
++int dpsw_set_irq_enable(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u8 en);
++
++int dpsw_set_irq_mask(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      u8 irq_index,
++		      u32 mask);
++
++int dpsw_get_irq_status(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u32 *status);
++
++int dpsw_clear_irq_status(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u32 status);
++
++/**
++ * struct dpsw_attr - Structure representing DPSW attributes
++ * @id: DPSW object ID
++ * @options: Enable/Disable DPSW features
++ * @max_vlans: Maximum Number of VLANs
++ * @max_meters_per_if:  Number of meters per interface
++ * @max_fdbs: Maximum Number of FDBs
++ * @max_fdb_entries: Number of FDB entries for default FDB table;
++ *			0 - indicates default 1024 entries.
++ * @fdb_aging_time: Default FDB aging time for default FDB table;
++ *			0 - indicates default 300 seconds
++ * @max_fdb_mc_groups: Number of multicast groups in each FDB table;
++ *			0 - indicates default 32
++ * @mem_size: DPSW frame storage memory size
++ * @num_ifs: Number of interfaces
++ * @num_vlans: Current number of VLANs
++ * @num_fdbs: Current number of FDBs
++ * @component_type: Component type of this bridge
++ */
++struct dpsw_attr {
++	int id;
++	u64 options;
++	u16 max_vlans;
++	u8 max_meters_per_if;
++	u8 max_fdbs;
++	u16 max_fdb_entries;
++	u16 fdb_aging_time;
++	u16 max_fdb_mc_groups;
++	u16 num_ifs;
++	u16 mem_size;
++	u16 num_vlans;
++	u8 num_fdbs;
++	enum dpsw_component_type component_type;
++};
++
++int dpsw_get_attributes(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			struct dpsw_attr *attr);
++
++/**
++ * enum dpsw_action - Action selection for special/control frames
++ * @DPSW_ACTION_DROP: Drop frame
++ * @DPSW_ACTION_REDIRECT: Redirect frame to control port
++ */
++enum dpsw_action {
++	DPSW_ACTION_DROP = 0,
++	DPSW_ACTION_REDIRECT = 1
++};
++
++/**
++ * Enable auto-negotiation
++ */
++#define DPSW_LINK_OPT_AUTONEG		0x0000000000000001ULL
++/**
++ * Enable half-duplex mode
++ */
++#define DPSW_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
++/**
++ * Enable pause frames
++ */
++#define DPSW_LINK_OPT_PAUSE		0x0000000000000004ULL
++/**
++ * Enable a-symmetric pause frames
++ */
++#define DPSW_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
++
++/**
++ * struct dpsw_link_cfg - Structure representing DPSW link configuration
++ * @rate: Rate
++ * @options: Mask of available options; use 'DPSW_LINK_OPT_<X>' values
++ */
++struct dpsw_link_cfg {
++	u32 rate;
++	u64 options;
++};
++
++int dpsw_if_set_link_cfg(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u16 if_id,
++			 struct dpsw_link_cfg *cfg);
++/**
++ * struct dpsw_link_state - Structure representing DPSW link state
++ * @rate: Rate
++ * @options: Mask of available options; use 'DPSW_LINK_OPT_<X>' values
++ * @up: 0 - covers two cases: down and disconnected, 1 - up
++ */
++struct dpsw_link_state {
++	u32 rate;
++	u64 options;
++	u8 up;
++};
++
++int dpsw_if_get_link_state(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u16 if_id,
++			   struct dpsw_link_state *state);
++
++int dpsw_if_set_flooding(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u16 if_id,
++			 u8 en);
++
++int dpsw_if_set_broadcast(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u16 if_id,
++			  u8 en);
++
++/**
++ * struct dpsw_tci_cfg - Tag Control Information (TCI) configuration
++ * @pcp: Priority Code Point (PCP): a 3-bit field which refers
++ *		 to the IEEE 802.1p priority
++ * @dei: Drop Eligible Indicator (DEI): a 1-bit field. May be used
++ *		 separately or in conjunction with PCP to indicate frames
++ *		 eligible to be dropped in the presence of congestion
++ * @vlan_id: VLAN Identifier (VID): a 12-bit field specifying the VLAN
++ *			to which the frame belongs. The hexadecimal values
++ *			of 0x000 and 0xFFF are reserved;
++ *			all other values may be used as VLAN identifiers,
++ *			allowing up to 4,094 VLANs
++ */
++struct dpsw_tci_cfg {
++	u8 pcp;
++	u8 dei;
++	u16 vlan_id;
++};
++
++int dpsw_if_set_tci(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    u16 if_id,
++		    const struct dpsw_tci_cfg *cfg);
++
++int dpsw_if_get_tci(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    u16 if_id,
++		    struct dpsw_tci_cfg *cfg);
++
++/**
++ * enum dpsw_stp_state - Spanning Tree Protocol (STP) states
++ * @DPSW_STP_STATE_BLOCKING: Blocking state
++ * @DPSW_STP_STATE_LISTENING: Listening state
++ * @DPSW_STP_STATE_LEARNING: Learning state
++ * @DPSW_STP_STATE_FORWARDING: Forwarding state
++ *
++ */
++enum dpsw_stp_state {
++	DPSW_STP_STATE_DISABLED = 0,
++	DPSW_STP_STATE_LISTENING = 1,
++	DPSW_STP_STATE_LEARNING = 2,
++	DPSW_STP_STATE_FORWARDING = 3,
++	DPSW_STP_STATE_BLOCKING = 0
++};
++
++/**
++ * struct dpsw_stp_cfg - Spanning Tree Protocol (STP) Configuration
++ * @vlan_id: VLAN ID STP state
++ * @state: STP state
++ */
++struct dpsw_stp_cfg {
++	u16 vlan_id;
++	enum dpsw_stp_state state;
++};
++
++int dpsw_if_set_stp(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    u16 if_id,
++		    const struct dpsw_stp_cfg *cfg);
++
++/**
++ * enum dpsw_accepted_frames - Types of frames to accept
++ * @DPSW_ADMIT_ALL: The device accepts VLAN tagged, untagged and
++ *			priority tagged frames
++ * @DPSW_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or
++ *			Priority-Tagged frames received on this interface.
++ *
++ */
++enum dpsw_accepted_frames {
++	DPSW_ADMIT_ALL = 1,
++	DPSW_ADMIT_ONLY_VLAN_TAGGED = 3
++};
++
++/**
++ * enum dpsw_counter  - Counters types
++ * @DPSW_CNT_ING_FRAME: Counts ingress frames
++ * @DPSW_CNT_ING_BYTE: Counts ingress bytes
++ * @DPSW_CNT_ING_FLTR_FRAME: Counts filtered ingress frames
++ * @DPSW_CNT_ING_FRAME_DISCARD: Counts discarded ingress frame
++ * @DPSW_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
++ * @DPSW_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
++ * @DPSW_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
++ * @DPSW_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
++ * @DPSW_CNT_EGR_FRAME: Counts egress frames
++ * @DPSW_CNT_EGR_BYTE: Counts eEgress bytes
++ * @DPSW_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames
++ * @DPSW_CNT_EGR_STP_FRAME_DISCARD: Counts egress STP discarded frames
++ */
++enum dpsw_counter {
++	DPSW_CNT_ING_FRAME = 0x0,
++	DPSW_CNT_ING_BYTE = 0x1,
++	DPSW_CNT_ING_FLTR_FRAME = 0x2,
++	DPSW_CNT_ING_FRAME_DISCARD = 0x3,
++	DPSW_CNT_ING_MCAST_FRAME = 0x4,
++	DPSW_CNT_ING_MCAST_BYTE = 0x5,
++	DPSW_CNT_ING_BCAST_FRAME = 0x6,
++	DPSW_CNT_ING_BCAST_BYTES = 0x7,
++	DPSW_CNT_EGR_FRAME = 0x8,
++	DPSW_CNT_EGR_BYTE = 0x9,
++	DPSW_CNT_EGR_FRAME_DISCARD = 0xa,
++	DPSW_CNT_EGR_STP_FRAME_DISCARD = 0xb
++};
++
++int dpsw_if_get_counter(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u16 if_id,
++			enum dpsw_counter type,
++			u64 *counter);
++
++int dpsw_if_enable(struct fsl_mc_io *mc_io,
++		   u32 cmd_flags,
++		   u16 token,
++		   u16 if_id);
++
++int dpsw_if_disable(struct fsl_mc_io *mc_io,
++		    u32 cmd_flags,
++		    u16 token,
++		    u16 if_id);
++
++int dpsw_if_set_max_frame_length(struct fsl_mc_io *mc_io,
++				 u32 cmd_flags,
++				 u16 token,
++				 u16 if_id,
++				 u16 frame_length);
++
++/**
++ * struct dpsw_vlan_cfg - VLAN Configuration
++ * @fdb_id: Forwarding Data Base
++ */
++struct dpsw_vlan_cfg {
++	u16 fdb_id;
++};
++
++int dpsw_vlan_add(struct fsl_mc_io *mc_io,
++		  u32 cmd_flags,
++		  u16 token,
++		  u16 vlan_id,
++		  const struct dpsw_vlan_cfg *cfg);
++
++/**
++ * struct dpsw_vlan_if_cfg - Set of VLAN Interfaces
++ * @num_ifs: The number of interfaces that are assigned to the egress
++ *		list for this VLAN
++ * @if_id: The set of interfaces that are
++ *		assigned to the egress list for this VLAN
++ */
++struct dpsw_vlan_if_cfg {
++	u16 num_ifs;
++	u16 if_id[DPSW_MAX_IF];
++};
++
++int dpsw_vlan_add_if(struct fsl_mc_io *mc_io,
++		     u32 cmd_flags,
++		     u16 token,
++		     u16 vlan_id,
++		     const struct dpsw_vlan_if_cfg *cfg);
++
++int dpsw_vlan_add_if_untagged(struct fsl_mc_io *mc_io,
++			      u32 cmd_flags,
++			      u16 token,
++			      u16 vlan_id,
++			      const struct dpsw_vlan_if_cfg *cfg);
++
++int dpsw_vlan_remove_if(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u16 vlan_id,
++			const struct dpsw_vlan_if_cfg *cfg);
++
++int dpsw_vlan_remove_if_untagged(struct fsl_mc_io *mc_io,
++				 u32 cmd_flags,
++				 u16 token,
++				 u16 vlan_id,
++				 const struct dpsw_vlan_if_cfg *cfg);
++
++int dpsw_vlan_remove(struct fsl_mc_io *mc_io,
++		     u32 cmd_flags,
++		     u16 token,
++		     u16 vlan_id);
++
++/**
++ * enum dpsw_fdb_entry_type - FDB Entry type - Static/Dynamic
++ * @DPSW_FDB_ENTRY_STATIC: Static entry
++ * @DPSW_FDB_ENTRY_DINAMIC: Dynamic entry
++ */
++enum dpsw_fdb_entry_type {
++	DPSW_FDB_ENTRY_STATIC = 0,
++	DPSW_FDB_ENTRY_DINAMIC = 1
++};
++
++/**
++ * struct dpsw_fdb_unicast_cfg - Unicast entry configuration
++ * @type: Select static or dynamic entry
++ * @mac_addr: MAC address
++ * @if_egress: Egress interface ID
++ */
++struct dpsw_fdb_unicast_cfg {
++	enum dpsw_fdb_entry_type type;
++	u8 mac_addr[6];
++	u16 if_egress;
++};
++
++int dpsw_fdb_add_unicast(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u16 fdb_id,
++			 const struct dpsw_fdb_unicast_cfg *cfg);
++
++int dpsw_fdb_remove_unicast(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    u16 fdb_id,
++			    const struct dpsw_fdb_unicast_cfg *cfg);
++
++/**
++ * struct dpsw_fdb_multicast_cfg - Multi-cast entry configuration
++ * @type: Select static or dynamic entry
++ * @mac_addr: MAC address
++ * @num_ifs: Number of external and internal interfaces
++ * @if_id: Egress interface IDs
++ */
++struct dpsw_fdb_multicast_cfg {
++	enum dpsw_fdb_entry_type type;
++	u8 mac_addr[6];
++	u16 num_ifs;
++	u16 if_id[DPSW_MAX_IF];
++};
++
++int dpsw_fdb_add_multicast(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u16 fdb_id,
++			   const struct dpsw_fdb_multicast_cfg *cfg);
++
++int dpsw_fdb_remove_multicast(struct fsl_mc_io *mc_io,
++			      u32 cmd_flags,
++			      u16 token,
++			      u16 fdb_id,
++			      const struct dpsw_fdb_multicast_cfg *cfg);
++
++/**
++ * enum dpsw_fdb_learning_mode - Auto-learning modes
++ * @DPSW_FDB_LEARNING_MODE_DIS: Disable Auto-learning
++ * @DPSW_FDB_LEARNING_MODE_HW: Enable HW auto-Learning
++ * @DPSW_FDB_LEARNING_MODE_NON_SECURE: Enable None secure learning by CPU
++ * @DPSW_FDB_LEARNING_MODE_SECURE: Enable secure learning by CPU
++ *
++ *	NONE - SECURE LEARNING
++ *	SMAC found	DMAC found	CTLU Action
++ *	v		v	Forward frame to
++ *						1.  DMAC destination
++ *	-		v	Forward frame to
++ *						1.  DMAC destination
++ *						2.  Control interface
++ *	v		-	Forward frame to
++ *						1.  Flooding list of interfaces
++ *	-		-	Forward frame to
++ *						1.  Flooding list of interfaces
++ *						2.  Control interface
++ *	SECURE LEARING
++ *	SMAC found	DMAC found	CTLU Action
++ *	v		v		Forward frame to
++ *						1.  DMAC destination
++ *	-		v		Forward frame to
++ *						1.  Control interface
++ *	v		-		Forward frame to
++ *						1.  Flooding list of interfaces
++ *	-		-		Forward frame to
++ *						1.  Control interface
++ */
++enum dpsw_fdb_learning_mode {
++	DPSW_FDB_LEARNING_MODE_DIS = 0,
++	DPSW_FDB_LEARNING_MODE_HW = 1,
++	DPSW_FDB_LEARNING_MODE_NON_SECURE = 2,
++	DPSW_FDB_LEARNING_MODE_SECURE = 3
++};
++
++int dpsw_fdb_set_learning_mode(struct fsl_mc_io *mc_io,
++			       u32 cmd_flags,
++			       u16 token,
++			       u16 fdb_id,
++			       enum dpsw_fdb_learning_mode mode);
++
++/**
++ * struct dpsw_fdb_attr - FDB Attributes
++ * @max_fdb_entries: Number of FDB entries
++ * @fdb_aging_time: Aging time in seconds
++ * @learning_mode: Learning mode
++ * @num_fdb_mc_groups: Current number of multicast groups
++ * @max_fdb_mc_groups: Maximum number of multicast groups
++ */
++struct dpsw_fdb_attr {
++	u16 max_fdb_entries;
++	u16 fdb_aging_time;
++	enum dpsw_fdb_learning_mode learning_mode;
++	u16 num_fdb_mc_groups;
++	u16 max_fdb_mc_groups;
++};
++
++int dpsw_get_api_version(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 *major_ver,
++			 u16 *minor_ver);
++
++#endif /* __FSL_DPSW_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/ethsw-ethtool.c
+@@ -0,0 +1,206 @@
++/* Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include "ethsw.h"
++
++static struct {
++	enum dpsw_counter id;
++	char name[ETH_GSTRING_LEN];
++} ethsw_ethtool_counters[] =  {
++	{DPSW_CNT_ING_FRAME,		"rx frames"},
++	{DPSW_CNT_ING_BYTE,		"rx bytes"},
++	{DPSW_CNT_ING_FLTR_FRAME,	"rx filtered frames"},
++	{DPSW_CNT_ING_FRAME_DISCARD,	"rx discarded frames"},
++	{DPSW_CNT_ING_BCAST_FRAME,	"rx b-cast frames"},
++	{DPSW_CNT_ING_BCAST_BYTES,	"rx b-cast bytes"},
++	{DPSW_CNT_ING_MCAST_FRAME,	"rx m-cast frames"},
++	{DPSW_CNT_ING_MCAST_BYTE,	"rx m-cast bytes"},
++	{DPSW_CNT_EGR_FRAME,		"tx frames"},
++	{DPSW_CNT_EGR_BYTE,		"tx bytes"},
++	{DPSW_CNT_EGR_FRAME_DISCARD,	"tx discarded frames"},
++
++};
++
++#define ETHSW_NUM_COUNTERS	ARRAY_SIZE(ethsw_ethtool_counters)
++
++static void ethsw_get_drvinfo(struct net_device *netdev,
++			      struct ethtool_drvinfo *drvinfo)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	u16 version_major, version_minor;
++	int err;
++
++	strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
++
++	err = dpsw_get_api_version(port_priv->ethsw_data->mc_io, 0,
++				   &version_major,
++				   &version_minor);
++	if (err)
++		strlcpy(drvinfo->fw_version, "N/A",
++			sizeof(drvinfo->fw_version));
++	else
++		snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
++			 "%u.%u", version_major, version_minor);
++
++	strlcpy(drvinfo->bus_info, dev_name(netdev->dev.parent->parent),
++		sizeof(drvinfo->bus_info));
++}
++
++static int
++ethsw_get_link_ksettings(struct net_device *netdev,
++			 struct ethtool_link_ksettings *link_ksettings)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	struct dpsw_link_state state = {0};
++	int err = 0;
++
++	err = dpsw_if_get_link_state(port_priv->ethsw_data->mc_io, 0,
++				     port_priv->ethsw_data->dpsw_handle,
++				     port_priv->idx,
++				     &state);
++	if (err) {
++		netdev_err(netdev, "ERROR %d getting link state", err);
++		goto out;
++	}
++
++	/* At the moment, we have no way of interrogating the DPMAC
++	 * from the DPSW side or there may not exist a DPMAC at all.
++	 * Report only autoneg state, duplexity and speed.
++	 */
++	if (state.options & DPSW_LINK_OPT_AUTONEG)
++		link_ksettings->base.autoneg = AUTONEG_ENABLE;
++	if (!(state.options & DPSW_LINK_OPT_HALF_DUPLEX))
++		link_ksettings->base.duplex = DUPLEX_FULL;
++	link_ksettings->base.speed = state.rate;
++
++out:
++	return err;
++}
++
++static int
++ethsw_set_link_ksettings(struct net_device *netdev,
++			 const struct ethtool_link_ksettings *link_ksettings)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	struct dpsw_link_cfg cfg = {0};
++	int err = 0;
++
++	netdev_dbg(netdev, "Setting link parameters...");
++
++	/* Due to a temporary MC limitation, the DPSW port must be down
++	 * in order to be able to change link settings. Taking steps to let
++	 * the user know that.
++	 */
++	if (netif_running(netdev)) {
++		netdev_info(netdev, "Sorry, interface must be brought down first.\n");
++		return -EACCES;
++	}
++
++	cfg.rate = link_ksettings->base.speed;
++	if (link_ksettings->base.autoneg == AUTONEG_ENABLE)
++		cfg.options |= DPSW_LINK_OPT_AUTONEG;
++	else
++		cfg.options &= ~DPSW_LINK_OPT_AUTONEG;
++	if (link_ksettings->base.duplex  == DUPLEX_HALF)
++		cfg.options |= DPSW_LINK_OPT_HALF_DUPLEX;
++	else
++		cfg.options &= ~DPSW_LINK_OPT_HALF_DUPLEX;
++
++	err = dpsw_if_set_link_cfg(port_priv->ethsw_data->mc_io, 0,
++				   port_priv->ethsw_data->dpsw_handle,
++				   port_priv->idx,
++				   &cfg);
++	if (err)
++		/* ethtool will be loud enough if we return an error; no point
++		 * in putting our own error message on the console by default
++		 */
++		netdev_dbg(netdev, "ERROR %d setting link cfg", err);
++
++	return err;
++}
++
++static int ethsw_ethtool_get_sset_count(struct net_device *dev, int sset)
++{
++	switch (sset) {
++	case ETH_SS_STATS:
++		return ETHSW_NUM_COUNTERS;
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static void ethsw_ethtool_get_strings(struct net_device *netdev,
++				      u32 stringset, u8 *data)
++{
++	int i;
++
++	switch (stringset) {
++	case ETH_SS_STATS:
++		for (i = 0; i < ETHSW_NUM_COUNTERS; i++)
++			memcpy(data + i * ETH_GSTRING_LEN,
++			       ethsw_ethtool_counters[i].name, ETH_GSTRING_LEN);
++		break;
++	}
++}
++
++static void ethsw_ethtool_get_stats(struct net_device *netdev,
++				    struct ethtool_stats *stats,
++				    u64 *data)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	int i, err;
++
++	memset(data, 0,
++	       sizeof(u64) * ETHSW_NUM_COUNTERS);
++
++	for (i = 0; i < ETHSW_NUM_COUNTERS; i++) {
++		err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
++					  port_priv->ethsw_data->dpsw_handle,
++					  port_priv->idx,
++					  ethsw_ethtool_counters[i].id,
++					  &data[i]);
++		if (err)
++			netdev_err(netdev, "dpsw_if_get_counter[%s] err %d\n",
++				   ethsw_ethtool_counters[i].name, err);
++	}
++}
++
++const struct ethtool_ops ethsw_port_ethtool_ops = {
++	.get_drvinfo		= ethsw_get_drvinfo,
++	.get_link		= ethtool_op_get_link,
++	.get_link_ksettings	= ethsw_get_link_ksettings,
++	.set_link_ksettings	= ethsw_set_link_ksettings,
++	.get_strings		= ethsw_ethtool_get_strings,
++	.get_ethtool_stats	= ethsw_ethtool_get_stats,
++	.get_sset_count		= ethsw_ethtool_get_sset_count,
++};
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/ethsw.c
+@@ -0,0 +1,1438 @@
++/* Copyright 2014-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/module.h>
++
++#include <linux/interrupt.h>
++#include <linux/msi.h>
++#include <linux/kthread.h>
++#include <linux/workqueue.h>
++
++#include <linux/fsl/mc.h>
++
++#include "ethsw.h"
++
++static struct workqueue_struct *ethsw_owq;
++
++/* Minimal supported DPSW version */
++#define DPSW_MIN_VER_MAJOR		8
++#define DPSW_MIN_VER_MINOR		0
++
++#define DEFAULT_VLAN_ID			1
++
++static int ethsw_add_vlan(struct ethsw_core *ethsw, u16 vid)
++{
++	int err;
++
++	struct dpsw_vlan_cfg	vcfg = {
++		.fdb_id = 0,
++	};
++
++	if (ethsw->vlans[vid]) {
++		dev_err(ethsw->dev, "VLAN already configured\n");
++		return -EEXIST;
++	}
++
++	err = dpsw_vlan_add(ethsw->mc_io, 0,
++			    ethsw->dpsw_handle, vid, &vcfg);
++	if (err) {
++		dev_err(ethsw->dev, "dpsw_vlan_add err %d\n", err);
++		return err;
++	}
++	ethsw->vlans[vid] = ETHSW_VLAN_MEMBER;
++
++	return 0;
++}
++
++static int ethsw_port_set_pvid(struct ethsw_port_priv *port_priv, u16 pvid)
++{
++	struct ethsw_core *ethsw = port_priv->ethsw_data;
++	struct net_device *netdev = port_priv->netdev;
++	struct dpsw_tci_cfg tci_cfg = { 0 };
++	bool is_oper;
++	int err, ret;
++
++	err = dpsw_if_get_tci(ethsw->mc_io, 0, ethsw->dpsw_handle,
++			      port_priv->idx, &tci_cfg);
++	if (err) {
++		netdev_err(netdev, "dpsw_if_get_tci err %d\n", err);
++		return err;
++	}
++
++	tci_cfg.vlan_id = pvid;
++
++	/* Interface needs to be down to change PVID */
++	is_oper = netif_oper_up(netdev);
++	if (is_oper) {
++		err = dpsw_if_disable(ethsw->mc_io, 0,
++				      ethsw->dpsw_handle,
++				      port_priv->idx);
++		if (err) {
++			netdev_err(netdev, "dpsw_if_disable err %d\n", err);
++			return err;
++		}
++	}
++
++	err = dpsw_if_set_tci(ethsw->mc_io, 0, ethsw->dpsw_handle,
++			      port_priv->idx, &tci_cfg);
++	if (err) {
++		netdev_err(netdev, "dpsw_if_set_tci err %d\n", err);
++		goto set_tci_error;
++	}
++
++	/* Delete previous PVID info and mark the new one */
++	port_priv->vlans[port_priv->pvid] &= ~ETHSW_VLAN_PVID;
++	port_priv->vlans[pvid] |= ETHSW_VLAN_PVID;
++	port_priv->pvid = pvid;
++
++set_tci_error:
++	if (is_oper) {
++		ret = dpsw_if_enable(ethsw->mc_io, 0,
++				     ethsw->dpsw_handle,
++				     port_priv->idx);
++		if (ret) {
++			netdev_err(netdev, "dpsw_if_enable err %d\n", ret);
++			return ret;
++		}
++	}
++
++	return err;
++}
++
++static int ethsw_port_add_vlan(struct ethsw_port_priv *port_priv,
++			       u16 vid, u16 flags)
++{
++	struct ethsw_core *ethsw = port_priv->ethsw_data;
++	struct net_device *netdev = port_priv->netdev;
++	struct dpsw_vlan_if_cfg vcfg;
++	int err;
++
++	if (port_priv->vlans[vid]) {
++		netdev_warn(netdev, "VLAN %d already configured\n", vid);
++		return -EEXIST;
++	}
++
++	vcfg.num_ifs = 1;
++	vcfg.if_id[0] = port_priv->idx;
++	err = dpsw_vlan_add_if(ethsw->mc_io, 0, ethsw->dpsw_handle, vid, &vcfg);
++	if (err) {
++		netdev_err(netdev, "dpsw_vlan_add_if err %d\n", err);
++		return err;
++	}
++
++	port_priv->vlans[vid] = ETHSW_VLAN_MEMBER;
++
++	if (flags & BRIDGE_VLAN_INFO_UNTAGGED) {
++		err = dpsw_vlan_add_if_untagged(ethsw->mc_io, 0,
++						ethsw->dpsw_handle,
++						vid, &vcfg);
++		if (err) {
++			netdev_err(netdev,
++				   "dpsw_vlan_add_if_untagged err %d\n", err);
++			return err;
++		}
++		port_priv->vlans[vid] |= ETHSW_VLAN_UNTAGGED;
++	}
++
++	if (flags & BRIDGE_VLAN_INFO_PVID) {
++		err = ethsw_port_set_pvid(port_priv, vid);
++		if (err)
++			return err;
++	}
++
++	return 0;
++}
++
++static int ethsw_set_learning(struct ethsw_core *ethsw, u8 flag)
++{
++	enum dpsw_fdb_learning_mode learn_mode;
++	int err;
++
++	if (flag)
++		learn_mode = DPSW_FDB_LEARNING_MODE_HW;
++	else
++		learn_mode = DPSW_FDB_LEARNING_MODE_DIS;
++
++	err = dpsw_fdb_set_learning_mode(ethsw->mc_io, 0, ethsw->dpsw_handle, 0,
++					 learn_mode);
++	if (err) {
++		dev_err(ethsw->dev, "dpsw_fdb_set_learning_mode err %d\n", err);
++		return err;
++	}
++	ethsw->learning = !!flag;
++
++	return 0;
++}
++
++static int ethsw_port_set_flood(struct ethsw_port_priv *port_priv, u8 flag)
++{
++	int err;
++
++	err = dpsw_if_set_flooding(port_priv->ethsw_data->mc_io, 0,
++				   port_priv->ethsw_data->dpsw_handle,
++				   port_priv->idx, flag);
++	if (err) {
++		netdev_err(port_priv->netdev,
++			   "dpsw_fdb_set_learning_mode err %d\n", err);
++		return err;
++	}
++	port_priv->flood = !!flag;
++
++	return 0;
++}
++
++static int ethsw_port_set_stp_state(struct ethsw_port_priv *port_priv, u8 state)
++{
++	struct dpsw_stp_cfg stp_cfg = {
++		.vlan_id = DEFAULT_VLAN_ID,
++		.state = state,
++	};
++	int err;
++
++	if (!netif_oper_up(port_priv->netdev) || state == port_priv->stp_state)
++		return 0;	/* Nothing to do */
++
++	err = dpsw_if_set_stp(port_priv->ethsw_data->mc_io, 0,
++			      port_priv->ethsw_data->dpsw_handle,
++			      port_priv->idx, &stp_cfg);
++	if (err) {
++		netdev_err(port_priv->netdev,
++			   "dpsw_if_set_stp err %d\n", err);
++		return err;
++	}
++
++	port_priv->stp_state = state;
++
++	return 0;
++}
++
++static int ethsw_dellink_switch(struct ethsw_core *ethsw, u16 vid)
++{
++	struct ethsw_port_priv *ppriv_local = NULL;
++	int i, err;
++
++	if (!ethsw->vlans[vid])
++		return -ENOENT;
++
++	err = dpsw_vlan_remove(ethsw->mc_io, 0, ethsw->dpsw_handle, vid);
++	if (err) {
++		dev_err(ethsw->dev, "dpsw_vlan_remove err %d\n", err);
++		return err;
++	}
++	ethsw->vlans[vid] = 0;
++
++	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
++		ppriv_local = ethsw->ports[i];
++		ppriv_local->vlans[vid] = 0;
++	}
++
++	return 0;
++}
++
++static int ethsw_port_fdb_add_uc(struct ethsw_port_priv *port_priv,
++				 const unsigned char *addr)
++{
++	struct dpsw_fdb_unicast_cfg entry = {0};
++	int err;
++
++	entry.if_egress = port_priv->idx;
++	entry.type = DPSW_FDB_ENTRY_STATIC;
++	ether_addr_copy(entry.mac_addr, addr);
++
++	err = dpsw_fdb_add_unicast(port_priv->ethsw_data->mc_io, 0,
++				   port_priv->ethsw_data->dpsw_handle,
++				   0, &entry);
++	if (err)
++		netdev_err(port_priv->netdev,
++			   "dpsw_fdb_add_unicast err %d\n", err);
++	return err;
++}
++
++static int ethsw_port_fdb_del_uc(struct ethsw_port_priv *port_priv,
++				 const unsigned char *addr)
++{
++	struct dpsw_fdb_unicast_cfg entry = {0};
++	int err;
++
++	entry.if_egress = port_priv->idx;
++	entry.type = DPSW_FDB_ENTRY_STATIC;
++	ether_addr_copy(entry.mac_addr, addr);
++
++	err = dpsw_fdb_remove_unicast(port_priv->ethsw_data->mc_io, 0,
++				      port_priv->ethsw_data->dpsw_handle,
++				      0, &entry);
++	/* Silently discard calling multiple times the del command */
++	if (err && err != -ENXIO)
++		netdev_err(port_priv->netdev,
++			   "dpsw_fdb_remove_unicast err %d\n", err);
++	return err;
++}
++
++static int ethsw_port_fdb_add_mc(struct ethsw_port_priv *port_priv,
++				 const unsigned char *addr)
++{
++	struct dpsw_fdb_multicast_cfg entry = {0};
++	int err;
++
++	ether_addr_copy(entry.mac_addr, addr);
++	entry.type = DPSW_FDB_ENTRY_STATIC;
++	entry.num_ifs = 1;
++	entry.if_id[0] = port_priv->idx;
++
++	err = dpsw_fdb_add_multicast(port_priv->ethsw_data->mc_io, 0,
++				     port_priv->ethsw_data->dpsw_handle,
++				     0, &entry);
++	/* Silently discard calling multiple times the add command */
++	if (err && err != -ENXIO)
++		netdev_err(port_priv->netdev, "dpsw_fdb_add_multicast err %d\n",
++			   err);
++	return err;
++}
++
++static int ethsw_port_fdb_del_mc(struct ethsw_port_priv *port_priv,
++				 const unsigned char *addr)
++{
++	struct dpsw_fdb_multicast_cfg entry = {0};
++	int err;
++
++	ether_addr_copy(entry.mac_addr, addr);
++	entry.type = DPSW_FDB_ENTRY_STATIC;
++	entry.num_ifs = 1;
++	entry.if_id[0] = port_priv->idx;
++
++	err = dpsw_fdb_remove_multicast(port_priv->ethsw_data->mc_io, 0,
++					port_priv->ethsw_data->dpsw_handle,
++					0, &entry);
++	/* Silently discard calling multiple times the del command */
++	if (err && err != -ENAVAIL)
++		netdev_err(port_priv->netdev,
++			   "dpsw_fdb_remove_multicast err %d\n", err);
++	return err;
++}
++
++static void port_get_stats(struct net_device *netdev,
++			   struct rtnl_link_stats64 *stats)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	u64 tmp;
++	int err;
++
++	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
++				  port_priv->ethsw_data->dpsw_handle,
++				  port_priv->idx,
++				  DPSW_CNT_ING_FRAME, &stats->rx_packets);
++	if (err)
++		goto error;
++
++	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
++				  port_priv->ethsw_data->dpsw_handle,
++				  port_priv->idx,
++				  DPSW_CNT_EGR_FRAME, &stats->tx_packets);
++	if (err)
++		goto error;
++
++	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
++				  port_priv->ethsw_data->dpsw_handle,
++				  port_priv->idx,
++				  DPSW_CNT_ING_BYTE, &stats->rx_bytes);
++	if (err)
++		goto error;
++
++	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
++				  port_priv->ethsw_data->dpsw_handle,
++				  port_priv->idx,
++				  DPSW_CNT_EGR_BYTE, &stats->tx_bytes);
++	if (err)
++		goto error;
++
++	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
++				  port_priv->ethsw_data->dpsw_handle,
++				  port_priv->idx,
++				  DPSW_CNT_ING_FRAME_DISCARD,
++				  &stats->rx_dropped);
++	if (err)
++		goto error;
++
++	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
++				  port_priv->ethsw_data->dpsw_handle,
++				  port_priv->idx,
++				  DPSW_CNT_ING_FLTR_FRAME,
++				  &tmp);
++	if (err)
++		goto error;
++	stats->rx_dropped += tmp;
++
++	err = dpsw_if_get_counter(port_priv->ethsw_data->mc_io, 0,
++				  port_priv->ethsw_data->dpsw_handle,
++				  port_priv->idx,
++				  DPSW_CNT_EGR_FRAME_DISCARD,
++				  &stats->tx_dropped);
++	if (err)
++		goto error;
++
++	return;
++
++error:
++	netdev_err(netdev, "dpsw_if_get_counter err %d\n", err);
++}
++
++static bool port_has_offload_stats(const struct net_device *netdev,
++				   int attr_id)
++{
++	return (attr_id == IFLA_OFFLOAD_XSTATS_CPU_HIT);
++}
++
++static int port_get_offload_stats(int attr_id,
++				  const struct net_device *netdev,
++				  void *sp)
++{
++	switch (attr_id) {
++	case IFLA_OFFLOAD_XSTATS_CPU_HIT:
++		port_get_stats((struct net_device *)netdev, sp);
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static int port_change_mtu(struct net_device *netdev, int mtu)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	int err;
++
++	err = dpsw_if_set_max_frame_length(port_priv->ethsw_data->mc_io,
++					   0,
++					   port_priv->ethsw_data->dpsw_handle,
++					   port_priv->idx,
++					   (u16)ETHSW_L2_MAX_FRM(mtu));
++	if (err) {
++		netdev_err(netdev,
++			   "dpsw_if_set_max_frame_length() err %d\n", err);
++		return err;
++	}
++
++	netdev->mtu = mtu;
++	return 0;
++}
++
++static int port_carrier_state_sync(struct net_device *netdev)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	struct dpsw_link_state state;
++	int err;
++
++	err = dpsw_if_get_link_state(port_priv->ethsw_data->mc_io, 0,
++				     port_priv->ethsw_data->dpsw_handle,
++				     port_priv->idx, &state);
++	if (err) {
++		netdev_err(netdev, "dpsw_if_get_link_state() err %d\n", err);
++		return err;
++	}
++
++	WARN_ONCE(state.up > 1, "Garbage read into link_state");
++
++	if (state.up != port_priv->link_state) {
++		if (state.up)
++			netif_carrier_on(netdev);
++		else
++			netif_carrier_off(netdev);
++		port_priv->link_state = state.up;
++	}
++	return 0;
++}
++
++static int port_open(struct net_device *netdev)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	int err;
++
++	/* No need to allow Tx as control interface is disabled */
++	netif_tx_stop_all_queues(netdev);
++
++	err = dpsw_if_enable(port_priv->ethsw_data->mc_io, 0,
++			     port_priv->ethsw_data->dpsw_handle,
++			     port_priv->idx);
++	if (err) {
++		netdev_err(netdev, "dpsw_if_enable err %d\n", err);
++		return err;
++	}
++
++	/* sync carrier state */
++	err = port_carrier_state_sync(netdev);
++	if (err) {
++		netdev_err(netdev,
++			   "port_carrier_state_sync err %d\n", err);
++		goto err_carrier_sync;
++	}
++
++	return 0;
++
++err_carrier_sync:
++	dpsw_if_disable(port_priv->ethsw_data->mc_io, 0,
++			port_priv->ethsw_data->dpsw_handle,
++			port_priv->idx);
++	return err;
++}
++
++static int port_stop(struct net_device *netdev)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	int err;
++
++	err = dpsw_if_disable(port_priv->ethsw_data->mc_io, 0,
++			      port_priv->ethsw_data->dpsw_handle,
++			      port_priv->idx);
++	if (err) {
++		netdev_err(netdev, "dpsw_if_disable err %d\n", err);
++		return err;
++	}
++
++	return 0;
++}
++
++static netdev_tx_t port_dropframe(struct sk_buff *skb,
++				  struct net_device *netdev)
++{
++	/* we don't support I/O for now, drop the frame */
++	dev_kfree_skb_any(skb);
++
++	return NETDEV_TX_OK;
++}
++
++static const struct net_device_ops ethsw_port_ops = {
++	.ndo_open		= port_open,
++	.ndo_stop		= port_stop,
++
++	.ndo_set_mac_address	= eth_mac_addr,
++	.ndo_change_mtu		= port_change_mtu,
++	.ndo_has_offload_stats	= port_has_offload_stats,
++	.ndo_get_offload_stats	= port_get_offload_stats,
++
++	.ndo_start_xmit		= port_dropframe,
++};
++
++static void ethsw_links_state_update(struct ethsw_core *ethsw)
++{
++	int i;
++
++	for (i = 0; i < ethsw->sw_attr.num_ifs; i++)
++		port_carrier_state_sync(ethsw->ports[i]->netdev);
++}
++
++static irqreturn_t ethsw_irq0_handler(int irq_num, void *arg)
++{
++	return IRQ_WAKE_THREAD;
++}
++
++static irqreturn_t ethsw_irq0_handler_thread(int irq_num, void *arg)
++{
++	struct device *dev = (struct device *)arg;
++	struct ethsw_core *ethsw = dev_get_drvdata(dev);
++
++	/* Mask the events and the if_id reserved bits to be cleared on read */
++	u32 status = DPSW_IRQ_EVENT_LINK_CHANGED | 0xFFFF0000;
++	int err;
++
++	err = dpsw_get_irq_status(ethsw->mc_io, 0, ethsw->dpsw_handle,
++				  DPSW_IRQ_INDEX_IF, &status);
++	if (err) {
++		dev_err(dev, "Can't get irq status (err %d)", err);
++
++		err = dpsw_clear_irq_status(ethsw->mc_io, 0, ethsw->dpsw_handle,
++					    DPSW_IRQ_INDEX_IF, 0xFFFFFFFF);
++		if (err)
++			dev_err(dev, "Can't clear irq status (err %d)", err);
++		goto out;
++	}
++
++	if (status & DPSW_IRQ_EVENT_LINK_CHANGED)
++		ethsw_links_state_update(ethsw);
++
++out:
++	return IRQ_HANDLED;
++}
++
++static int ethsw_setup_irqs(struct fsl_mc_device *sw_dev)
++{
++	struct device *dev = &sw_dev->dev;
++	struct ethsw_core *ethsw = dev_get_drvdata(dev);
++	u32 mask = DPSW_IRQ_EVENT_LINK_CHANGED;
++	struct fsl_mc_device_irq *irq;
++	int err;
++
++	err = fsl_mc_allocate_irqs(sw_dev);
++	if (err) {
++		dev_err(dev, "MC irqs allocation failed\n");
++		return err;
++	}
++
++	if (WARN_ON(sw_dev->obj_desc.irq_count != DPSW_IRQ_NUM)) {
++		err = -EINVAL;
++		goto free_irq;
++	}
++
++	err = dpsw_set_irq_enable(ethsw->mc_io, 0, ethsw->dpsw_handle,
++				  DPSW_IRQ_INDEX_IF, 0);
++	if (err) {
++		dev_err(dev, "dpsw_set_irq_enable err %d\n", err);
++		goto free_irq;
++	}
++
++	irq = sw_dev->irqs[DPSW_IRQ_INDEX_IF];
++
++	err = devm_request_threaded_irq(dev, irq->msi_desc->irq,
++					ethsw_irq0_handler,
++					ethsw_irq0_handler_thread,
++					IRQF_NO_SUSPEND | IRQF_ONESHOT,
++					dev_name(dev), dev);
++	if (err) {
++		dev_err(dev, "devm_request_threaded_irq(): %d", err);
++		goto free_irq;
++	}
++
++	err = dpsw_set_irq_mask(ethsw->mc_io, 0, ethsw->dpsw_handle,
++				DPSW_IRQ_INDEX_IF, mask);
++	if (err) {
++		dev_err(dev, "dpsw_set_irq_mask(): %d", err);
++		goto free_devm_irq;
++	}
++
++	err = dpsw_set_irq_enable(ethsw->mc_io, 0, ethsw->dpsw_handle,
++				  DPSW_IRQ_INDEX_IF, 1);
++	if (err) {
++		dev_err(dev, "dpsw_set_irq_enable(): %d", err);
++		goto free_devm_irq;
++	}
++
++	return 0;
++
++free_devm_irq:
++	devm_free_irq(dev, irq->msi_desc->irq, dev);
++free_irq:
++	fsl_mc_free_irqs(sw_dev);
++	return err;
++}
++
++static void ethsw_teardown_irqs(struct fsl_mc_device *sw_dev)
++{
++	struct device *dev = &sw_dev->dev;
++	struct ethsw_core *ethsw = dev_get_drvdata(dev);
++	struct fsl_mc_device_irq *irq;
++	int err;
++
++	irq = sw_dev->irqs[DPSW_IRQ_INDEX_IF];
++	err = dpsw_set_irq_enable(ethsw->mc_io, 0, ethsw->dpsw_handle,
++				  DPSW_IRQ_INDEX_IF, 0);
++	if (err)
++		dev_err(dev, "dpsw_set_irq_enable err %d\n", err);
++
++	fsl_mc_free_irqs(sw_dev);
++}
++
++static int swdev_port_attr_get(struct net_device *netdev,
++			       struct switchdev_attr *attr)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++
++	switch (attr->id) {
++	case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
++		attr->u.ppid.id_len = 1;
++		attr->u.ppid.id[0] = port_priv->ethsw_data->dev_id;
++		break;
++	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
++		attr->u.brport_flags =
++			(port_priv->ethsw_data->learning ? BR_LEARNING : 0) |
++			(port_priv->flood ? BR_FLOOD : 0);
++		break;
++	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS_SUPPORT:
++		attr->u.brport_flags_support = BR_LEARNING | BR_FLOOD;
++		break;
++	default:
++		return -EOPNOTSUPP;
++	}
++
++	return 0;
++}
++
++static int port_attr_stp_state_set(struct net_device *netdev,
++				   struct switchdev_trans *trans,
++				   u8 state)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++
++	if (switchdev_trans_ph_prepare(trans))
++		return 0;
++
++	return ethsw_port_set_stp_state(port_priv, state);
++}
++
++static int port_attr_br_flags_set(struct net_device *netdev,
++				  struct switchdev_trans *trans,
++				  unsigned long flags)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	int err = 0;
++
++	if (switchdev_trans_ph_prepare(trans))
++		return 0;
++
++	/* Learning is enabled per switch */
++	err = ethsw_set_learning(port_priv->ethsw_data, !!(flags & BR_LEARNING));
++	if (err)
++		goto exit;
++
++	err = ethsw_port_set_flood(port_priv, !!(flags & BR_FLOOD));
++
++exit:
++	return err;
++}
++
++static int swdev_port_attr_set(struct net_device *netdev,
++			       const struct switchdev_attr *attr,
++			       struct switchdev_trans *trans)
++{
++	int err = 0;
++
++	switch (attr->id) {
++	case SWITCHDEV_ATTR_ID_PORT_STP_STATE:
++		err = port_attr_stp_state_set(netdev, trans,
++					      attr->u.stp_state);
++		break;
++	case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:
++		err = port_attr_br_flags_set(netdev, trans,
++					     attr->u.brport_flags);
++		break;
++	case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING:
++		/* VLANs are supported by default  */
++		break;
++	default:
++		err = -EOPNOTSUPP;
++		break;
++	}
++
++	return err;
++}
++
++static int port_vlans_add(struct net_device *netdev,
++			  const struct switchdev_obj_port_vlan *vlan,
++			  struct switchdev_trans *trans)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	int vid, err;
++
++	if (switchdev_trans_ph_prepare(trans))
++		return 0;
++
++	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
++		if (!port_priv->ethsw_data->vlans[vid]) {
++			/* this is a new VLAN */
++			err = ethsw_add_vlan(port_priv->ethsw_data, vid);
++			if (err)
++				return err;
++
++			port_priv->ethsw_data->vlans[vid] |= ETHSW_VLAN_GLOBAL;
++		}
++		err = ethsw_port_add_vlan(port_priv, vid, vlan->flags);
++		if (err)
++			break;
++	}
++
++	return err;
++}
++
++static int swdev_port_obj_add(struct net_device *netdev,
++			      const struct switchdev_obj *obj,
++			      struct switchdev_trans *trans)
++{
++	int err;
++
++	switch (obj->id) {
++	case SWITCHDEV_OBJ_ID_PORT_VLAN:
++		err = port_vlans_add(netdev,
++				     SWITCHDEV_OBJ_PORT_VLAN(obj),
++				     trans);
++		break;
++	default:
++		err = -EOPNOTSUPP;
++		break;
++	}
++
++	return err;
++}
++
++static int ethsw_port_del_vlan(struct ethsw_port_priv *port_priv, u16 vid)
++{
++	struct ethsw_core *ethsw = port_priv->ethsw_data;
++	struct net_device *netdev = port_priv->netdev;
++	struct dpsw_vlan_if_cfg vcfg;
++	int i, err;
++
++	if (!port_priv->vlans[vid])
++		return -ENOENT;
++
++	if (port_priv->vlans[vid] & ETHSW_VLAN_PVID) {
++		err = ethsw_port_set_pvid(port_priv, 0);
++		if (err)
++			return err;
++	}
++
++	vcfg.num_ifs = 1;
++	vcfg.if_id[0] = port_priv->idx;
++	if (port_priv->vlans[vid] & ETHSW_VLAN_UNTAGGED) {
++		err = dpsw_vlan_remove_if_untagged(ethsw->mc_io, 0,
++						   ethsw->dpsw_handle,
++						   vid, &vcfg);
++		if (err) {
++			netdev_err(netdev,
++				   "dpsw_vlan_remove_if_untagged err %d\n",
++				   err);
++		}
++		port_priv->vlans[vid] &= ~ETHSW_VLAN_UNTAGGED;
++	}
++
++	if (port_priv->vlans[vid] & ETHSW_VLAN_MEMBER) {
++		err = dpsw_vlan_remove_if(ethsw->mc_io, 0, ethsw->dpsw_handle,
++					  vid, &vcfg);
++		if (err) {
++			netdev_err(netdev,
++				   "dpsw_vlan_remove_if err %d\n", err);
++			return err;
++		}
++		port_priv->vlans[vid] &= ~ETHSW_VLAN_MEMBER;
++
++		/* Delete VLAN from switch if it is no longer configured on
++		 * any port
++		 */
++		for (i = 0; i < ethsw->sw_attr.num_ifs; i++)
++			if (ethsw->ports[i]->vlans[vid] & ETHSW_VLAN_MEMBER)
++				return 0; /* Found a port member in VID */
++
++		ethsw->vlans[vid] &= ~ETHSW_VLAN_GLOBAL;
++
++		err = ethsw_dellink_switch(ethsw, vid);
++		if (err)
++			return err;
++	}
++
++	return 0;
++}
++
++static int port_vlans_del(struct net_device *netdev,
++			  const struct switchdev_obj_port_vlan *vlan)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++	int vid, err;
++
++	for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
++		err = ethsw_port_del_vlan(port_priv, vid);
++		if (err)
++			break;
++	}
++
++	return err;
++}
++
++static int swdev_port_obj_del(struct net_device *netdev,
++			      const struct switchdev_obj *obj)
++{
++	int err;
++
++	switch (obj->id) {
++	case SWITCHDEV_OBJ_ID_PORT_VLAN:
++		err = port_vlans_del(netdev, SWITCHDEV_OBJ_PORT_VLAN(obj));
++		break;
++	default:
++		err = -EOPNOTSUPP;
++		break;
++	}
++	return err;
++}
++
++static const struct switchdev_ops ethsw_port_switchdev_ops = {
++	.switchdev_port_attr_get	= swdev_port_attr_get,
++	.switchdev_port_attr_set	= swdev_port_attr_set,
++	.switchdev_port_obj_add		= swdev_port_obj_add,
++	.switchdev_port_obj_del		= swdev_port_obj_del,
++};
++
++/* For the moment, only flood setting needs to be updated */
++static int port_bridge_join(struct net_device *netdev)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++
++	/* Enable flooding */
++	return ethsw_port_set_flood(port_priv, 1);
++}
++
++static int port_bridge_leave(struct net_device *netdev)
++{
++	struct ethsw_port_priv *port_priv = netdev_priv(netdev);
++
++	/* Disable flooding */
++	return ethsw_port_set_flood(port_priv, 0);
++}
++
++static int port_netdevice_event(struct notifier_block *unused,
++				unsigned long event, void *ptr)
++{
++	struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
++	struct netdev_notifier_changeupper_info *info = ptr;
++	struct net_device *upper_dev;
++	int err = 0;
++
++	if (netdev->netdev_ops != &ethsw_port_ops)
++		return NOTIFY_DONE;
++
++	/* Handle just upper dev link/unlink for the moment */
++	if (event == NETDEV_CHANGEUPPER) {
++		upper_dev = info->upper_dev;
++		if (netif_is_bridge_master(upper_dev)) {
++			if (info->linking)
++				err = port_bridge_join(netdev);
++			else
++				err = port_bridge_leave(netdev);
++		}
++	}
++
++	return notifier_from_errno(err);
++}
++
++static struct notifier_block port_nb __read_mostly = {
++	.notifier_call = port_netdevice_event,
++};
++
++struct ethsw_switchdev_event_work {
++	struct work_struct work;
++	struct switchdev_notifier_fdb_info fdb_info;
++	struct net_device *dev;
++	unsigned long event;
++};
++
++static void ethsw_switchdev_event_work(struct work_struct *work)
++{
++	struct ethsw_switchdev_event_work *switchdev_work =
++		container_of(work, struct ethsw_switchdev_event_work, work);
++	struct net_device *dev = switchdev_work->dev;
++	struct switchdev_notifier_fdb_info *fdb_info;
++	struct ethsw_port_priv *port_priv;
++
++	rtnl_lock();
++	port_priv = netdev_priv(dev);
++	fdb_info = &switchdev_work->fdb_info;
++
++	switch (switchdev_work->event) {
++	case SWITCHDEV_FDB_ADD_TO_DEVICE:
++		if (is_unicast_ether_addr(fdb_info->addr))
++			ethsw_port_fdb_add_uc(netdev_priv(dev), fdb_info->addr);
++		else
++			ethsw_port_fdb_add_mc(netdev_priv(dev), fdb_info->addr);
++		break;
++	case SWITCHDEV_FDB_DEL_TO_DEVICE:
++		if (is_unicast_ether_addr(fdb_info->addr))
++			ethsw_port_fdb_del_uc(netdev_priv(dev), fdb_info->addr);
++		else
++			ethsw_port_fdb_del_mc(netdev_priv(dev), fdb_info->addr);
++		break;
++	}
++
++	rtnl_unlock();
++	kfree(switchdev_work->fdb_info.addr);
++	kfree(switchdev_work);
++	dev_put(dev);
++}
++
++/* Called under rcu_read_lock() */
++static int port_switchdev_event(struct notifier_block *unused,
++				unsigned long event, void *ptr)
++{
++	struct net_device *dev = switchdev_notifier_info_to_dev(ptr);
++	struct ethsw_switchdev_event_work *switchdev_work;
++	struct switchdev_notifier_fdb_info *fdb_info = ptr;
++
++	switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);
++	if (!switchdev_work)
++		return NOTIFY_BAD;
++
++	INIT_WORK(&switchdev_work->work, ethsw_switchdev_event_work);
++	switchdev_work->dev = dev;
++	switchdev_work->event = event;
++
++	switch (event) {
++	case SWITCHDEV_FDB_ADD_TO_DEVICE:
++	case SWITCHDEV_FDB_DEL_TO_DEVICE:
++		memcpy(&switchdev_work->fdb_info, ptr,
++		       sizeof(switchdev_work->fdb_info));
++		switchdev_work->fdb_info.addr = kzalloc(ETH_ALEN, GFP_ATOMIC);
++		if (!switchdev_work->fdb_info.addr)
++			goto err_addr_alloc;
++
++		ether_addr_copy((u8 *)switchdev_work->fdb_info.addr,
++				fdb_info->addr);
++
++		/* Take a reference on the device to avoid being freed. */
++		dev_hold(dev);
++		break;
++	default:
++		return NOTIFY_DONE;
++	}
++
++	queue_work(ethsw_owq, &switchdev_work->work);
++
++	return NOTIFY_DONE;
++
++err_addr_alloc:
++	kfree(switchdev_work);
++	return NOTIFY_BAD;
++}
++
++static struct notifier_block port_switchdev_nb = {
++	.notifier_call = port_switchdev_event,
++};
++
++static int ethsw_register_notifier(struct device *dev)
++{
++	int err;
++
++	err = register_netdevice_notifier(&port_nb);
++	if (err) {
++		dev_err(dev, "Failed to register netdev notifier\n");
++		return err;
++	}
++
++	err = register_switchdev_notifier(&port_switchdev_nb);
++	if (err) {
++		dev_err(dev, "Failed to register switchdev notifier\n");
++		goto err_switchdev_nb;
++	}
++
++	return 0;
++
++err_switchdev_nb:
++	unregister_netdevice_notifier(&port_nb);
++	return err;
++}
++
++static int ethsw_open(struct ethsw_core *ethsw)
++{
++	struct ethsw_port_priv *port_priv = NULL;
++	int i, err;
++
++	err = dpsw_enable(ethsw->mc_io, 0, ethsw->dpsw_handle);
++	if (err) {
++		dev_err(ethsw->dev, "dpsw_enable err %d\n", err);
++		return err;
++	}
++
++	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
++		port_priv = ethsw->ports[i];
++		err = dev_open(port_priv->netdev);
++		if (err) {
++			netdev_err(port_priv->netdev, "dev_open err %d\n", err);
++			return err;
++		}
++	}
++
++	return 0;
++}
++
++static int ethsw_stop(struct ethsw_core *ethsw)
++{
++	struct ethsw_port_priv *port_priv = NULL;
++	int i, err;
++
++	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
++		port_priv = ethsw->ports[i];
++		dev_close(port_priv->netdev);
++	}
++
++	err = dpsw_disable(ethsw->mc_io, 0, ethsw->dpsw_handle);
++	if (err) {
++		dev_err(ethsw->dev, "dpsw_disable err %d\n", err);
++		return err;
++	}
++
++	return 0;
++}
++
++static int ethsw_init(struct fsl_mc_device *sw_dev)
++{
++	struct device *dev = &sw_dev->dev;
++	struct ethsw_core *ethsw = dev_get_drvdata(dev);
++	u16 version_major, version_minor, i;
++	struct dpsw_stp_cfg stp_cfg;
++	int err;
++
++	ethsw->dev_id = sw_dev->obj_desc.id;
++
++	err = dpsw_open(ethsw->mc_io, 0, ethsw->dev_id, &ethsw->dpsw_handle);
++	if (err) {
++		dev_err(dev, "dpsw_open err %d\n", err);
++		return err;
++	}
++
++	err = dpsw_get_attributes(ethsw->mc_io, 0, ethsw->dpsw_handle,
++				  &ethsw->sw_attr);
++	if (err) {
++		dev_err(dev, "dpsw_get_attributes err %d\n", err);
++		goto err_close;
++	}
++
++	err = dpsw_get_api_version(ethsw->mc_io, 0,
++				   &version_major,
++				   &version_minor);
++	if (err) {
++		dev_err(dev, "dpsw_get_api_version err %d\n", err);
++		goto err_close;
++	}
++
++	/* Minimum supported DPSW version check */
++	if (version_major < DPSW_MIN_VER_MAJOR ||
++	    (version_major == DPSW_MIN_VER_MAJOR &&
++	     version_minor < DPSW_MIN_VER_MINOR)) {
++		dev_err(dev, "DPSW version %d:%d not supported. Use %d.%d or greater.\n",
++			version_major,
++			version_minor,
++			DPSW_MIN_VER_MAJOR, DPSW_MIN_VER_MINOR);
++		err = -ENOTSUPP;
++		goto err_close;
++	}
++
++	err = dpsw_reset(ethsw->mc_io, 0, ethsw->dpsw_handle);
++	if (err) {
++		dev_err(dev, "dpsw_reset err %d\n", err);
++		goto err_close;
++	}
++
++	err = dpsw_fdb_set_learning_mode(ethsw->mc_io, 0, ethsw->dpsw_handle, 0,
++					 DPSW_FDB_LEARNING_MODE_HW);
++	if (err) {
++		dev_err(dev, "dpsw_fdb_set_learning_mode err %d\n", err);
++		goto err_close;
++	}
++
++	stp_cfg.vlan_id = DEFAULT_VLAN_ID;
++	stp_cfg.state = DPSW_STP_STATE_FORWARDING;
++
++	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
++		err = dpsw_if_set_stp(ethsw->mc_io, 0, ethsw->dpsw_handle, i,
++				      &stp_cfg);
++		if (err) {
++			dev_err(dev, "dpsw_if_set_stp err %d for port %d\n",
++				err, i);
++			goto err_close;
++		}
++
++		err = dpsw_if_set_broadcast(ethsw->mc_io, 0,
++					    ethsw->dpsw_handle, i, 1);
++		if (err) {
++			dev_err(dev,
++				"dpsw_if_set_broadcast err %d for port %d\n",
++				err, i);
++			goto err_close;
++		}
++	}
++
++	ethsw_owq = alloc_ordered_workqueue("%s_ordered", WQ_MEM_RECLAIM,
++					    "ethsw");
++	if (!ethsw_owq) {
++		err = -ENOMEM;
++		goto err_close;
++	}
++
++	err = ethsw_register_notifier(dev);
++	if (err)
++		goto err_destroy_ordered_workqueue;
++
++	return 0;
++
++err_destroy_ordered_workqueue:
++	destroy_workqueue(ethsw_owq);
++
++err_close:
++	dpsw_close(ethsw->mc_io, 0, ethsw->dpsw_handle);
++	return err;
++}
++
++static int ethsw_port_init(struct ethsw_port_priv *port_priv, u16 port)
++{
++	const char def_mcast[ETH_ALEN] = {0x01, 0x00, 0x5e, 0x00, 0x00, 0x01};
++	struct net_device *netdev = port_priv->netdev;
++	struct ethsw_core *ethsw = port_priv->ethsw_data;
++	struct dpsw_vlan_if_cfg vcfg;
++	int err;
++
++	/* Switch starts with all ports configured to VLAN 1. Need to
++	 * remove this setting to allow configuration at bridge join
++	 */
++	vcfg.num_ifs = 1;
++	vcfg.if_id[0] = port_priv->idx;
++
++	err = dpsw_vlan_remove_if_untagged(ethsw->mc_io, 0, ethsw->dpsw_handle,
++					   DEFAULT_VLAN_ID, &vcfg);
++	if (err) {
++		netdev_err(netdev, "dpsw_vlan_remove_if_untagged err %d\n",
++			   err);
++		return err;
++	}
++
++	err = ethsw_port_set_pvid(port_priv, 0);
++	if (err)
++		return err;
++
++	err = dpsw_vlan_remove_if(ethsw->mc_io, 0, ethsw->dpsw_handle,
++				  DEFAULT_VLAN_ID, &vcfg);
++	if (err) {
++		netdev_err(netdev, "dpsw_vlan_remove_if err %d\n", err);
++		return err;
++	}
++
++	err = ethsw_port_fdb_add_mc(port_priv, def_mcast);
++
++	return err;
++}
++
++static void ethsw_unregister_notifier(struct device *dev)
++{
++	int err;
++
++	err = unregister_switchdev_notifier(&port_switchdev_nb);
++	if (err)
++		dev_err(dev,
++			"Failed to unregister switchdev notifier (%d)\n", err);
++
++	err = unregister_netdevice_notifier(&port_nb);
++	if (err)
++		dev_err(dev,
++			"Failed to unregister netdev notifier (%d)\n", err);
++}
++
++static void ethsw_takedown(struct fsl_mc_device *sw_dev)
++{
++	struct device *dev = &sw_dev->dev;
++	struct ethsw_core *ethsw = dev_get_drvdata(dev);
++	int err;
++
++	ethsw_unregister_notifier(dev);
++
++	err = dpsw_close(ethsw->mc_io, 0, ethsw->dpsw_handle);
++	if (err)
++		dev_warn(dev, "dpsw_close err %d\n", err);
++}
++
++static int ethsw_remove(struct fsl_mc_device *sw_dev)
++{
++	struct ethsw_port_priv *port_priv;
++	struct ethsw_core *ethsw;
++	struct device *dev;
++	int i;
++
++	dev = &sw_dev->dev;
++	ethsw = dev_get_drvdata(dev);
++
++	ethsw_teardown_irqs(sw_dev);
++
++	destroy_workqueue(ethsw_owq);
++
++	rtnl_lock();
++	ethsw_stop(ethsw);
++	rtnl_unlock();
++
++	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
++		port_priv = ethsw->ports[i];
++		unregister_netdev(port_priv->netdev);
++		free_netdev(port_priv->netdev);
++	}
++	kfree(ethsw->ports);
++
++	ethsw_takedown(sw_dev);
++	fsl_mc_portal_free(ethsw->mc_io);
++
++	kfree(ethsw);
++
++	dev_set_drvdata(dev, NULL);
++
++	return 0;
++}
++
++static int ethsw_probe_port(struct ethsw_core *ethsw, u16 port_idx)
++{
++	struct ethsw_port_priv *port_priv;
++	struct device *dev = ethsw->dev;
++	struct net_device *port_netdev;
++	int err;
++
++	port_netdev = alloc_etherdev(sizeof(struct ethsw_port_priv));
++	if (!port_netdev) {
++		dev_err(dev, "alloc_etherdev error\n");
++		return -ENOMEM;
++	}
++
++	port_priv = netdev_priv(port_netdev);
++	port_priv->netdev = port_netdev;
++	port_priv->ethsw_data = ethsw;
++
++	port_priv->idx = port_idx;
++	port_priv->stp_state = BR_STATE_FORWARDING;
++
++	/* Flooding is implicitly enabled */
++	port_priv->flood = true;
++
++	SET_NETDEV_DEV(port_netdev, dev);
++	port_netdev->netdev_ops = &ethsw_port_ops;
++	port_netdev->ethtool_ops = &ethsw_port_ethtool_ops;
++	port_netdev->switchdev_ops = &ethsw_port_switchdev_ops;
++
++	/* Set MTU limits */
++	port_netdev->min_mtu = ETH_MIN_MTU;
++	port_netdev->max_mtu = ETHSW_MAX_FRAME_LENGTH;
++
++	err = register_netdev(port_netdev);
++	if (err < 0) {
++		dev_err(dev, "register_netdev error %d\n", err);
++			free_netdev(port_netdev);
++			return err;
++		}
++
++	ethsw->ports[port_idx] = port_priv;
++
++	return ethsw_port_init(port_priv, port_idx);
++}
++
++static int ethsw_probe(struct fsl_mc_device *sw_dev)
++{
++	struct device *dev = &sw_dev->dev;
++	struct ethsw_core *ethsw;
++	int i, err;
++
++	/* Allocate switch core*/
++	ethsw = kzalloc(sizeof(*ethsw), GFP_KERNEL);
++
++	if (!ethsw)
++		return -ENOMEM;
++
++	ethsw->dev = dev;
++	dev_set_drvdata(dev, ethsw);
++
++	err = fsl_mc_portal_allocate(sw_dev, 0, &ethsw->mc_io);
++	if (err) {
++		dev_err(dev, "fsl_mc_portal_allocate err %d\n", err);
++		goto err_free_drvdata;
++	}
++
++	err = ethsw_init(sw_dev);
++	if (err)
++		goto err_free_cmdport;
++
++	/* DEFAULT_VLAN_ID is implicitly configured on the switch */
++	ethsw->vlans[DEFAULT_VLAN_ID] = ETHSW_VLAN_MEMBER;
++
++	/* Learning is implicitly enabled */
++	ethsw->learning = true;
++
++	ethsw->ports = kcalloc(ethsw->sw_attr.num_ifs, sizeof(*ethsw->ports),
++			       GFP_KERNEL);
++	if (!(ethsw->ports)) {
++		err = -ENOMEM;
++		goto err_takedown;
++	}
++
++	for (i = 0; i < ethsw->sw_attr.num_ifs; i++) {
++		err = ethsw_probe_port(ethsw, i);
++		if (err)
++			goto err_free_ports;
++	}
++
++	/* Switch starts up enabled */
++	rtnl_lock();
++	err = ethsw_open(ethsw);
++	rtnl_unlock();
++	if (err)
++		goto err_free_ports;
++
++	/* Setup IRQs */
++	err = ethsw_setup_irqs(sw_dev);
++	if (err)
++		goto err_stop;
++
++	dev_info(dev, "probed %d port switch\n", ethsw->sw_attr.num_ifs);
++	return 0;
++
++err_stop:
++	rtnl_lock();
++	ethsw_stop(ethsw);
++	rtnl_unlock();
++
++err_free_ports:
++	/* Cleanup registered ports only */
++	for (i--; i >= 0; i--) {
++		unregister_netdev(ethsw->ports[i]->netdev);
++		free_netdev(ethsw->ports[i]->netdev);
++	}
++	kfree(ethsw->ports);
++
++err_takedown:
++	ethsw_takedown(sw_dev);
++
++err_free_cmdport:
++	fsl_mc_portal_free(ethsw->mc_io);
++
++err_free_drvdata:
++	kfree(ethsw);
++	dev_set_drvdata(dev, NULL);
++
++	return err;
++}
++
++static const struct fsl_mc_device_id ethsw_match_id_table[] = {
++	{
++		.vendor = FSL_MC_VENDOR_FREESCALE,
++		.obj_type = "dpsw",
++	},
++	{ .vendor = 0x0 }
++};
++MODULE_DEVICE_TABLE(fslmc, ethsw_match_id_table);
++
++static struct fsl_mc_driver eth_sw_drv = {
++	.driver = {
++		.name = KBUILD_MODNAME,
++		.owner = THIS_MODULE,
++	},
++	.probe = ethsw_probe,
++	.remove = ethsw_remove,
++	.match_id_table = ethsw_match_id_table
++};
++
++module_fsl_mc_driver(eth_sw_drv);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("DPAA2 Ethernet Switch Driver");
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/ethsw/ethsw.h
+@@ -0,0 +1,90 @@
++/* Copyright 2014-2017 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __ETHSW_H
++#define __ETHSW_H
++
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/rtnetlink.h>
++#include <linux/if_vlan.h>
++#include <uapi/linux/if_bridge.h>
++#include <net/switchdev.h>
++#include <linux/if_bridge.h>
++
++#include "dpsw.h"
++
++/* Number of IRQs supported */
++#define DPSW_IRQ_NUM	2
++
++#define ETHSW_VLAN_MEMBER	1
++#define ETHSW_VLAN_UNTAGGED	2
++#define ETHSW_VLAN_PVID		4
++#define ETHSW_VLAN_GLOBAL	8
++
++/* Maximum Frame Length supported by HW (currently 10k) */
++#define DPAA2_MFL		(10 * 1024)
++#define ETHSW_MAX_FRAME_LENGTH	(DPAA2_MFL - VLAN_ETH_HLEN - ETH_FCS_LEN)
++#define ETHSW_L2_MAX_FRM(mtu)	((mtu) + VLAN_ETH_HLEN + ETH_FCS_LEN)
++
++extern const struct ethtool_ops ethsw_port_ethtool_ops;
++
++struct ethsw_core;
++
++/* Per port private data */
++struct ethsw_port_priv {
++	struct net_device	*netdev;
++	u16			idx;
++	struct ethsw_core	*ethsw_data;
++	u8			link_state;
++	u8			stp_state;
++	bool			flood;
++
++	u8			vlans[VLAN_VID_MASK + 1];
++	u16			pvid;
++};
++
++/* Switch data */
++struct ethsw_core {
++	struct device			*dev;
++	struct fsl_mc_io		*mc_io;
++	u16				dpsw_handle;
++	struct dpsw_attr		sw_attr;
++	int				dev_id;
++	struct ethsw_port_priv		**ports;
++
++	u8				vlans[VLAN_VID_MASK + 1];
++	bool				learning;
++};
++
++#endif	/* __ETHSW_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/evb/Kconfig
+@@ -0,0 +1,7 @@
++config FSL_DPAA2_EVB
++	tristate "DPAA2 Edge Virtual Bridge"
++	depends on FSL_MC_BUS && FSL_DPAA2
++	select VLAN_8021Q
++	default y
++	---help---
++	Prototype driver for DPAA2 Edge Virtual Bridge.
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/evb/Makefile
+@@ -0,0 +1,10 @@
++
++obj-$(CONFIG_FSL_DPAA2_EVB) += dpaa2-evb.o
++
++dpaa2-evb-objs := evb.o dpdmux.o
++
++all:
++	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
++
++clean:
++	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/evb/dpdmux-cmd.h
+@@ -0,0 +1,279 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef _FSL_DPDMUX_CMD_H
++#define _FSL_DPDMUX_CMD_H
++
++/* DPDMUX Version */
++#define DPDMUX_VER_MAJOR		6
++#define DPDMUX_VER_MINOR		1
++
++#define DPDMUX_CMD_BASE_VER		1
++#define DPDMUX_CMD_ID_OFFSET		4
++
++#define DPDMUX_CMD(id)	(((id) << DPDMUX_CMD_ID_OFFSET) | DPDMUX_CMD_BASE_VER)
++
++/* Command IDs */
++#define DPDMUX_CMDID_CLOSE			DPDMUX_CMD(0x800)
++#define DPDMUX_CMDID_OPEN			DPDMUX_CMD(0x806)
++#define DPDMUX_CMDID_CREATE			DPDMUX_CMD(0x906)
++#define DPDMUX_CMDID_DESTROY			DPDMUX_CMD(0x986)
++#define DPDMUX_CMDID_GET_API_VERSION		DPDMUX_CMD(0xa06)
++
++#define DPDMUX_CMDID_ENABLE			DPDMUX_CMD(0x002)
++#define DPDMUX_CMDID_DISABLE			DPDMUX_CMD(0x003)
++#define DPDMUX_CMDID_GET_ATTR			DPDMUX_CMD(0x004)
++#define DPDMUX_CMDID_RESET			DPDMUX_CMD(0x005)
++#define DPDMUX_CMDID_IS_ENABLED			DPDMUX_CMD(0x006)
++
++#define DPDMUX_CMDID_SET_IRQ_ENABLE		DPDMUX_CMD(0x012)
++#define DPDMUX_CMDID_GET_IRQ_ENABLE		DPDMUX_CMD(0x013)
++#define DPDMUX_CMDID_SET_IRQ_MASK		DPDMUX_CMD(0x014)
++#define DPDMUX_CMDID_GET_IRQ_MASK		DPDMUX_CMD(0x015)
++#define DPDMUX_CMDID_GET_IRQ_STATUS		DPDMUX_CMD(0x016)
++#define DPDMUX_CMDID_CLEAR_IRQ_STATUS		DPDMUX_CMD(0x017)
++
++#define DPDMUX_CMDID_SET_MAX_FRAME_LENGTH	DPDMUX_CMD(0x0a1)
++
++#define DPDMUX_CMDID_UL_RESET_COUNTERS		DPDMUX_CMD(0x0a3)
++
++#define DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES	DPDMUX_CMD(0x0a7)
++#define DPDMUX_CMDID_IF_GET_ATTR		DPDMUX_CMD(0x0a8)
++#define DPDMUX_CMDID_IF_ENABLE			DPDMUX_CMD(0x0a9)
++#define DPDMUX_CMDID_IF_DISABLE			DPDMUX_CMD(0x0aa)
++
++#define DPDMUX_CMDID_IF_ADD_L2_RULE		DPDMUX_CMD(0x0b0)
++#define DPDMUX_CMDID_IF_REMOVE_L2_RULE		DPDMUX_CMD(0x0b1)
++#define DPDMUX_CMDID_IF_GET_COUNTER		DPDMUX_CMD(0x0b2)
++#define DPDMUX_CMDID_IF_SET_LINK_CFG		DPDMUX_CMD(0x0b3)
++#define DPDMUX_CMDID_IF_GET_LINK_STATE		DPDMUX_CMD(0x0b4)
++
++#define DPDMUX_CMDID_SET_CUSTOM_KEY		DPDMUX_CMD(0x0b5)
++#define DPDMUX_CMDID_ADD_CUSTOM_CLS_ENTRY	DPDMUX_CMD(0x0b6)
++#define DPDMUX_CMDID_REMOVE_CUSTOM_CLS_ENTRY	DPDMUX_CMD(0x0b7)
++
++#define DPDMUX_MASK(field)        \
++	GENMASK(DPDMUX_##field##_SHIFT + DPDMUX_##field##_SIZE - 1, \
++		DPDMUX_##field##_SHIFT)
++#define dpdmux_set_field(var, field, val) \
++	((var) |= (((val) << DPDMUX_##field##_SHIFT) & DPDMUX_MASK(field)))
++#define dpdmux_get_field(var, field)      \
++	(((var) & DPDMUX_MASK(field)) >> DPDMUX_##field##_SHIFT)
++
++struct dpdmux_cmd_open {
++	u32 dpdmux_id;
++};
++
++struct dpdmux_cmd_create {
++	u8 method;
++	u8 manip;
++	u16 num_ifs;
++	u32 pad;
++
++	u16 adv_max_dmat_entries;
++	u16 adv_max_mc_groups;
++	u16 adv_max_vlan_ids;
++	u16 pad1;
++
++	u64 options;
++};
++
++struct dpdmux_cmd_destroy {
++	u32 dpdmux_id;
++};
++
++#define DPDMUX_ENABLE_SHIFT	0
++#define DPDMUX_ENABLE_SIZE	1
++
++struct dpdmux_rsp_is_enabled {
++	u8 en;
++};
++
++struct dpdmux_cmd_set_irq_enable {
++	u8 enable;
++	u8 pad[3];
++	u8 irq_index;
++};
++
++struct dpdmux_cmd_get_irq_enable {
++	u32 pad;
++	u8 irq_index;
++};
++
++struct dpdmux_rsp_get_irq_enable {
++	u8 enable;
++};
++
++struct dpdmux_cmd_set_irq_mask {
++	u32 mask;
++	u8 irq_index;
++};
++
++struct dpdmux_cmd_get_irq_mask {
++	u32 pad;
++	u8 irq_index;
++};
++
++struct dpdmux_rsp_get_irq_mask {
++	u32 mask;
++};
++
++struct dpdmux_cmd_get_irq_status {
++	u32 status;
++	u8 irq_index;
++};
++
++struct dpdmux_rsp_get_irq_status {
++	u32 status;
++};
++
++struct dpdmux_cmd_clear_irq_status {
++	u32 status;
++	u8 irq_index;
++};
++
++struct dpdmux_rsp_get_attr {
++	u8 method;
++	u8 manip;
++	u16 num_ifs;
++	u16 mem_size;
++	u16 pad;
++
++	u64 pad1;
++
++	u32 id;
++	u32 pad2;
++
++	u64 options;
++};
++
++struct dpdmux_cmd_set_max_frame_length {
++	u16 max_frame_length;
++};
++
++#define DPDMUX_ACCEPTED_FRAMES_TYPE_SHIFT	0
++#define DPDMUX_ACCEPTED_FRAMES_TYPE_SIZE	4
++#define DPDMUX_UNACCEPTED_FRAMES_ACTION_SHIFT	4
++#define DPDMUX_UNACCEPTED_FRAMES_ACTION_SIZE	4
++
++struct dpdmux_cmd_if_set_accepted_frames {
++	u16 if_id;
++	u8 frames_options;
++};
++
++struct dpdmux_cmd_if {
++	u16 if_id;
++};
++
++struct dpdmux_rsp_if_get_attr {
++	u8 pad[3];
++	u8 enabled;
++	u8 pad1[3];
++	u8 accepted_frames_type;
++	u32 rate;
++};
++
++struct dpdmux_cmd_if_l2_rule {
++	u16 if_id;
++	u8 mac_addr5;
++	u8 mac_addr4;
++	u8 mac_addr3;
++	u8 mac_addr2;
++	u8 mac_addr1;
++	u8 mac_addr0;
++
++	u32 pad;
++	u16 vlan_id;
++};
++
++struct dpdmux_cmd_if_get_counter {
++	u16 if_id;
++	u8 counter_type;
++};
++
++struct dpdmux_rsp_if_get_counter {
++	u64 pad;
++	u64 counter;
++};
++
++struct dpdmux_cmd_if_set_link_cfg {
++	u16 if_id;
++	u16 pad[3];
++
++	u32 rate;
++	u32 pad1;
++
++	u64 options;
++};
++
++struct dpdmux_cmd_if_get_link_state {
++	u16 if_id;
++};
++
++struct dpdmux_rsp_if_get_link_state {
++	u32 pad;
++	u8 up;
++	u8 pad1[3];
++
++	u32 rate;
++	u32 pad2;
++
++	u64 options;
++};
++
++struct dpdmux_rsp_get_api_version {
++	u16 major;
++	u16 minor;
++};
++
++struct dpdmux_set_custom_key {
++	u64 pad[6];
++	u64 key_cfg_iova;
++};
++
++struct dpdmux_cmd_add_custom_cls_entry {
++	u8 pad[3];
++	u8 key_size;
++	u16 pad1;
++	u16 dest_if;
++	u64 key_iova;
++	u64 mask_iova;
++};
++
++struct dpdmux_cmd_remove_custom_cls_entry {
++	u8 pad[3];
++	u8 key_size;
++	u32 pad1;
++	u64 key_iova;
++	u64 mask_iova;
++};
++
++#endif /* _FSL_DPDMUX_CMD_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/evb/dpdmux.c
+@@ -0,0 +1,1111 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#include <linux/fsl/mc.h>
++#include "dpdmux.h"
++#include "dpdmux-cmd.h"
++
++/**
++ * dpdmux_open() - Open a control session for the specified object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @dpdmux_id:		DPDMUX unique ID
++ * @token:		Returned token; use in subsequent API calls
++ *
++ * This function can be used to open a control session for an
++ * already created object; an object may have been declared in
++ * the DPL or by calling the dpdmux_create() function.
++ * This function returns a unique authentication token,
++ * associated with the specific object ID and the specific MC
++ * portal; this token must be used in all subsequent commands for
++ * this specific object.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_open(struct fsl_mc_io *mc_io,
++		u32 cmd_flags,
++		int dpdmux_id,
++		u16 *token)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_open *cmd_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_OPEN,
++					  cmd_flags,
++					  0);
++	cmd_params = (struct dpdmux_cmd_open *)cmd.params;
++	cmd_params->dpdmux_id = cpu_to_le32(dpdmux_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*token = mc_cmd_hdr_read_token(&cmd);
++
++	return 0;
++}
++
++/**
++ * dpdmux_close() - Close the control session of the object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:		Token of DPDMUX object
++ *
++ * After this function is called, no further operations are
++ * allowed on the object without opening a new control session.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_close(struct fsl_mc_io *mc_io,
++		 u32 cmd_flags,
++		 u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CLOSE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_create() - Create the DPDMUX object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @dprc_token:	Parent container token; '0' for default container
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @cfg:	Configuration structure
++ * @obj_id: returned object id
++ *
++ * Create the DPDMUX object, allocate required resources and
++ * perform required initialization.
++ *
++ * The object can be created either by declaring it in the
++ * DPL file, or by calling this function.
++ *
++ * The function accepts an authentication token of a parent
++ * container that this object should be assigned to. The token
++ * can be '0' so the object will be assigned to the default container.
++ * The newly created object can be opened with the returned
++ * object id and using the container's associated tokens and MC portals.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_create(struct fsl_mc_io *mc_io,
++		  u16 dprc_token,
++		  u32 cmd_flags,
++		  const struct dpdmux_cfg *cfg,
++		  u32 *obj_id)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_create *cmd_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CREATE,
++					  cmd_flags,
++					  dprc_token);
++	cmd_params = (struct dpdmux_cmd_create *)cmd.params;
++	cmd_params->method = cfg->method;
++	cmd_params->manip = cfg->manip;
++	cmd_params->num_ifs = cpu_to_le16(cfg->num_ifs);
++	cmd_params->adv_max_dmat_entries =
++			cpu_to_le16(cfg->adv.max_dmat_entries);
++	cmd_params->adv_max_mc_groups = cpu_to_le16(cfg->adv.max_mc_groups);
++	cmd_params->adv_max_vlan_ids = cpu_to_le16(cfg->adv.max_vlan_ids);
++	cmd_params->options = cpu_to_le64(cfg->adv.options);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*obj_id = mc_cmd_hdr_read_token(&cmd);
++
++	return 0;
++}
++
++/**
++ * dpdmux_destroy() - Destroy the DPDMUX object and release all its resources.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @dprc_token: Parent container token; '0' for default container
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @object_id:	The object id; it must be a valid id within the container that
++ * created this object;
++ *
++ * The function accepts the authentication token of the parent container that
++ * created the object (not the one that currently owns the object). The object
++ * is searched within parent using the provided 'object_id'.
++ * All tokens to the object must be closed before calling destroy.
++ *
++ * Return:	'0' on Success; error code otherwise.
++ */
++int dpdmux_destroy(struct fsl_mc_io *mc_io,
++		   u16 dprc_token,
++		   u32 cmd_flags,
++		   u32 object_id)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_destroy *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_DESTROY,
++					  cmd_flags,
++					  dprc_token);
++	cmd_params = (struct dpdmux_cmd_destroy *)cmd.params;
++	cmd_params->dpdmux_id = cpu_to_le32(object_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_enable() - Enable DPDMUX functionality
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_enable(struct fsl_mc_io *mc_io,
++		  u32 cmd_flags,
++		  u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_ENABLE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_disable() - Disable DPDMUX functionality
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_disable(struct fsl_mc_io *mc_io,
++		   u32 cmd_flags,
++		   u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_DISABLE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_is_enabled() - Check if the DPDMUX is enabled.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @en:		Returns '1' if object is enabled; '0' otherwise
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_is_enabled(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      int *en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_rsp_is_enabled *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IS_ENABLED,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpdmux_rsp_is_enabled *)cmd.params;
++	*en = dpdmux_get_field(rsp_params->en, ENABLE);
++
++	return 0;
++}
++
++/**
++ * dpdmux_reset() - Reset the DPDMUX, returns the object to initial state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_reset(struct fsl_mc_io *mc_io,
++		 u32 cmd_flags,
++		 u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_RESET,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_set_irq_enable() - Set overall interrupt state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Interrupt state - enable = 1, disable = 0
++ *
++ * Allows GPP software to control when interrupts are generated.
++ * Each interrupt can have up to 32 causes.  The enable/disable control's the
++ * overall interrupt state. if the interrupt is disabled no causes will cause
++ * an interrupt.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_set_irq_enable(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u8 en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_set_irq_enable *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_set_irq_enable *)cmd.params;
++	cmd_params->enable = en;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_get_irq_enable() - Get overall interrupt state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Returned interrupt state - enable = 1, disable = 0
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_get_irq_enable(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u8 *en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_get_irq_enable *cmd_params;
++	struct dpdmux_rsp_get_irq_enable *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_get_irq_enable *)cmd.params;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpdmux_rsp_get_irq_enable *)cmd.params;
++	*en = rsp_params->enable;
++
++	return 0;
++}
++
++/**
++ * dpdmux_set_irq_mask() - Set interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	event mask to trigger interrupt;
++ *		each bit:
++ *			0 = ignore event
++ *			1 = consider event for asserting IRQ
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_set_irq_mask(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u32 mask)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_set_irq_mask *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_set_irq_mask *)cmd.params;
++	cmd_params->mask = cpu_to_le32(mask);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_get_irq_mask() - Get interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	Returned event mask to trigger interrupt
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_get_irq_mask(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u32 *mask)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_get_irq_mask *cmd_params;
++	struct dpdmux_rsp_get_irq_mask *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_get_irq_mask *)cmd.params;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpdmux_rsp_get_irq_mask *)cmd.params;
++	*mask = le32_to_cpu(rsp_params->mask);
++
++	return 0;
++}
++
++/**
++ * dpdmux_get_irq_status() - Get the current status of any pending interrupts.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @irq_index:	The interrupt index to configure
++ * @status:	Returned interrupts status - one bit per cause:
++ *			0 = no interrupt pending
++ *			1 = interrupt pending
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_get_irq_status(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u32 *status)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_get_irq_status *cmd_params;
++	struct dpdmux_rsp_get_irq_status *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_get_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(*status);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpdmux_rsp_get_irq_status *)cmd.params;
++	*status = le32_to_cpu(rsp_params->status);
++
++	return 0;
++}
++
++/**
++ * dpdmux_clear_irq_status() - Clear a pending interrupt's status
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @irq_index:	The interrupt index to configure
++ * @status:	bits to clear (W1C) - one bit per cause:
++ *			0 = don't change
++ *			1 = clear status bit
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_clear_irq_status(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    u8 irq_index,
++			    u32 status)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_clear_irq_status *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_CLEAR_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_clear_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(status);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_get_attributes() - Retrieve DPDMUX attributes
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @attr:	Returned object's attributes
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_get_attributes(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  struct dpdmux_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_rsp_get_attr *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_ATTR,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpdmux_rsp_get_attr *)cmd.params;
++	attr->id = le32_to_cpu(rsp_params->id);
++	attr->options = le64_to_cpu(rsp_params->options);
++	attr->method = rsp_params->method;
++	attr->manip = rsp_params->manip;
++	attr->num_ifs = le16_to_cpu(rsp_params->num_ifs);
++	attr->mem_size = le16_to_cpu(rsp_params->mem_size);
++
++	return 0;
++}
++
++/**
++ * dpdmux_if_enable() - Enable Interface
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @if_id:	Interface Identifier
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpdmux_if_enable(struct fsl_mc_io *mc_io,
++		     u32 cmd_flags,
++		     u16 token,
++		     u16 if_id)
++{
++	struct dpdmux_cmd_if *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_if_disable() - Disable Interface
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @if_id:	Interface Identifier
++ *
++ * Return:	Completion status. '0' on Success; Error code otherwise.
++ */
++int dpdmux_if_disable(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      u16 if_id)
++{
++	struct dpdmux_cmd_if *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_DISABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_set_max_frame_length() - Set the maximum frame length in DPDMUX
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:		Token of DPDMUX object
++ * @max_frame_length:	The required maximum frame length
++ *
++ * Update the maximum frame length on all DMUX interfaces.
++ * In case of VEPA, the maximum frame length on all dmux interfaces
++ * will be updated with the minimum value of the mfls of the connected
++ * dpnis and the actual value of dmux mfl.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_set_max_frame_length(struct fsl_mc_io *mc_io,
++				u32 cmd_flags,
++				u16 token,
++				u16 max_frame_length)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_set_max_frame_length *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_MAX_FRAME_LENGTH,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_set_max_frame_length *)cmd.params;
++	cmd_params->max_frame_length = cpu_to_le16(max_frame_length);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_ul_reset_counters() - Function resets the uplink counter
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_ul_reset_counters(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_UL_RESET_COUNTERS,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_if_set_accepted_frames() - Set the accepted frame types
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @if_id:	Interface ID (0 for uplink, or 1-num_ifs);
++ * @cfg:	Frame types configuration
++ *
++ * if 'DPDMUX_ADMIT_ONLY_VLAN_TAGGED' is set - untagged frames or
++ * priority-tagged frames are discarded.
++ * if 'DPDMUX_ADMIT_ONLY_UNTAGGED' is set - untagged frames or
++ * priority-tagged frames are accepted.
++ * if 'DPDMUX_ADMIT_ALL' is set (default mode) - all VLAN tagged,
++ * untagged and priority-tagged frame are accepted;
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_if_set_accepted_frames(struct fsl_mc_io *mc_io,
++				  u32 cmd_flags,
++				  u16 token,
++				  u16 if_id,
++				  const struct dpdmux_accepted_frames *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_if_set_accepted_frames *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if_set_accepted_frames *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	dpdmux_set_field(cmd_params->frames_options, ACCEPTED_FRAMES_TYPE,
++			 cfg->type);
++	dpdmux_set_field(cmd_params->frames_options, UNACCEPTED_FRAMES_ACTION,
++			 cfg->unaccept_act);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_if_get_attributes() - Obtain DPDMUX interface attributes
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @if_id:	Interface ID (0 for uplink, or 1-num_ifs);
++ * @attr:	Interface attributes
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_if_get_attributes(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     u16 if_id,
++			     struct dpdmux_if_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_if *cmd_params;
++	struct dpdmux_rsp_if_get_attr *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_ATTR,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpdmux_rsp_if_get_attr *)cmd.params;
++	attr->rate = le32_to_cpu(rsp_params->rate);
++	attr->enabled = dpdmux_get_field(rsp_params->enabled, ENABLE);
++	attr->accept_frame_type =
++			dpdmux_get_field(rsp_params->accepted_frames_type,
++					 ACCEPTED_FRAMES_TYPE);
++
++	return 0;
++}
++
++/**
++ * dpdmux_if_remove_l2_rule() - Remove L2 rule from DPDMUX table
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @if_id:	Destination interface ID
++ * @rule:	L2 rule
++ *
++ * Function removes a L2 rule from DPDMUX table
++ * or adds an interface to an existing multicast address
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_if_remove_l2_rule(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     u16 if_id,
++			     const struct dpdmux_l2_rule *rule)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_if_l2_rule *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_REMOVE_L2_RULE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if_l2_rule *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	cmd_params->vlan_id = cpu_to_le16(rule->vlan_id);
++	cmd_params->mac_addr5 = rule->mac_addr[5];
++	cmd_params->mac_addr4 = rule->mac_addr[4];
++	cmd_params->mac_addr3 = rule->mac_addr[3];
++	cmd_params->mac_addr2 = rule->mac_addr[2];
++	cmd_params->mac_addr1 = rule->mac_addr[1];
++	cmd_params->mac_addr0 = rule->mac_addr[0];
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_if_add_l2_rule() - Add L2 rule into DPDMUX table
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPDMUX object
++ * @if_id:	Destination interface ID
++ * @rule:	L2 rule
++ *
++ * Function adds a L2 rule into DPDMUX table
++ * or adds an interface to an existing multicast address
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_if_add_l2_rule(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u16 if_id,
++			  const struct dpdmux_l2_rule *rule)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_if_l2_rule *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_ADD_L2_RULE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if_l2_rule *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	cmd_params->vlan_id = cpu_to_le16(rule->vlan_id);
++	cmd_params->mac_addr5 = rule->mac_addr[5];
++	cmd_params->mac_addr4 = rule->mac_addr[4];
++	cmd_params->mac_addr3 = rule->mac_addr[3];
++	cmd_params->mac_addr2 = rule->mac_addr[2];
++	cmd_params->mac_addr1 = rule->mac_addr[1];
++	cmd_params->mac_addr0 = rule->mac_addr[0];
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_if_get_counter() - Functions obtains specific counter of an interface
++ * @mc_io: Pointer to MC portal's I/O object
++ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token: Token of DPDMUX object
++ * @if_id:  Interface Id
++ * @counter_type: counter type
++ * @counter: Returned specific counter information
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_if_get_counter(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u16 if_id,
++			  enum dpdmux_counter_type counter_type,
++			  u64 *counter)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_if_get_counter *cmd_params;
++	struct dpdmux_rsp_if_get_counter *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_COUNTER,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if_get_counter *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	cmd_params->counter_type = counter_type;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpdmux_rsp_if_get_counter *)cmd.params;
++	*counter = le64_to_cpu(rsp_params->counter);
++
++	return 0;
++}
++
++/**
++ * dpdmux_if_set_link_cfg() - set the link configuration.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token: Token of DPSW object
++ * @if_id: interface id
++ * @cfg: Link configuration
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpdmux_if_set_link_cfg(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u16 if_id,
++			   struct dpdmux_link_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_if_set_link_cfg *cmd_params;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_SET_LINK_CFG,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if_set_link_cfg *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++	cmd_params->rate = cpu_to_le32(cfg->rate);
++	cmd_params->options = cpu_to_le64(cfg->options);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_if_get_link_state - Return the link state
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token: Token of DPSW object
++ * @if_id: interface id
++ * @state: link state
++ *
++ * @returns	'0' on Success; Error code otherwise.
++ */
++int dpdmux_if_get_link_state(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     u16 if_id,
++			     struct dpdmux_link_state *state)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_cmd_if_get_link_state *cmd_params;
++	struct dpdmux_rsp_if_get_link_state *rsp_params;
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_IF_GET_LINK_STATE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_if_get_link_state *)cmd.params;
++	cmd_params->if_id = cpu_to_le16(if_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpdmux_rsp_if_get_link_state *)cmd.params;
++	state->rate = le32_to_cpu(rsp_params->rate);
++	state->options = le64_to_cpu(rsp_params->options);
++	state->up = dpdmux_get_field(rsp_params->up, ENABLE);
++
++	return 0;
++}
++
++/**
++ * dpdmux_set_custom_key - Set a custom classification key.
++ *
++ * This API is only available for DPDMUX instance created with
++ * DPDMUX_METHOD_CUSTOM.  This API must be called before populating the
++ * classification table using dpdmux_add_custom_cls_entry.
++ *
++ * Calls to dpdmux_set_custom_key remove all existing classification entries
++ * that may have been added previously using dpdmux_add_custom_cls_entry.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token: Token of DPSW object
++ * @if_id: interface id
++ * @key_cfg_iova: DMA address of a configuration structure set up using
++ *		  dpkg_prepare_key_cfg. Maximum key size is 24 bytes.
++ *
++ * @returns	'0' on Success; Error code otherwise.
++ */
++int dpdmux_set_custom_key(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u64 key_cfg_iova)
++{
++	struct dpdmux_set_custom_key *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_SET_CUSTOM_KEY,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_set_custom_key *)cmd.params;
++	cmd_params->key_cfg_iova = cpu_to_le64(key_cfg_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_add_custom_cls_entry - Adds a custom classification entry.
++ *
++ * This API is only available for DPDMUX instances created with
++ * DPDMUX_METHOD_CUSTOM.  Before calling this function a classification key
++ * composition rule must be set up using dpdmux_set_custom_key.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token: Token of DPSW object
++ * @rule: Classification rule to insert.  Rules cannot be duplicated, if a
++ *	matching rule already exists, the action will be replaced.
++ * @action: Action to perform for matching traffic.
++ *
++ * @returns	'0' on Success; Error code otherwise.
++ */
++int dpdmux_add_custom_cls_entry(struct fsl_mc_io *mc_io,
++				u32 cmd_flags,
++				u16 token,
++				struct dpdmux_rule_cfg *rule,
++				struct dpdmux_cls_action *action)
++{
++	struct dpdmux_cmd_add_custom_cls_entry *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_ADD_CUSTOM_CLS_ENTRY,
++					  cmd_flags,
++					  token);
++
++	cmd_params = (struct dpdmux_cmd_add_custom_cls_entry *)cmd.params;
++	cmd_params->key_size = rule->key_size;
++	cmd_params->dest_if = cpu_to_le16(action->dest_if);
++	cmd_params->key_iova = cpu_to_le64(rule->key_iova);
++	cmd_params->mask_iova = cpu_to_le64(rule->mask_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_remove_custom_cls_entry - Removes a custom classification entry.
++ *
++ * This API is only available for DPDMUX instances created with
++ * DPDMUX_METHOD_CUSTOM.  The API can be used to remove classification
++ * entries previously inserted using dpdmux_add_custom_cls_entry.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token: Token of DPSW object
++ * @rule: Classification rule to remove
++ *
++ * @returns	'0' on Success; Error code otherwise.
++ */
++int dpdmux_remove_custom_cls_entry(struct fsl_mc_io *mc_io,
++				   u32 cmd_flags,
++				   u16 token,
++				   struct dpdmux_rule_cfg *rule)
++{
++	struct dpdmux_cmd_remove_custom_cls_entry *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_REMOVE_CUSTOM_CLS_ENTRY,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpdmux_cmd_remove_custom_cls_entry *)cmd.params;
++	cmd_params->key_size = rule->key_size;
++	cmd_params->key_iova = cpu_to_le64(rule->key_iova);
++	cmd_params->mask_iova = cpu_to_le64(rule->mask_iova);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpdmux_get_api_version() - Get Data Path Demux API version
++ * @mc_io:  Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @major_ver:	Major version of data path demux API
++ * @minor_ver:	Minor version of data path demux API
++ *
++ * Return:  '0' on Success; Error code otherwise.
++ */
++int dpdmux_get_api_version(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 *major_ver,
++			   u16 *minor_ver)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpdmux_rsp_get_api_version *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPDMUX_CMDID_GET_API_VERSION,
++					cmd_flags,
++					0);
++
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpdmux_rsp_get_api_version *)cmd.params;
++	*major_ver = le16_to_cpu(rsp_params->major);
++	*minor_ver = le16_to_cpu(rsp_params->minor);
++
++	return 0;
++}
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/evb/dpdmux.h
+@@ -0,0 +1,453 @@
++/* Copyright 2013-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef __FSL_DPDMUX_H
++#define __FSL_DPDMUX_H
++
++struct fsl_mc_io;
++
++/* Data Path Demux API
++ * Contains API for handling DPDMUX topology and functionality
++ */
++
++int dpdmux_open(struct fsl_mc_io *mc_io,
++		u32 cmd_flags,
++		int dpdmux_id,
++		u16 *token);
++
++int dpdmux_close(struct fsl_mc_io *mc_io,
++		 u32 cmd_flags,
++		 u16 token);
++
++/**
++ * DPDMUX general options
++ */
++
++/**
++ * Enable bridging between internal interfaces
++ */
++#define DPDMUX_OPT_BRIDGE_EN	0x0000000000000002ULL
++
++/**
++ * Mask support for classification
++ */
++#define DPDMUX_OPT_CLS_MASK_SUPPORT		0x0000000000000020ULL
++
++#define DPDMUX_IRQ_INDEX_IF	0x0000
++#define DPDMUX_IRQ_INDEX	0x0001
++
++/**
++ * IRQ event - Indicates that the link state changed
++ */
++#define DPDMUX_IRQ_EVENT_LINK_CHANGED	0x0001
++
++/**
++ * enum dpdmux_manip - DPDMUX manipulation operations
++ * @DPDMUX_MANIP_NONE:	No manipulation on frames
++ * @DPDMUX_MANIP_ADD_REMOVE_S_VLAN: Add S-VLAN on egress, remove it on ingress
++ */
++enum dpdmux_manip {
++	DPDMUX_MANIP_NONE = 0x0,
++	DPDMUX_MANIP_ADD_REMOVE_S_VLAN = 0x1
++};
++
++/**
++ * enum dpdmux_method - DPDMUX method options
++ * @DPDMUX_METHOD_NONE: no DPDMUX method
++ * @DPDMUX_METHOD_C_VLAN_MAC: DPDMUX based on C-VLAN and MAC address
++ * @DPDMUX_METHOD_MAC: DPDMUX based on MAC address
++ * @DPDMUX_METHOD_C_VLAN: DPDMUX based on C-VLAN
++ * @DPDMUX_METHOD_S_VLAN: DPDMUX based on S-VLAN
++ */
++enum dpdmux_method {
++	DPDMUX_METHOD_NONE = 0x0,
++	DPDMUX_METHOD_C_VLAN_MAC = 0x1,
++	DPDMUX_METHOD_MAC = 0x2,
++	DPDMUX_METHOD_C_VLAN = 0x3,
++	DPDMUX_METHOD_S_VLAN = 0x4,
++	DPDMUX_METHOD_CUSTOM = 0x5
++};
++
++/**
++ * struct dpdmux_cfg - DPDMUX configuration parameters
++ * @method: Defines the operation method for the DPDMUX address table
++ * @manip: Required manipulation operation
++ * @num_ifs: Number of interfaces (excluding the uplink interface)
++ * @adv: Advanced parameters; default is all zeros;
++ *	 use this structure to change default settings
++ */
++struct dpdmux_cfg {
++	enum dpdmux_method method;
++	enum dpdmux_manip manip;
++	u16 num_ifs;
++	/**
++	 * struct adv - Advanced parameters
++	 * @options: DPDMUX options - combination of 'DPDMUX_OPT_<X>' flags
++	 * @max_dmat_entries: Maximum entries in DPDMUX address table
++	 *		0 - indicates default: 64 entries per interface.
++	 * @max_mc_groups: Number of multicast groups in DPDMUX table
++	 *		0 - indicates default: 32 multicast groups
++	 * @max_vlan_ids: max vlan ids allowed in the system -
++	 *		relevant only case of working in mac+vlan method.
++	 *		0 - indicates default 16 vlan ids.
++	 */
++	struct {
++		u64 options;
++		u16 max_dmat_entries;
++		u16 max_mc_groups;
++		u16 max_vlan_ids;
++	} adv;
++};
++
++int dpdmux_create(struct fsl_mc_io *mc_io,
++		  u16 dprc_token,
++		  u32 cmd_flags,
++		  const struct dpdmux_cfg *cfg,
++		  u32 *obj_id);
++
++int dpdmux_destroy(struct fsl_mc_io *mc_io,
++		   u16 dprc_token,
++		   u32 cmd_flags,
++		   u32 object_id);
++
++int dpdmux_enable(struct fsl_mc_io *mc_io,
++		  u32 cmd_flags,
++		  u16 token);
++
++int dpdmux_disable(struct fsl_mc_io *mc_io,
++		   u32 cmd_flags,
++		   u16 token);
++
++int dpdmux_is_enabled(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      int *en);
++
++int dpdmux_reset(struct fsl_mc_io *mc_io,
++		 u32 cmd_flags,
++		 u16 token);
++
++int dpdmux_set_irq_enable(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u8 en);
++
++int dpdmux_get_irq_enable(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u8 *en);
++
++int dpdmux_set_irq_mask(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u32 mask);
++
++int dpdmux_get_irq_mask(struct fsl_mc_io *mc_io,
++			u32 cmd_flags,
++			u16 token,
++			u8 irq_index,
++			u32 *mask);
++
++int dpdmux_get_irq_status(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u8 irq_index,
++			  u32 *status);
++
++int dpdmux_clear_irq_status(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    u8 irq_index,
++			    u32 status);
++
++/**
++ * struct dpdmux_attr - Structure representing DPDMUX attributes
++ * @id: DPDMUX object ID
++ * @options: Configuration options (bitmap)
++ * @method: DPDMUX address table method
++ * @manip: DPDMUX manipulation type
++ * @num_ifs: Number of interfaces (excluding the uplink interface)
++ * @mem_size: DPDMUX frame storage memory size
++ */
++struct dpdmux_attr {
++	int id;
++	u64 options;
++	enum dpdmux_method method;
++	enum dpdmux_manip manip;
++	u16 num_ifs;
++	u16 mem_size;
++};
++
++int dpdmux_get_attributes(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  struct dpdmux_attr *attr);
++
++int dpdmux_set_max_frame_length(struct fsl_mc_io *mc_io,
++				u32 cmd_flags,
++				u16 token,
++				u16 max_frame_length);
++
++/**
++ * enum dpdmux_counter_type - Counter types
++ * @DPDMUX_CNT_ING_FRAME: Counts ingress frames
++ * @DPDMUX_CNT_ING_BYTE: Counts ingress bytes
++ * @DPDMUX_CNT_ING_FLTR_FRAME: Counts filtered ingress frames
++ * @DPDMUX_CNT_ING_FRAME_DISCARD: Counts discarded ingress frames
++ * @DPDMUX_CNT_ING_MCAST_FRAME: Counts ingress multicast frames
++ * @DPDMUX_CNT_ING_MCAST_BYTE: Counts ingress multicast bytes
++ * @DPDMUX_CNT_ING_BCAST_FRAME: Counts ingress broadcast frames
++ * @DPDMUX_CNT_ING_BCAST_BYTES: Counts ingress broadcast bytes
++ * @DPDMUX_CNT_EGR_FRAME: Counts egress frames
++ * @DPDMUX_CNT_EGR_BYTE: Counts egress bytes
++ * @DPDMUX_CNT_EGR_FRAME_DISCARD: Counts discarded egress frames
++ */
++enum dpdmux_counter_type {
++	DPDMUX_CNT_ING_FRAME = 0x0,
++	DPDMUX_CNT_ING_BYTE = 0x1,
++	DPDMUX_CNT_ING_FLTR_FRAME = 0x2,
++	DPDMUX_CNT_ING_FRAME_DISCARD = 0x3,
++	DPDMUX_CNT_ING_MCAST_FRAME = 0x4,
++	DPDMUX_CNT_ING_MCAST_BYTE = 0x5,
++	DPDMUX_CNT_ING_BCAST_FRAME = 0x6,
++	DPDMUX_CNT_ING_BCAST_BYTES = 0x7,
++	DPDMUX_CNT_EGR_FRAME = 0x8,
++	DPDMUX_CNT_EGR_BYTE = 0x9,
++	DPDMUX_CNT_EGR_FRAME_DISCARD = 0xa
++};
++
++/**
++ * enum dpdmux_accepted_frames_type - DPDMUX frame types
++ * @DPDMUX_ADMIT_ALL: The device accepts VLAN tagged, untagged and
++ *			priority-tagged frames
++ * @DPDMUX_ADMIT_ONLY_VLAN_TAGGED: The device discards untagged frames or
++ *				priority-tagged frames that are received on this
++ *				interface
++ * @DPDMUX_ADMIT_ONLY_UNTAGGED: Untagged frames or priority-tagged frames
++ *				received on this interface are accepted
++ */
++enum dpdmux_accepted_frames_type {
++	DPDMUX_ADMIT_ALL = 0,
++	DPDMUX_ADMIT_ONLY_VLAN_TAGGED = 1,
++	DPDMUX_ADMIT_ONLY_UNTAGGED = 2
++};
++
++/**
++ * enum dpdmux_action - DPDMUX action for un-accepted frames
++ * @DPDMUX_ACTION_DROP: Drop un-accepted frames
++ * @DPDMUX_ACTION_REDIRECT_TO_CTRL: Redirect un-accepted frames to the
++ *					control interface
++ */
++enum dpdmux_action {
++	DPDMUX_ACTION_DROP = 0,
++	DPDMUX_ACTION_REDIRECT_TO_CTRL = 1
++};
++
++/**
++ * struct dpdmux_accepted_frames - Frame types configuration
++ * @type: Defines ingress accepted frames
++ * @unaccept_act: Defines action on frames not accepted
++ */
++struct dpdmux_accepted_frames {
++	enum dpdmux_accepted_frames_type type;
++	enum dpdmux_action unaccept_act;
++};
++
++int dpdmux_if_set_accepted_frames(struct fsl_mc_io *mc_io,
++				  u32 cmd_flags,
++				  u16 token,
++				  u16 if_id,
++				  const struct dpdmux_accepted_frames *cfg);
++
++/**
++ * struct dpdmux_if_attr - Structure representing frame types configuration
++ * @rate: Configured interface rate (in bits per second)
++ * @enabled: Indicates if interface is enabled
++ * @accept_frame_type: Indicates type of accepted frames for the interface
++ */
++struct dpdmux_if_attr {
++	u32 rate;
++	int enabled;
++	enum dpdmux_accepted_frames_type accept_frame_type;
++};
++
++int dpdmux_if_get_attributes(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     u16 if_id,
++			     struct dpdmux_if_attr *attr);
++
++int dpdmux_if_enable(struct fsl_mc_io *mc_io,
++		     u32 cmd_flags,
++		     u16 token,
++		     u16 if_id);
++
++int dpdmux_if_disable(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      u16 if_id);
++
++/**
++ * struct dpdmux_l2_rule - Structure representing L2 rule
++ * @mac_addr: MAC address
++ * @vlan_id: VLAN ID
++ */
++struct dpdmux_l2_rule {
++	u8 mac_addr[6];
++	u16 vlan_id;
++};
++
++int dpdmux_if_remove_l2_rule(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     u16 if_id,
++			     const struct dpdmux_l2_rule *rule);
++
++int dpdmux_if_add_l2_rule(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u16 if_id,
++			  const struct dpdmux_l2_rule *rule);
++
++int dpdmux_if_get_counter(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u16 if_id,
++			  enum dpdmux_counter_type counter_type,
++			  u64 *counter);
++
++int dpdmux_ul_reset_counters(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token);
++
++/**
++ * Enable auto-negotiation
++ */
++#define DPDMUX_LINK_OPT_AUTONEG		0x0000000000000001ULL
++/**
++ * Enable half-duplex mode
++ */
++#define DPDMUX_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
++/**
++ * Enable pause frames
++ */
++#define DPDMUX_LINK_OPT_PAUSE		0x0000000000000004ULL
++/**
++ * Enable a-symmetric pause frames
++ */
++#define DPDMUX_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
++
++/**
++ * struct dpdmux_link_cfg - Structure representing DPDMUX link configuration
++ * @rate: Rate
++ * @options: Mask of available options; use 'DPDMUX_LINK_OPT_<X>' values
++ */
++struct dpdmux_link_cfg {
++	u32 rate;
++	u64 options;
++};
++
++int dpdmux_if_set_link_cfg(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u16 if_id,
++			   struct dpdmux_link_cfg *cfg);
++/**
++ * struct dpdmux_link_state - Structure representing DPDMUX link state
++ * @rate: Rate
++ * @options: Mask of available options; use 'DPDMUX_LINK_OPT_<X>' values
++ * @up: 0 - down, 1 - up
++ */
++struct dpdmux_link_state {
++	u32 rate;
++	u64 options;
++	int      up;
++};
++
++int dpdmux_if_get_link_state(struct fsl_mc_io *mc_io,
++			     u32 cmd_flags,
++			     u16 token,
++			     u16 if_id,
++			     struct dpdmux_link_state *state);
++
++int dpdmux_set_custom_key(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 token,
++			  u64 key_cfg_iova);
++
++/**
++ * struct dpdmux_rule_cfg - Custom classification rule.
++ *
++ * @key_iova: DMA address of buffer storing the look-up value
++ * @mask_iova: DMA address of the mask used for TCAM classification
++ * @key_size: size, in bytes, of the look-up value. This must match the size
++ *	of the look-up key defined using dpdmux_set_custom_key, otherwise the
++ *	entry will never be hit
++ */
++struct dpdmux_rule_cfg {
++	u64 key_iova;
++	u64 mask_iova;
++	u8 key_size;
++};
++
++/**
++ * struct dpdmux_cls_action - Action to execute for frames matching the
++ *	classification entry
++ *
++ * @dest_if: Interface to forward the frames to. Port numbering is similar to
++ *	the one used to connect interfaces:
++ *	- 0 is the uplink port,
++ *	- all others are downlink ports.
++ */
++struct dpdmux_cls_action {
++	u16 dest_if;
++};
++
++int dpdmux_add_custom_cls_entry(struct fsl_mc_io *mc_io,
++				u32 cmd_flags,
++				u16 token,
++				struct dpdmux_rule_cfg *rule,
++				struct dpdmux_cls_action *action);
++
++int dpdmux_remove_custom_cls_entry(struct fsl_mc_io *mc_io,
++				   u32 cmd_flags,
++				   u16 token,
++				   struct dpdmux_rule_cfg *rule);
++
++int dpdmux_get_api_version(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 *major_ver,
++			   u16 *minor_ver);
++
++#endif /* __FSL_DPDMUX_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/evb/evb.c
+@@ -0,0 +1,1354 @@
++/* Copyright 2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++#include <linux/module.h>
++#include <linux/msi.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/rtnetlink.h>
++#include <linux/if_vlan.h>
++
++#include <uapi/linux/if_bridge.h>
++#include <net/netlink.h>
++
++#include <linux/fsl/mc.h>
++
++#include "dpdmux.h"
++#include "dpdmux-cmd.h"
++
++static const char evb_drv_version[] = "0.1";
++
++/* Minimal supported DPDMUX version */
++#define DPDMUX_MIN_VER_MAJOR			6
++#define DPDMUX_MIN_VER_MINOR			0
++
++/* IRQ index */
++#define DPDMUX_MAX_IRQ_NUM			2
++
++/* MAX FRAME LENGTH (currently 10k) */
++#define EVB_MAX_FRAME_LENGTH		(10 * 1024)
++#define EVB_MAX_MTU			(EVB_MAX_FRAME_LENGTH - VLAN_ETH_HLEN)
++#define EVB_MIN_MTU			68
++
++struct evb_port_priv {
++	struct net_device	*netdev;
++	struct list_head	list;
++	u16			port_index;
++	struct evb_priv		*evb_priv;
++	u8			vlans[VLAN_VID_MASK + 1];
++};
++
++struct evb_priv {
++	/* keep first */
++	struct evb_port_priv	uplink;
++
++	struct fsl_mc_io	*mc_io;
++	struct list_head	port_list;
++	struct dpdmux_attr	attr;
++	u16			mux_handle;
++	int			dev_id;
++};
++
++static int _evb_port_carrier_state_sync(struct net_device *netdev)
++{
++	struct evb_port_priv		*port_priv = netdev_priv(netdev);
++	struct dpdmux_link_state	state;
++	int err;
++
++	err = dpdmux_if_get_link_state(port_priv->evb_priv->mc_io, 0,
++				       port_priv->evb_priv->mux_handle,
++				       port_priv->port_index, &state);
++	if (unlikely(err)) {
++		netdev_err(netdev, "dpdmux_if_get_link_state() err %d\n", err);
++		return err;
++	}
++
++	WARN_ONCE(state.up > 1, "Garbage read into link_state");
++
++	if (state.up)
++		netif_carrier_on(port_priv->netdev);
++	else
++		netif_carrier_off(port_priv->netdev);
++
++	return 0;
++}
++
++static int evb_port_open(struct net_device *netdev)
++{
++	int			err;
++
++	/* FIXME: enable port when support added */
++
++	err = _evb_port_carrier_state_sync(netdev);
++	if (err) {
++		netdev_err(netdev, "ethsw_port_carrier_state_sync err %d\n",
++			   err);
++		return err;
++	}
++
++	return 0;
++}
++
++static netdev_tx_t evb_dropframe(struct sk_buff *skb, struct net_device *dev)
++{
++	/* we don't support I/O for now, drop the frame */
++	dev_kfree_skb_any(skb);
++	return NETDEV_TX_OK;
++}
++
++static int evb_links_state_update(struct evb_priv *priv)
++{
++	struct evb_port_priv	*port_priv;
++	struct list_head	*pos;
++	int err;
++
++	list_for_each(pos, &priv->port_list) {
++		port_priv = list_entry(pos, struct evb_port_priv, list);
++
++		err = _evb_port_carrier_state_sync(port_priv->netdev);
++		if (err)
++			netdev_err(port_priv->netdev,
++				   "_evb_port_carrier_state_sync err %d\n",
++				   err);
++	}
++
++	return 0;
++}
++
++static irqreturn_t evb_irq0_handler(int irq_num, void *arg)
++{
++	return IRQ_WAKE_THREAD;
++}
++
++static irqreturn_t _evb_irq0_handler_thread(int irq_num, void *arg)
++{
++	struct device		*dev = (struct device *)arg;
++	struct fsl_mc_device	*evb_dev = to_fsl_mc_device(dev);
++	struct net_device	*netdev = dev_get_drvdata(dev);
++	struct evb_priv		*priv = netdev_priv(netdev);
++	struct fsl_mc_io	*io = priv->mc_io;
++	u16 token = priv->mux_handle;
++	int irq_index = DPDMUX_IRQ_INDEX_IF;
++
++	/* Mask the events and the if_id reserved bits to be cleared on read */
++	u32 status = DPDMUX_IRQ_EVENT_LINK_CHANGED | 0xFFFF0000;
++	int err;
++
++	/* Sanity check */
++	if (WARN_ON(!evb_dev || !evb_dev->irqs || !evb_dev->irqs[irq_index]))
++		goto out;
++	if (WARN_ON(evb_dev->irqs[irq_index]->msi_desc->irq != (u32)irq_num))
++		goto out;
++
++	err = dpdmux_get_irq_status(io, 0, token, irq_index, &status);
++	if (unlikely(err)) {
++		netdev_err(netdev, "Can't get irq status (err %d)", err);
++		err = dpdmux_clear_irq_status(io, 0, token, irq_index,
++					      0xFFFFFFFF);
++		if (unlikely(err))
++			netdev_err(netdev, "Can't clear irq status (err %d)",
++				   err);
++		goto out;
++	}
++
++	if (status & DPDMUX_IRQ_EVENT_LINK_CHANGED) {
++		err = evb_links_state_update(priv);
++		if (unlikely(err))
++			goto out;
++	}
++
++out:
++	return IRQ_HANDLED;
++}
++
++static int evb_setup_irqs(struct fsl_mc_device *evb_dev)
++{
++	struct device		*dev = &evb_dev->dev;
++	struct net_device	*netdev = dev_get_drvdata(dev);
++	struct evb_priv		*priv = netdev_priv(netdev);
++	int err = 0;
++	struct fsl_mc_device_irq *irq;
++	const int irq_index = DPDMUX_IRQ_INDEX_IF;
++	u32 mask = DPDMUX_IRQ_EVENT_LINK_CHANGED;
++
++	err = fsl_mc_allocate_irqs(evb_dev);
++	if (unlikely(err)) {
++		dev_err(dev, "MC irqs allocation failed\n");
++		return err;
++	}
++
++	if (WARN_ON(evb_dev->obj_desc.irq_count != DPDMUX_MAX_IRQ_NUM)) {
++		err = -EINVAL;
++		goto free_irq;
++	}
++
++	err = dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle,
++				    irq_index, 0);
++	if (unlikely(err)) {
++		dev_err(dev, "dpdmux_set_irq_enable err %d\n", err);
++		goto free_irq;
++	}
++
++	irq = evb_dev->irqs[irq_index];
++
++	err = devm_request_threaded_irq(dev, irq->msi_desc->irq,
++					evb_irq0_handler,
++					_evb_irq0_handler_thread,
++					IRQF_NO_SUSPEND | IRQF_ONESHOT,
++					dev_name(dev), dev);
++	if (unlikely(err)) {
++		dev_err(dev, "devm_request_threaded_irq(): %d", err);
++		goto free_irq;
++	}
++
++	err = dpdmux_set_irq_mask(priv->mc_io, 0, priv->mux_handle,
++				  irq_index, mask);
++	if (unlikely(err)) {
++		dev_err(dev, "dpdmux_set_irq_mask(): %d", err);
++		goto free_devm_irq;
++	}
++
++	err = dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle,
++				    irq_index, 1);
++	if (unlikely(err)) {
++		dev_err(dev, "dpdmux_set_irq_enable(): %d", err);
++		goto free_devm_irq;
++	}
++
++	return 0;
++
++free_devm_irq:
++	devm_free_irq(dev, irq->msi_desc->irq, dev);
++free_irq:
++	fsl_mc_free_irqs(evb_dev);
++	return err;
++}
++
++static void evb_teardown_irqs(struct fsl_mc_device *evb_dev)
++{
++	struct device		*dev = &evb_dev->dev;
++	struct net_device	*netdev = dev_get_drvdata(dev);
++	struct evb_priv		*priv = netdev_priv(netdev);
++
++	dpdmux_set_irq_enable(priv->mc_io, 0, priv->mux_handle,
++			      DPDMUX_IRQ_INDEX_IF, 0);
++
++	devm_free_irq(dev,
++		      evb_dev->irqs[DPDMUX_IRQ_INDEX_IF]->msi_desc->irq,
++		      dev);
++	fsl_mc_free_irqs(evb_dev);
++}
++
++static int evb_port_add_rule(struct net_device *netdev,
++			     const unsigned char *addr, u16 vid)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	struct dpdmux_l2_rule	rule = { .vlan_id = vid };
++	int			err;
++
++	if (addr)
++		ether_addr_copy(rule.mac_addr, addr);
++
++	err = dpdmux_if_add_l2_rule(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index, &rule);
++	if (unlikely(err))
++		netdev_err(netdev, "dpdmux_if_add_l2_rule err %d\n", err);
++	return err;
++}
++
++static int evb_port_del_rule(struct net_device *netdev,
++			     const unsigned char *addr, u16 vid)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	struct dpdmux_l2_rule	rule = { .vlan_id = vid };
++	int err;
++
++	if (addr)
++		ether_addr_copy(rule.mac_addr, addr);
++
++	err = dpdmux_if_remove_l2_rule(port_priv->evb_priv->mc_io,
++				       0,
++				       port_priv->evb_priv->mux_handle,
++				       port_priv->port_index, &rule);
++	if (unlikely(err))
++		netdev_err(netdev, "dpdmux_if_remove_l2_rule err %d\n", err);
++	return err;
++}
++
++static bool _lookup_address(struct net_device *netdev,
++			    const unsigned char *addr)
++{
++	struct netdev_hw_addr	   *ha;
++	struct netdev_hw_addr_list *list = (is_unicast_ether_addr(addr)) ?
++					   &netdev->uc : &netdev->mc;
++
++	netif_addr_lock_bh(netdev);
++	list_for_each_entry(ha, &list->list, list) {
++		if (ether_addr_equal(ha->addr, addr)) {
++			netif_addr_unlock_bh(netdev);
++			return true;
++		}
++	}
++	netif_addr_unlock_bh(netdev);
++	return false;
++}
++
++static inline int evb_port_fdb_prep(struct nlattr *tb[],
++				    struct net_device *netdev,
++				    const unsigned char *addr, u16 *vid,
++				    bool del)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	struct evb_priv		*evb_priv = port_priv->evb_priv;
++
++	*vid = 0;
++
++	if (evb_priv->attr.method != DPDMUX_METHOD_MAC &&
++	    evb_priv->attr.method != DPDMUX_METHOD_C_VLAN_MAC) {
++		netdev_err(netdev,
++			   "EVB mode does not support MAC classification\n");
++		return -EOPNOTSUPP;
++	}
++
++	/* check if the address is configured on this port */
++	if (_lookup_address(netdev, addr)) {
++		if (!del)
++			return -EEXIST;
++	} else {
++		if (del)
++			return -ENOENT;
++	}
++
++	if (tb[NDA_VLAN] && evb_priv->attr.method == DPDMUX_METHOD_C_VLAN_MAC) {
++		if (nla_len(tb[NDA_VLAN]) != sizeof(unsigned short)) {
++			netdev_err(netdev, "invalid vlan size %d\n",
++				   nla_len(tb[NDA_VLAN]));
++			return -EINVAL;
++		}
++
++		*vid = nla_get_u16(tb[NDA_VLAN]);
++
++		if (!*vid || *vid >= VLAN_VID_MASK) {
++			netdev_err(netdev, "invalid vid value 0x%04x\n", *vid);
++			return -EINVAL;
++		}
++	} else if (evb_priv->attr.method == DPDMUX_METHOD_C_VLAN_MAC) {
++		netdev_err(netdev,
++			   "EVB mode requires explicit VLAN configuration\n");
++		return -EINVAL;
++	} else if (tb[NDA_VLAN]) {
++		netdev_warn(netdev, "VLAN not supported, argument ignored\n");
++	}
++
++	return 0;
++}
++
++static int evb_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
++			    struct net_device *netdev,
++			    const unsigned char *addr, u16 vid, u16 flags)
++{
++	u16 _vid;
++	int err;
++
++	/* TODO: add replace support when added to iproute bridge */
++	if (!(flags & NLM_F_REQUEST)) {
++		netdev_err(netdev,
++			   "evb_port_fdb_add unexpected flags value %08x\n",
++			   flags);
++		return -EINVAL;
++	}
++
++	err = evb_port_fdb_prep(tb, netdev, addr, &_vid, 0);
++	if (unlikely(err))
++		return err;
++
++	err = evb_port_add_rule(netdev, addr, _vid);
++	if (unlikely(err))
++		return err;
++
++	if (is_unicast_ether_addr(addr)) {
++		err = dev_uc_add(netdev, addr);
++		if (unlikely(err)) {
++			netdev_err(netdev, "dev_uc_add err %d\n", err);
++			return err;
++		}
++	} else {
++		err = dev_mc_add(netdev, addr);
++		if (unlikely(err)) {
++			netdev_err(netdev, "dev_mc_add err %d\n", err);
++			return err;
++		}
++	}
++
++	return 0;
++}
++
++static int evb_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
++			    struct net_device *netdev,
++			    const unsigned char *addr, u16 vid)
++{
++	u16 _vid;
++	int err;
++
++	err = evb_port_fdb_prep(tb, netdev, addr, &_vid, 1);
++	if (unlikely(err))
++		return err;
++
++	err = evb_port_del_rule(netdev, addr, _vid);
++	if (unlikely(err))
++		return err;
++
++	if (is_unicast_ether_addr(addr)) {
++		err = dev_uc_del(netdev, addr);
++		if (unlikely(err)) {
++			netdev_err(netdev, "dev_uc_del err %d\n", err);
++			return err;
++		}
++	} else {
++		err = dev_mc_del(netdev, addr);
++		if (unlikely(err)) {
++			netdev_err(netdev, "dev_mc_del err %d\n", err);
++			return err;
++		}
++	}
++
++	return 0;
++}
++
++static int evb_change_mtu(struct net_device *netdev,
++			  int mtu)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	struct evb_priv		*evb_priv = port_priv->evb_priv;
++	struct list_head	*pos;
++	int			err = 0;
++
++	/* This operation is not permitted on downlinks */
++	if (port_priv->port_index > 0)
++		return -EPERM;
++
++	err = dpdmux_set_max_frame_length(evb_priv->mc_io,
++					  0,
++					  evb_priv->mux_handle,
++					  (uint16_t)(mtu + VLAN_ETH_HLEN));
++
++	if (unlikely(err)) {
++		netdev_err(netdev, "dpdmux_ul_set_max_frame_length err %d\n",
++			   err);
++		return err;
++	}
++
++	/* Update the max frame length for downlinks */
++	list_for_each(pos, &evb_priv->port_list) {
++		port_priv = list_entry(pos, struct evb_port_priv, list);
++		port_priv->netdev->mtu = mtu;
++	}
++
++	netdev->mtu = mtu;
++	return 0;
++}
++
++static const struct nla_policy ifla_br_policy[IFLA_MAX + 1] = {
++	[IFLA_BRIDGE_FLAGS]	= { .type = NLA_U16 },
++	[IFLA_BRIDGE_MODE]	= { .type = NLA_U16 },
++	[IFLA_BRIDGE_VLAN_INFO]	= { .type = NLA_BINARY,
++				.len = sizeof(struct bridge_vlan_info), },
++};
++
++static int evb_setlink_af_spec(struct net_device *netdev,
++			       struct nlattr **tb)
++{
++	struct bridge_vlan_info	*vinfo;
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	int			err = 0;
++
++	if (!tb[IFLA_BRIDGE_VLAN_INFO]) {
++		netdev_err(netdev, "no VLAN INFO in nlmsg\n");
++		return -EOPNOTSUPP;
++	}
++
++	vinfo = nla_data(tb[IFLA_BRIDGE_VLAN_INFO]);
++
++	if (!vinfo->vid || vinfo->vid > VLAN_VID_MASK)
++		return -EINVAL;
++
++	err = evb_port_add_rule(netdev, NULL, vinfo->vid);
++	if (unlikely(err))
++		return err;
++
++	port_priv->vlans[vinfo->vid] = 1;
++
++	return 0;
++}
++
++static int evb_setlink(struct net_device *netdev,
++		       struct nlmsghdr *nlh,
++		       u16 flags)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	struct evb_priv		*evb_priv = port_priv->evb_priv;
++	struct nlattr		*attr;
++	struct nlattr		*tb[(IFLA_BRIDGE_MAX > IFLA_BRPORT_MAX) ?
++					IFLA_BRIDGE_MAX : IFLA_BRPORT_MAX + 1];
++	int			err = 0;
++
++	if (evb_priv->attr.method != DPDMUX_METHOD_C_VLAN &&
++	    evb_priv->attr.method != DPDMUX_METHOD_S_VLAN) {
++		netdev_err(netdev,
++			   "EVB mode does not support VLAN only classification\n");
++		return -EOPNOTSUPP;
++	}
++
++	attr = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
++	if (attr) {
++		err = nla_parse_nested(tb, IFLA_BRIDGE_MAX, attr,
++				       ifla_br_policy);
++		if (unlikely(err)) {
++			netdev_err(netdev,
++				   "nla_parse_nested for br_policy err %d\n",
++				   err);
++			return err;
++		}
++
++		err = evb_setlink_af_spec(netdev, tb);
++		return err;
++	}
++
++	netdev_err(netdev, "nlmsg_find_attr found no AF_SPEC\n");
++	return -EOPNOTSUPP;
++}
++
++static int __nla_put_netdev(struct sk_buff *skb, struct net_device *netdev)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	struct evb_priv		*evb_priv = port_priv->evb_priv;
++	u8			operstate = netif_running(netdev) ?
++				netdev->operstate : IF_OPER_DOWN;
++	int			iflink;
++	int			err;
++
++	err = nla_put_string(skb, IFLA_IFNAME, netdev->name);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u32(skb, IFLA_MASTER, evb_priv->uplink.netdev->ifindex);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u32(skb, IFLA_MTU, netdev->mtu);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u8(skb, IFLA_OPERSTATE, operstate);
++	if (unlikely(err))
++		goto nla_put_err;
++	if (netdev->addr_len) {
++		err = nla_put(skb, IFLA_ADDRESS, netdev->addr_len,
++			      netdev->dev_addr);
++		if (unlikely(err))
++			goto nla_put_err;
++	}
++
++	iflink = dev_get_iflink(netdev);
++	if (netdev->ifindex != iflink) {
++		err = nla_put_u32(skb, IFLA_LINK, iflink);
++		if (unlikely(err))
++			goto nla_put_err;
++	}
++
++	return 0;
++
++nla_put_err:
++	netdev_err(netdev, "nla_put_ err %d\n", err);
++	return err;
++}
++
++static int __nla_put_port(struct sk_buff *skb, struct net_device *netdev)
++{
++	struct nlattr	*nest;
++	int		err;
++
++	nest = nla_nest_start(skb, IFLA_PROTINFO | NLA_F_NESTED);
++	if (!nest) {
++		netdev_err(netdev, "nla_nest_start failed\n");
++		return -ENOMEM;
++	}
++
++	err = nla_put_u8(skb, IFLA_BRPORT_STATE, BR_STATE_FORWARDING);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u16(skb, IFLA_BRPORT_PRIORITY, 0);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u32(skb, IFLA_BRPORT_COST, 0);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u8(skb, IFLA_BRPORT_MODE, 0);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u8(skb, IFLA_BRPORT_GUARD, 0);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u8(skb, IFLA_BRPORT_PROTECT, 0);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u8(skb, IFLA_BRPORT_FAST_LEAVE, 0);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u8(skb, IFLA_BRPORT_LEARNING, 0);
++	if (unlikely(err))
++		goto nla_put_err;
++	err = nla_put_u8(skb, IFLA_BRPORT_UNICAST_FLOOD, 1);
++	if (unlikely(err))
++		goto nla_put_err;
++	nla_nest_end(skb, nest);
++
++	return 0;
++
++nla_put_err:
++	netdev_err(netdev, "nla_put_ err %d\n", err);
++	nla_nest_cancel(skb, nest);
++	return err;
++}
++
++static int __nla_put_vlan(struct sk_buff *skb,  struct net_device *netdev)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	struct nlattr		*nest;
++	struct bridge_vlan_info	vinfo;
++	const u8		*vlans = port_priv->vlans;
++	u16			i;
++	int			err;
++
++	nest = nla_nest_start(skb, IFLA_AF_SPEC);
++	if (!nest) {
++		netdev_err(netdev, "nla_nest_start failed");
++		return -ENOMEM;
++	}
++
++	for (i = 0; i < VLAN_VID_MASK + 1; i++) {
++		if (!vlans[i])
++			continue;
++
++		vinfo.flags = 0;
++		vinfo.vid = i;
++
++		err = nla_put(skb, IFLA_BRIDGE_VLAN_INFO,
++			      sizeof(vinfo), &vinfo);
++		if (unlikely(err))
++			goto nla_put_err;
++	}
++
++	nla_nest_end(skb, nest);
++
++	return 0;
++
++nla_put_err:
++	netdev_err(netdev, "nla_put_ err %d\n", err);
++	nla_nest_cancel(skb, nest);
++	return err;
++}
++
++static int evb_getlink(struct sk_buff *skb, u32 pid, u32 seq,
++		       struct net_device *netdev, u32 filter_mask, int nlflags)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	struct evb_priv		*evb_priv = port_priv->evb_priv;
++	struct ifinfomsg	*hdr;
++	struct nlmsghdr		*nlh;
++	int			err;
++
++	if (evb_priv->attr.method != DPDMUX_METHOD_C_VLAN &&
++	    evb_priv->attr.method != DPDMUX_METHOD_S_VLAN) {
++		return 0;
++	}
++
++	nlh = nlmsg_put(skb, pid, seq, RTM_NEWLINK, sizeof(*hdr), NLM_F_MULTI);
++	if (!nlh)
++		return -EMSGSIZE;
++
++	hdr = nlmsg_data(nlh);
++	memset(hdr, 0, sizeof(*hdr));
++	hdr->ifi_family = AF_BRIDGE;
++	hdr->ifi_type = netdev->type;
++	hdr->ifi_index = netdev->ifindex;
++	hdr->ifi_flags = dev_get_flags(netdev);
++
++	err = __nla_put_netdev(skb, netdev);
++	if (unlikely(err))
++		goto nla_put_err;
++
++	err = __nla_put_port(skb, netdev);
++	if (unlikely(err))
++		goto nla_put_err;
++
++	/* Check if the VID information is requested */
++	if (filter_mask & RTEXT_FILTER_BRVLAN) {
++		err = __nla_put_vlan(skb, netdev);
++		if (unlikely(err))
++			goto nla_put_err;
++	}
++
++	nlmsg_end(skb, nlh);
++	return skb->len;
++
++nla_put_err:
++	nlmsg_cancel(skb, nlh);
++	return -EMSGSIZE;
++}
++
++static int evb_dellink(struct net_device *netdev,
++		       struct nlmsghdr *nlh,
++		       u16 flags)
++{
++	struct nlattr		*tb[IFLA_BRIDGE_MAX + 1];
++	struct nlattr		*spec;
++	struct bridge_vlan_info	*vinfo;
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	int			err = 0;
++
++	spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
++	if (!spec)
++		return 0;
++
++	err = nla_parse_nested(tb, IFLA_BRIDGE_MAX, spec, ifla_br_policy);
++	if (unlikely(err))
++		return err;
++
++	if (!tb[IFLA_BRIDGE_VLAN_INFO])
++		return -EOPNOTSUPP;
++
++	vinfo = nla_data(tb[IFLA_BRIDGE_VLAN_INFO]);
++
++	if (!vinfo->vid || vinfo->vid > VLAN_VID_MASK)
++		return -EINVAL;
++
++	err = evb_port_del_rule(netdev, NULL, vinfo->vid);
++	if (unlikely(err)) {
++		netdev_err(netdev, "evb_port_del_rule err %d\n", err);
++		return err;
++	}
++	port_priv->vlans[vinfo->vid] = 0;
++
++	return 0;
++}
++
++struct rtnl_link_stats64 *evb_port_get_stats(struct net_device *netdev,
++			struct rtnl_link_stats64 *storage)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	u64			tmp;
++	int			err;
++
++	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index,
++				    DPDMUX_CNT_ING_FRAME, &storage->rx_packets);
++	if (unlikely(err))
++		goto error;
++
++	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index,
++				    DPDMUX_CNT_ING_BYTE, &storage->rx_bytes);
++	if (unlikely(err))
++		goto error;
++
++	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index,
++				    DPDMUX_CNT_ING_FLTR_FRAME, &tmp);
++	if (unlikely(err))
++		goto error;
++
++	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index,
++				    DPDMUX_CNT_ING_FRAME_DISCARD,
++				    &storage->rx_dropped);
++	if (unlikely(err)) {
++		storage->rx_dropped = tmp;
++		goto error;
++	}
++	storage->rx_dropped += tmp;
++
++	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index,
++				    DPDMUX_CNT_ING_MCAST_FRAME,
++				    &storage->multicast);
++	if (unlikely(err))
++		goto error;
++
++	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index,
++				    DPDMUX_CNT_EGR_FRAME, &storage->tx_packets);
++	if (unlikely(err))
++		goto error;
++
++	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index,
++				    DPDMUX_CNT_EGR_BYTE, &storage->tx_bytes);
++	if (unlikely(err))
++		goto error;
++
++	err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++				    0,
++				    port_priv->evb_priv->mux_handle,
++				    port_priv->port_index,
++				    DPDMUX_CNT_EGR_FRAME_DISCARD,
++				    &storage->tx_dropped);
++	if (unlikely(err))
++		goto error;
++
++	return storage;
++
++error:
++	netdev_err(netdev, "dpdmux_if_get_counter err %d\n", err);
++	return storage;
++}
++
++static const struct net_device_ops evb_port_ops = {
++	.ndo_open		= &evb_port_open,
++
++	.ndo_start_xmit		= &evb_dropframe,
++
++	.ndo_fdb_add		= &evb_port_fdb_add,
++	.ndo_fdb_del		= &evb_port_fdb_del,
++
++	.ndo_get_stats64	= &evb_port_get_stats,
++	.ndo_change_mtu		= &evb_change_mtu,
++};
++
++static void evb_get_drvinfo(struct net_device *netdev,
++			    struct ethtool_drvinfo *drvinfo)
++{
++	struct evb_port_priv *port_priv = netdev_priv(netdev);
++	u16 version_major, version_minor;
++	int err;
++
++	strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
++	strlcpy(drvinfo->version, evb_drv_version, sizeof(drvinfo->version));
++
++	err = dpdmux_get_api_version(port_priv->evb_priv->mc_io, 0,
++				     &version_major,
++				     &version_minor);
++	if (err)
++		strlcpy(drvinfo->fw_version, "N/A",
++			sizeof(drvinfo->fw_version));
++	else
++		snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
++			 "%u.%u", version_major, version_minor);
++
++	strlcpy(drvinfo->bus_info, dev_name(netdev->dev.parent->parent),
++		sizeof(drvinfo->bus_info));
++}
++
++static int evb_get_settings(struct net_device *netdev,
++			    struct ethtool_cmd *cmd)
++{
++	struct evb_port_priv *port_priv = netdev_priv(netdev);
++	struct dpdmux_link_state state = {0};
++	int err = 0;
++
++	err = dpdmux_if_get_link_state(port_priv->evb_priv->mc_io, 0,
++				       port_priv->evb_priv->mux_handle,
++				       port_priv->port_index,
++				       &state);
++	if (err) {
++		netdev_err(netdev, "ERROR %d getting link state", err);
++		goto out;
++	}
++
++	/* At the moment, we have no way of interrogating the DPMAC
++	 * from the DPDMUX side or there may not exist a DPMAC at all.
++	 * Report only autoneg state, duplexity and speed.
++	 */
++	if (state.options & DPDMUX_LINK_OPT_AUTONEG)
++		cmd->autoneg = AUTONEG_ENABLE;
++	if (!(state.options & DPDMUX_LINK_OPT_HALF_DUPLEX))
++		cmd->duplex = DUPLEX_FULL;
++	ethtool_cmd_speed_set(cmd, state.rate);
++
++out:
++	return err;
++}
++
++static int evb_set_settings(struct net_device *netdev,
++			    struct ethtool_cmd *cmd)
++{
++	struct evb_port_priv *port_priv = netdev_priv(netdev);
++	struct dpdmux_link_state state = {0};
++	struct dpdmux_link_cfg cfg = {0};
++	int err = 0;
++
++	netdev_dbg(netdev, "Setting link parameters...");
++
++	err = dpdmux_if_get_link_state(port_priv->evb_priv->mc_io, 0,
++				       port_priv->evb_priv->mux_handle,
++				       port_priv->port_index,
++				       &state);
++	if (err) {
++		netdev_err(netdev, "ERROR %d getting link state", err);
++		goto out;
++	}
++
++	/* Due to a temporary MC limitation, the DPDMUX port must be down
++	 * in order to be able to change link settings. Taking steps to let
++	 * the user know that.
++	 */
++	if (netif_running(netdev)) {
++		netdev_info(netdev,
++			    "Sorry, interface must be brought down first.\n");
++		return -EACCES;
++	}
++
++	cfg.options = state.options;
++	cfg.rate = ethtool_cmd_speed(cmd);
++	if (cmd->autoneg == AUTONEG_ENABLE)
++		cfg.options |= DPDMUX_LINK_OPT_AUTONEG;
++	else
++		cfg.options &= ~DPDMUX_LINK_OPT_AUTONEG;
++	if (cmd->duplex == DUPLEX_HALF)
++		cfg.options |= DPDMUX_LINK_OPT_HALF_DUPLEX;
++	else
++		cfg.options &= ~DPDMUX_LINK_OPT_HALF_DUPLEX;
++
++	err = dpdmux_if_set_link_cfg(port_priv->evb_priv->mc_io, 0,
++				     port_priv->evb_priv->mux_handle,
++				     port_priv->port_index,
++				     &cfg);
++	if (err)
++		/* ethtool will be loud enough if we return an error; no point
++		 * in putting our own error message on the console by default
++		 */
++		netdev_dbg(netdev, "ERROR %d setting link cfg", err);
++
++out:
++	return err;
++}
++
++static struct {
++	enum dpdmux_counter_type id;
++	char name[ETH_GSTRING_LEN];
++} evb_ethtool_counters[] =  {
++	{DPDMUX_CNT_ING_FRAME,		"rx frames"},
++	{DPDMUX_CNT_ING_BYTE,		"rx bytes"},
++	{DPDMUX_CNT_ING_FLTR_FRAME,	"rx filtered frames"},
++	{DPDMUX_CNT_ING_FRAME_DISCARD,	"rx discarded frames"},
++	{DPDMUX_CNT_ING_BCAST_FRAME,	"rx b-cast frames"},
++	{DPDMUX_CNT_ING_BCAST_BYTES,	"rx b-cast bytes"},
++	{DPDMUX_CNT_ING_MCAST_FRAME,	"rx m-cast frames"},
++	{DPDMUX_CNT_ING_MCAST_BYTE,	"rx m-cast bytes"},
++	{DPDMUX_CNT_EGR_FRAME,		"tx frames"},
++	{DPDMUX_CNT_EGR_BYTE,		"tx bytes"},
++	{DPDMUX_CNT_EGR_FRAME_DISCARD,	"tx discarded frames"},
++};
++
++static int evb_ethtool_get_sset_count(struct net_device *dev, int sset)
++{
++	switch (sset) {
++	case ETH_SS_STATS:
++		return ARRAY_SIZE(evb_ethtool_counters);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static void evb_ethtool_get_strings(struct net_device *netdev,
++				    u32 stringset, u8 *data)
++{
++	u32 i;
++
++	switch (stringset) {
++	case ETH_SS_STATS:
++		for (i = 0; i < ARRAY_SIZE(evb_ethtool_counters); i++)
++			memcpy(data + i * ETH_GSTRING_LEN,
++			       evb_ethtool_counters[i].name, ETH_GSTRING_LEN);
++		break;
++	}
++}
++
++static void evb_ethtool_get_stats(struct net_device *netdev,
++				  struct ethtool_stats *stats,
++				  u64 *data)
++{
++	struct evb_port_priv	*port_priv = netdev_priv(netdev);
++	u32			i;
++	int			err;
++
++	for (i = 0; i < ARRAY_SIZE(evb_ethtool_counters); i++) {
++		err = dpdmux_if_get_counter(port_priv->evb_priv->mc_io,
++					    0,
++					    port_priv->evb_priv->mux_handle,
++					    port_priv->port_index,
++					    evb_ethtool_counters[i].id,
++					    &data[i]);
++		if (err)
++			netdev_err(netdev, "dpdmux_if_get_counter[%s] err %d\n",
++				   evb_ethtool_counters[i].name, err);
++	}
++}
++
++static const struct ethtool_ops evb_port_ethtool_ops = {
++	.get_drvinfo		= &evb_get_drvinfo,
++	.get_link		= &ethtool_op_get_link,
++	.get_settings		= &evb_get_settings,
++	.set_settings		= &evb_set_settings,
++	.get_strings		= &evb_ethtool_get_strings,
++	.get_ethtool_stats	= &evb_ethtool_get_stats,
++	.get_sset_count		= &evb_ethtool_get_sset_count,
++};
++
++static int evb_open(struct net_device *netdev)
++{
++	struct evb_priv	*priv = netdev_priv(netdev);
++	int		err = 0;
++
++	err = dpdmux_enable(priv->mc_io, 0, priv->mux_handle);
++	if (unlikely(err))
++		netdev_err(netdev, "dpdmux_enable err %d\n", err);
++
++	return err;
++}
++
++static int evb_close(struct net_device *netdev)
++{
++	struct evb_priv	*priv = netdev_priv(netdev);
++	int		err = 0;
++
++	err = dpdmux_disable(priv->mc_io, 0, priv->mux_handle);
++	if (unlikely(err))
++		netdev_err(netdev, "dpdmux_disable err %d\n", err);
++
++	return err;
++}
++
++static const struct net_device_ops evb_ops = {
++	.ndo_start_xmit		= &evb_dropframe,
++	.ndo_open		= &evb_open,
++	.ndo_stop		= &evb_close,
++
++	.ndo_bridge_setlink	= &evb_setlink,
++	.ndo_bridge_getlink	= &evb_getlink,
++	.ndo_bridge_dellink	= &evb_dellink,
++
++	.ndo_get_stats64	= &evb_port_get_stats,
++	.ndo_change_mtu		= &evb_change_mtu,
++};
++
++static int evb_takedown(struct fsl_mc_device *evb_dev)
++{
++	struct device		*dev = &evb_dev->dev;
++	struct net_device	*netdev = dev_get_drvdata(dev);
++	struct evb_priv		*priv = netdev_priv(netdev);
++	int			err;
++
++	err = dpdmux_close(priv->mc_io, 0, priv->mux_handle);
++	if (unlikely(err))
++		dev_warn(dev, "dpdmux_close err %d\n", err);
++
++	return 0;
++}
++
++static int evb_init(struct fsl_mc_device *evb_dev)
++{
++	struct device		*dev = &evb_dev->dev;
++	struct net_device	*netdev = dev_get_drvdata(dev);
++	struct evb_priv		*priv = netdev_priv(netdev);
++	u16			version_major;
++	u16			version_minor;
++	int			err = 0;
++
++	priv->dev_id = evb_dev->obj_desc.id;
++
++	err = dpdmux_open(priv->mc_io, 0, priv->dev_id, &priv->mux_handle);
++	if (unlikely(err)) {
++		dev_err(dev, "dpdmux_open err %d\n", err);
++		goto err_exit;
++	}
++	if (!priv->mux_handle) {
++		dev_err(dev, "dpdmux_open returned null handle but no error\n");
++		err = -EFAULT;
++		goto err_exit;
++	}
++
++	err = dpdmux_get_attributes(priv->mc_io, 0, priv->mux_handle,
++				    &priv->attr);
++	if (unlikely(err)) {
++		dev_err(dev, "dpdmux_get_attributes err %d\n", err);
++		goto err_close;
++	}
++
++	err = dpdmux_get_api_version(priv->mc_io, 0,
++				     &version_major,
++				     &version_minor);
++	if (unlikely(err)) {
++		dev_err(dev, "dpdmux_get_api_version err %d\n", err);
++		goto err_close;
++	}
++
++	/* Minimum supported DPDMUX version check */
++	if (version_major < DPDMUX_MIN_VER_MAJOR ||
++	    (version_major == DPDMUX_MIN_VER_MAJOR &&
++	     version_minor < DPDMUX_MIN_VER_MINOR)) {
++		dev_err(dev, "DPDMUX version %d.%d not supported. Use %d.%d or greater.\n",
++			version_major, version_minor,
++			DPDMUX_MIN_VER_MAJOR, DPDMUX_MIN_VER_MAJOR);
++		err = -ENOTSUPP;
++		goto err_close;
++	}
++
++	err = dpdmux_reset(priv->mc_io, 0, priv->mux_handle);
++	if (unlikely(err)) {
++		dev_err(dev, "dpdmux_reset err %d\n", err);
++		goto err_close;
++	}
++
++	return 0;
++
++err_close:
++	dpdmux_close(priv->mc_io, 0, priv->mux_handle);
++err_exit:
++	return err;
++}
++
++static int evb_remove(struct fsl_mc_device *evb_dev)
++{
++	struct device		*dev = &evb_dev->dev;
++	struct net_device	*netdev = dev_get_drvdata(dev);
++	struct evb_priv		*priv = netdev_priv(netdev);
++	struct evb_port_priv	*port_priv;
++	struct list_head	*pos;
++
++	list_for_each(pos, &priv->port_list) {
++		port_priv = list_entry(pos, struct evb_port_priv, list);
++
++		rtnl_lock();
++		netdev_upper_dev_unlink(port_priv->netdev, netdev);
++		rtnl_unlock();
++
++		unregister_netdev(port_priv->netdev);
++		free_netdev(port_priv->netdev);
++	}
++
++	evb_teardown_irqs(evb_dev);
++
++	unregister_netdev(netdev);
++
++	evb_takedown(evb_dev);
++	fsl_mc_portal_free(priv->mc_io);
++
++	dev_set_drvdata(dev, NULL);
++	free_netdev(netdev);
++
++	return 0;
++}
++
++static int evb_probe(struct fsl_mc_device *evb_dev)
++{
++	struct device		*dev;
++	struct evb_priv		*priv = NULL;
++	struct net_device	*netdev = NULL;
++	char			port_name[IFNAMSIZ];
++	int			i;
++	int			err = 0;
++
++	dev = &evb_dev->dev;
++
++	/* register switch device, it's for management only - no I/O */
++	netdev = alloc_etherdev(sizeof(*priv));
++	if (!netdev) {
++		dev_err(dev, "alloc_etherdev error\n");
++		return -ENOMEM;
++	}
++	netdev->netdev_ops = &evb_ops;
++
++	dev_set_drvdata(dev, netdev);
++
++	priv = netdev_priv(netdev);
++
++	err = fsl_mc_portal_allocate(evb_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
++				     &priv->mc_io);
++	if (err) {
++		if (err == -ENXIO)
++			err = -EPROBE_DEFER;
++		else
++			dev_err(dev, "fsl_mc_portal_allocate err %d\n", err);
++		goto err_free_netdev;
++	}
++
++	if (!priv->mc_io) {
++		dev_err(dev, "fsl_mc_portal_allocate returned null handle but no error\n");
++		err = -EFAULT;
++		goto err_free_netdev;
++	}
++
++	err = evb_init(evb_dev);
++	if (unlikely(err)) {
++		dev_err(dev, "evb init err %d\n", err);
++		goto err_free_cmdport;
++	}
++
++	INIT_LIST_HEAD(&priv->port_list);
++	netdev->flags |= IFF_PROMISC | IFF_MASTER;
++
++	dev_alloc_name(netdev, "evb%d");
++
++	/* register switch ports */
++	snprintf(port_name, IFNAMSIZ, "%sp%%d", netdev->name);
++
++	/* only register downlinks? */
++	for (i = 0; i < priv->attr.num_ifs + 1; i++) {
++		struct net_device *port_netdev;
++		struct evb_port_priv *port_priv;
++
++		if (i) {
++			port_netdev =
++				alloc_etherdev(sizeof(struct evb_port_priv));
++			if (!port_netdev) {
++				dev_err(dev, "alloc_etherdev error\n");
++				goto err_takedown;
++			}
++
++			port_priv = netdev_priv(port_netdev);
++
++			port_netdev->flags |= IFF_PROMISC | IFF_SLAVE;
++
++			dev_alloc_name(port_netdev, port_name);
++		} else {
++			port_netdev = netdev;
++			port_priv = &priv->uplink;
++		}
++
++		port_priv->netdev = port_netdev;
++		port_priv->evb_priv = priv;
++		port_priv->port_index = i;
++
++		SET_NETDEV_DEV(port_netdev, dev);
++
++		if (i) {
++			port_netdev->netdev_ops = &evb_port_ops;
++
++			err = register_netdev(port_netdev);
++			if (err < 0) {
++				dev_err(dev, "register_netdev err %d\n", err);
++				free_netdev(port_netdev);
++				goto err_takedown;
++			}
++
++			rtnl_lock();
++			err = netdev_master_upper_dev_link(port_netdev, netdev,
++							   NULL, NULL);
++			if (unlikely(err)) {
++				dev_err(dev, "netdev_master_upper_dev_link err %d\n",
++					err);
++				unregister_netdev(port_netdev);
++				free_netdev(port_netdev);
++				rtnl_unlock();
++				goto err_takedown;
++			}
++			rtmsg_ifinfo(RTM_NEWLINK, port_netdev,
++				     IFF_SLAVE, GFP_KERNEL);
++			rtnl_unlock();
++
++			list_add(&port_priv->list, &priv->port_list);
++		} else {
++			/* Set MTU limits only on uplink */
++			port_netdev->min_mtu = EVB_MIN_MTU;
++			port_netdev->max_mtu = EVB_MAX_MTU;
++
++			err = register_netdev(netdev);
++
++			if (err < 0) {
++				dev_err(dev, "register_netdev error %d\n", err);
++				goto err_takedown;
++			}
++		}
++
++		port_netdev->ethtool_ops = &evb_port_ethtool_ops;
++
++		/* ports are up from init */
++		rtnl_lock();
++		err = dev_open(port_netdev);
++		rtnl_unlock();
++		if (unlikely(err))
++			dev_warn(dev, "dev_open err %d\n", err);
++	}
++
++	/* setup irqs */
++	err = evb_setup_irqs(evb_dev);
++	if (unlikely(err)) {
++		dev_warn(dev, "evb_setup_irqs err %d\n", err);
++		goto err_takedown;
++	}
++
++	dev_info(dev, "probed evb device with %d ports\n",
++		 priv->attr.num_ifs);
++	return 0;
++
++err_takedown:
++	evb_remove(evb_dev);
++err_free_cmdport:
++	fsl_mc_portal_free(priv->mc_io);
++err_free_netdev:
++	return err;
++}
++
++static const struct fsl_mc_device_id evb_match_id_table[] = {
++	{
++		.vendor = FSL_MC_VENDOR_FREESCALE,
++		.obj_type = "dpdmux",
++	},
++	{}
++};
++
++static struct fsl_mc_driver evb_drv = {
++	.driver = {
++		.name		= KBUILD_MODNAME,
++		.owner		= THIS_MODULE,
++	},
++	.probe		= evb_probe,
++	.remove		= evb_remove,
++	.match_id_table = evb_match_id_table,
++};
++
++module_fsl_mc_driver(evb_drv);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Layerscape DPAA Edge Virtual Bridge driver (prototype)");
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/mac/Kconfig
+@@ -0,0 +1,23 @@
++config FSL_DPAA2_MAC
++	tristate "DPAA2 MAC / PHY interface"
++	depends on FSL_MC_BUS && FSL_DPAA2
++	select MDIO_BUS_MUX_MMIOREG
++	select FSL_XGMAC_MDIO
++	select FIXED_PHY
++	---help---
++	Prototype driver for DPAA2 MAC / PHY interface object.
++	This driver works as a proxy between phylib including phy drivers and
++	the MC firmware.  It receives updates on link state changes from PHY
++	lib and forwards them to MC and receives interrupt from MC whenever
++	a request is made to change the link state.
++
++
++config FSL_DPAA2_MAC_NETDEVS
++	bool "Expose net interfaces for PHYs"
++	default n
++	depends on FSL_DPAA2_MAC
++	---help---
++	Exposes macX net interfaces which allow direct control over MACs and
++	PHYs.
++	.
++	Leave disabled if unsure.
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/mac/Makefile
+@@ -0,0 +1,10 @@
++
++obj-$(CONFIG_FSL_DPAA2_MAC) += dpaa2-mac.o
++
++dpaa2-mac-objs := mac.o dpmac.o
++
++all:
++	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
++
++clean:
++	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/mac/dpmac-cmd.h
+@@ -0,0 +1,172 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef _FSL_DPMAC_CMD_H
++#define _FSL_DPMAC_CMD_H
++
++/* DPMAC Version */
++#define DPMAC_VER_MAJOR				4
++#define DPMAC_VER_MINOR				2
++#define DPMAC_CMD_BASE_VERSION			1
++#define DPMAC_CMD_ID_OFFSET			4
++
++#define DPMAC_CMD(id)	(((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_BASE_VERSION)
++
++/* Command IDs */
++#define DPMAC_CMDID_CLOSE		DPMAC_CMD(0x800)
++#define DPMAC_CMDID_OPEN		DPMAC_CMD(0x80c)
++#define DPMAC_CMDID_CREATE		DPMAC_CMD(0x90c)
++#define DPMAC_CMDID_DESTROY		DPMAC_CMD(0x98c)
++#define DPMAC_CMDID_GET_API_VERSION	DPMAC_CMD(0xa0c)
++
++#define DPMAC_CMDID_GET_ATTR		DPMAC_CMD(0x004)
++#define DPMAC_CMDID_RESET		DPMAC_CMD(0x005)
++
++#define DPMAC_CMDID_SET_IRQ_ENABLE	DPMAC_CMD(0x012)
++#define DPMAC_CMDID_GET_IRQ_ENABLE	DPMAC_CMD(0x013)
++#define DPMAC_CMDID_SET_IRQ_MASK	DPMAC_CMD(0x014)
++#define DPMAC_CMDID_GET_IRQ_MASK	DPMAC_CMD(0x015)
++#define DPMAC_CMDID_GET_IRQ_STATUS	DPMAC_CMD(0x016)
++#define DPMAC_CMDID_CLEAR_IRQ_STATUS	DPMAC_CMD(0x017)
++
++#define DPMAC_CMDID_GET_LINK_CFG	DPMAC_CMD(0x0c2)
++#define DPMAC_CMDID_SET_LINK_STATE	DPMAC_CMD(0x0c3)
++#define DPMAC_CMDID_GET_COUNTER		DPMAC_CMD(0x0c4)
++
++#define DPMAC_CMDID_SET_PORT_MAC_ADDR	DPMAC_CMD(0x0c5)
++
++/* Macros for accessing command fields smaller than 1byte */
++#define DPMAC_MASK(field)        \
++	GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \
++		DPMAC_##field##_SHIFT)
++#define dpmac_set_field(var, field, val) \
++	((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field)))
++#define dpmac_get_field(var, field)      \
++	(((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT)
++
++struct dpmac_cmd_open {
++	u32 dpmac_id;
++};
++
++struct dpmac_cmd_create {
++	u32 mac_id;
++};
++
++struct dpmac_cmd_destroy {
++	u32 dpmac_id;
++};
++
++struct dpmac_cmd_set_irq_enable {
++	u8 enable;
++	u8 pad[3];
++	u8 irq_index;
++};
++
++struct dpmac_cmd_get_irq_enable {
++	u32 pad;
++	u8 irq_index;
++};
++
++struct dpmac_rsp_get_irq_enable {
++	u8 enabled;
++};
++
++struct dpmac_cmd_set_irq_mask {
++	u32 mask;
++	u8 irq_index;
++};
++
++struct dpmac_cmd_get_irq_mask {
++	u32 pad;
++	u8 irq_index;
++};
++
++struct dpmac_rsp_get_irq_mask {
++	u32 mask;
++};
++
++struct dpmac_cmd_get_irq_status {
++	u32 status;
++	u8 irq_index;
++};
++
++struct dpmac_rsp_get_irq_status {
++	u32 status;
++};
++
++struct dpmac_cmd_clear_irq_status {
++	u32 status;
++	u8 irq_index;
++};
++
++struct dpmac_rsp_get_attributes {
++	u8 eth_if;
++	u8 link_type;
++	u16 id;
++	u32 max_rate;
++};
++
++struct dpmac_rsp_get_link_cfg {
++	u64 options;
++	u32 rate;
++};
++
++#define DPMAC_STATE_SIZE	1
++#define DPMAC_STATE_SHIFT	0
++
++struct dpmac_cmd_set_link_state {
++	u64 options;
++	u32 rate;
++	u32 pad;
++	/* only least significant bit is valid */
++	u8 up;
++};
++
++struct dpmac_cmd_get_counter {
++	u8 type;
++};
++
++struct dpmac_rsp_get_counter {
++	u64 pad;
++	u64 counter;
++};
++
++struct dpmac_rsp_get_api_version {
++	u16 major;
++	u16 minor;
++};
++
++struct dpmac_cmd_set_port_mac_addr {
++	u8 pad[2];
++	u8 addr[6];
++};
++
++#endif /* _FSL_DPMAC_CMD_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/mac/dpmac.c
+@@ -0,0 +1,619 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#include <linux/fsl/mc.h>
++#include "dpmac.h"
++#include "dpmac-cmd.h"
++
++/**
++ * dpmac_open() - Open a control session for the specified object.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @dpmac_id:	DPMAC unique ID
++ * @token:	Returned token; use in subsequent API calls
++ *
++ * This function can be used to open a control session for an
++ * already created object; an object may have been declared in
++ * the DPL or by calling the dpmac_create function.
++ * This function returns a unique authentication token,
++ * associated with the specific object ID and the specific MC
++ * portal; this token must be used in all subsequent commands for
++ * this specific object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_open(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       int dpmac_id,
++	       u16 *token)
++{
++	struct dpmac_cmd_open *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN,
++					  cmd_flags,
++					  0);
++	cmd_params = (struct dpmac_cmd_open *)cmd.params;
++	cmd_params->dpmac_id = cpu_to_le32(dpmac_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*token = mc_cmd_hdr_read_token(&cmd);
++
++	return err;
++}
++
++/**
++ * dpmac_close() - Close the control session of the object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ *
++ * After this function is called, no further operations are
++ * allowed on the object without opening a new control session.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_close(struct fsl_mc_io *mc_io,
++		u32 cmd_flags,
++		u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpmac_create() - Create the DPMAC object.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @dprc_token: Parent container token; '0' for default container
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @cfg:	Configuration structure
++ * @obj_id:	Returned object id
++ *
++ * Create the DPMAC object, allocate required resources and
++ * perform required initialization.
++ *
++ * The function accepts an authentication token of a parent
++ * container that this object should be assigned to. The token
++ * can be '0' so the object will be assigned to the default container.
++ * The newly created object can be opened with the returned
++ * object id and using the container's associated tokens and MC portals.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_create(struct fsl_mc_io *mc_io,
++		 u16 dprc_token,
++		 u32 cmd_flags,
++		 const struct dpmac_cfg *cfg,
++		 u32 *obj_id)
++{
++	struct dpmac_cmd_create *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE,
++					  cmd_flags,
++					  dprc_token);
++	cmd_params = (struct dpmac_cmd_create *)cmd.params;
++	cmd_params->mac_id = cpu_to_le32(cfg->mac_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*obj_id = mc_cmd_read_object_id(&cmd);
++
++	return 0;
++}
++
++/**
++ * dpmac_destroy() - Destroy the DPMAC object and release all its resources.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @dprc_token: Parent container token; '0' for default container
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @object_id:	The object id; it must be a valid id within the container that
++ * created this object;
++ *
++ * The function accepts the authentication token of the parent container that
++ * created the object (not the one that currently owns the object). The object
++ * is searched within parent using the provided 'object_id'.
++ * All tokens to the object must be closed before calling destroy.
++ *
++ * Return:	'0' on Success; error code otherwise.
++ */
++int dpmac_destroy(struct fsl_mc_io *mc_io,
++		  u16 dprc_token,
++		  u32 cmd_flags,
++		  u32 object_id)
++{
++	struct dpmac_cmd_destroy *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY,
++					  cmd_flags,
++					  dprc_token);
++	cmd_params = (struct dpmac_cmd_destroy *)cmd.params;
++	cmd_params->dpmac_id = cpu_to_le32(object_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpmac_set_irq_enable() - Set overall interrupt state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Interrupt state - enable = 1, disable = 0
++ *
++ * Allows GPP software to control when interrupts are generated.
++ * Each interrupt can have up to 32 causes.  The enable/disable control's the
++ * overall interrupt state. if the interrupt is disabled no causes will cause
++ * an interrupt.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_set_irq_enable(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u8 irq_index,
++			 u8 en)
++{
++	struct dpmac_cmd_set_irq_enable *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpmac_cmd_set_irq_enable *)cmd.params;
++	cmd_params->irq_index = irq_index;
++	cmd_params->enable = en;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpmac_get_irq_enable() - Get overall interrupt state
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Returned interrupt state - enable = 1, disable = 0
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_get_irq_enable(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u8 irq_index,
++			 u8 *en)
++{
++	struct dpmac_cmd_get_irq_enable *cmd_params;
++	struct dpmac_rsp_get_irq_enable *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpmac_cmd_get_irq_enable *)cmd.params;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpmac_rsp_get_irq_enable *)cmd.params;
++	*en = rsp_params->enabled;
++
++	return 0;
++}
++
++/**
++ * dpmac_set_irq_mask() - Set interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	Event mask to trigger interrupt;
++ *		each bit:
++ *			0 = ignore event
++ *			1 = consider event for asserting IRQ
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_set_irq_mask(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       u8 irq_index,
++		       u32 mask)
++{
++	struct dpmac_cmd_set_irq_mask *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpmac_cmd_set_irq_mask *)cmd.params;
++	cmd_params->mask = cpu_to_le32(mask);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpmac_get_irq_mask() - Get interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	Returned event mask to trigger interrupt
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_get_irq_mask(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       u8 irq_index,
++		       u32 *mask)
++{
++	struct dpmac_cmd_get_irq_mask *cmd_params;
++	struct dpmac_rsp_get_irq_mask *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpmac_cmd_get_irq_mask *)cmd.params;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpmac_rsp_get_irq_mask *)cmd.params;
++	*mask = le32_to_cpu(rsp_params->mask);
++
++	return 0;
++}
++
++/**
++ * dpmac_get_irq_status() - Get the current status of any pending interrupts.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @irq_index:	The interrupt index to configure
++ * @status:	Returned interrupts status - one bit per cause:
++ *			0 = no interrupt pending
++ *			1 = interrupt pending
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_get_irq_status(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u8 irq_index,
++			 u32 *status)
++{
++	struct dpmac_cmd_get_irq_status *cmd_params;
++	struct dpmac_rsp_get_irq_status *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpmac_cmd_get_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(*status);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpmac_rsp_get_irq_status *)cmd.params;
++	*status = le32_to_cpu(rsp_params->status);
++
++	return 0;
++}
++
++/**
++ * dpmac_clear_irq_status() - Clear a pending interrupt's status
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @irq_index:	The interrupt index to configure
++ * @status:	Bits to clear (W1C) - one bit per cause:
++ *			0 = don't change
++ *			1 = clear status bit
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u8 irq_index,
++			   u32 status)
++{
++	struct dpmac_cmd_clear_irq_status *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLEAR_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpmac_cmd_clear_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(status);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpmac_get_attributes - Retrieve DPMAC attributes.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @attr:	Returned object's attributes
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_get_attributes(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 struct dpmac_attr *attr)
++{
++	struct dpmac_rsp_get_attributes *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dpmac_rsp_get_attributes *)cmd.params;
++	attr->eth_if = rsp_params->eth_if;
++	attr->link_type = rsp_params->link_type;
++	attr->id = le16_to_cpu(rsp_params->id);
++	attr->max_rate = le32_to_cpu(rsp_params->max_rate);
++
++	return 0;
++}
++
++/**
++ * dpmac_get_link_cfg() - Get Ethernet link configuration
++ * @mc_io:	Pointer to opaque I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @cfg:	Returned structure with the link configuration
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       struct dpmac_link_cfg *cfg)
++{
++	struct dpmac_rsp_get_link_cfg *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err = 0;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpmac_rsp_get_link_cfg *)cmd.params;
++	cfg->options = le64_to_cpu(rsp_params->options);
++	cfg->rate = le32_to_cpu(rsp_params->rate);
++
++	return 0;
++}
++
++/**
++ * dpmac_set_link_state() - Set the Ethernet link status
++ * @mc_io:	Pointer to opaque I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @link_state:	Link state configuration
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dpmac_set_link_state(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 struct dpmac_link_state *link_state)
++{
++	struct dpmac_cmd_set_link_state *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpmac_cmd_set_link_state *)cmd.params;
++	cmd_params->options = cpu_to_le64(link_state->options);
++	cmd_params->rate = cpu_to_le32(link_state->rate);
++	cmd_params->up = dpmac_get_field(link_state->up, STATE);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpmac_get_counter() - Read a specific DPMAC counter
++ * @mc_io:	Pointer to opaque I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @type:	The requested counter
++ * @counter:	Returned counter value
++ *
++ * Return:	The requested counter; '0' otherwise.
++ */
++int dpmac_get_counter(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      enum dpmac_counter type,
++		      u64 *counter)
++{
++	struct dpmac_cmd_get_counter *dpmac_cmd;
++	struct dpmac_rsp_get_counter *dpmac_rsp;
++	struct fsl_mc_command cmd = { 0 };
++	int err = 0;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER,
++					  cmd_flags,
++					  token);
++	dpmac_cmd = (struct dpmac_cmd_get_counter *)cmd.params;
++	dpmac_cmd->type = type;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	dpmac_rsp = (struct dpmac_rsp_get_counter *)cmd.params;
++	*counter = le64_to_cpu(dpmac_rsp->counter);
++
++	return 0;
++}
++
++/* untested */
++int dpmac_set_port_mac_addr(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    const u8 addr[6])
++{
++	struct dpmac_cmd_set_port_mac_addr *dpmac_cmd;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_PORT_MAC_ADDR,
++					  cmd_flags,
++					  token);
++	dpmac_cmd = (struct dpmac_cmd_set_port_mac_addr *)cmd.params;
++	dpmac_cmd->addr[0] = addr[5];
++	dpmac_cmd->addr[1] = addr[4];
++	dpmac_cmd->addr[2] = addr[3];
++	dpmac_cmd->addr[3] = addr[2];
++	dpmac_cmd->addr[4] = addr[1];
++	dpmac_cmd->addr[5] = addr[0];
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpmac_get_api_version() - Get Data Path MAC version
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @major_ver:	Major version of data path mac API
++ * @minor_ver:	Minor version of data path mac API
++ *
++ * Return:  '0' on Success; Error code otherwise.
++ */
++int dpmac_get_api_version(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 *major_ver,
++			  u16 *minor_ver)
++{
++	struct dpmac_rsp_get_api_version *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION,
++					cmd_flags,
++					0);
++
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpmac_rsp_get_api_version *)cmd.params;
++	*major_ver = le16_to_cpu(rsp_params->major);
++	*minor_ver = le16_to_cpu(rsp_params->minor);
++
++	return 0;
++}
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/mac/dpmac.h
+@@ -0,0 +1,342 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef __FSL_DPMAC_H
++#define __FSL_DPMAC_H
++
++/* Data Path MAC API
++ * Contains initialization APIs and runtime control APIs for DPMAC
++ */
++
++struct fsl_mc_io;
++
++int dpmac_open(struct fsl_mc_io *mc_io,
++	       u32 cmd_flags,
++	       int dpmac_id,
++	       u16 *token);
++
++int dpmac_close(struct fsl_mc_io *mc_io,
++		u32 cmd_flags,
++		u16 token);
++
++/**
++ * enum dpmac_link_type -  DPMAC link type
++ * @DPMAC_LINK_TYPE_NONE: No link
++ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
++ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
++ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
++ */
++enum dpmac_link_type {
++	DPMAC_LINK_TYPE_NONE,
++	DPMAC_LINK_TYPE_FIXED,
++	DPMAC_LINK_TYPE_PHY,
++	DPMAC_LINK_TYPE_BACKPLANE
++};
++
++/**
++ * enum dpmac_eth_if - DPMAC Ethrnet interface
++ * @DPMAC_ETH_IF_MII: MII interface
++ * @DPMAC_ETH_IF_RMII: RMII interface
++ * @DPMAC_ETH_IF_SMII: SMII interface
++ * @DPMAC_ETH_IF_GMII: GMII interface
++ * @DPMAC_ETH_IF_RGMII: RGMII interface
++ * @DPMAC_ETH_IF_SGMII: SGMII interface
++ * @DPMAC_ETH_IF_QSGMII: QSGMII interface
++ * @DPMAC_ETH_IF_XAUI: XAUI interface
++ * @DPMAC_ETH_IF_XFI: XFI interface
++ */
++enum dpmac_eth_if {
++	DPMAC_ETH_IF_MII,
++	DPMAC_ETH_IF_RMII,
++	DPMAC_ETH_IF_SMII,
++	DPMAC_ETH_IF_GMII,
++	DPMAC_ETH_IF_RGMII,
++	DPMAC_ETH_IF_SGMII,
++	DPMAC_ETH_IF_QSGMII,
++	DPMAC_ETH_IF_XAUI,
++	DPMAC_ETH_IF_XFI
++};
++
++/**
++ * struct dpmac_cfg - Structure representing DPMAC configuration
++ * @mac_id:	Represents the Hardware MAC ID; in case of multiple WRIOP,
++ *		the MAC IDs are continuous.
++ *		For example:  2 WRIOPs, 16 MACs in each:
++ *				MAC IDs for the 1st WRIOP: 1-16,
++ *				MAC IDs for the 2nd WRIOP: 17-32.
++ */
++struct dpmac_cfg {
++	u16 mac_id;
++};
++
++int dpmac_create(struct fsl_mc_io *mc_io,
++		 u16 dprc_token,
++		 u32 cmd_flags,
++		 const struct dpmac_cfg *cfg,
++		 u32 *obj_id);
++
++int dpmac_destroy(struct fsl_mc_io *mc_io,
++		  u16 dprc_token,
++		  u32 cmd_flags,
++		  u32 object_id);
++
++/**
++ * DPMAC IRQ Index and Events
++ */
++
++/**
++ * IRQ index
++ */
++#define DPMAC_IRQ_INDEX				0
++/**
++ * IRQ event - indicates a change in link state
++ */
++#define DPMAC_IRQ_EVENT_LINK_CFG_REQ		0x00000001
++/**
++ * IRQ event - Indicates that the link state changed
++ */
++#define DPMAC_IRQ_EVENT_LINK_CHANGED		0x00000002
++
++int dpmac_set_irq_enable(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u8 irq_index,
++			 u8 en);
++
++int dpmac_get_irq_enable(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u8 irq_index,
++			 u8 *en);
++
++int dpmac_set_irq_mask(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       u8 irq_index,
++		       u32 mask);
++
++int dpmac_get_irq_mask(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       u8 irq_index,
++		       u32 *mask);
++
++int dpmac_get_irq_status(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 u8 irq_index,
++			 u32 *status);
++
++int dpmac_clear_irq_status(struct fsl_mc_io *mc_io,
++			   u32 cmd_flags,
++			   u16 token,
++			   u8 irq_index,
++			   u32 status);
++
++/**
++ * struct dpmac_attr - Structure representing DPMAC attributes
++ * @id:		DPMAC object ID
++ * @max_rate:	Maximum supported rate - in Mbps
++ * @eth_if:	Ethernet interface
++ * @link_type:	link type
++ */
++struct dpmac_attr {
++	u16 id;
++	u32 max_rate;
++	enum dpmac_eth_if eth_if;
++	enum dpmac_link_type link_type;
++};
++
++int dpmac_get_attributes(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 struct dpmac_attr *attr);
++
++/**
++ * DPMAC link configuration/state options
++ */
++
++/**
++ * Enable auto-negotiation
++ */
++#define DPMAC_LINK_OPT_AUTONEG		0x0000000000000001ULL
++/**
++ * Enable half-duplex mode
++ */
++#define DPMAC_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
++/**
++ * Enable pause frames
++ */
++#define DPMAC_LINK_OPT_PAUSE		0x0000000000000004ULL
++/**
++ * Enable a-symmetric pause frames
++ */
++#define DPMAC_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
++
++/**
++ * struct dpmac_link_cfg - Structure representing DPMAC link configuration
++ * @rate: Link's rate - in Mbps
++ * @options: Enable/Disable DPMAC link cfg features (bitmap)
++ */
++struct dpmac_link_cfg {
++	u32 rate;
++	u64 options;
++};
++
++int dpmac_get_link_cfg(struct fsl_mc_io *mc_io,
++		       u32 cmd_flags,
++		       u16 token,
++		       struct dpmac_link_cfg *cfg);
++
++/**
++ * struct dpmac_link_state - DPMAC link configuration request
++ * @rate: Rate in Mbps
++ * @options: Enable/Disable DPMAC link cfg features (bitmap)
++ * @up: Link state
++ */
++struct dpmac_link_state {
++	u32 rate;
++	u64 options;
++	int up;
++};
++
++int dpmac_set_link_state(struct fsl_mc_io *mc_io,
++			 u32 cmd_flags,
++			 u16 token,
++			 struct dpmac_link_state *link_state);
++
++/**
++ * enum dpmac_counter - DPMAC counter types
++ * @DPMAC_CNT_ING_FRAME_64: counts 64-bytes frames, good or bad.
++ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-bytes frames, good or bad.
++ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-bytes frames, good or bad.
++ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-bytes frames, good or bad.
++ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-bytes frames, good or bad.
++ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-bytes frames, good or bad.
++ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-bytes frames and larger
++ *				  (up to max frame length specified),
++ *				  good or bad.
++ * @DPMAC_CNT_ING_FRAG: counts frames which are shorter than 64 bytes received
++ *			with a wrong CRC
++ * @DPMAC_CNT_ING_JABBER: counts frames longer than the maximum frame length
++ *			  specified, with a bad frame check sequence.
++ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped frames due to internal errors.
++ *				 Occurs when a receive FIFO overflows.
++ *				 Includes also frames truncated as a result of
++ *				 the receive FIFO overflow.
++ * @DPMAC_CNT_ING_ALIGN_ERR: counts frames with an alignment error
++ *			     (optional used for wrong SFD).
++ * @DPMAC_CNT_EGR_UNDERSIZED: counts frames transmitted that was less than 64
++ *			      bytes long with a good CRC.
++ * @DPMAC_CNT_ING_OVERSIZED: counts frames longer than the maximum frame length
++ *			     specified, with a good frame check sequence.
++ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frames (regular and PFC)
++ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frames transmitted
++ *				     (regular and PFC).
++ * @DPMAC_CNT_ING_BYTE: counts bytes received except preamble for all valid
++ *			frames and valid pause frames.
++ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frames.
++ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frames.
++ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad frames received.
++ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frames.
++ * @DPMAC_CNT_ING_ERR_FRAME: counts frames received with an error
++ *			     (except for undersized/fragment frame).
++ * @DPMAC_CNT_EGR_BYTE: counts bytes transmitted except preamble for all valid
++ *			frames and valid pause frames transmitted.
++ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frames.
++ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frames.
++ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frames.
++ * @DPMAC_CNT_EGR_ERR_FRAME: counts frames transmitted with an error.
++ * @DPMAC_CNT_ING_GOOD_FRAME: counts frames received without error, including
++ *			      pause frames.
++ * @DPMAC_CNT_ENG_GOOD_FRAME: counts frames transmitted without error, including
++ *			      pause frames.
++ */
++enum dpmac_counter {
++	DPMAC_CNT_ING_FRAME_64,
++	DPMAC_CNT_ING_FRAME_127,
++	DPMAC_CNT_ING_FRAME_255,
++	DPMAC_CNT_ING_FRAME_511,
++	DPMAC_CNT_ING_FRAME_1023,
++	DPMAC_CNT_ING_FRAME_1518,
++	DPMAC_CNT_ING_FRAME_1519_MAX,
++	DPMAC_CNT_ING_FRAG,
++	DPMAC_CNT_ING_JABBER,
++	DPMAC_CNT_ING_FRAME_DISCARD,
++	DPMAC_CNT_ING_ALIGN_ERR,
++	DPMAC_CNT_EGR_UNDERSIZED,
++	DPMAC_CNT_ING_OVERSIZED,
++	DPMAC_CNT_ING_VALID_PAUSE_FRAME,
++	DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
++	DPMAC_CNT_ING_BYTE,
++	DPMAC_CNT_ING_MCAST_FRAME,
++	DPMAC_CNT_ING_BCAST_FRAME,
++	DPMAC_CNT_ING_ALL_FRAME,
++	DPMAC_CNT_ING_UCAST_FRAME,
++	DPMAC_CNT_ING_ERR_FRAME,
++	DPMAC_CNT_EGR_BYTE,
++	DPMAC_CNT_EGR_MCAST_FRAME,
++	DPMAC_CNT_EGR_BCAST_FRAME,
++	DPMAC_CNT_EGR_UCAST_FRAME,
++	DPMAC_CNT_EGR_ERR_FRAME,
++	DPMAC_CNT_ING_GOOD_FRAME,
++	DPMAC_CNT_ENG_GOOD_FRAME
++};
++
++int dpmac_get_counter(struct fsl_mc_io *mc_io,
++		      u32 cmd_flags,
++		      u16 token,
++		      enum dpmac_counter type,
++		      u64 *counter);
++
++/**
++ * dpmac_set_port_mac_addr() - Set a MAC address associated with the physical
++ *              port.  This is not used for filtering, MAC is always in
++ *              promiscuous mode, it is passed to DPNIs through DPNI API for
++ *              application used.
++ * @mc_io:	Pointer to opaque I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPMAC object
++ * @addr:	MAC address to set
++ *
++ * Return:	The requested counter; '0' otherwise.
++ */
++int dpmac_set_port_mac_addr(struct fsl_mc_io *mc_io,
++			    u32 cmd_flags,
++			    u16 token,
++			    const u8 addr[6]);
++
++int dpmac_get_api_version(struct fsl_mc_io *mc_io,
++			  u32 cmd_flags,
++			  u16 *major_ver,
++			  u16 *minor_ver);
++
++#endif /* __FSL_DPMAC_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/mac/mac.c
+@@ -0,0 +1,673 @@
++/* Copyright 2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *	 names of its contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/module.h>
++
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/msi.h>
++#include <linux/rtnetlink.h>
++#include <linux/if_vlan.h>
++
++#include <uapi/linux/if_bridge.h>
++#include <net/netlink.h>
++
++#include <linux/of.h>
++#include <linux/of_mdio.h>
++#include <linux/of_net.h>
++#include <linux/phy.h>
++#include <linux/phy_fixed.h>
++
++#include <linux/fsl/mc.h>
++
++#include "dpmac.h"
++#include "dpmac-cmd.h"
++
++struct dpaa2_mac_priv {
++	struct net_device		*netdev;
++	struct fsl_mc_device		*mc_dev;
++	struct dpmac_attr		attr;
++	struct dpmac_link_state		old_state;
++};
++
++/* TODO: fix the 10G modes, mapping can't be right:
++ *  XGMII is paralel
++ *  XAUI is serial, using 8b/10b encoding
++ *  XFI is also serial but using 64b/66b encoding
++ * they can't all map to XGMII...
++ *
++ * This must be kept in sync with enum dpmac_eth_if.
++ */
++static phy_interface_t dpaa2_mac_iface_mode[] =  {
++	PHY_INTERFACE_MODE_MII,		/* DPMAC_ETH_IF_MII */
++	PHY_INTERFACE_MODE_RMII,	/* DPMAC_ETH_IF_RMII */
++	PHY_INTERFACE_MODE_SMII,	/* DPMAC_ETH_IF_SMII */
++	PHY_INTERFACE_MODE_GMII,	/* DPMAC_ETH_IF_GMII */
++	PHY_INTERFACE_MODE_RGMII,	/* DPMAC_ETH_IF_RGMII */
++	PHY_INTERFACE_MODE_SGMII,	/* DPMAC_ETH_IF_SGMII */
++	PHY_INTERFACE_MODE_QSGMII,	/* DPMAC_ETH_IF_QSGMII */
++	PHY_INTERFACE_MODE_XGMII,	/* DPMAC_ETH_IF_XAUI */
++	PHY_INTERFACE_MODE_XGMII,	/* DPMAC_ETH_IF_XFI */
++};
++
++static void dpaa2_mac_link_changed(struct net_device *netdev)
++{
++	struct phy_device	*phydev;
++	struct dpmac_link_state	state = { 0 };
++	struct dpaa2_mac_priv	*priv = netdev_priv(netdev);
++	int			err;
++
++	/* the PHY just notified us of link state change */
++	phydev = netdev->phydev;
++
++	state.up = !!phydev->link;
++	if (phydev->link) {
++		state.rate = phydev->speed;
++
++		if (!phydev->duplex)
++			state.options |= DPMAC_LINK_OPT_HALF_DUPLEX;
++		if (phydev->autoneg)
++			state.options |= DPMAC_LINK_OPT_AUTONEG;
++
++		netif_carrier_on(netdev);
++	} else {
++		netif_carrier_off(netdev);
++	}
++
++	if (priv->old_state.up != state.up ||
++	    priv->old_state.rate != state.rate ||
++	    priv->old_state.options != state.options) {
++		priv->old_state = state;
++		phy_print_status(phydev);
++	}
++
++	/* We must interrogate MC at all times, because we don't know
++	 * when and whether a potential DPNI may have read the link state.
++	 */
++	err = dpmac_set_link_state(priv->mc_dev->mc_io, 0,
++				   priv->mc_dev->mc_handle, &state);
++	if (unlikely(err))
++		dev_err(&priv->mc_dev->dev, "dpmac_set_link_state: %d\n", err);
++}
++
++static int dpaa2_mac_open(struct net_device *netdev)
++{
++	/* start PHY state machine */
++	phy_start(netdev->phydev);
++
++	return 0;
++}
++
++static int dpaa2_mac_stop(struct net_device *netdev)
++{
++	if (!netdev->phydev)
++		goto done;
++
++	/* stop PHY state machine */
++	phy_stop(netdev->phydev);
++
++	/* signal link down to firmware */
++	netdev->phydev->link = 0;
++	dpaa2_mac_link_changed(netdev);
++
++done:
++	return 0;
++}
++
++#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
++static netdev_tx_t dpaa2_mac_drop_frame(struct sk_buff *skb,
++					struct net_device *dev)
++{
++	/* we don't support I/O for now, drop the frame */
++	dev_kfree_skb_any(skb);
++	return NETDEV_TX_OK;
++}
++
++static int dpaa2_mac_get_link_ksettings(struct net_device *netdev,
++					struct ethtool_link_ksettings *ks)
++{
++	phy_ethtool_ksettings_get(netdev->phydev, ks);
++
++	return 0;
++}
++
++static int dpaa2_mac_set_link_ksettings(struct net_device *netdev,
++					const struct ethtool_link_ksettings *ks)
++{
++	return phy_ethtool_ksettings_set(netdev->phydev, ks);
++}
++
++static struct rtnl_link_stats64 *dpaa2_mac_get_stats(struct net_device *netdev,
++				struct rtnl_link_stats64 *storage)
++{
++	struct dpaa2_mac_priv	*priv = netdev_priv(netdev);
++	u64			tmp;
++	int			err;
++
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_EGR_MCAST_FRAME,
++				&storage->tx_packets);
++	if (err)
++		goto error;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_EGR_BCAST_FRAME, &tmp);
++	if (err)
++		goto error;
++	storage->tx_packets += tmp;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_EGR_UCAST_FRAME, &tmp);
++	if (err)
++		goto error;
++	storage->tx_packets += tmp;
++
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_EGR_UNDERSIZED, &storage->tx_dropped);
++	if (err)
++		goto error;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_EGR_BYTE, &storage->tx_bytes);
++	if (err)
++		goto error;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_EGR_ERR_FRAME, &storage->tx_errors);
++	if (err)
++		goto error;
++
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_ING_ALL_FRAME, &storage->rx_packets);
++	if (err)
++		goto error;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_ING_MCAST_FRAME, &storage->multicast);
++	if (err)
++		goto error;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_ING_FRAME_DISCARD,
++				&storage->rx_dropped);
++	if (err)
++		goto error;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_ING_ALIGN_ERR, &storage->rx_errors);
++	if (err)
++		goto error;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_ING_OVERSIZED, &tmp);
++	if (err)
++		goto error;
++	storage->rx_errors += tmp;
++	err = dpmac_get_counter(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle,
++				DPMAC_CNT_ING_BYTE, &storage->rx_bytes);
++	if (err)
++		goto error;
++
++	return storage;
++error:
++	netdev_err(netdev, "dpmac_get_counter err %d\n", err);
++	return storage;
++}
++
++static struct {
++	enum dpmac_counter id;
++	char name[ETH_GSTRING_LEN];
++} dpaa2_mac_counters[] =  {
++	{DPMAC_CNT_ING_ALL_FRAME,		"rx all frames"},
++	{DPMAC_CNT_ING_GOOD_FRAME,		"rx frames ok"},
++	{DPMAC_CNT_ING_ERR_FRAME,		"rx frame errors"},
++	{DPMAC_CNT_ING_FRAME_DISCARD,		"rx frame discards"},
++	{DPMAC_CNT_ING_UCAST_FRAME,		"rx u-cast"},
++	{DPMAC_CNT_ING_BCAST_FRAME,		"rx b-cast"},
++	{DPMAC_CNT_ING_MCAST_FRAME,		"rx m-cast"},
++	{DPMAC_CNT_ING_FRAME_64,		"rx 64 bytes"},
++	{DPMAC_CNT_ING_FRAME_127,		"rx 65-127 bytes"},
++	{DPMAC_CNT_ING_FRAME_255,		"rx 128-255 bytes"},
++	{DPMAC_CNT_ING_FRAME_511,		"rx 256-511 bytes"},
++	{DPMAC_CNT_ING_FRAME_1023,		"rx 512-1023 bytes"},
++	{DPMAC_CNT_ING_FRAME_1518,		"rx 1024-1518 bytes"},
++	{DPMAC_CNT_ING_FRAME_1519_MAX,		"rx 1519-max bytes"},
++	{DPMAC_CNT_ING_FRAG,			"rx frags"},
++	{DPMAC_CNT_ING_JABBER,			"rx jabber"},
++	{DPMAC_CNT_ING_ALIGN_ERR,		"rx align errors"},
++	{DPMAC_CNT_ING_OVERSIZED,		"rx oversized"},
++	{DPMAC_CNT_ING_VALID_PAUSE_FRAME,	"rx pause"},
++	{DPMAC_CNT_ING_BYTE,			"rx bytes"},
++	{DPMAC_CNT_ENG_GOOD_FRAME,		"tx frames ok"},
++	{DPMAC_CNT_EGR_UCAST_FRAME,		"tx u-cast"},
++	{DPMAC_CNT_EGR_MCAST_FRAME,		"tx m-cast"},
++	{DPMAC_CNT_EGR_BCAST_FRAME,		"tx b-cast"},
++	{DPMAC_CNT_EGR_ERR_FRAME,		"tx frame errors"},
++	{DPMAC_CNT_EGR_UNDERSIZED,		"tx undersized"},
++	{DPMAC_CNT_EGR_VALID_PAUSE_FRAME,	"tx b-pause"},
++	{DPMAC_CNT_EGR_BYTE,			"tx bytes"},
++
++};
++
++static void dpaa2_mac_get_strings(struct net_device *netdev,
++				  u32 stringset, u8 *data)
++{
++	int i;
++
++	switch (stringset) {
++	case ETH_SS_STATS:
++		for (i = 0; i < ARRAY_SIZE(dpaa2_mac_counters); i++)
++			memcpy(data + i * ETH_GSTRING_LEN,
++			       dpaa2_mac_counters[i].name,
++			       ETH_GSTRING_LEN);
++		break;
++	}
++}
++
++static void dpaa2_mac_get_ethtool_stats(struct net_device *netdev,
++					struct ethtool_stats *stats,
++					u64 *data)
++{
++	struct dpaa2_mac_priv	*priv = netdev_priv(netdev);
++	int			i;
++	int			err;
++
++	for (i = 0; i < ARRAY_SIZE(dpaa2_mac_counters); i++) {
++		err = dpmac_get_counter(priv->mc_dev->mc_io,
++					0,
++					priv->mc_dev->mc_handle,
++					dpaa2_mac_counters[i].id, &data[i]);
++		if (err)
++			netdev_err(netdev, "dpmac_get_counter[%s] err %d\n",
++				   dpaa2_mac_counters[i].name, err);
++	}
++}
++
++static int dpaa2_mac_get_sset_count(struct net_device *dev, int sset)
++{
++	switch (sset) {
++	case ETH_SS_STATS:
++		return ARRAY_SIZE(dpaa2_mac_counters);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static const struct net_device_ops dpaa2_mac_ndo_ops = {
++	.ndo_open		= &dpaa2_mac_open,
++	.ndo_stop		= &dpaa2_mac_stop,
++	.ndo_start_xmit		= &dpaa2_mac_drop_frame,
++	.ndo_get_stats64	= &dpaa2_mac_get_stats,
++};
++
++static const struct ethtool_ops dpaa2_mac_ethtool_ops = {
++	.get_link_ksettings	= &dpaa2_mac_get_link_ksettings,
++	.set_link_ksettings	= &dpaa2_mac_set_link_ksettings,
++	.get_strings		= &dpaa2_mac_get_strings,
++	.get_ethtool_stats	= &dpaa2_mac_get_ethtool_stats,
++	.get_sset_count		= &dpaa2_mac_get_sset_count,
++};
++#endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */
++
++static void configure_link(struct dpaa2_mac_priv *priv,
++			   struct dpmac_link_cfg *cfg)
++{
++	struct phy_device *phydev = priv->netdev->phydev;
++
++	if (unlikely(!phydev))
++		return;
++
++	phydev->speed = cfg->rate;
++	phydev->duplex  = !!(cfg->options & DPMAC_LINK_OPT_HALF_DUPLEX);
++
++	if (cfg->options & DPMAC_LINK_OPT_AUTONEG) {
++		phydev->autoneg = 1;
++		phydev->advertising |= ADVERTISED_Autoneg;
++	} else {
++		phydev->autoneg = 0;
++		phydev->advertising &= ~ADVERTISED_Autoneg;
++	}
++
++	phy_start_aneg(phydev);
++}
++
++static irqreturn_t dpaa2_mac_irq_handler(int irq_num, void *arg)
++{
++	struct device *dev = (struct device *)arg;
++	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
++	struct dpaa2_mac_priv *priv = dev_get_drvdata(dev);
++	struct dpmac_link_cfg link_cfg;
++	u32 status;
++	int err;
++
++	err = dpmac_get_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle,
++				   DPMAC_IRQ_INDEX, &status);
++	if (unlikely(err || !status))
++		return IRQ_NONE;
++
++	/* DPNI-initiated link configuration; 'ifconfig up' also calls this */
++	if (status & DPMAC_IRQ_EVENT_LINK_CFG_REQ) {
++		err = dpmac_get_link_cfg(mc_dev->mc_io, 0, mc_dev->mc_handle,
++					 &link_cfg);
++		if (unlikely(err))
++			goto out;
++
++		configure_link(priv, &link_cfg);
++	}
++
++out:
++	dpmac_clear_irq_status(mc_dev->mc_io, 0, mc_dev->mc_handle,
++			       DPMAC_IRQ_INDEX, status);
++
++	return IRQ_HANDLED;
++}
++
++static int setup_irqs(struct fsl_mc_device *mc_dev)
++{
++	int err = 0;
++	struct fsl_mc_device_irq *irq;
++
++	err = fsl_mc_allocate_irqs(mc_dev);
++	if (err) {
++		dev_err(&mc_dev->dev, "fsl_mc_allocate_irqs err %d\n", err);
++		return err;
++	}
++
++	irq = mc_dev->irqs[0];
++	err = devm_request_threaded_irq(&mc_dev->dev, irq->msi_desc->irq,
++					NULL, &dpaa2_mac_irq_handler,
++					IRQF_NO_SUSPEND | IRQF_ONESHOT,
++					dev_name(&mc_dev->dev), &mc_dev->dev);
++	if (err) {
++		dev_err(&mc_dev->dev, "devm_request_threaded_irq err %d\n",
++			err);
++		goto free_irq;
++	}
++
++	err = dpmac_set_irq_mask(mc_dev->mc_io, 0, mc_dev->mc_handle,
++				 DPMAC_IRQ_INDEX, DPMAC_IRQ_EVENT_LINK_CFG_REQ);
++	if (err) {
++		dev_err(&mc_dev->dev, "dpmac_set_irq_mask err %d\n", err);
++		goto free_irq;
++	}
++	err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle,
++				   DPMAC_IRQ_INDEX, 1);
++	if (err) {
++		dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err);
++		goto free_irq;
++	}
++
++	return 0;
++
++free_irq:
++	fsl_mc_free_irqs(mc_dev);
++
++	return err;
++}
++
++static void teardown_irqs(struct fsl_mc_device *mc_dev)
++{
++	int err;
++
++	err = dpmac_set_irq_enable(mc_dev->mc_io, 0, mc_dev->mc_handle,
++				   DPMAC_IRQ_INDEX, 0);
++	if (err)
++		dev_err(&mc_dev->dev, "dpmac_set_irq_enable err %d\n", err);
++
++	fsl_mc_free_irqs(mc_dev);
++}
++
++static struct device_node *find_dpmac_node(struct device *dev, u16 dpmac_id)
++{
++	struct device_node *dpmacs, *dpmac = NULL;
++	struct device_node *mc_node = dev->of_node;
++	u32 id;
++	int err;
++
++	dpmacs = of_find_node_by_name(mc_node, "dpmacs");
++	if (!dpmacs) {
++		dev_err(dev, "No dpmacs subnode in device-tree\n");
++		return NULL;
++	}
++
++	while ((dpmac = of_get_next_child(dpmacs, dpmac))) {
++		err = of_property_read_u32(dpmac, "reg", &id);
++		if (err)
++			continue;
++		if (id == dpmac_id)
++			return dpmac;
++	}
++
++	return NULL;
++}
++
++static int dpaa2_mac_probe(struct fsl_mc_device *mc_dev)
++{
++	struct device		*dev;
++	struct dpaa2_mac_priv	*priv = NULL;
++	struct device_node	*phy_node, *dpmac_node;
++	struct net_device	*netdev;
++	phy_interface_t		if_mode;
++	int			err = 0;
++
++	dev = &mc_dev->dev;
++
++	/* prepare a net_dev structure to make the phy lib API happy */
++	netdev = alloc_etherdev(sizeof(*priv));
++	if (!netdev) {
++		dev_err(dev, "alloc_etherdev error\n");
++		err = -ENOMEM;
++		goto err_exit;
++	}
++	priv = netdev_priv(netdev);
++	priv->mc_dev = mc_dev;
++	priv->netdev = netdev;
++
++	SET_NETDEV_DEV(netdev, dev);
++
++#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
++	snprintf(netdev->name, IFNAMSIZ, "mac%d", mc_dev->obj_desc.id);
++#endif
++
++	dev_set_drvdata(dev, priv);
++
++	/* We may need to issue MC commands while in atomic context */
++	err = fsl_mc_portal_allocate(mc_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
++				     &mc_dev->mc_io);
++	if (err || !mc_dev->mc_io) {
++		dev_dbg(dev, "fsl_mc_portal_allocate error: %d\n", err);
++		err = -EPROBE_DEFER;
++		goto err_free_netdev;
++	}
++
++	err = dpmac_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id,
++			 &mc_dev->mc_handle);
++	if (err || !mc_dev->mc_handle) {
++		dev_err(dev, "dpmac_open error: %d\n", err);
++		err = -ENODEV;
++		goto err_free_mcp;
++	}
++
++	err = dpmac_get_attributes(mc_dev->mc_io, 0,
++				   mc_dev->mc_handle, &priv->attr);
++	if (err) {
++		dev_err(dev, "dpmac_get_attributes err %d\n", err);
++		err = -EINVAL;
++		goto err_close;
++	}
++
++	/* Look up the DPMAC node in the device-tree. */
++	dpmac_node = find_dpmac_node(dev, priv->attr.id);
++	if (!dpmac_node) {
++		dev_err(dev, "No dpmac@%d subnode found.\n", priv->attr.id);
++		err = -ENODEV;
++		goto err_close;
++	}
++
++	err = setup_irqs(mc_dev);
++	if (err) {
++		err = -EFAULT;
++		goto err_close;
++	}
++
++#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
++	/* OPTIONAL, register netdev just to make it visible to the user */
++	netdev->netdev_ops = &dpaa2_mac_ndo_ops;
++	netdev->ethtool_ops = &dpaa2_mac_ethtool_ops;
++
++	/* phy starts up enabled so netdev should be up too */
++	netdev->flags |= IFF_UP;
++
++	err = register_netdev(priv->netdev);
++	if (err < 0) {
++		dev_err(dev, "register_netdev error %d\n", err);
++		err = -ENODEV;
++		goto err_free_irq;
++	}
++#endif /* CONFIG_FSL_DPAA2_MAC_NETDEVS */
++
++	/* probe the PHY as a fixed-link if there's a phy-handle defined
++	 * in the device tree
++	 */
++	phy_node = of_parse_phandle(dpmac_node, "phy-handle", 0);
++	if (!phy_node) {
++		goto probe_fixed_link;
++	}
++
++	if (priv->attr.eth_if < ARRAY_SIZE(dpaa2_mac_iface_mode)) {
++		if_mode = dpaa2_mac_iface_mode[priv->attr.eth_if];
++		dev_dbg(dev, "\tusing if mode %s for eth_if %d\n",
++			phy_modes(if_mode), priv->attr.eth_if);
++	} else {
++		dev_warn(dev, "Unexpected interface mode %d, will probe as fixed link\n",
++			 priv->attr.eth_if);
++		goto probe_fixed_link;
++	}
++
++	/* try to connect to the PHY */
++	netdev->phydev = of_phy_connect(netdev, phy_node,
++					&dpaa2_mac_link_changed, 0, if_mode);
++	if (!netdev->phydev) {
++		/* No need for dev_err(); the kernel's loud enough as it is. */
++		dev_dbg(dev, "Can't of_phy_connect() now.\n");
++		/* We might be waiting for the MDIO MUX to probe, so defer
++		 * our own probing.
++		 */
++		err = -EPROBE_DEFER;
++		goto err_defer;
++	}
++	dev_info(dev, "Connected to %s PHY.\n", phy_modes(if_mode));
++
++probe_fixed_link:
++	if (!netdev->phydev) {
++		struct fixed_phy_status status = {
++			.link = 1,
++			/* fixed-phys don't support 10Gbps speed for now */
++			.speed = 1000,
++			.duplex = 1,
++		};
++
++		/* try to register a fixed link phy */
++		netdev->phydev = fixed_phy_register(PHY_POLL, &status, -1,
++						    NULL);
++		if (!netdev->phydev || IS_ERR(netdev->phydev)) {
++			dev_err(dev, "error trying to register fixed PHY\n");
++			/* So we don't crash unregister_netdev() later on */
++			netdev->phydev = NULL;
++			err = -EFAULT;
++			goto err_no_phy;
++		}
++		dev_info(dev, "Registered fixed PHY.\n");
++	}
++
++	dpaa2_mac_open(netdev);
++
++	return 0;
++
++err_defer:
++err_no_phy:
++#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
++	unregister_netdev(netdev);
++err_free_irq:
++#endif
++	teardown_irqs(mc_dev);
++err_close:
++	dpmac_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
++err_free_mcp:
++	fsl_mc_portal_free(mc_dev->mc_io);
++err_free_netdev:
++	free_netdev(netdev);
++err_exit:
++	return err;
++}
++
++static int dpaa2_mac_remove(struct fsl_mc_device *mc_dev)
++{
++	struct device		*dev = &mc_dev->dev;
++	struct dpaa2_mac_priv	*priv = dev_get_drvdata(dev);
++	struct net_device	*netdev = priv->netdev;
++
++	dpaa2_mac_stop(netdev);
++
++	if (phy_is_pseudo_fixed_link(netdev->phydev))
++		fixed_phy_unregister(netdev->phydev);
++	else
++		phy_disconnect(netdev->phydev);
++	netdev->phydev = NULL;
++
++#ifdef CONFIG_FSL_DPAA2_MAC_NETDEVS
++	unregister_netdev(priv->netdev);
++#endif
++	teardown_irqs(priv->mc_dev);
++	dpmac_close(priv->mc_dev->mc_io, 0, priv->mc_dev->mc_handle);
++	fsl_mc_portal_free(priv->mc_dev->mc_io);
++	free_netdev(priv->netdev);
++
++	dev_set_drvdata(dev, NULL);
++
++	return 0;
++}
++
++static const struct fsl_mc_device_id dpaa2_mac_match_id_table[] = {
++	{
++		.vendor = FSL_MC_VENDOR_FREESCALE,
++		.obj_type = "dpmac",
++	},
++	{ .vendor = 0x0 }
++};
++MODULE_DEVICE_TABLE(fslmc, dpaa2_mac_match_id_table);
++
++static struct fsl_mc_driver dpaa2_mac_drv = {
++	.driver = {
++		.name		= KBUILD_MODNAME,
++		.owner		= THIS_MODULE,
++	},
++	.probe		= dpaa2_mac_probe,
++	.remove		= dpaa2_mac_remove,
++	.match_id_table = dpaa2_mac_match_id_table,
++};
++
++module_fsl_mc_driver(dpaa2_mac_drv);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("DPAA2 PHY proxy interface driver");
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/rtc/Makefile
+@@ -0,0 +1,10 @@
++
++obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += dpaa2-rtc.o
++
++dpaa2-rtc-objs := rtc.o dprtc.o
++
++all:
++	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
++
++clean:
++	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/rtc/dprtc-cmd.h
+@@ -0,0 +1,160 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef _FSL_DPRTC_CMD_H
++#define _FSL_DPRTC_CMD_H
++
++/* DPRTC Version */
++#define DPRTC_VER_MAJOR			2
++#define DPRTC_VER_MINOR			0
++
++/* Command versioning */
++#define DPRTC_CMD_BASE_VERSION		1
++#define DPRTC_CMD_ID_OFFSET		4
++
++#define DPRTC_CMD(id)	(((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_BASE_VERSION)
++
++/* Command IDs */
++#define DPRTC_CMDID_CLOSE			DPRTC_CMD(0x800)
++#define DPRTC_CMDID_OPEN			DPRTC_CMD(0x810)
++#define DPRTC_CMDID_CREATE			DPRTC_CMD(0x910)
++#define DPRTC_CMDID_DESTROY			DPRTC_CMD(0x990)
++#define DPRTC_CMDID_GET_API_VERSION		DPRTC_CMD(0xa10)
++
++#define DPRTC_CMDID_ENABLE			DPRTC_CMD(0x002)
++#define DPRTC_CMDID_DISABLE			DPRTC_CMD(0x003)
++#define DPRTC_CMDID_GET_ATTR			DPRTC_CMD(0x004)
++#define DPRTC_CMDID_RESET			DPRTC_CMD(0x005)
++#define DPRTC_CMDID_IS_ENABLED			DPRTC_CMD(0x006)
++
++#define DPRTC_CMDID_SET_IRQ_ENABLE		DPRTC_CMD(0x012)
++#define DPRTC_CMDID_GET_IRQ_ENABLE		DPRTC_CMD(0x013)
++#define DPRTC_CMDID_SET_IRQ_MASK		DPRTC_CMD(0x014)
++#define DPRTC_CMDID_GET_IRQ_MASK		DPRTC_CMD(0x015)
++#define DPRTC_CMDID_GET_IRQ_STATUS		DPRTC_CMD(0x016)
++#define DPRTC_CMDID_CLEAR_IRQ_STATUS		DPRTC_CMD(0x017)
++
++#define DPRTC_CMDID_SET_CLOCK_OFFSET		DPRTC_CMD(0x1d0)
++#define DPRTC_CMDID_SET_FREQ_COMPENSATION	DPRTC_CMD(0x1d1)
++#define DPRTC_CMDID_GET_FREQ_COMPENSATION	DPRTC_CMD(0x1d2)
++#define DPRTC_CMDID_GET_TIME			DPRTC_CMD(0x1d3)
++#define DPRTC_CMDID_SET_TIME			DPRTC_CMD(0x1d4)
++#define DPRTC_CMDID_SET_ALARM			DPRTC_CMD(0x1d5)
++#define DPRTC_CMDID_SET_PERIODIC_PULSE		DPRTC_CMD(0x1d6)
++#define DPRTC_CMDID_CLEAR_PERIODIC_PULSE	DPRTC_CMD(0x1d7)
++#define DPRTC_CMDID_SET_EXT_TRIGGER		DPRTC_CMD(0x1d8)
++#define DPRTC_CMDID_CLEAR_EXT_TRIGGER		DPRTC_CMD(0x1d9)
++#define DPRTC_CMDID_GET_EXT_TRIGGER_TIMESTAMP	DPRTC_CMD(0x1dA)
++
++/* Macros for accessing command fields smaller than 1byte */
++#define DPRTC_MASK(field)        \
++	GENMASK(DPRTC_##field##_SHIFT + DPRTC_##field##_SIZE - 1, \
++		DPRTC_##field##_SHIFT)
++#define dprtc_get_field(var, field)      \
++	(((var) & DPRTC_MASK(field)) >> DPRTC_##field##_SHIFT)
++
++#pragma pack(push, 1)
++struct dprtc_cmd_open {
++	uint32_t dprtc_id;
++};
++
++struct dprtc_cmd_destroy {
++	uint32_t object_id;
++};
++
++#define DPRTC_ENABLE_SHIFT	0
++#define DPRTC_ENABLE_SIZE	1
++
++struct dprtc_rsp_is_enabled {
++	uint8_t en;
++};
++
++struct dprtc_cmd_get_irq {
++	uint32_t pad;
++	uint8_t irq_index;
++};
++
++struct dprtc_cmd_set_irq_enable {
++	uint8_t en;
++	uint8_t pad[3];
++	uint8_t irq_index;
++};
++
++struct dprtc_rsp_get_irq_enable {
++	uint8_t en;
++};
++
++struct dprtc_cmd_set_irq_mask {
++	uint32_t mask;
++	uint8_t irq_index;
++};
++
++struct dprtc_rsp_get_irq_mask {
++	uint32_t mask;
++};
++
++struct dprtc_cmd_get_irq_status {
++	uint32_t status;
++	uint8_t irq_index;
++};
++
++struct dprtc_rsp_get_irq_status {
++	uint32_t status;
++};
++
++struct dprtc_cmd_clear_irq_status {
++	uint32_t status;
++	uint8_t irq_index;
++};
++
++struct dprtc_rsp_get_attributes {
++	uint32_t pad;
++	uint32_t id;
++};
++
++struct dprtc_cmd_set_clock_offset {
++	uint64_t offset;
++};
++
++struct dprtc_get_freq_compensation {
++	uint32_t freq_compensation;
++};
++
++struct dprtc_time {
++	uint64_t time;
++};
++
++struct dprtc_rsp_get_api_version {
++	uint16_t major;
++	uint16_t minor;
++};
++#pragma pack(pop)
++#endif /* _FSL_DPRTC_CMD_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/rtc/dprtc.c
+@@ -0,0 +1,746 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#include <linux/fsl/mc.h>
++
++#include "dprtc.h"
++#include "dprtc-cmd.h"
++
++/**
++ * dprtc_open() - Open a control session for the specified object.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @dprtc_id:	DPRTC unique ID
++ * @token:	Returned token; use in subsequent API calls
++ *
++ * This function can be used to open a control session for an
++ * already created object; an object may have been declared in
++ * the DPL or by calling the dprtc_create function.
++ * This function returns a unique authentication token,
++ * associated with the specific object ID and the specific MC
++ * portal; this token must be used in all subsequent commands for
++ * this specific object
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_open(struct fsl_mc_io *mc_io,
++	       uint32_t cmd_flags,
++	       int dprtc_id,
++	       uint16_t *token)
++{
++	struct dprtc_cmd_open *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_OPEN,
++					  cmd_flags,
++					  0);
++	cmd_params = (struct dprtc_cmd_open *)cmd.params;
++	cmd_params->dprtc_id = cpu_to_le32(dprtc_id);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*token = mc_cmd_hdr_read_token(&cmd);
++
++	return err;
++}
++
++/**
++ * dprtc_close() - Close the control session of the object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ *
++ * After this function is called, no further operations are
++ * allowed on the object without opening a new control session.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_close(struct fsl_mc_io *mc_io,
++		uint32_t cmd_flags,
++		uint16_t token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLOSE, cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_create() - Create the DPRTC object.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @dprc_token:	Parent container token; '0' for default container
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @cfg:	Configuration structure
++ * @obj_id:	Returned object id
++ *
++ * Create the DPRTC object, allocate required resources and
++ * perform required initialization.
++ *
++ * The function accepts an authentication token of a parent
++ * container that this object should be assigned to. The token
++ * can be '0' so the object will be assigned to the default container.
++ * The newly created object can be opened with the returned
++ * object id and using the container's associated tokens and MC portals.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_create(struct fsl_mc_io *mc_io,
++		 uint16_t dprc_token,
++		 uint32_t cmd_flags,
++		 const struct dprtc_cfg *cfg,
++		 uint32_t *obj_id)
++{
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	(void)(cfg); /* unused */
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CREATE,
++					  cmd_flags,
++					  dprc_token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	*obj_id = mc_cmd_read_object_id(&cmd);
++
++	return 0;
++}
++
++/**
++ * dprtc_destroy() - Destroy the DPRTC object and release all its resources.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @dprc_token: Parent container token; '0' for default container
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @object_id:	The object id; it must be a valid id within the container that
++ * created this object;
++ *
++ * The function accepts the authentication token of the parent container that
++ * created the object (not the one that currently owns the object). The object
++ * is searched within parent using the provided 'object_id'.
++ * All tokens to the object must be closed before calling destroy.
++ *
++ * Return:	'0' on Success; error code otherwise.
++ */
++int dprtc_destroy(struct fsl_mc_io *mc_io,
++		  uint16_t dprc_token,
++		  uint32_t cmd_flags,
++		  uint32_t object_id)
++{
++	struct dprtc_cmd_destroy *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_DESTROY,
++					  cmd_flags,
++					  dprc_token);
++	cmd_params = (struct dprtc_cmd_destroy *)cmd.params;
++	cmd_params->object_id = cpu_to_le32(object_id);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++int dprtc_enable(struct fsl_mc_io *mc_io,
++		 uint32_t cmd_flags,
++		 uint16_t token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_ENABLE, cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++int dprtc_disable(struct fsl_mc_io *mc_io,
++		  uint32_t cmd_flags,
++		  uint16_t token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_DISABLE,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++int dprtc_is_enabled(struct fsl_mc_io *mc_io,
++		     uint32_t cmd_flags,
++		     uint16_t token,
++		     int *en)
++{
++	struct dprtc_rsp_is_enabled *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_IS_ENABLED, cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dprtc_rsp_is_enabled *)cmd.params;
++	*en = dprtc_get_field(rsp_params->en, ENABLE);
++
++	return 0;
++}
++
++int dprtc_reset(struct fsl_mc_io *mc_io,
++		uint32_t cmd_flags,
++		uint16_t token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_RESET,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_set_irq_enable() - Set overall interrupt state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Interrupt state - enable = 1, disable = 0
++ *
++ * Allows GPP software to control when interrupts are generated.
++ * Each interrupt can have up to 32 causes.  The enable/disable control's the
++ * overall interrupt state. if the interrupt is disabled no causes will cause
++ * an interrupt.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
++			 uint32_t cmd_flags,
++			 uint16_t token,
++			 uint8_t irq_index,
++			 uint8_t en)
++{
++	struct dprtc_cmd_set_irq_enable *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_cmd_set_irq_enable *)cmd.params;
++	cmd_params->irq_index = irq_index;
++	cmd_params->en = en;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_get_irq_enable() - Get overall interrupt state
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Returned interrupt state - enable = 1, disable = 0
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
++			 uint32_t cmd_flags,
++			 uint16_t token,
++			 uint8_t irq_index,
++			 uint8_t *en)
++{
++	struct dprtc_rsp_get_irq_enable *rsp_params;
++	struct dprtc_cmd_get_irq *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_cmd_get_irq *)cmd.params;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dprtc_rsp_get_irq_enable *)cmd.params;
++	*en = rsp_params->en;
++
++	return 0;
++}
++
++/**
++ * dprtc_set_irq_mask() - Set interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	Event mask to trigger interrupt;
++ *		each bit:
++ *			0 = ignore event
++ *			1 = consider event for asserting IRQ
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
++		       uint32_t cmd_flags,
++		       uint16_t token,
++		       uint8_t irq_index,
++		       uint32_t mask)
++{
++	struct dprtc_cmd_set_irq_mask *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_cmd_set_irq_mask *)cmd.params;
++	cmd_params->mask = cpu_to_le32(mask);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_get_irq_mask() - Get interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	Returned event mask to trigger interrupt
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
++		       uint32_t cmd_flags,
++		       uint16_t token,
++		       uint8_t irq_index,
++		       uint32_t *mask)
++{
++	struct dprtc_rsp_get_irq_mask *rsp_params;
++	struct dprtc_cmd_get_irq *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_cmd_get_irq *)cmd.params;
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dprtc_rsp_get_irq_mask *)cmd.params;
++	*mask = le32_to_cpu(rsp_params->mask);
++
++	return 0;
++}
++
++/**
++ * dprtc_get_irq_status() - Get the current status of any pending interrupts.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @irq_index:	The interrupt index to configure
++ * @status:	Returned interrupts status - one bit per cause:
++ *			0 = no interrupt pending
++ *			1 = interrupt pending
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
++			 uint32_t cmd_flags,
++			 uint16_t token,
++			 uint8_t irq_index,
++			 uint32_t *status)
++{
++	struct dprtc_cmd_get_irq_status *cmd_params;
++	struct dprtc_rsp_get_irq_status *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_cmd_get_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(*status);
++	cmd_params->irq_index = irq_index;
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dprtc_rsp_get_irq_status *)cmd.params;
++	*status = rsp_params->status;
++
++	return 0;
++}
++
++/**
++ * dprtc_clear_irq_status() - Clear a pending interrupt's status
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @irq_index:	The interrupt index to configure
++ * @status:	Bits to clear (W1C) - one bit per cause:
++ *			0 = don't change
++ *			1 = clear status bit
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
++			   uint32_t cmd_flags,
++			   uint16_t token,
++			   uint8_t irq_index,
++			   uint32_t status)
++{
++	struct dprtc_cmd_clear_irq_status *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_CLEAR_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_cmd_clear_irq_status *)cmd.params;
++	cmd_params->irq_index = irq_index;
++	cmd_params->status = cpu_to_le32(status);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_get_attributes - Retrieve DPRTC attributes.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @attr:	Returned object's attributes
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_get_attributes(struct fsl_mc_io *mc_io,
++			 uint32_t cmd_flags,
++			 uint16_t token,
++			 struct dprtc_attr *attr)
++{
++	struct dprtc_rsp_get_attributes *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_ATTR,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dprtc_rsp_get_attributes *)cmd.params;
++	attr->id = le32_to_cpu(rsp_params->id);
++
++	return 0;
++}
++
++/**
++ * dprtc_set_clock_offset() - Sets the clock's offset
++ * (usually relative to another clock).
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @offset:	New clock offset (in nanoseconds).
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_set_clock_offset(struct fsl_mc_io *mc_io,
++			   uint32_t cmd_flags,
++			   uint16_t token,
++			   int64_t offset)
++{
++	struct dprtc_cmd_set_clock_offset *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_CLOCK_OFFSET,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_cmd_set_clock_offset *)cmd.params;
++	cmd_params->offset = cpu_to_le64(offset);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_set_freq_compensation() - Sets a new frequency compensation value.
++ *
++ * @mc_io:		Pointer to MC portal's I/O object
++ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:		Token of DPRTC object
++ * @freq_compensation:	The new frequency compensation value to set.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
++				uint32_t cmd_flags,
++				uint16_t token,
++				uint32_t freq_compensation)
++{
++	struct dprtc_get_freq_compensation *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_FREQ_COMPENSATION,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_get_freq_compensation *)cmd.params;
++	cmd_params->freq_compensation = cpu_to_le32(freq_compensation);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_get_freq_compensation() - Retrieves the frequency compensation value
++ *
++ * @mc_io:		Pointer to MC portal's I/O object
++ * @cmd_flags:		Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:		Token of DPRTC object
++ * @freq_compensation:	Frequency compensation value
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io,
++				uint32_t cmd_flags,
++				uint16_t token,
++				uint32_t *freq_compensation)
++{
++	struct dprtc_get_freq_compensation *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_FREQ_COMPENSATION,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dprtc_get_freq_compensation *)cmd.params;
++	*freq_compensation = le32_to_cpu(rsp_params->freq_compensation);
++
++	return 0;
++}
++
++/**
++ * dprtc_get_time() - Returns the current RTC time.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @time:	Current RTC time.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_get_time(struct fsl_mc_io *mc_io,
++		   uint32_t cmd_flags,
++		   uint16_t token,
++		   uint64_t *time)
++{
++	struct dprtc_time *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_TIME,
++					  cmd_flags,
++					  token);
++
++	/* send command to mc*/
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	/* retrieve response parameters */
++	rsp_params = (struct dprtc_time *)cmd.params;
++	*time = le64_to_cpu(rsp_params->time);
++
++	return 0;
++}
++
++/**
++ * dprtc_set_time() - Updates current RTC time.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @time:	New RTC time.
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_set_time(struct fsl_mc_io *mc_io,
++		   uint32_t cmd_flags,
++		   uint16_t token,
++		   uint64_t time)
++{
++	struct dprtc_time *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_TIME,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_time *)cmd.params;
++	cmd_params->time = cpu_to_le64(time);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_set_alarm() - Defines and sets alarm.
++ *
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPRTC object
++ * @time:	In nanoseconds, the time when the alarm
++ *			should go off - must be a multiple of
++ *			1 microsecond
++ *
++ * Return:	'0' on Success; Error code otherwise.
++ */
++int dprtc_set_alarm(struct fsl_mc_io *mc_io,
++		    uint32_t cmd_flags,
++		    uint16_t token, uint64_t time)
++{
++	struct dprtc_time *cmd_params;
++	struct fsl_mc_command cmd = { 0 };
++
++	/* prepare command */
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_SET_ALARM,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dprtc_time *)cmd.params;
++	cmd_params->time = cpu_to_le64(time);
++
++	/* send command to mc*/
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dprtc_get_api_version() - Get Data Path Real Time Counter API version
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @major_ver:	Major version of data path real time counter API
++ * @minor_ver:	Minor version of data path real time counter API
++ *
++ * Return:  '0' on Success; Error code otherwise.
++ */
++int dprtc_get_api_version(struct fsl_mc_io *mc_io,
++			  uint32_t cmd_flags,
++			  uint16_t *major_ver,
++			  uint16_t *minor_ver)
++{
++	struct dprtc_rsp_get_api_version *rsp_params;
++	struct fsl_mc_command cmd = { 0 };
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPRTC_CMDID_GET_API_VERSION,
++					cmd_flags,
++					0);
++
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dprtc_rsp_get_api_version *)cmd.params;
++	*major_ver = le16_to_cpu(rsp_params->major);
++	*minor_ver = le16_to_cpu(rsp_params->minor);
++
++	return 0;
++}
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/rtc/dprtc.h
+@@ -0,0 +1,172 @@
++/* Copyright 2013-2016 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef __FSL_DPRTC_H
++#define __FSL_DPRTC_H
++
++/* Data Path Real Time Counter API
++ * Contains initialization APIs and runtime control APIs for RTC
++ */
++
++struct fsl_mc_io;
++
++/**
++ * Number of irq's
++ */
++#define DPRTC_MAX_IRQ_NUM			1
++#define DPRTC_IRQ_INDEX				0
++
++/**
++ * Interrupt event masks:
++ */
++
++/**
++ * Interrupt event mask indicating alarm event had occurred
++ */
++#define DPRTC_EVENT_ALARM			0x40000000
++/**
++ * Interrupt event mask indicating periodic pulse event had occurred
++ */
++#define DPRTC_EVENT_PPS				0x08000000
++
++int dprtc_open(struct fsl_mc_io *mc_io,
++	       uint32_t cmd_flags,
++	       int dprtc_id,
++	       uint16_t *token);
++
++int dprtc_close(struct fsl_mc_io *mc_io,
++		uint32_t cmd_flags,
++		uint16_t token);
++
++/**
++ * struct dprtc_cfg - Structure representing DPRTC configuration
++ * @options:	place holder
++ */
++struct dprtc_cfg {
++	uint32_t options;
++};
++
++int dprtc_create(struct fsl_mc_io *mc_io,
++		 uint16_t dprc_token,
++		 uint32_t cmd_flags,
++		 const struct dprtc_cfg *cfg,
++		 uint32_t *obj_id);
++
++int dprtc_destroy(struct fsl_mc_io *mc_io,
++		  uint16_t dprc_token,
++		  uint32_t cmd_flags,
++		  uint32_t object_id);
++
++int dprtc_set_clock_offset(struct fsl_mc_io *mc_io,
++			   uint32_t cmd_flags,
++			   uint16_t token,
++			   int64_t offset);
++
++int dprtc_set_freq_compensation(struct fsl_mc_io *mc_io,
++		  uint32_t cmd_flags,
++		  uint16_t token,
++		  uint32_t freq_compensation);
++
++int dprtc_get_freq_compensation(struct fsl_mc_io *mc_io,
++		  uint32_t cmd_flags,
++		  uint16_t token,
++		  uint32_t *freq_compensation);
++
++int dprtc_get_time(struct fsl_mc_io *mc_io,
++		   uint32_t cmd_flags,
++		   uint16_t token,
++		   uint64_t *time);
++
++int dprtc_set_time(struct fsl_mc_io *mc_io,
++		   uint32_t cmd_flags,
++		   uint16_t token,
++		   uint64_t time);
++
++int dprtc_set_alarm(struct fsl_mc_io *mc_io,
++		    uint32_t cmd_flags,
++		    uint16_t token,
++		    uint64_t time);
++
++int dprtc_set_irq_enable(struct fsl_mc_io *mc_io,
++			 uint32_t cmd_flags,
++			 uint16_t token,
++			 uint8_t irq_index,
++			 uint8_t en);
++
++int dprtc_get_irq_enable(struct fsl_mc_io *mc_io,
++			 uint32_t cmd_flags,
++			 uint16_t token,
++			 uint8_t irq_index,
++			 uint8_t *en);
++
++int dprtc_set_irq_mask(struct fsl_mc_io *mc_io,
++		       uint32_t cmd_flags,
++		       uint16_t token,
++		       uint8_t irq_index,
++		       uint32_t mask);
++
++int dprtc_get_irq_mask(struct fsl_mc_io *mc_io,
++		       uint32_t cmd_flags,
++		       uint16_t token,
++		       uint8_t irq_index,
++		       uint32_t *mask);
++
++int dprtc_get_irq_status(struct fsl_mc_io *mc_io,
++			 uint32_t cmd_flags,
++			 uint16_t token,
++			 uint8_t irq_index,
++			 uint32_t *status);
++
++int dprtc_clear_irq_status(struct fsl_mc_io *mc_io,
++			   uint32_t cmd_flags,
++			   uint16_t token,
++			   uint8_t irq_index,
++			   uint32_t status);
++
++/**
++ * struct dprtc_attr - Structure representing DPRTC attributes
++ * @id:		DPRTC object ID
++ */
++struct dprtc_attr {
++	int id;
++};
++
++int dprtc_get_attributes(struct fsl_mc_io *mc_io,
++			 uint32_t cmd_flags,
++			 uint16_t token,
++			 struct dprtc_attr *attr);
++
++int dprtc_get_api_version(struct fsl_mc_io *mc_io,
++			  uint32_t cmd_flags,
++			  uint16_t *major_ver,
++			  uint16_t *minor_ver);
++
++#endif /* __FSL_DPRTC_H */
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/rtc/rtc.c
+@@ -0,0 +1,242 @@
++/* Copyright 2013-2015 Freescale Semiconductor Inc.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of the above-listed copyright holders nor the
++ * names of any contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/module.h>
++#include <linux/ptp_clock_kernel.h>
++
++#include <linux/fsl/mc.h>
++
++#include "dprtc.h"
++#include "dprtc-cmd.h"
++
++#define N_EXT_TS	2
++
++struct ptp_clock *clock;
++struct fsl_mc_device *rtc_mc_dev;
++u32 freqCompensation;
++
++/* PTP clock operations */
++static int ptp_dpaa2_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
++{
++	u64 adj;
++	u32 diff, tmr_add;
++	int neg_adj = 0;
++	int err = 0;
++	struct fsl_mc_device *mc_dev = rtc_mc_dev;
++	struct device *dev = &mc_dev->dev;
++
++	if (ppb < 0) {
++		neg_adj = 1;
++		ppb = -ppb;
++	}
++
++	tmr_add = freqCompensation;
++	adj = tmr_add;
++	adj *= ppb;
++	diff = div_u64(adj, 1000000000ULL);
++
++	tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
++
++	err = dprtc_set_freq_compensation(mc_dev->mc_io, 0,
++					  mc_dev->mc_handle, tmr_add);
++	if (err)
++		dev_err(dev, "dprtc_set_freq_compensation err %d\n", err);
++	return 0;
++}
++
++static int ptp_dpaa2_adjtime(struct ptp_clock_info *ptp, s64 delta)
++{
++	s64 now;
++	int err = 0;
++	struct fsl_mc_device *mc_dev = rtc_mc_dev;
++	struct device *dev = &mc_dev->dev;
++
++	err = dprtc_get_time(mc_dev->mc_io, 0, mc_dev->mc_handle, &now);
++	if (err) {
++		dev_err(dev, "dprtc_get_time err %d\n", err);
++		return 0;
++	}
++
++	now += delta;
++
++	err = dprtc_set_time(mc_dev->mc_io, 0, mc_dev->mc_handle, now);
++	if (err) {
++		dev_err(dev, "dprtc_set_time err %d\n", err);
++		return 0;
++	}
++	return 0;
++}
++
++static int ptp_dpaa2_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
++{
++	u64 ns;
++	u32 remainder;
++	int err = 0;
++	struct fsl_mc_device *mc_dev = rtc_mc_dev;
++	struct device *dev = &mc_dev->dev;
++
++	err = dprtc_get_time(mc_dev->mc_io, 0, mc_dev->mc_handle, &ns);
++	if (err) {
++		dev_err(dev, "dprtc_get_time err %d\n", err);
++		return 0;
++	}
++
++	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
++	ts->tv_nsec = remainder;
++	return 0;
++}
++
++static int ptp_dpaa2_settime(struct ptp_clock_info *ptp,
++			       const struct timespec *ts)
++{
++	u64 ns;
++	int err = 0;
++	struct fsl_mc_device *mc_dev = rtc_mc_dev;
++	struct device *dev = &mc_dev->dev;
++
++	ns = ts->tv_sec * 1000000000ULL;
++	ns += ts->tv_nsec;
++
++	err = dprtc_set_time(mc_dev->mc_io, 0, mc_dev->mc_handle, ns);
++	if (err)
++		dev_err(dev, "dprtc_set_time err %d\n", err);
++	return 0;
++}
++
++static struct ptp_clock_info ptp_dpaa2_caps = {
++	.owner		= THIS_MODULE,
++	.name		= "dpaa2 clock",
++	.max_adj	= 512000,
++	.n_alarm	= 0,
++	.n_ext_ts	= N_EXT_TS,
++	.n_per_out	= 0,
++	.n_pins		= 0,
++	.pps		= 1,
++	.adjfreq	= ptp_dpaa2_adjfreq,
++	.adjtime	= ptp_dpaa2_adjtime,
++	.gettime64	= ptp_dpaa2_gettime,
++	.settime64	= ptp_dpaa2_settime,
++};
++
++static int rtc_probe(struct fsl_mc_device *mc_dev)
++{
++	struct device		*dev;
++	int			err = 0;
++	int			dpaa2_phc_index;
++	u32			tmr_add = 0;
++
++	if (!mc_dev)
++		return -EFAULT;
++
++	dev = &mc_dev->dev;
++
++	err = fsl_mc_portal_allocate(mc_dev, 0, &mc_dev->mc_io);
++	if (unlikely(err)) {
++		dev_err(dev, "fsl_mc_portal_allocate err %d\n", err);
++		goto err_exit;
++	}
++	if (!mc_dev->mc_io) {
++		dev_err(dev,
++			"fsl_mc_portal_allocate returned null handle but no error\n");
++		err = -EFAULT;
++		goto err_exit;
++	}
++
++	err = dprtc_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id,
++			 &mc_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dprtc_open err %d\n", err);
++		goto err_free_mcp;
++	}
++	if (!mc_dev->mc_handle) {
++		dev_err(dev, "dprtc_open returned null handle but no error\n");
++		err = -EFAULT;
++		goto err_free_mcp;
++	}
++
++	rtc_mc_dev = mc_dev;
++
++	err = dprtc_get_freq_compensation(mc_dev->mc_io, 0,
++					  mc_dev->mc_handle, &tmr_add);
++	if (err) {
++		dev_err(dev, "dprtc_get_freq_compensation err %d\n", err);
++		goto err_close;
++	}
++	freqCompensation = tmr_add;
++
++	clock = ptp_clock_register(&ptp_dpaa2_caps, dev);
++	if (IS_ERR(clock)) {
++		err = PTR_ERR(clock);
++		goto err_close;
++	}
++	dpaa2_phc_index = ptp_clock_index(clock);
++
++	return 0;
++err_close:
++	dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
++err_free_mcp:
++	fsl_mc_portal_free(mc_dev->mc_io);
++err_exit:
++	return err;
++}
++
++static int rtc_remove(struct fsl_mc_device *mc_dev)
++{
++	ptp_clock_unregister(clock);
++	dprtc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
++	fsl_mc_portal_free(mc_dev->mc_io);
++
++	return 0;
++}
++
++static const struct fsl_mc_device_id rtc_match_id_table[] = {
++	{
++		.vendor = FSL_MC_VENDOR_FREESCALE,
++		.obj_type = "dprtc",
++	},
++	{}
++};
++
++static struct fsl_mc_driver rtc_drv = {
++	.driver = {
++		.name		= KBUILD_MODNAME,
++		.owner		= THIS_MODULE,
++	},
++	.probe		= rtc_probe,
++	.remove		= rtc_remove,
++	.match_id_table = rtc_match_id_table,
++};
++
++module_fsl_mc_driver(rtc_drv);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("DPAA2 RTC (PTP 1588 clock) driver (prototype)");
+--- a/include/linux/filter.h
++++ b/include/linux/filter.h
+@@ -429,12 +429,15 @@ struct sk_filter {
+ 
+ struct bpf_skb_data_end {
+ 	struct qdisc_skb_cb qdisc_cb;
++	void *data_meta;
+ 	void *data_end;
+ };
+ 
+ struct xdp_buff {
+ 	void *data;
+ 	void *data_end;
++	void *data_meta;
++	void *data_hard_start;
+ };
+ 
+ /* compute the linear packet data range [data, data_end) which
diff --git a/target/linux/layerscape/patches-4.14/710-pfe-eth-support-layerscape.patch b/target/linux/layerscape/patches-4.9/706-fsl_ppfe-support-layercape.patch
similarity index 97%
rename from target/linux/layerscape/patches-4.14/710-pfe-eth-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/706-fsl_ppfe-support-layercape.patch
index ae64527f3..e71c85c7f 100644
--- a/target/linux/layerscape/patches-4.14/710-pfe-eth-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/706-fsl_ppfe-support-layercape.patch
@@ -1,21 +1,13 @@
-From 93febc09be23aa75cbc5bf5e76250c923f4004e5 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:59 +0800
-Subject: [PATCH 16/40] pfe-eth: support layerscape
-This is an integrated patch of pfe-eth for layerscape
+From 50fb2f2e93aeae0baed156eb4794a2f358376b77 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:19:20 +0800
+Subject: [PATCH 12/32] fsl_ppfe: support layercape
 
-Signed-off-by: Akhila Kavi <akhila.kavi@nxp.com>
-Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
-Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
-Signed-off-by: Archana Madhavan <archana.madhavan@nxp.com>
-Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
-Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
-Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
+This is an integrated patch for layerscape pfe support.
+
+Calvin Johnson <calvin.johnson@nxp.com>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
 ---
- .../devicetree/bindings/net/fsl_ppfe/pfe.txt  |  173 ++
  drivers/staging/fsl_ppfe/Kconfig              |   20 +
  drivers/staging/fsl_ppfe/Makefile             |   19 +
  drivers/staging/fsl_ppfe/TODO                 |    2 +
@@ -28,30 +20,29 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h     |   50 +
  .../fsl_ppfe/include/pfe/cbus/tmu_csr.h       |  168 ++
  .../fsl_ppfe/include/pfe/cbus/util_csr.h      |   61 +
- drivers/staging/fsl_ppfe/include/pfe/pfe.h    |  373 +++
+ drivers/staging/fsl_ppfe/include/pfe/pfe.h    |  372 +++
  drivers/staging/fsl_ppfe/pfe_ctrl.c           |  238 ++
  drivers/staging/fsl_ppfe/pfe_ctrl.h           |  112 +
  drivers/staging/fsl_ppfe/pfe_debugfs.c        |  111 +
  drivers/staging/fsl_ppfe/pfe_debugfs.h        |   25 +
- drivers/staging/fsl_ppfe/pfe_eth.c            | 2521 +++++++++++++++++
- drivers/staging/fsl_ppfe/pfe_eth.h            |  185 ++
- drivers/staging/fsl_ppfe/pfe_firmware.c       |  314 ++
+ drivers/staging/fsl_ppfe/pfe_eth.c            | 2491 +++++++++++++++++
+ drivers/staging/fsl_ppfe/pfe_eth.h            |  184 ++
+ drivers/staging/fsl_ppfe/pfe_firmware.c       |  314 +++
  drivers/staging/fsl_ppfe/pfe_firmware.h       |   32 +
- drivers/staging/fsl_ppfe/pfe_hal.c            | 1528 ++++++++++
+ drivers/staging/fsl_ppfe/pfe_hal.c            | 1516 ++++++++++
  drivers/staging/fsl_ppfe/pfe_hif.c            | 1072 +++++++
- drivers/staging/fsl_ppfe/pfe_hif.h            |  212 ++
+ drivers/staging/fsl_ppfe/pfe_hif.h            |  211 ++
  drivers/staging/fsl_ppfe/pfe_hif_lib.c        |  640 +++++
  drivers/staging/fsl_ppfe/pfe_hif_lib.h        |  241 ++
  drivers/staging/fsl_ppfe/pfe_hw.c             |  176 ++
  drivers/staging/fsl_ppfe/pfe_hw.h             |   27 +
  .../staging/fsl_ppfe/pfe_ls1012a_platform.c   |  385 +++
- drivers/staging/fsl_ppfe/pfe_mod.c            |  156 +
+ drivers/staging/fsl_ppfe/pfe_mod.c            |  156 ++
  drivers/staging/fsl_ppfe/pfe_mod.h            |  114 +
  drivers/staging/fsl_ppfe/pfe_perfmon.h        |   38 +
  drivers/staging/fsl_ppfe/pfe_sysfs.c          |  818 ++++++
  drivers/staging/fsl_ppfe/pfe_sysfs.h          |   29 +
- 35 files changed, 10690 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
+ 34 files changed, 10472 insertions(+)
  create mode 100644 drivers/staging/fsl_ppfe/Kconfig
  create mode 100644 drivers/staging/fsl_ppfe/Makefile
  create mode 100644 drivers/staging/fsl_ppfe/TODO
@@ -87,182 +78,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c
  create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h
 
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
-@@ -0,0 +1,173 @@
-+=============================================================================
-+NXP Programmable Packet Forwarding Engine Device Bindings
-+
-+CONTENTS
-+  - PFE Node
-+  - Ethernet Node
-+
-+=============================================================================
-+PFE Node
-+
-+DESCRIPTION
-+
-+PFE Node has all the properties associated with Packet Forwarding Engine block.
-+
-+PROPERTIES
-+
-+- compatible
-+		Usage: required
-+		Value type: <stringlist>
-+		Definition: Must include "fsl,pfe"
-+
-+- reg
-+		Usage: required
-+		Value type: <prop-encoded-array>
-+		Definition: A standard property.
-+		Specifies the offset of the following registers:
-+		- PFE configuration registers
-+		- DDR memory used by PFE
-+
-+- fsl,pfe-num-interfaces
-+		Usage: required
-+		Value type: <u32>
-+		Definition: Must be present. Value can be either one or two.
-+
-+- interrupts
-+		Usage: required
-+		Value type: <prop-encoded-array>
-+		Definition: Three interrupts are specified in this property.
-+		- HIF interrupt
-+		- HIF NO COPY interrupt
-+		- Wake On LAN interrupt
-+
-+- interrupt-names
-+		Usage: required
-+		Value type: <stringlist>
-+		Definition: Following strings are defined for the 3 interrupts.
-+		"pfe_hif" - HIF interrupt
-+		"pfe_hif_nocpy" - HIF NO COPY interrupt
-+		"pfe_wol" - Wake On LAN interrupt
-+
-+- memory-region
-+		Usage: required
-+		Value type: <phandle>
-+		Definition: phandle to a node describing reserved memory used by pfe.
-+		Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
-+
-+- fsl,pfe-scfg
-+		Usage: required
-+		Value type: <phandle>
-+		Definition: phandle for scfg.
-+
-+- fsl,rcpm-wakeup
-+		Usage: required
-+		Value type: <phandle>
-+		Definition: phandle for rcpm.
-+
-+- clocks
-+		Usage: required
-+		Value type: <phandle>
-+		Definition: phandle for clockgen.
-+
-+- clock-names
-+		Usage: required
-+		Value type: <string>
-+		Definition: phandle for clock name.
-+
-+EXAMPLE
-+
-+pfe: pfe@04000000 {
-+	compatible = "fsl,pfe";
-+	reg =   <0x0 0x04000000 0x0 0xc00000>,	/* AXI 16M */
-+		<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */
-+	reg-names = "pfe", "pfe-ddr";
-+	fsl,pfe-num-interfaces = <0x2>;
-+	interrupts = <0 172 0x4>,    /* HIF interrupt */
-+		     <0 173 0x4>,    /*HIF_NOCPY interrupt */
-+		     <0 174 0x4>;    /* WoL interrupt */
-+	interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
-+	memory-region = <&pfe_reserved>;
-+	fsl,pfe-scfg = <&scfg 0>;
-+	fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
-+	clocks = <&clockgen 4 0>;
-+	clock-names = "pfe";
-+
-+	status = "okay";
-+	pfe_mac0: ethernet@0 {
-+	};
-+
-+	pfe_mac1: ethernet@1 {
-+	};
-+};
-+
-+=============================================================================
-+Ethernet Node
-+
-+DESCRIPTION
-+
-+Ethernet Node has all the properties associated with PFE used by platforms to
-+connect to PHY:
-+
-+PROPERTIES
-+
-+- compatible
-+		Usage: required
-+		Value type: <stringlist>
-+		Definition: Must include "fsl,pfe-gemac-port"
-+
-+- reg
-+		Usage: required
-+		Value type: <prop-encoded-array>
-+		Definition: A standard property.
-+		Specifies the gemacid of the interface.
-+
-+- fsl,gemac-bus-id
-+		Usage: required
-+		Value type: <u32>
-+		Definition: Must be present. Value should be the id of the bus
-+		connected to gemac.
-+
-+- fsl,gemac-phy-id
-+		Usage: required
-+		Value type: <u32>
-+		Definition: Must be present. Value should be the id of the phy
-+		connected to gemac.
-+
-+- fsl,mdio-mux-val
-+		Usage: required
-+		Value type: <u32>
-+		Definition: Must be present. Value can be either 0 or 2 or 3.
-+		This value is used to configure the mux to enable mdio.
-+
-+- phy-mode
-+		Usage: required
-+		Value type: <string>
-+		Definition: Must include "sgmii"
-+
-+- fsl,pfe-phy-if-flags
-+		Usage: required
-+		Value type: <u32>
-+		Definition: Must be present. Value should be 0 by default.
-+		If there is not phy connected, this need to be 1.
-+
-+- mdio
-+		optional subnode that specifies the mdio bus. This has reg
-+		property which is used to enable/disable the mdio bus.
-+
-+EXAMPLE
-+
-+ethernet@0 {
-+	compatible = "fsl,pfe-gemac-port";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	reg = <0x0>;	/* GEM_ID */
-+	fsl,gemac-bus-id = <0x0>;	/* BUS_ID */
-+	fsl,gemac-phy-id = <0x2>;	/* PHY_ID */
-+	fsl,mdio-mux-val = <0x0>;
-+	phy-mode = "sgmii";
-+	fsl,pfe-phy-if-flags = <0x0>;
-+
-+	mdio@0 {
-+		reg = <0x1>; /* enabled/disabled */
-+	};
-+};
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/Kconfig
 @@ -0,0 +1,20 @@
@@ -1471,7 +1286,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif /* _UTIL_CSR_H_ */
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h
-@@ -0,0 +1,373 @@
+@@ -0,0 +1,372 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@@ -1777,7 +1592,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +void gemac_no_broadcast(void *base);
 +void gemac_enable_1536_rx(void *base);
 +void gemac_disable_1536_rx(void *base);
-+void gemac_set_rx_max_fl(void *base, int mtu);
 +void gemac_enable_rx_jmb(void *base);
 +void gemac_disable_rx_jmb(void *base);
 +void gemac_enable_stacked_vlan(void *base);
@@ -2345,7 +2159,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif /* _PFE_DEBUGFS_H_ */
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_eth.c
-@@ -0,0 +1,2521 @@
+@@ -0,0 +1,2491 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@@ -2392,7 +2206,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#include <linux/delay.h>
 +#include <linux/regmap.h>
 +#include <linux/i2c.h>
-+#include <linux/fsl/guts.h>
 +
 +#if defined(CONFIG_NF_CONNTRACK_MARK)
 +#include <net/netfilter/nf_conntrack.h>
@@ -2401,10 +2214,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#include "pfe_mod.h"
 +#include "pfe_eth.h"
 +
-+#define LS1012A_REV_1_0		0x87040010
-+
-+bool pfe_errata_a010897;
-+
 +static void *cbus_emac_base[3];
 +static void *cbus_gpi_base[3];
 +
@@ -3449,8 +3258,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			new_state = 1;
 +			gemac_set_speed(priv->EMAC_baseaddr,
 +					pfe_get_phydev_speed(phydev));
-+			if (priv->einfo->mii_config ==
-+					PHY_INTERFACE_MODE_RGMII_TXID)
++			if (priv->einfo->mii_config == PHY_INTERFACE_MODE_RGMII_TXID)
 +				pfe_set_rgmii_speed(phydev);
 +			priv->oldspeed = phydev->speed;
 +		}
@@ -3625,6 +3433,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	gemac_set_config(priv->EMAC_baseaddr, &cfg);
 +	gemac_allow_broadcast(priv->EMAC_baseaddr);
 +	gemac_enable_1536_rx(priv->EMAC_baseaddr);
++	gemac_enable_rx_jmb(priv->EMAC_baseaddr);
 +	gemac_enable_stacked_vlan(priv->EMAC_baseaddr);
 +	gemac_enable_pause_rx(priv->EMAC_baseaddr);
 +	gemac_set_bus_width(priv->EMAC_baseaddr, 64);
@@ -3697,17 +3506,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	return 0;
 +}
 +
-+static int pfe_eth_change_mtu(struct net_device *ndev, int new_mtu)
-+{
-+	struct pfe_eth_priv_s *priv = netdev_priv(ndev);
-+
-+	ndev->mtu = new_mtu;
-+	new_mtu += ETH_HLEN + ETH_FCS_LEN;
-+	gemac_set_rx_max_fl(priv->EMAC_baseaddr, new_mtu);
-+
-+	return 0;
-+}
-+
 +/* pfe_eth_open
 + */
 +static int pfe_eth_open(struct net_device *ndev)
@@ -3918,7 +3716,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	 * then fallback to default
 +	 */
 +#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)
-+	if (skb->_nfct) {
++	if (skb->nfct) {
 +		enum ip_conntrack_info cinfo;
 +		struct nf_conn *ct;
 +
@@ -4606,12 +4404,11 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	.ndo_stop = pfe_eth_close,
 +	.ndo_start_xmit = pfe_eth_send_packet,
 +	.ndo_select_queue = pfe_eth_select_queue,
-+	.ndo_set_rx_mode = pfe_eth_set_multi,
-+	.ndo_set_mac_address = pfe_eth_set_mac_address,
-+	.ndo_validate_addr = eth_validate_addr,
-+	.ndo_change_mtu = pfe_eth_change_mtu,
 +	.ndo_get_stats = pfe_eth_get_stats,
++	.ndo_set_mac_address = pfe_eth_set_mac_address,
++	.ndo_set_rx_mode = pfe_eth_set_multi,
 +	.ndo_set_features = pfe_eth_set_features,
++	.ndo_validate_addr = eth_validate_addr,
 +};
 +
 +/* pfe_eth_init_one
@@ -4715,15 +4512,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	/* Set MTU limits */
 +	ndev->min_mtu = ETH_MIN_MTU;
-+
-+/*
-+ * Jumbo frames are not supported on LS1012A rev-1.0.
-+ * So max mtu should be restricted to supported frame length.
-+ */
-+	if (pfe_errata_a010897)
-+		ndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN;
-+	else
-+		ndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN;
++	ndev->max_mtu = JUMBO_FRAME_SIZE;
 +
 +	/* supported features */
 +	ndev->hw_features = NETIF_F_SG;
@@ -4814,11 +4603,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	cbus_gpi_base[0] = EGPI1_BASE_ADDR;
 +	cbus_gpi_base[1] = EGPI2_BASE_ADDR;
 +
-+	if (fsl_guts_get_svr() == LS1012A_REV_1_0)
-+		pfe_errata_a010897 = true;
-+	else
-+		pfe_errata_a010897 = false;
-+
 +	for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
 +		err = pfe_eth_init_one(pfe, ii);
 +		if (err)
@@ -4869,7 +4653,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_eth.h
-@@ -0,0 +1,185 @@
+@@ -0,0 +1,184 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@@ -4957,8 +4741,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#define EMAC_TXQ_CNT	16
 +#define EMAC_TXQ_DEPTH	(HIF_TX_DESC_NT)
 +
-+#define JUMBO_FRAME_SIZE_V1	1900
-+#define JUMBO_FRAME_SIZE_V2	10258
++#define JUMBO_FRAME_SIZE	10258
 +/*
 + * Client Tx queue threshold, for txQ flush condition.
 + * It must be smaller than the queue size (in case we ever change it in the
@@ -5409,7 +5192,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif /* _PFE_FIRMWARE_H_ */
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_hal.c
-@@ -0,0 +1,1528 @@
+@@ -0,0 +1,1516 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@@ -5431,11 +5214,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#include "pfe_mod.h"
 +#include "pfe/pfe.h"
 +
-+/* A-010897: Jumbo frame is not supported */
-+extern bool pfe_errata_a010897;
-+
-+#define PFE_RCR_MAX_FL_MASK	0xC000FFFF
-+
 +void *cbus_base_addr;
 +void *ddr_base_addr;
 +unsigned long ddr_phys_base_addr;
@@ -6284,8 +6062,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	/*Remove loopbank*/
 +	val &= ~EMAC_RCNTRL_LOOP;
 +
-+	/* Enable flow control and MII mode and terminate received CRC */
-+	val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE | EMAC_RCNTRL_CRC_FWD);
++	/*Enable flow control and MII mode*/
++	val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE);
 +
 +	writel(val, base + EMAC_RCNTRL_REG);
 +}
@@ -6428,19 +6206,17 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +void gemac_enable_1536_rx(void *base)
 +{
 +	/* Set 1536 as Maximum frame length */
-+	writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)
-+		| (1536 << 16), base +	EMAC_RCNTRL_REG);
++	writel(readl(base + EMAC_RCNTRL_REG) | (1536 << 16), base +
++		EMAC_RCNTRL_REG);
 +}
 +
-+/* GEMAC set rx Max frame length.
++/* GEMAC enable jumbo function.
 + * @param[in]	base	GEMAC base address
-+ * @param[in]	mtu	new mtu
 + */
-+void gemac_set_rx_max_fl(void *base, int mtu)
++void gemac_enable_rx_jmb(void *base)
 +{
-+	/* Set mtu as Maximum frame length */
-+	writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)
-+		| (mtu << 16), base + EMAC_RCNTRL_REG);
++	writel(readl(base + EMAC_RCNTRL_REG) | (JUMBO_FRAME_SIZE << 16), base
++		+ EMAC_RCNTRL_REG);
 +}
 +
 +/* GEMAC enable stacked vlan function.
@@ -6517,12 +6293,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	/*GEMAC config taken from VLSI */
 +	writel(0x00000004, base + EMAC_TFWR_STR_FWD);
 +	writel(0x00000005, base + EMAC_RX_SECTION_FULL);
-+
-+	if (pfe_errata_a010897)
-+		writel(0x0000076c, base + EMAC_TRUNC_FL);
-+	else
-+		writel(0x00003fff, base + EMAC_TRUNC_FL);
-+
++	writel(0x00003fff, base + EMAC_TRUNC_FL);
 +	writel(0x00000030, base + EMAC_TX_SECTION_EMPTY);
 +	writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);
 +
@@ -8015,7 +7786,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 --- /dev/null
 +++ b/drivers/staging/fsl_ppfe/pfe_hif.h
-@@ -0,0 +1,212 @@
+@@ -0,0 +1,211 @@
 +/*
 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
 + * Copyright 2017 NXP
@@ -8038,7 +7809,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#define _PFE_HIF_H_
 +
 +#include <linux/netdevice.h>
-+#include <linux/interrupt.h>
 +
 +#define HIF_NAPI_STATS
 +
diff --git a/target/linux/layerscape/patches-4.9/801-ata-support-layerscape.patch b/target/linux/layerscape/patches-4.9/801-ata-support-layerscape.patch
new file mode 100644
index 000000000..e9d34d36c
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/801-ata-support-layerscape.patch
@@ -0,0 +1,144 @@
+From 4c3979602db05bca439bfc98db88dc14a8663db0 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:14:57 +0800
+Subject: [PATCH 13/30] ata: support layerscape
+
+This is an integrated patch for layerscape sata support.
+
+Signed-off-by: Tang Yuantian <Yuantian.Tang@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/ata/ahci_qoriq.c | 63 ++++++++++++++++++++++++++++++++++++++++++------
+ 1 file changed, 56 insertions(+), 7 deletions(-)
+
+--- a/drivers/ata/ahci_qoriq.c
++++ b/drivers/ata/ahci_qoriq.c
+@@ -1,7 +1,7 @@
+ /*
+  * Freescale QorIQ AHCI SATA platform driver
+  *
+- * Copyright 2015 Freescale, Inc.
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+  *   Tang Yuantian <Yuantian.Tang@freescale.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+@@ -46,23 +46,32 @@
+ #define LS1021A_AXICC_ADDR	0xC0
+ 
+ #define SATA_ECC_DISABLE	0x00020000
++#define ECC_DIS_ARMV8_CH2	0x80000000
++#define ECC_DIS_LS1088A		0x40000000
+ 
+ enum ahci_qoriq_type {
+ 	AHCI_LS1021A,
+ 	AHCI_LS1043A,
+ 	AHCI_LS2080A,
++	AHCI_LS1046A,
++	AHCI_LS1088A,
++	AHCI_LS2088A,
+ };
+ 
+ struct ahci_qoriq_priv {
+ 	struct ccsr_ahci *reg_base;
+ 	enum ahci_qoriq_type type;
+ 	void __iomem *ecc_addr;
++	bool is_dmacoherent;
+ };
+ 
+ static const struct of_device_id ahci_qoriq_of_match[] = {
+ 	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
+ 	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
+ 	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
++	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
++	{ .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
++	{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
+@@ -154,6 +163,8 @@ static int ahci_qoriq_phy_init(struct ah
+ 
+ 	switch (qpriv->type) {
+ 	case AHCI_LS1021A:
++		if (!qpriv->ecc_addr)
++			return -EINVAL;
+ 		writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
+ 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
+ 		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
+@@ -161,19 +172,56 @@ static int ahci_qoriq_phy_init(struct ah
+ 		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
+ 		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
+ 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+-		writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
++		if (qpriv->is_dmacoherent)
++			writel(AHCI_PORT_AXICC_CFG,
++					reg_base + LS1021A_AXICC_ADDR);
+ 		break;
+ 
+ 	case AHCI_LS1043A:
++		if (!qpriv->ecc_addr)
++			return -EINVAL;
++		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
++				qpriv->ecc_addr);
+ 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
+ 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+-		writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
++		if (qpriv->is_dmacoherent)
++			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ 		break;
+ 
+ 	case AHCI_LS2080A:
+ 		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
+ 		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+-		writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
++		if (qpriv->is_dmacoherent)
++			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
++		break;
++
++	case AHCI_LS1046A:
++		if (!qpriv->ecc_addr)
++			return -EINVAL;
++		writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
++				qpriv->ecc_addr);
++		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
++		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
++		if (qpriv->is_dmacoherent)
++			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
++		break;
++
++	case AHCI_LS1088A:
++		if (!qpriv->ecc_addr)
++			return -EINVAL;
++		writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
++		       qpriv->ecc_addr);
++		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
++		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
++		if (qpriv->is_dmacoherent)
++			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
++		break;
++
++	case AHCI_LS2088A:
++		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
++		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
++		if (qpriv->is_dmacoherent)
++			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ 		break;
+ 	}
+ 
+@@ -204,13 +252,14 @@ static int ahci_qoriq_probe(struct platf
+ 
+ 	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
+ 
+-	if (qoriq_priv->type == AHCI_LS1021A) {
+-		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+-				"sata-ecc");
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++			"sata-ecc");
++	if (res) {
+ 		qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
+ 		if (IS_ERR(qoriq_priv->ecc_addr))
+ 			return PTR_ERR(qoriq_priv->ecc_addr);
+ 	}
++	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
+ 
+ 	rc = ahci_platform_enable_resources(hpriv);
+ 	if (rc)
diff --git a/target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch b/target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch
new file mode 100644
index 000000000..0d05dc78a
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch
@@ -0,0 +1,323 @@
+From 82a391a067491f4c46b75d0dfe2bf9e5a11aca8e Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:15:44 +0800
+Subject: [PATCH 14/30] clk: support layerscape
+
+This is an integrated patch for layerscape clock support.
+
+Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
+Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
+Signed-off-by: Scott Wood <oss@buserror.net>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/clk/clk-qoriq.c | 179 ++++++++++++++++++++++++++++++++++++++++++++----
+ 1 file changed, 164 insertions(+), 15 deletions(-)
+
+--- a/drivers/clk/clk-qoriq.c
++++ b/drivers/clk/clk-qoriq.c
+@@ -12,6 +12,7 @@
+ 
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
++#include <linux/clkdev.h>
+ #include <linux/fsl/guts.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+@@ -40,7 +41,7 @@ struct clockgen_pll_div {
+ };
+ 
+ struct clockgen_pll {
+-	struct clockgen_pll_div div[4];
++	struct clockgen_pll_div div[8];
+ };
+ 
+ #define CLKSEL_VALID	1
+@@ -87,7 +88,7 @@ struct clockgen {
+ 	struct device_node *node;
+ 	void __iomem *regs;
+ 	struct clockgen_chipinfo info; /* mutable copy */
+-	struct clk *sysclk;
++	struct clk *sysclk, *coreclk;
+ 	struct clockgen_pll pll[6];
+ 	struct clk *cmux[NUM_CMUX];
+ 	struct clk *hwaccel[NUM_HWACCEL];
+@@ -266,6 +267,39 @@ static const struct clockgen_muxinfo ls1
+ 	},
+ };
+ 
++static const struct clockgen_muxinfo ls1046a_hwa1 = {
++	{
++		{},
++		{},
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
++		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++	},
++};
++
++static const struct clockgen_muxinfo ls1046a_hwa2 = {
++	{
++		{},
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
++		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
++		{},
++		{},
++		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++	},
++};
++
++static const struct clockgen_muxinfo ls1012a_cmux = {
++	{
++		[0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
++		{},
++		[2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
++	}
++};
++
+ static const struct clockgen_muxinfo t1023_hwa1 = {
+ 	{
+ 		{},
+@@ -489,6 +523,42 @@ static const struct clockgen_chipinfo ch
+ 		.flags = CG_PLL_8BIT,
+ 	},
+ 	{
++		.compat = "fsl,ls1046a-clockgen",
++		.init_periph = t2080_init_periph,
++		.cmux_groups = {
++			&t1040_cmux
++		},
++		.hwaccel = {
++			&ls1046a_hwa1, &ls1046a_hwa2
++		},
++		.cmux_to_group = {
++			0, -1
++		},
++		.pll_mask = 0x07,
++		.flags = CG_PLL_8BIT,
++	},
++	{
++		.compat = "fsl,ls1088a-clockgen",
++		.cmux_groups = {
++			&clockgen2_cmux_cga12
++		},
++		.cmux_to_group = {
++			0, 0, -1
++		},
++		.pll_mask = 0x07,
++		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
++	},
++	{
++		.compat = "fsl,ls1012a-clockgen",
++		.cmux_groups = {
++			&ls1012a_cmux
++		},
++		.cmux_to_group = {
++			0, -1
++		},
++		.pll_mask = 0x03,
++	},
++	{
+ 		.compat = "fsl,ls2080a-clockgen",
+ 		.cmux_groups = {
+ 			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+@@ -846,7 +916,12 @@ static void __init create_muxes(struct c
+ 
+ static void __init clockgen_init(struct device_node *np);
+ 
+-/* Legacy nodes may get probed before the parent clockgen node */
++/*
++ * Legacy nodes may get probed before the parent clockgen node.
++ * It is assumed that device trees with legacy nodes will not
++ * contain a "clocks" property -- otherwise the input clocks may
++ * not be initialized at this point.
++ */
+ static void __init legacy_init_clockgen(struct device_node *np)
+ {
+ 	if (!clockgen.node)
+@@ -887,18 +962,13 @@ static struct clk __init
+ 	return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
+ }
+ 
+-static struct clk *sysclk_from_parent(const char *name)
++static struct clk __init *input_clock(const char *name, struct clk *clk)
+ {
+-	struct clk *clk;
+-	const char *parent_name;
+-
+-	clk = of_clk_get(clockgen.node, 0);
+-	if (IS_ERR(clk))
+-		return clk;
++	const char *input_name;
+ 
+ 	/* Register the input clock under the desired name. */
+-	parent_name = __clk_get_name(clk);
+-	clk = clk_register_fixed_factor(NULL, name, parent_name,
++	input_name = __clk_get_name(clk);
++	clk = clk_register_fixed_factor(NULL, name, input_name,
+ 					0, 1, 1);
+ 	if (IS_ERR(clk))
+ 		pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
+@@ -907,6 +977,29 @@ static struct clk *sysclk_from_parent(co
+ 	return clk;
+ }
+ 
++static struct clk __init *input_clock_by_name(const char *name,
++					      const char *dtname)
++{
++	struct clk *clk;
++
++	clk = of_clk_get_by_name(clockgen.node, dtname);
++	if (IS_ERR(clk))
++		return clk;
++
++	return input_clock(name, clk);
++}
++
++static struct clk __init *input_clock_by_index(const char *name, int idx)
++{
++	struct clk *clk;
++
++	clk = of_clk_get(clockgen.node, 0);
++	if (IS_ERR(clk))
++		return clk;
++
++	return input_clock(name, clk);
++}
++
+ static struct clk * __init create_sysclk(const char *name)
+ {
+ 	struct device_node *sysclk;
+@@ -916,7 +1009,11 @@ static struct clk * __init create_sysclk
+ 	if (!IS_ERR(clk))
+ 		return clk;
+ 
+-	clk = sysclk_from_parent(name);
++	clk = input_clock_by_name(name, "sysclk");
++	if (!IS_ERR(clk))
++		return clk;
++
++	clk = input_clock_by_index(name, 0);
+ 	if (!IS_ERR(clk))
+ 		return clk;
+ 
+@@ -927,7 +1024,27 @@ static struct clk * __init create_sysclk
+ 			return clk;
+ 	}
+ 
+-	pr_err("%s: No input clock\n", __func__);
++	pr_err("%s: No input sysclk\n", __func__);
++	return NULL;
++}
++
++static struct clk * __init create_coreclk(const char *name)
++{
++	struct clk *clk;
++
++	clk = input_clock_by_name(name, "coreclk");
++	if (!IS_ERR(clk))
++		return clk;
++
++	/*
++	 * This indicates a mix of legacy nodes with the new coreclk
++	 * mechanism, which should never happen.  If this error occurs,
++	 * don't use the wrong input clock just because coreclk isn't
++	 * ready yet.
++	 */
++	if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
++		return clk;
++
+ 	return NULL;
+ }
+ 
+@@ -950,11 +1067,19 @@ static void __init create_one_pll(struct
+ 	u32 __iomem *reg;
+ 	u32 mult;
+ 	struct clockgen_pll *pll = &cg->pll[idx];
++	const char *input = "cg-sysclk";
+ 	int i;
+ 
+ 	if (!(cg->info.pll_mask & (1 << idx)))
+ 		return;
+ 
++	if (cg->coreclk && idx != PLATFORM_PLL) {
++		if (IS_ERR(cg->coreclk))
++			return;
++
++		input = "cg-coreclk";
++	}
++
+ 	if (cg->info.flags & CG_VER3) {
+ 		switch (idx) {
+ 		case PLATFORM_PLL:
+@@ -1000,12 +1125,20 @@ static void __init create_one_pll(struct
+ 
+ 	for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
+ 		struct clk *clk;
++		int ret;
++
++		/*
++		 * For platform PLL, there are 8 divider clocks.
++		 * For core PLL, there are 4 divider clocks at most.
++		 */
++		if (idx != 0 && i >= 4)
++			break;
+ 
+ 		snprintf(pll->div[i].name, sizeof(pll->div[i].name),
+ 			 "cg-pll%d-div%d", idx, i + 1);
+ 
+ 		clk = clk_register_fixed_factor(NULL,
+-				pll->div[i].name, "cg-sysclk", 0, mult, i + 1);
++				pll->div[i].name, input, 0, mult, i + 1);
+ 		if (IS_ERR(clk)) {
+ 			pr_err("%s: %s: register failed %ld\n",
+ 			       __func__, pll->div[i].name, PTR_ERR(clk));
+@@ -1013,6 +1146,11 @@ static void __init create_one_pll(struct
+ 		}
+ 
+ 		pll->div[i].clk = clk;
++		ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
++		if (ret != 0)
++			pr_err("%s: %s: register to lookup table failed %ld\n",
++			       __func__, pll->div[i].name, PTR_ERR(clk));
++
+ 	}
+ }
+ 
+@@ -1142,6 +1280,13 @@ static struct clk *clockgen_clk_get(stru
+ 			goto bad_args;
+ 		clk = pll->div[idx].clk;
+ 		break;
++	case 5:
++		if (idx != 0)
++			goto bad_args;
++		clk = cg->coreclk;
++		if (IS_ERR(clk))
++			clk = NULL;
++		break;
+ 	default:
+ 		goto bad_args;
+ 	}
+@@ -1253,6 +1398,7 @@ static void __init clockgen_init(struct
+ 		clockgen.info.flags |= CG_CMUX_GE_PLAT;
+ 
+ 	clockgen.sysclk = create_sysclk("cg-sysclk");
++	clockgen.coreclk = create_coreclk("cg-coreclk");
+ 	create_plls(&clockgen);
+ 	create_muxes(&clockgen);
+ 
+@@ -1273,8 +1419,11 @@ err:
+ 
+ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
++CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
+ CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+ 
+ /* Legacy nodes */
diff --git a/target/linux/layerscape/patches-4.14/823-pm-support-layerscape.patch b/target/linux/layerscape/patches-4.9/803-cpufreq-support-layerscape.patch
similarity index 71%
rename from target/linux/layerscape/patches-4.14/823-pm-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/803-cpufreq-support-layerscape.patch
index e5c3b7db0..cf2b42a54 100644
--- a/target/linux/layerscape/patches-4.14/823-pm-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/803-cpufreq-support-layerscape.patch
@@ -1,23 +1,21 @@
-From aded309f403c4202b9c6f61ea6a635e0c736eb77 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:27:07 +0800
-Subject: [PATCH 40/40] pm: support layerscape
-This is an integrated patch of pm for layerscape
+From d78d78ccbaded757e8bea0d13c4120518bdd4660 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:21:38 +0800
+Subject: [PATCH 15/32] cpufreq: support layerscape
 
-Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
-Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
-Signed-off-by: Li Yang <leoyang.li@nxp.com>
-Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
-Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
-Signed-off-by: Zhao Chenhui <chenhui.zhao@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+This is an integrated patch for layerscape pm support.
+
+Signed-off-by: Tang Yuantian <Yuantian.Tang@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
  .../devicetree/bindings/powerpc/fsl/pmc.txt   |  59 ++--
- drivers/firmware/psci.c                       |  16 +-
+ drivers/cpufreq/Kconfig                       |   2 +-
+ drivers/cpufreq/qoriq-cpufreq.c               | 176 +++++------
+ drivers/firmware/psci.c                       |  12 +-
  drivers/soc/fsl/rcpm.c                        | 158 ++++++++++
  drivers/soc/fsl/sleep_fsm.c                   | 279 ++++++++++++++++++
  drivers/soc/fsl/sleep_fsm.h                   | 130 ++++++++
- 5 files changed, 615 insertions(+), 27 deletions(-)
+ 7 files changed, 678 insertions(+), 138 deletions(-)
  create mode 100644 drivers/soc/fsl/rcpm.c
  create mode 100644 drivers/soc/fsl/sleep_fsm.c
  create mode 100644 drivers/soc/fsl/sleep_fsm.h
@@ -108,34 +106,348 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			fsl,pmcdr-mask = <0x00000020>;
 +		};
  	};
+--- a/drivers/cpufreq/Kconfig
++++ b/drivers/cpufreq/Kconfig
+@@ -334,7 +334,7 @@ endif
+ 
+ config QORIQ_CPUFREQ
+ 	tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
+-	depends on OF && COMMON_CLK && (PPC_E500MC || ARM)
++	depends on OF && COMMON_CLK && (PPC_E500MC || ARM || ARM64)
+ 	depends on !CPU_THERMAL || THERMAL
+ 	select CLK_QORIQ
+ 	help
+--- a/drivers/cpufreq/qoriq-cpufreq.c
++++ b/drivers/cpufreq/qoriq-cpufreq.c
+@@ -11,6 +11,7 @@
+ #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
+ 
+ #include <linux/clk.h>
++#include <linux/clk-provider.h>
+ #include <linux/cpufreq.h>
+ #include <linux/cpu_cooling.h>
+ #include <linux/errno.h>
+@@ -22,10 +23,6 @@
+ #include <linux/slab.h>
+ #include <linux/smp.h>
+ 
+-#if !defined(CONFIG_ARM)
+-#include <asm/smp.h>	/* for get_hard_smp_processor_id() in UP configs */
+-#endif
+-
+ /**
+  * struct cpu_data
+  * @pclk: the parent clock of cpu
+@@ -37,73 +34,51 @@ struct cpu_data {
+ 	struct thermal_cooling_device *cdev;
+ };
+ 
++/*
++ * Don't use cpufreq on this SoC -- used when the SoC would have otherwise
++ * matched a more generic compatible.
++ */
++#define SOC_BLACKLIST		1
++
+ /**
+  * struct soc_data - SoC specific data
+- * @freq_mask: mask the disallowed frequencies
+- * @flag: unique flags
++ * @flags: SOC_xxx
+  */
+ struct soc_data {
+-	u32 freq_mask[4];
+-	u32 flag;
+-};
+-
+-#define FREQ_MASK	1
+-/* see hardware specification for the allowed frqeuencies */
+-static const struct soc_data sdata[] = {
+-	{ /* used by p2041 and p3041 */
+-		.freq_mask = {0x8, 0x8, 0x2, 0x2},
+-		.flag = FREQ_MASK,
+-	},
+-	{ /* used by p5020 */
+-		.freq_mask = {0x8, 0x2},
+-		.flag = FREQ_MASK,
+-	},
+-	{ /* used by p4080, p5040 */
+-		.freq_mask = {0},
+-		.flag = 0,
+-	},
++	u32 flags;
+ };
+ 
+-/*
+- * the minimum allowed core frequency, in Hz
+- * for chassis v1.0, >= platform frequency
+- * for chassis v2.0, >= platform frequency / 2
+- */
+-static u32 min_cpufreq;
+-static const u32 *fmask;
+-
+-#if defined(CONFIG_ARM)
+-static int get_cpu_physical_id(int cpu)
+-{
+-	return topology_core_id(cpu);
+-}
+-#else
+-static int get_cpu_physical_id(int cpu)
+-{
+-	return get_hard_smp_processor_id(cpu);
+-}
+-#endif
+-
+ static u32 get_bus_freq(void)
+ {
+ 	struct device_node *soc;
+ 	u32 sysfreq;
++	struct clk *pltclk;
++	int ret;
+ 
++	/* get platform freq by searching bus-frequency property */
+ 	soc = of_find_node_by_type(NULL, "soc");
+-	if (!soc)
+-		return 0;
+-
+-	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
+-		sysfreq = 0;
++	if (soc) {
++		ret = of_property_read_u32(soc, "bus-frequency", &sysfreq);
++		of_node_put(soc);
++		if (!ret)
++			return sysfreq;
++	}
+ 
+-	of_node_put(soc);
++	/* get platform freq by its clock name */
++	pltclk = clk_get(NULL, "cg-pll0-div1");
++	if (IS_ERR(pltclk)) {
++		pr_err("%s: can't get bus frequency %ld\n",
++		       __func__, PTR_ERR(pltclk));
++		return PTR_ERR(pltclk);
++	}
+ 
+-	return sysfreq;
++	return clk_get_rate(pltclk);
+ }
+ 
+-static struct device_node *cpu_to_clk_node(int cpu)
++static struct clk *cpu_to_clk(int cpu)
+ {
+-	struct device_node *np, *clk_np;
++	struct device_node *np;
++	struct clk *clk;
+ 
+ 	if (!cpu_present(cpu))
+ 		return NULL;
+@@ -112,37 +87,28 @@ static struct device_node *cpu_to_clk_no
+ 	if (!np)
+ 		return NULL;
+ 
+-	clk_np = of_parse_phandle(np, "clocks", 0);
+-	if (!clk_np)
+-		return NULL;
+-
++	clk = of_clk_get(np, 0);
+ 	of_node_put(np);
+-
+-	return clk_np;
++	return clk;
+ }
+ 
+ /* traverse cpu nodes to get cpu mask of sharing clock wire */
+ static void set_affected_cpus(struct cpufreq_policy *policy)
+ {
+-	struct device_node *np, *clk_np;
+ 	struct cpumask *dstp = policy->cpus;
++	struct clk *clk;
+ 	int i;
+ 
+-	np = cpu_to_clk_node(policy->cpu);
+-	if (!np)
+-		return;
+-
+ 	for_each_present_cpu(i) {
+-		clk_np = cpu_to_clk_node(i);
+-		if (!clk_np)
++		clk = cpu_to_clk(i);
++		if (IS_ERR(clk)) {
++			pr_err("%s: no clock for cpu %d\n", __func__, i);
+ 			continue;
++		}
+ 
+-		if (clk_np == np)
++		if (clk_is_match(policy->clk, clk))
+ 			cpumask_set_cpu(i, dstp);
+-
+-		of_node_put(clk_np);
+ 	}
+-	of_node_put(np);
+ }
+ 
+ /* reduce the duplicated frequencies in frequency table */
+@@ -198,10 +164,11 @@ static void freq_table_sort(struct cpufr
+ 
+ static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
+ {
+-	struct device_node *np, *pnode;
++	struct device_node *np;
+ 	int i, count, ret;
+-	u32 freq, mask;
++	u32 freq;
+ 	struct clk *clk;
++	const struct clk_hw *hwclk;
+ 	struct cpufreq_frequency_table *table;
+ 	struct cpu_data *data;
+ 	unsigned int cpu = policy->cpu;
+@@ -221,17 +188,13 @@ static int qoriq_cpufreq_cpu_init(struct
+ 		goto err_nomem2;
+ 	}
+ 
+-	pnode = of_parse_phandle(np, "clocks", 0);
+-	if (!pnode) {
+-		pr_err("%s: could not get clock information\n", __func__);
+-		goto err_nomem2;
+-	}
++	hwclk = __clk_get_hw(policy->clk);
++	count = clk_hw_get_num_parents(hwclk);
+ 
+-	count = of_property_count_strings(pnode, "clock-names");
+ 	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
+ 	if (!data->pclk) {
+ 		pr_err("%s: no memory\n", __func__);
+-		goto err_node;
++		goto err_nomem2;
+ 	}
+ 
+ 	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
+@@ -240,23 +203,11 @@ static int qoriq_cpufreq_cpu_init(struct
+ 		goto err_pclk;
+ 	}
+ 
+-	if (fmask)
+-		mask = fmask[get_cpu_physical_id(cpu)];
+-	else
+-		mask = 0x0;
+-
+ 	for (i = 0; i < count; i++) {
+-		clk = of_clk_get(pnode, i);
++		clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
+ 		data->pclk[i] = clk;
+ 		freq = clk_get_rate(clk);
+-		/*
+-		 * the clock is valid if its frequency is not masked
+-		 * and large than minimum allowed frequency.
+-		 */
+-		if (freq < min_cpufreq || (mask & (1 << i)))
+-			table[i].frequency = CPUFREQ_ENTRY_INVALID;
+-		else
+-			table[i].frequency = freq / 1000;
++		table[i].frequency = freq / 1000;
+ 		table[i].driver_data = i;
+ 	}
+ 	freq_table_redup(table, count);
+@@ -282,7 +233,6 @@ static int qoriq_cpufreq_cpu_init(struct
+ 	policy->cpuinfo.transition_latency = u64temp + 1;
+ 
+ 	of_node_put(np);
+-	of_node_put(pnode);
+ 
+ 	return 0;
+ 
+@@ -290,10 +240,7 @@ err_nomem1:
+ 	kfree(table);
+ err_pclk:
+ 	kfree(data->pclk);
+-err_node:
+-	of_node_put(pnode);
+ err_nomem2:
+-	policy->driver_data = NULL;
+ 	kfree(data);
+ err_np:
+ 	of_node_put(np);
+@@ -357,12 +304,25 @@ static struct cpufreq_driver qoriq_cpufr
+ 	.attr		= cpufreq_generic_attr,
+ };
+ 
++static const struct soc_data blacklist = {
++	.flags = SOC_BLACKLIST,
++};
++
+ static const struct of_device_id node_matches[] __initconst = {
+-	{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
+-	{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
+-	{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
+-	{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
+-	{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
++	/* e6500 cannot use cpufreq due to erratum A-008083 */
++	{ .compatible = "fsl,b4420-clockgen", &blacklist },
++	{ .compatible = "fsl,b4860-clockgen", &blacklist },
++	{ .compatible = "fsl,t2080-clockgen", &blacklist },
++	{ .compatible = "fsl,t4240-clockgen", &blacklist },
++
++	{ .compatible = "fsl,ls1012a-clockgen", },
++	{ .compatible = "fsl,ls1021a-clockgen", },
++	{ .compatible = "fsl,ls1043a-clockgen", },
++	{ .compatible = "fsl,ls1046a-clockgen", },
++	{ .compatible = "fsl,ls1088a-clockgen", },
++	{ .compatible = "fsl,ls2080a-clockgen", },
++	{ .compatible = "fsl,p4080-clockgen", },
++	{ .compatible = "fsl,qoriq-clockgen-1.0", },
+ 	{ .compatible = "fsl,qoriq-clockgen-2.0", },
+ 	{}
+ };
+@@ -380,16 +340,12 @@ static int __init qoriq_cpufreq_init(voi
+ 
+ 	match = of_match_node(node_matches, np);
+ 	data = match->data;
+-	if (data) {
+-		if (data->flag)
+-			fmask = data->freq_mask;
+-		min_cpufreq = get_bus_freq();
+-	} else {
+-		min_cpufreq = get_bus_freq() / 2;
+-	}
+ 
+ 	of_node_put(np);
+ 
++	if (data && data->flags & SOC_BLACKLIST)
++		return -ENODEV;
++
+ 	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
+ 	if (!ret)
+ 		pr_info("Freescale QorIQ CPU frequency scaling driver\n");
 --- a/drivers/firmware/psci.c
 +++ b/drivers/firmware/psci.c
-@@ -437,8 +437,18 @@ CPUIDLE_METHOD_OF_DECLARE(psci, "psci",
+@@ -437,8 +437,12 @@ CPUIDLE_METHOD_OF_DECLARE(psci, "psci",
  
  static int psci_system_suspend(unsigned long unused)
  {
 -	return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
--			      __pa_symbol(cpu_resume), 0, 0);
+-			      virt_to_phys(cpu_resume), 0, 0);
 +	u32 state;
-+	u32 ver = psci_get_version();
 +
-+	if (PSCI_VERSION_MAJOR(ver) >= 1) {
-+		return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
-+				virt_to_phys(cpu_resume), 0, 0);
-+	} else {
-+		state = ( 2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
-+			(1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
++	state = ( 2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
++		(1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
 +
-+		return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
-+	}
++	return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
  }
  
  static int psci_system_suspend_enter(suspend_state_t state)
-@@ -562,6 +572,8 @@ static void __init psci_0_2_set_function
+@@ -458,6 +462,8 @@ static void __init psci_init_system_susp
+ 	if (!IS_ENABLED(CONFIG_SUSPEND))
+ 		return;
+ 
++	suspend_set_ops(&psci_suspend_ops);
++
+ 	ret = psci_features(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND));
+ 
+ 	if (ret != PSCI_RET_NOT_SUPPORTED)
+@@ -562,6 +568,8 @@ static void __init psci_0_2_set_function
  	arm_pm_restart = psci_sys_reset;
  
  	pm_power_off = psci_sys_poweroff;
-+
++	psci_init_system_suspend();
 +	suspend_set_ops(&psci_suspend_ops);
  }
  
diff --git a/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch b/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch
new file mode 100644
index 000000000..714fba3a7
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch
@@ -0,0 +1,29223 @@
+From 2a0aa9bd187f6f5693982a8f79665585af772237 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:29:41 +0800
+Subject: [PATCH 16/32] crypto: support layerscape
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is an integrated patch for layerscape sec support.
+
+Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
+Signed-off-by: Fabio Estevam <festevam@gmail.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
+Signed-off-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
+Signed-off-by: Eric Biggers <ebiggers@google.com>
+Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
+Signed-off-by: Xulin Sun <xulin.sun@windriver.com>
+Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
+Signed-off-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
+Signed-off-by: Andrew Lutomirski <luto@kernel.org>
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Marcelo Cerri <marcelo.cerri@canonical.com>
+Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Laura Abbott <labbott@redhat.com>
+Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
+Singed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ crypto/Kconfig                                |   30 +
+ crypto/Makefile                               |    4 +
+ crypto/acompress.c                            |  169 +
+ crypto/algboss.c                              |   12 +-
+ crypto/crypto_user.c                          |   19 +
+ crypto/scompress.c                            |  356 +
+ crypto/tcrypt.c                               |   17 +-
+ crypto/testmgr.c                              | 1708 ++---
+ crypto/testmgr.h                              | 1125 ++--
+ crypto/tls.c                                  |  607 ++
+ drivers/crypto/caam/Kconfig                   |   77 +-
+ drivers/crypto/caam/Makefile                  |   16 +-
+ drivers/crypto/caam/caamalg.c                 | 2185 ++----
+ drivers/crypto/caam/caamalg_desc.c            | 1961 ++++++
+ drivers/crypto/caam/caamalg_desc.h            |  127 +
+ drivers/crypto/caam/caamalg_qi.c              | 3321 +++++++++
+ drivers/crypto/caam/caamalg_qi2.c             | 5938 +++++++++++++++++
+ drivers/crypto/caam/caamalg_qi2.h             |  283 +
+ drivers/crypto/caam/caamhash.c                |  555 +-
+ drivers/crypto/caam/caamhash_desc.c           |  108 +
+ drivers/crypto/caam/caamhash_desc.h           |   49 +
+ drivers/crypto/caam/caampkc.c                 |  471 +-
+ drivers/crypto/caam/caampkc.h                 |   58 +
+ drivers/crypto/caam/caamrng.c                 |   16 +-
+ drivers/crypto/caam/compat.h                  |    1 +
+ drivers/crypto/caam/ctrl.c                    |  358 +-
+ drivers/crypto/caam/ctrl.h                    |    2 +
+ drivers/crypto/caam/desc.h                    |   84 +-
+ drivers/crypto/caam/desc_constr.h             |  180 +-
+ drivers/crypto/caam/dpseci.c                  |  858 +++
+ drivers/crypto/caam/dpseci.h                  |  395 ++
+ drivers/crypto/caam/dpseci_cmd.h              |  261 +
+ drivers/crypto/caam/error.c                   |  127 +-
+ drivers/crypto/caam/error.h                   |   10 +-
+ drivers/crypto/caam/intern.h                  |   31 +-
+ drivers/crypto/caam/jr.c                      |   72 +-
+ drivers/crypto/caam/jr.h                      |    2 +
+ drivers/crypto/caam/key_gen.c                 |   32 +-
+ drivers/crypto/caam/key_gen.h                 |   36 +-
+ drivers/crypto/caam/pdb.h                     |   62 +
+ drivers/crypto/caam/pkc_desc.c                |   36 +
+ drivers/crypto/caam/qi.c                      |  804 +++
+ drivers/crypto/caam/qi.h                      |  204 +
+ drivers/crypto/caam/regs.h                    |   63 +-
+ drivers/crypto/caam/sg_sw_qm.h                |  126 +
+ drivers/crypto/caam/sg_sw_qm2.h               |   81 +
+ drivers/crypto/caam/sg_sw_sec4.h              |   60 +-
+ drivers/crypto/talitos.c                      |    8 +
+ drivers/net/wireless/rsi/rsi_91x_usb.c        |    2 +-
+ drivers/staging/wilc1000/linux_wlan.c         |    2 +-
+ .../staging/wilc1000/wilc_wfi_cfgoperations.c |    2 +-
+ include/crypto/acompress.h                    |  269 +
+ include/crypto/internal/acompress.h           |   81 +
+ include/crypto/internal/scompress.h           |  136 +
+ include/linux/crypto.h                        |    3 +
+ include/uapi/linux/cryptouser.h               |    5 +
+ scripts/spelling.txt                          |    3 +
+ sound/soc/amd/acp-pcm-dma.c                   |    2 +-
+ 58 files changed, 19620 insertions(+), 3990 deletions(-)
+ create mode 100644 crypto/acompress.c
+ create mode 100644 crypto/scompress.c
+ create mode 100644 crypto/tls.c
+ create mode 100644 drivers/crypto/caam/caamalg_desc.c
+ create mode 100644 drivers/crypto/caam/caamalg_desc.h
+ create mode 100644 drivers/crypto/caam/caamalg_qi.c
+ create mode 100644 drivers/crypto/caam/caamalg_qi2.c
+ create mode 100644 drivers/crypto/caam/caamalg_qi2.h
+ create mode 100644 drivers/crypto/caam/caamhash_desc.c
+ create mode 100644 drivers/crypto/caam/caamhash_desc.h
+ create mode 100644 drivers/crypto/caam/dpseci.c
+ create mode 100644 drivers/crypto/caam/dpseci.h
+ create mode 100644 drivers/crypto/caam/dpseci_cmd.h
+ create mode 100644 drivers/crypto/caam/qi.c
+ create mode 100644 drivers/crypto/caam/qi.h
+ create mode 100644 drivers/crypto/caam/sg_sw_qm.h
+ create mode 100644 drivers/crypto/caam/sg_sw_qm2.h
+ create mode 100644 include/crypto/acompress.h
+ create mode 100644 include/crypto/internal/acompress.h
+ create mode 100644 include/crypto/internal/scompress.h
+
+--- a/crypto/Kconfig
++++ b/crypto/Kconfig
+@@ -102,6 +102,15 @@ config CRYPTO_KPP
+ 	select CRYPTO_ALGAPI
+ 	select CRYPTO_KPP2
+ 
++config CRYPTO_ACOMP2
++	tristate
++	select CRYPTO_ALGAPI2
++
++config CRYPTO_ACOMP
++	tristate
++	select CRYPTO_ALGAPI
++	select CRYPTO_ACOMP2
++
+ config CRYPTO_RSA
+ 	tristate "RSA algorithm"
+ 	select CRYPTO_AKCIPHER
+@@ -138,6 +147,7 @@ config CRYPTO_MANAGER2
+ 	select CRYPTO_BLKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS
+ 	select CRYPTO_AKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS
+ 	select CRYPTO_KPP2 if !CRYPTO_MANAGER_DISABLE_TESTS
++	select CRYPTO_ACOMP2 if !CRYPTO_MANAGER_DISABLE_TESTS
+ 
+ config CRYPTO_USER
+ 	tristate "Userspace cryptographic algorithm configuration"
+@@ -295,6 +305,26 @@ config CRYPTO_ECHAINIV
+ 	  a sequence number xored with a salt.  This is the default
+ 	  algorithm for CBC.
+ 
++config CRYPTO_TLS
++	tristate "TLS support"
++	select CRYPTO_AEAD
++	select CRYPTO_BLKCIPHER
++	select CRYPTO_MANAGER
++	select CRYPTO_HASH
++	select CRYPTO_NULL
++	select CRYPTO_AUTHENC
++	help
++	  Support for TLS 1.0 record encryption and decryption
++
++	  This module adds support for encryption/decryption of TLS 1.0 frames
++	  using blockcipher algorithms. The name of the resulting algorithm is
++	  "tls10(hmac(<digest>),cbc(<cipher>))". By default, the generic base
++	  algorithms are used (e.g. aes-generic, sha1-generic), but hardware
++	  accelerated versions will be used automatically if available.
++
++	  User-space applications (OpenSSL, GnuTLS) can offload TLS 1.0
++	  operations through AF_ALG or cryptodev interfaces
++
+ comment "Block modes"
+ 
+ config CRYPTO_CBC
+--- a/crypto/Makefile
++++ b/crypto/Makefile
+@@ -51,6 +51,9 @@ rsa_generic-y += rsa_helper.o
+ rsa_generic-y += rsa-pkcs1pad.o
+ obj-$(CONFIG_CRYPTO_RSA) += rsa_generic.o
+ 
++obj-$(CONFIG_CRYPTO_ACOMP2) += acompress.o
++obj-$(CONFIG_CRYPTO_ACOMP2) += scompress.o
++
+ cryptomgr-y := algboss.o testmgr.o
+ 
+ obj-$(CONFIG_CRYPTO_MANAGER2) += cryptomgr.o
+@@ -115,6 +118,7 @@ obj-$(CONFIG_CRYPTO_CRC32C) += crc32c_ge
+ obj-$(CONFIG_CRYPTO_CRC32) += crc32_generic.o
+ obj-$(CONFIG_CRYPTO_CRCT10DIF) += crct10dif_common.o crct10dif_generic.o
+ obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o
++obj-$(CONFIG_CRYPTO_TLS) += tls.o
+ obj-$(CONFIG_CRYPTO_LZO) += lzo.o
+ obj-$(CONFIG_CRYPTO_LZ4) += lz4.o
+ obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o
+--- /dev/null
++++ b/crypto/acompress.c
+@@ -0,0 +1,169 @@
++/*
++ * Asynchronous Compression operations
++ *
++ * Copyright (c) 2016, Intel Corporation
++ * Authors: Weigang Li <weigang.li@intel.com>
++ *          Giovanni Cabiddu <giovanni.cabiddu@intel.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; either version 2 of the License, or (at your option)
++ * any later version.
++ *
++ */
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/seq_file.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/crypto.h>
++#include <crypto/algapi.h>
++#include <linux/cryptouser.h>
++#include <net/netlink.h>
++#include <crypto/internal/acompress.h>
++#include <crypto/internal/scompress.h>
++#include "internal.h"
++
++static const struct crypto_type crypto_acomp_type;
++
++#ifdef CONFIG_NET
++static int crypto_acomp_report(struct sk_buff *skb, struct crypto_alg *alg)
++{
++	struct crypto_report_acomp racomp;
++
++	strncpy(racomp.type, "acomp", sizeof(racomp.type));
++
++	if (nla_put(skb, CRYPTOCFGA_REPORT_ACOMP,
++		    sizeof(struct crypto_report_acomp), &racomp))
++		goto nla_put_failure;
++	return 0;
++
++nla_put_failure:
++	return -EMSGSIZE;
++}
++#else
++static int crypto_acomp_report(struct sk_buff *skb, struct crypto_alg *alg)
++{
++	return -ENOSYS;
++}
++#endif
++
++static void crypto_acomp_show(struct seq_file *m, struct crypto_alg *alg)
++	__attribute__ ((unused));
++
++static void crypto_acomp_show(struct seq_file *m, struct crypto_alg *alg)
++{
++	seq_puts(m, "type         : acomp\n");
++}
++
++static void crypto_acomp_exit_tfm(struct crypto_tfm *tfm)
++{
++	struct crypto_acomp *acomp = __crypto_acomp_tfm(tfm);
++	struct acomp_alg *alg = crypto_acomp_alg(acomp);
++
++	alg->exit(acomp);
++}
++
++static int crypto_acomp_init_tfm(struct crypto_tfm *tfm)
++{
++	struct crypto_acomp *acomp = __crypto_acomp_tfm(tfm);
++	struct acomp_alg *alg = crypto_acomp_alg(acomp);
++
++	if (tfm->__crt_alg->cra_type != &crypto_acomp_type)
++		return crypto_init_scomp_ops_async(tfm);
++
++	acomp->compress = alg->compress;
++	acomp->decompress = alg->decompress;
++	acomp->dst_free = alg->dst_free;
++	acomp->reqsize = alg->reqsize;
++
++	if (alg->exit)
++		acomp->base.exit = crypto_acomp_exit_tfm;
++
++	if (alg->init)
++		return alg->init(acomp);
++
++	return 0;
++}
++
++static unsigned int crypto_acomp_extsize(struct crypto_alg *alg)
++{
++	int extsize = crypto_alg_extsize(alg);
++
++	if (alg->cra_type != &crypto_acomp_type)
++		extsize += sizeof(struct crypto_scomp *);
++
++	return extsize;
++}
++
++static const struct crypto_type crypto_acomp_type = {
++	.extsize = crypto_acomp_extsize,
++	.init_tfm = crypto_acomp_init_tfm,
++#ifdef CONFIG_PROC_FS
++	.show = crypto_acomp_show,
++#endif
++	.report = crypto_acomp_report,
++	.maskclear = ~CRYPTO_ALG_TYPE_MASK,
++	.maskset = CRYPTO_ALG_TYPE_ACOMPRESS_MASK,
++	.type = CRYPTO_ALG_TYPE_ACOMPRESS,
++	.tfmsize = offsetof(struct crypto_acomp, base),
++};
++
++struct crypto_acomp *crypto_alloc_acomp(const char *alg_name, u32 type,
++					u32 mask)
++{
++	return crypto_alloc_tfm(alg_name, &crypto_acomp_type, type, mask);
++}
++EXPORT_SYMBOL_GPL(crypto_alloc_acomp);
++
++struct acomp_req *acomp_request_alloc(struct crypto_acomp *acomp)
++{
++	struct crypto_tfm *tfm = crypto_acomp_tfm(acomp);
++	struct acomp_req *req;
++
++	req = __acomp_request_alloc(acomp);
++	if (req && (tfm->__crt_alg->cra_type != &crypto_acomp_type))
++		return crypto_acomp_scomp_alloc_ctx(req);
++
++	return req;
++}
++EXPORT_SYMBOL_GPL(acomp_request_alloc);
++
++void acomp_request_free(struct acomp_req *req)
++{
++	struct crypto_acomp *acomp = crypto_acomp_reqtfm(req);
++	struct crypto_tfm *tfm = crypto_acomp_tfm(acomp);
++
++	if (tfm->__crt_alg->cra_type != &crypto_acomp_type)
++		crypto_acomp_scomp_free_ctx(req);
++
++	if (req->flags & CRYPTO_ACOMP_ALLOC_OUTPUT) {
++		acomp->dst_free(req->dst);
++		req->dst = NULL;
++	}
++
++	__acomp_request_free(req);
++}
++EXPORT_SYMBOL_GPL(acomp_request_free);
++
++int crypto_register_acomp(struct acomp_alg *alg)
++{
++	struct crypto_alg *base = &alg->base;
++
++	base->cra_type = &crypto_acomp_type;
++	base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK;
++	base->cra_flags |= CRYPTO_ALG_TYPE_ACOMPRESS;
++
++	return crypto_register_alg(base);
++}
++EXPORT_SYMBOL_GPL(crypto_register_acomp);
++
++int crypto_unregister_acomp(struct acomp_alg *alg)
++{
++	return crypto_unregister_alg(&alg->base);
++}
++EXPORT_SYMBOL_GPL(crypto_unregister_acomp);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Asynchronous compression type");
+--- a/crypto/algboss.c
++++ b/crypto/algboss.c
+@@ -247,17 +247,9 @@ static int cryptomgr_schedule_test(struc
+ 	memcpy(param->alg, alg->cra_name, sizeof(param->alg));
+ 	type = alg->cra_flags;
+ 
+-	/* This piece of crap needs to disappear into per-type test hooks. */
+-#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS
+-	type |= CRYPTO_ALG_TESTED;
+-#else
+-	if (!((type ^ CRYPTO_ALG_TYPE_BLKCIPHER) &
+-	      CRYPTO_ALG_TYPE_BLKCIPHER_MASK) && !(type & CRYPTO_ALG_GENIV) &&
+-	    ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) ==
+-	     CRYPTO_ALG_TYPE_BLKCIPHER ? alg->cra_blkcipher.ivsize :
+-					 alg->cra_ablkcipher.ivsize))
++	/* Do not test internal algorithms. */
++	if (type & CRYPTO_ALG_INTERNAL)
+ 		type |= CRYPTO_ALG_TESTED;
+-#endif
+ 
+ 	param->type = type;
+ 
+--- a/crypto/crypto_user.c
++++ b/crypto/crypto_user.c
+@@ -112,6 +112,21 @@ nla_put_failure:
+ 	return -EMSGSIZE;
+ }
+ 
++static int crypto_report_acomp(struct sk_buff *skb, struct crypto_alg *alg)
++{
++	struct crypto_report_acomp racomp;
++
++	strncpy(racomp.type, "acomp", sizeof(racomp.type));
++
++	if (nla_put(skb, CRYPTOCFGA_REPORT_ACOMP,
++		    sizeof(struct crypto_report_acomp), &racomp))
++		goto nla_put_failure;
++	return 0;
++
++nla_put_failure:
++	return -EMSGSIZE;
++}
++
+ static int crypto_report_akcipher(struct sk_buff *skb, struct crypto_alg *alg)
+ {
+ 	struct crypto_report_akcipher rakcipher;
+@@ -186,7 +201,11 @@ static int crypto_report_one(struct cryp
+ 			goto nla_put_failure;
+ 
+ 		break;
++	case CRYPTO_ALG_TYPE_ACOMPRESS:
++		if (crypto_report_acomp(skb, alg))
++			goto nla_put_failure;
+ 
++		break;
+ 	case CRYPTO_ALG_TYPE_AKCIPHER:
+ 		if (crypto_report_akcipher(skb, alg))
+ 			goto nla_put_failure;
+--- /dev/null
++++ b/crypto/scompress.c
+@@ -0,0 +1,356 @@
++/*
++ * Synchronous Compression operations
++ *
++ * Copyright 2015 LG Electronics Inc.
++ * Copyright (c) 2016, Intel Corporation
++ * Author: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; either version 2 of the License, or (at your option)
++ * any later version.
++ *
++ */
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/seq_file.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/crypto.h>
++#include <linux/vmalloc.h>
++#include <crypto/algapi.h>
++#include <linux/cryptouser.h>
++#include <net/netlink.h>
++#include <linux/scatterlist.h>
++#include <crypto/scatterwalk.h>
++#include <crypto/internal/acompress.h>
++#include <crypto/internal/scompress.h>
++#include "internal.h"
++
++static const struct crypto_type crypto_scomp_type;
++static void * __percpu *scomp_src_scratches;
++static void * __percpu *scomp_dst_scratches;
++static int scomp_scratch_users;
++static DEFINE_MUTEX(scomp_lock);
++
++#ifdef CONFIG_NET
++static int crypto_scomp_report(struct sk_buff *skb, struct crypto_alg *alg)
++{
++	struct crypto_report_comp rscomp;
++
++	strncpy(rscomp.type, "scomp", sizeof(rscomp.type));
++
++	if (nla_put(skb, CRYPTOCFGA_REPORT_COMPRESS,
++		    sizeof(struct crypto_report_comp), &rscomp))
++		goto nla_put_failure;
++	return 0;
++
++nla_put_failure:
++	return -EMSGSIZE;
++}
++#else
++static int crypto_scomp_report(struct sk_buff *skb, struct crypto_alg *alg)
++{
++	return -ENOSYS;
++}
++#endif
++
++static void crypto_scomp_show(struct seq_file *m, struct crypto_alg *alg)
++	__attribute__ ((unused));
++
++static void crypto_scomp_show(struct seq_file *m, struct crypto_alg *alg)
++{
++	seq_puts(m, "type         : scomp\n");
++}
++
++static int crypto_scomp_init_tfm(struct crypto_tfm *tfm)
++{
++	return 0;
++}
++
++static void crypto_scomp_free_scratches(void * __percpu *scratches)
++{
++	int i;
++
++	if (!scratches)
++		return;
++
++	for_each_possible_cpu(i)
++		vfree(*per_cpu_ptr(scratches, i));
++
++	free_percpu(scratches);
++}
++
++static void * __percpu *crypto_scomp_alloc_scratches(void)
++{
++	void * __percpu *scratches;
++	int i;
++
++	scratches = alloc_percpu(void *);
++	if (!scratches)
++		return NULL;
++
++	for_each_possible_cpu(i) {
++		void *scratch;
++
++		scratch = vmalloc_node(SCOMP_SCRATCH_SIZE, cpu_to_node(i));
++		if (!scratch)
++			goto error;
++		*per_cpu_ptr(scratches, i) = scratch;
++	}
++
++	return scratches;
++
++error:
++	crypto_scomp_free_scratches(scratches);
++	return NULL;
++}
++
++static void crypto_scomp_free_all_scratches(void)
++{
++	if (!--scomp_scratch_users) {
++		crypto_scomp_free_scratches(scomp_src_scratches);
++		crypto_scomp_free_scratches(scomp_dst_scratches);
++		scomp_src_scratches = NULL;
++		scomp_dst_scratches = NULL;
++	}
++}
++
++static int crypto_scomp_alloc_all_scratches(void)
++{
++	if (!scomp_scratch_users++) {
++		scomp_src_scratches = crypto_scomp_alloc_scratches();
++		if (!scomp_src_scratches)
++			return -ENOMEM;
++		scomp_dst_scratches = crypto_scomp_alloc_scratches();
++		if (!scomp_dst_scratches)
++			return -ENOMEM;
++	}
++	return 0;
++}
++
++static void crypto_scomp_sg_free(struct scatterlist *sgl)
++{
++	int i, n;
++	struct page *page;
++
++	if (!sgl)
++		return;
++
++	n = sg_nents(sgl);
++	for_each_sg(sgl, sgl, n, i) {
++		page = sg_page(sgl);
++		if (page)
++			__free_page(page);
++	}
++
++	kfree(sgl);
++}
++
++static struct scatterlist *crypto_scomp_sg_alloc(size_t size, gfp_t gfp)
++{
++	struct scatterlist *sgl;
++	struct page *page;
++	int i, n;
++
++	n = ((size - 1) >> PAGE_SHIFT) + 1;
++
++	sgl = kmalloc_array(n, sizeof(struct scatterlist), gfp);
++	if (!sgl)
++		return NULL;
++
++	sg_init_table(sgl, n);
++
++	for (i = 0; i < n; i++) {
++		page = alloc_page(gfp);
++		if (!page)
++			goto err;
++		sg_set_page(sgl + i, page, PAGE_SIZE, 0);
++	}
++
++	return sgl;
++
++err:
++	sg_mark_end(sgl + i);
++	crypto_scomp_sg_free(sgl);
++	return NULL;
++}
++
++static int scomp_acomp_comp_decomp(struct acomp_req *req, int dir)
++{
++	struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
++	void **tfm_ctx = acomp_tfm_ctx(tfm);
++	struct crypto_scomp *scomp = *tfm_ctx;
++	void **ctx = acomp_request_ctx(req);
++	const int cpu = get_cpu();
++	u8 *scratch_src = *per_cpu_ptr(scomp_src_scratches, cpu);
++	u8 *scratch_dst = *per_cpu_ptr(scomp_dst_scratches, cpu);
++	int ret;
++
++	if (!req->src || !req->slen || req->slen > SCOMP_SCRATCH_SIZE) {
++		ret = -EINVAL;
++		goto out;
++	}
++
++	if (req->dst && !req->dlen) {
++		ret = -EINVAL;
++		goto out;
++	}
++
++	if (!req->dlen || req->dlen > SCOMP_SCRATCH_SIZE)
++		req->dlen = SCOMP_SCRATCH_SIZE;
++
++	scatterwalk_map_and_copy(scratch_src, req->src, 0, req->slen, 0);
++	if (dir)
++		ret = crypto_scomp_compress(scomp, scratch_src, req->slen,
++					    scratch_dst, &req->dlen, *ctx);
++	else
++		ret = crypto_scomp_decompress(scomp, scratch_src, req->slen,
++					      scratch_dst, &req->dlen, *ctx);
++	if (!ret) {
++		if (!req->dst) {
++			req->dst = crypto_scomp_sg_alloc(req->dlen,
++				   req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
++				   GFP_KERNEL : GFP_ATOMIC);
++			if (!req->dst)
++				goto out;
++		}
++		scatterwalk_map_and_copy(scratch_dst, req->dst, 0, req->dlen,
++					 1);
++	}
++out:
++	put_cpu();
++	return ret;
++}
++
++static int scomp_acomp_compress(struct acomp_req *req)
++{
++	return scomp_acomp_comp_decomp(req, 1);
++}
++
++static int scomp_acomp_decompress(struct acomp_req *req)
++{
++	return scomp_acomp_comp_decomp(req, 0);
++}
++
++static void crypto_exit_scomp_ops_async(struct crypto_tfm *tfm)
++{
++	struct crypto_scomp **ctx = crypto_tfm_ctx(tfm);
++
++	crypto_free_scomp(*ctx);
++}
++
++int crypto_init_scomp_ops_async(struct crypto_tfm *tfm)
++{
++	struct crypto_alg *calg = tfm->__crt_alg;
++	struct crypto_acomp *crt = __crypto_acomp_tfm(tfm);
++	struct crypto_scomp **ctx = crypto_tfm_ctx(tfm);
++	struct crypto_scomp *scomp;
++
++	if (!crypto_mod_get(calg))
++		return -EAGAIN;
++
++	scomp = crypto_create_tfm(calg, &crypto_scomp_type);
++	if (IS_ERR(scomp)) {
++		crypto_mod_put(calg);
++		return PTR_ERR(scomp);
++	}
++
++	*ctx = scomp;
++	tfm->exit = crypto_exit_scomp_ops_async;
++
++	crt->compress = scomp_acomp_compress;
++	crt->decompress = scomp_acomp_decompress;
++	crt->dst_free = crypto_scomp_sg_free;
++	crt->reqsize = sizeof(void *);
++
++	return 0;
++}
++
++struct acomp_req *crypto_acomp_scomp_alloc_ctx(struct acomp_req *req)
++{
++	struct crypto_acomp *acomp = crypto_acomp_reqtfm(req);
++	struct crypto_tfm *tfm = crypto_acomp_tfm(acomp);
++	struct crypto_scomp **tfm_ctx = crypto_tfm_ctx(tfm);
++	struct crypto_scomp *scomp = *tfm_ctx;
++	void *ctx;
++
++	ctx = crypto_scomp_alloc_ctx(scomp);
++	if (IS_ERR(ctx)) {
++		kfree(req);
++		return NULL;
++	}
++
++	*req->__ctx = ctx;
++
++	return req;
++}
++
++void crypto_acomp_scomp_free_ctx(struct acomp_req *req)
++{
++	struct crypto_acomp *acomp = crypto_acomp_reqtfm(req);
++	struct crypto_tfm *tfm = crypto_acomp_tfm(acomp);
++	struct crypto_scomp **tfm_ctx = crypto_tfm_ctx(tfm);
++	struct crypto_scomp *scomp = *tfm_ctx;
++	void *ctx = *req->__ctx;
++
++	if (ctx)
++		crypto_scomp_free_ctx(scomp, ctx);
++}
++
++static const struct crypto_type crypto_scomp_type = {
++	.extsize = crypto_alg_extsize,
++	.init_tfm = crypto_scomp_init_tfm,
++#ifdef CONFIG_PROC_FS
++	.show = crypto_scomp_show,
++#endif
++	.report = crypto_scomp_report,
++	.maskclear = ~CRYPTO_ALG_TYPE_MASK,
++	.maskset = CRYPTO_ALG_TYPE_MASK,
++	.type = CRYPTO_ALG_TYPE_SCOMPRESS,
++	.tfmsize = offsetof(struct crypto_scomp, base),
++};
++
++int crypto_register_scomp(struct scomp_alg *alg)
++{
++	struct crypto_alg *base = &alg->base;
++	int ret = -ENOMEM;
++
++	mutex_lock(&scomp_lock);
++	if (crypto_scomp_alloc_all_scratches())
++		goto error;
++
++	base->cra_type = &crypto_scomp_type;
++	base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK;
++	base->cra_flags |= CRYPTO_ALG_TYPE_SCOMPRESS;
++
++	ret = crypto_register_alg(base);
++	if (ret)
++		goto error;
++
++	mutex_unlock(&scomp_lock);
++	return ret;
++
++error:
++	crypto_scomp_free_all_scratches();
++	mutex_unlock(&scomp_lock);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(crypto_register_scomp);
++
++int crypto_unregister_scomp(struct scomp_alg *alg)
++{
++	int ret;
++
++	mutex_lock(&scomp_lock);
++	ret = crypto_unregister_alg(&alg->base);
++	crypto_scomp_free_all_scratches();
++	mutex_unlock(&scomp_lock);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(crypto_unregister_scomp);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Synchronous compression type");
+--- a/crypto/tcrypt.c
++++ b/crypto/tcrypt.c
+@@ -74,7 +74,7 @@ static char *check[] = {
+ 	"khazad", "wp512", "wp384", "wp256", "tnepres", "xeta",  "fcrypt",
+ 	"camellia", "seed", "salsa20", "rmd128", "rmd160", "rmd256", "rmd320",
+ 	"lzo", "cts", "zlib", "sha3-224", "sha3-256", "sha3-384", "sha3-512",
+-	NULL
++	"rsa", NULL
+ };
+ 
+ struct tcrypt_result {
+@@ -1336,6 +1336,10 @@ static int do_test(const char *alg, u32
+ 		ret += tcrypt_test("hmac(sha3-512)");
+ 		break;
+ 
++	case 115:
++		ret += tcrypt_test("rsa");
++		break;
++
+ 	case 150:
+ 		ret += tcrypt_test("ansi_cprng");
+ 		break;
+@@ -1397,6 +1401,9 @@ static int do_test(const char *alg, u32
+ 	case 190:
+ 		ret += tcrypt_test("authenc(hmac(sha512),cbc(des3_ede))");
+ 		break;
++	case 191:
++		ret += tcrypt_test("tls10(hmac(sha1),cbc(aes))");
++		break;
+ 	case 200:
+ 		test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0,
+ 				speed_template_16_24_32);
+@@ -1411,9 +1418,9 @@ static int do_test(const char *alg, u32
+ 		test_cipher_speed("lrw(aes)", DECRYPT, sec, NULL, 0,
+ 				speed_template_32_40_48);
+ 		test_cipher_speed("xts(aes)", ENCRYPT, sec, NULL, 0,
+-				speed_template_32_48_64);
++				speed_template_32_64);
+ 		test_cipher_speed("xts(aes)", DECRYPT, sec, NULL, 0,
+-				speed_template_32_48_64);
++				speed_template_32_64);
+ 		test_cipher_speed("cts(cbc(aes))", ENCRYPT, sec, NULL, 0,
+ 				speed_template_16_24_32);
+ 		test_cipher_speed("cts(cbc(aes))", DECRYPT, sec, NULL, 0,
+@@ -1844,9 +1851,9 @@ static int do_test(const char *alg, u32
+ 		test_acipher_speed("lrw(aes)", DECRYPT, sec, NULL, 0,
+ 				   speed_template_32_40_48);
+ 		test_acipher_speed("xts(aes)", ENCRYPT, sec, NULL, 0,
+-				   speed_template_32_48_64);
++				   speed_template_32_64);
+ 		test_acipher_speed("xts(aes)", DECRYPT, sec, NULL, 0,
+-				   speed_template_32_48_64);
++				   speed_template_32_64);
+ 		test_acipher_speed("cts(cbc(aes))", ENCRYPT, sec, NULL, 0,
+ 				   speed_template_16_24_32);
+ 		test_acipher_speed("cts(cbc(aes))", DECRYPT, sec, NULL, 0,
+--- a/crypto/testmgr.c
++++ b/crypto/testmgr.c
+@@ -33,6 +33,7 @@
+ #include <crypto/drbg.h>
+ #include <crypto/akcipher.h>
+ #include <crypto/kpp.h>
++#include <crypto/acompress.h>
+ 
+ #include "internal.h"
+ 
+@@ -62,7 +63,7 @@ int alg_test(const char *driver, const c
+  */
+ #define IDX1		32
+ #define IDX2		32400
+-#define IDX3		1
++#define IDX3		1511
+ #define IDX4		8193
+ #define IDX5		22222
+ #define IDX6		17101
+@@ -82,47 +83,54 @@ struct tcrypt_result {
+ 
+ struct aead_test_suite {
+ 	struct {
+-		struct aead_testvec *vecs;
++		const struct aead_testvec *vecs;
+ 		unsigned int count;
+ 	} enc, dec;
+ };
+ 
+ struct cipher_test_suite {
+ 	struct {
+-		struct cipher_testvec *vecs;
++		const struct cipher_testvec *vecs;
+ 		unsigned int count;
+ 	} enc, dec;
+ };
+ 
+ struct comp_test_suite {
+ 	struct {
+-		struct comp_testvec *vecs;
++		const struct comp_testvec *vecs;
+ 		unsigned int count;
+ 	} comp, decomp;
+ };
+ 
+ struct hash_test_suite {
+-	struct hash_testvec *vecs;
++	const struct hash_testvec *vecs;
+ 	unsigned int count;
+ };
+ 
+ struct cprng_test_suite {
+-	struct cprng_testvec *vecs;
++	const struct cprng_testvec *vecs;
+ 	unsigned int count;
+ };
+ 
+ struct drbg_test_suite {
+-	struct drbg_testvec *vecs;
++	const struct drbg_testvec *vecs;
+ 	unsigned int count;
+ };
+ 
++struct tls_test_suite {
++	struct {
++		struct tls_testvec *vecs;
++		unsigned int count;
++	} enc, dec;
++};
++
+ struct akcipher_test_suite {
+-	struct akcipher_testvec *vecs;
++	const struct akcipher_testvec *vecs;
+ 	unsigned int count;
+ };
+ 
+ struct kpp_test_suite {
+-	struct kpp_testvec *vecs;
++	const struct kpp_testvec *vecs;
+ 	unsigned int count;
+ };
+ 
+@@ -139,12 +147,14 @@ struct alg_test_desc {
+ 		struct hash_test_suite hash;
+ 		struct cprng_test_suite cprng;
+ 		struct drbg_test_suite drbg;
++		struct tls_test_suite tls;
+ 		struct akcipher_test_suite akcipher;
+ 		struct kpp_test_suite kpp;
+ 	} suite;
+ };
+ 
+-static unsigned int IDX[8] = { IDX1, IDX2, IDX3, IDX4, IDX5, IDX6, IDX7, IDX8 };
++static const unsigned int IDX[8] = {
++	IDX1, IDX2, IDX3, IDX4, IDX5, IDX6, IDX7, IDX8 };
+ 
+ static void hexdump(unsigned char *buf, unsigned int len)
+ {
+@@ -202,7 +212,7 @@ static int wait_async_op(struct tcrypt_r
+ }
+ 
+ static int ahash_partial_update(struct ahash_request **preq,
+-	struct crypto_ahash *tfm, struct hash_testvec *template,
++	struct crypto_ahash *tfm, const struct hash_testvec *template,
+ 	void *hash_buff, int k, int temp, struct scatterlist *sg,
+ 	const char *algo, char *result, struct tcrypt_result *tresult)
+ {
+@@ -259,11 +269,12 @@ out_nostate:
+ 	return ret;
+ }
+ 
+-static int __test_hash(struct crypto_ahash *tfm, struct hash_testvec *template,
+-		       unsigned int tcount, bool use_digest,
+-		       const int align_offset)
++static int __test_hash(struct crypto_ahash *tfm,
++		       const struct hash_testvec *template, unsigned int tcount,
++		       bool use_digest, const int align_offset)
+ {
+ 	const char *algo = crypto_tfm_alg_driver_name(crypto_ahash_tfm(tfm));
++	size_t digest_size = crypto_ahash_digestsize(tfm);
+ 	unsigned int i, j, k, temp;
+ 	struct scatterlist sg[8];
+ 	char *result;
+@@ -274,7 +285,7 @@ static int __test_hash(struct crypto_aha
+ 	char *xbuf[XBUFSIZE];
+ 	int ret = -ENOMEM;
+ 
+-	result = kmalloc(MAX_DIGEST_SIZE, GFP_KERNEL);
++	result = kmalloc(digest_size, GFP_KERNEL);
+ 	if (!result)
+ 		return ret;
+ 	key = kmalloc(MAX_KEYLEN, GFP_KERNEL);
+@@ -304,7 +315,7 @@ static int __test_hash(struct crypto_aha
+ 			goto out;
+ 
+ 		j++;
+-		memset(result, 0, MAX_DIGEST_SIZE);
++		memset(result, 0, digest_size);
+ 
+ 		hash_buff = xbuf[0];
+ 		hash_buff += align_offset;
+@@ -379,7 +390,7 @@ static int __test_hash(struct crypto_aha
+ 			continue;
+ 
+ 		j++;
+-		memset(result, 0, MAX_DIGEST_SIZE);
++		memset(result, 0, digest_size);
+ 
+ 		temp = 0;
+ 		sg_init_table(sg, template[i].np);
+@@ -457,7 +468,7 @@ static int __test_hash(struct crypto_aha
+ 			continue;
+ 
+ 		j++;
+-		memset(result, 0, MAX_DIGEST_SIZE);
++		memset(result, 0, digest_size);
+ 
+ 		ret = -EINVAL;
+ 		hash_buff = xbuf[0];
+@@ -536,7 +547,8 @@ out_nobuf:
+ 	return ret;
+ }
+ 
+-static int test_hash(struct crypto_ahash *tfm, struct hash_testvec *template,
++static int test_hash(struct crypto_ahash *tfm,
++		     const struct hash_testvec *template,
+ 		     unsigned int tcount, bool use_digest)
+ {
+ 	unsigned int alignmask;
+@@ -564,7 +576,7 @@ static int test_hash(struct crypto_ahash
+ }
+ 
+ static int __test_aead(struct crypto_aead *tfm, int enc,
+-		       struct aead_testvec *template, unsigned int tcount,
++		       const struct aead_testvec *template, unsigned int tcount,
+ 		       const bool diff_dst, const int align_offset)
+ {
+ 	const char *algo = crypto_tfm_alg_driver_name(crypto_aead_tfm(tfm));
+@@ -955,7 +967,7 @@ out_noxbuf:
+ }
+ 
+ static int test_aead(struct crypto_aead *tfm, int enc,
+-		     struct aead_testvec *template, unsigned int tcount)
++		     const struct aead_testvec *template, unsigned int tcount)
+ {
+ 	unsigned int alignmask;
+ 	int ret;
+@@ -987,8 +999,236 @@ static int test_aead(struct crypto_aead
+ 	return 0;
+ }
+ 
++static int __test_tls(struct crypto_aead *tfm, int enc,
++		      struct tls_testvec *template, unsigned int tcount,
++		      const bool diff_dst)
++{
++	const char *algo = crypto_tfm_alg_driver_name(crypto_aead_tfm(tfm));
++	unsigned int i, k, authsize;
++	char *q;
++	struct aead_request *req;
++	struct scatterlist *sg;
++	struct scatterlist *sgout;
++	const char *e, *d;
++	struct tcrypt_result result;
++	void *input;
++	void *output;
++	void *assoc;
++	char *iv;
++	char *key;
++	char *xbuf[XBUFSIZE];
++	char *xoutbuf[XBUFSIZE];
++	char *axbuf[XBUFSIZE];
++	int ret = -ENOMEM;
++
++	if (testmgr_alloc_buf(xbuf))
++		goto out_noxbuf;
++
++	if (diff_dst && testmgr_alloc_buf(xoutbuf))
++		goto out_nooutbuf;
++
++	if (testmgr_alloc_buf(axbuf))
++		goto out_noaxbuf;
++
++	iv = kzalloc(MAX_IVLEN, GFP_KERNEL);
++	if (!iv)
++		goto out_noiv;
++
++	key = kzalloc(MAX_KEYLEN, GFP_KERNEL);
++	if (!key)
++		goto out_nokey;
++
++	sg = kmalloc(sizeof(*sg) * 8 * (diff_dst ? 2 : 1), GFP_KERNEL);
++	if (!sg)
++		goto out_nosg;
++
++	sgout = sg + 8;
++
++	d = diff_dst ? "-ddst" : "";
++	e = enc ? "encryption" : "decryption";
++
++	init_completion(&result.completion);
++
++	req = aead_request_alloc(tfm, GFP_KERNEL);
++	if (!req) {
++		pr_err("alg: tls%s: Failed to allocate request for %s\n",
++		       d, algo);
++		goto out;
++	}
++
++	aead_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
++				  tcrypt_complete, &result);
++
++	for (i = 0; i < tcount; i++) {
++		input = xbuf[0];
++		assoc = axbuf[0];
++
++		ret = -EINVAL;
++		if (WARN_ON(template[i].ilen > PAGE_SIZE ||
++			    template[i].alen > PAGE_SIZE))
++			goto out;
++
++		memcpy(assoc, template[i].assoc, template[i].alen);
++		memcpy(input, template[i].input, template[i].ilen);
++
++		if (template[i].iv)
++			memcpy(iv, template[i].iv, MAX_IVLEN);
++		else
++			memset(iv, 0, MAX_IVLEN);
++
++		crypto_aead_clear_flags(tfm, ~0);
++
++		if (template[i].klen > MAX_KEYLEN) {
++			pr_err("alg: aead%s: setkey failed on test %d for %s: key size %d > %d\n",
++			       d, i, algo, template[i].klen, MAX_KEYLEN);
++			ret = -EINVAL;
++			goto out;
++		}
++		memcpy(key, template[i].key, template[i].klen);
++
++		ret = crypto_aead_setkey(tfm, key, template[i].klen);
++		if (!ret == template[i].fail) {
++			pr_err("alg: tls%s: setkey failed on test %d for %s: flags=%x\n",
++			       d, i, algo, crypto_aead_get_flags(tfm));
++			goto out;
++		} else if (ret)
++			continue;
++
++		authsize = 20;
++		ret = crypto_aead_setauthsize(tfm, authsize);
++		if (ret) {
++			pr_err("alg: aead%s: Failed to set authsize to %u on test %d for %s\n",
++			       d, authsize, i, algo);
++			goto out;
++		}
++
++		k = !!template[i].alen;
++		sg_init_table(sg, k + 1);
++		sg_set_buf(&sg[0], assoc, template[i].alen);
++		sg_set_buf(&sg[k], input, (enc ? template[i].rlen :
++					   template[i].ilen));
++		output = input;
++
++		if (diff_dst) {
++			sg_init_table(sgout, k + 1);
++			sg_set_buf(&sgout[0], assoc, template[i].alen);
++
++			output = xoutbuf[0];
++			sg_set_buf(&sgout[k], output,
++				   (enc ? template[i].rlen : template[i].ilen));
++		}
++
++		aead_request_set_crypt(req, sg, (diff_dst) ? sgout : sg,
++				       template[i].ilen, iv);
++
++		aead_request_set_ad(req, template[i].alen);
++
++		ret = enc ? crypto_aead_encrypt(req) : crypto_aead_decrypt(req);
++
++		switch (ret) {
++		case 0:
++			if (template[i].novrfy) {
++				/* verification was supposed to fail */
++				pr_err("alg: tls%s: %s failed on test %d for %s: ret was 0, expected -EBADMSG\n",
++				       d, e, i, algo);
++				/* so really, we got a bad message */
++				ret = -EBADMSG;
++				goto out;
++			}
++			break;
++		case -EINPROGRESS:
++		case -EBUSY:
++			wait_for_completion(&result.completion);
++			reinit_completion(&result.completion);
++			ret = result.err;
++			if (!ret)
++				break;
++		case -EBADMSG:
++			/* verification failure was expected */
++			if (template[i].novrfy)
++				continue;
++			/* fall through */
++		default:
++			pr_err("alg: tls%s: %s failed on test %d for %s: ret=%d\n",
++			       d, e, i, algo, -ret);
++			goto out;
++		}
++
++		q = output;
++		if (memcmp(q, template[i].result, template[i].rlen)) {
++			pr_err("alg: tls%s: Test %d failed on %s for %s\n",
++			       d, i, e, algo);
++			hexdump(q, template[i].rlen);
++			pr_err("should be:\n");
++			hexdump(template[i].result, template[i].rlen);
++			ret = -EINVAL;
++			goto out;
++		}
++	}
++
++out:
++	aead_request_free(req);
++
++	kfree(sg);
++out_nosg:
++	kfree(key);
++out_nokey:
++	kfree(iv);
++out_noiv:
++	testmgr_free_buf(axbuf);
++out_noaxbuf:
++	if (diff_dst)
++		testmgr_free_buf(xoutbuf);
++out_nooutbuf:
++	testmgr_free_buf(xbuf);
++out_noxbuf:
++	return ret;
++}
++
++static int test_tls(struct crypto_aead *tfm, int enc,
++		    struct tls_testvec *template, unsigned int tcount)
++{
++	int ret;
++	/* test 'dst == src' case */
++	ret = __test_tls(tfm, enc, template, tcount, false);
++	if (ret)
++		return ret;
++	/* test 'dst != src' case */
++	return __test_tls(tfm, enc, template, tcount, true);
++}
++
++static int alg_test_tls(const struct alg_test_desc *desc, const char *driver,
++			u32 type, u32 mask)
++{
++	struct crypto_aead *tfm;
++	int err = 0;
++
++	tfm = crypto_alloc_aead(driver, type, mask);
++	if (IS_ERR(tfm)) {
++		pr_err("alg: aead: Failed to load transform for %s: %ld\n",
++		       driver, PTR_ERR(tfm));
++		return PTR_ERR(tfm);
++	}
++
++	if (desc->suite.tls.enc.vecs) {
++		err = test_tls(tfm, ENCRYPT, desc->suite.tls.enc.vecs,
++			       desc->suite.tls.enc.count);
++		if (err)
++			goto out;
++	}
++
++	if (!err && desc->suite.tls.dec.vecs)
++		err = test_tls(tfm, DECRYPT, desc->suite.tls.dec.vecs,
++			       desc->suite.tls.dec.count);
++
++out:
++	crypto_free_aead(tfm);
++	return err;
++}
++
+ static int test_cipher(struct crypto_cipher *tfm, int enc,
+-		       struct cipher_testvec *template, unsigned int tcount)
++		       const struct cipher_testvec *template,
++		       unsigned int tcount)
+ {
+ 	const char *algo = crypto_tfm_alg_driver_name(crypto_cipher_tfm(tfm));
+ 	unsigned int i, j, k;
+@@ -1066,7 +1306,8 @@ out_nobuf:
+ }
+ 
+ static int __test_skcipher(struct crypto_skcipher *tfm, int enc,
+-			   struct cipher_testvec *template, unsigned int tcount,
++			   const struct cipher_testvec *template,
++			   unsigned int tcount,
+ 			   const bool diff_dst, const int align_offset)
+ {
+ 	const char *algo =
+@@ -1079,12 +1320,16 @@ static int __test_skcipher(struct crypto
+ 	const char *e, *d;
+ 	struct tcrypt_result result;
+ 	void *data;
+-	char iv[MAX_IVLEN];
++	char *iv;
+ 	char *xbuf[XBUFSIZE];
+ 	char *xoutbuf[XBUFSIZE];
+ 	int ret = -ENOMEM;
+ 	unsigned int ivsize = crypto_skcipher_ivsize(tfm);
+ 
++	iv = kmalloc(MAX_IVLEN, GFP_KERNEL);
++	if (!iv)
++		return ret;
++
+ 	if (testmgr_alloc_buf(xbuf))
+ 		goto out_nobuf;
+ 
+@@ -1325,12 +1570,14 @@ out:
+ 		testmgr_free_buf(xoutbuf);
+ out_nooutbuf:
+ 	testmgr_free_buf(xbuf);
++	kfree(iv);
+ out_nobuf:
+ 	return ret;
+ }
+ 
+ static int test_skcipher(struct crypto_skcipher *tfm, int enc,
+-			 struct cipher_testvec *template, unsigned int tcount)
++			 const struct cipher_testvec *template,
++			 unsigned int tcount)
+ {
+ 	unsigned int alignmask;
+ 	int ret;
+@@ -1362,8 +1609,10 @@ static int test_skcipher(struct crypto_s
+ 	return 0;
+ }
+ 
+-static int test_comp(struct crypto_comp *tfm, struct comp_testvec *ctemplate,
+-		     struct comp_testvec *dtemplate, int ctcount, int dtcount)
++static int test_comp(struct crypto_comp *tfm,
++		     const struct comp_testvec *ctemplate,
++		     const struct comp_testvec *dtemplate,
++		     int ctcount, int dtcount)
+ {
+ 	const char *algo = crypto_tfm_alg_driver_name(crypto_comp_tfm(tfm));
+ 	unsigned int i;
+@@ -1442,7 +1691,154 @@ out:
+ 	return ret;
+ }
+ 
+-static int test_cprng(struct crypto_rng *tfm, struct cprng_testvec *template,
++static int test_acomp(struct crypto_acomp *tfm,
++		      const struct comp_testvec *ctemplate,
++		      const struct comp_testvec *dtemplate,
++		      int ctcount, int dtcount)
++{
++	const char *algo = crypto_tfm_alg_driver_name(crypto_acomp_tfm(tfm));
++	unsigned int i;
++	char *output;
++	int ret;
++	struct scatterlist src, dst;
++	struct acomp_req *req;
++	struct tcrypt_result result;
++
++	output = kmalloc(COMP_BUF_SIZE, GFP_KERNEL);
++	if (!output)
++		return -ENOMEM;
++
++	for (i = 0; i < ctcount; i++) {
++		unsigned int dlen = COMP_BUF_SIZE;
++		int ilen = ctemplate[i].inlen;
++		void *input_vec;
++
++		input_vec = kmemdup(ctemplate[i].input, ilen, GFP_KERNEL);
++		if (!input_vec) {
++			ret = -ENOMEM;
++			goto out;
++		}
++
++		memset(output, 0, dlen);
++		init_completion(&result.completion);
++		sg_init_one(&src, input_vec, ilen);
++		sg_init_one(&dst, output, dlen);
++
++		req = acomp_request_alloc(tfm);
++		if (!req) {
++			pr_err("alg: acomp: request alloc failed for %s\n",
++			       algo);
++			kfree(input_vec);
++			ret = -ENOMEM;
++			goto out;
++		}
++
++		acomp_request_set_params(req, &src, &dst, ilen, dlen);
++		acomp_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
++					   tcrypt_complete, &result);
++
++		ret = wait_async_op(&result, crypto_acomp_compress(req));
++		if (ret) {
++			pr_err("alg: acomp: compression failed on test %d for %s: ret=%d\n",
++			       i + 1, algo, -ret);
++			kfree(input_vec);
++			acomp_request_free(req);
++			goto out;
++		}
++
++		if (req->dlen != ctemplate[i].outlen) {
++			pr_err("alg: acomp: Compression test %d failed for %s: output len = %d\n",
++			       i + 1, algo, req->dlen);
++			ret = -EINVAL;
++			kfree(input_vec);
++			acomp_request_free(req);
++			goto out;
++		}
++
++		if (memcmp(output, ctemplate[i].output, req->dlen)) {
++			pr_err("alg: acomp: Compression test %d failed for %s\n",
++			       i + 1, algo);
++			hexdump(output, req->dlen);
++			ret = -EINVAL;
++			kfree(input_vec);
++			acomp_request_free(req);
++			goto out;
++		}
++
++		kfree(input_vec);
++		acomp_request_free(req);
++	}
++
++	for (i = 0; i < dtcount; i++) {
++		unsigned int dlen = COMP_BUF_SIZE;
++		int ilen = dtemplate[i].inlen;
++		void *input_vec;
++
++		input_vec = kmemdup(dtemplate[i].input, ilen, GFP_KERNEL);
++		if (!input_vec) {
++			ret = -ENOMEM;
++			goto out;
++		}
++
++		memset(output, 0, dlen);
++		init_completion(&result.completion);
++		sg_init_one(&src, input_vec, ilen);
++		sg_init_one(&dst, output, dlen);
++
++		req = acomp_request_alloc(tfm);
++		if (!req) {
++			pr_err("alg: acomp: request alloc failed for %s\n",
++			       algo);
++			kfree(input_vec);
++			ret = -ENOMEM;
++			goto out;
++		}
++
++		acomp_request_set_params(req, &src, &dst, ilen, dlen);
++		acomp_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
++					   tcrypt_complete, &result);
++
++		ret = wait_async_op(&result, crypto_acomp_decompress(req));
++		if (ret) {
++			pr_err("alg: acomp: decompression failed on test %d for %s: ret=%d\n",
++			       i + 1, algo, -ret);
++			kfree(input_vec);
++			acomp_request_free(req);
++			goto out;
++		}
++
++		if (req->dlen != dtemplate[i].outlen) {
++			pr_err("alg: acomp: Decompression test %d failed for %s: output len = %d\n",
++			       i + 1, algo, req->dlen);
++			ret = -EINVAL;
++			kfree(input_vec);
++			acomp_request_free(req);
++			goto out;
++		}
++
++		if (memcmp(output, dtemplate[i].output, req->dlen)) {
++			pr_err("alg: acomp: Decompression test %d failed for %s\n",
++			       i + 1, algo);
++			hexdump(output, req->dlen);
++			ret = -EINVAL;
++			kfree(input_vec);
++			acomp_request_free(req);
++			goto out;
++		}
++
++		kfree(input_vec);
++		acomp_request_free(req);
++	}
++
++	ret = 0;
++
++out:
++	kfree(output);
++	return ret;
++}
++
++static int test_cprng(struct crypto_rng *tfm,
++		      const struct cprng_testvec *template,
+ 		      unsigned int tcount)
+ {
+ 	const char *algo = crypto_tfm_alg_driver_name(crypto_rng_tfm(tfm));
+@@ -1509,7 +1905,7 @@ static int alg_test_aead(const struct al
+ 	struct crypto_aead *tfm;
+ 	int err = 0;
+ 
+-	tfm = crypto_alloc_aead(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	tfm = crypto_alloc_aead(driver, type, mask);
+ 	if (IS_ERR(tfm)) {
+ 		printk(KERN_ERR "alg: aead: Failed to load transform for %s: "
+ 		       "%ld\n", driver, PTR_ERR(tfm));
+@@ -1538,7 +1934,7 @@ static int alg_test_cipher(const struct
+ 	struct crypto_cipher *tfm;
+ 	int err = 0;
+ 
+-	tfm = crypto_alloc_cipher(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	tfm = crypto_alloc_cipher(driver, type, mask);
+ 	if (IS_ERR(tfm)) {
+ 		printk(KERN_ERR "alg: cipher: Failed to load transform for "
+ 		       "%s: %ld\n", driver, PTR_ERR(tfm));
+@@ -1567,7 +1963,7 @@ static int alg_test_skcipher(const struc
+ 	struct crypto_skcipher *tfm;
+ 	int err = 0;
+ 
+-	tfm = crypto_alloc_skcipher(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	tfm = crypto_alloc_skcipher(driver, type, mask);
+ 	if (IS_ERR(tfm)) {
+ 		printk(KERN_ERR "alg: skcipher: Failed to load transform for "
+ 		       "%s: %ld\n", driver, PTR_ERR(tfm));
+@@ -1593,22 +1989,38 @@ out:
+ static int alg_test_comp(const struct alg_test_desc *desc, const char *driver,
+ 			 u32 type, u32 mask)
+ {
+-	struct crypto_comp *tfm;
++	struct crypto_comp *comp;
++	struct crypto_acomp *acomp;
+ 	int err;
++	u32 algo_type = type & CRYPTO_ALG_TYPE_ACOMPRESS_MASK;
+ 
+-	tfm = crypto_alloc_comp(driver, type, mask);
+-	if (IS_ERR(tfm)) {
+-		printk(KERN_ERR "alg: comp: Failed to load transform for %s: "
+-		       "%ld\n", driver, PTR_ERR(tfm));
+-		return PTR_ERR(tfm);
+-	}
++	if (algo_type == CRYPTO_ALG_TYPE_ACOMPRESS) {
++		acomp = crypto_alloc_acomp(driver, type, mask);
++		if (IS_ERR(acomp)) {
++			pr_err("alg: acomp: Failed to load transform for %s: %ld\n",
++			       driver, PTR_ERR(acomp));
++			return PTR_ERR(acomp);
++		}
++		err = test_acomp(acomp, desc->suite.comp.comp.vecs,
++				 desc->suite.comp.decomp.vecs,
++				 desc->suite.comp.comp.count,
++				 desc->suite.comp.decomp.count);
++		crypto_free_acomp(acomp);
++	} else {
++		comp = crypto_alloc_comp(driver, type, mask);
++		if (IS_ERR(comp)) {
++			pr_err("alg: comp: Failed to load transform for %s: %ld\n",
++			       driver, PTR_ERR(comp));
++			return PTR_ERR(comp);
++		}
+ 
+-	err = test_comp(tfm, desc->suite.comp.comp.vecs,
+-			desc->suite.comp.decomp.vecs,
+-			desc->suite.comp.comp.count,
+-			desc->suite.comp.decomp.count);
++		err = test_comp(comp, desc->suite.comp.comp.vecs,
++				desc->suite.comp.decomp.vecs,
++				desc->suite.comp.comp.count,
++				desc->suite.comp.decomp.count);
+ 
+-	crypto_free_comp(tfm);
++		crypto_free_comp(comp);
++	}
+ 	return err;
+ }
+ 
+@@ -1618,7 +2030,7 @@ static int alg_test_hash(const struct al
+ 	struct crypto_ahash *tfm;
+ 	int err;
+ 
+-	tfm = crypto_alloc_ahash(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	tfm = crypto_alloc_ahash(driver, type, mask);
+ 	if (IS_ERR(tfm)) {
+ 		printk(KERN_ERR "alg: hash: Failed to load transform for %s: "
+ 		       "%ld\n", driver, PTR_ERR(tfm));
+@@ -1646,7 +2058,7 @@ static int alg_test_crc32c(const struct
+ 	if (err)
+ 		goto out;
+ 
+-	tfm = crypto_alloc_shash(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	tfm = crypto_alloc_shash(driver, type, mask);
+ 	if (IS_ERR(tfm)) {
+ 		printk(KERN_ERR "alg: crc32c: Failed to load transform for %s: "
+ 		       "%ld\n", driver, PTR_ERR(tfm));
+@@ -1688,7 +2100,7 @@ static int alg_test_cprng(const struct a
+ 	struct crypto_rng *rng;
+ 	int err;
+ 
+-	rng = crypto_alloc_rng(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	rng = crypto_alloc_rng(driver, type, mask);
+ 	if (IS_ERR(rng)) {
+ 		printk(KERN_ERR "alg: cprng: Failed to load transform for %s: "
+ 		       "%ld\n", driver, PTR_ERR(rng));
+@@ -1703,7 +2115,7 @@ static int alg_test_cprng(const struct a
+ }
+ 
+ 
+-static int drbg_cavs_test(struct drbg_testvec *test, int pr,
++static int drbg_cavs_test(const struct drbg_testvec *test, int pr,
+ 			  const char *driver, u32 type, u32 mask)
+ {
+ 	int ret = -EAGAIN;
+@@ -1715,7 +2127,7 @@ static int drbg_cavs_test(struct drbg_te
+ 	if (!buf)
+ 		return -ENOMEM;
+ 
+-	drng = crypto_alloc_rng(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	drng = crypto_alloc_rng(driver, type, mask);
+ 	if (IS_ERR(drng)) {
+ 		printk(KERN_ERR "alg: drbg: could not allocate DRNG handle for "
+ 		       "%s\n", driver);
+@@ -1777,7 +2189,7 @@ static int alg_test_drbg(const struct al
+ 	int err = 0;
+ 	int pr = 0;
+ 	int i = 0;
+-	struct drbg_testvec *template = desc->suite.drbg.vecs;
++	const struct drbg_testvec *template = desc->suite.drbg.vecs;
+ 	unsigned int tcount = desc->suite.drbg.count;
+ 
+ 	if (0 == memcmp(driver, "drbg_pr_", 8))
+@@ -1796,7 +2208,7 @@ static int alg_test_drbg(const struct al
+ 
+ }
+ 
+-static int do_test_kpp(struct crypto_kpp *tfm, struct kpp_testvec *vec,
++static int do_test_kpp(struct crypto_kpp *tfm, const struct kpp_testvec *vec,
+ 		       const char *alg)
+ {
+ 	struct kpp_request *req;
+@@ -1888,7 +2300,7 @@ free_req:
+ }
+ 
+ static int test_kpp(struct crypto_kpp *tfm, const char *alg,
+-		    struct kpp_testvec *vecs, unsigned int tcount)
++		    const struct kpp_testvec *vecs, unsigned int tcount)
+ {
+ 	int ret, i;
+ 
+@@ -1909,7 +2321,7 @@ static int alg_test_kpp(const struct alg
+ 	struct crypto_kpp *tfm;
+ 	int err = 0;
+ 
+-	tfm = crypto_alloc_kpp(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	tfm = crypto_alloc_kpp(driver, type, mask);
+ 	if (IS_ERR(tfm)) {
+ 		pr_err("alg: kpp: Failed to load tfm for %s: %ld\n",
+ 		       driver, PTR_ERR(tfm));
+@@ -1924,7 +2336,7 @@ static int alg_test_kpp(const struct alg
+ }
+ 
+ static int test_akcipher_one(struct crypto_akcipher *tfm,
+-			     struct akcipher_testvec *vecs)
++			     const struct akcipher_testvec *vecs)
+ {
+ 	char *xbuf[XBUFSIZE];
+ 	struct akcipher_request *req;
+@@ -2044,7 +2456,8 @@ free_xbuf:
+ }
+ 
+ static int test_akcipher(struct crypto_akcipher *tfm, const char *alg,
+-			 struct akcipher_testvec *vecs, unsigned int tcount)
++			 const struct akcipher_testvec *vecs,
++			 unsigned int tcount)
+ {
+ 	const char *algo =
+ 		crypto_tfm_alg_driver_name(crypto_akcipher_tfm(tfm));
+@@ -2068,7 +2481,7 @@ static int alg_test_akcipher(const struc
+ 	struct crypto_akcipher *tfm;
+ 	int err = 0;
+ 
+-	tfm = crypto_alloc_akcipher(driver, type | CRYPTO_ALG_INTERNAL, mask);
++	tfm = crypto_alloc_akcipher(driver, type, mask);
+ 	if (IS_ERR(tfm)) {
+ 		pr_err("alg: akcipher: Failed to load tfm for %s: %ld\n",
+ 		       driver, PTR_ERR(tfm));
+@@ -2088,112 +2501,23 @@ static int alg_test_null(const struct al
+ 	return 0;
+ }
+ 
++#define __VECS(tv)	{ .vecs = tv, .count = ARRAY_SIZE(tv) }
++
+ /* Please keep this list sorted by algorithm name. */
+ static const struct alg_test_desc alg_test_descs[] = {
+ 	{
+-		.alg = "__cbc-cast5-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__cbc-cast6-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__cbc-serpent-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__cbc-serpent-avx2",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__cbc-serpent-sse2",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__cbc-twofish-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-cbc-aes-aesni",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+-		.alg = "__driver-cbc-camellia-aesni",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-cbc-camellia-aesni-avx2",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-cbc-cast5-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-cbc-cast6-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-cbc-serpent-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-cbc-serpent-avx2",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-cbc-serpent-sse2",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-cbc-twofish-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-ecb-aes-aesni",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+-		.alg = "__driver-ecb-camellia-aesni",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-ecb-camellia-aesni-avx2",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-ecb-cast5-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-ecb-cast6-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-ecb-serpent-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-ecb-serpent-avx2",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-ecb-serpent-sse2",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-ecb-twofish-avx",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "__driver-gcm-aes-aesni",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+-		.alg = "__ghash-pclmulqdqni",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+ 		.alg = "ansi_cprng",
+ 		.test = alg_test_cprng,
+ 		.suite = {
+-			.cprng = {
+-				.vecs = ansi_cprng_aes_tv_template,
+-				.count = ANSI_CPRNG_AES_TEST_VECTORS
+-			}
++			.cprng = __VECS(ansi_cprng_aes_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "authenc(hmac(md5),ecb(cipher_null))",
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs = hmac_md5_ecb_cipher_null_enc_tv_template,
+-					.count = HMAC_MD5_ECB_CIPHER_NULL_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = hmac_md5_ecb_cipher_null_dec_tv_template,
+-					.count = HMAC_MD5_ECB_CIPHER_NULL_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(hmac_md5_ecb_cipher_null_enc_tv_template),
++				.dec = __VECS(hmac_md5_ecb_cipher_null_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2201,12 +2525,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha1_aes_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA1_AES_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha1_aes_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2214,12 +2533,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha1_des_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA1_DES_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha1_des_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2228,12 +2542,7 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha1_des3_ede_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA1_DES3_EDE_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha1_des3_ede_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2245,18 +2554,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha1_ecb_cipher_null_enc_tv_temp,
+-					.count =
+-					HMAC_SHA1_ECB_CIPHER_NULL_ENC_TEST_VEC
+-				},
+-				.dec = {
+-					.vecs =
+-					hmac_sha1_ecb_cipher_null_dec_tv_temp,
+-					.count =
+-					HMAC_SHA1_ECB_CIPHER_NULL_DEC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha1_ecb_cipher_null_enc_tv_temp),
++				.dec = __VECS(hmac_sha1_ecb_cipher_null_dec_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2268,12 +2567,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha224_des_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA224_DES_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha224_des_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2282,12 +2576,7 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha224_des3_ede_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA224_DES3_EDE_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha224_des3_ede_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2296,12 +2585,7 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha256_aes_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA256_AES_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha256_aes_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2309,12 +2593,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha256_des_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA256_DES_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha256_des_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2323,12 +2602,7 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha256_des3_ede_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA256_DES3_EDE_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha256_des3_ede_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2344,12 +2618,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha384_des_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA384_DES_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha384_des_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2358,12 +2627,7 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha384_des3_ede_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA384_DES3_EDE_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha384_des3_ede_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2380,12 +2644,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha512_aes_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA512_AES_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha512_aes_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2393,12 +2652,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha512_des_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA512_DES_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha512_des_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2407,12 +2661,7 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs =
+-					hmac_sha512_des3_ede_cbc_enc_tv_temp,
+-					.count =
+-					HMAC_SHA512_DES3_EDE_CBC_ENC_TEST_VEC
+-				}
++				.enc = __VECS(hmac_sha512_des3_ede_cbc_enc_tv_temp)
+ 			}
+ 		}
+ 	}, {
+@@ -2429,14 +2678,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = aes_cbc_enc_tv_template,
+-					.count = AES_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_cbc_dec_tv_template,
+-					.count = AES_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_cbc_enc_tv_template),
++				.dec = __VECS(aes_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2444,14 +2687,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = anubis_cbc_enc_tv_template,
+-					.count = ANUBIS_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = anubis_cbc_dec_tv_template,
+-					.count = ANUBIS_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(anubis_cbc_enc_tv_template),
++				.dec = __VECS(anubis_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2459,14 +2696,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = bf_cbc_enc_tv_template,
+-					.count = BF_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = bf_cbc_dec_tv_template,
+-					.count = BF_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(bf_cbc_enc_tv_template),
++				.dec = __VECS(bf_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2474,14 +2705,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = camellia_cbc_enc_tv_template,
+-					.count = CAMELLIA_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = camellia_cbc_dec_tv_template,
+-					.count = CAMELLIA_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(camellia_cbc_enc_tv_template),
++				.dec = __VECS(camellia_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2489,14 +2714,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cast5_cbc_enc_tv_template,
+-					.count = CAST5_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cast5_cbc_dec_tv_template,
+-					.count = CAST5_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cast5_cbc_enc_tv_template),
++				.dec = __VECS(cast5_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2504,14 +2723,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cast6_cbc_enc_tv_template,
+-					.count = CAST6_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cast6_cbc_dec_tv_template,
+-					.count = CAST6_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cast6_cbc_enc_tv_template),
++				.dec = __VECS(cast6_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2519,14 +2732,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = des_cbc_enc_tv_template,
+-					.count = DES_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = des_cbc_dec_tv_template,
+-					.count = DES_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(des_cbc_enc_tv_template),
++				.dec = __VECS(des_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2535,14 +2742,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = des3_ede_cbc_enc_tv_template,
+-					.count = DES3_EDE_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = des3_ede_cbc_dec_tv_template,
+-					.count = DES3_EDE_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(des3_ede_cbc_enc_tv_template),
++				.dec = __VECS(des3_ede_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2550,14 +2751,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = serpent_cbc_enc_tv_template,
+-					.count = SERPENT_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = serpent_cbc_dec_tv_template,
+-					.count = SERPENT_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(serpent_cbc_enc_tv_template),
++				.dec = __VECS(serpent_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2565,30 +2760,25 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = tf_cbc_enc_tv_template,
+-					.count = TF_CBC_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = tf_cbc_dec_tv_template,
+-					.count = TF_CBC_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(tf_cbc_enc_tv_template),
++				.dec = __VECS(tf_cbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
++		.alg = "cbcmac(aes)",
++		.fips_allowed = 1,
++		.test = alg_test_hash,
++		.suite = {
++			.hash = __VECS(aes_cbcmac_tv_template)
++		}
++	}, {
+ 		.alg = "ccm(aes)",
+ 		.test = alg_test_aead,
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs = aes_ccm_enc_tv_template,
+-					.count = AES_CCM_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_ccm_dec_tv_template,
+-					.count = AES_CCM_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_ccm_enc_tv_template),
++				.dec = __VECS(aes_ccm_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2596,14 +2786,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = chacha20_enc_tv_template,
+-					.count = CHACHA20_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = chacha20_enc_tv_template,
+-					.count = CHACHA20_ENC_TEST_VECTORS
+-				},
++				.enc = __VECS(chacha20_enc_tv_template),
++				.dec = __VECS(chacha20_enc_tv_template),
+ 			}
+ 		}
+ 	}, {
+@@ -2611,20 +2795,14 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = aes_cmac128_tv_template,
+-				.count = CMAC_AES_TEST_VECTORS
+-			}
++			.hash = __VECS(aes_cmac128_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "cmac(des3_ede)",
+ 		.fips_allowed = 1,
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = des3_ede_cmac64_tv_template,
+-				.count = CMAC_DES3_EDE_TEST_VECTORS
+-			}
++			.hash = __VECS(des3_ede_cmac64_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "compress_null",
+@@ -2633,94 +2811,30 @@ static const struct alg_test_desc alg_te
+ 		.alg = "crc32",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = crc32_tv_template,
+-				.count = CRC32_TEST_VECTORS
+-			}
++			.hash = __VECS(crc32_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "crc32c",
+ 		.test = alg_test_crc32c,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = crc32c_tv_template,
+-				.count = CRC32C_TEST_VECTORS
+-			}
++			.hash = __VECS(crc32c_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "crct10dif",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = crct10dif_tv_template,
+-				.count = CRCT10DIF_TEST_VECTORS
+-			}
++			.hash = __VECS(crct10dif_tv_template)
+ 		}
+ 	}, {
+-		.alg = "cryptd(__driver-cbc-aes-aesni)",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+-		.alg = "cryptd(__driver-cbc-camellia-aesni)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-cbc-camellia-aesni-avx2)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-cbc-serpent-avx2)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-aes-aesni)",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-camellia-aesni)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-camellia-aesni-avx2)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-cast5-avx)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-cast6-avx)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-serpent-avx)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-serpent-avx2)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-serpent-sse2)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-ecb-twofish-avx)",
+-		.test = alg_test_null,
+-	}, {
+-		.alg = "cryptd(__driver-gcm-aes-aesni)",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+-		.alg = "cryptd(__ghash-pclmulqdqni)",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+ 		.alg = "ctr(aes)",
+ 		.test = alg_test_skcipher,
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = aes_ctr_enc_tv_template,
+-					.count = AES_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_ctr_dec_tv_template,
+-					.count = AES_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_ctr_enc_tv_template),
++				.dec = __VECS(aes_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2728,14 +2842,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = bf_ctr_enc_tv_template,
+-					.count = BF_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = bf_ctr_dec_tv_template,
+-					.count = BF_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(bf_ctr_enc_tv_template),
++				.dec = __VECS(bf_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2743,14 +2851,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = camellia_ctr_enc_tv_template,
+-					.count = CAMELLIA_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = camellia_ctr_dec_tv_template,
+-					.count = CAMELLIA_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(camellia_ctr_enc_tv_template),
++				.dec = __VECS(camellia_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2758,14 +2860,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cast5_ctr_enc_tv_template,
+-					.count = CAST5_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cast5_ctr_dec_tv_template,
+-					.count = CAST5_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cast5_ctr_enc_tv_template),
++				.dec = __VECS(cast5_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2773,14 +2869,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cast6_ctr_enc_tv_template,
+-					.count = CAST6_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cast6_ctr_dec_tv_template,
+-					.count = CAST6_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cast6_ctr_enc_tv_template),
++				.dec = __VECS(cast6_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2788,29 +2878,18 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = des_ctr_enc_tv_template,
+-					.count = DES_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = des_ctr_dec_tv_template,
+-					.count = DES_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(des_ctr_enc_tv_template),
++				.dec = __VECS(des_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+ 		.alg = "ctr(des3_ede)",
+ 		.test = alg_test_skcipher,
++		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = des3_ede_ctr_enc_tv_template,
+-					.count = DES3_EDE_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = des3_ede_ctr_dec_tv_template,
+-					.count = DES3_EDE_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(des3_ede_ctr_enc_tv_template),
++				.dec = __VECS(des3_ede_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2818,14 +2897,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = serpent_ctr_enc_tv_template,
+-					.count = SERPENT_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = serpent_ctr_dec_tv_template,
+-					.count = SERPENT_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(serpent_ctr_enc_tv_template),
++				.dec = __VECS(serpent_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2833,14 +2906,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = tf_ctr_enc_tv_template,
+-					.count = TF_CTR_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = tf_ctr_dec_tv_template,
+-					.count = TF_CTR_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(tf_ctr_enc_tv_template),
++				.dec = __VECS(tf_ctr_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2848,14 +2915,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cts_mode_enc_tv_template,
+-					.count = CTS_MODE_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cts_mode_dec_tv_template,
+-					.count = CTS_MODE_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cts_mode_enc_tv_template),
++				.dec = __VECS(cts_mode_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2864,14 +2925,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.comp = {
+-				.comp = {
+-					.vecs = deflate_comp_tv_template,
+-					.count = DEFLATE_COMP_TEST_VECTORS
+-				},
+-				.decomp = {
+-					.vecs = deflate_decomp_tv_template,
+-					.count = DEFLATE_DECOMP_TEST_VECTORS
+-				}
++				.comp = __VECS(deflate_comp_tv_template),
++				.decomp = __VECS(deflate_decomp_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -2879,10 +2934,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_kpp,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.kpp = {
+-				.vecs = dh_tv_template,
+-				.count = DH_TEST_VECTORS
+-			}
++			.kpp = __VECS(dh_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "digest_null",
+@@ -2892,30 +2944,21 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_drbg,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.drbg = {
+-				.vecs = drbg_nopr_ctr_aes128_tv_template,
+-				.count = ARRAY_SIZE(drbg_nopr_ctr_aes128_tv_template)
+-			}
++			.drbg = __VECS(drbg_nopr_ctr_aes128_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "drbg_nopr_ctr_aes192",
+ 		.test = alg_test_drbg,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.drbg = {
+-				.vecs = drbg_nopr_ctr_aes192_tv_template,
+-				.count = ARRAY_SIZE(drbg_nopr_ctr_aes192_tv_template)
+-			}
++			.drbg = __VECS(drbg_nopr_ctr_aes192_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "drbg_nopr_ctr_aes256",
+ 		.test = alg_test_drbg,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.drbg = {
+-				.vecs = drbg_nopr_ctr_aes256_tv_template,
+-				.count = ARRAY_SIZE(drbg_nopr_ctr_aes256_tv_template)
+-			}
++			.drbg = __VECS(drbg_nopr_ctr_aes256_tv_template)
+ 		}
+ 	}, {
+ 		/*
+@@ -2930,11 +2973,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_drbg,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.drbg = {
+-				.vecs = drbg_nopr_hmac_sha256_tv_template,
+-				.count =
+-				ARRAY_SIZE(drbg_nopr_hmac_sha256_tv_template)
+-			}
++			.drbg = __VECS(drbg_nopr_hmac_sha256_tv_template)
+ 		}
+ 	}, {
+ 		/* covered by drbg_nopr_hmac_sha256 test */
+@@ -2954,10 +2993,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_drbg,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.drbg = {
+-				.vecs = drbg_nopr_sha256_tv_template,
+-				.count = ARRAY_SIZE(drbg_nopr_sha256_tv_template)
+-			}
++			.drbg = __VECS(drbg_nopr_sha256_tv_template)
+ 		}
+ 	}, {
+ 		/* covered by drbg_nopr_sha256 test */
+@@ -2973,10 +3009,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_drbg,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.drbg = {
+-				.vecs = drbg_pr_ctr_aes128_tv_template,
+-				.count = ARRAY_SIZE(drbg_pr_ctr_aes128_tv_template)
+-			}
++			.drbg = __VECS(drbg_pr_ctr_aes128_tv_template)
+ 		}
+ 	}, {
+ 		/* covered by drbg_pr_ctr_aes128 test */
+@@ -2996,10 +3029,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_drbg,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.drbg = {
+-				.vecs = drbg_pr_hmac_sha256_tv_template,
+-				.count = ARRAY_SIZE(drbg_pr_hmac_sha256_tv_template)
+-			}
++			.drbg = __VECS(drbg_pr_hmac_sha256_tv_template)
+ 		}
+ 	}, {
+ 		/* covered by drbg_pr_hmac_sha256 test */
+@@ -3019,10 +3049,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_drbg,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.drbg = {
+-				.vecs = drbg_pr_sha256_tv_template,
+-				.count = ARRAY_SIZE(drbg_pr_sha256_tv_template)
+-			}
++			.drbg = __VECS(drbg_pr_sha256_tv_template)
+ 		}
+ 	}, {
+ 		/* covered by drbg_pr_sha256 test */
+@@ -3034,23 +3061,13 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.test = alg_test_null,
+ 	}, {
+-		.alg = "ecb(__aes-aesni)",
+-		.test = alg_test_null,
+-		.fips_allowed = 1,
+-	}, {
+ 		.alg = "ecb(aes)",
+ 		.test = alg_test_skcipher,
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = aes_enc_tv_template,
+-					.count = AES_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_dec_tv_template,
+-					.count = AES_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_enc_tv_template),
++				.dec = __VECS(aes_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3058,14 +3075,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = anubis_enc_tv_template,
+-					.count = ANUBIS_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = anubis_dec_tv_template,
+-					.count = ANUBIS_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(anubis_enc_tv_template),
++				.dec = __VECS(anubis_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3073,14 +3084,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = arc4_enc_tv_template,
+-					.count = ARC4_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = arc4_dec_tv_template,
+-					.count = ARC4_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(arc4_enc_tv_template),
++				.dec = __VECS(arc4_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3088,14 +3093,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = bf_enc_tv_template,
+-					.count = BF_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = bf_dec_tv_template,
+-					.count = BF_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(bf_enc_tv_template),
++				.dec = __VECS(bf_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3103,14 +3102,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = camellia_enc_tv_template,
+-					.count = CAMELLIA_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = camellia_dec_tv_template,
+-					.count = CAMELLIA_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(camellia_enc_tv_template),
++				.dec = __VECS(camellia_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3118,14 +3111,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cast5_enc_tv_template,
+-					.count = CAST5_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cast5_dec_tv_template,
+-					.count = CAST5_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cast5_enc_tv_template),
++				.dec = __VECS(cast5_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3133,14 +3120,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cast6_enc_tv_template,
+-					.count = CAST6_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cast6_dec_tv_template,
+-					.count = CAST6_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cast6_enc_tv_template),
++				.dec = __VECS(cast6_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3151,14 +3132,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = des_enc_tv_template,
+-					.count = DES_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = des_dec_tv_template,
+-					.count = DES_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(des_enc_tv_template),
++				.dec = __VECS(des_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3167,14 +3142,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = des3_ede_enc_tv_template,
+-					.count = DES3_EDE_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = des3_ede_dec_tv_template,
+-					.count = DES3_EDE_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(des3_ede_enc_tv_template),
++				.dec = __VECS(des3_ede_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3197,14 +3166,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = khazad_enc_tv_template,
+-					.count = KHAZAD_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = khazad_dec_tv_template,
+-					.count = KHAZAD_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(khazad_enc_tv_template),
++				.dec = __VECS(khazad_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3212,14 +3175,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = seed_enc_tv_template,
+-					.count = SEED_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = seed_dec_tv_template,
+-					.count = SEED_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(seed_enc_tv_template),
++				.dec = __VECS(seed_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3227,14 +3184,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = serpent_enc_tv_template,
+-					.count = SERPENT_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = serpent_dec_tv_template,
+-					.count = SERPENT_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(serpent_enc_tv_template),
++				.dec = __VECS(serpent_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3242,14 +3193,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = tea_enc_tv_template,
+-					.count = TEA_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = tea_dec_tv_template,
+-					.count = TEA_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(tea_enc_tv_template),
++				.dec = __VECS(tea_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3257,14 +3202,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = tnepres_enc_tv_template,
+-					.count = TNEPRES_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = tnepres_dec_tv_template,
+-					.count = TNEPRES_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(tnepres_enc_tv_template),
++				.dec = __VECS(tnepres_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3272,14 +3211,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = tf_enc_tv_template,
+-					.count = TF_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = tf_dec_tv_template,
+-					.count = TF_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(tf_enc_tv_template),
++				.dec = __VECS(tf_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3287,14 +3220,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = xeta_enc_tv_template,
+-					.count = XETA_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = xeta_dec_tv_template,
+-					.count = XETA_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(xeta_enc_tv_template),
++				.dec = __VECS(xeta_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3302,14 +3229,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = xtea_enc_tv_template,
+-					.count = XTEA_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = xtea_dec_tv_template,
+-					.count = XTEA_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(xtea_enc_tv_template),
++				.dec = __VECS(xtea_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3317,10 +3238,7 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_kpp,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.kpp = {
+-				.vecs = ecdh_tv_template,
+-				.count = ECDH_TEST_VECTORS
+-			}
++			.kpp = __VECS(ecdh_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "gcm(aes)",
+@@ -3328,14 +3246,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs = aes_gcm_enc_tv_template,
+-					.count = AES_GCM_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_gcm_dec_tv_template,
+-					.count = AES_GCM_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_gcm_enc_tv_template),
++				.dec = __VECS(aes_gcm_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3343,136 +3255,94 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = ghash_tv_template,
+-				.count = GHASH_TEST_VECTORS
+-			}
++			.hash = __VECS(ghash_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(crc32)",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = bfin_crc_tv_template,
+-				.count = BFIN_CRC_TEST_VECTORS
+-			}
++			.hash = __VECS(bfin_crc_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(md5)",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_md5_tv_template,
+-				.count = HMAC_MD5_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_md5_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(rmd128)",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_rmd128_tv_template,
+-				.count = HMAC_RMD128_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_rmd128_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(rmd160)",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_rmd160_tv_template,
+-				.count = HMAC_RMD160_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_rmd160_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha1)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha1_tv_template,
+-				.count = HMAC_SHA1_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha1_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha224)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha224_tv_template,
+-				.count = HMAC_SHA224_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha224_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha256)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha256_tv_template,
+-				.count = HMAC_SHA256_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha256_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha3-224)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha3_224_tv_template,
+-				.count = HMAC_SHA3_224_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha3_224_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha3-256)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha3_256_tv_template,
+-				.count = HMAC_SHA3_256_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha3_256_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha3-384)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha3_384_tv_template,
+-				.count = HMAC_SHA3_384_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha3_384_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha3-512)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha3_512_tv_template,
+-				.count = HMAC_SHA3_512_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha3_512_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha384)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha384_tv_template,
+-				.count = HMAC_SHA384_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha384_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "hmac(sha512)",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = hmac_sha512_tv_template,
+-				.count = HMAC_SHA512_TEST_VECTORS
+-			}
++			.hash = __VECS(hmac_sha512_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "jitterentropy_rng",
+@@ -3484,14 +3354,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = aes_kw_enc_tv_template,
+-					.count = ARRAY_SIZE(aes_kw_enc_tv_template)
+-				},
+-				.dec = {
+-					.vecs = aes_kw_dec_tv_template,
+-					.count = ARRAY_SIZE(aes_kw_dec_tv_template)
+-				}
++				.enc = __VECS(aes_kw_enc_tv_template),
++				.dec = __VECS(aes_kw_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3499,14 +3363,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = aes_lrw_enc_tv_template,
+-					.count = AES_LRW_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_lrw_dec_tv_template,
+-					.count = AES_LRW_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_lrw_enc_tv_template),
++				.dec = __VECS(aes_lrw_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3514,14 +3372,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = camellia_lrw_enc_tv_template,
+-					.count = CAMELLIA_LRW_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = camellia_lrw_dec_tv_template,
+-					.count = CAMELLIA_LRW_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(camellia_lrw_enc_tv_template),
++				.dec = __VECS(camellia_lrw_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3529,14 +3381,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cast6_lrw_enc_tv_template,
+-					.count = CAST6_LRW_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cast6_lrw_dec_tv_template,
+-					.count = CAST6_LRW_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cast6_lrw_enc_tv_template),
++				.dec = __VECS(cast6_lrw_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3544,14 +3390,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = serpent_lrw_enc_tv_template,
+-					.count = SERPENT_LRW_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = serpent_lrw_dec_tv_template,
+-					.count = SERPENT_LRW_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(serpent_lrw_enc_tv_template),
++				.dec = __VECS(serpent_lrw_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3559,14 +3399,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = tf_lrw_enc_tv_template,
+-					.count = TF_LRW_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = tf_lrw_dec_tv_template,
+-					.count = TF_LRW_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(tf_lrw_enc_tv_template),
++				.dec = __VECS(tf_lrw_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3575,14 +3409,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.comp = {
+-				.comp = {
+-					.vecs = lz4_comp_tv_template,
+-					.count = LZ4_COMP_TEST_VECTORS
+-				},
+-				.decomp = {
+-					.vecs = lz4_decomp_tv_template,
+-					.count = LZ4_DECOMP_TEST_VECTORS
+-				}
++				.comp = __VECS(lz4_comp_tv_template),
++				.decomp = __VECS(lz4_decomp_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3591,14 +3419,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.comp = {
+-				.comp = {
+-					.vecs = lz4hc_comp_tv_template,
+-					.count = LZ4HC_COMP_TEST_VECTORS
+-				},
+-				.decomp = {
+-					.vecs = lz4hc_decomp_tv_template,
+-					.count = LZ4HC_DECOMP_TEST_VECTORS
+-				}
++				.comp = __VECS(lz4hc_comp_tv_template),
++				.decomp = __VECS(lz4hc_decomp_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3607,42 +3429,27 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.comp = {
+-				.comp = {
+-					.vecs = lzo_comp_tv_template,
+-					.count = LZO_COMP_TEST_VECTORS
+-				},
+-				.decomp = {
+-					.vecs = lzo_decomp_tv_template,
+-					.count = LZO_DECOMP_TEST_VECTORS
+-				}
++				.comp = __VECS(lzo_comp_tv_template),
++				.decomp = __VECS(lzo_decomp_tv_template)
+ 			}
+ 		}
+ 	}, {
+ 		.alg = "md4",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = md4_tv_template,
+-				.count = MD4_TEST_VECTORS
+-			}
++			.hash = __VECS(md4_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "md5",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = md5_tv_template,
+-				.count = MD5_TEST_VECTORS
+-			}
++			.hash = __VECS(md5_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "michael_mic",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = michael_mic_tv_template,
+-				.count = MICHAEL_MIC_TEST_VECTORS
+-			}
++			.hash = __VECS(michael_mic_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "ofb(aes)",
+@@ -3650,14 +3457,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = aes_ofb_enc_tv_template,
+-					.count = AES_OFB_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_ofb_dec_tv_template,
+-					.count = AES_OFB_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_ofb_enc_tv_template),
++				.dec = __VECS(aes_ofb_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3665,24 +3466,15 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = fcrypt_pcbc_enc_tv_template,
+-					.count = FCRYPT_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = fcrypt_pcbc_dec_tv_template,
+-					.count = FCRYPT_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(fcrypt_pcbc_enc_tv_template),
++				.dec = __VECS(fcrypt_pcbc_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+ 		.alg = "poly1305",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = poly1305_tv_template,
+-				.count = POLY1305_TEST_VECTORS
+-			}
++			.hash = __VECS(poly1305_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "rfc3686(ctr(aes))",
+@@ -3690,14 +3482,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = aes_ctr_rfc3686_enc_tv_template,
+-					.count = AES_CTR_3686_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_ctr_rfc3686_dec_tv_template,
+-					.count = AES_CTR_3686_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_ctr_rfc3686_enc_tv_template),
++				.dec = __VECS(aes_ctr_rfc3686_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3706,14 +3492,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs = aes_gcm_rfc4106_enc_tv_template,
+-					.count = AES_GCM_4106_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_gcm_rfc4106_dec_tv_template,
+-					.count = AES_GCM_4106_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_gcm_rfc4106_enc_tv_template),
++				.dec = __VECS(aes_gcm_rfc4106_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3722,14 +3502,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs = aes_ccm_rfc4309_enc_tv_template,
+-					.count = AES_CCM_4309_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_ccm_rfc4309_dec_tv_template,
+-					.count = AES_CCM_4309_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_ccm_rfc4309_enc_tv_template),
++				.dec = __VECS(aes_ccm_rfc4309_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3737,14 +3511,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs = aes_gcm_rfc4543_enc_tv_template,
+-					.count = AES_GCM_4543_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_gcm_rfc4543_dec_tv_template,
+-					.count = AES_GCM_4543_DEC_TEST_VECTORS
+-				},
++				.enc = __VECS(aes_gcm_rfc4543_enc_tv_template),
++				.dec = __VECS(aes_gcm_rfc4543_dec_tv_template),
+ 			}
+ 		}
+ 	}, {
+@@ -3752,14 +3520,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs = rfc7539_enc_tv_template,
+-					.count = RFC7539_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = rfc7539_dec_tv_template,
+-					.count = RFC7539_DEC_TEST_VECTORS
+-				},
++				.enc = __VECS(rfc7539_enc_tv_template),
++				.dec = __VECS(rfc7539_dec_tv_template),
+ 			}
+ 		}
+ 	}, {
+@@ -3767,71 +3529,47 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_aead,
+ 		.suite = {
+ 			.aead = {
+-				.enc = {
+-					.vecs = rfc7539esp_enc_tv_template,
+-					.count = RFC7539ESP_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = rfc7539esp_dec_tv_template,
+-					.count = RFC7539ESP_DEC_TEST_VECTORS
+-				},
++				.enc = __VECS(rfc7539esp_enc_tv_template),
++				.dec = __VECS(rfc7539esp_dec_tv_template),
+ 			}
+ 		}
+ 	}, {
+ 		.alg = "rmd128",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = rmd128_tv_template,
+-				.count = RMD128_TEST_VECTORS
+-			}
++			.hash = __VECS(rmd128_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "rmd160",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = rmd160_tv_template,
+-				.count = RMD160_TEST_VECTORS
+-			}
++			.hash = __VECS(rmd160_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "rmd256",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = rmd256_tv_template,
+-				.count = RMD256_TEST_VECTORS
+-			}
++			.hash = __VECS(rmd256_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "rmd320",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = rmd320_tv_template,
+-				.count = RMD320_TEST_VECTORS
+-			}
++			.hash = __VECS(rmd320_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "rsa",
+ 		.test = alg_test_akcipher,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.akcipher = {
+-				.vecs = rsa_tv_template,
+-				.count = RSA_TEST_VECTORS
+-			}
++			.akcipher = __VECS(rsa_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "salsa20",
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = salsa20_stream_enc_tv_template,
+-					.count = SALSA20_STREAM_ENC_TEST_VECTORS
+-				}
++				.enc = __VECS(salsa20_stream_enc_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -3839,162 +3577,120 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha1_tv_template,
+-				.count = SHA1_TEST_VECTORS
+-			}
++			.hash = __VECS(sha1_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "sha224",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha224_tv_template,
+-				.count = SHA224_TEST_VECTORS
+-			}
++			.hash = __VECS(sha224_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "sha256",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha256_tv_template,
+-				.count = SHA256_TEST_VECTORS
+-			}
++			.hash = __VECS(sha256_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "sha3-224",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha3_224_tv_template,
+-				.count = SHA3_224_TEST_VECTORS
+-			}
++			.hash = __VECS(sha3_224_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "sha3-256",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha3_256_tv_template,
+-				.count = SHA3_256_TEST_VECTORS
+-			}
++			.hash = __VECS(sha3_256_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "sha3-384",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha3_384_tv_template,
+-				.count = SHA3_384_TEST_VECTORS
+-			}
++			.hash = __VECS(sha3_384_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "sha3-512",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha3_512_tv_template,
+-				.count = SHA3_512_TEST_VECTORS
+-			}
++			.hash = __VECS(sha3_512_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "sha384",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha384_tv_template,
+-				.count = SHA384_TEST_VECTORS
+-			}
++			.hash = __VECS(sha384_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "sha512",
+ 		.test = alg_test_hash,
+ 		.fips_allowed = 1,
+ 		.suite = {
+-			.hash = {
+-				.vecs = sha512_tv_template,
+-				.count = SHA512_TEST_VECTORS
+-			}
++			.hash = __VECS(sha512_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "tgr128",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = tgr128_tv_template,
+-				.count = TGR128_TEST_VECTORS
+-			}
++			.hash = __VECS(tgr128_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "tgr160",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = tgr160_tv_template,
+-				.count = TGR160_TEST_VECTORS
+-			}
++			.hash = __VECS(tgr160_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "tgr192",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = tgr192_tv_template,
+-				.count = TGR192_TEST_VECTORS
++			.hash = __VECS(tgr192_tv_template)
++		}
++	}, {
++		.alg = "tls10(hmac(sha1),cbc(aes))",
++		.test = alg_test_tls,
++		.suite = {
++			.tls = {
++				.enc = __VECS(tls_enc_tv_template),
++				.dec = __VECS(tls_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+ 		.alg = "vmac(aes)",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = aes_vmac128_tv_template,
+-				.count = VMAC_AES_TEST_VECTORS
+-			}
++			.hash = __VECS(aes_vmac128_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "wp256",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = wp256_tv_template,
+-				.count = WP256_TEST_VECTORS
+-			}
++			.hash = __VECS(wp256_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "wp384",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = wp384_tv_template,
+-				.count = WP384_TEST_VECTORS
+-			}
++			.hash = __VECS(wp384_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "wp512",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = wp512_tv_template,
+-				.count = WP512_TEST_VECTORS
+-			}
++			.hash = __VECS(wp512_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "xcbc(aes)",
+ 		.test = alg_test_hash,
+ 		.suite = {
+-			.hash = {
+-				.vecs = aes_xcbc128_tv_template,
+-				.count = XCBC_AES_TEST_VECTORS
+-			}
++			.hash = __VECS(aes_xcbc128_tv_template)
+ 		}
+ 	}, {
+ 		.alg = "xts(aes)",
+@@ -4002,14 +3698,8 @@ static const struct alg_test_desc alg_te
+ 		.fips_allowed = 1,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = aes_xts_enc_tv_template,
+-					.count = AES_XTS_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = aes_xts_dec_tv_template,
+-					.count = AES_XTS_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(aes_xts_enc_tv_template),
++				.dec = __VECS(aes_xts_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -4017,14 +3707,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = camellia_xts_enc_tv_template,
+-					.count = CAMELLIA_XTS_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = camellia_xts_dec_tv_template,
+-					.count = CAMELLIA_XTS_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(camellia_xts_enc_tv_template),
++				.dec = __VECS(camellia_xts_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -4032,14 +3716,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = cast6_xts_enc_tv_template,
+-					.count = CAST6_XTS_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = cast6_xts_dec_tv_template,
+-					.count = CAST6_XTS_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(cast6_xts_enc_tv_template),
++				.dec = __VECS(cast6_xts_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -4047,14 +3725,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = serpent_xts_enc_tv_template,
+-					.count = SERPENT_XTS_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = serpent_xts_dec_tv_template,
+-					.count = SERPENT_XTS_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(serpent_xts_enc_tv_template),
++				.dec = __VECS(serpent_xts_dec_tv_template)
+ 			}
+ 		}
+ 	}, {
+@@ -4062,14 +3734,8 @@ static const struct alg_test_desc alg_te
+ 		.test = alg_test_skcipher,
+ 		.suite = {
+ 			.cipher = {
+-				.enc = {
+-					.vecs = tf_xts_enc_tv_template,
+-					.count = TF_XTS_ENC_TEST_VECTORS
+-				},
+-				.dec = {
+-					.vecs = tf_xts_dec_tv_template,
+-					.count = TF_XTS_DEC_TEST_VECTORS
+-				}
++				.enc = __VECS(tf_xts_enc_tv_template),
++				.dec = __VECS(tf_xts_dec_tv_template)
+ 			}
+ 		}
+ 	}
+--- a/crypto/testmgr.h
++++ b/crypto/testmgr.h
+@@ -34,9 +34,9 @@
+ 
+ struct hash_testvec {
+ 	/* only used with keyed hash algorithms */
+-	char *key;
+-	char *plaintext;
+-	char *digest;
++	const char *key;
++	const char *plaintext;
++	const char *digest;
+ 	unsigned char tap[MAX_TAP];
+ 	unsigned short psize;
+ 	unsigned char np;
+@@ -63,11 +63,11 @@ struct hash_testvec {
+  */
+ 
+ struct cipher_testvec {
+-	char *key;
+-	char *iv;
+-	char *iv_out;
+-	char *input;
+-	char *result;
++	const char *key;
++	const char *iv;
++	const char *iv_out;
++	const char *input;
++	const char *result;
+ 	unsigned short tap[MAX_TAP];
+ 	int np;
+ 	unsigned char also_non_np;
+@@ -80,11 +80,11 @@ struct cipher_testvec {
+ };
+ 
+ struct aead_testvec {
+-	char *key;
+-	char *iv;
+-	char *input;
+-	char *assoc;
+-	char *result;
++	const char *key;
++	const char *iv;
++	const char *input;
++	const char *assoc;
++	const char *result;
+ 	unsigned char tap[MAX_TAP];
+ 	unsigned char atap[MAX_TAP];
+ 	int np;
+@@ -99,10 +99,10 @@ struct aead_testvec {
+ };
+ 
+ struct cprng_testvec {
+-	char *key;
+-	char *dt;
+-	char *v;
+-	char *result;
++	const char *key;
++	const char *dt;
++	const char *v;
++	const char *result;
+ 	unsigned char klen;
+ 	unsigned short dtlen;
+ 	unsigned short vlen;
+@@ -111,24 +111,38 @@ struct cprng_testvec {
+ };
+ 
+ struct drbg_testvec {
+-	unsigned char *entropy;
++	const unsigned char *entropy;
+ 	size_t entropylen;
+-	unsigned char *entpra;
+-	unsigned char *entprb;
++	const unsigned char *entpra;
++	const unsigned char *entprb;
+ 	size_t entprlen;
+-	unsigned char *addtla;
+-	unsigned char *addtlb;
++	const unsigned char *addtla;
++	const unsigned char *addtlb;
+ 	size_t addtllen;
+-	unsigned char *pers;
++	const unsigned char *pers;
+ 	size_t perslen;
+-	unsigned char *expected;
++	const unsigned char *expected;
+ 	size_t expectedlen;
+ };
+ 
++struct tls_testvec {
++	char *key;	/* wrapped keys for encryption and authentication */
++	char *iv;	/* initialization vector */
++	char *input;	/* input data */
++	char *assoc;	/* associated data: seq num, type, version, input len */
++	char *result;	/* result data */
++	unsigned char fail;	/* the test failure is expected */
++	unsigned char novrfy;	/* dec verification failure expected */
++	unsigned char klen;	/* key length */
++	unsigned short ilen;	/* input data length */
++	unsigned short alen;	/* associated data length */
++	unsigned short rlen;	/* result length */
++};
++
+ struct akcipher_testvec {
+-	unsigned char *key;
+-	unsigned char *m;
+-	unsigned char *c;
++	const unsigned char *key;
++	const unsigned char *m;
++	const unsigned char *c;
+ 	unsigned int key_len;
+ 	unsigned int m_size;
+ 	unsigned int c_size;
+@@ -136,27 +150,227 @@ struct akcipher_testvec {
+ };
+ 
+ struct kpp_testvec {
+-	unsigned char *secret;
+-	unsigned char *b_public;
+-	unsigned char *expected_a_public;
+-	unsigned char *expected_ss;
++	const unsigned char *secret;
++	const unsigned char *b_public;
++	const unsigned char *expected_a_public;
++	const unsigned char *expected_ss;
+ 	unsigned short secret_size;
+ 	unsigned short b_public_size;
+ 	unsigned short expected_a_public_size;
+ 	unsigned short expected_ss_size;
+ };
+ 
+-static char zeroed_string[48];
++static const char zeroed_string[48];
+ 
+ /*
+- * RSA test vectors. Borrowed from openSSL.
++ * TLS1.0 synthetic test vectors
+  */
+-#ifdef CONFIG_CRYPTO_FIPS
+-#define RSA_TEST_VECTORS	2
++static struct tls_testvec tls_enc_tv_template[] = {
++	{
++#ifdef __LITTLE_ENDIAN
++		.key	= "\x08\x00"		/* rta length */
++			"\x01\x00"		/* rta type */
++#else
++		.key	= "\x00\x08"		/* rta length */
++			"\x00\x01"		/* rta type */
++#endif
++			"\x00\x00\x00\x10"	/* enc key length */
++			"authenticationkey20benckeyis16_bytes",
++		.klen	= 8 + 20 + 16,
++		.iv	= "iv0123456789abcd",
++		.input	= "Single block msg",
++		.ilen	= 16,
++		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
++			"\x00\x03\x01\x00\x10",
++		.alen	= 13,
++		.result	= "\xd5\xac\xb\xd2\xac\xad\x3f\xb1"
++			"\x59\x79\x1e\x91\x5f\x52\x14\x9c"
++			"\xc0\x75\xd8\x4c\x97\x0f\x07\x73"
++			"\xdc\x89\x47\x49\x49\xcb\x30\x6b"
++			"\x1b\x45\x23\xa1\xd0\x51\xcf\x02"
++			"\x2e\xa8\x5d\xa0\xfe\xca\x82\x61",
++		.rlen	= 16 + 20 + 12,
++	}, {
++#ifdef __LITTLE_ENDIAN
++		.key	= "\x08\x00"		/* rta length */
++			"\x01\x00"		/* rta type */
++#else
++		.key	= "\x00\x08"		/* rta length */
++			"\x00\x01"		/* rta type */
++#endif
++			"\x00\x00\x00\x10"	/* enc key length */
++			"authenticationkey20benckeyis16_bytes",
++		.klen	= 8 + 20 + 16,
++		.iv	= "iv0123456789abcd",
++		.input	= "",
++		.ilen	= 0,
++		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
++			"\x00\x03\x01\x00\x00",
++		.alen	= 13,
++		.result = "\x58\x2a\x11\xc\x86\x8e\x4b\x67"
++			"\x2d\x16\x26\x1a\xac\x4b\xe2\x1a"
++			"\xe9\x6a\xcc\x4d\x6f\x79\x8a\x45"
++			"\x1f\x4e\x27\xf2\xa7\x59\xb4\x5a",
++		.rlen	= 20 + 12,
++	}, {
++#ifdef __LITTLE_ENDIAN
++		.key	= "\x08\x00"		/* rta length */
++			"\x01\x00"		/* rta type */
++#else
++		.key	= "\x00\x08"		/* rta length */
++			"\x00\x01"		/* rta type */
++#endif
++			"\x00\x00\x00\x10"	/* enc key length */
++			"authenticationkey20benckeyis16_bytes",
++		.klen	= 8 + 20 + 16,
++		.iv	= "iv0123456789abcd",
++		.input	= "285 bytes plaintext285 bytes plaintext285 bytes"
++			" plaintext285 bytes plaintext285 bytes plaintext285"
++			" bytes plaintext285 bytes plaintext285 bytes"
++			" plaintext285 bytes plaintext285 bytes plaintext285"
++			" bytes plaintext285 bytes plaintext285 bytes"
++			" plaintext285 bytes plaintext285 bytes plaintext285"
++			" bytes plaintext285 bytes plaintext",
++		.ilen	= 285,
++		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
++			"\x00\x03\x01\x01\x1d",
++		.alen	= 13,
++		.result = "\x80\x23\x82\x44\x14\x2a\x1d\x94\xc\xc2\x1d\xd"
++			"\x3a\x32\x89\x4c\x57\x30\xa8\x89\x76\x46\xcc\x90"
++			"\x1d\x88\xb8\xa6\x1a\x58\xe\x2d\xeb\x2c\xc7\x3a"
++			"\x52\x4e\xdb\xb3\x1e\x83\x11\xf5\x3c\xce\x6e\x94"
++			"\xd3\x26\x6a\x9a\xd\xbd\xc7\x98\xb9\xb3\x3a\x51"
++			"\x1e\x4\x84\x8a\x8f\x54\x9a\x51\x69\x9c\xce\x31"
++			"\x8d\x5d\x8b\xee\x5f\x70\xc\xc9\xb8\x50\x54\xf8"
++			"\xb2\x4a\x7a\xcd\xeb\x7a\x82\x81\xc6\x41\xc8\x50"
++			"\x91\x8d\xc8\xed\xcd\x40\x8f\x55\xd1\xec\xc9\xac"
++			"\x15\x18\xf9\x20\xa0\xed\x18\xa1\xe3\x56\xe3\x14"
++			"\xe5\xe8\x66\x63\x20\xed\xe4\x62\x9d\xa3\xa4\x1d"
++			"\x81\x89\x18\xf2\x36\xae\xc8\x8a\x2b\xbc\xc3\xb8"
++			"\x80\xf\x97\x21\x36\x39\x8\x84\x23\x18\x9e\x9c"
++			"\x72\x32\x75\x2d\x2e\xf9\x60\xb\xe8\xcc\xd9\x74"
++			"\x4\x1b\x8e\x99\xc1\x94\xee\xd0\xac\x4e\xfc\x7e"
++			"\xf1\x96\xb3\xe7\x14\xb8\xf2\xc\x25\x97\x82\x6b"
++			"\xbd\x0\x65\xab\x5c\xe3\x16\xfb\x68\xef\xea\x9d"
++			"\xff\x44\x1d\x2a\x44\xf5\xc8\x56\x77\xb7\xbf\x13"
++			"\xc8\x54\xdb\x92\xfe\x16\x4c\xbe\x18\xe9\xb\x8d"
++			"\xb\xd4\x43\x58\x43\xaa\xf4\x3\x80\x97\x62\xd5"
++			"\xdf\x3c\x28\xaa\xee\x48\x4b\x55\x41\x1b\x31\x2"
++			"\xbe\xa0\x1c\xbd\xb7\x22\x2a\xe5\x53\x72\x73\x20"
++			"\x44\x4f\xe6\x1\x2b\x34\x33\x11\x7d\xfb\x10\xc1"
++			"\x66\x7c\xa6\xf4\x48\x36\x5e\x2\xda\x41\x4b\x3e"
++			"\xe7\x80\x17\x17\xce\xf1\x3e\x6a\x8e\x26\xf3\xb7"
++			"\x2b\x85\xd\x31\x8d\xba\x6c\x22\xb4\x28\x55\x7e"
++			"\x2a\x9e\x26\xf1\x3d\x21\xac\x65",
++		.rlen	= 285 + 20 + 15,
++	}
++};
++
++static struct tls_testvec tls_dec_tv_template[] = {
++	{
++#ifdef __LITTLE_ENDIAN
++		.key	= "\x08\x00"		/* rta length */
++			"\x01\x00"		/* rta type */
++#else
++		.key	= "\x00\x08"		/* rta length */
++			"\x00\x01"		/* rta type */
++#endif
++			"\x00\x00\x00\x10"	/* enc key length */
++			"authenticationkey20benckeyis16_bytes",
++		.klen	= 8 + 20 + 16,
++		.iv	= "iv0123456789abcd",
++		.input	= "\xd5\xac\xb\xd2\xac\xad\x3f\xb1"
++			"\x59\x79\x1e\x91\x5f\x52\x14\x9c"
++			"\xc0\x75\xd8\x4c\x97\x0f\x07\x73"
++			"\xdc\x89\x47\x49\x49\xcb\x30\x6b"
++			"\x1b\x45\x23\xa1\xd0\x51\xcf\x02"
++			"\x2e\xa8\x5d\xa0\xfe\xca\x82\x61",
++		.ilen	= 16 + 20 + 12,
++		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
++			"\x00\x03\x01\x00\x30",
++		.alen	= 13,
++		.result	= "Single block msg",
++		.rlen	= 16,
++	}, {
++#ifdef __LITTLE_ENDIAN
++		.key	= "\x08\x00"		/* rta length */
++			"\x01\x00"		/* rta type */
+ #else
+-#define RSA_TEST_VECTORS	5
++		.key	= "\x00\x08"		/* rta length */
++			"\x00\x01"		/* rta type */
+ #endif
+-static struct akcipher_testvec rsa_tv_template[] = {
++			"\x00\x00\x00\x10"	/* enc key length */
++			"authenticationkey20benckeyis16_bytes",
++		.klen	= 8 + 20 + 16,
++		.iv	= "iv0123456789abcd",
++		.input = "\x58\x2a\x11\xc\x86\x8e\x4b\x67"
++			"\x2d\x16\x26\x1a\xac\x4b\xe2\x1a"
++			"\xe9\x6a\xcc\x4d\x6f\x79\x8a\x45"
++			"\x1f\x4e\x27\xf2\xa7\x59\xb4\x5a",
++		.ilen	= 20 + 12,
++		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
++			"\x00\x03\x01\x00\x20",
++		.alen	= 13,
++		.result	= "",
++		.rlen	= 0,
++	}, {
++#ifdef __LITTLE_ENDIAN
++		.key	= "\x08\x00"		/* rta length */
++			"\x01\x00"		/* rta type */
++#else
++		.key	= "\x00\x08"		/* rta length */
++			"\x00\x01"		/* rta type */
++#endif
++			"\x00\x00\x00\x10"	/* enc key length */
++			"authenticationkey20benckeyis16_bytes",
++		.klen	= 8 + 20 + 16,
++		.iv	= "iv0123456789abcd",
++		.input = "\x80\x23\x82\x44\x14\x2a\x1d\x94\xc\xc2\x1d\xd"
++			"\x3a\x32\x89\x4c\x57\x30\xa8\x89\x76\x46\xcc\x90"
++			"\x1d\x88\xb8\xa6\x1a\x58\xe\x2d\xeb\x2c\xc7\x3a"
++			"\x52\x4e\xdb\xb3\x1e\x83\x11\xf5\x3c\xce\x6e\x94"
++			"\xd3\x26\x6a\x9a\xd\xbd\xc7\x98\xb9\xb3\x3a\x51"
++			"\x1e\x4\x84\x8a\x8f\x54\x9a\x51\x69\x9c\xce\x31"
++			"\x8d\x5d\x8b\xee\x5f\x70\xc\xc9\xb8\x50\x54\xf8"
++			"\xb2\x4a\x7a\xcd\xeb\x7a\x82\x81\xc6\x41\xc8\x50"
++			"\x91\x8d\xc8\xed\xcd\x40\x8f\x55\xd1\xec\xc9\xac"
++			"\x15\x18\xf9\x20\xa0\xed\x18\xa1\xe3\x56\xe3\x14"
++			"\xe5\xe8\x66\x63\x20\xed\xe4\x62\x9d\xa3\xa4\x1d"
++			"\x81\x89\x18\xf2\x36\xae\xc8\x8a\x2b\xbc\xc3\xb8"
++			"\x80\xf\x97\x21\x36\x39\x8\x84\x23\x18\x9e\x9c"
++			"\x72\x32\x75\x2d\x2e\xf9\x60\xb\xe8\xcc\xd9\x74"
++			"\x4\x1b\x8e\x99\xc1\x94\xee\xd0\xac\x4e\xfc\x7e"
++			"\xf1\x96\xb3\xe7\x14\xb8\xf2\xc\x25\x97\x82\x6b"
++			"\xbd\x0\x65\xab\x5c\xe3\x16\xfb\x68\xef\xea\x9d"
++			"\xff\x44\x1d\x2a\x44\xf5\xc8\x56\x77\xb7\xbf\x13"
++			"\xc8\x54\xdb\x92\xfe\x16\x4c\xbe\x18\xe9\xb\x8d"
++			"\xb\xd4\x43\x58\x43\xaa\xf4\x3\x80\x97\x62\xd5"
++			"\xdf\x3c\x28\xaa\xee\x48\x4b\x55\x41\x1b\x31\x2"
++			"\xbe\xa0\x1c\xbd\xb7\x22\x2a\xe5\x53\x72\x73\x20"
++			"\x44\x4f\xe6\x1\x2b\x34\x33\x11\x7d\xfb\x10\xc1"
++			"\x66\x7c\xa6\xf4\x48\x36\x5e\x2\xda\x41\x4b\x3e"
++			"\xe7\x80\x17\x17\xce\xf1\x3e\x6a\x8e\x26\xf3\xb7"
++			"\x2b\x85\xd\x31\x8d\xba\x6c\x22\xb4\x28\x55\x7e"
++			"\x2a\x9e\x26\xf1\x3d\x21\xac\x65",
++
++		.ilen	= 285 + 20 + 15,
++		.assoc	= "\x00\x01\x02\x03\x04\x05\x06\x07"
++			"\x00\x03\x01\x01\x40",
++		.alen	= 13,
++		.result	= "285 bytes plaintext285 bytes plaintext285 bytes"
++			" plaintext285 bytes plaintext285 bytes plaintext285"
++			" bytes plaintext285 bytes plaintext285 bytes"
++			" plaintext285 bytes plaintext285 bytes plaintext285"
++			" bytes plaintext285 bytes plaintext285 bytes"
++			" plaintext285 bytes plaintext285 bytes plaintext",
++		.rlen	= 285,
++	}
++};
++
++/*
++ * RSA test vectors. Borrowed from openSSL.
++ */
++static const struct akcipher_testvec rsa_tv_template[] = {
+ 	{
+ #ifndef CONFIG_CRYPTO_FIPS
+ 	.key =
+@@ -340,6 +554,7 @@ static struct akcipher_testvec rsa_tv_te
+ 	.m_size = 8,
+ 	.c_size = 256,
+ 	.public_key_vec = true,
++#ifndef CONFIG_CRYPTO_FIPS
+ 	}, {
+ 	.key =
+ 	"\x30\x82\x09\x29" /* sequence of 2345 bytes */
+@@ -538,12 +753,11 @@ static struct akcipher_testvec rsa_tv_te
+ 	.key_len = 2349,
+ 	.m_size = 8,
+ 	.c_size = 512,
++#endif
+ 	}
+ };
+ 
+-#define DH_TEST_VECTORS 2
+-
+-struct kpp_testvec dh_tv_template[] = {
++static const struct kpp_testvec dh_tv_template[] = {
+ 	{
+ 	.secret =
+ #ifdef __LITTLE_ENDIAN
+@@ -760,12 +974,7 @@ struct kpp_testvec dh_tv_template[] = {
+ 	}
+ };
+ 
+-#ifdef CONFIG_CRYPTO_FIPS
+-#define ECDH_TEST_VECTORS 1
+-#else
+-#define ECDH_TEST_VECTORS 2
+-#endif
+-struct kpp_testvec ecdh_tv_template[] = {
++static const struct kpp_testvec ecdh_tv_template[] = {
+ 	{
+ #ifndef CONFIG_CRYPTO_FIPS
+ 	.secret =
+@@ -856,9 +1065,7 @@ struct kpp_testvec ecdh_tv_template[] =
+ /*
+  * MD4 test vectors from RFC1320
+  */
+-#define MD4_TEST_VECTORS	7
+-
+-static struct hash_testvec md4_tv_template [] = {
++static const struct hash_testvec md4_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.digest	= "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31"
+@@ -899,8 +1106,7 @@ static struct hash_testvec md4_tv_templa
+ 	},
+ };
+ 
+-#define SHA3_224_TEST_VECTORS	3
+-static struct hash_testvec sha3_224_tv_template[] = {
++static const struct hash_testvec sha3_224_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.digest	= "\x6b\x4e\x03\x42\x36\x67\xdb\xb7"
+@@ -925,8 +1131,7 @@ static struct hash_testvec sha3_224_tv_t
+ 	},
+ };
+ 
+-#define SHA3_256_TEST_VECTORS	3
+-static struct hash_testvec sha3_256_tv_template[] = {
++static const struct hash_testvec sha3_256_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.digest	= "\xa7\xff\xc6\xf8\xbf\x1e\xd7\x66"
+@@ -952,8 +1157,7 @@ static struct hash_testvec sha3_256_tv_t
+ };
+ 
+ 
+-#define SHA3_384_TEST_VECTORS	3
+-static struct hash_testvec sha3_384_tv_template[] = {
++static const struct hash_testvec sha3_384_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.digest	= "\x0c\x63\xa7\x5b\x84\x5e\x4f\x7d"
+@@ -985,8 +1189,7 @@ static struct hash_testvec sha3_384_tv_t
+ };
+ 
+ 
+-#define SHA3_512_TEST_VECTORS	3
+-static struct hash_testvec sha3_512_tv_template[] = {
++static const struct hash_testvec sha3_512_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.digest	= "\xa6\x9f\x73\xcc\xa2\x3a\x9a\xc5"
+@@ -1027,9 +1230,7 @@ static struct hash_testvec sha3_512_tv_t
+ /*
+  * MD5 test vectors from RFC1321
+  */
+-#define MD5_TEST_VECTORS	7
+-
+-static struct hash_testvec md5_tv_template[] = {
++static const struct hash_testvec md5_tv_template[] = {
+ 	{
+ 		.digest	= "\xd4\x1d\x8c\xd9\x8f\x00\xb2\x04"
+ 			  "\xe9\x80\x09\x98\xec\xf8\x42\x7e",
+@@ -1073,9 +1274,7 @@ static struct hash_testvec md5_tv_templa
+ /*
+  * RIPEMD-128 test vectors from ISO/IEC 10118-3:2004(E)
+  */
+-#define RMD128_TEST_VECTORS     10
+-
+-static struct hash_testvec rmd128_tv_template[] = {
++static const struct hash_testvec rmd128_tv_template[] = {
+ 	{
+ 		.digest	= "\xcd\xf2\x62\x13\xa1\x50\xdc\x3e"
+ 			  "\xcb\x61\x0f\x18\xf6\xb3\x8b\x46",
+@@ -1137,9 +1336,7 @@ static struct hash_testvec rmd128_tv_tem
+ /*
+  * RIPEMD-160 test vectors from ISO/IEC 10118-3:2004(E)
+  */
+-#define RMD160_TEST_VECTORS     10
+-
+-static struct hash_testvec rmd160_tv_template[] = {
++static const struct hash_testvec rmd160_tv_template[] = {
+ 	{
+ 		.digest	= "\x9c\x11\x85\xa5\xc5\xe9\xfc\x54\x61\x28"
+ 			  "\x08\x97\x7e\xe8\xf5\x48\xb2\x25\x8d\x31",
+@@ -1201,9 +1398,7 @@ static struct hash_testvec rmd160_tv_tem
+ /*
+  * RIPEMD-256 test vectors
+  */
+-#define RMD256_TEST_VECTORS     8
+-
+-static struct hash_testvec rmd256_tv_template[] = {
++static const struct hash_testvec rmd256_tv_template[] = {
+ 	{
+ 		.digest	= "\x02\xba\x4c\x4e\x5f\x8e\xcd\x18"
+ 			  "\x77\xfc\x52\xd6\x4d\x30\xe3\x7a"
+@@ -1269,9 +1464,7 @@ static struct hash_testvec rmd256_tv_tem
+ /*
+  * RIPEMD-320 test vectors
+  */
+-#define RMD320_TEST_VECTORS     8
+-
+-static struct hash_testvec rmd320_tv_template[] = {
++static const struct hash_testvec rmd320_tv_template[] = {
+ 	{
+ 		.digest	= "\x22\xd6\x5d\x56\x61\x53\x6c\xdc\x75\xc1"
+ 			  "\xfd\xf5\xc6\xde\x7b\x41\xb9\xf2\x73\x25"
+@@ -1334,36 +1527,49 @@ static struct hash_testvec rmd320_tv_tem
+ 	}
+ };
+ 
+-#define CRCT10DIF_TEST_VECTORS	3
+-static struct hash_testvec crct10dif_tv_template[] = {
++static const struct hash_testvec crct10dif_tv_template[] = {
+ 	{
+-		.plaintext = "abc",
+-		.psize  = 3,
+-#ifdef __LITTLE_ENDIAN
+-		.digest = "\x3b\x44",
+-#else
+-		.digest = "\x44\x3b",
+-#endif
+-	}, {
+-		.plaintext = "1234567890123456789012345678901234567890"
+-			     "123456789012345678901234567890123456789",
+-		.psize	= 79,
+-#ifdef __LITTLE_ENDIAN
+-		.digest	= "\x70\x4b",
+-#else
+-		.digest	= "\x4b\x70",
+-#endif
+-	}, {
+-		.plaintext =
+-		"abcddddddddddddddddddddddddddddddddddddddddddddddddddddd",
+-		.psize  = 56,
+-#ifdef __LITTLE_ENDIAN
+-		.digest = "\xe3\x9c",
+-#else
+-		.digest = "\x9c\xe3",
+-#endif
+-		.np     = 2,
+-		.tap    = { 28, 28 }
++		.plaintext	= "abc",
++		.psize		= 3,
++		.digest		= (u8 *)(u16 []){ 0x443b },
++	}, {
++		.plaintext 	= "1234567890123456789012345678901234567890"
++				  "123456789012345678901234567890123456789",
++		.psize		= 79,
++		.digest 	= (u8 *)(u16 []){ 0x4b70 },
++		.np		= 2,
++		.tap		= { 63, 16 },
++	}, {
++		.plaintext	= "abcdddddddddddddddddddddddddddddddddddddddd"
++				  "ddddddddddddd",
++		.psize		= 56,
++		.digest		= (u8 *)(u16 []){ 0x9ce3 },
++		.np		= 8,
++		.tap		= { 1, 2, 28, 7, 6, 5, 4, 3 },
++	}, {
++		.plaintext 	= "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "123456789012345678901234567890123456789",
++		.psize		= 319,
++		.digest		= (u8 *)(u16 []){ 0x44c6 },
++	}, {
++		.plaintext 	= "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "1234567890123456789012345678901234567890"
++				  "123456789012345678901234567890123456789",
++		.psize		= 319,
++		.digest		= (u8 *)(u16 []){ 0x44c6 },
++		.np		= 4,
++		.tap		= { 1, 255, 57, 6 },
+ 	}
+ };
+ 
+@@ -1371,9 +1577,7 @@ static struct hash_testvec crct10dif_tv_
+  * SHA1 test vectors  from from FIPS PUB 180-1
+  * Long vector from CAVS 5.0
+  */
+-#define SHA1_TEST_VECTORS	6
+-
+-static struct hash_testvec sha1_tv_template[] = {
++static const struct hash_testvec sha1_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -1563,9 +1767,7 @@ static struct hash_testvec sha1_tv_templ
+ /*
+  * SHA224 test vectors from from FIPS PUB 180-2
+  */
+-#define SHA224_TEST_VECTORS     5
+-
+-static struct hash_testvec sha224_tv_template[] = {
++static const struct hash_testvec sha224_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -1737,9 +1939,7 @@ static struct hash_testvec sha224_tv_tem
+ /*
+  * SHA256 test vectors from from NIST
+  */
+-#define SHA256_TEST_VECTORS	5
+-
+-static struct hash_testvec sha256_tv_template[] = {
++static const struct hash_testvec sha256_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -1910,9 +2110,7 @@ static struct hash_testvec sha256_tv_tem
+ /*
+  * SHA384 test vectors from from NIST and kerneli
+  */
+-#define SHA384_TEST_VECTORS	6
+-
+-static struct hash_testvec sha384_tv_template[] = {
++static const struct hash_testvec sha384_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -2104,9 +2302,7 @@ static struct hash_testvec sha384_tv_tem
+ /*
+  * SHA512 test vectors from from NIST and kerneli
+  */
+-#define SHA512_TEST_VECTORS	6
+-
+-static struct hash_testvec sha512_tv_template[] = {
++static const struct hash_testvec sha512_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -2313,9 +2509,7 @@ static struct hash_testvec sha512_tv_tem
+  * by Vincent Rijmen and Paulo S. L. M. Barreto as part of the NESSIE
+  * submission
+  */
+-#define WP512_TEST_VECTORS	8
+-
+-static struct hash_testvec wp512_tv_template[] = {
++static const struct hash_testvec wp512_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -2411,9 +2605,7 @@ static struct hash_testvec wp512_tv_temp
+ 	},
+ };
+ 
+-#define WP384_TEST_VECTORS	8
+-
+-static struct hash_testvec wp384_tv_template[] = {
++static const struct hash_testvec wp384_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -2493,9 +2685,7 @@ static struct hash_testvec wp384_tv_temp
+ 	},
+ };
+ 
+-#define WP256_TEST_VECTORS	8
+-
+-static struct hash_testvec wp256_tv_template[] = {
++static const struct hash_testvec wp256_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -2562,9 +2752,7 @@ static struct hash_testvec wp256_tv_temp
+ /*
+  * TIGER test vectors from Tiger website
+  */
+-#define TGR192_TEST_VECTORS	6
+-
+-static struct hash_testvec tgr192_tv_template[] = {
++static const struct hash_testvec tgr192_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -2607,9 +2795,7 @@ static struct hash_testvec tgr192_tv_tem
+ 	},
+ };
+ 
+-#define TGR160_TEST_VECTORS	6
+-
+-static struct hash_testvec tgr160_tv_template[] = {
++static const struct hash_testvec tgr160_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -2652,9 +2838,7 @@ static struct hash_testvec tgr160_tv_tem
+ 	},
+ };
+ 
+-#define TGR128_TEST_VECTORS	6
+-
+-static struct hash_testvec tgr128_tv_template[] = {
++static const struct hash_testvec tgr128_tv_template[] = {
+ 	{
+ 		.plaintext = "",
+ 		.psize	= 0,
+@@ -2691,9 +2875,7 @@ static struct hash_testvec tgr128_tv_tem
+ 	},
+ };
+ 
+-#define GHASH_TEST_VECTORS 6
+-
+-static struct hash_testvec ghash_tv_template[] =
++static const struct hash_testvec ghash_tv_template[] =
+ {
+ 	{
+ 		.key	= "\xdf\xa6\xbf\x4d\xed\x81\xdb\x03"
+@@ -2808,9 +2990,7 @@ static struct hash_testvec ghash_tv_temp
+  * HMAC-MD5 test vectors from RFC2202
+  * (These need to be fixed to not use strlen).
+  */
+-#define HMAC_MD5_TEST_VECTORS	7
+-
+-static struct hash_testvec hmac_md5_tv_template[] =
++static const struct hash_testvec hmac_md5_tv_template[] =
+ {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
+@@ -2890,9 +3070,7 @@ static struct hash_testvec hmac_md5_tv_t
+ /*
+  * HMAC-RIPEMD128 test vectors from RFC2286
+  */
+-#define HMAC_RMD128_TEST_VECTORS	7
+-
+-static struct hash_testvec hmac_rmd128_tv_template[] = {
++static const struct hash_testvec hmac_rmd128_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
+ 		.ksize	= 16,
+@@ -2971,9 +3149,7 @@ static struct hash_testvec hmac_rmd128_t
+ /*
+  * HMAC-RIPEMD160 test vectors from RFC2286
+  */
+-#define HMAC_RMD160_TEST_VECTORS	7
+-
+-static struct hash_testvec hmac_rmd160_tv_template[] = {
++static const struct hash_testvec hmac_rmd160_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
+ 		.ksize	= 20,
+@@ -3052,9 +3228,7 @@ static struct hash_testvec hmac_rmd160_t
+ /*
+  * HMAC-SHA1 test vectors from RFC2202
+  */
+-#define HMAC_SHA1_TEST_VECTORS	7
+-
+-static struct hash_testvec hmac_sha1_tv_template[] = {
++static const struct hash_testvec hmac_sha1_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
+ 		.ksize	= 20,
+@@ -3135,9 +3309,7 @@ static struct hash_testvec hmac_sha1_tv_
+ /*
+  * SHA224 HMAC test vectors from RFC4231
+  */
+-#define HMAC_SHA224_TEST_VECTORS    4
+-
+-static struct hash_testvec hmac_sha224_tv_template[] = {
++static const struct hash_testvec hmac_sha224_tv_template[] = {
+ 	{
+ 		.key    = "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ 			"\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+@@ -3250,9 +3422,7 @@ static struct hash_testvec hmac_sha224_t
+  * HMAC-SHA256 test vectors from
+  * draft-ietf-ipsec-ciph-sha-256-01.txt
+  */
+-#define HMAC_SHA256_TEST_VECTORS	10
+-
+-static struct hash_testvec hmac_sha256_tv_template[] = {
++static const struct hash_testvec hmac_sha256_tv_template[] = {
+ 	{
+ 		.key	= "\x01\x02\x03\x04\x05\x06\x07\x08"
+ 			  "\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10"
+@@ -3387,9 +3557,7 @@ static struct hash_testvec hmac_sha256_t
+ 	},
+ };
+ 
+-#define CMAC_AES_TEST_VECTORS 6
+-
+-static struct hash_testvec aes_cmac128_tv_template[] = {
++static const struct hash_testvec aes_cmac128_tv_template[] = {
+ 	{ /* From NIST Special Publication 800-38B, AES-128 */
+ 		.key		= "\x2b\x7e\x15\x16\x28\xae\xd2\xa6"
+ 				  "\xab\xf7\x15\x88\x09\xcf\x4f\x3c",
+@@ -3464,9 +3632,67 @@ static struct hash_testvec aes_cmac128_t
+ 	}
+ };
+ 
+-#define CMAC_DES3_EDE_TEST_VECTORS 4
++static const struct hash_testvec aes_cbcmac_tv_template[] = {
++	{
++		.key		= "\x2b\x7e\x15\x16\x28\xae\xd2\xa6"
++				  "\xab\xf7\x15\x88\x09\xcf\x4f\x3c",
++		.plaintext	= "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96"
++				  "\xe9\x3d\x7e\x11\x73\x93\x17\x2a",
++		.digest		= "\x3a\xd7\x7b\xb4\x0d\x7a\x36\x60"
++				  "\xa8\x9e\xca\xf3\x24\x66\xef\x97",
++		.psize		= 16,
++		.ksize		= 16,
++	}, {
++		.key		= "\x2b\x7e\x15\x16\x28\xae\xd2\xa6"
++				  "\xab\xf7\x15\x88\x09\xcf\x4f\x3c",
++		.plaintext	= "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96"
++				  "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
++				  "\xae\x2d\x8a\x57\x1e\x03\xac\x9c"
++				  "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51"
++				  "\x30",
++		.digest		= "\x9d\x0d\xd0\x63\xfb\xcb\x24\x43"
++				  "\xf8\xf2\x76\x03\xac\x39\xb0\x9d",
++		.psize		= 33,
++		.ksize		= 16,
++		.np		= 2,
++		.tap		= { 7, 26 },
++	}, {
++		.key		= "\x2b\x7e\x15\x16\x28\xae\xd2\xa6"
++				  "\xab\xf7\x15\x88\x09\xcf\x4f\x3c",
++		.plaintext	= "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96"
++				  "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
++				  "\xae\x2d\x8a\x57\x1e\x03\xac\x9c"
++				  "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51"
++				  "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
++				  "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef"
++				  "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17"
++				  "\xad\x2b\x41\x7b\xe6\x6c\x37",
++		.digest		= "\xc0\x71\x73\xb8\xa0\x2c\x11\x7c"
++				  "\xaf\xdc\xb2\xf8\x89\x32\xa3\x3a",
++		.psize		= 63,
++		.ksize		= 16,
++	}, {
++		.key		= "\x60\x3d\xeb\x10\x15\xca\x71\xbe"
++				  "\x2b\x73\xae\xf0\x85\x7d\x77\x81"
++				  "\x1f\x35\x2c\x07\x3b\x61\x08\xd7"
++				  "\x2d\x98\x10\xa3\x09\x14\xdf\xf4",
++		.plaintext	= "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96"
++				  "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
++				  "\xae\x2d\x8a\x57\x1e\x03\xac\x9c"
++				  "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51"
++				  "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11"
++				  "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef"
++				  "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17"
++				  "\xad\x2b\x41\x7b\xe6\x6c\x37\x10"
++				  "\x1c",
++		.digest		= "\x6a\x4e\xdb\x21\x47\x51\xdf\x4f"
++				  "\xa8\x4d\x4c\x10\x3b\x72\x7d\xd6",
++		.psize		= 65,
++		.ksize		= 32,
++	}
++};
+ 
+-static struct hash_testvec des3_ede_cmac64_tv_template[] = {
++static const struct hash_testvec des3_ede_cmac64_tv_template[] = {
+ /*
+  * From NIST Special Publication 800-38B, Three Key TDEA
+  * Corrected test vectors from:
+@@ -3512,9 +3738,7 @@ static struct hash_testvec des3_ede_cmac
+ 	}
+ };
+ 
+-#define XCBC_AES_TEST_VECTORS 6
+-
+-static struct hash_testvec aes_xcbc128_tv_template[] = {
++static const struct hash_testvec aes_xcbc128_tv_template[] = {
+ 	{
+ 		.key	= "\x00\x01\x02\x03\x04\x05\x06\x07"
+ 			  "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+@@ -3580,36 +3804,35 @@ static struct hash_testvec aes_xcbc128_t
+ 	}
+ };
+ 
+-#define VMAC_AES_TEST_VECTORS	11
+-static char vmac_string1[128] = {'\x01', '\x01', '\x01', '\x01',
+-				'\x02', '\x03', '\x02', '\x02',
+-				'\x02', '\x04', '\x01', '\x07',
+-				'\x04', '\x01', '\x04', '\x03',};
+-static char vmac_string2[128] = {'a', 'b', 'c',};
+-static char vmac_string3[128] = {'a', 'b', 'c', 'a', 'b', 'c',
+-				'a', 'b', 'c', 'a', 'b', 'c',
+-				'a', 'b', 'c', 'a', 'b', 'c',
+-				'a', 'b', 'c', 'a', 'b', 'c',
+-				'a', 'b', 'c', 'a', 'b', 'c',
+-				'a', 'b', 'c', 'a', 'b', 'c',
+-				'a', 'b', 'c', 'a', 'b', 'c',
+-				'a', 'b', 'c', 'a', 'b', 'c',
+-				};
+-
+-static char vmac_string4[17] = {'b', 'c', 'e', 'f',
+-				'i', 'j', 'l', 'm',
+-				'o', 'p', 'r', 's',
+-				't', 'u', 'w', 'x', 'z'};
+-
+-static char vmac_string5[127] = {'r', 'm', 'b', 't', 'c',
+-				 'o', 'l', 'k', ']', '%',
+-				 '9', '2', '7', '!', 'A'};
+-
+-static char vmac_string6[129] = {'p', 't', '*', '7', 'l',
+-				 'i', '!', '#', 'w', '0',
+-				 'z', '/', '4', 'A', 'n'};
++static const char vmac_string1[128] = {'\x01', '\x01', '\x01', '\x01',
++				       '\x02', '\x03', '\x02', '\x02',
++				       '\x02', '\x04', '\x01', '\x07',
++				       '\x04', '\x01', '\x04', '\x03',};
++static const char vmac_string2[128] = {'a', 'b', 'c',};
++static const char vmac_string3[128] = {'a', 'b', 'c', 'a', 'b', 'c',
++				       'a', 'b', 'c', 'a', 'b', 'c',
++				       'a', 'b', 'c', 'a', 'b', 'c',
++				       'a', 'b', 'c', 'a', 'b', 'c',
++				       'a', 'b', 'c', 'a', 'b', 'c',
++				       'a', 'b', 'c', 'a', 'b', 'c',
++				       'a', 'b', 'c', 'a', 'b', 'c',
++				       'a', 'b', 'c', 'a', 'b', 'c',
++				      };
++
++static const char vmac_string4[17] = {'b', 'c', 'e', 'f',
++				      'i', 'j', 'l', 'm',
++				      'o', 'p', 'r', 's',
++				      't', 'u', 'w', 'x', 'z'};
++
++static const char vmac_string5[127] = {'r', 'm', 'b', 't', 'c',
++				       'o', 'l', 'k', ']', '%',
++				       '9', '2', '7', '!', 'A'};
++
++static const char vmac_string6[129] = {'p', 't', '*', '7', 'l',
++				       'i', '!', '#', 'w', '0',
++				       'z', '/', '4', 'A', 'n'};
+ 
+-static struct hash_testvec aes_vmac128_tv_template[] = {
++static const struct hash_testvec aes_vmac128_tv_template[] = {
+ 	{
+ 		.key	= "\x00\x01\x02\x03\x04\x05\x06\x07"
+ 			  "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+@@ -3687,9 +3910,7 @@ static struct hash_testvec aes_vmac128_t
+  * SHA384 HMAC test vectors from RFC4231
+  */
+ 
+-#define HMAC_SHA384_TEST_VECTORS	4
+-
+-static struct hash_testvec hmac_sha384_tv_template[] = {
++static const struct hash_testvec hmac_sha384_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ 			  "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+@@ -3787,9 +4008,7 @@ static struct hash_testvec hmac_sha384_t
+  * SHA512 HMAC test vectors from RFC4231
+  */
+ 
+-#define HMAC_SHA512_TEST_VECTORS	4
+-
+-static struct hash_testvec hmac_sha512_tv_template[] = {
++static const struct hash_testvec hmac_sha512_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ 			  "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+@@ -3894,9 +4113,7 @@ static struct hash_testvec hmac_sha512_t
+ 	},
+ };
+ 
+-#define HMAC_SHA3_224_TEST_VECTORS	4
+-
+-static struct hash_testvec hmac_sha3_224_tv_template[] = {
++static const struct hash_testvec hmac_sha3_224_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ 			  "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+@@ -3985,9 +4202,7 @@ static struct hash_testvec hmac_sha3_224
+ 	},
+ };
+ 
+-#define HMAC_SHA3_256_TEST_VECTORS	4
+-
+-static struct hash_testvec hmac_sha3_256_tv_template[] = {
++static const struct hash_testvec hmac_sha3_256_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ 			  "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+@@ -4076,9 +4291,7 @@ static struct hash_testvec hmac_sha3_256
+ 	},
+ };
+ 
+-#define HMAC_SHA3_384_TEST_VECTORS	4
+-
+-static struct hash_testvec hmac_sha3_384_tv_template[] = {
++static const struct hash_testvec hmac_sha3_384_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ 			  "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+@@ -4175,9 +4388,7 @@ static struct hash_testvec hmac_sha3_384
+ 	},
+ };
+ 
+-#define HMAC_SHA3_512_TEST_VECTORS	4
+-
+-static struct hash_testvec hmac_sha3_512_tv_template[] = {
++static const struct hash_testvec hmac_sha3_512_tv_template[] = {
+ 	{
+ 		.key	= "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+ 			  "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+@@ -4286,9 +4497,7 @@ static struct hash_testvec hmac_sha3_512
+  * Poly1305 test vectors from RFC7539 A.3.
+  */
+ 
+-#define POLY1305_TEST_VECTORS	11
+-
+-static struct hash_testvec poly1305_tv_template[] = {
++static const struct hash_testvec poly1305_tv_template[] = {
+ 	{ /* Test Vector #1 */
+ 		.plaintext	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+ 				  "\x00\x00\x00\x00\x00\x00\x00\x00"
+@@ -4533,20 +4742,7 @@ static struct hash_testvec poly1305_tv_t
+ /*
+  * DES test vectors.
+  */
+-#define DES_ENC_TEST_VECTORS		11
+-#define DES_DEC_TEST_VECTORS		5
+-#define DES_CBC_ENC_TEST_VECTORS	6
+-#define DES_CBC_DEC_TEST_VECTORS	5
+-#define DES_CTR_ENC_TEST_VECTORS	2
+-#define DES_CTR_DEC_TEST_VECTORS	2
+-#define DES3_EDE_ENC_TEST_VECTORS	4
+-#define DES3_EDE_DEC_TEST_VECTORS	4
+-#define DES3_EDE_CBC_ENC_TEST_VECTORS	2
+-#define DES3_EDE_CBC_DEC_TEST_VECTORS	2
+-#define DES3_EDE_CTR_ENC_TEST_VECTORS	2
+-#define DES3_EDE_CTR_DEC_TEST_VECTORS	2
+-
+-static struct cipher_testvec des_enc_tv_template[] = {
++static const struct cipher_testvec des_enc_tv_template[] = {
+ 	{ /* From Applied Cryptography */
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef",
+ 		.klen	= 8,
+@@ -4720,7 +4916,7 @@ static struct cipher_testvec des_enc_tv_
+ 	},
+ };
+ 
+-static struct cipher_testvec des_dec_tv_template[] = {
++static const struct cipher_testvec des_dec_tv_template[] = {
+ 	{ /* From Applied Cryptography */
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef",
+ 		.klen	= 8,
+@@ -4830,7 +5026,7 @@ static struct cipher_testvec des_dec_tv_
+ 	},
+ };
+ 
+-static struct cipher_testvec des_cbc_enc_tv_template[] = {
++static const struct cipher_testvec des_cbc_enc_tv_template[] = {
+ 	{ /* From OpenSSL */
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef",
+ 		.klen	= 8,
+@@ -4956,7 +5152,7 @@ static struct cipher_testvec des_cbc_enc
+ 	},
+ };
+ 
+-static struct cipher_testvec des_cbc_dec_tv_template[] = {
++static const struct cipher_testvec des_cbc_dec_tv_template[] = {
+ 	{ /* FIPS Pub 81 */
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef",
+ 		.klen	= 8,
+@@ -5065,7 +5261,7 @@ static struct cipher_testvec des_cbc_dec
+ 	},
+ };
+ 
+-static struct cipher_testvec des_ctr_enc_tv_template[] = {
++static const struct cipher_testvec des_ctr_enc_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\xC9\x83\xA6\xC9\xEC\x0F\x32\x55",
+ 		.klen	= 8,
+@@ -5211,7 +5407,7 @@ static struct cipher_testvec des_ctr_enc
+ 	},
+ };
+ 
+-static struct cipher_testvec des_ctr_dec_tv_template[] = {
++static const struct cipher_testvec des_ctr_dec_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\xC9\x83\xA6\xC9\xEC\x0F\x32\x55",
+ 		.klen	= 8,
+@@ -5357,7 +5553,7 @@ static struct cipher_testvec des_ctr_dec
+ 	},
+ };
+ 
+-static struct cipher_testvec des3_ede_enc_tv_template[] = {
++static const struct cipher_testvec des3_ede_enc_tv_template[] = {
+ 	{ /* These are from openssl */
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ 			  "\x55\x55\x55\x55\x55\x55\x55\x55"
+@@ -5522,7 +5718,7 @@ static struct cipher_testvec des3_ede_en
+ 	},
+ };
+ 
+-static struct cipher_testvec des3_ede_dec_tv_template[] = {
++static const struct cipher_testvec des3_ede_dec_tv_template[] = {
+ 	{ /* These are from openssl */
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ 			  "\x55\x55\x55\x55\x55\x55\x55\x55"
+@@ -5687,7 +5883,7 @@ static struct cipher_testvec des3_ede_de
+ 	},
+ };
+ 
+-static struct cipher_testvec des3_ede_cbc_enc_tv_template[] = {
++static const struct cipher_testvec des3_ede_cbc_enc_tv_template[] = {
+ 	{ /* Generated from openssl */
+ 		.key	= "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
+ 			  "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
+@@ -5867,7 +6063,7 @@ static struct cipher_testvec des3_ede_cb
+ 	},
+ };
+ 
+-static struct cipher_testvec des3_ede_cbc_dec_tv_template[] = {
++static const struct cipher_testvec des3_ede_cbc_dec_tv_template[] = {
+ 	{ /* Generated from openssl */
+ 		.key	= "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
+ 			  "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
+@@ -6047,7 +6243,7 @@ static struct cipher_testvec des3_ede_cb
+ 	},
+ };
+ 
+-static struct cipher_testvec des3_ede_ctr_enc_tv_template[] = {
++static const struct cipher_testvec des3_ede_ctr_enc_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x9C\xD6\xF3\x9C\xB9\x5A\x67\x00"
+ 			  "\x5A\x67\x00\x2D\xCE\xEB\x2D\xCE"
+@@ -6325,7 +6521,7 @@ static struct cipher_testvec des3_ede_ct
+ 	},
+ };
+ 
+-static struct cipher_testvec des3_ede_ctr_dec_tv_template[] = {
++static const struct cipher_testvec des3_ede_ctr_dec_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x9C\xD6\xF3\x9C\xB9\x5A\x67\x00"
+ 			  "\x5A\x67\x00\x2D\xCE\xEB\x2D\xCE"
+@@ -6606,14 +6802,7 @@ static struct cipher_testvec des3_ede_ct
+ /*
+  * Blowfish test vectors.
+  */
+-#define BF_ENC_TEST_VECTORS	7
+-#define BF_DEC_TEST_VECTORS	7
+-#define BF_CBC_ENC_TEST_VECTORS	2
+-#define BF_CBC_DEC_TEST_VECTORS	2
+-#define BF_CTR_ENC_TEST_VECTORS	2
+-#define BF_CTR_DEC_TEST_VECTORS	2
+-
+-static struct cipher_testvec bf_enc_tv_template[] = {
++static const struct cipher_testvec bf_enc_tv_template[] = {
+ 	{ /* DES test vectors from OpenSSL */
+ 		.key	= "\x00\x00\x00\x00\x00\x00\x00\x00",
+ 		.klen	= 8,
+@@ -6805,7 +6994,7 @@ static struct cipher_testvec bf_enc_tv_t
+ 	},
+ };
+ 
+-static struct cipher_testvec bf_dec_tv_template[] = {
++static const struct cipher_testvec bf_dec_tv_template[] = {
+ 	{ /* DES test vectors from OpenSSL */
+ 		.key	= "\x00\x00\x00\x00\x00\x00\x00\x00",
+ 		.klen	= 8,
+@@ -6997,7 +7186,7 @@ static struct cipher_testvec bf_dec_tv_t
+ 	},
+ };
+ 
+-static struct cipher_testvec bf_cbc_enc_tv_template[] = {
++static const struct cipher_testvec bf_cbc_enc_tv_template[] = {
+ 	{ /* From OpenSSL */
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ 			  "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
+@@ -7154,7 +7343,7 @@ static struct cipher_testvec bf_cbc_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec bf_cbc_dec_tv_template[] = {
++static const struct cipher_testvec bf_cbc_dec_tv_template[] = {
+ 	{ /* From OpenSSL */
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ 			  "\xf0\xe1\xd2\xc3\xb4\xa5\x96\x87",
+@@ -7311,7 +7500,7 @@ static struct cipher_testvec bf_cbc_dec_
+ 	},
+ };
+ 
+-static struct cipher_testvec bf_ctr_enc_tv_template[] = {
++static const struct cipher_testvec bf_ctr_enc_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -7723,7 +7912,7 @@ static struct cipher_testvec bf_ctr_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec bf_ctr_dec_tv_template[] = {
++static const struct cipher_testvec bf_ctr_dec_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -8138,18 +8327,7 @@ static struct cipher_testvec bf_ctr_dec_
+ /*
+  * Twofish test vectors.
+  */
+-#define TF_ENC_TEST_VECTORS		4
+-#define TF_DEC_TEST_VECTORS		4
+-#define TF_CBC_ENC_TEST_VECTORS		5
+-#define TF_CBC_DEC_TEST_VECTORS		5
+-#define TF_CTR_ENC_TEST_VECTORS		2
+-#define TF_CTR_DEC_TEST_VECTORS		2
+-#define TF_LRW_ENC_TEST_VECTORS		8
+-#define TF_LRW_DEC_TEST_VECTORS		8
+-#define TF_XTS_ENC_TEST_VECTORS		5
+-#define TF_XTS_DEC_TEST_VECTORS		5
+-
+-static struct cipher_testvec tf_enc_tv_template[] = {
++static const struct cipher_testvec tf_enc_tv_template[] = {
+ 	{
+ 		.key	= zeroed_string,
+ 		.klen	= 16,
+@@ -8317,7 +8495,7 @@ static struct cipher_testvec tf_enc_tv_t
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_dec_tv_template[] = {
++static const struct cipher_testvec tf_dec_tv_template[] = {
+ 	{
+ 		.key	= zeroed_string,
+ 		.klen	= 16,
+@@ -8485,7 +8663,7 @@ static struct cipher_testvec tf_dec_tv_t
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_cbc_enc_tv_template[] = {
++static const struct cipher_testvec tf_cbc_enc_tv_template[] = {
+ 	{ /* Generated with Nettle */
+ 		.key	= zeroed_string,
+ 		.klen	= 16,
+@@ -8668,7 +8846,7 @@ static struct cipher_testvec tf_cbc_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_cbc_dec_tv_template[] = {
++static const struct cipher_testvec tf_cbc_dec_tv_template[] = {
+ 	{ /* Reverse of the first four above */
+ 		.key	= zeroed_string,
+ 		.klen	= 16,
+@@ -8851,7 +9029,7 @@ static struct cipher_testvec tf_cbc_dec_
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_ctr_enc_tv_template[] = {
++static const struct cipher_testvec tf_ctr_enc_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -9262,7 +9440,7 @@ static struct cipher_testvec tf_ctr_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_ctr_dec_tv_template[] = {
++static const struct cipher_testvec tf_ctr_dec_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -9673,7 +9851,7 @@ static struct cipher_testvec tf_ctr_dec_
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_lrw_enc_tv_template[] = {
++static const struct cipher_testvec tf_lrw_enc_tv_template[] = {
+ 	/* Generated from AES-LRW test vectors */
+ 	{
+ 		.key	= "\x45\x62\xac\x25\xf8\x28\x17\x6d"
+@@ -9925,7 +10103,7 @@ static struct cipher_testvec tf_lrw_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_lrw_dec_tv_template[] = {
++static const struct cipher_testvec tf_lrw_dec_tv_template[] = {
+ 	/* Generated from AES-LRW test vectors */
+ 	/* same as enc vectors with input and result reversed */
+ 	{
+@@ -10178,7 +10356,7 @@ static struct cipher_testvec tf_lrw_dec_
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_xts_enc_tv_template[] = {
++static const struct cipher_testvec tf_xts_enc_tv_template[] = {
+ 	/* Generated from AES-XTS test vectors */
+ {
+ 		.key	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+@@ -10520,7 +10698,7 @@ static struct cipher_testvec tf_xts_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec tf_xts_dec_tv_template[] = {
++static const struct cipher_testvec tf_xts_dec_tv_template[] = {
+ 	/* Generated from AES-XTS test vectors */
+ 	/* same as enc vectors with input and result reversed */
+ 	{
+@@ -10867,25 +11045,7 @@ static struct cipher_testvec tf_xts_dec_
+  * Serpent test vectors.  These are backwards because Serpent writes
+  * octet sequences in right-to-left mode.
+  */
+-#define SERPENT_ENC_TEST_VECTORS	5
+-#define SERPENT_DEC_TEST_VECTORS	5
+-
+-#define TNEPRES_ENC_TEST_VECTORS	4
+-#define TNEPRES_DEC_TEST_VECTORS	4
+-
+-#define SERPENT_CBC_ENC_TEST_VECTORS	1
+-#define SERPENT_CBC_DEC_TEST_VECTORS	1
+-
+-#define SERPENT_CTR_ENC_TEST_VECTORS	2
+-#define SERPENT_CTR_DEC_TEST_VECTORS	2
+-
+-#define SERPENT_LRW_ENC_TEST_VECTORS	8
+-#define SERPENT_LRW_DEC_TEST_VECTORS	8
+-
+-#define SERPENT_XTS_ENC_TEST_VECTORS	5
+-#define SERPENT_XTS_DEC_TEST_VECTORS	5
+-
+-static struct cipher_testvec serpent_enc_tv_template[] = {
++static const struct cipher_testvec serpent_enc_tv_template[] = {
+ 	{
+ 		.input	= "\x00\x01\x02\x03\x04\x05\x06\x07"
+ 			  "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+@@ -11061,7 +11221,7 @@ static struct cipher_testvec serpent_enc
+ 	},
+ };
+ 
+-static struct cipher_testvec tnepres_enc_tv_template[] = {
++static const struct cipher_testvec tnepres_enc_tv_template[] = {
+ 	{ /* KeySize=128, PT=0, I=1 */
+ 		.input	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+ 			  "\x00\x00\x00\x00\x00\x00\x00\x00",
+@@ -11111,7 +11271,7 @@ static struct cipher_testvec tnepres_enc
+ };
+ 
+ 
+-static struct cipher_testvec serpent_dec_tv_template[] = {
++static const struct cipher_testvec serpent_dec_tv_template[] = {
+ 	{
+ 		.input	= "\x12\x07\xfc\xce\x9b\xd0\xd6\x47"
+ 			  "\x6a\xe9\x8f\xbe\xd1\x43\xa0\xe2",
+@@ -11287,7 +11447,7 @@ static struct cipher_testvec serpent_dec
+ 	},
+ };
+ 
+-static struct cipher_testvec tnepres_dec_tv_template[] = {
++static const struct cipher_testvec tnepres_dec_tv_template[] = {
+ 	{
+ 		.input	= "\x41\xcc\x6b\x31\x59\x31\x45\x97"
+ 			  "\x6d\x6f\xbb\x38\x4b\x37\x21\x28",
+@@ -11328,7 +11488,7 @@ static struct cipher_testvec tnepres_dec
+ 	},
+ };
+ 
+-static struct cipher_testvec serpent_cbc_enc_tv_template[] = {
++static const struct cipher_testvec serpent_cbc_enc_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -11469,7 +11629,7 @@ static struct cipher_testvec serpent_cbc
+ 	},
+ };
+ 
+-static struct cipher_testvec serpent_cbc_dec_tv_template[] = {
++static const struct cipher_testvec serpent_cbc_dec_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -11610,7 +11770,7 @@ static struct cipher_testvec serpent_cbc
+ 	},
+ };
+ 
+-static struct cipher_testvec serpent_ctr_enc_tv_template[] = {
++static const struct cipher_testvec serpent_ctr_enc_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -12021,7 +12181,7 @@ static struct cipher_testvec serpent_ctr
+ 	},
+ };
+ 
+-static struct cipher_testvec serpent_ctr_dec_tv_template[] = {
++static const struct cipher_testvec serpent_ctr_dec_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -12432,7 +12592,7 @@ static struct cipher_testvec serpent_ctr
+ 	},
+ };
+ 
+-static struct cipher_testvec serpent_lrw_enc_tv_template[] = {
++static const struct cipher_testvec serpent_lrw_enc_tv_template[] = {
+ 	/* Generated from AES-LRW test vectors */
+ 	{
+ 		.key	= "\x45\x62\xac\x25\xf8\x28\x17\x6d"
+@@ -12684,7 +12844,7 @@ static struct cipher_testvec serpent_lrw
+ 	},
+ };
+ 
+-static struct cipher_testvec serpent_lrw_dec_tv_template[] = {
++static const struct cipher_testvec serpent_lrw_dec_tv_template[] = {
+ 	/* Generated from AES-LRW test vectors */
+ 	/* same as enc vectors with input and result reversed */
+ 	{
+@@ -12937,7 +13097,7 @@ static struct cipher_testvec serpent_lrw
+ 	},
+ };
+ 
+-static struct cipher_testvec serpent_xts_enc_tv_template[] = {
++static const struct cipher_testvec serpent_xts_enc_tv_template[] = {
+ 	/* Generated from AES-XTS test vectors */
+ 	{
+ 		.key	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+@@ -13279,7 +13439,7 @@ static struct cipher_testvec serpent_xts
+ 	},
+ };
+ 
+-static struct cipher_testvec serpent_xts_dec_tv_template[] = {
++static const struct cipher_testvec serpent_xts_dec_tv_template[] = {
+ 	/* Generated from AES-XTS test vectors */
+ 	/* same as enc vectors with input and result reversed */
+ 	{
+@@ -13623,18 +13783,7 @@ static struct cipher_testvec serpent_xts
+ };
+ 
+ /* Cast6 test vectors from RFC 2612 */
+-#define CAST6_ENC_TEST_VECTORS		4
+-#define CAST6_DEC_TEST_VECTORS		4
+-#define CAST6_CBC_ENC_TEST_VECTORS	1
+-#define CAST6_CBC_DEC_TEST_VECTORS	1
+-#define CAST6_CTR_ENC_TEST_VECTORS	2
+-#define CAST6_CTR_DEC_TEST_VECTORS	2
+-#define CAST6_LRW_ENC_TEST_VECTORS	1
+-#define CAST6_LRW_DEC_TEST_VECTORS	1
+-#define CAST6_XTS_ENC_TEST_VECTORS	1
+-#define CAST6_XTS_DEC_TEST_VECTORS	1
+-
+-static struct cipher_testvec cast6_enc_tv_template[] = {
++static const struct cipher_testvec cast6_enc_tv_template[] = {
+ 	{
+ 		.key	= "\x23\x42\xbb\x9e\xfa\x38\x54\x2c"
+ 			  "\x0a\xf7\x56\x47\xf2\x9f\x61\x5d",
+@@ -13805,7 +13954,7 @@ static struct cipher_testvec cast6_enc_t
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_dec_tv_template[] = {
++static const struct cipher_testvec cast6_dec_tv_template[] = {
+ 	{
+ 		.key	= "\x23\x42\xbb\x9e\xfa\x38\x54\x2c"
+ 			  "\x0a\xf7\x56\x47\xf2\x9f\x61\x5d",
+@@ -13976,7 +14125,7 @@ static struct cipher_testvec cast6_dec_t
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_cbc_enc_tv_template[] = {
++static const struct cipher_testvec cast6_cbc_enc_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -14117,7 +14266,7 @@ static struct cipher_testvec cast6_cbc_e
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_cbc_dec_tv_template[] = {
++static const struct cipher_testvec cast6_cbc_dec_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -14258,7 +14407,7 @@ static struct cipher_testvec cast6_cbc_d
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_ctr_enc_tv_template[] = {
++static const struct cipher_testvec cast6_ctr_enc_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -14415,7 +14564,7 @@ static struct cipher_testvec cast6_ctr_e
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_ctr_dec_tv_template[] = {
++static const struct cipher_testvec cast6_ctr_dec_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -14572,7 +14721,7 @@ static struct cipher_testvec cast6_ctr_d
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_lrw_enc_tv_template[] = {
++static const struct cipher_testvec cast6_lrw_enc_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\xf8\xd4\x76\xff\xd6\x46\xee\x6c"
+ 			  "\x23\x84\xcb\x1c\x77\xd6\x19\x5d"
+@@ -14719,7 +14868,7 @@ static struct cipher_testvec cast6_lrw_e
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_lrw_dec_tv_template[] = {
++static const struct cipher_testvec cast6_lrw_dec_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\xf8\xd4\x76\xff\xd6\x46\xee\x6c"
+ 			  "\x23\x84\xcb\x1c\x77\xd6\x19\x5d"
+@@ -14866,7 +15015,7 @@ static struct cipher_testvec cast6_lrw_d
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_xts_enc_tv_template[] = {
++static const struct cipher_testvec cast6_xts_enc_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x27\x18\x28\x18\x28\x45\x90\x45"
+ 			  "\x23\x53\x60\x28\x74\x71\x35\x26"
+@@ -15015,7 +15164,7 @@ static struct cipher_testvec cast6_xts_e
+ 	},
+ };
+ 
+-static struct cipher_testvec cast6_xts_dec_tv_template[] = {
++static const struct cipher_testvec cast6_xts_dec_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x27\x18\x28\x18\x28\x45\x90\x45"
+ 			  "\x23\x53\x60\x28\x74\x71\x35\x26"
+@@ -15168,39 +15317,7 @@ static struct cipher_testvec cast6_xts_d
+ /*
+  * AES test vectors.
+  */
+-#define AES_ENC_TEST_VECTORS 4
+-#define AES_DEC_TEST_VECTORS 4
+-#define AES_CBC_ENC_TEST_VECTORS 5
+-#define AES_CBC_DEC_TEST_VECTORS 5
+-#define HMAC_MD5_ECB_CIPHER_NULL_ENC_TEST_VECTORS 2
+-#define HMAC_MD5_ECB_CIPHER_NULL_DEC_TEST_VECTORS 2
+-#define HMAC_SHA1_ECB_CIPHER_NULL_ENC_TEST_VEC 2
+-#define HMAC_SHA1_ECB_CIPHER_NULL_DEC_TEST_VEC 2
+-#define HMAC_SHA1_AES_CBC_ENC_TEST_VEC 7
+-#define HMAC_SHA256_AES_CBC_ENC_TEST_VEC 7
+-#define HMAC_SHA512_AES_CBC_ENC_TEST_VEC 7
+-#define AES_LRW_ENC_TEST_VECTORS 8
+-#define AES_LRW_DEC_TEST_VECTORS 8
+-#define AES_XTS_ENC_TEST_VECTORS 5
+-#define AES_XTS_DEC_TEST_VECTORS 5
+-#define AES_CTR_ENC_TEST_VECTORS 5
+-#define AES_CTR_DEC_TEST_VECTORS 5
+-#define AES_OFB_ENC_TEST_VECTORS 1
+-#define AES_OFB_DEC_TEST_VECTORS 1
+-#define AES_CTR_3686_ENC_TEST_VECTORS 7
+-#define AES_CTR_3686_DEC_TEST_VECTORS 6
+-#define AES_GCM_ENC_TEST_VECTORS 9
+-#define AES_GCM_DEC_TEST_VECTORS 8
+-#define AES_GCM_4106_ENC_TEST_VECTORS 23
+-#define AES_GCM_4106_DEC_TEST_VECTORS 23
+-#define AES_GCM_4543_ENC_TEST_VECTORS 1
+-#define AES_GCM_4543_DEC_TEST_VECTORS 2
+-#define AES_CCM_ENC_TEST_VECTORS 8
+-#define AES_CCM_DEC_TEST_VECTORS 7
+-#define AES_CCM_4309_ENC_TEST_VECTORS 7
+-#define AES_CCM_4309_DEC_TEST_VECTORS 10
+-
+-static struct cipher_testvec aes_enc_tv_template[] = {
++static const struct cipher_testvec aes_enc_tv_template[] = {
+ 	{ /* From FIPS-197 */
+ 		.key	= "\x00\x01\x02\x03\x04\x05\x06\x07"
+ 			  "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+@@ -15372,7 +15489,7 @@ static struct cipher_testvec aes_enc_tv_
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_dec_tv_template[] = {
++static const struct cipher_testvec aes_dec_tv_template[] = {
+ 	{ /* From FIPS-197 */
+ 		.key	= "\x00\x01\x02\x03\x04\x05\x06\x07"
+ 			  "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f",
+@@ -15544,7 +15661,7 @@ static struct cipher_testvec aes_dec_tv_
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_cbc_enc_tv_template[] = {
++static const struct cipher_testvec aes_cbc_enc_tv_template[] = {
+ 	{ /* From RFC 3602 */
+ 		.key    = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
+ 			  "\x51\x2e\x03\xd5\x34\x12\x00\x06",
+@@ -15766,7 +15883,7 @@ static struct cipher_testvec aes_cbc_enc
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_cbc_dec_tv_template[] = {
++static const struct cipher_testvec aes_cbc_dec_tv_template[] = {
+ 	{ /* From RFC 3602 */
+ 		.key    = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
+ 			  "\x51\x2e\x03\xd5\x34\x12\x00\x06",
+@@ -15988,7 +16105,7 @@ static struct cipher_testvec aes_cbc_dec
+ 	},
+ };
+ 
+-static struct aead_testvec hmac_md5_ecb_cipher_null_enc_tv_template[] = {
++static const struct aead_testvec hmac_md5_ecb_cipher_null_enc_tv_template[] = {
+ 	{ /* Input data from RFC 2410 Case 1 */
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -16030,7 +16147,7 @@ static struct aead_testvec hmac_md5_ecb_
+ 	},
+ };
+ 
+-static struct aead_testvec hmac_md5_ecb_cipher_null_dec_tv_template[] = {
++static const struct aead_testvec hmac_md5_ecb_cipher_null_dec_tv_template[] = {
+ 	{
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -16072,7 +16189,7 @@ static struct aead_testvec hmac_md5_ecb_
+ 	},
+ };
+ 
+-static struct aead_testvec hmac_sha1_aes_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha1_aes_cbc_enc_tv_temp[] = {
+ 	{ /* RFC 3602 Case 1 */
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -16341,7 +16458,7 @@ static struct aead_testvec hmac_sha1_aes
+ 	},
+ };
+ 
+-static struct aead_testvec hmac_sha1_ecb_cipher_null_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha1_ecb_cipher_null_enc_tv_temp[] = {
+ 	{ /* Input data from RFC 2410 Case 1 */
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -16387,7 +16504,7 @@ static struct aead_testvec hmac_sha1_ecb
+ 	},
+ };
+ 
+-static struct aead_testvec hmac_sha1_ecb_cipher_null_dec_tv_temp[] = {
++static const struct aead_testvec hmac_sha1_ecb_cipher_null_dec_tv_temp[] = {
+ 	{
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -16433,7 +16550,7 @@ static struct aead_testvec hmac_sha1_ecb
+ 	},
+ };
+ 
+-static struct aead_testvec hmac_sha256_aes_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha256_aes_cbc_enc_tv_temp[] = {
+ 	{ /* RFC 3602 Case 1 */
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -16716,7 +16833,7 @@ static struct aead_testvec hmac_sha256_a
+ 	},
+ };
+ 
+-static struct aead_testvec hmac_sha512_aes_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha512_aes_cbc_enc_tv_temp[] = {
+ 	{ /* RFC 3602 Case 1 */
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17055,9 +17172,7 @@ static struct aead_testvec hmac_sha512_a
+ 	},
+ };
+ 
+-#define HMAC_SHA1_DES_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha1_des_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha1_des_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17116,9 +17231,7 @@ static struct aead_testvec hmac_sha1_des
+ 	},
+ };
+ 
+-#define HMAC_SHA224_DES_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha224_des_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha224_des_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17177,9 +17290,7 @@ static struct aead_testvec hmac_sha224_d
+ 	},
+ };
+ 
+-#define HMAC_SHA256_DES_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha256_des_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha256_des_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17240,9 +17351,7 @@ static struct aead_testvec hmac_sha256_d
+ 	},
+ };
+ 
+-#define HMAC_SHA384_DES_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha384_des_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha384_des_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17307,9 +17416,7 @@ static struct aead_testvec hmac_sha384_d
+ 	},
+ };
+ 
+-#define HMAC_SHA512_DES_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha512_des_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha512_des_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17378,9 +17485,7 @@ static struct aead_testvec hmac_sha512_d
+ 	},
+ };
+ 
+-#define HMAC_SHA1_DES3_EDE_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha1_des3_ede_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha1_des3_ede_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17441,9 +17546,7 @@ static struct aead_testvec hmac_sha1_des
+ 	},
+ };
+ 
+-#define HMAC_SHA224_DES3_EDE_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha224_des3_ede_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha224_des3_ede_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17504,9 +17607,7 @@ static struct aead_testvec hmac_sha224_d
+ 	},
+ };
+ 
+-#define HMAC_SHA256_DES3_EDE_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha256_des3_ede_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha256_des3_ede_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17569,9 +17670,7 @@ static struct aead_testvec hmac_sha256_d
+ 	},
+ };
+ 
+-#define HMAC_SHA384_DES3_EDE_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha384_des3_ede_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha384_des3_ede_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17638,9 +17737,7 @@ static struct aead_testvec hmac_sha384_d
+ 	},
+ };
+ 
+-#define HMAC_SHA512_DES3_EDE_CBC_ENC_TEST_VEC	1
+-
+-static struct aead_testvec hmac_sha512_des3_ede_cbc_enc_tv_temp[] = {
++static const struct aead_testvec hmac_sha512_des3_ede_cbc_enc_tv_temp[] = {
+ 	{ /*Generated with cryptopp*/
+ #ifdef __LITTLE_ENDIAN
+ 		.key    = "\x08\x00"		/* rta length */
+@@ -17711,7 +17808,7 @@ static struct aead_testvec hmac_sha512_d
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_lrw_enc_tv_template[] = {
++static const struct cipher_testvec aes_lrw_enc_tv_template[] = {
+ 	/* from http://grouper.ieee.org/groups/1619/email/pdf00017.pdf */
+ 	{ /* LRW-32-AES 1 */
+ 		.key    = "\x45\x62\xac\x25\xf8\x28\x17\x6d"
+@@ -17964,7 +18061,7 @@ static struct cipher_testvec aes_lrw_enc
+ 	}
+ };
+ 
+-static struct cipher_testvec aes_lrw_dec_tv_template[] = {
++static const struct cipher_testvec aes_lrw_dec_tv_template[] = {
+ 	/* from http://grouper.ieee.org/groups/1619/email/pdf00017.pdf */
+ 	/* same as enc vectors with input and result reversed */
+ 	{ /* LRW-32-AES 1 */
+@@ -18218,7 +18315,7 @@ static struct cipher_testvec aes_lrw_dec
+ 	}
+ };
+ 
+-static struct cipher_testvec aes_xts_enc_tv_template[] = {
++static const struct cipher_testvec aes_xts_enc_tv_template[] = {
+ 	/* http://grouper.ieee.org/groups/1619/email/pdf00086.pdf */
+ 	{ /* XTS-AES 1 */
+ 		.key    = "\x00\x00\x00\x00\x00\x00\x00\x00"
+@@ -18561,7 +18658,7 @@ static struct cipher_testvec aes_xts_enc
+ 	}
+ };
+ 
+-static struct cipher_testvec aes_xts_dec_tv_template[] = {
++static const struct cipher_testvec aes_xts_dec_tv_template[] = {
+ 	/* http://grouper.ieee.org/groups/1619/email/pdf00086.pdf */
+ 	{ /* XTS-AES 1 */
+ 		.key    = "\x00\x00\x00\x00\x00\x00\x00\x00"
+@@ -18905,7 +19002,7 @@ static struct cipher_testvec aes_xts_dec
+ };
+ 
+ 
+-static struct cipher_testvec aes_ctr_enc_tv_template[] = {
++static const struct cipher_testvec aes_ctr_enc_tv_template[] = {
+ 	{ /* From NIST Special Publication 800-38A, Appendix F.5 */
+ 		.key	= "\x2b\x7e\x15\x16\x28\xae\xd2\xa6"
+ 			  "\xab\xf7\x15\x88\x09\xcf\x4f\x3c",
+@@ -19260,7 +19357,7 @@ static struct cipher_testvec aes_ctr_enc
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_ctr_dec_tv_template[] = {
++static const struct cipher_testvec aes_ctr_dec_tv_template[] = {
+ 	{ /* From NIST Special Publication 800-38A, Appendix F.5 */
+ 		.key	= "\x2b\x7e\x15\x16\x28\xae\xd2\xa6"
+ 			  "\xab\xf7\x15\x88\x09\xcf\x4f\x3c",
+@@ -19615,7 +19712,7 @@ static struct cipher_testvec aes_ctr_dec
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_ctr_rfc3686_enc_tv_template[] = {
++static const struct cipher_testvec aes_ctr_rfc3686_enc_tv_template[] = {
+ 	{ /* From RFC 3686 */
+ 		.key	= "\xae\x68\x52\xf8\x12\x10\x67\xcc"
+ 			  "\x4b\xf7\xa5\x76\x55\x77\xf3\x9e"
+@@ -20747,7 +20844,7 @@ static struct cipher_testvec aes_ctr_rfc
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_ctr_rfc3686_dec_tv_template[] = {
++static const struct cipher_testvec aes_ctr_rfc3686_dec_tv_template[] = {
+ 	{ /* From RFC 3686 */
+ 		.key	= "\xae\x68\x52\xf8\x12\x10\x67\xcc"
+ 			  "\x4b\xf7\xa5\x76\x55\x77\xf3\x9e"
+@@ -20838,7 +20935,7 @@ static struct cipher_testvec aes_ctr_rfc
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_ofb_enc_tv_template[] = {
++static const struct cipher_testvec aes_ofb_enc_tv_template[] = {
+ 	 /* From NIST Special Publication 800-38A, Appendix F.5 */
+ 	{
+ 		.key	= "\x2b\x7e\x15\x16\x28\xae\xd2\xa6"
+@@ -20867,7 +20964,7 @@ static struct cipher_testvec aes_ofb_enc
+ 	}
+ };
+ 
+-static struct cipher_testvec aes_ofb_dec_tv_template[] = {
++static const struct cipher_testvec aes_ofb_dec_tv_template[] = {
+ 	 /* From NIST Special Publication 800-38A, Appendix F.5 */
+ 	{
+ 		.key	= "\x2b\x7e\x15\x16\x28\xae\xd2\xa6"
+@@ -20896,7 +20993,7 @@ static struct cipher_testvec aes_ofb_dec
+ 	}
+ };
+ 
+-static struct aead_testvec aes_gcm_enc_tv_template[] = {
++static const struct aead_testvec aes_gcm_enc_tv_template[] = {
+ 	{ /* From McGrew & Viega - http://citeseer.ist.psu.edu/656989.html */
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -21056,7 +21153,7 @@ static struct aead_testvec aes_gcm_enc_t
+ 	}
+ };
+ 
+-static struct aead_testvec aes_gcm_dec_tv_template[] = {
++static const struct aead_testvec aes_gcm_dec_tv_template[] = {
+ 	{ /* From McGrew & Viega - http://citeseer.ist.psu.edu/656989.html */
+ 		.key    = zeroed_string,
+ 		.klen	= 32,
+@@ -21258,7 +21355,7 @@ static struct aead_testvec aes_gcm_dec_t
+ 	}
+ };
+ 
+-static struct aead_testvec aes_gcm_rfc4106_enc_tv_template[] = {
++static const struct aead_testvec aes_gcm_rfc4106_enc_tv_template[] = {
+ 	{ /* Generated using Crypto++ */
+ 		.key    = zeroed_string,
+ 		.klen	= 20,
+@@ -21871,7 +21968,7 @@ static struct aead_testvec aes_gcm_rfc41
+ 	}
+ };
+ 
+-static struct aead_testvec aes_gcm_rfc4106_dec_tv_template[] = {
++static const struct aead_testvec aes_gcm_rfc4106_dec_tv_template[] = {
+ 	{ /* Generated using Crypto++ */
+ 		.key    = zeroed_string,
+ 		.klen	= 20,
+@@ -22485,7 +22582,7 @@ static struct aead_testvec aes_gcm_rfc41
+ 	}
+ };
+ 
+-static struct aead_testvec aes_gcm_rfc4543_enc_tv_template[] = {
++static const struct aead_testvec aes_gcm_rfc4543_enc_tv_template[] = {
+ 	{ /* From draft-mcgrew-gcm-test-01 */
+ 		.key	= "\x4c\x80\xcd\xef\xbb\x5d\x10\xda"
+ 			  "\x90\x6a\xc7\x3c\x36\x13\xa6\x34"
+@@ -22516,7 +22613,7 @@ static struct aead_testvec aes_gcm_rfc45
+ 	}
+ };
+ 
+-static struct aead_testvec aes_gcm_rfc4543_dec_tv_template[] = {
++static const struct aead_testvec aes_gcm_rfc4543_dec_tv_template[] = {
+ 	{ /* From draft-mcgrew-gcm-test-01 */
+ 		.key	= "\x4c\x80\xcd\xef\xbb\x5d\x10\xda"
+ 			  "\x90\x6a\xc7\x3c\x36\x13\xa6\x34"
+@@ -22575,7 +22672,7 @@ static struct aead_testvec aes_gcm_rfc45
+ 	},
+ };
+ 
+-static struct aead_testvec aes_ccm_enc_tv_template[] = {
++static const struct aead_testvec aes_ccm_enc_tv_template[] = {
+ 	{ /* From RFC 3610 */
+ 		.key	= "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ 			  "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
+@@ -22859,7 +22956,7 @@ static struct aead_testvec aes_ccm_enc_t
+ 	}
+ };
+ 
+-static struct aead_testvec aes_ccm_dec_tv_template[] = {
++static const struct aead_testvec aes_ccm_dec_tv_template[] = {
+ 	{ /* From RFC 3610 */
+ 		.key	= "\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7"
+ 			  "\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf",
+@@ -23191,7 +23288,7 @@ static struct aead_testvec aes_ccm_dec_t
+  * These vectors are copied/generated from the ones for rfc4106 with
+  * the key truncated by one byte..
+  */
+-static struct aead_testvec aes_ccm_rfc4309_enc_tv_template[] = {
++static const struct aead_testvec aes_ccm_rfc4309_enc_tv_template[] = {
+ 	{ /* Generated using Crypto++ */
+ 		.key	= zeroed_string,
+ 		.klen	= 19,
+@@ -23804,7 +23901,7 @@ static struct aead_testvec aes_ccm_rfc43
+ 	}
+ };
+ 
+-static struct aead_testvec aes_ccm_rfc4309_dec_tv_template[]	= {
++static const struct aead_testvec aes_ccm_rfc4309_dec_tv_template[]	= {
+ 	{ /* Generated using Crypto++ */
+ 		.key	= zeroed_string,
+ 		.klen	= 19,
+@@ -24420,9 +24517,7 @@ static struct aead_testvec aes_ccm_rfc43
+ /*
+  * ChaCha20-Poly1305 AEAD test vectors from RFC7539 2.8.2./A.5.
+  */
+-#define RFC7539_ENC_TEST_VECTORS 2
+-#define RFC7539_DEC_TEST_VECTORS 2
+-static struct aead_testvec rfc7539_enc_tv_template[] = {
++static const struct aead_testvec rfc7539_enc_tv_template[] = {
+ 	{
+ 		.key	= "\x80\x81\x82\x83\x84\x85\x86\x87"
+ 			  "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f"
+@@ -24554,7 +24649,7 @@ static struct aead_testvec rfc7539_enc_t
+ 	},
+ };
+ 
+-static struct aead_testvec rfc7539_dec_tv_template[] = {
++static const struct aead_testvec rfc7539_dec_tv_template[] = {
+ 	{
+ 		.key	= "\x80\x81\x82\x83\x84\x85\x86\x87"
+ 			  "\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f"
+@@ -24689,9 +24784,7 @@ static struct aead_testvec rfc7539_dec_t
+ /*
+  * draft-irtf-cfrg-chacha20-poly1305
+  */
+-#define RFC7539ESP_DEC_TEST_VECTORS 1
+-#define RFC7539ESP_ENC_TEST_VECTORS 1
+-static struct aead_testvec rfc7539esp_enc_tv_template[] = {
++static const struct aead_testvec rfc7539esp_enc_tv_template[] = {
+ 	{
+ 		.key	= "\x1c\x92\x40\xa5\xeb\x55\xd3\x8a"
+ 			  "\xf3\x33\x88\x86\x04\xf6\xb5\xf0"
+@@ -24779,7 +24872,7 @@ static struct aead_testvec rfc7539esp_en
+ 	},
+ };
+ 
+-static struct aead_testvec rfc7539esp_dec_tv_template[] = {
++static const struct aead_testvec rfc7539esp_dec_tv_template[] = {
+ 	{
+ 		.key	= "\x1c\x92\x40\xa5\xeb\x55\xd3\x8a"
+ 			  "\xf3\x33\x88\x86\x04\xf6\xb5\xf0"
+@@ -24875,7 +24968,7 @@ static struct aead_testvec rfc7539esp_de
+  * semiblock of the ciphertext from the test vector. For decryption, iv is
+  * the first semiblock of the ciphertext.
+  */
+-static struct cipher_testvec aes_kw_enc_tv_template[] = {
++static const struct cipher_testvec aes_kw_enc_tv_template[] = {
+ 	{
+ 		.key	= "\x75\x75\xda\x3a\x93\x60\x7c\xc2"
+ 			  "\xbf\xd8\xce\xc7\xaa\xdf\xd9\xa6",
+@@ -24890,7 +24983,7 @@ static struct cipher_testvec aes_kw_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec aes_kw_dec_tv_template[] = {
++static const struct cipher_testvec aes_kw_dec_tv_template[] = {
+ 	{
+ 		.key	= "\x80\xaa\x99\x73\x27\xa4\x80\x6b"
+ 			  "\x6a\x7a\x41\xa5\x2b\x86\xc3\x71"
+@@ -24913,9 +25006,7 @@ static struct cipher_testvec aes_kw_dec_
+  *     http://csrc.nist.gov/groups/STM/cavp/documents/rng/RNGVS.pdf
+  * Only AES-128 is supported at this time.
+  */
+-#define ANSI_CPRNG_AES_TEST_VECTORS	6
+-
+-static struct cprng_testvec ansi_cprng_aes_tv_template[] = {
++static const struct cprng_testvec ansi_cprng_aes_tv_template[] = {
+ 	{
+ 		.key	= "\xf3\xb1\x66\x6d\x13\x60\x72\x42"
+ 			  "\xed\x06\x1c\xab\xb8\xd4\x62\x02",
+@@ -25011,7 +25102,7 @@ static struct cprng_testvec ansi_cprng_a
+  * (Hash, HMAC, CTR) are tested with all permutations of use cases (w/ and
+  * w/o personalization string, w/ and w/o additional input string).
+  */
+-static struct drbg_testvec drbg_pr_sha256_tv_template[] = {
++static const struct drbg_testvec drbg_pr_sha256_tv_template[] = {
+ 	{
+ 		.entropy = (unsigned char *)
+ 			"\x72\x88\x4c\xcd\x6c\x85\x57\x70\xf7\x0b\x8b\x86"
+@@ -25169,7 +25260,7 @@ static struct drbg_testvec drbg_pr_sha25
+ 	},
+ };
+ 
+-static struct drbg_testvec drbg_pr_hmac_sha256_tv_template[] = {
++static const struct drbg_testvec drbg_pr_hmac_sha256_tv_template[] = {
+ 	{
+ 		.entropy = (unsigned char *)
+ 			"\x99\x69\xe5\x4b\x47\x03\xff\x31\x78\x5b\x87\x9a"
+@@ -25327,7 +25418,7 @@ static struct drbg_testvec drbg_pr_hmac_
+ 	},
+ };
+ 
+-static struct drbg_testvec drbg_pr_ctr_aes128_tv_template[] = {
++static const struct drbg_testvec drbg_pr_ctr_aes128_tv_template[] = {
+ 	{
+ 		.entropy = (unsigned char *)
+ 			"\xd1\x44\xc6\x61\x81\x6d\xca\x9d\x15\x28\x8a\x42"
+@@ -25451,7 +25542,7 @@ static struct drbg_testvec drbg_pr_ctr_a
+  * (Hash, HMAC, CTR) are tested with all permutations of use cases (w/ and
+  * w/o personalization string, w/ and w/o additional input string).
+  */
+-static struct drbg_testvec drbg_nopr_sha256_tv_template[] = {
++static const struct drbg_testvec drbg_nopr_sha256_tv_template[] = {
+ 	{
+ 		.entropy = (unsigned char *)
+ 			"\xa6\x5a\xd0\xf3\x45\xdb\x4e\x0e\xff\xe8\x75\xc3"
+@@ -25573,7 +25664,7 @@ static struct drbg_testvec drbg_nopr_sha
+ 	},
+ };
+ 
+-static struct drbg_testvec drbg_nopr_hmac_sha256_tv_template[] = {
++static const struct drbg_testvec drbg_nopr_hmac_sha256_tv_template[] = {
+ 	{
+ 		.entropy = (unsigned char *)
+ 			"\xca\x85\x19\x11\x34\x93\x84\xbf\xfe\x89\xde\x1c"
+@@ -25695,7 +25786,7 @@ static struct drbg_testvec drbg_nopr_hma
+ 	},
+ };
+ 
+-static struct drbg_testvec drbg_nopr_ctr_aes192_tv_template[] = {
++static const struct drbg_testvec drbg_nopr_ctr_aes192_tv_template[] = {
+ 	{
+ 		.entropy = (unsigned char *)
+ 			"\xc3\x5c\x2f\xa2\xa8\x9d\x52\xa1\x1f\xa3\x2a\xa9"
+@@ -25719,7 +25810,7 @@ static struct drbg_testvec drbg_nopr_ctr
+ 	},
+ };
+ 
+-static struct drbg_testvec drbg_nopr_ctr_aes256_tv_template[] = {
++static const struct drbg_testvec drbg_nopr_ctr_aes256_tv_template[] = {
+ 	{
+ 		.entropy = (unsigned char *)
+ 			"\x36\x40\x19\x40\xfa\x8b\x1f\xba\x91\xa1\x66\x1f"
+@@ -25743,7 +25834,7 @@ static struct drbg_testvec drbg_nopr_ctr
+ 	},
+ };
+ 
+-static struct drbg_testvec drbg_nopr_ctr_aes128_tv_template[] = {
++static const struct drbg_testvec drbg_nopr_ctr_aes128_tv_template[] = {
+ 	{
+ 		.entropy = (unsigned char *)
+ 			"\x87\xe1\xc5\x32\x99\x7f\x57\xa3\x5c\x28\x6d\xe8"
+@@ -25832,14 +25923,7 @@ static struct drbg_testvec drbg_nopr_ctr
+ };
+ 
+ /* Cast5 test vectors from RFC 2144 */
+-#define CAST5_ENC_TEST_VECTORS		4
+-#define CAST5_DEC_TEST_VECTORS		4
+-#define CAST5_CBC_ENC_TEST_VECTORS	1
+-#define CAST5_CBC_DEC_TEST_VECTORS	1
+-#define CAST5_CTR_ENC_TEST_VECTORS	2
+-#define CAST5_CTR_DEC_TEST_VECTORS	2
+-
+-static struct cipher_testvec cast5_enc_tv_template[] = {
++static const struct cipher_testvec cast5_enc_tv_template[] = {
+ 	{
+ 		.key	= "\x01\x23\x45\x67\x12\x34\x56\x78"
+ 			  "\x23\x45\x67\x89\x34\x56\x78\x9a",
+@@ -26000,7 +26084,7 @@ static struct cipher_testvec cast5_enc_t
+ 	},
+ };
+ 
+-static struct cipher_testvec cast5_dec_tv_template[] = {
++static const struct cipher_testvec cast5_dec_tv_template[] = {
+ 	{
+ 		.key	= "\x01\x23\x45\x67\x12\x34\x56\x78"
+ 			  "\x23\x45\x67\x89\x34\x56\x78\x9a",
+@@ -26161,7 +26245,7 @@ static struct cipher_testvec cast5_dec_t
+ 	},
+ };
+ 
+-static struct cipher_testvec cast5_cbc_enc_tv_template[] = {
++static const struct cipher_testvec cast5_cbc_enc_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A",
+@@ -26299,7 +26383,7 @@ static struct cipher_testvec cast5_cbc_e
+ 	},
+ };
+ 
+-static struct cipher_testvec cast5_cbc_dec_tv_template[] = {
++static const struct cipher_testvec cast5_cbc_dec_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A",
+@@ -26437,7 +26521,7 @@ static struct cipher_testvec cast5_cbc_d
+ 	},
+ };
+ 
+-static struct cipher_testvec cast5_ctr_enc_tv_template[] = {
++static const struct cipher_testvec cast5_ctr_enc_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A",
+@@ -26588,7 +26672,7 @@ static struct cipher_testvec cast5_ctr_e
+ 	},
+ };
+ 
+-static struct cipher_testvec cast5_ctr_dec_tv_template[] = {
++static const struct cipher_testvec cast5_ctr_dec_tv_template[] = {
+ 	{ /* Generated from TF test vectors */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A",
+@@ -26742,10 +26826,7 @@ static struct cipher_testvec cast5_ctr_d
+ /*
+  * ARC4 test vectors from OpenSSL
+  */
+-#define ARC4_ENC_TEST_VECTORS	7
+-#define ARC4_DEC_TEST_VECTORS	7
+-
+-static struct cipher_testvec arc4_enc_tv_template[] = {
++static const struct cipher_testvec arc4_enc_tv_template[] = {
+ 	{
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef",
+ 		.klen	= 8,
+@@ -26811,7 +26892,7 @@ static struct cipher_testvec arc4_enc_tv
+ 	},
+ };
+ 
+-static struct cipher_testvec arc4_dec_tv_template[] = {
++static const struct cipher_testvec arc4_dec_tv_template[] = {
+ 	{
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef",
+ 		.klen	= 8,
+@@ -26880,10 +26961,7 @@ static struct cipher_testvec arc4_dec_tv
+ /*
+  * TEA test vectors
+  */
+-#define TEA_ENC_TEST_VECTORS	4
+-#define TEA_DEC_TEST_VECTORS	4
+-
+-static struct cipher_testvec tea_enc_tv_template[] = {
++static const struct cipher_testvec tea_enc_tv_template[] = {
+ 	{
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -26926,7 +27004,7 @@ static struct cipher_testvec tea_enc_tv_
+ 	}
+ };
+ 
+-static struct cipher_testvec tea_dec_tv_template[] = {
++static const struct cipher_testvec tea_dec_tv_template[] = {
+ 	{
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -26972,10 +27050,7 @@ static struct cipher_testvec tea_dec_tv_
+ /*
+  * XTEA test vectors
+  */
+-#define XTEA_ENC_TEST_VECTORS	4
+-#define XTEA_DEC_TEST_VECTORS	4
+-
+-static struct cipher_testvec xtea_enc_tv_template[] = {
++static const struct cipher_testvec xtea_enc_tv_template[] = {
+ 	{
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -27018,7 +27093,7 @@ static struct cipher_testvec xtea_enc_tv
+ 	}
+ };
+ 
+-static struct cipher_testvec xtea_dec_tv_template[] = {
++static const struct cipher_testvec xtea_dec_tv_template[] = {
+ 	{
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -27064,10 +27139,7 @@ static struct cipher_testvec xtea_dec_tv
+ /*
+  * KHAZAD test vectors.
+  */
+-#define KHAZAD_ENC_TEST_VECTORS 5
+-#define KHAZAD_DEC_TEST_VECTORS 5
+-
+-static struct cipher_testvec khazad_enc_tv_template[] = {
++static const struct cipher_testvec khazad_enc_tv_template[] = {
+ 	{
+ 		.key	= "\x80\x00\x00\x00\x00\x00\x00\x00"
+ 			  "\x00\x00\x00\x00\x00\x00\x00\x00",
+@@ -27113,7 +27185,7 @@ static struct cipher_testvec khazad_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec khazad_dec_tv_template[] = {
++static const struct cipher_testvec khazad_dec_tv_template[] = {
+ 	{
+ 		.key	= "\x80\x00\x00\x00\x00\x00\x00\x00"
+ 			  "\x00\x00\x00\x00\x00\x00\x00\x00",
+@@ -27163,12 +27235,7 @@ static struct cipher_testvec khazad_dec_
+  * Anubis test vectors.
+  */
+ 
+-#define ANUBIS_ENC_TEST_VECTORS			5
+-#define ANUBIS_DEC_TEST_VECTORS			5
+-#define ANUBIS_CBC_ENC_TEST_VECTORS		2
+-#define ANUBIS_CBC_DEC_TEST_VECTORS		2
+-
+-static struct cipher_testvec anubis_enc_tv_template[] = {
++static const struct cipher_testvec anubis_enc_tv_template[] = {
+ 	{
+ 		.key	= "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ 			  "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
+@@ -27231,7 +27298,7 @@ static struct cipher_testvec anubis_enc_
+ 	},
+ };
+ 
+-static struct cipher_testvec anubis_dec_tv_template[] = {
++static const struct cipher_testvec anubis_dec_tv_template[] = {
+ 	{
+ 		.key	= "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ 			  "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
+@@ -27294,7 +27361,7 @@ static struct cipher_testvec anubis_dec_
+ 	},
+ };
+ 
+-static struct cipher_testvec anubis_cbc_enc_tv_template[] = {
++static const struct cipher_testvec anubis_cbc_enc_tv_template[] = {
+ 	{
+ 		.key	= "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ 			  "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
+@@ -27329,7 +27396,7 @@ static struct cipher_testvec anubis_cbc_
+ 	},
+ };
+ 
+-static struct cipher_testvec anubis_cbc_dec_tv_template[] = {
++static const struct cipher_testvec anubis_cbc_dec_tv_template[] = {
+ 	{
+ 		.key	= "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe"
+ 			  "\xfe\xfe\xfe\xfe\xfe\xfe\xfe\xfe",
+@@ -27367,10 +27434,7 @@ static struct cipher_testvec anubis_cbc_
+ /*
+  * XETA test vectors
+  */
+-#define XETA_ENC_TEST_VECTORS	4
+-#define XETA_DEC_TEST_VECTORS	4
+-
+-static struct cipher_testvec xeta_enc_tv_template[] = {
++static const struct cipher_testvec xeta_enc_tv_template[] = {
+ 	{
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -27413,7 +27477,7 @@ static struct cipher_testvec xeta_enc_tv
+ 	}
+ };
+ 
+-static struct cipher_testvec xeta_dec_tv_template[] = {
++static const struct cipher_testvec xeta_dec_tv_template[] = {
+ 	{
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -27459,10 +27523,7 @@ static struct cipher_testvec xeta_dec_tv
+ /*
+  * FCrypt test vectors
+  */
+-#define FCRYPT_ENC_TEST_VECTORS	ARRAY_SIZE(fcrypt_pcbc_enc_tv_template)
+-#define FCRYPT_DEC_TEST_VECTORS	ARRAY_SIZE(fcrypt_pcbc_dec_tv_template)
+-
+-static struct cipher_testvec fcrypt_pcbc_enc_tv_template[] = {
++static const struct cipher_testvec fcrypt_pcbc_enc_tv_template[] = {
+ 	{ /* http://www.openafs.org/pipermail/openafs-devel/2000-December/005320.html */
+ 		.key	= "\x00\x00\x00\x00\x00\x00\x00\x00",
+ 		.klen	= 8,
+@@ -27523,7 +27584,7 @@ static struct cipher_testvec fcrypt_pcbc
+ 	}
+ };
+ 
+-static struct cipher_testvec fcrypt_pcbc_dec_tv_template[] = {
++static const struct cipher_testvec fcrypt_pcbc_dec_tv_template[] = {
+ 	{ /* http://www.openafs.org/pipermail/openafs-devel/2000-December/005320.html */
+ 		.key	= "\x00\x00\x00\x00\x00\x00\x00\x00",
+ 		.klen	= 8,
+@@ -27587,18 +27648,7 @@ static struct cipher_testvec fcrypt_pcbc
+ /*
+  * CAMELLIA test vectors.
+  */
+-#define CAMELLIA_ENC_TEST_VECTORS 4
+-#define CAMELLIA_DEC_TEST_VECTORS 4
+-#define CAMELLIA_CBC_ENC_TEST_VECTORS 3
+-#define CAMELLIA_CBC_DEC_TEST_VECTORS 3
+-#define CAMELLIA_CTR_ENC_TEST_VECTORS 2
+-#define CAMELLIA_CTR_DEC_TEST_VECTORS 2
+-#define CAMELLIA_LRW_ENC_TEST_VECTORS 8
+-#define CAMELLIA_LRW_DEC_TEST_VECTORS 8
+-#define CAMELLIA_XTS_ENC_TEST_VECTORS 5
+-#define CAMELLIA_XTS_DEC_TEST_VECTORS 5
+-
+-static struct cipher_testvec camellia_enc_tv_template[] = {
++static const struct cipher_testvec camellia_enc_tv_template[] = {
+ 	{
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ 			  "\xfe\xdc\xba\x98\x76\x54\x32\x10",
+@@ -27898,7 +27948,7 @@ static struct cipher_testvec camellia_en
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_dec_tv_template[] = {
++static const struct cipher_testvec camellia_dec_tv_template[] = {
+ 	{
+ 		.key	= "\x01\x23\x45\x67\x89\xab\xcd\xef"
+ 			  "\xfe\xdc\xba\x98\x76\x54\x32\x10",
+@@ -28198,7 +28248,7 @@ static struct cipher_testvec camellia_de
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_cbc_enc_tv_template[] = {
++static const struct cipher_testvec camellia_cbc_enc_tv_template[] = {
+ 	{
+ 		.key    = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
+ 			  "\x51\x2e\x03\xd5\x34\x12\x00\x06",
+@@ -28494,7 +28544,7 @@ static struct cipher_testvec camellia_cb
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_cbc_dec_tv_template[] = {
++static const struct cipher_testvec camellia_cbc_dec_tv_template[] = {
+ 	{
+ 		.key    = "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
+ 			  "\x51\x2e\x03\xd5\x34\x12\x00\x06",
+@@ -28790,7 +28840,7 @@ static struct cipher_testvec camellia_cb
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_ctr_enc_tv_template[] = {
++static const struct cipher_testvec camellia_ctr_enc_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -29457,7 +29507,7 @@ static struct cipher_testvec camellia_ct
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_ctr_dec_tv_template[] = {
++static const struct cipher_testvec camellia_ctr_dec_tv_template[] = {
+ 	{ /* Generated with Crypto++ */
+ 		.key	= "\x85\x62\x3F\x1C\xF9\xD6\x1C\xF9"
+ 			  "\xD6\xB3\x90\x6D\x4A\x90\x6D\x4A"
+@@ -30124,7 +30174,7 @@ static struct cipher_testvec camellia_ct
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_lrw_enc_tv_template[] = {
++static const struct cipher_testvec camellia_lrw_enc_tv_template[] = {
+ 	/* Generated from AES-LRW test vectors */
+ 	{
+ 		.key	= "\x45\x62\xac\x25\xf8\x28\x17\x6d"
+@@ -30376,7 +30426,7 @@ static struct cipher_testvec camellia_lr
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_lrw_dec_tv_template[] = {
++static const struct cipher_testvec camellia_lrw_dec_tv_template[] = {
+ 	/* Generated from AES-LRW test vectors */
+ 	/* same as enc vectors with input and result reversed */
+ 	{
+@@ -30629,7 +30679,7 @@ static struct cipher_testvec camellia_lr
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_xts_enc_tv_template[] = {
++static const struct cipher_testvec camellia_xts_enc_tv_template[] = {
+ 	/* Generated from AES-XTS test vectors */
+ 	{
+ 		.key	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+@@ -30971,7 +31021,7 @@ static struct cipher_testvec camellia_xt
+ 	},
+ };
+ 
+-static struct cipher_testvec camellia_xts_dec_tv_template[] = {
++static const struct cipher_testvec camellia_xts_dec_tv_template[] = {
+ 	/* Generated from AES-XTS test vectors */
+ 	/* same as enc vectors with input and result reversed */
+ 	{
+@@ -31317,10 +31367,7 @@ static struct cipher_testvec camellia_xt
+ /*
+  * SEED test vectors
+  */
+-#define SEED_ENC_TEST_VECTORS	4
+-#define SEED_DEC_TEST_VECTORS	4
+-
+-static struct cipher_testvec seed_enc_tv_template[] = {
++static const struct cipher_testvec seed_enc_tv_template[] = {
+ 	{
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -31362,7 +31409,7 @@ static struct cipher_testvec seed_enc_tv
+ 	}
+ };
+ 
+-static struct cipher_testvec seed_dec_tv_template[] = {
++static const struct cipher_testvec seed_dec_tv_template[] = {
+ 	{
+ 		.key    = zeroed_string,
+ 		.klen	= 16,
+@@ -31404,8 +31451,7 @@ static struct cipher_testvec seed_dec_tv
+ 	}
+ };
+ 
+-#define SALSA20_STREAM_ENC_TEST_VECTORS 5
+-static struct cipher_testvec salsa20_stream_enc_tv_template[] = {
++static const struct cipher_testvec salsa20_stream_enc_tv_template[] = {
+ 	/*
+ 	* Testvectors from verified.test-vectors submitted to ECRYPT.
+ 	* They are truncated to size 39, 64, 111, 129 to test a variety
+@@ -32574,8 +32620,7 @@ static struct cipher_testvec salsa20_str
+ 	},
+ };
+ 
+-#define CHACHA20_ENC_TEST_VECTORS 4
+-static struct cipher_testvec chacha20_enc_tv_template[] = {
++static const struct cipher_testvec chacha20_enc_tv_template[] = {
+ 	{ /* RFC7539 A.2. Test Vector #1 */
+ 		.key	= "\x00\x00\x00\x00\x00\x00\x00\x00"
+ 			  "\x00\x00\x00\x00\x00\x00\x00\x00"
+@@ -33086,9 +33131,7 @@ static struct cipher_testvec chacha20_en
+ /*
+  * CTS (Cipher Text Stealing) mode tests
+  */
+-#define CTS_MODE_ENC_TEST_VECTORS 6
+-#define CTS_MODE_DEC_TEST_VECTORS 6
+-static struct cipher_testvec cts_mode_enc_tv_template[] = {
++static const struct cipher_testvec cts_mode_enc_tv_template[] = {
+ 	{ /* from rfc3962 */
+ 		.klen	= 16,
+ 		.key    = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+@@ -33190,7 +33233,7 @@ static struct cipher_testvec cts_mode_en
+ 	}
+ };
+ 
+-static struct cipher_testvec cts_mode_dec_tv_template[] = {
++static const struct cipher_testvec cts_mode_dec_tv_template[] = {
+ 	{ /* from rfc3962 */
+ 		.klen	= 16,
+ 		.key    = "\x63\x68\x69\x63\x6b\x65\x6e\x20"
+@@ -33308,10 +33351,7 @@ struct comp_testvec {
+  * Params: winbits=-11, Z_DEFAULT_COMPRESSION, MAX_MEM_LEVEL.
+  */
+ 
+-#define DEFLATE_COMP_TEST_VECTORS 2
+-#define DEFLATE_DECOMP_TEST_VECTORS 2
+-
+-static struct comp_testvec deflate_comp_tv_template[] = {
++static const struct comp_testvec deflate_comp_tv_template[] = {
+ 	{
+ 		.inlen	= 70,
+ 		.outlen	= 38,
+@@ -33347,7 +33387,7 @@ static struct comp_testvec deflate_comp_
+ 	},
+ };
+ 
+-static struct comp_testvec deflate_decomp_tv_template[] = {
++static const struct comp_testvec deflate_decomp_tv_template[] = {
+ 	{
+ 		.inlen	= 122,
+ 		.outlen	= 191,
+@@ -33386,10 +33426,7 @@ static struct comp_testvec deflate_decom
+ /*
+  * LZO test vectors (null-terminated strings).
+  */
+-#define LZO_COMP_TEST_VECTORS 2
+-#define LZO_DECOMP_TEST_VECTORS 2
+-
+-static struct comp_testvec lzo_comp_tv_template[] = {
++static const struct comp_testvec lzo_comp_tv_template[] = {
+ 	{
+ 		.inlen	= 70,
+ 		.outlen	= 57,
+@@ -33429,7 +33466,7 @@ static struct comp_testvec lzo_comp_tv_t
+ 	},
+ };
+ 
+-static struct comp_testvec lzo_decomp_tv_template[] = {
++static const struct comp_testvec lzo_decomp_tv_template[] = {
+ 	{
+ 		.inlen	= 133,
+ 		.outlen	= 159,
+@@ -33472,7 +33509,7 @@ static struct comp_testvec lzo_decomp_tv
+  */
+ #define MICHAEL_MIC_TEST_VECTORS 6
+ 
+-static struct hash_testvec michael_mic_tv_template[] = {
++static const struct hash_testvec michael_mic_tv_template[] = {
+ 	{
+ 		.key = "\x00\x00\x00\x00\x00\x00\x00\x00",
+ 		.ksize = 8,
+@@ -33520,9 +33557,7 @@ static struct hash_testvec michael_mic_t
+ /*
+  * CRC32 test vectors
+  */
+-#define CRC32_TEST_VECTORS 14
+-
+-static struct hash_testvec crc32_tv_template[] = {
++static const struct hash_testvec crc32_tv_template[] = {
+ 	{
+ 		.key = "\x87\xa9\xcb\xed",
+ 		.ksize = 4,
+@@ -33954,9 +33989,7 @@ static struct hash_testvec crc32_tv_temp
+ /*
+  * CRC32C test vectors
+  */
+-#define CRC32C_TEST_VECTORS 15
+-
+-static struct hash_testvec crc32c_tv_template[] = {
++static const struct hash_testvec crc32c_tv_template[] = {
+ 	{
+ 		.psize = 0,
+ 		.digest = "\x00\x00\x00\x00",
+@@ -34392,9 +34425,7 @@ static struct hash_testvec crc32c_tv_tem
+ /*
+  * Blakcifn CRC test vectors
+  */
+-#define BFIN_CRC_TEST_VECTORS 6
+-
+-static struct hash_testvec bfin_crc_tv_template[] = {
++static const struct hash_testvec bfin_crc_tv_template[] = {
+ 	{
+ 		.psize = 0,
+ 		.digest = "\x00\x00\x00\x00",
+@@ -34479,9 +34510,6 @@ static struct hash_testvec bfin_crc_tv_t
+ 
+ };
+ 
+-#define LZ4_COMP_TEST_VECTORS 1
+-#define LZ4_DECOMP_TEST_VECTORS 1
+-
+ static struct comp_testvec lz4_comp_tv_template[] = {
+ 	{
+ 		.inlen	= 70,
+@@ -34512,9 +34540,6 @@ static struct comp_testvec lz4_decomp_tv
+ 	},
+ };
+ 
+-#define LZ4HC_COMP_TEST_VECTORS 1
+-#define LZ4HC_DECOMP_TEST_VECTORS 1
+-
+ static struct comp_testvec lz4hc_comp_tv_template[] = {
+ 	{
+ 		.inlen	= 70,
+--- /dev/null
++++ b/crypto/tls.c
+@@ -0,0 +1,607 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; either version 2 of the License, or (at your option)
++ * any later version.
++ *
++ */
++
++#include <crypto/internal/aead.h>
++#include <crypto/internal/hash.h>
++#include <crypto/internal/skcipher.h>
++#include <crypto/authenc.h>
++#include <crypto/null.h>
++#include <crypto/scatterwalk.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/rtnetlink.h>
++
++struct tls_instance_ctx {
++	struct crypto_ahash_spawn auth;
++	struct crypto_skcipher_spawn enc;
++};
++
++struct crypto_tls_ctx {
++	unsigned int reqoff;
++	struct crypto_ahash *auth;
++	struct crypto_skcipher *enc;
++	struct crypto_skcipher *null;
++};
++
++struct tls_request_ctx {
++	/*
++	 * cryptlen holds the payload length in the case of encryption or
++	 * payload_len + icv_len + padding_len in case of decryption
++	 */
++	unsigned int cryptlen;
++	/* working space for partial results */
++	struct scatterlist tmp[2];
++	struct scatterlist cipher[2];
++	struct scatterlist dst[2];
++	char tail[];
++};
++
++struct async_op {
++	struct completion completion;
++	int err;
++};
++
++static void tls_async_op_done(struct crypto_async_request *req, int err)
++{
++	struct async_op *areq = req->data;
++
++	if (err == -EINPROGRESS)
++		return;
++
++	areq->err = err;
++	complete(&areq->completion);
++}
++
++static int crypto_tls_setkey(struct crypto_aead *tls, const u8 *key,
++			     unsigned int keylen)
++{
++	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
++	struct crypto_ahash *auth = ctx->auth;
++	struct crypto_skcipher *enc = ctx->enc;
++	struct crypto_authenc_keys keys;
++	int err = -EINVAL;
++
++	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
++		goto badkey;
++
++	crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK);
++	crypto_ahash_set_flags(auth, crypto_aead_get_flags(tls) &
++				    CRYPTO_TFM_REQ_MASK);
++	err = crypto_ahash_setkey(auth, keys.authkey, keys.authkeylen);
++	crypto_aead_set_flags(tls, crypto_ahash_get_flags(auth) &
++				       CRYPTO_TFM_RES_MASK);
++
++	if (err)
++		goto out;
++
++	crypto_skcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK);
++	crypto_skcipher_set_flags(enc, crypto_aead_get_flags(tls) &
++					 CRYPTO_TFM_REQ_MASK);
++	err = crypto_skcipher_setkey(enc, keys.enckey, keys.enckeylen);
++	crypto_aead_set_flags(tls, crypto_skcipher_get_flags(enc) &
++				       CRYPTO_TFM_RES_MASK);
++
++out:
++	return err;
++
++badkey:
++	crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN);
++	goto out;
++}
++
++/**
++ * crypto_tls_genicv - Calculate hmac digest for a TLS record
++ * @hash:	(output) buffer to save the digest into
++ * @src:	(input) scatterlist with the assoc and payload data
++ * @srclen:	(input) size of the source buffer (assoclen + cryptlen)
++ * @req:	(input) aead request
++ **/
++static int crypto_tls_genicv(u8 *hash, struct scatterlist *src,
++			     unsigned int srclen, struct aead_request *req)
++{
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
++	struct tls_request_ctx *treq_ctx = aead_request_ctx(req);
++	struct async_op ahash_op;
++	struct ahash_request *ahreq = (void *)(treq_ctx->tail + ctx->reqoff);
++	unsigned int flags = CRYPTO_TFM_REQ_MAY_SLEEP;
++	int err = -EBADMSG;
++
++	 /* Bail out if the request assoc len is 0 */
++	if (!req->assoclen)
++		return err;
++
++	init_completion(&ahash_op.completion);
++
++	/* the hash transform to be executed comes from the original request */
++	ahash_request_set_tfm(ahreq, ctx->auth);
++	/* prepare the hash request with input data and result pointer */
++	ahash_request_set_crypt(ahreq, src, hash, srclen);
++	/* set the notifier for when the async hash function returns */
++	ahash_request_set_callback(ahreq, aead_request_flags(req) & flags,
++				   tls_async_op_done, &ahash_op);
++
++	/* Calculate the digest on the given data. The result is put in hash */
++	err = crypto_ahash_digest(ahreq);
++	if (err == -EINPROGRESS) {
++		err = wait_for_completion_interruptible(&ahash_op.completion);
++		if (!err)
++			err = ahash_op.err;
++	}
++
++	return err;
++}
++
++/**
++ * crypto_tls_gen_padicv - Calculate and pad hmac digest for a TLS record
++ * @hash:	(output) buffer to save the digest and padding into
++ * @phashlen:	(output) the size of digest + padding
++ * @req:	(input) aead request
++ **/
++static int crypto_tls_gen_padicv(u8 *hash, unsigned int *phashlen,
++				 struct aead_request *req)
++{
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	unsigned int hash_size = crypto_aead_authsize(tls);
++	unsigned int block_size = crypto_aead_blocksize(tls);
++	unsigned int srclen = req->cryptlen + hash_size;
++	unsigned int icvlen = req->cryptlen + req->assoclen;
++	unsigned int padlen;
++	int err;
++
++	err = crypto_tls_genicv(hash, req->src, icvlen, req);
++	if (err)
++		goto out;
++
++	/* add padding after digest */
++	padlen = block_size - (srclen % block_size);
++	memset(hash + hash_size, padlen - 1, padlen);
++
++	*phashlen = hash_size + padlen;
++out:
++	return err;
++}
++
++static int crypto_tls_copy_data(struct aead_request *req,
++				struct scatterlist *src,
++				struct scatterlist *dst,
++				unsigned int len)
++{
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
++	SKCIPHER_REQUEST_ON_STACK(skreq, ctx->null);
++
++	skcipher_request_set_tfm(skreq, ctx->null);
++	skcipher_request_set_callback(skreq, aead_request_flags(req),
++				      NULL, NULL);
++	skcipher_request_set_crypt(skreq, src, dst, len, NULL);
++
++	return crypto_skcipher_encrypt(skreq);
++}
++
++static int crypto_tls_encrypt(struct aead_request *req)
++{
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
++	struct tls_request_ctx *treq_ctx = aead_request_ctx(req);
++	struct skcipher_request *skreq;
++	struct scatterlist *cipher = treq_ctx->cipher;
++	struct scatterlist *tmp = treq_ctx->tmp;
++	struct scatterlist *sg, *src, *dst;
++	unsigned int cryptlen, phashlen;
++	u8 *hash = treq_ctx->tail;
++	int err;
++
++	/*
++	 * The hash result is saved at the beginning of the tls request ctx
++	 * and is aligned as required by the hash transform. Enough space was
++	 * allocated in crypto_tls_init_tfm to accommodate the difference. The
++	 * requests themselves start later at treq_ctx->tail + ctx->reqoff so
++	 * the result is not overwritten by the second (cipher) request.
++	 */
++	hash = (u8 *)ALIGN((unsigned long)hash +
++			   crypto_ahash_alignmask(ctx->auth),
++			   crypto_ahash_alignmask(ctx->auth) + 1);
++
++	/*
++	 * STEP 1: create ICV together with necessary padding
++	 */
++	err = crypto_tls_gen_padicv(hash, &phashlen, req);
++	if (err)
++		return err;
++
++	/*
++	 * STEP 2: Hash and padding are combined with the payload
++	 * depending on the form it arrives. Scatter tables must have at least
++	 * one page of data before chaining with another table and can't have
++	 * an empty data page. The following code addresses these requirements.
++	 *
++	 * If the payload is empty, only the hash is encrypted, otherwise the
++	 * payload scatterlist is merged with the hash. A special merging case
++	 * is when the payload has only one page of data. In that case the
++	 * payload page is moved to another scatterlist and prepared there for
++	 * encryption.
++	 */
++	if (req->cryptlen) {
++		src = scatterwalk_ffwd(tmp, req->src, req->assoclen);
++
++		sg_init_table(cipher, 2);
++		sg_set_buf(cipher + 1, hash, phashlen);
++
++		if (sg_is_last(src)) {
++			sg_set_page(cipher, sg_page(src), req->cryptlen,
++				    src->offset);
++			src = cipher;
++		} else {
++			unsigned int rem_len = req->cryptlen;
++
++			for (sg = src; rem_len > sg->length; sg = sg_next(sg))
++				rem_len -= min(rem_len, sg->length);
++
++			sg_set_page(cipher, sg_page(sg), rem_len, sg->offset);
++			sg_chain(sg, 1, cipher);
++		}
++	} else {
++		sg_init_one(cipher, hash, phashlen);
++		src = cipher;
++	}
++
++	/**
++	 * If src != dst copy the associated data from source to destination.
++	 * In both cases fast-forward passed the associated data in the dest.
++	 */
++	if (req->src != req->dst) {
++		err = crypto_tls_copy_data(req, req->src, req->dst,
++					   req->assoclen);
++		if (err)
++			return err;
++	}
++	dst = scatterwalk_ffwd(treq_ctx->dst, req->dst, req->assoclen);
++
++	/*
++	 * STEP 3: encrypt the frame and return the result
++	 */
++	cryptlen = req->cryptlen + phashlen;
++
++	/*
++	 * The hash and the cipher are applied at different times and their
++	 * requests can use the same memory space without interference
++	 */
++	skreq = (void *)(treq_ctx->tail + ctx->reqoff);
++	skcipher_request_set_tfm(skreq, ctx->enc);
++	skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv);
++	skcipher_request_set_callback(skreq, aead_request_flags(req),
++				      req->base.complete, req->base.data);
++	/*
++	 * Apply the cipher transform. The result will be in req->dst when the
++	 * asynchronuous call terminates
++	 */
++	err = crypto_skcipher_encrypt(skreq);
++
++	return err;
++}
++
++static int crypto_tls_decrypt(struct aead_request *req)
++{
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tls);
++	struct tls_request_ctx *treq_ctx = aead_request_ctx(req);
++	unsigned int cryptlen = req->cryptlen;
++	unsigned int hash_size = crypto_aead_authsize(tls);
++	unsigned int block_size = crypto_aead_blocksize(tls);
++	struct skcipher_request *skreq = (void *)(treq_ctx->tail + ctx->reqoff);
++	struct scatterlist *tmp = treq_ctx->tmp;
++	struct scatterlist *src, *dst;
++
++	u8 padding[255]; /* padding can be 0-255 bytes */
++	u8 pad_size;
++	u16 *len_field;
++	u8 *ihash, *hash = treq_ctx->tail;
++
++	int paderr = 0;
++	int err = -EINVAL;
++	int i;
++	struct async_op ciph_op;
++
++	/*
++	 * Rule out bad packets. The input packet length must be at least one
++	 * byte more than the hash_size
++	 */
++	if (cryptlen <= hash_size || cryptlen % block_size)
++		goto out;
++
++	/*
++	 * Step 1 - Decrypt the source. Fast-forward past the associated data
++	 * to the encrypted data. The result will be overwritten in place so
++	 * that the decrypted data will be adjacent to the associated data. The
++	 * last step (computing the hash) will have it's input data already
++	 * prepared and ready to be accessed at req->src.
++	 */
++	src = scatterwalk_ffwd(tmp, req->src, req->assoclen);
++	dst = src;
++
++	init_completion(&ciph_op.completion);
++	skcipher_request_set_tfm(skreq, ctx->enc);
++	skcipher_request_set_callback(skreq, aead_request_flags(req),
++				      tls_async_op_done, &ciph_op);
++	skcipher_request_set_crypt(skreq, src, dst, cryptlen, req->iv);
++	err = crypto_skcipher_decrypt(skreq);
++	if (err == -EINPROGRESS) {
++		err = wait_for_completion_interruptible(&ciph_op.completion);
++		if (!err)
++			err = ciph_op.err;
++	}
++	if (err)
++		goto out;
++
++	/*
++	 * Step 2 - Verify padding
++	 * Retrieve the last byte of the payload; this is the padding size.
++	 */
++	cryptlen -= 1;
++	scatterwalk_map_and_copy(&pad_size, dst, cryptlen, 1, 0);
++
++	/* RFC recommendation for invalid padding size. */
++	if (cryptlen < pad_size + hash_size) {
++		pad_size = 0;
++		paderr = -EBADMSG;
++	}
++	cryptlen -= pad_size;
++	scatterwalk_map_and_copy(padding, dst, cryptlen, pad_size, 0);
++
++	/* Padding content must be equal with pad_size. We verify it all */
++	for (i = 0; i < pad_size; i++)
++		if (padding[i] != pad_size)
++			paderr = -EBADMSG;
++
++	/*
++	 * Step 3 - Verify hash
++	 * Align the digest result as required by the hash transform. Enough
++	 * space was allocated in crypto_tls_init_tfm
++	 */
++	hash = (u8 *)ALIGN((unsigned long)hash +
++			   crypto_ahash_alignmask(ctx->auth),
++			   crypto_ahash_alignmask(ctx->auth) + 1);
++	/*
++	 * Two bytes at the end of the associated data make the length field.
++	 * It must be updated with the length of the cleartext message before
++	 * the hash is calculated.
++	 */
++	len_field = sg_virt(req->src) + req->assoclen - 2;
++	cryptlen -= hash_size;
++	*len_field = htons(cryptlen);
++
++	/* This is the hash from the decrypted packet. Save it for later */
++	ihash = hash + hash_size;
++	scatterwalk_map_and_copy(ihash, dst, cryptlen, hash_size, 0);
++
++	/* Now compute and compare our ICV with the one from the packet */
++	err = crypto_tls_genicv(hash, req->src, cryptlen + req->assoclen, req);
++	if (!err)
++		err = memcmp(hash, ihash, hash_size) ? -EBADMSG : 0;
++
++	if (req->src != req->dst) {
++		err = crypto_tls_copy_data(req, req->src, req->dst, cryptlen +
++					   req->assoclen);
++		if (err)
++			goto out;
++	}
++
++	/* return the first found error */
++	if (paderr)
++		err = paderr;
++
++out:
++	aead_request_complete(req, err);
++	return err;
++}
++
++static int crypto_tls_init_tfm(struct crypto_aead *tfm)
++{
++	struct aead_instance *inst = aead_alg_instance(tfm);
++	struct tls_instance_ctx *ictx = aead_instance_ctx(inst);
++	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm);
++	struct crypto_ahash *auth;
++	struct crypto_skcipher *enc;
++	struct crypto_skcipher *null;
++	int err;
++
++	auth = crypto_spawn_ahash(&ictx->auth);
++	if (IS_ERR(auth))
++		return PTR_ERR(auth);
++
++	enc = crypto_spawn_skcipher(&ictx->enc);
++	err = PTR_ERR(enc);
++	if (IS_ERR(enc))
++		goto err_free_ahash;
++
++	null = crypto_get_default_null_skcipher2();
++	err = PTR_ERR(null);
++	if (IS_ERR(null))
++		goto err_free_skcipher;
++
++	ctx->auth = auth;
++	ctx->enc = enc;
++	ctx->null = null;
++
++	/*
++	 * Allow enough space for two digests. The two digests will be compared
++	 * during the decryption phase. One will come from the decrypted packet
++	 * and the other will be calculated. For encryption, one digest is
++	 * padded (up to a cipher blocksize) and chained with the payload
++	 */
++	ctx->reqoff = ALIGN(crypto_ahash_digestsize(auth) +
++			    crypto_ahash_alignmask(auth),
++			    crypto_ahash_alignmask(auth) + 1) +
++			    max(crypto_ahash_digestsize(auth),
++				crypto_skcipher_blocksize(enc));
++
++	crypto_aead_set_reqsize(tfm,
++				sizeof(struct tls_request_ctx) +
++				ctx->reqoff +
++				max_t(unsigned int,
++				      crypto_ahash_reqsize(auth) +
++				      sizeof(struct ahash_request),
++				      crypto_skcipher_reqsize(enc) +
++				      sizeof(struct skcipher_request)));
++
++	return 0;
++
++err_free_skcipher:
++	crypto_free_skcipher(enc);
++err_free_ahash:
++	crypto_free_ahash(auth);
++	return err;
++}
++
++static void crypto_tls_exit_tfm(struct crypto_aead *tfm)
++{
++	struct crypto_tls_ctx *ctx = crypto_aead_ctx(tfm);
++
++	crypto_free_ahash(ctx->auth);
++	crypto_free_skcipher(ctx->enc);
++	crypto_put_default_null_skcipher2();
++}
++
++static void crypto_tls_free(struct aead_instance *inst)
++{
++	struct tls_instance_ctx *ctx = aead_instance_ctx(inst);
++
++	crypto_drop_skcipher(&ctx->enc);
++	crypto_drop_ahash(&ctx->auth);
++	kfree(inst);
++}
++
++static int crypto_tls_create(struct crypto_template *tmpl, struct rtattr **tb)
++{
++	struct crypto_attr_type *algt;
++	struct aead_instance *inst;
++	struct hash_alg_common *auth;
++	struct crypto_alg *auth_base;
++	struct skcipher_alg *enc;
++	struct tls_instance_ctx *ctx;
++	const char *enc_name;
++	int err;
++
++	algt = crypto_get_attr_type(tb);
++	if (IS_ERR(algt))
++		return PTR_ERR(algt);
++
++	if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask)
++		return -EINVAL;
++
++	auth = ahash_attr_alg(tb[1], CRYPTO_ALG_TYPE_HASH,
++			      CRYPTO_ALG_TYPE_AHASH_MASK |
++			      crypto_requires_sync(algt->type, algt->mask));
++	if (IS_ERR(auth))
++		return PTR_ERR(auth);
++
++	auth_base = &auth->base;
++
++	enc_name = crypto_attr_alg_name(tb[2]);
++	err = PTR_ERR(enc_name);
++	if (IS_ERR(enc_name))
++		goto out_put_auth;
++
++	inst = kzalloc(sizeof(*inst) + sizeof(*ctx), GFP_KERNEL);
++	err = -ENOMEM;
++	if (!inst)
++		goto out_put_auth;
++
++	ctx = aead_instance_ctx(inst);
++
++	err = crypto_init_ahash_spawn(&ctx->auth, auth,
++				      aead_crypto_instance(inst));
++	if (err)
++		goto err_free_inst;
++
++	crypto_set_skcipher_spawn(&ctx->enc, aead_crypto_instance(inst));
++	err = crypto_grab_skcipher(&ctx->enc, enc_name, 0,
++				   crypto_requires_sync(algt->type,
++							algt->mask));
++	if (err)
++		goto err_drop_auth;
++
++	enc = crypto_spawn_skcipher_alg(&ctx->enc);
++
++	err = -ENAMETOOLONG;
++	if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME,
++		     "tls10(%s,%s)", auth_base->cra_name,
++		     enc->base.cra_name) >= CRYPTO_MAX_ALG_NAME)
++		goto err_drop_enc;
++
++	if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
++		     "tls10(%s,%s)", auth_base->cra_driver_name,
++		     enc->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME)
++		goto err_drop_enc;
++
++	inst->alg.base.cra_flags = (auth_base->cra_flags |
++					enc->base.cra_flags) & CRYPTO_ALG_ASYNC;
++	inst->alg.base.cra_priority = enc->base.cra_priority * 10 +
++					auth_base->cra_priority;
++	inst->alg.base.cra_blocksize = enc->base.cra_blocksize;
++	inst->alg.base.cra_alignmask = auth_base->cra_alignmask |
++					enc->base.cra_alignmask;
++	inst->alg.base.cra_ctxsize = sizeof(struct crypto_tls_ctx);
++
++	inst->alg.ivsize = crypto_skcipher_alg_ivsize(enc);
++	inst->alg.chunksize = crypto_skcipher_alg_chunksize(enc);
++	inst->alg.maxauthsize = auth->digestsize;
++
++	inst->alg.init = crypto_tls_init_tfm;
++	inst->alg.exit = crypto_tls_exit_tfm;
++
++	inst->alg.setkey = crypto_tls_setkey;
++	inst->alg.encrypt = crypto_tls_encrypt;
++	inst->alg.decrypt = crypto_tls_decrypt;
++
++	inst->free = crypto_tls_free;
++
++	err = aead_register_instance(tmpl, inst);
++	if (err)
++		goto err_drop_enc;
++
++out:
++	crypto_mod_put(auth_base);
++	return err;
++
++err_drop_enc:
++	crypto_drop_skcipher(&ctx->enc);
++err_drop_auth:
++	crypto_drop_ahash(&ctx->auth);
++err_free_inst:
++	kfree(inst);
++out_put_auth:
++	goto out;
++}
++
++static struct crypto_template crypto_tls_tmpl = {
++	.name = "tls10",
++	.create = crypto_tls_create,
++	.module = THIS_MODULE,
++};
++
++static int __init crypto_tls_module_init(void)
++{
++	return crypto_register_template(&crypto_tls_tmpl);
++}
++
++static void __exit crypto_tls_module_exit(void)
++{
++	crypto_unregister_template(&crypto_tls_tmpl);
++}
++
++module_init(crypto_tls_module_init);
++module_exit(crypto_tls_module_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("TLS 1.0 record encryption");
+--- a/drivers/crypto/caam/Kconfig
++++ b/drivers/crypto/caam/Kconfig
+@@ -1,6 +1,11 @@
++config CRYPTO_DEV_FSL_CAAM_COMMON
++	tristate
++
+ config CRYPTO_DEV_FSL_CAAM
+-	tristate "Freescale CAAM-Multicore driver backend"
++	tristate "Freescale CAAM-Multicore platform driver backend"
+ 	depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE
++	select CRYPTO_DEV_FSL_CAAM_COMMON
++	select SOC_BUS
+ 	help
+ 	  Enables the driver module for Freescale's Cryptographic Accelerator
+ 	  and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
+@@ -11,9 +16,16 @@ config CRYPTO_DEV_FSL_CAAM
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called caam.
+ 
++if CRYPTO_DEV_FSL_CAAM
++
++config CRYPTO_DEV_FSL_CAAM_DEBUG
++	bool "Enable debug output in CAAM driver"
++	help
++	  Selecting this will enable printing of various debug
++	  information in the CAAM driver.
++
+ config CRYPTO_DEV_FSL_CAAM_JR
+ 	tristate "Freescale CAAM Job Ring driver backend"
+-	depends on CRYPTO_DEV_FSL_CAAM
+ 	default y
+ 	help
+ 	  Enables the driver module for Job Rings which are part of
+@@ -24,9 +36,10 @@ config CRYPTO_DEV_FSL_CAAM_JR
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called caam_jr.
+ 
++if CRYPTO_DEV_FSL_CAAM_JR
++
+ config CRYPTO_DEV_FSL_CAAM_RINGSIZE
+ 	int "Job Ring size"
+-	depends on CRYPTO_DEV_FSL_CAAM_JR
+ 	range 2 9
+ 	default "9"
+ 	help
+@@ -44,7 +57,6 @@ config CRYPTO_DEV_FSL_CAAM_RINGSIZE
+ 
+ config CRYPTO_DEV_FSL_CAAM_INTC
+ 	bool "Job Ring interrupt coalescing"
+-	depends on CRYPTO_DEV_FSL_CAAM_JR
+ 	help
+ 	  Enable the Job Ring's interrupt coalescing feature.
+ 
+@@ -74,7 +86,6 @@ config CRYPTO_DEV_FSL_CAAM_INTC_TIME_THL
+ 
+ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
+ 	tristate "Register algorithm implementations with the Crypto API"
+-	depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
+ 	default y
+ 	select CRYPTO_AEAD
+ 	select CRYPTO_AUTHENC
+@@ -87,9 +98,25 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
+ 	  To compile this as a module, choose M here: the module
+ 	  will be called caamalg.
+ 
++config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
++	tristate "Queue Interface as Crypto API backend"
++	depends on FSL_SDK_DPA && NET
++	default y
++	select CRYPTO_AUTHENC
++	select CRYPTO_BLKCIPHER
++	help
++	  Selecting this will use CAAM Queue Interface (QI) for sending
++	  & receiving crypto jobs to/from CAAM. This gives better performance
++	  than job ring interface when the number of cores are more than the
++	  number of job rings assigned to the kernel. The number of portals
++	  assigned to the kernel should also be more than the number of
++	  job rings.
++
++	  To compile this as a module, choose M here: the module
++	  will be called caamalg_qi.
++
+ config CRYPTO_DEV_FSL_CAAM_AHASH_API
+ 	tristate "Register hash algorithm implementations with Crypto API"
+-	depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
+ 	default y
+ 	select CRYPTO_HASH
+ 	help
+@@ -101,7 +128,6 @@ config CRYPTO_DEV_FSL_CAAM_AHASH_API
+ 
+ config CRYPTO_DEV_FSL_CAAM_PKC_API
+         tristate "Register public key cryptography implementations with Crypto API"
+-        depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
+         default y
+         select CRYPTO_RSA
+         help
+@@ -113,7 +139,6 @@ config CRYPTO_DEV_FSL_CAAM_PKC_API
+ 
+ config CRYPTO_DEV_FSL_CAAM_RNG_API
+ 	tristate "Register caam device for hwrng API"
+-	depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
+ 	default y
+ 	select CRYPTO_RNG
+ 	select HW_RANDOM
+@@ -124,13 +149,31 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API
+ 	  To compile this as a module, choose M here: the module
+ 	  will be called caamrng.
+ 
+-config CRYPTO_DEV_FSL_CAAM_IMX
+-	def_bool SOC_IMX6 || SOC_IMX7D
+-	depends on CRYPTO_DEV_FSL_CAAM
++endif # CRYPTO_DEV_FSL_CAAM_JR
+ 
+-config CRYPTO_DEV_FSL_CAAM_DEBUG
+-	bool "Enable debug output in CAAM driver"
+-	depends on CRYPTO_DEV_FSL_CAAM
+-	help
+-	  Selecting this will enable printing of various debug
+-	  information in the CAAM driver.
++endif # CRYPTO_DEV_FSL_CAAM
++
++config CRYPTO_DEV_FSL_DPAA2_CAAM
++	tristate "QorIQ DPAA2 CAAM (DPSECI) driver"
++	depends on FSL_MC_DPIO
++	select CRYPTO_DEV_FSL_CAAM_COMMON
++	select CRYPTO_BLKCIPHER
++	select CRYPTO_AUTHENC
++	select CRYPTO_AEAD
++	select CRYPTO_HASH
++	---help---
++	  CAAM driver for QorIQ Data Path Acceleration Architecture 2.
++	  It handles DPSECI DPAA2 objects that sit on the Management Complex
++	  (MC) fsl-mc bus.
++
++	  To compile this as a module, choose M here: the module
++	  will be called dpaa2_caam.
++
++config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC
++	def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \
++		      CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI || \
++		      CRYPTO_DEV_FSL_DPAA2_CAAM)
++
++config CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC
++	def_tristate (CRYPTO_DEV_FSL_CAAM_AHASH_API || \
++		      CRYPTO_DEV_FSL_DPAA2_CAAM)
+--- a/drivers/crypto/caam/Makefile
++++ b/drivers/crypto/caam/Makefile
+@@ -5,13 +5,27 @@ ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG
+ 	ccflags-y := -DDEBUG
+ endif
+ 
++ccflags-y += -DVERSION=\"\"
++
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON) += error.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC) += caamhash_desc.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caam_pkc.o
+ 
+ caam-objs := ctrl.o
+-caam_jr-objs := jr.o key_gen.o error.o
++caam_jr-objs := jr.o key_gen.o
+ caam_pkc-y := caampkc.o pkc_desc.o
++ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),)
++	ccflags-y += -DCONFIG_CAAM_QI
++	caam-objs += qi.o
++endif
++
++obj-$(CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM) += dpaa2_caam.o
++
++dpaa2_caam-y    := caamalg_qi2.o dpseci.o
+--- a/drivers/crypto/caam/caamalg.c
++++ b/drivers/crypto/caam/caamalg.c
+@@ -2,6 +2,7 @@
+  * caam - Freescale FSL CAAM support for crypto API
+  *
+  * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright 2016 NXP
+  *
+  * Based on talitos crypto API driver.
+  *
+@@ -53,6 +54,7 @@
+ #include "error.h"
+ #include "sg_sw_sec4.h"
+ #include "key_gen.h"
++#include "caamalg_desc.h"
+ 
+ /*
+  * crypto alg
+@@ -62,8 +64,6 @@
+ #define CAAM_MAX_KEY_SIZE		(AES_MAX_KEY_SIZE + \
+ 					 CTR_RFC3686_NONCE_SIZE + \
+ 					 SHA512_DIGEST_SIZE * 2)
+-/* max IV is max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
+-#define CAAM_MAX_IV_LENGTH		16
+ 
+ #define AEAD_DESC_JOB_IO_LEN		(DESC_JOB_IO_LEN + CAAM_CMD_SZ * 2)
+ #define GCM_DESC_JOB_IO_LEN		(AEAD_DESC_JOB_IO_LEN + \
+@@ -71,37 +71,6 @@
+ #define AUTHENC_DESC_JOB_IO_LEN		(AEAD_DESC_JOB_IO_LEN + \
+ 					 CAAM_CMD_SZ * 5)
+ 
+-/* length of descriptors text */
+-#define DESC_AEAD_BASE			(4 * CAAM_CMD_SZ)
+-#define DESC_AEAD_ENC_LEN		(DESC_AEAD_BASE + 11 * CAAM_CMD_SZ)
+-#define DESC_AEAD_DEC_LEN		(DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)
+-#define DESC_AEAD_GIVENC_LEN		(DESC_AEAD_ENC_LEN + 9 * CAAM_CMD_SZ)
+-
+-/* Note: Nonce is counted in enckeylen */
+-#define DESC_AEAD_CTR_RFC3686_LEN	(4 * CAAM_CMD_SZ)
+-
+-#define DESC_AEAD_NULL_BASE		(3 * CAAM_CMD_SZ)
+-#define DESC_AEAD_NULL_ENC_LEN		(DESC_AEAD_NULL_BASE + 11 * CAAM_CMD_SZ)
+-#define DESC_AEAD_NULL_DEC_LEN		(DESC_AEAD_NULL_BASE + 13 * CAAM_CMD_SZ)
+-
+-#define DESC_GCM_BASE			(3 * CAAM_CMD_SZ)
+-#define DESC_GCM_ENC_LEN		(DESC_GCM_BASE + 16 * CAAM_CMD_SZ)
+-#define DESC_GCM_DEC_LEN		(DESC_GCM_BASE + 12 * CAAM_CMD_SZ)
+-
+-#define DESC_RFC4106_BASE		(3 * CAAM_CMD_SZ)
+-#define DESC_RFC4106_ENC_LEN		(DESC_RFC4106_BASE + 13 * CAAM_CMD_SZ)
+-#define DESC_RFC4106_DEC_LEN		(DESC_RFC4106_BASE + 13 * CAAM_CMD_SZ)
+-
+-#define DESC_RFC4543_BASE		(3 * CAAM_CMD_SZ)
+-#define DESC_RFC4543_ENC_LEN		(DESC_RFC4543_BASE + 11 * CAAM_CMD_SZ)
+-#define DESC_RFC4543_DEC_LEN		(DESC_RFC4543_BASE + 12 * CAAM_CMD_SZ)
+-
+-#define DESC_ABLKCIPHER_BASE		(3 * CAAM_CMD_SZ)
+-#define DESC_ABLKCIPHER_ENC_LEN		(DESC_ABLKCIPHER_BASE + \
+-					 20 * CAAM_CMD_SZ)
+-#define DESC_ABLKCIPHER_DEC_LEN		(DESC_ABLKCIPHER_BASE + \
+-					 15 * CAAM_CMD_SZ)
+-
+ #define DESC_MAX_USED_BYTES		(CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN)
+ #define DESC_MAX_USED_LEN		(DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
+ 
+@@ -112,47 +81,11 @@
+ #define debug(format, arg...)
+ #endif
+ 
+-#ifdef DEBUG
+-#include <linux/highmem.h>
+-
+-static void dbg_dump_sg(const char *level, const char *prefix_str,
+-			int prefix_type, int rowsize, int groupsize,
+-			struct scatterlist *sg, size_t tlen, bool ascii,
+-			bool may_sleep)
+-{
+-	struct scatterlist *it;
+-	void *it_page;
+-	size_t len;
+-	void *buf;
+-
+-	for (it = sg; it != NULL && tlen > 0 ; it = sg_next(sg)) {
+-		/*
+-		 * make sure the scatterlist's page
+-		 * has a valid virtual memory mapping
+-		 */
+-		it_page = kmap_atomic(sg_page(it));
+-		if (unlikely(!it_page)) {
+-			printk(KERN_ERR "dbg_dump_sg: kmap failed\n");
+-			return;
+-		}
+-
+-		buf = it_page + it->offset;
+-		len = min_t(size_t, tlen, it->length);
+-		print_hex_dump(level, prefix_str, prefix_type, rowsize,
+-			       groupsize, buf, len, ascii);
+-		tlen -= len;
+-
+-		kunmap_atomic(it_page);
+-	}
+-}
+-#endif
+-
+ static struct list_head alg_list;
+ 
+ struct caam_alg_entry {
+ 	int class1_alg_type;
+ 	int class2_alg_type;
+-	int alg_op;
+ 	bool rfc3686;
+ 	bool geniv;
+ };
+@@ -163,302 +96,71 @@ struct caam_aead_alg {
+ 	bool registered;
+ };
+ 
+-/* Set DK bit in class 1 operation if shared */
+-static inline void append_dec_op1(u32 *desc, u32 type)
+-{
+-	u32 *jump_cmd, *uncond_jump_cmd;
+-
+-	/* DK bit is valid only for AES */
+-	if ((type & OP_ALG_ALGSEL_MASK) != OP_ALG_ALGSEL_AES) {
+-		append_operation(desc, type | OP_ALG_AS_INITFINAL |
+-				 OP_ALG_DECRYPT);
+-		return;
+-	}
+-
+-	jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
+-	append_operation(desc, type | OP_ALG_AS_INITFINAL |
+-			 OP_ALG_DECRYPT);
+-	uncond_jump_cmd = append_jump(desc, JUMP_TEST_ALL);
+-	set_jump_tgt_here(desc, jump_cmd);
+-	append_operation(desc, type | OP_ALG_AS_INITFINAL |
+-			 OP_ALG_DECRYPT | OP_ALG_AAI_DK);
+-	set_jump_tgt_here(desc, uncond_jump_cmd);
+-}
+-
+-/*
+- * For aead functions, read payload and write payload,
+- * both of which are specified in req->src and req->dst
+- */
+-static inline void aead_append_src_dst(u32 *desc, u32 msg_type)
+-{
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
+-			     KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH);
+-}
+-
+-/*
+- * For ablkcipher encrypt and decrypt, read from req->src and
+- * write to req->dst
+- */
+-static inline void ablkcipher_append_src_dst(u32 *desc)
+-{
+-	append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 |
+-			     KEY_VLF | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
+-}
+-
+ /*
+  * per-session context
+  */
+ struct caam_ctx {
+-	struct device *jrdev;
+ 	u32 sh_desc_enc[DESC_MAX_USED_LEN];
+ 	u32 sh_desc_dec[DESC_MAX_USED_LEN];
+ 	u32 sh_desc_givenc[DESC_MAX_USED_LEN];
++	u8 key[CAAM_MAX_KEY_SIZE];
+ 	dma_addr_t sh_desc_enc_dma;
+ 	dma_addr_t sh_desc_dec_dma;
+ 	dma_addr_t sh_desc_givenc_dma;
+-	u32 class1_alg_type;
+-	u32 class2_alg_type;
+-	u32 alg_op;
+-	u8 key[CAAM_MAX_KEY_SIZE];
+ 	dma_addr_t key_dma;
+-	unsigned int enckeylen;
+-	unsigned int split_key_len;
+-	unsigned int split_key_pad_len;
++	enum dma_data_direction dir;
++	struct device *jrdev;
++	struct alginfo adata;
++	struct alginfo cdata;
+ 	unsigned int authsize;
+ };
+ 
+-static void append_key_aead(u32 *desc, struct caam_ctx *ctx,
+-			    int keys_fit_inline, bool is_rfc3686)
+-{
+-	u32 *nonce;
+-	unsigned int enckeylen = ctx->enckeylen;
+-
+-	/*
+-	 * RFC3686 specific:
+-	 *	| ctx->key = {AUTH_KEY, ENC_KEY, NONCE}
+-	 *	| enckeylen = encryption key size + nonce size
+-	 */
+-	if (is_rfc3686)
+-		enckeylen -= CTR_RFC3686_NONCE_SIZE;
+-
+-	if (keys_fit_inline) {
+-		append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
+-				  ctx->split_key_len, CLASS_2 |
+-				  KEY_DEST_MDHA_SPLIT | KEY_ENC);
+-		append_key_as_imm(desc, (void *)ctx->key +
+-				  ctx->split_key_pad_len, enckeylen,
+-				  enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-	} else {
+-		append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
+-			   KEY_DEST_MDHA_SPLIT | KEY_ENC);
+-		append_key(desc, ctx->key_dma + ctx->split_key_pad_len,
+-			   enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-	}
+-
+-	/* Load Counter into CONTEXT1 reg */
+-	if (is_rfc3686) {
+-		nonce = (u32 *)((void *)ctx->key + ctx->split_key_pad_len +
+-			       enckeylen);
+-		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
+-				   LDST_CLASS_IND_CCB |
+-				   LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
+-		append_move(desc,
+-			    MOVE_SRC_OUTFIFO |
+-			    MOVE_DEST_CLASS1CTX |
+-			    (16 << MOVE_OFFSET_SHIFT) |
+-			    (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
+-	}
+-}
+-
+-static void init_sh_desc_key_aead(u32 *desc, struct caam_ctx *ctx,
+-				  int keys_fit_inline, bool is_rfc3686)
+-{
+-	u32 *key_jump_cmd;
+-
+-	/* Note: Context registers are saved. */
+-	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
+-
+-	/* Skip if already shared */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-
+-	append_key_aead(desc, ctx, keys_fit_inline, is_rfc3686);
+-
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-}
+-
+ static int aead_null_set_sh_desc(struct crypto_aead *aead)
+ {
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	bool keys_fit_inline = false;
+-	u32 *key_jump_cmd, *jump_cmd, *read_move_cmd, *write_move_cmd;
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
+ 	u32 *desc;
++	int rem_bytes = CAAM_DESC_BYTES_MAX - AEAD_DESC_JOB_IO_LEN -
++			ctx->adata.keylen_pad;
+ 
+ 	/*
+ 	 * Job Descriptor and Shared Descriptors
+ 	 * must all fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	if (DESC_AEAD_NULL_ENC_LEN + AEAD_DESC_JOB_IO_LEN +
+-	    ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
++	if (rem_bytes >= DESC_AEAD_NULL_ENC_LEN) {
++		ctx->adata.key_inline = true;
++		ctx->adata.key_virt = ctx->key;
++	} else {
++		ctx->adata.key_inline = false;
++		ctx->adata.key_dma = ctx->key_dma;
++	}
+ 
+ 	/* aead_encrypt shared descriptor */
+ 	desc = ctx->sh_desc_enc;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* Skip if already shared */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-	if (keys_fit_inline)
+-		append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
+-				  ctx->split_key_len, CLASS_2 |
+-				  KEY_DEST_MDHA_SPLIT | KEY_ENC);
+-	else
+-		append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
+-			   KEY_DEST_MDHA_SPLIT | KEY_ENC);
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* assoclen + cryptlen = seqinlen */
+-	append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Prepare to read and write cryptlen + assoclen bytes */
+-	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+-	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+-	/*
+-	 * MOVE_LEN opcode is not available in all SEC HW revisions,
+-	 * thus need to do some magic, i.e. self-patch the descriptor
+-	 * buffer.
+-	 */
+-	read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF |
+-				    MOVE_DEST_MATH3 |
+-				    (0x6 << MOVE_LEN_SHIFT));
+-	write_move_cmd = append_move(desc, MOVE_SRC_MATH3 |
+-				     MOVE_DEST_DESCBUF |
+-				     MOVE_WAITCOMP |
+-				     (0x8 << MOVE_LEN_SHIFT));
+-
+-	/* Class 2 operation */
+-	append_operation(desc, ctx->class2_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* Read and write cryptlen bytes */
+-	aead_append_src_dst(desc, FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
+-
+-	set_move_tgt_here(desc, read_move_cmd);
+-	set_move_tgt_here(desc, write_move_cmd);
+-	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+-	append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO |
+-		    MOVE_AUX_LS);
+-
+-	/* Write ICV */
+-	append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
+-			 LDST_SRCDST_BYTE_CONTEXT);
+-
+-	ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR,
+-		       "aead null enc shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_aead_null_encap(desc, &ctx->adata, ctx->authsize,
++				    ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	/*
+ 	 * Job Descriptor and Shared Descriptors
+ 	 * must all fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	keys_fit_inline = false;
+-	if (DESC_AEAD_NULL_DEC_LEN + DESC_JOB_IO_LEN +
+-	    ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
+-
+-	desc = ctx->sh_desc_dec;
++	if (rem_bytes >= DESC_AEAD_NULL_DEC_LEN) {
++		ctx->adata.key_inline = true;
++		ctx->adata.key_virt = ctx->key;
++	} else {
++		ctx->adata.key_inline = false;
++		ctx->adata.key_dma = ctx->key_dma;
++	}
+ 
+ 	/* aead_decrypt shared descriptor */
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* Skip if already shared */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-	if (keys_fit_inline)
+-		append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
+-				  ctx->split_key_len, CLASS_2 |
+-				  KEY_DEST_MDHA_SPLIT | KEY_ENC);
+-	else
+-		append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
+-			   KEY_DEST_MDHA_SPLIT | KEY_ENC);
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* Class 2 operation */
+-	append_operation(desc, ctx->class2_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+-
+-	/* assoclen + cryptlen = seqoutlen */
+-	append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Prepare to read and write cryptlen + assoclen bytes */
+-	append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
+-	append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
+-
+-	/*
+-	 * MOVE_LEN opcode is not available in all SEC HW revisions,
+-	 * thus need to do some magic, i.e. self-patch the descriptor
+-	 * buffer.
+-	 */
+-	read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF |
+-				    MOVE_DEST_MATH2 |
+-				    (0x6 << MOVE_LEN_SHIFT));
+-	write_move_cmd = append_move(desc, MOVE_SRC_MATH2 |
+-				     MOVE_DEST_DESCBUF |
+-				     MOVE_WAITCOMP |
+-				     (0x8 << MOVE_LEN_SHIFT));
+-
+-	/* Read and write cryptlen bytes */
+-	aead_append_src_dst(desc, FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
+-
+-	/*
+-	 * Insert a NOP here, since we need at least 4 instructions between
+-	 * code patching the descriptor buffer and the location being patched.
+-	 */
+-	jump_cmd = append_jump(desc, JUMP_TEST_ALL);
+-	set_jump_tgt_here(desc, jump_cmd);
+-
+-	set_move_tgt_here(desc, read_move_cmd);
+-	set_move_tgt_here(desc, write_move_cmd);
+-	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+-	append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO |
+-		    MOVE_AUX_LS);
+-	append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+-	/* Load ICV */
+-	append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 |
+-			     FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
+-
+-	ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR,
+-		       "aead null dec shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	desc = ctx->sh_desc_dec;
++	cnstr_shdsc_aead_null_decap(desc, &ctx->adata, ctx->authsize,
++				    ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	return 0;
+ }
+@@ -470,11 +172,12 @@ static int aead_set_sh_desc(struct crypt
+ 	unsigned int ivsize = crypto_aead_ivsize(aead);
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	bool keys_fit_inline;
+-	u32 geniv, moveiv;
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
+ 	u32 ctx1_iv_off = 0;
+-	u32 *desc;
+-	const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) ==
++	u32 *desc, *nonce = NULL;
++	u32 inl_mask;
++	unsigned int data_len[2];
++	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
+ 			       OP_ALG_AAI_CTR_MOD128);
+ 	const bool is_rfc3686 = alg->caam.rfc3686;
+ 
+@@ -482,7 +185,7 @@ static int aead_set_sh_desc(struct crypt
+ 		return 0;
+ 
+ 	/* NULL encryption / decryption */
+-	if (!ctx->enckeylen)
++	if (!ctx->cdata.keylen)
+ 		return aead_null_set_sh_desc(aead);
+ 
+ 	/*
+@@ -497,8 +200,14 @@ static int aead_set_sh_desc(struct crypt
+ 	 * RFC3686 specific:
+ 	 *	CONTEXT1[255:128] = {NONCE, IV, COUNTER}
+ 	 */
+-	if (is_rfc3686)
++	if (is_rfc3686) {
+ 		ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
++		nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
++				ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
++	}
++
++	data_len[0] = ctx->adata.keylen_pad;
++	data_len[1] = ctx->cdata.keylen;
+ 
+ 	if (alg->caam.geniv)
+ 		goto skip_enc;
+@@ -507,146 +216,64 @@ static int aead_set_sh_desc(struct crypt
+ 	 * Job Descriptor and Shared Descriptors
+ 	 * must all fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	keys_fit_inline = false;
+-	if (DESC_AEAD_ENC_LEN + AUTHENC_DESC_JOB_IO_LEN +
+-	    ctx->split_key_pad_len + ctx->enckeylen +
+-	    (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <=
+-	    CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
+-
+-	/* aead_encrypt shared descriptor */
+-	desc = ctx->sh_desc_enc;
+-
+-	/* Note: Context registers are saved. */
+-	init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686);
+-
+-	/* Class 2 operation */
+-	append_operation(desc, ctx->class2_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* Read and write assoclen bytes */
+-	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+-	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
++	if (desc_inline_query(DESC_AEAD_ENC_LEN +
++			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
++			      AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
++			      ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
+ 
+-	/* Skip assoc data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
+ 
+-	/* read assoc before reading payload */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+-				      FIFOLDST_VLF);
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
+ 
+-	/* Load Counter into CONTEXT1 reg */
+-	if (is_rfc3686)
+-		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
+-				     LDST_SRCDST_BYTE_CONTEXT |
+-				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+-				      LDST_OFFSET_SHIFT));
+-
+-	/* Class 1 operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* Read and write cryptlen bytes */
+-	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-	append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-	aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
+-
+-	/* Write ICV */
+-	append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
+-			 LDST_SRCDST_BYTE_CONTEXT);
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
+ 
+-	ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "aead enc shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	/* aead_encrypt shared descriptor */
++	desc = ctx->sh_desc_enc;
++	cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,
++			       ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,
++			       false, ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ skip_enc:
+ 	/*
+ 	 * Job Descriptor and Shared Descriptors
+ 	 * must all fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	keys_fit_inline = false;
+-	if (DESC_AEAD_DEC_LEN + AUTHENC_DESC_JOB_IO_LEN +
+-	    ctx->split_key_pad_len + ctx->enckeylen +
+-	    (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <=
+-	    CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
+-
+-	/* aead_decrypt shared descriptor */
+-	desc = ctx->sh_desc_dec;
+-
+-	/* Note: Context registers are saved. */
+-	init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686);
+-
+-	/* Class 2 operation */
+-	append_operation(desc, ctx->class2_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
++	if (desc_inline_query(DESC_AEAD_DEC_LEN +
++			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
++			      AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
++			      ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
+ 
+-	/* Read and write assoclen bytes */
+-	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+-	if (alg->caam.geniv)
+-		append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM, ivsize);
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
+ 	else
+-		append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+-	/* Skip assoc data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
+-
+-	/* read assoc before reading payload */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+-			     KEY_VLF);
+-
+-	if (alg->caam.geniv) {
+-		append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
+-				LDST_SRCDST_BYTE_CONTEXT |
+-				(ctx1_iv_off << LDST_OFFSET_SHIFT));
+-		append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO |
+-			    (ctx1_iv_off << MOVE_OFFSET_SHIFT) | ivsize);
+-	}
+-
+-	/* Load Counter into CONTEXT1 reg */
+-	if (is_rfc3686)
+-		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
+-				     LDST_SRCDST_BYTE_CONTEXT |
+-				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+-				      LDST_OFFSET_SHIFT));
++		ctx->adata.key_dma = ctx->key_dma;
+ 
+-	/* Choose operation */
+-	if (ctr_mode)
+-		append_operation(desc, ctx->class1_alg_type |
+-				 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
+ 	else
+-		append_dec_op1(desc, ctx->class1_alg_type);
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
+ 
+-	/* Read and write cryptlen bytes */
+-	append_math_add(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-	append_math_add(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-	aead_append_src_dst(desc, FIFOLD_TYPE_MSG);
+-
+-	/* Load ICV */
+-	append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 |
+-			     FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
+ 
+-	ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "aead dec shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	/* aead_decrypt shared descriptor */
++	desc = ctx->sh_desc_dec;
++	cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
++			       ctx->authsize, alg->caam.geniv, is_rfc3686,
++			       nonce, ctx1_iv_off, false, ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	if (!alg->caam.geniv)
+ 		goto skip_givenc;
+@@ -655,107 +282,32 @@ skip_enc:
+ 	 * Job Descriptor and Shared Descriptors
+ 	 * must all fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	keys_fit_inline = false;
+-	if (DESC_AEAD_GIVENC_LEN + AUTHENC_DESC_JOB_IO_LEN +
+-	    ctx->split_key_pad_len + ctx->enckeylen +
+-	    (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <=
+-	    CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
+-
+-	/* aead_givencrypt shared descriptor */
+-	desc = ctx->sh_desc_enc;
+-
+-	/* Note: Context registers are saved. */
+-	init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686);
++	if (desc_inline_query(DESC_AEAD_GIVENC_LEN +
++			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
++			      AUTHENC_DESC_JOB_IO_LEN, data_len, &inl_mask,
++			      ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
+ 
+-	if (is_rfc3686)
+-		goto copy_iv;
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
+ 
+-	/* Generate IV */
+-	geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
+-		NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
+-		NFIFOENTRY_PTYPE_RND | (ivsize << NFIFOENTRY_DLEN_SHIFT);
+-	append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
+-			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+-	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+-	append_move(desc, MOVE_WAITCOMP |
+-		    MOVE_SRC_INFIFO | MOVE_DEST_CLASS1CTX |
+-		    (ctx1_iv_off << MOVE_OFFSET_SHIFT) |
+-		    (ivsize << MOVE_LEN_SHIFT));
+-	append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+-copy_iv:
+-	/* Copy IV to class 1 context */
+-	append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_OUTFIFO |
+-		    (ctx1_iv_off << MOVE_OFFSET_SHIFT) |
+-		    (ivsize << MOVE_LEN_SHIFT));
+-
+-	/* Return to encryption */
+-	append_operation(desc, ctx->class2_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* Read and write assoclen bytes */
+-	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+-	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+-	/* ivsize + cryptlen = seqoutlen - authsize */
+-	append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
+-
+-	/* Skip assoc data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
+-
+-	/* read assoc before reading payload */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+-			     KEY_VLF);
+-
+-	/* Copy iv from outfifo to class 2 fifo */
+-	moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 |
+-		 NFIFOENTRY_DTYPE_MSG | (ivsize << NFIFOENTRY_DLEN_SHIFT);
+-	append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB |
+-			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+-	append_load_imm_u32(desc, ivsize, LDST_CLASS_2_CCB |
+-			    LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
+ 
+-	/* Load Counter into CONTEXT1 reg */
+-	if (is_rfc3686)
+-		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
+-				     LDST_SRCDST_BYTE_CONTEXT |
+-				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+-				      LDST_OFFSET_SHIFT));
+-
+-	/* Class 1 operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* Will write ivsize + cryptlen */
+-	append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Not need to reload iv */
+-	append_seq_fifo_load(desc, ivsize,
+-			     FIFOLD_CLASS_SKIP);
+-
+-	/* Will read cryptlen */
+-	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | KEY_VLF |
+-			     FIFOLD_TYPE_MSG1OUT2 | FIFOLD_TYPE_LASTBOTH);
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
+-
+-	/* Write ICV */
+-	append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
+-			 LDST_SRCDST_BYTE_CONTEXT);
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
+ 
+-	ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "aead givenc shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	/* aead_givencrypt shared descriptor */
++	desc = ctx->sh_desc_enc;
++	cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
++				  ctx->authsize, is_rfc3686, nonce,
++				  ctx1_iv_off, false, ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ skip_givenc:
+ 	return 0;
+@@ -776,12 +328,12 @@ static int gcm_set_sh_desc(struct crypto
+ {
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	bool keys_fit_inline = false;
+-	u32 *key_jump_cmd, *zero_payload_jump_cmd,
+-	    *zero_assoc_jump_cmd1, *zero_assoc_jump_cmd2;
++	unsigned int ivsize = crypto_aead_ivsize(aead);
+ 	u32 *desc;
++	int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
+ 
+-	if (!ctx->enckeylen || !ctx->authsize)
++	if (!ctx->cdata.keylen || !ctx->authsize)
+ 		return 0;
+ 
+ 	/*
+@@ -789,175 +341,35 @@ static int gcm_set_sh_desc(struct crypto
+ 	 * Job Descriptor and Shared Descriptor
+ 	 * must fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	if (DESC_GCM_ENC_LEN + GCM_DESC_JOB_IO_LEN +
+-	    ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
++	if (rem_bytes >= DESC_GCM_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
+ 
+ 	desc = ctx->sh_desc_enc;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* skip key loading if they are loaded due to sharing */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD | JUMP_COND_SELF);
+-	if (keys_fit_inline)
+-		append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-				  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-	else
+-		append_key(desc, ctx->key_dma, ctx->enckeylen,
+-			   CLASS_1 | KEY_DEST_CLASS_REG);
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* class 1 operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* if assoclen + cryptlen is ZERO, skip to ICV write */
+-	append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-	zero_assoc_jump_cmd2 = append_jump(desc, JUMP_TEST_ALL |
+-						 JUMP_COND_MATH_Z);
+-
+-	/* if assoclen is ZERO, skip reading the assoc data */
+-	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+-	zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL |
+-						 JUMP_COND_MATH_Z);
+-
+-	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+-	/* skip assoc data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
+-
+-	/* cryptlen = seqinlen - assoclen */
+-	append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
+-
+-	/* if cryptlen is ZERO jump to zero-payload commands */
+-	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
+-					    JUMP_COND_MATH_Z);
+-
+-	/* read assoc data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+-	set_jump_tgt_here(desc, zero_assoc_jump_cmd1);
+-
+-	append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* write encrypted data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+-	/* read payload data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
+-
+-	/* jump the zero-payload commands */
+-	append_jump(desc, JUMP_TEST_ALL | 2);
+-
+-	/* zero-payload commands */
+-	set_jump_tgt_here(desc, zero_payload_jump_cmd);
+-
+-	/* read assoc data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST1);
+-
+-	/* There is no input data */
+-	set_jump_tgt_here(desc, zero_assoc_jump_cmd2);
+-
+-	/* write ICV */
+-	append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB |
+-			 LDST_SRCDST_BYTE_CONTEXT);
+-
+-	ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "gcm enc shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ivsize, ctx->authsize, false);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	/*
+ 	 * Job Descriptor and Shared Descriptors
+ 	 * must all fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	keys_fit_inline = false;
+-	if (DESC_GCM_DEC_LEN + GCM_DESC_JOB_IO_LEN +
+-	    ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
++	if (rem_bytes >= DESC_GCM_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
+ 
+ 	desc = ctx->sh_desc_dec;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* skip key loading if they are loaded due to sharing */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL |
+-				   JUMP_TEST_ALL | JUMP_COND_SHRD |
+-				   JUMP_COND_SELF);
+-	if (keys_fit_inline)
+-		append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-				  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-	else
+-		append_key(desc, ctx->key_dma, ctx->enckeylen,
+-			   CLASS_1 | KEY_DEST_CLASS_REG);
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* class 1 operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+-
+-	/* if assoclen is ZERO, skip reading the assoc data */
+-	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+-	zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL |
+-						 JUMP_COND_MATH_Z);
+-
+-	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+-	/* skip assoc data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
+-
+-	/* read assoc data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+-
+-	set_jump_tgt_here(desc, zero_assoc_jump_cmd1);
+-
+-	/* cryptlen = seqoutlen - assoclen */
+-	append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* jump to zero-payload command if cryptlen is zero */
+-	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
+-					    JUMP_COND_MATH_Z);
+-
+-	append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* store encrypted data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+-	/* read payload data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
+-
+-	/* zero-payload command */
+-	set_jump_tgt_here(desc, zero_payload_jump_cmd);
+-
+-	/* read ICV */
+-	append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 |
+-			     FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
+-
+-	ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "gcm dec shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ivsize, ctx->authsize, false);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	return 0;
+ }
+@@ -976,11 +388,12 @@ static int rfc4106_set_sh_desc(struct cr
+ {
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	bool keys_fit_inline = false;
+-	u32 *key_jump_cmd;
++	unsigned int ivsize = crypto_aead_ivsize(aead);
+ 	u32 *desc;
++	int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
+ 
+-	if (!ctx->enckeylen || !ctx->authsize)
++	if (!ctx->cdata.keylen || !ctx->authsize)
+ 		return 0;
+ 
+ 	/*
+@@ -988,148 +401,37 @@ static int rfc4106_set_sh_desc(struct cr
+ 	 * Job Descriptor and Shared Descriptor
+ 	 * must fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	if (DESC_RFC4106_ENC_LEN + GCM_DESC_JOB_IO_LEN +
+-	    ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
++	if (rem_bytes >= DESC_RFC4106_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
+ 
+ 	desc = ctx->sh_desc_enc;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* Skip key loading if it is loaded due to sharing */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-	if (keys_fit_inline)
+-		append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-				  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-	else
+-		append_key(desc, ctx->key_dma, ctx->enckeylen,
+-			   CLASS_1 | KEY_DEST_CLASS_REG);
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* Class 1 operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, 8);
+-	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+-	/* Read assoc data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+-
+-	/* Skip IV */
+-	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_SKIP);
+-
+-	/* Will read cryptlen bytes */
+-	append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Workaround for erratum A-005473 (simultaneous SEQ FIFO skips) */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG);
+-
+-	/* Skip assoc data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
+-
+-	/* cryptlen = seqoutlen - assoclen */
+-	append_math_sub(desc, VARSEQOUTLEN, VARSEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Write encrypted data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+-	/* Read payload data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
+-
+-	/* Write ICV */
+-	append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB |
+-			 LDST_SRCDST_BYTE_CONTEXT);
+-
+-	ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "rfc4106 enc shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
++				  false);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	/*
+ 	 * Job Descriptor and Shared Descriptors
+ 	 * must all fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	keys_fit_inline = false;
+-	if (DESC_RFC4106_DEC_LEN + DESC_JOB_IO_LEN +
+-	    ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
++	if (rem_bytes >= DESC_RFC4106_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
+ 
+ 	desc = ctx->sh_desc_dec;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* Skip key loading if it is loaded due to sharing */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL |
+-				   JUMP_TEST_ALL | JUMP_COND_SHRD);
+-	if (keys_fit_inline)
+-		append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-				  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-	else
+-		append_key(desc, ctx->key_dma, ctx->enckeylen,
+-			   CLASS_1 | KEY_DEST_CLASS_REG);
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* Class 1 operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+-
+-	append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, 8);
+-	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+-
+-	/* Read assoc data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
+-
+-	/* Skip IV */
+-	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_SKIP);
+-
+-	/* Will read cryptlen bytes */
+-	append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG3, CAAM_CMD_SZ);
+-
+-	/* Workaround for erratum A-005473 (simultaneous SEQ FIFO skips) */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG);
+-
+-	/* Skip assoc data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
+-
+-	/* Will write cryptlen bytes */
+-	append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Store payload data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+-	/* Read encrypted data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
+-
+-	/* Read ICV */
+-	append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 |
+-			     FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
+-
+-	ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "rfc4106 dec shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
++				  false);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	return 0;
+ }
+@@ -1149,12 +451,12 @@ static int rfc4543_set_sh_desc(struct cr
+ {
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	bool keys_fit_inline = false;
+-	u32 *key_jump_cmd;
+-	u32 *read_move_cmd, *write_move_cmd;
++	unsigned int ivsize = crypto_aead_ivsize(aead);
+ 	u32 *desc;
++	int rem_bytes = CAAM_DESC_BYTES_MAX - GCM_DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
+ 
+-	if (!ctx->enckeylen || !ctx->authsize)
++	if (!ctx->cdata.keylen || !ctx->authsize)
+ 		return 0;
+ 
+ 	/*
+@@ -1162,151 +464,37 @@ static int rfc4543_set_sh_desc(struct cr
+ 	 * Job Descriptor and Shared Descriptor
+ 	 * must fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	if (DESC_RFC4543_ENC_LEN + GCM_DESC_JOB_IO_LEN +
+-	    ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
++	if (rem_bytes >= DESC_RFC4543_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
+ 
+ 	desc = ctx->sh_desc_enc;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* Skip key loading if it is loaded due to sharing */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-	if (keys_fit_inline)
+-		append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-				  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-	else
+-		append_key(desc, ctx->key_dma, ctx->enckeylen,
+-			   CLASS_1 | KEY_DEST_CLASS_REG);
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* Class 1 operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* assoclen + cryptlen = seqinlen */
+-	append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/*
+-	 * MOVE_LEN opcode is not available in all SEC HW revisions,
+-	 * thus need to do some magic, i.e. self-patch the descriptor
+-	 * buffer.
+-	 */
+-	read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 |
+-				    (0x6 << MOVE_LEN_SHIFT));
+-	write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF |
+-				     (0x8 << MOVE_LEN_SHIFT));
+-
+-	/* Will read assoclen + cryptlen bytes */
+-	append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Will write assoclen + cryptlen bytes */
+-	append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Read and write assoclen + cryptlen bytes */
+-	aead_append_src_dst(desc, FIFOLD_TYPE_AAD);
+-
+-	set_move_tgt_here(desc, read_move_cmd);
+-	set_move_tgt_here(desc, write_move_cmd);
+-	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+-	/* Move payload data to OFIFO */
+-	append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO);
+-
+-	/* Write ICV */
+-	append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB |
+-			 LDST_SRCDST_BYTE_CONTEXT);
+-
+-	ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "rfc4543 enc shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
++				  false);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	/*
+ 	 * Job Descriptor and Shared Descriptors
+ 	 * must all fit into the 64-word Descriptor h/w Buffer
+ 	 */
+-	keys_fit_inline = false;
+-	if (DESC_RFC4543_DEC_LEN + GCM_DESC_JOB_IO_LEN +
+-	    ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
+-		keys_fit_inline = true;
++	if (rem_bytes >= DESC_RFC4543_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
+ 
+ 	desc = ctx->sh_desc_dec;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* Skip key loading if it is loaded due to sharing */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL |
+-				   JUMP_TEST_ALL | JUMP_COND_SHRD);
+-	if (keys_fit_inline)
+-		append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-				  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-	else
+-		append_key(desc, ctx->key_dma, ctx->enckeylen,
+-			   CLASS_1 | KEY_DEST_CLASS_REG);
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* Class 1 operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+-
+-	/* assoclen + cryptlen = seqoutlen */
+-	append_math_sub(desc, REG3, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-
+-	/*
+-	 * MOVE_LEN opcode is not available in all SEC HW revisions,
+-	 * thus need to do some magic, i.e. self-patch the descriptor
+-	 * buffer.
+-	 */
+-	read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 |
+-				    (0x6 << MOVE_LEN_SHIFT));
+-	write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF |
+-				     (0x8 << MOVE_LEN_SHIFT));
+-
+-	/* Will read assoclen + cryptlen bytes */
+-	append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Will write assoclen + cryptlen bytes */
+-	append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Store payload data */
+-	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
+-
+-	/* In-snoop assoclen + cryptlen data */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLDST_VLF |
+-			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST2FLUSH1);
+-
+-	set_move_tgt_here(desc, read_move_cmd);
+-	set_move_tgt_here(desc, write_move_cmd);
+-	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+-	/* Move payload data to OFIFO */
+-	append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO);
+-	append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+-	/* Read ICV */
+-	append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 |
+-			     FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
+-
+-	ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "rfc4543 dec shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
++				  false);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	return 0;
+ }
+@@ -1322,74 +510,67 @@ static int rfc4543_setauthsize(struct cr
+ 	return 0;
+ }
+ 
+-static u32 gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in,
+-			      u32 authkeylen)
+-{
+-	return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
+-			       ctx->split_key_pad_len, key_in, authkeylen,
+-			       ctx->alg_op);
+-}
+-
+ static int aead_setkey(struct crypto_aead *aead,
+ 			       const u8 *key, unsigned int keylen)
+ {
+-	/* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
+-	static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
+ 	struct crypto_authenc_keys keys;
+ 	int ret = 0;
+ 
+ 	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
+ 		goto badkey;
+ 
+-	/* Pick class 2 key length from algorithm submask */
+-	ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
+-				      OP_ALG_ALGSEL_SHIFT] * 2;
+-	ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
+-
+-	if (ctx->split_key_pad_len + keys.enckeylen > CAAM_MAX_KEY_SIZE)
+-		goto badkey;
+-
+ #ifdef DEBUG
+ 	printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n",
+ 	       keys.authkeylen + keys.enckeylen, keys.enckeylen,
+ 	       keys.authkeylen);
+-	printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
+-	       ctx->split_key_len, ctx->split_key_pad_len);
+ 	print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+ #endif
+ 
+-	ret = gen_split_aead_key(ctx, keys.authkey, keys.authkeylen);
++	/*
++	 * If DKP is supported, use it in the shared descriptor to generate
++	 * the split key.
++	 */
++	if (ctrlpriv->era >= 6) {
++		ctx->adata.keylen = keys.authkeylen;
++		ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
++						      OP_ALG_ALGSEL_MASK);
++
++		if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
++			goto badkey;
++
++		memcpy(ctx->key, keys.authkey, keys.authkeylen);
++		memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
++		       keys.enckeylen);
++		dma_sync_single_for_device(jrdev, ctx->key_dma,
++					   ctx->adata.keylen_pad +
++					   keys.enckeylen, ctx->dir);
++		goto skip_split_key;
++	}
++
++	ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, keys.authkey,
++			    keys.authkeylen, CAAM_MAX_KEY_SIZE -
++			    keys.enckeylen);
+ 	if (ret) {
+ 		goto badkey;
+ 	}
+ 
+ 	/* postpend encryption key to auth split key */
+-	memcpy(ctx->key + ctx->split_key_pad_len, keys.enckey, keys.enckeylen);
+-
+-	ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
+-				      keys.enckeylen, DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->key_dma)) {
+-		dev_err(jrdev, "unable to map key i/o memory\n");
+-		return -ENOMEM;
+-	}
++	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
++	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
++				   keys.enckeylen, ctx->dir);
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
+-		       ctx->split_key_pad_len + keys.enckeylen, 1);
++		       ctx->adata.keylen_pad + keys.enckeylen, 1);
+ #endif
+ 
+-	ctx->enckeylen = keys.enckeylen;
+-
+-	ret = aead_set_sh_desc(aead);
+-	if (ret) {
+-		dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len +
+-				 keys.enckeylen, DMA_TO_DEVICE);
+-	}
+-
+-	return ret;
++skip_split_key:
++	ctx->cdata.keylen = keys.enckeylen;
++	return aead_set_sh_desc(aead);
+ badkey:
+ 	crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ 	return -EINVAL;
+@@ -1400,7 +581,6 @@ static int gcm_setkey(struct crypto_aead
+ {
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	int ret = 0;
+ 
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
+@@ -1408,21 +588,10 @@ static int gcm_setkey(struct crypto_aead
+ #endif
+ 
+ 	memcpy(ctx->key, key, keylen);
+-	ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
+-				      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->key_dma)) {
+-		dev_err(jrdev, "unable to map key i/o memory\n");
+-		return -ENOMEM;
+-	}
+-	ctx->enckeylen = keylen;
++	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, ctx->dir);
++	ctx->cdata.keylen = keylen;
+ 
+-	ret = gcm_set_sh_desc(aead);
+-	if (ret) {
+-		dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen,
+-				 DMA_TO_DEVICE);
+-	}
+-
+-	return ret;
++	return gcm_set_sh_desc(aead);
+ }
+ 
+ static int rfc4106_setkey(struct crypto_aead *aead,
+@@ -1430,7 +599,6 @@ static int rfc4106_setkey(struct crypto_
+ {
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	int ret = 0;
+ 
+ 	if (keylen < 4)
+ 		return -EINVAL;
+@@ -1446,22 +614,10 @@ static int rfc4106_setkey(struct crypto_
+ 	 * The last four bytes of the key material are used as the salt value
+ 	 * in the nonce. Update the AES key length.
+ 	 */
+-	ctx->enckeylen = keylen - 4;
+-
+-	ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->enckeylen,
+-				      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->key_dma)) {
+-		dev_err(jrdev, "unable to map key i/o memory\n");
+-		return -ENOMEM;
+-	}
+-
+-	ret = rfc4106_set_sh_desc(aead);
+-	if (ret) {
+-		dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen,
+-				 DMA_TO_DEVICE);
+-	}
+-
+-	return ret;
++	ctx->cdata.keylen = keylen - 4;
++	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
++				   ctx->dir);
++	return rfc4106_set_sh_desc(aead);
+ }
+ 
+ static int rfc4543_setkey(struct crypto_aead *aead,
+@@ -1469,7 +625,6 @@ static int rfc4543_setkey(struct crypto_
+ {
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	int ret = 0;
+ 
+ 	if (keylen < 4)
+ 		return -EINVAL;
+@@ -1485,43 +640,28 @@ static int rfc4543_setkey(struct crypto_
+ 	 * The last four bytes of the key material are used as the salt value
+ 	 * in the nonce. Update the AES key length.
+ 	 */
+-	ctx->enckeylen = keylen - 4;
+-
+-	ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->enckeylen,
+-				      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->key_dma)) {
+-		dev_err(jrdev, "unable to map key i/o memory\n");
+-		return -ENOMEM;
+-	}
+-
+-	ret = rfc4543_set_sh_desc(aead);
+-	if (ret) {
+-		dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen,
+-				 DMA_TO_DEVICE);
+-	}
+-
+-	return ret;
++	ctx->cdata.keylen = keylen - 4;
++	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
++				   ctx->dir);
++	return rfc4543_set_sh_desc(aead);
+ }
+ 
+ static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
+ 			     const u8 *key, unsigned int keylen)
+ {
+ 	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+-	struct ablkcipher_tfm *crt = &ablkcipher->base.crt_ablkcipher;
+ 	struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablkcipher);
+ 	const char *alg_name = crypto_tfm_alg_name(tfm);
+ 	struct device *jrdev = ctx->jrdev;
+-	int ret = 0;
+-	u32 *key_jump_cmd;
++	unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+ 	u32 *desc;
+-	u8 *nonce;
+-	u32 geniv;
+ 	u32 ctx1_iv_off = 0;
+-	const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) ==
++	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
+ 			       OP_ALG_AAI_CTR_MOD128);
+ 	const bool is_rfc3686 = (ctr_mode &&
+ 				 (strstr(alg_name, "rfc3686") != NULL));
+ 
++	memcpy(ctx->key, key, keylen);
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+@@ -1544,215 +684,33 @@ static int ablkcipher_setkey(struct cryp
+ 		keylen -= CTR_RFC3686_NONCE_SIZE;
+ 	}
+ 
+-	memcpy(ctx->key, key, keylen);
+-	ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
+-				      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->key_dma)) {
+-		dev_err(jrdev, "unable to map key i/o memory\n");
+-		return -ENOMEM;
+-	}
+-	ctx->enckeylen = keylen;
++	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE);
++	ctx->cdata.keylen = keylen;
++	ctx->cdata.key_virt = ctx->key;
++	ctx->cdata.key_inline = true;
+ 
+ 	/* ablkcipher_encrypt shared descriptor */
+ 	desc = ctx->sh_desc_enc;
+-	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
+-	/* Skip if already shared */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-
+-	/* Load class1 key only */
+-	append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-			  ctx->enckeylen, CLASS_1 |
+-			  KEY_DEST_CLASS_REG);
+-
+-	/* Load nonce into CONTEXT1 reg */
+-	if (is_rfc3686) {
+-		nonce = (u8 *)key + keylen;
+-		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
+-				   LDST_CLASS_IND_CCB |
+-				   LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
+-		append_move(desc, MOVE_WAITCOMP |
+-			    MOVE_SRC_OUTFIFO |
+-			    MOVE_DEST_CLASS1CTX |
+-			    (16 << MOVE_OFFSET_SHIFT) |
+-			    (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
+-	}
+-
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* Load iv */
+-	append_seq_load(desc, crt->ivsize, LDST_SRCDST_BYTE_CONTEXT |
+-			LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT));
+-
+-	/* Load counter into CONTEXT1 reg */
+-	if (is_rfc3686)
+-		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
+-				     LDST_SRCDST_BYTE_CONTEXT |
+-				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+-				      LDST_OFFSET_SHIFT));
+-
+-	/* Load operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* Perform operation */
+-	ablkcipher_append_src_dst(desc);
++	cnstr_shdsc_ablkcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686,
++				     ctx1_iv_off);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+-	ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR,
+-		       "ablkcipher enc shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
+ 	/* ablkcipher_decrypt shared descriptor */
+ 	desc = ctx->sh_desc_dec;
++	cnstr_shdsc_ablkcipher_decap(desc, &ctx->cdata, ivsize, is_rfc3686,
++				     ctx1_iv_off);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+-	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
+-	/* Skip if already shared */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-
+-	/* Load class1 key only */
+-	append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-			  ctx->enckeylen, CLASS_1 |
+-			  KEY_DEST_CLASS_REG);
+-
+-	/* Load nonce into CONTEXT1 reg */
+-	if (is_rfc3686) {
+-		nonce = (u8 *)key + keylen;
+-		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
+-				   LDST_CLASS_IND_CCB |
+-				   LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
+-		append_move(desc, MOVE_WAITCOMP |
+-			    MOVE_SRC_OUTFIFO |
+-			    MOVE_DEST_CLASS1CTX |
+-			    (16 << MOVE_OFFSET_SHIFT) |
+-			    (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
+-	}
+-
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* load IV */
+-	append_seq_load(desc, crt->ivsize, LDST_SRCDST_BYTE_CONTEXT |
+-			LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT));
+-
+-	/* Load counter into CONTEXT1 reg */
+-	if (is_rfc3686)
+-		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
+-				     LDST_SRCDST_BYTE_CONTEXT |
+-				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+-				      LDST_OFFSET_SHIFT));
+-
+-	/* Choose operation */
+-	if (ctr_mode)
+-		append_operation(desc, ctx->class1_alg_type |
+-				 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
+-	else
+-		append_dec_op1(desc, ctx->class1_alg_type);
+-
+-	/* Perform operation */
+-	ablkcipher_append_src_dst(desc);
+-
+-	ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+-					      desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR,
+-		       "ablkcipher dec shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
+ 	/* ablkcipher_givencrypt shared descriptor */
+ 	desc = ctx->sh_desc_givenc;
++	cnstr_shdsc_ablkcipher_givencap(desc, &ctx->cdata, ivsize, is_rfc3686,
++					ctx1_iv_off);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_givenc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+-	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
+-	/* Skip if already shared */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-
+-	/* Load class1 key only */
+-	append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-			  ctx->enckeylen, CLASS_1 |
+-			  KEY_DEST_CLASS_REG);
+-
+-	/* Load Nonce into CONTEXT1 reg */
+-	if (is_rfc3686) {
+-		nonce = (u8 *)key + keylen;
+-		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
+-				   LDST_CLASS_IND_CCB |
+-				   LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
+-		append_move(desc, MOVE_WAITCOMP |
+-			    MOVE_SRC_OUTFIFO |
+-			    MOVE_DEST_CLASS1CTX |
+-			    (16 << MOVE_OFFSET_SHIFT) |
+-			    (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
+-	}
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/* Generate IV */
+-	geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
+-		NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
+-		NFIFOENTRY_PTYPE_RND | (crt->ivsize << NFIFOENTRY_DLEN_SHIFT);
+-	append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
+-			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+-	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+-	append_move(desc, MOVE_WAITCOMP |
+-		    MOVE_SRC_INFIFO |
+-		    MOVE_DEST_CLASS1CTX |
+-		    (crt->ivsize << MOVE_LEN_SHIFT) |
+-		    (ctx1_iv_off << MOVE_OFFSET_SHIFT));
+-	append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+-
+-	/* Copy generated IV to memory */
+-	append_seq_store(desc, crt->ivsize,
+-			 LDST_SRCDST_BYTE_CONTEXT | LDST_CLASS_1_CCB |
+-			 (ctx1_iv_off << LDST_OFFSET_SHIFT));
+-
+-	/* Load Counter into CONTEXT1 reg */
+-	if (is_rfc3686)
+-		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
+-				     LDST_SRCDST_BYTE_CONTEXT |
+-				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
+-				      LDST_OFFSET_SHIFT));
+-
+-	if (ctx1_iv_off)
+-		append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | JUMP_COND_NCP |
+-			    (1 << JUMP_OFFSET_SHIFT));
+-
+-	/* Load operation */
+-	append_operation(desc, ctx->class1_alg_type |
+-			 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+-
+-	/* Perform operation */
+-	ablkcipher_append_src_dst(desc);
+-
+-	ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
+-						 desc_bytes(desc),
+-						 DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR,
+-		       "ablkcipher givenc shdesc@" __stringify(__LINE__) ": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
+-
+-	return ret;
++	return 0;
+ }
+ 
+ static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
+@@ -1760,8 +718,7 @@ static int xts_ablkcipher_setkey(struct
+ {
+ 	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+ 	struct device *jrdev = ctx->jrdev;
+-	u32 *key_jump_cmd, *desc;
+-	__be64 sector_size = cpu_to_be64(512);
++	u32 *desc;
+ 
+ 	if (keylen != 2 * AES_MIN_KEY_SIZE  && keylen != 2 * AES_MAX_KEY_SIZE) {
+ 		crypto_ablkcipher_set_flags(ablkcipher,
+@@ -1771,126 +728,38 @@ static int xts_ablkcipher_setkey(struct
+ 	}
+ 
+ 	memcpy(ctx->key, key, keylen);
+-	ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen, DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->key_dma)) {
+-		dev_err(jrdev, "unable to map key i/o memory\n");
+-		return -ENOMEM;
+-	}
+-	ctx->enckeylen = keylen;
++	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE);
++	ctx->cdata.keylen = keylen;
++	ctx->cdata.key_virt = ctx->key;
++	ctx->cdata.key_inline = true;
+ 
+ 	/* xts_ablkcipher_encrypt shared descriptor */
+ 	desc = ctx->sh_desc_enc;
+-	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
+-	/* Skip if already shared */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-
+-	/* Load class1 keys only */
+-	append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-			  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-
+-	/* Load sector size with index 40 bytes (0x28) */
+-	append_cmd(desc, CMD_LOAD | IMMEDIATE | LDST_SRCDST_BYTE_CONTEXT |
+-		   LDST_CLASS_1_CCB | (0x28 << LDST_OFFSET_SHIFT) | 8);
+-	append_data(desc, (void *)&sector_size, 8);
+-
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/*
+-	 * create sequence for loading the sector index
+-	 * Upper 8B of IV - will be used as sector index
+-	 * Lower 8B of IV - will be discarded
+-	 */
+-	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+-		   LDST_CLASS_1_CCB | (0x20 << LDST_OFFSET_SHIFT) | 8);
+-	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_SKIP);
+-
+-	/* Load operation */
+-	append_operation(desc, ctx->class1_alg_type | OP_ALG_AS_INITFINAL |
+-			 OP_ALG_ENCRYPT);
+-
+-	/* Perform operation */
+-	ablkcipher_append_src_dst(desc);
+-
+-	ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR,
+-		       "xts ablkcipher enc shdesc@" __stringify(__LINE__) ": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_xts_ablkcipher_encap(desc, &ctx->cdata);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	/* xts_ablkcipher_decrypt shared descriptor */
+ 	desc = ctx->sh_desc_dec;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
+-	/* Skip if already shared */
+-	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-				   JUMP_COND_SHRD);
+-
+-	/* Load class1 key only */
+-	append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+-			  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+-
+-	/* Load sector size with index 40 bytes (0x28) */
+-	append_cmd(desc, CMD_LOAD | IMMEDIATE | LDST_SRCDST_BYTE_CONTEXT |
+-		   LDST_CLASS_1_CCB | (0x28 << LDST_OFFSET_SHIFT) | 8);
+-	append_data(desc, (void *)&sector_size, 8);
+-
+-	set_jump_tgt_here(desc, key_jump_cmd);
+-
+-	/*
+-	 * create sequence for loading the sector index
+-	 * Upper 8B of IV - will be used as sector index
+-	 * Lower 8B of IV - will be discarded
+-	 */
+-	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+-		   LDST_CLASS_1_CCB | (0x20 << LDST_OFFSET_SHIFT) | 8);
+-	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_SKIP);
+-
+-	/* Load operation */
+-	append_dec_op1(desc, ctx->class1_alg_type);
+-
+-	/* Perform operation */
+-	ablkcipher_append_src_dst(desc);
+-
+-	ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+-		dma_unmap_single(jrdev, ctx->sh_desc_enc_dma,
+-				 desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE);
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR,
+-		       "xts ablkcipher dec shdesc@" __stringify(__LINE__) ": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+-#endif
++	cnstr_shdsc_xts_ablkcipher_decap(desc, &ctx->cdata);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++				   desc_bytes(desc), ctx->dir);
+ 
+ 	return 0;
+ }
+ 
+ /*
+  * aead_edesc - s/w-extended aead descriptor
+- * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist
+- * @src_nents: number of segments in input scatterlist
+- * @dst_nents: number of segments in output scatterlist
+- * @iv_dma: dma address of iv for checking continuity and link table
+- * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
++ * @src_nents: number of segments in input s/w scatterlist
++ * @dst_nents: number of segments in output s/w scatterlist
+  * @sec4_sg_bytes: length of dma mapped sec4_sg space
+  * @sec4_sg_dma: bus physical mapped address of h/w link table
++ * @sec4_sg: pointer to h/w link table
+  * @hw_desc: the h/w job descriptor followed by any referenced link tables
+  */
+ struct aead_edesc {
+-	int assoc_nents;
+ 	int src_nents;
+ 	int dst_nents;
+-	dma_addr_t iv_dma;
+ 	int sec4_sg_bytes;
+ 	dma_addr_t sec4_sg_dma;
+ 	struct sec4_sg_entry *sec4_sg;
+@@ -1899,12 +768,12 @@ struct aead_edesc {
+ 
+ /*
+  * ablkcipher_edesc - s/w-extended ablkcipher descriptor
+- * @src_nents: number of segments in input scatterlist
+- * @dst_nents: number of segments in output scatterlist
++ * @src_nents: number of segments in input s/w scatterlist
++ * @dst_nents: number of segments in output s/w scatterlist
+  * @iv_dma: dma address of iv for checking continuity and link table
+- * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
+  * @sec4_sg_bytes: length of dma mapped sec4_sg space
+  * @sec4_sg_dma: bus physical mapped address of h/w link table
++ * @sec4_sg: pointer to h/w link table
+  * @hw_desc: the h/w job descriptor followed by any referenced link tables
+  */
+ struct ablkcipher_edesc {
+@@ -1924,10 +793,11 @@ static void caam_unmap(struct device *de
+ 		       int sec4_sg_bytes)
+ {
+ 	if (dst != src) {
+-		dma_unmap_sg(dev, src, src_nents ? : 1, DMA_TO_DEVICE);
+-		dma_unmap_sg(dev, dst, dst_nents ? : 1, DMA_FROM_DEVICE);
++		if (src_nents)
++			dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
++		dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
+ 	} else {
+-		dma_unmap_sg(dev, src, src_nents ? : 1, DMA_BIDIRECTIONAL);
++		dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
+ 	}
+ 
+ 	if (iv_dma)
+@@ -2021,8 +891,7 @@ static void ablkcipher_encrypt_done(stru
+ 	dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+ #endif
+ 
+-	edesc = (struct ablkcipher_edesc *)((char *)desc -
+-		 offsetof(struct ablkcipher_edesc, hw_desc));
++	edesc = container_of(desc, struct ablkcipher_edesc, hw_desc[0]);
+ 
+ 	if (err)
+ 		caam_jr_strstatus(jrdev, err);
+@@ -2031,10 +900,10 @@ static void ablkcipher_encrypt_done(stru
+ 	print_hex_dump(KERN_ERR, "dstiv  @"__stringify(__LINE__)": ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+ 		       edesc->src_nents > 1 ? 100 : ivsize, 1);
+-	dbg_dump_sg(KERN_ERR, "dst    @"__stringify(__LINE__)": ",
+-		    DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
+-		    edesc->dst_nents > 1 ? 100 : req->nbytes, 1, true);
+ #endif
++	caam_dump_sg(KERN_ERR, "dst    @" __stringify(__LINE__)": ",
++		     DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
++		     edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
+ 
+ 	ablkcipher_unmap(jrdev, edesc, req);
+ 
+@@ -2062,8 +931,7 @@ static void ablkcipher_decrypt_done(stru
+ 	dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+ #endif
+ 
+-	edesc = (struct ablkcipher_edesc *)((char *)desc -
+-		 offsetof(struct ablkcipher_edesc, hw_desc));
++	edesc = container_of(desc, struct ablkcipher_edesc, hw_desc[0]);
+ 	if (err)
+ 		caam_jr_strstatus(jrdev, err);
+ 
+@@ -2071,10 +939,10 @@ static void ablkcipher_decrypt_done(stru
+ 	print_hex_dump(KERN_ERR, "dstiv  @"__stringify(__LINE__)": ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+ 		       ivsize, 1);
+-	dbg_dump_sg(KERN_ERR, "dst    @"__stringify(__LINE__)": ",
+-		    DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
+-		    edesc->dst_nents > 1 ? 100 : req->nbytes, 1, true);
+ #endif
++	caam_dump_sg(KERN_ERR, "dst    @" __stringify(__LINE__)": ",
++		     DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
++		     edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
+ 
+ 	ablkcipher_unmap(jrdev, edesc, req);
+ 
+@@ -2114,7 +982,7 @@ static void init_aead_job(struct aead_re
+ 	init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
+ 
+ 	if (all_contig) {
+-		src_dma = sg_dma_address(req->src);
++		src_dma = edesc->src_nents ? sg_dma_address(req->src) : 0;
+ 		in_options = 0;
+ 	} else {
+ 		src_dma = edesc->sec4_sg_dma;
+@@ -2129,7 +997,7 @@ static void init_aead_job(struct aead_re
+ 	out_options = in_options;
+ 
+ 	if (unlikely(req->src != req->dst)) {
+-		if (!edesc->dst_nents) {
++		if (edesc->dst_nents == 1) {
+ 			dst_dma = sg_dma_address(req->dst);
+ 		} else {
+ 			dst_dma = edesc->sec4_sg_dma +
+@@ -2147,9 +1015,6 @@ static void init_aead_job(struct aead_re
+ 		append_seq_out_ptr(desc, dst_dma,
+ 				   req->assoclen + req->cryptlen - authsize,
+ 				   out_options);
+-
+-	/* REG3 = assoclen */
+-	append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
+ }
+ 
+ static void init_gcm_job(struct aead_request *req,
+@@ -2164,6 +1029,7 @@ static void init_gcm_job(struct aead_req
+ 	unsigned int last;
+ 
+ 	init_aead_job(req, edesc, all_contig, encrypt);
++	append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
+ 
+ 	/* BUG This should not be specific to generic GCM. */
+ 	last = 0;
+@@ -2175,7 +1041,7 @@ static void init_gcm_job(struct aead_req
+ 			 FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | 12 | last);
+ 	/* Append Salt */
+ 	if (!generic_gcm)
+-		append_data(desc, ctx->key + ctx->enckeylen, 4);
++		append_data(desc, ctx->key + ctx->cdata.keylen, 4);
+ 	/* Append IV */
+ 	append_data(desc, req->iv, ivsize);
+ 	/* End of blank commands */
+@@ -2190,7 +1056,8 @@ static void init_authenc_job(struct aead
+ 						 struct caam_aead_alg, aead);
+ 	unsigned int ivsize = crypto_aead_ivsize(aead);
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+-	const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) ==
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
++	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
+ 			       OP_ALG_AAI_CTR_MOD128);
+ 	const bool is_rfc3686 = alg->caam.rfc3686;
+ 	u32 *desc = edesc->hw_desc;
+@@ -2213,6 +1080,15 @@ static void init_authenc_job(struct aead
+ 
+ 	init_aead_job(req, edesc, all_contig, encrypt);
+ 
++	/*
++	 * {REG3, DPOVRD} = assoclen, depending on whether MATH command supports
++	 * having DPOVRD as destination.
++	 */
++	if (ctrlpriv->era < 3)
++		append_math_add_imm_u32(desc, REG3, ZERO, IMM, req->assoclen);
++	else
++		append_math_add_imm_u32(desc, DPOVRD, ZERO, IMM, req->assoclen);
++
+ 	if (ivsize && ((is_rfc3686 && encrypt) || !alg->caam.geniv))
+ 		append_load_as_imm(desc, req->iv, ivsize,
+ 				   LDST_CLASS_1_CCB |
+@@ -2236,16 +1112,15 @@ static void init_ablkcipher_job(u32 *sh_
+ 	int len, sec4_sg_index = 0;
+ 
+ #ifdef DEBUG
+-	bool may_sleep = ((req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-					      CRYPTO_TFM_REQ_MAY_SLEEP)) != 0);
+ 	print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+ 		       ivsize, 1);
+-	printk(KERN_ERR "asked=%d, nbytes%d\n", (int)edesc->src_nents ? 100 : req->nbytes, req->nbytes);
+-	dbg_dump_sg(KERN_ERR, "src    @"__stringify(__LINE__)": ",
+-		    DUMP_PREFIX_ADDRESS, 16, 4, req->src,
+-		    edesc->src_nents ? 100 : req->nbytes, 1, may_sleep);
++	pr_err("asked=%d, nbytes%d\n",
++	       (int)edesc->src_nents > 1 ? 100 : req->nbytes, req->nbytes);
+ #endif
++	caam_dump_sg(KERN_ERR, "src    @" __stringify(__LINE__)": ",
++		     DUMP_PREFIX_ADDRESS, 16, 4, req->src,
++		     edesc->src_nents > 1 ? 100 : req->nbytes, 1);
+ 
+ 	len = desc_len(sh_desc);
+ 	init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
+@@ -2261,7 +1136,7 @@ static void init_ablkcipher_job(u32 *sh_
+ 	append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options);
+ 
+ 	if (likely(req->src == req->dst)) {
+-		if (!edesc->src_nents && iv_contig) {
++		if (edesc->src_nents == 1 && iv_contig) {
+ 			dst_dma = sg_dma_address(req->src);
+ 		} else {
+ 			dst_dma = edesc->sec4_sg_dma +
+@@ -2269,7 +1144,7 @@ static void init_ablkcipher_job(u32 *sh_
+ 			out_options = LDST_SGF;
+ 		}
+ 	} else {
+-		if (!edesc->dst_nents) {
++		if (edesc->dst_nents == 1) {
+ 			dst_dma = sg_dma_address(req->dst);
+ 		} else {
+ 			dst_dma = edesc->sec4_sg_dma +
+@@ -2296,20 +1171,18 @@ static void init_ablkcipher_giv_job(u32
+ 	int len, sec4_sg_index = 0;
+ 
+ #ifdef DEBUG
+-	bool may_sleep = ((req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-					      CRYPTO_TFM_REQ_MAY_SLEEP)) != 0);
+ 	print_hex_dump(KERN_ERR, "presciv@" __stringify(__LINE__) ": ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+ 		       ivsize, 1);
+-	dbg_dump_sg(KERN_ERR, "src    @" __stringify(__LINE__) ": ",
+-		    DUMP_PREFIX_ADDRESS, 16, 4, req->src,
+-		    edesc->src_nents ? 100 : req->nbytes, 1, may_sleep);
+ #endif
++	caam_dump_sg(KERN_ERR, "src    @" __stringify(__LINE__) ": ",
++		     DUMP_PREFIX_ADDRESS, 16, 4, req->src,
++		     edesc->src_nents > 1 ? 100 : req->nbytes, 1);
+ 
+ 	len = desc_len(sh_desc);
+ 	init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
+ 
+-	if (!edesc->src_nents) {
++	if (edesc->src_nents == 1) {
+ 		src_dma = sg_dma_address(req->src);
+ 		in_options = 0;
+ 	} else {
+@@ -2340,87 +1213,100 @@ static struct aead_edesc *aead_edesc_all
+ 	struct crypto_aead *aead = crypto_aead_reqtfm(req);
+ 	struct caam_ctx *ctx = crypto_aead_ctx(aead);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+-	int src_nents, dst_nents = 0;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
+ 	struct aead_edesc *edesc;
+-	int sgc;
+-	bool all_contig = true;
+-	int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
++	int sec4_sg_index, sec4_sg_len, sec4_sg_bytes;
+ 	unsigned int authsize = ctx->authsize;
+ 
+ 	if (unlikely(req->dst != req->src)) {
+-		src_nents = sg_count(req->src, req->assoclen + req->cryptlen);
+-		dst_nents = sg_count(req->dst,
+-				     req->assoclen + req->cryptlen +
+-					(encrypt ? authsize : (-authsize)));
+-	} else {
+-		src_nents = sg_count(req->src,
+-				     req->assoclen + req->cryptlen +
+-					(encrypt ? authsize : 0));
+-	}
+-
+-	/* Check if data are contiguous. */
+-	all_contig = !src_nents;
+-	if (!all_contig) {
+-		src_nents = src_nents ? : 1;
+-		sec4_sg_len = src_nents;
+-	}
+-
+-	sec4_sg_len += dst_nents;
+-
+-	sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen);
++		if (unlikely(src_nents < 0)) {
++			dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen);
++			return ERR_PTR(src_nents);
++		}
+ 
+-	/* allocate space for base edesc and hw desc commands, link tables */
+-	edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+-			GFP_DMA | flags);
+-	if (!edesc) {
+-		dev_err(jrdev, "could not allocate extended descriptor\n");
+-		return ERR_PTR(-ENOMEM);
++		dst_nents = sg_nents_for_len(req->dst, req->assoclen +
++					     req->cryptlen +
++						(encrypt ? authsize :
++							   (-authsize)));
++		if (unlikely(dst_nents < 0)) {
++			dev_err(jrdev, "Insufficient bytes (%d) in dst S/G\n",
++				req->assoclen + req->cryptlen +
++				(encrypt ? authsize : (-authsize)));
++			return ERR_PTR(dst_nents);
++		}
++	} else {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen +
++					     (encrypt ? authsize : 0));
++		if (unlikely(src_nents < 0)) {
++			dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen +
++				(encrypt ? authsize : 0));
++			return ERR_PTR(src_nents);
++		}
+ 	}
+ 
+ 	if (likely(req->src == req->dst)) {
+-		sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+-				 DMA_BIDIRECTIONAL);
+-		if (unlikely(!sgc)) {
++		mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
+ 			dev_err(jrdev, "unable to map source\n");
+-			kfree(edesc);
+ 			return ERR_PTR(-ENOMEM);
+ 		}
+ 	} else {
+-		sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+-				 DMA_TO_DEVICE);
+-		if (unlikely(!sgc)) {
+-			dev_err(jrdev, "unable to map source\n");
+-			kfree(edesc);
+-			return ERR_PTR(-ENOMEM);
++		/* Cover also the case of null (zero length) input data */
++		if (src_nents) {
++			mapped_src_nents = dma_map_sg(jrdev, req->src,
++						      src_nents, DMA_TO_DEVICE);
++			if (unlikely(!mapped_src_nents)) {
++				dev_err(jrdev, "unable to map source\n");
++				return ERR_PTR(-ENOMEM);
++			}
++		} else {
++			mapped_src_nents = 0;
+ 		}
+ 
+-		sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
+-				 DMA_FROM_DEVICE);
+-		if (unlikely(!sgc)) {
++		mapped_dst_nents = dma_map_sg(jrdev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
+ 			dev_err(jrdev, "unable to map destination\n");
+-			dma_unmap_sg(jrdev, req->src, src_nents ? : 1,
+-				     DMA_TO_DEVICE);
+-			kfree(edesc);
++			dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
+ 			return ERR_PTR(-ENOMEM);
+ 		}
+ 	}
+ 
++	sec4_sg_len = mapped_src_nents > 1 ? mapped_src_nents : 0;
++	sec4_sg_len += mapped_dst_nents > 1 ? mapped_dst_nents : 0;
++	sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
++
++	/* allocate space for base edesc and hw desc commands, link tables */
++	edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
++			GFP_DMA | flags);
++	if (!edesc) {
++		caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
++			   0, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
+ 	edesc->src_nents = src_nents;
+ 	edesc->dst_nents = dst_nents;
+ 	edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
+ 			 desc_bytes;
+-	*all_contig_ptr = all_contig;
++	*all_contig_ptr = !(mapped_src_nents > 1);
+ 
+ 	sec4_sg_index = 0;
+-	if (!all_contig) {
+-		sg_to_sec4_sg_last(req->src, src_nents,
+-			      edesc->sec4_sg + sec4_sg_index, 0);
+-		sec4_sg_index += src_nents;
++	if (mapped_src_nents > 1) {
++		sg_to_sec4_sg_last(req->src, mapped_src_nents,
++				   edesc->sec4_sg + sec4_sg_index, 0);
++		sec4_sg_index += mapped_src_nents;
+ 	}
+-	if (dst_nents) {
+-		sg_to_sec4_sg_last(req->dst, dst_nents,
++	if (mapped_dst_nents > 1) {
++		sg_to_sec4_sg_last(req->dst, mapped_dst_nents,
+ 				   edesc->sec4_sg + sec4_sg_index, 0);
+ 	}
+ 
+@@ -2573,13 +1459,9 @@ static int aead_decrypt(struct aead_requ
+ 	u32 *desc;
+ 	int ret = 0;
+ 
+-#ifdef DEBUG
+-	bool may_sleep = ((req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-					      CRYPTO_TFM_REQ_MAY_SLEEP)) != 0);
+-	dbg_dump_sg(KERN_ERR, "dec src@"__stringify(__LINE__)": ",
+-		    DUMP_PREFIX_ADDRESS, 16, 4, req->src,
+-		    req->assoclen + req->cryptlen, 1, may_sleep);
+-#endif
++	caam_dump_sg(KERN_ERR, "dec src@" __stringify(__LINE__)": ",
++		     DUMP_PREFIX_ADDRESS, 16, 4, req->src,
++		     req->assoclen + req->cryptlen, 1);
+ 
+ 	/* allocate extended descriptor */
+ 	edesc = aead_edesc_alloc(req, AUTHENC_DESC_JOB_IO_LEN,
+@@ -2619,51 +1501,80 @@ static struct ablkcipher_edesc *ablkciph
+ 	struct device *jrdev = ctx->jrdev;
+ 	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
+ 		       GFP_KERNEL : GFP_ATOMIC;
+-	int src_nents, dst_nents = 0, sec4_sg_bytes;
++	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
+ 	struct ablkcipher_edesc *edesc;
+ 	dma_addr_t iv_dma = 0;
+-	bool iv_contig = false;
+-	int sgc;
++	bool in_contig;
+ 	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+-	int sec4_sg_index;
++	int dst_sg_idx, sec4_sg_ents, sec4_sg_bytes;
+ 
+-	src_nents = sg_count(req->src, req->nbytes);
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (unlikely(src_nents < 0)) {
++		dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
++			req->nbytes);
++		return ERR_PTR(src_nents);
++	}
+ 
+-	if (req->dst != req->src)
+-		dst_nents = sg_count(req->dst, req->nbytes);
++	if (req->dst != req->src) {
++		dst_nents = sg_nents_for_len(req->dst, req->nbytes);
++		if (unlikely(dst_nents < 0)) {
++			dev_err(jrdev, "Insufficient bytes (%d) in dst S/G\n",
++				req->nbytes);
++			return ERR_PTR(dst_nents);
++		}
++	}
+ 
+ 	if (likely(req->src == req->dst)) {
+-		sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+-				 DMA_BIDIRECTIONAL);
++		mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(jrdev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
+ 	} else {
+-		sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+-				 DMA_TO_DEVICE);
+-		sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
+-				 DMA_FROM_DEVICE);
++		mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
++					      DMA_TO_DEVICE);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(jrdev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		mapped_dst_nents = dma_map_sg(jrdev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(jrdev, "unable to map destination\n");
++			dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
++			return ERR_PTR(-ENOMEM);
++		}
+ 	}
+ 
+ 	iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
+ 	if (dma_mapping_error(jrdev, iv_dma)) {
+ 		dev_err(jrdev, "unable to map IV\n");
++		caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
++			   0, 0, 0);
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 
+-	/*
+-	 * Check if iv can be contiguous with source and destination.
+-	 * If so, include it. If not, create scatterlist.
+-	 */
+-	if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
+-		iv_contig = true;
+-	else
+-		src_nents = src_nents ? : 1;
+-	sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
+-			sizeof(struct sec4_sg_entry);
++	if (mapped_src_nents == 1 &&
++	    iv_dma + ivsize == sg_dma_address(req->src)) {
++		in_contig = true;
++		sec4_sg_ents = 0;
++	} else {
++		in_contig = false;
++		sec4_sg_ents = 1 + mapped_src_nents;
++	}
++	dst_sg_idx = sec4_sg_ents;
++	sec4_sg_ents += mapped_dst_nents > 1 ? mapped_dst_nents : 0;
++	sec4_sg_bytes = sec4_sg_ents * sizeof(struct sec4_sg_entry);
+ 
+ 	/* allocate space for base edesc and hw desc commands, link tables */
+ 	edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ 			GFP_DMA | flags);
+ 	if (!edesc) {
+ 		dev_err(jrdev, "could not allocate extended descriptor\n");
++		caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, 0, 0);
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 
+@@ -2673,23 +1584,24 @@ static struct ablkcipher_edesc *ablkciph
+ 	edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) +
+ 			 desc_bytes;
+ 
+-	sec4_sg_index = 0;
+-	if (!iv_contig) {
++	if (!in_contig) {
+ 		dma_to_sec4_sg_one(edesc->sec4_sg, iv_dma, ivsize, 0);
+-		sg_to_sec4_sg_last(req->src, src_nents,
++		sg_to_sec4_sg_last(req->src, mapped_src_nents,
+ 				   edesc->sec4_sg + 1, 0);
+-		sec4_sg_index += 1 + src_nents;
+ 	}
+ 
+-	if (dst_nents) {
+-		sg_to_sec4_sg_last(req->dst, dst_nents,
+-			edesc->sec4_sg + sec4_sg_index, 0);
++	if (mapped_dst_nents > 1) {
++		sg_to_sec4_sg_last(req->dst, mapped_dst_nents,
++				   edesc->sec4_sg + dst_sg_idx, 0);
+ 	}
+ 
+ 	edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+ 					    sec4_sg_bytes, DMA_TO_DEVICE);
+ 	if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+ 		dev_err(jrdev, "unable to map S/G table\n");
++		caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, 0, 0);
++		kfree(edesc);
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 
+@@ -2701,7 +1613,7 @@ static struct ablkcipher_edesc *ablkciph
+ 		       sec4_sg_bytes, 1);
+ #endif
+ 
+-	*iv_contig_out = iv_contig;
++	*iv_contig_out = in_contig;
+ 	return edesc;
+ }
+ 
+@@ -2792,30 +1704,54 @@ static struct ablkcipher_edesc *ablkciph
+ 	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+ 	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-					  CRYPTO_TFM_REQ_MAY_SLEEP)) ?
++	gfp_t flags = (req->base.flags &  CRYPTO_TFM_REQ_MAY_SLEEP) ?
+ 		       GFP_KERNEL : GFP_ATOMIC;
+-	int src_nents, dst_nents = 0, sec4_sg_bytes;
++	int src_nents, mapped_src_nents, dst_nents, mapped_dst_nents;
+ 	struct ablkcipher_edesc *edesc;
+ 	dma_addr_t iv_dma = 0;
+-	bool iv_contig = false;
+-	int sgc;
++	bool out_contig;
+ 	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+-	int sec4_sg_index;
++	int dst_sg_idx, sec4_sg_ents, sec4_sg_bytes;
+ 
+-	src_nents = sg_count(req->src, req->nbytes);
+-
+-	if (unlikely(req->dst != req->src))
+-		dst_nents = sg_count(req->dst, req->nbytes);
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (unlikely(src_nents < 0)) {
++		dev_err(jrdev, "Insufficient bytes (%d) in src S/G\n",
++			req->nbytes);
++		return ERR_PTR(src_nents);
++	}
+ 
+ 	if (likely(req->src == req->dst)) {
+-		sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+-				 DMA_BIDIRECTIONAL);
++		mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(jrdev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		dst_nents = src_nents;
++		mapped_dst_nents = src_nents;
+ 	} else {
+-		sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+-				 DMA_TO_DEVICE);
+-		sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
+-				 DMA_FROM_DEVICE);
++		mapped_src_nents = dma_map_sg(jrdev, req->src, src_nents,
++					      DMA_TO_DEVICE);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(jrdev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		dst_nents = sg_nents_for_len(req->dst, req->nbytes);
++		if (unlikely(dst_nents < 0)) {
++			dev_err(jrdev, "Insufficient bytes (%d) in dst S/G\n",
++				req->nbytes);
++			return ERR_PTR(dst_nents);
++		}
++
++		mapped_dst_nents = dma_map_sg(jrdev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(jrdev, "unable to map destination\n");
++			dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
++			return ERR_PTR(-ENOMEM);
++		}
+ 	}
+ 
+ 	/*
+@@ -2825,21 +1761,29 @@ static struct ablkcipher_edesc *ablkciph
+ 	iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE);
+ 	if (dma_mapping_error(jrdev, iv_dma)) {
+ 		dev_err(jrdev, "unable to map IV\n");
++		caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents, 0,
++			   0, 0, 0);
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 
+-	if (!dst_nents && iv_dma + ivsize == sg_dma_address(req->dst))
+-		iv_contig = true;
+-	else
+-		dst_nents = dst_nents ? : 1;
+-	sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
+-			sizeof(struct sec4_sg_entry);
++	sec4_sg_ents = mapped_src_nents > 1 ? mapped_src_nents : 0;
++	dst_sg_idx = sec4_sg_ents;
++	if (mapped_dst_nents == 1 &&
++	    iv_dma + ivsize == sg_dma_address(req->dst)) {
++		out_contig = true;
++	} else {
++		out_contig = false;
++		sec4_sg_ents += 1 + mapped_dst_nents;
++	}
+ 
+ 	/* allocate space for base edesc and hw desc commands, link tables */
++	sec4_sg_bytes = sec4_sg_ents * sizeof(struct sec4_sg_entry);
+ 	edesc = kzalloc(sizeof(*edesc) + desc_bytes + sec4_sg_bytes,
+ 			GFP_DMA | flags);
+ 	if (!edesc) {
+ 		dev_err(jrdev, "could not allocate extended descriptor\n");
++		caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, 0, 0);
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 
+@@ -2849,24 +1793,24 @@ static struct ablkcipher_edesc *ablkciph
+ 	edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) +
+ 			 desc_bytes;
+ 
+-	sec4_sg_index = 0;
+-	if (src_nents) {
+-		sg_to_sec4_sg_last(req->src, src_nents, edesc->sec4_sg, 0);
+-		sec4_sg_index += src_nents;
+-	}
++	if (mapped_src_nents > 1)
++		sg_to_sec4_sg_last(req->src, mapped_src_nents, edesc->sec4_sg,
++				   0);
+ 
+-	if (!iv_contig) {
+-		dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
++	if (!out_contig) {
++		dma_to_sec4_sg_one(edesc->sec4_sg + dst_sg_idx,
+ 				   iv_dma, ivsize, 0);
+-		sec4_sg_index += 1;
+-		sg_to_sec4_sg_last(req->dst, dst_nents,
+-				   edesc->sec4_sg + sec4_sg_index, 0);
++		sg_to_sec4_sg_last(req->dst, mapped_dst_nents,
++				   edesc->sec4_sg + dst_sg_idx + 1, 0);
+ 	}
+ 
+ 	edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+ 					    sec4_sg_bytes, DMA_TO_DEVICE);
+ 	if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
+ 		dev_err(jrdev, "unable to map S/G table\n");
++		caam_unmap(jrdev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, 0, 0);
++		kfree(edesc);
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 	edesc->iv_dma = iv_dma;
+@@ -2878,7 +1822,7 @@ static struct ablkcipher_edesc *ablkciph
+ 		       sec4_sg_bytes, 1);
+ #endif
+ 
+-	*iv_contig_out = iv_contig;
++	*iv_contig_out = out_contig;
+ 	return edesc;
+ }
+ 
+@@ -2889,7 +1833,7 @@ static int ablkcipher_givencrypt(struct
+ 	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+ 	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+ 	struct device *jrdev = ctx->jrdev;
+-	bool iv_contig;
++	bool iv_contig = false;
+ 	u32 *desc;
+ 	int ret = 0;
+ 
+@@ -2933,7 +1877,6 @@ struct caam_alg_template {
+ 	} template_u;
+ 	u32 class1_alg_type;
+ 	u32 class2_alg_type;
+-	u32 alg_op;
+ };
+ 
+ static struct caam_alg_template driver_algs[] = {
+@@ -3118,7 +2061,6 @@ static struct caam_aead_alg driver_aeads
+ 		.caam = {
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3140,7 +2082,6 @@ static struct caam_aead_alg driver_aeads
+ 		.caam = {
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3162,7 +2103,6 @@ static struct caam_aead_alg driver_aeads
+ 		.caam = {
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3184,7 +2124,6 @@ static struct caam_aead_alg driver_aeads
+ 		.caam = {
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3206,7 +2145,6 @@ static struct caam_aead_alg driver_aeads
+ 		.caam = {
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3228,7 +2166,6 @@ static struct caam_aead_alg driver_aeads
+ 		.caam = {
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3250,7 +2187,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3273,7 +2209,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3296,7 +2231,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3319,7 +2253,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3342,7 +2275,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3365,7 +2297,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3388,7 +2319,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3411,7 +2341,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3434,7 +2363,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3457,7 +2385,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3480,7 +2407,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3503,7 +2429,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3526,7 +2451,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 		}
+ 	},
+ 	{
+@@ -3549,7 +2473,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		}
+ 	},
+@@ -3573,7 +2496,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3597,7 +2519,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3621,7 +2542,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3645,7 +2565,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3669,7 +2588,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3693,7 +2611,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3717,7 +2634,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3741,7 +2657,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3765,7 +2680,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3789,7 +2703,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3812,7 +2725,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3835,7 +2747,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3858,7 +2769,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3881,7 +2791,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3904,7 +2813,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3927,7 +2835,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3950,7 +2857,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -3973,7 +2879,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -3996,7 +2901,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -4019,7 +2923,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -4042,7 +2945,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 		},
+ 	},
+ 	{
+@@ -4065,7 +2967,6 @@ static struct caam_aead_alg driver_aeads
+ 			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 			.geniv = true,
+ 		},
+ 	},
+@@ -4090,7 +2991,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 		},
+ 	},
+@@ -4115,7 +3015,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 			.geniv = true,
+ 		},
+@@ -4141,7 +3040,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 		},
+ 	},
+@@ -4166,7 +3064,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 			.geniv = true,
+ 		},
+@@ -4192,7 +3089,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 		},
+ 	},
+@@ -4217,7 +3113,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 			.geniv = true,
+ 		},
+@@ -4243,7 +3138,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 		},
+ 	},
+@@ -4268,7 +3162,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 			.geniv = true,
+ 		},
+@@ -4294,7 +3187,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 		},
+ 	},
+@@ -4319,7 +3211,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 			.geniv = true,
+ 		},
+@@ -4345,7 +3236,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 		},
+ 	},
+@@ -4370,7 +3260,6 @@ static struct caam_aead_alg driver_aeads
+ 					   OP_ALG_AAI_CTR_MOD128,
+ 			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
+ 					   OP_ALG_AAI_HMAC_PRECOMP,
+-			.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 			.rfc3686 = true,
+ 			.geniv = true,
+ 		},
+@@ -4383,18 +3272,44 @@ struct caam_crypto_alg {
+ 	struct caam_alg_entry caam;
+ };
+ 
+-static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam)
++static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam,
++			   bool uses_dkp)
+ {
++	dma_addr_t dma_addr;
++	struct caam_drv_private *priv;
++
+ 	ctx->jrdev = caam_jr_alloc();
+ 	if (IS_ERR(ctx->jrdev)) {
+ 		pr_err("Job Ring Device allocation for transform failed\n");
+ 		return PTR_ERR(ctx->jrdev);
+ 	}
+ 
++	priv = dev_get_drvdata(ctx->jrdev->parent);
++	if (priv->era >= 6 && uses_dkp)
++		ctx->dir = DMA_BIDIRECTIONAL;
++	else
++		ctx->dir = DMA_TO_DEVICE;
++
++	dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_enc,
++					offsetof(struct caam_ctx,
++						 sh_desc_enc_dma),
++					ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
++	if (dma_mapping_error(ctx->jrdev, dma_addr)) {
++		dev_err(ctx->jrdev, "unable to map key, shared descriptors\n");
++		caam_jr_free(ctx->jrdev);
++		return -ENOMEM;
++	}
++
++	ctx->sh_desc_enc_dma = dma_addr;
++	ctx->sh_desc_dec_dma = dma_addr + offsetof(struct caam_ctx,
++						   sh_desc_dec);
++	ctx->sh_desc_givenc_dma = dma_addr + offsetof(struct caam_ctx,
++						      sh_desc_givenc);
++	ctx->key_dma = dma_addr + offsetof(struct caam_ctx, key);
++
+ 	/* copy descriptor header template value */
+-	ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
+-	ctx->class2_alg_type = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
+-	ctx->alg_op = OP_TYPE_CLASS2_ALG | caam->alg_op;
++	ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
++	ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
+ 
+ 	return 0;
+ }
+@@ -4406,7 +3321,7 @@ static int caam_cra_init(struct crypto_t
+ 		 container_of(alg, struct caam_crypto_alg, crypto_alg);
+ 	struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
+ 
+-	return caam_init_common(ctx, &caam_alg->caam);
++	return caam_init_common(ctx, &caam_alg->caam, false);
+ }
+ 
+ static int caam_aead_init(struct crypto_aead *tfm)
+@@ -4416,30 +3331,15 @@ static int caam_aead_init(struct crypto_
+ 		 container_of(alg, struct caam_aead_alg, aead);
+ 	struct caam_ctx *ctx = crypto_aead_ctx(tfm);
+ 
+-	return caam_init_common(ctx, &caam_alg->caam);
++	return caam_init_common(ctx, &caam_alg->caam,
++				alg->setkey == aead_setkey);
+ }
+ 
+ static void caam_exit_common(struct caam_ctx *ctx)
+ {
+-	if (ctx->sh_desc_enc_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->sh_desc_enc_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->sh_desc_enc_dma,
+-				 desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE);
+-	if (ctx->sh_desc_dec_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->sh_desc_dec_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->sh_desc_dec_dma,
+-				 desc_bytes(ctx->sh_desc_dec), DMA_TO_DEVICE);
+-	if (ctx->sh_desc_givenc_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->sh_desc_givenc_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
+-				 desc_bytes(ctx->sh_desc_givenc),
+-				 DMA_TO_DEVICE);
+-	if (ctx->key_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->key_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->key_dma,
+-				 ctx->enckeylen + ctx->split_key_pad_len,
+-				 DMA_TO_DEVICE);
+-
++	dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_enc_dma,
++			       offsetof(struct caam_ctx, sh_desc_enc_dma),
++			       ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
+ 	caam_jr_free(ctx->jrdev);
+ }
+ 
+@@ -4515,7 +3415,6 @@ static struct caam_crypto_alg *caam_alg_
+ 
+ 	t_alg->caam.class1_alg_type = template->class1_alg_type;
+ 	t_alg->caam.class2_alg_type = template->class2_alg_type;
+-	t_alg->caam.alg_op = template->alg_op;
+ 
+ 	return t_alg;
+ }
+--- /dev/null
++++ b/drivers/crypto/caam/caamalg_desc.c
+@@ -0,0 +1,1961 @@
++/*
++ * Shared descriptors for aead, ablkcipher algorithms
++ *
++ * Copyright 2016 NXP
++ */
++
++#include "compat.h"
++#include "desc_constr.h"
++#include "caamalg_desc.h"
++
++/*
++ * For aead functions, read payload and write payload,
++ * both of which are specified in req->src and req->dst
++ */
++static inline void aead_append_src_dst(u32 *desc, u32 msg_type)
++{
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
++			     KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH);
++}
++
++/* Set DK bit in class 1 operation if shared */
++static inline void append_dec_op1(u32 *desc, u32 type)
++{
++	u32 *jump_cmd, *uncond_jump_cmd;
++
++	/* DK bit is valid only for AES */
++	if ((type & OP_ALG_ALGSEL_MASK) != OP_ALG_ALGSEL_AES) {
++		append_operation(desc, type | OP_ALG_AS_INITFINAL |
++				 OP_ALG_DECRYPT);
++		return;
++	}
++
++	jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
++	append_operation(desc, type | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT);
++	uncond_jump_cmd = append_jump(desc, JUMP_TEST_ALL);
++	set_jump_tgt_here(desc, jump_cmd);
++	append_operation(desc, type | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT | OP_ALG_AAI_DK);
++	set_jump_tgt_here(desc, uncond_jump_cmd);
++}
++
++/**
++ * cnstr_shdsc_aead_null_encap - IPSec ESP encapsulation shared descriptor
++ *                               (non-protocol) with no (null) encryption.
++ * @desc: pointer to buffer used for descriptor construction
++ * @adata: pointer to authentication transform definitions.
++ *         A split key is required for SEC Era < 6; the size of the split key
++ *         is specified in this case. Valid algorithm values - one of
++ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
++ *         with OP_ALG_AAI_HMAC_PRECOMP.
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @era: SEC Era
++ */
++void cnstr_shdsc_aead_null_encap(u32 * const desc, struct alginfo *adata,
++				 unsigned int icvsize, int era)
++{
++	u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* Skip if already shared */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++	if (era < 6) {
++		if (adata->key_inline)
++			append_key_as_imm(desc, adata->key_virt,
++					  adata->keylen_pad, adata->keylen,
++					  CLASS_2 | KEY_DEST_MDHA_SPLIT |
++					  KEY_ENC);
++		else
++			append_key(desc, adata->key_dma, adata->keylen,
++				   CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
++	} else {
++		append_proto_dkp(desc, adata);
++	}
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* assoclen + cryptlen = seqinlen */
++	append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++	/* Prepare to read and write cryptlen + assoclen bytes */
++	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
++	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
++
++	/*
++	 * MOVE_LEN opcode is not available in all SEC HW revisions,
++	 * thus need to do some magic, i.e. self-patch the descriptor
++	 * buffer.
++	 */
++	read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF |
++				    MOVE_DEST_MATH3 |
++				    (0x6 << MOVE_LEN_SHIFT));
++	write_move_cmd = append_move(desc, MOVE_SRC_MATH3 |
++				     MOVE_DEST_DESCBUF |
++				     MOVE_WAITCOMP |
++				     (0x8 << MOVE_LEN_SHIFT));
++
++	/* Class 2 operation */
++	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	/* Read and write cryptlen bytes */
++	aead_append_src_dst(desc, FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
++
++	set_move_tgt_here(desc, read_move_cmd);
++	set_move_tgt_here(desc, write_move_cmd);
++	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
++	append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO |
++		    MOVE_AUX_LS);
++
++	/* Write ICV */
++	append_seq_store(desc, icvsize, LDST_CLASS_2_CCB |
++			 LDST_SRCDST_BYTE_CONTEXT);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "aead null enc shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_aead_null_encap);
++
++/**
++ * cnstr_shdsc_aead_null_decap - IPSec ESP decapsulation shared descriptor
++ *                               (non-protocol) with no (null) decryption.
++ * @desc: pointer to buffer used for descriptor construction
++ * @adata: pointer to authentication transform definitions.
++ *         A split key is required for SEC Era < 6; the size of the split key
++ *         is specified in this case. Valid algorithm values - one of
++ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
++ *         with OP_ALG_AAI_HMAC_PRECOMP.
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @era: SEC Era
++ */
++void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
++				 unsigned int icvsize, int era)
++{
++	u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd, *jump_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* Skip if already shared */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++	if (era < 6) {
++		if (adata->key_inline)
++			append_key_as_imm(desc, adata->key_virt,
++					  adata->keylen_pad, adata->keylen,
++					  CLASS_2 | KEY_DEST_MDHA_SPLIT |
++					  KEY_ENC);
++		else
++			append_key(desc, adata->key_dma, adata->keylen,
++				   CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
++	} else {
++		append_proto_dkp(desc, adata);
++	}
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* Class 2 operation */
++	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
++
++	/* assoclen + cryptlen = seqoutlen */
++	append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++
++	/* Prepare to read and write cryptlen + assoclen bytes */
++	append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
++	append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
++
++	/*
++	 * MOVE_LEN opcode is not available in all SEC HW revisions,
++	 * thus need to do some magic, i.e. self-patch the descriptor
++	 * buffer.
++	 */
++	read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF |
++				    MOVE_DEST_MATH2 |
++				    (0x6 << MOVE_LEN_SHIFT));
++	write_move_cmd = append_move(desc, MOVE_SRC_MATH2 |
++				     MOVE_DEST_DESCBUF |
++				     MOVE_WAITCOMP |
++				     (0x8 << MOVE_LEN_SHIFT));
++
++	/* Read and write cryptlen bytes */
++	aead_append_src_dst(desc, FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
++
++	/*
++	 * Insert a NOP here, since we need at least 4 instructions between
++	 * code patching the descriptor buffer and the location being patched.
++	 */
++	jump_cmd = append_jump(desc, JUMP_TEST_ALL);
++	set_jump_tgt_here(desc, jump_cmd);
++
++	set_move_tgt_here(desc, read_move_cmd);
++	set_move_tgt_here(desc, write_move_cmd);
++	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
++	append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO |
++		    MOVE_AUX_LS);
++	append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
++
++	/* Load ICV */
++	append_seq_fifo_load(desc, icvsize, FIFOLD_CLASS_CLASS2 |
++			     FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "aead null dec shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_aead_null_decap);
++
++static void init_sh_desc_key_aead(u32 * const desc,
++				  struct alginfo * const cdata,
++				  struct alginfo * const adata,
++				  const bool is_rfc3686, u32 *nonce, int era)
++{
++	u32 *key_jump_cmd;
++	unsigned int enckeylen = cdata->keylen;
++
++	/* Note: Context registers are saved. */
++	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
++
++	/* Skip if already shared */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++
++	/*
++	 * RFC3686 specific:
++	 *	| key = {AUTH_KEY, ENC_KEY, NONCE}
++	 *	| enckeylen = encryption key size + nonce size
++	 */
++	if (is_rfc3686)
++		enckeylen -= CTR_RFC3686_NONCE_SIZE;
++
++	if (era < 6) {
++		if (adata->key_inline)
++			append_key_as_imm(desc, adata->key_virt,
++					  adata->keylen_pad, adata->keylen,
++					  CLASS_2 | KEY_DEST_MDHA_SPLIT |
++					  KEY_ENC);
++		else
++			append_key(desc, adata->key_dma, adata->keylen,
++				   CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
++	} else {
++		append_proto_dkp(desc, adata);
++	}
++
++	if (cdata->key_inline)
++		append_key_as_imm(desc, cdata->key_virt, enckeylen,
++				  enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
++	else
++		append_key(desc, cdata->key_dma, enckeylen, CLASS_1 |
++			   KEY_DEST_CLASS_REG);
++
++	/* Load Counter into CONTEXT1 reg */
++	if (is_rfc3686) {
++		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
++				   LDST_CLASS_IND_CCB |
++				   LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
++		append_move(desc,
++			    MOVE_SRC_OUTFIFO |
++			    MOVE_DEST_CLASS1CTX |
++			    (16 << MOVE_OFFSET_SHIFT) |
++			    (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
++	}
++
++	set_jump_tgt_here(desc, key_jump_cmd);
++}
++
++/**
++ * cnstr_shdsc_aead_encap - IPSec ESP encapsulation shared descriptor
++ *                          (non-protocol).
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
++ *         with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128.
++ * @adata: pointer to authentication transform definitions.
++ *         A split key is required for SEC Era < 6; the size of the split key
++ *         is specified in this case. Valid algorithm values - one of
++ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
++ *         with OP_ALG_AAI_HMAC_PRECOMP.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
++ * @nonce: pointer to rfc3686 nonce
++ * @ctx1_iv_off: IV offset in CONTEXT1 register
++ * @is_qi: true when called from caam/qi
++ * @era: SEC Era
++ */
++void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
++			    struct alginfo *adata, unsigned int ivsize,
++			    unsigned int icvsize, const bool is_rfc3686,
++			    u32 *nonce, const u32 ctx1_iv_off, const bool is_qi,
++			    int era)
++{
++	/* Note: Context registers are saved. */
++	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era);
++
++	/* Class 2 operation */
++	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	if (is_qi) {
++		u32 *wait_load_cmd;
++
++		/* REG3 = assoclen */
++		append_seq_load(desc, 4, LDST_CLASS_DECO |
++				LDST_SRCDST_WORD_DECO_MATH3 |
++				(4 << LDST_OFFSET_SHIFT));
++
++		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++					    JUMP_COND_CALM | JUMP_COND_NCP |
++					    JUMP_COND_NOP | JUMP_COND_NIP |
++					    JUMP_COND_NIFP);
++		set_jump_tgt_here(desc, wait_load_cmd);
++
++		append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
++				LDST_SRCDST_BYTE_CONTEXT |
++				(ctx1_iv_off << LDST_OFFSET_SHIFT));
++	}
++
++	/* Read and write assoclen bytes */
++	if (is_qi || era < 3) {
++		append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
++		append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
++	} else {
++		append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
++		append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
++	}
++
++	/* Skip assoc data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
++
++	/* read assoc before reading payload */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
++				      FIFOLDST_VLF);
++
++	/* Load Counter into CONTEXT1 reg */
++	if (is_rfc3686)
++		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
++				     LDST_SRCDST_BYTE_CONTEXT |
++				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
++				      LDST_OFFSET_SHIFT));
++
++	/* Class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	/* Read and write cryptlen bytes */
++	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++	append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++	aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
++
++	/* Write ICV */
++	append_seq_store(desc, icvsize, LDST_CLASS_2_CCB |
++			 LDST_SRCDST_BYTE_CONTEXT);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "aead enc shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_aead_encap);
++
++/**
++ * cnstr_shdsc_aead_decap - IPSec ESP decapsulation shared descriptor
++ *                          (non-protocol).
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
++ *         with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128.
++ * @adata: pointer to authentication transform definitions.
++ *         A split key is required for SEC Era < 6; the size of the split key
++ *         is specified in this case. Valid algorithm values - one of
++ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
++ *         with OP_ALG_AAI_HMAC_PRECOMP.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
++ * @nonce: pointer to rfc3686 nonce
++ * @ctx1_iv_off: IV offset in CONTEXT1 register
++ * @is_qi: true when called from caam/qi
++ * @era: SEC Era
++ */
++void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
++			    struct alginfo *adata, unsigned int ivsize,
++			    unsigned int icvsize, const bool geniv,
++			    const bool is_rfc3686, u32 *nonce,
++			    const u32 ctx1_iv_off, const bool is_qi, int era)
++{
++	/* Note: Context registers are saved. */
++	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era);
++
++	/* Class 2 operation */
++	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
++
++	if (is_qi) {
++		u32 *wait_load_cmd;
++
++		/* REG3 = assoclen */
++		append_seq_load(desc, 4, LDST_CLASS_DECO |
++				LDST_SRCDST_WORD_DECO_MATH3 |
++				(4 << LDST_OFFSET_SHIFT));
++
++		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++					    JUMP_COND_CALM | JUMP_COND_NCP |
++					    JUMP_COND_NOP | JUMP_COND_NIP |
++					    JUMP_COND_NIFP);
++		set_jump_tgt_here(desc, wait_load_cmd);
++
++		if (!geniv)
++			append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
++					LDST_SRCDST_BYTE_CONTEXT |
++					(ctx1_iv_off << LDST_OFFSET_SHIFT));
++	}
++
++	/* Read and write assoclen bytes */
++	if (is_qi || era < 3) {
++		append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
++		if (geniv)
++			append_math_add_imm_u32(desc, VARSEQOUTLEN, REG3, IMM,
++						ivsize);
++		else
++			append_math_add(desc, VARSEQOUTLEN, ZERO, REG3,
++					CAAM_CMD_SZ);
++	} else {
++		append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
++		if (geniv)
++			append_math_add_imm_u32(desc, VARSEQOUTLEN, DPOVRD, IMM,
++						ivsize);
++		else
++			append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD,
++					CAAM_CMD_SZ);
++	}
++
++	/* Skip assoc data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
++
++	/* read assoc before reading payload */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
++			     KEY_VLF);
++
++	if (geniv) {
++		append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
++				LDST_SRCDST_BYTE_CONTEXT |
++				(ctx1_iv_off << LDST_OFFSET_SHIFT));
++		append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO |
++			    (ctx1_iv_off << MOVE_OFFSET_SHIFT) | ivsize);
++	}
++
++	/* Load Counter into CONTEXT1 reg */
++	if (is_rfc3686)
++		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
++				     LDST_SRCDST_BYTE_CONTEXT |
++				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
++				      LDST_OFFSET_SHIFT));
++
++	/* Choose operation */
++	if (ctx1_iv_off)
++		append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++				 OP_ALG_DECRYPT);
++	else
++		append_dec_op1(desc, cdata->algtype);
++
++	/* Read and write cryptlen bytes */
++	append_math_add(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++	append_math_add(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++	aead_append_src_dst(desc, FIFOLD_TYPE_MSG);
++
++	/* Load ICV */
++	append_seq_fifo_load(desc, icvsize, FIFOLD_CLASS_CLASS2 |
++			     FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "aead dec shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_aead_decap);
++
++/**
++ * cnstr_shdsc_aead_givencap - IPSec ESP encapsulation shared descriptor
++ *                             (non-protocol) with HW-generated initialization
++ *                             vector.
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
++ *         with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128.
++ * @adata: pointer to authentication transform definitions.
++ *         A split key is required for SEC Era < 6; the size of the split key
++ *         is specified in this case. Valid algorithm values - one of
++ *         OP_ALG_ALGSEL_{MD5, SHA1, SHA224, SHA256, SHA384, SHA512} ANDed
++ *         with OP_ALG_AAI_HMAC_PRECOMP.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
++ * @nonce: pointer to rfc3686 nonce
++ * @ctx1_iv_off: IV offset in CONTEXT1 register
++ * @is_qi: true when called from caam/qi
++ * @era: SEC Era
++ */
++void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
++			       struct alginfo *adata, unsigned int ivsize,
++			       unsigned int icvsize, const bool is_rfc3686,
++			       u32 *nonce, const u32 ctx1_iv_off,
++			       const bool is_qi, int era)
++{
++	u32 geniv, moveiv;
++
++	/* Note: Context registers are saved. */
++	init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce, era);
++
++	if (is_qi) {
++		u32 *wait_load_cmd;
++
++		/* REG3 = assoclen */
++		append_seq_load(desc, 4, LDST_CLASS_DECO |
++				LDST_SRCDST_WORD_DECO_MATH3 |
++				(4 << LDST_OFFSET_SHIFT));
++
++		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++					    JUMP_COND_CALM | JUMP_COND_NCP |
++					    JUMP_COND_NOP | JUMP_COND_NIP |
++					    JUMP_COND_NIFP);
++		set_jump_tgt_here(desc, wait_load_cmd);
++	}
++
++	if (is_rfc3686) {
++		if (is_qi)
++			append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
++					LDST_SRCDST_BYTE_CONTEXT |
++					(ctx1_iv_off << LDST_OFFSET_SHIFT));
++
++		goto copy_iv;
++	}
++
++	/* Generate IV */
++	geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
++		NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
++		NFIFOENTRY_PTYPE_RND | (ivsize << NFIFOENTRY_DLEN_SHIFT);
++	append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
++			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
++	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
++	append_move(desc, MOVE_WAITCOMP |
++		    MOVE_SRC_INFIFO | MOVE_DEST_CLASS1CTX |
++		    (ctx1_iv_off << MOVE_OFFSET_SHIFT) |
++		    (ivsize << MOVE_LEN_SHIFT));
++	append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
++
++copy_iv:
++	/* Copy IV to class 1 context */
++	append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_OUTFIFO |
++		    (ctx1_iv_off << MOVE_OFFSET_SHIFT) |
++		    (ivsize << MOVE_LEN_SHIFT));
++
++	/* Return to encryption */
++	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	/* Read and write assoclen bytes */
++	if (is_qi || era < 3) {
++		append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
++		append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
++	} else {
++		append_math_add(desc, VARSEQINLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
++		append_math_add(desc, VARSEQOUTLEN, ZERO, DPOVRD, CAAM_CMD_SZ);
++	}
++
++	/* Skip assoc data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
++
++	/* read assoc before reading payload */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
++			     KEY_VLF);
++
++	/* Copy iv from outfifo to class 2 fifo */
++	moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 |
++		 NFIFOENTRY_DTYPE_MSG | (ivsize << NFIFOENTRY_DLEN_SHIFT);
++	append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB |
++			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
++	append_load_imm_u32(desc, ivsize, LDST_CLASS_2_CCB |
++			    LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
++
++	/* Load Counter into CONTEXT1 reg */
++	if (is_rfc3686)
++		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
++				     LDST_SRCDST_BYTE_CONTEXT |
++				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
++				      LDST_OFFSET_SHIFT));
++
++	/* Class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	/* Will write ivsize + cryptlen */
++	append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++	/* Not need to reload iv */
++	append_seq_fifo_load(desc, ivsize,
++			     FIFOLD_CLASS_SKIP);
++
++	/* Will read cryptlen */
++	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | KEY_VLF |
++			     FIFOLD_TYPE_MSG1OUT2 | FIFOLD_TYPE_LASTBOTH);
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
++
++	/* Write ICV */
++	append_seq_store(desc, icvsize, LDST_CLASS_2_CCB |
++			 LDST_SRCDST_BYTE_CONTEXT);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "aead givenc shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_aead_givencap);
++
++/**
++ * cnstr_shdsc_tls_encap - tls encapsulation shared descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed
++ *         with OP_ALG_AAI_CBC
++ * @adata: pointer to authentication transform definitions.
++ *         A split key is required for SEC Era < 6; the size of the split key
++ *         is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1
++ *         ANDed with OP_ALG_AAI_HMAC_PRECOMP.
++ * @assoclen: associated data length
++ * @ivsize: initialization vector size
++ * @authsize: authentication data size
++ * @blocksize: block cipher size
++ * @era: SEC Era
++ */
++void cnstr_shdsc_tls_encap(u32 * const desc, struct alginfo *cdata,
++			   struct alginfo *adata, unsigned int assoclen,
++			   unsigned int ivsize, unsigned int authsize,
++			   unsigned int blocksize, int era)
++{
++	u32 *key_jump_cmd, *zero_payload_jump_cmd;
++	u32 genpad, idx_ld_datasz, idx_ld_pad, stidx;
++
++	/*
++	 * Compute the index (in bytes) for the LOAD with destination of
++	 * Class 1 Data Size Register and for the LOAD that generates padding
++	 */
++	if (adata->key_inline) {
++		idx_ld_datasz = DESC_TLS10_ENC_LEN + adata->keylen_pad +
++				cdata->keylen - 4 * CAAM_CMD_SZ;
++		idx_ld_pad = DESC_TLS10_ENC_LEN + adata->keylen_pad +
++			     cdata->keylen - 2 * CAAM_CMD_SZ;
++	} else {
++		idx_ld_datasz = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ -
++				4 * CAAM_CMD_SZ;
++		idx_ld_pad = DESC_TLS10_ENC_LEN + 2 * CAAM_PTR_SZ -
++			     2 * CAAM_CMD_SZ;
++	}
++
++	stidx = 1 << HDR_START_IDX_SHIFT;
++	init_sh_desc(desc, HDR_SHARE_SERIAL | stidx);
++
++	/* skip key loading if they are loaded due to sharing */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++
++	if (era < 6) {
++		if (adata->key_inline)
++			append_key_as_imm(desc, adata->key_virt,
++					  adata->keylen_pad, adata->keylen,
++					  CLASS_2 | KEY_DEST_MDHA_SPLIT |
++					  KEY_ENC);
++		else
++			append_key(desc, adata->key_dma, adata->keylen,
++				   CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
++	} else {
++		append_proto_dkp(desc, adata);
++	}
++
++	if (cdata->key_inline)
++		append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++				  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++	else
++		append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
++			   KEY_DEST_CLASS_REG);
++
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* class 2 operation */
++	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++	/* class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	/* payloadlen = input data length - (assoclen + ivlen) */
++	append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, assoclen + ivsize);
++
++	/* math1 = payloadlen + icvlen */
++	append_math_add_imm_u32(desc, REG1, REG0, IMM, authsize);
++
++	/* padlen = block_size - math1 % block_size */
++	append_math_and_imm_u32(desc, REG3, REG1, IMM, blocksize - 1);
++	append_math_sub_imm_u32(desc, REG2, IMM, REG3, blocksize);
++
++	/* cryptlen = payloadlen + icvlen + padlen */
++	append_math_add(desc, VARSEQOUTLEN, REG1, REG2, 4);
++
++	/*
++	 * update immediate data with the padding length value
++	 * for the LOAD in the class 1 data size register.
++	 */
++	append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 |
++			(idx_ld_datasz << MOVE_OFFSET_SHIFT) | 7);
++	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF |
++			(idx_ld_datasz << MOVE_OFFSET_SHIFT) | 8);
++
++	/* overwrite PL field for the padding iNFO FIFO entry  */
++	append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH2 |
++			(idx_ld_pad << MOVE_OFFSET_SHIFT) | 7);
++	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH2 | MOVE_DEST_DESCBUF |
++			(idx_ld_pad << MOVE_OFFSET_SHIFT) | 8);
++
++	/* store encrypted payload, icv and padding */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF);
++
++	/* if payload length is zero, jump to zero-payload commands */
++	append_math_add(desc, VARSEQINLEN, ZERO, REG0, 4);
++	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
++					    JUMP_COND_MATH_Z);
++
++	/* load iv in context1 */
++	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX |
++		   LDST_CLASS_1_CCB | ivsize);
++
++	/* read assoc for authentication */
++	append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 |
++			     FIFOLD_TYPE_MSG);
++	/* insnoop payload */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLD_TYPE_MSG |
++			     FIFOLD_TYPE_LAST2 | FIFOLDST_VLF);
++
++	/* jump the zero-payload commands */
++	append_jump(desc, JUMP_TEST_ALL | 3);
++
++	/* zero-payload commands */
++	set_jump_tgt_here(desc, zero_payload_jump_cmd);
++
++	/* load iv in context1 */
++	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX |
++		   LDST_CLASS_1_CCB | ivsize);
++
++	/* assoc data is the only data for authentication */
++	append_seq_fifo_load(desc, assoclen, FIFOLD_CLASS_CLASS2 |
++			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST2);
++
++	/* send icv to encryption */
++	append_move(desc, MOVE_SRC_CLASS2CTX | MOVE_DEST_CLASS1INFIFO |
++		    authsize);
++
++	/* update class 1 data size register with padding length */
++	append_load_imm_u32(desc, 0, LDST_CLASS_1_CCB |
++			    LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
++
++	/* generate padding and send it to encryption */
++	genpad = NFIFOENTRY_DEST_CLASS1 | NFIFOENTRY_LC1 | NFIFOENTRY_FC1 |
++	      NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_PTYPE_N;
++	append_load_imm_u32(desc, genpad, LDST_CLASS_IND_CCB |
++			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "tls enc shdesc@" __stringify(__LINE__) ": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
++		       desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_tls_encap);
++
++/**
++ * cnstr_shdsc_tls_decap - tls decapsulation shared descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_AES ANDed
++ *         with OP_ALG_AAI_CBC
++ * @adata: pointer to authentication transform definitions.
++ *         A split key is required for SEC Era < 6; the size of the split key
++ *         is specified in this case. Valid algorithm values OP_ALG_ALGSEL_SHA1
++ *         ANDed with OP_ALG_AAI_HMAC_PRECOMP.
++ * @assoclen: associated data length
++ * @ivsize: initialization vector size
++ * @authsize: authentication data size
++ * @blocksize: block cipher size
++ * @era: SEC Era
++ */
++void cnstr_shdsc_tls_decap(u32 * const desc, struct alginfo *cdata,
++			   struct alginfo *adata, unsigned int assoclen,
++			   unsigned int ivsize, unsigned int authsize,
++			   unsigned int blocksize, int era)
++{
++	u32 stidx, jumpback;
++	u32 *key_jump_cmd, *zero_payload_jump_cmd, *skip_zero_jump_cmd;
++	/*
++	 * Pointer Size bool determines the size of address pointers.
++	 * false - Pointers fit in one 32-bit word.
++	 * true - Pointers fit in two 32-bit words.
++	 */
++	static const bool ps = (CAAM_PTR_SZ != CAAM_CMD_SZ);
++
++	stidx = 1 << HDR_START_IDX_SHIFT;
++	init_sh_desc(desc, HDR_SHARE_SERIAL | stidx);
++
++	/* skip key loading if they are loaded due to sharing */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++
++	if (era < 6)
++		append_key(desc, adata->key_dma, adata->keylen, CLASS_2 |
++			   KEY_DEST_MDHA_SPLIT | KEY_ENC);
++	else
++		append_proto_dkp(desc, adata);
++
++	append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
++		   KEY_DEST_CLASS_REG);
++
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* class 2 operation */
++	append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
++	/* class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT);
++
++	/* VSIL = input data length - 2 * block_size */
++	append_math_sub_imm_u32(desc, VARSEQINLEN, SEQINLEN, IMM, 2 *
++				blocksize);
++
++	/*
++	 * payloadlen + icvlen + padlen = input data length - (assoclen +
++	 * ivsize)
++	 */
++	append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, assoclen + ivsize);
++
++	/* skip data to the last but one cipher block */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | LDST_VLF);
++
++	/* load iv for the last cipher block */
++	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_CLASS_CTX |
++		   LDST_CLASS_1_CCB | ivsize);
++
++	/* read last cipher block */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG |
++			     FIFOLD_TYPE_LAST1 | blocksize);
++
++	/* move decrypted block into math0 and math1 */
++	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO | MOVE_DEST_MATH0 |
++		    blocksize);
++
++	/* reset AES CHA */
++	append_load_imm_u32(desc, CCTRL_RESET_CHA_AESA, LDST_CLASS_IND_CCB |
++			    LDST_SRCDST_WORD_CHACTRL | LDST_IMM);
++
++	/* rewind input sequence */
++	append_seq_in_ptr_intlen(desc, 0, 65535, SQIN_RTO);
++
++	/* key1 is in decryption form */
++	append_operation(desc, cdata->algtype | OP_ALG_AAI_DK |
++			 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
++
++	/* load iv in context1 */
++	append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_1_CCB |
++		   LDST_SRCDST_WORD_CLASS_CTX | ivsize);
++
++	/* read sequence number */
++	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG);
++	/* load Type, Version and Len fields in math0 */
++	append_cmd(desc, CMD_SEQ_LOAD | LDST_CLASS_DECO |
++		   LDST_SRCDST_WORD_DECO_MATH0 | (3 << LDST_OFFSET_SHIFT) | 5);
++
++	/* compute (padlen - 1) */
++	append_math_and_imm_u64(desc, REG1, REG1, IMM, 255);
++
++	/* math2 = icvlen + (padlen - 1) + 1 */
++	append_math_add_imm_u32(desc, REG2, REG1, IMM, authsize + 1);
++
++	append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1);
++
++	/* VSOL = payloadlen + icvlen + padlen */
++	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, 4);
++
++	if (caam_little_end)
++		append_moveb(desc, MOVE_WAITCOMP |
++			     MOVE_SRC_MATH0 | MOVE_DEST_MATH0 | 8);
++
++	/* update Len field */
++	append_math_sub(desc, REG0, REG0, REG2, 8);
++
++	/* store decrypted payload, icv and padding */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | LDST_VLF);
++
++	/* VSIL = (payloadlen + icvlen + padlen) - (icvlen + padlen)*/
++	append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4);
++
++	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
++					    JUMP_COND_MATH_Z);
++
++	/* send Type, Version and Len(pre ICV) fields to authentication */
++	append_move(desc, MOVE_WAITCOMP |
++		    MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO |
++		    (3 << MOVE_OFFSET_SHIFT) | 5);
++
++	/* outsnooping payload */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
++			     FIFOLD_TYPE_MSG1OUT2 | FIFOLD_TYPE_LAST2 |
++			     FIFOLDST_VLF);
++	skip_zero_jump_cmd = append_jump(desc, JUMP_TEST_ALL | 2);
++
++	set_jump_tgt_here(desc, zero_payload_jump_cmd);
++	/* send Type, Version and Len(pre ICV) fields to authentication */
++	append_move(desc, MOVE_WAITCOMP | MOVE_AUX_LS |
++		    MOVE_SRC_MATH0 | MOVE_DEST_CLASS2INFIFO |
++		    (3 << MOVE_OFFSET_SHIFT) | 5);
++
++	set_jump_tgt_here(desc, skip_zero_jump_cmd);
++	append_math_add(desc, VARSEQINLEN, ZERO, REG2, 4);
++
++	/* load icvlen and padlen */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG |
++			     FIFOLD_TYPE_LAST1 | FIFOLDST_VLF);
++
++	/* VSIL = (payloadlen + icvlen + padlen) - icvlen + padlen */
++	append_math_sub(desc, VARSEQINLEN, REG3, REG2, 4);
++
++	/*
++	 * Start a new input sequence using the SEQ OUT PTR command options,
++	 * pointer and length used when the current output sequence was defined.
++	 */
++	if (ps) {
++		/*
++		 * Move the lower 32 bits of Shared Descriptor address, the
++		 * SEQ OUT PTR command, Output Pointer (2 words) and
++		 * Output Length into math registers.
++		 */
++		if (caam_little_end)
++			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF |
++				    MOVE_DEST_MATH0 |
++				    (55 * 4 << MOVE_OFFSET_SHIFT) | 20);
++		else
++			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF |
++				    MOVE_DEST_MATH0 |
++				    (54 * 4 << MOVE_OFFSET_SHIFT) | 20);
++
++		/* Transform SEQ OUT PTR command in SEQ IN PTR command */
++		append_math_and_imm_u32(desc, REG0, REG0, IMM,
++					~(CMD_SEQ_IN_PTR ^ CMD_SEQ_OUT_PTR));
++		/* Append a JUMP command after the copied fields */
++		jumpback = CMD_JUMP | (char)-9;
++		append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM |
++				    LDST_SRCDST_WORD_DECO_MATH2 |
++				    (4 << LDST_OFFSET_SHIFT));
++		append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1);
++		/* Move the updated fields back to the Job Descriptor */
++		if (caam_little_end)
++			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 |
++				    MOVE_DEST_DESCBUF |
++				    (55 * 4 << MOVE_OFFSET_SHIFT) | 24);
++		else
++			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 |
++				    MOVE_DEST_DESCBUF |
++				    (54 * 4 << MOVE_OFFSET_SHIFT) | 24);
++
++		/*
++		 * Read the new SEQ IN PTR command, Input Pointer, Input Length
++		 * and then jump back to the next command from the
++		 * Shared Descriptor.
++		 */
++		append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 6);
++	} else {
++		/*
++		 * Move the SEQ OUT PTR command, Output Pointer (1 word) and
++		 * Output Length into math registers.
++		 */
++		if (caam_little_end)
++			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF |
++				    MOVE_DEST_MATH0 |
++				    (54 * 4 << MOVE_OFFSET_SHIFT) | 12);
++		else
++			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_DESCBUF |
++				    MOVE_DEST_MATH0 |
++				    (53 * 4 << MOVE_OFFSET_SHIFT) | 12);
++
++		/* Transform SEQ OUT PTR command in SEQ IN PTR command */
++		append_math_and_imm_u64(desc, REG0, REG0, IMM,
++					~(((u64)(CMD_SEQ_IN_PTR ^
++						 CMD_SEQ_OUT_PTR)) << 32));
++		/* Append a JUMP command after the copied fields */
++		jumpback = CMD_JUMP | (char)-7;
++		append_load_imm_u32(desc, jumpback, LDST_CLASS_DECO | LDST_IMM |
++				    LDST_SRCDST_WORD_DECO_MATH1 |
++				    (4 << LDST_OFFSET_SHIFT));
++		append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 1);
++		/* Move the updated fields back to the Job Descriptor */
++		if (caam_little_end)
++			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 |
++				    MOVE_DEST_DESCBUF |
++				    (54 * 4 << MOVE_OFFSET_SHIFT) | 16);
++		else
++			append_move(desc, MOVE_WAITCOMP | MOVE_SRC_MATH0 |
++				    MOVE_DEST_DESCBUF |
++				    (53 * 4 << MOVE_OFFSET_SHIFT) | 16);
++
++		/*
++		 * Read the new SEQ IN PTR command, Input Pointer, Input Length
++		 * and then jump back to the next command from the
++		 * Shared Descriptor.
++		 */
++		 append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | 5);
++	}
++
++	/* skip payload */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_SKIP | FIFOLDST_VLF);
++	/* check icv */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_ICV |
++			     FIFOLD_TYPE_LAST2 | authsize);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "tls dec shdesc@" __stringify(__LINE__) ": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
++		       desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_tls_decap);
++
++/**
++ * cnstr_shdsc_gcm_encap - gcm encapsulation shared descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_qi: true when called from caam/qi
++ */
++void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
++			   unsigned int ivsize, unsigned int icvsize,
++			   const bool is_qi)
++{
++	u32 *key_jump_cmd, *zero_payload_jump_cmd, *zero_assoc_jump_cmd1,
++	    *zero_assoc_jump_cmd2;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* skip key loading if they are loaded due to sharing */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++	if (cdata->key_inline)
++		append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++				  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++	else
++		append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
++			   KEY_DEST_CLASS_REG);
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	if (is_qi) {
++		u32 *wait_load_cmd;
++
++		/* REG3 = assoclen */
++		append_seq_load(desc, 4, LDST_CLASS_DECO |
++				LDST_SRCDST_WORD_DECO_MATH3 |
++				(4 << LDST_OFFSET_SHIFT));
++
++		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++					    JUMP_COND_CALM | JUMP_COND_NCP |
++					    JUMP_COND_NOP | JUMP_COND_NIP |
++					    JUMP_COND_NIFP);
++		set_jump_tgt_here(desc, wait_load_cmd);
++
++		append_math_sub_imm_u32(desc, VARSEQOUTLEN, SEQINLEN, IMM,
++					ivsize);
++	} else {
++		append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG0,
++				CAAM_CMD_SZ);
++	}
++
++	/* if assoclen + cryptlen is ZERO, skip to ICV write */
++	zero_assoc_jump_cmd2 = append_jump(desc, JUMP_TEST_ALL |
++						 JUMP_COND_MATH_Z);
++
++	if (is_qi)
++		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
++				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
++
++	/* if assoclen is ZERO, skip reading the assoc data */
++	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
++	zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL |
++					   JUMP_COND_MATH_Z);
++
++	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
++
++	/* skip assoc data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
++
++	/* cryptlen = seqinlen - assoclen */
++	append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
++
++	/* if cryptlen is ZERO jump to zero-payload commands */
++	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
++					    JUMP_COND_MATH_Z);
++
++	/* read assoc data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
++	set_jump_tgt_here(desc, zero_assoc_jump_cmd1);
++
++	append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++	/* write encrypted data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
++
++	/* read payload data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
++
++	/* jump to ICV writing */
++	if (is_qi)
++		append_jump(desc, JUMP_TEST_ALL | 4);
++	else
++		append_jump(desc, JUMP_TEST_ALL | 2);
++
++	/* zero-payload commands */
++	set_jump_tgt_here(desc, zero_payload_jump_cmd);
++
++	/* read assoc data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST1);
++	if (is_qi)
++		/* jump to ICV writing */
++		append_jump(desc, JUMP_TEST_ALL | 2);
++
++	/* There is no input data */
++	set_jump_tgt_here(desc, zero_assoc_jump_cmd2);
++
++	if (is_qi)
++		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
++				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 |
++				     FIFOLD_TYPE_LAST1);
++
++	/* write ICV */
++	append_seq_store(desc, icvsize, LDST_CLASS_1_CCB |
++			 LDST_SRCDST_BYTE_CONTEXT);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "gcm enc shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_gcm_encap);
++
++/**
++ * cnstr_shdsc_gcm_decap - gcm decapsulation shared descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_qi: true when called from caam/qi
++ */
++void cnstr_shdsc_gcm_decap(u32 * const desc, struct alginfo *cdata,
++			   unsigned int ivsize, unsigned int icvsize,
++			   const bool is_qi)
++{
++	u32 *key_jump_cmd, *zero_payload_jump_cmd, *zero_assoc_jump_cmd1;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* skip key loading if they are loaded due to sharing */
++	key_jump_cmd = append_jump(desc, JUMP_JSL |
++				   JUMP_TEST_ALL | JUMP_COND_SHRD);
++	if (cdata->key_inline)
++		append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++				  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++	else
++		append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
++			   KEY_DEST_CLASS_REG);
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
++
++	if (is_qi) {
++		u32 *wait_load_cmd;
++
++		/* REG3 = assoclen */
++		append_seq_load(desc, 4, LDST_CLASS_DECO |
++				LDST_SRCDST_WORD_DECO_MATH3 |
++				(4 << LDST_OFFSET_SHIFT));
++
++		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++					    JUMP_COND_CALM | JUMP_COND_NCP |
++					    JUMP_COND_NOP | JUMP_COND_NIP |
++					    JUMP_COND_NIFP);
++		set_jump_tgt_here(desc, wait_load_cmd);
++
++		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
++				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
++	}
++
++	/* if assoclen is ZERO, skip reading the assoc data */
++	append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
++	zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL |
++						 JUMP_COND_MATH_Z);
++
++	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
++
++	/* skip assoc data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
++
++	/* read assoc data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
++
++	set_jump_tgt_here(desc, zero_assoc_jump_cmd1);
++
++	/* cryptlen = seqoutlen - assoclen */
++	append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++
++	/* jump to zero-payload command if cryptlen is zero */
++	zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL |
++					    JUMP_COND_MATH_Z);
++
++	append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++
++	/* store encrypted data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
++
++	/* read payload data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
++
++	/* zero-payload command */
++	set_jump_tgt_here(desc, zero_payload_jump_cmd);
++
++	/* read ICV */
++	append_seq_fifo_load(desc, icvsize, FIFOLD_CLASS_CLASS1 |
++			     FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "gcm dec shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_gcm_decap);
++
++/**
++ * cnstr_shdsc_rfc4106_encap - IPSec ESP gcm encapsulation shared descriptor
++ *                             (non-protocol).
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_qi: true when called from caam/qi
++ */
++void cnstr_shdsc_rfc4106_encap(u32 * const desc, struct alginfo *cdata,
++			       unsigned int ivsize, unsigned int icvsize,
++			       const bool is_qi)
++{
++	u32 *key_jump_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* Skip key loading if it is loaded due to sharing */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++	if (cdata->key_inline)
++		append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++				  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++	else
++		append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
++			   KEY_DEST_CLASS_REG);
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* Class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	if (is_qi) {
++		u32 *wait_load_cmd;
++
++		/* REG3 = assoclen */
++		append_seq_load(desc, 4, LDST_CLASS_DECO |
++				LDST_SRCDST_WORD_DECO_MATH3 |
++				(4 << LDST_OFFSET_SHIFT));
++
++		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++					    JUMP_COND_CALM | JUMP_COND_NCP |
++					    JUMP_COND_NOP | JUMP_COND_NIP |
++					    JUMP_COND_NIFP);
++		set_jump_tgt_here(desc, wait_load_cmd);
++
++		/* Read salt and IV */
++		append_fifo_load_as_imm(desc, (void *)(cdata->key_virt +
++					cdata->keylen), 4, FIFOLD_CLASS_CLASS1 |
++					FIFOLD_TYPE_IV);
++		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
++				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
++	}
++
++	append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, ivsize);
++	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
++
++	/* Read assoc data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
++
++	/* Skip IV */
++	append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_SKIP);
++
++	/* Will read cryptlen bytes */
++	append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++	/* Workaround for erratum A-005473 (simultaneous SEQ FIFO skips) */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG);
++
++	/* Skip assoc data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
++
++	/* cryptlen = seqoutlen - assoclen */
++	append_math_sub(desc, VARSEQOUTLEN, VARSEQINLEN, REG0, CAAM_CMD_SZ);
++
++	/* Write encrypted data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
++
++	/* Read payload data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
++
++	/* Write ICV */
++	append_seq_store(desc, icvsize, LDST_CLASS_1_CCB |
++			 LDST_SRCDST_BYTE_CONTEXT);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "rfc4106 enc shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_rfc4106_encap);
++
++/**
++ * cnstr_shdsc_rfc4106_decap - IPSec ESP gcm decapsulation shared descriptor
++ *                             (non-protocol).
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_qi: true when called from caam/qi
++ */
++void cnstr_shdsc_rfc4106_decap(u32 * const desc, struct alginfo *cdata,
++			       unsigned int ivsize, unsigned int icvsize,
++			       const bool is_qi)
++{
++	u32 *key_jump_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* Skip key loading if it is loaded due to sharing */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++	if (cdata->key_inline)
++		append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++				  cdata->keylen, CLASS_1 |
++				  KEY_DEST_CLASS_REG);
++	else
++		append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
++			   KEY_DEST_CLASS_REG);
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* Class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
++
++	if (is_qi) {
++		u32 *wait_load_cmd;
++
++		/* REG3 = assoclen */
++		append_seq_load(desc, 4, LDST_CLASS_DECO |
++				LDST_SRCDST_WORD_DECO_MATH3 |
++				(4 << LDST_OFFSET_SHIFT));
++
++		wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++					    JUMP_COND_CALM | JUMP_COND_NCP |
++					    JUMP_COND_NOP | JUMP_COND_NIP |
++					    JUMP_COND_NIFP);
++		set_jump_tgt_here(desc, wait_load_cmd);
++
++		/* Read salt and IV */
++		append_fifo_load_as_imm(desc, (void *)(cdata->key_virt +
++					cdata->keylen), 4, FIFOLD_CLASS_CLASS1 |
++					FIFOLD_TYPE_IV);
++		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
++				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
++	}
++
++	append_math_sub_imm_u32(desc, VARSEQINLEN, REG3, IMM, ivsize);
++	append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
++
++	/* Read assoc data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1);
++
++	/* Skip IV */
++	append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_SKIP);
++
++	/* Will read cryptlen bytes */
++	append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG3, CAAM_CMD_SZ);
++
++	/* Workaround for erratum A-005473 (simultaneous SEQ FIFO skips) */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG);
++
++	/* Skip assoc data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_SKIP | FIFOLDST_VLF);
++
++	/* Will write cryptlen bytes */
++	append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++
++	/* Store payload data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
++
++	/* Read encrypted data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF |
++			     FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1);
++
++	/* Read ICV */
++	append_seq_fifo_load(desc, icvsize, FIFOLD_CLASS_CLASS1 |
++			     FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "rfc4106 dec shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_rfc4106_decap);
++
++/**
++ * cnstr_shdsc_rfc4543_encap - IPSec ESP gmac encapsulation shared descriptor
++ *                             (non-protocol).
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_qi: true when called from caam/qi
++ */
++void cnstr_shdsc_rfc4543_encap(u32 * const desc, struct alginfo *cdata,
++			       unsigned int ivsize, unsigned int icvsize,
++			       const bool is_qi)
++{
++	u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* Skip key loading if it is loaded due to sharing */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++	if (cdata->key_inline)
++		append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++				  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++	else
++		append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
++			   KEY_DEST_CLASS_REG);
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* Class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	if (is_qi) {
++		/* assoclen is not needed, skip it */
++		append_seq_fifo_load(desc, 4, FIFOLD_CLASS_SKIP);
++
++		/* Read salt and IV */
++		append_fifo_load_as_imm(desc, (void *)(cdata->key_virt +
++					cdata->keylen), 4, FIFOLD_CLASS_CLASS1 |
++					FIFOLD_TYPE_IV);
++		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
++				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
++	}
++
++	/* assoclen + cryptlen = seqinlen */
++	append_math_sub(desc, REG3, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++	/*
++	 * MOVE_LEN opcode is not available in all SEC HW revisions,
++	 * thus need to do some magic, i.e. self-patch the descriptor
++	 * buffer.
++	 */
++	read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 |
++				    (0x6 << MOVE_LEN_SHIFT));
++	write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF |
++				     (0x8 << MOVE_LEN_SHIFT));
++
++	/* Will read assoclen + cryptlen bytes */
++	append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++	/* Will write assoclen + cryptlen bytes */
++	append_math_sub(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++	/* Read and write assoclen + cryptlen bytes */
++	aead_append_src_dst(desc, FIFOLD_TYPE_AAD);
++
++	set_move_tgt_here(desc, read_move_cmd);
++	set_move_tgt_here(desc, write_move_cmd);
++	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
++	/* Move payload data to OFIFO */
++	append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO);
++
++	/* Write ICV */
++	append_seq_store(desc, icvsize, LDST_CLASS_1_CCB |
++			 LDST_SRCDST_BYTE_CONTEXT);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "rfc4543 enc shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_rfc4543_encap);
++
++/**
++ * cnstr_shdsc_rfc4543_decap - IPSec ESP gmac decapsulation shared descriptor
++ *                             (non-protocol).
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_GCM.
++ * @ivsize: initialization vector size
++ * @icvsize: integrity check value (ICV) size (truncated or full)
++ * @is_qi: true when called from caam/qi
++ */
++void cnstr_shdsc_rfc4543_decap(u32 * const desc, struct alginfo *cdata,
++			       unsigned int ivsize, unsigned int icvsize,
++			       const bool is_qi)
++{
++	u32 *key_jump_cmd, *read_move_cmd, *write_move_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* Skip key loading if it is loaded due to sharing */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++	if (cdata->key_inline)
++		append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++				  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++	else
++		append_key(desc, cdata->key_dma, cdata->keylen, CLASS_1 |
++			   KEY_DEST_CLASS_REG);
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* Class 1 operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_DECRYPT | OP_ALG_ICV_ON);
++
++	if (is_qi) {
++		/* assoclen is not needed, skip it */
++		append_seq_fifo_load(desc, 4, FIFOLD_CLASS_SKIP);
++
++		/* Read salt and IV */
++		append_fifo_load_as_imm(desc, (void *)(cdata->key_virt +
++					cdata->keylen), 4, FIFOLD_CLASS_CLASS1 |
++					FIFOLD_TYPE_IV);
++		append_seq_fifo_load(desc, ivsize, FIFOLD_CLASS_CLASS1 |
++				     FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1);
++	}
++
++	/* assoclen + cryptlen = seqoutlen */
++	append_math_sub(desc, REG3, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++
++	/*
++	 * MOVE_LEN opcode is not available in all SEC HW revisions,
++	 * thus need to do some magic, i.e. self-patch the descriptor
++	 * buffer.
++	 */
++	read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 |
++				    (0x6 << MOVE_LEN_SHIFT));
++	write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF |
++				     (0x8 << MOVE_LEN_SHIFT));
++
++	/* Will read assoclen + cryptlen bytes */
++	append_math_sub(desc, VARSEQINLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++
++	/* Will write assoclen + cryptlen bytes */
++	append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ);
++
++	/* Store payload data */
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF);
++
++	/* In-snoop assoclen + cryptlen data */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLDST_VLF |
++			     FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST2FLUSH1);
++
++	set_move_tgt_here(desc, read_move_cmd);
++	set_move_tgt_here(desc, write_move_cmd);
++	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
++	/* Move payload data to OFIFO */
++	append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO);
++	append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
++
++	/* Read ICV */
++	append_seq_fifo_load(desc, icvsize, FIFOLD_CLASS_CLASS1 |
++			     FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "rfc4543 dec shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_rfc4543_decap);
++
++/*
++ * For ablkcipher encrypt and decrypt, read from req->src and
++ * write to req->dst
++ */
++static inline void ablkcipher_append_src_dst(u32 *desc)
++{
++	append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 |
++			     KEY_VLF | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
++	append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
++}
++
++/**
++ * cnstr_shdsc_ablkcipher_encap - ablkcipher encapsulation shared descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
++ *         with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128.
++ * @ivsize: initialization vector size
++ * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
++ * @ctx1_iv_off: IV offset in CONTEXT1 register
++ */
++void cnstr_shdsc_ablkcipher_encap(u32 * const desc, struct alginfo *cdata,
++				  unsigned int ivsize, const bool is_rfc3686,
++				  const u32 ctx1_iv_off)
++{
++	u32 *key_jump_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
++	/* Skip if already shared */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++
++	/* Load class1 key only */
++	append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++			  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++
++	/* Load nonce into CONTEXT1 reg */
++	if (is_rfc3686) {
++		const u8 *nonce = cdata->key_virt + cdata->keylen;
++
++		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
++				   LDST_CLASS_IND_CCB |
++				   LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
++		append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO |
++			    MOVE_DEST_CLASS1CTX | (16 << MOVE_OFFSET_SHIFT) |
++			    (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
++	}
++
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* Load iv */
++	append_seq_load(desc, ivsize, LDST_SRCDST_BYTE_CONTEXT |
++			LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT));
++
++	/* Load counter into CONTEXT1 reg */
++	if (is_rfc3686)
++		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
++				     LDST_SRCDST_BYTE_CONTEXT |
++				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
++				      LDST_OFFSET_SHIFT));
++
++	/* Load operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	/* Perform operation */
++	ablkcipher_append_src_dst(desc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "ablkcipher enc shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_ablkcipher_encap);
++
++/**
++ * cnstr_shdsc_ablkcipher_decap - ablkcipher decapsulation shared descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
++ *         with OP_ALG_AAI_CBC or OP_ALG_AAI_CTR_MOD128.
++ * @ivsize: initialization vector size
++ * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
++ * @ctx1_iv_off: IV offset in CONTEXT1 register
++ */
++void cnstr_shdsc_ablkcipher_decap(u32 * const desc, struct alginfo *cdata,
++				  unsigned int ivsize, const bool is_rfc3686,
++				  const u32 ctx1_iv_off)
++{
++	u32 *key_jump_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
++	/* Skip if already shared */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++
++	/* Load class1 key only */
++	append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++			  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++
++	/* Load nonce into CONTEXT1 reg */
++	if (is_rfc3686) {
++		const u8 *nonce = cdata->key_virt + cdata->keylen;
++
++		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
++				   LDST_CLASS_IND_CCB |
++				   LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
++		append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO |
++			    MOVE_DEST_CLASS1CTX | (16 << MOVE_OFFSET_SHIFT) |
++			    (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
++	}
++
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* load IV */
++	append_seq_load(desc, ivsize, LDST_SRCDST_BYTE_CONTEXT |
++			LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT));
++
++	/* Load counter into CONTEXT1 reg */
++	if (is_rfc3686)
++		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
++				     LDST_SRCDST_BYTE_CONTEXT |
++				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
++				      LDST_OFFSET_SHIFT));
++
++	/* Choose operation */
++	if (ctx1_iv_off)
++		append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++				 OP_ALG_DECRYPT);
++	else
++		append_dec_op1(desc, cdata->algtype);
++
++	/* Perform operation */
++	ablkcipher_append_src_dst(desc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "ablkcipher dec shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_ablkcipher_decap);
++
++/**
++ * cnstr_shdsc_ablkcipher_givencap - ablkcipher encapsulation shared descriptor
++ *                                   with HW-generated initialization vector.
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_{AES, DES, 3DES} ANDed
++ *         with OP_ALG_AAI_CBC.
++ * @ivsize: initialization vector size
++ * @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
++ * @ctx1_iv_off: IV offset in CONTEXT1 register
++ */
++void cnstr_shdsc_ablkcipher_givencap(u32 * const desc, struct alginfo *cdata,
++				     unsigned int ivsize, const bool is_rfc3686,
++				     const u32 ctx1_iv_off)
++{
++	u32 *key_jump_cmd, geniv;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
++	/* Skip if already shared */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++
++	/* Load class1 key only */
++	append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++			  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++
++	/* Load Nonce into CONTEXT1 reg */
++	if (is_rfc3686) {
++		const u8 *nonce = cdata->key_virt + cdata->keylen;
++
++		append_load_as_imm(desc, nonce, CTR_RFC3686_NONCE_SIZE,
++				   LDST_CLASS_IND_CCB |
++				   LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM);
++		append_move(desc, MOVE_WAITCOMP | MOVE_SRC_OUTFIFO |
++			    MOVE_DEST_CLASS1CTX | (16 << MOVE_OFFSET_SHIFT) |
++			    (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT));
++	}
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/* Generate IV */
++	geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
++		NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 | NFIFOENTRY_PTYPE_RND |
++		(ivsize << NFIFOENTRY_DLEN_SHIFT);
++	append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
++			    LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
++	append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
++	append_move(desc, MOVE_WAITCOMP | MOVE_SRC_INFIFO |
++		    MOVE_DEST_CLASS1CTX | (ivsize << MOVE_LEN_SHIFT) |
++		    (ctx1_iv_off << MOVE_OFFSET_SHIFT));
++	append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
++
++	/* Copy generated IV to memory */
++	append_seq_store(desc, ivsize, LDST_SRCDST_BYTE_CONTEXT |
++			 LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT));
++
++	/* Load Counter into CONTEXT1 reg */
++	if (is_rfc3686)
++		append_load_imm_be32(desc, 1, LDST_IMM | LDST_CLASS_1_CCB |
++				     LDST_SRCDST_BYTE_CONTEXT |
++				     ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) <<
++				      LDST_OFFSET_SHIFT));
++
++	if (ctx1_iv_off)
++		append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | JUMP_COND_NCP |
++			    (1 << JUMP_OFFSET_SHIFT));
++
++	/* Load operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	/* Perform operation */
++	ablkcipher_append_src_dst(desc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "ablkcipher givenc shdesc@" __stringify(__LINE__) ": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_ablkcipher_givencap);
++
++/**
++ * cnstr_shdsc_xts_ablkcipher_encap - xts ablkcipher encapsulation shared
++ *                                    descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_XTS.
++ */
++void cnstr_shdsc_xts_ablkcipher_encap(u32 * const desc, struct alginfo *cdata)
++{
++	__be64 sector_size = cpu_to_be64(512);
++	u32 *key_jump_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
++	/* Skip if already shared */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++
++	/* Load class1 keys only */
++	append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++			  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++
++	/* Load sector size with index 40 bytes (0x28) */
++	append_load_as_imm(desc, (void *)&sector_size, 8, LDST_CLASS_1_CCB |
++			   LDST_SRCDST_BYTE_CONTEXT |
++			   (0x28 << LDST_OFFSET_SHIFT));
++
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/*
++	 * create sequence for loading the sector index
++	 * Upper 8B of IV - will be used as sector index
++	 * Lower 8B of IV - will be discarded
++	 */
++	append_seq_load(desc, 8, LDST_SRCDST_BYTE_CONTEXT | LDST_CLASS_1_CCB |
++			(0x20 << LDST_OFFSET_SHIFT));
++	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_SKIP);
++
++	/* Load operation */
++	append_operation(desc, cdata->algtype | OP_ALG_AS_INITFINAL |
++			 OP_ALG_ENCRYPT);
++
++	/* Perform operation */
++	ablkcipher_append_src_dst(desc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "xts ablkcipher enc shdesc@" __stringify(__LINE__) ": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_xts_ablkcipher_encap);
++
++/**
++ * cnstr_shdsc_xts_ablkcipher_decap - xts ablkcipher decapsulation shared
++ *                                    descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @cdata: pointer to block cipher transform definitions
++ *         Valid algorithm values - OP_ALG_ALGSEL_AES ANDed with OP_ALG_AAI_XTS.
++ */
++void cnstr_shdsc_xts_ablkcipher_decap(u32 * const desc, struct alginfo *cdata)
++{
++	__be64 sector_size = cpu_to_be64(512);
++	u32 *key_jump_cmd;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX);
++	/* Skip if already shared */
++	key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++				   JUMP_COND_SHRD);
++
++	/* Load class1 key only */
++	append_key_as_imm(desc, cdata->key_virt, cdata->keylen,
++			  cdata->keylen, CLASS_1 | KEY_DEST_CLASS_REG);
++
++	/* Load sector size with index 40 bytes (0x28) */
++	append_load_as_imm(desc, (void *)&sector_size, 8, LDST_CLASS_1_CCB |
++			   LDST_SRCDST_BYTE_CONTEXT |
++			   (0x28 << LDST_OFFSET_SHIFT));
++
++	set_jump_tgt_here(desc, key_jump_cmd);
++
++	/*
++	 * create sequence for loading the sector index
++	 * Upper 8B of IV - will be used as sector index
++	 * Lower 8B of IV - will be discarded
++	 */
++	append_seq_load(desc, 8, LDST_SRCDST_BYTE_CONTEXT | LDST_CLASS_1_CCB |
++			(0x20 << LDST_OFFSET_SHIFT));
++	append_seq_fifo_load(desc, 8, FIFOLD_CLASS_SKIP);
++
++	/* Load operation */
++	append_dec_op1(desc, cdata->algtype);
++
++	/* Perform operation */
++	ablkcipher_append_src_dst(desc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "xts ablkcipher dec shdesc@" __stringify(__LINE__) ": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++}
++EXPORT_SYMBOL(cnstr_shdsc_xts_ablkcipher_decap);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("FSL CAAM descriptor support");
++MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
+--- /dev/null
++++ b/drivers/crypto/caam/caamalg_desc.h
+@@ -0,0 +1,127 @@
++/*
++ * Shared descriptors for aead, ablkcipher algorithms
++ *
++ * Copyright 2016 NXP
++ */
++
++#ifndef _CAAMALG_DESC_H_
++#define _CAAMALG_DESC_H_
++
++/* length of descriptors text */
++#define DESC_AEAD_BASE			(4 * CAAM_CMD_SZ)
++#define DESC_AEAD_ENC_LEN		(DESC_AEAD_BASE + 11 * CAAM_CMD_SZ)
++#define DESC_AEAD_DEC_LEN		(DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)
++#define DESC_AEAD_GIVENC_LEN		(DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
++#define DESC_QI_AEAD_ENC_LEN		(DESC_AEAD_ENC_LEN + 3 * CAAM_CMD_SZ)
++#define DESC_QI_AEAD_DEC_LEN		(DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ)
++#define DESC_QI_AEAD_GIVENC_LEN		(DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ)
++
++#define DESC_TLS_BASE			(4 * CAAM_CMD_SZ)
++#define DESC_TLS10_ENC_LEN		(DESC_TLS_BASE + 29 * CAAM_CMD_SZ)
++
++/* Note: Nonce is counted in cdata.keylen */
++#define DESC_AEAD_CTR_RFC3686_LEN	(4 * CAAM_CMD_SZ)
++
++#define DESC_AEAD_NULL_BASE		(3 * CAAM_CMD_SZ)
++#define DESC_AEAD_NULL_ENC_LEN		(DESC_AEAD_NULL_BASE + 11 * CAAM_CMD_SZ)
++#define DESC_AEAD_NULL_DEC_LEN		(DESC_AEAD_NULL_BASE + 13 * CAAM_CMD_SZ)
++
++#define DESC_GCM_BASE			(3 * CAAM_CMD_SZ)
++#define DESC_GCM_ENC_LEN		(DESC_GCM_BASE + 16 * CAAM_CMD_SZ)
++#define DESC_GCM_DEC_LEN		(DESC_GCM_BASE + 12 * CAAM_CMD_SZ)
++#define DESC_QI_GCM_ENC_LEN		(DESC_GCM_ENC_LEN + 6 * CAAM_CMD_SZ)
++#define DESC_QI_GCM_DEC_LEN		(DESC_GCM_DEC_LEN + 3 * CAAM_CMD_SZ)
++
++#define DESC_RFC4106_BASE		(3 * CAAM_CMD_SZ)
++#define DESC_RFC4106_ENC_LEN		(DESC_RFC4106_BASE + 13 * CAAM_CMD_SZ)
++#define DESC_RFC4106_DEC_LEN		(DESC_RFC4106_BASE + 13 * CAAM_CMD_SZ)
++#define DESC_QI_RFC4106_ENC_LEN		(DESC_RFC4106_ENC_LEN + 5 * CAAM_CMD_SZ)
++#define DESC_QI_RFC4106_DEC_LEN		(DESC_RFC4106_DEC_LEN + 5 * CAAM_CMD_SZ)
++
++#define DESC_RFC4543_BASE		(3 * CAAM_CMD_SZ)
++#define DESC_RFC4543_ENC_LEN		(DESC_RFC4543_BASE + 11 * CAAM_CMD_SZ)
++#define DESC_RFC4543_DEC_LEN		(DESC_RFC4543_BASE + 12 * CAAM_CMD_SZ)
++#define DESC_QI_RFC4543_ENC_LEN		(DESC_RFC4543_ENC_LEN + 4 * CAAM_CMD_SZ)
++#define DESC_QI_RFC4543_DEC_LEN		(DESC_RFC4543_DEC_LEN + 4 * CAAM_CMD_SZ)
++
++#define DESC_ABLKCIPHER_BASE		(3 * CAAM_CMD_SZ)
++#define DESC_ABLKCIPHER_ENC_LEN		(DESC_ABLKCIPHER_BASE + \
++					 20 * CAAM_CMD_SZ)
++#define DESC_ABLKCIPHER_DEC_LEN		(DESC_ABLKCIPHER_BASE + \
++					 15 * CAAM_CMD_SZ)
++
++void cnstr_shdsc_aead_null_encap(u32 * const desc, struct alginfo *adata,
++				 unsigned int icvsize, int era);
++
++void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
++				 unsigned int icvsize, int era);
++
++void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
++			    struct alginfo *adata, unsigned int ivsize,
++			    unsigned int icvsize, const bool is_rfc3686,
++			    u32 *nonce, const u32 ctx1_iv_off,
++			    const bool is_qi, int era);
++
++void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
++			    struct alginfo *adata, unsigned int ivsize,
++			    unsigned int icvsize, const bool geniv,
++			    const bool is_rfc3686, u32 *nonce,
++			    const u32 ctx1_iv_off, const bool is_qi, int era);
++
++void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
++			       struct alginfo *adata, unsigned int ivsize,
++			       unsigned int icvsize, const bool is_rfc3686,
++			       u32 *nonce, const u32 ctx1_iv_off,
++			       const bool is_qi, int era);
++
++void cnstr_shdsc_tls_encap(u32 *const desc, struct alginfo *cdata,
++			   struct alginfo *adata, unsigned int assoclen,
++			   unsigned int ivsize, unsigned int authsize,
++			   unsigned int blocksize, int era);
++
++void cnstr_shdsc_tls_decap(u32 *const desc, struct alginfo *cdata,
++			   struct alginfo *adata, unsigned int assoclen,
++			   unsigned int ivsize, unsigned int authsize,
++			   unsigned int blocksize, int era);
++
++void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
++			   unsigned int ivsize, unsigned int icvsize,
++			   const bool is_qi);
++
++void cnstr_shdsc_gcm_decap(u32 * const desc, struct alginfo *cdata,
++			   unsigned int ivsize, unsigned int icvsize,
++			   const bool is_qi);
++
++void cnstr_shdsc_rfc4106_encap(u32 * const desc, struct alginfo *cdata,
++			       unsigned int ivsize, unsigned int icvsize,
++			       const bool is_qi);
++
++void cnstr_shdsc_rfc4106_decap(u32 * const desc, struct alginfo *cdata,
++			       unsigned int ivsize, unsigned int icvsize,
++			       const bool is_qi);
++
++void cnstr_shdsc_rfc4543_encap(u32 * const desc, struct alginfo *cdata,
++			       unsigned int ivsize, unsigned int icvsize,
++			       const bool is_qi);
++
++void cnstr_shdsc_rfc4543_decap(u32 * const desc, struct alginfo *cdata,
++			       unsigned int ivsize, unsigned int icvsize,
++			       const bool is_qi);
++
++void cnstr_shdsc_ablkcipher_encap(u32 * const desc, struct alginfo *cdata,
++				  unsigned int ivsize, const bool is_rfc3686,
++				  const u32 ctx1_iv_off);
++
++void cnstr_shdsc_ablkcipher_decap(u32 * const desc, struct alginfo *cdata,
++				  unsigned int ivsize, const bool is_rfc3686,
++				  const u32 ctx1_iv_off);
++
++void cnstr_shdsc_ablkcipher_givencap(u32 * const desc, struct alginfo *cdata,
++				     unsigned int ivsize, const bool is_rfc3686,
++				     const u32 ctx1_iv_off);
++
++void cnstr_shdsc_xts_ablkcipher_encap(u32 * const desc, struct alginfo *cdata);
++
++void cnstr_shdsc_xts_ablkcipher_decap(u32 * const desc, struct alginfo *cdata);
++
++#endif /* _CAAMALG_DESC_H_ */
+--- /dev/null
++++ b/drivers/crypto/caam/caamalg_qi.c
+@@ -0,0 +1,3321 @@
++/*
++ * Freescale FSL CAAM support for crypto API over QI backend.
++ * Based on caamalg.c
++ *
++ * Copyright 2013-2016 Freescale Semiconductor, Inc.
++ * Copyright 2016-2017 NXP
++ */
++
++#include "compat.h"
++#include "ctrl.h"
++#include "regs.h"
++#include "intern.h"
++#include "desc_constr.h"
++#include "error.h"
++#include "sg_sw_qm.h"
++#include "key_gen.h"
++#include "qi.h"
++#include "jr.h"
++#include "caamalg_desc.h"
++
++/*
++ * crypto alg
++ */
++#define CAAM_CRA_PRIORITY		2000
++/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
++#define CAAM_MAX_KEY_SIZE		(AES_MAX_KEY_SIZE + \
++					 SHA512_DIGEST_SIZE * 2)
++
++#define DESC_MAX_USED_BYTES		(DESC_QI_AEAD_GIVENC_LEN + \
++					 CAAM_MAX_KEY_SIZE)
++#define DESC_MAX_USED_LEN		(DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
++
++struct caam_alg_entry {
++	int class1_alg_type;
++	int class2_alg_type;
++	bool rfc3686;
++	bool geniv;
++};
++
++struct caam_aead_alg {
++	struct aead_alg aead;
++	struct caam_alg_entry caam;
++	bool registered;
++};
++
++/*
++ * per-session context
++ */
++struct caam_ctx {
++	struct device *jrdev;
++	u32 sh_desc_enc[DESC_MAX_USED_LEN];
++	u32 sh_desc_dec[DESC_MAX_USED_LEN];
++	u32 sh_desc_givenc[DESC_MAX_USED_LEN];
++	u8 key[CAAM_MAX_KEY_SIZE];
++	dma_addr_t key_dma;
++	enum dma_data_direction dir;
++	struct alginfo adata;
++	struct alginfo cdata;
++	unsigned int authsize;
++	struct device *qidev;
++	spinlock_t lock;	/* Protects multiple init of driver context */
++	struct caam_drv_ctx *drv_ctx[NUM_OP];
++};
++
++static int aead_set_sh_desc(struct crypto_aead *aead)
++{
++	struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
++						 typeof(*alg), aead);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	unsigned int ivsize = crypto_aead_ivsize(aead);
++	u32 ctx1_iv_off = 0;
++	u32 *nonce = NULL;
++	unsigned int data_len[2];
++	u32 inl_mask;
++	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
++			       OP_ALG_AAI_CTR_MOD128);
++	const bool is_rfc3686 = alg->caam.rfc3686;
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	/*
++	 * AES-CTR needs to load IV in CONTEXT1 reg
++	 * at an offset of 128bits (16bytes)
++	 * CONTEXT1[255:128] = IV
++	 */
++	if (ctr_mode)
++		ctx1_iv_off = 16;
++
++	/*
++	 * RFC3686 specific:
++	 *	CONTEXT1[255:128] = {NONCE, IV, COUNTER}
++	 */
++	if (is_rfc3686) {
++		ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
++		nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
++				ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
++	}
++
++	data_len[0] = ctx->adata.keylen_pad;
++	data_len[1] = ctx->cdata.keylen;
++
++	if (alg->caam.geniv)
++		goto skip_enc;
++
++	/* aead_encrypt shared descriptor */
++	if (desc_inline_query(DESC_QI_AEAD_ENC_LEN +
++			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
++			      DESC_JOB_IO_LEN, data_len, &inl_mask,
++			      ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
++
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
++
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
++
++	cnstr_shdsc_aead_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata,
++			       ivsize, ctx->authsize, is_rfc3686, nonce,
++			       ctx1_iv_off, true, ctrlpriv->era);
++
++skip_enc:
++	/* aead_decrypt shared descriptor */
++	if (desc_inline_query(DESC_QI_AEAD_DEC_LEN +
++			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
++			      DESC_JOB_IO_LEN, data_len, &inl_mask,
++			      ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
++
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
++
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
++
++	cnstr_shdsc_aead_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata,
++			       ivsize, ctx->authsize, alg->caam.geniv,
++			       is_rfc3686, nonce, ctx1_iv_off, true,
++			       ctrlpriv->era);
++
++	if (!alg->caam.geniv)
++		goto skip_givenc;
++
++	/* aead_givencrypt shared descriptor */
++	if (desc_inline_query(DESC_QI_AEAD_GIVENC_LEN +
++			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
++			      DESC_JOB_IO_LEN, data_len, &inl_mask,
++			      ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
++
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
++
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
++
++	cnstr_shdsc_aead_givencap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata,
++				  ivsize, ctx->authsize, is_rfc3686, nonce,
++				  ctx1_iv_off, true, ctrlpriv->era);
++
++skip_givenc:
++	return 0;
++}
++
++static int aead_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
++
++	ctx->authsize = authsize;
++	aead_set_sh_desc(authenc);
++
++	return 0;
++}
++
++static int aead_setkey(struct crypto_aead *aead, const u8 *key,
++		       unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *jrdev = ctx->jrdev;
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
++	struct crypto_authenc_keys keys;
++	int ret = 0;
++
++	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
++		goto badkey;
++
++#ifdef DEBUG
++	dev_err(jrdev, "keylen %d enckeylen %d authkeylen %d\n",
++		keys.authkeylen + keys.enckeylen, keys.enckeylen,
++		keys.authkeylen);
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	/*
++	 * If DKP is supported, use it in the shared descriptor to generate
++	 * the split key.
++	 */
++	if (ctrlpriv->era >= 6) {
++		ctx->adata.keylen = keys.authkeylen;
++		ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
++						      OP_ALG_ALGSEL_MASK);
++
++		if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
++			goto badkey;
++
++		memcpy(ctx->key, keys.authkey, keys.authkeylen);
++		memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
++		       keys.enckeylen);
++		dma_sync_single_for_device(jrdev, ctx->key_dma,
++					   ctx->adata.keylen_pad +
++					   keys.enckeylen, ctx->dir);
++		goto skip_split_key;
++	}
++
++	ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey,
++			    keys.authkeylen, CAAM_MAX_KEY_SIZE -
++			    keys.enckeylen);
++	if (ret)
++		goto badkey;
++
++	/* postpend encryption key to auth split key */
++	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
++	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
++				   keys.enckeylen, ctx->dir);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
++		       ctx->adata.keylen_pad + keys.enckeylen, 1);
++#endif
++
++skip_split_key:
++	ctx->cdata.keylen = keys.enckeylen;
++
++	ret = aead_set_sh_desc(aead);
++	if (ret)
++		goto badkey;
++
++	/* Now update the driver contexts with the new shared descriptor */
++	if (ctx->drv_ctx[ENCRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
++					  ctx->sh_desc_enc);
++		if (ret) {
++			dev_err(jrdev, "driver enc context update failed\n");
++			goto badkey;
++		}
++	}
++
++	if (ctx->drv_ctx[DECRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
++					  ctx->sh_desc_dec);
++		if (ret) {
++			dev_err(jrdev, "driver dec context update failed\n");
++			goto badkey;
++		}
++	}
++
++	return ret;
++badkey:
++	crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
++	return -EINVAL;
++}
++
++static int tls_set_sh_desc(struct crypto_aead *tls)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	unsigned int ivsize = crypto_aead_ivsize(tls);
++	unsigned int blocksize = crypto_aead_blocksize(tls);
++	unsigned int assoclen = 13; /* always 13 bytes for TLS */
++	unsigned int data_len[2];
++	u32 inl_mask;
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	/*
++	 * TLS 1.0 encrypt shared descriptor
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	data_len[0] = ctx->adata.keylen_pad;
++	data_len[1] = ctx->cdata.keylen;
++
++	if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len,
++			      &inl_mask, ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
++
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
++
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
++
++	cnstr_shdsc_tls_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata,
++			      assoclen, ivsize, ctx->authsize, blocksize,
++			      ctrlpriv->era);
++
++	/*
++	 * TLS 1.0 decrypt shared descriptor
++	 * Keys do not fit inline, regardless of algorithms used
++	 */
++	ctx->adata.key_inline = false;
++	ctx->adata.key_dma = ctx->key_dma;
++	ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	cnstr_shdsc_tls_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata,
++			      assoclen, ivsize, ctx->authsize, blocksize,
++			      ctrlpriv->era);
++
++	return 0;
++}
++
++static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++
++	ctx->authsize = authsize;
++	tls_set_sh_desc(tls);
++
++	return 0;
++}
++
++static int tls_setkey(struct crypto_aead *tls, const u8 *key,
++		      unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	struct device *jrdev = ctx->jrdev;
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
++	struct crypto_authenc_keys keys;
++	int ret = 0;
++
++	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
++		goto badkey;
++
++#ifdef DEBUG
++	dev_err(jrdev, "keylen %d enckeylen %d authkeylen %d\n",
++		keys.authkeylen + keys.enckeylen, keys.enckeylen,
++		keys.authkeylen);
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	/*
++	 * If DKP is supported, use it in the shared descriptor to generate
++	 * the split key.
++	 */
++	if (ctrlpriv->era >= 6) {
++		ctx->adata.keylen = keys.authkeylen;
++		ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
++						      OP_ALG_ALGSEL_MASK);
++
++		if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
++			goto badkey;
++
++		memcpy(ctx->key, keys.authkey, keys.authkeylen);
++		memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
++		       keys.enckeylen);
++		dma_sync_single_for_device(jrdev, ctx->key_dma,
++					   ctx->adata.keylen_pad +
++					   keys.enckeylen, ctx->dir);
++		goto skip_split_key;
++	}
++
++	ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey,
++			    keys.authkeylen, CAAM_MAX_KEY_SIZE -
++			    keys.enckeylen);
++	if (ret)
++		goto badkey;
++
++	/* postpend encryption key to auth split key */
++	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
++	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->adata.keylen_pad +
++				   keys.enckeylen, ctx->dir);
++
++#ifdef DEBUG
++	dev_err(jrdev, "split keylen %d split keylen padded %d\n",
++		ctx->adata.keylen, ctx->adata.keylen_pad);
++	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
++		       ctx->adata.keylen_pad + keys.enckeylen, 1);
++#endif
++
++skip_split_key:
++	ctx->cdata.keylen = keys.enckeylen;
++
++	ret = tls_set_sh_desc(tls);
++	if (ret)
++		goto badkey;
++
++	/* Now update the driver contexts with the new shared descriptor */
++	if (ctx->drv_ctx[ENCRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
++					  ctx->sh_desc_enc);
++		if (ret) {
++			dev_err(jrdev, "driver enc context update failed\n");
++			goto badkey;
++		}
++	}
++
++	if (ctx->drv_ctx[DECRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
++					  ctx->sh_desc_dec);
++		if (ret) {
++			dev_err(jrdev, "driver dec context update failed\n");
++			goto badkey;
++		}
++	}
++
++	return ret;
++badkey:
++	crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN);
++	return -EINVAL;
++}
++
++static int gcm_set_sh_desc(struct crypto_aead *aead)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	unsigned int ivsize = crypto_aead_ivsize(aead);
++	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	/*
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_GCM_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	cnstr_shdsc_gcm_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
++			      ctx->authsize, true);
++
++	/*
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_GCM_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	cnstr_shdsc_gcm_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
++			      ctx->authsize, true);
++
++	return 0;
++}
++
++static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
++
++	ctx->authsize = authsize;
++	gcm_set_sh_desc(authenc);
++
++	return 0;
++}
++
++static int gcm_setkey(struct crypto_aead *aead,
++		      const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *jrdev = ctx->jrdev;
++	int ret;
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	memcpy(ctx->key, key, keylen);
++	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, ctx->dir);
++	ctx->cdata.keylen = keylen;
++
++	ret = gcm_set_sh_desc(aead);
++	if (ret)
++		return ret;
++
++	/* Now update the driver contexts with the new shared descriptor */
++	if (ctx->drv_ctx[ENCRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
++					  ctx->sh_desc_enc);
++		if (ret) {
++			dev_err(jrdev, "driver enc context update failed\n");
++			return ret;
++		}
++	}
++
++	if (ctx->drv_ctx[DECRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
++					  ctx->sh_desc_dec);
++		if (ret) {
++			dev_err(jrdev, "driver dec context update failed\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int rfc4106_set_sh_desc(struct crypto_aead *aead)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	unsigned int ivsize = crypto_aead_ivsize(aead);
++	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	ctx->cdata.key_virt = ctx->key;
++
++	/*
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_RFC4106_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	cnstr_shdsc_rfc4106_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
++				  ctx->authsize, true);
++
++	/*
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_RFC4106_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	cnstr_shdsc_rfc4106_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
++				  ctx->authsize, true);
++
++	return 0;
++}
++
++static int rfc4106_setauthsize(struct crypto_aead *authenc,
++			       unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
++
++	ctx->authsize = authsize;
++	rfc4106_set_sh_desc(authenc);
++
++	return 0;
++}
++
++static int rfc4106_setkey(struct crypto_aead *aead,
++			  const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *jrdev = ctx->jrdev;
++	int ret;
++
++	if (keylen < 4)
++		return -EINVAL;
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	memcpy(ctx->key, key, keylen);
++	/*
++	 * The last four bytes of the key material are used as the salt value
++	 * in the nonce. Update the AES key length.
++	 */
++	ctx->cdata.keylen = keylen - 4;
++	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
++				   ctx->dir);
++
++	ret = rfc4106_set_sh_desc(aead);
++	if (ret)
++		return ret;
++
++	/* Now update the driver contexts with the new shared descriptor */
++	if (ctx->drv_ctx[ENCRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
++					  ctx->sh_desc_enc);
++		if (ret) {
++			dev_err(jrdev, "driver enc context update failed\n");
++			return ret;
++		}
++	}
++
++	if (ctx->drv_ctx[DECRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
++					  ctx->sh_desc_dec);
++		if (ret) {
++			dev_err(jrdev, "driver dec context update failed\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int rfc4543_set_sh_desc(struct crypto_aead *aead)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	unsigned int ivsize = crypto_aead_ivsize(aead);
++	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	ctx->cdata.key_virt = ctx->key;
++
++	/*
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_RFC4543_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	cnstr_shdsc_rfc4543_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
++				  ctx->authsize, true);
++
++	/*
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_RFC4543_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	cnstr_shdsc_rfc4543_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
++				  ctx->authsize, true);
++
++	return 0;
++}
++
++static int rfc4543_setauthsize(struct crypto_aead *authenc,
++			       unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
++
++	ctx->authsize = authsize;
++	rfc4543_set_sh_desc(authenc);
++
++	return 0;
++}
++
++static int rfc4543_setkey(struct crypto_aead *aead,
++			  const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *jrdev = ctx->jrdev;
++	int ret;
++
++	if (keylen < 4)
++		return -EINVAL;
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	memcpy(ctx->key, key, keylen);
++	/*
++	 * The last four bytes of the key material are used as the salt value
++	 * in the nonce. Update the AES key length.
++	 */
++	ctx->cdata.keylen = keylen - 4;
++	dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->cdata.keylen,
++				   ctx->dir);
++
++	ret = rfc4543_set_sh_desc(aead);
++	if (ret)
++		return ret;
++
++	/* Now update the driver contexts with the new shared descriptor */
++	if (ctx->drv_ctx[ENCRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
++					  ctx->sh_desc_enc);
++		if (ret) {
++			dev_err(jrdev, "driver enc context update failed\n");
++			return ret;
++		}
++	}
++
++	if (ctx->drv_ctx[DECRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
++					  ctx->sh_desc_dec);
++		if (ret) {
++			dev_err(jrdev, "driver dec context update failed\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
++			     const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablkcipher);
++	const char *alg_name = crypto_tfm_alg_name(tfm);
++	struct device *jrdev = ctx->jrdev;
++	unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++	u32 ctx1_iv_off = 0;
++	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
++			       OP_ALG_AAI_CTR_MOD128);
++	const bool is_rfc3686 = (ctr_mode && strstr(alg_name, "rfc3686"));
++	int ret = 0;
++
++	memcpy(ctx->key, key, keylen);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++	/*
++	 * AES-CTR needs to load IV in CONTEXT1 reg
++	 * at an offset of 128bits (16bytes)
++	 * CONTEXT1[255:128] = IV
++	 */
++	if (ctr_mode)
++		ctx1_iv_off = 16;
++
++	/*
++	 * RFC3686 specific:
++	 *	| CONTEXT1[255:128] = {NONCE, IV, COUNTER}
++	 *	| *key = {KEY, NONCE}
++	 */
++	if (is_rfc3686) {
++		ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
++		keylen -= CTR_RFC3686_NONCE_SIZE;
++	}
++
++	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE);
++	ctx->cdata.keylen = keylen;
++	ctx->cdata.key_virt = ctx->key;
++	ctx->cdata.key_inline = true;
++
++	/* ablkcipher encrypt, decrypt, givencrypt shared descriptors */
++	cnstr_shdsc_ablkcipher_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
++				     is_rfc3686, ctx1_iv_off);
++	cnstr_shdsc_ablkcipher_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
++				     is_rfc3686, ctx1_iv_off);
++	cnstr_shdsc_ablkcipher_givencap(ctx->sh_desc_givenc, &ctx->cdata,
++					ivsize, is_rfc3686, ctx1_iv_off);
++
++	/* Now update the driver contexts with the new shared descriptor */
++	if (ctx->drv_ctx[ENCRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
++					  ctx->sh_desc_enc);
++		if (ret) {
++			dev_err(jrdev, "driver enc context update failed\n");
++			goto badkey;
++		}
++	}
++
++	if (ctx->drv_ctx[DECRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
++					  ctx->sh_desc_dec);
++		if (ret) {
++			dev_err(jrdev, "driver dec context update failed\n");
++			goto badkey;
++		}
++	}
++
++	if (ctx->drv_ctx[GIVENCRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[GIVENCRYPT],
++					  ctx->sh_desc_givenc);
++		if (ret) {
++			dev_err(jrdev, "driver givenc context update failed\n");
++			goto badkey;
++		}
++	}
++
++	return ret;
++badkey:
++	crypto_ablkcipher_set_flags(ablkcipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
++	return -EINVAL;
++}
++
++static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
++				 const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct device *jrdev = ctx->jrdev;
++	int ret = 0;
++
++	if (keylen != 2 * AES_MIN_KEY_SIZE  && keylen != 2 * AES_MAX_KEY_SIZE) {
++		crypto_ablkcipher_set_flags(ablkcipher,
++					    CRYPTO_TFM_RES_BAD_KEY_LEN);
++		dev_err(jrdev, "key size mismatch\n");
++		return -EINVAL;
++	}
++
++	memcpy(ctx->key, key, keylen);
++	dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE);
++	ctx->cdata.keylen = keylen;
++	ctx->cdata.key_virt = ctx->key;
++	ctx->cdata.key_inline = true;
++
++	/* xts ablkcipher encrypt, decrypt shared descriptors */
++	cnstr_shdsc_xts_ablkcipher_encap(ctx->sh_desc_enc, &ctx->cdata);
++	cnstr_shdsc_xts_ablkcipher_decap(ctx->sh_desc_dec, &ctx->cdata);
++
++	/* Now update the driver contexts with the new shared descriptor */
++	if (ctx->drv_ctx[ENCRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
++					  ctx->sh_desc_enc);
++		if (ret) {
++			dev_err(jrdev, "driver enc context update failed\n");
++			goto badkey;
++		}
++	}
++
++	if (ctx->drv_ctx[DECRYPT]) {
++		ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
++					  ctx->sh_desc_dec);
++		if (ret) {
++			dev_err(jrdev, "driver dec context update failed\n");
++			goto badkey;
++		}
++	}
++
++	return ret;
++badkey:
++	crypto_ablkcipher_set_flags(ablkcipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
++	return 0;
++}
++
++/*
++ * aead_edesc - s/w-extended aead descriptor
++ * @src_nents: number of segments in input scatterlist
++ * @dst_nents: number of segments in output scatterlist
++ * @iv_dma: dma address of iv for checking continuity and link table
++ * @qm_sg_bytes: length of dma mapped h/w link table
++ * @qm_sg_dma: bus physical mapped address of h/w link table
++ * @assoclen: associated data length, in CAAM endianness
++ * @assoclen_dma: bus physical mapped address of req->assoclen
++ * @drv_req: driver-specific request structure
++ * @sgt: the h/w link table
++ */
++struct aead_edesc {
++	int src_nents;
++	int dst_nents;
++	dma_addr_t iv_dma;
++	int qm_sg_bytes;
++	dma_addr_t qm_sg_dma;
++	unsigned int assoclen;
++	dma_addr_t assoclen_dma;
++	struct caam_drv_req drv_req;
++#define CAAM_QI_MAX_AEAD_SG						\
++	((CAAM_QI_MEMCACHE_SIZE - offsetof(struct aead_edesc, sgt)) /	\
++	 sizeof(struct qm_sg_entry))
++	struct qm_sg_entry sgt[0];
++};
++
++/*
++ * tls_edesc - s/w-extended tls descriptor
++ * @src_nents: number of segments in input scatterlist
++ * @dst_nents: number of segments in output scatterlist
++ * @iv_dma: dma address of iv for checking continuity and link table
++ * @qm_sg_bytes: length of dma mapped h/w link table
++ * @tmp: array of scatterlists used by 'scatterwalk_ffwd'
++ * @qm_sg_dma: bus physical mapped address of h/w link table
++ * @drv_req: driver-specific request structure
++ * @sgt: the h/w link table
++ */
++struct tls_edesc {
++	int src_nents;
++	int dst_nents;
++	dma_addr_t iv_dma;
++	int qm_sg_bytes;
++	dma_addr_t qm_sg_dma;
++	struct scatterlist tmp[2];
++	struct scatterlist *dst;
++	struct caam_drv_req drv_req;
++	struct qm_sg_entry sgt[0];
++};
++
++/*
++ * ablkcipher_edesc - s/w-extended ablkcipher descriptor
++ * @src_nents: number of segments in input scatterlist
++ * @dst_nents: number of segments in output scatterlist
++ * @iv_dma: dma address of iv for checking continuity and link table
++ * @qm_sg_bytes: length of dma mapped h/w link table
++ * @qm_sg_dma: bus physical mapped address of h/w link table
++ * @drv_req: driver-specific request structure
++ * @sgt: the h/w link table
++ */
++struct ablkcipher_edesc {
++	int src_nents;
++	int dst_nents;
++	dma_addr_t iv_dma;
++	int qm_sg_bytes;
++	dma_addr_t qm_sg_dma;
++	struct caam_drv_req drv_req;
++#define CAAM_QI_MAX_ABLKCIPHER_SG					    \
++	((CAAM_QI_MEMCACHE_SIZE - offsetof(struct ablkcipher_edesc, sgt)) / \
++	 sizeof(struct qm_sg_entry))
++	struct qm_sg_entry sgt[0];
++};
++
++static struct caam_drv_ctx *get_drv_ctx(struct caam_ctx *ctx,
++					enum optype type)
++{
++	/*
++	 * This function is called on the fast path with values of 'type'
++	 * known at compile time. Invalid arguments are not expected and
++	 * thus no checks are made.
++	 */
++	struct caam_drv_ctx *drv_ctx = ctx->drv_ctx[type];
++	u32 *desc;
++
++	if (unlikely(!drv_ctx)) {
++		spin_lock(&ctx->lock);
++
++		/* Read again to check if some other core init drv_ctx */
++		drv_ctx = ctx->drv_ctx[type];
++		if (!drv_ctx) {
++			int cpu;
++
++			if (type == ENCRYPT)
++				desc = ctx->sh_desc_enc;
++			else if (type == DECRYPT)
++				desc = ctx->sh_desc_dec;
++			else /* (type == GIVENCRYPT) */
++				desc = ctx->sh_desc_givenc;
++
++			cpu = smp_processor_id();
++			drv_ctx = caam_drv_ctx_init(ctx->qidev, &cpu, desc);
++			if (likely(!IS_ERR_OR_NULL(drv_ctx)))
++				drv_ctx->op_type = type;
++
++			ctx->drv_ctx[type] = drv_ctx;
++		}
++
++		spin_unlock(&ctx->lock);
++	}
++
++	return drv_ctx;
++}
++
++static void caam_unmap(struct device *dev, struct scatterlist *src,
++		       struct scatterlist *dst, int src_nents,
++		       int dst_nents, dma_addr_t iv_dma, int ivsize,
++		       enum optype op_type, dma_addr_t qm_sg_dma,
++		       int qm_sg_bytes)
++{
++	if (dst != src) {
++		if (src_nents)
++			dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
++		dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
++	} else {
++		dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
++	}
++
++	if (iv_dma)
++		dma_unmap_single(dev, iv_dma, ivsize,
++				 op_type == GIVENCRYPT ? DMA_FROM_DEVICE :
++							 DMA_TO_DEVICE);
++	if (qm_sg_bytes)
++		dma_unmap_single(dev, qm_sg_dma, qm_sg_bytes, DMA_TO_DEVICE);
++}
++
++static void aead_unmap(struct device *dev,
++		       struct aead_edesc *edesc,
++		       struct aead_request *req)
++{
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	int ivsize = crypto_aead_ivsize(aead);
++
++	caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
++		   edesc->iv_dma, ivsize, edesc->drv_req.drv_ctx->op_type,
++		   edesc->qm_sg_dma, edesc->qm_sg_bytes);
++	dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
++}
++
++static void tls_unmap(struct device *dev,
++		      struct tls_edesc *edesc,
++		      struct aead_request *req)
++{
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	int ivsize = crypto_aead_ivsize(aead);
++
++	caam_unmap(dev, req->src, edesc->dst, edesc->src_nents,
++		   edesc->dst_nents, edesc->iv_dma, ivsize,
++		   edesc->drv_req.drv_ctx->op_type, edesc->qm_sg_dma,
++		   edesc->qm_sg_bytes);
++}
++
++static void ablkcipher_unmap(struct device *dev,
++			     struct ablkcipher_edesc *edesc,
++			     struct ablkcipher_request *req)
++{
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++
++	caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
++		   edesc->iv_dma, ivsize, edesc->drv_req.drv_ctx->op_type,
++		   edesc->qm_sg_dma, edesc->qm_sg_bytes);
++}
++
++static void aead_done(struct caam_drv_req *drv_req, u32 status)
++{
++	struct device *qidev;
++	struct aead_edesc *edesc;
++	struct aead_request *aead_req = drv_req->app_ctx;
++	struct crypto_aead *aead = crypto_aead_reqtfm(aead_req);
++	struct caam_ctx *caam_ctx = crypto_aead_ctx(aead);
++	int ecode = 0;
++
++	qidev = caam_ctx->qidev;
++
++	if (unlikely(status)) {
++		u32 ssrc = status & JRSTA_SSRC_MASK;
++		u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
++
++		caam_jr_strstatus(qidev, status);
++		/*
++		 * verify hw auth check passed else return -EBADMSG
++		 */
++		if (ssrc == JRSTA_SSRC_CCB_ERROR &&
++		    err_id == JRSTA_CCBERR_ERRID_ICVCHK)
++			ecode = -EBADMSG;
++		else
++			ecode = -EIO;
++	}
++
++	edesc = container_of(drv_req, typeof(*edesc), drv_req);
++	aead_unmap(qidev, edesc, aead_req);
++
++	aead_request_complete(aead_req, ecode);
++	qi_cache_free(edesc);
++}
++
++/*
++ * allocate and map the aead extended descriptor
++ */
++static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
++					   bool encrypt)
++{
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
++						 typeof(*alg), aead);
++	struct device *qidev = ctx->qidev;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
++	struct aead_edesc *edesc;
++	dma_addr_t qm_sg_dma, iv_dma = 0;
++	int ivsize = 0;
++	unsigned int authsize = ctx->authsize;
++	int qm_sg_index = 0, qm_sg_ents = 0, qm_sg_bytes;
++	int in_len, out_len;
++	struct qm_sg_entry *sg_table, *fd_sgt;
++	struct caam_drv_ctx *drv_ctx;
++	enum optype op_type = encrypt ? ENCRYPT : DECRYPT;
++
++	drv_ctx = get_drv_ctx(ctx, op_type);
++	if (unlikely(IS_ERR_OR_NULL(drv_ctx)))
++		return (struct aead_edesc *)drv_ctx;
++
++	/* allocate space for base edesc and hw desc commands, link tables */
++	edesc = qi_cache_alloc(GFP_DMA | flags);
++	if (unlikely(!edesc)) {
++		dev_err(qidev, "could not allocate extended descriptor\n");
++		return ERR_PTR(-ENOMEM);
++	}
++
++	if (likely(req->src == req->dst)) {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen +
++						(encrypt ? authsize : 0));
++		if (unlikely(src_nents < 0)) {
++			dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen +
++				(encrypt ? authsize : 0));
++			qi_cache_free(edesc);
++			return ERR_PTR(src_nents);
++		}
++
++		mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(qidev, "unable to map source\n");
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++	} else {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen);
++		if (unlikely(src_nents < 0)) {
++			dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen);
++			qi_cache_free(edesc);
++			return ERR_PTR(src_nents);
++		}
++
++		dst_nents = sg_nents_for_len(req->dst, req->assoclen +
++					     req->cryptlen +
++					     (encrypt ? authsize :
++							(-authsize)));
++		if (unlikely(dst_nents < 0)) {
++			dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n",
++				req->assoclen + req->cryptlen +
++				(encrypt ? authsize : (-authsize)));
++			qi_cache_free(edesc);
++			return ERR_PTR(dst_nents);
++		}
++
++		if (src_nents) {
++			mapped_src_nents = dma_map_sg(qidev, req->src,
++						      src_nents, DMA_TO_DEVICE);
++			if (unlikely(!mapped_src_nents)) {
++				dev_err(qidev, "unable to map source\n");
++				qi_cache_free(edesc);
++				return ERR_PTR(-ENOMEM);
++			}
++		} else {
++			mapped_src_nents = 0;
++		}
++
++		mapped_dst_nents = dma_map_sg(qidev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(qidev, "unable to map destination\n");
++			dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE);
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++
++	if ((alg->caam.rfc3686 && encrypt) || !alg->caam.geniv) {
++		ivsize = crypto_aead_ivsize(aead);
++		iv_dma = dma_map_single(qidev, req->iv, ivsize, DMA_TO_DEVICE);
++		if (dma_mapping_error(qidev, iv_dma)) {
++			dev_err(qidev, "unable to map IV\n");
++			caam_unmap(qidev, req->src, req->dst, src_nents,
++				   dst_nents, 0, 0, op_type, 0, 0);
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++
++	/*
++	 * Create S/G table: req->assoclen, [IV,] req->src [, req->dst].
++	 * Input is not contiguous.
++	 */
++	qm_sg_ents = 1 + !!ivsize + mapped_src_nents +
++		     (mapped_dst_nents > 1 ? mapped_dst_nents : 0);
++	if (unlikely(qm_sg_ents > CAAM_QI_MAX_AEAD_SG)) {
++		dev_err(qidev, "Insufficient S/G entries: %d > %lu\n",
++			qm_sg_ents, CAAM_QI_MAX_AEAD_SG);
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++	sg_table = &edesc->sgt[0];
++	qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
++
++	edesc->src_nents = src_nents;
++	edesc->dst_nents = dst_nents;
++	edesc->iv_dma = iv_dma;
++	edesc->drv_req.app_ctx = req;
++	edesc->drv_req.cbk = aead_done;
++	edesc->drv_req.drv_ctx = drv_ctx;
++
++	edesc->assoclen = cpu_to_caam32(req->assoclen);
++	edesc->assoclen_dma = dma_map_single(qidev, &edesc->assoclen, 4,
++					     DMA_TO_DEVICE);
++	if (dma_mapping_error(qidev, edesc->assoclen_dma)) {
++		dev_err(qidev, "unable to map assoclen\n");
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	dma_to_qm_sg_one(sg_table, edesc->assoclen_dma, 4, 0);
++	qm_sg_index++;
++	if (ivsize) {
++		dma_to_qm_sg_one(sg_table + qm_sg_index, iv_dma, ivsize, 0);
++		qm_sg_index++;
++	}
++	sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0);
++	qm_sg_index += mapped_src_nents;
++
++	if (mapped_dst_nents > 1)
++		sg_to_qm_sg_last(req->dst, mapped_dst_nents, sg_table +
++				 qm_sg_index, 0);
++
++	qm_sg_dma = dma_map_single(qidev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
++	if (dma_mapping_error(qidev, qm_sg_dma)) {
++		dev_err(qidev, "unable to map S/G table\n");
++		dma_unmap_single(qidev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->qm_sg_dma = qm_sg_dma;
++	edesc->qm_sg_bytes = qm_sg_bytes;
++
++	out_len = req->assoclen + req->cryptlen +
++		  (encrypt ? ctx->authsize : (-ctx->authsize));
++	in_len = 4 + ivsize + req->assoclen + req->cryptlen;
++
++	fd_sgt = &edesc->drv_req.fd_sgt[0];
++	dma_to_qm_sg_one_last_ext(&fd_sgt[1], qm_sg_dma, in_len, 0);
++
++	if (req->dst == req->src) {
++		if (mapped_src_nents == 1)
++			dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(req->src),
++					 out_len, 0);
++		else
++			dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma +
++					     (1 + !!ivsize) * sizeof(*sg_table),
++					     out_len, 0);
++	} else if (mapped_dst_nents == 1) {
++		dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(req->dst), out_len,
++				 0);
++	} else {
++		dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + sizeof(*sg_table) *
++				     qm_sg_index, out_len, 0);
++	}
++
++	return edesc;
++}
++
++static inline int aead_crypt(struct aead_request *req, bool encrypt)
++{
++	struct aead_edesc *edesc;
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	int ret;
++
++	if (unlikely(caam_congested))
++		return -EAGAIN;
++
++	/* allocate extended descriptor */
++	edesc = aead_edesc_alloc(req, encrypt);
++	if (IS_ERR_OR_NULL(edesc))
++		return PTR_ERR(edesc);
++
++	/* Create and submit job descriptor */
++	ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req);
++	if (!ret) {
++		ret = -EINPROGRESS;
++	} else {
++		aead_unmap(ctx->qidev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static int aead_encrypt(struct aead_request *req)
++{
++	return aead_crypt(req, true);
++}
++
++static int aead_decrypt(struct aead_request *req)
++{
++	return aead_crypt(req, false);
++}
++
++static int ipsec_gcm_encrypt(struct aead_request *req)
++{
++	if (req->assoclen < 8)
++		return -EINVAL;
++
++	return aead_crypt(req, true);
++}
++
++static int ipsec_gcm_decrypt(struct aead_request *req)
++{
++	if (req->assoclen < 8)
++		return -EINVAL;
++
++	return aead_crypt(req, false);
++}
++
++static void tls_done(struct caam_drv_req *drv_req, u32 status)
++{
++	struct device *qidev;
++	struct tls_edesc *edesc;
++	struct aead_request *aead_req = drv_req->app_ctx;
++	struct crypto_aead *aead = crypto_aead_reqtfm(aead_req);
++	struct caam_ctx *caam_ctx = crypto_aead_ctx(aead);
++	int ecode = 0;
++
++	qidev = caam_ctx->qidev;
++
++	if (unlikely(status)) {
++		caam_jr_strstatus(qidev, status);
++		ecode = -EIO;
++	}
++
++	edesc = container_of(drv_req, typeof(*edesc), drv_req);
++	tls_unmap(qidev, edesc, aead_req);
++
++	aead_request_complete(aead_req, ecode);
++	qi_cache_free(edesc);
++}
++
++/*
++ * allocate and map the tls extended descriptor
++ */
++static struct tls_edesc *tls_edesc_alloc(struct aead_request *req, bool encrypt)
++{
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	unsigned int blocksize = crypto_aead_blocksize(aead);
++	unsigned int padsize, authsize;
++	struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
++						 typeof(*alg), aead);
++	struct device *qidev = ctx->qidev;
++	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
++		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
++	struct tls_edesc *edesc;
++	dma_addr_t qm_sg_dma, iv_dma = 0;
++	int ivsize = 0;
++	int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes;
++	int in_len, out_len;
++	struct qm_sg_entry *sg_table, *fd_sgt;
++	struct caam_drv_ctx *drv_ctx;
++	enum optype op_type = encrypt ? ENCRYPT : DECRYPT;
++	struct scatterlist *dst;
++
++	if (encrypt) {
++		padsize = blocksize - ((req->cryptlen + ctx->authsize) %
++					blocksize);
++		authsize = ctx->authsize + padsize;
++	} else {
++		authsize = ctx->authsize;
++	}
++
++	drv_ctx = get_drv_ctx(ctx, op_type);
++	if (unlikely(IS_ERR_OR_NULL(drv_ctx)))
++		return (struct tls_edesc *)drv_ctx;
++
++	/* allocate space for base edesc and hw desc commands, link tables */
++	edesc = qi_cache_alloc(GFP_DMA | flags);
++	if (unlikely(!edesc)) {
++		dev_err(qidev, "could not allocate extended descriptor\n");
++		return ERR_PTR(-ENOMEM);
++	}
++
++	if (likely(req->src == req->dst)) {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen +
++					     (encrypt ? authsize : 0));
++		if (unlikely(src_nents < 0)) {
++			dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen +
++				(encrypt ? authsize : 0));
++			qi_cache_free(edesc);
++			return ERR_PTR(src_nents);
++		}
++
++		mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(qidev, "unable to map source\n");
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++		dst = req->dst;
++	} else {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen);
++		if (unlikely(src_nents < 0)) {
++			dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen);
++			qi_cache_free(edesc);
++			return ERR_PTR(src_nents);
++		}
++
++		dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen);
++		dst_nents = sg_nents_for_len(dst, req->cryptlen +
++					     (encrypt ? authsize : 0));
++		if (unlikely(dst_nents < 0)) {
++			dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n",
++				req->cryptlen +
++				(encrypt ? authsize : 0));
++			qi_cache_free(edesc);
++			return ERR_PTR(dst_nents);
++		}
++
++		if (src_nents) {
++			mapped_src_nents = dma_map_sg(qidev, req->src,
++						      src_nents, DMA_TO_DEVICE);
++			if (unlikely(!mapped_src_nents)) {
++				dev_err(qidev, "unable to map source\n");
++				qi_cache_free(edesc);
++				return ERR_PTR(-ENOMEM);
++			}
++		} else {
++			mapped_src_nents = 0;
++		}
++
++		mapped_dst_nents = dma_map_sg(qidev, dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(qidev, "unable to map destination\n");
++			dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE);
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++
++	ivsize = crypto_aead_ivsize(aead);
++	iv_dma = dma_map_single(qidev, req->iv, ivsize, DMA_TO_DEVICE);
++	if (dma_mapping_error(qidev, iv_dma)) {
++		dev_err(qidev, "unable to map IV\n");
++		caam_unmap(qidev, req->src, dst, src_nents, dst_nents, 0, 0,
++			   op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/*
++	 * Create S/G table: IV, src, dst.
++	 * Input is not contiguous.
++	 */
++	qm_sg_ents = 1 + mapped_src_nents +
++		     (mapped_dst_nents > 1 ? mapped_dst_nents : 0);
++	sg_table = &edesc->sgt[0];
++	qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
++
++	edesc->src_nents = src_nents;
++	edesc->dst_nents = dst_nents;
++	edesc->dst = dst;
++	edesc->iv_dma = iv_dma;
++	edesc->drv_req.app_ctx = req;
++	edesc->drv_req.cbk = tls_done;
++	edesc->drv_req.drv_ctx = drv_ctx;
++
++	dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
++	qm_sg_index = 1;
++
++	sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0);
++	qm_sg_index += mapped_src_nents;
++
++	if (mapped_dst_nents > 1)
++		sg_to_qm_sg_last(dst, mapped_dst_nents, sg_table +
++				 qm_sg_index, 0);
++
++	qm_sg_dma = dma_map_single(qidev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
++	if (dma_mapping_error(qidev, qm_sg_dma)) {
++		dev_err(qidev, "unable to map S/G table\n");
++		caam_unmap(qidev, req->src, dst, src_nents, dst_nents, iv_dma,
++			   ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->qm_sg_dma = qm_sg_dma;
++	edesc->qm_sg_bytes = qm_sg_bytes;
++
++	out_len = req->cryptlen + (encrypt ? authsize : 0);
++	in_len = ivsize + req->assoclen + req->cryptlen;
++
++	fd_sgt = &edesc->drv_req.fd_sgt[0];
++
++	dma_to_qm_sg_one_last_ext(&fd_sgt[1], qm_sg_dma, in_len, 0);
++
++	if (req->dst == req->src)
++		dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma +
++				    (sg_nents_for_len(req->src, req->assoclen) +
++				     1) * sizeof(*sg_table), out_len, 0);
++	else if (mapped_dst_nents == 1)
++		dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(dst), out_len, 0);
++	else
++		dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + sizeof(*sg_table) *
++				     qm_sg_index, out_len, 0);
++
++	return edesc;
++}
++
++static int tls_crypt(struct aead_request *req, bool encrypt)
++{
++	struct tls_edesc *edesc;
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	int ret;
++
++	if (unlikely(caam_congested))
++		return -EAGAIN;
++
++	edesc = tls_edesc_alloc(req, encrypt);
++	if (IS_ERR_OR_NULL(edesc))
++		return PTR_ERR(edesc);
++
++	ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req);
++	if (!ret) {
++		ret = -EINPROGRESS;
++	} else {
++		tls_unmap(ctx->qidev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static int tls_encrypt(struct aead_request *req)
++{
++	return tls_crypt(req, true);
++}
++
++static int tls_decrypt(struct aead_request *req)
++{
++	return tls_crypt(req, false);
++}
++
++static void ablkcipher_done(struct caam_drv_req *drv_req, u32 status)
++{
++	struct ablkcipher_edesc *edesc;
++	struct ablkcipher_request *req = drv_req->app_ctx;
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *caam_ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct device *qidev = caam_ctx->qidev;
++	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++
++#ifdef DEBUG
++	dev_err(qidev, "%s %d: status 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	edesc = container_of(drv_req, typeof(*edesc), drv_req);
++
++	if (status)
++		caam_jr_strstatus(qidev, status);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "dstiv  @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
++		       edesc->src_nents > 1 ? 100 : ivsize, 1);
++	caam_dump_sg(KERN_ERR, "dst    @" __stringify(__LINE__)": ",
++		     DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
++		     edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
++#endif
++
++	ablkcipher_unmap(qidev, edesc, req);
++	qi_cache_free(edesc);
++
++	/*
++	 * The crypto API expects us to set the IV (req->info) to the last
++	 * ciphertext block. This is used e.g. by the CTS mode.
++	 */
++	scatterwalk_map_and_copy(req->info, req->dst, req->nbytes - ivsize,
++				 ivsize, 0);
++
++	ablkcipher_request_complete(req, status);
++}
++
++static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
++						       *req, bool encrypt)
++{
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct device *qidev = ctx->qidev;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
++	struct ablkcipher_edesc *edesc;
++	dma_addr_t iv_dma;
++	bool in_contig;
++	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++	int dst_sg_idx, qm_sg_ents;
++	struct qm_sg_entry *sg_table, *fd_sgt;
++	struct caam_drv_ctx *drv_ctx;
++	enum optype op_type = encrypt ? ENCRYPT : DECRYPT;
++
++	drv_ctx = get_drv_ctx(ctx, op_type);
++	if (unlikely(IS_ERR_OR_NULL(drv_ctx)))
++		return (struct ablkcipher_edesc *)drv_ctx;
++
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (unlikely(src_nents < 0)) {
++		dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
++			req->nbytes);
++		return ERR_PTR(src_nents);
++	}
++
++	if (unlikely(req->src != req->dst)) {
++		dst_nents = sg_nents_for_len(req->dst, req->nbytes);
++		if (unlikely(dst_nents < 0)) {
++			dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n",
++				req->nbytes);
++			return ERR_PTR(dst_nents);
++		}
++
++		mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
++					      DMA_TO_DEVICE);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(qidev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		mapped_dst_nents = dma_map_sg(qidev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(qidev, "unable to map destination\n");
++			dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE);
++			return ERR_PTR(-ENOMEM);
++		}
++	} else {
++		mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(qidev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++
++	iv_dma = dma_map_single(qidev, req->info, ivsize, DMA_TO_DEVICE);
++	if (dma_mapping_error(qidev, iv_dma)) {
++		dev_err(qidev, "unable to map IV\n");
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents, 0,
++			   0, 0, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	if (mapped_src_nents == 1 &&
++	    iv_dma + ivsize == sg_dma_address(req->src)) {
++		in_contig = true;
++		qm_sg_ents = 0;
++	} else {
++		in_contig = false;
++		qm_sg_ents = 1 + mapped_src_nents;
++	}
++	dst_sg_idx = qm_sg_ents;
++
++	qm_sg_ents += mapped_dst_nents > 1 ? mapped_dst_nents : 0;
++	if (unlikely(qm_sg_ents > CAAM_QI_MAX_ABLKCIPHER_SG)) {
++		dev_err(qidev, "Insufficient S/G entries: %d > %lu\n",
++			qm_sg_ents, CAAM_QI_MAX_ABLKCIPHER_SG);
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_alloc(GFP_DMA | flags);
++	if (unlikely(!edesc)) {
++		dev_err(qidev, "could not allocate extended descriptor\n");
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->src_nents = src_nents;
++	edesc->dst_nents = dst_nents;
++	edesc->iv_dma = iv_dma;
++	sg_table = &edesc->sgt[0];
++	edesc->qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
++	edesc->drv_req.app_ctx = req;
++	edesc->drv_req.cbk = ablkcipher_done;
++	edesc->drv_req.drv_ctx = drv_ctx;
++
++	if (!in_contig) {
++		dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
++		sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + 1, 0);
++	}
++
++	if (mapped_dst_nents > 1)
++		sg_to_qm_sg_last(req->dst, mapped_dst_nents, sg_table +
++				 dst_sg_idx, 0);
++
++	edesc->qm_sg_dma = dma_map_single(qidev, sg_table, edesc->qm_sg_bytes,
++					  DMA_TO_DEVICE);
++	if (dma_mapping_error(qidev, edesc->qm_sg_dma)) {
++		dev_err(qidev, "unable to map S/G table\n");
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	fd_sgt = &edesc->drv_req.fd_sgt[0];
++
++	if (!in_contig)
++		dma_to_qm_sg_one_last_ext(&fd_sgt[1], edesc->qm_sg_dma,
++					  ivsize + req->nbytes, 0);
++	else
++		dma_to_qm_sg_one_last(&fd_sgt[1], iv_dma, ivsize + req->nbytes,
++				      0);
++
++	if (req->src == req->dst) {
++		if (!in_contig)
++			dma_to_qm_sg_one_ext(&fd_sgt[0], edesc->qm_sg_dma +
++					     sizeof(*sg_table), req->nbytes, 0);
++		else
++			dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(req->src),
++					 req->nbytes, 0);
++	} else if (mapped_dst_nents > 1) {
++		dma_to_qm_sg_one_ext(&fd_sgt[0], edesc->qm_sg_dma + dst_sg_idx *
++				     sizeof(*sg_table), req->nbytes, 0);
++	} else {
++		dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(req->dst),
++				 req->nbytes, 0);
++	}
++
++	return edesc;
++}
++
++static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc(
++	struct skcipher_givcrypt_request *creq)
++{
++	struct ablkcipher_request *req = &creq->creq;
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct device *qidev = ctx->qidev;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents, mapped_dst_nents;
++	struct ablkcipher_edesc *edesc;
++	dma_addr_t iv_dma;
++	bool out_contig;
++	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++	struct qm_sg_entry *sg_table, *fd_sgt;
++	int dst_sg_idx, qm_sg_ents;
++	struct caam_drv_ctx *drv_ctx;
++
++	drv_ctx = get_drv_ctx(ctx, GIVENCRYPT);
++	if (unlikely(IS_ERR_OR_NULL(drv_ctx)))
++		return (struct ablkcipher_edesc *)drv_ctx;
++
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (unlikely(src_nents < 0)) {
++		dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
++			req->nbytes);
++		return ERR_PTR(src_nents);
++	}
++
++	if (unlikely(req->src != req->dst)) {
++		dst_nents = sg_nents_for_len(req->dst, req->nbytes);
++		if (unlikely(dst_nents < 0)) {
++			dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n",
++				req->nbytes);
++			return ERR_PTR(dst_nents);
++		}
++
++		mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
++					      DMA_TO_DEVICE);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(qidev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		mapped_dst_nents = dma_map_sg(qidev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(qidev, "unable to map destination\n");
++			dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE);
++			return ERR_PTR(-ENOMEM);
++		}
++	} else {
++		mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(qidev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		dst_nents = src_nents;
++		mapped_dst_nents = src_nents;
++	}
++
++	iv_dma = dma_map_single(qidev, creq->giv, ivsize, DMA_FROM_DEVICE);
++	if (dma_mapping_error(qidev, iv_dma)) {
++		dev_err(qidev, "unable to map IV\n");
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents, 0,
++			   0, 0, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	qm_sg_ents = mapped_src_nents > 1 ? mapped_src_nents : 0;
++	dst_sg_idx = qm_sg_ents;
++	if (mapped_dst_nents == 1 &&
++	    iv_dma + ivsize == sg_dma_address(req->dst)) {
++		out_contig = true;
++	} else {
++		out_contig = false;
++		qm_sg_ents += 1 + mapped_dst_nents;
++	}
++
++	if (unlikely(qm_sg_ents > CAAM_QI_MAX_ABLKCIPHER_SG)) {
++		dev_err(qidev, "Insufficient S/G entries: %d > %lu\n",
++			qm_sg_ents, CAAM_QI_MAX_ABLKCIPHER_SG);
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, GIVENCRYPT, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_alloc(GFP_DMA | flags);
++	if (!edesc) {
++		dev_err(qidev, "could not allocate extended descriptor\n");
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, GIVENCRYPT, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->src_nents = src_nents;
++	edesc->dst_nents = dst_nents;
++	edesc->iv_dma = iv_dma;
++	sg_table = &edesc->sgt[0];
++	edesc->qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
++	edesc->drv_req.app_ctx = req;
++	edesc->drv_req.cbk = ablkcipher_done;
++	edesc->drv_req.drv_ctx = drv_ctx;
++
++	if (mapped_src_nents > 1)
++		sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table, 0);
++
++	if (!out_contig) {
++		dma_to_qm_sg_one(sg_table + dst_sg_idx, iv_dma, ivsize, 0);
++		sg_to_qm_sg_last(req->dst, mapped_dst_nents, sg_table +
++				 dst_sg_idx + 1, 0);
++	}
++
++	edesc->qm_sg_dma = dma_map_single(qidev, sg_table, edesc->qm_sg_bytes,
++					  DMA_TO_DEVICE);
++	if (dma_mapping_error(qidev, edesc->qm_sg_dma)) {
++		dev_err(qidev, "unable to map S/G table\n");
++		caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, GIVENCRYPT, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	fd_sgt = &edesc->drv_req.fd_sgt[0];
++
++	if (mapped_src_nents > 1)
++		dma_to_qm_sg_one_ext(&fd_sgt[1], edesc->qm_sg_dma, req->nbytes,
++				     0);
++	else
++		dma_to_qm_sg_one(&fd_sgt[1], sg_dma_address(req->src),
++				 req->nbytes, 0);
++
++	if (!out_contig)
++		dma_to_qm_sg_one_ext(&fd_sgt[0], edesc->qm_sg_dma + dst_sg_idx *
++				     sizeof(*sg_table), ivsize + req->nbytes,
++				     0);
++	else
++		dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(req->dst),
++				 ivsize + req->nbytes, 0);
++
++	return edesc;
++}
++
++static inline int ablkcipher_crypt(struct ablkcipher_request *req, bool encrypt)
++{
++	struct ablkcipher_edesc *edesc;
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	int ret;
++
++	if (unlikely(caam_congested))
++		return -EAGAIN;
++
++	/* allocate extended descriptor */
++	edesc = ablkcipher_edesc_alloc(req, encrypt);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req);
++	if (!ret) {
++		ret = -EINPROGRESS;
++	} else {
++		ablkcipher_unmap(ctx->qidev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static int ablkcipher_encrypt(struct ablkcipher_request *req)
++{
++	return ablkcipher_crypt(req, true);
++}
++
++static int ablkcipher_decrypt(struct ablkcipher_request *req)
++{
++	return ablkcipher_crypt(req, false);
++}
++
++static int ablkcipher_givencrypt(struct skcipher_givcrypt_request *creq)
++{
++	struct ablkcipher_request *req = &creq->creq;
++	struct ablkcipher_edesc *edesc;
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	int ret;
++
++	if (unlikely(caam_congested))
++		return -EAGAIN;
++
++	/* allocate extended descriptor */
++	edesc = ablkcipher_giv_edesc_alloc(creq);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req);
++	if (!ret) {
++		ret = -EINPROGRESS;
++	} else {
++		ablkcipher_unmap(ctx->qidev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++#define template_ablkcipher	template_u.ablkcipher
++struct caam_alg_template {
++	char name[CRYPTO_MAX_ALG_NAME];
++	char driver_name[CRYPTO_MAX_ALG_NAME];
++	unsigned int blocksize;
++	u32 type;
++	union {
++		struct ablkcipher_alg ablkcipher;
++	} template_u;
++	u32 class1_alg_type;
++	u32 class2_alg_type;
++};
++
++static struct caam_alg_template driver_algs[] = {
++	/* ablkcipher descriptor */
++	{
++		.name = "cbc(aes)",
++		.driver_name = "cbc-aes-caam-qi",
++		.blocksize = AES_BLOCK_SIZE,
++		.type = CRYPTO_ALG_TYPE_GIVCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.givencrypt = ablkcipher_givencrypt,
++			.geniv = "<built-in>",
++			.min_keysize = AES_MIN_KEY_SIZE,
++			.max_keysize = AES_MAX_KEY_SIZE,
++			.ivsize = AES_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++	},
++	{
++		.name = "cbc(des3_ede)",
++		.driver_name = "cbc-3des-caam-qi",
++		.blocksize = DES3_EDE_BLOCK_SIZE,
++		.type = CRYPTO_ALG_TYPE_GIVCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.givencrypt = ablkcipher_givencrypt,
++			.geniv = "<built-in>",
++			.min_keysize = DES3_EDE_KEY_SIZE,
++			.max_keysize = DES3_EDE_KEY_SIZE,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++	},
++	{
++		.name = "cbc(des)",
++		.driver_name = "cbc-des-caam-qi",
++		.blocksize = DES_BLOCK_SIZE,
++		.type = CRYPTO_ALG_TYPE_GIVCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.givencrypt = ablkcipher_givencrypt,
++			.geniv = "<built-in>",
++			.min_keysize = DES_KEY_SIZE,
++			.max_keysize = DES_KEY_SIZE,
++			.ivsize = DES_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++	},
++	{
++		.name = "ctr(aes)",
++		.driver_name = "ctr-aes-caam-qi",
++		.blocksize = 1,
++		.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.geniv = "chainiv",
++			.min_keysize = AES_MIN_KEY_SIZE,
++			.max_keysize = AES_MAX_KEY_SIZE,
++			.ivsize = AES_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
++	},
++	{
++		.name = "rfc3686(ctr(aes))",
++		.driver_name = "rfc3686-ctr-aes-caam-qi",
++		.blocksize = 1,
++		.type = CRYPTO_ALG_TYPE_GIVCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.givencrypt = ablkcipher_givencrypt,
++			.geniv = "<built-in>",
++			.min_keysize = AES_MIN_KEY_SIZE +
++				       CTR_RFC3686_NONCE_SIZE,
++			.max_keysize = AES_MAX_KEY_SIZE +
++				       CTR_RFC3686_NONCE_SIZE,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
++	},
++	{
++		.name = "xts(aes)",
++		.driver_name = "xts-aes-caam-qi",
++		.blocksize = AES_BLOCK_SIZE,
++		.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++		.template_ablkcipher = {
++			.setkey = xts_ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.geniv = "eseqiv",
++			.min_keysize = 2 * AES_MIN_KEY_SIZE,
++			.max_keysize = 2 * AES_MAX_KEY_SIZE,
++			.ivsize = AES_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS,
++	},
++};
++
++static struct caam_aead_alg driver_aeads[] = {
++	{
++		.aead = {
++			.base = {
++				.cra_name = "rfc4106(gcm(aes))",
++				.cra_driver_name = "rfc4106-gcm-aes-caam-qi",
++				.cra_blocksize = 1,
++			},
++			.setkey = rfc4106_setkey,
++			.setauthsize = rfc4106_setauthsize,
++			.encrypt = ipsec_gcm_encrypt,
++			.decrypt = ipsec_gcm_decrypt,
++			.ivsize = 8,
++			.maxauthsize = AES_BLOCK_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "rfc4543(gcm(aes))",
++				.cra_driver_name = "rfc4543-gcm-aes-caam-qi",
++				.cra_blocksize = 1,
++			},
++			.setkey = rfc4543_setkey,
++			.setauthsize = rfc4543_setauthsize,
++			.encrypt = ipsec_gcm_encrypt,
++			.decrypt = ipsec_gcm_decrypt,
++			.ivsize = 8,
++			.maxauthsize = AES_BLOCK_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
++		},
++	},
++	/* Galois Counter Mode */
++	{
++		.aead = {
++			.base = {
++				.cra_name = "gcm(aes)",
++				.cra_driver_name = "gcm-aes-caam-qi",
++				.cra_blocksize = 1,
++			},
++			.setkey = gcm_setkey,
++			.setauthsize = gcm_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = 12,
++			.maxauthsize = AES_BLOCK_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
++		}
++	},
++	/* single-pass ipsec_esp descriptor */
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(md5),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-md5-"
++						   "cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(md5),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-hmac-md5-"
++						   "cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha1),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha1-"
++						   "cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha1),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha1-cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha224),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha224-"
++						   "cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha224),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha224-cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha256),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha256-"
++						   "cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha256),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha256-cbc-aes-"
++						   "caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha384),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha384-"
++						   "cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha384),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha384-cbc-aes-"
++						   "caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha512),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha512-"
++						   "cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha512),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha512-cbc-aes-"
++						   "caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-md5-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(md5),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-hmac-md5-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha1),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha1-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha1),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha1-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha224),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha224-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha224),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha224-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha256),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha256-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha256),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha256-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha384),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha384-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha384),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha384-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha512),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha512-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha512),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha512-"
++						   "cbc-des3_ede-caam-qi",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(md5),cbc(des))",
++				.cra_driver_name = "authenc-hmac-md5-"
++						   "cbc-des-caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(md5),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-hmac-md5-"
++						   "cbc-des-caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha1),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha1-"
++						   "cbc-des-caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha1),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha1-cbc-des-caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha224),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha224-"
++						   "cbc-des-caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha224),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha224-cbc-des-"
++						   "caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha256),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha256-"
++						   "cbc-des-caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha256),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha256-cbc-des-"
++						   "caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha384),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha384-"
++						   "cbc-des-caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha384),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha384-cbc-des-"
++						   "caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha512),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha512-"
++						   "cbc-des-caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha512),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha512-cbc-des-"
++						   "caam-qi",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "tls10(hmac(sha1),cbc(aes))",
++				.cra_driver_name = "tls10-hmac-sha1-cbc-aes-caam-qi",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = tls_setkey,
++			.setauthsize = tls_setauthsize,
++			.encrypt = tls_encrypt,
++			.decrypt = tls_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	}
++};
++
++struct caam_crypto_alg {
++	struct list_head entry;
++	struct crypto_alg crypto_alg;
++	struct caam_alg_entry caam;
++};
++
++static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam,
++			   bool uses_dkp)
++{
++	struct caam_drv_private *priv;
++	/* Digest sizes for MD5, SHA1, SHA-224, SHA-256, SHA-384, SHA-512 */
++	static const u8 digest_size[] = {
++		MD5_DIGEST_SIZE,
++		SHA1_DIGEST_SIZE,
++		SHA224_DIGEST_SIZE,
++		SHA256_DIGEST_SIZE,
++		SHA384_DIGEST_SIZE,
++		SHA512_DIGEST_SIZE
++	};
++	u8 op_id;
++
++	/*
++	 * distribute tfms across job rings to ensure in-order
++	 * crypto request processing per tfm
++	 */
++	ctx->jrdev = caam_jr_alloc();
++	if (IS_ERR(ctx->jrdev)) {
++		pr_err("Job Ring Device allocation for transform failed\n");
++		return PTR_ERR(ctx->jrdev);
++	}
++
++	priv = dev_get_drvdata(ctx->jrdev->parent);
++	if (priv->era >= 6 && uses_dkp)
++		ctx->dir = DMA_BIDIRECTIONAL;
++	else
++		ctx->dir = DMA_TO_DEVICE;
++
++	ctx->key_dma = dma_map_single(ctx->jrdev, ctx->key, sizeof(ctx->key),
++				      ctx->dir);
++	if (dma_mapping_error(ctx->jrdev, ctx->key_dma)) {
++		dev_err(ctx->jrdev, "unable to map key\n");
++		caam_jr_free(ctx->jrdev);
++		return -ENOMEM;
++	}
++
++	/* copy descriptor header template value */
++	ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
++	ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
++
++	if (ctx->adata.algtype) {
++		op_id = (ctx->adata.algtype & OP_ALG_ALGSEL_SUBMASK)
++				>> OP_ALG_ALGSEL_SHIFT;
++		if (op_id < ARRAY_SIZE(digest_size)) {
++			ctx->authsize = digest_size[op_id];
++		} else {
++			dev_err(ctx->jrdev,
++				"incorrect op_id %d; must be less than %zu\n",
++				op_id, ARRAY_SIZE(digest_size));
++			caam_jr_free(ctx->jrdev);
++			return -EINVAL;
++		}
++	} else {
++		ctx->authsize = 0;
++	}
++
++	ctx->qidev = priv->qidev;
++
++	spin_lock_init(&ctx->lock);
++	ctx->drv_ctx[ENCRYPT] = NULL;
++	ctx->drv_ctx[DECRYPT] = NULL;
++	ctx->drv_ctx[GIVENCRYPT] = NULL;
++
++	return 0;
++}
++
++static int caam_cra_init(struct crypto_tfm *tfm)
++{
++	struct crypto_alg *alg = tfm->__crt_alg;
++	struct caam_crypto_alg *caam_alg = container_of(alg, typeof(*caam_alg),
++							crypto_alg);
++	struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
++
++	return caam_init_common(ctx, &caam_alg->caam, false);
++}
++
++static int caam_aead_init(struct crypto_aead *tfm)
++{
++	struct aead_alg *alg = crypto_aead_alg(tfm);
++	struct caam_aead_alg *caam_alg = container_of(alg, typeof(*caam_alg),
++						      aead);
++	struct caam_ctx *ctx = crypto_aead_ctx(tfm);
++
++	return caam_init_common(ctx, &caam_alg->caam,
++				(alg->setkey == aead_setkey) ||
++				(alg->setkey == tls_setkey));
++}
++
++static void caam_exit_common(struct caam_ctx *ctx)
++{
++	caam_drv_ctx_rel(ctx->drv_ctx[ENCRYPT]);
++	caam_drv_ctx_rel(ctx->drv_ctx[DECRYPT]);
++	caam_drv_ctx_rel(ctx->drv_ctx[GIVENCRYPT]);
++
++	dma_unmap_single(ctx->jrdev, ctx->key_dma, sizeof(ctx->key), ctx->dir);
++
++	caam_jr_free(ctx->jrdev);
++}
++
++static void caam_cra_exit(struct crypto_tfm *tfm)
++{
++	caam_exit_common(crypto_tfm_ctx(tfm));
++}
++
++static void caam_aead_exit(struct crypto_aead *tfm)
++{
++	caam_exit_common(crypto_aead_ctx(tfm));
++}
++
++static struct list_head alg_list;
++static void __exit caam_qi_algapi_exit(void)
++{
++	struct caam_crypto_alg *t_alg, *n;
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
++		struct caam_aead_alg *t_alg = driver_aeads + i;
++
++		if (t_alg->registered)
++			crypto_unregister_aead(&t_alg->aead);
++	}
++
++	if (!alg_list.next)
++		return;
++
++	list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
++		crypto_unregister_alg(&t_alg->crypto_alg);
++		list_del(&t_alg->entry);
++		kfree(t_alg);
++	}
++}
++
++static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
++					      *template)
++{
++	struct caam_crypto_alg *t_alg;
++	struct crypto_alg *alg;
++
++	t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
++	if (!t_alg)
++		return ERR_PTR(-ENOMEM);
++
++	alg = &t_alg->crypto_alg;
++
++	snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
++	snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
++		 template->driver_name);
++	alg->cra_module = THIS_MODULE;
++	alg->cra_init = caam_cra_init;
++	alg->cra_exit = caam_cra_exit;
++	alg->cra_priority = CAAM_CRA_PRIORITY;
++	alg->cra_blocksize = template->blocksize;
++	alg->cra_alignmask = 0;
++	alg->cra_ctxsize = sizeof(struct caam_ctx);
++	alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
++			 template->type;
++	switch (template->type) {
++	case CRYPTO_ALG_TYPE_GIVCIPHER:
++		alg->cra_type = &crypto_givcipher_type;
++		alg->cra_ablkcipher = template->template_ablkcipher;
++		break;
++	case CRYPTO_ALG_TYPE_ABLKCIPHER:
++		alg->cra_type = &crypto_ablkcipher_type;
++		alg->cra_ablkcipher = template->template_ablkcipher;
++		break;
++	}
++
++	t_alg->caam.class1_alg_type = template->class1_alg_type;
++	t_alg->caam.class2_alg_type = template->class2_alg_type;
++
++	return t_alg;
++}
++
++static void caam_aead_alg_init(struct caam_aead_alg *t_alg)
++{
++	struct aead_alg *alg = &t_alg->aead;
++
++	alg->base.cra_module = THIS_MODULE;
++	alg->base.cra_priority = CAAM_CRA_PRIORITY;
++	alg->base.cra_ctxsize = sizeof(struct caam_ctx);
++	alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
++
++	alg->init = caam_aead_init;
++	alg->exit = caam_aead_exit;
++}
++
++static int __init caam_qi_algapi_init(void)
++{
++	struct device_node *dev_node;
++	struct platform_device *pdev;
++	struct device *ctrldev;
++	struct caam_drv_private *priv;
++	int i = 0, err = 0;
++	u32 cha_vid, cha_inst, des_inst, aes_inst, md_inst;
++	unsigned int md_limit = SHA512_DIGEST_SIZE;
++	bool registered = false;
++
++	dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++	if (!dev_node) {
++		dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++		if (!dev_node)
++			return -ENODEV;
++	}
++
++	pdev = of_find_device_by_node(dev_node);
++	of_node_put(dev_node);
++	if (!pdev)
++		return -ENODEV;
++
++	ctrldev = &pdev->dev;
++	priv = dev_get_drvdata(ctrldev);
++
++	/*
++	 * If priv is NULL, it's probably because the caam driver wasn't
++	 * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
++	 */
++	if (!priv || !priv->qi_present)
++		return -ENODEV;
++
++	if (caam_dpaa2) {
++		dev_info(ctrldev, "caam/qi frontend driver not suitable for DPAA 2.x, aborting...\n");
++		return -ENODEV;
++	}
++
++	INIT_LIST_HEAD(&alg_list);
++
++	/*
++	 * Register crypto algorithms the device supports.
++	 * First, detect presence and attributes of DES, AES, and MD blocks.
++	 */
++	cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
++	cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
++	des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT;
++	aes_inst = (cha_inst & CHA_ID_LS_AES_MASK) >> CHA_ID_LS_AES_SHIFT;
++	md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
++
++	/* If MD is present, limit digest size based on LP256 */
++	if (md_inst && ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256))
++		md_limit = SHA256_DIGEST_SIZE;
++
++	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
++		struct caam_crypto_alg *t_alg;
++		struct caam_alg_template *alg = driver_algs + i;
++		u32 alg_sel = alg->class1_alg_type & OP_ALG_ALGSEL_MASK;
++
++		/* Skip DES algorithms if not supported by device */
++		if (!des_inst &&
++		    ((alg_sel == OP_ALG_ALGSEL_3DES) ||
++		     (alg_sel == OP_ALG_ALGSEL_DES)))
++			continue;
++
++		/* Skip AES algorithms if not supported by device */
++		if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES))
++			continue;
++
++		t_alg = caam_alg_alloc(alg);
++		if (IS_ERR(t_alg)) {
++			err = PTR_ERR(t_alg);
++			dev_warn(priv->qidev, "%s alg allocation failed\n",
++				 alg->driver_name);
++			continue;
++		}
++
++		err = crypto_register_alg(&t_alg->crypto_alg);
++		if (err) {
++			dev_warn(priv->qidev, "%s alg registration failed\n",
++				 t_alg->crypto_alg.cra_driver_name);
++			kfree(t_alg);
++			continue;
++		}
++
++		list_add_tail(&t_alg->entry, &alg_list);
++		registered = true;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
++		struct caam_aead_alg *t_alg = driver_aeads + i;
++		u32 c1_alg_sel = t_alg->caam.class1_alg_type &
++				 OP_ALG_ALGSEL_MASK;
++		u32 c2_alg_sel = t_alg->caam.class2_alg_type &
++				 OP_ALG_ALGSEL_MASK;
++		u32 alg_aai = t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
++
++		/* Skip DES algorithms if not supported by device */
++		if (!des_inst &&
++		    ((c1_alg_sel == OP_ALG_ALGSEL_3DES) ||
++		     (c1_alg_sel == OP_ALG_ALGSEL_DES)))
++			continue;
++
++		/* Skip AES algorithms if not supported by device */
++		if (!aes_inst && (c1_alg_sel == OP_ALG_ALGSEL_AES))
++			continue;
++
++		/*
++		 * Check support for AES algorithms not available
++		 * on LP devices.
++		 */
++		if (((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP) &&
++		    (alg_aai == OP_ALG_AAI_GCM))
++			continue;
++
++		/*
++		 * Skip algorithms requiring message digests
++		 * if MD or MD size is not supported by device.
++		 */
++		if (c2_alg_sel &&
++		    (!md_inst || (t_alg->aead.maxauthsize > md_limit)))
++			continue;
++
++		caam_aead_alg_init(t_alg);
++
++		err = crypto_register_aead(&t_alg->aead);
++		if (err) {
++			pr_warn("%s alg registration failed\n",
++				t_alg->aead.base.cra_driver_name);
++			continue;
++		}
++
++		t_alg->registered = true;
++		registered = true;
++	}
++
++	if (registered)
++		dev_info(priv->qidev, "algorithms registered in /proc/crypto\n");
++
++	return err;
++}
++
++module_init(caam_qi_algapi_init);
++module_exit(caam_qi_algapi_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Support for crypto API using CAAM-QI backend");
++MODULE_AUTHOR("Freescale Semiconductor");
+--- /dev/null
++++ b/drivers/crypto/caam/caamalg_qi2.c
+@@ -0,0 +1,5938 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the names of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/fsl/mc.h>
++#include "compat.h"
++#include "regs.h"
++#include "caamalg_qi2.h"
++#include "dpseci_cmd.h"
++#include "desc_constr.h"
++#include "error.h"
++#include "sg_sw_sec4.h"
++#include "sg_sw_qm2.h"
++#include "key_gen.h"
++#include "caamalg_desc.h"
++#include "caamhash_desc.h"
++#include "../../../drivers/staging/fsl-mc/include/dpaa2-io.h"
++#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
++
++#define CAAM_CRA_PRIORITY	2000
++
++/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
++#define CAAM_MAX_KEY_SIZE	(AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE + \
++				 SHA512_DIGEST_SIZE * 2)
++
++#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM
++bool caam_little_end;
++EXPORT_SYMBOL(caam_little_end);
++bool caam_imx;
++EXPORT_SYMBOL(caam_imx);
++#endif
++
++/*
++ * This is a a cache of buffers, from which the users of CAAM QI driver
++ * can allocate short buffers. It's speedier than doing kmalloc on the hotpath.
++ * NOTE: A more elegant solution would be to have some headroom in the frames
++ *       being processed. This can be added by the dpaa2-eth driver. This would
++ *       pose a problem for userspace application processing which cannot
++ *       know of this limitation. So for now, this will work.
++ * NOTE: The memcache is SMP-safe. No need to handle spinlocks in-here
++ */
++static struct kmem_cache *qi_cache;
++
++struct caam_alg_entry {
++	struct device *dev;
++	int class1_alg_type;
++	int class2_alg_type;
++	bool rfc3686;
++	bool geniv;
++};
++
++struct caam_aead_alg {
++	struct aead_alg aead;
++	struct caam_alg_entry caam;
++	bool registered;
++};
++
++/**
++ * caam_ctx - per-session context
++ * @flc: Flow Contexts array
++ * @key:  virtual address of the key(s): [authentication key], encryption key
++ * @flc_dma: I/O virtual addresses of the Flow Contexts
++ * @key_dma: I/O virtual address of the key
++ * @dir: DMA direction for mapping key and Flow Contexts
++ * @dev: dpseci device
++ * @adata: authentication algorithm details
++ * @cdata: encryption algorithm details
++ * @authsize: authentication tag (a.k.a. ICV / MAC) size
++ */
++struct caam_ctx {
++	struct caam_flc flc[NUM_OP];
++	u8 key[CAAM_MAX_KEY_SIZE];
++	dma_addr_t flc_dma[NUM_OP];
++	dma_addr_t key_dma;
++	enum dma_data_direction dir;
++	struct device *dev;
++	struct alginfo adata;
++	struct alginfo cdata;
++	unsigned int authsize;
++};
++
++void *dpaa2_caam_iova_to_virt(struct dpaa2_caam_priv *priv,
++			      dma_addr_t iova_addr)
++{
++	phys_addr_t phys_addr;
++
++	phys_addr = priv->domain ? iommu_iova_to_phys(priv->domain, iova_addr) :
++				   iova_addr;
++
++	return phys_to_virt(phys_addr);
++}
++
++/*
++ * qi_cache_zalloc - Allocate buffers from CAAM-QI cache
++ *
++ * Allocate data on the hotpath. Instead of using kzalloc, one can use the
++ * services of the CAAM QI memory cache (backed by kmem_cache). The buffers
++ * will have a size of CAAM_QI_MEMCACHE_SIZE, which should be sufficient for
++ * hosting 16 SG entries.
++ *
++ * @flags - flags that would be used for the equivalent kmalloc(..) call
++ *
++ * Returns a pointer to a retrieved buffer on success or NULL on failure.
++ */
++static inline void *qi_cache_zalloc(gfp_t flags)
++{
++	return kmem_cache_zalloc(qi_cache, flags);
++}
++
++/*
++ * qi_cache_free - Frees buffers allocated from CAAM-QI cache
++ *
++ * @obj - buffer previously allocated by qi_cache_zalloc
++ *
++ * No checking is being done, the call is a passthrough call to
++ * kmem_cache_free(...)
++ */
++static inline void qi_cache_free(void *obj)
++{
++	kmem_cache_free(qi_cache, obj);
++}
++
++static struct caam_request *to_caam_req(struct crypto_async_request *areq)
++{
++	switch (crypto_tfm_alg_type(areq->tfm)) {
++	case CRYPTO_ALG_TYPE_ABLKCIPHER:
++	case CRYPTO_ALG_TYPE_GIVCIPHER:
++		return ablkcipher_request_ctx(ablkcipher_request_cast(areq));
++	case CRYPTO_ALG_TYPE_AEAD:
++		return aead_request_ctx(container_of(areq, struct aead_request,
++						     base));
++	case CRYPTO_ALG_TYPE_AHASH:
++		return ahash_request_ctx(ahash_request_cast(areq));
++	default:
++		return ERR_PTR(-EINVAL);
++	}
++}
++
++static void caam_unmap(struct device *dev, struct scatterlist *src,
++		       struct scatterlist *dst, int src_nents,
++		       int dst_nents, dma_addr_t iv_dma, int ivsize,
++		       enum optype op_type, dma_addr_t qm_sg_dma,
++		       int qm_sg_bytes)
++{
++	if (dst != src) {
++		if (src_nents)
++			dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
++		dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
++	} else {
++		dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
++	}
++
++	if (iv_dma)
++		dma_unmap_single(dev, iv_dma, ivsize,
++				 op_type == GIVENCRYPT ? DMA_FROM_DEVICE :
++							 DMA_TO_DEVICE);
++
++	if (qm_sg_bytes)
++		dma_unmap_single(dev, qm_sg_dma, qm_sg_bytes, DMA_TO_DEVICE);
++}
++
++static int aead_set_sh_desc(struct crypto_aead *aead)
++{
++	struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
++						 typeof(*alg), aead);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	unsigned int ivsize = crypto_aead_ivsize(aead);
++	struct device *dev = ctx->dev;
++	struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
++	struct caam_flc *flc;
++	u32 *desc;
++	u32 ctx1_iv_off = 0;
++	u32 *nonce = NULL;
++	unsigned int data_len[2];
++	u32 inl_mask;
++	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
++			       OP_ALG_AAI_CTR_MOD128);
++	const bool is_rfc3686 = alg->caam.rfc3686;
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	/*
++	 * AES-CTR needs to load IV in CONTEXT1 reg
++	 * at an offset of 128bits (16bytes)
++	 * CONTEXT1[255:128] = IV
++	 */
++	if (ctr_mode)
++		ctx1_iv_off = 16;
++
++	/*
++	 * RFC3686 specific:
++	 *	CONTEXT1[255:128] = {NONCE, IV, COUNTER}
++	 */
++	if (is_rfc3686) {
++		ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
++		nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
++				ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
++	}
++
++	data_len[0] = ctx->adata.keylen_pad;
++	data_len[1] = ctx->cdata.keylen;
++
++	/* aead_encrypt shared descriptor */
++	if (desc_inline_query((alg->caam.geniv ? DESC_QI_AEAD_GIVENC_LEN :
++						 DESC_QI_AEAD_ENC_LEN) +
++			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
++			      DESC_JOB_IO_LEN, data_len, &inl_mask,
++			      ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
++
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
++
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
++
++	flc = &ctx->flc[ENCRYPT];
++	desc = flc->sh_desc;
++
++	if (alg->caam.geniv)
++		cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata,
++					  ivsize, ctx->authsize, is_rfc3686,
++					  nonce, ctx1_iv_off, true,
++					  priv->sec_attr.era);
++	else
++		cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata,
++				       ivsize, ctx->authsize, is_rfc3686, nonce,
++				       ctx1_iv_off, true, priv->sec_attr.era);
++
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	/* aead_decrypt shared descriptor */
++	if (desc_inline_query(DESC_QI_AEAD_DEC_LEN +
++			      (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
++			      DESC_JOB_IO_LEN, data_len, &inl_mask,
++			      ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
++
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
++
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
++
++	flc = &ctx->flc[DECRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata,
++			       ivsize, ctx->authsize, alg->caam.geniv,
++			       is_rfc3686, nonce, ctx1_iv_off, true,
++			       priv->sec_attr.era);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	return 0;
++}
++
++static int aead_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
++
++	ctx->authsize = authsize;
++	aead_set_sh_desc(authenc);
++
++	return 0;
++}
++
++struct split_key_sh_result {
++	struct completion completion;
++	int err;
++	struct device *dev;
++};
++
++static void split_key_sh_done(void *cbk_ctx, u32 err)
++{
++	struct split_key_sh_result *res = cbk_ctx;
++
++#ifdef DEBUG
++	dev_err(res->dev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
++#endif
++
++	if (err)
++		caam_qi2_strstatus(res->dev, err);
++
++	res->err = err;
++	complete(&res->completion);
++}
++
++static int aead_setkey(struct crypto_aead *aead, const u8 *key,
++		       unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *dev = ctx->dev;
++	struct crypto_authenc_keys keys;
++
++	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
++		goto badkey;
++
++#ifdef DEBUG
++	dev_err(dev, "keylen %d enckeylen %d authkeylen %d\n",
++		keys.authkeylen + keys.enckeylen, keys.enckeylen,
++		keys.authkeylen);
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	ctx->adata.keylen = keys.authkeylen;
++	ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
++					      OP_ALG_ALGSEL_MASK);
++
++	if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
++		goto badkey;
++
++	memcpy(ctx->key, keys.authkey, keys.authkeylen);
++	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
++	dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad +
++				   keys.enckeylen, ctx->dir);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
++		       ctx->adata.keylen_pad + keys.enckeylen, 1);
++#endif
++
++	ctx->cdata.keylen = keys.enckeylen;
++
++	return aead_set_sh_desc(aead);
++badkey:
++	crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
++	return -EINVAL;
++}
++
++static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
++					   bool encrypt)
++{
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_request *req_ctx = aead_request_ctx(req);
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
++						 typeof(*alg), aead);
++	struct device *dev = ctx->dev;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
++	struct aead_edesc *edesc;
++	dma_addr_t qm_sg_dma, iv_dma = 0;
++	int ivsize = 0;
++	unsigned int authsize = ctx->authsize;
++	int qm_sg_index = 0, qm_sg_nents = 0, qm_sg_bytes;
++	int in_len, out_len;
++	struct dpaa2_sg_entry *sg_table;
++	enum optype op_type = encrypt ? ENCRYPT : DECRYPT;
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (unlikely(!edesc)) {
++		dev_err(dev, "could not allocate extended descriptor\n");
++		return ERR_PTR(-ENOMEM);
++	}
++
++	if (unlikely(req->dst != req->src)) {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen);
++		if (unlikely(src_nents < 0)) {
++			dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen);
++			qi_cache_free(edesc);
++			return ERR_PTR(src_nents);
++		}
++
++		dst_nents = sg_nents_for_len(req->dst, req->assoclen +
++					     req->cryptlen +
++					     (encrypt ? authsize :
++							(-authsize)));
++		if (unlikely(dst_nents < 0)) {
++			dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
++				req->assoclen + req->cryptlen +
++				(encrypt ? authsize : (-authsize)));
++			qi_cache_free(edesc);
++			return ERR_PTR(dst_nents);
++		}
++
++		if (src_nents) {
++			mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
++						      DMA_TO_DEVICE);
++			if (unlikely(!mapped_src_nents)) {
++				dev_err(dev, "unable to map source\n");
++				qi_cache_free(edesc);
++				return ERR_PTR(-ENOMEM);
++			}
++		} else {
++			mapped_src_nents = 0;
++		}
++
++		mapped_dst_nents = dma_map_sg(dev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(dev, "unable to map destination\n");
++			dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE);
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++	} else {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen +
++						(encrypt ? authsize : 0));
++		if (unlikely(src_nents < 0)) {
++			dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen +
++				(encrypt ? authsize : 0));
++			qi_cache_free(edesc);
++			return ERR_PTR(src_nents);
++		}
++
++		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(dev, "unable to map source\n");
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++
++	if ((alg->caam.rfc3686 && encrypt) || !alg->caam.geniv) {
++		ivsize = crypto_aead_ivsize(aead);
++		iv_dma = dma_map_single(dev, req->iv, ivsize, DMA_TO_DEVICE);
++		if (dma_mapping_error(dev, iv_dma)) {
++			dev_err(dev, "unable to map IV\n");
++			caam_unmap(dev, req->src, req->dst, src_nents,
++				   dst_nents, 0, 0, op_type, 0, 0);
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++
++	/*
++	 * Create S/G table: req->assoclen, [IV,] req->src [, req->dst].
++	 * Input is not contiguous.
++	 */
++	qm_sg_nents = 1 + !!ivsize + mapped_src_nents +
++		      (mapped_dst_nents > 1 ? mapped_dst_nents : 0);
++	if (unlikely(qm_sg_nents > CAAM_QI_MAX_AEAD_SG)) {
++		dev_err(dev, "Insufficient S/G entries: %d > %lu\n",
++			qm_sg_nents, CAAM_QI_MAX_AEAD_SG);
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++	sg_table = &edesc->sgt[0];
++	qm_sg_bytes = qm_sg_nents * sizeof(*sg_table);
++
++	edesc->src_nents = src_nents;
++	edesc->dst_nents = dst_nents;
++	edesc->iv_dma = iv_dma;
++
++	edesc->assoclen = cpu_to_caam32(req->assoclen);
++	edesc->assoclen_dma = dma_map_single(dev, &edesc->assoclen, 4,
++					     DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, edesc->assoclen_dma)) {
++		dev_err(dev, "unable to map assoclen\n");
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	dma_to_qm_sg_one(sg_table, edesc->assoclen_dma, 4, 0);
++	qm_sg_index++;
++	if (ivsize) {
++		dma_to_qm_sg_one(sg_table + qm_sg_index, iv_dma, ivsize, 0);
++		qm_sg_index++;
++	}
++	sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0);
++	qm_sg_index += mapped_src_nents;
++
++	if (mapped_dst_nents > 1)
++		sg_to_qm_sg_last(req->dst, mapped_dst_nents, sg_table +
++				 qm_sg_index, 0);
++
++	qm_sg_dma = dma_map_single(dev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, qm_sg_dma)) {
++		dev_err(dev, "unable to map S/G table\n");
++		dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->qm_sg_dma = qm_sg_dma;
++	edesc->qm_sg_bytes = qm_sg_bytes;
++
++	out_len = req->assoclen + req->cryptlen +
++		  (encrypt ? ctx->authsize : (-ctx->authsize));
++	in_len = 4 + ivsize + req->assoclen + req->cryptlen;
++
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++	dpaa2_fl_set_addr(in_fle, qm_sg_dma);
++	dpaa2_fl_set_len(in_fle, in_len);
++
++	if (req->dst == req->src) {
++		if (mapped_src_nents == 1) {
++			dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++			dpaa2_fl_set_addr(out_fle, sg_dma_address(req->src));
++		} else {
++			dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
++			dpaa2_fl_set_addr(out_fle, qm_sg_dma +
++					  (1 + !!ivsize) * sizeof(*sg_table));
++		}
++	} else if (mapped_dst_nents == 1) {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(out_fle, sg_dma_address(req->dst));
++	} else {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(out_fle, qm_sg_dma + qm_sg_index *
++				  sizeof(*sg_table));
++	}
++
++	dpaa2_fl_set_len(out_fle, out_len);
++
++	return edesc;
++}
++
++static struct tls_edesc *tls_edesc_alloc(struct aead_request *req,
++					 bool encrypt)
++{
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	unsigned int blocksize = crypto_aead_blocksize(tls);
++	unsigned int padsize, authsize;
++	struct caam_request *req_ctx = aead_request_ctx(req);
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	struct caam_aead_alg *alg = container_of(crypto_aead_alg(tls),
++						 typeof(*alg), aead);
++	struct device *dev = ctx->dev;
++	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
++		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
++	struct tls_edesc *edesc;
++	dma_addr_t qm_sg_dma, iv_dma = 0;
++	int ivsize = 0;
++	int qm_sg_index, qm_sg_ents = 0, qm_sg_bytes;
++	int in_len, out_len;
++	struct dpaa2_sg_entry *sg_table;
++	enum optype op_type = encrypt ? ENCRYPT : DECRYPT;
++	struct scatterlist *dst;
++
++	if (encrypt) {
++		padsize = blocksize - ((req->cryptlen + ctx->authsize) %
++					blocksize);
++		authsize = ctx->authsize + padsize;
++	} else {
++		authsize = ctx->authsize;
++	}
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (unlikely(!edesc)) {
++		dev_err(dev, "could not allocate extended descriptor\n");
++		return ERR_PTR(-ENOMEM);
++	}
++
++	if (likely(req->src == req->dst)) {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen +
++					     (encrypt ? authsize : 0));
++		if (unlikely(src_nents < 0)) {
++			dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen +
++				(encrypt ? authsize : 0));
++			qi_cache_free(edesc);
++			return ERR_PTR(src_nents);
++		}
++
++		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(dev, "unable to map source\n");
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++		dst = req->dst;
++	} else {
++		src_nents = sg_nents_for_len(req->src, req->assoclen +
++					     req->cryptlen);
++		if (unlikely(src_nents < 0)) {
++			dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
++				req->assoclen + req->cryptlen);
++			qi_cache_free(edesc);
++			return ERR_PTR(src_nents);
++		}
++
++		dst = scatterwalk_ffwd(edesc->tmp, req->dst, req->assoclen);
++		dst_nents = sg_nents_for_len(dst, req->cryptlen +
++					     (encrypt ? authsize : 0));
++		if (unlikely(dst_nents < 0)) {
++			dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
++				req->cryptlen +
++				(encrypt ? authsize : 0));
++			qi_cache_free(edesc);
++			return ERR_PTR(dst_nents);
++		}
++
++		if (src_nents) {
++			mapped_src_nents = dma_map_sg(dev, req->src,
++						      src_nents, DMA_TO_DEVICE);
++			if (unlikely(!mapped_src_nents)) {
++				dev_err(dev, "unable to map source\n");
++				qi_cache_free(edesc);
++				return ERR_PTR(-ENOMEM);
++			}
++		} else {
++			mapped_src_nents = 0;
++		}
++
++		mapped_dst_nents = dma_map_sg(dev, dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(dev, "unable to map destination\n");
++			dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE);
++			qi_cache_free(edesc);
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++
++	ivsize = crypto_aead_ivsize(tls);
++	iv_dma = dma_map_single(dev, req->iv, ivsize, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, iv_dma)) {
++		dev_err(dev, "unable to map IV\n");
++		caam_unmap(dev, req->src, dst, src_nents, dst_nents, 0, 0,
++			   op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/*
++	 * Create S/G table: IV, src, dst.
++	 * Input is not contiguous.
++	 */
++	qm_sg_ents = 1 + mapped_src_nents +
++		     (mapped_dst_nents > 1 ? mapped_dst_nents : 0);
++	sg_table = &edesc->sgt[0];
++	qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
++
++	edesc->src_nents = src_nents;
++	edesc->dst_nents = dst_nents;
++	edesc->dst = dst;
++	edesc->iv_dma = iv_dma;
++
++	dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
++	qm_sg_index = 1;
++
++	sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + qm_sg_index, 0);
++	qm_sg_index += mapped_src_nents;
++
++	if (mapped_dst_nents > 1)
++		sg_to_qm_sg_last(dst, mapped_dst_nents, sg_table +
++				 qm_sg_index, 0);
++
++	qm_sg_dma = dma_map_single(dev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, qm_sg_dma)) {
++		dev_err(dev, "unable to map S/G table\n");
++		caam_unmap(dev, req->src, dst, src_nents, dst_nents, iv_dma,
++			   ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->qm_sg_dma = qm_sg_dma;
++	edesc->qm_sg_bytes = qm_sg_bytes;
++
++	out_len = req->cryptlen + (encrypt ? authsize : 0);
++	in_len = ivsize + req->assoclen + req->cryptlen;
++
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++	dpaa2_fl_set_addr(in_fle, qm_sg_dma);
++	dpaa2_fl_set_len(in_fle, in_len);
++
++	if (req->dst == req->src) {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(out_fle, qm_sg_dma +
++				  (sg_nents_for_len(req->src, req->assoclen) +
++				   1) * sizeof(*sg_table));
++	} else if (mapped_dst_nents == 1) {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(out_fle, sg_dma_address(dst));
++	} else {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(out_fle, qm_sg_dma + qm_sg_index *
++				  sizeof(*sg_table));
++	}
++
++	dpaa2_fl_set_len(out_fle, out_len);
++
++	return edesc;
++}
++
++static int tls_set_sh_desc(struct crypto_aead *tls)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	unsigned int ivsize = crypto_aead_ivsize(tls);
++	unsigned int blocksize = crypto_aead_blocksize(tls);
++	struct device *dev = ctx->dev;
++	struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
++	struct caam_flc *flc;
++	u32 *desc;
++	unsigned int assoclen = 13; /* always 13 bytes for TLS */
++	unsigned int data_len[2];
++	u32 inl_mask;
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	/*
++	 * TLS 1.0 encrypt shared descriptor
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	data_len[0] = ctx->adata.keylen_pad;
++	data_len[1] = ctx->cdata.keylen;
++
++	if (desc_inline_query(DESC_TLS10_ENC_LEN, DESC_JOB_IO_LEN, data_len,
++			      &inl_mask, ARRAY_SIZE(data_len)) < 0)
++		return -EINVAL;
++
++	if (inl_mask & 1)
++		ctx->adata.key_virt = ctx->key;
++	else
++		ctx->adata.key_dma = ctx->key_dma;
++
++	if (inl_mask & 2)
++		ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
++	else
++		ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	ctx->adata.key_inline = !!(inl_mask & 1);
++	ctx->cdata.key_inline = !!(inl_mask & 2);
++
++	flc = &ctx->flc[ENCRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_tls_encap(desc, &ctx->cdata, &ctx->adata,
++			      assoclen, ivsize, ctx->authsize, blocksize,
++			      priv->sec_attr.era);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc));
++	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	/*
++	 * TLS 1.0 decrypt shared descriptor
++	 * Keys do not fit inline, regardless of algorithms used
++	 */
++	ctx->adata.key_inline = false;
++	ctx->adata.key_dma = ctx->key_dma;
++	ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
++
++	flc = &ctx->flc[DECRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_tls_decap(desc, &ctx->cdata, &ctx->adata, assoclen, ivsize,
++			      ctx->authsize, blocksize, priv->sec_attr.era);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	return 0;
++}
++
++static int tls_setkey(struct crypto_aead *tls, const u8 *key,
++		      unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	struct device *dev = ctx->dev;
++	struct crypto_authenc_keys keys;
++
++	if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
++		goto badkey;
++
++#ifdef DEBUG
++	dev_err(dev, "keylen %d enckeylen %d authkeylen %d\n",
++		keys.authkeylen + keys.enckeylen, keys.enckeylen,
++		keys.authkeylen);
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	ctx->adata.keylen = keys.authkeylen;
++	ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
++					      OP_ALG_ALGSEL_MASK);
++
++	if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
++		goto badkey;
++
++	memcpy(ctx->key, keys.authkey, keys.authkeylen);
++	memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
++	dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad +
++				   keys.enckeylen, ctx->dir);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
++		       ctx->adata.keylen_pad + keys.enckeylen, 1);
++#endif
++
++	ctx->cdata.keylen = keys.enckeylen;
++
++	return tls_set_sh_desc(tls);
++badkey:
++	crypto_aead_set_flags(tls, CRYPTO_TFM_RES_BAD_KEY_LEN);
++	return -EINVAL;
++}
++
++static int tls_setauthsize(struct crypto_aead *tls, unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++
++	ctx->authsize = authsize;
++	tls_set_sh_desc(tls);
++
++	return 0;
++}
++
++static int gcm_set_sh_desc(struct crypto_aead *aead)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *dev = ctx->dev;
++	unsigned int ivsize = crypto_aead_ivsize(aead);
++	struct caam_flc *flc;
++	u32 *desc;
++	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	/*
++	 * AES GCM encrypt shared descriptor
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_GCM_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	flc = &ctx->flc[ENCRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ivsize, ctx->authsize, true);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	/*
++	 * Job Descriptor and Shared Descriptors
++	 * must all fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_GCM_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++		ctx->cdata.key_virt = ctx->key;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	flc = &ctx->flc[DECRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ivsize, ctx->authsize, true);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	return 0;
++}
++
++static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
++
++	ctx->authsize = authsize;
++	gcm_set_sh_desc(authenc);
++
++	return 0;
++}
++
++static int gcm_setkey(struct crypto_aead *aead,
++		      const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *dev = ctx->dev;
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	memcpy(ctx->key, key, keylen);
++	dma_sync_single_for_device(dev, ctx->key_dma, keylen, ctx->dir);
++	ctx->cdata.keylen = keylen;
++
++	return gcm_set_sh_desc(aead);
++}
++
++static int rfc4106_set_sh_desc(struct crypto_aead *aead)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *dev = ctx->dev;
++	unsigned int ivsize = crypto_aead_ivsize(aead);
++	struct caam_flc *flc;
++	u32 *desc;
++	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	ctx->cdata.key_virt = ctx->key;
++
++	/*
++	 * RFC4106 encrypt shared descriptor
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_RFC4106_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	flc = &ctx->flc[ENCRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
++				  true);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	/*
++	 * Job Descriptor and Shared Descriptors
++	 * must all fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_RFC4106_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	flc = &ctx->flc[DECRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
++				  true);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	return 0;
++}
++
++static int rfc4106_setauthsize(struct crypto_aead *authenc,
++			       unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
++
++	ctx->authsize = authsize;
++	rfc4106_set_sh_desc(authenc);
++
++	return 0;
++}
++
++static int rfc4106_setkey(struct crypto_aead *aead,
++			  const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *dev = ctx->dev;
++
++	if (keylen < 4)
++		return -EINVAL;
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	memcpy(ctx->key, key, keylen);
++	/*
++	 * The last four bytes of the key material are used as the salt value
++	 * in the nonce. Update the AES key length.
++	 */
++	ctx->cdata.keylen = keylen - 4;
++	dma_sync_single_for_device(dev, ctx->key_dma, ctx->cdata.keylen,
++				   ctx->dir);
++
++	return rfc4106_set_sh_desc(aead);
++}
++
++static int rfc4543_set_sh_desc(struct crypto_aead *aead)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *dev = ctx->dev;
++	unsigned int ivsize = crypto_aead_ivsize(aead);
++	struct caam_flc *flc;
++	u32 *desc;
++	int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
++			ctx->cdata.keylen;
++
++	if (!ctx->cdata.keylen || !ctx->authsize)
++		return 0;
++
++	ctx->cdata.key_virt = ctx->key;
++
++	/*
++	 * RFC4543 encrypt shared descriptor
++	 * Job Descriptor and Shared Descriptor
++	 * must fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_RFC4543_ENC_LEN) {
++		ctx->cdata.key_inline = true;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	flc = &ctx->flc[ENCRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
++				  true);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	/*
++	 * Job Descriptor and Shared Descriptors
++	 * must all fit into the 64-word Descriptor h/w Buffer
++	 */
++	if (rem_bytes >= DESC_QI_RFC4543_DEC_LEN) {
++		ctx->cdata.key_inline = true;
++	} else {
++		ctx->cdata.key_inline = false;
++		ctx->cdata.key_dma = ctx->key_dma;
++	}
++
++	flc = &ctx->flc[DECRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
++				  true);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	return 0;
++}
++
++static int rfc4543_setauthsize(struct crypto_aead *authenc,
++			       unsigned int authsize)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(authenc);
++
++	ctx->authsize = authsize;
++	rfc4543_set_sh_desc(authenc);
++
++	return 0;
++}
++
++static int rfc4543_setkey(struct crypto_aead *aead,
++			  const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct device *dev = ctx->dev;
++
++	if (keylen < 4)
++		return -EINVAL;
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++
++	memcpy(ctx->key, key, keylen);
++	/*
++	 * The last four bytes of the key material are used as the salt value
++	 * in the nonce. Update the AES key length.
++	 */
++	ctx->cdata.keylen = keylen - 4;
++	dma_sync_single_for_device(dev, ctx->key_dma, ctx->cdata.keylen,
++				   ctx->dir);
++
++	return rfc4543_set_sh_desc(aead);
++}
++
++static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
++			     const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablkcipher);
++	const char *alg_name = crypto_tfm_alg_name(tfm);
++	struct device *dev = ctx->dev;
++	struct caam_flc *flc;
++	unsigned int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++	u32 *desc;
++	u32 ctx1_iv_off = 0;
++	const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
++			       OP_ALG_AAI_CTR_MOD128);
++	const bool is_rfc3686 = (ctr_mode && strstr(alg_name, "rfc3686"));
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key in @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
++#endif
++	/*
++	 * AES-CTR needs to load IV in CONTEXT1 reg
++	 * at an offset of 128bits (16bytes)
++	 * CONTEXT1[255:128] = IV
++	 */
++	if (ctr_mode)
++		ctx1_iv_off = 16;
++
++	/*
++	 * RFC3686 specific:
++	 *	| CONTEXT1[255:128] = {NONCE, IV, COUNTER}
++	 *	| *key = {KEY, NONCE}
++	 */
++	if (is_rfc3686) {
++		ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
++		keylen -= CTR_RFC3686_NONCE_SIZE;
++	}
++
++	ctx->cdata.keylen = keylen;
++	ctx->cdata.key_virt = key;
++	ctx->cdata.key_inline = true;
++
++	/* ablkcipher_encrypt shared descriptor */
++	flc = &ctx->flc[ENCRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_ablkcipher_encap(desc, &ctx->cdata, ivsize,
++				     is_rfc3686, ctx1_iv_off);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	/* ablkcipher_decrypt shared descriptor */
++	flc = &ctx->flc[DECRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_ablkcipher_decap(desc, &ctx->cdata, ivsize,
++				     is_rfc3686, ctx1_iv_off);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	/* ablkcipher_givencrypt shared descriptor */
++	flc = &ctx->flc[GIVENCRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_ablkcipher_givencap(desc, &ctx->cdata,
++					ivsize, is_rfc3686, ctx1_iv_off);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[GIVENCRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	return 0;
++}
++
++static int xts_ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
++				 const u8 *key, unsigned int keylen)
++{
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct device *dev = ctx->dev;
++	struct caam_flc *flc;
++	u32 *desc;
++
++	if (keylen != 2 * AES_MIN_KEY_SIZE  && keylen != 2 * AES_MAX_KEY_SIZE) {
++		dev_err(dev, "key size mismatch\n");
++		crypto_ablkcipher_set_flags(ablkcipher,
++					    CRYPTO_TFM_RES_BAD_KEY_LEN);
++		return -EINVAL;
++	}
++
++	ctx->cdata.keylen = keylen;
++	ctx->cdata.key_virt = key;
++	ctx->cdata.key_inline = true;
++
++	/* xts_ablkcipher_encrypt shared descriptor */
++	flc = &ctx->flc[ENCRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_xts_ablkcipher_encap(desc, &ctx->cdata);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	/* xts_ablkcipher_decrypt shared descriptor */
++	flc = &ctx->flc[DECRYPT];
++	desc = flc->sh_desc;
++	cnstr_shdsc_xts_ablkcipher_decap(desc, &ctx->cdata);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
++				   sizeof(flc->flc) + desc_bytes(desc),
++				   ctx->dir);
++
++	return 0;
++}
++
++static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
++						       *req, bool encrypt)
++{
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_request *req_ctx = ablkcipher_request_ctx(req);
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct device *dev = ctx->dev;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
++	struct ablkcipher_edesc *edesc;
++	dma_addr_t iv_dma;
++	bool in_contig;
++	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++	int dst_sg_idx, qm_sg_ents;
++	struct dpaa2_sg_entry *sg_table;
++	enum optype op_type = encrypt ? ENCRYPT : DECRYPT;
++
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (unlikely(src_nents < 0)) {
++		dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
++			req->nbytes);
++		return ERR_PTR(src_nents);
++	}
++
++	if (unlikely(req->dst != req->src)) {
++		dst_nents = sg_nents_for_len(req->dst, req->nbytes);
++		if (unlikely(dst_nents < 0)) {
++			dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
++				req->nbytes);
++			return ERR_PTR(dst_nents);
++		}
++
++		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
++					      DMA_TO_DEVICE);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(dev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		mapped_dst_nents = dma_map_sg(dev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(dev, "unable to map destination\n");
++			dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE);
++			return ERR_PTR(-ENOMEM);
++		}
++	} else {
++		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(dev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++	}
++
++	iv_dma = dma_map_single(dev, req->info, ivsize, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, iv_dma)) {
++		dev_err(dev, "unable to map IV\n");
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
++			   0, 0, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	if (mapped_src_nents == 1 &&
++	    iv_dma + ivsize == sg_dma_address(req->src)) {
++		in_contig = true;
++		qm_sg_ents = 0;
++	} else {
++		in_contig = false;
++		qm_sg_ents = 1 + mapped_src_nents;
++	}
++	dst_sg_idx = qm_sg_ents;
++
++	qm_sg_ents += mapped_dst_nents > 1 ? mapped_dst_nents : 0;
++	if (unlikely(qm_sg_ents > CAAM_QI_MAX_ABLKCIPHER_SG)) {
++		dev_err(dev, "Insufficient S/G entries: %d > %lu\n",
++			qm_sg_ents, CAAM_QI_MAX_ABLKCIPHER_SG);
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (unlikely(!edesc)) {
++		dev_err(dev, "could not allocate extended descriptor\n");
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->src_nents = src_nents;
++	edesc->dst_nents = dst_nents;
++	edesc->iv_dma = iv_dma;
++	sg_table = &edesc->sgt[0];
++	edesc->qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
++
++	if (!in_contig) {
++		dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
++		sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table + 1, 0);
++	}
++
++	if (mapped_dst_nents > 1)
++		sg_to_qm_sg_last(req->dst, mapped_dst_nents, sg_table +
++				 dst_sg_idx, 0);
++
++	edesc->qm_sg_dma = dma_map_single(dev, sg_table, edesc->qm_sg_bytes,
++					  DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, edesc->qm_sg_dma)) {
++		dev_err(dev, "unable to map S/G table\n");
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, op_type, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_len(in_fle, req->nbytes + ivsize);
++	dpaa2_fl_set_len(out_fle, req->nbytes);
++
++	if (!in_contig) {
++		dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++	} else {
++		dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(in_fle, iv_dma);
++	}
++
++	if (req->src == req->dst) {
++		if (!in_contig) {
++			dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
++			dpaa2_fl_set_addr(out_fle, edesc->qm_sg_dma +
++					  sizeof(*sg_table));
++		} else {
++			dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++			dpaa2_fl_set_addr(out_fle, sg_dma_address(req->src));
++		}
++	} else if (mapped_dst_nents > 1) {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(out_fle, edesc->qm_sg_dma + dst_sg_idx *
++				  sizeof(*sg_table));
++	} else {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(out_fle, sg_dma_address(req->dst));
++	}
++
++	return edesc;
++}
++
++static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc(
++	struct skcipher_givcrypt_request *greq)
++{
++	struct ablkcipher_request *req = &greq->creq;
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_request *req_ctx = ablkcipher_request_ctx(req);
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct device *dev = ctx->dev;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int src_nents, mapped_src_nents, dst_nents, mapped_dst_nents;
++	struct ablkcipher_edesc *edesc;
++	dma_addr_t iv_dma;
++	bool out_contig;
++	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++	struct dpaa2_sg_entry *sg_table;
++	int dst_sg_idx, qm_sg_ents;
++
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (unlikely(src_nents < 0)) {
++		dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
++			req->nbytes);
++		return ERR_PTR(src_nents);
++	}
++
++	if (unlikely(req->dst != req->src)) {
++		dst_nents = sg_nents_for_len(req->dst, req->nbytes);
++		if (unlikely(dst_nents < 0)) {
++			dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
++				req->nbytes);
++			return ERR_PTR(dst_nents);
++		}
++
++		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
++					      DMA_TO_DEVICE);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(dev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		mapped_dst_nents = dma_map_sg(dev, req->dst, dst_nents,
++					      DMA_FROM_DEVICE);
++		if (unlikely(!mapped_dst_nents)) {
++			dev_err(dev, "unable to map destination\n");
++			dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE);
++			return ERR_PTR(-ENOMEM);
++		}
++	} else {
++		mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
++					      DMA_BIDIRECTIONAL);
++		if (unlikely(!mapped_src_nents)) {
++			dev_err(dev, "unable to map source\n");
++			return ERR_PTR(-ENOMEM);
++		}
++
++		dst_nents = src_nents;
++		mapped_dst_nents = src_nents;
++	}
++
++	iv_dma = dma_map_single(dev, greq->giv, ivsize, DMA_FROM_DEVICE);
++	if (dma_mapping_error(dev, iv_dma)) {
++		dev_err(dev, "unable to map IV\n");
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
++			   0, 0, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	qm_sg_ents = mapped_src_nents > 1 ? mapped_src_nents : 0;
++	dst_sg_idx = qm_sg_ents;
++	if (mapped_dst_nents == 1 &&
++	    iv_dma + ivsize == sg_dma_address(req->dst)) {
++		out_contig = true;
++	} else {
++		out_contig = false;
++		qm_sg_ents += 1 + mapped_dst_nents;
++	}
++
++	if (unlikely(qm_sg_ents > CAAM_QI_MAX_ABLKCIPHER_SG)) {
++		dev_err(dev, "Insufficient S/G entries: %d > %lu\n",
++			qm_sg_ents, CAAM_QI_MAX_ABLKCIPHER_SG);
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, GIVENCRYPT, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (!edesc) {
++		dev_err(dev, "could not allocate extended descriptor\n");
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, GIVENCRYPT, 0, 0);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->src_nents = src_nents;
++	edesc->dst_nents = dst_nents;
++	edesc->iv_dma = iv_dma;
++	sg_table = &edesc->sgt[0];
++	edesc->qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
++
++	if (mapped_src_nents > 1)
++		sg_to_qm_sg_last(req->src, mapped_src_nents, sg_table, 0);
++
++	if (!out_contig) {
++		dma_to_qm_sg_one(sg_table + dst_sg_idx, iv_dma, ivsize, 0);
++		sg_to_qm_sg_last(req->dst, mapped_dst_nents, sg_table +
++				 dst_sg_idx + 1, 0);
++	}
++
++	edesc->qm_sg_dma = dma_map_single(dev, sg_table, edesc->qm_sg_bytes,
++					  DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, edesc->qm_sg_dma)) {
++		dev_err(dev, "unable to map S/G table\n");
++		caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
++			   iv_dma, ivsize, GIVENCRYPT, 0, 0);
++		qi_cache_free(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_len(in_fle, req->nbytes);
++	dpaa2_fl_set_len(out_fle, ivsize + req->nbytes);
++
++	if (mapped_src_nents > 1) {
++		dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++	} else {
++		dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src));
++	}
++
++	if (!out_contig) {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(out_fle, edesc->qm_sg_dma + dst_sg_idx *
++				  sizeof(*sg_table));
++	} else {
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(out_fle, sg_dma_address(req->dst));
++	}
++
++	return edesc;
++}
++
++static void aead_unmap(struct device *dev, struct aead_edesc *edesc,
++		       struct aead_request *req)
++{
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	int ivsize = crypto_aead_ivsize(aead);
++	struct caam_request *caam_req = aead_request_ctx(req);
++
++	caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
++		   edesc->iv_dma, ivsize, caam_req->op_type,
++		   edesc->qm_sg_dma, edesc->qm_sg_bytes);
++	dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
++}
++
++static void tls_unmap(struct device *dev, struct tls_edesc *edesc,
++		      struct aead_request *req)
++{
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	int ivsize = crypto_aead_ivsize(tls);
++	struct caam_request *caam_req = aead_request_ctx(req);
++
++	caam_unmap(dev, req->src, edesc->dst, edesc->src_nents,
++		   edesc->dst_nents, edesc->iv_dma, ivsize, caam_req->op_type,
++		   edesc->qm_sg_dma, edesc->qm_sg_bytes);
++}
++
++static void ablkcipher_unmap(struct device *dev,
++			     struct ablkcipher_edesc *edesc,
++			     struct ablkcipher_request *req)
++{
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++	struct caam_request *caam_req = ablkcipher_request_ctx(req);
++
++	caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
++		   edesc->iv_dma, ivsize, caam_req->op_type,
++		   edesc->qm_sg_dma, edesc->qm_sg_bytes);
++}
++
++static void aead_encrypt_done(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct aead_request *req = container_of(areq, struct aead_request,
++						base);
++	struct caam_request *req_ctx = to_caam_req(areq);
++	struct aead_edesc *edesc = req_ctx->edesc;
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	int ecode = 0;
++
++#ifdef DEBUG
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		ecode = -EIO;
++	}
++
++	aead_unmap(ctx->dev, edesc, req);
++	qi_cache_free(edesc);
++	aead_request_complete(req, ecode);
++}
++
++static void aead_decrypt_done(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct aead_request *req = container_of(areq, struct aead_request,
++						base);
++	struct caam_request *req_ctx = to_caam_req(areq);
++	struct aead_edesc *edesc = req_ctx->edesc;
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	int ecode = 0;
++
++#ifdef DEBUG
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		/*
++		 * verify hw auth check passed else return -EBADMSG
++		 */
++		if ((status & JRSTA_CCBERR_ERRID_MASK) ==
++		     JRSTA_CCBERR_ERRID_ICVCHK)
++			ecode = -EBADMSG;
++		else
++			ecode = -EIO;
++	}
++
++	aead_unmap(ctx->dev, edesc, req);
++	qi_cache_free(edesc);
++	aead_request_complete(req, ecode);
++}
++
++static int aead_encrypt(struct aead_request *req)
++{
++	struct aead_edesc *edesc;
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct caam_request *caam_req = aead_request_ctx(req);
++	int ret;
++
++	/* allocate extended descriptor */
++	edesc = aead_edesc_alloc(req, true);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	caam_req->flc = &ctx->flc[ENCRYPT];
++	caam_req->flc_dma = ctx->flc_dma[ENCRYPT];
++	caam_req->op_type = ENCRYPT;
++	caam_req->cbk = aead_encrypt_done;
++	caam_req->ctx = &req->base;
++	caam_req->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
++	if (ret != -EINPROGRESS &&
++	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
++		aead_unmap(ctx->dev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static int aead_decrypt(struct aead_request *req)
++{
++	struct aead_edesc *edesc;
++	struct crypto_aead *aead = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(aead);
++	struct caam_request *caam_req = aead_request_ctx(req);
++	int ret;
++
++	/* allocate extended descriptor */
++	edesc = aead_edesc_alloc(req, false);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	caam_req->flc = &ctx->flc[DECRYPT];
++	caam_req->flc_dma = ctx->flc_dma[DECRYPT];
++	caam_req->op_type = DECRYPT;
++	caam_req->cbk = aead_decrypt_done;
++	caam_req->ctx = &req->base;
++	caam_req->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
++	if (ret != -EINPROGRESS &&
++	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
++		aead_unmap(ctx->dev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static void tls_encrypt_done(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct aead_request *req = container_of(areq, struct aead_request,
++						base);
++	struct caam_request *req_ctx = to_caam_req(areq);
++	struct tls_edesc *edesc = req_ctx->edesc;
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	int ecode = 0;
++
++#ifdef DEBUG
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		ecode = -EIO;
++	}
++
++	tls_unmap(ctx->dev, edesc, req);
++	qi_cache_free(edesc);
++	aead_request_complete(req, ecode);
++}
++
++static void tls_decrypt_done(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct aead_request *req = container_of(areq, struct aead_request,
++						base);
++	struct caam_request *req_ctx = to_caam_req(areq);
++	struct tls_edesc *edesc = req_ctx->edesc;
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	int ecode = 0;
++
++#ifdef DEBUG
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		/*
++		 * verify hw auth check passed else return -EBADMSG
++		 */
++		if ((status & JRSTA_CCBERR_ERRID_MASK) ==
++		     JRSTA_CCBERR_ERRID_ICVCHK)
++			ecode = -EBADMSG;
++		else
++			ecode = -EIO;
++	}
++
++	tls_unmap(ctx->dev, edesc, req);
++	qi_cache_free(edesc);
++	aead_request_complete(req, ecode);
++}
++
++static int tls_encrypt(struct aead_request *req)
++{
++	struct tls_edesc *edesc;
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	struct caam_request *caam_req = aead_request_ctx(req);
++	int ret;
++
++	/* allocate extended descriptor */
++	edesc = tls_edesc_alloc(req, true);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	caam_req->flc = &ctx->flc[ENCRYPT];
++	caam_req->flc_dma = ctx->flc_dma[ENCRYPT];
++	caam_req->op_type = ENCRYPT;
++	caam_req->cbk = tls_encrypt_done;
++	caam_req->ctx = &req->base;
++	caam_req->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
++	if (ret != -EINPROGRESS &&
++	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
++		tls_unmap(ctx->dev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static int tls_decrypt(struct aead_request *req)
++{
++	struct tls_edesc *edesc;
++	struct crypto_aead *tls = crypto_aead_reqtfm(req);
++	struct caam_ctx *ctx = crypto_aead_ctx(tls);
++	struct caam_request *caam_req = aead_request_ctx(req);
++	int ret;
++
++	/* allocate extended descriptor */
++	edesc = tls_edesc_alloc(req, false);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	caam_req->flc = &ctx->flc[DECRYPT];
++	caam_req->flc_dma = ctx->flc_dma[DECRYPT];
++	caam_req->op_type = DECRYPT;
++	caam_req->cbk = tls_decrypt_done;
++	caam_req->ctx = &req->base;
++	caam_req->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
++	if (ret != -EINPROGRESS &&
++	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
++		tls_unmap(ctx->dev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static int ipsec_gcm_encrypt(struct aead_request *req)
++{
++	if (req->assoclen < 8)
++		return -EINVAL;
++
++	return aead_encrypt(req);
++}
++
++static int ipsec_gcm_decrypt(struct aead_request *req)
++{
++	if (req->assoclen < 8)
++		return -EINVAL;
++
++	return aead_decrypt(req);
++}
++
++static void ablkcipher_done(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct ablkcipher_request *req = ablkcipher_request_cast(areq);
++	struct caam_request *req_ctx = to_caam_req(areq);
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct ablkcipher_edesc *edesc = req_ctx->edesc;
++	int ecode = 0;
++	int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
++
++#ifdef DEBUG
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		ecode = -EIO;
++	}
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "dstiv  @" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
++		       edesc->src_nents > 1 ? 100 : ivsize, 1);
++	caam_dump_sg(KERN_ERR, "dst    @" __stringify(__LINE__)": ",
++		     DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
++		     edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
++#endif
++
++	ablkcipher_unmap(ctx->dev, edesc, req);
++	qi_cache_free(edesc);
++
++	/*
++	 * The crypto API expects us to set the IV (req->info) to the last
++	 * ciphertext block. This is used e.g. by the CTS mode.
++	 */
++	scatterwalk_map_and_copy(req->info, req->dst, req->nbytes - ivsize,
++				 ivsize, 0);
++
++	ablkcipher_request_complete(req, ecode);
++}
++
++static int ablkcipher_encrypt(struct ablkcipher_request *req)
++{
++	struct ablkcipher_edesc *edesc;
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct caam_request *caam_req = ablkcipher_request_ctx(req);
++	int ret;
++
++	/* allocate extended descriptor */
++	edesc = ablkcipher_edesc_alloc(req, true);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	caam_req->flc = &ctx->flc[ENCRYPT];
++	caam_req->flc_dma = ctx->flc_dma[ENCRYPT];
++	caam_req->op_type = ENCRYPT;
++	caam_req->cbk = ablkcipher_done;
++	caam_req->ctx = &req->base;
++	caam_req->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
++	if (ret != -EINPROGRESS &&
++	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
++		ablkcipher_unmap(ctx->dev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static int ablkcipher_givencrypt(struct skcipher_givcrypt_request *greq)
++{
++	struct ablkcipher_request *req = &greq->creq;
++	struct ablkcipher_edesc *edesc;
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct caam_request *caam_req = ablkcipher_request_ctx(req);
++	int ret;
++
++	/* allocate extended descriptor */
++	edesc = ablkcipher_giv_edesc_alloc(greq);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	caam_req->flc = &ctx->flc[GIVENCRYPT];
++	caam_req->flc_dma = ctx->flc_dma[GIVENCRYPT];
++	caam_req->op_type = GIVENCRYPT;
++	caam_req->cbk = ablkcipher_done;
++	caam_req->ctx = &req->base;
++	caam_req->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
++	if (ret != -EINPROGRESS &&
++	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
++		ablkcipher_unmap(ctx->dev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++static int ablkcipher_decrypt(struct ablkcipher_request *req)
++{
++	struct ablkcipher_edesc *edesc;
++	struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
++	struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
++	struct caam_request *caam_req = ablkcipher_request_ctx(req);
++	int ret;
++
++	/* allocate extended descriptor */
++	edesc = ablkcipher_edesc_alloc(req, false);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	caam_req->flc = &ctx->flc[DECRYPT];
++	caam_req->flc_dma = ctx->flc_dma[DECRYPT];
++	caam_req->op_type = DECRYPT;
++	caam_req->cbk = ablkcipher_done;
++	caam_req->ctx = &req->base;
++	caam_req->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
++	if (ret != -EINPROGRESS &&
++	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
++		ablkcipher_unmap(ctx->dev, edesc, req);
++		qi_cache_free(edesc);
++	}
++
++	return ret;
++}
++
++struct caam_crypto_alg {
++	struct list_head entry;
++	struct crypto_alg crypto_alg;
++	struct caam_alg_entry caam;
++};
++
++static int caam_cra_init(struct crypto_tfm *tfm, bool uses_dkp)
++{
++	struct crypto_alg *alg = tfm->__crt_alg;
++	struct caam_crypto_alg *caam_alg = container_of(alg, typeof(*caam_alg),
++							crypto_alg);
++	struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
++	dma_addr_t dma_addr;
++	int i;
++
++	/* copy descriptor header template value */
++	ctx->cdata.algtype = OP_TYPE_CLASS1_ALG |
++			     caam_alg->caam.class1_alg_type;
++	ctx->adata.algtype = OP_TYPE_CLASS2_ALG |
++			     caam_alg->caam.class2_alg_type;
++
++	ctx->dev = caam_alg->caam.dev;
++	ctx->dir = uses_dkp ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
++
++	dma_addr = dma_map_single_attrs(ctx->dev, ctx->flc,
++					offsetof(struct caam_ctx, flc_dma),
++					ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
++	if (dma_mapping_error(ctx->dev, dma_addr)) {
++		dev_err(ctx->dev, "unable to map key, shared descriptors\n");
++		return -ENOMEM;
++	}
++
++	for (i = 0; i < NUM_OP; i++)
++		ctx->flc_dma[i] = dma_addr + i * sizeof(ctx->flc[i]);
++	ctx->key_dma = dma_addr + NUM_OP * sizeof(ctx->flc[0]);
++
++	return 0;
++}
++
++static int caam_cra_init_ablkcipher(struct crypto_tfm *tfm)
++{
++	struct ablkcipher_tfm *ablkcipher_tfm =
++		crypto_ablkcipher_crt(__crypto_ablkcipher_cast(tfm));
++
++	ablkcipher_tfm->reqsize = sizeof(struct caam_request);
++	return caam_cra_init(tfm, false);
++}
++
++static int caam_cra_init_aead(struct crypto_aead *tfm)
++{
++	struct aead_alg *alg = crypto_aead_alg(tfm);
++
++	crypto_aead_set_reqsize(tfm, sizeof(struct caam_request));
++	return caam_cra_init(crypto_aead_tfm(tfm),
++			     (alg->setkey == aead_setkey) ||
++			     (alg->setkey == tls_setkey));
++}
++
++static void caam_exit_common(struct caam_ctx *ctx)
++{
++	dma_unmap_single_attrs(ctx->dev, ctx->flc_dma[0],
++			       offsetof(struct caam_ctx, flc_dma), ctx->dir,
++			       DMA_ATTR_SKIP_CPU_SYNC);
++}
++
++static void caam_cra_exit(struct crypto_tfm *tfm)
++{
++	caam_exit_common(crypto_tfm_ctx(tfm));
++}
++
++static void caam_cra_exit_aead(struct crypto_aead *tfm)
++{
++	caam_exit_common(crypto_aead_ctx(tfm));
++}
++
++#define template_ablkcipher	template_u.ablkcipher
++struct caam_alg_template {
++	char name[CRYPTO_MAX_ALG_NAME];
++	char driver_name[CRYPTO_MAX_ALG_NAME];
++	unsigned int blocksize;
++	u32 type;
++	union {
++		struct ablkcipher_alg ablkcipher;
++	} template_u;
++	u32 class1_alg_type;
++	u32 class2_alg_type;
++};
++
++static struct caam_alg_template driver_algs[] = {
++	/* ablkcipher descriptor */
++	{
++		.name = "cbc(aes)",
++		.driver_name = "cbc-aes-caam-qi2",
++		.blocksize = AES_BLOCK_SIZE,
++		.type = CRYPTO_ALG_TYPE_GIVCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.givencrypt = ablkcipher_givencrypt,
++			.geniv = "<built-in>",
++			.min_keysize = AES_MIN_KEY_SIZE,
++			.max_keysize = AES_MAX_KEY_SIZE,
++			.ivsize = AES_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++	},
++	{
++		.name = "cbc(des3_ede)",
++		.driver_name = "cbc-3des-caam-qi2",
++		.blocksize = DES3_EDE_BLOCK_SIZE,
++		.type = CRYPTO_ALG_TYPE_GIVCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.givencrypt = ablkcipher_givencrypt,
++			.geniv = "<built-in>",
++			.min_keysize = DES3_EDE_KEY_SIZE,
++			.max_keysize = DES3_EDE_KEY_SIZE,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++	},
++	{
++		.name = "cbc(des)",
++		.driver_name = "cbc-des-caam-qi2",
++		.blocksize = DES_BLOCK_SIZE,
++		.type = CRYPTO_ALG_TYPE_GIVCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.givencrypt = ablkcipher_givencrypt,
++			.geniv = "<built-in>",
++			.min_keysize = DES_KEY_SIZE,
++			.max_keysize = DES_KEY_SIZE,
++			.ivsize = DES_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++	},
++	{
++		.name = "ctr(aes)",
++		.driver_name = "ctr-aes-caam-qi2",
++		.blocksize = 1,
++		.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.geniv = "chainiv",
++			.min_keysize = AES_MIN_KEY_SIZE,
++			.max_keysize = AES_MAX_KEY_SIZE,
++			.ivsize = AES_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
++	},
++	{
++		.name = "rfc3686(ctr(aes))",
++		.driver_name = "rfc3686-ctr-aes-caam-qi2",
++		.blocksize = 1,
++		.type = CRYPTO_ALG_TYPE_GIVCIPHER,
++		.template_ablkcipher = {
++			.setkey = ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.givencrypt = ablkcipher_givencrypt,
++			.geniv = "<built-in>",
++			.min_keysize = AES_MIN_KEY_SIZE +
++				       CTR_RFC3686_NONCE_SIZE,
++			.max_keysize = AES_MAX_KEY_SIZE +
++				       CTR_RFC3686_NONCE_SIZE,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
++	},
++	{
++		.name = "xts(aes)",
++		.driver_name = "xts-aes-caam-qi2",
++		.blocksize = AES_BLOCK_SIZE,
++		.type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++		.template_ablkcipher = {
++			.setkey = xts_ablkcipher_setkey,
++			.encrypt = ablkcipher_encrypt,
++			.decrypt = ablkcipher_decrypt,
++			.geniv = "eseqiv",
++			.min_keysize = 2 * AES_MIN_KEY_SIZE,
++			.max_keysize = 2 * AES_MAX_KEY_SIZE,
++			.ivsize = AES_BLOCK_SIZE,
++		},
++		.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS,
++	}
++};
++
++static struct caam_aead_alg driver_aeads[] = {
++	{
++		.aead = {
++			.base = {
++				.cra_name = "rfc4106(gcm(aes))",
++				.cra_driver_name = "rfc4106-gcm-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = rfc4106_setkey,
++			.setauthsize = rfc4106_setauthsize,
++			.encrypt = ipsec_gcm_encrypt,
++			.decrypt = ipsec_gcm_decrypt,
++			.ivsize = 8,
++			.maxauthsize = AES_BLOCK_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "rfc4543(gcm(aes))",
++				.cra_driver_name = "rfc4543-gcm-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = rfc4543_setkey,
++			.setauthsize = rfc4543_setauthsize,
++			.encrypt = ipsec_gcm_encrypt,
++			.decrypt = ipsec_gcm_decrypt,
++			.ivsize = 8,
++			.maxauthsize = AES_BLOCK_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
++		},
++	},
++	/* Galois Counter Mode */
++	{
++		.aead = {
++			.base = {
++				.cra_name = "gcm(aes)",
++				.cra_driver_name = "gcm-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = gcm_setkey,
++			.setauthsize = gcm_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = 12,
++			.maxauthsize = AES_BLOCK_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
++		}
++	},
++	/* single-pass ipsec_esp descriptor */
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(md5),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-md5-"
++						   "cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(md5),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-hmac-md5-"
++						   "cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha1),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha1-"
++						   "cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha1),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha1-cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha224),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha224-"
++						   "cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha224),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha224-cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha256),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha256-"
++						   "cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha256),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha256-cbc-aes-"
++						   "caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha384),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha384-"
++						   "cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha384),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha384-cbc-aes-"
++						   "caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha512),cbc(aes))",
++				.cra_driver_name = "authenc-hmac-sha512-"
++						   "cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha512),"
++					    "cbc(aes)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha512-cbc-aes-"
++						   "caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(md5),cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-md5-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(md5),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-hmac-md5-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha1),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha1-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha1),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha1-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha224),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha224-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha224),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha224-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha256),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha256-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha256),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha256-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha384),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha384-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha384),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha384-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha512),"
++					    "cbc(des3_ede))",
++				.cra_driver_name = "authenc-hmac-sha512-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha512),"
++					    "cbc(des3_ede)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha512-"
++						   "cbc-des3_ede-caam-qi2",
++				.cra_blocksize = DES3_EDE_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES3_EDE_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(md5),cbc(des))",
++				.cra_driver_name = "authenc-hmac-md5-"
++						   "cbc-des-caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(md5),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-hmac-md5-"
++						   "cbc-des-caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha1),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha1-"
++						   "cbc-des-caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha1),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha1-cbc-des-caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha224),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha224-"
++						   "cbc-des-caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha224),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha224-cbc-des-"
++						   "caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha256),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha256-"
++						   "cbc-des-caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha256),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha256-cbc-desi-"
++						   "caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha384),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha384-"
++						   "cbc-des-caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha384),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha384-cbc-des-"
++						   "caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha512),cbc(des))",
++				.cra_driver_name = "authenc-hmac-sha512-"
++						   "cbc-des-caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "echainiv(authenc(hmac(sha512),"
++					    "cbc(des)))",
++				.cra_driver_name = "echainiv-authenc-"
++						   "hmac-sha512-cbc-des-"
++						   "caam-qi2",
++				.cra_blocksize = DES_BLOCK_SIZE,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = DES_BLOCK_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.geniv = true,
++		}
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(md5),"
++					    "rfc3686(ctr(aes)))",
++				.cra_driver_name = "authenc-hmac-md5-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "seqiv(authenc("
++					    "hmac(md5),rfc3686(ctr(aes))))",
++				.cra_driver_name = "seqiv-authenc-hmac-md5-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = MD5_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_MD5 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha1),"
++					    "rfc3686(ctr(aes)))",
++				.cra_driver_name = "authenc-hmac-sha1-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "seqiv(authenc("
++					    "hmac(sha1),rfc3686(ctr(aes))))",
++				.cra_driver_name = "seqiv-authenc-hmac-sha1-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha224),"
++					    "rfc3686(ctr(aes)))",
++				.cra_driver_name = "authenc-hmac-sha224-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "seqiv(authenc("
++					    "hmac(sha224),rfc3686(ctr(aes))))",
++				.cra_driver_name = "seqiv-authenc-hmac-sha224-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA224_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA224 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha256),"
++					    "rfc3686(ctr(aes)))",
++				.cra_driver_name = "authenc-hmac-sha256-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "seqiv(authenc(hmac(sha256),"
++					    "rfc3686(ctr(aes))))",
++				.cra_driver_name = "seqiv-authenc-hmac-sha256-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA256_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA256 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha384),"
++					    "rfc3686(ctr(aes)))",
++				.cra_driver_name = "authenc-hmac-sha384-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "seqiv(authenc(hmac(sha384),"
++					    "rfc3686(ctr(aes))))",
++				.cra_driver_name = "seqiv-authenc-hmac-sha384-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA384_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA384 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "authenc(hmac(sha512),"
++					    "rfc3686(ctr(aes)))",
++				.cra_driver_name = "authenc-hmac-sha512-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "seqiv(authenc(hmac(sha512),"
++					    "rfc3686(ctr(aes))))",
++				.cra_driver_name = "seqiv-authenc-hmac-sha512-"
++						   "rfc3686-ctr-aes-caam-qi2",
++				.cra_blocksize = 1,
++			},
++			.setkey = aead_setkey,
++			.setauthsize = aead_setauthsize,
++			.encrypt = aead_encrypt,
++			.decrypt = aead_decrypt,
++			.ivsize = CTR_RFC3686_IV_SIZE,
++			.maxauthsize = SHA512_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES |
++					   OP_ALG_AAI_CTR_MOD128,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA512 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++			.rfc3686 = true,
++			.geniv = true,
++		},
++	},
++	{
++		.aead = {
++			.base = {
++				.cra_name = "tls10(hmac(sha1),cbc(aes))",
++				.cra_driver_name = "tls10-hmac-sha1-cbc-aes-caam-qi2",
++				.cra_blocksize = AES_BLOCK_SIZE,
++			},
++			.setkey = tls_setkey,
++			.setauthsize = tls_setauthsize,
++			.encrypt = tls_encrypt,
++			.decrypt = tls_decrypt,
++			.ivsize = AES_BLOCK_SIZE,
++			.maxauthsize = SHA1_DIGEST_SIZE,
++		},
++		.caam = {
++			.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
++			.class2_alg_type = OP_ALG_ALGSEL_SHA1 |
++					   OP_ALG_AAI_HMAC_PRECOMP,
++		},
++	},
++};
++
++static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
++					      *template)
++{
++	struct caam_crypto_alg *t_alg;
++	struct crypto_alg *alg;
++
++	t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
++	if (!t_alg)
++		return ERR_PTR(-ENOMEM);
++
++	alg = &t_alg->crypto_alg;
++
++	snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
++	snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
++		 template->driver_name);
++	alg->cra_module = THIS_MODULE;
++	alg->cra_exit = caam_cra_exit;
++	alg->cra_priority = CAAM_CRA_PRIORITY;
++	alg->cra_blocksize = template->blocksize;
++	alg->cra_alignmask = 0;
++	alg->cra_ctxsize = sizeof(struct caam_ctx);
++	alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
++			 template->type;
++	switch (template->type) {
++	case CRYPTO_ALG_TYPE_GIVCIPHER:
++		alg->cra_init = caam_cra_init_ablkcipher;
++		alg->cra_type = &crypto_givcipher_type;
++		alg->cra_ablkcipher = template->template_ablkcipher;
++		break;
++	case CRYPTO_ALG_TYPE_ABLKCIPHER:
++		alg->cra_init = caam_cra_init_ablkcipher;
++		alg->cra_type = &crypto_ablkcipher_type;
++		alg->cra_ablkcipher = template->template_ablkcipher;
++		break;
++	}
++
++	t_alg->caam.class1_alg_type = template->class1_alg_type;
++	t_alg->caam.class2_alg_type = template->class2_alg_type;
++
++	return t_alg;
++}
++
++static void caam_aead_alg_init(struct caam_aead_alg *t_alg)
++{
++	struct aead_alg *alg = &t_alg->aead;
++
++	alg->base.cra_module = THIS_MODULE;
++	alg->base.cra_priority = CAAM_CRA_PRIORITY;
++	alg->base.cra_ctxsize = sizeof(struct caam_ctx);
++	alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
++
++	alg->init = caam_cra_init_aead;
++	alg->exit = caam_cra_exit_aead;
++}
++
++/* max hash key is max split key size */
++#define CAAM_MAX_HASH_KEY_SIZE		(SHA512_DIGEST_SIZE * 2)
++
++#define CAAM_MAX_HASH_BLOCK_SIZE	SHA512_BLOCK_SIZE
++#define CAAM_MAX_HASH_DIGEST_SIZE	SHA512_DIGEST_SIZE
++
++#define DESC_HASH_MAX_USED_BYTES	(DESC_AHASH_FINAL_LEN + \
++					 CAAM_MAX_HASH_KEY_SIZE)
++#define DESC_HASH_MAX_USED_LEN		(DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ)
++
++/* caam context sizes for hashes: running digest + 8 */
++#define HASH_MSG_LEN			8
++#define MAX_CTX_LEN			(HASH_MSG_LEN + SHA512_DIGEST_SIZE)
++
++enum hash_optype {
++	UPDATE = 0,
++	UPDATE_FIRST,
++	FINALIZE,
++	DIGEST,
++	HASH_NUM_OP
++};
++
++/**
++ * caam_hash_ctx - ahash per-session context
++ * @flc: Flow Contexts array
++ * @flc_dma: I/O virtual addresses of the Flow Contexts
++ * @key:  virtual address of the authentication key
++ * @dev: dpseci device
++ * @ctx_len: size of Context Register
++ * @adata: hashing algorithm details
++ */
++struct caam_hash_ctx {
++	struct caam_flc flc[HASH_NUM_OP];
++	dma_addr_t flc_dma[HASH_NUM_OP];
++	u8 key[CAAM_MAX_HASH_KEY_SIZE];
++	struct device *dev;
++	int ctx_len;
++	struct alginfo adata;
++};
++
++/* ahash state */
++struct caam_hash_state {
++	struct caam_request caam_req;
++	dma_addr_t buf_dma;
++	dma_addr_t ctx_dma;
++	u8 buf_0[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
++	int buflen_0;
++	u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
++	int buflen_1;
++	u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
++	int (*update)(struct ahash_request *req);
++	int (*final)(struct ahash_request *req);
++	int (*finup)(struct ahash_request *req);
++	int current_buf;
++};
++
++struct caam_export_state {
++	u8 buf[CAAM_MAX_HASH_BLOCK_SIZE];
++	u8 caam_ctx[MAX_CTX_LEN];
++	int buflen;
++	int (*update)(struct ahash_request *req);
++	int (*final)(struct ahash_request *req);
++	int (*finup)(struct ahash_request *req);
++};
++
++static inline void switch_buf(struct caam_hash_state *state)
++{
++	state->current_buf ^= 1;
++}
++
++static inline u8 *current_buf(struct caam_hash_state *state)
++{
++	return state->current_buf ? state->buf_1 : state->buf_0;
++}
++
++static inline u8 *alt_buf(struct caam_hash_state *state)
++{
++	return state->current_buf ? state->buf_0 : state->buf_1;
++}
++
++static inline int *current_buflen(struct caam_hash_state *state)
++{
++	return state->current_buf ? &state->buflen_1 : &state->buflen_0;
++}
++
++static inline int *alt_buflen(struct caam_hash_state *state)
++{
++	return state->current_buf ? &state->buflen_0 : &state->buflen_1;
++}
++
++/* Map current buffer in state (if length > 0) and put it in link table */
++static inline int buf_map_to_qm_sg(struct device *dev,
++				   struct dpaa2_sg_entry *qm_sg,
++				   struct caam_hash_state *state)
++{
++	int buflen = *current_buflen(state);
++
++	if (!buflen)
++		return 0;
++
++	state->buf_dma = dma_map_single(dev, current_buf(state), buflen,
++					DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, state->buf_dma)) {
++		dev_err(dev, "unable to map buf\n");
++		state->buf_dma = 0;
++		return -ENOMEM;
++	}
++
++	dma_to_qm_sg_one(qm_sg, state->buf_dma, buflen, 0);
++
++	return 0;
++}
++
++/* Map state->caam_ctx, and add it to link table */
++static inline int ctx_map_to_qm_sg(struct device *dev,
++				   struct caam_hash_state *state, int ctx_len,
++				   struct dpaa2_sg_entry *qm_sg, u32 flag)
++{
++	state->ctx_dma = dma_map_single(dev, state->caam_ctx, ctx_len, flag);
++	if (dma_mapping_error(dev, state->ctx_dma)) {
++		dev_err(dev, "unable to map ctx\n");
++		state->ctx_dma = 0;
++		return -ENOMEM;
++	}
++
++	dma_to_qm_sg_one(qm_sg, state->ctx_dma, ctx_len, 0);
++
++	return 0;
++}
++
++static int ahash_set_sh_desc(struct crypto_ahash *ahash)
++{
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	int digestsize = crypto_ahash_digestsize(ahash);
++	struct dpaa2_caam_priv *priv = dev_get_drvdata(ctx->dev);
++	struct caam_flc *flc;
++	u32 *desc;
++
++	ctx->adata.key_virt = ctx->key;
++	ctx->adata.key_inline = true;
++
++	/* ahash_update shared descriptor */
++	flc = &ctx->flc[UPDATE];
++	desc = flc->sh_desc;
++	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_UPDATE, ctx->ctx_len,
++			  ctx->ctx_len, true, priv->sec_attr.era);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE],
++				   desc_bytes(desc), DMA_BIDIRECTIONAL);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "ahash update shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++
++	/* ahash_update_first shared descriptor */
++	flc = &ctx->flc[UPDATE_FIRST];
++	desc = flc->sh_desc;
++	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len,
++			  ctx->ctx_len, false, priv->sec_attr.era);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE_FIRST],
++				   desc_bytes(desc), DMA_BIDIRECTIONAL);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "ahash update first shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++
++	/* ahash_final shared descriptor */
++	flc = &ctx->flc[FINALIZE];
++	desc = flc->sh_desc;
++	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, digestsize,
++			  ctx->ctx_len, true, priv->sec_attr.era);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[FINALIZE],
++				   desc_bytes(desc), DMA_BIDIRECTIONAL);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "ahash final shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++
++	/* ahash_digest shared descriptor */
++	flc = &ctx->flc[DIGEST];
++	desc = flc->sh_desc;
++	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, digestsize,
++			  ctx->ctx_len, false, priv->sec_attr.era);
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	dma_sync_single_for_device(ctx->dev, ctx->flc_dma[DIGEST],
++				   desc_bytes(desc), DMA_BIDIRECTIONAL);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR,
++		       "ahash digest shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++
++	return 0;
++}
++
++/* Digest hash size if it is too large */
++static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
++			   u32 *keylen, u8 *key_out, u32 digestsize)
++{
++	struct caam_request *req_ctx;
++	u32 *desc;
++	struct split_key_sh_result result;
++	dma_addr_t src_dma, dst_dma;
++	struct caam_flc *flc;
++	dma_addr_t flc_dma;
++	int ret = -ENOMEM;
++	struct dpaa2_fl_entry *in_fle, *out_fle;
++
++	req_ctx = kzalloc(sizeof(*req_ctx), GFP_KERNEL | GFP_DMA);
++	if (!req_ctx)
++		return -ENOMEM;
++
++	in_fle = &req_ctx->fd_flt[1];
++	out_fle = &req_ctx->fd_flt[0];
++
++	flc = kzalloc(sizeof(*flc), GFP_KERNEL | GFP_DMA);
++	if (!flc)
++		goto err_flc;
++
++	src_dma = dma_map_single(ctx->dev, (void *)key_in, *keylen,
++				 DMA_TO_DEVICE);
++	if (dma_mapping_error(ctx->dev, src_dma)) {
++		dev_err(ctx->dev, "unable to map key input memory\n");
++		goto err_src_dma;
++	}
++	dst_dma = dma_map_single(ctx->dev, (void *)key_out, digestsize,
++				 DMA_FROM_DEVICE);
++	if (dma_mapping_error(ctx->dev, dst_dma)) {
++		dev_err(ctx->dev, "unable to map key output memory\n");
++		goto err_dst_dma;
++	}
++
++	desc = flc->sh_desc;
++
++	init_sh_desc(desc, 0);
++
++	/* descriptor to perform unkeyed hash on key_in */
++	append_operation(desc, ctx->adata.algtype | OP_ALG_ENCRYPT |
++			 OP_ALG_AS_INITFINAL);
++	append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 |
++			     FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_MSG);
++	append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
++			 LDST_SRCDST_BYTE_CONTEXT);
++
++	flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
++	flc_dma = dma_map_single(ctx->dev, flc, sizeof(flc->flc) +
++				 desc_bytes(desc), DMA_TO_DEVICE);
++	if (dma_mapping_error(ctx->dev, flc_dma)) {
++		dev_err(ctx->dev, "unable to map shared descriptor\n");
++		goto err_flc_dma;
++	}
++
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
++	dpaa2_fl_set_addr(in_fle, src_dma);
++	dpaa2_fl_set_len(in_fle, *keylen);
++	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++	dpaa2_fl_set_addr(out_fle, dst_dma);
++	dpaa2_fl_set_len(out_fle, digestsize);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "key_in@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key_in, *keylen, 1);
++	print_hex_dump(KERN_ERR, "shdesc@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++
++	result.err = 0;
++	init_completion(&result.completion);
++	result.dev = ctx->dev;
++
++	req_ctx->flc = flc;
++	req_ctx->flc_dma = flc_dma;
++	req_ctx->cbk = split_key_sh_done;
++	req_ctx->ctx = &result;
++
++	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++	if (ret == -EINPROGRESS) {
++		/* in progress */
++		wait_for_completion(&result.completion);
++		ret = result.err;
++#ifdef DEBUG
++		print_hex_dump(KERN_ERR,
++			       "digested key@" __stringify(__LINE__)": ",
++			       DUMP_PREFIX_ADDRESS, 16, 4, key_in, digestsize,
++			       1);
++#endif
++	}
++
++	dma_unmap_single(ctx->dev, flc_dma, sizeof(flc->flc) + desc_bytes(desc),
++			 DMA_TO_DEVICE);
++err_flc_dma:
++	dma_unmap_single(ctx->dev, dst_dma, digestsize, DMA_FROM_DEVICE);
++err_dst_dma:
++	dma_unmap_single(ctx->dev, src_dma, *keylen, DMA_TO_DEVICE);
++err_src_dma:
++	kfree(flc);
++err_flc:
++	kfree(req_ctx);
++
++	*keylen = digestsize;
++
++	return ret;
++}
++
++static int ahash_setkey(struct crypto_ahash *ahash, const u8 *key,
++			unsigned int keylen)
++{
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	unsigned int blocksize = crypto_tfm_alg_blocksize(&ahash->base);
++	unsigned int digestsize = crypto_ahash_digestsize(ahash);
++	int ret;
++	u8 *hashed_key = NULL;
++
++#ifdef DEBUG
++	dev_err(ctx->dev, "keylen %d blocksize %d\n", keylen, blocksize);
++#endif
++
++	if (keylen > blocksize) {
++		hashed_key = kmalloc_array(digestsize, sizeof(*hashed_key),
++					   GFP_KERNEL | GFP_DMA);
++		if (!hashed_key)
++			return -ENOMEM;
++		ret = hash_digest_key(ctx, key, &keylen, hashed_key,
++				      digestsize);
++		if (ret)
++			goto bad_free_key;
++		key = hashed_key;
++	}
++
++	ctx->adata.keylen = keylen;
++	ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
++					      OP_ALG_ALGSEL_MASK);
++	if (ctx->adata.keylen_pad > CAAM_MAX_HASH_KEY_SIZE)
++		goto bad_free_key;
++
++	memcpy(ctx->key, key, keylen);
++
++	kfree(hashed_key);
++	return ahash_set_sh_desc(ahash);
++bad_free_key:
++	kfree(hashed_key);
++	crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
++	return -EINVAL;
++}
++
++static inline void ahash_unmap(struct device *dev, struct ahash_edesc *edesc,
++			       struct ahash_request *req, int dst_len)
++{
++	struct caam_hash_state *state = ahash_request_ctx(req);
++
++	if (edesc->src_nents)
++		dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE);
++	if (edesc->dst_dma)
++		dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE);
++
++	if (edesc->qm_sg_bytes)
++		dma_unmap_single(dev, edesc->qm_sg_dma, edesc->qm_sg_bytes,
++				 DMA_TO_DEVICE);
++
++	if (state->buf_dma) {
++		dma_unmap_single(dev, state->buf_dma, *current_buflen(state),
++				 DMA_TO_DEVICE);
++		state->buf_dma = 0;
++	}
++}
++
++static inline void ahash_unmap_ctx(struct device *dev,
++				   struct ahash_edesc *edesc,
++				   struct ahash_request *req, int dst_len,
++				   u32 flag)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++
++	if (state->ctx_dma) {
++		dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag);
++		state->ctx_dma = 0;
++	}
++	ahash_unmap(dev, edesc, req, dst_len);
++}
++
++static void ahash_done(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct ahash_request *req = ahash_request_cast(areq);
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct ahash_edesc *edesc = state->caam_req.edesc;
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	int digestsize = crypto_ahash_digestsize(ahash);
++	int ecode = 0;
++
++#ifdef DEBUG
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		ecode = -EIO;
++	}
++
++	ahash_unmap(ctx->dev, edesc, req, digestsize);
++	qi_cache_free(edesc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
++		       ctx->ctx_len, 1);
++	if (req->result)
++		print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ",
++			       DUMP_PREFIX_ADDRESS, 16, 4, req->result,
++			       digestsize, 1);
++#endif
++
++	req->base.complete(&req->base, ecode);
++}
++
++static void ahash_done_bi(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct ahash_request *req = ahash_request_cast(areq);
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct ahash_edesc *edesc = state->caam_req.edesc;
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	int ecode = 0;
++#ifdef DEBUG
++	int digestsize = crypto_ahash_digestsize(ahash);
++
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		ecode = -EIO;
++	}
++
++	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
++	switch_buf(state);
++	qi_cache_free(edesc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
++		       ctx->ctx_len, 1);
++	if (req->result)
++		print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ",
++			       DUMP_PREFIX_ADDRESS, 16, 4, req->result,
++			       digestsize, 1);
++#endif
++
++	req->base.complete(&req->base, ecode);
++}
++
++static void ahash_done_ctx_src(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct ahash_request *req = ahash_request_cast(areq);
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct ahash_edesc *edesc = state->caam_req.edesc;
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	int digestsize = crypto_ahash_digestsize(ahash);
++	int ecode = 0;
++
++#ifdef DEBUG
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		ecode = -EIO;
++	}
++
++	ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_TO_DEVICE);
++	qi_cache_free(edesc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
++		       ctx->ctx_len, 1);
++	if (req->result)
++		print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ",
++			       DUMP_PREFIX_ADDRESS, 16, 4, req->result,
++			       digestsize, 1);
++#endif
++
++	req->base.complete(&req->base, ecode);
++}
++
++static void ahash_done_ctx_dst(void *cbk_ctx, u32 status)
++{
++	struct crypto_async_request *areq = cbk_ctx;
++	struct ahash_request *req = ahash_request_cast(areq);
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct ahash_edesc *edesc = state->caam_req.edesc;
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	int ecode = 0;
++#ifdef DEBUG
++	int digestsize = crypto_ahash_digestsize(ahash);
++
++	dev_err(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
++#endif
++
++	if (unlikely(status)) {
++		caam_qi2_strstatus(ctx->dev, status);
++		ecode = -EIO;
++	}
++
++	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE);
++	switch_buf(state);
++	qi_cache_free(edesc);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "ctx@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
++		       ctx->ctx_len, 1);
++	if (req->result)
++		print_hex_dump(KERN_ERR, "result@" __stringify(__LINE__)": ",
++			       DUMP_PREFIX_ADDRESS, 16, 4, req->result,
++			       digestsize, 1);
++#endif
++
++	req->base.complete(&req->base, ecode);
++}
++
++static int ahash_update_ctx(struct ahash_request *req)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_request *req_ctx = &state->caam_req;
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	u8 *buf = current_buf(state);
++	int *buflen = current_buflen(state);
++	u8 *next_buf = alt_buf(state);
++	int *next_buflen = alt_buflen(state), last_buflen;
++	int in_len = *buflen + req->nbytes, to_hash;
++	int src_nents, mapped_nents, qm_sg_bytes, qm_sg_src_index;
++	struct ahash_edesc *edesc;
++	int ret = 0;
++
++	last_buflen = *next_buflen;
++	*next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
++	to_hash = in_len - *next_buflen;
++
++	if (to_hash) {
++		struct dpaa2_sg_entry *sg_table;
++
++		src_nents = sg_nents_for_len(req->src,
++					     req->nbytes - (*next_buflen));
++		if (src_nents < 0) {
++			dev_err(ctx->dev, "Invalid number of src SG.\n");
++			return src_nents;
++		}
++
++		if (src_nents) {
++			mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
++						  DMA_TO_DEVICE);
++			if (!mapped_nents) {
++				dev_err(ctx->dev, "unable to DMA map source\n");
++				return -ENOMEM;
++			}
++		} else {
++			mapped_nents = 0;
++		}
++
++		/* allocate space for base edesc and link tables */
++		edesc = qi_cache_zalloc(GFP_DMA | flags);
++		if (!edesc) {
++			dma_unmap_sg(ctx->dev, req->src, src_nents,
++				     DMA_TO_DEVICE);
++			return -ENOMEM;
++		}
++
++		edesc->src_nents = src_nents;
++		qm_sg_src_index = 1 + (*buflen ? 1 : 0);
++		qm_sg_bytes = (qm_sg_src_index + mapped_nents) *
++			      sizeof(*sg_table);
++		sg_table = &edesc->sgt[0];
++
++		ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
++				       DMA_BIDIRECTIONAL);
++		if (ret)
++			goto unmap_ctx;
++
++		ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
++		if (ret)
++			goto unmap_ctx;
++
++		if (mapped_nents) {
++			sg_to_qm_sg_last(req->src, mapped_nents,
++					 sg_table + qm_sg_src_index, 0);
++			if (*next_buflen)
++				scatterwalk_map_and_copy(next_buf, req->src,
++							 to_hash - *buflen,
++							 *next_buflen, 0);
++		} else {
++			dpaa2_sg_set_final(sg_table + qm_sg_src_index - 1,
++					   true);
++		}
++
++		edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
++						  qm_sg_bytes, DMA_TO_DEVICE);
++		if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
++			dev_err(ctx->dev, "unable to map S/G table\n");
++			ret = -ENOMEM;
++			goto unmap_ctx;
++		}
++		edesc->qm_sg_bytes = qm_sg_bytes;
++
++		memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++		dpaa2_fl_set_final(in_fle, true);
++		dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++		dpaa2_fl_set_len(in_fle, ctx->ctx_len + to_hash);
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(out_fle, state->ctx_dma);
++		dpaa2_fl_set_len(out_fle, ctx->ctx_len);
++
++		req_ctx->flc = &ctx->flc[UPDATE];
++		req_ctx->flc_dma = ctx->flc_dma[UPDATE];
++		req_ctx->cbk = ahash_done_bi;
++		req_ctx->ctx = &req->base;
++		req_ctx->edesc = edesc;
++
++		ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++		if (ret != -EINPROGRESS &&
++		    !(ret == -EBUSY &&
++		      req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
++			goto unmap_ctx;
++	} else if (*next_buflen) {
++		scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
++					 req->nbytes, 0);
++		*buflen = *next_buflen;
++		*next_buflen = last_buflen;
++	}
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "buf@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
++	print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
++		       *next_buflen, 1);
++#endif
++
++	return ret;
++unmap_ctx:
++	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
++	qi_cache_free(edesc);
++	return ret;
++}
++
++static int ahash_final_ctx(struct ahash_request *req)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_request *req_ctx = &state->caam_req;
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	int buflen = *current_buflen(state);
++	int qm_sg_bytes, qm_sg_src_index;
++	int digestsize = crypto_ahash_digestsize(ahash);
++	struct ahash_edesc *edesc;
++	struct dpaa2_sg_entry *sg_table;
++	int ret;
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (!edesc)
++		return -ENOMEM;
++
++	qm_sg_src_index = 1 + (buflen ? 1 : 0);
++	qm_sg_bytes = qm_sg_src_index * sizeof(*sg_table);
++	sg_table = &edesc->sgt[0];
++
++	ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
++			       DMA_TO_DEVICE);
++	if (ret)
++		goto unmap_ctx;
++
++	ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
++	if (ret)
++		goto unmap_ctx;
++
++	dpaa2_sg_set_final(sg_table + qm_sg_src_index - 1, true);
++
++	edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
++					  DMA_TO_DEVICE);
++	if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
++		dev_err(ctx->dev, "unable to map S/G table\n");
++		ret = -ENOMEM;
++		goto unmap_ctx;
++	}
++	edesc->qm_sg_bytes = qm_sg_bytes;
++
++	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
++					DMA_FROM_DEVICE);
++	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
++		dev_err(ctx->dev, "unable to map dst\n");
++		edesc->dst_dma = 0;
++		ret = -ENOMEM;
++		goto unmap_ctx;
++	}
++
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++	dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++	dpaa2_fl_set_len(in_fle, ctx->ctx_len + buflen);
++	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
++	dpaa2_fl_set_len(out_fle, digestsize);
++
++	req_ctx->flc = &ctx->flc[FINALIZE];
++	req_ctx->flc_dma = ctx->flc_dma[FINALIZE];
++	req_ctx->cbk = ahash_done_ctx_src;
++	req_ctx->ctx = &req->base;
++	req_ctx->edesc = edesc;
++
++	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++	if (ret == -EINPROGRESS ||
++	    (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
++		return ret;
++
++unmap_ctx:
++	ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_FROM_DEVICE);
++	qi_cache_free(edesc);
++	return ret;
++}
++
++static int ahash_finup_ctx(struct ahash_request *req)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_request *req_ctx = &state->caam_req;
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	int buflen = *current_buflen(state);
++	int qm_sg_bytes, qm_sg_src_index;
++	int src_nents, mapped_nents;
++	int digestsize = crypto_ahash_digestsize(ahash);
++	struct ahash_edesc *edesc;
++	struct dpaa2_sg_entry *sg_table;
++	int ret;
++
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (src_nents < 0) {
++		dev_err(ctx->dev, "Invalid number of src SG.\n");
++		return src_nents;
++	}
++
++	if (src_nents) {
++		mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
++					  DMA_TO_DEVICE);
++		if (!mapped_nents) {
++			dev_err(ctx->dev, "unable to DMA map source\n");
++			return -ENOMEM;
++		}
++	} else {
++		mapped_nents = 0;
++	}
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (!edesc) {
++		dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
++		return -ENOMEM;
++	}
++
++	edesc->src_nents = src_nents;
++	qm_sg_src_index = 1 + (buflen ? 1 : 0);
++	qm_sg_bytes = (qm_sg_src_index + mapped_nents) * sizeof(*sg_table);
++	sg_table = &edesc->sgt[0];
++
++	ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
++			       DMA_TO_DEVICE);
++	if (ret)
++		goto unmap_ctx;
++
++	ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
++	if (ret)
++		goto unmap_ctx;
++
++	sg_to_qm_sg_last(req->src, mapped_nents, sg_table + qm_sg_src_index, 0);
++
++	edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
++					  DMA_TO_DEVICE);
++	if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
++		dev_err(ctx->dev, "unable to map S/G table\n");
++		ret = -ENOMEM;
++		goto unmap_ctx;
++	}
++	edesc->qm_sg_bytes = qm_sg_bytes;
++
++	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
++					DMA_FROM_DEVICE);
++	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
++		dev_err(ctx->dev, "unable to map dst\n");
++		edesc->dst_dma = 0;
++		ret = -ENOMEM;
++		goto unmap_ctx;
++	}
++
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++	dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++	dpaa2_fl_set_len(in_fle, ctx->ctx_len + buflen + req->nbytes);
++	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
++	dpaa2_fl_set_len(out_fle, digestsize);
++
++	req_ctx->flc = &ctx->flc[FINALIZE];
++	req_ctx->flc_dma = ctx->flc_dma[FINALIZE];
++	req_ctx->cbk = ahash_done_ctx_src;
++	req_ctx->ctx = &req->base;
++	req_ctx->edesc = edesc;
++
++	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++	if (ret == -EINPROGRESS ||
++	    (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
++		return ret;
++
++unmap_ctx:
++	ahash_unmap_ctx(ctx->dev, edesc, req, digestsize, DMA_FROM_DEVICE);
++	qi_cache_free(edesc);
++	return ret;
++}
++
++static int ahash_digest(struct ahash_request *req)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_request *req_ctx = &state->caam_req;
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	int digestsize = crypto_ahash_digestsize(ahash);
++	int src_nents, mapped_nents;
++	struct ahash_edesc *edesc;
++	int ret = -ENOMEM;
++
++	state->buf_dma = 0;
++
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (src_nents < 0) {
++		dev_err(ctx->dev, "Invalid number of src SG.\n");
++		return src_nents;
++	}
++
++	if (src_nents) {
++		mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
++					  DMA_TO_DEVICE);
++		if (!mapped_nents) {
++			dev_err(ctx->dev, "unable to map source for DMA\n");
++			return ret;
++		}
++	} else {
++		mapped_nents = 0;
++	}
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (!edesc) {
++		dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
++		return ret;
++	}
++
++	edesc->src_nents = src_nents;
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++
++	if (mapped_nents > 1) {
++		int qm_sg_bytes;
++		struct dpaa2_sg_entry *sg_table = &edesc->sgt[0];
++
++		qm_sg_bytes = mapped_nents * sizeof(*sg_table);
++		sg_to_qm_sg_last(req->src, mapped_nents, sg_table, 0);
++		edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
++						  qm_sg_bytes, DMA_TO_DEVICE);
++		if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
++			dev_err(ctx->dev, "unable to map S/G table\n");
++			goto unmap;
++		}
++		edesc->qm_sg_bytes = qm_sg_bytes;
++		dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++	} else {
++		dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src));
++	}
++
++	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
++					DMA_FROM_DEVICE);
++	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
++		dev_err(ctx->dev, "unable to map dst\n");
++		edesc->dst_dma = 0;
++		goto unmap;
++	}
++
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_len(in_fle, req->nbytes);
++	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
++	dpaa2_fl_set_len(out_fle, digestsize);
++
++	req_ctx->flc = &ctx->flc[DIGEST];
++	req_ctx->flc_dma = ctx->flc_dma[DIGEST];
++	req_ctx->cbk = ahash_done;
++	req_ctx->ctx = &req->base;
++	req_ctx->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++	if (ret == -EINPROGRESS ||
++	    (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
++		return ret;
++
++unmap:
++	ahash_unmap(ctx->dev, edesc, req, digestsize);
++	qi_cache_free(edesc);
++	return ret;
++}
++
++static int ahash_final_no_ctx(struct ahash_request *req)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_request *req_ctx = &state->caam_req;
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	u8 *buf = current_buf(state);
++	int buflen = *current_buflen(state);
++	int digestsize = crypto_ahash_digestsize(ahash);
++	struct ahash_edesc *edesc;
++	int ret = -ENOMEM;
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (!edesc)
++		return ret;
++
++	state->buf_dma = dma_map_single(ctx->dev, buf, buflen, DMA_TO_DEVICE);
++	if (dma_mapping_error(ctx->dev, state->buf_dma)) {
++		dev_err(ctx->dev, "unable to map src\n");
++		goto unmap;
++	}
++
++	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
++					DMA_FROM_DEVICE);
++	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
++		dev_err(ctx->dev, "unable to map dst\n");
++		edesc->dst_dma = 0;
++		goto unmap;
++	}
++
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
++	dpaa2_fl_set_addr(in_fle, state->buf_dma);
++	dpaa2_fl_set_len(in_fle, buflen);
++	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
++	dpaa2_fl_set_len(out_fle, digestsize);
++
++	req_ctx->flc = &ctx->flc[DIGEST];
++	req_ctx->flc_dma = ctx->flc_dma[DIGEST];
++	req_ctx->cbk = ahash_done;
++	req_ctx->ctx = &req->base;
++	req_ctx->edesc = edesc;
++
++	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++	if (ret == -EINPROGRESS ||
++	    (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
++		return ret;
++
++unmap:
++	ahash_unmap(ctx->dev, edesc, req, digestsize);
++	qi_cache_free(edesc);
++	return ret;
++}
++
++static int ahash_update_no_ctx(struct ahash_request *req)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_request *req_ctx = &state->caam_req;
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	u8 *buf = current_buf(state);
++	int *buflen = current_buflen(state);
++	u8 *next_buf = alt_buf(state);
++	int *next_buflen = alt_buflen(state);
++	int in_len = *buflen + req->nbytes, to_hash;
++	int qm_sg_bytes, src_nents, mapped_nents;
++	struct ahash_edesc *edesc;
++	int ret = 0;
++
++	*next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
++	to_hash = in_len - *next_buflen;
++
++	if (to_hash) {
++		struct dpaa2_sg_entry *sg_table;
++
++		src_nents = sg_nents_for_len(req->src,
++					     req->nbytes - *next_buflen);
++		if (src_nents < 0) {
++			dev_err(ctx->dev, "Invalid number of src SG.\n");
++			return src_nents;
++		}
++
++		if (src_nents) {
++			mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
++						  DMA_TO_DEVICE);
++			if (!mapped_nents) {
++				dev_err(ctx->dev, "unable to DMA map source\n");
++				return -ENOMEM;
++			}
++		} else {
++			mapped_nents = 0;
++		}
++
++		/* allocate space for base edesc and link tables */
++		edesc = qi_cache_zalloc(GFP_DMA | flags);
++		if (!edesc) {
++			dma_unmap_sg(ctx->dev, req->src, src_nents,
++				     DMA_TO_DEVICE);
++			return -ENOMEM;
++		}
++
++		edesc->src_nents = src_nents;
++		qm_sg_bytes = (1 + mapped_nents) * sizeof(*sg_table);
++		sg_table = &edesc->sgt[0];
++
++		ret = buf_map_to_qm_sg(ctx->dev, sg_table, state);
++		if (ret)
++			goto unmap_ctx;
++
++		sg_to_qm_sg_last(req->src, mapped_nents, sg_table + 1, 0);
++
++		if (*next_buflen)
++			scatterwalk_map_and_copy(next_buf, req->src,
++						 to_hash - *buflen,
++						 *next_buflen, 0);
++
++		edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
++						  qm_sg_bytes, DMA_TO_DEVICE);
++		if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
++			dev_err(ctx->dev, "unable to map S/G table\n");
++			ret = -ENOMEM;
++			goto unmap_ctx;
++		}
++		edesc->qm_sg_bytes = qm_sg_bytes;
++
++		state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx,
++						ctx->ctx_len, DMA_FROM_DEVICE);
++		if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
++			dev_err(ctx->dev, "unable to map ctx\n");
++			state->ctx_dma = 0;
++			ret = -ENOMEM;
++			goto unmap_ctx;
++		}
++
++		memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++		dpaa2_fl_set_final(in_fle, true);
++		dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++		dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++		dpaa2_fl_set_len(in_fle, to_hash);
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(out_fle, state->ctx_dma);
++		dpaa2_fl_set_len(out_fle, ctx->ctx_len);
++
++		req_ctx->flc = &ctx->flc[UPDATE_FIRST];
++		req_ctx->flc_dma = ctx->flc_dma[UPDATE_FIRST];
++		req_ctx->cbk = ahash_done_ctx_dst;
++		req_ctx->ctx = &req->base;
++		req_ctx->edesc = edesc;
++
++		ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++		if (ret != -EINPROGRESS &&
++		    !(ret == -EBUSY &&
++		      req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
++			goto unmap_ctx;
++
++		state->update = ahash_update_ctx;
++		state->finup = ahash_finup_ctx;
++		state->final = ahash_final_ctx;
++	} else if (*next_buflen) {
++		scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
++					 req->nbytes, 0);
++		*buflen = *next_buflen;
++		*next_buflen = 0;
++	}
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "buf@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
++	print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
++		       *next_buflen, 1);
++#endif
++
++	return ret;
++unmap_ctx:
++	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE);
++	qi_cache_free(edesc);
++	return ret;
++}
++
++static int ahash_finup_no_ctx(struct ahash_request *req)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_request *req_ctx = &state->caam_req;
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	int buflen = *current_buflen(state);
++	int qm_sg_bytes, src_nents, mapped_nents;
++	int digestsize = crypto_ahash_digestsize(ahash);
++	struct ahash_edesc *edesc;
++	struct dpaa2_sg_entry *sg_table;
++	int ret;
++
++	src_nents = sg_nents_for_len(req->src, req->nbytes);
++	if (src_nents < 0) {
++		dev_err(ctx->dev, "Invalid number of src SG.\n");
++		return src_nents;
++	}
++
++	if (src_nents) {
++		mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
++					  DMA_TO_DEVICE);
++		if (!mapped_nents) {
++			dev_err(ctx->dev, "unable to DMA map source\n");
++			return -ENOMEM;
++		}
++	} else {
++		mapped_nents = 0;
++	}
++
++	/* allocate space for base edesc and link tables */
++	edesc = qi_cache_zalloc(GFP_DMA | flags);
++	if (!edesc) {
++		dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
++		return -ENOMEM;
++	}
++
++	edesc->src_nents = src_nents;
++	qm_sg_bytes = (2 + mapped_nents) * sizeof(*sg_table);
++	sg_table = &edesc->sgt[0];
++
++	ret = buf_map_to_qm_sg(ctx->dev, sg_table, state);
++	if (ret)
++		goto unmap;
++
++	sg_to_qm_sg_last(req->src, mapped_nents, sg_table + 1, 0);
++
++	edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
++					  DMA_TO_DEVICE);
++	if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
++		dev_err(ctx->dev, "unable to map S/G table\n");
++		ret = -ENOMEM;
++		goto unmap;
++	}
++	edesc->qm_sg_bytes = qm_sg_bytes;
++
++	edesc->dst_dma = dma_map_single(ctx->dev, req->result, digestsize,
++					DMA_FROM_DEVICE);
++	if (dma_mapping_error(ctx->dev, edesc->dst_dma)) {
++		dev_err(ctx->dev, "unable to map dst\n");
++		edesc->dst_dma = 0;
++		ret = -ENOMEM;
++		goto unmap;
++	}
++
++	memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++	dpaa2_fl_set_final(in_fle, true);
++	dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++	dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++	dpaa2_fl_set_len(in_fle, buflen + req->nbytes);
++	dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++	dpaa2_fl_set_addr(out_fle, edesc->dst_dma);
++	dpaa2_fl_set_len(out_fle, digestsize);
++
++	req_ctx->flc = &ctx->flc[DIGEST];
++	req_ctx->flc_dma = ctx->flc_dma[DIGEST];
++	req_ctx->cbk = ahash_done;
++	req_ctx->ctx = &req->base;
++	req_ctx->edesc = edesc;
++	ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++	if (ret != -EINPROGRESS &&
++	    !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
++		goto unmap;
++
++	return ret;
++unmap:
++	ahash_unmap(ctx->dev, edesc, req, digestsize);
++	qi_cache_free(edesc);
++	return -ENOMEM;
++}
++
++static int ahash_update_first(struct ahash_request *req)
++{
++	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
++	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_request *req_ctx = &state->caam_req;
++	struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
++	struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		      GFP_KERNEL : GFP_ATOMIC;
++	u8 *next_buf = alt_buf(state);
++	int *next_buflen = alt_buflen(state);
++	int to_hash;
++	int src_nents, mapped_nents;
++	struct ahash_edesc *edesc;
++	int ret = 0;
++
++	*next_buflen = req->nbytes & (crypto_tfm_alg_blocksize(&ahash->base) -
++				      1);
++	to_hash = req->nbytes - *next_buflen;
++
++	if (to_hash) {
++		struct dpaa2_sg_entry *sg_table;
++
++		src_nents = sg_nents_for_len(req->src,
++					     req->nbytes - (*next_buflen));
++		if (src_nents < 0) {
++			dev_err(ctx->dev, "Invalid number of src SG.\n");
++			return src_nents;
++		}
++
++		if (src_nents) {
++			mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
++						  DMA_TO_DEVICE);
++			if (!mapped_nents) {
++				dev_err(ctx->dev, "unable to map source for DMA\n");
++				return -ENOMEM;
++			}
++		} else {
++			mapped_nents = 0;
++		}
++
++		/* allocate space for base edesc and link tables */
++		edesc = qi_cache_zalloc(GFP_DMA | flags);
++		if (!edesc) {
++			dma_unmap_sg(ctx->dev, req->src, src_nents,
++				     DMA_TO_DEVICE);
++			return -ENOMEM;
++		}
++
++		edesc->src_nents = src_nents;
++		sg_table = &edesc->sgt[0];
++
++		memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
++		dpaa2_fl_set_final(in_fle, true);
++		dpaa2_fl_set_len(in_fle, to_hash);
++
++		if (mapped_nents > 1) {
++			int qm_sg_bytes;
++
++			sg_to_qm_sg_last(req->src, mapped_nents, sg_table, 0);
++			qm_sg_bytes = mapped_nents * sizeof(*sg_table);
++			edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
++							  qm_sg_bytes,
++							  DMA_TO_DEVICE);
++			if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
++				dev_err(ctx->dev, "unable to map S/G table\n");
++				ret = -ENOMEM;
++				goto unmap_ctx;
++			}
++			edesc->qm_sg_bytes = qm_sg_bytes;
++			dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
++			dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
++		} else {
++			dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
++			dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src));
++		}
++
++		if (*next_buflen)
++			scatterwalk_map_and_copy(next_buf, req->src, to_hash,
++						 *next_buflen, 0);
++
++		state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx,
++						ctx->ctx_len, DMA_FROM_DEVICE);
++		if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
++			dev_err(ctx->dev, "unable to map ctx\n");
++			state->ctx_dma = 0;
++			ret = -ENOMEM;
++			goto unmap_ctx;
++		}
++
++		dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
++		dpaa2_fl_set_addr(out_fle, state->ctx_dma);
++		dpaa2_fl_set_len(out_fle, ctx->ctx_len);
++
++		req_ctx->flc = &ctx->flc[UPDATE_FIRST];
++		req_ctx->flc_dma = ctx->flc_dma[UPDATE_FIRST];
++		req_ctx->cbk = ahash_done_ctx_dst;
++		req_ctx->ctx = &req->base;
++		req_ctx->edesc = edesc;
++
++		ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
++		if (ret != -EINPROGRESS &&
++		    !(ret == -EBUSY && req->base.flags &
++		      CRYPTO_TFM_REQ_MAY_BACKLOG))
++			goto unmap_ctx;
++
++		state->update = ahash_update_ctx;
++		state->finup = ahash_finup_ctx;
++		state->final = ahash_final_ctx;
++	} else if (*next_buflen) {
++		state->update = ahash_update_no_ctx;
++		state->finup = ahash_finup_no_ctx;
++		state->final = ahash_final_no_ctx;
++		scatterwalk_map_and_copy(next_buf, req->src, 0,
++					 req->nbytes, 0);
++		switch_buf(state);
++	}
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "next buf@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, next_buf, *next_buflen, 1);
++#endif
++
++	return ret;
++unmap_ctx:
++	ahash_unmap_ctx(ctx->dev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE);
++	qi_cache_free(edesc);
++	return ret;
++}
++
++static int ahash_finup_first(struct ahash_request *req)
++{
++	return ahash_digest(req);
++}
++
++static int ahash_init(struct ahash_request *req)
++{
++	struct caam_hash_state *state = ahash_request_ctx(req);
++
++	state->update = ahash_update_first;
++	state->finup = ahash_finup_first;
++	state->final = ahash_final_no_ctx;
++
++	state->ctx_dma = 0;
++	state->current_buf = 0;
++	state->buf_dma = 0;
++	state->buflen_0 = 0;
++	state->buflen_1 = 0;
++
++	return 0;
++}
++
++static int ahash_update(struct ahash_request *req)
++{
++	struct caam_hash_state *state = ahash_request_ctx(req);
++
++	return state->update(req);
++}
++
++static int ahash_finup(struct ahash_request *req)
++{
++	struct caam_hash_state *state = ahash_request_ctx(req);
++
++	return state->finup(req);
++}
++
++static int ahash_final(struct ahash_request *req)
++{
++	struct caam_hash_state *state = ahash_request_ctx(req);
++
++	return state->final(req);
++}
++
++static int ahash_export(struct ahash_request *req, void *out)
++{
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	struct caam_export_state *export = out;
++	int len;
++	u8 *buf;
++
++	if (state->current_buf) {
++		buf = state->buf_1;
++		len = state->buflen_1;
++	} else {
++		buf = state->buf_0;
++		len = state->buflen_0;
++	}
++
++	memcpy(export->buf, buf, len);
++	memcpy(export->caam_ctx, state->caam_ctx, sizeof(export->caam_ctx));
++	export->buflen = len;
++	export->update = state->update;
++	export->final = state->final;
++	export->finup = state->finup;
++
++	return 0;
++}
++
++static int ahash_import(struct ahash_request *req, const void *in)
++{
++	struct caam_hash_state *state = ahash_request_ctx(req);
++	const struct caam_export_state *export = in;
++
++	memset(state, 0, sizeof(*state));
++	memcpy(state->buf_0, export->buf, export->buflen);
++	memcpy(state->caam_ctx, export->caam_ctx, sizeof(state->caam_ctx));
++	state->buflen_0 = export->buflen;
++	state->update = export->update;
++	state->final = export->final;
++	state->finup = export->finup;
++
++	return 0;
++}
++
++struct caam_hash_template {
++	char name[CRYPTO_MAX_ALG_NAME];
++	char driver_name[CRYPTO_MAX_ALG_NAME];
++	char hmac_name[CRYPTO_MAX_ALG_NAME];
++	char hmac_driver_name[CRYPTO_MAX_ALG_NAME];
++	unsigned int blocksize;
++	struct ahash_alg template_ahash;
++	u32 alg_type;
++};
++
++/* ahash descriptors */
++static struct caam_hash_template driver_hash[] = {
++	{
++		.name = "sha1",
++		.driver_name = "sha1-caam-qi2",
++		.hmac_name = "hmac(sha1)",
++		.hmac_driver_name = "hmac-sha1-caam-qi2",
++		.blocksize = SHA1_BLOCK_SIZE,
++		.template_ahash = {
++			.init = ahash_init,
++			.update = ahash_update,
++			.final = ahash_final,
++			.finup = ahash_finup,
++			.digest = ahash_digest,
++			.export = ahash_export,
++			.import = ahash_import,
++			.setkey = ahash_setkey,
++			.halg = {
++				.digestsize = SHA1_DIGEST_SIZE,
++				.statesize = sizeof(struct caam_export_state),
++			},
++		},
++		.alg_type = OP_ALG_ALGSEL_SHA1,
++	}, {
++		.name = "sha224",
++		.driver_name = "sha224-caam-qi2",
++		.hmac_name = "hmac(sha224)",
++		.hmac_driver_name = "hmac-sha224-caam-qi2",
++		.blocksize = SHA224_BLOCK_SIZE,
++		.template_ahash = {
++			.init = ahash_init,
++			.update = ahash_update,
++			.final = ahash_final,
++			.finup = ahash_finup,
++			.digest = ahash_digest,
++			.export = ahash_export,
++			.import = ahash_import,
++			.setkey = ahash_setkey,
++			.halg = {
++				.digestsize = SHA224_DIGEST_SIZE,
++				.statesize = sizeof(struct caam_export_state),
++			},
++		},
++		.alg_type = OP_ALG_ALGSEL_SHA224,
++	}, {
++		.name = "sha256",
++		.driver_name = "sha256-caam-qi2",
++		.hmac_name = "hmac(sha256)",
++		.hmac_driver_name = "hmac-sha256-caam-qi2",
++		.blocksize = SHA256_BLOCK_SIZE,
++		.template_ahash = {
++			.init = ahash_init,
++			.update = ahash_update,
++			.final = ahash_final,
++			.finup = ahash_finup,
++			.digest = ahash_digest,
++			.export = ahash_export,
++			.import = ahash_import,
++			.setkey = ahash_setkey,
++			.halg = {
++				.digestsize = SHA256_DIGEST_SIZE,
++				.statesize = sizeof(struct caam_export_state),
++			},
++		},
++		.alg_type = OP_ALG_ALGSEL_SHA256,
++	}, {
++		.name = "sha384",
++		.driver_name = "sha384-caam-qi2",
++		.hmac_name = "hmac(sha384)",
++		.hmac_driver_name = "hmac-sha384-caam-qi2",
++		.blocksize = SHA384_BLOCK_SIZE,
++		.template_ahash = {
++			.init = ahash_init,
++			.update = ahash_update,
++			.final = ahash_final,
++			.finup = ahash_finup,
++			.digest = ahash_digest,
++			.export = ahash_export,
++			.import = ahash_import,
++			.setkey = ahash_setkey,
++			.halg = {
++				.digestsize = SHA384_DIGEST_SIZE,
++				.statesize = sizeof(struct caam_export_state),
++			},
++		},
++		.alg_type = OP_ALG_ALGSEL_SHA384,
++	}, {
++		.name = "sha512",
++		.driver_name = "sha512-caam-qi2",
++		.hmac_name = "hmac(sha512)",
++		.hmac_driver_name = "hmac-sha512-caam-qi2",
++		.blocksize = SHA512_BLOCK_SIZE,
++		.template_ahash = {
++			.init = ahash_init,
++			.update = ahash_update,
++			.final = ahash_final,
++			.finup = ahash_finup,
++			.digest = ahash_digest,
++			.export = ahash_export,
++			.import = ahash_import,
++			.setkey = ahash_setkey,
++			.halg = {
++				.digestsize = SHA512_DIGEST_SIZE,
++				.statesize = sizeof(struct caam_export_state),
++			},
++		},
++		.alg_type = OP_ALG_ALGSEL_SHA512,
++	}, {
++		.name = "md5",
++		.driver_name = "md5-caam-qi2",
++		.hmac_name = "hmac(md5)",
++		.hmac_driver_name = "hmac-md5-caam-qi2",
++		.blocksize = MD5_BLOCK_WORDS * 4,
++		.template_ahash = {
++			.init = ahash_init,
++			.update = ahash_update,
++			.final = ahash_final,
++			.finup = ahash_finup,
++			.digest = ahash_digest,
++			.export = ahash_export,
++			.import = ahash_import,
++			.setkey = ahash_setkey,
++			.halg = {
++				.digestsize = MD5_DIGEST_SIZE,
++				.statesize = sizeof(struct caam_export_state),
++			},
++		},
++		.alg_type = OP_ALG_ALGSEL_MD5,
++	}
++};
++
++struct caam_hash_alg {
++	struct list_head entry;
++	struct device *dev;
++	int alg_type;
++	struct ahash_alg ahash_alg;
++};
++
++static int caam_hash_cra_init(struct crypto_tfm *tfm)
++{
++	struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
++	struct crypto_alg *base = tfm->__crt_alg;
++	struct hash_alg_common *halg =
++		 container_of(base, struct hash_alg_common, base);
++	struct ahash_alg *alg =
++		 container_of(halg, struct ahash_alg, halg);
++	struct caam_hash_alg *caam_hash =
++		 container_of(alg, struct caam_hash_alg, ahash_alg);
++	struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
++	/* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
++	static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
++					 HASH_MSG_LEN + SHA1_DIGEST_SIZE,
++					 HASH_MSG_LEN + 32,
++					 HASH_MSG_LEN + SHA256_DIGEST_SIZE,
++					 HASH_MSG_LEN + 64,
++					 HASH_MSG_LEN + SHA512_DIGEST_SIZE };
++	dma_addr_t dma_addr;
++	int i;
++
++	ctx->dev = caam_hash->dev;
++
++	dma_addr = dma_map_single_attrs(ctx->dev, ctx->flc, sizeof(ctx->flc),
++					DMA_BIDIRECTIONAL,
++					DMA_ATTR_SKIP_CPU_SYNC);
++	if (dma_mapping_error(ctx->dev, dma_addr)) {
++		dev_err(ctx->dev, "unable to map shared descriptors\n");
++		return -ENOMEM;
++	}
++
++	for (i = 0; i < HASH_NUM_OP; i++)
++		ctx->flc_dma[i] = dma_addr + i * sizeof(ctx->flc[i]);
++
++	/* copy descriptor header template value */
++	ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
++
++	ctx->ctx_len = runninglen[(ctx->adata.algtype &
++				   OP_ALG_ALGSEL_SUBMASK) >>
++				  OP_ALG_ALGSEL_SHIFT];
++
++	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
++				 sizeof(struct caam_hash_state));
++
++	return ahash_set_sh_desc(ahash);
++}
++
++static void caam_hash_cra_exit(struct crypto_tfm *tfm)
++{
++	struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
++
++	dma_unmap_single_attrs(ctx->dev, ctx->flc_dma[0], sizeof(ctx->flc),
++			       DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC);
++}
++
++static struct caam_hash_alg *caam_hash_alloc(struct device *dev,
++	struct caam_hash_template *template, bool keyed)
++{
++	struct caam_hash_alg *t_alg;
++	struct ahash_alg *halg;
++	struct crypto_alg *alg;
++
++	t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
++	if (!t_alg)
++		return ERR_PTR(-ENOMEM);
++
++	t_alg->ahash_alg = template->template_ahash;
++	halg = &t_alg->ahash_alg;
++	alg = &halg->halg.base;
++
++	if (keyed) {
++		snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
++			 template->hmac_name);
++		snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
++			 template->hmac_driver_name);
++	} else {
++		snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
++			 template->name);
++		snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
++			 template->driver_name);
++		t_alg->ahash_alg.setkey = NULL;
++	}
++	alg->cra_module = THIS_MODULE;
++	alg->cra_init = caam_hash_cra_init;
++	alg->cra_exit = caam_hash_cra_exit;
++	alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
++	alg->cra_priority = CAAM_CRA_PRIORITY;
++	alg->cra_blocksize = template->blocksize;
++	alg->cra_alignmask = 0;
++	alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH;
++	alg->cra_type = &crypto_ahash_type;
++
++	t_alg->alg_type = template->alg_type;
++	t_alg->dev = dev;
++
++	return t_alg;
++}
++
++static void dpaa2_caam_fqdan_cb(struct dpaa2_io_notification_ctx *nctx)
++{
++	struct dpaa2_caam_priv_per_cpu *ppriv;
++
++	ppriv = container_of(nctx, struct dpaa2_caam_priv_per_cpu, nctx);
++	napi_schedule_irqoff(&ppriv->napi);
++}
++
++static int __cold dpaa2_dpseci_dpio_setup(struct dpaa2_caam_priv *priv)
++{
++	struct device *dev = priv->dev;
++	struct dpaa2_io_notification_ctx *nctx;
++	struct dpaa2_caam_priv_per_cpu *ppriv;
++	int err, i = 0, cpu;
++
++	for_each_online_cpu(cpu) {
++		ppriv = per_cpu_ptr(priv->ppriv, cpu);
++		ppriv->priv = priv;
++		nctx = &ppriv->nctx;
++		nctx->is_cdan = 0;
++		nctx->id = ppriv->rsp_fqid;
++		nctx->desired_cpu = cpu;
++		nctx->cb = dpaa2_caam_fqdan_cb;
++
++		/* Register notification callbacks */
++		err = dpaa2_io_service_register(NULL, nctx);
++		if (unlikely(err)) {
++			dev_dbg(dev, "No affine DPIO for cpu %d\n", cpu);
++			nctx->cb = NULL;
++			/*
++			 * If no affine DPIO for this core, there's probably
++			 * none available for next cores either. Signal we want
++			 * to retry later, in case the DPIO devices weren't
++			 * probed yet.
++			 */
++			err = -EPROBE_DEFER;
++			goto err;
++		}
++
++		ppriv->store = dpaa2_io_store_create(DPAA2_CAAM_STORE_SIZE,
++						     dev);
++		if (unlikely(!ppriv->store)) {
++			dev_err(dev, "dpaa2_io_store_create() failed\n");
++			goto err;
++		}
++
++		if (++i == priv->num_pairs)
++			break;
++	}
++
++	return 0;
++
++err:
++	for_each_online_cpu(cpu) {
++		ppriv = per_cpu_ptr(priv->ppriv, cpu);
++		if (!ppriv->nctx.cb)
++			break;
++		dpaa2_io_service_deregister(NULL, &ppriv->nctx);
++	}
++
++	for_each_online_cpu(cpu) {
++		ppriv = per_cpu_ptr(priv->ppriv, cpu);
++		if (!ppriv->store)
++			break;
++		dpaa2_io_store_destroy(ppriv->store);
++	}
++
++	return err;
++}
++
++static void __cold dpaa2_dpseci_dpio_free(struct dpaa2_caam_priv *priv)
++{
++	struct dpaa2_caam_priv_per_cpu *ppriv;
++	int i = 0, cpu;
++
++	for_each_online_cpu(cpu) {
++		ppriv = per_cpu_ptr(priv->ppriv, cpu);
++		dpaa2_io_service_deregister(NULL, &ppriv->nctx);
++		dpaa2_io_store_destroy(ppriv->store);
++
++		if (++i == priv->num_pairs)
++			return;
++	}
++}
++
++static int dpaa2_dpseci_bind(struct dpaa2_caam_priv *priv)
++{
++	struct dpseci_rx_queue_cfg rx_queue_cfg;
++	struct device *dev = priv->dev;
++	struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
++	struct dpaa2_caam_priv_per_cpu *ppriv;
++	int err = 0, i = 0, cpu;
++
++	/* Configure Rx queues */
++	for_each_online_cpu(cpu) {
++		ppriv = per_cpu_ptr(priv->ppriv, cpu);
++
++		rx_queue_cfg.options = DPSECI_QUEUE_OPT_DEST |
++				       DPSECI_QUEUE_OPT_USER_CTX;
++		rx_queue_cfg.order_preservation_en = 0;
++		rx_queue_cfg.dest_cfg.dest_type = DPSECI_DEST_DPIO;
++		rx_queue_cfg.dest_cfg.dest_id = ppriv->nctx.dpio_id;
++		/*
++		 * Rx priority (WQ) doesn't really matter, since we use
++		 * pull mode, i.e. volatile dequeues from specific FQs
++		 */
++		rx_queue_cfg.dest_cfg.priority = 0;
++		rx_queue_cfg.user_ctx = ppriv->nctx.qman64;
++
++		err = dpseci_set_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
++					  &rx_queue_cfg);
++		if (err) {
++			dev_err(dev, "dpseci_set_rx_queue() failed with err %d\n",
++				err);
++			return err;
++		}
++
++		if (++i == priv->num_pairs)
++			break;
++	}
++
++	return err;
++}
++
++static void dpaa2_dpseci_congestion_free(struct dpaa2_caam_priv *priv)
++{
++	struct device *dev = priv->dev;
++
++	if (!priv->cscn_mem)
++		return;
++
++	dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
++	kfree(priv->cscn_mem);
++}
++
++static void dpaa2_dpseci_free(struct dpaa2_caam_priv *priv)
++{
++	struct device *dev = priv->dev;
++	struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
++
++	dpaa2_dpseci_congestion_free(priv);
++	dpseci_close(priv->mc_io, 0, ls_dev->mc_handle);
++}
++
++static void dpaa2_caam_process_fd(struct dpaa2_caam_priv *priv,
++				  const struct dpaa2_fd *fd)
++{
++	struct caam_request *req;
++	u32 fd_err;
++
++	if (dpaa2_fd_get_format(fd) != dpaa2_fd_list) {
++		dev_err(priv->dev, "Only Frame List FD format is supported!\n");
++		return;
++	}
++
++	fd_err = dpaa2_fd_get_ctrl(fd) & FD_CTRL_ERR_MASK;
++	if (unlikely(fd_err))
++		dev_err(priv->dev, "FD error: %08x\n", fd_err);
++
++	/*
++	 * FD[ADDR] is guaranteed to be valid, irrespective of errors reported
++	 * in FD[ERR] or FD[FRC].
++	 */
++	req = dpaa2_caam_iova_to_virt(priv, dpaa2_fd_get_addr(fd));
++	dma_unmap_single(priv->dev, req->fd_flt_dma, sizeof(req->fd_flt),
++			 DMA_BIDIRECTIONAL);
++	req->cbk(req->ctx, dpaa2_fd_get_frc(fd));
++}
++
++static int dpaa2_caam_pull_fq(struct dpaa2_caam_priv_per_cpu *ppriv)
++{
++	int err;
++
++	/* Retry while portal is busy */
++	do {
++		err = dpaa2_io_service_pull_fq(NULL, ppriv->rsp_fqid,
++					       ppriv->store);
++	} while (err == -EBUSY);
++
++	if (unlikely(err))
++		dev_err(ppriv->priv->dev, "dpaa2_io_service_pull err %d", err);
++
++	return err;
++}
++
++static int dpaa2_caam_store_consume(struct dpaa2_caam_priv_per_cpu *ppriv)
++{
++	struct dpaa2_dq *dq;
++	int cleaned = 0, is_last;
++
++	do {
++		dq = dpaa2_io_store_next(ppriv->store, &is_last);
++		if (unlikely(!dq)) {
++			if (unlikely(!is_last)) {
++				dev_dbg(ppriv->priv->dev,
++					"FQ %d returned no valid frames\n",
++					ppriv->rsp_fqid);
++				/*
++				 * MUST retry until we get some sort of
++				 * valid response token (be it "empty dequeue"
++				 * or a valid frame).
++				 */
++				continue;
++			}
++			break;
++		}
++
++		/* Process FD */
++		dpaa2_caam_process_fd(ppriv->priv, dpaa2_dq_fd(dq));
++		cleaned++;
++	} while (!is_last);
++
++	return cleaned;
++}
++
++static int dpaa2_dpseci_poll(struct napi_struct *napi, int budget)
++{
++	struct dpaa2_caam_priv_per_cpu *ppriv;
++	struct dpaa2_caam_priv *priv;
++	int err, cleaned = 0, store_cleaned;
++
++	ppriv = container_of(napi, struct dpaa2_caam_priv_per_cpu, napi);
++	priv = ppriv->priv;
++
++	if (unlikely(dpaa2_caam_pull_fq(ppriv)))
++		return 0;
++
++	do {
++		store_cleaned = dpaa2_caam_store_consume(ppriv);
++		cleaned += store_cleaned;
++
++		if (store_cleaned == 0 ||
++		    cleaned > budget - DPAA2_CAAM_STORE_SIZE)
++			break;
++
++		/* Try to dequeue some more */
++		err = dpaa2_caam_pull_fq(ppriv);
++		if (unlikely(err))
++			break;
++	} while (1);
++
++	if (cleaned < budget) {
++		napi_complete_done(napi, cleaned);
++		err = dpaa2_io_service_rearm(NULL, &ppriv->nctx);
++		if (unlikely(err))
++			dev_err(priv->dev, "Notification rearm failed: %d\n",
++				err);
++	}
++
++	return cleaned;
++}
++
++static int dpaa2_dpseci_congestion_setup(struct dpaa2_caam_priv *priv,
++					 u16 token)
++{
++	struct dpseci_congestion_notification_cfg cong_notif_cfg = { 0 };
++	struct device *dev = priv->dev;
++	int err;
++
++	/*
++	 * Congestion group feature supported starting with DPSECI API v5.1
++	 * and only when object has been created with this capability.
++	 */
++	if ((DPSECI_VER(priv->major_ver, priv->minor_ver) < DPSECI_VER(5, 1)) ||
++	    !(priv->dpseci_attr.options & DPSECI_OPT_HAS_CG))
++		return 0;
++
++	priv->cscn_mem = kzalloc(DPAA2_CSCN_SIZE + DPAA2_CSCN_ALIGN,
++				 GFP_KERNEL | GFP_DMA);
++	if (!priv->cscn_mem)
++		return -ENOMEM;
++
++	priv->cscn_mem_aligned = PTR_ALIGN(priv->cscn_mem, DPAA2_CSCN_ALIGN);
++	priv->cscn_dma = dma_map_single(dev, priv->cscn_mem_aligned,
++					DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
++	if (dma_mapping_error(dev, priv->cscn_dma)) {
++		dev_err(dev, "Error mapping CSCN memory area\n");
++		err = -ENOMEM;
++		goto err_dma_map;
++	}
++
++	cong_notif_cfg.units = DPSECI_CONGESTION_UNIT_BYTES;
++	cong_notif_cfg.threshold_entry = DPAA2_SEC_CONG_ENTRY_THRESH;
++	cong_notif_cfg.threshold_exit = DPAA2_SEC_CONG_EXIT_THRESH;
++	cong_notif_cfg.message_ctx = (u64)priv;
++	cong_notif_cfg.message_iova = priv->cscn_dma;
++	cong_notif_cfg.notification_mode = DPSECI_CGN_MODE_WRITE_MEM_ON_ENTER |
++					DPSECI_CGN_MODE_WRITE_MEM_ON_EXIT |
++					DPSECI_CGN_MODE_COHERENT_WRITE;
++
++	err = dpseci_set_congestion_notification(priv->mc_io, 0, token,
++						 &cong_notif_cfg);
++	if (err) {
++		dev_err(dev, "dpseci_set_congestion_notification failed\n");
++		goto err_set_cong;
++	}
++
++	return 0;
++
++err_set_cong:
++	dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
++err_dma_map:
++	kfree(priv->cscn_mem);
++
++	return err;
++}
++
++static int __cold dpaa2_dpseci_setup(struct fsl_mc_device *ls_dev)
++{
++	struct device *dev = &ls_dev->dev;
++	struct dpaa2_caam_priv *priv;
++	struct dpaa2_caam_priv_per_cpu *ppriv;
++	int err, cpu;
++	u8 i;
++
++	priv = dev_get_drvdata(dev);
++
++	priv->dev = dev;
++	priv->dpsec_id = ls_dev->obj_desc.id;
++
++	/* Get a handle for the DPSECI this interface is associate with */
++	err = dpseci_open(priv->mc_io, 0, priv->dpsec_id, &ls_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpsec_open() failed: %d\n", err);
++		goto err_open;
++	}
++
++	dev_info(dev, "Opened dpseci object successfully\n");
++
++	err = dpseci_get_api_version(priv->mc_io, 0, &priv->major_ver,
++				     &priv->minor_ver);
++	if (err) {
++		dev_err(dev, "dpseci_get_api_version() failed\n");
++		goto err_get_vers;
++	}
++
++	err = dpseci_get_attributes(priv->mc_io, 0, ls_dev->mc_handle,
++				    &priv->dpseci_attr);
++	if (err) {
++		dev_err(dev, "dpseci_get_attributes() failed\n");
++		goto err_get_vers;
++	}
++
++	err = dpseci_get_sec_attr(priv->mc_io, 0, ls_dev->mc_handle,
++				  &priv->sec_attr);
++	if (err) {
++		dev_err(dev, "dpseci_get_sec_attr() failed\n");
++		goto err_get_vers;
++	}
++
++	err = dpaa2_dpseci_congestion_setup(priv, ls_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "setup_congestion() failed\n");
++		goto err_get_vers;
++	}
++
++	priv->num_pairs = min(priv->dpseci_attr.num_rx_queues,
++			      priv->dpseci_attr.num_tx_queues);
++	if (priv->num_pairs > num_online_cpus()) {
++		dev_warn(dev, "%d queues won't be used\n",
++			 priv->num_pairs - num_online_cpus());
++		priv->num_pairs = num_online_cpus();
++	}
++
++	for (i = 0; i < priv->dpseci_attr.num_rx_queues; i++) {
++		err = dpseci_get_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
++					  &priv->rx_queue_attr[i]);
++		if (err) {
++			dev_err(dev, "dpseci_get_rx_queue() failed\n");
++			goto err_get_rx_queue;
++		}
++	}
++
++	for (i = 0; i < priv->dpseci_attr.num_tx_queues; i++) {
++		err = dpseci_get_tx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
++					  &priv->tx_queue_attr[i]);
++		if (err) {
++			dev_err(dev, "dpseci_get_tx_queue() failed\n");
++			goto err_get_rx_queue;
++		}
++	}
++
++	i = 0;
++	for_each_online_cpu(cpu) {
++		dev_info(dev, "prio %d: rx queue %d, tx queue %d\n", i,
++			 priv->rx_queue_attr[i].fqid,
++			 priv->tx_queue_attr[i].fqid);
++
++		ppriv = per_cpu_ptr(priv->ppriv, cpu);
++		ppriv->req_fqid = priv->tx_queue_attr[i].fqid;
++		ppriv->rsp_fqid = priv->rx_queue_attr[i].fqid;
++		ppriv->prio = i;
++
++		ppriv->net_dev.dev = *dev;
++		INIT_LIST_HEAD(&ppriv->net_dev.napi_list);
++		netif_napi_add(&ppriv->net_dev, &ppriv->napi, dpaa2_dpseci_poll,
++			       DPAA2_CAAM_NAPI_WEIGHT);
++		if (++i == priv->num_pairs)
++			break;
++	}
++
++	return 0;
++
++err_get_rx_queue:
++	dpaa2_dpseci_congestion_free(priv);
++err_get_vers:
++	dpseci_close(priv->mc_io, 0, ls_dev->mc_handle);
++err_open:
++	return err;
++}
++
++static int dpaa2_dpseci_enable(struct dpaa2_caam_priv *priv)
++{
++	struct device *dev = priv->dev;
++	struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
++	struct dpaa2_caam_priv_per_cpu *ppriv;
++	int err, i;
++
++	for (i = 0; i < priv->num_pairs; i++) {
++		ppriv = per_cpu_ptr(priv->ppriv, i);
++		napi_enable(&ppriv->napi);
++	}
++
++	err = dpseci_enable(priv->mc_io, 0, ls_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpseci_enable() failed\n");
++		return err;
++	}
++
++	dev_info(dev, "DPSECI version %d.%d\n",
++		 priv->major_ver,
++		 priv->minor_ver);
++
++	return 0;
++}
++
++static int __cold dpaa2_dpseci_disable(struct dpaa2_caam_priv *priv)
++{
++	struct device *dev = priv->dev;
++	struct dpaa2_caam_priv_per_cpu *ppriv;
++	struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
++	int i, err = 0, enabled;
++
++	err = dpseci_disable(priv->mc_io, 0, ls_dev->mc_handle);
++	if (err) {
++		dev_err(dev, "dpseci_disable() failed\n");
++		return err;
++	}
++
++	err = dpseci_is_enabled(priv->mc_io, 0, ls_dev->mc_handle, &enabled);
++	if (err) {
++		dev_err(dev, "dpseci_is_enabled() failed\n");
++		return err;
++	}
++
++	dev_dbg(dev, "disable: %s\n", enabled ? "false" : "true");
++
++	for (i = 0; i < priv->num_pairs; i++) {
++		ppriv = per_cpu_ptr(priv->ppriv, i);
++		napi_disable(&ppriv->napi);
++		netif_napi_del(&ppriv->napi);
++	}
++
++	return 0;
++}
++
++static struct list_head alg_list;
++static struct list_head hash_list;
++
++static int dpaa2_caam_probe(struct fsl_mc_device *dpseci_dev)
++{
++	struct device *dev;
++	struct dpaa2_caam_priv *priv;
++	int i, err = 0;
++	bool registered = false;
++
++	/*
++	 * There is no way to get CAAM endianness - there is no direct register
++	 * space access and MC f/w does not provide this attribute.
++	 * All DPAA2-based SoCs have little endian CAAM, thus hard-code this
++	 * property.
++	 */
++	caam_little_end = true;
++
++	caam_imx = false;
++
++	dev = &dpseci_dev->dev;
++
++	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	dev_set_drvdata(dev, priv);
++
++	priv->domain = iommu_get_domain_for_dev(dev);
++
++	qi_cache = kmem_cache_create("dpaa2_caamqicache", CAAM_QI_MEMCACHE_SIZE,
++				     0, SLAB_CACHE_DMA, NULL);
++	if (!qi_cache) {
++		dev_err(dev, "Can't allocate SEC cache\n");
++		err = -ENOMEM;
++		goto err_qicache;
++	}
++
++	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
++	if (err) {
++		dev_err(dev, "dma_set_mask_and_coherent() failed\n");
++		goto err_dma_mask;
++	}
++
++	/* Obtain a MC portal */
++	err = fsl_mc_portal_allocate(dpseci_dev, 0, &priv->mc_io);
++	if (err) {
++		if (err == -ENXIO)
++			err = -EPROBE_DEFER;
++		else
++			dev_err(dev, "MC portal allocation failed\n");
++
++		goto err_dma_mask;
++	}
++
++	priv->ppriv = alloc_percpu(*priv->ppriv);
++	if (!priv->ppriv) {
++		dev_err(dev, "alloc_percpu() failed\n");
++		goto err_alloc_ppriv;
++	}
++
++	/* DPSECI initialization */
++	err = dpaa2_dpseci_setup(dpseci_dev);
++	if (err < 0) {
++		dev_err(dev, "dpaa2_dpseci_setup() failed\n");
++		goto err_dpseci_setup;
++	}
++
++	/* DPIO */
++	err = dpaa2_dpseci_dpio_setup(priv);
++	if (err) {
++		dev_err(dev, "dpaa2_dpseci_dpio_setup() failed\n");
++		goto err_dpio_setup;
++	}
++
++	/* DPSECI binding to DPIO */
++	err = dpaa2_dpseci_bind(priv);
++	if (err) {
++		dev_err(dev, "dpaa2_dpseci_bind() failed\n");
++		goto err_bind;
++	}
++
++	/* DPSECI enable */
++	err = dpaa2_dpseci_enable(priv);
++	if (err) {
++		dev_err(dev, "dpaa2_dpseci_enable() failed");
++		goto err_bind;
++	}
++
++	/* register crypto algorithms the device supports */
++	INIT_LIST_HEAD(&alg_list);
++	for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
++		struct caam_crypto_alg *t_alg;
++		struct caam_alg_template *alg = driver_algs + i;
++		u32 alg_sel = alg->class1_alg_type & OP_ALG_ALGSEL_MASK;
++
++		/* Skip DES algorithms if not supported by device */
++		if (!priv->sec_attr.des_acc_num &&
++		    ((alg_sel == OP_ALG_ALGSEL_3DES) ||
++		     (alg_sel == OP_ALG_ALGSEL_DES)))
++			continue;
++
++		/* Skip AES algorithms if not supported by device */
++		if (!priv->sec_attr.aes_acc_num &&
++		    (alg_sel == OP_ALG_ALGSEL_AES))
++			continue;
++
++		t_alg = caam_alg_alloc(alg);
++		if (IS_ERR(t_alg)) {
++			err = PTR_ERR(t_alg);
++			dev_warn(dev, "%s alg allocation failed: %d\n",
++				 alg->driver_name, err);
++			continue;
++		}
++		t_alg->caam.dev = dev;
++
++		err = crypto_register_alg(&t_alg->crypto_alg);
++		if (err) {
++			dev_warn(dev, "%s alg registration failed: %d\n",
++				 t_alg->crypto_alg.cra_driver_name, err);
++			kfree(t_alg);
++			continue;
++		}
++
++		list_add_tail(&t_alg->entry, &alg_list);
++		registered = true;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
++		struct caam_aead_alg *t_alg = driver_aeads + i;
++		u32 c1_alg_sel = t_alg->caam.class1_alg_type &
++				 OP_ALG_ALGSEL_MASK;
++		u32 c2_alg_sel = t_alg->caam.class2_alg_type &
++				 OP_ALG_ALGSEL_MASK;
++
++		/* Skip DES algorithms if not supported by device */
++		if (!priv->sec_attr.des_acc_num &&
++		    ((c1_alg_sel == OP_ALG_ALGSEL_3DES) ||
++		     (c1_alg_sel == OP_ALG_ALGSEL_DES)))
++			continue;
++
++		/* Skip AES algorithms if not supported by device */
++		if (!priv->sec_attr.aes_acc_num &&
++		    (c1_alg_sel == OP_ALG_ALGSEL_AES))
++			continue;
++
++		/*
++		 * Skip algorithms requiring message digests
++		 * if MD not supported by device.
++		 */
++		if (!priv->sec_attr.md_acc_num && c2_alg_sel)
++			continue;
++
++		t_alg->caam.dev = dev;
++		caam_aead_alg_init(t_alg);
++
++		err = crypto_register_aead(&t_alg->aead);
++		if (err) {
++			dev_warn(dev, "%s alg registration failed: %d\n",
++				 t_alg->aead.base.cra_driver_name, err);
++			continue;
++		}
++
++		t_alg->registered = true;
++		registered = true;
++	}
++	if (registered)
++		dev_info(dev, "algorithms registered in /proc/crypto\n");
++
++	/* register hash algorithms the device supports */
++	INIT_LIST_HEAD(&hash_list);
++
++	/*
++	 * Skip registration of any hashing algorithms if MD block
++	 * is not present.
++	 */
++	if (!priv->sec_attr.md_acc_num)
++		return 0;
++
++	for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
++		struct caam_hash_alg *t_alg;
++		struct caam_hash_template *alg = driver_hash + i;
++
++		/* register hmac version */
++		t_alg = caam_hash_alloc(dev, alg, true);
++		if (IS_ERR(t_alg)) {
++			err = PTR_ERR(t_alg);
++			dev_warn(dev, "%s hash alg allocation failed: %d\n",
++				 alg->driver_name, err);
++			continue;
++		}
++
++		err = crypto_register_ahash(&t_alg->ahash_alg);
++		if (err) {
++			dev_warn(dev, "%s alg registration failed: %d\n",
++				 t_alg->ahash_alg.halg.base.cra_driver_name,
++				 err);
++			kfree(t_alg);
++		} else {
++			list_add_tail(&t_alg->entry, &hash_list);
++		}
++
++		/* register unkeyed version */
++		t_alg = caam_hash_alloc(dev, alg, false);
++		if (IS_ERR(t_alg)) {
++			err = PTR_ERR(t_alg);
++			dev_warn(dev, "%s alg allocation failed: %d\n",
++				 alg->driver_name, err);
++			continue;
++		}
++
++		err = crypto_register_ahash(&t_alg->ahash_alg);
++		if (err) {
++			dev_warn(dev, "%s alg registration failed: %d\n",
++				 t_alg->ahash_alg.halg.base.cra_driver_name,
++				 err);
++			kfree(t_alg);
++		} else {
++			list_add_tail(&t_alg->entry, &hash_list);
++		}
++	}
++	if (!list_empty(&hash_list))
++		dev_info(dev, "hash algorithms registered in /proc/crypto\n");
++
++	return err;
++
++err_bind:
++	dpaa2_dpseci_dpio_free(priv);
++err_dpio_setup:
++	dpaa2_dpseci_free(priv);
++err_dpseci_setup:
++	free_percpu(priv->ppriv);
++err_alloc_ppriv:
++	fsl_mc_portal_free(priv->mc_io);
++err_dma_mask:
++	kmem_cache_destroy(qi_cache);
++err_qicache:
++	dev_set_drvdata(dev, NULL);
++
++	return err;
++}
++
++static int __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev)
++{
++	struct device *dev;
++	struct dpaa2_caam_priv *priv;
++	int i;
++
++	dev = &ls_dev->dev;
++	priv = dev_get_drvdata(dev);
++
++	for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
++		struct caam_aead_alg *t_alg = driver_aeads + i;
++
++		if (t_alg->registered)
++			crypto_unregister_aead(&t_alg->aead);
++	}
++
++	if (alg_list.next) {
++		struct caam_crypto_alg *t_alg, *n;
++
++		list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
++			crypto_unregister_alg(&t_alg->crypto_alg);
++			list_del(&t_alg->entry);
++			kfree(t_alg);
++		}
++	}
++
++	if (hash_list.next) {
++		struct caam_hash_alg *t_hash_alg, *p;
++
++		list_for_each_entry_safe(t_hash_alg, p, &hash_list, entry) {
++			crypto_unregister_ahash(&t_hash_alg->ahash_alg);
++			list_del(&t_hash_alg->entry);
++			kfree(t_hash_alg);
++		}
++	}
++
++	dpaa2_dpseci_disable(priv);
++	dpaa2_dpseci_dpio_free(priv);
++	dpaa2_dpseci_free(priv);
++	free_percpu(priv->ppriv);
++	fsl_mc_portal_free(priv->mc_io);
++	dev_set_drvdata(dev, NULL);
++	kmem_cache_destroy(qi_cache);
++
++	return 0;
++}
++
++int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req)
++{
++	struct dpaa2_fd fd;
++	struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
++	int err = 0, i, id;
++
++	if (IS_ERR(req))
++		return PTR_ERR(req);
++
++	if (priv->cscn_mem) {
++		dma_sync_single_for_cpu(priv->dev, priv->cscn_dma,
++					DPAA2_CSCN_SIZE,
++					DMA_FROM_DEVICE);
++		if (unlikely(dpaa2_cscn_state_congested(priv->cscn_mem_aligned))) {
++			dev_dbg_ratelimited(dev, "Dropping request\n");
++			return -EBUSY;
++		}
++	}
++
++	dpaa2_fl_set_flc(&req->fd_flt[1], req->flc_dma);
++
++	req->fd_flt_dma = dma_map_single(dev, req->fd_flt, sizeof(req->fd_flt),
++					 DMA_BIDIRECTIONAL);
++	if (dma_mapping_error(dev, req->fd_flt_dma)) {
++		dev_err(dev, "DMA mapping error for QI enqueue request\n");
++		goto err_out;
++	}
++
++	memset(&fd, 0, sizeof(fd));
++	dpaa2_fd_set_format(&fd, dpaa2_fd_list);
++	dpaa2_fd_set_addr(&fd, req->fd_flt_dma);
++	dpaa2_fd_set_len(&fd, dpaa2_fl_get_len(&req->fd_flt[1]));
++	dpaa2_fd_set_flc(&fd, req->flc_dma);
++
++	/*
++	 * There is no guarantee that preemption is disabled here,
++	 * thus take action.
++	 */
++	preempt_disable();
++	id = smp_processor_id() % priv->dpseci_attr.num_tx_queues;
++	for (i = 0; i < (priv->dpseci_attr.num_tx_queues << 1); i++) {
++		err = dpaa2_io_service_enqueue_fq(NULL,
++						  priv->tx_queue_attr[id].fqid,
++						  &fd);
++		if (err != -EBUSY)
++			break;
++	}
++	preempt_enable();
++
++	if (unlikely(err < 0)) {
++		dev_err(dev, "Error enqueuing frame: %d\n", err);
++		goto err_out;
++	}
++
++	return -EINPROGRESS;
++
++err_out:
++	dma_unmap_single(dev, req->fd_flt_dma, sizeof(req->fd_flt),
++			 DMA_BIDIRECTIONAL);
++	return -EIO;
++}
++EXPORT_SYMBOL(dpaa2_caam_enqueue);
++
++const struct fsl_mc_device_id dpaa2_caam_match_id_table[] = {
++	{
++		.vendor = FSL_MC_VENDOR_FREESCALE,
++		.obj_type = "dpseci",
++	},
++	{ .vendor = 0x0 }
++};
++
++static struct fsl_mc_driver dpaa2_caam_driver = {
++	.driver = {
++		.name		= KBUILD_MODNAME,
++		.owner		= THIS_MODULE,
++	},
++	.probe		= dpaa2_caam_probe,
++	.remove		= dpaa2_caam_remove,
++	.match_id_table = dpaa2_caam_match_id_table
++};
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_AUTHOR("Freescale Semiconductor, Inc");
++MODULE_DESCRIPTION("Freescale DPAA2 CAAM Driver");
++
++module_fsl_mc_driver(dpaa2_caam_driver);
+--- /dev/null
++++ b/drivers/crypto/caam/caamalg_qi2.h
+@@ -0,0 +1,283 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the names of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef _CAAMALG_QI2_H_
++#define _CAAMALG_QI2_H_
++
++#include "../../../drivers/staging/fsl-mc/include/dpaa2-io.h"
++#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
++#include <linux/threads.h>
++#include "dpseci.h"
++#include "desc_constr.h"
++
++#define DPAA2_CAAM_STORE_SIZE	16
++/* NAPI weight *must* be a multiple of the store size. */
++#define DPAA2_CAAM_NAPI_WEIGHT	64
++
++/* The congestion entrance threshold was chosen so that on LS2088
++ * we support the maximum throughput for the available memory
++ */
++#define DPAA2_SEC_CONG_ENTRY_THRESH	(128 * 1024 * 1024)
++#define DPAA2_SEC_CONG_EXIT_THRESH	(DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
++
++/**
++ * dpaa2_caam_priv - driver private data
++ * @dpseci_id: DPSECI object unique ID
++ * @major_ver: DPSECI major version
++ * @minor_ver: DPSECI minor version
++ * @dpseci_attr: DPSECI attributes
++ * @sec_attr: SEC engine attributes
++ * @rx_queue_attr: array of Rx queue attributes
++ * @tx_queue_attr: array of Tx queue attributes
++ * @cscn_mem: pointer to memory region containing the
++ *	dpaa2_cscn struct; it's size is larger than
++ *	sizeof(struct dpaa2_cscn) to accommodate alignment
++ * @cscn_mem_aligned: pointer to struct dpaa2_cscn; it is computed
++ *	as PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
++ * @cscn_dma: dma address used by the QMAN to write CSCN messages
++ * @dev: device associated with the DPSECI object
++ * @mc_io: pointer to MC portal's I/O object
++ * @domain: IOMMU domain
++ * @ppriv: per CPU pointers to privata data
++ */
++struct dpaa2_caam_priv {
++	int dpsec_id;
++
++	u16 major_ver;
++	u16 minor_ver;
++
++	struct dpseci_attr dpseci_attr;
++	struct dpseci_sec_attr sec_attr;
++	struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_PRIO_NUM];
++	struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_PRIO_NUM];
++	int num_pairs;
++
++	/* congestion */
++	void *cscn_mem;
++	void *cscn_mem_aligned;
++	dma_addr_t cscn_dma;
++
++	struct device *dev;
++	struct fsl_mc_io *mc_io;
++	struct iommu_domain *domain;
++
++	struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
++};
++
++/**
++ * dpaa2_caam_priv_per_cpu - per CPU private data
++ * @napi: napi structure
++ * @net_dev: netdev used by napi
++ * @req_fqid: (virtual) request (Tx / enqueue) FQID
++ * @rsp_fqid: (virtual) response (Rx / dequeue) FQID
++ * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
++ * @nctx: notification context of response FQ
++ * @store: where dequeued frames are stored
++ * @priv: backpointer to dpaa2_caam_priv
++ */
++struct dpaa2_caam_priv_per_cpu {
++	struct napi_struct napi;
++	struct net_device net_dev;
++	int req_fqid;
++	int rsp_fqid;
++	int prio;
++	struct dpaa2_io_notification_ctx nctx;
++	struct dpaa2_io_store *store;
++	struct dpaa2_caam_priv *priv;
++};
++
++/*
++ * The CAAM QI hardware constructs a job descriptor which points
++ * to shared descriptor (as pointed by context_a of FQ to CAAM).
++ * When the job descriptor is executed by deco, the whole job
++ * descriptor together with shared descriptor gets loaded in
++ * deco buffer which is 64 words long (each 32-bit).
++ *
++ * The job descriptor constructed by QI hardware has layout:
++ *
++ *	HEADER		(1 word)
++ *	Shdesc ptr	(1 or 2 words)
++ *	SEQ_OUT_PTR	(1 word)
++ *	Out ptr		(1 or 2 words)
++ *	Out length	(1 word)
++ *	SEQ_IN_PTR	(1 word)
++ *	In ptr		(1 or 2 words)
++ *	In length	(1 word)
++ *
++ * The shdesc ptr is used to fetch shared descriptor contents
++ * into deco buffer.
++ *
++ * Apart from shdesc contents, the total number of words that
++ * get loaded in deco buffer are '8' or '11'. The remaining words
++ * in deco buffer can be used for storing shared descriptor.
++ */
++#define MAX_SDLEN	((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
++
++/* Length of a single buffer in the QI driver memory cache */
++#define CAAM_QI_MEMCACHE_SIZE	512
++
++/*
++ * aead_edesc - s/w-extended aead descriptor
++ * @src_nents: number of segments in input scatterlist
++ * @dst_nents: number of segments in output scatterlist
++ * @iv_dma: dma address of iv for checking continuity and link table
++ * @qm_sg_bytes: length of dma mapped h/w link table
++ * @qm_sg_dma: bus physical mapped address of h/w link table
++ * @assoclen: associated data length, in CAAM endianness
++ * @assoclen_dma: bus physical mapped address of req->assoclen
++ * @sgt: the h/w link table
++ */
++struct aead_edesc {
++	int src_nents;
++	int dst_nents;
++	dma_addr_t iv_dma;
++	int qm_sg_bytes;
++	dma_addr_t qm_sg_dma;
++	unsigned int assoclen;
++	dma_addr_t assoclen_dma;
++#define CAAM_QI_MAX_AEAD_SG						\
++	((CAAM_QI_MEMCACHE_SIZE - offsetof(struct aead_edesc, sgt)) /	\
++	 sizeof(struct dpaa2_sg_entry))
++	struct dpaa2_sg_entry sgt[0];
++};
++
++/*
++ * tls_edesc - s/w-extended tls descriptor
++ * @src_nents: number of segments in input scatterlist
++ * @dst_nents: number of segments in output scatterlist
++ * @iv_dma: dma address of iv for checking continuity and link table
++ * @qm_sg_bytes: length of dma mapped h/w link table
++ * @qm_sg_dma: bus physical mapped address of h/w link table
++ * @tmp: array of scatterlists used by 'scatterwalk_ffwd'
++ * @dst: pointer to output scatterlist, usefull for unmapping
++ * @sgt: the h/w link table
++ */
++struct tls_edesc {
++	int src_nents;
++	int dst_nents;
++	dma_addr_t iv_dma;
++	int qm_sg_bytes;
++	dma_addr_t qm_sg_dma;
++	struct scatterlist tmp[2];
++	struct scatterlist *dst;
++	struct dpaa2_sg_entry sgt[0];
++};
++
++/*
++ * ablkcipher_edesc - s/w-extended ablkcipher descriptor
++ * @src_nents: number of segments in input scatterlist
++ * @dst_nents: number of segments in output scatterlist
++ * @iv_dma: dma address of iv for checking continuity and link table
++ * @qm_sg_bytes: length of dma mapped qm_sg space
++ * @qm_sg_dma: I/O virtual address of h/w link table
++ * @sgt: the h/w link table
++ */
++struct ablkcipher_edesc {
++	int src_nents;
++	int dst_nents;
++	dma_addr_t iv_dma;
++	int qm_sg_bytes;
++	dma_addr_t qm_sg_dma;
++#define CAAM_QI_MAX_ABLKCIPHER_SG					    \
++	((CAAM_QI_MEMCACHE_SIZE - offsetof(struct ablkcipher_edesc, sgt)) / \
++	 sizeof(struct dpaa2_sg_entry))
++	struct dpaa2_sg_entry sgt[0];
++};
++
++/*
++ * ahash_edesc - s/w-extended ahash descriptor
++ * @dst_dma: I/O virtual address of req->result
++ * @qm_sg_dma: I/O virtual address of h/w link table
++ * @src_nents: number of segments in input scatterlist
++ * @qm_sg_bytes: length of dma mapped qm_sg space
++ * @sgt: pointer to h/w link table
++ */
++struct ahash_edesc {
++	dma_addr_t dst_dma;
++	dma_addr_t qm_sg_dma;
++	int src_nents;
++	int qm_sg_bytes;
++	struct dpaa2_sg_entry sgt[0];
++};
++
++/**
++ * caam_flc - Flow Context (FLC)
++ * @flc: Flow Context options
++ * @sh_desc: Shared Descriptor
++ */
++struct caam_flc {
++	u32 flc[16];
++	u32 sh_desc[MAX_SDLEN];
++} ____cacheline_aligned;
++
++enum optype {
++	ENCRYPT = 0,
++	DECRYPT,
++	GIVENCRYPT,
++	NUM_OP
++};
++
++/**
++ * caam_request - the request structure the driver application should fill while
++ *                submitting a job to driver.
++ * @fd_flt: Frame list table defining input and output
++ *          fd_flt[0] - FLE pointing to output buffer
++ *          fd_flt[1] - FLE pointing to input buffer
++ * @fd_flt_dma: DMA address for the frame list table
++ * @flc: Flow Context
++ * @flc_dma: I/O virtual address of Flow Context
++ * @op_type: operation type
++ * @cbk: Callback function to invoke when job is completed
++ * @ctx: arbit context attached with request by the application
++ * @edesc: extended descriptor; points to one of {ablkcipher,aead}_edesc
++ */
++struct caam_request {
++	struct dpaa2_fl_entry fd_flt[2];
++	dma_addr_t fd_flt_dma;
++	struct caam_flc *flc;
++	dma_addr_t flc_dma;
++	enum optype op_type;
++	void (*cbk)(void *ctx, u32 err);
++	void *ctx;
++	void *edesc;
++};
++
++/**
++ * dpaa2_caam_enqueue() - enqueue a crypto request
++ * @dev: device associated with the DPSECI object
++ * @req: pointer to caam_request
++ */
++int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
++
++#endif	/* _CAAMALG_QI2_H_ */
+--- a/drivers/crypto/caam/caamhash.c
++++ b/drivers/crypto/caam/caamhash.c
+@@ -62,6 +62,7 @@
+ #include "error.h"
+ #include "sg_sw_sec4.h"
+ #include "key_gen.h"
++#include "caamhash_desc.h"
+ 
+ #define CAAM_CRA_PRIORITY		3000
+ 
+@@ -71,14 +72,6 @@
+ #define CAAM_MAX_HASH_BLOCK_SIZE	SHA512_BLOCK_SIZE
+ #define CAAM_MAX_HASH_DIGEST_SIZE	SHA512_DIGEST_SIZE
+ 
+-/* length of descriptors text */
+-#define DESC_AHASH_BASE			(4 * CAAM_CMD_SZ)
+-#define DESC_AHASH_UPDATE_LEN		(6 * CAAM_CMD_SZ)
+-#define DESC_AHASH_UPDATE_FIRST_LEN	(DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
+-#define DESC_AHASH_FINAL_LEN		(DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
+-#define DESC_AHASH_FINUP_LEN		(DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
+-#define DESC_AHASH_DIGEST_LEN		(DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
+-
+ #define DESC_HASH_MAX_USED_BYTES	(DESC_AHASH_FINAL_LEN + \
+ 					 CAAM_MAX_HASH_KEY_SIZE)
+ #define DESC_HASH_MAX_USED_LEN		(DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ)
+@@ -103,20 +96,15 @@ struct caam_hash_ctx {
+ 	u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+ 	u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+ 	u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+-	u32 sh_desc_finup[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
+ 	dma_addr_t sh_desc_update_dma ____cacheline_aligned;
+ 	dma_addr_t sh_desc_update_first_dma;
+ 	dma_addr_t sh_desc_fin_dma;
+ 	dma_addr_t sh_desc_digest_dma;
+-	dma_addr_t sh_desc_finup_dma;
++	enum dma_data_direction dir;
+ 	struct device *jrdev;
+-	u32 alg_type;
+-	u32 alg_op;
+ 	u8 key[CAAM_MAX_HASH_KEY_SIZE];
+-	dma_addr_t key_dma;
+ 	int ctx_len;
+-	unsigned int split_key_len;
+-	unsigned int split_key_pad_len;
++	struct alginfo adata;
+ };
+ 
+ /* ahash state */
+@@ -143,6 +131,31 @@ struct caam_export_state {
+ 	int (*finup)(struct ahash_request *req);
+ };
+ 
++static inline void switch_buf(struct caam_hash_state *state)
++{
++	state->current_buf ^= 1;
++}
++
++static inline u8 *current_buf(struct caam_hash_state *state)
++{
++	return state->current_buf ? state->buf_1 : state->buf_0;
++}
++
++static inline u8 *alt_buf(struct caam_hash_state *state)
++{
++	return state->current_buf ? state->buf_0 : state->buf_1;
++}
++
++static inline int *current_buflen(struct caam_hash_state *state)
++{
++	return state->current_buf ? &state->buflen_1 : &state->buflen_0;
++}
++
++static inline int *alt_buflen(struct caam_hash_state *state)
++{
++	return state->current_buf ? &state->buflen_0 : &state->buflen_1;
++}
++
+ /* Common job descriptor seq in/out ptr routines */
+ 
+ /* Map state->caam_ctx, and append seq_out_ptr command that points to it */
+@@ -175,40 +188,31 @@ static inline dma_addr_t map_seq_out_ptr
+ 	return dst_dma;
+ }
+ 
+-/* Map current buffer in state and put it in link table */
+-static inline dma_addr_t buf_map_to_sec4_sg(struct device *jrdev,
+-					    struct sec4_sg_entry *sec4_sg,
+-					    u8 *buf, int buflen)
++/* Map current buffer in state (if length > 0) and put it in link table */
++static inline int buf_map_to_sec4_sg(struct device *jrdev,
++				     struct sec4_sg_entry *sec4_sg,
++				     struct caam_hash_state *state)
+ {
+-	dma_addr_t buf_dma;
++	int buflen = *current_buflen(state);
+ 
+-	buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
+-	dma_to_sec4_sg_one(sec4_sg, buf_dma, buflen, 0);
++	if (!buflen)
++		return 0;
+ 
+-	return buf_dma;
+-}
++	state->buf_dma = dma_map_single(jrdev, current_buf(state), buflen,
++					DMA_TO_DEVICE);
++	if (dma_mapping_error(jrdev, state->buf_dma)) {
++		dev_err(jrdev, "unable to map buf\n");
++		state->buf_dma = 0;
++		return -ENOMEM;
++	}
+ 
+-/*
+- * Only put buffer in link table if it contains data, which is possible,
+- * since a buffer has previously been used, and needs to be unmapped,
+- */
+-static inline dma_addr_t
+-try_buf_map_to_sec4_sg(struct device *jrdev, struct sec4_sg_entry *sec4_sg,
+-		       u8 *buf, dma_addr_t buf_dma, int buflen,
+-		       int last_buflen)
+-{
+-	if (buf_dma && !dma_mapping_error(jrdev, buf_dma))
+-		dma_unmap_single(jrdev, buf_dma, last_buflen, DMA_TO_DEVICE);
+-	if (buflen)
+-		buf_dma = buf_map_to_sec4_sg(jrdev, sec4_sg, buf, buflen);
+-	else
+-		buf_dma = 0;
++	dma_to_sec4_sg_one(sec4_sg, state->buf_dma, buflen, 0);
+ 
+-	return buf_dma;
++	return 0;
+ }
+ 
+ /* Map state->caam_ctx, and add it to link table */
+-static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
++static inline int ctx_map_to_sec4_sg(struct device *jrdev,
+ 				     struct caam_hash_state *state, int ctx_len,
+ 				     struct sec4_sg_entry *sec4_sg, u32 flag)
+ {
+@@ -224,124 +228,22 @@ static inline int ctx_map_to_sec4_sg(u32
+ 	return 0;
+ }
+ 
+-/* Common shared descriptor commands */
+-static inline void append_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
+-{
+-	append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
+-			  ctx->split_key_len, CLASS_2 |
+-			  KEY_DEST_MDHA_SPLIT | KEY_ENC);
+-}
+-
+-/* Append key if it has been set */
+-static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
+-{
+-	u32 *key_jump_cmd;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	if (ctx->split_key_len) {
+-		/* Skip if already shared */
+-		key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+-					   JUMP_COND_SHRD);
+-
+-		append_key_ahash(desc, ctx);
+-
+-		set_jump_tgt_here(desc, key_jump_cmd);
+-	}
+-
+-	/* Propagate errors from shared to job descriptor */
+-	append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+-}
+-
+-/*
+- * For ahash read data from seqin following state->caam_ctx,
+- * and write resulting class2 context to seqout, which may be state->caam_ctx
+- * or req->result
+- */
+-static inline void ahash_append_load_str(u32 *desc, int digestsize)
+-{
+-	/* Calculate remaining bytes to read */
+-	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+-
+-	/* Read remaining bytes */
+-	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 |
+-			     FIFOLD_TYPE_MSG | KEY_VLF);
+-
+-	/* Store class2 context bytes */
+-	append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
+-			 LDST_SRCDST_BYTE_CONTEXT);
+-}
+-
+-/*
+- * For ahash update, final and finup, import context, read and write to seqout
+- */
+-static inline void ahash_ctx_data_to_out(u32 *desc, u32 op, u32 state,
+-					 int digestsize,
+-					 struct caam_hash_ctx *ctx)
+-{
+-	init_sh_desc_key_ahash(desc, ctx);
+-
+-	/* Import context from software */
+-	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+-		   LDST_CLASS_2_CCB | ctx->ctx_len);
+-
+-	/* Class 2 operation */
+-	append_operation(desc, op | state | OP_ALG_ENCRYPT);
+-
+-	/*
+-	 * Load from buf and/or src and write to req->result or state->context
+-	 */
+-	ahash_append_load_str(desc, digestsize);
+-}
+-
+-/* For ahash firsts and digest, read and write to seqout */
+-static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state,
+-				     int digestsize, struct caam_hash_ctx *ctx)
+-{
+-	init_sh_desc_key_ahash(desc, ctx);
+-
+-	/* Class 2 operation */
+-	append_operation(desc, op | state | OP_ALG_ENCRYPT);
+-
+-	/*
+-	 * Load from buf and/or src and write to req->result or state->context
+-	 */
+-	ahash_append_load_str(desc, digestsize);
+-}
+-
+ static int ahash_set_sh_desc(struct crypto_ahash *ahash)
+ {
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ 	int digestsize = crypto_ahash_digestsize(ahash);
+ 	struct device *jrdev = ctx->jrdev;
+-	u32 have_key = 0;
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
+ 	u32 *desc;
+ 
+-	if (ctx->split_key_len)
+-		have_key = OP_ALG_AAI_HMAC_PRECOMP;
++	ctx->adata.key_virt = ctx->key;
+ 
+ 	/* ahash_update shared descriptor */
+ 	desc = ctx->sh_desc_update;
+-
+-	init_sh_desc(desc, HDR_SHARE_SERIAL);
+-
+-	/* Import context from software */
+-	append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+-		   LDST_CLASS_2_CCB | ctx->ctx_len);
+-
+-	/* Class 2 operation */
+-	append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE |
+-			 OP_ALG_ENCRYPT);
+-
+-	/* Load data and write to result or context */
+-	ahash_append_load_str(desc, ctx->ctx_len);
+-
+-	ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
+-						 DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
++	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_UPDATE, ctx->ctx_len,
++			  ctx->ctx_len, true, ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_update_dma,
++				   desc_bytes(desc), ctx->dir);
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR,
+ 		       "ahash update shdesc@"__stringify(__LINE__)": ",
+@@ -350,17 +252,10 @@ static int ahash_set_sh_desc(struct cryp
+ 
+ 	/* ahash_update_first shared descriptor */
+ 	desc = ctx->sh_desc_update_first;
+-
+-	ahash_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT,
+-			  ctx->ctx_len, ctx);
+-
+-	ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc,
+-						       desc_bytes(desc),
+-						       DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
++	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len,
++			  ctx->ctx_len, false, ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
++				   desc_bytes(desc), ctx->dir);
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR,
+ 		       "ahash update first shdesc@"__stringify(__LINE__)": ",
+@@ -369,53 +264,22 @@ static int ahash_set_sh_desc(struct cryp
+ 
+ 	/* ahash_final shared descriptor */
+ 	desc = ctx->sh_desc_fin;
+-
+-	ahash_ctx_data_to_out(desc, have_key | ctx->alg_type,
+-			      OP_ALG_AS_FINALIZE, digestsize, ctx);
+-
+-	ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
+-					      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
++	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, digestsize,
++			  ctx->ctx_len, true, ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
++				   desc_bytes(desc), ctx->dir);
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ 		       desc_bytes(desc), 1);
+ #endif
+ 
+-	/* ahash_finup shared descriptor */
+-	desc = ctx->sh_desc_finup;
+-
+-	ahash_ctx_data_to_out(desc, have_key | ctx->alg_type,
+-			      OP_ALG_AS_FINALIZE, digestsize, ctx);
+-
+-	ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
+-						DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+-		       desc_bytes(desc), 1);
+-#endif
+-
+ 	/* ahash_digest shared descriptor */
+ 	desc = ctx->sh_desc_digest;
+-
+-	ahash_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL,
+-			  digestsize, ctx);
+-
+-	ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc,
+-						 desc_bytes(desc),
+-						 DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) {
+-		dev_err(jrdev, "unable to map shared descriptor\n");
+-		return -ENOMEM;
+-	}
++	cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, digestsize,
++			  ctx->ctx_len, false, ctrlpriv->era);
++	dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
++				   desc_bytes(desc), ctx->dir);
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR,
+ 		       "ahash digest shdesc@"__stringify(__LINE__)": ",
+@@ -426,14 +290,6 @@ static int ahash_set_sh_desc(struct cryp
+ 	return 0;
+ }
+ 
+-static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
+-			      u32 keylen)
+-{
+-	return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
+-			       ctx->split_key_pad_len, key_in, keylen,
+-			       ctx->alg_op);
+-}
+-
+ /* Digest hash size if it is too large */
+ static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
+ 			   u32 *keylen, u8 *key_out, u32 digestsize)
+@@ -469,7 +325,7 @@ static int hash_digest_key(struct caam_h
+ 	}
+ 
+ 	/* Job descriptor to perform unkeyed hash on key_in */
+-	append_operation(desc, ctx->alg_type | OP_ALG_ENCRYPT |
++	append_operation(desc, ctx->adata.algtype | OP_ALG_ENCRYPT |
+ 			 OP_ALG_AS_INITFINAL);
+ 	append_seq_in_ptr(desc, src_dma, *keylen, 0);
+ 	append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 |
+@@ -513,12 +369,10 @@ static int hash_digest_key(struct caam_h
+ static int ahash_setkey(struct crypto_ahash *ahash,
+ 			const u8 *key, unsigned int keylen)
+ {
+-	/* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
+-	static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+-	struct device *jrdev = ctx->jrdev;
+ 	int blocksize = crypto_tfm_alg_blocksize(&ahash->base);
+ 	int digestsize = crypto_ahash_digestsize(ahash);
++	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
+ 	int ret;
+ 	u8 *hashed_key = NULL;
+ 
+@@ -539,43 +393,29 @@ static int ahash_setkey(struct crypto_ah
+ 		key = hashed_key;
+ 	}
+ 
+-	/* Pick class 2 key length from algorithm submask */
+-	ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
+-				      OP_ALG_ALGSEL_SHIFT] * 2;
+-	ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
+-
+-#ifdef DEBUG
+-	printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
+-	       ctx->split_key_len, ctx->split_key_pad_len);
+-	print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+-#endif
++	/*
++	 * If DKP is supported, use it in the shared descriptor to generate
++	 * the split key.
++	 */
++	if (ctrlpriv->era >= 6) {
++		ctx->adata.key_inline = true;
++		ctx->adata.keylen = keylen;
++		ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
++						      OP_ALG_ALGSEL_MASK);
+ 
+-	ret = gen_split_hash_key(ctx, key, keylen);
+-	if (ret)
+-		goto bad_free_key;
++		if (ctx->adata.keylen_pad > CAAM_MAX_HASH_KEY_SIZE)
++			goto bad_free_key;
+ 
+-	ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len,
+-				      DMA_TO_DEVICE);
+-	if (dma_mapping_error(jrdev, ctx->key_dma)) {
+-		dev_err(jrdev, "unable to map key i/o memory\n");
+-		ret = -ENOMEM;
+-		goto error_free_key;
++		memcpy(ctx->key, key, keylen);
++	} else {
++		ret = gen_split_key(ctx->jrdev, ctx->key, &ctx->adata, key,
++				    keylen, CAAM_MAX_HASH_KEY_SIZE);
++		if (ret)
++			goto bad_free_key;
+ 	}
+-#ifdef DEBUG
+-	print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
+-		       DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
+-		       ctx->split_key_pad_len, 1);
+-#endif
+ 
+-	ret = ahash_set_sh_desc(ahash);
+-	if (ret) {
+-		dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len,
+-				 DMA_TO_DEVICE);
+-	}
+- error_free_key:
+ 	kfree(hashed_key);
+-	return ret;
++	return ahash_set_sh_desc(ahash);
+  bad_free_key:
+ 	kfree(hashed_key);
+ 	crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+@@ -604,6 +444,8 @@ static inline void ahash_unmap(struct de
+ 			struct ahash_edesc *edesc,
+ 			struct ahash_request *req, int dst_len)
+ {
++	struct caam_hash_state *state = ahash_request_ctx(req);
++
+ 	if (edesc->src_nents)
+ 		dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE);
+ 	if (edesc->dst_dma)
+@@ -612,6 +454,12 @@ static inline void ahash_unmap(struct de
+ 	if (edesc->sec4_sg_bytes)
+ 		dma_unmap_single(dev, edesc->sec4_sg_dma,
+ 				 edesc->sec4_sg_bytes, DMA_TO_DEVICE);
++
++	if (state->buf_dma) {
++		dma_unmap_single(dev, state->buf_dma, *current_buflen(state),
++				 DMA_TO_DEVICE);
++		state->buf_dma = 0;
++	}
+ }
+ 
+ static inline void ahash_unmap_ctx(struct device *dev,
+@@ -643,8 +491,7 @@ static void ahash_done(struct device *jr
+ 	dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+ #endif
+ 
+-	edesc = (struct ahash_edesc *)((char *)desc -
+-		 offsetof(struct ahash_edesc, hw_desc));
++	edesc = container_of(desc, struct ahash_edesc, hw_desc[0]);
+ 	if (err)
+ 		caam_jr_strstatus(jrdev, err);
+ 
+@@ -671,19 +518,19 @@ static void ahash_done_bi(struct device
+ 	struct ahash_edesc *edesc;
+ 	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+-#ifdef DEBUG
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
++#ifdef DEBUG
+ 	int digestsize = crypto_ahash_digestsize(ahash);
+ 
+ 	dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+ #endif
+ 
+-	edesc = (struct ahash_edesc *)((char *)desc -
+-		 offsetof(struct ahash_edesc, hw_desc));
++	edesc = container_of(desc, struct ahash_edesc, hw_desc[0]);
+ 	if (err)
+ 		caam_jr_strstatus(jrdev, err);
+ 
+ 	ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
++	switch_buf(state);
+ 	kfree(edesc);
+ 
+ #ifdef DEBUG
+@@ -713,8 +560,7 @@ static void ahash_done_ctx_src(struct de
+ 	dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+ #endif
+ 
+-	edesc = (struct ahash_edesc *)((char *)desc -
+-		 offsetof(struct ahash_edesc, hw_desc));
++	edesc = container_of(desc, struct ahash_edesc, hw_desc[0]);
+ 	if (err)
+ 		caam_jr_strstatus(jrdev, err);
+ 
+@@ -741,19 +587,19 @@ static void ahash_done_ctx_dst(struct de
+ 	struct ahash_edesc *edesc;
+ 	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+-#ifdef DEBUG
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
++#ifdef DEBUG
+ 	int digestsize = crypto_ahash_digestsize(ahash);
+ 
+ 	dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+ #endif
+ 
+-	edesc = (struct ahash_edesc *)((char *)desc -
+-		 offsetof(struct ahash_edesc, hw_desc));
++	edesc = container_of(desc, struct ahash_edesc, hw_desc[0]);
+ 	if (err)
+ 		caam_jr_strstatus(jrdev, err);
+ 
+ 	ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE);
++	switch_buf(state);
+ 	kfree(edesc);
+ 
+ #ifdef DEBUG
+@@ -835,13 +681,12 @@ static int ahash_update_ctx(struct ahash
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+-	u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
+-	int *buflen = state->current_buf ? &state->buflen_1 : &state->buflen_0;
+-	u8 *next_buf = state->current_buf ? state->buf_0 : state->buf_1;
+-	int *next_buflen = state->current_buf ? &state->buflen_0 :
+-			   &state->buflen_1, last_buflen;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	u8 *buf = current_buf(state);
++	int *buflen = current_buflen(state);
++	u8 *next_buf = alt_buf(state);
++	int *next_buflen = alt_buflen(state), last_buflen;
+ 	int in_len = *buflen + req->nbytes, to_hash;
+ 	u32 *desc;
+ 	int src_nents, mapped_nents, sec4_sg_bytes, sec4_sg_src_index;
+@@ -890,15 +735,14 @@ static int ahash_update_ctx(struct ahash
+ 		edesc->src_nents = src_nents;
+ 		edesc->sec4_sg_bytes = sec4_sg_bytes;
+ 
+-		ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
++		ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
+ 					 edesc->sec4_sg, DMA_BIDIRECTIONAL);
+ 		if (ret)
+ 			goto unmap_ctx;
+ 
+-		state->buf_dma = try_buf_map_to_sec4_sg(jrdev,
+-							edesc->sec4_sg + 1,
+-							buf, state->buf_dma,
+-							*buflen, last_buflen);
++		ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1, state);
++		if (ret)
++			goto unmap_ctx;
+ 
+ 		if (mapped_nents) {
+ 			sg_to_sec4_sg_last(req->src, mapped_nents,
+@@ -909,12 +753,10 @@ static int ahash_update_ctx(struct ahash
+ 							 to_hash - *buflen,
+ 							 *next_buflen, 0);
+ 		} else {
+-			(edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
+-				cpu_to_caam32(SEC4_SG_LEN_FIN);
++			sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index -
++					    1);
+ 		}
+ 
+-		state->current_buf = !state->current_buf;
+-
+ 		desc = edesc->hw_desc;
+ 
+ 		edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+@@ -969,12 +811,9 @@ static int ahash_final_ctx(struct ahash_
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+-	u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
+-	int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
+-	int last_buflen = state->current_buf ? state->buflen_0 :
+-			  state->buflen_1;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int buflen = *current_buflen(state);
+ 	u32 *desc;
+ 	int sec4_sg_bytes, sec4_sg_src_index;
+ 	int digestsize = crypto_ahash_digestsize(ahash);
+@@ -994,18 +833,17 @@ static int ahash_final_ctx(struct ahash_
+ 	desc = edesc->hw_desc;
+ 
+ 	edesc->sec4_sg_bytes = sec4_sg_bytes;
+-	edesc->src_nents = 0;
+ 
+-	ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
++	ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
+ 				 edesc->sec4_sg, DMA_TO_DEVICE);
+ 	if (ret)
+ 		goto unmap_ctx;
+ 
+-	state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
+-						buf, state->buf_dma, buflen,
+-						last_buflen);
+-	(edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
+-		cpu_to_caam32(SEC4_SG_LEN_FIN);
++	ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1, state);
++	if (ret)
++		goto unmap_ctx;
++
++	sg_to_sec4_set_last(edesc->sec4_sg + sec4_sg_src_index - 1);
+ 
+ 	edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+ 					    sec4_sg_bytes, DMA_TO_DEVICE);
+@@ -1048,12 +886,9 @@ static int ahash_finup_ctx(struct ahash_
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+-	u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
+-	int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
+-	int last_buflen = state->current_buf ? state->buflen_0 :
+-			  state->buflen_1;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int buflen = *current_buflen(state);
+ 	u32 *desc;
+ 	int sec4_sg_src_index;
+ 	int src_nents, mapped_nents;
+@@ -1082,7 +917,7 @@ static int ahash_finup_ctx(struct ahash_
+ 
+ 	/* allocate space for base edesc and hw desc commands, link tables */
+ 	edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents,
+-				  ctx->sh_desc_finup, ctx->sh_desc_finup_dma,
++				  ctx->sh_desc_fin, ctx->sh_desc_fin_dma,
+ 				  flags);
+ 	if (!edesc) {
+ 		dma_unmap_sg(jrdev, req->src, src_nents, DMA_TO_DEVICE);
+@@ -1093,14 +928,14 @@ static int ahash_finup_ctx(struct ahash_
+ 
+ 	edesc->src_nents = src_nents;
+ 
+-	ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
++	ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
+ 				 edesc->sec4_sg, DMA_TO_DEVICE);
+ 	if (ret)
+ 		goto unmap_ctx;
+ 
+-	state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
+-						buf, state->buf_dma, buflen,
+-						last_buflen);
++	ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1, state);
++	if (ret)
++		goto unmap_ctx;
+ 
+ 	ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents,
+ 				  sec4_sg_src_index, ctx->ctx_len + buflen,
+@@ -1136,15 +971,18 @@ static int ahash_digest(struct ahash_req
+ {
+ 	struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++	struct caam_hash_state *state = ahash_request_ctx(req);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
+ 	u32 *desc;
+ 	int digestsize = crypto_ahash_digestsize(ahash);
+ 	int src_nents, mapped_nents;
+ 	struct ahash_edesc *edesc;
+ 	int ret;
+ 
++	state->buf_dma = 0;
++
+ 	src_nents = sg_nents_for_len(req->src, req->nbytes);
+ 	if (src_nents < 0) {
+ 		dev_err(jrdev, "Invalid number of src SG.\n");
+@@ -1215,10 +1053,10 @@ static int ahash_final_no_ctx(struct aha
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+-	u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
+-	int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	u8 *buf = current_buf(state);
++	int buflen = *current_buflen(state);
+ 	u32 *desc;
+ 	int digestsize = crypto_ahash_digestsize(ahash);
+ 	struct ahash_edesc *edesc;
+@@ -1246,7 +1084,6 @@ static int ahash_final_no_ctx(struct aha
+ 		dev_err(jrdev, "unable to map dst\n");
+ 		goto unmap;
+ 	}
+-	edesc->src_nents = 0;
+ 
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
+@@ -1276,13 +1113,12 @@ static int ahash_update_no_ctx(struct ah
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+-	u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
+-	int *buflen = state->current_buf ? &state->buflen_1 : &state->buflen_0;
+-	u8 *next_buf = state->current_buf ? state->buf_0 : state->buf_1;
+-	int *next_buflen = state->current_buf ? &state->buflen_0 :
+-			   &state->buflen_1;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	u8 *buf = current_buf(state);
++	int *buflen = current_buflen(state);
++	u8 *next_buf = alt_buf(state);
++	int *next_buflen = alt_buflen(state);
+ 	int in_len = *buflen + req->nbytes, to_hash;
+ 	int sec4_sg_bytes, src_nents, mapped_nents;
+ 	struct ahash_edesc *edesc;
+@@ -1329,10 +1165,11 @@ static int ahash_update_no_ctx(struct ah
+ 
+ 		edesc->src_nents = src_nents;
+ 		edesc->sec4_sg_bytes = sec4_sg_bytes;
+-		edesc->dst_dma = 0;
+ 
+-		state->buf_dma = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg,
+-						    buf, *buflen);
++		ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, state);
++		if (ret)
++			goto unmap_ctx;
++
+ 		sg_to_sec4_sg_last(req->src, mapped_nents,
+ 				   edesc->sec4_sg + 1, 0);
+ 
+@@ -1342,8 +1179,6 @@ static int ahash_update_no_ctx(struct ah
+ 						 *next_buflen, 0);
+ 		}
+ 
+-		state->current_buf = !state->current_buf;
+-
+ 		desc = edesc->hw_desc;
+ 
+ 		edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+@@ -1403,12 +1238,9 @@ static int ahash_finup_no_ctx(struct aha
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+-	u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
+-	int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
+-	int last_buflen = state->current_buf ? state->buflen_0 :
+-			  state->buflen_1;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	int buflen = *current_buflen(state);
+ 	u32 *desc;
+ 	int sec4_sg_bytes, sec4_sg_src_index, src_nents, mapped_nents;
+ 	int digestsize = crypto_ahash_digestsize(ahash);
+@@ -1450,9 +1282,9 @@ static int ahash_finup_no_ctx(struct aha
+ 	edesc->src_nents = src_nents;
+ 	edesc->sec4_sg_bytes = sec4_sg_bytes;
+ 
+-	state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, buf,
+-						state->buf_dma, buflen,
+-						last_buflen);
++	ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, state);
++	if (ret)
++		goto unmap;
+ 
+ 	ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 1, buflen,
+ 				  req->nbytes);
+@@ -1496,11 +1328,10 @@ static int ahash_update_first(struct aha
+ 	struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ 	struct caam_hash_state *state = ahash_request_ctx(req);
+ 	struct device *jrdev = ctx->jrdev;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+-	u8 *next_buf = state->current_buf ? state->buf_1 : state->buf_0;
+-	int *next_buflen = state->current_buf ?
+-		&state->buflen_1 : &state->buflen_0;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
++	u8 *next_buf = alt_buf(state);
++	int *next_buflen = alt_buflen(state);
+ 	int to_hash;
+ 	u32 *desc;
+ 	int src_nents, mapped_nents;
+@@ -1545,7 +1376,6 @@ static int ahash_update_first(struct aha
+ 		}
+ 
+ 		edesc->src_nents = src_nents;
+-		edesc->dst_dma = 0;
+ 
+ 		ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 0, 0,
+ 					  to_hash);
+@@ -1582,6 +1412,7 @@ static int ahash_update_first(struct aha
+ 		state->final = ahash_final_no_ctx;
+ 		scatterwalk_map_and_copy(next_buf, req->src, 0,
+ 					 req->nbytes, 0);
++		switch_buf(state);
+ 	}
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
+@@ -1688,7 +1519,6 @@ struct caam_hash_template {
+ 	unsigned int blocksize;
+ 	struct ahash_alg template_ahash;
+ 	u32 alg_type;
+-	u32 alg_op;
+ };
+ 
+ /* ahash descriptors */
+@@ -1714,7 +1544,6 @@ static struct caam_hash_template driver_
+ 			},
+ 		},
+ 		.alg_type = OP_ALG_ALGSEL_SHA1,
+-		.alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ 	}, {
+ 		.name = "sha224",
+ 		.driver_name = "sha224-caam",
+@@ -1736,7 +1565,6 @@ static struct caam_hash_template driver_
+ 			},
+ 		},
+ 		.alg_type = OP_ALG_ALGSEL_SHA224,
+-		.alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ 	}, {
+ 		.name = "sha256",
+ 		.driver_name = "sha256-caam",
+@@ -1758,7 +1586,6 @@ static struct caam_hash_template driver_
+ 			},
+ 		},
+ 		.alg_type = OP_ALG_ALGSEL_SHA256,
+-		.alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ 	}, {
+ 		.name = "sha384",
+ 		.driver_name = "sha384-caam",
+@@ -1780,7 +1607,6 @@ static struct caam_hash_template driver_
+ 			},
+ 		},
+ 		.alg_type = OP_ALG_ALGSEL_SHA384,
+-		.alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ 	}, {
+ 		.name = "sha512",
+ 		.driver_name = "sha512-caam",
+@@ -1802,7 +1628,6 @@ static struct caam_hash_template driver_
+ 			},
+ 		},
+ 		.alg_type = OP_ALG_ALGSEL_SHA512,
+-		.alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ 	}, {
+ 		.name = "md5",
+ 		.driver_name = "md5-caam",
+@@ -1824,14 +1649,12 @@ static struct caam_hash_template driver_
+ 			},
+ 		},
+ 		.alg_type = OP_ALG_ALGSEL_MD5,
+-		.alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ 	},
+ };
+ 
+ struct caam_hash_alg {
+ 	struct list_head entry;
+ 	int alg_type;
+-	int alg_op;
+ 	struct ahash_alg ahash_alg;
+ };
+ 
+@@ -1853,6 +1676,8 @@ static int caam_hash_cra_init(struct cry
+ 					 HASH_MSG_LEN + SHA256_DIGEST_SIZE,
+ 					 HASH_MSG_LEN + 64,
+ 					 HASH_MSG_LEN + SHA512_DIGEST_SIZE };
++	dma_addr_t dma_addr;
++	struct caam_drv_private *priv;
+ 
+ 	/*
+ 	 * Get a Job ring from Job Ring driver to ensure in-order
+@@ -1863,11 +1688,34 @@ static int caam_hash_cra_init(struct cry
+ 		pr_err("Job Ring Device allocation for transform failed\n");
+ 		return PTR_ERR(ctx->jrdev);
+ 	}
++
++	priv = dev_get_drvdata(ctx->jrdev->parent);
++	ctx->dir = priv->era >= 6 ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
++
++	dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_update,
++					offsetof(struct caam_hash_ctx,
++						 sh_desc_update_dma),
++					ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
++	if (dma_mapping_error(ctx->jrdev, dma_addr)) {
++		dev_err(ctx->jrdev, "unable to map shared descriptors\n");
++		caam_jr_free(ctx->jrdev);
++		return -ENOMEM;
++	}
++
++	ctx->sh_desc_update_dma = dma_addr;
++	ctx->sh_desc_update_first_dma = dma_addr +
++					offsetof(struct caam_hash_ctx,
++						 sh_desc_update_first);
++	ctx->sh_desc_fin_dma = dma_addr + offsetof(struct caam_hash_ctx,
++						   sh_desc_fin);
++	ctx->sh_desc_digest_dma = dma_addr + offsetof(struct caam_hash_ctx,
++						      sh_desc_digest);
++
+ 	/* copy descriptor header template value */
+-	ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
+-	ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op;
++	ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
+ 
+-	ctx->ctx_len = runninglen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
++	ctx->ctx_len = runninglen[(ctx->adata.algtype &
++				   OP_ALG_ALGSEL_SUBMASK) >>
+ 				  OP_ALG_ALGSEL_SHIFT];
+ 
+ 	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
+@@ -1879,30 +1727,10 @@ static void caam_hash_cra_exit(struct cr
+ {
+ 	struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
+ 
+-	if (ctx->sh_desc_update_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->sh_desc_update_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->sh_desc_update_dma,
+-				 desc_bytes(ctx->sh_desc_update),
+-				 DMA_TO_DEVICE);
+-	if (ctx->sh_desc_update_first_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->sh_desc_update_first_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->sh_desc_update_first_dma,
+-				 desc_bytes(ctx->sh_desc_update_first),
+-				 DMA_TO_DEVICE);
+-	if (ctx->sh_desc_fin_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->sh_desc_fin_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->sh_desc_fin_dma,
+-				 desc_bytes(ctx->sh_desc_fin), DMA_TO_DEVICE);
+-	if (ctx->sh_desc_digest_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->sh_desc_digest_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->sh_desc_digest_dma,
+-				 desc_bytes(ctx->sh_desc_digest),
+-				 DMA_TO_DEVICE);
+-	if (ctx->sh_desc_finup_dma &&
+-	    !dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma))
+-		dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma,
+-				 desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE);
+-
++	dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_update_dma,
++			       offsetof(struct caam_hash_ctx,
++					sh_desc_update_dma),
++			       ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
+ 	caam_jr_free(ctx->jrdev);
+ }
+ 
+@@ -1961,7 +1789,6 @@ caam_hash_alloc(struct caam_hash_templat
+ 	alg->cra_type = &crypto_ahash_type;
+ 
+ 	t_alg->alg_type = template->alg_type;
+-	t_alg->alg_op = template->alg_op;
+ 
+ 	return t_alg;
+ }
+--- /dev/null
++++ b/drivers/crypto/caam/caamhash_desc.c
+@@ -0,0 +1,108 @@
++/*
++ * Shared descriptors for ahash algorithms
++ *
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the names of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include "compat.h"
++#include "desc_constr.h"
++#include "caamhash_desc.h"
++
++/**
++ * cnstr_shdsc_ahash - ahash shared descriptor
++ * @desc: pointer to buffer used for descriptor construction
++ * @adata: pointer to authentication transform definitions.
++ *         A split key is required for SEC Era < 6; the size of the split key
++ *         is specified in this case.
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224,
++ *         SHA256, SHA384, SHA512}.
++ * @state: algorithm state OP_ALG_AS_{INIT, FINALIZE, INITFINALIZE, UPDATE}
++ * @digestsize: algorithm's digest size
++ * @ctx_len: size of Context Register
++ * @import_ctx: true if previous Context Register needs to be restored
++ *              must be true for ahash update and final
++ *              must be false for for ahash first and digest
++ * @era: SEC Era
++ */
++void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state,
++		       int digestsize, int ctx_len, bool import_ctx, int era)
++{
++	u32 op = adata->algtype;
++
++	init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++	/* Append key if it has been set; ahash update excluded */
++	if (state != OP_ALG_AS_UPDATE && adata->keylen) {
++		u32 *skip_key_load;
++
++		/* Skip key loading if already shared */
++		skip_key_load = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++					    JUMP_COND_SHRD);
++
++		if (era < 6)
++			append_key_as_imm(desc, adata->key_virt,
++					  adata->keylen_pad,
++					  adata->keylen, CLASS_2 |
++					  KEY_DEST_MDHA_SPLIT | KEY_ENC);
++		else
++			append_proto_dkp(desc, adata);
++
++		set_jump_tgt_here(desc, skip_key_load);
++
++		op |= OP_ALG_AAI_HMAC_PRECOMP;
++	}
++
++	/* If needed, import context from software */
++	if (import_ctx)
++		append_seq_load(desc, ctx_len, LDST_CLASS_2_CCB |
++				LDST_SRCDST_BYTE_CONTEXT);
++
++	/* Class 2 operation */
++	append_operation(desc, op | state | OP_ALG_ENCRYPT);
++
++	/*
++	 * Load from buf and/or src and write to req->result or state->context
++	 * Calculate remaining bytes to read
++	 */
++	append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++	/* Read remaining bytes */
++	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 |
++			     FIFOLD_TYPE_MSG | KEY_VLF);
++	/* Store class2 context bytes */
++	append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
++			 LDST_SRCDST_BYTE_CONTEXT);
++}
++EXPORT_SYMBOL(cnstr_shdsc_ahash);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM ahash descriptors support");
++MODULE_AUTHOR("NXP Semiconductors");
+--- /dev/null
++++ b/drivers/crypto/caam/caamhash_desc.h
+@@ -0,0 +1,49 @@
++/*
++ * Shared descriptors for ahash algorithms
++ *
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the names of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef _CAAMHASH_DESC_H_
++#define _CAAMHASH_DESC_H_
++
++/* length of descriptors text */
++#define DESC_AHASH_BASE			(3 * CAAM_CMD_SZ)
++#define DESC_AHASH_UPDATE_LEN		(6 * CAAM_CMD_SZ)
++#define DESC_AHASH_UPDATE_FIRST_LEN	(DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
++#define DESC_AHASH_FINAL_LEN		(DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
++#define DESC_AHASH_DIGEST_LEN		(DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
++
++void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state,
++		       int digestsize, int ctx_len, bool import_ctx, int era);
++
++#endif /* _CAAMHASH_DESC_H_ */
+--- a/drivers/crypto/caam/caampkc.c
++++ b/drivers/crypto/caam/caampkc.c
+@@ -18,6 +18,10 @@
+ #define DESC_RSA_PUB_LEN	(2 * CAAM_CMD_SZ + sizeof(struct rsa_pub_pdb))
+ #define DESC_RSA_PRIV_F1_LEN	(2 * CAAM_CMD_SZ + \
+ 				 sizeof(struct rsa_priv_f1_pdb))
++#define DESC_RSA_PRIV_F2_LEN	(2 * CAAM_CMD_SZ + \
++				 sizeof(struct rsa_priv_f2_pdb))
++#define DESC_RSA_PRIV_F3_LEN	(2 * CAAM_CMD_SZ + \
++				 sizeof(struct rsa_priv_f3_pdb))
+ 
+ static void rsa_io_unmap(struct device *dev, struct rsa_edesc *edesc,
+ 			 struct akcipher_request *req)
+@@ -54,6 +58,42 @@ static void rsa_priv_f1_unmap(struct dev
+ 	dma_unmap_single(dev, pdb->d_dma, key->d_sz, DMA_TO_DEVICE);
+ }
+ 
++static void rsa_priv_f2_unmap(struct device *dev, struct rsa_edesc *edesc,
++			      struct akcipher_request *req)
++{
++	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
++	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
++	struct caam_rsa_key *key = &ctx->key;
++	struct rsa_priv_f2_pdb *pdb = &edesc->pdb.priv_f2;
++	size_t p_sz = key->p_sz;
++	size_t q_sz = key->p_sz;
++
++	dma_unmap_single(dev, pdb->d_dma, key->d_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->p_dma, p_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->q_dma, q_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->tmp1_dma, p_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->tmp2_dma, q_sz, DMA_TO_DEVICE);
++}
++
++static void rsa_priv_f3_unmap(struct device *dev, struct rsa_edesc *edesc,
++			      struct akcipher_request *req)
++{
++	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
++	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
++	struct caam_rsa_key *key = &ctx->key;
++	struct rsa_priv_f3_pdb *pdb = &edesc->pdb.priv_f3;
++	size_t p_sz = key->p_sz;
++	size_t q_sz = key->p_sz;
++
++	dma_unmap_single(dev, pdb->p_dma, p_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->q_dma, q_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->dp_dma, p_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->dq_dma, q_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->c_dma, p_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->tmp1_dma, p_sz, DMA_TO_DEVICE);
++	dma_unmap_single(dev, pdb->tmp2_dma, q_sz, DMA_TO_DEVICE);
++}
++
+ /* RSA Job Completion handler */
+ static void rsa_pub_done(struct device *dev, u32 *desc, u32 err, void *context)
+ {
+@@ -90,6 +130,42 @@ static void rsa_priv_f1_done(struct devi
+ 	akcipher_request_complete(req, err);
+ }
+ 
++static void rsa_priv_f2_done(struct device *dev, u32 *desc, u32 err,
++			     void *context)
++{
++	struct akcipher_request *req = context;
++	struct rsa_edesc *edesc;
++
++	if (err)
++		caam_jr_strstatus(dev, err);
++
++	edesc = container_of(desc, struct rsa_edesc, hw_desc[0]);
++
++	rsa_priv_f2_unmap(dev, edesc, req);
++	rsa_io_unmap(dev, edesc, req);
++	kfree(edesc);
++
++	akcipher_request_complete(req, err);
++}
++
++static void rsa_priv_f3_done(struct device *dev, u32 *desc, u32 err,
++			     void *context)
++{
++	struct akcipher_request *req = context;
++	struct rsa_edesc *edesc;
++
++	if (err)
++		caam_jr_strstatus(dev, err);
++
++	edesc = container_of(desc, struct rsa_edesc, hw_desc[0]);
++
++	rsa_priv_f3_unmap(dev, edesc, req);
++	rsa_io_unmap(dev, edesc, req);
++	kfree(edesc);
++
++	akcipher_request_complete(req, err);
++}
++
+ static struct rsa_edesc *rsa_edesc_alloc(struct akcipher_request *req,
+ 					 size_t desclen)
+ {
+@@ -97,8 +173,8 @@ static struct rsa_edesc *rsa_edesc_alloc
+ 	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
+ 	struct device *dev = ctx->dev;
+ 	struct rsa_edesc *edesc;
+-	gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+-		       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
++	gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
++		       GFP_KERNEL : GFP_ATOMIC;
+ 	int sgc;
+ 	int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
+ 	int src_nents, dst_nents;
+@@ -258,6 +334,172 @@ static int set_rsa_priv_f1_pdb(struct ak
+ 	return 0;
+ }
+ 
++static int set_rsa_priv_f2_pdb(struct akcipher_request *req,
++			       struct rsa_edesc *edesc)
++{
++	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
++	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
++	struct caam_rsa_key *key = &ctx->key;
++	struct device *dev = ctx->dev;
++	struct rsa_priv_f2_pdb *pdb = &edesc->pdb.priv_f2;
++	int sec4_sg_index = 0;
++	size_t p_sz = key->p_sz;
++	size_t q_sz = key->p_sz;
++
++	pdb->d_dma = dma_map_single(dev, key->d, key->d_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->d_dma)) {
++		dev_err(dev, "Unable to map RSA private exponent memory\n");
++		return -ENOMEM;
++	}
++
++	pdb->p_dma = dma_map_single(dev, key->p, p_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->p_dma)) {
++		dev_err(dev, "Unable to map RSA prime factor p memory\n");
++		goto unmap_d;
++	}
++
++	pdb->q_dma = dma_map_single(dev, key->q, q_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->q_dma)) {
++		dev_err(dev, "Unable to map RSA prime factor q memory\n");
++		goto unmap_p;
++	}
++
++	pdb->tmp1_dma = dma_map_single(dev, key->tmp1, p_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->tmp1_dma)) {
++		dev_err(dev, "Unable to map RSA tmp1 memory\n");
++		goto unmap_q;
++	}
++
++	pdb->tmp2_dma = dma_map_single(dev, key->tmp2, q_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->tmp2_dma)) {
++		dev_err(dev, "Unable to map RSA tmp2 memory\n");
++		goto unmap_tmp1;
++	}
++
++	if (edesc->src_nents > 1) {
++		pdb->sgf |= RSA_PRIV_PDB_SGF_G;
++		pdb->g_dma = edesc->sec4_sg_dma;
++		sec4_sg_index += edesc->src_nents;
++	} else {
++		pdb->g_dma = sg_dma_address(req->src);
++	}
++
++	if (edesc->dst_nents > 1) {
++		pdb->sgf |= RSA_PRIV_PDB_SGF_F;
++		pdb->f_dma = edesc->sec4_sg_dma +
++			     sec4_sg_index * sizeof(struct sec4_sg_entry);
++	} else {
++		pdb->f_dma = sg_dma_address(req->dst);
++	}
++
++	pdb->sgf |= (key->d_sz << RSA_PDB_D_SHIFT) | key->n_sz;
++	pdb->p_q_len = (q_sz << RSA_PDB_Q_SHIFT) | p_sz;
++
++	return 0;
++
++unmap_tmp1:
++	dma_unmap_single(dev, pdb->tmp1_dma, p_sz, DMA_TO_DEVICE);
++unmap_q:
++	dma_unmap_single(dev, pdb->q_dma, q_sz, DMA_TO_DEVICE);
++unmap_p:
++	dma_unmap_single(dev, pdb->p_dma, p_sz, DMA_TO_DEVICE);
++unmap_d:
++	dma_unmap_single(dev, pdb->d_dma, key->d_sz, DMA_TO_DEVICE);
++
++	return -ENOMEM;
++}
++
++static int set_rsa_priv_f3_pdb(struct akcipher_request *req,
++			       struct rsa_edesc *edesc)
++{
++	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
++	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
++	struct caam_rsa_key *key = &ctx->key;
++	struct device *dev = ctx->dev;
++	struct rsa_priv_f3_pdb *pdb = &edesc->pdb.priv_f3;
++	int sec4_sg_index = 0;
++	size_t p_sz = key->p_sz;
++	size_t q_sz = key->p_sz;
++
++	pdb->p_dma = dma_map_single(dev, key->p, p_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->p_dma)) {
++		dev_err(dev, "Unable to map RSA prime factor p memory\n");
++		return -ENOMEM;
++	}
++
++	pdb->q_dma = dma_map_single(dev, key->q, q_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->q_dma)) {
++		dev_err(dev, "Unable to map RSA prime factor q memory\n");
++		goto unmap_p;
++	}
++
++	pdb->dp_dma = dma_map_single(dev, key->dp, p_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->dp_dma)) {
++		dev_err(dev, "Unable to map RSA exponent dp memory\n");
++		goto unmap_q;
++	}
++
++	pdb->dq_dma = dma_map_single(dev, key->dq, q_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->dq_dma)) {
++		dev_err(dev, "Unable to map RSA exponent dq memory\n");
++		goto unmap_dp;
++	}
++
++	pdb->c_dma = dma_map_single(dev, key->qinv, p_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->c_dma)) {
++		dev_err(dev, "Unable to map RSA CRT coefficient qinv memory\n");
++		goto unmap_dq;
++	}
++
++	pdb->tmp1_dma = dma_map_single(dev, key->tmp1, p_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->tmp1_dma)) {
++		dev_err(dev, "Unable to map RSA tmp1 memory\n");
++		goto unmap_qinv;
++	}
++
++	pdb->tmp2_dma = dma_map_single(dev, key->tmp2, q_sz, DMA_TO_DEVICE);
++	if (dma_mapping_error(dev, pdb->tmp2_dma)) {
++		dev_err(dev, "Unable to map RSA tmp2 memory\n");
++		goto unmap_tmp1;
++	}
++
++	if (edesc->src_nents > 1) {
++		pdb->sgf |= RSA_PRIV_PDB_SGF_G;
++		pdb->g_dma = edesc->sec4_sg_dma;
++		sec4_sg_index += edesc->src_nents;
++	} else {
++		pdb->g_dma = sg_dma_address(req->src);
++	}
++
++	if (edesc->dst_nents > 1) {
++		pdb->sgf |= RSA_PRIV_PDB_SGF_F;
++		pdb->f_dma = edesc->sec4_sg_dma +
++			     sec4_sg_index * sizeof(struct sec4_sg_entry);
++	} else {
++		pdb->f_dma = sg_dma_address(req->dst);
++	}
++
++	pdb->sgf |= key->n_sz;
++	pdb->p_q_len = (q_sz << RSA_PDB_Q_SHIFT) | p_sz;
++
++	return 0;
++
++unmap_tmp1:
++	dma_unmap_single(dev, pdb->tmp1_dma, p_sz, DMA_TO_DEVICE);
++unmap_qinv:
++	dma_unmap_single(dev, pdb->c_dma, p_sz, DMA_TO_DEVICE);
++unmap_dq:
++	dma_unmap_single(dev, pdb->dq_dma, q_sz, DMA_TO_DEVICE);
++unmap_dp:
++	dma_unmap_single(dev, pdb->dp_dma, p_sz, DMA_TO_DEVICE);
++unmap_q:
++	dma_unmap_single(dev, pdb->q_dma, q_sz, DMA_TO_DEVICE);
++unmap_p:
++	dma_unmap_single(dev, pdb->p_dma, p_sz, DMA_TO_DEVICE);
++
++	return -ENOMEM;
++}
++
+ static int caam_rsa_enc(struct akcipher_request *req)
+ {
+ 	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
+@@ -301,24 +543,14 @@ init_fail:
+ 	return ret;
+ }
+ 
+-static int caam_rsa_dec(struct akcipher_request *req)
++static int caam_rsa_dec_priv_f1(struct akcipher_request *req)
+ {
+ 	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
+ 	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
+-	struct caam_rsa_key *key = &ctx->key;
+ 	struct device *jrdev = ctx->dev;
+ 	struct rsa_edesc *edesc;
+ 	int ret;
+ 
+-	if (unlikely(!key->n || !key->d))
+-		return -EINVAL;
+-
+-	if (req->dst_len < key->n_sz) {
+-		req->dst_len = key->n_sz;
+-		dev_err(jrdev, "Output buffer length less than parameter n\n");
+-		return -EOVERFLOW;
+-	}
+-
+ 	/* Allocate extended descriptor */
+ 	edesc = rsa_edesc_alloc(req, DESC_RSA_PRIV_F1_LEN);
+ 	if (IS_ERR(edesc))
+@@ -344,17 +576,147 @@ init_fail:
+ 	return ret;
+ }
+ 
++static int caam_rsa_dec_priv_f2(struct akcipher_request *req)
++{
++	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
++	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
++	struct device *jrdev = ctx->dev;
++	struct rsa_edesc *edesc;
++	int ret;
++
++	/* Allocate extended descriptor */
++	edesc = rsa_edesc_alloc(req, DESC_RSA_PRIV_F2_LEN);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	/* Set RSA Decrypt Protocol Data Block - Private Key Form #2 */
++	ret = set_rsa_priv_f2_pdb(req, edesc);
++	if (ret)
++		goto init_fail;
++
++	/* Initialize Job Descriptor */
++	init_rsa_priv_f2_desc(edesc->hw_desc, &edesc->pdb.priv_f2);
++
++	ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f2_done, req);
++	if (!ret)
++		return -EINPROGRESS;
++
++	rsa_priv_f2_unmap(jrdev, edesc, req);
++
++init_fail:
++	rsa_io_unmap(jrdev, edesc, req);
++	kfree(edesc);
++	return ret;
++}
++
++static int caam_rsa_dec_priv_f3(struct akcipher_request *req)
++{
++	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
++	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
++	struct device *jrdev = ctx->dev;
++	struct rsa_edesc *edesc;
++	int ret;
++
++	/* Allocate extended descriptor */
++	edesc = rsa_edesc_alloc(req, DESC_RSA_PRIV_F3_LEN);
++	if (IS_ERR(edesc))
++		return PTR_ERR(edesc);
++
++	/* Set RSA Decrypt Protocol Data Block - Private Key Form #3 */
++	ret = set_rsa_priv_f3_pdb(req, edesc);
++	if (ret)
++		goto init_fail;
++
++	/* Initialize Job Descriptor */
++	init_rsa_priv_f3_desc(edesc->hw_desc, &edesc->pdb.priv_f3);
++
++	ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f3_done, req);
++	if (!ret)
++		return -EINPROGRESS;
++
++	rsa_priv_f3_unmap(jrdev, edesc, req);
++
++init_fail:
++	rsa_io_unmap(jrdev, edesc, req);
++	kfree(edesc);
++	return ret;
++}
++
++static int caam_rsa_dec(struct akcipher_request *req)
++{
++	struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
++	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
++	struct caam_rsa_key *key = &ctx->key;
++	int ret;
++
++	if (unlikely(!key->n || !key->d))
++		return -EINVAL;
++
++	if (req->dst_len < key->n_sz) {
++		req->dst_len = key->n_sz;
++		dev_err(ctx->dev, "Output buffer length less than parameter n\n");
++		return -EOVERFLOW;
++	}
++
++	if (key->priv_form == FORM3)
++		ret = caam_rsa_dec_priv_f3(req);
++	else if (key->priv_form == FORM2)
++		ret = caam_rsa_dec_priv_f2(req);
++	else
++		ret = caam_rsa_dec_priv_f1(req);
++
++	return ret;
++}
++
+ static void caam_rsa_free_key(struct caam_rsa_key *key)
+ {
+ 	kzfree(key->d);
++	kzfree(key->p);
++	kzfree(key->q);
++	kzfree(key->dp);
++	kzfree(key->dq);
++	kzfree(key->qinv);
++	kzfree(key->tmp1);
++	kzfree(key->tmp2);
+ 	kfree(key->e);
+ 	kfree(key->n);
+-	key->d = NULL;
+-	key->e = NULL;
+-	key->n = NULL;
+-	key->d_sz = 0;
+-	key->e_sz = 0;
+-	key->n_sz = 0;
++	memset(key, 0, sizeof(*key));
++}
++
++static void caam_rsa_drop_leading_zeros(const u8 **ptr, size_t *nbytes)
++{
++	while (!**ptr && *nbytes) {
++		(*ptr)++;
++		(*nbytes)--;
++	}
++}
++
++/**
++ * caam_read_rsa_crt - Used for reading dP, dQ, qInv CRT members.
++ * dP, dQ and qInv could decode to less than corresponding p, q length, as the
++ * BER-encoding requires that the minimum number of bytes be used to encode the
++ * integer. dP, dQ, qInv decoded values have to be zero-padded to appropriate
++ * length.
++ *
++ * @ptr   : pointer to {dP, dQ, qInv} CRT member
++ * @nbytes: length in bytes of {dP, dQ, qInv} CRT member
++ * @dstlen: length in bytes of corresponding p or q prime factor
++ */
++static u8 *caam_read_rsa_crt(const u8 *ptr, size_t nbytes, size_t dstlen)
++{
++	u8 *dst;
++
++	caam_rsa_drop_leading_zeros(&ptr, &nbytes);
++	if (!nbytes)
++		return NULL;
++
++	dst = kzalloc(dstlen, GFP_DMA | GFP_KERNEL);
++	if (!dst)
++		return NULL;
++
++	memcpy(dst + (dstlen - nbytes), ptr, nbytes);
++
++	return dst;
+ }
+ 
+ /**
+@@ -370,10 +732,9 @@ static inline u8 *caam_read_raw_data(con
+ {
+ 	u8 *val;
+ 
+-	while (!*buf && *nbytes) {
+-		buf++;
+-		(*nbytes)--;
+-	}
++	caam_rsa_drop_leading_zeros(&buf, nbytes);
++	if (!*nbytes)
++		return NULL;
+ 
+ 	val = kzalloc(*nbytes, GFP_DMA | GFP_KERNEL);
+ 	if (!val)
+@@ -395,7 +756,7 @@ static int caam_rsa_set_pub_key(struct c
+ 				unsigned int keylen)
+ {
+ 	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
+-	struct rsa_key raw_key = {0};
++	struct rsa_key raw_key = {NULL};
+ 	struct caam_rsa_key *rsa_key = &ctx->key;
+ 	int ret;
+ 
+@@ -437,11 +798,69 @@ err:
+ 	return -ENOMEM;
+ }
+ 
++static void caam_rsa_set_priv_key_form(struct caam_rsa_ctx *ctx,
++				       struct rsa_key *raw_key)
++{
++	struct caam_rsa_key *rsa_key = &ctx->key;
++	size_t p_sz = raw_key->p_sz;
++	size_t q_sz = raw_key->q_sz;
++
++	rsa_key->p = caam_read_raw_data(raw_key->p, &p_sz);
++	if (!rsa_key->p)
++		return;
++	rsa_key->p_sz = p_sz;
++
++	rsa_key->q = caam_read_raw_data(raw_key->q, &q_sz);
++	if (!rsa_key->q)
++		goto free_p;
++	rsa_key->q_sz = q_sz;
++
++	rsa_key->tmp1 = kzalloc(raw_key->p_sz, GFP_DMA | GFP_KERNEL);
++	if (!rsa_key->tmp1)
++		goto free_q;
++
++	rsa_key->tmp2 = kzalloc(raw_key->q_sz, GFP_DMA | GFP_KERNEL);
++	if (!rsa_key->tmp2)
++		goto free_tmp1;
++
++	rsa_key->priv_form = FORM2;
++
++	rsa_key->dp = caam_read_rsa_crt(raw_key->dp, raw_key->dp_sz, p_sz);
++	if (!rsa_key->dp)
++		goto free_tmp2;
++
++	rsa_key->dq = caam_read_rsa_crt(raw_key->dq, raw_key->dq_sz, q_sz);
++	if (!rsa_key->dq)
++		goto free_dp;
++
++	rsa_key->qinv = caam_read_rsa_crt(raw_key->qinv, raw_key->qinv_sz,
++					  q_sz);
++	if (!rsa_key->qinv)
++		goto free_dq;
++
++	rsa_key->priv_form = FORM3;
++
++	return;
++
++free_dq:
++	kzfree(rsa_key->dq);
++free_dp:
++	kzfree(rsa_key->dp);
++free_tmp2:
++	kzfree(rsa_key->tmp2);
++free_tmp1:
++	kzfree(rsa_key->tmp1);
++free_q:
++	kzfree(rsa_key->q);
++free_p:
++	kzfree(rsa_key->p);
++}
++
+ static int caam_rsa_set_priv_key(struct crypto_akcipher *tfm, const void *key,
+ 				 unsigned int keylen)
+ {
+ 	struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
+-	struct rsa_key raw_key = {0};
++	struct rsa_key raw_key = {NULL};
+ 	struct caam_rsa_key *rsa_key = &ctx->key;
+ 	int ret;
+ 
+@@ -483,6 +902,8 @@ static int caam_rsa_set_priv_key(struct
+ 	memcpy(rsa_key->d, raw_key.d, raw_key.d_sz);
+ 	memcpy(rsa_key->e, raw_key.e, raw_key.e_sz);
+ 
++	caam_rsa_set_priv_key_form(ctx, &raw_key);
++
+ 	return 0;
+ 
+ err:
+--- a/drivers/crypto/caam/caampkc.h
++++ b/drivers/crypto/caam/caampkc.h
+@@ -13,21 +13,75 @@
+ #include "pdb.h"
+ 
+ /**
++ * caam_priv_key_form - CAAM RSA private key representation
++ * CAAM RSA private key may have either of three forms.
++ *
++ * 1. The first representation consists of the pair (n, d), where the
++ *    components have the following meanings:
++ *        n      the RSA modulus
++ *        d      the RSA private exponent
++ *
++ * 2. The second representation consists of the triplet (p, q, d), where the
++ *    components have the following meanings:
++ *        p      the first prime factor of the RSA modulus n
++ *        q      the second prime factor of the RSA modulus n
++ *        d      the RSA private exponent
++ *
++ * 3. The third representation consists of the quintuple (p, q, dP, dQ, qInv),
++ *    where the components have the following meanings:
++ *        p      the first prime factor of the RSA modulus n
++ *        q      the second prime factor of the RSA modulus n
++ *        dP     the first factors's CRT exponent
++ *        dQ     the second factors's CRT exponent
++ *        qInv   the (first) CRT coefficient
++ *
++ * The benefit of using the third or the second key form is lower computational
++ * cost for the decryption and signature operations.
++ */
++enum caam_priv_key_form {
++	FORM1,
++	FORM2,
++	FORM3
++};
++
++/**
+  * caam_rsa_key - CAAM RSA key structure. Keys are allocated in DMA zone.
+  * @n           : RSA modulus raw byte stream
+  * @e           : RSA public exponent raw byte stream
+  * @d           : RSA private exponent raw byte stream
++ * @p           : RSA prime factor p of RSA modulus n
++ * @q           : RSA prime factor q of RSA modulus n
++ * @dp          : RSA CRT exponent of p
++ * @dp          : RSA CRT exponent of q
++ * @qinv        : RSA CRT coefficient
++ * @tmp1        : CAAM uses this temporary buffer as internal state buffer.
++ *                It is assumed to be as long as p.
++ * @tmp2        : CAAM uses this temporary buffer as internal state buffer.
++ *                It is assumed to be as long as q.
+  * @n_sz        : length in bytes of RSA modulus n
+  * @e_sz        : length in bytes of RSA public exponent
+  * @d_sz        : length in bytes of RSA private exponent
++ * @p_sz        : length in bytes of RSA prime factor p of RSA modulus n
++ * @q_sz        : length in bytes of RSA prime factor q of RSA modulus n
++ * @priv_form   : CAAM RSA private key representation
+  */
+ struct caam_rsa_key {
+ 	u8 *n;
+ 	u8 *e;
+ 	u8 *d;
++	u8 *p;
++	u8 *q;
++	u8 *dp;
++	u8 *dq;
++	u8 *qinv;
++	u8 *tmp1;
++	u8 *tmp2;
+ 	size_t n_sz;
+ 	size_t e_sz;
+ 	size_t d_sz;
++	size_t p_sz;
++	size_t q_sz;
++	enum caam_priv_key_form priv_form;
+ };
+ 
+ /**
+@@ -59,6 +113,8 @@ struct rsa_edesc {
+ 	union {
+ 		struct rsa_pub_pdb pub;
+ 		struct rsa_priv_f1_pdb priv_f1;
++		struct rsa_priv_f2_pdb priv_f2;
++		struct rsa_priv_f3_pdb priv_f3;
+ 	} pdb;
+ 	u32 hw_desc[];
+ };
+@@ -66,5 +122,7 @@ struct rsa_edesc {
+ /* Descriptor construction primitives. */
+ void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb);
+ void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb);
++void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb);
++void init_rsa_priv_f3_desc(u32 *desc, struct rsa_priv_f3_pdb *pdb);
+ 
+ #endif
+--- a/drivers/crypto/caam/caamrng.c
++++ b/drivers/crypto/caam/caamrng.c
+@@ -52,7 +52,7 @@
+ 
+ /* length of descriptors */
+ #define DESC_JOB_O_LEN			(CAAM_CMD_SZ * 2 + CAAM_PTR_SZ * 2)
+-#define DESC_RNG_LEN			(4 * CAAM_CMD_SZ)
++#define DESC_RNG_LEN			(3 * CAAM_CMD_SZ)
+ 
+ /* Buffer, its dma address and lock */
+ struct buf_data {
+@@ -100,8 +100,7 @@ static void rng_done(struct device *jrde
+ {
+ 	struct buf_data *bd;
+ 
+-	bd = (struct buf_data *)((char *)desc -
+-	      offsetof(struct buf_data, hw_desc));
++	bd = container_of(desc, struct buf_data, hw_desc[0]);
+ 
+ 	if (err)
+ 		caam_jr_strstatus(jrdev, err);
+@@ -196,9 +195,6 @@ static inline int rng_create_sh_desc(str
+ 
+ 	init_sh_desc(desc, HDR_SHARE_SERIAL);
+ 
+-	/* Propagate errors from shared to job descriptor */
+-	append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+-
+ 	/* Generate random bytes */
+ 	append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG);
+ 
+@@ -289,11 +285,7 @@ static int caam_init_rng(struct caam_rng
+ 	if (err)
+ 		return err;
+ 
+-	err = caam_init_buf(ctx, 1);
+-	if (err)
+-		return err;
+-
+-	return 0;
++	return caam_init_buf(ctx, 1);
+ }
+ 
+ static struct hwrng caam_rng = {
+@@ -351,7 +343,7 @@ static int __init caam_rng_init(void)
+ 		pr_err("Job Ring Device allocation for transform failed\n");
+ 		return PTR_ERR(dev);
+ 	}
+-	rng_ctx = kmalloc(sizeof(*rng_ctx), GFP_DMA);
++	rng_ctx = kmalloc(sizeof(*rng_ctx), GFP_DMA | GFP_KERNEL);
+ 	if (!rng_ctx) {
+ 		err = -ENOMEM;
+ 		goto free_caam_alloc;
+--- a/drivers/crypto/caam/compat.h
++++ b/drivers/crypto/caam/compat.h
+@@ -16,6 +16,7 @@
+ #include <linux/of_platform.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/io.h>
++#include <linux/iommu.h>
+ #include <linux/spinlock.h>
+ #include <linux/rtnetlink.h>
+ #include <linux/in.h>
+--- a/drivers/crypto/caam/ctrl.c
++++ b/drivers/crypto/caam/ctrl.c
+@@ -2,40 +2,41 @@
+  * Controller-level driver, kernel property detection, initialization
+  *
+  * Copyright 2008-2012 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
+  */
+ 
+ #include <linux/device.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <linux/sys_soc.h>
+ 
+ #include "compat.h"
+ #include "regs.h"
+ #include "intern.h"
+ #include "jr.h"
+ #include "desc_constr.h"
+-#include "error.h"
+ #include "ctrl.h"
+ 
+ bool caam_little_end;
+ EXPORT_SYMBOL(caam_little_end);
++bool caam_imx;
++EXPORT_SYMBOL(caam_imx);
++bool caam_dpaa2;
++EXPORT_SYMBOL(caam_dpaa2);
++
++#ifdef CONFIG_CAAM_QI
++#include "qi.h"
++#endif
+ 
+ /*
+  * i.MX targets tend to have clock control subsystems that can
+  * enable/disable clocking to our device.
+  */
+-#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
+-static inline struct clk *caam_drv_identify_clk(struct device *dev,
+-						char *clk_name)
+-{
+-	return devm_clk_get(dev, clk_name);
+-}
+-#else
+ static inline struct clk *caam_drv_identify_clk(struct device *dev,
+ 						char *clk_name)
+ {
+-	return NULL;
++	return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
+ }
+-#endif
+ 
+ /*
+  * Descriptor to instantiate RNG State Handle 0 in normal mode and
+@@ -274,7 +275,7 @@ static int deinstantiate_rng(struct devi
+ 		/*
+ 		 * If the corresponding bit is set, then it means the state
+ 		 * handle was initialized by us, and thus it needs to be
+-		 * deintialized as well
++		 * deinitialized as well
+ 		 */
+ 		if ((1 << sh_idx) & state_handle_mask) {
+ 			/*
+@@ -307,20 +308,24 @@ static int caam_remove(struct platform_d
+ 	struct device *ctrldev;
+ 	struct caam_drv_private *ctrlpriv;
+ 	struct caam_ctrl __iomem *ctrl;
+-	int ring;
+ 
+ 	ctrldev = &pdev->dev;
+ 	ctrlpriv = dev_get_drvdata(ctrldev);
+ 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
+ 
+-	/* Remove platform devices for JobRs */
+-	for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
+-		if (ctrlpriv->jrpdev[ring])
+-			of_device_unregister(ctrlpriv->jrpdev[ring]);
+-	}
++	/* Remove platform devices under the crypto node */
++	of_platform_depopulate(ctrldev);
++
++#ifdef CONFIG_CAAM_QI
++	if (ctrlpriv->qidev)
++		caam_qi_shutdown(ctrlpriv->qidev);
++#endif
+ 
+-	/* De-initialize RNG state handles initialized by this driver. */
+-	if (ctrlpriv->rng4_sh_init)
++	/*
++	 * De-initialize RNG state handles initialized by this driver.
++	 * In case of DPAA 2.x, RNG is managed by MC firmware.
++	 */
++	if (!caam_dpaa2 && ctrlpriv->rng4_sh_init)
+ 		deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
+ 
+ 	/* Shut down debug views */
+@@ -335,8 +340,8 @@ static int caam_remove(struct platform_d
+ 	clk_disable_unprepare(ctrlpriv->caam_ipg);
+ 	clk_disable_unprepare(ctrlpriv->caam_mem);
+ 	clk_disable_unprepare(ctrlpriv->caam_aclk);
+-	clk_disable_unprepare(ctrlpriv->caam_emi_slow);
+-
++	if (ctrlpriv->caam_emi_slow)
++		clk_disable_unprepare(ctrlpriv->caam_emi_slow);
+ 	return 0;
+ }
+ 
+@@ -370,11 +375,8 @@ static void kick_trng(struct platform_de
+ 	 */
+ 	val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
+ 	      >> RTSDCTL_ENT_DLY_SHIFT;
+-	if (ent_delay <= val) {
+-		/* put RNG4 into run mode */
+-		clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, 0);
+-		return;
+-	}
++	if (ent_delay <= val)
++		goto start_rng;
+ 
+ 	val = rd_reg32(&r4tst->rtsdctl);
+ 	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
+@@ -386,15 +388,12 @@ static void kick_trng(struct platform_de
+ 	wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
+ 	/* read the control register */
+ 	val = rd_reg32(&r4tst->rtmctl);
++start_rng:
+ 	/*
+ 	 * select raw sampling in both entropy shifter
+-	 * and statistical checker
++	 * and statistical checker; ; put RNG4 into run mode
+ 	 */
+-	clrsetbits_32(&val, 0, RTMCTL_SAMP_MODE_RAW_ES_SC);
+-	/* put RNG4 into run mode */
+-	clrsetbits_32(&val, RTMCTL_PRGM, 0);
+-	/* write back the control register */
+-	wr_reg32(&r4tst->rtmctl, val);
++	clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
+ }
+ 
+ /**
+@@ -415,28 +414,26 @@ int caam_get_era(void)
+ }
+ EXPORT_SYMBOL(caam_get_era);
+ 
+-#ifdef CONFIG_DEBUG_FS
+-static int caam_debugfs_u64_get(void *data, u64 *val)
+-{
+-	*val = caam64_to_cpu(*(u64 *)data);
+-	return 0;
+-}
+-
+-static int caam_debugfs_u32_get(void *data, u64 *val)
+-{
+-	*val = caam32_to_cpu(*(u32 *)data);
+-	return 0;
+-}
+-
+-DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
+-DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
+-#endif
++static const struct of_device_id caam_match[] = {
++	{
++		.compatible = "fsl,sec-v4.0",
++	},
++	{
++		.compatible = "fsl,sec4.0",
++	},
++	{},
++};
++MODULE_DEVICE_TABLE(of, caam_match);
+ 
+ /* Probe routine for CAAM top (controller) level */
+ static int caam_probe(struct platform_device *pdev)
+ {
+-	int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
++	int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
+ 	u64 caam_id;
++	static const struct soc_device_attribute imx_soc[] = {
++		{.family = "Freescale i.MX"},
++		{},
++	};
+ 	struct device *dev;
+ 	struct device_node *nprop, *np;
+ 	struct caam_ctrl __iomem *ctrl;
+@@ -456,9 +453,10 @@ static int caam_probe(struct platform_de
+ 
+ 	dev = &pdev->dev;
+ 	dev_set_drvdata(dev, ctrlpriv);
+-	ctrlpriv->pdev = pdev;
+ 	nprop = pdev->dev.of_node;
+ 
++	caam_imx = (bool)soc_device_match(imx_soc);
++
+ 	/* Enable clocking */
+ 	clk = caam_drv_identify_clk(&pdev->dev, "ipg");
+ 	if (IS_ERR(clk)) {
+@@ -487,14 +485,16 @@ static int caam_probe(struct platform_de
+ 	}
+ 	ctrlpriv->caam_aclk = clk;
+ 
+-	clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
+-	if (IS_ERR(clk)) {
+-		ret = PTR_ERR(clk);
+-		dev_err(&pdev->dev,
+-			"can't identify CAAM emi_slow clk: %d\n", ret);
+-		return ret;
++	if (!of_machine_is_compatible("fsl,imx6ul")) {
++		clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
++		if (IS_ERR(clk)) {
++			ret = PTR_ERR(clk);
++			dev_err(&pdev->dev,
++				"can't identify CAAM emi_slow clk: %d\n", ret);
++			return ret;
++		}
++		ctrlpriv->caam_emi_slow = clk;
+ 	}
+-	ctrlpriv->caam_emi_slow = clk;
+ 
+ 	ret = clk_prepare_enable(ctrlpriv->caam_ipg);
+ 	if (ret < 0) {
+@@ -515,11 +515,13 @@ static int caam_probe(struct platform_de
+ 		goto disable_caam_mem;
+ 	}
+ 
+-	ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
+-	if (ret < 0) {
+-		dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
+-			ret);
+-		goto disable_caam_aclk;
++	if (ctrlpriv->caam_emi_slow) {
++		ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
++		if (ret < 0) {
++			dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
++				ret);
++			goto disable_caam_aclk;
++		}
+ 	}
+ 
+ 	/* Get configuration properties from device tree */
+@@ -546,13 +548,13 @@ static int caam_probe(struct platform_de
+ 	else
+ 		BLOCK_OFFSET = PG_SIZE_64K;
+ 
+-	ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
+-	ctrlpriv->assure = (struct caam_assurance __force *)
+-			   ((uint8_t *)ctrl +
++	ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
++	ctrlpriv->assure = (struct caam_assurance __iomem __force *)
++			   ((__force uint8_t *)ctrl +
+ 			    BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
+ 			   );
+-	ctrlpriv->deco = (struct caam_deco __force *)
+-			 ((uint8_t *)ctrl +
++	ctrlpriv->deco = (struct caam_deco __iomem __force *)
++			 ((__force uint8_t *)ctrl +
+ 			 BLOCK_OFFSET * DECO_BLOCK_NUMBER
+ 			 );
+ 
+@@ -561,12 +563,17 @@ static int caam_probe(struct platform_de
+ 
+ 	/*
+ 	 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
+-	 * long pointers in master configuration register
++	 * long pointers in master configuration register.
++	 * In case of DPAA 2.x, Management Complex firmware performs
++	 * the configuration.
+ 	 */
+-	clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
+-		      MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
+-		      MCFGR_WDENABLE | MCFGR_LARGE_BURST |
+-		      (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
++	caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
++	if (!caam_dpaa2)
++		clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
++			      MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
++			      MCFGR_WDENABLE | MCFGR_LARGE_BURST |
++			      (sizeof(dma_addr_t) == sizeof(u64) ?
++			       MCFGR_LONG_PTR : 0));
+ 
+ 	/*
+ 	 *  Read the Compile Time paramters and SCFGR to determine
+@@ -594,64 +601,69 @@ static int caam_probe(struct platform_de
+ 			      JRSTART_JR1_START | JRSTART_JR2_START |
+ 			      JRSTART_JR3_START);
+ 
+-	if (sizeof(dma_addr_t) == sizeof(u64))
+-		if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
+-			dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
++	if (sizeof(dma_addr_t) == sizeof(u64)) {
++		if (caam_dpaa2)
++			ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
++		else if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
++			ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
+ 		else
+-			dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
+-	else
+-		dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
++			ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
++	} else {
++		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
++	}
++	if (ret) {
++		dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
++		goto iounmap_ctrl;
++	}
+ 
+-	/*
+-	 * Detect and enable JobRs
+-	 * First, find out how many ring spec'ed, allocate references
+-	 * for all, then go probe each one.
+-	 */
+-	rspec = 0;
+-	for_each_available_child_of_node(nprop, np)
+-		if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
+-		    of_device_is_compatible(np, "fsl,sec4.0-job-ring"))
+-			rspec++;
++	ctrlpriv->era = caam_get_era();
+ 
+-	ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec,
+-					sizeof(*ctrlpriv->jrpdev), GFP_KERNEL);
+-	if (ctrlpriv->jrpdev == NULL) {
+-		ret = -ENOMEM;
++	ret = of_platform_populate(nprop, caam_match, NULL, dev);
++	if (ret) {
++		dev_err(dev, "JR platform devices creation error\n");
+ 		goto iounmap_ctrl;
+ 	}
+ 
++#ifdef CONFIG_DEBUG_FS
++	/*
++	 * FIXME: needs better naming distinction, as some amalgamation of
++	 * "caam" and nprop->full_name. The OF name isn't distinctive,
++	 * but does separate instances
++	 */
++	perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
++
++	ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
++	ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
++#endif
+ 	ring = 0;
+-	ctrlpriv->total_jobrs = 0;
+ 	for_each_available_child_of_node(nprop, np)
+ 		if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
+ 		    of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
+-			ctrlpriv->jrpdev[ring] =
+-				of_platform_device_create(np, NULL, dev);
+-			if (!ctrlpriv->jrpdev[ring]) {
+-				pr_warn("JR%d Platform device creation error\n",
+-					ring);
+-				continue;
+-			}
+-			ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
+-					     ((uint8_t *)ctrl +
++			ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
++					     ((__force uint8_t *)ctrl +
+ 					     (ring + JR_BLOCK_NUMBER) *
+ 					      BLOCK_OFFSET
+ 					     );
+ 			ctrlpriv->total_jobrs++;
+ 			ring++;
+-	}
++		}
+ 
+-	/* Check to see if QI present. If so, enable */
+-	ctrlpriv->qi_present =
+-			!!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
+-			   CTPR_MS_QI_MASK);
+-	if (ctrlpriv->qi_present) {
+-		ctrlpriv->qi = (struct caam_queue_if __force *)
+-			       ((uint8_t *)ctrl +
++	/* Check to see if (DPAA 1.x) QI present. If so, enable */
++	ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
++	if (ctrlpriv->qi_present && !caam_dpaa2) {
++		ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
++			       ((__force uint8_t *)ctrl +
+ 				 BLOCK_OFFSET * QI_BLOCK_NUMBER
+ 			       );
+ 		/* This is all that's required to physically enable QI */
+ 		wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
++
++		/* If QMAN driver is present, init CAAM-QI backend */
++#ifdef CONFIG_CAAM_QI
++		ret = caam_qi_init(pdev);
++		if (ret)
++			dev_err(dev, "caam qi i/f init failed: %d\n", ret);
++#endif
+ 	}
+ 
+ 	/* If no QI and no rings specified, quit and go home */
+@@ -666,8 +678,10 @@ static int caam_probe(struct platform_de
+ 	/*
+ 	 * If SEC has RNG version >= 4 and RNG state handle has not been
+ 	 * already instantiated, do RNG instantiation
++	 * In case of DPAA 2.x, RNG is managed by MC firmware.
+ 	 */
+-	if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
++	if (!caam_dpaa2 &&
++	    (cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
+ 		ctrlpriv->rng4_sh_init =
+ 			rd_reg32(&ctrl->r4tst[0].rdsta);
+ 		/*
+@@ -734,78 +748,47 @@ static int caam_probe(struct platform_de
+ 
+ 	/* Report "alive" for developer to see */
+ 	dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
+-		 caam_get_era());
+-	dev_info(dev, "job rings = %d, qi = %d\n",
+-		 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
++		 ctrlpriv->era);
++	dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n",
++		 ctrlpriv->total_jobrs, ctrlpriv->qi_present,
++		 caam_dpaa2 ? "yes" : "no");
+ 
+ #ifdef CONFIG_DEBUG_FS
+-	/*
+-	 * FIXME: needs better naming distinction, as some amalgamation of
+-	 * "caam" and nprop->full_name. The OF name isn't distinctive,
+-	 * but does separate instances
+-	 */
+-	perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
+-
+-	ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
+-	ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
+-
+-	/* Controller-level - performance monitor counters */
+-
+-	ctrlpriv->ctl_rq_dequeued =
+-		debugfs_create_file("rq_dequeued",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->req_dequeued,
+-				    &caam_fops_u64_ro);
+-	ctrlpriv->ctl_ob_enc_req =
+-		debugfs_create_file("ob_rq_encrypted",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->ob_enc_req,
+-				    &caam_fops_u64_ro);
+-	ctrlpriv->ctl_ib_dec_req =
+-		debugfs_create_file("ib_rq_decrypted",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->ib_dec_req,
+-				    &caam_fops_u64_ro);
+-	ctrlpriv->ctl_ob_enc_bytes =
+-		debugfs_create_file("ob_bytes_encrypted",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->ob_enc_bytes,
+-				    &caam_fops_u64_ro);
+-	ctrlpriv->ctl_ob_prot_bytes =
+-		debugfs_create_file("ob_bytes_protected",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->ob_prot_bytes,
+-				    &caam_fops_u64_ro);
+-	ctrlpriv->ctl_ib_dec_bytes =
+-		debugfs_create_file("ib_bytes_decrypted",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->ib_dec_bytes,
+-				    &caam_fops_u64_ro);
+-	ctrlpriv->ctl_ib_valid_bytes =
+-		debugfs_create_file("ib_bytes_validated",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->ib_valid_bytes,
+-				    &caam_fops_u64_ro);
++	debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->req_dequeued,
++			    &caam_fops_u64_ro);
++	debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->ob_enc_req,
++			    &caam_fops_u64_ro);
++	debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->ib_dec_req,
++			    &caam_fops_u64_ro);
++	debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->ob_enc_bytes,
++			    &caam_fops_u64_ro);
++	debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->ob_prot_bytes,
++			    &caam_fops_u64_ro);
++	debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->ib_dec_bytes,
++			    &caam_fops_u64_ro);
++	debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->ib_valid_bytes,
++			    &caam_fops_u64_ro);
+ 
+ 	/* Controller level - global status values */
+-	ctrlpriv->ctl_faultaddr =
+-		debugfs_create_file("fault_addr",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->faultaddr,
+-				    &caam_fops_u32_ro);
+-	ctrlpriv->ctl_faultdetail =
+-		debugfs_create_file("fault_detail",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->faultdetail,
+-				    &caam_fops_u32_ro);
+-	ctrlpriv->ctl_faultstatus =
+-		debugfs_create_file("fault_status",
+-				    S_IRUSR | S_IRGRP | S_IROTH,
+-				    ctrlpriv->ctl, &perfmon->status,
+-				    &caam_fops_u32_ro);
++	debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->faultaddr,
++			    &caam_fops_u32_ro);
++	debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->faultdetail,
++			    &caam_fops_u32_ro);
++	debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH,
++			    ctrlpriv->ctl, &perfmon->status,
++			    &caam_fops_u32_ro);
+ 
+ 	/* Internal covering keys (useful in non-secure mode only) */
+-	ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
++	ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
+ 	ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
+ 	ctrlpriv->ctl_kek = debugfs_create_blob("kek",
+ 						S_IRUSR |
+@@ -813,7 +796,7 @@ static int caam_probe(struct platform_de
+ 						ctrlpriv->ctl,
+ 						&ctrlpriv->ctl_kek_wrap);
+ 
+-	ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
++	ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
+ 	ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
+ 	ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
+ 						 S_IRUSR |
+@@ -821,7 +804,7 @@ static int caam_probe(struct platform_de
+ 						 ctrlpriv->ctl,
+ 						 &ctrlpriv->ctl_tkek_wrap);
+ 
+-	ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
++	ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
+ 	ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
+ 	ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
+ 						 S_IRUSR |
+@@ -832,13 +815,17 @@ static int caam_probe(struct platform_de
+ 	return 0;
+ 
+ caam_remove:
++#ifdef CONFIG_DEBUG_FS
++	debugfs_remove_recursive(ctrlpriv->dfs_root);
++#endif
+ 	caam_remove(pdev);
+ 	return ret;
+ 
+ iounmap_ctrl:
+ 	iounmap(ctrl);
+ disable_caam_emi_slow:
+-	clk_disable_unprepare(ctrlpriv->caam_emi_slow);
++	if (ctrlpriv->caam_emi_slow)
++		clk_disable_unprepare(ctrlpriv->caam_emi_slow);
+ disable_caam_aclk:
+ 	clk_disable_unprepare(ctrlpriv->caam_aclk);
+ disable_caam_mem:
+@@ -848,17 +835,6 @@ disable_caam_ipg:
+ 	return ret;
+ }
+ 
+-static struct of_device_id caam_match[] = {
+-	{
+-		.compatible = "fsl,sec-v4.0",
+-	},
+-	{
+-		.compatible = "fsl,sec4.0",
+-	},
+-	{},
+-};
+-MODULE_DEVICE_TABLE(of, caam_match);
+-
+ static struct platform_driver caam_driver = {
+ 	.driver = {
+ 		.name = "caam",
+--- a/drivers/crypto/caam/ctrl.h
++++ b/drivers/crypto/caam/ctrl.h
+@@ -10,4 +10,6 @@
+ /* Prototypes for backend-level services exposed to APIs */
+ int caam_get_era(void);
+ 
++extern bool caam_dpaa2;
++
+ #endif /* CTRL_H */
+--- a/drivers/crypto/caam/desc.h
++++ b/drivers/crypto/caam/desc.h
+@@ -22,12 +22,6 @@
+ #define SEC4_SG_LEN_MASK	0x3fffffff	/* Excludes EXT and FINAL */
+ #define SEC4_SG_OFFSET_MASK	0x00001fff
+ 
+-struct sec4_sg_entry {
+-	u64 ptr;
+-	u32 len;
+-	u32 bpid_offset;
+-};
+-
+ /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
+ #define MAX_CAAM_DESCSIZE	64
+ 
+@@ -47,6 +41,7 @@ struct sec4_sg_entry {
+ #define CMD_SEQ_LOAD		(0x03 << CMD_SHIFT)
+ #define CMD_FIFO_LOAD		(0x04 << CMD_SHIFT)
+ #define CMD_SEQ_FIFO_LOAD	(0x05 << CMD_SHIFT)
++#define CMD_MOVEB		(0x07 << CMD_SHIFT)
+ #define CMD_STORE		(0x0a << CMD_SHIFT)
+ #define CMD_SEQ_STORE		(0x0b << CMD_SHIFT)
+ #define CMD_FIFO_STORE		(0x0c << CMD_SHIFT)
+@@ -90,8 +85,8 @@ struct sec4_sg_entry {
+ #define HDR_ZRO			0x00008000
+ 
+ /* Start Index or SharedDesc Length */
+-#define HDR_START_IDX_MASK	0x3f
+ #define HDR_START_IDX_SHIFT	16
++#define HDR_START_IDX_MASK	(0x3f << HDR_START_IDX_SHIFT)
+ 
+ /* If shared descriptor header, 6-bit length */
+ #define HDR_DESCLEN_SHR_MASK	0x3f
+@@ -121,10 +116,10 @@ struct sec4_sg_entry {
+ #define HDR_PROP_DNR		0x00000800
+ 
+ /* JobDesc/SharedDesc share property */
+-#define HDR_SD_SHARE_MASK	0x03
+ #define HDR_SD_SHARE_SHIFT	8
+-#define HDR_JD_SHARE_MASK	0x07
++#define HDR_SD_SHARE_MASK	(0x03 << HDR_SD_SHARE_SHIFT)
+ #define HDR_JD_SHARE_SHIFT	8
++#define HDR_JD_SHARE_MASK	(0x07 << HDR_JD_SHARE_SHIFT)
+ 
+ #define HDR_SHARE_NEVER		(0x00 << HDR_SD_SHARE_SHIFT)
+ #define HDR_SHARE_WAIT		(0x01 << HDR_SD_SHARE_SHIFT)
+@@ -235,7 +230,7 @@ struct sec4_sg_entry {
+ #define LDST_SRCDST_WORD_DECO_MATH2	(0x0a << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_DECO_AAD_SZ	(0x0b << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_DECO_MATH3	(0x0b << LDST_SRCDST_SHIFT)
+-#define LDST_SRCDST_WORD_CLASS1_ICV_SZ	(0x0c << LDST_SRCDST_SHIFT)
++#define LDST_SRCDST_WORD_CLASS1_IV_SZ	(0x0c << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_ALTDS_CLASS1	(0x0f << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_PKHA_A_SZ	(0x10 << LDST_SRCDST_SHIFT)
+ #define LDST_SRCDST_WORD_PKHA_B_SZ	(0x11 << LDST_SRCDST_SHIFT)
+@@ -360,6 +355,7 @@ struct sec4_sg_entry {
+ #define FIFOLD_TYPE_PK_N	(0x08 << FIFOLD_TYPE_SHIFT)
+ #define FIFOLD_TYPE_PK_A	(0x0c << FIFOLD_TYPE_SHIFT)
+ #define FIFOLD_TYPE_PK_B	(0x0d << FIFOLD_TYPE_SHIFT)
++#define FIFOLD_TYPE_IFIFO	(0x0f << FIFOLD_TYPE_SHIFT)
+ 
+ /* Other types. Need to OR in last/flush bits as desired */
+ #define FIFOLD_TYPE_MSG_MASK	(0x38 << FIFOLD_TYPE_SHIFT)
+@@ -400,7 +396,7 @@ struct sec4_sg_entry {
+ #define FIFOST_TYPE_PKHA_N	 (0x08 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_PKHA_A	 (0x0c << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_PKHA_B	 (0x0d << FIFOST_TYPE_SHIFT)
+-#define FIFOST_TYPE_AF_SBOX_JKEK (0x10 << FIFOST_TYPE_SHIFT)
++#define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_PKHA_E_JKEK	 (0x22 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_PKHA_E_TKEK	 (0x23 << FIFOST_TYPE_SHIFT)
+@@ -413,6 +409,7 @@ struct sec4_sg_entry {
+ #define FIFOST_TYPE_MESSAGE_DATA (0x30 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_RNGSTORE	 (0x34 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_RNGFIFO	 (0x35 << FIFOST_TYPE_SHIFT)
++#define FIFOST_TYPE_METADATA	 (0x3e << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_SKIP	 (0x3f << FIFOST_TYPE_SHIFT)
+ 
+ /*
+@@ -449,6 +446,18 @@ struct sec4_sg_entry {
+ #define OP_PCLID_DSAVERIFY	(0x16 << OP_PCLID_SHIFT)
+ #define OP_PCLID_RSAENC_PUBKEY  (0x18 << OP_PCLID_SHIFT)
+ #define OP_PCLID_RSADEC_PRVKEY  (0x19 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_MD5	(0x20 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_SHA1	(0x21 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_SHA224	(0x22 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_SHA256	(0x23 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_SHA384	(0x24 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_SHA512	(0x25 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_RIF_MD5	(0x60 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_RIF_SHA1	(0x61 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_RIF_SHA224	(0x62 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_RIF_SHA256	(0x63 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_RIF_SHA384	(0x64 << OP_PCLID_SHIFT)
++#define OP_PCLID_DKP_RIF_SHA512	(0x65 << OP_PCLID_SHIFT)
+ 
+ /* Assuming OP_TYPE = OP_TYPE_DECAP_PROTOCOL/ENCAP_PROTOCOL */
+ #define OP_PCLID_IPSEC		(0x01 << OP_PCLID_SHIFT)
+@@ -1098,6 +1107,22 @@ struct sec4_sg_entry {
+ /* MacSec protinfos */
+ #define OP_PCL_MACSEC				 0x0001
+ 
++/* Derived Key Protocol (DKP) Protinfo */
++#define OP_PCL_DKP_SRC_SHIFT	14
++#define OP_PCL_DKP_SRC_MASK	(3 << OP_PCL_DKP_SRC_SHIFT)
++#define OP_PCL_DKP_SRC_IMM	(0 << OP_PCL_DKP_SRC_SHIFT)
++#define OP_PCL_DKP_SRC_SEQ	(1 << OP_PCL_DKP_SRC_SHIFT)
++#define OP_PCL_DKP_SRC_PTR	(2 << OP_PCL_DKP_SRC_SHIFT)
++#define OP_PCL_DKP_SRC_SGF	(3 << OP_PCL_DKP_SRC_SHIFT)
++#define OP_PCL_DKP_DST_SHIFT	12
++#define OP_PCL_DKP_DST_MASK	(3 << OP_PCL_DKP_DST_SHIFT)
++#define OP_PCL_DKP_DST_IMM	(0 << OP_PCL_DKP_DST_SHIFT)
++#define OP_PCL_DKP_DST_SEQ	(1 << OP_PCL_DKP_DST_SHIFT)
++#define OP_PCL_DKP_DST_PTR	(2 << OP_PCL_DKP_DST_SHIFT)
++#define OP_PCL_DKP_DST_SGF	(3 << OP_PCL_DKP_DST_SHIFT)
++#define OP_PCL_DKP_KEY_SHIFT	0
++#define OP_PCL_DKP_KEY_MASK	(0xfff << OP_PCL_DKP_KEY_SHIFT)
++
+ /* PKI unidirectional protocol protinfo bits */
+ #define OP_PCL_PKPROT_TEST			 0x0008
+ #define OP_PCL_PKPROT_DECRYPT			 0x0004
+@@ -1107,8 +1132,8 @@ struct sec4_sg_entry {
+ /* For non-protocol/alg-only op commands */
+ #define OP_ALG_TYPE_SHIFT	24
+ #define OP_ALG_TYPE_MASK	(0x7 << OP_ALG_TYPE_SHIFT)
+-#define OP_ALG_TYPE_CLASS1	2
+-#define OP_ALG_TYPE_CLASS2	4
++#define OP_ALG_TYPE_CLASS1	(2 << OP_ALG_TYPE_SHIFT)
++#define OP_ALG_TYPE_CLASS2	(4 << OP_ALG_TYPE_SHIFT)
+ 
+ #define OP_ALG_ALGSEL_SHIFT	16
+ #define OP_ALG_ALGSEL_MASK	(0xff << OP_ALG_ALGSEL_SHIFT)
+@@ -1249,7 +1274,7 @@ struct sec4_sg_entry {
+ #define OP_ALG_PKMODE_MOD_PRIMALITY	0x00f
+ 
+ /* PKHA mode copy-memory functions */
+-#define OP_ALG_PKMODE_SRC_REG_SHIFT	13
++#define OP_ALG_PKMODE_SRC_REG_SHIFT	17
+ #define OP_ALG_PKMODE_SRC_REG_MASK	(7 << OP_ALG_PKMODE_SRC_REG_SHIFT)
+ #define OP_ALG_PKMODE_DST_REG_SHIFT	10
+ #define OP_ALG_PKMODE_DST_REG_MASK	(7 << OP_ALG_PKMODE_DST_REG_SHIFT)
+@@ -1445,10 +1470,11 @@ struct sec4_sg_entry {
+ #define MATH_SRC1_REG2		(0x02 << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_REG3		(0x03 << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_IMM		(0x04 << MATH_SRC1_SHIFT)
+-#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC0_SHIFT)
++#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_INFIFO	(0x0a << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_OUTFIFO	(0x0b << MATH_SRC1_SHIFT)
+ #define MATH_SRC1_ONE		(0x0c << MATH_SRC1_SHIFT)
++#define MATH_SRC1_ZERO		(0x0f << MATH_SRC1_SHIFT)
+ 
+ /* Destination selectors */
+ #define MATH_DEST_SHIFT		8
+@@ -1457,6 +1483,7 @@ struct sec4_sg_entry {
+ #define MATH_DEST_REG1		(0x01 << MATH_DEST_SHIFT)
+ #define MATH_DEST_REG2		(0x02 << MATH_DEST_SHIFT)
+ #define MATH_DEST_REG3		(0x03 << MATH_DEST_SHIFT)
++#define MATH_DEST_DPOVRD	(0x07 << MATH_DEST_SHIFT)
+ #define MATH_DEST_SEQINLEN	(0x08 << MATH_DEST_SHIFT)
+ #define MATH_DEST_SEQOUTLEN	(0x09 << MATH_DEST_SHIFT)
+ #define MATH_DEST_VARSEQINLEN	(0x0a << MATH_DEST_SHIFT)
+@@ -1629,4 +1656,31 @@ struct sec4_sg_entry {
+ /* Frame Descriptor Command for Replacement Job Descriptor */
+ #define FD_CMD_REPLACE_JOB_DESC				0x20000000
+ 
++/* CHA Control Register bits */
++#define CCTRL_RESET_CHA_ALL          0x1
++#define CCTRL_RESET_CHA_AESA         0x2
++#define CCTRL_RESET_CHA_DESA         0x4
++#define CCTRL_RESET_CHA_AFHA         0x8
++#define CCTRL_RESET_CHA_KFHA         0x10
++#define CCTRL_RESET_CHA_SF8A         0x20
++#define CCTRL_RESET_CHA_PKHA         0x40
++#define CCTRL_RESET_CHA_MDHA         0x80
++#define CCTRL_RESET_CHA_CRCA         0x100
++#define CCTRL_RESET_CHA_RNG          0x200
++#define CCTRL_RESET_CHA_SF9A         0x400
++#define CCTRL_RESET_CHA_ZUCE         0x800
++#define CCTRL_RESET_CHA_ZUCA         0x1000
++#define CCTRL_UNLOAD_PK_A0           0x10000
++#define CCTRL_UNLOAD_PK_A1           0x20000
++#define CCTRL_UNLOAD_PK_A2           0x40000
++#define CCTRL_UNLOAD_PK_A3           0x80000
++#define CCTRL_UNLOAD_PK_B0           0x100000
++#define CCTRL_UNLOAD_PK_B1           0x200000
++#define CCTRL_UNLOAD_PK_B2           0x400000
++#define CCTRL_UNLOAD_PK_B3           0x800000
++#define CCTRL_UNLOAD_PK_N            0x1000000
++#define CCTRL_UNLOAD_PK_A            0x4000000
++#define CCTRL_UNLOAD_PK_B            0x8000000
++#define CCTRL_UNLOAD_SBOX            0x10000000
++
+ #endif /* DESC_H */
+--- a/drivers/crypto/caam/desc_constr.h
++++ b/drivers/crypto/caam/desc_constr.h
+@@ -4,6 +4,9 @@
+  * Copyright 2008-2012 Freescale Semiconductor, Inc.
+  */
+ 
++#ifndef DESC_CONSTR_H
++#define DESC_CONSTR_H
++
+ #include "desc.h"
+ #include "regs.h"
+ 
+@@ -33,38 +36,39 @@
+ 
+ extern bool caam_little_end;
+ 
+-static inline int desc_len(u32 *desc)
++static inline int desc_len(u32 * const desc)
+ {
+ 	return caam32_to_cpu(*desc) & HDR_DESCLEN_MASK;
+ }
+ 
+-static inline int desc_bytes(void *desc)
++static inline int desc_bytes(void * const desc)
+ {
+ 	return desc_len(desc) * CAAM_CMD_SZ;
+ }
+ 
+-static inline u32 *desc_end(u32 *desc)
++static inline u32 *desc_end(u32 * const desc)
+ {
+ 	return desc + desc_len(desc);
+ }
+ 
+-static inline void *sh_desc_pdb(u32 *desc)
++static inline void *sh_desc_pdb(u32 * const desc)
+ {
+ 	return desc + 1;
+ }
+ 
+-static inline void init_desc(u32 *desc, u32 options)
++static inline void init_desc(u32 * const desc, u32 options)
+ {
+ 	*desc = cpu_to_caam32((options | HDR_ONE) + 1);
+ }
+ 
+-static inline void init_sh_desc(u32 *desc, u32 options)
++static inline void init_sh_desc(u32 * const desc, u32 options)
+ {
+ 	PRINT_POS;
+ 	init_desc(desc, CMD_SHARED_DESC_HDR | options);
+ }
+ 
+-static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
++static inline void init_sh_desc_pdb(u32 * const desc, u32 options,
++				    size_t pdb_bytes)
+ {
+ 	u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+ 
+@@ -72,19 +76,20 @@ static inline void init_sh_desc_pdb(u32
+ 		     options);
+ }
+ 
+-static inline void init_job_desc(u32 *desc, u32 options)
++static inline void init_job_desc(u32 * const desc, u32 options)
+ {
+ 	init_desc(desc, CMD_DESC_HDR | options);
+ }
+ 
+-static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
++static inline void init_job_desc_pdb(u32 * const desc, u32 options,
++				     size_t pdb_bytes)
+ {
+ 	u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+ 
+ 	init_job_desc(desc, (((pdb_len + 1) << HDR_START_IDX_SHIFT)) | options);
+ }
+ 
+-static inline void append_ptr(u32 *desc, dma_addr_t ptr)
++static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
+ {
+ 	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+ 
+@@ -94,8 +99,8 @@ static inline void append_ptr(u32 *desc,
+ 				CAAM_PTR_SZ / CAAM_CMD_SZ);
+ }
+ 
+-static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
+-					u32 options)
++static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
++					int len, u32 options)
+ {
+ 	PRINT_POS;
+ 	init_job_desc(desc, HDR_SHARED | options |
+@@ -103,7 +108,7 @@ static inline void init_job_desc_shared(
+ 	append_ptr(desc, ptr);
+ }
+ 
+-static inline void append_data(u32 *desc, void *data, int len)
++static inline void append_data(u32 * const desc, const void *data, int len)
+ {
+ 	u32 *offset = desc_end(desc);
+ 
+@@ -114,7 +119,7 @@ static inline void append_data(u32 *desc
+ 				(len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ);
+ }
+ 
+-static inline void append_cmd(u32 *desc, u32 command)
++static inline void append_cmd(u32 * const desc, u32 command)
+ {
+ 	u32 *cmd = desc_end(desc);
+ 
+@@ -125,7 +130,7 @@ static inline void append_cmd(u32 *desc,
+ 
+ #define append_u32 append_cmd
+ 
+-static inline void append_u64(u32 *desc, u64 data)
++static inline void append_u64(u32 * const desc, u64 data)
+ {
+ 	u32 *offset = desc_end(desc);
+ 
+@@ -142,14 +147,14 @@ static inline void append_u64(u32 *desc,
+ }
+ 
+ /* Write command without affecting header, and return pointer to next word */
+-static inline u32 *write_cmd(u32 *desc, u32 command)
++static inline u32 *write_cmd(u32 * const desc, u32 command)
+ {
+ 	*desc = cpu_to_caam32(command);
+ 
+ 	return desc + 1;
+ }
+ 
+-static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
++static inline void append_cmd_ptr(u32 * const desc, dma_addr_t ptr, int len,
+ 				  u32 command)
+ {
+ 	append_cmd(desc, command | len);
+@@ -157,7 +162,7 @@ static inline void append_cmd_ptr(u32 *d
+ }
+ 
+ /* Write length after pointer, rather than inside command */
+-static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
++static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
+ 					 unsigned int len, u32 command)
+ {
+ 	append_cmd(desc, command);
+@@ -166,7 +171,7 @@ static inline void append_cmd_ptr_extlen
+ 	append_cmd(desc, len);
+ }
+ 
+-static inline void append_cmd_data(u32 *desc, void *data, int len,
++static inline void append_cmd_data(u32 * const desc, const void *data, int len,
+ 				   u32 command)
+ {
+ 	append_cmd(desc, command | IMMEDIATE | len);
+@@ -174,7 +179,7 @@ static inline void append_cmd_data(u32 *
+ }
+ 
+ #define APPEND_CMD_RET(cmd, op) \
+-static inline u32 *append_##cmd(u32 *desc, u32 options) \
++static inline u32 *append_##cmd(u32 * const desc, u32 options) \
+ { \
+ 	u32 *cmd = desc_end(desc); \
+ 	PRINT_POS; \
+@@ -183,14 +188,15 @@ static inline u32 *append_##cmd(u32 *des
+ }
+ APPEND_CMD_RET(jump, JUMP)
+ APPEND_CMD_RET(move, MOVE)
++APPEND_CMD_RET(moveb, MOVEB)
+ 
+-static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
++static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd)
+ {
+ 	*jump_cmd = cpu_to_caam32(caam32_to_cpu(*jump_cmd) |
+ 				  (desc_len(desc) - (jump_cmd - desc)));
+ }
+ 
+-static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
++static inline void set_move_tgt_here(u32 * const desc, u32 *move_cmd)
+ {
+ 	u32 val = caam32_to_cpu(*move_cmd);
+ 
+@@ -200,7 +206,7 @@ static inline void set_move_tgt_here(u32
+ }
+ 
+ #define APPEND_CMD(cmd, op) \
+-static inline void append_##cmd(u32 *desc, u32 options) \
++static inline void append_##cmd(u32 * const desc, u32 options) \
+ { \
+ 	PRINT_POS; \
+ 	append_cmd(desc, CMD_##op | options); \
+@@ -208,7 +214,8 @@ static inline void append_##cmd(u32 *des
+ APPEND_CMD(operation, OPERATION)
+ 
+ #define APPEND_CMD_LEN(cmd, op) \
+-static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \
++static inline void append_##cmd(u32 * const desc, unsigned int len, \
++				u32 options) \
+ { \
+ 	PRINT_POS; \
+ 	append_cmd(desc, CMD_##op | len | options); \
+@@ -220,8 +227,8 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_L
+ APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
+ 
+ #define APPEND_CMD_PTR(cmd, op) \
+-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \
+-				u32 options) \
++static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
++				unsigned int len, u32 options) \
+ { \
+ 	PRINT_POS; \
+ 	append_cmd_ptr(desc, ptr, len, CMD_##op | options); \
+@@ -231,8 +238,8 @@ APPEND_CMD_PTR(load, LOAD)
+ APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
+ APPEND_CMD_PTR(fifo_store, FIFO_STORE)
+ 
+-static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
+-				u32 options)
++static inline void append_store(u32 * const desc, dma_addr_t ptr,
++				unsigned int len, u32 options)
+ {
+ 	u32 cmd_src;
+ 
+@@ -249,7 +256,8 @@ static inline void append_store(u32 *des
+ }
+ 
+ #define APPEND_SEQ_PTR_INTLEN(cmd, op) \
+-static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
++static inline void append_seq_##cmd##_ptr_intlen(u32 * const desc, \
++						 dma_addr_t ptr, \
+ 						 unsigned int len, \
+ 						 u32 options) \
+ { \
+@@ -263,7 +271,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
+ APPEND_SEQ_PTR_INTLEN(out, OUT)
+ 
+ #define APPEND_CMD_PTR_TO_IMM(cmd, op) \
+-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
++static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
+ 					 unsigned int len, u32 options) \
+ { \
+ 	PRINT_POS; \
+@@ -273,7 +281,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
+ APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
+ 
+ #define APPEND_CMD_PTR_EXTLEN(cmd, op) \
+-static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \
++static inline void append_##cmd##_extlen(u32 * const desc, dma_addr_t ptr, \
+ 					 unsigned int len, u32 options) \
+ { \
+ 	PRINT_POS; \
+@@ -287,7 +295,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_O
+  * the size of its type
+  */
+ #define APPEND_CMD_PTR_LEN(cmd, op, type) \
+-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \
++static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
+ 				type len, u32 options) \
+ { \
+ 	PRINT_POS; \
+@@ -304,7 +312,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_
+  * from length of immediate data provided, e.g., split keys
+  */
+ #define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
+-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
++static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
+ 					 unsigned int data_len, \
+ 					 unsigned int len, u32 options) \
+ { \
+@@ -315,7 +323,7 @@ static inline void append_##cmd##_as_imm
+ APPEND_CMD_PTR_TO_IMM2(key, KEY);
+ 
+ #define APPEND_CMD_RAW_IMM(cmd, op, type) \
+-static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \
++static inline void append_##cmd##_imm_##type(u32 * const desc, type immediate, \
+ 					     u32 options) \
+ { \
+ 	PRINT_POS; \
+@@ -426,3 +434,107 @@ do { \
+ 	APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data)
+ #define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \
+ 	APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data)
++
++/**
++ * struct alginfo - Container for algorithm details
++ * @algtype: algorithm selector; for valid values, see documentation of the
++ *           functions where it is used.
++ * @keylen: length of the provided algorithm key, in bytes
++ * @keylen_pad: padded length of the provided algorithm key, in bytes
++ * @key: address where algorithm key resides; virtual address if key_inline
++ *       is true, dma (bus) address if key_inline is false.
++ * @key_inline: true - key can be inlined in the descriptor; false - key is
++ *              referenced by the descriptor
++ */
++struct alginfo {
++	u32 algtype;
++	unsigned int keylen;
++	unsigned int keylen_pad;
++	union {
++		dma_addr_t key_dma;
++		const void *key_virt;
++	};
++	bool key_inline;
++};
++
++/**
++ * desc_inline_query() - Provide indications on which data items can be inlined
++ *                       and which shall be referenced in a shared descriptor.
++ * @sd_base_len: Shared descriptor base length - bytes consumed by the commands,
++ *               excluding the data items to be inlined (or corresponding
++ *               pointer if an item is not inlined). Each cnstr_* function that
++ *               generates descriptors should have a define mentioning
++ *               corresponding length.
++ * @jd_len: Maximum length of the job descriptor(s) that will be used
++ *          together with the shared descriptor.
++ * @data_len: Array of lengths of the data items trying to be inlined
++ * @inl_mask: 32bit mask with bit x = 1 if data item x can be inlined, 0
++ *            otherwise.
++ * @count: Number of data items (size of @data_len array); must be <= 32
++ *
++ * Return: 0 if data can be inlined / referenced, negative value if not. If 0,
++ *         check @inl_mask for details.
++ */
++static inline int desc_inline_query(unsigned int sd_base_len,
++				    unsigned int jd_len, unsigned int *data_len,
++				    u32 *inl_mask, unsigned int count)
++{
++	int rem_bytes = (int)(CAAM_DESC_BYTES_MAX - sd_base_len - jd_len);
++	unsigned int i;
++
++	*inl_mask = 0;
++	for (i = 0; (i < count) && (rem_bytes > 0); i++) {
++		if (rem_bytes - (int)(data_len[i] +
++			(count - i - 1) * CAAM_PTR_SZ) >= 0) {
++			rem_bytes -= data_len[i];
++			*inl_mask |= (1 << i);
++		} else {
++			rem_bytes -= CAAM_PTR_SZ;
++		}
++	}
++
++	return (rem_bytes >= 0) ? 0 : -1;
++}
++
++/**
++ * append_proto_dkp - Derived Key Protocol (DKP): key -> split key
++ * @desc: pointer to buffer used for descriptor construction
++ * @adata: pointer to authentication transform definitions.
++ *         keylen should be the length of initial key, while keylen_pad
++ *         the length of the derived (split) key.
++ *         Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1, SHA224,
++ *         SHA256, SHA384, SHA512}.
++ */
++static inline void append_proto_dkp(u32 * const desc, struct alginfo *adata)
++{
++	u32 protid;
++
++	/*
++	 * Quick & dirty translation from OP_ALG_ALGSEL_{MD5, SHA*}
++	 * to OP_PCLID_DKP_{MD5, SHA*}
++	 */
++	protid = (adata->algtype & OP_ALG_ALGSEL_SUBMASK) |
++		 (0x20 << OP_ALG_ALGSEL_SHIFT);
++
++	if (adata->key_inline) {
++		int words;
++
++		append_operation(desc, OP_TYPE_UNI_PROTOCOL | protid |
++				 OP_PCL_DKP_SRC_IMM | OP_PCL_DKP_DST_IMM |
++				 adata->keylen);
++		append_data(desc, adata->key_virt, adata->keylen);
++
++		/* Reserve space in descriptor buffer for the derived key */
++		words = (ALIGN(adata->keylen_pad, CAAM_CMD_SZ) -
++			 ALIGN(adata->keylen, CAAM_CMD_SZ)) / CAAM_CMD_SZ;
++		if (words)
++			(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + words);
++	} else {
++		append_operation(desc, OP_TYPE_UNI_PROTOCOL | protid |
++				 OP_PCL_DKP_SRC_PTR | OP_PCL_DKP_DST_PTR |
++				 adata->keylen);
++		append_ptr(desc, adata->key_dma);
++	}
++}
++
++#endif /* DESC_CONSTR_H */
+--- /dev/null
++++ b/drivers/crypto/caam/dpseci.c
+@@ -0,0 +1,858 @@
++/*
++ * Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the names of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/fsl/mc.h>
++#include "../../../drivers/staging/fsl-mc/include/dpopr.h"
++#include "dpseci.h"
++#include "dpseci_cmd.h"
++
++/**
++ * dpseci_open() - Open a control session for the specified object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @dpseci_id:	DPSECI unique ID
++ * @token:	Returned token; use in subsequent API calls
++ *
++ * This function can be used to open a control session for an already created
++ * object; an object may have been declared in the DPL or by calling the
++ * dpseci_create() function.
++ * This function returns a unique authentication token, associated with the
++ * specific object ID and the specific MC portal; this token must be used in all
++ * subsequent commands for this specific object.
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpseci_id,
++		u16 *token)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_open *cmd_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_OPEN,
++					  cmd_flags,
++					  0);
++	cmd_params = (struct dpseci_cmd_open *)cmd.params;
++	cmd_params->dpseci_id = cpu_to_le32(dpseci_id);
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	*token = mc_cmd_hdr_read_token(&cmd);
++
++	return 0;
++}
++
++/**
++ * dpseci_close() - Close the control session of the object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ *
++ * After this function is called, no further operations are allowed on the
++ * object without opening a new control session.
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLOSE,
++					  cmd_flags,
++					  token);
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_create() - Create the DPSECI object
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @dprc_token:	Parent container token; '0' for default container
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @cfg:	Configuration structure
++ * @obj_id:	returned object id
++ *
++ * Create the DPSECI object, allocate required resources and perform required
++ * initialization.
++ *
++ * The object can be created either by declaring it in the DPL file, or by
++ * calling this function.
++ *
++ * The function accepts an authentication token of a parent container that this
++ * object should be assigned to. The token can be '0' so the object will be
++ * assigned to the default container.
++ * The newly created object can be opened with the returned object id and using
++ * the container's associated tokens and MC portals.
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
++		  const struct dpseci_cfg *cfg, u32 *obj_id)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_create *cmd_params;
++	int i, err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CREATE,
++					  cmd_flags,
++					  dprc_token);
++	cmd_params = (struct dpseci_cmd_create *)cmd.params;
++	for (i = 0; i < 8; i++)
++		cmd_params->priorities[i] = cfg->priorities[i];
++	cmd_params->num_tx_queues = cfg->num_tx_queues;
++	cmd_params->num_rx_queues = cfg->num_rx_queues;
++	cmd_params->options = cpu_to_le32(cfg->options);
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	*obj_id = mc_cmd_read_object_id(&cmd);
++
++	return 0;
++}
++
++/**
++ * dpseci_destroy() - Destroy the DPSECI object and release all its resources
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @dprc_token: Parent container token; '0' for default container
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @object_id:	The object id; it must be a valid id within the container that
++ *		created this object
++ *
++ * The function accepts the authentication token of the parent container that
++ * created the object (not the one that currently owns the object). The object
++ * is searched within parent using the provided 'object_id'.
++ * All tokens to the object must be closed before calling destroy.
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
++		   u32 object_id)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_destroy *cmd_params;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DESTROY,
++					  cmd_flags,
++					  dprc_token);
++	cmd_params = (struct dpseci_cmd_destroy *)cmd.params;
++	cmd_params->object_id = cpu_to_le32(object_id);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_enable() - Enable the DPSECI, allow sending and receiving frames
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_ENABLE,
++					  cmd_flags,
++					  token);
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_disable() - Disable the DPSECI, stop sending and receiving frames
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_DISABLE,
++					  cmd_flags,
++					  token);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_is_enabled() - Check if the DPSECI is enabled.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @en:		Returns '1' if object is enabled; '0' otherwise
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++		      int *en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_rsp_is_enabled *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_IS_ENABLED,
++					  cmd_flags,
++					  token);
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_rsp_is_enabled *)cmd.params;
++	*en = le32_to_cpu(rsp_params->is_enabled);
++
++	return 0;
++}
++
++/**
++ * dpseci_reset() - Reset the DPSECI, returns the object to initial state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token)
++{
++	struct fsl_mc_command cmd = { 0 };
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_RESET,
++					  cmd_flags,
++					  token);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_get_irq_enable() - Get overall interrupt state
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Returned Interrupt state - enable = 1, disable = 0
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			  u8 irq_index, u8 *en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_irq_enable *cmd_params;
++	struct dpseci_rsp_get_irq_enable *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params;
++	cmd_params->irq_index = irq_index;
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_rsp_get_irq_enable *)cmd.params;
++	*en = rsp_params->enable_state;
++
++	return 0;
++}
++
++/**
++ * dpseci_set_irq_enable() - Set overall interrupt state.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @irq_index:	The interrupt index to configure
++ * @en:		Interrupt state - enable = 1, disable = 0
++ *
++ * Allows GPP software to control when interrupts are generated.
++ * Each interrupt can have up to 32 causes. The enable/disable control's the
++ * overall interrupt state. If the interrupt is disabled no causes will cause
++ * an interrupt.
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			  u8 irq_index, u8 en)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_irq_enable *cmd_params;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_ENABLE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_irq_enable *)cmd.params;
++	cmd_params->irq_index = irq_index;
++	cmd_params->enable_state = en;
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_get_irq_mask() - Get interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	Returned event mask to trigger interrupt
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently.
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 irq_index, u32 *mask)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_irq_mask *cmd_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params;
++	cmd_params->irq_index = irq_index;
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	*mask = le32_to_cpu(cmd_params->mask);
++
++	return 0;
++}
++
++/**
++ * dpseci_set_irq_mask() - Set interrupt mask.
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @irq_index:	The interrupt index to configure
++ * @mask:	event mask to trigger interrupt;
++ *		each bit:
++ *			0 = ignore event
++ *			1 = consider event for asserting IRQ
++ *
++ * Every interrupt can have up to 32 causes and the interrupt model supports
++ * masking/unmasking each cause independently
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 irq_index, u32 mask)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_irq_mask *cmd_params;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_IRQ_MASK,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_irq_mask *)cmd.params;
++	cmd_params->mask = cpu_to_le32(mask);
++	cmd_params->irq_index = irq_index;
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_get_irq_status() - Get the current status of any pending interrupts
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @irq_index:	The interrupt index to configure
++ * @status:	Returned interrupts status - one bit per cause:
++ *			0 = no interrupt pending
++ *			1 = interrupt pending
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			  u8 irq_index, u32 *status)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_irq_status *cmd_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(*status);
++	cmd_params->irq_index = irq_index;
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	*status = le32_to_cpu(cmd_params->status);
++
++	return 0;
++}
++
++/**
++ * dpseci_clear_irq_status() - Clear a pending interrupt's status
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @irq_index:	The interrupt index to configure
++ * @status:	bits to clear (W1C) - one bit per cause:
++ *			0 = don't change
++ *			1 = clear status bit
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			    u8 irq_index, u32 status)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_irq_status *cmd_params;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_CLEAR_IRQ_STATUS,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_irq_status *)cmd.params;
++	cmd_params->status = cpu_to_le32(status);
++	cmd_params->irq_index = irq_index;
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_get_attributes() - Retrieve DPSECI attributes
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @attr:	Returned object's attributes
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			  struct dpseci_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_rsp_get_attributes *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_ATTR,
++					  cmd_flags,
++					  token);
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_rsp_get_attributes *)cmd.params;
++	attr->id = le32_to_cpu(rsp_params->id);
++	attr->num_tx_queues = rsp_params->num_tx_queues;
++	attr->num_rx_queues = rsp_params->num_rx_queues;
++	attr->options = le32_to_cpu(rsp_params->options);
++
++	return 0;
++}
++
++/**
++ * dpseci_set_rx_queue() - Set Rx queue configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @queue:	Select the queue relative to number of priorities configured at
++ *		DPSECI creation; use DPSECI_ALL_QUEUES to configure all
++ *		Rx queues identically.
++ * @cfg:	Rx queue configuration
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 queue, const struct dpseci_rx_queue_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_queue *cmd_params;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_RX_QUEUE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_queue *)cmd.params;
++	cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
++	cmd_params->priority = cfg->dest_cfg.priority;
++	cmd_params->queue = queue;
++	cmd_params->dest_type = cfg->dest_cfg.dest_type;
++	cmd_params->user_ctx = cpu_to_le64(cfg->user_ctx);
++	cmd_params->options = cpu_to_le32(cfg->options);
++	cmd_params->order_preservation_en =
++		cpu_to_le32(cfg->order_preservation_en);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_get_rx_queue() - Retrieve Rx queue attributes
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @queue:	Select the queue relative to number of priorities configured at
++ *		DPSECI creation
++ * @attr:	Returned Rx queue attributes
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 queue, struct dpseci_rx_queue_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_queue *cmd_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_RX_QUEUE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_queue *)cmd.params;
++	cmd_params->queue = queue;
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	attr->dest_cfg.dest_id = le32_to_cpu(cmd_params->dest_id);
++	attr->dest_cfg.priority = cmd_params->priority;
++	attr->dest_cfg.dest_type = cmd_params->dest_type;
++	attr->user_ctx = le64_to_cpu(cmd_params->user_ctx);
++	attr->fqid = le32_to_cpu(cmd_params->fqid);
++	attr->order_preservation_en =
++		le32_to_cpu(cmd_params->order_preservation_en);
++
++	return 0;
++}
++
++/**
++ * dpseci_get_tx_queue() - Retrieve Tx queue attributes
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @queue:	Select the queue relative to number of priorities configured at
++ *		DPSECI creation
++ * @attr:	Returned Tx queue attributes
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 queue, struct dpseci_tx_queue_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_queue *cmd_params;
++	struct dpseci_rsp_get_tx_queue *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_TX_QUEUE,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_queue *)cmd.params;
++	cmd_params->queue = queue;
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_rsp_get_tx_queue *)cmd.params;
++	attr->fqid = le32_to_cpu(rsp_params->fqid);
++	attr->priority = rsp_params->priority;
++
++	return 0;
++}
++
++/**
++ * dpseci_get_sec_attr() - Retrieve SEC accelerator attributes
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @attr:	Returned SEC attributes
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			struct dpseci_sec_attr *attr)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_rsp_get_sec_attr *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_ATTR,
++					  cmd_flags,
++					  token);
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_rsp_get_sec_attr *)cmd.params;
++	attr->ip_id = le16_to_cpu(rsp_params->ip_id);
++	attr->major_rev = rsp_params->major_rev;
++	attr->minor_rev = rsp_params->minor_rev;
++	attr->era = rsp_params->era;
++	attr->deco_num = rsp_params->deco_num;
++	attr->zuc_auth_acc_num = rsp_params->zuc_auth_acc_num;
++	attr->zuc_enc_acc_num = rsp_params->zuc_enc_acc_num;
++	attr->snow_f8_acc_num = rsp_params->snow_f8_acc_num;
++	attr->snow_f9_acc_num = rsp_params->snow_f9_acc_num;
++	attr->crc_acc_num = rsp_params->crc_acc_num;
++	attr->pk_acc_num = rsp_params->pk_acc_num;
++	attr->kasumi_acc_num = rsp_params->kasumi_acc_num;
++	attr->rng_acc_num = rsp_params->rng_acc_num;
++	attr->md_acc_num = rsp_params->md_acc_num;
++	attr->arc4_acc_num = rsp_params->arc4_acc_num;
++	attr->des_acc_num = rsp_params->des_acc_num;
++	attr->aes_acc_num = rsp_params->aes_acc_num;
++
++	return 0;
++}
++
++/**
++ * dpseci_get_sec_counters() - Retrieve SEC accelerator counters
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @counters:	Returned SEC counters
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			    struct dpseci_sec_counters *counters)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_rsp_get_sec_counters *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_SEC_COUNTERS,
++					  cmd_flags,
++					  token);
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_rsp_get_sec_counters *)cmd.params;
++	counters->dequeued_requests =
++		le64_to_cpu(rsp_params->dequeued_requests);
++	counters->ob_enc_requests = le64_to_cpu(rsp_params->ob_enc_requests);
++	counters->ib_dec_requests = le64_to_cpu(rsp_params->ib_dec_requests);
++	counters->ob_enc_bytes = le64_to_cpu(rsp_params->ob_enc_bytes);
++	counters->ob_prot_bytes = le64_to_cpu(rsp_params->ob_prot_bytes);
++	counters->ib_dec_bytes = le64_to_cpu(rsp_params->ib_dec_bytes);
++	counters->ib_valid_bytes = le64_to_cpu(rsp_params->ib_valid_bytes);
++
++	return 0;
++}
++
++/**
++ * dpseci_get_api_version() - Get Data Path SEC Interface API version
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @major_ver:	Major version of data path sec API
++ * @minor_ver:	Minor version of data path sec API
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
++			   u16 *major_ver, u16 *minor_ver)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_rsp_get_api_version *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_API_VERSION,
++					  cmd_flags, 0);
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_rsp_get_api_version *)cmd.params;
++	*major_ver = le16_to_cpu(rsp_params->major);
++	*minor_ver = le16_to_cpu(rsp_params->minor);
++
++	return 0;
++}
++
++/**
++ * dpseci_set_opr() - Set Order Restoration configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @index:	The queue index
++ * @options:	Configuration mode options; can be OPR_OPT_CREATE or
++ *		OPR_OPT_RETIRE
++ * @cfg:	Configuration options for the OPR
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
++		   u8 options, struct opr_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_opr *cmd_params;
++
++	cmd.header = mc_encode_cmd_header(
++			DPSECI_CMDID_SET_OPR,
++			cmd_flags,
++			token);
++	cmd_params = (struct dpseci_cmd_opr *)cmd.params;
++	cmd_params->index = index;
++	cmd_params->options = options;
++	cmd_params->oloe = cfg->oloe;
++	cmd_params->oeane = cfg->oeane;
++	cmd_params->olws = cfg->olws;
++	cmd_params->oa = cfg->oa;
++	cmd_params->oprrws = cfg->oprrws;
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_get_opr() - Retrieve Order Restoration config and query
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @index:	The queue index
++ * @cfg:	Returned OPR configuration
++ * @qry:	Returned OPR query
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
++		   struct opr_cfg *cfg, struct opr_qry *qry)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_opr *cmd_params;
++	struct dpseci_rsp_get_opr *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_OPR,
++					  cmd_flags,
++					  token);
++	cmd_params = (struct dpseci_cmd_opr *)cmd.params;
++	cmd_params->index = index;
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_rsp_get_opr *)cmd.params;
++	qry->rip = dpseci_get_field(rsp_params->rip_enable, OPR_RIP);
++	qry->enable = dpseci_get_field(rsp_params->rip_enable, OPR_ENABLE);
++	cfg->oloe = rsp_params->oloe;
++	cfg->oeane = rsp_params->oeane;
++	cfg->olws = rsp_params->olws;
++	cfg->oa = rsp_params->oa;
++	cfg->oprrws = rsp_params->oprrws;
++	qry->nesn = le16_to_cpu(rsp_params->nesn);
++	qry->ndsn = le16_to_cpu(rsp_params->ndsn);
++	qry->ea_tseq = le16_to_cpu(rsp_params->ea_tseq);
++	qry->tseq_nlis = dpseci_get_field(rsp_params->tseq_nlis, OPR_TSEQ_NLIS);
++	qry->ea_hseq = le16_to_cpu(rsp_params->ea_hseq);
++	qry->hseq_nlis = dpseci_get_field(rsp_params->tseq_nlis, OPR_HSEQ_NLIS);
++	qry->ea_hptr = le16_to_cpu(rsp_params->ea_hptr);
++	qry->ea_tptr = le16_to_cpu(rsp_params->ea_tptr);
++	qry->opr_vid = le16_to_cpu(rsp_params->opr_vid);
++	qry->opr_id = le16_to_cpu(rsp_params->opr_id);
++
++	return 0;
++}
++
++/**
++ * dpseci_set_congestion_notification() - Set congestion group
++ *	notification configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @cfg:	congestion notification configuration
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_set_congestion_notification(struct fsl_mc_io *mc_io, u32 cmd_flags,
++	u16 token, const struct dpseci_congestion_notification_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_congestion_notification *cmd_params;
++
++	cmd.header = mc_encode_cmd_header(
++			DPSECI_CMDID_SET_CONGESTION_NOTIFICATION,
++			cmd_flags,
++			token);
++	cmd_params = (struct dpseci_cmd_congestion_notification *)cmd.params;
++	cmd_params->dest_id = cpu_to_le32(cfg->dest_cfg.dest_id);
++	cmd_params->notification_mode = cpu_to_le16(cfg->notification_mode);
++	cmd_params->priority = cfg->dest_cfg.priority;
++	dpseci_set_field(cmd_params->options, CGN_DEST_TYPE,
++			 cfg->dest_cfg.dest_type);
++	dpseci_set_field(cmd_params->options, CGN_UNITS, cfg->units);
++	cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
++	cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
++	cmd_params->threshold_entry = cpu_to_le32(cfg->threshold_entry);
++	cmd_params->threshold_exit = cpu_to_le32(cfg->threshold_exit);
++
++	return mc_send_command(mc_io, &cmd);
++}
++
++/**
++ * dpseci_get_congestion_notification() - Get congestion group notification
++ *	configuration
++ * @mc_io:	Pointer to MC portal's I/O object
++ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
++ * @token:	Token of DPSECI object
++ * @cfg:	congestion notification configuration
++ *
++ * Return:	'0' on success, error code otherwise
++ */
++int dpseci_get_congestion_notification(struct fsl_mc_io *mc_io, u32 cmd_flags,
++	u16 token, struct dpseci_congestion_notification_cfg *cfg)
++{
++	struct fsl_mc_command cmd = { 0 };
++	struct dpseci_cmd_congestion_notification *rsp_params;
++	int err;
++
++	cmd.header = mc_encode_cmd_header(
++			DPSECI_CMDID_GET_CONGESTION_NOTIFICATION,
++			cmd_flags,
++			token);
++	err = mc_send_command(mc_io, &cmd);
++	if (err)
++		return err;
++
++	rsp_params = (struct dpseci_cmd_congestion_notification *)cmd.params;
++	cfg->dest_cfg.dest_id = le32_to_cpu(rsp_params->dest_id);
++	cfg->notification_mode = le16_to_cpu(rsp_params->notification_mode);
++	cfg->dest_cfg.priority = rsp_params->priority;
++	cfg->dest_cfg.dest_type = dpseci_get_field(rsp_params->options,
++						   CGN_DEST_TYPE);
++	cfg->units = dpseci_get_field(rsp_params->options, CGN_UNITS);
++	cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
++	cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
++	cfg->threshold_entry = le32_to_cpu(rsp_params->threshold_entry);
++	cfg->threshold_exit = le32_to_cpu(rsp_params->threshold_exit);
++
++	return 0;
++}
+--- /dev/null
++++ b/drivers/crypto/caam/dpseci.h
+@@ -0,0 +1,395 @@
++/*
++ * Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the names of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++#ifndef _DPSECI_H_
++#define _DPSECI_H_
++
++/*
++ * Data Path SEC Interface API
++ * Contains initialization APIs and runtime control APIs for DPSECI
++ */
++
++struct fsl_mc_io;
++struct opr_cfg;
++struct opr_qry;
++
++/**
++ * General DPSECI macros
++ */
++
++/**
++ * Maximum number of Tx/Rx priorities per DPSECI object
++ */
++#define DPSECI_PRIO_NUM		8
++
++/**
++ * All queues considered; see dpseci_set_rx_queue()
++ */
++#define DPSECI_ALL_QUEUES	(u8)(-1)
++
++int dpseci_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpseci_id,
++		u16 *token);
++
++int dpseci_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
++
++/**
++ * Enable the Congestion Group support
++ */
++#define DPSECI_OPT_HAS_CG		0x000020
++
++/**
++ * Enable the Order Restoration support
++ */
++#define DPSECI_OPT_HAS_OPR		0x000040
++
++/**
++ * Order Point Records are shared for the entire DPSECI
++ */
++#define DPSECI_OPT_OPR_SHARED		0x000080
++
++/**
++ * struct dpseci_cfg - Structure representing DPSECI configuration
++ * @options: Any combination of the following options:
++ *		DPSECI_OPT_HAS_CG
++ *		DPSECI_OPT_HAS_OPR
++ *		DPSECI_OPT_OPR_SHARED
++ * @num_tx_queues: num of queues towards the SEC
++ * @num_rx_queues: num of queues back from the SEC
++ * @priorities: Priorities for the SEC hardware processing;
++ *		each place in the array is the priority of the tx queue
++ *		towards the SEC;
++ *		valid priorities are configured with values 1-8;
++ */
++struct dpseci_cfg {
++	u32 options;
++	u8 num_tx_queues;
++	u8 num_rx_queues;
++	u8 priorities[DPSECI_PRIO_NUM];
++};
++
++int dpseci_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
++		  const struct dpseci_cfg *cfg, u32 *obj_id);
++
++int dpseci_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
++		   u32 object_id);
++
++int dpseci_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
++
++int dpseci_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
++
++int dpseci_is_enabled(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++		      int *en);
++
++int dpseci_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
++
++int dpseci_get_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			  u8 irq_index, u8 *en);
++
++int dpseci_set_irq_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			  u8 irq_index, u8 en);
++
++int dpseci_get_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 irq_index, u32 *mask);
++
++int dpseci_set_irq_mask(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 irq_index, u32 mask);
++
++int dpseci_get_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			  u8 irq_index, u32 *status);
++
++int dpseci_clear_irq_status(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			    u8 irq_index, u32 status);
++
++/**
++ * struct dpseci_attr - Structure representing DPSECI attributes
++ * @id: DPSECI object ID
++ * @num_tx_queues: number of queues towards the SEC
++ * @num_rx_queues: number of queues back from the SEC
++ * @options: any combination of the following options:
++ *		DPSECI_OPT_HAS_CG
++ *		DPSECI_OPT_HAS_OPR
++ *		DPSECI_OPT_OPR_SHARED
++ */
++struct dpseci_attr {
++	int id;
++	u8 num_tx_queues;
++	u8 num_rx_queues;
++	u32 options;
++};
++
++int dpseci_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			  struct dpseci_attr *attr);
++
++/**
++ * enum dpseci_dest - DPSECI destination types
++ * @DPSECI_DEST_NONE: Unassigned destination; The queue is set in parked mode
++ *	and does not generate FQDAN notifications; user is expected to dequeue
++ *	from the queue based on polling or other user-defined method
++ * @DPSECI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
++ *	notifications to the specified DPIO; user is expected to dequeue from
++ *	the queue only after notification is received
++ * @DPSECI_DEST_DPCON: The queue is set in schedule mode and does not generate
++ *	FQDAN notifications, but is connected to the specified DPCON object;
++ *	user is expected to dequeue from the DPCON channel
++ */
++enum dpseci_dest {
++	DPSECI_DEST_NONE = 0,
++	DPSECI_DEST_DPIO,
++	DPSECI_DEST_DPCON
++};
++
++/**
++ * struct dpseci_dest_cfg - Structure representing DPSECI destination parameters
++ * @dest_type: Destination type
++ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
++ * @priority: Priority selection within the DPIO or DPCON channel; valid values
++ *	are 0-1 or 0-7, depending on the number of priorities in that channel;
++ *	not relevant for 'DPSECI_DEST_NONE' option
++ */
++struct dpseci_dest_cfg {
++	enum dpseci_dest dest_type;
++	int dest_id;
++	u8 priority;
++};
++
++/**
++ * DPSECI queue modification options
++ */
++
++/**
++ * Select to modify the user's context associated with the queue
++ */
++#define DPSECI_QUEUE_OPT_USER_CTX		0x00000001
++
++/**
++ * Select to modify the queue's destination
++ */
++#define DPSECI_QUEUE_OPT_DEST			0x00000002
++
++/**
++ * Select to modify the queue's order preservation
++ */
++#define DPSECI_QUEUE_OPT_ORDER_PRESERVATION	0x00000004
++
++/**
++ * struct dpseci_rx_queue_cfg - DPSECI RX queue configuration
++ * @options: Flags representing the suggested modifications to the queue;
++ *	Use any combination of 'DPSECI_QUEUE_OPT_<X>' flags
++ * @order_preservation_en: order preservation configuration for the rx queue
++ * valid only if 'DPSECI_QUEUE_OPT_ORDER_PRESERVATION' is contained in 'options'
++ * @user_ctx: User context value provided in the frame descriptor of each
++ *	dequeued frame;	valid only if 'DPSECI_QUEUE_OPT_USER_CTX' is contained
++ *	in 'options'
++ * @dest_cfg: Queue destination parameters; valid only if
++ *	'DPSECI_QUEUE_OPT_DEST' is contained in 'options'
++ */
++struct dpseci_rx_queue_cfg {
++	u32 options;
++	int order_preservation_en;
++	u64 user_ctx;
++	struct dpseci_dest_cfg dest_cfg;
++};
++
++int dpseci_set_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 queue, const struct dpseci_rx_queue_cfg *cfg);
++
++/**
++ * struct dpseci_rx_queue_attr - Structure representing attributes of Rx queues
++ * @user_ctx: User context value provided in the frame descriptor of each
++ *	dequeued frame
++ * @order_preservation_en: Status of the order preservation configuration on the
++ *	queue
++ * @dest_cfg: Queue destination configuration
++ * @fqid: Virtual FQID value to be used for dequeue operations
++ */
++struct dpseci_rx_queue_attr {
++	u64 user_ctx;
++	int order_preservation_en;
++	struct dpseci_dest_cfg dest_cfg;
++	u32 fqid;
++};
++
++int dpseci_get_rx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 queue, struct dpseci_rx_queue_attr *attr);
++
++/**
++ * struct dpseci_tx_queue_attr - Structure representing attributes of Tx queues
++ * @fqid: Virtual FQID to be used for sending frames to SEC hardware
++ * @priority: SEC hardware processing priority for the queue
++ */
++struct dpseci_tx_queue_attr {
++	u32 fqid;
++	u8 priority;
++};
++
++int dpseci_get_tx_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			u8 queue, struct dpseci_tx_queue_attr *attr);
++
++/**
++ * struct dpseci_sec_attr - Structure representing attributes of the SEC
++ *	hardware accelerator
++ * @ip_id: ID for SEC
++ * @major_rev: Major revision number for SEC
++ * @minor_rev: Minor revision number for SEC
++ * @era: SEC Era
++ * @deco_num: The number of copies of the DECO that are implemented in this
++ *	version of SEC
++ * @zuc_auth_acc_num: The number of copies of ZUCA that are implemented in this
++ *	version of SEC
++ * @zuc_enc_acc_num: The number of copies of ZUCE that are implemented in this
++ *	version of SEC
++ * @snow_f8_acc_num: The number of copies of the SNOW-f8 module that are
++ *	implemented in this version of SEC
++ * @snow_f9_acc_num: The number of copies of the SNOW-f9 module that are
++ *	implemented in this version of SEC
++ * @crc_acc_num: The number of copies of the CRC module that are implemented in
++ *	this version of SEC
++ * @pk_acc_num:  The number of copies of the Public Key module that are
++ *	implemented in this version of SEC
++ * @kasumi_acc_num: The number of copies of the Kasumi module that are
++ *	implemented in this version of SEC
++ * @rng_acc_num: The number of copies of the Random Number Generator that are
++ *	implemented in this version of SEC
++ * @md_acc_num: The number of copies of the MDHA (Hashing module) that are
++ *	implemented in this version of SEC
++ * @arc4_acc_num: The number of copies of the ARC4 module that are implemented
++ *	in this version of SEC
++ * @des_acc_num: The number of copies of the DES module that are implemented in
++ *	this version of SEC
++ * @aes_acc_num: The number of copies of the AES module that are implemented in
++ *	this version of SEC
++ **/
++struct dpseci_sec_attr {
++	u16 ip_id;
++	u8 major_rev;
++	u8 minor_rev;
++	u8 era;
++	u8 deco_num;
++	u8 zuc_auth_acc_num;
++	u8 zuc_enc_acc_num;
++	u8 snow_f8_acc_num;
++	u8 snow_f9_acc_num;
++	u8 crc_acc_num;
++	u8 pk_acc_num;
++	u8 kasumi_acc_num;
++	u8 rng_acc_num;
++	u8 md_acc_num;
++	u8 arc4_acc_num;
++	u8 des_acc_num;
++	u8 aes_acc_num;
++};
++
++int dpseci_get_sec_attr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			struct dpseci_sec_attr *attr);
++
++/**
++ * struct dpseci_sec_counters - Structure representing global SEC counters and
++ *				not per dpseci counters
++ * @dequeued_requests:	Number of Requests Dequeued
++ * @ob_enc_requests:	Number of Outbound Encrypt Requests
++ * @ib_dec_requests:	Number of Inbound Decrypt Requests
++ * @ob_enc_bytes:	Number of Outbound Bytes Encrypted
++ * @ob_prot_bytes:	Number of Outbound Bytes Protected
++ * @ib_dec_bytes:	Number of Inbound Bytes Decrypted
++ * @ib_valid_bytes:	Number of Inbound Bytes Validated
++ */
++struct dpseci_sec_counters {
++	u64 dequeued_requests;
++	u64 ob_enc_requests;
++	u64 ib_dec_requests;
++	u64 ob_enc_bytes;
++	u64 ob_prot_bytes;
++	u64 ib_dec_bytes;
++	u64 ib_valid_bytes;
++};
++
++int dpseci_get_sec_counters(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
++			    struct dpseci_sec_counters *counters);
++
++int dpseci_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
++			   u16 *major_ver, u16 *minor_ver);
++
++int dpseci_set_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
++		   u8 options, struct opr_cfg *cfg);
++
++int dpseci_get_opr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, u8 index,
++		   struct opr_cfg *cfg, struct opr_qry *qry);
++
++/**
++ * enum dpseci_congestion_unit - DPSECI congestion units
++ * @DPSECI_CONGESTION_UNIT_BYTES: bytes units
++ * @DPSECI_CONGESTION_UNIT_FRAMES: frames units
++ */
++enum dpseci_congestion_unit {
++	DPSECI_CONGESTION_UNIT_BYTES = 0,
++	DPSECI_CONGESTION_UNIT_FRAMES
++};
++
++#define DPSECI_CGN_MODE_WRITE_MEM_ON_ENTER		0x00000001
++#define DPSECI_CGN_MODE_WRITE_MEM_ON_EXIT		0x00000002
++#define DPSECI_CGN_MODE_COHERENT_WRITE			0x00000004
++#define DPSECI_CGN_MODE_NOTIFY_DEST_ON_ENTER		0x00000008
++#define DPSECI_CGN_MODE_NOTIFY_DEST_ON_EXIT		0x00000010
++#define DPSECI_CGN_MODE_INTR_COALESCING_DISABLED	0x00000020
++
++/**
++ * struct dpseci_congestion_notification_cfg - congestion notification
++ *	configuration
++ * @units: units type
++ * @threshold_entry: above this threshold we enter a congestion state.
++ *	set it to '0' to disable it
++ * @threshold_exit: below this threshold we exit the congestion state.
++ * @message_ctx: The context that will be part of the CSCN message
++ * @message_iova: I/O virtual address (must be in DMA-able memory),
++ *	must be 16B aligned;
++ * @dest_cfg: CSCN can be send to either DPIO or DPCON WQ channel
++ * @notification_mode: Mask of available options; use 'DPSECI_CGN_MODE_<X>'
++ *	values
++ */
++struct dpseci_congestion_notification_cfg {
++	enum dpseci_congestion_unit units;
++	u32 threshold_entry;
++	u32 threshold_exit;
++	u64 message_ctx;
++	u64 message_iova;
++	struct dpseci_dest_cfg dest_cfg;
++	u16 notification_mode;
++};
++
++int dpseci_set_congestion_notification(struct fsl_mc_io *mc_io, u32 cmd_flags,
++	u16 token, const struct dpseci_congestion_notification_cfg *cfg);
++
++int dpseci_get_congestion_notification(struct fsl_mc_io *mc_io, u32 cmd_flags,
++	u16 token, struct dpseci_congestion_notification_cfg *cfg);
++
++#endif /* _DPSECI_H_ */
+--- /dev/null
++++ b/drivers/crypto/caam/dpseci_cmd.h
+@@ -0,0 +1,261 @@
++/*
++ * Copyright 2013-2016 Freescale Semiconductor Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the names of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef _DPSECI_CMD_H_
++#define _DPSECI_CMD_H_
++
++/* DPSECI Version */
++#define DPSECI_VER_MAJOR				5
++#define DPSECI_VER_MINOR				1
++
++#define DPSECI_VER(maj, min)	(((maj) << 16) | (min))
++#define DPSECI_VERSION		DPSECI_VER(DPSECI_VER_MAJOR, DPSECI_VER_MINOR)
++
++/* Command IDs */
++
++#define DPSECI_CMDID_CLOSE                              0x8001
++#define DPSECI_CMDID_OPEN                               0x8091
++#define DPSECI_CMDID_CREATE                             0x9092
++#define DPSECI_CMDID_DESTROY                            0x9891
++#define DPSECI_CMDID_GET_API_VERSION                    0xa091
++
++#define DPSECI_CMDID_ENABLE                             0x0021
++#define DPSECI_CMDID_DISABLE                            0x0031
++#define DPSECI_CMDID_GET_ATTR                           0x0041
++#define DPSECI_CMDID_RESET                              0x0051
++#define DPSECI_CMDID_IS_ENABLED                         0x0061
++
++#define DPSECI_CMDID_SET_IRQ_ENABLE                     0x0121
++#define DPSECI_CMDID_GET_IRQ_ENABLE                     0x0131
++#define DPSECI_CMDID_SET_IRQ_MASK                       0x0141
++#define DPSECI_CMDID_GET_IRQ_MASK                       0x0151
++#define DPSECI_CMDID_GET_IRQ_STATUS                     0x0161
++#define DPSECI_CMDID_CLEAR_IRQ_STATUS                   0x0171
++
++#define DPSECI_CMDID_SET_RX_QUEUE                       0x1941
++#define DPSECI_CMDID_GET_RX_QUEUE                       0x1961
++#define DPSECI_CMDID_GET_TX_QUEUE                       0x1971
++#define DPSECI_CMDID_GET_SEC_ATTR                       0x1981
++#define DPSECI_CMDID_GET_SEC_COUNTERS                   0x1991
++#define DPSECI_CMDID_SET_OPR				0x19A1
++#define DPSECI_CMDID_GET_OPR				0x19B1
++
++#define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION	0x1701
++#define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION	0x1711
++
++/* Macros for accessing command fields smaller than 1 byte */
++#define DPSECI_MASK(field)	\
++	GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1,	\
++		DPSECI_##field##_SHIFT)
++
++#define dpseci_set_field(var, field, val)	\
++	((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field)))
++
++#define dpseci_get_field(var, field)	\
++	(((var) & DPSECI_MASK(field)) >> DPSECI_##field##_SHIFT)
++
++struct dpseci_cmd_open {
++	__le32 dpseci_id;
++};
++
++struct dpseci_cmd_create {
++	u8 priorities[8];
++	u8 num_tx_queues;
++	u8 num_rx_queues;
++	__le16 pad;
++	__le32 options;
++};
++
++struct dpseci_cmd_destroy {
++	__le32 object_id;
++};
++
++struct dpseci_rsp_is_enabled {
++	__le32 is_enabled;
++};
++
++struct dpseci_cmd_irq_enable {
++	u8 enable_state;
++	u8 pad[3];
++	u8 irq_index;
++};
++
++struct dpseci_rsp_get_irq_enable {
++	u8 enable_state;
++};
++
++struct dpseci_cmd_irq_mask {
++	__le32 mask;
++	u8 irq_index;
++};
++
++struct dpseci_cmd_irq_status {
++	__le32 status;
++	u8 irq_index;
++};
++
++struct dpseci_rsp_get_attributes {
++	__le32 id;
++	__le32 pad0;
++	u8 num_tx_queues;
++	u8 num_rx_queues;
++	u8 pad1[6];
++	__le32 options;
++};
++
++struct dpseci_cmd_queue {
++	__le32 dest_id;
++	u8 priority;
++	u8 queue;
++	u8 dest_type;
++	u8 pad;
++	__le64 user_ctx;
++	union {
++		__le32 options;
++		__le32 fqid;
++	};
++	__le32 order_preservation_en;
++};
++
++struct dpseci_rsp_get_tx_queue {
++	__le32 pad;
++	__le32 fqid;
++	u8 priority;
++};
++
++struct dpseci_rsp_get_sec_attr {
++	__le16 ip_id;
++	u8 major_rev;
++	u8 minor_rev;
++	u8 era;
++	u8 pad0[3];
++	u8 deco_num;
++	u8 zuc_auth_acc_num;
++	u8 zuc_enc_acc_num;
++	u8 pad1;
++	u8 snow_f8_acc_num;
++	u8 snow_f9_acc_num;
++	u8 crc_acc_num;
++	u8 pad2;
++	u8 pk_acc_num;
++	u8 kasumi_acc_num;
++	u8 rng_acc_num;
++	u8 pad3;
++	u8 md_acc_num;
++	u8 arc4_acc_num;
++	u8 des_acc_num;
++	u8 aes_acc_num;
++};
++
++struct dpseci_rsp_get_sec_counters {
++	__le64 dequeued_requests;
++	__le64 ob_enc_requests;
++	__le64 ib_dec_requests;
++	__le64 ob_enc_bytes;
++	__le64 ob_prot_bytes;
++	__le64 ib_dec_bytes;
++	__le64 ib_valid_bytes;
++};
++
++struct dpseci_rsp_get_api_version {
++	__le16 major;
++	__le16 minor;
++};
++
++struct dpseci_cmd_opr {
++	__le16 pad;
++	u8 index;
++	u8 options;
++	u8 pad1[7];
++	u8 oloe;
++	u8 oeane;
++	u8 olws;
++	u8 oa;
++	u8 oprrws;
++};
++
++#define DPSECI_OPR_RIP_SHIFT		0
++#define DPSECI_OPR_RIP_SIZE		1
++#define DPSECI_OPR_ENABLE_SHIFT		1
++#define DPSECI_OPR_ENABLE_SIZE		1
++#define DPSECI_OPR_TSEQ_NLIS_SHIFT	1
++#define DPSECI_OPR_TSEQ_NLIS_SIZE	1
++#define DPSECI_OPR_HSEQ_NLIS_SHIFT	1
++#define DPSECI_OPR_HSEQ_NLIS_SIZE	1
++
++struct dpseci_rsp_get_opr {
++	__le64 pad;
++	u8 rip_enable;
++	u8 pad0[2];
++	u8 oloe;
++	u8 oeane;
++	u8 olws;
++	u8 oa;
++	u8 oprrws;
++	__le16 nesn;
++	__le16 pad1;
++	__le16 ndsn;
++	__le16 pad2;
++	__le16 ea_tseq;
++	u8 tseq_nlis;
++	u8 pad3;
++	__le16 ea_hseq;
++	u8 hseq_nlis;
++	u8 pad4;
++	__le16 ea_hptr;
++	__le16 pad5;
++	__le16 ea_tptr;
++	__le16 pad6;
++	__le16 opr_vid;
++	__le16 pad7;
++	__le16 opr_id;
++};
++
++#define DPSECI_CGN_DEST_TYPE_SHIFT	0
++#define DPSECI_CGN_DEST_TYPE_SIZE	4
++#define DPSECI_CGN_UNITS_SHIFT		4
++#define DPSECI_CGN_UNITS_SIZE		2
++
++struct dpseci_cmd_congestion_notification {
++	__le32 dest_id;
++	__le16 notification_mode;
++	u8 priority;
++	u8 options;
++	__le64 message_iova;
++	__le64 message_ctx;
++	__le32 threshold_entry;
++	__le32 threshold_exit;
++};
++
++#endif /* _DPSECI_CMD_H_ */
+--- a/drivers/crypto/caam/error.c
++++ b/drivers/crypto/caam/error.c
+@@ -6,11 +6,54 @@
+ 
+ #include "compat.h"
+ #include "regs.h"
+-#include "intern.h"
+ #include "desc.h"
+-#include "jr.h"
+ #include "error.h"
+ 
++#ifdef DEBUG
++
++#include <linux/highmem.h>
++
++void caam_dump_sg(const char *level, const char *prefix_str, int prefix_type,
++		  int rowsize, int groupsize, struct scatterlist *sg,
++		  size_t tlen, bool ascii)
++{
++	struct scatterlist *it;
++	void *it_page;
++	size_t len;
++	void *buf;
++
++	for (it = sg; it && tlen > 0 ; it = sg_next(sg)) {
++		/*
++		 * make sure the scatterlist's page
++		 * has a valid virtual memory mapping
++		 */
++		it_page = kmap_atomic(sg_page(it));
++		if (unlikely(!it_page)) {
++			pr_err("caam_dump_sg: kmap failed\n");
++			return;
++		}
++
++		buf = it_page + it->offset;
++		len = min_t(size_t, tlen, it->length);
++		print_hex_dump(level, prefix_str, prefix_type, rowsize,
++			       groupsize, buf, len, ascii);
++		tlen -= len;
++
++		kunmap_atomic(it_page);
++	}
++}
++
++#else
++
++void caam_dump_sg(const char *level, const char *prefix_str, int prefix_type,
++		  int rowsize, int groupsize, struct scatterlist *sg,
++		  size_t tlen, bool ascii)
++{}
++
++#endif
++
++EXPORT_SYMBOL(caam_dump_sg);
++
+ static const struct {
+ 	u8 value;
+ 	const char *error_text;
+@@ -69,6 +112,54 @@ static const struct {
+ 	{ 0xF1, "3GPP HFN matches or exceeds the Threshold" },
+ };
+ 
++static const struct {
++	u8 value;
++	const char *error_text;
++} qi_error_list[] = {
++	{ 0x1F, "Job terminated by FQ or ICID flush" },
++	{ 0x20, "FD format error"},
++	{ 0x21, "FD command format error"},
++	{ 0x23, "FL format error"},
++	{ 0x25, "CRJD specified in FD, but not enabled in FLC"},
++	{ 0x30, "Max. buffer size too small"},
++	{ 0x31, "DHR exceeds max. buffer size (allocate mode, S/G format)"},
++	{ 0x32, "SGT exceeds max. buffer size (allocate mode, S/G format"},
++	{ 0x33, "Size over/underflow (allocate mode)"},
++	{ 0x34, "Size over/underflow (reuse mode)"},
++	{ 0x35, "Length exceeds max. short length (allocate mode, S/G/ format)"},
++	{ 0x36, "Memory footprint exceeds max. value (allocate mode, S/G/ format)"},
++	{ 0x41, "SBC frame format not supported (allocate mode)"},
++	{ 0x42, "Pool 0 invalid / pool 1 size < pool 0 size (allocate mode)"},
++	{ 0x43, "Annotation output enabled but ASAR = 0 (allocate mode)"},
++	{ 0x44, "Unsupported or reserved frame format or SGHR = 1 (reuse mode)"},
++	{ 0x45, "DHR correction underflow (reuse mode, single buffer format)"},
++	{ 0x46, "Annotation length exceeds offset (reuse mode)"},
++	{ 0x48, "Annotation output enabled but ASA limited by ASAR (reuse mode)"},
++	{ 0x49, "Data offset correction exceeds input frame data length (reuse mode)"},
++	{ 0x4B, "Annotation output enabled but ASA cannote be expanded (frame list)"},
++	{ 0x51, "Unsupported IF reuse mode"},
++	{ 0x52, "Unsupported FL use mode"},
++	{ 0x53, "Unsupported RJD use mode"},
++	{ 0x54, "Unsupported inline descriptor use mode"},
++	{ 0xC0, "Table buffer pool 0 depletion"},
++	{ 0xC1, "Table buffer pool 1 depletion"},
++	{ 0xC2, "Data buffer pool 0 depletion, no OF allocated"},
++	{ 0xC3, "Data buffer pool 1 depletion, no OF allocated"},
++	{ 0xC4, "Data buffer pool 0 depletion, partial OF allocated"},
++	{ 0xC5, "Data buffer pool 1 depletion, partial OF allocated"},
++	{ 0xD0, "FLC read error"},
++	{ 0xD1, "FL read error"},
++	{ 0xD2, "FL write error"},
++	{ 0xD3, "OF SGT write error"},
++	{ 0xD4, "PTA read error"},
++	{ 0xD5, "PTA write error"},
++	{ 0xD6, "OF SGT F-bit write error"},
++	{ 0xD7, "ASA write error"},
++	{ 0xE1, "FLC[ICR]=0 ICID error"},
++	{ 0xE2, "FLC[ICR]=1 ICID error"},
++	{ 0xE4, "source of ICID flush not trusted (BDI = 0)"},
++};
++
+ static const char * const cha_id_list[] = {
+ 	"",
+ 	"AES",
+@@ -146,10 +237,9 @@ static void report_ccb_status(struct dev
+ 	    strlen(rng_err_id_list[err_id])) {
+ 		/* RNG-only error */
+ 		err_str = rng_err_id_list[err_id];
+-	} else if (err_id < ARRAY_SIZE(err_id_list))
++	} else {
+ 		err_str = err_id_list[err_id];
+-	else
+-		snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
++	}
+ 
+ 	/*
+ 	 * CCB ICV check failures are part of normal operation life;
+@@ -198,6 +288,27 @@ static void report_deco_status(struct de
+ 		status, error, idx_str, idx, err_str, err_err_code);
+ }
+ 
++static void report_qi_status(struct device *qidev, const u32 status,
++			     const char *error)
++{
++	u8 err_id = status & JRSTA_QIERR_ERROR_MASK;
++	const char *err_str = "unidentified error value 0x";
++	char err_err_code[3] = { 0 };
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qi_error_list); i++)
++		if (qi_error_list[i].value == err_id)
++			break;
++
++	if (i != ARRAY_SIZE(qi_error_list) && qi_error_list[i].error_text)
++		err_str = qi_error_list[i].error_text;
++	else
++		snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
++
++	dev_err(qidev, "%08x: %s: %s%s\n",
++		status, error, err_str, err_err_code);
++}
++
+ static void report_jr_status(struct device *jrdev, const u32 status,
+ 			     const char *error)
+ {
+@@ -212,7 +323,7 @@ static void report_cond_code_status(stru
+ 		status, error, __func__);
+ }
+ 
+-void caam_jr_strstatus(struct device *jrdev, u32 status)
++void caam_strstatus(struct device *jrdev, u32 status, bool qi_v2)
+ {
+ 	static const struct stat_src {
+ 		void (*report_ssed)(struct device *jrdev, const u32 status,
+@@ -224,7 +335,7 @@ void caam_jr_strstatus(struct device *jr
+ 		{ report_ccb_status, "CCB" },
+ 		{ report_jump_status, "Jump" },
+ 		{ report_deco_status, "DECO" },
+-		{ NULL, "Queue Manager Interface" },
++		{ report_qi_status, "Queue Manager Interface" },
+ 		{ report_jr_status, "Job Ring" },
+ 		{ report_cond_code_status, "Condition Code" },
+ 		{ NULL, NULL },
+@@ -250,4 +361,4 @@ void caam_jr_strstatus(struct device *jr
+ 	else
+ 		dev_err(jrdev, "%d: unknown error source\n", ssrc);
+ }
+-EXPORT_SYMBOL(caam_jr_strstatus);
++EXPORT_SYMBOL(caam_strstatus);
+--- a/drivers/crypto/caam/error.h
++++ b/drivers/crypto/caam/error.h
+@@ -7,5 +7,13 @@
+ #ifndef CAAM_ERROR_H
+ #define CAAM_ERROR_H
+ #define CAAM_ERROR_STR_MAX 302
+-void caam_jr_strstatus(struct device *jrdev, u32 status);
++
++void caam_strstatus(struct device *dev, u32 status, bool qi_v2);
++
++#define caam_jr_strstatus(jrdev, status) caam_strstatus(jrdev, status, false)
++#define caam_qi2_strstatus(qidev, status) caam_strstatus(qidev, status, true)
++
++void caam_dump_sg(const char *level, const char *prefix_str, int prefix_type,
++		  int rowsize, int groupsize, struct scatterlist *sg,
++		  size_t tlen, bool ascii);
+ #endif /* CAAM_ERROR_H */
+--- a/drivers/crypto/caam/intern.h
++++ b/drivers/crypto/caam/intern.h
+@@ -64,10 +64,9 @@ struct caam_drv_private_jr {
+  * Driver-private storage for a single CAAM block instance
+  */
+ struct caam_drv_private {
+-
+-	struct device *dev;
+-	struct platform_device **jrpdev; /* Alloc'ed array per sub-device */
+-	struct platform_device *pdev;
++#ifdef CONFIG_CAAM_QI
++	struct device *qidev;
++#endif
+ 
+ 	/* Physical-presence section */
+ 	struct caam_ctrl __iomem *ctrl; /* controller region */
+@@ -84,6 +83,7 @@ struct caam_drv_private {
+ 	u8 qi_present;		/* Nonzero if QI present in device */
+ 	int secvio_irq;		/* Security violation interrupt number */
+ 	int virt_en;		/* Virtualization enabled in CAAM */
++	int era;		/* CAAM Era (internal HW revision) */
+ 
+ #define	RNG4_MAX_HANDLES 2
+ 	/* RNG4 block */
+@@ -103,11 +103,6 @@ struct caam_drv_private {
+ #ifdef CONFIG_DEBUG_FS
+ 	struct dentry *dfs_root;
+ 	struct dentry *ctl; /* controller dir */
+-	struct dentry *ctl_rq_dequeued, *ctl_ob_enc_req, *ctl_ib_dec_req;
+-	struct dentry *ctl_ob_enc_bytes, *ctl_ob_prot_bytes;
+-	struct dentry *ctl_ib_dec_bytes, *ctl_ib_valid_bytes;
+-	struct dentry *ctl_faultaddr, *ctl_faultdetail, *ctl_faultstatus;
+-
+ 	struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
+ 	struct dentry *ctl_kek, *ctl_tkek, *ctl_tdsk;
+ #endif
+@@ -115,4 +110,22 @@ struct caam_drv_private {
+ 
+ void caam_jr_algapi_init(struct device *dev);
+ void caam_jr_algapi_remove(struct device *dev);
++
++#ifdef CONFIG_DEBUG_FS
++static int caam_debugfs_u64_get(void *data, u64 *val)
++{
++	*val = caam64_to_cpu(*(u64 *)data);
++	return 0;
++}
++
++static int caam_debugfs_u32_get(void *data, u64 *val)
++{
++	*val = caam32_to_cpu(*(u32 *)data);
++	return 0;
++}
++
++DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
++DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
++#endif
++
+ #endif /* INTERN_H */
+--- a/drivers/crypto/caam/jr.c
++++ b/drivers/crypto/caam/jr.c
+@@ -9,6 +9,7 @@
+ #include <linux/of_address.h>
+ 
+ #include "compat.h"
++#include "ctrl.h"
+ #include "regs.h"
+ #include "jr.h"
+ #include "desc.h"
+@@ -22,6 +23,14 @@ struct jr_driver_data {
+ 
+ static struct jr_driver_data driver_data;
+ 
++static int jr_driver_probed;
++
++int caam_jr_driver_probed(void)
++{
++	return jr_driver_probed;
++}
++EXPORT_SYMBOL(caam_jr_driver_probed);
++
+ static int caam_reset_hw_jr(struct device *dev)
+ {
+ 	struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
+@@ -118,6 +127,8 @@ static int caam_jr_remove(struct platfor
+ 		dev_err(jrdev, "Failed to shut down job ring\n");
+ 	irq_dispose_mapping(jrpriv->irq);
+ 
++	jr_driver_probed--;
++
+ 	return ret;
+ }
+ 
+@@ -281,6 +292,36 @@ struct device *caam_jr_alloc(void)
+ EXPORT_SYMBOL(caam_jr_alloc);
+ 
+ /**
++ * caam_jridx_alloc() - Alloc a specific job ring based on its index.
++ *
++ * returns :  pointer to the newly allocated physical
++ *	      JobR dev can be written to if successful.
++ **/
++struct device *caam_jridx_alloc(int idx)
++{
++	struct caam_drv_private_jr *jrpriv;
++	struct device *dev = ERR_PTR(-ENODEV);
++
++	spin_lock(&driver_data.jr_alloc_lock);
++
++	if (list_empty(&driver_data.jr_list))
++		goto end;
++
++	list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) {
++		if (jrpriv->ridx == idx) {
++			atomic_inc(&jrpriv->tfm_count);
++			dev = jrpriv->dev;
++			break;
++		}
++	}
++
++end:
++	spin_unlock(&driver_data.jr_alloc_lock);
++	return dev;
++}
++EXPORT_SYMBOL(caam_jridx_alloc);
++
++/**
+  * caam_jr_free() - Free the Job Ring
+  * @rdev     - points to the dev that identifies the Job ring to
+  *             be released.
+@@ -497,15 +538,28 @@ static int caam_jr_probe(struct platform
+ 		return -ENOMEM;
+ 	}
+ 
+-	jrpriv->rregs = (struct caam_job_ring __force *)ctrl;
++	jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl;
+ 
+-	if (sizeof(dma_addr_t) == sizeof(u64))
+-		if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring"))
+-			dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(40));
++	if (sizeof(dma_addr_t) == sizeof(u64)) {
++		if (caam_dpaa2)
++			error = dma_set_mask_and_coherent(jrdev,
++							  DMA_BIT_MASK(49));
++		else if (of_device_is_compatible(nprop,
++						 "fsl,sec-v5.0-job-ring"))
++			error = dma_set_mask_and_coherent(jrdev,
++							  DMA_BIT_MASK(40));
+ 		else
+-			dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(36));
+-	else
+-		dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(32));
++			error = dma_set_mask_and_coherent(jrdev,
++							  DMA_BIT_MASK(36));
++	} else {
++		error = dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(32));
++	}
++	if (error) {
++		dev_err(jrdev, "dma_set_mask_and_coherent failed (%d)\n",
++			error);
++		iounmap(ctrl);
++		return error;
++	}
+ 
+ 	/* Identify the interrupt */
+ 	jrpriv->irq = irq_of_parse_and_map(nprop, 0);
+@@ -525,10 +579,12 @@ static int caam_jr_probe(struct platform
+ 
+ 	atomic_set(&jrpriv->tfm_count, 0);
+ 
++	jr_driver_probed++;
++
+ 	return 0;
+ }
+ 
+-static struct of_device_id caam_jr_match[] = {
++static const struct of_device_id caam_jr_match[] = {
+ 	{
+ 		.compatible = "fsl,sec-v4.0-job-ring",
+ 	},
+--- a/drivers/crypto/caam/jr.h
++++ b/drivers/crypto/caam/jr.h
+@@ -8,7 +8,9 @@
+ #define JR_H
+ 
+ /* Prototypes for backend-level services exposed to APIs */
++int caam_jr_driver_probed(void);
+ struct device *caam_jr_alloc(void);
++struct device *caam_jridx_alloc(int idx);
+ void caam_jr_free(struct device *rdev);
+ int caam_jr_enqueue(struct device *dev, u32 *desc,
+ 		    void (*cbk)(struct device *dev, u32 *desc, u32 status,
+--- a/drivers/crypto/caam/key_gen.c
++++ b/drivers/crypto/caam/key_gen.c
+@@ -41,15 +41,29 @@ Split key generation--------------------
+ [06] 0x64260028    fifostr: class2 mdsplit-jdk len=40
+ 			@0xffe04000
+ */
+-int gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len,
+-		  int split_key_pad_len, const u8 *key_in, u32 keylen,
+-		  u32 alg_op)
++int gen_split_key(struct device *jrdev, u8 *key_out,
++		  struct alginfo * const adata, const u8 *key_in, u32 keylen,
++		  int max_keylen)
+ {
+ 	u32 *desc;
+ 	struct split_key_result result;
+ 	dma_addr_t dma_addr_in, dma_addr_out;
+ 	int ret = -ENOMEM;
+ 
++	adata->keylen = split_key_len(adata->algtype & OP_ALG_ALGSEL_MASK);
++	adata->keylen_pad = split_key_pad_len(adata->algtype &
++					      OP_ALG_ALGSEL_MASK);
++
++#ifdef DEBUG
++	dev_err(jrdev, "split keylen %d split keylen padded %d\n",
++		adata->keylen, adata->keylen_pad);
++	print_hex_dump(KERN_ERR, "ctx.key@" __stringify(__LINE__)": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, key_in, keylen, 1);
++#endif
++
++	if (adata->keylen_pad > max_keylen)
++		return -EINVAL;
++
+ 	desc = kmalloc(CAAM_CMD_SZ * 6 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA);
+ 	if (!desc) {
+ 		dev_err(jrdev, "unable to allocate key input memory\n");
+@@ -63,7 +77,7 @@ int gen_split_key(struct device *jrdev,
+ 		goto out_free;
+ 	}
+ 
+-	dma_addr_out = dma_map_single(jrdev, key_out, split_key_pad_len,
++	dma_addr_out = dma_map_single(jrdev, key_out, adata->keylen_pad,
+ 				      DMA_FROM_DEVICE);
+ 	if (dma_mapping_error(jrdev, dma_addr_out)) {
+ 		dev_err(jrdev, "unable to map key output memory\n");
+@@ -74,7 +88,9 @@ int gen_split_key(struct device *jrdev,
+ 	append_key(desc, dma_addr_in, keylen, CLASS_2 | KEY_DEST_CLASS_REG);
+ 
+ 	/* Sets MDHA up into an HMAC-INIT */
+-	append_operation(desc, alg_op | OP_ALG_DECRYPT | OP_ALG_AS_INIT);
++	append_operation(desc, (adata->algtype & OP_ALG_ALGSEL_MASK) |
++			 OP_ALG_AAI_HMAC | OP_TYPE_CLASS2_ALG | OP_ALG_DECRYPT |
++			 OP_ALG_AS_INIT);
+ 
+ 	/*
+ 	 * do a FIFO_LOAD of zero, this will trigger the internal key expansion
+@@ -87,7 +103,7 @@ int gen_split_key(struct device *jrdev,
+ 	 * FIFO_STORE with the explicit split-key content store
+ 	 * (0x26 output type)
+ 	 */
+-	append_fifo_store(desc, dma_addr_out, split_key_len,
++	append_fifo_store(desc, dma_addr_out, adata->keylen,
+ 			  LDST_CLASS_2_CCB | FIFOST_TYPE_SPLIT_KEK);
+ 
+ #ifdef DEBUG
+@@ -108,11 +124,11 @@ int gen_split_key(struct device *jrdev,
+ #ifdef DEBUG
+ 		print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
+ 			       DUMP_PREFIX_ADDRESS, 16, 4, key_out,
+-			       split_key_pad_len, 1);
++			       adata->keylen_pad, 1);
+ #endif
+ 	}
+ 
+-	dma_unmap_single(jrdev, dma_addr_out, split_key_pad_len,
++	dma_unmap_single(jrdev, dma_addr_out, adata->keylen_pad,
+ 			 DMA_FROM_DEVICE);
+ out_unmap_in:
+ 	dma_unmap_single(jrdev, dma_addr_in, keylen, DMA_TO_DEVICE);
+--- a/drivers/crypto/caam/key_gen.h
++++ b/drivers/crypto/caam/key_gen.h
+@@ -5,6 +5,36 @@
+  *
+  */
+ 
++/**
++ * split_key_len - Compute MDHA split key length for a given algorithm
++ * @hash: Hashing algorithm selection, one of OP_ALG_ALGSEL_* - MD5, SHA1,
++ *        SHA224, SHA384, SHA512.
++ *
++ * Return: MDHA split key length
++ */
++static inline u32 split_key_len(u32 hash)
++{
++	/* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
++	static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
++	u32 idx;
++
++	idx = (hash & OP_ALG_ALGSEL_SUBMASK) >> OP_ALG_ALGSEL_SHIFT;
++
++	return (u32)(mdpadlen[idx] * 2);
++}
++
++/**
++ * split_key_pad_len - Compute MDHA split key pad length for a given algorithm
++ * @hash: Hashing algorithm selection, one of OP_ALG_ALGSEL_* - MD5, SHA1,
++ *        SHA224, SHA384, SHA512.
++ *
++ * Return: MDHA split key pad length
++ */
++static inline u32 split_key_pad_len(u32 hash)
++{
++	return ALIGN(split_key_len(hash), 16);
++}
++
+ struct split_key_result {
+ 	struct completion completion;
+ 	int err;
+@@ -12,6 +42,6 @@ struct split_key_result {
+ 
+ void split_key_done(struct device *dev, u32 *desc, u32 err, void *context);
+ 
+-int gen_split_key(struct device *jrdev, u8 *key_out, int split_key_len,
+-		    int split_key_pad_len, const u8 *key_in, u32 keylen,
+-		    u32 alg_op);
++int gen_split_key(struct device *jrdev, u8 *key_out,
++		  struct alginfo * const adata, const u8 *key_in, u32 keylen,
++		  int max_keylen);
+--- a/drivers/crypto/caam/pdb.h
++++ b/drivers/crypto/caam/pdb.h
+@@ -483,6 +483,8 @@ struct dsa_verify_pdb {
+ #define RSA_PDB_E_MASK          (0xFFF << RSA_PDB_E_SHIFT)
+ #define RSA_PDB_D_SHIFT         12
+ #define RSA_PDB_D_MASK          (0xFFF << RSA_PDB_D_SHIFT)
++#define RSA_PDB_Q_SHIFT         12
++#define RSA_PDB_Q_MASK          (0xFFF << RSA_PDB_Q_SHIFT)
+ 
+ #define RSA_PDB_SGF_F           (0x8 << RSA_PDB_SGF_SHIFT)
+ #define RSA_PDB_SGF_G           (0x4 << RSA_PDB_SGF_SHIFT)
+@@ -490,6 +492,8 @@ struct dsa_verify_pdb {
+ #define RSA_PRIV_PDB_SGF_G      (0x8 << RSA_PDB_SGF_SHIFT)
+ 
+ #define RSA_PRIV_KEY_FRM_1      0
++#define RSA_PRIV_KEY_FRM_2      1
++#define RSA_PRIV_KEY_FRM_3      2
+ 
+ /**
+  * RSA Encrypt Protocol Data Block
+@@ -525,4 +529,62 @@ struct rsa_priv_f1_pdb {
+ 	dma_addr_t	d_dma;
+ } __packed;
+ 
++/**
++ * RSA Decrypt PDB - Private Key Form #2
++ * @sgf     : scatter-gather field
++ * @g_dma   : dma address of encrypted input data
++ * @f_dma   : dma address of output data
++ * @d_dma   : dma address of RSA private exponent
++ * @p_dma   : dma address of RSA prime factor p of RSA modulus n
++ * @q_dma   : dma address of RSA prime factor q of RSA modulus n
++ * @tmp1_dma: dma address of temporary buffer. CAAM uses this temporary buffer
++ *            as internal state buffer. It is assumed to be as long as p.
++ * @tmp2_dma: dma address of temporary buffer. CAAM uses this temporary buffer
++ *            as internal state buffer. It is assumed to be as long as q.
++ * @p_q_len : length in bytes of first two prime factors of the RSA modulus n
++ */
++struct rsa_priv_f2_pdb {
++	u32		sgf;
++	dma_addr_t	g_dma;
++	dma_addr_t	f_dma;
++	dma_addr_t	d_dma;
++	dma_addr_t	p_dma;
++	dma_addr_t	q_dma;
++	dma_addr_t	tmp1_dma;
++	dma_addr_t	tmp2_dma;
++	u32		p_q_len;
++} __packed;
++
++/**
++ * RSA Decrypt PDB - Private Key Form #3
++ * This is the RSA Chinese Reminder Theorem (CRT) form for two prime factors of
++ * the RSA modulus.
++ * @sgf     : scatter-gather field
++ * @g_dma   : dma address of encrypted input data
++ * @f_dma   : dma address of output data
++ * @c_dma   : dma address of RSA CRT coefficient
++ * @p_dma   : dma address of RSA prime factor p of RSA modulus n
++ * @q_dma   : dma address of RSA prime factor q of RSA modulus n
++ * @dp_dma  : dma address of RSA CRT exponent of RSA prime factor p
++ * @dp_dma  : dma address of RSA CRT exponent of RSA prime factor q
++ * @tmp1_dma: dma address of temporary buffer. CAAM uses this temporary buffer
++ *            as internal state buffer. It is assumed to be as long as p.
++ * @tmp2_dma: dma address of temporary buffer. CAAM uses this temporary buffer
++ *            as internal state buffer. It is assumed to be as long as q.
++ * @p_q_len : length in bytes of first two prime factors of the RSA modulus n
++ */
++struct rsa_priv_f3_pdb {
++	u32		sgf;
++	dma_addr_t	g_dma;
++	dma_addr_t	f_dma;
++	dma_addr_t	c_dma;
++	dma_addr_t	p_dma;
++	dma_addr_t	q_dma;
++	dma_addr_t	dp_dma;
++	dma_addr_t	dq_dma;
++	dma_addr_t	tmp1_dma;
++	dma_addr_t	tmp2_dma;
++	u32		p_q_len;
++} __packed;
++
+ #endif
+--- a/drivers/crypto/caam/pkc_desc.c
++++ b/drivers/crypto/caam/pkc_desc.c
+@@ -34,3 +34,39 @@ void init_rsa_priv_f1_desc(u32 *desc, st
+ 	append_operation(desc, OP_TYPE_UNI_PROTOCOL | OP_PCLID_RSADEC_PRVKEY |
+ 			 RSA_PRIV_KEY_FRM_1);
+ }
++
++/* Descriptor for RSA Private operation - Private Key Form #2 */
++void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb)
++{
++	init_job_desc_pdb(desc, 0, sizeof(*pdb));
++	append_cmd(desc, pdb->sgf);
++	append_ptr(desc, pdb->g_dma);
++	append_ptr(desc, pdb->f_dma);
++	append_ptr(desc, pdb->d_dma);
++	append_ptr(desc, pdb->p_dma);
++	append_ptr(desc, pdb->q_dma);
++	append_ptr(desc, pdb->tmp1_dma);
++	append_ptr(desc, pdb->tmp2_dma);
++	append_cmd(desc, pdb->p_q_len);
++	append_operation(desc, OP_TYPE_UNI_PROTOCOL | OP_PCLID_RSADEC_PRVKEY |
++			 RSA_PRIV_KEY_FRM_2);
++}
++
++/* Descriptor for RSA Private operation - Private Key Form #3 */
++void init_rsa_priv_f3_desc(u32 *desc, struct rsa_priv_f3_pdb *pdb)
++{
++	init_job_desc_pdb(desc, 0, sizeof(*pdb));
++	append_cmd(desc, pdb->sgf);
++	append_ptr(desc, pdb->g_dma);
++	append_ptr(desc, pdb->f_dma);
++	append_ptr(desc, pdb->c_dma);
++	append_ptr(desc, pdb->p_dma);
++	append_ptr(desc, pdb->q_dma);
++	append_ptr(desc, pdb->dp_dma);
++	append_ptr(desc, pdb->dq_dma);
++	append_ptr(desc, pdb->tmp1_dma);
++	append_ptr(desc, pdb->tmp2_dma);
++	append_cmd(desc, pdb->p_q_len);
++	append_operation(desc, OP_TYPE_UNI_PROTOCOL | OP_PCLID_RSADEC_PRVKEY |
++			 RSA_PRIV_KEY_FRM_3);
++}
+--- /dev/null
++++ b/drivers/crypto/caam/qi.c
+@@ -0,0 +1,804 @@
++/*
++ * CAAM/SEC 4.x QI transport/backend driver
++ * Queue Interface backend functionality
++ *
++ * Copyright 2013-2016 Freescale Semiconductor, Inc.
++ * Copyright 2016-2017 NXP
++ */
++
++#include <linux/cpumask.h>
++#include <linux/kthread.h>
++#include <linux/fsl_qman.h>
++
++#include "regs.h"
++#include "qi.h"
++#include "desc.h"
++#include "intern.h"
++#include "desc_constr.h"
++
++#define PREHDR_RSLS_SHIFT	31
++
++/*
++ * Use a reasonable backlog of frames (per CPU) as congestion threshold,
++ * so that resources used by the in-flight buffers do not become a memory hog.
++ */
++#define MAX_RSP_FQ_BACKLOG_PER_CPU	256
++
++#define CAAM_QI_ENQUEUE_RETRIES	10000
++
++#define CAAM_NAPI_WEIGHT	63
++
++/*
++ * caam_napi - struct holding CAAM NAPI-related params
++ * @irqtask: IRQ task for QI backend
++ * @p: QMan portal
++ */
++struct caam_napi {
++	struct napi_struct irqtask;
++	struct qman_portal *p;
++};
++
++/*
++ * caam_qi_pcpu_priv - percpu private data structure to main list of pending
++ *                     responses expected on each cpu.
++ * @caam_napi: CAAM NAPI params
++ * @net_dev: netdev used by NAPI
++ * @rsp_fq: response FQ from CAAM
++ */
++struct caam_qi_pcpu_priv {
++	struct caam_napi caam_napi;
++	struct net_device net_dev;
++	struct qman_fq *rsp_fq;
++} ____cacheline_aligned;
++
++static DEFINE_PER_CPU(struct caam_qi_pcpu_priv, pcpu_qipriv);
++static DEFINE_PER_CPU(int, last_cpu);
++
++/*
++ * caam_qi_priv - CAAM QI backend private params
++ * @cgr: QMan congestion group
++ * @qi_pdev: platform device for QI backend
++ */
++struct caam_qi_priv {
++	struct qman_cgr cgr;
++	struct platform_device *qi_pdev;
++};
++
++static struct caam_qi_priv qipriv ____cacheline_aligned;
++
++/*
++ * This is written by only one core - the one that initialized the CGR - and
++ * read by multiple cores (all the others).
++ */
++bool caam_congested __read_mostly;
++EXPORT_SYMBOL(caam_congested);
++
++#ifdef CONFIG_DEBUG_FS
++/*
++ * This is a counter for the number of times the congestion group (where all
++ * the request and response queueus are) reached congestion. Incremented
++ * each time the congestion callback is called with congested == true.
++ */
++static u64 times_congested;
++#endif
++
++/*
++ * CPU from where the module initialised. This is required because QMan driver
++ * requires CGRs to be removed from same CPU from where they were originally
++ * allocated.
++ */
++static int mod_init_cpu;
++
++/*
++ * This is a a cache of buffers, from which the users of CAAM QI driver
++ * can allocate short (CAAM_QI_MEMCACHE_SIZE) buffers. It's faster than
++ * doing malloc on the hotpath.
++ * NOTE: A more elegant solution would be to have some headroom in the frames
++ *       being processed. This could be added by the dpaa-ethernet driver.
++ *       This would pose a problem for userspace application processing which
++ *       cannot know of this limitation. So for now, this will work.
++ * NOTE: The memcache is SMP-safe. No need to handle spinlocks in-here
++ */
++static struct kmem_cache *qi_cache;
++
++int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req)
++{
++	struct qm_fd fd;
++	int ret;
++	int num_retries = 0;
++
++	fd.cmd = 0;
++	fd.format = qm_fd_compound;
++	fd.cong_weight = caam32_to_cpu(req->fd_sgt[1].length);
++	fd.addr = dma_map_single(qidev, req->fd_sgt, sizeof(req->fd_sgt),
++			      DMA_BIDIRECTIONAL);
++	if (dma_mapping_error(qidev, fd.addr)) {
++		dev_err(qidev, "DMA mapping error for QI enqueue request\n");
++		return -EIO;
++	}
++
++	do {
++		ret = qman_enqueue(req->drv_ctx->req_fq, &fd, 0);
++		if (likely(!ret))
++			return 0;
++
++		if (ret != -EBUSY)
++			break;
++		num_retries++;
++	} while (num_retries < CAAM_QI_ENQUEUE_RETRIES);
++
++	dev_err(qidev, "qman_enqueue failed: %d\n", ret);
++
++	return ret;
++}
++EXPORT_SYMBOL(caam_qi_enqueue);
++
++static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq,
++			   const struct qm_mr_entry *msg)
++{
++	const struct qm_fd *fd;
++	struct caam_drv_req *drv_req;
++	struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
++
++	fd = &msg->ern.fd;
++
++	if (fd->format != qm_fd_compound) {
++		dev_err(qidev, "Non-compound FD from CAAM\n");
++		return;
++	}
++
++	drv_req = (struct caam_drv_req *)phys_to_virt(qm_fd_addr_get64(fd));
++	if (!drv_req) {
++		dev_err(qidev,
++			"Can't find original request for CAAM response\n");
++		return;
++	}
++
++	dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
++			 sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
++
++	drv_req->cbk(drv_req, -EIO);
++}
++
++static struct qman_fq *create_caam_req_fq(struct device *qidev,
++					  struct qman_fq *rsp_fq,
++					  dma_addr_t hwdesc,
++					  int fq_sched_flag)
++{
++	int ret;
++	struct qman_fq *req_fq;
++	struct qm_mcc_initfq opts;
++
++	req_fq = kzalloc(sizeof(*req_fq), GFP_ATOMIC);
++	if (!req_fq)
++		return ERR_PTR(-ENOMEM);
++
++	req_fq->cb.ern = caam_fq_ern_cb;
++	req_fq->cb.fqs = NULL;
++
++	ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
++				QMAN_FQ_FLAG_TO_DCPORTAL | QMAN_FQ_FLAG_LOCKED,
++			     req_fq);
++	if (ret) {
++		dev_err(qidev, "Failed to create session req FQ\n");
++		goto create_req_fq_fail;
++	}
++
++	opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
++		       QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA |
++		       QM_INITFQ_WE_CGID;
++	opts.fqd.fq_ctrl = QM_FQCTRL_CPCSTASH | QM_FQCTRL_CGE;
++	opts.fqd.dest.channel = qm_channel_caam;
++	opts.fqd.dest.wq = 2;
++	opts.fqd.context_b = qman_fq_fqid(rsp_fq);
++	opts.fqd.context_a.hi = upper_32_bits(hwdesc);
++	opts.fqd.context_a.lo = lower_32_bits(hwdesc);
++	opts.fqd.cgid = qipriv.cgr.cgrid;
++
++	ret = qman_init_fq(req_fq, fq_sched_flag, &opts);
++	if (ret) {
++		dev_err(qidev, "Failed to init session req FQ\n");
++		goto init_req_fq_fail;
++	}
++
++	dev_dbg(qidev, "Allocated request FQ %u for CPU %u\n", req_fq->fqid,
++		smp_processor_id());
++	return req_fq;
++
++init_req_fq_fail:
++	qman_destroy_fq(req_fq, 0);
++create_req_fq_fail:
++	kfree(req_fq);
++	return ERR_PTR(ret);
++}
++
++static int empty_retired_fq(struct device *qidev, struct qman_fq *fq)
++{
++	int ret;
++
++	ret = qman_volatile_dequeue(fq, QMAN_VOLATILE_FLAG_WAIT_INT |
++				    QMAN_VOLATILE_FLAG_FINISH,
++				    QM_VDQCR_PRECEDENCE_VDQCR |
++				    QM_VDQCR_NUMFRAMES_TILLEMPTY);
++	if (ret) {
++		dev_err(qidev, "Volatile dequeue fail for FQ: %u\n", fq->fqid);
++		return ret;
++	}
++
++	do {
++		struct qman_portal *p;
++
++		p = qman_get_affine_portal(smp_processor_id());
++		qman_p_poll_dqrr(p, 16);
++	} while (fq->flags & QMAN_FQ_STATE_NE);
++
++	return 0;
++}
++
++static int kill_fq(struct device *qidev, struct qman_fq *fq)
++{
++	u32 flags;
++	int ret;
++
++	ret = qman_retire_fq(fq, &flags);
++	if (ret < 0) {
++		dev_err(qidev, "qman_retire_fq failed: %d\n", ret);
++		return ret;
++	}
++
++	if (!ret)
++		goto empty_fq;
++
++	/* Async FQ retirement condition */
++	if (ret == 1) {
++		/* Retry till FQ gets in retired state */
++		do {
++			msleep(20);
++		} while (fq->state != qman_fq_state_retired);
++
++		WARN_ON(fq->flags & QMAN_FQ_STATE_BLOCKOOS);
++		WARN_ON(fq->flags & QMAN_FQ_STATE_ORL);
++	}
++
++empty_fq:
++	if (fq->flags & QMAN_FQ_STATE_NE) {
++		ret = empty_retired_fq(qidev, fq);
++		if (ret) {
++			dev_err(qidev, "empty_retired_fq fail for FQ: %u\n",
++				fq->fqid);
++			return ret;
++		}
++	}
++
++	ret = qman_oos_fq(fq);
++	if (ret)
++		dev_err(qidev, "OOS of FQID: %u failed\n", fq->fqid);
++
++	qman_destroy_fq(fq, 0);
++	kfree(fq);
++
++	return ret;
++}
++
++static int empty_caam_fq(struct qman_fq *fq)
++{
++	int ret;
++	struct qm_mcr_queryfq_np np;
++
++	/* Wait till the older CAAM FQ get empty */
++	do {
++		ret = qman_query_fq_np(fq, &np);
++		if (ret)
++			return ret;
++
++		if (!np.frm_cnt)
++			break;
++
++		msleep(20);
++	} while (1);
++
++	/*
++	 * Give extra time for pending jobs from this FQ in holding tanks
++	 * to get processed
++	 */
++	msleep(20);
++	return 0;
++}
++
++int caam_drv_ctx_update(struct caam_drv_ctx *drv_ctx, u32 *sh_desc)
++{
++	int ret;
++	u32 num_words;
++	struct qman_fq *new_fq, *old_fq;
++	struct device *qidev = drv_ctx->qidev;
++
++	num_words = desc_len(sh_desc);
++	if (num_words > MAX_SDLEN) {
++		dev_err(qidev, "Invalid descriptor len: %d words\n", num_words);
++		return -EINVAL;
++	}
++
++	/* Note down older req FQ */
++	old_fq = drv_ctx->req_fq;
++
++	/* Create a new req FQ in parked state */
++	new_fq = create_caam_req_fq(drv_ctx->qidev, drv_ctx->rsp_fq,
++				    drv_ctx->context_a, 0);
++	if (unlikely(IS_ERR_OR_NULL(new_fq))) {
++		dev_err(qidev, "FQ allocation for shdesc update failed\n");
++		return PTR_ERR(new_fq);
++	}
++
++	/* Hook up new FQ to context so that new requests keep queuing */
++	drv_ctx->req_fq = new_fq;
++
++	/* Empty and remove the older FQ */
++	ret = empty_caam_fq(old_fq);
++	if (ret) {
++		dev_err(qidev, "Old CAAM FQ empty failed: %d\n", ret);
++
++		/* We can revert to older FQ */
++		drv_ctx->req_fq = old_fq;
++
++		if (kill_fq(qidev, new_fq))
++			dev_warn(qidev, "New CAAM FQ kill failed\n");
++
++		return ret;
++	}
++
++	/*
++	 * Re-initialise pre-header. Set RSLS and SDLEN.
++	 * Update the shared descriptor for driver context.
++	 */
++	drv_ctx->prehdr[0] = cpu_to_caam32((1 << PREHDR_RSLS_SHIFT) |
++					   num_words);
++	memcpy(drv_ctx->sh_desc, sh_desc, desc_bytes(sh_desc));
++	dma_sync_single_for_device(qidev, drv_ctx->context_a,
++				   sizeof(drv_ctx->sh_desc) +
++				   sizeof(drv_ctx->prehdr),
++				   DMA_BIDIRECTIONAL);
++
++	/* Put the new FQ in scheduled state */
++	ret = qman_schedule_fq(new_fq);
++	if (ret) {
++		dev_err(qidev, "Fail to sched new CAAM FQ, ecode = %d\n", ret);
++
++		/*
++		 * We can kill new FQ and revert to old FQ.
++		 * Since the desc is already modified, it is success case
++		 */
++
++		drv_ctx->req_fq = old_fq;
++
++		if (kill_fq(qidev, new_fq))
++			dev_warn(qidev, "New CAAM FQ kill failed\n");
++	} else if (kill_fq(qidev, old_fq)) {
++		dev_warn(qidev, "Old CAAM FQ kill failed\n");
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL(caam_drv_ctx_update);
++
++struct caam_drv_ctx *caam_drv_ctx_init(struct device *qidev,
++				       int *cpu,
++				       u32 *sh_desc)
++{
++	size_t size;
++	u32 num_words;
++	dma_addr_t hwdesc;
++	struct caam_drv_ctx *drv_ctx;
++	const cpumask_t *cpus = qman_affine_cpus();
++
++	num_words = desc_len(sh_desc);
++	if (num_words > MAX_SDLEN) {
++		dev_err(qidev, "Invalid descriptor len: %d words\n",
++			num_words);
++		return ERR_PTR(-EINVAL);
++	}
++
++	drv_ctx = kzalloc(sizeof(*drv_ctx), GFP_ATOMIC);
++	if (!drv_ctx)
++		return ERR_PTR(-ENOMEM);
++
++	/*
++	 * Initialise pre-header - set RSLS and SDLEN - and shared descriptor
++	 * and dma-map them.
++	 */
++	drv_ctx->prehdr[0] = cpu_to_caam32((1 << PREHDR_RSLS_SHIFT) |
++					   num_words);
++	memcpy(drv_ctx->sh_desc, sh_desc, desc_bytes(sh_desc));
++	size = sizeof(drv_ctx->prehdr) + sizeof(drv_ctx->sh_desc);
++	hwdesc = dma_map_single(qidev, drv_ctx->prehdr, size,
++				DMA_BIDIRECTIONAL);
++	if (dma_mapping_error(qidev, hwdesc)) {
++		dev_err(qidev, "DMA map error for preheader + shdesc\n");
++		kfree(drv_ctx);
++		return ERR_PTR(-ENOMEM);
++	}
++	drv_ctx->context_a = hwdesc;
++
++	/* If given CPU does not own the portal, choose another one that does */
++	if (!cpumask_test_cpu(*cpu, cpus)) {
++		int *pcpu = &get_cpu_var(last_cpu);
++
++		*pcpu = cpumask_next(*pcpu, cpus);
++		if (*pcpu >= nr_cpu_ids)
++			*pcpu = cpumask_first(cpus);
++		*cpu = *pcpu;
++
++		put_cpu_var(last_cpu);
++	}
++	drv_ctx->cpu = *cpu;
++
++	/* Find response FQ hooked with this CPU */
++	drv_ctx->rsp_fq = per_cpu(pcpu_qipriv.rsp_fq, drv_ctx->cpu);
++
++	/* Attach request FQ */
++	drv_ctx->req_fq = create_caam_req_fq(qidev, drv_ctx->rsp_fq, hwdesc,
++					     QMAN_INITFQ_FLAG_SCHED);
++	if (unlikely(IS_ERR_OR_NULL(drv_ctx->req_fq))) {
++		dev_err(qidev, "create_caam_req_fq failed\n");
++		dma_unmap_single(qidev, hwdesc, size, DMA_BIDIRECTIONAL);
++		kfree(drv_ctx);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	drv_ctx->qidev = qidev;
++	return drv_ctx;
++}
++EXPORT_SYMBOL(caam_drv_ctx_init);
++
++void *qi_cache_alloc(gfp_t flags)
++{
++	return kmem_cache_alloc(qi_cache, flags);
++}
++EXPORT_SYMBOL(qi_cache_alloc);
++
++void qi_cache_free(void *obj)
++{
++	kmem_cache_free(qi_cache, obj);
++}
++EXPORT_SYMBOL(qi_cache_free);
++
++static int caam_qi_poll(struct napi_struct *napi, int budget)
++{
++	struct caam_napi *np = container_of(napi, struct caam_napi, irqtask);
++
++	int cleaned = qman_p_poll_dqrr(np->p, budget);
++
++	if (cleaned < budget) {
++		napi_complete(napi);
++		qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
++	}
++
++	return cleaned;
++}
++
++void caam_drv_ctx_rel(struct caam_drv_ctx *drv_ctx)
++{
++	if (IS_ERR_OR_NULL(drv_ctx))
++		return;
++
++	/* Remove request FQ */
++	if (kill_fq(drv_ctx->qidev, drv_ctx->req_fq))
++		dev_err(drv_ctx->qidev, "Crypto session req FQ kill failed\n");
++
++	dma_unmap_single(drv_ctx->qidev, drv_ctx->context_a,
++			 sizeof(drv_ctx->sh_desc) + sizeof(drv_ctx->prehdr),
++			 DMA_BIDIRECTIONAL);
++	kfree(drv_ctx);
++}
++EXPORT_SYMBOL(caam_drv_ctx_rel);
++
++int caam_qi_shutdown(struct device *qidev)
++{
++	int i, ret;
++	struct caam_qi_priv *priv = dev_get_drvdata(qidev);
++	const cpumask_t *cpus = qman_affine_cpus();
++	struct cpumask old_cpumask = current->cpus_allowed;
++
++	for_each_cpu(i, cpus) {
++		struct napi_struct *irqtask;
++
++		irqtask = &per_cpu_ptr(&pcpu_qipriv.caam_napi, i)->irqtask;
++		napi_disable(irqtask);
++		netif_napi_del(irqtask);
++
++		if (kill_fq(qidev, per_cpu(pcpu_qipriv.rsp_fq, i)))
++			dev_err(qidev, "Rsp FQ kill failed, cpu: %d\n", i);
++	}
++
++	/*
++	 * QMan driver requires CGRs to be deleted from same CPU from where they
++	 * were instantiated. Hence we get the module removal execute from the
++	 * same CPU from where it was originally inserted.
++	 */
++	set_cpus_allowed_ptr(current, get_cpu_mask(mod_init_cpu));
++
++	ret = qman_delete_cgr(&priv->cgr);
++	if (ret)
++		dev_err(qidev, "Deletion of CGR failed: %d\n", ret);
++	else
++		qman_release_cgrid(priv->cgr.cgrid);
++
++	kmem_cache_destroy(qi_cache);
++
++	/* Now that we're done with the CGRs, restore the cpus allowed mask */
++	set_cpus_allowed_ptr(current, &old_cpumask);
++
++	platform_device_unregister(priv->qi_pdev);
++	return ret;
++}
++
++static void cgr_cb(struct qman_portal *qm, struct qman_cgr *cgr, int congested)
++{
++	caam_congested = congested;
++
++	if (congested) {
++#ifdef CONFIG_DEBUG_FS
++		times_congested++;
++#endif
++		pr_debug_ratelimited("CAAM entered congestion\n");
++
++	} else {
++		pr_debug_ratelimited("CAAM exited congestion\n");
++	}
++}
++
++static int caam_qi_napi_schedule(struct qman_portal *p, struct caam_napi *np)
++{
++	/*
++	 * In case of threaded ISR, for RT kernels in_irq() does not return
++	 * appropriate value, so use in_serving_softirq to distinguish between
++	 * softirq and irq contexts.
++	 */
++	if (unlikely(in_irq() || !in_serving_softirq())) {
++		/* Disable QMan IRQ source and invoke NAPI */
++		qman_p_irqsource_remove(p, QM_PIRQ_DQRI);
++		np->p = p;
++		napi_schedule(&np->irqtask);
++		return 1;
++	}
++	return 0;
++}
++
++static enum qman_cb_dqrr_result caam_rsp_fq_dqrr_cb(struct qman_portal *p,
++						    struct qman_fq *rsp_fq,
++						    const struct qm_dqrr_entry *dqrr)
++{
++	struct caam_napi *caam_napi = raw_cpu_ptr(&pcpu_qipriv.caam_napi);
++	struct caam_drv_req *drv_req;
++	const struct qm_fd *fd;
++	struct device *qidev = &(raw_cpu_ptr(&pcpu_qipriv)->net_dev.dev);
++
++	if (caam_qi_napi_schedule(p, caam_napi))
++		return qman_cb_dqrr_stop;
++
++	fd = &dqrr->fd;
++	if (unlikely(fd->status)) {
++		u32 ssrc = fd->status & JRSTA_SSRC_MASK;
++		u8 err_id = fd->status & JRSTA_CCBERR_ERRID_MASK;
++
++		if (ssrc != JRSTA_SSRC_CCB_ERROR ||
++		    err_id != JRSTA_CCBERR_ERRID_ICVCHK)
++			dev_err(qidev, "Error: %#x in CAAM response FD\n",
++				fd->status);
++	}
++
++	if (unlikely(fd->format != fd->format)) {
++		dev_err(qidev, "Non-compound FD from CAAM\n");
++		return qman_cb_dqrr_consume;
++	}
++
++	drv_req = (struct caam_drv_req *)phys_to_virt(fd->addr);
++	if (unlikely(!drv_req)) {
++		dev_err(qidev,
++			"Can't find original request for caam response\n");
++		return qman_cb_dqrr_consume;
++	}
++
++	dma_unmap_single(drv_req->drv_ctx->qidev, qm_fd_addr(fd),
++			 sizeof(drv_req->fd_sgt), DMA_BIDIRECTIONAL);
++
++	drv_req->cbk(drv_req, fd->status);
++	return qman_cb_dqrr_consume;
++}
++
++static int alloc_rsp_fq_cpu(struct device *qidev, unsigned int cpu)
++{
++	struct qm_mcc_initfq opts;
++	struct qman_fq *fq;
++	int ret;
++
++	fq = kzalloc(sizeof(*fq), GFP_KERNEL | GFP_DMA);
++	if (!fq)
++		return -ENOMEM;
++
++	fq->cb.dqrr = caam_rsp_fq_dqrr_cb;
++
++	ret = qman_create_fq(0, QMAN_FQ_FLAG_NO_ENQUEUE |
++			     QMAN_FQ_FLAG_DYNAMIC_FQID, fq);
++	if (ret) {
++		dev_err(qidev, "Rsp FQ create failed\n");
++		kfree(fq);
++		return -ENODEV;
++	}
++
++	opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_DESTWQ |
++		QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA |
++		QM_INITFQ_WE_CGID;
++	opts.fqd.fq_ctrl = QM_FQCTRL_CTXASTASHING | QM_FQCTRL_CPCSTASH |
++			   QM_FQCTRL_CGE;
++	opts.fqd.dest.channel = qman_affine_channel(cpu);
++	opts.fqd.dest.wq = 3;
++	opts.fqd.cgid = qipriv.cgr.cgrid;
++	opts.fqd.context_a.stashing.exclusive =	QM_STASHING_EXCL_CTX |
++						QM_STASHING_EXCL_DATA;
++	opts.fqd.context_a.stashing.data_cl = 1;
++	opts.fqd.context_a.stashing.context_cl = 1;
++
++	ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
++	if (ret) {
++		dev_err(qidev, "Rsp FQ init failed\n");
++		kfree(fq);
++		return -ENODEV;
++	}
++
++	per_cpu(pcpu_qipriv.rsp_fq, cpu) = fq;
++
++	dev_dbg(qidev, "Allocated response FQ %u for CPU %u", fq->fqid, cpu);
++	return 0;
++}
++
++static int init_cgr(struct device *qidev)
++{
++	int ret;
++	struct qm_mcc_initcgr opts;
++	const u64 cpus = *(u64 *)qman_affine_cpus();
++	const int num_cpus = hweight64(cpus);
++	const u64 val = num_cpus * MAX_RSP_FQ_BACKLOG_PER_CPU;
++
++	ret = qman_alloc_cgrid(&qipriv.cgr.cgrid);
++	if (ret) {
++		dev_err(qidev, "CGR alloc failed for rsp FQs: %d\n", ret);
++		return ret;
++	}
++
++	qipriv.cgr.cb = cgr_cb;
++	memset(&opts, 0, sizeof(opts));
++	opts.we_mask = QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES | QM_CGR_WE_MODE;
++	opts.cgr.cscn_en = QM_CGR_EN;
++	opts.cgr.mode = QMAN_CGR_MODE_FRAME;
++	qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, val, 1);
++
++	ret = qman_create_cgr(&qipriv.cgr, QMAN_CGR_FLAG_USE_INIT, &opts);
++	if (ret) {
++		dev_err(qidev, "Error %d creating CAAM CGRID: %u\n", ret,
++			qipriv.cgr.cgrid);
++		return ret;
++	}
++
++	dev_dbg(qidev, "Congestion threshold set to %llu\n", val);
++	return 0;
++}
++
++static int alloc_rsp_fqs(struct device *qidev)
++{
++	int ret, i;
++	const cpumask_t *cpus = qman_affine_cpus();
++
++	/*Now create response FQs*/
++	for_each_cpu(i, cpus) {
++		ret = alloc_rsp_fq_cpu(qidev, i);
++		if (ret) {
++			dev_err(qidev, "CAAM rsp FQ alloc failed, cpu: %u", i);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static void free_rsp_fqs(void)
++{
++	int i;
++	const cpumask_t *cpus = qman_affine_cpus();
++
++	for_each_cpu(i, cpus)
++		kfree(per_cpu(pcpu_qipriv.rsp_fq, i));
++}
++
++int caam_qi_init(struct platform_device *caam_pdev)
++{
++	int err, i;
++	struct platform_device *qi_pdev;
++	struct device *ctrldev = &caam_pdev->dev, *qidev;
++	struct caam_drv_private *ctrlpriv;
++	const cpumask_t *cpus = qman_affine_cpus();
++	struct cpumask old_cpumask = current->cpus_allowed;
++	static struct platform_device_info qi_pdev_info = {
++		.name = "caam_qi",
++		.id = PLATFORM_DEVID_NONE
++	};
++
++	/*
++	 * QMAN requires CGRs to be removed from same CPU+portal from where it
++	 * was originally allocated. Hence we need to note down the
++	 * initialisation CPU and use the same CPU for module exit.
++	 * We select the first CPU to from the list of portal owning CPUs.
++	 * Then we pin module init to this CPU.
++	 */
++	mod_init_cpu = cpumask_first(cpus);
++	set_cpus_allowed_ptr(current, get_cpu_mask(mod_init_cpu));
++
++	qi_pdev_info.parent = ctrldev;
++	qi_pdev_info.dma_mask = dma_get_mask(ctrldev);
++	qi_pdev = platform_device_register_full(&qi_pdev_info);
++	if (IS_ERR(qi_pdev))
++		return PTR_ERR(qi_pdev);
++	arch_setup_dma_ops(&qi_pdev->dev, 0, 0, NULL, true);
++
++	ctrlpriv = dev_get_drvdata(ctrldev);
++	qidev = &qi_pdev->dev;
++
++	qipriv.qi_pdev = qi_pdev;
++	dev_set_drvdata(qidev, &qipriv);
++
++	/* Initialize the congestion detection */
++	err = init_cgr(qidev);
++	if (err) {
++		dev_err(qidev, "CGR initialization failed: %d\n", err);
++		platform_device_unregister(qi_pdev);
++		return err;
++	}
++
++	/* Initialise response FQs */
++	err = alloc_rsp_fqs(qidev);
++	if (err) {
++		dev_err(qidev, "Can't allocate CAAM response FQs: %d\n", err);
++		free_rsp_fqs();
++		platform_device_unregister(qi_pdev);
++		return err;
++	}
++
++	/*
++	 * Enable the NAPI contexts on each of the core which has an affine
++	 * portal.
++	 */
++	for_each_cpu(i, cpus) {
++		struct caam_qi_pcpu_priv *priv = per_cpu_ptr(&pcpu_qipriv, i);
++		struct caam_napi *caam_napi = &priv->caam_napi;
++		struct napi_struct *irqtask = &caam_napi->irqtask;
++		struct net_device *net_dev = &priv->net_dev;
++
++		net_dev->dev = *qidev;
++		INIT_LIST_HEAD(&net_dev->napi_list);
++
++		netif_napi_add(net_dev, irqtask, caam_qi_poll,
++			       CAAM_NAPI_WEIGHT);
++
++		napi_enable(irqtask);
++	}
++
++	/* Hook up QI device to parent controlling caam device */
++	ctrlpriv->qidev = qidev;
++
++	qi_cache = kmem_cache_create("caamqicache", CAAM_QI_MEMCACHE_SIZE, 0,
++				     SLAB_CACHE_DMA, NULL);
++	if (!qi_cache) {
++		dev_err(qidev, "Can't allocate CAAM cache\n");
++		free_rsp_fqs();
++		platform_device_unregister(qi_pdev);
++		return -ENOMEM;
++	}
++
++	/* Done with the CGRs; restore the cpus allowed mask */
++	set_cpus_allowed_ptr(current, &old_cpumask);
++#ifdef CONFIG_DEBUG_FS
++	debugfs_create_file("qi_congested", 0444, ctrlpriv->ctl,
++			    &times_congested, &caam_fops_u64_ro);
++#endif
++	dev_info(qidev, "Linux CAAM Queue I/F driver initialised\n");
++	return 0;
++}
+--- /dev/null
++++ b/drivers/crypto/caam/qi.h
+@@ -0,0 +1,204 @@
++/*
++ * Public definitions for the CAAM/QI (Queue Interface) backend.
++ *
++ * Copyright 2013-2016 Freescale Semiconductor, Inc.
++ * Copyright 2016-2017 NXP
++ */
++
++#ifndef __QI_H__
++#define __QI_H__
++
++#include <linux/fsl_qman.h>
++#include "compat.h"
++#include "desc.h"
++#include "desc_constr.h"
++
++/*
++ * CAAM hardware constructs a job descriptor which points to a shared descriptor
++ * (as pointed by context_a of to-CAAM FQ).
++ * When the job descriptor is executed by DECO, the whole job descriptor
++ * together with shared descriptor gets loaded in DECO buffer, which is
++ * 64 words (each 32-bit) long.
++ *
++ * The job descriptor constructed by CAAM hardware has the following layout:
++ *
++ *	HEADER		(1 word)
++ *	Shdesc ptr	(1 or 2 words)
++ *	SEQ_OUT_PTR	(1 word)
++ *	Out ptr		(1 or 2 words)
++ *	Out length	(1 word)
++ *	SEQ_IN_PTR	(1 word)
++ *	In ptr		(1 or 2 words)
++ *	In length	(1 word)
++ *
++ * The shdesc ptr is used to fetch shared descriptor contents into DECO buffer.
++ *
++ * Apart from shdesc contents, the total number of words that get loaded in DECO
++ * buffer are '8' or '11'. The remaining words in DECO buffer can be used for
++ * storing shared descriptor.
++ */
++#define MAX_SDLEN	((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
++
++/* Length of a single buffer in the QI driver memory cache */
++#define CAAM_QI_MEMCACHE_SIZE	768
++
++extern bool caam_congested __read_mostly;
++
++/*
++ * This is the request structure the driver application should fill while
++ * submitting a job to driver.
++ */
++struct caam_drv_req;
++
++/*
++ * caam_qi_cbk - application's callback function invoked by the driver when the
++ *               request has been successfully processed.
++ * @drv_req: original request that was submitted
++ * @status: completion status of request (0 - success, non-zero - error code)
++ */
++typedef void (*caam_qi_cbk)(struct caam_drv_req *drv_req, u32 status);
++
++enum optype {
++	ENCRYPT,
++	DECRYPT,
++	GIVENCRYPT,
++	NUM_OP
++};
++
++/**
++ * caam_drv_ctx - CAAM/QI backend driver context
++ *
++ * The jobs are processed by the driver against a driver context.
++ * With every cryptographic context, a driver context is attached.
++ * The driver context contains data for private use by driver.
++ * For the applications, this is an opaque structure.
++ *
++ * @prehdr: preheader placed before shrd desc
++ * @sh_desc: shared descriptor
++ * @context_a: shared descriptor dma address
++ * @req_fq: to-CAAM request frame queue
++ * @rsp_fq: from-CAAM response frame queue
++ * @cpu: cpu on which to receive CAAM response
++ * @op_type: operation type
++ * @qidev: device pointer for CAAM/QI backend
++ */
++struct caam_drv_ctx {
++	u32 prehdr[2];
++	u32 sh_desc[MAX_SDLEN];
++	dma_addr_t context_a;
++	struct qman_fq *req_fq;
++	struct qman_fq *rsp_fq;
++	int cpu;
++	enum optype op_type;
++	struct device *qidev;
++} ____cacheline_aligned;
++
++/**
++ * caam_drv_req - The request structure the driver application should fill while
++ *                submitting a job to driver.
++ * @fd_sgt: QMan S/G pointing to output (fd_sgt[0]) and input (fd_sgt[1])
++ *          buffers.
++ * @cbk: callback function to invoke when job is completed
++ * @app_ctx: arbitrary context attached with request by the application
++ *
++ * The fields mentioned below should not be used by application.
++ * These are for private use by driver.
++ *
++ * @hdr__: linked list header to maintain list of outstanding requests to CAAM
++ * @hwaddr: DMA address for the S/G table.
++ */
++struct caam_drv_req {
++	struct qm_sg_entry fd_sgt[2];
++	struct caam_drv_ctx *drv_ctx;
++	caam_qi_cbk cbk;
++	void *app_ctx;
++} ____cacheline_aligned;
++
++/**
++ * caam_drv_ctx_init - Initialise a CAAM/QI driver context
++ *
++ * A CAAM/QI driver context must be attached with each cryptographic context.
++ * This function allocates memory for CAAM/QI context and returns a handle to
++ * the application. This handle must be submitted along with each enqueue
++ * request to the driver by the application.
++ *
++ * @cpu: CPU where the application prefers to the driver to receive CAAM
++ *       responses. The request completion callback would be issued from this
++ *       CPU.
++ * @sh_desc: shared descriptor pointer to be attached with CAAM/QI driver
++ *           context.
++ *
++ * Returns a driver context on success or negative error code on failure.
++ */
++struct caam_drv_ctx *caam_drv_ctx_init(struct device *qidev, int *cpu,
++				       u32 *sh_desc);
++
++/**
++ * caam_qi_enqueue - Submit a request to QI backend driver.
++ *
++ * The request structure must be properly filled as described above.
++ *
++ * @qidev: device pointer for QI backend
++ * @req: CAAM QI request structure
++ *
++ * Returns 0 on success or negative error code on failure.
++ */
++int caam_qi_enqueue(struct device *qidev, struct caam_drv_req *req);
++
++/**
++ * caam_drv_ctx_busy - Check if there are too many jobs pending with CAAM
++ *		       or too many CAAM responses are pending to be processed.
++ * @drv_ctx: driver context for which job is to be submitted
++ *
++ * Returns caam congestion status 'true/false'
++ */
++bool caam_drv_ctx_busy(struct caam_drv_ctx *drv_ctx);
++
++/**
++ * caam_drv_ctx_update - Update QI driver context
++ *
++ * Invoked when shared descriptor is required to be change in driver context.
++ *
++ * @drv_ctx: driver context to be updated
++ * @sh_desc: new shared descriptor pointer to be updated in QI driver context
++ *
++ * Returns 0 on success or negative error code on failure.
++ */
++int caam_drv_ctx_update(struct caam_drv_ctx *drv_ctx, u32 *sh_desc);
++
++/**
++ * caam_drv_ctx_rel - Release a QI driver context
++ * @drv_ctx: context to be released
++ */
++void caam_drv_ctx_rel(struct caam_drv_ctx *drv_ctx);
++
++int caam_qi_init(struct platform_device *pdev);
++int caam_qi_shutdown(struct device *dev);
++
++/**
++ * qi_cache_alloc - Allocate buffers from CAAM-QI cache
++ *
++ * Invoked when a user of the CAAM-QI (i.e. caamalg-qi) needs data which has
++ * to be allocated on the hotpath. Instead of using malloc, one can use the
++ * services of the CAAM QI memory cache (backed by kmem_cache). The buffers
++ * will have a size of 256B, which is sufficient for hosting 16 SG entries.
++ *
++ * @flags: flags that would be used for the equivalent malloc(..) call
++ *
++ * Returns a pointer to a retrieved buffer on success or NULL on failure.
++ */
++void *qi_cache_alloc(gfp_t flags);
++
++/**
++ * qi_cache_free - Frees buffers allocated from CAAM-QI cache
++ *
++ * Invoked when a user of the CAAM-QI (i.e. caamalg-qi) no longer needs
++ * the buffer previously allocated by a qi_cache_alloc call.
++ * No checking is being done, the call is a passthrough call to
++ * kmem_cache_free(...)
++ *
++ * @obj: object previously allocated using qi_cache_alloc()
++ */
++void qi_cache_free(void *obj);
++
++#endif /* __QI_H__ */
+--- a/drivers/crypto/caam/regs.h
++++ b/drivers/crypto/caam/regs.h
+@@ -2,6 +2,7 @@
+  * CAAM hardware register-level view
+  *
+  * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
+  */
+ 
+ #ifndef REGS_H
+@@ -67,6 +68,7 @@
+  */
+ 
+ extern bool caam_little_end;
++extern bool caam_imx;
+ 
+ #define caam_to_cpu(len)						\
+ static inline u##len caam##len ## _to_cpu(u##len val)			\
+@@ -154,13 +156,10 @@ static inline u64 rd_reg64(void __iomem
+ #else /* CONFIG_64BIT */
+ static inline void wr_reg64(void __iomem *reg, u64 data)
+ {
+-#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
+-	if (caam_little_end) {
++	if (!caam_imx && caam_little_end) {
+ 		wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
+ 		wr_reg32((u32 __iomem *)(reg), data);
+-	} else
+-#endif
+-	{
++	} else {
+ 		wr_reg32((u32 __iomem *)(reg), data >> 32);
+ 		wr_reg32((u32 __iomem *)(reg) + 1, data);
+ 	}
+@@ -168,41 +167,40 @@ static inline void wr_reg64(void __iomem
+ 
+ static inline u64 rd_reg64(void __iomem *reg)
+ {
+-#ifndef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
+-	if (caam_little_end)
++	if (!caam_imx && caam_little_end)
+ 		return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
+ 			(u64)rd_reg32((u32 __iomem *)(reg)));
+-	else
+-#endif
+-		return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
+-			(u64)rd_reg32((u32 __iomem *)(reg) + 1));
++
++	return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
++		(u64)rd_reg32((u32 __iomem *)(reg) + 1));
+ }
+ #endif /* CONFIG_64BIT  */
+ 
++static inline u64 cpu_to_caam_dma64(dma_addr_t value)
++{
++	if (caam_imx)
++		return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
++			 (u64)cpu_to_caam32(upper_32_bits(value)));
++
++	return cpu_to_caam64(value);
++}
++
++static inline u64 caam_dma64_to_cpu(u64 value)
++{
++	if (caam_imx)
++		return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
++			 (u64)caam32_to_cpu(upper_32_bits(value)));
++
++	return caam64_to_cpu(value);
++}
++
+ #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+-#ifdef CONFIG_SOC_IMX7D
+-#define cpu_to_caam_dma(value) \
+-		(((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
+-		  (u64)cpu_to_caam32(upper_32_bits(value)))
+-#define caam_dma_to_cpu(value) \
+-		(((u64)caam32_to_cpu(lower_32_bits(value)) << 32) | \
+-		  (u64)caam32_to_cpu(upper_32_bits(value)))
+-#else
+-#define cpu_to_caam_dma(value) cpu_to_caam64(value)
+-#define caam_dma_to_cpu(value) caam64_to_cpu(value)
+-#endif /* CONFIG_SOC_IMX7D */
++#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
++#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
+ #else
+ #define cpu_to_caam_dma(value) cpu_to_caam32(value)
+ #define caam_dma_to_cpu(value) caam32_to_cpu(value)
+-#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT  */
+-
+-#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
+-#define cpu_to_caam_dma64(value) \
+-		(((u64)cpu_to_caam32(lower_32_bits(value)) << 32) | \
+-		 (u64)cpu_to_caam32(upper_32_bits(value)))
+-#else
+-#define cpu_to_caam_dma64(value) cpu_to_caam64(value)
+-#endif
++#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
+ 
+ /*
+  * jr_outentry
+@@ -293,6 +291,7 @@ struct caam_perfmon {
+ 	u32 cha_rev_ls;		/* CRNR - CHA Rev No. Least significant half*/
+ #define CTPR_MS_QI_SHIFT	25
+ #define CTPR_MS_QI_MASK		(0x1ull << CTPR_MS_QI_SHIFT)
++#define CTPR_MS_DPAA2		BIT(13)
+ #define CTPR_MS_VIRT_EN_INCL	0x00000001
+ #define CTPR_MS_VIRT_EN_POR	0x00000002
+ #define CTPR_MS_PG_SZ_MASK	0x10
+@@ -628,6 +627,8 @@ struct caam_job_ring {
+ #define JRSTA_DECOERR_INVSIGN       0x86
+ #define JRSTA_DECOERR_DSASIGN       0x87
+ 
++#define JRSTA_QIERR_ERROR_MASK      0x00ff
++
+ #define JRSTA_CCBERR_JUMP           0x08000000
+ #define JRSTA_CCBERR_INDEX_MASK     0xff00
+ #define JRSTA_CCBERR_INDEX_SHIFT    8
+--- /dev/null
++++ b/drivers/crypto/caam/sg_sw_qm.h
+@@ -0,0 +1,126 @@
++/*
++ * Copyright 2013-2016 Freescale Semiconductor, Inc.
++ * Copyright 2016-2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *       notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *       notice, this list of conditions and the following disclaimer in the
++ *       documentation and/or other materials provided with the distribution.
++ *     * Neither the name of Freescale Semiconductor nor the
++ *       names of its contributors may be used to endorse or promote products
++ *       derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
++ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __SG_SW_QM_H
++#define __SG_SW_QM_H
++
++#include <linux/fsl_qman.h>
++#include "regs.h"
++
++static inline void cpu_to_hw_sg(struct qm_sg_entry *qm_sg_ptr)
++{
++	dma_addr_t addr = qm_sg_ptr->opaque;
++
++	qm_sg_ptr->opaque = cpu_to_caam64(addr);
++	qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl);
++}
++
++static inline void __dma_to_qm_sg(struct qm_sg_entry *qm_sg_ptr, dma_addr_t dma,
++				  u32 len, u16 offset)
++{
++	qm_sg_ptr->addr = dma;
++	qm_sg_ptr->length = len;
++	qm_sg_ptr->__reserved2 = 0;
++	qm_sg_ptr->bpid = 0;
++	qm_sg_ptr->__reserved3 = 0;
++	qm_sg_ptr->offset = offset & QM_SG_OFFSET_MASK;
++
++	cpu_to_hw_sg(qm_sg_ptr);
++}
++
++static inline void dma_to_qm_sg_one(struct qm_sg_entry *qm_sg_ptr,
++				    dma_addr_t dma, u32 len, u16 offset)
++{
++	qm_sg_ptr->extension = 0;
++	qm_sg_ptr->final = 0;
++	__dma_to_qm_sg(qm_sg_ptr, dma, len, offset);
++}
++
++static inline void dma_to_qm_sg_one_last(struct qm_sg_entry *qm_sg_ptr,
++					 dma_addr_t dma, u32 len, u16 offset)
++{
++	qm_sg_ptr->extension = 0;
++	qm_sg_ptr->final = 1;
++	__dma_to_qm_sg(qm_sg_ptr, dma, len, offset);
++}
++
++static inline void dma_to_qm_sg_one_ext(struct qm_sg_entry *qm_sg_ptr,
++					dma_addr_t dma, u32 len, u16 offset)
++{
++	qm_sg_ptr->extension = 1;
++	qm_sg_ptr->final = 0;
++	__dma_to_qm_sg(qm_sg_ptr, dma, len, offset);
++}
++
++static inline void dma_to_qm_sg_one_last_ext(struct qm_sg_entry *qm_sg_ptr,
++					     dma_addr_t dma, u32 len,
++					     u16 offset)
++{
++	qm_sg_ptr->extension = 1;
++	qm_sg_ptr->final = 1;
++	__dma_to_qm_sg(qm_sg_ptr, dma, len, offset);
++}
++
++/*
++ * convert scatterlist to h/w link table format
++ * but does not have final bit; instead, returns last entry
++ */
++static inline struct qm_sg_entry *
++sg_to_qm_sg(struct scatterlist *sg, int sg_count,
++	    struct qm_sg_entry *qm_sg_ptr, u16 offset)
++{
++	while (sg_count && sg) {
++		dma_to_qm_sg_one(qm_sg_ptr, sg_dma_address(sg),
++				 sg_dma_len(sg), offset);
++		qm_sg_ptr++;
++		sg = sg_next(sg);
++		sg_count--;
++	}
++	return qm_sg_ptr - 1;
++}
++
++/*
++ * convert scatterlist to h/w link table format
++ * scatterlist must have been previously dma mapped
++ */
++static inline void sg_to_qm_sg_last(struct scatterlist *sg, int sg_count,
++				    struct qm_sg_entry *qm_sg_ptr, u16 offset)
++{
++	qm_sg_ptr = sg_to_qm_sg(sg, sg_count, qm_sg_ptr, offset);
++
++	qm_sg_ptr->sgt_efl = caam32_to_cpu(qm_sg_ptr->sgt_efl);
++	qm_sg_ptr->final = 1;
++	qm_sg_ptr->sgt_efl = cpu_to_caam32(qm_sg_ptr->sgt_efl);
++}
++
++#endif /* __SG_SW_QM_H */
+--- /dev/null
++++ b/drivers/crypto/caam/sg_sw_qm2.h
+@@ -0,0 +1,81 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *     * Redistributions of source code must retain the above copyright
++ *	 notice, this list of conditions and the following disclaimer.
++ *     * Redistributions in binary form must reproduce the above copyright
++ *	 notice, this list of conditions and the following disclaimer in the
++ *	 documentation and/or other materials provided with the distribution.
++ *     * Neither the names of the above-listed copyright holders nor the
++ *	 names of any contributors may be used to endorse or promote products
++ *	 derived from this software without specific prior written permission.
++ *
++ *
++ * ALTERNATIVELY, this software may be distributed under the terms of the
++ * GNU General Public License ("GPL") as published by the Free Software
++ * Foundation, either version 2 of that License or (at your option) any
++ * later version.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef _SG_SW_QM2_H_
++#define _SG_SW_QM2_H_
++
++#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
++
++static inline void dma_to_qm_sg_one(struct dpaa2_sg_entry *qm_sg_ptr,
++				    dma_addr_t dma, u32 len, u16 offset)
++{
++	dpaa2_sg_set_addr(qm_sg_ptr, dma);
++	dpaa2_sg_set_format(qm_sg_ptr, dpaa2_sg_single);
++	dpaa2_sg_set_final(qm_sg_ptr, false);
++	dpaa2_sg_set_len(qm_sg_ptr, len);
++	dpaa2_sg_set_bpid(qm_sg_ptr, 0);
++	dpaa2_sg_set_offset(qm_sg_ptr, offset);
++}
++
++/*
++ * convert scatterlist to h/w link table format
++ * but does not have final bit; instead, returns last entry
++ */
++static inline struct dpaa2_sg_entry *
++sg_to_qm_sg(struct scatterlist *sg, int sg_count,
++	    struct dpaa2_sg_entry *qm_sg_ptr, u16 offset)
++{
++	while (sg_count && sg) {
++		dma_to_qm_sg_one(qm_sg_ptr, sg_dma_address(sg),
++				 sg_dma_len(sg), offset);
++		qm_sg_ptr++;
++		sg = sg_next(sg);
++		sg_count--;
++	}
++	return qm_sg_ptr - 1;
++}
++
++/*
++ * convert scatterlist to h/w link table format
++ * scatterlist must have been previously dma mapped
++ */
++static inline void sg_to_qm_sg_last(struct scatterlist *sg, int sg_count,
++				    struct dpaa2_sg_entry *qm_sg_ptr,
++				    u16 offset)
++{
++	qm_sg_ptr = sg_to_qm_sg(sg, sg_count, qm_sg_ptr, offset);
++	dpaa2_sg_set_final(qm_sg_ptr, true);
++}
++
++#endif /* _SG_SW_QM2_H_ */
+--- a/drivers/crypto/caam/sg_sw_sec4.h
++++ b/drivers/crypto/caam/sg_sw_sec4.h
+@@ -5,9 +5,19 @@
+  *
+  */
+ 
++#ifndef _SG_SW_SEC4_H_
++#define _SG_SW_SEC4_H_
++
++#include "ctrl.h"
+ #include "regs.h"
++#include "sg_sw_qm2.h"
++#include "../../../drivers/staging/fsl-mc/include/dpaa2-fd.h"
+ 
+-struct sec4_sg_entry;
++struct sec4_sg_entry {
++	u64 ptr;
++	u32 len;
++	u32 bpid_offset;
++};
+ 
+ /*
+  * convert single dma address to h/w link table format
+@@ -15,9 +25,15 @@ struct sec4_sg_entry;
+ static inline void dma_to_sec4_sg_one(struct sec4_sg_entry *sec4_sg_ptr,
+ 				      dma_addr_t dma, u32 len, u16 offset)
+ {
+-	sec4_sg_ptr->ptr = cpu_to_caam_dma64(dma);
+-	sec4_sg_ptr->len = cpu_to_caam32(len);
+-	sec4_sg_ptr->bpid_offset = cpu_to_caam32(offset & SEC4_SG_OFFSET_MASK);
++	if (caam_dpaa2) {
++		dma_to_qm_sg_one((struct dpaa2_sg_entry *)sec4_sg_ptr, dma, len,
++				 offset);
++	} else {
++		sec4_sg_ptr->ptr = cpu_to_caam_dma64(dma);
++		sec4_sg_ptr->len = cpu_to_caam32(len);
++		sec4_sg_ptr->bpid_offset = cpu_to_caam32(offset &
++							 SEC4_SG_OFFSET_MASK);
++	}
+ #ifdef DEBUG
+ 	print_hex_dump(KERN_ERR, "sec4_sg_ptr@: ",
+ 		       DUMP_PREFIX_ADDRESS, 16, 4, sec4_sg_ptr,
+@@ -43,6 +59,14 @@ sg_to_sec4_sg(struct scatterlist *sg, in
+ 	return sec4_sg_ptr - 1;
+ }
+ 
++static inline void sg_to_sec4_set_last(struct sec4_sg_entry *sec4_sg_ptr)
++{
++	if (caam_dpaa2)
++		dpaa2_sg_set_final((struct dpaa2_sg_entry *)sec4_sg_ptr, true);
++	else
++		sec4_sg_ptr->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
++}
++
+ /*
+  * convert scatterlist to h/w link table format
+  * scatterlist must have been previously dma mapped
+@@ -52,31 +76,7 @@ static inline void sg_to_sec4_sg_last(st
+ 				      u16 offset)
+ {
+ 	sec4_sg_ptr = sg_to_sec4_sg(sg, sg_count, sec4_sg_ptr, offset);
+-	sec4_sg_ptr->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
+-}
+-
+-static inline struct sec4_sg_entry *sg_to_sec4_sg_len(
+-	struct scatterlist *sg, unsigned int total,
+-	struct sec4_sg_entry *sec4_sg_ptr)
+-{
+-	do {
+-		unsigned int len = min(sg_dma_len(sg), total);
+-
+-		dma_to_sec4_sg_one(sec4_sg_ptr, sg_dma_address(sg), len, 0);
+-		sec4_sg_ptr++;
+-		sg = sg_next(sg);
+-		total -= len;
+-	} while (total);
+-	return sec4_sg_ptr - 1;
++	sg_to_sec4_set_last(sec4_sg_ptr);
+ }
+ 
+-/* derive number of elements in scatterlist, but return 0 for 1 */
+-static inline int sg_count(struct scatterlist *sg_list, int nbytes)
+-{
+-	int sg_nents = sg_nents_for_len(sg_list, nbytes);
+-
+-	if (likely(sg_nents == 1))
+-		return 0;
+-
+-	return sg_nents;
+-}
++#endif /* _SG_SW_SEC4_H_ */
+--- a/drivers/crypto/talitos.c
++++ b/drivers/crypto/talitos.c
+@@ -1241,6 +1241,14 @@ static int ipsec_esp(struct talitos_edes
+ 	ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
+ 				 sg_count, areq->assoclen, tbl_off, elen);
+ 
++	/*
++	 * In case of SEC 2.x+, cipher in len must include only the ciphertext,
++	 * while extent is used for ICV len.
++	 */
++	if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
++	    (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
++		desc->ptr[4].len = cpu_to_be16(cryptlen);
++
+ 	if (ret > 1) {
+ 		tbl_off += ret;
+ 		sync_needed = true;
+--- a/drivers/net/wireless/rsi/rsi_91x_usb.c
++++ b/drivers/net/wireless/rsi/rsi_91x_usb.c
+@@ -516,7 +516,7 @@ err:
+ 
+ /**
+  * rsi_disconnect() - This function performs the reverse of the probe function,
+- *		      it deintialize the driver structure.
++ *		      it deinitialize the driver structure.
+  * @pfunction: Pointer to the USB interface structure.
+  *
+  * Return: None.
+--- a/drivers/staging/wilc1000/linux_wlan.c
++++ b/drivers/staging/wilc1000/linux_wlan.c
+@@ -211,7 +211,7 @@ static void deinit_irq(struct net_device
+ 	vif = netdev_priv(dev);
+ 	wilc = vif->wilc;
+ 
+-	/* Deintialize IRQ */
++	/* Deinitialize IRQ */
+ 	if (wilc->dev_irq_num) {
+ 		free_irq(wilc->dev_irq_num, wilc);
+ 		gpio_free(wilc->gpio);
+--- a/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c
++++ b/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c
+@@ -2359,7 +2359,7 @@ int wilc_deinit_host_int(struct net_devi
+ 		del_timer_sync(&wilc_during_ip_timer);
+ 
+ 	if (s32Error)
+-		netdev_err(net, "Error while deintializing host interface\n");
++		netdev_err(net, "Error while deinitializing host interface\n");
+ 
+ 	return s32Error;
+ }
+--- /dev/null
++++ b/include/crypto/acompress.h
+@@ -0,0 +1,269 @@
++/*
++ * Asynchronous Compression operations
++ *
++ * Copyright (c) 2016, Intel Corporation
++ * Authors: Weigang Li <weigang.li@intel.com>
++ *          Giovanni Cabiddu <giovanni.cabiddu@intel.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; either version 2 of the License, or (at your option)
++ * any later version.
++ *
++ */
++#ifndef _CRYPTO_ACOMP_H
++#define _CRYPTO_ACOMP_H
++#include <linux/crypto.h>
++
++#define CRYPTO_ACOMP_ALLOC_OUTPUT	0x00000001
++
++/**
++ * struct acomp_req - asynchronous (de)compression request
++ *
++ * @base:	Common attributes for asynchronous crypto requests
++ * @src:	Source Data
++ * @dst:	Destination data
++ * @slen:	Size of the input buffer
++ * @dlen:	Size of the output buffer and number of bytes produced
++ * @flags:	Internal flags
++ * @__ctx:	Start of private context data
++ */
++struct acomp_req {
++	struct crypto_async_request base;
++	struct scatterlist *src;
++	struct scatterlist *dst;
++	unsigned int slen;
++	unsigned int dlen;
++	u32 flags;
++	void *__ctx[] CRYPTO_MINALIGN_ATTR;
++};
++
++/**
++ * struct crypto_acomp - user-instantiated objects which encapsulate
++ * algorithms and core processing logic
++ *
++ * @compress:		Function performs a compress operation
++ * @decompress:		Function performs a de-compress operation
++ * @dst_free:		Frees destination buffer if allocated inside the
++ *			algorithm
++ * @reqsize:		Context size for (de)compression requests
++ * @base:		Common crypto API algorithm data structure
++ */
++struct crypto_acomp {
++	int (*compress)(struct acomp_req *req);
++	int (*decompress)(struct acomp_req *req);
++	void (*dst_free)(struct scatterlist *dst);
++	unsigned int reqsize;
++	struct crypto_tfm base;
++};
++
++/**
++ * struct acomp_alg - asynchronous compression algorithm
++ *
++ * @compress:	Function performs a compress operation
++ * @decompress:	Function performs a de-compress operation
++ * @dst_free:	Frees destination buffer if allocated inside the algorithm
++ * @init:	Initialize the cryptographic transformation object.
++ *		This function is used to initialize the cryptographic
++ *		transformation object. This function is called only once at
++ *		the instantiation time, right after the transformation context
++ *		was allocated. In case the cryptographic hardware has some
++ *		special requirements which need to be handled by software, this
++ *		function shall check for the precise requirement of the
++ *		transformation and put any software fallbacks in place.
++ * @exit:	Deinitialize the cryptographic transformation object. This is a
++ *		counterpart to @init, used to remove various changes set in
++ *		@init.
++ *
++ * @reqsize:	Context size for (de)compression requests
++ * @base:	Common crypto API algorithm data structure
++ */
++struct acomp_alg {
++	int (*compress)(struct acomp_req *req);
++	int (*decompress)(struct acomp_req *req);
++	void (*dst_free)(struct scatterlist *dst);
++	int (*init)(struct crypto_acomp *tfm);
++	void (*exit)(struct crypto_acomp *tfm);
++	unsigned int reqsize;
++	struct crypto_alg base;
++};
++
++/**
++ * DOC: Asynchronous Compression API
++ *
++ * The Asynchronous Compression API is used with the algorithms of type
++ * CRYPTO_ALG_TYPE_ACOMPRESS (listed as type "acomp" in /proc/crypto)
++ */
++
++/**
++ * crypto_alloc_acomp() -- allocate ACOMPRESS tfm handle
++ * @alg_name:	is the cra_name / name or cra_driver_name / driver name of the
++ *		compression algorithm e.g. "deflate"
++ * @type:	specifies the type of the algorithm
++ * @mask:	specifies the mask for the algorithm
++ *
++ * Allocate a handle for a compression algorithm. The returned struct
++ * crypto_acomp is the handle that is required for any subsequent
++ * API invocation for the compression operations.
++ *
++ * Return:	allocated handle in case of success; IS_ERR() is true in case
++ *		of an error, PTR_ERR() returns the error code.
++ */
++struct crypto_acomp *crypto_alloc_acomp(const char *alg_name, u32 type,
++					u32 mask);
++
++static inline struct crypto_tfm *crypto_acomp_tfm(struct crypto_acomp *tfm)
++{
++	return &tfm->base;
++}
++
++static inline struct acomp_alg *__crypto_acomp_alg(struct crypto_alg *alg)
++{
++	return container_of(alg, struct acomp_alg, base);
++}
++
++static inline struct crypto_acomp *__crypto_acomp_tfm(struct crypto_tfm *tfm)
++{
++	return container_of(tfm, struct crypto_acomp, base);
++}
++
++static inline struct acomp_alg *crypto_acomp_alg(struct crypto_acomp *tfm)
++{
++	return __crypto_acomp_alg(crypto_acomp_tfm(tfm)->__crt_alg);
++}
++
++static inline unsigned int crypto_acomp_reqsize(struct crypto_acomp *tfm)
++{
++	return tfm->reqsize;
++}
++
++static inline void acomp_request_set_tfm(struct acomp_req *req,
++					 struct crypto_acomp *tfm)
++{
++	req->base.tfm = crypto_acomp_tfm(tfm);
++}
++
++static inline struct crypto_acomp *crypto_acomp_reqtfm(struct acomp_req *req)
++{
++	return __crypto_acomp_tfm(req->base.tfm);
++}
++
++/**
++ * crypto_free_acomp() -- free ACOMPRESS tfm handle
++ *
++ * @tfm:	ACOMPRESS tfm handle allocated with crypto_alloc_acomp()
++ */
++static inline void crypto_free_acomp(struct crypto_acomp *tfm)
++{
++	crypto_destroy_tfm(tfm, crypto_acomp_tfm(tfm));
++}
++
++static inline int crypto_has_acomp(const char *alg_name, u32 type, u32 mask)
++{
++	type &= ~CRYPTO_ALG_TYPE_MASK;
++	type |= CRYPTO_ALG_TYPE_ACOMPRESS;
++	mask |= CRYPTO_ALG_TYPE_MASK;
++
++	return crypto_has_alg(alg_name, type, mask);
++}
++
++/**
++ * acomp_request_alloc() -- allocates asynchronous (de)compression request
++ *
++ * @tfm:	ACOMPRESS tfm handle allocated with crypto_alloc_acomp()
++ *
++ * Return:	allocated handle in case of success or NULL in case of an error
++ */
++struct acomp_req *acomp_request_alloc(struct crypto_acomp *tfm);
++
++/**
++ * acomp_request_free() -- zeroize and free asynchronous (de)compression
++ *			   request as well as the output buffer if allocated
++ *			   inside the algorithm
++ *
++ * @req:	request to free
++ */
++void acomp_request_free(struct acomp_req *req);
++
++/**
++ * acomp_request_set_callback() -- Sets an asynchronous callback
++ *
++ * Callback will be called when an asynchronous operation on a given
++ * request is finished.
++ *
++ * @req:	request that the callback will be set for
++ * @flgs:	specify for instance if the operation may backlog
++ * @cmlp:	callback which will be called
++ * @data:	private data used by the caller
++ */
++static inline void acomp_request_set_callback(struct acomp_req *req,
++					      u32 flgs,
++					      crypto_completion_t cmpl,
++					      void *data)
++{
++	req->base.complete = cmpl;
++	req->base.data = data;
++	req->base.flags = flgs;
++}
++
++/**
++ * acomp_request_set_params() -- Sets request parameters
++ *
++ * Sets parameters required by an acomp operation
++ *
++ * @req:	asynchronous compress request
++ * @src:	pointer to input buffer scatterlist
++ * @dst:	pointer to output buffer scatterlist. If this is NULL, the
++ *		acomp layer will allocate the output memory
++ * @slen:	size of the input buffer
++ * @dlen:	size of the output buffer. If dst is NULL, this can be used by
++ *		the user to specify the maximum amount of memory to allocate
++ */
++static inline void acomp_request_set_params(struct acomp_req *req,
++					    struct scatterlist *src,
++					    struct scatterlist *dst,
++					    unsigned int slen,
++					    unsigned int dlen)
++{
++	req->src = src;
++	req->dst = dst;
++	req->slen = slen;
++	req->dlen = dlen;
++
++	if (!req->dst)
++		req->flags |= CRYPTO_ACOMP_ALLOC_OUTPUT;
++}
++
++/**
++ * crypto_acomp_compress() -- Invoke asynchronous compress operation
++ *
++ * Function invokes the asynchronous compress operation
++ *
++ * @req:	asynchronous compress request
++ *
++ * Return:	zero on success; error code in case of error
++ */
++static inline int crypto_acomp_compress(struct acomp_req *req)
++{
++	struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
++
++	return tfm->compress(req);
++}
++
++/**
++ * crypto_acomp_decompress() -- Invoke asynchronous decompress operation
++ *
++ * Function invokes the asynchronous decompress operation
++ *
++ * @req:	asynchronous compress request
++ *
++ * Return:	zero on success; error code in case of error
++ */
++static inline int crypto_acomp_decompress(struct acomp_req *req)
++{
++	struct crypto_acomp *tfm = crypto_acomp_reqtfm(req);
++
++	return tfm->decompress(req);
++}
++
++#endif
+--- /dev/null
++++ b/include/crypto/internal/acompress.h
+@@ -0,0 +1,81 @@
++/*
++ * Asynchronous Compression operations
++ *
++ * Copyright (c) 2016, Intel Corporation
++ * Authors: Weigang Li <weigang.li@intel.com>
++ *          Giovanni Cabiddu <giovanni.cabiddu@intel.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; either version 2 of the License, or (at your option)
++ * any later version.
++ *
++ */
++#ifndef _CRYPTO_ACOMP_INT_H
++#define _CRYPTO_ACOMP_INT_H
++#include <crypto/acompress.h>
++
++/*
++ * Transform internal helpers.
++ */
++static inline void *acomp_request_ctx(struct acomp_req *req)
++{
++	return req->__ctx;
++}
++
++static inline void *acomp_tfm_ctx(struct crypto_acomp *tfm)
++{
++	return tfm->base.__crt_ctx;
++}
++
++static inline void acomp_request_complete(struct acomp_req *req,
++					  int err)
++{
++	req->base.complete(&req->base, err);
++}
++
++static inline const char *acomp_alg_name(struct crypto_acomp *tfm)
++{
++	return crypto_acomp_tfm(tfm)->__crt_alg->cra_name;
++}
++
++static inline struct acomp_req *__acomp_request_alloc(struct crypto_acomp *tfm)
++{
++	struct acomp_req *req;
++
++	req = kzalloc(sizeof(*req) + crypto_acomp_reqsize(tfm), GFP_KERNEL);
++	if (likely(req))
++		acomp_request_set_tfm(req, tfm);
++	return req;
++}
++
++static inline void __acomp_request_free(struct acomp_req *req)
++{
++	kzfree(req);
++}
++
++/**
++ * crypto_register_acomp() -- Register asynchronous compression algorithm
++ *
++ * Function registers an implementation of an asynchronous
++ * compression algorithm
++ *
++ * @alg:	algorithm definition
++ *
++ * Return:	zero on success; error code in case of error
++ */
++int crypto_register_acomp(struct acomp_alg *alg);
++
++/**
++ * crypto_unregister_acomp() -- Unregister asynchronous compression algorithm
++ *
++ * Function unregisters an implementation of an asynchronous
++ * compression algorithm
++ *
++ * @alg:	algorithm definition
++ *
++ * Return:	zero on success; error code in case of error
++ */
++int crypto_unregister_acomp(struct acomp_alg *alg);
++
++#endif
+--- /dev/null
++++ b/include/crypto/internal/scompress.h
+@@ -0,0 +1,136 @@
++/*
++ * Synchronous Compression operations
++ *
++ * Copyright 2015 LG Electronics Inc.
++ * Copyright (c) 2016, Intel Corporation
++ * Author: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; either version 2 of the License, or (at your option)
++ * any later version.
++ *
++ */
++#ifndef _CRYPTO_SCOMP_INT_H
++#define _CRYPTO_SCOMP_INT_H
++#include <linux/crypto.h>
++
++#define SCOMP_SCRATCH_SIZE	131072
++
++struct crypto_scomp {
++	struct crypto_tfm base;
++};
++
++/**
++ * struct scomp_alg - synchronous compression algorithm
++ *
++ * @alloc_ctx:	Function allocates algorithm specific context
++ * @free_ctx:	Function frees context allocated with alloc_ctx
++ * @compress:	Function performs a compress operation
++ * @decompress:	Function performs a de-compress operation
++ * @init:	Initialize the cryptographic transformation object.
++ *		This function is used to initialize the cryptographic
++ *		transformation object. This function is called only once at
++ *		the instantiation time, right after the transformation context
++ *		was allocated. In case the cryptographic hardware has some
++ *		special requirements which need to be handled by software, this
++ *		function shall check for the precise requirement of the
++ *		transformation and put any software fallbacks in place.
++ * @exit:	Deinitialize the cryptographic transformation object. This is a
++ *		counterpart to @init, used to remove various changes set in
++ *		@init.
++ * @base:	Common crypto API algorithm data structure
++ */
++struct scomp_alg {
++	void *(*alloc_ctx)(struct crypto_scomp *tfm);
++	void (*free_ctx)(struct crypto_scomp *tfm, void *ctx);
++	int (*compress)(struct crypto_scomp *tfm, const u8 *src,
++			unsigned int slen, u8 *dst, unsigned int *dlen,
++			void *ctx);
++	int (*decompress)(struct crypto_scomp *tfm, const u8 *src,
++			  unsigned int slen, u8 *dst, unsigned int *dlen,
++			  void *ctx);
++	struct crypto_alg base;
++};
++
++static inline struct scomp_alg *__crypto_scomp_alg(struct crypto_alg *alg)
++{
++	return container_of(alg, struct scomp_alg, base);
++}
++
++static inline struct crypto_scomp *__crypto_scomp_tfm(struct crypto_tfm *tfm)
++{
++	return container_of(tfm, struct crypto_scomp, base);
++}
++
++static inline struct crypto_tfm *crypto_scomp_tfm(struct crypto_scomp *tfm)
++{
++	return &tfm->base;
++}
++
++static inline void crypto_free_scomp(struct crypto_scomp *tfm)
++{
++	crypto_destroy_tfm(tfm, crypto_scomp_tfm(tfm));
++}
++
++static inline struct scomp_alg *crypto_scomp_alg(struct crypto_scomp *tfm)
++{
++	return __crypto_scomp_alg(crypto_scomp_tfm(tfm)->__crt_alg);
++}
++
++static inline void *crypto_scomp_alloc_ctx(struct crypto_scomp *tfm)
++{
++	return crypto_scomp_alg(tfm)->alloc_ctx(tfm);
++}
++
++static inline void crypto_scomp_free_ctx(struct crypto_scomp *tfm,
++					 void *ctx)
++{
++	return crypto_scomp_alg(tfm)->free_ctx(tfm, ctx);
++}
++
++static inline int crypto_scomp_compress(struct crypto_scomp *tfm,
++					const u8 *src, unsigned int slen,
++					u8 *dst, unsigned int *dlen, void *ctx)
++{
++	return crypto_scomp_alg(tfm)->compress(tfm, src, slen, dst, dlen, ctx);
++}
++
++static inline int crypto_scomp_decompress(struct crypto_scomp *tfm,
++					  const u8 *src, unsigned int slen,
++					  u8 *dst, unsigned int *dlen,
++					  void *ctx)
++{
++	return crypto_scomp_alg(tfm)->decompress(tfm, src, slen, dst, dlen,
++						 ctx);
++}
++
++int crypto_init_scomp_ops_async(struct crypto_tfm *tfm);
++struct acomp_req *crypto_acomp_scomp_alloc_ctx(struct acomp_req *req);
++void crypto_acomp_scomp_free_ctx(struct acomp_req *req);
++
++/**
++ * crypto_register_scomp() -- Register synchronous compression algorithm
++ *
++ * Function registers an implementation of a synchronous
++ * compression algorithm
++ *
++ * @alg:	algorithm definition
++ *
++ * Return: zero on success; error code in case of error
++ */
++int crypto_register_scomp(struct scomp_alg *alg);
++
++/**
++ * crypto_unregister_scomp() -- Unregister synchronous compression algorithm
++ *
++ * Function unregisters an implementation of a synchronous
++ * compression algorithm
++ *
++ * @alg:	algorithm definition
++ *
++ * Return: zero on success; error code in case of error
++ */
++int crypto_unregister_scomp(struct scomp_alg *alg);
++
++#endif
+--- a/include/linux/crypto.h
++++ b/include/linux/crypto.h
+@@ -50,6 +50,8 @@
+ #define CRYPTO_ALG_TYPE_SKCIPHER	0x00000005
+ #define CRYPTO_ALG_TYPE_GIVCIPHER	0x00000006
+ #define CRYPTO_ALG_TYPE_KPP		0x00000008
++#define CRYPTO_ALG_TYPE_ACOMPRESS	0x0000000a
++#define CRYPTO_ALG_TYPE_SCOMPRESS	0x0000000b
+ #define CRYPTO_ALG_TYPE_RNG		0x0000000c
+ #define CRYPTO_ALG_TYPE_AKCIPHER	0x0000000d
+ #define CRYPTO_ALG_TYPE_DIGEST		0x0000000e
+@@ -60,6 +62,7 @@
+ #define CRYPTO_ALG_TYPE_HASH_MASK	0x0000000e
+ #define CRYPTO_ALG_TYPE_AHASH_MASK	0x0000000e
+ #define CRYPTO_ALG_TYPE_BLKCIPHER_MASK	0x0000000c
++#define CRYPTO_ALG_TYPE_ACOMPRESS_MASK	0x0000000e
+ 
+ #define CRYPTO_ALG_LARVAL		0x00000010
+ #define CRYPTO_ALG_DEAD			0x00000020
+--- a/include/uapi/linux/cryptouser.h
++++ b/include/uapi/linux/cryptouser.h
+@@ -46,6 +46,7 @@ enum crypto_attr_type_t {
+ 	CRYPTOCFGA_REPORT_CIPHER,	/* struct crypto_report_cipher */
+ 	CRYPTOCFGA_REPORT_AKCIPHER,	/* struct crypto_report_akcipher */
+ 	CRYPTOCFGA_REPORT_KPP,		/* struct crypto_report_kpp */
++	CRYPTOCFGA_REPORT_ACOMP,	/* struct crypto_report_acomp */
+ 	__CRYPTOCFGA_MAX
+ 
+ #define CRYPTOCFGA_MAX (__CRYPTOCFGA_MAX - 1)
+@@ -112,5 +113,9 @@ struct crypto_report_kpp {
+ 	char type[CRYPTO_MAX_NAME];
+ };
+ 
++struct crypto_report_acomp {
++	char type[CRYPTO_MAX_NAME];
++};
++
+ #define CRYPTO_REPORT_MAXSIZE (sizeof(struct crypto_user_alg) + \
+ 			       sizeof(struct crypto_report_blkcipher))
+--- a/scripts/spelling.txt
++++ b/scripts/spelling.txt
+@@ -305,6 +305,9 @@ defintion||definition
+ defintions||definitions
+ defualt||default
+ defult||default
++deintializing||deinitializing
++deintialize||deinitialize
++deintialized||deinitialized
+ deivce||device
+ delared||declared
+ delare||declare
+--- a/sound/soc/amd/acp-pcm-dma.c
++++ b/sound/soc/amd/acp-pcm-dma.c
+@@ -506,7 +506,7 @@ static int acp_init(void __iomem *acp_mm
+ 	return 0;
+ }
+ 
+-/* Deintialize ACP */
++/* Deinitialize ACP */
+ static int acp_deinit(void __iomem *acp_mmio)
+ {
+ 	u32 val;
diff --git a/target/linux/layerscape/patches-4.14/802-dma-support-layerscape.patch b/target/linux/layerscape/patches-4.9/805-dma-support-layerscape.patch
similarity index 82%
rename from target/linux/layerscape/patches-4.14/802-dma-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/805-dma-support-layerscape.patch
index aee4ae294..fb42fdaa5 100644
--- a/target/linux/layerscape/patches-4.14/802-dma-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/805-dma-support-layerscape.patch
@@ -1,35 +1,25 @@
-From 731adfb43892a1d7fe00e2036200f33a9b61a589 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:02 +0800
-Subject: [PATCH 19/40] dma: support layerscape
-This is an integrated patch of dma for layerscape
+From d3d537ebe9884e7d945ab74bb02312d0c2c9b08d Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:32:53 +0800
+Subject: [PATCH 17/32] dma: support layerscape
+
+This is an integrated patch for layerscape dma support.
 
-Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
-Signed-off-by: Changming Huang <jerry.huang@nxp.com>
-Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
 Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
-Signed-off-by: Peng Ma <peng.ma@nxp.com>
-Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
-Signed-off-by: Rajiv Vishwakarma <rajiv.vishwakarma@nxp.com>
-Signed-off-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
-Signed-off-by: Wen He <wen.he_1@nxp.com>
-Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- .../devicetree/bindings/dma/fsl-qdma.txt      |   51 +
- drivers/dma/Kconfig                           |   33 +-
- drivers/dma/Makefile                          |    3 +
- drivers/dma/caam_dma.c                        |  462 ++++++
- drivers/dma/dpaa2-qdma/Kconfig                |    8 +
- drivers/dma/dpaa2-qdma/Makefile               |    8 +
- drivers/dma/dpaa2-qdma/dpaa2-qdma.c           |  940 ++++++++++++
- drivers/dma/dpaa2-qdma/dpaa2-qdma.h           |  227 +++
- drivers/dma/dpaa2-qdma/dpdmai.c               |  515 +++++++
- drivers/dma/dpaa2-qdma/fsl_dpdmai.h           |  521 +++++++
- drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h       |  222 +++
- drivers/dma/fsl-qdma.c                        | 1278 +++++++++++++++++
- 12 files changed, 4267 insertions(+), 1 deletion(-)
- create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
+ drivers/dma/Kconfig                     |   31 +
+ drivers/dma/Makefile                    |    3 +
+ drivers/dma/caam_dma.c                  |  563 ++++++++++
+ drivers/dma/dpaa2-qdma/Kconfig          |    8 +
+ drivers/dma/dpaa2-qdma/Makefile         |    8 +
+ drivers/dma/dpaa2-qdma/dpaa2-qdma.c     |  940 +++++++++++++++++
+ drivers/dma/dpaa2-qdma/dpaa2-qdma.h     |  227 +++++
+ drivers/dma/dpaa2-qdma/dpdmai.c         |  515 ++++++++++
+ drivers/dma/dpaa2-qdma/fsl_dpdmai.h     |  521 ++++++++++
+ drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h |  222 ++++
+ drivers/dma/fsl-qdma.c                  | 1243 +++++++++++++++++++++++
+ 11 files changed, 4281 insertions(+)
  create mode 100644 drivers/dma/caam_dma.c
  create mode 100644 drivers/dma/dpaa2-qdma/Kconfig
  create mode 100644 drivers/dma/dpaa2-qdma/Makefile
@@ -40,70 +30,37 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  create mode 100644 drivers/dma/dpaa2-qdma/fsl_dpdmai_cmd.h
  create mode 100644 drivers/dma/fsl-qdma.c
 
---- /dev/null
-+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
-@@ -0,0 +1,51 @@
-+* Freescale queue Direct Memory Access(qDMA) Controller
-+
-+The qDMA supports channel virtualization by allowing DMA jobs to be enqueued into
-+different command queues. Core can initiate a DMA transaction by preparing a command
-+descriptor for each DMA job and enqueuing this job to a command queue.
-+
-+* qDMA Controller
-+Required properties:
-+- compatible :
-+	should be "fsl,ls1021a-qdma".
-+- reg : Specifies base physical address(s) and size of the qDMA registers.
-+	The 1st region is qDMA control register's address and size.
-+	The 2nd region is status queue control register's address and size.
-+	The 3rd region is virtual block control register's address and size.
-+- interrupts : A list of interrupt-specifiers, one for each entry in
-+	interrupt-names.
-+- interrupt-names : Should contain:
-+	"qdma-queue0" - the block0 interrupt
-+	"qdma-queue1" - the block1 interrupt
-+	"qdma-queue2" - the block2 interrupt
-+	"qdma-queue3" - the block3 interrupt
-+	"qdma-error"  - the error interrupt
-+- channels : Number of DMA channels supported
-+- block-number : the virtual block number
-+- block-offset : the offset of different virtual block
-+- queues : the number of command queue per virtual block
-+- status-sizes : status queue size of per virtual block
-+- queue-sizes : command queue size of per virtual block, the size number based on queues
-+- big-endian: If present registers and hardware scatter/gather descriptors
-+	of the qDMA are implemented in big endian mode, otherwise in little
-+	mode.
-+
-+Examples:
-+	qdma: qdma@8390000 {
-+				compatible = "fsl,ls1021a-qdma";
-+				reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
-+				      <0x0 0x8389000 0x0 0x1000>, /* Status regs */
-+				      <0x0 0x838a000 0x0 0x2000>; /* Block regs */
-+				interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
-+					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
-+					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-+				interrupt-names = "qdma-error",
-+					"qdma-queue0", "qdma-queue1";
-+				channels = <8>;
-+				block-number = <2>;
-+				block-offset = <0x1000>;
-+				queues = <2>;
-+				status-sizes = <64>;
-+				queue-sizes = <64 64>;
-+				big-endian;
-+			};
 --- a/drivers/dma/Kconfig
 +++ b/drivers/dma/Kconfig
-@@ -129,6 +129,24 @@ config COH901318
+@@ -192,6 +192,20 @@ config FSL_EDMA
+ 	  multiplexing capability for DMA request sources(slot).
+ 	  This module can be found on Freescale Vybrid and LS-1 SoCs.
+ 
++config FSL_QDMA
++       tristate "Freescale qDMA engine support"
++       select DMA_ENGINE
++       select DMA_VIRTUAL_CHANNELS
++       select DMA_ENGINE_RAID
++       select ASYNC_TX_ENABLE_CHANNEL_SWITCH
++       help
++         Support the Freescale qDMA engine with command queue and legacy mode.
++         Channel virtualization is supported through enqueuing of DMA jobs to,
++         or dequeuing DMA jobs from, different work queues.
++         This module can be found on Freescale LS SoCs.
++
++source drivers/dma/dpaa2-qdma/Kconfig
++
+ config FSL_RAID
+         tristate "Freescale RAID engine Support"
+         depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
+@@ -564,6 +578,23 @@ config ZX_DMA
  	help
- 	  Enable support for ST-Ericsson COH 901 318 DMA.
+ 	  Support the DMA engine for ZTE ZX296702 platform devices.
  
 +config CRYPTO_DEV_FSL_CAAM_DMA
 +	tristate "CAAM DMA engine support"
 +	depends on CRYPTO_DEV_FSL_CAAM_JR
-+	default n
++	default y
 +	select DMA_ENGINE
 +	select ASYNC_CORE
 +	select ASYNC_TX_ENABLE_CHANNEL_SWITCH
@@ -117,116 +74,59 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	  To compile this as a module, choose M here: the module
 +	  will be called caam_dma.
-+
- config DMA_BCM2835
- 	tristate "BCM2835 DMA engine support"
- 	depends on ARCH_BCM2835
-@@ -215,6 +233,20 @@ config FSL_EDMA
- 	  multiplexing capability for DMA request sources(slot).
- 	  This module can be found on Freescale Vybrid and LS-1 SoCs.
  
-+config FSL_QDMA
-+       tristate "NXP Layerscape qDMA engine support"
-+       select DMA_ENGINE
-+       select DMA_VIRTUAL_CHANNELS
-+       select DMA_ENGINE_RAID
-+       select ASYNC_TX_ENABLE_CHANNEL_SWITCH
-+       help
-+         Support the NXP Layerscape qDMA engine with command queue and legacy mode.
-+         Channel virtualization is supported through enqueuing of DMA jobs to,
-+         or dequeuing DMA jobs from, different work queues.
-+         This module can be found on NXP Layerscape SoCs.
-+
-+source drivers/dma/dpaa2-qdma/Kconfig
-+
- config FSL_RAID
-         tristate "Freescale RAID engine Support"
-         depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
-@@ -600,7 +632,6 @@ config ZX_DMA
- 	help
- 	  Support the DMA engine for ZTE ZX family platform devices.
- 
--
  # driver files
  source "drivers/dma/bestcomm/Kconfig"
- 
 --- a/drivers/dma/Makefile
 +++ b/drivers/dma/Makefile
-@@ -31,7 +31,9 @@ obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
- obj-$(CONFIG_DW_DMAC_CORE) += dw/
+@@ -29,6 +29,8 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
  obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
  obj-$(CONFIG_FSL_DMA) += fsldma.o
-+obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma/
  obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
 +obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
++obj-$(CONFIG_FSL_DPAA2_QDMA) += dpaa2-qdma/
  obj-$(CONFIG_FSL_RAID) += fsl_raid.o
  obj-$(CONFIG_HSU_DMA) += hsu/
  obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
-@@ -71,6 +73,7 @@ obj-$(CONFIG_TI_EDMA) += edma.o
+@@ -67,6 +69,7 @@ obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-
+ obj-$(CONFIG_TI_EDMA) += edma.o
  obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
- obj-$(CONFIG_ZX_DMA) += zx_dma.o
- obj-$(CONFIG_ST_FDMA) += st_fdma.o
+ obj-$(CONFIG_ZX_DMA) += zx296702_dma.o
 +obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_DMA) += caam_dma.o
  
  obj-y += qcom/
  obj-y += xilinx/
 --- /dev/null
 +++ b/drivers/dma/caam_dma.c
-@@ -0,0 +1,462 @@
+@@ -0,0 +1,563 @@
 +/*
 + * caam support for SG DMA
 + *
 + * Copyright 2016 Freescale Semiconductor, Inc
 + * Copyright 2017 NXP
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions are met:
-+ *     * Redistributions of source code must retain the above copyright
-+ *       notice, this list of conditions and the following disclaimer.
-+ *     * Redistributions in binary form must reproduce the above copyright
-+ *       notice, this list of conditions and the following disclaimer in the
-+ *       documentation and/or other materials provided with the distribution.
-+ *     * Neither the names of the above-listed copyright holders nor the
-+ *       names of any contributors may be used to endorse or promote products
-+ *       derived from this software without specific prior written permission.
-+ *
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") as published by the Free Software
-+ * Foundation, either version 2 of that License or (at your option) any
-+ * later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-+ * POSSIBILITY OF SUCH DAMAGE.
 + */
 +
-+#include <linux/dma-mapping.h>
-+#include <linux/dmaengine.h>
 +#include <linux/module.h>
 +#include <linux/platform_device.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
 +#include <linux/slab.h>
++#include <linux/debugfs.h>
 +
++#include <linux/dmaengine.h>
 +#include "dmaengine.h"
 +
 +#include "../crypto/caam/regs.h"
 +#include "../crypto/caam/jr.h"
 +#include "../crypto/caam/error.h"
++#include "../crypto/caam/intern.h"
 +#include "../crypto/caam/desc_constr.h"
++#include "../crypto/caam/sg_sw_sec4.h"
 +
 +#define DESC_DMA_MEMCPY_LEN	((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / \
 +				 CAAM_CMD_SZ)
 +
-+/*
-+ * This is max chunk size of a DMA transfer. If a buffer is larger than this
++/* This is max chunk size of a DMA transfer. If a buffer is larger than this
 + * value it is internally broken into chunks of max CAAM_DMA_CHUNK_SIZE bytes
 + * and for each chunk a DMA transfer request is issued.
 + * This value is the largest number on 16 bits that is a multiple of 256 bytes
@@ -248,6 +148,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	dma_addr_t dst_dma;
 +	unsigned int src_len;
 +	unsigned int dst_len;
++	struct sec4_sg_entry *sec4_sg;
 +	u32 jd[] ____cacheline_aligned;
 +};
 +
@@ -256,7 +157,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + * @chan: dma channel used by async_tx API
 + * @node: list_head used to attach to the global dma_ctx_list
 + * @jrdev: Job Ring device
-+ * @pending_q: queue of pending (submitted, but not enqueued) jobs
++ * @submit_q: queue of pending (submitted, but not enqueued) jobs
 + * @done_not_acked: jobs that have been completed by jr, but maybe not acked
 + * @edesc_lock: protects extended descriptor
 + */
@@ -264,7 +165,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	struct dma_chan chan;
 +	struct list_head node;
 +	struct device *jrdev;
-+	struct list_head pending_q;
++	struct list_head submit_q;
 +	struct list_head done_not_acked;
 +	spinlock_t edesc_lock;
 +};
@@ -285,13 +186,87 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	spin_lock_bh(&ctx->edesc_lock);
 +
 +	cookie = dma_cookie_assign(tx);
-+	list_add_tail(&edesc->node, &ctx->pending_q);
++	list_add_tail(&edesc->node, &ctx->submit_q);
 +
 +	spin_unlock_bh(&ctx->edesc_lock);
 +
 +	return cookie;
 +}
 +
++static unsigned int caam_dma_sg_dma_len(struct scatterlist *sg,
++					unsigned int nents)
++{
++	unsigned int len;
++
++	for (len = 0; sg && nents; sg = sg_next(sg), nents--)
++		len += sg_dma_len(sg);
++
++	return len;
++}
++
++static struct caam_dma_edesc *
++caam_dma_sg_edesc_alloc(struct dma_chan *chan,
++			struct scatterlist *dst_sg, unsigned int dst_nents,
++			struct scatterlist *src_sg, unsigned int src_nents,
++			unsigned long flags)
++{
++	struct caam_dma_ctx *ctx = container_of(chan, struct caam_dma_ctx,
++						chan);
++	struct device *jrdev = ctx->jrdev;
++	struct caam_dma_edesc *edesc;
++	struct sec4_sg_entry *sec4_sg;
++	dma_addr_t sec4_sg_dma_src;
++	unsigned int sec4_sg_bytes;
++
++	if (!dst_sg || !src_sg || !dst_nents || !src_nents)
++		return NULL;
++
++	sec4_sg_bytes = (src_nents + dst_nents) * sizeof(*sec4_sg);
++
++	edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
++			GFP_DMA | GFP_NOWAIT);
++	if (!edesc)
++		return ERR_PTR(-ENOMEM);
++
++	edesc->src_len = caam_dma_sg_dma_len(src_sg, src_nents);
++	edesc->dst_len = caam_dma_sg_dma_len(dst_sg, dst_nents);
++	if (edesc->src_len != edesc->dst_len) {
++		dev_err(jrdev, "%s: src(%u) and dst(%u) len mismatch.\n",
++			__func__, edesc->src_len, edesc->dst_len);
++		kfree(edesc);
++		return ERR_PTR(-EINVAL);
++	}
++
++	dma_async_tx_descriptor_init(&edesc->async_tx, chan);
++	edesc->async_tx.tx_submit = caam_dma_tx_submit;
++	edesc->async_tx.flags = flags;
++	edesc->async_tx.cookie = -EBUSY;
++
++	/* Prepare SEC SGs */
++	edesc->sec4_sg = (void *)edesc + offsetof(struct caam_dma_edesc, jd) +
++			 DESC_JOB_IO_LEN;
++
++	sec4_sg = edesc->sec4_sg;
++	sg_to_sec4_sg_last(src_sg, src_nents, sec4_sg, 0);
++
++	sec4_sg += src_nents;
++	sg_to_sec4_sg_last(dst_sg, dst_nents, sec4_sg, 0);
++
++	sec4_sg_dma_src = dma_map_single(jrdev, edesc->sec4_sg, sec4_sg_bytes,
++					 DMA_TO_DEVICE);
++	if (dma_mapping_error(jrdev, sec4_sg_dma_src)) {
++		dev_err(jrdev, "error mapping segments to device\n");
++		kfree(edesc);
++		return ERR_PTR(-ENOMEM);
++	}
++
++	edesc->src_dma = sec4_sg_dma_src;
++	edesc->dst_dma = sec4_sg_dma_src + src_nents * sizeof(*sec4_sg);
++	edesc->ctx = ctx;
++
++	return edesc;
++}
++
 +static void caam_jr_chan_free_edesc(struct caam_dma_edesc *edesc)
 +{
 +	struct caam_dma_ctx *ctx = edesc->ctx;
@@ -338,6 +313,47 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		callback(callback_param);
 +}
 +
++static void caam_dma_sg_init_job_desc(struct caam_dma_edesc *edesc)
++{
++	u32 *jd = edesc->jd;
++	u32 *sh_desc = dma_sh_desc->desc;
++	dma_addr_t desc_dma = dma_sh_desc->desc_dma;
++
++	/* init the job descriptor */
++	init_job_desc_shared(jd, desc_dma, desc_len(sh_desc), HDR_REVERSE);
++
++	/* set SEQIN PTR */
++	append_seq_in_ptr(jd, edesc->src_dma, edesc->src_len, LDST_SGF);
++
++	/* set SEQOUT PTR */
++	append_seq_out_ptr(jd, edesc->dst_dma, edesc->dst_len, LDST_SGF);
++
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "caam dma desc@" __stringify(__LINE__) ": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, jd, desc_bytes(jd), 1);
++#endif
++}
++
++/* This function can be called from an interrupt context */
++static struct dma_async_tx_descriptor *
++caam_dma_prep_sg(struct dma_chan *chan, struct scatterlist *dst_sg,
++		 unsigned int dst_nents, struct scatterlist *src_sg,
++		 unsigned int src_nents, unsigned long flags)
++{
++	struct caam_dma_edesc *edesc;
++
++	/* allocate extended descriptor */
++	edesc = caam_dma_sg_edesc_alloc(chan, dst_sg, dst_nents, src_sg,
++					src_nents, flags);
++	if (IS_ERR_OR_NULL(edesc))
++		return ERR_CAST(edesc);
++
++	/* Initialize job descriptor */
++	caam_dma_sg_init_job_desc(edesc);
++
++	return &edesc->async_tx;
++}
++
 +static void caam_dma_memcpy_init_job_desc(struct caam_dma_edesc *edesc)
 +{
 +	u32 *jd = edesc->jd;
@@ -353,8 +369,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	/* set SEQOUT PTR */
 +	append_seq_out_ptr(jd, edesc->dst_dma, edesc->dst_len, 0);
 +
-+	print_hex_dump_debug("caam dma desc@" __stringify(__LINE__) ": ",
-+			     DUMP_PREFIX_ADDRESS, 16, 4, jd, desc_bytes(jd), 1);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "caam dma desc@" __stringify(__LINE__) ": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, jd, desc_bytes(jd), 1);
++#endif
 +}
 +
 +static struct dma_async_tx_descriptor *
@@ -393,7 +411,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	struct caam_dma_edesc *edesc, *_edesc;
 +
 +	spin_lock_bh(&ctx->edesc_lock);
-+	list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) {
++	list_for_each_entry_safe(edesc, _edesc, &ctx->submit_q, node) {
 +		if (caam_jr_enqueue(ctx->jrdev, edesc->jd,
 +				    caam_dma_done, edesc) < 0)
 +			break;
@@ -409,7 +427,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	struct caam_dma_edesc *edesc, *_edesc;
 +
 +	spin_lock_bh(&ctx->edesc_lock);
-+	list_for_each_entry_safe(edesc, _edesc, &ctx->pending_q, node) {
++	list_for_each_entry_safe(edesc, _edesc, &ctx->submit_q, node) {
 +		list_del(&edesc->node);
 +		kfree(edesc);
 +	}
@@ -445,7 +463,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +		ctx->jrdev = jrdev;
 +
-+		INIT_LIST_HEAD(&ctx->pending_q);
++		INIT_LIST_HEAD(&ctx->submit_q);
 +		INIT_LIST_HEAD(&ctx->done_not_acked);
 +		INIT_LIST_HEAD(&ctx->node);
 +		spin_lock_init(&ctx->edesc_lock);
@@ -488,8 +506,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	/* REG0 = SEQINLEN - CAAM_DMA_CHUNK_SIZE */
 +	append_math_sub_imm_u32(desc, REG0, SEQINLEN, IMM, CAAM_DMA_CHUNK_SIZE);
 +
-+	/*
-+	 * if (REG0 > 0)
++	/* if (REG0 > 0)
 +	 *	jmp to LABEL1
 +	 */
 +	jmp_cmd = append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N |
@@ -514,16 +531,16 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 |
 +			     FIFOLD_TYPE_IFIFO | LDST_VLF);
 +
-+	/*
-+	 * if (REG0 > 0)
++	/* if (REG0 > 0)
 +	 *	jmp 0xF8 (after shared desc header)
 +	 */
 +	append_jump(desc, JUMP_TEST_INVALL | JUMP_COND_MATH_N |
 +		    JUMP_COND_MATH_Z | 0xF8);
 +
-+	print_hex_dump_debug("caam dma shdesc@" __stringify(__LINE__) ": ",
-+			     DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
-+			     1);
++#ifdef DEBUG
++	print_hex_dump(KERN_ERR, "caam dma shdesc@" __stringify(__LINE__) ": ",
++		       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
 +}
 +
 +static int __init caam_dma_probe(struct platform_device *pdev)
@@ -568,10 +585,12 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	dma_dev->dev = dev;
 +	dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
++	dma_cap_set(DMA_SG, dma_dev->cap_mask);
 +	dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
 +	dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
 +	dma_dev->device_tx_status = dma_cookie_status;
 +	dma_dev->device_issue_pending = caam_dma_issue_pending;
++	dma_dev->device_prep_dma_sg = caam_dma_prep_sg;
 +	dma_dev->device_prep_dma_memcpy = caam_dma_prep_memcpy;
 +	dma_dev->device_free_chan_resources = caam_dma_free_chan_resources;
 +
@@ -622,9 +641,18 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	return 0;
 +}
 +
++static const struct of_device_id caam_dma_match[] = {
++	{ .compatible = "fsl,sec-v5.4-dma", },
++	{ .compatible = "fsl,sec-v5.0-dma", },
++	{ .compatible = "fsl,sec-v4.0-dma", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, caam_dma_match);
++
 +static struct platform_driver caam_dma_driver = {
 +	.driver = {
 +		.name = "caam-dma",
++		.of_match_table = caam_dma_match,
 +	},
 +	.probe  = caam_dma_probe,
 +	.remove = caam_dma_remove,
@@ -632,9 +660,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +module_platform_driver(caam_dma_driver);
 +
 +MODULE_LICENSE("Dual BSD/GPL");
-+MODULE_DESCRIPTION("NXP CAAM support for DMA engine");
++MODULE_DESCRIPTION("NXP CAAM support for SG DMA");
 +MODULE_AUTHOR("NXP Semiconductors");
-+MODULE_ALIAS("platform:caam-dma");
 --- /dev/null
 +++ b/drivers/dma/dpaa2-qdma/Kconfig
 @@ -0,0 +1,8 @@
@@ -3099,29 +3126,36 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#endif /* _FSL_DPDMAI_CMD_H */
 --- /dev/null
 +++ b/drivers/dma/fsl-qdma.c
-@@ -0,0 +1,1278 @@
+@@ -0,0 +1,1243 @@
 +/*
-+ * Driver for NXP Layerscape Queue direct memory access controller (qDMA)
++ * drivers/dma/fsl-qdma.c
 + *
-+ * Copyright 2017 NXP
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
 + *
-+ * Author:
-+ *  Jiaheng Fan <jiaheng.fan@nxp.com>
-+ *  Wen He <wen.he_1@nxp.com>
++ * Driver for the Freescale qDMA engine with software command queue mode.
++ * Channel virtualization is supported through enqueuing of DMA jobs to,
++ * or dequeuing DMA jobs from, different work queues.
++ * This module can be found on Freescale LS SoCs.
 + *
-+ * SPDX-License-Identifier: GPL-2.0+
++ * This program is free software; you can redistribute  it and/or modify it
++ * under  the terms of  the GNU General  Public License as published by the
++ * Free Software Foundation;  either version 2 of the  License, or (at your
++ * option) any later version.
 + */
 +
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
++#include <asm/cacheflush.h>
++#include <linux/clk.h>
 +#include <linux/delay.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_address.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_dma.h>
 +#include <linux/dma-mapping.h>
 +#include <linux/dmapool.h>
-+#include <linux/dmaengine.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/of_dma.h>
++#include <linux/of_irq.h>
 +#include <linux/slab.h>
 +#include <linux/spinlock.h>
 +
@@ -3192,8 +3226,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#define FSL_QDMA_DMR_DQD		0x40000000
 +#define FSL_QDMA_DSR_DB			0x80000000
 +
-+#define FSL_QDMA_COMMAND_BUFFER_SIZE	64
-+#define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
++#define FSL_QDMA_BASE_BUFFER_SIZE	96
++#define FSL_QDMA_EXPECT_SG_ENTRY_NUM	16
 +#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN	64
 +#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX	16384
 +#define FSL_QDMA_QUEUE_NUM_MAX		8
@@ -3208,36 +3242,16 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#define FSL_QDMA_CMD_DSEN_OFFSET	19
 +#define FSL_QDMA_CMD_LWC_OFFSET		16
 +
-+#define QDMA_CCDF_STATUS		20
-+#define QDMA_CCDF_OFFSET		20
-+#define QDMA_CCDF_MASK			GENMASK(28, 20)
-+#define QDMA_CCDF_FOTMAT		BIT(29)
-+#define QDMA_CCDF_SER			BIT(30)
++#define FSL_QDMA_E_SG_TABLE		1
++#define FSL_QDMA_E_DATA_BUFFER		0
++#define FSL_QDMA_F_LAST_ENTRY		1
 +
-+#define QDMA_SG_FIN			BIT(30)
-+#define QDMA_SG_EXT			BIT(31)
-+#define QDMA_SG_LEN_MASK		GENMASK(29, 0)
-+
-+#define QDMA_BIG_ENDIAN			0x00000001
-+#define	COMP_TIMEOUT			1000
-+#define COMMAND_QUEUE_OVERFLLOW		10
-+
-+#define QDMA_IN(fsl_qdma_engine, addr)					\
-+	(((fsl_qdma_engine)->big_endian & QDMA_BIG_ENDIAN) ?		\
-+		ioread32be(addr) : ioread32(addr))
-+#define QDMA_OUT(fsl_qdma_engine, addr, val)				\
-+	(((fsl_qdma_engine)->big_endian & QDMA_BIG_ENDIAN) ?		\
-+		iowrite32be(val, addr) : iowrite32(val, addr))
-+
-+#define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x)			\
-+	(((fsl_qdma_engine)->block_offset) * (x))
-+
-+static DEFINE_PER_CPU(u64, pre_addr);
-+static DEFINE_PER_CPU(u64, pre_queue);
++u64 pre_addr, pre_queue;
 +
 +/* qDMA Command Descriptor Fotmats */
 +
-+struct fsl_qdma_format {
++/* Compound Command Descriptor Fotmat */
++struct fsl_qdma_ccdf {
 +	__le32 status; /* ser, status */
 +	__le32 cfg;	/* format, offset */
 +	union {
@@ -3245,66 +3259,82 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			__le32 addr_lo;	/* low 32-bits of 40-bit address */
 +			u8 addr_hi;	/* high 8-bits of 40-bit address */
 +			u8 __reserved1[2];
-+			u8 cfg8b_w1; /* dd, queue */
++			u8 cfg8b_w1; /* dd, queue*/
 +		} __packed;
 +		__le64 data;
 +	};
 +} __packed;
 +
-+static inline u64
-+qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf)
++#define QDMA_CCDF_STATUS		20
++#define QDMA_CCDF_OFFSET		20
++#define QDMA_CCDF_MASK		GENMASK(28, 20)
++#define QDMA_CCDF_FOTMAT		BIT(29)
++#define QDMA_CCDF_SER			BIT(30)
++
++static inline u64 qdma_ccdf_addr_get64(const struct fsl_qdma_ccdf *ccdf)
 +{
 +	return le64_to_cpu(ccdf->data) & 0xffffffffffLLU;
 +}
-+
-+static inline void
-+qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)
++static inline u64 qdma_ccdf_get_queue(const struct fsl_qdma_ccdf *ccdf)
++{
++	return ccdf->cfg8b_w1 & 0xff;
++}
++static inline void qdma_ccdf_addr_set64(struct fsl_qdma_ccdf *ccdf, u64 addr)
 +{
 +	ccdf->addr_hi = upper_32_bits(addr);
 +	ccdf->addr_lo = cpu_to_le32(lower_32_bits(addr));
 +}
-+
-+static inline u64
-+qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf)
-+{
-+	return ccdf->cfg8b_w1 & 0xff;
-+}
-+
-+static inline int
-+qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf)
++static inline int qdma_ccdf_get_offset(const struct fsl_qdma_ccdf *ccdf)
 +{
 +	return (le32_to_cpu(ccdf->cfg) & QDMA_CCDF_MASK) >> QDMA_CCDF_OFFSET;
 +}
-+
-+static inline void
-+qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset)
++static inline void qdma_ccdf_set_format(struct fsl_qdma_ccdf *ccdf, int offset)
 +{
 +	ccdf->cfg = cpu_to_le32(QDMA_CCDF_FOTMAT | offset);
 +}
-+
-+static inline int
-+qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf)
++static inline int qdma_ccdf_get_status(const struct fsl_qdma_ccdf *ccdf)
 +{
 +	return (le32_to_cpu(ccdf->status) & QDMA_CCDF_MASK) >> QDMA_CCDF_STATUS;
 +}
-+
-+static inline void
-+qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status)
++static inline void qdma_ccdf_set_ser(struct fsl_qdma_ccdf *ccdf, int status)
 +{
 +	ccdf->status = cpu_to_le32(QDMA_CCDF_SER | status);
 +}
++/* qDMA Compound S/G Format */
++struct fsl_qdma_csgf {
++	__le32 offset; /* offset */
++	__le32 cfg;	/* E bit, F bit, length */
++	union {
++		struct {
++			__le32 addr_lo;	/* low 32-bits of 40-bit address */
++			u8 addr_hi;	/* high 8-bits of 40-bit address */
++			u8 __reserved1[3];
++		};
++		__le64 data;
++	};
++} __packed;
 +
-+static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)
++#define QDMA_SG_FIN	BIT(30)
++#define QDMA_SG_EXT	BIT(31)
++#define QDMA_SG_LEN_MASK	GENMASK(29, 0)
++static inline u64 qdma_csgf_addr_get64(const struct fsl_qdma_csgf *sg)
++{
++	return be64_to_cpu(sg->data) & 0xffffffffffLLU;
++}
++static inline void qdma_csgf_addr_set64(struct fsl_qdma_csgf *sg, u64 addr)
++{
++	sg->addr_hi = upper_32_bits(addr);
++	sg->addr_lo = cpu_to_le32(lower_32_bits(addr));
++}
++static inline void qdma_csgf_set_len(struct fsl_qdma_csgf *csgf, int len)
 +{
 +	csgf->cfg = cpu_to_le32(len & QDMA_SG_LEN_MASK);
 +}
-+
-+static inline void qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len)
++static inline void qdma_csgf_set_f(struct fsl_qdma_csgf *csgf, int len)
 +{
 +	csgf->cfg = cpu_to_le32(QDMA_SG_FIN | (len & QDMA_SG_LEN_MASK));
 +}
-+
-+static inline void qdma_csgf_set_e(struct fsl_qdma_format *csgf, int len)
++static inline void qdma_csgf_set_e(struct fsl_qdma_csgf *csgf, int len)
 +{
 +	csgf->cfg = cpu_to_le32(QDMA_SG_EXT | (len & QDMA_SG_LEN_MASK));
 +}
@@ -3317,7 +3347,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	__le32 cmd;
 +} __packed;
 +
-+/* qDMA Destination Descriptor Format */
++/*qDMA Destination Descriptor Format*/
 +struct fsl_qdma_ddf {
 +	__le32 rev1;
 +	__le32 cfg; /* rev2, bit[0-11] - dsd, bit[12-23] - dss */
@@ -3329,33 +3359,40 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	struct virt_dma_chan		vchan;
 +	struct virt_dma_desc		vdesc;
 +	enum dma_status			status;
++	u32				slave_id;
 +	struct fsl_qdma_engine		*qdma;
 +	struct fsl_qdma_queue		*queue;
++	struct list_head		qcomp;
 +};
 +
 +struct fsl_qdma_queue {
-+	struct fsl_qdma_format	*virt_head;
-+	struct fsl_qdma_format	*virt_tail;
++	struct fsl_qdma_ccdf	*virt_head;
++	struct fsl_qdma_ccdf	*virt_tail;
 +	struct list_head	comp_used;
 +	struct list_head	comp_free;
 +	struct dma_pool		*comp_pool;
-+	struct dma_pool		*desc_pool;
++	struct dma_pool		*sg_pool;
 +	spinlock_t		queue_lock;
 +	dma_addr_t		bus_addr;
 +	u32                     n_cq;
 +	u32			id;
-+	struct fsl_qdma_format	*cq;
-+	void __iomem		*block_base;
++	struct fsl_qdma_ccdf	*cq;
++};
++
++struct fsl_qdma_sg {
++	dma_addr_t		bus_addr;
++	void			*virt_addr;
 +};
 +
 +struct fsl_qdma_comp {
 +	dma_addr_t              bus_addr;
-+	dma_addr_t              desc_bus_addr;
 +	void			*virt_addr;
-+	void			*desc_virt_addr;
 +	struct fsl_qdma_chan	*qchan;
++	struct fsl_qdma_sg	*sg_block;
 +	struct virt_dma_desc    vdesc;
 +	struct list_head	list;
++	u32			sg_block_src;
++	u32			sg_block_dst;
 +};
 +
 +struct fsl_qdma_engine {
@@ -3367,27 +3404,29 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	u32			n_queues;
 +	struct mutex            fsl_qdma_mutex;
 +	int			error_irq;
-+	int			*queue_irq;
++	int			queue_irq;
 +	bool			big_endian;
 +	struct fsl_qdma_queue	*queue;
-+	struct fsl_qdma_queue	**status;
-+	struct fsl_qdma_chan	*chans;
-+	int			block_number;
-+	int			block_offset;
-+	int			irq_base;
-+	int			desc_allocated;
++	struct fsl_qdma_queue	*status;
++	struct fsl_qdma_chan	chans[];
 +
 +};
 +
 +static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem *addr)
 +{
-+	return QDMA_IN(qdma, addr);
++	if (qdma->big_endian)
++		return ioread32be(addr);
++	else
++		return ioread32(addr);
 +}
 +
 +static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
 +						void __iomem *addr)
 +{
-+	QDMA_OUT(qdma, addr, val);
++	if (qdma->big_endian)
++		iowrite32be(val, addr);
++	else
++		iowrite32(val, addr);
 +}
 +
 +static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
@@ -3400,12 +3439,17 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	return container_of(vd, struct fsl_qdma_comp, vdesc);
 +}
 +
++static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
++{
++	/*
++	 * In QDMA mode, We don't need to do anything.
++	 */
++	return 0;
++}
++
 +static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
 +{
 +	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
-+	struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
-+	struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
-+	struct fsl_qdma_comp *comp_temp, *_comp_temp;
 +	unsigned long flags;
 +	LIST_HEAD(head);
 +
@@ -3414,70 +3458,36 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 +
 +	vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
-+
-+	if (!fsl_queue->comp_pool && !fsl_queue->comp_pool)
-+		return;
-+
-+	list_for_each_entry_safe(comp_temp, _comp_temp,
-+				&fsl_queue->comp_used,	list) {
-+		dma_pool_free(fsl_queue->comp_pool,
-+					 comp_temp->virt_addr,
-+					 comp_temp->bus_addr);
-+		dma_pool_free(fsl_queue->desc_pool,
-+				comp_temp->desc_virt_addr,
-+				comp_temp->desc_bus_addr);
-+		list_del(&comp_temp->list);
-+		kfree(comp_temp);
-+	}
-+
-+	list_for_each_entry_safe(comp_temp, _comp_temp,
-+				&fsl_queue->comp_free, list) {
-+		dma_pool_free(fsl_queue->comp_pool,
-+					 comp_temp->virt_addr,
-+					 comp_temp->bus_addr);
-+		dma_pool_free(fsl_queue->desc_pool,
-+				comp_temp->desc_virt_addr,
-+				comp_temp->desc_bus_addr);
-+		list_del(&comp_temp->list);
-+		kfree(comp_temp);
-+	}
-+
-+	dma_pool_destroy(fsl_queue->comp_pool);
-+	dma_pool_destroy(fsl_queue->desc_pool);
-+
-+	fsl_qdma->desc_allocated--;
-+	fsl_queue->comp_pool = NULL;
-+	fsl_queue->desc_pool = NULL;
 +}
 +
 +static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
 +					dma_addr_t dst, dma_addr_t src, u32 len)
 +{
-+	struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
++	struct fsl_qdma_ccdf *ccdf;
++	struct fsl_qdma_csgf *csgf_desc, *csgf_src, *csgf_dest;
 +	struct fsl_qdma_sdf *sdf;
 +	struct fsl_qdma_ddf *ddf;
 +
-+	ccdf = (struct fsl_qdma_format *)fsl_comp->virt_addr;
-+	csgf_desc = (struct fsl_qdma_format *)fsl_comp->virt_addr + 1;
-+	csgf_src = (struct fsl_qdma_format *)fsl_comp->virt_addr + 2;
-+	csgf_dest = (struct fsl_qdma_format *)fsl_comp->virt_addr + 3;
-+	sdf = (struct fsl_qdma_sdf *)fsl_comp->desc_virt_addr;
-+	ddf = (struct fsl_qdma_ddf *)fsl_comp->desc_virt_addr + 1;
++	ccdf = (struct fsl_qdma_ccdf *)fsl_comp->virt_addr;
++	csgf_desc = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 1;
++	csgf_src = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 2;
++	csgf_dest = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 3;
++	sdf = (struct fsl_qdma_sdf *)fsl_comp->virt_addr + 4;
++	ddf = (struct fsl_qdma_ddf *)fsl_comp->virt_addr + 5;
 +
-+	memset(fsl_comp->virt_addr, 0, FSL_QDMA_COMMAND_BUFFER_SIZE);
-+	memset(fsl_comp->desc_virt_addr, 0, FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
++	memset(fsl_comp->virt_addr, 0, FSL_QDMA_BASE_BUFFER_SIZE);
 +	/* Head Command Descriptor(Frame Descriptor) */
-+	qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
++	qdma_ccdf_addr_set64(ccdf, fsl_comp->bus_addr + 16);
 +	qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf));
 +	qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(ccdf));
 +	/* Status notification is enqueued to status queue. */
 +	/* Compound Command Descriptor(Frame List Table) */
-+	qdma_desc_addr_set64(csgf_desc, fsl_comp->desc_bus_addr);
++	qdma_csgf_addr_set64(csgf_desc, fsl_comp->bus_addr + 64);
 +	/* It must be 32 as Compound S/G Descriptor */
 +	qdma_csgf_set_len(csgf_desc, 32);
-+	qdma_desc_addr_set64(csgf_src, src);
++	qdma_csgf_addr_set64(csgf_src, src);
 +	qdma_csgf_set_len(csgf_src, len);
-+	qdma_desc_addr_set64(csgf_dest, dst);
++	qdma_csgf_addr_set64(csgf_dest, dst);
 +	qdma_csgf_set_len(csgf_dest, len);
 +	/* This entry is the last entry. */
 +	qdma_csgf_set_f(csgf_dest, len);
@@ -3490,49 +3500,123 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			FSL_QDMA_CMD_LWC << FSL_QDMA_CMD_LWC_OFFSET);
 +}
 +
++static void fsl_qdma_comp_fill_sg(
++		struct fsl_qdma_comp *fsl_comp,
++		struct scatterlist *dst_sg, unsigned int dst_nents,
++		struct scatterlist *src_sg, unsigned int src_nents)
++{
++	struct fsl_qdma_ccdf *ccdf;
++	struct fsl_qdma_csgf *csgf_desc, *csgf_src, *csgf_dest, *csgf_sg;
++	struct fsl_qdma_sdf *sdf;
++	struct fsl_qdma_ddf *ddf;
++	struct fsl_qdma_sg *sg_block, *temp;
++	struct scatterlist *sg;
++	u64 total_src_len = 0;
++	u64 total_dst_len = 0;
++	u32 i;
++
++	ccdf = (struct fsl_qdma_ccdf *)fsl_comp->virt_addr;
++	csgf_desc = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 1;
++	csgf_src = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 2;
++	csgf_dest = (struct fsl_qdma_csgf *)fsl_comp->virt_addr + 3;
++	sdf = (struct fsl_qdma_sdf *)fsl_comp->virt_addr + 4;
++	ddf = (struct fsl_qdma_ddf *)fsl_comp->virt_addr + 5;
++	memset(fsl_comp->virt_addr, 0, FSL_QDMA_BASE_BUFFER_SIZE);
++	/* Head Command Descriptor(Frame Descriptor) */
++	qdma_ccdf_addr_set64(ccdf, fsl_comp->bus_addr + 16);
++	qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf));
++	/* Status notification is enqueued to status queue. */
++	qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(ccdf));
++
++	/* Compound Command Descriptor(Frame List Table) */
++	qdma_csgf_addr_set64(csgf_desc, fsl_comp->bus_addr + 64);
++	/* It must be 32 as Compound S/G Descriptor */
++	qdma_csgf_set_len(csgf_desc, 32);
++
++	sg_block = fsl_comp->sg_block;
++	qdma_csgf_addr_set64(csgf_src, sg_block->bus_addr);
++	/* This entry link to the s/g entry. */
++	qdma_csgf_set_e(csgf_src, 32);
++
++	temp = sg_block + fsl_comp->sg_block_src;
++	qdma_csgf_addr_set64(csgf_dest, temp->bus_addr);
++	/* This entry is the last entry. */
++	qdma_csgf_set_f(csgf_dest, 32);
++	/* This entry link to the s/g entry. */
++	qdma_csgf_set_e(csgf_dest, 32);
++
++	for_each_sg(src_sg, sg, src_nents, i) {
++		temp = sg_block + i / (FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1);
++		csgf_sg = (struct fsl_qdma_csgf *)temp->virt_addr +
++			  i % (FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1);
++		qdma_csgf_addr_set64(csgf_sg, sg_dma_address(sg));
++		qdma_csgf_set_len(csgf_sg, sg_dma_len(sg));
++		total_src_len += sg_dma_len(sg);
++
++		if (i == src_nents - 1)
++			qdma_csgf_set_f(csgf_sg, sg_dma_len(sg));
++		if (i % (FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1) ==
++		    FSL_QDMA_EXPECT_SG_ENTRY_NUM - 2) {
++			csgf_sg = (struct fsl_qdma_csgf *)temp->virt_addr +
++				  FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1;
++			temp = sg_block +
++				i / (FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1) + 1;
++			qdma_csgf_addr_set64(csgf_sg, temp->bus_addr);
++			qdma_csgf_set_e(csgf_sg, sg_dma_len(sg));
++		}
++	}
++
++	sg_block += fsl_comp->sg_block_src;
++	for_each_sg(dst_sg, sg, dst_nents, i) {
++		temp = sg_block + i / (FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1);
++		csgf_sg = (struct fsl_qdma_csgf *)temp->virt_addr +
++			  i % (FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1);
++		qdma_csgf_addr_set64(csgf_sg, sg_dma_address(sg));
++		qdma_csgf_set_len(csgf_sg, sg_dma_len(sg));
++		total_dst_len += sg_dma_len(sg);
++
++		if (i == dst_nents - 1)
++			qdma_csgf_set_f(csgf_sg, sg_dma_len(sg));
++		if (i % (FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1) ==
++		    FSL_QDMA_EXPECT_SG_ENTRY_NUM - 2) {
++			csgf_sg = (struct fsl_qdma_csgf *)temp->virt_addr +
++				  FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1;
++			temp = sg_block +
++				i / (FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1) + 1;
++			qdma_csgf_addr_set64(csgf_sg, temp->bus_addr);
++			qdma_csgf_set_e(csgf_sg, sg_dma_len(sg));
++		}
++	}
++
++	if (total_src_len != total_dst_len)
++		dev_err(&fsl_comp->qchan->vchan.chan.dev->device,
++			"The data length for src and dst isn't match.\n");
++
++	qdma_csgf_set_len(csgf_src, total_src_len);
++	qdma_csgf_set_len(csgf_dest, total_dst_len);
++
++	/* Descriptor Buffer */
++}
++
 +/*
-+ * Pre-request command descriptor and compound S/G for enqueue.
++ * Prei-request full command descriptor for enqueue.
 + */
-+static int fsl_qdma_pre_request_enqueue_comp_desc(struct fsl_qdma_queue *queue)
++static int fsl_qdma_pre_request_enqueue_desc(struct fsl_qdma_queue *queue)
 +{
 +	struct fsl_qdma_comp *comp_temp;
 +	int i;
 +
-+	for (i = 0; i < queue->n_cq + COMMAND_QUEUE_OVERFLLOW; i++) {
++	for (i = 0; i < queue->n_cq; i++) {
 +		comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
 +		if (!comp_temp)
-+			return -ENOMEM;
++			return -1;
 +		comp_temp->virt_addr = dma_pool_alloc(queue->comp_pool,
-+						      GFP_KERNEL,
++						      GFP_NOWAIT,
 +						      &comp_temp->bus_addr);
-+
-+		if (!comp_temp->virt_addr) {
-+			kfree(comp_temp);
-+			return -ENOMEM;
-+		}
-+
++		if (!comp_temp->virt_addr)
++			return -1;
 +		list_add_tail(&comp_temp->list, &queue->comp_free);
 +	}
-+
-+	return 0;
-+}
-+
-+/*
-+ * Pre-request source and destination descriptor for enqueue.
-+ */
-+static int fsl_qdma_pre_request_enqueue_sd_desc(struct fsl_qdma_queue *queue)
-+{
-+	struct fsl_qdma_comp *comp_temp, *_comp_temp;
-+
-+	list_for_each_entry_safe(comp_temp, _comp_temp,
-+				&queue->comp_free, list) {
-+		comp_temp->desc_virt_addr = dma_pool_alloc(queue->desc_pool,
-+						GFP_KERNEL,
-+						&comp_temp->desc_bus_addr);
-+		if (!comp_temp->desc_virt_addr)
-+			return -ENOMEM;
-+	}
-+
 +	return 0;
 +}
 +
@@ -3540,90 +3624,152 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 + * Request a command descriptor for enqueue.
 + */
 +static struct fsl_qdma_comp *fsl_qdma_request_enqueue_desc(
-+					struct fsl_qdma_chan *fsl_chan)
++					struct fsl_qdma_chan *fsl_chan,
++					unsigned int dst_nents,
++					unsigned int src_nents)
 +{
 +	struct fsl_qdma_comp *comp_temp;
++	struct fsl_qdma_sg *sg_block;
 +	struct fsl_qdma_queue *queue = fsl_chan->queue;
 +	unsigned long flags;
-+	int timeout = COMP_TIMEOUT;
++	unsigned int dst_sg_entry_block, src_sg_entry_block, sg_entry_total, i;
 +
-+	while (timeout) {
-+		spin_lock_irqsave(&queue->queue_lock, flags);
-+		if (!list_empty(&queue->comp_free)) {
-+			comp_temp = list_first_entry(&queue->comp_free,
++	spin_lock_irqsave(&queue->queue_lock, flags);
++	if (list_empty(&queue->comp_free)) {
++		spin_unlock_irqrestore(&queue->queue_lock, flags);
++		comp_temp = kzalloc(sizeof(*comp_temp), GFP_KERNEL);
++		if (!comp_temp)
++			return NULL;
++		comp_temp->virt_addr = dma_pool_alloc(queue->comp_pool,
++						      GFP_NOWAIT,
++						      &comp_temp->bus_addr);
++		if (!comp_temp->virt_addr)
++			return NULL;
++	} else {
++		comp_temp = list_first_entry(&queue->comp_free,
 +					     struct fsl_qdma_comp,
 +					     list);
-+			list_del(&comp_temp->list);
-+
-+			spin_unlock_irqrestore(&queue->queue_lock, flags);
-+			comp_temp->qchan = fsl_chan;
-+			return comp_temp;
-+		}
++		list_del(&comp_temp->list);
 +		spin_unlock_irqrestore(&queue->queue_lock, flags);
-+		udelay(1);
-+		timeout--;
 +	}
 +
-+	return NULL;
++	if (dst_nents != 0)
++		dst_sg_entry_block = dst_nents /
++					(FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1) + 1;
++	else
++		dst_sg_entry_block = 0;
++
++	if (src_nents != 0)
++		src_sg_entry_block = src_nents /
++					(FSL_QDMA_EXPECT_SG_ENTRY_NUM - 1) + 1;
++	else
++		src_sg_entry_block = 0;
++
++	sg_entry_total = dst_sg_entry_block + src_sg_entry_block;
++	if (sg_entry_total) {
++		sg_block = kzalloc(sizeof(*sg_block) *
++					      sg_entry_total,
++					      GFP_KERNEL);
++		if (!sg_block)
++			return NULL;
++		comp_temp->sg_block = sg_block;
++		for (i = 0; i < sg_entry_total; i++) {
++			sg_block->virt_addr = dma_pool_alloc(queue->sg_pool,
++							GFP_NOWAIT,
++							&sg_block->bus_addr);
++			memset(sg_block->virt_addr, 0,
++					FSL_QDMA_EXPECT_SG_ENTRY_NUM * 16);
++			sg_block++;
++		}
++	}
++
++	comp_temp->sg_block_src = src_sg_entry_block;
++	comp_temp->sg_block_dst = dst_sg_entry_block;
++	comp_temp->qchan = fsl_chan;
++
++	return comp_temp;
 +}
 +
 +static struct fsl_qdma_queue *fsl_qdma_alloc_queue_resources(
 +					struct platform_device *pdev,
-+					struct fsl_qdma_engine *fsl_qdma)
++					unsigned int queue_num)
 +{
++	struct device_node *np = pdev->dev.of_node;
 +	struct fsl_qdma_queue *queue_head, *queue_temp;
-+	int ret, len, i, j;
++	int ret, len, i;
 +	unsigned int queue_size[FSL_QDMA_QUEUE_MAX];
-+	int queue_num;
-+	int block_number;
-+
-+	queue_num = fsl_qdma->n_queues;
-+	block_number = fsl_qdma->block_number;
 +
 +	if (queue_num > FSL_QDMA_QUEUE_MAX)
 +		queue_num = FSL_QDMA_QUEUE_MAX;
-+	len = sizeof(*queue_head) * queue_num * block_number;
++	len = sizeof(*queue_head) * queue_num;
 +	queue_head = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
 +	if (!queue_head)
 +		return NULL;
 +
-+	ret = device_property_read_u32_array(&pdev->dev, "queue-sizes",
-+					queue_size, queue_num);
++	ret = of_property_read_u32_array(np, "queue-sizes", queue_size,
++								queue_num);
 +	if (ret) {
 +		dev_err(&pdev->dev, "Can't get queue-sizes.\n");
 +		return NULL;
 +	}
-+	for (j = 0; j < block_number; j++) {
-+		for (i = 0; i < queue_num; i++) {
-+			if (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
-+			   queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
-+				dev_err(&pdev->dev,
-+				       "Get wrong queue-sizes.\n");
-+				return NULL;
-+			}
-+			queue_temp = queue_head + i + (j * queue_num);
 +
-+			queue_temp->cq =
-+			dma_alloc_coherent(&pdev->dev,
-+					sizeof(struct fsl_qdma_format) *
-+					queue_size[i],
-+					&queue_temp->bus_addr,
-+					GFP_KERNEL);
-+			if (!queue_temp->cq)
-+				return NULL;
-+			queue_temp->block_base = fsl_qdma->block_base +
-+				FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
-+			queue_temp->n_cq = queue_size[i];
-+			queue_temp->id = i;
-+			queue_temp->virt_head = queue_temp->cq;
-+			queue_temp->virt_tail = queue_temp->cq;
-+			/*
-+			 * List for queue command buffer
-+			 */
-+			INIT_LIST_HEAD(&queue_temp->comp_used);
-+			spin_lock_init(&queue_temp->queue_lock);
++	for (i = 0; i < queue_num; i++) {
++		if (queue_size[i] > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX
++			|| queue_size[i] < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
++			dev_err(&pdev->dev, "Get wrong queue-sizes.\n");
++			return NULL;
 +		}
++		queue_temp = queue_head + i;
++		queue_temp->cq = dma_alloc_coherent(&pdev->dev,
++						sizeof(struct fsl_qdma_ccdf) *
++						queue_size[i],
++						&queue_temp->bus_addr,
++						GFP_KERNEL);
++		if (!queue_temp->cq)
++			return NULL;
++		queue_temp->n_cq = queue_size[i];
++		queue_temp->id = i;
++		queue_temp->virt_head = queue_temp->cq;
++		queue_temp->virt_tail = queue_temp->cq;
++		/*
++		 * The dma pool for queue command buffer
++		 */
++		queue_temp->comp_pool = dma_pool_create("comp_pool",
++						&pdev->dev,
++						FSL_QDMA_BASE_BUFFER_SIZE,
++						16, 0);
++		if (!queue_temp->comp_pool) {
++			dma_free_coherent(&pdev->dev,
++						sizeof(struct fsl_qdma_ccdf) *
++						queue_size[i],
++						queue_temp->cq,
++						queue_temp->bus_addr);
++			return NULL;
++		}
++		/*
++		 * The dma pool for queue command buffer
++		 */
++		queue_temp->sg_pool = dma_pool_create("sg_pool",
++					&pdev->dev,
++					FSL_QDMA_EXPECT_SG_ENTRY_NUM * 16,
++					64, 0);
++		if (!queue_temp->sg_pool) {
++			dma_free_coherent(&pdev->dev,
++						sizeof(struct fsl_qdma_ccdf) *
++						queue_size[i],
++						queue_temp->cq,
++						queue_temp->bus_addr);
++			dma_pool_destroy(queue_temp->comp_pool);
++			return NULL;
++		}
++		/*
++		 * List for queue command buffer
++		 */
++		INIT_LIST_HEAD(&queue_temp->comp_used);
++		INIT_LIST_HEAD(&queue_temp->comp_free);
++		spin_lock_init(&queue_temp->queue_lock);
 +	}
++
 +	return queue_head;
 +}
 +
@@ -3654,7 +3800,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	 * Buffer for queue command
 +	 */
 +	status_head->cq = dma_alloc_coherent(&pdev->dev,
-+						sizeof(struct fsl_qdma_format) *
++						sizeof(struct fsl_qdma_ccdf) *
 +						status_size,
 +						&status_head->bus_addr,
 +						GFP_KERNEL);
@@ -3671,21 +3817,17 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
 +{
 +	void __iomem *ctrl = fsl_qdma->ctrl_base;
-+	void __iomem *block;
++	void __iomem *block = fsl_qdma->block_base;
 +	int i, count = 5;
-+	int j;
 +	u32 reg;
 +
 +	/* Disable the command queue and wait for idle state. */
 +	reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
 +	reg |= FSL_QDMA_DMR_DQD;
 +	qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
-+	for (j = 0; j < fsl_qdma->block_number; j++) {
-+		block = fsl_qdma->block_base +
-+			FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
-+		for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)
-+			qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQMR(i));
-+	}
++	for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)
++		qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQMR(i));
++
 +	while (1) {
 +		reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DSR);
 +		if (!(reg & FSL_QDMA_DSR_DB))
@@ -3695,34 +3837,26 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		udelay(100);
 +	}
 +
-+	for (j = 0; j < fsl_qdma->block_number; j++) {
++	/* Disable status queue. */
++	qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BSQMR);
 +
-+		block = fsl_qdma->block_base +
-+			FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
-+
-+		/* Disable status queue. */
-+		qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BSQMR);
-+
-+		/*
-+		 * clear the command queue interrupt detect register for
-+		 * all queues.
-+		 */
-+		qdma_writel(fsl_qdma, 0xffffffff, block + FSL_QDMA_BCQIDR(0));
-+	}
++	/*
++	 * Clear the command queue interrupt detect register for all queues.
++	 */
++	qdma_writel(fsl_qdma, 0xffffffff, block + FSL_QDMA_BCQIDR(0));
 +
 +	return 0;
 +}
 +
-+static int fsl_qdma_queue_transfer_complete(
-+				struct fsl_qdma_engine *fsl_qdma,
-+				void *block,
-+				int id)
++static int fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma)
 +{
 +	struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
-+	struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];
++	struct fsl_qdma_queue *fsl_status = fsl_qdma->status;
 +	struct fsl_qdma_queue *temp_queue;
-+	struct fsl_qdma_format *status_addr;
-+	struct fsl_qdma_comp *fsl_comp = NULL;
++	struct fsl_qdma_comp *fsl_comp;
++	struct fsl_qdma_ccdf *status_addr;
++	struct fsl_qdma_csgf *csgf_src;
++	void __iomem *block = fsl_qdma->block_base;
 +	u32 reg, i;
 +	bool duplicate, duplicate_handle;
 +
@@ -3732,20 +3866,14 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQSR);
 +		if (reg & FSL_QDMA_BSQSR_QE)
 +			return 0;
-+
 +		status_addr = fsl_status->virt_head;
-+
-+		if (qdma_ccdf_get_queue(status_addr) ==
-+		   __this_cpu_read(pre_queue) &&
-+			qdma_ccdf_addr_get64(status_addr) ==
-+			__this_cpu_read(pre_addr))
++		if (qdma_ccdf_get_queue(status_addr) == pre_queue &&
++			qdma_ccdf_addr_get64(status_addr) == pre_addr)
 +			duplicate = 1;
-+		i = qdma_ccdf_get_queue(status_addr) +
-+			id * fsl_qdma->n_queues;
-+		__this_cpu_write(pre_addr, qdma_ccdf_addr_get64(status_addr));
-+		__this_cpu_write(pre_queue, qdma_ccdf_get_queue(status_addr));
++		i = qdma_ccdf_get_queue(status_addr);
++		pre_queue = qdma_ccdf_get_queue(status_addr);
++		pre_addr = qdma_ccdf_addr_get64(status_addr);
 +		temp_queue = fsl_queue + i;
-+
 +		spin_lock(&temp_queue->queue_lock);
 +		if (list_empty(&temp_queue->comp_used)) {
 +			if (duplicate)
@@ -3758,8 +3886,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			fsl_comp = list_first_entry(&temp_queue->comp_used,
 +							struct fsl_qdma_comp,
 +							list);
-+			if (fsl_comp->bus_addr + 16 !=
-+				__this_cpu_read(pre_addr)) {
++			csgf_src = (struct fsl_qdma_csgf *)fsl_comp->virt_addr
++							   + 2;
++			if (fsl_comp->bus_addr + 16 != pre_addr) {
 +				if (duplicate)
 +					duplicate_handle = 1;
 +				else {
@@ -3767,13 +3896,12 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +					return -1;
 +				}
 +			}
-+
 +		}
 +
-+		if (duplicate_handle) {
++			if (duplicate_handle) {
 +			reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
 +			reg |= FSL_QDMA_BSQMR_DI;
-+			qdma_desc_addr_set64(status_addr, 0x0);
++			qdma_ccdf_addr_set64(status_addr, 0x0);
 +			fsl_status->virt_head++;
 +			if (fsl_status->virt_head == fsl_status->cq
 +						   + fsl_status->n_cq)
@@ -3786,7 +3914,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +		reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
 +		reg |= FSL_QDMA_BSQMR_DI;
-+		qdma_desc_addr_set64(status_addr, 0x0);
++		qdma_ccdf_addr_set64(status_addr, 0x0);
 +		fsl_status->virt_head++;
 +		if (fsl_status->virt_head == fsl_status->cq + fsl_status->n_cq)
 +			fsl_status->virt_head = fsl_status->cq;
@@ -3820,24 +3948,13 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +{
 +	struct fsl_qdma_engine *fsl_qdma = dev_id;
 +	unsigned int intr, reg;
++	void __iomem *block = fsl_qdma->block_base;
 +	void __iomem *ctrl = fsl_qdma->ctrl_base;
-+	void __iomem *block;
-+	int id;
-+
-+	id = irq - fsl_qdma->irq_base;
-+	if (id < 0 && id > fsl_qdma->block_number) {
-+		dev_err(fsl_qdma->dma_dev.dev,
-+			"irq %d is wrong irq_base is %d\n",
-+			irq, fsl_qdma->irq_base);
-+	}
-+
-+	block = fsl_qdma->block_base +
-+		FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
 +
 +	intr = qdma_readl(fsl_qdma, block + FSL_QDMA_BCQIDR(0));
 +
 +	if ((intr & FSL_QDMA_CQIDR_SQT) != 0)
-+		intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id);
++		intr = fsl_qdma_queue_transfer_complete(fsl_qdma);
 +
 +	if (intr != 0) {
 +		reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
@@ -3856,9 +3973,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +fsl_qdma_irq_init(struct platform_device *pdev,
 +		  struct fsl_qdma_engine *fsl_qdma)
 +{
-+	char irq_name[20];
-+	int i;
-+	int cpu;
 +	int ret;
 +
 +	fsl_qdma->error_irq = platform_get_irq_byname(pdev,
@@ -3868,72 +3982,36 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return fsl_qdma->error_irq;
 +	}
 +
++	fsl_qdma->queue_irq = platform_get_irq_byname(pdev, "qdma-queue");
++	if (fsl_qdma->queue_irq < 0) {
++		dev_err(&pdev->dev, "Can't get qdma queue irq.\n");
++		return fsl_qdma->queue_irq;
++	}
++
 +	ret = devm_request_irq(&pdev->dev, fsl_qdma->error_irq,
 +			fsl_qdma_error_handler, 0, "qDMA error", fsl_qdma);
 +	if (ret) {
 +		dev_err(&pdev->dev, "Can't register qDMA controller IRQ.\n");
 +		return  ret;
 +	}
-+
-+	for (i = 0; i < fsl_qdma->block_number; i++) {
-+		sprintf(irq_name, "qdma-queue%d", i);
-+		fsl_qdma->queue_irq[i] = platform_get_irq_byname(pdev,
-+								irq_name);
-+
-+		if (fsl_qdma->queue_irq[i] < 0) {
-+			dev_err(&pdev->dev,
-+				   "Can't get qdma queue %d irq.\n",
-+				   i);
-+			return fsl_qdma->queue_irq[i];
-+		}
-+
-+		ret = devm_request_irq(&pdev->dev,
-+				      fsl_qdma->queue_irq[i],
-+				      fsl_qdma_queue_handler,
-+				      0,
-+				      "qDMA queue",
-+				      fsl_qdma);
-+		if (ret) {
-+			dev_err(&pdev->dev,
-+			       "Can't register qDMA queue IRQ.\n");
-+			return  ret;
-+		}
-+
-+		cpu = i % num_online_cpus();
-+		ret = irq_set_affinity_hint(fsl_qdma->queue_irq[i],
-+					   get_cpu_mask(cpu));
-+		if (ret) {
-+			dev_err(&pdev->dev,
-+			       "Can't set cpu %d affinity to IRQ %d.\n",
-+				cpu,
-+				fsl_qdma->queue_irq[i]);
-+			return  ret;
-+		}
-+
++	ret = devm_request_irq(&pdev->dev, fsl_qdma->queue_irq,
++			fsl_qdma_queue_handler, 0, "qDMA queue", fsl_qdma);
++	if (ret) {
++		dev_err(&pdev->dev, "Can't register qDMA queue IRQ.\n");
++		return  ret;
 +	}
 +
 +	return 0;
 +}
 +
-+static void fsl_qdma_irq_exit(
-+		struct platform_device *pdev, struct fsl_qdma_engine *fsl_qdma)
-+{
-+	if (fsl_qdma->queue_irq[0] == fsl_qdma->error_irq) {
-+		devm_free_irq(&pdev->dev, fsl_qdma->queue_irq[0], fsl_qdma);
-+	} else {
-+		devm_free_irq(&pdev->dev, fsl_qdma->queue_irq[0], fsl_qdma);
-+		devm_free_irq(&pdev->dev, fsl_qdma->error_irq, fsl_qdma);
-+	}
-+}
-+
 +static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
 +{
 +	struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
 +	struct fsl_qdma_queue *temp;
 +	void __iomem *ctrl = fsl_qdma->ctrl_base;
 +	void __iomem *status = fsl_qdma->status_base;
-+	void __iomem *block;
-+	int i, j, ret;
++	void __iomem *block = fsl_qdma->block_base;
++	int i, ret;
 +	u32 reg;
 +
 +	/* Try to halt the qDMA engine first. */
@@ -3943,86 +4021,65 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return ret;
 +	}
 +
-+	for (i = 0; i < fsl_qdma->block_number; i++) {
++	/*
++	 * Clear the command queue interrupt detect register for all queues.
++	 */
++	qdma_writel(fsl_qdma, 0xffffffff, block + FSL_QDMA_BCQIDR(0));
++
++	for (i = 0; i < fsl_qdma->n_queues; i++) {
++		temp = fsl_queue + i;
 +		/*
-+		 * Clear the command queue interrupt detect register for
-+		 * all queues.
-+		 */
-+
-+		block = fsl_qdma->block_base +
-+			FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, i);
-+		qdma_writel(fsl_qdma, 0xffffffff, block + FSL_QDMA_BCQIDR(0));
-+	}
-+
-+	for (j = 0; j < fsl_qdma->block_number; j++) {
-+		block = fsl_qdma->block_base +
-+			FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
-+		for (i = 0; i < fsl_qdma->n_queues; i++) {
-+			temp = fsl_queue + i + (j * fsl_qdma->n_queues);
-+			/*
-+			 * Initialize Command Queue registers to
-+			 * point to the first
-+			 * command descriptor in memory.
-+			 * Dequeue Pointer Address Registers
-+			 * Enqueue Pointer Address Registers
-+			 */
-+
-+			qdma_writel(fsl_qdma, temp->bus_addr,
-+					   block + FSL_QDMA_BCQDPA_SADDR(i));
-+			qdma_writel(fsl_qdma, temp->bus_addr,
-+					   block + FSL_QDMA_BCQEPA_SADDR(i));
-+
-+			/* Initialize the queue mode. */
-+			reg = FSL_QDMA_BCQMR_EN;
-+			reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq) - 4);
-+			reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq) - 6);
-+			qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BCQMR(i));
-+		}
-+
-+		/*
-+		 * Workaround for erratum: ERR010812.
-+		 * We must enable XOFF to avoid the enqueue rejection occurs.
-+		 * Setting SQCCMR ENTER_WM to 0x20.
-+		 */
-+
-+		qdma_writel(fsl_qdma, FSL_QDMA_SQCCMR_ENTER_WM,
-+				   block + FSL_QDMA_SQCCMR);
-+
-+		/*
-+		 * Initialize status queue registers to point to the first
++		 * Initialize Command Queue registers to point to the first
 +		 * command descriptor in memory.
 +		 * Dequeue Pointer Address Registers
 +		 * Enqueue Pointer Address Registers
 +		 */
++		qdma_writel(fsl_qdma, temp->bus_addr,
++				block + FSL_QDMA_BCQDPA_SADDR(i));
++		qdma_writel(fsl_qdma, temp->bus_addr,
++				block + FSL_QDMA_BCQEPA_SADDR(i));
 +
-+		qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
-+				   block + FSL_QDMA_SQEPAR);
-+		qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
-+				   block + FSL_QDMA_SQDPAR);
-+		/* Initialize status queue interrupt. */
-+		qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE,
-+				   block + FSL_QDMA_BCQIER(0));
-+		qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN |
-+				   FSL_QDMA_BSQICR_ICST(5) | 0x8000,
-+				   block + FSL_QDMA_BSQICR);
-+		qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE |
-+				   FSL_QDMA_CQIER_TEIE,
-+				   block + FSL_QDMA_CQIER);
-+
-+		/* Initialize the status queue mode. */
-+		reg = FSL_QDMA_BSQMR_EN;
-+		reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2(
-+			fsl_qdma->status[j]->n_cq) - 6);
-+
-+		qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
-+		reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
-+
++		/* Initialize the queue mode. */
++		reg = FSL_QDMA_BCQMR_EN;
++		reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq)-4);
++		reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq)-6);
++		qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BCQMR(i));
 +	}
 +
++	/*
++	 * Workaround for erratum: ERR010812.
++	 * We must enable XOFF to avoid the enqueue rejection occurs.
++	 * Setting SQCCMR ENTER_WM to 0x20.
++	 */
++	qdma_writel(fsl_qdma, FSL_QDMA_SQCCMR_ENTER_WM,
++			      block + FSL_QDMA_SQCCMR);
++	/*
++	 * Initialize status queue registers to point to the first
++	 * command descriptor in memory.
++	 * Dequeue Pointer Address Registers
++	 * Enqueue Pointer Address Registers
++	 */
++	qdma_writel(fsl_qdma, fsl_qdma->status->bus_addr,
++					block + FSL_QDMA_SQEPAR);
++	qdma_writel(fsl_qdma, fsl_qdma->status->bus_addr,
++					block + FSL_QDMA_SQDPAR);
++	/* Initialize status queue interrupt. */
++	qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE,
++			      block + FSL_QDMA_BCQIER(0));
++	qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN | FSL_QDMA_BSQICR_ICST(5)
++						   | 0x8000,
++			      block + FSL_QDMA_BSQICR);
++	qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE | FSL_QDMA_CQIER_TEIE,
++			      block + FSL_QDMA_CQIER);
 +	/* Initialize controller interrupt register. */
 +	qdma_writel(fsl_qdma, 0xffffffff, status + FSL_QDMA_DEDR);
 +	qdma_writel(fsl_qdma, 0xffffffff, status + FSL_QDMA_DEIER);
 +
++	/* Initialize the status queue mode. */
++	reg = FSL_QDMA_BSQMR_EN;
++	reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2(fsl_qdma->status->n_cq)-6);
++	qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
++
 +	reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
 +	reg &= ~FSL_QDMA_DMR_DQD;
 +	qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
@@ -4030,6 +4087,23 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	return 0;
 +}
 +
++static struct dma_async_tx_descriptor *fsl_qdma_prep_dma_sg(
++		struct dma_chan *chan,
++		struct scatterlist *dst_sg, unsigned int dst_nents,
++		struct scatterlist *src_sg, unsigned int src_nents,
++		unsigned long flags)
++{
++	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
++	struct fsl_qdma_comp *fsl_comp;
++
++	fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan,
++						 dst_nents,
++						 src_nents);
++	fsl_qdma_comp_fill_sg(fsl_comp, dst_sg, dst_nents, src_sg, src_nents);
++
++	return vchan_tx_prep(&fsl_chan->vchan, &fsl_comp->vdesc, flags);
++}
++
 +static struct dma_async_tx_descriptor *
 +fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
 +		dma_addr_t src, size_t len, unsigned long flags)
@@ -4037,11 +4111,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
 +	struct fsl_qdma_comp *fsl_comp;
 +
-+	fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan);
-+
-+	if (!fsl_comp)
-+		return NULL;
-+
++	fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan, 0, 0);
 +	fsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len);
 +
 +	return vchan_tx_prep(&fsl_chan->vchan, &fsl_comp->vdesc, flags);
@@ -4049,10 +4119,10 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
 +{
++	void __iomem *block = fsl_chan->qdma->block_base;
 +	struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
 +	struct fsl_qdma_comp *fsl_comp;
 +	struct virt_dma_desc *vdesc;
-+	void __iomem *block = fsl_queue->block_base;
 +	u32 reg;
 +
 +	reg = qdma_readl(fsl_chan->qdma, block + FSL_QDMA_BCQSR(fsl_queue->id));
@@ -4086,11 +4156,24 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +{
 +	struct fsl_qdma_comp *fsl_comp;
 +	struct fsl_qdma_queue *fsl_queue;
++	struct fsl_qdma_sg *sg_block;
 +	unsigned long flags;
++	unsigned int i;
 +
 +	fsl_comp = to_fsl_qdma_comp(vdesc);
 +	fsl_queue = fsl_comp->qchan->queue;
 +
++	if (fsl_comp->sg_block) {
++		for (i = 0; i < fsl_comp->sg_block_src +
++				fsl_comp->sg_block_dst; i++) {
++			sg_block = fsl_comp->sg_block + i;
++			dma_pool_free(fsl_queue->sg_pool,
++				      sg_block->virt_addr,
++				      sg_block->bus_addr);
++		}
++		kfree(fsl_comp->sg_block);
++	}
++
 +	spin_lock_irqsave(&fsl_queue->queue_lock, flags);
 +	list_add_tail(&fsl_comp->list, &fsl_queue->comp_free);
 +	spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
@@ -4110,84 +4193,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
 +}
 +
-+static void fsl_qdma_synchronize(struct dma_chan *chan)
-+{
-+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
-+
-+	vchan_synchronize(&fsl_chan->vchan);
-+}
-+
-+static int fsl_qdma_terminate_all(struct dma_chan *chan)
-+{
-+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
-+	unsigned long flags;
-+	LIST_HEAD(head);
-+
-+	spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
-+	vchan_get_all_descriptors(&fsl_chan->vchan, &head);
-+	spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
-+	vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
-+	return 0;
-+}
-+
-+static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
-+{
-+	struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
-+	struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
-+	struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
-+	int ret;
-+
-+	if (fsl_queue->comp_pool && fsl_queue->desc_pool)
-+		return fsl_qdma->desc_allocated;
-+
-+	INIT_LIST_HEAD(&fsl_queue->comp_free);
-+
-+	/*
-+	 * The dma pool for queue command buffer
-+	 */
-+	fsl_queue->comp_pool =
-+	dma_pool_create("comp_pool",
-+		       chan->device->dev,
-+		       FSL_QDMA_COMMAND_BUFFER_SIZE,
-+		       64, 0);
-+	if (!fsl_queue->comp_pool)
-+		return -ENOMEM;
-+
-+	/*
-+	 * The dma pool for Descriptor(SD/DD) buffer
-+	 */
-+	fsl_queue->desc_pool =
-+	dma_pool_create("desc_pool",
-+		       chan->device->dev,
-+		       FSL_QDMA_DESCRIPTOR_BUFFER_SIZE,
-+		       32, 0);
-+	if (!fsl_queue->desc_pool)
-+		goto err_desc_pool;
-+
-+	ret = fsl_qdma_pre_request_enqueue_comp_desc(fsl_queue);
-+	if (ret) {
-+		dev_err(chan->device->dev, "failed to alloc dma buffer for "
-+				"comp S/G descriptor\n");
-+		goto err_mem;
-+	}
-+
-+	ret = fsl_qdma_pre_request_enqueue_sd_desc(fsl_queue);
-+	if (ret) {
-+		dev_err(chan->device->dev, "failed to alloc dma buffer for "
-+				"S/D descriptor\n");
-+		goto err_mem;
-+	}
-+
-+	fsl_qdma->desc_allocated++;
-+	return fsl_qdma->desc_allocated;
-+
-+err_mem:
-+	dma_pool_destroy(fsl_queue->desc_pool);
-+err_desc_pool:
-+	dma_pool_destroy(fsl_queue->comp_pool);
-+	return -ENOMEM;
-+}
-+
 +static int fsl_qdma_probe(struct platform_device *pdev)
 +{
 +	struct device_node *np = pdev->dev.of_node;
@@ -4196,8 +4201,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	struct resource *res;
 +	unsigned int len, chans, queues;
 +	int ret, i;
-+	int blk_num;
-+	int blk_off;
 +
 +	ret = of_property_read_u32(np, "channels", &chans);
 +	if (ret) {
@@ -4205,59 +4208,29 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return ret;
 +	}
 +
-+	ret = of_property_read_u32(np, "block-offset", &blk_off);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Can't get block-offset.\n");
-+		return ret;
-+	}
-+
-+	ret = of_property_read_u32(np, "block-number", &blk_num);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Can't get block-number.\n");
-+		return ret;
-+	}
-+
-+	blk_num = min_t(int, blk_num, num_online_cpus());
-+
-+	len = sizeof(*fsl_qdma);
++	len = sizeof(*fsl_qdma) + sizeof(*fsl_chan) * chans;
 +	fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
 +	if (!fsl_qdma)
 +		return -ENOMEM;
 +
-+	len = sizeof(*fsl_chan) * chans;
-+	fsl_qdma->chans = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
-+	if (!fsl_qdma->chans)
-+		return -ENOMEM;
-+
-+	len = sizeof(struct fsl_qdma_queue *) * blk_num;
-+	fsl_qdma->status = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
-+	if (!fsl_qdma->status)
-+		return -ENOMEM;
-+
-+	len = sizeof(int) * blk_num;
-+	fsl_qdma->queue_irq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
-+	if (!fsl_qdma->queue_irq)
-+		return -ENOMEM;
-+
 +	ret = of_property_read_u32(np, "queues", &queues);
 +	if (ret) {
 +		dev_err(&pdev->dev, "Can't get queues.\n");
 +		return ret;
 +	}
 +
-+	fsl_qdma->desc_allocated = 0;
++	fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, queues);
++	if (!fsl_qdma->queue)
++		return -ENOMEM;
++
++	fsl_qdma->status = fsl_qdma_prep_status_queue(pdev);
++	if (!fsl_qdma->status)
++		return -ENOMEM;
++
 +	fsl_qdma->n_chans = chans;
 +	fsl_qdma->n_queues = queues;
-+	fsl_qdma->block_number = blk_num;
-+	fsl_qdma->block_offset = blk_off;
-+
 +	mutex_init(&fsl_qdma->fsl_qdma_mutex);
 +
-+	for (i = 0; i < fsl_qdma->block_number; i++) {
-+		fsl_qdma->status[i] = fsl_qdma_prep_status_queue(pdev);
-+		if (!fsl_qdma->status[i])
-+			return -ENOMEM;
-+	}
 +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 +	fsl_qdma->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
 +	if (IS_ERR(fsl_qdma->ctrl_base))
@@ -4272,40 +4245,37 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	fsl_qdma->block_base = devm_ioremap_resource(&pdev->dev, res);
 +	if (IS_ERR(fsl_qdma->block_base))
 +		return PTR_ERR(fsl_qdma->block_base);
-+	fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, fsl_qdma);
-+	if (!fsl_qdma->queue)
-+		return -ENOMEM;
 +
 +	ret = fsl_qdma_irq_init(pdev, fsl_qdma);
 +	if (ret)
 +		return ret;
 +
-+	fsl_qdma->irq_base = platform_get_irq_byname(pdev, "qdma-queue0");
 +	fsl_qdma->big_endian = of_property_read_bool(np, "big-endian");
 +	INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
-+
 +	for (i = 0; i < fsl_qdma->n_chans; i++) {
 +		struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
 +
 +		fsl_chan->qdma = fsl_qdma;
-+		fsl_chan->queue = fsl_qdma->queue + i % (fsl_qdma->n_queues *
-+							fsl_qdma->block_number);
++		fsl_chan->queue = fsl_qdma->queue + i % fsl_qdma->n_queues;
 +		fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
++		INIT_LIST_HEAD(&fsl_chan->qcomp);
 +		vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
 +	}
++	for (i = 0; i < fsl_qdma->n_queues; i++)
++		fsl_qdma_pre_request_enqueue_desc(fsl_qdma->queue + i);
 +
 +	dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
++	dma_cap_set(DMA_SG, fsl_qdma->dma_dev.cap_mask);
 +
 +	fsl_qdma->dma_dev.dev = &pdev->dev;
-+	fsl_qdma->dma_dev.device_free_chan_resources
-+		= fsl_qdma_free_chan_resources;
 +	fsl_qdma->dma_dev.device_alloc_chan_resources
 +		= fsl_qdma_alloc_chan_resources;
++	fsl_qdma->dma_dev.device_free_chan_resources
++		= fsl_qdma_free_chan_resources;
 +	fsl_qdma->dma_dev.device_tx_status = fsl_qdma_tx_status;
 +	fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
++	fsl_qdma->dma_dev.device_prep_dma_sg = fsl_qdma_prep_dma_sg;
 +	fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
-+	fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
-+	fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all;
 +
 +	dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
 +
@@ -4313,8 +4283,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +	ret = dma_async_device_register(&fsl_qdma->dma_dev);
 +	if (ret) {
-+		dev_err(&pdev->dev,
-+			"Can't register NXP Layerscape qDMA engine.\n");
++		dev_err(&pdev->dev, "Can't register Freescale qDMA engine.\n");
 +		return ret;
 +	}
 +
@@ -4324,37 +4293,49 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +		return ret;
 +	}
 +
++
 +	return 0;
 +}
 +
-+static void fsl_qdma_cleanup_vchan(struct dma_device *dmadev)
-+{
-+	struct fsl_qdma_chan *chan, *_chan;
-+
-+	list_for_each_entry_safe(chan, _chan,
-+				&dmadev->channels, vchan.chan.device_node) {
-+		list_del(&chan->vchan.chan.device_node);
-+		tasklet_kill(&chan->vchan.task);
-+	}
-+}
-+
 +static int fsl_qdma_remove(struct platform_device *pdev)
 +{
 +	struct device_node *np = pdev->dev.of_node;
 +	struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
-+	struct fsl_qdma_queue *status;
++	struct fsl_qdma_queue *queue_temp;
++	struct fsl_qdma_queue *status = fsl_qdma->status;
++	struct fsl_qdma_comp *comp_temp, *_comp_temp;
 +	int i;
 +
-+	fsl_qdma_irq_exit(pdev, fsl_qdma);
-+	fsl_qdma_cleanup_vchan(&fsl_qdma->dma_dev);
 +	of_dma_controller_free(np);
 +	dma_async_device_unregister(&fsl_qdma->dma_dev);
 +
-+	for (i = 0; i < fsl_qdma->block_number; i++) {
-+		status = fsl_qdma->status[i];
-+		dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_format) *
-+				status->n_cq, status->cq, status->bus_addr);
++	/* Free descriptor areas */
++	for (i = 0; i < fsl_qdma->n_queues; i++) {
++		queue_temp = fsl_qdma->queue + i;
++		list_for_each_entry_safe(comp_temp, _comp_temp,
++					&queue_temp->comp_used,	list) {
++			dma_pool_free(queue_temp->comp_pool,
++					comp_temp->virt_addr,
++					comp_temp->bus_addr);
++			list_del(&comp_temp->list);
++			kfree(comp_temp);
++		}
++		list_for_each_entry_safe(comp_temp, _comp_temp,
++					&queue_temp->comp_free, list) {
++			dma_pool_free(queue_temp->comp_pool,
++					comp_temp->virt_addr,
++					comp_temp->bus_addr);
++			list_del(&comp_temp->list);
++			kfree(comp_temp);
++		}
++		dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
++					queue_temp->n_cq, queue_temp->cq,
++					queue_temp->bus_addr);
++		dma_pool_destroy(queue_temp->comp_pool);
 +	}
++
++	dma_free_coherent(&pdev->dev, sizeof(struct fsl_qdma_ccdf) *
++				status->n_cq, status->cq, status->bus_addr);
 +	return 0;
 +}
 +
@@ -4367,14 +4348,25 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +static struct platform_driver fsl_qdma_driver = {
 +	.driver		= {
 +		.name	= "fsl-qdma",
++		.owner  = THIS_MODULE,
 +		.of_match_table = fsl_qdma_dt_ids,
 +	},
 +	.probe          = fsl_qdma_probe,
 +	.remove		= fsl_qdma_remove,
 +};
 +
-+module_platform_driver(fsl_qdma_driver);
++static int __init fsl_qdma_init(void)
++{
++	return platform_driver_register(&fsl_qdma_driver);
++}
++subsys_initcall(fsl_qdma_init);
++
++static void __exit fsl_qdma_exit(void)
++{
++	platform_driver_unregister(&fsl_qdma_driver);
++}
++module_exit(fsl_qdma_exit);
 +
 +MODULE_ALIAS("platform:fsl-qdma");
-+MODULE_DESCRIPTION("NXP Layerscape qDMA engine driver");
++MODULE_DESCRIPTION("Freescale qDMA engine driver");
 +MODULE_LICENSE("GPL v2");
diff --git a/target/linux/layerscape/patches-4.14/803-flextimer-support-layerscape.patch b/target/linux/layerscape/patches-4.9/806-flextimer-support-layerscape.patch
similarity index 72%
rename from target/linux/layerscape/patches-4.14/803-flextimer-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/806-flextimer-support-layerscape.patch
index 55ee18511..9826d822e 100644
--- a/target/linux/layerscape/patches-4.14/803-flextimer-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/806-flextimer-support-layerscape.patch
@@ -1,56 +1,19 @@
-From d586effc9b71ddf240fb294b1ab1205bbe6fec4b Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:32 +0800
-Subject: [PATCH 20/40] flextimer: support layerscape
-This is an integrated patch of flextimer for layerscape
+From b92e223750a07b28f175eae97d5ce3978df41be8 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:32:05 +0800
+Subject: [PATCH 18/30] flextimer: support layerscape
 
+This is an integrated patch for layerscape flextimer support.
+
+Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
 Signed-off-by: Meng Yi <meng.yi@nxp.com>
-Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
-Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- .../bindings/soc/fsl/layerscape/ftm-alarm.txt |  32 ++
- drivers/clocksource/fsl_ftm_timer.c           |   8 +-
- drivers/soc/fsl/layerscape/ftm_alarm.c        | 375 ++++++++++++++++++
- 3 files changed, 411 insertions(+), 4 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/soc/fsl/layerscape/ftm-alarm.txt
+ drivers/clocksource/fsl_ftm_timer.c    |   8 +-
+ drivers/soc/fsl/layerscape/ftm_alarm.c | 367 +++++++++++++++++++++++++++++++++
+ 2 files changed, 371 insertions(+), 4 deletions(-)
  create mode 100644 drivers/soc/fsl/layerscape/ftm_alarm.c
 
---- /dev/null
-+++ b/Documentation/devicetree/bindings/soc/fsl/layerscape/ftm-alarm.txt
-@@ -0,0 +1,32 @@
-+Freescale FlexTimer Module (FTM) Alarm
-+
-+Required properties:
-+
-+- compatible : Should be "fsl,ftm-alarm" or "fsl,<chip>-ftm-alarm", the
-+	       supported chips include
-+	       "fsl,ls1012a-ftm-alarm"
-+	       "fsl,ls1021a-ftm-alarm"
-+	       "fsl,ls1043a-ftm-alarm"
-+	       "fsl,ls1046a-ftm-alarm"
-+	       "fsl,ls1088a-ftm-alarm"
-+	       "fsl,ls208xa-ftm-alarm"
-+- reg : Specifies base physical address and size of the register sets for the
-+  FlexTimer Module and base physical address of IP Powerdown Exception Control
-+  Register.
-+- reg-names: names of the mapped memory regions listed in regs property.
-+  should include the following entries:
-+  "ftm":    Address of the register sets for FlexTimer Module
-+  "pmctrl": Address of IP Powerdown Exception Control register
-+- interrupts : Should be the FlexTimer Module interrupt.
-+- big-endian: If the host controller is big-endian mode, specify this property.
-+  The default endian mode is little-endian.
-+
-+Example:
-+ftm0: ftm0@29d0000 {
-+	compatible = "fsl,ls1043a-ftm-alarm";
-+	reg = <0x0 0x29d0000 0x0 0x10000>,
-+	      <0x0 0x1ee2140 0x0 0x4>;
-+	reg-names = "ftm", "pmctrl";
-+	interrupts = <0 86 0x4>;
-+	big-endian;
-+};
 --- a/drivers/clocksource/fsl_ftm_timer.c
 +++ b/drivers/clocksource/fsl_ftm_timer.c
 @@ -83,11 +83,11 @@ static inline void ftm_counter_disable(v
@@ -71,7 +34,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  static inline void ftm_irq_enable(void __iomem *base)
 --- /dev/null
 +++ b/drivers/soc/fsl/layerscape/ftm_alarm.c
-@@ -0,0 +1,375 @@
+@@ -0,0 +1,367 @@
 +/*
 + * Freescale FlexTimer Module (FTM) Alarm driver.
 + *
@@ -115,7 +78,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +static void __iomem *ftm1_base;
 +static void __iomem *rcpm_ftm_addr;
-+static void __iomem *scfg_scrachpad_addr;
 +static u32 alarm_freq;
 +static bool big_endian;
 +
@@ -125,8 +87,8 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +};
 +
 +struct rcpm_cfg {
-+	enum pmu_endian_type big_endian; /* Big/Little endian of PMU module */
-+	u32 flextimer_set_bit;	/* FTM is not powerdown during device LPM20 */
++	enum pmu_endian_type big_endian;	/* Big/Little endian of PMU module */
++	u32 flextimer_set_bit;	/* FlexTimer1 is not powerdown during device LPM20 */
 +};
 +
 +static struct rcpm_cfg ls1012a_rcpm_cfg = {
@@ -136,7 +98,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +
 +static struct rcpm_cfg ls1021a_rcpm_cfg = {
 +	.big_endian = BIG_ENDIAN,
-+	.flextimer_set_bit = 0x30000000,
++	.flextimer_set_bit = 0x20000,
 +};
 +
 +static struct rcpm_cfg ls1043a_rcpm_cfg = {
@@ -160,12 +122,12 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +};
 +
 +static const struct of_device_id ippdexpcr_of_match[] = {
-+	{ .compatible = "fsl,ls1012a-ftm-alarm", .data = &ls1012a_rcpm_cfg},
-+	{ .compatible = "fsl,ls1021a-ftm-alarm", .data = &ls1021a_rcpm_cfg},
-+	{ .compatible = "fsl,ls1043a-ftm-alarm", .data = &ls1043a_rcpm_cfg},
-+	{ .compatible = "fsl,ls1046a-ftm-alarm", .data = &ls1046a_rcpm_cfg},
-+	{ .compatible = "fsl,ls1088a-ftm-alarm", .data = &ls1088a_rcpm_cfg},
-+	{ .compatible = "fsl,ls208xa-ftm-alarm", .data = &ls208xa_rcpm_cfg},
++	{ .compatible = "fsl,ls1012a-ftm", .data = &ls1012a_rcpm_cfg},
++	{ .compatible = "fsl,ls1021a-ftm", .data = &ls1021a_rcpm_cfg},
++	{ .compatible = "fsl,ls1043a-ftm", .data = &ls1043a_rcpm_cfg},
++	{ .compatible = "fsl,ls1046a-ftm", .data = &ls1046a_rcpm_cfg},
++	{ .compatible = "fsl,ls1088a-ftm", .data = &ls1088a_rcpm_cfg},
++	{ .compatible = "fsl,ls208xa-ftm", .data = &ls208xa_rcpm_cfg},
 +	{},
 +};
 +MODULE_DEVICE_TABLE(of, ippdexpcr_of_match);
@@ -365,11 +327,11 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	if (!rcpm_cfg)
 +		return -ENOMEM;
 +
-+	rcpm_cfg = (struct rcpm_cfg *)of_id->data;
++	rcpm_cfg = (struct rcpm_cfg*)of_id->data;
 +	endian = rcpm_cfg->big_endian;
 +	flextimer = rcpm_cfg->flextimer_set_bit;
 +
-+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmctrl");
++	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "FlexTimer1");
 +	if (r) {
 +		rcpm_ftm_addr = devm_ioremap_resource(&pdev->dev, r);
 +		if (IS_ERR(rcpm_ftm_addr))
@@ -383,12 +345,6 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			iowrite32be(ippdexpcr, rcpm_ftm_addr);
 +		else
 +			iowrite32(ippdexpcr, rcpm_ftm_addr);
-+
-+		r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scrachpad");
-+		if (r) {
-+			scfg_scrachpad_addr = devm_ioremap_resource(&pdev->dev, r);
-+			iowrite32(ippdexpcr, scfg_scrachpad_addr);
-+		}
 +	}
 +
 +	irq = irq_of_parse_and_map(np, 0);
@@ -422,13 +378,12 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 +
 +static const struct of_device_id ftm_alarm_match[] = {
-+	{ .compatible = "fsl,ftm-alarm", },
-+	{ .compatible = "fsl,ls1012a-ftm-alarm", },
-+	{ .compatible = "fsl,ls1021a-ftm-alarm", },
-+	{ .compatible = "fsl,ls1043a-ftm-alarm", },
-+	{ .compatible = "fsl,ls1046a-ftm-alarm", },
-+	{ .compatible = "fsl,ls1088a-ftm-alarm", },
-+	{ .compatible = "fsl,ls208xa-ftm-alarm", },
++	{ .compatible = "fsl,ls1012a-ftm", },
++	{ .compatible = "fsl,ls1021a-ftm", },
++	{ .compatible = "fsl,ls1043a-ftm", },
++	{ .compatible = "fsl,ls1046a-ftm", },
++	{ .compatible = "fsl,ls1088a-ftm", },
++	{ .compatible = "fsl,ls208xa-ftm", },
 +	{ .compatible = "fsl,ftm-timer", },
 +	{ },
 +};
diff --git a/target/linux/layerscape/patches-4.9/807-gpu-support-layerscape.patch b/target/linux/layerscape/patches-4.9/807-gpu-support-layerscape.patch
new file mode 100644
index 000000000..5aea9ea73
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/807-gpu-support-layerscape.patch
@@ -0,0 +1,58 @@
+From 177f92a14d8177124f37db0fafc11182e2dcdd62 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:33:05 +0800
+Subject: [PATCH 19/30] gpu: support layerscape
+
+This is an integrated patch for layerscape dcu support.
+
+Signed-off-by: Alison Wang <b18965@freescale.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
++++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+@@ -225,7 +225,6 @@ static int fsl_dcu_drm_pm_suspend(struct
+ 	if (!fsl_dev)
+ 		return 0;
+ 
+-	disable_irq(fsl_dev->irq);
+ 	drm_kms_helper_poll_disable(fsl_dev->drm);
+ 
+ 	console_lock();
+@@ -243,6 +242,8 @@ static int fsl_dcu_drm_pm_suspend(struct
+ 		return PTR_ERR(fsl_dev->state);
+ 	}
+ 
++	disable_irq(fsl_dev->irq);
++
+ 	clk_disable_unprepare(fsl_dev->clk);
+ 
+ 	return 0;
+@@ -262,6 +263,12 @@ static int fsl_dcu_drm_pm_resume(struct
+ 		return ret;
+ 	}
+ 
++	ret = clk_prepare_enable(fsl_dev->pix_clk);
++	if (ret < 0) {
++		dev_err(dev, "failed to enable dcu pix clk\n");
++		return ret;
++	}
++
+ 	if (fsl_dev->tcon)
+ 		fsl_tcon_bypass_enable(fsl_dev->tcon);
+ 	fsl_dcu_drm_init_planes(fsl_dev->drm);
+@@ -388,6 +395,12 @@ static int fsl_dcu_drm_probe(struct plat
+ 		goto disable_clk;
+ 	}
+ 
++	ret = clk_prepare_enable(fsl_dev->pix_clk);
++	if (ret < 0) {
++		dev_err(dev, "failed to enable dcu pix clk\n");
++		return ret;
++	}
++
+ 	fsl_dev->tcon = fsl_tcon_init(dev);
+ 
+ 	drm = drm_dev_alloc(driver, dev);
diff --git a/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch b/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch
new file mode 100644
index 000000000..26412c5eb
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch
@@ -0,0 +1,421 @@
+From 45b0e1589b25ea3106a8c8d18bf653fde95baa9f Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:34:22 +0800
+Subject: [PATCH 20/30] guts: support layerscape
+
+This is an integrated patch for layerscape guts support.
+
+Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/soc/fsl/guts.c   | 238 +++++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/fsl/guts.h | 125 +++++++++++++++----------
+ 2 files changed, 315 insertions(+), 48 deletions(-)
+ create mode 100644 drivers/soc/fsl/guts.c
+
+--- /dev/null
++++ b/drivers/soc/fsl/guts.c
+@@ -0,0 +1,238 @@
++/*
++ * Freescale QorIQ Platforms GUTS Driver
++ *
++ * Copyright (C) 2016 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/of_fdt.h>
++#include <linux/sys_soc.h>
++#include <linux/of_address.h>
++#include <linux/platform_device.h>
++#include <linux/fsl/guts.h>
++
++struct guts {
++	struct ccsr_guts __iomem *regs;
++	bool little_endian;
++};
++
++struct fsl_soc_die_attr {
++	char	*die;
++	u32	svr;
++	u32	mask;
++};
++
++static struct guts *guts;
++static struct soc_device_attribute soc_dev_attr;
++static struct soc_device *soc_dev;
++
++
++/* SoC die attribute definition for QorIQ platform */
++static const struct fsl_soc_die_attr fsl_soc_die[] = {
++	/*
++	 * Power Architecture-based SoCs T Series
++	 */
++
++	/* Die: T4240, SoC: T4240/T4160/T4080 */
++	{ .die		= "T4240",
++	  .svr		= 0x82400000,
++	  .mask		= 0xfff00000,
++	},
++	/* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
++	{ .die		= "T1040",
++	  .svr		= 0x85200000,
++	  .mask		= 0xfff00000,
++	},
++	/* Die: T2080, SoC: T2080/T2081 */
++	{ .die		= "T2080",
++	  .svr		= 0x85300000,
++	  .mask		= 0xfff00000,
++	},
++	/* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
++	{ .die		= "T1024",
++	  .svr		= 0x85400000,
++	  .mask		= 0xfff00000,
++	},
++
++	/*
++	 * ARM-based SoCs LS Series
++	 */
++
++	/* Die: LS1043A, SoC: LS1043A/LS1023A */
++	{ .die		= "LS1043A",
++	  .svr		= 0x87920000,
++	  .mask		= 0xffff0000,
++	},
++	/* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
++	{ .die		= "LS2080A",
++	  .svr		= 0x87010000,
++	  .mask		= 0xff3f0000,
++	},
++	/* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */
++	{ .die		= "LS1088A",
++	  .svr		= 0x87030000,
++	  .mask		= 0xff3f0000,
++	},
++	/* Die: LS1012A, SoC: LS1012A */
++	{ .die		= "LS1012A",
++	  .svr		= 0x87040000,
++	  .mask		= 0xffff0000,
++	},
++	/* Die: LS1046A, SoC: LS1046A/LS1026A */
++	{ .die		= "LS1046A",
++	  .svr		= 0x87070000,
++	  .mask		= 0xffff0000,
++	},
++	/* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */
++	{ .die		= "LS2088A",
++	  .svr		= 0x87090000,
++	  .mask		= 0xff3f0000,
++	},
++	/* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */
++	{ .die		= "LS1021A",
++	  .svr		= 0x87000000,
++	  .mask		= 0xfff70000,
++	},
++	{ },
++};
++
++static const struct fsl_soc_die_attr *fsl_soc_die_match(
++	u32 svr, const struct fsl_soc_die_attr *matches)
++{
++	while (matches->svr) {
++		if (matches->svr == (svr & matches->mask))
++			return matches;
++		matches++;
++	};
++	return NULL;
++}
++
++u32 fsl_guts_get_svr(void)
++{
++	u32 svr = 0;
++
++	if (!guts || !guts->regs)
++		return svr;
++
++	if (guts->little_endian)
++		svr = ioread32(&guts->regs->svr);
++	else
++		svr = ioread32be(&guts->regs->svr);
++
++	return svr;
++}
++EXPORT_SYMBOL(fsl_guts_get_svr);
++
++static int fsl_guts_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct device *dev = &pdev->dev;
++	struct resource *res;
++	const struct fsl_soc_die_attr *soc_die;
++	const char *machine;
++	u32 svr;
++
++	/* Initialize guts */
++	guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
++	if (!guts)
++		return -ENOMEM;
++
++	guts->little_endian = of_property_read_bool(np, "little-endian");
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	guts->regs = devm_ioremap_resource(dev, res);
++	if (IS_ERR(guts->regs))
++		return PTR_ERR(guts->regs);
++
++	/* Register soc device */
++	machine = of_flat_dt_get_machine_name();
++	if (machine)
++		soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
++
++	svr = fsl_guts_get_svr();
++	soc_die = fsl_soc_die_match(svr, fsl_soc_die);
++	if (soc_die) {
++		soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
++						     "QorIQ %s", soc_die->die);
++	} else {
++		soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
++	}
++	soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
++					     "svr:0x%08x", svr);
++	soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
++					       (svr >>  4) & 0xf, svr & 0xf);
++
++	soc_dev = soc_device_register(&soc_dev_attr);
++	if (IS_ERR(soc_dev))
++		return PTR_ERR(soc_dev);
++
++	pr_info("Machine: %s\n", soc_dev_attr.machine);
++	pr_info("SoC family: %s\n", soc_dev_attr.family);
++	pr_info("SoC ID: %s, Revision: %s\n",
++		soc_dev_attr.soc_id, soc_dev_attr.revision);
++	return 0;
++}
++
++static int fsl_guts_remove(struct platform_device *dev)
++{
++	soc_device_unregister(soc_dev);
++	return 0;
++}
++
++/*
++ * Table for matching compatible strings, for device tree
++ * guts node, for Freescale QorIQ SOCs.
++ */
++static const struct of_device_id fsl_guts_of_match[] = {
++	{ .compatible = "fsl,qoriq-device-config-1.0", },
++	{ .compatible = "fsl,qoriq-device-config-2.0", },
++	{ .compatible = "fsl,p1010-guts", },
++	{ .compatible = "fsl,p1020-guts", },
++	{ .compatible = "fsl,p1021-guts", },
++	{ .compatible = "fsl,p1022-guts", },
++	{ .compatible = "fsl,p1023-guts", },
++	{ .compatible = "fsl,p2020-guts", },
++	{ .compatible = "fsl,bsc9131-guts", },
++	{ .compatible = "fsl,bsc9132-guts", },
++	{ .compatible = "fsl,mpc8536-guts", },
++	{ .compatible = "fsl,mpc8544-guts", },
++	{ .compatible = "fsl,mpc8548-guts", },
++	{ .compatible = "fsl,mpc8568-guts", },
++	{ .compatible = "fsl,mpc8569-guts", },
++	{ .compatible = "fsl,mpc8572-guts", },
++	{ .compatible = "fsl,ls1021a-dcfg", },
++	{ .compatible = "fsl,ls1043a-dcfg", },
++	{ .compatible = "fsl,ls1046a-dcfg", },
++	{ .compatible = "fsl,ls2080a-dcfg", },
++	{ .compatible = "fsl,ls1088a-dcfg", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
++
++static struct platform_driver fsl_guts_driver = {
++	.driver = {
++		.name = "fsl-guts",
++		.of_match_table = fsl_guts_of_match,
++	},
++	.probe = fsl_guts_probe,
++	.remove = fsl_guts_remove,
++};
++
++static int __init fsl_guts_init(void)
++{
++	return platform_driver_register(&fsl_guts_driver);
++}
++core_initcall(fsl_guts_init);
++
++static void __exit fsl_guts_exit(void)
++{
++	platform_driver_unregister(&fsl_guts_driver);
++}
++module_exit(fsl_guts_exit);
+--- a/include/linux/fsl/guts.h
++++ b/include/linux/fsl/guts.h
+@@ -30,83 +30,112 @@
+  * #ifdefs.
+  */
+ struct ccsr_guts {
+-	__be32	porpllsr;	/* 0x.0000 - POR PLL Ratio Status Register */
+-	__be32	porbmsr;	/* 0x.0004 - POR Boot Mode Status Register */
+-	__be32	porimpscr;	/* 0x.0008 - POR I/O Impedance Status and Control Register */
+-	__be32	pordevsr;	/* 0x.000c - POR I/O Device Status Register */
+-	__be32	pordbgmsr;	/* 0x.0010 - POR Debug Mode Status Register */
+-	__be32	pordevsr2;	/* 0x.0014 - POR device status register 2 */
++	u32	porpllsr;	/* 0x.0000 - POR PLL Ratio Status Register */
++	u32	porbmsr;	/* 0x.0004 - POR Boot Mode Status Register */
++	u32	porimpscr;	/* 0x.0008 - POR I/O Impedance Status and
++				 *           Control Register
++				 */
++	u32	pordevsr;	/* 0x.000c - POR I/O Device Status Register */
++	u32	pordbgmsr;	/* 0x.0010 - POR Debug Mode Status Register */
++	u32	pordevsr2;	/* 0x.0014 - POR device status register 2 */
+ 	u8	res018[0x20 - 0x18];
+-	__be32	porcir;		/* 0x.0020 - POR Configuration Information Register */
++	u32	porcir;		/* 0x.0020 - POR Configuration Information
++				 *           Register
++				 */
+ 	u8	res024[0x30 - 0x24];
+-	__be32	gpiocr;		/* 0x.0030 - GPIO Control Register */
++	u32	gpiocr;		/* 0x.0030 - GPIO Control Register */
+ 	u8	res034[0x40 - 0x34];
+-	__be32	gpoutdr;	/* 0x.0040 - General-Purpose Output Data Register */
++	u32	gpoutdr;	/* 0x.0040 - General-Purpose Output Data
++				 *           Register
++				 */
+ 	u8	res044[0x50 - 0x44];
+-	__be32	gpindr;		/* 0x.0050 - General-Purpose Input Data Register */
++	u32	gpindr;		/* 0x.0050 - General-Purpose Input Data
++				 *           Register
++				 */
+ 	u8	res054[0x60 - 0x54];
+-	__be32	pmuxcr;		/* 0x.0060 - Alternate Function Signal Multiplex Control */
+-        __be32  pmuxcr2;	/* 0x.0064 - Alternate function signal multiplex control 2 */
+-        __be32  dmuxcr;		/* 0x.0068 - DMA Mux Control Register */
++	u32	pmuxcr;		/* 0x.0060 - Alternate Function Signal
++				 *           Multiplex Control
++				 */
++	u32	pmuxcr2;	/* 0x.0064 - Alternate function signal
++				 *           multiplex control 2
++				 */
++	u32	dmuxcr;		/* 0x.0068 - DMA Mux Control Register */
+         u8	res06c[0x70 - 0x6c];
+-	__be32	devdisr;	/* 0x.0070 - Device Disable Control */
++	u32	devdisr;	/* 0x.0070 - Device Disable Control */
+ #define CCSR_GUTS_DEVDISR_TB1	0x00001000
+ #define CCSR_GUTS_DEVDISR_TB0	0x00004000
+-	__be32	devdisr2;	/* 0x.0074 - Device Disable Control 2 */
++	u32	devdisr2;	/* 0x.0074 - Device Disable Control 2 */
+ 	u8	res078[0x7c - 0x78];
+-	__be32  pmjcr;		/* 0x.007c - 4 Power Management Jog Control Register */
+-	__be32	powmgtcsr;	/* 0x.0080 - Power Management Status and Control Register */
+-	__be32  pmrccr;		/* 0x.0084 - Power Management Reset Counter Configuration Register */
+-	__be32  pmpdccr;	/* 0x.0088 - Power Management Power Down Counter Configuration Register */
+-	__be32  pmcdr;		/* 0x.008c - 4Power management clock disable register */
+-	__be32	mcpsumr;	/* 0x.0090 - Machine Check Summary Register */
+-	__be32	rstrscr;	/* 0x.0094 - Reset Request Status and Control Register */
+-	__be32  ectrstcr;	/* 0x.0098 - Exception reset control register */
+-	__be32  autorstsr;	/* 0x.009c - Automatic reset status register */
+-	__be32	pvr;		/* 0x.00a0 - Processor Version Register */
+-	__be32	svr;		/* 0x.00a4 - System Version Register */
++	u32	pmjcr;		/* 0x.007c - 4 Power Management Jog Control
++				 *           Register
++				 */
++	u32	powmgtcsr;	/* 0x.0080 - Power Management Status and
++				 *           Control Register
++				 */
++	u32	pmrccr;		/* 0x.0084 - Power Management Reset Counter
++				 *           Configuration Register
++				 */
++	u32	pmpdccr;	/* 0x.0088 - Power Management Power Down Counter
++				 *           Configuration Register
++				 */
++	u32	pmcdr;		/* 0x.008c - 4Power management clock disable
++				 *           register
++				 */
++	u32	mcpsumr;	/* 0x.0090 - Machine Check Summary Register */
++	u32	rstrscr;	/* 0x.0094 - Reset Request Status and
++				 *           Control Register
++				 */
++	u32	ectrstcr;	/* 0x.0098 - Exception reset control register */
++	u32	autorstsr;	/* 0x.009c - Automatic reset status register */
++	u32	pvr;		/* 0x.00a0 - Processor Version Register */
++	u32	svr;		/* 0x.00a4 - System Version Register */
+ 	u8	res0a8[0xb0 - 0xa8];
+-	__be32	rstcr;		/* 0x.00b0 - Reset Control Register */
++	u32	rstcr;		/* 0x.00b0 - Reset Control Register */
+ 	u8	res0b4[0xc0 - 0xb4];
+-	__be32  iovselsr;	/* 0x.00c0 - I/O voltage select status register
++	u32	iovselsr;	/* 0x.00c0 - I/O voltage select status register
+ 					     Called 'elbcvselcr' on 86xx SOCs */
+ 	u8	res0c4[0x100 - 0xc4];
+-	__be32	rcwsr[16];	/* 0x.0100 - Reset Control Word Status registers
++	u32	rcwsr[16];	/* 0x.0100 - Reset Control Word Status registers
+ 					     There are 16 registers */
+ 	u8	res140[0x224 - 0x140];
+-	__be32  iodelay1;	/* 0x.0224 - IO delay control register 1 */
+-	__be32  iodelay2;	/* 0x.0228 - IO delay control register 2 */
++	u32	iodelay1;	/* 0x.0224 - IO delay control register 1 */
++	u32	iodelay2;	/* 0x.0228 - IO delay control register 2 */
+ 	u8	res22c[0x604 - 0x22c];
+-	__be32	pamubypenr; 	/* 0x.604 - PAMU bypass enable register */
++	u32	pamubypenr;	/* 0x.604 - PAMU bypass enable register */
+ 	u8	res608[0x800 - 0x608];
+-	__be32	clkdvdr;	/* 0x.0800 - Clock Divide Register */
++	u32	clkdvdr;	/* 0x.0800 - Clock Divide Register */
+ 	u8	res804[0x900 - 0x804];
+-	__be32	ircr;		/* 0x.0900 - Infrared Control Register */
++	u32	ircr;		/* 0x.0900 - Infrared Control Register */
+ 	u8	res904[0x908 - 0x904];
+-	__be32	dmacr;		/* 0x.0908 - DMA Control Register */
++	u32	dmacr;		/* 0x.0908 - DMA Control Register */
+ 	u8	res90c[0x914 - 0x90c];
+-	__be32	elbccr;		/* 0x.0914 - eLBC Control Register */
++	u32	elbccr;		/* 0x.0914 - eLBC Control Register */
+ 	u8	res918[0xb20 - 0x918];
+-	__be32	ddr1clkdr;	/* 0x.0b20 - DDR1 Clock Disable Register */
+-	__be32	ddr2clkdr;	/* 0x.0b24 - DDR2 Clock Disable Register */
+-	__be32	ddrclkdr;	/* 0x.0b28 - DDR Clock Disable Register */
++	u32	ddr1clkdr;	/* 0x.0b20 - DDR1 Clock Disable Register */
++	u32	ddr2clkdr;	/* 0x.0b24 - DDR2 Clock Disable Register */
++	u32	ddrclkdr;	/* 0x.0b28 - DDR Clock Disable Register */
+ 	u8	resb2c[0xe00 - 0xb2c];
+-	__be32	clkocr;		/* 0x.0e00 - Clock Out Select Register */
++	u32	clkocr;		/* 0x.0e00 - Clock Out Select Register */
+ 	u8	rese04[0xe10 - 0xe04];
+-	__be32	ddrdllcr;	/* 0x.0e10 - DDR DLL Control Register */
++	u32	ddrdllcr;	/* 0x.0e10 - DDR DLL Control Register */
+ 	u8	rese14[0xe20 - 0xe14];
+-	__be32	lbcdllcr;	/* 0x.0e20 - LBC DLL Control Register */
+-	__be32  cpfor;		/* 0x.0e24 - L2 charge pump fuse override register */
++	u32	lbcdllcr;	/* 0x.0e20 - LBC DLL Control Register */
++	u32	cpfor;		/* 0x.0e24 - L2 charge pump fuse override
++				 *           register
++				 */
+ 	u8	rese28[0xf04 - 0xe28];
+-	__be32	srds1cr0;	/* 0x.0f04 - SerDes1 Control Register 0 */
+-	__be32	srds1cr1;	/* 0x.0f08 - SerDes1 Control Register 0 */
++	u32	srds1cr0;	/* 0x.0f04 - SerDes1 Control Register 0 */
++	u32	srds1cr1;	/* 0x.0f08 - SerDes1 Control Register 0 */
+ 	u8	resf0c[0xf2c - 0xf0c];
+-	__be32  itcr;		/* 0x.0f2c - Internal transaction control register */
++	u32	itcr;		/* 0x.0f2c - Internal transaction control
++				 *           register
++				 */
+ 	u8	resf30[0xf40 - 0xf30];
+-	__be32	srds2cr0;	/* 0x.0f40 - SerDes2 Control Register 0 */
+-	__be32	srds2cr1;	/* 0x.0f44 - SerDes2 Control Register 0 */
++	u32	srds2cr0;	/* 0x.0f40 - SerDes2 Control Register 0 */
++	u32	srds2cr1;	/* 0x.0f44 - SerDes2 Control Register 0 */
+ } __attribute__ ((packed));
+ 
++u32 fsl_guts_get_svr(void);
+ 
+ /* Alternate function signal multiplex control */
+ #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
diff --git a/target/linux/layerscape/patches-4.14/804-i2c-support-layerscape.patch b/target/linux/layerscape/patches-4.9/809-i2c-support-layerscape.patch
similarity index 88%
rename from target/linux/layerscape/patches-4.14/804-i2c-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/809-i2c-support-layerscape.patch
index 820f384af..ffb95cc34 100644
--- a/target/linux/layerscape/patches-4.14/804-i2c-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/809-i2c-support-layerscape.patch
@@ -1,15 +1,17 @@
-From 4f22b58a2f809aff55aa9321c9100b0caf3b6694 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:36 +0800
-Subject: [PATCH 21/40] i2c: support layerscape
-This is an integrated patch of i2c for layerscape
+From 659aa30c59fb188b533a7edcb9bd38ac007a2739 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:35:11 +0800
+Subject: [PATCH 21/30] i2c: support layerscape
+
+This is an integrated patch for layerscape i2c support.
 
 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/i2c/busses/i2c-imx.c        | 193 ++++++++++++++++++++++++++++
- drivers/i2c/muxes/i2c-mux-pca954x.c |  44 ++++++-
- 2 files changed, 236 insertions(+), 1 deletion(-)
+ drivers/i2c/busses/i2c-imx.c        | 195 +++++++++++++++++++++++++++++++++++-
+ drivers/i2c/muxes/i2c-mux-pca954x.c |  43 ++++++++
+ 2 files changed, 237 insertions(+), 1 deletion(-)
 
 --- a/drivers/i2c/busses/i2c-imx.c
 +++ b/drivers/i2c/busses/i2c-imx.c
@@ -255,17 +257,26 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	/* Get I2C clock */
  	i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
  	if (IS_ERR(i2c_imx->clk)) {
+@@ -1099,7 +1292,7 @@ static int i2c_imx_probe(struct platform
+ 	}
+ 
+ 	/* Request IRQ */
+-	ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
++	ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED,
+ 				pdev->name, i2c_imx);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "can't claim irq %d\n", irq);
 --- a/drivers/i2c/muxes/i2c-mux-pca954x.c
 +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
-@@ -85,6 +85,7 @@ struct pca954x {
- 	struct irq_domain *irq;
- 	unsigned int irq_mask;
- 	raw_spinlock_t lock;
+@@ -74,6 +74,7 @@ struct pca954x {
+ 	u8 last_chan;		/* last register value */
+ 	u8 deselect;
+ 	struct i2c_client *client;
 +	u8 disable_mux;		/* do not disable mux if val not 0 */
  };
  
  /* Provide specs for the PCA954x types we know about */
-@@ -221,6 +222,13 @@ static int pca954x_deselect_mux(struct i
+@@ -196,6 +197,13 @@ static int pca954x_deselect_mux(struct i
  	if (!(data->deselect & (1 << chan)))
  		return 0;
  
@@ -279,7 +290,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	/* Deselect active channel */
  	data->last_chan = 0;
  	return pca954x_reg_write(muxc->parent, client, data->last_chan);
-@@ -361,6 +369,28 @@ static int pca954x_probe(struct i2c_clie
+@@ -228,6 +236,28 @@ static int pca954x_probe(struct i2c_clie
  		return -ENOMEM;
  	data = i2c_mux_priv(muxc);
  
@@ -308,7 +319,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	i2c_set_clientdata(client, muxc);
  	data->client = client;
  
-@@ -373,18 +403,23 @@ static int pca954x_probe(struct i2c_clie
+@@ -240,11 +270,16 @@ static int pca954x_probe(struct i2c_clie
  	 * that the mux is in fact present. This also
  	 * initializes the mux to disconnected state.
  	 */
@@ -325,15 +336,15 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev);
  	if (match)
  		data->chip = of_device_get_match_data(&client->dev);
- 	else
+@@ -252,6 +287,7 @@ static int pca954x_probe(struct i2c_clie
  		data->chip = &chips[id->driver_data];
--
+ 
  	data->last_chan = 0;		   /* force the first selection */
 +#endif
  
  	idle_disconnect_dt = of_node &&
  		of_property_read_bool(of_node, "i2c-mux-idle-disconnect");
-@@ -454,6 +489,13 @@ static int pca954x_resume(struct device
+@@ -312,6 +348,13 @@ static int pca954x_resume(struct device
  	struct i2c_mux_core *muxc = i2c_get_clientdata(client);
  	struct pca954x *data = i2c_mux_priv(muxc);
  
diff --git a/target/linux/layerscape/patches-4.9/810-iommu-support-layerscape.patch b/target/linux/layerscape/patches-4.9/810-iommu-support-layerscape.patch
new file mode 100644
index 000000000..5dbeb0c45
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/810-iommu-support-layerscape.patch
@@ -0,0 +1,1671 @@
+From 89a1f0d7826df69d8e02268b97bc3da02e07203f Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:35:15 +0800
+Subject: [PATCH 22/32] iommu: support layerscape
+
+This is an integrated patch for layerscape smmu support.
+
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
+Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/iommu/amd_iommu.c    |  56 +++++---
+ drivers/iommu/arm-smmu-v3.c  | 111 +++++++++++-----
+ drivers/iommu/arm-smmu.c     | 100 ++++++++++++---
+ drivers/iommu/dma-iommu.c    | 242 +++++++++++++++++++++++++++++------
+ drivers/iommu/intel-iommu.c  |  92 ++++++++++---
+ drivers/iommu/iommu.c        | 240 ++++++++++++++++++++++++++++++++--
+ drivers/iommu/mtk_iommu.c    |   2 +
+ drivers/iommu/mtk_iommu_v1.c |   2 +
+ include/linux/dma-iommu.h    |  11 ++
+ include/linux/iommu.h        |  57 +++++++--
+ 10 files changed, 762 insertions(+), 151 deletions(-)
+
+--- a/drivers/iommu/amd_iommu.c
++++ b/drivers/iommu/amd_iommu.c
+@@ -379,6 +379,8 @@ static struct iommu_group *acpihid_devic
+ 
+ 	if (!entry->group)
+ 		entry->group = generic_device_group(dev);
++	else
++		iommu_group_ref_get(entry->group);
+ 
+ 	return entry->group;
+ }
+@@ -3166,9 +3168,10 @@ static bool amd_iommu_capable(enum iommu
+ 	return false;
+ }
+ 
+-static void amd_iommu_get_dm_regions(struct device *dev,
+-				     struct list_head *head)
++static void amd_iommu_get_resv_regions(struct device *dev,
++				       struct list_head *head)
+ {
++	struct iommu_resv_region *region;
+ 	struct unity_map_entry *entry;
+ 	int devid;
+ 
+@@ -3177,41 +3180,56 @@ static void amd_iommu_get_dm_regions(str
+ 		return;
+ 
+ 	list_for_each_entry(entry, &amd_iommu_unity_map, list) {
+-		struct iommu_dm_region *region;
++		size_t length;
++		int prot = 0;
+ 
+ 		if (devid < entry->devid_start || devid > entry->devid_end)
+ 			continue;
+ 
+-		region = kzalloc(sizeof(*region), GFP_KERNEL);
++		length = entry->address_end - entry->address_start;
++		if (entry->prot & IOMMU_PROT_IR)
++			prot |= IOMMU_READ;
++		if (entry->prot & IOMMU_PROT_IW)
++			prot |= IOMMU_WRITE;
++
++		region = iommu_alloc_resv_region(entry->address_start,
++						 length, prot,
++						 IOMMU_RESV_DIRECT);
+ 		if (!region) {
+ 			pr_err("Out of memory allocating dm-regions for %s\n",
+ 				dev_name(dev));
+ 			return;
+ 		}
+-
+-		region->start = entry->address_start;
+-		region->length = entry->address_end - entry->address_start;
+-		if (entry->prot & IOMMU_PROT_IR)
+-			region->prot |= IOMMU_READ;
+-		if (entry->prot & IOMMU_PROT_IW)
+-			region->prot |= IOMMU_WRITE;
+-
+ 		list_add_tail(&region->list, head);
+ 	}
++
++	region = iommu_alloc_resv_region(MSI_RANGE_START,
++					 MSI_RANGE_END - MSI_RANGE_START + 1,
++					 0, IOMMU_RESV_MSI);
++	if (!region)
++		return;
++	list_add_tail(&region->list, head);
++
++	region = iommu_alloc_resv_region(HT_RANGE_START,
++					 HT_RANGE_END - HT_RANGE_START + 1,
++					 0, IOMMU_RESV_RESERVED);
++	if (!region)
++		return;
++	list_add_tail(&region->list, head);
+ }
+ 
+-static void amd_iommu_put_dm_regions(struct device *dev,
++static void amd_iommu_put_resv_regions(struct device *dev,
+ 				     struct list_head *head)
+ {
+-	struct iommu_dm_region *entry, *next;
++	struct iommu_resv_region *entry, *next;
+ 
+ 	list_for_each_entry_safe(entry, next, head, list)
+ 		kfree(entry);
+ }
+ 
+-static void amd_iommu_apply_dm_region(struct device *dev,
++static void amd_iommu_apply_resv_region(struct device *dev,
+ 				      struct iommu_domain *domain,
+-				      struct iommu_dm_region *region)
++				      struct iommu_resv_region *region)
+ {
+ 	struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
+ 	unsigned long start, end;
+@@ -3235,9 +3253,9 @@ static const struct iommu_ops amd_iommu_
+ 	.add_device = amd_iommu_add_device,
+ 	.remove_device = amd_iommu_remove_device,
+ 	.device_group = amd_iommu_device_group,
+-	.get_dm_regions = amd_iommu_get_dm_regions,
+-	.put_dm_regions = amd_iommu_put_dm_regions,
+-	.apply_dm_region = amd_iommu_apply_dm_region,
++	.get_resv_regions = amd_iommu_get_resv_regions,
++	.put_resv_regions = amd_iommu_put_resv_regions,
++	.apply_resv_region = amd_iommu_apply_resv_region,
+ 	.pgsize_bitmap	= AMD_IOMMU_PGSIZES,
+ };
+ 
+--- a/drivers/iommu/arm-smmu-v3.c
++++ b/drivers/iommu/arm-smmu-v3.c
+@@ -410,6 +410,9 @@
+ /* High-level queue structures */
+ #define ARM_SMMU_POLL_TIMEOUT_US	100
+ 
++#define MSI_IOVA_BASE			0x8000000
++#define MSI_IOVA_LENGTH			0x100000
++
+ static bool disable_bypass;
+ module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO);
+ MODULE_PARM_DESC(disable_bypass,
+@@ -552,9 +555,14 @@ struct arm_smmu_s2_cfg {
+ };
+ 
+ struct arm_smmu_strtab_ent {
+-	bool				valid;
+-
+-	bool				bypass;	/* Overrides s1/s2 config */
++	/*
++	 * An STE is "assigned" if the master emitting the corresponding SID
++	 * is attached to a domain. The behaviour of an unassigned STE is
++	 * determined by the disable_bypass parameter, whereas an assigned
++	 * STE behaves according to s1_cfg/s2_cfg, which themselves are
++	 * configured according to the domain type.
++	 */
++	bool				assigned;
+ 	struct arm_smmu_s1_cfg		*s1_cfg;
+ 	struct arm_smmu_s2_cfg		*s2_cfg;
+ };
+@@ -627,6 +635,7 @@ enum arm_smmu_domain_stage {
+ 	ARM_SMMU_DOMAIN_S1 = 0,
+ 	ARM_SMMU_DOMAIN_S2,
+ 	ARM_SMMU_DOMAIN_NESTED,
++	ARM_SMMU_DOMAIN_BYPASS,
+ };
+ 
+ struct arm_smmu_domain {
+@@ -1000,9 +1009,9 @@ static void arm_smmu_write_strtab_ent(st
+ 	 * This is hideously complicated, but we only really care about
+ 	 * three cases at the moment:
+ 	 *
+-	 * 1. Invalid (all zero) -> bypass  (init)
+-	 * 2. Bypass -> translation (attach)
+-	 * 3. Translation -> bypass (detach)
++	 * 1. Invalid (all zero) -> bypass/fault (init)
++	 * 2. Bypass/fault -> translation/bypass (attach)
++	 * 3. Translation/bypass -> bypass/fault (detach)
+ 	 *
+ 	 * Given that we can't update the STE atomically and the SMMU
+ 	 * doesn't read the thing in a defined order, that leaves us
+@@ -1041,11 +1050,15 @@ static void arm_smmu_write_strtab_ent(st
+ 	}
+ 
+ 	/* Nuke the existing STE_0 value, as we're going to rewrite it */
+-	val = ste->valid ? STRTAB_STE_0_V : 0;
++	val = STRTAB_STE_0_V;
++
++	/* Bypass/fault */
++	if (!ste->assigned || !(ste->s1_cfg || ste->s2_cfg)) {
++		if (!ste->assigned && disable_bypass)
++			val |= STRTAB_STE_0_CFG_ABORT;
++		else
++			val |= STRTAB_STE_0_CFG_BYPASS;
+ 
+-	if (ste->bypass) {
+-		val |= disable_bypass ? STRTAB_STE_0_CFG_ABORT
+-				      : STRTAB_STE_0_CFG_BYPASS;
+ 		dst[0] = cpu_to_le64(val);
+ 		dst[1] = cpu_to_le64(STRTAB_STE_1_SHCFG_INCOMING
+ 			 << STRTAB_STE_1_SHCFG_SHIFT);
+@@ -1108,10 +1121,7 @@ static void arm_smmu_write_strtab_ent(st
+ static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent)
+ {
+ 	unsigned int i;
+-	struct arm_smmu_strtab_ent ste = {
+-		.valid	= true,
+-		.bypass	= true,
+-	};
++	struct arm_smmu_strtab_ent ste = { .assigned = false };
+ 
+ 	for (i = 0; i < nent; ++i) {
+ 		arm_smmu_write_strtab_ent(NULL, -1, strtab, &ste);
+@@ -1365,8 +1375,6 @@ static bool arm_smmu_capable(enum iommu_
+ 	switch (cap) {
+ 	case IOMMU_CAP_CACHE_COHERENCY:
+ 		return true;
+-	case IOMMU_CAP_INTR_REMAP:
+-		return true; /* MSIs are just memory writes */
+ 	case IOMMU_CAP_NOEXEC:
+ 		return true;
+ 	default:
+@@ -1378,7 +1386,9 @@ static struct iommu_domain *arm_smmu_dom
+ {
+ 	struct arm_smmu_domain *smmu_domain;
+ 
+-	if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
++	if (type != IOMMU_DOMAIN_UNMANAGED &&
++	    type != IOMMU_DOMAIN_DMA &&
++	    type != IOMMU_DOMAIN_IDENTITY)
+ 		return NULL;
+ 
+ 	/*
+@@ -1509,6 +1519,11 @@ static int arm_smmu_domain_finalise(stru
+ 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+ 	struct arm_smmu_device *smmu = smmu_domain->smmu;
+ 
++	if (domain->type == IOMMU_DOMAIN_IDENTITY) {
++		smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS;
++		return 0;
++	}
++
+ 	/* Restrict the stage to what we can actually support */
+ 	if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
+ 		smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
+@@ -1581,7 +1596,7 @@ static __le64 *arm_smmu_get_step_for_sid
+ 	return step;
+ }
+ 
+-static int arm_smmu_install_ste_for_dev(struct iommu_fwspec *fwspec)
++static void arm_smmu_install_ste_for_dev(struct iommu_fwspec *fwspec)
+ {
+ 	int i, j;
+ 	struct arm_smmu_master_data *master = fwspec->iommu_priv;
+@@ -1600,17 +1615,14 @@ static int arm_smmu_install_ste_for_dev(
+ 
+ 		arm_smmu_write_strtab_ent(smmu, sid, step, &master->ste);
+ 	}
+-
+-	return 0;
+ }
+ 
+ static void arm_smmu_detach_dev(struct device *dev)
+ {
+ 	struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv;
+ 
+-	master->ste.bypass = true;
+-	if (arm_smmu_install_ste_for_dev(dev->iommu_fwspec) < 0)
+-		dev_warn(dev, "failed to install bypass STE\n");
++	master->ste.assigned = false;
++	arm_smmu_install_ste_for_dev(dev->iommu_fwspec);
+ }
+ 
+ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
+@@ -1629,7 +1641,7 @@ static int arm_smmu_attach_dev(struct io
+ 	ste = &master->ste;
+ 
+ 	/* Already attached to a different domain? */
+-	if (!ste->bypass)
++	if (ste->assigned)
+ 		arm_smmu_detach_dev(dev);
+ 
+ 	mutex_lock(&smmu_domain->init_mutex);
+@@ -1650,10 +1662,12 @@ static int arm_smmu_attach_dev(struct io
+ 		goto out_unlock;
+ 	}
+ 
+-	ste->bypass = false;
+-	ste->valid = true;
++	ste->assigned = true;
+ 
+-	if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
++	if (smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS) {
++		ste->s1_cfg = NULL;
++		ste->s2_cfg = NULL;
++	} else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
+ 		ste->s1_cfg = &smmu_domain->s1_cfg;
+ 		ste->s2_cfg = NULL;
+ 		arm_smmu_write_ctx_desc(smmu, ste->s1_cfg);
+@@ -1662,10 +1676,7 @@ static int arm_smmu_attach_dev(struct io
+ 		ste->s2_cfg = &smmu_domain->s2_cfg;
+ 	}
+ 
+-	ret = arm_smmu_install_ste_for_dev(dev->iommu_fwspec);
+-	if (ret < 0)
+-		ste->valid = false;
+-
++	arm_smmu_install_ste_for_dev(dev->iommu_fwspec);
+ out_unlock:
+ 	mutex_unlock(&smmu_domain->init_mutex);
+ 	return ret;
+@@ -1696,6 +1707,9 @@ arm_smmu_unmap(struct iommu_domain *doma
+ 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+ 	struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
+ 
++	if (domain->type == IOMMU_DOMAIN_IDENTITY)
++		return iova;
++
+ 	if (!ops)
+ 		return 0;
+ 
+@@ -1811,7 +1825,7 @@ static void arm_smmu_remove_device(struc
+ 		return;
+ 
+ 	master = fwspec->iommu_priv;
+-	if (master && master->ste.valid)
++	if (master && master->ste.assigned)
+ 		arm_smmu_detach_dev(dev);
+ 	iommu_group_remove_device(dev);
+ 	kfree(master);
+@@ -1840,6 +1854,9 @@ static int arm_smmu_domain_get_attr(stru
+ {
+ 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+ 
++	if (domain->type != IOMMU_DOMAIN_UNMANAGED)
++		return -EINVAL;
++
+ 	switch (attr) {
+ 	case DOMAIN_ATTR_NESTING:
+ 		*(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
+@@ -1855,6 +1872,9 @@ static int arm_smmu_domain_set_attr(stru
+ 	int ret = 0;
+ 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+ 
++	if (domain->type != IOMMU_DOMAIN_UNMANAGED)
++		return -EINVAL;
++
+ 	mutex_lock(&smmu_domain->init_mutex);
+ 
+ 	switch (attr) {
+@@ -1884,6 +1904,31 @@ static int arm_smmu_of_xlate(struct devi
+ 	return iommu_fwspec_add_ids(dev, args->args, 1);
+ }
+ 
++static void arm_smmu_get_resv_regions(struct device *dev,
++				      struct list_head *head)
++{
++	struct iommu_resv_region *region;
++	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
++
++	region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH,
++					 prot, IOMMU_RESV_SW_MSI);
++	if (!region)
++		return;
++
++	list_add_tail(&region->list, head);
++
++	iommu_dma_get_resv_regions(dev, head);
++}
++
++static void arm_smmu_put_resv_regions(struct device *dev,
++				      struct list_head *head)
++{
++	struct iommu_resv_region *entry, *next;
++
++	list_for_each_entry_safe(entry, next, head, list)
++		kfree(entry);
++}
++
+ static struct iommu_ops arm_smmu_ops = {
+ 	.capable		= arm_smmu_capable,
+ 	.domain_alloc		= arm_smmu_domain_alloc,
+@@ -1899,6 +1944,8 @@ static struct iommu_ops arm_smmu_ops = {
+ 	.domain_get_attr	= arm_smmu_domain_get_attr,
+ 	.domain_set_attr	= arm_smmu_domain_set_attr,
+ 	.of_xlate		= arm_smmu_of_xlate,
++	.get_resv_regions	= arm_smmu_get_resv_regions,
++	.put_resv_regions	= arm_smmu_put_resv_regions,
+ 	.pgsize_bitmap		= -1UL, /* Restricted during device attach */
+ };
+ 
+--- a/drivers/iommu/arm-smmu.c
++++ b/drivers/iommu/arm-smmu.c
+@@ -49,6 +49,7 @@
+ #include <linux/spinlock.h>
+ 
+ #include <linux/amba/bus.h>
++#include <linux/fsl/mc.h>
+ 
+ #include "io-pgtable.h"
+ 
+@@ -247,6 +248,7 @@ enum arm_smmu_s2cr_privcfg {
+ #define ARM_MMU500_ACTLR_CPRE		(1 << 1)
+ 
+ #define ARM_MMU500_ACR_CACHE_LOCK	(1 << 26)
++#define ARM_MMU500_ACR_SMTNMB_TLBEN	(1 << 8)
+ 
+ #define CB_PAR_F			(1 << 0)
+ 
+@@ -278,6 +280,9 @@ enum arm_smmu_s2cr_privcfg {
+ 
+ #define FSYNR0_WNR			(1 << 4)
+ 
++#define MSI_IOVA_BASE			0x8000000
++#define MSI_IOVA_LENGTH			0x100000
++
+ static int force_stage;
+ module_param(force_stage, int, S_IRUGO);
+ MODULE_PARM_DESC(force_stage,
+@@ -401,6 +406,7 @@ enum arm_smmu_domain_stage {
+ 	ARM_SMMU_DOMAIN_S1 = 0,
+ 	ARM_SMMU_DOMAIN_S2,
+ 	ARM_SMMU_DOMAIN_NESTED,
++	ARM_SMMU_DOMAIN_BYPASS,
+ };
+ 
+ struct arm_smmu_domain {
+@@ -821,6 +827,12 @@ static int arm_smmu_init_domain_context(
+ 	if (smmu_domain->smmu)
+ 		goto out_unlock;
+ 
++	if (domain->type == IOMMU_DOMAIN_IDENTITY) {
++		smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS;
++		smmu_domain->smmu = smmu;
++		goto out_unlock;
++	}
++
+ 	/*
+ 	 * Mapping the requested stage onto what we support is surprisingly
+ 	 * complicated, mainly because the spec allows S1+S2 SMMUs without
+@@ -981,7 +993,7 @@ static void arm_smmu_destroy_domain_cont
+ 	void __iomem *cb_base;
+ 	int irq;
+ 
+-	if (!smmu)
++	if (!smmu || domain->type == IOMMU_DOMAIN_IDENTITY)
+ 		return;
+ 
+ 	/*
+@@ -1004,7 +1016,9 @@ static struct iommu_domain *arm_smmu_dom
+ {
+ 	struct arm_smmu_domain *smmu_domain;
+ 
+-	if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
++	if (type != IOMMU_DOMAIN_UNMANAGED &&
++	    type != IOMMU_DOMAIN_DMA &&
++	    type != IOMMU_DOMAIN_IDENTITY)
+ 		return NULL;
+ 	/*
+ 	 * Allocate the domain and initialise some of its data structures.
+@@ -1202,10 +1216,15 @@ static int arm_smmu_domain_add_master(st
+ {
+ 	struct arm_smmu_device *smmu = smmu_domain->smmu;
+ 	struct arm_smmu_s2cr *s2cr = smmu->s2crs;
+-	enum arm_smmu_s2cr_type type = S2CR_TYPE_TRANS;
+ 	u8 cbndx = smmu_domain->cfg.cbndx;
++	enum arm_smmu_s2cr_type type;
+ 	int i, idx;
+ 
++	if (smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS)
++		type = S2CR_TYPE_BYPASS;
++	else
++		type = S2CR_TYPE_TRANS;
++
+ 	for_each_cfg_sme(fwspec, i, idx) {
+ 		if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)
+ 			continue;
+@@ -1343,6 +1362,9 @@ static phys_addr_t arm_smmu_iova_to_phys
+ 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+ 	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
+ 
++	if (domain->type == IOMMU_DOMAIN_IDENTITY)
++		return iova;
++
+ 	if (!ops)
+ 		return 0;
+ 
+@@ -1368,8 +1390,6 @@ static bool arm_smmu_capable(enum iommu_
+ 		 * requests.
+ 		 */
+ 		return true;
+-	case IOMMU_CAP_INTR_REMAP:
+-		return true; /* MSIs are just memory writes */
+ 	case IOMMU_CAP_NOEXEC:
+ 		return true;
+ 	default:
+@@ -1478,10 +1498,12 @@ static struct iommu_group *arm_smmu_devi
+ 	}
+ 
+ 	if (group)
+-		return group;
++		return iommu_group_ref_get(group);
+ 
+ 	if (dev_is_pci(dev))
+ 		group = pci_device_group(dev);
++	else if (dev_is_fsl_mc(dev))
++		group = fsl_mc_device_group(dev);
+ 	else
+ 		group = generic_device_group(dev);
+ 
+@@ -1493,6 +1515,9 @@ static int arm_smmu_domain_get_attr(stru
+ {
+ 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+ 
++	if (domain->type != IOMMU_DOMAIN_UNMANAGED)
++		return -EINVAL;
++
+ 	switch (attr) {
+ 	case DOMAIN_ATTR_NESTING:
+ 		*(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
+@@ -1508,6 +1533,9 @@ static int arm_smmu_domain_set_attr(stru
+ 	int ret = 0;
+ 	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+ 
++	if (domain->type != IOMMU_DOMAIN_UNMANAGED)
++		return -EINVAL;
++
+ 	mutex_lock(&smmu_domain->init_mutex);
+ 
+ 	switch (attr) {
+@@ -1534,17 +1562,44 @@ out_unlock:
+ 
+ static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
+ {
+-	u32 fwid = 0;
++	u32 mask, fwid = 0;
+ 
+ 	if (args->args_count > 0)
+ 		fwid |= (u16)args->args[0];
+ 
+ 	if (args->args_count > 1)
+ 		fwid |= (u16)args->args[1] << SMR_MASK_SHIFT;
++	else if (!of_property_read_u32(args->np, "stream-match-mask", &mask))
++		fwid |= (u16)mask << SMR_MASK_SHIFT;
+ 
+ 	return iommu_fwspec_add_ids(dev, &fwid, 1);
+ }
+ 
++static void arm_smmu_get_resv_regions(struct device *dev,
++				      struct list_head *head)
++{
++	struct iommu_resv_region *region;
++	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
++
++	region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH,
++					 prot, IOMMU_RESV_SW_MSI);
++	if (!region)
++		return;
++
++	list_add_tail(&region->list, head);
++
++	iommu_dma_get_resv_regions(dev, head);
++}
++
++static void arm_smmu_put_resv_regions(struct device *dev,
++				      struct list_head *head)
++{
++	struct iommu_resv_region *entry, *next;
++
++	list_for_each_entry_safe(entry, next, head, list)
++		kfree(entry);
++}
++
+ static struct iommu_ops arm_smmu_ops = {
+ 	.capable		= arm_smmu_capable,
+ 	.domain_alloc		= arm_smmu_domain_alloc,
+@@ -1560,6 +1615,8 @@ static struct iommu_ops arm_smmu_ops = {
+ 	.domain_get_attr	= arm_smmu_domain_get_attr,
+ 	.domain_set_attr	= arm_smmu_domain_set_attr,
+ 	.of_xlate		= arm_smmu_of_xlate,
++	.get_resv_regions	= arm_smmu_get_resv_regions,
++	.put_resv_regions	= arm_smmu_put_resv_regions,
+ 	.pgsize_bitmap		= -1UL, /* Restricted during device attach */
+ };
+ 
+@@ -1581,16 +1638,22 @@ static void arm_smmu_device_reset(struct
+ 	for (i = 0; i < smmu->num_mapping_groups; ++i)
+ 		arm_smmu_write_sme(smmu, i);
+ 
+-	/*
+-	 * Before clearing ARM_MMU500_ACTLR_CPRE, need to
+-	 * clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
+-	 * bit is only present in MMU-500r2 onwards.
+-	 */
+-	reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
+-	major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
+-	if ((smmu->model == ARM_MMU500) && (major >= 2)) {
++	if (smmu->model == ARM_MMU500) {
++		/*
++		 * Before clearing ARM_MMU500_ACTLR_CPRE, need to
++		 * clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
++		 * bit is only present in MMU-500r2 onwards.
++		 */
++		reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
++		major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
+ 		reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
+-		reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
++		if (major >= 2)
++			reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
++		/*
++		 * Allow unmatched Stream IDs to allocate bypass
++		 * TLB entries for reduced latency.
++		 */
++		reg |= ARM_MMU500_ACR_SMTNMB_TLBEN;
+ 		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
+ 	}
+ 
+@@ -2024,6 +2087,11 @@ static int arm_smmu_device_dt_probe(stru
+ 		bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
+ 	}
+ #endif
++#ifdef CONFIG_FSL_MC_BUS
++	if (!iommu_present(&fsl_mc_bus_type))
++		bus_set_iommu(&fsl_mc_bus_type, &arm_smmu_ops);
++#endif
++
+ 	return 0;
+ }
+ 
+--- a/drivers/iommu/dma-iommu.c
++++ b/drivers/iommu/dma-iommu.c
+@@ -37,15 +37,50 @@ struct iommu_dma_msi_page {
+ 	phys_addr_t		phys;
+ };
+ 
++enum iommu_dma_cookie_type {
++	IOMMU_DMA_IOVA_COOKIE,
++	IOMMU_DMA_MSI_COOKIE,
++};
++
+ struct iommu_dma_cookie {
+-	struct iova_domain	iovad;
+-	struct list_head	msi_page_list;
+-	spinlock_t		msi_lock;
++	enum iommu_dma_cookie_type	type;
++	union {
++		/* Full allocator for IOMMU_DMA_IOVA_COOKIE */
++		struct iova_domain	iovad;
++		/* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
++		dma_addr_t		msi_iova;
++	};
++	struct list_head		msi_page_list;
++	spinlock_t			msi_lock;
+ };
+ 
++static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
++{
++	if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
++		return cookie->iovad.granule;
++	return PAGE_SIZE;
++}
++
+ static inline struct iova_domain *cookie_iovad(struct iommu_domain *domain)
+ {
+-	return &((struct iommu_dma_cookie *)domain->iova_cookie)->iovad;
++	struct iommu_dma_cookie *cookie = domain->iova_cookie;
++
++	if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
++		return &cookie->iovad;
++	return NULL;
++}
++
++static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
++{
++	struct iommu_dma_cookie *cookie;
++
++	cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
++	if (cookie) {
++		spin_lock_init(&cookie->msi_lock);
++		INIT_LIST_HEAD(&cookie->msi_page_list);
++		cookie->type = type;
++	}
++	return cookie;
+ }
+ 
+ int iommu_dma_init(void)
+@@ -62,25 +97,53 @@ int iommu_dma_init(void)
+  */
+ int iommu_get_dma_cookie(struct iommu_domain *domain)
+ {
++	if (domain->iova_cookie)
++		return -EEXIST;
++
++	domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
++	if (!domain->iova_cookie)
++		return -ENOMEM;
++
++	return 0;
++}
++EXPORT_SYMBOL(iommu_get_dma_cookie);
++
++/**
++ * iommu_get_msi_cookie - Acquire just MSI remapping resources
++ * @domain: IOMMU domain to prepare
++ * @base: Start address of IOVA region for MSI mappings
++ *
++ * Users who manage their own IOVA allocation and do not want DMA API support,
++ * but would still like to take advantage of automatic MSI remapping, can use
++ * this to initialise their own domain appropriately. Users should reserve a
++ * contiguous IOVA region, starting at @base, large enough to accommodate the
++ * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
++ * used by the devices attached to @domain.
++ */
++int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
++{
+ 	struct iommu_dma_cookie *cookie;
+ 
++	if (domain->type != IOMMU_DOMAIN_UNMANAGED)
++		return -EINVAL;
++
+ 	if (domain->iova_cookie)
+ 		return -EEXIST;
+ 
+-	cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
++	cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
+ 	if (!cookie)
+ 		return -ENOMEM;
+ 
+-	spin_lock_init(&cookie->msi_lock);
+-	INIT_LIST_HEAD(&cookie->msi_page_list);
++	cookie->msi_iova = base;
+ 	domain->iova_cookie = cookie;
+ 	return 0;
+ }
+-EXPORT_SYMBOL(iommu_get_dma_cookie);
++EXPORT_SYMBOL(iommu_get_msi_cookie);
+ 
+ /**
+  * iommu_put_dma_cookie - Release a domain's DMA mapping resources
+- * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
++ * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
++ *          iommu_get_msi_cookie()
+  *
+  * IOMMU drivers should normally call this from their domain_free callback.
+  */
+@@ -92,7 +155,7 @@ void iommu_put_dma_cookie(struct iommu_d
+ 	if (!cookie)
+ 		return;
+ 
+-	if (cookie->iovad.granule)
++	if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule)
+ 		put_iova_domain(&cookie->iovad);
+ 
+ 	list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
+@@ -104,21 +167,99 @@ void iommu_put_dma_cookie(struct iommu_d
+ }
+ EXPORT_SYMBOL(iommu_put_dma_cookie);
+ 
+-static void iova_reserve_pci_windows(struct pci_dev *dev,
+-		struct iova_domain *iovad)
++/**
++ * iommu_dma_get_resv_regions - Reserved region driver helper
++ * @dev: Device from iommu_get_resv_regions()
++ * @list: Reserved region list from iommu_get_resv_regions()
++ *
++ * IOMMU drivers can use this to implement their .get_resv_regions callback
++ * for general non-IOMMU-specific reservations. Currently, this covers host
++ * bridge windows for PCI devices.
++ */
++void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
+ {
+-	struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
++	struct pci_host_bridge *bridge;
+ 	struct resource_entry *window;
+-	unsigned long lo, hi;
+ 
++	if (!dev_is_pci(dev))
++		return;
++
++	bridge = pci_find_host_bridge(to_pci_dev(dev)->bus);
+ 	resource_list_for_each_entry(window, &bridge->windows) {
++		struct iommu_resv_region *region;
++		phys_addr_t start;
++		size_t length;
++
+ 		if (resource_type(window->res) != IORESOURCE_MEM)
+ 			continue;
+ 
+-		lo = iova_pfn(iovad, window->res->start - window->offset);
+-		hi = iova_pfn(iovad, window->res->end - window->offset);
++		start = window->res->start - window->offset;
++		length = window->res->end - window->res->start + 1;
++		region = iommu_alloc_resv_region(start, length, 0,
++				IOMMU_RESV_RESERVED);
++		if (!region)
++			return;
++
++		list_add_tail(&region->list, list);
++	}
++}
++EXPORT_SYMBOL(iommu_dma_get_resv_regions);
++
++static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie,
++		phys_addr_t start, phys_addr_t end)
++{
++	struct iova_domain *iovad = &cookie->iovad;
++	struct iommu_dma_msi_page *msi_page;
++	int i, num_pages;
++
++	start -= iova_offset(iovad, start);
++	num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
++
++	msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL);
++	if (!msi_page)
++		return -ENOMEM;
++
++	for (i = 0; i < num_pages; i++) {
++		msi_page[i].phys = start;
++		msi_page[i].iova = start;
++		INIT_LIST_HEAD(&msi_page[i].list);
++		list_add(&msi_page[i].list, &cookie->msi_page_list);
++		start += iovad->granule;
++	}
++
++	return 0;
++}
++
++static int iova_reserve_iommu_regions(struct device *dev,
++		struct iommu_domain *domain)
++{
++	struct iommu_dma_cookie *cookie = domain->iova_cookie;
++	struct iova_domain *iovad = &cookie->iovad;
++	struct iommu_resv_region *region;
++	LIST_HEAD(resv_regions);
++	int ret = 0;
++
++	iommu_get_resv_regions(dev, &resv_regions);
++	list_for_each_entry(region, &resv_regions, list) {
++		unsigned long lo, hi;
++
++		/* We ARE the software that manages these! */
++		if (region->type == IOMMU_RESV_SW_MSI)
++			continue;
++
++		lo = iova_pfn(iovad, region->start);
++		hi = iova_pfn(iovad, region->start + region->length - 1);
+ 		reserve_iova(iovad, lo, hi);
++
++		if (region->type == IOMMU_RESV_MSI)
++			ret = cookie_init_hw_msi_region(cookie, region->start,
++					region->start + region->length);
++		if (ret)
++			break;
+ 	}
++	iommu_put_resv_regions(dev, &resv_regions);
++
++	return ret;
+ }
+ 
+ /**
+@@ -136,11 +277,12 @@ static void iova_reserve_pci_windows(str
+ int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
+ 		u64 size, struct device *dev)
+ {
+-	struct iova_domain *iovad = cookie_iovad(domain);
++	struct iommu_dma_cookie *cookie = domain->iova_cookie;
++	struct iova_domain *iovad = &cookie->iovad;
+ 	unsigned long order, base_pfn, end_pfn;
+ 
+-	if (!iovad)
+-		return -ENODEV;
++	if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
++		return -EINVAL;
+ 
+ 	/* Use the smallest supported page size for IOVA granularity */
+ 	order = __ffs(domain->pgsize_bitmap);
+@@ -160,22 +302,37 @@ int iommu_dma_init_domain(struct iommu_d
+ 		end_pfn = min_t(unsigned long, end_pfn,
+ 				domain->geometry.aperture_end >> order);
+ 	}
++	/*
++	 * PCI devices may have larger DMA masks, but still prefer allocating
++	 * within a 32-bit mask to avoid DAC addressing. Such limitations don't
++	 * apply to the typical platform device, so for those we may as well
++	 * leave the cache limit at the top of their range to save an rb_last()
++	 * traversal on every allocation.
++	 */
++	if (dev && dev_is_pci(dev))
++		end_pfn &= DMA_BIT_MASK(32) >> order;
+ 
+-	/* All we can safely do with an existing domain is enlarge it */
++	/* start_pfn is always nonzero for an already-initialised domain */
+ 	if (iovad->start_pfn) {
+ 		if (1UL << order != iovad->granule ||
+-		    base_pfn != iovad->start_pfn ||
+-		    end_pfn < iovad->dma_32bit_pfn) {
++		    base_pfn != iovad->start_pfn) {
+ 			pr_warn("Incompatible range for DMA domain\n");
+ 			return -EFAULT;
+ 		}
+-		iovad->dma_32bit_pfn = end_pfn;
+-	} else {
+-		init_iova_domain(iovad, 1UL << order, base_pfn, end_pfn);
+-		if (dev && dev_is_pci(dev))
+-			iova_reserve_pci_windows(to_pci_dev(dev), iovad);
++		/*
++		 * If we have devices with different DMA masks, move the free
++		 * area cache limit down for the benefit of the smaller one.
++		 */
++		iovad->dma_32bit_pfn = min(end_pfn, iovad->dma_32bit_pfn);
++
++		return 0;
+ 	}
+-	return 0;
++
++	init_iova_domain(iovad, 1UL << order, base_pfn, end_pfn);
++	if (!dev)
++		return 0;
++
++	return iova_reserve_iommu_regions(dev, domain);
+ }
+ EXPORT_SYMBOL(iommu_dma_init_domain);
+ 
+@@ -643,11 +800,12 @@ static struct iommu_dma_msi_page *iommu_
+ {
+ 	struct iommu_dma_cookie *cookie = domain->iova_cookie;
+ 	struct iommu_dma_msi_page *msi_page;
+-	struct iova_domain *iovad = &cookie->iovad;
++	struct iova_domain *iovad = cookie_iovad(domain);
+ 	struct iova *iova;
+ 	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
++	size_t size = cookie_msi_granule(cookie);
+ 
+-	msi_addr &= ~(phys_addr_t)iova_mask(iovad);
++	msi_addr &= ~(phys_addr_t)(size - 1);
+ 	list_for_each_entry(msi_page, &cookie->msi_page_list, list)
+ 		if (msi_page->phys == msi_addr)
+ 			return msi_page;
+@@ -656,13 +814,18 @@ static struct iommu_dma_msi_page *iommu_
+ 	if (!msi_page)
+ 		return NULL;
+ 
+-	iova = __alloc_iova(domain, iovad->granule, dma_get_mask(dev));
+-	if (!iova)
+-		goto out_free_page;
+-
+ 	msi_page->phys = msi_addr;
+-	msi_page->iova = iova_dma_addr(iovad, iova);
+-	if (iommu_map(domain, msi_page->iova, msi_addr, iovad->granule, prot))
++	if (iovad) {
++		iova = __alloc_iova(domain, size, dma_get_mask(dev));
++		if (!iova)
++			goto out_free_page;
++		msi_page->iova = iova_dma_addr(iovad, iova);
++	} else {
++		msi_page->iova = cookie->msi_iova;
++		cookie->msi_iova += size;
++	}
++
++	if (iommu_map(domain, msi_page->iova, msi_addr, size, prot))
+ 		goto out_free_iova;
+ 
+ 	INIT_LIST_HEAD(&msi_page->list);
+@@ -670,7 +833,10 @@ static struct iommu_dma_msi_page *iommu_
+ 	return msi_page;
+ 
+ out_free_iova:
+-	__free_iova(iovad, iova);
++	if (iovad)
++		__free_iova(iovad, iova);
++	else
++		cookie->msi_iova -= size;
+ out_free_page:
+ 	kfree(msi_page);
+ 	return NULL;
+@@ -711,7 +877,7 @@ void iommu_dma_map_msi_msg(int irq, stru
+ 		msg->data = ~0U;
+ 	} else {
+ 		msg->address_hi = upper_32_bits(msi_page->iova);
+-		msg->address_lo &= iova_mask(&cookie->iovad);
++		msg->address_lo &= cookie_msi_granule(cookie) - 1;
+ 		msg->address_lo += lower_32_bits(msi_page->iova);
+ 	}
+ }
+--- a/drivers/iommu/intel-iommu.c
++++ b/drivers/iommu/intel-iommu.c
+@@ -441,6 +441,7 @@ struct dmar_rmrr_unit {
+ 	u64	end_address;		/* reserved end address */
+ 	struct dmar_dev_scope *devices;	/* target devices */
+ 	int	devices_cnt;		/* target device count */
++	struct iommu_resv_region *resv; /* reserved region handle */
+ };
+ 
+ struct dmar_atsr_unit {
+@@ -4267,27 +4268,40 @@ static inline void init_iommu_pm_ops(voi
+ int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg)
+ {
+ 	struct acpi_dmar_reserved_memory *rmrr;
++	int prot = DMA_PTE_READ|DMA_PTE_WRITE;
+ 	struct dmar_rmrr_unit *rmrru;
++	size_t length;
+ 
+ 	rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
+ 	if (!rmrru)
+-		return -ENOMEM;
++		goto out;
+ 
+ 	rmrru->hdr = header;
+ 	rmrr = (struct acpi_dmar_reserved_memory *)header;
+ 	rmrru->base_address = rmrr->base_address;
+ 	rmrru->end_address = rmrr->end_address;
++
++	length = rmrr->end_address - rmrr->base_address + 1;
++	rmrru->resv = iommu_alloc_resv_region(rmrr->base_address, length, prot,
++					      IOMMU_RESV_DIRECT);
++	if (!rmrru->resv)
++		goto free_rmrru;
++
+ 	rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
+ 				((void *)rmrr) + rmrr->header.length,
+ 				&rmrru->devices_cnt);
+-	if (rmrru->devices_cnt && rmrru->devices == NULL) {
+-		kfree(rmrru);
+-		return -ENOMEM;
+-	}
++	if (rmrru->devices_cnt && rmrru->devices == NULL)
++		goto free_all;
+ 
+ 	list_add(&rmrru->list, &dmar_rmrr_units);
+ 
+ 	return 0;
++free_all:
++	kfree(rmrru->resv);
++free_rmrru:
++	kfree(rmrru);
++out:
++	return -ENOMEM;
+ }
+ 
+ static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr)
+@@ -4501,6 +4515,7 @@ static void intel_iommu_free_dmars(void)
+ 	list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
+ 		list_del(&rmrru->list);
+ 		dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
++		kfree(rmrru->resv);
+ 		kfree(rmrru);
+ 	}
+ 
+@@ -5236,6 +5251,45 @@ static void intel_iommu_remove_device(st
+ 	iommu_device_unlink(iommu->iommu_dev, dev);
+ }
+ 
++static void intel_iommu_get_resv_regions(struct device *device,
++					 struct list_head *head)
++{
++	struct iommu_resv_region *reg;
++	struct dmar_rmrr_unit *rmrr;
++	struct device *i_dev;
++	int i;
++
++	rcu_read_lock();
++	for_each_rmrr_units(rmrr) {
++		for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
++					  i, i_dev) {
++			if (i_dev != device)
++				continue;
++
++			list_add_tail(&rmrr->resv->list, head);
++		}
++	}
++	rcu_read_unlock();
++
++	reg = iommu_alloc_resv_region(IOAPIC_RANGE_START,
++				      IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1,
++				      0, IOMMU_RESV_MSI);
++	if (!reg)
++		return;
++	list_add_tail(&reg->list, head);
++}
++
++static void intel_iommu_put_resv_regions(struct device *dev,
++					 struct list_head *head)
++{
++	struct iommu_resv_region *entry, *next;
++
++	list_for_each_entry_safe(entry, next, head, list) {
++		if (entry->type == IOMMU_RESV_RESERVED)
++			kfree(entry);
++	}
++}
++
+ #ifdef CONFIG_INTEL_IOMMU_SVM
+ #define MAX_NR_PASID_BITS (20)
+ static inline unsigned long intel_iommu_get_pts(struct intel_iommu *iommu)
+@@ -5366,19 +5420,21 @@ struct intel_iommu *intel_svm_device_to_
+ #endif /* CONFIG_INTEL_IOMMU_SVM */
+ 
+ static const struct iommu_ops intel_iommu_ops = {
+-	.capable	= intel_iommu_capable,
+-	.domain_alloc	= intel_iommu_domain_alloc,
+-	.domain_free	= intel_iommu_domain_free,
+-	.attach_dev	= intel_iommu_attach_device,
+-	.detach_dev	= intel_iommu_detach_device,
+-	.map		= intel_iommu_map,
+-	.unmap		= intel_iommu_unmap,
+-	.map_sg		= default_iommu_map_sg,
+-	.iova_to_phys	= intel_iommu_iova_to_phys,
+-	.add_device	= intel_iommu_add_device,
+-	.remove_device	= intel_iommu_remove_device,
+-	.device_group   = pci_device_group,
+-	.pgsize_bitmap	= INTEL_IOMMU_PGSIZES,
++	.capable		= intel_iommu_capable,
++	.domain_alloc		= intel_iommu_domain_alloc,
++	.domain_free		= intel_iommu_domain_free,
++	.attach_dev		= intel_iommu_attach_device,
++	.detach_dev		= intel_iommu_detach_device,
++	.map			= intel_iommu_map,
++	.unmap			= intel_iommu_unmap,
++	.map_sg			= default_iommu_map_sg,
++	.iova_to_phys		= intel_iommu_iova_to_phys,
++	.add_device		= intel_iommu_add_device,
++	.remove_device		= intel_iommu_remove_device,
++	.get_resv_regions	= intel_iommu_get_resv_regions,
++	.put_resv_regions	= intel_iommu_put_resv_regions,
++	.device_group		= pci_device_group,
++	.pgsize_bitmap		= INTEL_IOMMU_PGSIZES,
+ };
+ 
+ static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
+--- a/drivers/iommu/iommu.c
++++ b/drivers/iommu/iommu.c
+@@ -33,9 +33,11 @@
+ #include <linux/bitops.h>
+ #include <linux/property.h>
+ #include <trace/events/iommu.h>
++#include <linux/fsl/mc.h>
+ 
+ static struct kset *iommu_group_kset;
+ static DEFINE_IDA(iommu_group_ida);
++static unsigned int iommu_def_domain_type = IOMMU_DOMAIN_DMA;
+ 
+ struct iommu_callback_data {
+ 	const struct iommu_ops *ops;
+@@ -68,6 +70,13 @@ struct iommu_group_attribute {
+ 			 const char *buf, size_t count);
+ };
+ 
++static const char * const iommu_group_resv_type_string[] = {
++	[IOMMU_RESV_DIRECT]	= "direct",
++	[IOMMU_RESV_RESERVED]	= "reserved",
++	[IOMMU_RESV_MSI]	= "msi",
++	[IOMMU_RESV_SW_MSI]	= "msi",
++};
++
+ #define IOMMU_GROUP_ATTR(_name, _mode, _show, _store)		\
+ struct iommu_group_attribute iommu_group_attr_##_name =		\
+ 	__ATTR(_name, _mode, _show, _store)
+@@ -86,6 +95,18 @@ static int __iommu_attach_group(struct i
+ static void __iommu_detach_group(struct iommu_domain *domain,
+ 				 struct iommu_group *group);
+ 
++static int __init iommu_set_def_domain_type(char *str)
++{
++	bool pt;
++
++	if (!str || strtobool(str, &pt))
++		return -EINVAL;
++
++	iommu_def_domain_type = pt ? IOMMU_DOMAIN_IDENTITY : IOMMU_DOMAIN_DMA;
++	return 0;
++}
++early_param("iommu.passthrough", iommu_set_def_domain_type);
++
+ static ssize_t iommu_group_attr_show(struct kobject *kobj,
+ 				     struct attribute *__attr, char *buf)
+ {
+@@ -133,8 +154,131 @@ static ssize_t iommu_group_show_name(str
+ 	return sprintf(buf, "%s\n", group->name);
+ }
+ 
++/**
++ * iommu_insert_resv_region - Insert a new region in the
++ * list of reserved regions.
++ * @new: new region to insert
++ * @regions: list of regions
++ *
++ * The new element is sorted by address with respect to the other
++ * regions of the same type. In case it overlaps with another
++ * region of the same type, regions are merged. In case it
++ * overlaps with another region of different type, regions are
++ * not merged.
++ */
++static int iommu_insert_resv_region(struct iommu_resv_region *new,
++				    struct list_head *regions)
++{
++	struct iommu_resv_region *region;
++	phys_addr_t start = new->start;
++	phys_addr_t end = new->start + new->length - 1;
++	struct list_head *pos = regions->next;
++
++	while (pos != regions) {
++		struct iommu_resv_region *entry =
++			list_entry(pos, struct iommu_resv_region, list);
++		phys_addr_t a = entry->start;
++		phys_addr_t b = entry->start + entry->length - 1;
++		int type = entry->type;
++
++		if (end < a) {
++			goto insert;
++		} else if (start > b) {
++			pos = pos->next;
++		} else if ((start >= a) && (end <= b)) {
++			if (new->type == type)
++				goto done;
++			else
++				pos = pos->next;
++		} else {
++			if (new->type == type) {
++				phys_addr_t new_start = min(a, start);
++				phys_addr_t new_end = max(b, end);
++
++				list_del(&entry->list);
++				entry->start = new_start;
++				entry->length = new_end - new_start + 1;
++				iommu_insert_resv_region(entry, regions);
++			} else {
++				pos = pos->next;
++			}
++		}
++	}
++insert:
++	region = iommu_alloc_resv_region(new->start, new->length,
++					 new->prot, new->type);
++	if (!region)
++		return -ENOMEM;
++
++	list_add_tail(&region->list, pos);
++done:
++	return 0;
++}
++
++static int
++iommu_insert_device_resv_regions(struct list_head *dev_resv_regions,
++				 struct list_head *group_resv_regions)
++{
++	struct iommu_resv_region *entry;
++	int ret;
++
++	list_for_each_entry(entry, dev_resv_regions, list) {
++		ret = iommu_insert_resv_region(entry, group_resv_regions);
++		if (ret)
++			break;
++	}
++	return ret;
++}
++
++int iommu_get_group_resv_regions(struct iommu_group *group,
++				 struct list_head *head)
++{
++	struct iommu_device *device;
++	int ret = 0;
++
++	mutex_lock(&group->mutex);
++	list_for_each_entry(device, &group->devices, list) {
++		struct list_head dev_resv_regions;
++
++		INIT_LIST_HEAD(&dev_resv_regions);
++		iommu_get_resv_regions(device->dev, &dev_resv_regions);
++		ret = iommu_insert_device_resv_regions(&dev_resv_regions, head);
++		iommu_put_resv_regions(device->dev, &dev_resv_regions);
++		if (ret)
++			break;
++	}
++	mutex_unlock(&group->mutex);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(iommu_get_group_resv_regions);
++
++static ssize_t iommu_group_show_resv_regions(struct iommu_group *group,
++					     char *buf)
++{
++	struct iommu_resv_region *region, *next;
++	struct list_head group_resv_regions;
++	char *str = buf;
++
++	INIT_LIST_HEAD(&group_resv_regions);
++	iommu_get_group_resv_regions(group, &group_resv_regions);
++
++	list_for_each_entry_safe(region, next, &group_resv_regions, list) {
++		str += sprintf(str, "0x%016llx 0x%016llx %s\n",
++			       (long long int)region->start,
++			       (long long int)(region->start +
++						region->length - 1),
++			       iommu_group_resv_type_string[region->type]);
++		kfree(region);
++	}
++
++	return (str - buf);
++}
++
+ static IOMMU_GROUP_ATTR(name, S_IRUGO, iommu_group_show_name, NULL);
+ 
++static IOMMU_GROUP_ATTR(reserved_regions, 0444,
++			iommu_group_show_resv_regions, NULL);
++
+ static void iommu_group_release(struct kobject *kobj)
+ {
+ 	struct iommu_group *group = to_iommu_group(kobj);
+@@ -212,6 +356,11 @@ struct iommu_group *iommu_group_alloc(vo
+ 	 */
+ 	kobject_put(&group->kobj);
+ 
++	ret = iommu_group_create_file(group,
++				      &iommu_group_attr_reserved_regions);
++	if (ret)
++		return ERR_PTR(ret);
++
+ 	pr_debug("Allocated group %d\n", group->id);
+ 
+ 	return group;
+@@ -318,7 +467,7 @@ static int iommu_group_create_direct_map
+ 					      struct device *dev)
+ {
+ 	struct iommu_domain *domain = group->default_domain;
+-	struct iommu_dm_region *entry;
++	struct iommu_resv_region *entry;
+ 	struct list_head mappings;
+ 	unsigned long pg_size;
+ 	int ret = 0;
+@@ -331,18 +480,21 @@ static int iommu_group_create_direct_map
+ 	pg_size = 1UL << __ffs(domain->pgsize_bitmap);
+ 	INIT_LIST_HEAD(&mappings);
+ 
+-	iommu_get_dm_regions(dev, &mappings);
++	iommu_get_resv_regions(dev, &mappings);
+ 
+ 	/* We need to consider overlapping regions for different devices */
+ 	list_for_each_entry(entry, &mappings, list) {
+ 		dma_addr_t start, end, addr;
+ 
+-		if (domain->ops->apply_dm_region)
+-			domain->ops->apply_dm_region(dev, domain, entry);
++		if (domain->ops->apply_resv_region)
++			domain->ops->apply_resv_region(dev, domain, entry);
+ 
+ 		start = ALIGN(entry->start, pg_size);
+ 		end   = ALIGN(entry->start + entry->length, pg_size);
+ 
++		if (entry->type != IOMMU_RESV_DIRECT)
++			continue;
++
+ 		for (addr = start; addr < end; addr += pg_size) {
+ 			phys_addr_t phys_addr;
+ 
+@@ -358,7 +510,7 @@ static int iommu_group_create_direct_map
+ 	}
+ 
+ out:
+-	iommu_put_dm_regions(dev, &mappings);
++	iommu_put_resv_regions(dev, &mappings);
+ 
+ 	return ret;
+ }
+@@ -563,6 +715,19 @@ struct iommu_group *iommu_group_get(stru
+ EXPORT_SYMBOL_GPL(iommu_group_get);
+ 
+ /**
++ * iommu_group_ref_get - Increment reference on a group
++ * @group: the group to use, must not be NULL
++ *
++ * This function is called by iommu drivers to take additional references on an
++ * existing group.  Returns the given group for convenience.
++ */
++struct iommu_group *iommu_group_ref_get(struct iommu_group *group)
++{
++	kobject_get(group->devices_kobj);
++	return group;
++}
++
++/**
+  * iommu_group_put - Decrement group reference
+  * @group: the group to use
+  *
+@@ -812,6 +977,26 @@ struct iommu_group *pci_device_group(str
+ 	return group;
+ }
+ 
++/* Get the IOMMU group for device on fsl-mc bus */
++struct iommu_group *fsl_mc_device_group(struct device *dev)
++{
++	struct device *cont_dev = fsl_mc_cont_dev(dev);
++	struct iommu_group *group;
++
++	/* Container device is responsible for creating the iommu group */
++	if (fsl_mc_is_cont_dev(dev)) {
++		group = iommu_group_alloc();
++		if (IS_ERR(group))
++			return NULL;
++	} else {
++		get_device(cont_dev);
++		group = iommu_group_get(cont_dev);
++		put_device(cont_dev);
++	}
++
++	return group;
++}
++
+ /**
+  * iommu_group_get_for_dev - Find or create the IOMMU group for a device
+  * @dev: target device
+@@ -845,10 +1030,19 @@ struct iommu_group *iommu_group_get_for_
+ 	 * IOMMU driver.
+ 	 */
+ 	if (!group->default_domain) {
+-		group->default_domain = __iommu_domain_alloc(dev->bus,
+-							     IOMMU_DOMAIN_DMA);
++		struct iommu_domain *dom;
++
++		dom = __iommu_domain_alloc(dev->bus, iommu_def_domain_type);
++		if (!dom && iommu_def_domain_type != IOMMU_DOMAIN_DMA) {
++			dev_warn(dev,
++				 "failed to allocate default IOMMU domain of type %u; falling back to IOMMU_DOMAIN_DMA",
++				 iommu_def_domain_type);
++			dom = __iommu_domain_alloc(dev->bus, IOMMU_DOMAIN_DMA);
++		}
++
++		group->default_domain = dom;
+ 		if (!group->domain)
+-			group->domain = group->default_domain;
++			group->domain = dom;
+ 	}
+ 
+ 	ret = iommu_group_add_device(group, dev);
+@@ -1557,20 +1751,38 @@ int iommu_domain_set_attr(struct iommu_d
+ }
+ EXPORT_SYMBOL_GPL(iommu_domain_set_attr);
+ 
+-void iommu_get_dm_regions(struct device *dev, struct list_head *list)
++void iommu_get_resv_regions(struct device *dev, struct list_head *list)
+ {
+ 	const struct iommu_ops *ops = dev->bus->iommu_ops;
+ 
+-	if (ops && ops->get_dm_regions)
+-		ops->get_dm_regions(dev, list);
++	if (ops && ops->get_resv_regions)
++		ops->get_resv_regions(dev, list);
+ }
+ 
+-void iommu_put_dm_regions(struct device *dev, struct list_head *list)
++void iommu_put_resv_regions(struct device *dev, struct list_head *list)
+ {
+ 	const struct iommu_ops *ops = dev->bus->iommu_ops;
+ 
+-	if (ops && ops->put_dm_regions)
+-		ops->put_dm_regions(dev, list);
++	if (ops && ops->put_resv_regions)
++		ops->put_resv_regions(dev, list);
++}
++
++struct iommu_resv_region *iommu_alloc_resv_region(phys_addr_t start,
++						  size_t length, int prot,
++						  enum iommu_resv_type type)
++{
++	struct iommu_resv_region *region;
++
++	region = kzalloc(sizeof(*region), GFP_KERNEL);
++	if (!region)
++		return NULL;
++
++	INIT_LIST_HEAD(&region->list);
++	region->start = start;
++	region->length = length;
++	region->prot = prot;
++	region->type = type;
++	return region;
+ }
+ 
+ /* Request that a device is direct mapped by the IOMMU */
+--- a/drivers/iommu/mtk_iommu.c
++++ b/drivers/iommu/mtk_iommu.c
+@@ -410,6 +410,8 @@ static struct iommu_group *mtk_iommu_dev
+ 		data->m4u_group = iommu_group_alloc();
+ 		if (IS_ERR(data->m4u_group))
+ 			dev_err(dev, "Failed to allocate M4U IOMMU group\n");
++	} else {
++		iommu_group_ref_get(data->m4u_group);
+ 	}
+ 	return data->m4u_group;
+ }
+--- a/drivers/iommu/mtk_iommu_v1.c
++++ b/drivers/iommu/mtk_iommu_v1.c
+@@ -502,6 +502,8 @@ static struct iommu_group *mtk_iommu_dev
+ 		data->m4u_group = iommu_group_alloc();
+ 		if (IS_ERR(data->m4u_group))
+ 			dev_err(dev, "Failed to allocate M4U IOMMU group\n");
++	} else {
++		iommu_group_ref_get(data->m4u_group);
+ 	}
+ 	return data->m4u_group;
+ }
+--- a/include/linux/dma-iommu.h
++++ b/include/linux/dma-iommu.h
+@@ -28,6 +28,7 @@ int iommu_dma_init(void);
+ 
+ /* Domain management interface for IOMMU drivers */
+ int iommu_get_dma_cookie(struct iommu_domain *domain);
++int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base);
+ void iommu_put_dma_cookie(struct iommu_domain *domain);
+ 
+ /* Setup call for arch DMA mapping code */
+@@ -67,6 +68,7 @@ int iommu_dma_mapping_error(struct devic
+ 
+ /* The DMA API isn't _quite_ the whole story, though... */
+ void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg);
++void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list);
+ 
+ #else
+ 
+@@ -83,6 +85,11 @@ static inline int iommu_get_dma_cookie(s
+ 	return -ENODEV;
+ }
+ 
++static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
++{
++	return -ENODEV;
++}
++
+ static inline void iommu_put_dma_cookie(struct iommu_domain *domain)
+ {
+ }
+@@ -91,6 +98,10 @@ static inline void iommu_dma_map_msi_msg
+ {
+ }
+ 
++static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
++{
++}
++
+ #endif	/* CONFIG_IOMMU_DMA */
+ #endif	/* __KERNEL__ */
+ #endif	/* __DMA_IOMMU_H */
+--- a/include/linux/iommu.h
++++ b/include/linux/iommu.h
+@@ -117,18 +117,32 @@ enum iommu_attr {
+ 	DOMAIN_ATTR_MAX,
+ };
+ 
++/* These are the possible reserved region types */
++enum iommu_resv_type {
++	/* Memory regions which must be mapped 1:1 at all times */
++	IOMMU_RESV_DIRECT,
++	/* Arbitrary "never map this or give it to a device" address ranges */
++	IOMMU_RESV_RESERVED,
++	/* Hardware MSI region (untranslated) */
++	IOMMU_RESV_MSI,
++	/* Software-managed MSI translation window */
++	IOMMU_RESV_SW_MSI,
++};
++
+ /**
+- * struct iommu_dm_region - descriptor for a direct mapped memory region
++ * struct iommu_resv_region - descriptor for a reserved memory region
+  * @list: Linked list pointers
+  * @start: System physical start address of the region
+  * @length: Length of the region in bytes
+  * @prot: IOMMU Protection flags (READ/WRITE/...)
++ * @type: Type of the reserved region
+  */
+-struct iommu_dm_region {
++struct iommu_resv_region {
+ 	struct list_head	list;
+ 	phys_addr_t		start;
+ 	size_t			length;
+ 	int			prot;
++	enum iommu_resv_type	type;
+ };
+ 
+ #ifdef CONFIG_IOMMU_API
+@@ -150,9 +164,9 @@ struct iommu_dm_region {
+  * @device_group: find iommu group for a particular device
+  * @domain_get_attr: Query domain attributes
+  * @domain_set_attr: Change domain attributes
+- * @get_dm_regions: Request list of direct mapping requirements for a device
+- * @put_dm_regions: Free list of direct mapping requirements for a device
+- * @apply_dm_region: Temporary helper call-back for iova reserved ranges
++ * @get_resv_regions: Request list of reserved regions for a device
++ * @put_resv_regions: Free list of reserved regions for a device
++ * @apply_resv_region: Temporary helper call-back for iova reserved ranges
+  * @domain_window_enable: Configure and enable a particular window for a domain
+  * @domain_window_disable: Disable a particular window for a domain
+  * @domain_set_windows: Set the number of windows for a domain
+@@ -184,11 +198,12 @@ struct iommu_ops {
+ 	int (*domain_set_attr)(struct iommu_domain *domain,
+ 			       enum iommu_attr attr, void *data);
+ 
+-	/* Request/Free a list of direct mapping requirements for a device */
+-	void (*get_dm_regions)(struct device *dev, struct list_head *list);
+-	void (*put_dm_regions)(struct device *dev, struct list_head *list);
+-	void (*apply_dm_region)(struct device *dev, struct iommu_domain *domain,
+-				struct iommu_dm_region *region);
++	/* Request/Free a list of reserved regions for a device */
++	void (*get_resv_regions)(struct device *dev, struct list_head *list);
++	void (*put_resv_regions)(struct device *dev, struct list_head *list);
++	void (*apply_resv_region)(struct device *dev,
++				  struct iommu_domain *domain,
++				  struct iommu_resv_region *region);
+ 
+ 	/* Window handling functions */
+ 	int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr,
+@@ -233,9 +248,14 @@ extern phys_addr_t iommu_iova_to_phys(st
+ extern void iommu_set_fault_handler(struct iommu_domain *domain,
+ 			iommu_fault_handler_t handler, void *token);
+ 
+-extern void iommu_get_dm_regions(struct device *dev, struct list_head *list);
+-extern void iommu_put_dm_regions(struct device *dev, struct list_head *list);
++extern void iommu_get_resv_regions(struct device *dev, struct list_head *list);
++extern void iommu_put_resv_regions(struct device *dev, struct list_head *list);
+ extern int iommu_request_dm_for_dev(struct device *dev);
++extern struct iommu_resv_region *
++iommu_alloc_resv_region(phys_addr_t start, size_t length, int prot,
++			enum iommu_resv_type type);
++extern int iommu_get_group_resv_regions(struct iommu_group *group,
++					struct list_head *head);
+ 
+ extern int iommu_attach_group(struct iommu_domain *domain,
+ 			      struct iommu_group *group);
+@@ -253,6 +273,7 @@ extern void iommu_group_remove_device(st
+ extern int iommu_group_for_each_dev(struct iommu_group *group, void *data,
+ 				    int (*fn)(struct device *, void *));
+ extern struct iommu_group *iommu_group_get(struct device *dev);
++extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group);
+ extern void iommu_group_put(struct iommu_group *group);
+ extern int iommu_group_register_notifier(struct iommu_group *group,
+ 					 struct notifier_block *nb);
+@@ -330,6 +351,8 @@ static inline size_t iommu_map_sg(struct
+ extern struct iommu_group *pci_device_group(struct device *dev);
+ /* Generic device grouping function */
+ extern struct iommu_group *generic_device_group(struct device *dev);
++/* FSL-MC device grouping function */
++struct iommu_group *fsl_mc_device_group(struct device *dev);
+ 
+ /**
+  * struct iommu_fwspec - per-device IOMMU instance data
+@@ -439,16 +462,22 @@ static inline void iommu_set_fault_handl
+ {
+ }
+ 
+-static inline void iommu_get_dm_regions(struct device *dev,
++static inline void iommu_get_resv_regions(struct device *dev,
+ 					struct list_head *list)
+ {
+ }
+ 
+-static inline void iommu_put_dm_regions(struct device *dev,
++static inline void iommu_put_resv_regions(struct device *dev,
+ 					struct list_head *list)
+ {
+ }
+ 
++static inline int iommu_get_group_resv_regions(struct iommu_group *group,
++					       struct list_head *head)
++{
++	return -ENODEV;
++}
++
+ static inline int iommu_request_dm_for_dev(struct device *dev)
+ {
+ 	return -ENODEV;
diff --git a/target/linux/layerscape/patches-4.9/811-irqchip-support-layerscape.patch b/target/linux/layerscape/patches-4.9/811-irqchip-support-layerscape.patch
new file mode 100644
index 000000000..3aca25267
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/811-irqchip-support-layerscape.patch
@@ -0,0 +1,182 @@
+From dab02a7cc54494740e849cd51b554d100eb5541d Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:36:09 +0800
+Subject: [PATCH 23/32] irqchip: support layerscape
+
+This is an integrated patch for layerscape gic support.
+
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/irqchip/Makefile           |  1 +
+ drivers/irqchip/irq-gic-v3-its.c   |  1 +
+ include/linux/irqchip/arm-gic-v3.h |  3 +++
+ include/linux/irqdomain.h          | 36 +++++++++++++++++++++++++++
+ kernel/irq/irqdomain.c             | 39 ++++++++++++++++++++++++++++++
+ kernel/irq/msi.c                   |  4 +--
+ 6 files changed, 82 insertions(+), 2 deletions(-)
+
+--- a/drivers/irqchip/Makefile
++++ b/drivers/irqchip/Makefile
+@@ -75,3 +75,4 @@ obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scf
+ obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
+ obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o
+ obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
++obj-$(CONFIG_QUICC_ENGINE)		+= irq-qeic.o
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -1658,6 +1658,7 @@ static int its_init_domain(struct fwnode
+ 
+ 	inner_domain->parent = its_parent;
+ 	inner_domain->bus_token = DOMAIN_BUS_NEXUS;
++	inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP;
+ 	info->ops = &its_msi_domain_ops;
+ 	info->data = its;
+ 	inner_domain->host_data = info;
+--- a/include/linux/irqchip/arm-gic-v3.h
++++ b/include/linux/irqchip/arm-gic-v3.h
+@@ -133,6 +133,9 @@
+ #define GIC_BASER_SHAREABILITY(reg, type)				\
+ 	(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
+ 
++/* encode a size field of width @w containing @n - 1 units */
++#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
++
+ #define GICR_PROPBASER_SHAREABILITY_SHIFT		(10)
+ #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT		(7)
+ #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT		(56)
+--- a/include/linux/irqdomain.h
++++ b/include/linux/irqdomain.h
+@@ -187,6 +187,12 @@ enum {
+ 	/* Irq domain is an IPI domain with single virq */
+ 	IRQ_DOMAIN_FLAG_IPI_SINGLE	= (1 << 3),
+ 
++	/* Irq domain implements MSIs */
++	IRQ_DOMAIN_FLAG_MSI		= (1 << 4),
++
++	/* Irq domain implements MSI remapping */
++	IRQ_DOMAIN_FLAG_MSI_REMAP	= (1 << 5),
++
+ 	/*
+ 	 * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved
+ 	 * for implementation specific purposes and ignored by the
+@@ -220,6 +226,7 @@ struct irq_domain *irq_domain_add_legacy
+ 					 void *host_data);
+ extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec,
+ 						   enum irq_domain_bus_token bus_token);
++extern bool irq_domain_check_msi_remap(void);
+ extern void irq_set_default_host(struct irq_domain *host);
+ extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs,
+ 				  irq_hw_number_t hwirq, int node,
+@@ -453,6 +460,19 @@ static inline bool irq_domain_is_ipi_sin
+ {
+ 	return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE;
+ }
++
++static inline bool irq_domain_is_msi(struct irq_domain *domain)
++{
++	return domain->flags & IRQ_DOMAIN_FLAG_MSI;
++}
++
++static inline bool irq_domain_is_msi_remap(struct irq_domain *domain)
++{
++	return domain->flags & IRQ_DOMAIN_FLAG_MSI_REMAP;
++}
++
++extern bool irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain);
++
+ #else	/* CONFIG_IRQ_DOMAIN_HIERARCHY */
+ static inline void irq_domain_activate_irq(struct irq_data *data) { }
+ static inline void irq_domain_deactivate_irq(struct irq_data *data) { }
+@@ -484,6 +504,22 @@ static inline bool irq_domain_is_ipi_sin
+ {
+ 	return false;
+ }
++
++static inline bool irq_domain_is_msi(struct irq_domain *domain)
++{
++	return false;
++}
++
++static inline bool irq_domain_is_msi_remap(struct irq_domain *domain)
++{
++	return false;
++}
++
++static inline bool
++irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain)
++{
++	return false;
++}
+ #endif	/* CONFIG_IRQ_DOMAIN_HIERARCHY */
+ 
+ #else /* CONFIG_IRQ_DOMAIN */
+--- a/kernel/irq/irqdomain.c
++++ b/kernel/irq/irqdomain.c
+@@ -319,6 +319,31 @@ struct irq_domain *irq_find_matching_fws
+ EXPORT_SYMBOL_GPL(irq_find_matching_fwspec);
+ 
+ /**
++ * irq_domain_check_msi_remap - Check whether all MSI irq domains implement
++ * IRQ remapping
++ *
++ * Return: false if any MSI irq domain does not support IRQ remapping,
++ * true otherwise (including if there is no MSI irq domain)
++ */
++bool irq_domain_check_msi_remap(void)
++{
++	struct irq_domain *h;
++	bool ret = true;
++
++	mutex_lock(&irq_domain_mutex);
++	list_for_each_entry(h, &irq_domain_list, link) {
++		if (irq_domain_is_msi(h) &&
++		    !irq_domain_hierarchical_is_msi_remap(h)) {
++			ret = false;
++			break;
++		}
++	}
++	mutex_unlock(&irq_domain_mutex);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(irq_domain_check_msi_remap);
++
++/**
+  * irq_set_default_host() - Set a "default" irq domain
+  * @domain: default domain pointer
+  *
+@@ -1420,6 +1445,20 @@ static void irq_domain_check_hierarchy(s
+ 	if (domain->ops->alloc)
+ 		domain->flags |= IRQ_DOMAIN_FLAG_HIERARCHY;
+ }
++
++/**
++ * irq_domain_hierarchical_is_msi_remap - Check if the domain or any
++ * parent has MSI remapping support
++ * @domain: domain pointer
++ */
++bool irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain)
++{
++	for (; domain; domain = domain->parent) {
++		if (irq_domain_is_msi_remap(domain))
++			return true;
++	}
++	return false;
++}
+ #else	/* CONFIG_IRQ_DOMAIN_HIERARCHY */
+ /**
+  * irq_domain_get_irq_data - Get irq_data associated with @virq and @domain
+--- a/kernel/irq/msi.c
++++ b/kernel/irq/msi.c
+@@ -272,8 +272,8 @@ struct irq_domain *msi_create_irq_domain
+ 	if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
+ 		msi_domain_update_chip_ops(info);
+ 
+-	return irq_domain_create_hierarchy(parent, 0, 0, fwnode,
+-					   &msi_domain_ops, info);
++	return irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0,
++					   fwnode, &msi_domain_ops, info);
+ }
+ 
+ int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
diff --git a/target/linux/layerscape/patches-4.9/812-mmc-layerscape-support.patch b/target/linux/layerscape/patches-4.9/812-mmc-layerscape-support.patch
new file mode 100644
index 000000000..4b3241737
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/812-mmc-layerscape-support.patch
@@ -0,0 +1,594 @@
+From 4215d5757595e7ec7ca146c2b901beb177f415d8 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:37:13 +0800
+Subject: [PATCH 24/30] mmc: layerscape support
+
+This is an integrated patch for layerscape mmc support.
+
+Adrian Hunter <adrian.hunter@intel.com>
+Jaehoon Chung <jh80.chung@samsung.com>
+Masahiro Yamada <yamada.masahiro@socionext.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/mmc/host/Kconfig          |   1 +
+ drivers/mmc/host/sdhci-esdhc.h    |  52 +++++---
+ drivers/mmc/host/sdhci-of-esdhc.c | 265 ++++++++++++++++++++++++++++++++++++--
+ drivers/mmc/host/sdhci.c          |  45 ++++---
+ drivers/mmc/host/sdhci.h          |   3 +
+ 5 files changed, 320 insertions(+), 46 deletions(-)
+
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -144,6 +144,7 @@ config MMC_SDHCI_OF_ESDHC
+ 	depends on MMC_SDHCI_PLTFM
+ 	depends on PPC || ARCH_MXC || ARCH_LAYERSCAPE
+ 	select MMC_SDHCI_IO_ACCESSORS
++	select FSL_GUTS
+ 	help
+ 	  This selects the Freescale eSDHC controller support.
+ 
+--- a/drivers/mmc/host/sdhci-esdhc.h
++++ b/drivers/mmc/host/sdhci-esdhc.h
+@@ -24,30 +24,46 @@
+ 				SDHCI_QUIRK_PIO_NEEDS_DELAY | \
+ 				SDHCI_QUIRK_NO_HISPD_BIT)
+ 
+-#define ESDHC_PROCTL		0x28
+-
+-#define ESDHC_SYSTEM_CONTROL	0x2c
+-#define ESDHC_CLOCK_MASK	0x0000fff0
+-#define ESDHC_PREDIV_SHIFT	8
+-#define ESDHC_DIVIDER_SHIFT	4
+-#define ESDHC_CLOCK_PEREN	0x00000004
+-#define ESDHC_CLOCK_HCKEN	0x00000002
+-#define ESDHC_CLOCK_IPGEN	0x00000001
+-
+ /* pltfm-specific */
+ #define ESDHC_HOST_CONTROL_LE	0x20
+ 
+ /*
+- * P2020 interpretation of the SDHCI_HOST_CONTROL register
++ * eSDHC register definition
+  */
+-#define ESDHC_CTRL_4BITBUS          (0x1 << 1)
+-#define ESDHC_CTRL_8BITBUS          (0x2 << 1)
+-#define ESDHC_CTRL_BUSWIDTH_MASK    (0x3 << 1)
+-
+-/* OF-specific */
+-#define ESDHC_DMA_SYSCTL	0x40c
+-#define ESDHC_DMA_SNOOP		0x00000040
+ 
+-#define ESDHC_HOST_CONTROL_RES	0x01
++/* Present State Register */
++#define ESDHC_PRSSTAT			0x24
++#define ESDHC_CLOCK_STABLE		0x00000008
++
++/* Protocol Control Register */
++#define ESDHC_PROCTL			0x28
++#define ESDHC_VOLT_SEL			0x00000400
++#define ESDHC_CTRL_4BITBUS		(0x1 << 1)
++#define ESDHC_CTRL_8BITBUS		(0x2 << 1)
++#define ESDHC_CTRL_BUSWIDTH_MASK	(0x3 << 1)
++#define ESDHC_HOST_CONTROL_RES		0x01
++
++/* System Control Register */
++#define ESDHC_SYSTEM_CONTROL		0x2c
++#define ESDHC_CLOCK_MASK		0x0000fff0
++#define ESDHC_PREDIV_SHIFT		8
++#define ESDHC_DIVIDER_SHIFT		4
++#define ESDHC_CLOCK_SDCLKEN		0x00000008
++#define ESDHC_CLOCK_PEREN		0x00000004
++#define ESDHC_CLOCK_HCKEN		0x00000002
++#define ESDHC_CLOCK_IPGEN		0x00000001
++
++/* Host Controller Capabilities Register 2 */
++#define ESDHC_CAPABILITIES_1		0x114
++
++/* Tuning Block Control Register */
++#define ESDHC_TBCTL			0x120
++#define ESDHC_TB_EN			0x00000004
++
++/* Control Register for DMA transfer */
++#define ESDHC_DMA_SYSCTL		0x40c
++#define ESDHC_PERIPHERAL_CLK_SEL	0x00080000
++#define ESDHC_FLUSH_ASYNC_FIFO		0x00040000
++#define ESDHC_DMA_SNOOP			0x00000040
+ 
+ #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
+--- a/drivers/mmc/host/sdhci-of-esdhc.c
++++ b/drivers/mmc/host/sdhci-of-esdhc.c
+@@ -16,8 +16,12 @@
+ #include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
++#include <linux/of_address.h>
+ #include <linux/delay.h>
+ #include <linux/module.h>
++#include <linux/sys_soc.h>
++#include <linux/clk.h>
++#include <linux/ktime.h>
+ #include <linux/mmc/host.h>
+ #include "sdhci-pltfm.h"
+ #include "sdhci-esdhc.h"
+@@ -28,8 +32,12 @@
+ struct sdhci_esdhc {
+ 	u8 vendor_ver;
+ 	u8 spec_ver;
++	bool quirk_incorrect_hostver;
++	unsigned int peripheral_clock;
+ };
+ 
++static void esdhc_clock_enable(struct sdhci_host *host, bool enable);
++
+ /**
+  * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
+  *		       to make it compatible with SD spec.
+@@ -80,6 +88,17 @@ static u32 esdhc_readl_fixup(struct sdhc
+ 		return ret;
+ 	}
+ 
++	/*
++	 * DTS properties of mmc host are used to enable each speed mode
++	 * according to soc and board capability. So clean up
++	 * SDR50/SDR104/DDR50 support bits here.
++	 */
++	if (spec_reg == SDHCI_CAPABILITIES_1) {
++		ret = value & (~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
++				 SDHCI_SUPPORT_DDR50));
++		return ret;
++	}
++
+ 	ret = value;
+ 	return ret;
+ }
+@@ -87,6 +106,8 @@ static u32 esdhc_readl_fixup(struct sdhc
+ static u16 esdhc_readw_fixup(struct sdhci_host *host,
+ 				     int spec_reg, u32 value)
+ {
++	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
+ 	u16 ret;
+ 	int shift = (spec_reg & 0x2) * 8;
+ 
+@@ -94,6 +115,12 @@ static u16 esdhc_readw_fixup(struct sdhc
+ 		ret = value & 0xffff;
+ 	else
+ 		ret = (value >> shift) & 0xffff;
++	/* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
++	 * vendor version and spec version information.
++	 */
++	if ((spec_reg == SDHCI_HOST_VERSION) &&
++	    (esdhc->quirk_incorrect_hostver))
++		ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
+ 	return ret;
+ }
+ 
+@@ -235,7 +262,11 @@ static u32 esdhc_be_readl(struct sdhci_h
+ 	u32 ret;
+ 	u32 value;
+ 
+-	value = ioread32be(host->ioaddr + reg);
++	if (reg == SDHCI_CAPABILITIES_1)
++		value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
++	else
++		value = ioread32be(host->ioaddr + reg);
++
+ 	ret = esdhc_readl_fixup(host, reg, value);
+ 
+ 	return ret;
+@@ -246,7 +277,11 @@ static u32 esdhc_le_readl(struct sdhci_h
+ 	u32 ret;
+ 	u32 value;
+ 
+-	value = ioread32(host->ioaddr + reg);
++	if (reg == SDHCI_CAPABILITIES_1)
++		value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
++	else
++		value = ioread32(host->ioaddr + reg);
++
+ 	ret = esdhc_readl_fixup(host, reg, value);
+ 
+ 	return ret;
+@@ -404,15 +439,25 @@ static int esdhc_of_enable_dma(struct sd
+ static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
+ {
+ 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
+ 
+-	return pltfm_host->clock;
++	if (esdhc->peripheral_clock)
++		return esdhc->peripheral_clock;
++	else
++		return pltfm_host->clock;
+ }
+ 
+ static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
+ {
+ 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
++	unsigned int clock;
+ 
+-	return pltfm_host->clock / 256 / 16;
++	if (esdhc->peripheral_clock)
++		clock = esdhc->peripheral_clock;
++	else
++		clock = pltfm_host->clock;
++	return clock / 256 / 16;
+ }
+ 
+ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
+@@ -421,12 +466,15 @@ static void esdhc_of_set_clock(struct sd
+ 	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
+ 	int pre_div = 1;
+ 	int div = 1;
++	ktime_t timeout;
+ 	u32 temp;
+ 
+ 	host->mmc->actual_clock = 0;
+ 
+-	if (clock == 0)
++	if (clock == 0) {
++		esdhc_clock_enable(host, false);
+ 		return;
++	}
+ 
+ 	/* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
+ 	if (esdhc->vendor_ver < VENDOR_V_23)
+@@ -454,9 +502,15 @@ static void esdhc_of_set_clock(struct sd
+ 			clock -= 5000000;
+ 	}
+ 
++	/* Workaround to reduce the clock frequency for ls1021a esdhc */
++	if (of_find_compatible_node(NULL, NULL, "fsl,ls1021a-esdhc")) {
++		if (clock == 50000000)
++			clock = 46500000;
++	}
++
+ 	temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
+-	temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
+-		| ESDHC_CLOCK_MASK);
++	temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
++		  ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
+ 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
+ 
+ 	while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
+@@ -476,7 +530,20 @@ static void esdhc_of_set_clock(struct sd
+ 		| (div << ESDHC_DIVIDER_SHIFT)
+ 		| (pre_div << ESDHC_PREDIV_SHIFT));
+ 	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
+-	mdelay(1);
++
++	/* Wait max 20 ms */
++	timeout = ktime_add_ms(ktime_get(), 20);
++	while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) {
++		if (ktime_after(ktime_get(), timeout)) {
++			pr_err("%s: Internal clock never stabilised.\n",
++				mmc_hostname(host->mmc));
++			return;
++		}
++		udelay(10);
++	}
++
++	temp |= ESDHC_CLOCK_SDCLKEN;
++	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
+ }
+ 
+ static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
+@@ -501,12 +568,136 @@ static void esdhc_pltfm_set_bus_width(st
+ 	sdhci_writel(host, ctrl, ESDHC_PROCTL);
+ }
+ 
++static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
++{
++	u32 val;
++	ktime_t timeout;
++
++	val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
++
++	if (enable)
++		val |= ESDHC_CLOCK_SDCLKEN;
++	else
++		val &= ~ESDHC_CLOCK_SDCLKEN;
++
++	sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
++
++	/* Wait max 20 ms */
++	timeout = ktime_add_ms(ktime_get(), 20);
++	val = ESDHC_CLOCK_STABLE;
++	while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) {
++		if (ktime_after(ktime_get(), timeout)) {
++			pr_err("%s: Internal clock never stabilised.\n",
++				mmc_hostname(host->mmc));
++			break;
++		}
++		udelay(10);
++	}
++}
++
+ static void esdhc_reset(struct sdhci_host *host, u8 mask)
+ {
++	u32 val;
++
+ 	sdhci_reset(host, mask);
+ 
+ 	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ 	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
++
++	if (mask & SDHCI_RESET_ALL) {
++		val = sdhci_readl(host, ESDHC_TBCTL);
++		val &= ~ESDHC_TB_EN;
++		sdhci_writel(host, val, ESDHC_TBCTL);
++	}
++}
++
++/* The SCFG, Supplemental Configuration Unit, provides SoC specific
++ * configuration and status registers for the device. There is a
++ * SDHC IO VSEL control register on SCFG for some platforms. It's
++ * used to support SDHC IO voltage switching.
++ */
++static const struct of_device_id scfg_device_ids[] = {
++	{ .compatible = "fsl,t1040-scfg", },
++	{ .compatible = "fsl,ls1012a-scfg", },
++	{ .compatible = "fsl,ls1046a-scfg", },
++	{}
++};
++
++/* SDHC IO VSEL control register definition */
++#define SCFG_SDHCIOVSELCR	0x408
++#define SDHCIOVSELCR_TGLEN	0x80000000
++#define SDHCIOVSELCR_VSELVAL	0x60000000
++#define SDHCIOVSELCR_SDHC_VS	0x00000001
++
++static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
++				       struct mmc_ios *ios)
++{
++	struct sdhci_host *host = mmc_priv(mmc);
++	struct device_node *scfg_node;
++	void __iomem *scfg_base = NULL;
++	u32 sdhciovselcr;
++	u32 val;
++
++	/*
++	 * Signal Voltage Switching is only applicable for Host Controllers
++	 * v3.00 and above.
++	 */
++	if (host->version < SDHCI_SPEC_300)
++		return 0;
++
++	val = sdhci_readl(host, ESDHC_PROCTL);
++
++	switch (ios->signal_voltage) {
++	case MMC_SIGNAL_VOLTAGE_330:
++		val &= ~ESDHC_VOLT_SEL;
++		sdhci_writel(host, val, ESDHC_PROCTL);
++		return 0;
++	case MMC_SIGNAL_VOLTAGE_180:
++		scfg_node = of_find_matching_node(NULL, scfg_device_ids);
++		if (scfg_node)
++			scfg_base = of_iomap(scfg_node, 0);
++		if (scfg_base) {
++			sdhciovselcr = SDHCIOVSELCR_TGLEN |
++				       SDHCIOVSELCR_VSELVAL;
++			iowrite32be(sdhciovselcr,
++				scfg_base + SCFG_SDHCIOVSELCR);
++
++			val |= ESDHC_VOLT_SEL;
++			sdhci_writel(host, val, ESDHC_PROCTL);
++			mdelay(5);
++
++			sdhciovselcr = SDHCIOVSELCR_TGLEN |
++				       SDHCIOVSELCR_SDHC_VS;
++			iowrite32be(sdhciovselcr,
++				scfg_base + SCFG_SDHCIOVSELCR);
++			iounmap(scfg_base);
++		} else {
++			val |= ESDHC_VOLT_SEL;
++			sdhci_writel(host, val, ESDHC_PROCTL);
++		}
++		return 0;
++	default:
++		return 0;
++	}
++}
++
++static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
++{
++	struct sdhci_host *host = mmc_priv(mmc);
++	u32 val;
++
++	/* Use tuning block for tuning procedure */
++	esdhc_clock_enable(host, false);
++	val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
++	val |= ESDHC_FLUSH_ASYNC_FIFO;
++	sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
++
++	val = sdhci_readl(host, ESDHC_TBCTL);
++	val |= ESDHC_TB_EN;
++	sdhci_writel(host, val, ESDHC_TBCTL);
++	esdhc_clock_enable(host, true);
++
++	return sdhci_execute_tuning(mmc, opcode);
+ }
+ 
+ #ifdef CONFIG_PM_SLEEP
+@@ -589,10 +780,19 @@ static const struct sdhci_pltfm_data sdh
+ 	.ops = &sdhci_esdhc_le_ops,
+ };
+ 
++static struct soc_device_attribute soc_incorrect_hostver[] = {
++	{ .family = "QorIQ T4240", .revision = "1.0", },
++	{ .family = "QorIQ T4240", .revision = "2.0", },
++	{ },
++};
++
+ static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
+ {
+ 	struct sdhci_pltfm_host *pltfm_host;
+ 	struct sdhci_esdhc *esdhc;
++	struct device_node *np;
++	struct clk *clk;
++	u32 val;
+ 	u16 host_ver;
+ 
+ 	pltfm_host = sdhci_priv(host);
+@@ -602,6 +802,36 @@ static void esdhc_init(struct platform_d
+ 	esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
+ 			     SDHCI_VENDOR_VER_SHIFT;
+ 	esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
++	if (soc_device_match(soc_incorrect_hostver))
++		esdhc->quirk_incorrect_hostver = true;
++	else
++		esdhc->quirk_incorrect_hostver = false;
++
++	np = pdev->dev.of_node;
++	clk = of_clk_get(np, 0);
++	if (!IS_ERR(clk)) {
++		/*
++		 * esdhc->peripheral_clock would be assigned with a value
++		 * which is eSDHC base clock when use periperal clock.
++		 * For ls1046a, the clock value got by common clk API is
++		 * peripheral clock while the eSDHC base clock is 1/2
++		 * peripheral clock.
++		 */
++		if (of_device_is_compatible(np, "fsl,ls1046a-esdhc"))
++			esdhc->peripheral_clock = clk_get_rate(clk) / 2;
++		else
++			esdhc->peripheral_clock = clk_get_rate(clk);
++
++		clk_put(clk);
++	}
++
++	if (esdhc->peripheral_clock) {
++		esdhc_clock_enable(host, false);
++		val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
++		val |= ESDHC_PERIPHERAL_CLK_SEL;
++		sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
++		esdhc_clock_enable(host, true);
++	}
+ }
+ 
+ static int sdhci_esdhc_probe(struct platform_device *pdev)
+@@ -624,6 +854,11 @@ static int sdhci_esdhc_probe(struct plat
+ 	if (IS_ERR(host))
+ 		return PTR_ERR(host);
+ 
++	host->mmc_host_ops.start_signal_voltage_switch =
++		esdhc_signal_voltage_switch;
++	host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
++	host->tuning_delay = 1;
++
+ 	esdhc_init(pdev, host);
+ 
+ 	sdhci_get_of_property(pdev);
+--- a/drivers/mmc/host/sdhci.c
++++ b/drivers/mmc/host/sdhci.c
+@@ -1631,26 +1631,24 @@ static void sdhci_set_ios(struct mmc_hos
+ 
+ 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ 
+-	if ((ios->timing == MMC_TIMING_SD_HS ||
+-	     ios->timing == MMC_TIMING_MMC_HS)
+-	    && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
+-		ctrl |= SDHCI_CTRL_HISPD;
+-	else
+-		ctrl &= ~SDHCI_CTRL_HISPD;
++	if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
++		if ((ios->timing == MMC_TIMING_SD_HS ||
++		     ios->timing == MMC_TIMING_MMC_HS ||
++		     ios->timing == MMC_TIMING_MMC_HS400 ||
++		     ios->timing == MMC_TIMING_MMC_HS200 ||
++		     ios->timing == MMC_TIMING_MMC_DDR52 ||
++		     ios->timing == MMC_TIMING_UHS_SDR50 ||
++		     ios->timing == MMC_TIMING_UHS_SDR104 ||
++		     ios->timing == MMC_TIMING_UHS_DDR50 ||
++		     ios->timing == MMC_TIMING_UHS_SDR25))
++			ctrl |= SDHCI_CTRL_HISPD;
++		else
++			ctrl &= ~SDHCI_CTRL_HISPD;
++	}
+ 
+ 	if (host->version >= SDHCI_SPEC_300) {
+ 		u16 clk, ctrl_2;
+ 
+-		/* In case of UHS-I modes, set High Speed Enable */
+-		if ((ios->timing == MMC_TIMING_MMC_HS400) ||
+-		    (ios->timing == MMC_TIMING_MMC_HS200) ||
+-		    (ios->timing == MMC_TIMING_MMC_DDR52) ||
+-		    (ios->timing == MMC_TIMING_UHS_SDR50) ||
+-		    (ios->timing == MMC_TIMING_UHS_SDR104) ||
+-		    (ios->timing == MMC_TIMING_UHS_DDR50) ||
+-		    (ios->timing == MMC_TIMING_UHS_SDR25))
+-			ctrl |= SDHCI_CTRL_HISPD;
+-
+ 		if (!host->preset_enabled) {
+ 			sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ 			/*
+@@ -1963,7 +1961,7 @@ static int sdhci_prepare_hs400_tuning(st
+ 	return 0;
+ }
+ 
+-static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
++int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+ {
+ 	struct sdhci_host *host = mmc_priv(mmc);
+ 	u16 ctrl;
+@@ -2022,6 +2020,9 @@ static int sdhci_execute_tuning(struct m
+ 		return err;
+ 	}
+ 
++	if (host->tuning_delay < 0)
++	host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
++
+ 	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ 	ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ 	if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
+@@ -2134,9 +2135,10 @@ static int sdhci_execute_tuning(struct m
+ 
+ 		ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ 
+-		/* eMMC spec does not require a delay between tuning cycles */
+-		if (opcode == MMC_SEND_TUNING_BLOCK)
+-			mdelay(1);
++		/* Spec does not require a delay between tuning cycles */
++		if (host->tuning_delay > 0)
++		mdelay(host->tuning_delay);
++
+ 	} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+ 
+ 	/*
+@@ -2172,6 +2174,7 @@ out_unlock:
+ 	spin_unlock_irqrestore(&host->lock, flags);
+ 	return err;
+ }
++EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
+ 
+ static int sdhci_select_drive_strength(struct mmc_card *card,
+ 				       unsigned int max_dtr, int host_drv,
+@@ -3004,6 +3007,8 @@ struct sdhci_host *sdhci_alloc_host(stru
+ 
+ 	host->flags = SDHCI_SIGNALING_330;
+ 
++	host->tuning_delay = -1;
++
+ 	return host;
+ }
+ 
+--- a/drivers/mmc/host/sdhci.h
++++ b/drivers/mmc/host/sdhci.h
+@@ -524,6 +524,8 @@ struct sdhci_host {
+ #define SDHCI_TUNING_MODE_1	0
+ #define SDHCI_TUNING_MODE_2	1
+ #define SDHCI_TUNING_MODE_3	2
++	/* Delay (ms) between tuning commands */
++	int			tuning_delay;
+ 
+ 	unsigned long private[0] ____cacheline_aligned;
+ };
+@@ -689,6 +691,7 @@ void sdhci_set_power_noreg(struct sdhci_
+ void sdhci_set_bus_width(struct sdhci_host *host, int width);
+ void sdhci_reset(struct sdhci_host *host, u8 mask);
+ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
++int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
+ 
+ #ifdef CONFIG_PM
+ extern int sdhci_suspend_host(struct sdhci_host *host);
diff --git a/target/linux/layerscape/patches-4.14/805-qe-support-layerscape.patch b/target/linux/layerscape/patches-4.9/813-qe-support-layerscape.patch
similarity index 95%
rename from target/linux/layerscape/patches-4.14/805-qe-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/813-qe-support-layerscape.patch
index 141677c08..1dfa46e83 100644
--- a/target/linux/layerscape/patches-4.14/805-qe-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/813-qe-support-layerscape.patch
@@ -1,25 +1,27 @@
-From cfa7e6ed5a6ba529097ae8a50ed2c8fa12b4cad0 Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:27:13 +0800
-Subject: [PATCH 22/40] qe: support layerscape
-This is an integrated patch of qe for layerscape
+From 2ab544f7e943c63c300933d34815e78451cc0c26 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:37:56 +0800
+Subject: [PATCH 25/30] qe: support layerscape
 
-Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+This is an integrated patch for layerscape qe support.
+
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- .../fsl/qe/qe_ic.c => irqchip/irq-qeic.c}     | 389 +++++++++++-------
- drivers/soc/fsl/qe/Kconfig                    |   2 +-
- drivers/soc/fsl/qe/Makefile                   |   2 +-
- drivers/soc/fsl/qe/qe.c                       |  78 ++--
- drivers/soc/fsl/qe/qe_ic.h                    | 103 -----
- drivers/soc/fsl/qe/qe_io.c                    |  42 +-
- drivers/soc/fsl/qe/qe_tdm.c                   |   8 +-
- drivers/soc/fsl/qe/ucc.c                      |  10 +-
- drivers/soc/fsl/qe/ucc_fast.c                 |  74 ++--
- drivers/tty/serial/ucc_uart.c                 |   1 +
- include/soc/fsl/qe/qe.h                       |   1 -
- include/soc/fsl/qe/qe_ic.h                    | 139 -------
- 12 files changed, 357 insertions(+), 492 deletions(-)
+ drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 389 +++++++++++++--------
+ drivers/net/wan/fsl_ucc_hdlc.c                     |   4 +-
+ drivers/soc/fsl/qe/Kconfig                         |   2 +-
+ drivers/soc/fsl/qe/Makefile                        |   2 +-
+ drivers/soc/fsl/qe/qe.c                            |  80 +++--
+ drivers/soc/fsl/qe/qe_ic.h                         | 103 ------
+ drivers/soc/fsl/qe/qe_io.c                         |  42 +--
+ drivers/soc/fsl/qe/qe_tdm.c                        |   8 +-
+ drivers/soc/fsl/qe/ucc.c                           |  10 +-
+ drivers/soc/fsl/qe/ucc_fast.c                      |  74 ++--
+ drivers/tty/serial/ucc_uart.c                      |   1 +
+ include/soc/fsl/qe/qe.h                            |   1 -
+ include/soc/fsl/qe/qe_ic.h                         | 139 --------
+ 13 files changed, 359 insertions(+), 496 deletions(-)
  rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (54%)
  delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
  delete mode 100644 include/soc/fsl/qe/qe_ic.h
@@ -1147,6 +1149,27 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +}
 +
 +IRQCHIP_DECLARE(qeic, "fsl,qe-ic", init_qe_ic);
+--- a/drivers/net/wan/fsl_ucc_hdlc.c
++++ b/drivers/net/wan/fsl_ucc_hdlc.c
+@@ -381,8 +381,8 @@ static netdev_tx_t ucc_hdlc_tx(struct sk
+ 	/* set bd status and length */
+ 	bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
+ 
+-	iowrite16be(bd_status, &bd->status);
+ 	iowrite16be(skb->len, &bd->length);
++	iowrite16be(bd_status, &bd->status);
+ 
+ 	/* Move to next BD in the ring */
+ 	if (!(bd_status & T_W_S))
+@@ -457,7 +457,7 @@ static int hdlc_rx_done(struct ucc_hdlc_
+ 	struct sk_buff *skb = NULL;
+ 	hdlc_device *hdlc = dev_to_hdlc(dev);
+ 	struct qe_bd *bd;
+-	u32 bd_status;
++	u16 bd_status;
+ 	u16 length, howmany = 0;
+ 	u8 *bdbuffer;
+ 	int i;
 --- a/drivers/soc/fsl/qe/Kconfig
 +++ b/drivers/soc/fsl/qe/Kconfig
 @@ -4,7 +4,7 @@
@@ -1160,7 +1183,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	help
 --- a/drivers/soc/fsl/qe/Makefile
 +++ b/drivers/soc/fsl/qe/Makefile
-@@ -2,7 +2,7 @@
+@@ -1,7 +1,7 @@
  #
  # Makefile for the linux ppc-specific parts of QE
  #
@@ -1180,7 +1203,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  static void qe_snums_init(void);
  static int qe_sdma_init(void);
-@@ -107,15 +105,27 @@ void qe_reset(void)
+@@ -109,15 +107,27 @@ void qe_reset(void)
  		panic("sdma init failed!");
  }
  
@@ -1210,7 +1233,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	} else {
  		if (cmd == QE_ASSIGN_PAGE) {
  			/* Here device is the SNUM, not sub-block */
-@@ -132,20 +142,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8
+@@ -134,20 +144,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8
  				mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
  		}
  
@@ -1244,16 +1267,18 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  }
  EXPORT_SYMBOL(qe_issue_cmd);
  
-@@ -170,6 +186,8 @@ unsigned int qe_get_brg_clk(void)
- 	int size;
- 	const u32 *prop;
- 	unsigned int mod;
+@@ -169,8 +185,8 @@ static unsigned int brg_clk = 0;
+ unsigned int qe_get_brg_clk(void)
+ {
+ 	struct device_node *qe;
+-	int size;
+-	const u32 *prop;
 +	u32 val;
 +	int ret;
+ 	unsigned int mod;
  
  	if (brg_clk)
- 		return brg_clk;
-@@ -181,9 +199,9 @@ unsigned int qe_get_brg_clk(void)
+@@ -183,9 +199,9 @@ unsigned int qe_get_brg_clk(void)
  			return brg_clk;
  	}
  
@@ -1266,7 +1291,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  	of_node_put(qe);
  
-@@ -236,7 +254,7 @@ int qe_setbrg(enum qe_clock brg, unsigne
+@@ -234,7 +250,7 @@ int qe_setbrg(enum qe_clock brg, unsigne
  	tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
  		QE_BRGC_ENABLE | div16;
  
@@ -1275,7 +1300,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  	return 0;
  }
-@@ -370,9 +388,9 @@ static int qe_sdma_init(void)
+@@ -368,9 +384,9 @@ static int qe_sdma_init(void)
  			return -ENOMEM;
  	}
  
@@ -1288,7 +1313,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  	return 0;
  }
-@@ -410,14 +428,14 @@ static void qe_upload_microcode(const vo
+@@ -408,14 +424,14 @@ static void qe_upload_microcode(const vo
  			"uploading microcode '%s'\n", ucode->id);
  
  	/* Use auto-increment */
@@ -1307,7 +1332,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  }
  
  /*
-@@ -502,7 +520,7 @@ int qe_upload_firmware(const struct qe_f
+@@ -500,7 +516,7 @@ int qe_upload_firmware(const struct qe_f
  	 * If the microcode calls for it, split the I-RAM.
  	 */
  	if (!firmware->split)
@@ -1316,7 +1341,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  	if (firmware->soc.model)
  		printk(KERN_INFO
-@@ -536,11 +554,11 @@ int qe_upload_firmware(const struct qe_f
+@@ -534,11 +550,11 @@ int qe_upload_firmware(const struct qe_f
  			u32 trap = be32_to_cpu(ucode->traps[j]);
  
  			if (trap)
@@ -1330,7 +1355,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	}
  
  	qe_firmware_uploaded = 1;
-@@ -659,9 +677,9 @@ EXPORT_SYMBOL(qe_get_num_of_risc);
+@@ -657,9 +673,9 @@ EXPORT_SYMBOL(qe_get_num_of_risc);
  unsigned int qe_get_num_of_snums(void)
  {
  	struct device_node *qe;
@@ -1342,7 +1367,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  	num_of_snums = 28; /* The default number of snum for threads is 28 */
  	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
-@@ -675,9 +693,9 @@ unsigned int qe_get_num_of_snums(void)
+@@ -673,9 +689,9 @@ unsigned int qe_get_num_of_snums(void)
  			return num_of_snums;
  	}
  
@@ -1557,7 +1582,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  }
 --- a/drivers/soc/fsl/qe/qe_tdm.c
 +++ b/drivers/soc/fsl/qe/qe_tdm.c
-@@ -228,10 +228,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm,
+@@ -227,10 +227,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm,
  				    &siram[siram_entry_id * 32 + 0x200 +  i]);
  	}
  
diff --git a/target/linux/layerscape/patches-4.14/806-rtc-support-layerscape.patch b/target/linux/layerscape/patches-4.9/814-rtc-support-layerscape.patch
similarity index 83%
rename from target/linux/layerscape/patches-4.14/806-rtc-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/814-rtc-support-layerscape.patch
index b7535100b..9510a524d 100644
--- a/target/linux/layerscape/patches-4.14/806-rtc-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/814-rtc-support-layerscape.patch
@@ -1,98 +1,20 @@
-From f8d89482075e2a4a62fc5cbacf6bea6baf4dc65f Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:27:31 +0800
-Subject: [PATCH 23/40] rtc: support layerscape
-This is an integrated patch of rtc for layerscape
+From bda12381598c3df43f4e60362a8cd4af58b7f5b0 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:38:54 +0800
+Subject: [PATCH 26/30] rtc: support layerscape
+
+This is an integrated patch for layerscape rtc support.
 
-Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- .../devicetree/bindings/rtc/nxp,pcf85263.txt  |  42 ++
- drivers/rtc/Kconfig                           |   8 +
- drivers/rtc/Makefile                          |   1 +
- drivers/rtc/rtc-pcf85263.c                    | 664 ++++++++++++++++++
- include/dt-bindings/rtc/nxp,pcf85263.h        |  14 +
- 5 files changed, 729 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf85263.txt
+ drivers/rtc/rtc-pcf85263.c | 665 +++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 665 insertions(+)
  create mode 100644 drivers/rtc/rtc-pcf85263.c
- create mode 100644 include/dt-bindings/rtc/nxp,pcf85263.h
 
 --- /dev/null
-+++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85263.txt
-@@ -0,0 +1,42 @@
-+NXP PCF85263 I2C Real Time Clock
-+
-+Required properties:
-+- compatible: must be: "nxp,rtc-pcf85263"
-+- reg: must be the I2C address
-+
-+Optional properties:
-+- interrupt-names: Which interrupt signal is used must be "INTA" or "INTB"
-+    Defaults to "INTA"
-+
-+- quartz-load-capacitance: The internal capacitor to select for the quartz:
-+	PCF85263_QUARTZCAP_7pF		[0]
-+	PCF85263_QUARTZCAP_6pF		[1]
-+	PCF85263_QUARTZCAP_12p5pF	[2] DEFAULT
-+
-+- quartz-drive-strength: Drive strength for the quartz:
-+	PCF85263_QUARTZDRIVE_NORMAL	[0] DEFAULT
-+	PCF85263_QUARTZDRIVE_LOW	[1]
-+	PCF85263_QUARTZDRIVE_HIGH	[2]
-+
-+- quartz-low-jitter: Boolean property, if present enables low jitter mode
-+which
-+    reduces jitter at the cost of increased power consumption.
-+
-+- wakeup-source: mark the chip as a wakeup source, independently of
-+    the availability of an IRQ line connected to the SoC.
-+    This is useful if the IRQ line is connected to a PMIC or other circuit
-+    that can power up the device rather than to a normal SOC interrupt.
-+
-+Example:
-+
-+rtc@51 {
-+	compatible = "nxp,pcf85263";
-+	reg = <0x51>;
-+
-+	interrupt-parent = <&gpio4>;
-+	interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
-+	interrupt-names = "INTB";
-+
-+	quartz-load-capacitance = <PCF85263_QUARTZCAP_12p5pF>;
-+	quartz-drive-strength = <PCF85263_QUARTZDRIVE_LOW>;
-+};
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -433,6 +433,14 @@ config RTC_DRV_PCF85063
- 	  This driver can also be built as a module. If so, the module
- 	  will be called rtc-pcf85063.
- 
-+config RTC_DRV_PCF85263
-+	tristate "NXP PCF85263"
-+	help
-+	  If you say yes here you get support for the PCF85263 RTC chip
-+
-+	  This driver can also be built as a module. If so, the module
-+	  will be called rtc-pcf85263.
-+
- config RTC_DRV_PCF8563
- 	tristate "Philips PCF8563/Epson RTC8564"
- 	help
---- a/drivers/rtc/Makefile
-+++ b/drivers/rtc/Makefile
-@@ -115,6 +115,7 @@ obj-$(CONFIG_RTC_DRV_PCF2127)	+= rtc-pcf
- obj-$(CONFIG_RTC_DRV_PCF50633)	+= rtc-pcf50633.o
- obj-$(CONFIG_RTC_DRV_PCF85063)	+= rtc-pcf85063.o
- obj-$(CONFIG_RTC_DRV_PCF8523)	+= rtc-pcf8523.o
-+obj-$(CONFIG_RTC_DRV_PCF85263)	+= rtc-pcf85263.o
- obj-$(CONFIG_RTC_DRV_PCF8563)	+= rtc-pcf8563.o
- obj-$(CONFIG_RTC_DRV_PCF8583)	+= rtc-pcf8583.o
- obj-$(CONFIG_RTC_DRV_PIC32)	+= rtc-pic32.o
---- /dev/null
 +++ b/drivers/rtc/rtc-pcf85263.c
-@@ -0,0 +1,664 @@
+@@ -0,0 +1,665 @@
 +/*
 + * rtc-pcf85263 Driver for the NXP PCF85263 RTC
 + * Copyright 2016 Parkeon
@@ -757,20 +679,4 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +MODULE_AUTHOR("Martin Fuzzey <mfuzzey@parkeon.com>");
 +MODULE_DESCRIPTION("PCF85263 RTC Driver");
 +MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/include/dt-bindings/rtc/nxp,pcf85263.h
-@@ -0,0 +1,14 @@
-+#ifndef _DT_BINDINGS_RTC_NXP_PCF85263_H
-+#define _DT_BINDINGS_RTC_NXP_PCF85263_H
 +
-+/* Quartz capacitance */
-+#define PCF85263_QUARTZCAP_7pF		0
-+#define PCF85263_QUARTZCAP_6pF		1
-+#define PCF85263_QUARTZCAP_12p5pF	2
-+
-+/* Quartz drive strength */
-+#define PCF85263_QUARTZDRIVE_NORMAL	0
-+#define PCF85263_QUARTZDRIVE_LOW	1
-+#define PCF85263_QUARTZDRIVE_HIGH	2
-+
-+#endif /* _DT_BINDINGS_RTC_NXP_PCF85263_H */
diff --git a/target/linux/layerscape/patches-4.9/815-spi-support-layerscape.patch b/target/linux/layerscape/patches-4.9/815-spi-support-layerscape.patch
new file mode 100644
index 000000000..b798a366b
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/815-spi-support-layerscape.patch
@@ -0,0 +1,427 @@
+From 027b679f248f15dea36c6cd6782d6643e2151057 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:39:43 +0800
+Subject: [PATCH 27/30] spi: support layerscape
+
+This is an integrated patch for layerscape dspi support.
+
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/spi/spi-fsl-dspi.c | 309 ++++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 304 insertions(+), 5 deletions(-)
+
+--- a/drivers/spi/spi-fsl-dspi.c
++++ b/drivers/spi/spi-fsl-dspi.c
+@@ -15,6 +15,8 @@
+ 
+ #include <linux/clk.h>
+ #include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
+ #include <linux/err.h>
+ #include <linux/errno.h>
+ #include <linux/interrupt.h>
+@@ -40,6 +42,7 @@
+ #define TRAN_STATE_WORD_ODD_NUM	0x04
+ 
+ #define DSPI_FIFO_SIZE			4
++#define DSPI_DMA_BUFSIZE		(DSPI_FIFO_SIZE * 1024)
+ 
+ #define SPI_MCR		0x00
+ #define SPI_MCR_MASTER		(1 << 31)
+@@ -72,6 +75,11 @@
+ #define SPI_SR_TCFQF		0x80000000
+ #define SPI_SR_CLEAR		0xdaad0000
+ 
++#define SPI_RSER_TFFFE		BIT(25)
++#define SPI_RSER_TFFFD		BIT(24)
++#define SPI_RSER_RFDFE		BIT(17)
++#define SPI_RSER_RFDFD		BIT(16)
++
+ #define SPI_RSER		0x30
+ #define SPI_RSER_EOQFE		0x10000000
+ #define SPI_RSER_TCFQE		0x80000000
+@@ -109,6 +117,8 @@
+ 
+ #define SPI_TCR_TCNT_MAX	0x10000
+ 
++#define DMA_COMPLETION_TIMEOUT	msecs_to_jiffies(3000)
++
+ struct chip_data {
+ 	u32 mcr_val;
+ 	u32 ctar_val;
+@@ -118,6 +128,7 @@ struct chip_data {
+ enum dspi_trans_mode {
+ 	DSPI_EOQ_MODE = 0,
+ 	DSPI_TCFQ_MODE,
++	DSPI_DMA_MODE,
+ };
+ 
+ struct fsl_dspi_devtype_data {
+@@ -126,7 +137,7 @@ struct fsl_dspi_devtype_data {
+ };
+ 
+ static const struct fsl_dspi_devtype_data vf610_data = {
+-	.trans_mode = DSPI_EOQ_MODE,
++	.trans_mode = DSPI_DMA_MODE,
+ 	.max_clock_factor = 2,
+ };
+ 
+@@ -140,6 +151,23 @@ static const struct fsl_dspi_devtype_dat
+ 	.max_clock_factor = 8,
+ };
+ 
++struct fsl_dspi_dma {
++	/* Length of transfer in words of DSPI_FIFO_SIZE */
++	u32 curr_xfer_len;
++
++	u32 *tx_dma_buf;
++	struct dma_chan *chan_tx;
++	dma_addr_t tx_dma_phys;
++	struct completion cmd_tx_complete;
++	struct dma_async_tx_descriptor *tx_desc;
++
++	u32 *rx_dma_buf;
++	struct dma_chan *chan_rx;
++	dma_addr_t rx_dma_phys;
++	struct completion cmd_rx_complete;
++	struct dma_async_tx_descriptor *rx_desc;
++};
++
+ struct fsl_dspi {
+ 	struct spi_master	*master;
+ 	struct platform_device	*pdev;
+@@ -166,8 +194,11 @@ struct fsl_dspi {
+ 	u32			waitflags;
+ 
+ 	u32			spi_tcnt;
++	struct fsl_dspi_dma	*dma;
+ };
+ 
++static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word);
++
+ static inline int is_double_byte_mode(struct fsl_dspi *dspi)
+ {
+ 	unsigned int val;
+@@ -177,6 +208,255 @@ static inline int is_double_byte_mode(st
+ 	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
+ }
+ 
++static void dspi_tx_dma_callback(void *arg)
++{
++	struct fsl_dspi *dspi = arg;
++	struct fsl_dspi_dma *dma = dspi->dma;
++
++	complete(&dma->cmd_tx_complete);
++}
++
++static void dspi_rx_dma_callback(void *arg)
++{
++	struct fsl_dspi *dspi = arg;
++	struct fsl_dspi_dma *dma = dspi->dma;
++	int rx_word;
++	int i;
++	u16 d;
++
++	rx_word = is_double_byte_mode(dspi);
++
++	if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) {
++		for (i = 0; i < dma->curr_xfer_len; i++) {
++			d = dspi->dma->rx_dma_buf[i];
++			rx_word ? (*(u16 *)dspi->rx = d) :
++						(*(u8 *)dspi->rx = d);
++			dspi->rx += rx_word + 1;
++		}
++	}
++
++	complete(&dma->cmd_rx_complete);
++}
++
++static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
++{
++	struct fsl_dspi_dma *dma = dspi->dma;
++	struct device *dev = &dspi->pdev->dev;
++	int time_left;
++	int tx_word;
++	int i;
++
++	tx_word = is_double_byte_mode(dspi);
++
++	for (i = 0; i < dma->curr_xfer_len; i++) {
++		dspi->dma->tx_dma_buf[i] = dspi_data_to_pushr(dspi, tx_word);
++		if ((dspi->cs_change) && (!dspi->len))
++			dspi->dma->tx_dma_buf[i] &= ~SPI_PUSHR_CONT;
++	}
++
++	dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
++					dma->tx_dma_phys,
++					dma->curr_xfer_len *
++					DMA_SLAVE_BUSWIDTH_4_BYTES,
++					DMA_MEM_TO_DEV,
++					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	if (!dma->tx_desc) {
++		dev_err(dev, "Not able to get desc for DMA xfer\n");
++		return -EIO;
++	}
++
++	dma->tx_desc->callback = dspi_tx_dma_callback;
++	dma->tx_desc->callback_param = dspi;
++	if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
++		dev_err(dev, "DMA submit failed\n");
++		return -EINVAL;
++	}
++
++	dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
++					dma->rx_dma_phys,
++					dma->curr_xfer_len *
++					DMA_SLAVE_BUSWIDTH_4_BYTES,
++					DMA_DEV_TO_MEM,
++					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++	if (!dma->rx_desc) {
++		dev_err(dev, "Not able to get desc for DMA xfer\n");
++		return -EIO;
++	}
++
++	dma->rx_desc->callback = dspi_rx_dma_callback;
++	dma->rx_desc->callback_param = dspi;
++	if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
++		dev_err(dev, "DMA submit failed\n");
++		return -EINVAL;
++	}
++
++	reinit_completion(&dspi->dma->cmd_rx_complete);
++	reinit_completion(&dspi->dma->cmd_tx_complete);
++
++	dma_async_issue_pending(dma->chan_rx);
++	dma_async_issue_pending(dma->chan_tx);
++
++	time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
++					DMA_COMPLETION_TIMEOUT);
++	if (time_left == 0) {
++		dev_err(dev, "DMA tx timeout\n");
++		dmaengine_terminate_all(dma->chan_tx);
++		dmaengine_terminate_all(dma->chan_rx);
++		return -ETIMEDOUT;
++	}
++
++	time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
++					DMA_COMPLETION_TIMEOUT);
++	if (time_left == 0) {
++		dev_err(dev, "DMA rx timeout\n");
++		dmaengine_terminate_all(dma->chan_tx);
++		dmaengine_terminate_all(dma->chan_rx);
++		return -ETIMEDOUT;
++	}
++
++	return 0;
++}
++
++static int dspi_dma_xfer(struct fsl_dspi *dspi)
++{
++	struct fsl_dspi_dma *dma = dspi->dma;
++	struct device *dev = &dspi->pdev->dev;
++	int curr_remaining_bytes;
++	int bytes_per_buffer;
++	int word = 1;
++	int ret = 0;
++
++	if (is_double_byte_mode(dspi))
++		word = 2;
++	curr_remaining_bytes = dspi->len;
++	bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
++	while (curr_remaining_bytes) {
++		/* Check if current transfer fits the DMA buffer */
++		dma->curr_xfer_len = curr_remaining_bytes / word;
++		if (dma->curr_xfer_len > bytes_per_buffer)
++			dma->curr_xfer_len = bytes_per_buffer;
++
++		ret = dspi_next_xfer_dma_submit(dspi);
++		if (ret) {
++			dev_err(dev, "DMA transfer failed\n");
++			goto exit;
++
++		} else {
++			curr_remaining_bytes -= dma->curr_xfer_len * word;
++			if (curr_remaining_bytes < 0)
++				curr_remaining_bytes = 0;
++		}
++	}
++
++exit:
++	return ret;
++}
++
++static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
++{
++	struct fsl_dspi_dma *dma;
++	struct dma_slave_config cfg;
++	struct device *dev = &dspi->pdev->dev;
++	int ret;
++
++	dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
++	if (!dma)
++		return -ENOMEM;
++
++	dma->chan_rx = dma_request_slave_channel(dev, "rx");
++	if (!dma->chan_rx) {
++		dev_err(dev, "rx dma channel not available\n");
++		ret = -ENODEV;
++		return ret;
++	}
++
++	dma->chan_tx = dma_request_slave_channel(dev, "tx");
++	if (!dma->chan_tx) {
++		dev_err(dev, "tx dma channel not available\n");
++		ret = -ENODEV;
++		goto err_tx_channel;
++	}
++
++	dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
++					&dma->tx_dma_phys, GFP_KERNEL);
++	if (!dma->tx_dma_buf) {
++		ret = -ENOMEM;
++		goto err_tx_dma_buf;
++	}
++
++	dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
++					&dma->rx_dma_phys, GFP_KERNEL);
++	if (!dma->rx_dma_buf) {
++		ret = -ENOMEM;
++		goto err_rx_dma_buf;
++	}
++
++	cfg.src_addr = phy_addr + SPI_POPR;
++	cfg.dst_addr = phy_addr + SPI_PUSHR;
++	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	cfg.src_maxburst = 1;
++	cfg.dst_maxburst = 1;
++
++	cfg.direction = DMA_DEV_TO_MEM;
++	ret = dmaengine_slave_config(dma->chan_rx, &cfg);
++	if (ret) {
++		dev_err(dev, "can't configure rx dma channel\n");
++		ret = -EINVAL;
++		goto err_slave_config;
++	}
++
++	cfg.direction = DMA_MEM_TO_DEV;
++	ret = dmaengine_slave_config(dma->chan_tx, &cfg);
++	if (ret) {
++		dev_err(dev, "can't configure tx dma channel\n");
++		ret = -EINVAL;
++		goto err_slave_config;
++	}
++
++	dspi->dma = dma;
++	init_completion(&dma->cmd_tx_complete);
++	init_completion(&dma->cmd_rx_complete);
++
++	return 0;
++
++err_slave_config:
++	dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
++			dma->rx_dma_buf, dma->rx_dma_phys);
++err_rx_dma_buf:
++	dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
++			dma->tx_dma_buf, dma->tx_dma_phys);
++err_tx_dma_buf:
++	dma_release_channel(dma->chan_tx);
++err_tx_channel:
++	dma_release_channel(dma->chan_rx);
++
++	devm_kfree(dev, dma);
++	dspi->dma = NULL;
++
++	return ret;
++}
++
++static void dspi_release_dma(struct fsl_dspi *dspi)
++{
++	struct fsl_dspi_dma *dma = dspi->dma;
++	struct device *dev = &dspi->pdev->dev;
++
++	if (dma) {
++		if (dma->chan_tx) {
++			dma_unmap_single(dev, dma->tx_dma_phys,
++					DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
++			dma_release_channel(dma->chan_tx);
++		}
++
++		if (dma->chan_rx) {
++			dma_unmap_single(dev, dma->rx_dma_phys,
++					DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
++			dma_release_channel(dma->chan_rx);
++		}
++	}
++}
++
+ static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
+ 		unsigned long clkrate)
+ {
+@@ -425,6 +705,12 @@ static int dspi_transfer_one_message(str
+ 			regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
+ 			dspi_tcfq_write(dspi);
+ 			break;
++		case DSPI_DMA_MODE:
++			regmap_write(dspi->regmap, SPI_RSER,
++				SPI_RSER_TFFFE | SPI_RSER_TFFFD |
++				SPI_RSER_RFDFE | SPI_RSER_RFDFD);
++			status = dspi_dma_xfer(dspi);
++			break;
+ 		default:
+ 			dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
+ 				trans_mode);
+@@ -432,9 +718,13 @@ static int dspi_transfer_one_message(str
+ 			goto out;
+ 		}
+ 
+-		if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
+-			dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
+-		dspi->waitflags = 0;
++		if (trans_mode != DSPI_DMA_MODE) {
++			if (wait_event_interruptible(dspi->waitq,
++						dspi->waitflags))
++				dev_err(&dspi->pdev->dev,
++					"wait transfer complete fail!\n");
++			dspi->waitflags = 0;
++		}
+ 
+ 		if (transfer->delay_usecs)
+ 			udelay(transfer->delay_usecs);
+@@ -712,7 +1002,8 @@ static int dspi_probe(struct platform_de
+ 	if (IS_ERR(dspi->regmap)) {
+ 		dev_err(&pdev->dev, "failed to init regmap: %ld\n",
+ 				PTR_ERR(dspi->regmap));
+-		return PTR_ERR(dspi->regmap);
++		ret = PTR_ERR(dspi->regmap);
++		goto out_master_put;
+ 	}
+ 
+ 	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
+@@ -740,6 +1031,13 @@ static int dspi_probe(struct platform_de
+ 		goto out_clk_put;
+ 	}
+ 
++	if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
++		if (dspi_request_dma(dspi, res->start)) {
++			dev_err(&pdev->dev, "can't get dma channels\n");
++			goto out_clk_put;
++		}
++	}
++
+ 	master->max_speed_hz =
+ 		clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
+ 
+@@ -768,6 +1066,7 @@ static int dspi_remove(struct platform_d
+ 	struct fsl_dspi *dspi = spi_master_get_devdata(master);
+ 
+ 	/* Disconnect from the SPI framework */
++	dspi_release_dma(dspi);
+ 	clk_disable_unprepare(dspi->clk);
+ 	spi_unregister_master(dspi->master);
+ 
diff --git a/target/linux/layerscape/patches-4.9/816-tty-serial-support-layerscape.patch b/target/linux/layerscape/patches-4.9/816-tty-serial-support-layerscape.patch
new file mode 100644
index 000000000..3271563f7
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/816-tty-serial-support-layerscape.patch
@@ -0,0 +1,162 @@
+From c35aec61e5bb0faafb2847a0d750ebd7345a4b0f Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Wed, 17 Jan 2018 15:40:24 +0800
+Subject: [PATCH 28/30] tty: serial: support layerscape
+
+This is an integrated patch for layerscape uart support.
+
+Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
+Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/tty/serial/fsl_lpuart.c | 66 ++++++++++++++++++++++++++++-------------
+ 1 file changed, 46 insertions(+), 20 deletions(-)
+
+--- a/drivers/tty/serial/fsl_lpuart.c
++++ b/drivers/tty/serial/fsl_lpuart.c
+@@ -231,6 +231,8 @@
+ #define DEV_NAME	"ttyLP"
+ #define UART_NR		6
+ 
++static DECLARE_BITMAP(linemap, UART_NR);
++
+ struct lpuart_port {
+ 	struct uart_port	port;
+ 	struct clk		*clk;
+@@ -1349,6 +1351,18 @@ lpuart_set_termios(struct uart_port *por
+ 	/* ask the core to calculate the divisor */
+ 	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
+ 
++	/*
++	 * Need to update the Ring buffer length according to the selected
++	 * baud rate and restart Rx DMA path.
++	 *
++	 * Since timer function acqures sport->port.lock, need to stop before
++	 * acquring same lock because otherwise del_timer_sync() can deadlock.
++	 */
++	if (old && sport->lpuart_dma_rx_use) {
++		del_timer_sync(&sport->lpuart_timer);
++		lpuart_dma_rx_free(&sport->port);
++	}
++
+ 	spin_lock_irqsave(&sport->port.lock, flags);
+ 
+ 	sport->port.read_status_mask = 0;
+@@ -1398,22 +1412,11 @@ lpuart_set_termios(struct uart_port *por
+ 	/* restore control register */
+ 	writeb(old_cr2, sport->port.membase + UARTCR2);
+ 
+-	/*
+-	 * If new baud rate is set, we will also need to update the Ring buffer
+-	 * length according to the selected baud rate and restart Rx DMA path.
+-	 */
+-	if (old) {
+-		if (sport->lpuart_dma_rx_use) {
+-			del_timer_sync(&sport->lpuart_timer);
+-			lpuart_dma_rx_free(&sport->port);
+-		}
+-
+-		if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
+-			sport->lpuart_dma_rx_use = true;
++	if (old && sport->lpuart_dma_rx_use) {
++		if (!lpuart_start_rx_dma(sport))
+ 			rx_dma_timer_init(sport);
+-		} else {
++		else
+ 			sport->lpuart_dma_rx_use = false;
+-		}
+ 	}
+ 
+ 	spin_unlock_irqrestore(&sport->port.lock, flags);
+@@ -1641,6 +1644,13 @@ lpuart_console_write(struct console *co,
+ {
+ 	struct lpuart_port *sport = lpuart_ports[co->index];
+ 	unsigned char  old_cr2, cr2;
++	unsigned long flags;
++	int locked = 1;
++
++	if (sport->port.sysrq || oops_in_progress)
++		locked = spin_trylock_irqsave(&sport->port.lock, flags);
++	else
++		spin_lock_irqsave(&sport->port.lock, flags);
+ 
+ 	/* first save CR2 and then disable interrupts */
+ 	cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
+@@ -1655,6 +1665,9 @@ lpuart_console_write(struct console *co,
+ 		barrier();
+ 
+ 	writeb(old_cr2, sport->port.membase + UARTCR2);
++
++	if (locked)
++		spin_unlock_irqrestore(&sport->port.lock, flags);
+ }
+ 
+ static void
+@@ -1662,6 +1675,13 @@ lpuart32_console_write(struct console *c
+ {
+ 	struct lpuart_port *sport = lpuart_ports[co->index];
+ 	unsigned long  old_cr, cr;
++	unsigned long flags;
++	int locked = 1;
++
++	if (sport->port.sysrq || oops_in_progress)
++		locked = spin_trylock_irqsave(&sport->port.lock, flags);
++	else
++		spin_lock_irqsave(&sport->port.lock, flags);
+ 
+ 	/* first save CR2 and then disable interrupts */
+ 	cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
+@@ -1676,6 +1696,9 @@ lpuart32_console_write(struct console *c
+ 		barrier();
+ 
+ 	lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
++
++	if (locked)
++		spin_unlock_irqrestore(&sport->port.lock, flags);
+ }
+ 
+ /*
+@@ -1900,13 +1923,13 @@ static int lpuart_probe(struct platform_
+ 
+ 	ret = of_alias_get_id(np, "serial");
+ 	if (ret < 0) {
+-		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
+-		return ret;
+-	}
+-	if (ret >= ARRAY_SIZE(lpuart_ports)) {
+-		dev_err(&pdev->dev, "serial%d out of range\n", ret);
+-		return -EINVAL;
++		ret = find_first_zero_bit(linemap, UART_NR);
++		if (ret >= UART_NR) {
++			dev_err(&pdev->dev, "port line is full, add device failed\n");
++			return ret;
++		}
+ 	}
++	set_bit(ret, linemap);
+ 	sport->port.line = ret;
+ 	sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
+ 
+@@ -1988,6 +2011,7 @@ static int lpuart_remove(struct platform
+ 	struct lpuart_port *sport = platform_get_drvdata(pdev);
+ 
+ 	uart_remove_one_port(&lpuart_reg, &sport->port);
++	clear_bit(sport->port.line, linemap);
+ 
+ 	clk_disable_unprepare(sport->clk);
+ 
+@@ -2072,12 +2096,10 @@ static int lpuart_resume(struct device *
+ 
+ 	if (sport->lpuart_dma_rx_use) {
+ 		if (sport->port.irq_wake) {
+-			if (!lpuart_start_rx_dma(sport)) {
+-				sport->lpuart_dma_rx_use = true;
++			if (!lpuart_start_rx_dma(sport))
+ 				rx_dma_timer_init(sport);
+-			} else {
++			else
+ 				sport->lpuart_dma_rx_use = false;
+-			}
+ 		}
+ 	}
+ 
diff --git a/target/linux/layerscape/patches-4.14/807-usb-support-layerscape.patch b/target/linux/layerscape/patches-4.9/817-usb-support-layerscape.patch
similarity index 62%
rename from target/linux/layerscape/patches-4.14/807-usb-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/817-usb-support-layerscape.patch
index 5fd8350b6..a6a1594a9 100644
--- a/target/linux/layerscape/patches-4.14/807-usb-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/817-usb-support-layerscape.patch
@@ -1,102 +1,101 @@
-From 01b1b2989e907305d8b885468c2743f5e35e1b9a Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Thu, 13 Dec 2018 11:15:15 +0800
-Subject: [PATCH] usb: support layerscape
+From 1d35e363dd6e8bb1733bca0dfc186e3f70e692fe Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:38:52 +0800
+Subject: [PATCH 29/32] usb: support layerscape
 
-This is an integrated patch of usb for layerscape
+This is an integrated patch for layerscape usb support.
 
-Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
-Signed-off-by: Changming Huang <jerry.huang@nxp.com>
-Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
-Signed-off-by: Li Yang <leoli@freescale.com>
-Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
-Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
-Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
-Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
-Signed-off-by: Roger Quadros <rogerq@ti.com>
-Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
-Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
+Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
+Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
+Signed-off-by: Changming Huang <jerry.huang@nxp.com>
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
+Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- .../devicetree/bindings/usb/dwc3.txt          |   2 +
- arch/arm64/include/asm/io.h                   |  28 ++
- drivers/usb/common/common.c                   |  50 ++++
- drivers/usb/core/usb.c                        |   1 +
- drivers/usb/dwc3/core.c                       | 104 +++++++
- drivers/usb/dwc3/core.h                       |  44 +++
- drivers/usb/dwc3/ep0.c                        |   4 +-
- drivers/usb/dwc3/gadget.c                     |   7 +
- drivers/usb/dwc3/host.c                       |   9 +
- drivers/usb/gadget/udc/fsl_udc_core.c         |  46 +--
- drivers/usb/gadget/udc/fsl_usb2_udc.h         |  16 +-
- drivers/usb/host/Kconfig                      |   2 +-
- drivers/usb/host/ehci-fsl.c                   | 276 ++++++++++++++++--
- drivers/usb/host/ehci-fsl.h                   |   3 +
- drivers/usb/host/ehci-hub.c                   |   2 +
- drivers/usb/host/ehci.h                       |   3 +
- drivers/usb/host/fsl-mph-dr-of.c              |  11 +
- drivers/usb/host/xhci-hub.c                   |  22 ++
- drivers/usb/host/xhci-plat.c                  |  16 +-
- drivers/usb/host/xhci-ring.c                  |  28 +-
- drivers/usb/host/xhci.c                       |  39 ++-
- drivers/usb/host/xhci.h                       |   6 +-
- drivers/usb/phy/phy-fsl-usb.c                 |  59 +++-
- drivers/usb/phy/phy-fsl-usb.h                 |   8 +
- include/linux/usb.h                           |   1 +
- include/linux/usb/of.h                        |   2 +
- 26 files changed, 704 insertions(+), 85 deletions(-)
+ drivers/net/usb/cdc_ether.c           |   8 +
+ drivers/net/usb/r8152.c               |   6 +
+ drivers/usb/common/common.c           |  50 +++++
+ drivers/usb/core/hub.c                |   8 +
+ drivers/usb/dwc3/core.c               | 243 +++++++++++++++++++++-
+ drivers/usb/dwc3/core.h               |  51 ++++-
+ drivers/usb/dwc3/ep0.c                |   4 +-
+ drivers/usb/dwc3/gadget.c             |   7 +
+ drivers/usb/dwc3/host.c               |  24 ++-
+ drivers/usb/gadget/udc/fsl_udc_core.c |  46 +++--
+ drivers/usb/gadget/udc/fsl_usb2_udc.h |  16 +-
+ drivers/usb/host/Kconfig              |   4 +-
+ drivers/usb/host/ehci-fsl.c           | 279 ++++++++++++++++++++++++--
+ drivers/usb/host/ehci-fsl.h           |   3 +
+ drivers/usb/host/ehci-hub.c           |   4 +
+ drivers/usb/host/ehci.h               |   9 +
+ drivers/usb/host/fsl-mph-dr-of.c      |  16 +-
+ drivers/usb/host/xhci-hub.c           |  22 ++
+ drivers/usb/host/xhci-plat.c          |  16 +-
+ drivers/usb/host/xhci-ring.c          |  29 ++-
+ drivers/usb/host/xhci.c               |  38 +++-
+ drivers/usb/host/xhci.h               |   6 +-
+ drivers/usb/phy/phy-fsl-usb.c         |  59 ++++--
+ drivers/usb/phy/phy-fsl-usb.h         |   8 +
+ include/linux/usb.h                   |   1 +
+ include/linux/usb/of.h                |   2 +
+ 26 files changed, 867 insertions(+), 92 deletions(-)
 
---- a/Documentation/devicetree/bindings/usb/dwc3.txt
-+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
-@@ -47,6 +47,8 @@ Optional properties:
- 			from P0 to P1/P2/P3 without delay.
-  - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check
- 			during HS transmit.
-+ - snps,disable_devinit_u1u2: when set, disable device-initiated U1/U2
-+			LPM request in USB device mode.
-  - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
- 			utmi_l1_suspend_n, false when asserts utmi_sleep_n
-  - snps,hird-threshold: HIRD threshold
---- a/arch/arm64/include/asm/io.h
-+++ b/arch/arm64/include/asm/io.h
-@@ -194,6 +194,34 @@ extern void __iomem *ioremap_cache(phys_
- #define iowrite32be(v,p)	({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
- #define iowrite64be(v,p)	({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
+--- a/drivers/net/usb/cdc_ether.c
++++ b/drivers/net/usb/cdc_ether.c
+@@ -533,6 +533,7 @@ static const struct driver_info wwan_inf
+ #define LINKSYS_VENDOR_ID	0x13b1
+ #define NVIDIA_VENDOR_ID	0x0955
+ #define HP_VENDOR_ID		0x03f0
++#define TPLINK_VENDOR_ID	0x2357
  
-+/* access ports */
-+#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
-+#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
+ static const struct usb_device_id	products[] = {
+ /* BLACKLIST !!
+@@ -742,6 +743,13 @@ static const struct usb_device_id	produc
+ 			USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
+ 	.driver_info = 0,
+ },
 +
-+#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
-+#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
-+
-+#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
-+#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
-+
-+/* Clear and set bits in one shot.  These macros can be used to clear and
-+ * set multiple bits in a register using a single read-modify-write.  These
-+ * macros can also be used to set a multiple-bit bit pattern using a mask,
-+ * by specifying the mask in the 'clear' parameter and the new bit pattern
-+ * in the 'set' parameter.
-+ */
-+
-+#define clrsetbits_be32(addr, clear, set) \
-+	iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
-+#define clrsetbits_le32(addr, clear, set) \
-+	iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
-+#define clrsetbits_be16(addr, clear, set) \
-+	iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
-+#define clrsetbits_le16(addr, clear, set) \
-+	iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
-+#define clrsetbits_8(addr, clear, set) \
-+	iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
-+
- #include <asm-generic/io.h>
++	/* TP-LINK UE300 USB 3.0 Ethernet Adapters (based on Realtek RTL8153) */
++{
++	USB_DEVICE_AND_INTERFACE_INFO(TPLINK_VENDOR_ID, 0x0601, USB_CLASS_COMM,
++			USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
++	.driver_info = 0,
++},
+ 
+ /* WHITELIST!!!
+  *
+--- a/drivers/net/usb/r8152.c
++++ b/drivers/net/usb/r8152.c
+@@ -521,6 +521,7 @@ enum rtl8152_flags {
+ #define VENDOR_ID_LENOVO		0x17ef
+ #define VENDOR_ID_LINKSYS		0x13b1
+ #define VENDOR_ID_NVIDIA		0x0955
++#define VENDOR_ID_TPLINK		0x2357
+ 
+ #define MCU_TYPE_PLA			0x0100
+ #define MCU_TYPE_USB			0x0000
+@@ -1817,6 +1818,10 @@ static int rx_bottom(struct r8152 *tp, i
+ 			unsigned int pkt_len;
+ 			struct sk_buff *skb;
+ 
++			/* limite the skb numbers for rx_queue */
++			if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
++				break;
++
+ 			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
+ 			if (pkt_len < ETH_ZLEN)
+ 				break;
+@@ -4513,6 +4518,7 @@ static struct usb_device_id rtl8152_tabl
+ 	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
+ 	{REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
+ 	{REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
++	{REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
+ 	{}
+ };
  
- /*
 --- a/drivers/usb/common/common.c
 +++ b/drivers/usb/common/common.c
 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[]
@@ -156,21 +155,73 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
  {
  	int ret;
---- a/drivers/usb/core/usb.c
-+++ b/drivers/usb/core/usb.c
-@@ -593,6 +593,7 @@ struct usb_device *usb_alloc_dev(struct
- 	dev->dev.dma_mask = bus->sysdev->dma_mask;
- 	dev->dev.dma_pfn_offset = bus->sysdev->dma_pfn_offset;
- 	set_dev_node(&dev->dev, dev_to_node(bus->sysdev));
-+	dev->dev.of_node = bus->controller->of_node;
- 	dev->state = USB_STATE_ATTACHED;
- 	dev->lpm_disable_count = 1;
- 	atomic_set(&dev->urbnum, 0);
+--- a/drivers/usb/core/hub.c
++++ b/drivers/usb/core/hub.c
+@@ -4433,6 +4433,14 @@ hub_port_init(struct usb_hub *hub, struc
+ 	else
+ 		speed = usb_speed_string(udev->speed);
+ 
++#if !defined(CONFIG_FSL_USB2_OTG) && !defined(CONFIG_FSL_USB2_OTG_MODULE)
++if (udev->speed != USB_SPEED_SUPER)
++	dev_info(&udev->dev,
++	"%s %s USB device number %d using %s\n",
++	 (udev->config) ? "reset" : "new", speed,
++	devnum, udev->bus->controller->driver->name);
++#endif
++
+ 	if (udev->speed < USB_SPEED_SUPER)
+ 		dev_info(&udev->dev,
+ 				"%s %s USB device number %d using %s\n",
 --- a/drivers/usb/dwc3/core.c
 +++ b/drivers/usb/dwc3/core.c
-@@ -766,6 +766,96 @@ static void dwc3_core_setup_global_contr
- static int dwc3_core_get_phy(struct dwc3 *dwc);
- static int dwc3_core_ulpi_init(struct dwc3 *dwc);
+@@ -58,6 +58,7 @@ static int dwc3_get_dr_mode(struct dwc3
+ 	enum usb_dr_mode mode;
+ 	struct device *dev = dwc->dev;
+ 	unsigned int hw_mode;
++	struct device_node      *node = dev->of_node;
+ 
+ 	if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
+ 		dwc->dr_mode = USB_DR_MODE_OTG;
+@@ -83,6 +84,24 @@ static int dwc3_get_dr_mode(struct dwc3
+ 		mode = USB_DR_MODE_HOST;
+ 		break;
+ 	default:
++		/* Adjust Frame Length */
++		if (dwc->configure_gfladj)
++		dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
++				GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
++
++	/* Change burst beat and outstanding pipelined transfers requests */
++	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
++		(dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
++	dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
++		dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
++
++	/* Enable Snooping */
++	if (node && of_dma_is_coherent(node)) {
++		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
++		dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
++		dev_dbg(dev, "enabled snooping for usb\n");
++	}
++
+ 		if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
+ 			mode = USB_DR_MODE_HOST;
+ 		else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
+@@ -227,8 +246,9 @@ static void dwc3_frame_length_adjustment
+ 
+ 	reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
+ 	dft = reg & DWC3_GFLADJ_30MHZ_MASK;
+-	if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
+-	    "request value same as default, ignoring\n")) {
++	if (dft == dwc->fladj) {
++		dev_warn(dwc->dev, "request value same as default, ignoring\n");
++	} else {
+ 		reg &= ~DWC3_GFLADJ_30MHZ_MASK;
+ 		reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
+ 		dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
+@@ -599,6 +619,99 @@ static int dwc3_phy_setup(struct dwc3 *d
+ 	return 0;
+ }
  
 +/* set global soc bus configuration registers */
 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
@@ -251,7 +302,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	}
 +
 +	/* Handle usb snooping */
-+	if (dwc->dma_coherent) {
++	if (dwc->dma_snooping_quirk) {
 +		cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
 +		cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
 +			(AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
@@ -260,64 +311,198 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	}
 +
 +	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
++
 +}
 +
- /**
-  * dwc3_core_init - Low-level initialization of DWC3 Core
-  * @dwc: Pointer to our controller context structure
-@@ -828,6 +918,8 @@ static int dwc3_core_init(struct dwc3 *d
- 	/* Adjust Frame Length */
- 	dwc3_frame_length_adjustment(dwc);
++
++
+ static void dwc3_core_exit(struct dwc3 *dwc)
+ {
+ 	dwc3_event_buffers_cleanup(dwc);
+@@ -741,6 +854,8 @@ static int dwc3_core_init(struct dwc3 *d
+ 	if (ret)
+ 		goto err1;
  
 +	dwc3_set_soc_bus_cfg(dwc);
 +
- 	usb_phy_set_suspend(dwc->usb2_phy, 0);
- 	usb_phy_set_suspend(dwc->usb3_phy, 0);
- 	ret = phy_power_on(dwc->usb2_generic_phy);
-@@ -1074,6 +1166,8 @@ static void dwc3_get_properties(struct d
- 				&hird_threshold);
- 	dwc->usb3_lpm_capable = device_property_read_bool(dev,
- 				"snps,usb3_lpm_capable");
-+	dwc->dma_coherent = device_property_read_bool(dev,
-+				"dma-coherent");
+ 	/* Adjust Frame Length */
+ 	dwc3_frame_length_adjustment(dwc);
  
- 	dwc->disable_scramble_quirk = device_property_read_bool(dev,
- 				"snps,disable_scramble_quirk");
-@@ -1106,8 +1200,16 @@ static void dwc3_get_properties(struct d
- 	dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
- 				"snps,dis-tx-ipgap-linecheck-quirk");
+@@ -939,11 +1054,117 @@ static void dwc3_core_exit_mode(struct d
+ 	}
+ }
  
++static void dwc3_get_properties(struct dwc3 *dwc)
++{
++	struct device           *dev = dwc->dev;
++	struct device_node      *node = dev->of_node;
++	u8                      lpm_nyet_threshold;
++	u8                      tx_de_emphasis;
++	u8                      hird_threshold;
++
++	/* default to highest possible threshold */
++	lpm_nyet_threshold = 0xff;
++
++	/* default to -3.5dB de-emphasis */
++	tx_de_emphasis = 1;
++
++	/*
++	 * default to assert utmi_sleep_n and use maximum allowed HIRD
++	 * threshold value of 0b1100
++	 */
++	hird_threshold = 12;
++
++	dwc->maximum_speed = usb_get_maximum_speed(dev);
++	dwc->dr_mode = usb_get_dr_mode(dev);
++	dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
++
++	dwc->sysdev_is_parent = device_property_read_bool(dev,
++				"linux,sysdev_is_parent");
++	if (dwc->sysdev_is_parent)
++		dwc->sysdev = dwc->dev->parent;
++	else
++		dwc->sysdev = dwc->dev;
++
++	dwc->has_lpm_erratum = device_property_read_bool(dev,
++				"snps,has-lpm-erratum");
++	device_property_read_u8(dev, "snps,lpm-nyet-threshold",
++				&lpm_nyet_threshold);
++	dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
++				"snps,is-utmi-l1-suspend");
++	device_property_read_u8(dev, "snps,hird-threshold",
++				&hird_threshold);
++	dwc->usb3_lpm_capable = device_property_read_bool(dev,
++				"snps,usb3_lpm_capable");
 +	dwc->quirk_reverse_in_out = device_property_read_bool(dev,
 +				"snps,quirk_reverse_in_out");
 +	dwc->quirk_stop_transfer_in_block = device_property_read_bool(dev,
 +				"snps,quirk_stop_transfer_in_block");
 +	dwc->quirk_stop_ep_in_u1 = device_property_read_bool(dev,
 +				"snps,quirk_stop_ep_in_u1");
- 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
- 				"snps,tx_de_emphasis_quirk");
++
++	dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
++
++	dwc->configure_gfladj =
++				of_property_read_bool(node, "configure-gfladj");
++	dwc->dr_mode = usb_get_dr_mode(dev);
++
++	dwc->disable_scramble_quirk = device_property_read_bool(dev,
++				"snps,disable_scramble_quirk");
++	dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
++				"snps,u2exit_lfps_quirk");
++	dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
++				"snps,u2ss_inp3_quirk");
++	dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
++				"snps,req_p1p2p3_quirk");
++	dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
++				"snps,del_p1p2p3_quirk");
++	dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
++				"snps,del_phy_power_chg_quirk");
++	dwc->lfps_filter_quirk = device_property_read_bool(dev,
++				"snps,lfps_filter_quirk");
++	dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
++				"snps,rx_detect_poll_quirk");
++	dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
++				"snps,dis_u3_susphy_quirk");
++	dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
++				"snps,dis_u2_susphy_quirk");
++	dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
++				"snps,dis_enblslpm_quirk");
++	dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
++				"snps,dis_rxdet_inp3_quirk");
++	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
++				"snps,dis-u2-freeclk-exists-quirk");
++	dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
++				"snps,dis-del-phy-power-chg-quirk");
++	dwc->dma_snooping_quirk = device_property_read_bool(dev,
++				"snps,dma-snooping");
++
++	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
++				"snps,tx_de_emphasis_quirk");
 +	dwc->disable_devinit_u1u2_quirk = device_property_read_bool(dev,
 +				"snps,disable_devinit_u1u2");
- 	device_property_read_u8(dev, "snps,tx_de_emphasis",
- 				&tx_de_emphasis);
- 	device_property_read_string(dev, "snps,hsphy_interface",
-@@ -1365,12 +1467,14 @@ static int dwc3_resume_common(struct dwc
++	device_property_read_u8(dev, "snps,tx_de_emphasis",
++				&tx_de_emphasis);
++	device_property_read_string(dev, "snps,hsphy_interface",
++				&dwc->hsphy_interface);
++	device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
++				&dwc->fladj);
++
++	dwc->lpm_nyet_threshold = lpm_nyet_threshold;
++	dwc->tx_de_emphasis = tx_de_emphasis;
++
++	dwc->hird_threshold = hird_threshold
++		| (dwc->is_utmi_l1_suspend << 4);
++
++	dwc->imod_interval = 0;
++}
++
+ #define DWC3_ALIGN_MASK		(16 - 1)
  
- 	switch (dwc->dr_mode) {
- 	case USB_DR_MODE_PERIPHERAL:
-+		dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
- 	case USB_DR_MODE_OTG:
- 		spin_lock_irqsave(&dwc->lock, flags);
- 		dwc3_gadget_resume(dwc);
- 		spin_unlock_irqrestore(&dwc->lock, flags);
- 		/* FALLTHROUGH */
- 	case USB_DR_MODE_HOST:
-+		dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
- 	default:
- 		/* do nothing */
- 		break;
+ static int dwc3_probe(struct platform_device *pdev)
+ {
+ 	struct device		*dev = &pdev->dev;
++	struct device_node      *node = dev->of_node;
+ 	struct resource		*res;
+ 	struct dwc3		*dwc;
+ 	u8			lpm_nyet_threshold;
+@@ -975,6 +1196,11 @@ static int dwc3_probe(struct platform_de
+ 	dwc->xhci_resources[0].flags = res->flags;
+ 	dwc->xhci_resources[0].name = res->name;
+ 
++	if (node) {
++		dwc->configure_gfladj =
++			of_property_read_bool(node, "configure-gfladj");
++	}
++
+ 	res->start += DWC3_GLOBALS_REGS_START;
+ 
+ 	/*
+@@ -1017,6 +1243,12 @@ static int dwc3_probe(struct platform_de
+ 	dwc->usb3_lpm_capable = device_property_read_bool(dev,
+ 				"snps,usb3_lpm_capable");
+ 
++	dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
++
++	dwc->configure_gfladj =
++			of_property_read_bool(node, "configure-gfladj");
++	dwc->dr_mode = of_usb_get_dr_mode(node);
++
+ 	dwc->disable_scramble_quirk = device_property_read_bool(dev,
+ 				"snps,disable_scramble_quirk");
+ 	dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
+@@ -1061,6 +1293,8 @@ static int dwc3_probe(struct platform_de
+ 	dwc->hird_threshold = hird_threshold
+ 		| (dwc->is_utmi_l1_suspend << 4);
+ 
++	dwc3_get_properties(dwc);
++
+ 	platform_set_drvdata(pdev, dwc);
+ 	dwc3_cache_hwparams(dwc);
+ 
+@@ -1084,6 +1318,11 @@ static int dwc3_probe(struct platform_de
+ 	if (ret < 0)
+ 		goto err1;
+ 
++	/* Adjust Frame Length */
++	if (dwc->configure_gfladj)
++	dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
++		    GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
++
+ 	pm_runtime_forbid(dev);
+ 
+ 	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 --- a/drivers/usb/dwc3/core.h
 +++ b/drivers/usb/dwc3/core.h
-@@ -161,6 +161,32 @@
+@@ -26,6 +26,7 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/mm.h>
+ #include <linux/debugfs.h>
++#include <linux/of_address.h>
+ 
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
+@@ -154,6 +155,32 @@
  
  /* Bit fields */
  
@@ -350,7 +535,26 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  /* Global Debug Queue/FIFO Space Available Register */
  #define DWC3_GDBGFIFOSPACE_NUM(n)	((n) & 0x1f)
  #define DWC3_GDBGFIFOSPACE_TYPE(n)	(((n) << 5) & 0x1e0)
-@@ -788,6 +814,7 @@ struct dwc3_scratchpad_array {
+@@ -182,7 +209,6 @@
+ #define DWC3_GCTL_CLK_PIPE	(1)
+ #define DWC3_GCTL_CLK_PIPEHALF	(2)
+ #define DWC3_GCTL_CLK_MASK	(3)
+-
+ #define DWC3_GCTL_PRTCAP(n)	(((n) & (3 << 12)) >> 12)
+ #define DWC3_GCTL_PRTCAPDIR(n)	((n) << 12)
+ #define DWC3_GCTL_PRTCAP_HOST	1
+@@ -294,6 +320,10 @@
+ /* Global Frame Length Adjustment Register */
+ #define DWC3_GFLADJ_30MHZ_SDBND_SEL		(1 << 7)
+ #define DWC3_GFLADJ_30MHZ_MASK			0x3f
++#define GFLADJ_30MHZ_REG_SEL           (1 << 7)
++#define GFLADJ_30MHZ(n)                        ((n) & 0x3f)
++#define GFLADJ_30MHZ_DEFAULT           0x20
++
+ 
+ /* Global User Control Register 2 */
+ #define DWC3_GUCTL2_RST_ACTBITLATER		(1 << 14)
+@@ -758,6 +788,7 @@ struct dwc3_scratchpad_array {
   * @regs: base address for our registers
   * @regs_size: address space size
   * @fladj: frame length adjustment
@@ -358,27 +562,23 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
   * @irq_gadget: peripheral controller's IRQ number
   * @nr_scratch: number of scratch buffers
   * @u1u2: only used on revisions <1.83a for workaround
-@@ -843,6 +870,7 @@ struct dwc3_scratchpad_array {
-  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
-  * @three_stage_setup: set if we perform a three phase setup
-  * @usb3_lpm_capable: set if hadrware supports Link Power Management
-+ * @dma_coherent: set if hadrware supports DMA snoop
-  * @disable_scramble_quirk: set if we enable the disable scramble quirk
-  * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
-  * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
-@@ -869,6 +897,11 @@ struct dwc3_scratchpad_array {
+@@ -834,6 +865,7 @@ struct dwc3_scratchpad_array {
   * 	1	- -3.5dB de-emphasis
   * 	2	- No de-emphasis
   * 	3	- Reserved
 + * @disable_devinit_u1u2_quirk: disable device-initiated U1/U2 request.
-+ * @quirk_reverse_in_out: prevent tx fifo reverse the data direction
-+ * @quirk_stop_transfer_in_block: prevent block transmission from being
-+ *				interrupted
-+ * @quirk_stop_ep_in_u1: replace stop commad with disable slot command
-  * @imod_interval: set the interrupt moderation interval in 250ns
-  *                 increments or 0 to disable.
   */
-@@ -921,6 +954,12 @@ struct dwc3 {
+ struct dwc3 {
+ 	struct usb_ctrlrequest	*ctrl_req;
+@@ -852,6 +884,7 @@ struct dwc3 {
+ 	spinlock_t		lock;
+ 
+ 	struct device		*dev;
++	struct device           *sysdev;
+ 
+ 	struct platform_device	*xhci;
+ 	struct resource		xhci_resources[DWC3_XHCI_RESOURCES_NUM];
+@@ -877,6 +910,12 @@ struct dwc3 {
  	enum usb_phy_interface	hsphy_mode;
  
  	u32			fladj;
@@ -391,15 +591,24 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	u32			irq_gadget;
  	u32			nr_scratch;
  	u32			u1u2;
-@@ -1005,6 +1044,7 @@ struct dwc3 {
+@@ -953,9 +992,12 @@ struct dwc3 {
+ 	unsigned		ep0_bounced:1;
+ 	unsigned		ep0_expect_in:1;
+ 	unsigned		has_hibernation:1;
++	unsigned		sysdev_is_parent:1;
+ 	unsigned		has_lpm_erratum:1;
+ 	unsigned		is_utmi_l1_suspend:1;
+ 	unsigned		is_fpga:1;
++	unsigned		needs_fifo_resize:1;
++	unsigned		configure_gfladj:1;
+ 	unsigned		pending_events:1;
+ 	unsigned		pullups_connected:1;
  	unsigned		setup_packet_pending:1;
- 	unsigned		three_stage_setup:1;
- 	unsigned		usb3_lpm_capable:1;
-+	unsigned		dma_coherent:1;
- 
- 	unsigned		disable_scramble_quirk:1;
- 	unsigned		u2exit_lfps_quirk:1;
-@@ -1024,6 +1064,10 @@ struct dwc3 {
+@@ -976,9 +1018,16 @@ struct dwc3 {
+ 	unsigned		dis_rxdet_inp3_quirk:1;
+ 	unsigned		dis_u2_freeclk_exists_quirk:1;
+ 	unsigned		dis_del_phy_power_chg_quirk:1;
++	unsigned		dma_snooping_quirk:1;
  
  	unsigned		tx_de_emphasis_quirk:1;
  	unsigned		tx_de_emphasis:2;
@@ -407,41 +616,37 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	unsigned                quirk_reverse_in_out:1;
 +	unsigned                quirk_stop_transfer_in_block:1;
 +	unsigned                quirk_stop_ep_in_u1:1;
- 
- 	u16			imod_interval;
++
++	u16                     imod_interval;
  };
+ 
+ /* -------------------------------------------------------------------------- */
 --- a/drivers/usb/dwc3/ep0.c
 +++ b/drivers/usb/dwc3/ep0.c
-@@ -391,7 +391,7 @@ static int dwc3_ep0_handle_u1(struct dwc
- 		return -EINVAL;
+@@ -360,9 +360,9 @@ static int dwc3_ep0_handle_status(struct
+ 		if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
+ 		    (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
+ 			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
+-			if (reg & DWC3_DCTL_INITU1ENA)
++			if ((reg & DWC3_DCTL_INITU1ENA) && !dwc->disable_devinit_u1u2_quirk)
+ 				usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
+-			if (reg & DWC3_DCTL_INITU2ENA)
++			if ((reg & DWC3_DCTL_INITU2ENA) && !dwc->disable_devinit_u1u2_quirk)
+ 				usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
+ 		}
  
- 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
--	if (set)
-+	if (set && !dwc->disable_devinit_u1u2_quirk)
- 		reg |= DWC3_DCTL_INITU1ENA;
- 	else
- 		reg &= ~DWC3_DCTL_INITU1ENA;
-@@ -413,7 +413,7 @@ static int dwc3_ep0_handle_u2(struct dwc
- 		return -EINVAL;
- 
- 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
--	if (set)
-+	if (set && !dwc->disable_devinit_u1u2_quirk)
- 		reg |= DWC3_DCTL_INITU2ENA;
- 	else
- 		reg &= ~DWC3_DCTL_INITU2ENA;
 --- a/drivers/usb/dwc3/gadget.c
 +++ b/drivers/usb/dwc3/gadget.c
-@@ -3203,6 +3203,7 @@ int dwc3_gadget_init(struct dwc3 *dwc)
+@@ -2927,6 +2927,7 @@ static irqreturn_t dwc3_interrupt(int ir
+ int dwc3_gadget_init(struct dwc3 *dwc)
  {
- 	int ret;
- 	int irq;
+ 	int ret, irq;
 +	u32	reg;
+ 	struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
  
- 	irq = dwc3_gadget_get_irq(dwc);
- 	if (irq < 0) {
-@@ -3279,6 +3280,12 @@ int dwc3_gadget_init(struct dwc3 *dwc)
- 		goto err4;
+ 	irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
+@@ -3041,6 +3042,12 @@ int dwc3_gadget_init(struct dwc3 *dwc)
+ 		goto err5;
  	}
  
 +	if (dwc->disable_devinit_u1u2_quirk) {
@@ -452,10 +657,43 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +
  	return 0;
  
- err4:
+ err5:
 --- a/drivers/usb/dwc3/host.c
 +++ b/drivers/usb/dwc3/host.c
-@@ -98,6 +98,15 @@ int dwc3_host_init(struct dwc3 *dwc)
+@@ -17,6 +17,8 @@
+ 
+ #include <linux/platform_device.h>
+ 
++#include <linux/of_device.h>
++
+ #include "core.h"
+ 
+ int dwc3_host_init(struct dwc3 *dwc)
+@@ -73,12 +75,21 @@ int dwc3_host_init(struct dwc3 *dwc)
+ 		return -ENOMEM;
+ 	}
+ 
+-	dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
++	if (IS_ENABLED(CONFIG_OF) && dwc->dev->of_node)
++		of_dma_configure(&xhci->dev, dwc->dev->of_node);
++	else
++		dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
+ 
+-	xhci->dev.parent	= dwc->dev;
++	xhci->dev.parent        = dwc->dev;
+ 	xhci->dev.dma_mask	= dwc->dev->dma_mask;
+ 	xhci->dev.dma_parms	= dwc->dev->dma_parms;
+ 
++	/* set DMA operations */
++	if (dwc->dev->of_node && of_dma_is_coherent(dwc->dev->of_node)) {
++		xhci->dev.archdata.dma_ops = dwc->dev->archdata.dma_ops;
++		dev_dbg(dwc->dev, "set dma_ops for usb\n");
++	}
++
+ 	dwc->xhci = xhci;
+ 
+ 	ret = platform_device_add_resources(xhci, dwc->xhci_resources,
+@@ -90,6 +101,15 @@ int dwc3_host_init(struct dwc3 *dwc)
  
  	memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
  
@@ -544,7 +782,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	}
  #endif
  
-@@ -1056,7 +1061,7 @@ static int fsl_ep_fifo_status(struct usb
+@@ -1057,7 +1062,7 @@ static int fsl_ep_fifo_status(struct usb
  	struct ep_queue_head *qh;
  
  	ep = container_of(_ep, struct fsl_ep, ep);
@@ -553,7 +791,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		return -ENODEV;
  
  	udc = (struct fsl_udc *)ep->udc;
-@@ -1598,14 +1603,13 @@ static int process_ep_req(struct fsl_udc
+@@ -1599,14 +1604,13 @@ static int process_ep_req(struct fsl_udc
  		struct fsl_req *curr_req)
  {
  	struct ep_td_struct *curr_td;
@@ -569,7 +807,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	actual = curr_req->req.length;
  
  	for (j = 0; j < curr_req->dtd_count; j++) {
-@@ -1650,11 +1654,9 @@ static int process_ep_req(struct fsl_udc
+@@ -1651,11 +1655,9 @@ static int process_ep_req(struct fsl_udc
  				status = -EPROTO;
  				break;
  			} else {
@@ -581,7 +819,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  			VDBG("dTD transmitted successful");
  		}
  
-@@ -1697,7 +1699,7 @@ static void dtd_complete_irq(struct fsl_
+@@ -1698,7 +1700,7 @@ static void dtd_complete_irq(struct fsl_
  		curr_ep = get_ep_by_pipe(udc, i);
  
  		/* If the ep is configured */
@@ -590,7 +828,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  			WARNING("Invalid EP?");
  			continue;
  		}
-@@ -2419,10 +2421,12 @@ static int fsl_udc_probe(struct platform
+@@ -2420,10 +2422,12 @@ static int fsl_udc_probe(struct platform
  		usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
  #endif
  
@@ -603,7 +841,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	/* Read Device Controller Capability Parameters register */
  	dccparams = fsl_readl(&dr_regs->dccparams);
-@@ -2462,9 +2466,11 @@ static int fsl_udc_probe(struct platform
+@@ -2463,9 +2467,11 @@ static int fsl_udc_probe(struct platform
  		dr_controller_setup(udc_controller);
  	}
  
@@ -615,15 +853,15 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	/* Setup gadget structure */
  	udc_controller->gadget.ops = &fsl_gadget_ops;
-@@ -2477,6 +2483,7 @@ static int fsl_udc_probe(struct platform
+@@ -2478,6 +2484,7 @@ static int fsl_udc_probe(struct platform
  	/* Setup gadget.dev and register with kernel */
  	dev_set_name(&udc_controller->gadget.dev, "gadget");
  	udc_controller->gadget.dev.of_node = pdev->dev.of_node;
-+	set_dma_ops(&udc_controller->gadget.dev, pdev->dev.dma_ops);
++	set_dma_ops(&udc_controller->gadget.dev, pdev->dev.archdata.dma_ops);
  
  	if (!IS_ERR_OR_NULL(udc_controller->transceiver))
  		udc_controller->gadget.is_otg = 1;
-@@ -2528,7 +2535,9 @@ err_free_irq:
+@@ -2529,7 +2536,9 @@ err_free_irq:
  err_iounmap:
  	if (pdata->exit)
  		pdata->exit(pdev);
@@ -633,7 +871,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  err_iounmap_noclk:
  	iounmap(dr_regs);
  err_release_mem_region:
-@@ -2556,8 +2565,9 @@ static int fsl_udc_remove(struct platfor
+@@ -2557,8 +2566,9 @@ static int fsl_udc_remove(struct platfor
  	udc_controller->done = &done;
  	usb_del_gadget_udc(&udc_controller->gadget);
  
@@ -644,7 +882,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	/* DR has been stopped in usb_gadget_unregister_driver() */
  	remove_proc_file();
  
-@@ -2569,7 +2579,7 @@ static int fsl_udc_remove(struct platfor
+@@ -2570,7 +2580,7 @@ static int fsl_udc_remove(struct platfor
  	dma_pool_destroy(udc_controller->td_pool);
  	free_irq(udc_controller->irq, udc_controller);
  	iounmap(dr_regs);
@@ -687,24 +925,27 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  #endif
 --- a/drivers/usb/host/Kconfig
 +++ b/drivers/usb/host/Kconfig
-@@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
+@@ -164,8 +164,8 @@ config XPS_USB_HCD_XILINX
+ 		devices only.
  
  config USB_EHCI_FSL
- 	tristate "Support for Freescale PPC on-chip EHCI USB controller"
+-	tristate "Support for Freescale PPC on-chip EHCI USB controller"
 -	depends on FSL_SOC
++	tristate "Support for Freescale QorIQ(ARM/PPC) on-chip EHCI USB controller"
 +	depends on USB_EHCI_HCD
  	select USB_EHCI_ROOT_HUB_TT
  	---help---
  	  Variation of ARC USB block used in some Freescale chips.
 --- a/drivers/usb/host/ehci-fsl.c
 +++ b/drivers/usb/host/ehci-fsl.c
-@@ -36,15 +36,126 @@
+@@ -36,15 +36,127 @@
  #include <linux/platform_device.h>
  #include <linux/fsl_devices.h>
  #include <linux/of_platform.h>
 +#include <linux/io.h>
 +
-+#ifdef CONFIG_PM
++#ifdef CONFIG_PPC
++#include <asm/fsl_pm.h>
 +#include <linux/suspend.h>
 +#endif
  
@@ -779,19 +1020,19 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
 +static void do_change_hcd(struct work_struct *work)
 +{
-+	struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
-+			change_hcd_work);
-+	struct usb_hcd *hcd = ehci_to_hcd(ehci);
-+	struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
-+	void __iomem *non_ehci = hcd->regs;
-+	int retval;
++struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
++				     change_hcd_work);
++struct usb_hcd *hcd = ehci_to_hcd(ehci);
++struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
++void __iomem *non_ehci = hcd->regs;
++int retval;
 +
 +	if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
-+		writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
-+		/* host, gadget and otg share same int line */
-+		retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
-+		if (retval == 0)
-+			ehci_fsl->have_hcd = 1;
++	writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
++	/* host, gadget and otg share same int line */
++	retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
++	if (retval == 0)
++		ehci_fsl->have_hcd = 1;
 +	} else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
 +		usb_remove_hcd(hcd);
 +		ehci_fsl->have_hcd = 0;
@@ -825,7 +1066,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  /* configure so an HC device and id are always provided */
  /* always called with process context; sleeping is OK */
  
-@@ -131,6 +242,12 @@ static int fsl_ehci_drv_probe(struct pla
+@@ -131,6 +243,12 @@ static int fsl_ehci_drv_probe(struct pla
  		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
  				CONTROL_REGISTER_W1C_MASK, 0x4);
  
@@ -838,7 +1079,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	/*
  	 * Enable UTMI phy and program PTS field in UTMI mode before asserting
  	 * controller reset for USB Controller version 2.5
-@@ -143,16 +260,20 @@ static int fsl_ehci_drv_probe(struct pla
+@@ -143,16 +261,20 @@ static int fsl_ehci_drv_probe(struct pla
  
  	/* Don't need to set host mode here. It will be done by tdi_reset() */
  
@@ -861,7 +1102,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		dev_dbg(&pdev->dev, "hcd=0x%p  ehci=0x%p, phy=0x%p\n",
  			hcd, ehci, hcd->usb_phy);
  
-@@ -168,6 +289,11 @@ static int fsl_ehci_drv_probe(struct pla
+@@ -168,6 +290,11 @@ static int fsl_ehci_drv_probe(struct pla
  			retval = -ENODEV;
  			goto err2;
  		}
@@ -873,7 +1114,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	}
  #endif
  	return retval;
-@@ -181,6 +307,17 @@ static int fsl_ehci_drv_probe(struct pla
+@@ -181,6 +308,17 @@ static int fsl_ehci_drv_probe(struct pla
  	return retval;
  }
  
@@ -891,7 +1132,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
  			       enum fsl_usb2_phy_modes phy_mode,
  			       unsigned int port_offset)
-@@ -219,6 +356,21 @@ static int ehci_fsl_setup_phy(struct usb
+@@ -219,6 +357,21 @@ static int ehci_fsl_setup_phy(struct usb
  		/* fall through */
  	case FSL_USB2_PHY_UTMI:
  	case FSL_USB2_PHY_UTMI_DUAL:
@@ -913,7 +1154,16 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		if (pdata->have_sysif_regs && pdata->controller_ver) {
  			/* controller version 1.6 or above */
  			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
-@@ -295,14 +447,9 @@ static int ehci_fsl_usb_setup(struct ehc
+@@ -286,20 +439,18 @@ static int ehci_fsl_usb_setup(struct ehc
+ 	if (pdata->has_fsl_erratum_a005275 == 1)
+ 		ehci->has_fsl_hs_errata = 1;
+ 
++	if (pdata->has_fsl_erratum_a005697 == 1)
++		ehci->has_fsl_susp_errata = 1;
++
+ 	if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
+ 			(pdata->operating_mode == FSL_USB2_DR_OTG))
+ 		if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  			return -EINVAL;
  
  	if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
@@ -929,13 +1179,13 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  			ehci->has_fsl_port_bug = 1;
  
  		if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
-@@ -382,16 +529,56 @@ static int ehci_fsl_setup(struct usb_hcd
+@@ -379,16 +530,57 @@ static int ehci_fsl_setup(struct usb_hcd
  	return retval;
  }
  
 -struct ehci_fsl {
 -	struct ehci_hcd	ehci;
--
+ 
  #ifdef CONFIG_PM
 -	/* Saved USB PHY settings, need to restore after deep sleep. */
 -	u32 usb_ctrl;
@@ -994,7 +1244,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  #ifdef CONFIG_PPC_MPC512x
  static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
-@@ -538,26 +725,45 @@ static inline int ehci_fsl_mpc512x_drv_r
+@@ -535,26 +727,45 @@ static inline int ehci_fsl_mpc512x_drv_r
  }
  #endif /* CONFIG_PPC_MPC512x */
  
@@ -1015,10 +1265,10 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#endif
 +
 +#ifdef CONFIG_PPC
-+	suspend_state_t pm_state;
-+	/* FIXME:Need to port fsl_pm.h before enable below code. */
-+	/*pm_state = pm_suspend_state();*/
-+	pm_state = PM_SUSPEND_MEM;
++suspend_state_t pm_state;
++/* FIXME:Need to port fsl_pm.h before enable below code. */
++/*pm_state = pm_suspend_state();*/
++pm_state = PM_SUSPEND_MEM;
 +
 +if (pm_state == PM_SUSPEND_MEM)
 +	ehci_fsl_save_context(hcd);
@@ -1047,7 +1297,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	if (!fsl_deep_sleep())
  		return 0;
  
-@@ -571,12 +777,36 @@ static int ehci_fsl_drv_resume(struct de
+@@ -568,12 +779,36 @@ static int ehci_fsl_drv_resume(struct de
  	struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  	void __iomem *non_ehci = hcd->regs;
@@ -1056,13 +1306,13 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +#endif
 +
 +#ifdef CONFIG_PPC
-+	suspend_state_t pm_state;
-+	/* FIXME:Need to port fsl_pm.h before enable below code.*/
-+	/* pm_state = pm_suspend_state(); */
-+	pm_state = PM_SUSPEND_MEM;
++suspend_state_t pm_state;
++/* FIXME:Need to port fsl_pm.h before enable below code.*/
++/* pm_state = pm_suspend_state(); */
++pm_state = PM_SUSPEND_MEM;
 +
-+	if (pm_state == PM_SUSPEND_MEM)
-+		ehci_fsl_restore_context(hcd);
++if (pm_state == PM_SUSPEND_MEM)
++	ehci_fsl_restore_context(hcd);
 +#endif
  
  	if (of_device_is_compatible(dev->parent->of_node,
@@ -1096,7 +1346,16 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  #endif				/* _EHCI_FSL_H */
 --- a/drivers/usb/host/ehci-hub.c
 +++ b/drivers/usb/host/ehci-hub.c
-@@ -305,6 +305,8 @@ static int ehci_bus_suspend (struct usb_
+@@ -278,6 +278,8 @@ static int ehci_bus_suspend (struct usb_
+ 		else if ((t1 & PORT_PE) && !(t1 & PORT_SUSPEND)) {
+ 			t2 |= PORT_SUSPEND;
+ 			set_bit(port, &ehci->bus_suspended);
++			if (ehci_has_fsl_susp_errata(ehci))
++				usleep_range(10000, 20000);
+ 		}
+ 
+ 		/* enable remote wakeup on all ports, if told to do so */
+@@ -305,6 +307,8 @@ static int ehci_bus_suspend (struct usb_
  						USB_PORT_STAT_HIGH_SPEED)
  				fs_idle_delay = true;
  			ehci_writel(ehci, t2, reg);
@@ -1117,12 +1376,49 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  
  	/* list of itds & sitds completed while now_frame was still active */
  	struct list_head	cached_itd_list;
+@@ -219,6 +222,7 @@ struct ehci_hcd {			/* one per controlle
+ 	unsigned		no_selective_suspend:1;
+ 	unsigned		has_fsl_port_bug:1; /* FreeScale */
+ 	unsigned		has_fsl_hs_errata:1;	/* Freescale HS quirk */
++	unsigned		has_fsl_susp_errata:1; /*Freescale SUSP quirk*/
+ 	unsigned		big_endian_mmio:1;
+ 	unsigned		big_endian_desc:1;
+ 	unsigned		big_endian_capbase:1;
+@@ -704,10 +708,15 @@ ehci_port_speed(struct ehci_hcd *ehci, u
+ #if defined(CONFIG_PPC_85xx)
+ /* Some Freescale processors have an erratum (USB A-005275) in which
+  * incoming packets get corrupted in HS mode
++ * Some Freescale processors have an erratum (USB A-005697) in which
++ * we need to wait for 10ms for bus to fo into suspend mode after
++ * setting SUSP bit
+  */
+ #define ehci_has_fsl_hs_errata(e)	((e)->has_fsl_hs_errata)
++#define ehci_has_fsl_susp_errata(e)     ((e)->has_fsl_susp_errata)
+ #else
+ #define ehci_has_fsl_hs_errata(e)	(0)
++#define ehci_has_fsl_susp_errata(e)     (0)
+ #endif
+ 
+ /*
 --- a/drivers/usb/host/fsl-mph-dr-of.c
 +++ b/drivers/usb/host/fsl-mph-dr-of.c
-@@ -229,6 +229,17 @@ static int fsl_usb2_mph_dr_of_probe(stru
- 	pdata->has_fsl_erratum_a005697 =
- 		of_property_read_bool(np, "fsl,usb_erratum-a005697");
+@@ -98,8 +98,8 @@ static struct platform_device *fsl_usb2_
  
+ 	pdev->dev.coherent_dma_mask = ofdev->dev.coherent_dma_mask;
+ 
+-	if (!pdev->dev.dma_mask)
+-		pdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
++	if (!pdev->dev.dma_mask && ofdev->dev.of_node)
++		of_dma_configure(&pdev->dev, ofdev->dev.of_node);
+ 	else
+ 		dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+ 
+@@ -226,6 +226,18 @@ static int fsl_usb2_mph_dr_of_probe(stru
+ 		of_property_read_bool(np, "fsl,usb-erratum-a007792");
+ 	pdata->has_fsl_erratum_a005275 =
+ 		of_property_read_bool(np, "fsl,usb-erratum-a005275");
++	pdata->has_fsl_erratum_a005697 =
++		of_property_read_bool(np, "fsl,usb_erratum-a005697");
 +	if (of_get_property(np, "fsl,erratum_a006918", NULL))
 +		pdata->has_fsl_erratum_a006918 = 1;
 +	else
@@ -1133,13 +1429,12 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +	else
 +		pdata->has_fsl_erratum_14 = 0;
 +
-+
+ 
  	/*
  	 * Determine whether phy_clk_valid needs to be checked
- 	 * by reading property in device tree
 --- a/drivers/usb/host/xhci-hub.c
 +++ b/drivers/usb/host/xhci-hub.c
-@@ -689,12 +689,34 @@ void xhci_set_link_state(struct xhci_hcd
+@@ -562,12 +562,34 @@ void xhci_set_link_state(struct xhci_hcd
  				int port_id, u32 link_state)
  {
  	u32 temp;
@@ -1176,14 +1471,14 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 --- a/drivers/usb/host/xhci-plat.c
 +++ b/drivers/usb/host/xhci-plat.c
-@@ -263,8 +263,22 @@ static int xhci_plat_probe(struct platfo
+@@ -220,8 +220,22 @@ static int xhci_plat_probe(struct platfo
  		goto disable_clk;
  	}
  
--	if (device_property_read_bool(sysdev, "usb3-lpm-capable"))
-+	if (device_property_read_bool(sysdev, "usb3-lpm-capable")) {
+-	if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable"))
++	if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable")) {
  		xhci->quirks |= XHCI_LPM_SUPPORT;
-+		if (device_property_read_bool(sysdev,
++		if (device_property_read_bool(&pdev->dev,
 +					"snps,dis-u1u2-when-u3-quirk"))
 +			xhci->quirks |= XHCI_DIS_U1U2_WHEN_U3;
 +	}
@@ -1202,41 +1497,46 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  		xhci->quirks |= XHCI_BROKEN_PORT_PED;
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -1969,10 +1969,12 @@ static int finish_td(struct xhci_hcd *xh
- 	union xhci_trb *ep_trb, struct xhci_transfer_event *event,
- 	struct xhci_virt_ep *ep, int *status)
+@@ -1852,14 +1852,17 @@ static int finish_td(struct xhci_hcd *xh
+ 	union xhci_trb *event_trb, struct xhci_transfer_event *event,
+ 	struct xhci_virt_ep *ep, int *status, bool skip)
  {
 +	struct xhci_dequeue_state deq_state;
  	struct xhci_virt_device *xdev;
- 	struct xhci_ep_ctx *ep_ctx;
  	struct xhci_ring *ep_ring;
++	unsigned int stream_id;
  	unsigned int slot_id;
+ 	int ep_index;
+ 	struct urb *urb = NULL;
+ 	struct xhci_ep_ctx *ep_ctx;
+ 	int ret = 0;
+ 	struct urb_priv	*urb_priv;
 +	u32 remaining;
  	u32 trb_comp_code;
- 	int ep_index;
  
-@@ -1995,14 +1997,30 @@ static int finish_td(struct xhci_hcd *xh
- 	if (trb_comp_code == COMP_STALL_ERROR ||
+ 	slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
+@@ -1885,13 +1888,29 @@ static int finish_td(struct xhci_hcd *xh
+ 	if (trb_comp_code == COMP_STALL ||
  		xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
  						trb_comp_code)) {
 -		/* Issue a reset endpoint command to clear the host side
 -		 * halt, followed by a set dequeue command to move the
 -		 * dequeue pointer past the TD.
 -		 * The class driver clears the device side halt later.
-+		/*erratum A-007463:
-+		 *After transaction error, controller switches control transfer
-+		 *data stage from IN to OUT direction.
++		/*
++		 * A-007463: After transaction error, controller switches
++		 * control transfer data stage from IN to OUT direction.
  		 */
 -		xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
 +		remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
 +		if (remaining && xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
-+				trb_comp_code) &&
-+				(xhci->quirks & XHCI_REVERSE_IN_OUT)) {
++					trb_comp_code) &&
++					(xhci->quirks & XHCI_REVERSE_IN_OUT)) {
 +			memset(&deq_state, 0, sizeof(deq_state));
 +			xhci_find_new_dequeue_state(xhci, slot_id,
 +				ep_index, td->urb->stream_id, td, &deq_state);
 +			xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
-+						&deq_state);
++							stream_id, &deq_state);
 +			xhci_ring_cmd_db(xhci);
 +		} else {
 +			/* Issue a reset endpoint command to clear the host side
@@ -1245,31 +1545,31 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +			 * The class driver clears the device side halt later.
 +			 */
 +			xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
- 					ep_ring->stream_id, td, ep_trb,
- 					EP_HARD_RESET);
+ 					ep_ring->stream_id, td, event_trb);
 +		}
  	} else {
  		/* Update ring dequeue pointer */
  		while (ep_ring->dequeue != td->last_trb)
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
-@@ -1599,13 +1599,38 @@ static int xhci_urb_dequeue(struct usb_h
+@@ -1609,14 +1609,38 @@ int xhci_urb_dequeue(struct usb_hcd *hcd
  			ret = -ENOMEM;
  			goto done;
  		}
--		ep->ep_state |= EP_STOP_CMD_PENDING;
+-		ep->ep_state |= EP_HALT_PENDING;
+-		ep->stop_cmds_pending++;
 -		ep->stop_cmd_timer.expires = jiffies +
 +		/*
-+		 *erratum A-009611: Issuing an End Transfer command on an IN
-+		 *endpoint. when a transfer is in progress on USB blocks the
-+		 *transmission.
++		 *A-009611: Issuing an End Transfer command on an IN endpoint.
++		 *when a transfer is in progress on USB blocks the transmission
 +		 *Workaround: Software must wait for all existing TRBs to
 +		 *complete before issuing End transfer command.
 +		 */
 +		if ((ep_ring->enqueue == ep_ring->dequeue &&
 +				(xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) ||
 +				!(xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) {
-+			ep->ep_state |= EP_STOP_CMD_PENDING;
++			ep->ep_state |= EP_HALT_PENDING;
++			ep->stop_cmds_pending++;
 +			ep->stop_cmd_timer.expires = jiffies +
  			XHCI_STOP_EP_CMD_TIMEOUT * HZ;
 -		add_timer(&ep->stop_cmd_timer);
@@ -1284,7 +1584,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		}
 +
 +		/*
-+		 *erratum A-009668: Stop Endpoint Command does not complete.
++		 *A-009668: Stop Endpoint Command does not complete.
 +		 *Workaround: Instead of issuing a Stop Endpoint Command,
 +		 *issue a Disable Slot Command with the corresponding slot ID.
 +		 *Alternately, you can issue an Address Device Command with
@@ -1293,49 +1593,33 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 +		if ((urb->dev->speed <= USB_SPEED_HIGH) &&
 +					(xhci->quirks & XHCI_STOP_EP_IN_U1)) {
 +			xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
-+				urb->dev->slot_id);
++					urb->dev->slot_id);
 +		}
  	}
  done:
  	spin_unlock_irqrestore(&xhci->lock, flags);
-@@ -4990,7 +5015,7 @@ int xhci_gen_setup(struct usb_hcd *hcd,
- 		return retval;
- 	xhci_dbg(xhci, "Called HCD init\n");
- 
--	xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
-+	xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%llx\n",
- 		  xhci->hcc_params, xhci->hci_version, xhci->quirks);
- 
- 	return 0;
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1794,7 +1794,7 @@ struct xhci_hcd {
- #define XHCI_STATE_DYING	(1 << 0)
- #define XHCI_STATE_HALTED	(1 << 1)
+@@ -1625,7 +1625,7 @@ struct xhci_hcd {
  #define XHCI_STATE_REMOVING	(1 << 2)
--	unsigned long long	quirks;
-+	u64		quirks;
- #define	XHCI_LINK_TRB_QUIRK	BIT_ULL(0)
- #define XHCI_RESET_EP_QUIRK	BIT_ULL(1)
- #define XHCI_NEC_HOST		BIT_ULL(2)
-@@ -1830,6 +1830,9 @@ struct xhci_hcd {
- #define XHCI_SSIC_PORT_UNUSED	BIT_ULL(22)
- #define XHCI_NO_64BIT_SUPPORT	BIT_ULL(23)
- #define XHCI_MISSING_CAS	BIT_ULL(24)
-+#define XHCI_REVERSE_IN_OUT     BIT(32)
-+#define XHCI_STOP_TRANSFER_IN_BLOCK   BIT(33)
-+#define XHCI_STOP_EP_IN_U1     BIT(34)
+ 	/* Statistics */
+ 	int			error_bitmask;
+-	unsigned int		quirks;
++	u64			quirks;
+ #define	XHCI_LINK_TRB_QUIRK	(1 << 0)
+ #define XHCI_RESET_EP_QUIRK	(1 << 1)
+ #define XHCI_NEC_HOST		(1 << 2)
+@@ -1661,6 +1661,10 @@ struct xhci_hcd {
+ #define XHCI_SSIC_PORT_UNUSED	(1 << 22)
+ #define XHCI_NO_64BIT_SUPPORT	(1 << 23)
+ #define XHCI_MISSING_CAS	(1 << 24)
++#define XHCI_REVERSE_IN_OUT    (1 << 29)
++#define XHCI_STOP_TRANSFER_IN_BLOCK    (1 << 30)
++#define XHCI_STOP_EP_IN_U1    (1 << 31)
++#define XHCI_DIS_U1U2_WHEN_U3 (1 << 32)
  /* For controller with a broken Port Disable implementation */
- #define XHCI_BROKEN_PORT_PED	BIT_ULL(25)
- #define XHCI_LIMIT_ENDPOINT_INTERVAL_7	BIT_ULL(26)
-@@ -1840,6 +1843,7 @@ struct xhci_hcd {
- #define XHCI_INTEL_USB_ROLE_SW	BIT_ULL(31)
- #define XHCI_RESET_PLL_ON_DISCONNECT	BIT_ULL(34)
- #define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
-+#define XHCI_DIS_U1U2_WHEN_U3 BIT(36)
- 
- 	unsigned int		num_active_eps;
- 	unsigned int		limit_active_eps;
+ #define XHCI_BROKEN_PORT_PED	(1 << 25)
+ #define XHCI_LIMIT_ENDPOINT_INTERVAL_7	(1 << 26)
 --- a/drivers/usb/phy/phy-fsl-usb.c
 +++ b/drivers/usb/phy/phy-fsl-usb.c
 @@ -1,5 +1,5 @@
@@ -1345,7 +1629,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
   *
   * Author: Li Yang <LeoLi@freescale.com>
   *         Jerry Huang <Chang-Ming.Huang@freescale.com>
-@@ -470,6 +470,7 @@ void otg_reset_controller(void)
+@@ -463,6 +463,7 @@ void otg_reset_controller(void)
  int fsl_otg_start_host(struct otg_fsm *fsm, int on)
  {
  	struct usb_otg *otg = fsm->otg;
@@ -1353,7 +1637,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	struct device *dev;
  	struct fsl_otg *otg_dev =
  		container_of(otg->usb_phy, struct fsl_otg, phy);
-@@ -493,6 +494,7 @@ int fsl_otg_start_host(struct otg_fsm *f
+@@ -486,6 +487,7 @@ int fsl_otg_start_host(struct otg_fsm *f
  			otg_reset_controller();
  			VDBG("host on......\n");
  			if (dev->driver->pm && dev->driver->pm->resume) {
@@ -1361,7 +1645,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  				retval = dev->driver->pm->resume(dev);
  				if (fsm->id) {
  					/* default-b */
-@@ -517,8 +519,11 @@ int fsl_otg_start_host(struct otg_fsm *f
+@@ -510,8 +512,11 @@ int fsl_otg_start_host(struct otg_fsm *f
  		else {
  			VDBG("host off......\n");
  			if (dev && dev->driver) {
@@ -1374,7 +1658,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  				if (fsm->id)
  					/* default-b */
  					fsl_otg_drv_vbus(fsm, 0);
-@@ -546,8 +551,17 @@ int fsl_otg_start_gadget(struct otg_fsm
+@@ -539,8 +544,17 @@ int fsl_otg_start_gadget(struct otg_fsm
  	dev = otg->gadget->dev.parent;
  
  	if (on) {
@@ -1393,7 +1677,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	} else {
  		if (dev->driver->suspend)
  			dev->driver->suspend(dev, otg_suspend_state);
-@@ -668,6 +682,10 @@ static void fsl_otg_event(struct work_st
+@@ -672,6 +686,10 @@ static void fsl_otg_event(struct work_st
  		fsl_otg_start_host(fsm, 0);
  		otg_drv_vbus(fsm, 0);
  		fsl_otg_start_gadget(fsm, 1);
@@ -1404,7 +1688,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	}
  }
  
-@@ -720,6 +738,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
+@@ -724,6 +742,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
  {
  	struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
  	struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
@@ -1412,7 +1696,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  	u32 otg_int_src, otg_sc;
  
  	otg_sc = fsl_readl(&usb_dr_regs->otgsc);
-@@ -749,18 +768,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
+@@ -753,18 +772,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
  				otg->gadget->is_a_peripheral = !fsm->id;
  			VDBG("ID int (ID is %d)\n", fsm->id);
  
@@ -1433,7 +1717,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  			return IRQ_HANDLED;
  		}
  	}
-@@ -920,12 +929,32 @@ int usb_otg_start(struct platform_device
+@@ -925,12 +934,32 @@ int usb_otg_start(struct platform_device
  	temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
  	switch (pdata->phy_mode) {
  	case FSL_USB2_PHY_ULPI:
@@ -1485,7 +1769,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  #define BCSR5_INT_USB			(0x02)
 --- a/include/linux/usb.h
 +++ b/include/linux/usb.h
-@@ -434,6 +434,7 @@ struct usb_bus {
+@@ -362,6 +362,7 @@ struct usb_bus {
  					 * for control transfers?
  					 */
  	u8 otg_port;			/* 0, or number of OTG/HNP port */
diff --git a/target/linux/layerscape/patches-4.14/808-vfio-support-layerscape.patch b/target/linux/layerscape/patches-4.9/818-vfio-support-layerscape.patch
similarity index 89%
rename from target/linux/layerscape/patches-4.14/808-vfio-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/818-vfio-support-layerscape.patch
index 9083c70ca..f2a65ffba 100644
--- a/target/linux/layerscape/patches-4.14/808-vfio-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/818-vfio-support-layerscape.patch
@@ -1,21 +1,26 @@
-From 92f0ef51270b2961f63b2e985831f5e9a6251a2f Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:29:03 +0800
-Subject: [PATCH 25/40] vfio: support layerscape
-This is an integrated patch of vfio for layerscape
+From e6af99cc1d56322fc960d072af1a7e0e9285b90c Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:39:43 +0800
+Subject: [PATCH 30/32] vfio: support layerscape
+
+This is an integrated patch for layerscape vfio support.
 
 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
+Signed-off-by: Robin Murphy <robin.murphy@arm.com>
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
  drivers/vfio/Kconfig                      |   1 +
  drivers/vfio/Makefile                     |   1 +
  drivers/vfio/fsl-mc/Kconfig               |   9 +
  drivers/vfio/fsl-mc/Makefile              |   2 +
- drivers/vfio/fsl-mc/vfio_fsl_mc.c         | 751 ++++++++++++++++++++++
+ drivers/vfio/fsl-mc/vfio_fsl_mc.c         | 752 ++++++++++++++++++++++
  drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c    | 199 ++++++
  drivers/vfio/fsl-mc/vfio_fsl_mc_private.h |  55 ++
+ drivers/vfio/vfio_iommu_type1.c           |  39 +-
  include/uapi/linux/vfio.h                 |   1 +
- 8 files changed, 1019 insertions(+)
+ 9 files changed, 1057 insertions(+), 2 deletions(-)
  create mode 100644 drivers/vfio/fsl-mc/Kconfig
  create mode 100644 drivers/vfio/fsl-mc/Makefile
  create mode 100644 drivers/vfio/fsl-mc/vfio_fsl_mc.c
@@ -24,18 +29,18 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 
 --- a/drivers/vfio/Kconfig
 +++ b/drivers/vfio/Kconfig
-@@ -47,4 +47,5 @@ menuconfig VFIO_NOIOMMU
+@@ -48,4 +48,5 @@ menuconfig VFIO_NOIOMMU
+ 
  source "drivers/vfio/pci/Kconfig"
  source "drivers/vfio/platform/Kconfig"
- source "drivers/vfio/mdev/Kconfig"
 +source "drivers/vfio/fsl-mc/Kconfig"
  source "virt/lib/Kconfig"
 --- a/drivers/vfio/Makefile
 +++ b/drivers/vfio/Makefile
-@@ -9,3 +9,4 @@ obj-$(CONFIG_VFIO_SPAPR_EEH) += vfio_spa
+@@ -7,3 +7,4 @@ obj-$(CONFIG_VFIO_IOMMU_SPAPR_TCE) += vf
+ obj-$(CONFIG_VFIO_SPAPR_EEH) += vfio_spapr_eeh.o
  obj-$(CONFIG_VFIO_PCI) += pci/
  obj-$(CONFIG_VFIO_PLATFORM) += platform/
- obj-$(CONFIG_VFIO_MDEV) += mdev/
 +obj-$(CONFIG_VFIO_FSL_MC) += fsl-mc/
 --- /dev/null
 +++ b/drivers/vfio/fsl-mc/Kconfig
@@ -56,7 +61,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +obj-$(CONFIG_VFIO_FSL_MC) += vfio_fsl_mc.o vfio_fsl_mc_intr.o
 --- /dev/null
 +++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
-@@ -0,0 +1,751 @@
+@@ -0,0 +1,752 @@
 +/*
 + * Freescale Management Complex (MC) device passthrough using VFIO
 + *
@@ -77,6 +82,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +#include <linux/types.h>
 +#include <linux/vfio.h>
 +#include <linux/delay.h>
++
 +#include <linux/fsl/mc.h>
 +
 +#include "vfio_fsl_mc_private.h"
@@ -1068,12 +1074,91 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +			       unsigned int start, unsigned int count,
 +			       void *data);
 +#endif /* VFIO_PCI_PRIVATE_H */
+--- a/drivers/vfio/vfio_iommu_type1.c
++++ b/drivers/vfio/vfio_iommu_type1.c
+@@ -36,6 +36,8 @@
+ #include <linux/uaccess.h>
+ #include <linux/vfio.h>
+ #include <linux/workqueue.h>
++#include <linux/dma-iommu.h>
++#include <linux/irqdomain.h>
+ 
+ #define DRIVER_VERSION  "0.2"
+ #define DRIVER_AUTHOR   "Alex Williamson <alex.williamson@redhat.com>"
+@@ -720,6 +722,27 @@ static void vfio_test_domain_fgsp(struct
+ 	__free_pages(pages, order);
+ }
+ 
++static bool vfio_iommu_has_sw_msi(struct iommu_group *group, phys_addr_t *base)
++{
++	struct list_head group_resv_regions;
++	struct iommu_resv_region *region, *next;
++	bool ret = false;
++
++	INIT_LIST_HEAD(&group_resv_regions);
++	iommu_get_group_resv_regions(group, &group_resv_regions);
++	list_for_each_entry(region, &group_resv_regions, list) {
++		if (region->type == IOMMU_RESV_SW_MSI) {
++			*base = region->start;
++			ret = true;
++			goto out;
++		}
++	}
++out:
++	list_for_each_entry_safe(region, next, &group_resv_regions, list)
++		kfree(region);
++	return ret;
++}
++
+ static int vfio_iommu_type1_attach_group(void *iommu_data,
+ 					 struct iommu_group *iommu_group)
+ {
+@@ -728,6 +751,8 @@ static int vfio_iommu_type1_attach_group
+ 	struct vfio_domain *domain, *d;
+ 	struct bus_type *bus = NULL;
+ 	int ret;
++	bool resv_msi, msi_remap;
++	phys_addr_t resv_msi_base;
+ 
+ 	mutex_lock(&iommu->lock);
+ 
+@@ -774,11 +799,15 @@ static int vfio_iommu_type1_attach_group
+ 	if (ret)
+ 		goto out_domain;
+ 
++	resv_msi = vfio_iommu_has_sw_msi(iommu_group, &resv_msi_base);
++
+ 	INIT_LIST_HEAD(&domain->group_list);
+ 	list_add(&group->next, &domain->group_list);
+ 
+-	if (!allow_unsafe_interrupts &&
+-	    !iommu_capable(bus, IOMMU_CAP_INTR_REMAP)) {
++	msi_remap = resv_msi ? irq_domain_check_msi_remap() :
++				iommu_capable(bus, IOMMU_CAP_INTR_REMAP);
++
++	if (!allow_unsafe_interrupts && !msi_remap) {
+ 		pr_warn("%s: No interrupt remapping support.  Use the module param \"allow_unsafe_interrupts\" to enable VFIO IOMMU support on this platform\n",
+ 		       __func__);
+ 		ret = -EPERM;
+@@ -820,6 +849,12 @@ static int vfio_iommu_type1_attach_group
+ 	if (ret)
+ 		goto out_detach;
+ 
++	if (resv_msi) {
++		ret = iommu_get_msi_cookie(domain->domain, resv_msi_base);
++		if (ret)
++			goto out_detach;
++	}
++
+ 	list_add(&domain->next, &iommu->domain_list);
+ 
+ 	mutex_unlock(&iommu->lock);
 --- a/include/uapi/linux/vfio.h
 +++ b/include/uapi/linux/vfio.h
-@@ -200,6 +200,7 @@ struct vfio_device_info {
+@@ -198,6 +198,7 @@ struct vfio_device_info {
+ #define VFIO_DEVICE_FLAGS_PCI	(1 << 1)	/* vfio-pci device */
  #define VFIO_DEVICE_FLAGS_PLATFORM (1 << 2)	/* vfio-platform device */
  #define VFIO_DEVICE_FLAGS_AMBA  (1 << 3)	/* vfio-amba device */
- #define VFIO_DEVICE_FLAGS_CCW	(1 << 4)	/* vfio-ccw device */
 +#define VFIO_DEVICE_FLAGS_FSL_MC (1 << 5)	/* vfio-fsl-mc device */
  	__u32	num_regions;	/* Max region index + 1 */
  	__u32	num_irqs;	/* Max IRQ index + 1 */
diff --git a/target/linux/layerscape/patches-4.14/809-flexcan-support-layerscape.patch b/target/linux/layerscape/patches-4.9/819-flexcan-support-layerscape.patch
similarity index 63%
rename from target/linux/layerscape/patches-4.14/809-flexcan-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/819-flexcan-support-layerscape.patch
index a52b8b516..5b0b3fd88 100644
--- a/target/linux/layerscape/patches-4.14/809-flexcan-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/819-flexcan-support-layerscape.patch
@@ -1,30 +1,30 @@
-From 3ed707fde8a33f2b888f75ac2f5e0a98e7774dad Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:27 +0800
-Subject: [PATCH 26/40] flexcan: support layerscape
-This is an integrated patch of flexcan for layerscape
+From 2887442bd13bc8be687afc7172cb01c2b7f0dd3b Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:41:14 +0800
+Subject: [PATCH 31/32] flexcan: support layerscape
+
+This is an integrated patch for layerscape flexcan support.
 
-Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
-Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
 Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
+Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
 Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
-Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
- drivers/net/can/flexcan.c | 240 ++++++++++++++++++++++----------------
- 1 file changed, 138 insertions(+), 102 deletions(-)
+ drivers/net/can/flexcan.c | 212 ++++++++++++++++++++++----------------
+ 1 file changed, 123 insertions(+), 89 deletions(-)
 
 --- a/drivers/net/can/flexcan.c
 +++ b/drivers/net/can/flexcan.c
-@@ -190,6 +190,7 @@
-  *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
-  *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
-  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
+@@ -184,6 +184,7 @@
+  *   MX53  FlexCAN2  03.00.00.00    yes        no         no        no
+  *   MX6s  FlexCAN3  10.00.12.00    yes       yes         no       yes
+  *   VF610 FlexCAN3  ?               no       yes        yes       yes?
 + * LS1021A FlexCAN2  03.00.04.00     no       yes         no       yes
   *
   * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
   */
-@@ -279,6 +280,10 @@ struct flexcan_priv {
- 	struct clk *clk_per;
+@@ -260,6 +261,10 @@ struct flexcan_priv {
+ 	struct flexcan_platform_data *pdata;
  	const struct flexcan_devtype_data *devtype_data;
  	struct regulator *reg_xceiver;
 +
@@ -33,20 +33,19 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	void (*write)(u32 val, void __iomem *addr);
  };
  
- static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
-@@ -301,6 +306,11 @@ static const struct flexcan_devtype_data
- 		FLEXCAN_QUIRK_BROKEN_PERR_STATE,
+ static struct flexcan_devtype_data fsl_p1010_devtype_data = {
+@@ -276,6 +281,10 @@ static struct flexcan_devtype_data fsl_v
+ 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
  };
  
 +static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
-+	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
-+		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
++	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
 +};
 +
  static const struct can_bittiming_const flexcan_bittiming_const = {
  	.name = DRV_NAME,
  	.tseg1_min = 4,
-@@ -313,39 +323,45 @@ static const struct can_bittiming_const
+@@ -288,32 +297,38 @@ static const struct can_bittiming_const
  	.brp_inc = 1,
  };
  
@@ -98,26 +97,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  }
 -#endif
  
- static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
- {
- 	struct flexcan_regs __iomem *regs = priv->regs;
- 	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
- 
--	flexcan_write(reg_ctrl, &regs->ctrl);
-+	priv->write(reg_ctrl, &regs->ctrl);
- }
- 
- static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
-@@ -353,7 +369,7 @@ static inline void flexcan_error_irq_dis
- 	struct flexcan_regs __iomem *regs = priv->regs;
- 	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
- 
--	flexcan_write(reg_ctrl, &regs->ctrl);
-+	priv->write(reg_ctrl, &regs->ctrl);
- }
- 
  static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
-@@ -378,14 +394,14 @@ static int flexcan_chip_enable(struct fl
+ {
+@@ -344,14 +359,14 @@ static int flexcan_chip_enable(struct fl
  	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
  	u32 reg;
  
@@ -136,7 +118,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  		return -ETIMEDOUT;
  
  	return 0;
-@@ -397,14 +413,14 @@ static int flexcan_chip_disable(struct f
+@@ -363,14 +378,14 @@ static int flexcan_chip_disable(struct f
  	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
  	u32 reg;
  
@@ -155,7 +137,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  		return -ETIMEDOUT;
  
  	return 0;
-@@ -416,14 +432,14 @@ static int flexcan_chip_freeze(struct fl
+@@ -382,14 +397,14 @@ static int flexcan_chip_freeze(struct fl
  	unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
  	u32 reg;
  
@@ -174,7 +156,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  		return -ETIMEDOUT;
  
  	return 0;
-@@ -435,14 +451,14 @@ static int flexcan_chip_unfreeze(struct
+@@ -401,14 +416,14 @@ static int flexcan_chip_unfreeze(struct
  	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
  	u32 reg;
  
@@ -193,7 +175,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  		return -ETIMEDOUT;
  
  	return 0;
-@@ -453,11 +469,11 @@ static int flexcan_chip_softreset(struct
+@@ -419,11 +434,11 @@ static int flexcan_chip_softreset(struct
  	struct flexcan_regs __iomem *regs = priv->regs;
  	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
  
@@ -208,7 +190,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  		return -ETIMEDOUT;
  
  	return 0;
-@@ -468,7 +484,7 @@ static int __flexcan_get_berr_counter(co
+@@ -434,7 +449,7 @@ static int __flexcan_get_berr_counter(co
  {
  	const struct flexcan_priv *priv = netdev_priv(dev);
  	struct flexcan_regs __iomem *regs = priv->regs;
@@ -217,68 +199,49 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  	bec->txerr = (reg >> 0) & 0xff;
  	bec->rxerr = (reg >> 8) & 0xff;
-@@ -524,24 +540,24 @@ static int flexcan_start_xmit(struct sk_
+@@ -491,24 +506,24 @@ static int flexcan_start_xmit(struct sk_
  
  	if (cf->can_dlc > 0) {
  		data = be32_to_cpup((__be32 *)&cf->data[0]);
--		flexcan_write(data, &priv->tx_mb->data[0]);
-+		priv->write(data, &priv->tx_mb->data[0]);
+-		flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);
++		priv->write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[0]);
  	}
  	if (cf->can_dlc > 4) {
  		data = be32_to_cpup((__be32 *)&cf->data[4]);
--		flexcan_write(data, &priv->tx_mb->data[1]);
-+		priv->write(data, &priv->tx_mb->data[1]);
+-		flexcan_write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);
++		priv->write(data, &regs->mb[FLEXCAN_TX_BUF_ID].data[1]);
  	}
  
  	can_put_echo_skb(skb, dev, 0);
  
--	flexcan_write(can_id, &priv->tx_mb->can_id);
--	flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
-+	priv->write(can_id, &priv->tx_mb->can_id);
-+	priv->write(ctrl, &priv->tx_mb->can_ctrl);
+-	flexcan_write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);
+-	flexcan_write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
++	priv->write(can_id, &regs->mb[FLEXCAN_TX_BUF_ID].can_id);
++	priv->write(ctrl, &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
  
  	/* Errata ERR005829 step8:
  	 * Write twice INACTIVE(0x8) code to first MB.
  	 */
 -	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
 +	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
- 		      &priv->tx_mb_reserved->can_ctrl);
+ 		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
 -	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
 +	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
- 		      &priv->tx_mb_reserved->can_ctrl);
+ 		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
  
  	return NETDEV_TX_OK;
-@@ -660,7 +676,7 @@ static unsigned int flexcan_mailbox_read
- 		u32 code;
- 
- 		do {
--			reg_ctrl = flexcan_read(&mb->can_ctrl);
-+			reg_ctrl = priv->read(&mb->can_ctrl);
- 		} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
- 
- 		/* is this MB empty? */
-@@ -675,17 +691,17 @@ static unsigned int flexcan_mailbox_read
- 			offload->dev->stats.rx_errors++;
- 		}
- 	} else {
--		reg_iflag1 = flexcan_read(&regs->iflag1);
-+		reg_iflag1 = priv->read(&regs->iflag1);
- 		if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
- 			return 0;
- 
--		reg_ctrl = flexcan_read(&mb->can_ctrl);
-+		reg_ctrl = priv->read(&mb->can_ctrl);
- 	}
- 
- 	/* increase timstamp to full 32 bit */
- 	*timestamp = reg_ctrl << 16;
+@@ -632,8 +647,8 @@ static void flexcan_read_fifo(const stru
+ 	struct flexcan_mb __iomem *mb = &regs->mb[0];
+ 	u32 reg_ctrl, reg_id;
  
+-	reg_ctrl = flexcan_read(&mb->can_ctrl);
 -	reg_id = flexcan_read(&mb->can_id);
++	reg_ctrl = priv->read(&mb->can_ctrl);
 +	reg_id = priv->read(&mb->can_id);
  	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
  		cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
  	else
-@@ -695,19 +711,19 @@ static unsigned int flexcan_mailbox_read
+@@ -643,12 +658,12 @@ static void flexcan_read_fifo(const stru
  		cf->can_id |= CAN_RTR_FLAG;
  	cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
  
@@ -288,77 +251,94 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	*(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
  
  	/* mark as read */
- 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
- 		/* Clear IRQ */
- 		if (n < 32)
--			flexcan_write(BIT(n), &regs->iflag1);
-+			priv->write(BIT(n), &regs->iflag1);
- 		else
--			flexcan_write(BIT(n - 32), &regs->iflag2);
-+			priv->write(BIT(n - 32), &regs->iflag2);
- 	} else {
--		flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
--		flexcan_read(&regs->timer);
-+		priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
-+		priv->read(&regs->timer);
- 	}
+-	flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
+-	flexcan_read(&regs->timer);
++	priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
++	priv->read(&regs->timer);
+ }
  
- 	return 1;
-@@ -719,8 +735,8 @@ static inline u64 flexcan_read_reg_iflag
- 	struct flexcan_regs __iomem *regs = priv->regs;
- 	u32 iflag1, iflag2;
+ static int flexcan_read_frame(struct net_device *dev)
+@@ -685,17 +700,17 @@ static int flexcan_poll(struct napi_stru
+ 	/* The error bits are cleared on read,
+ 	 * use saved value from irq handler.
+ 	 */
+-	reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
++	reg_esr = priv->read(&regs->esr) | priv->reg_esr;
  
--	iflag2 = flexcan_read(&regs->iflag2) & priv->reg_imask2_default;
--	iflag1 = flexcan_read(&regs->iflag1) & priv->reg_imask1_default &
-+	iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default;
-+	iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default &
- 		~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
- 
- 	return (u64)iflag2 << 32 | iflag1;
-@@ -736,7 +752,7 @@ static irqreturn_t flexcan_irq(int irq,
- 	u32 reg_iflag1, reg_esr;
- 	enum can_state last_state = priv->can.state;
+ 	/* handle state changes */
+ 	work_done += flexcan_poll_state(dev, reg_esr);
  
+ 	/* handle RX-FIFO */
 -	reg_iflag1 = flexcan_read(&regs->iflag1);
 +	reg_iflag1 = priv->read(&regs->iflag1);
+ 	while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
+ 	       work_done < quota) {
+ 		work_done += flexcan_read_frame(dev);
+-		reg_iflag1 = flexcan_read(&regs->iflag1);
++		reg_iflag1 = priv->read(&regs->iflag1);
+ 	}
  
- 	/* reception interrupt */
- 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
-@@ -759,7 +775,8 @@ static irqreturn_t flexcan_irq(int irq,
- 		/* FIFO overflow interrupt */
- 		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
- 			handled = IRQ_HANDLED;
--			flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
-+			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
-+				    &regs->iflag1);
- 			dev->stats.rx_over_errors++;
- 			dev->stats.rx_errors++;
- 		}
-@@ -773,18 +790,18 @@ static irqreturn_t flexcan_irq(int irq,
+ 	/* report bus errors */
+@@ -705,8 +720,8 @@ static int flexcan_poll(struct napi_stru
+ 	if (work_done < quota) {
+ 		napi_complete_done(napi, work_done);
+ 		/* enable IRQs */
+-		flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
+-		flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
++		priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
++		priv->write(priv->reg_ctrl_default, &regs->ctrl);
+ 	}
+ 
+ 	return work_done;
+@@ -720,12 +735,12 @@ static irqreturn_t flexcan_irq(int irq,
+ 	struct flexcan_regs __iomem *regs = priv->regs;
+ 	u32 reg_iflag1, reg_esr;
+ 
+-	reg_iflag1 = flexcan_read(&regs->iflag1);
+-	reg_esr = flexcan_read(&regs->esr);
++	reg_iflag1 = priv->read(&regs->iflag1);
++	reg_esr = priv->read(&regs->esr);
+ 
+ 	/* ACK all bus error and state change IRQ sources */
+ 	if (reg_esr & FLEXCAN_ESR_ALL_INT)
+-		flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
++		priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+ 
+ 	/* schedule NAPI in case of:
+ 	 * - rx IRQ
+@@ -739,16 +754,16 @@ static irqreturn_t flexcan_irq(int irq,
+ 		 * save them for later use.
+ 		 */
+ 		priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
+-		flexcan_write(FLEXCAN_IFLAG_DEFAULT &
++		priv->write(FLEXCAN_IFLAG_DEFAULT &
+ 			      ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
+-		flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
++		priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+ 			      &regs->ctrl);
+ 		napi_schedule(&priv->napi);
+ 	}
+ 
+ 	/* FIFO overflow */
+ 	if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
+-		flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
++		priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
+ 		dev->stats.rx_over_errors++;
+ 		dev->stats.rx_errors++;
+ 	}
+@@ -760,9 +775,9 @@ static irqreturn_t flexcan_irq(int irq,
  		can_led_event(dev, CAN_LED_EVENT_TX);
  
  		/* after sending a RTR frame MB is in RX mode */
 -		flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
--			      &priv->tx_mb->can_ctrl);
--		flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
 +		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
-+			    &priv->tx_mb->can_ctrl);
-+		priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag1);
+ 			      &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
+-		flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
++		priv->write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
  		netif_wake_queue(dev);
  	}
  
--	reg_esr = flexcan_read(&regs->esr);
-+	reg_esr = priv->read(&regs->esr);
- 
- 	/* ACK all bus error and state change IRQ sources */
- 	if (reg_esr & FLEXCAN_ESR_ALL_INT) {
- 		handled = IRQ_HANDLED;
--		flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
-+		priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
- 	}
- 
- 	/* state change interrupt or broken error state quirk fix is enabled */
-@@ -846,7 +863,7 @@ static void flexcan_set_bittiming(struct
+@@ -776,7 +791,7 @@ static void flexcan_set_bittiming(struct
  	struct flexcan_regs __iomem *regs = priv->regs;
  	u32 reg;
  
@@ -367,7 +347,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
  		 FLEXCAN_CTRL_RJW(0x3) |
  		 FLEXCAN_CTRL_PSEG1(0x7) |
-@@ -870,11 +887,11 @@ static void flexcan_set_bittiming(struct
+@@ -800,11 +815,11 @@ static void flexcan_set_bittiming(struct
  		reg |= FLEXCAN_CTRL_SMP;
  
  	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
@@ -381,25 +361,23 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  }
  
  /* flexcan_chip_start
-@@ -913,7 +930,7 @@ static int flexcan_chip_start(struct net
+@@ -842,13 +857,13 @@ static int flexcan_chip_start(struct net
  	 * choose format C
  	 * set max mailbox number
  	 */
 -	reg_mcr = flexcan_read(&regs->mcr);
 +	reg_mcr = priv->read(&regs->mcr);
  	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
- 	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
- 		FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
-@@ -927,7 +944,7 @@ static int flexcan_chip_start(struct net
- 			FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
- 	}
+ 	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
+ 		FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS |
+ 		FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
  	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 -	flexcan_write(reg_mcr, &regs->mcr);
 +	priv->write(reg_mcr, &regs->mcr);
  
  	/* CTRL
  	 *
-@@ -940,7 +957,7 @@ static int flexcan_chip_start(struct net
+@@ -861,7 +876,7 @@ static int flexcan_chip_start(struct net
  	 * enable bus off interrupt
  	 * (== FLEXCAN_CTRL_ERR_STATE)
  	 */
@@ -408,48 +386,29 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
  	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
  		FLEXCAN_CTRL_ERR_STATE;
-@@ -960,45 +977,45 @@ static int flexcan_chip_start(struct net
+@@ -881,29 +896,29 @@ static int flexcan_chip_start(struct net
  	/* leave interrupts disabled for now */
  	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
  	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
 -	flexcan_write(reg_ctrl, &regs->ctrl);
 +	priv->write(reg_ctrl, &regs->ctrl);
  
- 	if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
--		reg_ctrl2 = flexcan_read(&regs->ctrl2);
-+		reg_ctrl2 = priv->read(&regs->ctrl2);
- 		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
--		flexcan_write(reg_ctrl2, &regs->ctrl2);
-+		priv->write(reg_ctrl2, &regs->ctrl2);
- 	}
- 
  	/* clear and invalidate all mailboxes first */
- 	for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
+ 	for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->mb); i++) {
 -		flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
--			      &regs->mb[i].can_ctrl);
 +		priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
-+			    &regs->mb[i].can_ctrl);
- 	}
- 
- 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
- 		for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
--			flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
--				      &regs->mb[i].can_ctrl);
-+			priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
-+				    &regs->mb[i].can_ctrl);
+ 			      &regs->mb[i].can_ctrl);
  	}
  
  	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
 -	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
--		      &priv->tx_mb_reserved->can_ctrl);
 +	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
-+		    &priv->tx_mb_reserved->can_ctrl);
+ 		      &regs->mb[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
  
  	/* mark TX mailbox as INACTIVE */
 -	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
--		      &priv->tx_mb->can_ctrl);
 +	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
-+		    &priv->tx_mb->can_ctrl);
+ 		      &regs->mb[FLEXCAN_TX_BUF_ID].can_ctrl);
  
  	/* acceptance mask/acceptance code (accept everything) */
 -	flexcan_write(0x0, &regs->rxgmask);
@@ -463,14 +422,9 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 -		flexcan_write(0x0, &regs->rxfgmask);
 +		priv->write(0x0, &regs->rxfgmask);
  
- 	/* clear acceptance filters */
- 	for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
--		flexcan_write(0, &regs->rximr[i]);
-+		priv->write(0, &regs->rximr[i]);
- 
  	/* On Vybrid, disable memory error detection interrupts
  	 * and freeze mode.
-@@ -1011,16 +1028,16 @@ static int flexcan_chip_start(struct net
+@@ -916,16 +931,16 @@ static int flexcan_chip_start(struct net
  		 * and Correction of Memory Errors" to write to
  		 * MECR register
  		 */
@@ -492,16 +446,14 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	}
  
  	err = flexcan_transceiver_enable(priv);
-@@ -1036,14 +1053,14 @@ static int flexcan_chip_start(struct net
+@@ -941,13 +956,13 @@ static int flexcan_chip_start(struct net
  
  	/* enable interrupts atomically */
  	disable_irq(dev->irq);
 -	flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
--	flexcan_write(priv->reg_imask1_default, &regs->imask1);
--	flexcan_write(priv->reg_imask2_default, &regs->imask2);
+-	flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 +	priv->write(priv->reg_ctrl_default, &regs->ctrl);
-+	priv->write(priv->reg_imask1_default, &regs->imask1);
-+	priv->write(priv->reg_imask2_default, &regs->imask2);
++	priv->write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
  	enable_irq(dev->irq);
  
  	/* print chip status */
@@ -511,22 +463,18 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  	return 0;
  
-@@ -1068,10 +1085,10 @@ static void flexcan_chip_stop(struct net
+@@ -972,8 +987,8 @@ static void flexcan_chip_stop(struct net
  	flexcan_chip_disable(priv);
  
  	/* Disable all interrupts */
--	flexcan_write(0, &regs->imask2);
 -	flexcan_write(0, &regs->imask1);
 -	flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
--		      &regs->ctrl);
-+	priv->write(0, &regs->imask2);
 +	priv->write(0, &regs->imask1);
 +	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
-+		    &regs->ctrl);
+ 		      &regs->ctrl);
  
  	flexcan_transceiver_disable(priv);
- 	priv->can.state = CAN_STATE_STOPPED;
-@@ -1186,26 +1203,26 @@ static int register_flexcandev(struct ne
+@@ -1089,25 +1104,25 @@ static int register_flexcandev(struct ne
  	err = flexcan_chip_disable(priv);
  	if (err)
  		goto out_disable_per;
@@ -549,16 +497,15 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
 +	priv->write(reg, &regs->mcr);
  
  	/* Currently we only support newer versions of this core
- 	 * featuring a RX hardware FIFO (although this driver doesn't
- 	 * make use of it on some cores). Older cores, found on some
- 	 * Coldfire derivates are not tested.
+ 	 * featuring a RX FIFO. Older cores found on some Coldfire
+ 	 * derivates are not yet supported.
  	 */
 -	reg = flexcan_read(&regs->mcr);
 +	reg = priv->read(&regs->mcr);
  	if (!(reg & FLEXCAN_MCR_FEN)) {
  		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
  		err = -ENODEV;
-@@ -1233,8 +1250,12 @@ static void unregister_flexcandev(struct
+@@ -1135,8 +1150,12 @@ static void unregister_flexcandev(struct
  static const struct of_device_id flexcan_of_match[] = {
  	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
  	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
@@ -571,7 +518,7 @@ Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	{ /* sentinel */ },
  };
  MODULE_DEVICE_TABLE(of, flexcan_of_match);
-@@ -1314,6 +1335,21 @@ static int flexcan_probe(struct platform
+@@ -1213,6 +1232,21 @@ static int flexcan_probe(struct platform
  	dev->flags |= IFF_ECHO;
  
  	priv = netdev_priv(dev);
diff --git a/target/linux/layerscape/patches-4.14/810-kvm-support-layerscape.patch b/target/linux/layerscape/patches-4.9/820-kvm-support-layerscape.patch
similarity index 59%
rename from target/linux/layerscape/patches-4.14/810-kvm-support-layerscape.patch
rename to target/linux/layerscape/patches-4.9/820-kvm-support-layerscape.patch
index 07bfef9cf..a652660f9 100644
--- a/target/linux/layerscape/patches-4.14/810-kvm-support-layerscape.patch
+++ b/target/linux/layerscape/patches-4.9/820-kvm-support-layerscape.patch
@@ -1,20 +1,21 @@
-From 621f2c4753b03170213e178cdafd66e78b212b3c Mon Sep 17 00:00:00 2001
-From: Biwen Li <biwen.li@nxp.com>
-Date: Tue, 30 Oct 2018 18:26:41 +0800
-Subject: [PATCH 27/40] kvm: support layerscape
-This is an integrated patch of kvm for layerscape
+From fe22151c95c02c6bb145ea6c3685941e8fb09d60 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Thu, 5 Jul 2018 17:43:16 +0800
+Subject: [PATCH 32/32] kvm: support layerscape
+
+This is an integrated patch for layerscape kvm support.
 
-Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
-Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
 ---
  arch/arm/include/asm/kvm_mmu.h   |  3 +-
+ arch/arm/kvm/mmu.c               | 56 ++++++++++++++++++++++++++++++--
  arch/arm64/include/asm/kvm_mmu.h | 14 ++++++--
- arch/powerpc/kvm/booke.c         |  5 +++
- virt/kvm/arm/mmu.c               | 56 ++++++++++++++++++++++++++++++--
- virt/kvm/arm/vgic/vgic-its.c     |  2 +-
+ virt/kvm/arm/vgic/vgic-its.c     | 24 +++++++++++---
  virt/kvm/arm/vgic/vgic-v2.c      |  3 +-
- 6 files changed, 74 insertions(+), 9 deletions(-)
+ 5 files changed, 88 insertions(+), 12 deletions(-)
 
 --- a/arch/arm/include/asm/kvm_mmu.h
 +++ b/arch/arm/include/asm/kvm_mmu.h
@@ -28,53 +29,9 @@ Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
  
---- a/arch/arm64/include/asm/kvm_mmu.h
-+++ b/arch/arm64/include/asm/kvm_mmu.h
-@@ -167,7 +167,8 @@ void stage2_unmap_vm(struct kvm *kvm);
- int kvm_alloc_stage2_pgd(struct kvm *kvm);
- void kvm_free_stage2_pgd(struct kvm *kvm);
- int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
--			  phys_addr_t pa, unsigned long size, bool writable);
-+			  phys_addr_t pa, unsigned long size, bool writable,
-+			  pgprot_t prot);
- 
- int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
- 
-@@ -270,8 +271,15 @@ static inline void __coherent_cache_gues
- 
- static inline void __kvm_flush_dcache_pte(pte_t pte)
- {
--	struct page *page = pte_page(pte);
--	kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
-+	if (pfn_valid(pte_pfn(pte))) {
-+		struct page *page = pte_page(pte);
-+		kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
-+	} else {
-+		void __iomem *va = ioremap_cache_ns(pte_pfn(pte) << PAGE_SHIFT, PAGE_SIZE);
-+
-+		kvm_flush_dcache_to_poc(va, PAGE_SIZE);
-+		iounmap(va);
-+	}
- }
- 
- static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
---- a/arch/powerpc/kvm/booke.c
-+++ b/arch/powerpc/kvm/booke.c
-@@ -305,6 +305,11 @@ void kvmppc_core_queue_fpunavail(struct
- 	kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
- }
- 
-+void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu)
-+{
-+	kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL);
-+}
-+
- void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
- {
- 	kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
---- a/virt/kvm/arm/mmu.c
-+++ b/virt/kvm/arm/mmu.c
-@@ -1027,9 +1027,11 @@ static int stage2_pmdp_test_and_clear_yo
+--- a/arch/arm/kvm/mmu.c
++++ b/arch/arm/kvm/mmu.c
+@@ -1020,9 +1020,11 @@ static int stage2_pmdp_test_and_clear_yo
   * @guest_ipa:	The IPA at which to insert the mapping
   * @pa:		The physical address of the device
   * @size:	The size of the mapping
@@ -87,7 +44,7 @@ Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
  {
  	phys_addr_t addr, end;
  	int ret = 0;
-@@ -1040,7 +1042,7 @@ int kvm_phys_addr_ioremap(struct kvm *kv
+@@ -1033,7 +1035,7 @@ int kvm_phys_addr_ioremap(struct kvm *kv
  	pfn = __phys_to_pfn(pa);
  
  	for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
@@ -96,7 +53,7 @@ Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  		if (writable)
  			pte = kvm_s2pte_mkwrite(pte);
-@@ -1064,6 +1066,30 @@ out:
+@@ -1057,6 +1059,30 @@ out:
  	return ret;
  }
  
@@ -127,26 +84,27 @@ Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
  static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap)
  {
  	kvm_pfn_t pfn = *pfnp;
-@@ -1334,6 +1360,18 @@ static int user_mem_abort(struct kvm_vcp
+@@ -1308,6 +1334,19 @@ static int user_mem_abort(struct kvm_vcp
  		hugetlb = true;
  		gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT;
  	} else {
-+		pte_t *pte;
-+		spinlock_t *ptl;
-+		pgprot_t prot;
++		if (!is_vm_hugetlb_page(vma)) {
++			pte_t *pte;
++			spinlock_t *ptl;
++			pgprot_t prot;
 +
-+		pte = get_locked_pte(current->mm, memslot->userspace_addr, &ptl);
-+		prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
-+		pte_unmap_unlock(pte, ptl);
++			pte = get_locked_pte(current->mm, memslot->userspace_addr, &ptl);
++			prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
++			pte_unmap_unlock(pte, ptl);
 +#ifdef CONFIG_ARM64
-+		if (pgprot_val(prot) == pgprot_val(PAGE_S2_NS))
-+			mem_type = PAGE_S2_NS;
++			if (pgprot_val(prot) == pgprot_val(PAGE_S2_NS))
++				mem_type = PAGE_S2_NS;
 +#endif
-+
++		}
  		/*
  		 * Pages belonging to memslots that don't have the same
  		 * alignment for userspace and IPA cannot be mapped using
-@@ -1375,6 +1413,11 @@ static int user_mem_abort(struct kvm_vcp
+@@ -1345,6 +1384,11 @@ static int user_mem_abort(struct kvm_vcp
  	if (is_error_noslot_pfn(pfn))
  		return -EFAULT;
  
@@ -158,7 +116,7 @@ Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
  	if (kvm_is_device_pfn(pfn)) {
  		mem_type = PAGE_S2_DEVICE;
  		flags |= KVM_S2PTE_FLAG_IS_IOMAP;
-@@ -1911,6 +1954,9 @@ int kvm_arch_prepare_memory_region(struc
+@@ -1882,6 +1926,9 @@ int kvm_arch_prepare_memory_region(struc
  			gpa_t gpa = mem->guest_phys_addr +
  				    (vm_start - mem->userspace_addr);
  			phys_addr_t pa;
@@ -168,14 +126,14 @@ Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
  
  			pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
  			pa += vm_start - vma->vm_start;
-@@ -1921,9 +1967,13 @@ int kvm_arch_prepare_memory_region(struc
+@@ -1891,10 +1938,13 @@ int kvm_arch_prepare_memory_region(struc
+ 				ret = -EINVAL;
  				goto out;
  			}
- 
 +			pte = get_locked_pte(current->mm, mem->userspace_addr, &ptl);
 +			prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
 +			pte_unmap_unlock(pte, ptl);
-+
+ 
  			ret = kvm_phys_addr_ioremap(kvm, gpa, pa,
  						    vm_end - vm_start,
 -						    writable);
@@ -183,20 +141,93 @@ Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
  			if (ret)
  				break;
  		}
+--- a/arch/arm64/include/asm/kvm_mmu.h
++++ b/arch/arm64/include/asm/kvm_mmu.h
+@@ -167,7 +167,8 @@ void stage2_unmap_vm(struct kvm *kvm);
+ int kvm_alloc_stage2_pgd(struct kvm *kvm);
+ void kvm_free_stage2_pgd(struct kvm *kvm);
+ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+-			  phys_addr_t pa, unsigned long size, bool writable);
++			  phys_addr_t pa, unsigned long size, bool writable,
++			  pgprot_t prot);
+ 
+ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
+ 
+@@ -274,8 +275,15 @@ static inline void __coherent_cache_gues
+ 
+ static inline void __kvm_flush_dcache_pte(pte_t pte)
+ {
+-	struct page *page = pte_page(pte);
+-	kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
++	if (pfn_valid(pte_pfn(pte))) {
++		struct page *page = pte_page(pte);
++		kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
++	} else {
++		void __iomem *va = ioremap_cache_ns(pte_pfn(pte) << PAGE_SHIFT, PAGE_SIZE);
++
++		kvm_flush_dcache_to_poc(va, PAGE_SIZE);
++		iounmap(va);
++	}
+ }
+ 
+ static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
 --- a/virt/kvm/arm/vgic/vgic-its.c
 +++ b/virt/kvm/arm/vgic/vgic-its.c
-@@ -243,7 +243,7 @@ static struct its_ite *find_ite(struct v
+@@ -176,6 +176,8 @@ static struct its_itte *find_itte(struct
+ 
  #define GIC_LPI_OFFSET 8192
  
- #define VITS_TYPER_IDBITS 16
--#define VITS_TYPER_DEVBITS 16
 +#define VITS_TYPER_DEVBITS 17
- #define VITS_DTE_MAX_DEVID_OFFSET	(BIT(14) - 1)
- #define VITS_ITE_MAX_EVENTID_OFFSET	(BIT(16) - 1)
++
+ /*
+  * Finds and returns a collection in the ITS collection table.
+  * Must be called with the its_lock mutex held.
+@@ -375,7 +377,7 @@ static unsigned long vgic_mmio_read_its_
+ 	 * To avoid memory waste in the guest, we keep the number of IDBits and
+ 	 * DevBits low - as least for the time being.
+ 	 */
+-	reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
++	reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
+ 	reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
+ 
+ 	return extract_bytes(reg, addr & 7, len);
+@@ -601,16 +603,30 @@ static int vgic_its_cmd_handle_movi(stru
+  * Check whether an ID can be stored into the corresponding guest table.
+  * For a direct table this is pretty easy, but gets a bit nasty for
+  * indirect tables. We check whether the resulting guest physical address
+- * is actually valid (covered by a memslot and guest accessbible).
++ * is actually valid (covered by a memslot and guest accessible).
+  * For this we have to read the respective first level entry.
+  */
+-static bool vgic_its_check_id(struct vgic_its *its, u64 baser, int id)
++static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id)
+ {
+ 	int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
++	u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
+ 	int index;
+-	u64 indirect_ptr;
+ 	gfn_t gfn;
+ 
++	switch (type) {
++	case GITS_BASER_TYPE_DEVICE:
++		if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
++			return false;
++		break;
++	case GITS_BASER_TYPE_COLLECTION:
++		/* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */
++		if (id >= BIT_ULL(16))
++			return false;
++		break;
++	default:
++		return false;
++	}
++
+ 	if (!(baser & GITS_BASER_INDIRECT)) {
+ 		phys_addr_t addr;
  
 --- a/virt/kvm/arm/vgic/vgic-v2.c
 +++ b/virt/kvm/arm/vgic/vgic-v2.c
-@@ -304,7 +304,8 @@ int vgic_v2_map_resources(struct kvm *kv
+@@ -290,7 +290,8 @@ int vgic_v2_map_resources(struct kvm *kv
  	if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
  		ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
  					    kvm_vgic_global_state.vcpu_base,
diff --git a/target/linux/layerscape/patches-4.9/821-add-esdhc-vsel-to-ls1043.patch b/target/linux/layerscape/patches-4.9/821-add-esdhc-vsel-to-ls1043.patch
new file mode 100644
index 000000000..c45c6b4a2
--- /dev/null
+++ b/target/linux/layerscape/patches-4.9/821-add-esdhc-vsel-to-ls1043.patch
@@ -0,0 +1,10 @@
+--- a/drivers/mmc/host/sdhci-of-esdhc.c
++++ b/drivers/mmc/host/sdhci-of-esdhc.c
+@@ -619,6 +619,7 @@ static void esdhc_reset(struct sdhci_hos
+ static const struct of_device_id scfg_device_ids[] = {
+ 	{ .compatible = "fsl,t1040-scfg", },
+ 	{ .compatible = "fsl,ls1012a-scfg", },
++	{ .compatible = "fsl,ls1043a-scfg", },
+ 	{ .compatible = "fsl,ls1046a-scfg", },
+ 	{}
+ };
diff --git a/target/linux/layerscape/patches-4.14/712-sdk-dpaa-rgmii-fixed-link.patch b/target/linux/layerscape/patches-4.9/822-rgmii-fixed-link.patch
similarity index 90%
rename from target/linux/layerscape/patches-4.14/712-sdk-dpaa-rgmii-fixed-link.patch
rename to target/linux/layerscape/patches-4.9/822-rgmii-fixed-link.patch
index d6cf803e4..593bd3e79 100644
--- a/target/linux/layerscape/patches-4.14/712-sdk-dpaa-rgmii-fixed-link.patch
+++ b/target/linux/layerscape/patches-4.9/822-rgmii-fixed-link.patch
@@ -1,12 +1,12 @@
-From b3544990f8496edda965e1ff9a14727360660676 Mon Sep 17 00:00:00 2001
+From f27ef8941ca29b2d10428754be51e8ee06bb1263 Mon Sep 17 00:00:00 2001
 From: Mathew McBride <matt@traverse.com.au>
 Date: Mon, 7 Aug 2017 10:19:48 +1000
 Subject: [PATCH] Recognize when an RGMII Link is set as fixed (in the device
  tree) and set up the MAC accordingly
 
 ---
- drivers/net/ethernet/freescale/sdk_dpaa/mac.c       |  1 +
- .../freescale/sdk_fman/Peripherals/FM/MAC/memac.c   | 13 +++++++++++++
+ drivers/net/ethernet/freescale/sdk_dpaa/mac.c                      |    1 
+ drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c |   13 ++++++++++
  2 files changed, 14 insertions(+)
 
 --- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
diff --git a/target/linux/oxnas/patches-4.14/999-libata-hacks.patch b/target/linux/oxnas/patches-4.14/999-libata-hacks.patch
index 382a16329..e490dbf7c 100644
--- a/target/linux/oxnas/patches-4.14/999-libata-hacks.patch
+++ b/target/linux/oxnas/patches-4.14/999-libata-hacks.patch
@@ -15,7 +15,7 @@
  	/* initialize internal qc */
  
  	/* XXX: Tag 0 is used for drivers with legacy EH as some
-@@ -5128,6 +5136,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
+@@ -5127,6 +5135,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
  	if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
  		return NULL;
  
@@ -25,7 +25,7 @@
  	/* libsas case */
  	if (ap->flags & ATA_FLAG_SAS_HOST) {
  		tag = ata_sas_allocate_tag(ap);
-@@ -5173,6 +5184,8 @@ void ata_qc_free(struct ata_queued_cmd *
+@@ -5172,6 +5183,8 @@ void ata_qc_free(struct ata_queued_cmd *
  		qc->tag = ATA_TAG_POISON;
  		if (ap->flags & ATA_FLAG_SAS_HOST)
  			ata_sas_free_tag(tag, ap);