rockchip: refresh rk3568 devices support

This commit is contained in:
aiamadeus 2024-08-15 23:28:12 +08:00
parent 68ec0da1d5
commit 12641b1ce1
10 changed files with 66 additions and 92 deletions

View File

@ -0,0 +1,14 @@
. /lib/functions.sh
preinit_reorder_eth() {
case $(board_name) in
lyt,t68m)
ip link set eth0 name lan1
ip link set eth1 name lan2
ip link set eth2 name lan4
ip link set eth3 name lan3
;;
esac
}
boot_hook_add preinit_main preinit_reorder_eth

View File

@ -380,16 +380,16 @@
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@0,0 {
bridge@0,0 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
rtl8125_1: pcie-eth@10,0 {
ethernet@0,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x238>;
led-data = <0x23f 0x3f 0 0>;
};
};
};
@ -400,16 +400,16 @@
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@0,0 {
bridge@0,0 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
rtl8125_2: pcie-eth@20,0 {
ethernet@0,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x238>;
led-data = <0x23f 0x3f 0 0>;
};
};
};

View File

@ -436,10 +436,6 @@
};
};
};
codec {
mic-in-differential;
};
};
};
@ -472,17 +468,6 @@
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@0,0 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_1: pcie-eth@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
};
};
};
&pcie3x2 {
@ -490,17 +475,6 @@
reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@0,0 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_2: pcie-eth@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
};
};
};
&pinctrl {
@ -551,6 +525,7 @@
};
&pwm0 {
pinctrl-names = "active";
status = "okay";
};

View File

@ -8,11 +8,6 @@
/ {
model = "HINLINK OPC-H66K Board";
compatible = "hinlink,opc-h66k", "rockchip,rk3568";
aliases {
ethernet0 = &rtl8125_1;
ethernet1 = &rtl8125_2;
};
};
&vcc3v3_pcie {

View File

@ -63,6 +63,7 @@
rgmii_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
realtek,led-data = <0x6d60>;
};
};
@ -70,6 +71,7 @@
rgmii_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
realtek,led-data = <0x6d60>;
};
};

View File

@ -12,10 +12,6 @@
mmc0 = &sdhci;
};
chosen {
stdout-path = "serial2:1500000n8";
};
gpio-leds {
compatible = "gpio-leds";
@ -108,16 +104,10 @@
cpu-supply = <&vdd_cpu>;
};
#ifdef DTS_NO_LEGACY
&display_subsystem {
status = "disabled";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
#endif
&i2c0 {
status = "okay";

View File

@ -11,6 +11,10 @@
mmc1 = &sdmmc0;
};
chosen {
stdout-path = "serial2:1500000n8";
};
pwm-leds {
compatible = "pwm-leds-multicolor";
@ -103,12 +107,29 @@
phy-supply = <&vcc3v3_pcie30x1>;
};
&display_subsystem {
status = "disabled";
};
&pcie2x1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie20_reset_h>;
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
ethernet@0,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
led-data = <0 0x3f 0x23f 0>;
};
};
};
&pcie30phy {
@ -132,6 +153,19 @@
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
status = "okay";
bridge@0,0 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
ethernet@0,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
led-data = <0 0x3f 0x23f 0>;
};
};
};
&pinctrl {

View File

@ -518,10 +518,6 @@
};
};
};
codec {
mic-in-differential;
};
};
};

View File

@ -28,7 +28,6 @@
stdout-path = "serial2:1500000n8";
};
#ifdef DTS_NO_LEGACY
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@ -39,7 +38,6 @@
};
};
};
#endif
gpio-keys {
compatible = "gpio-keys";
@ -214,7 +212,6 @@
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
label = "lan1";
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
@ -237,7 +234,6 @@
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
label = "lan2";
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
@ -255,7 +251,6 @@
status = "okay";
};
#ifdef DTS_NO_LEGACY
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@ -282,7 +277,6 @@
&hdmi_sound {
status = "okay";
};
#endif
&i2c0 {
status = "okay";
@ -555,18 +549,6 @@
reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@0,0 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
pcie-eth@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
label = "lan4";
};
};
};
&pcie3x2 {
@ -574,18 +556,6 @@
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@0,0 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
pcie-eth@20,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
label = "lan3";
};
};
};
&pinctrl {
@ -741,7 +711,6 @@
status = "okay";
};
#ifdef DTS_NO_LEGACY
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
@ -758,4 +727,3 @@
remote-endpoint = <&hdmi_in_vp0>;
};
};
#endif

View File

@ -58,7 +58,7 @@ define Device/ezpro_mrkaio-m68s-plus
SOC := rk3568
UBOOT_DEVICE_NAME := mrkaio-m68s-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script vop | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-ata-ahci-dwc kmod-drm-rockchip kmod-r8125
DEVICE_PACKAGES := kmod-ata-ahci-dwc kmod-drm-rockchip kmod-r8125-rss
endef
TARGET_DEVICES += ezpro_mrkaio-m68s-plus
@ -67,7 +67,7 @@ define Device/fastrhino_common
SOC := rk3568
UBOOT_DEVICE_NAME := r66s-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-r8125
DEVICE_PACKAGES := kmod-r8125-rss
endef
define Device/fastrhino_r66s
@ -137,7 +137,7 @@ define Device/friendlyarm_nanopi-r5c
SOC := rk3568
UBOOT_DEVICE_NAME := nanopi-r5s-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-r8125 kmod-nvme kmod-scsi-core
DEVICE_PACKAGES := kmod-r8125-rss
endef
TARGET_DEVICES += friendlyarm_nanopi-r5c
@ -147,7 +147,7 @@ define Device/friendlyarm_nanopi-r5s
SOC := rk3568
UBOOT_DEVICE_NAME := nanopi-r5s-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-r8125 kmod-nvme kmod-scsi-core
DEVICE_PACKAGES := kmod-r8125-rss
endef
TARGET_DEVICES += friendlyarm_nanopi-r5s
@ -165,7 +165,7 @@ define Device/hinlink_common
DEVICE_VENDOR := HINLINK
UBOOT_DEVICE_NAME := opc-h68k-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script vop | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-ata-ahci-dwc kmod-drm-rockchip kmod-hwmon-pwmfan kmod-mt7921e kmod-r8125 wpad-openssl
DEVICE_PACKAGES := kmod-ata-ahci-dwc kmod-drm-rockchip kmod-hwmon-pwmfan kmod-mt7921e kmod-r8125-rss wpad-openssl
endef
define Device/hinlink_opc-h66k
@ -196,7 +196,7 @@ define Device/lyt_t68m
SOC := rk3568
UBOOT_DEVICE_NAME := lyt-t68m-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script vop | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-drm-rockchip kmod-mt7921e kmod-r8125 wpad-openssl uboot-envtools
DEVICE_PACKAGES := kmod-drm-rockchip kmod-mt7921e kmod-r8125-rss wpad-openssl uboot-envtools
endef
TARGET_DEVICES += lyt_t68m
@ -226,7 +226,7 @@ define Device/radxa_e25
DEVICE_DTS := rockchip/rk3568-radxa-e25
UBOOT_DEVICE_NAME := radxa-e25-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-ata-ahci-dwc kmod-r8125
DEVICE_PACKAGES := kmod-ata-ahci-dwc kmod-r8125-rss
endef
TARGET_DEVICES += radxa_e25