kernel: bump 6.x to latest HEAD

This commit is contained in:
coolsnowwolf 2025-02-05 23:19:38 +08:00
parent e905fdb169
commit 111e93f75d
8 changed files with 30 additions and 38 deletions

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@ -1,2 +1,2 @@
LINUX_VERSION-6.1 = .127
LINUX_KERNEL_HASH-6.1.127 = 18b0d41d1a7fbad56045cde0d7fc176bfb18361d29c9f07e57109bbf21bf7876
LINUX_VERSION-6.1 = .128
LINUX_KERNEL_HASH-6.1.128 = 874d67d3181570e69ac6b33853f0448f05fc90d4cf3e4baaadc4a9cede7c50f3

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@ -1,2 +1,2 @@
LINUX_VERSION-6.12 = .11
LINUX_KERNEL_HASH-6.12.11 = 475172fdbd87a153f123a57952672e773bdb6daf5b58a417d1a5e419fcfeec49
LINUX_VERSION-6.12 = .12
LINUX_KERNEL_HASH-6.12.12 = e98942d17ef7063b3f2d6d7692bf24899e2e021cf832d19b55308ec8e8e08eff

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@ -1,2 +1,2 @@
LINUX_VERSION-6.6 = .74
LINUX_KERNEL_HASH-6.6.74 = f15e2b1a8bab0eba494b07858a5abc88d8f788e25f6fe4a572a77840bbd5494d
LINUX_VERSION-6.6 = .75
LINUX_KERNEL_HASH-6.6.75 = f7dfb1fa9716ba139d0b4c8161535816d400dea21d5943f513448429b1790290

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@ -13,7 +13,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/gpu/drm/v3d/v3d_irq.c
+++ b/drivers/gpu/drm/v3d/v3d_irq.c
@@ -177,6 +177,7 @@ v3d_hub_irq(int irq, void *arg)
@@ -181,6 +181,7 @@ v3d_hub_irq(int irq, void *arg)
"GMP",
};
const char *client = "?";
@ -21,7 +21,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
@@ -186,6 +187,7 @@ v3d_hub_irq(int irq, void *arg)
@@ -190,6 +191,7 @@ v3d_hub_irq(int irq, void *arg)
client = v3d41_axi_ids[axi_id];
}
@ -29,7 +29,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
client, axi_id, (long long)vio_addr,
((intsts & V3D_HUB_INT_MMU_WRV) ?
@@ -194,6 +196,7 @@ v3d_hub_irq(int irq, void *arg)
@@ -198,6 +200,7 @@ v3d_hub_irq(int irq, void *arg)
", pte invalid" : ""),
((intsts & V3D_HUB_INT_MMU_CAP) ?
", cap exceeded" : ""));

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@ -258,7 +258,7 @@ Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
dma_fence_signal(&fence->base);
@@ -109,6 +111,7 @@ v3d_irq(int irq, void *arg)
@@ -110,6 +112,7 @@ v3d_irq(int irq, void *arg)
if (intsts & V3D_INT_FRDONE) {
struct v3d_fence *fence =
to_v3d_fence(v3d->render_job->base.irq_fence);
@ -266,7 +266,7 @@ Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
dma_fence_signal(&fence->base);
@@ -118,6 +121,7 @@ v3d_irq(int irq, void *arg)
@@ -120,6 +123,7 @@ v3d_irq(int irq, void *arg)
if (intsts & V3D_INT_CSDDONE) {
struct v3d_fence *fence =
to_v3d_fence(v3d->csd_job->base.irq_fence);
@ -274,7 +274,7 @@ Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
trace_v3d_csd_irq(&v3d->drm, fence->seqno);
dma_fence_signal(&fence->base);
@@ -154,6 +158,7 @@ v3d_hub_irq(int irq, void *arg)
@@ -157,6 +161,7 @@ v3d_hub_irq(int irq, void *arg)
if (intsts & V3D_HUB_INT_TFUC) {
struct v3d_fence *fence =
to_v3d_fence(v3d->tfu_job->base.irq_fence);

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@ -295,7 +295,7 @@ v2: fix kernel panic with debug-fs interface to list registers
static irqreturn_t
v3d_hub_irq(int irq, void *arg);
@@ -118,7 +119,8 @@ v3d_irq(int irq, void *arg)
@@ -120,7 +121,8 @@ v3d_irq(int irq, void *arg)
status = IRQ_HANDLED;
}
@ -305,7 +305,7 @@ v2: fix kernel panic with debug-fs interface to list registers
struct v3d_fence *fence =
to_v3d_fence(v3d->csd_job->base.irq_fence);
v3d->gpu_queue_stats[V3D_CSD].last_exec_end = local_clock();
@@ -131,7 +133,7 @@ v3d_irq(int irq, void *arg)
@@ -134,7 +136,7 @@ v3d_irq(int irq, void *arg)
/* We shouldn't be triggering these if we have GMP in
* always-allowed mode.
*/
@ -314,7 +314,7 @@ v2: fix kernel panic with debug-fs interface to list registers
dev_err(v3d->drm.dev, "GMP violation\n");
/* V3D 4.2 wires the hub and core IRQs together, so if we &
@@ -205,6 +207,11 @@ v3d_hub_irq(int irq, void *arg)
@@ -209,6 +211,11 @@ v3d_hub_irq(int irq, void *arg)
status = IRQ_HANDLED;
}
@ -326,7 +326,7 @@ v2: fix kernel panic with debug-fs interface to list registers
return status;
}
@@ -219,8 +226,8 @@ v3d_irq_init(struct v3d_dev *v3d)
@@ -223,8 +230,8 @@ v3d_irq_init(struct v3d_dev *v3d)
* for us.
*/
for (core = 0; core < v3d->cores; core++)
@ -337,7 +337,7 @@ v2: fix kernel panic with debug-fs interface to list registers
irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
if (irq1 == -EPROBE_DEFER)
@@ -264,12 +271,12 @@ v3d_irq_enable(struct v3d_dev *v3d)
@@ -268,12 +275,12 @@ v3d_irq_enable(struct v3d_dev *v3d)
/* Enable our set of interrupts, masking out any others. */
for (core = 0; core < v3d->cores; core++) {
@ -354,7 +354,7 @@ v2: fix kernel panic with debug-fs interface to list registers
}
void
@@ -284,8 +291,8 @@ v3d_irq_disable(struct v3d_dev *v3d)
@@ -288,8 +295,8 @@ v3d_irq_disable(struct v3d_dev *v3d)
/* Clear any pending interrupts we might have left. */
for (core = 0; core < v3d->cores; core++)

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@ -1,20 +0,0 @@
--- a/drivers/mtd/nand/raw/internals.h
+++ b/drivers/mtd/nand/raw/internals.h
@@ -18,6 +18,7 @@
*/
#define NAND_MFR_AMD 0x01
#define NAND_MFR_ATO 0x9b
+#define NAND_MFR_DOSILICON 0xf8
#define NAND_MFR_EON 0x92
#define NAND_MFR_ESMT 0xc8
#define NAND_MFR_FUJITSU 0x04
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -178,6 +178,7 @@ struct nand_flash_dev nand_flash_ids[] =
static const struct nand_manufacturer_desc nand_manufacturer_descs[] = {
{NAND_MFR_AMD, "AMD/Spansion", &amd_nand_manuf_ops},
{NAND_MFR_ATO, "ATO"},
+ {NAND_MFR_DOSILICON, "Dosilicon"},
{NAND_MFR_EON, "Eon"},
{NAND_MFR_ESMT, "ESMT", &esmt_nand_manuf_ops},
{NAND_MFR_FUJITSU, "Fujitsu"},

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@ -0,0 +1,12 @@
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -55,6 +55,9 @@ struct nand_flash_dev nand_flash_ids[] =
{ .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
NAND_ECC_INFO(40, SZ_1K) },
+ {"TH58NYG3S0HBAI4 8G 1.8V 8-bit", /* Last ID bytes missing */
+ { .id = {0x98, 0xa3, 0x91, 0x26} },
+ SZ_4K, SZ_1K, SZ_256K, 0, 4, 256, NAND_ECC_INFO(8, SZ_512) },
{"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x91, 0x15, 0x76} },
SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) },