mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
parent
04147dcaf5
commit
0d498429b5
@ -10,7 +10,7 @@
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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@@ -0,0 +1,66 @@
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@@ -0,0 +1,71 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
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@ -53,6 +53,11 @@
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+ compatible = "ethernet-phy-id4f51.e91b",
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+ "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+
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+ motorcomm,clk-out-frequency-hz = <125000000>;
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+ motorcomm,keep-pll-enabled;
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+ motorcomm,auto-sleep-disabled;
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+
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <15000>;
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@ -10,7 +10,7 @@
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
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@@ -0,0 +1,55 @@
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@@ -0,0 +1,60 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
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@ -40,6 +40,11 @@
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+ compatible = "ethernet-phy-id0000.011a",
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+ "ethernet-phy-ieee802.3-c22";
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+ reg = <3>;
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+
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+ motorcomm,clk-out-frequency-hz = <125000000>;
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+ motorcomm,keep-pll-enabled;
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+ motorcomm,auto-sleep-disabled;
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+
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+ interrupt-parent = <&gpio2>;
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+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
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+ pinctrl-0 = <ð_phy_reset_pin>;
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@ -10,7 +10,7 @@
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
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@@ -0,0 +1,66 @@
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@@ -0,0 +1,71 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
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@ -53,6 +53,11 @@
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+ compatible = "ethernet-phy-id4f51.e91b",
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+ "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+
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+ motorcomm,clk-out-frequency-hz = <125000000>;
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+ motorcomm,keep-pll-enabled;
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+ motorcomm,auto-sleep-disabled;
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+
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <15000>;
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@ -10,7 +10,7 @@
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
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@@ -0,0 +1,55 @@
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@@ -0,0 +1,60 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
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@ -40,6 +40,11 @@
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+ compatible = "ethernet-phy-id0000.011a",
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+ "ethernet-phy-ieee802.3-c22";
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+ reg = <3>;
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+
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+ motorcomm,clk-out-frequency-hz = <125000000>;
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+ motorcomm,keep-pll-enabled;
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+ motorcomm,auto-sleep-disabled;
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+
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+ interrupt-parent = <&gpio2>;
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+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
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+ pinctrl-0 = <ð_phy_reset_pin>;
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