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rockchip: fix wan port for nanopi r2c (#11091)

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Fixes: #11074
This commit is contained in:
XiaoBinin 2023-04-08 21:28:32 +08:00 committed by GitHub
parent 04147dcaf5
commit 0d498429b5
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 24 additions and 4 deletions
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7
target/linux/rockchip/patches-5.15/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch
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@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,66 @@ @@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +/*
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd. + * Copyright (c) 2016 Xunlong Software. Co., Ltd.
@ -53,6 +53,11 @@
+ compatible = "ethernet-phy-id4f51.e91b", + compatible = "ethernet-phy-id4f51.e91b",
+ "ethernet-phy-ieee802.3-c22"; + "ethernet-phy-ieee802.3-c22";
+ reg = <0>; + reg = <0>;
+
+ motorcomm,clk-out-frequency-hz = <125000000>;
+ motorcomm,keep-pll-enabled;
+ motorcomm,auto-sleep-disabled;
+
+ pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ reset-assert-us = <15000>; + reset-assert-us = <15000>;

7
target/linux/rockchip/patches-5.15/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
View File

@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -0,0 +1,55 @@ @@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
@ -40,6 +40,11 @@
+ compatible = "ethernet-phy-id0000.011a", + compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22"; + "ethernet-phy-ieee802.3-c22";
+ reg = <3>; + reg = <3>;
+
+ motorcomm,clk-out-frequency-hz = <125000000>;
+ motorcomm,keep-pll-enabled;
+ motorcomm,auto-sleep-disabled;
+
+ interrupt-parent = <&gpio2>; + interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>; + interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-0 = <&eth_phy_reset_pin>;

7
target/linux/rockchip/patches-6.1/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch
View File

@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -0,0 +1,66 @@ @@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +/*
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd. + * Copyright (c) 2016 Xunlong Software. Co., Ltd.
@ -53,6 +53,11 @@
+ compatible = "ethernet-phy-id4f51.e91b", + compatible = "ethernet-phy-id4f51.e91b",
+ "ethernet-phy-ieee802.3-c22"; + "ethernet-phy-ieee802.3-c22";
+ reg = <0>; + reg = <0>;
+
+ motorcomm,clk-out-frequency-hz = <125000000>;
+ motorcomm,keep-pll-enabled;
+ motorcomm,auto-sleep-disabled;
+
+ pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ reset-assert-us = <15000>; + reset-assert-us = <15000>;

7
target/linux/rockchip/patches-6.1/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
View File

@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -0,0 +1,55 @@ @@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
@ -40,6 +40,11 @@
+ compatible = "ethernet-phy-id0000.011a", + compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22"; + "ethernet-phy-ieee802.3-c22";
+ reg = <3>; + reg = <3>;
+
+ motorcomm,clk-out-frequency-hz = <125000000>;
+ motorcomm,keep-pll-enabled;
+ motorcomm,auto-sleep-disabled;
+
+ interrupt-parent = <&gpio2>; + interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>; + interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-0 = <&eth_phy_reset_pin>;