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ipq807x: add support for Aquantia AQR113C
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lean
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142
target/linux/ipq807x/patches-5.10/720-net-phy-add-aqr-phys.patch
Normal file
142
target/linux/ipq807x/patches-5.10/720-net-phy-add-aqr-phys.patch
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@ -0,0 +1,142 @@
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From: Birger Koblitz <git@birger-koblitz.de>
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Date: Sun, 5 Sep 2021 15:13:10 +0200
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Subject: [PATCH] kernel: Add AQR113C and AQR813 support
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This hack adds support for the Aquantia 4th generation, 10GBit
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PHYs AQR113C and AQR813.
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Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
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--- a/drivers/net/phy/aquantia_main.c
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+++ b/drivers/net/phy/aquantia_main.c
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@@ -20,8 +20,10 @@
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#define PHY_ID_AQR105 0x03a1b4a2
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#define PHY_ID_AQR106 0x03a1b4d0
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#define PHY_ID_AQR107 0x03a1b4e0
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+#define PHY_ID_AQR113C 0x31c31c12
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#define PHY_ID_AQCS109 0x03a1b5c2
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#define PHY_ID_AQR405 0x03a1b4b0
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+#define PHY_ID_AQR813 0x31c31cb2
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#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
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@@ -330,6 +332,49 @@ static int aqr107_read_rate(struct phy_d
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return 0;
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}
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+static int aqr113c_read_status(struct phy_device *phydev)
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+{
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+ int val, ret;
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+
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+ ret = aqr_read_status(phydev);
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+ if (ret)
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+ return ret;
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+
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+ if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
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+ return 0;
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+
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+ // On AQR113C, the speed returned by aqr_read_status is wrong
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+ aqr107_read_rate(phydev);
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+
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+ val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
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+ if (val < 0)
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+ return val;
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+
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+ switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
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+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
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+ phydev->interface = PHY_INTERFACE_MODE_10GKR;
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+ break;
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+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
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+ phydev->interface = PHY_INTERFACE_MODE_10GBASER;
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+ break;
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+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
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+ phydev->interface = PHY_INTERFACE_MODE_USXGMII;
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+ break;
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+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
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+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
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+ break;
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+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
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+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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+ break;
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+ default:
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+ phydev->interface = PHY_INTERFACE_MODE_NA;
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+ break;
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+ }
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+
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+ /* Read downshifted rate from vendor register */
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+ return aqr107_read_rate(phydev);
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+}
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+
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static int aqr107_read_status(struct phy_device *phydev)
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{
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int val, ret;
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@@ -460,7 +505,7 @@ static void aqr107_chip_info(struct phy_
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build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
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prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
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- phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
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+ phydev_info(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
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fw_major, fw_minor, build_id, prov_id);
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}
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@@ -632,6 +677,24 @@ static struct phy_driver aqr_driver[] =
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.link_change_notify = aqr107_link_change_notify,
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},
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{
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+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
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+ .name = "Aquantia AQR113C",
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+ .probe = aqr107_probe,
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+ .config_init = aqr107_config_init,
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+ .config_aneg = aqr_config_aneg,
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+ .config_intr = aqr_config_intr,
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+ .handle_interrupt = aqr_handle_interrupt,
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+ .read_status = aqr113c_read_status,
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+ .get_tunable = aqr107_get_tunable,
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+ .set_tunable = aqr107_set_tunable,
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+ .suspend = aqr107_suspend,
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+ .resume = aqr107_resume,
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+ .get_sset_count = aqr107_get_sset_count,
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+ .get_strings = aqr107_get_strings,
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+ .get_stats = aqr107_get_stats,
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+ .link_change_notify = aqr107_link_change_notify,
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+},
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+{
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PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
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.name = "Aquantia AQCS109",
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.probe = aqr107_probe,
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@@ -657,6 +720,24 @@ static struct phy_driver aqr_driver[] =
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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+{
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+ PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
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+ .name = "Aquantia AQR813",
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+ .probe = aqr107_probe,
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+ .config_init = aqr107_config_init,
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+ .config_aneg = aqr_config_aneg,
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+ .config_intr = aqr_config_intr,
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+ .handle_interrupt = aqr_handle_interrupt,
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+ .read_status = aqr113c_read_status,
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+ .get_tunable = aqr107_get_tunable,
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+ .set_tunable = aqr107_set_tunable,
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+ .suspend = aqr107_suspend,
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+ .resume = aqr107_resume,
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+ .get_sset_count = aqr107_get_sset_count,
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+ .get_strings = aqr107_get_strings,
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+ .get_stats = aqr107_get_stats,
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+ .link_change_notify = aqr107_link_change_notify,
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+},
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};
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module_phy_driver(aqr_driver);
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@@ -667,8 +748,10 @@ static struct mdio_device_id __maybe_unu
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
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+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
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+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
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{ }
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};
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@ -0,0 +1,154 @@
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From 5f62951fba63a9f9cfff564209426bdea5fcc371 Mon Sep 17 00:00:00 2001
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From: Alex Marginean <alexandru.marginean@nxp.com>
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Date: Tue, 27 Aug 2019 15:16:56 +0300
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Subject: [PATCH] drivers: net: phy: aquantia: enable AQR112 and AQR412
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Adds support for AQR112 and AQR412 which is mostly based on existing code
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with the addition of code configuring the protocol on system side.
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This allows changing the system side protocol without having to deploy a
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different firmware on the PHY.
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Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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---
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drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
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1 file changed, 88 insertions(+)
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--- a/drivers/net/phy/aquantia_main.c
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+++ b/drivers/net/phy/aquantia_main.c
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@@ -20,9 +20,11 @@
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#define PHY_ID_AQR105 0x03a1b4a2
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#define PHY_ID_AQR106 0x03a1b4d0
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#define PHY_ID_AQR107 0x03a1b4e0
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+#define PHY_ID_AQR112 0x03a1b662
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#define PHY_ID_AQR113C 0x31c31c12
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#define PHY_ID_AQCS109 0x03a1b5c2
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#define PHY_ID_AQR405 0x03a1b4b0
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+#define PHY_ID_AQR412 0x03a1b712
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#define PHY_ID_AQR813 0x31c31cb2
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#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
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@@ -123,6 +125,29 @@
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
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+/* registers in MDIO_MMD_VEND1 region */
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+#define AQUANTIA_VND1_GLOBAL_SC 0x000
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+#define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb)
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+
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+/* global start rate, the protocol associated with this speed is used by default
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+ * on SI.
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+ */
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+#define AQUANTIA_VND1_GSTART_RATE 0x31a
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+#define AQUANTIA_VND1_GSTART_RATE_OFF 0
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+#define AQUANTIA_VND1_GSTART_RATE_100M 1
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+#define AQUANTIA_VND1_GSTART_RATE_1G 2
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+#define AQUANTIA_VND1_GSTART_RATE_10G 3
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+#define AQUANTIA_VND1_GSTART_RATE_2_5G 4
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+#define AQUANTIA_VND1_GSTART_RATE_5G 5
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+
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+/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
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+#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
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+#define AQUANTIA_VND1_GSYSCFG_100M 0
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+#define AQUANTIA_VND1_GSYSCFG_1G 1
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+#define AQUANTIA_VND1_GSYSCFG_2_5G 2
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+#define AQUANTIA_VND1_GSYSCFG_5G 3
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+#define AQUANTIA_VND1_GSYSCFG_10G 4
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+
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struct aqr107_hw_stat {
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const char *name;
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int reg;
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@@ -243,6 +268,51 @@ static int aqr_config_aneg(struct phy_de
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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+static struct {
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+ u16 syscfg;
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+ int cnt;
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+ u16 start_rate;
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+} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {
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+ [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
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+ AQUANTIA_VND1_GSTART_RATE_1G},
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+ [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
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+ AQUANTIA_VND1_GSTART_RATE_2_5G},
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+ [PHY_INTERFACE_MODE_XGMII] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
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+ AQUANTIA_VND1_GSTART_RATE_10G},
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+ [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
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+ AQUANTIA_VND1_GSTART_RATE_10G},
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+};
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+
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+/* Sets up protocol on system side before calling aqr_config_aneg */
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+static int aqr_config_aneg_set_prot(struct phy_device *phydev)
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+{
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+ int if_type = phydev->interface;
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+ int i;
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+
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+ if (!aquantia_syscfg[if_type].cnt)
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+ return 0;
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+
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+ /* set PHY in low power mode so we can configure protocols */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
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+ AQUANTIA_VND1_GLOBAL_SC_LP);
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+ mdelay(10);
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+
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+ /* set the default rate to enable the SI link */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
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+ aquantia_syscfg[if_type].start_rate);
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+
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+ for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1,
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+ AQUANTIA_VND1_GSYSCFG_BASE + i,
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+ aquantia_syscfg[if_type].syscfg);
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+
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+ /* wake PHY back up */
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+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
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+ mdelay(10);
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+
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+ return aqr_config_aneg(phydev);
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+}
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+
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static int aqr_config_intr(struct phy_device *phydev)
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{
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bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
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@@ -738,6 +808,30 @@ static struct phy_driver aqr_driver[] =
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.get_stats = aqr107_get_stats,
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.link_change_notify = aqr107_link_change_notify,
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},
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+{
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+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
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+ .name = "Aquantia AQR112",
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+ .probe = aqr107_probe,
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+ .config_aneg = aqr_config_aneg_set_prot,
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+ .config_intr = aqr_config_intr,
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+ .handle_interrupt = aqr_handle_interrupt,
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+ .read_status = aqr107_read_status,
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+ .get_sset_count = aqr107_get_sset_count,
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+ .get_strings = aqr107_get_strings,
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+ .get_stats = aqr107_get_stats,
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+},
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+{
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+ PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
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+ .name = "Aquantia AQR412",
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+ .probe = aqr107_probe,
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+ .config_aneg = aqr_config_aneg_set_prot,
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+ .config_intr = aqr_config_intr,
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+ .handle_interrupt = aqr_handle_interrupt,
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+ .read_status = aqr107_read_status,
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+ .get_sset_count = aqr107_get_sset_count,
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+ .get_strings = aqr107_get_strings,
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+ .get_stats = aqr107_get_stats,
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+},
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};
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module_phy_driver(aqr_driver);
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@@ -748,9 +842,11 @@ static struct mdio_device_id __maybe_unu
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
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+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
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+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
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{ }
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};
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@ -0,0 +1,34 @@
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From 5f008cb22f60da4e10375f22266c1a4e20b1252e Mon Sep 17 00:00:00 2001
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From: Alex Marginean <alexandru.marginean@nxp.com>
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Date: Fri, 20 Sep 2019 18:22:52 +0300
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Subject: [PATCH] drivers: net: phy: aquantia: fix system side protocol
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misconfiguration
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Do not set up protocols for speeds that are not supported by FW. Enabling
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||||||
|
these protocols leads to link issues on system side.
|
||||||
|
|
||||||
|
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
|
||||||
|
---
|
||||||
|
drivers/net/phy/aquantia_main.c | 8 +++++++-
|
||||||
|
1 file changed, 7 insertions(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--- a/drivers/net/phy/aquantia_main.c
|
||||||
|
+++ b/drivers/net/phy/aquantia_main.c
|
||||||
|
@@ -301,10 +301,16 @@ static int aqr_config_aneg_set_prot(stru
|
||||||
|
phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
|
||||||
|
aquantia_syscfg[if_type].start_rate);
|
||||||
|
|
||||||
|
- for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)
|
||||||
|
+ for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++) {
|
||||||
|
+ u16 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,
|
||||||
|
+ AQUANTIA_VND1_GSYSCFG_BASE + i);
|
||||||
|
+ if (!reg)
|
||||||
|
+ continue;
|
||||||
|
+
|
||||||
|
phy_write_mmd(phydev, MDIO_MMD_VEND1,
|
||||||
|
AQUANTIA_VND1_GSYSCFG_BASE + i,
|
||||||
|
aquantia_syscfg[if_type].syscfg);
|
||||||
|
+ }
|
||||||
|
|
||||||
|
/* wake PHY back up */
|
||||||
|
phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
|
||||||
@ -0,0 +1,43 @@
|
|||||||
|
From 2e677e4ae8f8330f68013163b060d0fda3a43095 Mon Sep 17 00:00:00 2001
|
||||||
|
From: "Langer, Thomas" <tlanger@maxlinear.com>
|
||||||
|
Date: Fri, 9 Jul 2021 17:36:46 +0200
|
||||||
|
Subject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support
|
||||||
|
|
||||||
|
Add a new entry for AQR113 PHY_ID
|
||||||
|
---
|
||||||
|
drivers/net/phy/aquantia_main.c | 10 ++++++++++
|
||||||
|
1 file changed, 10 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/net/phy/aquantia_main.c
|
||||||
|
+++ b/drivers/net/phy/aquantia_main.c
|
||||||
|
@@ -21,6 +21,7 @@
|
||||||
|
#define PHY_ID_AQR106 0x03a1b4d0
|
||||||
|
#define PHY_ID_AQR107 0x03a1b4e0
|
||||||
|
#define PHY_ID_AQR112 0x03a1b662
|
||||||
|
+#define PHY_ID_AQR113 0x31c31c40
|
||||||
|
#define PHY_ID_AQR113C 0x31c31c12
|
||||||
|
#define PHY_ID_AQCS109 0x03a1b5c2
|
||||||
|
#define PHY_ID_AQR405 0x03a1b4b0
|
||||||
|
@@ -827,6 +828,14 @@ static struct phy_driver aqr_driver[] =
|
||||||
|
.get_stats = aqr107_get_stats,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
|
||||||
|
+ .name = "Aquantia AQR113",
|
||||||
|
+ .config_aneg = aqr_config_aneg,
|
||||||
|
+ .config_intr = aqr_config_intr,
|
||||||
|
+ .handle_interrupt = aqr_handle_interrupt,
|
||||||
|
+ .read_status = aqr107_read_status,
|
||||||
|
+},
|
||||||
|
+{
|
||||||
|
PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
|
||||||
|
.name = "Aquantia AQR412",
|
||||||
|
.probe = aqr107_probe,
|
||||||
|
@@ -849,6 +858,7 @@ static struct mdio_device_id __maybe_unu
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
|
||||||
|
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
|
||||||
@ -0,0 +1,63 @@
|
|||||||
|
From 3b92ee7b7899b6beffb2b484c58326e36612a873 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Date: Thu, 23 Dec 2021 14:52:56 +0000
|
||||||
|
Subject: [PATCH] net: phy: aquantia: add PHY_ID for AQR112R
|
||||||
|
|
||||||
|
As advised by Ian Chang this PHY is used in Puzzle devices.
|
||||||
|
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
---
|
||||||
|
drivers/net/phy/aquantia_main.c | 10 ++++++++++
|
||||||
|
1 file changed, 10 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/net/phy/aquantia_main.c
|
||||||
|
+++ b/drivers/net/phy/aquantia_main.c
|
||||||
|
@@ -21,6 +21,8 @@
|
||||||
|
#define PHY_ID_AQR106 0x03a1b4d0
|
||||||
|
#define PHY_ID_AQR107 0x03a1b4e0
|
||||||
|
#define PHY_ID_AQR112 0x03a1b662
|
||||||
|
+#define PHY_ID_AQR112C 0x03a1b790
|
||||||
|
+#define PHY_ID_AQR112R 0x31c31d12
|
||||||
|
#define PHY_ID_AQR113 0x31c31c40
|
||||||
|
#define PHY_ID_AQR113C 0x31c31c12
|
||||||
|
#define PHY_ID_AQCS109 0x03a1b5c2
|
||||||
|
@@ -828,6 +830,30 @@ static struct phy_driver aqr_driver[] =
|
||||||
|
.get_stats = aqr107_get_stats,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C),
|
||||||
|
+ .name = "Aquantia AQR112C",
|
||||||
|
+ .probe = aqr107_probe,
|
||||||
|
+ .config_aneg = aqr_config_aneg_set_prot,
|
||||||
|
+ .config_intr = aqr_config_intr,
|
||||||
|
+ .handle_interrupt = aqr_handle_interrupt,
|
||||||
|
+ .read_status = aqr107_read_status,
|
||||||
|
+ .get_sset_count = aqr107_get_sset_count,
|
||||||
|
+ .get_strings = aqr107_get_strings,
|
||||||
|
+ .get_stats = aqr107_get_stats,
|
||||||
|
+},
|
||||||
|
+{
|
||||||
|
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R),
|
||||||
|
+ .name = "Aquantia AQR112R",
|
||||||
|
+ .probe = aqr107_probe,
|
||||||
|
+ .config_aneg = aqr_config_aneg_set_prot,
|
||||||
|
+ .config_intr = aqr_config_intr,
|
||||||
|
+ .handle_interrupt = aqr_handle_interrupt,
|
||||||
|
+ .read_status = aqr107_read_status,
|
||||||
|
+ .get_sset_count = aqr107_get_sset_count,
|
||||||
|
+ .get_strings = aqr107_get_strings,
|
||||||
|
+ .get_stats = aqr107_get_stats,
|
||||||
|
+},
|
||||||
|
+{
|
||||||
|
PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
|
||||||
|
.name = "Aquantia AQR113",
|
||||||
|
.config_aneg = aqr_config_aneg,
|
||||||
|
@@ -858,6 +884,8 @@ static struct mdio_device_id __maybe_unu
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
|
||||||
|
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
|
||||||
|
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
|
||||||
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
|
||||||
Loading…
Reference in New Issue
Block a user