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uboot-rockchip: fixes spl mode for rk3568

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Give spl more privileges so that it can be used at least.
Fixes: 8dbff7b ("uboot-rockchip: add rk3568 board support")
This commit is contained in:
AmadeusGhost 2022-12-22 23:07:40 +08:00
parent 8d54436f94
commit 034b35e9e6
8 changed files with 274 additions and 12 deletions
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42
package/boot/uboot-rockchip/patches/016-rk356x-ddr-fix-dbw-detect-bug.patch Normal file
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@ -0,0 +1,42 @@
From c9a8a3b5fb4ae210c5a5acb1538b0e961c5d1421 Mon Sep 17 00:00:00 2001
From: Tang Yun ping <typ@rock-chips.com>
Date: Wed, 23 Jun 2021 19:48:59 +0800
Subject: [PATCH] rk356x: ddr: fix dbw detect bug
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Change-Id: Ifadad00853eb0ad43a68f12335fd243e6a1bc04b
---
drivers/ram/rockchip/sdram_common.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/drivers/ram/rockchip/sdram_common.c
+++ b/drivers/ram/rockchip/sdram_common.c
@@ -299,22 +299,22 @@ int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type)
bw = cap_info->bw;
cs_cap = (1 << (row + col + bk + bw - 20));
if (bw == 2) {
- if (cs_cap <= 0x2000000) /* 256Mb */
+ if (cs_cap <= 0x20) /* 256Mb */
die_bw_0 = (col < 9) ? 2 : 1;
- else if (cs_cap <= 0x10000000) /* 2Gb */
+ else if (cs_cap <= 0x100) /* 2Gb */
die_bw_0 = (col < 10) ? 2 : 1;
- else if (cs_cap <= 0x40000000) /* 8Gb */
+ else if (cs_cap <= 0x400) /* 8Gb */
die_bw_0 = (col < 11) ? 2 : 1;
else
die_bw_0 = (col < 12) ? 2 : 1;
if (cs > 1) {
row = cap_info->cs1_row;
cs_cap = (1 << (row + col + bk + bw - 20));
- if (cs_cap <= 0x2000000) /* 256Mb */
+ if (cs_cap <= 0x20) /* 256Mb */
die_bw_0 = (col < 9) ? 2 : 1;
- else if (cs_cap <= 0x10000000) /* 2Gb */
+ else if (cs_cap <= 0x100) /* 2Gb */
die_bw_0 = (col < 10) ? 2 : 1;
- else if (cs_cap <= 0x40000000) /* 8Gb */
+ else if (cs_cap <= 0x400) /* 8Gb */
die_bw_0 = (col < 11) ? 2 : 1;
else
die_bw_0 = (col < 12) ? 2 : 1;

44
package/boot/uboot-rockchip/patches/017-gpio-rockchip-fix-building-for-spl.patch Normal file
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@ -0,0 +1,44 @@
From c7496009386dbac8f8d18a94258031f30683d7c6 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 20 Feb 2022 07:59:02 -0500
Subject: [PATCH] gpio: rockchip: fix building for spl
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
drivers/gpio/rk_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -454,6 +454,11 @@ config SPL_FIT_IMAGE_TINY
ensure this information is available to the next image
invoked).
+config SPL_ADC
+ bool "Support ADC drivers in SPL"
+ help
+ Enable ADC drivers in SPL.
+
config SPL_CACHE
bool "Support CACHE drivers"
help
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_$(SPL_)ADC) += adc/
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -118,7 +118,7 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
}
/* Simple SPL interface to GPIOs */
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ROCKCHIP_GPIO_V2)
enum {
PULL_NONE_1V8 = 0,

28
package/boot/uboot-rockchip/patches/018-clk-rockchip-rk3568-fix-reset-handler.patch Normal file
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@ -0,0 +1,28 @@
From 5011ceb0da47f7c3d54d20b45b7df884e6e92ac5 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 20 Feb 2022 07:58:38 -0500
Subject: [PATCH] clk: rockchip: rk3568: fix reset handler
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
drivers/clk/rockchip/clk_rk3568.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -14,6 +14,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3568-cru.h>
@@ -2934,6 +2935,7 @@ static int rk3568_clk_bind(struct udevice *dev)
glb_srst_fst);
priv->glb_srst_snd_value = offsetof(struct rk3568_cru,
glb_srsr_snd);
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)

144
package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch Normal file
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@ -0,0 +1,144 @@
From 79cb33b9da0c9475486ca0759341057854b25e38 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Sun, 20 Feb 2022 07:57:50 -0500
Subject: [PATCH] rockchip: handle bootrom mode in spl
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/Makefile | 6 +--
arch/arm/mach-rockchip/boot_mode.c | 4 +-
arch/arm/mach-rockchip/rk3568/rk3568.c | 54 +++++++++++++++++++++++++-
3 files changed, 59 insertions(+), 5 deletions(-)
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
-
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way,
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
-obj-y += boot_mode.o
+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void)
ret = -ENODEV;
uclass_foreach_dev(dev, uc) {
if (!strncmp(dev->name, "saradc", 6)) {
- ret = adc_channel_single_shot(dev->name, 1, &val);
+ ret = adc_channel_single_shot(dev->name, 0, &val);
break;
}
}
@@ -89,6 +89,7 @@ int setup_boot_mode(void)
boot_mode = readl(reg);
debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
/* Clear boot mode */
writel(BOOT_NORMAL, reg);
@@ -102,6 +103,7 @@ int setup_boot_mode(void)
env_set("preboot", "setenv preboot; ums mmc 0");
break;
}
+#endif
return 0;
}
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -9,19 +9,30 @@
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/boot_mode.h>
#include <asm/arch-rockchip/grf_rk3568.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
#define PMUGRF_BASE 0xfdc20000
#define GRF_BASE 0xfdc60000
+#define GRF_GPIO1B_IOMUX_H 0x0c
+#define GRF_GPIO1C_IOMUX_L 0x10
+#define GRF_GPIO1C_IOMUX_H 0x14
+#define GRF_GPIO1D_IOMUX_L 0x18
+#define GRF_GPIO1D_IOMUX_H 0x1c
+#define GRF_GPIO2A_IOMUX_L 0x20
#define GRF_GPIO1B_DS_2 0x218
#define GRF_GPIO1B_DS_3 0x21c
#define GRF_GPIO1C_DS_0 0x220
#define GRF_GPIO1C_DS_1 0x224
#define GRF_GPIO1C_DS_2 0x228
#define GRF_GPIO1C_DS_3 0x22c
-#define SGRF_BASE 0xFDD18000
+#define GRF_GPIO1D_DS_0 0x230
+#define GRF_GPIO1D_DS_1 0x234
+#define GRF_GPIO1D_DS_2 0x238
+#define SGRF_BASE 0xfdd18000
+#define SGRF_SOC_CON3 0x0c
#define SGRF_SOC_CON4 0x10
#define EMMC_HPROT_SECURE_CTRL 0x03
#define SDMMC0_HPROT_SECURE_CTRL 0x01
@@ -133,6 +144,24 @@ int arch_cpu_init(void)
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
+
+ /* emmc, sfc, and sdmmc iomux */
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H);
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L);
+ writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H);
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L);
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_H);
+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO2A_IOMUX_L);
+
+ /* set the fspi d0~3 cs0 to level 2 */
+ writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3);
+ writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0);
+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1);
+ writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2);
+
+ /* Set the fspi to secure */
+ writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3);
+
#endif
return 0;
}
@@ -164,3 +193,26 @@ int ft_system_setup(void *blob, struct bd_info *bd)
return 0;
};
#endif
+
+#ifdef CONFIG_SPL_BUILD
+
+void __weak led_setup(void)
+{
+}
+
+void spl_board_init(void)
+{
+ led_setup();
+
+#if defined(SPL_DM_REGULATOR)
+ /*
+ * Turning the eMMC and SPI back on (if disabled via the Qseven
+ * BIOS_ENABLE) signal is done through a always-on regulator).
+ */
+ if (regulators_enable_boot_on(false))
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+ setup_boot_mode();
+}
+#endif

7
package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch
View File

@ -305,7 +305,7 @@
+};
--- /dev/null
+++ b/configs/mrkaio-m68s-rk3568_defconfig
@@ -0,0 +1,98 @@
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
@ -338,8 +338,10 @@
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ADC=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
@ -387,7 +389,6 @@
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y

7
package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch
View File

@ -314,7 +314,7 @@
+};
--- /dev/null
+++ b/configs/opc-h68k-rk3568_defconfig
@@ -0,0 +1,98 @@
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
@ -347,8 +347,10 @@
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ADC=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
@ -396,7 +398,6 @@
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y

7
package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch
View File

@ -39,7 +39,7 @@
+#include "rk3568-evb.dts"
--- /dev/null
+++ b/configs/r66s-rk3568_defconfig
@@ -0,0 +1,98 @@
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
@ -72,8 +72,10 @@
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ADC=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
@ -121,7 +123,6 @@
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y

7
package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch
View File

@ -52,7 +52,7 @@
+};
--- /dev/null
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -0,0 +1,98 @@
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
@ -85,8 +85,10 @@
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ADC=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
@ -134,7 +136,6 @@
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y