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Merge branch 'master' of https://github.com/coolsnowwolf/lede
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lean
commit
00522a1d86
@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
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PKG_NAME:=openssl
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PKG_BASE:=1.1.1
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PKG_BUGFIX:=p
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PKG_BUGFIX:=q
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PKG_VERSION:=$(PKG_BASE)$(PKG_BUGFIX)
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PKG_RELEASE:=$(AUTORELEASE)
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PKG_USE_MIPS16:=0
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@ -27,7 +27,7 @@ PKG_SOURCE_URL:= \
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ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/ \
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ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/old/$(PKG_BASE)/
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PKG_HASH:=bf61b62aaa66c7c7639942a94de4c9ae8280c08f17d4eac2e44644d9fc8ace6f
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PKG_HASH:=d7939ce614029cdff0b6c20f0e2e5703158a489a72b2507b8bd51bf8c8fd10ca
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PKG_LICENSE:=OpenSSL
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PKG_LICENSE_FILES:=LICENSE
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@ -71,7 +71,7 @@ config WOLFSSL_ASM_CAPABLE
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choice
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prompt "Hardware Acceleration"
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default WOLFSSL_HAS_CPU_CRYPTO if WOLFSSL_ASM_CAPABLE && !x86_64
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default WOLFSSL_HAS_CPU_CRYPTO if WOLFSSL_ASM_CAPABLE
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default WOLFSSL_HAS_NO_HW
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config WOLFSSL_HAS_NO_HW
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@ -83,7 +83,6 @@ choice
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help
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This will use Intel AESNI insturctions or armv8 Crypto Extensions.
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Either of them should easily outperform hardware crypto in WolfSSL.
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Beware that for Intel, the CPU has to support SSE4 instructions.
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config WOLFSSL_HAS_AFALG
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bool "AF_ALG"
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@ -100,9 +99,5 @@ choice
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bool "/dev/crypto - full"
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select WOLFSSL_HAS_DEVCRYPTO
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endchoice
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if x86_64 && WOLFSSL_HAS_CPU_CRYPTO
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comment "WARNING: make sure your CPU supports SSE4 instructions"
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comment "WolfSSL may crash with an invalid opcode exception"
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endif
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endif
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@ -0,0 +1,44 @@
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From 9ba77300f9f5dea9f53aed00bf6c33d10b7b2fce Mon Sep 17 00:00:00 2001
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From: Sean Parkinson <sean@wolfssl.com>
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Date: Thu, 7 Jul 2022 09:30:48 +1000
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Subject: [PATCH] AESNI: fix configure to use minimal compiler flags
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diff --git a/configure.ac b/configure.ac
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index df97ac75c..6abb0c744 100644
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--- a/configure.ac
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+++ b/configure.ac
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@@ -2142,21 +2142,19 @@ then
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if test "$ENABLED_AESNI" = "yes" || test "$ENABLED_INTELASM" = "yes"
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then
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AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_AESNI"
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- if test "$GCC" = "yes"
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+ if test "$CC" != "icc"
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then
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- # clang needs these flags
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- if test "$CC" = "clang"
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- then
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- AM_CFLAGS="$AM_CFLAGS -maes -mpclmul"
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- else
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- # GCC needs these flags, icc doesn't
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- # opt levels greater than 2 may cause problems on systems w/o
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- # aesni
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- if test "$CC" != "icc"
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- then
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- AM_CFLAGS="$AM_CFLAGS -maes -msse4 -mpclmul"
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- fi
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- fi
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+ case $host_os in
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+ mingw*)
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+ # Windows uses intrinsics for GCM which uses SSE4 instructions.
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+ # MSVC has own build files.
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+ AM_CFLAGS="$AM_CFLAGS -maes -msse4 -mpclmul"
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+ ;;
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+ *)
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+ # Intrinsics used in AES_set_decrypt_key (TODO: rework)
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+ AM_CFLAGS="$AM_CFLAGS -maes"
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+ ;;
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+ esac
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fi
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AS_IF([test "x$ENABLED_AESGCM" != "xno"],[AM_CCASFLAGS="$AM_CCASFLAGS -DHAVE_AESGCM"])
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fi
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@ -1,29 +0,0 @@
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -171,6 +171,7 @@ void __init ralink_clk_init(void)
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u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
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u32 pll, prediv, fbdiv;
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u32 xtal_clk, cpu_clk, bus_clk;
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+ u32 target_fbdiv, target_pll;
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const static u32 prediv_tbl[] = {0, 1, 2, 2};
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syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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@@ -198,6 +199,18 @@ void __init ralink_clk_init(void)
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pll = rt_memc_r32(MEMC_REG_CPU_PLL);
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fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
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prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
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+ /* When using the PLL, this code will overclock the CPU */
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+#define MT7621A_TARGET_CLOCK_HZ 1100000000
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+ target_fbdiv = (MT7621A_TARGET_CLOCK_HZ * ffiv) / ffrac;
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+ target_fbdiv = target_fbdiv << prediv_tbl[prediv];
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+ target_fbdiv = (target_fbdiv / xtal_clk) - 1;
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+ target_pll = pll & ~(CPU_PLL_FBDIV_MASK << CPU_PLL_FBDIV_SHIFT);
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+ target_pll = target_pll | (target_fbdiv << CPU_PLL_FBDIV_SHIFT);
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+ pr_info("CPU Overclock PLL: 0x%x\n", target_pll);
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+ rt_memc_w32(target_pll, MEMC_REG_CPU_PLL);
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+ pll = rt_memc_r32(MEMC_REG_CPU_PLL);
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+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
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+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
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cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
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break;
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default:
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@ -5,12 +5,13 @@
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get_device_irq() {
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local device="$1"
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local line
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local seconds
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local seconds="0"
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# wait up to 10 seconds for the irq/device to appear
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for seconds in $(seq 0 9); do
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while [ "${seconds}" -le 10 ]; do
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line=$(grep -m 1 "${device}\$" /proc/interrupts) && break
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sleep 1
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seconds="$(( seconds + 2 ))"
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sleep 2
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done
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echo ${line} | sed 's/:.*//'
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}
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@ -122,7 +122,7 @@ GCC_CONFIGURE:= \
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--disable-decimal-float \
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--with-diagnostics-color=auto-if-env \
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--enable-__cxa_atexit \
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--disable-libstdcxx-dual-abi \
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--enable-libstdcxx-dual-abi \
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--with-default-libstdcxx-abi=new
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ifneq ($(CONFIG_mips)$(CONFIG_mipsel),)
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GCC_CONFIGURE += --with-mips-plt
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