Merge branch 'master' of https://github.com/coolsnowwolf/lede

package/libs/openssl/Makefile

@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 
 PKG_NAME:=openssl
 PKG_BASE:=1.1.1
-PKG_BUGFIX:=p
+PKG_BUGFIX:=q
 PKG_VERSION:=$(PKG_BASE)$(PKG_BUGFIX)
 PKG_RELEASE:=$(AUTORELEASE)
 PKG_USE_MIPS16:=0
@@ -27,7 +27,7 @@ PKG_SOURCE_URL:= \
 	ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/ \
 	ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/old/$(PKG_BASE)/
 
-PKG_HASH:=bf61b62aaa66c7c7639942a94de4c9ae8280c08f17d4eac2e44644d9fc8ace6f
+PKG_HASH:=d7939ce614029cdff0b6c20f0e2e5703158a489a72b2507b8bd51bf8c8fd10ca
 
 PKG_LICENSE:=OpenSSL
 PKG_LICENSE_FILES:=LICENSE

package/libs/wolfssl/Config.in

@@ -71,7 +71,7 @@ config WOLFSSL_ASM_CAPABLE
 
 choice
 	prompt "Hardware Acceleration"
-	default WOLFSSL_HAS_CPU_CRYPTO if WOLFSSL_ASM_CAPABLE && !x86_64
+	default WOLFSSL_HAS_CPU_CRYPTO if WOLFSSL_ASM_CAPABLE
 	default WOLFSSL_HAS_NO_HW
 
 	config WOLFSSL_HAS_NO_HW
@@ -83,7 +83,6 @@ choice
 		help
 		This will use Intel AESNI insturctions or armv8 Crypto Extensions.
 		Either of them should easily outperform hardware crypto in WolfSSL.
-		Beware that for Intel, the CPU has to support SSE4 instructions.
 
 	config WOLFSSL_HAS_AFALG
 		bool "AF_ALG"
@@ -100,9 +99,5 @@ choice
 		bool "/dev/crypto - full"
 		select WOLFSSL_HAS_DEVCRYPTO
 endchoice
-if x86_64 && WOLFSSL_HAS_CPU_CRYPTO
-	comment "WARNING: make sure your CPU supports SSE4 instructions"
-	comment "WolfSSL may crash with an invalid opcode exception"
-endif
 
 endif

package/libs/wolfssl/patches/300-AESNI-fix-configure-to-use-minimal-compiler-flags.patch

@@ -0,0 +1,44 @@
+From 9ba77300f9f5dea9f53aed00bf6c33d10b7b2fce Mon Sep 17 00:00:00 2001
+From: Sean Parkinson <sean@wolfssl.com>
+Date: Thu, 7 Jul 2022 09:30:48 +1000
+Subject: [PATCH] AESNI: fix configure to use minimal compiler flags
+
+
+diff --git a/configure.ac b/configure.ac
+index df97ac75c..6abb0c744 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -2142,21 +2142,19 @@ then
+     if test "$ENABLED_AESNI" = "yes" || test "$ENABLED_INTELASM" = "yes"
+     then
+         AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_AESNI"
+-        if test "$GCC" = "yes"
++        if test "$CC" != "icc"
+         then
+-            # clang needs these flags
+-            if test "$CC" = "clang"
+-            then
+-                AM_CFLAGS="$AM_CFLAGS -maes -mpclmul"
+-            else
+-                # GCC needs these flags, icc doesn't
+-                # opt levels greater than 2 may cause problems on systems w/o
+-                # aesni
+-                if test "$CC" != "icc"
+-                then
+-                    AM_CFLAGS="$AM_CFLAGS -maes -msse4 -mpclmul"
+-                fi
+-            fi
++            case $host_os in
++            mingw*)
++                # Windows uses intrinsics for GCM which uses SSE4 instructions.
++                # MSVC has own build files.
++                AM_CFLAGS="$AM_CFLAGS -maes -msse4 -mpclmul"
++                ;;
++            *)
++                # Intrinsics used in AES_set_decrypt_key (TODO: rework)
++                AM_CFLAGS="$AM_CFLAGS -maes"
++                ;;
++            esac
+         fi
+         AS_IF([test "x$ENABLED_AESGCM" != "xno"],[AM_CCASFLAGS="$AM_CCASFLAGS -DHAVE_AESGCM"])
+     fi

target/linux/ramips/patches-5.4/991-mt7621-improve_cpu_clock.patch

@@ -1,29 +0,0 @@
---- a/arch/mips/ralink/mt7621.c
-+++ b/arch/mips/ralink/mt7621.c
-@@ -171,6 +171,7 @@ void __init ralink_clk_init(void)
- 	u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
- 	u32 pll, prediv, fbdiv;
- 	u32 xtal_clk, cpu_clk, bus_clk;
-+	u32 target_fbdiv, target_pll;
- 	const static u32 prediv_tbl[] = {0, 1, 2, 2};
- 
- 	syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
-@@ -198,6 +199,18 @@ void __init ralink_clk_init(void)
- 		pll = rt_memc_r32(MEMC_REG_CPU_PLL);
- 		fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
- 		prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
-+		/* When using the PLL, this code will overclock the CPU */
-+#define MT7621A_TARGET_CLOCK_HZ		1100000000
-+		target_fbdiv = (MT7621A_TARGET_CLOCK_HZ * ffiv) / ffrac;
-+		target_fbdiv = target_fbdiv << prediv_tbl[prediv];
-+		target_fbdiv = (target_fbdiv / xtal_clk) - 1;
-+		target_pll = pll & ~(CPU_PLL_FBDIV_MASK << CPU_PLL_FBDIV_SHIFT);
-+		target_pll = target_pll | (target_fbdiv << CPU_PLL_FBDIV_SHIFT);
-+		pr_info("CPU Overclock PLL: 0x%x\n", target_pll);
-+		rt_memc_w32(target_pll, MEMC_REG_CPU_PLL);
-+		pll = rt_memc_r32(MEMC_REG_CPU_PLL);
-+		fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
-+		prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
- 		cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
- 		break;
- 	default:

target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity

@@ -5,12 +5,13 @@
 get_device_irq() {
 	local device="$1"
 	local line
-	local seconds
+	local seconds="0"
 
 	# wait up to 10 seconds for the irq/device to appear
-	for seconds in $(seq 0 9); do
+	while [ "${seconds}" -le 10 ]; do
 		line=$(grep -m 1 "${device}\$" /proc/interrupts) && break
-		sleep 1
+		seconds="$(( seconds + 2 ))"
+		sleep 2
 	done
 	echo ${line} | sed 's/:.*//'
 }

toolchain/gcc/common.mk

@@ -122,7 +122,7 @@ GCC_CONFIGURE:= \
 		--disable-decimal-float \
 		--with-diagnostics-color=auto-if-env \
 		--enable-__cxa_atexit \
-		--disable-libstdcxx-dual-abi \
+		--enable-libstdcxx-dual-abi \
 		--with-default-libstdcxx-abi=new
 ifneq ($(CONFIG_mips)$(CONFIG_mipsel),)
   GCC_CONFIGURE += --with-mips-plt