diff --git a/target/linux/ramips/patches-5.4/991-mt7621-improve_cpu_clock.patch b/target/linux/ramips/patches-5.4/991-mt7621-improve_cpu_clock.patch
new file mode 100644
index 000000000..6444b8241
--- /dev/null
+++ b/target/linux/ramips/patches-5.4/991-mt7621-improve_cpu_clock.patch
@@ -0,0 +1,29 @@
+--- a/arch/mips/ralink/mt7621.c
++++ b/arch/mips/ralink/mt7621.c
+@@ -171,6 +171,7 @@ void __init ralink_clk_init(void)
+ 	u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
+ 	u32 pll, prediv, fbdiv;
+ 	u32 xtal_clk, cpu_clk, bus_clk;
++	u32 target_fbdiv, target_pll;
+ 	const static u32 prediv_tbl[] = {0, 1, 2, 2};
+ 
+ 	syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
+@@ -198,6 +199,18 @@ void __init ralink_clk_init(void)
+ 		pll = rt_memc_r32(MEMC_REG_CPU_PLL);
+ 		fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
+ 		prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
++		/* When using the PLL, this code will overclock the CPU */
++#define MT7621A_TARGET_CLOCK_HZ		1100000000
++		target_fbdiv = (MT7621A_TARGET_CLOCK_HZ * ffiv) / ffrac;
++		target_fbdiv = target_fbdiv << prediv_tbl[prediv];
++		target_fbdiv = (target_fbdiv / xtal_clk) - 1;
++		target_pll = pll & ~(CPU_PLL_FBDIV_MASK << CPU_PLL_FBDIV_SHIFT);
++		target_pll = target_pll | (target_fbdiv << CPU_PLL_FBDIV_SHIFT);
++		pr_info("CPU Overclock PLL: 0x%x\n", target_pll);
++		rt_memc_w32(target_pll, MEMC_REG_CPU_PLL);
++		pll = rt_memc_r32(MEMC_REG_CPU_PLL);
++		fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
++		prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
+ 		cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
+ 		break;
+ 	default: